aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorAyaz Abdulla <aabdulla@nvidia.com>2007-07-15 06:50:53 -0400
committerJeff Garzik <jeff@garzik.org>2007-07-16 18:29:17 -0400
commitd215d8a269f397d303c3d5f7c74e98592e8284f1 (patch)
treec20bc36384c71d86f32be55a9ddb4979caa9ab7a /drivers
parent14a67f3c6ca319edd011db4edad63dd686426ae2 (diff)
forcedeth bug fix: vitesse phy
This patch contains errata fixes for the vitesse phy. Signed-off-by: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/forcedeth.c88
1 files changed, 88 insertions, 0 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 998afb927d44..f66c521d429d 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -550,6 +550,7 @@ union ring_type {
550/* PHY defines */ 550/* PHY defines */
551#define PHY_OUI_MARVELL 0x5043 551#define PHY_OUI_MARVELL 0x5043
552#define PHY_OUI_CICADA 0x03f1 552#define PHY_OUI_CICADA 0x03f1
553#define PHY_OUI_VITESSE 0x01c1
553#define PHYID1_OUI_MASK 0x03ff 554#define PHYID1_OUI_MASK 0x03ff
554#define PHYID1_OUI_SHFT 6 555#define PHYID1_OUI_SHFT 6
555#define PHYID2_OUI_MASK 0xfc00 556#define PHYID2_OUI_MASK 0xfc00
@@ -563,6 +564,23 @@ union ring_type {
563#define PHY_CICADA_INIT4 0x0200 564#define PHY_CICADA_INIT4 0x0200
564#define PHY_CICADA_INIT5 0x0004 565#define PHY_CICADA_INIT5 0x0004
565#define PHY_CICADA_INIT6 0x02000 566#define PHY_CICADA_INIT6 0x02000
567#define PHY_VITESSE_INIT_REG1 0x1f
568#define PHY_VITESSE_INIT_REG2 0x10
569#define PHY_VITESSE_INIT_REG3 0x11
570#define PHY_VITESSE_INIT_REG4 0x12
571#define PHY_VITESSE_INIT_MSK1 0xc
572#define PHY_VITESSE_INIT_MSK2 0x0180
573#define PHY_VITESSE_INIT1 0x52b5
574#define PHY_VITESSE_INIT2 0xaf8a
575#define PHY_VITESSE_INIT3 0x8
576#define PHY_VITESSE_INIT4 0x8f8a
577#define PHY_VITESSE_INIT5 0xaf86
578#define PHY_VITESSE_INIT6 0x8f86
579#define PHY_VITESSE_INIT7 0xaf82
580#define PHY_VITESSE_INIT8 0x0100
581#define PHY_VITESSE_INIT9 0x8f82
582#define PHY_VITESSE_INIT10 0x0
583
566#define PHY_GIGABIT 0x0100 584#define PHY_GIGABIT 0x0100
567 585
568#define PHY_TIMEOUT 0x1 586#define PHY_TIMEOUT 0x1
@@ -1162,6 +1180,76 @@ static int phy_init(struct net_device *dev)
1162 return PHY_ERROR; 1180 return PHY_ERROR;
1163 } 1181 }
1164 } 1182 }
1183 if (np->phy_oui == PHY_OUI_VITESSE) {
1184 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1185 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1186 return PHY_ERROR;
1187 }
1188 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1189 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1190 return PHY_ERROR;
1191 }
1192 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1193 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1194 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1195 return PHY_ERROR;
1196 }
1197 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1198 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1199 phy_reserved |= PHY_VITESSE_INIT3;
1200 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1201 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1202 return PHY_ERROR;
1203 }
1204 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1205 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1206 return PHY_ERROR;
1207 }
1208 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1209 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1210 return PHY_ERROR;
1211 }
1212 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1213 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1214 phy_reserved |= PHY_VITESSE_INIT3;
1215 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1216 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1217 return PHY_ERROR;
1218 }
1219 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1220 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1221 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1222 return PHY_ERROR;
1223 }
1224 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1225 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1226 return PHY_ERROR;
1227 }
1228 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1229 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1230 return PHY_ERROR;
1231 }
1232 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1233 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1234 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1235 return PHY_ERROR;
1236 }
1237 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1238 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1239 phy_reserved |= PHY_VITESSE_INIT8;
1240 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1241 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1242 return PHY_ERROR;
1243 }
1244 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1245 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1246 return PHY_ERROR;
1247 }
1248 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1249 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1250 return PHY_ERROR;
1251 }
1252 }
1165 /* some phys clear out pause advertisment on reset, set it back */ 1253 /* some phys clear out pause advertisment on reset, set it back */
1166 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); 1254 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1167 1255