diff options
author | Jiri Slaby <jirislaby@gmail.com> | 2007-10-19 02:40:31 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-19 14:53:42 -0400 |
commit | 5159f40742508e03aed4273a9b3ef06f4e71929f (patch) | |
tree | baedc0b1ea5187294bc6d4622d254fb448aec0d5 /drivers | |
parent | b7b5a1282c37e1acf6c10391664ef9d6ad58e933 (diff) |
amba-pl011, rename BIT macro
amba-pl011, rename BIT macro
Signed-off-by: Jiri Slaby <jirislaby@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/serial/amba-pl011.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c index 72229df9dc11..40604a092921 100644 --- a/drivers/serial/amba-pl011.c +++ b/drivers/serial/amba-pl011.c | |||
@@ -263,15 +263,15 @@ static unsigned int pl01x_get_mctrl(struct uart_port *port) | |||
263 | unsigned int result = 0; | 263 | unsigned int result = 0; |
264 | unsigned int status = readw(uap->port.membase + UART01x_FR); | 264 | unsigned int status = readw(uap->port.membase + UART01x_FR); |
265 | 265 | ||
266 | #define BIT(uartbit, tiocmbit) \ | 266 | #define TIOCMBIT(uartbit, tiocmbit) \ |
267 | if (status & uartbit) \ | 267 | if (status & uartbit) \ |
268 | result |= tiocmbit | 268 | result |= tiocmbit |
269 | 269 | ||
270 | BIT(UART01x_FR_DCD, TIOCM_CAR); | 270 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
271 | BIT(UART01x_FR_DSR, TIOCM_DSR); | 271 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); |
272 | BIT(UART01x_FR_CTS, TIOCM_CTS); | 272 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); |
273 | BIT(UART011_FR_RI, TIOCM_RNG); | 273 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); |
274 | #undef BIT | 274 | #undef TIOCMBIT |
275 | return result; | 275 | return result; |
276 | } | 276 | } |
277 | 277 | ||
@@ -282,18 +282,18 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |||
282 | 282 | ||
283 | cr = readw(uap->port.membase + UART011_CR); | 283 | cr = readw(uap->port.membase + UART011_CR); |
284 | 284 | ||
285 | #define BIT(tiocmbit, uartbit) \ | 285 | #define TIOCMBIT(tiocmbit, uartbit) \ |
286 | if (mctrl & tiocmbit) \ | 286 | if (mctrl & tiocmbit) \ |
287 | cr |= uartbit; \ | 287 | cr |= uartbit; \ |
288 | else \ | 288 | else \ |
289 | cr &= ~uartbit | 289 | cr &= ~uartbit |
290 | 290 | ||
291 | BIT(TIOCM_RTS, UART011_CR_RTS); | 291 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
292 | BIT(TIOCM_DTR, UART011_CR_DTR); | 292 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); |
293 | BIT(TIOCM_OUT1, UART011_CR_OUT1); | 293 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); |
294 | BIT(TIOCM_OUT2, UART011_CR_OUT2); | 294 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); |
295 | BIT(TIOCM_LOOP, UART011_CR_LBE); | 295 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); |
296 | #undef BIT | 296 | #undef TIOCMBIT |
297 | 297 | ||
298 | writew(cr, uap->port.membase + UART011_CR); | 298 | writew(cr, uap->port.membase + UART011_CR); |
299 | } | 299 | } |