diff options
author | Finn Thain <fthain@telegraphics.com.au> | 2009-11-03 08:40:23 -0500 |
---|---|---|
committer | Geert Uytterhoeven <geert@linux-m68k.org> | 2010-02-27 12:28:37 -0500 |
commit | 1f7b5fff505232521a7a770a639b63cd17636549 (patch) | |
tree | d1550de0c66883a050bc46ec2ba70608e9cc9a02 /drivers | |
parent | 2724daf439d9f4e9f25c9fb8de8602ba61758478 (diff) |
pmac-zilog: cleanup
Whitespace cleanups and comment typo fix.
Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/serial/pmac_zilog.c | 85 | ||||
-rw-r--r-- | drivers/serial/pmac_zilog.h | 20 |
2 files changed, 51 insertions, 54 deletions
diff --git a/drivers/serial/pmac_zilog.c b/drivers/serial/pmac_zilog.c index 3e2ae4807ae2..1c8afd98e14e 100644 --- a/drivers/serial/pmac_zilog.c +++ b/drivers/serial/pmac_zilog.c | |||
@@ -153,8 +153,8 @@ static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) | |||
153 | write_zsreg(uap, R10, regs[R10]); | 153 | write_zsreg(uap, R10, regs[R10]); |
154 | 154 | ||
155 | /* Set TX/RX controls sans the enable bits. */ | 155 | /* Set TX/RX controls sans the enable bits. */ |
156 | write_zsreg(uap, R3, regs[R3] & ~RxENABLE); | 156 | write_zsreg(uap, R3, regs[R3] & ~RxENABLE); |
157 | write_zsreg(uap, R5, regs[R5] & ~TxENABLE); | 157 | write_zsreg(uap, R5, regs[R5] & ~TxENABLE); |
158 | 158 | ||
159 | /* now set R7 "prime" on ESCC */ | 159 | /* now set R7 "prime" on ESCC */ |
160 | write_zsreg(uap, R15, regs[R15] | EN85C30); | 160 | write_zsreg(uap, R15, regs[R15] | EN85C30); |
@@ -205,7 +205,7 @@ static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) | |||
205 | */ | 205 | */ |
206 | static void pmz_maybe_update_regs(struct uart_pmac_port *uap) | 206 | static void pmz_maybe_update_regs(struct uart_pmac_port *uap) |
207 | { | 207 | { |
208 | if (!ZS_REGS_HELD(uap)) { | 208 | if (!ZS_REGS_HELD(uap)) { |
209 | if (ZS_TX_ACTIVE(uap)) { | 209 | if (ZS_TX_ACTIVE(uap)) { |
210 | uap->flags |= PMACZILOG_FLAG_REGS_HELD; | 210 | uap->flags |= PMACZILOG_FLAG_REGS_HELD; |
211 | } else { | 211 | } else { |
@@ -281,7 +281,7 @@ static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap) | |||
281 | spin_lock(&uap->port.lock); | 281 | spin_lock(&uap->port.lock); |
282 | if (swallow) | 282 | if (swallow) |
283 | goto next_char; | 283 | goto next_char; |
284 | } | 284 | } |
285 | #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ | 285 | #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ |
286 | 286 | ||
287 | /* A real serial line, record the character and status. */ | 287 | /* A real serial line, record the character and status. */ |
@@ -317,7 +317,7 @@ static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap) | |||
317 | 317 | ||
318 | if (uap->port.ignore_status_mask == 0xff || | 318 | if (uap->port.ignore_status_mask == 0xff || |
319 | (r1 & uap->port.ignore_status_mask) == 0) { | 319 | (r1 & uap->port.ignore_status_mask) == 0) { |
320 | tty_insert_flip_char(tty, ch, flag); | 320 | tty_insert_flip_char(tty, ch, flag); |
321 | } | 321 | } |
322 | if (r1 & Rx_OVR) | 322 | if (r1 & Rx_OVR) |
323 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | 323 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); |
@@ -470,47 +470,47 @@ static irqreturn_t pmz_interrupt(int irq, void *dev_id) | |||
470 | 470 | ||
471 | uap_a = pmz_get_port_A(uap); | 471 | uap_a = pmz_get_port_A(uap); |
472 | uap_b = uap_a->mate; | 472 | uap_b = uap_a->mate; |
473 | 473 | ||
474 | spin_lock(&uap_a->port.lock); | 474 | spin_lock(&uap_a->port.lock); |
475 | r3 = read_zsreg(uap_a, R3); | 475 | r3 = read_zsreg(uap_a, R3); |
476 | 476 | ||
477 | #ifdef DEBUG_HARD | 477 | #ifdef DEBUG_HARD |
478 | pmz_debug("irq, r3: %x\n", r3); | 478 | pmz_debug("irq, r3: %x\n", r3); |
479 | #endif | 479 | #endif |
480 | /* Channel A */ | 480 | /* Channel A */ |
481 | tty = NULL; | 481 | tty = NULL; |
482 | if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { | 482 | if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { |
483 | write_zsreg(uap_a, R0, RES_H_IUS); | 483 | write_zsreg(uap_a, R0, RES_H_IUS); |
484 | zssync(uap_a); | 484 | zssync(uap_a); |
485 | if (r3 & CHAEXT) | 485 | if (r3 & CHAEXT) |
486 | pmz_status_handle(uap_a); | 486 | pmz_status_handle(uap_a); |
487 | if (r3 & CHARxIP) | 487 | if (r3 & CHARxIP) |
488 | tty = pmz_receive_chars(uap_a); | 488 | tty = pmz_receive_chars(uap_a); |
489 | if (r3 & CHATxIP) | 489 | if (r3 & CHATxIP) |
490 | pmz_transmit_chars(uap_a); | 490 | pmz_transmit_chars(uap_a); |
491 | rc = IRQ_HANDLED; | 491 | rc = IRQ_HANDLED; |
492 | } | 492 | } |
493 | spin_unlock(&uap_a->port.lock); | 493 | spin_unlock(&uap_a->port.lock); |
494 | if (tty != NULL) | 494 | if (tty != NULL) |
495 | tty_flip_buffer_push(tty); | 495 | tty_flip_buffer_push(tty); |
496 | 496 | ||
497 | if (uap_b->node == NULL) | 497 | if (uap_b->node == NULL) |
498 | goto out; | 498 | goto out; |
499 | 499 | ||
500 | spin_lock(&uap_b->port.lock); | 500 | spin_lock(&uap_b->port.lock); |
501 | tty = NULL; | 501 | tty = NULL; |
502 | if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { | 502 | if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { |
503 | write_zsreg(uap_b, R0, RES_H_IUS); | 503 | write_zsreg(uap_b, R0, RES_H_IUS); |
504 | zssync(uap_b); | 504 | zssync(uap_b); |
505 | if (r3 & CHBEXT) | 505 | if (r3 & CHBEXT) |
506 | pmz_status_handle(uap_b); | 506 | pmz_status_handle(uap_b); |
507 | if (r3 & CHBRxIP) | 507 | if (r3 & CHBRxIP) |
508 | tty = pmz_receive_chars(uap_b); | 508 | tty = pmz_receive_chars(uap_b); |
509 | if (r3 & CHBTxIP) | 509 | if (r3 & CHBTxIP) |
510 | pmz_transmit_chars(uap_b); | 510 | pmz_transmit_chars(uap_b); |
511 | rc = IRQ_HANDLED; | 511 | rc = IRQ_HANDLED; |
512 | } | 512 | } |
513 | spin_unlock(&uap_b->port.lock); | 513 | spin_unlock(&uap_b->port.lock); |
514 | if (tty != NULL) | 514 | if (tty != NULL) |
515 | tty_flip_buffer_push(tty); | 515 | tty_flip_buffer_push(tty); |
516 | 516 | ||
@@ -718,7 +718,7 @@ static void pmz_enable_ms(struct uart_port *port) | |||
718 | 718 | ||
719 | if (ZS_IS_ASLEEP(uap)) | 719 | if (ZS_IS_ASLEEP(uap)) |
720 | return; | 720 | return; |
721 | /* NOTE: Not subject to 'transmitter active' rule. */ | 721 | /* NOTE: Not subject to 'transmitter active' rule. */ |
722 | write_zsreg(uap, R15, uap->curregs[R15]); | 722 | write_zsreg(uap, R15, uap->curregs[R15]); |
723 | } | 723 | } |
724 | } | 724 | } |
@@ -748,7 +748,7 @@ static void pmz_break_ctl(struct uart_port *port, int break_state) | |||
748 | if (new_reg != uap->curregs[R5]) { | 748 | if (new_reg != uap->curregs[R5]) { |
749 | uap->curregs[R5] = new_reg; | 749 | uap->curregs[R5] = new_reg; |
750 | 750 | ||
751 | /* NOTE: Not subject to 'transmitter active' rule. */ | 751 | /* NOTE: Not subject to 'transmitter active' rule. */ |
752 | if (ZS_IS_ASLEEP(uap)) | 752 | if (ZS_IS_ASLEEP(uap)) |
753 | return; | 753 | return; |
754 | write_zsreg(uap, R5, uap->curregs[R5]); | 754 | write_zsreg(uap, R5, uap->curregs[R5]); |
@@ -908,7 +908,6 @@ static int __pmz_startup(struct uart_pmac_port *uap) | |||
908 | /* Remember status for DCD/CTS changes */ | 908 | /* Remember status for DCD/CTS changes */ |
909 | uap->prev_status = read_zsreg(uap, R0); | 909 | uap->prev_status = read_zsreg(uap, R0); |
910 | 910 | ||
911 | |||
912 | return pwr_delay; | 911 | return pwr_delay; |
913 | } | 912 | } |
914 | 913 | ||
@@ -983,7 +982,7 @@ static int pmz_startup(struct uart_port *port) | |||
983 | if (!ZS_IS_EXTCLK(uap)) | 982 | if (!ZS_IS_EXTCLK(uap)) |
984 | uap->curregs[R1] |= EXT_INT_ENAB; | 983 | uap->curregs[R1] |= EXT_INT_ENAB; |
985 | write_zsreg(uap, R1, uap->curregs[R1]); | 984 | write_zsreg(uap, R1, uap->curregs[R1]); |
986 | spin_unlock_irqrestore(&port->lock, flags); | 985 | spin_unlock_irqrestore(&port->lock, flags); |
987 | 986 | ||
988 | pmz_debug("pmz: startup() done.\n"); | 987 | pmz_debug("pmz: startup() done.\n"); |
989 | 988 | ||
@@ -1003,7 +1002,7 @@ static void pmz_shutdown(struct uart_port *port) | |||
1003 | mutex_lock(&pmz_irq_mutex); | 1002 | mutex_lock(&pmz_irq_mutex); |
1004 | 1003 | ||
1005 | /* Release interrupt handler */ | 1004 | /* Release interrupt handler */ |
1006 | free_irq(uap->port.irq, uap); | 1005 | free_irq(uap->port.irq, uap); |
1007 | 1006 | ||
1008 | spin_lock_irqsave(&port->lock, flags); | 1007 | spin_lock_irqsave(&port->lock, flags); |
1009 | 1008 | ||
@@ -1051,7 +1050,6 @@ static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, | |||
1051 | { | 1050 | { |
1052 | int brg; | 1051 | int brg; |
1053 | 1052 | ||
1054 | |||
1055 | /* Switch to external clocking for IrDA high clock rates. That | 1053 | /* Switch to external clocking for IrDA high clock rates. That |
1056 | * code could be re-used for Midi interfaces with different | 1054 | * code could be re-used for Midi interfaces with different |
1057 | * multipliers | 1055 | * multipliers |
@@ -1223,12 +1221,12 @@ static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) | |||
1223 | uap->curregs[R5] |= DTR; | 1221 | uap->curregs[R5] |= DTR; |
1224 | write_zsreg(uap, R5, uap->curregs[R5]); | 1222 | write_zsreg(uap, R5, uap->curregs[R5]); |
1225 | zssync(uap); | 1223 | zssync(uap); |
1226 | mdelay(1); | 1224 | mdelay(1); |
1227 | 1225 | ||
1228 | /* Switch SCC to 19200 */ | 1226 | /* Switch SCC to 19200 */ |
1229 | pmz_convert_to_zs(uap, CS8, 0, 19200); | 1227 | pmz_convert_to_zs(uap, CS8, 0, 19200); |
1230 | pmz_load_zsregs(uap, uap->curregs); | 1228 | pmz_load_zsregs(uap, uap->curregs); |
1231 | mdelay(1); | 1229 | mdelay(1); |
1232 | 1230 | ||
1233 | /* Write get_version command byte */ | 1231 | /* Write get_version command byte */ |
1234 | write_zsdata(uap, 1); | 1232 | write_zsdata(uap, 1); |
@@ -1463,7 +1461,7 @@ static int __init pmz_init_port(struct uart_pmac_port *uap) | |||
1463 | return -ENODEV; | 1461 | return -ENODEV; |
1464 | uap->port.mapbase = r_ports.start; | 1462 | uap->port.mapbase = r_ports.start; |
1465 | uap->port.membase = ioremap(uap->port.mapbase, 0x1000); | 1463 | uap->port.membase = ioremap(uap->port.mapbase, 0x1000); |
1466 | 1464 | ||
1467 | uap->control_reg = uap->port.membase; | 1465 | uap->control_reg = uap->port.membase; |
1468 | uap->data_reg = uap->control_reg + 0x10; | 1466 | uap->data_reg = uap->control_reg + 0x10; |
1469 | 1467 | ||
@@ -1590,7 +1588,7 @@ static void pmz_dispose_port(struct uart_pmac_port *uap) | |||
1590 | } | 1588 | } |
1591 | 1589 | ||
1592 | /* | 1590 | /* |
1593 | * Called upon match with an escc node in the devive-tree. | 1591 | * Called upon match with an escc node in the device-tree. |
1594 | */ | 1592 | */ |
1595 | static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) | 1593 | static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) |
1596 | { | 1594 | { |
@@ -1812,7 +1810,7 @@ static int __init pmz_probe(void) | |||
1812 | pmz_ports[count].node = node_a; | 1810 | pmz_ports[count].node = node_a; |
1813 | pmz_ports[count+1].node = node_b; | 1811 | pmz_ports[count+1].node = node_b; |
1814 | pmz_ports[count].port.line = count; | 1812 | pmz_ports[count].port.line = count; |
1815 | pmz_ports[count+1].port.line = count+1; | 1813 | pmz_ports[count+1].port.line = count+1; |
1816 | 1814 | ||
1817 | /* | 1815 | /* |
1818 | * Setup the ports for real | 1816 | * Setup the ports for real |
@@ -1899,23 +1897,22 @@ err_out: | |||
1899 | static struct of_device_id pmz_match[] = | 1897 | static struct of_device_id pmz_match[] = |
1900 | { | 1898 | { |
1901 | { | 1899 | { |
1902 | .name = "ch-a", | 1900 | .name = "ch-a", |
1903 | }, | 1901 | }, |
1904 | { | 1902 | { |
1905 | .name = "ch-b", | 1903 | .name = "ch-b", |
1906 | }, | 1904 | }, |
1907 | {}, | 1905 | {}, |
1908 | }; | 1906 | }; |
1909 | MODULE_DEVICE_TABLE (of, pmz_match); | 1907 | MODULE_DEVICE_TABLE (of, pmz_match); |
1910 | 1908 | ||
1911 | static struct macio_driver pmz_driver = | 1909 | static struct macio_driver pmz_driver = { |
1912 | { | ||
1913 | .name = "pmac_zilog", | 1910 | .name = "pmac_zilog", |
1914 | .match_table = pmz_match, | 1911 | .match_table = pmz_match, |
1915 | .probe = pmz_attach, | 1912 | .probe = pmz_attach, |
1916 | .remove = pmz_detach, | 1913 | .remove = pmz_detach, |
1917 | .suspend = pmz_suspend, | 1914 | .suspend = pmz_suspend, |
1918 | .resume = pmz_resume, | 1915 | .resume = pmz_resume, |
1919 | }; | 1916 | }; |
1920 | 1917 | ||
1921 | static int __init init_pmz(void) | 1918 | static int __init init_pmz(void) |
@@ -1952,7 +1949,7 @@ static int __init init_pmz(void) | |||
1952 | pmz_dispose_port(&pmz_ports[i]); | 1949 | pmz_dispose_port(&pmz_ports[i]); |
1953 | return rc; | 1950 | return rc; |
1954 | } | 1951 | } |
1955 | 1952 | ||
1956 | /* | 1953 | /* |
1957 | * Then we register the macio driver itself | 1954 | * Then we register the macio driver itself |
1958 | */ | 1955 | */ |
@@ -2034,7 +2031,7 @@ static int __init pmz_console_setup(struct console *co, char *options) | |||
2034 | if (of_machine_is_compatible("RackMac1,1") | 2031 | if (of_machine_is_compatible("RackMac1,1") |
2035 | || of_machine_is_compatible("RackMac1,2") | 2032 | || of_machine_is_compatible("RackMac1,2") |
2036 | || of_machine_is_compatible("MacRISC4")) | 2033 | || of_machine_is_compatible("MacRISC4")) |
2037 | baud = 57600; | 2034 | baud = 57600; |
2038 | 2035 | ||
2039 | /* | 2036 | /* |
2040 | * Check whether an invalid uart number has been specified, and | 2037 | * Check whether an invalid uart number has been specified, and |
diff --git a/drivers/serial/pmac_zilog.h b/drivers/serial/pmac_zilog.h index f6e77f12acd5..f18c426324a4 100644 --- a/drivers/serial/pmac_zilog.h +++ b/drivers/serial/pmac_zilog.h | |||
@@ -1,7 +1,7 @@ | |||
1 | #ifndef __PMAC_ZILOG_H__ | 1 | #ifndef __PMAC_ZILOG_H__ |
2 | #define __PMAC_ZILOG_H__ | 2 | #define __PMAC_ZILOG_H__ |
3 | 3 | ||
4 | #define pmz_debug(fmt,arg...) dev_dbg(&uap->dev->ofdev.dev, fmt, ## arg) | 4 | #define pmz_debug(fmt, arg...) dev_dbg(&uap->dev->ofdev.dev, fmt, ## arg) |
5 | 5 | ||
6 | /* | 6 | /* |
7 | * At most 2 ESCCs with 2 ports each | 7 | * At most 2 ESCCs with 2 ports each |
@@ -113,7 +113,7 @@ static inline void zssync(struct uart_pmac_port *port) | |||
113 | #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) | 113 | #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) |
114 | #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) | 114 | #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) |
115 | 115 | ||
116 | #define ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */ | 116 | #define ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */ |
117 | 117 | ||
118 | /* The Zilog register set */ | 118 | /* The Zilog register set */ |
119 | 119 | ||
@@ -171,7 +171,7 @@ static inline void zssync(struct uart_pmac_port *port) | |||
171 | 171 | ||
172 | /* Write Register 3 */ | 172 | /* Write Register 3 */ |
173 | 173 | ||
174 | #define RxENABLE 0x1 /* Rx Enable */ | 174 | #define RxENABLE 0x1 /* Rx Enable */ |
175 | #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ | 175 | #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ |
176 | #define ADD_SM 0x4 /* Address Search Mode (SDLC) */ | 176 | #define ADD_SM 0x4 /* Address Search Mode (SDLC) */ |
177 | #define RxCRC_ENAB 0x8 /* Rx CRC Enable */ | 177 | #define RxCRC_ENAB 0x8 /* Rx CRC Enable */ |
@@ -185,7 +185,7 @@ static inline void zssync(struct uart_pmac_port *port) | |||
185 | 185 | ||
186 | /* Write Register 4 */ | 186 | /* Write Register 4 */ |
187 | 187 | ||
188 | #define PAR_ENAB 0x1 /* Parity Enable */ | 188 | #define PAR_ENAB 0x1 /* Parity Enable */ |
189 | #define PAR_EVEN 0x2 /* Parity Even/Odd* */ | 189 | #define PAR_EVEN 0x2 /* Parity Even/Odd* */ |
190 | 190 | ||
191 | #define SYNC_ENAB 0 /* Sync Modes Enable */ | 191 | #define SYNC_ENAB 0 /* Sync Modes Enable */ |
@@ -210,7 +210,7 @@ static inline void zssync(struct uart_pmac_port *port) | |||
210 | #define TxCRC_ENAB 0x1 /* Tx CRC Enable */ | 210 | #define TxCRC_ENAB 0x1 /* Tx CRC Enable */ |
211 | #define RTS 0x2 /* RTS */ | 211 | #define RTS 0x2 /* RTS */ |
212 | #define SDLC_CRC 0x4 /* SDLC/CRC-16 */ | 212 | #define SDLC_CRC 0x4 /* SDLC/CRC-16 */ |
213 | #define TxENABLE 0x8 /* Tx Enable */ | 213 | #define TxENABLE 0x8 /* Tx Enable */ |
214 | #define SND_BRK 0x10 /* Send Break */ | 214 | #define SND_BRK 0x10 /* Send Break */ |
215 | #define Tx5 0x0 /* Tx 5 bits (or less)/character */ | 215 | #define Tx5 0x0 /* Tx 5 bits (or less)/character */ |
216 | #define Tx7 0x20 /* Tx 7 bits/character */ | 216 | #define Tx7 0x20 /* Tx 7 bits/character */ |
@@ -372,11 +372,11 @@ static inline void zssync(struct uart_pmac_port *port) | |||
372 | #define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE) | 372 | #define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE) |
373 | #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS) | 373 | #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS) |
374 | #define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA) | 374 | #define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA) |
375 | #define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM) | 375 | #define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM) |
376 | #define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA) | 376 | #define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA) |
377 | #define ZS_IS_ASLEEP(UP) ((UP)->flags & PMACZILOG_FLAG_IS_ASLEEP) | 377 | #define ZS_IS_ASLEEP(UP) ((UP)->flags & PMACZILOG_FLAG_IS_ASLEEP) |
378 | #define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN) | 378 | #define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN) |
379 | #define ZS_IS_IRQ_ON(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRQ_ON) | 379 | #define ZS_IS_IRQ_ON(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRQ_ON) |
380 | #define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK) | 380 | #define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK) |
381 | 381 | ||
382 | #endif /* __PMAC_ZILOG_H__ */ | 382 | #endif /* __PMAC_ZILOG_H__ */ |