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authorLinus Torvalds <torvalds@linux-foundation.org>2009-08-19 13:38:36 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-08-19 13:38:36 -0400
commitcad2c8fd9b3afceced08838c87c520e6da417a65 (patch)
tree8da6ce24a55e59bb1b81c75c9835626558f7bbf7 /drivers
parent4aa2d56b2149e70a0b944b4f21e4aed33d9ab94e (diff)
parent5ef5f72febfea420ce58f670bad83830a5e5e3de (diff)
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/kms: teardown crtc correctly when fb is destroyed. drm/kms/radeon: cleanup combios TV table like DDX. drm/radeon/kms: memset the allocated framebuffer before using it. drm/radeon/kms: although LVDS might be possible on crtc 1 don't do it. drm/radeon/kms: implement bo busy check + current domain drm/radeon/kms: cut down indirects in register accesses. drm/radeon/kms: Fix up vertical blank interrupt support. drm/radeon/kms: add rv530 R300_SU_REG_DEST + reloc for ZPASS_ADDR drm/edid: fixup detailed timings like the X server. drm/radeon/kms: Add specific rs690 authorized register table
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/drm_crtc.c40
-rw-r--r--drivers/gpu/drm/drm_edid.c72
-rw-r--r--drivers/gpu/drm/radeon/r100.c86
-rw-r--r--drivers/gpu/drm/radeon/r300.c38
-rw-r--r--drivers/gpu/drm/radeon/r500_reg.h16
-rw-r--r--drivers/gpu/drm/radeon/radeon.h54
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h26
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c48
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c13
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c22
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c54
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c33
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c19
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h11
-rw-r--r--drivers/gpu/drm/radeon/rs600.c82
-rw-r--r--drivers/gpu/drm/radeon/rs690.c65
-rw-r--r--drivers/gpu/drm/radeon/rv515.c19
20 files changed, 455 insertions, 253 deletions
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 33be210d6723..2f631c75f704 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -258,31 +258,6 @@ void *drm_mode_object_find(struct drm_device *dev, uint32_t id, uint32_t type)
258EXPORT_SYMBOL(drm_mode_object_find); 258EXPORT_SYMBOL(drm_mode_object_find);
259 259
260/** 260/**
261 * drm_crtc_from_fb - find the CRTC structure associated with an fb
262 * @dev: DRM device
263 * @fb: framebuffer in question
264 *
265 * LOCKING:
266 * Caller must hold mode_config lock.
267 *
268 * Find CRTC in the mode_config structure that matches @fb.
269 *
270 * RETURNS:
271 * Pointer to the CRTC or NULL if it wasn't found.
272 */
273struct drm_crtc *drm_crtc_from_fb(struct drm_device *dev,
274 struct drm_framebuffer *fb)
275{
276 struct drm_crtc *crtc;
277
278 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
279 if (crtc->fb == fb)
280 return crtc;
281 }
282 return NULL;
283}
284
285/**
286 * drm_framebuffer_init - initialize a framebuffer 261 * drm_framebuffer_init - initialize a framebuffer
287 * @dev: DRM device 262 * @dev: DRM device
288 * 263 *
@@ -328,11 +303,20 @@ void drm_framebuffer_cleanup(struct drm_framebuffer *fb)
328{ 303{
329 struct drm_device *dev = fb->dev; 304 struct drm_device *dev = fb->dev;
330 struct drm_crtc *crtc; 305 struct drm_crtc *crtc;
306 struct drm_mode_set set;
307 int ret;
331 308
332 /* remove from any CRTC */ 309 /* remove from any CRTC */
333 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 310 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
334 if (crtc->fb == fb) 311 if (crtc->fb == fb) {
335 crtc->fb = NULL; 312 /* should turn off the crtc */
313 memset(&set, 0, sizeof(struct drm_mode_set));
314 set.crtc = crtc;
315 set.fb = NULL;
316 ret = crtc->funcs->set_config(&set);
317 if (ret)
318 DRM_ERROR("failed to reset crtc %p when fb was deleted\n", crtc);
319 }
336 } 320 }
337 321
338 drm_mode_object_put(dev, &fb->base); 322 drm_mode_object_put(dev, &fb->base);
@@ -1511,7 +1495,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data,
1511 set.mode = mode; 1495 set.mode = mode;
1512 set.connectors = connector_set; 1496 set.connectors = connector_set;
1513 set.num_connectors = crtc_req->count_connectors; 1497 set.num_connectors = crtc_req->count_connectors;
1514 set.fb =fb; 1498 set.fb = fb;
1515 ret = crtc->funcs->set_config(&set); 1499 ret = crtc->funcs->set_config(&set);
1516 1500
1517out: 1501out:
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 80cc6d06d61b..7f2728bbc16c 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -502,12 +502,40 @@ static int add_detailed_info(struct drm_connector *connector,
502 struct detailed_non_pixel *data = &timing->data.other_data; 502 struct detailed_non_pixel *data = &timing->data.other_data;
503 struct drm_display_mode *newmode; 503 struct drm_display_mode *newmode;
504 504
505 /* EDID up to and including 1.2 may put monitor info here */ 505 /* X server check is version 1.1 or higher */
506 if (edid->version == 1 && edid->revision < 3) 506 if (edid->version == 1 && edid->revision >= 1 &&
507 continue; 507 !timing->pixel_clock) {
508 508 /* Other timing or info */
509 /* Detailed mode timing */ 509 switch (data->type) {
510 if (timing->pixel_clock) { 510 case EDID_DETAIL_MONITOR_SERIAL:
511 break;
512 case EDID_DETAIL_MONITOR_STRING:
513 break;
514 case EDID_DETAIL_MONITOR_RANGE:
515 /* Get monitor range data */
516 break;
517 case EDID_DETAIL_MONITOR_NAME:
518 break;
519 case EDID_DETAIL_MONITOR_CPDATA:
520 break;
521 case EDID_DETAIL_STD_MODES:
522 /* Five modes per detailed section */
523 for (j = 0; j < 5; i++) {
524 struct std_timing *std;
525 struct drm_display_mode *newmode;
526
527 std = &data->data.timings[j];
528 newmode = drm_mode_std(dev, std);
529 if (newmode) {
530 drm_mode_probed_add(connector, newmode);
531 modes++;
532 }
533 }
534 break;
535 default:
536 break;
537 }
538 } else {
511 newmode = drm_mode_detailed(dev, edid, timing, quirks); 539 newmode = drm_mode_detailed(dev, edid, timing, quirks);
512 if (!newmode) 540 if (!newmode)
513 continue; 541 continue;
@@ -518,38 +546,6 @@ static int add_detailed_info(struct drm_connector *connector,
518 drm_mode_probed_add(connector, newmode); 546 drm_mode_probed_add(connector, newmode);
519 547
520 modes++; 548 modes++;
521 continue;
522 }
523
524 /* Other timing or info */
525 switch (data->type) {
526 case EDID_DETAIL_MONITOR_SERIAL:
527 break;
528 case EDID_DETAIL_MONITOR_STRING:
529 break;
530 case EDID_DETAIL_MONITOR_RANGE:
531 /* Get monitor range data */
532 break;
533 case EDID_DETAIL_MONITOR_NAME:
534 break;
535 case EDID_DETAIL_MONITOR_CPDATA:
536 break;
537 case EDID_DETAIL_STD_MODES:
538 /* Five modes per detailed section */
539 for (j = 0; j < 5; i++) {
540 struct std_timing *std;
541 struct drm_display_mode *newmode;
542
543 std = &data->data.timings[j];
544 newmode = drm_mode_std(dev, std);
545 if (newmode) {
546 drm_mode_probed_add(connector, newmode);
547 modes++;
548 }
549 }
550 break;
551 default:
552 break;
553 } 549 }
554 } 550 }
555 551
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index f1ba8ff41130..90ff8e0ac04e 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -254,6 +254,72 @@ void r100_mc_fini(struct radeon_device *rdev)
254 254
255 255
256/* 256/*
257 * Interrupts
258 */
259int r100_irq_set(struct radeon_device *rdev)
260{
261 uint32_t tmp = 0;
262
263 if (rdev->irq.sw_int) {
264 tmp |= RADEON_SW_INT_ENABLE;
265 }
266 if (rdev->irq.crtc_vblank_int[0]) {
267 tmp |= RADEON_CRTC_VBLANK_MASK;
268 }
269 if (rdev->irq.crtc_vblank_int[1]) {
270 tmp |= RADEON_CRTC2_VBLANK_MASK;
271 }
272 WREG32(RADEON_GEN_INT_CNTL, tmp);
273 return 0;
274}
275
276static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
277{
278 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
279 uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
280 RADEON_CRTC2_VBLANK_STAT;
281
282 if (irqs) {
283 WREG32(RADEON_GEN_INT_STATUS, irqs);
284 }
285 return irqs & irq_mask;
286}
287
288int r100_irq_process(struct radeon_device *rdev)
289{
290 uint32_t status;
291
292 status = r100_irq_ack(rdev);
293 if (!status) {
294 return IRQ_NONE;
295 }
296 while (status) {
297 /* SW interrupt */
298 if (status & RADEON_SW_INT_TEST) {
299 radeon_fence_process(rdev);
300 }
301 /* Vertical blank interrupts */
302 if (status & RADEON_CRTC_VBLANK_STAT) {
303 drm_handle_vblank(rdev->ddev, 0);
304 }
305 if (status & RADEON_CRTC2_VBLANK_STAT) {
306 drm_handle_vblank(rdev->ddev, 1);
307 }
308 status = r100_irq_ack(rdev);
309 }
310 return IRQ_HANDLED;
311}
312
313u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
314{
315 if (crtc == 0)
316 return RREG32(RADEON_CRTC_CRNT_FRAME);
317 else
318 return RREG32(RADEON_CRTC2_CRNT_FRAME);
319}
320
321
322/*
257 * Fence emission 323 * Fence emission
258 */ 324 */
259void r100_fence_ring_emit(struct radeon_device *rdev, 325void r100_fence_ring_emit(struct radeon_device *rdev,
@@ -1556,26 +1622,6 @@ void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1556 r100_pll_errata_after_data(rdev); 1622 r100_pll_errata_after_data(rdev);
1557} 1623}
1558 1624
1559uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1560{
1561 if (reg < 0x10000)
1562 return readl(((void __iomem *)rdev->rmmio) + reg);
1563 else {
1564 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1565 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1566 }
1567}
1568
1569void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1570{
1571 if (reg < 0x10000)
1572 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1573 else {
1574 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1575 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1576 }
1577}
1578
1579int r100_init(struct radeon_device *rdev) 1625int r100_init(struct radeon_device *rdev)
1580{ 1626{
1581 return 0; 1627 return 0;
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 9c8d41534a5d..c47579dcafa1 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -83,8 +83,8 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
83 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 83 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
84 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 84 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
85 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 85 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
86 mb();
87 } 86 }
87 mb();
88} 88}
89 89
90int rv370_pcie_gart_enable(struct radeon_device *rdev) 90int rv370_pcie_gart_enable(struct radeon_device *rdev)
@@ -593,27 +593,6 @@ void r300_vram_info(struct radeon_device *rdev)
593 593
594 594
595/* 595/*
596 * Indirect registers accessor
597 */
598uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
599{
600 uint32_t r;
601
602 WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff));
603 (void)RREG32(RADEON_PCIE_INDEX);
604 r = RREG32(RADEON_PCIE_DATA);
605 return r;
606}
607
608void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
609{
610 WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff));
611 (void)RREG32(RADEON_PCIE_INDEX);
612 WREG32(RADEON_PCIE_DATA, (v));
613 (void)RREG32(RADEON_PCIE_DATA);
614}
615
616/*
617 * PCIE Lanes 596 * PCIE Lanes
618 */ 597 */
619 598
@@ -1403,6 +1382,21 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1403 tmp = (ib_chunk->kdata[idx] >> 22) & 0xF; 1382 tmp = (ib_chunk->kdata[idx] >> 22) & 0xF;
1404 track->textures[i].txdepth = tmp; 1383 track->textures[i].txdepth = tmp;
1405 break; 1384 break;
1385 case R300_ZB_ZPASS_ADDR:
1386 r = r100_cs_packet_next_reloc(p, &reloc);
1387 if (r) {
1388 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1389 idx, reg);
1390 r100_cs_dump_packet(p, pkt);
1391 return r;
1392 }
1393 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1394 break;
1395 case 0x4be8:
1396 /* valid register only on RV530 */
1397 if (p->rdev->family == CHIP_RV530)
1398 break;
1399 /* fallthrough do not move */
1406 default: 1400 default:
1407 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1401 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1408 reg, idx); 1402 reg, idx);
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index 036691b38cb7..e1d5e0331e19 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -350,6 +350,7 @@
350#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 350#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
351#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 351#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
352#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c 352#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
353#define AVIVO_D1CRTC_FRAME_COUNT 0x60a4
353#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 354#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
354 355
355/* master controls */ 356/* master controls */
@@ -438,14 +439,15 @@
438# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 439# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4
439# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff 440# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
440 441
441#define R500_DxMODE_INT_MASK 0x6540
442#define R500_D1MODE_INT_MASK (1<<0)
443#define R500_D2MODE_INT_MASK (1<<8)
444
445#define AVIVO_D1MODE_DATA_FORMAT 0x6528 442#define AVIVO_D1MODE_DATA_FORMAT 0x6528
446# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) 443# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
447#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C 444#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
445#define AVIVO_D1MODE_VBLANK_STATUS 0x6534
446# define AVIVO_VBLANK_ACK (1 << 4)
448#define AVIVO_D1MODE_VLINE_START_END 0x6538 447#define AVIVO_D1MODE_VLINE_START_END 0x6538
448#define AVIVO_DxMODE_INT_MASK 0x6540
449# define AVIVO_D1MODE_INT_MASK (1 << 0)
450# define AVIVO_D2MODE_INT_MASK (1 << 8)
449#define AVIVO_D1MODE_VIEWPORT_START 0x6580 451#define AVIVO_D1MODE_VIEWPORT_START 0x6580
450#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 452#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
451#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 453#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
@@ -475,6 +477,7 @@
475#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 477#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
476#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 478#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
477#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c 479#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
480#define AVIVO_D2CRTC_FRAME_COUNT 0x68a4
478#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 481#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
479 482
480#define AVIVO_D2GRPH_ENABLE 0x6900 483#define AVIVO_D2GRPH_ENABLE 0x6900
@@ -497,6 +500,7 @@
497#define AVIVO_D2CUR_SIZE 0x6c10 500#define AVIVO_D2CUR_SIZE 0x6c10
498#define AVIVO_D2CUR_POSITION 0x6c14 501#define AVIVO_D2CUR_POSITION 0x6c14
499 502
503#define AVIVO_D2MODE_VBLANK_STATUS 0x6d34
500#define AVIVO_D2MODE_VLINE_START_END 0x6d38 504#define AVIVO_D2MODE_VLINE_START_END 0x6d38
501#define AVIVO_D2MODE_VIEWPORT_START 0x6d80 505#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
502#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 506#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
@@ -748,4 +752,8 @@
748# define AVIVO_I2C_EN (1 << 0) 752# define AVIVO_I2C_EN (1 << 0)
749# define AVIVO_I2C_RESET (1 << 8) 753# define AVIVO_I2C_RESET (1 << 8)
750 754
755#define AVIVO_DISP_INTERRUPT_STATUS 0x7edc
756# define AVIVO_D1_VBLANK_INTERRUPT (1 << 4)
757# define AVIVO_D2_VBLANK_INTERRUPT (1 << 5)
758
751#endif 759#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b1d945b8ed6c..79ad98264e33 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -242,6 +242,7 @@ int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
242 uint64_t *gpu_addr); 242 uint64_t *gpu_addr);
243void radeon_object_unpin(struct radeon_object *robj); 243void radeon_object_unpin(struct radeon_object *robj);
244int radeon_object_wait(struct radeon_object *robj); 244int radeon_object_wait(struct radeon_object *robj);
245int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
245int radeon_object_evict_vram(struct radeon_device *rdev); 246int radeon_object_evict_vram(struct radeon_device *rdev);
246int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset); 247int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
247void radeon_object_force_delete(struct radeon_device *rdev); 248void radeon_object_force_delete(struct radeon_device *rdev);
@@ -574,6 +575,7 @@ struct radeon_asic {
574 void (*ring_start)(struct radeon_device *rdev); 575 void (*ring_start)(struct radeon_device *rdev);
575 int (*irq_set)(struct radeon_device *rdev); 576 int (*irq_set)(struct radeon_device *rdev);
576 int (*irq_process)(struct radeon_device *rdev); 577 int (*irq_process)(struct radeon_device *rdev);
578 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
577 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); 579 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
578 int (*cs_parse)(struct radeon_cs_parser *p); 580 int (*cs_parse)(struct radeon_cs_parser *p);
579 int (*copy_blit)(struct radeon_device *rdev, 581 int (*copy_blit)(struct radeon_device *rdev,
@@ -666,14 +668,11 @@ struct radeon_device {
666 resource_size_t rmmio_base; 668 resource_size_t rmmio_base;
667 resource_size_t rmmio_size; 669 resource_size_t rmmio_size;
668 void *rmmio; 670 void *rmmio;
669 radeon_rreg_t mm_rreg;
670 radeon_wreg_t mm_wreg;
671 radeon_rreg_t mc_rreg; 671 radeon_rreg_t mc_rreg;
672 radeon_wreg_t mc_wreg; 672 radeon_wreg_t mc_wreg;
673 radeon_rreg_t pll_rreg; 673 radeon_rreg_t pll_rreg;
674 radeon_wreg_t pll_wreg; 674 radeon_wreg_t pll_wreg;
675 radeon_rreg_t pcie_rreg; 675 uint32_t pcie_reg_mask;
676 radeon_wreg_t pcie_wreg;
677 radeon_rreg_t pciep_rreg; 676 radeon_rreg_t pciep_rreg;
678 radeon_wreg_t pciep_wreg; 677 radeon_wreg_t pciep_wreg;
679 struct radeon_clock clock; 678 struct radeon_clock clock;
@@ -705,22 +704,42 @@ int radeon_device_init(struct radeon_device *rdev,
705void radeon_device_fini(struct radeon_device *rdev); 704void radeon_device_fini(struct radeon_device *rdev);
706int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 705int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
707 706
707static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
708{
709 if (reg < 0x10000)
710 return readl(((void __iomem *)rdev->rmmio) + reg);
711 else {
712 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
713 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
714 }
715}
716
717static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
718{
719 if (reg < 0x10000)
720 writel(v, ((void __iomem *)rdev->rmmio) + reg);
721 else {
722 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
723 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
724 }
725}
726
708 727
709/* 728/*
710 * Registers read & write functions. 729 * Registers read & write functions.
711 */ 730 */
712#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) 731#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
713#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) 732#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
714#define RREG32(reg) rdev->mm_rreg(rdev, (reg)) 733#define RREG32(reg) r100_mm_rreg(rdev, (reg))
715#define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v)) 734#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
716#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 735#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
717#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 736#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
718#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 737#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
719#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 738#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
720#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 739#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
721#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 740#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
722#define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg)) 741#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
723#define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v)) 742#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
724#define WREG32_P(reg, val, mask) \ 743#define WREG32_P(reg, val, mask) \
725 do { \ 744 do { \
726 uint32_t tmp_ = RREG32(reg); \ 745 uint32_t tmp_ = RREG32(reg); \
@@ -736,6 +755,24 @@ int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
736 WREG32_PLL(reg, tmp_); \ 755 WREG32_PLL(reg, tmp_); \
737 } while (0) 756 } while (0)
738 757
758/*
759 * Indirect registers accessor
760 */
761static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
762{
763 uint32_t r;
764
765 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
766 r = RREG32(RADEON_PCIE_DATA);
767 return r;
768}
769
770static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
771{
772 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
773 WREG32(RADEON_PCIE_DATA, (v));
774}
775
739void r100_pll_errata_after_index(struct radeon_device *rdev); 776void r100_pll_errata_after_index(struct radeon_device *rdev);
740 777
741 778
@@ -862,6 +899,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
862#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 899#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
863#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 900#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
864#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 901#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
902#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
865#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) 903#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
866#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 904#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
867#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 905#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 9a75876e0c3b..7ca6c13569b5 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -49,6 +49,7 @@ void r100_vram_info(struct radeon_device *rdev);
49int r100_gpu_reset(struct radeon_device *rdev); 49int r100_gpu_reset(struct radeon_device *rdev);
50int r100_mc_init(struct radeon_device *rdev); 50int r100_mc_init(struct radeon_device *rdev);
51void r100_mc_fini(struct radeon_device *rdev); 51void r100_mc_fini(struct radeon_device *rdev);
52u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
52int r100_wb_init(struct radeon_device *rdev); 53int r100_wb_init(struct radeon_device *rdev);
53void r100_wb_fini(struct radeon_device *rdev); 54void r100_wb_fini(struct radeon_device *rdev);
54int r100_gart_enable(struct radeon_device *rdev); 55int r100_gart_enable(struct radeon_device *rdev);
@@ -96,6 +97,7 @@ static struct radeon_asic r100_asic = {
96 .ring_start = &r100_ring_start, 97 .ring_start = &r100_ring_start,
97 .irq_set = &r100_irq_set, 98 .irq_set = &r100_irq_set,
98 .irq_process = &r100_irq_process, 99 .irq_process = &r100_irq_process,
100 .get_vblank_counter = &r100_get_vblank_counter,
99 .fence_ring_emit = &r100_fence_ring_emit, 101 .fence_ring_emit = &r100_fence_ring_emit,
100 .cs_parse = &r100_cs_parse, 102 .cs_parse = &r100_cs_parse,
101 .copy_blit = &r100_copy_blit, 103 .copy_blit = &r100_copy_blit,
@@ -156,6 +158,7 @@ static struct radeon_asic r300_asic = {
156 .ring_start = &r300_ring_start, 158 .ring_start = &r300_ring_start,
157 .irq_set = &r100_irq_set, 159 .irq_set = &r100_irq_set,
158 .irq_process = &r100_irq_process, 160 .irq_process = &r100_irq_process,
161 .get_vblank_counter = &r100_get_vblank_counter,
159 .fence_ring_emit = &r300_fence_ring_emit, 162 .fence_ring_emit = &r300_fence_ring_emit,
160 .cs_parse = &r300_cs_parse, 163 .cs_parse = &r300_cs_parse,
161 .copy_blit = &r100_copy_blit, 164 .copy_blit = &r100_copy_blit,
@@ -196,6 +199,7 @@ static struct radeon_asic r420_asic = {
196 .ring_start = &r300_ring_start, 199 .ring_start = &r300_ring_start,
197 .irq_set = &r100_irq_set, 200 .irq_set = &r100_irq_set,
198 .irq_process = &r100_irq_process, 201 .irq_process = &r100_irq_process,
202 .get_vblank_counter = &r100_get_vblank_counter,
199 .fence_ring_emit = &r300_fence_ring_emit, 203 .fence_ring_emit = &r300_fence_ring_emit,
200 .cs_parse = &r300_cs_parse, 204 .cs_parse = &r300_cs_parse,
201 .copy_blit = &r100_copy_blit, 205 .copy_blit = &r100_copy_blit,
@@ -243,6 +247,7 @@ static struct radeon_asic rs400_asic = {
243 .ring_start = &r300_ring_start, 247 .ring_start = &r300_ring_start,
244 .irq_set = &r100_irq_set, 248 .irq_set = &r100_irq_set,
245 .irq_process = &r100_irq_process, 249 .irq_process = &r100_irq_process,
250 .get_vblank_counter = &r100_get_vblank_counter,
246 .fence_ring_emit = &r300_fence_ring_emit, 251 .fence_ring_emit = &r300_fence_ring_emit,
247 .cs_parse = &r300_cs_parse, 252 .cs_parse = &r300_cs_parse,
248 .copy_blit = &r100_copy_blit, 253 .copy_blit = &r100_copy_blit,
@@ -266,6 +271,8 @@ void rs600_vram_info(struct radeon_device *rdev);
266int rs600_mc_init(struct radeon_device *rdev); 271int rs600_mc_init(struct radeon_device *rdev);
267void rs600_mc_fini(struct radeon_device *rdev); 272void rs600_mc_fini(struct radeon_device *rdev);
268int rs600_irq_set(struct radeon_device *rdev); 273int rs600_irq_set(struct radeon_device *rdev);
274int rs600_irq_process(struct radeon_device *rdev);
275u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
269int rs600_gart_enable(struct radeon_device *rdev); 276int rs600_gart_enable(struct radeon_device *rdev);
270void rs600_gart_disable(struct radeon_device *rdev); 277void rs600_gart_disable(struct radeon_device *rdev);
271void rs600_gart_tlb_flush(struct radeon_device *rdev); 278void rs600_gart_tlb_flush(struct radeon_device *rdev);
@@ -291,7 +298,8 @@ static struct radeon_asic rs600_asic = {
291 .cp_disable = &r100_cp_disable, 298 .cp_disable = &r100_cp_disable,
292 .ring_start = &r300_ring_start, 299 .ring_start = &r300_ring_start,
293 .irq_set = &rs600_irq_set, 300 .irq_set = &rs600_irq_set,
294 .irq_process = &r100_irq_process, 301 .irq_process = &rs600_irq_process,
302 .get_vblank_counter = &rs600_get_vblank_counter,
295 .fence_ring_emit = &r300_fence_ring_emit, 303 .fence_ring_emit = &r300_fence_ring_emit,
296 .cs_parse = &r300_cs_parse, 304 .cs_parse = &r300_cs_parse,
297 .copy_blit = &r100_copy_blit, 305 .copy_blit = &r100_copy_blit,
@@ -308,6 +316,7 @@ static struct radeon_asic rs600_asic = {
308/* 316/*
309 * rs690,rs740 317 * rs690,rs740
310 */ 318 */
319int rs690_init(struct radeon_device *rdev);
311void rs690_errata(struct radeon_device *rdev); 320void rs690_errata(struct radeon_device *rdev);
312void rs690_vram_info(struct radeon_device *rdev); 321void rs690_vram_info(struct radeon_device *rdev);
313int rs690_mc_init(struct radeon_device *rdev); 322int rs690_mc_init(struct radeon_device *rdev);
@@ -316,7 +325,7 @@ uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
316void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 325void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
317void rs690_bandwidth_update(struct radeon_device *rdev); 326void rs690_bandwidth_update(struct radeon_device *rdev);
318static struct radeon_asic rs690_asic = { 327static struct radeon_asic rs690_asic = {
319 .init = &r300_init, 328 .init = &rs690_init,
320 .errata = &rs690_errata, 329 .errata = &rs690_errata,
321 .vram_info = &rs690_vram_info, 330 .vram_info = &rs690_vram_info,
322 .gpu_reset = &r300_gpu_reset, 331 .gpu_reset = &r300_gpu_reset,
@@ -333,7 +342,8 @@ static struct radeon_asic rs690_asic = {
333 .cp_disable = &r100_cp_disable, 342 .cp_disable = &r100_cp_disable,
334 .ring_start = &r300_ring_start, 343 .ring_start = &r300_ring_start,
335 .irq_set = &rs600_irq_set, 344 .irq_set = &rs600_irq_set,
336 .irq_process = &r100_irq_process, 345 .irq_process = &rs600_irq_process,
346 .get_vblank_counter = &rs600_get_vblank_counter,
337 .fence_ring_emit = &r300_fence_ring_emit, 347 .fence_ring_emit = &r300_fence_ring_emit,
338 .cs_parse = &r300_cs_parse, 348 .cs_parse = &r300_cs_parse,
339 .copy_blit = &r100_copy_blit, 349 .copy_blit = &r100_copy_blit,
@@ -381,8 +391,9 @@ static struct radeon_asic rv515_asic = {
381 .cp_fini = &r100_cp_fini, 391 .cp_fini = &r100_cp_fini,
382 .cp_disable = &r100_cp_disable, 392 .cp_disable = &r100_cp_disable,
383 .ring_start = &rv515_ring_start, 393 .ring_start = &rv515_ring_start,
384 .irq_set = &r100_irq_set, 394 .irq_set = &rs600_irq_set,
385 .irq_process = &r100_irq_process, 395 .irq_process = &rs600_irq_process,
396 .get_vblank_counter = &rs600_get_vblank_counter,
386 .fence_ring_emit = &r300_fence_ring_emit, 397 .fence_ring_emit = &r300_fence_ring_emit,
387 .cs_parse = &r300_cs_parse, 398 .cs_parse = &r300_cs_parse,
388 .copy_blit = &r100_copy_blit, 399 .copy_blit = &r100_copy_blit,
@@ -423,8 +434,9 @@ static struct radeon_asic r520_asic = {
423 .cp_fini = &r100_cp_fini, 434 .cp_fini = &r100_cp_fini,
424 .cp_disable = &r100_cp_disable, 435 .cp_disable = &r100_cp_disable,
425 .ring_start = &rv515_ring_start, 436 .ring_start = &rv515_ring_start,
426 .irq_set = &r100_irq_set, 437 .irq_set = &rs600_irq_set,
427 .irq_process = &r100_irq_process, 438 .irq_process = &rs600_irq_process,
439 .get_vblank_counter = &rs600_get_vblank_counter,
428 .fence_ring_emit = &r300_fence_ring_emit, 440 .fence_ring_emit = &r300_fence_ring_emit,
429 .cs_parse = &r300_cs_parse, 441 .cs_parse = &r300_cs_parse,
430 .copy_blit = &r100_copy_blit, 442 .copy_blit = &r100_copy_blit,
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index afc4db280b94..2a027e00762a 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -685,23 +685,15 @@ static const uint32_t default_tvdac_adj[CHIP_LAST] = {
685 0x00780000, /* rs480 */ 685 0x00780000, /* rs480 */
686}; 686};
687 687
688static struct radeon_encoder_tv_dac 688static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
689 *radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev) 689 struct radeon_encoder_tv_dac *tv_dac)
690{ 690{
691 struct radeon_encoder_tv_dac *tv_dac = NULL;
692
693 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
694
695 if (!tv_dac)
696 return NULL;
697
698 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 691 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
699 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 692 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
700 tv_dac->ps2_tvdac_adj = 0x00880000; 693 tv_dac->ps2_tvdac_adj = 0x00880000;
701 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 694 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
702 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 695 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
703 696 return;
704 return tv_dac;
705} 697}
706 698
707struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 699struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
@@ -713,19 +705,18 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
713 uint16_t dac_info; 705 uint16_t dac_info;
714 uint8_t rev, bg, dac; 706 uint8_t rev, bg, dac;
715 struct radeon_encoder_tv_dac *tv_dac = NULL; 707 struct radeon_encoder_tv_dac *tv_dac = NULL;
708 int found = 0;
709
710 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
711 if (!tv_dac)
712 return NULL;
716 713
717 if (rdev->bios == NULL) 714 if (rdev->bios == NULL)
718 return radeon_legacy_get_tv_dac_info_from_table(rdev); 715 goto out;
719 716
720 /* first check TV table */ 717 /* first check TV table */
721 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 718 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
722 if (dac_info) { 719 if (dac_info) {
723 tv_dac =
724 kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
725
726 if (!tv_dac)
727 return NULL;
728
729 rev = RBIOS8(dac_info + 0x3); 720 rev = RBIOS8(dac_info + 0x3);
730 if (rev > 4) { 721 if (rev > 4) {
731 bg = RBIOS8(dac_info + 0xc) & 0xf; 722 bg = RBIOS8(dac_info + 0xc) & 0xf;
@@ -739,6 +730,7 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
739 bg = RBIOS8(dac_info + 0x10) & 0xf; 730 bg = RBIOS8(dac_info + 0x10) & 0xf;
740 dac = RBIOS8(dac_info + 0x11) & 0xf; 731 dac = RBIOS8(dac_info + 0x11) & 0xf;
741 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 732 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
733 found = 1;
742 } else if (rev > 1) { 734 } else if (rev > 1) {
743 bg = RBIOS8(dac_info + 0xc) & 0xf; 735 bg = RBIOS8(dac_info + 0xc) & 0xf;
744 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 736 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
@@ -751,22 +743,15 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
751 bg = RBIOS8(dac_info + 0xe) & 0xf; 743 bg = RBIOS8(dac_info + 0xe) & 0xf;
752 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 744 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
753 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 745 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
746 found = 1;
754 } 747 }
755
756 tv_dac->tv_std = radeon_combios_get_tv_info(encoder); 748 tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
757 749 }
758 } else { 750 if (!found) {
759 /* then check CRT table */ 751 /* then check CRT table */
760 dac_info = 752 dac_info =
761 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 753 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
762 if (dac_info) { 754 if (dac_info) {
763 tv_dac =
764 kzalloc(sizeof(struct radeon_encoder_tv_dac),
765 GFP_KERNEL);
766
767 if (!tv_dac)
768 return NULL;
769
770 rev = RBIOS8(dac_info) & 0x3; 755 rev = RBIOS8(dac_info) & 0x3;
771 if (rev < 2) { 756 if (rev < 2) {
772 bg = RBIOS8(dac_info + 0x3) & 0xf; 757 bg = RBIOS8(dac_info + 0x3) & 0xf;
@@ -775,6 +760,7 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
775 (bg << 16) | (dac << 20); 760 (bg << 16) | (dac << 20);
776 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 761 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
777 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 762 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
763 found = 1;
778 } else { 764 } else {
779 bg = RBIOS8(dac_info + 0x4) & 0xf; 765 bg = RBIOS8(dac_info + 0x4) & 0xf;
780 dac = RBIOS8(dac_info + 0x5) & 0xf; 766 dac = RBIOS8(dac_info + 0x5) & 0xf;
@@ -782,13 +768,17 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
782 (bg << 16) | (dac << 20); 768 (bg << 16) | (dac << 20);
783 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 769 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
784 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 770 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
771 found = 1;
785 } 772 }
786 } else { 773 } else {
787 DRM_INFO("No TV DAC info found in BIOS\n"); 774 DRM_INFO("No TV DAC info found in BIOS\n");
788 return radeon_legacy_get_tv_dac_info_from_table(rdev);
789 } 775 }
790 } 776 }
791 777
778out:
779 if (!found) /* fallback to defaults */
780 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
781
792 return tv_dac; 782 return tv_dac;
793} 783}
794 784
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 9ff6dcb97f9d..7693f7c67bd3 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -225,25 +225,18 @@ void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
225 225
226void radeon_register_accessor_init(struct radeon_device *rdev) 226void radeon_register_accessor_init(struct radeon_device *rdev)
227{ 227{
228 rdev->mm_rreg = &r100_mm_rreg;
229 rdev->mm_wreg = &r100_mm_wreg;
230 rdev->mc_rreg = &radeon_invalid_rreg; 228 rdev->mc_rreg = &radeon_invalid_rreg;
231 rdev->mc_wreg = &radeon_invalid_wreg; 229 rdev->mc_wreg = &radeon_invalid_wreg;
232 rdev->pll_rreg = &radeon_invalid_rreg; 230 rdev->pll_rreg = &radeon_invalid_rreg;
233 rdev->pll_wreg = &radeon_invalid_wreg; 231 rdev->pll_wreg = &radeon_invalid_wreg;
234 rdev->pcie_rreg = &radeon_invalid_rreg;
235 rdev->pcie_wreg = &radeon_invalid_wreg;
236 rdev->pciep_rreg = &radeon_invalid_rreg; 232 rdev->pciep_rreg = &radeon_invalid_rreg;
237 rdev->pciep_wreg = &radeon_invalid_wreg; 233 rdev->pciep_wreg = &radeon_invalid_wreg;
238 234
239 /* Don't change order as we are overridding accessor. */ 235 /* Don't change order as we are overridding accessor. */
240 if (rdev->family < CHIP_RV515) { 236 if (rdev->family < CHIP_RV515) {
241 rdev->pcie_rreg = &rv370_pcie_rreg; 237 rdev->pcie_reg_mask = 0xff;
242 rdev->pcie_wreg = &rv370_pcie_wreg; 238 } else {
243 } 239 rdev->pcie_reg_mask = 0x7ff;
244 if (rdev->family >= CHIP_RV515) {
245 rdev->pcie_rreg = &rv515_pcie_rreg;
246 rdev->pcie_wreg = &rv515_pcie_wreg;
247 } 240 }
248 /* FIXME: not sure here */ 241 /* FIXME: not sure here */
249 if (rdev->family <= CHIP_R580) { 242 if (rdev->family <= CHIP_R580) {
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 3206c0ad7b6c..ec383edf5f38 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -574,6 +574,8 @@ int radeonfb_create(struct radeon_device *rdev,
574 goto out_unref; 574 goto out_unref;
575 } 575 }
576 576
577 memset_io(fbptr, 0, aligned_size);
578
577 strcpy(info->fix.id, "radeondrmfb"); 579 strcpy(info->fix.id, "radeondrmfb");
578 info->fix.type = FB_TYPE_PACKED_PIXELS; 580 info->fix.type = FB_TYPE_PACKED_PIXELS;
579 info->fix.visual = FB_VISUAL_TRUECOLOR; 581 info->fix.visual = FB_VISUAL_TRUECOLOR;
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index cded5180c752..d4ceff13bbb1 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -262,7 +262,27 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
262int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 262int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
263 struct drm_file *filp) 263 struct drm_file *filp)
264{ 264{
265 /* FIXME: implement */ 265 struct drm_radeon_gem_busy *args = data;
266 struct drm_gem_object *gobj;
267 struct radeon_object *robj;
268 int r;
269 uint32_t cur_placement;
270
271 gobj = drm_gem_object_lookup(dev, filp, args->handle);
272 if (gobj == NULL) {
273 return -EINVAL;
274 }
275 robj = gobj->driver_private;
276 r = radeon_object_busy_domain(robj, &cur_placement);
277 if (cur_placement == TTM_PL_VRAM)
278 args->domain = RADEON_GEM_DOMAIN_VRAM;
279 if (cur_placement == TTM_PL_FLAG_TT)
280 args->domain = RADEON_GEM_DOMAIN_GTT;
281 if (cur_placement == TTM_PL_FLAG_SYSTEM)
282 args->domain = RADEON_GEM_DOMAIN_CPU;
283 mutex_lock(&dev->struct_mutex);
284 drm_gem_object_unreference(gobj);
285 mutex_unlock(&dev->struct_mutex);
266 return 0; 286 return 0;
267} 287}
268 288
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 491d569deb0e..9805e4b6ca1b 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -32,60 +32,6 @@
32#include "radeon.h" 32#include "radeon.h"
33#include "atom.h" 33#include "atom.h"
34 34
35static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
36{
37 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
38 uint32_t irq_mask = RADEON_SW_INT_TEST;
39
40 if (irqs) {
41 WREG32(RADEON_GEN_INT_STATUS, irqs);
42 }
43 return irqs & irq_mask;
44}
45
46int r100_irq_set(struct radeon_device *rdev)
47{
48 uint32_t tmp = 0;
49
50 if (rdev->irq.sw_int) {
51 tmp |= RADEON_SW_INT_ENABLE;
52 }
53 /* Todo go through CRTC and enable vblank int or not */
54 WREG32(RADEON_GEN_INT_CNTL, tmp);
55 return 0;
56}
57
58int r100_irq_process(struct radeon_device *rdev)
59{
60 uint32_t status;
61
62 status = r100_irq_ack(rdev);
63 if (!status) {
64 return IRQ_NONE;
65 }
66 while (status) {
67 /* SW interrupt */
68 if (status & RADEON_SW_INT_TEST) {
69 radeon_fence_process(rdev);
70 }
71 status = r100_irq_ack(rdev);
72 }
73 return IRQ_HANDLED;
74}
75
76int rs600_irq_set(struct radeon_device *rdev)
77{
78 uint32_t tmp = 0;
79
80 if (rdev->irq.sw_int) {
81 tmp |= RADEON_SW_INT_ENABLE;
82 }
83 WREG32(RADEON_GEN_INT_CNTL, tmp);
84 /* Todo go through CRTC and enable vblank int or not */
85 WREG32(R500_DxMODE_INT_MASK, 0);
86 return 0;
87}
88
89irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS) 35irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS)
90{ 36{
91 struct drm_device *dev = (struct drm_device *) arg; 37 struct drm_device *dev = (struct drm_device *) arg;
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 3357110e30ce..d2764bf6b2a2 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -141,19 +141,42 @@ void radeon_driver_preclose_kms(struct drm_device *dev,
141 */ 141 */
142u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 142u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
143{ 143{
144 /* FIXME: implement */ 144 struct radeon_device *rdev = dev->dev_private;
145 return 0; 145
146 if (crtc < 0 || crtc > 1) {
147 DRM_ERROR("Invalid crtc %d\n", crtc);
148 return -EINVAL;
149 }
150
151 return radeon_get_vblank_counter(rdev, crtc);
146} 152}
147 153
148int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 154int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
149{ 155{
150 /* FIXME: implement */ 156 struct radeon_device *rdev = dev->dev_private;
151 return 0; 157
158 if (crtc < 0 || crtc > 1) {
159 DRM_ERROR("Invalid crtc %d\n", crtc);
160 return -EINVAL;
161 }
162
163 rdev->irq.crtc_vblank_int[crtc] = true;
164
165 return radeon_irq_set(rdev);
152} 166}
153 167
154void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 168void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
155{ 169{
156 /* FIXME: implement */ 170 struct radeon_device *rdev = dev->dev_private;
171
172 if (crtc < 0 || crtc > 1) {
173 DRM_ERROR("Invalid crtc %d\n", crtc);
174 return;
175 }
176
177 rdev->irq.crtc_vblank_int[crtc] = false;
178
179 radeon_irq_set(rdev);
157} 180}
158 181
159 182
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 7d06dc98a42a..0da72f18fd3a 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -310,10 +310,13 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
310 RADEON_CRTC_DISP_REQ_EN_B)); 310 RADEON_CRTC_DISP_REQ_EN_B));
311 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask); 311 WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
312 } 312 }
313 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
314 radeon_crtc_load_lut(crtc);
313 break; 315 break;
314 case DRM_MODE_DPMS_STANDBY: 316 case DRM_MODE_DPMS_STANDBY:
315 case DRM_MODE_DPMS_SUSPEND: 317 case DRM_MODE_DPMS_SUSPEND:
316 case DRM_MODE_DPMS_OFF: 318 case DRM_MODE_DPMS_OFF:
319 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
317 if (radeon_crtc->crtc_id) 320 if (radeon_crtc->crtc_id)
318 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask); 321 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
319 else { 322 else {
@@ -323,10 +326,6 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
323 } 326 }
324 break; 327 break;
325 } 328 }
326
327 if (mode != DRM_MODE_DPMS_OFF) {
328 radeon_crtc_load_lut(crtc);
329 }
330} 329}
331 330
332/* properly set crtc bpp when using atombios */ 331/* properly set crtc bpp when using atombios */
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 34d0f58eb944..9322675ef6d0 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -1066,6 +1066,7 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t
1066 1066
1067 switch (radeon_encoder->encoder_id) { 1067 switch (radeon_encoder->encoder_id) {
1068 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1068 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1069 encoder->possible_crtcs = 0x1;
1069 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS); 1070 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1070 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs); 1071 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1071 if (rdev->is_atom_bios) 1072 if (rdev->is_atom_bios)
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index e98cae3bf4a6..b85fb83d7ae8 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -316,6 +316,25 @@ int radeon_object_wait(struct radeon_object *robj)
316 return r; 316 return r;
317} 317}
318 318
319int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement)
320{
321 int r = 0;
322
323 r = radeon_object_reserve(robj, true);
324 if (unlikely(r != 0)) {
325 DRM_ERROR("radeon: failed to reserve object for waiting.\n");
326 return r;
327 }
328 spin_lock(&robj->tobj.lock);
329 *cur_placement = robj->tobj.mem.mem_type;
330 if (robj->tobj.sync_obj) {
331 r = ttm_bo_wait(&robj->tobj, true, true, true);
332 }
333 spin_unlock(&robj->tobj.lock);
334 radeon_object_unreserve(robj);
335 return r;
336}
337
319int radeon_object_evict_vram(struct radeon_device *rdev) 338int radeon_object_evict_vram(struct radeon_device *rdev)
320{ 339{
321 if (rdev->flags & RADEON_IS_IGP) { 340 if (rdev->flags & RADEON_IS_IGP) {
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index e1b618574461..5a098f304edb 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -982,12 +982,15 @@
982# define RS400_TMDS2_PLLRST (1 << 1) 982# define RS400_TMDS2_PLLRST (1 << 1)
983 983
984#define RADEON_GEN_INT_CNTL 0x0040 984#define RADEON_GEN_INT_CNTL 0x0040
985# define RADEON_CRTC_VBLANK_MASK (1 << 0)
986# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
985# define RADEON_SW_INT_ENABLE (1 << 25) 987# define RADEON_SW_INT_ENABLE (1 << 25)
986#define RADEON_GEN_INT_STATUS 0x0044 988#define RADEON_GEN_INT_STATUS 0x0044
987# define RADEON_VSYNC_INT_AK (1 << 2) 989# define AVIVO_DISPLAY_INT_STATUS (1 << 0)
988# define RADEON_VSYNC_INT (1 << 2) 990# define RADEON_CRTC_VBLANK_STAT (1 << 0)
989# define RADEON_VSYNC2_INT_AK (1 << 6) 991# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
990# define RADEON_VSYNC2_INT (1 << 6) 992# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
993# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
991# define RADEON_SW_INT_FIRE (1 << 26) 994# define RADEON_SW_INT_FIRE (1 << 26)
992# define RADEON_SW_INT_TEST (1 << 25) 995# define RADEON_SW_INT_TEST (1 << 25)
993# define RADEON_SW_INT_TEST_ACK (1 << 25) 996# define RADEON_SW_INT_TEST_ACK (1 << 25)
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index bbea6dee4a94..7e8ce983a908 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -240,6 +240,88 @@ void rs600_mc_fini(struct radeon_device *rdev)
240 240
241 241
242/* 242/*
243 * Interrupts
244 */
245int rs600_irq_set(struct radeon_device *rdev)
246{
247 uint32_t tmp = 0;
248 uint32_t mode_int = 0;
249
250 if (rdev->irq.sw_int) {
251 tmp |= RADEON_SW_INT_ENABLE;
252 }
253 if (rdev->irq.crtc_vblank_int[0]) {
254 tmp |= AVIVO_DISPLAY_INT_STATUS;
255 mode_int |= AVIVO_D1MODE_INT_MASK;
256 }
257 if (rdev->irq.crtc_vblank_int[1]) {
258 tmp |= AVIVO_DISPLAY_INT_STATUS;
259 mode_int |= AVIVO_D2MODE_INT_MASK;
260 }
261 WREG32(RADEON_GEN_INT_CNTL, tmp);
262 WREG32(AVIVO_DxMODE_INT_MASK, mode_int);
263 return 0;
264}
265
266static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
267{
268 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
269 uint32_t irq_mask = RADEON_SW_INT_TEST;
270
271 if (irqs & AVIVO_DISPLAY_INT_STATUS) {
272 *r500_disp_int = RREG32(AVIVO_DISP_INTERRUPT_STATUS);
273 if (*r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
274 WREG32(AVIVO_D1MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
275 }
276 if (*r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
277 WREG32(AVIVO_D2MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
278 }
279 } else {
280 *r500_disp_int = 0;
281 }
282
283 if (irqs) {
284 WREG32(RADEON_GEN_INT_STATUS, irqs);
285 }
286 return irqs & irq_mask;
287}
288
289int rs600_irq_process(struct radeon_device *rdev)
290{
291 uint32_t status;
292 uint32_t r500_disp_int;
293
294 status = rs600_irq_ack(rdev, &r500_disp_int);
295 if (!status && !r500_disp_int) {
296 return IRQ_NONE;
297 }
298 while (status || r500_disp_int) {
299 /* SW interrupt */
300 if (status & RADEON_SW_INT_TEST) {
301 radeon_fence_process(rdev);
302 }
303 /* Vertical blank interrupts */
304 if (r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
305 drm_handle_vblank(rdev->ddev, 0);
306 }
307 if (r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
308 drm_handle_vblank(rdev->ddev, 1);
309 }
310 status = rs600_irq_ack(rdev, &r500_disp_int);
311 }
312 return IRQ_HANDLED;
313}
314
315u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
316{
317 if (crtc == 0)
318 return RREG32(AVIVO_D1CRTC_FRAME_COUNT);
319 else
320 return RREG32(AVIVO_D2CRTC_FRAME_COUNT);
321}
322
323
324/*
243 * Global GPU functions 325 * Global GPU functions
244 */ 326 */
245void rs600_disable_vga(struct radeon_device *rdev) 327void rs600_disable_vga(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 839595b00728..bc6b7c5339bc 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -652,3 +652,68 @@ void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
652 WREG32(RS690_MC_DATA, v); 652 WREG32(RS690_MC_DATA, v);
653 WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); 653 WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
654} 654}
655
656static const unsigned rs690_reg_safe_bm[219] = {
657 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
658 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
659 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
660 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
661 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
662 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
663 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
664 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
665 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
666 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
667 0x17FF1FFF,0xFFFFFFFC,0xFFFFFFFF,0xFF30FFBF,
668 0xFFFFFFF8,0xC3E6FFFF,0xFFFFF6DF,0xFFFFFFFF,
669 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
670 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
671 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFF03F,
672 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
673 0xFFFFFFFF,0xFFFFEFCE,0xF00EBFFF,0x007C0000,
674 0xF0000078,0xFF000009,0xFFFFFFFF,0xFFFFFFFF,
675 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
676 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
677 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
678 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
679 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
680 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
681 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
682 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
683 0xFFFFF7FF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
684 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
685 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
686 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
687 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
688 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
689 0xFFFFFC78,0xFFFFFFFF,0xFFFFFFFE,0xFFFFFFFF,
690 0x38FF8F50,0xFFF88082,0xF000000C,0xFAE009FF,
691 0x0000FFFF,0xFFFFFFFF,0xFFFFFFFF,0x00000000,
692 0x00000000,0x0000C100,0x00000000,0x00000000,
693 0x00000000,0x00000000,0x00000000,0x00000000,
694 0x00000000,0xFFFF0000,0xFFFFFFFF,0xFF80FFFF,
695 0x00000000,0x00000000,0x00000000,0x00000000,
696 0x0003FC01,0xFFFFFFF8,0xFE800B19,0xFFFFFFFF,
697 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
698 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
699 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
700 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
701 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
702 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
703 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
704 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
705 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
706 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
707 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
708 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
709 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
710 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
711 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,
712};
713
714int rs690_init(struct radeon_device *rdev)
715{
716 rdev->config.r300.reg_safe_bm = rs690_reg_safe_bm;
717 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs690_reg_safe_bm);
718 return 0;
719}
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index fd8f3ca716ea..31a7f668ae5a 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -400,25 +400,6 @@ void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
400 WREG32(MC_IND_INDEX, 0); 400 WREG32(MC_IND_INDEX, 0);
401} 401}
402 402
403uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
404{
405 uint32_t r;
406
407 WREG32(PCIE_INDEX, ((reg) & 0x7ff));
408 (void)RREG32(PCIE_INDEX);
409 r = RREG32(PCIE_DATA);
410 return r;
411}
412
413void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
414{
415 WREG32(PCIE_INDEX, ((reg) & 0x7ff));
416 (void)RREG32(PCIE_INDEX);
417 WREG32(PCIE_DATA, (v));
418 (void)RREG32(PCIE_DATA);
419}
420
421
422/* 403/*
423 * Debugfs info 404 * Debugfs info
424 */ 405 */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 03:01:04 -0500