diff options
author | Al Viro <viro@ftp.linux.org.uk> | 2008-03-19 12:27:48 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-03-19 22:42:36 -0400 |
commit | 457fb605834504af294916411be128a9b21fc3f6 (patch) | |
tree | 6813daab294e40068269c0564bd8c4f479f73dbc /drivers | |
parent | 635440c0235537a3f0a90ed5b6f8cd8a5da862de (diff) |
drivers/char/rocket portability fixes
unsigned long != __le32, TYVM, and unsigned char[4] is not guaranteed
to be aligned for u32.
While we are at it, sanitize sOutDW() a bit - have it take Byte_t * and
handle dereferencing internally.
NB: sWriteTxPrioByte() is almost certainly buggered on big-endian and is
missing cpu_to_le16() on assignments to *WordPtr; I've left it alone for now.
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Acked-by: "Theodore Ts'o" <tytso@mit.edu>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/char/rocket.c | 37 | ||||
-rw-r--r-- | drivers/char/rocket_int.h | 83 |
2 files changed, 56 insertions, 64 deletions
diff --git a/drivers/char/rocket.c b/drivers/char/rocket.c index 72f289279d8f..f585bc8579e9 100644 --- a/drivers/char/rocket.c +++ b/drivers/char/rocket.c | |||
@@ -83,6 +83,7 @@ | |||
83 | #include <linux/pci.h> | 83 | #include <linux/pci.h> |
84 | #include <asm/uaccess.h> | 84 | #include <asm/uaccess.h> |
85 | #include <asm/atomic.h> | 85 | #include <asm/atomic.h> |
86 | #include <asm/unaligned.h> | ||
86 | #include <linux/bitops.h> | 87 | #include <linux/bitops.h> |
87 | #include <linux/spinlock.h> | 88 | #include <linux/spinlock.h> |
88 | #include <linux/init.h> | 89 | #include <linux/init.h> |
@@ -1312,7 +1313,7 @@ static int rp_tiocmset(struct tty_struct *tty, struct file *file, | |||
1312 | if (clear & TIOCM_DTR) | 1313 | if (clear & TIOCM_DTR) |
1313 | info->channel.TxControl[3] &= ~SET_DTR; | 1314 | info->channel.TxControl[3] &= ~SET_DTR; |
1314 | 1315 | ||
1315 | sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0])); | 1316 | out32(info->channel.IndexAddr, info->channel.TxControl); |
1316 | return 0; | 1317 | return 0; |
1317 | } | 1318 | } |
1318 | 1319 | ||
@@ -1748,7 +1749,7 @@ static int rp_write(struct tty_struct *tty, | |||
1748 | 1749 | ||
1749 | /* Write remaining data into the port's xmit_buf */ | 1750 | /* Write remaining data into the port's xmit_buf */ |
1750 | while (1) { | 1751 | while (1) { |
1751 | if (info->tty == 0) /* Seemingly obligatory check... */ | 1752 | if (!info->tty) /* Seemingly obligatory check... */ |
1752 | goto end; | 1753 | goto end; |
1753 | 1754 | ||
1754 | c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head)); | 1755 | c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head)); |
@@ -2798,7 +2799,7 @@ static int sReadAiopNumChan(WordIO_t io) | |||
2798 | static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 }; | 2799 | static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 }; |
2799 | 2800 | ||
2800 | /* write to chan 0 SRAM */ | 2801 | /* write to chan 0 SRAM */ |
2801 | sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0])); | 2802 | out32((DWordIO_t) io + _INDX_ADDR, R); |
2802 | sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */ | 2803 | sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */ |
2803 | x = sInW(io + _INDX_DATA); | 2804 | x = sInW(io + _INDX_DATA); |
2804 | sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */ | 2805 | sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */ |
@@ -2864,7 +2865,7 @@ static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum, | |||
2864 | R[1] = RData[i + 1] + 0x10 * ChanNum; | 2865 | R[1] = RData[i + 1] + 0x10 * ChanNum; |
2865 | R[2] = RData[i + 2]; | 2866 | R[2] = RData[i + 2]; |
2866 | R[3] = RData[i + 3]; | 2867 | R[3] = RData[i + 3]; |
2867 | sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0])); | 2868 | out32(ChP->IndexAddr, R); |
2868 | } | 2869 | } |
2869 | 2870 | ||
2870 | ChR = ChP->R; | 2871 | ChR = ChP->R; |
@@ -2887,43 +2888,43 @@ static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum, | |||
2887 | ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8); | 2888 | ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8); |
2888 | ChP->BaudDiv[2] = (Byte_t) brd9600; | 2889 | ChP->BaudDiv[2] = (Byte_t) brd9600; |
2889 | ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8); | 2890 | ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8); |
2890 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]); | 2891 | out32(ChP->IndexAddr, ChP->BaudDiv); |
2891 | 2892 | ||
2892 | ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL); | 2893 | ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL); |
2893 | ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8); | 2894 | ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8); |
2894 | ChP->TxControl[2] = 0; | 2895 | ChP->TxControl[2] = 0; |
2895 | ChP->TxControl[3] = 0; | 2896 | ChP->TxControl[3] = 0; |
2896 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); | 2897 | out32(ChP->IndexAddr, ChP->TxControl); |
2897 | 2898 | ||
2898 | ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL); | 2899 | ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL); |
2899 | ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8); | 2900 | ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8); |
2900 | ChP->RxControl[2] = 0; | 2901 | ChP->RxControl[2] = 0; |
2901 | ChP->RxControl[3] = 0; | 2902 | ChP->RxControl[3] = 0; |
2902 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); | 2903 | out32(ChP->IndexAddr, ChP->RxControl); |
2903 | 2904 | ||
2904 | ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS); | 2905 | ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS); |
2905 | ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8); | 2906 | ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8); |
2906 | ChP->TxEnables[2] = 0; | 2907 | ChP->TxEnables[2] = 0; |
2907 | ChP->TxEnables[3] = 0; | 2908 | ChP->TxEnables[3] = 0; |
2908 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]); | 2909 | out32(ChP->IndexAddr, ChP->TxEnables); |
2909 | 2910 | ||
2910 | ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1); | 2911 | ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1); |
2911 | ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8); | 2912 | ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8); |
2912 | ChP->TxCompare[2] = 0; | 2913 | ChP->TxCompare[2] = 0; |
2913 | ChP->TxCompare[3] = 0; | 2914 | ChP->TxCompare[3] = 0; |
2914 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]); | 2915 | out32(ChP->IndexAddr, ChP->TxCompare); |
2915 | 2916 | ||
2916 | ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1); | 2917 | ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1); |
2917 | ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8); | 2918 | ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8); |
2918 | ChP->TxReplace1[2] = 0; | 2919 | ChP->TxReplace1[2] = 0; |
2919 | ChP->TxReplace1[3] = 0; | 2920 | ChP->TxReplace1[3] = 0; |
2920 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]); | 2921 | out32(ChP->IndexAddr, ChP->TxReplace1); |
2921 | 2922 | ||
2922 | ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2); | 2923 | ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2); |
2923 | ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8); | 2924 | ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8); |
2924 | ChP->TxReplace2[2] = 0; | 2925 | ChP->TxReplace2[2] = 0; |
2925 | ChP->TxReplace2[3] = 0; | 2926 | ChP->TxReplace2[3] = 0; |
2926 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]); | 2927 | out32(ChP->IndexAddr, ChP->TxReplace2); |
2927 | 2928 | ||
2928 | ChP->TxFIFOPtrs = ChOff + _TXF_OUTP; | 2929 | ChP->TxFIFOPtrs = ChOff + _TXF_OUTP; |
2929 | ChP->TxFIFO = ChOff + _TX_FIFO; | 2930 | ChP->TxFIFO = ChOff + _TX_FIFO; |
@@ -2979,7 +2980,7 @@ static void sStopRxProcessor(CHANNEL_T * ChP) | |||
2979 | R[1] = ChP->R[1]; | 2980 | R[1] = ChP->R[1]; |
2980 | R[2] = 0x0a; | 2981 | R[2] = 0x0a; |
2981 | R[3] = ChP->R[3]; | 2982 | R[3] = ChP->R[3]; |
2982 | sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]); | 2983 | out32(ChP->IndexAddr, R); |
2983 | } | 2984 | } |
2984 | 2985 | ||
2985 | /*************************************************************************** | 2986 | /*************************************************************************** |
@@ -3094,13 +3095,13 @@ static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data) | |||
3094 | *WordPtr = ChP->TxPrioBuf; /* data byte address */ | 3095 | *WordPtr = ChP->TxPrioBuf; /* data byte address */ |
3095 | 3096 | ||
3096 | DWBuf[2] = Data; /* data byte value */ | 3097 | DWBuf[2] = Data; /* data byte value */ |
3097 | sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */ | 3098 | out32(IndexAddr, DWBuf); /* write it out */ |
3098 | 3099 | ||
3099 | *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */ | 3100 | *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */ |
3100 | 3101 | ||
3101 | DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */ | 3102 | DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */ |
3102 | DWBuf[3] = 0; /* priority buffer pointer */ | 3103 | DWBuf[3] = 0; /* priority buffer pointer */ |
3103 | sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */ | 3104 | out32(IndexAddr, DWBuf); /* write it out */ |
3104 | } else { /* write it to Tx FIFO */ | 3105 | } else { /* write it to Tx FIFO */ |
3105 | 3106 | ||
3106 | sWriteTxByte(sGetTxRxDataIO(ChP), Data); | 3107 | sWriteTxByte(sGetTxRxDataIO(ChP), Data); |
@@ -3147,11 +3148,11 @@ static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags) | |||
3147 | ChP->RxControl[2] |= | 3148 | ChP->RxControl[2] |= |
3148 | ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); | 3149 | ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); |
3149 | 3150 | ||
3150 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); | 3151 | out32(ChP->IndexAddr, ChP->RxControl); |
3151 | 3152 | ||
3152 | ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN); | 3153 | ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN); |
3153 | 3154 | ||
3154 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); | 3155 | out32(ChP->IndexAddr, ChP->TxControl); |
3155 | 3156 | ||
3156 | if (Flags & CHANINT_EN) { | 3157 | if (Flags & CHANINT_EN) { |
3157 | Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum]; | 3158 | Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum]; |
@@ -3190,9 +3191,9 @@ static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags) | |||
3190 | 3191 | ||
3191 | ChP->RxControl[2] &= | 3192 | ChP->RxControl[2] &= |
3192 | ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); | 3193 | ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN)); |
3193 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]); | 3194 | out32(ChP->IndexAddr, ChP->RxControl); |
3194 | ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN); | 3195 | ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN); |
3195 | sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]); | 3196 | out32(ChP->IndexAddr, ChP->TxControl); |
3196 | 3197 | ||
3197 | if (Flags & CHANINT_EN) { | 3198 | if (Flags & CHANINT_EN) { |
3198 | Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum]; | 3199 | Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum]; |
diff --git a/drivers/char/rocket_int.h b/drivers/char/rocket_int.h index f3a75791b811..b01d38125a8f 100644 --- a/drivers/char/rocket_int.h +++ b/drivers/char/rocket_int.h | |||
@@ -26,7 +26,6 @@ typedef unsigned int ByteIO_t; | |||
26 | typedef unsigned int Word_t; | 26 | typedef unsigned int Word_t; |
27 | typedef unsigned int WordIO_t; | 27 | typedef unsigned int WordIO_t; |
28 | 28 | ||
29 | typedef unsigned long DWord_t; | ||
30 | typedef unsigned int DWordIO_t; | 29 | typedef unsigned int DWordIO_t; |
31 | 30 | ||
32 | /* | 31 | /* |
@@ -38,7 +37,6 @@ typedef unsigned int DWordIO_t; | |||
38 | * instruction. | 37 | * instruction. |
39 | */ | 38 | */ |
40 | 39 | ||
41 | #ifdef ROCKET_DEBUG_IO | ||
42 | static inline void sOutB(unsigned short port, unsigned char value) | 40 | static inline void sOutB(unsigned short port, unsigned char value) |
43 | { | 41 | { |
44 | #ifdef ROCKET_DEBUG_IO | 42 | #ifdef ROCKET_DEBUG_IO |
@@ -55,12 +53,13 @@ static inline void sOutW(unsigned short port, unsigned short value) | |||
55 | outw_p(value, port); | 53 | outw_p(value, port); |
56 | } | 54 | } |
57 | 55 | ||
58 | static inline void sOutDW(unsigned short port, unsigned long value) | 56 | static inline void out32(unsigned short port, Byte_t *p) |
59 | { | 57 | { |
58 | u32 value = le32_to_cpu(get_unaligned((__le32 *)p)); | ||
60 | #ifdef ROCKET_DEBUG_IO | 59 | #ifdef ROCKET_DEBUG_IO |
61 | printk(KERN_DEBUG "sOutDW(%x, %lx)...\n", port, value); | 60 | printk(KERN_DEBUG "out32(%x, %lx)...\n", port, value); |
62 | #endif | 61 | #endif |
63 | outl_p(cpu_to_le32(value), port); | 62 | outl_p(value, port); |
64 | } | 63 | } |
65 | 64 | ||
66 | static inline unsigned char sInB(unsigned short port) | 65 | static inline unsigned char sInB(unsigned short port) |
@@ -73,14 +72,6 @@ static inline unsigned short sInW(unsigned short port) | |||
73 | return inw_p(port); | 72 | return inw_p(port); |
74 | } | 73 | } |
75 | 74 | ||
76 | #else /* !ROCKET_DEBUG_IO */ | ||
77 | #define sOutB(a, b) outb_p(b, a) | ||
78 | #define sOutW(a, b) outw_p(b, a) | ||
79 | #define sOutDW(port, value) outl_p(cpu_to_le32(value), port) | ||
80 | #define sInB(a) (inb_p(a)) | ||
81 | #define sInW(a) (inw_p(a)) | ||
82 | #endif /* ROCKET_DEBUG_IO */ | ||
83 | |||
84 | /* This is used to move arrays of bytes so byte swapping isn't appropriate. */ | 75 | /* This is used to move arrays of bytes so byte swapping isn't appropriate. */ |
85 | #define sOutStrW(port, addr, count) if (count) outsw(port, addr, count) | 76 | #define sOutStrW(port, addr, count) if (count) outsw(port, addr, count) |
86 | #define sInStrW(port, addr, count) if (count) insw(port, addr, count) | 77 | #define sInStrW(port, addr, count) if (count) insw(port, addr, count) |
@@ -390,7 +381,7 @@ Call: sClrBreak(ChP) | |||
390 | #define sClrBreak(ChP) \ | 381 | #define sClrBreak(ChP) \ |
391 | do { \ | 382 | do { \ |
392 | (ChP)->TxControl[3] &= ~SETBREAK; \ | 383 | (ChP)->TxControl[3] &= ~SETBREAK; \ |
393 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 384 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
394 | } while (0) | 385 | } while (0) |
395 | 386 | ||
396 | /*************************************************************************** | 387 | /*************************************************************************** |
@@ -402,7 +393,7 @@ Call: sClrDTR(ChP) | |||
402 | #define sClrDTR(ChP) \ | 393 | #define sClrDTR(ChP) \ |
403 | do { \ | 394 | do { \ |
404 | (ChP)->TxControl[3] &= ~SET_DTR; \ | 395 | (ChP)->TxControl[3] &= ~SET_DTR; \ |
405 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 396 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
406 | } while (0) | 397 | } while (0) |
407 | 398 | ||
408 | /*************************************************************************** | 399 | /*************************************************************************** |
@@ -415,7 +406,7 @@ Call: sClrRTS(ChP) | |||
415 | do { \ | 406 | do { \ |
416 | if ((ChP)->rtsToggle) break; \ | 407 | if ((ChP)->rtsToggle) break; \ |
417 | (ChP)->TxControl[3] &= ~SET_RTS; \ | 408 | (ChP)->TxControl[3] &= ~SET_RTS; \ |
418 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 409 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
419 | } while (0) | 410 | } while (0) |
420 | 411 | ||
421 | /*************************************************************************** | 412 | /*************************************************************************** |
@@ -489,7 +480,7 @@ Call: sDisCTSFlowCtl(ChP) | |||
489 | #define sDisCTSFlowCtl(ChP) \ | 480 | #define sDisCTSFlowCtl(ChP) \ |
490 | do { \ | 481 | do { \ |
491 | (ChP)->TxControl[2] &= ~CTSFC_EN; \ | 482 | (ChP)->TxControl[2] &= ~CTSFC_EN; \ |
492 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 483 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
493 | } while (0) | 484 | } while (0) |
494 | 485 | ||
495 | /*************************************************************************** | 486 | /*************************************************************************** |
@@ -501,7 +492,7 @@ Call: sDisIXANY(ChP) | |||
501 | #define sDisIXANY(ChP) \ | 492 | #define sDisIXANY(ChP) \ |
502 | do { \ | 493 | do { \ |
503 | (ChP)->R[0x0e] = 0x86; \ | 494 | (ChP)->R[0x0e] = 0x86; \ |
504 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ | 495 | out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \ |
505 | } while (0) | 496 | } while (0) |
506 | 497 | ||
507 | /*************************************************************************** | 498 | /*************************************************************************** |
@@ -515,7 +506,7 @@ Comments: Function sSetParity() can be used in place of functions sEnParity(), | |||
515 | #define sDisParity(ChP) \ | 506 | #define sDisParity(ChP) \ |
516 | do { \ | 507 | do { \ |
517 | (ChP)->TxControl[2] &= ~PARITY_EN; \ | 508 | (ChP)->TxControl[2] &= ~PARITY_EN; \ |
518 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 509 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
519 | } while (0) | 510 | } while (0) |
520 | 511 | ||
521 | /*************************************************************************** | 512 | /*************************************************************************** |
@@ -527,7 +518,7 @@ Call: sDisRTSToggle(ChP) | |||
527 | #define sDisRTSToggle(ChP) \ | 518 | #define sDisRTSToggle(ChP) \ |
528 | do { \ | 519 | do { \ |
529 | (ChP)->TxControl[2] &= ~RTSTOG_EN; \ | 520 | (ChP)->TxControl[2] &= ~RTSTOG_EN; \ |
530 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 521 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
531 | (ChP)->rtsToggle = 0; \ | 522 | (ChP)->rtsToggle = 0; \ |
532 | } while (0) | 523 | } while (0) |
533 | 524 | ||
@@ -540,7 +531,7 @@ Call: sDisRxFIFO(ChP) | |||
540 | #define sDisRxFIFO(ChP) \ | 531 | #define sDisRxFIFO(ChP) \ |
541 | do { \ | 532 | do { \ |
542 | (ChP)->R[0x32] = 0x0a; \ | 533 | (ChP)->R[0x32] = 0x0a; \ |
543 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ | 534 | out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \ |
544 | } while (0) | 535 | } while (0) |
545 | 536 | ||
546 | /*************************************************************************** | 537 | /*************************************************************************** |
@@ -567,7 +558,7 @@ Call: sDisTransmit(ChP) | |||
567 | #define sDisTransmit(ChP) \ | 558 | #define sDisTransmit(ChP) \ |
568 | do { \ | 559 | do { \ |
569 | (ChP)->TxControl[3] &= ~TX_ENABLE; \ | 560 | (ChP)->TxControl[3] &= ~TX_ENABLE; \ |
570 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 561 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
571 | } while (0) | 562 | } while (0) |
572 | 563 | ||
573 | /*************************************************************************** | 564 | /*************************************************************************** |
@@ -579,7 +570,7 @@ Call: sDisTxSoftFlowCtl(ChP) | |||
579 | #define sDisTxSoftFlowCtl(ChP) \ | 570 | #define sDisTxSoftFlowCtl(ChP) \ |
580 | do { \ | 571 | do { \ |
581 | (ChP)->R[0x06] = 0x8a; \ | 572 | (ChP)->R[0x06] = 0x8a; \ |
582 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ | 573 | out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \ |
583 | } while (0) | 574 | } while (0) |
584 | 575 | ||
585 | /*************************************************************************** | 576 | /*************************************************************************** |
@@ -604,7 +595,7 @@ Call: sEnCTSFlowCtl(ChP) | |||
604 | #define sEnCTSFlowCtl(ChP) \ | 595 | #define sEnCTSFlowCtl(ChP) \ |
605 | do { \ | 596 | do { \ |
606 | (ChP)->TxControl[2] |= CTSFC_EN; \ | 597 | (ChP)->TxControl[2] |= CTSFC_EN; \ |
607 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 598 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
608 | } while (0) | 599 | } while (0) |
609 | 600 | ||
610 | /*************************************************************************** | 601 | /*************************************************************************** |
@@ -616,7 +607,7 @@ Call: sEnIXANY(ChP) | |||
616 | #define sEnIXANY(ChP) \ | 607 | #define sEnIXANY(ChP) \ |
617 | do { \ | 608 | do { \ |
618 | (ChP)->R[0x0e] = 0x21; \ | 609 | (ChP)->R[0x0e] = 0x21; \ |
619 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x0c]); \ | 610 | out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \ |
620 | } while (0) | 611 | } while (0) |
621 | 612 | ||
622 | /*************************************************************************** | 613 | /*************************************************************************** |
@@ -633,7 +624,7 @@ Warnings: Before enabling parity odd or even parity should be chosen using | |||
633 | #define sEnParity(ChP) \ | 624 | #define sEnParity(ChP) \ |
634 | do { \ | 625 | do { \ |
635 | (ChP)->TxControl[2] |= PARITY_EN; \ | 626 | (ChP)->TxControl[2] |= PARITY_EN; \ |
636 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 627 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
637 | } while (0) | 628 | } while (0) |
638 | 629 | ||
639 | /*************************************************************************** | 630 | /*************************************************************************** |
@@ -647,10 +638,10 @@ Comments: This function will disable RTS flow control and clear the RTS | |||
647 | #define sEnRTSToggle(ChP) \ | 638 | #define sEnRTSToggle(ChP) \ |
648 | do { \ | 639 | do { \ |
649 | (ChP)->RxControl[2] &= ~RTSFC_EN; \ | 640 | (ChP)->RxControl[2] &= ~RTSFC_EN; \ |
650 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ | 641 | out32((ChP)->IndexAddr,(ChP)->RxControl); \ |
651 | (ChP)->TxControl[2] |= RTSTOG_EN; \ | 642 | (ChP)->TxControl[2] |= RTSTOG_EN; \ |
652 | (ChP)->TxControl[3] &= ~SET_RTS; \ | 643 | (ChP)->TxControl[3] &= ~SET_RTS; \ |
653 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 644 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
654 | (ChP)->rtsToggle = 1; \ | 645 | (ChP)->rtsToggle = 1; \ |
655 | } while (0) | 646 | } while (0) |
656 | 647 | ||
@@ -663,7 +654,7 @@ Call: sEnRxFIFO(ChP) | |||
663 | #define sEnRxFIFO(ChP) \ | 654 | #define sEnRxFIFO(ChP) \ |
664 | do { \ | 655 | do { \ |
665 | (ChP)->R[0x32] = 0x08; \ | 656 | (ChP)->R[0x32] = 0x08; \ |
666 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \ | 657 | out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \ |
667 | } while (0) | 658 | } while (0) |
668 | 659 | ||
669 | /*************************************************************************** | 660 | /*************************************************************************** |
@@ -684,7 +675,7 @@ Warnings: This function must be called after valid microcode has been | |||
684 | #define sEnRxProcessor(ChP) \ | 675 | #define sEnRxProcessor(ChP) \ |
685 | do { \ | 676 | do { \ |
686 | (ChP)->RxControl[2] |= RXPROC_EN; \ | 677 | (ChP)->RxControl[2] |= RXPROC_EN; \ |
687 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ | 678 | out32((ChP)->IndexAddr,(ChP)->RxControl); \ |
688 | } while (0) | 679 | } while (0) |
689 | 680 | ||
690 | /*************************************************************************** | 681 | /*************************************************************************** |
@@ -708,7 +699,7 @@ Call: sEnTransmit(ChP) | |||
708 | #define sEnTransmit(ChP) \ | 699 | #define sEnTransmit(ChP) \ |
709 | do { \ | 700 | do { \ |
710 | (ChP)->TxControl[3] |= TX_ENABLE; \ | 701 | (ChP)->TxControl[3] |= TX_ENABLE; \ |
711 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 702 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
712 | } while (0) | 703 | } while (0) |
713 | 704 | ||
714 | /*************************************************************************** | 705 | /*************************************************************************** |
@@ -720,7 +711,7 @@ Call: sEnTxSoftFlowCtl(ChP) | |||
720 | #define sEnTxSoftFlowCtl(ChP) \ | 711 | #define sEnTxSoftFlowCtl(ChP) \ |
721 | do { \ | 712 | do { \ |
722 | (ChP)->R[0x06] = 0xc5; \ | 713 | (ChP)->R[0x06] = 0xc5; \ |
723 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ | 714 | out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \ |
724 | } while (0) | 715 | } while (0) |
725 | 716 | ||
726 | /*************************************************************************** | 717 | /*************************************************************************** |
@@ -927,7 +918,7 @@ Call: sSendBreak(ChP) | |||
927 | #define sSendBreak(ChP) \ | 918 | #define sSendBreak(ChP) \ |
928 | do { \ | 919 | do { \ |
929 | (ChP)->TxControl[3] |= SETBREAK; \ | 920 | (ChP)->TxControl[3] |= SETBREAK; \ |
930 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 921 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
931 | } while (0) | 922 | } while (0) |
932 | 923 | ||
933 | /*************************************************************************** | 924 | /*************************************************************************** |
@@ -941,7 +932,7 @@ Call: sSetBaud(ChP,Divisor) | |||
941 | do { \ | 932 | do { \ |
942 | (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ | 933 | (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \ |
943 | (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ | 934 | (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \ |
944 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \ | 935 | out32((ChP)->IndexAddr,(ChP)->BaudDiv); \ |
945 | } while (0) | 936 | } while (0) |
946 | 937 | ||
947 | /*************************************************************************** | 938 | /*************************************************************************** |
@@ -953,7 +944,7 @@ Call: sSetData7(ChP) | |||
953 | #define sSetData7(ChP) \ | 944 | #define sSetData7(ChP) \ |
954 | do { \ | 945 | do { \ |
955 | (ChP)->TxControl[2] &= ~DATA8BIT; \ | 946 | (ChP)->TxControl[2] &= ~DATA8BIT; \ |
956 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 947 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
957 | } while (0) | 948 | } while (0) |
958 | 949 | ||
959 | /*************************************************************************** | 950 | /*************************************************************************** |
@@ -965,7 +956,7 @@ Call: sSetData8(ChP) | |||
965 | #define sSetData8(ChP) \ | 956 | #define sSetData8(ChP) \ |
966 | do { \ | 957 | do { \ |
967 | (ChP)->TxControl[2] |= DATA8BIT; \ | 958 | (ChP)->TxControl[2] |= DATA8BIT; \ |
968 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 959 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
969 | } while (0) | 960 | } while (0) |
970 | 961 | ||
971 | /*************************************************************************** | 962 | /*************************************************************************** |
@@ -977,7 +968,7 @@ Call: sSetDTR(ChP) | |||
977 | #define sSetDTR(ChP) \ | 968 | #define sSetDTR(ChP) \ |
978 | do { \ | 969 | do { \ |
979 | (ChP)->TxControl[3] |= SET_DTR; \ | 970 | (ChP)->TxControl[3] |= SET_DTR; \ |
980 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 971 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
981 | } while (0) | 972 | } while (0) |
982 | 973 | ||
983 | /*************************************************************************** | 974 | /*************************************************************************** |
@@ -994,7 +985,7 @@ Warnings: This function has no effect unless parity is enabled with function | |||
994 | #define sSetEvenParity(ChP) \ | 985 | #define sSetEvenParity(ChP) \ |
995 | do { \ | 986 | do { \ |
996 | (ChP)->TxControl[2] |= EVEN_PAR; \ | 987 | (ChP)->TxControl[2] |= EVEN_PAR; \ |
997 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 988 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
998 | } while (0) | 989 | } while (0) |
999 | 990 | ||
1000 | /*************************************************************************** | 991 | /*************************************************************************** |
@@ -1011,7 +1002,7 @@ Warnings: This function has no effect unless parity is enabled with function | |||
1011 | #define sSetOddParity(ChP) \ | 1002 | #define sSetOddParity(ChP) \ |
1012 | do { \ | 1003 | do { \ |
1013 | (ChP)->TxControl[2] &= ~EVEN_PAR; \ | 1004 | (ChP)->TxControl[2] &= ~EVEN_PAR; \ |
1014 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 1005 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
1015 | } while (0) | 1006 | } while (0) |
1016 | 1007 | ||
1017 | /*************************************************************************** | 1008 | /*************************************************************************** |
@@ -1024,7 +1015,7 @@ Call: sSetRTS(ChP) | |||
1024 | do { \ | 1015 | do { \ |
1025 | if ((ChP)->rtsToggle) break; \ | 1016 | if ((ChP)->rtsToggle) break; \ |
1026 | (ChP)->TxControl[3] |= SET_RTS; \ | 1017 | (ChP)->TxControl[3] |= SET_RTS; \ |
1027 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 1018 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
1028 | } while (0) | 1019 | } while (0) |
1029 | 1020 | ||
1030 | /*************************************************************************** | 1021 | /*************************************************************************** |
@@ -1050,7 +1041,7 @@ Comments: An interrupt will be generated when the trigger level is reached | |||
1050 | do { \ | 1041 | do { \ |
1051 | (ChP)->RxControl[2] &= ~TRIG_MASK; \ | 1042 | (ChP)->RxControl[2] &= ~TRIG_MASK; \ |
1052 | (ChP)->RxControl[2] |= LEVEL; \ | 1043 | (ChP)->RxControl[2] |= LEVEL; \ |
1053 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \ | 1044 | out32((ChP)->IndexAddr,(ChP)->RxControl); \ |
1054 | } while (0) | 1045 | } while (0) |
1055 | 1046 | ||
1056 | /*************************************************************************** | 1047 | /*************************************************************************** |
@@ -1062,7 +1053,7 @@ Call: sSetStop1(ChP) | |||
1062 | #define sSetStop1(ChP) \ | 1053 | #define sSetStop1(ChP) \ |
1063 | do { \ | 1054 | do { \ |
1064 | (ChP)->TxControl[2] &= ~STOP2; \ | 1055 | (ChP)->TxControl[2] &= ~STOP2; \ |
1065 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 1056 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
1066 | } while (0) | 1057 | } while (0) |
1067 | 1058 | ||
1068 | /*************************************************************************** | 1059 | /*************************************************************************** |
@@ -1074,7 +1065,7 @@ Call: sSetStop2(ChP) | |||
1074 | #define sSetStop2(ChP) \ | 1065 | #define sSetStop2(ChP) \ |
1075 | do { \ | 1066 | do { \ |
1076 | (ChP)->TxControl[2] |= STOP2; \ | 1067 | (ChP)->TxControl[2] |= STOP2; \ |
1077 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \ | 1068 | out32((ChP)->IndexAddr,(ChP)->TxControl); \ |
1078 | } while (0) | 1069 | } while (0) |
1079 | 1070 | ||
1080 | /*************************************************************************** | 1071 | /*************************************************************************** |
@@ -1087,7 +1078,7 @@ Call: sSetTxXOFFChar(ChP,Ch) | |||
1087 | #define sSetTxXOFFChar(ChP,CH) \ | 1078 | #define sSetTxXOFFChar(ChP,CH) \ |
1088 | do { \ | 1079 | do { \ |
1089 | (ChP)->R[0x07] = (CH); \ | 1080 | (ChP)->R[0x07] = (CH); \ |
1090 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \ | 1081 | out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \ |
1091 | } while (0) | 1082 | } while (0) |
1092 | 1083 | ||
1093 | /*************************************************************************** | 1084 | /*************************************************************************** |
@@ -1100,7 +1091,7 @@ Call: sSetTxXONChar(ChP,Ch) | |||
1100 | #define sSetTxXONChar(ChP,CH) \ | 1091 | #define sSetTxXONChar(ChP,CH) \ |
1101 | do { \ | 1092 | do { \ |
1102 | (ChP)->R[0x0b] = (CH); \ | 1093 | (ChP)->R[0x0b] = (CH); \ |
1103 | sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x08]); \ | 1094 | out32((ChP)->IndexAddr,&(ChP)->R[0x08]); \ |
1104 | } while (0) | 1095 | } while (0) |
1105 | 1096 | ||
1106 | /*************************************************************************** | 1097 | /*************************************************************************** |
@@ -1113,7 +1104,7 @@ Comments: This function is used to start a Rx processor after it was | |||
1113 | will restart both the Rx processor and software input flow control. | 1104 | will restart both the Rx processor and software input flow control. |
1114 | 1105 | ||
1115 | */ | 1106 | */ |
1116 | #define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0]) | 1107 | #define sStartRxProcessor(ChP) out32((ChP)->IndexAddr,&(ChP)->R[0]) |
1117 | 1108 | ||
1118 | /*************************************************************************** | 1109 | /*************************************************************************** |
1119 | Function: sWriteTxByte | 1110 | Function: sWriteTxByte |