diff options
author | Borislav Petkov <borislav.petkov@amd.com> | 2009-10-09 13:14:43 -0400 |
---|---|---|
committer | Borislav Petkov <borislav.petkov@amd.com> | 2009-12-07 13:14:26 -0500 |
commit | 72381bd55e4ce2aaed8660551e8f56a2c959c11f (patch) | |
tree | c727201496a65f6c8c6434aec9c9a3af30160e11 /drivers | |
parent | 6ec22f9b037fc0c2e00ddb7023fad279c365324d (diff) |
amd64_edac: clarify DRAM CTL debug reporting
Make debug info formulations about the DRAM and DCT configuration of the
machine more human readable.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/edac/amd64_edac.c | 37 |
1 files changed, 23 insertions, 14 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index a38831c82649..0252a61f3d26 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c | |||
@@ -1402,27 +1402,36 @@ static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) | |||
1402 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW, | 1402 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW, |
1403 | &pvt->dram_ctl_select_low); | 1403 | &pvt->dram_ctl_select_low); |
1404 | if (err) { | 1404 | if (err) { |
1405 | debugf0("Reading F10_DCTL_SEL_LOW failed\n"); | 1405 | debugf0("Reading F2x110 (DCTL Sel. Low) failed\n"); |
1406 | } else { | 1406 | } else { |
1407 | debugf0("DRAM_DCTL_SEL_LOW=0x%x DctSelBaseAddr=0x%x\n", | 1407 | debugf0("F2x110 (DCTL Sel. Low): 0x%08x, " |
1408 | pvt->dram_ctl_select_low, dct_sel_baseaddr(pvt)); | 1408 | "High range addresses at: 0x%x\n", |
1409 | 1409 | pvt->dram_ctl_select_low, | |
1410 | debugf0(" DRAM DCTs are=%s DRAM Is=%s DRAM-Ctl-" | 1410 | dct_sel_baseaddr(pvt)); |
1411 | "sel-hi-range=%s\n", | 1411 | |
1412 | (dct_ganging_enabled(pvt) ? "GANGED" : "NOT GANGED"), | 1412 | debugf0(" DCT mode: %s, All DCTs on: %s\n", |
1413 | (dct_dram_enabled(pvt) ? "Enabled" : "Disabled"), | 1413 | (dct_ganging_enabled(pvt) ? "ganged" : "unganged"), |
1414 | (dct_high_range_enabled(pvt) ? "Enabled" : "Disabled")); | 1414 | (dct_dram_enabled(pvt) ? "yes" : "no")); |
1415 | 1415 | ||
1416 | debugf0(" DctDatIntLv=%s MemCleared=%s DctSelIntLvAddr=0x%x\n", | 1416 | if (!dct_ganging_enabled(pvt)) |
1417 | (dct_data_intlv_enabled(pvt) ? "Enabled" : "Disabled"), | 1417 | debugf0(" Address range split per DCT: %s\n", |
1418 | (dct_memory_cleared(pvt) ? "True " : "False "), | 1418 | (dct_high_range_enabled(pvt) ? "yes" : "no")); |
1419 | |||
1420 | debugf0(" DCT data interleave for ECC: %s, " | ||
1421 | "DRAM cleared since last warm reset: %s\n", | ||
1422 | (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), | ||
1423 | (dct_memory_cleared(pvt) ? "yes" : "no")); | ||
1424 | |||
1425 | debugf0(" DCT channel interleave: %s, " | ||
1426 | "DCT interleave bits selector: 0x%x\n", | ||
1427 | (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), | ||
1419 | dct_sel_interleave_addr(pvt)); | 1428 | dct_sel_interleave_addr(pvt)); |
1420 | } | 1429 | } |
1421 | 1430 | ||
1422 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH, | 1431 | err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH, |
1423 | &pvt->dram_ctl_select_high); | 1432 | &pvt->dram_ctl_select_high); |
1424 | if (err) | 1433 | if (err) |
1425 | debugf0("Reading F10_DCTL_SEL_HIGH failed\n"); | 1434 | debugf0("Reading F2x114 (DCT Sel. High) failed\n"); |
1426 | } | 1435 | } |
1427 | 1436 | ||
1428 | /* | 1437 | /* |