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authorMathias Fröhlich <Mathias.Froehlich@web.de>2009-10-19 12:50:41 -0400
committerDave Airlie <airlied@redhat.com>2009-10-25 23:28:19 -0400
commitceb776bc87280eb8d13f38e4d7afae757e95af44 (patch)
treeecc62b9bf5f3563a0fe30227e04f3226e7477059 /drivers
parentc850cb782626fda78e5e9e5baf18a5bd806a225c (diff)
drm/radeon/kms: fix cs parser tex bit 11 check
The problem boils down to the order when the bit11 of the texture size is or'ed to the original width. In the end each mipmap level has the same width or height because of that 11 bit is ored to the scaled down lod with and thus blows up the size again to the full size or more due to the power of two rounding afterwards. The attached patch changes this order so that the texture sizes are computed correct. Also the on error the yet missing inputs to the size computation are printed which helped me to find out where it really breaks. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/radeon/r100.c9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index c22adff179a9..ed5e983d21e9 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2548,8 +2548,11 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2548static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2548static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2549{ 2549{
2550 DRM_ERROR("pitch %d\n", t->pitch); 2550 DRM_ERROR("pitch %d\n", t->pitch);
2551 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2551 DRM_ERROR("width %d\n", t->width); 2552 DRM_ERROR("width %d\n", t->width);
2553 DRM_ERROR("width_11 %d\n", t->width_11);
2552 DRM_ERROR("height %d\n", t->height); 2554 DRM_ERROR("height %d\n", t->height);
2555 DRM_ERROR("height_11 %d\n", t->height_11);
2553 DRM_ERROR("num levels %d\n", t->num_levels); 2556 DRM_ERROR("num levels %d\n", t->num_levels);
2554 DRM_ERROR("depth %d\n", t->txdepth); 2557 DRM_ERROR("depth %d\n", t->txdepth);
2555 DRM_ERROR("bpp %d\n", t->cpp); 2558 DRM_ERROR("bpp %d\n", t->cpp);
@@ -2609,15 +2612,17 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
2609 else 2612 else
2610 w = track->textures[u].pitch / (1 << i); 2613 w = track->textures[u].pitch / (1 << i);
2611 } else { 2614 } else {
2612 w = track->textures[u].width / (1 << i); 2615 w = track->textures[u].width;
2613 if (rdev->family >= CHIP_RV515) 2616 if (rdev->family >= CHIP_RV515)
2614 w |= track->textures[u].width_11; 2617 w |= track->textures[u].width_11;
2618 w = w / (1 << i);
2615 if (track->textures[u].roundup_w) 2619 if (track->textures[u].roundup_w)
2616 w = roundup_pow_of_two(w); 2620 w = roundup_pow_of_two(w);
2617 } 2621 }
2618 h = track->textures[u].height / (1 << i); 2622 h = track->textures[u].height;
2619 if (rdev->family >= CHIP_RV515) 2623 if (rdev->family >= CHIP_RV515)
2620 h |= track->textures[u].height_11; 2624 h |= track->textures[u].height_11;
2625 h = h / (1 << i);
2621 if (track->textures[u].roundup_h) 2626 if (track->textures[u].roundup_h)
2622 h = roundup_pow_of_two(h); 2627 h = roundup_pow_of_two(h);
2623 size += w * h; 2628 size += w * h;