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authorBen Hutchings <bhutchings@solarflare.com>2009-11-28 22:42:03 -0500
committerDavid S. Miller <davem@davemloft.net>2009-11-29 19:46:25 -0500
commit39e60212087a36a53daca3904563012ccaf6e92d (patch)
tree563aa14ce6a8b151c3e424fa1d2beab30171cb5c /drivers
parent3291b9db567e1ec38362024049cbd02987b1e277 (diff)
sfc: Remove redundant writes to INT_ADR_KER
This register only needs to be written after reset, not each time we enable interrupts. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/sfc/falcon.c15
1 files changed, 7 insertions, 8 deletions
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index 2f219ce61392..b7e9238aaec4 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -1290,19 +1290,11 @@ static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1290 1290
1291void falcon_enable_interrupts(struct efx_nic *efx) 1291void falcon_enable_interrupts(struct efx_nic *efx)
1292{ 1292{
1293 efx_oword_t int_adr_reg_ker;
1294 struct efx_channel *channel; 1293 struct efx_channel *channel;
1295 1294
1296 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr)); 1295 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1297 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */ 1296 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1298 1297
1299 /* Program address */
1300 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1301 FRF_AZ_NORM_INT_VEC_DIS_KER,
1302 EFX_INT_MODE_USE_MSI(efx),
1303 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1304 efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1305
1306 /* Enable interrupts */ 1298 /* Enable interrupts */
1307 falcon_interrupts(efx, 1, 0); 1299 falcon_interrupts(efx, 1, 0);
1308 1300
@@ -3061,6 +3053,13 @@ int falcon_init_nic(struct efx_nic *efx)
3061 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8); 3053 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3062 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM); 3054 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
3063 3055
3056 /* Program INT_KER address */
3057 EFX_POPULATE_OWORD_2(temp,
3058 FRF_AZ_NORM_INT_VEC_DIS_KER,
3059 EFX_INT_MODE_USE_MSI(efx),
3060 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
3061 efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
3062
3064 /* Clear the parity enables on the TX data fifos as 3063 /* Clear the parity enables on the TX data fifos as
3065 * they produce false parity errors because of timing issues 3064 * they produce false parity errors because of timing issues
3066 */ 3065 */