diff options
author | Harvey Harrison <harvey.harrison@gmail.com> | 2009-01-19 01:03:01 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-01-21 17:34:08 -0500 |
commit | 649aa95d75cbadb9f440c1b8d04c666461de326f (patch) | |
tree | cf330cb0ecddde1bc09649f12903e9b62640d0dc /drivers | |
parent | da3bc07171dff957906cbe2ad5abb443eccf57c4 (diff) |
typhoon: replace users of __constant_{endian}
The base versions handle constant folding just fine, use them
directly.
Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com>
Acked-by: David Dillow <dave@thedillows.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/typhoon.c | 2 | ||||
-rw-r--r-- | drivers/net/typhoon.h | 234 |
2 files changed, 118 insertions, 118 deletions
diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c index dcff5ade6d08..a8e5651f3165 100644 --- a/drivers/net/typhoon.c +++ b/drivers/net/typhoon.c | |||
@@ -1944,7 +1944,7 @@ typhoon_start_runtime(struct typhoon *tp) | |||
1944 | goto error_out; | 1944 | goto error_out; |
1945 | 1945 | ||
1946 | INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE); | 1946 | INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE); |
1947 | xp_cmd.parm1 = __constant_cpu_to_le16(ETH_P_8021Q); | 1947 | xp_cmd.parm1 = cpu_to_le16(ETH_P_8021Q); |
1948 | err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL); | 1948 | err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL); |
1949 | if(err < 0) | 1949 | if(err < 0) |
1950 | goto error_out; | 1950 | goto error_out; |
diff --git a/drivers/net/typhoon.h b/drivers/net/typhoon.h index dd7022ca7354..673fd5125914 100644 --- a/drivers/net/typhoon.h +++ b/drivers/net/typhoon.h | |||
@@ -174,18 +174,18 @@ struct tx_desc { | |||
174 | u64 tx_addr; /* opaque for hardware, for TX_DESC */ | 174 | u64 tx_addr; /* opaque for hardware, for TX_DESC */ |
175 | }; | 175 | }; |
176 | __le32 processFlags; | 176 | __le32 processFlags; |
177 | #define TYPHOON_TX_PF_NO_CRC __constant_cpu_to_le32(0x00000001) | 177 | #define TYPHOON_TX_PF_NO_CRC cpu_to_le32(0x00000001) |
178 | #define TYPHOON_TX_PF_IP_CHKSUM __constant_cpu_to_le32(0x00000002) | 178 | #define TYPHOON_TX_PF_IP_CHKSUM cpu_to_le32(0x00000002) |
179 | #define TYPHOON_TX_PF_TCP_CHKSUM __constant_cpu_to_le32(0x00000004) | 179 | #define TYPHOON_TX_PF_TCP_CHKSUM cpu_to_le32(0x00000004) |
180 | #define TYPHOON_TX_PF_TCP_SEGMENT __constant_cpu_to_le32(0x00000008) | 180 | #define TYPHOON_TX_PF_TCP_SEGMENT cpu_to_le32(0x00000008) |
181 | #define TYPHOON_TX_PF_INSERT_VLAN __constant_cpu_to_le32(0x00000010) | 181 | #define TYPHOON_TX_PF_INSERT_VLAN cpu_to_le32(0x00000010) |
182 | #define TYPHOON_TX_PF_IPSEC __constant_cpu_to_le32(0x00000020) | 182 | #define TYPHOON_TX_PF_IPSEC cpu_to_le32(0x00000020) |
183 | #define TYPHOON_TX_PF_VLAN_PRIORITY __constant_cpu_to_le32(0x00000040) | 183 | #define TYPHOON_TX_PF_VLAN_PRIORITY cpu_to_le32(0x00000040) |
184 | #define TYPHOON_TX_PF_UDP_CHKSUM __constant_cpu_to_le32(0x00000080) | 184 | #define TYPHOON_TX_PF_UDP_CHKSUM cpu_to_le32(0x00000080) |
185 | #define TYPHOON_TX_PF_PAD_FRAME __constant_cpu_to_le32(0x00000100) | 185 | #define TYPHOON_TX_PF_PAD_FRAME cpu_to_le32(0x00000100) |
186 | #define TYPHOON_TX_PF_RESERVED __constant_cpu_to_le32(0x00000e00) | 186 | #define TYPHOON_TX_PF_RESERVED cpu_to_le32(0x00000e00) |
187 | #define TYPHOON_TX_PF_VLAN_MASK __constant_cpu_to_le32(0x0ffff000) | 187 | #define TYPHOON_TX_PF_VLAN_MASK cpu_to_le32(0x0ffff000) |
188 | #define TYPHOON_TX_PF_INTERNAL __constant_cpu_to_le32(0xf0000000) | 188 | #define TYPHOON_TX_PF_INTERNAL cpu_to_le32(0xf0000000) |
189 | #define TYPHOON_TX_PF_VLAN_TAG_SHIFT 12 | 189 | #define TYPHOON_TX_PF_VLAN_TAG_SHIFT 12 |
190 | } __attribute__ ((packed)); | 190 | } __attribute__ ((packed)); |
191 | 191 | ||
@@ -203,8 +203,8 @@ struct tcpopt_desc { | |||
203 | u8 flags; | 203 | u8 flags; |
204 | u8 numDesc; | 204 | u8 numDesc; |
205 | __le16 mss_flags; | 205 | __le16 mss_flags; |
206 | #define TYPHOON_TSO_FIRST __constant_cpu_to_le16(0x1000) | 206 | #define TYPHOON_TSO_FIRST cpu_to_le16(0x1000) |
207 | #define TYPHOON_TSO_LAST __constant_cpu_to_le16(0x2000) | 207 | #define TYPHOON_TSO_LAST cpu_to_le16(0x2000) |
208 | __le32 respAddrLo; | 208 | __le32 respAddrLo; |
209 | __le32 bytesTx; | 209 | __le32 bytesTx; |
210 | __le32 status; | 210 | __le32 status; |
@@ -222,8 +222,8 @@ struct ipsec_desc { | |||
222 | u8 flags; | 222 | u8 flags; |
223 | u8 numDesc; | 223 | u8 numDesc; |
224 | __le16 ipsecFlags; | 224 | __le16 ipsecFlags; |
225 | #define TYPHOON_IPSEC_GEN_IV __constant_cpu_to_le16(0x0000) | 225 | #define TYPHOON_IPSEC_GEN_IV cpu_to_le16(0x0000) |
226 | #define TYPHOON_IPSEC_USE_IV __constant_cpu_to_le16(0x0001) | 226 | #define TYPHOON_IPSEC_USE_IV cpu_to_le16(0x0001) |
227 | __le32 sa1; | 227 | __le32 sa1; |
228 | __le32 sa2; | 228 | __le32 sa2; |
229 | __le32 reserved; | 229 | __le32 reserved; |
@@ -248,41 +248,41 @@ struct rx_desc { | |||
248 | u32 addr; /* opaque, comes from virtAddr */ | 248 | u32 addr; /* opaque, comes from virtAddr */ |
249 | u32 addrHi; /* opaque, comes from virtAddrHi */ | 249 | u32 addrHi; /* opaque, comes from virtAddrHi */ |
250 | __le32 rxStatus; | 250 | __le32 rxStatus; |
251 | #define TYPHOON_RX_ERR_INTERNAL __constant_cpu_to_le32(0x00000000) | 251 | #define TYPHOON_RX_ERR_INTERNAL cpu_to_le32(0x00000000) |
252 | #define TYPHOON_RX_ERR_FIFO_UNDERRUN __constant_cpu_to_le32(0x00000001) | 252 | #define TYPHOON_RX_ERR_FIFO_UNDERRUN cpu_to_le32(0x00000001) |
253 | #define TYPHOON_RX_ERR_BAD_SSD __constant_cpu_to_le32(0x00000002) | 253 | #define TYPHOON_RX_ERR_BAD_SSD cpu_to_le32(0x00000002) |
254 | #define TYPHOON_RX_ERR_RUNT __constant_cpu_to_le32(0x00000003) | 254 | #define TYPHOON_RX_ERR_RUNT cpu_to_le32(0x00000003) |
255 | #define TYPHOON_RX_ERR_CRC __constant_cpu_to_le32(0x00000004) | 255 | #define TYPHOON_RX_ERR_CRC cpu_to_le32(0x00000004) |
256 | #define TYPHOON_RX_ERR_OVERSIZE __constant_cpu_to_le32(0x00000005) | 256 | #define TYPHOON_RX_ERR_OVERSIZE cpu_to_le32(0x00000005) |
257 | #define TYPHOON_RX_ERR_ALIGN __constant_cpu_to_le32(0x00000006) | 257 | #define TYPHOON_RX_ERR_ALIGN cpu_to_le32(0x00000006) |
258 | #define TYPHOON_RX_ERR_DRIBBLE __constant_cpu_to_le32(0x00000007) | 258 | #define TYPHOON_RX_ERR_DRIBBLE cpu_to_le32(0x00000007) |
259 | #define TYPHOON_RX_PROTO_MASK __constant_cpu_to_le32(0x00000003) | 259 | #define TYPHOON_RX_PROTO_MASK cpu_to_le32(0x00000003) |
260 | #define TYPHOON_RX_PROTO_UNKNOWN __constant_cpu_to_le32(0x00000000) | 260 | #define TYPHOON_RX_PROTO_UNKNOWN cpu_to_le32(0x00000000) |
261 | #define TYPHOON_RX_PROTO_IP __constant_cpu_to_le32(0x00000001) | 261 | #define TYPHOON_RX_PROTO_IP cpu_to_le32(0x00000001) |
262 | #define TYPHOON_RX_PROTO_IPX __constant_cpu_to_le32(0x00000002) | 262 | #define TYPHOON_RX_PROTO_IPX cpu_to_le32(0x00000002) |
263 | #define TYPHOON_RX_VLAN __constant_cpu_to_le32(0x00000004) | 263 | #define TYPHOON_RX_VLAN cpu_to_le32(0x00000004) |
264 | #define TYPHOON_RX_IP_FRAG __constant_cpu_to_le32(0x00000008) | 264 | #define TYPHOON_RX_IP_FRAG cpu_to_le32(0x00000008) |
265 | #define TYPHOON_RX_IPSEC __constant_cpu_to_le32(0x00000010) | 265 | #define TYPHOON_RX_IPSEC cpu_to_le32(0x00000010) |
266 | #define TYPHOON_RX_IP_CHK_FAIL __constant_cpu_to_le32(0x00000020) | 266 | #define TYPHOON_RX_IP_CHK_FAIL cpu_to_le32(0x00000020) |
267 | #define TYPHOON_RX_TCP_CHK_FAIL __constant_cpu_to_le32(0x00000040) | 267 | #define TYPHOON_RX_TCP_CHK_FAIL cpu_to_le32(0x00000040) |
268 | #define TYPHOON_RX_UDP_CHK_FAIL __constant_cpu_to_le32(0x00000080) | 268 | #define TYPHOON_RX_UDP_CHK_FAIL cpu_to_le32(0x00000080) |
269 | #define TYPHOON_RX_IP_CHK_GOOD __constant_cpu_to_le32(0x00000100) | 269 | #define TYPHOON_RX_IP_CHK_GOOD cpu_to_le32(0x00000100) |
270 | #define TYPHOON_RX_TCP_CHK_GOOD __constant_cpu_to_le32(0x00000200) | 270 | #define TYPHOON_RX_TCP_CHK_GOOD cpu_to_le32(0x00000200) |
271 | #define TYPHOON_RX_UDP_CHK_GOOD __constant_cpu_to_le32(0x00000400) | 271 | #define TYPHOON_RX_UDP_CHK_GOOD cpu_to_le32(0x00000400) |
272 | __le16 filterResults; | 272 | __le16 filterResults; |
273 | #define TYPHOON_RX_FILTER_MASK __constant_cpu_to_le16(0x7fff) | 273 | #define TYPHOON_RX_FILTER_MASK cpu_to_le16(0x7fff) |
274 | #define TYPHOON_RX_FILTERED __constant_cpu_to_le16(0x8000) | 274 | #define TYPHOON_RX_FILTERED cpu_to_le16(0x8000) |
275 | __le16 ipsecResults; | 275 | __le16 ipsecResults; |
276 | #define TYPHOON_RX_OUTER_AH_GOOD __constant_cpu_to_le16(0x0001) | 276 | #define TYPHOON_RX_OUTER_AH_GOOD cpu_to_le16(0x0001) |
277 | #define TYPHOON_RX_OUTER_ESP_GOOD __constant_cpu_to_le16(0x0002) | 277 | #define TYPHOON_RX_OUTER_ESP_GOOD cpu_to_le16(0x0002) |
278 | #define TYPHOON_RX_INNER_AH_GOOD __constant_cpu_to_le16(0x0004) | 278 | #define TYPHOON_RX_INNER_AH_GOOD cpu_to_le16(0x0004) |
279 | #define TYPHOON_RX_INNER_ESP_GOOD __constant_cpu_to_le16(0x0008) | 279 | #define TYPHOON_RX_INNER_ESP_GOOD cpu_to_le16(0x0008) |
280 | #define TYPHOON_RX_OUTER_AH_FAIL __constant_cpu_to_le16(0x0010) | 280 | #define TYPHOON_RX_OUTER_AH_FAIL cpu_to_le16(0x0010) |
281 | #define TYPHOON_RX_OUTER_ESP_FAIL __constant_cpu_to_le16(0x0020) | 281 | #define TYPHOON_RX_OUTER_ESP_FAIL cpu_to_le16(0x0020) |
282 | #define TYPHOON_RX_INNER_AH_FAIL __constant_cpu_to_le16(0x0040) | 282 | #define TYPHOON_RX_INNER_AH_FAIL cpu_to_le16(0x0040) |
283 | #define TYPHOON_RX_INNER_ESP_FAIL __constant_cpu_to_le16(0x0080) | 283 | #define TYPHOON_RX_INNER_ESP_FAIL cpu_to_le16(0x0080) |
284 | #define TYPHOON_RX_UNKNOWN_SA __constant_cpu_to_le16(0x0100) | 284 | #define TYPHOON_RX_UNKNOWN_SA cpu_to_le16(0x0100) |
285 | #define TYPHOON_RX_ESP_FORMAT_ERR __constant_cpu_to_le16(0x0200) | 285 | #define TYPHOON_RX_ESP_FORMAT_ERR cpu_to_le16(0x0200) |
286 | __be32 vlanTag; | 286 | __be32 vlanTag; |
287 | } __attribute__ ((packed)); | 287 | } __attribute__ ((packed)); |
288 | 288 | ||
@@ -318,31 +318,31 @@ struct cmd_desc { | |||
318 | u8 flags; | 318 | u8 flags; |
319 | u8 numDesc; | 319 | u8 numDesc; |
320 | __le16 cmd; | 320 | __le16 cmd; |
321 | #define TYPHOON_CMD_TX_ENABLE __constant_cpu_to_le16(0x0001) | 321 | #define TYPHOON_CMD_TX_ENABLE cpu_to_le16(0x0001) |
322 | #define TYPHOON_CMD_TX_DISABLE __constant_cpu_to_le16(0x0002) | 322 | #define TYPHOON_CMD_TX_DISABLE cpu_to_le16(0x0002) |
323 | #define TYPHOON_CMD_RX_ENABLE __constant_cpu_to_le16(0x0003) | 323 | #define TYPHOON_CMD_RX_ENABLE cpu_to_le16(0x0003) |
324 | #define TYPHOON_CMD_RX_DISABLE __constant_cpu_to_le16(0x0004) | 324 | #define TYPHOON_CMD_RX_DISABLE cpu_to_le16(0x0004) |
325 | #define TYPHOON_CMD_SET_RX_FILTER __constant_cpu_to_le16(0x0005) | 325 | #define TYPHOON_CMD_SET_RX_FILTER cpu_to_le16(0x0005) |
326 | #define TYPHOON_CMD_READ_STATS __constant_cpu_to_le16(0x0007) | 326 | #define TYPHOON_CMD_READ_STATS cpu_to_le16(0x0007) |
327 | #define TYPHOON_CMD_XCVR_SELECT __constant_cpu_to_le16(0x0013) | 327 | #define TYPHOON_CMD_XCVR_SELECT cpu_to_le16(0x0013) |
328 | #define TYPHOON_CMD_SET_MAX_PKT_SIZE __constant_cpu_to_le16(0x001a) | 328 | #define TYPHOON_CMD_SET_MAX_PKT_SIZE cpu_to_le16(0x001a) |
329 | #define TYPHOON_CMD_READ_MEDIA_STATUS __constant_cpu_to_le16(0x001b) | 329 | #define TYPHOON_CMD_READ_MEDIA_STATUS cpu_to_le16(0x001b) |
330 | #define TYPHOON_CMD_GOTO_SLEEP __constant_cpu_to_le16(0x0023) | 330 | #define TYPHOON_CMD_GOTO_SLEEP cpu_to_le16(0x0023) |
331 | #define TYPHOON_CMD_SET_MULTICAST_HASH __constant_cpu_to_le16(0x0025) | 331 | #define TYPHOON_CMD_SET_MULTICAST_HASH cpu_to_le16(0x0025) |
332 | #define TYPHOON_CMD_SET_MAC_ADDRESS __constant_cpu_to_le16(0x0026) | 332 | #define TYPHOON_CMD_SET_MAC_ADDRESS cpu_to_le16(0x0026) |
333 | #define TYPHOON_CMD_READ_MAC_ADDRESS __constant_cpu_to_le16(0x0027) | 333 | #define TYPHOON_CMD_READ_MAC_ADDRESS cpu_to_le16(0x0027) |
334 | #define TYPHOON_CMD_VLAN_TYPE_WRITE __constant_cpu_to_le16(0x002b) | 334 | #define TYPHOON_CMD_VLAN_TYPE_WRITE cpu_to_le16(0x002b) |
335 | #define TYPHOON_CMD_CREATE_SA __constant_cpu_to_le16(0x0034) | 335 | #define TYPHOON_CMD_CREATE_SA cpu_to_le16(0x0034) |
336 | #define TYPHOON_CMD_DELETE_SA __constant_cpu_to_le16(0x0035) | 336 | #define TYPHOON_CMD_DELETE_SA cpu_to_le16(0x0035) |
337 | #define TYPHOON_CMD_READ_VERSIONS __constant_cpu_to_le16(0x0043) | 337 | #define TYPHOON_CMD_READ_VERSIONS cpu_to_le16(0x0043) |
338 | #define TYPHOON_CMD_IRQ_COALESCE_CTRL __constant_cpu_to_le16(0x0045) | 338 | #define TYPHOON_CMD_IRQ_COALESCE_CTRL cpu_to_le16(0x0045) |
339 | #define TYPHOON_CMD_ENABLE_WAKE_EVENTS __constant_cpu_to_le16(0x0049) | 339 | #define TYPHOON_CMD_ENABLE_WAKE_EVENTS cpu_to_le16(0x0049) |
340 | #define TYPHOON_CMD_SET_OFFLOAD_TASKS __constant_cpu_to_le16(0x004f) | 340 | #define TYPHOON_CMD_SET_OFFLOAD_TASKS cpu_to_le16(0x004f) |
341 | #define TYPHOON_CMD_HELLO_RESP __constant_cpu_to_le16(0x0057) | 341 | #define TYPHOON_CMD_HELLO_RESP cpu_to_le16(0x0057) |
342 | #define TYPHOON_CMD_HALT __constant_cpu_to_le16(0x005d) | 342 | #define TYPHOON_CMD_HALT cpu_to_le16(0x005d) |
343 | #define TYPHOON_CMD_READ_IPSEC_INFO __constant_cpu_to_le16(0x005e) | 343 | #define TYPHOON_CMD_READ_IPSEC_INFO cpu_to_le16(0x005e) |
344 | #define TYPHOON_CMD_GET_IPSEC_ENABLE __constant_cpu_to_le16(0x0067) | 344 | #define TYPHOON_CMD_GET_IPSEC_ENABLE cpu_to_le16(0x0067) |
345 | #define TYPHOON_CMD_GET_CMD_LVL __constant_cpu_to_le16(0x0069) | 345 | #define TYPHOON_CMD_GET_CMD_LVL cpu_to_le16(0x0069) |
346 | u16 seqNo; | 346 | u16 seqNo; |
347 | __le16 parm1; | 347 | __le16 parm1; |
348 | __le32 parm2; | 348 | __le32 parm2; |
@@ -380,11 +380,11 @@ struct resp_desc { | |||
380 | 380 | ||
381 | /* TYPHOON_CMD_SET_RX_FILTER filter bits (cmd.parm1) | 381 | /* TYPHOON_CMD_SET_RX_FILTER filter bits (cmd.parm1) |
382 | */ | 382 | */ |
383 | #define TYPHOON_RX_FILTER_DIRECTED __constant_cpu_to_le16(0x0001) | 383 | #define TYPHOON_RX_FILTER_DIRECTED cpu_to_le16(0x0001) |
384 | #define TYPHOON_RX_FILTER_ALL_MCAST __constant_cpu_to_le16(0x0002) | 384 | #define TYPHOON_RX_FILTER_ALL_MCAST cpu_to_le16(0x0002) |
385 | #define TYPHOON_RX_FILTER_BROADCAST __constant_cpu_to_le16(0x0004) | 385 | #define TYPHOON_RX_FILTER_BROADCAST cpu_to_le16(0x0004) |
386 | #define TYPHOON_RX_FILTER_PROMISCOUS __constant_cpu_to_le16(0x0008) | 386 | #define TYPHOON_RX_FILTER_PROMISCOUS cpu_to_le16(0x0008) |
387 | #define TYPHOON_RX_FILTER_MCAST_HASH __constant_cpu_to_le16(0x0010) | 387 | #define TYPHOON_RX_FILTER_MCAST_HASH cpu_to_le16(0x0010) |
388 | 388 | ||
389 | /* TYPHOON_CMD_READ_STATS response format | 389 | /* TYPHOON_CMD_READ_STATS response format |
390 | */ | 390 | */ |
@@ -416,40 +416,40 @@ struct stats_resp { | |||
416 | __le32 rxOverflow; | 416 | __le32 rxOverflow; |
417 | __le32 rxFiltered; | 417 | __le32 rxFiltered; |
418 | __le32 linkStatus; | 418 | __le32 linkStatus; |
419 | #define TYPHOON_LINK_STAT_MASK __constant_cpu_to_le32(0x00000001) | 419 | #define TYPHOON_LINK_STAT_MASK cpu_to_le32(0x00000001) |
420 | #define TYPHOON_LINK_GOOD __constant_cpu_to_le32(0x00000001) | 420 | #define TYPHOON_LINK_GOOD cpu_to_le32(0x00000001) |
421 | #define TYPHOON_LINK_BAD __constant_cpu_to_le32(0x00000000) | 421 | #define TYPHOON_LINK_BAD cpu_to_le32(0x00000000) |
422 | #define TYPHOON_LINK_SPEED_MASK __constant_cpu_to_le32(0x00000002) | 422 | #define TYPHOON_LINK_SPEED_MASK cpu_to_le32(0x00000002) |
423 | #define TYPHOON_LINK_100MBPS __constant_cpu_to_le32(0x00000002) | 423 | #define TYPHOON_LINK_100MBPS cpu_to_le32(0x00000002) |
424 | #define TYPHOON_LINK_10MBPS __constant_cpu_to_le32(0x00000000) | 424 | #define TYPHOON_LINK_10MBPS cpu_to_le32(0x00000000) |
425 | #define TYPHOON_LINK_DUPLEX_MASK __constant_cpu_to_le32(0x00000004) | 425 | #define TYPHOON_LINK_DUPLEX_MASK cpu_to_le32(0x00000004) |
426 | #define TYPHOON_LINK_FULL_DUPLEX __constant_cpu_to_le32(0x00000004) | 426 | #define TYPHOON_LINK_FULL_DUPLEX cpu_to_le32(0x00000004) |
427 | #define TYPHOON_LINK_HALF_DUPLEX __constant_cpu_to_le32(0x00000000) | 427 | #define TYPHOON_LINK_HALF_DUPLEX cpu_to_le32(0x00000000) |
428 | __le32 unused2; | 428 | __le32 unused2; |
429 | __le32 unused3; | 429 | __le32 unused3; |
430 | } __attribute__ ((packed)); | 430 | } __attribute__ ((packed)); |
431 | 431 | ||
432 | /* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1) | 432 | /* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1) |
433 | */ | 433 | */ |
434 | #define TYPHOON_XCVR_10HALF __constant_cpu_to_le16(0x0000) | 434 | #define TYPHOON_XCVR_10HALF cpu_to_le16(0x0000) |
435 | #define TYPHOON_XCVR_10FULL __constant_cpu_to_le16(0x0001) | 435 | #define TYPHOON_XCVR_10FULL cpu_to_le16(0x0001) |
436 | #define TYPHOON_XCVR_100HALF __constant_cpu_to_le16(0x0002) | 436 | #define TYPHOON_XCVR_100HALF cpu_to_le16(0x0002) |
437 | #define TYPHOON_XCVR_100FULL __constant_cpu_to_le16(0x0003) | 437 | #define TYPHOON_XCVR_100FULL cpu_to_le16(0x0003) |
438 | #define TYPHOON_XCVR_AUTONEG __constant_cpu_to_le16(0x0004) | 438 | #define TYPHOON_XCVR_AUTONEG cpu_to_le16(0x0004) |
439 | 439 | ||
440 | /* TYPHOON_CMD_READ_MEDIA_STATUS (resp.parm1) | 440 | /* TYPHOON_CMD_READ_MEDIA_STATUS (resp.parm1) |
441 | */ | 441 | */ |
442 | #define TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE __constant_cpu_to_le16(0x0004) | 442 | #define TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE cpu_to_le16(0x0004) |
443 | #define TYPHOON_MEDIA_STAT_COLLISION_DETECT __constant_cpu_to_le16(0x0010) | 443 | #define TYPHOON_MEDIA_STAT_COLLISION_DETECT cpu_to_le16(0x0010) |
444 | #define TYPHOON_MEDIA_STAT_CARRIER_SENSE __constant_cpu_to_le16(0x0020) | 444 | #define TYPHOON_MEDIA_STAT_CARRIER_SENSE cpu_to_le16(0x0020) |
445 | #define TYPHOON_MEDIA_STAT_POLARITY_REV __constant_cpu_to_le16(0x0400) | 445 | #define TYPHOON_MEDIA_STAT_POLARITY_REV cpu_to_le16(0x0400) |
446 | #define TYPHOON_MEDIA_STAT_NO_LINK __constant_cpu_to_le16(0x0800) | 446 | #define TYPHOON_MEDIA_STAT_NO_LINK cpu_to_le16(0x0800) |
447 | 447 | ||
448 | /* TYPHOON_CMD_SET_MULTICAST_HASH enable values (cmd.parm1) | 448 | /* TYPHOON_CMD_SET_MULTICAST_HASH enable values (cmd.parm1) |
449 | */ | 449 | */ |
450 | #define TYPHOON_MCAST_HASH_DISABLE __constant_cpu_to_le16(0x0000) | 450 | #define TYPHOON_MCAST_HASH_DISABLE cpu_to_le16(0x0000) |
451 | #define TYPHOON_MCAST_HASH_ENABLE __constant_cpu_to_le16(0x0001) | 451 | #define TYPHOON_MCAST_HASH_ENABLE cpu_to_le16(0x0001) |
452 | #define TYPHOON_MCAST_HASH_SET __constant_cpu_to_le16(0x0002) | 452 | #define TYPHOON_MCAST_HASH_SET cpu_to_le16(0x0002) |
453 | 453 | ||
454 | /* TYPHOON_CMD_CREATE_SA descriptor and settings | 454 | /* TYPHOON_CMD_CREATE_SA descriptor and settings |
455 | */ | 455 | */ |
@@ -459,9 +459,9 @@ struct sa_descriptor { | |||
459 | u16 cmd; | 459 | u16 cmd; |
460 | u16 seqNo; | 460 | u16 seqNo; |
461 | u16 mode; | 461 | u16 mode; |
462 | #define TYPHOON_SA_MODE_NULL __constant_cpu_to_le16(0x0000) | 462 | #define TYPHOON_SA_MODE_NULL cpu_to_le16(0x0000) |
463 | #define TYPHOON_SA_MODE_AH __constant_cpu_to_le16(0x0001) | 463 | #define TYPHOON_SA_MODE_AH cpu_to_le16(0x0001) |
464 | #define TYPHOON_SA_MODE_ESP __constant_cpu_to_le16(0x0002) | 464 | #define TYPHOON_SA_MODE_ESP cpu_to_le16(0x0002) |
465 | u8 hashFlags; | 465 | u8 hashFlags; |
466 | #define TYPHOON_SA_HASH_ENABLE 0x01 | 466 | #define TYPHOON_SA_HASH_ENABLE 0x01 |
467 | #define TYPHOON_SA_HASH_SHA1 0x02 | 467 | #define TYPHOON_SA_HASH_SHA1 0x02 |
@@ -493,22 +493,22 @@ struct sa_descriptor { | |||
493 | /* TYPHOON_CMD_SET_OFFLOAD_TASKS bits (cmd.parm2 (Tx) & cmd.parm3 (Rx)) | 493 | /* TYPHOON_CMD_SET_OFFLOAD_TASKS bits (cmd.parm2 (Tx) & cmd.parm3 (Rx)) |
494 | * This is all for IPv4. | 494 | * This is all for IPv4. |
495 | */ | 495 | */ |
496 | #define TYPHOON_OFFLOAD_TCP_CHKSUM __constant_cpu_to_le32(0x00000002) | 496 | #define TYPHOON_OFFLOAD_TCP_CHKSUM cpu_to_le32(0x00000002) |
497 | #define TYPHOON_OFFLOAD_UDP_CHKSUM __constant_cpu_to_le32(0x00000004) | 497 | #define TYPHOON_OFFLOAD_UDP_CHKSUM cpu_to_le32(0x00000004) |
498 | #define TYPHOON_OFFLOAD_IP_CHKSUM __constant_cpu_to_le32(0x00000008) | 498 | #define TYPHOON_OFFLOAD_IP_CHKSUM cpu_to_le32(0x00000008) |
499 | #define TYPHOON_OFFLOAD_IPSEC __constant_cpu_to_le32(0x00000010) | 499 | #define TYPHOON_OFFLOAD_IPSEC cpu_to_le32(0x00000010) |
500 | #define TYPHOON_OFFLOAD_BCAST_THROTTLE __constant_cpu_to_le32(0x00000020) | 500 | #define TYPHOON_OFFLOAD_BCAST_THROTTLE cpu_to_le32(0x00000020) |
501 | #define TYPHOON_OFFLOAD_DHCP_PREVENT __constant_cpu_to_le32(0x00000040) | 501 | #define TYPHOON_OFFLOAD_DHCP_PREVENT cpu_to_le32(0x00000040) |
502 | #define TYPHOON_OFFLOAD_VLAN __constant_cpu_to_le32(0x00000080) | 502 | #define TYPHOON_OFFLOAD_VLAN cpu_to_le32(0x00000080) |
503 | #define TYPHOON_OFFLOAD_FILTERING __constant_cpu_to_le32(0x00000100) | 503 | #define TYPHOON_OFFLOAD_FILTERING cpu_to_le32(0x00000100) |
504 | #define TYPHOON_OFFLOAD_TCP_SEGMENT __constant_cpu_to_le32(0x00000200) | 504 | #define TYPHOON_OFFLOAD_TCP_SEGMENT cpu_to_le32(0x00000200) |
505 | 505 | ||
506 | /* TYPHOON_CMD_ENABLE_WAKE_EVENTS bits (cmd.parm1) | 506 | /* TYPHOON_CMD_ENABLE_WAKE_EVENTS bits (cmd.parm1) |
507 | */ | 507 | */ |
508 | #define TYPHOON_WAKE_MAGIC_PKT __constant_cpu_to_le16(0x01) | 508 | #define TYPHOON_WAKE_MAGIC_PKT cpu_to_le16(0x01) |
509 | #define TYPHOON_WAKE_LINK_EVENT __constant_cpu_to_le16(0x02) | 509 | #define TYPHOON_WAKE_LINK_EVENT cpu_to_le16(0x02) |
510 | #define TYPHOON_WAKE_ICMP_ECHO __constant_cpu_to_le16(0x04) | 510 | #define TYPHOON_WAKE_ICMP_ECHO cpu_to_le16(0x04) |
511 | #define TYPHOON_WAKE_ARP __constant_cpu_to_le16(0x08) | 511 | #define TYPHOON_WAKE_ARP cpu_to_le16(0x08) |
512 | 512 | ||
513 | /* These are used to load the firmware image on the NIC | 513 | /* These are used to load the firmware image on the NIC |
514 | */ | 514 | */ |