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authorYoshinori Sato <ysato@users.sourceforge.jp>2006-11-05 01:40:13 -0500
committerPaul Mundt <lethal@linux-sh.org>2006-12-05 20:45:36 -0500
commit9d4436a6fbc8c5eccdfcb8f5884e0a7b4a57f6d2 (patch)
treea8b7532fffa76ae526dea547cc87200466e00842 /drivers
parente62438630ca37539c8cc1553710bbfaa3cf960a7 (diff)
sh: Add support for SH7206 and SH7619 CPU subtypes.
This implements initial support for the SH7206 (SH-2A) and SH7619 (SH-2) MMU-less CPUs. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/serial/sh-sci.h36
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 7ee992146ae9..b2bc0cfb4014 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -133,6 +133,20 @@
133# define SCIF_ORER 0x0001 /* Overrun error bit */ 133# define SCIF_ORER 0x0001 /* Overrun error bit */
134# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 134# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
135# define SCIF_ONLY 135# define SCIF_ONLY
136#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
137# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
138# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
139# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
140# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
141# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
142# define SCIF_ONLY
143#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
144# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
145# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
146# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
147# define SCIF_ORER 0x0001 /* overrun error bit */
148# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
149# define SCIF_ONLY
136#else 150#else
137# error CPU subtype not defined 151# error CPU subtype not defined
138#endif 152#endif
@@ -544,6 +558,28 @@ static inline int sci_rxd_in(struct uart_port *port)
544 if (port->mapbase == 0xffe10000) 558 if (port->mapbase == 0xffe10000)
545 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ 559 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
546} 560}
561#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
562static inline int sci_rxd_in(struct uart_port *port)
563{
564 if (port->mapbase == 0xfffe8000)
565 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
566 if (port->mapbase == 0xfffe8800)
567 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
568 if (port->mapbase == 0xfffe9000)
569 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
570 if (port->mapbase == 0xfffe9800)
571 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
572}
573#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
574static inline int sci_rxd_in(struct uart_port *port)
575{
576 if (port->mapbase == 0xf8400000)
577 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
578 if (port->mapbase == 0xf8410000)
579 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
580 if (port->mapbase == 0xf8420000)
581 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
582}
547#endif 583#endif
548 584
549/* 585/*