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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-12 21:09:18 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-12 21:09:18 -0400
commit6b702462cbe5b6f372966a53f4465d745d86b65c (patch)
tree19a8d090b284bb804e8a2ffa38fa51b58118db6a /drivers
parent947ec0b0c1e7e80eef4fe64f7763a06d0cf04d2e (diff)
parent3c24475c1e4e8d10e50df161d8c4f1d382997a7c (diff)
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (50 commits) drm: include kernel list header file in hashtab header drm: Export hash table functionality. drm: Split out the mm declarations in a separate header. Add atomic operations. drm/radeon: add support for RV790. drm/radeon: add rv740 drm support. drm_calloc_large: check right size, check integer overflow, use GFP_ZERO drm: Eliminate magic I2C frobbing when reading EDID drm/i915: duplicate desired mode for use by fbcon. drm/via: vfree() no need checking before calling it drm: Replace DRM_DEBUG with DRM_DEBUG_DRIVER in i915 driver drm: Replace DRM_DEBUG with DRM_DEBUG_MODE in drm_mode drm/i915: Replace DRM_DEBUG with DRM_DEBUG_KMS in intel_sdvo drm/i915: replace DRM_DEBUG with DRM_DEBUG_KMS in intel_lvds drm: add separate drm debugging levels radeon: remove _DRM_DRIVER from the preadded sarea map drm: don't associate _DRM_DRIVER maps with a master drm: simplify kcalloc() call to kzalloc(). intelfb: fix spelling of "CLOCK" drm: fix LOCK_TEST_WITH_RETURN macro drm/i915: Hook connector to encoder during load detection (fixes tv/vga detect) ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/char/agp/intel-agp.c16
-rw-r--r--drivers/gpu/drm/drm_bufs.c3
-rw-r--r--drivers/gpu/drm/drm_edid.c74
-rw-r--r--drivers/gpu/drm/drm_gem.c2
-rw-r--r--drivers/gpu/drm/drm_hashtab.c4
-rw-r--r--drivers/gpu/drm/drm_mm.c165
-rw-r--r--drivers/gpu/drm/drm_modes.c18
-rw-r--r--drivers/gpu/drm/drm_stub.c17
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c67
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h48
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c153
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c152
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c190
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h616
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c20
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c86
-rw-r--r--drivers/gpu/drm/i915/intel_bios.h101
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c76
-rw-r--r--drivers/gpu/drm/i915/intel_display.c645
-rw-r--r--drivers/gpu/drm/i915/intel_fb.c26
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c33
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c151
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c110
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c3
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c42
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h1
-rw-r--r--drivers/gpu/drm/via/via_dmablit.c6
-rw-r--r--drivers/pnp/resource.c18
29 files changed, 2506 insertions, 339 deletions
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 3686912427ba..7a748fa0dfce 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -46,6 +46,10 @@
46#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 46#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
47#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 47#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
48#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 48#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
49#define PCI_DEVICE_ID_INTEL_IGDNG_D_HB 0x0040
50#define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x0042
51#define PCI_DEVICE_ID_INTEL_IGDNG_M_HB 0x0044
52#define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x0046
49 53
50/* cover 915 and 945 variants */ 54/* cover 915 and 945 variants */
51#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ 55#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
@@ -75,7 +79,9 @@
75 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ 79 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
76 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ 80 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
77 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ 81 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
78 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB) 82 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
83 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
84 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB)
79 85
80extern int agp_memory_reserved; 86extern int agp_memory_reserved;
81 87
@@ -1211,6 +1217,8 @@ static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1211 case PCI_DEVICE_ID_INTEL_Q45_HB: 1217 case PCI_DEVICE_ID_INTEL_Q45_HB:
1212 case PCI_DEVICE_ID_INTEL_G45_HB: 1218 case PCI_DEVICE_ID_INTEL_G45_HB:
1213 case PCI_DEVICE_ID_INTEL_G41_HB: 1219 case PCI_DEVICE_ID_INTEL_G41_HB:
1220 case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1221 case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1214 *gtt_offset = *gtt_size = MB(2); 1222 *gtt_offset = *gtt_size = MB(2);
1215 break; 1223 break;
1216 default: 1224 default:
@@ -2186,6 +2194,10 @@ static const struct intel_driver_description {
2186 "G45/G43", NULL, &intel_i965_driver }, 2194 "G45/G43", NULL, &intel_i965_driver },
2187 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, 2195 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2188 "G41", NULL, &intel_i965_driver }, 2196 "G41", NULL, &intel_i965_driver },
2197 { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
2198 "IGDNG/D", NULL, &intel_i965_driver },
2199 { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2200 "IGDNG/M", NULL, &intel_i965_driver },
2189 { 0, 0, 0, NULL, NULL, NULL } 2201 { 0, 0, 0, NULL, NULL, NULL }
2190}; 2202};
2191 2203
@@ -2387,6 +2399,8 @@ static struct pci_device_id agp_intel_pci_table[] = {
2387 ID(PCI_DEVICE_ID_INTEL_Q45_HB), 2399 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2388 ID(PCI_DEVICE_ID_INTEL_G45_HB), 2400 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2389 ID(PCI_DEVICE_ID_INTEL_G41_HB), 2401 ID(PCI_DEVICE_ID_INTEL_G41_HB),
2402 ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2403 ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2390 { } 2404 { }
2391}; 2405};
2392 2406
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
index 0411d912d82a..80a257554b30 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -371,7 +371,8 @@ static int drm_addmap_core(struct drm_device * dev, resource_size_t offset,
371 list->user_token = list->hash.key << PAGE_SHIFT; 371 list->user_token = list->hash.key << PAGE_SHIFT;
372 mutex_unlock(&dev->struct_mutex); 372 mutex_unlock(&dev->struct_mutex);
373 373
374 list->master = dev->primary->master; 374 if (!(map->flags & _DRM_DRIVER))
375 list->master = dev->primary->master;
375 *maplist = list; 376 *maplist = list;
376 return 0; 377 return 0;
377 } 378 }
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 6f6b26479d82..801a0d0e0810 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -589,85 +589,13 @@ int drm_do_probe_ddc_edid(struct i2c_adapter *adapter,
589} 589}
590EXPORT_SYMBOL(drm_do_probe_ddc_edid); 590EXPORT_SYMBOL(drm_do_probe_ddc_edid);
591 591
592/**
593 * Get EDID information.
594 *
595 * \param adapter : i2c device adaptor.
596 * \param buf : EDID data buffer to be filled
597 * \param len : EDID data buffer length
598 * \return 0 on success or -1 on failure.
599 *
600 * Initialize DDC, then fetch EDID information
601 * by calling drm_do_probe_ddc_edid function.
602 */
603static int drm_ddc_read(struct i2c_adapter *adapter,
604 unsigned char *buf, int len)
605{
606 struct i2c_algo_bit_data *algo_data = adapter->algo_data;
607 int i, j;
608 int ret = -1;
609
610 algo_data->setscl(algo_data->data, 1);
611
612 for (i = 0; i < 1; i++) {
613 /* For some old monitors we need the
614 * following process to initialize/stop DDC
615 */
616 algo_data->setsda(algo_data->data, 1);
617 msleep(13);
618
619 algo_data->setscl(algo_data->data, 1);
620 for (j = 0; j < 5; j++) {
621 msleep(10);
622 if (algo_data->getscl(algo_data->data))
623 break;
624 }
625 if (j == 5)
626 continue;
627
628 algo_data->setsda(algo_data->data, 0);
629 msleep(15);
630 algo_data->setscl(algo_data->data, 0);
631 msleep(15);
632 algo_data->setsda(algo_data->data, 1);
633 msleep(15);
634
635 /* Do the real work */
636 ret = drm_do_probe_ddc_edid(adapter, buf, len);
637 algo_data->setsda(algo_data->data, 0);
638 algo_data->setscl(algo_data->data, 0);
639 msleep(15);
640
641 algo_data->setscl(algo_data->data, 1);
642 for (j = 0; j < 10; j++) {
643 msleep(10);
644 if (algo_data->getscl(algo_data->data))
645 break;
646 }
647
648 algo_data->setsda(algo_data->data, 1);
649 msleep(15);
650 algo_data->setscl(algo_data->data, 0);
651 algo_data->setsda(algo_data->data, 0);
652 if (ret == 0)
653 break;
654 }
655 /* Release the DDC lines when done or the Apple Cinema HD display
656 * will switch off
657 */
658 algo_data->setsda(algo_data->data, 1);
659 algo_data->setscl(algo_data->data, 1);
660
661 return ret;
662}
663
664static int drm_ddc_read_edid(struct drm_connector *connector, 592static int drm_ddc_read_edid(struct drm_connector *connector,
665 struct i2c_adapter *adapter, 593 struct i2c_adapter *adapter,
666 char *buf, int len) 594 char *buf, int len)
667{ 595{
668 int ret; 596 int ret;
669 597
670 ret = drm_ddc_read(adapter, buf, len); 598 ret = drm_do_probe_ddc_edid(adapter, buf, len);
671 if (ret != 0) { 599 if (ret != 0) {
672 dev_info(&connector->dev->pdev->dev, "%s: no EDID data\n", 600 dev_info(&connector->dev->pdev->dev, "%s: no EDID data\n",
673 drm_get_connector_name(connector)); 601 drm_get_connector_name(connector));
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 4984aa89cf3d..ec43005100d9 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -133,7 +133,7 @@ drm_gem_object_alloc(struct drm_device *dev, size_t size)
133 133
134 BUG_ON((size & (PAGE_SIZE - 1)) != 0); 134 BUG_ON((size & (PAGE_SIZE - 1)) != 0);
135 135
136 obj = kcalloc(1, sizeof(*obj), GFP_KERNEL); 136 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
137 137
138 obj->dev = dev; 138 obj->dev = dev;
139 obj->filp = shmem_file_setup("drm mm object", size, VM_NORESERVE); 139 obj->filp = shmem_file_setup("drm mm object", size, VM_NORESERVE);
diff --git a/drivers/gpu/drm/drm_hashtab.c b/drivers/gpu/drm/drm_hashtab.c
index af539f7d87dd..ac35145c3e20 100644
--- a/drivers/gpu/drm/drm_hashtab.c
+++ b/drivers/gpu/drm/drm_hashtab.c
@@ -62,6 +62,7 @@ int drm_ht_create(struct drm_open_hash *ht, unsigned int order)
62 } 62 }
63 return 0; 63 return 0;
64} 64}
65EXPORT_SYMBOL(drm_ht_create);
65 66
66void drm_ht_verbose_list(struct drm_open_hash *ht, unsigned long key) 67void drm_ht_verbose_list(struct drm_open_hash *ht, unsigned long key)
67{ 68{
@@ -156,6 +157,7 @@ int drm_ht_just_insert_please(struct drm_open_hash *ht, struct drm_hash_item *it
156 } 157 }
157 return 0; 158 return 0;
158} 159}
160EXPORT_SYMBOL(drm_ht_just_insert_please);
159 161
160int drm_ht_find_item(struct drm_open_hash *ht, unsigned long key, 162int drm_ht_find_item(struct drm_open_hash *ht, unsigned long key,
161 struct drm_hash_item **item) 163 struct drm_hash_item **item)
@@ -169,6 +171,7 @@ int drm_ht_find_item(struct drm_open_hash *ht, unsigned long key,
169 *item = hlist_entry(list, struct drm_hash_item, head); 171 *item = hlist_entry(list, struct drm_hash_item, head);
170 return 0; 172 return 0;
171} 173}
174EXPORT_SYMBOL(drm_ht_find_item);
172 175
173int drm_ht_remove_key(struct drm_open_hash *ht, unsigned long key) 176int drm_ht_remove_key(struct drm_open_hash *ht, unsigned long key)
174{ 177{
@@ -202,3 +205,4 @@ void drm_ht_remove(struct drm_open_hash *ht)
202 ht->table = NULL; 205 ht->table = NULL;
203 } 206 }
204} 207}
208EXPORT_SYMBOL(drm_ht_remove);
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index 367c590ffbba..7819fd930a51 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -42,8 +42,11 @@
42 */ 42 */
43 43
44#include "drmP.h" 44#include "drmP.h"
45#include "drm_mm.h"
45#include <linux/slab.h> 46#include <linux/slab.h>
46 47
48#define MM_UNUSED_TARGET 4
49
47unsigned long drm_mm_tail_space(struct drm_mm *mm) 50unsigned long drm_mm_tail_space(struct drm_mm *mm)
48{ 51{
49 struct list_head *tail_node; 52 struct list_head *tail_node;
@@ -74,16 +77,62 @@ int drm_mm_remove_space_from_tail(struct drm_mm *mm, unsigned long size)
74 return 0; 77 return 0;
75} 78}
76 79
80static struct drm_mm_node *drm_mm_kmalloc(struct drm_mm *mm, int atomic)
81{
82 struct drm_mm_node *child;
83
84 if (atomic)
85 child = kmalloc(sizeof(*child), GFP_ATOMIC);
86 else
87 child = kmalloc(sizeof(*child), GFP_KERNEL);
88
89 if (unlikely(child == NULL)) {
90 spin_lock(&mm->unused_lock);
91 if (list_empty(&mm->unused_nodes))
92 child = NULL;
93 else {
94 child =
95 list_entry(mm->unused_nodes.next,
96 struct drm_mm_node, fl_entry);
97 list_del(&child->fl_entry);
98 --mm->num_unused;
99 }
100 spin_unlock(&mm->unused_lock);
101 }
102 return child;
103}
104
105int drm_mm_pre_get(struct drm_mm *mm)
106{
107 struct drm_mm_node *node;
108
109 spin_lock(&mm->unused_lock);
110 while (mm->num_unused < MM_UNUSED_TARGET) {
111 spin_unlock(&mm->unused_lock);
112 node = kmalloc(sizeof(*node), GFP_KERNEL);
113 spin_lock(&mm->unused_lock);
114
115 if (unlikely(node == NULL)) {
116 int ret = (mm->num_unused < 2) ? -ENOMEM : 0;
117 spin_unlock(&mm->unused_lock);
118 return ret;
119 }
120 ++mm->num_unused;
121 list_add_tail(&node->fl_entry, &mm->unused_nodes);
122 }
123 spin_unlock(&mm->unused_lock);
124 return 0;
125}
126EXPORT_SYMBOL(drm_mm_pre_get);
77 127
78static int drm_mm_create_tail_node(struct drm_mm *mm, 128static int drm_mm_create_tail_node(struct drm_mm *mm,
79 unsigned long start, 129 unsigned long start,
80 unsigned long size) 130 unsigned long size, int atomic)
81{ 131{
82 struct drm_mm_node *child; 132 struct drm_mm_node *child;
83 133
84 child = (struct drm_mm_node *) 134 child = drm_mm_kmalloc(mm, atomic);
85 drm_alloc(sizeof(*child), DRM_MEM_MM); 135 if (unlikely(child == NULL))
86 if (!child)
87 return -ENOMEM; 136 return -ENOMEM;
88 137
89 child->free = 1; 138 child->free = 1;
@@ -97,8 +146,7 @@ static int drm_mm_create_tail_node(struct drm_mm *mm,
97 return 0; 146 return 0;
98} 147}
99 148
100 149int drm_mm_add_space_to_tail(struct drm_mm *mm, unsigned long size, int atomic)
101int drm_mm_add_space_to_tail(struct drm_mm *mm, unsigned long size)
102{ 150{
103 struct list_head *tail_node; 151 struct list_head *tail_node;
104 struct drm_mm_node *entry; 152 struct drm_mm_node *entry;
@@ -106,20 +154,21 @@ int drm_mm_add_space_to_tail(struct drm_mm *mm, unsigned long size)
106 tail_node = mm->ml_entry.prev; 154 tail_node = mm->ml_entry.prev;
107 entry = list_entry(tail_node, struct drm_mm_node, ml_entry); 155 entry = list_entry(tail_node, struct drm_mm_node, ml_entry);
108 if (!entry->free) { 156 if (!entry->free) {
109 return drm_mm_create_tail_node(mm, entry->start + entry->size, size); 157 return drm_mm_create_tail_node(mm, entry->start + entry->size,
158 size, atomic);
110 } 159 }
111 entry->size += size; 160 entry->size += size;
112 return 0; 161 return 0;
113} 162}
114 163
115static struct drm_mm_node *drm_mm_split_at_start(struct drm_mm_node *parent, 164static struct drm_mm_node *drm_mm_split_at_start(struct drm_mm_node *parent,
116 unsigned long size) 165 unsigned long size,
166 int atomic)
117{ 167{
118 struct drm_mm_node *child; 168 struct drm_mm_node *child;
119 169
120 child = (struct drm_mm_node *) 170 child = drm_mm_kmalloc(parent->mm, atomic);
121 drm_alloc(sizeof(*child), DRM_MEM_MM); 171 if (unlikely(child == NULL))
122 if (!child)
123 return NULL; 172 return NULL;
124 173
125 INIT_LIST_HEAD(&child->fl_entry); 174 INIT_LIST_HEAD(&child->fl_entry);
@@ -151,8 +200,9 @@ struct drm_mm_node *drm_mm_get_block(struct drm_mm_node * parent,
151 tmp = parent->start % alignment; 200 tmp = parent->start % alignment;
152 201
153 if (tmp) { 202 if (tmp) {
154 align_splitoff = drm_mm_split_at_start(parent, alignment - tmp); 203 align_splitoff =
155 if (!align_splitoff) 204 drm_mm_split_at_start(parent, alignment - tmp, 0);
205 if (unlikely(align_splitoff == NULL))
156 return NULL; 206 return NULL;
157 } 207 }
158 208
@@ -161,7 +211,7 @@ struct drm_mm_node *drm_mm_get_block(struct drm_mm_node * parent,
161 parent->free = 0; 211 parent->free = 0;
162 return parent; 212 return parent;
163 } else { 213 } else {
164 child = drm_mm_split_at_start(parent, size); 214 child = drm_mm_split_at_start(parent, size, 0);
165 } 215 }
166 216
167 if (align_splitoff) 217 if (align_splitoff)
@@ -169,14 +219,49 @@ struct drm_mm_node *drm_mm_get_block(struct drm_mm_node * parent,
169 219
170 return child; 220 return child;
171} 221}
222
172EXPORT_SYMBOL(drm_mm_get_block); 223EXPORT_SYMBOL(drm_mm_get_block);
173 224
225struct drm_mm_node *drm_mm_get_block_atomic(struct drm_mm_node *parent,
226 unsigned long size,
227 unsigned alignment)
228{
229
230 struct drm_mm_node *align_splitoff = NULL;
231 struct drm_mm_node *child;
232 unsigned tmp = 0;
233
234 if (alignment)
235 tmp = parent->start % alignment;
236
237 if (tmp) {
238 align_splitoff =
239 drm_mm_split_at_start(parent, alignment - tmp, 1);
240 if (unlikely(align_splitoff == NULL))
241 return NULL;
242 }
243
244 if (parent->size == size) {
245 list_del_init(&parent->fl_entry);
246 parent->free = 0;
247 return parent;
248 } else {
249 child = drm_mm_split_at_start(parent, size, 1);
250 }
251
252 if (align_splitoff)
253 drm_mm_put_block(align_splitoff);
254
255 return child;
256}
257EXPORT_SYMBOL(drm_mm_get_block_atomic);
258
174/* 259/*
175 * Put a block. Merge with the previous and / or next block if they are free. 260 * Put a block. Merge with the previous and / or next block if they are free.
176 * Otherwise add to the free stack. 261 * Otherwise add to the free stack.
177 */ 262 */
178 263
179void drm_mm_put_block(struct drm_mm_node * cur) 264void drm_mm_put_block(struct drm_mm_node *cur)
180{ 265{
181 266
182 struct drm_mm *mm = cur->mm; 267 struct drm_mm *mm = cur->mm;
@@ -188,21 +273,27 @@ void drm_mm_put_block(struct drm_mm_node * cur)
188 int merged = 0; 273 int merged = 0;
189 274
190 if (cur_head->prev != root_head) { 275 if (cur_head->prev != root_head) {
191 prev_node = list_entry(cur_head->prev, struct drm_mm_node, ml_entry); 276 prev_node =
277 list_entry(cur_head->prev, struct drm_mm_node, ml_entry);
192 if (prev_node->free) { 278 if (prev_node->free) {
193 prev_node->size += cur->size; 279 prev_node->size += cur->size;
194 merged = 1; 280 merged = 1;
195 } 281 }
196 } 282 }
197 if (cur_head->next != root_head) { 283 if (cur_head->next != root_head) {
198 next_node = list_entry(cur_head->next, struct drm_mm_node, ml_entry); 284 next_node =
285 list_entry(cur_head->next, struct drm_mm_node, ml_entry);
199 if (next_node->free) { 286 if (next_node->free) {
200 if (merged) { 287 if (merged) {
201 prev_node->size += next_node->size; 288 prev_node->size += next_node->size;
202 list_del(&next_node->ml_entry); 289 list_del(&next_node->ml_entry);
203 list_del(&next_node->fl_entry); 290 list_del(&next_node->fl_entry);
204 drm_free(next_node, sizeof(*next_node), 291 if (mm->num_unused < MM_UNUSED_TARGET) {
205 DRM_MEM_MM); 292 list_add(&next_node->fl_entry,
293 &mm->unused_nodes);
294 ++mm->num_unused;
295 } else
296 kfree(next_node);
206 } else { 297 } else {
207 next_node->size += cur->size; 298 next_node->size += cur->size;
208 next_node->start = cur->start; 299 next_node->start = cur->start;
@@ -215,14 +306,19 @@ void drm_mm_put_block(struct drm_mm_node * cur)
215 list_add(&cur->fl_entry, &mm->fl_entry); 306 list_add(&cur->fl_entry, &mm->fl_entry);
216 } else { 307 } else {
217 list_del(&cur->ml_entry); 308 list_del(&cur->ml_entry);
218 drm_free(cur, sizeof(*cur), DRM_MEM_MM); 309 if (mm->num_unused < MM_UNUSED_TARGET) {
310 list_add(&cur->fl_entry, &mm->unused_nodes);
311 ++mm->num_unused;
312 } else
313 kfree(cur);
219 } 314 }
220} 315}
316
221EXPORT_SYMBOL(drm_mm_put_block); 317EXPORT_SYMBOL(drm_mm_put_block);
222 318
223struct drm_mm_node *drm_mm_search_free(const struct drm_mm * mm, 319struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm,
224 unsigned long size, 320 unsigned long size,
225 unsigned alignment, int best_match) 321 unsigned alignment, int best_match)
226{ 322{
227 struct list_head *list; 323 struct list_head *list;
228 const struct list_head *free_stack = &mm->fl_entry; 324 const struct list_head *free_stack = &mm->fl_entry;
@@ -247,7 +343,6 @@ struct drm_mm_node *drm_mm_search_free(const struct drm_mm * mm,
247 wasted += alignment - tmp; 343 wasted += alignment - tmp;
248 } 344 }
249 345
250
251 if (entry->size >= size + wasted) { 346 if (entry->size >= size + wasted) {
252 if (!best_match) 347 if (!best_match)
253 return entry; 348 return entry;
@@ -260,6 +355,7 @@ struct drm_mm_node *drm_mm_search_free(const struct drm_mm * mm,
260 355
261 return best; 356 return best;
262} 357}
358EXPORT_SYMBOL(drm_mm_search_free);
263 359
264int drm_mm_clean(struct drm_mm * mm) 360int drm_mm_clean(struct drm_mm * mm)
265{ 361{
@@ -267,14 +363,17 @@ int drm_mm_clean(struct drm_mm * mm)
267 363
268 return (head->next->next == head); 364 return (head->next->next == head);
269} 365}
270EXPORT_SYMBOL(drm_mm_search_free); 366EXPORT_SYMBOL(drm_mm_clean);
271 367
272int drm_mm_init(struct drm_mm * mm, unsigned long start, unsigned long size) 368int drm_mm_init(struct drm_mm * mm, unsigned long start, unsigned long size)
273{ 369{
274 INIT_LIST_HEAD(&mm->ml_entry); 370 INIT_LIST_HEAD(&mm->ml_entry);
275 INIT_LIST_HEAD(&mm->fl_entry); 371 INIT_LIST_HEAD(&mm->fl_entry);
372 INIT_LIST_HEAD(&mm->unused_nodes);
373 mm->num_unused = 0;
374 spin_lock_init(&mm->unused_lock);
276 375
277 return drm_mm_create_tail_node(mm, start, size); 376 return drm_mm_create_tail_node(mm, start, size, 0);
278} 377}
279EXPORT_SYMBOL(drm_mm_init); 378EXPORT_SYMBOL(drm_mm_init);
280 379
@@ -282,6 +381,7 @@ void drm_mm_takedown(struct drm_mm * mm)
282{ 381{
283 struct list_head *bnode = mm->fl_entry.next; 382 struct list_head *bnode = mm->fl_entry.next;
284 struct drm_mm_node *entry; 383 struct drm_mm_node *entry;
384 struct drm_mm_node *next;
285 385
286 entry = list_entry(bnode, struct drm_mm_node, fl_entry); 386 entry = list_entry(bnode, struct drm_mm_node, fl_entry);
287 387
@@ -293,7 +393,16 @@ void drm_mm_takedown(struct drm_mm * mm)
293 393
294 list_del(&entry->fl_entry); 394 list_del(&entry->fl_entry);
295 list_del(&entry->ml_entry); 395 list_del(&entry->ml_entry);
396 kfree(entry);
397
398 spin_lock(&mm->unused_lock);
399 list_for_each_entry_safe(entry, next, &mm->unused_nodes, fl_entry) {
400 list_del(&entry->fl_entry);
401 kfree(entry);
402 --mm->num_unused;
403 }
404 spin_unlock(&mm->unused_lock);
296 405
297 drm_free(entry, sizeof(*entry), DRM_MEM_MM); 406 BUG_ON(mm->num_unused != 0);
298} 407}
299EXPORT_SYMBOL(drm_mm_takedown); 408EXPORT_SYMBOL(drm_mm_takedown);
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index c9b80fdd4630..54f492a488a9 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -38,6 +38,7 @@
38#include "drm.h" 38#include "drm.h"
39#include "drm_crtc.h" 39#include "drm_crtc.h"
40 40
41#define DRM_MODESET_DEBUG "drm_mode"
41/** 42/**
42 * drm_mode_debug_printmodeline - debug print a mode 43 * drm_mode_debug_printmodeline - debug print a mode
43 * @dev: DRM device 44 * @dev: DRM device
@@ -50,12 +51,13 @@
50 */ 51 */
51void drm_mode_debug_printmodeline(struct drm_display_mode *mode) 52void drm_mode_debug_printmodeline(struct drm_display_mode *mode)
52{ 53{
53 DRM_DEBUG("Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x\n", 54 DRM_DEBUG_MODE(DRM_MODESET_DEBUG,
54 mode->base.id, mode->name, mode->vrefresh, mode->clock, 55 "Modeline %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x\n",
55 mode->hdisplay, mode->hsync_start, 56 mode->base.id, mode->name, mode->vrefresh, mode->clock,
56 mode->hsync_end, mode->htotal, 57 mode->hdisplay, mode->hsync_start,
57 mode->vdisplay, mode->vsync_start, 58 mode->hsync_end, mode->htotal,
58 mode->vsync_end, mode->vtotal, mode->type, mode->flags); 59 mode->vdisplay, mode->vsync_start,
60 mode->vsync_end, mode->vtotal, mode->type, mode->flags);
59} 61}
60EXPORT_SYMBOL(drm_mode_debug_printmodeline); 62EXPORT_SYMBOL(drm_mode_debug_printmodeline);
61 63
@@ -401,7 +403,9 @@ void drm_mode_prune_invalid(struct drm_device *dev,
401 list_del(&mode->head); 403 list_del(&mode->head);
402 if (verbose) { 404 if (verbose) {
403 drm_mode_debug_printmodeline(mode); 405 drm_mode_debug_printmodeline(mode);
404 DRM_DEBUG("Not using %s mode %d\n", mode->name, mode->status); 406 DRM_DEBUG_MODE(DRM_MODESET_DEBUG,
407 "Not using %s mode %d\n",
408 mode->name, mode->status);
405 } 409 }
406 drm_mode_destroy(dev, mode); 410 drm_mode_destroy(dev, mode);
407 } 411 }
diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
index b9631e3a1ea6..89050684fe0d 100644
--- a/drivers/gpu/drm/drm_stub.c
+++ b/drivers/gpu/drm/drm_stub.c
@@ -51,7 +51,22 @@ struct idr drm_minors_idr;
51struct class *drm_class; 51struct class *drm_class;
52struct proc_dir_entry *drm_proc_root; 52struct proc_dir_entry *drm_proc_root;
53struct dentry *drm_debugfs_root; 53struct dentry *drm_debugfs_root;
54 54void drm_ut_debug_printk(unsigned int request_level,
55 const char *prefix,
56 const char *function_name,
57 const char *format, ...)
58{
59 va_list args;
60
61 if (drm_debug & request_level) {
62 if (function_name)
63 printk(KERN_DEBUG "[%s:%s], ", prefix, function_name);
64 va_start(args, format);
65 vprintk(format, args);
66 va_end(args);
67 }
68}
69EXPORT_SYMBOL(drm_ut_debug_printk);
55static int drm_minor_get_id(struct drm_device *dev, int type) 70static int drm_minor_get_id(struct drm_device *dev, int type)
56{ 71{
57 int new_id; 72 int new_id;
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 0ccb63ee50ee..1a60626f6803 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -33,6 +33,8 @@
33#include "i915_drm.h" 33#include "i915_drm.h"
34#include "i915_drv.h" 34#include "i915_drv.h"
35 35
36#define I915_DRV "i915_drv"
37
36/* Really want an OS-independent resettable timer. Would like to have 38/* Really want an OS-independent resettable timer. Would like to have
37 * this loop run for (eg) 3 sec, but have the timer reset every time 39 * this loop run for (eg) 3 sec, but have the timer reset every time
38 * the head pointer changes, so that EBUSY only happens if the ring 40 * the head pointer changes, so that EBUSY only happens if the ring
@@ -99,7 +101,7 @@ static int i915_init_phys_hws(struct drm_device *dev)
99 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 101 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
100 102
101 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 103 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
102 DRM_DEBUG("Enabled hardware status page\n"); 104 DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n");
103 return 0; 105 return 0;
104} 106}
105 107
@@ -185,7 +187,8 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
185 master_priv->sarea_priv = (drm_i915_sarea_t *) 187 master_priv->sarea_priv = (drm_i915_sarea_t *)
186 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset); 188 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
187 } else { 189 } else {
188 DRM_DEBUG("sarea not found assuming DRI2 userspace\n"); 190 DRM_DEBUG_DRIVER(I915_DRV,
191 "sarea not found assuming DRI2 userspace\n");
189 } 192 }
190 193
191 if (init->ring_size != 0) { 194 if (init->ring_size != 0) {
@@ -235,7 +238,7 @@ static int i915_dma_resume(struct drm_device * dev)
235{ 238{
236 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 239 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
237 240
238 DRM_DEBUG("%s\n", __func__); 241 DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__);
239 242
240 if (dev_priv->ring.map.handle == NULL) { 243 if (dev_priv->ring.map.handle == NULL) {
241 DRM_ERROR("can not ioremap virtual address for" 244 DRM_ERROR("can not ioremap virtual address for"
@@ -248,13 +251,14 @@ static int i915_dma_resume(struct drm_device * dev)
248 DRM_ERROR("Can not find hardware status page\n"); 251 DRM_ERROR("Can not find hardware status page\n");
249 return -EINVAL; 252 return -EINVAL;
250 } 253 }
251 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); 254 DRM_DEBUG_DRIVER(I915_DRV, "hw status page @ %p\n",
255 dev_priv->hw_status_page);
252 256
253 if (dev_priv->status_gfx_addr != 0) 257 if (dev_priv->status_gfx_addr != 0)
254 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); 258 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
255 else 259 else
256 I915_WRITE(HWS_PGA, dev_priv->dma_status_page); 260 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
257 DRM_DEBUG("Enabled hardware status page\n"); 261 DRM_DEBUG_DRIVER(I915_DRV, "Enabled hardware status page\n");
258 262
259 return 0; 263 return 0;
260} 264}
@@ -548,10 +552,10 @@ static int i915_dispatch_flip(struct drm_device * dev)
548 if (!master_priv->sarea_priv) 552 if (!master_priv->sarea_priv)
549 return -EINVAL; 553 return -EINVAL;
550 554
551 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", 555 DRM_DEBUG_DRIVER(I915_DRV, "%s: page=%d pfCurrentPage=%d\n",
552 __func__, 556 __func__,
553 dev_priv->current_page, 557 dev_priv->current_page,
554 master_priv->sarea_priv->pf_current_page); 558 master_priv->sarea_priv->pf_current_page);
555 559
556 i915_kernel_lost_context(dev); 560 i915_kernel_lost_context(dev);
557 561
@@ -629,8 +633,9 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
629 return -EINVAL; 633 return -EINVAL;
630 } 634 }
631 635
632 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n", 636 DRM_DEBUG_DRIVER(I915_DRV,
633 batch->start, batch->used, batch->num_cliprects); 637 "i915 batchbuffer, start %x used %d cliprects %d\n",
638 batch->start, batch->used, batch->num_cliprects);
634 639
635 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 640 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
636 641
@@ -678,8 +683,9 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
678 void *batch_data; 683 void *batch_data;
679 int ret; 684 int ret;
680 685
681 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n", 686 DRM_DEBUG_DRIVER(I915_DRV,
682 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects); 687 "i915 cmdbuffer, buf %p sz %d cliprects %d\n",
688 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
683 689
684 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 690 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
685 691
@@ -734,7 +740,7 @@ static int i915_flip_bufs(struct drm_device *dev, void *data,
734{ 740{
735 int ret; 741 int ret;
736 742
737 DRM_DEBUG("%s\n", __func__); 743 DRM_DEBUG_DRIVER(I915_DRV, "%s\n", __func__);
738 744
739 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 745 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
740 746
@@ -777,7 +783,8 @@ static int i915_getparam(struct drm_device *dev, void *data,
777 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; 783 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
778 break; 784 break;
779 default: 785 default:
780 DRM_DEBUG("Unknown parameter %d\n", param->param); 786 DRM_DEBUG_DRIVER(I915_DRV, "Unknown parameter %d\n",
787 param->param);
781 return -EINVAL; 788 return -EINVAL;
782 } 789 }
783 790
@@ -817,7 +824,8 @@ static int i915_setparam(struct drm_device *dev, void *data,
817 dev_priv->fence_reg_start = param->value; 824 dev_priv->fence_reg_start = param->value;
818 break; 825 break;
819 default: 826 default:
820 DRM_DEBUG("unknown parameter %d\n", param->param); 827 DRM_DEBUG_DRIVER(I915_DRV, "unknown parameter %d\n",
828 param->param);
821 return -EINVAL; 829 return -EINVAL;
822 } 830 }
823 831
@@ -865,9 +873,10 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
865 873
866 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 874 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
867 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); 875 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
868 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n", 876 DRM_DEBUG_DRIVER(I915_DRV, "load hws HWS_PGA with gfx mem 0x%x\n",
869 dev_priv->status_gfx_addr); 877 dev_priv->status_gfx_addr);
870 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); 878 DRM_DEBUG_DRIVER(I915_DRV, "load hws at %p\n",
879 dev_priv->hw_status_page);
871 return 0; 880 return 0;
872} 881}
873 882
@@ -922,7 +931,7 @@ static int i915_probe_agp(struct drm_device *dev, unsigned long *aperture_size,
922 * Some of the preallocated space is taken by the GTT 931 * Some of the preallocated space is taken by the GTT
923 * and popup. GTT is 1K per MB of aperture size, and popup is 4K. 932 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
924 */ 933 */
925 if (IS_G4X(dev) || IS_IGD(dev)) 934 if (IS_G4X(dev) || IS_IGD(dev) || IS_IGDNG(dev))
926 overhead = 4096; 935 overhead = 4096;
927 else 936 else
928 overhead = (*aperture_size / 1024) + 4096; 937 overhead = (*aperture_size / 1024) + 4096;
@@ -1153,8 +1162,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1153#endif 1162#endif
1154 1163
1155 dev->driver->get_vblank_counter = i915_get_vblank_counter; 1164 dev->driver->get_vblank_counter = i915_get_vblank_counter;
1156 if (IS_GM45(dev)) 1165 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1166 if (IS_G4X(dev) || IS_IGDNG(dev)) {
1167 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1157 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 1168 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1169 }
1158 1170
1159 i915_gem_load(dev); 1171 i915_gem_load(dev);
1160 1172
@@ -1198,7 +1210,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1198 } 1210 }
1199 1211
1200 /* Must be done after probing outputs */ 1212 /* Must be done after probing outputs */
1201 intel_opregion_init(dev, 0); 1213 /* FIXME: verify on IGDNG */
1214 if (!IS_IGDNG(dev))
1215 intel_opregion_init(dev, 0);
1202 1216
1203 return 0; 1217 return 0;
1204 1218
@@ -1232,7 +1246,8 @@ int i915_driver_unload(struct drm_device *dev)
1232 if (dev_priv->regs != NULL) 1246 if (dev_priv->regs != NULL)
1233 iounmap(dev_priv->regs); 1247 iounmap(dev_priv->regs);
1234 1248
1235 intel_opregion_free(dev, 0); 1249 if (!IS_IGDNG(dev))
1250 intel_opregion_free(dev, 0);
1236 1251
1237 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1252 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1238 intel_modeset_cleanup(dev); 1253 intel_modeset_cleanup(dev);
@@ -1256,7 +1271,7 @@ int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1256{ 1271{
1257 struct drm_i915_file_private *i915_file_priv; 1272 struct drm_i915_file_private *i915_file_priv;
1258 1273
1259 DRM_DEBUG("\n"); 1274 DRM_DEBUG_DRIVER(I915_DRV, "\n");
1260 i915_file_priv = (struct drm_i915_file_private *) 1275 i915_file_priv = (struct drm_i915_file_private *)
1261 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES); 1276 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
1262 1277
@@ -1265,8 +1280,7 @@ int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1265 1280
1266 file_priv->driver_priv = i915_file_priv; 1281 file_priv->driver_priv = i915_file_priv;
1267 1282
1268 i915_file_priv->mm.last_gem_seqno = 0; 1283 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1269 i915_file_priv->mm.last_gem_throttle_seqno = 0;
1270 1284
1271 return 0; 1285 return 0;
1272} 1286}
@@ -1303,6 +1317,7 @@ void i915_driver_lastclose(struct drm_device * dev)
1303void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) 1317void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1304{ 1318{
1305 drm_i915_private_t *dev_priv = dev->dev_private; 1319 drm_i915_private_t *dev_priv = dev->dev_private;
1320 i915_gem_release(dev, file_priv);
1306 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 1321 if (!drm_core_check_feature(dev, DRIVER_MODESET))
1307 i915_mem_release(dev, file_priv, dev_priv->agp_heap); 1322 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1308} 1323}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c431fa54bbb5..8ef6bcec211b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -126,6 +126,13 @@ struct drm_i915_fence_reg {
126 struct drm_gem_object *obj; 126 struct drm_gem_object *obj;
127}; 127};
128 128
129struct sdvo_device_mapping {
130 u8 dvo_port;
131 u8 slave_addr;
132 u8 dvo_wiring;
133 u8 initialized;
134};
135
129typedef struct drm_i915_private { 136typedef struct drm_i915_private {
130 struct drm_device *dev; 137 struct drm_device *dev;
131 138
@@ -143,6 +150,8 @@ typedef struct drm_i915_private {
143 drm_local_map_t hws_map; 150 drm_local_map_t hws_map;
144 struct drm_gem_object *hws_obj; 151 struct drm_gem_object *hws_obj;
145 152
153 struct resource mch_res;
154
146 unsigned int cpp; 155 unsigned int cpp;
147 int back_offset; 156 int back_offset;
148 int front_offset; 157 int front_offset;
@@ -158,6 +167,11 @@ typedef struct drm_i915_private {
158 /** Cached value of IMR to avoid reads in updating the bitfield */ 167 /** Cached value of IMR to avoid reads in updating the bitfield */
159 u32 irq_mask_reg; 168 u32 irq_mask_reg;
160 u32 pipestat[2]; 169 u32 pipestat[2];
170 /** splitted irq regs for graphics and display engine on IGDNG,
171 irq_mask_reg is still used for display irq. */
172 u32 gt_irq_mask_reg;
173 u32 gt_irq_enable_reg;
174 u32 de_irq_enable_reg;
161 175
162 u32 hotplug_supported_mask; 176 u32 hotplug_supported_mask;
163 struct work_struct hotplug_work; 177 struct work_struct hotplug_work;
@@ -285,6 +299,13 @@ typedef struct drm_i915_private {
285 u8 saveDACMASK; 299 u8 saveDACMASK;
286 u8 saveCR[37]; 300 u8 saveCR[37];
287 uint64_t saveFENCE[16]; 301 uint64_t saveFENCE[16];
302 u32 saveCURACNTR;
303 u32 saveCURAPOS;
304 u32 saveCURABASE;
305 u32 saveCURBCNTR;
306 u32 saveCURBPOS;
307 u32 saveCURBBASE;
308 u32 saveCURSIZE;
288 309
289 struct { 310 struct {
290 struct drm_mm gtt_space; 311 struct drm_mm gtt_space;
@@ -382,6 +403,7 @@ typedef struct drm_i915_private {
382 /* storage for physical objects */ 403 /* storage for physical objects */
383 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 404 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
384 } mm; 405 } mm;
406 struct sdvo_device_mapping sdvo_mappings[2];
385} drm_i915_private_t; 407} drm_i915_private_t;
386 408
387/** driver private structure attached to each drm_gem_object */ 409/** driver private structure attached to each drm_gem_object */
@@ -491,13 +513,16 @@ struct drm_i915_gem_request {
491 /** Time at which this request was emitted, in jiffies. */ 513 /** Time at which this request was emitted, in jiffies. */
492 unsigned long emitted_jiffies; 514 unsigned long emitted_jiffies;
493 515
516 /** global list entry for this request */
494 struct list_head list; 517 struct list_head list;
518
519 /** file_priv list entry for this request */
520 struct list_head client_list;
495}; 521};
496 522
497struct drm_i915_file_private { 523struct drm_i915_file_private {
498 struct { 524 struct {
499 uint32_t last_gem_seqno; 525 struct list_head request_list;
500 uint32_t last_gem_throttle_seqno;
501 } mm; 526 } mm;
502}; 527};
503 528
@@ -642,6 +667,7 @@ void i915_gem_detach_phys_object(struct drm_device *dev,
642void i915_gem_free_all_phys_object(struct drm_device *dev); 667void i915_gem_free_all_phys_object(struct drm_device *dev);
643int i915_gem_object_get_pages(struct drm_gem_object *obj); 668int i915_gem_object_get_pages(struct drm_gem_object *obj);
644void i915_gem_object_put_pages(struct drm_gem_object *obj); 669void i915_gem_object_put_pages(struct drm_gem_object *obj);
670void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
645 671
646/* i915_gem_tiling.c */ 672/* i915_gem_tiling.c */
647void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 673void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
@@ -785,7 +811,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
785 (dev)->pci_device == 0x2E02 || \ 811 (dev)->pci_device == 0x2E02 || \
786 (dev)->pci_device == 0x2E12 || \ 812 (dev)->pci_device == 0x2E12 || \
787 (dev)->pci_device == 0x2E22 || \ 813 (dev)->pci_device == 0x2E22 || \
788 (dev)->pci_device == 0x2E32) 814 (dev)->pci_device == 0x2E32 || \
815 (dev)->pci_device == 0x0042 || \
816 (dev)->pci_device == 0x0046)
789 817
790#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \ 818#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
791 (dev)->pci_device == 0x2A12) 819 (dev)->pci_device == 0x2A12)
@@ -807,20 +835,26 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
807 (dev)->pci_device == 0x29D2 || \ 835 (dev)->pci_device == 0x29D2 || \
808 (IS_IGD(dev))) 836 (IS_IGD(dev)))
809 837
838#define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
839#define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
840#define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
841
810#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 842#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
811 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 843 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
844 IS_IGDNG(dev))
812 845
813#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 846#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
814 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \ 847 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
815 IS_IGD(dev)) 848 IS_IGD(dev) || IS_IGDNG_M(dev))
816 849
817#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 850#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
851 IS_IGDNG(dev))
818/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 852/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
819 * rows, which changed the alignment requirements and fence programming. 853 * rows, which changed the alignment requirements and fence programming.
820 */ 854 */
821#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ 855#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
822 IS_I915GM(dev))) 856 IS_I915GM(dev)))
823#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev)) 857#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
824#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev)) 858#define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
825 859
826#define PRIMARY_RINGBUFFER_SIZE (128*1024) 860#define PRIMARY_RINGBUFFER_SIZE (128*1024)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 39f5c658ef5e..c0ae6bbbd9b5 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -989,10 +989,10 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
989 return -ENODEV; 989 return -ENODEV;
990 990
991 /* Only handle setting domains to types used by the CPU. */ 991 /* Only handle setting domains to types used by the CPU. */
992 if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 992 if (write_domain & I915_GEM_GPU_DOMAINS)
993 return -EINVAL; 993 return -EINVAL;
994 994
995 if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 995 if (read_domains & I915_GEM_GPU_DOMAINS)
996 return -EINVAL; 996 return -EINVAL;
997 997
998 /* Having something in the write domain implies it's in the read 998 /* Having something in the write domain implies it's in the read
@@ -1481,14 +1481,19 @@ i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1481 * Returned sequence numbers are nonzero on success. 1481 * Returned sequence numbers are nonzero on success.
1482 */ 1482 */
1483static uint32_t 1483static uint32_t
1484i915_add_request(struct drm_device *dev, uint32_t flush_domains) 1484i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1485 uint32_t flush_domains)
1485{ 1486{
1486 drm_i915_private_t *dev_priv = dev->dev_private; 1487 drm_i915_private_t *dev_priv = dev->dev_private;
1488 struct drm_i915_file_private *i915_file_priv = NULL;
1487 struct drm_i915_gem_request *request; 1489 struct drm_i915_gem_request *request;
1488 uint32_t seqno; 1490 uint32_t seqno;
1489 int was_empty; 1491 int was_empty;
1490 RING_LOCALS; 1492 RING_LOCALS;
1491 1493
1494 if (file_priv != NULL)
1495 i915_file_priv = file_priv->driver_priv;
1496
1492 request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER); 1497 request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
1493 if (request == NULL) 1498 if (request == NULL)
1494 return 0; 1499 return 0;
@@ -1515,6 +1520,12 @@ i915_add_request(struct drm_device *dev, uint32_t flush_domains)
1515 request->emitted_jiffies = jiffies; 1520 request->emitted_jiffies = jiffies;
1516 was_empty = list_empty(&dev_priv->mm.request_list); 1521 was_empty = list_empty(&dev_priv->mm.request_list);
1517 list_add_tail(&request->list, &dev_priv->mm.request_list); 1522 list_add_tail(&request->list, &dev_priv->mm.request_list);
1523 if (i915_file_priv) {
1524 list_add_tail(&request->client_list,
1525 &i915_file_priv->mm.request_list);
1526 } else {
1527 INIT_LIST_HEAD(&request->client_list);
1528 }
1518 1529
1519 /* Associate any objects on the flushing list matching the write 1530 /* Associate any objects on the flushing list matching the write
1520 * domain we're flushing with our flush. 1531 * domain we're flushing with our flush.
@@ -1664,6 +1675,7 @@ i915_gem_retire_requests(struct drm_device *dev)
1664 i915_gem_retire_request(dev, request); 1675 i915_gem_retire_request(dev, request);
1665 1676
1666 list_del(&request->list); 1677 list_del(&request->list);
1678 list_del(&request->client_list);
1667 drm_free(request, sizeof(*request), DRM_MEM_DRIVER); 1679 drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1668 } else 1680 } else
1669 break; 1681 break;
@@ -1702,7 +1714,10 @@ i915_wait_request(struct drm_device *dev, uint32_t seqno)
1702 BUG_ON(seqno == 0); 1714 BUG_ON(seqno == 0);
1703 1715
1704 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { 1716 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1705 ier = I915_READ(IER); 1717 if (IS_IGDNG(dev))
1718 ier = I915_READ(DEIER) | I915_READ(GTIER);
1719 else
1720 ier = I915_READ(IER);
1706 if (!ier) { 1721 if (!ier) {
1707 DRM_ERROR("something (likely vbetool) disabled " 1722 DRM_ERROR("something (likely vbetool) disabled "
1708 "interrupts, re-enabling\n"); 1723 "interrupts, re-enabling\n");
@@ -1754,8 +1769,7 @@ i915_gem_flush(struct drm_device *dev,
1754 if (flush_domains & I915_GEM_DOMAIN_CPU) 1769 if (flush_domains & I915_GEM_DOMAIN_CPU)
1755 drm_agp_chipset_flush(dev); 1770 drm_agp_chipset_flush(dev);
1756 1771
1757 if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU | 1772 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
1758 I915_GEM_DOMAIN_GTT)) {
1759 /* 1773 /*
1760 * read/write caches: 1774 * read/write caches:
1761 * 1775 *
@@ -1977,7 +1991,7 @@ i915_gem_evict_something(struct drm_device *dev)
1977 i915_gem_flush(dev, 1991 i915_gem_flush(dev,
1978 obj->write_domain, 1992 obj->write_domain,
1979 obj->write_domain); 1993 obj->write_domain);
1980 i915_add_request(dev, obj->write_domain); 1994 i915_add_request(dev, NULL, obj->write_domain);
1981 1995
1982 obj = NULL; 1996 obj = NULL;
1983 continue; 1997 continue;
@@ -1991,7 +2005,7 @@ i915_gem_evict_something(struct drm_device *dev)
1991 /* If we didn't do any of the above, there's nothing to be done 2005 /* If we didn't do any of the above, there's nothing to be done
1992 * and we just can't fit it in. 2006 * and we just can't fit it in.
1993 */ 2007 */
1994 return -ENOMEM; 2008 return -ENOSPC;
1995 } 2009 }
1996 return ret; 2010 return ret;
1997} 2011}
@@ -2006,7 +2020,7 @@ i915_gem_evict_everything(struct drm_device *dev)
2006 if (ret != 0) 2020 if (ret != 0)
2007 break; 2021 break;
2008 } 2022 }
2009 if (ret == -ENOMEM) 2023 if (ret == -ENOSPC)
2010 return 0; 2024 return 0;
2011 return ret; 2025 return ret;
2012} 2026}
@@ -2215,7 +2229,7 @@ try_again:
2215 loff_t offset; 2229 loff_t offset;
2216 2230
2217 if (avail == 0) 2231 if (avail == 0)
2218 return -ENOMEM; 2232 return -ENOSPC;
2219 2233
2220 for (i = dev_priv->fence_reg_start; 2234 for (i = dev_priv->fence_reg_start;
2221 i < dev_priv->num_fence_regs; i++) { 2235 i < dev_priv->num_fence_regs; i++) {
@@ -2248,7 +2262,7 @@ try_again:
2248 i915_gem_flush(dev, 2262 i915_gem_flush(dev,
2249 I915_GEM_GPU_DOMAINS, 2263 I915_GEM_GPU_DOMAINS,
2250 I915_GEM_GPU_DOMAINS); 2264 I915_GEM_GPU_DOMAINS);
2251 seqno = i915_add_request(dev, 2265 seqno = i915_add_request(dev, NULL,
2252 I915_GEM_GPU_DOMAINS); 2266 I915_GEM_GPU_DOMAINS);
2253 if (seqno == 0) 2267 if (seqno == 0)
2254 return -ENOMEM; 2268 return -ENOMEM;
@@ -2364,7 +2378,7 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2364 spin_unlock(&dev_priv->mm.active_list_lock); 2378 spin_unlock(&dev_priv->mm.active_list_lock);
2365 if (lists_empty) { 2379 if (lists_empty) {
2366 DRM_ERROR("GTT full, but LRU list empty\n"); 2380 DRM_ERROR("GTT full, but LRU list empty\n");
2367 return -ENOMEM; 2381 return -ENOSPC;
2368 } 2382 }
2369 2383
2370 ret = i915_gem_evict_something(dev); 2384 ret = i915_gem_evict_something(dev);
@@ -2409,8 +2423,8 @@ i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2409 * wasn't in the GTT, there shouldn't be any way it could have been in 2423 * wasn't in the GTT, there shouldn't be any way it could have been in
2410 * a GPU cache 2424 * a GPU cache
2411 */ 2425 */
2412 BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); 2426 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2413 BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); 2427 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2414 2428
2415 return 0; 2429 return 0;
2416} 2430}
@@ -2452,7 +2466,7 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2452 2466
2453 /* Queue the GPU write cache flushing we need. */ 2467 /* Queue the GPU write cache flushing we need. */
2454 i915_gem_flush(dev, 0, obj->write_domain); 2468 i915_gem_flush(dev, 0, obj->write_domain);
2455 seqno = i915_add_request(dev, obj->write_domain); 2469 seqno = i915_add_request(dev, NULL, obj->write_domain);
2456 obj->write_domain = 0; 2470 obj->write_domain = 0;
2457 i915_gem_object_move_to_active(obj, seqno); 2471 i915_gem_object_move_to_active(obj, seqno);
2458} 2472}
@@ -3035,20 +3049,12 @@ i915_dispatch_gem_execbuffer(struct drm_device *dev,
3035 drm_i915_private_t *dev_priv = dev->dev_private; 3049 drm_i915_private_t *dev_priv = dev->dev_private;
3036 int nbox = exec->num_cliprects; 3050 int nbox = exec->num_cliprects;
3037 int i = 0, count; 3051 int i = 0, count;
3038 uint32_t exec_start, exec_len; 3052 uint32_t exec_start, exec_len;
3039 RING_LOCALS; 3053 RING_LOCALS;
3040 3054
3041 exec_start = (uint32_t) exec_offset + exec->batch_start_offset; 3055 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3042 exec_len = (uint32_t) exec->batch_len; 3056 exec_len = (uint32_t) exec->batch_len;
3043 3057
3044 if ((exec_start | exec_len) & 0x7) {
3045 DRM_ERROR("alignment\n");
3046 return -EINVAL;
3047 }
3048
3049 if (!exec_start)
3050 return -EINVAL;
3051
3052 count = nbox ? nbox : 1; 3058 count = nbox ? nbox : 1;
3053 3059
3054 for (i = 0; i < count; i++) { 3060 for (i = 0; i < count; i++) {
@@ -3089,6 +3095,10 @@ i915_dispatch_gem_execbuffer(struct drm_device *dev,
3089/* Throttle our rendering by waiting until the ring has completed our requests 3095/* Throttle our rendering by waiting until the ring has completed our requests
3090 * emitted over 20 msec ago. 3096 * emitted over 20 msec ago.
3091 * 3097 *
3098 * Note that if we were to use the current jiffies each time around the loop,
3099 * we wouldn't escape the function with any frames outstanding if the time to
3100 * render a frame was over 20ms.
3101 *
3092 * This should get us reasonable parallelism between CPU and GPU but also 3102 * This should get us reasonable parallelism between CPU and GPU but also
3093 * relatively low latency when blocking on a particular request to finish. 3103 * relatively low latency when blocking on a particular request to finish.
3094 */ 3104 */
@@ -3097,15 +3107,25 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3097{ 3107{
3098 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; 3108 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3099 int ret = 0; 3109 int ret = 0;
3100 uint32_t seqno; 3110 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3101 3111
3102 mutex_lock(&dev->struct_mutex); 3112 mutex_lock(&dev->struct_mutex);
3103 seqno = i915_file_priv->mm.last_gem_throttle_seqno; 3113 while (!list_empty(&i915_file_priv->mm.request_list)) {
3104 i915_file_priv->mm.last_gem_throttle_seqno = 3114 struct drm_i915_gem_request *request;
3105 i915_file_priv->mm.last_gem_seqno; 3115
3106 if (seqno) 3116 request = list_first_entry(&i915_file_priv->mm.request_list,
3107 ret = i915_wait_request(dev, seqno); 3117 struct drm_i915_gem_request,
3118 client_list);
3119
3120 if (time_after_eq(request->emitted_jiffies, recent_enough))
3121 break;
3122
3123 ret = i915_wait_request(dev, request->seqno);
3124 if (ret != 0)
3125 break;
3126 }
3108 mutex_unlock(&dev->struct_mutex); 3127 mutex_unlock(&dev->struct_mutex);
3128
3109 return ret; 3129 return ret;
3110} 3130}
3111 3131
@@ -3182,12 +3202,29 @@ err:
3182 return ret; 3202 return ret;
3183} 3203}
3184 3204
3205static int
3206i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3207 uint64_t exec_offset)
3208{
3209 uint32_t exec_start, exec_len;
3210
3211 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3212 exec_len = (uint32_t) exec->batch_len;
3213
3214 if ((exec_start | exec_len) & 0x7)
3215 return -EINVAL;
3216
3217 if (!exec_start)
3218 return -EINVAL;
3219
3220 return 0;
3221}
3222
3185int 3223int
3186i915_gem_execbuffer(struct drm_device *dev, void *data, 3224i915_gem_execbuffer(struct drm_device *dev, void *data,
3187 struct drm_file *file_priv) 3225 struct drm_file *file_priv)
3188{ 3226{
3189 drm_i915_private_t *dev_priv = dev->dev_private; 3227 drm_i915_private_t *dev_priv = dev->dev_private;
3190 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3191 struct drm_i915_gem_execbuffer *args = data; 3228 struct drm_i915_gem_execbuffer *args = data;
3192 struct drm_i915_gem_exec_object *exec_list = NULL; 3229 struct drm_i915_gem_exec_object *exec_list = NULL;
3193 struct drm_gem_object **object_list = NULL; 3230 struct drm_gem_object **object_list = NULL;
@@ -3312,7 +3349,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3312 break; 3349 break;
3313 3350
3314 /* error other than GTT full, or we've already tried again */ 3351 /* error other than GTT full, or we've already tried again */
3315 if (ret != -ENOMEM || pin_tries >= 1) { 3352 if (ret != -ENOSPC || pin_tries >= 1) {
3316 if (ret != -ERESTARTSYS) 3353 if (ret != -ERESTARTSYS)
3317 DRM_ERROR("Failed to pin buffers %d\n", ret); 3354 DRM_ERROR("Failed to pin buffers %d\n", ret);
3318 goto err; 3355 goto err;
@@ -3331,8 +3368,20 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3331 3368
3332 /* Set the pending read domains for the batch buffer to COMMAND */ 3369 /* Set the pending read domains for the batch buffer to COMMAND */
3333 batch_obj = object_list[args->buffer_count-1]; 3370 batch_obj = object_list[args->buffer_count-1];
3334 batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND; 3371 if (batch_obj->pending_write_domain) {
3335 batch_obj->pending_write_domain = 0; 3372 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3373 ret = -EINVAL;
3374 goto err;
3375 }
3376 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3377
3378 /* Sanity check the batch buffer, prior to moving objects */
3379 exec_offset = exec_list[args->buffer_count - 1].offset;
3380 ret = i915_gem_check_execbuffer (args, exec_offset);
3381 if (ret != 0) {
3382 DRM_ERROR("execbuf with invalid offset/length\n");
3383 goto err;
3384 }
3336 3385
3337 i915_verify_inactive(dev, __FILE__, __LINE__); 3386 i915_verify_inactive(dev, __FILE__, __LINE__);
3338 3387
@@ -3363,7 +3412,8 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3363 dev->invalidate_domains, 3412 dev->invalidate_domains,
3364 dev->flush_domains); 3413 dev->flush_domains);
3365 if (dev->flush_domains) 3414 if (dev->flush_domains)
3366 (void)i915_add_request(dev, dev->flush_domains); 3415 (void)i915_add_request(dev, file_priv,
3416 dev->flush_domains);
3367 } 3417 }
3368 3418
3369 for (i = 0; i < args->buffer_count; i++) { 3419 for (i = 0; i < args->buffer_count; i++) {
@@ -3381,8 +3431,6 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3381 } 3431 }
3382#endif 3432#endif
3383 3433
3384 exec_offset = exec_list[args->buffer_count - 1].offset;
3385
3386#if WATCH_EXEC 3434#if WATCH_EXEC
3387 i915_gem_dump_object(batch_obj, 3435 i915_gem_dump_object(batch_obj,
3388 args->batch_len, 3436 args->batch_len,
@@ -3412,9 +3460,8 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
3412 * *some* interrupts representing completion of buffers that we can 3460 * *some* interrupts representing completion of buffers that we can
3413 * wait on when trying to clear up gtt space). 3461 * wait on when trying to clear up gtt space).
3414 */ 3462 */
3415 seqno = i915_add_request(dev, flush_domains); 3463 seqno = i915_add_request(dev, file_priv, flush_domains);
3416 BUG_ON(seqno == 0); 3464 BUG_ON(seqno == 0);
3417 i915_file_priv->mm.last_gem_seqno = seqno;
3418 for (i = 0; i < args->buffer_count; i++) { 3465 for (i = 0; i < args->buffer_count; i++) {
3419 struct drm_gem_object *obj = object_list[i]; 3466 struct drm_gem_object *obj = object_list[i];
3420 3467
@@ -3520,8 +3567,7 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3520 atomic_inc(&dev->pin_count); 3567 atomic_inc(&dev->pin_count);
3521 atomic_add(obj->size, &dev->pin_memory); 3568 atomic_add(obj->size, &dev->pin_memory);
3522 if (!obj_priv->active && 3569 if (!obj_priv->active &&
3523 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | 3570 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
3524 I915_GEM_DOMAIN_GTT)) == 0 &&
3525 !list_empty(&obj_priv->list)) 3571 !list_empty(&obj_priv->list))
3526 list_del_init(&obj_priv->list); 3572 list_del_init(&obj_priv->list);
3527 } 3573 }
@@ -3548,8 +3594,7 @@ i915_gem_object_unpin(struct drm_gem_object *obj)
3548 */ 3594 */
3549 if (obj_priv->pin_count == 0) { 3595 if (obj_priv->pin_count == 0) {
3550 if (!obj_priv->active && 3596 if (!obj_priv->active &&
3551 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | 3597 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
3552 I915_GEM_DOMAIN_GTT)) == 0)
3553 list_move_tail(&obj_priv->list, 3598 list_move_tail(&obj_priv->list,
3554 &dev_priv->mm.inactive_list); 3599 &dev_priv->mm.inactive_list);
3555 atomic_dec(&dev->pin_count); 3600 atomic_dec(&dev->pin_count);
@@ -3653,15 +3698,14 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3653 struct drm_gem_object *obj; 3698 struct drm_gem_object *obj;
3654 struct drm_i915_gem_object *obj_priv; 3699 struct drm_i915_gem_object *obj_priv;
3655 3700
3656 mutex_lock(&dev->struct_mutex);
3657 obj = drm_gem_object_lookup(dev, file_priv, args->handle); 3701 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3658 if (obj == NULL) { 3702 if (obj == NULL) {
3659 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", 3703 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
3660 args->handle); 3704 args->handle);
3661 mutex_unlock(&dev->struct_mutex);
3662 return -EBADF; 3705 return -EBADF;
3663 } 3706 }
3664 3707
3708 mutex_lock(&dev->struct_mutex);
3665 /* Update the active list for the hardware's current position. 3709 /* Update the active list for the hardware's current position.
3666 * Otherwise this only updates on a delayed timer or when irqs are 3710 * Otherwise this only updates on a delayed timer or when irqs are
3667 * actually unmasked, and our working set ends up being larger than 3711 * actually unmasked, and our working set ends up being larger than
@@ -3800,9 +3844,8 @@ i915_gem_idle(struct drm_device *dev)
3800 3844
3801 /* Flush the GPU along with all non-CPU write domains 3845 /* Flush the GPU along with all non-CPU write domains
3802 */ 3846 */
3803 i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT), 3847 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
3804 ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); 3848 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
3805 seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
3806 3849
3807 if (seqno == 0) { 3850 if (seqno == 0) {
3808 mutex_unlock(&dev->struct_mutex); 3851 mutex_unlock(&dev->struct_mutex);
@@ -4352,3 +4395,17 @@ i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4352 drm_agp_chipset_flush(dev); 4395 drm_agp_chipset_flush(dev);
4353 return 0; 4396 return 0;
4354} 4397}
4398
4399void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4400{
4401 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4402
4403 /* Clean up our request list when the client is going away, so that
4404 * later retire_requests won't dereference our soon-to-be-gone
4405 * file_priv.
4406 */
4407 mutex_lock(&dev->struct_mutex);
4408 while (!list_empty(&i915_file_priv->mm.request_list))
4409 list_del_init(i915_file_priv->mm.request_list.next);
4410 mutex_unlock(&dev->struct_mutex);
4411}
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 540dd336e6ec..9a05cadaa4ad 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -25,6 +25,8 @@
25 * 25 *
26 */ 26 */
27 27
28#include <linux/acpi.h>
29#include <linux/pnp.h>
28#include "linux/string.h" 30#include "linux/string.h"
29#include "linux/bitops.h" 31#include "linux/bitops.h"
30#include "drmP.h" 32#include "drmP.h"
@@ -81,6 +83,143 @@
81 * to match what the GPU expects. 83 * to match what the GPU expects.
82 */ 84 */
83 85
86#define MCHBAR_I915 0x44
87#define MCHBAR_I965 0x48
88#define MCHBAR_SIZE (4*4096)
89
90#define DEVEN_REG 0x54
91#define DEVEN_MCHBAR_EN (1 << 28)
92
93/* Allocate space for the MCH regs if needed, return nonzero on error */
94static int
95intel_alloc_mchbar_resource(struct drm_device *dev)
96{
97 struct pci_dev *bridge_dev;
98 drm_i915_private_t *dev_priv = dev->dev_private;
99 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
100 u32 temp_lo, temp_hi = 0;
101 u64 mchbar_addr;
102 int ret = 0;
103
104 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
105 if (!bridge_dev) {
106 DRM_DEBUG("no bridge dev?!\n");
107 ret = -ENODEV;
108 goto out;
109 }
110
111 if (IS_I965G(dev))
112 pci_read_config_dword(bridge_dev, reg + 4, &temp_hi);
113 pci_read_config_dword(bridge_dev, reg, &temp_lo);
114 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
115
116 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
117 if (mchbar_addr &&
118 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
119 ret = 0;
120 goto out_put;
121 }
122
123 /* Get some space for it */
124 ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res,
125 MCHBAR_SIZE, MCHBAR_SIZE,
126 PCIBIOS_MIN_MEM,
127 0, pcibios_align_resource,
128 bridge_dev);
129 if (ret) {
130 DRM_DEBUG("failed bus alloc: %d\n", ret);
131 dev_priv->mch_res.start = 0;
132 goto out_put;
133 }
134
135 if (IS_I965G(dev))
136 pci_write_config_dword(bridge_dev, reg + 4,
137 upper_32_bits(dev_priv->mch_res.start));
138
139 pci_write_config_dword(bridge_dev, reg,
140 lower_32_bits(dev_priv->mch_res.start));
141out_put:
142 pci_dev_put(bridge_dev);
143out:
144 return ret;
145}
146
147/* Setup MCHBAR if possible, return true if we should disable it again */
148static bool
149intel_setup_mchbar(struct drm_device *dev)
150{
151 struct pci_dev *bridge_dev;
152 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
153 u32 temp;
154 bool need_disable = false, enabled;
155
156 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
157 if (!bridge_dev) {
158 DRM_DEBUG("no bridge dev?!\n");
159 goto out;
160 }
161
162 if (IS_I915G(dev) || IS_I915GM(dev)) {
163 pci_read_config_dword(bridge_dev, DEVEN_REG, &temp);
164 enabled = !!(temp & DEVEN_MCHBAR_EN);
165 } else {
166 pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
167 enabled = temp & 1;
168 }
169
170 /* If it's already enabled, don't have to do anything */
171 if (enabled)
172 goto out_put;
173
174 if (intel_alloc_mchbar_resource(dev))
175 goto out_put;
176
177 need_disable = true;
178
179 /* Space is allocated or reserved, so enable it. */
180 if (IS_I915G(dev) || IS_I915GM(dev)) {
181 pci_write_config_dword(bridge_dev, DEVEN_REG,
182 temp | DEVEN_MCHBAR_EN);
183 } else {
184 pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
185 pci_write_config_dword(bridge_dev, mchbar_reg, temp | 1);
186 }
187out_put:
188 pci_dev_put(bridge_dev);
189out:
190 return need_disable;
191}
192
193static void
194intel_teardown_mchbar(struct drm_device *dev, bool disable)
195{
196 drm_i915_private_t *dev_priv = dev->dev_private;
197 struct pci_dev *bridge_dev;
198 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
199 u32 temp;
200
201 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
202 if (!bridge_dev) {
203 DRM_DEBUG("no bridge dev?!\n");
204 return;
205 }
206
207 if (disable) {
208 if (IS_I915G(dev) || IS_I915GM(dev)) {
209 pci_read_config_dword(bridge_dev, DEVEN_REG, &temp);
210 temp &= ~DEVEN_MCHBAR_EN;
211 pci_write_config_dword(bridge_dev, DEVEN_REG, temp);
212 } else {
213 pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
214 temp &= ~1;
215 pci_write_config_dword(bridge_dev, mchbar_reg, temp);
216 }
217 }
218
219 if (dev_priv->mch_res.start)
220 release_resource(&dev_priv->mch_res);
221}
222
84/** 223/**
85 * Detects bit 6 swizzling of address lookup between IGD access and CPU 224 * Detects bit 6 swizzling of address lookup between IGD access and CPU
86 * access through main memory. 225 * access through main memory.
@@ -91,6 +230,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
91 drm_i915_private_t *dev_priv = dev->dev_private; 230 drm_i915_private_t *dev_priv = dev->dev_private;
92 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 231 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
93 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 232 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
233 bool need_disable;
94 234
95 if (!IS_I9XX(dev)) { 235 if (!IS_I9XX(dev)) {
96 /* As far as we know, the 865 doesn't have these bit 6 236 /* As far as we know, the 865 doesn't have these bit 6
@@ -101,6 +241,9 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
101 } else if (IS_MOBILE(dev)) { 241 } else if (IS_MOBILE(dev)) {
102 uint32_t dcc; 242 uint32_t dcc;
103 243
244 /* Try to make sure MCHBAR is enabled before poking at it */
245 need_disable = intel_setup_mchbar(dev);
246
104 /* On mobile 9xx chipsets, channel interleave by the CPU is 247 /* On mobile 9xx chipsets, channel interleave by the CPU is
105 * determined by DCC. For single-channel, neither the CPU 248 * determined by DCC. For single-channel, neither the CPU
106 * nor the GPU do swizzling. For dual channel interleaved, 249 * nor the GPU do swizzling. For dual channel interleaved,
@@ -140,6 +283,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
140 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; 283 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
141 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; 284 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
142 } 285 }
286
287 intel_teardown_mchbar(dev, need_disable);
143 } else { 288 } else {
144 /* The 965, G33, and newer, have a very flexible memory 289 /* The 965, G33, and newer, have a very flexible memory
145 * configuration. It will enable dual-channel mode 290 * configuration. It will enable dual-channel mode
@@ -170,6 +315,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
170 } 315 }
171 } 316 }
172 317
318 /* FIXME: check with memory config on IGDNG */
319 if (IS_IGDNG(dev)) {
320 DRM_ERROR("disable tiling on IGDNG...\n");
321 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
322 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
323 }
324
173 dev_priv->mm.bit_6_swizzle_x = swizzle_x; 325 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
174 dev_priv->mm.bit_6_swizzle_y = swizzle_y; 326 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
175} 327}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98bb4c878c4e..b86b7b7130c6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -58,6 +58,47 @@
58 DRM_I915_VBLANK_PIPE_B) 58 DRM_I915_VBLANK_PIPE_B)
59 59
60void 60void
61igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
62{
63 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
64 dev_priv->gt_irq_mask_reg &= ~mask;
65 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
66 (void) I915_READ(GTIMR);
67 }
68}
69
70static inline void
71igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
72{
73 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
74 dev_priv->gt_irq_mask_reg |= mask;
75 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
76 (void) I915_READ(GTIMR);
77 }
78}
79
80/* For display hotplug interrupt */
81void
82igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
83{
84 if ((dev_priv->irq_mask_reg & mask) != 0) {
85 dev_priv->irq_mask_reg &= ~mask;
86 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
87 (void) I915_READ(DEIMR);
88 }
89}
90
91static inline void
92igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
93{
94 if ((dev_priv->irq_mask_reg & mask) != mask) {
95 dev_priv->irq_mask_reg |= mask;
96 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
97 (void) I915_READ(DEIMR);
98 }
99}
100
101void
61i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) 102i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
62{ 103{
63 if ((dev_priv->irq_mask_reg & mask) != 0) { 104 if ((dev_priv->irq_mask_reg & mask) != 0) {
@@ -196,6 +237,47 @@ static void i915_hotplug_work_func(struct work_struct *work)
196 drm_sysfs_hotplug_event(dev); 237 drm_sysfs_hotplug_event(dev);
197} 238}
198 239
240irqreturn_t igdng_irq_handler(struct drm_device *dev)
241{
242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
243 int ret = IRQ_NONE;
244 u32 de_iir, gt_iir;
245 u32 new_de_iir, new_gt_iir;
246 struct drm_i915_master_private *master_priv;
247
248 de_iir = I915_READ(DEIIR);
249 gt_iir = I915_READ(GTIIR);
250
251 for (;;) {
252 if (de_iir == 0 && gt_iir == 0)
253 break;
254
255 ret = IRQ_HANDLED;
256
257 I915_WRITE(DEIIR, de_iir);
258 new_de_iir = I915_READ(DEIIR);
259 I915_WRITE(GTIIR, gt_iir);
260 new_gt_iir = I915_READ(GTIIR);
261
262 if (dev->primary->master) {
263 master_priv = dev->primary->master->driver_priv;
264 if (master_priv->sarea_priv)
265 master_priv->sarea_priv->last_dispatch =
266 READ_BREADCRUMB(dev_priv);
267 }
268
269 if (gt_iir & GT_USER_INTERRUPT) {
270 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
271 DRM_WAKEUP(&dev_priv->irq_queue);
272 }
273
274 de_iir = new_de_iir;
275 gt_iir = new_gt_iir;
276 }
277
278 return ret;
279}
280
199irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) 281irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
200{ 282{
201 struct drm_device *dev = (struct drm_device *) arg; 283 struct drm_device *dev = (struct drm_device *) arg;
@@ -212,6 +294,9 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
212 294
213 atomic_inc(&dev_priv->irq_received); 295 atomic_inc(&dev_priv->irq_received);
214 296
297 if (IS_IGDNG(dev))
298 return igdng_irq_handler(dev);
299
215 iir = I915_READ(IIR); 300 iir = I915_READ(IIR);
216 301
217 if (IS_I965G(dev)) { 302 if (IS_I965G(dev)) {
@@ -349,8 +434,12 @@ void i915_user_irq_get(struct drm_device *dev)
349 unsigned long irqflags; 434 unsigned long irqflags;
350 435
351 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 436 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
352 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) 437 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
353 i915_enable_irq(dev_priv, I915_USER_INTERRUPT); 438 if (IS_IGDNG(dev))
439 igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
440 else
441 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
442 }
354 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); 443 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
355} 444}
356 445
@@ -361,8 +450,12 @@ void i915_user_irq_put(struct drm_device *dev)
361 450
362 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 451 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
363 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); 452 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
364 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) 453 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
365 i915_disable_irq(dev_priv, I915_USER_INTERRUPT); 454 if (IS_IGDNG(dev))
455 igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
456 else
457 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
458 }
366 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); 459 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
367} 460}
368 461
@@ -455,6 +548,9 @@ int i915_enable_vblank(struct drm_device *dev, int pipe)
455 if (!(pipeconf & PIPEACONF_ENABLE)) 548 if (!(pipeconf & PIPEACONF_ENABLE))
456 return -EINVAL; 549 return -EINVAL;
457 550
551 if (IS_IGDNG(dev))
552 return 0;
553
458 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 554 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
459 if (IS_I965G(dev)) 555 if (IS_I965G(dev))
460 i915_enable_pipestat(dev_priv, pipe, 556 i915_enable_pipestat(dev_priv, pipe,
@@ -474,6 +570,9 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
474 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 570 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
475 unsigned long irqflags; 571 unsigned long irqflags;
476 572
573 if (IS_IGDNG(dev))
574 return;
575
477 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); 576 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
478 i915_disable_pipestat(dev_priv, pipe, 577 i915_disable_pipestat(dev_priv, pipe,
479 PIPE_VBLANK_INTERRUPT_ENABLE | 578 PIPE_VBLANK_INTERRUPT_ENABLE |
@@ -484,7 +583,9 @@ void i915_disable_vblank(struct drm_device *dev, int pipe)
484void i915_enable_interrupt (struct drm_device *dev) 583void i915_enable_interrupt (struct drm_device *dev)
485{ 584{
486 struct drm_i915_private *dev_priv = dev->dev_private; 585 struct drm_i915_private *dev_priv = dev->dev_private;
487 opregion_enable_asle(dev); 586
587 if (!IS_IGDNG(dev))
588 opregion_enable_asle(dev);
488 dev_priv->irq_enabled = 1; 589 dev_priv->irq_enabled = 1;
489} 590}
490 591
@@ -545,12 +646,65 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
545 646
546/* drm_dma.h hooks 647/* drm_dma.h hooks
547*/ 648*/
649static void igdng_irq_preinstall(struct drm_device *dev)
650{
651 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
652
653 I915_WRITE(HWSTAM, 0xeffe);
654
655 /* XXX hotplug from PCH */
656
657 I915_WRITE(DEIMR, 0xffffffff);
658 I915_WRITE(DEIER, 0x0);
659 (void) I915_READ(DEIER);
660
661 /* and GT */
662 I915_WRITE(GTIMR, 0xffffffff);
663 I915_WRITE(GTIER, 0x0);
664 (void) I915_READ(GTIER);
665}
666
667static int igdng_irq_postinstall(struct drm_device *dev)
668{
669 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
670 /* enable kind of interrupts always enabled */
671 u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */;
672 u32 render_mask = GT_USER_INTERRUPT;
673
674 dev_priv->irq_mask_reg = ~display_mask;
675 dev_priv->de_irq_enable_reg = display_mask;
676
677 /* should always can generate irq */
678 I915_WRITE(DEIIR, I915_READ(DEIIR));
679 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
680 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
681 (void) I915_READ(DEIER);
682
683 /* user interrupt should be enabled, but masked initial */
684 dev_priv->gt_irq_mask_reg = 0xffffffff;
685 dev_priv->gt_irq_enable_reg = render_mask;
686
687 I915_WRITE(GTIIR, I915_READ(GTIIR));
688 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
689 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
690 (void) I915_READ(GTIER);
691
692 return 0;
693}
694
548void i915_driver_irq_preinstall(struct drm_device * dev) 695void i915_driver_irq_preinstall(struct drm_device * dev)
549{ 696{
550 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 697 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
551 698
552 atomic_set(&dev_priv->irq_received, 0); 699 atomic_set(&dev_priv->irq_received, 0);
553 700
701 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
702
703 if (IS_IGDNG(dev)) {
704 igdng_irq_preinstall(dev);
705 return;
706 }
707
554 if (I915_HAS_HOTPLUG(dev)) { 708 if (I915_HAS_HOTPLUG(dev)) {
555 I915_WRITE(PORT_HOTPLUG_EN, 0); 709 I915_WRITE(PORT_HOTPLUG_EN, 0);
556 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 710 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
@@ -562,7 +716,6 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
562 I915_WRITE(IMR, 0xffffffff); 716 I915_WRITE(IMR, 0xffffffff);
563 I915_WRITE(IER, 0x0); 717 I915_WRITE(IER, 0x0);
564 (void) I915_READ(IER); 718 (void) I915_READ(IER);
565 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
566} 719}
567 720
568int i915_driver_irq_postinstall(struct drm_device *dev) 721int i915_driver_irq_postinstall(struct drm_device *dev)
@@ -570,9 +723,12 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
570 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 723 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
571 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; 724 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
572 725
726 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
727
573 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 728 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
574 729
575 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 730 if (IS_IGDNG(dev))
731 return igdng_irq_postinstall(dev);
576 732
577 /* Unmask the interrupts that we always want on. */ 733 /* Unmask the interrupts that we always want on. */
578 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; 734 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
@@ -613,11 +769,24 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
613 (void) I915_READ(IER); 769 (void) I915_READ(IER);
614 770
615 opregion_enable_asle(dev); 771 opregion_enable_asle(dev);
616 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
617 772
618 return 0; 773 return 0;
619} 774}
620 775
776static void igdng_irq_uninstall(struct drm_device *dev)
777{
778 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
779 I915_WRITE(HWSTAM, 0xffffffff);
780
781 I915_WRITE(DEIMR, 0xffffffff);
782 I915_WRITE(DEIER, 0x0);
783 I915_WRITE(DEIIR, I915_READ(DEIIR));
784
785 I915_WRITE(GTIMR, 0xffffffff);
786 I915_WRITE(GTIER, 0x0);
787 I915_WRITE(GTIIR, I915_READ(GTIIR));
788}
789
621void i915_driver_irq_uninstall(struct drm_device * dev) 790void i915_driver_irq_uninstall(struct drm_device * dev)
622{ 791{
623 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 792 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -627,6 +796,11 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
627 796
628 dev_priv->vblank_pipe = 0; 797 dev_priv->vblank_pipe = 0;
629 798
799 if (IS_IGDNG(dev)) {
800 igdng_irq_uninstall(dev);
801 return;
802 }
803
630 if (I915_HAS_HOTPLUG(dev)) { 804 if (I915_HAS_HOTPLUG(dev)) {
631 I915_WRITE(PORT_HOTPLUG_EN, 0); 805 I915_WRITE(PORT_HOTPLUG_EN, 0);
632 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 806 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 375569d01d01..f6237a0b1133 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -450,6 +450,13 @@
450#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 450#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
451#define PLL_REF_INPUT_MASK (3 << 13) 451#define PLL_REF_INPUT_MASK (3 << 13)
452#define PLL_LOAD_PULSE_PHASE_SHIFT 9 452#define PLL_LOAD_PULSE_PHASE_SHIFT 9
453/* IGDNG */
454# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
455# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
456# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
457# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
458# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
459
453/* 460/*
454 * Parallel to Serial Load Pulse phase selection. 461 * Parallel to Serial Load Pulse phase selection.
455 * Selects the phase for the 10X DPLL clock for the PCIe 462 * Selects the phase for the 10X DPLL clock for the PCIe
@@ -631,8 +638,11 @@
631/* Hotplug control (945+ only) */ 638/* Hotplug control (945+ only) */
632#define PORT_HOTPLUG_EN 0x61110 639#define PORT_HOTPLUG_EN 0x61110
633#define HDMIB_HOTPLUG_INT_EN (1 << 29) 640#define HDMIB_HOTPLUG_INT_EN (1 << 29)
641#define DPB_HOTPLUG_INT_EN (1 << 29)
634#define HDMIC_HOTPLUG_INT_EN (1 << 28) 642#define HDMIC_HOTPLUG_INT_EN (1 << 28)
643#define DPC_HOTPLUG_INT_EN (1 << 28)
635#define HDMID_HOTPLUG_INT_EN (1 << 27) 644#define HDMID_HOTPLUG_INT_EN (1 << 27)
645#define DPD_HOTPLUG_INT_EN (1 << 27)
636#define SDVOB_HOTPLUG_INT_EN (1 << 26) 646#define SDVOB_HOTPLUG_INT_EN (1 << 26)
637#define SDVOC_HOTPLUG_INT_EN (1 << 25) 647#define SDVOC_HOTPLUG_INT_EN (1 << 25)
638#define TV_HOTPLUG_INT_EN (1 << 18) 648#define TV_HOTPLUG_INT_EN (1 << 18)
@@ -665,8 +675,11 @@
665 675
666#define PORT_HOTPLUG_STAT 0x61114 676#define PORT_HOTPLUG_STAT 0x61114
667#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) 677#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
678#define DPB_HOTPLUG_INT_STATUS (1 << 29)
668#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) 679#define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
680#define DPC_HOTPLUG_INT_STATUS (1 << 28)
669#define HDMID_HOTPLUG_INT_STATUS (1 << 27) 681#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
682#define DPD_HOTPLUG_INT_STATUS (1 << 27)
670#define CRT_HOTPLUG_INT_STATUS (1 << 11) 683#define CRT_HOTPLUG_INT_STATUS (1 << 11)
671#define TV_HOTPLUG_INT_STATUS (1 << 10) 684#define TV_HOTPLUG_INT_STATUS (1 << 10)
672#define CRT_HOTPLUG_MONITOR_MASK (3 << 8) 685#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
@@ -951,15 +964,15 @@
951# define DAC_A_1_3_V (0 << 4) 964# define DAC_A_1_3_V (0 << 4)
952# define DAC_A_1_1_V (1 << 4) 965# define DAC_A_1_1_V (1 << 4)
953# define DAC_A_0_7_V (2 << 4) 966# define DAC_A_0_7_V (2 << 4)
954# define DAC_A_OFF (3 << 4) 967# define DAC_A_MASK (3 << 4)
955# define DAC_B_1_3_V (0 << 2) 968# define DAC_B_1_3_V (0 << 2)
956# define DAC_B_1_1_V (1 << 2) 969# define DAC_B_1_1_V (1 << 2)
957# define DAC_B_0_7_V (2 << 2) 970# define DAC_B_0_7_V (2 << 2)
958# define DAC_B_OFF (3 << 2) 971# define DAC_B_MASK (3 << 2)
959# define DAC_C_1_3_V (0 << 0) 972# define DAC_C_1_3_V (0 << 0)
960# define DAC_C_1_1_V (1 << 0) 973# define DAC_C_1_1_V (1 << 0)
961# define DAC_C_0_7_V (2 << 0) 974# define DAC_C_0_7_V (2 << 0)
962# define DAC_C_OFF (3 << 0) 975# define DAC_C_MASK (3 << 0)
963 976
964/** 977/**
965 * CSC coefficients are stored in a floating point format with 9 bits of 978 * CSC coefficients are stored in a floating point format with 9 bits of
@@ -1328,6 +1341,163 @@
1328#define TV_V_CHROMA_0 0x68400 1341#define TV_V_CHROMA_0 0x68400
1329#define TV_V_CHROMA_42 0x684a8 1342#define TV_V_CHROMA_42 0x684a8
1330 1343
1344/* Display Port */
1345#define DP_B 0x64100
1346#define DP_C 0x64200
1347#define DP_D 0x64300
1348
1349#define DP_PORT_EN (1 << 31)
1350#define DP_PIPEB_SELECT (1 << 30)
1351
1352/* Link training mode - select a suitable mode for each stage */
1353#define DP_LINK_TRAIN_PAT_1 (0 << 28)
1354#define DP_LINK_TRAIN_PAT_2 (1 << 28)
1355#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
1356#define DP_LINK_TRAIN_OFF (3 << 28)
1357#define DP_LINK_TRAIN_MASK (3 << 28)
1358#define DP_LINK_TRAIN_SHIFT 28
1359
1360/* Signal voltages. These are mostly controlled by the other end */
1361#define DP_VOLTAGE_0_4 (0 << 25)
1362#define DP_VOLTAGE_0_6 (1 << 25)
1363#define DP_VOLTAGE_0_8 (2 << 25)
1364#define DP_VOLTAGE_1_2 (3 << 25)
1365#define DP_VOLTAGE_MASK (7 << 25)
1366#define DP_VOLTAGE_SHIFT 25
1367
1368/* Signal pre-emphasis levels, like voltages, the other end tells us what
1369 * they want
1370 */
1371#define DP_PRE_EMPHASIS_0 (0 << 22)
1372#define DP_PRE_EMPHASIS_3_5 (1 << 22)
1373#define DP_PRE_EMPHASIS_6 (2 << 22)
1374#define DP_PRE_EMPHASIS_9_5 (3 << 22)
1375#define DP_PRE_EMPHASIS_MASK (7 << 22)
1376#define DP_PRE_EMPHASIS_SHIFT 22
1377
1378/* How many wires to use. I guess 3 was too hard */
1379#define DP_PORT_WIDTH_1 (0 << 19)
1380#define DP_PORT_WIDTH_2 (1 << 19)
1381#define DP_PORT_WIDTH_4 (3 << 19)
1382#define DP_PORT_WIDTH_MASK (7 << 19)
1383
1384/* Mystic DPCD version 1.1 special mode */
1385#define DP_ENHANCED_FRAMING (1 << 18)
1386
1387/** locked once port is enabled */
1388#define DP_PORT_REVERSAL (1 << 15)
1389
1390/** sends the clock on lane 15 of the PEG for debug */
1391#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
1392
1393#define DP_SCRAMBLING_DISABLE (1 << 12)
1394
1395/** limit RGB values to avoid confusing TVs */
1396#define DP_COLOR_RANGE_16_235 (1 << 8)
1397
1398/** Turn on the audio link */
1399#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
1400
1401/** vs and hs sync polarity */
1402#define DP_SYNC_VS_HIGH (1 << 4)
1403#define DP_SYNC_HS_HIGH (1 << 3)
1404
1405/** A fantasy */
1406#define DP_DETECTED (1 << 2)
1407
1408/** The aux channel provides a way to talk to the
1409 * signal sink for DDC etc. Max packet size supported
1410 * is 20 bytes in each direction, hence the 5 fixed
1411 * data registers
1412 */
1413#define DPB_AUX_CH_CTL 0x64110
1414#define DPB_AUX_CH_DATA1 0x64114
1415#define DPB_AUX_CH_DATA2 0x64118
1416#define DPB_AUX_CH_DATA3 0x6411c
1417#define DPB_AUX_CH_DATA4 0x64120
1418#define DPB_AUX_CH_DATA5 0x64124
1419
1420#define DPC_AUX_CH_CTL 0x64210
1421#define DPC_AUX_CH_DATA1 0x64214
1422#define DPC_AUX_CH_DATA2 0x64218
1423#define DPC_AUX_CH_DATA3 0x6421c
1424#define DPC_AUX_CH_DATA4 0x64220
1425#define DPC_AUX_CH_DATA5 0x64224
1426
1427#define DPD_AUX_CH_CTL 0x64310
1428#define DPD_AUX_CH_DATA1 0x64314
1429#define DPD_AUX_CH_DATA2 0x64318
1430#define DPD_AUX_CH_DATA3 0x6431c
1431#define DPD_AUX_CH_DATA4 0x64320
1432#define DPD_AUX_CH_DATA5 0x64324
1433
1434#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
1435#define DP_AUX_CH_CTL_DONE (1 << 30)
1436#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
1437#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
1438#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
1439#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
1440#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
1441#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
1442#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
1443#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
1444#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
1445#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
1446#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
1447#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
1448#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
1449#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
1450#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
1451#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
1452#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
1453#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
1454#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
1455
1456/*
1457 * Computing GMCH M and N values for the Display Port link
1458 *
1459 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
1460 *
1461 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1462 *
1463 * The GMCH value is used internally
1464 *
1465 * bytes_per_pixel is the number of bytes coming out of the plane,
1466 * which is after the LUTs, so we want the bytes for our color format.
1467 * For our current usage, this is always 3, one byte for R, G and B.
1468 */
1469#define PIPEA_GMCH_DATA_M 0x70050
1470#define PIPEB_GMCH_DATA_M 0x71050
1471
1472/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1473#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
1474#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
1475
1476#define PIPE_GMCH_DATA_M_MASK (0xffffff)
1477
1478#define PIPEA_GMCH_DATA_N 0x70054
1479#define PIPEB_GMCH_DATA_N 0x71054
1480#define PIPE_GMCH_DATA_N_MASK (0xffffff)
1481
1482/*
1483 * Computing Link M and N values for the Display Port link
1484 *
1485 * Link M / N = pixel_clock / ls_clk
1486 *
1487 * (the DP spec calls pixel_clock the 'strm_clk')
1488 *
1489 * The Link value is transmitted in the Main Stream
1490 * Attributes and VB-ID.
1491 */
1492
1493#define PIPEA_DP_LINK_M 0x70060
1494#define PIPEB_DP_LINK_M 0x71060
1495#define PIPEA_DP_LINK_M_MASK (0xffffff)
1496
1497#define PIPEA_DP_LINK_N 0x70064
1498#define PIPEB_DP_LINK_N 0x71064
1499#define PIPEA_DP_LINK_N_MASK (0xffffff)
1500
1331/* Display & cursor control */ 1501/* Display & cursor control */
1332 1502
1333/* Pipe A */ 1503/* Pipe A */
@@ -1517,4 +1687,444 @@
1517# define VGA_2X_MODE (1 << 30) 1687# define VGA_2X_MODE (1 << 30)
1518# define VGA_PIPE_B_SELECT (1 << 29) 1688# define VGA_PIPE_B_SELECT (1 << 29)
1519 1689
1690/* IGDNG */
1691
1692#define CPU_VGACNTRL 0x41000
1693
1694#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
1695#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
1696#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
1697#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
1698#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
1699#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
1700#define DIGITAL_PORTA_NO_DETECT (0 << 0)
1701#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
1702#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
1703
1704/* refresh rate hardware control */
1705#define RR_HW_CTL 0x45300
1706#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
1707#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
1708
1709#define FDI_PLL_BIOS_0 0x46000
1710#define FDI_PLL_BIOS_1 0x46004
1711#define FDI_PLL_BIOS_2 0x46008
1712#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
1713#define DISPLAY_PORT_PLL_BIOS_1 0x46010
1714#define DISPLAY_PORT_PLL_BIOS_2 0x46014
1715
1716#define FDI_PLL_FREQ_CTL 0x46030
1717#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
1718#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
1719#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
1720
1721
1722#define PIPEA_DATA_M1 0x60030
1723#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
1724#define TU_SIZE_MASK 0x7e000000
1725#define PIPEA_DATA_M1_OFFSET 0
1726#define PIPEA_DATA_N1 0x60034
1727#define PIPEA_DATA_N1_OFFSET 0
1728
1729#define PIPEA_DATA_M2 0x60038
1730#define PIPEA_DATA_M2_OFFSET 0
1731#define PIPEA_DATA_N2 0x6003c
1732#define PIPEA_DATA_N2_OFFSET 0
1733
1734#define PIPEA_LINK_M1 0x60040
1735#define PIPEA_LINK_M1_OFFSET 0
1736#define PIPEA_LINK_N1 0x60044
1737#define PIPEA_LINK_N1_OFFSET 0
1738
1739#define PIPEA_LINK_M2 0x60048
1740#define PIPEA_LINK_M2_OFFSET 0
1741#define PIPEA_LINK_N2 0x6004c
1742#define PIPEA_LINK_N2_OFFSET 0
1743
1744/* PIPEB timing regs are same start from 0x61000 */
1745
1746#define PIPEB_DATA_M1 0x61030
1747#define PIPEB_DATA_M1_OFFSET 0
1748#define PIPEB_DATA_N1 0x61034
1749#define PIPEB_DATA_N1_OFFSET 0
1750
1751#define PIPEB_DATA_M2 0x61038
1752#define PIPEB_DATA_M2_OFFSET 0
1753#define PIPEB_DATA_N2 0x6103c
1754#define PIPEB_DATA_N2_OFFSET 0
1755
1756#define PIPEB_LINK_M1 0x61040
1757#define PIPEB_LINK_M1_OFFSET 0
1758#define PIPEB_LINK_N1 0x61044
1759#define PIPEB_LINK_N1_OFFSET 0
1760
1761#define PIPEB_LINK_M2 0x61048
1762#define PIPEB_LINK_M2_OFFSET 0
1763#define PIPEB_LINK_N2 0x6104c
1764#define PIPEB_LINK_N2_OFFSET 0
1765
1766/* CPU panel fitter */
1767#define PFA_CTL_1 0x68080
1768#define PFB_CTL_1 0x68880
1769#define PF_ENABLE (1<<31)
1770
1771/* legacy palette */
1772#define LGC_PALETTE_A 0x4a000
1773#define LGC_PALETTE_B 0x4a800
1774
1775/* interrupts */
1776#define DE_MASTER_IRQ_CONTROL (1 << 31)
1777#define DE_SPRITEB_FLIP_DONE (1 << 29)
1778#define DE_SPRITEA_FLIP_DONE (1 << 28)
1779#define DE_PLANEB_FLIP_DONE (1 << 27)
1780#define DE_PLANEA_FLIP_DONE (1 << 26)
1781#define DE_PCU_EVENT (1 << 25)
1782#define DE_GTT_FAULT (1 << 24)
1783#define DE_POISON (1 << 23)
1784#define DE_PERFORM_COUNTER (1 << 22)
1785#define DE_PCH_EVENT (1 << 21)
1786#define DE_AUX_CHANNEL_A (1 << 20)
1787#define DE_DP_A_HOTPLUG (1 << 19)
1788#define DE_GSE (1 << 18)
1789#define DE_PIPEB_VBLANK (1 << 15)
1790#define DE_PIPEB_EVEN_FIELD (1 << 14)
1791#define DE_PIPEB_ODD_FIELD (1 << 13)
1792#define DE_PIPEB_LINE_COMPARE (1 << 12)
1793#define DE_PIPEB_VSYNC (1 << 11)
1794#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
1795#define DE_PIPEA_VBLANK (1 << 7)
1796#define DE_PIPEA_EVEN_FIELD (1 << 6)
1797#define DE_PIPEA_ODD_FIELD (1 << 5)
1798#define DE_PIPEA_LINE_COMPARE (1 << 4)
1799#define DE_PIPEA_VSYNC (1 << 3)
1800#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
1801
1802#define DEISR 0x44000
1803#define DEIMR 0x44004
1804#define DEIIR 0x44008
1805#define DEIER 0x4400c
1806
1807/* GT interrupt */
1808#define GT_SYNC_STATUS (1 << 2)
1809#define GT_USER_INTERRUPT (1 << 0)
1810
1811#define GTISR 0x44010
1812#define GTIMR 0x44014
1813#define GTIIR 0x44018
1814#define GTIER 0x4401c
1815
1816/* PCH */
1817
1818/* south display engine interrupt */
1819#define SDE_CRT_HOTPLUG (1 << 11)
1820#define SDE_PORTD_HOTPLUG (1 << 10)
1821#define SDE_PORTC_HOTPLUG (1 << 9)
1822#define SDE_PORTB_HOTPLUG (1 << 8)
1823#define SDE_SDVOB_HOTPLUG (1 << 6)
1824
1825#define SDEISR 0xc4000
1826#define SDEIMR 0xc4004
1827#define SDEIIR 0xc4008
1828#define SDEIER 0xc400c
1829
1830/* digital port hotplug */
1831#define PCH_PORT_HOTPLUG 0xc4030
1832#define PORTD_HOTPLUG_ENABLE (1 << 20)
1833#define PORTD_PULSE_DURATION_2ms (0)
1834#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
1835#define PORTD_PULSE_DURATION_6ms (2 << 18)
1836#define PORTD_PULSE_DURATION_100ms (3 << 18)
1837#define PORTD_HOTPLUG_NO_DETECT (0)
1838#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
1839#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
1840#define PORTC_HOTPLUG_ENABLE (1 << 12)
1841#define PORTC_PULSE_DURATION_2ms (0)
1842#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
1843#define PORTC_PULSE_DURATION_6ms (2 << 10)
1844#define PORTC_PULSE_DURATION_100ms (3 << 10)
1845#define PORTC_HOTPLUG_NO_DETECT (0)
1846#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
1847#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
1848#define PORTB_HOTPLUG_ENABLE (1 << 4)
1849#define PORTB_PULSE_DURATION_2ms (0)
1850#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
1851#define PORTB_PULSE_DURATION_6ms (2 << 2)
1852#define PORTB_PULSE_DURATION_100ms (3 << 2)
1853#define PORTB_HOTPLUG_NO_DETECT (0)
1854#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
1855#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
1856
1857#define PCH_GPIOA 0xc5010
1858#define PCH_GPIOB 0xc5014
1859#define PCH_GPIOC 0xc5018
1860#define PCH_GPIOD 0xc501c
1861#define PCH_GPIOE 0xc5020
1862#define PCH_GPIOF 0xc5024
1863
1864#define PCH_DPLL_A 0xc6014
1865#define PCH_DPLL_B 0xc6018
1866
1867#define PCH_FPA0 0xc6040
1868#define PCH_FPA1 0xc6044
1869#define PCH_FPB0 0xc6048
1870#define PCH_FPB1 0xc604c
1871
1872#define PCH_DPLL_TEST 0xc606c
1873
1874#define PCH_DREF_CONTROL 0xC6200
1875#define DREF_CONTROL_MASK 0x7fc3
1876#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
1877#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
1878#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
1879#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
1880#define DREF_SSC_SOURCE_DISABLE (0<<11)
1881#define DREF_SSC_SOURCE_ENABLE (2<<11)
1882#define DREF_SSC_SOURCE_MASK (2<<11)
1883#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
1884#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
1885#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
1886#define DREF_NONSPREAD_SOURCE_MASK (2<<9)
1887#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
1888#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
1889#define DREF_SSC4_DOWNSPREAD (0<<6)
1890#define DREF_SSC4_CENTERSPREAD (1<<6)
1891#define DREF_SSC1_DISABLE (0<<1)
1892#define DREF_SSC1_ENABLE (1<<1)
1893#define DREF_SSC4_DISABLE (0)
1894#define DREF_SSC4_ENABLE (1)
1895
1896#define PCH_RAWCLK_FREQ 0xc6204
1897#define FDL_TP1_TIMER_SHIFT 12
1898#define FDL_TP1_TIMER_MASK (3<<12)
1899#define FDL_TP2_TIMER_SHIFT 10
1900#define FDL_TP2_TIMER_MASK (3<<10)
1901#define RAWCLK_FREQ_MASK 0x3ff
1902
1903#define PCH_DPLL_TMR_CFG 0xc6208
1904
1905#define PCH_SSC4_PARMS 0xc6210
1906#define PCH_SSC4_AUX_PARMS 0xc6214
1907
1908/* transcoder */
1909
1910#define TRANS_HTOTAL_A 0xe0000
1911#define TRANS_HTOTAL_SHIFT 16
1912#define TRANS_HACTIVE_SHIFT 0
1913#define TRANS_HBLANK_A 0xe0004
1914#define TRANS_HBLANK_END_SHIFT 16
1915#define TRANS_HBLANK_START_SHIFT 0
1916#define TRANS_HSYNC_A 0xe0008
1917#define TRANS_HSYNC_END_SHIFT 16
1918#define TRANS_HSYNC_START_SHIFT 0
1919#define TRANS_VTOTAL_A 0xe000c
1920#define TRANS_VTOTAL_SHIFT 16
1921#define TRANS_VACTIVE_SHIFT 0
1922#define TRANS_VBLANK_A 0xe0010
1923#define TRANS_VBLANK_END_SHIFT 16
1924#define TRANS_VBLANK_START_SHIFT 0
1925#define TRANS_VSYNC_A 0xe0014
1926#define TRANS_VSYNC_END_SHIFT 16
1927#define TRANS_VSYNC_START_SHIFT 0
1928
1929#define TRANSA_DATA_M1 0xe0030
1930#define TRANSA_DATA_N1 0xe0034
1931#define TRANSA_DATA_M2 0xe0038
1932#define TRANSA_DATA_N2 0xe003c
1933#define TRANSA_DP_LINK_M1 0xe0040
1934#define TRANSA_DP_LINK_N1 0xe0044
1935#define TRANSA_DP_LINK_M2 0xe0048
1936#define TRANSA_DP_LINK_N2 0xe004c
1937
1938#define TRANS_HTOTAL_B 0xe1000
1939#define TRANS_HBLANK_B 0xe1004
1940#define TRANS_HSYNC_B 0xe1008
1941#define TRANS_VTOTAL_B 0xe100c
1942#define TRANS_VBLANK_B 0xe1010
1943#define TRANS_VSYNC_B 0xe1014
1944
1945#define TRANSB_DATA_M1 0xe1030
1946#define TRANSB_DATA_N1 0xe1034
1947#define TRANSB_DATA_M2 0xe1038
1948#define TRANSB_DATA_N2 0xe103c
1949#define TRANSB_DP_LINK_M1 0xe1040
1950#define TRANSB_DP_LINK_N1 0xe1044
1951#define TRANSB_DP_LINK_M2 0xe1048
1952#define TRANSB_DP_LINK_N2 0xe104c
1953
1954#define TRANSACONF 0xf0008
1955#define TRANSBCONF 0xf1008
1956#define TRANS_DISABLE (0<<31)
1957#define TRANS_ENABLE (1<<31)
1958#define TRANS_STATE_MASK (1<<30)
1959#define TRANS_STATE_DISABLE (0<<30)
1960#define TRANS_STATE_ENABLE (1<<30)
1961#define TRANS_FSYNC_DELAY_HB1 (0<<27)
1962#define TRANS_FSYNC_DELAY_HB2 (1<<27)
1963#define TRANS_FSYNC_DELAY_HB3 (2<<27)
1964#define TRANS_FSYNC_DELAY_HB4 (3<<27)
1965#define TRANS_DP_AUDIO_ONLY (1<<26)
1966#define TRANS_DP_VIDEO_AUDIO (0<<26)
1967#define TRANS_PROGRESSIVE (0<<21)
1968#define TRANS_8BPC (0<<5)
1969#define TRANS_10BPC (1<<5)
1970#define TRANS_6BPC (2<<5)
1971#define TRANS_12BPC (3<<5)
1972
1973#define FDI_RXA_CHICKEN 0xc200c
1974#define FDI_RXB_CHICKEN 0xc2010
1975#define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
1976
1977/* CPU: FDI_TX */
1978#define FDI_TXA_CTL 0x60100
1979#define FDI_TXB_CTL 0x61100
1980#define FDI_TX_DISABLE (0<<31)
1981#define FDI_TX_ENABLE (1<<31)
1982#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
1983#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
1984#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
1985#define FDI_LINK_TRAIN_NONE (3<<28)
1986#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
1987#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
1988#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
1989#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
1990#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
1991#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
1992#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
1993#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
1994#define FDI_DP_PORT_WIDTH_X1 (0<<19)
1995#define FDI_DP_PORT_WIDTH_X2 (1<<19)
1996#define FDI_DP_PORT_WIDTH_X3 (2<<19)
1997#define FDI_DP_PORT_WIDTH_X4 (3<<19)
1998#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
1999/* IGDNG: hardwired to 1 */
2000#define FDI_TX_PLL_ENABLE (1<<14)
2001/* both Tx and Rx */
2002#define FDI_SCRAMBLING_ENABLE (0<<7)
2003#define FDI_SCRAMBLING_DISABLE (1<<7)
2004
2005/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
2006#define FDI_RXA_CTL 0xf000c
2007#define FDI_RXB_CTL 0xf100c
2008#define FDI_RX_ENABLE (1<<31)
2009#define FDI_RX_DISABLE (0<<31)
2010/* train, dp width same as FDI_TX */
2011#define FDI_DP_PORT_WIDTH_X8 (7<<19)
2012#define FDI_8BPC (0<<16)
2013#define FDI_10BPC (1<<16)
2014#define FDI_6BPC (2<<16)
2015#define FDI_12BPC (3<<16)
2016#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
2017#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
2018#define FDI_RX_PLL_ENABLE (1<<13)
2019#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
2020#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
2021#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
2022#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
2023#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
2024#define FDI_SEL_RAWCLK (0<<4)
2025#define FDI_SEL_PCDCLK (1<<4)
2026
2027#define FDI_RXA_MISC 0xf0010
2028#define FDI_RXB_MISC 0xf1010
2029#define FDI_RXA_TUSIZE1 0xf0030
2030#define FDI_RXA_TUSIZE2 0xf0038
2031#define FDI_RXB_TUSIZE1 0xf1030
2032#define FDI_RXB_TUSIZE2 0xf1038
2033
2034/* FDI_RX interrupt register format */
2035#define FDI_RX_INTER_LANE_ALIGN (1<<10)
2036#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
2037#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
2038#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
2039#define FDI_RX_FS_CODE_ERR (1<<6)
2040#define FDI_RX_FE_CODE_ERR (1<<5)
2041#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
2042#define FDI_RX_HDCP_LINK_FAIL (1<<3)
2043#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
2044#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
2045#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
2046
2047#define FDI_RXA_IIR 0xf0014
2048#define FDI_RXA_IMR 0xf0018
2049#define FDI_RXB_IIR 0xf1014
2050#define FDI_RXB_IMR 0xf1018
2051
2052#define FDI_PLL_CTL_1 0xfe000
2053#define FDI_PLL_CTL_2 0xfe004
2054
2055/* CRT */
2056#define PCH_ADPA 0xe1100
2057#define ADPA_TRANS_SELECT_MASK (1<<30)
2058#define ADPA_TRANS_A_SELECT 0
2059#define ADPA_TRANS_B_SELECT (1<<30)
2060#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2061#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2062#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2063#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2064#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2065#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2066#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2067#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2068#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2069#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2070#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2071#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2072#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2073#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2074#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2075#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2076#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2077#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2078#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2079
2080/* or SDVOB */
2081#define HDMIB 0xe1140
2082#define PORT_ENABLE (1 << 31)
2083#define TRANSCODER_A (0)
2084#define TRANSCODER_B (1 << 30)
2085#define COLOR_FORMAT_8bpc (0)
2086#define COLOR_FORMAT_12bpc (3 << 26)
2087#define SDVOB_HOTPLUG_ENABLE (1 << 23)
2088#define SDVO_ENCODING (0)
2089#define TMDS_ENCODING (2 << 10)
2090#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
2091#define SDVOB_BORDER_ENABLE (1 << 7)
2092#define AUDIO_ENABLE (1 << 6)
2093#define VSYNC_ACTIVE_HIGH (1 << 4)
2094#define HSYNC_ACTIVE_HIGH (1 << 3)
2095#define PORT_DETECTED (1 << 2)
2096
2097#define HDMIC 0xe1150
2098#define HDMID 0xe1160
2099
2100#define PCH_LVDS 0xe1180
2101#define LVDS_DETECTED (1 << 1)
2102
2103#define BLC_PWM_CPU_CTL2 0x48250
2104#define PWM_ENABLE (1 << 31)
2105#define PWM_PIPE_A (0 << 29)
2106#define PWM_PIPE_B (1 << 29)
2107#define BLC_PWM_CPU_CTL 0x48254
2108
2109#define BLC_PWM_PCH_CTL1 0xc8250
2110#define PWM_PCH_ENABLE (1 << 31)
2111#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
2112#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
2113#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
2114#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
2115
2116#define BLC_PWM_PCH_CTL2 0xc8254
2117
2118#define PCH_PP_STATUS 0xc7200
2119#define PCH_PP_CONTROL 0xc7204
2120#define EDP_FORCE_VDD (1 << 3)
2121#define EDP_BLC_ENABLE (1 << 2)
2122#define PANEL_POWER_RESET (1 << 1)
2123#define PANEL_POWER_OFF (0 << 0)
2124#define PANEL_POWER_ON (1 << 0)
2125#define PCH_PP_ON_DELAYS 0xc7208
2126#define EDP_PANEL (1 << 30)
2127#define PCH_PP_OFF_DELAYS 0xc720c
2128#define PCH_PP_DIVISOR 0xc7210
2129
1520#endif /* _I915_REG_H_ */ 2130#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index ce8a21344a71..a98e2831ed31 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -295,6 +295,16 @@ int i915_save_state(struct drm_device *dev)
295 i915_save_palette(dev, PIPE_B); 295 i915_save_palette(dev, PIPE_B);
296 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT); 296 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
297 297
298 /* Cursor state */
299 dev_priv->saveCURACNTR = I915_READ(CURACNTR);
300 dev_priv->saveCURAPOS = I915_READ(CURAPOS);
301 dev_priv->saveCURABASE = I915_READ(CURABASE);
302 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
303 dev_priv->saveCURBPOS = I915_READ(CURBPOS);
304 dev_priv->saveCURBBASE = I915_READ(CURBBASE);
305 if (!IS_I9XX(dev))
306 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
307
298 /* CRT state */ 308 /* CRT state */
299 dev_priv->saveADPA = I915_READ(ADPA); 309 dev_priv->saveADPA = I915_READ(ADPA);
300 310
@@ -480,6 +490,16 @@ int i915_restore_state(struct drm_device *dev)
480 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); 490 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
481 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR)); 491 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
482 492
493 /* Cursor state */
494 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
495 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
496 I915_WRITE(CURABASE, dev_priv->saveCURABASE);
497 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
498 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
499 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
500 if (!IS_I9XX(dev))
501 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
502
483 /* CRT state */ 503 /* CRT state */
484 I915_WRITE(ADPA, dev_priv->saveADPA); 504 I915_WRITE(ADPA, dev_priv->saveADPA);
485 505
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 9d78cff33b24..754dd22fdd77 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -30,6 +30,8 @@
30#include "i915_drv.h" 30#include "i915_drv.h"
31#include "intel_bios.h" 31#include "intel_bios.h"
32 32
33#define SLAVE_ADDR1 0x70
34#define SLAVE_ADDR2 0x72
33 35
34static void * 36static void *
35find_section(struct bdb_header *bdb, int section_id) 37find_section(struct bdb_header *bdb, int section_id)
@@ -193,6 +195,88 @@ parse_general_features(struct drm_i915_private *dev_priv,
193 } 195 }
194} 196}
195 197
198static void
199parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
200 struct bdb_header *bdb)
201{
202 struct sdvo_device_mapping *p_mapping;
203 struct bdb_general_definitions *p_defs;
204 struct child_device_config *p_child;
205 int i, child_device_num, count;
206 u16 block_size, *block_ptr;
207
208 p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
209 if (!p_defs) {
210 DRM_DEBUG("No general definition block is found\n");
211 return;
212 }
213 /* judge whether the size of child device meets the requirements.
214 * If the child device size obtained from general definition block
215 * is different with sizeof(struct child_device_config), skip the
216 * parsing of sdvo device info
217 */
218 if (p_defs->child_dev_size != sizeof(*p_child)) {
219 /* different child dev size . Ignore it */
220 DRM_DEBUG("different child size is found. Invalid.\n");
221 return;
222 }
223 /* get the block size of general definitions */
224 block_ptr = (u16 *)((char *)p_defs - 2);
225 block_size = *block_ptr;
226 /* get the number of child device */
227 child_device_num = (block_size - sizeof(*p_defs)) /
228 sizeof(*p_child);
229 count = 0;
230 for (i = 0; i < child_device_num; i++) {
231 p_child = &(p_defs->devices[i]);
232 if (!p_child->device_type) {
233 /* skip the device block if device type is invalid */
234 continue;
235 }
236 if (p_child->slave_addr != SLAVE_ADDR1 &&
237 p_child->slave_addr != SLAVE_ADDR2) {
238 /*
239 * If the slave address is neither 0x70 nor 0x72,
240 * it is not a SDVO device. Skip it.
241 */
242 continue;
243 }
244 if (p_child->dvo_port != DEVICE_PORT_DVOB &&
245 p_child->dvo_port != DEVICE_PORT_DVOC) {
246 /* skip the incorrect SDVO port */
247 DRM_DEBUG("Incorrect SDVO port. Skip it \n");
248 continue;
249 }
250 DRM_DEBUG("the SDVO device with slave addr %2x is found on "
251 "%s port\n",
252 p_child->slave_addr,
253 (p_child->dvo_port == DEVICE_PORT_DVOB) ?
254 "SDVOB" : "SDVOC");
255 p_mapping = &(dev_priv->sdvo_mappings[p_child->dvo_port - 1]);
256 if (!p_mapping->initialized) {
257 p_mapping->dvo_port = p_child->dvo_port;
258 p_mapping->slave_addr = p_child->slave_addr;
259 p_mapping->dvo_wiring = p_child->dvo_wiring;
260 p_mapping->initialized = 1;
261 } else {
262 DRM_DEBUG("Maybe one SDVO port is shared by "
263 "two SDVO device.\n");
264 }
265 if (p_child->slave2_addr) {
266 /* Maybe this is a SDVO device with multiple inputs */
267 /* And the mapping info is not added */
268 DRM_DEBUG("there exists the slave2_addr. Maybe this "
269 "is a SDVO device with multiple inputs.\n");
270 }
271 count++;
272 }
273
274 if (!count) {
275 /* No SDVO device info is found */
276 DRM_DEBUG("No SDVO device info is found in VBT\n");
277 }
278 return;
279}
196/** 280/**
197 * intel_init_bios - initialize VBIOS settings & find VBT 281 * intel_init_bios - initialize VBIOS settings & find VBT
198 * @dev: DRM device 282 * @dev: DRM device
@@ -242,7 +326,7 @@ intel_init_bios(struct drm_device *dev)
242 parse_general_features(dev_priv, bdb); 326 parse_general_features(dev_priv, bdb);
243 parse_lfp_panel_data(dev_priv, bdb); 327 parse_lfp_panel_data(dev_priv, bdb);
244 parse_sdvo_panel_data(dev_priv, bdb); 328 parse_sdvo_panel_data(dev_priv, bdb);
245 329 parse_sdvo_device_mapping(dev_priv, bdb);
246 pci_unmap_rom(pdev, bios); 330 pci_unmap_rom(pdev, bios);
247 331
248 return 0; 332 return 0;
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index 8ca2cde15804..fe72e1c225d8 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -135,6 +135,86 @@ struct bdb_general_features {
135 u8 rsvd11:6; /* finish byte */ 135 u8 rsvd11:6; /* finish byte */
136} __attribute__((packed)); 136} __attribute__((packed));
137 137
138/* pre-915 */
139#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
140#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
141#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
142#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
143
144/* Pre 915 */
145#define DEVICE_TYPE_NONE 0x00
146#define DEVICE_TYPE_CRT 0x01
147#define DEVICE_TYPE_TV 0x09
148#define DEVICE_TYPE_EFP 0x12
149#define DEVICE_TYPE_LFP 0x22
150/* On 915+ */
151#define DEVICE_TYPE_CRT_DPMS 0x6001
152#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
153#define DEVICE_TYPE_TV_COMPOSITE 0x0209
154#define DEVICE_TYPE_TV_MACROVISION 0x0289
155#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
156#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
157#define DEVICE_TYPE_TV_SCART 0x0209
158#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
159#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
160#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
161#define DEVICE_TYPE_EFP_DVI_I 0x6053
162#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
163#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
164#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
165#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
166#define DEVICE_TYPE_LFP_PANELLINK 0x5012
167#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
168#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
169#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
170#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
171
172#define DEVICE_CFG_NONE 0x00
173#define DEVICE_CFG_12BIT_DVOB 0x01
174#define DEVICE_CFG_12BIT_DVOC 0x02
175#define DEVICE_CFG_24BIT_DVOBC 0x09
176#define DEVICE_CFG_24BIT_DVOCB 0x0a
177#define DEVICE_CFG_DUAL_DVOB 0x11
178#define DEVICE_CFG_DUAL_DVOC 0x12
179#define DEVICE_CFG_DUAL_DVOBC 0x13
180#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
181#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
182
183#define DEVICE_WIRE_NONE 0x00
184#define DEVICE_WIRE_DVOB 0x01
185#define DEVICE_WIRE_DVOC 0x02
186#define DEVICE_WIRE_DVOBC 0x03
187#define DEVICE_WIRE_DVOBB 0x05
188#define DEVICE_WIRE_DVOCC 0x06
189#define DEVICE_WIRE_DVOB_MASTER 0x0d
190#define DEVICE_WIRE_DVOC_MASTER 0x0e
191
192#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
193#define DEVICE_PORT_DVOB 0x01
194#define DEVICE_PORT_DVOC 0x02
195
196struct child_device_config {
197 u16 handle;
198 u16 device_type;
199 u8 device_id[10]; /* See DEVICE_TYPE_* above */
200 u16 addin_offset;
201 u8 dvo_port; /* See Device_PORT_* above */
202 u8 i2c_pin;
203 u8 slave_addr;
204 u8 ddc_pin;
205 u16 edid_ptr;
206 u8 dvo_cfg; /* See DEVICE_CFG_* above */
207 u8 dvo2_port;
208 u8 i2c2_pin;
209 u8 slave2_addr;
210 u8 ddc2_pin;
211 u8 capabilities;
212 u8 dvo_wiring;/* See DEVICE_WIRE_* above */
213 u8 dvo2_wiring;
214 u16 extended_type;
215 u8 dvo_function;
216} __attribute__((packed));
217
138struct bdb_general_definitions { 218struct bdb_general_definitions {
139 /* DDC GPIO */ 219 /* DDC GPIO */
140 u8 crt_ddc_gmbus_pin; 220 u8 crt_ddc_gmbus_pin;
@@ -149,14 +229,19 @@ struct bdb_general_definitions {
149 u8 boot_display[2]; 229 u8 boot_display[2];
150 u8 child_dev_size; 230 u8 child_dev_size;
151 231
152 /* device info */ 232 /*
153 u8 tv_or_lvds_info[33]; 233 * Device info:
154 u8 dev1[33]; 234 * If TV is present, it'll be at devices[0].
155 u8 dev2[33]; 235 * LVDS will be next, either devices[0] or [1], if present.
156 u8 dev3[33]; 236 * On some platforms the number of device is 6. But could be as few as
157 u8 dev4[33]; 237 * 4 if both TV and LVDS are missing.
158 /* may be another device block here on some platforms */ 238 * And the device num is related with the size of general definition
159}; 239 * block. It is obtained by using the following formula:
240 * number = (block_size - sizeof(bdb_general_definitions))/
241 * sizeof(child_device_config);
242 */
243 struct child_device_config devices[0];
244} __attribute__((packed));
160 245
161struct bdb_lvds_options { 246struct bdb_lvds_options {
162 u8 panel_type; 247 u8 panel_type;
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 79acc4f4c1f8..6de97fc66029 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -37,9 +37,14 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
37{ 37{
38 struct drm_device *dev = encoder->dev; 38 struct drm_device *dev = encoder->dev;
39 struct drm_i915_private *dev_priv = dev->dev_private; 39 struct drm_i915_private *dev_priv = dev->dev_private;
40 u32 temp; 40 u32 temp, reg;
41 41
42 temp = I915_READ(ADPA); 42 if (IS_IGDNG(dev))
43 reg = PCH_ADPA;
44 else
45 reg = ADPA;
46
47 temp = I915_READ(reg);
43 temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 48 temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
44 temp |= ADPA_DAC_ENABLE; 49 temp |= ADPA_DAC_ENABLE;
45 50
@@ -58,7 +63,7 @@ static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
58 break; 63 break;
59 } 64 }
60 65
61 I915_WRITE(ADPA, temp); 66 I915_WRITE(reg, temp);
62} 67}
63 68
64static int intel_crt_mode_valid(struct drm_connector *connector, 69static int intel_crt_mode_valid(struct drm_connector *connector,
@@ -101,17 +106,23 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
101 struct drm_i915_private *dev_priv = dev->dev_private; 106 struct drm_i915_private *dev_priv = dev->dev_private;
102 int dpll_md_reg; 107 int dpll_md_reg;
103 u32 adpa, dpll_md; 108 u32 adpa, dpll_md;
109 u32 adpa_reg;
104 110
105 if (intel_crtc->pipe == 0) 111 if (intel_crtc->pipe == 0)
106 dpll_md_reg = DPLL_A_MD; 112 dpll_md_reg = DPLL_A_MD;
107 else 113 else
108 dpll_md_reg = DPLL_B_MD; 114 dpll_md_reg = DPLL_B_MD;
109 115
116 if (IS_IGDNG(dev))
117 adpa_reg = PCH_ADPA;
118 else
119 adpa_reg = ADPA;
120
110 /* 121 /*
111 * Disable separate mode multiplier used when cloning SDVO to CRT 122 * Disable separate mode multiplier used when cloning SDVO to CRT
112 * XXX this needs to be adjusted when we really are cloning 123 * XXX this needs to be adjusted when we really are cloning
113 */ 124 */
114 if (IS_I965G(dev)) { 125 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
115 dpll_md = I915_READ(dpll_md_reg); 126 dpll_md = I915_READ(dpll_md_reg);
116 I915_WRITE(dpll_md_reg, 127 I915_WRITE(dpll_md_reg,
117 dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK); 128 dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
@@ -125,13 +136,53 @@ static void intel_crt_mode_set(struct drm_encoder *encoder,
125 136
126 if (intel_crtc->pipe == 0) { 137 if (intel_crtc->pipe == 0) {
127 adpa |= ADPA_PIPE_A_SELECT; 138 adpa |= ADPA_PIPE_A_SELECT;
128 I915_WRITE(BCLRPAT_A, 0); 139 if (!IS_IGDNG(dev))
140 I915_WRITE(BCLRPAT_A, 0);
129 } else { 141 } else {
130 adpa |= ADPA_PIPE_B_SELECT; 142 adpa |= ADPA_PIPE_B_SELECT;
131 I915_WRITE(BCLRPAT_B, 0); 143 if (!IS_IGDNG(dev))
144 I915_WRITE(BCLRPAT_B, 0);
132 } 145 }
133 146
134 I915_WRITE(ADPA, adpa); 147 I915_WRITE(adpa_reg, adpa);
148}
149
150static bool intel_igdng_crt_detect_hotplug(struct drm_connector *connector)
151{
152 struct drm_device *dev = connector->dev;
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 u32 adpa, temp;
155 bool ret;
156
157 temp = adpa = I915_READ(PCH_ADPA);
158
159 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
160
161 adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
162 ADPA_CRT_HOTPLUG_WARMUP_10MS |
163 ADPA_CRT_HOTPLUG_SAMPLE_4S |
164 ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */
165 ADPA_CRT_HOTPLUG_VOLREF_325MV |
166 ADPA_CRT_HOTPLUG_ENABLE |
167 ADPA_CRT_HOTPLUG_FORCE_TRIGGER);
168
169 DRM_DEBUG("pch crt adpa 0x%x", adpa);
170 I915_WRITE(PCH_ADPA, adpa);
171
172 /* This might not be needed as not specified in spec...*/
173 udelay(1000);
174
175 /* Check the status to see if both blue and green are on now */
176 adpa = I915_READ(PCH_ADPA);
177 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) ==
178 ADPA_CRT_HOTPLUG_MONITOR_COLOR)
179 ret = true;
180 else
181 ret = false;
182
183 /* restore origin register */
184 I915_WRITE(PCH_ADPA, temp);
185 return ret;
135} 186}
136 187
137/** 188/**
@@ -148,6 +199,10 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
148 struct drm_i915_private *dev_priv = dev->dev_private; 199 struct drm_i915_private *dev_priv = dev->dev_private;
149 u32 hotplug_en; 200 u32 hotplug_en;
150 int i, tries = 0; 201 int i, tries = 0;
202
203 if (IS_IGDNG(dev))
204 return intel_igdng_crt_detect_hotplug(connector);
205
151 /* 206 /*
152 * On 4 series desktop, CRT detect sequence need to be done twice 207 * On 4 series desktop, CRT detect sequence need to be done twice
153 * to get a reliable result. 208 * to get a reliable result.
@@ -423,6 +478,7 @@ void intel_crt_init(struct drm_device *dev)
423{ 478{
424 struct drm_connector *connector; 479 struct drm_connector *connector;
425 struct intel_output *intel_output; 480 struct intel_output *intel_output;
481 u32 i2c_reg;
426 482
427 intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); 483 intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL);
428 if (!intel_output) 484 if (!intel_output)
@@ -439,7 +495,11 @@ void intel_crt_init(struct drm_device *dev)
439 &intel_output->enc); 495 &intel_output->enc);
440 496
441 /* Set up the DDC bus. */ 497 /* Set up the DDC bus. */
442 intel_output->ddc_bus = intel_i2c_create(dev, GPIOA, "CRTDDC_A"); 498 if (IS_IGDNG(dev))
499 i2c_reg = PCH_GPIOA;
500 else
501 i2c_reg = GPIOA;
502 intel_output->ddc_bus = intel_i2c_create(dev, i2c_reg, "CRTDDC_A");
443 if (!intel_output->ddc_bus) { 503 if (!intel_output->ddc_bus) {
444 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " 504 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
445 "failed.\n"); 505 "failed.\n");
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c9d6f10ba92e..028f5b66e3d8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -137,6 +137,8 @@ struct intel_limit {
137#define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS 7 137#define INTEL_LIMIT_G4X_DUAL_CHANNEL_LVDS 7
138#define INTEL_LIMIT_IGD_SDVO_DAC 8 138#define INTEL_LIMIT_IGD_SDVO_DAC 8
139#define INTEL_LIMIT_IGD_LVDS 9 139#define INTEL_LIMIT_IGD_LVDS 9
140#define INTEL_LIMIT_IGDNG_SDVO_DAC 10
141#define INTEL_LIMIT_IGDNG_LVDS 11
140 142
141/*The parameter is for SDVO on G4x platform*/ 143/*The parameter is for SDVO on G4x platform*/
142#define G4X_DOT_SDVO_MIN 25000 144#define G4X_DOT_SDVO_MIN 25000
@@ -216,12 +218,43 @@ struct intel_limit {
216#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7 218#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
217#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0 219#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
218 220
221/* IGDNG */
222/* as we calculate clock using (register_value + 2) for
223 N/M1/M2, so here the range value for them is (actual_value-2).
224 */
225#define IGDNG_DOT_MIN 25000
226#define IGDNG_DOT_MAX 350000
227#define IGDNG_VCO_MIN 1760000
228#define IGDNG_VCO_MAX 3510000
229#define IGDNG_N_MIN 1
230#define IGDNG_N_MAX 5
231#define IGDNG_M_MIN 79
232#define IGDNG_M_MAX 118
233#define IGDNG_M1_MIN 12
234#define IGDNG_M1_MAX 23
235#define IGDNG_M2_MIN 5
236#define IGDNG_M2_MAX 9
237#define IGDNG_P_SDVO_DAC_MIN 5
238#define IGDNG_P_SDVO_DAC_MAX 80
239#define IGDNG_P_LVDS_MIN 28
240#define IGDNG_P_LVDS_MAX 112
241#define IGDNG_P1_MIN 1
242#define IGDNG_P1_MAX 8
243#define IGDNG_P2_SDVO_DAC_SLOW 10
244#define IGDNG_P2_SDVO_DAC_FAST 5
245#define IGDNG_P2_LVDS_SLOW 14 /* single channel */
246#define IGDNG_P2_LVDS_FAST 7 /* double channel */
247#define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
248
219static bool 249static bool
220intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 250intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
221 int target, int refclk, intel_clock_t *best_clock); 251 int target, int refclk, intel_clock_t *best_clock);
222static bool 252static bool
223intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 253intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
224 int target, int refclk, intel_clock_t *best_clock); 254 int target, int refclk, intel_clock_t *best_clock);
255static bool
256intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
257 int target, int refclk, intel_clock_t *best_clock);
225 258
226static const intel_limit_t intel_limits[] = { 259static const intel_limit_t intel_limits[] = {
227 { /* INTEL_LIMIT_I8XX_DVO_DAC */ 260 { /* INTEL_LIMIT_I8XX_DVO_DAC */
@@ -383,9 +416,47 @@ static const intel_limit_t intel_limits[] = {
383 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW }, 416 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
384 .find_pll = intel_find_best_PLL, 417 .find_pll = intel_find_best_PLL,
385 }, 418 },
386 419 { /* INTEL_LIMIT_IGDNG_SDVO_DAC */
420 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
421 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
422 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
423 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
424 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
425 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
426 .p = { .min = IGDNG_P_SDVO_DAC_MIN, .max = IGDNG_P_SDVO_DAC_MAX },
427 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
428 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
429 .p2_slow = IGDNG_P2_SDVO_DAC_SLOW,
430 .p2_fast = IGDNG_P2_SDVO_DAC_FAST },
431 .find_pll = intel_igdng_find_best_PLL,
432 },
433 { /* INTEL_LIMIT_IGDNG_LVDS */
434 .dot = { .min = IGDNG_DOT_MIN, .max = IGDNG_DOT_MAX },
435 .vco = { .min = IGDNG_VCO_MIN, .max = IGDNG_VCO_MAX },
436 .n = { .min = IGDNG_N_MIN, .max = IGDNG_N_MAX },
437 .m = { .min = IGDNG_M_MIN, .max = IGDNG_M_MAX },
438 .m1 = { .min = IGDNG_M1_MIN, .max = IGDNG_M1_MAX },
439 .m2 = { .min = IGDNG_M2_MIN, .max = IGDNG_M2_MAX },
440 .p = { .min = IGDNG_P_LVDS_MIN, .max = IGDNG_P_LVDS_MAX },
441 .p1 = { .min = IGDNG_P1_MIN, .max = IGDNG_P1_MAX },
442 .p2 = { .dot_limit = IGDNG_P2_DOT_LIMIT,
443 .p2_slow = IGDNG_P2_LVDS_SLOW,
444 .p2_fast = IGDNG_P2_LVDS_FAST },
445 .find_pll = intel_igdng_find_best_PLL,
446 },
387}; 447};
388 448
449static const intel_limit_t *intel_igdng_limit(struct drm_crtc *crtc)
450{
451 const intel_limit_t *limit;
452 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
453 limit = &intel_limits[INTEL_LIMIT_IGDNG_LVDS];
454 else
455 limit = &intel_limits[INTEL_LIMIT_IGDNG_SDVO_DAC];
456
457 return limit;
458}
459
389static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) 460static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390{ 461{
391 struct drm_device *dev = crtc->dev; 462 struct drm_device *dev = crtc->dev;
@@ -418,7 +489,9 @@ static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
418 struct drm_device *dev = crtc->dev; 489 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit; 490 const intel_limit_t *limit;
420 491
421 if (IS_G4X(dev)) { 492 if (IS_IGDNG(dev))
493 limit = intel_igdng_limit(crtc);
494 else if (IS_G4X(dev)) {
422 limit = intel_g4x_limit(crtc); 495 limit = intel_g4x_limit(crtc);
423 } else if (IS_I9XX(dev) && !IS_IGD(dev)) { 496 } else if (IS_I9XX(dev) && !IS_IGD(dev)) {
424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 497 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
@@ -630,7 +703,64 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
630 } 703 }
631 } 704 }
632 } 705 }
706 return found;
707}
633 708
709static bool
710intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
711 int target, int refclk, intel_clock_t *best_clock)
712{
713 struct drm_device *dev = crtc->dev;
714 struct drm_i915_private *dev_priv = dev->dev_private;
715 intel_clock_t clock;
716 int max_n;
717 bool found;
718 int err_most = 47;
719 found = false;
720
721 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
722 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
723 LVDS_CLKB_POWER_UP)
724 clock.p2 = limit->p2.p2_fast;
725 else
726 clock.p2 = limit->p2.p2_slow;
727 } else {
728 if (target < limit->p2.dot_limit)
729 clock.p2 = limit->p2.p2_slow;
730 else
731 clock.p2 = limit->p2.p2_fast;
732 }
733
734 memset(best_clock, 0, sizeof(*best_clock));
735 max_n = limit->n.max;
736 /* based on hardware requriment prefer smaller n to precision */
737 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
738 /* based on hardware requirment prefere larger m1,m2, p1 */
739 for (clock.m1 = limit->m1.max;
740 clock.m1 >= limit->m1.min; clock.m1--) {
741 for (clock.m2 = limit->m2.max;
742 clock.m2 >= limit->m2.min; clock.m2--) {
743 for (clock.p1 = limit->p1.max;
744 clock.p1 >= limit->p1.min; clock.p1--) {
745 int this_err;
746
747 intel_clock(dev, refclk, &clock);
748 if (!intel_PLL_is_valid(crtc, &clock))
749 continue;
750 this_err = abs((10000 - (target*10000/clock.dot)));
751 if (this_err < err_most) {
752 *best_clock = clock;
753 err_most = this_err;
754 max_n = clock.n;
755 found = true;
756 /* found on first matching */
757 goto out;
758 }
759 }
760 }
761 }
762 }
763out:
634 return found; 764 return found;
635} 765}
636 766
@@ -785,18 +915,292 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
785 return 0; 915 return 0;
786} 916}
787 917
918static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
919{
920 struct drm_device *dev = crtc->dev;
921 struct drm_i915_private *dev_priv = dev->dev_private;
922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
923 int pipe = intel_crtc->pipe;
924 int plane = intel_crtc->pipe;
925 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
926 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
927 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
928 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
929 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
930 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
931 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
932 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
933 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
934 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
935 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
936 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
937 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
938 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
939 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
940 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
941 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
942 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
943 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
944 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
945 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
946 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
947 u32 temp;
948 int tries = 5, j;
788 949
950 /* XXX: When our outputs are all unaware of DPMS modes other than off
951 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
952 */
953 switch (mode) {
954 case DRM_MODE_DPMS_ON:
955 case DRM_MODE_DPMS_STANDBY:
956 case DRM_MODE_DPMS_SUSPEND:
957 DRM_DEBUG("crtc %d dpms on\n", pipe);
958 /* enable PCH DPLL */
959 temp = I915_READ(pch_dpll_reg);
960 if ((temp & DPLL_VCO_ENABLE) == 0) {
961 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
962 I915_READ(pch_dpll_reg);
963 }
789 964
790/** 965 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
791 * Sets the power management mode of the pipe and plane. 966 temp = I915_READ(fdi_rx_reg);
792 * 967 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
793 * This code should probably grow support for turning the cursor off and back 968 FDI_SEL_PCDCLK |
794 * on appropriately at the same time as we're turning the pipe off/on. 969 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
795 */ 970 I915_READ(fdi_rx_reg);
796static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) 971 udelay(200);
972
973 /* Enable CPU FDI TX PLL, always on for IGDNG */
974 temp = I915_READ(fdi_tx_reg);
975 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
976 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
977 I915_READ(fdi_tx_reg);
978 udelay(100);
979 }
980
981 /* Enable CPU pipe */
982 temp = I915_READ(pipeconf_reg);
983 if ((temp & PIPEACONF_ENABLE) == 0) {
984 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
985 I915_READ(pipeconf_reg);
986 udelay(100);
987 }
988
989 /* configure and enable CPU plane */
990 temp = I915_READ(dspcntr_reg);
991 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
992 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
993 /* Flush the plane changes */
994 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
995 }
996
997 /* enable CPU FDI TX and PCH FDI RX */
998 temp = I915_READ(fdi_tx_reg);
999 temp |= FDI_TX_ENABLE;
1000 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1001 temp &= ~FDI_LINK_TRAIN_NONE;
1002 temp |= FDI_LINK_TRAIN_PATTERN_1;
1003 I915_WRITE(fdi_tx_reg, temp);
1004 I915_READ(fdi_tx_reg);
1005
1006 temp = I915_READ(fdi_rx_reg);
1007 temp &= ~FDI_LINK_TRAIN_NONE;
1008 temp |= FDI_LINK_TRAIN_PATTERN_1;
1009 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1010 I915_READ(fdi_rx_reg);
1011
1012 udelay(150);
1013
1014 /* Train FDI. */
1015 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1016 for train result */
1017 temp = I915_READ(fdi_rx_imr_reg);
1018 temp &= ~FDI_RX_SYMBOL_LOCK;
1019 temp &= ~FDI_RX_BIT_LOCK;
1020 I915_WRITE(fdi_rx_imr_reg, temp);
1021 I915_READ(fdi_rx_imr_reg);
1022 udelay(150);
1023
1024 temp = I915_READ(fdi_rx_iir_reg);
1025 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1026
1027 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1028 for (j = 0; j < tries; j++) {
1029 temp = I915_READ(fdi_rx_iir_reg);
1030 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1031 if (temp & FDI_RX_BIT_LOCK)
1032 break;
1033 udelay(200);
1034 }
1035 if (j != tries)
1036 I915_WRITE(fdi_rx_iir_reg,
1037 temp | FDI_RX_BIT_LOCK);
1038 else
1039 DRM_DEBUG("train 1 fail\n");
1040 } else {
1041 I915_WRITE(fdi_rx_iir_reg,
1042 temp | FDI_RX_BIT_LOCK);
1043 DRM_DEBUG("train 1 ok 2!\n");
1044 }
1045 temp = I915_READ(fdi_tx_reg);
1046 temp &= ~FDI_LINK_TRAIN_NONE;
1047 temp |= FDI_LINK_TRAIN_PATTERN_2;
1048 I915_WRITE(fdi_tx_reg, temp);
1049
1050 temp = I915_READ(fdi_rx_reg);
1051 temp &= ~FDI_LINK_TRAIN_NONE;
1052 temp |= FDI_LINK_TRAIN_PATTERN_2;
1053 I915_WRITE(fdi_rx_reg, temp);
1054
1055 udelay(150);
1056
1057 temp = I915_READ(fdi_rx_iir_reg);
1058 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1059
1060 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1061 for (j = 0; j < tries; j++) {
1062 temp = I915_READ(fdi_rx_iir_reg);
1063 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp);
1064 if (temp & FDI_RX_SYMBOL_LOCK)
1065 break;
1066 udelay(200);
1067 }
1068 if (j != tries) {
1069 I915_WRITE(fdi_rx_iir_reg,
1070 temp | FDI_RX_SYMBOL_LOCK);
1071 DRM_DEBUG("train 2 ok 1!\n");
1072 } else
1073 DRM_DEBUG("train 2 fail\n");
1074 } else {
1075 I915_WRITE(fdi_rx_iir_reg, temp | FDI_RX_SYMBOL_LOCK);
1076 DRM_DEBUG("train 2 ok 2!\n");
1077 }
1078 DRM_DEBUG("train done\n");
1079
1080 /* set transcoder timing */
1081 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1082 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1083 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1084
1085 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1086 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1087 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1088
1089 /* enable PCH transcoder */
1090 temp = I915_READ(transconf_reg);
1091 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1092 I915_READ(transconf_reg);
1093
1094 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1095 ;
1096
1097 /* enable normal */
1098
1099 temp = I915_READ(fdi_tx_reg);
1100 temp &= ~FDI_LINK_TRAIN_NONE;
1101 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1102 FDI_TX_ENHANCE_FRAME_ENABLE);
1103 I915_READ(fdi_tx_reg);
1104
1105 temp = I915_READ(fdi_rx_reg);
1106 temp &= ~FDI_LINK_TRAIN_NONE;
1107 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1108 FDI_RX_ENHANCE_FRAME_ENABLE);
1109 I915_READ(fdi_rx_reg);
1110
1111 /* wait one idle pattern time */
1112 udelay(100);
1113
1114 intel_crtc_load_lut(crtc);
1115
1116 break;
1117 case DRM_MODE_DPMS_OFF:
1118 DRM_DEBUG("crtc %d dpms off\n", pipe);
1119
1120 /* Disable the VGA plane that we never use */
1121 I915_WRITE(CPU_VGACNTRL, VGA_DISP_DISABLE);
1122
1123 /* Disable display plane */
1124 temp = I915_READ(dspcntr_reg);
1125 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1126 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1127 /* Flush the plane changes */
1128 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1129 I915_READ(dspbase_reg);
1130 }
1131
1132 /* disable cpu pipe, disable after all planes disabled */
1133 temp = I915_READ(pipeconf_reg);
1134 if ((temp & PIPEACONF_ENABLE) != 0) {
1135 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1136 I915_READ(pipeconf_reg);
1137 /* wait for cpu pipe off, pipe state */
1138 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0)
1139 ;
1140 } else
1141 DRM_DEBUG("crtc %d is disabled\n", pipe);
1142
1143 /* IGDNG-A : disable cpu panel fitter ? */
1144 temp = I915_READ(pf_ctl_reg);
1145 if ((temp & PF_ENABLE) != 0) {
1146 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1147 I915_READ(pf_ctl_reg);
1148 }
1149
1150 /* disable CPU FDI tx and PCH FDI rx */
1151 temp = I915_READ(fdi_tx_reg);
1152 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1153 I915_READ(fdi_tx_reg);
1154
1155 temp = I915_READ(fdi_rx_reg);
1156 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1157 I915_READ(fdi_rx_reg);
1158
1159 /* still set train pattern 1 */
1160 temp = I915_READ(fdi_tx_reg);
1161 temp &= ~FDI_LINK_TRAIN_NONE;
1162 temp |= FDI_LINK_TRAIN_PATTERN_1;
1163 I915_WRITE(fdi_tx_reg, temp);
1164
1165 temp = I915_READ(fdi_rx_reg);
1166 temp &= ~FDI_LINK_TRAIN_NONE;
1167 temp |= FDI_LINK_TRAIN_PATTERN_1;
1168 I915_WRITE(fdi_rx_reg, temp);
1169
1170 /* disable PCH transcoder */
1171 temp = I915_READ(transconf_reg);
1172 if ((temp & TRANS_ENABLE) != 0) {
1173 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1174 I915_READ(transconf_reg);
1175 /* wait for PCH transcoder off, transcoder state */
1176 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0)
1177 ;
1178 }
1179
1180 /* disable PCH DPLL */
1181 temp = I915_READ(pch_dpll_reg);
1182 if ((temp & DPLL_VCO_ENABLE) != 0) {
1183 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1184 I915_READ(pch_dpll_reg);
1185 }
1186
1187 temp = I915_READ(fdi_rx_reg);
1188 if ((temp & FDI_RX_PLL_ENABLE) != 0) {
1189 temp &= ~FDI_SEL_PCDCLK;
1190 temp &= ~FDI_RX_PLL_ENABLE;
1191 I915_WRITE(fdi_rx_reg, temp);
1192 I915_READ(fdi_rx_reg);
1193 }
1194
1195 /* Wait for the clocks to turn off. */
1196 udelay(150);
1197 break;
1198 }
1199}
1200
1201static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
797{ 1202{
798 struct drm_device *dev = crtc->dev; 1203 struct drm_device *dev = crtc->dev;
799 struct drm_i915_master_private *master_priv;
800 struct drm_i915_private *dev_priv = dev->dev_private; 1204 struct drm_i915_private *dev_priv = dev->dev_private;
801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
802 int pipe = intel_crtc->pipe; 1206 int pipe = intel_crtc->pipe;
@@ -805,7 +1209,6 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
805 int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR; 1209 int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
806 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; 1210 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
807 u32 temp; 1211 u32 temp;
808 bool enabled;
809 1212
810 /* XXX: When our outputs are all unaware of DPMS modes other than off 1213 /* XXX: When our outputs are all unaware of DPMS modes other than off
811 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. 1214 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
@@ -890,6 +1293,26 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
890 udelay(150); 1293 udelay(150);
891 break; 1294 break;
892 } 1295 }
1296}
1297
1298/**
1299 * Sets the power management mode of the pipe and plane.
1300 *
1301 * This code should probably grow support for turning the cursor off and back
1302 * on appropriately at the same time as we're turning the pipe off/on.
1303 */
1304static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1305{
1306 struct drm_device *dev = crtc->dev;
1307 struct drm_i915_master_private *master_priv;
1308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1309 int pipe = intel_crtc->pipe;
1310 bool enabled;
1311
1312 if (IS_IGDNG(dev))
1313 igdng_crtc_dpms(crtc, mode);
1314 else
1315 i9xx_crtc_dpms(crtc, mode);
893 1316
894 if (!dev->primary->master) 1317 if (!dev->primary->master)
895 return; 1318 return;
@@ -947,6 +1370,12 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
947 struct drm_display_mode *mode, 1370 struct drm_display_mode *mode,
948 struct drm_display_mode *adjusted_mode) 1371 struct drm_display_mode *adjusted_mode)
949{ 1372{
1373 struct drm_device *dev = crtc->dev;
1374 if (IS_IGDNG(dev)) {
1375 /* FDI link clock is fixed at 2.7G */
1376 if (mode->clock * 3 > 27000 * 4)
1377 return MODE_CLOCK_HIGH;
1378 }
950 return true; 1379 return true;
951} 1380}
952 1381
@@ -1030,6 +1459,48 @@ static int intel_panel_fitter_pipe (struct drm_device *dev)
1030 return 1; 1459 return 1;
1031} 1460}
1032 1461
1462struct fdi_m_n {
1463 u32 tu;
1464 u32 gmch_m;
1465 u32 gmch_n;
1466 u32 link_m;
1467 u32 link_n;
1468};
1469
1470static void
1471fdi_reduce_ratio(u32 *num, u32 *den)
1472{
1473 while (*num > 0xffffff || *den > 0xffffff) {
1474 *num >>= 1;
1475 *den >>= 1;
1476 }
1477}
1478
1479#define DATA_N 0x800000
1480#define LINK_N 0x80000
1481
1482static void
1483igdng_compute_m_n(int bytes_per_pixel, int nlanes,
1484 int pixel_clock, int link_clock,
1485 struct fdi_m_n *m_n)
1486{
1487 u64 temp;
1488
1489 m_n->tu = 64; /* default size */
1490
1491 temp = (u64) DATA_N * pixel_clock;
1492 temp = div_u64(temp, link_clock);
1493 m_n->gmch_m = (temp * bytes_per_pixel) / nlanes;
1494 m_n->gmch_n = DATA_N;
1495 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
1496
1497 temp = (u64) LINK_N * pixel_clock;
1498 m_n->link_m = div_u64(temp, link_clock);
1499 m_n->link_n = LINK_N;
1500 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
1501}
1502
1503
1033static int intel_crtc_mode_set(struct drm_crtc *crtc, 1504static int intel_crtc_mode_set(struct drm_crtc *crtc,
1034 struct drm_display_mode *mode, 1505 struct drm_display_mode *mode,
1035 struct drm_display_mode *adjusted_mode, 1506 struct drm_display_mode *adjusted_mode,
@@ -1063,6 +1534,17 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1063 struct drm_connector *connector; 1534 struct drm_connector *connector;
1064 const intel_limit_t *limit; 1535 const intel_limit_t *limit;
1065 int ret; 1536 int ret;
1537 struct fdi_m_n m_n = {0};
1538 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
1539 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
1540 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
1541 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
1542 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
1543 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1544 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1545 int lvds_reg = LVDS;
1546 u32 temp;
1547 int sdvo_pixel_multiply;
1066 1548
1067 drm_vblank_pre_modeset(dev, pipe); 1549 drm_vblank_pre_modeset(dev, pipe);
1068 1550
@@ -1101,6 +1583,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1101 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000); 1583 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk / 1000);
1102 } else if (IS_I9XX(dev)) { 1584 } else if (IS_I9XX(dev)) {
1103 refclk = 96000; 1585 refclk = 96000;
1586 if (IS_IGDNG(dev))
1587 refclk = 120000; /* 120Mhz refclk */
1104 } else { 1588 } else {
1105 refclk = 48000; 1589 refclk = 48000;
1106 } 1590 }
@@ -1114,6 +1598,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1114 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock); 1598 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
1115 if (!ok) { 1599 if (!ok) {
1116 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 1600 DRM_ERROR("Couldn't find PLL settings for mode!\n");
1601 drm_vblank_post_modeset(dev, pipe);
1117 return -EINVAL; 1602 return -EINVAL;
1118 } 1603 }
1119 1604
@@ -1137,12 +1622,21 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1137 } 1622 }
1138 } 1623 }
1139 1624
1625 /* FDI link */
1626 if (IS_IGDNG(dev))
1627 igdng_compute_m_n(3, 4, /* lane num 4 */
1628 adjusted_mode->clock,
1629 270000, /* lane clock */
1630 &m_n);
1631
1140 if (IS_IGD(dev)) 1632 if (IS_IGD(dev))
1141 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; 1633 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
1142 else 1634 else
1143 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 1635 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
1144 1636
1145 dpll = DPLL_VGA_MODE_DIS; 1637 if (!IS_IGDNG(dev))
1638 dpll = DPLL_VGA_MODE_DIS;
1639
1146 if (IS_I9XX(dev)) { 1640 if (IS_I9XX(dev)) {
1147 if (is_lvds) 1641 if (is_lvds)
1148 dpll |= DPLLB_MODE_LVDS; 1642 dpll |= DPLLB_MODE_LVDS;
@@ -1150,17 +1644,22 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1150 dpll |= DPLLB_MODE_DAC_SERIAL; 1644 dpll |= DPLLB_MODE_DAC_SERIAL;
1151 if (is_sdvo) { 1645 if (is_sdvo) {
1152 dpll |= DPLL_DVO_HIGH_SPEED; 1646 dpll |= DPLL_DVO_HIGH_SPEED;
1153 if (IS_I945G(dev) || IS_I945GM(dev)) { 1647 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1154 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 1648 if (IS_I945G(dev) || IS_I945GM(dev))
1155 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 1649 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
1156 } 1650 else if (IS_IGDNG(dev))
1651 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
1157 } 1652 }
1158 1653
1159 /* compute bitmask from p1 value */ 1654 /* compute bitmask from p1 value */
1160 if (IS_IGD(dev)) 1655 if (IS_IGD(dev))
1161 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD; 1656 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD;
1162 else 1657 else {
1163 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1658 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
1659 /* also FPA1 */
1660 if (IS_IGDNG(dev))
1661 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
1662 }
1164 switch (clock.p2) { 1663 switch (clock.p2) {
1165 case 5: 1664 case 5:
1166 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 1665 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
@@ -1175,7 +1674,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1175 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 1674 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
1176 break; 1675 break;
1177 } 1676 }
1178 if (IS_I965G(dev)) 1677 if (IS_I965G(dev) && !IS_IGDNG(dev))
1179 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 1678 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
1180 } else { 1679 } else {
1181 if (is_lvds) { 1680 if (is_lvds) {
@@ -1207,10 +1706,14 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1207 /* Set up the display plane register */ 1706 /* Set up the display plane register */
1208 dspcntr = DISPPLANE_GAMMA_ENABLE; 1707 dspcntr = DISPPLANE_GAMMA_ENABLE;
1209 1708
1210 if (pipe == 0) 1709 /* IGDNG's plane is forced to pipe, bit 24 is to
1211 dspcntr |= DISPPLANE_SEL_PIPE_A; 1710 enable color space conversion */
1212 else 1711 if (!IS_IGDNG(dev)) {
1213 dspcntr |= DISPPLANE_SEL_PIPE_B; 1712 if (pipe == 0)
1713 dspcntr |= DISPPLANE_SEL_PIPE_A;
1714 else
1715 dspcntr |= DISPPLANE_SEL_PIPE_B;
1716 }
1214 1717
1215 if (pipe == 0 && !IS_I965G(dev)) { 1718 if (pipe == 0 && !IS_I965G(dev)) {
1216 /* Enable pixel doubling when the dot clock is > 90% of the (display) 1719 /* Enable pixel doubling when the dot clock is > 90% of the (display)
@@ -1231,12 +1734,17 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1231 1734
1232 1735
1233 /* Disable the panel fitter if it was on our pipe */ 1736 /* Disable the panel fitter if it was on our pipe */
1234 if (intel_panel_fitter_pipe(dev) == pipe) 1737 if (!IS_IGDNG(dev) && intel_panel_fitter_pipe(dev) == pipe)
1235 I915_WRITE(PFIT_CONTROL, 0); 1738 I915_WRITE(PFIT_CONTROL, 0);
1236 1739
1237 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 1740 DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
1238 drm_mode_debug_printmodeline(mode); 1741 drm_mode_debug_printmodeline(mode);
1239 1742
1743 /* assign to IGDNG registers */
1744 if (IS_IGDNG(dev)) {
1745 fp_reg = pch_fp_reg;
1746 dpll_reg = pch_dpll_reg;
1747 }
1240 1748
1241 if (dpll & DPLL_VCO_ENABLE) { 1749 if (dpll & DPLL_VCO_ENABLE) {
1242 I915_WRITE(fp_reg, fp); 1750 I915_WRITE(fp_reg, fp);
@@ -1245,13 +1753,33 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1245 udelay(150); 1753 udelay(150);
1246 } 1754 }
1247 1755
1756 if (IS_IGDNG(dev)) {
1757 /* enable PCH clock reference source */
1758 /* XXX need to change the setting for other outputs */
1759 u32 temp;
1760 temp = I915_READ(PCH_DREF_CONTROL);
1761 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
1762 temp |= DREF_NONSPREAD_CK505_ENABLE;
1763 temp &= ~DREF_SSC_SOURCE_MASK;
1764 temp |= DREF_SSC_SOURCE_ENABLE;
1765 temp &= ~DREF_SSC1_ENABLE;
1766 /* if no eDP, disable source output to CPU */
1767 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
1768 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
1769 I915_WRITE(PCH_DREF_CONTROL, temp);
1770 }
1771
1248 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 1772 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1249 * This is an exception to the general rule that mode_set doesn't turn 1773 * This is an exception to the general rule that mode_set doesn't turn
1250 * things on. 1774 * things on.
1251 */ 1775 */
1252 if (is_lvds) { 1776 if (is_lvds) {
1253 u32 lvds = I915_READ(LVDS); 1777 u32 lvds;
1254 1778
1779 if (IS_IGDNG(dev))
1780 lvds_reg = PCH_LVDS;
1781
1782 lvds = I915_READ(lvds_reg);
1255 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; 1783 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
1256 /* Set the B0-B3 data pairs corresponding to whether we're going to 1784 /* Set the B0-B3 data pairs corresponding to whether we're going to
1257 * set the DPLLs for dual-channel mode or not. 1785 * set the DPLLs for dual-channel mode or not.
@@ -1266,8 +1794,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1266 * panels behave in the two modes. 1794 * panels behave in the two modes.
1267 */ 1795 */
1268 1796
1269 I915_WRITE(LVDS, lvds); 1797 I915_WRITE(lvds_reg, lvds);
1270 I915_READ(LVDS); 1798 I915_READ(lvds_reg);
1271 } 1799 }
1272 1800
1273 I915_WRITE(fp_reg, fp); 1801 I915_WRITE(fp_reg, fp);
@@ -1276,8 +1804,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1276 /* Wait for the clocks to stabilize. */ 1804 /* Wait for the clocks to stabilize. */
1277 udelay(150); 1805 udelay(150);
1278 1806
1279 if (IS_I965G(dev)) { 1807 if (IS_I965G(dev) && !IS_IGDNG(dev)) {
1280 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; 1808 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1281 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | 1809 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
1282 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); 1810 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
1283 } else { 1811 } else {
@@ -1303,9 +1831,25 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1303 /* pipesrc and dspsize control the size that is scaled from, which should 1831 /* pipesrc and dspsize control the size that is scaled from, which should
1304 * always be the user's requested size. 1832 * always be the user's requested size.
1305 */ 1833 */
1306 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); 1834 if (!IS_IGDNG(dev)) {
1307 I915_WRITE(dsppos_reg, 0); 1835 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
1836 (mode->hdisplay - 1));
1837 I915_WRITE(dsppos_reg, 0);
1838 }
1308 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 1839 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
1840
1841 if (IS_IGDNG(dev)) {
1842 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
1843 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
1844 I915_WRITE(link_m1_reg, m_n.link_m);
1845 I915_WRITE(link_n1_reg, m_n.link_n);
1846
1847 /* enable FDI RX PLL too */
1848 temp = I915_READ(fdi_rx_reg);
1849 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
1850 udelay(200);
1851 }
1852
1309 I915_WRITE(pipeconf_reg, pipeconf); 1853 I915_WRITE(pipeconf_reg, pipeconf);
1310 I915_READ(pipeconf_reg); 1854 I915_READ(pipeconf_reg);
1311 1855
@@ -1315,12 +1859,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
1315 1859
1316 /* Flush the plane changes */ 1860 /* Flush the plane changes */
1317 ret = intel_pipe_set_base(crtc, x, y, old_fb); 1861 ret = intel_pipe_set_base(crtc, x, y, old_fb);
1318 if (ret != 0)
1319 return ret;
1320
1321 drm_vblank_post_modeset(dev, pipe); 1862 drm_vblank_post_modeset(dev, pipe);
1322 1863
1323 return 0; 1864 return ret;
1324} 1865}
1325 1866
1326/** Loads the palette/gamma unit for the CRTC with the prepared values */ 1867/** Loads the palette/gamma unit for the CRTC with the prepared values */
@@ -1336,6 +1877,11 @@ void intel_crtc_load_lut(struct drm_crtc *crtc)
1336 if (!crtc->enabled) 1877 if (!crtc->enabled)
1337 return; 1878 return;
1338 1879
1880 /* use legacy palette for IGDNG */
1881 if (IS_IGDNG(dev))
1882 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
1883 LGC_PALETTE_B;
1884
1339 for (i = 0; i < 256; i++) { 1885 for (i = 0; i < 256; i++) {
1340 I915_WRITE(palreg + 4 * i, 1886 I915_WRITE(palreg + 4 * i,
1341 (intel_crtc->lut_r[i] << 16) | 1887 (intel_crtc->lut_r[i] << 16) |
@@ -1464,16 +2010,16 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1464 uint32_t adder; 2010 uint32_t adder;
1465 2011
1466 if (x < 0) { 2012 if (x < 0) {
1467 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); 2013 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
1468 x = -x; 2014 x = -x;
1469 } 2015 }
1470 if (y < 0) { 2016 if (y < 0) {
1471 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); 2017 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
1472 y = -y; 2018 y = -y;
1473 } 2019 }
1474 2020
1475 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); 2021 temp |= x << CURSOR_X_SHIFT;
1476 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); 2022 temp |= y << CURSOR_Y_SHIFT;
1477 2023
1478 adder = intel_crtc->cursor_addr; 2024 adder = intel_crtc->cursor_addr;
1479 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); 2025 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
@@ -1590,6 +2136,7 @@ struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
1590 } 2136 }
1591 2137
1592 encoder->crtc = crtc; 2138 encoder->crtc = crtc;
2139 intel_output->base.encoder = encoder;
1593 intel_output->load_detect_temp = true; 2140 intel_output->load_detect_temp = true;
1594 2141
1595 intel_crtc = to_intel_crtc(crtc); 2142 intel_crtc = to_intel_crtc(crtc);
@@ -1625,6 +2172,7 @@ void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_
1625 2172
1626 if (intel_output->load_detect_temp) { 2173 if (intel_output->load_detect_temp) {
1627 encoder->crtc = NULL; 2174 encoder->crtc = NULL;
2175 intel_output->base.encoder = NULL;
1628 intel_output->load_detect_temp = false; 2176 intel_output->load_detect_temp = false;
1629 crtc->enabled = drm_helper_crtc_in_use(crtc); 2177 crtc->enabled = drm_helper_crtc_in_use(crtc);
1630 drm_helper_disable_unused_functions(dev); 2178 drm_helper_disable_unused_functions(dev);
@@ -1762,6 +2310,8 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
1762{ 2310{
1763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1764 2312
2313 if (intel_crtc->mode_set.mode)
2314 drm_mode_destroy(crtc->dev, intel_crtc->mode_set.mode);
1765 drm_crtc_cleanup(crtc); 2315 drm_crtc_cleanup(crtc);
1766 kfree(intel_crtc); 2316 kfree(intel_crtc);
1767} 2317}
@@ -1888,7 +2438,24 @@ static void intel_setup_outputs(struct drm_device *dev)
1888 if (IS_MOBILE(dev) && !IS_I830(dev)) 2438 if (IS_MOBILE(dev) && !IS_I830(dev))
1889 intel_lvds_init(dev); 2439 intel_lvds_init(dev);
1890 2440
1891 if (IS_I9XX(dev)) { 2441 if (IS_IGDNG(dev)) {
2442 int found;
2443
2444 if (I915_READ(HDMIB) & PORT_DETECTED) {
2445 /* check SDVOB */
2446 /* found = intel_sdvo_init(dev, HDMIB); */
2447 found = 0;
2448 if (!found)
2449 intel_hdmi_init(dev, HDMIB);
2450 }
2451
2452 if (I915_READ(HDMIC) & PORT_DETECTED)
2453 intel_hdmi_init(dev, HDMIC);
2454
2455 if (I915_READ(HDMID) & PORT_DETECTED)
2456 intel_hdmi_init(dev, HDMID);
2457
2458 } else if (IS_I9XX(dev)) {
1892 int found; 2459 int found;
1893 u32 reg; 2460 u32 reg;
1894 2461
@@ -1912,7 +2479,7 @@ static void intel_setup_outputs(struct drm_device *dev)
1912 } else 2479 } else
1913 intel_dvo_init(dev); 2480 intel_dvo_init(dev);
1914 2481
1915 if (IS_I9XX(dev) && IS_MOBILE(dev)) 2482 if (IS_I9XX(dev) && IS_MOBILE(dev) && !IS_IGDNG(dev))
1916 intel_tv_init(dev); 2483 intel_tv_init(dev);
1917 2484
1918 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 2485 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index e4652dcdd9bb..0ecf6b76a401 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -207,7 +207,7 @@ static int intelfb_set_par(struct fb_info *info)
207 207
208 if (var->pixclock != -1) { 208 if (var->pixclock != -1) {
209 209
210 DRM_ERROR("PIXEL CLCOK SET\n"); 210 DRM_ERROR("PIXEL CLOCK SET\n");
211 return -EINVAL; 211 return -EINVAL;
212 } else { 212 } else {
213 struct drm_crtc *crtc; 213 struct drm_crtc *crtc;
@@ -674,8 +674,12 @@ static int intelfb_multi_fb_probe_crtc(struct drm_device *dev, struct drm_crtc *
674 par->crtc_ids[0] = crtc->base.id; 674 par->crtc_ids[0] = crtc->base.id;
675 675
676 modeset->num_connectors = conn_count; 676 modeset->num_connectors = conn_count;
677 if (modeset->mode != modeset->crtc->desired_mode) 677 if (modeset->crtc->desired_mode) {
678 modeset->mode = modeset->crtc->desired_mode; 678 if (modeset->mode)
679 drm_mode_destroy(dev, modeset->mode);
680 modeset->mode = drm_mode_duplicate(dev,
681 modeset->crtc->desired_mode);
682 }
679 683
680 par->crtc_count = 1; 684 par->crtc_count = 1;
681 685
@@ -824,8 +828,12 @@ static int intelfb_single_fb_probe(struct drm_device *dev)
824 par->crtc_ids[crtc_count++] = crtc->base.id; 828 par->crtc_ids[crtc_count++] = crtc->base.id;
825 829
826 modeset->num_connectors = conn_count; 830 modeset->num_connectors = conn_count;
827 if (modeset->mode != modeset->crtc->desired_mode) 831 if (modeset->crtc->desired_mode) {
828 modeset->mode = modeset->crtc->desired_mode; 832 if (modeset->mode)
833 drm_mode_destroy(dev, modeset->mode);
834 modeset->mode = drm_mode_duplicate(dev,
835 modeset->crtc->desired_mode);
836 }
829 } 837 }
830 par->crtc_count = crtc_count; 838 par->crtc_count = crtc_count;
831 839
@@ -857,9 +865,15 @@ void intelfb_restore(void)
857 drm_crtc_helper_set_config(&kernelfb_mode); 865 drm_crtc_helper_set_config(&kernelfb_mode);
858} 866}
859 867
868static void intelfb_restore_work_fn(struct work_struct *ignored)
869{
870 intelfb_restore();
871}
872static DECLARE_WORK(intelfb_restore_work, intelfb_restore_work_fn);
873
860static void intelfb_sysrq(int dummy1, struct tty_struct *dummy3) 874static void intelfb_sysrq(int dummy1, struct tty_struct *dummy3)
861{ 875{
862 intelfb_restore(); 876 schedule_work(&intelfb_restore_work);
863} 877}
864 878
865static struct sysrq_key_op sysrq_intelfb_restore_op = { 879static struct sysrq_key_op sysrq_intelfb_restore_op = {
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 7d6bdd705326..4ea2a651b92c 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -56,7 +56,8 @@ static void intel_hdmi_mode_set(struct drm_encoder *encoder,
56 sdvox = SDVO_ENCODING_HDMI | 56 sdvox = SDVO_ENCODING_HDMI |
57 SDVO_BORDER_ENABLE | 57 SDVO_BORDER_ENABLE |
58 SDVO_VSYNC_ACTIVE_HIGH | 58 SDVO_VSYNC_ACTIVE_HIGH |
59 SDVO_HSYNC_ACTIVE_HIGH; 59 SDVO_HSYNC_ACTIVE_HIGH |
60 SDVO_NULL_PACKETS_DURING_VSYNC;
60 61
61 if (hdmi_priv->has_hdmi_sink) 62 if (hdmi_priv->has_hdmi_sink)
62 sdvox |= SDVO_AUDIO_ENABLE; 63 sdvox |= SDVO_AUDIO_ENABLE;
@@ -145,6 +146,22 @@ intel_hdmi_sink_detect(struct drm_connector *connector)
145} 146}
146 147
147static enum drm_connector_status 148static enum drm_connector_status
149igdng_hdmi_detect(struct drm_connector *connector)
150{
151 struct intel_output *intel_output = to_intel_output(connector);
152 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
153
154 /* FIXME hotplug detect */
155
156 hdmi_priv->has_hdmi_sink = false;
157 intel_hdmi_sink_detect(connector);
158 if (hdmi_priv->has_hdmi_sink)
159 return connector_status_connected;
160 else
161 return connector_status_disconnected;
162}
163
164static enum drm_connector_status
148intel_hdmi_detect(struct drm_connector *connector) 165intel_hdmi_detect(struct drm_connector *connector)
149{ 166{
150 struct drm_device *dev = connector->dev; 167 struct drm_device *dev = connector->dev;
@@ -153,6 +170,9 @@ intel_hdmi_detect(struct drm_connector *connector)
153 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv; 170 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
154 u32 temp, bit; 171 u32 temp, bit;
155 172
173 if (IS_IGDNG(dev))
174 return igdng_hdmi_detect(connector);
175
156 temp = I915_READ(PORT_HOTPLUG_EN); 176 temp = I915_READ(PORT_HOTPLUG_EN);
157 177
158 switch (hdmi_priv->sdvox_reg) { 178 switch (hdmi_priv->sdvox_reg) {
@@ -269,8 +289,17 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
269 /* Set up the DDC bus. */ 289 /* Set up the DDC bus. */
270 if (sdvox_reg == SDVOB) 290 if (sdvox_reg == SDVOB)
271 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB"); 291 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB");
272 else 292 else if (sdvox_reg == SDVOC)
273 intel_output->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC"); 293 intel_output->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC");
294 else if (sdvox_reg == HDMIB)
295 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOE,
296 "HDMIB");
297 else if (sdvox_reg == HDMIC)
298 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOD,
299 "HDMIC");
300 else if (sdvox_reg == HDMID)
301 intel_output->ddc_bus = intel_i2c_create(dev, PCH_GPIOF,
302 "HDMID");
274 303
275 if (!intel_output->ddc_bus) 304 if (!intel_output->ddc_bus)
276 goto err_connector; 305 goto err_connector;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 53cccfa58b95..f073ed8432e8 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -37,6 +37,8 @@
37#include "i915_drm.h" 37#include "i915_drm.h"
38#include "i915_drv.h" 38#include "i915_drv.h"
39 39
40#define I915_LVDS "i915_lvds"
41
40/** 42/**
41 * Sets the backlight level. 43 * Sets the backlight level.
42 * 44 *
@@ -45,10 +47,15 @@
45static void intel_lvds_set_backlight(struct drm_device *dev, int level) 47static void intel_lvds_set_backlight(struct drm_device *dev, int level)
46{ 48{
47 struct drm_i915_private *dev_priv = dev->dev_private; 49 struct drm_i915_private *dev_priv = dev->dev_private;
48 u32 blc_pwm_ctl; 50 u32 blc_pwm_ctl, reg;
51
52 if (IS_IGDNG(dev))
53 reg = BLC_PWM_CPU_CTL;
54 else
55 reg = BLC_PWM_CTL;
49 56
50 blc_pwm_ctl = I915_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; 57 blc_pwm_ctl = I915_READ(reg) & ~BACKLIGHT_DUTY_CYCLE_MASK;
51 I915_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | 58 I915_WRITE(reg, (blc_pwm_ctl |
52 (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); 59 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
53} 60}
54 61
@@ -58,8 +65,14 @@ static void intel_lvds_set_backlight(struct drm_device *dev, int level)
58static u32 intel_lvds_get_max_backlight(struct drm_device *dev) 65static u32 intel_lvds_get_max_backlight(struct drm_device *dev)
59{ 66{
60 struct drm_i915_private *dev_priv = dev->dev_private; 67 struct drm_i915_private *dev_priv = dev->dev_private;
68 u32 reg;
69
70 if (IS_IGDNG(dev))
71 reg = BLC_PWM_PCH_CTL2;
72 else
73 reg = BLC_PWM_CTL;
61 74
62 return ((I915_READ(BLC_PWM_CTL) & BACKLIGHT_MODULATION_FREQ_MASK) >> 75 return ((I915_READ(reg) & BACKLIGHT_MODULATION_FREQ_MASK) >>
63 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2; 76 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
64} 77}
65 78
@@ -69,23 +82,31 @@ static u32 intel_lvds_get_max_backlight(struct drm_device *dev)
69static void intel_lvds_set_power(struct drm_device *dev, bool on) 82static void intel_lvds_set_power(struct drm_device *dev, bool on)
70{ 83{
71 struct drm_i915_private *dev_priv = dev->dev_private; 84 struct drm_i915_private *dev_priv = dev->dev_private;
72 u32 pp_status; 85 u32 pp_status, ctl_reg, status_reg;
86
87 if (IS_IGDNG(dev)) {
88 ctl_reg = PCH_PP_CONTROL;
89 status_reg = PCH_PP_STATUS;
90 } else {
91 ctl_reg = PP_CONTROL;
92 status_reg = PP_STATUS;
93 }
73 94
74 if (on) { 95 if (on) {
75 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | 96 I915_WRITE(ctl_reg, I915_READ(ctl_reg) |
76 POWER_TARGET_ON); 97 POWER_TARGET_ON);
77 do { 98 do {
78 pp_status = I915_READ(PP_STATUS); 99 pp_status = I915_READ(status_reg);
79 } while ((pp_status & PP_ON) == 0); 100 } while ((pp_status & PP_ON) == 0);
80 101
81 intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle); 102 intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle);
82 } else { 103 } else {
83 intel_lvds_set_backlight(dev, 0); 104 intel_lvds_set_backlight(dev, 0);
84 105
85 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 106 I915_WRITE(ctl_reg, I915_READ(ctl_reg) &
86 ~POWER_TARGET_ON); 107 ~POWER_TARGET_ON);
87 do { 108 do {
88 pp_status = I915_READ(PP_STATUS); 109 pp_status = I915_READ(status_reg);
89 } while (pp_status & PP_ON); 110 } while (pp_status & PP_ON);
90 } 111 }
91} 112}
@@ -106,12 +127,28 @@ static void intel_lvds_save(struct drm_connector *connector)
106{ 127{
107 struct drm_device *dev = connector->dev; 128 struct drm_device *dev = connector->dev;
108 struct drm_i915_private *dev_priv = dev->dev_private; 129 struct drm_i915_private *dev_priv = dev->dev_private;
130 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
131 u32 pwm_ctl_reg;
132
133 if (IS_IGDNG(dev)) {
134 pp_on_reg = PCH_PP_ON_DELAYS;
135 pp_off_reg = PCH_PP_OFF_DELAYS;
136 pp_ctl_reg = PCH_PP_CONTROL;
137 pp_div_reg = PCH_PP_DIVISOR;
138 pwm_ctl_reg = BLC_PWM_CPU_CTL;
139 } else {
140 pp_on_reg = PP_ON_DELAYS;
141 pp_off_reg = PP_OFF_DELAYS;
142 pp_ctl_reg = PP_CONTROL;
143 pp_div_reg = PP_DIVISOR;
144 pwm_ctl_reg = BLC_PWM_CTL;
145 }
109 146
110 dev_priv->savePP_ON = I915_READ(PP_ON_DELAYS); 147 dev_priv->savePP_ON = I915_READ(pp_on_reg);
111 dev_priv->savePP_OFF = I915_READ(PP_OFF_DELAYS); 148 dev_priv->savePP_OFF = I915_READ(pp_off_reg);
112 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); 149 dev_priv->savePP_CONTROL = I915_READ(pp_ctl_reg);
113 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); 150 dev_priv->savePP_DIVISOR = I915_READ(pp_div_reg);
114 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); 151 dev_priv->saveBLC_PWM_CTL = I915_READ(pwm_ctl_reg);
115 dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & 152 dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
116 BACKLIGHT_DUTY_CYCLE_MASK); 153 BACKLIGHT_DUTY_CYCLE_MASK);
117 154
@@ -127,12 +164,28 @@ static void intel_lvds_restore(struct drm_connector *connector)
127{ 164{
128 struct drm_device *dev = connector->dev; 165 struct drm_device *dev = connector->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private; 166 struct drm_i915_private *dev_priv = dev->dev_private;
167 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
168 u32 pwm_ctl_reg;
169
170 if (IS_IGDNG(dev)) {
171 pp_on_reg = PCH_PP_ON_DELAYS;
172 pp_off_reg = PCH_PP_OFF_DELAYS;
173 pp_ctl_reg = PCH_PP_CONTROL;
174 pp_div_reg = PCH_PP_DIVISOR;
175 pwm_ctl_reg = BLC_PWM_CPU_CTL;
176 } else {
177 pp_on_reg = PP_ON_DELAYS;
178 pp_off_reg = PP_OFF_DELAYS;
179 pp_ctl_reg = PP_CONTROL;
180 pp_div_reg = PP_DIVISOR;
181 pwm_ctl_reg = BLC_PWM_CTL;
182 }
130 183
131 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); 184 I915_WRITE(pwm_ctl_reg, dev_priv->saveBLC_PWM_CTL);
132 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON); 185 I915_WRITE(pp_on_reg, dev_priv->savePP_ON);
133 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF); 186 I915_WRITE(pp_off_reg, dev_priv->savePP_OFF);
134 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); 187 I915_WRITE(pp_div_reg, dev_priv->savePP_DIVISOR);
135 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); 188 I915_WRITE(pp_ctl_reg, dev_priv->savePP_CONTROL);
136 if (dev_priv->savePP_CONTROL & POWER_TARGET_ON) 189 if (dev_priv->savePP_CONTROL & POWER_TARGET_ON)
137 intel_lvds_set_power(dev, true); 190 intel_lvds_set_power(dev, true);
138 else 191 else
@@ -216,8 +269,14 @@ static void intel_lvds_prepare(struct drm_encoder *encoder)
216{ 269{
217 struct drm_device *dev = encoder->dev; 270 struct drm_device *dev = encoder->dev;
218 struct drm_i915_private *dev_priv = dev->dev_private; 271 struct drm_i915_private *dev_priv = dev->dev_private;
272 u32 reg;
273
274 if (IS_IGDNG(dev))
275 reg = BLC_PWM_CPU_CTL;
276 else
277 reg = BLC_PWM_CTL;
219 278
220 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); 279 dev_priv->saveBLC_PWM_CTL = I915_READ(reg);
221 dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & 280 dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
222 BACKLIGHT_DUTY_CYCLE_MASK); 281 BACKLIGHT_DUTY_CYCLE_MASK);
223 282
@@ -251,6 +310,10 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
251 * settings. 310 * settings.
252 */ 311 */
253 312
313 /* No panel fitting yet, fixme */
314 if (IS_IGDNG(dev))
315 return;
316
254 /* 317 /*
255 * Enable automatic panel scaling so that non-native modes fill the 318 * Enable automatic panel scaling so that non-native modes fill the
256 * screen. Should be enabled before the pipe is enabled, according to 319 * screen. Should be enabled before the pipe is enabled, according to
@@ -382,7 +445,8 @@ static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
382 445
383static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 446static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
384{ 447{
385 DRM_DEBUG("Skipping LVDS initialization for %s\n", id->ident); 448 DRM_DEBUG_KMS(I915_LVDS,
449 "Skipping LVDS initialization for %s\n", id->ident);
386 return 1; 450 return 1;
387} 451}
388 452
@@ -420,8 +484,21 @@ static const struct dmi_system_id intel_no_lvds[] = {
420 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 484 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
421 }, 485 },
422 }, 486 },
423 487 {
424 /* FIXME: add a check for the Aopen Mini PC */ 488 .callback = intel_no_lvds_dmi_callback,
489 .ident = "AOpen Mini PC",
490 .matches = {
491 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
492 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
493 },
494 },
495 {
496 .callback = intel_no_lvds_dmi_callback,
497 .ident = "Aopen i945GTt-VFA",
498 .matches = {
499 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
500 },
501 },
425 502
426 { } /* terminating entry */ 503 { } /* terminating entry */
427}; 504};
@@ -442,12 +519,18 @@ void intel_lvds_init(struct drm_device *dev)
442 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 519 struct drm_display_mode *scan; /* *modes, *bios_mode; */
443 struct drm_crtc *crtc; 520 struct drm_crtc *crtc;
444 u32 lvds; 521 u32 lvds;
445 int pipe; 522 int pipe, gpio = GPIOC;
446 523
447 /* Skip init on machines we know falsely report LVDS */ 524 /* Skip init on machines we know falsely report LVDS */
448 if (dmi_check_system(intel_no_lvds)) 525 if (dmi_check_system(intel_no_lvds))
449 return; 526 return;
450 527
528 if (IS_IGDNG(dev)) {
529 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
530 return;
531 gpio = PCH_GPIOC;
532 }
533
451 intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); 534 intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL);
452 if (!intel_output) { 535 if (!intel_output) {
453 return; 536 return;
@@ -482,7 +565,7 @@ void intel_lvds_init(struct drm_device *dev)
482 */ 565 */
483 566
484 /* Set up the DDC bus. */ 567 /* Set up the DDC bus. */
485 intel_output->ddc_bus = intel_i2c_create(dev, GPIOC, "LVDSDDC_C"); 568 intel_output->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C");
486 if (!intel_output->ddc_bus) { 569 if (!intel_output->ddc_bus) {
487 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration " 570 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
488 "failed.\n"); 571 "failed.\n");
@@ -524,6 +607,11 @@ void intel_lvds_init(struct drm_device *dev)
524 * on. If so, assume that whatever is currently programmed is the 607 * on. If so, assume that whatever is currently programmed is the
525 * correct mode. 608 * correct mode.
526 */ 609 */
610
611 /* IGDNG: FIXME if still fail, not try pipe mode now */
612 if (IS_IGDNG(dev))
613 goto failed;
614
527 lvds = I915_READ(LVDS); 615 lvds = I915_READ(LVDS);
528 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; 616 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
529 crtc = intel_get_crtc_from_pipe(dev, pipe); 617 crtc = intel_get_crtc_from_pipe(dev, pipe);
@@ -542,11 +630,22 @@ void intel_lvds_init(struct drm_device *dev)
542 goto failed; 630 goto failed;
543 631
544out: 632out:
633 if (IS_IGDNG(dev)) {
634 u32 pwm;
635 /* make sure PWM is enabled */
636 pwm = I915_READ(BLC_PWM_CPU_CTL2);
637 pwm |= (PWM_ENABLE | PWM_PIPE_B);
638 I915_WRITE(BLC_PWM_CPU_CTL2, pwm);
639
640 pwm = I915_READ(BLC_PWM_PCH_CTL1);
641 pwm |= PWM_PCH_ENABLE;
642 I915_WRITE(BLC_PWM_PCH_CTL1, pwm);
643 }
545 drm_sysfs_connector_add(connector); 644 drm_sysfs_connector_add(connector);
546 return; 645 return;
547 646
548failed: 647failed:
549 DRM_DEBUG("No LVDS modes found, disabling.\n"); 648 DRM_DEBUG_KMS(I915_LVDS, "No LVDS modes found, disabling.\n");
550 if (intel_output->ddc_bus) 649 if (intel_output->ddc_bus)
551 intel_i2c_destroy(intel_output->ddc_bus); 650 intel_i2c_destroy(intel_output->ddc_bus);
552 drm_connector_cleanup(connector); 651 drm_connector_cleanup(connector);
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 3093b4d4a4dd..9a00adb3a508 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -36,7 +36,7 @@
36#include "intel_sdvo_regs.h" 36#include "intel_sdvo_regs.h"
37 37
38#undef SDVO_DEBUG 38#undef SDVO_DEBUG
39 39#define I915_SDVO "i915_sdvo"
40struct intel_sdvo_priv { 40struct intel_sdvo_priv {
41 struct intel_i2c_chan *i2c_bus; 41 struct intel_i2c_chan *i2c_bus;
42 int slaveaddr; 42 int slaveaddr;
@@ -277,20 +277,21 @@ static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
277 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 277 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
278 int i; 278 int i;
279 279
280 printk(KERN_DEBUG "%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd); 280 DRM_DEBUG_KMS(I915_SDVO, "%s: W: %02X ",
281 SDVO_NAME(sdvo_priv), cmd);
281 for (i = 0; i < args_len; i++) 282 for (i = 0; i < args_len; i++)
282 printk(KERN_DEBUG "%02X ", ((u8 *)args)[i]); 283 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
283 for (; i < 8; i++) 284 for (; i < 8; i++)
284 printk(KERN_DEBUG " "); 285 DRM_LOG_KMS(" ");
285 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) { 286 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
286 if (cmd == sdvo_cmd_names[i].cmd) { 287 if (cmd == sdvo_cmd_names[i].cmd) {
287 printk(KERN_DEBUG "(%s)", sdvo_cmd_names[i].name); 288 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
288 break; 289 break;
289 } 290 }
290 } 291 }
291 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0])) 292 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
292 printk(KERN_DEBUG "(%02X)", cmd); 293 DRM_LOG_KMS("(%02X)", cmd);
293 printk(KERN_DEBUG "\n"); 294 DRM_LOG_KMS("\n");
294} 295}
295#else 296#else
296#define intel_sdvo_debug_write(o, c, a, l) 297#define intel_sdvo_debug_write(o, c, a, l)
@@ -329,16 +330,16 @@ static void intel_sdvo_debug_response(struct intel_output *intel_output,
329 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; 330 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
330 int i; 331 int i;
331 332
332 printk(KERN_DEBUG "%s: R: ", SDVO_NAME(sdvo_priv)); 333 DRM_DEBUG_KMS(I915_SDVO, "%s: R: ", SDVO_NAME(sdvo_priv));
333 for (i = 0; i < response_len; i++) 334 for (i = 0; i < response_len; i++)
334 printk(KERN_DEBUG "%02X ", ((u8 *)response)[i]); 335 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
335 for (; i < 8; i++) 336 for (; i < 8; i++)
336 printk(KERN_DEBUG " "); 337 DRM_LOG_KMS(" ");
337 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 338 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
338 printk(KERN_DEBUG "(%s)", cmd_status_names[status]); 339 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
339 else 340 else
340 printk(KERN_DEBUG "(??? %d)", status); 341 DRM_LOG_KMS("(??? %d)", status);
341 printk(KERN_DEBUG "\n"); 342 DRM_LOG_KMS("\n");
342} 343}
343#else 344#else
344#define intel_sdvo_debug_response(o, r, l, s) 345#define intel_sdvo_debug_response(o, r, l, s)
@@ -1742,6 +1743,43 @@ static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
1742 .master_xfer = intel_sdvo_master_xfer, 1743 .master_xfer = intel_sdvo_master_xfer,
1743}; 1744};
1744 1745
1746static u8
1747intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
1748{
1749 struct drm_i915_private *dev_priv = dev->dev_private;
1750 struct sdvo_device_mapping *my_mapping, *other_mapping;
1751
1752 if (output_device == SDVOB) {
1753 my_mapping = &dev_priv->sdvo_mappings[0];
1754 other_mapping = &dev_priv->sdvo_mappings[1];
1755 } else {
1756 my_mapping = &dev_priv->sdvo_mappings[1];
1757 other_mapping = &dev_priv->sdvo_mappings[0];
1758 }
1759
1760 /* If the BIOS described our SDVO device, take advantage of it. */
1761 if (my_mapping->slave_addr)
1762 return my_mapping->slave_addr;
1763
1764 /* If the BIOS only described a different SDVO device, use the
1765 * address that it isn't using.
1766 */
1767 if (other_mapping->slave_addr) {
1768 if (other_mapping->slave_addr == 0x70)
1769 return 0x72;
1770 else
1771 return 0x70;
1772 }
1773
1774 /* No SDVO device info is found for another DVO port,
1775 * so use mapping assumption we had before BIOS parsing.
1776 */
1777 if (output_device == SDVOB)
1778 return 0x70;
1779 else
1780 return 0x72;
1781}
1782
1745bool intel_sdvo_init(struct drm_device *dev, int output_device) 1783bool intel_sdvo_init(struct drm_device *dev, int output_device)
1746{ 1784{
1747 struct drm_connector *connector; 1785 struct drm_connector *connector;
@@ -1753,6 +1791,7 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
1753 u8 ch[0x40]; 1791 u8 ch[0x40];
1754 int i; 1792 int i;
1755 int encoder_type, output_id; 1793 int encoder_type, output_id;
1794 u8 slave_addr;
1756 1795
1757 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL); 1796 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
1758 if (!intel_output) { 1797 if (!intel_output) {
@@ -1771,16 +1810,15 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
1771 if (!i2cbus) 1810 if (!i2cbus)
1772 goto err_inteloutput; 1811 goto err_inteloutput;
1773 1812
1813 slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
1774 sdvo_priv->i2c_bus = i2cbus; 1814 sdvo_priv->i2c_bus = i2cbus;
1775 1815
1776 if (output_device == SDVOB) { 1816 if (output_device == SDVOB) {
1777 output_id = 1; 1817 output_id = 1;
1778 sdvo_priv->i2c_bus->slave_addr = 0x38;
1779 } else { 1818 } else {
1780 output_id = 2; 1819 output_id = 2;
1781 sdvo_priv->i2c_bus->slave_addr = 0x39;
1782 } 1820 }
1783 1821 sdvo_priv->i2c_bus->slave_addr = slave_addr >> 1;
1784 sdvo_priv->output_device = output_device; 1822 sdvo_priv->output_device = output_device;
1785 intel_output->i2c_bus = i2cbus; 1823 intel_output->i2c_bus = i2cbus;
1786 intel_output->dev_priv = sdvo_priv; 1824 intel_output->dev_priv = sdvo_priv;
@@ -1788,8 +1826,9 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
1788 /* Read the regs to test if we can talk to the device */ 1826 /* Read the regs to test if we can talk to the device */
1789 for (i = 0; i < 0x40; i++) { 1827 for (i = 0; i < 0x40; i++) {
1790 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) { 1828 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
1791 DRM_DEBUG("No SDVO device found on SDVO%c\n", 1829 DRM_DEBUG_KMS(I915_SDVO,
1792 output_device == SDVOB ? 'B' : 'C'); 1830 "No SDVO device found on SDVO%c\n",
1831 output_device == SDVOB ? 'B' : 'C');
1793 goto err_i2c; 1832 goto err_i2c;
1794 } 1833 }
1795 } 1834 }
@@ -1873,9 +1912,10 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
1873 1912
1874 sdvo_priv->controlled_output = 0; 1913 sdvo_priv->controlled_output = 0;
1875 memcpy (bytes, &sdvo_priv->caps.output_flags, 2); 1914 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
1876 DRM_DEBUG("%s: Unknown SDVO output type (0x%02x%02x)\n", 1915 DRM_DEBUG_KMS(I915_SDVO,
1877 SDVO_NAME(sdvo_priv), 1916 "%s: Unknown SDVO output type (0x%02x%02x)\n",
1878 bytes[0], bytes[1]); 1917 SDVO_NAME(sdvo_priv),
1918 bytes[0], bytes[1]);
1879 encoder_type = DRM_MODE_ENCODER_NONE; 1919 encoder_type = DRM_MODE_ENCODER_NONE;
1880 connector_type = DRM_MODE_CONNECTOR_Unknown; 1920 connector_type = DRM_MODE_CONNECTOR_Unknown;
1881 goto err_i2c; 1921 goto err_i2c;
@@ -1905,21 +1945,21 @@ bool intel_sdvo_init(struct drm_device *dev, int output_device)
1905 &sdvo_priv->pixel_clock_max); 1945 &sdvo_priv->pixel_clock_max);
1906 1946
1907 1947
1908 DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, " 1948 DRM_DEBUG_KMS(I915_SDVO, "%s device VID/DID: %02X:%02X.%02X, "
1909 "clock range %dMHz - %dMHz, " 1949 "clock range %dMHz - %dMHz, "
1910 "input 1: %c, input 2: %c, " 1950 "input 1: %c, input 2: %c, "
1911 "output 1: %c, output 2: %c\n", 1951 "output 1: %c, output 2: %c\n",
1912 SDVO_NAME(sdvo_priv), 1952 SDVO_NAME(sdvo_priv),
1913 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id, 1953 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
1914 sdvo_priv->caps.device_rev_id, 1954 sdvo_priv->caps.device_rev_id,
1915 sdvo_priv->pixel_clock_min / 1000, 1955 sdvo_priv->pixel_clock_min / 1000,
1916 sdvo_priv->pixel_clock_max / 1000, 1956 sdvo_priv->pixel_clock_max / 1000,
1917 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 1957 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
1918 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 1958 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
1919 /* check currently supported outputs */ 1959 /* check currently supported outputs */
1920 sdvo_priv->caps.output_flags & 1960 sdvo_priv->caps.output_flags &
1921 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 1961 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
1922 sdvo_priv->caps.output_flags & 1962 sdvo_priv->caps.output_flags &
1923 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 1963 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
1924 1964
1925 return true; 1965 return true;
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 98ac0546b7bd..50d7ed70b338 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1392,6 +1392,9 @@ intel_tv_detect_type (struct drm_crtc *crtc, struct intel_output *intel_output)
1392 tv_ctl &= ~TV_TEST_MODE_MASK; 1392 tv_ctl &= ~TV_TEST_MODE_MASK;
1393 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT; 1393 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
1394 tv_dac &= ~TVDAC_SENSE_MASK; 1394 tv_dac &= ~TVDAC_SENSE_MASK;
1395 tv_dac &= ~DAC_A_MASK;
1396 tv_dac &= ~DAC_B_MASK;
1397 tv_dac &= ~DAC_C_MASK;
1395 tv_dac |= (TVDAC_STATE_CHG_EN | 1398 tv_dac |= (TVDAC_STATE_CHG_EN |
1396 TVDAC_A_SENSE_CTL | 1399 TVDAC_A_SENSE_CTL |
1397 TVDAC_B_SENSE_CTL | 1400 TVDAC_B_SENSE_CTL |
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index bc9d09dfa8e7..146f3570af8e 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -478,26 +478,27 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
478 478
479 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) { 479 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) {
480 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 480 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
481 DRM_INFO("Loading RV770 PFP Microcode\n"); 481 DRM_INFO("Loading RV770/RV790 PFP Microcode\n");
482 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 482 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
483 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]); 483 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]);
484 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 484 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
485 485
486 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 486 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
487 DRM_INFO("Loading RV770 CP Microcode\n"); 487 DRM_INFO("Loading RV770/RV790 CP Microcode\n");
488 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 488 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
489 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]); 489 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]);
490 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 490 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
491 491
492 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730)) { 492 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) ||
493 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) {
493 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 494 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
494 DRM_INFO("Loading RV730 PFP Microcode\n"); 495 DRM_INFO("Loading RV730/RV740 PFP Microcode\n");
495 for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 496 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
496 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]); 497 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]);
497 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 498 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
498 499
499 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 500 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
500 DRM_INFO("Loading RV730 CP Microcode\n"); 501 DRM_INFO("Loading RV730/RV740 CP Microcode\n");
501 for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 502 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
502 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]); 503 RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]);
503 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 504 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
@@ -1324,6 +1325,10 @@ static void r700_gfx_init(struct drm_device *dev,
1324 dev_priv->r700_sc_prim_fifo_size = 0xf9; 1325 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1325 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1326 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1326 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1327 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1328 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1329 dev_priv->r600_sx_max_export_pos_size -= 16;
1330 dev_priv->r600_sx_max_export_smx_size += 16;
1331 }
1327 break; 1332 break;
1328 case CHIP_RV710: 1333 case CHIP_RV710:
1329 dev_priv->r600_max_pipes = 2; 1334 dev_priv->r600_max_pipes = 2;
@@ -1345,6 +1350,31 @@ static void r700_gfx_init(struct drm_device *dev,
1345 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1350 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1346 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1351 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1347 break; 1352 break;
1353 case CHIP_RV740:
1354 dev_priv->r600_max_pipes = 4;
1355 dev_priv->r600_max_tile_pipes = 4;
1356 dev_priv->r600_max_simds = 8;
1357 dev_priv->r600_max_backends = 4;
1358 dev_priv->r600_max_gprs = 256;
1359 dev_priv->r600_max_threads = 248;
1360 dev_priv->r600_max_stack_entries = 512;
1361 dev_priv->r600_max_hw_contexts = 8;
1362 dev_priv->r600_max_gs_threads = 16 * 2;
1363 dev_priv->r600_sx_max_export_size = 256;
1364 dev_priv->r600_sx_max_export_pos_size = 32;
1365 dev_priv->r600_sx_max_export_smx_size = 224;
1366 dev_priv->r600_sq_num_cf_insts = 2;
1367
1368 dev_priv->r700_sx_num_of_sets = 7;
1369 dev_priv->r700_sc_prim_fifo_size = 0x100;
1370 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1371 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1372
1373 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1374 dev_priv->r600_sx_max_export_pos_size -= 16;
1375 dev_priv->r600_sx_max_export_smx_size += 16;
1376 }
1377 break;
1348 default: 1378 default:
1349 break; 1379 break;
1350 } 1380 }
@@ -1493,6 +1523,7 @@ static void r700_gfx_init(struct drm_device *dev,
1493 break; 1523 break;
1494 case CHIP_RV730: 1524 case CHIP_RV730:
1495 case CHIP_RV710: 1525 case CHIP_RV710:
1526 case CHIP_RV740:
1496 default: 1527 default:
1497 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); 1528 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1498 break; 1529 break;
@@ -1569,6 +1600,7 @@ static void r700_gfx_init(struct drm_device *dev,
1569 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1600 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1570 case CHIP_RV770: 1601 case CHIP_RV770:
1571 case CHIP_RV730: 1602 case CHIP_RV730:
1603 case CHIP_RV740:
1572 gs_prim_buffer_depth = 384; 1604 gs_prim_buffer_depth = 384;
1573 break; 1605 break;
1574 case CHIP_RV710: 1606 case CHIP_RV710:
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index aff90bb96488..89c4c44169f7 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -2109,7 +2109,7 @@ int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2109 2109
2110 /* prebuild the SAREA */ 2110 /* prebuild the SAREA */
2111 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE); 2111 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2112 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER, 2112 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2113 &master_priv->sarea); 2113 &master_priv->sarea);
2114 if (ret) { 2114 if (ret) {
2115 DRM_ERROR("SAREA setup failed\n"); 2115 DRM_ERROR("SAREA setup failed\n");
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 0c6bfc1de153..127d0456f628 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -146,6 +146,7 @@ enum radeon_family {
146 CHIP_RV770, 146 CHIP_RV770,
147 CHIP_RV730, 147 CHIP_RV730,
148 CHIP_RV710, 148 CHIP_RV710,
149 CHIP_RV740,
149 CHIP_LAST, 150 CHIP_LAST,
150}; 151};
151 152
diff --git a/drivers/gpu/drm/via/via_dmablit.c b/drivers/gpu/drm/via/via_dmablit.c
index 409e00afdd07..327380888b4a 100644
--- a/drivers/gpu/drm/via/via_dmablit.c
+++ b/drivers/gpu/drm/via/via_dmablit.c
@@ -195,10 +195,8 @@ via_free_sg_info(struct pci_dev *pdev, drm_via_sg_info_t *vsg)
195 default: 195 default:
196 vsg->state = dr_via_sg_init; 196 vsg->state = dr_via_sg_init;
197 } 197 }
198 if (vsg->bounce_buffer) { 198 vfree(vsg->bounce_buffer);
199 vfree(vsg->bounce_buffer); 199 vsg->bounce_buffer = NULL;
200 vsg->bounce_buffer = NULL;
201 }
202 vsg->free_on_sequence = 0; 200 vsg->free_on_sequence = 0;
203} 201}
204 202
diff --git a/drivers/pnp/resource.c b/drivers/pnp/resource.c
index f604061d2bb0..ba9765427886 100644
--- a/drivers/pnp/resource.c
+++ b/drivers/pnp/resource.c
@@ -638,6 +638,24 @@ int pnp_possible_config(struct pnp_dev *dev, int type, resource_size_t start,
638} 638}
639EXPORT_SYMBOL(pnp_possible_config); 639EXPORT_SYMBOL(pnp_possible_config);
640 640
641int pnp_range_reserved(resource_size_t start, resource_size_t end)
642{
643 struct pnp_dev *dev;
644 struct pnp_resource *pnp_res;
645 resource_size_t *dev_start, *dev_end;
646
647 pnp_for_each_dev(dev) {
648 list_for_each_entry(pnp_res, &dev->resources, list) {
649 dev_start = &pnp_res->res.start;
650 dev_end = &pnp_res->res.end;
651 if (ranged_conflict(&start, &end, dev_start, dev_end))
652 return 1;
653 }
654 }
655 return 0;
656}
657EXPORT_SYMBOL(pnp_range_reserved);
658
641/* format is: pnp_reserve_irq=irq1[,irq2] .... */ 659/* format is: pnp_reserve_irq=irq1[,irq2] .... */
642static int __init pnp_setup_reserve_irq(char *str) 660static int __init pnp_setup_reserve_irq(char *str)
643{ 661{
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 23:14:07 -0500