diff options
author | David S. Miller <davem@davemloft.net> | 2008-07-06 02:08:07 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-07-06 02:08:07 -0400 |
commit | ea2aca084ba82aaf7c148d04914ceed8758ce08a (patch) | |
tree | dcb3f4f849cf48deac2dd3bafd5c2cd2f0e7dc79 /drivers | |
parent | f3032be921cd126615ce3bfd7084e3d319f3f892 (diff) | |
parent | c5a78ac00c400df29645e59938700301efb371d0 (diff) |
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts:
Documentation/feature-removal-schedule.txt
drivers/net/wan/hdlc_fr.c
drivers/net/wireless/iwlwifi/iwl-4965.c
drivers/net/wireless/iwlwifi/iwl3945-base.c
Diffstat (limited to 'drivers')
169 files changed, 11280 insertions, 2382 deletions
diff --git a/drivers/acpi/ac.c b/drivers/acpi/ac.c index 5b73f6a2cd86..831883b7d6c9 100644 --- a/drivers/acpi/ac.c +++ b/drivers/acpi/ac.c | |||
@@ -233,6 +233,9 @@ static void acpi_ac_notify(acpi_handle handle, u32 event, void *data) | |||
233 | 233 | ||
234 | device = ac->device; | 234 | device = ac->device; |
235 | switch (event) { | 235 | switch (event) { |
236 | default: | ||
237 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | ||
238 | "Unsupported event [0x%x]\n", event)); | ||
236 | case ACPI_AC_NOTIFY_STATUS: | 239 | case ACPI_AC_NOTIFY_STATUS: |
237 | case ACPI_NOTIFY_BUS_CHECK: | 240 | case ACPI_NOTIFY_BUS_CHECK: |
238 | case ACPI_NOTIFY_DEVICE_CHECK: | 241 | case ACPI_NOTIFY_DEVICE_CHECK: |
@@ -244,11 +247,6 @@ static void acpi_ac_notify(acpi_handle handle, u32 event, void *data) | |||
244 | #ifdef CONFIG_ACPI_SYSFS_POWER | 247 | #ifdef CONFIG_ACPI_SYSFS_POWER |
245 | kobject_uevent(&ac->charger.dev->kobj, KOBJ_CHANGE); | 248 | kobject_uevent(&ac->charger.dev->kobj, KOBJ_CHANGE); |
246 | #endif | 249 | #endif |
247 | break; | ||
248 | default: | ||
249 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | ||
250 | "Unsupported event [0x%x]\n", event)); | ||
251 | break; | ||
252 | } | 250 | } |
253 | 251 | ||
254 | return; | 252 | return; |
diff --git a/drivers/acpi/bay.c b/drivers/acpi/bay.c index 26038c2a2a71..61b6c5beb2d3 100644 --- a/drivers/acpi/bay.c +++ b/drivers/acpi/bay.c | |||
@@ -377,6 +377,9 @@ static int __init bay_init(void) | |||
377 | 377 | ||
378 | INIT_LIST_HEAD(&drive_bays); | 378 | INIT_LIST_HEAD(&drive_bays); |
379 | 379 | ||
380 | if (acpi_disabled) | ||
381 | return -ENODEV; | ||
382 | |||
380 | /* look for dockable drive bays */ | 383 | /* look for dockable drive bays */ |
381 | acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, | 384 | acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, |
382 | ACPI_UINT32_MAX, find_bay, &bays, NULL); | 385 | ACPI_UINT32_MAX, find_bay, &bays, NULL); |
diff --git a/drivers/acpi/dock.c b/drivers/acpi/dock.c index 96c542f7fded..bb7c51f712bd 100644 --- a/drivers/acpi/dock.c +++ b/drivers/acpi/dock.c | |||
@@ -917,6 +917,9 @@ static int __init dock_init(void) | |||
917 | 917 | ||
918 | dock_station = NULL; | 918 | dock_station = NULL; |
919 | 919 | ||
920 | if (acpi_disabled) | ||
921 | return 0; | ||
922 | |||
920 | /* look for a dock station */ | 923 | /* look for a dock station */ |
921 | acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, | 924 | acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, |
922 | ACPI_UINT32_MAX, find_dock, &num, NULL); | 925 | ACPI_UINT32_MAX, find_dock, &num, NULL); |
diff --git a/drivers/acpi/glue.c b/drivers/acpi/glue.c index 2808dc60fd67..9b227d4dc9c9 100644 --- a/drivers/acpi/glue.c +++ b/drivers/acpi/glue.c | |||
@@ -333,6 +333,9 @@ static int __init acpi_rtc_init(void) | |||
333 | { | 333 | { |
334 | struct device *dev = get_rtc_dev(); | 334 | struct device *dev = get_rtc_dev(); |
335 | 335 | ||
336 | if (acpi_disabled) | ||
337 | return 0; | ||
338 | |||
336 | if (dev) { | 339 | if (dev) { |
337 | rtc_wake_setup(); | 340 | rtc_wake_setup(); |
338 | rtc_info.wake_on = rtc_wake_on; | 341 | rtc_info.wake_on = rtc_wake_on; |
diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c index 5e5dda3a3027..d089c4519d45 100644 --- a/drivers/acpi/video.c +++ b/drivers/acpi/video.c | |||
@@ -1713,7 +1713,8 @@ acpi_video_bus_get_devices(struct acpi_video_bus *video, | |||
1713 | 1713 | ||
1714 | status = acpi_video_bus_get_one_device(dev, video); | 1714 | status = acpi_video_bus_get_one_device(dev, video); |
1715 | if (ACPI_FAILURE(status)) { | 1715 | if (ACPI_FAILURE(status)) { |
1716 | ACPI_EXCEPTION((AE_INFO, status, "Cant attach device")); | 1716 | ACPI_DEBUG_PRINT((ACPI_DB_WARN, |
1717 | "Cant attach device")); | ||
1717 | continue; | 1718 | continue; |
1718 | } | 1719 | } |
1719 | } | 1720 | } |
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 9bf2986a2788..ae8494944c45 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig | |||
@@ -651,9 +651,17 @@ config PATA_WINBOND_VLB | |||
651 | Support for the Winbond W83759A controller on Vesa Local Bus | 651 | Support for the Winbond W83759A controller on Vesa Local Bus |
652 | systems. | 652 | systems. |
653 | 653 | ||
654 | config HAVE_PATA_PLATFORM | ||
655 | bool | ||
656 | help | ||
657 | This is an internal configuration node for any machine that | ||
658 | uses pata-platform driver to enable the relevant driver in the | ||
659 | configuration structure without having to submit endless patches | ||
660 | to update the PATA_PLATFORM entry. | ||
661 | |||
654 | config PATA_PLATFORM | 662 | config PATA_PLATFORM |
655 | tristate "Generic platform device PATA support" | 663 | tristate "Generic platform device PATA support" |
656 | depends on EMBEDDED || ARCH_RPC || PPC | 664 | depends on EMBEDDED || ARCH_RPC || PPC || HAVE_PATA_PLATFORM |
657 | help | 665 | help |
658 | This option enables support for generic directly connected ATA | 666 | This option enables support for generic directly connected ATA |
659 | devices commonly found on embedded systems. | 667 | devices commonly found on embedded systems. |
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 966ab401e523..6a4a2a25d97a 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c | |||
@@ -90,6 +90,7 @@ enum { | |||
90 | board_ahci_mv = 4, | 90 | board_ahci_mv = 4, |
91 | board_ahci_sb700 = 5, | 91 | board_ahci_sb700 = 5, |
92 | board_ahci_mcp65 = 6, | 92 | board_ahci_mcp65 = 6, |
93 | board_ahci_nopmp = 7, | ||
93 | 94 | ||
94 | /* global controller registers */ | 95 | /* global controller registers */ |
95 | HOST_CAP = 0x00, /* host capabilities */ | 96 | HOST_CAP = 0x00, /* host capabilities */ |
@@ -401,6 +402,14 @@ static const struct ata_port_info ahci_port_info[] = { | |||
401 | .udma_mask = ATA_UDMA6, | 402 | .udma_mask = ATA_UDMA6, |
402 | .port_ops = &ahci_ops, | 403 | .port_ops = &ahci_ops, |
403 | }, | 404 | }, |
405 | /* board_ahci_nopmp */ | ||
406 | { | ||
407 | AHCI_HFLAGS (AHCI_HFLAG_NO_PMP), | ||
408 | .flags = AHCI_FLAG_COMMON, | ||
409 | .pio_mask = 0x1f, /* pio0-4 */ | ||
410 | .udma_mask = ATA_UDMA6, | ||
411 | .port_ops = &ahci_ops, | ||
412 | }, | ||
404 | }; | 413 | }; |
405 | 414 | ||
406 | static const struct pci_device_id ahci_pci_tbl[] = { | 415 | static const struct pci_device_id ahci_pci_tbl[] = { |
@@ -525,9 +534,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { | |||
525 | { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */ | 534 | { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */ |
526 | 535 | ||
527 | /* SiS */ | 536 | /* SiS */ |
528 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ | 537 | { PCI_VDEVICE(SI, 0x1184), board_ahci_nopmp }, /* SiS 966 */ |
529 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ | 538 | { PCI_VDEVICE(SI, 0x1185), board_ahci_nopmp }, /* SiS 968 */ |
530 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | 539 | { PCI_VDEVICE(SI, 0x0186), board_ahci_nopmp }, /* SiS 968 */ |
531 | 540 | ||
532 | /* Marvell */ | 541 | /* Marvell */ |
533 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ | 542 | { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */ |
@@ -653,6 +662,14 @@ static void ahci_save_initial_config(struct pci_dev *pdev, | |||
653 | cap &= ~HOST_CAP_PMP; | 662 | cap &= ~HOST_CAP_PMP; |
654 | } | 663 | } |
655 | 664 | ||
665 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 && | ||
666 | port_map != 1) { | ||
667 | dev_printk(KERN_INFO, &pdev->dev, | ||
668 | "JMB361 has only one port, port_map 0x%x -> 0x%x\n", | ||
669 | port_map, 1); | ||
670 | port_map = 1; | ||
671 | } | ||
672 | |||
656 | /* | 673 | /* |
657 | * Temporary Marvell 6145 hack: PATA port presence | 674 | * Temporary Marvell 6145 hack: PATA port presence |
658 | * is asserted through the standard AHCI port | 675 | * is asserted through the standard AHCI port |
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c index 81b7ae376951..a90ae03f56b2 100644 --- a/drivers/ata/ata_piix.c +++ b/drivers/ata/ata_piix.c | |||
@@ -1043,6 +1043,13 @@ static int piix_broken_suspend(void) | |||
1043 | }, | 1043 | }, |
1044 | }, | 1044 | }, |
1045 | { | 1045 | { |
1046 | .ident = "TECRA M4", | ||
1047 | .matches = { | ||
1048 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | ||
1049 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), | ||
1050 | }, | ||
1051 | }, | ||
1052 | { | ||
1046 | .ident = "TECRA M5", | 1053 | .ident = "TECRA M5", |
1047 | .matches = { | 1054 | .matches = { |
1048 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | 1055 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index cc816ca623d3..303fc0d2b978 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c | |||
@@ -4297,7 +4297,7 @@ void ata_sg_clean(struct ata_queued_cmd *qc) | |||
4297 | } | 4297 | } |
4298 | 4298 | ||
4299 | /** | 4299 | /** |
4300 | * ata_check_atapi_dma - Check whether ATAPI DMA can be supported | 4300 | * atapi_check_dma - Check whether ATAPI DMA can be supported |
4301 | * @qc: Metadata associated with taskfile to check | 4301 | * @qc: Metadata associated with taskfile to check |
4302 | * | 4302 | * |
4303 | * Allow low-level driver to filter ATA PACKET commands, returning | 4303 | * Allow low-level driver to filter ATA PACKET commands, returning |
@@ -4310,7 +4310,7 @@ void ata_sg_clean(struct ata_queued_cmd *qc) | |||
4310 | * RETURNS: 0 when ATAPI DMA can be used | 4310 | * RETURNS: 0 when ATAPI DMA can be used |
4311 | * nonzero otherwise | 4311 | * nonzero otherwise |
4312 | */ | 4312 | */ |
4313 | int ata_check_atapi_dma(struct ata_queued_cmd *qc) | 4313 | int atapi_check_dma(struct ata_queued_cmd *qc) |
4314 | { | 4314 | { |
4315 | struct ata_port *ap = qc->ap; | 4315 | struct ata_port *ap = qc->ap; |
4316 | 4316 | ||
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index 2e6e1622dc6d..57a43649a461 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c | |||
@@ -2343,8 +2343,8 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc) | |||
2343 | { | 2343 | { |
2344 | struct scsi_cmnd *scmd = qc->scsicmd; | 2344 | struct scsi_cmnd *scmd = qc->scsicmd; |
2345 | struct ata_device *dev = qc->dev; | 2345 | struct ata_device *dev = qc->dev; |
2346 | int using_pio = (dev->flags & ATA_DFLAG_PIO); | ||
2347 | int nodata = (scmd->sc_data_direction == DMA_NONE); | 2346 | int nodata = (scmd->sc_data_direction == DMA_NONE); |
2347 | int using_pio = !nodata && (dev->flags & ATA_DFLAG_PIO); | ||
2348 | unsigned int nbytes; | 2348 | unsigned int nbytes; |
2349 | 2349 | ||
2350 | memset(qc->cdb, 0, dev->cdb_len); | 2350 | memset(qc->cdb, 0, dev->cdb_len); |
@@ -2362,7 +2362,7 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc) | |||
2362 | ata_qc_set_pc_nbytes(qc); | 2362 | ata_qc_set_pc_nbytes(qc); |
2363 | 2363 | ||
2364 | /* check whether ATAPI DMA is safe */ | 2364 | /* check whether ATAPI DMA is safe */ |
2365 | if (!using_pio && ata_check_atapi_dma(qc)) | 2365 | if (!nodata && !using_pio && atapi_check_dma(qc)) |
2366 | using_pio = 1; | 2366 | using_pio = 1; |
2367 | 2367 | ||
2368 | /* Some controller variants snoop this value for Packet | 2368 | /* Some controller variants snoop this value for Packet |
@@ -2402,13 +2402,11 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc) | |||
2402 | qc->tf.lbam = (nbytes & 0xFF); | 2402 | qc->tf.lbam = (nbytes & 0xFF); |
2403 | qc->tf.lbah = (nbytes >> 8); | 2403 | qc->tf.lbah = (nbytes >> 8); |
2404 | 2404 | ||
2405 | if (using_pio || nodata) { | 2405 | if (nodata) |
2406 | /* no data, or PIO data xfer */ | 2406 | qc->tf.protocol = ATAPI_PROT_NODATA; |
2407 | if (nodata) | 2407 | else if (using_pio) |
2408 | qc->tf.protocol = ATAPI_PROT_NODATA; | 2408 | qc->tf.protocol = ATAPI_PROT_PIO; |
2409 | else | 2409 | else { |
2410 | qc->tf.protocol = ATAPI_PROT_PIO; | ||
2411 | } else { | ||
2412 | /* DMA data xfer */ | 2410 | /* DMA data xfer */ |
2413 | qc->tf.protocol = ATAPI_PROT_DMA; | 2411 | qc->tf.protocol = ATAPI_PROT_DMA; |
2414 | qc->tf.feature |= ATAPI_PKT_DMA; | 2412 | qc->tf.feature |= ATAPI_PKT_DMA; |
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h index 4514283937ea..1cf803adbc95 100644 --- a/drivers/ata/libata.h +++ b/drivers/ata/libata.h | |||
@@ -106,7 +106,7 @@ extern void ata_sg_clean(struct ata_queued_cmd *qc); | |||
106 | extern void ata_qc_free(struct ata_queued_cmd *qc); | 106 | extern void ata_qc_free(struct ata_queued_cmd *qc); |
107 | extern void ata_qc_issue(struct ata_queued_cmd *qc); | 107 | extern void ata_qc_issue(struct ata_queued_cmd *qc); |
108 | extern void __ata_qc_complete(struct ata_queued_cmd *qc); | 108 | extern void __ata_qc_complete(struct ata_queued_cmd *qc); |
109 | extern int ata_check_atapi_dma(struct ata_queued_cmd *qc); | 109 | extern int atapi_check_dma(struct ata_queued_cmd *qc); |
110 | extern void swap_buf_le16(u16 *buf, unsigned int buf_words); | 110 | extern void swap_buf_le16(u16 *buf, unsigned int buf_words); |
111 | extern void ata_dev_init(struct ata_device *dev); | 111 | extern void ata_dev_init(struct ata_device *dev); |
112 | extern void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp); | 112 | extern void ata_link_init(struct ata_port *ap, struct ata_link *link, int pmp); |
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c index 3d39f9dfec5a..41b4361bbf6e 100644 --- a/drivers/ata/pata_pcmcia.c +++ b/drivers/ata/pata_pcmcia.c | |||
@@ -414,6 +414,7 @@ static struct pcmcia_device_id pcmcia_devices[] = { | |||
414 | PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149), | 414 | PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149), |
415 | PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674), | 415 | PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674), |
416 | PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b), | 416 | PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b), |
417 | PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF300", 0x7ed2ad87, 0x7e9e78ee), | ||
417 | PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c), | 418 | PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c), |
418 | PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79), | 419 | PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79), |
419 | PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591), | 420 | PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591), |
@@ -424,6 +425,7 @@ static struct pcmcia_device_id pcmcia_devices[] = { | |||
424 | PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6), | 425 | PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6), |
425 | PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003), | 426 | PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003), |
426 | PCMCIA_DEVICE_PROD_ID1("TRANSCEND 512M ", 0xd0909443), | 427 | PCMCIA_DEVICE_PROD_ID1("TRANSCEND 512M ", 0xd0909443), |
428 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF45", 0x709b1bf1, 0xf68b6f32), | ||
427 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1), | 429 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1), |
428 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2), | 430 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2), |
429 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8), | 431 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8), |
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 60391e9a84db..28092bc50146 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c | |||
@@ -1322,6 +1322,9 @@ static int mv_port_start(struct ata_port *ap) | |||
1322 | goto out_port_free_dma_mem; | 1322 | goto out_port_free_dma_mem; |
1323 | memset(pp->crpb, 0, MV_CRPB_Q_SZ); | 1323 | memset(pp->crpb, 0, MV_CRPB_Q_SZ); |
1324 | 1324 | ||
1325 | /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ | ||
1326 | if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) | ||
1327 | ap->flags |= ATA_FLAG_AN; | ||
1325 | /* | 1328 | /* |
1326 | * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. | 1329 | * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. |
1327 | * For later hardware, we need one unique sg_tbl per NCQ tag. | 1330 | * For later hardware, we need one unique sg_tbl per NCQ tag. |
@@ -1592,6 +1595,24 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) | |||
1592 | 1595 | ||
1593 | if ((qc->tf.protocol != ATA_PROT_DMA) && | 1596 | if ((qc->tf.protocol != ATA_PROT_DMA) && |
1594 | (qc->tf.protocol != ATA_PROT_NCQ)) { | 1597 | (qc->tf.protocol != ATA_PROT_NCQ)) { |
1598 | static int limit_warnings = 10; | ||
1599 | /* | ||
1600 | * Errata SATA#16, SATA#24: warn if multiple DRQs expected. | ||
1601 | * | ||
1602 | * Someday, we might implement special polling workarounds | ||
1603 | * for these, but it all seems rather unnecessary since we | ||
1604 | * normally use only DMA for commands which transfer more | ||
1605 | * than a single block of data. | ||
1606 | * | ||
1607 | * Much of the time, this could just work regardless. | ||
1608 | * So for now, just log the incident, and allow the attempt. | ||
1609 | */ | ||
1610 | if (limit_warnings && (qc->nbytes / qc->sect_size) > 1) { | ||
1611 | --limit_warnings; | ||
1612 | ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME | ||
1613 | ": attempting PIO w/multiple DRQ: " | ||
1614 | "this may fail due to h/w errata\n"); | ||
1615 | } | ||
1595 | /* | 1616 | /* |
1596 | * We're about to send a non-EDMA capable command to the | 1617 | * We're about to send a non-EDMA capable command to the |
1597 | * port. Turn off EDMA so there won't be problems accessing | 1618 | * port. Turn off EDMA so there won't be problems accessing |
diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h index 99e6a406efb4..81e14bea54bd 100644 --- a/drivers/char/agp/agp.h +++ b/drivers/char/agp/agp.h | |||
@@ -99,8 +99,8 @@ struct agp_bridge_driver { | |||
99 | const void *aperture_sizes; | 99 | const void *aperture_sizes; |
100 | int num_aperture_sizes; | 100 | int num_aperture_sizes; |
101 | enum aper_size_type size_type; | 101 | enum aper_size_type size_type; |
102 | int cant_use_aperture; | 102 | bool cant_use_aperture; |
103 | int needs_scratch_page; | 103 | bool needs_scratch_page; |
104 | const struct gatt_mask *masks; | 104 | const struct gatt_mask *masks; |
105 | int (*fetch_size)(void); | 105 | int (*fetch_size)(void); |
106 | int (*configure)(void); | 106 | int (*configure)(void); |
@@ -278,7 +278,7 @@ void agp_generic_destroy_page(void *addr, int flags); | |||
278 | void agp_free_key(int key); | 278 | void agp_free_key(int key); |
279 | int agp_num_entries(void); | 279 | int agp_num_entries(void); |
280 | u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command); | 280 | u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command); |
281 | void agp_device_command(u32 command, int agp_v3); | 281 | void agp_device_command(u32 command, bool agp_v3); |
282 | int agp_3_5_enable(struct agp_bridge_data *bridge); | 282 | int agp_3_5_enable(struct agp_bridge_data *bridge); |
283 | void global_cache_flush(void); | 283 | void global_cache_flush(void); |
284 | void get_agp_version(struct agp_bridge_data *bridge); | 284 | void get_agp_version(struct agp_bridge_data *bridge); |
diff --git a/drivers/char/agp/alpha-agp.c b/drivers/char/agp/alpha-agp.c index e77c17838c8a..5da89f6c6c25 100644 --- a/drivers/char/agp/alpha-agp.c +++ b/drivers/char/agp/alpha-agp.c | |||
@@ -80,7 +80,7 @@ static void alpha_core_agp_enable(struct agp_bridge_data *bridge, u32 mode) | |||
80 | agp->mode.bits.enable = 1; | 80 | agp->mode.bits.enable = 1; |
81 | agp->ops->configure(agp); | 81 | agp->ops->configure(agp); |
82 | 82 | ||
83 | agp_device_command(agp->mode.lw, 0); | 83 | agp_device_command(agp->mode.lw, false); |
84 | } | 84 | } |
85 | 85 | ||
86 | static int alpha_core_agp_insert_memory(struct agp_memory *mem, off_t pg_start, | 86 | static int alpha_core_agp_insert_memory(struct agp_memory *mem, off_t pg_start, |
@@ -126,7 +126,7 @@ struct agp_bridge_driver alpha_core_agp_driver = { | |||
126 | .aperture_sizes = alpha_core_agp_sizes, | 126 | .aperture_sizes = alpha_core_agp_sizes, |
127 | .num_aperture_sizes = 1, | 127 | .num_aperture_sizes = 1, |
128 | .size_type = FIXED_APER_SIZE, | 128 | .size_type = FIXED_APER_SIZE, |
129 | .cant_use_aperture = 1, | 129 | .cant_use_aperture = true, |
130 | .masks = NULL, | 130 | .masks = NULL, |
131 | 131 | ||
132 | .fetch_size = alpha_core_agp_fetch_size, | 132 | .fetch_size = alpha_core_agp_fetch_size, |
diff --git a/drivers/char/agp/amd-k7-agp.c b/drivers/char/agp/amd-k7-agp.c index 96bdb9296b07..39a0718bc616 100644 --- a/drivers/char/agp/amd-k7-agp.c +++ b/drivers/char/agp/amd-k7-agp.c | |||
@@ -314,9 +314,9 @@ static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type) | |||
314 | j++; | 314 | j++; |
315 | } | 315 | } |
316 | 316 | ||
317 | if (mem->is_flushed == FALSE) { | 317 | if (!mem->is_flushed) { |
318 | global_cache_flush(); | 318 | global_cache_flush(); |
319 | mem->is_flushed = TRUE; | 319 | mem->is_flushed = true; |
320 | } | 320 | } |
321 | 321 | ||
322 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | 322 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { |
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c index d8200ac8f8cb..13665db363d6 100644 --- a/drivers/char/agp/amd64-agp.c +++ b/drivers/char/agp/amd64-agp.c | |||
@@ -90,9 +90,9 @@ static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type) | |||
90 | j++; | 90 | j++; |
91 | } | 91 | } |
92 | 92 | ||
93 | if (mem->is_flushed == FALSE) { | 93 | if (!mem->is_flushed) { |
94 | global_cache_flush(); | 94 | global_cache_flush(); |
95 | mem->is_flushed = TRUE; | 95 | mem->is_flushed = true; |
96 | } | 96 | } |
97 | 97 | ||
98 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | 98 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { |
diff --git a/drivers/char/agp/ati-agp.c b/drivers/char/agp/ati-agp.c index 07b4d8ff56e5..3a4566c0d84f 100644 --- a/drivers/char/agp/ati-agp.c +++ b/drivers/char/agp/ati-agp.c | |||
@@ -287,10 +287,10 @@ static int ati_insert_memory(struct agp_memory * mem, | |||
287 | j++; | 287 | j++; |
288 | } | 288 | } |
289 | 289 | ||
290 | if (mem->is_flushed == FALSE) { | 290 | if (!mem->is_flushed) { |
291 | /*CACHE_FLUSH(); */ | 291 | /*CACHE_FLUSH(); */ |
292 | global_cache_flush(); | 292 | global_cache_flush(); |
293 | mem->is_flushed = TRUE; | 293 | mem->is_flushed = true; |
294 | } | 294 | } |
295 | 295 | ||
296 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | 296 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { |
diff --git a/drivers/char/agp/backend.c b/drivers/char/agp/backend.c index b1bdd015165c..1ec87104e68c 100644 --- a/drivers/char/agp/backend.c +++ b/drivers/char/agp/backend.c | |||
@@ -188,10 +188,10 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge) | |||
188 | 188 | ||
189 | err_out: | 189 | err_out: |
190 | if (bridge->driver->needs_scratch_page) { | 190 | if (bridge->driver->needs_scratch_page) { |
191 | bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), | 191 | void *va = gart_to_virt(bridge->scratch_page_real); |
192 | AGP_PAGE_DESTROY_UNMAP); | 192 | |
193 | bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), | 193 | bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP); |
194 | AGP_PAGE_DESTROY_FREE); | 194 | bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE); |
195 | } | 195 | } |
196 | if (got_gatt) | 196 | if (got_gatt) |
197 | bridge->driver->free_gatt_table(bridge); | 197 | bridge->driver->free_gatt_table(bridge); |
@@ -215,10 +215,10 @@ static void agp_backend_cleanup(struct agp_bridge_data *bridge) | |||
215 | 215 | ||
216 | if (bridge->driver->agp_destroy_page && | 216 | if (bridge->driver->agp_destroy_page && |
217 | bridge->driver->needs_scratch_page) { | 217 | bridge->driver->needs_scratch_page) { |
218 | bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), | 218 | void *va = gart_to_virt(bridge->scratch_page_real); |
219 | AGP_PAGE_DESTROY_UNMAP); | 219 | |
220 | bridge->driver->agp_destroy_page(gart_to_virt(bridge->scratch_page_real), | 220 | bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP); |
221 | AGP_PAGE_DESTROY_FREE); | 221 | bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE); |
222 | } | 222 | } |
223 | } | 223 | } |
224 | 224 | ||
diff --git a/drivers/char/agp/compat_ioctl.c b/drivers/char/agp/compat_ioctl.c index 39275794fe63..58c57cb2518c 100644 --- a/drivers/char/agp/compat_ioctl.c +++ b/drivers/char/agp/compat_ioctl.c | |||
@@ -214,7 +214,7 @@ long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |||
214 | ret_val = -EINVAL; | 214 | ret_val = -EINVAL; |
215 | goto ioctl_out; | 215 | goto ioctl_out; |
216 | } | 216 | } |
217 | if ((agp_fe.backend_acquired != TRUE) && | 217 | if ((agp_fe.backend_acquired != true) && |
218 | (cmd != AGPIOC_ACQUIRE32)) { | 218 | (cmd != AGPIOC_ACQUIRE32)) { |
219 | ret_val = -EBUSY; | 219 | ret_val = -EBUSY; |
220 | goto ioctl_out; | 220 | goto ioctl_out; |
diff --git a/drivers/char/agp/efficeon-agp.c b/drivers/char/agp/efficeon-agp.c index cac0009cebc1..8ca6f262ef85 100644 --- a/drivers/char/agp/efficeon-agp.c +++ b/drivers/char/agp/efficeon-agp.c | |||
@@ -249,9 +249,9 @@ static int efficeon_insert_memory(struct agp_memory * mem, off_t pg_start, int t | |||
249 | if (type != 0 || mem->type != 0) | 249 | if (type != 0 || mem->type != 0) |
250 | return -EINVAL; | 250 | return -EINVAL; |
251 | 251 | ||
252 | if (mem->is_flushed == FALSE) { | 252 | if (!mem->is_flushed) { |
253 | global_cache_flush(); | 253 | global_cache_flush(); |
254 | mem->is_flushed = TRUE; | 254 | mem->is_flushed = true; |
255 | } | 255 | } |
256 | 256 | ||
257 | last_page = NULL; | 257 | last_page = NULL; |
@@ -329,7 +329,7 @@ static const struct agp_bridge_driver efficeon_driver = { | |||
329 | .free_gatt_table = efficeon_free_gatt_table, | 329 | .free_gatt_table = efficeon_free_gatt_table, |
330 | .insert_memory = efficeon_insert_memory, | 330 | .insert_memory = efficeon_insert_memory, |
331 | .remove_memory = efficeon_remove_memory, | 331 | .remove_memory = efficeon_remove_memory, |
332 | .cant_use_aperture = 0, // 1 might be faster? | 332 | .cant_use_aperture = false, // true might be faster? |
333 | 333 | ||
334 | // Generic | 334 | // Generic |
335 | .alloc_by_type = agp_generic_alloc_by_type, | 335 | .alloc_by_type = agp_generic_alloc_by_type, |
diff --git a/drivers/char/agp/frontend.c b/drivers/char/agp/frontend.c index 857b26227d87..e6cb1ab03e06 100644 --- a/drivers/char/agp/frontend.c +++ b/drivers/char/agp/frontend.c | |||
@@ -395,7 +395,7 @@ static int agp_remove_controller(struct agp_controller *controller) | |||
395 | 395 | ||
396 | if (agp_fe.current_controller == controller) { | 396 | if (agp_fe.current_controller == controller) { |
397 | agp_fe.current_controller = NULL; | 397 | agp_fe.current_controller = NULL; |
398 | agp_fe.backend_acquired = FALSE; | 398 | agp_fe.backend_acquired = false; |
399 | agp_backend_release(agp_bridge); | 399 | agp_backend_release(agp_bridge); |
400 | } | 400 | } |
401 | kfree(controller); | 401 | kfree(controller); |
@@ -443,7 +443,7 @@ static void agp_controller_release_current(struct agp_controller *controller, | |||
443 | } | 443 | } |
444 | 444 | ||
445 | agp_fe.current_controller = NULL; | 445 | agp_fe.current_controller = NULL; |
446 | agp_fe.used_by_controller = FALSE; | 446 | agp_fe.used_by_controller = false; |
447 | agp_backend_release(agp_bridge); | 447 | agp_backend_release(agp_bridge); |
448 | } | 448 | } |
449 | 449 | ||
@@ -573,7 +573,7 @@ static int agp_mmap(struct file *file, struct vm_area_struct *vma) | |||
573 | 573 | ||
574 | mutex_lock(&(agp_fe.agp_mutex)); | 574 | mutex_lock(&(agp_fe.agp_mutex)); |
575 | 575 | ||
576 | if (agp_fe.backend_acquired != TRUE) | 576 | if (agp_fe.backend_acquired != true) |
577 | goto out_eperm; | 577 | goto out_eperm; |
578 | 578 | ||
579 | if (!(test_bit(AGP_FF_IS_VALID, &priv->access_flags))) | 579 | if (!(test_bit(AGP_FF_IS_VALID, &priv->access_flags))) |
@@ -768,7 +768,7 @@ int agpioc_acquire_wrap(struct agp_file_private *priv) | |||
768 | 768 | ||
769 | atomic_inc(&agp_bridge->agp_in_use); | 769 | atomic_inc(&agp_bridge->agp_in_use); |
770 | 770 | ||
771 | agp_fe.backend_acquired = TRUE; | 771 | agp_fe.backend_acquired = true; |
772 | 772 | ||
773 | controller = agp_find_controller_by_pid(priv->my_pid); | 773 | controller = agp_find_controller_by_pid(priv->my_pid); |
774 | 774 | ||
@@ -778,7 +778,7 @@ int agpioc_acquire_wrap(struct agp_file_private *priv) | |||
778 | controller = agp_create_controller(priv->my_pid); | 778 | controller = agp_create_controller(priv->my_pid); |
779 | 779 | ||
780 | if (controller == NULL) { | 780 | if (controller == NULL) { |
781 | agp_fe.backend_acquired = FALSE; | 781 | agp_fe.backend_acquired = false; |
782 | agp_backend_release(agp_bridge); | 782 | agp_backend_release(agp_bridge); |
783 | return -ENOMEM; | 783 | return -ENOMEM; |
784 | } | 784 | } |
@@ -981,7 +981,7 @@ static long agp_ioctl(struct file *file, | |||
981 | ret_val = -EINVAL; | 981 | ret_val = -EINVAL; |
982 | goto ioctl_out; | 982 | goto ioctl_out; |
983 | } | 983 | } |
984 | if ((agp_fe.backend_acquired != TRUE) && | 984 | if ((agp_fe.backend_acquired != true) && |
985 | (cmd != AGPIOC_ACQUIRE)) { | 985 | (cmd != AGPIOC_ACQUIRE)) { |
986 | ret_val = -EBUSY; | 986 | ret_val = -EBUSY; |
987 | goto ioctl_out; | 987 | goto ioctl_out; |
diff --git a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c index 7fc0c99a3a58..564daaa6c7d0 100644 --- a/drivers/char/agp/generic.c +++ b/drivers/char/agp/generic.c | |||
@@ -96,13 +96,13 @@ EXPORT_SYMBOL(agp_flush_chipset); | |||
96 | void agp_alloc_page_array(size_t size, struct agp_memory *mem) | 96 | void agp_alloc_page_array(size_t size, struct agp_memory *mem) |
97 | { | 97 | { |
98 | mem->memory = NULL; | 98 | mem->memory = NULL; |
99 | mem->vmalloc_flag = 0; | 99 | mem->vmalloc_flag = false; |
100 | 100 | ||
101 | if (size <= 2*PAGE_SIZE) | 101 | if (size <= 2*PAGE_SIZE) |
102 | mem->memory = kmalloc(size, GFP_KERNEL | __GFP_NORETRY); | 102 | mem->memory = kmalloc(size, GFP_KERNEL | __GFP_NORETRY); |
103 | if (mem->memory == NULL) { | 103 | if (mem->memory == NULL) { |
104 | mem->memory = vmalloc(size); | 104 | mem->memory = vmalloc(size); |
105 | mem->vmalloc_flag = 1; | 105 | mem->vmalloc_flag = true; |
106 | } | 106 | } |
107 | } | 107 | } |
108 | EXPORT_SYMBOL(agp_alloc_page_array); | 108 | EXPORT_SYMBOL(agp_alloc_page_array); |
@@ -188,7 +188,7 @@ void agp_free_memory(struct agp_memory *curr) | |||
188 | if (curr == NULL) | 188 | if (curr == NULL) |
189 | return; | 189 | return; |
190 | 190 | ||
191 | if (curr->is_bound == TRUE) | 191 | if (curr->is_bound) |
192 | agp_unbind_memory(curr); | 192 | agp_unbind_memory(curr); |
193 | 193 | ||
194 | if (curr->type >= AGP_USER_TYPES) { | 194 | if (curr->type >= AGP_USER_TYPES) { |
@@ -202,10 +202,13 @@ void agp_free_memory(struct agp_memory *curr) | |||
202 | } | 202 | } |
203 | if (curr->page_count != 0) { | 203 | if (curr->page_count != 0) { |
204 | for (i = 0; i < curr->page_count; i++) { | 204 | for (i = 0; i < curr->page_count; i++) { |
205 | curr->bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[i]), AGP_PAGE_DESTROY_UNMAP); | 205 | curr->memory[i] = (unsigned long)gart_to_virt(curr->memory[i]); |
206 | curr->bridge->driver->agp_destroy_page((void *)curr->memory[i], | ||
207 | AGP_PAGE_DESTROY_UNMAP); | ||
206 | } | 208 | } |
207 | for (i = 0; i < curr->page_count; i++) { | 209 | for (i = 0; i < curr->page_count; i++) { |
208 | curr->bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[i]), AGP_PAGE_DESTROY_FREE); | 210 | curr->bridge->driver->agp_destroy_page((void *)curr->memory[i], |
211 | AGP_PAGE_DESTROY_FREE); | ||
209 | } | 212 | } |
210 | } | 213 | } |
211 | agp_free_key(curr->key); | 214 | agp_free_key(curr->key); |
@@ -411,20 +414,20 @@ int agp_bind_memory(struct agp_memory *curr, off_t pg_start) | |||
411 | if (curr == NULL) | 414 | if (curr == NULL) |
412 | return -EINVAL; | 415 | return -EINVAL; |
413 | 416 | ||
414 | if (curr->is_bound == TRUE) { | 417 | if (curr->is_bound) { |
415 | printk(KERN_INFO PFX "memory %p is already bound!\n", curr); | 418 | printk(KERN_INFO PFX "memory %p is already bound!\n", curr); |
416 | return -EINVAL; | 419 | return -EINVAL; |
417 | } | 420 | } |
418 | if (curr->is_flushed == FALSE) { | 421 | if (!curr->is_flushed) { |
419 | curr->bridge->driver->cache_flush(); | 422 | curr->bridge->driver->cache_flush(); |
420 | curr->is_flushed = TRUE; | 423 | curr->is_flushed = true; |
421 | } | 424 | } |
422 | ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type); | 425 | ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type); |
423 | 426 | ||
424 | if (ret_val != 0) | 427 | if (ret_val != 0) |
425 | return ret_val; | 428 | return ret_val; |
426 | 429 | ||
427 | curr->is_bound = TRUE; | 430 | curr->is_bound = true; |
428 | curr->pg_start = pg_start; | 431 | curr->pg_start = pg_start; |
429 | return 0; | 432 | return 0; |
430 | } | 433 | } |
@@ -446,7 +449,7 @@ int agp_unbind_memory(struct agp_memory *curr) | |||
446 | if (curr == NULL) | 449 | if (curr == NULL) |
447 | return -EINVAL; | 450 | return -EINVAL; |
448 | 451 | ||
449 | if (curr->is_bound != TRUE) { | 452 | if (!curr->is_bound) { |
450 | printk(KERN_INFO PFX "memory %p was not bound!\n", curr); | 453 | printk(KERN_INFO PFX "memory %p was not bound!\n", curr); |
451 | return -EINVAL; | 454 | return -EINVAL; |
452 | } | 455 | } |
@@ -456,7 +459,7 @@ int agp_unbind_memory(struct agp_memory *curr) | |||
456 | if (ret_val != 0) | 459 | if (ret_val != 0) |
457 | return ret_val; | 460 | return ret_val; |
458 | 461 | ||
459 | curr->is_bound = FALSE; | 462 | curr->is_bound = false; |
460 | curr->pg_start = 0; | 463 | curr->pg_start = 0; |
461 | return 0; | 464 | return 0; |
462 | } | 465 | } |
@@ -754,7 +757,7 @@ u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 requested_mode | |||
754 | EXPORT_SYMBOL(agp_collect_device_status); | 757 | EXPORT_SYMBOL(agp_collect_device_status); |
755 | 758 | ||
756 | 759 | ||
757 | void agp_device_command(u32 bridge_agpstat, int agp_v3) | 760 | void agp_device_command(u32 bridge_agpstat, bool agp_v3) |
758 | { | 761 | { |
759 | struct pci_dev *device = NULL; | 762 | struct pci_dev *device = NULL; |
760 | int mode; | 763 | int mode; |
@@ -818,7 +821,7 @@ void agp_generic_enable(struct agp_bridge_data *bridge, u32 requested_mode) | |||
818 | /* If we have 3.5, we can do the isoch stuff. */ | 821 | /* If we have 3.5, we can do the isoch stuff. */ |
819 | if (bridge->minor_version >= 5) | 822 | if (bridge->minor_version >= 5) |
820 | agp_3_5_enable(bridge); | 823 | agp_3_5_enable(bridge); |
821 | agp_device_command(bridge_agpstat, TRUE); | 824 | agp_device_command(bridge_agpstat, true); |
822 | return; | 825 | return; |
823 | } else { | 826 | } else { |
824 | /* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/ | 827 | /* Disable calibration cycle in RX91<1> when not in AGP3.0 mode of operation.*/ |
@@ -835,7 +838,7 @@ void agp_generic_enable(struct agp_bridge_data *bridge, u32 requested_mode) | |||
835 | } | 838 | } |
836 | 839 | ||
837 | /* AGP v<3 */ | 840 | /* AGP v<3 */ |
838 | agp_device_command(bridge_agpstat, FALSE); | 841 | agp_device_command(bridge_agpstat, false); |
839 | } | 842 | } |
840 | EXPORT_SYMBOL(agp_generic_enable); | 843 | EXPORT_SYMBOL(agp_generic_enable); |
841 | 844 | ||
@@ -1083,9 +1086,9 @@ int agp_generic_insert_memory(struct agp_memory * mem, off_t pg_start, int type) | |||
1083 | j++; | 1086 | j++; |
1084 | } | 1087 | } |
1085 | 1088 | ||
1086 | if (mem->is_flushed == FALSE) { | 1089 | if (!mem->is_flushed) { |
1087 | bridge->driver->cache_flush(); | 1090 | bridge->driver->cache_flush(); |
1088 | mem->is_flushed = TRUE; | 1091 | mem->is_flushed = true; |
1089 | } | 1092 | } |
1090 | 1093 | ||
1091 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | 1094 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { |
diff --git a/drivers/char/agp/hp-agp.c b/drivers/char/agp/hp-agp.c index cbb0444467ba..80d7317f85c9 100644 --- a/drivers/char/agp/hp-agp.c +++ b/drivers/char/agp/hp-agp.c | |||
@@ -353,9 +353,9 @@ hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type) | |||
353 | j++; | 353 | j++; |
354 | } | 354 | } |
355 | 355 | ||
356 | if (mem->is_flushed == FALSE) { | 356 | if (!mem->is_flushed) { |
357 | global_cache_flush(); | 357 | global_cache_flush(); |
358 | mem->is_flushed = TRUE; | 358 | mem->is_flushed = true; |
359 | } | 359 | } |
360 | 360 | ||
361 | for (i = 0, j = io_pg_start; i < mem->page_count; i++) { | 361 | for (i = 0, j = io_pg_start; i < mem->page_count; i++) { |
@@ -437,7 +437,7 @@ const struct agp_bridge_driver hp_zx1_driver = { | |||
437 | .agp_alloc_page = agp_generic_alloc_page, | 437 | .agp_alloc_page = agp_generic_alloc_page, |
438 | .agp_destroy_page = agp_generic_destroy_page, | 438 | .agp_destroy_page = agp_generic_destroy_page, |
439 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, | 439 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
440 | .cant_use_aperture = 1, | 440 | .cant_use_aperture = true, |
441 | }; | 441 | }; |
442 | 442 | ||
443 | static int __init | 443 | static int __init |
diff --git a/drivers/char/agp/i460-agp.c b/drivers/char/agp/i460-agp.c index 76f581c85a7d..e587eebebc67 100644 --- a/drivers/char/agp/i460-agp.c +++ b/drivers/char/agp/i460-agp.c | |||
@@ -580,7 +580,7 @@ const struct agp_bridge_driver intel_i460_driver = { | |||
580 | .alloc_by_type = agp_generic_alloc_by_type, | 580 | .alloc_by_type = agp_generic_alloc_by_type, |
581 | .free_by_type = agp_generic_free_by_type, | 581 | .free_by_type = agp_generic_free_by_type, |
582 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, | 582 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
583 | .cant_use_aperture = 1, | 583 | .cant_use_aperture = true, |
584 | }; | 584 | }; |
585 | 585 | ||
586 | static int __devinit agp_intel_i460_probe(struct pci_dev *pdev, | 586 | static int __devinit agp_intel_i460_probe(struct pci_dev *pdev, |
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index eeea50a1d22a..df702642ab8f 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c | |||
@@ -34,6 +34,12 @@ | |||
34 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 | 34 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 |
35 | #define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40 | 35 | #define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40 |
36 | #define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42 | 36 | #define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42 |
37 | #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 | ||
38 | #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02 | ||
39 | #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 | ||
40 | #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 | ||
41 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 | ||
42 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 | ||
37 | 43 | ||
38 | /* cover 915 and 945 variants */ | 44 | /* cover 915 and 945 variants */ |
39 | #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ | 45 | #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ |
@@ -55,6 +61,10 @@ | |||
55 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ | 61 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ |
56 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB) | 62 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB) |
57 | 63 | ||
64 | #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \ | ||
65 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ | ||
66 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB) | ||
67 | |||
58 | extern int agp_memory_reserved; | 68 | extern int agp_memory_reserved; |
59 | 69 | ||
60 | 70 | ||
@@ -80,8 +90,13 @@ extern int agp_memory_reserved; | |||
80 | #define I915_PTEADDR 0x1C | 90 | #define I915_PTEADDR 0x1C |
81 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | 91 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) |
82 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | 92 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) |
83 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) | 93 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) |
84 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) | 94 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) |
95 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) | ||
96 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) | ||
97 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | ||
98 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | ||
99 | |||
85 | #define I915_IFPADDR 0x60 | 100 | #define I915_IFPADDR 0x60 |
86 | 101 | ||
87 | /* Intel 965G registers */ | 102 | /* Intel 965G registers */ |
@@ -325,7 +340,7 @@ static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, | |||
325 | out: | 340 | out: |
326 | ret = 0; | 341 | ret = 0; |
327 | out_err: | 342 | out_err: |
328 | mem->is_flushed = 1; | 343 | mem->is_flushed = true; |
329 | return ret; | 344 | return ret; |
330 | } | 345 | } |
331 | 346 | ||
@@ -418,9 +433,11 @@ static void intel_i810_free_by_type(struct agp_memory *curr) | |||
418 | if (curr->page_count == 4) | 433 | if (curr->page_count == 4) |
419 | i8xx_destroy_pages(gart_to_virt(curr->memory[0])); | 434 | i8xx_destroy_pages(gart_to_virt(curr->memory[0])); |
420 | else { | 435 | else { |
421 | agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]), | 436 | void *va = gart_to_virt(curr->memory[0]); |
437 | |||
438 | agp_bridge->driver->agp_destroy_page(va, | ||
422 | AGP_PAGE_DESTROY_UNMAP); | 439 | AGP_PAGE_DESTROY_UNMAP); |
423 | agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]), | 440 | agp_bridge->driver->agp_destroy_page(va, |
424 | AGP_PAGE_DESTROY_FREE); | 441 | AGP_PAGE_DESTROY_FREE); |
425 | } | 442 | } |
426 | agp_free_page_array(curr); | 443 | agp_free_page_array(curr); |
@@ -504,6 +521,10 @@ static void intel_i830_init_gtt_entries(void) | |||
504 | size = 512; | 521 | size = 512; |
505 | } | 522 | } |
506 | size += 4; | 523 | size += 4; |
524 | } else if (IS_G4X) { | ||
525 | /* On 4 series hardware, GTT stolen is separate from graphics | ||
526 | * stolen, ignore it in stolen gtt entries counting */ | ||
527 | size = 0; | ||
507 | } else { | 528 | } else { |
508 | /* On previous hardware, the GTT size was just what was | 529 | /* On previous hardware, the GTT size was just what was |
509 | * required to map the aperture. | 530 | * required to map the aperture. |
@@ -552,30 +573,54 @@ static void intel_i830_init_gtt_entries(void) | |||
552 | break; | 573 | break; |
553 | case I915_GMCH_GMS_STOLEN_48M: | 574 | case I915_GMCH_GMS_STOLEN_48M: |
554 | /* Check it's really I915G */ | 575 | /* Check it's really I915G */ |
555 | if (IS_I915 || IS_I965 || IS_G33) | 576 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
556 | gtt_entries = MB(48) - KB(size); | 577 | gtt_entries = MB(48) - KB(size); |
557 | else | 578 | else |
558 | gtt_entries = 0; | 579 | gtt_entries = 0; |
559 | break; | 580 | break; |
560 | case I915_GMCH_GMS_STOLEN_64M: | 581 | case I915_GMCH_GMS_STOLEN_64M: |
561 | /* Check it's really I915G */ | 582 | /* Check it's really I915G */ |
562 | if (IS_I915 || IS_I965 || IS_G33) | 583 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
563 | gtt_entries = MB(64) - KB(size); | 584 | gtt_entries = MB(64) - KB(size); |
564 | else | 585 | else |
565 | gtt_entries = 0; | 586 | gtt_entries = 0; |
566 | break; | 587 | break; |
567 | case G33_GMCH_GMS_STOLEN_128M: | 588 | case G33_GMCH_GMS_STOLEN_128M: |
568 | if (IS_G33) | 589 | if (IS_G33 || IS_I965 || IS_G4X) |
569 | gtt_entries = MB(128) - KB(size); | 590 | gtt_entries = MB(128) - KB(size); |
570 | else | 591 | else |
571 | gtt_entries = 0; | 592 | gtt_entries = 0; |
572 | break; | 593 | break; |
573 | case G33_GMCH_GMS_STOLEN_256M: | 594 | case G33_GMCH_GMS_STOLEN_256M: |
574 | if (IS_G33) | 595 | if (IS_G33 || IS_I965 || IS_G4X) |
575 | gtt_entries = MB(256) - KB(size); | 596 | gtt_entries = MB(256) - KB(size); |
576 | else | 597 | else |
577 | gtt_entries = 0; | 598 | gtt_entries = 0; |
578 | break; | 599 | break; |
600 | case INTEL_GMCH_GMS_STOLEN_96M: | ||
601 | if (IS_I965 || IS_G4X) | ||
602 | gtt_entries = MB(96) - KB(size); | ||
603 | else | ||
604 | gtt_entries = 0; | ||
605 | break; | ||
606 | case INTEL_GMCH_GMS_STOLEN_160M: | ||
607 | if (IS_I965 || IS_G4X) | ||
608 | gtt_entries = MB(160) - KB(size); | ||
609 | else | ||
610 | gtt_entries = 0; | ||
611 | break; | ||
612 | case INTEL_GMCH_GMS_STOLEN_224M: | ||
613 | if (IS_I965 || IS_G4X) | ||
614 | gtt_entries = MB(224) - KB(size); | ||
615 | else | ||
616 | gtt_entries = 0; | ||
617 | break; | ||
618 | case INTEL_GMCH_GMS_STOLEN_352M: | ||
619 | if (IS_I965 || IS_G4X) | ||
620 | gtt_entries = MB(352) - KB(size); | ||
621 | else | ||
622 | gtt_entries = 0; | ||
623 | break; | ||
579 | default: | 624 | default: |
580 | gtt_entries = 0; | 625 | gtt_entries = 0; |
581 | break; | 626 | break; |
@@ -793,7 +838,7 @@ static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, | |||
793 | out: | 838 | out: |
794 | ret = 0; | 839 | ret = 0; |
795 | out_err: | 840 | out_err: |
796 | mem->is_flushed = 1; | 841 | mem->is_flushed = true; |
797 | return ret; | 842 | return ret; |
798 | } | 843 | } |
799 | 844 | ||
@@ -903,7 +948,7 @@ static void intel_i9xx_setup_flush(void) | |||
903 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | 948 | intel_private.ifp_resource.flags = IORESOURCE_MEM; |
904 | 949 | ||
905 | /* Setup chipset flush for 915 */ | 950 | /* Setup chipset flush for 915 */ |
906 | if (IS_I965 || IS_G33) { | 951 | if (IS_I965 || IS_G33 || IS_G4X) { |
907 | intel_i965_g33_setup_chipset_flush(); | 952 | intel_i965_g33_setup_chipset_flush(); |
908 | } else { | 953 | } else { |
909 | intel_i915_setup_chipset_flush(); | 954 | intel_i915_setup_chipset_flush(); |
@@ -1020,7 +1065,7 @@ static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, | |||
1020 | out: | 1065 | out: |
1021 | ret = 0; | 1066 | ret = 0; |
1022 | out_err: | 1067 | out_err: |
1023 | mem->is_flushed = 1; | 1068 | mem->is_flushed = true; |
1024 | return ret; | 1069 | return ret; |
1025 | } | 1070 | } |
1026 | 1071 | ||
@@ -1134,53 +1179,64 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, | |||
1134 | return addr | bridge->driver->masks[type].mask; | 1179 | return addr | bridge->driver->masks[type].mask; |
1135 | } | 1180 | } |
1136 | 1181 | ||
1182 | static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) | ||
1183 | { | ||
1184 | switch (agp_bridge->dev->device) { | ||
1185 | case PCI_DEVICE_ID_INTEL_IGD_HB: | ||
1186 | case PCI_DEVICE_ID_INTEL_IGD_E_HB: | ||
1187 | case PCI_DEVICE_ID_INTEL_Q45_HB: | ||
1188 | case PCI_DEVICE_ID_INTEL_G45_HB: | ||
1189 | *gtt_offset = *gtt_size = MB(2); | ||
1190 | break; | ||
1191 | default: | ||
1192 | *gtt_offset = *gtt_size = KB(512); | ||
1193 | } | ||
1194 | } | ||
1195 | |||
1137 | /* The intel i965 automatically initializes the agp aperture during POST. | 1196 | /* The intel i965 automatically initializes the agp aperture during POST. |
1138 | * Use the memory already set aside for in the GTT. | 1197 | * Use the memory already set aside for in the GTT. |
1139 | */ | 1198 | */ |
1140 | static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) | 1199 | static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) |
1141 | { | 1200 | { |
1142 | int page_order; | 1201 | int page_order; |
1143 | struct aper_size_info_fixed *size; | 1202 | struct aper_size_info_fixed *size; |
1144 | int num_entries; | 1203 | int num_entries; |
1145 | u32 temp; | 1204 | u32 temp; |
1146 | int gtt_offset, gtt_size; | 1205 | int gtt_offset, gtt_size; |
1147 | 1206 | ||
1148 | size = agp_bridge->current_size; | 1207 | size = agp_bridge->current_size; |
1149 | page_order = size->page_order; | 1208 | page_order = size->page_order; |
1150 | num_entries = size->num_entries; | 1209 | num_entries = size->num_entries; |
1151 | agp_bridge->gatt_table_real = NULL; | 1210 | agp_bridge->gatt_table_real = NULL; |
1152 | 1211 | ||
1153 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); | 1212 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
1154 | 1213 | ||
1155 | temp &= 0xfff00000; | 1214 | temp &= 0xfff00000; |
1156 | 1215 | ||
1157 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB) | 1216 | intel_i965_get_gtt_range(>t_offset, >t_size); |
1158 | gtt_offset = gtt_size = MB(2); | ||
1159 | else | ||
1160 | gtt_offset = gtt_size = KB(512); | ||
1161 | 1217 | ||
1162 | intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); | 1218 | intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); |
1163 | 1219 | ||
1164 | if (!intel_private.gtt) | 1220 | if (!intel_private.gtt) |
1165 | return -ENOMEM; | 1221 | return -ENOMEM; |
1166 | 1222 | ||
1167 | intel_private.registers = ioremap(temp, 128 * 4096); | 1223 | intel_private.registers = ioremap(temp, 128 * 4096); |
1168 | if (!intel_private.registers) { | 1224 | if (!intel_private.registers) { |
1169 | iounmap(intel_private.gtt); | 1225 | iounmap(intel_private.gtt); |
1170 | return -ENOMEM; | 1226 | return -ENOMEM; |
1171 | } | 1227 | } |
1172 | 1228 | ||
1173 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; | 1229 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1174 | global_cache_flush(); /* FIXME: ? */ | 1230 | global_cache_flush(); /* FIXME: ? */ |
1175 | 1231 | ||
1176 | /* we have to call this as early as possible after the MMIO base address is known */ | 1232 | /* we have to call this as early as possible after the MMIO base address is known */ |
1177 | intel_i830_init_gtt_entries(); | 1233 | intel_i830_init_gtt_entries(); |
1178 | 1234 | ||
1179 | agp_bridge->gatt_table = NULL; | 1235 | agp_bridge->gatt_table = NULL; |
1180 | 1236 | ||
1181 | agp_bridge->gatt_bus_addr = temp; | 1237 | agp_bridge->gatt_bus_addr = temp; |
1182 | 1238 | ||
1183 | return 0; | 1239 | return 0; |
1184 | } | 1240 | } |
1185 | 1241 | ||
1186 | 1242 | ||
@@ -1656,7 +1712,7 @@ static const struct agp_bridge_driver intel_810_driver = { | |||
1656 | .aperture_sizes = intel_i810_sizes, | 1712 | .aperture_sizes = intel_i810_sizes, |
1657 | .size_type = FIXED_APER_SIZE, | 1713 | .size_type = FIXED_APER_SIZE, |
1658 | .num_aperture_sizes = 2, | 1714 | .num_aperture_sizes = 2, |
1659 | .needs_scratch_page = TRUE, | 1715 | .needs_scratch_page = true, |
1660 | .configure = intel_i810_configure, | 1716 | .configure = intel_i810_configure, |
1661 | .fetch_size = intel_i810_fetch_size, | 1717 | .fetch_size = intel_i810_fetch_size, |
1662 | .cleanup = intel_i810_cleanup, | 1718 | .cleanup = intel_i810_cleanup, |
@@ -1697,7 +1753,7 @@ static const struct agp_bridge_driver intel_815_driver = { | |||
1697 | .free_by_type = agp_generic_free_by_type, | 1753 | .free_by_type = agp_generic_free_by_type, |
1698 | .agp_alloc_page = agp_generic_alloc_page, | 1754 | .agp_alloc_page = agp_generic_alloc_page, |
1699 | .agp_destroy_page = agp_generic_destroy_page, | 1755 | .agp_destroy_page = agp_generic_destroy_page, |
1700 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, | 1756 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1701 | }; | 1757 | }; |
1702 | 1758 | ||
1703 | static const struct agp_bridge_driver intel_830_driver = { | 1759 | static const struct agp_bridge_driver intel_830_driver = { |
@@ -1705,7 +1761,7 @@ static const struct agp_bridge_driver intel_830_driver = { | |||
1705 | .aperture_sizes = intel_i830_sizes, | 1761 | .aperture_sizes = intel_i830_sizes, |
1706 | .size_type = FIXED_APER_SIZE, | 1762 | .size_type = FIXED_APER_SIZE, |
1707 | .num_aperture_sizes = 4, | 1763 | .num_aperture_sizes = 4, |
1708 | .needs_scratch_page = TRUE, | 1764 | .needs_scratch_page = true, |
1709 | .configure = intel_i830_configure, | 1765 | .configure = intel_i830_configure, |
1710 | .fetch_size = intel_i830_fetch_size, | 1766 | .fetch_size = intel_i830_fetch_size, |
1711 | .cleanup = intel_i830_cleanup, | 1767 | .cleanup = intel_i830_cleanup, |
@@ -1876,7 +1932,7 @@ static const struct agp_bridge_driver intel_915_driver = { | |||
1876 | .aperture_sizes = intel_i830_sizes, | 1932 | .aperture_sizes = intel_i830_sizes, |
1877 | .size_type = FIXED_APER_SIZE, | 1933 | .size_type = FIXED_APER_SIZE, |
1878 | .num_aperture_sizes = 4, | 1934 | .num_aperture_sizes = 4, |
1879 | .needs_scratch_page = TRUE, | 1935 | .needs_scratch_page = true, |
1880 | .configure = intel_i915_configure, | 1936 | .configure = intel_i915_configure, |
1881 | .fetch_size = intel_i9xx_fetch_size, | 1937 | .fetch_size = intel_i9xx_fetch_size, |
1882 | .cleanup = intel_i915_cleanup, | 1938 | .cleanup = intel_i915_cleanup, |
@@ -1898,28 +1954,28 @@ static const struct agp_bridge_driver intel_915_driver = { | |||
1898 | }; | 1954 | }; |
1899 | 1955 | ||
1900 | static const struct agp_bridge_driver intel_i965_driver = { | 1956 | static const struct agp_bridge_driver intel_i965_driver = { |
1901 | .owner = THIS_MODULE, | 1957 | .owner = THIS_MODULE, |
1902 | .aperture_sizes = intel_i830_sizes, | 1958 | .aperture_sizes = intel_i830_sizes, |
1903 | .size_type = FIXED_APER_SIZE, | 1959 | .size_type = FIXED_APER_SIZE, |
1904 | .num_aperture_sizes = 4, | 1960 | .num_aperture_sizes = 4, |
1905 | .needs_scratch_page = TRUE, | 1961 | .needs_scratch_page = true, |
1906 | .configure = intel_i915_configure, | 1962 | .configure = intel_i915_configure, |
1907 | .fetch_size = intel_i9xx_fetch_size, | 1963 | .fetch_size = intel_i9xx_fetch_size, |
1908 | .cleanup = intel_i915_cleanup, | 1964 | .cleanup = intel_i915_cleanup, |
1909 | .tlb_flush = intel_i810_tlbflush, | 1965 | .tlb_flush = intel_i810_tlbflush, |
1910 | .mask_memory = intel_i965_mask_memory, | 1966 | .mask_memory = intel_i965_mask_memory, |
1911 | .masks = intel_i810_masks, | 1967 | .masks = intel_i810_masks, |
1912 | .agp_enable = intel_i810_agp_enable, | 1968 | .agp_enable = intel_i810_agp_enable, |
1913 | .cache_flush = global_cache_flush, | 1969 | .cache_flush = global_cache_flush, |
1914 | .create_gatt_table = intel_i965_create_gatt_table, | 1970 | .create_gatt_table = intel_i965_create_gatt_table, |
1915 | .free_gatt_table = intel_i830_free_gatt_table, | 1971 | .free_gatt_table = intel_i830_free_gatt_table, |
1916 | .insert_memory = intel_i915_insert_entries, | 1972 | .insert_memory = intel_i915_insert_entries, |
1917 | .remove_memory = intel_i915_remove_entries, | 1973 | .remove_memory = intel_i915_remove_entries, |
1918 | .alloc_by_type = intel_i830_alloc_by_type, | 1974 | .alloc_by_type = intel_i830_alloc_by_type, |
1919 | .free_by_type = intel_i810_free_by_type, | 1975 | .free_by_type = intel_i810_free_by_type, |
1920 | .agp_alloc_page = agp_generic_alloc_page, | 1976 | .agp_alloc_page = agp_generic_alloc_page, |
1921 | .agp_destroy_page = agp_generic_destroy_page, | 1977 | .agp_destroy_page = agp_generic_destroy_page, |
1922 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | 1978 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
1923 | .chipset_flush = intel_i915_chipset_flush, | 1979 | .chipset_flush = intel_i915_chipset_flush, |
1924 | }; | 1980 | }; |
1925 | 1981 | ||
@@ -1948,28 +2004,28 @@ static const struct agp_bridge_driver intel_7505_driver = { | |||
1948 | }; | 2004 | }; |
1949 | 2005 | ||
1950 | static const struct agp_bridge_driver intel_g33_driver = { | 2006 | static const struct agp_bridge_driver intel_g33_driver = { |
1951 | .owner = THIS_MODULE, | 2007 | .owner = THIS_MODULE, |
1952 | .aperture_sizes = intel_i830_sizes, | 2008 | .aperture_sizes = intel_i830_sizes, |
1953 | .size_type = FIXED_APER_SIZE, | 2009 | .size_type = FIXED_APER_SIZE, |
1954 | .num_aperture_sizes = 4, | 2010 | .num_aperture_sizes = 4, |
1955 | .needs_scratch_page = TRUE, | 2011 | .needs_scratch_page = true, |
1956 | .configure = intel_i915_configure, | 2012 | .configure = intel_i915_configure, |
1957 | .fetch_size = intel_i9xx_fetch_size, | 2013 | .fetch_size = intel_i9xx_fetch_size, |
1958 | .cleanup = intel_i915_cleanup, | 2014 | .cleanup = intel_i915_cleanup, |
1959 | .tlb_flush = intel_i810_tlbflush, | 2015 | .tlb_flush = intel_i810_tlbflush, |
1960 | .mask_memory = intel_i965_mask_memory, | 2016 | .mask_memory = intel_i965_mask_memory, |
1961 | .masks = intel_i810_masks, | 2017 | .masks = intel_i810_masks, |
1962 | .agp_enable = intel_i810_agp_enable, | 2018 | .agp_enable = intel_i810_agp_enable, |
1963 | .cache_flush = global_cache_flush, | 2019 | .cache_flush = global_cache_flush, |
1964 | .create_gatt_table = intel_i915_create_gatt_table, | 2020 | .create_gatt_table = intel_i915_create_gatt_table, |
1965 | .free_gatt_table = intel_i830_free_gatt_table, | 2021 | .free_gatt_table = intel_i830_free_gatt_table, |
1966 | .insert_memory = intel_i915_insert_entries, | 2022 | .insert_memory = intel_i915_insert_entries, |
1967 | .remove_memory = intel_i915_remove_entries, | 2023 | .remove_memory = intel_i915_remove_entries, |
1968 | .alloc_by_type = intel_i830_alloc_by_type, | 2024 | .alloc_by_type = intel_i830_alloc_by_type, |
1969 | .free_by_type = intel_i810_free_by_type, | 2025 | .free_by_type = intel_i810_free_by_type, |
1970 | .agp_alloc_page = agp_generic_alloc_page, | 2026 | .agp_alloc_page = agp_generic_alloc_page, |
1971 | .agp_destroy_page = agp_generic_destroy_page, | 2027 | .agp_destroy_page = agp_generic_destroy_page, |
1972 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | 2028 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
1973 | .chipset_flush = intel_i915_chipset_flush, | 2029 | .chipset_flush = intel_i915_chipset_flush, |
1974 | }; | 2030 | }; |
1975 | 2031 | ||
@@ -2063,6 +2119,12 @@ static const struct intel_driver_description { | |||
2063 | NULL, &intel_g33_driver }, | 2119 | NULL, &intel_g33_driver }, |
2064 | { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0, | 2120 | { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0, |
2065 | "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, | 2121 | "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, |
2122 | { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0, | ||
2123 | "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, | ||
2124 | { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, | ||
2125 | "Q45/Q43", NULL, &intel_i965_driver }, | ||
2126 | { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, | ||
2127 | "G45/G43", NULL, &intel_i965_driver }, | ||
2066 | { 0, 0, 0, NULL, NULL, NULL } | 2128 | { 0, 0, 0, NULL, NULL, NULL } |
2067 | }; | 2129 | }; |
2068 | 2130 | ||
@@ -2254,6 +2316,9 @@ static struct pci_device_id agp_intel_pci_table[] = { | |||
2254 | ID(PCI_DEVICE_ID_INTEL_Q35_HB), | 2316 | ID(PCI_DEVICE_ID_INTEL_Q35_HB), |
2255 | ID(PCI_DEVICE_ID_INTEL_Q33_HB), | 2317 | ID(PCI_DEVICE_ID_INTEL_Q33_HB), |
2256 | ID(PCI_DEVICE_ID_INTEL_IGD_HB), | 2318 | ID(PCI_DEVICE_ID_INTEL_IGD_HB), |
2319 | ID(PCI_DEVICE_ID_INTEL_IGD_E_HB), | ||
2320 | ID(PCI_DEVICE_ID_INTEL_Q45_HB), | ||
2321 | ID(PCI_DEVICE_ID_INTEL_G45_HB), | ||
2257 | { } | 2322 | { } |
2258 | }; | 2323 | }; |
2259 | 2324 | ||
diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c index 225ed2a53d45..eaceb61ba2dc 100644 --- a/drivers/char/agp/nvidia-agp.c +++ b/drivers/char/agp/nvidia-agp.c | |||
@@ -214,9 +214,9 @@ static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type | |||
214 | return -EBUSY; | 214 | return -EBUSY; |
215 | } | 215 | } |
216 | 216 | ||
217 | if (mem->is_flushed == FALSE) { | 217 | if (!mem->is_flushed) { |
218 | global_cache_flush(); | 218 | global_cache_flush(); |
219 | mem->is_flushed = TRUE; | 219 | mem->is_flushed = true; |
220 | } | 220 | } |
221 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | 221 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { |
222 | writel(agp_bridge->driver->mask_memory(agp_bridge, | 222 | writel(agp_bridge->driver->mask_memory(agp_bridge, |
diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c index 2939e3570f9d..8c42dcc5958c 100644 --- a/drivers/char/agp/parisc-agp.c +++ b/drivers/char/agp/parisc-agp.c | |||
@@ -141,9 +141,9 @@ parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type) | |||
141 | j++; | 141 | j++; |
142 | } | 142 | } |
143 | 143 | ||
144 | if (mem->is_flushed == FALSE) { | 144 | if (!mem->is_flushed) { |
145 | global_cache_flush(); | 145 | global_cache_flush(); |
146 | mem->is_flushed = TRUE; | 146 | mem->is_flushed = true; |
147 | } | 147 | } |
148 | 148 | ||
149 | for (i = 0, j = io_pg_start; i < mem->page_count; i++) { | 149 | for (i = 0, j = io_pg_start; i < mem->page_count; i++) { |
@@ -226,7 +226,7 @@ static const struct agp_bridge_driver parisc_agp_driver = { | |||
226 | .agp_alloc_page = agp_generic_alloc_page, | 226 | .agp_alloc_page = agp_generic_alloc_page, |
227 | .agp_destroy_page = agp_generic_destroy_page, | 227 | .agp_destroy_page = agp_generic_destroy_page, |
228 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, | 228 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
229 | .cant_use_aperture = 1, | 229 | .cant_use_aperture = true, |
230 | }; | 230 | }; |
231 | 231 | ||
232 | static int __init | 232 | static int __init |
diff --git a/drivers/char/agp/sgi-agp.c b/drivers/char/agp/sgi-agp.c index 98cf8abb3e57..b972d83bb1b2 100644 --- a/drivers/char/agp/sgi-agp.c +++ b/drivers/char/agp/sgi-agp.c | |||
@@ -182,9 +182,9 @@ static int sgi_tioca_insert_memory(struct agp_memory *mem, off_t pg_start, | |||
182 | j++; | 182 | j++; |
183 | } | 183 | } |
184 | 184 | ||
185 | if (mem->is_flushed == FALSE) { | 185 | if (!mem->is_flushed) { |
186 | bridge->driver->cache_flush(); | 186 | bridge->driver->cache_flush(); |
187 | mem->is_flushed = TRUE; | 187 | mem->is_flushed = true; |
188 | } | 188 | } |
189 | 189 | ||
190 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | 190 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { |
@@ -264,8 +264,8 @@ const struct agp_bridge_driver sgi_tioca_driver = { | |||
264 | .agp_alloc_page = sgi_tioca_alloc_page, | 264 | .agp_alloc_page = sgi_tioca_alloc_page, |
265 | .agp_destroy_page = agp_generic_destroy_page, | 265 | .agp_destroy_page = agp_generic_destroy_page, |
266 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, | 266 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
267 | .cant_use_aperture = 1, | 267 | .cant_use_aperture = true, |
268 | .needs_scratch_page = 0, | 268 | .needs_scratch_page = false, |
269 | .num_aperture_sizes = 1, | 269 | .num_aperture_sizes = 1, |
270 | }; | 270 | }; |
271 | 271 | ||
diff --git a/drivers/char/agp/sworks-agp.c b/drivers/char/agp/sworks-agp.c index e08934e58f32..0e054c134490 100644 --- a/drivers/char/agp/sworks-agp.c +++ b/drivers/char/agp/sworks-agp.c | |||
@@ -339,9 +339,9 @@ static int serverworks_insert_memory(struct agp_memory *mem, | |||
339 | j++; | 339 | j++; |
340 | } | 340 | } |
341 | 341 | ||
342 | if (mem->is_flushed == FALSE) { | 342 | if (!mem->is_flushed) { |
343 | global_cache_flush(); | 343 | global_cache_flush(); |
344 | mem->is_flushed = TRUE; | 344 | mem->is_flushed = true; |
345 | } | 345 | } |
346 | 346 | ||
347 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | 347 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { |
@@ -412,7 +412,7 @@ static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode) | |||
412 | bridge->capndx + PCI_AGP_COMMAND, | 412 | bridge->capndx + PCI_AGP_COMMAND, |
413 | command); | 413 | command); |
414 | 414 | ||
415 | agp_device_command(command, 0); | 415 | agp_device_command(command, false); |
416 | } | 416 | } |
417 | 417 | ||
418 | static const struct agp_bridge_driver sworks_driver = { | 418 | static const struct agp_bridge_driver sworks_driver = { |
diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c index 42c0a600b1ac..d2fa3cfca02a 100644 --- a/drivers/char/agp/uninorth-agp.c +++ b/drivers/char/agp/uninorth-agp.c | |||
@@ -281,10 +281,10 @@ static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode) | |||
281 | 281 | ||
282 | if (uninorth_rev >= 0x30) { | 282 | if (uninorth_rev >= 0x30) { |
283 | /* This is an AGP V3 */ | 283 | /* This is an AGP V3 */ |
284 | agp_device_command(command, (status & AGPSTAT_MODE_3_0)); | 284 | agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0); |
285 | } else { | 285 | } else { |
286 | /* AGP V2 */ | 286 | /* AGP V2 */ |
287 | agp_device_command(command, 0); | 287 | agp_device_command(command, false); |
288 | } | 288 | } |
289 | 289 | ||
290 | uninorth_tlbflush(NULL); | 290 | uninorth_tlbflush(NULL); |
@@ -511,7 +511,7 @@ const struct agp_bridge_driver uninorth_agp_driver = { | |||
511 | .agp_alloc_page = agp_generic_alloc_page, | 511 | .agp_alloc_page = agp_generic_alloc_page, |
512 | .agp_destroy_page = agp_generic_destroy_page, | 512 | .agp_destroy_page = agp_generic_destroy_page, |
513 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, | 513 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
514 | .cant_use_aperture = 1, | 514 | .cant_use_aperture = true, |
515 | }; | 515 | }; |
516 | 516 | ||
517 | const struct agp_bridge_driver u3_agp_driver = { | 517 | const struct agp_bridge_driver u3_agp_driver = { |
@@ -536,8 +536,8 @@ const struct agp_bridge_driver u3_agp_driver = { | |||
536 | .agp_alloc_page = agp_generic_alloc_page, | 536 | .agp_alloc_page = agp_generic_alloc_page, |
537 | .agp_destroy_page = agp_generic_destroy_page, | 537 | .agp_destroy_page = agp_generic_destroy_page, |
538 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, | 538 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
539 | .cant_use_aperture = 1, | 539 | .cant_use_aperture = true, |
540 | .needs_scratch_page = 1, | 540 | .needs_scratch_page = true, |
541 | }; | 541 | }; |
542 | 542 | ||
543 | static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = { | 543 | static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = { |
diff --git a/drivers/char/agp/via-agp.c b/drivers/char/agp/via-agp.c index 0ecc54d327bc..7b36476dff41 100644 --- a/drivers/char/agp/via-agp.c +++ b/drivers/char/agp/via-agp.c | |||
@@ -389,11 +389,20 @@ static struct agp_device_ids via_agp_device_ids[] __devinitdata = | |||
389 | .device_id = PCI_DEVICE_ID_VIA_VT3324, | 389 | .device_id = PCI_DEVICE_ID_VIA_VT3324, |
390 | .chipset_name = "CX700", | 390 | .chipset_name = "CX700", |
391 | }, | 391 | }, |
392 | /* VT3336 */ | 392 | /* VT3336 - this is a chipset for AMD Athlon/K8 CPU. Due to K8's unique |
393 | * architecture, the AGP resource and behavior are different from | ||
394 | * the traditional AGP which resides only in chipset. AGP is used | ||
395 | * by 3D driver which wasn't available for the VT3336 and VT3364 | ||
396 | * generation until now. Unfortunately, by testing, VT3364 works | ||
397 | * but VT3336 doesn't. - explaination from via, just leave this as | ||
398 | * as a placeholder to avoid future patches adding it back in. | ||
399 | */ | ||
400 | #if 0 | ||
393 | { | 401 | { |
394 | .device_id = PCI_DEVICE_ID_VIA_VT3336, | 402 | .device_id = PCI_DEVICE_ID_VIA_VT3336, |
395 | .chipset_name = "VT3336", | 403 | .chipset_name = "VT3336", |
396 | }, | 404 | }, |
405 | #endif | ||
397 | /* P4M890 */ | 406 | /* P4M890 */ |
398 | { | 407 | { |
399 | .device_id = PCI_DEVICE_ID_VIA_P4M890, | 408 | .device_id = PCI_DEVICE_ID_VIA_P4M890, |
@@ -546,8 +555,8 @@ static const struct pci_device_id agp_via_pci_table[] = { | |||
546 | ID(PCI_DEVICE_ID_VIA_3296_0), | 555 | ID(PCI_DEVICE_ID_VIA_3296_0), |
547 | ID(PCI_DEVICE_ID_VIA_P4M800CE), | 556 | ID(PCI_DEVICE_ID_VIA_P4M800CE), |
548 | ID(PCI_DEVICE_ID_VIA_VT3324), | 557 | ID(PCI_DEVICE_ID_VIA_VT3324), |
549 | ID(PCI_DEVICE_ID_VIA_VT3336), | ||
550 | ID(PCI_DEVICE_ID_VIA_P4M890), | 558 | ID(PCI_DEVICE_ID_VIA_P4M890), |
559 | ID(PCI_DEVICE_ID_VIA_VT3364), | ||
551 | { } | 560 | { } |
552 | }; | 561 | }; |
553 | 562 | ||
diff --git a/drivers/char/drm/ati_pcigart.c b/drivers/char/drm/ati_pcigart.c index b710426bab3e..c533d0c9ec61 100644 --- a/drivers/char/drm/ati_pcigart.c +++ b/drivers/char/drm/ati_pcigart.c | |||
@@ -76,7 +76,7 @@ int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info | |||
76 | for (i = 0; i < pages; i++) { | 76 | for (i = 0; i < pages; i++) { |
77 | if (!entry->busaddr[i]) | 77 | if (!entry->busaddr[i]) |
78 | break; | 78 | break; |
79 | pci_unmap_single(dev->pdev, entry->busaddr[i], | 79 | pci_unmap_page(dev->pdev, entry->busaddr[i], |
80 | PAGE_SIZE, PCI_DMA_TODEVICE); | 80 | PAGE_SIZE, PCI_DMA_TODEVICE); |
81 | } | 81 | } |
82 | 82 | ||
@@ -137,10 +137,8 @@ int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *ga | |||
137 | 137 | ||
138 | for (i = 0; i < pages; i++) { | 138 | for (i = 0; i < pages; i++) { |
139 | /* we need to support large memory configurations */ | 139 | /* we need to support large memory configurations */ |
140 | entry->busaddr[i] = pci_map_single(dev->pdev, | 140 | entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i], |
141 | page_address(entry-> | 141 | 0, PAGE_SIZE, PCI_DMA_TODEVICE); |
142 | pagelist[i]), | ||
143 | PAGE_SIZE, PCI_DMA_TODEVICE); | ||
144 | if (entry->busaddr[i] == 0) { | 142 | if (entry->busaddr[i] == 0) { |
145 | DRM_ERROR("unable to map PCIGART pages!\n"); | 143 | DRM_ERROR("unable to map PCIGART pages!\n"); |
146 | drm_ati_pcigart_cleanup(dev, gart_info); | 144 | drm_ati_pcigart_cleanup(dev, gart_info); |
diff --git a/drivers/char/drm/drm.h b/drivers/char/drm/drm.h index 3a05c6d5ebe1..38d3c6b8276a 100644 --- a/drivers/char/drm/drm.h +++ b/drivers/char/drm/drm.h | |||
@@ -628,7 +628,7 @@ struct drm_set_version { | |||
628 | #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) | 628 | #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) |
629 | #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) | 629 | #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) |
630 | 630 | ||
631 | #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather) | 631 | #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) |
632 | #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) | 632 | #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) |
633 | 633 | ||
634 | #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) | 634 | #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) |
diff --git a/drivers/char/drm/drm_drv.c b/drivers/char/drm/drm_drv.c index fc54140551a7..564138714bb5 100644 --- a/drivers/char/drm/drm_drv.c +++ b/drivers/char/drm/drm_drv.c | |||
@@ -470,17 +470,18 @@ int drm_ioctl(struct inode *inode, struct file *filp, | |||
470 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) && | 470 | if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) && |
471 | (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) | 471 | (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) |
472 | ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE]; | 472 | ioctl = &dev->driver->ioctls[nr - DRM_COMMAND_BASE]; |
473 | else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) | 473 | else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) { |
474 | ioctl = &drm_ioctls[nr]; | 474 | ioctl = &drm_ioctls[nr]; |
475 | else | 475 | cmd = ioctl->cmd; |
476 | } else | ||
476 | goto err_i1; | 477 | goto err_i1; |
477 | 478 | ||
479 | /* Do not trust userspace, use our own definition */ | ||
478 | func = ioctl->func; | 480 | func = ioctl->func; |
479 | /* is there a local override? */ | 481 | /* is there a local override? */ |
480 | if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl) | 482 | if ((nr == DRM_IOCTL_NR(DRM_IOCTL_DMA)) && dev->driver->dma_ioctl) |
481 | func = dev->driver->dma_ioctl; | 483 | func = dev->driver->dma_ioctl; |
482 | 484 | ||
483 | |||
484 | if (!func) { | 485 | if (!func) { |
485 | DRM_DEBUG("no function\n"); | 486 | DRM_DEBUG("no function\n"); |
486 | retcode = -EINVAL; | 487 | retcode = -EINVAL; |
diff --git a/drivers/char/drm/drm_pciids.h b/drivers/char/drm/drm_pciids.h index a6a499f97e22..135bd19499fc 100644 --- a/drivers/char/drm/drm_pciids.h +++ b/drivers/char/drm/drm_pciids.h | |||
@@ -103,20 +103,18 @@ | |||
103 | {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ | 103 | {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
104 | {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ | 104 | {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ |
105 | {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ | 105 | {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
106 | {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | 106 | {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
107 | {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | 107 | {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
108 | {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | 108 | {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
109 | {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | 109 | {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
110 | {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ | 110 | {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
111 | {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ | 111 | {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
112 | {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ | 112 | {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
113 | {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ | 113 | {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
114 | {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ | 114 | {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
115 | {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ | 115 | {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
116 | {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | 116 | {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
117 | {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | 117 | {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
118 | {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | ||
119 | {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ | ||
120 | {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ | 118 | {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
121 | {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ | 119 | {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
122 | {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ | 120 | {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
@@ -411,4 +409,7 @@ | |||
411 | {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | 409 | {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ |
412 | {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | 410 | {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ |
413 | {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | 411 | {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ |
412 | {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
413 | {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
414 | {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \ | ||
414 | {0, 0, 0} | 415 | {0, 0, 0} |
diff --git a/drivers/char/drm/i915_drv.c b/drivers/char/drm/i915_drv.c index e8f3d682e3b1..93aed1c38bd2 100644 --- a/drivers/char/drm/i915_drv.c +++ b/drivers/char/drm/i915_drv.c | |||
@@ -389,6 +389,7 @@ static int i915_resume(struct drm_device *dev) | |||
389 | pci_restore_state(dev->pdev); | 389 | pci_restore_state(dev->pdev); |
390 | if (pci_enable_device(dev->pdev)) | 390 | if (pci_enable_device(dev->pdev)) |
391 | return -1; | 391 | return -1; |
392 | pci_set_master(dev->pdev); | ||
392 | 393 | ||
393 | pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); | 394 | pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); |
394 | 395 | ||
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h index 1b20f7c0639c..d7326d92a237 100644 --- a/drivers/char/drm/i915_drv.h +++ b/drivers/char/drm/i915_drv.h | |||
@@ -1112,12 +1112,19 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); | |||
1112 | (dev)->pci_device == 0x29A2 || \ | 1112 | (dev)->pci_device == 0x29A2 || \ |
1113 | (dev)->pci_device == 0x2A02 || \ | 1113 | (dev)->pci_device == 0x2A02 || \ |
1114 | (dev)->pci_device == 0x2A12 || \ | 1114 | (dev)->pci_device == 0x2A12 || \ |
1115 | (dev)->pci_device == 0x2A42) | 1115 | (dev)->pci_device == 0x2A42 || \ |
1116 | (dev)->pci_device == 0x2E02 || \ | ||
1117 | (dev)->pci_device == 0x2E12 || \ | ||
1118 | (dev)->pci_device == 0x2E22) | ||
1116 | 1119 | ||
1117 | #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) | 1120 | #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) |
1118 | 1121 | ||
1119 | #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42) | 1122 | #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42) |
1120 | 1123 | ||
1124 | #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ | ||
1125 | (dev)->pci_device == 0x2E12 || \ | ||
1126 | (dev)->pci_device == 0x2E22) | ||
1127 | |||
1121 | #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ | 1128 | #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ |
1122 | (dev)->pci_device == 0x29B2 || \ | 1129 | (dev)->pci_device == 0x29B2 || \ |
1123 | (dev)->pci_device == 0x29D2) | 1130 | (dev)->pci_device == 0x29D2) |
@@ -1128,7 +1135,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); | |||
1128 | #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ | 1135 | #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ |
1129 | IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev)) | 1136 | IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev)) |
1130 | 1137 | ||
1131 | #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev)) | 1138 | #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev)) |
1132 | 1139 | ||
1133 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) | 1140 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
1134 | 1141 | ||
diff --git a/drivers/char/drm/i915_irq.c b/drivers/char/drm/i915_irq.c index f7f16e7a8bf3..df036118b8b1 100644 --- a/drivers/char/drm/i915_irq.c +++ b/drivers/char/drm/i915_irq.c | |||
@@ -62,11 +62,11 @@ static void i915_vblank_tasklet(struct drm_device *dev) | |||
62 | u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24); | 62 | u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24); |
63 | RING_LOCALS; | 63 | RING_LOCALS; |
64 | 64 | ||
65 | if (sarea_priv->front_tiled) { | 65 | if (IS_I965G(dev) && sarea_priv->front_tiled) { |
66 | cmd |= XY_SRC_COPY_BLT_DST_TILED; | 66 | cmd |= XY_SRC_COPY_BLT_DST_TILED; |
67 | dst_pitch >>= 2; | 67 | dst_pitch >>= 2; |
68 | } | 68 | } |
69 | if (sarea_priv->back_tiled) { | 69 | if (IS_I965G(dev) && sarea_priv->back_tiled) { |
70 | cmd |= XY_SRC_COPY_BLT_SRC_TILED; | 70 | cmd |= XY_SRC_COPY_BLT_SRC_TILED; |
71 | src_pitch >>= 2; | 71 | src_pitch >>= 2; |
72 | } | 72 | } |
diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c index f535812e4057..702df45320f7 100644 --- a/drivers/char/drm/r300_cmdbuf.c +++ b/drivers/char/drm/r300_cmdbuf.c | |||
@@ -189,18 +189,12 @@ void r300_init_reg_flags(struct drm_device *dev) | |||
189 | ADD_RANGE(R300_RE_CULL_CNTL, 1); | 189 | ADD_RANGE(R300_RE_CULL_CNTL, 1); |
190 | ADD_RANGE(0x42C0, 2); | 190 | ADD_RANGE(0x42C0, 2); |
191 | ADD_RANGE(R300_RS_CNTL_0, 2); | 191 | ADD_RANGE(R300_RS_CNTL_0, 2); |
192 | ADD_RANGE(R300_RS_INTERP_0, 8); | 192 | |
193 | ADD_RANGE(R300_RS_ROUTE_0, 8); | 193 | ADD_RANGE(R300_SC_HYPERZ, 2); |
194 | ADD_RANGE(0x43A4, 2); | ||
195 | ADD_RANGE(0x43E8, 1); | 194 | ADD_RANGE(0x43E8, 1); |
196 | ADD_RANGE(R300_PFS_CNTL_0, 3); | 195 | |
197 | ADD_RANGE(R300_PFS_NODE_0, 4); | ||
198 | ADD_RANGE(R300_PFS_TEXI_0, 64); | ||
199 | ADD_RANGE(0x46A4, 5); | 196 | ADD_RANGE(0x46A4, 5); |
200 | ADD_RANGE(R300_PFS_INSTR0_0, 64); | 197 | |
201 | ADD_RANGE(R300_PFS_INSTR1_0, 64); | ||
202 | ADD_RANGE(R300_PFS_INSTR2_0, 64); | ||
203 | ADD_RANGE(R300_PFS_INSTR3_0, 64); | ||
204 | ADD_RANGE(R300_RE_FOG_STATE, 1); | 198 | ADD_RANGE(R300_RE_FOG_STATE, 1); |
205 | ADD_RANGE(R300_FOG_COLOR_R, 3); | 199 | ADD_RANGE(R300_FOG_COLOR_R, 3); |
206 | ADD_RANGE(R300_PP_ALPHA_TEST, 2); | 200 | ADD_RANGE(R300_PP_ALPHA_TEST, 2); |
@@ -215,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev) | |||
215 | ADD_RANGE(0x4E50, 9); | 209 | ADD_RANGE(0x4E50, 9); |
216 | ADD_RANGE(0x4E88, 1); | 210 | ADD_RANGE(0x4E88, 1); |
217 | ADD_RANGE(0x4EA0, 2); | 211 | ADD_RANGE(0x4EA0, 2); |
218 | ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3); | 212 | ADD_RANGE(R300_ZB_CNTL, 3); |
219 | ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4); | 213 | ADD_RANGE(R300_ZB_FORMAT, 4); |
220 | ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ | 214 | ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */ |
221 | ADD_RANGE(R300_RB3D_DEPTHPITCH, 1); | 215 | ADD_RANGE(R300_ZB_DEPTHPITCH, 1); |
222 | ADD_RANGE(0x4F28, 1); | 216 | ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1); |
223 | ADD_RANGE(0x4F30, 2); | 217 | ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13); |
224 | ADD_RANGE(0x4F44, 1); | ||
225 | ADD_RANGE(0x4F54, 1); | ||
226 | 218 | ||
227 | ADD_RANGE(R300_TX_FILTER_0, 16); | 219 | ADD_RANGE(R300_TX_FILTER_0, 16); |
228 | ADD_RANGE(R300_TX_FILTER1_0, 16); | 220 | ADD_RANGE(R300_TX_FILTER1_0, 16); |
@@ -235,13 +227,32 @@ void r300_init_reg_flags(struct drm_device *dev) | |||
235 | ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); | 227 | ADD_RANGE(R300_TX_BORDER_COLOR_0, 16); |
236 | 228 | ||
237 | /* Sporadic registers used as primitives are emitted */ | 229 | /* Sporadic registers used as primitives are emitted */ |
238 | ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1); | 230 | ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1); |
239 | ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); | 231 | ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1); |
240 | ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); | 232 | ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8); |
241 | ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); | 233 | ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8); |
242 | 234 | ||
243 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { | 235 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { |
244 | ADD_RANGE(0x4074, 16); | 236 | ADD_RANGE(R500_VAP_INDEX_OFFSET, 1); |
237 | ADD_RANGE(R500_US_CONFIG, 2); | ||
238 | ADD_RANGE(R500_US_CODE_ADDR, 3); | ||
239 | ADD_RANGE(R500_US_FC_CTRL, 1); | ||
240 | ADD_RANGE(R500_RS_IP_0, 16); | ||
241 | ADD_RANGE(R500_RS_INST_0, 16); | ||
242 | ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2); | ||
243 | ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2); | ||
244 | ADD_RANGE(R500_ZB_FIFO_SIZE, 2); | ||
245 | } else { | ||
246 | ADD_RANGE(R300_PFS_CNTL_0, 3); | ||
247 | ADD_RANGE(R300_PFS_NODE_0, 4); | ||
248 | ADD_RANGE(R300_PFS_TEXI_0, 64); | ||
249 | ADD_RANGE(R300_PFS_INSTR0_0, 64); | ||
250 | ADD_RANGE(R300_PFS_INSTR1_0, 64); | ||
251 | ADD_RANGE(R300_PFS_INSTR2_0, 64); | ||
252 | ADD_RANGE(R300_PFS_INSTR3_0, 64); | ||
253 | ADD_RANGE(R300_RS_INTERP_0, 8); | ||
254 | ADD_RANGE(R300_RS_ROUTE_0, 8); | ||
255 | |||
245 | } | 256 | } |
246 | } | 257 | } |
247 | 258 | ||
@@ -707,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv) | |||
707 | BEGIN_RING(6); | 718 | BEGIN_RING(6); |
708 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); | 719 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
709 | OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A); | 720 | OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A); |
710 | OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); | 721 | OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); |
711 | OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03); | 722 | OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE| |
723 | R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE); | ||
712 | OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); | 724 | OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0)); |
713 | OUT_RING(0x0); | 725 | OUT_RING(0x0); |
714 | ADVANCE_RING(); | 726 | ADVANCE_RING(); |
@@ -829,6 +841,54 @@ static int r300_scratch(drm_radeon_private_t *dev_priv, | |||
829 | } | 841 | } |
830 | 842 | ||
831 | /** | 843 | /** |
844 | * Uploads user-supplied vertex program instructions or parameters onto | ||
845 | * the graphics card. | ||
846 | * Called by r300_do_cp_cmdbuf. | ||
847 | */ | ||
848 | static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv, | ||
849 | drm_radeon_kcmd_buffer_t *cmdbuf, | ||
850 | drm_r300_cmd_header_t header) | ||
851 | { | ||
852 | int sz; | ||
853 | int addr; | ||
854 | int type; | ||
855 | int clamp; | ||
856 | int stride; | ||
857 | RING_LOCALS; | ||
858 | |||
859 | sz = header.r500fp.count; | ||
860 | /* address is 9 bits 0 - 8, bit 1 of flags is part of address */ | ||
861 | addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo; | ||
862 | |||
863 | type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE); | ||
864 | clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP); | ||
865 | |||
866 | addr |= (type << 16); | ||
867 | addr |= (clamp << 17); | ||
868 | |||
869 | stride = type ? 4 : 6; | ||
870 | |||
871 | DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type); | ||
872 | if (!sz) | ||
873 | return 0; | ||
874 | if (sz * stride * 4 > cmdbuf->bufsz) | ||
875 | return -EINVAL; | ||
876 | |||
877 | BEGIN_RING(3 + sz * stride); | ||
878 | OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr); | ||
879 | OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1)); | ||
880 | OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride); | ||
881 | |||
882 | ADVANCE_RING(); | ||
883 | |||
884 | cmdbuf->buf += sz * stride * 4; | ||
885 | cmdbuf->bufsz -= sz * stride * 4; | ||
886 | |||
887 | return 0; | ||
888 | } | ||
889 | |||
890 | |||
891 | /** | ||
832 | * Parses and validates a user-supplied command buffer and emits appropriate | 892 | * Parses and validates a user-supplied command buffer and emits appropriate |
833 | * commands on the DMA ring buffer. | 893 | * commands on the DMA ring buffer. |
834 | * Called by the ioctl handler function radeon_cp_cmdbuf. | 894 | * Called by the ioctl handler function radeon_cp_cmdbuf. |
@@ -963,6 +1023,19 @@ int r300_do_cp_cmdbuf(struct drm_device *dev, | |||
963 | } | 1023 | } |
964 | break; | 1024 | break; |
965 | 1025 | ||
1026 | case R300_CMD_R500FP: | ||
1027 | if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { | ||
1028 | DRM_ERROR("Calling r500 command on r300 card\n"); | ||
1029 | ret = -EINVAL; | ||
1030 | goto cleanup; | ||
1031 | } | ||
1032 | DRM_DEBUG("R300_CMD_R500FP\n"); | ||
1033 | ret = r300_emit_r500fp(dev_priv, cmdbuf, header); | ||
1034 | if (ret) { | ||
1035 | DRM_ERROR("r300_emit_r500fp failed\n"); | ||
1036 | goto cleanup; | ||
1037 | } | ||
1038 | break; | ||
966 | default: | 1039 | default: |
967 | DRM_ERROR("bad cmd_type %i at %p\n", | 1040 | DRM_ERROR("bad cmd_type %i at %p\n", |
968 | header.header.cmd_type, | 1041 | header.header.cmd_type, |
diff --git a/drivers/char/drm/r300_reg.h b/drivers/char/drm/r300_reg.h index 8f664af9c4a4..a6802f26afc4 100644 --- a/drivers/char/drm/r300_reg.h +++ b/drivers/char/drm/r300_reg.h | |||
@@ -702,6 +702,27 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. | |||
702 | # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) | 702 | # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) |
703 | /* END: Rasterization / Interpolators - many guesses */ | 703 | /* END: Rasterization / Interpolators - many guesses */ |
704 | 704 | ||
705 | /* Hierarchical Z Enable */ | ||
706 | #define R300_SC_HYPERZ 0x43a4 | ||
707 | # define R300_SC_HYPERZ_DISABLE (0 << 0) | ||
708 | # define R300_SC_HYPERZ_ENABLE (1 << 0) | ||
709 | # define R300_SC_HYPERZ_MIN (0 << 1) | ||
710 | # define R300_SC_HYPERZ_MAX (1 << 1) | ||
711 | # define R300_SC_HYPERZ_ADJ_256 (0 << 2) | ||
712 | # define R300_SC_HYPERZ_ADJ_128 (1 << 2) | ||
713 | # define R300_SC_HYPERZ_ADJ_64 (2 << 2) | ||
714 | # define R300_SC_HYPERZ_ADJ_32 (3 << 2) | ||
715 | # define R300_SC_HYPERZ_ADJ_16 (4 << 2) | ||
716 | # define R300_SC_HYPERZ_ADJ_8 (5 << 2) | ||
717 | # define R300_SC_HYPERZ_ADJ_4 (6 << 2) | ||
718 | # define R300_SC_HYPERZ_ADJ_2 (7 << 2) | ||
719 | # define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5) | ||
720 | # define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5) | ||
721 | # define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6) | ||
722 | # define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6) | ||
723 | |||
724 | #define R300_SC_EDGERULE 0x43a8 | ||
725 | |||
705 | /* BEGIN: Scissors and cliprects */ | 726 | /* BEGIN: Scissors and cliprects */ |
706 | 727 | ||
707 | /* There are four clipping rectangles. Their corner coordinates are inclusive. | 728 | /* There are four clipping rectangles. Their corner coordinates are inclusive. |
@@ -1346,7 +1367,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. | |||
1346 | /* Guess by Vladimir. | 1367 | /* Guess by Vladimir. |
1347 | * Set to 0A before 3D operations, set to 02 afterwards. | 1368 | * Set to 0A before 3D operations, set to 02 afterwards. |
1348 | */ | 1369 | */ |
1349 | #define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C | 1370 | /*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/ |
1350 | # define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002 | 1371 | # define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002 |
1351 | # define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A | 1372 | # define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A |
1352 | 1373 | ||
@@ -1355,19 +1376,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. | |||
1355 | * for this. | 1376 | * for this. |
1356 | * Bit (1<<8) is the "test" bit. so plain write is 6 - vd | 1377 | * Bit (1<<8) is the "test" bit. so plain write is 6 - vd |
1357 | */ | 1378 | */ |
1358 | #define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 | 1379 | #define R300_ZB_CNTL 0x4F00 |
1359 | # define R300_RB3D_Z_DISABLED_1 0x00000010 | 1380 | # define R300_STENCIL_ENABLE (1 << 0) |
1360 | # define R300_RB3D_Z_DISABLED_2 0x00000014 | 1381 | # define R300_Z_ENABLE (1 << 1) |
1361 | # define R300_RB3D_Z_TEST 0x00000012 | 1382 | # define R300_Z_WRITE_ENABLE (1 << 2) |
1362 | # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 | 1383 | # define R300_Z_SIGNED_COMPARE (1 << 3) |
1363 | # define R300_RB3D_Z_WRITE_ONLY 0x00000006 | 1384 | # define R300_STENCIL_FRONT_BACK (1 << 4) |
1364 | 1385 | ||
1365 | # define R300_RB3D_Z_TEST 0x00000012 | 1386 | #define R300_ZB_ZSTENCILCNTL 0x4f04 |
1366 | # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 | ||
1367 | # define R300_RB3D_Z_WRITE_ONLY 0x00000006 | ||
1368 | # define R300_RB3D_STENCIL_ENABLE 0x00000001 | ||
1369 | |||
1370 | #define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04 | ||
1371 | /* functions */ | 1387 | /* functions */ |
1372 | # define R300_ZS_NEVER 0 | 1388 | # define R300_ZS_NEVER 0 |
1373 | # define R300_ZS_LESS 1 | 1389 | # define R300_ZS_LESS 1 |
@@ -1387,52 +1403,166 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. | |||
1387 | # define R300_ZS_INVERT 5 | 1403 | # define R300_ZS_INVERT 5 |
1388 | # define R300_ZS_INCR_WRAP 6 | 1404 | # define R300_ZS_INCR_WRAP 6 |
1389 | # define R300_ZS_DECR_WRAP 7 | 1405 | # define R300_ZS_DECR_WRAP 7 |
1406 | # define R300_Z_FUNC_SHIFT 0 | ||
1390 | /* front and back refer to operations done for front | 1407 | /* front and back refer to operations done for front |
1391 | and back faces, i.e. separate stencil function support */ | 1408 | and back faces, i.e. separate stencil function support */ |
1392 | # define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0 | 1409 | # define R300_S_FRONT_FUNC_SHIFT 3 |
1393 | # define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3 | 1410 | # define R300_S_FRONT_SFAIL_OP_SHIFT 6 |
1394 | # define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6 | 1411 | # define R300_S_FRONT_ZPASS_OP_SHIFT 9 |
1395 | # define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9 | 1412 | # define R300_S_FRONT_ZFAIL_OP_SHIFT 12 |
1396 | # define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12 | 1413 | # define R300_S_BACK_FUNC_SHIFT 15 |
1397 | # define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15 | 1414 | # define R300_S_BACK_SFAIL_OP_SHIFT 18 |
1398 | # define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18 | 1415 | # define R300_S_BACK_ZPASS_OP_SHIFT 21 |
1399 | # define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 | 1416 | # define R300_S_BACK_ZFAIL_OP_SHIFT 24 |
1400 | # define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24 | 1417 | |
1401 | 1418 | #define R300_ZB_STENCILREFMASK 0x4f08 | |
1402 | #define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 | 1419 | # define R300_STENCILREF_SHIFT 0 |
1403 | # define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 | 1420 | # define R300_STENCILREF_MASK 0x000000ff |
1404 | # define R300_RB3D_ZS2_STENCIL_MASK 0xFF | 1421 | # define R300_STENCILMASK_SHIFT 8 |
1405 | # define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8 | 1422 | # define R300_STENCILMASK_MASK 0x0000ff00 |
1406 | # define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16 | 1423 | # define R300_STENCILWRITEMASK_SHIFT 16 |
1424 | # define R300_STENCILWRITEMASK_MASK 0x00ff0000 | ||
1407 | 1425 | ||
1408 | /* gap */ | 1426 | /* gap */ |
1409 | 1427 | ||
1410 | #define R300_RB3D_ZSTENCIL_FORMAT 0x4F10 | 1428 | #define R300_ZB_FORMAT 0x4f10 |
1411 | # define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) | 1429 | # define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0) |
1412 | # define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) | 1430 | # define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0) |
1413 | /* 16 bit format or some aditional bit ? */ | 1431 | # define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0) |
1414 | # define R300_DEPTH_FORMAT_UNK32 (32 << 0) | 1432 | /* reserved up to (15 << 0) */ |
1433 | # define R300_INVERT_13E3_LEADING_ONES (0 << 4) | ||
1434 | # define R300_INVERT_13E3_LEADING_ZEROS (1 << 4) | ||
1415 | 1435 | ||
1416 | #define R300_RB3D_EARLY_Z 0x4F14 | 1436 | #define R300_ZB_ZTOP 0x4F14 |
1417 | # define R300_EARLY_Z_DISABLE (0 << 0) | 1437 | # define R300_ZTOP_DISABLE (0 << 0) |
1418 | # define R300_EARLY_Z_ENABLE (1 << 0) | 1438 | # define R300_ZTOP_ENABLE (1 << 0) |
1419 | 1439 | ||
1420 | /* gap */ | 1440 | /* gap */ |
1421 | 1441 | ||
1422 | #define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */ | 1442 | #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 |
1423 | # define R300_RB3D_ZCACHE_UNKNOWN_01 0x1 | 1443 | # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0) |
1424 | # define R300_RB3D_ZCACHE_UNKNOWN_03 0x3 | 1444 | # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0) |
1445 | # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) | ||
1446 | # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) | ||
1447 | # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) | ||
1448 | # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) | ||
1449 | |||
1450 | #define R300_ZB_BW_CNTL 0x4f1c | ||
1451 | # define R300_HIZ_DISABLE (0 << 0) | ||
1452 | # define R300_HIZ_ENABLE (1 << 0) | ||
1453 | # define R300_HIZ_MIN (0 << 1) | ||
1454 | # define R300_HIZ_MAX (1 << 1) | ||
1455 | # define R300_FAST_FILL_DISABLE (0 << 2) | ||
1456 | # define R300_FAST_FILL_ENABLE (1 << 2) | ||
1457 | # define R300_RD_COMP_DISABLE (0 << 3) | ||
1458 | # define R300_RD_COMP_ENABLE (1 << 3) | ||
1459 | # define R300_WR_COMP_DISABLE (0 << 4) | ||
1460 | # define R300_WR_COMP_ENABLE (1 << 4) | ||
1461 | # define R300_ZB_CB_CLEAR_RMW (0 << 5) | ||
1462 | # define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5) | ||
1463 | # define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6) | ||
1464 | # define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6) | ||
1465 | |||
1466 | # define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7) | ||
1467 | # define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7) | ||
1468 | # define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8) | ||
1469 | # define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8) | ||
1470 | |||
1471 | # define R500_BMASK_ENABLE (0 << 10) | ||
1472 | # define R500_BMASK_DISABLE (1 << 10) | ||
1473 | # define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11) | ||
1474 | # define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11) | ||
1475 | # define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12) | ||
1476 | # define R500_HIZ_FP_EXP_BITS_1 (1 << 12) | ||
1477 | # define R500_HIZ_FP_EXP_BITS_2 (2 << 12) | ||
1478 | # define R500_HIZ_FP_EXP_BITS_3 (3 << 12) | ||
1479 | # define R500_HIZ_FP_EXP_BITS_4 (4 << 12) | ||
1480 | # define R500_HIZ_FP_EXP_BITS_5 (5 << 12) | ||
1481 | # define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15) | ||
1482 | # define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15) | ||
1483 | # define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16) | ||
1484 | # define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16) | ||
1485 | # define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17) | ||
1486 | # define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17) | ||
1487 | # define R500_PEQ_PACKING_DISABLE (0 << 18) | ||
1488 | # define R500_PEQ_PACKING_ENABLE (1 << 18) | ||
1489 | # define R500_COVERED_PTR_MASKING_DISABLE (0 << 18) | ||
1490 | # define R500_COVERED_PTR_MASKING_ENABLE (1 << 18) | ||
1491 | |||
1425 | 1492 | ||
1426 | /* gap */ | 1493 | /* gap */ |
1427 | 1494 | ||
1428 | #define R300_RB3D_DEPTHOFFSET 0x4F20 | 1495 | /* Z Buffer Address Offset. |
1429 | #define R300_RB3D_DEPTHPITCH 0x4F24 | 1496 | * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles. |
1430 | # define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ | 1497 | */ |
1431 | # define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ | 1498 | #define R300_ZB_DEPTHOFFSET 0x4f20 |
1432 | # define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ | 1499 | |
1433 | # define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ | 1500 | /* Z Buffer Pitch and Endian Control */ |
1434 | # define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ | 1501 | #define R300_ZB_DEPTHPITCH 0x4f24 |
1435 | # define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ | 1502 | # define R300_DEPTHPITCH_MASK 0x00003FFC |
1503 | # define R300_DEPTHMACROTILE_DISABLE (0 << 16) | ||
1504 | # define R300_DEPTHMACROTILE_ENABLE (1 << 16) | ||
1505 | # define R300_DEPTHMICROTILE_LINEAR (0 << 17) | ||
1506 | # define R300_DEPTHMICROTILE_TILED (1 << 17) | ||
1507 | # define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17) | ||
1508 | # define R300_DEPTHENDIAN_NO_SWAP (0 << 18) | ||
1509 | # define R300_DEPTHENDIAN_WORD_SWAP (1 << 18) | ||
1510 | # define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18) | ||
1511 | # define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18) | ||
1512 | |||
1513 | /* Z Buffer Clear Value */ | ||
1514 | #define R300_ZB_DEPTHCLEARVALUE 0x4f28 | ||
1515 | |||
1516 | #define R300_ZB_ZMASK_OFFSET 0x4f30 | ||
1517 | #define R300_ZB_ZMASK_PITCH 0x4f34 | ||
1518 | #define R300_ZB_ZMASK_WRINDEX 0x4f38 | ||
1519 | #define R300_ZB_ZMASK_DWORD 0x4f3c | ||
1520 | #define R300_ZB_ZMASK_RDINDEX 0x4f40 | ||
1521 | |||
1522 | /* Hierarchical Z Memory Offset */ | ||
1523 | #define R300_ZB_HIZ_OFFSET 0x4f44 | ||
1524 | |||
1525 | /* Hierarchical Z Write Index */ | ||
1526 | #define R300_ZB_HIZ_WRINDEX 0x4f48 | ||
1527 | |||
1528 | /* Hierarchical Z Data */ | ||
1529 | #define R300_ZB_HIZ_DWORD 0x4f4c | ||
1530 | |||
1531 | /* Hierarchical Z Read Index */ | ||
1532 | #define R300_ZB_HIZ_RDINDEX 0x4f50 | ||
1533 | |||
1534 | /* Hierarchical Z Pitch */ | ||
1535 | #define R300_ZB_HIZ_PITCH 0x4f54 | ||
1536 | |||
1537 | /* Z Buffer Z Pass Counter Data */ | ||
1538 | #define R300_ZB_ZPASS_DATA 0x4f58 | ||
1539 | |||
1540 | /* Z Buffer Z Pass Counter Address */ | ||
1541 | #define R300_ZB_ZPASS_ADDR 0x4f5c | ||
1542 | |||
1543 | /* Depth buffer X and Y coordinate offset */ | ||
1544 | #define R300_ZB_DEPTHXY_OFFSET 0x4f60 | ||
1545 | # define R300_DEPTHX_OFFSET_SHIFT 1 | ||
1546 | # define R300_DEPTHX_OFFSET_MASK 0x000007FE | ||
1547 | # define R300_DEPTHY_OFFSET_SHIFT 17 | ||
1548 | # define R300_DEPTHY_OFFSET_MASK 0x07FE0000 | ||
1549 | |||
1550 | /* Sets the fifo sizes */ | ||
1551 | #define R500_ZB_FIFO_SIZE 0x4fd0 | ||
1552 | # define R500_OP_FIFO_SIZE_FULL (0 << 0) | ||
1553 | # define R500_OP_FIFO_SIZE_HALF (1 << 0) | ||
1554 | # define R500_OP_FIFO_SIZE_QUATER (2 << 0) | ||
1555 | # define R500_OP_FIFO_SIZE_EIGTHS (4 << 0) | ||
1556 | |||
1557 | /* Stencil Reference Value and Mask for backfacing quads */ | ||
1558 | /* R300_ZB_STENCILREFMASK handles front face */ | ||
1559 | #define R500_ZB_STENCILREFMASK_BF 0x4fd4 | ||
1560 | # define R500_STENCILREF_SHIFT 0 | ||
1561 | # define R500_STENCILREF_MASK 0x000000ff | ||
1562 | # define R500_STENCILMASK_SHIFT 8 | ||
1563 | # define R500_STENCILMASK_MASK 0x0000ff00 | ||
1564 | # define R500_STENCILWRITEMASK_SHIFT 16 | ||
1565 | # define R500_STENCILWRITEMASK_MASK 0x00ff0000 | ||
1436 | 1566 | ||
1437 | /* BEGIN: Vertex program instruction set */ | 1567 | /* BEGIN: Vertex program instruction set */ |
1438 | 1568 | ||
@@ -1623,4 +1753,20 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. | |||
1623 | */ | 1753 | */ |
1624 | #define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 | 1754 | #define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 |
1625 | 1755 | ||
1756 | #define R500_VAP_INDEX_OFFSET 0x208c | ||
1757 | |||
1758 | #define R500_GA_US_VECTOR_INDEX 0x4250 | ||
1759 | #define R500_GA_US_VECTOR_DATA 0x4254 | ||
1760 | |||
1761 | #define R500_RS_IP_0 0x4074 | ||
1762 | #define R500_RS_INST_0 0x4320 | ||
1763 | |||
1764 | #define R500_US_CONFIG 0x4600 | ||
1765 | |||
1766 | #define R500_US_FC_CTRL 0x4624 | ||
1767 | #define R500_US_CODE_ADDR 0x4630 | ||
1768 | |||
1769 | #define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0 | ||
1770 | #define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 | ||
1771 | |||
1626 | #endif /* _R300_REG_H */ | 1772 | #endif /* _R300_REG_H */ |
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c index f6f6c92bf771..e53158f0ecb5 100644 --- a/drivers/char/drm/radeon_cp.c +++ b/drivers/char/drm/radeon_cp.c | |||
@@ -2,6 +2,7 @@ | |||
2 | /* | 2 | /* |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | 3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | 4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. |
5 | * Copyright 2007 Advanced Micro Devices, Inc. | ||
5 | * All Rights Reserved. | 6 | * All Rights Reserved. |
6 | * | 7 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | 8 | * Permission is hereby granted, free of charge, to any person obtaining a |
@@ -34,789 +35,13 @@ | |||
34 | #include "radeon_drv.h" | 35 | #include "radeon_drv.h" |
35 | #include "r300_reg.h" | 36 | #include "r300_reg.h" |
36 | 37 | ||
38 | #include "radeon_microcode.h" | ||
39 | |||
37 | #define RADEON_FIFO_DEBUG 0 | 40 | #define RADEON_FIFO_DEBUG 0 |
38 | 41 | ||
39 | static int radeon_do_cleanup_cp(struct drm_device * dev); | 42 | static int radeon_do_cleanup_cp(struct drm_device * dev); |
40 | 43 | ||
41 | /* CP microcode (from ATI) */ | 44 | static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
42 | static const u32 R200_cp_microcode[][2] = { | ||
43 | {0x21007000, 0000000000}, | ||
44 | {0x20007000, 0000000000}, | ||
45 | {0x000000ab, 0x00000004}, | ||
46 | {0x000000af, 0x00000004}, | ||
47 | {0x66544a49, 0000000000}, | ||
48 | {0x49494174, 0000000000}, | ||
49 | {0x54517d83, 0000000000}, | ||
50 | {0x498d8b64, 0000000000}, | ||
51 | {0x49494949, 0000000000}, | ||
52 | {0x49da493c, 0000000000}, | ||
53 | {0x49989898, 0000000000}, | ||
54 | {0xd34949d5, 0000000000}, | ||
55 | {0x9dc90e11, 0000000000}, | ||
56 | {0xce9b9b9b, 0000000000}, | ||
57 | {0x000f0000, 0x00000016}, | ||
58 | {0x352e232c, 0000000000}, | ||
59 | {0x00000013, 0x00000004}, | ||
60 | {0x000f0000, 0x00000016}, | ||
61 | {0x352e272c, 0000000000}, | ||
62 | {0x000f0001, 0x00000016}, | ||
63 | {0x3239362f, 0000000000}, | ||
64 | {0x000077ef, 0x00000002}, | ||
65 | {0x00061000, 0x00000002}, | ||
66 | {0x00000020, 0x0000001a}, | ||
67 | {0x00004000, 0x0000001e}, | ||
68 | {0x00061000, 0x00000002}, | ||
69 | {0x00000020, 0x0000001a}, | ||
70 | {0x00004000, 0x0000001e}, | ||
71 | {0x00061000, 0x00000002}, | ||
72 | {0x00000020, 0x0000001a}, | ||
73 | {0x00004000, 0x0000001e}, | ||
74 | {0x00000016, 0x00000004}, | ||
75 | {0x0003802a, 0x00000002}, | ||
76 | {0x040067e0, 0x00000002}, | ||
77 | {0x00000016, 0x00000004}, | ||
78 | {0x000077e0, 0x00000002}, | ||
79 | {0x00065000, 0x00000002}, | ||
80 | {0x000037e1, 0x00000002}, | ||
81 | {0x040067e1, 0x00000006}, | ||
82 | {0x000077e0, 0x00000002}, | ||
83 | {0x000077e1, 0x00000002}, | ||
84 | {0x000077e1, 0x00000006}, | ||
85 | {0xffffffff, 0000000000}, | ||
86 | {0x10000000, 0000000000}, | ||
87 | {0x0003802a, 0x00000002}, | ||
88 | {0x040067e0, 0x00000006}, | ||
89 | {0x00007675, 0x00000002}, | ||
90 | {0x00007676, 0x00000002}, | ||
91 | {0x00007677, 0x00000002}, | ||
92 | {0x00007678, 0x00000006}, | ||
93 | {0x0003802b, 0x00000002}, | ||
94 | {0x04002676, 0x00000002}, | ||
95 | {0x00007677, 0x00000002}, | ||
96 | {0x00007678, 0x00000006}, | ||
97 | {0x0000002e, 0x00000018}, | ||
98 | {0x0000002e, 0x00000018}, | ||
99 | {0000000000, 0x00000006}, | ||
100 | {0x0000002f, 0x00000018}, | ||
101 | {0x0000002f, 0x00000018}, | ||
102 | {0000000000, 0x00000006}, | ||
103 | {0x01605000, 0x00000002}, | ||
104 | {0x00065000, 0x00000002}, | ||
105 | {0x00098000, 0x00000002}, | ||
106 | {0x00061000, 0x00000002}, | ||
107 | {0x64c0603d, 0x00000004}, | ||
108 | {0x00080000, 0x00000016}, | ||
109 | {0000000000, 0000000000}, | ||
110 | {0x0400251d, 0x00000002}, | ||
111 | {0x00007580, 0x00000002}, | ||
112 | {0x00067581, 0x00000002}, | ||
113 | {0x04002580, 0x00000002}, | ||
114 | {0x00067581, 0x00000002}, | ||
115 | {0x00000046, 0x00000004}, | ||
116 | {0x00005000, 0000000000}, | ||
117 | {0x00061000, 0x00000002}, | ||
118 | {0x0000750e, 0x00000002}, | ||
119 | {0x00019000, 0x00000002}, | ||
120 | {0x00011055, 0x00000014}, | ||
121 | {0x00000055, 0x00000012}, | ||
122 | {0x0400250f, 0x00000002}, | ||
123 | {0x0000504a, 0x00000004}, | ||
124 | {0x00007565, 0x00000002}, | ||
125 | {0x00007566, 0x00000002}, | ||
126 | {0x00000051, 0x00000004}, | ||
127 | {0x01e655b4, 0x00000002}, | ||
128 | {0x4401b0dc, 0x00000002}, | ||
129 | {0x01c110dc, 0x00000002}, | ||
130 | {0x2666705d, 0x00000018}, | ||
131 | {0x040c2565, 0x00000002}, | ||
132 | {0x0000005d, 0x00000018}, | ||
133 | {0x04002564, 0x00000002}, | ||
134 | {0x00007566, 0x00000002}, | ||
135 | {0x00000054, 0x00000004}, | ||
136 | {0x00401060, 0x00000008}, | ||
137 | {0x00101000, 0x00000002}, | ||
138 | {0x000d80ff, 0x00000002}, | ||
139 | {0x00800063, 0x00000008}, | ||
140 | {0x000f9000, 0x00000002}, | ||
141 | {0x000e00ff, 0x00000002}, | ||
142 | {0000000000, 0x00000006}, | ||
143 | {0x00000080, 0x00000018}, | ||
144 | {0x00000054, 0x00000004}, | ||
145 | {0x00007576, 0x00000002}, | ||
146 | {0x00065000, 0x00000002}, | ||
147 | {0x00009000, 0x00000002}, | ||
148 | {0x00041000, 0x00000002}, | ||
149 | {0x0c00350e, 0x00000002}, | ||
150 | {0x00049000, 0x00000002}, | ||
151 | {0x00051000, 0x00000002}, | ||
152 | {0x01e785f8, 0x00000002}, | ||
153 | {0x00200000, 0x00000002}, | ||
154 | {0x00600073, 0x0000000c}, | ||
155 | {0x00007563, 0x00000002}, | ||
156 | {0x006075f0, 0x00000021}, | ||
157 | {0x20007068, 0x00000004}, | ||
158 | {0x00005068, 0x00000004}, | ||
159 | {0x00007576, 0x00000002}, | ||
160 | {0x00007577, 0x00000002}, | ||
161 | {0x0000750e, 0x00000002}, | ||
162 | {0x0000750f, 0x00000002}, | ||
163 | {0x00a05000, 0x00000002}, | ||
164 | {0x00600076, 0x0000000c}, | ||
165 | {0x006075f0, 0x00000021}, | ||
166 | {0x000075f8, 0x00000002}, | ||
167 | {0x00000076, 0x00000004}, | ||
168 | {0x000a750e, 0x00000002}, | ||
169 | {0x0020750f, 0x00000002}, | ||
170 | {0x00600079, 0x00000004}, | ||
171 | {0x00007570, 0x00000002}, | ||
172 | {0x00007571, 0x00000002}, | ||
173 | {0x00007572, 0x00000006}, | ||
174 | {0x00005000, 0x00000002}, | ||
175 | {0x00a05000, 0x00000002}, | ||
176 | {0x00007568, 0x00000002}, | ||
177 | {0x00061000, 0x00000002}, | ||
178 | {0x00000084, 0x0000000c}, | ||
179 | {0x00058000, 0x00000002}, | ||
180 | {0x0c607562, 0x00000002}, | ||
181 | {0x00000086, 0x00000004}, | ||
182 | {0x00600085, 0x00000004}, | ||
183 | {0x400070dd, 0000000000}, | ||
184 | {0x000380dd, 0x00000002}, | ||
185 | {0x00000093, 0x0000001c}, | ||
186 | {0x00065095, 0x00000018}, | ||
187 | {0x040025bb, 0x00000002}, | ||
188 | {0x00061096, 0x00000018}, | ||
189 | {0x040075bc, 0000000000}, | ||
190 | {0x000075bb, 0x00000002}, | ||
191 | {0x000075bc, 0000000000}, | ||
192 | {0x00090000, 0x00000006}, | ||
193 | {0x00090000, 0x00000002}, | ||
194 | {0x000d8002, 0x00000006}, | ||
195 | {0x00005000, 0x00000002}, | ||
196 | {0x00007821, 0x00000002}, | ||
197 | {0x00007800, 0000000000}, | ||
198 | {0x00007821, 0x00000002}, | ||
199 | {0x00007800, 0000000000}, | ||
200 | {0x01665000, 0x00000002}, | ||
201 | {0x000a0000, 0x00000002}, | ||
202 | {0x000671cc, 0x00000002}, | ||
203 | {0x0286f1cd, 0x00000002}, | ||
204 | {0x000000a3, 0x00000010}, | ||
205 | {0x21007000, 0000000000}, | ||
206 | {0x000000aa, 0x0000001c}, | ||
207 | {0x00065000, 0x00000002}, | ||
208 | {0x000a0000, 0x00000002}, | ||
209 | {0x00061000, 0x00000002}, | ||
210 | {0x000b0000, 0x00000002}, | ||
211 | {0x38067000, 0x00000002}, | ||
212 | {0x000a00a6, 0x00000004}, | ||
213 | {0x20007000, 0000000000}, | ||
214 | {0x01200000, 0x00000002}, | ||
215 | {0x20077000, 0x00000002}, | ||
216 | {0x01200000, 0x00000002}, | ||
217 | {0x20007000, 0000000000}, | ||
218 | {0x00061000, 0x00000002}, | ||
219 | {0x0120751b, 0x00000002}, | ||
220 | {0x8040750a, 0x00000002}, | ||
221 | {0x8040750b, 0x00000002}, | ||
222 | {0x00110000, 0x00000002}, | ||
223 | {0x000380dd, 0x00000002}, | ||
224 | {0x000000bd, 0x0000001c}, | ||
225 | {0x00061096, 0x00000018}, | ||
226 | {0x844075bd, 0x00000002}, | ||
227 | {0x00061095, 0x00000018}, | ||
228 | {0x840075bb, 0x00000002}, | ||
229 | {0x00061096, 0x00000018}, | ||
230 | {0x844075bc, 0x00000002}, | ||
231 | {0x000000c0, 0x00000004}, | ||
232 | {0x804075bd, 0x00000002}, | ||
233 | {0x800075bb, 0x00000002}, | ||
234 | {0x804075bc, 0x00000002}, | ||
235 | {0x00108000, 0x00000002}, | ||
236 | {0x01400000, 0x00000002}, | ||
237 | {0x006000c4, 0x0000000c}, | ||
238 | {0x20c07000, 0x00000020}, | ||
239 | {0x000000c6, 0x00000012}, | ||
240 | {0x00800000, 0x00000006}, | ||
241 | {0x0080751d, 0x00000006}, | ||
242 | {0x000025bb, 0x00000002}, | ||
243 | {0x000040c0, 0x00000004}, | ||
244 | {0x0000775c, 0x00000002}, | ||
245 | {0x00a05000, 0x00000002}, | ||
246 | {0x00661000, 0x00000002}, | ||
247 | {0x0460275d, 0x00000020}, | ||
248 | {0x00004000, 0000000000}, | ||
249 | {0x00007999, 0x00000002}, | ||
250 | {0x00a05000, 0x00000002}, | ||
251 | {0x00661000, 0x00000002}, | ||
252 | {0x0460299b, 0x00000020}, | ||
253 | {0x00004000, 0000000000}, | ||
254 | {0x01e00830, 0x00000002}, | ||
255 | {0x21007000, 0000000000}, | ||
256 | {0x00005000, 0x00000002}, | ||
257 | {0x00038042, 0x00000002}, | ||
258 | {0x040025e0, 0x00000002}, | ||
259 | {0x000075e1, 0000000000}, | ||
260 | {0x00000001, 0000000000}, | ||
261 | {0x000380d9, 0x00000002}, | ||
262 | {0x04007394, 0000000000}, | ||
263 | {0000000000, 0000000000}, | ||
264 | {0000000000, 0000000000}, | ||
265 | {0000000000, 0000000000}, | ||
266 | {0000000000, 0000000000}, | ||
267 | {0000000000, 0000000000}, | ||
268 | {0000000000, 0000000000}, | ||
269 | {0000000000, 0000000000}, | ||
270 | {0000000000, 0000000000}, | ||
271 | {0000000000, 0000000000}, | ||
272 | {0000000000, 0000000000}, | ||
273 | {0000000000, 0000000000}, | ||
274 | {0000000000, 0000000000}, | ||
275 | {0000000000, 0000000000}, | ||
276 | {0000000000, 0000000000}, | ||
277 | {0000000000, 0000000000}, | ||
278 | {0000000000, 0000000000}, | ||
279 | {0000000000, 0000000000}, | ||
280 | {0000000000, 0000000000}, | ||
281 | {0000000000, 0000000000}, | ||
282 | {0000000000, 0000000000}, | ||
283 | {0000000000, 0000000000}, | ||
284 | {0000000000, 0000000000}, | ||
285 | {0000000000, 0000000000}, | ||
286 | {0000000000, 0000000000}, | ||
287 | {0000000000, 0000000000}, | ||
288 | {0000000000, 0000000000}, | ||
289 | {0000000000, 0000000000}, | ||
290 | {0000000000, 0000000000}, | ||
291 | {0000000000, 0000000000}, | ||
292 | {0000000000, 0000000000}, | ||
293 | {0000000000, 0000000000}, | ||
294 | {0000000000, 0000000000}, | ||
295 | {0000000000, 0000000000}, | ||
296 | {0000000000, 0000000000}, | ||
297 | {0000000000, 0000000000}, | ||
298 | {0000000000, 0000000000}, | ||
299 | }; | ||
300 | |||
301 | static const u32 radeon_cp_microcode[][2] = { | ||
302 | {0x21007000, 0000000000}, | ||
303 | {0x20007000, 0000000000}, | ||
304 | {0x000000b4, 0x00000004}, | ||
305 | {0x000000b8, 0x00000004}, | ||
306 | {0x6f5b4d4c, 0000000000}, | ||
307 | {0x4c4c427f, 0000000000}, | ||
308 | {0x5b568a92, 0000000000}, | ||
309 | {0x4ca09c6d, 0000000000}, | ||
310 | {0xad4c4c4c, 0000000000}, | ||
311 | {0x4ce1af3d, 0000000000}, | ||
312 | {0xd8afafaf, 0000000000}, | ||
313 | {0xd64c4cdc, 0000000000}, | ||
314 | {0x4cd10d10, 0000000000}, | ||
315 | {0x000f0000, 0x00000016}, | ||
316 | {0x362f242d, 0000000000}, | ||
317 | {0x00000012, 0x00000004}, | ||
318 | {0x000f0000, 0x00000016}, | ||
319 | {0x362f282d, 0000000000}, | ||
320 | {0x000380e7, 0x00000002}, | ||
321 | {0x04002c97, 0x00000002}, | ||
322 | {0x000f0001, 0x00000016}, | ||
323 | {0x333a3730, 0000000000}, | ||
324 | {0x000077ef, 0x00000002}, | ||
325 | {0x00061000, 0x00000002}, | ||
326 | {0x00000021, 0x0000001a}, | ||
327 | {0x00004000, 0x0000001e}, | ||
328 | {0x00061000, 0x00000002}, | ||
329 | {0x00000021, 0x0000001a}, | ||
330 | {0x00004000, 0x0000001e}, | ||
331 | {0x00061000, 0x00000002}, | ||
332 | {0x00000021, 0x0000001a}, | ||
333 | {0x00004000, 0x0000001e}, | ||
334 | {0x00000017, 0x00000004}, | ||
335 | {0x0003802b, 0x00000002}, | ||
336 | {0x040067e0, 0x00000002}, | ||
337 | {0x00000017, 0x00000004}, | ||
338 | {0x000077e0, 0x00000002}, | ||
339 | {0x00065000, 0x00000002}, | ||
340 | {0x000037e1, 0x00000002}, | ||
341 | {0x040067e1, 0x00000006}, | ||
342 | {0x000077e0, 0x00000002}, | ||
343 | {0x000077e1, 0x00000002}, | ||
344 | {0x000077e1, 0x00000006}, | ||
345 | {0xffffffff, 0000000000}, | ||
346 | {0x10000000, 0000000000}, | ||
347 | {0x0003802b, 0x00000002}, | ||
348 | {0x040067e0, 0x00000006}, | ||
349 | {0x00007675, 0x00000002}, | ||
350 | {0x00007676, 0x00000002}, | ||
351 | {0x00007677, 0x00000002}, | ||
352 | {0x00007678, 0x00000006}, | ||
353 | {0x0003802c, 0x00000002}, | ||
354 | {0x04002676, 0x00000002}, | ||
355 | {0x00007677, 0x00000002}, | ||
356 | {0x00007678, 0x00000006}, | ||
357 | {0x0000002f, 0x00000018}, | ||
358 | {0x0000002f, 0x00000018}, | ||
359 | {0000000000, 0x00000006}, | ||
360 | {0x00000030, 0x00000018}, | ||
361 | {0x00000030, 0x00000018}, | ||
362 | {0000000000, 0x00000006}, | ||
363 | {0x01605000, 0x00000002}, | ||
364 | {0x00065000, 0x00000002}, | ||
365 | {0x00098000, 0x00000002}, | ||
366 | {0x00061000, 0x00000002}, | ||
367 | {0x64c0603e, 0x00000004}, | ||
368 | {0x000380e6, 0x00000002}, | ||
369 | {0x040025c5, 0x00000002}, | ||
370 | {0x00080000, 0x00000016}, | ||
371 | {0000000000, 0000000000}, | ||
372 | {0x0400251d, 0x00000002}, | ||
373 | {0x00007580, 0x00000002}, | ||
374 | {0x00067581, 0x00000002}, | ||
375 | {0x04002580, 0x00000002}, | ||
376 | {0x00067581, 0x00000002}, | ||
377 | {0x00000049, 0x00000004}, | ||
378 | {0x00005000, 0000000000}, | ||
379 | {0x000380e6, 0x00000002}, | ||
380 | {0x040025c5, 0x00000002}, | ||
381 | {0x00061000, 0x00000002}, | ||
382 | {0x0000750e, 0x00000002}, | ||
383 | {0x00019000, 0x00000002}, | ||
384 | {0x00011055, 0x00000014}, | ||
385 | {0x00000055, 0x00000012}, | ||
386 | {0x0400250f, 0x00000002}, | ||
387 | {0x0000504f, 0x00000004}, | ||
388 | {0x000380e6, 0x00000002}, | ||
389 | {0x040025c5, 0x00000002}, | ||
390 | {0x00007565, 0x00000002}, | ||
391 | {0x00007566, 0x00000002}, | ||
392 | {0x00000058, 0x00000004}, | ||
393 | {0x000380e6, 0x00000002}, | ||
394 | {0x040025c5, 0x00000002}, | ||
395 | {0x01e655b4, 0x00000002}, | ||
396 | {0x4401b0e4, 0x00000002}, | ||
397 | {0x01c110e4, 0x00000002}, | ||
398 | {0x26667066, 0x00000018}, | ||
399 | {0x040c2565, 0x00000002}, | ||
400 | {0x00000066, 0x00000018}, | ||
401 | {0x04002564, 0x00000002}, | ||
402 | {0x00007566, 0x00000002}, | ||
403 | {0x0000005d, 0x00000004}, | ||
404 | {0x00401069, 0x00000008}, | ||
405 | {0x00101000, 0x00000002}, | ||
406 | {0x000d80ff, 0x00000002}, | ||
407 | {0x0080006c, 0x00000008}, | ||
408 | {0x000f9000, 0x00000002}, | ||
409 | {0x000e00ff, 0x00000002}, | ||
410 | {0000000000, 0x00000006}, | ||
411 | {0x0000008f, 0x00000018}, | ||
412 | {0x0000005b, 0x00000004}, | ||
413 | {0x000380e6, 0x00000002}, | ||
414 | {0x040025c5, 0x00000002}, | ||
415 | {0x00007576, 0x00000002}, | ||
416 | {0x00065000, 0x00000002}, | ||
417 | {0x00009000, 0x00000002}, | ||
418 | {0x00041000, 0x00000002}, | ||
419 | {0x0c00350e, 0x00000002}, | ||
420 | {0x00049000, 0x00000002}, | ||
421 | {0x00051000, 0x00000002}, | ||
422 | {0x01e785f8, 0x00000002}, | ||
423 | {0x00200000, 0x00000002}, | ||
424 | {0x0060007e, 0x0000000c}, | ||
425 | {0x00007563, 0x00000002}, | ||
426 | {0x006075f0, 0x00000021}, | ||
427 | {0x20007073, 0x00000004}, | ||
428 | {0x00005073, 0x00000004}, | ||
429 | {0x000380e6, 0x00000002}, | ||
430 | {0x040025c5, 0x00000002}, | ||
431 | {0x00007576, 0x00000002}, | ||
432 | {0x00007577, 0x00000002}, | ||
433 | {0x0000750e, 0x00000002}, | ||
434 | {0x0000750f, 0x00000002}, | ||
435 | {0x00a05000, 0x00000002}, | ||
436 | {0x00600083, 0x0000000c}, | ||
437 | {0x006075f0, 0x00000021}, | ||
438 | {0x000075f8, 0x00000002}, | ||
439 | {0x00000083, 0x00000004}, | ||
440 | {0x000a750e, 0x00000002}, | ||
441 | {0x000380e6, 0x00000002}, | ||
442 | {0x040025c5, 0x00000002}, | ||
443 | {0x0020750f, 0x00000002}, | ||
444 | {0x00600086, 0x00000004}, | ||
445 | {0x00007570, 0x00000002}, | ||
446 | {0x00007571, 0x00000002}, | ||
447 | {0x00007572, 0x00000006}, | ||
448 | {0x000380e6, 0x00000002}, | ||
449 | {0x040025c5, 0x00000002}, | ||
450 | {0x00005000, 0x00000002}, | ||
451 | {0x00a05000, 0x00000002}, | ||
452 | {0x00007568, 0x00000002}, | ||
453 | {0x00061000, 0x00000002}, | ||
454 | {0x00000095, 0x0000000c}, | ||
455 | {0x00058000, 0x00000002}, | ||
456 | {0x0c607562, 0x00000002}, | ||
457 | {0x00000097, 0x00000004}, | ||
458 | {0x000380e6, 0x00000002}, | ||
459 | {0x040025c5, 0x00000002}, | ||
460 | {0x00600096, 0x00000004}, | ||
461 | {0x400070e5, 0000000000}, | ||
462 | {0x000380e6, 0x00000002}, | ||
463 | {0x040025c5, 0x00000002}, | ||
464 | {0x000380e5, 0x00000002}, | ||
465 | {0x000000a8, 0x0000001c}, | ||
466 | {0x000650aa, 0x00000018}, | ||
467 | {0x040025bb, 0x00000002}, | ||
468 | {0x000610ab, 0x00000018}, | ||
469 | {0x040075bc, 0000000000}, | ||
470 | {0x000075bb, 0x00000002}, | ||
471 | {0x000075bc, 0000000000}, | ||
472 | {0x00090000, 0x00000006}, | ||
473 | {0x00090000, 0x00000002}, | ||
474 | {0x000d8002, 0x00000006}, | ||
475 | {0x00007832, 0x00000002}, | ||
476 | {0x00005000, 0x00000002}, | ||
477 | {0x000380e7, 0x00000002}, | ||
478 | {0x04002c97, 0x00000002}, | ||
479 | {0x00007820, 0x00000002}, | ||
480 | {0x00007821, 0x00000002}, | ||
481 | {0x00007800, 0000000000}, | ||
482 | {0x01200000, 0x00000002}, | ||
483 | {0x20077000, 0x00000002}, | ||
484 | {0x01200000, 0x00000002}, | ||
485 | {0x20007000, 0x00000002}, | ||
486 | {0x00061000, 0x00000002}, | ||
487 | {0x0120751b, 0x00000002}, | ||
488 | {0x8040750a, 0x00000002}, | ||
489 | {0x8040750b, 0x00000002}, | ||
490 | {0x00110000, 0x00000002}, | ||
491 | {0x000380e5, 0x00000002}, | ||
492 | {0x000000c6, 0x0000001c}, | ||
493 | {0x000610ab, 0x00000018}, | ||
494 | {0x844075bd, 0x00000002}, | ||
495 | {0x000610aa, 0x00000018}, | ||
496 | {0x840075bb, 0x00000002}, | ||
497 | {0x000610ab, 0x00000018}, | ||
498 | {0x844075bc, 0x00000002}, | ||
499 | {0x000000c9, 0x00000004}, | ||
500 | {0x804075bd, 0x00000002}, | ||
501 | {0x800075bb, 0x00000002}, | ||
502 | {0x804075bc, 0x00000002}, | ||
503 | {0x00108000, 0x00000002}, | ||
504 | {0x01400000, 0x00000002}, | ||
505 | {0x006000cd, 0x0000000c}, | ||
506 | {0x20c07000, 0x00000020}, | ||
507 | {0x000000cf, 0x00000012}, | ||
508 | {0x00800000, 0x00000006}, | ||
509 | {0x0080751d, 0x00000006}, | ||
510 | {0000000000, 0000000000}, | ||
511 | {0x0000775c, 0x00000002}, | ||
512 | {0x00a05000, 0x00000002}, | ||
513 | {0x00661000, 0x00000002}, | ||
514 | {0x0460275d, 0x00000020}, | ||
515 | {0x00004000, 0000000000}, | ||
516 | {0x01e00830, 0x00000002}, | ||
517 | {0x21007000, 0000000000}, | ||
518 | {0x6464614d, 0000000000}, | ||
519 | {0x69687420, 0000000000}, | ||
520 | {0x00000073, 0000000000}, | ||
521 | {0000000000, 0000000000}, | ||
522 | {0x00005000, 0x00000002}, | ||
523 | {0x000380d0, 0x00000002}, | ||
524 | {0x040025e0, 0x00000002}, | ||
525 | {0x000075e1, 0000000000}, | ||
526 | {0x00000001, 0000000000}, | ||
527 | {0x000380e0, 0x00000002}, | ||
528 | {0x04002394, 0x00000002}, | ||
529 | {0x00005000, 0000000000}, | ||
530 | {0000000000, 0000000000}, | ||
531 | {0000000000, 0000000000}, | ||
532 | {0x00000008, 0000000000}, | ||
533 | {0x00000004, 0000000000}, | ||
534 | {0000000000, 0000000000}, | ||
535 | {0000000000, 0000000000}, | ||
536 | {0000000000, 0000000000}, | ||
537 | {0000000000, 0000000000}, | ||
538 | {0000000000, 0000000000}, | ||
539 | {0000000000, 0000000000}, | ||
540 | {0000000000, 0000000000}, | ||
541 | {0000000000, 0000000000}, | ||
542 | {0000000000, 0000000000}, | ||
543 | {0000000000, 0000000000}, | ||
544 | {0000000000, 0000000000}, | ||
545 | {0000000000, 0000000000}, | ||
546 | {0000000000, 0000000000}, | ||
547 | {0000000000, 0000000000}, | ||
548 | {0000000000, 0000000000}, | ||
549 | {0000000000, 0000000000}, | ||
550 | {0000000000, 0000000000}, | ||
551 | {0000000000, 0000000000}, | ||
552 | {0000000000, 0000000000}, | ||
553 | {0000000000, 0000000000}, | ||
554 | {0000000000, 0000000000}, | ||
555 | {0000000000, 0000000000}, | ||
556 | {0000000000, 0000000000}, | ||
557 | {0000000000, 0000000000}, | ||
558 | }; | ||
559 | |||
560 | static const u32 R300_cp_microcode[][2] = { | ||
561 | {0x4200e000, 0000000000}, | ||
562 | {0x4000e000, 0000000000}, | ||
563 | {0x000000af, 0x00000008}, | ||
564 | {0x000000b3, 0x00000008}, | ||
565 | {0x6c5a504f, 0000000000}, | ||
566 | {0x4f4f497a, 0000000000}, | ||
567 | {0x5a578288, 0000000000}, | ||
568 | {0x4f91906a, 0000000000}, | ||
569 | {0x4f4f4f4f, 0000000000}, | ||
570 | {0x4fe24f44, 0000000000}, | ||
571 | {0x4f9c9c9c, 0000000000}, | ||
572 | {0xdc4f4fde, 0000000000}, | ||
573 | {0xa1cd4f4f, 0000000000}, | ||
574 | {0xd29d9d9d, 0000000000}, | ||
575 | {0x4f0f9fd7, 0000000000}, | ||
576 | {0x000ca000, 0x00000004}, | ||
577 | {0x000d0012, 0x00000038}, | ||
578 | {0x0000e8b4, 0x00000004}, | ||
579 | {0x000d0014, 0x00000038}, | ||
580 | {0x0000e8b6, 0x00000004}, | ||
581 | {0x000d0016, 0x00000038}, | ||
582 | {0x0000e854, 0x00000004}, | ||
583 | {0x000d0018, 0x00000038}, | ||
584 | {0x0000e855, 0x00000004}, | ||
585 | {0x000d001a, 0x00000038}, | ||
586 | {0x0000e856, 0x00000004}, | ||
587 | {0x000d001c, 0x00000038}, | ||
588 | {0x0000e857, 0x00000004}, | ||
589 | {0x000d001e, 0x00000038}, | ||
590 | {0x0000e824, 0x00000004}, | ||
591 | {0x000d0020, 0x00000038}, | ||
592 | {0x0000e825, 0x00000004}, | ||
593 | {0x000d0022, 0x00000038}, | ||
594 | {0x0000e830, 0x00000004}, | ||
595 | {0x000d0024, 0x00000038}, | ||
596 | {0x0000f0c0, 0x00000004}, | ||
597 | {0x000d0026, 0x00000038}, | ||
598 | {0x0000f0c1, 0x00000004}, | ||
599 | {0x000d0028, 0x00000038}, | ||
600 | {0x0000f041, 0x00000004}, | ||
601 | {0x000d002a, 0x00000038}, | ||
602 | {0x0000f184, 0x00000004}, | ||
603 | {0x000d002c, 0x00000038}, | ||
604 | {0x0000f185, 0x00000004}, | ||
605 | {0x000d002e, 0x00000038}, | ||
606 | {0x0000f186, 0x00000004}, | ||
607 | {0x000d0030, 0x00000038}, | ||
608 | {0x0000f187, 0x00000004}, | ||
609 | {0x000d0032, 0x00000038}, | ||
610 | {0x0000f180, 0x00000004}, | ||
611 | {0x000d0034, 0x00000038}, | ||
612 | {0x0000f393, 0x00000004}, | ||
613 | {0x000d0036, 0x00000038}, | ||
614 | {0x0000f38a, 0x00000004}, | ||
615 | {0x000d0038, 0x00000038}, | ||
616 | {0x0000f38e, 0x00000004}, | ||
617 | {0x0000e821, 0x00000004}, | ||
618 | {0x0140a000, 0x00000004}, | ||
619 | {0x00000043, 0x00000018}, | ||
620 | {0x00cce800, 0x00000004}, | ||
621 | {0x001b0001, 0x00000004}, | ||
622 | {0x08004800, 0x00000004}, | ||
623 | {0x001b0001, 0x00000004}, | ||
624 | {0x08004800, 0x00000004}, | ||
625 | {0x001b0001, 0x00000004}, | ||
626 | {0x08004800, 0x00000004}, | ||
627 | {0x0000003a, 0x00000008}, | ||
628 | {0x0000a000, 0000000000}, | ||
629 | {0x02c0a000, 0x00000004}, | ||
630 | {0x000ca000, 0x00000004}, | ||
631 | {0x00130000, 0x00000004}, | ||
632 | {0x000c2000, 0x00000004}, | ||
633 | {0xc980c045, 0x00000008}, | ||
634 | {0x2000451d, 0x00000004}, | ||
635 | {0x0000e580, 0x00000004}, | ||
636 | {0x000ce581, 0x00000004}, | ||
637 | {0x08004580, 0x00000004}, | ||
638 | {0x000ce581, 0x00000004}, | ||
639 | {0x0000004c, 0x00000008}, | ||
640 | {0x0000a000, 0000000000}, | ||
641 | {0x000c2000, 0x00000004}, | ||
642 | {0x0000e50e, 0x00000004}, | ||
643 | {0x00032000, 0x00000004}, | ||
644 | {0x00022056, 0x00000028}, | ||
645 | {0x00000056, 0x00000024}, | ||
646 | {0x0800450f, 0x00000004}, | ||
647 | {0x0000a050, 0x00000008}, | ||
648 | {0x0000e565, 0x00000004}, | ||
649 | {0x0000e566, 0x00000004}, | ||
650 | {0x00000057, 0x00000008}, | ||
651 | {0x03cca5b4, 0x00000004}, | ||
652 | {0x05432000, 0x00000004}, | ||
653 | {0x00022000, 0x00000004}, | ||
654 | {0x4ccce063, 0x00000030}, | ||
655 | {0x08274565, 0x00000004}, | ||
656 | {0x00000063, 0x00000030}, | ||
657 | {0x08004564, 0x00000004}, | ||
658 | {0x0000e566, 0x00000004}, | ||
659 | {0x0000005a, 0x00000008}, | ||
660 | {0x00802066, 0x00000010}, | ||
661 | {0x00202000, 0x00000004}, | ||
662 | {0x001b00ff, 0x00000004}, | ||
663 | {0x01000069, 0x00000010}, | ||
664 | {0x001f2000, 0x00000004}, | ||
665 | {0x001c00ff, 0x00000004}, | ||
666 | {0000000000, 0x0000000c}, | ||
667 | {0x00000085, 0x00000030}, | ||
668 | {0x0000005a, 0x00000008}, | ||
669 | {0x0000e576, 0x00000004}, | ||
670 | {0x000ca000, 0x00000004}, | ||
671 | {0x00012000, 0x00000004}, | ||
672 | {0x00082000, 0x00000004}, | ||
673 | {0x1800650e, 0x00000004}, | ||
674 | {0x00092000, 0x00000004}, | ||
675 | {0x000a2000, 0x00000004}, | ||
676 | {0x000f0000, 0x00000004}, | ||
677 | {0x00400000, 0x00000004}, | ||
678 | {0x00000079, 0x00000018}, | ||
679 | {0x0000e563, 0x00000004}, | ||
680 | {0x00c0e5f9, 0x000000c2}, | ||
681 | {0x0000006e, 0x00000008}, | ||
682 | {0x0000a06e, 0x00000008}, | ||
683 | {0x0000e576, 0x00000004}, | ||
684 | {0x0000e577, 0x00000004}, | ||
685 | {0x0000e50e, 0x00000004}, | ||
686 | {0x0000e50f, 0x00000004}, | ||
687 | {0x0140a000, 0x00000004}, | ||
688 | {0x0000007c, 0x00000018}, | ||
689 | {0x00c0e5f9, 0x000000c2}, | ||
690 | {0x0000007c, 0x00000008}, | ||
691 | {0x0014e50e, 0x00000004}, | ||
692 | {0x0040e50f, 0x00000004}, | ||
693 | {0x00c0007f, 0x00000008}, | ||
694 | {0x0000e570, 0x00000004}, | ||
695 | {0x0000e571, 0x00000004}, | ||
696 | {0x0000e572, 0x0000000c}, | ||
697 | {0x0000a000, 0x00000004}, | ||
698 | {0x0140a000, 0x00000004}, | ||
699 | {0x0000e568, 0x00000004}, | ||
700 | {0x000c2000, 0x00000004}, | ||
701 | {0x00000089, 0x00000018}, | ||
702 | {0x000b0000, 0x00000004}, | ||
703 | {0x18c0e562, 0x00000004}, | ||
704 | {0x0000008b, 0x00000008}, | ||
705 | {0x00c0008a, 0x00000008}, | ||
706 | {0x000700e4, 0x00000004}, | ||
707 | {0x00000097, 0x00000038}, | ||
708 | {0x000ca099, 0x00000030}, | ||
709 | {0x080045bb, 0x00000004}, | ||
710 | {0x000c209a, 0x00000030}, | ||
711 | {0x0800e5bc, 0000000000}, | ||
712 | {0x0000e5bb, 0x00000004}, | ||
713 | {0x0000e5bc, 0000000000}, | ||
714 | {0x00120000, 0x0000000c}, | ||
715 | {0x00120000, 0x00000004}, | ||
716 | {0x001b0002, 0x0000000c}, | ||
717 | {0x0000a000, 0x00000004}, | ||
718 | {0x0000e821, 0x00000004}, | ||
719 | {0x0000e800, 0000000000}, | ||
720 | {0x0000e821, 0x00000004}, | ||
721 | {0x0000e82e, 0000000000}, | ||
722 | {0x02cca000, 0x00000004}, | ||
723 | {0x00140000, 0x00000004}, | ||
724 | {0x000ce1cc, 0x00000004}, | ||
725 | {0x050de1cd, 0x00000004}, | ||
726 | {0x000000a7, 0x00000020}, | ||
727 | {0x4200e000, 0000000000}, | ||
728 | {0x000000ae, 0x00000038}, | ||
729 | {0x000ca000, 0x00000004}, | ||
730 | {0x00140000, 0x00000004}, | ||
731 | {0x000c2000, 0x00000004}, | ||
732 | {0x00160000, 0x00000004}, | ||
733 | {0x700ce000, 0x00000004}, | ||
734 | {0x001400aa, 0x00000008}, | ||
735 | {0x4000e000, 0000000000}, | ||
736 | {0x02400000, 0x00000004}, | ||
737 | {0x400ee000, 0x00000004}, | ||
738 | {0x02400000, 0x00000004}, | ||
739 | {0x4000e000, 0000000000}, | ||
740 | {0x000c2000, 0x00000004}, | ||
741 | {0x0240e51b, 0x00000004}, | ||
742 | {0x0080e50a, 0x00000005}, | ||
743 | {0x0080e50b, 0x00000005}, | ||
744 | {0x00220000, 0x00000004}, | ||
745 | {0x000700e4, 0x00000004}, | ||
746 | {0x000000c1, 0x00000038}, | ||
747 | {0x000c209a, 0x00000030}, | ||
748 | {0x0880e5bd, 0x00000005}, | ||
749 | {0x000c2099, 0x00000030}, | ||
750 | {0x0800e5bb, 0x00000005}, | ||
751 | {0x000c209a, 0x00000030}, | ||
752 | {0x0880e5bc, 0x00000005}, | ||
753 | {0x000000c4, 0x00000008}, | ||
754 | {0x0080e5bd, 0x00000005}, | ||
755 | {0x0000e5bb, 0x00000005}, | ||
756 | {0x0080e5bc, 0x00000005}, | ||
757 | {0x00210000, 0x00000004}, | ||
758 | {0x02800000, 0x00000004}, | ||
759 | {0x00c000c8, 0x00000018}, | ||
760 | {0x4180e000, 0x00000040}, | ||
761 | {0x000000ca, 0x00000024}, | ||
762 | {0x01000000, 0x0000000c}, | ||
763 | {0x0100e51d, 0x0000000c}, | ||
764 | {0x000045bb, 0x00000004}, | ||
765 | {0x000080c4, 0x00000008}, | ||
766 | {0x0000f3ce, 0x00000004}, | ||
767 | {0x0140a000, 0x00000004}, | ||
768 | {0x00cc2000, 0x00000004}, | ||
769 | {0x08c053cf, 0x00000040}, | ||
770 | {0x00008000, 0000000000}, | ||
771 | {0x0000f3d2, 0x00000004}, | ||
772 | {0x0140a000, 0x00000004}, | ||
773 | {0x00cc2000, 0x00000004}, | ||
774 | {0x08c053d3, 0x00000040}, | ||
775 | {0x00008000, 0000000000}, | ||
776 | {0x0000f39d, 0x00000004}, | ||
777 | {0x0140a000, 0x00000004}, | ||
778 | {0x00cc2000, 0x00000004}, | ||
779 | {0x08c0539e, 0x00000040}, | ||
780 | {0x00008000, 0000000000}, | ||
781 | {0x03c00830, 0x00000004}, | ||
782 | {0x4200e000, 0000000000}, | ||
783 | {0x0000a000, 0x00000004}, | ||
784 | {0x200045e0, 0x00000004}, | ||
785 | {0x0000e5e1, 0000000000}, | ||
786 | {0x00000001, 0000000000}, | ||
787 | {0x000700e1, 0x00000004}, | ||
788 | {0x0800e394, 0000000000}, | ||
789 | {0000000000, 0000000000}, | ||
790 | {0000000000, 0000000000}, | ||
791 | {0000000000, 0000000000}, | ||
792 | {0000000000, 0000000000}, | ||
793 | {0000000000, 0000000000}, | ||
794 | {0000000000, 0000000000}, | ||
795 | {0000000000, 0000000000}, | ||
796 | {0000000000, 0000000000}, | ||
797 | {0000000000, 0000000000}, | ||
798 | {0000000000, 0000000000}, | ||
799 | {0000000000, 0000000000}, | ||
800 | {0000000000, 0000000000}, | ||
801 | {0000000000, 0000000000}, | ||
802 | {0000000000, 0000000000}, | ||
803 | {0000000000, 0000000000}, | ||
804 | {0000000000, 0000000000}, | ||
805 | {0000000000, 0000000000}, | ||
806 | {0000000000, 0000000000}, | ||
807 | {0000000000, 0000000000}, | ||
808 | {0000000000, 0000000000}, | ||
809 | {0000000000, 0000000000}, | ||
810 | {0000000000, 0000000000}, | ||
811 | {0000000000, 0000000000}, | ||
812 | {0000000000, 0000000000}, | ||
813 | {0000000000, 0000000000}, | ||
814 | {0000000000, 0000000000}, | ||
815 | {0000000000, 0000000000}, | ||
816 | {0000000000, 0000000000}, | ||
817 | }; | ||
818 | |||
819 | static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) | ||
820 | { | 45 | { |
821 | u32 ret; | 46 | u32 ret; |
822 | RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); | 47 | RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); |
@@ -825,21 +50,41 @@ static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) | |||
825 | return ret; | 50 | return ret; |
826 | } | 51 | } |
827 | 52 | ||
53 | static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) | ||
54 | { | ||
55 | u32 ret; | ||
56 | RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); | ||
57 | ret = RADEON_READ(RS480_NB_MC_DATA); | ||
58 | RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); | ||
59 | return ret; | ||
60 | } | ||
61 | |||
828 | static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) | 62 | static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
829 | { | 63 | { |
64 | u32 ret; | ||
830 | RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); | 65 | RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
831 | return RADEON_READ(RS690_MC_DATA); | 66 | ret = RADEON_READ(RS690_MC_DATA); |
67 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); | ||
68 | return ret; | ||
69 | } | ||
70 | |||
71 | static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) | ||
72 | { | ||
73 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) | ||
74 | return RS690_READ_MCIND(dev_priv, addr); | ||
75 | else | ||
76 | return RS480_READ_MCIND(dev_priv, addr); | ||
832 | } | 77 | } |
833 | 78 | ||
834 | u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) | 79 | u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) |
835 | { | 80 | { |
836 | 81 | ||
837 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | 82 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) |
838 | return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); | 83 | return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); |
839 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) | 84 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
840 | return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); | 85 | return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); |
841 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) | 86 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
842 | return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); | 87 | return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); |
843 | else | 88 | else |
844 | return RADEON_READ(RADEON_MC_FB_LOCATION); | 89 | return RADEON_READ(RADEON_MC_FB_LOCATION); |
845 | } | 90 | } |
@@ -847,11 +92,11 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) | |||
847 | static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) | 92 | static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) |
848 | { | 93 | { |
849 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | 94 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) |
850 | RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); | 95 | R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); |
851 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) | 96 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
852 | RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); | 97 | RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); |
853 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) | 98 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
854 | RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); | 99 | R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); |
855 | else | 100 | else |
856 | RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); | 101 | RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); |
857 | } | 102 | } |
@@ -859,15 +104,39 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) | |||
859 | static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) | 104 | static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) |
860 | { | 105 | { |
861 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) | 106 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) |
862 | RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); | 107 | R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); |
863 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) | 108 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
864 | RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); | 109 | RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); |
865 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) | 110 | else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) |
866 | RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); | 111 | R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); |
867 | else | 112 | else |
868 | RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); | 113 | RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); |
869 | } | 114 | } |
870 | 115 | ||
116 | static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) | ||
117 | { | ||
118 | u32 agp_base_hi = upper_32_bits(agp_base); | ||
119 | u32 agp_base_lo = agp_base & 0xffffffff; | ||
120 | |||
121 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { | ||
122 | R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); | ||
123 | R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); | ||
124 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { | ||
125 | RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); | ||
126 | RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); | ||
127 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { | ||
128 | R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); | ||
129 | R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); | ||
130 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) { | ||
131 | RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); | ||
132 | RADEON_WRITE(RS480_AGP_BASE_2, 0); | ||
133 | } else { | ||
134 | RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); | ||
135 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) | ||
136 | RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); | ||
137 | } | ||
138 | } | ||
139 | |||
871 | static int RADEON_READ_PLL(struct drm_device * dev, int addr) | 140 | static int RADEON_READ_PLL(struct drm_device * dev, int addr) |
872 | { | 141 | { |
873 | drm_radeon_private_t *dev_priv = dev->dev_private; | 142 | drm_radeon_private_t *dev_priv = dev->dev_private; |
@@ -882,15 +151,6 @@ static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) | |||
882 | return RADEON_READ(RADEON_PCIE_DATA); | 151 | return RADEON_READ(RADEON_PCIE_DATA); |
883 | } | 152 | } |
884 | 153 | ||
885 | static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr) | ||
886 | { | ||
887 | u32 ret; | ||
888 | RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f); | ||
889 | ret = RADEON_READ(RADEON_IGPGART_DATA); | ||
890 | RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f); | ||
891 | return ret; | ||
892 | } | ||
893 | |||
894 | #if RADEON_FIFO_DEBUG | 154 | #if RADEON_FIFO_DEBUG |
895 | static void radeon_status(drm_radeon_private_t * dev_priv) | 155 | static void radeon_status(drm_radeon_private_t * dev_priv) |
896 | { | 156 | { |
@@ -925,16 +185,36 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) | |||
925 | 185 | ||
926 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | 186 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
927 | 187 | ||
928 | tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); | 188 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { |
929 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; | 189 | tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); |
930 | RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); | 190 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; |
191 | RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); | ||
931 | 192 | ||
932 | for (i = 0; i < dev_priv->usec_timeout; i++) { | 193 | for (i = 0; i < dev_priv->usec_timeout; i++) { |
933 | if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) | 194 | if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) |
934 | & RADEON_RB3D_DC_BUSY)) { | 195 | & RADEON_RB3D_DC_BUSY)) { |
935 | return 0; | 196 | return 0; |
197 | } | ||
198 | DRM_UDELAY(1); | ||
199 | } | ||
200 | } else { | ||
201 | /* 3D */ | ||
202 | tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT); | ||
203 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; | ||
204 | RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp); | ||
205 | |||
206 | /* 2D */ | ||
207 | tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT); | ||
208 | tmp |= RADEON_RB3D_DC_FLUSH_ALL; | ||
209 | RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp); | ||
210 | |||
211 | for (i = 0; i < dev_priv->usec_timeout; i++) { | ||
212 | if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT) | ||
213 | & RADEON_RB3D_DC_BUSY)) { | ||
214 | return 0; | ||
215 | } | ||
216 | DRM_UDELAY(1); | ||
936 | } | 217 | } |
937 | DRM_UDELAY(1); | ||
938 | } | 218 | } |
939 | 219 | ||
940 | #if RADEON_FIFO_DEBUG | 220 | #if RADEON_FIFO_DEBUG |
@@ -991,6 +271,50 @@ static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) | |||
991 | return -EBUSY; | 271 | return -EBUSY; |
992 | } | 272 | } |
993 | 273 | ||
274 | static void radeon_init_pipes(drm_radeon_private_t *dev_priv) | ||
275 | { | ||
276 | uint32_t gb_tile_config, gb_pipe_sel = 0; | ||
277 | |||
278 | /* RS4xx/RS6xx/R4xx/R5xx */ | ||
279 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { | ||
280 | gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); | ||
281 | dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; | ||
282 | } else { | ||
283 | /* R3xx */ | ||
284 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || | ||
285 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { | ||
286 | dev_priv->num_gb_pipes = 2; | ||
287 | } else { | ||
288 | /* R3Vxx */ | ||
289 | dev_priv->num_gb_pipes = 1; | ||
290 | } | ||
291 | } | ||
292 | DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); | ||
293 | |||
294 | gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); | ||
295 | |||
296 | switch (dev_priv->num_gb_pipes) { | ||
297 | case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; | ||
298 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; | ||
299 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; | ||
300 | default: | ||
301 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; | ||
302 | } | ||
303 | |||
304 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { | ||
305 | RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); | ||
306 | RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); | ||
307 | } | ||
308 | RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); | ||
309 | radeon_do_wait_for_idle(dev_priv); | ||
310 | RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); | ||
311 | RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) | | ||
312 | R300_DC_AUTOFLUSH_ENABLE | | ||
313 | R300_DC_DC_DISABLE_IGNORE_PE)); | ||
314 | |||
315 | |||
316 | } | ||
317 | |||
994 | /* ================================================================ | 318 | /* ================================================================ |
995 | * CP control, initialization | 319 | * CP control, initialization |
996 | */ | 320 | */ |
@@ -1004,8 +328,22 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) | |||
1004 | radeon_do_wait_for_idle(dev_priv); | 328 | radeon_do_wait_for_idle(dev_priv); |
1005 | 329 | ||
1006 | RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); | 330 | RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); |
1007 | 331 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) || | |
1008 | if (dev_priv->microcode_version == UCODE_R200) { | 332 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) || |
333 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) || | ||
334 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) || | ||
335 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) { | ||
336 | DRM_INFO("Loading R100 Microcode\n"); | ||
337 | for (i = 0; i < 256; i++) { | ||
338 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | ||
339 | R100_cp_microcode[i][1]); | ||
340 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | ||
341 | R100_cp_microcode[i][0]); | ||
342 | } | ||
343 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) || | ||
344 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) || | ||
345 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) || | ||
346 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) { | ||
1009 | DRM_INFO("Loading R200 Microcode\n"); | 347 | DRM_INFO("Loading R200 Microcode\n"); |
1010 | for (i = 0; i < 256; i++) { | 348 | for (i = 0; i < 256; i++) { |
1011 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | 349 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, |
@@ -1013,7 +351,11 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) | |||
1013 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | 351 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, |
1014 | R200_cp_microcode[i][0]); | 352 | R200_cp_microcode[i][0]); |
1015 | } | 353 | } |
1016 | } else if (dev_priv->microcode_version == UCODE_R300) { | 354 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || |
355 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) || | ||
356 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) || | ||
357 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || | ||
358 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { | ||
1017 | DRM_INFO("Loading R300 Microcode\n"); | 359 | DRM_INFO("Loading R300 Microcode\n"); |
1018 | for (i = 0; i < 256; i++) { | 360 | for (i = 0; i < 256; i++) { |
1019 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | 361 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, |
@@ -1021,12 +363,35 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) | |||
1021 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | 363 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, |
1022 | R300_cp_microcode[i][0]); | 364 | R300_cp_microcode[i][0]); |
1023 | } | 365 | } |
1024 | } else { | 366 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || |
367 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { | ||
368 | DRM_INFO("Loading R400 Microcode\n"); | ||
1025 | for (i = 0; i < 256; i++) { | 369 | for (i = 0; i < 256; i++) { |
1026 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | 370 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, |
1027 | radeon_cp_microcode[i][1]); | 371 | R420_cp_microcode[i][1]); |
1028 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | 372 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, |
1029 | radeon_cp_microcode[i][0]); | 373 | R420_cp_microcode[i][0]); |
374 | } | ||
375 | } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { | ||
376 | DRM_INFO("Loading RS690 Microcode\n"); | ||
377 | for (i = 0; i < 256; i++) { | ||
378 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | ||
379 | RS690_cp_microcode[i][1]); | ||
380 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | ||
381 | RS690_cp_microcode[i][0]); | ||
382 | } | ||
383 | } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) || | ||
384 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) || | ||
385 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) || | ||
386 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) || | ||
387 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) || | ||
388 | ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) { | ||
389 | DRM_INFO("Loading R500 Microcode\n"); | ||
390 | for (i = 0; i < 256; i++) { | ||
391 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, | ||
392 | R520_cp_microcode[i][1]); | ||
393 | RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, | ||
394 | R520_cp_microcode[i][0]); | ||
1030 | } | 395 | } |
1031 | } | 396 | } |
1032 | } | 397 | } |
@@ -1121,12 +486,13 @@ static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) | |||
1121 | static int radeon_do_engine_reset(struct drm_device * dev) | 486 | static int radeon_do_engine_reset(struct drm_device * dev) |
1122 | { | 487 | { |
1123 | drm_radeon_private_t *dev_priv = dev->dev_private; | 488 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1124 | u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset; | 489 | u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; |
1125 | DRM_DEBUG("\n"); | 490 | DRM_DEBUG("\n"); |
1126 | 491 | ||
1127 | radeon_do_pixcache_flush(dev_priv); | 492 | radeon_do_pixcache_flush(dev_priv); |
1128 | 493 | ||
1129 | if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) { | 494 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { |
495 | /* may need something similar for newer chips */ | ||
1130 | clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); | 496 | clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); |
1131 | mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); | 497 | mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); |
1132 | 498 | ||
@@ -1137,33 +503,39 @@ static int radeon_do_engine_reset(struct drm_device * dev) | |||
1137 | RADEON_FORCEON_YCLKB | | 503 | RADEON_FORCEON_YCLKB | |
1138 | RADEON_FORCEON_MC | | 504 | RADEON_FORCEON_MC | |
1139 | RADEON_FORCEON_AIC)); | 505 | RADEON_FORCEON_AIC)); |
506 | } | ||
1140 | 507 | ||
1141 | rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); | 508 | rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); |
1142 | 509 | ||
1143 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | | 510 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | |
1144 | RADEON_SOFT_RESET_CP | | 511 | RADEON_SOFT_RESET_CP | |
1145 | RADEON_SOFT_RESET_HI | | 512 | RADEON_SOFT_RESET_HI | |
1146 | RADEON_SOFT_RESET_SE | | 513 | RADEON_SOFT_RESET_SE | |
1147 | RADEON_SOFT_RESET_RE | | 514 | RADEON_SOFT_RESET_RE | |
1148 | RADEON_SOFT_RESET_PP | | 515 | RADEON_SOFT_RESET_PP | |
1149 | RADEON_SOFT_RESET_E2 | | 516 | RADEON_SOFT_RESET_E2 | |
1150 | RADEON_SOFT_RESET_RB)); | 517 | RADEON_SOFT_RESET_RB)); |
1151 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | 518 | RADEON_READ(RADEON_RBBM_SOFT_RESET); |
1152 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & | 519 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & |
1153 | ~(RADEON_SOFT_RESET_CP | | 520 | ~(RADEON_SOFT_RESET_CP | |
1154 | RADEON_SOFT_RESET_HI | | 521 | RADEON_SOFT_RESET_HI | |
1155 | RADEON_SOFT_RESET_SE | | 522 | RADEON_SOFT_RESET_SE | |
1156 | RADEON_SOFT_RESET_RE | | 523 | RADEON_SOFT_RESET_RE | |
1157 | RADEON_SOFT_RESET_PP | | 524 | RADEON_SOFT_RESET_PP | |
1158 | RADEON_SOFT_RESET_E2 | | 525 | RADEON_SOFT_RESET_E2 | |
1159 | RADEON_SOFT_RESET_RB))); | 526 | RADEON_SOFT_RESET_RB))); |
1160 | RADEON_READ(RADEON_RBBM_SOFT_RESET); | 527 | RADEON_READ(RADEON_RBBM_SOFT_RESET); |
1161 | 528 | ||
529 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { | ||
1162 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); | 530 | RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); |
1163 | RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); | 531 | RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); |
1164 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); | 532 | RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); |
1165 | } | 533 | } |
1166 | 534 | ||
535 | /* setup the raster pipes */ | ||
536 | if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) | ||
537 | radeon_init_pipes(dev_priv); | ||
538 | |||
1167 | /* Reset the CP ring */ | 539 | /* Reset the CP ring */ |
1168 | radeon_do_cp_reset(dev_priv); | 540 | radeon_do_cp_reset(dev_priv); |
1169 | 541 | ||
@@ -1194,7 +566,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev, | |||
1194 | 566 | ||
1195 | #if __OS_HAS_AGP | 567 | #if __OS_HAS_AGP |
1196 | if (dev_priv->flags & RADEON_IS_AGP) { | 568 | if (dev_priv->flags & RADEON_IS_AGP) { |
1197 | RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base); | 569 | radeon_write_agp_base(dev_priv, dev->agp->base); |
570 | |||
1198 | radeon_write_agp_location(dev_priv, | 571 | radeon_write_agp_location(dev_priv, |
1199 | (((dev_priv->gart_vm_start - 1 + | 572 | (((dev_priv->gart_vm_start - 1 + |
1200 | dev_priv->gart_size) & 0xffff0000) | | 573 | dev_priv->gart_size) & 0xffff0000) | |
@@ -1339,102 +712,70 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv) | |||
1339 | /* Enable or disable IGP GART on the chip */ | 712 | /* Enable or disable IGP GART on the chip */ |
1340 | static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) | 713 | static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) |
1341 | { | 714 | { |
1342 | u32 temp, tmp; | ||
1343 | |||
1344 | tmp = RADEON_READ(RADEON_AIC_CNTL); | ||
1345 | if (on) { | ||
1346 | DRM_DEBUG("programming igpgart %08X %08lX %08X\n", | ||
1347 | dev_priv->gart_vm_start, | ||
1348 | (long)dev_priv->gart_info.bus_addr, | ||
1349 | dev_priv->gart_size); | ||
1350 | |||
1351 | RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000); | ||
1352 | RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1); | ||
1353 | RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800); | ||
1354 | RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR, | ||
1355 | dev_priv->gart_info.bus_addr); | ||
1356 | |||
1357 | temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39); | ||
1358 | RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp); | ||
1359 | |||
1360 | RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start); | ||
1361 | dev_priv->gart_size = 32*1024*1024; | ||
1362 | radeon_write_agp_location(dev_priv, | ||
1363 | (((dev_priv->gart_vm_start - 1 + | ||
1364 | dev_priv->gart_size) & 0xffff0000) | | ||
1365 | (dev_priv->gart_vm_start >> 16))); | ||
1366 | |||
1367 | temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE); | ||
1368 | RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp); | ||
1369 | |||
1370 | RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); | ||
1371 | RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1); | ||
1372 | RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH); | ||
1373 | RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0); | ||
1374 | } | ||
1375 | } | ||
1376 | |||
1377 | /* Enable or disable RS690 GART on the chip */ | ||
1378 | static void radeon_set_rs690gart(drm_radeon_private_t *dev_priv, int on) | ||
1379 | { | ||
1380 | u32 temp; | 715 | u32 temp; |
1381 | 716 | ||
1382 | if (on) { | 717 | if (on) { |
1383 | DRM_DEBUG("programming rs690 gart %08X %08lX %08X\n", | 718 | DRM_DEBUG("programming igp gart %08X %08lX %08X\n", |
1384 | dev_priv->gart_vm_start, | 719 | dev_priv->gart_vm_start, |
1385 | (long)dev_priv->gart_info.bus_addr, | 720 | (long)dev_priv->gart_info.bus_addr, |
1386 | dev_priv->gart_size); | 721 | dev_priv->gart_size); |
1387 | 722 | ||
1388 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_MISC_CNTL); | 723 | temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); |
1389 | RS690_WRITE_MCIND(RS690_MC_MISC_CNTL, 0x5000); | 724 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) |
725 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | | ||
726 | RS690_BLOCK_GFX_D3_EN)); | ||
727 | else | ||
728 | IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); | ||
1390 | 729 | ||
1391 | RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, | 730 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | |
1392 | RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); | 731 | RS480_VA_SIZE_32MB)); |
1393 | 732 | ||
1394 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_FEATURE_ID); | 733 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); |
1395 | RS690_WRITE_MCIND(RS690_MC_GART_FEATURE_ID, 0x42040800); | 734 | IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | |
735 | RS480_TLB_ENABLE | | ||
736 | RS480_GTW_LAC_EN | | ||
737 | RS480_1LEVEL_GART)); | ||
1396 | 738 | ||
1397 | RS690_WRITE_MCIND(RS690_MC_GART_BASE, | 739 | temp = dev_priv->gart_info.bus_addr & 0xfffff000; |
1398 | dev_priv->gart_info.bus_addr); | 740 | temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; |
741 | IGP_WRITE_MCIND(RS480_GART_BASE, temp); | ||
1399 | 742 | ||
1400 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_MODE_CONTROL); | 743 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); |
1401 | RS690_WRITE_MCIND(RS690_MC_AGP_MODE_CONTROL, 0x01400000); | 744 | IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | |
745 | RS480_REQ_TYPE_SNOOP_DIS)); | ||
1402 | 746 | ||
1403 | RS690_WRITE_MCIND(RS690_MC_AGP_BASE, | 747 | radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); |
1404 | (unsigned int)dev_priv->gart_vm_start); | ||
1405 | 748 | ||
1406 | dev_priv->gart_size = 32*1024*1024; | 749 | dev_priv->gart_size = 32*1024*1024; |
1407 | temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & | 750 | temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & |
1408 | 0xffff0000) | (dev_priv->gart_vm_start >> 16)); | 751 | 0xffff0000) | (dev_priv->gart_vm_start >> 16)); |
1409 | 752 | ||
1410 | RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, temp); | 753 | radeon_write_agp_location(dev_priv, temp); |
1411 | 754 | ||
1412 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_AGP_SIZE); | 755 | temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); |
1413 | RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, | 756 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | |
1414 | RS690_MC_GART_EN | RS690_MC_AGP_SIZE_32MB); | 757 | RS480_VA_SIZE_32MB)); |
1415 | 758 | ||
1416 | do { | 759 | do { |
1417 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); | 760 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
1418 | if ((temp & RS690_MC_GART_CLEAR_STATUS) == | 761 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) |
1419 | RS690_MC_GART_CLEAR_DONE) | ||
1420 | break; | 762 | break; |
1421 | DRM_UDELAY(1); | 763 | DRM_UDELAY(1); |
1422 | } while (1); | 764 | } while (1); |
1423 | 765 | ||
1424 | RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, | 766 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, |
1425 | RS690_MC_GART_CC_CLEAR); | 767 | RS480_GART_CACHE_INVALIDATE); |
768 | |||
1426 | do { | 769 | do { |
1427 | temp = RS690_READ_MCIND(dev_priv, RS690_MC_GART_CACHE_CNTL); | 770 | temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); |
1428 | if ((temp & RS690_MC_GART_CLEAR_STATUS) == | 771 | if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) |
1429 | RS690_MC_GART_CLEAR_DONE) | ||
1430 | break; | 772 | break; |
1431 | DRM_UDELAY(1); | 773 | DRM_UDELAY(1); |
1432 | } while (1); | 774 | } while (1); |
1433 | 775 | ||
1434 | RS690_WRITE_MCIND(RS690_MC_GART_CACHE_CNTL, | 776 | IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); |
1435 | RS690_MC_GART_CC_NO_CHANGE); | ||
1436 | } else { | 777 | } else { |
1437 | RS690_WRITE_MCIND(RS690_MC_AGP_SIZE, RS690_MC_GART_DIS); | 778 | IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); |
1438 | } | 779 | } |
1439 | } | 780 | } |
1440 | 781 | ||
@@ -1472,12 +813,8 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) | |||
1472 | { | 813 | { |
1473 | u32 tmp; | 814 | u32 tmp; |
1474 | 815 | ||
1475 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) { | 816 | if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || |
1476 | radeon_set_rs690gart(dev_priv, on); | 817 | (dev_priv->flags & RADEON_IS_IGPGART)) { |
1477 | return; | ||
1478 | } | ||
1479 | |||
1480 | if (dev_priv->flags & RADEON_IS_IGPGART) { | ||
1481 | radeon_set_igpgart(dev_priv, on); | 818 | radeon_set_igpgart(dev_priv, on); |
1482 | return; | 819 | return; |
1483 | } | 820 | } |
@@ -1951,6 +1288,7 @@ static int radeon_do_resume_cp(struct drm_device * dev) | |||
1951 | radeon_cp_init_ring_buffer(dev, dev_priv); | 1288 | radeon_cp_init_ring_buffer(dev, dev_priv); |
1952 | 1289 | ||
1953 | radeon_do_engine_reset(dev); | 1290 | radeon_do_engine_reset(dev); |
1291 | radeon_enable_interrupt(dev); | ||
1954 | 1292 | ||
1955 | DRM_DEBUG("radeon_do_resume_cp() complete\n"); | 1293 | DRM_DEBUG("radeon_do_resume_cp() complete\n"); |
1956 | 1294 | ||
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h index aab82e121e07..73ff51f12311 100644 --- a/drivers/char/drm/radeon_drm.h +++ b/drivers/char/drm/radeon_drm.h | |||
@@ -240,6 +240,7 @@ typedef union { | |||
240 | # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 | 240 | # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 |
241 | 241 | ||
242 | #define R300_CMD_SCRATCH 8 | 242 | #define R300_CMD_SCRATCH 8 |
243 | #define R300_CMD_R500FP 9 | ||
243 | 244 | ||
244 | typedef union { | 245 | typedef union { |
245 | unsigned int u; | 246 | unsigned int u; |
@@ -268,6 +269,9 @@ typedef union { | |||
268 | struct { | 269 | struct { |
269 | unsigned char cmd_type, reg, n_bufs, flags; | 270 | unsigned char cmd_type, reg, n_bufs, flags; |
270 | } scratch; | 271 | } scratch; |
272 | struct { | ||
273 | unsigned char cmd_type, count, adrlo, adrhi_flags; | ||
274 | } r500fp; | ||
271 | } drm_r300_cmd_header_t; | 275 | } drm_r300_cmd_header_t; |
272 | 276 | ||
273 | #define RADEON_FRONT 0x1 | 277 | #define RADEON_FRONT 0x1 |
@@ -278,6 +282,9 @@ typedef union { | |||
278 | #define RADEON_USE_HIERZ 0x40000000 | 282 | #define RADEON_USE_HIERZ 0x40000000 |
279 | #define RADEON_USE_COMP_ZBUF 0x20000000 | 283 | #define RADEON_USE_COMP_ZBUF 0x20000000 |
280 | 284 | ||
285 | #define R500FP_CONSTANT_TYPE (1 << 1) | ||
286 | #define R500FP_CONSTANT_CLAMP (1 << 2) | ||
287 | |||
281 | /* Primitive types | 288 | /* Primitive types |
282 | */ | 289 | */ |
283 | #define RADEON_POINTS 0x1 | 290 | #define RADEON_POINTS 0x1 |
@@ -669,6 +676,7 @@ typedef struct drm_radeon_indirect { | |||
669 | #define RADEON_PARAM_CARD_TYPE 12 | 676 | #define RADEON_PARAM_CARD_TYPE 12 |
670 | #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ | 677 | #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ |
671 | #define RADEON_PARAM_FB_LOCATION 14 /* FB location */ | 678 | #define RADEON_PARAM_FB_LOCATION 14 /* FB location */ |
679 | #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ | ||
672 | 680 | ||
673 | typedef struct drm_radeon_getparam { | 681 | typedef struct drm_radeon_getparam { |
674 | int param; | 682 | int param; |
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 173ae620223a..3f0eca957aa7 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h | |||
@@ -38,7 +38,7 @@ | |||
38 | 38 | ||
39 | #define DRIVER_NAME "radeon" | 39 | #define DRIVER_NAME "radeon" |
40 | #define DRIVER_DESC "ATI Radeon" | 40 | #define DRIVER_DESC "ATI Radeon" |
41 | #define DRIVER_DATE "20060524" | 41 | #define DRIVER_DATE "20080528" |
42 | 42 | ||
43 | /* Interface history: | 43 | /* Interface history: |
44 | * | 44 | * |
@@ -98,9 +98,10 @@ | |||
98 | * 1.26- Add support for variable size PCI(E) gart aperture | 98 | * 1.26- Add support for variable size PCI(E) gart aperture |
99 | * 1.27- Add support for IGP GART | 99 | * 1.27- Add support for IGP GART |
100 | * 1.28- Add support for VBL on CRTC2 | 100 | * 1.28- Add support for VBL on CRTC2 |
101 | * 1.29- R500 3D cmd buffer support | ||
101 | */ | 102 | */ |
102 | #define DRIVER_MAJOR 1 | 103 | #define DRIVER_MAJOR 1 |
103 | #define DRIVER_MINOR 28 | 104 | #define DRIVER_MINOR 29 |
104 | #define DRIVER_PATCHLEVEL 0 | 105 | #define DRIVER_PATCHLEVEL 0 |
105 | 106 | ||
106 | /* | 107 | /* |
@@ -122,7 +123,7 @@ enum radeon_family { | |||
122 | CHIP_RV380, | 123 | CHIP_RV380, |
123 | CHIP_R420, | 124 | CHIP_R420, |
124 | CHIP_RV410, | 125 | CHIP_RV410, |
125 | CHIP_RS400, | 126 | CHIP_RS480, |
126 | CHIP_RS690, | 127 | CHIP_RS690, |
127 | CHIP_RV515, | 128 | CHIP_RV515, |
128 | CHIP_R520, | 129 | CHIP_R520, |
@@ -294,6 +295,7 @@ typedef struct drm_radeon_private { | |||
294 | int vblank_crtc; | 295 | int vblank_crtc; |
295 | uint32_t irq_enable_reg; | 296 | uint32_t irq_enable_reg; |
296 | int irq_enabled; | 297 | int irq_enabled; |
298 | uint32_t r500_disp_irq_reg; | ||
297 | 299 | ||
298 | struct radeon_surface surfaces[RADEON_MAX_SURFACES]; | 300 | struct radeon_surface surfaces[RADEON_MAX_SURFACES]; |
299 | struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; | 301 | struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; |
@@ -307,6 +309,8 @@ typedef struct drm_radeon_private { | |||
307 | /* starting from here on, data is preserved accross an open */ | 309 | /* starting from here on, data is preserved accross an open */ |
308 | uint32_t flags; /* see radeon_chip_flags */ | 310 | uint32_t flags; /* see radeon_chip_flags */ |
309 | unsigned long fb_aper_offset; | 311 | unsigned long fb_aper_offset; |
312 | |||
313 | int num_gb_pipes; | ||
310 | } drm_radeon_private_t; | 314 | } drm_radeon_private_t; |
311 | 315 | ||
312 | typedef struct drm_radeon_buf_priv { | 316 | typedef struct drm_radeon_buf_priv { |
@@ -382,6 +386,7 @@ extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); | |||
382 | extern void radeon_driver_irq_preinstall(struct drm_device * dev); | 386 | extern void radeon_driver_irq_preinstall(struct drm_device * dev); |
383 | extern void radeon_driver_irq_postinstall(struct drm_device * dev); | 387 | extern void radeon_driver_irq_postinstall(struct drm_device * dev); |
384 | extern void radeon_driver_irq_uninstall(struct drm_device * dev); | 388 | extern void radeon_driver_irq_uninstall(struct drm_device * dev); |
389 | extern void radeon_enable_interrupt(struct drm_device *dev); | ||
385 | extern int radeon_vblank_crtc_get(struct drm_device *dev); | 390 | extern int radeon_vblank_crtc_get(struct drm_device *dev); |
386 | extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); | 391 | extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); |
387 | 392 | ||
@@ -444,13 +449,13 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, | |||
444 | #define RADEON_PCIE_DATA 0x0034 | 449 | #define RADEON_PCIE_DATA 0x0034 |
445 | #define RADEON_PCIE_TX_GART_CNTL 0x10 | 450 | #define RADEON_PCIE_TX_GART_CNTL 0x10 |
446 | # define RADEON_PCIE_TX_GART_EN (1 << 0) | 451 | # define RADEON_PCIE_TX_GART_EN (1 << 0) |
447 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) | 452 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) |
448 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) | 453 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) |
449 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) | 454 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) |
450 | # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) | 455 | # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) |
451 | # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) | 456 | # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) |
452 | # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) | 457 | # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) |
453 | # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) | 458 | # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) |
454 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 | 459 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 |
455 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 | 460 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 |
456 | #define RADEON_PCIE_TX_GART_BASE 0x13 | 461 | #define RADEON_PCIE_TX_GART_BASE 0x13 |
@@ -459,14 +464,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, | |||
459 | #define RADEON_PCIE_TX_GART_END_LO 0x16 | 464 | #define RADEON_PCIE_TX_GART_END_LO 0x16 |
460 | #define RADEON_PCIE_TX_GART_END_HI 0x17 | 465 | #define RADEON_PCIE_TX_GART_END_HI 0x17 |
461 | 466 | ||
462 | #define RADEON_IGPGART_INDEX 0x168 | 467 | #define RS480_NB_MC_INDEX 0x168 |
463 | #define RADEON_IGPGART_DATA 0x16c | 468 | # define RS480_NB_MC_IND_WR_EN (1 << 8) |
464 | #define RADEON_IGPGART_UNK_18 0x18 | 469 | #define RS480_NB_MC_DATA 0x16c |
465 | #define RADEON_IGPGART_CTRL 0x2b | ||
466 | #define RADEON_IGPGART_BASE_ADDR 0x2c | ||
467 | #define RADEON_IGPGART_FLUSH 0x2e | ||
468 | #define RADEON_IGPGART_ENABLE 0x38 | ||
469 | #define RADEON_IGPGART_UNK_39 0x39 | ||
470 | 470 | ||
471 | #define RS690_MC_INDEX 0x78 | 471 | #define RS690_MC_INDEX 0x78 |
472 | # define RS690_MC_INDEX_MASK 0x1ff | 472 | # define RS690_MC_INDEX_MASK 0x1ff |
@@ -474,45 +474,91 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, | |||
474 | # define RS690_MC_INDEX_WR_ACK 0x7f | 474 | # define RS690_MC_INDEX_WR_ACK 0x7f |
475 | #define RS690_MC_DATA 0x7c | 475 | #define RS690_MC_DATA 0x7c |
476 | 476 | ||
477 | #define RS690_MC_MISC_CNTL 0x18 | 477 | /* MC indirect registers */ |
478 | #define RS690_MC_GART_FEATURE_ID 0x2b | 478 | #define RS480_MC_MISC_CNTL 0x18 |
479 | #define RS690_MC_GART_BASE 0x2c | 479 | # define RS480_DISABLE_GTW (1 << 1) |
480 | #define RS690_MC_GART_CACHE_CNTL 0x2e | 480 | /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ |
481 | # define RS690_MC_GART_CC_NO_CHANGE 0x0 | 481 | # define RS480_GART_INDEX_REG_EN (1 << 12) |
482 | # define RS690_MC_GART_CC_CLEAR 0x1 | 482 | # define RS690_BLOCK_GFX_D3_EN (1 << 14) |
483 | # define RS690_MC_GART_CLEAR_STATUS (1 << 1) | 483 | #define RS480_K8_FB_LOCATION 0x1e |
484 | # define RS690_MC_GART_CLEAR_DONE (0 << 1) | 484 | #define RS480_GART_FEATURE_ID 0x2b |
485 | # define RS690_MC_GART_CLEAR_PENDING (1 << 1) | 485 | # define RS480_HANG_EN (1 << 11) |
486 | #define RS690_MC_AGP_SIZE 0x38 | 486 | # define RS480_TLB_ENABLE (1 << 18) |
487 | # define RS690_MC_GART_DIS 0x0 | 487 | # define RS480_P2P_ENABLE (1 << 19) |
488 | # define RS690_MC_GART_EN 0x1 | 488 | # define RS480_GTW_LAC_EN (1 << 25) |
489 | # define RS690_MC_AGP_SIZE_32MB (0 << 1) | 489 | # define RS480_2LEVEL_GART (0 << 30) |
490 | # define RS690_MC_AGP_SIZE_64MB (1 << 1) | 490 | # define RS480_1LEVEL_GART (1 << 30) |
491 | # define RS690_MC_AGP_SIZE_128MB (2 << 1) | 491 | # define RS480_PDC_EN (1 << 31) |
492 | # define RS690_MC_AGP_SIZE_256MB (3 << 1) | 492 | #define RS480_GART_BASE 0x2c |
493 | # define RS690_MC_AGP_SIZE_512MB (4 << 1) | 493 | #define RS480_GART_CACHE_CNTRL 0x2e |
494 | # define RS690_MC_AGP_SIZE_1GB (5 << 1) | 494 | # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ |
495 | # define RS690_MC_AGP_SIZE_2GB (6 << 1) | 495 | #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 |
496 | #define RS690_MC_AGP_MODE_CONTROL 0x39 | 496 | # define RS480_GART_EN (1 << 0) |
497 | # define RS480_VA_SIZE_32MB (0 << 1) | ||
498 | # define RS480_VA_SIZE_64MB (1 << 1) | ||
499 | # define RS480_VA_SIZE_128MB (2 << 1) | ||
500 | # define RS480_VA_SIZE_256MB (3 << 1) | ||
501 | # define RS480_VA_SIZE_512MB (4 << 1) | ||
502 | # define RS480_VA_SIZE_1GB (5 << 1) | ||
503 | # define RS480_VA_SIZE_2GB (6 << 1) | ||
504 | #define RS480_AGP_MODE_CNTL 0x39 | ||
505 | # define RS480_POST_GART_Q_SIZE (1 << 18) | ||
506 | # define RS480_NONGART_SNOOP (1 << 19) | ||
507 | # define RS480_AGP_RD_BUF_SIZE (1 << 20) | ||
508 | # define RS480_REQ_TYPE_SNOOP_SHIFT 22 | ||
509 | # define RS480_REQ_TYPE_SNOOP_MASK 0x3 | ||
510 | # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) | ||
511 | #define RS480_MC_MISC_UMA_CNTL 0x5f | ||
512 | #define RS480_MC_MCLK_CNTL 0x7a | ||
513 | #define RS480_MC_UMA_DUALCH_CNTL 0x86 | ||
514 | |||
497 | #define RS690_MC_FB_LOCATION 0x100 | 515 | #define RS690_MC_FB_LOCATION 0x100 |
498 | #define RS690_MC_AGP_LOCATION 0x101 | 516 | #define RS690_MC_AGP_LOCATION 0x101 |
499 | #define RS690_MC_AGP_BASE 0x102 | 517 | #define RS690_MC_AGP_BASE 0x102 |
518 | #define RS690_MC_AGP_BASE_2 0x103 | ||
500 | 519 | ||
501 | #define R520_MC_IND_INDEX 0x70 | 520 | #define R520_MC_IND_INDEX 0x70 |
502 | #define R520_MC_IND_WR_EN (1<<24) | 521 | #define R520_MC_IND_WR_EN (1 << 24) |
503 | #define R520_MC_IND_DATA 0x74 | 522 | #define R520_MC_IND_DATA 0x74 |
504 | 523 | ||
505 | #define RV515_MC_FB_LOCATION 0x01 | 524 | #define RV515_MC_FB_LOCATION 0x01 |
506 | #define RV515_MC_AGP_LOCATION 0x02 | 525 | #define RV515_MC_AGP_LOCATION 0x02 |
526 | #define RV515_MC_AGP_BASE 0x03 | ||
527 | #define RV515_MC_AGP_BASE_2 0x04 | ||
507 | 528 | ||
508 | #define R520_MC_FB_LOCATION 0x04 | 529 | #define R520_MC_FB_LOCATION 0x04 |
509 | #define R520_MC_AGP_LOCATION 0x05 | 530 | #define R520_MC_AGP_LOCATION 0x05 |
531 | #define R520_MC_AGP_BASE 0x06 | ||
532 | #define R520_MC_AGP_BASE_2 0x07 | ||
510 | 533 | ||
511 | #define RADEON_MPP_TB_CONFIG 0x01c0 | 534 | #define RADEON_MPP_TB_CONFIG 0x01c0 |
512 | #define RADEON_MEM_CNTL 0x0140 | 535 | #define RADEON_MEM_CNTL 0x0140 |
513 | #define RADEON_MEM_SDRAM_MODE_REG 0x0158 | 536 | #define RADEON_MEM_SDRAM_MODE_REG 0x0158 |
537 | #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ | ||
538 | #define RS480_AGP_BASE_2 0x0164 | ||
514 | #define RADEON_AGP_BASE 0x0170 | 539 | #define RADEON_AGP_BASE 0x0170 |
515 | 540 | ||
541 | /* pipe config regs */ | ||
542 | #define R400_GB_PIPE_SELECT 0x402c | ||
543 | #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ | ||
544 | #define R500_SU_REG_DEST 0x42c8 | ||
545 | #define R300_GB_TILE_CONFIG 0x4018 | ||
546 | # define R300_ENABLE_TILING (1 << 0) | ||
547 | # define R300_PIPE_COUNT_RV350 (0 << 1) | ||
548 | # define R300_PIPE_COUNT_R300 (3 << 1) | ||
549 | # define R300_PIPE_COUNT_R420_3P (6 << 1) | ||
550 | # define R300_PIPE_COUNT_R420 (7 << 1) | ||
551 | # define R300_TILE_SIZE_8 (0 << 4) | ||
552 | # define R300_TILE_SIZE_16 (1 << 4) | ||
553 | # define R300_TILE_SIZE_32 (2 << 4) | ||
554 | # define R300_SUBPIXEL_1_12 (0 << 16) | ||
555 | # define R300_SUBPIXEL_1_16 (1 << 16) | ||
556 | #define R300_DST_PIPE_CONFIG 0x170c | ||
557 | # define R300_PIPE_AUTO_CONFIG (1 << 31) | ||
558 | #define R300_RB2D_DSTCACHE_MODE 0x3428 | ||
559 | # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) | ||
560 | # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) | ||
561 | |||
516 | #define RADEON_RB3D_COLOROFFSET 0x1c40 | 562 | #define RADEON_RB3D_COLOROFFSET 0x1c40 |
517 | #define RADEON_RB3D_COLORPITCH 0x1c48 | 563 | #define RADEON_RB3D_COLORPITCH 0x1c48 |
518 | 564 | ||
@@ -616,11 +662,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, | |||
616 | #define RADEON_PP_TXFILTER_1 0x1c6c | 662 | #define RADEON_PP_TXFILTER_1 0x1c6c |
617 | #define RADEON_PP_TXFILTER_2 0x1c84 | 663 | #define RADEON_PP_TXFILTER_2 0x1c84 |
618 | 664 | ||
619 | #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c | 665 | #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ |
620 | # define RADEON_RB2D_DC_FLUSH (3 << 0) | 666 | #define R300_DSTCACHE_CTLSTAT 0x1714 |
621 | # define RADEON_RB2D_DC_FREE (3 << 2) | 667 | # define R300_RB2D_DC_FLUSH (3 << 0) |
622 | # define RADEON_RB2D_DC_FLUSH_ALL 0xf | 668 | # define R300_RB2D_DC_FREE (3 << 2) |
623 | # define RADEON_RB2D_DC_BUSY (1 << 31) | 669 | # define R300_RB2D_DC_FLUSH_ALL 0xf |
670 | # define R300_RB2D_DC_BUSY (1 << 31) | ||
624 | #define RADEON_RB3D_CNTL 0x1c3c | 671 | #define RADEON_RB3D_CNTL 0x1c3c |
625 | # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) | 672 | # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) |
626 | # define RADEON_PLANE_MASK_ENABLE (1 << 1) | 673 | # define RADEON_PLANE_MASK_ENABLE (1 << 1) |
@@ -643,11 +690,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, | |||
643 | # define RADEON_RB3D_ZC_FREE (1 << 2) | 690 | # define RADEON_RB3D_ZC_FREE (1 << 2) |
644 | # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 | 691 | # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 |
645 | # define RADEON_RB3D_ZC_BUSY (1 << 31) | 692 | # define RADEON_RB3D_ZC_BUSY (1 << 31) |
693 | #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 | ||
694 | # define R300_ZC_FLUSH (1 << 0) | ||
695 | # define R300_ZC_FREE (1 << 1) | ||
696 | # define R300_ZC_FLUSH_ALL 0x3 | ||
697 | # define R300_ZC_BUSY (1 << 31) | ||
646 | #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c | 698 | #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c |
647 | # define RADEON_RB3D_DC_FLUSH (3 << 0) | 699 | # define RADEON_RB3D_DC_FLUSH (3 << 0) |
648 | # define RADEON_RB3D_DC_FREE (3 << 2) | 700 | # define RADEON_RB3D_DC_FREE (3 << 2) |
649 | # define RADEON_RB3D_DC_FLUSH_ALL 0xf | 701 | # define RADEON_RB3D_DC_FLUSH_ALL 0xf |
650 | # define RADEON_RB3D_DC_BUSY (1 << 31) | 702 | # define RADEON_RB3D_DC_BUSY (1 << 31) |
703 | #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c | ||
704 | # define R300_RB3D_DC_FINISH (1 << 4) | ||
651 | #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c | 705 | #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c |
652 | # define RADEON_Z_TEST_MASK (7 << 4) | 706 | # define RADEON_Z_TEST_MASK (7 << 4) |
653 | # define RADEON_Z_TEST_ALWAYS (7 << 4) | 707 | # define RADEON_Z_TEST_ALWAYS (7 << 4) |
@@ -1057,6 +1111,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, | |||
1057 | 1111 | ||
1058 | #define R200_VAP_PVS_CNTL_1 0x22D0 | 1112 | #define R200_VAP_PVS_CNTL_1 0x22D0 |
1059 | 1113 | ||
1114 | #define R500_D1CRTC_STATUS 0x609c | ||
1115 | #define R500_D2CRTC_STATUS 0x689c | ||
1116 | #define R500_CRTC_V_BLANK (1<<0) | ||
1117 | |||
1118 | #define R500_D1CRTC_FRAME_COUNT 0x60a4 | ||
1119 | #define R500_D2CRTC_FRAME_COUNT 0x68a4 | ||
1120 | |||
1121 | #define R500_D1MODE_V_COUNTER 0x6530 | ||
1122 | #define R500_D2MODE_V_COUNTER 0x6d30 | ||
1123 | |||
1124 | #define R500_D1MODE_VBLANK_STATUS 0x6534 | ||
1125 | #define R500_D2MODE_VBLANK_STATUS 0x6d34 | ||
1126 | #define R500_VBLANK_OCCURED (1<<0) | ||
1127 | #define R500_VBLANK_ACK (1<<4) | ||
1128 | #define R500_VBLANK_STAT (1<<12) | ||
1129 | #define R500_VBLANK_INT (1<<16) | ||
1130 | |||
1131 | #define R500_DxMODE_INT_MASK 0x6540 | ||
1132 | #define R500_D1MODE_INT_MASK (1<<0) | ||
1133 | #define R500_D2MODE_INT_MASK (1<<8) | ||
1134 | |||
1135 | #define R500_DISP_INTERRUPT_STATUS 0x7edc | ||
1136 | #define R500_D1_VBLANK_INTERRUPT (1 << 4) | ||
1137 | #define R500_D2_VBLANK_INTERRUPT (1 << 5) | ||
1138 | |||
1060 | /* Constants */ | 1139 | /* Constants */ |
1061 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | 1140 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
1062 | 1141 | ||
@@ -1078,42 +1157,50 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev, | |||
1078 | #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) | 1157 | #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) |
1079 | #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) | 1158 | #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) |
1080 | 1159 | ||
1081 | #define RADEON_WRITE_PLL( addr, val ) \ | 1160 | #define RADEON_WRITE_PLL(addr, val) \ |
1082 | do { \ | 1161 | do { \ |
1083 | RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ | 1162 | RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ |
1084 | ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ | 1163 | ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ |
1085 | RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ | 1164 | RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ |
1086 | } while (0) | 1165 | } while (0) |
1087 | 1166 | ||
1088 | #define RADEON_WRITE_IGPGART( addr, val ) \ | 1167 | #define RADEON_WRITE_PCIE(addr, val) \ |
1089 | do { \ | 1168 | do { \ |
1090 | RADEON_WRITE( RADEON_IGPGART_INDEX, \ | 1169 | RADEON_WRITE8(RADEON_PCIE_INDEX, \ |
1091 | ((addr) & 0x7f) | (1 << 8)); \ | 1170 | ((addr) & 0xff)); \ |
1092 | RADEON_WRITE( RADEON_IGPGART_DATA, (val) ); \ | 1171 | RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ |
1093 | RADEON_WRITE( RADEON_IGPGART_INDEX, 0x7f ); \ | ||
1094 | } while (0) | 1172 | } while (0) |
1095 | 1173 | ||
1096 | #define RADEON_WRITE_PCIE( addr, val ) \ | 1174 | #define R500_WRITE_MCIND(addr, val) \ |
1097 | do { \ | 1175 | do { \ |
1098 | RADEON_WRITE8( RADEON_PCIE_INDEX, \ | 1176 | RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ |
1099 | ((addr) & 0xff)); \ | 1177 | RADEON_WRITE(R520_MC_IND_DATA, (val)); \ |
1100 | RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ | 1178 | RADEON_WRITE(R520_MC_IND_INDEX, 0); \ |
1101 | } while (0) | 1179 | } while (0) |
1102 | 1180 | ||
1103 | #define RADEON_WRITE_MCIND( addr, val ) \ | 1181 | #define RS480_WRITE_MCIND(addr, val) \ |
1104 | do { \ | 1182 | do { \ |
1105 | RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ | 1183 | RADEON_WRITE(RS480_NB_MC_INDEX, \ |
1106 | RADEON_WRITE(R520_MC_IND_DATA, (val)); \ | 1184 | ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ |
1107 | RADEON_WRITE(R520_MC_IND_INDEX, 0); \ | 1185 | RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ |
1108 | } while (0) | 1186 | RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ |
1187 | } while (0) | ||
1109 | 1188 | ||
1110 | #define RS690_WRITE_MCIND( addr, val ) \ | 1189 | #define RS690_WRITE_MCIND(addr, val) \ |
1111 | do { \ | 1190 | do { \ |
1112 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ | 1191 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ |
1113 | RADEON_WRITE(RS690_MC_DATA, val); \ | 1192 | RADEON_WRITE(RS690_MC_DATA, val); \ |
1114 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ | 1193 | RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ |
1115 | } while (0) | 1194 | } while (0) |
1116 | 1195 | ||
1196 | #define IGP_WRITE_MCIND(addr, val) \ | ||
1197 | do { \ | ||
1198 | if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \ | ||
1199 | RS690_WRITE_MCIND(addr, val); \ | ||
1200 | else \ | ||
1201 | RS480_WRITE_MCIND(addr, val); \ | ||
1202 | } while (0) | ||
1203 | |||
1117 | #define CP_PACKET0( reg, n ) \ | 1204 | #define CP_PACKET0( reg, n ) \ |
1118 | (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) | 1205 | (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) |
1119 | #define CP_PACKET0_TABLE( reg, n ) \ | 1206 | #define CP_PACKET0_TABLE( reg, n ) \ |
@@ -1154,23 +1241,43 @@ do { \ | |||
1154 | } while (0) | 1241 | } while (0) |
1155 | 1242 | ||
1156 | #define RADEON_FLUSH_CACHE() do { \ | 1243 | #define RADEON_FLUSH_CACHE() do { \ |
1157 | OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ | 1244 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1158 | OUT_RING( RADEON_RB3D_DC_FLUSH ); \ | 1245 | OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ |
1246 | OUT_RING(RADEON_RB3D_DC_FLUSH); \ | ||
1247 | } else { \ | ||
1248 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ | ||
1249 | OUT_RING(RADEON_RB3D_DC_FLUSH); \ | ||
1250 | } \ | ||
1159 | } while (0) | 1251 | } while (0) |
1160 | 1252 | ||
1161 | #define RADEON_PURGE_CACHE() do { \ | 1253 | #define RADEON_PURGE_CACHE() do { \ |
1162 | OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ | 1254 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1163 | OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \ | 1255 | OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ |
1256 | OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ | ||
1257 | } else { \ | ||
1258 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ | ||
1259 | OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ | ||
1260 | } \ | ||
1164 | } while (0) | 1261 | } while (0) |
1165 | 1262 | ||
1166 | #define RADEON_FLUSH_ZCACHE() do { \ | 1263 | #define RADEON_FLUSH_ZCACHE() do { \ |
1167 | OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ | 1264 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1168 | OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ | 1265 | OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ |
1266 | OUT_RING(RADEON_RB3D_ZC_FLUSH); \ | ||
1267 | } else { \ | ||
1268 | OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ | ||
1269 | OUT_RING(R300_ZC_FLUSH); \ | ||
1270 | } \ | ||
1169 | } while (0) | 1271 | } while (0) |
1170 | 1272 | ||
1171 | #define RADEON_PURGE_ZCACHE() do { \ | 1273 | #define RADEON_PURGE_ZCACHE() do { \ |
1172 | OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ | 1274 | if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ |
1173 | OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ | 1275 | OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ |
1276 | OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \ | ||
1277 | } else { \ | ||
1278 | OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ | ||
1279 | OUT_RING(R300_ZC_FLUSH_ALL); \ | ||
1280 | } \ | ||
1174 | } while (0) | 1281 | } while (0) |
1175 | 1282 | ||
1176 | /* ================================================================ | 1283 | /* ================================================================ |
diff --git a/drivers/char/drm/radeon_irq.c b/drivers/char/drm/radeon_irq.c index 009af3814b6f..ee40d197deb7 100644 --- a/drivers/char/drm/radeon_irq.c +++ b/drivers/char/drm/radeon_irq.c | |||
@@ -234,7 +234,7 @@ int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_pr | |||
234 | return radeon_wait_irq(dev, irqwait->irq_seq); | 234 | return radeon_wait_irq(dev, irqwait->irq_seq); |
235 | } | 235 | } |
236 | 236 | ||
237 | static void radeon_enable_interrupt(struct drm_device *dev) | 237 | void radeon_enable_interrupt(struct drm_device *dev) |
238 | { | 238 | { |
239 | drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; | 239 | drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private; |
240 | 240 | ||
diff --git a/drivers/char/drm/radeon_microcode.h b/drivers/char/drm/radeon_microcode.h new file mode 100644 index 000000000000..a348c9e7db1c --- /dev/null +++ b/drivers/char/drm/radeon_microcode.h | |||
@@ -0,0 +1,1844 @@ | |||
1 | /* | ||
2 | * Copyright 2007 Advanced Micro Devices, Inc. | ||
3 | * All Rights Reserved. | ||
4 | * | ||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
6 | * copy of this software and associated documentation files (the "Software"), | ||
7 | * to deal in the Software without restriction, including without limitation | ||
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
9 | * and/or sell copies of the Software, and to permit persons to whom the | ||
10 | * Software is furnished to do so, subject to the following conditions: | ||
11 | * | ||
12 | * The above copyright notice and this permission notice (including the next | ||
13 | * paragraph) shall be included in all copies or substantial portions of the | ||
14 | * Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | ||
20 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | ||
21 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | ||
22 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
23 | * | ||
24 | */ | ||
25 | |||
26 | #ifndef RADEON_MICROCODE_H | ||
27 | #define RADEON_MICROCODE_H | ||
28 | |||
29 | /* production radeon ucode r1xx-r6xx */ | ||
30 | static const u32 R100_cp_microcode[][2] = { | ||
31 | { 0x21007000, 0000000000 }, | ||
32 | { 0x20007000, 0000000000 }, | ||
33 | { 0x000000b4, 0x00000004 }, | ||
34 | { 0x000000b8, 0x00000004 }, | ||
35 | { 0x6f5b4d4c, 0000000000 }, | ||
36 | { 0x4c4c427f, 0000000000 }, | ||
37 | { 0x5b568a92, 0000000000 }, | ||
38 | { 0x4ca09c6d, 0000000000 }, | ||
39 | { 0xad4c4c4c, 0000000000 }, | ||
40 | { 0x4ce1af3d, 0000000000 }, | ||
41 | { 0xd8afafaf, 0000000000 }, | ||
42 | { 0xd64c4cdc, 0000000000 }, | ||
43 | { 0x4cd10d10, 0000000000 }, | ||
44 | { 0x000f0000, 0x00000016 }, | ||
45 | { 0x362f242d, 0000000000 }, | ||
46 | { 0x00000012, 0x00000004 }, | ||
47 | { 0x000f0000, 0x00000016 }, | ||
48 | { 0x362f282d, 0000000000 }, | ||
49 | { 0x000380e7, 0x00000002 }, | ||
50 | { 0x04002c97, 0x00000002 }, | ||
51 | { 0x000f0001, 0x00000016 }, | ||
52 | { 0x333a3730, 0000000000 }, | ||
53 | { 0x000077ef, 0x00000002 }, | ||
54 | { 0x00061000, 0x00000002 }, | ||
55 | { 0x00000021, 0x0000001a }, | ||
56 | { 0x00004000, 0x0000001e }, | ||
57 | { 0x00061000, 0x00000002 }, | ||
58 | { 0x00000021, 0x0000001a }, | ||
59 | { 0x00004000, 0x0000001e }, | ||
60 | { 0x00061000, 0x00000002 }, | ||
61 | { 0x00000021, 0x0000001a }, | ||
62 | { 0x00004000, 0x0000001e }, | ||
63 | { 0x00000017, 0x00000004 }, | ||
64 | { 0x0003802b, 0x00000002 }, | ||
65 | { 0x040067e0, 0x00000002 }, | ||
66 | { 0x00000017, 0x00000004 }, | ||
67 | { 0x000077e0, 0x00000002 }, | ||
68 | { 0x00065000, 0x00000002 }, | ||
69 | { 0x000037e1, 0x00000002 }, | ||
70 | { 0x040067e1, 0x00000006 }, | ||
71 | { 0x000077e0, 0x00000002 }, | ||
72 | { 0x000077e1, 0x00000002 }, | ||
73 | { 0x000077e1, 0x00000006 }, | ||
74 | { 0xffffffff, 0000000000 }, | ||
75 | { 0x10000000, 0000000000 }, | ||
76 | { 0x0003802b, 0x00000002 }, | ||
77 | { 0x040067e0, 0x00000006 }, | ||
78 | { 0x00007675, 0x00000002 }, | ||
79 | { 0x00007676, 0x00000002 }, | ||
80 | { 0x00007677, 0x00000002 }, | ||
81 | { 0x00007678, 0x00000006 }, | ||
82 | { 0x0003802c, 0x00000002 }, | ||
83 | { 0x04002676, 0x00000002 }, | ||
84 | { 0x00007677, 0x00000002 }, | ||
85 | { 0x00007678, 0x00000006 }, | ||
86 | { 0x0000002f, 0x00000018 }, | ||
87 | { 0x0000002f, 0x00000018 }, | ||
88 | { 0000000000, 0x00000006 }, | ||
89 | { 0x00000030, 0x00000018 }, | ||
90 | { 0x00000030, 0x00000018 }, | ||
91 | { 0000000000, 0x00000006 }, | ||
92 | { 0x01605000, 0x00000002 }, | ||
93 | { 0x00065000, 0x00000002 }, | ||
94 | { 0x00098000, 0x00000002 }, | ||
95 | { 0x00061000, 0x00000002 }, | ||
96 | { 0x64c0603e, 0x00000004 }, | ||
97 | { 0x000380e6, 0x00000002 }, | ||
98 | { 0x040025c5, 0x00000002 }, | ||
99 | { 0x00080000, 0x00000016 }, | ||
100 | { 0000000000, 0000000000 }, | ||
101 | { 0x0400251d, 0x00000002 }, | ||
102 | { 0x00007580, 0x00000002 }, | ||
103 | { 0x00067581, 0x00000002 }, | ||
104 | { 0x04002580, 0x00000002 }, | ||
105 | { 0x00067581, 0x00000002 }, | ||
106 | { 0x00000049, 0x00000004 }, | ||
107 | { 0x00005000, 0000000000 }, | ||
108 | { 0x000380e6, 0x00000002 }, | ||
109 | { 0x040025c5, 0x00000002 }, | ||
110 | { 0x00061000, 0x00000002 }, | ||
111 | { 0x0000750e, 0x00000002 }, | ||
112 | { 0x00019000, 0x00000002 }, | ||
113 | { 0x00011055, 0x00000014 }, | ||
114 | { 0x00000055, 0x00000012 }, | ||
115 | { 0x0400250f, 0x00000002 }, | ||
116 | { 0x0000504f, 0x00000004 }, | ||
117 | { 0x000380e6, 0x00000002 }, | ||
118 | { 0x040025c5, 0x00000002 }, | ||
119 | { 0x00007565, 0x00000002 }, | ||
120 | { 0x00007566, 0x00000002 }, | ||
121 | { 0x00000058, 0x00000004 }, | ||
122 | { 0x000380e6, 0x00000002 }, | ||
123 | { 0x040025c5, 0x00000002 }, | ||
124 | { 0x01e655b4, 0x00000002 }, | ||
125 | { 0x4401b0e4, 0x00000002 }, | ||
126 | { 0x01c110e4, 0x00000002 }, | ||
127 | { 0x26667066, 0x00000018 }, | ||
128 | { 0x040c2565, 0x00000002 }, | ||
129 | { 0x00000066, 0x00000018 }, | ||
130 | { 0x04002564, 0x00000002 }, | ||
131 | { 0x00007566, 0x00000002 }, | ||
132 | { 0x0000005d, 0x00000004 }, | ||
133 | { 0x00401069, 0x00000008 }, | ||
134 | { 0x00101000, 0x00000002 }, | ||
135 | { 0x000d80ff, 0x00000002 }, | ||
136 | { 0x0080006c, 0x00000008 }, | ||
137 | { 0x000f9000, 0x00000002 }, | ||
138 | { 0x000e00ff, 0x00000002 }, | ||
139 | { 0000000000, 0x00000006 }, | ||
140 | { 0x0000008f, 0x00000018 }, | ||
141 | { 0x0000005b, 0x00000004 }, | ||
142 | { 0x000380e6, 0x00000002 }, | ||
143 | { 0x040025c5, 0x00000002 }, | ||
144 | { 0x00007576, 0x00000002 }, | ||
145 | { 0x00065000, 0x00000002 }, | ||
146 | { 0x00009000, 0x00000002 }, | ||
147 | { 0x00041000, 0x00000002 }, | ||
148 | { 0x0c00350e, 0x00000002 }, | ||
149 | { 0x00049000, 0x00000002 }, | ||
150 | { 0x00051000, 0x00000002 }, | ||
151 | { 0x01e785f8, 0x00000002 }, | ||
152 | { 0x00200000, 0x00000002 }, | ||
153 | { 0x0060007e, 0x0000000c }, | ||
154 | { 0x00007563, 0x00000002 }, | ||
155 | { 0x006075f0, 0x00000021 }, | ||
156 | { 0x20007073, 0x00000004 }, | ||
157 | { 0x00005073, 0x00000004 }, | ||
158 | { 0x000380e6, 0x00000002 }, | ||
159 | { 0x040025c5, 0x00000002 }, | ||
160 | { 0x00007576, 0x00000002 }, | ||
161 | { 0x00007577, 0x00000002 }, | ||
162 | { 0x0000750e, 0x00000002 }, | ||
163 | { 0x0000750f, 0x00000002 }, | ||
164 | { 0x00a05000, 0x00000002 }, | ||
165 | { 0x00600083, 0x0000000c }, | ||
166 | { 0x006075f0, 0x00000021 }, | ||
167 | { 0x000075f8, 0x00000002 }, | ||
168 | { 0x00000083, 0x00000004 }, | ||
169 | { 0x000a750e, 0x00000002 }, | ||
170 | { 0x000380e6, 0x00000002 }, | ||
171 | { 0x040025c5, 0x00000002 }, | ||
172 | { 0x0020750f, 0x00000002 }, | ||
173 | { 0x00600086, 0x00000004 }, | ||
174 | { 0x00007570, 0x00000002 }, | ||
175 | { 0x00007571, 0x00000002 }, | ||
176 | { 0x00007572, 0x00000006 }, | ||
177 | { 0x000380e6, 0x00000002 }, | ||
178 | { 0x040025c5, 0x00000002 }, | ||
179 | { 0x00005000, 0x00000002 }, | ||
180 | { 0x00a05000, 0x00000002 }, | ||
181 | { 0x00007568, 0x00000002 }, | ||
182 | { 0x00061000, 0x00000002 }, | ||
183 | { 0x00000095, 0x0000000c }, | ||
184 | { 0x00058000, 0x00000002 }, | ||
185 | { 0x0c607562, 0x00000002 }, | ||
186 | { 0x00000097, 0x00000004 }, | ||
187 | { 0x000380e6, 0x00000002 }, | ||
188 | { 0x040025c5, 0x00000002 }, | ||
189 | { 0x00600096, 0x00000004 }, | ||
190 | { 0x400070e5, 0000000000 }, | ||
191 | { 0x000380e6, 0x00000002 }, | ||
192 | { 0x040025c5, 0x00000002 }, | ||
193 | { 0x000380e5, 0x00000002 }, | ||
194 | { 0x000000a8, 0x0000001c }, | ||
195 | { 0x000650aa, 0x00000018 }, | ||
196 | { 0x040025bb, 0x00000002 }, | ||
197 | { 0x000610ab, 0x00000018 }, | ||
198 | { 0x040075bc, 0000000000 }, | ||
199 | { 0x000075bb, 0x00000002 }, | ||
200 | { 0x000075bc, 0000000000 }, | ||
201 | { 0x00090000, 0x00000006 }, | ||
202 | { 0x00090000, 0x00000002 }, | ||
203 | { 0x000d8002, 0x00000006 }, | ||
204 | { 0x00007832, 0x00000002 }, | ||
205 | { 0x00005000, 0x00000002 }, | ||
206 | { 0x000380e7, 0x00000002 }, | ||
207 | { 0x04002c97, 0x00000002 }, | ||
208 | { 0x00007820, 0x00000002 }, | ||
209 | { 0x00007821, 0x00000002 }, | ||
210 | { 0x00007800, 0000000000 }, | ||
211 | { 0x01200000, 0x00000002 }, | ||
212 | { 0x20077000, 0x00000002 }, | ||
213 | { 0x01200000, 0x00000002 }, | ||
214 | { 0x20007000, 0x00000002 }, | ||
215 | { 0x00061000, 0x00000002 }, | ||
216 | { 0x0120751b, 0x00000002 }, | ||
217 | { 0x8040750a, 0x00000002 }, | ||
218 | { 0x8040750b, 0x00000002 }, | ||
219 | { 0x00110000, 0x00000002 }, | ||
220 | { 0x000380e5, 0x00000002 }, | ||
221 | { 0x000000c6, 0x0000001c }, | ||
222 | { 0x000610ab, 0x00000018 }, | ||
223 | { 0x844075bd, 0x00000002 }, | ||
224 | { 0x000610aa, 0x00000018 }, | ||
225 | { 0x840075bb, 0x00000002 }, | ||
226 | { 0x000610ab, 0x00000018 }, | ||
227 | { 0x844075bc, 0x00000002 }, | ||
228 | { 0x000000c9, 0x00000004 }, | ||
229 | { 0x804075bd, 0x00000002 }, | ||
230 | { 0x800075bb, 0x00000002 }, | ||
231 | { 0x804075bc, 0x00000002 }, | ||
232 | { 0x00108000, 0x00000002 }, | ||
233 | { 0x01400000, 0x00000002 }, | ||
234 | { 0x006000cd, 0x0000000c }, | ||
235 | { 0x20c07000, 0x00000020 }, | ||
236 | { 0x000000cf, 0x00000012 }, | ||
237 | { 0x00800000, 0x00000006 }, | ||
238 | { 0x0080751d, 0x00000006 }, | ||
239 | { 0000000000, 0000000000 }, | ||
240 | { 0x0000775c, 0x00000002 }, | ||
241 | { 0x00a05000, 0x00000002 }, | ||
242 | { 0x00661000, 0x00000002 }, | ||
243 | { 0x0460275d, 0x00000020 }, | ||
244 | { 0x00004000, 0000000000 }, | ||
245 | { 0x01e00830, 0x00000002 }, | ||
246 | { 0x21007000, 0000000000 }, | ||
247 | { 0x6464614d, 0000000000 }, | ||
248 | { 0x69687420, 0000000000 }, | ||
249 | { 0x00000073, 0000000000 }, | ||
250 | { 0000000000, 0000000000 }, | ||
251 | { 0x00005000, 0x00000002 }, | ||
252 | { 0x000380d0, 0x00000002 }, | ||
253 | { 0x040025e0, 0x00000002 }, | ||
254 | { 0x000075e1, 0000000000 }, | ||
255 | { 0x00000001, 0000000000 }, | ||
256 | { 0x000380e0, 0x00000002 }, | ||
257 | { 0x04002394, 0x00000002 }, | ||
258 | { 0x00005000, 0000000000 }, | ||
259 | { 0000000000, 0000000000 }, | ||
260 | { 0000000000, 0000000000 }, | ||
261 | { 0x00000008, 0000000000 }, | ||
262 | { 0x00000004, 0000000000 }, | ||
263 | { 0000000000, 0000000000 }, | ||
264 | { 0000000000, 0000000000 }, | ||
265 | { 0000000000, 0000000000 }, | ||
266 | { 0000000000, 0000000000 }, | ||
267 | { 0000000000, 0000000000 }, | ||
268 | { 0000000000, 0000000000 }, | ||
269 | { 0000000000, 0000000000 }, | ||
270 | { 0000000000, 0000000000 }, | ||
271 | { 0000000000, 0000000000 }, | ||
272 | { 0000000000, 0000000000 }, | ||
273 | { 0000000000, 0000000000 }, | ||
274 | { 0000000000, 0000000000 }, | ||
275 | { 0000000000, 0000000000 }, | ||
276 | { 0000000000, 0000000000 }, | ||
277 | { 0000000000, 0000000000 }, | ||
278 | { 0000000000, 0000000000 }, | ||
279 | { 0000000000, 0000000000 }, | ||
280 | { 0000000000, 0000000000 }, | ||
281 | { 0000000000, 0000000000 }, | ||
282 | { 0000000000, 0000000000 }, | ||
283 | { 0000000000, 0000000000 }, | ||
284 | { 0000000000, 0000000000 }, | ||
285 | { 0000000000, 0000000000 }, | ||
286 | { 0000000000, 0000000000 }, | ||
287 | }; | ||
288 | |||
289 | static const u32 R200_cp_microcode[][2] = { | ||
290 | { 0x21007000, 0000000000 }, | ||
291 | { 0x20007000, 0000000000 }, | ||
292 | { 0x000000bf, 0x00000004 }, | ||
293 | { 0x000000c3, 0x00000004 }, | ||
294 | { 0x7a685e5d, 0000000000 }, | ||
295 | { 0x5d5d5588, 0000000000 }, | ||
296 | { 0x68659197, 0000000000 }, | ||
297 | { 0x5da19f78, 0000000000 }, | ||
298 | { 0x5d5d5d5d, 0000000000 }, | ||
299 | { 0x5dee5d50, 0000000000 }, | ||
300 | { 0xf2acacac, 0000000000 }, | ||
301 | { 0xe75df9e9, 0000000000 }, | ||
302 | { 0xb1dd0e11, 0000000000 }, | ||
303 | { 0xe2afafaf, 0000000000 }, | ||
304 | { 0x000f0000, 0x00000016 }, | ||
305 | { 0x452f232d, 0000000000 }, | ||
306 | { 0x00000013, 0x00000004 }, | ||
307 | { 0x000f0000, 0x00000016 }, | ||
308 | { 0x452f272d, 0000000000 }, | ||
309 | { 0x000f0001, 0x00000016 }, | ||
310 | { 0x3e4d4a37, 0000000000 }, | ||
311 | { 0x000077ef, 0x00000002 }, | ||
312 | { 0x00061000, 0x00000002 }, | ||
313 | { 0x00000020, 0x0000001a }, | ||
314 | { 0x00004000, 0x0000001e }, | ||
315 | { 0x00061000, 0x00000002 }, | ||
316 | { 0x00000020, 0x0000001a }, | ||
317 | { 0x00004000, 0x0000001e }, | ||
318 | { 0x00061000, 0x00000002 }, | ||
319 | { 0x00000020, 0x0000001a }, | ||
320 | { 0x00004000, 0x0000001e }, | ||
321 | { 0x00000016, 0x00000004 }, | ||
322 | { 0x0003802a, 0x00000002 }, | ||
323 | { 0x040067e0, 0x00000002 }, | ||
324 | { 0x00000016, 0x00000004 }, | ||
325 | { 0x000077e0, 0x00000002 }, | ||
326 | { 0x00065000, 0x00000002 }, | ||
327 | { 0x000037e1, 0x00000002 }, | ||
328 | { 0x040067e1, 0x00000006 }, | ||
329 | { 0x000077e0, 0x00000002 }, | ||
330 | { 0x000077e1, 0x00000002 }, | ||
331 | { 0x000077e1, 0x00000006 }, | ||
332 | { 0xffffffff, 0000000000 }, | ||
333 | { 0x10000000, 0000000000 }, | ||
334 | { 0x07f007f0, 0000000000 }, | ||
335 | { 0x0003802a, 0x00000002 }, | ||
336 | { 0x040067e0, 0x00000006 }, | ||
337 | { 0x0003802c, 0x00000002 }, | ||
338 | { 0x04002741, 0x00000002 }, | ||
339 | { 0x04002741, 0x00000002 }, | ||
340 | { 0x04002743, 0x00000002 }, | ||
341 | { 0x00007675, 0x00000002 }, | ||
342 | { 0x00007676, 0x00000002 }, | ||
343 | { 0x00007677, 0x00000002 }, | ||
344 | { 0x00007678, 0x00000006 }, | ||
345 | { 0x0003802c, 0x00000002 }, | ||
346 | { 0x04002741, 0x00000002 }, | ||
347 | { 0x04002741, 0x00000002 }, | ||
348 | { 0x04002743, 0x00000002 }, | ||
349 | { 0x00007676, 0x00000002 }, | ||
350 | { 0x00007677, 0x00000002 }, | ||
351 | { 0x00007678, 0x00000006 }, | ||
352 | { 0x0003802b, 0x00000002 }, | ||
353 | { 0x04002676, 0x00000002 }, | ||
354 | { 0x00007677, 0x00000002 }, | ||
355 | { 0x0003802c, 0x00000002 }, | ||
356 | { 0x04002741, 0x00000002 }, | ||
357 | { 0x04002743, 0x00000002 }, | ||
358 | { 0x00007678, 0x00000006 }, | ||
359 | { 0x0003802c, 0x00000002 }, | ||
360 | { 0x04002741, 0x00000002 }, | ||
361 | { 0x04002741, 0x00000002 }, | ||
362 | { 0x04002743, 0x00000002 }, | ||
363 | { 0x00007678, 0x00000006 }, | ||
364 | { 0x0000002f, 0x00000018 }, | ||
365 | { 0x0000002f, 0x00000018 }, | ||
366 | { 0000000000, 0x00000006 }, | ||
367 | { 0x00000037, 0x00000018 }, | ||
368 | { 0x00000037, 0x00000018 }, | ||
369 | { 0000000000, 0x00000006 }, | ||
370 | { 0x01605000, 0x00000002 }, | ||
371 | { 0x00065000, 0x00000002 }, | ||
372 | { 0x00098000, 0x00000002 }, | ||
373 | { 0x00061000, 0x00000002 }, | ||
374 | { 0x64c06051, 0x00000004 }, | ||
375 | { 0x00080000, 0x00000016 }, | ||
376 | { 0000000000, 0000000000 }, | ||
377 | { 0x0400251d, 0x00000002 }, | ||
378 | { 0x00007580, 0x00000002 }, | ||
379 | { 0x00067581, 0x00000002 }, | ||
380 | { 0x04002580, 0x00000002 }, | ||
381 | { 0x00067581, 0x00000002 }, | ||
382 | { 0x0000005a, 0x00000004 }, | ||
383 | { 0x00005000, 0000000000 }, | ||
384 | { 0x00061000, 0x00000002 }, | ||
385 | { 0x0000750e, 0x00000002 }, | ||
386 | { 0x00019000, 0x00000002 }, | ||
387 | { 0x00011064, 0x00000014 }, | ||
388 | { 0x00000064, 0x00000012 }, | ||
389 | { 0x0400250f, 0x00000002 }, | ||
390 | { 0x0000505e, 0x00000004 }, | ||
391 | { 0x00007565, 0x00000002 }, | ||
392 | { 0x00007566, 0x00000002 }, | ||
393 | { 0x00000065, 0x00000004 }, | ||
394 | { 0x01e655b4, 0x00000002 }, | ||
395 | { 0x4401b0f0, 0x00000002 }, | ||
396 | { 0x01c110f0, 0x00000002 }, | ||
397 | { 0x26667071, 0x00000018 }, | ||
398 | { 0x040c2565, 0x00000002 }, | ||
399 | { 0x00000071, 0x00000018 }, | ||
400 | { 0x04002564, 0x00000002 }, | ||
401 | { 0x00007566, 0x00000002 }, | ||
402 | { 0x00000068, 0x00000004 }, | ||
403 | { 0x00401074, 0x00000008 }, | ||
404 | { 0x00101000, 0x00000002 }, | ||
405 | { 0x000d80ff, 0x00000002 }, | ||
406 | { 0x00800077, 0x00000008 }, | ||
407 | { 0x000f9000, 0x00000002 }, | ||
408 | { 0x000e00ff, 0x00000002 }, | ||
409 | { 0000000000, 0x00000006 }, | ||
410 | { 0x00000094, 0x00000018 }, | ||
411 | { 0x00000068, 0x00000004 }, | ||
412 | { 0x00007576, 0x00000002 }, | ||
413 | { 0x00065000, 0x00000002 }, | ||
414 | { 0x00009000, 0x00000002 }, | ||
415 | { 0x00041000, 0x00000002 }, | ||
416 | { 0x0c00350e, 0x00000002 }, | ||
417 | { 0x00049000, 0x00000002 }, | ||
418 | { 0x00051000, 0x00000002 }, | ||
419 | { 0x01e785f8, 0x00000002 }, | ||
420 | { 0x00200000, 0x00000002 }, | ||
421 | { 0x00600087, 0x0000000c }, | ||
422 | { 0x00007563, 0x00000002 }, | ||
423 | { 0x006075f0, 0x00000021 }, | ||
424 | { 0x2000707c, 0x00000004 }, | ||
425 | { 0x0000507c, 0x00000004 }, | ||
426 | { 0x00007576, 0x00000002 }, | ||
427 | { 0x00007577, 0x00000002 }, | ||
428 | { 0x0000750e, 0x00000002 }, | ||
429 | { 0x0000750f, 0x00000002 }, | ||
430 | { 0x00a05000, 0x00000002 }, | ||
431 | { 0x0060008a, 0x0000000c }, | ||
432 | { 0x006075f0, 0x00000021 }, | ||
433 | { 0x000075f8, 0x00000002 }, | ||
434 | { 0x0000008a, 0x00000004 }, | ||
435 | { 0x000a750e, 0x00000002 }, | ||
436 | { 0x0020750f, 0x00000002 }, | ||
437 | { 0x0060008d, 0x00000004 }, | ||
438 | { 0x00007570, 0x00000002 }, | ||
439 | { 0x00007571, 0x00000002 }, | ||
440 | { 0x00007572, 0x00000006 }, | ||
441 | { 0x00005000, 0x00000002 }, | ||
442 | { 0x00a05000, 0x00000002 }, | ||
443 | { 0x00007568, 0x00000002 }, | ||
444 | { 0x00061000, 0x00000002 }, | ||
445 | { 0x00000098, 0x0000000c }, | ||
446 | { 0x00058000, 0x00000002 }, | ||
447 | { 0x0c607562, 0x00000002 }, | ||
448 | { 0x0000009a, 0x00000004 }, | ||
449 | { 0x00600099, 0x00000004 }, | ||
450 | { 0x400070f1, 0000000000 }, | ||
451 | { 0x000380f1, 0x00000002 }, | ||
452 | { 0x000000a7, 0x0000001c }, | ||
453 | { 0x000650a9, 0x00000018 }, | ||
454 | { 0x040025bb, 0x00000002 }, | ||
455 | { 0x000610aa, 0x00000018 }, | ||
456 | { 0x040075bc, 0000000000 }, | ||
457 | { 0x000075bb, 0x00000002 }, | ||
458 | { 0x000075bc, 0000000000 }, | ||
459 | { 0x00090000, 0x00000006 }, | ||
460 | { 0x00090000, 0x00000002 }, | ||
461 | { 0x000d8002, 0x00000006 }, | ||
462 | { 0x00005000, 0x00000002 }, | ||
463 | { 0x00007821, 0x00000002 }, | ||
464 | { 0x00007800, 0000000000 }, | ||
465 | { 0x00007821, 0x00000002 }, | ||
466 | { 0x00007800, 0000000000 }, | ||
467 | { 0x01665000, 0x00000002 }, | ||
468 | { 0x000a0000, 0x00000002 }, | ||
469 | { 0x000671cc, 0x00000002 }, | ||
470 | { 0x0286f1cd, 0x00000002 }, | ||
471 | { 0x000000b7, 0x00000010 }, | ||
472 | { 0x21007000, 0000000000 }, | ||
473 | { 0x000000be, 0x0000001c }, | ||
474 | { 0x00065000, 0x00000002 }, | ||
475 | { 0x000a0000, 0x00000002 }, | ||
476 | { 0x00061000, 0x00000002 }, | ||
477 | { 0x000b0000, 0x00000002 }, | ||
478 | { 0x38067000, 0x00000002 }, | ||
479 | { 0x000a00ba, 0x00000004 }, | ||
480 | { 0x20007000, 0000000000 }, | ||
481 | { 0x01200000, 0x00000002 }, | ||
482 | { 0x20077000, 0x00000002 }, | ||
483 | { 0x01200000, 0x00000002 }, | ||
484 | { 0x20007000, 0000000000 }, | ||
485 | { 0x00061000, 0x00000002 }, | ||
486 | { 0x0120751b, 0x00000002 }, | ||
487 | { 0x8040750a, 0x00000002 }, | ||
488 | { 0x8040750b, 0x00000002 }, | ||
489 | { 0x00110000, 0x00000002 }, | ||
490 | { 0x000380f1, 0x00000002 }, | ||
491 | { 0x000000d1, 0x0000001c }, | ||
492 | { 0x000610aa, 0x00000018 }, | ||
493 | { 0x844075bd, 0x00000002 }, | ||
494 | { 0x000610a9, 0x00000018 }, | ||
495 | { 0x840075bb, 0x00000002 }, | ||
496 | { 0x000610aa, 0x00000018 }, | ||
497 | { 0x844075bc, 0x00000002 }, | ||
498 | { 0x000000d4, 0x00000004 }, | ||
499 | { 0x804075bd, 0x00000002 }, | ||
500 | { 0x800075bb, 0x00000002 }, | ||
501 | { 0x804075bc, 0x00000002 }, | ||
502 | { 0x00108000, 0x00000002 }, | ||
503 | { 0x01400000, 0x00000002 }, | ||
504 | { 0x006000d8, 0x0000000c }, | ||
505 | { 0x20c07000, 0x00000020 }, | ||
506 | { 0x000000da, 0x00000012 }, | ||
507 | { 0x00800000, 0x00000006 }, | ||
508 | { 0x0080751d, 0x00000006 }, | ||
509 | { 0x000025bb, 0x00000002 }, | ||
510 | { 0x000040d4, 0x00000004 }, | ||
511 | { 0x0000775c, 0x00000002 }, | ||
512 | { 0x00a05000, 0x00000002 }, | ||
513 | { 0x00661000, 0x00000002 }, | ||
514 | { 0x0460275d, 0x00000020 }, | ||
515 | { 0x00004000, 0000000000 }, | ||
516 | { 0x00007999, 0x00000002 }, | ||
517 | { 0x00a05000, 0x00000002 }, | ||
518 | { 0x00661000, 0x00000002 }, | ||
519 | { 0x0460299b, 0x00000020 }, | ||
520 | { 0x00004000, 0000000000 }, | ||
521 | { 0x01e00830, 0x00000002 }, | ||
522 | { 0x21007000, 0000000000 }, | ||
523 | { 0x00005000, 0x00000002 }, | ||
524 | { 0x00038056, 0x00000002 }, | ||
525 | { 0x040025e0, 0x00000002 }, | ||
526 | { 0x000075e1, 0000000000 }, | ||
527 | { 0x00000001, 0000000000 }, | ||
528 | { 0x000380ed, 0x00000002 }, | ||
529 | { 0x04007394, 0000000000 }, | ||
530 | { 0000000000, 0000000000 }, | ||
531 | { 0000000000, 0000000000 }, | ||
532 | { 0x000078c4, 0x00000002 }, | ||
533 | { 0x000078c5, 0x00000002 }, | ||
534 | { 0x000078c6, 0x00000002 }, | ||
535 | { 0x00007924, 0x00000002 }, | ||
536 | { 0x00007925, 0x00000002 }, | ||
537 | { 0x00007926, 0x00000002 }, | ||
538 | { 0x000000f2, 0x00000004 }, | ||
539 | { 0x00007924, 0x00000002 }, | ||
540 | { 0x00007925, 0x00000002 }, | ||
541 | { 0x00007926, 0x00000002 }, | ||
542 | { 0x000000f9, 0x00000004 }, | ||
543 | { 0000000000, 0000000000 }, | ||
544 | { 0000000000, 0000000000 }, | ||
545 | { 0000000000, 0000000000 }, | ||
546 | }; | ||
547 | |||
548 | static const u32 R300_cp_microcode[][2] = { | ||
549 | { 0x4200e000, 0000000000 }, | ||
550 | { 0x4000e000, 0000000000 }, | ||
551 | { 0x000000ae, 0x00000008 }, | ||
552 | { 0x000000b2, 0x00000008 }, | ||
553 | { 0x67554b4a, 0000000000 }, | ||
554 | { 0x4a4a4475, 0000000000 }, | ||
555 | { 0x55527d83, 0000000000 }, | ||
556 | { 0x4a8c8b65, 0000000000 }, | ||
557 | { 0x4aef4af6, 0000000000 }, | ||
558 | { 0x4ae14a4a, 0000000000 }, | ||
559 | { 0xe4979797, 0000000000 }, | ||
560 | { 0xdb4aebdd, 0000000000 }, | ||
561 | { 0x9ccc4a4a, 0000000000 }, | ||
562 | { 0xd1989898, 0000000000 }, | ||
563 | { 0x4a0f9ad6, 0000000000 }, | ||
564 | { 0x000ca000, 0x00000004 }, | ||
565 | { 0x000d0012, 0x00000038 }, | ||
566 | { 0x0000e8b4, 0x00000004 }, | ||
567 | { 0x000d0014, 0x00000038 }, | ||
568 | { 0x0000e8b6, 0x00000004 }, | ||
569 | { 0x000d0016, 0x00000038 }, | ||
570 | { 0x0000e854, 0x00000004 }, | ||
571 | { 0x000d0018, 0x00000038 }, | ||
572 | { 0x0000e855, 0x00000004 }, | ||
573 | { 0x000d001a, 0x00000038 }, | ||
574 | { 0x0000e856, 0x00000004 }, | ||
575 | { 0x000d001c, 0x00000038 }, | ||
576 | { 0x0000e857, 0x00000004 }, | ||
577 | { 0x000d001e, 0x00000038 }, | ||
578 | { 0x0000e824, 0x00000004 }, | ||
579 | { 0x000d0020, 0x00000038 }, | ||
580 | { 0x0000e825, 0x00000004 }, | ||
581 | { 0x000d0022, 0x00000038 }, | ||
582 | { 0x0000e830, 0x00000004 }, | ||
583 | { 0x000d0024, 0x00000038 }, | ||
584 | { 0x0000f0c0, 0x00000004 }, | ||
585 | { 0x000d0026, 0x00000038 }, | ||
586 | { 0x0000f0c1, 0x00000004 }, | ||
587 | { 0x000d0028, 0x00000038 }, | ||
588 | { 0x0000f041, 0x00000004 }, | ||
589 | { 0x000d002a, 0x00000038 }, | ||
590 | { 0x0000f184, 0x00000004 }, | ||
591 | { 0x000d002c, 0x00000038 }, | ||
592 | { 0x0000f185, 0x00000004 }, | ||
593 | { 0x000d002e, 0x00000038 }, | ||
594 | { 0x0000f186, 0x00000004 }, | ||
595 | { 0x000d0030, 0x00000038 }, | ||
596 | { 0x0000f187, 0x00000004 }, | ||
597 | { 0x000d0032, 0x00000038 }, | ||
598 | { 0x0000f180, 0x00000004 }, | ||
599 | { 0x000d0034, 0x00000038 }, | ||
600 | { 0x0000f393, 0x00000004 }, | ||
601 | { 0x000d0036, 0x00000038 }, | ||
602 | { 0x0000f38a, 0x00000004 }, | ||
603 | { 0x000d0038, 0x00000038 }, | ||
604 | { 0x0000f38e, 0x00000004 }, | ||
605 | { 0x0000e821, 0x00000004 }, | ||
606 | { 0x0140a000, 0x00000004 }, | ||
607 | { 0x00000043, 0x00000018 }, | ||
608 | { 0x00cce800, 0x00000004 }, | ||
609 | { 0x001b0001, 0x00000004 }, | ||
610 | { 0x08004800, 0x00000004 }, | ||
611 | { 0x001b0001, 0x00000004 }, | ||
612 | { 0x08004800, 0x00000004 }, | ||
613 | { 0x001b0001, 0x00000004 }, | ||
614 | { 0x08004800, 0x00000004 }, | ||
615 | { 0x0000003a, 0x00000008 }, | ||
616 | { 0x0000a000, 0000000000 }, | ||
617 | { 0x2000451d, 0x00000004 }, | ||
618 | { 0x0000e580, 0x00000004 }, | ||
619 | { 0x000ce581, 0x00000004 }, | ||
620 | { 0x08004580, 0x00000004 }, | ||
621 | { 0x000ce581, 0x00000004 }, | ||
622 | { 0x00000047, 0x00000008 }, | ||
623 | { 0x0000a000, 0000000000 }, | ||
624 | { 0x000c2000, 0x00000004 }, | ||
625 | { 0x0000e50e, 0x00000004 }, | ||
626 | { 0x00032000, 0x00000004 }, | ||
627 | { 0x00022051, 0x00000028 }, | ||
628 | { 0x00000051, 0x00000024 }, | ||
629 | { 0x0800450f, 0x00000004 }, | ||
630 | { 0x0000a04b, 0x00000008 }, | ||
631 | { 0x0000e565, 0x00000004 }, | ||
632 | { 0x0000e566, 0x00000004 }, | ||
633 | { 0x00000052, 0x00000008 }, | ||
634 | { 0x03cca5b4, 0x00000004 }, | ||
635 | { 0x05432000, 0x00000004 }, | ||
636 | { 0x00022000, 0x00000004 }, | ||
637 | { 0x4ccce05e, 0x00000030 }, | ||
638 | { 0x08274565, 0x00000004 }, | ||
639 | { 0x0000005e, 0x00000030 }, | ||
640 | { 0x08004564, 0x00000004 }, | ||
641 | { 0x0000e566, 0x00000004 }, | ||
642 | { 0x00000055, 0x00000008 }, | ||
643 | { 0x00802061, 0x00000010 }, | ||
644 | { 0x00202000, 0x00000004 }, | ||
645 | { 0x001b00ff, 0x00000004 }, | ||
646 | { 0x01000064, 0x00000010 }, | ||
647 | { 0x001f2000, 0x00000004 }, | ||
648 | { 0x001c00ff, 0x00000004 }, | ||
649 | { 0000000000, 0x0000000c }, | ||
650 | { 0x00000080, 0x00000030 }, | ||
651 | { 0x00000055, 0x00000008 }, | ||
652 | { 0x0000e576, 0x00000004 }, | ||
653 | { 0x000ca000, 0x00000004 }, | ||
654 | { 0x00012000, 0x00000004 }, | ||
655 | { 0x00082000, 0x00000004 }, | ||
656 | { 0x1800650e, 0x00000004 }, | ||
657 | { 0x00092000, 0x00000004 }, | ||
658 | { 0x000a2000, 0x00000004 }, | ||
659 | { 0x000f0000, 0x00000004 }, | ||
660 | { 0x00400000, 0x00000004 }, | ||
661 | { 0x00000074, 0x00000018 }, | ||
662 | { 0x0000e563, 0x00000004 }, | ||
663 | { 0x00c0e5f9, 0x000000c2 }, | ||
664 | { 0x00000069, 0x00000008 }, | ||
665 | { 0x0000a069, 0x00000008 }, | ||
666 | { 0x0000e576, 0x00000004 }, | ||
667 | { 0x0000e577, 0x00000004 }, | ||
668 | { 0x0000e50e, 0x00000004 }, | ||
669 | { 0x0000e50f, 0x00000004 }, | ||
670 | { 0x0140a000, 0x00000004 }, | ||
671 | { 0x00000077, 0x00000018 }, | ||
672 | { 0x00c0e5f9, 0x000000c2 }, | ||
673 | { 0x00000077, 0x00000008 }, | ||
674 | { 0x0014e50e, 0x00000004 }, | ||
675 | { 0x0040e50f, 0x00000004 }, | ||
676 | { 0x00c0007a, 0x00000008 }, | ||
677 | { 0x0000e570, 0x00000004 }, | ||
678 | { 0x0000e571, 0x00000004 }, | ||
679 | { 0x0000e572, 0x0000000c }, | ||
680 | { 0x0000a000, 0x00000004 }, | ||
681 | { 0x0140a000, 0x00000004 }, | ||
682 | { 0x0000e568, 0x00000004 }, | ||
683 | { 0x000c2000, 0x00000004 }, | ||
684 | { 0x00000084, 0x00000018 }, | ||
685 | { 0x000b0000, 0x00000004 }, | ||
686 | { 0x18c0e562, 0x00000004 }, | ||
687 | { 0x00000086, 0x00000008 }, | ||
688 | { 0x00c00085, 0x00000008 }, | ||
689 | { 0x000700e3, 0x00000004 }, | ||
690 | { 0x00000092, 0x00000038 }, | ||
691 | { 0x000ca094, 0x00000030 }, | ||
692 | { 0x080045bb, 0x00000004 }, | ||
693 | { 0x000c2095, 0x00000030 }, | ||
694 | { 0x0800e5bc, 0000000000 }, | ||
695 | { 0x0000e5bb, 0x00000004 }, | ||
696 | { 0x0000e5bc, 0000000000 }, | ||
697 | { 0x00120000, 0x0000000c }, | ||
698 | { 0x00120000, 0x00000004 }, | ||
699 | { 0x001b0002, 0x0000000c }, | ||
700 | { 0x0000a000, 0x00000004 }, | ||
701 | { 0x0000e821, 0x00000004 }, | ||
702 | { 0x0000e800, 0000000000 }, | ||
703 | { 0x0000e821, 0x00000004 }, | ||
704 | { 0x0000e82e, 0000000000 }, | ||
705 | { 0x02cca000, 0x00000004 }, | ||
706 | { 0x00140000, 0x00000004 }, | ||
707 | { 0x000ce1cc, 0x00000004 }, | ||
708 | { 0x050de1cd, 0x00000004 }, | ||
709 | { 0x00400000, 0x00000004 }, | ||
710 | { 0x000000a4, 0x00000018 }, | ||
711 | { 0x00c0a000, 0x00000004 }, | ||
712 | { 0x000000a1, 0x00000008 }, | ||
713 | { 0x000000a6, 0x00000020 }, | ||
714 | { 0x4200e000, 0000000000 }, | ||
715 | { 0x000000ad, 0x00000038 }, | ||
716 | { 0x000ca000, 0x00000004 }, | ||
717 | { 0x00140000, 0x00000004 }, | ||
718 | { 0x000c2000, 0x00000004 }, | ||
719 | { 0x00160000, 0x00000004 }, | ||
720 | { 0x700ce000, 0x00000004 }, | ||
721 | { 0x001400a9, 0x00000008 }, | ||
722 | { 0x4000e000, 0000000000 }, | ||
723 | { 0x02400000, 0x00000004 }, | ||
724 | { 0x400ee000, 0x00000004 }, | ||
725 | { 0x02400000, 0x00000004 }, | ||
726 | { 0x4000e000, 0000000000 }, | ||
727 | { 0x000c2000, 0x00000004 }, | ||
728 | { 0x0240e51b, 0x00000004 }, | ||
729 | { 0x0080e50a, 0x00000005 }, | ||
730 | { 0x0080e50b, 0x00000005 }, | ||
731 | { 0x00220000, 0x00000004 }, | ||
732 | { 0x000700e3, 0x00000004 }, | ||
733 | { 0x000000c0, 0x00000038 }, | ||
734 | { 0x000c2095, 0x00000030 }, | ||
735 | { 0x0880e5bd, 0x00000005 }, | ||
736 | { 0x000c2094, 0x00000030 }, | ||
737 | { 0x0800e5bb, 0x00000005 }, | ||
738 | { 0x000c2095, 0x00000030 }, | ||
739 | { 0x0880e5bc, 0x00000005 }, | ||
740 | { 0x000000c3, 0x00000008 }, | ||
741 | { 0x0080e5bd, 0x00000005 }, | ||
742 | { 0x0000e5bb, 0x00000005 }, | ||
743 | { 0x0080e5bc, 0x00000005 }, | ||
744 | { 0x00210000, 0x00000004 }, | ||
745 | { 0x02800000, 0x00000004 }, | ||
746 | { 0x00c000c7, 0x00000018 }, | ||
747 | { 0x4180e000, 0x00000040 }, | ||
748 | { 0x000000c9, 0x00000024 }, | ||
749 | { 0x01000000, 0x0000000c }, | ||
750 | { 0x0100e51d, 0x0000000c }, | ||
751 | { 0x000045bb, 0x00000004 }, | ||
752 | { 0x000080c3, 0x00000008 }, | ||
753 | { 0x0000f3ce, 0x00000004 }, | ||
754 | { 0x0140a000, 0x00000004 }, | ||
755 | { 0x00cc2000, 0x00000004 }, | ||
756 | { 0x08c053cf, 0x00000040 }, | ||
757 | { 0x00008000, 0000000000 }, | ||
758 | { 0x0000f3d2, 0x00000004 }, | ||
759 | { 0x0140a000, 0x00000004 }, | ||
760 | { 0x00cc2000, 0x00000004 }, | ||
761 | { 0x08c053d3, 0x00000040 }, | ||
762 | { 0x00008000, 0000000000 }, | ||
763 | { 0x0000f39d, 0x00000004 }, | ||
764 | { 0x0140a000, 0x00000004 }, | ||
765 | { 0x00cc2000, 0x00000004 }, | ||
766 | { 0x08c0539e, 0x00000040 }, | ||
767 | { 0x00008000, 0000000000 }, | ||
768 | { 0x03c00830, 0x00000004 }, | ||
769 | { 0x4200e000, 0000000000 }, | ||
770 | { 0x0000a000, 0x00000004 }, | ||
771 | { 0x200045e0, 0x00000004 }, | ||
772 | { 0x0000e5e1, 0000000000 }, | ||
773 | { 0x00000001, 0000000000 }, | ||
774 | { 0x000700e0, 0x00000004 }, | ||
775 | { 0x0800e394, 0000000000 }, | ||
776 | { 0000000000, 0000000000 }, | ||
777 | { 0x0000e8c4, 0x00000004 }, | ||
778 | { 0x0000e8c5, 0x00000004 }, | ||
779 | { 0x0000e8c6, 0x00000004 }, | ||
780 | { 0x0000e928, 0x00000004 }, | ||
781 | { 0x0000e929, 0x00000004 }, | ||
782 | { 0x0000e92a, 0x00000004 }, | ||
783 | { 0x000000e4, 0x00000008 }, | ||
784 | { 0x0000e928, 0x00000004 }, | ||
785 | { 0x0000e929, 0x00000004 }, | ||
786 | { 0x0000e92a, 0x00000004 }, | ||
787 | { 0x000000eb, 0x00000008 }, | ||
788 | { 0x02c02000, 0x00000004 }, | ||
789 | { 0x00060000, 0x00000004 }, | ||
790 | { 0x000000f3, 0x00000034 }, | ||
791 | { 0x000000f0, 0x00000008 }, | ||
792 | { 0x00008000, 0x00000004 }, | ||
793 | { 0xc000e000, 0000000000 }, | ||
794 | { 0000000000, 0000000000 }, | ||
795 | { 0x000c2000, 0x00000004 }, | ||
796 | { 0x001d0018, 0x00000004 }, | ||
797 | { 0x001a0001, 0x00000004 }, | ||
798 | { 0x000000fb, 0x00000034 }, | ||
799 | { 0x0000004a, 0x00000008 }, | ||
800 | { 0x0500a04a, 0x00000008 }, | ||
801 | { 0000000000, 0000000000 }, | ||
802 | { 0000000000, 0000000000 }, | ||
803 | { 0000000000, 0000000000 }, | ||
804 | { 0000000000, 0000000000 }, | ||
805 | }; | ||
806 | |||
807 | static const u32 R420_cp_microcode[][2] = { | ||
808 | { 0x4200e000, 0000000000 }, | ||
809 | { 0x4000e000, 0000000000 }, | ||
810 | { 0x00000099, 0x00000008 }, | ||
811 | { 0x0000009d, 0x00000008 }, | ||
812 | { 0x4a554b4a, 0000000000 }, | ||
813 | { 0x4a4a4467, 0000000000 }, | ||
814 | { 0x55526f75, 0000000000 }, | ||
815 | { 0x4a7e7d65, 0000000000 }, | ||
816 | { 0xd9d3dff6, 0000000000 }, | ||
817 | { 0x4ac54a4a, 0000000000 }, | ||
818 | { 0xc8828282, 0000000000 }, | ||
819 | { 0xbf4acfc1, 0000000000 }, | ||
820 | { 0x87b04a4a, 0000000000 }, | ||
821 | { 0xb5838383, 0000000000 }, | ||
822 | { 0x4a0f85ba, 0000000000 }, | ||
823 | { 0x000ca000, 0x00000004 }, | ||
824 | { 0x000d0012, 0x00000038 }, | ||
825 | { 0x0000e8b4, 0x00000004 }, | ||
826 | { 0x000d0014, 0x00000038 }, | ||
827 | { 0x0000e8b6, 0x00000004 }, | ||
828 | { 0x000d0016, 0x00000038 }, | ||
829 | { 0x0000e854, 0x00000004 }, | ||
830 | { 0x000d0018, 0x00000038 }, | ||
831 | { 0x0000e855, 0x00000004 }, | ||
832 | { 0x000d001a, 0x00000038 }, | ||
833 | { 0x0000e856, 0x00000004 }, | ||
834 | { 0x000d001c, 0x00000038 }, | ||
835 | { 0x0000e857, 0x00000004 }, | ||
836 | { 0x000d001e, 0x00000038 }, | ||
837 | { 0x0000e824, 0x00000004 }, | ||
838 | { 0x000d0020, 0x00000038 }, | ||
839 | { 0x0000e825, 0x00000004 }, | ||
840 | { 0x000d0022, 0x00000038 }, | ||
841 | { 0x0000e830, 0x00000004 }, | ||
842 | { 0x000d0024, 0x00000038 }, | ||
843 | { 0x0000f0c0, 0x00000004 }, | ||
844 | { 0x000d0026, 0x00000038 }, | ||
845 | { 0x0000f0c1, 0x00000004 }, | ||
846 | { 0x000d0028, 0x00000038 }, | ||
847 | { 0x0000f041, 0x00000004 }, | ||
848 | { 0x000d002a, 0x00000038 }, | ||
849 | { 0x0000f184, 0x00000004 }, | ||
850 | { 0x000d002c, 0x00000038 }, | ||
851 | { 0x0000f185, 0x00000004 }, | ||
852 | { 0x000d002e, 0x00000038 }, | ||
853 | { 0x0000f186, 0x00000004 }, | ||
854 | { 0x000d0030, 0x00000038 }, | ||
855 | { 0x0000f187, 0x00000004 }, | ||
856 | { 0x000d0032, 0x00000038 }, | ||
857 | { 0x0000f180, 0x00000004 }, | ||
858 | { 0x000d0034, 0x00000038 }, | ||
859 | { 0x0000f393, 0x00000004 }, | ||
860 | { 0x000d0036, 0x00000038 }, | ||
861 | { 0x0000f38a, 0x00000004 }, | ||
862 | { 0x000d0038, 0x00000038 }, | ||
863 | { 0x0000f38e, 0x00000004 }, | ||
864 | { 0x0000e821, 0x00000004 }, | ||
865 | { 0x0140a000, 0x00000004 }, | ||
866 | { 0x00000043, 0x00000018 }, | ||
867 | { 0x00cce800, 0x00000004 }, | ||
868 | { 0x001b0001, 0x00000004 }, | ||
869 | { 0x08004800, 0x00000004 }, | ||
870 | { 0x001b0001, 0x00000004 }, | ||
871 | { 0x08004800, 0x00000004 }, | ||
872 | { 0x001b0001, 0x00000004 }, | ||
873 | { 0x08004800, 0x00000004 }, | ||
874 | { 0x0000003a, 0x00000008 }, | ||
875 | { 0x0000a000, 0000000000 }, | ||
876 | { 0x2000451d, 0x00000004 }, | ||
877 | { 0x0000e580, 0x00000004 }, | ||
878 | { 0x000ce581, 0x00000004 }, | ||
879 | { 0x08004580, 0x00000004 }, | ||
880 | { 0x000ce581, 0x00000004 }, | ||
881 | { 0x00000047, 0x00000008 }, | ||
882 | { 0x0000a000, 0000000000 }, | ||
883 | { 0x000c2000, 0x00000004 }, | ||
884 | { 0x0000e50e, 0x00000004 }, | ||
885 | { 0x00032000, 0x00000004 }, | ||
886 | { 0x00022051, 0x00000028 }, | ||
887 | { 0x00000051, 0x00000024 }, | ||
888 | { 0x0800450f, 0x00000004 }, | ||
889 | { 0x0000a04b, 0x00000008 }, | ||
890 | { 0x0000e565, 0x00000004 }, | ||
891 | { 0x0000e566, 0x00000004 }, | ||
892 | { 0x00000052, 0x00000008 }, | ||
893 | { 0x03cca5b4, 0x00000004 }, | ||
894 | { 0x05432000, 0x00000004 }, | ||
895 | { 0x00022000, 0x00000004 }, | ||
896 | { 0x4ccce05e, 0x00000030 }, | ||
897 | { 0x08274565, 0x00000004 }, | ||
898 | { 0x0000005e, 0x00000030 }, | ||
899 | { 0x08004564, 0x00000004 }, | ||
900 | { 0x0000e566, 0x00000004 }, | ||
901 | { 0x00000055, 0x00000008 }, | ||
902 | { 0x00802061, 0x00000010 }, | ||
903 | { 0x00202000, 0x00000004 }, | ||
904 | { 0x001b00ff, 0x00000004 }, | ||
905 | { 0x01000064, 0x00000010 }, | ||
906 | { 0x001f2000, 0x00000004 }, | ||
907 | { 0x001c00ff, 0x00000004 }, | ||
908 | { 0000000000, 0x0000000c }, | ||
909 | { 0x00000072, 0x00000030 }, | ||
910 | { 0x00000055, 0x00000008 }, | ||
911 | { 0x0000e576, 0x00000004 }, | ||
912 | { 0x0000e577, 0x00000004 }, | ||
913 | { 0x0000e50e, 0x00000004 }, | ||
914 | { 0x0000e50f, 0x00000004 }, | ||
915 | { 0x0140a000, 0x00000004 }, | ||
916 | { 0x00000069, 0x00000018 }, | ||
917 | { 0x00c0e5f9, 0x000000c2 }, | ||
918 | { 0x00000069, 0x00000008 }, | ||
919 | { 0x0014e50e, 0x00000004 }, | ||
920 | { 0x0040e50f, 0x00000004 }, | ||
921 | { 0x00c0006c, 0x00000008 }, | ||
922 | { 0x0000e570, 0x00000004 }, | ||
923 | { 0x0000e571, 0x00000004 }, | ||
924 | { 0x0000e572, 0x0000000c }, | ||
925 | { 0x0000a000, 0x00000004 }, | ||
926 | { 0x0140a000, 0x00000004 }, | ||
927 | { 0x0000e568, 0x00000004 }, | ||
928 | { 0x000c2000, 0x00000004 }, | ||
929 | { 0x00000076, 0x00000018 }, | ||
930 | { 0x000b0000, 0x00000004 }, | ||
931 | { 0x18c0e562, 0x00000004 }, | ||
932 | { 0x00000078, 0x00000008 }, | ||
933 | { 0x00c00077, 0x00000008 }, | ||
934 | { 0x000700c7, 0x00000004 }, | ||
935 | { 0x00000080, 0x00000038 }, | ||
936 | { 0x0000e5bb, 0x00000004 }, | ||
937 | { 0x0000e5bc, 0000000000 }, | ||
938 | { 0x0000a000, 0x00000004 }, | ||
939 | { 0x0000e821, 0x00000004 }, | ||
940 | { 0x0000e800, 0000000000 }, | ||
941 | { 0x0000e821, 0x00000004 }, | ||
942 | { 0x0000e82e, 0000000000 }, | ||
943 | { 0x02cca000, 0x00000004 }, | ||
944 | { 0x00140000, 0x00000004 }, | ||
945 | { 0x000ce1cc, 0x00000004 }, | ||
946 | { 0x050de1cd, 0x00000004 }, | ||
947 | { 0x00400000, 0x00000004 }, | ||
948 | { 0x0000008f, 0x00000018 }, | ||
949 | { 0x00c0a000, 0x00000004 }, | ||
950 | { 0x0000008c, 0x00000008 }, | ||
951 | { 0x00000091, 0x00000020 }, | ||
952 | { 0x4200e000, 0000000000 }, | ||
953 | { 0x00000098, 0x00000038 }, | ||
954 | { 0x000ca000, 0x00000004 }, | ||
955 | { 0x00140000, 0x00000004 }, | ||
956 | { 0x000c2000, 0x00000004 }, | ||
957 | { 0x00160000, 0x00000004 }, | ||
958 | { 0x700ce000, 0x00000004 }, | ||
959 | { 0x00140094, 0x00000008 }, | ||
960 | { 0x4000e000, 0000000000 }, | ||
961 | { 0x02400000, 0x00000004 }, | ||
962 | { 0x400ee000, 0x00000004 }, | ||
963 | { 0x02400000, 0x00000004 }, | ||
964 | { 0x4000e000, 0000000000 }, | ||
965 | { 0x000c2000, 0x00000004 }, | ||
966 | { 0x0240e51b, 0x00000004 }, | ||
967 | { 0x0080e50a, 0x00000005 }, | ||
968 | { 0x0080e50b, 0x00000005 }, | ||
969 | { 0x00220000, 0x00000004 }, | ||
970 | { 0x000700c7, 0x00000004 }, | ||
971 | { 0x000000a4, 0x00000038 }, | ||
972 | { 0x0080e5bd, 0x00000005 }, | ||
973 | { 0x0000e5bb, 0x00000005 }, | ||
974 | { 0x0080e5bc, 0x00000005 }, | ||
975 | { 0x00210000, 0x00000004 }, | ||
976 | { 0x02800000, 0x00000004 }, | ||
977 | { 0x00c000ab, 0x00000018 }, | ||
978 | { 0x4180e000, 0x00000040 }, | ||
979 | { 0x000000ad, 0x00000024 }, | ||
980 | { 0x01000000, 0x0000000c }, | ||
981 | { 0x0100e51d, 0x0000000c }, | ||
982 | { 0x000045bb, 0x00000004 }, | ||
983 | { 0x000080a7, 0x00000008 }, | ||
984 | { 0x0000f3ce, 0x00000004 }, | ||
985 | { 0x0140a000, 0x00000004 }, | ||
986 | { 0x00cc2000, 0x00000004 }, | ||
987 | { 0x08c053cf, 0x00000040 }, | ||
988 | { 0x00008000, 0000000000 }, | ||
989 | { 0x0000f3d2, 0x00000004 }, | ||
990 | { 0x0140a000, 0x00000004 }, | ||
991 | { 0x00cc2000, 0x00000004 }, | ||
992 | { 0x08c053d3, 0x00000040 }, | ||
993 | { 0x00008000, 0000000000 }, | ||
994 | { 0x0000f39d, 0x00000004 }, | ||
995 | { 0x0140a000, 0x00000004 }, | ||
996 | { 0x00cc2000, 0x00000004 }, | ||
997 | { 0x08c0539e, 0x00000040 }, | ||
998 | { 0x00008000, 0000000000 }, | ||
999 | { 0x03c00830, 0x00000004 }, | ||
1000 | { 0x4200e000, 0000000000 }, | ||
1001 | { 0x0000a000, 0x00000004 }, | ||
1002 | { 0x200045e0, 0x00000004 }, | ||
1003 | { 0x0000e5e1, 0000000000 }, | ||
1004 | { 0x00000001, 0000000000 }, | ||
1005 | { 0x000700c4, 0x00000004 }, | ||
1006 | { 0x0800e394, 0000000000 }, | ||
1007 | { 0000000000, 0000000000 }, | ||
1008 | { 0x0000e8c4, 0x00000004 }, | ||
1009 | { 0x0000e8c5, 0x00000004 }, | ||
1010 | { 0x0000e8c6, 0x00000004 }, | ||
1011 | { 0x0000e928, 0x00000004 }, | ||
1012 | { 0x0000e929, 0x00000004 }, | ||
1013 | { 0x0000e92a, 0x00000004 }, | ||
1014 | { 0x000000c8, 0x00000008 }, | ||
1015 | { 0x0000e928, 0x00000004 }, | ||
1016 | { 0x0000e929, 0x00000004 }, | ||
1017 | { 0x0000e92a, 0x00000004 }, | ||
1018 | { 0x000000cf, 0x00000008 }, | ||
1019 | { 0x02c02000, 0x00000004 }, | ||
1020 | { 0x00060000, 0x00000004 }, | ||
1021 | { 0x000000d7, 0x00000034 }, | ||
1022 | { 0x000000d4, 0x00000008 }, | ||
1023 | { 0x00008000, 0x00000004 }, | ||
1024 | { 0xc000e000, 0000000000 }, | ||
1025 | { 0x0000e1cc, 0x00000004 }, | ||
1026 | { 0x0500e1cd, 0x00000004 }, | ||
1027 | { 0x000ca000, 0x00000004 }, | ||
1028 | { 0x000000de, 0x00000034 }, | ||
1029 | { 0x000000da, 0x00000008 }, | ||
1030 | { 0x0000a000, 0000000000 }, | ||
1031 | { 0x0019e1cc, 0x00000004 }, | ||
1032 | { 0x001b0001, 0x00000004 }, | ||
1033 | { 0x0500a000, 0x00000004 }, | ||
1034 | { 0x080041cd, 0x00000004 }, | ||
1035 | { 0x000ca000, 0x00000004 }, | ||
1036 | { 0x000000fb, 0x00000034 }, | ||
1037 | { 0x0000004a, 0x00000008 }, | ||
1038 | { 0000000000, 0000000000 }, | ||
1039 | { 0000000000, 0000000000 }, | ||
1040 | { 0000000000, 0000000000 }, | ||
1041 | { 0000000000, 0000000000 }, | ||
1042 | { 0000000000, 0000000000 }, | ||
1043 | { 0000000000, 0000000000 }, | ||
1044 | { 0000000000, 0000000000 }, | ||
1045 | { 0000000000, 0000000000 }, | ||
1046 | { 0000000000, 0000000000 }, | ||
1047 | { 0000000000, 0000000000 }, | ||
1048 | { 0000000000, 0000000000 }, | ||
1049 | { 0000000000, 0000000000 }, | ||
1050 | { 0000000000, 0000000000 }, | ||
1051 | { 0000000000, 0000000000 }, | ||
1052 | { 0000000000, 0000000000 }, | ||
1053 | { 0000000000, 0000000000 }, | ||
1054 | { 0x000c2000, 0x00000004 }, | ||
1055 | { 0x001d0018, 0x00000004 }, | ||
1056 | { 0x001a0001, 0x00000004 }, | ||
1057 | { 0x000000fb, 0x00000034 }, | ||
1058 | { 0x0000004a, 0x00000008 }, | ||
1059 | { 0x0500a04a, 0x00000008 }, | ||
1060 | { 0000000000, 0000000000 }, | ||
1061 | { 0000000000, 0000000000 }, | ||
1062 | { 0000000000, 0000000000 }, | ||
1063 | { 0000000000, 0000000000 }, | ||
1064 | }; | ||
1065 | |||
1066 | static const u32 RS600_cp_microcode[][2] = { | ||
1067 | { 0x4200e000, 0000000000 }, | ||
1068 | { 0x4000e000, 0000000000 }, | ||
1069 | { 0x000000a0, 0x00000008 }, | ||
1070 | { 0x000000a4, 0x00000008 }, | ||
1071 | { 0x4a554b4a, 0000000000 }, | ||
1072 | { 0x4a4a4467, 0000000000 }, | ||
1073 | { 0x55526f75, 0000000000 }, | ||
1074 | { 0x4a7e7d65, 0000000000 }, | ||
1075 | { 0x4ae74af6, 0000000000 }, | ||
1076 | { 0x4ad34a4a, 0000000000 }, | ||
1077 | { 0xd6898989, 0000000000 }, | ||
1078 | { 0xcd4addcf, 0000000000 }, | ||
1079 | { 0x8ebe4ae2, 0000000000 }, | ||
1080 | { 0xc38a8a8a, 0000000000 }, | ||
1081 | { 0x4a0f8cc8, 0000000000 }, | ||
1082 | { 0x000ca000, 0x00000004 }, | ||
1083 | { 0x000d0012, 0x00000038 }, | ||
1084 | { 0x0000e8b4, 0x00000004 }, | ||
1085 | { 0x000d0014, 0x00000038 }, | ||
1086 | { 0x0000e8b6, 0x00000004 }, | ||
1087 | { 0x000d0016, 0x00000038 }, | ||
1088 | { 0x0000e854, 0x00000004 }, | ||
1089 | { 0x000d0018, 0x00000038 }, | ||
1090 | { 0x0000e855, 0x00000004 }, | ||
1091 | { 0x000d001a, 0x00000038 }, | ||
1092 | { 0x0000e856, 0x00000004 }, | ||
1093 | { 0x000d001c, 0x00000038 }, | ||
1094 | { 0x0000e857, 0x00000004 }, | ||
1095 | { 0x000d001e, 0x00000038 }, | ||
1096 | { 0x0000e824, 0x00000004 }, | ||
1097 | { 0x000d0020, 0x00000038 }, | ||
1098 | { 0x0000e825, 0x00000004 }, | ||
1099 | { 0x000d0022, 0x00000038 }, | ||
1100 | { 0x0000e830, 0x00000004 }, | ||
1101 | { 0x000d0024, 0x00000038 }, | ||
1102 | { 0x0000f0c0, 0x00000004 }, | ||
1103 | { 0x000d0026, 0x00000038 }, | ||
1104 | { 0x0000f0c1, 0x00000004 }, | ||
1105 | { 0x000d0028, 0x00000038 }, | ||
1106 | { 0x0000f041, 0x00000004 }, | ||
1107 | { 0x000d002a, 0x00000038 }, | ||
1108 | { 0x0000f184, 0x00000004 }, | ||
1109 | { 0x000d002c, 0x00000038 }, | ||
1110 | { 0x0000f185, 0x00000004 }, | ||
1111 | { 0x000d002e, 0x00000038 }, | ||
1112 | { 0x0000f186, 0x00000004 }, | ||
1113 | { 0x000d0030, 0x00000038 }, | ||
1114 | { 0x0000f187, 0x00000004 }, | ||
1115 | { 0x000d0032, 0x00000038 }, | ||
1116 | { 0x0000f180, 0x00000004 }, | ||
1117 | { 0x000d0034, 0x00000038 }, | ||
1118 | { 0x0000f393, 0x00000004 }, | ||
1119 | { 0x000d0036, 0x00000038 }, | ||
1120 | { 0x0000f38a, 0x00000004 }, | ||
1121 | { 0x000d0038, 0x00000038 }, | ||
1122 | { 0x0000f38e, 0x00000004 }, | ||
1123 | { 0x0000e821, 0x00000004 }, | ||
1124 | { 0x0140a000, 0x00000004 }, | ||
1125 | { 0x00000043, 0x00000018 }, | ||
1126 | { 0x00cce800, 0x00000004 }, | ||
1127 | { 0x001b0001, 0x00000004 }, | ||
1128 | { 0x08004800, 0x00000004 }, | ||
1129 | { 0x001b0001, 0x00000004 }, | ||
1130 | { 0x08004800, 0x00000004 }, | ||
1131 | { 0x001b0001, 0x00000004 }, | ||
1132 | { 0x08004800, 0x00000004 }, | ||
1133 | { 0x0000003a, 0x00000008 }, | ||
1134 | { 0x0000a000, 0000000000 }, | ||
1135 | { 0x2000451d, 0x00000004 }, | ||
1136 | { 0x0000e580, 0x00000004 }, | ||
1137 | { 0x000ce581, 0x00000004 }, | ||
1138 | { 0x08004580, 0x00000004 }, | ||
1139 | { 0x000ce581, 0x00000004 }, | ||
1140 | { 0x00000047, 0x00000008 }, | ||
1141 | { 0x0000a000, 0000000000 }, | ||
1142 | { 0x000c2000, 0x00000004 }, | ||
1143 | { 0x0000e50e, 0x00000004 }, | ||
1144 | { 0x00032000, 0x00000004 }, | ||
1145 | { 0x00022051, 0x00000028 }, | ||
1146 | { 0x00000051, 0x00000024 }, | ||
1147 | { 0x0800450f, 0x00000004 }, | ||
1148 | { 0x0000a04b, 0x00000008 }, | ||
1149 | { 0x0000e565, 0x00000004 }, | ||
1150 | { 0x0000e566, 0x00000004 }, | ||
1151 | { 0x00000052, 0x00000008 }, | ||
1152 | { 0x03cca5b4, 0x00000004 }, | ||
1153 | { 0x05432000, 0x00000004 }, | ||
1154 | { 0x00022000, 0x00000004 }, | ||
1155 | { 0x4ccce05e, 0x00000030 }, | ||
1156 | { 0x08274565, 0x00000004 }, | ||
1157 | { 0x0000005e, 0x00000030 }, | ||
1158 | { 0x08004564, 0x00000004 }, | ||
1159 | { 0x0000e566, 0x00000004 }, | ||
1160 | { 0x00000055, 0x00000008 }, | ||
1161 | { 0x00802061, 0x00000010 }, | ||
1162 | { 0x00202000, 0x00000004 }, | ||
1163 | { 0x001b00ff, 0x00000004 }, | ||
1164 | { 0x01000064, 0x00000010 }, | ||
1165 | { 0x001f2000, 0x00000004 }, | ||
1166 | { 0x001c00ff, 0x00000004 }, | ||
1167 | { 0000000000, 0x0000000c }, | ||
1168 | { 0x00000072, 0x00000030 }, | ||
1169 | { 0x00000055, 0x00000008 }, | ||
1170 | { 0x0000e576, 0x00000004 }, | ||
1171 | { 0x0000e577, 0x00000004 }, | ||
1172 | { 0x0000e50e, 0x00000004 }, | ||
1173 | { 0x0000e50f, 0x00000004 }, | ||
1174 | { 0x0140a000, 0x00000004 }, | ||
1175 | { 0x00000069, 0x00000018 }, | ||
1176 | { 0x00c0e5f9, 0x000000c2 }, | ||
1177 | { 0x00000069, 0x00000008 }, | ||
1178 | { 0x0014e50e, 0x00000004 }, | ||
1179 | { 0x0040e50f, 0x00000004 }, | ||
1180 | { 0x00c0006c, 0x00000008 }, | ||
1181 | { 0x0000e570, 0x00000004 }, | ||
1182 | { 0x0000e571, 0x00000004 }, | ||
1183 | { 0x0000e572, 0x0000000c }, | ||
1184 | { 0x0000a000, 0x00000004 }, | ||
1185 | { 0x0140a000, 0x00000004 }, | ||
1186 | { 0x0000e568, 0x00000004 }, | ||
1187 | { 0x000c2000, 0x00000004 }, | ||
1188 | { 0x00000076, 0x00000018 }, | ||
1189 | { 0x000b0000, 0x00000004 }, | ||
1190 | { 0x18c0e562, 0x00000004 }, | ||
1191 | { 0x00000078, 0x00000008 }, | ||
1192 | { 0x00c00077, 0x00000008 }, | ||
1193 | { 0x000700d5, 0x00000004 }, | ||
1194 | { 0x00000084, 0x00000038 }, | ||
1195 | { 0x000ca086, 0x00000030 }, | ||
1196 | { 0x080045bb, 0x00000004 }, | ||
1197 | { 0x000c2087, 0x00000030 }, | ||
1198 | { 0x0800e5bc, 0000000000 }, | ||
1199 | { 0x0000e5bb, 0x00000004 }, | ||
1200 | { 0x0000e5bc, 0000000000 }, | ||
1201 | { 0x00120000, 0x0000000c }, | ||
1202 | { 0x00120000, 0x00000004 }, | ||
1203 | { 0x001b0002, 0x0000000c }, | ||
1204 | { 0x0000a000, 0x00000004 }, | ||
1205 | { 0x0000e821, 0x00000004 }, | ||
1206 | { 0x0000e800, 0000000000 }, | ||
1207 | { 0x0000e821, 0x00000004 }, | ||
1208 | { 0x0000e82e, 0000000000 }, | ||
1209 | { 0x02cca000, 0x00000004 }, | ||
1210 | { 0x00140000, 0x00000004 }, | ||
1211 | { 0x000ce1cc, 0x00000004 }, | ||
1212 | { 0x050de1cd, 0x00000004 }, | ||
1213 | { 0x00400000, 0x00000004 }, | ||
1214 | { 0x00000096, 0x00000018 }, | ||
1215 | { 0x00c0a000, 0x00000004 }, | ||
1216 | { 0x00000093, 0x00000008 }, | ||
1217 | { 0x00000098, 0x00000020 }, | ||
1218 | { 0x4200e000, 0000000000 }, | ||
1219 | { 0x0000009f, 0x00000038 }, | ||
1220 | { 0x000ca000, 0x00000004 }, | ||
1221 | { 0x00140000, 0x00000004 }, | ||
1222 | { 0x000c2000, 0x00000004 }, | ||
1223 | { 0x00160000, 0x00000004 }, | ||
1224 | { 0x700ce000, 0x00000004 }, | ||
1225 | { 0x0014009b, 0x00000008 }, | ||
1226 | { 0x4000e000, 0000000000 }, | ||
1227 | { 0x02400000, 0x00000004 }, | ||
1228 | { 0x400ee000, 0x00000004 }, | ||
1229 | { 0x02400000, 0x00000004 }, | ||
1230 | { 0x4000e000, 0000000000 }, | ||
1231 | { 0x000c2000, 0x00000004 }, | ||
1232 | { 0x0240e51b, 0x00000004 }, | ||
1233 | { 0x0080e50a, 0x00000005 }, | ||
1234 | { 0x0080e50b, 0x00000005 }, | ||
1235 | { 0x00220000, 0x00000004 }, | ||
1236 | { 0x000700d5, 0x00000004 }, | ||
1237 | { 0x000000b2, 0x00000038 }, | ||
1238 | { 0x000c2087, 0x00000030 }, | ||
1239 | { 0x0880e5bd, 0x00000005 }, | ||
1240 | { 0x000c2086, 0x00000030 }, | ||
1241 | { 0x0800e5bb, 0x00000005 }, | ||
1242 | { 0x000c2087, 0x00000030 }, | ||
1243 | { 0x0880e5bc, 0x00000005 }, | ||
1244 | { 0x000000b5, 0x00000008 }, | ||
1245 | { 0x0080e5bd, 0x00000005 }, | ||
1246 | { 0x0000e5bb, 0x00000005 }, | ||
1247 | { 0x0080e5bc, 0x00000005 }, | ||
1248 | { 0x00210000, 0x00000004 }, | ||
1249 | { 0x02800000, 0x00000004 }, | ||
1250 | { 0x00c000b9, 0x00000018 }, | ||
1251 | { 0x4180e000, 0x00000040 }, | ||
1252 | { 0x000000bb, 0x00000024 }, | ||
1253 | { 0x01000000, 0x0000000c }, | ||
1254 | { 0x0100e51d, 0x0000000c }, | ||
1255 | { 0x000045bb, 0x00000004 }, | ||
1256 | { 0x000080b5, 0x00000008 }, | ||
1257 | { 0x0000f3ce, 0x00000004 }, | ||
1258 | { 0x0140a000, 0x00000004 }, | ||
1259 | { 0x00cc2000, 0x00000004 }, | ||
1260 | { 0x08c053cf, 0x00000040 }, | ||
1261 | { 0x00008000, 0000000000 }, | ||
1262 | { 0x0000f3d2, 0x00000004 }, | ||
1263 | { 0x0140a000, 0x00000004 }, | ||
1264 | { 0x00cc2000, 0x00000004 }, | ||
1265 | { 0x08c053d3, 0x00000040 }, | ||
1266 | { 0x00008000, 0000000000 }, | ||
1267 | { 0x0000f39d, 0x00000004 }, | ||
1268 | { 0x0140a000, 0x00000004 }, | ||
1269 | { 0x00cc2000, 0x00000004 }, | ||
1270 | { 0x08c0539e, 0x00000040 }, | ||
1271 | { 0x00008000, 0000000000 }, | ||
1272 | { 0x03c00830, 0x00000004 }, | ||
1273 | { 0x4200e000, 0000000000 }, | ||
1274 | { 0x0000a000, 0x00000004 }, | ||
1275 | { 0x200045e0, 0x00000004 }, | ||
1276 | { 0x0000e5e1, 0000000000 }, | ||
1277 | { 0x00000001, 0000000000 }, | ||
1278 | { 0x000700d2, 0x00000004 }, | ||
1279 | { 0x0800e394, 0000000000 }, | ||
1280 | { 0000000000, 0000000000 }, | ||
1281 | { 0x0000e8c4, 0x00000004 }, | ||
1282 | { 0x0000e8c5, 0x00000004 }, | ||
1283 | { 0x0000e8c6, 0x00000004 }, | ||
1284 | { 0x0000e928, 0x00000004 }, | ||
1285 | { 0x0000e929, 0x00000004 }, | ||
1286 | { 0x0000e92a, 0x00000004 }, | ||
1287 | { 0x000000d6, 0x00000008 }, | ||
1288 | { 0x0000e928, 0x00000004 }, | ||
1289 | { 0x0000e929, 0x00000004 }, | ||
1290 | { 0x0000e92a, 0x00000004 }, | ||
1291 | { 0x000000dd, 0x00000008 }, | ||
1292 | { 0x00e00116, 0000000000 }, | ||
1293 | { 0x000700e1, 0x00000004 }, | ||
1294 | { 0x0800401c, 0x00000004 }, | ||
1295 | { 0x200050e7, 0x00000004 }, | ||
1296 | { 0x0000e01d, 0x00000004 }, | ||
1297 | { 0x000000e4, 0x00000008 }, | ||
1298 | { 0x02c02000, 0x00000004 }, | ||
1299 | { 0x00060000, 0x00000004 }, | ||
1300 | { 0x000000eb, 0x00000034 }, | ||
1301 | { 0x000000e8, 0x00000008 }, | ||
1302 | { 0x00008000, 0x00000004 }, | ||
1303 | { 0xc000e000, 0000000000 }, | ||
1304 | { 0000000000, 0000000000 }, | ||
1305 | { 0000000000, 0000000000 }, | ||
1306 | { 0000000000, 0000000000 }, | ||
1307 | { 0000000000, 0000000000 }, | ||
1308 | { 0000000000, 0000000000 }, | ||
1309 | { 0000000000, 0000000000 }, | ||
1310 | { 0000000000, 0000000000 }, | ||
1311 | { 0000000000, 0000000000 }, | ||
1312 | { 0000000000, 0000000000 }, | ||
1313 | { 0x000c2000, 0x00000004 }, | ||
1314 | { 0x001d0018, 0x00000004 }, | ||
1315 | { 0x001a0001, 0x00000004 }, | ||
1316 | { 0x000000fb, 0x00000034 }, | ||
1317 | { 0x0000004a, 0x00000008 }, | ||
1318 | { 0x0500a04a, 0x00000008 }, | ||
1319 | { 0000000000, 0000000000 }, | ||
1320 | { 0000000000, 0000000000 }, | ||
1321 | { 0000000000, 0000000000 }, | ||
1322 | { 0000000000, 0000000000 }, | ||
1323 | }; | ||
1324 | |||
1325 | static const u32 RS690_cp_microcode[][2] = { | ||
1326 | { 0x000000dd, 0x00000008 }, | ||
1327 | { 0x000000df, 0x00000008 }, | ||
1328 | { 0x000000a0, 0x00000008 }, | ||
1329 | { 0x000000a4, 0x00000008 }, | ||
1330 | { 0x4a554b4a, 0000000000 }, | ||
1331 | { 0x4a4a4467, 0000000000 }, | ||
1332 | { 0x55526f75, 0000000000 }, | ||
1333 | { 0x4a7e7d65, 0000000000 }, | ||
1334 | { 0x4ad74af6, 0000000000 }, | ||
1335 | { 0x4ac94a4a, 0000000000 }, | ||
1336 | { 0xcc898989, 0000000000 }, | ||
1337 | { 0xc34ad3c5, 0000000000 }, | ||
1338 | { 0x8e4a4a4a, 0000000000 }, | ||
1339 | { 0x4a8a8a8a, 0000000000 }, | ||
1340 | { 0x4a0f8c4a, 0000000000 }, | ||
1341 | { 0x000ca000, 0x00000004 }, | ||
1342 | { 0x000d0012, 0x00000038 }, | ||
1343 | { 0x0000e8b4, 0x00000004 }, | ||
1344 | { 0x000d0014, 0x00000038 }, | ||
1345 | { 0x0000e8b6, 0x00000004 }, | ||
1346 | { 0x000d0016, 0x00000038 }, | ||
1347 | { 0x0000e854, 0x00000004 }, | ||
1348 | { 0x000d0018, 0x00000038 }, | ||
1349 | { 0x0000e855, 0x00000004 }, | ||
1350 | { 0x000d001a, 0x00000038 }, | ||
1351 | { 0x0000e856, 0x00000004 }, | ||
1352 | { 0x000d001c, 0x00000038 }, | ||
1353 | { 0x0000e857, 0x00000004 }, | ||
1354 | { 0x000d001e, 0x00000038 }, | ||
1355 | { 0x0000e824, 0x00000004 }, | ||
1356 | { 0x000d0020, 0x00000038 }, | ||
1357 | { 0x0000e825, 0x00000004 }, | ||
1358 | { 0x000d0022, 0x00000038 }, | ||
1359 | { 0x0000e830, 0x00000004 }, | ||
1360 | { 0x000d0024, 0x00000038 }, | ||
1361 | { 0x0000f0c0, 0x00000004 }, | ||
1362 | { 0x000d0026, 0x00000038 }, | ||
1363 | { 0x0000f0c1, 0x00000004 }, | ||
1364 | { 0x000d0028, 0x00000038 }, | ||
1365 | { 0x0000f041, 0x00000004 }, | ||
1366 | { 0x000d002a, 0x00000038 }, | ||
1367 | { 0x0000f184, 0x00000004 }, | ||
1368 | { 0x000d002c, 0x00000038 }, | ||
1369 | { 0x0000f185, 0x00000004 }, | ||
1370 | { 0x000d002e, 0x00000038 }, | ||
1371 | { 0x0000f186, 0x00000004 }, | ||
1372 | { 0x000d0030, 0x00000038 }, | ||
1373 | { 0x0000f187, 0x00000004 }, | ||
1374 | { 0x000d0032, 0x00000038 }, | ||
1375 | { 0x0000f180, 0x00000004 }, | ||
1376 | { 0x000d0034, 0x00000038 }, | ||
1377 | { 0x0000f393, 0x00000004 }, | ||
1378 | { 0x000d0036, 0x00000038 }, | ||
1379 | { 0x0000f38a, 0x00000004 }, | ||
1380 | { 0x000d0038, 0x00000038 }, | ||
1381 | { 0x0000f38e, 0x00000004 }, | ||
1382 | { 0x0000e821, 0x00000004 }, | ||
1383 | { 0x0140a000, 0x00000004 }, | ||
1384 | { 0x00000043, 0x00000018 }, | ||
1385 | { 0x00cce800, 0x00000004 }, | ||
1386 | { 0x001b0001, 0x00000004 }, | ||
1387 | { 0x08004800, 0x00000004 }, | ||
1388 | { 0x001b0001, 0x00000004 }, | ||
1389 | { 0x08004800, 0x00000004 }, | ||
1390 | { 0x001b0001, 0x00000004 }, | ||
1391 | { 0x08004800, 0x00000004 }, | ||
1392 | { 0x0000003a, 0x00000008 }, | ||
1393 | { 0x0000a000, 0000000000 }, | ||
1394 | { 0x2000451d, 0x00000004 }, | ||
1395 | { 0x0000e580, 0x00000004 }, | ||
1396 | { 0x000ce581, 0x00000004 }, | ||
1397 | { 0x08004580, 0x00000004 }, | ||
1398 | { 0x000ce581, 0x00000004 }, | ||
1399 | { 0x00000047, 0x00000008 }, | ||
1400 | { 0x0000a000, 0000000000 }, | ||
1401 | { 0x000c2000, 0x00000004 }, | ||
1402 | { 0x0000e50e, 0x00000004 }, | ||
1403 | { 0x00032000, 0x00000004 }, | ||
1404 | { 0x00022051, 0x00000028 }, | ||
1405 | { 0x00000051, 0x00000024 }, | ||
1406 | { 0x0800450f, 0x00000004 }, | ||
1407 | { 0x0000a04b, 0x00000008 }, | ||
1408 | { 0x0000e565, 0x00000004 }, | ||
1409 | { 0x0000e566, 0x00000004 }, | ||
1410 | { 0x00000052, 0x00000008 }, | ||
1411 | { 0x03cca5b4, 0x00000004 }, | ||
1412 | { 0x05432000, 0x00000004 }, | ||
1413 | { 0x00022000, 0x00000004 }, | ||
1414 | { 0x4ccce05e, 0x00000030 }, | ||
1415 | { 0x08274565, 0x00000004 }, | ||
1416 | { 0x0000005e, 0x00000030 }, | ||
1417 | { 0x08004564, 0x00000004 }, | ||
1418 | { 0x0000e566, 0x00000004 }, | ||
1419 | { 0x00000055, 0x00000008 }, | ||
1420 | { 0x00802061, 0x00000010 }, | ||
1421 | { 0x00202000, 0x00000004 }, | ||
1422 | { 0x001b00ff, 0x00000004 }, | ||
1423 | { 0x01000064, 0x00000010 }, | ||
1424 | { 0x001f2000, 0x00000004 }, | ||
1425 | { 0x001c00ff, 0x00000004 }, | ||
1426 | { 0000000000, 0x0000000c }, | ||
1427 | { 0x00000072, 0x00000030 }, | ||
1428 | { 0x00000055, 0x00000008 }, | ||
1429 | { 0x0000e576, 0x00000004 }, | ||
1430 | { 0x0000e577, 0x00000004 }, | ||
1431 | { 0x0000e50e, 0x00000004 }, | ||
1432 | { 0x0000e50f, 0x00000004 }, | ||
1433 | { 0x0140a000, 0x00000004 }, | ||
1434 | { 0x00000069, 0x00000018 }, | ||
1435 | { 0x00c0e5f9, 0x000000c2 }, | ||
1436 | { 0x00000069, 0x00000008 }, | ||
1437 | { 0x0014e50e, 0x00000004 }, | ||
1438 | { 0x0040e50f, 0x00000004 }, | ||
1439 | { 0x00c0006c, 0x00000008 }, | ||
1440 | { 0x0000e570, 0x00000004 }, | ||
1441 | { 0x0000e571, 0x00000004 }, | ||
1442 | { 0x0000e572, 0x0000000c }, | ||
1443 | { 0x0000a000, 0x00000004 }, | ||
1444 | { 0x0140a000, 0x00000004 }, | ||
1445 | { 0x0000e568, 0x00000004 }, | ||
1446 | { 0x000c2000, 0x00000004 }, | ||
1447 | { 0x00000076, 0x00000018 }, | ||
1448 | { 0x000b0000, 0x00000004 }, | ||
1449 | { 0x18c0e562, 0x00000004 }, | ||
1450 | { 0x00000078, 0x00000008 }, | ||
1451 | { 0x00c00077, 0x00000008 }, | ||
1452 | { 0x000700cb, 0x00000004 }, | ||
1453 | { 0x00000084, 0x00000038 }, | ||
1454 | { 0x000ca086, 0x00000030 }, | ||
1455 | { 0x080045bb, 0x00000004 }, | ||
1456 | { 0x000c2087, 0x00000030 }, | ||
1457 | { 0x0800e5bc, 0000000000 }, | ||
1458 | { 0x0000e5bb, 0x00000004 }, | ||
1459 | { 0x0000e5bc, 0000000000 }, | ||
1460 | { 0x00120000, 0x0000000c }, | ||
1461 | { 0x00120000, 0x00000004 }, | ||
1462 | { 0x001b0002, 0x0000000c }, | ||
1463 | { 0x0000a000, 0x00000004 }, | ||
1464 | { 0x0000e821, 0x00000004 }, | ||
1465 | { 0x0000e800, 0000000000 }, | ||
1466 | { 0x0000e821, 0x00000004 }, | ||
1467 | { 0x0000e82e, 0000000000 }, | ||
1468 | { 0x02cca000, 0x00000004 }, | ||
1469 | { 0x00140000, 0x00000004 }, | ||
1470 | { 0x000ce1cc, 0x00000004 }, | ||
1471 | { 0x050de1cd, 0x00000004 }, | ||
1472 | { 0x00400000, 0x00000004 }, | ||
1473 | { 0x00000096, 0x00000018 }, | ||
1474 | { 0x00c0a000, 0x00000004 }, | ||
1475 | { 0x00000093, 0x00000008 }, | ||
1476 | { 0x00000098, 0x00000020 }, | ||
1477 | { 0x4200e000, 0000000000 }, | ||
1478 | { 0x0000009f, 0x00000038 }, | ||
1479 | { 0x000ca000, 0x00000004 }, | ||
1480 | { 0x00140000, 0x00000004 }, | ||
1481 | { 0x000c2000, 0x00000004 }, | ||
1482 | { 0x00160000, 0x00000004 }, | ||
1483 | { 0x700ce000, 0x00000004 }, | ||
1484 | { 0x0014009b, 0x00000008 }, | ||
1485 | { 0x4000e000, 0000000000 }, | ||
1486 | { 0x02400000, 0x00000004 }, | ||
1487 | { 0x400ee000, 0x00000004 }, | ||
1488 | { 0x02400000, 0x00000004 }, | ||
1489 | { 0x4000e000, 0000000000 }, | ||
1490 | { 0x00100000, 0x0000002c }, | ||
1491 | { 0x00004000, 0000000000 }, | ||
1492 | { 0x080045c8, 0x00000004 }, | ||
1493 | { 0x00240005, 0x00000004 }, | ||
1494 | { 0x08004d0b, 0x00000004 }, | ||
1495 | { 0x000c2000, 0x00000004 }, | ||
1496 | { 0x0240e51b, 0x00000004 }, | ||
1497 | { 0x0080e50a, 0x00000005 }, | ||
1498 | { 0x0080e50b, 0x00000005 }, | ||
1499 | { 0x00220000, 0x00000004 }, | ||
1500 | { 0x000700cb, 0x00000004 }, | ||
1501 | { 0x000000b7, 0x00000038 }, | ||
1502 | { 0x000c2087, 0x00000030 }, | ||
1503 | { 0x0880e5bd, 0x00000005 }, | ||
1504 | { 0x000c2086, 0x00000030 }, | ||
1505 | { 0x0800e5bb, 0x00000005 }, | ||
1506 | { 0x000c2087, 0x00000030 }, | ||
1507 | { 0x0880e5bc, 0x00000005 }, | ||
1508 | { 0x000000ba, 0x00000008 }, | ||
1509 | { 0x0080e5bd, 0x00000005 }, | ||
1510 | { 0x0000e5bb, 0x00000005 }, | ||
1511 | { 0x0080e5bc, 0x00000005 }, | ||
1512 | { 0x00210000, 0x00000004 }, | ||
1513 | { 0x02800000, 0x00000004 }, | ||
1514 | { 0x00c000be, 0x00000018 }, | ||
1515 | { 0x4180e000, 0x00000040 }, | ||
1516 | { 0x000000c0, 0x00000024 }, | ||
1517 | { 0x01000000, 0x0000000c }, | ||
1518 | { 0x0100e51d, 0x0000000c }, | ||
1519 | { 0x000045bb, 0x00000004 }, | ||
1520 | { 0x000080ba, 0x00000008 }, | ||
1521 | { 0x03c00830, 0x00000004 }, | ||
1522 | { 0x4200e000, 0000000000 }, | ||
1523 | { 0x0000a000, 0x00000004 }, | ||
1524 | { 0x200045e0, 0x00000004 }, | ||
1525 | { 0x0000e5e1, 0000000000 }, | ||
1526 | { 0x00000001, 0000000000 }, | ||
1527 | { 0x000700c8, 0x00000004 }, | ||
1528 | { 0x0800e394, 0000000000 }, | ||
1529 | { 0000000000, 0000000000 }, | ||
1530 | { 0x0000e8c4, 0x00000004 }, | ||
1531 | { 0x0000e8c5, 0x00000004 }, | ||
1532 | { 0x0000e8c6, 0x00000004 }, | ||
1533 | { 0x0000e928, 0x00000004 }, | ||
1534 | { 0x0000e929, 0x00000004 }, | ||
1535 | { 0x0000e92a, 0x00000004 }, | ||
1536 | { 0x000000cc, 0x00000008 }, | ||
1537 | { 0x0000e928, 0x00000004 }, | ||
1538 | { 0x0000e929, 0x00000004 }, | ||
1539 | { 0x0000e92a, 0x00000004 }, | ||
1540 | { 0x000000d3, 0x00000008 }, | ||
1541 | { 0x02c02000, 0x00000004 }, | ||
1542 | { 0x00060000, 0x00000004 }, | ||
1543 | { 0x000000db, 0x00000034 }, | ||
1544 | { 0x000000d8, 0x00000008 }, | ||
1545 | { 0x00008000, 0x00000004 }, | ||
1546 | { 0xc000e000, 0000000000 }, | ||
1547 | { 0x000000e1, 0x00000030 }, | ||
1548 | { 0x4200e000, 0000000000 }, | ||
1549 | { 0x000000e1, 0x00000030 }, | ||
1550 | { 0x4000e000, 0000000000 }, | ||
1551 | { 0x0025001b, 0x00000004 }, | ||
1552 | { 0x00230000, 0x00000004 }, | ||
1553 | { 0x00250005, 0x00000004 }, | ||
1554 | { 0x000000e6, 0x00000034 }, | ||
1555 | { 0000000000, 0x0000000c }, | ||
1556 | { 0x00244000, 0x00000004 }, | ||
1557 | { 0x080045c8, 0x00000004 }, | ||
1558 | { 0x00240005, 0x00000004 }, | ||
1559 | { 0x08004d0b, 0x0000000c }, | ||
1560 | { 0000000000, 0000000000 }, | ||
1561 | { 0000000000, 0000000000 }, | ||
1562 | { 0000000000, 0000000000 }, | ||
1563 | { 0000000000, 0000000000 }, | ||
1564 | { 0000000000, 0000000000 }, | ||
1565 | { 0000000000, 0000000000 }, | ||
1566 | { 0000000000, 0000000000 }, | ||
1567 | { 0000000000, 0000000000 }, | ||
1568 | { 0000000000, 0000000000 }, | ||
1569 | { 0000000000, 0000000000 }, | ||
1570 | { 0000000000, 0000000000 }, | ||
1571 | { 0000000000, 0000000000 }, | ||
1572 | { 0x000c2000, 0x00000004 }, | ||
1573 | { 0x001d0018, 0x00000004 }, | ||
1574 | { 0x001a0001, 0x00000004 }, | ||
1575 | { 0x000000fb, 0x00000034 }, | ||
1576 | { 0x0000004a, 0x00000008 }, | ||
1577 | { 0x0500a04a, 0x00000008 }, | ||
1578 | { 0000000000, 0000000000 }, | ||
1579 | { 0000000000, 0000000000 }, | ||
1580 | { 0000000000, 0000000000 }, | ||
1581 | { 0000000000, 0000000000 }, | ||
1582 | }; | ||
1583 | |||
1584 | static const u32 R520_cp_microcode[][2] = { | ||
1585 | { 0x4200e000, 0000000000 }, | ||
1586 | { 0x4000e000, 0000000000 }, | ||
1587 | { 0x00000099, 0x00000008 }, | ||
1588 | { 0x0000009d, 0x00000008 }, | ||
1589 | { 0x4a554b4a, 0000000000 }, | ||
1590 | { 0x4a4a4467, 0000000000 }, | ||
1591 | { 0x55526f75, 0000000000 }, | ||
1592 | { 0x4a7e7d65, 0000000000 }, | ||
1593 | { 0xe0dae6f6, 0000000000 }, | ||
1594 | { 0x4ac54a4a, 0000000000 }, | ||
1595 | { 0xc8828282, 0000000000 }, | ||
1596 | { 0xbf4acfc1, 0000000000 }, | ||
1597 | { 0x87b04ad5, 0000000000 }, | ||
1598 | { 0xb5838383, 0000000000 }, | ||
1599 | { 0x4a0f85ba, 0000000000 }, | ||
1600 | { 0x000ca000, 0x00000004 }, | ||
1601 | { 0x000d0012, 0x00000038 }, | ||
1602 | { 0x0000e8b4, 0x00000004 }, | ||
1603 | { 0x000d0014, 0x00000038 }, | ||
1604 | { 0x0000e8b6, 0x00000004 }, | ||
1605 | { 0x000d0016, 0x00000038 }, | ||
1606 | { 0x0000e854, 0x00000004 }, | ||
1607 | { 0x000d0018, 0x00000038 }, | ||
1608 | { 0x0000e855, 0x00000004 }, | ||
1609 | { 0x000d001a, 0x00000038 }, | ||
1610 | { 0x0000e856, 0x00000004 }, | ||
1611 | { 0x000d001c, 0x00000038 }, | ||
1612 | { 0x0000e857, 0x00000004 }, | ||
1613 | { 0x000d001e, 0x00000038 }, | ||
1614 | { 0x0000e824, 0x00000004 }, | ||
1615 | { 0x000d0020, 0x00000038 }, | ||
1616 | { 0x0000e825, 0x00000004 }, | ||
1617 | { 0x000d0022, 0x00000038 }, | ||
1618 | { 0x0000e830, 0x00000004 }, | ||
1619 | { 0x000d0024, 0x00000038 }, | ||
1620 | { 0x0000f0c0, 0x00000004 }, | ||
1621 | { 0x000d0026, 0x00000038 }, | ||
1622 | { 0x0000f0c1, 0x00000004 }, | ||
1623 | { 0x000d0028, 0x00000038 }, | ||
1624 | { 0x0000e000, 0x00000004 }, | ||
1625 | { 0x000d002a, 0x00000038 }, | ||
1626 | { 0x0000e000, 0x00000004 }, | ||
1627 | { 0x000d002c, 0x00000038 }, | ||
1628 | { 0x0000e000, 0x00000004 }, | ||
1629 | { 0x000d002e, 0x00000038 }, | ||
1630 | { 0x0000e000, 0x00000004 }, | ||
1631 | { 0x000d0030, 0x00000038 }, | ||
1632 | { 0x0000e000, 0x00000004 }, | ||
1633 | { 0x000d0032, 0x00000038 }, | ||
1634 | { 0x0000f180, 0x00000004 }, | ||
1635 | { 0x000d0034, 0x00000038 }, | ||
1636 | { 0x0000f393, 0x00000004 }, | ||
1637 | { 0x000d0036, 0x00000038 }, | ||
1638 | { 0x0000f38a, 0x00000004 }, | ||
1639 | { 0x000d0038, 0x00000038 }, | ||
1640 | { 0x0000f38e, 0x00000004 }, | ||
1641 | { 0x0000e821, 0x00000004 }, | ||
1642 | { 0x0140a000, 0x00000004 }, | ||
1643 | { 0x00000043, 0x00000018 }, | ||
1644 | { 0x00cce800, 0x00000004 }, | ||
1645 | { 0x001b0001, 0x00000004 }, | ||
1646 | { 0x08004800, 0x00000004 }, | ||
1647 | { 0x001b0001, 0x00000004 }, | ||
1648 | { 0x08004800, 0x00000004 }, | ||
1649 | { 0x001b0001, 0x00000004 }, | ||
1650 | { 0x08004800, 0x00000004 }, | ||
1651 | { 0x0000003a, 0x00000008 }, | ||
1652 | { 0x0000a000, 0000000000 }, | ||
1653 | { 0x2000451d, 0x00000004 }, | ||
1654 | { 0x0000e580, 0x00000004 }, | ||
1655 | { 0x000ce581, 0x00000004 }, | ||
1656 | { 0x08004580, 0x00000004 }, | ||
1657 | { 0x000ce581, 0x00000004 }, | ||
1658 | { 0x00000047, 0x00000008 }, | ||
1659 | { 0x0000a000, 0000000000 }, | ||
1660 | { 0x000c2000, 0x00000004 }, | ||
1661 | { 0x0000e50e, 0x00000004 }, | ||
1662 | { 0x00032000, 0x00000004 }, | ||
1663 | { 0x00022051, 0x00000028 }, | ||
1664 | { 0x00000051, 0x00000024 }, | ||
1665 | { 0x0800450f, 0x00000004 }, | ||
1666 | { 0x0000a04b, 0x00000008 }, | ||
1667 | { 0x0000e565, 0x00000004 }, | ||
1668 | { 0x0000e566, 0x00000004 }, | ||
1669 | { 0x00000052, 0x00000008 }, | ||
1670 | { 0x03cca5b4, 0x00000004 }, | ||
1671 | { 0x05432000, 0x00000004 }, | ||
1672 | { 0x00022000, 0x00000004 }, | ||
1673 | { 0x4ccce05e, 0x00000030 }, | ||
1674 | { 0x08274565, 0x00000004 }, | ||
1675 | { 0x0000005e, 0x00000030 }, | ||
1676 | { 0x08004564, 0x00000004 }, | ||
1677 | { 0x0000e566, 0x00000004 }, | ||
1678 | { 0x00000055, 0x00000008 }, | ||
1679 | { 0x00802061, 0x00000010 }, | ||
1680 | { 0x00202000, 0x00000004 }, | ||
1681 | { 0x001b00ff, 0x00000004 }, | ||
1682 | { 0x01000064, 0x00000010 }, | ||
1683 | { 0x001f2000, 0x00000004 }, | ||
1684 | { 0x001c00ff, 0x00000004 }, | ||
1685 | { 0000000000, 0x0000000c }, | ||
1686 | { 0x00000072, 0x00000030 }, | ||
1687 | { 0x00000055, 0x00000008 }, | ||
1688 | { 0x0000e576, 0x00000004 }, | ||
1689 | { 0x0000e577, 0x00000004 }, | ||
1690 | { 0x0000e50e, 0x00000004 }, | ||
1691 | { 0x0000e50f, 0x00000004 }, | ||
1692 | { 0x0140a000, 0x00000004 }, | ||
1693 | { 0x00000069, 0x00000018 }, | ||
1694 | { 0x00c0e5f9, 0x000000c2 }, | ||
1695 | { 0x00000069, 0x00000008 }, | ||
1696 | { 0x0014e50e, 0x00000004 }, | ||
1697 | { 0x0040e50f, 0x00000004 }, | ||
1698 | { 0x00c0006c, 0x00000008 }, | ||
1699 | { 0x0000e570, 0x00000004 }, | ||
1700 | { 0x0000e571, 0x00000004 }, | ||
1701 | { 0x0000e572, 0x0000000c }, | ||
1702 | { 0x0000a000, 0x00000004 }, | ||
1703 | { 0x0140a000, 0x00000004 }, | ||
1704 | { 0x0000e568, 0x00000004 }, | ||
1705 | { 0x000c2000, 0x00000004 }, | ||
1706 | { 0x00000076, 0x00000018 }, | ||
1707 | { 0x000b0000, 0x00000004 }, | ||
1708 | { 0x18c0e562, 0x00000004 }, | ||
1709 | { 0x00000078, 0x00000008 }, | ||
1710 | { 0x00c00077, 0x00000008 }, | ||
1711 | { 0x000700c7, 0x00000004 }, | ||
1712 | { 0x00000080, 0x00000038 }, | ||
1713 | { 0x0000e5bb, 0x00000004 }, | ||
1714 | { 0x0000e5bc, 0000000000 }, | ||
1715 | { 0x0000a000, 0x00000004 }, | ||
1716 | { 0x0000e821, 0x00000004 }, | ||
1717 | { 0x0000e800, 0000000000 }, | ||
1718 | { 0x0000e821, 0x00000004 }, | ||
1719 | { 0x0000e82e, 0000000000 }, | ||
1720 | { 0x02cca000, 0x00000004 }, | ||
1721 | { 0x00140000, 0x00000004 }, | ||
1722 | { 0x000ce1cc, 0x00000004 }, | ||
1723 | { 0x050de1cd, 0x00000004 }, | ||
1724 | { 0x00400000, 0x00000004 }, | ||
1725 | { 0x0000008f, 0x00000018 }, | ||
1726 | { 0x00c0a000, 0x00000004 }, | ||
1727 | { 0x0000008c, 0x00000008 }, | ||
1728 | { 0x00000091, 0x00000020 }, | ||
1729 | { 0x4200e000, 0000000000 }, | ||
1730 | { 0x00000098, 0x00000038 }, | ||
1731 | { 0x000ca000, 0x00000004 }, | ||
1732 | { 0x00140000, 0x00000004 }, | ||
1733 | { 0x000c2000, 0x00000004 }, | ||
1734 | { 0x00160000, 0x00000004 }, | ||
1735 | { 0x700ce000, 0x00000004 }, | ||
1736 | { 0x00140094, 0x00000008 }, | ||
1737 | { 0x4000e000, 0000000000 }, | ||
1738 | { 0x02400000, 0x00000004 }, | ||
1739 | { 0x400ee000, 0x00000004 }, | ||
1740 | { 0x02400000, 0x00000004 }, | ||
1741 | { 0x4000e000, 0000000000 }, | ||
1742 | { 0x000c2000, 0x00000004 }, | ||
1743 | { 0x0240e51b, 0x00000004 }, | ||
1744 | { 0x0080e50a, 0x00000005 }, | ||
1745 | { 0x0080e50b, 0x00000005 }, | ||
1746 | { 0x00220000, 0x00000004 }, | ||
1747 | { 0x000700c7, 0x00000004 }, | ||
1748 | { 0x000000a4, 0x00000038 }, | ||
1749 | { 0x0080e5bd, 0x00000005 }, | ||
1750 | { 0x0000e5bb, 0x00000005 }, | ||
1751 | { 0x0080e5bc, 0x00000005 }, | ||
1752 | { 0x00210000, 0x00000004 }, | ||
1753 | { 0x02800000, 0x00000004 }, | ||
1754 | { 0x00c000ab, 0x00000018 }, | ||
1755 | { 0x4180e000, 0x00000040 }, | ||
1756 | { 0x000000ad, 0x00000024 }, | ||
1757 | { 0x01000000, 0x0000000c }, | ||
1758 | { 0x0100e51d, 0x0000000c }, | ||
1759 | { 0x000045bb, 0x00000004 }, | ||
1760 | { 0x000080a7, 0x00000008 }, | ||
1761 | { 0x0000f3ce, 0x00000004 }, | ||
1762 | { 0x0140a000, 0x00000004 }, | ||
1763 | { 0x00cc2000, 0x00000004 }, | ||
1764 | { 0x08c053cf, 0x00000040 }, | ||
1765 | { 0x00008000, 0000000000 }, | ||
1766 | { 0x0000f3d2, 0x00000004 }, | ||
1767 | { 0x0140a000, 0x00000004 }, | ||
1768 | { 0x00cc2000, 0x00000004 }, | ||
1769 | { 0x08c053d3, 0x00000040 }, | ||
1770 | { 0x00008000, 0000000000 }, | ||
1771 | { 0x0000f39d, 0x00000004 }, | ||
1772 | { 0x0140a000, 0x00000004 }, | ||
1773 | { 0x00cc2000, 0x00000004 }, | ||
1774 | { 0x08c0539e, 0x00000040 }, | ||
1775 | { 0x00008000, 0000000000 }, | ||
1776 | { 0x03c00830, 0x00000004 }, | ||
1777 | { 0x4200e000, 0000000000 }, | ||
1778 | { 0x0000a000, 0x00000004 }, | ||
1779 | { 0x200045e0, 0x00000004 }, | ||
1780 | { 0x0000e5e1, 0000000000 }, | ||
1781 | { 0x00000001, 0000000000 }, | ||
1782 | { 0x000700c4, 0x00000004 }, | ||
1783 | { 0x0800e394, 0000000000 }, | ||
1784 | { 0000000000, 0000000000 }, | ||
1785 | { 0x0000e8c4, 0x00000004 }, | ||
1786 | { 0x0000e8c5, 0x00000004 }, | ||
1787 | { 0x0000e8c6, 0x00000004 }, | ||
1788 | { 0x0000e928, 0x00000004 }, | ||
1789 | { 0x0000e929, 0x00000004 }, | ||
1790 | { 0x0000e92a, 0x00000004 }, | ||
1791 | { 0x000000c8, 0x00000008 }, | ||
1792 | { 0x0000e928, 0x00000004 }, | ||
1793 | { 0x0000e929, 0x00000004 }, | ||
1794 | { 0x0000e92a, 0x00000004 }, | ||
1795 | { 0x000000cf, 0x00000008 }, | ||
1796 | { 0xdeadbeef, 0000000000 }, | ||
1797 | { 0x00000116, 0000000000 }, | ||
1798 | { 0x000700d3, 0x00000004 }, | ||
1799 | { 0x080050e7, 0x00000004 }, | ||
1800 | { 0x000700d4, 0x00000004 }, | ||
1801 | { 0x0800401c, 0x00000004 }, | ||
1802 | { 0x0000e01d, 0000000000 }, | ||
1803 | { 0x02c02000, 0x00000004 }, | ||
1804 | { 0x00060000, 0x00000004 }, | ||
1805 | { 0x000000de, 0x00000034 }, | ||
1806 | { 0x000000db, 0x00000008 }, | ||
1807 | { 0x00008000, 0x00000004 }, | ||
1808 | { 0xc000e000, 0000000000 }, | ||
1809 | { 0x0000e1cc, 0x00000004 }, | ||
1810 | { 0x0500e1cd, 0x00000004 }, | ||
1811 | { 0x000ca000, 0x00000004 }, | ||
1812 | { 0x000000e5, 0x00000034 }, | ||
1813 | { 0x000000e1, 0x00000008 }, | ||
1814 | { 0x0000a000, 0000000000 }, | ||
1815 | { 0x0019e1cc, 0x00000004 }, | ||
1816 | { 0x001b0001, 0x00000004 }, | ||
1817 | { 0x0500a000, 0x00000004 }, | ||
1818 | { 0x080041cd, 0x00000004 }, | ||
1819 | { 0x000ca000, 0x00000004 }, | ||
1820 | { 0x000000fb, 0x00000034 }, | ||
1821 | { 0x0000004a, 0x00000008 }, | ||
1822 | { 0000000000, 0000000000 }, | ||
1823 | { 0000000000, 0000000000 }, | ||
1824 | { 0000000000, 0000000000 }, | ||
1825 | { 0000000000, 0000000000 }, | ||
1826 | { 0000000000, 0000000000 }, | ||
1827 | { 0000000000, 0000000000 }, | ||
1828 | { 0000000000, 0000000000 }, | ||
1829 | { 0000000000, 0000000000 }, | ||
1830 | { 0000000000, 0000000000 }, | ||
1831 | { 0x000c2000, 0x00000004 }, | ||
1832 | { 0x001d0018, 0x00000004 }, | ||
1833 | { 0x001a0001, 0x00000004 }, | ||
1834 | { 0x000000fb, 0x00000034 }, | ||
1835 | { 0x0000004a, 0x00000008 }, | ||
1836 | { 0x0500a04a, 0x00000008 }, | ||
1837 | { 0000000000, 0000000000 }, | ||
1838 | { 0000000000, 0000000000 }, | ||
1839 | { 0000000000, 0000000000 }, | ||
1840 | { 0000000000, 0000000000 }, | ||
1841 | }; | ||
1842 | |||
1843 | |||
1844 | #endif | ||
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index 6f75512f591e..11c146b49211 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c | |||
@@ -1662,7 +1662,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev, | |||
1662 | u32 height; | 1662 | u32 height; |
1663 | int i; | 1663 | int i; |
1664 | u32 texpitch, microtile; | 1664 | u32 texpitch, microtile; |
1665 | u32 offset; | 1665 | u32 offset, byte_offset; |
1666 | RING_LOCALS; | 1666 | RING_LOCALS; |
1667 | 1667 | ||
1668 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { | 1668 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { |
@@ -1727,6 +1727,13 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev, | |||
1727 | } else | 1727 | } else |
1728 | microtile = 0; | 1728 | microtile = 0; |
1729 | 1729 | ||
1730 | /* this might fail for zero-sized uploads - are those illegal? */ | ||
1731 | if (!radeon_check_offset(dev_priv, tex->offset + image->height * | ||
1732 | blit_width - 1)) { | ||
1733 | DRM_ERROR("Invalid final destination offset\n"); | ||
1734 | return -EINVAL; | ||
1735 | } | ||
1736 | |||
1730 | DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); | 1737 | DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); |
1731 | 1738 | ||
1732 | do { | 1739 | do { |
@@ -1840,6 +1847,7 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev, | |||
1840 | } | 1847 | } |
1841 | 1848 | ||
1842 | #undef RADEON_COPY_MT | 1849 | #undef RADEON_COPY_MT |
1850 | byte_offset = (image->y & ~2047) * blit_width; | ||
1843 | buf->file_priv = file_priv; | 1851 | buf->file_priv = file_priv; |
1844 | buf->used = size; | 1852 | buf->used = size; |
1845 | offset = dev_priv->gart_buffers_offset + buf->offset; | 1853 | offset = dev_priv->gart_buffers_offset + buf->offset; |
@@ -1854,9 +1862,9 @@ static int radeon_cp_dispatch_texture(struct drm_device * dev, | |||
1854 | RADEON_DP_SRC_SOURCE_MEMORY | | 1862 | RADEON_DP_SRC_SOURCE_MEMORY | |
1855 | RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); | 1863 | RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); |
1856 | OUT_RING((spitch << 22) | (offset >> 10)); | 1864 | OUT_RING((spitch << 22) | (offset >> 10)); |
1857 | OUT_RING((texpitch << 22) | (tex->offset >> 10)); | 1865 | OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10))); |
1858 | OUT_RING(0); | 1866 | OUT_RING(0); |
1859 | OUT_RING((image->x << 16) | image->y); | 1867 | OUT_RING((image->x << 16) | (image->y % 2048)); |
1860 | OUT_RING((image->width << 16) | height); | 1868 | OUT_RING((image->width << 16) | height); |
1861 | RADEON_WAIT_UNTIL_2D_IDLE(); | 1869 | RADEON_WAIT_UNTIL_2D_IDLE(); |
1862 | ADVANCE_RING(); | 1870 | ADVANCE_RING(); |
@@ -3037,6 +3045,9 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil | |||
3037 | case RADEON_PARAM_FB_LOCATION: | 3045 | case RADEON_PARAM_FB_LOCATION: |
3038 | value = radeon_read_fb_location(dev_priv); | 3046 | value = radeon_read_fb_location(dev_priv); |
3039 | break; | 3047 | break; |
3048 | case RADEON_PARAM_NUM_GB_PIPES: | ||
3049 | value = dev_priv->num_gb_pipes; | ||
3050 | break; | ||
3040 | default: | 3051 | default: |
3041 | DRM_DEBUG("Invalid parameter %d\n", param->param); | 3052 | DRM_DEBUG("Invalid parameter %d\n", param->param); |
3042 | return -EINVAL; | 3053 | return -EINVAL; |
diff --git a/drivers/char/tty_io.c b/drivers/char/tty_io.c index e94bee032314..750131010af0 100644 --- a/drivers/char/tty_io.c +++ b/drivers/char/tty_io.c | |||
@@ -3322,7 +3322,7 @@ static int send_break(struct tty_struct *tty, unsigned int duration) | |||
3322 | msleep_interruptible(duration); | 3322 | msleep_interruptible(duration); |
3323 | tty->ops->break_ctl(tty, 0); | 3323 | tty->ops->break_ctl(tty, 0); |
3324 | tty_write_unlock(tty); | 3324 | tty_write_unlock(tty); |
3325 | if (!signal_pending(current)) | 3325 | if (signal_pending(current)) |
3326 | return -EINTR; | 3326 | return -EINTR; |
3327 | return 0; | 3327 | return 0; |
3328 | } | 3328 | } |
diff --git a/drivers/char/tty_ioctl.c b/drivers/char/tty_ioctl.c index b1a757a5ee27..8f81139d6194 100644 --- a/drivers/char/tty_ioctl.c +++ b/drivers/char/tty_ioctl.c | |||
@@ -981,16 +981,9 @@ EXPORT_SYMBOL_GPL(tty_perform_flush); | |||
981 | int n_tty_ioctl(struct tty_struct *tty, struct file *file, | 981 | int n_tty_ioctl(struct tty_struct *tty, struct file *file, |
982 | unsigned int cmd, unsigned long arg) | 982 | unsigned int cmd, unsigned long arg) |
983 | { | 983 | { |
984 | struct tty_struct *real_tty; | ||
985 | unsigned long flags; | 984 | unsigned long flags; |
986 | int retval; | 985 | int retval; |
987 | 986 | ||
988 | if (tty->driver->type == TTY_DRIVER_TYPE_PTY && | ||
989 | tty->driver->subtype == PTY_TYPE_MASTER) | ||
990 | real_tty = tty->link; | ||
991 | else | ||
992 | real_tty = tty; | ||
993 | |||
994 | switch (cmd) { | 987 | switch (cmd) { |
995 | case TCXONC: | 988 | case TCXONC: |
996 | retval = tty_check_change(tty); | 989 | retval = tty_check_change(tty); |
diff --git a/drivers/firewire/Kconfig b/drivers/firewire/Kconfig index fb4d391810b6..76f26710fc16 100644 --- a/drivers/firewire/Kconfig +++ b/drivers/firewire/Kconfig | |||
@@ -1,28 +1,26 @@ | |||
1 | comment "An alternative FireWire stack is available with EXPERIMENTAL=y" | 1 | comment "A new alternative FireWire stack is available with EXPERIMENTAL=y" |
2 | depends on EXPERIMENTAL=n | 2 | depends on EXPERIMENTAL=n |
3 | 3 | ||
4 | comment "Enable only one of the two stacks, unless you know what you are doing" | ||
5 | depends on EXPERIMENTAL | ||
6 | |||
4 | config FIREWIRE | 7 | config FIREWIRE |
5 | tristate "IEEE 1394 (FireWire) support - alternative stack, EXPERIMENTAL" | 8 | tristate "New FireWire stack, EXPERIMENTAL" |
6 | depends on EXPERIMENTAL | 9 | depends on EXPERIMENTAL |
7 | select CRC_ITU_T | 10 | select CRC_ITU_T |
8 | help | 11 | help |
9 | This is the "Juju" FireWire stack, a new alternative implementation | 12 | This is the "Juju" FireWire stack, a new alternative implementation |
10 | designed for robustness and simplicity. You can build either this | 13 | designed for robustness and simplicity. You can build either this |
11 | stack, or the classic stack (the ieee1394 driver, ohci1394 etc.) | 14 | stack, or the old stack (the ieee1394 driver, ohci1394 etc.) or both. |
12 | or both. Please read http://wiki.linux1394.org/JujuMigration before | 15 | Please read http://wiki.linux1394.org/JujuMigration before you |
13 | you enable the new stack. | 16 | enable the new stack. |
14 | 17 | ||
15 | To compile this driver as a module, say M here: the module will be | 18 | To compile this driver as a module, say M here: the module will be |
16 | called firewire-core. It functionally replaces ieee1394, raw1394, | 19 | called firewire-core. It functionally replaces ieee1394, raw1394, |
17 | and video1394. | 20 | and video1394. |
18 | 21 | ||
19 | NOTE: | ||
20 | |||
21 | You should only build ONE of the stacks, unless you REALLY know what | ||
22 | you are doing. | ||
23 | |||
24 | config FIREWIRE_OHCI | 22 | config FIREWIRE_OHCI |
25 | tristate "Support for OHCI FireWire host controllers" | 23 | tristate "OHCI-1394 controllers" |
26 | depends on PCI && FIREWIRE | 24 | depends on PCI && FIREWIRE |
27 | help | 25 | help |
28 | Enable this driver if you have a FireWire controller based | 26 | Enable this driver if you have a FireWire controller based |
@@ -33,12 +31,12 @@ config FIREWIRE_OHCI | |||
33 | called firewire-ohci. It replaces ohci1394 of the classic IEEE 1394 | 31 | called firewire-ohci. It replaces ohci1394 of the classic IEEE 1394 |
34 | stack. | 32 | stack. |
35 | 33 | ||
36 | NOTE: | 34 | NOTE: |
37 | 35 | ||
38 | You should only build ohci1394 or firewire-ohci, but not both. | 36 | You should only build either firewire-ohci or the old ohci1394 driver, |
39 | If you nevertheless want to install both, you should configure them | 37 | but not both. If you nevertheless want to install both, you should |
40 | only as modules and blacklist the driver(s) which you don't want to | 38 | configure them only as modules and blacklist the driver(s) which you |
41 | have auto-loaded. Add either | 39 | don't want to have auto-loaded. Add either |
42 | 40 | ||
43 | blacklist firewire-ohci | 41 | blacklist firewire-ohci |
44 | or | 42 | or |
@@ -60,7 +58,7 @@ config FIREWIRE_OHCI_DEBUG | |||
60 | default y | 58 | default y |
61 | 59 | ||
62 | config FIREWIRE_SBP2 | 60 | config FIREWIRE_SBP2 |
63 | tristate "Support for storage devices (SBP-2 protocol driver)" | 61 | tristate "Storage devices (SBP-2 protocol)" |
64 | depends on FIREWIRE && SCSI | 62 | depends on FIREWIRE && SCSI |
65 | help | 63 | help |
66 | This option enables you to use SBP-2 devices connected to a | 64 | This option enables you to use SBP-2 devices connected to a |
diff --git a/drivers/firewire/fw-cdev.c b/drivers/firewire/fw-cdev.c index dda14015e873..c639915fc3cb 100644 --- a/drivers/firewire/fw-cdev.c +++ b/drivers/firewire/fw-cdev.c | |||
@@ -205,6 +205,7 @@ fw_device_op_read(struct file *file, | |||
205 | return dequeue_event(client, buffer, count); | 205 | return dequeue_event(client, buffer, count); |
206 | } | 206 | } |
207 | 207 | ||
208 | /* caller must hold card->lock so that node pointers can be dereferenced here */ | ||
208 | static void | 209 | static void |
209 | fill_bus_reset_event(struct fw_cdev_event_bus_reset *event, | 210 | fill_bus_reset_event(struct fw_cdev_event_bus_reset *event, |
210 | struct client *client) | 211 | struct client *client) |
@@ -214,7 +215,6 @@ fill_bus_reset_event(struct fw_cdev_event_bus_reset *event, | |||
214 | event->closure = client->bus_reset_closure; | 215 | event->closure = client->bus_reset_closure; |
215 | event->type = FW_CDEV_EVENT_BUS_RESET; | 216 | event->type = FW_CDEV_EVENT_BUS_RESET; |
216 | event->generation = client->device->generation; | 217 | event->generation = client->device->generation; |
217 | smp_rmb(); /* node_id must not be older than generation */ | ||
218 | event->node_id = client->device->node_id; | 218 | event->node_id = client->device->node_id; |
219 | event->local_node_id = card->local_node->node_id; | 219 | event->local_node_id = card->local_node->node_id; |
220 | event->bm_node_id = 0; /* FIXME: We don't track the BM. */ | 220 | event->bm_node_id = 0; /* FIXME: We don't track the BM. */ |
@@ -274,6 +274,7 @@ static int ioctl_get_info(struct client *client, void *buffer) | |||
274 | { | 274 | { |
275 | struct fw_cdev_get_info *get_info = buffer; | 275 | struct fw_cdev_get_info *get_info = buffer; |
276 | struct fw_cdev_event_bus_reset bus_reset; | 276 | struct fw_cdev_event_bus_reset bus_reset; |
277 | struct fw_card *card = client->device->card; | ||
277 | unsigned long ret = 0; | 278 | unsigned long ret = 0; |
278 | 279 | ||
279 | client->version = get_info->version; | 280 | client->version = get_info->version; |
@@ -299,13 +300,17 @@ static int ioctl_get_info(struct client *client, void *buffer) | |||
299 | client->bus_reset_closure = get_info->bus_reset_closure; | 300 | client->bus_reset_closure = get_info->bus_reset_closure; |
300 | if (get_info->bus_reset != 0) { | 301 | if (get_info->bus_reset != 0) { |
301 | void __user *uptr = u64_to_uptr(get_info->bus_reset); | 302 | void __user *uptr = u64_to_uptr(get_info->bus_reset); |
303 | unsigned long flags; | ||
302 | 304 | ||
305 | spin_lock_irqsave(&card->lock, flags); | ||
303 | fill_bus_reset_event(&bus_reset, client); | 306 | fill_bus_reset_event(&bus_reset, client); |
307 | spin_unlock_irqrestore(&card->lock, flags); | ||
308 | |||
304 | if (copy_to_user(uptr, &bus_reset, sizeof(bus_reset))) | 309 | if (copy_to_user(uptr, &bus_reset, sizeof(bus_reset))) |
305 | return -EFAULT; | 310 | return -EFAULT; |
306 | } | 311 | } |
307 | 312 | ||
308 | get_info->card = client->device->card->index; | 313 | get_info->card = card->index; |
309 | 314 | ||
310 | return 0; | 315 | return 0; |
311 | } | 316 | } |
diff --git a/drivers/firewire/fw-ohci.c b/drivers/firewire/fw-ohci.c index 4f02c55f13e1..0b66306af479 100644 --- a/drivers/firewire/fw-ohci.c +++ b/drivers/firewire/fw-ohci.c | |||
@@ -265,27 +265,25 @@ static void log_irqs(u32 evt) | |||
265 | !(evt & OHCI1394_busReset)) | 265 | !(evt & OHCI1394_busReset)) |
266 | return; | 266 | return; |
267 | 267 | ||
268 | printk(KERN_DEBUG KBUILD_MODNAME ": IRQ " | 268 | fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, |
269 | "%08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", | 269 | evt & OHCI1394_selfIDComplete ? " selfID" : "", |
270 | evt, | 270 | evt & OHCI1394_RQPkt ? " AR_req" : "", |
271 | evt & OHCI1394_selfIDComplete ? " selfID" : "", | 271 | evt & OHCI1394_RSPkt ? " AR_resp" : "", |
272 | evt & OHCI1394_RQPkt ? " AR_req" : "", | 272 | evt & OHCI1394_reqTxComplete ? " AT_req" : "", |
273 | evt & OHCI1394_RSPkt ? " AR_resp" : "", | 273 | evt & OHCI1394_respTxComplete ? " AT_resp" : "", |
274 | evt & OHCI1394_reqTxComplete ? " AT_req" : "", | 274 | evt & OHCI1394_isochRx ? " IR" : "", |
275 | evt & OHCI1394_respTxComplete ? " AT_resp" : "", | 275 | evt & OHCI1394_isochTx ? " IT" : "", |
276 | evt & OHCI1394_isochRx ? " IR" : "", | 276 | evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", |
277 | evt & OHCI1394_isochTx ? " IT" : "", | 277 | evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", |
278 | evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", | 278 | evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", |
279 | evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", | 279 | evt & OHCI1394_regAccessFail ? " regAccessFail" : "", |
280 | evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", | 280 | evt & OHCI1394_busReset ? " busReset" : "", |
281 | evt & OHCI1394_regAccessFail ? " regAccessFail" : "", | 281 | evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | |
282 | evt & OHCI1394_busReset ? " busReset" : "", | 282 | OHCI1394_RSPkt | OHCI1394_reqTxComplete | |
283 | evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | | 283 | OHCI1394_respTxComplete | OHCI1394_isochRx | |
284 | OHCI1394_RSPkt | OHCI1394_reqTxComplete | | 284 | OHCI1394_isochTx | OHCI1394_postedWriteErr | |
285 | OHCI1394_respTxComplete | OHCI1394_isochRx | | 285 | OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | |
286 | OHCI1394_isochTx | OHCI1394_postedWriteErr | | 286 | OHCI1394_regAccessFail | OHCI1394_busReset) |
287 | OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | | ||
288 | OHCI1394_regAccessFail | OHCI1394_busReset) | ||
289 | ? " ?" : ""); | 287 | ? " ?" : ""); |
290 | } | 288 | } |
291 | 289 | ||
@@ -308,23 +306,22 @@ static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) | |||
308 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) | 306 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) |
309 | return; | 307 | return; |
310 | 308 | ||
311 | printk(KERN_DEBUG KBUILD_MODNAME ": %d selfIDs, generation %d, " | 309 | fw_notify("%d selfIDs, generation %d, local node ID %04x\n", |
312 | "local node ID %04x\n", self_id_count, generation, node_id); | 310 | self_id_count, generation, node_id); |
313 | 311 | ||
314 | for (; self_id_count--; ++s) | 312 | for (; self_id_count--; ++s) |
315 | if ((*s & 1 << 23) == 0) | 313 | if ((*s & 1 << 23) == 0) |
316 | printk(KERN_DEBUG "selfID 0: %08x, phy %d [%c%c%c] " | 314 | fw_notify("selfID 0: %08x, phy %d [%c%c%c] " |
317 | "%s gc=%d %s %s%s%s\n", | 315 | "%s gc=%d %s %s%s%s\n", |
318 | *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), | 316 | *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), |
319 | speed[*s >> 14 & 3], *s >> 16 & 63, | 317 | speed[*s >> 14 & 3], *s >> 16 & 63, |
320 | power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", | 318 | power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", |
321 | *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); | 319 | *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); |
322 | else | 320 | else |
323 | printk(KERN_DEBUG "selfID n: %08x, phy %d " | 321 | fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", |
324 | "[%c%c%c%c%c%c%c%c]\n", | 322 | *s, *s >> 24 & 63, |
325 | *s, *s >> 24 & 63, | 323 | _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), |
326 | _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), | 324 | _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); |
327 | _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); | ||
328 | } | 325 | } |
329 | 326 | ||
330 | static const char *evts[] = { | 327 | static const char *evts[] = { |
@@ -373,15 +370,14 @@ static void log_ar_at_event(char dir, int speed, u32 *header, int evt) | |||
373 | evt = 0x1f; | 370 | evt = 0x1f; |
374 | 371 | ||
375 | if (evt == OHCI1394_evt_bus_reset) { | 372 | if (evt == OHCI1394_evt_bus_reset) { |
376 | printk(KERN_DEBUG "A%c evt_bus_reset, generation %d\n", | 373 | fw_notify("A%c evt_bus_reset, generation %d\n", |
377 | dir, (header[2] >> 16) & 0xff); | 374 | dir, (header[2] >> 16) & 0xff); |
378 | return; | 375 | return; |
379 | } | 376 | } |
380 | 377 | ||
381 | if (header[0] == ~header[1]) { | 378 | if (header[0] == ~header[1]) { |
382 | printk(KERN_DEBUG "A%c %s, %s, %08x\n", | 379 | fw_notify("A%c %s, %s, %08x\n", |
383 | dir, evts[evt], phys[header[0] >> 30 & 0x3], | 380 | dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]); |
384 | header[0]); | ||
385 | return; | 381 | return; |
386 | } | 382 | } |
387 | 383 | ||
@@ -400,24 +396,23 @@ static void log_ar_at_event(char dir, int speed, u32 *header, int evt) | |||
400 | 396 | ||
401 | switch (tcode) { | 397 | switch (tcode) { |
402 | case 0xe: case 0xa: | 398 | case 0xe: case 0xa: |
403 | printk(KERN_DEBUG "A%c %s, %s\n", | 399 | fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); |
404 | dir, evts[evt], tcodes[tcode]); | ||
405 | break; | 400 | break; |
406 | case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: | 401 | case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: |
407 | printk(KERN_DEBUG "A%c spd %x tl %02x, " | 402 | fw_notify("A%c spd %x tl %02x, " |
408 | "%04x -> %04x, %s, " | 403 | "%04x -> %04x, %s, " |
409 | "%s, %04x%08x%s\n", | 404 | "%s, %04x%08x%s\n", |
410 | dir, speed, header[0] >> 10 & 0x3f, | 405 | dir, speed, header[0] >> 10 & 0x3f, |
411 | header[1] >> 16, header[0] >> 16, evts[evt], | 406 | header[1] >> 16, header[0] >> 16, evts[evt], |
412 | tcodes[tcode], header[1] & 0xffff, header[2], specific); | 407 | tcodes[tcode], header[1] & 0xffff, header[2], specific); |
413 | break; | 408 | break; |
414 | default: | 409 | default: |
415 | printk(KERN_DEBUG "A%c spd %x tl %02x, " | 410 | fw_notify("A%c spd %x tl %02x, " |
416 | "%04x -> %04x, %s, " | 411 | "%04x -> %04x, %s, " |
417 | "%s%s\n", | 412 | "%s%s\n", |
418 | dir, speed, header[0] >> 10 & 0x3f, | 413 | dir, speed, header[0] >> 10 & 0x3f, |
419 | header[1] >> 16, header[0] >> 16, evts[evt], | 414 | header[1] >> 16, header[0] >> 16, evts[evt], |
420 | tcodes[tcode], specific); | 415 | tcodes[tcode], specific); |
421 | } | 416 | } |
422 | } | 417 | } |
423 | 418 | ||
@@ -548,6 +543,11 @@ static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) | |||
548 | p.header_length = 12; | 543 | p.header_length = 12; |
549 | p.payload_length = 0; | 544 | p.payload_length = 0; |
550 | break; | 545 | break; |
546 | |||
547 | default: | ||
548 | /* FIXME: Stop context, discard everything, and restart? */ | ||
549 | p.header_length = 0; | ||
550 | p.payload_length = 0; | ||
551 | } | 551 | } |
552 | 552 | ||
553 | p.payload = (void *) buffer + p.header_length; | 553 | p.payload = (void *) buffer + p.header_length; |
@@ -1468,6 +1468,9 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) | |||
1468 | reg_write(ohci, OHCI1394_HCControlClear, | 1468 | reg_write(ohci, OHCI1394_HCControlClear, |
1469 | OHCI1394_HCControl_noByteSwapData); | 1469 | OHCI1394_HCControl_noByteSwapData); |
1470 | 1470 | ||
1471 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | ||
1472 | reg_write(ohci, OHCI1394_LinkControlClear, | ||
1473 | OHCI1394_LinkControl_rcvPhyPkt); | ||
1471 | reg_write(ohci, OHCI1394_LinkControlSet, | 1474 | reg_write(ohci, OHCI1394_LinkControlSet, |
1472 | OHCI1394_LinkControl_rcvSelfID | | 1475 | OHCI1394_LinkControl_rcvSelfID | |
1473 | OHCI1394_LinkControl_cycleTimerEnable | | 1476 | OHCI1394_LinkControl_cycleTimerEnable | |
@@ -1481,7 +1484,6 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) | |||
1481 | ar_context_run(&ohci->ar_request_ctx); | 1484 | ar_context_run(&ohci->ar_request_ctx); |
1482 | ar_context_run(&ohci->ar_response_ctx); | 1485 | ar_context_run(&ohci->ar_response_ctx); |
1483 | 1486 | ||
1484 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | ||
1485 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); | 1487 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); |
1486 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | 1488 | reg_write(ohci, OHCI1394_IntEventClear, ~0); |
1487 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | 1489 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); |
diff --git a/drivers/firewire/fw-sbp2.c b/drivers/firewire/fw-sbp2.c index b2458bb8e9ca..227d2e036cd8 100644 --- a/drivers/firewire/fw-sbp2.c +++ b/drivers/firewire/fw-sbp2.c | |||
@@ -1051,7 +1051,8 @@ static int sbp2_scan_unit_dir(struct sbp2_target *tgt, u32 *directory, | |||
1051 | break; | 1051 | break; |
1052 | 1052 | ||
1053 | case SBP2_CSR_LOGICAL_UNIT_DIRECTORY: | 1053 | case SBP2_CSR_LOGICAL_UNIT_DIRECTORY: |
1054 | if (sbp2_scan_logical_unit_dir(tgt, ci.p + value) < 0) | 1054 | /* Adjust for the increment in the iterator */ |
1055 | if (sbp2_scan_logical_unit_dir(tgt, ci.p - 1 + value) < 0) | ||
1055 | return -ENOMEM; | 1056 | return -ENOMEM; |
1056 | break; | 1057 | break; |
1057 | } | 1058 | } |
diff --git a/drivers/firewire/fw-transaction.c b/drivers/firewire/fw-transaction.c index ccf0e4cf108f..03ae8a77c479 100644 --- a/drivers/firewire/fw-transaction.c +++ b/drivers/firewire/fw-transaction.c | |||
@@ -20,6 +20,7 @@ | |||
20 | 20 | ||
21 | #include <linux/completion.h> | 21 | #include <linux/completion.h> |
22 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
23 | #include <linux/kref.h> | ||
23 | #include <linux/module.h> | 24 | #include <linux/module.h> |
24 | #include <linux/init.h> | 25 | #include <linux/init.h> |
25 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
@@ -297,37 +298,55 @@ EXPORT_SYMBOL(fw_send_request); | |||
297 | struct fw_phy_packet { | 298 | struct fw_phy_packet { |
298 | struct fw_packet packet; | 299 | struct fw_packet packet; |
299 | struct completion done; | 300 | struct completion done; |
301 | struct kref kref; | ||
300 | }; | 302 | }; |
301 | 303 | ||
302 | static void | 304 | static void phy_packet_release(struct kref *kref) |
303 | transmit_phy_packet_callback(struct fw_packet *packet, | 305 | { |
304 | struct fw_card *card, int status) | 306 | struct fw_phy_packet *p = |
307 | container_of(kref, struct fw_phy_packet, kref); | ||
308 | kfree(p); | ||
309 | } | ||
310 | |||
311 | static void transmit_phy_packet_callback(struct fw_packet *packet, | ||
312 | struct fw_card *card, int status) | ||
305 | { | 313 | { |
306 | struct fw_phy_packet *p = | 314 | struct fw_phy_packet *p = |
307 | container_of(packet, struct fw_phy_packet, packet); | 315 | container_of(packet, struct fw_phy_packet, packet); |
308 | 316 | ||
309 | complete(&p->done); | 317 | complete(&p->done); |
318 | kref_put(&p->kref, phy_packet_release); | ||
310 | } | 319 | } |
311 | 320 | ||
312 | void fw_send_phy_config(struct fw_card *card, | 321 | void fw_send_phy_config(struct fw_card *card, |
313 | int node_id, int generation, int gap_count) | 322 | int node_id, int generation, int gap_count) |
314 | { | 323 | { |
315 | struct fw_phy_packet p; | 324 | struct fw_phy_packet *p; |
325 | long timeout = DIV_ROUND_UP(HZ, 10); | ||
316 | u32 data = PHY_IDENTIFIER(PHY_PACKET_CONFIG) | | 326 | u32 data = PHY_IDENTIFIER(PHY_PACKET_CONFIG) | |
317 | PHY_CONFIG_ROOT_ID(node_id) | | 327 | PHY_CONFIG_ROOT_ID(node_id) | |
318 | PHY_CONFIG_GAP_COUNT(gap_count); | 328 | PHY_CONFIG_GAP_COUNT(gap_count); |
319 | 329 | ||
320 | p.packet.header[0] = data; | 330 | p = kmalloc(sizeof(*p), GFP_KERNEL); |
321 | p.packet.header[1] = ~data; | 331 | if (p == NULL) |
322 | p.packet.header_length = 8; | 332 | return; |
323 | p.packet.payload_length = 0; | 333 | |
324 | p.packet.speed = SCODE_100; | 334 | p->packet.header[0] = data; |
325 | p.packet.generation = generation; | 335 | p->packet.header[1] = ~data; |
326 | p.packet.callback = transmit_phy_packet_callback; | 336 | p->packet.header_length = 8; |
327 | init_completion(&p.done); | 337 | p->packet.payload_length = 0; |
328 | 338 | p->packet.speed = SCODE_100; | |
329 | card->driver->send_request(card, &p.packet); | 339 | p->packet.generation = generation; |
330 | wait_for_completion(&p.done); | 340 | p->packet.callback = transmit_phy_packet_callback; |
341 | init_completion(&p->done); | ||
342 | kref_set(&p->kref, 2); | ||
343 | |||
344 | card->driver->send_request(card, &p->packet); | ||
345 | timeout = wait_for_completion_timeout(&p->done, timeout); | ||
346 | kref_put(&p->kref, phy_packet_release); | ||
347 | |||
348 | /* will leak p if the callback is never executed */ | ||
349 | WARN_ON(timeout == 0); | ||
331 | } | 350 | } |
332 | 351 | ||
333 | void fw_flush_transactions(struct fw_card *card) | 352 | void fw_flush_transactions(struct fw_card *card) |
@@ -572,7 +591,8 @@ allocate_request(struct fw_packet *p) | |||
572 | break; | 591 | break; |
573 | 592 | ||
574 | default: | 593 | default: |
575 | BUG(); | 594 | fw_error("ERROR - corrupt request received - %08x %08x %08x\n", |
595 | p->header[0], p->header[1], p->header[2]); | ||
576 | return NULL; | 596 | return NULL; |
577 | } | 597 | } |
578 | 598 | ||
diff --git a/drivers/hwmon/abituguru3.c b/drivers/hwmon/abituguru3.c index ed33fddc4dee..f00f497b9ca9 100644 --- a/drivers/hwmon/abituguru3.c +++ b/drivers/hwmon/abituguru3.c | |||
@@ -30,6 +30,7 @@ | |||
30 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
31 | #include <linux/hwmon.h> | 31 | #include <linux/hwmon.h> |
32 | #include <linux/hwmon-sysfs.h> | 32 | #include <linux/hwmon-sysfs.h> |
33 | #include <linux/dmi.h> | ||
33 | #include <asm/io.h> | 34 | #include <asm/io.h> |
34 | 35 | ||
35 | /* uGuru3 bank addresses */ | 36 | /* uGuru3 bank addresses */ |
@@ -323,7 +324,7 @@ static const struct abituguru3_motherboard_info abituguru3_motherboards[] = { | |||
323 | { "AUX1 Fan", 36, 2, 60, 1, 0 }, | 324 | { "AUX1 Fan", 36, 2, 60, 1, 0 }, |
324 | { NULL, 0, 0, 0, 0, 0 } } | 325 | { NULL, 0, 0, 0, 0, 0 } } |
325 | }, | 326 | }, |
326 | { 0x0013, "unknown", { | 327 | { 0x0013, "Abit AW8D", { |
327 | { "CPU Core", 0, 0, 10, 1, 0 }, | 328 | { "CPU Core", 0, 0, 10, 1, 0 }, |
328 | { "DDR", 1, 0, 10, 1, 0 }, | 329 | { "DDR", 1, 0, 10, 1, 0 }, |
329 | { "DDR VTT", 2, 0, 10, 1, 0 }, | 330 | { "DDR VTT", 2, 0, 10, 1, 0 }, |
@@ -349,6 +350,7 @@ static const struct abituguru3_motherboard_info abituguru3_motherboards[] = { | |||
349 | { "AUX2 Fan", 36, 2, 60, 1, 0 }, | 350 | { "AUX2 Fan", 36, 2, 60, 1, 0 }, |
350 | { "AUX3 Fan", 37, 2, 60, 1, 0 }, | 351 | { "AUX3 Fan", 37, 2, 60, 1, 0 }, |
351 | { "AUX4 Fan", 38, 2, 60, 1, 0 }, | 352 | { "AUX4 Fan", 38, 2, 60, 1, 0 }, |
353 | { "AUX5 Fan", 39, 2, 60, 1, 0 }, | ||
352 | { NULL, 0, 0, 0, 0, 0 } } | 354 | { NULL, 0, 0, 0, 0, 0 } } |
353 | }, | 355 | }, |
354 | { 0x0014, "Abit AB9 Pro", { | 356 | { 0x0014, "Abit AB9 Pro", { |
@@ -1111,11 +1113,12 @@ static int __init abituguru3_detect(void) | |||
1111 | { | 1113 | { |
1112 | /* See if there is an uguru3 there. An idle uGuru3 will hold 0x00 or | 1114 | /* See if there is an uguru3 there. An idle uGuru3 will hold 0x00 or |
1113 | 0x08 at DATA and 0xAC at CMD. Sometimes the uGuru3 will hold 0x05 | 1115 | 0x08 at DATA and 0xAC at CMD. Sometimes the uGuru3 will hold 0x05 |
1114 | at CMD instead, why is unknown. So we test for 0x05 too. */ | 1116 | or 0x55 at CMD instead, why is unknown. */ |
1115 | u8 data_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_DATA); | 1117 | u8 data_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_DATA); |
1116 | u8 cmd_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_CMD); | 1118 | u8 cmd_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_CMD); |
1117 | if (((data_val == 0x00) || (data_val == 0x08)) && | 1119 | if (((data_val == 0x00) || (data_val == 0x08)) && |
1118 | ((cmd_val == 0xAC) || (cmd_val == 0x05))) | 1120 | ((cmd_val == 0xAC) || (cmd_val == 0x05) || |
1121 | (cmd_val == 0x55))) | ||
1119 | return ABIT_UGURU3_BASE; | 1122 | return ABIT_UGURU3_BASE; |
1120 | 1123 | ||
1121 | ABIT_UGURU3_DEBUG("no Abit uGuru3 found, data = 0x%02X, cmd = " | 1124 | ABIT_UGURU3_DEBUG("no Abit uGuru3 found, data = 0x%02X, cmd = " |
@@ -1138,6 +1141,15 @@ static int __init abituguru3_init(void) | |||
1138 | int address, err; | 1141 | int address, err; |
1139 | struct resource res = { .flags = IORESOURCE_IO }; | 1142 | struct resource res = { .flags = IORESOURCE_IO }; |
1140 | 1143 | ||
1144 | #ifdef CONFIG_DMI | ||
1145 | const char *board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR); | ||
1146 | |||
1147 | /* safety check, refuse to load on non Abit motherboards */ | ||
1148 | if (!force && (!board_vendor || | ||
1149 | strcmp(board_vendor, "http://www.abit.com.tw/"))) | ||
1150 | return -ENODEV; | ||
1151 | #endif | ||
1152 | |||
1141 | address = abituguru3_detect(); | 1153 | address = abituguru3_detect(); |
1142 | if (address < 0) | 1154 | if (address < 0) |
1143 | return address; | 1155 | return address; |
diff --git a/drivers/hwmon/adt7473.c b/drivers/hwmon/adt7473.c index c1009d6f9796..93dbf5e7ff8a 100644 --- a/drivers/hwmon/adt7473.c +++ b/drivers/hwmon/adt7473.c | |||
@@ -309,6 +309,9 @@ no_sensor_update: | |||
309 | ADT7473_REG_PWM_BHVR(i)); | 309 | ADT7473_REG_PWM_BHVR(i)); |
310 | } | 310 | } |
311 | 311 | ||
312 | i = i2c_smbus_read_byte_data(client, ADT7473_REG_CFG4); | ||
313 | data->max_duty_at_overheat = !!(i & ADT7473_CFG4_MAX_DUTY_AT_OVT); | ||
314 | |||
312 | data->limits_last_updated = local_jiffies; | 315 | data->limits_last_updated = local_jiffies; |
313 | data->limits_valid = 1; | 316 | data->limits_valid = 1; |
314 | 317 | ||
diff --git a/drivers/hwmon/lm75.c b/drivers/hwmon/lm75.c index fa7696905154..de698dc73020 100644 --- a/drivers/hwmon/lm75.c +++ b/drivers/hwmon/lm75.c | |||
@@ -251,10 +251,13 @@ static int lm75_detach_client(struct i2c_client *client) | |||
251 | the SMBus standard. */ | 251 | the SMBus standard. */ |
252 | static int lm75_read_value(struct i2c_client *client, u8 reg) | 252 | static int lm75_read_value(struct i2c_client *client, u8 reg) |
253 | { | 253 | { |
254 | int value; | ||
255 | |||
254 | if (reg == LM75_REG_CONF) | 256 | if (reg == LM75_REG_CONF) |
255 | return i2c_smbus_read_byte_data(client, reg); | 257 | return i2c_smbus_read_byte_data(client, reg); |
256 | else | 258 | |
257 | return swab16(i2c_smbus_read_word_data(client, reg)); | 259 | value = i2c_smbus_read_word_data(client, reg); |
260 | return (value < 0) ? value : swab16(value); | ||
258 | } | 261 | } |
259 | 262 | ||
260 | static int lm75_write_value(struct i2c_client *client, u8 reg, u16 value) | 263 | static int lm75_write_value(struct i2c_client *client, u8 reg, u16 value) |
@@ -287,9 +290,16 @@ static struct lm75_data *lm75_update_device(struct device *dev) | |||
287 | int i; | 290 | int i; |
288 | dev_dbg(&client->dev, "Starting lm75 update\n"); | 291 | dev_dbg(&client->dev, "Starting lm75 update\n"); |
289 | 292 | ||
290 | for (i = 0; i < ARRAY_SIZE(data->temp); i++) | 293 | for (i = 0; i < ARRAY_SIZE(data->temp); i++) { |
291 | data->temp[i] = lm75_read_value(client, | 294 | int status; |
292 | LM75_REG_TEMP[i]); | 295 | |
296 | status = lm75_read_value(client, LM75_REG_TEMP[i]); | ||
297 | if (status < 0) | ||
298 | dev_dbg(&client->dev, "reg %d, err %d\n", | ||
299 | LM75_REG_TEMP[i], status); | ||
300 | else | ||
301 | data->temp[i] = status; | ||
302 | } | ||
293 | data->last_updated = jiffies; | 303 | data->last_updated = jiffies; |
294 | data->valid = 1; | 304 | data->valid = 1; |
295 | } | 305 | } |
diff --git a/drivers/hwmon/lm85.c b/drivers/hwmon/lm85.c index 182fe6a5605f..ee5eca1c1921 100644 --- a/drivers/hwmon/lm85.c +++ b/drivers/hwmon/lm85.c | |||
@@ -192,23 +192,20 @@ static int RANGE_TO_REG( int range ) | |||
192 | { | 192 | { |
193 | int i; | 193 | int i; |
194 | 194 | ||
195 | if ( range < lm85_range_map[0] ) { | 195 | if (range >= lm85_range_map[15]) |
196 | return 0 ; | ||
197 | } else if ( range > lm85_range_map[15] ) { | ||
198 | return 15 ; | 196 | return 15 ; |
199 | } else { /* find closest match */ | 197 | |
200 | for ( i = 14 ; i >= 0 ; --i ) { | 198 | /* Find the closest match */ |
201 | if ( range > lm85_range_map[i] ) { /* range bracketed */ | 199 | for (i = 14; i >= 0; --i) { |
202 | if ((lm85_range_map[i+1] - range) < | 200 | if (range >= lm85_range_map[i]) { |
203 | (range - lm85_range_map[i])) { | 201 | if ((lm85_range_map[i + 1] - range) < |
204 | i++; | 202 | (range - lm85_range_map[i])) |
205 | break; | 203 | return i + 1; |
206 | } | 204 | return i; |
207 | break; | ||
208 | } | ||
209 | } | 205 | } |
210 | } | 206 | } |
211 | return( i & 0x0f ); | 207 | |
208 | return 0; | ||
212 | } | 209 | } |
213 | #define RANGE_FROM_REG(val) (lm85_range_map[(val)&0x0f]) | 210 | #define RANGE_FROM_REG(val) (lm85_range_map[(val)&0x0f]) |
214 | 211 | ||
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c index 1305ef190fc1..9e8c875437be 100644 --- a/drivers/i2c/busses/i2c-s3c2410.c +++ b/drivers/i2c/busses/i2c-s3c2410.c | |||
@@ -290,12 +290,12 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) | |||
290 | * bus, or started a new i2c message | 290 | * bus, or started a new i2c message |
291 | */ | 291 | */ |
292 | 292 | ||
293 | if (iicstat & S3C2410_IICSTAT_LASTBIT && | 293 | if (iicstat & S3C2410_IICSTAT_LASTBIT && |
294 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { | 294 | !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { |
295 | /* ack was not received... */ | 295 | /* ack was not received... */ |
296 | 296 | ||
297 | dev_dbg(i2c->dev, "ack was not received\n"); | 297 | dev_dbg(i2c->dev, "ack was not received\n"); |
298 | s3c24xx_i2c_stop(i2c, -EREMOTEIO); | 298 | s3c24xx_i2c_stop(i2c, -ENXIO); |
299 | goto out_ack; | 299 | goto out_ack; |
300 | } | 300 | } |
301 | 301 | ||
@@ -305,7 +305,7 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) | |||
305 | i2c->state = STATE_WRITE; | 305 | i2c->state = STATE_WRITE; |
306 | 306 | ||
307 | /* terminate the transfer if there is nothing to do | 307 | /* terminate the transfer if there is nothing to do |
308 | * (used by the i2c probe to find devices */ | 308 | * as this is used by the i2c probe to find devices. */ |
309 | 309 | ||
310 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { | 310 | if (is_lastmsg(i2c) && i2c->msg->len == 0) { |
311 | s3c24xx_i2c_stop(i2c, 0); | 311 | s3c24xx_i2c_stop(i2c, 0); |
@@ -323,7 +323,17 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) | |||
323 | * end of the message, and if so, work out what to do | 323 | * end of the message, and if so, work out what to do |
324 | */ | 324 | */ |
325 | 325 | ||
326 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { | ||
327 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | ||
328 | dev_dbg(i2c->dev, "WRITE: No Ack\n"); | ||
329 | |||
330 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | ||
331 | goto out_ack; | ||
332 | } | ||
333 | } | ||
334 | |||
326 | retry_write: | 335 | retry_write: |
336 | |||
327 | if (!is_msgend(i2c)) { | 337 | if (!is_msgend(i2c)) { |
328 | byte = i2c->msg->buf[i2c->msg_ptr++]; | 338 | byte = i2c->msg->buf[i2c->msg_ptr++]; |
329 | writeb(byte, i2c->regs + S3C2410_IICDS); | 339 | writeb(byte, i2c->regs + S3C2410_IICDS); |
@@ -377,17 +387,6 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) | |||
377 | * going to do any more read/write | 387 | * going to do any more read/write |
378 | */ | 388 | */ |
379 | 389 | ||
380 | if (!(i2c->msg->flags & I2C_M_IGNORE_NAK) && | ||
381 | !(is_msglast(i2c) && is_lastmsg(i2c))) { | ||
382 | |||
383 | if (iicstat & S3C2410_IICSTAT_LASTBIT) { | ||
384 | dev_dbg(i2c->dev, "READ: No Ack\n"); | ||
385 | |||
386 | s3c24xx_i2c_stop(i2c, -ECONNREFUSED); | ||
387 | goto out_ack; | ||
388 | } | ||
389 | } | ||
390 | |||
391 | byte = readb(i2c->regs + S3C2410_IICDS); | 390 | byte = readb(i2c->regs + S3C2410_IICDS); |
392 | i2c->msg->buf[i2c->msg_ptr++] = byte; | 391 | i2c->msg->buf[i2c->msg_ptr++] = byte; |
393 | 392 | ||
@@ -949,3 +948,4 @@ MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); | |||
949 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | 948 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); |
950 | MODULE_LICENSE("GPL"); | 949 | MODULE_LICENSE("GPL"); |
951 | MODULE_ALIAS("platform:s3c2410-i2c"); | 950 | MODULE_ALIAS("platform:s3c2410-i2c"); |
951 | MODULE_ALIAS("platform:s3c2440-i2c"); | ||
diff --git a/drivers/ide/arm/palm_bk3710.c b/drivers/ide/arm/palm_bk3710.c index d024ac8fad14..cc24803fadff 100644 --- a/drivers/ide/arm/palm_bk3710.c +++ b/drivers/ide/arm/palm_bk3710.c | |||
@@ -353,8 +353,8 @@ static int __devinit palm_bk3710_probe(struct platform_device *pdev) | |||
353 | struct clk *clkp; | 353 | struct clk *clkp; |
354 | struct resource *mem, *irq; | 354 | struct resource *mem, *irq; |
355 | ide_hwif_t *hwif; | 355 | ide_hwif_t *hwif; |
356 | void __iomem *base; | 356 | unsigned long base; |
357 | int pribase, i; | 357 | int i; |
358 | hw_regs_t hw; | 358 | hw_regs_t hw; |
359 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; | 359 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
360 | 360 | ||
@@ -374,22 +374,27 @@ static int __devinit palm_bk3710_probe(struct platform_device *pdev) | |||
374 | printk(KERN_ERR "failed to get memory region resource\n"); | 374 | printk(KERN_ERR "failed to get memory region resource\n"); |
375 | return -ENODEV; | 375 | return -ENODEV; |
376 | } | 376 | } |
377 | |||
377 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | 378 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
378 | if (irq == NULL) { | 379 | if (irq == NULL) { |
379 | printk(KERN_ERR "failed to get IRQ resource\n"); | 380 | printk(KERN_ERR "failed to get IRQ resource\n"); |
380 | return -ENODEV; | 381 | return -ENODEV; |
381 | } | 382 | } |
382 | 383 | ||
383 | base = (void *)mem->start; | 384 | if (request_mem_region(mem->start, mem->end - mem->start + 1, |
385 | "palm_bk3710") == NULL) { | ||
386 | printk(KERN_ERR "failed to request memory region\n"); | ||
387 | return -EBUSY; | ||
388 | } | ||
389 | |||
390 | base = IO_ADDRESS(mem->start); | ||
384 | 391 | ||
385 | /* Configure the Palm Chip controller */ | 392 | /* Configure the Palm Chip controller */ |
386 | palm_bk3710_chipinit(base); | 393 | palm_bk3710_chipinit((void __iomem *)base); |
387 | 394 | ||
388 | pribase = mem->start + IDE_PALM_ATA_PRI_REG_OFFSET; | ||
389 | for (i = 0; i < IDE_NR_PORTS - 2; i++) | 395 | for (i = 0; i < IDE_NR_PORTS - 2; i++) |
390 | hw.io_ports_array[i] = pribase + i; | 396 | hw.io_ports_array[i] = base + IDE_PALM_ATA_PRI_REG_OFFSET + i; |
391 | hw.io_ports.ctl_addr = mem->start + | 397 | hw.io_ports.ctl_addr = base + IDE_PALM_ATA_PRI_CTL_OFFSET; |
392 | IDE_PALM_ATA_PRI_CTL_OFFSET; | ||
393 | hw.irq = irq->start; | 398 | hw.irq = irq->start; |
394 | hw.chipset = ide_palm3710; | 399 | hw.chipset = ide_palm3710; |
395 | 400 | ||
@@ -434,4 +439,3 @@ static int __init palm_bk3710_init(void) | |||
434 | 439 | ||
435 | module_init(palm_bk3710_init); | 440 | module_init(palm_bk3710_init); |
436 | MODULE_LICENSE("GPL"); | 441 | MODULE_LICENSE("GPL"); |
437 | |||
diff --git a/drivers/ide/ide-generic.c b/drivers/ide/ide-generic.c index 9134488ac043..2d92214096ab 100644 --- a/drivers/ide/ide-generic.c +++ b/drivers/ide/ide-generic.c | |||
@@ -22,6 +22,10 @@ | |||
22 | 22 | ||
23 | #define DRV_NAME "ide_generic" | 23 | #define DRV_NAME "ide_generic" |
24 | 24 | ||
25 | static int probe_mask = 0x03; | ||
26 | module_param(probe_mask, int, 0); | ||
27 | MODULE_PARM_DESC(probe_mask, "probe mask for legacy ISA IDE ports"); | ||
28 | |||
25 | static ssize_t store_add(struct class *cls, const char *buf, size_t n) | 29 | static ssize_t store_add(struct class *cls, const char *buf, size_t n) |
26 | { | 30 | { |
27 | ide_hwif_t *hwif; | 31 | ide_hwif_t *hwif; |
@@ -89,6 +93,9 @@ static int __init ide_generic_init(void) | |||
89 | u8 idx[MAX_HWIFS]; | 93 | u8 idx[MAX_HWIFS]; |
90 | int i; | 94 | int i; |
91 | 95 | ||
96 | printk(KERN_INFO DRV_NAME ": please use \"probe_mask=0x3f\" module " | ||
97 | "parameter for probing all legacy ISA IDE ports\n"); | ||
98 | |||
92 | for (i = 0; i < MAX_HWIFS; i++) { | 99 | for (i = 0; i < MAX_HWIFS; i++) { |
93 | ide_hwif_t *hwif; | 100 | ide_hwif_t *hwif; |
94 | unsigned long io_addr = ide_default_io_base(i); | 101 | unsigned long io_addr = ide_default_io_base(i); |
@@ -96,7 +103,7 @@ static int __init ide_generic_init(void) | |||
96 | 103 | ||
97 | idx[i] = 0xff; | 104 | idx[i] = 0xff; |
98 | 105 | ||
99 | if (io_addr) { | 106 | if ((probe_mask & (1 << i)) && io_addr) { |
100 | if (!request_region(io_addr, 8, DRV_NAME)) { | 107 | if (!request_region(io_addr, 8, DRV_NAME)) { |
101 | printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX " | 108 | printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX " |
102 | "not free.\n", | 109 | "not free.\n", |
diff --git a/drivers/ide/ide-proc.c b/drivers/ide/ide-proc.c index 55ec7f798772..8af88bf0969b 100644 --- a/drivers/ide/ide-proc.c +++ b/drivers/ide/ide-proc.c | |||
@@ -76,7 +76,7 @@ static int proc_ide_read_mate | |||
76 | ide_hwif_t *hwif = (ide_hwif_t *) data; | 76 | ide_hwif_t *hwif = (ide_hwif_t *) data; |
77 | int len; | 77 | int len; |
78 | 78 | ||
79 | if (hwif && hwif->mate && hwif->mate->present) | 79 | if (hwif && hwif->mate) |
80 | len = sprintf(page, "%s\n", hwif->mate->name); | 80 | len = sprintf(page, "%s\n", hwif->mate->name); |
81 | else | 81 | else |
82 | len = sprintf(page, "(none)\n"); | 82 | len = sprintf(page, "(none)\n"); |
diff --git a/drivers/ide/ide-taskfile.c b/drivers/ide/ide-taskfile.c index 0c908ca3ff79..ab545ffa1549 100644 --- a/drivers/ide/ide-taskfile.c +++ b/drivers/ide/ide-taskfile.c | |||
@@ -225,10 +225,10 @@ static u8 wait_drive_not_busy(ide_drive_t *drive) | |||
225 | u8 stat; | 225 | u8 stat; |
226 | 226 | ||
227 | /* | 227 | /* |
228 | * Last sector was transfered, wait until drive is ready. | 228 | * Last sector was transfered, wait until device is ready. This can |
229 | * This can take up to 10 usec, but we will wait max 1 ms. | 229 | * take up to 6 ms on some ATAPI devices, so we will wait max 10 ms. |
230 | */ | 230 | */ |
231 | for (retries = 0; retries < 100; retries++) { | 231 | for (retries = 0; retries < 1000; retries++) { |
232 | stat = ide_read_status(drive); | 232 | stat = ide_read_status(drive); |
233 | 233 | ||
234 | if (stat & BUSY_STAT) | 234 | if (stat & BUSY_STAT) |
diff --git a/drivers/ide/legacy/ide-cs.c b/drivers/ide/legacy/ide-cs.c index aa2ea3deac85..3381424d70a1 100644 --- a/drivers/ide/legacy/ide-cs.c +++ b/drivers/ide/legacy/ide-cs.c | |||
@@ -135,13 +135,17 @@ static void ide_detach(struct pcmcia_device *link) | |||
135 | { | 135 | { |
136 | ide_info_t *info = link->priv; | 136 | ide_info_t *info = link->priv; |
137 | ide_hwif_t *hwif = info->hwif; | 137 | ide_hwif_t *hwif = info->hwif; |
138 | unsigned long data_addr, ctl_addr; | ||
138 | 139 | ||
139 | DEBUG(0, "ide_detach(0x%p)\n", link); | 140 | DEBUG(0, "ide_detach(0x%p)\n", link); |
140 | 141 | ||
142 | data_addr = hwif->io_ports.data_addr; | ||
143 | ctl_addr = hwif->io_ports.ctl_addr; | ||
144 | |||
141 | ide_release(link); | 145 | ide_release(link); |
142 | 146 | ||
143 | release_region(hwif->io_ports.ctl_addr, 1); | 147 | release_region(ctl_addr, 1); |
144 | release_region(hwif->io_ports.data_addr, 8); | 148 | release_region(data_addr, 8); |
145 | 149 | ||
146 | kfree(info); | 150 | kfree(info); |
147 | } /* ide_detach */ | 151 | } /* ide_detach */ |
@@ -194,6 +198,16 @@ static ide_hwif_t *idecs_register(unsigned long io, unsigned long ctl, | |||
194 | if (hwif->present) | 198 | if (hwif->present) |
195 | return hwif; | 199 | return hwif; |
196 | 200 | ||
201 | /* retry registration in case device is still spinning up */ | ||
202 | for (i = 0; i < 10; i++) { | ||
203 | msleep(100); | ||
204 | ide_port_scan(hwif); | ||
205 | if (hwif->present) | ||
206 | return hwif; | ||
207 | } | ||
208 | |||
209 | return hwif; | ||
210 | |||
197 | out_release: | 211 | out_release: |
198 | release_region(ctl, 1); | 212 | release_region(ctl, 1); |
199 | release_region(io, 8); | 213 | release_region(io, 8); |
@@ -222,7 +236,7 @@ static int ide_config(struct pcmcia_device *link) | |||
222 | cistpl_cftable_entry_t dflt; | 236 | cistpl_cftable_entry_t dflt; |
223 | } *stk = NULL; | 237 | } *stk = NULL; |
224 | cistpl_cftable_entry_t *cfg; | 238 | cistpl_cftable_entry_t *cfg; |
225 | int i, pass, last_ret = 0, last_fn = 0, is_kme = 0; | 239 | int pass, last_ret = 0, last_fn = 0, is_kme = 0; |
226 | unsigned long io_base, ctl_base; | 240 | unsigned long io_base, ctl_base; |
227 | ide_hwif_t *hwif; | 241 | ide_hwif_t *hwif; |
228 | 242 | ||
@@ -319,30 +333,15 @@ static int ide_config(struct pcmcia_device *link) | |||
319 | if (is_kme) | 333 | if (is_kme) |
320 | outb(0x81, ctl_base+1); | 334 | outb(0x81, ctl_base+1); |
321 | 335 | ||
322 | /* retry registration in case device is still spinning up */ | 336 | hwif = idecs_register(io_base, ctl_base, link->irq.AssignedIRQ, link); |
323 | for (i = 0; i < 10; i++) { | 337 | if (hwif == NULL && link->io.NumPorts1 == 0x20) { |
324 | hwif = idecs_register(io_base, ctl_base, link->irq.AssignedIRQ, link); | ||
325 | if (hwif) | ||
326 | break; | ||
327 | if (link->io.NumPorts1 == 0x20) { | ||
328 | outb(0x02, ctl_base + 0x10); | 338 | outb(0x02, ctl_base + 0x10); |
329 | hwif = idecs_register(io_base + 0x10, ctl_base + 0x10, | 339 | hwif = idecs_register(io_base + 0x10, ctl_base + 0x10, |
330 | link->irq.AssignedIRQ, link); | 340 | link->irq.AssignedIRQ, link); |
331 | if (hwif) { | ||
332 | io_base += 0x10; | ||
333 | ctl_base += 0x10; | ||
334 | break; | ||
335 | } | ||
336 | } | ||
337 | msleep(100); | ||
338 | } | 341 | } |
339 | 342 | ||
340 | if (hwif == NULL) { | 343 | if (hwif == NULL) |
341 | printk(KERN_NOTICE "ide-cs: ide_register() at 0x%3lx & 0x%3lx" | ||
342 | ", irq %u failed\n", io_base, ctl_base, | ||
343 | link->irq.AssignedIRQ); | ||
344 | goto failed; | 344 | goto failed; |
345 | } | ||
346 | 345 | ||
347 | info->ndev = 1; | 346 | info->ndev = 1; |
348 | sprintf(info->node.dev_name, "hd%c", 'a' + hwif->index * 2); | 347 | sprintf(info->node.dev_name, "hd%c", 'a' + hwif->index * 2); |
@@ -411,6 +410,7 @@ static struct pcmcia_device_id ide_ids[] = { | |||
411 | PCMCIA_DEVICE_MANF_CARD(0x001c, 0x0001), /* Mitsubishi CFA */ | 410 | PCMCIA_DEVICE_MANF_CARD(0x001c, 0x0001), /* Mitsubishi CFA */ |
412 | PCMCIA_DEVICE_MANF_CARD(0x0032, 0x0704), | 411 | PCMCIA_DEVICE_MANF_CARD(0x0032, 0x0704), |
413 | PCMCIA_DEVICE_MANF_CARD(0x0045, 0x0401), /* SanDisk CFA */ | 412 | PCMCIA_DEVICE_MANF_CARD(0x0045, 0x0401), /* SanDisk CFA */ |
413 | PCMCIA_DEVICE_MANF_CARD(0x004f, 0x0000), /* Kingston */ | ||
414 | PCMCIA_DEVICE_MANF_CARD(0x0098, 0x0000), /* Toshiba */ | 414 | PCMCIA_DEVICE_MANF_CARD(0x0098, 0x0000), /* Toshiba */ |
415 | PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x002d), | 415 | PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x002d), |
416 | PCMCIA_DEVICE_MANF_CARD(0x00ce, 0x0000), /* Samsung */ | 416 | PCMCIA_DEVICE_MANF_CARD(0x00ce, 0x0000), /* Samsung */ |
@@ -440,6 +440,7 @@ static struct pcmcia_device_id ide_ids[] = { | |||
440 | PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149), | 440 | PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDE", 0x547e66dc, 0x5c5ab149), |
441 | PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674), | 441 | PCMCIA_DEVICE_PROD_ID12("IO DATA", "PCIDEII", 0x547e66dc, 0xb3662674), |
442 | PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b), | 442 | PCMCIA_DEVICE_PROD_ID12("LOOKMEET", "CBIDE2 ", 0xe37be2b5, 0x8671043b), |
443 | PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF300", 0x7ed2ad87, 0x7e9e78ee), | ||
443 | PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c), | 444 | PCMCIA_DEVICE_PROD_ID12("M-Systems", "CF500", 0x7ed2ad87, 0x7a13045c), |
444 | PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79), | 445 | PCMCIA_DEVICE_PROD_ID2("NinjaATA-", 0xebe0bd79), |
445 | PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591), | 446 | PCMCIA_DEVICE_PROD_ID12("PCMCIA", "CD-ROM", 0x281f1c5d, 0x66536591), |
@@ -450,6 +451,7 @@ static struct pcmcia_device_id ide_ids[] = { | |||
450 | PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6), | 451 | PCMCIA_DEVICE_PROD_ID12("SMI VENDOR", "SMI PRODUCT", 0x30896c92, 0x703cc5f6), |
451 | PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003), | 452 | PCMCIA_DEVICE_PROD_ID12("TOSHIBA", "MK2001MPL", 0xb4585a1a, 0x3489e003), |
452 | PCMCIA_DEVICE_PROD_ID1("TRANSCEND 512M ", 0xd0909443), | 453 | PCMCIA_DEVICE_PROD_ID1("TRANSCEND 512M ", 0xd0909443), |
454 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF45", 0x709b1bf1, 0xf68b6f32), | ||
453 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1), | 455 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS1GCF80", 0x709b1bf1, 0x2a54d4b1), |
454 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2), | 456 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS2GCF120", 0x709b1bf1, 0x969aa4f2), |
455 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8), | 457 | PCMCIA_DEVICE_PROD_ID12("TRANSCEND", "TS4GCF120", 0x709b1bf1, 0xf54a91c8), |
diff --git a/drivers/ide/pci/opti621.c b/drivers/ide/pci/opti621.c index 6e99080497bf..725c80508d90 100644 --- a/drivers/ide/pci/opti621.c +++ b/drivers/ide/pci/opti621.c | |||
@@ -81,8 +81,6 @@ | |||
81 | * 0.5 doesn't work. | 81 | * 0.5 doesn't work. |
82 | */ | 82 | */ |
83 | 83 | ||
84 | #define OPTI621_DEBUG /* define for debug messages */ | ||
85 | |||
86 | #include <linux/types.h> | 84 | #include <linux/types.h> |
87 | #include <linux/module.h> | 85 | #include <linux/module.h> |
88 | #include <linux/kernel.h> | 86 | #include <linux/kernel.h> |
@@ -92,28 +90,6 @@ | |||
92 | 90 | ||
93 | #include <asm/io.h> | 91 | #include <asm/io.h> |
94 | 92 | ||
95 | //#define OPTI621_MAX_PIO 3 | ||
96 | /* In fact, I do not have any PIO 4 drive | ||
97 | * (address: 25 ns, data: 70 ns, recovery: 35 ns), | ||
98 | * but OPTi 82C621 is programmable and it can do (minimal values): | ||
99 | * on 40MHz PCI bus (pulse 25 ns): | ||
100 | * address: 25 ns, data: 25 ns, recovery: 50 ns; | ||
101 | * on 20MHz PCI bus (pulse 50 ns): | ||
102 | * address: 50 ns, data: 50 ns, recovery: 100 ns. | ||
103 | */ | ||
104 | |||
105 | /* #define READ_PREFETCH 0 */ | ||
106 | /* Uncomment for disable read prefetch. | ||
107 | * There is some readprefetch capatibility in hdparm, | ||
108 | * but when I type hdparm -P 1 /dev/hda, I got errors | ||
109 | * and till reset drive is inaccessible. | ||
110 | * This (hw) read prefetch is safe on my drive. | ||
111 | */ | ||
112 | |||
113 | #ifndef READ_PREFETCH | ||
114 | #define READ_PREFETCH 0x40 /* read prefetch is enabled */ | ||
115 | #endif /* else read prefetch is disabled */ | ||
116 | |||
117 | #define READ_REG 0 /* index of Read cycle timing register */ | 93 | #define READ_REG 0 /* index of Read cycle timing register */ |
118 | #define WRITE_REG 1 /* index of Write cycle timing register */ | 94 | #define WRITE_REG 1 /* index of Write cycle timing register */ |
119 | #define CNTRL_REG 3 /* index of Control register */ | 95 | #define CNTRL_REG 3 /* index of Control register */ |
@@ -122,51 +98,8 @@ | |||
122 | 98 | ||
123 | static int reg_base; | 99 | static int reg_base; |
124 | 100 | ||
125 | #define PIO_NOT_EXIST 254 | ||
126 | #define PIO_DONT_KNOW 255 | ||
127 | |||
128 | static DEFINE_SPINLOCK(opti621_lock); | 101 | static DEFINE_SPINLOCK(opti621_lock); |
129 | 102 | ||
130 | /* there are stored pio numbers from other calls of opti621_set_pio_mode */ | ||
131 | static void compute_pios(ide_drive_t *drive, const u8 pio) | ||
132 | /* Store values into drive->drive_data | ||
133 | * second_contr - 0 for primary controller, 1 for secondary | ||
134 | * slave_drive - 0 -> pio is for master, 1 -> pio is for slave | ||
135 | * pio - PIO mode for selected drive (for other we don't know) | ||
136 | */ | ||
137 | { | ||
138 | int d; | ||
139 | ide_hwif_t *hwif = HWIF(drive); | ||
140 | |||
141 | drive->drive_data = pio; | ||
142 | |||
143 | for (d = 0; d < 2; ++d) { | ||
144 | drive = &hwif->drives[d]; | ||
145 | if (drive->present) { | ||
146 | if (drive->drive_data == PIO_DONT_KNOW) | ||
147 | drive->drive_data = ide_get_best_pio_mode(drive, 255, 3); | ||
148 | #ifdef OPTI621_DEBUG | ||
149 | printk("%s: Selected PIO mode %d\n", | ||
150 | drive->name, drive->drive_data); | ||
151 | #endif | ||
152 | } else { | ||
153 | drive->drive_data = PIO_NOT_EXIST; | ||
154 | } | ||
155 | } | ||
156 | } | ||
157 | |||
158 | static int cmpt_clk(int time, int bus_speed) | ||
159 | /* Returns (rounded up) time in clocks for time in ns, | ||
160 | * with bus_speed in MHz. | ||
161 | * Example: bus_speed = 40 MHz, time = 80 ns | ||
162 | * 1000/40 = 25 ns (clk value), | ||
163 | * 80/25 = 3.2, rounded up to 4 (I hope ;-)). | ||
164 | * Use idebus=xx to select right frequency. | ||
165 | */ | ||
166 | { | ||
167 | return ((time*bus_speed+999)/1000); | ||
168 | } | ||
169 | |||
170 | /* Write value to register reg, base of register | 103 | /* Write value to register reg, base of register |
171 | * is at reg_base (0x1f0 primary, 0x170 secondary, | 104 | * is at reg_base (0x1f0 primary, 0x170 secondary, |
172 | * if not changed by PCI configuration). | 105 | * if not changed by PCI configuration). |
@@ -199,83 +132,29 @@ static u8 read_reg(int reg) | |||
199 | return ret; | 132 | return ret; |
200 | } | 133 | } |
201 | 134 | ||
202 | typedef struct pio_clocks_s { | ||
203 | int address_time; /* Address setup (clocks) */ | ||
204 | int data_time; /* Active/data pulse (clocks) */ | ||
205 | int recovery_time; /* Recovery time (clocks) */ | ||
206 | } pio_clocks_t; | ||
207 | |||
208 | static void compute_clocks(int pio, pio_clocks_t *clks) | ||
209 | { | ||
210 | if (pio != PIO_NOT_EXIST) { | ||
211 | int adr_setup, data_pls; | ||
212 | int bus_speed = ide_pci_clk ? ide_pci_clk : system_bus_clock(); | ||
213 | |||
214 | adr_setup = ide_pio_timings[pio].setup_time; | ||
215 | data_pls = ide_pio_timings[pio].active_time; | ||
216 | clks->address_time = cmpt_clk(adr_setup, bus_speed); | ||
217 | clks->data_time = cmpt_clk(data_pls, bus_speed); | ||
218 | clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time | ||
219 | - adr_setup-data_pls, bus_speed); | ||
220 | if (clks->address_time < 1) | ||
221 | clks->address_time = 1; | ||
222 | if (clks->address_time > 4) | ||
223 | clks->address_time = 4; | ||
224 | if (clks->data_time < 1) | ||
225 | clks->data_time = 1; | ||
226 | if (clks->data_time > 16) | ||
227 | clks->data_time = 16; | ||
228 | if (clks->recovery_time < 2) | ||
229 | clks->recovery_time = 2; | ||
230 | if (clks->recovery_time > 17) | ||
231 | clks->recovery_time = 17; | ||
232 | } else { | ||
233 | clks->address_time = 1; | ||
234 | clks->data_time = 1; | ||
235 | clks->recovery_time = 2; | ||
236 | /* minimal values */ | ||
237 | } | ||
238 | } | ||
239 | |||
240 | static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio) | 135 | static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio) |
241 | { | 136 | { |
242 | /* primary and secondary drives share some registers, | 137 | ide_hwif_t *hwif = drive->hwif; |
243 | * so we have to program both drives | 138 | ide_drive_t *pair = ide_get_paired_drive(drive); |
244 | */ | ||
245 | unsigned long flags; | 139 | unsigned long flags; |
246 | u8 pio1 = 0, pio2 = 0; | 140 | u8 tim, misc, addr_pio = pio, clk; |
247 | pio_clocks_t first, second; | 141 | |
248 | int ax, drdy; | 142 | /* DRDY is default 2 (by OPTi Databook) */ |
249 | u8 cycle1, cycle2, misc; | 143 | static const u8 addr_timings[2][5] = { |
250 | ide_hwif_t *hwif = HWIF(drive); | 144 | { 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */ |
251 | 145 | { 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */ | |
252 | /* sets drive->drive_data for both drives */ | 146 | }; |
253 | compute_pios(drive, pio); | 147 | static const u8 data_rec_timings[2][5] = { |
254 | pio1 = hwif->drives[0].drive_data; | 148 | { 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */ |
255 | pio2 = hwif->drives[1].drive_data; | 149 | { 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */ |
256 | 150 | }; | |
257 | compute_clocks(pio1, &first); | 151 | |
258 | compute_clocks(pio2, &second); | 152 | drive->drive_data = XFER_PIO_0 + pio; |
259 | 153 | ||
260 | /* ax = max(a1,a2) */ | 154 | if (pair->present) { |
261 | ax = (first.address_time < second.address_time) ? second.address_time : first.address_time; | 155 | if (pair->drive_data && pair->drive_data < drive->drive_data) |
262 | 156 | addr_pio = pair->drive_data - XFER_PIO_0; | |
263 | drdy = 2; /* DRDY is default 2 (by OPTi Databook) */ | 157 | } |
264 | |||
265 | cycle1 = ((first.data_time-1)<<4) | (first.recovery_time-2); | ||
266 | cycle2 = ((second.data_time-1)<<4) | (second.recovery_time-2); | ||
267 | misc = READ_PREFETCH | ((ax-1)<<4) | ((drdy-2)<<1); | ||
268 | |||
269 | #ifdef OPTI621_DEBUG | ||
270 | printk("%s: master: address: %d, data: %d, " | ||
271 | "recovery: %d, drdy: %d [clk]\n", | ||
272 | hwif->name, ax, first.data_time, | ||
273 | first.recovery_time, drdy); | ||
274 | printk("%s: slave: address: %d, data: %d, " | ||
275 | "recovery: %d, drdy: %d [clk]\n", | ||
276 | hwif->name, ax, second.data_time, | ||
277 | second.recovery_time, drdy); | ||
278 | #endif | ||
279 | 158 | ||
280 | spin_lock_irqsave(&opti621_lock, flags); | 159 | spin_lock_irqsave(&opti621_lock, flags); |
281 | 160 | ||
@@ -289,24 +168,21 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio) | |||
289 | (void)inb(reg_base + CNTRL_REG); | 168 | (void)inb(reg_base + CNTRL_REG); |
290 | /* if reads 0xc0, no interface exist? */ | 169 | /* if reads 0xc0, no interface exist? */ |
291 | read_reg(CNTRL_REG); | 170 | read_reg(CNTRL_REG); |
292 | /* read version, probably 0 */ | ||
293 | read_reg(STRAP_REG); | ||
294 | 171 | ||
295 | /* program primary drive */ | 172 | /* check CLK speed */ |
296 | /* select Index-0 for Register-A */ | 173 | clk = read_reg(STRAP_REG) & 1; |
297 | write_reg(0, MISC_REG); | 174 | |
298 | /* set read cycle timings */ | 175 | printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33); |
299 | write_reg(cycle1, READ_REG); | ||
300 | /* set write cycle timings */ | ||
301 | write_reg(cycle1, WRITE_REG); | ||
302 | 176 | ||
303 | /* program secondary drive */ | 177 | tim = data_rec_timings[clk][pio]; |
304 | /* select Index-1 for Register-B */ | 178 | misc = addr_timings[clk][addr_pio]; |
305 | write_reg(1, MISC_REG); | 179 | |
180 | /* select Index-0/1 for Register-A/B */ | ||
181 | write_reg(drive->select.b.unit, MISC_REG); | ||
306 | /* set read cycle timings */ | 182 | /* set read cycle timings */ |
307 | write_reg(cycle2, READ_REG); | 183 | write_reg(tim, READ_REG); |
308 | /* set write cycle timings */ | 184 | /* set write cycle timings */ |
309 | write_reg(cycle2, WRITE_REG); | 185 | write_reg(tim, WRITE_REG); |
310 | 186 | ||
311 | /* use Register-A for drive 0 */ | 187 | /* use Register-A for drive 0 */ |
312 | /* use Register-B for drive 1 */ | 188 | /* use Register-B for drive 1 */ |
@@ -319,45 +195,26 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio) | |||
319 | spin_unlock_irqrestore(&opti621_lock, flags); | 195 | spin_unlock_irqrestore(&opti621_lock, flags); |
320 | } | 196 | } |
321 | 197 | ||
322 | static void __devinit opti621_port_init_devs(ide_hwif_t *hwif) | ||
323 | { | ||
324 | hwif->drives[0].drive_data = PIO_DONT_KNOW; | ||
325 | hwif->drives[1].drive_data = PIO_DONT_KNOW; | ||
326 | } | ||
327 | |||
328 | static const struct ide_port_ops opti621_port_ops = { | 198 | static const struct ide_port_ops opti621_port_ops = { |
329 | .port_init_devs = opti621_port_init_devs, | ||
330 | .set_pio_mode = opti621_set_pio_mode, | 199 | .set_pio_mode = opti621_set_pio_mode, |
331 | }; | 200 | }; |
332 | 201 | ||
333 | static const struct ide_port_info opti621_chipsets[] __devinitdata = { | 202 | static const struct ide_port_info opti621_chipset __devinitdata = { |
334 | { /* 0 */ | 203 | .name = "OPTI621/X", |
335 | .name = "OPTI621", | 204 | .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} }, |
336 | .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} }, | 205 | .port_ops = &opti621_port_ops, |
337 | .port_ops = &opti621_port_ops, | 206 | .host_flags = IDE_HFLAG_NO_DMA, |
338 | .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, | 207 | .pio_mask = ATA_PIO4, |
339 | .pio_mask = ATA_PIO3, | ||
340 | .swdma_mask = ATA_SWDMA2, | ||
341 | .mwdma_mask = ATA_MWDMA2, | ||
342 | }, { /* 1 */ | ||
343 | .name = "OPTI621X", | ||
344 | .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} }, | ||
345 | .port_ops = &opti621_port_ops, | ||
346 | .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA, | ||
347 | .pio_mask = ATA_PIO3, | ||
348 | .swdma_mask = ATA_SWDMA2, | ||
349 | .mwdma_mask = ATA_MWDMA2, | ||
350 | } | ||
351 | }; | 208 | }; |
352 | 209 | ||
353 | static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id) | 210 | static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
354 | { | 211 | { |
355 | return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]); | 212 | return ide_setup_pci_device(dev, &opti621_chipset); |
356 | } | 213 | } |
357 | 214 | ||
358 | static const struct pci_device_id opti621_pci_tbl[] = { | 215 | static const struct pci_device_id opti621_pci_tbl[] = { |
359 | { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 }, | 216 | { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 }, |
360 | { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 1 }, | 217 | { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 }, |
361 | { 0, }, | 218 | { 0, }, |
362 | }; | 219 | }; |
363 | MODULE_DEVICE_TABLE(pci, opti621_pci_tbl); | 220 | MODULE_DEVICE_TABLE(pci, opti621_pci_tbl); |
diff --git a/drivers/ide/ppc/pmac.c b/drivers/ide/ppc/pmac.c index 48aa019127bc..ba2d58727964 100644 --- a/drivers/ide/ppc/pmac.c +++ b/drivers/ide/ppc/pmac.c | |||
@@ -59,7 +59,6 @@ typedef struct pmac_ide_hwif { | |||
59 | int irq; | 59 | int irq; |
60 | int kind; | 60 | int kind; |
61 | int aapl_bus_id; | 61 | int aapl_bus_id; |
62 | unsigned cable_80 : 1; | ||
63 | unsigned mediabay : 1; | 62 | unsigned mediabay : 1; |
64 | unsigned broken_dma : 1; | 63 | unsigned broken_dma : 1; |
65 | unsigned broken_dma_warn : 1; | 64 | unsigned broken_dma_warn : 1; |
@@ -918,10 +917,40 @@ pmac_ide_do_resume(ide_hwif_t *hwif) | |||
918 | return 0; | 917 | return 0; |
919 | } | 918 | } |
920 | 919 | ||
920 | static u8 pmac_ide_cable_detect(ide_hwif_t *hwif) | ||
921 | { | ||
922 | pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)ide_get_hwifdata(hwif); | ||
923 | struct device_node *np = pmif->node; | ||
924 | const char *cable = of_get_property(np, "cable-type", NULL); | ||
925 | |||
926 | /* Get cable type from device-tree. */ | ||
927 | if (cable && !strncmp(cable, "80-", 3)) | ||
928 | return ATA_CBL_PATA80; | ||
929 | |||
930 | /* | ||
931 | * G5's seem to have incorrect cable type in device-tree. | ||
932 | * Let's assume they have a 80 conductor cable, this seem | ||
933 | * to be always the case unless the user mucked around. | ||
934 | */ | ||
935 | if (of_device_is_compatible(np, "K2-UATA") || | ||
936 | of_device_is_compatible(np, "shasta-ata")) | ||
937 | return ATA_CBL_PATA80; | ||
938 | |||
939 | return ATA_CBL_PATA40; | ||
940 | } | ||
941 | |||
921 | static const struct ide_port_ops pmac_ide_ata6_port_ops = { | 942 | static const struct ide_port_ops pmac_ide_ata6_port_ops = { |
922 | .set_pio_mode = pmac_ide_set_pio_mode, | 943 | .set_pio_mode = pmac_ide_set_pio_mode, |
923 | .set_dma_mode = pmac_ide_set_dma_mode, | 944 | .set_dma_mode = pmac_ide_set_dma_mode, |
924 | .selectproc = pmac_ide_kauai_selectproc, | 945 | .selectproc = pmac_ide_kauai_selectproc, |
946 | .cable_detect = pmac_ide_cable_detect, | ||
947 | }; | ||
948 | |||
949 | static const struct ide_port_ops pmac_ide_ata4_port_ops = { | ||
950 | .set_pio_mode = pmac_ide_set_pio_mode, | ||
951 | .set_dma_mode = pmac_ide_set_dma_mode, | ||
952 | .selectproc = pmac_ide_selectproc, | ||
953 | .cable_detect = pmac_ide_cable_detect, | ||
925 | }; | 954 | }; |
926 | 955 | ||
927 | static const struct ide_port_ops pmac_ide_port_ops = { | 956 | static const struct ide_port_ops pmac_ide_port_ops = { |
@@ -949,10 +978,7 @@ static const struct ide_port_info pmac_port_info = { | |||
949 | 978 | ||
950 | /* | 979 | /* |
951 | * Setup, register & probe an IDE channel driven by this driver, this is | 980 | * Setup, register & probe an IDE channel driven by this driver, this is |
952 | * called by one of the 2 probe functions (macio or PCI). Note that a channel | 981 | * called by one of the 2 probe functions (macio or PCI). |
953 | * that ends up beeing free of any device is not kept around by this driver | ||
954 | * (it is kept in 2.4). This introduce an interface numbering change on some | ||
955 | * rare machines unfortunately, but it's better this way. | ||
956 | */ | 982 | */ |
957 | static int __devinit | 983 | static int __devinit |
958 | pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw) | 984 | pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw) |
@@ -962,7 +988,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw) | |||
962 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; | 988 | u8 idx[4] = { 0xff, 0xff, 0xff, 0xff }; |
963 | struct ide_port_info d = pmac_port_info; | 989 | struct ide_port_info d = pmac_port_info; |
964 | 990 | ||
965 | pmif->cable_80 = 0; | ||
966 | pmif->broken_dma = pmif->broken_dma_warn = 0; | 991 | pmif->broken_dma = pmif->broken_dma_warn = 0; |
967 | if (of_device_is_compatible(np, "shasta-ata")) { | 992 | if (of_device_is_compatible(np, "shasta-ata")) { |
968 | pmif->kind = controller_sh_ata6; | 993 | pmif->kind = controller_sh_ata6; |
@@ -979,6 +1004,7 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw) | |||
979 | } else if (of_device_is_compatible(np, "keylargo-ata")) { | 1004 | } else if (of_device_is_compatible(np, "keylargo-ata")) { |
980 | if (strcmp(np->name, "ata-4") == 0) { | 1005 | if (strcmp(np->name, "ata-4") == 0) { |
981 | pmif->kind = controller_kl_ata4; | 1006 | pmif->kind = controller_kl_ata4; |
1007 | d.port_ops = &pmac_ide_ata4_port_ops; | ||
982 | d.udma_mask = ATA_UDMA4; | 1008 | d.udma_mask = ATA_UDMA4; |
983 | } else | 1009 | } else |
984 | pmif->kind = controller_kl_ata3; | 1010 | pmif->kind = controller_kl_ata3; |
@@ -992,22 +1018,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw) | |||
992 | bidp = of_get_property(np, "AAPL,bus-id", NULL); | 1018 | bidp = of_get_property(np, "AAPL,bus-id", NULL); |
993 | pmif->aapl_bus_id = bidp ? *bidp : 0; | 1019 | pmif->aapl_bus_id = bidp ? *bidp : 0; |
994 | 1020 | ||
995 | /* Get cable type from device-tree */ | ||
996 | if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6 | ||
997 | || pmif->kind == controller_k2_ata6 | ||
998 | || pmif->kind == controller_sh_ata6) { | ||
999 | const char* cable = of_get_property(np, "cable-type", NULL); | ||
1000 | if (cable && !strncmp(cable, "80-", 3)) | ||
1001 | pmif->cable_80 = 1; | ||
1002 | } | ||
1003 | /* G5's seem to have incorrect cable type in device-tree. Let's assume | ||
1004 | * they have a 80 conductor cable, this seem to be always the case unless | ||
1005 | * the user mucked around | ||
1006 | */ | ||
1007 | if (of_device_is_compatible(np, "K2-UATA") || | ||
1008 | of_device_is_compatible(np, "shasta-ata")) | ||
1009 | pmif->cable_80 = 1; | ||
1010 | |||
1011 | /* On Kauai-type controllers, we make sure the FCR is correct */ | 1021 | /* On Kauai-type controllers, we make sure the FCR is correct */ |
1012 | if (pmif->kauai_fcr) | 1022 | if (pmif->kauai_fcr) |
1013 | writel(KAUAI_FCR_UATA_MAGIC | | 1023 | writel(KAUAI_FCR_UATA_MAGIC | |
@@ -1053,7 +1063,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw) | |||
1053 | 1063 | ||
1054 | hwif->hwif_data = pmif; | 1064 | hwif->hwif_data = pmif; |
1055 | ide_init_port_hw(hwif, hw); | 1065 | ide_init_port_hw(hwif, hw); |
1056 | hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40; | ||
1057 | 1066 | ||
1058 | printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n", | 1067 | printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n", |
1059 | hwif->index, model_name[pmif->kind], pmif->aapl_bus_id, | 1068 | hwif->index, model_name[pmif->kind], pmif->aapl_bus_id, |
@@ -1070,11 +1079,6 @@ pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif, hw_regs_t *hw) | |||
1070 | } | 1079 | } |
1071 | } | 1080 | } |
1072 | 1081 | ||
1073 | #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC | ||
1074 | if (pmif->cable_80 == 0) | ||
1075 | d.udma_mask &= ATA_UDMA2; | ||
1076 | #endif | ||
1077 | |||
1078 | idx[0] = hwif->index; | 1082 | idx[0] = hwif->index; |
1079 | 1083 | ||
1080 | ide_device_add(idx, &d); | 1084 | ide_device_add(idx, &d); |
diff --git a/drivers/ieee1394/Kconfig b/drivers/ieee1394/Kconfig index 545663ef820b..95f45f9b8e5e 100644 --- a/drivers/ieee1394/Kconfig +++ b/drivers/ieee1394/Kconfig | |||
@@ -4,7 +4,7 @@ menu "IEEE 1394 (FireWire) support" | |||
4 | source "drivers/firewire/Kconfig" | 4 | source "drivers/firewire/Kconfig" |
5 | 5 | ||
6 | config IEEE1394 | 6 | config IEEE1394 |
7 | tristate "IEEE 1394 (FireWire) support" | 7 | tristate "Stable FireWire stack" |
8 | depends on PCI || BROKEN | 8 | depends on PCI || BROKEN |
9 | help | 9 | help |
10 | IEEE 1394 describes a high performance serial bus, which is also | 10 | IEEE 1394 describes a high performance serial bus, which is also |
@@ -19,30 +19,45 @@ config IEEE1394 | |||
19 | To compile this driver as a module, say M here: the | 19 | To compile this driver as a module, say M here: the |
20 | module will be called ieee1394. | 20 | module will be called ieee1394. |
21 | 21 | ||
22 | comment "Subsystem Options" | 22 | config IEEE1394_OHCI1394 |
23 | depends on IEEE1394 | 23 | tristate "OHCI-1394 controllers" |
24 | 24 | depends on PCI && IEEE1394 | |
25 | config IEEE1394_VERBOSEDEBUG | ||
26 | bool "Excessive debugging output" | ||
27 | depends on IEEE1394 | ||
28 | help | 25 | help |
29 | If you say Y here, you will get very verbose debugging logs from | 26 | Enable this driver if you have an IEEE 1394 controller based on the |
30 | the subsystem which includes a dump of the header of every sent | 27 | OHCI-1394 specification. The current driver is only tested with OHCI |
31 | and received packet. This can amount to a high amount of data | 28 | chipsets made by Texas Instruments and NEC. Most third-party vendors |
32 | collected in a very short time which is usually also saved to | 29 | use one of these chipsets. It should work with any OHCI-1394 |
33 | disk by the system logging daemons. | 30 | compliant card, however. |
34 | 31 | ||
35 | Say Y if you really want or need the debugging output, everyone | 32 | To compile this driver as a module, say M here: the |
36 | else says N. | 33 | module will be called ohci1394. |
37 | 34 | ||
38 | comment "Controllers" | 35 | NOTE: |
39 | depends on IEEE1394 | ||
40 | 36 | ||
41 | comment "Texas Instruments PCILynx requires I2C" | 37 | You should only build either ohci1394 or the new firewire-ohci driver, |
38 | but not both. If you nevertheless want to install both, you should | ||
39 | configure them only as modules and blacklist the driver(s) which you | ||
40 | don't want to have auto-loaded. Add either | ||
41 | |||
42 | blacklist firewire-ohci | ||
43 | or | ||
44 | blacklist ohci1394 | ||
45 | blacklist video1394 | ||
46 | blacklist dv1394 | ||
47 | |||
48 | to /etc/modprobe.conf or /etc/modprobe.d/* and update modprobe.conf | ||
49 | depending on your distribution. The latter two modules should be | ||
50 | blacklisted together with ohci1394 because they depend on ohci1394. | ||
51 | |||
52 | If you have an old modprobe which doesn't implement the blacklist | ||
53 | directive, use "install modulename /bin/true" for the modules to be | ||
54 | blacklisted. | ||
55 | |||
56 | comment "PCILynx controller requires I2C" | ||
42 | depends on IEEE1394 && I2C=n | 57 | depends on IEEE1394 && I2C=n |
43 | 58 | ||
44 | config IEEE1394_PCILYNX | 59 | config IEEE1394_PCILYNX |
45 | tristate "Texas Instruments PCILynx support" | 60 | tristate "PCILynx controller" |
46 | depends on PCI && IEEE1394 && I2C | 61 | depends on PCI && IEEE1394 && I2C |
47 | select I2C_ALGOBIT | 62 | select I2C_ALGOBIT |
48 | help | 63 | help |
@@ -57,35 +72,11 @@ config IEEE1394_PCILYNX | |||
57 | PowerMacs G3 B&W contain the PCILynx controller. Therefore | 72 | PowerMacs G3 B&W contain the PCILynx controller. Therefore |
58 | almost everybody can say N here. | 73 | almost everybody can say N here. |
59 | 74 | ||
60 | config IEEE1394_OHCI1394 | ||
61 | tristate "OHCI-1394 support" | ||
62 | depends on PCI && IEEE1394 | ||
63 | help | ||
64 | Enable this driver if you have an IEEE 1394 controller based on the | ||
65 | OHCI-1394 specification. The current driver is only tested with OHCI | ||
66 | chipsets made by Texas Instruments and NEC. Most third-party vendors | ||
67 | use one of these chipsets. It should work with any OHCI-1394 | ||
68 | compliant card, however. | ||
69 | |||
70 | To compile this driver as a module, say M here: the | ||
71 | module will be called ohci1394. | ||
72 | |||
73 | comment "Protocols" | ||
74 | depends on IEEE1394 | ||
75 | |||
76 | config IEEE1394_VIDEO1394 | ||
77 | tristate "OHCI-1394 Video support" | ||
78 | depends on IEEE1394 && IEEE1394_OHCI1394 | ||
79 | help | ||
80 | This option enables video device usage for OHCI-1394 cards. Enable | ||
81 | this option only if you have an IEEE 1394 video device connected to | ||
82 | an OHCI-1394 card. | ||
83 | |||
84 | comment "SBP-2 support (for storage devices) requires SCSI" | 75 | comment "SBP-2 support (for storage devices) requires SCSI" |
85 | depends on IEEE1394 && SCSI=n | 76 | depends on IEEE1394 && SCSI=n |
86 | 77 | ||
87 | config IEEE1394_SBP2 | 78 | config IEEE1394_SBP2 |
88 | tristate "SBP-2 support (Harddisks etc.)" | 79 | tristate "Storage devices (SBP-2 protocol)" |
89 | depends on IEEE1394 && SCSI | 80 | depends on IEEE1394 && SCSI |
90 | help | 81 | help |
91 | This option enables you to use SBP-2 devices connected to an IEEE | 82 | This option enables you to use SBP-2 devices connected to an IEEE |
@@ -127,24 +118,47 @@ config IEEE1394_ETH1394 | |||
127 | 118 | ||
128 | The module is called eth1394 although it does not emulate Ethernet. | 119 | The module is called eth1394 although it does not emulate Ethernet. |
129 | 120 | ||
121 | config IEEE1394_RAWIO | ||
122 | tristate "raw1394 userspace interface" | ||
123 | depends on IEEE1394 | ||
124 | help | ||
125 | This option adds support for the raw1394 device file which enables | ||
126 | direct communication of user programs with IEEE 1394 devices | ||
127 | (isochronous and asynchronous). Almost all application programs | ||
128 | which access FireWire require this option. | ||
129 | |||
130 | To compile this driver as a module, say M here: the module will be | ||
131 | called raw1394. | ||
132 | |||
133 | config IEEE1394_VIDEO1394 | ||
134 | tristate "video1394 userspace interface" | ||
135 | depends on IEEE1394 && IEEE1394_OHCI1394 | ||
136 | help | ||
137 | This option adds support for the video1394 device files which enable | ||
138 | isochronous communication of user programs with IEEE 1394 devices, | ||
139 | especially video capture or export. This interface is used by all | ||
140 | libdc1394 based programs and by several other programs, in addition to | ||
141 | the raw1394 interface. It is generally not required for DV capture. | ||
142 | |||
143 | To compile this driver as a module, say M here: the module will be | ||
144 | called video1394. | ||
145 | |||
130 | config IEEE1394_DV1394 | 146 | config IEEE1394_DV1394 |
131 | tristate "OHCI-DV I/O support (deprecated)" | 147 | tristate "dv1394 userspace interface (deprecated)" |
132 | depends on IEEE1394 && IEEE1394_OHCI1394 | 148 | depends on IEEE1394 && IEEE1394_OHCI1394 |
133 | help | 149 | help |
134 | The dv1394 driver is unsupported and may be removed from Linux in a | 150 | The dv1394 driver is unsupported and may be removed from Linux in a |
135 | future release. Its functionality is now provided by raw1394 together | 151 | future release. Its functionality is now provided by raw1394 together |
136 | with libraries such as libiec61883. | 152 | with libraries such as libiec61883. |
137 | 153 | ||
138 | config IEEE1394_RAWIO | 154 | config IEEE1394_VERBOSEDEBUG |
139 | tristate "Raw IEEE1394 I/O support" | 155 | bool "Excessive debugging output" |
140 | depends on IEEE1394 | 156 | depends on IEEE1394 |
141 | help | 157 | help |
142 | This option adds support for the raw1394 device file which enables | 158 | If you say Y here, you will get very verbose debugging logs from the |
143 | direct communication of user programs with the IEEE 1394 bus and thus | 159 | ieee1394 drivers, including sent and received packet headers. This |
144 | with the attached peripherals. Almost all application programs which | 160 | will quickly result in large amounts of data sent to the system log. |
145 | access FireWire require this option. | ||
146 | 161 | ||
147 | To compile this driver as a module, say M here: the module will be | 162 | Say Y if you really need the debugging output. Everyone else says N. |
148 | called raw1394. | ||
149 | 163 | ||
150 | endmenu | 164 | endmenu |
diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c index f806da184b51..caed42bf7ef5 100644 --- a/drivers/infiniband/core/uverbs_main.c +++ b/drivers/infiniband/core/uverbs_main.c | |||
@@ -423,7 +423,7 @@ static void ib_uverbs_async_handler(struct ib_uverbs_file *file, | |||
423 | unsigned long flags; | 423 | unsigned long flags; |
424 | 424 | ||
425 | spin_lock_irqsave(&file->async_file->lock, flags); | 425 | spin_lock_irqsave(&file->async_file->lock, flags); |
426 | if (!file->async_file->is_closed) { | 426 | if (file->async_file->is_closed) { |
427 | spin_unlock_irqrestore(&file->async_file->lock, flags); | 427 | spin_unlock_irqrestore(&file->async_file->lock, flags); |
428 | return; | 428 | return; |
429 | } | 429 | } |
diff --git a/drivers/infiniband/hw/mthca/mthca_memfree.c b/drivers/infiniband/hw/mthca/mthca_memfree.c index b224079d4e1f..d5862e5d99a0 100644 --- a/drivers/infiniband/hw/mthca/mthca_memfree.c +++ b/drivers/infiniband/hw/mthca/mthca_memfree.c | |||
@@ -109,7 +109,11 @@ static int mthca_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_m | |||
109 | { | 109 | { |
110 | struct page *page; | 110 | struct page *page; |
111 | 111 | ||
112 | page = alloc_pages(gfp_mask, order); | 112 | /* |
113 | * Use __GFP_ZERO because buggy firmware assumes ICM pages are | ||
114 | * cleared, and subtle failures are seen if they aren't. | ||
115 | */ | ||
116 | page = alloc_pages(gfp_mask | __GFP_ZERO, order); | ||
113 | if (!page) | 117 | if (!page) |
114 | return -ENOMEM; | 118 | return -ENOMEM; |
115 | 119 | ||
diff --git a/drivers/infiniband/hw/nes/nes_verbs.c b/drivers/infiniband/hw/nes/nes_verbs.c index 99b3c4ae86eb..d617da9bd351 100644 --- a/drivers/infiniband/hw/nes/nes_verbs.c +++ b/drivers/infiniband/hw/nes/nes_verbs.c | |||
@@ -2456,10 +2456,8 @@ static struct ib_mr *nes_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, | |||
2456 | if ((page_count!=0)&&(page_count<<12)-(region->offset&(4096-1))>=region->length) | 2456 | if ((page_count!=0)&&(page_count<<12)-(region->offset&(4096-1))>=region->length) |
2457 | goto enough_pages; | 2457 | goto enough_pages; |
2458 | if ((page_count&0x01FF) == 0) { | 2458 | if ((page_count&0x01FF) == 0) { |
2459 | if (page_count>(1024*512)) { | 2459 | if (page_count >= 1024 * 512) { |
2460 | ib_umem_release(region); | 2460 | ib_umem_release(region); |
2461 | pci_free_consistent(nesdev->pcidev, 4096, vpbl.pbl_vbase, | ||
2462 | vpbl.pbl_pbase); | ||
2463 | nes_free_resource(nesadapter, | 2461 | nes_free_resource(nesadapter, |
2464 | nesadapter->allocated_mrs, stag_index); | 2462 | nesadapter->allocated_mrs, stag_index); |
2465 | kfree(nesmr); | 2463 | kfree(nesmr); |
diff --git a/drivers/input/ff-core.c b/drivers/input/ff-core.c index eebc72465fc9..72c63e5dd630 100644 --- a/drivers/input/ff-core.c +++ b/drivers/input/ff-core.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <linux/input.h> | 28 | #include <linux/input.h> |
29 | #include <linux/module.h> | 29 | #include <linux/module.h> |
30 | #include <linux/mutex.h> | 30 | #include <linux/mutex.h> |
31 | #include <linux/sched.h> | ||
31 | 32 | ||
32 | /* | 33 | /* |
33 | * Check that the effect_id is a valid effect and whether the user | 34 | * Check that the effect_id is a valid effect and whether the user |
@@ -166,8 +167,10 @@ int input_ff_upload(struct input_dev *dev, struct ff_effect *effect, | |||
166 | if (ret) | 167 | if (ret) |
167 | goto out; | 168 | goto out; |
168 | 169 | ||
170 | spin_lock_irq(&dev->event_lock); | ||
169 | ff->effects[id] = *effect; | 171 | ff->effects[id] = *effect; |
170 | ff->effect_owners[id] = file; | 172 | ff->effect_owners[id] = file; |
173 | spin_unlock_irq(&dev->event_lock); | ||
171 | 174 | ||
172 | out: | 175 | out: |
173 | mutex_unlock(&ff->mutex); | 176 | mutex_unlock(&ff->mutex); |
@@ -189,16 +192,22 @@ static int erase_effect(struct input_dev *dev, int effect_id, | |||
189 | if (error) | 192 | if (error) |
190 | return error; | 193 | return error; |
191 | 194 | ||
195 | spin_lock_irq(&dev->event_lock); | ||
192 | ff->playback(dev, effect_id, 0); | 196 | ff->playback(dev, effect_id, 0); |
197 | ff->effect_owners[effect_id] = NULL; | ||
198 | spin_unlock_irq(&dev->event_lock); | ||
193 | 199 | ||
194 | if (ff->erase) { | 200 | if (ff->erase) { |
195 | error = ff->erase(dev, effect_id); | 201 | error = ff->erase(dev, effect_id); |
196 | if (error) | 202 | if (error) { |
203 | spin_lock_irq(&dev->event_lock); | ||
204 | ff->effect_owners[effect_id] = file; | ||
205 | spin_unlock_irq(&dev->event_lock); | ||
206 | |||
197 | return error; | 207 | return error; |
208 | } | ||
198 | } | 209 | } |
199 | 210 | ||
200 | ff->effect_owners[effect_id] = NULL; | ||
201 | |||
202 | return 0; | 211 | return 0; |
203 | } | 212 | } |
204 | 213 | ||
@@ -263,8 +272,6 @@ int input_ff_event(struct input_dev *dev, unsigned int type, | |||
263 | if (type != EV_FF) | 272 | if (type != EV_FF) |
264 | return 0; | 273 | return 0; |
265 | 274 | ||
266 | mutex_lock(&ff->mutex); | ||
267 | |||
268 | switch (code) { | 275 | switch (code) { |
269 | case FF_GAIN: | 276 | case FF_GAIN: |
270 | if (!test_bit(FF_GAIN, dev->ffbit) || value > 0xffff) | 277 | if (!test_bit(FF_GAIN, dev->ffbit) || value > 0xffff) |
@@ -286,7 +293,6 @@ int input_ff_event(struct input_dev *dev, unsigned int type, | |||
286 | break; | 293 | break; |
287 | } | 294 | } |
288 | 295 | ||
289 | mutex_unlock(&ff->mutex); | ||
290 | return 0; | 296 | return 0; |
291 | } | 297 | } |
292 | EXPORT_SYMBOL_GPL(input_ff_event); | 298 | EXPORT_SYMBOL_GPL(input_ff_event); |
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 3ad8bd9f7543..432699d61c58 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig | |||
@@ -15,7 +15,6 @@ if INPUT_MISC | |||
15 | config INPUT_PCSPKR | 15 | config INPUT_PCSPKR |
16 | tristate "PC Speaker support" | 16 | tristate "PC Speaker support" |
17 | depends on PCSPKR_PLATFORM | 17 | depends on PCSPKR_PLATFORM |
18 | depends on SND_PCSP=n | ||
19 | help | 18 | help |
20 | Say Y here if you want the standard PC Speaker to be used for | 19 | Say Y here if you want the standard PC Speaker to be used for |
21 | bells and whistles. | 20 | bells and whistles. |
diff --git a/drivers/input/mouse/appletouch.c b/drivers/input/mouse/appletouch.c index 8dd3942f3022..ce6fdec19e14 100644 --- a/drivers/input/mouse/appletouch.c +++ b/drivers/input/mouse/appletouch.c | |||
@@ -589,6 +589,21 @@ static void atp_close(struct input_dev *input) | |||
589 | dev->open = 0; | 589 | dev->open = 0; |
590 | } | 590 | } |
591 | 591 | ||
592 | static int atp_handle_geyser(struct atp *dev) | ||
593 | { | ||
594 | struct usb_device *udev = dev->udev; | ||
595 | |||
596 | if (!atp_is_fountain(dev)) { | ||
597 | /* switch to raw sensor mode */ | ||
598 | if (atp_geyser_init(udev)) | ||
599 | return -EIO; | ||
600 | |||
601 | printk(KERN_INFO "appletouch: Geyser mode initialized.\n"); | ||
602 | } | ||
603 | |||
604 | return 0; | ||
605 | } | ||
606 | |||
592 | static int atp_probe(struct usb_interface *iface, const struct usb_device_id *id) | 607 | static int atp_probe(struct usb_interface *iface, const struct usb_device_id *id) |
593 | { | 608 | { |
594 | struct atp *dev; | 609 | struct atp *dev; |
@@ -633,14 +648,6 @@ static int atp_probe(struct usb_interface *iface, const struct usb_device_id *id | |||
633 | else | 648 | else |
634 | dev->datalen = 81; | 649 | dev->datalen = 81; |
635 | 650 | ||
636 | if (!atp_is_fountain(dev)) { | ||
637 | /* switch to raw sensor mode */ | ||
638 | if (atp_geyser_init(udev)) | ||
639 | goto err_free_devs; | ||
640 | |||
641 | printk(KERN_INFO "appletouch: Geyser mode initialized.\n"); | ||
642 | } | ||
643 | |||
644 | dev->urb = usb_alloc_urb(0, GFP_KERNEL); | 651 | dev->urb = usb_alloc_urb(0, GFP_KERNEL); |
645 | if (!dev->urb) | 652 | if (!dev->urb) |
646 | goto err_free_devs; | 653 | goto err_free_devs; |
@@ -654,6 +661,10 @@ static int atp_probe(struct usb_interface *iface, const struct usb_device_id *id | |||
654 | usb_rcvintpipe(udev, int_in_endpointAddr), | 661 | usb_rcvintpipe(udev, int_in_endpointAddr), |
655 | dev->data, dev->datalen, atp_complete, dev, 1); | 662 | dev->data, dev->datalen, atp_complete, dev, 1); |
656 | 663 | ||
664 | error = atp_handle_geyser(dev); | ||
665 | if (error) | ||
666 | goto err_free_buffer; | ||
667 | |||
657 | usb_make_path(udev, dev->phys, sizeof(dev->phys)); | 668 | usb_make_path(udev, dev->phys, sizeof(dev->phys)); |
658 | strlcat(dev->phys, "/input0", sizeof(dev->phys)); | 669 | strlcat(dev->phys, "/input0", sizeof(dev->phys)); |
659 | 670 | ||
@@ -744,6 +755,20 @@ static void atp_disconnect(struct usb_interface *iface) | |||
744 | printk(KERN_INFO "input: appletouch disconnected\n"); | 755 | printk(KERN_INFO "input: appletouch disconnected\n"); |
745 | } | 756 | } |
746 | 757 | ||
758 | static int atp_recover(struct atp *dev) | ||
759 | { | ||
760 | int error; | ||
761 | |||
762 | error = atp_handle_geyser(dev); | ||
763 | if (error) | ||
764 | return error; | ||
765 | |||
766 | if (dev->open && usb_submit_urb(dev->urb, GFP_ATOMIC)) | ||
767 | return -EIO; | ||
768 | |||
769 | return 0; | ||
770 | } | ||
771 | |||
747 | static int atp_suspend(struct usb_interface *iface, pm_message_t message) | 772 | static int atp_suspend(struct usb_interface *iface, pm_message_t message) |
748 | { | 773 | { |
749 | struct atp *dev = usb_get_intfdata(iface); | 774 | struct atp *dev = usb_get_intfdata(iface); |
@@ -764,12 +789,20 @@ static int atp_resume(struct usb_interface *iface) | |||
764 | return 0; | 789 | return 0; |
765 | } | 790 | } |
766 | 791 | ||
792 | static int atp_reset_resume(struct usb_interface *iface) | ||
793 | { | ||
794 | struct atp *dev = usb_get_intfdata(iface); | ||
795 | |||
796 | return atp_recover(dev); | ||
797 | } | ||
798 | |||
767 | static struct usb_driver atp_driver = { | 799 | static struct usb_driver atp_driver = { |
768 | .name = "appletouch", | 800 | .name = "appletouch", |
769 | .probe = atp_probe, | 801 | .probe = atp_probe, |
770 | .disconnect = atp_disconnect, | 802 | .disconnect = atp_disconnect, |
771 | .suspend = atp_suspend, | 803 | .suspend = atp_suspend, |
772 | .resume = atp_resume, | 804 | .resume = atp_resume, |
805 | .reset_resume = atp_reset_resume, | ||
773 | .id_table = atp_table, | 806 | .id_table = atp_table, |
774 | }; | 807 | }; |
775 | 808 | ||
diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h index 9aafa96cb746..78eb7841174c 100644 --- a/drivers/input/serio/i8042-x86ia64io.h +++ b/drivers/input/serio/i8042-x86ia64io.h | |||
@@ -193,6 +193,13 @@ static struct dmi_system_id __initdata i8042_dmi_nomux_table[] = { | |||
193 | }, | 193 | }, |
194 | }, | 194 | }, |
195 | { | 195 | { |
196 | .ident = "Fujitsu-Siemens Amilo Pro 2030", | ||
197 | .matches = { | ||
198 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"), | ||
199 | DMI_MATCH(DMI_PRODUCT_NAME, "AMILO PRO V2030"), | ||
200 | }, | ||
201 | }, | ||
202 | { | ||
196 | /* | 203 | /* |
197 | * No data is coming from the touchscreen unless KBC | 204 | * No data is coming from the touchscreen unless KBC |
198 | * is in legacy mode. | 205 | * is in legacy mode. |
diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c index 592ff55b62d0..170f71ee5772 100644 --- a/drivers/input/serio/i8042.c +++ b/drivers/input/serio/i8042.c | |||
@@ -952,8 +952,12 @@ static int i8042_resume(struct platform_device *dev) | |||
952 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; | 952 | i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; |
953 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); | 953 | i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); |
954 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | 954 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { |
955 | printk(KERN_ERR "i8042: Can't write CTR to resume\n"); | 955 | printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n"); |
956 | return -EIO; | 956 | msleep(50); |
957 | if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { | ||
958 | printk(KERN_ERR "i8042: CTR write retry failed\n"); | ||
959 | return -EIO; | ||
960 | } | ||
957 | } | 961 | } |
958 | 962 | ||
959 | 963 | ||
diff --git a/drivers/lguest/x86/core.c b/drivers/lguest/x86/core.c index 5126d5d9ea0e..2e554a4ab337 100644 --- a/drivers/lguest/x86/core.c +++ b/drivers/lguest/x86/core.c | |||
@@ -176,7 +176,7 @@ void lguest_arch_run_guest(struct lg_cpu *cpu) | |||
176 | * we set it now, so we can trap and pass that trap to the Guest if it | 176 | * we set it now, so we can trap and pass that trap to the Guest if it |
177 | * uses the FPU. */ | 177 | * uses the FPU. */ |
178 | if (cpu->ts) | 178 | if (cpu->ts) |
179 | lguest_set_ts(); | 179 | unlazy_fpu(current); |
180 | 180 | ||
181 | /* SYSENTER is an optimized way of doing system calls. We can't allow | 181 | /* SYSENTER is an optimized way of doing system calls. We can't allow |
182 | * it because it always jumps to privilege level 0. A normal Guest | 182 | * it because it always jumps to privilege level 0. A normal Guest |
@@ -196,6 +196,10 @@ void lguest_arch_run_guest(struct lg_cpu *cpu) | |||
196 | * trap made the switcher code come back, and an error code which some | 196 | * trap made the switcher code come back, and an error code which some |
197 | * traps set. */ | 197 | * traps set. */ |
198 | 198 | ||
199 | /* Restore SYSENTER if it's supposed to be on. */ | ||
200 | if (boot_cpu_has(X86_FEATURE_SEP)) | ||
201 | wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0); | ||
202 | |||
199 | /* If the Guest page faulted, then the cr2 register will tell us the | 203 | /* If the Guest page faulted, then the cr2 register will tell us the |
200 | * bad virtual address. We have to grab this now, because once we | 204 | * bad virtual address. We have to grab this now, because once we |
201 | * re-enable interrupts an interrupt could fault and thus overwrite | 205 | * re-enable interrupts an interrupt could fault and thus overwrite |
@@ -203,13 +207,12 @@ void lguest_arch_run_guest(struct lg_cpu *cpu) | |||
203 | if (cpu->regs->trapnum == 14) | 207 | if (cpu->regs->trapnum == 14) |
204 | cpu->arch.last_pagefault = read_cr2(); | 208 | cpu->arch.last_pagefault = read_cr2(); |
205 | /* Similarly, if we took a trap because the Guest used the FPU, | 209 | /* Similarly, if we took a trap because the Guest used the FPU, |
206 | * we have to restore the FPU it expects to see. */ | 210 | * we have to restore the FPU it expects to see. |
211 | * math_state_restore() may sleep and we may even move off to | ||
212 | * a different CPU. So all the critical stuff should be done | ||
213 | * before this. */ | ||
207 | else if (cpu->regs->trapnum == 7) | 214 | else if (cpu->regs->trapnum == 7) |
208 | math_state_restore(); | 215 | math_state_restore(); |
209 | |||
210 | /* Restore SYSENTER if it's supposed to be on. */ | ||
211 | if (boot_cpu_has(X86_FEATURE_SEP)) | ||
212 | wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0); | ||
213 | } | 216 | } |
214 | 217 | ||
215 | /*H:130 Now we've examined the hypercall code; our Guest can make requests. | 218 | /*H:130 Now we've examined the hypercall code; our Guest can make requests. |
diff --git a/drivers/macintosh/mediabay.c b/drivers/macintosh/mediabay.c index 82add26cc665..818aba368541 100644 --- a/drivers/macintosh/mediabay.c +++ b/drivers/macintosh/mediabay.c | |||
@@ -84,7 +84,7 @@ struct media_bay_info { | |||
84 | int cd_irq; | 84 | int cd_irq; |
85 | int cd_retry; | 85 | int cd_retry; |
86 | #endif | 86 | #endif |
87 | #if defined(CONFIG_BLK_DEV_IDE_PMAC) || defined(CONFIG_MAC_FLOPPY) | 87 | #if defined(CONFIG_BLK_DEV_IDE_PMAC) |
88 | int cd_index; | 88 | int cd_index; |
89 | #endif | 89 | #endif |
90 | }; | 90 | }; |
@@ -417,6 +417,7 @@ static void poll_media_bay(struct media_bay_info* bay) | |||
417 | } | 417 | } |
418 | } | 418 | } |
419 | 419 | ||
420 | #ifdef CONFIG_BLK_DEV_IDE_PMAC | ||
420 | int check_media_bay(struct device_node *which_bay, int what) | 421 | int check_media_bay(struct device_node *which_bay, int what) |
421 | { | 422 | { |
422 | int i; | 423 | int i; |
@@ -432,7 +433,6 @@ int check_media_bay(struct device_node *which_bay, int what) | |||
432 | } | 433 | } |
433 | EXPORT_SYMBOL(check_media_bay); | 434 | EXPORT_SYMBOL(check_media_bay); |
434 | 435 | ||
435 | #ifdef CONFIG_BLK_DEV_IDE_PMAC | ||
436 | int check_media_bay_by_base(unsigned long base, int what) | 436 | int check_media_bay_by_base(unsigned long base, int what) |
437 | { | 437 | { |
438 | int i; | 438 | int i; |
@@ -556,7 +556,8 @@ static void media_bay_step(int i) | |||
556 | printk("mediabay %d, registering IDE...\n", i); | 556 | printk("mediabay %d, registering IDE...\n", i); |
557 | pmu_suspend(); | 557 | pmu_suspend(); |
558 | ide_port_scan(bay->cd_port); | 558 | ide_port_scan(bay->cd_port); |
559 | bay->cd_index = bay->cd_port->index; | 559 | if (bay->cd_port->present) |
560 | bay->cd_index = bay->cd_port->index; | ||
560 | pmu_resume(); | 561 | pmu_resume(); |
561 | } | 562 | } |
562 | if (bay->cd_index == -1) { | 563 | if (bay->cd_index == -1) { |
diff --git a/drivers/macintosh/smu.c b/drivers/macintosh/smu.c index 77ad192962c5..d86d57af282a 100644 --- a/drivers/macintosh/smu.c +++ b/drivers/macintosh/smu.c | |||
@@ -483,12 +483,15 @@ int __init smu_init (void) | |||
483 | 483 | ||
484 | if (smu_cmdbuf_abs == 0) { | 484 | if (smu_cmdbuf_abs == 0) { |
485 | printk(KERN_ERR "SMU: Command buffer not allocated !\n"); | 485 | printk(KERN_ERR "SMU: Command buffer not allocated !\n"); |
486 | of_node_put(np); | ||
486 | return -EINVAL; | 487 | return -EINVAL; |
487 | } | 488 | } |
488 | 489 | ||
489 | smu = alloc_bootmem(sizeof(struct smu_device)); | 490 | smu = alloc_bootmem(sizeof(struct smu_device)); |
490 | if (smu == NULL) | 491 | if (smu == NULL) { |
492 | of_node_put(np); | ||
491 | return -ENOMEM; | 493 | return -ENOMEM; |
494 | } | ||
492 | memset(smu, 0, sizeof(*smu)); | 495 | memset(smu, 0, sizeof(*smu)); |
493 | 496 | ||
494 | spin_lock_init(&smu->lock); | 497 | spin_lock_init(&smu->lock); |
diff --git a/drivers/macintosh/therm_adt746x.c b/drivers/macintosh/therm_adt746x.c index 54f4942a2968..5366dc93fb38 100644 --- a/drivers/macintosh/therm_adt746x.c +++ b/drivers/macintosh/therm_adt746x.c | |||
@@ -562,18 +562,24 @@ thermostat_init(void) | |||
562 | therm_type = ADT7460; | 562 | therm_type = ADT7460; |
563 | else if (of_device_is_compatible(np, "adt7467")) | 563 | else if (of_device_is_compatible(np, "adt7467")) |
564 | therm_type = ADT7467; | 564 | therm_type = ADT7467; |
565 | else | 565 | else { |
566 | of_node_put(np); | ||
566 | return -ENODEV; | 567 | return -ENODEV; |
568 | } | ||
567 | 569 | ||
568 | prop = of_get_property(np, "hwsensor-params-version", NULL); | 570 | prop = of_get_property(np, "hwsensor-params-version", NULL); |
569 | printk(KERN_INFO "adt746x: version %d (%ssupported)\n", *prop, | 571 | printk(KERN_INFO "adt746x: version %d (%ssupported)\n", *prop, |
570 | (*prop == 1)?"":"un"); | 572 | (*prop == 1)?"":"un"); |
571 | if (*prop != 1) | 573 | if (*prop != 1) { |
574 | of_node_put(np); | ||
572 | return -ENODEV; | 575 | return -ENODEV; |
576 | } | ||
573 | 577 | ||
574 | prop = of_get_property(np, "reg", NULL); | 578 | prop = of_get_property(np, "reg", NULL); |
575 | if (!prop) | 579 | if (!prop) { |
580 | of_node_put(np); | ||
576 | return -ENODEV; | 581 | return -ENODEV; |
582 | } | ||
577 | 583 | ||
578 | /* look for bus either by path or using "reg" */ | 584 | /* look for bus either by path or using "reg" */ |
579 | if (strstr(np->full_name, "/i2c-bus@") != NULL) { | 585 | if (strstr(np->full_name, "/i2c-bus@") != NULL) { |
@@ -610,6 +616,7 @@ thermostat_init(void) | |||
610 | 616 | ||
611 | if (of_dev == NULL) { | 617 | if (of_dev == NULL) { |
612 | printk(KERN_ERR "Can't register temperatures device !\n"); | 618 | printk(KERN_ERR "Can't register temperatures device !\n"); |
619 | of_node_put(np); | ||
613 | return -ENODEV; | 620 | return -ENODEV; |
614 | } | 621 | } |
615 | 622 | ||
diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c index 835def11419d..ab6a61db63ce 100644 --- a/drivers/md/dm-crypt.c +++ b/drivers/md/dm-crypt.c | |||
@@ -432,6 +432,7 @@ static int crypt_convert(struct crypt_config *cc, | |||
432 | case 0: | 432 | case 0: |
433 | atomic_dec(&ctx->pending); | 433 | atomic_dec(&ctx->pending); |
434 | ctx->sector++; | 434 | ctx->sector++; |
435 | cond_resched(); | ||
435 | continue; | 436 | continue; |
436 | 437 | ||
437 | /* error */ | 438 | /* error */ |
diff --git a/drivers/md/md.c b/drivers/md/md.c index 7cf512a34ccf..2580ac1b9b0f 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c | |||
@@ -3897,8 +3897,10 @@ static void autorun_devices(int part) | |||
3897 | 3897 | ||
3898 | md_probe(dev, NULL, NULL); | 3898 | md_probe(dev, NULL, NULL); |
3899 | mddev = mddev_find(dev); | 3899 | mddev = mddev_find(dev); |
3900 | if (!mddev) { | 3900 | if (!mddev || !mddev->gendisk) { |
3901 | printk(KERN_ERR | 3901 | if (mddev) |
3902 | mddev_put(mddev); | ||
3903 | printk(KERN_ERR | ||
3902 | "md: cannot allocate memory for md drive.\n"); | 3904 | "md: cannot allocate memory for md drive.\n"); |
3903 | break; | 3905 | break; |
3904 | } | 3906 | } |
diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index 1de17da34a95..a71277b640ab 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c | |||
@@ -2137,6 +2137,8 @@ static int run(mddev_t *mddev) | |||
2137 | !test_bit(In_sync, &disk->rdev->flags)) { | 2137 | !test_bit(In_sync, &disk->rdev->flags)) { |
2138 | disk->head_position = 0; | 2138 | disk->head_position = 0; |
2139 | mddev->degraded++; | 2139 | mddev->degraded++; |
2140 | if (disk->rdev) | ||
2141 | conf->fullsync = 1; | ||
2140 | } | 2142 | } |
2141 | } | 2143 | } |
2142 | 2144 | ||
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index c37e256b1176..54c8ee28fcc4 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c | |||
@@ -2898,6 +2898,8 @@ static void handle_stripe5(struct stripe_head *sh) | |||
2898 | 2898 | ||
2899 | for (i = conf->raid_disks; i--; ) { | 2899 | for (i = conf->raid_disks; i--; ) { |
2900 | set_bit(R5_Wantwrite, &sh->dev[i].flags); | 2900 | set_bit(R5_Wantwrite, &sh->dev[i].flags); |
2901 | set_bit(R5_LOCKED, &dev->flags); | ||
2902 | s.locked++; | ||
2901 | if (!test_and_set_bit(STRIPE_OP_IO, &sh->ops.pending)) | 2903 | if (!test_and_set_bit(STRIPE_OP_IO, &sh->ops.pending)) |
2902 | sh->ops.count++; | 2904 | sh->ops.count++; |
2903 | } | 2905 | } |
@@ -2911,6 +2913,7 @@ static void handle_stripe5(struct stripe_head *sh) | |||
2911 | conf->raid_disks); | 2913 | conf->raid_disks); |
2912 | s.locked += handle_write_operations5(sh, 1, 1); | 2914 | s.locked += handle_write_operations5(sh, 1, 1); |
2913 | } else if (s.expanded && | 2915 | } else if (s.expanded && |
2916 | s.locked == 0 && | ||
2914 | !test_bit(STRIPE_OP_POSTXOR, &sh->ops.pending)) { | 2917 | !test_bit(STRIPE_OP_POSTXOR, &sh->ops.pending)) { |
2915 | clear_bit(STRIPE_EXPAND_READY, &sh->state); | 2918 | clear_bit(STRIPE_EXPAND_READY, &sh->state); |
2916 | atomic_dec(&conf->reshape_stripes); | 2919 | atomic_dec(&conf->reshape_stripes); |
@@ -4305,7 +4308,9 @@ static int run(mddev_t *mddev) | |||
4305 | " disk %d\n", bdevname(rdev->bdev,b), | 4308 | " disk %d\n", bdevname(rdev->bdev,b), |
4306 | raid_disk); | 4309 | raid_disk); |
4307 | working_disks++; | 4310 | working_disks++; |
4308 | } | 4311 | } else |
4312 | /* Cannot rely on bitmap to complete recovery */ | ||
4313 | conf->fullsync = 1; | ||
4309 | } | 4314 | } |
4310 | 4315 | ||
4311 | /* | 4316 | /* |
diff --git a/drivers/media/common/ir-keymaps.c b/drivers/media/common/ir-keymaps.c index a3485817e46c..8fa91f846d59 100644 --- a/drivers/media/common/ir-keymaps.c +++ b/drivers/media/common/ir-keymaps.c | |||
@@ -2201,3 +2201,41 @@ IR_KEYTAB_TYPE ir_codes_powercolor_real_angel[IR_KEYTAB_SIZE] = { | |||
2201 | [0x25] = KEY_POWER, /* power */ | 2201 | [0x25] = KEY_POWER, /* power */ |
2202 | }; | 2202 | }; |
2203 | EXPORT_SYMBOL_GPL(ir_codes_powercolor_real_angel); | 2203 | EXPORT_SYMBOL_GPL(ir_codes_powercolor_real_angel); |
2204 | |||
2205 | IR_KEYTAB_TYPE ir_codes_avermedia_a16d[IR_KEYTAB_SIZE] = { | ||
2206 | [0x20] = KEY_LIST, | ||
2207 | [0x00] = KEY_POWER, | ||
2208 | [0x28] = KEY_1, | ||
2209 | [0x18] = KEY_2, | ||
2210 | [0x38] = KEY_3, | ||
2211 | [0x24] = KEY_4, | ||
2212 | [0x14] = KEY_5, | ||
2213 | [0x34] = KEY_6, | ||
2214 | [0x2c] = KEY_7, | ||
2215 | [0x1c] = KEY_8, | ||
2216 | [0x3c] = KEY_9, | ||
2217 | [0x12] = KEY_SUBTITLE, | ||
2218 | [0x22] = KEY_0, | ||
2219 | [0x32] = KEY_REWIND, | ||
2220 | [0x3a] = KEY_SHUFFLE, | ||
2221 | [0x02] = KEY_PRINT, | ||
2222 | [0x11] = KEY_CHANNELDOWN, | ||
2223 | [0x31] = KEY_CHANNELUP, | ||
2224 | [0x0c] = KEY_ZOOM, | ||
2225 | [0x1e] = KEY_VOLUMEDOWN, | ||
2226 | [0x3e] = KEY_VOLUMEUP, | ||
2227 | [0x0a] = KEY_MUTE, | ||
2228 | [0x04] = KEY_AUDIO, | ||
2229 | [0x26] = KEY_RECORD, | ||
2230 | [0x06] = KEY_PLAY, | ||
2231 | [0x36] = KEY_STOP, | ||
2232 | [0x16] = KEY_PAUSE, | ||
2233 | [0x2e] = KEY_REWIND, | ||
2234 | [0x0e] = KEY_FASTFORWARD, | ||
2235 | [0x30] = KEY_TEXT, | ||
2236 | [0x21] = KEY_GREEN, | ||
2237 | [0x01] = KEY_BLUE, | ||
2238 | [0x08] = KEY_EPG, | ||
2239 | [0x2a] = KEY_MENU, | ||
2240 | }; | ||
2241 | EXPORT_SYMBOL_GPL(ir_codes_avermedia_a16d); | ||
diff --git a/drivers/media/common/tuners/tda18271-common.c b/drivers/media/common/tuners/tda18271-common.c index f1894fec32b9..6fb5b4586569 100644 --- a/drivers/media/common/tuners/tda18271-common.c +++ b/drivers/media/common/tuners/tda18271-common.c | |||
@@ -649,9 +649,17 @@ int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq) | |||
649 | u8 val; | 649 | u8 val; |
650 | 650 | ||
651 | int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val); | 651 | int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val); |
652 | /* The TDA18271HD/C1 rf_cal map lookup is expected to go out of range | ||
653 | * for frequencies above 61.1 MHz. In these cases, the internal RF | ||
654 | * tracking filters calibration mechanism is used. | ||
655 | * | ||
656 | * There is no need to warn the user about this. | ||
657 | */ | ||
658 | if (ret < 0) | ||
659 | goto fail; | ||
652 | 660 | ||
653 | regs[R_EB14] = val; | 661 | regs[R_EB14] = val; |
654 | 662 | fail: | |
655 | return ret; | 663 | return ret; |
656 | } | 664 | } |
657 | 665 | ||
diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c index 89c01fb1f859..93063c6fbbf6 100644 --- a/drivers/media/common/tuners/tda18271-fe.c +++ b/drivers/media/common/tuners/tda18271-fe.c | |||
@@ -45,6 +45,21 @@ static inline int charge_pump_source(struct dvb_frontend *fe, int force) | |||
45 | TDA18271_MAIN_PLL, force); | 45 | TDA18271_MAIN_PLL, force); |
46 | } | 46 | } |
47 | 47 | ||
48 | static inline void tda18271_set_if_notch(struct dvb_frontend *fe) | ||
49 | { | ||
50 | struct tda18271_priv *priv = fe->tuner_priv; | ||
51 | unsigned char *regs = priv->tda18271_regs; | ||
52 | |||
53 | switch (priv->mode) { | ||
54 | case TDA18271_ANALOG: | ||
55 | regs[R_MPD] &= ~0x80; /* IF notch = 0 */ | ||
56 | break; | ||
57 | case TDA18271_DIGITAL: | ||
58 | regs[R_MPD] |= 0x80; /* IF notch = 1 */ | ||
59 | break; | ||
60 | } | ||
61 | } | ||
62 | |||
48 | static int tda18271_channel_configuration(struct dvb_frontend *fe, | 63 | static int tda18271_channel_configuration(struct dvb_frontend *fe, |
49 | struct tda18271_std_map_item *map, | 64 | struct tda18271_std_map_item *map, |
50 | u32 freq, u32 bw) | 65 | u32 freq, u32 bw) |
@@ -60,25 +75,18 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, | |||
60 | regs[R_EP3] &= ~0x1f; /* clear std bits */ | 75 | regs[R_EP3] &= ~0x1f; /* clear std bits */ |
61 | regs[R_EP3] |= (map->agc_mode << 3) | map->std; | 76 | regs[R_EP3] |= (map->agc_mode << 3) | map->std; |
62 | 77 | ||
63 | /* set rfagc to high speed mode */ | 78 | if (priv->id == TDA18271HDC2) { |
64 | regs[R_EP3] &= ~0x04; | 79 | /* set rfagc to high speed mode */ |
80 | regs[R_EP3] &= ~0x04; | ||
81 | } | ||
65 | 82 | ||
66 | /* set cal mode to normal */ | 83 | /* set cal mode to normal */ |
67 | regs[R_EP4] &= ~0x03; | 84 | regs[R_EP4] &= ~0x03; |
68 | 85 | ||
69 | /* update IF output level & IF notch frequency */ | 86 | /* update IF output level */ |
70 | regs[R_EP4] &= ~0x1c; /* clear if level bits */ | 87 | regs[R_EP4] &= ~0x1c; /* clear if level bits */ |
71 | regs[R_EP4] |= (map->if_lvl << 2); | 88 | regs[R_EP4] |= (map->if_lvl << 2); |
72 | 89 | ||
73 | switch (priv->mode) { | ||
74 | case TDA18271_ANALOG: | ||
75 | regs[R_MPD] &= ~0x80; /* IF notch = 0 */ | ||
76 | break; | ||
77 | case TDA18271_DIGITAL: | ||
78 | regs[R_MPD] |= 0x80; /* IF notch = 1 */ | ||
79 | break; | ||
80 | } | ||
81 | |||
82 | /* update FM_RFn */ | 90 | /* update FM_RFn */ |
83 | regs[R_EP4] &= ~0x80; | 91 | regs[R_EP4] &= ~0x80; |
84 | regs[R_EP4] |= map->fm_rfn << 7; | 92 | regs[R_EP4] |= map->fm_rfn << 7; |
@@ -95,6 +103,9 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, | |||
95 | /* disable Power Level Indicator */ | 103 | /* disable Power Level Indicator */ |
96 | regs[R_EP1] |= 0x40; | 104 | regs[R_EP1] |= 0x40; |
97 | 105 | ||
106 | /* make sure thermometer is off */ | ||
107 | regs[R_TM] &= ~0x10; | ||
108 | |||
98 | /* frequency dependent parameters */ | 109 | /* frequency dependent parameters */ |
99 | 110 | ||
100 | tda18271_calc_ir_measure(fe, &freq); | 111 | tda18271_calc_ir_measure(fe, &freq); |
@@ -135,6 +146,7 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, | |||
135 | switch (priv->role) { | 146 | switch (priv->role) { |
136 | case TDA18271_MASTER: | 147 | case TDA18271_MASTER: |
137 | tda18271_calc_main_pll(fe, N); | 148 | tda18271_calc_main_pll(fe, N); |
149 | tda18271_set_if_notch(fe); | ||
138 | tda18271_write_regs(fe, R_MPD, 4); | 150 | tda18271_write_regs(fe, R_MPD, 4); |
139 | break; | 151 | break; |
140 | case TDA18271_SLAVE: | 152 | case TDA18271_SLAVE: |
@@ -142,6 +154,7 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, | |||
142 | tda18271_write_regs(fe, R_CPD, 4); | 154 | tda18271_write_regs(fe, R_CPD, 4); |
143 | 155 | ||
144 | regs[R_MPD] = regs[R_CPD] & 0x7f; | 156 | regs[R_MPD] = regs[R_CPD] & 0x7f; |
157 | tda18271_set_if_notch(fe); | ||
145 | tda18271_write_regs(fe, R_MPD, 1); | 158 | tda18271_write_regs(fe, R_MPD, 1); |
146 | break; | 159 | break; |
147 | } | 160 | } |
@@ -160,12 +173,14 @@ static int tda18271_channel_configuration(struct dvb_frontend *fe, | |||
160 | 173 | ||
161 | msleep(20); | 174 | msleep(20); |
162 | 175 | ||
163 | /* set rfagc to normal speed mode */ | 176 | if (priv->id == TDA18271HDC2) { |
164 | if (map->fm_rfn) | 177 | /* set rfagc to normal speed mode */ |
165 | regs[R_EP3] &= ~0x04; | 178 | if (map->fm_rfn) |
166 | else | 179 | regs[R_EP3] &= ~0x04; |
167 | regs[R_EP3] |= 0x04; | 180 | else |
168 | ret = tda18271_write_regs(fe, R_EP3, 1); | 181 | regs[R_EP3] |= 0x04; |
182 | ret = tda18271_write_regs(fe, R_EP3, 1); | ||
183 | } | ||
169 | fail: | 184 | fail: |
170 | return ret; | 185 | return ret; |
171 | } | 186 | } |
@@ -507,7 +522,7 @@ static int tda18271_powerscan_init(struct dvb_frontend *fe) | |||
507 | /* set cal mode to normal */ | 522 | /* set cal mode to normal */ |
508 | regs[R_EP4] &= ~0x03; | 523 | regs[R_EP4] &= ~0x03; |
509 | 524 | ||
510 | /* update IF output level & IF notch frequency */ | 525 | /* update IF output level */ |
511 | regs[R_EP4] &= ~0x1c; /* clear if level bits */ | 526 | regs[R_EP4] &= ~0x1c; /* clear if level bits */ |
512 | 527 | ||
513 | ret = tda18271_write_regs(fe, R_EP3, 2); | 528 | ret = tda18271_write_regs(fe, R_EP3, 2); |
diff --git a/drivers/media/common/tuners/xc5000.c b/drivers/media/common/tuners/xc5000.c index ceae6db901ec..7cf4f5bdb2ec 100644 --- a/drivers/media/common/tuners/xc5000.c +++ b/drivers/media/common/tuners/xc5000.c | |||
@@ -177,6 +177,7 @@ static XC_TV_STANDARD XC5000_Standard[MAX_TV_STANDARD] = { | |||
177 | {"FM Radio-INPUT1", 0x0208, 0x9002} | 177 | {"FM Radio-INPUT1", 0x0208, 0x9002} |
178 | }; | 178 | }; |
179 | 179 | ||
180 | static int xc5000_is_firmware_loaded(struct dvb_frontend *fe); | ||
180 | static int xc5000_writeregs(struct xc5000_priv *priv, u8 *buf, u8 len); | 181 | static int xc5000_writeregs(struct xc5000_priv *priv, u8 *buf, u8 len); |
181 | static int xc5000_readregs(struct xc5000_priv *priv, u8 *buf, u8 len); | 182 | static int xc5000_readregs(struct xc5000_priv *priv, u8 *buf, u8 len); |
182 | static void xc5000_TunerReset(struct dvb_frontend *fe); | 183 | static void xc5000_TunerReset(struct dvb_frontend *fe); |
@@ -352,7 +353,7 @@ static int xc_SetTVStandard(struct xc5000_priv *priv, | |||
352 | 353 | ||
353 | static int xc_shutdown(struct xc5000_priv *priv) | 354 | static int xc_shutdown(struct xc5000_priv *priv) |
354 | { | 355 | { |
355 | return 0; | 356 | return XC_RESULT_SUCCESS; |
356 | /* Fixme: cannot bring tuner back alive once shutdown | 357 | /* Fixme: cannot bring tuner back alive once shutdown |
357 | * without reloading the driver modules. | 358 | * without reloading the driver modules. |
358 | * return xc_write_reg(priv, XREG_POWER_DOWN, 0); | 359 | * return xc_write_reg(priv, XREG_POWER_DOWN, 0); |
@@ -685,6 +686,25 @@ static int xc5000_set_params(struct dvb_frontend *fe, | |||
685 | return 0; | 686 | return 0; |
686 | } | 687 | } |
687 | 688 | ||
689 | static int xc5000_is_firmware_loaded(struct dvb_frontend *fe) | ||
690 | { | ||
691 | struct xc5000_priv *priv = fe->tuner_priv; | ||
692 | int ret; | ||
693 | u16 id; | ||
694 | |||
695 | ret = xc5000_readreg(priv, XREG_PRODUCT_ID, &id); | ||
696 | if (ret == XC_RESULT_SUCCESS) { | ||
697 | if (id == XC_PRODUCT_ID_FW_NOT_LOADED) | ||
698 | ret = XC_RESULT_RESET_FAILURE; | ||
699 | else | ||
700 | ret = XC_RESULT_SUCCESS; | ||
701 | } | ||
702 | |||
703 | dprintk(1, "%s() returns %s id = 0x%x\n", __func__, | ||
704 | ret == XC_RESULT_SUCCESS ? "True" : "False", id); | ||
705 | return ret; | ||
706 | } | ||
707 | |||
688 | static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe); | 708 | static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe); |
689 | 709 | ||
690 | static int xc5000_set_analog_params(struct dvb_frontend *fe, | 710 | static int xc5000_set_analog_params(struct dvb_frontend *fe, |
@@ -693,7 +713,7 @@ static int xc5000_set_analog_params(struct dvb_frontend *fe, | |||
693 | struct xc5000_priv *priv = fe->tuner_priv; | 713 | struct xc5000_priv *priv = fe->tuner_priv; |
694 | int ret; | 714 | int ret; |
695 | 715 | ||
696 | if(priv->fwloaded == 0) | 716 | if (xc5000_is_firmware_loaded(fe) != XC_RESULT_SUCCESS) |
697 | xc_load_fw_and_init_tuner(fe); | 717 | xc_load_fw_and_init_tuner(fe); |
698 | 718 | ||
699 | dprintk(1, "%s() frequency=%d (in units of 62.5khz)\n", | 719 | dprintk(1, "%s() frequency=%d (in units of 62.5khz)\n", |
@@ -808,11 +828,10 @@ static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe) | |||
808 | struct xc5000_priv *priv = fe->tuner_priv; | 828 | struct xc5000_priv *priv = fe->tuner_priv; |
809 | int ret = 0; | 829 | int ret = 0; |
810 | 830 | ||
811 | if (priv->fwloaded == 0) { | 831 | if (xc5000_is_firmware_loaded(fe) != XC_RESULT_SUCCESS) { |
812 | ret = xc5000_fwupload(fe); | 832 | ret = xc5000_fwupload(fe); |
813 | if (ret != XC_RESULT_SUCCESS) | 833 | if (ret != XC_RESULT_SUCCESS) |
814 | return ret; | 834 | return ret; |
815 | priv->fwloaded = 1; | ||
816 | } | 835 | } |
817 | 836 | ||
818 | /* Start the tuner self-calibration process */ | 837 | /* Start the tuner self-calibration process */ |
@@ -852,7 +871,6 @@ static int xc5000_sleep(struct dvb_frontend *fe) | |||
852 | return -EREMOTEIO; | 871 | return -EREMOTEIO; |
853 | } | 872 | } |
854 | else { | 873 | else { |
855 | /* priv->fwloaded = 0; */ | ||
856 | return XC_RESULT_SUCCESS; | 874 | return XC_RESULT_SUCCESS; |
857 | } | 875 | } |
858 | } | 876 | } |
@@ -933,7 +951,6 @@ struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe, | |||
933 | cfg->i2c_address); | 951 | cfg->i2c_address); |
934 | printk(KERN_INFO | 952 | printk(KERN_INFO |
935 | "xc5000: Firmware has been loaded previously\n"); | 953 | "xc5000: Firmware has been loaded previously\n"); |
936 | priv->fwloaded = 1; | ||
937 | break; | 954 | break; |
938 | case XC_PRODUCT_ID_FW_NOT_LOADED: | 955 | case XC_PRODUCT_ID_FW_NOT_LOADED: |
939 | printk(KERN_INFO | 956 | printk(KERN_INFO |
@@ -941,7 +958,6 @@ struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe, | |||
941 | cfg->i2c_address); | 958 | cfg->i2c_address); |
942 | printk(KERN_INFO | 959 | printk(KERN_INFO |
943 | "xc5000: Firmware has not been loaded previously\n"); | 960 | "xc5000: Firmware has not been loaded previously\n"); |
944 | priv->fwloaded = 0; | ||
945 | break; | 961 | break; |
946 | default: | 962 | default: |
947 | printk(KERN_ERR | 963 | printk(KERN_ERR |
diff --git a/drivers/media/common/tuners/xc5000_priv.h b/drivers/media/common/tuners/xc5000_priv.h index ecebfe4745ad..a72a9887fe7f 100644 --- a/drivers/media/common/tuners/xc5000_priv.h +++ b/drivers/media/common/tuners/xc5000_priv.h | |||
@@ -30,7 +30,6 @@ struct xc5000_priv { | |||
30 | u32 bandwidth; | 30 | u32 bandwidth; |
31 | u8 video_standard; | 31 | u8 video_standard; |
32 | u8 rf_mode; | 32 | u8 rf_mode; |
33 | u8 fwloaded; | ||
34 | 33 | ||
35 | void *devptr; | 34 | void *devptr; |
36 | }; | 35 | }; |
diff --git a/drivers/media/dvb/dvb-usb/gl861.c b/drivers/media/dvb/dvb-usb/gl861.c index 0a8ac64a4e33..037f7ffb47b2 100644 --- a/drivers/media/dvb/dvb-usb/gl861.c +++ b/drivers/media/dvb/dvb-usb/gl861.c | |||
@@ -47,6 +47,8 @@ static int gl861_i2c_msg(struct dvb_usb_device *d, u8 addr, | |||
47 | return -EINVAL; | 47 | return -EINVAL; |
48 | } | 48 | } |
49 | 49 | ||
50 | msleep(1); /* avoid I2C errors */ | ||
51 | |||
50 | return usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev, 0), req, type, | 52 | return usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev, 0), req, type, |
51 | value, index, rbuf, rlen, 2000); | 53 | value, index, rbuf, rlen, 2000); |
52 | } | 54 | } |
@@ -92,16 +94,6 @@ static struct i2c_algorithm gl861_i2c_algo = { | |||
92 | }; | 94 | }; |
93 | 95 | ||
94 | /* Callbacks for DVB USB */ | 96 | /* Callbacks for DVB USB */ |
95 | static int gl861_identify_state(struct usb_device *udev, | ||
96 | struct dvb_usb_device_properties *props, | ||
97 | struct dvb_usb_device_description **desc, | ||
98 | int *cold) | ||
99 | { | ||
100 | *cold = 0; | ||
101 | |||
102 | return 0; | ||
103 | } | ||
104 | |||
105 | static struct zl10353_config gl861_zl10353_config = { | 97 | static struct zl10353_config gl861_zl10353_config = { |
106 | .demod_address = 0x0f, | 98 | .demod_address = 0x0f, |
107 | .no_tuner = 1, | 99 | .no_tuner = 1, |
@@ -172,7 +164,6 @@ static struct dvb_usb_device_properties gl861_properties = { | |||
172 | 164 | ||
173 | .size_of_priv = 0, | 165 | .size_of_priv = 0, |
174 | 166 | ||
175 | .identify_state = gl861_identify_state, | ||
176 | .num_adapters = 1, | 167 | .num_adapters = 1, |
177 | .adapter = {{ | 168 | .adapter = {{ |
178 | 169 | ||
@@ -194,13 +185,15 @@ static struct dvb_usb_device_properties gl861_properties = { | |||
194 | 185 | ||
195 | .num_device_descs = 2, | 186 | .num_device_descs = 2, |
196 | .devices = { | 187 | .devices = { |
197 | { "MSI Mega Sky 55801 DVB-T USB2.0", | 188 | { |
198 | { &gl861_table[0], NULL }, | 189 | .name = "MSI Mega Sky 55801 DVB-T USB2.0", |
199 | { NULL }, | 190 | .cold_ids = { NULL }, |
191 | .warm_ids = { &gl861_table[0], NULL }, | ||
200 | }, | 192 | }, |
201 | { "A-LINK DTU DVB-T USB2.0", | 193 | { |
202 | { &gl861_table[1], NULL }, | 194 | .name = "A-LINK DTU DVB-T USB2.0", |
203 | { NULL }, | 195 | .cold_ids = { NULL }, |
196 | .warm_ids = { &gl861_table[1], NULL }, | ||
204 | }, | 197 | }, |
205 | } | 198 | } |
206 | }; | 199 | }; |
diff --git a/drivers/media/dvb/dvb-usb/umt-010.c b/drivers/media/dvb/dvb-usb/umt-010.c index 9e7653bb3b66..118aab1a3e54 100644 --- a/drivers/media/dvb/dvb-usb/umt-010.c +++ b/drivers/media/dvb/dvb-usb/umt-010.c | |||
@@ -107,7 +107,7 @@ static struct dvb_usb_device_properties umt_properties = { | |||
107 | /* parameter for the MPEG2-data transfer */ | 107 | /* parameter for the MPEG2-data transfer */ |
108 | .stream = { | 108 | .stream = { |
109 | .type = USB_BULK, | 109 | .type = USB_BULK, |
110 | .count = 20, | 110 | .count = MAX_NO_URBS_FOR_DATA_STREAM, |
111 | .endpoint = 0x06, | 111 | .endpoint = 0x06, |
112 | .u = { | 112 | .u = { |
113 | .bulk = { | 113 | .bulk = { |
diff --git a/drivers/media/dvb/frontends/au8522.c b/drivers/media/dvb/frontends/au8522.c index 084a280c2d7f..03900d241a76 100644 --- a/drivers/media/dvb/frontends/au8522.c +++ b/drivers/media/dvb/frontends/au8522.c | |||
@@ -463,10 +463,13 @@ static int au8522_set_frontend(struct dvb_frontend *fe, | |||
463 | struct dvb_frontend_parameters *p) | 463 | struct dvb_frontend_parameters *p) |
464 | { | 464 | { |
465 | struct au8522_state *state = fe->demodulator_priv; | 465 | struct au8522_state *state = fe->demodulator_priv; |
466 | int ret = -EINVAL; | ||
466 | 467 | ||
467 | dprintk("%s(frequency=%d)\n", __func__, p->frequency); | 468 | dprintk("%s(frequency=%d)\n", __func__, p->frequency); |
468 | 469 | ||
469 | state->current_frequency = p->frequency; | 470 | if ((state->current_frequency == p->frequency) && |
471 | (state->current_modulation == p->u.vsb.modulation)) | ||
472 | return 0; | ||
470 | 473 | ||
471 | au8522_enable_modulation(fe, p->u.vsb.modulation); | 474 | au8522_enable_modulation(fe, p->u.vsb.modulation); |
472 | 475 | ||
@@ -476,11 +479,16 @@ static int au8522_set_frontend(struct dvb_frontend *fe, | |||
476 | if (fe->ops.tuner_ops.set_params) { | 479 | if (fe->ops.tuner_ops.set_params) { |
477 | if (fe->ops.i2c_gate_ctrl) | 480 | if (fe->ops.i2c_gate_ctrl) |
478 | fe->ops.i2c_gate_ctrl(fe, 1); | 481 | fe->ops.i2c_gate_ctrl(fe, 1); |
479 | fe->ops.tuner_ops.set_params(fe, p); | 482 | ret = fe->ops.tuner_ops.set_params(fe, p); |
480 | if (fe->ops.i2c_gate_ctrl) | 483 | if (fe->ops.i2c_gate_ctrl) |
481 | fe->ops.i2c_gate_ctrl(fe, 0); | 484 | fe->ops.i2c_gate_ctrl(fe, 0); |
482 | } | 485 | } |
483 | 486 | ||
487 | if (ret < 0) | ||
488 | return ret; | ||
489 | |||
490 | state->current_frequency = p->frequency; | ||
491 | |||
484 | return 0; | 492 | return 0; |
485 | } | 493 | } |
486 | 494 | ||
@@ -498,6 +506,16 @@ static int au8522_init(struct dvb_frontend *fe) | |||
498 | return 0; | 506 | return 0; |
499 | } | 507 | } |
500 | 508 | ||
509 | static int au8522_sleep(struct dvb_frontend *fe) | ||
510 | { | ||
511 | struct au8522_state *state = fe->demodulator_priv; | ||
512 | dprintk("%s()\n", __func__); | ||
513 | |||
514 | state->current_frequency = 0; | ||
515 | |||
516 | return 0; | ||
517 | } | ||
518 | |||
501 | static int au8522_read_status(struct dvb_frontend *fe, fe_status_t *status) | 519 | static int au8522_read_status(struct dvb_frontend *fe, fe_status_t *status) |
502 | { | 520 | { |
503 | struct au8522_state *state = fe->demodulator_priv; | 521 | struct au8522_state *state = fe->demodulator_priv; |
@@ -509,10 +527,8 @@ static int au8522_read_status(struct dvb_frontend *fe, fe_status_t *status) | |||
509 | if (state->current_modulation == VSB_8) { | 527 | if (state->current_modulation == VSB_8) { |
510 | dprintk("%s() Checking VSB_8\n", __func__); | 528 | dprintk("%s() Checking VSB_8\n", __func__); |
511 | reg = au8522_readreg(state, 0x4088); | 529 | reg = au8522_readreg(state, 0x4088); |
512 | if (reg & 0x01) | 530 | if ((reg & 0x03) == 0x03) |
513 | *status |= FE_HAS_VITERBI; | 531 | *status |= FE_HAS_LOCK | FE_HAS_SYNC | FE_HAS_VITERBI; |
514 | if (reg & 0x02) | ||
515 | *status |= FE_HAS_LOCK | FE_HAS_SYNC; | ||
516 | } else { | 532 | } else { |
517 | dprintk("%s() Checking QAM\n", __func__); | 533 | dprintk("%s() Checking QAM\n", __func__); |
518 | reg = au8522_readreg(state, 0x4541); | 534 | reg = au8522_readreg(state, 0x4541); |
@@ -672,6 +688,7 @@ static struct dvb_frontend_ops au8522_ops = { | |||
672 | }, | 688 | }, |
673 | 689 | ||
674 | .init = au8522_init, | 690 | .init = au8522_init, |
691 | .sleep = au8522_sleep, | ||
675 | .i2c_gate_ctrl = au8522_i2c_gate_ctrl, | 692 | .i2c_gate_ctrl = au8522_i2c_gate_ctrl, |
676 | .set_frontend = au8522_set_frontend, | 693 | .set_frontend = au8522_set_frontend, |
677 | .get_frontend = au8522_get_frontend, | 694 | .get_frontend = au8522_get_frontend, |
diff --git a/drivers/media/dvb/frontends/stv0299.c b/drivers/media/dvb/frontends/stv0299.c index 17556183e871..35435bef8e79 100644 --- a/drivers/media/dvb/frontends/stv0299.c +++ b/drivers/media/dvb/frontends/stv0299.c | |||
@@ -63,6 +63,7 @@ struct stv0299_state { | |||
63 | u32 symbol_rate; | 63 | u32 symbol_rate; |
64 | fe_code_rate_t fec_inner; | 64 | fe_code_rate_t fec_inner; |
65 | int errmode; | 65 | int errmode; |
66 | u32 ucblocks; | ||
66 | }; | 67 | }; |
67 | 68 | ||
68 | #define STATUS_BER 0 | 69 | #define STATUS_BER 0 |
@@ -501,8 +502,10 @@ static int stv0299_read_ber(struct dvb_frontend* fe, u32* ber) | |||
501 | { | 502 | { |
502 | struct stv0299_state* state = fe->demodulator_priv; | 503 | struct stv0299_state* state = fe->demodulator_priv; |
503 | 504 | ||
504 | if (state->errmode != STATUS_BER) return 0; | 505 | if (state->errmode != STATUS_BER) |
505 | *ber = (stv0299_readreg (state, 0x1d) << 8) | stv0299_readreg (state, 0x1e); | 506 | return -ENOSYS; |
507 | |||
508 | *ber = stv0299_readreg(state, 0x1e) | (stv0299_readreg(state, 0x1d) << 8); | ||
506 | 509 | ||
507 | return 0; | 510 | return 0; |
508 | } | 511 | } |
@@ -540,8 +543,12 @@ static int stv0299_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) | |||
540 | { | 543 | { |
541 | struct stv0299_state* state = fe->demodulator_priv; | 544 | struct stv0299_state* state = fe->demodulator_priv; |
542 | 545 | ||
543 | if (state->errmode != STATUS_UCBLOCKS) *ucblocks = 0; | 546 | if (state->errmode != STATUS_UCBLOCKS) |
544 | else *ucblocks = (stv0299_readreg (state, 0x1d) << 8) | stv0299_readreg (state, 0x1e); | 547 | return -ENOSYS; |
548 | |||
549 | state->ucblocks += stv0299_readreg(state, 0x1e); | ||
550 | state->ucblocks += (stv0299_readreg(state, 0x1d) << 8); | ||
551 | *ucblocks = state->ucblocks; | ||
545 | 552 | ||
546 | return 0; | 553 | return 0; |
547 | } | 554 | } |
diff --git a/drivers/media/dvb/frontends/tda10023.c b/drivers/media/dvb/frontends/tda10023.c index 0727b80bc4d2..c6ff5b82ff80 100644 --- a/drivers/media/dvb/frontends/tda10023.c +++ b/drivers/media/dvb/frontends/tda10023.c | |||
@@ -116,9 +116,12 @@ static u8 tda10023_readreg (struct tda10023_state* state, u8 reg) | |||
116 | int ret; | 116 | int ret; |
117 | 117 | ||
118 | ret = i2c_transfer (state->i2c, msg, 2); | 118 | ret = i2c_transfer (state->i2c, msg, 2); |
119 | if (ret != 2) | 119 | if (ret != 2) { |
120 | printk("DVB: TDA10023: %s: readreg error (ret == %i)\n", | 120 | int num = state->frontend.dvb ? state->frontend.dvb->num : -1; |
121 | __func__, ret); | 121 | printk(KERN_ERR "DVB: TDA10023(%d): %s: readreg error " |
122 | "(reg == 0x%02x, ret == %i)\n", | ||
123 | num, __func__, reg, ret); | ||
124 | } | ||
122 | return b1[0]; | 125 | return b1[0]; |
123 | } | 126 | } |
124 | 127 | ||
@@ -129,11 +132,12 @@ static int tda10023_writereg (struct tda10023_state* state, u8 reg, u8 data) | |||
129 | int ret; | 132 | int ret; |
130 | 133 | ||
131 | ret = i2c_transfer (state->i2c, &msg, 1); | 134 | ret = i2c_transfer (state->i2c, &msg, 1); |
132 | if (ret != 1) | 135 | if (ret != 1) { |
133 | printk("DVB: TDA10023(%d): %s, writereg error " | 136 | int num = state->frontend.dvb ? state->frontend.dvb->num : -1; |
137 | printk(KERN_ERR "DVB: TDA10023(%d): %s, writereg error " | ||
134 | "(reg == 0x%02x, val == 0x%02x, ret == %i)\n", | 138 | "(reg == 0x%02x, val == 0x%02x, ret == %i)\n", |
135 | state->frontend.dvb->num, __func__, reg, data, ret); | 139 | num, __func__, reg, data, ret); |
136 | 140 | } | |
137 | return (ret != 1) ? -EREMOTEIO : 0; | 141 | return (ret != 1) ? -EREMOTEIO : 0; |
138 | } | 142 | } |
139 | 143 | ||
@@ -464,7 +468,7 @@ struct dvb_frontend* tda10023_attach(const struct tda1002x_config* config, | |||
464 | int i; | 468 | int i; |
465 | 469 | ||
466 | /* allocate memory for the internal state */ | 470 | /* allocate memory for the internal state */ |
467 | state = kmalloc(sizeof(struct tda10023_state), GFP_KERNEL); | 471 | state = kzalloc(sizeof(struct tda10023_state), GFP_KERNEL); |
468 | if (state == NULL) goto error; | 472 | if (state == NULL) goto error; |
469 | 473 | ||
470 | /* setup the state */ | 474 | /* setup the state */ |
diff --git a/drivers/media/dvb/frontends/tda1004x.c b/drivers/media/dvb/frontends/tda1004x.c index 49973846373e..a0d638653567 100644 --- a/drivers/media/dvb/frontends/tda1004x.c +++ b/drivers/media/dvb/frontends/tda1004x.c | |||
@@ -1248,11 +1248,14 @@ struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config, | |||
1248 | struct i2c_adapter* i2c) | 1248 | struct i2c_adapter* i2c) |
1249 | { | 1249 | { |
1250 | struct tda1004x_state *state; | 1250 | struct tda1004x_state *state; |
1251 | int id; | ||
1251 | 1252 | ||
1252 | /* allocate memory for the internal state */ | 1253 | /* allocate memory for the internal state */ |
1253 | state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL); | 1254 | state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL); |
1254 | if (!state) | 1255 | if (!state) { |
1256 | printk(KERN_ERR "Can't alocate memory for tda10045 state\n"); | ||
1255 | return NULL; | 1257 | return NULL; |
1258 | } | ||
1256 | 1259 | ||
1257 | /* setup the state */ | 1260 | /* setup the state */ |
1258 | state->config = config; | 1261 | state->config = config; |
@@ -1260,7 +1263,15 @@ struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config, | |||
1260 | state->demod_type = TDA1004X_DEMOD_TDA10045; | 1263 | state->demod_type = TDA1004X_DEMOD_TDA10045; |
1261 | 1264 | ||
1262 | /* check if the demod is there */ | 1265 | /* check if the demod is there */ |
1263 | if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) { | 1266 | id = tda1004x_read_byte(state, TDA1004X_CHIPID); |
1267 | if (id < 0) { | ||
1268 | printk(KERN_ERR "tda10045: chip is not answering. Giving up.\n"); | ||
1269 | kfree(state); | ||
1270 | return NULL; | ||
1271 | } | ||
1272 | |||
1273 | if (id != 0x25) { | ||
1274 | printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id); | ||
1264 | kfree(state); | 1275 | kfree(state); |
1265 | return NULL; | 1276 | return NULL; |
1266 | } | 1277 | } |
@@ -1307,11 +1318,14 @@ struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config, | |||
1307 | struct i2c_adapter* i2c) | 1318 | struct i2c_adapter* i2c) |
1308 | { | 1319 | { |
1309 | struct tda1004x_state *state; | 1320 | struct tda1004x_state *state; |
1321 | int id; | ||
1310 | 1322 | ||
1311 | /* allocate memory for the internal state */ | 1323 | /* allocate memory for the internal state */ |
1312 | state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL); | 1324 | state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL); |
1313 | if (!state) | 1325 | if (!state) { |
1326 | printk(KERN_ERR "Can't alocate memory for tda10046 state\n"); | ||
1314 | return NULL; | 1327 | return NULL; |
1328 | } | ||
1315 | 1329 | ||
1316 | /* setup the state */ | 1330 | /* setup the state */ |
1317 | state->config = config; | 1331 | state->config = config; |
@@ -1319,7 +1333,14 @@ struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config, | |||
1319 | state->demod_type = TDA1004X_DEMOD_TDA10046; | 1333 | state->demod_type = TDA1004X_DEMOD_TDA10046; |
1320 | 1334 | ||
1321 | /* check if the demod is there */ | 1335 | /* check if the demod is there */ |
1322 | if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) { | 1336 | id = tda1004x_read_byte(state, TDA1004X_CHIPID); |
1337 | if (id < 0) { | ||
1338 | printk(KERN_ERR "tda10046: chip is not answering. Giving up.\n"); | ||
1339 | kfree(state); | ||
1340 | return NULL; | ||
1341 | } | ||
1342 | if (id != 0x46) { | ||
1343 | printk(KERN_ERR "Invalid tda1004x ID = 0x%02x. Can't proceed\n", id); | ||
1323 | kfree(state); | 1344 | kfree(state); |
1324 | return NULL; | 1345 | return NULL; |
1325 | } | 1346 | } |
diff --git a/drivers/media/dvb/ttpci/Kconfig b/drivers/media/dvb/ttpci/Kconfig index d4339b1b3b68..07643e010093 100644 --- a/drivers/media/dvb/ttpci/Kconfig +++ b/drivers/media/dvb/ttpci/Kconfig | |||
@@ -101,6 +101,7 @@ config DVB_BUDGET | |||
101 | config DVB_BUDGET_CI | 101 | config DVB_BUDGET_CI |
102 | tristate "Budget cards with onboard CI connector" | 102 | tristate "Budget cards with onboard CI connector" |
103 | depends on DVB_BUDGET_CORE && I2C | 103 | depends on DVB_BUDGET_CORE && I2C |
104 | depends on INPUT # due to IR | ||
104 | select DVB_STV0297 if !DVB_FE_CUSTOMISE | 105 | select DVB_STV0297 if !DVB_FE_CUSTOMISE |
105 | select DVB_STV0299 if !DVB_FE_CUSTOMISE | 106 | select DVB_STV0299 if !DVB_FE_CUSTOMISE |
106 | select DVB_TDA1004X if !DVB_FE_CUSTOMISE | 107 | select DVB_TDA1004X if !DVB_FE_CUSTOMISE |
diff --git a/drivers/media/dvb/ttpci/av7110_hw.c b/drivers/media/dvb/ttpci/av7110_hw.c index 9d81074b31df..3a3f5279e927 100644 --- a/drivers/media/dvb/ttpci/av7110_hw.c +++ b/drivers/media/dvb/ttpci/av7110_hw.c | |||
@@ -427,6 +427,7 @@ static int __av7110_send_fw_cmd(struct av7110 *av7110, u16* buf, int length) | |||
427 | if (err) { | 427 | if (err) { |
428 | printk(KERN_ERR "%s: timeout waiting on busy %s QUEUE\n", | 428 | printk(KERN_ERR "%s: timeout waiting on busy %s QUEUE\n", |
429 | __func__, type); | 429 | __func__, type); |
430 | av7110->arm_errors++; | ||
430 | return -ETIMEDOUT; | 431 | return -ETIMEDOUT; |
431 | } | 432 | } |
432 | msleep(1); | 433 | msleep(1); |
@@ -853,10 +854,8 @@ static osd_raw_window_t bpp2bit[8] = { | |||
853 | 854 | ||
854 | static inline int WaitUntilBmpLoaded(struct av7110 *av7110) | 855 | static inline int WaitUntilBmpLoaded(struct av7110 *av7110) |
855 | { | 856 | { |
856 | int ret = wait_event_interruptible_timeout(av7110->bmpq, | 857 | int ret = wait_event_timeout(av7110->bmpq, |
857 | av7110->bmp_state != BMP_LOADING, 10*HZ); | 858 | av7110->bmp_state != BMP_LOADING, 10*HZ); |
858 | if (ret == -ERESTARTSYS) | ||
859 | return ret; | ||
860 | if (ret == 0) { | 859 | if (ret == 0) { |
861 | printk("dvb-ttpci: warning: timeout waiting in LoadBitmap: %d, %d\n", | 860 | printk("dvb-ttpci: warning: timeout waiting in LoadBitmap: %d, %d\n", |
862 | ret, av7110->bmp_state); | 861 | ret, av7110->bmp_state); |
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index 3b26fbd3e558..5ccb0aeca8cc 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig | |||
@@ -793,6 +793,14 @@ menuconfig V4L_USB_DRIVERS | |||
793 | 793 | ||
794 | if V4L_USB_DRIVERS && USB | 794 | if V4L_USB_DRIVERS && USB |
795 | 795 | ||
796 | config USB_VIDEO_CLASS | ||
797 | tristate "USB Video Class (UVC)" | ||
798 | ---help--- | ||
799 | Support for the USB Video Class (UVC). Currently only video | ||
800 | input devices, such as webcams, are supported. | ||
801 | |||
802 | For more information see: <http://linux-uvc.berlios.de/> | ||
803 | |||
796 | source "drivers/media/video/pvrusb2/Kconfig" | 804 | source "drivers/media/video/pvrusb2/Kconfig" |
797 | 805 | ||
798 | source "drivers/media/video/em28xx/Kconfig" | 806 | source "drivers/media/video/em28xx/Kconfig" |
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile index dff0d6abe917..ecbbfaab24d5 100644 --- a/drivers/media/video/Makefile +++ b/drivers/media/video/Makefile | |||
@@ -136,6 +136,8 @@ obj-$(CONFIG_SOC_CAMERA_MT9V022) += mt9v022.o | |||
136 | 136 | ||
137 | obj-$(CONFIG_VIDEO_AU0828) += au0828/ | 137 | obj-$(CONFIG_VIDEO_AU0828) += au0828/ |
138 | 138 | ||
139 | obj-$(CONFIG_USB_VIDEO_CLASS) += uvc/ | ||
140 | |||
139 | EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core | 141 | EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core |
140 | EXTRA_CFLAGS += -Idrivers/media/dvb/frontends | 142 | EXTRA_CFLAGS += -Idrivers/media/dvb/frontends |
141 | EXTRA_CFLAGS += -Idrivers/media/common/tuners | 143 | EXTRA_CFLAGS += -Idrivers/media/common/tuners |
diff --git a/drivers/media/video/au0828/au0828-cards.c b/drivers/media/video/au0828/au0828-cards.c index a2a6983444fa..898e12395e7c 100644 --- a/drivers/media/video/au0828/au0828-cards.c +++ b/drivers/media/video/au0828/au0828-cards.c | |||
@@ -77,8 +77,14 @@ static void hauppauge_eeprom(struct au0828_dev *dev, u8 *eeprom_data) | |||
77 | 77 | ||
78 | /* Make sure we support the board model */ | 78 | /* Make sure we support the board model */ |
79 | switch (tv.model) { | 79 | switch (tv.model) { |
80 | case 72000: /* WinTV-HVR950q (Retail, IR, ATSC/QAM */ | ||
80 | case 72001: /* WinTV-HVR950q (Retail, IR, ATSC/QAM and basic analog video */ | 81 | case 72001: /* WinTV-HVR950q (Retail, IR, ATSC/QAM and basic analog video */ |
82 | case 72211: /* WinTV-HVR950q (OEM, IR, ATSC/QAM and basic analog video */ | ||
83 | case 72221: /* WinTV-HVR950q (OEM, IR, ATSC/QAM and basic analog video */ | ||
84 | case 72231: /* WinTV-HVR950q (OEM, IR, ATSC/QAM and basic analog video */ | ||
85 | case 72241: /* WinTV-HVR950q (OEM, No IR, ATSC/QAM and basic analog video */ | ||
81 | case 72301: /* WinTV-HVR850 (Retail, IR, ATSC and basic analog video */ | 86 | case 72301: /* WinTV-HVR850 (Retail, IR, ATSC and basic analog video */ |
87 | case 72500: /* WinTV-HVR950q (OEM, No IR, ATSC/QAM */ | ||
82 | break; | 88 | break; |
83 | default: | 89 | default: |
84 | printk(KERN_WARNING "%s: warning: " | 90 | printk(KERN_WARNING "%s: warning: " |
@@ -175,6 +181,18 @@ struct usb_device_id au0828_usb_id_table [] = { | |||
175 | .driver_info = AU0828_BOARD_HAUPPAUGE_HVR850 }, | 181 | .driver_info = AU0828_BOARD_HAUPPAUGE_HVR850 }, |
176 | { USB_DEVICE(0x0fe9, 0xd620), | 182 | { USB_DEVICE(0x0fe9, 0xd620), |
177 | .driver_info = AU0828_BOARD_DVICO_FUSIONHDTV7 }, | 183 | .driver_info = AU0828_BOARD_DVICO_FUSIONHDTV7 }, |
184 | { USB_DEVICE(0x2040, 0x7210), | ||
185 | .driver_info = AU0828_BOARD_HAUPPAUGE_HVR950Q }, | ||
186 | { USB_DEVICE(0x2040, 0x7217), | ||
187 | .driver_info = AU0828_BOARD_HAUPPAUGE_HVR950Q }, | ||
188 | { USB_DEVICE(0x2040, 0x721b), | ||
189 | .driver_info = AU0828_BOARD_HAUPPAUGE_HVR950Q }, | ||
190 | { USB_DEVICE(0x2040, 0x721f), | ||
191 | .driver_info = AU0828_BOARD_HAUPPAUGE_HVR950Q }, | ||
192 | { USB_DEVICE(0x2040, 0x7280), | ||
193 | .driver_info = AU0828_BOARD_HAUPPAUGE_HVR950Q }, | ||
194 | { USB_DEVICE(0x0fd9, 0x0008), | ||
195 | .driver_info = AU0828_BOARD_HAUPPAUGE_HVR950Q }, | ||
178 | { }, | 196 | { }, |
179 | }; | 197 | }; |
180 | 198 | ||
diff --git a/drivers/media/video/cx18/Kconfig b/drivers/media/video/cx18/Kconfig index 5f942690570c..9aefdc5ea79a 100644 --- a/drivers/media/video/cx18/Kconfig +++ b/drivers/media/video/cx18/Kconfig | |||
@@ -10,8 +10,8 @@ config VIDEO_CX18 | |||
10 | select VIDEO_TVEEPROM | 10 | select VIDEO_TVEEPROM |
11 | select VIDEO_CX2341X | 11 | select VIDEO_CX2341X |
12 | select VIDEO_CS5345 | 12 | select VIDEO_CS5345 |
13 | select DVB_S5H1409 | 13 | select DVB_S5H1409 if !DVB_FE_CUSTOMISE |
14 | select MEDIA_TUNER_MXL5005S | 14 | select MEDIA_TUNER_MXL5005S if !DVB_FE_CUSTOMISE |
15 | ---help--- | 15 | ---help--- |
16 | This is a video4linux driver for Conexant cx23418 based | 16 | This is a video4linux driver for Conexant cx23418 based |
17 | PCI combo video recorder devices. | 17 | PCI combo video recorder devices. |
diff --git a/drivers/media/video/cx18/cx18-av-core.c b/drivers/media/video/cx18/cx18-av-core.c index 9a26751615c6..faca43eb940f 100644 --- a/drivers/media/video/cx18/cx18-av-core.c +++ b/drivers/media/video/cx18/cx18-av-core.c | |||
@@ -69,6 +69,58 @@ int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask, | |||
69 | or_value); | 69 | or_value); |
70 | } | 70 | } |
71 | 71 | ||
72 | int cx18_av_write_no_acfg(struct cx18 *cx, u16 addr, u8 value, int no_acfg_mask) | ||
73 | { | ||
74 | int retval; | ||
75 | u32 saved_reg[8] = {0}; | ||
76 | |||
77 | if (no_acfg_mask & CXADEC_NO_ACFG_AFE) { | ||
78 | saved_reg[0] = cx18_av_read4(cx, CXADEC_CHIP_CTRL); | ||
79 | saved_reg[1] = cx18_av_read4(cx, CXADEC_AFE_CTRL); | ||
80 | } | ||
81 | |||
82 | if (no_acfg_mask & CXADEC_NO_ACFG_PLL) { | ||
83 | saved_reg[2] = cx18_av_read4(cx, CXADEC_PLL_CTRL1); | ||
84 | saved_reg[3] = cx18_av_read4(cx, CXADEC_VID_PLL_FRAC); | ||
85 | } | ||
86 | |||
87 | if (no_acfg_mask & CXADEC_NO_ACFG_VID) { | ||
88 | saved_reg[4] = cx18_av_read4(cx, CXADEC_HORIZ_TIM_CTRL); | ||
89 | saved_reg[5] = cx18_av_read4(cx, CXADEC_VERT_TIM_CTRL); | ||
90 | saved_reg[6] = cx18_av_read4(cx, CXADEC_SRC_COMB_CFG); | ||
91 | saved_reg[7] = cx18_av_read4(cx, CXADEC_CHROMA_VBIOFF_CFG); | ||
92 | } | ||
93 | |||
94 | retval = cx18_av_write(cx, addr, value); | ||
95 | |||
96 | if (no_acfg_mask & CXADEC_NO_ACFG_AFE) { | ||
97 | cx18_av_write4(cx, CXADEC_CHIP_CTRL, saved_reg[0]); | ||
98 | cx18_av_write4(cx, CXADEC_AFE_CTRL, saved_reg[1]); | ||
99 | } | ||
100 | |||
101 | if (no_acfg_mask & CXADEC_NO_ACFG_PLL) { | ||
102 | cx18_av_write4(cx, CXADEC_PLL_CTRL1, saved_reg[2]); | ||
103 | cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, saved_reg[3]); | ||
104 | } | ||
105 | |||
106 | if (no_acfg_mask & CXADEC_NO_ACFG_VID) { | ||
107 | cx18_av_write4(cx, CXADEC_HORIZ_TIM_CTRL, saved_reg[4]); | ||
108 | cx18_av_write4(cx, CXADEC_VERT_TIM_CTRL, saved_reg[5]); | ||
109 | cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, saved_reg[6]); | ||
110 | cx18_av_write4(cx, CXADEC_CHROMA_VBIOFF_CFG, saved_reg[7]); | ||
111 | } | ||
112 | |||
113 | return retval; | ||
114 | } | ||
115 | |||
116 | int cx18_av_and_or_no_acfg(struct cx18 *cx, u16 addr, unsigned and_mask, | ||
117 | u8 or_value, int no_acfg_mask) | ||
118 | { | ||
119 | return cx18_av_write_no_acfg(cx, addr, | ||
120 | (cx18_av_read(cx, addr) & and_mask) | | ||
121 | or_value, no_acfg_mask); | ||
122 | } | ||
123 | |||
72 | /* ----------------------------------------------------------------------- */ | 124 | /* ----------------------------------------------------------------------- */ |
73 | 125 | ||
74 | static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input, | 126 | static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input, |
@@ -170,13 +222,15 @@ static void input_change(struct cx18 *cx) | |||
170 | 222 | ||
171 | /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */ | 223 | /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */ |
172 | if (std & V4L2_STD_SECAM) | 224 | if (std & V4L2_STD_SECAM) |
173 | cx18_av_write(cx, 0x402, 0); | 225 | cx18_av_write_no_acfg(cx, 0x402, 0, CXADEC_NO_ACFG_ALL); |
174 | else { | 226 | else { |
175 | cx18_av_write(cx, 0x402, 0x04); | 227 | cx18_av_write_no_acfg(cx, 0x402, 0x04, CXADEC_NO_ACFG_ALL); |
176 | cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11); | 228 | cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11); |
177 | } | 229 | } |
178 | cx18_av_and_or(cx, 0x401, ~0x60, 0); | 230 | cx18_av_and_or_no_acfg(cx, 0x401, ~0x60, 0, |
179 | cx18_av_and_or(cx, 0x401, ~0x60, 0x60); | 231 | CXADEC_NO_ACFG_PLL | CXADEC_NO_ACFG_VID); |
232 | cx18_av_and_or_no_acfg(cx, 0x401, ~0x60, 0x60, | ||
233 | CXADEC_NO_ACFG_PLL | CXADEC_NO_ACFG_VID); | ||
180 | 234 | ||
181 | if (std & V4L2_STD_525_60) { | 235 | if (std & V4L2_STD_525_60) { |
182 | if (std == V4L2_STD_NTSC_M_JP) { | 236 | if (std == V4L2_STD_NTSC_M_JP) { |
@@ -228,7 +282,7 @@ static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input, | |||
228 | 282 | ||
229 | if ((vid_input & ~0xff0) || | 283 | if ((vid_input & ~0xff0) || |
230 | luma < CX18_AV_SVIDEO_LUMA1 || | 284 | luma < CX18_AV_SVIDEO_LUMA1 || |
231 | luma > CX18_AV_SVIDEO_LUMA4 || | 285 | luma > CX18_AV_SVIDEO_LUMA8 || |
232 | chroma < CX18_AV_SVIDEO_CHROMA4 || | 286 | chroma < CX18_AV_SVIDEO_CHROMA4 || |
233 | chroma > CX18_AV_SVIDEO_CHROMA8) { | 287 | chroma > CX18_AV_SVIDEO_CHROMA8) { |
234 | CX18_ERR("0x%04x is not a valid video input!\n", | 288 | CX18_ERR("0x%04x is not a valid video input!\n", |
@@ -262,7 +316,8 @@ static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input, | |||
262 | 316 | ||
263 | cx18_av_write(cx, 0x103, reg); | 317 | cx18_av_write(cx, 0x103, reg); |
264 | /* Set INPUT_MODE to Composite (0) or S-Video (1) */ | 318 | /* Set INPUT_MODE to Composite (0) or S-Video (1) */ |
265 | cx18_av_and_or(cx, 0x401, ~0x6, is_composite ? 0 : 0x02); | 319 | cx18_av_and_or_no_acfg(cx, 0x401, ~0x6, is_composite ? 0 : 0x02, |
320 | CXADEC_NO_ACFG_PLL | CXADEC_NO_ACFG_VID); | ||
266 | /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */ | 321 | /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */ |
267 | cx18_av_and_or(cx, 0x102, ~0x2, (reg & 0x80) == 0 ? 2 : 0); | 322 | cx18_av_and_or(cx, 0x102, ~0x2, (reg & 0x80) == 0 ? 2 : 0); |
268 | /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */ | 323 | /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */ |
@@ -318,12 +373,12 @@ static int set_v4lstd(struct cx18 *cx) | |||
318 | This happens for example with the Yuan MPC622. */ | 373 | This happens for example with the Yuan MPC622. */ |
319 | if (fmt >= 4 && fmt < 8) { | 374 | if (fmt >= 4 && fmt < 8) { |
320 | /* Set format to NTSC-M */ | 375 | /* Set format to NTSC-M */ |
321 | cx18_av_and_or(cx, 0x400, ~0xf, 1); | 376 | cx18_av_and_or_no_acfg(cx, 0x400, ~0xf, 1, CXADEC_NO_ACFG_AFE); |
322 | /* Turn off LCOMB */ | 377 | /* Turn off LCOMB */ |
323 | cx18_av_and_or(cx, 0x47b, ~6, 0); | 378 | cx18_av_and_or(cx, 0x47b, ~6, 0); |
324 | } | 379 | } |
325 | cx18_av_and_or(cx, 0x400, ~0xf, fmt); | 380 | cx18_av_and_or_no_acfg(cx, 0x400, ~0xf, fmt, CXADEC_NO_ACFG_AFE); |
326 | cx18_av_and_or(cx, 0x403, ~0x3, pal_m); | 381 | cx18_av_and_or_no_acfg(cx, 0x403, ~0x3, pal_m, CXADEC_NO_ACFG_ALL); |
327 | cx18_av_vbi_setup(cx); | 382 | cx18_av_vbi_setup(cx); |
328 | input_change(cx); | 383 | input_change(cx); |
329 | return 0; | 384 | return 0; |
diff --git a/drivers/media/video/cx18/cx18-av-core.h b/drivers/media/video/cx18/cx18-av-core.h index 786901d72e9a..c172823ce1d8 100644 --- a/drivers/media/video/cx18/cx18-av-core.h +++ b/drivers/media/video/cx18/cx18-av-core.h | |||
@@ -37,12 +37,16 @@ enum cx18_av_video_input { | |||
37 | CX18_AV_COMPOSITE7, | 37 | CX18_AV_COMPOSITE7, |
38 | CX18_AV_COMPOSITE8, | 38 | CX18_AV_COMPOSITE8, |
39 | 39 | ||
40 | /* S-Video inputs consist of one luma input (In1-In4) ORed with one | 40 | /* S-Video inputs consist of one luma input (In1-In8) ORed with one |
41 | chroma input (In5-In8) */ | 41 | chroma input (In5-In8) */ |
42 | CX18_AV_SVIDEO_LUMA1 = 0x10, | 42 | CX18_AV_SVIDEO_LUMA1 = 0x10, |
43 | CX18_AV_SVIDEO_LUMA2 = 0x20, | 43 | CX18_AV_SVIDEO_LUMA2 = 0x20, |
44 | CX18_AV_SVIDEO_LUMA3 = 0x30, | 44 | CX18_AV_SVIDEO_LUMA3 = 0x30, |
45 | CX18_AV_SVIDEO_LUMA4 = 0x40, | 45 | CX18_AV_SVIDEO_LUMA4 = 0x40, |
46 | CX18_AV_SVIDEO_LUMA5 = 0x50, | ||
47 | CX18_AV_SVIDEO_LUMA6 = 0x60, | ||
48 | CX18_AV_SVIDEO_LUMA7 = 0x70, | ||
49 | CX18_AV_SVIDEO_LUMA8 = 0x80, | ||
46 | CX18_AV_SVIDEO_CHROMA4 = 0x400, | 50 | CX18_AV_SVIDEO_CHROMA4 = 0x400, |
47 | CX18_AV_SVIDEO_CHROMA5 = 0x500, | 51 | CX18_AV_SVIDEO_CHROMA5 = 0x500, |
48 | CX18_AV_SVIDEO_CHROMA6 = 0x600, | 52 | CX18_AV_SVIDEO_CHROMA6 = 0x600, |
@@ -291,14 +295,24 @@ struct cx18_av_state { | |||
291 | #define CXADEC_SELECT_AUDIO_STANDARD_FM 0xF9 /* FM radio */ | 295 | #define CXADEC_SELECT_AUDIO_STANDARD_FM 0xF9 /* FM radio */ |
292 | #define CXADEC_SELECT_AUDIO_STANDARD_AUTO 0xFF /* Auto detect */ | 296 | #define CXADEC_SELECT_AUDIO_STANDARD_AUTO 0xFF /* Auto detect */ |
293 | 297 | ||
298 | /* Flags on what to preserve on write to 0x400-0x403 with cx18_av_.*_no_acfg()*/ | ||
299 | #define CXADEC_NO_ACFG_AFE 0x01 /* Preserve 0x100-0x107 */ | ||
300 | #define CXADEC_NO_ACFG_PLL 0x02 /* Preserve 0x108-0x10f */ | ||
301 | #define CXADEC_NO_ACFG_VID 0x04 /* Preserve 0x470-0x47f */ | ||
302 | #define CXADEC_NO_ACFG_ALL 0x07 | ||
303 | |||
294 | /* ----------------------------------------------------------------------- */ | 304 | /* ----------------------------------------------------------------------- */ |
295 | /* cx18_av-core.c */ | 305 | /* cx18_av-core.c */ |
296 | int cx18_av_write(struct cx18 *cx, u16 addr, u8 value); | 306 | int cx18_av_write(struct cx18 *cx, u16 addr, u8 value); |
297 | int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value); | 307 | int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value); |
308 | int cx18_av_write_no_acfg(struct cx18 *cx, u16 addr, u8 value, | ||
309 | int no_acfg_mask); | ||
298 | u8 cx18_av_read(struct cx18 *cx, u16 addr); | 310 | u8 cx18_av_read(struct cx18 *cx, u16 addr); |
299 | u32 cx18_av_read4(struct cx18 *cx, u16 addr); | 311 | u32 cx18_av_read4(struct cx18 *cx, u16 addr); |
300 | int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value); | 312 | int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned mask, u8 value); |
301 | int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value); | 313 | int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 mask, u32 value); |
314 | int cx18_av_and_or_no_acfg(struct cx18 *cx, u16 addr, unsigned mask, u8 value, | ||
315 | int no_acfg_mask); | ||
302 | int cx18_av_cmd(struct cx18 *cx, unsigned int cmd, void *arg); | 316 | int cx18_av_cmd(struct cx18 *cx, unsigned int cmd, void *arg); |
303 | 317 | ||
304 | /* ----------------------------------------------------------------------- */ | 318 | /* ----------------------------------------------------------------------- */ |
diff --git a/drivers/media/video/cx18/cx18-cards.c b/drivers/media/video/cx18/cx18-cards.c index baccd079243d..c26e0ef5b075 100644 --- a/drivers/media/video/cx18/cx18-cards.c +++ b/drivers/media/video/cx18/cx18-cards.c | |||
@@ -23,6 +23,7 @@ | |||
23 | 23 | ||
24 | #include "cx18-driver.h" | 24 | #include "cx18-driver.h" |
25 | #include "cx18-cards.h" | 25 | #include "cx18-cards.h" |
26 | #include "cx18-av-core.h" | ||
26 | #include "cx18-i2c.h" | 27 | #include "cx18-i2c.h" |
27 | #include <media/cs5345.h> | 28 | #include <media/cs5345.h> |
28 | 29 | ||
@@ -54,22 +55,22 @@ static const struct cx18_card cx18_card_hvr1600_esmt = { | |||
54 | .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | | 55 | .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | |
55 | CX18_HW_CS5345 | CX18_HW_DVB, | 56 | CX18_HW_CS5345 | CX18_HW_DVB, |
56 | .video_inputs = { | 57 | .video_inputs = { |
57 | { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 }, | 58 | { CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE7 }, |
58 | { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 }, | 59 | { CX18_CARD_INPUT_SVIDEO1, 1, CX18_AV_SVIDEO1 }, |
59 | { CX18_CARD_INPUT_COMPOSITE1, 1, CX23418_COMPOSITE3 }, | 60 | { CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE3 }, |
60 | { CX18_CARD_INPUT_SVIDEO2, 2, CX23418_SVIDEO2 }, | 61 | { CX18_CARD_INPUT_SVIDEO2, 2, CX18_AV_SVIDEO2 }, |
61 | { CX18_CARD_INPUT_COMPOSITE2, 2, CX23418_COMPOSITE4 }, | 62 | { CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE4 }, |
62 | }, | 63 | }, |
63 | .audio_inputs = { | 64 | .audio_inputs = { |
64 | { CX18_CARD_INPUT_AUD_TUNER, | 65 | { CX18_CARD_INPUT_AUD_TUNER, |
65 | CX23418_AUDIO8, CS5345_IN_1 | CS5345_MCLK_1_5 }, | 66 | CX18_AV_AUDIO8, CS5345_IN_1 | CS5345_MCLK_1_5 }, |
66 | { CX18_CARD_INPUT_LINE_IN1, | 67 | { CX18_CARD_INPUT_LINE_IN1, |
67 | CX23418_AUDIO_SERIAL, CS5345_IN_2 }, | 68 | CX18_AV_AUDIO_SERIAL, CS5345_IN_2 }, |
68 | { CX18_CARD_INPUT_LINE_IN2, | 69 | { CX18_CARD_INPUT_LINE_IN2, |
69 | CX23418_AUDIO_SERIAL, CS5345_IN_2 }, | 70 | CX18_AV_AUDIO_SERIAL, CS5345_IN_3 }, |
70 | }, | 71 | }, |
71 | .radio_input = { CX18_CARD_INPUT_AUD_TUNER, | 72 | .radio_input = { CX18_CARD_INPUT_AUD_TUNER, |
72 | CX23418_AUDIO_SERIAL, 0 }, | 73 | CX18_AV_AUDIO_SERIAL, CS5345_IN_4 }, |
73 | .ddr = { | 74 | .ddr = { |
74 | /* ESMT M13S128324A-5B memory */ | 75 | /* ESMT M13S128324A-5B memory */ |
75 | .chip_config = 0x003, | 76 | .chip_config = 0x003, |
@@ -81,6 +82,11 @@ static const struct cx18_card cx18_card_hvr1600_esmt = { | |||
81 | }, | 82 | }, |
82 | .gpio_init.initial_value = 0x3001, | 83 | .gpio_init.initial_value = 0x3001, |
83 | .gpio_init.direction = 0x3001, | 84 | .gpio_init.direction = 0x3001, |
85 | .gpio_i2c_slave_reset = { | ||
86 | .active_lo_mask = 0x3001, | ||
87 | .msecs_asserted = 10, | ||
88 | .msecs_recovery = 40, | ||
89 | }, | ||
84 | .i2c = &cx18_i2c_std, | 90 | .i2c = &cx18_i2c_std, |
85 | }; | 91 | }; |
86 | 92 | ||
@@ -94,22 +100,22 @@ static const struct cx18_card cx18_card_hvr1600_samsung = { | |||
94 | .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | | 100 | .hw_all = CX18_HW_TVEEPROM | CX18_HW_TUNER | |
95 | CX18_HW_CS5345 | CX18_HW_DVB, | 101 | CX18_HW_CS5345 | CX18_HW_DVB, |
96 | .video_inputs = { | 102 | .video_inputs = { |
97 | { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 }, | 103 | { CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE7 }, |
98 | { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 }, | 104 | { CX18_CARD_INPUT_SVIDEO1, 1, CX18_AV_SVIDEO1 }, |
99 | { CX18_CARD_INPUT_COMPOSITE1, 1, CX23418_COMPOSITE3 }, | 105 | { CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE3 }, |
100 | { CX18_CARD_INPUT_SVIDEO2, 2, CX23418_SVIDEO2 }, | 106 | { CX18_CARD_INPUT_SVIDEO2, 2, CX18_AV_SVIDEO2 }, |
101 | { CX18_CARD_INPUT_COMPOSITE2, 2, CX23418_COMPOSITE4 }, | 107 | { CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE4 }, |
102 | }, | 108 | }, |
103 | .audio_inputs = { | 109 | .audio_inputs = { |
104 | { CX18_CARD_INPUT_AUD_TUNER, | 110 | { CX18_CARD_INPUT_AUD_TUNER, |
105 | CX23418_AUDIO8, CS5345_IN_1 | CS5345_MCLK_1_5 }, | 111 | CX18_AV_AUDIO8, CS5345_IN_1 | CS5345_MCLK_1_5 }, |
106 | { CX18_CARD_INPUT_LINE_IN1, | 112 | { CX18_CARD_INPUT_LINE_IN1, |
107 | CX23418_AUDIO_SERIAL, CS5345_IN_2 }, | 113 | CX18_AV_AUDIO_SERIAL, CS5345_IN_2 }, |
108 | { CX18_CARD_INPUT_LINE_IN2, | 114 | { CX18_CARD_INPUT_LINE_IN2, |
109 | CX23418_AUDIO_SERIAL, CS5345_IN_2 }, | 115 | CX18_AV_AUDIO_SERIAL, CS5345_IN_3 }, |
110 | }, | 116 | }, |
111 | .radio_input = { CX18_CARD_INPUT_AUD_TUNER, | 117 | .radio_input = { CX18_CARD_INPUT_AUD_TUNER, |
112 | CX23418_AUDIO_SERIAL, 0 }, | 118 | CX18_AV_AUDIO_SERIAL, CS5345_IN_4 }, |
113 | .ddr = { | 119 | .ddr = { |
114 | /* Samsung K4D263238G-VC33 memory */ | 120 | /* Samsung K4D263238G-VC33 memory */ |
115 | .chip_config = 0x003, | 121 | .chip_config = 0x003, |
@@ -121,6 +127,11 @@ static const struct cx18_card cx18_card_hvr1600_samsung = { | |||
121 | }, | 127 | }, |
122 | .gpio_init.initial_value = 0x3001, | 128 | .gpio_init.initial_value = 0x3001, |
123 | .gpio_init.direction = 0x3001, | 129 | .gpio_init.direction = 0x3001, |
130 | .gpio_i2c_slave_reset = { | ||
131 | .active_lo_mask = 0x3001, | ||
132 | .msecs_asserted = 10, | ||
133 | .msecs_recovery = 40, | ||
134 | }, | ||
124 | .i2c = &cx18_i2c_std, | 135 | .i2c = &cx18_i2c_std, |
125 | }; | 136 | }; |
126 | 137 | ||
@@ -141,19 +152,19 @@ static const struct cx18_card cx18_card_h900 = { | |||
141 | .hw_audio_ctrl = CX18_HW_CX23418, | 152 | .hw_audio_ctrl = CX18_HW_CX23418, |
142 | .hw_all = CX18_HW_TUNER, | 153 | .hw_all = CX18_HW_TUNER, |
143 | .video_inputs = { | 154 | .video_inputs = { |
144 | { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE2 }, | 155 | { CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 }, |
145 | { CX18_CARD_INPUT_SVIDEO1, 1, | 156 | { CX18_CARD_INPUT_SVIDEO1, 1, |
146 | CX23418_SVIDEO_LUMA3 | CX23418_SVIDEO_CHROMA4 }, | 157 | CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 }, |
147 | { CX18_CARD_INPUT_COMPOSITE1, 1, CX23418_COMPOSITE1 }, | 158 | { CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 }, |
148 | }, | 159 | }, |
149 | .audio_inputs = { | 160 | .audio_inputs = { |
150 | { CX18_CARD_INPUT_AUD_TUNER, | 161 | { CX18_CARD_INPUT_AUD_TUNER, |
151 | CX23418_AUDIO8, 0 }, | 162 | CX18_AV_AUDIO8, 0 }, |
152 | { CX18_CARD_INPUT_LINE_IN1, | 163 | { CX18_CARD_INPUT_LINE_IN1, |
153 | CX23418_AUDIO_SERIAL, 0 }, | 164 | CX18_AV_AUDIO_SERIAL, 0 }, |
154 | }, | 165 | }, |
155 | .radio_input = { CX18_CARD_INPUT_AUD_TUNER, | 166 | .radio_input = { CX18_CARD_INPUT_AUD_TUNER, |
156 | CX23418_AUDIO_SERIAL, 0 }, | 167 | CX18_AV_AUDIO_SERIAL, 0 }, |
157 | .tuners = { | 168 | .tuners = { |
158 | { .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 }, | 169 | { .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 }, |
159 | }, | 170 | }, |
@@ -183,23 +194,26 @@ static const struct cx18_card_pci_info cx18_pci_mpc718[] = { | |||
183 | static const struct cx18_card cx18_card_mpc718 = { | 194 | static const struct cx18_card cx18_card_mpc718 = { |
184 | .type = CX18_CARD_YUAN_MPC718, | 195 | .type = CX18_CARD_YUAN_MPC718, |
185 | .name = "Yuan MPC718", | 196 | .name = "Yuan MPC718", |
186 | .comment = "Not yet supported!\n", | 197 | .comment = "Some Composite and S-Video inputs are currently working.\n", |
187 | .v4l2_capabilities = 0, | 198 | .v4l2_capabilities = CX18_CAP_ENCODER, |
188 | .hw_audio_ctrl = CX18_HW_CX23418, | 199 | .hw_audio_ctrl = CX18_HW_CX23418, |
189 | .hw_all = CX18_HW_TUNER, | 200 | .hw_all = CX18_HW_TUNER, |
190 | .video_inputs = { | 201 | .video_inputs = { |
191 | { CX18_CARD_INPUT_VID_TUNER, 0, CX23418_COMPOSITE7 }, | 202 | { CX18_CARD_INPUT_VID_TUNER, 0, CX18_AV_COMPOSITE2 }, |
192 | { CX18_CARD_INPUT_SVIDEO1, 1, CX23418_SVIDEO1 }, | 203 | { CX18_CARD_INPUT_SVIDEO1, 1, |
193 | { CX18_CARD_INPUT_COMPOSITE1, 1, CX23418_COMPOSITE3 }, | 204 | CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 }, |
205 | { CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE1 }, | ||
206 | { CX18_CARD_INPUT_SVIDEO2, 2, | ||
207 | CX18_AV_SVIDEO_LUMA7 | CX18_AV_SVIDEO_CHROMA8 }, | ||
208 | { CX18_CARD_INPUT_COMPOSITE2, 2, CX18_AV_COMPOSITE6 }, | ||
209 | { CX18_CARD_INPUT_COMPOSITE3, 2, CX18_AV_COMPOSITE3 }, | ||
194 | }, | 210 | }, |
195 | .audio_inputs = { | 211 | .audio_inputs = { |
196 | { CX18_CARD_INPUT_AUD_TUNER, | 212 | { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 0 }, |
197 | CX23418_AUDIO8, 0 }, | 213 | { CX18_CARD_INPUT_LINE_IN1, CX18_AV_AUDIO_SERIAL, 0 }, |
198 | { CX18_CARD_INPUT_LINE_IN1, | 214 | { CX18_CARD_INPUT_LINE_IN2, CX18_AV_AUDIO_SERIAL, 0 }, |
199 | CX23418_AUDIO_SERIAL, 0 }, | ||
200 | }, | 215 | }, |
201 | .radio_input = { CX18_CARD_INPUT_AUD_TUNER, | 216 | .radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO_SERIAL, 0 }, |
202 | CX23418_AUDIO_SERIAL, 0 }, | ||
203 | .tuners = { | 217 | .tuners = { |
204 | /* XC3028 tuner */ | 218 | /* XC3028 tuner */ |
205 | { .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 }, | 219 | { .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 }, |
diff --git a/drivers/media/video/cx18/cx18-cards.h b/drivers/media/video/cx18/cx18-cards.h index bccb67f0db16..dc2dd945d4c3 100644 --- a/drivers/media/video/cx18/cx18-cards.h +++ b/drivers/media/video/cx18/cx18-cards.h | |||
@@ -36,36 +36,6 @@ | |||
36 | #define CX18_CARD_INPUT_COMPOSITE2 5 | 36 | #define CX18_CARD_INPUT_COMPOSITE2 5 |
37 | #define CX18_CARD_INPUT_COMPOSITE3 6 | 37 | #define CX18_CARD_INPUT_COMPOSITE3 6 |
38 | 38 | ||
39 | enum cx34180_video_input { | ||
40 | /* Composite video inputs In1-In8 */ | ||
41 | CX23418_COMPOSITE1 = 1, | ||
42 | CX23418_COMPOSITE2, | ||
43 | CX23418_COMPOSITE3, | ||
44 | CX23418_COMPOSITE4, | ||
45 | CX23418_COMPOSITE5, | ||
46 | CX23418_COMPOSITE6, | ||
47 | CX23418_COMPOSITE7, | ||
48 | CX23418_COMPOSITE8, | ||
49 | |||
50 | /* S-Video inputs consist of one luma input (In1-In4) ORed with one | ||
51 | chroma input (In5-In8) */ | ||
52 | CX23418_SVIDEO_LUMA1 = 0x10, | ||
53 | CX23418_SVIDEO_LUMA2 = 0x20, | ||
54 | CX23418_SVIDEO_LUMA3 = 0x30, | ||
55 | CX23418_SVIDEO_LUMA4 = 0x40, | ||
56 | CX23418_SVIDEO_CHROMA4 = 0x400, | ||
57 | CX23418_SVIDEO_CHROMA5 = 0x500, | ||
58 | CX23418_SVIDEO_CHROMA6 = 0x600, | ||
59 | CX23418_SVIDEO_CHROMA7 = 0x700, | ||
60 | CX23418_SVIDEO_CHROMA8 = 0x800, | ||
61 | |||
62 | /* S-Video aliases for common luma/chroma combinations */ | ||
63 | CX23418_SVIDEO1 = 0x510, | ||
64 | CX23418_SVIDEO2 = 0x620, | ||
65 | CX23418_SVIDEO3 = 0x730, | ||
66 | CX23418_SVIDEO4 = 0x840, | ||
67 | }; | ||
68 | |||
69 | /* audio inputs */ | 39 | /* audio inputs */ |
70 | #define CX18_CARD_INPUT_AUD_TUNER 1 | 40 | #define CX18_CARD_INPUT_AUD_TUNER 1 |
71 | #define CX18_CARD_INPUT_LINE_IN1 2 | 41 | #define CX18_CARD_INPUT_LINE_IN1 2 |
@@ -75,16 +45,6 @@ enum cx34180_video_input { | |||
75 | #define CX18_CARD_MAX_AUDIO_INPUTS 3 | 45 | #define CX18_CARD_MAX_AUDIO_INPUTS 3 |
76 | #define CX18_CARD_MAX_TUNERS 2 | 46 | #define CX18_CARD_MAX_TUNERS 2 |
77 | 47 | ||
78 | enum cx23418_audio_input { | ||
79 | /* Audio inputs: serial or In4-In8 */ | ||
80 | CX23418_AUDIO_SERIAL, | ||
81 | CX23418_AUDIO4 = 4, | ||
82 | CX23418_AUDIO5, | ||
83 | CX23418_AUDIO6, | ||
84 | CX23418_AUDIO7, | ||
85 | CX23418_AUDIO8, | ||
86 | }; | ||
87 | |||
88 | /* V4L2 capability aliases */ | 48 | /* V4L2 capability aliases */ |
89 | #define CX18_CAP_ENCODER (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_TUNER | \ | 49 | #define CX18_CAP_ENCODER (V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_TUNER | \ |
90 | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE) | 50 | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE) |
@@ -118,6 +78,13 @@ struct cx18_gpio_init { /* set initial GPIO DIR and OUT values */ | |||
118 | u32 initial_value; | 78 | u32 initial_value; |
119 | }; | 79 | }; |
120 | 80 | ||
81 | struct cx18_gpio_i2c_slave_reset { | ||
82 | u32 active_lo_mask; /* GPIO outputs that reset i2c chips when low */ | ||
83 | u32 active_hi_mask; /* GPIO outputs that reset i2c chips when high */ | ||
84 | int msecs_asserted; /* time period reset must remain asserted */ | ||
85 | int msecs_recovery; /* time after deassert for chips to be ready */ | ||
86 | }; | ||
87 | |||
121 | struct cx18_card_tuner { | 88 | struct cx18_card_tuner { |
122 | v4l2_std_id std; /* standard for which the tuner is suitable */ | 89 | v4l2_std_id std; /* standard for which the tuner is suitable */ |
123 | int tuner; /* tuner ID (from tuner.h) */ | 90 | int tuner; /* tuner ID (from tuner.h) */ |
@@ -154,7 +121,8 @@ struct cx18_card { | |||
154 | 121 | ||
155 | /* GPIO card-specific settings */ | 122 | /* GPIO card-specific settings */ |
156 | u8 xceive_pin; /* XCeive tuner GPIO reset pin */ | 123 | u8 xceive_pin; /* XCeive tuner GPIO reset pin */ |
157 | struct cx18_gpio_init gpio_init; | 124 | struct cx18_gpio_init gpio_init; |
125 | struct cx18_gpio_i2c_slave_reset gpio_i2c_slave_reset; | ||
158 | 126 | ||
159 | struct cx18_card_tuner tuners[CX18_CARD_MAX_TUNERS]; | 127 | struct cx18_card_tuner tuners[CX18_CARD_MAX_TUNERS]; |
160 | struct cx18_card_tuner_i2c *i2c; | 128 | struct cx18_card_tuner_i2c *i2c; |
diff --git a/drivers/media/video/cx18/cx18-dvb.c b/drivers/media/video/cx18/cx18-dvb.c index c9744173f969..cae38985b131 100644 --- a/drivers/media/video/cx18/cx18-dvb.c +++ b/drivers/media/video/cx18/cx18-dvb.c | |||
@@ -69,11 +69,21 @@ static int cx18_dvb_start_feed(struct dvb_demux_feed *feed) | |||
69 | struct dvb_demux *demux = feed->demux; | 69 | struct dvb_demux *demux = feed->demux; |
70 | struct cx18_stream *stream = (struct cx18_stream *) demux->priv; | 70 | struct cx18_stream *stream = (struct cx18_stream *) demux->priv; |
71 | struct cx18 *cx = stream->cx; | 71 | struct cx18 *cx = stream->cx; |
72 | int ret = -EINVAL; | 72 | int ret; |
73 | u32 v; | 73 | u32 v; |
74 | 74 | ||
75 | CX18_DEBUG_INFO("Start feed: pid = 0x%x index = %d\n", | 75 | CX18_DEBUG_INFO("Start feed: pid = 0x%x index = %d\n", |
76 | feed->pid, feed->index); | 76 | feed->pid, feed->index); |
77 | |||
78 | mutex_lock(&cx->serialize_lock); | ||
79 | ret = cx18_init_on_first_open(cx); | ||
80 | mutex_unlock(&cx->serialize_lock); | ||
81 | if (ret) { | ||
82 | CX18_ERR("Failed to initialize firmware starting DVB feed\n"); | ||
83 | return ret; | ||
84 | } | ||
85 | ret = -EINVAL; | ||
86 | |||
77 | switch (cx->card->type) { | 87 | switch (cx->card->type) { |
78 | case CX18_CARD_HVR_1600_ESMT: | 88 | case CX18_CARD_HVR_1600_ESMT: |
79 | case CX18_CARD_HVR_1600_SAMSUNG: | 89 | case CX18_CARD_HVR_1600_SAMSUNG: |
@@ -101,6 +111,11 @@ static int cx18_dvb_start_feed(struct dvb_demux_feed *feed) | |||
101 | if (stream->dvb.feeding++ == 0) { | 111 | if (stream->dvb.feeding++ == 0) { |
102 | CX18_DEBUG_INFO("Starting Transport DMA\n"); | 112 | CX18_DEBUG_INFO("Starting Transport DMA\n"); |
103 | ret = cx18_start_v4l2_encode_stream(stream); | 113 | ret = cx18_start_v4l2_encode_stream(stream); |
114 | if (ret < 0) { | ||
115 | CX18_DEBUG_INFO( | ||
116 | "Failed to start Transport DMA\n"); | ||
117 | stream->dvb.feeding--; | ||
118 | } | ||
104 | } else | 119 | } else |
105 | ret = 0; | 120 | ret = 0; |
106 | mutex_unlock(&stream->dvb.feedlock); | 121 | mutex_unlock(&stream->dvb.feedlock); |
diff --git a/drivers/media/video/cx18/cx18-gpio.c b/drivers/media/video/cx18/cx18-gpio.c index ceb63653c926..b302833f6f9d 100644 --- a/drivers/media/video/cx18/cx18-gpio.c +++ b/drivers/media/video/cx18/cx18-gpio.c | |||
@@ -53,10 +53,34 @@ static void gpio_write(struct cx18 *cx) | |||
53 | write_reg(((dir & 0xffff) << 16) | (val & 0xffff), | 53 | write_reg(((dir & 0xffff) << 16) | (val & 0xffff), |
54 | CX18_REG_GPIO_OUT1); | 54 | CX18_REG_GPIO_OUT1); |
55 | write_reg(dir & 0xffff0000, CX18_REG_GPIO_DIR2); | 55 | write_reg(dir & 0xffff0000, CX18_REG_GPIO_DIR2); |
56 | write_reg((dir & 0xffff0000) | ((val & 0xffff0000) >> 16), | 56 | write_reg_sync((dir & 0xffff0000) | ((val & 0xffff0000) >> 16), |
57 | CX18_REG_GPIO_OUT2); | 57 | CX18_REG_GPIO_OUT2); |
58 | } | 58 | } |
59 | 59 | ||
60 | void cx18_reset_i2c_slaves_gpio(struct cx18 *cx) | ||
61 | { | ||
62 | const struct cx18_gpio_i2c_slave_reset *p; | ||
63 | |||
64 | p = &cx->card->gpio_i2c_slave_reset; | ||
65 | |||
66 | if ((p->active_lo_mask | p->active_hi_mask) == 0) | ||
67 | return; | ||
68 | |||
69 | /* Assuming that the masks are a subset of the bits in gpio_dir */ | ||
70 | |||
71 | /* Assert */ | ||
72 | cx->gpio_val = | ||
73 | (cx->gpio_val | p->active_hi_mask) & ~(p->active_lo_mask); | ||
74 | gpio_write(cx); | ||
75 | schedule_timeout_uninterruptible(msecs_to_jiffies(p->msecs_asserted)); | ||
76 | |||
77 | /* Deassert */ | ||
78 | cx->gpio_val = | ||
79 | (cx->gpio_val | p->active_lo_mask) & ~(p->active_hi_mask); | ||
80 | gpio_write(cx); | ||
81 | schedule_timeout_uninterruptible(msecs_to_jiffies(p->msecs_recovery)); | ||
82 | } | ||
83 | |||
60 | void cx18_gpio_init(struct cx18 *cx) | 84 | void cx18_gpio_init(struct cx18 *cx) |
61 | { | 85 | { |
62 | cx->gpio_dir = cx->card->gpio_init.direction; | 86 | cx->gpio_dir = cx->card->gpio_init.direction; |
diff --git a/drivers/media/video/cx18/cx18-gpio.h b/drivers/media/video/cx18/cx18-gpio.h index 41bac8856b50..525c328f748a 100644 --- a/drivers/media/video/cx18/cx18-gpio.h +++ b/drivers/media/video/cx18/cx18-gpio.h | |||
@@ -21,4 +21,5 @@ | |||
21 | */ | 21 | */ |
22 | 22 | ||
23 | void cx18_gpio_init(struct cx18 *cx); | 23 | void cx18_gpio_init(struct cx18 *cx); |
24 | void cx18_reset_i2c_slaves_gpio(struct cx18 *cx); | ||
24 | int cx18_reset_tuner_gpio(void *dev, int cmd, int value); | 25 | int cx18_reset_tuner_gpio(void *dev, int cmd, int value); |
diff --git a/drivers/media/video/cx18/cx18-i2c.c b/drivers/media/video/cx18/cx18-i2c.c index 1d6c51a75313..680bc4e35b79 100644 --- a/drivers/media/video/cx18/cx18-i2c.c +++ b/drivers/media/video/cx18/cx18-i2c.c | |||
@@ -405,6 +405,8 @@ int init_cx18_i2c(struct cx18 *cx) | |||
405 | cx18_setscl(&cx->i2c_algo_cb_data[1], 1); | 405 | cx18_setscl(&cx->i2c_algo_cb_data[1], 1); |
406 | cx18_setsda(&cx->i2c_algo_cb_data[1], 1); | 406 | cx18_setsda(&cx->i2c_algo_cb_data[1], 1); |
407 | 407 | ||
408 | cx18_reset_i2c_slaves_gpio(cx); | ||
409 | |||
408 | return i2c_bit_add_bus(&cx->i2c_adap[0]) || | 410 | return i2c_bit_add_bus(&cx->i2c_adap[0]) || |
409 | i2c_bit_add_bus(&cx->i2c_adap[1]); | 411 | i2c_bit_add_bus(&cx->i2c_adap[1]); |
410 | } | 412 | } |
diff --git a/drivers/media/video/cx25840/cx25840-core.c b/drivers/media/video/cx25840/cx25840-core.c index 607efdcd22f8..1da6f134888d 100644 --- a/drivers/media/video/cx25840/cx25840-core.c +++ b/drivers/media/video/cx25840/cx25840-core.c | |||
@@ -433,7 +433,7 @@ static int set_input(struct i2c_client *client, enum cx25840_video_input vid_inp | |||
433 | int chroma = vid_input & 0xf00; | 433 | int chroma = vid_input & 0xf00; |
434 | 434 | ||
435 | if ((vid_input & ~0xff0) || | 435 | if ((vid_input & ~0xff0) || |
436 | luma < CX25840_SVIDEO_LUMA1 || luma > CX25840_SVIDEO_LUMA4 || | 436 | luma < CX25840_SVIDEO_LUMA1 || luma > CX25840_SVIDEO_LUMA8 || |
437 | chroma < CX25840_SVIDEO_CHROMA4 || chroma > CX25840_SVIDEO_CHROMA8) { | 437 | chroma < CX25840_SVIDEO_CHROMA4 || chroma > CX25840_SVIDEO_CHROMA8) { |
438 | v4l_err(client, "0x%04x is not a valid video input!\n", | 438 | v4l_err(client, "0x%04x is not a valid video input!\n", |
439 | vid_input); | 439 | vid_input); |
diff --git a/drivers/media/video/cx88/cx88-alsa.c b/drivers/media/video/cx88/cx88-alsa.c index e976fc6bef7c..80c8883e54b5 100644 --- a/drivers/media/video/cx88/cx88-alsa.c +++ b/drivers/media/video/cx88/cx88-alsa.c | |||
@@ -332,6 +332,12 @@ static int snd_cx88_pcm_open(struct snd_pcm_substream *substream) | |||
332 | struct snd_pcm_runtime *runtime = substream->runtime; | 332 | struct snd_pcm_runtime *runtime = substream->runtime; |
333 | int err; | 333 | int err; |
334 | 334 | ||
335 | if (!chip) { | ||
336 | printk(KERN_ERR "BUG: cx88 can't find device struct." | ||
337 | " Can't proceed with open\n"); | ||
338 | return -ENODEV; | ||
339 | } | ||
340 | |||
335 | err = snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIODS); | 341 | err = snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIODS); |
336 | if (err < 0) | 342 | if (err < 0) |
337 | goto _error; | 343 | goto _error; |
diff --git a/drivers/media/video/em28xx/em28xx-audio.c b/drivers/media/video/em28xx/em28xx-audio.c index 92b2a6db4fdc..3c006103c1eb 100644 --- a/drivers/media/video/em28xx/em28xx-audio.c +++ b/drivers/media/video/em28xx/em28xx-audio.c | |||
@@ -268,6 +268,12 @@ static int snd_em28xx_capture_open(struct snd_pcm_substream *substream) | |||
268 | 268 | ||
269 | dprintk("opening device and trying to acquire exclusive lock\n"); | 269 | dprintk("opening device and trying to acquire exclusive lock\n"); |
270 | 270 | ||
271 | if (!dev) { | ||
272 | printk(KERN_ERR "BUG: em28xx can't find device struct." | ||
273 | " Can't proceed with open\n"); | ||
274 | return -ENODEV; | ||
275 | } | ||
276 | |||
271 | /* Sets volume, mute, etc */ | 277 | /* Sets volume, mute, etc */ |
272 | 278 | ||
273 | dev->mute = 0; | 279 | dev->mute = 0; |
@@ -415,6 +421,12 @@ static int em28xx_audio_init(struct em28xx *dev) | |||
415 | static int devnr; | 421 | static int devnr; |
416 | int ret, err; | 422 | int ret, err; |
417 | 423 | ||
424 | if (dev->has_audio_class) { | ||
425 | /* This device does not support the extension (in this case | ||
426 | the device is expecting the snd-usb-audio module */ | ||
427 | return 0; | ||
428 | } | ||
429 | |||
418 | printk(KERN_INFO "em28xx-audio.c: probing for em28x1 " | 430 | printk(KERN_INFO "em28xx-audio.c: probing for em28x1 " |
419 | "non standard usbaudio\n"); | 431 | "non standard usbaudio\n"); |
420 | printk(KERN_INFO "em28xx-audio.c: Copyright (C) 2006 Markus " | 432 | printk(KERN_INFO "em28xx-audio.c: Copyright (C) 2006 Markus " |
@@ -458,6 +470,12 @@ static int em28xx_audio_fini(struct em28xx *dev) | |||
458 | if (dev == NULL) | 470 | if (dev == NULL) |
459 | return 0; | 471 | return 0; |
460 | 472 | ||
473 | if (dev->has_audio_class) { | ||
474 | /* This device does not support the extension (in this case | ||
475 | the device is expecting the snd-usb-audio module */ | ||
476 | return 0; | ||
477 | } | ||
478 | |||
461 | if (dev->adev) { | 479 | if (dev->adev) { |
462 | snd_card_free(dev->adev->sndcard); | 480 | snd_card_free(dev->adev->sndcard); |
463 | kfree(dev->adev); | 481 | kfree(dev->adev); |
diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c index 3e4f3c7e92e7..8cbda43727c3 100644 --- a/drivers/media/video/em28xx/em28xx-cards.c +++ b/drivers/media/video/em28xx/em28xx-cards.c | |||
@@ -157,6 +157,7 @@ struct em28xx_board em28xx_boards[] = { | |||
157 | .tda9887_conf = TDA9887_PRESENT, | 157 | .tda9887_conf = TDA9887_PRESENT, |
158 | .tuner_type = TUNER_XC2028, | 158 | .tuner_type = TUNER_XC2028, |
159 | .mts_firmware = 1, | 159 | .mts_firmware = 1, |
160 | .has_dvb = 1, | ||
160 | .decoder = EM28XX_TVP5150, | 161 | .decoder = EM28XX_TVP5150, |
161 | .input = { { | 162 | .input = { { |
162 | .type = EM28XX_VMUX_TELEVISION, | 163 | .type = EM28XX_VMUX_TELEVISION, |
@@ -524,6 +525,9 @@ void em28xx_pre_card_setup(struct em28xx *dev) | |||
524 | rc = em28xx_read_reg(dev, EM28XX_R0A_CHIPID); | 525 | rc = em28xx_read_reg(dev, EM28XX_R0A_CHIPID); |
525 | if (rc > 0) { | 526 | if (rc > 0) { |
526 | switch (rc) { | 527 | switch (rc) { |
528 | case CHIP_ID_EM2860: | ||
529 | em28xx_info("chip ID is em2860\n"); | ||
530 | break; | ||
527 | case CHIP_ID_EM2883: | 531 | case CHIP_ID_EM2883: |
528 | em28xx_info("chip ID is em2882/em2883\n"); | 532 | em28xx_info("chip ID is em2882/em2883\n"); |
529 | dev->wait_after_write = 0; | 533 | dev->wait_after_write = 0; |
diff --git a/drivers/media/video/em28xx/em28xx-dvb.c b/drivers/media/video/em28xx/em28xx-dvb.c index 8cf4983f0039..0b2333ee07f8 100644 --- a/drivers/media/video/em28xx/em28xx-dvb.c +++ b/drivers/media/video/em28xx/em28xx-dvb.c | |||
@@ -382,6 +382,11 @@ static int dvb_init(struct em28xx *dev) | |||
382 | int result = 0; | 382 | int result = 0; |
383 | struct em28xx_dvb *dvb; | 383 | struct em28xx_dvb *dvb; |
384 | 384 | ||
385 | if (!dev->has_dvb) { | ||
386 | /* This device does not support the extension */ | ||
387 | return 0; | ||
388 | } | ||
389 | |||
385 | dvb = kzalloc(sizeof(struct em28xx_dvb), GFP_KERNEL); | 390 | dvb = kzalloc(sizeof(struct em28xx_dvb), GFP_KERNEL); |
386 | 391 | ||
387 | if (dvb == NULL) { | 392 | if (dvb == NULL) { |
@@ -444,6 +449,11 @@ out_free: | |||
444 | 449 | ||
445 | static int dvb_fini(struct em28xx *dev) | 450 | static int dvb_fini(struct em28xx *dev) |
446 | { | 451 | { |
452 | if (!dev->has_dvb) { | ||
453 | /* This device does not support the extension */ | ||
454 | return 0; | ||
455 | } | ||
456 | |||
447 | if (dev->dvb) { | 457 | if (dev->dvb) { |
448 | unregister_dvb(dev->dvb); | 458 | unregister_dvb(dev->dvb); |
449 | dev->dvb = NULL; | 459 | dev->dvb = NULL; |
diff --git a/drivers/media/video/em28xx/em28xx-reg.h b/drivers/media/video/em28xx/em28xx-reg.h index 9058bed07953..fac1ab23f621 100644 --- a/drivers/media/video/em28xx/em28xx-reg.h +++ b/drivers/media/video/em28xx/em28xx-reg.h | |||
@@ -84,5 +84,6 @@ | |||
84 | 84 | ||
85 | /* FIXME: Need to be populated with the other chip ID's */ | 85 | /* FIXME: Need to be populated with the other chip ID's */ |
86 | enum em28xx_chip_id { | 86 | enum em28xx_chip_id { |
87 | CHIP_ID_EM2860 = 34, | ||
87 | CHIP_ID_EM2883 = 36, | 88 | CHIP_ID_EM2883 = 36, |
88 | }; | 89 | }; |
diff --git a/drivers/media/video/em28xx/em28xx-video.c b/drivers/media/video/em28xx/em28xx-video.c index fb163ecd9216..285bc62bbe46 100644 --- a/drivers/media/video/em28xx/em28xx-video.c +++ b/drivers/media/video/em28xx/em28xx-video.c | |||
@@ -1848,32 +1848,28 @@ static DEFINE_MUTEX(em28xx_extension_devlist_lock); | |||
1848 | 1848 | ||
1849 | int em28xx_register_extension(struct em28xx_ops *ops) | 1849 | int em28xx_register_extension(struct em28xx_ops *ops) |
1850 | { | 1850 | { |
1851 | struct em28xx *h, *dev = NULL; | 1851 | struct em28xx *dev = NULL; |
1852 | |||
1853 | list_for_each_entry(h, &em28xx_devlist, devlist) | ||
1854 | dev = h; | ||
1855 | 1852 | ||
1856 | mutex_lock(&em28xx_extension_devlist_lock); | 1853 | mutex_lock(&em28xx_extension_devlist_lock); |
1857 | list_add_tail(&ops->next, &em28xx_extension_devlist); | 1854 | list_add_tail(&ops->next, &em28xx_extension_devlist); |
1858 | if (dev) | 1855 | list_for_each_entry(dev, &em28xx_devlist, devlist) { |
1859 | ops->init(dev); | 1856 | if (dev) |
1860 | 1857 | ops->init(dev); | |
1858 | } | ||
1861 | printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name); | 1859 | printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name); |
1862 | mutex_unlock(&em28xx_extension_devlist_lock); | 1860 | mutex_unlock(&em28xx_extension_devlist_lock); |
1863 | |||
1864 | return 0; | 1861 | return 0; |
1865 | } | 1862 | } |
1866 | EXPORT_SYMBOL(em28xx_register_extension); | 1863 | EXPORT_SYMBOL(em28xx_register_extension); |
1867 | 1864 | ||
1868 | void em28xx_unregister_extension(struct em28xx_ops *ops) | 1865 | void em28xx_unregister_extension(struct em28xx_ops *ops) |
1869 | { | 1866 | { |
1870 | struct em28xx *h, *dev = NULL; | 1867 | struct em28xx *dev = NULL; |
1871 | |||
1872 | list_for_each_entry(h, &em28xx_devlist, devlist) | ||
1873 | dev = h; | ||
1874 | 1868 | ||
1875 | if (dev) | 1869 | list_for_each_entry(dev, &em28xx_devlist, devlist) { |
1876 | ops->fini(dev); | 1870 | if (dev) |
1871 | ops->fini(dev); | ||
1872 | } | ||
1877 | 1873 | ||
1878 | mutex_lock(&em28xx_extension_devlist_lock); | 1874 | mutex_lock(&em28xx_extension_devlist_lock); |
1879 | printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name); | 1875 | printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name); |
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c index 7cc8e9b19fb7..5ec5bb9a94d2 100644 --- a/drivers/media/video/pxa_camera.c +++ b/drivers/media/video/pxa_camera.c | |||
@@ -1019,12 +1019,12 @@ static int pxa_camera_probe(struct platform_device *pdev) | |||
1019 | struct pxa_camera_dev *pcdev; | 1019 | struct pxa_camera_dev *pcdev; |
1020 | struct resource *res; | 1020 | struct resource *res; |
1021 | void __iomem *base; | 1021 | void __iomem *base; |
1022 | unsigned int irq; | 1022 | int irq; |
1023 | int err = 0; | 1023 | int err = 0; |
1024 | 1024 | ||
1025 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1025 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1026 | irq = platform_get_irq(pdev, 0); | 1026 | irq = platform_get_irq(pdev, 0); |
1027 | if (!res || !irq) { | 1027 | if (!res || irq < 0) { |
1028 | err = -ENODEV; | 1028 | err = -ENODEV; |
1029 | goto exit; | 1029 | goto exit; |
1030 | } | 1030 | } |
diff --git a/drivers/media/video/saa7134/saa7134-alsa.c b/drivers/media/video/saa7134/saa7134-alsa.c index ba3082422a01..f118de6e3672 100644 --- a/drivers/media/video/saa7134/saa7134-alsa.c +++ b/drivers/media/video/saa7134/saa7134-alsa.c | |||
@@ -613,9 +613,15 @@ static int snd_card_saa7134_capture_open(struct snd_pcm_substream * substream) | |||
613 | struct snd_pcm_runtime *runtime = substream->runtime; | 613 | struct snd_pcm_runtime *runtime = substream->runtime; |
614 | snd_card_saa7134_pcm_t *pcm; | 614 | snd_card_saa7134_pcm_t *pcm; |
615 | snd_card_saa7134_t *saa7134 = snd_pcm_substream_chip(substream); | 615 | snd_card_saa7134_t *saa7134 = snd_pcm_substream_chip(substream); |
616 | struct saa7134_dev *dev = saa7134->dev; | 616 | struct saa7134_dev *dev; |
617 | int amux, err; | 617 | int amux, err; |
618 | 618 | ||
619 | if (!saa7134) { | ||
620 | printk(KERN_ERR "BUG: saa7134 can't find device struct." | ||
621 | " Can't proceed with open\n"); | ||
622 | return -ENODEV; | ||
623 | } | ||
624 | dev = saa7134->dev; | ||
619 | mutex_lock(&dev->dmasound.lock); | 625 | mutex_lock(&dev->dmasound.lock); |
620 | 626 | ||
621 | dev->dmasound.read_count = 0; | 627 | dev->dmasound.read_count = 0; |
diff --git a/drivers/media/video/saa7134/saa7134-cards.c b/drivers/media/video/saa7134/saa7134-cards.c index b111903aa322..2618cfa592e7 100644 --- a/drivers/media/video/saa7134/saa7134-cards.c +++ b/drivers/media/video/saa7134/saa7134-cards.c | |||
@@ -4114,11 +4114,7 @@ struct saa7134_board saa7134_boards[] = { | |||
4114 | .radio_type = UNSET, | 4114 | .radio_type = UNSET, |
4115 | .tuner_addr = ADDR_UNSET, | 4115 | .tuner_addr = ADDR_UNSET, |
4116 | .radio_addr = ADDR_UNSET, | 4116 | .radio_addr = ADDR_UNSET, |
4117 | /* | ||
4118 | TODO: | ||
4119 | .mpeg = SAA7134_MPEG_DVB, | 4117 | .mpeg = SAA7134_MPEG_DVB, |
4120 | */ | ||
4121 | |||
4122 | .inputs = {{ | 4118 | .inputs = {{ |
4123 | .name = name_tv, | 4119 | .name = name_tv, |
4124 | .vmux = 1, | 4120 | .vmux = 1, |
@@ -4157,7 +4153,7 @@ struct saa7134_board saa7134_boards[] = { | |||
4157 | } }, | 4153 | } }, |
4158 | .radio = { | 4154 | .radio = { |
4159 | .name = name_radio, | 4155 | .name = name_radio, |
4160 | .amux = LINE1, | 4156 | .amux = TV, |
4161 | }, | 4157 | }, |
4162 | }, | 4158 | }, |
4163 | [SAA7134_BOARD_AVERMEDIA_M115] = { | 4159 | [SAA7134_BOARD_AVERMEDIA_M115] = { |
@@ -4167,6 +4163,7 @@ struct saa7134_board saa7134_boards[] = { | |||
4167 | .radio_type = UNSET, | 4163 | .radio_type = UNSET, |
4168 | .tuner_addr = ADDR_UNSET, | 4164 | .tuner_addr = ADDR_UNSET, |
4169 | .radio_addr = ADDR_UNSET, | 4165 | .radio_addr = ADDR_UNSET, |
4166 | .mpeg = SAA7134_MPEG_DVB, | ||
4170 | .inputs = {{ | 4167 | .inputs = {{ |
4171 | .name = name_tv, | 4168 | .name = name_tv, |
4172 | .vmux = 1, | 4169 | .vmux = 1, |
@@ -5351,22 +5348,21 @@ static int saa7134_xc2028_callback(struct saa7134_dev *dev, | |||
5351 | { | 5348 | { |
5352 | switch (command) { | 5349 | switch (command) { |
5353 | case XC2028_TUNER_RESET: | 5350 | case XC2028_TUNER_RESET: |
5354 | saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x06e20000, 0x06e20000); | 5351 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x00008000, 0x00000000); |
5355 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x06a20000, 0x06a20000); | 5352 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x00008000, 0x00008000); |
5356 | mdelay(250); | 5353 | switch (dev->board) { |
5357 | saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x06e20000, 0); | 5354 | case SAA7134_BOARD_AVERMEDIA_CARDBUS_506: |
5358 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x06a20000, 0); | 5355 | saa7134_set_gpio(dev, 23, 0); |
5359 | mdelay(250); | 5356 | msleep(10); |
5360 | saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x06e20000, 0x06e20000); | 5357 | saa7134_set_gpio(dev, 23, 1); |
5361 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x06a20000, 0x06a20000); | 5358 | break; |
5362 | mdelay(250); | 5359 | case SAA7134_BOARD_AVERMEDIA_A16D: |
5363 | saa_andorl(SAA7133_ANALOG_IO_SELECT >> 2, 0x02, 0x02); | 5360 | saa7134_set_gpio(dev, 21, 0); |
5364 | saa_andorl(SAA7134_ANALOG_IN_CTRL1 >> 2, 0x81, 0x81); | 5361 | msleep(10); |
5365 | saa_andorl(SAA7134_AUDIO_CLOCK0 >> 2, 0x03187de7, 0x03187de7); | 5362 | saa7134_set_gpio(dev, 21, 1); |
5366 | saa_andorl(SAA7134_AUDIO_PLL_CTRL >> 2, 0x03, 0x03); | 5363 | break; |
5367 | saa_andorl(SAA7134_AUDIO_CLOCKS_PER_FIELD0 >> 2, | 5364 | } |
5368 | 0x0001e000, 0x0001e000); | 5365 | return 0; |
5369 | return 0; | ||
5370 | } | 5366 | } |
5371 | return -EINVAL; | 5367 | return -EINVAL; |
5372 | } | 5368 | } |
@@ -5553,9 +5549,7 @@ int saa7134_board_init1(struct saa7134_dev *dev) | |||
5553 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x08000000, 0x00000000); | 5549 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x08000000, 0x00000000); |
5554 | break; | 5550 | break; |
5555 | case SAA7134_BOARD_AVERMEDIA_CARDBUS: | 5551 | case SAA7134_BOARD_AVERMEDIA_CARDBUS: |
5556 | case SAA7134_BOARD_AVERMEDIA_CARDBUS_506: | ||
5557 | case SAA7134_BOARD_AVERMEDIA_M115: | 5552 | case SAA7134_BOARD_AVERMEDIA_M115: |
5558 | case SAA7134_BOARD_AVERMEDIA_A16D: | ||
5559 | /* power-down tuner chip */ | 5553 | /* power-down tuner chip */ |
5560 | saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0xffffffff, 0); | 5554 | saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0xffffffff, 0); |
5561 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0xffffffff, 0); | 5555 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0xffffffff, 0); |
@@ -5565,6 +5559,18 @@ int saa7134_board_init1(struct saa7134_dev *dev) | |||
5565 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0xffffffff, 0xffffffff); | 5559 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0xffffffff, 0xffffffff); |
5566 | msleep(10); | 5560 | msleep(10); |
5567 | break; | 5561 | break; |
5562 | case SAA7134_BOARD_AVERMEDIA_CARDBUS_506: | ||
5563 | saa7134_set_gpio(dev, 23, 0); | ||
5564 | msleep(10); | ||
5565 | saa7134_set_gpio(dev, 23, 1); | ||
5566 | break; | ||
5567 | case SAA7134_BOARD_AVERMEDIA_A16D: | ||
5568 | saa7134_set_gpio(dev, 21, 0); | ||
5569 | msleep(10); | ||
5570 | saa7134_set_gpio(dev, 21, 1); | ||
5571 | msleep(1); | ||
5572 | dev->has_remote = SAA7134_REMOTE_GPIO; | ||
5573 | break; | ||
5568 | case SAA7134_BOARD_BEHOLD_COLUMBUS_TVFM: | 5574 | case SAA7134_BOARD_BEHOLD_COLUMBUS_TVFM: |
5569 | /* power-down tuner chip */ | 5575 | /* power-down tuner chip */ |
5570 | saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x000A8004, 0x000A8004); | 5576 | saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x000A8004, 0x000A8004); |
@@ -5615,7 +5621,8 @@ int saa7134_board_init1(struct saa7134_dev *dev) | |||
5615 | saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x80040100, 0x80040100); | 5621 | saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x80040100, 0x80040100); |
5616 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x80040100, 0x00040100); | 5622 | saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x80040100, 0x00040100); |
5617 | printk("%s: %s: hybrid analog/dvb card\n" | 5623 | printk("%s: %s: hybrid analog/dvb card\n" |
5618 | "%s: Sorry, only the analog inputs are supported for now.\n", | 5624 | "%s: Sorry, only analog s-video and composite input " |
5625 | "are supported for now.\n", | ||
5619 | dev->name, card(dev).name, dev->name); | 5626 | dev->name, card(dev).name, dev->name); |
5620 | break; | 5627 | break; |
5621 | } | 5628 | } |
@@ -5675,6 +5682,7 @@ static void saa7134_tuner_setup(struct saa7134_dev *dev) | |||
5675 | 5682 | ||
5676 | switch (dev->board) { | 5683 | switch (dev->board) { |
5677 | case SAA7134_BOARD_AVERMEDIA_A16D: | 5684 | case SAA7134_BOARD_AVERMEDIA_A16D: |
5685 | case SAA7134_BOARD_AVERMEDIA_CARDBUS_506: | ||
5678 | ctl.demod = XC3028_FE_ZARLINK456; | 5686 | ctl.demod = XC3028_FE_ZARLINK456; |
5679 | break; | 5687 | break; |
5680 | default: | 5688 | default: |
diff --git a/drivers/media/video/saa7134/saa7134-dvb.c b/drivers/media/video/saa7134/saa7134-dvb.c index 469f93aac008..341b101b0357 100644 --- a/drivers/media/video/saa7134/saa7134-dvb.c +++ b/drivers/media/video/saa7134/saa7134-dvb.c | |||
@@ -153,12 +153,12 @@ static int mt352_aver777_init(struct dvb_frontend* fe) | |||
153 | return 0; | 153 | return 0; |
154 | } | 154 | } |
155 | 155 | ||
156 | static int mt352_aver_a16d_init(struct dvb_frontend *fe) | 156 | static int mt352_avermedia_xc3028_init(struct dvb_frontend *fe) |
157 | { | 157 | { |
158 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x2d }; | 158 | static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x2d }; |
159 | static u8 reset [] = { RESET, 0x80 }; | 159 | static u8 reset [] = { RESET, 0x80 }; |
160 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; | 160 | static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 }; |
161 | static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0xa0 }; | 161 | static u8 agc_cfg [] = { AGC_TARGET, 0xe }; |
162 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 }; | 162 | static u8 capt_range_cfg[] = { CAPT_RANGE, 0x33 }; |
163 | 163 | ||
164 | mt352_write(fe, clock_config, sizeof(clock_config)); | 164 | mt352_write(fe, clock_config, sizeof(clock_config)); |
@@ -167,12 +167,9 @@ static int mt352_aver_a16d_init(struct dvb_frontend *fe) | |||
167 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); | 167 | mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg)); |
168 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); | 168 | mt352_write(fe, agc_cfg, sizeof(agc_cfg)); |
169 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); | 169 | mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg)); |
170 | |||
171 | return 0; | 170 | return 0; |
172 | } | 171 | } |
173 | 172 | ||
174 | |||
175 | |||
176 | static int mt352_pinnacle_tuner_set_params(struct dvb_frontend* fe, | 173 | static int mt352_pinnacle_tuner_set_params(struct dvb_frontend* fe, |
177 | struct dvb_frontend_parameters* params) | 174 | struct dvb_frontend_parameters* params) |
178 | { | 175 | { |
@@ -215,14 +212,10 @@ static struct mt352_config avermedia_777 = { | |||
215 | .demod_init = mt352_aver777_init, | 212 | .demod_init = mt352_aver777_init, |
216 | }; | 213 | }; |
217 | 214 | ||
218 | static struct mt352_config avermedia_16d = { | 215 | static struct mt352_config avermedia_xc3028_mt352_dev = { |
219 | .demod_address = 0xf, | ||
220 | .demod_init = mt352_aver_a16d_init, | ||
221 | }; | ||
222 | |||
223 | static struct mt352_config avermedia_e506r_mt352_dev = { | ||
224 | .demod_address = (0x1e >> 1), | 216 | .demod_address = (0x1e >> 1), |
225 | .no_tuner = 1, | 217 | .no_tuner = 1, |
218 | .demod_init = mt352_avermedia_xc3028_init, | ||
226 | }; | 219 | }; |
227 | 220 | ||
228 | /* ================================================================== | 221 | /* ================================================================== |
@@ -975,9 +968,10 @@ static int dvb_init(struct saa7134_dev *dev) | |||
975 | } | 968 | } |
976 | break; | 969 | break; |
977 | case SAA7134_BOARD_AVERMEDIA_A16D: | 970 | case SAA7134_BOARD_AVERMEDIA_A16D: |
978 | dprintk("avertv A16D dvb setup\n"); | 971 | dprintk("AverMedia A16D dvb setup\n"); |
979 | dev->dvb.frontend = dvb_attach(mt352_attach, &avermedia_16d, | 972 | dev->dvb.frontend = dvb_attach(mt352_attach, |
980 | &dev->i2c_adap); | 973 | &avermedia_xc3028_mt352_dev, |
974 | &dev->i2c_adap); | ||
981 | attach_xc3028 = 1; | 975 | attach_xc3028 = 1; |
982 | break; | 976 | break; |
983 | case SAA7134_BOARD_MD7134: | 977 | case SAA7134_BOARD_MD7134: |
@@ -1091,7 +1085,8 @@ static int dvb_init(struct saa7134_dev *dev) | |||
1091 | ads_tech_duo_config.tuner_address); | 1085 | ads_tech_duo_config.tuner_address); |
1092 | goto dettach_frontend; | 1086 | goto dettach_frontend; |
1093 | } | 1087 | } |
1094 | } | 1088 | } else |
1089 | wprintk("failed to attach tda10046\n"); | ||
1095 | break; | 1090 | break; |
1096 | case SAA7134_BOARD_TEVION_DVBT_220RF: | 1091 | case SAA7134_BOARD_TEVION_DVBT_220RF: |
1097 | if (configure_tda827x_fe(dev, &tevion_dvbt220rf_config, | 1092 | if (configure_tda827x_fe(dev, &tevion_dvbt220rf_config, |
@@ -1260,11 +1255,14 @@ static int dvb_init(struct saa7134_dev *dev) | |||
1260 | goto dettach_frontend; | 1255 | goto dettach_frontend; |
1261 | break; | 1256 | break; |
1262 | case SAA7134_BOARD_AVERMEDIA_CARDBUS_506: | 1257 | case SAA7134_BOARD_AVERMEDIA_CARDBUS_506: |
1258 | dprintk("AverMedia E506R dvb setup\n"); | ||
1259 | saa7134_set_gpio(dev, 25, 0); | ||
1260 | msleep(10); | ||
1261 | saa7134_set_gpio(dev, 25, 1); | ||
1263 | dev->dvb.frontend = dvb_attach(mt352_attach, | 1262 | dev->dvb.frontend = dvb_attach(mt352_attach, |
1264 | &avermedia_e506r_mt352_dev, | 1263 | &avermedia_xc3028_mt352_dev, |
1265 | &dev->i2c_adap); | 1264 | &dev->i2c_adap); |
1266 | attach_xc3028 = 1; | 1265 | attach_xc3028 = 1; |
1267 | break; | ||
1268 | case SAA7134_BOARD_MD7134_BRIDGE_2: | 1266 | case SAA7134_BOARD_MD7134_BRIDGE_2: |
1269 | dev->dvb.frontend = dvb_attach(tda10086_attach, | 1267 | dev->dvb.frontend = dvb_attach(tda10086_attach, |
1270 | &sd1878_4m, &dev->i2c_adap); | 1268 | &sd1878_4m, &dev->i2c_adap); |
@@ -1338,7 +1336,8 @@ static int dvb_init(struct saa7134_dev *dev) | |||
1338 | return ret; | 1336 | return ret; |
1339 | 1337 | ||
1340 | dettach_frontend: | 1338 | dettach_frontend: |
1341 | dvb_frontend_detach(dev->dvb.frontend); | 1339 | if (dev->dvb.frontend) |
1340 | dvb_frontend_detach(dev->dvb.frontend); | ||
1342 | dev->dvb.frontend = NULL; | 1341 | dev->dvb.frontend = NULL; |
1343 | 1342 | ||
1344 | return -1; | 1343 | return -1; |
diff --git a/drivers/media/video/saa7134/saa7134-empress.c b/drivers/media/video/saa7134/saa7134-empress.c index 81431ee41842..3ae71a340822 100644 --- a/drivers/media/video/saa7134/saa7134-empress.c +++ b/drivers/media/video/saa7134/saa7134-empress.c | |||
@@ -110,9 +110,10 @@ static int ts_release(struct inode *inode, struct file *file) | |||
110 | { | 110 | { |
111 | struct saa7134_dev *dev = file->private_data; | 111 | struct saa7134_dev *dev = file->private_data; |
112 | 112 | ||
113 | mutex_lock(&dev->empress_tsq.vb_lock); | ||
114 | |||
113 | videobuf_stop(&dev->empress_tsq); | 115 | videobuf_stop(&dev->empress_tsq); |
114 | videobuf_mmap_free(&dev->empress_tsq); | 116 | videobuf_mmap_free(&dev->empress_tsq); |
115 | dev->empress_users--; | ||
116 | 117 | ||
117 | /* stop the encoder */ | 118 | /* stop the encoder */ |
118 | ts_reset_encoder(dev); | 119 | ts_reset_encoder(dev); |
@@ -121,6 +122,10 @@ static int ts_release(struct inode *inode, struct file *file) | |||
121 | saa_writeb(SAA7134_AUDIO_MUTE_CTRL, | 122 | saa_writeb(SAA7134_AUDIO_MUTE_CTRL, |
122 | saa_readb(SAA7134_AUDIO_MUTE_CTRL) | (1 << 6)); | 123 | saa_readb(SAA7134_AUDIO_MUTE_CTRL) | (1 << 6)); |
123 | 124 | ||
125 | dev->empress_users--; | ||
126 | |||
127 | mutex_unlock(&dev->empress_tsq.vb_lock); | ||
128 | |||
124 | return 0; | 129 | return 0; |
125 | } | 130 | } |
126 | 131 | ||
@@ -218,8 +223,7 @@ static int empress_enum_fmt_cap(struct file *file, void *priv, | |||
218 | static int empress_g_fmt_cap(struct file *file, void *priv, | 223 | static int empress_g_fmt_cap(struct file *file, void *priv, |
219 | struct v4l2_format *f) | 224 | struct v4l2_format *f) |
220 | { | 225 | { |
221 | struct saa7134_fh *fh = priv; | 226 | struct saa7134_dev *dev = file->private_data; |
222 | struct saa7134_dev *dev = fh->dev; | ||
223 | 227 | ||
224 | saa7134_i2c_call_clients(dev, VIDIOC_G_FMT, f); | 228 | saa7134_i2c_call_clients(dev, VIDIOC_G_FMT, f); |
225 | 229 | ||
@@ -232,8 +236,7 @@ static int empress_g_fmt_cap(struct file *file, void *priv, | |||
232 | static int empress_s_fmt_cap(struct file *file, void *priv, | 236 | static int empress_s_fmt_cap(struct file *file, void *priv, |
233 | struct v4l2_format *f) | 237 | struct v4l2_format *f) |
234 | { | 238 | { |
235 | struct saa7134_fh *fh = priv; | 239 | struct saa7134_dev *dev = file->private_data; |
236 | struct saa7134_dev *dev = fh->dev; | ||
237 | 240 | ||
238 | saa7134_i2c_call_clients(dev, VIDIOC_S_FMT, f); | 241 | saa7134_i2c_call_clients(dev, VIDIOC_S_FMT, f); |
239 | 242 | ||
@@ -247,8 +250,7 @@ static int empress_s_fmt_cap(struct file *file, void *priv, | |||
247 | static int empress_reqbufs(struct file *file, void *priv, | 250 | static int empress_reqbufs(struct file *file, void *priv, |
248 | struct v4l2_requestbuffers *p) | 251 | struct v4l2_requestbuffers *p) |
249 | { | 252 | { |
250 | struct saa7134_fh *fh = priv; | 253 | struct saa7134_dev *dev = file->private_data; |
251 | struct saa7134_dev *dev = fh->dev; | ||
252 | 254 | ||
253 | return videobuf_reqbufs(&dev->empress_tsq, p); | 255 | return videobuf_reqbufs(&dev->empress_tsq, p); |
254 | } | 256 | } |
@@ -256,24 +258,21 @@ static int empress_reqbufs(struct file *file, void *priv, | |||
256 | static int empress_querybuf(struct file *file, void *priv, | 258 | static int empress_querybuf(struct file *file, void *priv, |
257 | struct v4l2_buffer *b) | 259 | struct v4l2_buffer *b) |
258 | { | 260 | { |
259 | struct saa7134_fh *fh = priv; | 261 | struct saa7134_dev *dev = file->private_data; |
260 | struct saa7134_dev *dev = fh->dev; | ||
261 | 262 | ||
262 | return videobuf_querybuf(&dev->empress_tsq, b); | 263 | return videobuf_querybuf(&dev->empress_tsq, b); |
263 | } | 264 | } |
264 | 265 | ||
265 | static int empress_qbuf(struct file *file, void *priv, struct v4l2_buffer *b) | 266 | static int empress_qbuf(struct file *file, void *priv, struct v4l2_buffer *b) |
266 | { | 267 | { |
267 | struct saa7134_fh *fh = priv; | 268 | struct saa7134_dev *dev = file->private_data; |
268 | struct saa7134_dev *dev = fh->dev; | ||
269 | 269 | ||
270 | return videobuf_qbuf(&dev->empress_tsq, b); | 270 | return videobuf_qbuf(&dev->empress_tsq, b); |
271 | } | 271 | } |
272 | 272 | ||
273 | static int empress_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) | 273 | static int empress_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) |
274 | { | 274 | { |
275 | struct saa7134_fh *fh = priv; | 275 | struct saa7134_dev *dev = file->private_data; |
276 | struct saa7134_dev *dev = fh->dev; | ||
277 | 276 | ||
278 | return videobuf_dqbuf(&dev->empress_tsq, b, | 277 | return videobuf_dqbuf(&dev->empress_tsq, b, |
279 | file->f_flags & O_NONBLOCK); | 278 | file->f_flags & O_NONBLOCK); |
@@ -282,8 +281,7 @@ static int empress_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b) | |||
282 | static int empress_streamon(struct file *file, void *priv, | 281 | static int empress_streamon(struct file *file, void *priv, |
283 | enum v4l2_buf_type type) | 282 | enum v4l2_buf_type type) |
284 | { | 283 | { |
285 | struct saa7134_fh *fh = priv; | 284 | struct saa7134_dev *dev = file->private_data; |
286 | struct saa7134_dev *dev = fh->dev; | ||
287 | 285 | ||
288 | return videobuf_streamon(&dev->empress_tsq); | 286 | return videobuf_streamon(&dev->empress_tsq); |
289 | } | 287 | } |
@@ -291,8 +289,7 @@ static int empress_streamon(struct file *file, void *priv, | |||
291 | static int empress_streamoff(struct file *file, void *priv, | 289 | static int empress_streamoff(struct file *file, void *priv, |
292 | enum v4l2_buf_type type) | 290 | enum v4l2_buf_type type) |
293 | { | 291 | { |
294 | struct saa7134_fh *fh = priv; | 292 | struct saa7134_dev *dev = file->private_data; |
295 | struct saa7134_dev *dev = fh->dev; | ||
296 | 293 | ||
297 | return videobuf_streamoff(&dev->empress_tsq); | 294 | return videobuf_streamoff(&dev->empress_tsq); |
298 | } | 295 | } |
@@ -300,8 +297,7 @@ static int empress_streamoff(struct file *file, void *priv, | |||
300 | static int empress_s_ext_ctrls(struct file *file, void *priv, | 297 | static int empress_s_ext_ctrls(struct file *file, void *priv, |
301 | struct v4l2_ext_controls *ctrls) | 298 | struct v4l2_ext_controls *ctrls) |
302 | { | 299 | { |
303 | struct saa7134_fh *fh = priv; | 300 | struct saa7134_dev *dev = file->private_data; |
304 | struct saa7134_dev *dev = fh->dev; | ||
305 | 301 | ||
306 | /* count == 0 is abused in saa6752hs.c, so that special | 302 | /* count == 0 is abused in saa6752hs.c, so that special |
307 | case is handled here explicitly. */ | 303 | case is handled here explicitly. */ |
@@ -320,8 +316,7 @@ static int empress_s_ext_ctrls(struct file *file, void *priv, | |||
320 | static int empress_g_ext_ctrls(struct file *file, void *priv, | 316 | static int empress_g_ext_ctrls(struct file *file, void *priv, |
321 | struct v4l2_ext_controls *ctrls) | 317 | struct v4l2_ext_controls *ctrls) |
322 | { | 318 | { |
323 | struct saa7134_fh *fh = priv; | 319 | struct saa7134_dev *dev = file->private_data; |
324 | struct saa7134_dev *dev = fh->dev; | ||
325 | 320 | ||
326 | if (ctrls->ctrl_class != V4L2_CTRL_CLASS_MPEG) | 321 | if (ctrls->ctrl_class != V4L2_CTRL_CLASS_MPEG) |
327 | return -EINVAL; | 322 | return -EINVAL; |
diff --git a/drivers/media/video/saa7134/saa7134-input.c b/drivers/media/video/saa7134/saa7134-input.c index 919632b10aae..76e6501d238d 100644 --- a/drivers/media/video/saa7134/saa7134-input.c +++ b/drivers/media/video/saa7134/saa7134-input.c | |||
@@ -323,6 +323,15 @@ int saa7134_input_init1(struct saa7134_dev *dev) | |||
323 | saa_setb(SAA7134_GPIO_GPMODE1, 0x1); | 323 | saa_setb(SAA7134_GPIO_GPMODE1, 0x1); |
324 | saa_setb(SAA7134_GPIO_GPSTATUS1, 0x1); | 324 | saa_setb(SAA7134_GPIO_GPSTATUS1, 0x1); |
325 | break; | 325 | break; |
326 | case SAA7134_BOARD_AVERMEDIA_A16D: | ||
327 | ir_codes = ir_codes_avermedia_a16d; | ||
328 | mask_keycode = 0x02F200; | ||
329 | mask_keydown = 0x000400; | ||
330 | polling = 50; /* ms */ | ||
331 | /* Without this we won't receive key up events */ | ||
332 | saa_setb(SAA7134_GPIO_GPMODE1, 0x1); | ||
333 | saa_setb(SAA7134_GPIO_GPSTATUS1, 0x1); | ||
334 | break; | ||
326 | case SAA7134_BOARD_KWORLD_TERMINATOR: | 335 | case SAA7134_BOARD_KWORLD_TERMINATOR: |
327 | ir_codes = ir_codes_pixelview; | 336 | ir_codes = ir_codes_pixelview; |
328 | mask_keycode = 0x00001f; | 337 | mask_keycode = 0x00001f; |
diff --git a/drivers/media/video/soc_camera.c b/drivers/media/video/soc_camera.c index a1b92446c8b4..d015bfe00950 100644 --- a/drivers/media/video/soc_camera.c +++ b/drivers/media/video/soc_camera.c | |||
@@ -763,15 +763,6 @@ static struct device_driver ic_drv = { | |||
763 | .owner = THIS_MODULE, | 763 | .owner = THIS_MODULE, |
764 | }; | 764 | }; |
765 | 765 | ||
766 | /* | ||
767 | * Image capture host - this is a host device, not a bus device, so, | ||
768 | * no bus reference, no probing. | ||
769 | */ | ||
770 | static struct class soc_camera_host_class = { | ||
771 | .owner = THIS_MODULE, | ||
772 | .name = "camera_host", | ||
773 | }; | ||
774 | |||
775 | static void dummy_release(struct device *dev) | 766 | static void dummy_release(struct device *dev) |
776 | { | 767 | { |
777 | } | 768 | } |
@@ -801,7 +792,6 @@ int soc_camera_host_register(struct soc_camera_host *ici) | |||
801 | 792 | ||
802 | /* Number might be equal to the platform device ID */ | 793 | /* Number might be equal to the platform device ID */ |
803 | sprintf(ici->dev.bus_id, "camera_host%d", ici->nr); | 794 | sprintf(ici->dev.bus_id, "camera_host%d", ici->nr); |
804 | ici->dev.class = &soc_camera_host_class; | ||
805 | 795 | ||
806 | mutex_lock(&list_lock); | 796 | mutex_lock(&list_lock); |
807 | list_for_each_entry(ix, &hosts, list) { | 797 | list_for_each_entry(ix, &hosts, list) { |
@@ -1003,14 +993,9 @@ static int __init soc_camera_init(void) | |||
1003 | ret = driver_register(&ic_drv); | 993 | ret = driver_register(&ic_drv); |
1004 | if (ret) | 994 | if (ret) |
1005 | goto edrvr; | 995 | goto edrvr; |
1006 | ret = class_register(&soc_camera_host_class); | ||
1007 | if (ret) | ||
1008 | goto eclr; | ||
1009 | 996 | ||
1010 | return 0; | 997 | return 0; |
1011 | 998 | ||
1012 | eclr: | ||
1013 | driver_unregister(&ic_drv); | ||
1014 | edrvr: | 999 | edrvr: |
1015 | bus_unregister(&soc_camera_bus_type); | 1000 | bus_unregister(&soc_camera_bus_type); |
1016 | return ret; | 1001 | return ret; |
@@ -1018,7 +1003,6 @@ edrvr: | |||
1018 | 1003 | ||
1019 | static void __exit soc_camera_exit(void) | 1004 | static void __exit soc_camera_exit(void) |
1020 | { | 1005 | { |
1021 | class_unregister(&soc_camera_host_class); | ||
1022 | driver_unregister(&ic_drv); | 1006 | driver_unregister(&ic_drv); |
1023 | bus_unregister(&soc_camera_bus_type); | 1007 | bus_unregister(&soc_camera_bus_type); |
1024 | } | 1008 | } |
diff --git a/drivers/media/video/uvc/Makefile b/drivers/media/video/uvc/Makefile new file mode 100644 index 000000000000..968c1994eda0 --- /dev/null +++ b/drivers/media/video/uvc/Makefile | |||
@@ -0,0 +1,3 @@ | |||
1 | uvcvideo-objs := uvc_driver.o uvc_queue.o uvc_v4l2.o uvc_video.o uvc_ctrl.o \ | ||
2 | uvc_status.o uvc_isight.o | ||
3 | obj-$(CONFIG_USB_VIDEO_CLASS) += uvcvideo.o | ||
diff --git a/drivers/media/video/uvc/uvc_ctrl.c b/drivers/media/video/uvc/uvc_ctrl.c new file mode 100644 index 000000000000..f0ee46d15540 --- /dev/null +++ b/drivers/media/video/uvc/uvc_ctrl.c | |||
@@ -0,0 +1,1256 @@ | |||
1 | /* | ||
2 | * uvc_ctrl.c -- USB Video Class driver - Controls | ||
3 | * | ||
4 | * Copyright (C) 2005-2008 | ||
5 | * Laurent Pinchart (laurent.pinchart@skynet.be) | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/version.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/uaccess.h> | ||
19 | #include <linux/usb.h> | ||
20 | #include <linux/videodev2.h> | ||
21 | #include <linux/vmalloc.h> | ||
22 | #include <linux/wait.h> | ||
23 | #include <asm/atomic.h> | ||
24 | |||
25 | #include "uvcvideo.h" | ||
26 | |||
27 | #define UVC_CTRL_NDATA 2 | ||
28 | #define UVC_CTRL_DATA_CURRENT 0 | ||
29 | #define UVC_CTRL_DATA_BACKUP 1 | ||
30 | |||
31 | /* ------------------------------------------------------------------------ | ||
32 | * Control, formats, ... | ||
33 | */ | ||
34 | |||
35 | static struct uvc_control_info uvc_ctrls[] = { | ||
36 | { | ||
37 | .entity = UVC_GUID_UVC_PROCESSING, | ||
38 | .selector = PU_BRIGHTNESS_CONTROL, | ||
39 | .index = 0, | ||
40 | .size = 2, | ||
41 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
42 | | UVC_CONTROL_RESTORE, | ||
43 | }, | ||
44 | { | ||
45 | .entity = UVC_GUID_UVC_PROCESSING, | ||
46 | .selector = PU_CONTRAST_CONTROL, | ||
47 | .index = 1, | ||
48 | .size = 2, | ||
49 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
50 | | UVC_CONTROL_RESTORE, | ||
51 | }, | ||
52 | { | ||
53 | .entity = UVC_GUID_UVC_PROCESSING, | ||
54 | .selector = PU_HUE_CONTROL, | ||
55 | .index = 2, | ||
56 | .size = 2, | ||
57 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
58 | | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE, | ||
59 | }, | ||
60 | { | ||
61 | .entity = UVC_GUID_UVC_PROCESSING, | ||
62 | .selector = PU_SATURATION_CONTROL, | ||
63 | .index = 3, | ||
64 | .size = 2, | ||
65 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
66 | | UVC_CONTROL_RESTORE, | ||
67 | }, | ||
68 | { | ||
69 | .entity = UVC_GUID_UVC_PROCESSING, | ||
70 | .selector = PU_SHARPNESS_CONTROL, | ||
71 | .index = 4, | ||
72 | .size = 2, | ||
73 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
74 | | UVC_CONTROL_RESTORE, | ||
75 | }, | ||
76 | { | ||
77 | .entity = UVC_GUID_UVC_PROCESSING, | ||
78 | .selector = PU_GAMMA_CONTROL, | ||
79 | .index = 5, | ||
80 | .size = 2, | ||
81 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
82 | | UVC_CONTROL_RESTORE, | ||
83 | }, | ||
84 | { | ||
85 | .entity = UVC_GUID_UVC_PROCESSING, | ||
86 | .selector = PU_BACKLIGHT_COMPENSATION_CONTROL, | ||
87 | .index = 8, | ||
88 | .size = 2, | ||
89 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
90 | | UVC_CONTROL_RESTORE, | ||
91 | }, | ||
92 | { | ||
93 | .entity = UVC_GUID_UVC_PROCESSING, | ||
94 | .selector = PU_GAIN_CONTROL, | ||
95 | .index = 9, | ||
96 | .size = 2, | ||
97 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
98 | | UVC_CONTROL_RESTORE, | ||
99 | }, | ||
100 | { | ||
101 | .entity = UVC_GUID_UVC_PROCESSING, | ||
102 | .selector = PU_POWER_LINE_FREQUENCY_CONTROL, | ||
103 | .index = 10, | ||
104 | .size = 1, | ||
105 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
106 | | UVC_CONTROL_RESTORE, | ||
107 | }, | ||
108 | { | ||
109 | .entity = UVC_GUID_UVC_PROCESSING, | ||
110 | .selector = PU_HUE_AUTO_CONTROL, | ||
111 | .index = 11, | ||
112 | .size = 1, | ||
113 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR | ||
114 | | UVC_CONTROL_GET_DEF | UVC_CONTROL_RESTORE, | ||
115 | }, | ||
116 | { | ||
117 | .entity = UVC_GUID_UVC_CAMERA, | ||
118 | .selector = CT_AE_MODE_CONTROL, | ||
119 | .index = 1, | ||
120 | .size = 1, | ||
121 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR | ||
122 | | UVC_CONTROL_GET_DEF | UVC_CONTROL_GET_RES | ||
123 | | UVC_CONTROL_RESTORE, | ||
124 | }, | ||
125 | { | ||
126 | .entity = UVC_GUID_UVC_CAMERA, | ||
127 | .selector = CT_AE_PRIORITY_CONTROL, | ||
128 | .index = 2, | ||
129 | .size = 1, | ||
130 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR | ||
131 | | UVC_CONTROL_RESTORE, | ||
132 | }, | ||
133 | { | ||
134 | .entity = UVC_GUID_UVC_CAMERA, | ||
135 | .selector = CT_EXPOSURE_TIME_ABSOLUTE_CONTROL, | ||
136 | .index = 3, | ||
137 | .size = 4, | ||
138 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
139 | | UVC_CONTROL_RESTORE, | ||
140 | }, | ||
141 | { | ||
142 | .entity = UVC_GUID_UVC_CAMERA, | ||
143 | .selector = CT_FOCUS_ABSOLUTE_CONTROL, | ||
144 | .index = 5, | ||
145 | .size = 2, | ||
146 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
147 | | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE, | ||
148 | }, | ||
149 | { | ||
150 | .entity = UVC_GUID_UVC_CAMERA, | ||
151 | .selector = CT_FOCUS_AUTO_CONTROL, | ||
152 | .index = 17, | ||
153 | .size = 1, | ||
154 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR | ||
155 | | UVC_CONTROL_GET_DEF | UVC_CONTROL_RESTORE, | ||
156 | }, | ||
157 | { | ||
158 | .entity = UVC_GUID_UVC_PROCESSING, | ||
159 | .selector = PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL, | ||
160 | .index = 12, | ||
161 | .size = 1, | ||
162 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR | ||
163 | | UVC_CONTROL_GET_DEF | UVC_CONTROL_RESTORE, | ||
164 | }, | ||
165 | { | ||
166 | .entity = UVC_GUID_UVC_PROCESSING, | ||
167 | .selector = PU_WHITE_BALANCE_TEMPERATURE_CONTROL, | ||
168 | .index = 6, | ||
169 | .size = 2, | ||
170 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
171 | | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE, | ||
172 | }, | ||
173 | { | ||
174 | .entity = UVC_GUID_UVC_PROCESSING, | ||
175 | .selector = PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL, | ||
176 | .index = 13, | ||
177 | .size = 1, | ||
178 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR | ||
179 | | UVC_CONTROL_GET_DEF | UVC_CONTROL_RESTORE, | ||
180 | }, | ||
181 | { | ||
182 | .entity = UVC_GUID_UVC_PROCESSING, | ||
183 | .selector = PU_WHITE_BALANCE_COMPONENT_CONTROL, | ||
184 | .index = 7, | ||
185 | .size = 4, | ||
186 | .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE | ||
187 | | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE, | ||
188 | }, | ||
189 | }; | ||
190 | |||
191 | static struct uvc_menu_info power_line_frequency_controls[] = { | ||
192 | { 0, "Disabled" }, | ||
193 | { 1, "50 Hz" }, | ||
194 | { 2, "60 Hz" }, | ||
195 | }; | ||
196 | |||
197 | static struct uvc_menu_info exposure_auto_controls[] = { | ||
198 | { 1, "Manual Mode" }, | ||
199 | { 2, "Auto Mode" }, | ||
200 | { 4, "Shutter Priority Mode" }, | ||
201 | { 8, "Aperture Priority Mode" }, | ||
202 | }; | ||
203 | |||
204 | static struct uvc_control_mapping uvc_ctrl_mappings[] = { | ||
205 | { | ||
206 | .id = V4L2_CID_BRIGHTNESS, | ||
207 | .name = "Brightness", | ||
208 | .entity = UVC_GUID_UVC_PROCESSING, | ||
209 | .selector = PU_BRIGHTNESS_CONTROL, | ||
210 | .size = 16, | ||
211 | .offset = 0, | ||
212 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
213 | .data_type = UVC_CTRL_DATA_TYPE_SIGNED, | ||
214 | }, | ||
215 | { | ||
216 | .id = V4L2_CID_CONTRAST, | ||
217 | .name = "Contrast", | ||
218 | .entity = UVC_GUID_UVC_PROCESSING, | ||
219 | .selector = PU_CONTRAST_CONTROL, | ||
220 | .size = 16, | ||
221 | .offset = 0, | ||
222 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
223 | .data_type = UVC_CTRL_DATA_TYPE_UNSIGNED, | ||
224 | }, | ||
225 | { | ||
226 | .id = V4L2_CID_HUE, | ||
227 | .name = "Hue", | ||
228 | .entity = UVC_GUID_UVC_PROCESSING, | ||
229 | .selector = PU_HUE_CONTROL, | ||
230 | .size = 16, | ||
231 | .offset = 0, | ||
232 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
233 | .data_type = UVC_CTRL_DATA_TYPE_SIGNED, | ||
234 | }, | ||
235 | { | ||
236 | .id = V4L2_CID_SATURATION, | ||
237 | .name = "Saturation", | ||
238 | .entity = UVC_GUID_UVC_PROCESSING, | ||
239 | .selector = PU_SATURATION_CONTROL, | ||
240 | .size = 16, | ||
241 | .offset = 0, | ||
242 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
243 | .data_type = UVC_CTRL_DATA_TYPE_UNSIGNED, | ||
244 | }, | ||
245 | { | ||
246 | .id = V4L2_CID_SHARPNESS, | ||
247 | .name = "Sharpness", | ||
248 | .entity = UVC_GUID_UVC_PROCESSING, | ||
249 | .selector = PU_SHARPNESS_CONTROL, | ||
250 | .size = 16, | ||
251 | .offset = 0, | ||
252 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
253 | .data_type = UVC_CTRL_DATA_TYPE_UNSIGNED, | ||
254 | }, | ||
255 | { | ||
256 | .id = V4L2_CID_GAMMA, | ||
257 | .name = "Gamma", | ||
258 | .entity = UVC_GUID_UVC_PROCESSING, | ||
259 | .selector = PU_GAMMA_CONTROL, | ||
260 | .size = 16, | ||
261 | .offset = 0, | ||
262 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
263 | .data_type = UVC_CTRL_DATA_TYPE_UNSIGNED, | ||
264 | }, | ||
265 | { | ||
266 | .id = V4L2_CID_BACKLIGHT_COMPENSATION, | ||
267 | .name = "Backlight Compensation", | ||
268 | .entity = UVC_GUID_UVC_PROCESSING, | ||
269 | .selector = PU_BACKLIGHT_COMPENSATION_CONTROL, | ||
270 | .size = 16, | ||
271 | .offset = 0, | ||
272 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
273 | .data_type = UVC_CTRL_DATA_TYPE_UNSIGNED, | ||
274 | }, | ||
275 | { | ||
276 | .id = V4L2_CID_GAIN, | ||
277 | .name = "Gain", | ||
278 | .entity = UVC_GUID_UVC_PROCESSING, | ||
279 | .selector = PU_GAIN_CONTROL, | ||
280 | .size = 16, | ||
281 | .offset = 0, | ||
282 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
283 | .data_type = UVC_CTRL_DATA_TYPE_UNSIGNED, | ||
284 | }, | ||
285 | { | ||
286 | .id = V4L2_CID_POWER_LINE_FREQUENCY, | ||
287 | .name = "Power Line Frequency", | ||
288 | .entity = UVC_GUID_UVC_PROCESSING, | ||
289 | .selector = PU_POWER_LINE_FREQUENCY_CONTROL, | ||
290 | .size = 2, | ||
291 | .offset = 0, | ||
292 | .v4l2_type = V4L2_CTRL_TYPE_MENU, | ||
293 | .data_type = UVC_CTRL_DATA_TYPE_ENUM, | ||
294 | .menu_info = power_line_frequency_controls, | ||
295 | .menu_count = ARRAY_SIZE(power_line_frequency_controls), | ||
296 | }, | ||
297 | { | ||
298 | .id = V4L2_CID_HUE_AUTO, | ||
299 | .name = "Hue, Auto", | ||
300 | .entity = UVC_GUID_UVC_PROCESSING, | ||
301 | .selector = PU_HUE_AUTO_CONTROL, | ||
302 | .size = 1, | ||
303 | .offset = 0, | ||
304 | .v4l2_type = V4L2_CTRL_TYPE_BOOLEAN, | ||
305 | .data_type = UVC_CTRL_DATA_TYPE_BOOLEAN, | ||
306 | }, | ||
307 | { | ||
308 | .id = V4L2_CID_EXPOSURE_AUTO, | ||
309 | .name = "Exposure, Auto", | ||
310 | .entity = UVC_GUID_UVC_CAMERA, | ||
311 | .selector = CT_AE_MODE_CONTROL, | ||
312 | .size = 4, | ||
313 | .offset = 0, | ||
314 | .v4l2_type = V4L2_CTRL_TYPE_MENU, | ||
315 | .data_type = UVC_CTRL_DATA_TYPE_BITMASK, | ||
316 | .menu_info = exposure_auto_controls, | ||
317 | .menu_count = ARRAY_SIZE(exposure_auto_controls), | ||
318 | }, | ||
319 | { | ||
320 | .id = V4L2_CID_EXPOSURE_AUTO_PRIORITY, | ||
321 | .name = "Exposure, Auto Priority", | ||
322 | .entity = UVC_GUID_UVC_CAMERA, | ||
323 | .selector = CT_AE_PRIORITY_CONTROL, | ||
324 | .size = 1, | ||
325 | .offset = 0, | ||
326 | .v4l2_type = V4L2_CTRL_TYPE_BOOLEAN, | ||
327 | .data_type = UVC_CTRL_DATA_TYPE_BOOLEAN, | ||
328 | }, | ||
329 | { | ||
330 | .id = V4L2_CID_EXPOSURE_ABSOLUTE, | ||
331 | .name = "Exposure (Absolute)", | ||
332 | .entity = UVC_GUID_UVC_CAMERA, | ||
333 | .selector = CT_EXPOSURE_TIME_ABSOLUTE_CONTROL, | ||
334 | .size = 32, | ||
335 | .offset = 0, | ||
336 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
337 | .data_type = UVC_CTRL_DATA_TYPE_UNSIGNED, | ||
338 | }, | ||
339 | { | ||
340 | .id = V4L2_CID_AUTO_WHITE_BALANCE, | ||
341 | .name = "White Balance Temperature, Auto", | ||
342 | .entity = UVC_GUID_UVC_PROCESSING, | ||
343 | .selector = PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL, | ||
344 | .size = 1, | ||
345 | .offset = 0, | ||
346 | .v4l2_type = V4L2_CTRL_TYPE_BOOLEAN, | ||
347 | .data_type = UVC_CTRL_DATA_TYPE_BOOLEAN, | ||
348 | }, | ||
349 | { | ||
350 | .id = V4L2_CID_WHITE_BALANCE_TEMPERATURE, | ||
351 | .name = "White Balance Temperature", | ||
352 | .entity = UVC_GUID_UVC_PROCESSING, | ||
353 | .selector = PU_WHITE_BALANCE_TEMPERATURE_CONTROL, | ||
354 | .size = 16, | ||
355 | .offset = 0, | ||
356 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
357 | .data_type = UVC_CTRL_DATA_TYPE_UNSIGNED, | ||
358 | }, | ||
359 | { | ||
360 | .id = V4L2_CID_AUTO_WHITE_BALANCE, | ||
361 | .name = "White Balance Component, Auto", | ||
362 | .entity = UVC_GUID_UVC_PROCESSING, | ||
363 | .selector = PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL, | ||
364 | .size = 1, | ||
365 | .offset = 0, | ||
366 | .v4l2_type = V4L2_CTRL_TYPE_BOOLEAN, | ||
367 | .data_type = UVC_CTRL_DATA_TYPE_BOOLEAN, | ||
368 | }, | ||
369 | { | ||
370 | .id = V4L2_CID_BLUE_BALANCE, | ||
371 | .name = "White Balance Blue Component", | ||
372 | .entity = UVC_GUID_UVC_PROCESSING, | ||
373 | .selector = PU_WHITE_BALANCE_COMPONENT_CONTROL, | ||
374 | .size = 16, | ||
375 | .offset = 0, | ||
376 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
377 | .data_type = UVC_CTRL_DATA_TYPE_SIGNED, | ||
378 | }, | ||
379 | { | ||
380 | .id = V4L2_CID_RED_BALANCE, | ||
381 | .name = "White Balance Red Component", | ||
382 | .entity = UVC_GUID_UVC_PROCESSING, | ||
383 | .selector = PU_WHITE_BALANCE_COMPONENT_CONTROL, | ||
384 | .size = 16, | ||
385 | .offset = 16, | ||
386 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
387 | .data_type = UVC_CTRL_DATA_TYPE_SIGNED, | ||
388 | }, | ||
389 | { | ||
390 | .id = V4L2_CID_FOCUS_ABSOLUTE, | ||
391 | .name = "Focus (absolute)", | ||
392 | .entity = UVC_GUID_UVC_CAMERA, | ||
393 | .selector = CT_FOCUS_ABSOLUTE_CONTROL, | ||
394 | .size = 16, | ||
395 | .offset = 0, | ||
396 | .v4l2_type = V4L2_CTRL_TYPE_INTEGER, | ||
397 | .data_type = UVC_CTRL_DATA_TYPE_UNSIGNED, | ||
398 | }, | ||
399 | { | ||
400 | .id = V4L2_CID_FOCUS_AUTO, | ||
401 | .name = "Focus, Auto", | ||
402 | .entity = UVC_GUID_UVC_CAMERA, | ||
403 | .selector = CT_FOCUS_AUTO_CONTROL, | ||
404 | .size = 1, | ||
405 | .offset = 0, | ||
406 | .v4l2_type = V4L2_CTRL_TYPE_BOOLEAN, | ||
407 | .data_type = UVC_CTRL_DATA_TYPE_BOOLEAN, | ||
408 | }, | ||
409 | }; | ||
410 | |||
411 | /* ------------------------------------------------------------------------ | ||
412 | * Utility functions | ||
413 | */ | ||
414 | |||
415 | static inline __u8 *uvc_ctrl_data(struct uvc_control *ctrl, int id) | ||
416 | { | ||
417 | return ctrl->data + id * ctrl->info->size; | ||
418 | } | ||
419 | |||
420 | static inline int uvc_get_bit(const __u8 *data, int bit) | ||
421 | { | ||
422 | return (data[bit >> 3] >> (bit & 7)) & 1; | ||
423 | } | ||
424 | |||
425 | /* Extract the bit string specified by mapping->offset and mapping->size | ||
426 | * from the little-endian data stored at 'data' and return the result as | ||
427 | * a signed 32bit integer. Sign extension will be performed if the mapping | ||
428 | * references a signed data type. | ||
429 | */ | ||
430 | static __s32 uvc_get_le_value(const __u8 *data, | ||
431 | struct uvc_control_mapping *mapping) | ||
432 | { | ||
433 | int bits = mapping->size; | ||
434 | int offset = mapping->offset; | ||
435 | __s32 value = 0; | ||
436 | __u8 mask; | ||
437 | |||
438 | data += offset / 8; | ||
439 | offset &= 7; | ||
440 | mask = ((1LL << bits) - 1) << offset; | ||
441 | |||
442 | for (; bits > 0; data++) { | ||
443 | __u8 byte = *data & mask; | ||
444 | value |= offset > 0 ? (byte >> offset) : (byte << (-offset)); | ||
445 | bits -= 8 - (offset > 0 ? offset : 0); | ||
446 | offset -= 8; | ||
447 | mask = (1 << bits) - 1; | ||
448 | } | ||
449 | |||
450 | /* Sign-extend the value if needed */ | ||
451 | if (mapping->data_type == UVC_CTRL_DATA_TYPE_SIGNED) | ||
452 | value |= -(value & (1 << (mapping->size - 1))); | ||
453 | |||
454 | return value; | ||
455 | } | ||
456 | |||
457 | /* Set the bit string specified by mapping->offset and mapping->size | ||
458 | * in the little-endian data stored at 'data' to the value 'value'. | ||
459 | */ | ||
460 | static void uvc_set_le_value(__s32 value, __u8 *data, | ||
461 | struct uvc_control_mapping *mapping) | ||
462 | { | ||
463 | int bits = mapping->size; | ||
464 | int offset = mapping->offset; | ||
465 | __u8 mask; | ||
466 | |||
467 | data += offset / 8; | ||
468 | offset &= 7; | ||
469 | |||
470 | for (; bits > 0; data++) { | ||
471 | mask = ((1LL << bits) - 1) << offset; | ||
472 | *data = (*data & ~mask) | ((value << offset) & mask); | ||
473 | value >>= offset ? offset : 8; | ||
474 | bits -= 8 - offset; | ||
475 | offset = 0; | ||
476 | } | ||
477 | } | ||
478 | |||
479 | /* ------------------------------------------------------------------------ | ||
480 | * Terminal and unit management | ||
481 | */ | ||
482 | |||
483 | static const __u8 uvc_processing_guid[16] = UVC_GUID_UVC_PROCESSING; | ||
484 | static const __u8 uvc_camera_guid[16] = UVC_GUID_UVC_CAMERA; | ||
485 | static const __u8 uvc_media_transport_input_guid[16] = | ||
486 | UVC_GUID_UVC_MEDIA_TRANSPORT_INPUT; | ||
487 | |||
488 | static int uvc_entity_match_guid(struct uvc_entity *entity, __u8 guid[16]) | ||
489 | { | ||
490 | switch (UVC_ENTITY_TYPE(entity)) { | ||
491 | case ITT_CAMERA: | ||
492 | return memcmp(uvc_camera_guid, guid, 16) == 0; | ||
493 | |||
494 | case ITT_MEDIA_TRANSPORT_INPUT: | ||
495 | return memcmp(uvc_media_transport_input_guid, guid, 16) == 0; | ||
496 | |||
497 | case VC_PROCESSING_UNIT: | ||
498 | return memcmp(uvc_processing_guid, guid, 16) == 0; | ||
499 | |||
500 | case VC_EXTENSION_UNIT: | ||
501 | return memcmp(entity->extension.guidExtensionCode, | ||
502 | guid, 16) == 0; | ||
503 | |||
504 | default: | ||
505 | return 0; | ||
506 | } | ||
507 | } | ||
508 | |||
509 | /* ------------------------------------------------------------------------ | ||
510 | * UVC Controls | ||
511 | */ | ||
512 | |||
513 | static void __uvc_find_control(struct uvc_entity *entity, __u32 v4l2_id, | ||
514 | struct uvc_control_mapping **mapping, struct uvc_control **control, | ||
515 | int next) | ||
516 | { | ||
517 | struct uvc_control *ctrl; | ||
518 | struct uvc_control_mapping *map; | ||
519 | unsigned int i; | ||
520 | |||
521 | if (entity == NULL) | ||
522 | return; | ||
523 | |||
524 | for (i = 0; i < entity->ncontrols; ++i) { | ||
525 | ctrl = &entity->controls[i]; | ||
526 | if (ctrl->info == NULL) | ||
527 | continue; | ||
528 | |||
529 | list_for_each_entry(map, &ctrl->info->mappings, list) { | ||
530 | if ((map->id == v4l2_id) && !next) { | ||
531 | *control = ctrl; | ||
532 | *mapping = map; | ||
533 | return; | ||
534 | } | ||
535 | |||
536 | if ((*mapping == NULL || (*mapping)->id > map->id) && | ||
537 | (map->id > v4l2_id) && next) { | ||
538 | *control = ctrl; | ||
539 | *mapping = map; | ||
540 | } | ||
541 | } | ||
542 | } | ||
543 | } | ||
544 | |||
545 | struct uvc_control *uvc_find_control(struct uvc_video_device *video, | ||
546 | __u32 v4l2_id, struct uvc_control_mapping **mapping) | ||
547 | { | ||
548 | struct uvc_control *ctrl = NULL; | ||
549 | struct uvc_entity *entity; | ||
550 | int next = v4l2_id & V4L2_CTRL_FLAG_NEXT_CTRL; | ||
551 | |||
552 | *mapping = NULL; | ||
553 | |||
554 | /* Mask the query flags. */ | ||
555 | v4l2_id &= V4L2_CTRL_ID_MASK; | ||
556 | |||
557 | /* Find the control. */ | ||
558 | __uvc_find_control(video->processing, v4l2_id, mapping, &ctrl, next); | ||
559 | if (ctrl && !next) | ||
560 | return ctrl; | ||
561 | |||
562 | list_for_each_entry(entity, &video->iterms, chain) { | ||
563 | __uvc_find_control(entity, v4l2_id, mapping, &ctrl, next); | ||
564 | if (ctrl && !next) | ||
565 | return ctrl; | ||
566 | } | ||
567 | |||
568 | list_for_each_entry(entity, &video->extensions, chain) { | ||
569 | __uvc_find_control(entity, v4l2_id, mapping, &ctrl, next); | ||
570 | if (ctrl && !next) | ||
571 | return ctrl; | ||
572 | } | ||
573 | |||
574 | if (ctrl == NULL && !next) | ||
575 | uvc_trace(UVC_TRACE_CONTROL, "Control 0x%08x not found.\n", | ||
576 | v4l2_id); | ||
577 | |||
578 | return ctrl; | ||
579 | } | ||
580 | |||
581 | int uvc_query_v4l2_ctrl(struct uvc_video_device *video, | ||
582 | struct v4l2_queryctrl *v4l2_ctrl) | ||
583 | { | ||
584 | struct uvc_control *ctrl; | ||
585 | struct uvc_control_mapping *mapping; | ||
586 | struct uvc_menu_info *menu; | ||
587 | unsigned int i; | ||
588 | __u8 data[8]; | ||
589 | int ret; | ||
590 | |||
591 | ctrl = uvc_find_control(video, v4l2_ctrl->id, &mapping); | ||
592 | if (ctrl == NULL) | ||
593 | return -EINVAL; | ||
594 | |||
595 | v4l2_ctrl->id = mapping->id; | ||
596 | v4l2_ctrl->type = mapping->v4l2_type; | ||
597 | strncpy(v4l2_ctrl->name, mapping->name, sizeof v4l2_ctrl->name); | ||
598 | v4l2_ctrl->flags = 0; | ||
599 | |||
600 | if (!(ctrl->info->flags & UVC_CONTROL_SET_CUR)) | ||
601 | v4l2_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; | ||
602 | |||
603 | if (ctrl->info->flags & UVC_CONTROL_GET_DEF) { | ||
604 | if ((ret = uvc_query_ctrl(video->dev, GET_DEF, ctrl->entity->id, | ||
605 | video->dev->intfnum, ctrl->info->selector, | ||
606 | &data, ctrl->info->size)) < 0) | ||
607 | return ret; | ||
608 | v4l2_ctrl->default_value = uvc_get_le_value(data, mapping); | ||
609 | } | ||
610 | |||
611 | if (mapping->v4l2_type == V4L2_CTRL_TYPE_MENU) { | ||
612 | v4l2_ctrl->minimum = 0; | ||
613 | v4l2_ctrl->maximum = mapping->menu_count - 1; | ||
614 | v4l2_ctrl->step = 1; | ||
615 | |||
616 | menu = mapping->menu_info; | ||
617 | for (i = 0; i < mapping->menu_count; ++i, ++menu) { | ||
618 | if (menu->value == v4l2_ctrl->default_value) { | ||
619 | v4l2_ctrl->default_value = i; | ||
620 | break; | ||
621 | } | ||
622 | } | ||
623 | |||
624 | return 0; | ||
625 | } | ||
626 | |||
627 | if (ctrl->info->flags & UVC_CONTROL_GET_MIN) { | ||
628 | if ((ret = uvc_query_ctrl(video->dev, GET_MIN, ctrl->entity->id, | ||
629 | video->dev->intfnum, ctrl->info->selector, | ||
630 | &data, ctrl->info->size)) < 0) | ||
631 | return ret; | ||
632 | v4l2_ctrl->minimum = uvc_get_le_value(data, mapping); | ||
633 | } | ||
634 | if (ctrl->info->flags & UVC_CONTROL_GET_MAX) { | ||
635 | if ((ret = uvc_query_ctrl(video->dev, GET_MAX, ctrl->entity->id, | ||
636 | video->dev->intfnum, ctrl->info->selector, | ||
637 | &data, ctrl->info->size)) < 0) | ||
638 | return ret; | ||
639 | v4l2_ctrl->maximum = uvc_get_le_value(data, mapping); | ||
640 | } | ||
641 | if (ctrl->info->flags & UVC_CONTROL_GET_RES) { | ||
642 | if ((ret = uvc_query_ctrl(video->dev, GET_RES, ctrl->entity->id, | ||
643 | video->dev->intfnum, ctrl->info->selector, | ||
644 | &data, ctrl->info->size)) < 0) | ||
645 | return ret; | ||
646 | v4l2_ctrl->step = uvc_get_le_value(data, mapping); | ||
647 | } | ||
648 | |||
649 | return 0; | ||
650 | } | ||
651 | |||
652 | |||
653 | /* -------------------------------------------------------------------------- | ||
654 | * Control transactions | ||
655 | * | ||
656 | * To make extended set operations as atomic as the hardware allows, controls | ||
657 | * are handled using begin/commit/rollback operations. | ||
658 | * | ||
659 | * At the beginning of a set request, uvc_ctrl_begin should be called to | ||
660 | * initialize the request. This function acquires the control lock. | ||
661 | * | ||
662 | * When setting a control, the new value is stored in the control data field | ||
663 | * at position UVC_CTRL_DATA_CURRENT. The control is then marked as dirty for | ||
664 | * later processing. If the UVC and V4L2 control sizes differ, the current | ||
665 | * value is loaded from the hardware before storing the new value in the data | ||
666 | * field. | ||
667 | * | ||
668 | * After processing all controls in the transaction, uvc_ctrl_commit or | ||
669 | * uvc_ctrl_rollback must be called to apply the pending changes to the | ||
670 | * hardware or revert them. When applying changes, all controls marked as | ||
671 | * dirty will be modified in the UVC device, and the dirty flag will be | ||
672 | * cleared. When reverting controls, the control data field | ||
673 | * UVC_CTRL_DATA_CURRENT is reverted to its previous value | ||
674 | * (UVC_CTRL_DATA_BACKUP) for all dirty controls. Both functions release the | ||
675 | * control lock. | ||
676 | */ | ||
677 | int uvc_ctrl_begin(struct uvc_video_device *video) | ||
678 | { | ||
679 | return mutex_lock_interruptible(&video->ctrl_mutex) ? -ERESTARTSYS : 0; | ||
680 | } | ||
681 | |||
682 | static int uvc_ctrl_commit_entity(struct uvc_device *dev, | ||
683 | struct uvc_entity *entity, int rollback) | ||
684 | { | ||
685 | struct uvc_control *ctrl; | ||
686 | unsigned int i; | ||
687 | int ret; | ||
688 | |||
689 | if (entity == NULL) | ||
690 | return 0; | ||
691 | |||
692 | for (i = 0; i < entity->ncontrols; ++i) { | ||
693 | ctrl = &entity->controls[i]; | ||
694 | if (ctrl->info == NULL || !ctrl->dirty) | ||
695 | continue; | ||
696 | |||
697 | if (!rollback) | ||
698 | ret = uvc_query_ctrl(dev, SET_CUR, ctrl->entity->id, | ||
699 | dev->intfnum, ctrl->info->selector, | ||
700 | uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), | ||
701 | ctrl->info->size); | ||
702 | else | ||
703 | ret = 0; | ||
704 | |||
705 | if (rollback || ret < 0) | ||
706 | memcpy(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), | ||
707 | uvc_ctrl_data(ctrl, UVC_CTRL_DATA_BACKUP), | ||
708 | ctrl->info->size); | ||
709 | |||
710 | if ((ctrl->info->flags & UVC_CONTROL_GET_CUR) == 0) | ||
711 | ctrl->loaded = 0; | ||
712 | |||
713 | ctrl->dirty = 0; | ||
714 | |||
715 | if (ret < 0) | ||
716 | return ret; | ||
717 | } | ||
718 | |||
719 | return 0; | ||
720 | } | ||
721 | |||
722 | int __uvc_ctrl_commit(struct uvc_video_device *video, int rollback) | ||
723 | { | ||
724 | struct uvc_entity *entity; | ||
725 | int ret = 0; | ||
726 | |||
727 | /* Find the control. */ | ||
728 | ret = uvc_ctrl_commit_entity(video->dev, video->processing, rollback); | ||
729 | if (ret < 0) | ||
730 | goto done; | ||
731 | |||
732 | list_for_each_entry(entity, &video->iterms, chain) { | ||
733 | ret = uvc_ctrl_commit_entity(video->dev, entity, rollback); | ||
734 | if (ret < 0) | ||
735 | goto done; | ||
736 | } | ||
737 | |||
738 | list_for_each_entry(entity, &video->extensions, chain) { | ||
739 | ret = uvc_ctrl_commit_entity(video->dev, entity, rollback); | ||
740 | if (ret < 0) | ||
741 | goto done; | ||
742 | } | ||
743 | |||
744 | done: | ||
745 | mutex_unlock(&video->ctrl_mutex); | ||
746 | return ret; | ||
747 | } | ||
748 | |||
749 | int uvc_ctrl_get(struct uvc_video_device *video, | ||
750 | struct v4l2_ext_control *xctrl) | ||
751 | { | ||
752 | struct uvc_control *ctrl; | ||
753 | struct uvc_control_mapping *mapping; | ||
754 | struct uvc_menu_info *menu; | ||
755 | unsigned int i; | ||
756 | int ret; | ||
757 | |||
758 | ctrl = uvc_find_control(video, xctrl->id, &mapping); | ||
759 | if (ctrl == NULL || (ctrl->info->flags & UVC_CONTROL_GET_CUR) == 0) | ||
760 | return -EINVAL; | ||
761 | |||
762 | if (!ctrl->loaded) { | ||
763 | ret = uvc_query_ctrl(video->dev, GET_CUR, ctrl->entity->id, | ||
764 | video->dev->intfnum, ctrl->info->selector, | ||
765 | uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), | ||
766 | ctrl->info->size); | ||
767 | if (ret < 0) | ||
768 | return ret; | ||
769 | |||
770 | if ((ctrl->info->flags & UVC_CONTROL_AUTO_UPDATE) == 0) | ||
771 | ctrl->loaded = 1; | ||
772 | } | ||
773 | |||
774 | xctrl->value = uvc_get_le_value( | ||
775 | uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), mapping); | ||
776 | |||
777 | if (mapping->v4l2_type == V4L2_CTRL_TYPE_MENU) { | ||
778 | menu = mapping->menu_info; | ||
779 | for (i = 0; i < mapping->menu_count; ++i, ++menu) { | ||
780 | if (menu->value == xctrl->value) { | ||
781 | xctrl->value = i; | ||
782 | break; | ||
783 | } | ||
784 | } | ||
785 | } | ||
786 | |||
787 | return 0; | ||
788 | } | ||
789 | |||
790 | int uvc_ctrl_set(struct uvc_video_device *video, | ||
791 | struct v4l2_ext_control *xctrl) | ||
792 | { | ||
793 | struct uvc_control *ctrl; | ||
794 | struct uvc_control_mapping *mapping; | ||
795 | s32 value = xctrl->value; | ||
796 | int ret; | ||
797 | |||
798 | ctrl = uvc_find_control(video, xctrl->id, &mapping); | ||
799 | if (ctrl == NULL || (ctrl->info->flags & UVC_CONTROL_SET_CUR) == 0) | ||
800 | return -EINVAL; | ||
801 | |||
802 | if (mapping->v4l2_type == V4L2_CTRL_TYPE_MENU) { | ||
803 | if (value < 0 || value >= mapping->menu_count) | ||
804 | return -EINVAL; | ||
805 | value = mapping->menu_info[value].value; | ||
806 | } | ||
807 | |||
808 | if (!ctrl->loaded && (ctrl->info->size * 8) != mapping->size) { | ||
809 | if ((ctrl->info->flags & UVC_CONTROL_GET_CUR) == 0) { | ||
810 | memset(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), | ||
811 | 0, ctrl->info->size); | ||
812 | } else { | ||
813 | ret = uvc_query_ctrl(video->dev, GET_CUR, | ||
814 | ctrl->entity->id, video->dev->intfnum, | ||
815 | ctrl->info->selector, | ||
816 | uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), | ||
817 | ctrl->info->size); | ||
818 | if (ret < 0) | ||
819 | return ret; | ||
820 | } | ||
821 | |||
822 | if ((ctrl->info->flags & UVC_CONTROL_AUTO_UPDATE) == 0) | ||
823 | ctrl->loaded = 1; | ||
824 | } | ||
825 | |||
826 | if (!ctrl->dirty) { | ||
827 | memcpy(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_BACKUP), | ||
828 | uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), | ||
829 | ctrl->info->size); | ||
830 | } | ||
831 | |||
832 | uvc_set_le_value(value, | ||
833 | uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), mapping); | ||
834 | |||
835 | ctrl->dirty = 1; | ||
836 | ctrl->modified = 1; | ||
837 | return 0; | ||
838 | } | ||
839 | |||
840 | /* -------------------------------------------------------------------------- | ||
841 | * Dynamic controls | ||
842 | */ | ||
843 | |||
844 | int uvc_xu_ctrl_query(struct uvc_video_device *video, | ||
845 | struct uvc_xu_control *xctrl, int set) | ||
846 | { | ||
847 | struct uvc_entity *entity; | ||
848 | struct uvc_control *ctrl = NULL; | ||
849 | unsigned int i, found = 0; | ||
850 | __u8 *data; | ||
851 | int ret; | ||
852 | |||
853 | /* Find the extension unit. */ | ||
854 | list_for_each_entry(entity, &video->extensions, chain) { | ||
855 | if (entity->id == xctrl->unit) | ||
856 | break; | ||
857 | } | ||
858 | |||
859 | if (entity->id != xctrl->unit) { | ||
860 | uvc_trace(UVC_TRACE_CONTROL, "Extension unit %u not found.\n", | ||
861 | xctrl->unit); | ||
862 | return -EINVAL; | ||
863 | } | ||
864 | |||
865 | /* Find the control. */ | ||
866 | for (i = 0; i < entity->ncontrols; ++i) { | ||
867 | ctrl = &entity->controls[i]; | ||
868 | if (ctrl->info == NULL) | ||
869 | continue; | ||
870 | |||
871 | if (ctrl->info->selector == xctrl->selector) { | ||
872 | found = 1; | ||
873 | break; | ||
874 | } | ||
875 | } | ||
876 | |||
877 | if (!found) { | ||
878 | uvc_trace(UVC_TRACE_CONTROL, | ||
879 | "Control " UVC_GUID_FORMAT "/%u not found.\n", | ||
880 | UVC_GUID_ARGS(entity->extension.guidExtensionCode), | ||
881 | xctrl->selector); | ||
882 | return -EINVAL; | ||
883 | } | ||
884 | |||
885 | /* Validate control data size. */ | ||
886 | if (ctrl->info->size != xctrl->size) | ||
887 | return -EINVAL; | ||
888 | |||
889 | if ((set && !(ctrl->info->flags & UVC_CONTROL_SET_CUR)) || | ||
890 | (!set && !(ctrl->info->flags & UVC_CONTROL_GET_CUR))) | ||
891 | return -EINVAL; | ||
892 | |||
893 | if (mutex_lock_interruptible(&video->ctrl_mutex)) | ||
894 | return -ERESTARTSYS; | ||
895 | |||
896 | memcpy(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_BACKUP), | ||
897 | uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), | ||
898 | xctrl->size); | ||
899 | data = uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT); | ||
900 | |||
901 | if (set && copy_from_user(data, xctrl->data, xctrl->size)) { | ||
902 | ret = -EFAULT; | ||
903 | goto out; | ||
904 | } | ||
905 | |||
906 | ret = uvc_query_ctrl(video->dev, set ? SET_CUR : GET_CUR, xctrl->unit, | ||
907 | video->dev->intfnum, xctrl->selector, data, | ||
908 | xctrl->size); | ||
909 | if (ret < 0) | ||
910 | goto out; | ||
911 | |||
912 | if (!set && copy_to_user(xctrl->data, data, xctrl->size)) { | ||
913 | ret = -EFAULT; | ||
914 | goto out; | ||
915 | } | ||
916 | |||
917 | out: | ||
918 | if (ret) | ||
919 | memcpy(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), | ||
920 | uvc_ctrl_data(ctrl, UVC_CTRL_DATA_BACKUP), | ||
921 | xctrl->size); | ||
922 | |||
923 | mutex_unlock(&video->ctrl_mutex); | ||
924 | return ret; | ||
925 | } | ||
926 | |||
927 | /* -------------------------------------------------------------------------- | ||
928 | * Suspend/resume | ||
929 | */ | ||
930 | |||
931 | /* | ||
932 | * Restore control values after resume, skipping controls that haven't been | ||
933 | * changed. | ||
934 | * | ||
935 | * TODO | ||
936 | * - Don't restore modified controls that are back to their default value. | ||
937 | * - Handle restore order (Auto-Exposure Mode should be restored before | ||
938 | * Exposure Time). | ||
939 | */ | ||
940 | int uvc_ctrl_resume_device(struct uvc_device *dev) | ||
941 | { | ||
942 | struct uvc_control *ctrl; | ||
943 | struct uvc_entity *entity; | ||
944 | unsigned int i; | ||
945 | int ret; | ||
946 | |||
947 | /* Walk the entities list and restore controls when possible. */ | ||
948 | list_for_each_entry(entity, &dev->entities, list) { | ||
949 | |||
950 | for (i = 0; i < entity->ncontrols; ++i) { | ||
951 | ctrl = &entity->controls[i]; | ||
952 | |||
953 | if (ctrl->info == NULL || !ctrl->modified || | ||
954 | (ctrl->info->flags & UVC_CONTROL_RESTORE) == 0) | ||
955 | continue; | ||
956 | |||
957 | printk(KERN_INFO "restoring control " UVC_GUID_FORMAT | ||
958 | "/%u/%u\n", UVC_GUID_ARGS(ctrl->info->entity), | ||
959 | ctrl->info->index, ctrl->info->selector); | ||
960 | ctrl->dirty = 1; | ||
961 | } | ||
962 | |||
963 | ret = uvc_ctrl_commit_entity(dev, entity, 0); | ||
964 | if (ret < 0) | ||
965 | return ret; | ||
966 | } | ||
967 | |||
968 | return 0; | ||
969 | } | ||
970 | |||
971 | /* -------------------------------------------------------------------------- | ||
972 | * Control and mapping handling | ||
973 | */ | ||
974 | |||
975 | static void uvc_ctrl_add_ctrl(struct uvc_device *dev, | ||
976 | struct uvc_control_info *info) | ||
977 | { | ||
978 | struct uvc_entity *entity; | ||
979 | struct uvc_control *ctrl = NULL; | ||
980 | int ret, found = 0; | ||
981 | unsigned int i; | ||
982 | |||
983 | list_for_each_entry(entity, &dev->entities, list) { | ||
984 | if (!uvc_entity_match_guid(entity, info->entity)) | ||
985 | continue; | ||
986 | |||
987 | for (i = 0; i < entity->ncontrols; ++i) { | ||
988 | ctrl = &entity->controls[i]; | ||
989 | if (ctrl->index == info->index) { | ||
990 | found = 1; | ||
991 | break; | ||
992 | } | ||
993 | } | ||
994 | |||
995 | if (found) | ||
996 | break; | ||
997 | } | ||
998 | |||
999 | if (!found) | ||
1000 | return; | ||
1001 | |||
1002 | if (UVC_ENTITY_TYPE(entity) == VC_EXTENSION_UNIT) { | ||
1003 | /* Check if the device control information and length match | ||
1004 | * the user supplied information. | ||
1005 | */ | ||
1006 | __u32 flags; | ||
1007 | __le16 size; | ||
1008 | __u8 inf; | ||
1009 | |||
1010 | if ((ret = uvc_query_ctrl(dev, GET_LEN, ctrl->entity->id, | ||
1011 | dev->intfnum, info->selector, (__u8 *)&size, 2)) < 0) { | ||
1012 | uvc_trace(UVC_TRACE_CONTROL, "GET_LEN failed on " | ||
1013 | "control " UVC_GUID_FORMAT "/%u (%d).\n", | ||
1014 | UVC_GUID_ARGS(info->entity), info->selector, | ||
1015 | ret); | ||
1016 | return; | ||
1017 | } | ||
1018 | |||
1019 | if (info->size != le16_to_cpu(size)) { | ||
1020 | uvc_trace(UVC_TRACE_CONTROL, "Control " UVC_GUID_FORMAT | ||
1021 | "/%u size doesn't match user supplied " | ||
1022 | "value.\n", UVC_GUID_ARGS(info->entity), | ||
1023 | info->selector); | ||
1024 | return; | ||
1025 | } | ||
1026 | |||
1027 | if ((ret = uvc_query_ctrl(dev, GET_INFO, ctrl->entity->id, | ||
1028 | dev->intfnum, info->selector, &inf, 1)) < 0) { | ||
1029 | uvc_trace(UVC_TRACE_CONTROL, "GET_INFO failed on " | ||
1030 | "control " UVC_GUID_FORMAT "/%u (%d).\n", | ||
1031 | UVC_GUID_ARGS(info->entity), info->selector, | ||
1032 | ret); | ||
1033 | return; | ||
1034 | } | ||
1035 | |||
1036 | flags = info->flags; | ||
1037 | if (((flags & UVC_CONTROL_GET_CUR) && !(inf & (1 << 0))) || | ||
1038 | ((flags & UVC_CONTROL_SET_CUR) && !(inf & (1 << 1)))) { | ||
1039 | uvc_trace(UVC_TRACE_CONTROL, "Control " | ||
1040 | UVC_GUID_FORMAT "/%u flags don't match " | ||
1041 | "supported operations.\n", | ||
1042 | UVC_GUID_ARGS(info->entity), info->selector); | ||
1043 | return; | ||
1044 | } | ||
1045 | } | ||
1046 | |||
1047 | ctrl->info = info; | ||
1048 | ctrl->data = kmalloc(ctrl->info->size * UVC_CTRL_NDATA, GFP_KERNEL); | ||
1049 | uvc_trace(UVC_TRACE_CONTROL, "Added control " UVC_GUID_FORMAT "/%u " | ||
1050 | "to device %s entity %u\n", UVC_GUID_ARGS(ctrl->info->entity), | ||
1051 | ctrl->info->selector, dev->udev->devpath, entity->id); | ||
1052 | } | ||
1053 | |||
1054 | /* | ||
1055 | * Add an item to the UVC control information list, and instantiate a control | ||
1056 | * structure for each device that supports the control. | ||
1057 | */ | ||
1058 | int uvc_ctrl_add_info(struct uvc_control_info *info) | ||
1059 | { | ||
1060 | struct uvc_control_info *ctrl; | ||
1061 | struct uvc_device *dev; | ||
1062 | int ret = 0; | ||
1063 | |||
1064 | /* Find matching controls by walking the devices, entities and | ||
1065 | * controls list. | ||
1066 | */ | ||
1067 | mutex_lock(&uvc_driver.ctrl_mutex); | ||
1068 | |||
1069 | /* First check if the list contains a control matching the new one. | ||
1070 | * Bail out if it does. | ||
1071 | */ | ||
1072 | list_for_each_entry(ctrl, &uvc_driver.controls, list) { | ||
1073 | if (memcmp(ctrl->entity, info->entity, 16)) | ||
1074 | continue; | ||
1075 | |||
1076 | if (ctrl->selector == info->selector) { | ||
1077 | uvc_trace(UVC_TRACE_CONTROL, "Control " | ||
1078 | UVC_GUID_FORMAT "/%u is already defined.\n", | ||
1079 | UVC_GUID_ARGS(info->entity), info->selector); | ||
1080 | ret = -EEXIST; | ||
1081 | goto end; | ||
1082 | } | ||
1083 | if (ctrl->index == info->index) { | ||
1084 | uvc_trace(UVC_TRACE_CONTROL, "Control " | ||
1085 | UVC_GUID_FORMAT "/%u would overwrite index " | ||
1086 | "%d.\n", UVC_GUID_ARGS(info->entity), | ||
1087 | info->selector, info->index); | ||
1088 | ret = -EEXIST; | ||
1089 | goto end; | ||
1090 | } | ||
1091 | } | ||
1092 | |||
1093 | list_for_each_entry(dev, &uvc_driver.devices, list) | ||
1094 | uvc_ctrl_add_ctrl(dev, info); | ||
1095 | |||
1096 | INIT_LIST_HEAD(&info->mappings); | ||
1097 | list_add_tail(&info->list, &uvc_driver.controls); | ||
1098 | end: | ||
1099 | mutex_unlock(&uvc_driver.ctrl_mutex); | ||
1100 | return ret; | ||
1101 | } | ||
1102 | |||
1103 | int uvc_ctrl_add_mapping(struct uvc_control_mapping *mapping) | ||
1104 | { | ||
1105 | struct uvc_control_info *info; | ||
1106 | struct uvc_control_mapping *map; | ||
1107 | int ret = -EINVAL; | ||
1108 | |||
1109 | if (mapping->id & ~V4L2_CTRL_ID_MASK) { | ||
1110 | uvc_trace(UVC_TRACE_CONTROL, "Can't add mapping '%s' with " | ||
1111 | "invalid control id 0x%08x\n", mapping->name, | ||
1112 | mapping->id); | ||
1113 | return -EINVAL; | ||
1114 | } | ||
1115 | |||
1116 | mutex_lock(&uvc_driver.ctrl_mutex); | ||
1117 | list_for_each_entry(info, &uvc_driver.controls, list) { | ||
1118 | if (memcmp(info->entity, mapping->entity, 16) || | ||
1119 | info->selector != mapping->selector) | ||
1120 | continue; | ||
1121 | |||
1122 | if (info->size * 8 < mapping->size + mapping->offset) { | ||
1123 | uvc_trace(UVC_TRACE_CONTROL, "Mapping '%s' would " | ||
1124 | "overflow control " UVC_GUID_FORMAT "/%u\n", | ||
1125 | mapping->name, UVC_GUID_ARGS(info->entity), | ||
1126 | info->selector); | ||
1127 | ret = -EOVERFLOW; | ||
1128 | goto end; | ||
1129 | } | ||
1130 | |||
1131 | /* Check if the list contains a mapping matching the new one. | ||
1132 | * Bail out if it does. | ||
1133 | */ | ||
1134 | list_for_each_entry(map, &info->mappings, list) { | ||
1135 | if (map->id == mapping->id) { | ||
1136 | uvc_trace(UVC_TRACE_CONTROL, "Mapping '%s' is " | ||
1137 | "already defined.\n", mapping->name); | ||
1138 | ret = -EEXIST; | ||
1139 | goto end; | ||
1140 | } | ||
1141 | } | ||
1142 | |||
1143 | mapping->ctrl = info; | ||
1144 | list_add_tail(&mapping->list, &info->mappings); | ||
1145 | uvc_trace(UVC_TRACE_CONTROL, "Adding mapping %s to control " | ||
1146 | UVC_GUID_FORMAT "/%u.\n", mapping->name, | ||
1147 | UVC_GUID_ARGS(info->entity), info->selector); | ||
1148 | |||
1149 | ret = 0; | ||
1150 | break; | ||
1151 | } | ||
1152 | end: | ||
1153 | mutex_unlock(&uvc_driver.ctrl_mutex); | ||
1154 | return ret; | ||
1155 | } | ||
1156 | |||
1157 | /* | ||
1158 | * Initialize device controls. | ||
1159 | */ | ||
1160 | int uvc_ctrl_init_device(struct uvc_device *dev) | ||
1161 | { | ||
1162 | struct uvc_control_info *info; | ||
1163 | struct uvc_control *ctrl; | ||
1164 | struct uvc_entity *entity; | ||
1165 | unsigned int i; | ||
1166 | |||
1167 | /* Walk the entities list and instantiate controls */ | ||
1168 | list_for_each_entry(entity, &dev->entities, list) { | ||
1169 | unsigned int bControlSize = 0, ncontrols = 0; | ||
1170 | __u8 *bmControls = NULL; | ||
1171 | |||
1172 | if (UVC_ENTITY_TYPE(entity) == VC_EXTENSION_UNIT) { | ||
1173 | bmControls = entity->extension.bmControls; | ||
1174 | bControlSize = entity->extension.bControlSize; | ||
1175 | } else if (UVC_ENTITY_TYPE(entity) == VC_PROCESSING_UNIT) { | ||
1176 | bmControls = entity->processing.bmControls; | ||
1177 | bControlSize = entity->processing.bControlSize; | ||
1178 | } else if (UVC_ENTITY_TYPE(entity) == ITT_CAMERA) { | ||
1179 | bmControls = entity->camera.bmControls; | ||
1180 | bControlSize = entity->camera.bControlSize; | ||
1181 | } | ||
1182 | |||
1183 | for (i = 0; i < bControlSize; ++i) | ||
1184 | ncontrols += hweight8(bmControls[i]); | ||
1185 | |||
1186 | if (ncontrols == 0) | ||
1187 | continue; | ||
1188 | |||
1189 | entity->controls = kzalloc(ncontrols*sizeof *ctrl, GFP_KERNEL); | ||
1190 | if (entity->controls == NULL) | ||
1191 | return -ENOMEM; | ||
1192 | |||
1193 | entity->ncontrols = ncontrols; | ||
1194 | |||
1195 | ctrl = entity->controls; | ||
1196 | for (i = 0; i < bControlSize * 8; ++i) { | ||
1197 | if (uvc_get_bit(bmControls, i) == 0) | ||
1198 | continue; | ||
1199 | |||
1200 | ctrl->entity = entity; | ||
1201 | ctrl->index = i; | ||
1202 | ctrl++; | ||
1203 | } | ||
1204 | } | ||
1205 | |||
1206 | /* Walk the controls info list and associate them with the device | ||
1207 | * controls, then add the device to the global device list. This has | ||
1208 | * to be done while holding the controls lock, to make sure | ||
1209 | * uvc_ctrl_add_info() will not get called in-between. | ||
1210 | */ | ||
1211 | mutex_lock(&uvc_driver.ctrl_mutex); | ||
1212 | list_for_each_entry(info, &uvc_driver.controls, list) | ||
1213 | uvc_ctrl_add_ctrl(dev, info); | ||
1214 | |||
1215 | list_add_tail(&dev->list, &uvc_driver.devices); | ||
1216 | mutex_unlock(&uvc_driver.ctrl_mutex); | ||
1217 | |||
1218 | return 0; | ||
1219 | } | ||
1220 | |||
1221 | /* | ||
1222 | * Cleanup device controls. | ||
1223 | */ | ||
1224 | void uvc_ctrl_cleanup_device(struct uvc_device *dev) | ||
1225 | { | ||
1226 | struct uvc_entity *entity; | ||
1227 | unsigned int i; | ||
1228 | |||
1229 | /* Remove the device from the global devices list */ | ||
1230 | mutex_lock(&uvc_driver.ctrl_mutex); | ||
1231 | if (dev->list.next != NULL) | ||
1232 | list_del(&dev->list); | ||
1233 | mutex_unlock(&uvc_driver.ctrl_mutex); | ||
1234 | |||
1235 | list_for_each_entry(entity, &dev->entities, list) { | ||
1236 | for (i = 0; i < entity->ncontrols; ++i) | ||
1237 | kfree(entity->controls[i].data); | ||
1238 | |||
1239 | kfree(entity->controls); | ||
1240 | } | ||
1241 | } | ||
1242 | |||
1243 | void uvc_ctrl_init(void) | ||
1244 | { | ||
1245 | struct uvc_control_info *ctrl = uvc_ctrls; | ||
1246 | struct uvc_control_info *cend = ctrl + ARRAY_SIZE(uvc_ctrls); | ||
1247 | struct uvc_control_mapping *mapping = uvc_ctrl_mappings; | ||
1248 | struct uvc_control_mapping *mend = | ||
1249 | mapping + ARRAY_SIZE(uvc_ctrl_mappings); | ||
1250 | |||
1251 | for (; ctrl < cend; ++ctrl) | ||
1252 | uvc_ctrl_add_info(ctrl); | ||
1253 | |||
1254 | for (; mapping < mend; ++mapping) | ||
1255 | uvc_ctrl_add_mapping(mapping); | ||
1256 | } | ||
diff --git a/drivers/media/video/uvc/uvc_driver.c b/drivers/media/video/uvc/uvc_driver.c new file mode 100644 index 000000000000..60ced589f898 --- /dev/null +++ b/drivers/media/video/uvc/uvc_driver.c | |||
@@ -0,0 +1,1955 @@ | |||
1 | /* | ||
2 | * uvc_driver.c -- USB Video Class driver | ||
3 | * | ||
4 | * Copyright (C) 2005-2008 | ||
5 | * Laurent Pinchart (laurent.pinchart@skynet.be) | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | /* | ||
15 | * This driver aims to support video input devices compliant with the 'USB | ||
16 | * Video Class' specification. | ||
17 | * | ||
18 | * The driver doesn't support the deprecated v4l1 interface. It implements the | ||
19 | * mmap capture method only, and doesn't do any image format conversion in | ||
20 | * software. If your user-space application doesn't support YUYV or MJPEG, fix | ||
21 | * it :-). Please note that the MJPEG data have been stripped from their | ||
22 | * Huffman tables (DHT marker), you will need to add it back if your JPEG | ||
23 | * codec can't handle MJPEG data. | ||
24 | */ | ||
25 | |||
26 | #include <linux/kernel.h> | ||
27 | #include <linux/version.h> | ||
28 | #include <linux/list.h> | ||
29 | #include <linux/module.h> | ||
30 | #include <linux/usb.h> | ||
31 | #include <linux/videodev2.h> | ||
32 | #include <linux/vmalloc.h> | ||
33 | #include <linux/wait.h> | ||
34 | #include <asm/atomic.h> | ||
35 | |||
36 | #include <media/v4l2-common.h> | ||
37 | |||
38 | #include "uvcvideo.h" | ||
39 | |||
40 | #define DRIVER_AUTHOR "Laurent Pinchart <laurent.pinchart@skynet.be>" | ||
41 | #define DRIVER_DESC "USB Video Class driver" | ||
42 | #ifndef DRIVER_VERSION | ||
43 | #define DRIVER_VERSION "v0.1.0" | ||
44 | #endif | ||
45 | |||
46 | static unsigned int uvc_quirks_param; | ||
47 | unsigned int uvc_trace_param; | ||
48 | |||
49 | /* ------------------------------------------------------------------------ | ||
50 | * Control, formats, ... | ||
51 | */ | ||
52 | |||
53 | static struct uvc_format_desc uvc_fmts[] = { | ||
54 | { | ||
55 | .name = "YUV 4:2:2 (YUYV)", | ||
56 | .guid = UVC_GUID_FORMAT_YUY2, | ||
57 | .fcc = V4L2_PIX_FMT_YUYV, | ||
58 | }, | ||
59 | { | ||
60 | .name = "YUV 4:2:0 (NV12)", | ||
61 | .guid = UVC_GUID_FORMAT_NV12, | ||
62 | .fcc = V4L2_PIX_FMT_NV12, | ||
63 | }, | ||
64 | { | ||
65 | .name = "MJPEG", | ||
66 | .guid = UVC_GUID_FORMAT_MJPEG, | ||
67 | .fcc = V4L2_PIX_FMT_MJPEG, | ||
68 | }, | ||
69 | { | ||
70 | .name = "YVU 4:2:0 (YV12)", | ||
71 | .guid = UVC_GUID_FORMAT_YV12, | ||
72 | .fcc = V4L2_PIX_FMT_YVU420, | ||
73 | }, | ||
74 | { | ||
75 | .name = "YUV 4:2:0 (I420)", | ||
76 | .guid = UVC_GUID_FORMAT_I420, | ||
77 | .fcc = V4L2_PIX_FMT_YUV420, | ||
78 | }, | ||
79 | { | ||
80 | .name = "YUV 4:2:2 (UYVY)", | ||
81 | .guid = UVC_GUID_FORMAT_UYVY, | ||
82 | .fcc = V4L2_PIX_FMT_UYVY, | ||
83 | }, | ||
84 | { | ||
85 | .name = "Greyscale", | ||
86 | .guid = UVC_GUID_FORMAT_Y800, | ||
87 | .fcc = V4L2_PIX_FMT_GREY, | ||
88 | }, | ||
89 | { | ||
90 | .name = "RGB Bayer", | ||
91 | .guid = UVC_GUID_FORMAT_BY8, | ||
92 | .fcc = V4L2_PIX_FMT_SBGGR8, | ||
93 | }, | ||
94 | }; | ||
95 | |||
96 | /* ------------------------------------------------------------------------ | ||
97 | * Utility functions | ||
98 | */ | ||
99 | |||
100 | struct usb_host_endpoint *uvc_find_endpoint(struct usb_host_interface *alts, | ||
101 | __u8 epaddr) | ||
102 | { | ||
103 | struct usb_host_endpoint *ep; | ||
104 | unsigned int i; | ||
105 | |||
106 | for (i = 0; i < alts->desc.bNumEndpoints; ++i) { | ||
107 | ep = &alts->endpoint[i]; | ||
108 | if (ep->desc.bEndpointAddress == epaddr) | ||
109 | return ep; | ||
110 | } | ||
111 | |||
112 | return NULL; | ||
113 | } | ||
114 | |||
115 | static struct uvc_format_desc *uvc_format_by_guid(const __u8 guid[16]) | ||
116 | { | ||
117 | unsigned int len = ARRAY_SIZE(uvc_fmts); | ||
118 | unsigned int i; | ||
119 | |||
120 | for (i = 0; i < len; ++i) { | ||
121 | if (memcmp(guid, uvc_fmts[i].guid, 16) == 0) | ||
122 | return &uvc_fmts[i]; | ||
123 | } | ||
124 | |||
125 | return NULL; | ||
126 | } | ||
127 | |||
128 | static __u32 uvc_colorspace(const __u8 primaries) | ||
129 | { | ||
130 | static const __u8 colorprimaries[] = { | ||
131 | 0, | ||
132 | V4L2_COLORSPACE_SRGB, | ||
133 | V4L2_COLORSPACE_470_SYSTEM_M, | ||
134 | V4L2_COLORSPACE_470_SYSTEM_BG, | ||
135 | V4L2_COLORSPACE_SMPTE170M, | ||
136 | V4L2_COLORSPACE_SMPTE240M, | ||
137 | }; | ||
138 | |||
139 | if (primaries < ARRAY_SIZE(colorprimaries)) | ||
140 | return colorprimaries[primaries]; | ||
141 | |||
142 | return 0; | ||
143 | } | ||
144 | |||
145 | /* Simplify a fraction using a simple continued fraction decomposition. The | ||
146 | * idea here is to convert fractions such as 333333/10000000 to 1/30 using | ||
147 | * 32 bit arithmetic only. The algorithm is not perfect and relies upon two | ||
148 | * arbitrary parameters to remove non-significative terms from the simple | ||
149 | * continued fraction decomposition. Using 8 and 333 for n_terms and threshold | ||
150 | * respectively seems to give nice results. | ||
151 | */ | ||
152 | void uvc_simplify_fraction(uint32_t *numerator, uint32_t *denominator, | ||
153 | unsigned int n_terms, unsigned int threshold) | ||
154 | { | ||
155 | uint32_t *an; | ||
156 | uint32_t x, y, r; | ||
157 | unsigned int i, n; | ||
158 | |||
159 | an = kmalloc(n_terms * sizeof *an, GFP_KERNEL); | ||
160 | if (an == NULL) | ||
161 | return; | ||
162 | |||
163 | /* Convert the fraction to a simple continued fraction. See | ||
164 | * http://mathforum.org/dr.math/faq/faq.fractions.html | ||
165 | * Stop if the current term is bigger than or equal to the given | ||
166 | * threshold. | ||
167 | */ | ||
168 | x = *numerator; | ||
169 | y = *denominator; | ||
170 | |||
171 | for (n = 0; n < n_terms && y != 0; ++n) { | ||
172 | an[n] = x / y; | ||
173 | if (an[n] >= threshold) { | ||
174 | if (n < 2) | ||
175 | n++; | ||
176 | break; | ||
177 | } | ||
178 | |||
179 | r = x - an[n] * y; | ||
180 | x = y; | ||
181 | y = r; | ||
182 | } | ||
183 | |||
184 | /* Expand the simple continued fraction back to an integer fraction. */ | ||
185 | x = 0; | ||
186 | y = 1; | ||
187 | |||
188 | for (i = n; i > 0; --i) { | ||
189 | r = y; | ||
190 | y = an[i-1] * y + x; | ||
191 | x = r; | ||
192 | } | ||
193 | |||
194 | *numerator = y; | ||
195 | *denominator = x; | ||
196 | kfree(an); | ||
197 | } | ||
198 | |||
199 | /* Convert a fraction to a frame interval in 100ns multiples. The idea here is | ||
200 | * to compute numerator / denominator * 10000000 using 32 bit fixed point | ||
201 | * arithmetic only. | ||
202 | */ | ||
203 | uint32_t uvc_fraction_to_interval(uint32_t numerator, uint32_t denominator) | ||
204 | { | ||
205 | uint32_t multiplier; | ||
206 | |||
207 | /* Saturate the result if the operation would overflow. */ | ||
208 | if (denominator == 0 || | ||
209 | numerator/denominator >= ((uint32_t)-1)/10000000) | ||
210 | return (uint32_t)-1; | ||
211 | |||
212 | /* Divide both the denominator and the multiplier by two until | ||
213 | * numerator * multiplier doesn't overflow. If anyone knows a better | ||
214 | * algorithm please let me know. | ||
215 | */ | ||
216 | multiplier = 10000000; | ||
217 | while (numerator > ((uint32_t)-1)/multiplier) { | ||
218 | multiplier /= 2; | ||
219 | denominator /= 2; | ||
220 | } | ||
221 | |||
222 | return denominator ? numerator * multiplier / denominator : 0; | ||
223 | } | ||
224 | |||
225 | /* ------------------------------------------------------------------------ | ||
226 | * Terminal and unit management | ||
227 | */ | ||
228 | |||
229 | static struct uvc_entity *uvc_entity_by_id(struct uvc_device *dev, int id) | ||
230 | { | ||
231 | struct uvc_entity *entity; | ||
232 | |||
233 | list_for_each_entry(entity, &dev->entities, list) { | ||
234 | if (entity->id == id) | ||
235 | return entity; | ||
236 | } | ||
237 | |||
238 | return NULL; | ||
239 | } | ||
240 | |||
241 | static struct uvc_entity *uvc_entity_by_reference(struct uvc_device *dev, | ||
242 | int id, struct uvc_entity *entity) | ||
243 | { | ||
244 | unsigned int i; | ||
245 | |||
246 | if (entity == NULL) | ||
247 | entity = list_entry(&dev->entities, struct uvc_entity, list); | ||
248 | |||
249 | list_for_each_entry_continue(entity, &dev->entities, list) { | ||
250 | switch (UVC_ENTITY_TYPE(entity)) { | ||
251 | case TT_STREAMING: | ||
252 | if (entity->output.bSourceID == id) | ||
253 | return entity; | ||
254 | break; | ||
255 | |||
256 | case VC_PROCESSING_UNIT: | ||
257 | if (entity->processing.bSourceID == id) | ||
258 | return entity; | ||
259 | break; | ||
260 | |||
261 | case VC_SELECTOR_UNIT: | ||
262 | for (i = 0; i < entity->selector.bNrInPins; ++i) | ||
263 | if (entity->selector.baSourceID[i] == id) | ||
264 | return entity; | ||
265 | break; | ||
266 | |||
267 | case VC_EXTENSION_UNIT: | ||
268 | for (i = 0; i < entity->extension.bNrInPins; ++i) | ||
269 | if (entity->extension.baSourceID[i] == id) | ||
270 | return entity; | ||
271 | break; | ||
272 | } | ||
273 | } | ||
274 | |||
275 | return NULL; | ||
276 | } | ||
277 | |||
278 | /* ------------------------------------------------------------------------ | ||
279 | * Descriptors handling | ||
280 | */ | ||
281 | |||
282 | static int uvc_parse_format(struct uvc_device *dev, | ||
283 | struct uvc_streaming *streaming, struct uvc_format *format, | ||
284 | __u32 **intervals, unsigned char *buffer, int buflen) | ||
285 | { | ||
286 | struct usb_interface *intf = streaming->intf; | ||
287 | struct usb_host_interface *alts = intf->cur_altsetting; | ||
288 | struct uvc_format_desc *fmtdesc; | ||
289 | struct uvc_frame *frame; | ||
290 | const unsigned char *start = buffer; | ||
291 | unsigned int interval; | ||
292 | unsigned int i, n; | ||
293 | __u8 ftype; | ||
294 | |||
295 | format->type = buffer[2]; | ||
296 | format->index = buffer[3]; | ||
297 | |||
298 | switch (buffer[2]) { | ||
299 | case VS_FORMAT_UNCOMPRESSED: | ||
300 | case VS_FORMAT_FRAME_BASED: | ||
301 | if (buflen < 27) { | ||
302 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming" | ||
303 | "interface %d FORMAT error\n", | ||
304 | dev->udev->devnum, | ||
305 | alts->desc.bInterfaceNumber); | ||
306 | return -EINVAL; | ||
307 | } | ||
308 | |||
309 | /* Find the format descriptor from its GUID. */ | ||
310 | fmtdesc = uvc_format_by_guid(&buffer[5]); | ||
311 | |||
312 | if (fmtdesc != NULL) { | ||
313 | strncpy(format->name, fmtdesc->name, | ||
314 | sizeof format->name); | ||
315 | format->fcc = fmtdesc->fcc; | ||
316 | } else { | ||
317 | uvc_printk(KERN_INFO, "Unknown video format " | ||
318 | UVC_GUID_FORMAT "\n", | ||
319 | UVC_GUID_ARGS(&buffer[5])); | ||
320 | snprintf(format->name, sizeof format->name, | ||
321 | UVC_GUID_FORMAT, UVC_GUID_ARGS(&buffer[5])); | ||
322 | format->fcc = 0; | ||
323 | } | ||
324 | |||
325 | format->bpp = buffer[21]; | ||
326 | if (buffer[2] == VS_FORMAT_UNCOMPRESSED) { | ||
327 | ftype = VS_FRAME_UNCOMPRESSED; | ||
328 | } else { | ||
329 | ftype = VS_FRAME_FRAME_BASED; | ||
330 | if (buffer[27]) | ||
331 | format->flags = UVC_FMT_FLAG_COMPRESSED; | ||
332 | } | ||
333 | break; | ||
334 | |||
335 | case VS_FORMAT_MJPEG: | ||
336 | if (buflen < 11) { | ||
337 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming" | ||
338 | "interface %d FORMAT error\n", | ||
339 | dev->udev->devnum, | ||
340 | alts->desc.bInterfaceNumber); | ||
341 | return -EINVAL; | ||
342 | } | ||
343 | |||
344 | strncpy(format->name, "MJPEG", sizeof format->name); | ||
345 | format->fcc = V4L2_PIX_FMT_MJPEG; | ||
346 | format->flags = UVC_FMT_FLAG_COMPRESSED; | ||
347 | format->bpp = 0; | ||
348 | ftype = VS_FRAME_MJPEG; | ||
349 | break; | ||
350 | |||
351 | case VS_FORMAT_DV: | ||
352 | if (buflen < 9) { | ||
353 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming" | ||
354 | "interface %d FORMAT error\n", | ||
355 | dev->udev->devnum, | ||
356 | alts->desc.bInterfaceNumber); | ||
357 | return -EINVAL; | ||
358 | } | ||
359 | |||
360 | switch (buffer[8] & 0x7f) { | ||
361 | case 0: | ||
362 | strncpy(format->name, "SD-DV", sizeof format->name); | ||
363 | break; | ||
364 | case 1: | ||
365 | strncpy(format->name, "SDL-DV", sizeof format->name); | ||
366 | break; | ||
367 | case 2: | ||
368 | strncpy(format->name, "HD-DV", sizeof format->name); | ||
369 | break; | ||
370 | default: | ||
371 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming" | ||
372 | "interface %d: unknown DV format %u\n", | ||
373 | dev->udev->devnum, | ||
374 | alts->desc.bInterfaceNumber, buffer[8]); | ||
375 | return -EINVAL; | ||
376 | } | ||
377 | |||
378 | strncat(format->name, buffer[8] & (1 << 7) ? " 60Hz" : " 50Hz", | ||
379 | sizeof format->name); | ||
380 | |||
381 | format->fcc = V4L2_PIX_FMT_DV; | ||
382 | format->flags = UVC_FMT_FLAG_COMPRESSED | UVC_FMT_FLAG_STREAM; | ||
383 | format->bpp = 0; | ||
384 | ftype = 0; | ||
385 | |||
386 | /* Create a dummy frame descriptor. */ | ||
387 | frame = &format->frame[0]; | ||
388 | memset(&format->frame[0], 0, sizeof format->frame[0]); | ||
389 | frame->bFrameIntervalType = 1; | ||
390 | frame->dwDefaultFrameInterval = 1; | ||
391 | frame->dwFrameInterval = *intervals; | ||
392 | *(*intervals)++ = 1; | ||
393 | format->nframes = 1; | ||
394 | break; | ||
395 | |||
396 | case VS_FORMAT_MPEG2TS: | ||
397 | case VS_FORMAT_STREAM_BASED: | ||
398 | /* Not supported yet. */ | ||
399 | default: | ||
400 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming" | ||
401 | "interface %d unsupported format %u\n", | ||
402 | dev->udev->devnum, alts->desc.bInterfaceNumber, | ||
403 | buffer[2]); | ||
404 | return -EINVAL; | ||
405 | } | ||
406 | |||
407 | uvc_trace(UVC_TRACE_DESCR, "Found format %s.\n", format->name); | ||
408 | |||
409 | buflen -= buffer[0]; | ||
410 | buffer += buffer[0]; | ||
411 | |||
412 | /* Parse the frame descriptors. Only uncompressed, MJPEG and frame | ||
413 | * based formats have frame descriptors. | ||
414 | */ | ||
415 | while (buflen > 2 && buffer[2] == ftype) { | ||
416 | frame = &format->frame[format->nframes]; | ||
417 | |||
418 | if (ftype != VS_FRAME_FRAME_BASED) | ||
419 | n = buflen > 25 ? buffer[25] : 0; | ||
420 | else | ||
421 | n = buflen > 21 ? buffer[21] : 0; | ||
422 | |||
423 | n = n ? n : 3; | ||
424 | |||
425 | if (buflen < 26 + 4*n) { | ||
426 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming" | ||
427 | "interface %d FRAME error\n", dev->udev->devnum, | ||
428 | alts->desc.bInterfaceNumber); | ||
429 | return -EINVAL; | ||
430 | } | ||
431 | |||
432 | frame->bFrameIndex = buffer[3]; | ||
433 | frame->bmCapabilities = buffer[4]; | ||
434 | frame->wWidth = le16_to_cpup((__le16 *)&buffer[5]); | ||
435 | frame->wHeight = le16_to_cpup((__le16 *)&buffer[7]); | ||
436 | frame->dwMinBitRate = le32_to_cpup((__le32 *)&buffer[9]); | ||
437 | frame->dwMaxBitRate = le32_to_cpup((__le32 *)&buffer[13]); | ||
438 | if (ftype != VS_FRAME_FRAME_BASED) { | ||
439 | frame->dwMaxVideoFrameBufferSize = | ||
440 | le32_to_cpup((__le32 *)&buffer[17]); | ||
441 | frame->dwDefaultFrameInterval = | ||
442 | le32_to_cpup((__le32 *)&buffer[21]); | ||
443 | frame->bFrameIntervalType = buffer[25]; | ||
444 | } else { | ||
445 | frame->dwMaxVideoFrameBufferSize = 0; | ||
446 | frame->dwDefaultFrameInterval = | ||
447 | le32_to_cpup((__le32 *)&buffer[17]); | ||
448 | frame->bFrameIntervalType = buffer[21]; | ||
449 | } | ||
450 | frame->dwFrameInterval = *intervals; | ||
451 | |||
452 | /* Several UVC chipsets screw up dwMaxVideoFrameBufferSize | ||
453 | * completely. Observed behaviours range from setting the | ||
454 | * value to 1.1x the actual frame size of hardwiring the | ||
455 | * 16 low bits to 0. This results in a higher than necessary | ||
456 | * memory usage as well as a wrong image size information. For | ||
457 | * uncompressed formats this can be fixed by computing the | ||
458 | * value from the frame size. | ||
459 | */ | ||
460 | if (!(format->flags & UVC_FMT_FLAG_COMPRESSED)) | ||
461 | frame->dwMaxVideoFrameBufferSize = format->bpp | ||
462 | * frame->wWidth * frame->wHeight / 8; | ||
463 | |||
464 | /* Some bogus devices report dwMinFrameInterval equal to | ||
465 | * dwMaxFrameInterval and have dwFrameIntervalStep set to | ||
466 | * zero. Setting all null intervals to 1 fixes the problem and | ||
467 | * some other divisions by zero which could happen. | ||
468 | */ | ||
469 | for (i = 0; i < n; ++i) { | ||
470 | interval = le32_to_cpup((__le32 *)&buffer[26+4*i]); | ||
471 | *(*intervals)++ = interval ? interval : 1; | ||
472 | } | ||
473 | |||
474 | /* Make sure that the default frame interval stays between | ||
475 | * the boundaries. | ||
476 | */ | ||
477 | n -= frame->bFrameIntervalType ? 1 : 2; | ||
478 | frame->dwDefaultFrameInterval = | ||
479 | min(frame->dwFrameInterval[n], | ||
480 | max(frame->dwFrameInterval[0], | ||
481 | frame->dwDefaultFrameInterval)); | ||
482 | |||
483 | uvc_trace(UVC_TRACE_DESCR, "- %ux%u (%u.%u fps)\n", | ||
484 | frame->wWidth, frame->wHeight, | ||
485 | 10000000/frame->dwDefaultFrameInterval, | ||
486 | (100000000/frame->dwDefaultFrameInterval)%10); | ||
487 | |||
488 | format->nframes++; | ||
489 | buflen -= buffer[0]; | ||
490 | buffer += buffer[0]; | ||
491 | } | ||
492 | |||
493 | if (buflen > 2 && buffer[2] == VS_STILL_IMAGE_FRAME) { | ||
494 | buflen -= buffer[0]; | ||
495 | buffer += buffer[0]; | ||
496 | } | ||
497 | |||
498 | if (buflen > 2 && buffer[2] == VS_COLORFORMAT) { | ||
499 | if (buflen < 6) { | ||
500 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming" | ||
501 | "interface %d COLORFORMAT error\n", | ||
502 | dev->udev->devnum, | ||
503 | alts->desc.bInterfaceNumber); | ||
504 | return -EINVAL; | ||
505 | } | ||
506 | |||
507 | format->colorspace = uvc_colorspace(buffer[3]); | ||
508 | |||
509 | buflen -= buffer[0]; | ||
510 | buffer += buffer[0]; | ||
511 | } | ||
512 | |||
513 | return buffer - start; | ||
514 | } | ||
515 | |||
516 | static int uvc_parse_streaming(struct uvc_device *dev, | ||
517 | struct usb_interface *intf) | ||
518 | { | ||
519 | struct uvc_streaming *streaming = NULL; | ||
520 | struct uvc_format *format; | ||
521 | struct uvc_frame *frame; | ||
522 | struct usb_host_interface *alts = &intf->altsetting[0]; | ||
523 | unsigned char *_buffer, *buffer = alts->extra; | ||
524 | int _buflen, buflen = alts->extralen; | ||
525 | unsigned int nformats = 0, nframes = 0, nintervals = 0; | ||
526 | unsigned int size, i, n, p; | ||
527 | __u32 *interval; | ||
528 | __u16 psize; | ||
529 | int ret = -EINVAL; | ||
530 | |||
531 | if (intf->cur_altsetting->desc.bInterfaceSubClass | ||
532 | != SC_VIDEOSTREAMING) { | ||
533 | uvc_trace(UVC_TRACE_DESCR, "device %d interface %d isn't a " | ||
534 | "video streaming interface\n", dev->udev->devnum, | ||
535 | intf->altsetting[0].desc.bInterfaceNumber); | ||
536 | return -EINVAL; | ||
537 | } | ||
538 | |||
539 | if (usb_driver_claim_interface(&uvc_driver.driver, intf, dev)) { | ||
540 | uvc_trace(UVC_TRACE_DESCR, "device %d interface %d is already " | ||
541 | "claimed\n", dev->udev->devnum, | ||
542 | intf->altsetting[0].desc.bInterfaceNumber); | ||
543 | return -EINVAL; | ||
544 | } | ||
545 | |||
546 | streaming = kzalloc(sizeof *streaming, GFP_KERNEL); | ||
547 | if (streaming == NULL) { | ||
548 | usb_driver_release_interface(&uvc_driver.driver, intf); | ||
549 | return -EINVAL; | ||
550 | } | ||
551 | |||
552 | mutex_init(&streaming->mutex); | ||
553 | streaming->intf = usb_get_intf(intf); | ||
554 | streaming->intfnum = intf->cur_altsetting->desc.bInterfaceNumber; | ||
555 | |||
556 | /* The Pico iMage webcam has its class-specific interface descriptors | ||
557 | * after the endpoint descriptors. | ||
558 | */ | ||
559 | if (buflen == 0) { | ||
560 | for (i = 0; i < alts->desc.bNumEndpoints; ++i) { | ||
561 | struct usb_host_endpoint *ep = &alts->endpoint[i]; | ||
562 | |||
563 | if (ep->extralen == 0) | ||
564 | continue; | ||
565 | |||
566 | if (ep->extralen > 2 && | ||
567 | ep->extra[1] == USB_DT_CS_INTERFACE) { | ||
568 | uvc_trace(UVC_TRACE_DESCR, "trying extra data " | ||
569 | "from endpoint %u.\n", i); | ||
570 | buffer = alts->endpoint[i].extra; | ||
571 | buflen = alts->endpoint[i].extralen; | ||
572 | break; | ||
573 | } | ||
574 | } | ||
575 | } | ||
576 | |||
577 | /* Skip the standard interface descriptors. */ | ||
578 | while (buflen > 2 && buffer[1] != USB_DT_CS_INTERFACE) { | ||
579 | buflen -= buffer[0]; | ||
580 | buffer += buffer[0]; | ||
581 | } | ||
582 | |||
583 | if (buflen <= 2) { | ||
584 | uvc_trace(UVC_TRACE_DESCR, "no class-specific streaming " | ||
585 | "interface descriptors found.\n"); | ||
586 | goto error; | ||
587 | } | ||
588 | |||
589 | /* Parse the header descriptor. */ | ||
590 | if (buffer[2] == VS_OUTPUT_HEADER) { | ||
591 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming interface " | ||
592 | "%d OUTPUT HEADER descriptor is not supported.\n", | ||
593 | dev->udev->devnum, alts->desc.bInterfaceNumber); | ||
594 | goto error; | ||
595 | } else if (buffer[2] == VS_INPUT_HEADER) { | ||
596 | p = buflen >= 5 ? buffer[3] : 0; | ||
597 | n = buflen >= 12 ? buffer[12] : 0; | ||
598 | |||
599 | if (buflen < 13 + p*n || buffer[2] != VS_INPUT_HEADER) { | ||
600 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming " | ||
601 | "interface %d INPUT HEADER descriptor is " | ||
602 | "invalid.\n", dev->udev->devnum, | ||
603 | alts->desc.bInterfaceNumber); | ||
604 | goto error; | ||
605 | } | ||
606 | |||
607 | streaming->header.bNumFormats = p; | ||
608 | streaming->header.bEndpointAddress = buffer[6]; | ||
609 | streaming->header.bmInfo = buffer[7]; | ||
610 | streaming->header.bTerminalLink = buffer[8]; | ||
611 | streaming->header.bStillCaptureMethod = buffer[9]; | ||
612 | streaming->header.bTriggerSupport = buffer[10]; | ||
613 | streaming->header.bTriggerUsage = buffer[11]; | ||
614 | streaming->header.bControlSize = n; | ||
615 | |||
616 | streaming->header.bmaControls = kmalloc(p*n, GFP_KERNEL); | ||
617 | if (streaming->header.bmaControls == NULL) { | ||
618 | ret = -ENOMEM; | ||
619 | goto error; | ||
620 | } | ||
621 | |||
622 | memcpy(streaming->header.bmaControls, &buffer[13], p*n); | ||
623 | } else { | ||
624 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming interface " | ||
625 | "%d HEADER descriptor not found.\n", dev->udev->devnum, | ||
626 | alts->desc.bInterfaceNumber); | ||
627 | goto error; | ||
628 | } | ||
629 | |||
630 | buflen -= buffer[0]; | ||
631 | buffer += buffer[0]; | ||
632 | |||
633 | _buffer = buffer; | ||
634 | _buflen = buflen; | ||
635 | |||
636 | /* Count the format and frame descriptors. */ | ||
637 | while (_buflen > 2) { | ||
638 | switch (_buffer[2]) { | ||
639 | case VS_FORMAT_UNCOMPRESSED: | ||
640 | case VS_FORMAT_MJPEG: | ||
641 | case VS_FORMAT_FRAME_BASED: | ||
642 | nformats++; | ||
643 | break; | ||
644 | |||
645 | case VS_FORMAT_DV: | ||
646 | /* DV format has no frame descriptor. We will create a | ||
647 | * dummy frame descriptor with a dummy frame interval. | ||
648 | */ | ||
649 | nformats++; | ||
650 | nframes++; | ||
651 | nintervals++; | ||
652 | break; | ||
653 | |||
654 | case VS_FORMAT_MPEG2TS: | ||
655 | case VS_FORMAT_STREAM_BASED: | ||
656 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming " | ||
657 | "interface %d FORMAT %u is not supported.\n", | ||
658 | dev->udev->devnum, | ||
659 | alts->desc.bInterfaceNumber, _buffer[2]); | ||
660 | break; | ||
661 | |||
662 | case VS_FRAME_UNCOMPRESSED: | ||
663 | case VS_FRAME_MJPEG: | ||
664 | nframes++; | ||
665 | if (_buflen > 25) | ||
666 | nintervals += _buffer[25] ? _buffer[25] : 3; | ||
667 | break; | ||
668 | |||
669 | case VS_FRAME_FRAME_BASED: | ||
670 | nframes++; | ||
671 | if (_buflen > 21) | ||
672 | nintervals += _buffer[21] ? _buffer[21] : 3; | ||
673 | break; | ||
674 | } | ||
675 | |||
676 | _buflen -= _buffer[0]; | ||
677 | _buffer += _buffer[0]; | ||
678 | } | ||
679 | |||
680 | if (nformats == 0) { | ||
681 | uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming interface " | ||
682 | "%d has no supported formats defined.\n", | ||
683 | dev->udev->devnum, alts->desc.bInterfaceNumber); | ||
684 | goto error; | ||
685 | } | ||
686 | |||
687 | size = nformats * sizeof *format + nframes * sizeof *frame | ||
688 | + nintervals * sizeof *interval; | ||
689 | format = kzalloc(size, GFP_KERNEL); | ||
690 | if (format == NULL) { | ||
691 | ret = -ENOMEM; | ||
692 | goto error; | ||
693 | } | ||
694 | |||
695 | frame = (struct uvc_frame *)&format[nformats]; | ||
696 | interval = (__u32 *)&frame[nframes]; | ||
697 | |||
698 | streaming->format = format; | ||
699 | streaming->nformats = nformats; | ||
700 | |||
701 | /* Parse the format descriptors. */ | ||
702 | while (buflen > 2) { | ||
703 | switch (buffer[2]) { | ||
704 | case VS_FORMAT_UNCOMPRESSED: | ||
705 | case VS_FORMAT_MJPEG: | ||
706 | case VS_FORMAT_DV: | ||
707 | case VS_FORMAT_FRAME_BASED: | ||
708 | format->frame = frame; | ||
709 | ret = uvc_parse_format(dev, streaming, format, | ||
710 | &interval, buffer, buflen); | ||
711 | if (ret < 0) | ||
712 | goto error; | ||
713 | |||
714 | frame += format->nframes; | ||
715 | format++; | ||
716 | |||
717 | buflen -= ret; | ||
718 | buffer += ret; | ||
719 | continue; | ||
720 | |||
721 | default: | ||
722 | break; | ||
723 | } | ||
724 | |||
725 | buflen -= buffer[0]; | ||
726 | buffer += buffer[0]; | ||
727 | } | ||
728 | |||
729 | /* Parse the alternate settings to find the maximum bandwidth. */ | ||
730 | for (i = 0; i < intf->num_altsetting; ++i) { | ||
731 | struct usb_host_endpoint *ep; | ||
732 | alts = &intf->altsetting[i]; | ||
733 | ep = uvc_find_endpoint(alts, | ||
734 | streaming->header.bEndpointAddress); | ||
735 | if (ep == NULL) | ||
736 | continue; | ||
737 | |||
738 | psize = le16_to_cpu(ep->desc.wMaxPacketSize); | ||
739 | psize = (psize & 0x07ff) * (1 + ((psize >> 11) & 3)); | ||
740 | if (psize > streaming->maxpsize) | ||
741 | streaming->maxpsize = psize; | ||
742 | } | ||
743 | |||
744 | list_add_tail(&streaming->list, &dev->streaming); | ||
745 | return 0; | ||
746 | |||
747 | error: | ||
748 | usb_driver_release_interface(&uvc_driver.driver, intf); | ||
749 | usb_put_intf(intf); | ||
750 | kfree(streaming->format); | ||
751 | kfree(streaming->header.bmaControls); | ||
752 | kfree(streaming); | ||
753 | return ret; | ||
754 | } | ||
755 | |||
756 | /* Parse vendor-specific extensions. */ | ||
757 | static int uvc_parse_vendor_control(struct uvc_device *dev, | ||
758 | const unsigned char *buffer, int buflen) | ||
759 | { | ||
760 | struct usb_device *udev = dev->udev; | ||
761 | struct usb_host_interface *alts = dev->intf->cur_altsetting; | ||
762 | struct uvc_entity *unit; | ||
763 | unsigned int n, p; | ||
764 | int handled = 0; | ||
765 | |||
766 | switch (le16_to_cpu(dev->udev->descriptor.idVendor)) { | ||
767 | case 0x046d: /* Logitech */ | ||
768 | if (buffer[1] != 0x41 || buffer[2] != 0x01) | ||
769 | break; | ||
770 | |||
771 | /* Logitech implements several vendor specific functions | ||
772 | * through vendor specific extension units (LXU). | ||
773 | * | ||
774 | * The LXU descriptors are similar to XU descriptors | ||
775 | * (see "USB Device Video Class for Video Devices", section | ||
776 | * 3.7.2.6 "Extension Unit Descriptor") with the following | ||
777 | * differences: | ||
778 | * | ||
779 | * ---------------------------------------------------------- | ||
780 | * 0 bLength 1 Number | ||
781 | * Size of this descriptor, in bytes: 24+p+n*2 | ||
782 | * ---------------------------------------------------------- | ||
783 | * 23+p+n bmControlsType N Bitmap | ||
784 | * Individual bits in the set are defined: | ||
785 | * 0: Absolute | ||
786 | * 1: Relative | ||
787 | * | ||
788 | * This bitset is mapped exactly the same as bmControls. | ||
789 | * ---------------------------------------------------------- | ||
790 | * 23+p+n*2 bReserved 1 Boolean | ||
791 | * ---------------------------------------------------------- | ||
792 | * 24+p+n*2 iExtension 1 Index | ||
793 | * Index of a string descriptor that describes this | ||
794 | * extension unit. | ||
795 | * ---------------------------------------------------------- | ||
796 | */ | ||
797 | p = buflen >= 22 ? buffer[21] : 0; | ||
798 | n = buflen >= 25 + p ? buffer[22+p] : 0; | ||
799 | |||
800 | if (buflen < 25 + p + 2*n) { | ||
801 | uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " | ||
802 | "interface %d EXTENSION_UNIT error\n", | ||
803 | udev->devnum, alts->desc.bInterfaceNumber); | ||
804 | break; | ||
805 | } | ||
806 | |||
807 | unit = kzalloc(sizeof *unit + p + 2*n, GFP_KERNEL); | ||
808 | if (unit == NULL) | ||
809 | return -ENOMEM; | ||
810 | |||
811 | unit->id = buffer[3]; | ||
812 | unit->type = VC_EXTENSION_UNIT; | ||
813 | memcpy(unit->extension.guidExtensionCode, &buffer[4], 16); | ||
814 | unit->extension.bNumControls = buffer[20]; | ||
815 | unit->extension.bNrInPins = | ||
816 | le16_to_cpup((__le16 *)&buffer[21]); | ||
817 | unit->extension.baSourceID = (__u8 *)unit + sizeof *unit; | ||
818 | memcpy(unit->extension.baSourceID, &buffer[22], p); | ||
819 | unit->extension.bControlSize = buffer[22+p]; | ||
820 | unit->extension.bmControls = (__u8 *)unit + sizeof *unit + p; | ||
821 | unit->extension.bmControlsType = (__u8 *)unit + sizeof *unit | ||
822 | + p + n; | ||
823 | memcpy(unit->extension.bmControls, &buffer[23+p], 2*n); | ||
824 | |||
825 | if (buffer[24+p+2*n] != 0) | ||
826 | usb_string(udev, buffer[24+p+2*n], unit->name, | ||
827 | sizeof unit->name); | ||
828 | else | ||
829 | sprintf(unit->name, "Extension %u", buffer[3]); | ||
830 | |||
831 | list_add_tail(&unit->list, &dev->entities); | ||
832 | handled = 1; | ||
833 | break; | ||
834 | } | ||
835 | |||
836 | return handled; | ||
837 | } | ||
838 | |||
839 | static int uvc_parse_standard_control(struct uvc_device *dev, | ||
840 | const unsigned char *buffer, int buflen) | ||
841 | { | ||
842 | struct usb_device *udev = dev->udev; | ||
843 | struct uvc_entity *unit, *term; | ||
844 | struct usb_interface *intf; | ||
845 | struct usb_host_interface *alts = dev->intf->cur_altsetting; | ||
846 | unsigned int i, n, p, len; | ||
847 | __u16 type; | ||
848 | |||
849 | switch (buffer[2]) { | ||
850 | case VC_HEADER: | ||
851 | n = buflen >= 12 ? buffer[11] : 0; | ||
852 | |||
853 | if (buflen < 12 || buflen < 12 + n) { | ||
854 | uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " | ||
855 | "interface %d HEADER error\n", udev->devnum, | ||
856 | alts->desc.bInterfaceNumber); | ||
857 | return -EINVAL; | ||
858 | } | ||
859 | |||
860 | dev->uvc_version = le16_to_cpup((__le16 *)&buffer[3]); | ||
861 | dev->clock_frequency = le32_to_cpup((__le32 *)&buffer[7]); | ||
862 | |||
863 | /* Parse all USB Video Streaming interfaces. */ | ||
864 | for (i = 0; i < n; ++i) { | ||
865 | intf = usb_ifnum_to_if(udev, buffer[12+i]); | ||
866 | if (intf == NULL) { | ||
867 | uvc_trace(UVC_TRACE_DESCR, "device %d " | ||
868 | "interface %d doesn't exists\n", | ||
869 | udev->devnum, i); | ||
870 | continue; | ||
871 | } | ||
872 | |||
873 | uvc_parse_streaming(dev, intf); | ||
874 | } | ||
875 | break; | ||
876 | |||
877 | case VC_INPUT_TERMINAL: | ||
878 | if (buflen < 8) { | ||
879 | uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " | ||
880 | "interface %d INPUT_TERMINAL error\n", | ||
881 | udev->devnum, alts->desc.bInterfaceNumber); | ||
882 | return -EINVAL; | ||
883 | } | ||
884 | |||
885 | /* Make sure the terminal type MSB is not null, otherwise it | ||
886 | * could be confused with a unit. | ||
887 | */ | ||
888 | type = le16_to_cpup((__le16 *)&buffer[4]); | ||
889 | if ((type & 0xff00) == 0) { | ||
890 | uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " | ||
891 | "interface %d INPUT_TERMINAL %d has invalid " | ||
892 | "type 0x%04x, skipping\n", udev->devnum, | ||
893 | alts->desc.bInterfaceNumber, | ||
894 | buffer[3], type); | ||
895 | return 0; | ||
896 | } | ||
897 | |||
898 | n = 0; | ||
899 | p = 0; | ||
900 | len = 8; | ||
901 | |||
902 | if (type == ITT_CAMERA) { | ||
903 | n = buflen >= 15 ? buffer[14] : 0; | ||
904 | len = 15; | ||
905 | |||
906 | } else if (type == ITT_MEDIA_TRANSPORT_INPUT) { | ||
907 | n = buflen >= 9 ? buffer[8] : 0; | ||
908 | p = buflen >= 10 + n ? buffer[9+n] : 0; | ||
909 | len = 10; | ||
910 | } | ||
911 | |||
912 | if (buflen < len + n + p) { | ||
913 | uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " | ||
914 | "interface %d INPUT_TERMINAL error\n", | ||
915 | udev->devnum, alts->desc.bInterfaceNumber); | ||
916 | return -EINVAL; | ||
917 | } | ||
918 | |||
919 | term = kzalloc(sizeof *term + n + p, GFP_KERNEL); | ||
920 | if (term == NULL) | ||
921 | return -ENOMEM; | ||
922 | |||
923 | term->id = buffer[3]; | ||
924 | term->type = type | UVC_TERM_INPUT; | ||
925 | |||
926 | if (UVC_ENTITY_TYPE(term) == ITT_CAMERA) { | ||
927 | term->camera.bControlSize = n; | ||
928 | term->camera.bmControls = (__u8 *)term + sizeof *term; | ||
929 | term->camera.wObjectiveFocalLengthMin = | ||
930 | le16_to_cpup((__le16 *)&buffer[8]); | ||
931 | term->camera.wObjectiveFocalLengthMax = | ||
932 | le16_to_cpup((__le16 *)&buffer[10]); | ||
933 | term->camera.wOcularFocalLength = | ||
934 | le16_to_cpup((__le16 *)&buffer[12]); | ||
935 | memcpy(term->camera.bmControls, &buffer[15], n); | ||
936 | } else if (UVC_ENTITY_TYPE(term) == ITT_MEDIA_TRANSPORT_INPUT) { | ||
937 | term->media.bControlSize = n; | ||
938 | term->media.bmControls = (__u8 *)term + sizeof *term; | ||
939 | term->media.bTransportModeSize = p; | ||
940 | term->media.bmTransportModes = (__u8 *)term | ||
941 | + sizeof *term + n; | ||
942 | memcpy(term->media.bmControls, &buffer[9], n); | ||
943 | memcpy(term->media.bmTransportModes, &buffer[10+n], p); | ||
944 | } | ||
945 | |||
946 | if (buffer[7] != 0) | ||
947 | usb_string(udev, buffer[7], term->name, | ||
948 | sizeof term->name); | ||
949 | else if (UVC_ENTITY_TYPE(term) == ITT_CAMERA) | ||
950 | sprintf(term->name, "Camera %u", buffer[3]); | ||
951 | else if (UVC_ENTITY_TYPE(term) == ITT_MEDIA_TRANSPORT_INPUT) | ||
952 | sprintf(term->name, "Media %u", buffer[3]); | ||
953 | else | ||
954 | sprintf(term->name, "Input %u", buffer[3]); | ||
955 | |||
956 | list_add_tail(&term->list, &dev->entities); | ||
957 | break; | ||
958 | |||
959 | case VC_OUTPUT_TERMINAL: | ||
960 | if (buflen < 9) { | ||
961 | uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " | ||
962 | "interface %d OUTPUT_TERMINAL error\n", | ||
963 | udev->devnum, alts->desc.bInterfaceNumber); | ||
964 | return -EINVAL; | ||
965 | } | ||
966 | |||
967 | /* Make sure the terminal type MSB is not null, otherwise it | ||
968 | * could be confused with a unit. | ||
969 | */ | ||
970 | type = le16_to_cpup((__le16 *)&buffer[4]); | ||
971 | if ((type & 0xff00) == 0) { | ||
972 | uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " | ||
973 | "interface %d OUTPUT_TERMINAL %d has invalid " | ||
974 | "type 0x%04x, skipping\n", udev->devnum, | ||
975 | alts->desc.bInterfaceNumber, buffer[3], type); | ||
976 | return 0; | ||
977 | } | ||
978 | |||
979 | term = kzalloc(sizeof *term, GFP_KERNEL); | ||
980 | if (term == NULL) | ||
981 | return -ENOMEM; | ||
982 | |||
983 | term->id = buffer[3]; | ||
984 | term->type = type | UVC_TERM_OUTPUT; | ||
985 | term->output.bSourceID = buffer[7]; | ||
986 | |||
987 | if (buffer[8] != 0) | ||
988 | usb_string(udev, buffer[8], term->name, | ||
989 | sizeof term->name); | ||
990 | else | ||
991 | sprintf(term->name, "Output %u", buffer[3]); | ||
992 | |||
993 | list_add_tail(&term->list, &dev->entities); | ||
994 | break; | ||
995 | |||
996 | case VC_SELECTOR_UNIT: | ||
997 | p = buflen >= 5 ? buffer[4] : 0; | ||
998 | |||
999 | if (buflen < 5 || buflen < 6 + p) { | ||
1000 | uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " | ||
1001 | "interface %d SELECTOR_UNIT error\n", | ||
1002 | udev->devnum, alts->desc.bInterfaceNumber); | ||
1003 | return -EINVAL; | ||
1004 | } | ||
1005 | |||
1006 | unit = kzalloc(sizeof *unit + p, GFP_KERNEL); | ||
1007 | if (unit == NULL) | ||
1008 | return -ENOMEM; | ||
1009 | |||
1010 | unit->id = buffer[3]; | ||
1011 | unit->type = buffer[2]; | ||
1012 | unit->selector.bNrInPins = buffer[4]; | ||
1013 | unit->selector.baSourceID = (__u8 *)unit + sizeof *unit; | ||
1014 | memcpy(unit->selector.baSourceID, &buffer[5], p); | ||
1015 | |||
1016 | if (buffer[5+p] != 0) | ||
1017 | usb_string(udev, buffer[5+p], unit->name, | ||
1018 | sizeof unit->name); | ||
1019 | else | ||
1020 | sprintf(unit->name, "Selector %u", buffer[3]); | ||
1021 | |||
1022 | list_add_tail(&unit->list, &dev->entities); | ||
1023 | break; | ||
1024 | |||
1025 | case VC_PROCESSING_UNIT: | ||
1026 | n = buflen >= 8 ? buffer[7] : 0; | ||
1027 | p = dev->uvc_version >= 0x0110 ? 10 : 9; | ||
1028 | |||
1029 | if (buflen < p + n) { | ||
1030 | uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " | ||
1031 | "interface %d PROCESSING_UNIT error\n", | ||
1032 | udev->devnum, alts->desc.bInterfaceNumber); | ||
1033 | return -EINVAL; | ||
1034 | } | ||
1035 | |||
1036 | unit = kzalloc(sizeof *unit + n, GFP_KERNEL); | ||
1037 | if (unit == NULL) | ||
1038 | return -ENOMEM; | ||
1039 | |||
1040 | unit->id = buffer[3]; | ||
1041 | unit->type = buffer[2]; | ||
1042 | unit->processing.bSourceID = buffer[4]; | ||
1043 | unit->processing.wMaxMultiplier = | ||
1044 | le16_to_cpup((__le16 *)&buffer[5]); | ||
1045 | unit->processing.bControlSize = buffer[7]; | ||
1046 | unit->processing.bmControls = (__u8 *)unit + sizeof *unit; | ||
1047 | memcpy(unit->processing.bmControls, &buffer[8], n); | ||
1048 | if (dev->uvc_version >= 0x0110) | ||
1049 | unit->processing.bmVideoStandards = buffer[9+n]; | ||
1050 | |||
1051 | if (buffer[8+n] != 0) | ||
1052 | usb_string(udev, buffer[8+n], unit->name, | ||
1053 | sizeof unit->name); | ||
1054 | else | ||
1055 | sprintf(unit->name, "Processing %u", buffer[3]); | ||
1056 | |||
1057 | list_add_tail(&unit->list, &dev->entities); | ||
1058 | break; | ||
1059 | |||
1060 | case VC_EXTENSION_UNIT: | ||
1061 | p = buflen >= 22 ? buffer[21] : 0; | ||
1062 | n = buflen >= 24 + p ? buffer[22+p] : 0; | ||
1063 | |||
1064 | if (buflen < 24 + p + n) { | ||
1065 | uvc_trace(UVC_TRACE_DESCR, "device %d videocontrol " | ||
1066 | "interface %d EXTENSION_UNIT error\n", | ||
1067 | udev->devnum, alts->desc.bInterfaceNumber); | ||
1068 | return -EINVAL; | ||
1069 | } | ||
1070 | |||
1071 | unit = kzalloc(sizeof *unit + p + n, GFP_KERNEL); | ||
1072 | if (unit == NULL) | ||
1073 | return -ENOMEM; | ||
1074 | |||
1075 | unit->id = buffer[3]; | ||
1076 | unit->type = buffer[2]; | ||
1077 | memcpy(unit->extension.guidExtensionCode, &buffer[4], 16); | ||
1078 | unit->extension.bNumControls = buffer[20]; | ||
1079 | unit->extension.bNrInPins = | ||
1080 | le16_to_cpup((__le16 *)&buffer[21]); | ||
1081 | unit->extension.baSourceID = (__u8 *)unit + sizeof *unit; | ||
1082 | memcpy(unit->extension.baSourceID, &buffer[22], p); | ||
1083 | unit->extension.bControlSize = buffer[22+p]; | ||
1084 | unit->extension.bmControls = (__u8 *)unit + sizeof *unit + p; | ||
1085 | memcpy(unit->extension.bmControls, &buffer[23+p], n); | ||
1086 | |||
1087 | if (buffer[23+p+n] != 0) | ||
1088 | usb_string(udev, buffer[23+p+n], unit->name, | ||
1089 | sizeof unit->name); | ||
1090 | else | ||
1091 | sprintf(unit->name, "Extension %u", buffer[3]); | ||
1092 | |||
1093 | list_add_tail(&unit->list, &dev->entities); | ||
1094 | break; | ||
1095 | |||
1096 | default: | ||
1097 | uvc_trace(UVC_TRACE_DESCR, "Found an unknown CS_INTERFACE " | ||
1098 | "descriptor (%u)\n", buffer[2]); | ||
1099 | break; | ||
1100 | } | ||
1101 | |||
1102 | return 0; | ||
1103 | } | ||
1104 | |||
1105 | static int uvc_parse_control(struct uvc_device *dev) | ||
1106 | { | ||
1107 | struct usb_host_interface *alts = dev->intf->cur_altsetting; | ||
1108 | unsigned char *buffer = alts->extra; | ||
1109 | int buflen = alts->extralen; | ||
1110 | int ret; | ||
1111 | |||
1112 | /* Parse the default alternate setting only, as the UVC specification | ||
1113 | * defines a single alternate setting, the default alternate setting | ||
1114 | * zero. | ||
1115 | */ | ||
1116 | |||
1117 | while (buflen > 2) { | ||
1118 | if (uvc_parse_vendor_control(dev, buffer, buflen) || | ||
1119 | buffer[1] != USB_DT_CS_INTERFACE) | ||
1120 | goto next_descriptor; | ||
1121 | |||
1122 | if ((ret = uvc_parse_standard_control(dev, buffer, buflen)) < 0) | ||
1123 | return ret; | ||
1124 | |||
1125 | next_descriptor: | ||
1126 | buflen -= buffer[0]; | ||
1127 | buffer += buffer[0]; | ||
1128 | } | ||
1129 | |||
1130 | /* Check if the optional status endpoint is present. */ | ||
1131 | if (alts->desc.bNumEndpoints == 1) { | ||
1132 | struct usb_host_endpoint *ep = &alts->endpoint[0]; | ||
1133 | struct usb_endpoint_descriptor *desc = &ep->desc; | ||
1134 | |||
1135 | if (usb_endpoint_is_int_in(desc) && | ||
1136 | le16_to_cpu(desc->wMaxPacketSize) >= 8 && | ||
1137 | desc->bInterval != 0) { | ||
1138 | uvc_trace(UVC_TRACE_DESCR, "Found a Status endpoint " | ||
1139 | "(addr %02x).\n", desc->bEndpointAddress); | ||
1140 | dev->int_ep = ep; | ||
1141 | } | ||
1142 | } | ||
1143 | |||
1144 | return 0; | ||
1145 | } | ||
1146 | |||
1147 | /* ------------------------------------------------------------------------ | ||
1148 | * USB probe and disconnect | ||
1149 | */ | ||
1150 | |||
1151 | /* | ||
1152 | * Unregister the video devices. | ||
1153 | */ | ||
1154 | static void uvc_unregister_video(struct uvc_device *dev) | ||
1155 | { | ||
1156 | if (dev->video.vdev) { | ||
1157 | if (dev->video.vdev->minor == -1) | ||
1158 | video_device_release(dev->video.vdev); | ||
1159 | else | ||
1160 | video_unregister_device(dev->video.vdev); | ||
1161 | dev->video.vdev = NULL; | ||
1162 | } | ||
1163 | } | ||
1164 | |||
1165 | /* | ||
1166 | * Scan the UVC descriptors to locate a chain starting at an Output Terminal | ||
1167 | * and containing the following units: | ||
1168 | * | ||
1169 | * - a USB Streaming Output Terminal | ||
1170 | * - zero or one Processing Unit | ||
1171 | * - zero, one or mode single-input Selector Units | ||
1172 | * - zero or one multiple-input Selector Units, provided all inputs are | ||
1173 | * connected to input terminals | ||
1174 | * - zero, one or mode single-input Extension Units | ||
1175 | * - one Camera Input Terminal, or one or more External terminals. | ||
1176 | * | ||
1177 | * A side forward scan is made on each detected entity to check for additional | ||
1178 | * extension units. | ||
1179 | */ | ||
1180 | static int uvc_scan_chain_entity(struct uvc_video_device *video, | ||
1181 | struct uvc_entity *entity) | ||
1182 | { | ||
1183 | switch (UVC_ENTITY_TYPE(entity)) { | ||
1184 | case VC_EXTENSION_UNIT: | ||
1185 | if (uvc_trace_param & UVC_TRACE_PROBE) | ||
1186 | printk(" <- XU %d", entity->id); | ||
1187 | |||
1188 | if (entity->extension.bNrInPins != 1) { | ||
1189 | uvc_trace(UVC_TRACE_DESCR, "Extension unit %d has more " | ||
1190 | "than 1 input pin.\n", entity->id); | ||
1191 | return -1; | ||
1192 | } | ||
1193 | |||
1194 | list_add_tail(&entity->chain, &video->extensions); | ||
1195 | break; | ||
1196 | |||
1197 | case VC_PROCESSING_UNIT: | ||
1198 | if (uvc_trace_param & UVC_TRACE_PROBE) | ||
1199 | printk(" <- PU %d", entity->id); | ||
1200 | |||
1201 | if (video->processing != NULL) { | ||
1202 | uvc_trace(UVC_TRACE_DESCR, "Found multiple " | ||
1203 | "Processing Units in chain.\n"); | ||
1204 | return -1; | ||
1205 | } | ||
1206 | |||
1207 | video->processing = entity; | ||
1208 | break; | ||
1209 | |||
1210 | case VC_SELECTOR_UNIT: | ||
1211 | if (uvc_trace_param & UVC_TRACE_PROBE) | ||
1212 | printk(" <- SU %d", entity->id); | ||
1213 | |||
1214 | /* Single-input selector units are ignored. */ | ||
1215 | if (entity->selector.bNrInPins == 1) | ||
1216 | break; | ||
1217 | |||
1218 | if (video->selector != NULL) { | ||
1219 | uvc_trace(UVC_TRACE_DESCR, "Found multiple Selector " | ||
1220 | "Units in chain.\n"); | ||
1221 | return -1; | ||
1222 | } | ||
1223 | |||
1224 | video->selector = entity; | ||
1225 | break; | ||
1226 | |||
1227 | case ITT_VENDOR_SPECIFIC: | ||
1228 | case ITT_CAMERA: | ||
1229 | case ITT_MEDIA_TRANSPORT_INPUT: | ||
1230 | if (uvc_trace_param & UVC_TRACE_PROBE) | ||
1231 | printk(" <- IT %d\n", entity->id); | ||
1232 | |||
1233 | list_add_tail(&entity->chain, &video->iterms); | ||
1234 | break; | ||
1235 | |||
1236 | default: | ||
1237 | uvc_trace(UVC_TRACE_DESCR, "Unsupported entity type " | ||
1238 | "0x%04x found in chain.\n", UVC_ENTITY_TYPE(entity)); | ||
1239 | return -1; | ||
1240 | } | ||
1241 | |||
1242 | return 0; | ||
1243 | } | ||
1244 | |||
1245 | static int uvc_scan_chain_forward(struct uvc_video_device *video, | ||
1246 | struct uvc_entity *entity, struct uvc_entity *prev) | ||
1247 | { | ||
1248 | struct uvc_entity *forward; | ||
1249 | int found; | ||
1250 | |||
1251 | /* Forward scan */ | ||
1252 | forward = NULL; | ||
1253 | found = 0; | ||
1254 | |||
1255 | while (1) { | ||
1256 | forward = uvc_entity_by_reference(video->dev, entity->id, | ||
1257 | forward); | ||
1258 | if (forward == NULL) | ||
1259 | break; | ||
1260 | |||
1261 | if (UVC_ENTITY_TYPE(forward) != VC_EXTENSION_UNIT || | ||
1262 | forward == prev) | ||
1263 | continue; | ||
1264 | |||
1265 | if (forward->extension.bNrInPins != 1) { | ||
1266 | uvc_trace(UVC_TRACE_DESCR, "Extension unit %d has" | ||
1267 | "more than 1 input pin.\n", entity->id); | ||
1268 | return -1; | ||
1269 | } | ||
1270 | |||
1271 | list_add_tail(&forward->chain, &video->extensions); | ||
1272 | if (uvc_trace_param & UVC_TRACE_PROBE) { | ||
1273 | if (!found) | ||
1274 | printk(" (-> XU"); | ||
1275 | |||
1276 | printk(" %d", forward->id); | ||
1277 | found = 1; | ||
1278 | } | ||
1279 | } | ||
1280 | if (found) | ||
1281 | printk(")"); | ||
1282 | |||
1283 | return 0; | ||
1284 | } | ||
1285 | |||
1286 | static int uvc_scan_chain_backward(struct uvc_video_device *video, | ||
1287 | struct uvc_entity *entity) | ||
1288 | { | ||
1289 | struct uvc_entity *term; | ||
1290 | int id = -1, i; | ||
1291 | |||
1292 | switch (UVC_ENTITY_TYPE(entity)) { | ||
1293 | case VC_EXTENSION_UNIT: | ||
1294 | id = entity->extension.baSourceID[0]; | ||
1295 | break; | ||
1296 | |||
1297 | case VC_PROCESSING_UNIT: | ||
1298 | id = entity->processing.bSourceID; | ||
1299 | break; | ||
1300 | |||
1301 | case VC_SELECTOR_UNIT: | ||
1302 | /* Single-input selector units are ignored. */ | ||
1303 | if (entity->selector.bNrInPins == 1) { | ||
1304 | id = entity->selector.baSourceID[0]; | ||
1305 | break; | ||
1306 | } | ||
1307 | |||
1308 | if (uvc_trace_param & UVC_TRACE_PROBE) | ||
1309 | printk(" <- IT"); | ||
1310 | |||
1311 | video->selector = entity; | ||
1312 | for (i = 0; i < entity->selector.bNrInPins; ++i) { | ||
1313 | id = entity->selector.baSourceID[i]; | ||
1314 | term = uvc_entity_by_id(video->dev, id); | ||
1315 | if (term == NULL || !UVC_ENTITY_IS_ITERM(term)) { | ||
1316 | uvc_trace(UVC_TRACE_DESCR, "Selector unit %d " | ||
1317 | "input %d isn't connected to an " | ||
1318 | "input terminal\n", entity->id, i); | ||
1319 | return -1; | ||
1320 | } | ||
1321 | |||
1322 | if (uvc_trace_param & UVC_TRACE_PROBE) | ||
1323 | printk(" %d", term->id); | ||
1324 | |||
1325 | list_add_tail(&term->chain, &video->iterms); | ||
1326 | uvc_scan_chain_forward(video, term, entity); | ||
1327 | } | ||
1328 | |||
1329 | if (uvc_trace_param & UVC_TRACE_PROBE) | ||
1330 | printk("\n"); | ||
1331 | |||
1332 | id = 0; | ||
1333 | break; | ||
1334 | } | ||
1335 | |||
1336 | return id; | ||
1337 | } | ||
1338 | |||
1339 | static int uvc_scan_chain(struct uvc_video_device *video) | ||
1340 | { | ||
1341 | struct uvc_entity *entity, *prev; | ||
1342 | int id; | ||
1343 | |||
1344 | entity = video->oterm; | ||
1345 | uvc_trace(UVC_TRACE_PROBE, "Scanning UVC chain: OT %d", entity->id); | ||
1346 | id = entity->output.bSourceID; | ||
1347 | while (id != 0) { | ||
1348 | prev = entity; | ||
1349 | entity = uvc_entity_by_id(video->dev, id); | ||
1350 | if (entity == NULL) { | ||
1351 | uvc_trace(UVC_TRACE_DESCR, "Found reference to " | ||
1352 | "unknown entity %d.\n", id); | ||
1353 | return -1; | ||
1354 | } | ||
1355 | |||
1356 | /* Process entity */ | ||
1357 | if (uvc_scan_chain_entity(video, entity) < 0) | ||
1358 | return -1; | ||
1359 | |||
1360 | /* Forward scan */ | ||
1361 | if (uvc_scan_chain_forward(video, entity, prev) < 0) | ||
1362 | return -1; | ||
1363 | |||
1364 | /* Stop when a terminal is found. */ | ||
1365 | if (!UVC_ENTITY_IS_UNIT(entity)) | ||
1366 | break; | ||
1367 | |||
1368 | /* Backward scan */ | ||
1369 | id = uvc_scan_chain_backward(video, entity); | ||
1370 | if (id < 0) | ||
1371 | return id; | ||
1372 | } | ||
1373 | |||
1374 | /* Initialize the video buffers queue. */ | ||
1375 | uvc_queue_init(&video->queue); | ||
1376 | |||
1377 | return 0; | ||
1378 | } | ||
1379 | |||
1380 | /* | ||
1381 | * Register the video devices. | ||
1382 | * | ||
1383 | * The driver currently supports a single video device per control interface | ||
1384 | * only. The terminal and units must match the following structure: | ||
1385 | * | ||
1386 | * ITT_CAMERA -> VC_PROCESSING_UNIT -> VC_EXTENSION_UNIT{0,n} -> TT_STREAMING | ||
1387 | * | ||
1388 | * The Extension Units, if present, must have a single input pin. The | ||
1389 | * Processing Unit and Extension Units can be in any order. Additional | ||
1390 | * Extension Units connected to the main chain as single-unit branches are | ||
1391 | * also supported. | ||
1392 | */ | ||
1393 | static int uvc_register_video(struct uvc_device *dev) | ||
1394 | { | ||
1395 | struct video_device *vdev; | ||
1396 | struct uvc_entity *term; | ||
1397 | int found = 0, ret; | ||
1398 | |||
1399 | /* Check if the control interface matches the structure we expect. */ | ||
1400 | list_for_each_entry(term, &dev->entities, list) { | ||
1401 | struct uvc_streaming *streaming; | ||
1402 | |||
1403 | if (UVC_ENTITY_TYPE(term) != TT_STREAMING) | ||
1404 | continue; | ||
1405 | |||
1406 | memset(&dev->video, 0, sizeof dev->video); | ||
1407 | mutex_init(&dev->video.ctrl_mutex); | ||
1408 | INIT_LIST_HEAD(&dev->video.iterms); | ||
1409 | INIT_LIST_HEAD(&dev->video.extensions); | ||
1410 | dev->video.oterm = term; | ||
1411 | dev->video.dev = dev; | ||
1412 | if (uvc_scan_chain(&dev->video) < 0) | ||
1413 | continue; | ||
1414 | |||
1415 | list_for_each_entry(streaming, &dev->streaming, list) { | ||
1416 | if (streaming->header.bTerminalLink == term->id) { | ||
1417 | dev->video.streaming = streaming; | ||
1418 | found = 1; | ||
1419 | break; | ||
1420 | } | ||
1421 | } | ||
1422 | |||
1423 | if (found) | ||
1424 | break; | ||
1425 | } | ||
1426 | |||
1427 | if (!found) { | ||
1428 | uvc_printk(KERN_INFO, "No valid video chain found.\n"); | ||
1429 | return -1; | ||
1430 | } | ||
1431 | |||
1432 | if (uvc_trace_param & UVC_TRACE_PROBE) { | ||
1433 | uvc_printk(KERN_INFO, "Found a valid video chain ("); | ||
1434 | list_for_each_entry(term, &dev->video.iterms, chain) { | ||
1435 | printk("%d", term->id); | ||
1436 | if (term->chain.next != &dev->video.iterms) | ||
1437 | printk(","); | ||
1438 | } | ||
1439 | printk(" -> %d).\n", dev->video.oterm->id); | ||
1440 | } | ||
1441 | |||
1442 | /* Initialize the streaming interface with default streaming | ||
1443 | * parameters. | ||
1444 | */ | ||
1445 | if ((ret = uvc_video_init(&dev->video)) < 0) { | ||
1446 | uvc_printk(KERN_ERR, "Failed to initialize the device " | ||
1447 | "(%d).\n", ret); | ||
1448 | return ret; | ||
1449 | } | ||
1450 | |||
1451 | /* Register the device with V4L. */ | ||
1452 | vdev = video_device_alloc(); | ||
1453 | if (vdev == NULL) | ||
1454 | return -1; | ||
1455 | |||
1456 | /* We already hold a reference to dev->udev. The video device will be | ||
1457 | * unregistered before the reference is released, so we don't need to | ||
1458 | * get another one. | ||
1459 | */ | ||
1460 | vdev->dev = &dev->intf->dev; | ||
1461 | vdev->type = 0; | ||
1462 | vdev->type2 = 0; | ||
1463 | vdev->minor = -1; | ||
1464 | vdev->fops = &uvc_fops; | ||
1465 | vdev->release = video_device_release; | ||
1466 | strncpy(vdev->name, dev->name, sizeof vdev->name); | ||
1467 | |||
1468 | /* Set the driver data before calling video_register_device, otherwise | ||
1469 | * uvc_v4l2_open might race us. | ||
1470 | * | ||
1471 | * FIXME: usb_set_intfdata hasn't been called so far. Is that a | ||
1472 | * problem ? Does any function which could be called here get | ||
1473 | * a pointer to the usb_interface ? | ||
1474 | */ | ||
1475 | dev->video.vdev = vdev; | ||
1476 | video_set_drvdata(vdev, &dev->video); | ||
1477 | |||
1478 | if (video_register_device(vdev, VFL_TYPE_GRABBER, -1) < 0) { | ||
1479 | dev->video.vdev = NULL; | ||
1480 | video_device_release(vdev); | ||
1481 | return -1; | ||
1482 | } | ||
1483 | |||
1484 | return 0; | ||
1485 | } | ||
1486 | |||
1487 | /* | ||
1488 | * Delete the UVC device. | ||
1489 | * | ||
1490 | * Called by the kernel when the last reference to the uvc_device structure | ||
1491 | * is released. | ||
1492 | * | ||
1493 | * Unregistering the video devices is done here because every opened instance | ||
1494 | * must be closed before the device can be unregistered. An alternative would | ||
1495 | * have been to use another reference count for uvc_v4l2_open/uvc_release, and | ||
1496 | * unregister the video devices on disconnect when that reference count drops | ||
1497 | * to zero. | ||
1498 | * | ||
1499 | * As this function is called after or during disconnect(), all URBs have | ||
1500 | * already been canceled by the USB core. There is no need to kill the | ||
1501 | * interrupt URB manually. | ||
1502 | */ | ||
1503 | void uvc_delete(struct kref *kref) | ||
1504 | { | ||
1505 | struct uvc_device *dev = container_of(kref, struct uvc_device, kref); | ||
1506 | struct list_head *p, *n; | ||
1507 | |||
1508 | /* Unregister the video device */ | ||
1509 | uvc_unregister_video(dev); | ||
1510 | usb_put_intf(dev->intf); | ||
1511 | usb_put_dev(dev->udev); | ||
1512 | |||
1513 | uvc_status_cleanup(dev); | ||
1514 | uvc_ctrl_cleanup_device(dev); | ||
1515 | |||
1516 | list_for_each_safe(p, n, &dev->entities) { | ||
1517 | struct uvc_entity *entity; | ||
1518 | entity = list_entry(p, struct uvc_entity, list); | ||
1519 | kfree(entity); | ||
1520 | } | ||
1521 | |||
1522 | list_for_each_safe(p, n, &dev->streaming) { | ||
1523 | struct uvc_streaming *streaming; | ||
1524 | streaming = list_entry(p, struct uvc_streaming, list); | ||
1525 | usb_driver_release_interface(&uvc_driver.driver, | ||
1526 | streaming->intf); | ||
1527 | usb_put_intf(streaming->intf); | ||
1528 | kfree(streaming->format); | ||
1529 | kfree(streaming->header.bmaControls); | ||
1530 | kfree(streaming); | ||
1531 | } | ||
1532 | |||
1533 | kfree(dev); | ||
1534 | } | ||
1535 | |||
1536 | static int uvc_probe(struct usb_interface *intf, | ||
1537 | const struct usb_device_id *id) | ||
1538 | { | ||
1539 | struct usb_device *udev = interface_to_usbdev(intf); | ||
1540 | struct uvc_device *dev; | ||
1541 | int ret; | ||
1542 | |||
1543 | if (id->idVendor && id->idProduct) | ||
1544 | uvc_trace(UVC_TRACE_PROBE, "Probing known UVC device %s " | ||
1545 | "(%04x:%04x)\n", udev->devpath, id->idVendor, | ||
1546 | id->idProduct); | ||
1547 | else | ||
1548 | uvc_trace(UVC_TRACE_PROBE, "Probing generic UVC device %s\n", | ||
1549 | udev->devpath); | ||
1550 | |||
1551 | /* Allocate memory for the device and initialize it */ | ||
1552 | if ((dev = kzalloc(sizeof *dev, GFP_KERNEL)) == NULL) | ||
1553 | return -ENOMEM; | ||
1554 | |||
1555 | INIT_LIST_HEAD(&dev->entities); | ||
1556 | INIT_LIST_HEAD(&dev->streaming); | ||
1557 | kref_init(&dev->kref); | ||
1558 | |||
1559 | dev->udev = usb_get_dev(udev); | ||
1560 | dev->intf = usb_get_intf(intf); | ||
1561 | dev->intfnum = intf->cur_altsetting->desc.bInterfaceNumber; | ||
1562 | dev->quirks = id->driver_info | uvc_quirks_param; | ||
1563 | |||
1564 | if (udev->product != NULL) | ||
1565 | strncpy(dev->name, udev->product, sizeof dev->name); | ||
1566 | else | ||
1567 | snprintf(dev->name, sizeof dev->name, | ||
1568 | "UVC Camera (%04x:%04x)", | ||
1569 | le16_to_cpu(udev->descriptor.idVendor), | ||
1570 | le16_to_cpu(udev->descriptor.idProduct)); | ||
1571 | |||
1572 | /* Parse the Video Class control descriptor */ | ||
1573 | if (uvc_parse_control(dev) < 0) { | ||
1574 | uvc_trace(UVC_TRACE_PROBE, "Unable to parse UVC " | ||
1575 | "descriptors.\n"); | ||
1576 | goto error; | ||
1577 | } | ||
1578 | |||
1579 | uvc_printk(KERN_INFO, "Found UVC %u.%02u device %s (%04x:%04x)\n", | ||
1580 | dev->uvc_version >> 8, dev->uvc_version & 0xff, | ||
1581 | udev->product ? udev->product : "<unnamed>", | ||
1582 | le16_to_cpu(udev->descriptor.idVendor), | ||
1583 | le16_to_cpu(udev->descriptor.idProduct)); | ||
1584 | |||
1585 | if (uvc_quirks_param != 0) { | ||
1586 | uvc_printk(KERN_INFO, "Forcing device quirks 0x%x by module " | ||
1587 | "parameter for testing purpose.\n", uvc_quirks_param); | ||
1588 | uvc_printk(KERN_INFO, "Please report required quirks to the " | ||
1589 | "linux-uvc-devel mailing list.\n"); | ||
1590 | } | ||
1591 | |||
1592 | /* Initialize controls */ | ||
1593 | if (uvc_ctrl_init_device(dev) < 0) | ||
1594 | goto error; | ||
1595 | |||
1596 | /* Register the video devices */ | ||
1597 | if (uvc_register_video(dev) < 0) | ||
1598 | goto error; | ||
1599 | |||
1600 | /* Save our data pointer in the interface data */ | ||
1601 | usb_set_intfdata(intf, dev); | ||
1602 | |||
1603 | /* Initialize the interrupt URB */ | ||
1604 | if ((ret = uvc_status_init(dev)) < 0) { | ||
1605 | uvc_printk(KERN_INFO, "Unable to initialize the status " | ||
1606 | "endpoint (%d), status interrupt will not be " | ||
1607 | "supported.\n", ret); | ||
1608 | } | ||
1609 | |||
1610 | uvc_trace(UVC_TRACE_PROBE, "UVC device initialized.\n"); | ||
1611 | return 0; | ||
1612 | |||
1613 | error: | ||
1614 | kref_put(&dev->kref, uvc_delete); | ||
1615 | return -ENODEV; | ||
1616 | } | ||
1617 | |||
1618 | static void uvc_disconnect(struct usb_interface *intf) | ||
1619 | { | ||
1620 | struct uvc_device *dev = usb_get_intfdata(intf); | ||
1621 | |||
1622 | /* Set the USB interface data to NULL. This can be done outside the | ||
1623 | * lock, as there's no other reader. | ||
1624 | */ | ||
1625 | usb_set_intfdata(intf, NULL); | ||
1626 | |||
1627 | if (intf->cur_altsetting->desc.bInterfaceSubClass == SC_VIDEOSTREAMING) | ||
1628 | return; | ||
1629 | |||
1630 | /* uvc_v4l2_open() might race uvc_disconnect(). A static driver-wide | ||
1631 | * lock is needed to prevent uvc_disconnect from releasing its | ||
1632 | * reference to the uvc_device instance after uvc_v4l2_open() received | ||
1633 | * the pointer to the device (video_devdata) but before it got the | ||
1634 | * chance to increase the reference count (kref_get). | ||
1635 | */ | ||
1636 | mutex_lock(&uvc_driver.open_mutex); | ||
1637 | |||
1638 | dev->state |= UVC_DEV_DISCONNECTED; | ||
1639 | kref_put(&dev->kref, uvc_delete); | ||
1640 | |||
1641 | mutex_unlock(&uvc_driver.open_mutex); | ||
1642 | } | ||
1643 | |||
1644 | static int uvc_suspend(struct usb_interface *intf, pm_message_t message) | ||
1645 | { | ||
1646 | struct uvc_device *dev = usb_get_intfdata(intf); | ||
1647 | |||
1648 | uvc_trace(UVC_TRACE_SUSPEND, "Suspending interface %u\n", | ||
1649 | intf->cur_altsetting->desc.bInterfaceNumber); | ||
1650 | |||
1651 | /* Controls are cached on the fly so they don't need to be saved. */ | ||
1652 | if (intf->cur_altsetting->desc.bInterfaceSubClass == SC_VIDEOCONTROL) | ||
1653 | return uvc_status_suspend(dev); | ||
1654 | |||
1655 | if (dev->video.streaming->intf != intf) { | ||
1656 | uvc_trace(UVC_TRACE_SUSPEND, "Suspend: video streaming USB " | ||
1657 | "interface mismatch.\n"); | ||
1658 | return -EINVAL; | ||
1659 | } | ||
1660 | |||
1661 | return uvc_video_suspend(&dev->video); | ||
1662 | } | ||
1663 | |||
1664 | static int uvc_resume(struct usb_interface *intf) | ||
1665 | { | ||
1666 | struct uvc_device *dev = usb_get_intfdata(intf); | ||
1667 | int ret; | ||
1668 | |||
1669 | uvc_trace(UVC_TRACE_SUSPEND, "Resuming interface %u\n", | ||
1670 | intf->cur_altsetting->desc.bInterfaceNumber); | ||
1671 | |||
1672 | if (intf->cur_altsetting->desc.bInterfaceSubClass == SC_VIDEOCONTROL) { | ||
1673 | if ((ret = uvc_ctrl_resume_device(dev)) < 0) | ||
1674 | return ret; | ||
1675 | |||
1676 | return uvc_status_resume(dev); | ||
1677 | } | ||
1678 | |||
1679 | if (dev->video.streaming->intf != intf) { | ||
1680 | uvc_trace(UVC_TRACE_SUSPEND, "Resume: video streaming USB " | ||
1681 | "interface mismatch.\n"); | ||
1682 | return -EINVAL; | ||
1683 | } | ||
1684 | |||
1685 | return uvc_video_resume(&dev->video); | ||
1686 | } | ||
1687 | |||
1688 | /* ------------------------------------------------------------------------ | ||
1689 | * Driver initialization and cleanup | ||
1690 | */ | ||
1691 | |||
1692 | /* | ||
1693 | * The Logitech cameras listed below have their interface class set to | ||
1694 | * VENDOR_SPEC because they don't announce themselves as UVC devices, even | ||
1695 | * though they are compliant. | ||
1696 | */ | ||
1697 | static struct usb_device_id uvc_ids[] = { | ||
1698 | /* ALi M5606 (Clevo M540SR) */ | ||
1699 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1700 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1701 | .idVendor = 0x0402, | ||
1702 | .idProduct = 0x5606, | ||
1703 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1704 | .bInterfaceSubClass = 1, | ||
1705 | .bInterfaceProtocol = 0, | ||
1706 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
1707 | /* Creative Live! Optia */ | ||
1708 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1709 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1710 | .idVendor = 0x041e, | ||
1711 | .idProduct = 0x4057, | ||
1712 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1713 | .bInterfaceSubClass = 1, | ||
1714 | .bInterfaceProtocol = 0, | ||
1715 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
1716 | /* Microsoft Lifecam NX-6000 */ | ||
1717 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1718 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1719 | .idVendor = 0x045e, | ||
1720 | .idProduct = 0x00f8, | ||
1721 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1722 | .bInterfaceSubClass = 1, | ||
1723 | .bInterfaceProtocol = 0, | ||
1724 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
1725 | /* Microsoft Lifecam VX-7000 */ | ||
1726 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1727 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1728 | .idVendor = 0x045e, | ||
1729 | .idProduct = 0x0723, | ||
1730 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1731 | .bInterfaceSubClass = 1, | ||
1732 | .bInterfaceProtocol = 0, | ||
1733 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
1734 | /* Logitech Quickcam Fusion */ | ||
1735 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1736 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1737 | .idVendor = 0x046d, | ||
1738 | .idProduct = 0x08c1, | ||
1739 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC, | ||
1740 | .bInterfaceSubClass = 1, | ||
1741 | .bInterfaceProtocol = 0 }, | ||
1742 | /* Logitech Quickcam Orbit MP */ | ||
1743 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1744 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1745 | .idVendor = 0x046d, | ||
1746 | .idProduct = 0x08c2, | ||
1747 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC, | ||
1748 | .bInterfaceSubClass = 1, | ||
1749 | .bInterfaceProtocol = 0 }, | ||
1750 | /* Logitech Quickcam Pro for Notebook */ | ||
1751 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1752 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1753 | .idVendor = 0x046d, | ||
1754 | .idProduct = 0x08c3, | ||
1755 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC, | ||
1756 | .bInterfaceSubClass = 1, | ||
1757 | .bInterfaceProtocol = 0 }, | ||
1758 | /* Logitech Quickcam Pro 5000 */ | ||
1759 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1760 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1761 | .idVendor = 0x046d, | ||
1762 | .idProduct = 0x08c5, | ||
1763 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC, | ||
1764 | .bInterfaceSubClass = 1, | ||
1765 | .bInterfaceProtocol = 0 }, | ||
1766 | /* Logitech Quickcam OEM Dell Notebook */ | ||
1767 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1768 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1769 | .idVendor = 0x046d, | ||
1770 | .idProduct = 0x08c6, | ||
1771 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC, | ||
1772 | .bInterfaceSubClass = 1, | ||
1773 | .bInterfaceProtocol = 0 }, | ||
1774 | /* Logitech Quickcam OEM Cisco VT Camera II */ | ||
1775 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1776 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1777 | .idVendor = 0x046d, | ||
1778 | .idProduct = 0x08c7, | ||
1779 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC, | ||
1780 | .bInterfaceSubClass = 1, | ||
1781 | .bInterfaceProtocol = 0 }, | ||
1782 | /* Apple Built-In iSight */ | ||
1783 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1784 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1785 | .idVendor = 0x05ac, | ||
1786 | .idProduct = 0x8501, | ||
1787 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1788 | .bInterfaceSubClass = 1, | ||
1789 | .bInterfaceProtocol = 0, | ||
1790 | .driver_info = UVC_QUIRK_PROBE_MINMAX | ||
1791 | | UVC_QUIRK_BUILTIN_ISIGHT }, | ||
1792 | /* Genesys Logic USB 2.0 PC Camera */ | ||
1793 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1794 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1795 | .idVendor = 0x05e3, | ||
1796 | .idProduct = 0x0505, | ||
1797 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1798 | .bInterfaceSubClass = 1, | ||
1799 | .bInterfaceProtocol = 0, | ||
1800 | .driver_info = UVC_QUIRK_STREAM_NO_FID }, | ||
1801 | /* Silicon Motion SM371 */ | ||
1802 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1803 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1804 | .idVendor = 0x090c, | ||
1805 | .idProduct = 0xb371, | ||
1806 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1807 | .bInterfaceSubClass = 1, | ||
1808 | .bInterfaceProtocol = 0, | ||
1809 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
1810 | /* MT6227 */ | ||
1811 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1812 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1813 | .idVendor = 0x0e8d, | ||
1814 | .idProduct = 0x0004, | ||
1815 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1816 | .bInterfaceSubClass = 1, | ||
1817 | .bInterfaceProtocol = 0, | ||
1818 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
1819 | /* Syntek (HP Spartan) */ | ||
1820 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1821 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1822 | .idVendor = 0x174f, | ||
1823 | .idProduct = 0x5212, | ||
1824 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1825 | .bInterfaceSubClass = 1, | ||
1826 | .bInterfaceProtocol = 0, | ||
1827 | .driver_info = UVC_QUIRK_STREAM_NO_FID }, | ||
1828 | /* Syntek (Asus U3S) */ | ||
1829 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1830 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1831 | .idVendor = 0x174f, | ||
1832 | .idProduct = 0x8a33, | ||
1833 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1834 | .bInterfaceSubClass = 1, | ||
1835 | .bInterfaceProtocol = 0, | ||
1836 | .driver_info = UVC_QUIRK_STREAM_NO_FID }, | ||
1837 | /* Ecamm Pico iMage */ | ||
1838 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1839 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1840 | .idVendor = 0x18cd, | ||
1841 | .idProduct = 0xcafe, | ||
1842 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1843 | .bInterfaceSubClass = 1, | ||
1844 | .bInterfaceProtocol = 0, | ||
1845 | .driver_info = UVC_QUIRK_PROBE_EXTRAFIELDS }, | ||
1846 | /* Bodelin ProScopeHR */ | ||
1847 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1848 | | USB_DEVICE_ID_MATCH_DEV_HI | ||
1849 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1850 | .idVendor = 0x19ab, | ||
1851 | .idProduct = 0x1000, | ||
1852 | .bcdDevice_hi = 0x0126, | ||
1853 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1854 | .bInterfaceSubClass = 1, | ||
1855 | .bInterfaceProtocol = 0, | ||
1856 | .driver_info = UVC_QUIRK_STATUS_INTERVAL }, | ||
1857 | /* SiGma Micro USB Web Camera */ | ||
1858 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1859 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1860 | .idVendor = 0x1c4f, | ||
1861 | .idProduct = 0x3000, | ||
1862 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1863 | .bInterfaceSubClass = 1, | ||
1864 | .bInterfaceProtocol = 0, | ||
1865 | .driver_info = UVC_QUIRK_PROBE_MINMAX | ||
1866 | | UVC_QUIRK_IGNORE_SELECTOR_UNIT}, | ||
1867 | /* Acer OEM Webcam - Unknown vendor */ | ||
1868 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1869 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1870 | .idVendor = 0x5986, | ||
1871 | .idProduct = 0x0100, | ||
1872 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1873 | .bInterfaceSubClass = 1, | ||
1874 | .bInterfaceProtocol = 0, | ||
1875 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
1876 | /* Packard Bell OEM Webcam */ | ||
1877 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1878 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1879 | .idVendor = 0x5986, | ||
1880 | .idProduct = 0x0101, | ||
1881 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1882 | .bInterfaceSubClass = 1, | ||
1883 | .bInterfaceProtocol = 0, | ||
1884 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
1885 | /* Acer Crystal Eye webcam */ | ||
1886 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1887 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1888 | .idVendor = 0x5986, | ||
1889 | .idProduct = 0x0102, | ||
1890 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1891 | .bInterfaceSubClass = 1, | ||
1892 | .bInterfaceProtocol = 0, | ||
1893 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
1894 | /* Acer OrbiCam - Unknown vendor */ | ||
1895 | { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | ||
1896 | | USB_DEVICE_ID_MATCH_INT_INFO, | ||
1897 | .idVendor = 0x5986, | ||
1898 | .idProduct = 0x0200, | ||
1899 | .bInterfaceClass = USB_CLASS_VIDEO, | ||
1900 | .bInterfaceSubClass = 1, | ||
1901 | .bInterfaceProtocol = 0, | ||
1902 | .driver_info = UVC_QUIRK_PROBE_MINMAX }, | ||
1903 | /* Generic USB Video Class */ | ||
1904 | { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, 0) }, | ||
1905 | {} | ||
1906 | }; | ||
1907 | |||
1908 | MODULE_DEVICE_TABLE(usb, uvc_ids); | ||
1909 | |||
1910 | struct uvc_driver uvc_driver = { | ||
1911 | .driver = { | ||
1912 | .name = "uvcvideo", | ||
1913 | .probe = uvc_probe, | ||
1914 | .disconnect = uvc_disconnect, | ||
1915 | .suspend = uvc_suspend, | ||
1916 | .resume = uvc_resume, | ||
1917 | .id_table = uvc_ids, | ||
1918 | .supports_autosuspend = 1, | ||
1919 | }, | ||
1920 | }; | ||
1921 | |||
1922 | static int __init uvc_init(void) | ||
1923 | { | ||
1924 | int result; | ||
1925 | |||
1926 | INIT_LIST_HEAD(&uvc_driver.devices); | ||
1927 | INIT_LIST_HEAD(&uvc_driver.controls); | ||
1928 | mutex_init(&uvc_driver.open_mutex); | ||
1929 | mutex_init(&uvc_driver.ctrl_mutex); | ||
1930 | |||
1931 | uvc_ctrl_init(); | ||
1932 | |||
1933 | result = usb_register(&uvc_driver.driver); | ||
1934 | if (result == 0) | ||
1935 | printk(KERN_INFO DRIVER_DESC " (" DRIVER_VERSION ")\n"); | ||
1936 | return result; | ||
1937 | } | ||
1938 | |||
1939 | static void __exit uvc_cleanup(void) | ||
1940 | { | ||
1941 | usb_deregister(&uvc_driver.driver); | ||
1942 | } | ||
1943 | |||
1944 | module_init(uvc_init); | ||
1945 | module_exit(uvc_cleanup); | ||
1946 | |||
1947 | module_param_named(quirks, uvc_quirks_param, uint, S_IRUGO|S_IWUSR); | ||
1948 | MODULE_PARM_DESC(quirks, "Forced device quirks"); | ||
1949 | module_param_named(trace, uvc_trace_param, uint, S_IRUGO|S_IWUSR); | ||
1950 | MODULE_PARM_DESC(trace, "Trace level bitmask"); | ||
1951 | |||
1952 | MODULE_AUTHOR(DRIVER_AUTHOR); | ||
1953 | MODULE_DESCRIPTION(DRIVER_DESC); | ||
1954 | MODULE_LICENSE("GPL"); | ||
1955 | MODULE_VERSION(DRIVER_VERSION); | ||
diff --git a/drivers/media/video/uvc/uvc_isight.c b/drivers/media/video/uvc/uvc_isight.c new file mode 100644 index 000000000000..37bdefdbead5 --- /dev/null +++ b/drivers/media/video/uvc/uvc_isight.c | |||
@@ -0,0 +1,134 @@ | |||
1 | /* | ||
2 | * uvc_isight.c -- USB Video Class driver - iSight support | ||
3 | * | ||
4 | * Copyright (C) 2006-2007 | ||
5 | * Ivan N. Zlatev <contact@i-nz.net> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/usb.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/mm.h> | ||
17 | |||
18 | #include "uvcvideo.h" | ||
19 | |||
20 | /* Built-in iSight webcams implements most of UVC 1.0 except a | ||
21 | * different packet format. Instead of sending a header at the | ||
22 | * beginning of each isochronous transfer payload, the webcam sends a | ||
23 | * single header per image (on its own in a packet), followed by | ||
24 | * packets containing data only. | ||
25 | * | ||
26 | * Offset Size (bytes) Description | ||
27 | * ------------------------------------------------------------------ | ||
28 | * 0x00 1 Header length | ||
29 | * 0x01 1 Flags (UVC-compliant) | ||
30 | * 0x02 4 Always equal to '11223344' | ||
31 | * 0x06 8 Always equal to 'deadbeefdeadface' | ||
32 | * 0x0e 16 Unknown | ||
33 | * | ||
34 | * The header can be prefixed by an optional, unknown-purpose byte. | ||
35 | */ | ||
36 | |||
37 | static int isight_decode(struct uvc_video_queue *queue, struct uvc_buffer *buf, | ||
38 | const __u8 *data, unsigned int len) | ||
39 | { | ||
40 | static const __u8 hdr[] = { | ||
41 | 0x11, 0x22, 0x33, 0x44, | ||
42 | 0xde, 0xad, 0xbe, 0xef, | ||
43 | 0xde, 0xad, 0xfa, 0xce | ||
44 | }; | ||
45 | |||
46 | unsigned int maxlen, nbytes; | ||
47 | __u8 *mem; | ||
48 | int is_header = 0; | ||
49 | |||
50 | if (buf == NULL) | ||
51 | return 0; | ||
52 | |||
53 | if ((len >= 14 && memcmp(&data[2], hdr, 12) == 0) || | ||
54 | (len >= 15 && memcmp(&data[3], hdr, 12) == 0)) { | ||
55 | uvc_trace(UVC_TRACE_FRAME, "iSight header found\n"); | ||
56 | is_header = 1; | ||
57 | } | ||
58 | |||
59 | /* Synchronize to the input stream by waiting for a header packet. */ | ||
60 | if (buf->state != UVC_BUF_STATE_ACTIVE) { | ||
61 | if (!is_header) { | ||
62 | uvc_trace(UVC_TRACE_FRAME, "Dropping packet (out of " | ||
63 | "sync).\n"); | ||
64 | return 0; | ||
65 | } | ||
66 | |||
67 | buf->state = UVC_BUF_STATE_ACTIVE; | ||
68 | } | ||
69 | |||
70 | /* Mark the buffer as done if we're at the beginning of a new frame. | ||
71 | * | ||
72 | * Empty buffers (bytesused == 0) don't trigger end of frame detection | ||
73 | * as it doesn't make sense to return an empty buffer. | ||
74 | */ | ||
75 | if (is_header && buf->buf.bytesused != 0) { | ||
76 | buf->state = UVC_BUF_STATE_DONE; | ||
77 | return -EAGAIN; | ||
78 | } | ||
79 | |||
80 | /* Copy the video data to the buffer. Skip header packets, as they | ||
81 | * contain no data. | ||
82 | */ | ||
83 | if (!is_header) { | ||
84 | maxlen = buf->buf.length - buf->buf.bytesused; | ||
85 | mem = queue->mem + buf->buf.m.offset + buf->buf.bytesused; | ||
86 | nbytes = min(len, maxlen); | ||
87 | memcpy(mem, data, nbytes); | ||
88 | buf->buf.bytesused += nbytes; | ||
89 | |||
90 | if (len > maxlen || buf->buf.bytesused == buf->buf.length) { | ||
91 | uvc_trace(UVC_TRACE_FRAME, "Frame complete " | ||
92 | "(overflow).\n"); | ||
93 | buf->state = UVC_BUF_STATE_DONE; | ||
94 | } | ||
95 | } | ||
96 | |||
97 | return 0; | ||
98 | } | ||
99 | |||
100 | void uvc_video_decode_isight(struct urb *urb, struct uvc_video_device *video, | ||
101 | struct uvc_buffer *buf) | ||
102 | { | ||
103 | int ret, i; | ||
104 | |||
105 | for (i = 0; i < urb->number_of_packets; ++i) { | ||
106 | if (urb->iso_frame_desc[i].status < 0) { | ||
107 | uvc_trace(UVC_TRACE_FRAME, "USB isochronous frame " | ||
108 | "lost (%d).\n", | ||
109 | urb->iso_frame_desc[i].status); | ||
110 | } | ||
111 | |||
112 | /* Decode the payload packet. | ||
113 | * uvc_video_decode is entered twice when a frame transition | ||
114 | * has been detected because the end of frame can only be | ||
115 | * reliably detected when the first packet of the new frame | ||
116 | * is processed. The first pass detects the transition and | ||
117 | * closes the previous frame's buffer, the second pass | ||
118 | * processes the data of the first payload of the new frame. | ||
119 | */ | ||
120 | do { | ||
121 | ret = isight_decode(&video->queue, buf, | ||
122 | urb->transfer_buffer + | ||
123 | urb->iso_frame_desc[i].offset, | ||
124 | urb->iso_frame_desc[i].actual_length); | ||
125 | |||
126 | if (buf == NULL) | ||
127 | break; | ||
128 | |||
129 | if (buf->state == UVC_BUF_STATE_DONE || | ||
130 | buf->state == UVC_BUF_STATE_ERROR) | ||
131 | buf = uvc_queue_next_buffer(&video->queue, buf); | ||
132 | } while (ret == -EAGAIN); | ||
133 | } | ||
134 | } | ||
diff --git a/drivers/media/video/uvc/uvc_queue.c b/drivers/media/video/uvc/uvc_queue.c new file mode 100644 index 000000000000..0923f0e3b3d4 --- /dev/null +++ b/drivers/media/video/uvc/uvc_queue.c | |||
@@ -0,0 +1,477 @@ | |||
1 | /* | ||
2 | * uvc_queue.c -- USB Video Class driver - Buffers management | ||
3 | * | ||
4 | * Copyright (C) 2005-2008 | ||
5 | * Laurent Pinchart (laurent.pinchart@skynet.be) | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/version.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/usb.h> | ||
19 | #include <linux/videodev2.h> | ||
20 | #include <linux/vmalloc.h> | ||
21 | #include <linux/wait.h> | ||
22 | #include <asm/atomic.h> | ||
23 | |||
24 | #include "uvcvideo.h" | ||
25 | |||
26 | /* ------------------------------------------------------------------------ | ||
27 | * Video buffers queue management. | ||
28 | * | ||
29 | * Video queues is initialized by uvc_queue_init(). The function performs | ||
30 | * basic initialization of the uvc_video_queue struct and never fails. | ||
31 | * | ||
32 | * Video buffer allocation and freeing are performed by uvc_alloc_buffers and | ||
33 | * uvc_free_buffers respectively. The former acquires the video queue lock, | ||
34 | * while the later must be called with the lock held (so that allocation can | ||
35 | * free previously allocated buffers). Trying to free buffers that are mapped | ||
36 | * to user space will return -EBUSY. | ||
37 | * | ||
38 | * Video buffers are managed using two queues. However, unlike most USB video | ||
39 | * drivers which use an in queue and an out queue, we use a main queue which | ||
40 | * holds all queued buffers (both 'empty' and 'done' buffers), and an irq | ||
41 | * queue which holds empty buffers. This design (copied from video-buf) | ||
42 | * minimizes locking in interrupt, as only one queue is shared between | ||
43 | * interrupt and user contexts. | ||
44 | * | ||
45 | * Use cases | ||
46 | * --------- | ||
47 | * | ||
48 | * Unless stated otherwise, all operations which modify the irq buffers queue | ||
49 | * are protected by the irq spinlock. | ||
50 | * | ||
51 | * 1. The user queues the buffers, starts streaming and dequeues a buffer. | ||
52 | * | ||
53 | * The buffers are added to the main and irq queues. Both operations are | ||
54 | * protected by the queue lock, and the latert is protected by the irq | ||
55 | * spinlock as well. | ||
56 | * | ||
57 | * The completion handler fetches a buffer from the irq queue and fills it | ||
58 | * with video data. If no buffer is available (irq queue empty), the handler | ||
59 | * returns immediately. | ||
60 | * | ||
61 | * When the buffer is full, the completion handler removes it from the irq | ||
62 | * queue, marks it as ready (UVC_BUF_STATE_DONE) and wake its wait queue. | ||
63 | * At that point, any process waiting on the buffer will be woken up. If a | ||
64 | * process tries to dequeue a buffer after it has been marked ready, the | ||
65 | * dequeing will succeed immediately. | ||
66 | * | ||
67 | * 2. Buffers are queued, user is waiting on a buffer and the device gets | ||
68 | * disconnected. | ||
69 | * | ||
70 | * When the device is disconnected, the kernel calls the completion handler | ||
71 | * with an appropriate status code. The handler marks all buffers in the | ||
72 | * irq queue as being erroneous (UVC_BUF_STATE_ERROR) and wakes them up so | ||
73 | * that any process waiting on a buffer gets woken up. | ||
74 | * | ||
75 | * Waking up up the first buffer on the irq list is not enough, as the | ||
76 | * process waiting on the buffer might restart the dequeue operation | ||
77 | * immediately. | ||
78 | * | ||
79 | */ | ||
80 | |||
81 | void uvc_queue_init(struct uvc_video_queue *queue) | ||
82 | { | ||
83 | mutex_init(&queue->mutex); | ||
84 | spin_lock_init(&queue->irqlock); | ||
85 | INIT_LIST_HEAD(&queue->mainqueue); | ||
86 | INIT_LIST_HEAD(&queue->irqqueue); | ||
87 | } | ||
88 | |||
89 | /* | ||
90 | * Allocate the video buffers. | ||
91 | * | ||
92 | * Pages are reserved to make sure they will not be swaped, as they will be | ||
93 | * filled in URB completion handler. | ||
94 | * | ||
95 | * Buffers will be individually mapped, so they must all be page aligned. | ||
96 | */ | ||
97 | int uvc_alloc_buffers(struct uvc_video_queue *queue, unsigned int nbuffers, | ||
98 | unsigned int buflength) | ||
99 | { | ||
100 | unsigned int bufsize = PAGE_ALIGN(buflength); | ||
101 | unsigned int i; | ||
102 | void *mem = NULL; | ||
103 | int ret; | ||
104 | |||
105 | if (nbuffers > UVC_MAX_VIDEO_BUFFERS) | ||
106 | nbuffers = UVC_MAX_VIDEO_BUFFERS; | ||
107 | |||
108 | mutex_lock(&queue->mutex); | ||
109 | |||
110 | if ((ret = uvc_free_buffers(queue)) < 0) | ||
111 | goto done; | ||
112 | |||
113 | /* Bail out if no buffers should be allocated. */ | ||
114 | if (nbuffers == 0) | ||
115 | goto done; | ||
116 | |||
117 | /* Decrement the number of buffers until allocation succeeds. */ | ||
118 | for (; nbuffers > 0; --nbuffers) { | ||
119 | mem = vmalloc_32(nbuffers * bufsize); | ||
120 | if (mem != NULL) | ||
121 | break; | ||
122 | } | ||
123 | |||
124 | if (mem == NULL) { | ||
125 | ret = -ENOMEM; | ||
126 | goto done; | ||
127 | } | ||
128 | |||
129 | for (i = 0; i < nbuffers; ++i) { | ||
130 | memset(&queue->buffer[i], 0, sizeof queue->buffer[i]); | ||
131 | queue->buffer[i].buf.index = i; | ||
132 | queue->buffer[i].buf.m.offset = i * bufsize; | ||
133 | queue->buffer[i].buf.length = buflength; | ||
134 | queue->buffer[i].buf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | ||
135 | queue->buffer[i].buf.sequence = 0; | ||
136 | queue->buffer[i].buf.field = V4L2_FIELD_NONE; | ||
137 | queue->buffer[i].buf.memory = V4L2_MEMORY_MMAP; | ||
138 | queue->buffer[i].buf.flags = 0; | ||
139 | init_waitqueue_head(&queue->buffer[i].wait); | ||
140 | } | ||
141 | |||
142 | queue->mem = mem; | ||
143 | queue->count = nbuffers; | ||
144 | queue->buf_size = bufsize; | ||
145 | ret = nbuffers; | ||
146 | |||
147 | done: | ||
148 | mutex_unlock(&queue->mutex); | ||
149 | return ret; | ||
150 | } | ||
151 | |||
152 | /* | ||
153 | * Free the video buffers. | ||
154 | * | ||
155 | * This function must be called with the queue lock held. | ||
156 | */ | ||
157 | int uvc_free_buffers(struct uvc_video_queue *queue) | ||
158 | { | ||
159 | unsigned int i; | ||
160 | |||
161 | for (i = 0; i < queue->count; ++i) { | ||
162 | if (queue->buffer[i].vma_use_count != 0) | ||
163 | return -EBUSY; | ||
164 | } | ||
165 | |||
166 | if (queue->count) { | ||
167 | vfree(queue->mem); | ||
168 | queue->count = 0; | ||
169 | } | ||
170 | |||
171 | return 0; | ||
172 | } | ||
173 | |||
174 | static void __uvc_query_buffer(struct uvc_buffer *buf, | ||
175 | struct v4l2_buffer *v4l2_buf) | ||
176 | { | ||
177 | memcpy(v4l2_buf, &buf->buf, sizeof *v4l2_buf); | ||
178 | |||
179 | if (buf->vma_use_count) | ||
180 | v4l2_buf->flags |= V4L2_BUF_FLAG_MAPPED; | ||
181 | |||
182 | switch (buf->state) { | ||
183 | case UVC_BUF_STATE_ERROR: | ||
184 | case UVC_BUF_STATE_DONE: | ||
185 | v4l2_buf->flags |= V4L2_BUF_FLAG_DONE; | ||
186 | break; | ||
187 | case UVC_BUF_STATE_QUEUED: | ||
188 | case UVC_BUF_STATE_ACTIVE: | ||
189 | v4l2_buf->flags |= V4L2_BUF_FLAG_QUEUED; | ||
190 | break; | ||
191 | case UVC_BUF_STATE_IDLE: | ||
192 | default: | ||
193 | break; | ||
194 | } | ||
195 | } | ||
196 | |||
197 | int uvc_query_buffer(struct uvc_video_queue *queue, | ||
198 | struct v4l2_buffer *v4l2_buf) | ||
199 | { | ||
200 | int ret = 0; | ||
201 | |||
202 | mutex_lock(&queue->mutex); | ||
203 | if (v4l2_buf->index >= queue->count) { | ||
204 | ret = -EINVAL; | ||
205 | goto done; | ||
206 | } | ||
207 | |||
208 | __uvc_query_buffer(&queue->buffer[v4l2_buf->index], v4l2_buf); | ||
209 | |||
210 | done: | ||
211 | mutex_unlock(&queue->mutex); | ||
212 | return ret; | ||
213 | } | ||
214 | |||
215 | /* | ||
216 | * Queue a video buffer. Attempting to queue a buffer that has already been | ||
217 | * queued will return -EINVAL. | ||
218 | */ | ||
219 | int uvc_queue_buffer(struct uvc_video_queue *queue, | ||
220 | struct v4l2_buffer *v4l2_buf) | ||
221 | { | ||
222 | struct uvc_buffer *buf; | ||
223 | unsigned long flags; | ||
224 | int ret = 0; | ||
225 | |||
226 | uvc_trace(UVC_TRACE_CAPTURE, "Queuing buffer %u.\n", v4l2_buf->index); | ||
227 | |||
228 | if (v4l2_buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE || | ||
229 | v4l2_buf->memory != V4L2_MEMORY_MMAP) { | ||
230 | uvc_trace(UVC_TRACE_CAPTURE, "[E] Invalid buffer type (%u) " | ||
231 | "and/or memory (%u).\n", v4l2_buf->type, | ||
232 | v4l2_buf->memory); | ||
233 | return -EINVAL; | ||
234 | } | ||
235 | |||
236 | mutex_lock(&queue->mutex); | ||
237 | if (v4l2_buf->index >= queue->count) { | ||
238 | uvc_trace(UVC_TRACE_CAPTURE, "[E] Out of range index.\n"); | ||
239 | ret = -EINVAL; | ||
240 | goto done; | ||
241 | } | ||
242 | |||
243 | buf = &queue->buffer[v4l2_buf->index]; | ||
244 | if (buf->state != UVC_BUF_STATE_IDLE) { | ||
245 | uvc_trace(UVC_TRACE_CAPTURE, "[E] Invalid buffer state " | ||
246 | "(%u).\n", buf->state); | ||
247 | ret = -EINVAL; | ||
248 | goto done; | ||
249 | } | ||
250 | |||
251 | spin_lock_irqsave(&queue->irqlock, flags); | ||
252 | if (queue->flags & UVC_QUEUE_DISCONNECTED) { | ||
253 | spin_unlock_irqrestore(&queue->irqlock, flags); | ||
254 | ret = -ENODEV; | ||
255 | goto done; | ||
256 | } | ||
257 | buf->state = UVC_BUF_STATE_QUEUED; | ||
258 | buf->buf.bytesused = 0; | ||
259 | list_add_tail(&buf->stream, &queue->mainqueue); | ||
260 | list_add_tail(&buf->queue, &queue->irqqueue); | ||
261 | spin_unlock_irqrestore(&queue->irqlock, flags); | ||
262 | |||
263 | done: | ||
264 | mutex_unlock(&queue->mutex); | ||
265 | return ret; | ||
266 | } | ||
267 | |||
268 | static int uvc_queue_waiton(struct uvc_buffer *buf, int nonblocking) | ||
269 | { | ||
270 | if (nonblocking) { | ||
271 | return (buf->state != UVC_BUF_STATE_QUEUED && | ||
272 | buf->state != UVC_BUF_STATE_ACTIVE) | ||
273 | ? 0 : -EAGAIN; | ||
274 | } | ||
275 | |||
276 | return wait_event_interruptible(buf->wait, | ||
277 | buf->state != UVC_BUF_STATE_QUEUED && | ||
278 | buf->state != UVC_BUF_STATE_ACTIVE); | ||
279 | } | ||
280 | |||
281 | /* | ||
282 | * Dequeue a video buffer. If nonblocking is false, block until a buffer is | ||
283 | * available. | ||
284 | */ | ||
285 | int uvc_dequeue_buffer(struct uvc_video_queue *queue, | ||
286 | struct v4l2_buffer *v4l2_buf, int nonblocking) | ||
287 | { | ||
288 | struct uvc_buffer *buf; | ||
289 | int ret = 0; | ||
290 | |||
291 | if (v4l2_buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE || | ||
292 | v4l2_buf->memory != V4L2_MEMORY_MMAP) { | ||
293 | uvc_trace(UVC_TRACE_CAPTURE, "[E] Invalid buffer type (%u) " | ||
294 | "and/or memory (%u).\n", v4l2_buf->type, | ||
295 | v4l2_buf->memory); | ||
296 | return -EINVAL; | ||
297 | } | ||
298 | |||
299 | mutex_lock(&queue->mutex); | ||
300 | if (list_empty(&queue->mainqueue)) { | ||
301 | uvc_trace(UVC_TRACE_CAPTURE, "[E] Empty buffer queue.\n"); | ||
302 | ret = -EINVAL; | ||
303 | goto done; | ||
304 | } | ||
305 | |||
306 | buf = list_first_entry(&queue->mainqueue, struct uvc_buffer, stream); | ||
307 | if ((ret = uvc_queue_waiton(buf, nonblocking)) < 0) | ||
308 | goto done; | ||
309 | |||
310 | uvc_trace(UVC_TRACE_CAPTURE, "Dequeuing buffer %u (%u, %u bytes).\n", | ||
311 | buf->buf.index, buf->state, buf->buf.bytesused); | ||
312 | |||
313 | switch (buf->state) { | ||
314 | case UVC_BUF_STATE_ERROR: | ||
315 | uvc_trace(UVC_TRACE_CAPTURE, "[W] Corrupted data " | ||
316 | "(transmission error).\n"); | ||
317 | ret = -EIO; | ||
318 | case UVC_BUF_STATE_DONE: | ||
319 | buf->state = UVC_BUF_STATE_IDLE; | ||
320 | break; | ||
321 | |||
322 | case UVC_BUF_STATE_IDLE: | ||
323 | case UVC_BUF_STATE_QUEUED: | ||
324 | case UVC_BUF_STATE_ACTIVE: | ||
325 | default: | ||
326 | uvc_trace(UVC_TRACE_CAPTURE, "[E] Invalid buffer state %u " | ||
327 | "(driver bug?).\n", buf->state); | ||
328 | ret = -EINVAL; | ||
329 | goto done; | ||
330 | } | ||
331 | |||
332 | list_del(&buf->stream); | ||
333 | __uvc_query_buffer(buf, v4l2_buf); | ||
334 | |||
335 | done: | ||
336 | mutex_unlock(&queue->mutex); | ||
337 | return ret; | ||
338 | } | ||
339 | |||
340 | /* | ||
341 | * Poll the video queue. | ||
342 | * | ||
343 | * This function implements video queue polling and is intended to be used by | ||
344 | * the device poll handler. | ||
345 | */ | ||
346 | unsigned int uvc_queue_poll(struct uvc_video_queue *queue, struct file *file, | ||
347 | poll_table *wait) | ||
348 | { | ||
349 | struct uvc_buffer *buf; | ||
350 | unsigned int mask = 0; | ||
351 | |||
352 | mutex_lock(&queue->mutex); | ||
353 | if (list_empty(&queue->mainqueue)) { | ||
354 | mask |= POLLERR; | ||
355 | goto done; | ||
356 | } | ||
357 | buf = list_first_entry(&queue->mainqueue, struct uvc_buffer, stream); | ||
358 | |||
359 | poll_wait(file, &buf->wait, wait); | ||
360 | if (buf->state == UVC_BUF_STATE_DONE || | ||
361 | buf->state == UVC_BUF_STATE_ERROR) | ||
362 | mask |= POLLIN | POLLRDNORM; | ||
363 | |||
364 | done: | ||
365 | mutex_unlock(&queue->mutex); | ||
366 | return mask; | ||
367 | } | ||
368 | |||
369 | /* | ||
370 | * Enable or disable the video buffers queue. | ||
371 | * | ||
372 | * The queue must be enabled before starting video acquisition and must be | ||
373 | * disabled after stopping it. This ensures that the video buffers queue | ||
374 | * state can be properly initialized before buffers are accessed from the | ||
375 | * interrupt handler. | ||
376 | * | ||
377 | * Enabling the video queue initializes parameters (such as sequence number, | ||
378 | * sync pattern, ...). If the queue is already enabled, return -EBUSY. | ||
379 | * | ||
380 | * Disabling the video queue cancels the queue and removes all buffers from | ||
381 | * the main queue. | ||
382 | * | ||
383 | * This function can't be called from interrupt context. Use | ||
384 | * uvc_queue_cancel() instead. | ||
385 | */ | ||
386 | int uvc_queue_enable(struct uvc_video_queue *queue, int enable) | ||
387 | { | ||
388 | unsigned int i; | ||
389 | int ret = 0; | ||
390 | |||
391 | mutex_lock(&queue->mutex); | ||
392 | if (enable) { | ||
393 | if (uvc_queue_streaming(queue)) { | ||
394 | ret = -EBUSY; | ||
395 | goto done; | ||
396 | } | ||
397 | queue->sequence = 0; | ||
398 | queue->flags |= UVC_QUEUE_STREAMING; | ||
399 | } else { | ||
400 | uvc_queue_cancel(queue, 0); | ||
401 | INIT_LIST_HEAD(&queue->mainqueue); | ||
402 | |||
403 | for (i = 0; i < queue->count; ++i) | ||
404 | queue->buffer[i].state = UVC_BUF_STATE_IDLE; | ||
405 | |||
406 | queue->flags &= ~UVC_QUEUE_STREAMING; | ||
407 | } | ||
408 | |||
409 | done: | ||
410 | mutex_unlock(&queue->mutex); | ||
411 | return ret; | ||
412 | } | ||
413 | |||
414 | /* | ||
415 | * Cancel the video buffers queue. | ||
416 | * | ||
417 | * Cancelling the queue marks all buffers on the irq queue as erroneous, | ||
418 | * wakes them up and remove them from the queue. | ||
419 | * | ||
420 | * If the disconnect parameter is set, further calls to uvc_queue_buffer will | ||
421 | * fail with -ENODEV. | ||
422 | * | ||
423 | * This function acquires the irq spinlock and can be called from interrupt | ||
424 | * context. | ||
425 | */ | ||
426 | void uvc_queue_cancel(struct uvc_video_queue *queue, int disconnect) | ||
427 | { | ||
428 | struct uvc_buffer *buf; | ||
429 | unsigned long flags; | ||
430 | |||
431 | spin_lock_irqsave(&queue->irqlock, flags); | ||
432 | while (!list_empty(&queue->irqqueue)) { | ||
433 | buf = list_first_entry(&queue->irqqueue, struct uvc_buffer, | ||
434 | queue); | ||
435 | list_del(&buf->queue); | ||
436 | buf->state = UVC_BUF_STATE_ERROR; | ||
437 | wake_up(&buf->wait); | ||
438 | } | ||
439 | /* This must be protected by the irqlock spinlock to avoid race | ||
440 | * conditions between uvc_queue_buffer and the disconnection event that | ||
441 | * could result in an interruptible wait in uvc_dequeue_buffer. Do not | ||
442 | * blindly replace this logic by checking for the UVC_DEV_DISCONNECTED | ||
443 | * state outside the queue code. | ||
444 | */ | ||
445 | if (disconnect) | ||
446 | queue->flags |= UVC_QUEUE_DISCONNECTED; | ||
447 | spin_unlock_irqrestore(&queue->irqlock, flags); | ||
448 | } | ||
449 | |||
450 | struct uvc_buffer *uvc_queue_next_buffer(struct uvc_video_queue *queue, | ||
451 | struct uvc_buffer *buf) | ||
452 | { | ||
453 | struct uvc_buffer *nextbuf; | ||
454 | unsigned long flags; | ||
455 | |||
456 | if ((queue->flags & UVC_QUEUE_DROP_INCOMPLETE) && | ||
457 | buf->buf.length != buf->buf.bytesused) { | ||
458 | buf->state = UVC_BUF_STATE_QUEUED; | ||
459 | buf->buf.bytesused = 0; | ||
460 | return buf; | ||
461 | } | ||
462 | |||
463 | spin_lock_irqsave(&queue->irqlock, flags); | ||
464 | list_del(&buf->queue); | ||
465 | if (!list_empty(&queue->irqqueue)) | ||
466 | nextbuf = list_first_entry(&queue->irqqueue, struct uvc_buffer, | ||
467 | queue); | ||
468 | else | ||
469 | nextbuf = NULL; | ||
470 | spin_unlock_irqrestore(&queue->irqlock, flags); | ||
471 | |||
472 | buf->buf.sequence = queue->sequence++; | ||
473 | do_gettimeofday(&buf->buf.timestamp); | ||
474 | |||
475 | wake_up(&buf->wait); | ||
476 | return nextbuf; | ||
477 | } | ||
diff --git a/drivers/media/video/uvc/uvc_status.c b/drivers/media/video/uvc/uvc_status.c new file mode 100644 index 000000000000..be9084e5eace --- /dev/null +++ b/drivers/media/video/uvc/uvc_status.c | |||
@@ -0,0 +1,207 @@ | |||
1 | /* | ||
2 | * uvc_status.c -- USB Video Class driver - Status endpoint | ||
3 | * | ||
4 | * Copyright (C) 2007-2008 | ||
5 | * Laurent Pinchart (laurent.pinchart@skynet.be) | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/version.h> | ||
16 | #include <linux/input.h> | ||
17 | #include <linux/usb.h> | ||
18 | #include <linux/usb/input.h> | ||
19 | |||
20 | #include "uvcvideo.h" | ||
21 | |||
22 | /* -------------------------------------------------------------------------- | ||
23 | * Input device | ||
24 | */ | ||
25 | static int uvc_input_init(struct uvc_device *dev) | ||
26 | { | ||
27 | struct usb_device *udev = dev->udev; | ||
28 | struct input_dev *input; | ||
29 | char *phys = NULL; | ||
30 | int ret; | ||
31 | |||
32 | input = input_allocate_device(); | ||
33 | if (input == NULL) | ||
34 | return -ENOMEM; | ||
35 | |||
36 | phys = kmalloc(6 + strlen(udev->bus->bus_name) + strlen(udev->devpath), | ||
37 | GFP_KERNEL); | ||
38 | if (phys == NULL) { | ||
39 | ret = -ENOMEM; | ||
40 | goto error; | ||
41 | } | ||
42 | sprintf(phys, "usb-%s-%s", udev->bus->bus_name, udev->devpath); | ||
43 | |||
44 | input->name = dev->name; | ||
45 | input->phys = phys; | ||
46 | usb_to_input_id(udev, &input->id); | ||
47 | input->dev.parent = &dev->intf->dev; | ||
48 | |||
49 | set_bit(EV_KEY, input->evbit); | ||
50 | set_bit(BTN_0, input->keybit); | ||
51 | |||
52 | if ((ret = input_register_device(input)) < 0) | ||
53 | goto error; | ||
54 | |||
55 | dev->input = input; | ||
56 | return 0; | ||
57 | |||
58 | error: | ||
59 | input_free_device(input); | ||
60 | kfree(phys); | ||
61 | return ret; | ||
62 | } | ||
63 | |||
64 | static void uvc_input_cleanup(struct uvc_device *dev) | ||
65 | { | ||
66 | if (dev->input) | ||
67 | input_unregister_device(dev->input); | ||
68 | } | ||
69 | |||
70 | /* -------------------------------------------------------------------------- | ||
71 | * Status interrupt endpoint | ||
72 | */ | ||
73 | static void uvc_event_streaming(struct uvc_device *dev, __u8 *data, int len) | ||
74 | { | ||
75 | if (len < 3) { | ||
76 | uvc_trace(UVC_TRACE_STATUS, "Invalid streaming status event " | ||
77 | "received.\n"); | ||
78 | return; | ||
79 | } | ||
80 | |||
81 | if (data[2] == 0) { | ||
82 | if (len < 4) | ||
83 | return; | ||
84 | uvc_trace(UVC_TRACE_STATUS, "Button (intf %u) %s len %d\n", | ||
85 | data[1], data[3] ? "pressed" : "released", len); | ||
86 | if (dev->input) | ||
87 | input_report_key(dev->input, BTN_0, data[3]); | ||
88 | } else { | ||
89 | uvc_trace(UVC_TRACE_STATUS, "Stream %u error event %02x %02x " | ||
90 | "len %d.\n", data[1], data[2], data[3], len); | ||
91 | } | ||
92 | } | ||
93 | |||
94 | static void uvc_event_control(struct uvc_device *dev, __u8 *data, int len) | ||
95 | { | ||
96 | char *attrs[3] = { "value", "info", "failure" }; | ||
97 | |||
98 | if (len < 6 || data[2] != 0 || data[4] > 2) { | ||
99 | uvc_trace(UVC_TRACE_STATUS, "Invalid control status event " | ||
100 | "received.\n"); | ||
101 | return; | ||
102 | } | ||
103 | |||
104 | uvc_trace(UVC_TRACE_STATUS, "Control %u/%u %s change len %d.\n", | ||
105 | data[1], data[3], attrs[data[4]], len); | ||
106 | } | ||
107 | |||
108 | static void uvc_status_complete(struct urb *urb) | ||
109 | { | ||
110 | struct uvc_device *dev = urb->context; | ||
111 | int len, ret; | ||
112 | |||
113 | switch (urb->status) { | ||
114 | case 0: | ||
115 | break; | ||
116 | |||
117 | case -ENOENT: /* usb_kill_urb() called. */ | ||
118 | case -ECONNRESET: /* usb_unlink_urb() called. */ | ||
119 | case -ESHUTDOWN: /* The endpoint is being disabled. */ | ||
120 | case -EPROTO: /* Device is disconnected (reported by some | ||
121 | * host controller). */ | ||
122 | return; | ||
123 | |||
124 | default: | ||
125 | uvc_printk(KERN_WARNING, "Non-zero status (%d) in status " | ||
126 | "completion handler.\n", urb->status); | ||
127 | return; | ||
128 | } | ||
129 | |||
130 | len = urb->actual_length; | ||
131 | if (len > 0) { | ||
132 | switch (dev->status[0] & 0x0f) { | ||
133 | case UVC_STATUS_TYPE_CONTROL: | ||
134 | uvc_event_control(dev, dev->status, len); | ||
135 | break; | ||
136 | |||
137 | case UVC_STATUS_TYPE_STREAMING: | ||
138 | uvc_event_streaming(dev, dev->status, len); | ||
139 | break; | ||
140 | |||
141 | default: | ||
142 | uvc_printk(KERN_INFO, "unknown event type %u.\n", | ||
143 | dev->status[0]); | ||
144 | break; | ||
145 | } | ||
146 | } | ||
147 | |||
148 | /* Resubmit the URB. */ | ||
149 | urb->interval = dev->int_ep->desc.bInterval; | ||
150 | if ((ret = usb_submit_urb(urb, GFP_ATOMIC)) < 0) { | ||
151 | uvc_printk(KERN_ERR, "Failed to resubmit status URB (%d).\n", | ||
152 | ret); | ||
153 | } | ||
154 | } | ||
155 | |||
156 | int uvc_status_init(struct uvc_device *dev) | ||
157 | { | ||
158 | struct usb_host_endpoint *ep = dev->int_ep; | ||
159 | unsigned int pipe; | ||
160 | int interval; | ||
161 | |||
162 | if (ep == NULL) | ||
163 | return 0; | ||
164 | |||
165 | uvc_input_init(dev); | ||
166 | |||
167 | dev->int_urb = usb_alloc_urb(0, GFP_KERNEL); | ||
168 | if (dev->int_urb == NULL) | ||
169 | return -ENOMEM; | ||
170 | |||
171 | pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress); | ||
172 | |||
173 | /* For high-speed interrupt endpoints, the bInterval value is used as | ||
174 | * an exponent of two. Some developers forgot about it. | ||
175 | */ | ||
176 | interval = ep->desc.bInterval; | ||
177 | if (interval > 16 && dev->udev->speed == USB_SPEED_HIGH && | ||
178 | (dev->quirks & UVC_QUIRK_STATUS_INTERVAL)) | ||
179 | interval = fls(interval) - 1; | ||
180 | |||
181 | usb_fill_int_urb(dev->int_urb, dev->udev, pipe, | ||
182 | dev->status, sizeof dev->status, uvc_status_complete, | ||
183 | dev, interval); | ||
184 | |||
185 | return usb_submit_urb(dev->int_urb, GFP_KERNEL); | ||
186 | } | ||
187 | |||
188 | void uvc_status_cleanup(struct uvc_device *dev) | ||
189 | { | ||
190 | usb_kill_urb(dev->int_urb); | ||
191 | usb_free_urb(dev->int_urb); | ||
192 | uvc_input_cleanup(dev); | ||
193 | } | ||
194 | |||
195 | int uvc_status_suspend(struct uvc_device *dev) | ||
196 | { | ||
197 | usb_kill_urb(dev->int_urb); | ||
198 | return 0; | ||
199 | } | ||
200 | |||
201 | int uvc_status_resume(struct uvc_device *dev) | ||
202 | { | ||
203 | if (dev->int_urb == NULL) | ||
204 | return 0; | ||
205 | |||
206 | return usb_submit_urb(dev->int_urb, GFP_KERNEL); | ||
207 | } | ||
diff --git a/drivers/media/video/uvc/uvc_v4l2.c b/drivers/media/video/uvc/uvc_v4l2.c new file mode 100644 index 000000000000..2e0a66575bb4 --- /dev/null +++ b/drivers/media/video/uvc/uvc_v4l2.c | |||
@@ -0,0 +1,1105 @@ | |||
1 | /* | ||
2 | * uvc_v4l2.c -- USB Video Class driver - V4L2 API | ||
3 | * | ||
4 | * Copyright (C) 2005-2008 | ||
5 | * Laurent Pinchart (laurent.pinchart@skynet.be) | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/version.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/usb.h> | ||
19 | #include <linux/videodev2.h> | ||
20 | #include <linux/vmalloc.h> | ||
21 | #include <linux/mm.h> | ||
22 | #include <linux/wait.h> | ||
23 | #include <asm/atomic.h> | ||
24 | |||
25 | #include <media/v4l2-common.h> | ||
26 | |||
27 | #include "uvcvideo.h" | ||
28 | |||
29 | /* ------------------------------------------------------------------------ | ||
30 | * V4L2 interface | ||
31 | */ | ||
32 | |||
33 | /* | ||
34 | * Mapping V4L2 controls to UVC controls can be straighforward if done well. | ||
35 | * Most of the UVC controls exist in V4L2, and can be mapped directly. Some | ||
36 | * must be grouped (for instance the Red Balance, Blue Balance and Do White | ||
37 | * Balance V4L2 controls use the White Balance Component UVC control) or | ||
38 | * otherwise translated. The approach we take here is to use a translation | ||
39 | * table for the controls which can be mapped directly, and handle the others | ||
40 | * manually. | ||
41 | */ | ||
42 | static int uvc_v4l2_query_menu(struct uvc_video_device *video, | ||
43 | struct v4l2_querymenu *query_menu) | ||
44 | { | ||
45 | struct uvc_menu_info *menu_info; | ||
46 | struct uvc_control_mapping *mapping; | ||
47 | struct uvc_control *ctrl; | ||
48 | |||
49 | ctrl = uvc_find_control(video, query_menu->id, &mapping); | ||
50 | if (ctrl == NULL || mapping->v4l2_type != V4L2_CTRL_TYPE_MENU) | ||
51 | return -EINVAL; | ||
52 | |||
53 | if (query_menu->index >= mapping->menu_count) | ||
54 | return -EINVAL; | ||
55 | |||
56 | menu_info = &mapping->menu_info[query_menu->index]; | ||
57 | strncpy(query_menu->name, menu_info->name, 32); | ||
58 | return 0; | ||
59 | } | ||
60 | |||
61 | /* | ||
62 | * Find the frame interval closest to the requested frame interval for the | ||
63 | * given frame format and size. This should be done by the device as part of | ||
64 | * the Video Probe and Commit negotiation, but some hardware don't implement | ||
65 | * that feature. | ||
66 | */ | ||
67 | static __u32 uvc_try_frame_interval(struct uvc_frame *frame, __u32 interval) | ||
68 | { | ||
69 | unsigned int i; | ||
70 | |||
71 | if (frame->bFrameIntervalType) { | ||
72 | __u32 best = -1, dist; | ||
73 | |||
74 | for (i = 0; i < frame->bFrameIntervalType; ++i) { | ||
75 | dist = interval > frame->dwFrameInterval[i] | ||
76 | ? interval - frame->dwFrameInterval[i] | ||
77 | : frame->dwFrameInterval[i] - interval; | ||
78 | |||
79 | if (dist > best) | ||
80 | break; | ||
81 | |||
82 | best = dist; | ||
83 | } | ||
84 | |||
85 | interval = frame->dwFrameInterval[i-1]; | ||
86 | } else { | ||
87 | const __u32 min = frame->dwFrameInterval[0]; | ||
88 | const __u32 max = frame->dwFrameInterval[1]; | ||
89 | const __u32 step = frame->dwFrameInterval[2]; | ||
90 | |||
91 | interval = min + (interval - min + step/2) / step * step; | ||
92 | if (interval > max) | ||
93 | interval = max; | ||
94 | } | ||
95 | |||
96 | return interval; | ||
97 | } | ||
98 | |||
99 | static int uvc_v4l2_try_format(struct uvc_video_device *video, | ||
100 | struct v4l2_format *fmt, struct uvc_streaming_control *probe, | ||
101 | struct uvc_format **uvc_format, struct uvc_frame **uvc_frame) | ||
102 | { | ||
103 | struct uvc_format *format = NULL; | ||
104 | struct uvc_frame *frame = NULL; | ||
105 | __u16 rw, rh; | ||
106 | unsigned int d, maxd; | ||
107 | unsigned int i; | ||
108 | __u32 interval; | ||
109 | int ret = 0; | ||
110 | __u8 *fcc; | ||
111 | |||
112 | if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | ||
113 | return -EINVAL; | ||
114 | |||
115 | fcc = (__u8 *)&fmt->fmt.pix.pixelformat; | ||
116 | uvc_trace(UVC_TRACE_FORMAT, "Trying format 0x%08x (%c%c%c%c): %ux%u.\n", | ||
117 | fmt->fmt.pix.pixelformat, | ||
118 | fcc[0], fcc[1], fcc[2], fcc[3], | ||
119 | fmt->fmt.pix.width, fmt->fmt.pix.height); | ||
120 | |||
121 | /* Check if the hardware supports the requested format. */ | ||
122 | for (i = 0; i < video->streaming->nformats; ++i) { | ||
123 | format = &video->streaming->format[i]; | ||
124 | if (format->fcc == fmt->fmt.pix.pixelformat) | ||
125 | break; | ||
126 | } | ||
127 | |||
128 | if (format == NULL || format->fcc != fmt->fmt.pix.pixelformat) { | ||
129 | uvc_trace(UVC_TRACE_FORMAT, "Unsupported format 0x%08x.\n", | ||
130 | fmt->fmt.pix.pixelformat); | ||
131 | return -EINVAL; | ||
132 | } | ||
133 | |||
134 | /* Find the closest image size. The distance between image sizes is | ||
135 | * the size in pixels of the non-overlapping regions between the | ||
136 | * requested size and the frame-specified size. | ||
137 | */ | ||
138 | rw = fmt->fmt.pix.width; | ||
139 | rh = fmt->fmt.pix.height; | ||
140 | maxd = (unsigned int)-1; | ||
141 | |||
142 | for (i = 0; i < format->nframes; ++i) { | ||
143 | __u16 w = format->frame[i].wWidth; | ||
144 | __u16 h = format->frame[i].wHeight; | ||
145 | |||
146 | d = min(w, rw) * min(h, rh); | ||
147 | d = w*h + rw*rh - 2*d; | ||
148 | if (d < maxd) { | ||
149 | maxd = d; | ||
150 | frame = &format->frame[i]; | ||
151 | } | ||
152 | |||
153 | if (maxd == 0) | ||
154 | break; | ||
155 | } | ||
156 | |||
157 | if (frame == NULL) { | ||
158 | uvc_trace(UVC_TRACE_FORMAT, "Unsupported size %ux%u.\n", | ||
159 | fmt->fmt.pix.width, fmt->fmt.pix.height); | ||
160 | return -EINVAL; | ||
161 | } | ||
162 | |||
163 | /* Use the default frame interval. */ | ||
164 | interval = frame->dwDefaultFrameInterval; | ||
165 | uvc_trace(UVC_TRACE_FORMAT, "Using default frame interval %u.%u us " | ||
166 | "(%u.%u fps).\n", interval/10, interval%10, 10000000/interval, | ||
167 | (100000000/interval)%10); | ||
168 | |||
169 | /* Set the format index, frame index and frame interval. */ | ||
170 | memset(probe, 0, sizeof *probe); | ||
171 | probe->bmHint = 1; /* dwFrameInterval */ | ||
172 | probe->bFormatIndex = format->index; | ||
173 | probe->bFrameIndex = frame->bFrameIndex; | ||
174 | probe->dwFrameInterval = uvc_try_frame_interval(frame, interval); | ||
175 | /* Some webcams stall the probe control set request when the | ||
176 | * dwMaxVideoFrameSize field is set to zero. The UVC specification | ||
177 | * clearly states that the field is read-only from the host, so this | ||
178 | * is a webcam bug. Set dwMaxVideoFrameSize to the value reported by | ||
179 | * the webcam to work around the problem. | ||
180 | * | ||
181 | * The workaround could probably be enabled for all webcams, so the | ||
182 | * quirk can be removed if needed. It's currently useful to detect | ||
183 | * webcam bugs and fix them before they hit the market (providing | ||
184 | * developers test their webcams with the Linux driver as well as with | ||
185 | * the Windows driver). | ||
186 | */ | ||
187 | if (video->dev->quirks & UVC_QUIRK_PROBE_EXTRAFIELDS) | ||
188 | probe->dwMaxVideoFrameSize = | ||
189 | video->streaming->ctrl.dwMaxVideoFrameSize; | ||
190 | |||
191 | /* Probe the device */ | ||
192 | if ((ret = uvc_probe_video(video, probe)) < 0) | ||
193 | goto done; | ||
194 | |||
195 | fmt->fmt.pix.width = frame->wWidth; | ||
196 | fmt->fmt.pix.height = frame->wHeight; | ||
197 | fmt->fmt.pix.field = V4L2_FIELD_NONE; | ||
198 | fmt->fmt.pix.bytesperline = format->bpp * frame->wWidth / 8; | ||
199 | fmt->fmt.pix.sizeimage = probe->dwMaxVideoFrameSize; | ||
200 | fmt->fmt.pix.colorspace = format->colorspace; | ||
201 | fmt->fmt.pix.priv = 0; | ||
202 | |||
203 | if (uvc_format != NULL) | ||
204 | *uvc_format = format; | ||
205 | if (uvc_frame != NULL) | ||
206 | *uvc_frame = frame; | ||
207 | |||
208 | done: | ||
209 | return ret; | ||
210 | } | ||
211 | |||
212 | static int uvc_v4l2_get_format(struct uvc_video_device *video, | ||
213 | struct v4l2_format *fmt) | ||
214 | { | ||
215 | struct uvc_format *format = video->streaming->cur_format; | ||
216 | struct uvc_frame *frame = video->streaming->cur_frame; | ||
217 | |||
218 | if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | ||
219 | return -EINVAL; | ||
220 | |||
221 | if (format == NULL || frame == NULL) | ||
222 | return -EINVAL; | ||
223 | |||
224 | fmt->fmt.pix.pixelformat = format->fcc; | ||
225 | fmt->fmt.pix.width = frame->wWidth; | ||
226 | fmt->fmt.pix.height = frame->wHeight; | ||
227 | fmt->fmt.pix.field = V4L2_FIELD_NONE; | ||
228 | fmt->fmt.pix.bytesperline = format->bpp * frame->wWidth / 8; | ||
229 | fmt->fmt.pix.sizeimage = video->streaming->ctrl.dwMaxVideoFrameSize; | ||
230 | fmt->fmt.pix.colorspace = format->colorspace; | ||
231 | fmt->fmt.pix.priv = 0; | ||
232 | |||
233 | return 0; | ||
234 | } | ||
235 | |||
236 | static int uvc_v4l2_set_format(struct uvc_video_device *video, | ||
237 | struct v4l2_format *fmt) | ||
238 | { | ||
239 | struct uvc_streaming_control probe; | ||
240 | struct uvc_format *format; | ||
241 | struct uvc_frame *frame; | ||
242 | int ret; | ||
243 | |||
244 | if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | ||
245 | return -EINVAL; | ||
246 | |||
247 | if (uvc_queue_streaming(&video->queue)) | ||
248 | return -EBUSY; | ||
249 | |||
250 | ret = uvc_v4l2_try_format(video, fmt, &probe, &format, &frame); | ||
251 | if (ret < 0) | ||
252 | return ret; | ||
253 | |||
254 | if ((ret = uvc_set_video_ctrl(video, &probe, 0)) < 0) | ||
255 | return ret; | ||
256 | |||
257 | memcpy(&video->streaming->ctrl, &probe, sizeof probe); | ||
258 | video->streaming->cur_format = format; | ||
259 | video->streaming->cur_frame = frame; | ||
260 | |||
261 | return 0; | ||
262 | } | ||
263 | |||
264 | static int uvc_v4l2_get_streamparm(struct uvc_video_device *video, | ||
265 | struct v4l2_streamparm *parm) | ||
266 | { | ||
267 | uint32_t numerator, denominator; | ||
268 | |||
269 | if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | ||
270 | return -EINVAL; | ||
271 | |||
272 | numerator = video->streaming->ctrl.dwFrameInterval; | ||
273 | denominator = 10000000; | ||
274 | uvc_simplify_fraction(&numerator, &denominator, 8, 333); | ||
275 | |||
276 | memset(parm, 0, sizeof *parm); | ||
277 | parm->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | ||
278 | parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; | ||
279 | parm->parm.capture.capturemode = 0; | ||
280 | parm->parm.capture.timeperframe.numerator = numerator; | ||
281 | parm->parm.capture.timeperframe.denominator = denominator; | ||
282 | parm->parm.capture.extendedmode = 0; | ||
283 | parm->parm.capture.readbuffers = 0; | ||
284 | |||
285 | return 0; | ||
286 | } | ||
287 | |||
288 | static int uvc_v4l2_set_streamparm(struct uvc_video_device *video, | ||
289 | struct v4l2_streamparm *parm) | ||
290 | { | ||
291 | struct uvc_frame *frame = video->streaming->cur_frame; | ||
292 | struct uvc_streaming_control probe; | ||
293 | uint32_t interval; | ||
294 | int ret; | ||
295 | |||
296 | if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | ||
297 | return -EINVAL; | ||
298 | |||
299 | if (uvc_queue_streaming(&video->queue)) | ||
300 | return -EBUSY; | ||
301 | |||
302 | memcpy(&probe, &video->streaming->ctrl, sizeof probe); | ||
303 | interval = uvc_fraction_to_interval( | ||
304 | parm->parm.capture.timeperframe.numerator, | ||
305 | parm->parm.capture.timeperframe.denominator); | ||
306 | |||
307 | uvc_trace(UVC_TRACE_FORMAT, "Setting frame interval to %u/%u (%u).\n", | ||
308 | parm->parm.capture.timeperframe.numerator, | ||
309 | parm->parm.capture.timeperframe.denominator, | ||
310 | interval); | ||
311 | probe.dwFrameInterval = uvc_try_frame_interval(frame, interval); | ||
312 | |||
313 | /* Probe the device with the new settings. */ | ||
314 | if ((ret = uvc_probe_video(video, &probe)) < 0) | ||
315 | return ret; | ||
316 | |||
317 | /* Commit the new settings. */ | ||
318 | if ((ret = uvc_set_video_ctrl(video, &probe, 0)) < 0) | ||
319 | return ret; | ||
320 | |||
321 | memcpy(&video->streaming->ctrl, &probe, sizeof probe); | ||
322 | |||
323 | /* Return the actual frame period. */ | ||
324 | parm->parm.capture.timeperframe.numerator = probe.dwFrameInterval; | ||
325 | parm->parm.capture.timeperframe.denominator = 10000000; | ||
326 | uvc_simplify_fraction(&parm->parm.capture.timeperframe.numerator, | ||
327 | &parm->parm.capture.timeperframe.denominator, | ||
328 | 8, 333); | ||
329 | |||
330 | return 0; | ||
331 | } | ||
332 | |||
333 | /* ------------------------------------------------------------------------ | ||
334 | * Privilege management | ||
335 | */ | ||
336 | |||
337 | /* | ||
338 | * Privilege management is the multiple-open implementation basis. The current | ||
339 | * implementation is completely transparent for the end-user and doesn't | ||
340 | * require explicit use of the VIDIOC_G_PRIORITY and VIDIOC_S_PRIORITY ioctls. | ||
341 | * Those ioctls enable finer control on the device (by making possible for a | ||
342 | * user to request exclusive access to a device), but are not mature yet. | ||
343 | * Switching to the V4L2 priority mechanism might be considered in the future | ||
344 | * if this situation changes. | ||
345 | * | ||
346 | * Each open instance of a UVC device can either be in a privileged or | ||
347 | * unprivileged state. Only a single instance can be in a privileged state at | ||
348 | * a given time. Trying to perform an operation which requires privileges will | ||
349 | * automatically acquire the required privileges if possible, or return -EBUSY | ||
350 | * otherwise. Privileges are dismissed when closing the instance. | ||
351 | * | ||
352 | * Operations which require privileges are: | ||
353 | * | ||
354 | * - VIDIOC_S_INPUT | ||
355 | * - VIDIOC_S_PARM | ||
356 | * - VIDIOC_S_FMT | ||
357 | * - VIDIOC_TRY_FMT | ||
358 | * - VIDIOC_REQBUFS | ||
359 | */ | ||
360 | static int uvc_acquire_privileges(struct uvc_fh *handle) | ||
361 | { | ||
362 | int ret = 0; | ||
363 | |||
364 | /* Always succeed if the handle is already privileged. */ | ||
365 | if (handle->state == UVC_HANDLE_ACTIVE) | ||
366 | return 0; | ||
367 | |||
368 | /* Check if the device already has a privileged handle. */ | ||
369 | mutex_lock(&uvc_driver.open_mutex); | ||
370 | if (atomic_inc_return(&handle->device->active) != 1) { | ||
371 | atomic_dec(&handle->device->active); | ||
372 | ret = -EBUSY; | ||
373 | goto done; | ||
374 | } | ||
375 | |||
376 | handle->state = UVC_HANDLE_ACTIVE; | ||
377 | |||
378 | done: | ||
379 | mutex_unlock(&uvc_driver.open_mutex); | ||
380 | return ret; | ||
381 | } | ||
382 | |||
383 | static void uvc_dismiss_privileges(struct uvc_fh *handle) | ||
384 | { | ||
385 | if (handle->state == UVC_HANDLE_ACTIVE) | ||
386 | atomic_dec(&handle->device->active); | ||
387 | |||
388 | handle->state = UVC_HANDLE_PASSIVE; | ||
389 | } | ||
390 | |||
391 | static int uvc_has_privileges(struct uvc_fh *handle) | ||
392 | { | ||
393 | return handle->state == UVC_HANDLE_ACTIVE; | ||
394 | } | ||
395 | |||
396 | /* ------------------------------------------------------------------------ | ||
397 | * V4L2 file operations | ||
398 | */ | ||
399 | |||
400 | static int uvc_v4l2_open(struct inode *inode, struct file *file) | ||
401 | { | ||
402 | struct video_device *vdev; | ||
403 | struct uvc_video_device *video; | ||
404 | struct uvc_fh *handle; | ||
405 | int ret = 0; | ||
406 | |||
407 | uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_open\n"); | ||
408 | mutex_lock(&uvc_driver.open_mutex); | ||
409 | vdev = video_devdata(file); | ||
410 | video = video_get_drvdata(vdev); | ||
411 | |||
412 | if (video->dev->state & UVC_DEV_DISCONNECTED) { | ||
413 | ret = -ENODEV; | ||
414 | goto done; | ||
415 | } | ||
416 | |||
417 | ret = usb_autopm_get_interface(video->dev->intf); | ||
418 | if (ret < 0) | ||
419 | goto done; | ||
420 | |||
421 | /* Create the device handle. */ | ||
422 | handle = kzalloc(sizeof *handle, GFP_KERNEL); | ||
423 | if (handle == NULL) { | ||
424 | usb_autopm_put_interface(video->dev->intf); | ||
425 | ret = -ENOMEM; | ||
426 | goto done; | ||
427 | } | ||
428 | |||
429 | handle->device = video; | ||
430 | handle->state = UVC_HANDLE_PASSIVE; | ||
431 | file->private_data = handle; | ||
432 | |||
433 | kref_get(&video->dev->kref); | ||
434 | |||
435 | done: | ||
436 | mutex_unlock(&uvc_driver.open_mutex); | ||
437 | return ret; | ||
438 | } | ||
439 | |||
440 | static int uvc_v4l2_release(struct inode *inode, struct file *file) | ||
441 | { | ||
442 | struct video_device *vdev = video_devdata(file); | ||
443 | struct uvc_video_device *video = video_get_drvdata(vdev); | ||
444 | struct uvc_fh *handle = (struct uvc_fh *)file->private_data; | ||
445 | |||
446 | uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_release\n"); | ||
447 | |||
448 | /* Only free resources if this is a privileged handle. */ | ||
449 | if (uvc_has_privileges(handle)) { | ||
450 | uvc_video_enable(video, 0); | ||
451 | |||
452 | mutex_lock(&video->queue.mutex); | ||
453 | if (uvc_free_buffers(&video->queue) < 0) | ||
454 | uvc_printk(KERN_ERR, "uvc_v4l2_release: Unable to " | ||
455 | "free buffers.\n"); | ||
456 | mutex_unlock(&video->queue.mutex); | ||
457 | } | ||
458 | |||
459 | /* Release the file handle. */ | ||
460 | uvc_dismiss_privileges(handle); | ||
461 | kfree(handle); | ||
462 | file->private_data = NULL; | ||
463 | |||
464 | usb_autopm_put_interface(video->dev->intf); | ||
465 | kref_put(&video->dev->kref, uvc_delete); | ||
466 | return 0; | ||
467 | } | ||
468 | |||
469 | static int uvc_v4l2_do_ioctl(struct inode *inode, struct file *file, | ||
470 | unsigned int cmd, void *arg) | ||
471 | { | ||
472 | struct video_device *vdev = video_devdata(file); | ||
473 | struct uvc_video_device *video = video_get_drvdata(vdev); | ||
474 | struct uvc_fh *handle = (struct uvc_fh *)file->private_data; | ||
475 | int ret = 0; | ||
476 | |||
477 | if (uvc_trace_param & UVC_TRACE_IOCTL) | ||
478 | v4l_printk_ioctl(cmd); | ||
479 | |||
480 | switch (cmd) { | ||
481 | /* Query capabilities */ | ||
482 | case VIDIOC_QUERYCAP: | ||
483 | { | ||
484 | struct v4l2_capability *cap = arg; | ||
485 | |||
486 | memset(cap, 0, sizeof *cap); | ||
487 | strncpy(cap->driver, "uvcvideo", sizeof cap->driver); | ||
488 | strncpy(cap->card, vdev->name, 32); | ||
489 | strncpy(cap->bus_info, video->dev->udev->bus->bus_name, | ||
490 | sizeof cap->bus_info); | ||
491 | cap->version = DRIVER_VERSION_NUMBER; | ||
492 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | ||
493 | | V4L2_CAP_STREAMING; | ||
494 | break; | ||
495 | } | ||
496 | |||
497 | /* Get, Set & Query control */ | ||
498 | case VIDIOC_QUERYCTRL: | ||
499 | return uvc_query_v4l2_ctrl(video, arg); | ||
500 | |||
501 | case VIDIOC_G_CTRL: | ||
502 | { | ||
503 | struct v4l2_control *ctrl = arg; | ||
504 | struct v4l2_ext_control xctrl; | ||
505 | |||
506 | memset(&xctrl, 0, sizeof xctrl); | ||
507 | xctrl.id = ctrl->id; | ||
508 | |||
509 | uvc_ctrl_begin(video); | ||
510 | ret = uvc_ctrl_get(video, &xctrl); | ||
511 | uvc_ctrl_rollback(video); | ||
512 | if (ret >= 0) | ||
513 | ctrl->value = xctrl.value; | ||
514 | break; | ||
515 | } | ||
516 | |||
517 | case VIDIOC_S_CTRL: | ||
518 | { | ||
519 | struct v4l2_control *ctrl = arg; | ||
520 | struct v4l2_ext_control xctrl; | ||
521 | |||
522 | memset(&xctrl, 0, sizeof xctrl); | ||
523 | xctrl.id = ctrl->id; | ||
524 | xctrl.value = ctrl->value; | ||
525 | |||
526 | uvc_ctrl_begin(video); | ||
527 | ret = uvc_ctrl_set(video, &xctrl); | ||
528 | if (ret < 0) { | ||
529 | uvc_ctrl_rollback(video); | ||
530 | return ret; | ||
531 | } | ||
532 | ret = uvc_ctrl_commit(video); | ||
533 | break; | ||
534 | } | ||
535 | |||
536 | case VIDIOC_QUERYMENU: | ||
537 | return uvc_v4l2_query_menu(video, arg); | ||
538 | |||
539 | case VIDIOC_G_EXT_CTRLS: | ||
540 | { | ||
541 | struct v4l2_ext_controls *ctrls = arg; | ||
542 | struct v4l2_ext_control *ctrl = ctrls->controls; | ||
543 | unsigned int i; | ||
544 | |||
545 | uvc_ctrl_begin(video); | ||
546 | for (i = 0; i < ctrls->count; ++ctrl, ++i) { | ||
547 | ret = uvc_ctrl_get(video, ctrl); | ||
548 | if (ret < 0) { | ||
549 | uvc_ctrl_rollback(video); | ||
550 | ctrls->error_idx = i; | ||
551 | return ret; | ||
552 | } | ||
553 | } | ||
554 | ctrls->error_idx = 0; | ||
555 | ret = uvc_ctrl_rollback(video); | ||
556 | break; | ||
557 | } | ||
558 | |||
559 | case VIDIOC_S_EXT_CTRLS: | ||
560 | case VIDIOC_TRY_EXT_CTRLS: | ||
561 | { | ||
562 | struct v4l2_ext_controls *ctrls = arg; | ||
563 | struct v4l2_ext_control *ctrl = ctrls->controls; | ||
564 | unsigned int i; | ||
565 | |||
566 | ret = uvc_ctrl_begin(video); | ||
567 | if (ret < 0) | ||
568 | return ret; | ||
569 | |||
570 | for (i = 0; i < ctrls->count; ++ctrl, ++i) { | ||
571 | ret = uvc_ctrl_set(video, ctrl); | ||
572 | if (ret < 0) { | ||
573 | uvc_ctrl_rollback(video); | ||
574 | ctrls->error_idx = i; | ||
575 | return ret; | ||
576 | } | ||
577 | } | ||
578 | |||
579 | ctrls->error_idx = 0; | ||
580 | |||
581 | if (cmd == VIDIOC_S_EXT_CTRLS) | ||
582 | ret = uvc_ctrl_commit(video); | ||
583 | else | ||
584 | ret = uvc_ctrl_rollback(video); | ||
585 | break; | ||
586 | } | ||
587 | |||
588 | /* Get, Set & Enum input */ | ||
589 | case VIDIOC_ENUMINPUT: | ||
590 | { | ||
591 | const struct uvc_entity *selector = video->selector; | ||
592 | struct v4l2_input *input = arg; | ||
593 | struct uvc_entity *iterm = NULL; | ||
594 | u32 index = input->index; | ||
595 | int pin = 0; | ||
596 | |||
597 | if (selector == NULL || | ||
598 | (video->dev->quirks & UVC_QUIRK_IGNORE_SELECTOR_UNIT)) { | ||
599 | if (index != 0) | ||
600 | return -EINVAL; | ||
601 | iterm = list_first_entry(&video->iterms, | ||
602 | struct uvc_entity, chain); | ||
603 | pin = iterm->id; | ||
604 | } else if (pin < selector->selector.bNrInPins) { | ||
605 | pin = selector->selector.baSourceID[index]; | ||
606 | list_for_each_entry(iterm, video->iterms.next, chain) { | ||
607 | if (iterm->id == pin) | ||
608 | break; | ||
609 | } | ||
610 | } | ||
611 | |||
612 | if (iterm == NULL || iterm->id != pin) | ||
613 | return -EINVAL; | ||
614 | |||
615 | memset(input, 0, sizeof *input); | ||
616 | input->index = index; | ||
617 | strncpy(input->name, iterm->name, sizeof input->name); | ||
618 | if (UVC_ENTITY_TYPE(iterm) == ITT_CAMERA) | ||
619 | input->type = V4L2_INPUT_TYPE_CAMERA; | ||
620 | break; | ||
621 | } | ||
622 | |||
623 | case VIDIOC_G_INPUT: | ||
624 | { | ||
625 | u8 input; | ||
626 | |||
627 | if (video->selector == NULL || | ||
628 | (video->dev->quirks & UVC_QUIRK_IGNORE_SELECTOR_UNIT)) { | ||
629 | *(int *)arg = 0; | ||
630 | break; | ||
631 | } | ||
632 | |||
633 | ret = uvc_query_ctrl(video->dev, GET_CUR, video->selector->id, | ||
634 | video->dev->intfnum, SU_INPUT_SELECT_CONTROL, | ||
635 | &input, 1); | ||
636 | if (ret < 0) | ||
637 | return ret; | ||
638 | |||
639 | *(int *)arg = input - 1; | ||
640 | break; | ||
641 | } | ||
642 | |||
643 | case VIDIOC_S_INPUT: | ||
644 | { | ||
645 | u8 input = *(u32 *)arg + 1; | ||
646 | |||
647 | if ((ret = uvc_acquire_privileges(handle)) < 0) | ||
648 | return ret; | ||
649 | |||
650 | if (video->selector == NULL || | ||
651 | (video->dev->quirks & UVC_QUIRK_IGNORE_SELECTOR_UNIT)) { | ||
652 | if (input != 1) | ||
653 | return -EINVAL; | ||
654 | break; | ||
655 | } | ||
656 | |||
657 | if (input > video->selector->selector.bNrInPins) | ||
658 | return -EINVAL; | ||
659 | |||
660 | return uvc_query_ctrl(video->dev, SET_CUR, video->selector->id, | ||
661 | video->dev->intfnum, SU_INPUT_SELECT_CONTROL, | ||
662 | &input, 1); | ||
663 | } | ||
664 | |||
665 | /* Try, Get, Set & Enum format */ | ||
666 | case VIDIOC_ENUM_FMT: | ||
667 | { | ||
668 | struct v4l2_fmtdesc *fmt = arg; | ||
669 | struct uvc_format *format; | ||
670 | |||
671 | if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE || | ||
672 | fmt->index >= video->streaming->nformats) | ||
673 | return -EINVAL; | ||
674 | |||
675 | format = &video->streaming->format[fmt->index]; | ||
676 | fmt->flags = 0; | ||
677 | if (format->flags & UVC_FMT_FLAG_COMPRESSED) | ||
678 | fmt->flags |= V4L2_FMT_FLAG_COMPRESSED; | ||
679 | strncpy(fmt->description, format->name, | ||
680 | sizeof fmt->description); | ||
681 | fmt->description[sizeof fmt->description - 1] = 0; | ||
682 | fmt->pixelformat = format->fcc; | ||
683 | break; | ||
684 | } | ||
685 | |||
686 | case VIDIOC_TRY_FMT: | ||
687 | { | ||
688 | struct uvc_streaming_control probe; | ||
689 | |||
690 | if ((ret = uvc_acquire_privileges(handle)) < 0) | ||
691 | return ret; | ||
692 | |||
693 | return uvc_v4l2_try_format(video, arg, &probe, NULL, NULL); | ||
694 | } | ||
695 | |||
696 | case VIDIOC_S_FMT: | ||
697 | if ((ret = uvc_acquire_privileges(handle)) < 0) | ||
698 | return ret; | ||
699 | |||
700 | return uvc_v4l2_set_format(video, arg); | ||
701 | |||
702 | case VIDIOC_G_FMT: | ||
703 | return uvc_v4l2_get_format(video, arg); | ||
704 | |||
705 | /* Frame size enumeration */ | ||
706 | case VIDIOC_ENUM_FRAMESIZES: | ||
707 | { | ||
708 | struct v4l2_frmsizeenum *fsize = arg; | ||
709 | struct uvc_format *format = NULL; | ||
710 | struct uvc_frame *frame; | ||
711 | int i; | ||
712 | |||
713 | /* Look for the given pixel format */ | ||
714 | for (i = 0; i < video->streaming->nformats; i++) { | ||
715 | if (video->streaming->format[i].fcc == | ||
716 | fsize->pixel_format) { | ||
717 | format = &video->streaming->format[i]; | ||
718 | break; | ||
719 | } | ||
720 | } | ||
721 | if (format == NULL) | ||
722 | return -EINVAL; | ||
723 | |||
724 | if (fsize->index >= format->nframes) | ||
725 | return -EINVAL; | ||
726 | |||
727 | frame = &format->frame[fsize->index]; | ||
728 | fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; | ||
729 | fsize->discrete.width = frame->wWidth; | ||
730 | fsize->discrete.height = frame->wHeight; | ||
731 | break; | ||
732 | } | ||
733 | |||
734 | /* Frame interval enumeration */ | ||
735 | case VIDIOC_ENUM_FRAMEINTERVALS: | ||
736 | { | ||
737 | struct v4l2_frmivalenum *fival = arg; | ||
738 | struct uvc_format *format = NULL; | ||
739 | struct uvc_frame *frame = NULL; | ||
740 | int i; | ||
741 | |||
742 | /* Look for the given pixel format and frame size */ | ||
743 | for (i = 0; i < video->streaming->nformats; i++) { | ||
744 | if (video->streaming->format[i].fcc == | ||
745 | fival->pixel_format) { | ||
746 | format = &video->streaming->format[i]; | ||
747 | break; | ||
748 | } | ||
749 | } | ||
750 | if (format == NULL) | ||
751 | return -EINVAL; | ||
752 | |||
753 | for (i = 0; i < format->nframes; i++) { | ||
754 | if (format->frame[i].wWidth == fival->width && | ||
755 | format->frame[i].wHeight == fival->height) { | ||
756 | frame = &format->frame[i]; | ||
757 | break; | ||
758 | } | ||
759 | } | ||
760 | if (frame == NULL) | ||
761 | return -EINVAL; | ||
762 | |||
763 | if (frame->bFrameIntervalType) { | ||
764 | if (fival->index >= frame->bFrameIntervalType) | ||
765 | return -EINVAL; | ||
766 | |||
767 | fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; | ||
768 | fival->discrete.numerator = | ||
769 | frame->dwFrameInterval[fival->index]; | ||
770 | fival->discrete.denominator = 10000000; | ||
771 | uvc_simplify_fraction(&fival->discrete.numerator, | ||
772 | &fival->discrete.denominator, 8, 333); | ||
773 | } else { | ||
774 | fival->type = V4L2_FRMIVAL_TYPE_STEPWISE; | ||
775 | fival->stepwise.min.numerator = | ||
776 | frame->dwFrameInterval[0]; | ||
777 | fival->stepwise.min.denominator = 10000000; | ||
778 | fival->stepwise.max.numerator = | ||
779 | frame->dwFrameInterval[1]; | ||
780 | fival->stepwise.max.denominator = 10000000; | ||
781 | fival->stepwise.step.numerator = | ||
782 | frame->dwFrameInterval[2]; | ||
783 | fival->stepwise.step.denominator = 10000000; | ||
784 | uvc_simplify_fraction(&fival->stepwise.min.numerator, | ||
785 | &fival->stepwise.min.denominator, 8, 333); | ||
786 | uvc_simplify_fraction(&fival->stepwise.max.numerator, | ||
787 | &fival->stepwise.max.denominator, 8, 333); | ||
788 | uvc_simplify_fraction(&fival->stepwise.step.numerator, | ||
789 | &fival->stepwise.step.denominator, 8, 333); | ||
790 | } | ||
791 | break; | ||
792 | } | ||
793 | |||
794 | /* Get & Set streaming parameters */ | ||
795 | case VIDIOC_G_PARM: | ||
796 | return uvc_v4l2_get_streamparm(video, arg); | ||
797 | |||
798 | case VIDIOC_S_PARM: | ||
799 | if ((ret = uvc_acquire_privileges(handle)) < 0) | ||
800 | return ret; | ||
801 | |||
802 | return uvc_v4l2_set_streamparm(video, arg); | ||
803 | |||
804 | /* Cropping and scaling */ | ||
805 | case VIDIOC_CROPCAP: | ||
806 | { | ||
807 | struct v4l2_cropcap *ccap = arg; | ||
808 | struct uvc_frame *frame = video->streaming->cur_frame; | ||
809 | |||
810 | if (ccap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | ||
811 | return -EINVAL; | ||
812 | |||
813 | ccap->bounds.left = 0; | ||
814 | ccap->bounds.top = 0; | ||
815 | ccap->bounds.width = frame->wWidth; | ||
816 | ccap->bounds.height = frame->wHeight; | ||
817 | |||
818 | ccap->defrect = ccap->bounds; | ||
819 | |||
820 | ccap->pixelaspect.numerator = 1; | ||
821 | ccap->pixelaspect.denominator = 1; | ||
822 | break; | ||
823 | } | ||
824 | |||
825 | case VIDIOC_G_CROP: | ||
826 | case VIDIOC_S_CROP: | ||
827 | return -EINVAL; | ||
828 | |||
829 | /* Buffers & streaming */ | ||
830 | case VIDIOC_REQBUFS: | ||
831 | { | ||
832 | struct v4l2_requestbuffers *rb = arg; | ||
833 | unsigned int bufsize = | ||
834 | video->streaming->ctrl.dwMaxVideoFrameSize; | ||
835 | |||
836 | if (rb->type != V4L2_BUF_TYPE_VIDEO_CAPTURE || | ||
837 | rb->memory != V4L2_MEMORY_MMAP) | ||
838 | return -EINVAL; | ||
839 | |||
840 | if ((ret = uvc_acquire_privileges(handle)) < 0) | ||
841 | return ret; | ||
842 | |||
843 | ret = uvc_alloc_buffers(&video->queue, rb->count, bufsize); | ||
844 | if (ret < 0) | ||
845 | return ret; | ||
846 | |||
847 | if (!(video->streaming->cur_format->flags & | ||
848 | UVC_FMT_FLAG_COMPRESSED)) | ||
849 | video->queue.flags |= UVC_QUEUE_DROP_INCOMPLETE; | ||
850 | |||
851 | rb->count = ret; | ||
852 | ret = 0; | ||
853 | break; | ||
854 | } | ||
855 | |||
856 | case VIDIOC_QUERYBUF: | ||
857 | { | ||
858 | struct v4l2_buffer *buf = arg; | ||
859 | |||
860 | if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | ||
861 | return -EINVAL; | ||
862 | |||
863 | if (!uvc_has_privileges(handle)) | ||
864 | return -EBUSY; | ||
865 | |||
866 | return uvc_query_buffer(&video->queue, buf); | ||
867 | } | ||
868 | |||
869 | case VIDIOC_QBUF: | ||
870 | if (!uvc_has_privileges(handle)) | ||
871 | return -EBUSY; | ||
872 | |||
873 | return uvc_queue_buffer(&video->queue, arg); | ||
874 | |||
875 | case VIDIOC_DQBUF: | ||
876 | if (!uvc_has_privileges(handle)) | ||
877 | return -EBUSY; | ||
878 | |||
879 | return uvc_dequeue_buffer(&video->queue, arg, | ||
880 | file->f_flags & O_NONBLOCK); | ||
881 | |||
882 | case VIDIOC_STREAMON: | ||
883 | { | ||
884 | int *type = arg; | ||
885 | |||
886 | if (*type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | ||
887 | return -EINVAL; | ||
888 | |||
889 | if (!uvc_has_privileges(handle)) | ||
890 | return -EBUSY; | ||
891 | |||
892 | if ((ret = uvc_video_enable(video, 1)) < 0) | ||
893 | return ret; | ||
894 | break; | ||
895 | } | ||
896 | |||
897 | case VIDIOC_STREAMOFF: | ||
898 | { | ||
899 | int *type = arg; | ||
900 | |||
901 | if (*type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | ||
902 | return -EINVAL; | ||
903 | |||
904 | if (!uvc_has_privileges(handle)) | ||
905 | return -EBUSY; | ||
906 | |||
907 | return uvc_video_enable(video, 0); | ||
908 | } | ||
909 | |||
910 | /* Analog video standards make no sense for digital cameras. */ | ||
911 | case VIDIOC_ENUMSTD: | ||
912 | case VIDIOC_QUERYSTD: | ||
913 | case VIDIOC_G_STD: | ||
914 | case VIDIOC_S_STD: | ||
915 | |||
916 | case VIDIOC_OVERLAY: | ||
917 | |||
918 | case VIDIOC_ENUMAUDIO: | ||
919 | case VIDIOC_ENUMAUDOUT: | ||
920 | |||
921 | case VIDIOC_ENUMOUTPUT: | ||
922 | uvc_trace(UVC_TRACE_IOCTL, "Unsupported ioctl 0x%08x\n", cmd); | ||
923 | return -EINVAL; | ||
924 | |||
925 | /* Dynamic controls. */ | ||
926 | case UVCIOC_CTRL_ADD: | ||
927 | { | ||
928 | struct uvc_xu_control_info *xinfo = arg; | ||
929 | struct uvc_control_info *info; | ||
930 | |||
931 | if (!capable(CAP_SYS_ADMIN)) | ||
932 | return -EPERM; | ||
933 | |||
934 | info = kmalloc(sizeof *info, GFP_KERNEL); | ||
935 | if (info == NULL) | ||
936 | return -ENOMEM; | ||
937 | |||
938 | memcpy(info->entity, xinfo->entity, sizeof info->entity); | ||
939 | info->index = xinfo->index; | ||
940 | info->selector = xinfo->selector; | ||
941 | info->size = xinfo->size; | ||
942 | info->flags = xinfo->flags; | ||
943 | |||
944 | info->flags |= UVC_CONTROL_GET_MIN | UVC_CONTROL_GET_MAX | | ||
945 | UVC_CONTROL_GET_RES | UVC_CONTROL_GET_DEF; | ||
946 | |||
947 | ret = uvc_ctrl_add_info(info); | ||
948 | if (ret < 0) | ||
949 | kfree(info); | ||
950 | break; | ||
951 | } | ||
952 | |||
953 | case UVCIOC_CTRL_MAP: | ||
954 | { | ||
955 | struct uvc_xu_control_mapping *xmap = arg; | ||
956 | struct uvc_control_mapping *map; | ||
957 | |||
958 | if (!capable(CAP_SYS_ADMIN)) | ||
959 | return -EPERM; | ||
960 | |||
961 | map = kmalloc(sizeof *map, GFP_KERNEL); | ||
962 | if (map == NULL) | ||
963 | return -ENOMEM; | ||
964 | |||
965 | map->id = xmap->id; | ||
966 | memcpy(map->name, xmap->name, sizeof map->name); | ||
967 | memcpy(map->entity, xmap->entity, sizeof map->entity); | ||
968 | map->selector = xmap->selector; | ||
969 | map->size = xmap->size; | ||
970 | map->offset = xmap->offset; | ||
971 | map->v4l2_type = xmap->v4l2_type; | ||
972 | map->data_type = xmap->data_type; | ||
973 | |||
974 | ret = uvc_ctrl_add_mapping(map); | ||
975 | if (ret < 0) | ||
976 | kfree(map); | ||
977 | break; | ||
978 | } | ||
979 | |||
980 | case UVCIOC_CTRL_GET: | ||
981 | return uvc_xu_ctrl_query(video, arg, 0); | ||
982 | |||
983 | case UVCIOC_CTRL_SET: | ||
984 | return uvc_xu_ctrl_query(video, arg, 1); | ||
985 | |||
986 | default: | ||
987 | if ((ret = v4l_compat_translate_ioctl(inode, file, cmd, arg, | ||
988 | uvc_v4l2_do_ioctl)) == -ENOIOCTLCMD) | ||
989 | uvc_trace(UVC_TRACE_IOCTL, "Unknown ioctl 0x%08x\n", | ||
990 | cmd); | ||
991 | return ret; | ||
992 | } | ||
993 | |||
994 | return ret; | ||
995 | } | ||
996 | |||
997 | static int uvc_v4l2_ioctl(struct inode *inode, struct file *file, | ||
998 | unsigned int cmd, unsigned long arg) | ||
999 | { | ||
1000 | uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_ioctl\n"); | ||
1001 | return video_usercopy(inode, file, cmd, arg, uvc_v4l2_do_ioctl); | ||
1002 | } | ||
1003 | |||
1004 | static ssize_t uvc_v4l2_read(struct file *file, char __user *data, | ||
1005 | size_t count, loff_t *ppos) | ||
1006 | { | ||
1007 | uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_read: not implemented.\n"); | ||
1008 | return -ENODEV; | ||
1009 | } | ||
1010 | |||
1011 | /* | ||
1012 | * VMA operations. | ||
1013 | */ | ||
1014 | static void uvc_vm_open(struct vm_area_struct *vma) | ||
1015 | { | ||
1016 | struct uvc_buffer *buffer = vma->vm_private_data; | ||
1017 | buffer->vma_use_count++; | ||
1018 | } | ||
1019 | |||
1020 | static void uvc_vm_close(struct vm_area_struct *vma) | ||
1021 | { | ||
1022 | struct uvc_buffer *buffer = vma->vm_private_data; | ||
1023 | buffer->vma_use_count--; | ||
1024 | } | ||
1025 | |||
1026 | static struct vm_operations_struct uvc_vm_ops = { | ||
1027 | .open = uvc_vm_open, | ||
1028 | .close = uvc_vm_close, | ||
1029 | }; | ||
1030 | |||
1031 | static int uvc_v4l2_mmap(struct file *file, struct vm_area_struct *vma) | ||
1032 | { | ||
1033 | struct video_device *vdev = video_devdata(file); | ||
1034 | struct uvc_video_device *video = video_get_drvdata(vdev); | ||
1035 | struct uvc_buffer *buffer; | ||
1036 | struct page *page; | ||
1037 | unsigned long addr, start, size; | ||
1038 | unsigned int i; | ||
1039 | int ret = 0; | ||
1040 | |||
1041 | uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_mmap\n"); | ||
1042 | |||
1043 | start = vma->vm_start; | ||
1044 | size = vma->vm_end - vma->vm_start; | ||
1045 | |||
1046 | mutex_lock(&video->queue.mutex); | ||
1047 | |||
1048 | for (i = 0; i < video->queue.count; ++i) { | ||
1049 | buffer = &video->queue.buffer[i]; | ||
1050 | if ((buffer->buf.m.offset >> PAGE_SHIFT) == vma->vm_pgoff) | ||
1051 | break; | ||
1052 | } | ||
1053 | |||
1054 | if (i == video->queue.count || size != video->queue.buf_size) { | ||
1055 | ret = -EINVAL; | ||
1056 | goto done; | ||
1057 | } | ||
1058 | |||
1059 | /* | ||
1060 | * VM_IO marks the area as being an mmaped region for I/O to a | ||
1061 | * device. It also prevents the region from being core dumped. | ||
1062 | */ | ||
1063 | vma->vm_flags |= VM_IO; | ||
1064 | |||
1065 | addr = (unsigned long)video->queue.mem + buffer->buf.m.offset; | ||
1066 | while (size > 0) { | ||
1067 | page = vmalloc_to_page((void *)addr); | ||
1068 | if ((ret = vm_insert_page(vma, start, page)) < 0) | ||
1069 | goto done; | ||
1070 | |||
1071 | start += PAGE_SIZE; | ||
1072 | addr += PAGE_SIZE; | ||
1073 | size -= PAGE_SIZE; | ||
1074 | } | ||
1075 | |||
1076 | vma->vm_ops = &uvc_vm_ops; | ||
1077 | vma->vm_private_data = buffer; | ||
1078 | uvc_vm_open(vma); | ||
1079 | |||
1080 | done: | ||
1081 | mutex_unlock(&video->queue.mutex); | ||
1082 | return ret; | ||
1083 | } | ||
1084 | |||
1085 | static unsigned int uvc_v4l2_poll(struct file *file, poll_table *wait) | ||
1086 | { | ||
1087 | struct video_device *vdev = video_devdata(file); | ||
1088 | struct uvc_video_device *video = video_get_drvdata(vdev); | ||
1089 | |||
1090 | uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_poll\n"); | ||
1091 | |||
1092 | return uvc_queue_poll(&video->queue, file, wait); | ||
1093 | } | ||
1094 | |||
1095 | struct file_operations uvc_fops = { | ||
1096 | .owner = THIS_MODULE, | ||
1097 | .open = uvc_v4l2_open, | ||
1098 | .release = uvc_v4l2_release, | ||
1099 | .ioctl = uvc_v4l2_ioctl, | ||
1100 | .compat_ioctl = v4l_compat_ioctl32, | ||
1101 | .llseek = no_llseek, | ||
1102 | .read = uvc_v4l2_read, | ||
1103 | .mmap = uvc_v4l2_mmap, | ||
1104 | .poll = uvc_v4l2_poll, | ||
1105 | }; | ||
diff --git a/drivers/media/video/uvc/uvc_video.c b/drivers/media/video/uvc/uvc_video.c new file mode 100644 index 000000000000..6faf1fb21614 --- /dev/null +++ b/drivers/media/video/uvc/uvc_video.c | |||
@@ -0,0 +1,934 @@ | |||
1 | /* | ||
2 | * uvc_video.c -- USB Video Class driver - Video handling | ||
3 | * | ||
4 | * Copyright (C) 2005-2008 | ||
5 | * Laurent Pinchart (laurent.pinchart@skynet.be) | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/version.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/usb.h> | ||
19 | #include <linux/videodev2.h> | ||
20 | #include <linux/vmalloc.h> | ||
21 | #include <linux/wait.h> | ||
22 | #include <asm/atomic.h> | ||
23 | #include <asm/unaligned.h> | ||
24 | |||
25 | #include <media/v4l2-common.h> | ||
26 | |||
27 | #include "uvcvideo.h" | ||
28 | |||
29 | /* ------------------------------------------------------------------------ | ||
30 | * UVC Controls | ||
31 | */ | ||
32 | |||
33 | static int __uvc_query_ctrl(struct uvc_device *dev, __u8 query, __u8 unit, | ||
34 | __u8 intfnum, __u8 cs, void *data, __u16 size, | ||
35 | int timeout) | ||
36 | { | ||
37 | __u8 type = USB_TYPE_CLASS | USB_RECIP_INTERFACE; | ||
38 | unsigned int pipe; | ||
39 | int ret; | ||
40 | |||
41 | pipe = (query & 0x80) ? usb_rcvctrlpipe(dev->udev, 0) | ||
42 | : usb_sndctrlpipe(dev->udev, 0); | ||
43 | type |= (query & 0x80) ? USB_DIR_IN : USB_DIR_OUT; | ||
44 | |||
45 | ret = usb_control_msg(dev->udev, pipe, query, type, cs << 8, | ||
46 | unit << 8 | intfnum, data, size, timeout); | ||
47 | |||
48 | if (ret != size) { | ||
49 | uvc_printk(KERN_ERR, "Failed to query (%u) UVC control %u " | ||
50 | "(unit %u) : %d (exp. %u).\n", query, cs, unit, ret, | ||
51 | size); | ||
52 | return -EIO; | ||
53 | } | ||
54 | |||
55 | return 0; | ||
56 | } | ||
57 | |||
58 | int uvc_query_ctrl(struct uvc_device *dev, __u8 query, __u8 unit, | ||
59 | __u8 intfnum, __u8 cs, void *data, __u16 size) | ||
60 | { | ||
61 | return __uvc_query_ctrl(dev, query, unit, intfnum, cs, data, size, | ||
62 | UVC_CTRL_CONTROL_TIMEOUT); | ||
63 | } | ||
64 | |||
65 | static void uvc_fixup_buffer_size(struct uvc_video_device *video, | ||
66 | struct uvc_streaming_control *ctrl) | ||
67 | { | ||
68 | struct uvc_format *format; | ||
69 | struct uvc_frame *frame; | ||
70 | |||
71 | if (ctrl->bFormatIndex <= 0 || | ||
72 | ctrl->bFormatIndex > video->streaming->nformats) | ||
73 | return; | ||
74 | |||
75 | format = &video->streaming->format[ctrl->bFormatIndex - 1]; | ||
76 | |||
77 | if (ctrl->bFrameIndex <= 0 || | ||
78 | ctrl->bFrameIndex > format->nframes) | ||
79 | return; | ||
80 | |||
81 | frame = &format->frame[ctrl->bFrameIndex - 1]; | ||
82 | |||
83 | if (!(format->flags & UVC_FMT_FLAG_COMPRESSED) || | ||
84 | (ctrl->dwMaxVideoFrameSize == 0 && | ||
85 | video->dev->uvc_version < 0x0110)) | ||
86 | ctrl->dwMaxVideoFrameSize = | ||
87 | frame->dwMaxVideoFrameBufferSize; | ||
88 | } | ||
89 | |||
90 | static int uvc_get_video_ctrl(struct uvc_video_device *video, | ||
91 | struct uvc_streaming_control *ctrl, int probe, __u8 query) | ||
92 | { | ||
93 | __u8 data[34]; | ||
94 | __u8 size; | ||
95 | int ret; | ||
96 | |||
97 | size = video->dev->uvc_version >= 0x0110 ? 34 : 26; | ||
98 | ret = __uvc_query_ctrl(video->dev, query, 0, video->streaming->intfnum, | ||
99 | probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, &data, size, | ||
100 | UVC_CTRL_STREAMING_TIMEOUT); | ||
101 | |||
102 | if (ret < 0) | ||
103 | return ret; | ||
104 | |||
105 | ctrl->bmHint = le16_to_cpup((__le16 *)&data[0]); | ||
106 | ctrl->bFormatIndex = data[2]; | ||
107 | ctrl->bFrameIndex = data[3]; | ||
108 | ctrl->dwFrameInterval = le32_to_cpup((__le32 *)&data[4]); | ||
109 | ctrl->wKeyFrameRate = le16_to_cpup((__le16 *)&data[8]); | ||
110 | ctrl->wPFrameRate = le16_to_cpup((__le16 *)&data[10]); | ||
111 | ctrl->wCompQuality = le16_to_cpup((__le16 *)&data[12]); | ||
112 | ctrl->wCompWindowSize = le16_to_cpup((__le16 *)&data[14]); | ||
113 | ctrl->wDelay = le16_to_cpup((__le16 *)&data[16]); | ||
114 | ctrl->dwMaxVideoFrameSize = | ||
115 | le32_to_cpu(get_unaligned((__le32 *)&data[18])); | ||
116 | ctrl->dwMaxPayloadTransferSize = | ||
117 | le32_to_cpu(get_unaligned((__le32 *)&data[22])); | ||
118 | |||
119 | if (size == 34) { | ||
120 | ctrl->dwClockFrequency = | ||
121 | le32_to_cpu(get_unaligned((__le32 *)&data[26])); | ||
122 | ctrl->bmFramingInfo = data[30]; | ||
123 | ctrl->bPreferedVersion = data[31]; | ||
124 | ctrl->bMinVersion = data[32]; | ||
125 | ctrl->bMaxVersion = data[33]; | ||
126 | } else { | ||
127 | ctrl->dwClockFrequency = video->dev->clock_frequency; | ||
128 | ctrl->bmFramingInfo = 0; | ||
129 | ctrl->bPreferedVersion = 0; | ||
130 | ctrl->bMinVersion = 0; | ||
131 | ctrl->bMaxVersion = 0; | ||
132 | } | ||
133 | |||
134 | /* Some broken devices return a null or wrong dwMaxVideoFrameSize. | ||
135 | * Try to get the value from the format and frame descriptor. | ||
136 | */ | ||
137 | uvc_fixup_buffer_size(video, ctrl); | ||
138 | |||
139 | return 0; | ||
140 | } | ||
141 | |||
142 | int uvc_set_video_ctrl(struct uvc_video_device *video, | ||
143 | struct uvc_streaming_control *ctrl, int probe) | ||
144 | { | ||
145 | __u8 data[34]; | ||
146 | __u8 size; | ||
147 | |||
148 | size = video->dev->uvc_version >= 0x0110 ? 34 : 26; | ||
149 | memset(data, 0, sizeof data); | ||
150 | |||
151 | *(__le16 *)&data[0] = cpu_to_le16(ctrl->bmHint); | ||
152 | data[2] = ctrl->bFormatIndex; | ||
153 | data[3] = ctrl->bFrameIndex; | ||
154 | *(__le32 *)&data[4] = cpu_to_le32(ctrl->dwFrameInterval); | ||
155 | *(__le16 *)&data[8] = cpu_to_le16(ctrl->wKeyFrameRate); | ||
156 | *(__le16 *)&data[10] = cpu_to_le16(ctrl->wPFrameRate); | ||
157 | *(__le16 *)&data[12] = cpu_to_le16(ctrl->wCompQuality); | ||
158 | *(__le16 *)&data[14] = cpu_to_le16(ctrl->wCompWindowSize); | ||
159 | *(__le16 *)&data[16] = cpu_to_le16(ctrl->wDelay); | ||
160 | /* Note: Some of the fields below are not required for IN devices (see | ||
161 | * UVC spec, 4.3.1.1), but we still copy them in case support for OUT | ||
162 | * devices is added in the future. */ | ||
163 | put_unaligned(cpu_to_le32(ctrl->dwMaxVideoFrameSize), | ||
164 | (__le32 *)&data[18]); | ||
165 | put_unaligned(cpu_to_le32(ctrl->dwMaxPayloadTransferSize), | ||
166 | (__le32 *)&data[22]); | ||
167 | |||
168 | if (size == 34) { | ||
169 | put_unaligned(cpu_to_le32(ctrl->dwClockFrequency), | ||
170 | (__le32 *)&data[26]); | ||
171 | data[30] = ctrl->bmFramingInfo; | ||
172 | data[31] = ctrl->bPreferedVersion; | ||
173 | data[32] = ctrl->bMinVersion; | ||
174 | data[33] = ctrl->bMaxVersion; | ||
175 | } | ||
176 | |||
177 | return __uvc_query_ctrl(video->dev, SET_CUR, 0, | ||
178 | video->streaming->intfnum, | ||
179 | probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, &data, size, | ||
180 | UVC_CTRL_STREAMING_TIMEOUT); | ||
181 | } | ||
182 | |||
183 | int uvc_probe_video(struct uvc_video_device *video, | ||
184 | struct uvc_streaming_control *probe) | ||
185 | { | ||
186 | struct uvc_streaming_control probe_min, probe_max; | ||
187 | __u16 bandwidth; | ||
188 | unsigned int i; | ||
189 | int ret; | ||
190 | |||
191 | mutex_lock(&video->streaming->mutex); | ||
192 | |||
193 | /* Perform probing. The device should adjust the requested values | ||
194 | * according to its capabilities. However, some devices, namely the | ||
195 | * first generation UVC Logitech webcams, don't implement the Video | ||
196 | * Probe control properly, and just return the needed bandwidth. For | ||
197 | * that reason, if the needed bandwidth exceeds the maximum available | ||
198 | * bandwidth, try to lower the quality. | ||
199 | */ | ||
200 | if ((ret = uvc_set_video_ctrl(video, probe, 1)) < 0) | ||
201 | goto done; | ||
202 | |||
203 | /* Get the minimum and maximum values for compression settings. */ | ||
204 | if (!(video->dev->quirks & UVC_QUIRK_PROBE_MINMAX)) { | ||
205 | ret = uvc_get_video_ctrl(video, &probe_min, 1, GET_MIN); | ||
206 | if (ret < 0) | ||
207 | goto done; | ||
208 | ret = uvc_get_video_ctrl(video, &probe_max, 1, GET_MAX); | ||
209 | if (ret < 0) | ||
210 | goto done; | ||
211 | |||
212 | probe->wCompQuality = probe_max.wCompQuality; | ||
213 | } | ||
214 | |||
215 | for (i = 0; i < 2; ++i) { | ||
216 | if ((ret = uvc_set_video_ctrl(video, probe, 1)) < 0 || | ||
217 | (ret = uvc_get_video_ctrl(video, probe, 1, GET_CUR)) < 0) | ||
218 | goto done; | ||
219 | |||
220 | if (video->streaming->intf->num_altsetting == 1) | ||
221 | break; | ||
222 | |||
223 | bandwidth = probe->dwMaxPayloadTransferSize; | ||
224 | if (bandwidth <= video->streaming->maxpsize) | ||
225 | break; | ||
226 | |||
227 | if (video->dev->quirks & UVC_QUIRK_PROBE_MINMAX) { | ||
228 | ret = -ENOSPC; | ||
229 | goto done; | ||
230 | } | ||
231 | |||
232 | /* TODO: negotiate compression parameters */ | ||
233 | probe->wKeyFrameRate = probe_min.wKeyFrameRate; | ||
234 | probe->wPFrameRate = probe_min.wPFrameRate; | ||
235 | probe->wCompQuality = probe_max.wCompQuality; | ||
236 | probe->wCompWindowSize = probe_min.wCompWindowSize; | ||
237 | } | ||
238 | |||
239 | done: | ||
240 | mutex_unlock(&video->streaming->mutex); | ||
241 | return ret; | ||
242 | } | ||
243 | |||
244 | /* ------------------------------------------------------------------------ | ||
245 | * Video codecs | ||
246 | */ | ||
247 | |||
248 | /* Values for bmHeaderInfo (Video and Still Image Payload Headers, 2.4.3.3) */ | ||
249 | #define UVC_STREAM_EOH (1 << 7) | ||
250 | #define UVC_STREAM_ERR (1 << 6) | ||
251 | #define UVC_STREAM_STI (1 << 5) | ||
252 | #define UVC_STREAM_RES (1 << 4) | ||
253 | #define UVC_STREAM_SCR (1 << 3) | ||
254 | #define UVC_STREAM_PTS (1 << 2) | ||
255 | #define UVC_STREAM_EOF (1 << 1) | ||
256 | #define UVC_STREAM_FID (1 << 0) | ||
257 | |||
258 | /* Video payload decoding is handled by uvc_video_decode_start(), | ||
259 | * uvc_video_decode_data() and uvc_video_decode_end(). | ||
260 | * | ||
261 | * uvc_video_decode_start is called with URB data at the start of a bulk or | ||
262 | * isochronous payload. It processes header data and returns the header size | ||
263 | * in bytes if successful. If an error occurs, it returns a negative error | ||
264 | * code. The following error codes have special meanings. | ||
265 | * | ||
266 | * - EAGAIN informs the caller that the current video buffer should be marked | ||
267 | * as done, and that the function should be called again with the same data | ||
268 | * and a new video buffer. This is used when end of frame conditions can be | ||
269 | * reliably detected at the beginning of the next frame only. | ||
270 | * | ||
271 | * If an error other than -EAGAIN is returned, the caller will drop the current | ||
272 | * payload. No call to uvc_video_decode_data and uvc_video_decode_end will be | ||
273 | * made until the next payload. -ENODATA can be used to drop the current | ||
274 | * payload if no other error code is appropriate. | ||
275 | * | ||
276 | * uvc_video_decode_data is called for every URB with URB data. It copies the | ||
277 | * data to the video buffer. | ||
278 | * | ||
279 | * uvc_video_decode_end is called with header data at the end of a bulk or | ||
280 | * isochronous payload. It performs any additional header data processing and | ||
281 | * returns 0 or a negative error code if an error occured. As header data have | ||
282 | * already been processed by uvc_video_decode_start, this functions isn't | ||
283 | * required to perform sanity checks a second time. | ||
284 | * | ||
285 | * For isochronous transfers where a payload is always transfered in a single | ||
286 | * URB, the three functions will be called in a row. | ||
287 | * | ||
288 | * To let the decoder process header data and update its internal state even | ||
289 | * when no video buffer is available, uvc_video_decode_start must be prepared | ||
290 | * to be called with a NULL buf parameter. uvc_video_decode_data and | ||
291 | * uvc_video_decode_end will never be called with a NULL buffer. | ||
292 | */ | ||
293 | static int uvc_video_decode_start(struct uvc_video_device *video, | ||
294 | struct uvc_buffer *buf, const __u8 *data, int len) | ||
295 | { | ||
296 | __u8 fid; | ||
297 | |||
298 | /* Sanity checks: | ||
299 | * - packet must be at least 2 bytes long | ||
300 | * - bHeaderLength value must be at least 2 bytes (see above) | ||
301 | * - bHeaderLength value can't be larger than the packet size. | ||
302 | */ | ||
303 | if (len < 2 || data[0] < 2 || data[0] > len) | ||
304 | return -EINVAL; | ||
305 | |||
306 | /* Skip payloads marked with the error bit ("error frames"). */ | ||
307 | if (data[1] & UVC_STREAM_ERR) { | ||
308 | uvc_trace(UVC_TRACE_FRAME, "Dropping payload (error bit " | ||
309 | "set).\n"); | ||
310 | return -ENODATA; | ||
311 | } | ||
312 | |||
313 | fid = data[1] & UVC_STREAM_FID; | ||
314 | |||
315 | /* Store the payload FID bit and return immediately when the buffer is | ||
316 | * NULL. | ||
317 | */ | ||
318 | if (buf == NULL) { | ||
319 | video->last_fid = fid; | ||
320 | return -ENODATA; | ||
321 | } | ||
322 | |||
323 | /* Synchronize to the input stream by waiting for the FID bit to be | ||
324 | * toggled when the the buffer state is not UVC_BUF_STATE_ACTIVE. | ||
325 | * queue->last_fid is initialized to -1, so the first isochronous | ||
326 | * frame will always be in sync. | ||
327 | * | ||
328 | * If the device doesn't toggle the FID bit, invert video->last_fid | ||
329 | * when the EOF bit is set to force synchronisation on the next packet. | ||
330 | */ | ||
331 | if (buf->state != UVC_BUF_STATE_ACTIVE) { | ||
332 | if (fid == video->last_fid) { | ||
333 | uvc_trace(UVC_TRACE_FRAME, "Dropping payload (out of " | ||
334 | "sync).\n"); | ||
335 | if ((video->dev->quirks & UVC_QUIRK_STREAM_NO_FID) && | ||
336 | (data[1] & UVC_STREAM_EOF)) | ||
337 | video->last_fid ^= UVC_STREAM_FID; | ||
338 | return -ENODATA; | ||
339 | } | ||
340 | |||
341 | /* TODO: Handle PTS and SCR. */ | ||
342 | buf->state = UVC_BUF_STATE_ACTIVE; | ||
343 | } | ||
344 | |||
345 | /* Mark the buffer as done if we're at the beginning of a new frame. | ||
346 | * End of frame detection is better implemented by checking the EOF | ||
347 | * bit (FID bit toggling is delayed by one frame compared to the EOF | ||
348 | * bit), but some devices don't set the bit at end of frame (and the | ||
349 | * last payload can be lost anyway). We thus must check if the FID has | ||
350 | * been toggled. | ||
351 | * | ||
352 | * queue->last_fid is initialized to -1, so the first isochronous | ||
353 | * frame will never trigger an end of frame detection. | ||
354 | * | ||
355 | * Empty buffers (bytesused == 0) don't trigger end of frame detection | ||
356 | * as it doesn't make sense to return an empty buffer. This also | ||
357 | * avoids detecting and of frame conditions at FID toggling if the | ||
358 | * previous payload had the EOF bit set. | ||
359 | */ | ||
360 | if (fid != video->last_fid && buf->buf.bytesused != 0) { | ||
361 | uvc_trace(UVC_TRACE_FRAME, "Frame complete (FID bit " | ||
362 | "toggled).\n"); | ||
363 | buf->state = UVC_BUF_STATE_DONE; | ||
364 | return -EAGAIN; | ||
365 | } | ||
366 | |||
367 | video->last_fid = fid; | ||
368 | |||
369 | return data[0]; | ||
370 | } | ||
371 | |||
372 | static void uvc_video_decode_data(struct uvc_video_device *video, | ||
373 | struct uvc_buffer *buf, const __u8 *data, int len) | ||
374 | { | ||
375 | struct uvc_video_queue *queue = &video->queue; | ||
376 | unsigned int maxlen, nbytes; | ||
377 | void *mem; | ||
378 | |||
379 | if (len <= 0) | ||
380 | return; | ||
381 | |||
382 | /* Copy the video data to the buffer. */ | ||
383 | maxlen = buf->buf.length - buf->buf.bytesused; | ||
384 | mem = queue->mem + buf->buf.m.offset + buf->buf.bytesused; | ||
385 | nbytes = min((unsigned int)len, maxlen); | ||
386 | memcpy(mem, data, nbytes); | ||
387 | buf->buf.bytesused += nbytes; | ||
388 | |||
389 | /* Complete the current frame if the buffer size was exceeded. */ | ||
390 | if (len > maxlen) { | ||
391 | uvc_trace(UVC_TRACE_FRAME, "Frame complete (overflow).\n"); | ||
392 | buf->state = UVC_BUF_STATE_DONE; | ||
393 | } | ||
394 | } | ||
395 | |||
396 | static void uvc_video_decode_end(struct uvc_video_device *video, | ||
397 | struct uvc_buffer *buf, const __u8 *data, int len) | ||
398 | { | ||
399 | /* Mark the buffer as done if the EOF marker is set. */ | ||
400 | if (data[1] & UVC_STREAM_EOF && buf->buf.bytesused != 0) { | ||
401 | uvc_trace(UVC_TRACE_FRAME, "Frame complete (EOF found).\n"); | ||
402 | if (data[0] == len) | ||
403 | uvc_trace(UVC_TRACE_FRAME, "EOF in empty payload.\n"); | ||
404 | buf->state = UVC_BUF_STATE_DONE; | ||
405 | if (video->dev->quirks & UVC_QUIRK_STREAM_NO_FID) | ||
406 | video->last_fid ^= UVC_STREAM_FID; | ||
407 | } | ||
408 | } | ||
409 | |||
410 | /* ------------------------------------------------------------------------ | ||
411 | * URB handling | ||
412 | */ | ||
413 | |||
414 | /* | ||
415 | * Completion handler for video URBs. | ||
416 | */ | ||
417 | static void uvc_video_decode_isoc(struct urb *urb, | ||
418 | struct uvc_video_device *video, struct uvc_buffer *buf) | ||
419 | { | ||
420 | u8 *mem; | ||
421 | int ret, i; | ||
422 | |||
423 | for (i = 0; i < urb->number_of_packets; ++i) { | ||
424 | if (urb->iso_frame_desc[i].status < 0) { | ||
425 | uvc_trace(UVC_TRACE_FRAME, "USB isochronous frame " | ||
426 | "lost (%d).\n", urb->iso_frame_desc[i].status); | ||
427 | continue; | ||
428 | } | ||
429 | |||
430 | /* Decode the payload header. */ | ||
431 | mem = urb->transfer_buffer + urb->iso_frame_desc[i].offset; | ||
432 | do { | ||
433 | ret = uvc_video_decode_start(video, buf, mem, | ||
434 | urb->iso_frame_desc[i].actual_length); | ||
435 | if (ret == -EAGAIN) | ||
436 | buf = uvc_queue_next_buffer(&video->queue, buf); | ||
437 | } while (ret == -EAGAIN); | ||
438 | |||
439 | if (ret < 0) | ||
440 | continue; | ||
441 | |||
442 | /* Decode the payload data. */ | ||
443 | uvc_video_decode_data(video, buf, mem + ret, | ||
444 | urb->iso_frame_desc[i].actual_length - ret); | ||
445 | |||
446 | /* Process the header again. */ | ||
447 | uvc_video_decode_end(video, buf, mem, ret); | ||
448 | |||
449 | if (buf->state == UVC_BUF_STATE_DONE || | ||
450 | buf->state == UVC_BUF_STATE_ERROR) | ||
451 | buf = uvc_queue_next_buffer(&video->queue, buf); | ||
452 | } | ||
453 | } | ||
454 | |||
455 | static void uvc_video_decode_bulk(struct urb *urb, | ||
456 | struct uvc_video_device *video, struct uvc_buffer *buf) | ||
457 | { | ||
458 | u8 *mem; | ||
459 | int len, ret; | ||
460 | |||
461 | mem = urb->transfer_buffer; | ||
462 | len = urb->actual_length; | ||
463 | video->bulk.payload_size += len; | ||
464 | |||
465 | /* If the URB is the first of its payload, decode and save the | ||
466 | * header. | ||
467 | */ | ||
468 | if (video->bulk.header_size == 0) { | ||
469 | do { | ||
470 | ret = uvc_video_decode_start(video, buf, mem, len); | ||
471 | if (ret == -EAGAIN) | ||
472 | buf = uvc_queue_next_buffer(&video->queue, buf); | ||
473 | } while (ret == -EAGAIN); | ||
474 | |||
475 | /* If an error occured skip the rest of the payload. */ | ||
476 | if (ret < 0 || buf == NULL) { | ||
477 | video->bulk.skip_payload = 1; | ||
478 | return; | ||
479 | } | ||
480 | |||
481 | video->bulk.header_size = ret; | ||
482 | memcpy(video->bulk.header, mem, video->bulk.header_size); | ||
483 | |||
484 | mem += ret; | ||
485 | len -= ret; | ||
486 | } | ||
487 | |||
488 | /* The buffer queue might have been cancelled while a bulk transfer | ||
489 | * was in progress, so we can reach here with buf equal to NULL. Make | ||
490 | * sure buf is never dereferenced if NULL. | ||
491 | */ | ||
492 | |||
493 | /* Process video data. */ | ||
494 | if (!video->bulk.skip_payload && buf != NULL) | ||
495 | uvc_video_decode_data(video, buf, mem, len); | ||
496 | |||
497 | /* Detect the payload end by a URB smaller than the maximum size (or | ||
498 | * a payload size equal to the maximum) and process the header again. | ||
499 | */ | ||
500 | if (urb->actual_length < urb->transfer_buffer_length || | ||
501 | video->bulk.payload_size >= video->bulk.max_payload_size) { | ||
502 | if (!video->bulk.skip_payload && buf != NULL) { | ||
503 | uvc_video_decode_end(video, buf, video->bulk.header, | ||
504 | video->bulk.header_size); | ||
505 | if (buf->state == UVC_BUF_STATE_DONE || | ||
506 | buf->state == UVC_BUF_STATE_ERROR) | ||
507 | buf = uvc_queue_next_buffer(&video->queue, buf); | ||
508 | } | ||
509 | |||
510 | video->bulk.header_size = 0; | ||
511 | video->bulk.skip_payload = 0; | ||
512 | video->bulk.payload_size = 0; | ||
513 | } | ||
514 | } | ||
515 | |||
516 | static void uvc_video_complete(struct urb *urb) | ||
517 | { | ||
518 | struct uvc_video_device *video = urb->context; | ||
519 | struct uvc_video_queue *queue = &video->queue; | ||
520 | struct uvc_buffer *buf = NULL; | ||
521 | unsigned long flags; | ||
522 | int ret; | ||
523 | |||
524 | switch (urb->status) { | ||
525 | case 0: | ||
526 | break; | ||
527 | |||
528 | default: | ||
529 | uvc_printk(KERN_WARNING, "Non-zero status (%d) in video " | ||
530 | "completion handler.\n", urb->status); | ||
531 | |||
532 | case -ENOENT: /* usb_kill_urb() called. */ | ||
533 | if (video->frozen) | ||
534 | return; | ||
535 | |||
536 | case -ECONNRESET: /* usb_unlink_urb() called. */ | ||
537 | case -ESHUTDOWN: /* The endpoint is being disabled. */ | ||
538 | uvc_queue_cancel(queue, urb->status == -ESHUTDOWN); | ||
539 | return; | ||
540 | } | ||
541 | |||
542 | spin_lock_irqsave(&queue->irqlock, flags); | ||
543 | if (!list_empty(&queue->irqqueue)) | ||
544 | buf = list_first_entry(&queue->irqqueue, struct uvc_buffer, | ||
545 | queue); | ||
546 | spin_unlock_irqrestore(&queue->irqlock, flags); | ||
547 | |||
548 | video->decode(urb, video, buf); | ||
549 | |||
550 | if ((ret = usb_submit_urb(urb, GFP_ATOMIC)) < 0) { | ||
551 | uvc_printk(KERN_ERR, "Failed to resubmit video URB (%d).\n", | ||
552 | ret); | ||
553 | } | ||
554 | } | ||
555 | |||
556 | /* | ||
557 | * Uninitialize isochronous/bulk URBs and free transfer buffers. | ||
558 | */ | ||
559 | static void uvc_uninit_video(struct uvc_video_device *video) | ||
560 | { | ||
561 | struct urb *urb; | ||
562 | unsigned int i; | ||
563 | |||
564 | for (i = 0; i < UVC_URBS; ++i) { | ||
565 | if ((urb = video->urb[i]) == NULL) | ||
566 | continue; | ||
567 | |||
568 | usb_kill_urb(urb); | ||
569 | /* urb->transfer_buffer_length is not touched by USB core, so | ||
570 | * we can use it here as the buffer length. | ||
571 | */ | ||
572 | if (video->urb_buffer[i]) { | ||
573 | usb_buffer_free(video->dev->udev, | ||
574 | urb->transfer_buffer_length, | ||
575 | video->urb_buffer[i], urb->transfer_dma); | ||
576 | video->urb_buffer[i] = NULL; | ||
577 | } | ||
578 | |||
579 | usb_free_urb(urb); | ||
580 | video->urb[i] = NULL; | ||
581 | } | ||
582 | } | ||
583 | |||
584 | /* | ||
585 | * Initialize isochronous URBs and allocate transfer buffers. The packet size | ||
586 | * is given by the endpoint. | ||
587 | */ | ||
588 | static int uvc_init_video_isoc(struct uvc_video_device *video, | ||
589 | struct usb_host_endpoint *ep) | ||
590 | { | ||
591 | struct urb *urb; | ||
592 | unsigned int npackets, i, j; | ||
593 | __u16 psize; | ||
594 | __u32 size; | ||
595 | |||
596 | /* Compute the number of isochronous packets to allocate by dividing | ||
597 | * the maximum video frame size by the packet size. Limit the result | ||
598 | * to UVC_MAX_ISO_PACKETS. | ||
599 | */ | ||
600 | psize = le16_to_cpu(ep->desc.wMaxPacketSize); | ||
601 | psize = (psize & 0x07ff) * (1 + ((psize >> 11) & 3)); | ||
602 | |||
603 | size = video->streaming->ctrl.dwMaxVideoFrameSize; | ||
604 | if (size > UVC_MAX_FRAME_SIZE) | ||
605 | return -EINVAL; | ||
606 | |||
607 | npackets = (size + psize - 1) / psize; | ||
608 | if (npackets > UVC_MAX_ISO_PACKETS) | ||
609 | npackets = UVC_MAX_ISO_PACKETS; | ||
610 | |||
611 | size = npackets * psize; | ||
612 | |||
613 | for (i = 0; i < UVC_URBS; ++i) { | ||
614 | urb = usb_alloc_urb(npackets, GFP_KERNEL); | ||
615 | if (urb == NULL) { | ||
616 | uvc_uninit_video(video); | ||
617 | return -ENOMEM; | ||
618 | } | ||
619 | |||
620 | video->urb_buffer[i] = usb_buffer_alloc(video->dev->udev, | ||
621 | size, GFP_KERNEL, &urb->transfer_dma); | ||
622 | if (video->urb_buffer[i] == NULL) { | ||
623 | usb_free_urb(urb); | ||
624 | uvc_uninit_video(video); | ||
625 | return -ENOMEM; | ||
626 | } | ||
627 | |||
628 | urb->dev = video->dev->udev; | ||
629 | urb->context = video; | ||
630 | urb->pipe = usb_rcvisocpipe(video->dev->udev, | ||
631 | ep->desc.bEndpointAddress); | ||
632 | urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP; | ||
633 | urb->interval = ep->desc.bInterval; | ||
634 | urb->transfer_buffer = video->urb_buffer[i]; | ||
635 | urb->complete = uvc_video_complete; | ||
636 | urb->number_of_packets = npackets; | ||
637 | urb->transfer_buffer_length = size; | ||
638 | |||
639 | for (j = 0; j < npackets; ++j) { | ||
640 | urb->iso_frame_desc[j].offset = j * psize; | ||
641 | urb->iso_frame_desc[j].length = psize; | ||
642 | } | ||
643 | |||
644 | video->urb[i] = urb; | ||
645 | } | ||
646 | |||
647 | return 0; | ||
648 | } | ||
649 | |||
650 | /* | ||
651 | * Initialize bulk URBs and allocate transfer buffers. The packet size is | ||
652 | * given by the endpoint. | ||
653 | */ | ||
654 | static int uvc_init_video_bulk(struct uvc_video_device *video, | ||
655 | struct usb_host_endpoint *ep) | ||
656 | { | ||
657 | struct urb *urb; | ||
658 | unsigned int pipe, i; | ||
659 | __u16 psize; | ||
660 | __u32 size; | ||
661 | |||
662 | /* Compute the bulk URB size. Some devices set the maximum payload | ||
663 | * size to a value too high for memory-constrained devices. We must | ||
664 | * then transfer the payload accross multiple URBs. To be consistant | ||
665 | * with isochronous mode, allocate maximum UVC_MAX_ISO_PACKETS per bulk | ||
666 | * URB. | ||
667 | */ | ||
668 | psize = le16_to_cpu(ep->desc.wMaxPacketSize) & 0x07ff; | ||
669 | size = video->streaming->ctrl.dwMaxPayloadTransferSize; | ||
670 | video->bulk.max_payload_size = size; | ||
671 | if (size > psize * UVC_MAX_ISO_PACKETS) | ||
672 | size = psize * UVC_MAX_ISO_PACKETS; | ||
673 | |||
674 | pipe = usb_rcvbulkpipe(video->dev->udev, ep->desc.bEndpointAddress); | ||
675 | |||
676 | for (i = 0; i < UVC_URBS; ++i) { | ||
677 | urb = usb_alloc_urb(0, GFP_KERNEL); | ||
678 | if (urb == NULL) { | ||
679 | uvc_uninit_video(video); | ||
680 | return -ENOMEM; | ||
681 | } | ||
682 | |||
683 | video->urb_buffer[i] = usb_buffer_alloc(video->dev->udev, | ||
684 | size, GFP_KERNEL, &urb->transfer_dma); | ||
685 | if (video->urb_buffer[i] == NULL) { | ||
686 | usb_free_urb(urb); | ||
687 | uvc_uninit_video(video); | ||
688 | return -ENOMEM; | ||
689 | } | ||
690 | |||
691 | usb_fill_bulk_urb(urb, video->dev->udev, pipe, | ||
692 | video->urb_buffer[i], size, uvc_video_complete, | ||
693 | video); | ||
694 | urb->transfer_flags = URB_NO_TRANSFER_DMA_MAP; | ||
695 | |||
696 | video->urb[i] = urb; | ||
697 | } | ||
698 | |||
699 | return 0; | ||
700 | } | ||
701 | |||
702 | /* | ||
703 | * Initialize isochronous/bulk URBs and allocate transfer buffers. | ||
704 | */ | ||
705 | static int uvc_init_video(struct uvc_video_device *video) | ||
706 | { | ||
707 | struct usb_interface *intf = video->streaming->intf; | ||
708 | struct usb_host_interface *alts; | ||
709 | struct usb_host_endpoint *ep = NULL; | ||
710 | int intfnum = video->streaming->intfnum; | ||
711 | unsigned int bandwidth, psize, i; | ||
712 | int ret; | ||
713 | |||
714 | video->last_fid = -1; | ||
715 | video->bulk.header_size = 0; | ||
716 | video->bulk.skip_payload = 0; | ||
717 | video->bulk.payload_size = 0; | ||
718 | |||
719 | if (intf->num_altsetting > 1) { | ||
720 | /* Isochronous endpoint, select the alternate setting. */ | ||
721 | bandwidth = video->streaming->ctrl.dwMaxPayloadTransferSize; | ||
722 | |||
723 | if (bandwidth == 0) { | ||
724 | uvc_printk(KERN_WARNING, "device %s requested null " | ||
725 | "bandwidth, defaulting to lowest.\n", | ||
726 | video->vdev->name); | ||
727 | bandwidth = 1; | ||
728 | } | ||
729 | |||
730 | for (i = 0; i < intf->num_altsetting; ++i) { | ||
731 | alts = &intf->altsetting[i]; | ||
732 | ep = uvc_find_endpoint(alts, | ||
733 | video->streaming->header.bEndpointAddress); | ||
734 | if (ep == NULL) | ||
735 | continue; | ||
736 | |||
737 | /* Check if the bandwidth is high enough. */ | ||
738 | psize = le16_to_cpu(ep->desc.wMaxPacketSize); | ||
739 | psize = (psize & 0x07ff) * (1 + ((psize >> 11) & 3)); | ||
740 | if (psize >= bandwidth) | ||
741 | break; | ||
742 | } | ||
743 | |||
744 | if (i >= intf->num_altsetting) | ||
745 | return -EIO; | ||
746 | |||
747 | if ((ret = usb_set_interface(video->dev->udev, intfnum, i)) < 0) | ||
748 | return ret; | ||
749 | |||
750 | ret = uvc_init_video_isoc(video, ep); | ||
751 | } else { | ||
752 | /* Bulk endpoint, proceed to URB initialization. */ | ||
753 | ep = uvc_find_endpoint(&intf->altsetting[0], | ||
754 | video->streaming->header.bEndpointAddress); | ||
755 | if (ep == NULL) | ||
756 | return -EIO; | ||
757 | |||
758 | ret = uvc_init_video_bulk(video, ep); | ||
759 | } | ||
760 | |||
761 | if (ret < 0) | ||
762 | return ret; | ||
763 | |||
764 | /* Submit the URBs. */ | ||
765 | for (i = 0; i < UVC_URBS; ++i) { | ||
766 | if ((ret = usb_submit_urb(video->urb[i], GFP_KERNEL)) < 0) { | ||
767 | uvc_printk(KERN_ERR, "Failed to submit URB %u " | ||
768 | "(%d).\n", i, ret); | ||
769 | uvc_uninit_video(video); | ||
770 | return ret; | ||
771 | } | ||
772 | } | ||
773 | |||
774 | return 0; | ||
775 | } | ||
776 | |||
777 | /* -------------------------------------------------------------------------- | ||
778 | * Suspend/resume | ||
779 | */ | ||
780 | |||
781 | /* | ||
782 | * Stop streaming without disabling the video queue. | ||
783 | * | ||
784 | * To let userspace applications resume without trouble, we must not touch the | ||
785 | * video buffers in any way. We mark the device as frozen to make sure the URB | ||
786 | * completion handler won't try to cancel the queue when we kill the URBs. | ||
787 | */ | ||
788 | int uvc_video_suspend(struct uvc_video_device *video) | ||
789 | { | ||
790 | if (!uvc_queue_streaming(&video->queue)) | ||
791 | return 0; | ||
792 | |||
793 | video->frozen = 1; | ||
794 | uvc_uninit_video(video); | ||
795 | usb_set_interface(video->dev->udev, video->streaming->intfnum, 0); | ||
796 | return 0; | ||
797 | } | ||
798 | |||
799 | /* | ||
800 | * Reconfigure the video interface and restart streaming if it was enable | ||
801 | * before suspend. | ||
802 | * | ||
803 | * If an error occurs, disable the video queue. This will wake all pending | ||
804 | * buffers, making sure userspace applications are notified of the problem | ||
805 | * instead of waiting forever. | ||
806 | */ | ||
807 | int uvc_video_resume(struct uvc_video_device *video) | ||
808 | { | ||
809 | int ret; | ||
810 | |||
811 | video->frozen = 0; | ||
812 | |||
813 | if ((ret = uvc_set_video_ctrl(video, &video->streaming->ctrl, 0)) < 0) { | ||
814 | uvc_queue_enable(&video->queue, 0); | ||
815 | return ret; | ||
816 | } | ||
817 | |||
818 | if (!uvc_queue_streaming(&video->queue)) | ||
819 | return 0; | ||
820 | |||
821 | if ((ret = uvc_init_video(video)) < 0) | ||
822 | uvc_queue_enable(&video->queue, 0); | ||
823 | |||
824 | return ret; | ||
825 | } | ||
826 | |||
827 | /* ------------------------------------------------------------------------ | ||
828 | * Video device | ||
829 | */ | ||
830 | |||
831 | /* | ||
832 | * Initialize the UVC video device by retrieving the default format and | ||
833 | * committing it. | ||
834 | * | ||
835 | * Some cameras (namely the Fuji Finepix) set the format and frame | ||
836 | * indexes to zero. The UVC standard doesn't clearly make this a spec | ||
837 | * violation, so try to silently fix the values if possible. | ||
838 | * | ||
839 | * This function is called before registering the device with V4L. | ||
840 | */ | ||
841 | int uvc_video_init(struct uvc_video_device *video) | ||
842 | { | ||
843 | struct uvc_streaming_control *probe = &video->streaming->ctrl; | ||
844 | struct uvc_format *format = NULL; | ||
845 | struct uvc_frame *frame = NULL; | ||
846 | unsigned int i; | ||
847 | int ret; | ||
848 | |||
849 | if (video->streaming->nformats == 0) { | ||
850 | uvc_printk(KERN_INFO, "No supported video formats found.\n"); | ||
851 | return -EINVAL; | ||
852 | } | ||
853 | |||
854 | /* Alternate setting 0 should be the default, yet the XBox Live Vision | ||
855 | * Cam (and possibly other devices) crash or otherwise misbehave if | ||
856 | * they don't receive a SET_INTERFACE request before any other video | ||
857 | * control request. | ||
858 | */ | ||
859 | usb_set_interface(video->dev->udev, video->streaming->intfnum, 0); | ||
860 | |||
861 | /* Some webcams don't suport GET_DEF request on the probe control. We | ||
862 | * fall back to GET_CUR if GET_DEF fails. | ||
863 | */ | ||
864 | if ((ret = uvc_get_video_ctrl(video, probe, 1, GET_DEF)) < 0 && | ||
865 | (ret = uvc_get_video_ctrl(video, probe, 1, GET_CUR)) < 0) | ||
866 | return ret; | ||
867 | |||
868 | /* Check if the default format descriptor exists. Use the first | ||
869 | * available format otherwise. | ||
870 | */ | ||
871 | for (i = video->streaming->nformats; i > 0; --i) { | ||
872 | format = &video->streaming->format[i-1]; | ||
873 | if (format->index == probe->bFormatIndex) | ||
874 | break; | ||
875 | } | ||
876 | |||
877 | if (format->nframes == 0) { | ||
878 | uvc_printk(KERN_INFO, "No frame descriptor found for the " | ||
879 | "default format.\n"); | ||
880 | return -EINVAL; | ||
881 | } | ||
882 | |||
883 | /* Zero bFrameIndex might be correct. Stream-based formats (including | ||
884 | * MPEG-2 TS and DV) do not support frames but have a dummy frame | ||
885 | * descriptor with bFrameIndex set to zero. If the default frame | ||
886 | * descriptor is not found, use the first avalable frame. | ||
887 | */ | ||
888 | for (i = format->nframes; i > 0; --i) { | ||
889 | frame = &format->frame[i-1]; | ||
890 | if (frame->bFrameIndex == probe->bFrameIndex) | ||
891 | break; | ||
892 | } | ||
893 | |||
894 | /* Commit the default settings. */ | ||
895 | probe->bFormatIndex = format->index; | ||
896 | probe->bFrameIndex = frame->bFrameIndex; | ||
897 | if ((ret = uvc_set_video_ctrl(video, probe, 0)) < 0) | ||
898 | return ret; | ||
899 | |||
900 | video->streaming->cur_format = format; | ||
901 | video->streaming->cur_frame = frame; | ||
902 | atomic_set(&video->active, 0); | ||
903 | |||
904 | /* Select the video decoding function */ | ||
905 | if (video->dev->quirks & UVC_QUIRK_BUILTIN_ISIGHT) | ||
906 | video->decode = uvc_video_decode_isight; | ||
907 | else if (video->streaming->intf->num_altsetting > 1) | ||
908 | video->decode = uvc_video_decode_isoc; | ||
909 | else | ||
910 | video->decode = uvc_video_decode_bulk; | ||
911 | |||
912 | return 0; | ||
913 | } | ||
914 | |||
915 | /* | ||
916 | * Enable or disable the video stream. | ||
917 | */ | ||
918 | int uvc_video_enable(struct uvc_video_device *video, int enable) | ||
919 | { | ||
920 | int ret; | ||
921 | |||
922 | if (!enable) { | ||
923 | uvc_uninit_video(video); | ||
924 | usb_set_interface(video->dev->udev, | ||
925 | video->streaming->intfnum, 0); | ||
926 | uvc_queue_enable(&video->queue, 0); | ||
927 | return 0; | ||
928 | } | ||
929 | |||
930 | if ((ret = uvc_queue_enable(&video->queue, 1)) < 0) | ||
931 | return ret; | ||
932 | |||
933 | return uvc_init_video(video); | ||
934 | } | ||
diff --git a/drivers/media/video/uvc/uvcvideo.h b/drivers/media/video/uvc/uvcvideo.h new file mode 100644 index 000000000000..a995a780db1c --- /dev/null +++ b/drivers/media/video/uvc/uvcvideo.h | |||
@@ -0,0 +1,796 @@ | |||
1 | #ifndef _USB_VIDEO_H_ | ||
2 | #define _USB_VIDEO_H_ | ||
3 | |||
4 | #include <linux/kernel.h> | ||
5 | #include <linux/videodev2.h> | ||
6 | |||
7 | |||
8 | /* | ||
9 | * Dynamic controls | ||
10 | */ | ||
11 | |||
12 | /* Data types for UVC control data */ | ||
13 | #define UVC_CTRL_DATA_TYPE_RAW 0 | ||
14 | #define UVC_CTRL_DATA_TYPE_SIGNED 1 | ||
15 | #define UVC_CTRL_DATA_TYPE_UNSIGNED 2 | ||
16 | #define UVC_CTRL_DATA_TYPE_BOOLEAN 3 | ||
17 | #define UVC_CTRL_DATA_TYPE_ENUM 4 | ||
18 | #define UVC_CTRL_DATA_TYPE_BITMASK 5 | ||
19 | |||
20 | /* Control flags */ | ||
21 | #define UVC_CONTROL_SET_CUR (1 << 0) | ||
22 | #define UVC_CONTROL_GET_CUR (1 << 1) | ||
23 | #define UVC_CONTROL_GET_MIN (1 << 2) | ||
24 | #define UVC_CONTROL_GET_MAX (1 << 3) | ||
25 | #define UVC_CONTROL_GET_RES (1 << 4) | ||
26 | #define UVC_CONTROL_GET_DEF (1 << 5) | ||
27 | /* Control should be saved at suspend and restored at resume. */ | ||
28 | #define UVC_CONTROL_RESTORE (1 << 6) | ||
29 | /* Control can be updated by the camera. */ | ||
30 | #define UVC_CONTROL_AUTO_UPDATE (1 << 7) | ||
31 | |||
32 | #define UVC_CONTROL_GET_RANGE (UVC_CONTROL_GET_CUR | UVC_CONTROL_GET_MIN | \ | ||
33 | UVC_CONTROL_GET_MAX | UVC_CONTROL_GET_RES | \ | ||
34 | UVC_CONTROL_GET_DEF) | ||
35 | |||
36 | struct uvc_xu_control_info { | ||
37 | __u8 entity[16]; | ||
38 | __u8 index; | ||
39 | __u8 selector; | ||
40 | __u16 size; | ||
41 | __u32 flags; | ||
42 | }; | ||
43 | |||
44 | struct uvc_xu_control_mapping { | ||
45 | __u32 id; | ||
46 | __u8 name[32]; | ||
47 | __u8 entity[16]; | ||
48 | __u8 selector; | ||
49 | |||
50 | __u8 size; | ||
51 | __u8 offset; | ||
52 | enum v4l2_ctrl_type v4l2_type; | ||
53 | __u32 data_type; | ||
54 | }; | ||
55 | |||
56 | struct uvc_xu_control { | ||
57 | __u8 unit; | ||
58 | __u8 selector; | ||
59 | __u16 size; | ||
60 | __u8 __user *data; | ||
61 | }; | ||
62 | |||
63 | #define UVCIOC_CTRL_ADD _IOW('U', 1, struct uvc_xu_control_info) | ||
64 | #define UVCIOC_CTRL_MAP _IOWR('U', 2, struct uvc_xu_control_mapping) | ||
65 | #define UVCIOC_CTRL_GET _IOWR('U', 3, struct uvc_xu_control) | ||
66 | #define UVCIOC_CTRL_SET _IOW('U', 4, struct uvc_xu_control) | ||
67 | |||
68 | #ifdef __KERNEL__ | ||
69 | |||
70 | #include <linux/poll.h> | ||
71 | |||
72 | /* -------------------------------------------------------------------------- | ||
73 | * UVC constants | ||
74 | */ | ||
75 | |||
76 | #define SC_UNDEFINED 0x00 | ||
77 | #define SC_VIDEOCONTROL 0x01 | ||
78 | #define SC_VIDEOSTREAMING 0x02 | ||
79 | #define SC_VIDEO_INTERFACE_COLLECTION 0x03 | ||
80 | |||
81 | #define PC_PROTOCOL_UNDEFINED 0x00 | ||
82 | |||
83 | #define CS_UNDEFINED 0x20 | ||
84 | #define CS_DEVICE 0x21 | ||
85 | #define CS_CONFIGURATION 0x22 | ||
86 | #define CS_STRING 0x23 | ||
87 | #define CS_INTERFACE 0x24 | ||
88 | #define CS_ENDPOINT 0x25 | ||
89 | |||
90 | /* VideoControl class specific interface descriptor */ | ||
91 | #define VC_DESCRIPTOR_UNDEFINED 0x00 | ||
92 | #define VC_HEADER 0x01 | ||
93 | #define VC_INPUT_TERMINAL 0x02 | ||
94 | #define VC_OUTPUT_TERMINAL 0x03 | ||
95 | #define VC_SELECTOR_UNIT 0x04 | ||
96 | #define VC_PROCESSING_UNIT 0x05 | ||
97 | #define VC_EXTENSION_UNIT 0x06 | ||
98 | |||
99 | /* VideoStreaming class specific interface descriptor */ | ||
100 | #define VS_UNDEFINED 0x00 | ||
101 | #define VS_INPUT_HEADER 0x01 | ||
102 | #define VS_OUTPUT_HEADER 0x02 | ||
103 | #define VS_STILL_IMAGE_FRAME 0x03 | ||
104 | #define VS_FORMAT_UNCOMPRESSED 0x04 | ||
105 | #define VS_FRAME_UNCOMPRESSED 0x05 | ||
106 | #define VS_FORMAT_MJPEG 0x06 | ||
107 | #define VS_FRAME_MJPEG 0x07 | ||
108 | #define VS_FORMAT_MPEG2TS 0x0a | ||
109 | #define VS_FORMAT_DV 0x0c | ||
110 | #define VS_COLORFORMAT 0x0d | ||
111 | #define VS_FORMAT_FRAME_BASED 0x10 | ||
112 | #define VS_FRAME_FRAME_BASED 0x11 | ||
113 | #define VS_FORMAT_STREAM_BASED 0x12 | ||
114 | |||
115 | /* Endpoint type */ | ||
116 | #define EP_UNDEFINED 0x00 | ||
117 | #define EP_GENERAL 0x01 | ||
118 | #define EP_ENDPOINT 0x02 | ||
119 | #define EP_INTERRUPT 0x03 | ||
120 | |||
121 | /* Request codes */ | ||
122 | #define RC_UNDEFINED 0x00 | ||
123 | #define SET_CUR 0x01 | ||
124 | #define GET_CUR 0x81 | ||
125 | #define GET_MIN 0x82 | ||
126 | #define GET_MAX 0x83 | ||
127 | #define GET_RES 0x84 | ||
128 | #define GET_LEN 0x85 | ||
129 | #define GET_INFO 0x86 | ||
130 | #define GET_DEF 0x87 | ||
131 | |||
132 | /* VideoControl interface controls */ | ||
133 | #define VC_CONTROL_UNDEFINED 0x00 | ||
134 | #define VC_VIDEO_POWER_MODE_CONTROL 0x01 | ||
135 | #define VC_REQUEST_ERROR_CODE_CONTROL 0x02 | ||
136 | |||
137 | /* Terminal controls */ | ||
138 | #define TE_CONTROL_UNDEFINED 0x00 | ||
139 | |||
140 | /* Selector Unit controls */ | ||
141 | #define SU_CONTROL_UNDEFINED 0x00 | ||
142 | #define SU_INPUT_SELECT_CONTROL 0x01 | ||
143 | |||
144 | /* Camera Terminal controls */ | ||
145 | #define CT_CONTROL_UNDEFINED 0x00 | ||
146 | #define CT_SCANNING_MODE_CONTROL 0x01 | ||
147 | #define CT_AE_MODE_CONTROL 0x02 | ||
148 | #define CT_AE_PRIORITY_CONTROL 0x03 | ||
149 | #define CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x04 | ||
150 | #define CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x05 | ||
151 | #define CT_FOCUS_ABSOLUTE_CONTROL 0x06 | ||
152 | #define CT_FOCUS_RELATIVE_CONTROL 0x07 | ||
153 | #define CT_FOCUS_AUTO_CONTROL 0x08 | ||
154 | #define CT_IRIS_ABSOLUTE_CONTROL 0x09 | ||
155 | #define CT_IRIS_RELATIVE_CONTROL 0x0a | ||
156 | #define CT_ZOOM_ABSOLUTE_CONTROL 0x0b | ||
157 | #define CT_ZOOM_RELATIVE_CONTROL 0x0c | ||
158 | #define CT_PANTILT_ABSOLUTE_CONTROL 0x0d | ||
159 | #define CT_PANTILT_RELATIVE_CONTROL 0x0e | ||
160 | #define CT_ROLL_ABSOLUTE_CONTROL 0x0f | ||
161 | #define CT_ROLL_RELATIVE_CONTROL 0x10 | ||
162 | #define CT_PRIVACY_CONTROL 0x11 | ||
163 | |||
164 | /* Processing Unit controls */ | ||
165 | #define PU_CONTROL_UNDEFINED 0x00 | ||
166 | #define PU_BACKLIGHT_COMPENSATION_CONTROL 0x01 | ||
167 | #define PU_BRIGHTNESS_CONTROL 0x02 | ||
168 | #define PU_CONTRAST_CONTROL 0x03 | ||
169 | #define PU_GAIN_CONTROL 0x04 | ||
170 | #define PU_POWER_LINE_FREQUENCY_CONTROL 0x05 | ||
171 | #define PU_HUE_CONTROL 0x06 | ||
172 | #define PU_SATURATION_CONTROL 0x07 | ||
173 | #define PU_SHARPNESS_CONTROL 0x08 | ||
174 | #define PU_GAMMA_CONTROL 0x09 | ||
175 | #define PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x0a | ||
176 | #define PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x0b | ||
177 | #define PU_WHITE_BALANCE_COMPONENT_CONTROL 0x0c | ||
178 | #define PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x0d | ||
179 | #define PU_DIGITAL_MULTIPLIER_CONTROL 0x0e | ||
180 | #define PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x0f | ||
181 | #define PU_HUE_AUTO_CONTROL 0x10 | ||
182 | #define PU_ANALOG_VIDEO_STANDARD_CONTROL 0x11 | ||
183 | #define PU_ANALOG_LOCK_STATUS_CONTROL 0x12 | ||
184 | |||
185 | #define LXU_MOTOR_PANTILT_RELATIVE_CONTROL 0x01 | ||
186 | #define LXU_MOTOR_PANTILT_RESET_CONTROL 0x02 | ||
187 | #define LXU_MOTOR_FOCUS_MOTOR_CONTROL 0x03 | ||
188 | |||
189 | /* VideoStreaming interface controls */ | ||
190 | #define VS_CONTROL_UNDEFINED 0x00 | ||
191 | #define VS_PROBE_CONTROL 0x01 | ||
192 | #define VS_COMMIT_CONTROL 0x02 | ||
193 | #define VS_STILL_PROBE_CONTROL 0x03 | ||
194 | #define VS_STILL_COMMIT_CONTROL 0x04 | ||
195 | #define VS_STILL_IMAGE_TRIGGER_CONTROL 0x05 | ||
196 | #define VS_STREAM_ERROR_CODE_CONTROL 0x06 | ||
197 | #define VS_GENERATE_KEY_FRAME_CONTROL 0x07 | ||
198 | #define VS_UPDATE_FRAME_SEGMENT_CONTROL 0x08 | ||
199 | #define VS_SYNC_DELAY_CONTROL 0x09 | ||
200 | |||
201 | #define TT_VENDOR_SPECIFIC 0x0100 | ||
202 | #define TT_STREAMING 0x0101 | ||
203 | |||
204 | /* Input Terminal types */ | ||
205 | #define ITT_VENDOR_SPECIFIC 0x0200 | ||
206 | #define ITT_CAMERA 0x0201 | ||
207 | #define ITT_MEDIA_TRANSPORT_INPUT 0x0202 | ||
208 | |||
209 | /* Output Terminal types */ | ||
210 | #define OTT_VENDOR_SPECIFIC 0x0300 | ||
211 | #define OTT_DISPLAY 0x0301 | ||
212 | #define OTT_MEDIA_TRANSPORT_OUTPUT 0x0302 | ||
213 | |||
214 | /* External Terminal types */ | ||
215 | #define EXTERNAL_VENDOR_SPECIFIC 0x0400 | ||
216 | #define COMPOSITE_CONNECTOR 0x0401 | ||
217 | #define SVIDEO_CONNECTOR 0x0402 | ||
218 | #define COMPONENT_CONNECTOR 0x0403 | ||
219 | |||
220 | #define UVC_TERM_INPUT 0x0000 | ||
221 | #define UVC_TERM_OUTPUT 0x8000 | ||
222 | |||
223 | #define UVC_ENTITY_TYPE(entity) ((entity)->type & 0x7fff) | ||
224 | #define UVC_ENTITY_IS_UNIT(entity) (((entity)->type & 0xff00) == 0) | ||
225 | #define UVC_ENTITY_IS_TERM(entity) (((entity)->type & 0xff00) != 0) | ||
226 | #define UVC_ENTITY_IS_ITERM(entity) \ | ||
227 | (((entity)->type & 0x8000) == UVC_TERM_INPUT) | ||
228 | #define UVC_ENTITY_IS_OTERM(entity) \ | ||
229 | (((entity)->type & 0x8000) == UVC_TERM_OUTPUT) | ||
230 | |||
231 | #define UVC_STATUS_TYPE_CONTROL 1 | ||
232 | #define UVC_STATUS_TYPE_STREAMING 2 | ||
233 | |||
234 | /* ------------------------------------------------------------------------ | ||
235 | * GUIDs | ||
236 | */ | ||
237 | #define UVC_GUID_UVC_CAMERA \ | ||
238 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ | ||
239 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} | ||
240 | #define UVC_GUID_UVC_OUTPUT \ | ||
241 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ | ||
242 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02} | ||
243 | #define UVC_GUID_UVC_MEDIA_TRANSPORT_INPUT \ | ||
244 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ | ||
245 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03} | ||
246 | #define UVC_GUID_UVC_PROCESSING \ | ||
247 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ | ||
248 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01} | ||
249 | #define UVC_GUID_UVC_SELECTOR \ | ||
250 | {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ | ||
251 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02} | ||
252 | |||
253 | #define UVC_GUID_LOGITECH_DEV_INFO \ | ||
254 | {0x82, 0x06, 0x61, 0x63, 0x70, 0x50, 0xab, 0x49, \ | ||
255 | 0xb8, 0xcc, 0xb3, 0x85, 0x5e, 0x8d, 0x22, 0x1e} | ||
256 | #define UVC_GUID_LOGITECH_USER_HW \ | ||
257 | {0x82, 0x06, 0x61, 0x63, 0x70, 0x50, 0xab, 0x49, \ | ||
258 | 0xb8, 0xcc, 0xb3, 0x85, 0x5e, 0x8d, 0x22, 0x1f} | ||
259 | #define UVC_GUID_LOGITECH_VIDEO \ | ||
260 | {0x82, 0x06, 0x61, 0x63, 0x70, 0x50, 0xab, 0x49, \ | ||
261 | 0xb8, 0xcc, 0xb3, 0x85, 0x5e, 0x8d, 0x22, 0x50} | ||
262 | #define UVC_GUID_LOGITECH_MOTOR \ | ||
263 | {0x82, 0x06, 0x61, 0x63, 0x70, 0x50, 0xab, 0x49, \ | ||
264 | 0xb8, 0xcc, 0xb3, 0x85, 0x5e, 0x8d, 0x22, 0x56} | ||
265 | |||
266 | #define UVC_GUID_FORMAT_MJPEG \ | ||
267 | { 'M', 'J', 'P', 'G', 0x00, 0x00, 0x10, 0x00, \ | ||
268 | 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} | ||
269 | #define UVC_GUID_FORMAT_YUY2 \ | ||
270 | { 'Y', 'U', 'Y', '2', 0x00, 0x00, 0x10, 0x00, \ | ||
271 | 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} | ||
272 | #define UVC_GUID_FORMAT_NV12 \ | ||
273 | { 'N', 'V', '1', '2', 0x00, 0x00, 0x10, 0x00, \ | ||
274 | 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} | ||
275 | #define UVC_GUID_FORMAT_YV12 \ | ||
276 | { 'Y', 'V', '1', '2', 0x00, 0x00, 0x10, 0x00, \ | ||
277 | 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} | ||
278 | #define UVC_GUID_FORMAT_I420 \ | ||
279 | { 'I', '4', '2', '0', 0x00, 0x00, 0x10, 0x00, \ | ||
280 | 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} | ||
281 | #define UVC_GUID_FORMAT_UYVY \ | ||
282 | { 'U', 'Y', 'V', 'Y', 0x00, 0x00, 0x10, 0x00, \ | ||
283 | 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} | ||
284 | #define UVC_GUID_FORMAT_Y800 \ | ||
285 | { 'Y', '8', '0', '0', 0x00, 0x00, 0x10, 0x00, \ | ||
286 | 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} | ||
287 | #define UVC_GUID_FORMAT_BY8 \ | ||
288 | { 'B', 'Y', '8', ' ', 0x00, 0x00, 0x10, 0x00, \ | ||
289 | 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} | ||
290 | |||
291 | |||
292 | /* ------------------------------------------------------------------------ | ||
293 | * Driver specific constants. | ||
294 | */ | ||
295 | |||
296 | #define DRIVER_VERSION_NUMBER KERNEL_VERSION(0, 1, 0) | ||
297 | |||
298 | /* Number of isochronous URBs. */ | ||
299 | #define UVC_URBS 5 | ||
300 | /* Maximum number of packets per isochronous URB. */ | ||
301 | #define UVC_MAX_ISO_PACKETS 40 | ||
302 | /* Maximum frame size in bytes, for sanity checking. */ | ||
303 | #define UVC_MAX_FRAME_SIZE (16*1024*1024) | ||
304 | /* Maximum number of video buffers. */ | ||
305 | #define UVC_MAX_VIDEO_BUFFERS 32 | ||
306 | |||
307 | #define UVC_CTRL_CONTROL_TIMEOUT 300 | ||
308 | #define UVC_CTRL_STREAMING_TIMEOUT 1000 | ||
309 | |||
310 | /* Devices quirks */ | ||
311 | #define UVC_QUIRK_STATUS_INTERVAL 0x00000001 | ||
312 | #define UVC_QUIRK_PROBE_MINMAX 0x00000002 | ||
313 | #define UVC_QUIRK_PROBE_EXTRAFIELDS 0x00000004 | ||
314 | #define UVC_QUIRK_BUILTIN_ISIGHT 0x00000008 | ||
315 | #define UVC_QUIRK_STREAM_NO_FID 0x00000010 | ||
316 | #define UVC_QUIRK_IGNORE_SELECTOR_UNIT 0x00000020 | ||
317 | |||
318 | /* Format flags */ | ||
319 | #define UVC_FMT_FLAG_COMPRESSED 0x00000001 | ||
320 | #define UVC_FMT_FLAG_STREAM 0x00000002 | ||
321 | |||
322 | /* ------------------------------------------------------------------------ | ||
323 | * Structures. | ||
324 | */ | ||
325 | |||
326 | struct uvc_device; | ||
327 | |||
328 | /* TODO: Put the most frequently accessed fields at the beginning of | ||
329 | * structures to maximize cache efficiency. | ||
330 | */ | ||
331 | struct uvc_streaming_control { | ||
332 | __u16 bmHint; | ||
333 | __u8 bFormatIndex; | ||
334 | __u8 bFrameIndex; | ||
335 | __u32 dwFrameInterval; | ||
336 | __u16 wKeyFrameRate; | ||
337 | __u16 wPFrameRate; | ||
338 | __u16 wCompQuality; | ||
339 | __u16 wCompWindowSize; | ||
340 | __u16 wDelay; | ||
341 | __u32 dwMaxVideoFrameSize; | ||
342 | __u32 dwMaxPayloadTransferSize; | ||
343 | __u32 dwClockFrequency; | ||
344 | __u8 bmFramingInfo; | ||
345 | __u8 bPreferedVersion; | ||
346 | __u8 bMinVersion; | ||
347 | __u8 bMaxVersion; | ||
348 | }; | ||
349 | |||
350 | struct uvc_menu_info { | ||
351 | __u32 value; | ||
352 | __u8 name[32]; | ||
353 | }; | ||
354 | |||
355 | struct uvc_control_info { | ||
356 | struct list_head list; | ||
357 | struct list_head mappings; | ||
358 | |||
359 | __u8 entity[16]; | ||
360 | __u8 index; | ||
361 | __u8 selector; | ||
362 | |||
363 | __u16 size; | ||
364 | __u32 flags; | ||
365 | }; | ||
366 | |||
367 | struct uvc_control_mapping { | ||
368 | struct list_head list; | ||
369 | |||
370 | struct uvc_control_info *ctrl; | ||
371 | |||
372 | __u32 id; | ||
373 | __u8 name[32]; | ||
374 | __u8 entity[16]; | ||
375 | __u8 selector; | ||
376 | |||
377 | __u8 size; | ||
378 | __u8 offset; | ||
379 | enum v4l2_ctrl_type v4l2_type; | ||
380 | __u32 data_type; | ||
381 | |||
382 | struct uvc_menu_info *menu_info; | ||
383 | __u32 menu_count; | ||
384 | }; | ||
385 | |||
386 | struct uvc_control { | ||
387 | struct uvc_entity *entity; | ||
388 | struct uvc_control_info *info; | ||
389 | |||
390 | __u8 index; /* Used to match the uvc_control entry with a | ||
391 | uvc_control_info. */ | ||
392 | __u8 dirty : 1, | ||
393 | loaded : 1, | ||
394 | modified : 1; | ||
395 | |||
396 | __u8 *data; | ||
397 | }; | ||
398 | |||
399 | struct uvc_format_desc { | ||
400 | char *name; | ||
401 | __u8 guid[16]; | ||
402 | __u32 fcc; | ||
403 | }; | ||
404 | |||
405 | /* The term 'entity' refers to both UVC units and UVC terminals. | ||
406 | * | ||
407 | * The type field is either the terminal type (wTerminalType in the terminal | ||
408 | * descriptor), or the unit type (bDescriptorSubtype in the unit descriptor). | ||
409 | * As the bDescriptorSubtype field is one byte long, the type value will | ||
410 | * always have a null MSB for units. All terminal types defined by the UVC | ||
411 | * specification have a non-null MSB, so it is safe to use the MSB to | ||
412 | * differentiate between units and terminals as long as the descriptor parsing | ||
413 | * code makes sure terminal types have a non-null MSB. | ||
414 | * | ||
415 | * For terminals, the type's most significant bit stores the terminal | ||
416 | * direction (either UVC_TERM_INPUT or UVC_TERM_OUTPUT). The type field should | ||
417 | * always be accessed with the UVC_ENTITY_* macros and never directly. | ||
418 | */ | ||
419 | |||
420 | struct uvc_entity { | ||
421 | struct list_head list; /* Entity as part of a UVC device. */ | ||
422 | struct list_head chain; /* Entity as part of a video device | ||
423 | * chain. */ | ||
424 | __u8 id; | ||
425 | __u16 type; | ||
426 | char name[64]; | ||
427 | |||
428 | union { | ||
429 | struct { | ||
430 | __u16 wObjectiveFocalLengthMin; | ||
431 | __u16 wObjectiveFocalLengthMax; | ||
432 | __u16 wOcularFocalLength; | ||
433 | __u8 bControlSize; | ||
434 | __u8 *bmControls; | ||
435 | } camera; | ||
436 | |||
437 | struct { | ||
438 | __u8 bControlSize; | ||
439 | __u8 *bmControls; | ||
440 | __u8 bTransportModeSize; | ||
441 | __u8 *bmTransportModes; | ||
442 | } media; | ||
443 | |||
444 | struct { | ||
445 | __u8 bSourceID; | ||
446 | } output; | ||
447 | |||
448 | struct { | ||
449 | __u8 bSourceID; | ||
450 | __u16 wMaxMultiplier; | ||
451 | __u8 bControlSize; | ||
452 | __u8 *bmControls; | ||
453 | __u8 bmVideoStandards; | ||
454 | } processing; | ||
455 | |||
456 | struct { | ||
457 | __u8 bNrInPins; | ||
458 | __u8 *baSourceID; | ||
459 | } selector; | ||
460 | |||
461 | struct { | ||
462 | __u8 guidExtensionCode[16]; | ||
463 | __u8 bNumControls; | ||
464 | __u8 bNrInPins; | ||
465 | __u8 *baSourceID; | ||
466 | __u8 bControlSize; | ||
467 | __u8 *bmControls; | ||
468 | __u8 *bmControlsType; | ||
469 | } extension; | ||
470 | }; | ||
471 | |||
472 | unsigned int ncontrols; | ||
473 | struct uvc_control *controls; | ||
474 | }; | ||
475 | |||
476 | struct uvc_frame { | ||
477 | __u8 bFrameIndex; | ||
478 | __u8 bmCapabilities; | ||
479 | __u16 wWidth; | ||
480 | __u16 wHeight; | ||
481 | __u32 dwMinBitRate; | ||
482 | __u32 dwMaxBitRate; | ||
483 | __u32 dwMaxVideoFrameBufferSize; | ||
484 | __u8 bFrameIntervalType; | ||
485 | __u32 dwDefaultFrameInterval; | ||
486 | __u32 *dwFrameInterval; | ||
487 | }; | ||
488 | |||
489 | struct uvc_format { | ||
490 | __u8 type; | ||
491 | __u8 index; | ||
492 | __u8 bpp; | ||
493 | __u8 colorspace; | ||
494 | __u32 fcc; | ||
495 | __u32 flags; | ||
496 | |||
497 | char name[32]; | ||
498 | |||
499 | unsigned int nframes; | ||
500 | struct uvc_frame *frame; | ||
501 | }; | ||
502 | |||
503 | struct uvc_streaming_header { | ||
504 | __u8 bNumFormats; | ||
505 | __u8 bEndpointAddress; | ||
506 | __u8 bTerminalLink; | ||
507 | __u8 bControlSize; | ||
508 | __u8 *bmaControls; | ||
509 | /* The following fields are used by input headers only. */ | ||
510 | __u8 bmInfo; | ||
511 | __u8 bStillCaptureMethod; | ||
512 | __u8 bTriggerSupport; | ||
513 | __u8 bTriggerUsage; | ||
514 | }; | ||
515 | |||
516 | struct uvc_streaming { | ||
517 | struct list_head list; | ||
518 | |||
519 | struct usb_interface *intf; | ||
520 | int intfnum; | ||
521 | __u16 maxpsize; | ||
522 | |||
523 | struct uvc_streaming_header header; | ||
524 | |||
525 | unsigned int nformats; | ||
526 | struct uvc_format *format; | ||
527 | |||
528 | struct uvc_streaming_control ctrl; | ||
529 | struct uvc_format *cur_format; | ||
530 | struct uvc_frame *cur_frame; | ||
531 | |||
532 | struct mutex mutex; | ||
533 | }; | ||
534 | |||
535 | enum uvc_buffer_state { | ||
536 | UVC_BUF_STATE_IDLE = 0, | ||
537 | UVC_BUF_STATE_QUEUED = 1, | ||
538 | UVC_BUF_STATE_ACTIVE = 2, | ||
539 | UVC_BUF_STATE_DONE = 3, | ||
540 | UVC_BUF_STATE_ERROR = 4, | ||
541 | }; | ||
542 | |||
543 | struct uvc_buffer { | ||
544 | unsigned long vma_use_count; | ||
545 | struct list_head stream; | ||
546 | |||
547 | /* Touched by interrupt handler. */ | ||
548 | struct v4l2_buffer buf; | ||
549 | struct list_head queue; | ||
550 | wait_queue_head_t wait; | ||
551 | enum uvc_buffer_state state; | ||
552 | }; | ||
553 | |||
554 | #define UVC_QUEUE_STREAMING (1 << 0) | ||
555 | #define UVC_QUEUE_DISCONNECTED (1 << 1) | ||
556 | #define UVC_QUEUE_DROP_INCOMPLETE (1 << 2) | ||
557 | |||
558 | struct uvc_video_queue { | ||
559 | void *mem; | ||
560 | unsigned int flags; | ||
561 | __u32 sequence; | ||
562 | |||
563 | unsigned int count; | ||
564 | unsigned int buf_size; | ||
565 | struct uvc_buffer buffer[UVC_MAX_VIDEO_BUFFERS]; | ||
566 | struct mutex mutex; /* protects buffers and mainqueue */ | ||
567 | spinlock_t irqlock; /* protects irqqueue */ | ||
568 | |||
569 | struct list_head mainqueue; | ||
570 | struct list_head irqqueue; | ||
571 | }; | ||
572 | |||
573 | struct uvc_video_device { | ||
574 | struct uvc_device *dev; | ||
575 | struct video_device *vdev; | ||
576 | atomic_t active; | ||
577 | unsigned int frozen : 1; | ||
578 | |||
579 | struct list_head iterms; | ||
580 | struct uvc_entity *oterm; | ||
581 | struct uvc_entity *processing; | ||
582 | struct uvc_entity *selector; | ||
583 | struct list_head extensions; | ||
584 | struct mutex ctrl_mutex; | ||
585 | |||
586 | struct uvc_video_queue queue; | ||
587 | |||
588 | /* Video streaming object, must always be non-NULL. */ | ||
589 | struct uvc_streaming *streaming; | ||
590 | |||
591 | void (*decode) (struct urb *urb, struct uvc_video_device *video, | ||
592 | struct uvc_buffer *buf); | ||
593 | |||
594 | /* Context data used by the bulk completion handler. */ | ||
595 | struct { | ||
596 | __u8 header[256]; | ||
597 | unsigned int header_size; | ||
598 | int skip_payload; | ||
599 | __u32 payload_size; | ||
600 | __u32 max_payload_size; | ||
601 | } bulk; | ||
602 | |||
603 | struct urb *urb[UVC_URBS]; | ||
604 | char *urb_buffer[UVC_URBS]; | ||
605 | |||
606 | __u8 last_fid; | ||
607 | }; | ||
608 | |||
609 | enum uvc_device_state { | ||
610 | UVC_DEV_DISCONNECTED = 1, | ||
611 | }; | ||
612 | |||
613 | struct uvc_device { | ||
614 | struct usb_device *udev; | ||
615 | struct usb_interface *intf; | ||
616 | __u32 quirks; | ||
617 | int intfnum; | ||
618 | char name[32]; | ||
619 | |||
620 | enum uvc_device_state state; | ||
621 | struct kref kref; | ||
622 | struct list_head list; | ||
623 | |||
624 | /* Video control interface */ | ||
625 | __u16 uvc_version; | ||
626 | __u32 clock_frequency; | ||
627 | |||
628 | struct list_head entities; | ||
629 | |||
630 | struct uvc_video_device video; | ||
631 | |||
632 | /* Status Interrupt Endpoint */ | ||
633 | struct usb_host_endpoint *int_ep; | ||
634 | struct urb *int_urb; | ||
635 | __u8 status[16]; | ||
636 | struct input_dev *input; | ||
637 | |||
638 | /* Video Streaming interfaces */ | ||
639 | struct list_head streaming; | ||
640 | }; | ||
641 | |||
642 | enum uvc_handle_state { | ||
643 | UVC_HANDLE_PASSIVE = 0, | ||
644 | UVC_HANDLE_ACTIVE = 1, | ||
645 | }; | ||
646 | |||
647 | struct uvc_fh { | ||
648 | struct uvc_video_device *device; | ||
649 | enum uvc_handle_state state; | ||
650 | }; | ||
651 | |||
652 | struct uvc_driver { | ||
653 | struct usb_driver driver; | ||
654 | |||
655 | struct mutex open_mutex; /* protects from open/disconnect race */ | ||
656 | |||
657 | struct list_head devices; /* struct uvc_device list */ | ||
658 | struct list_head controls; /* struct uvc_control_info list */ | ||
659 | struct mutex ctrl_mutex; /* protects controls and devices | ||
660 | lists */ | ||
661 | }; | ||
662 | |||
663 | /* ------------------------------------------------------------------------ | ||
664 | * Debugging, printing and logging | ||
665 | */ | ||
666 | |||
667 | #define UVC_TRACE_PROBE (1 << 0) | ||
668 | #define UVC_TRACE_DESCR (1 << 1) | ||
669 | #define UVC_TRACE_CONTROL (1 << 2) | ||
670 | #define UVC_TRACE_FORMAT (1 << 3) | ||
671 | #define UVC_TRACE_CAPTURE (1 << 4) | ||
672 | #define UVC_TRACE_CALLS (1 << 5) | ||
673 | #define UVC_TRACE_IOCTL (1 << 6) | ||
674 | #define UVC_TRACE_FRAME (1 << 7) | ||
675 | #define UVC_TRACE_SUSPEND (1 << 8) | ||
676 | #define UVC_TRACE_STATUS (1 << 9) | ||
677 | |||
678 | extern unsigned int uvc_trace_param; | ||
679 | |||
680 | #define uvc_trace(flag, msg...) \ | ||
681 | do { \ | ||
682 | if (uvc_trace_param & flag) \ | ||
683 | printk(KERN_DEBUG "uvcvideo: " msg); \ | ||
684 | } while (0) | ||
685 | |||
686 | #define uvc_printk(level, msg...) \ | ||
687 | printk(level "uvcvideo: " msg) | ||
688 | |||
689 | #define UVC_GUID_FORMAT "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-" \ | ||
690 | "%02x%02x%02x%02x%02x%02x" | ||
691 | #define UVC_GUID_ARGS(guid) \ | ||
692 | (guid)[3], (guid)[2], (guid)[1], (guid)[0], \ | ||
693 | (guid)[5], (guid)[4], \ | ||
694 | (guid)[7], (guid)[6], \ | ||
695 | (guid)[8], (guid)[9], \ | ||
696 | (guid)[10], (guid)[11], (guid)[12], \ | ||
697 | (guid)[13], (guid)[14], (guid)[15] | ||
698 | |||
699 | /* -------------------------------------------------------------------------- | ||
700 | * Internal functions. | ||
701 | */ | ||
702 | |||
703 | /* Core driver */ | ||
704 | extern struct uvc_driver uvc_driver; | ||
705 | extern void uvc_delete(struct kref *kref); | ||
706 | |||
707 | /* Video buffers queue management. */ | ||
708 | extern void uvc_queue_init(struct uvc_video_queue *queue); | ||
709 | extern int uvc_alloc_buffers(struct uvc_video_queue *queue, | ||
710 | unsigned int nbuffers, unsigned int buflength); | ||
711 | extern int uvc_free_buffers(struct uvc_video_queue *queue); | ||
712 | extern int uvc_query_buffer(struct uvc_video_queue *queue, | ||
713 | struct v4l2_buffer *v4l2_buf); | ||
714 | extern int uvc_queue_buffer(struct uvc_video_queue *queue, | ||
715 | struct v4l2_buffer *v4l2_buf); | ||
716 | extern int uvc_dequeue_buffer(struct uvc_video_queue *queue, | ||
717 | struct v4l2_buffer *v4l2_buf, int nonblocking); | ||
718 | extern int uvc_queue_enable(struct uvc_video_queue *queue, int enable); | ||
719 | extern void uvc_queue_cancel(struct uvc_video_queue *queue, int disconnect); | ||
720 | extern struct uvc_buffer *uvc_queue_next_buffer(struct uvc_video_queue *queue, | ||
721 | struct uvc_buffer *buf); | ||
722 | extern unsigned int uvc_queue_poll(struct uvc_video_queue *queue, | ||
723 | struct file *file, poll_table *wait); | ||
724 | static inline int uvc_queue_streaming(struct uvc_video_queue *queue) | ||
725 | { | ||
726 | return queue->flags & UVC_QUEUE_STREAMING; | ||
727 | } | ||
728 | |||
729 | /* V4L2 interface */ | ||
730 | extern struct file_operations uvc_fops; | ||
731 | |||
732 | /* Video */ | ||
733 | extern int uvc_video_init(struct uvc_video_device *video); | ||
734 | extern int uvc_video_suspend(struct uvc_video_device *video); | ||
735 | extern int uvc_video_resume(struct uvc_video_device *video); | ||
736 | extern int uvc_video_enable(struct uvc_video_device *video, int enable); | ||
737 | extern int uvc_probe_video(struct uvc_video_device *video, | ||
738 | struct uvc_streaming_control *probe); | ||
739 | extern int uvc_query_ctrl(struct uvc_device *dev, __u8 query, __u8 unit, | ||
740 | __u8 intfnum, __u8 cs, void *data, __u16 size); | ||
741 | extern int uvc_set_video_ctrl(struct uvc_video_device *video, | ||
742 | struct uvc_streaming_control *ctrl, int probe); | ||
743 | |||
744 | /* Status */ | ||
745 | extern int uvc_status_init(struct uvc_device *dev); | ||
746 | extern void uvc_status_cleanup(struct uvc_device *dev); | ||
747 | extern int uvc_status_suspend(struct uvc_device *dev); | ||
748 | extern int uvc_status_resume(struct uvc_device *dev); | ||
749 | |||
750 | /* Controls */ | ||
751 | extern struct uvc_control *uvc_find_control(struct uvc_video_device *video, | ||
752 | __u32 v4l2_id, struct uvc_control_mapping **mapping); | ||
753 | extern int uvc_query_v4l2_ctrl(struct uvc_video_device *video, | ||
754 | struct v4l2_queryctrl *v4l2_ctrl); | ||
755 | |||
756 | extern int uvc_ctrl_add_info(struct uvc_control_info *info); | ||
757 | extern int uvc_ctrl_add_mapping(struct uvc_control_mapping *mapping); | ||
758 | extern int uvc_ctrl_init_device(struct uvc_device *dev); | ||
759 | extern void uvc_ctrl_cleanup_device(struct uvc_device *dev); | ||
760 | extern int uvc_ctrl_resume_device(struct uvc_device *dev); | ||
761 | extern void uvc_ctrl_init(void); | ||
762 | |||
763 | extern int uvc_ctrl_begin(struct uvc_video_device *video); | ||
764 | extern int __uvc_ctrl_commit(struct uvc_video_device *video, int rollback); | ||
765 | static inline int uvc_ctrl_commit(struct uvc_video_device *video) | ||
766 | { | ||
767 | return __uvc_ctrl_commit(video, 0); | ||
768 | } | ||
769 | static inline int uvc_ctrl_rollback(struct uvc_video_device *video) | ||
770 | { | ||
771 | return __uvc_ctrl_commit(video, 1); | ||
772 | } | ||
773 | |||
774 | extern int uvc_ctrl_get(struct uvc_video_device *video, | ||
775 | struct v4l2_ext_control *xctrl); | ||
776 | extern int uvc_ctrl_set(struct uvc_video_device *video, | ||
777 | struct v4l2_ext_control *xctrl); | ||
778 | |||
779 | extern int uvc_xu_ctrl_query(struct uvc_video_device *video, | ||
780 | struct uvc_xu_control *ctrl, int set); | ||
781 | |||
782 | /* Utility functions */ | ||
783 | extern void uvc_simplify_fraction(uint32_t *numerator, uint32_t *denominator, | ||
784 | unsigned int n_terms, unsigned int threshold); | ||
785 | extern uint32_t uvc_fraction_to_interval(uint32_t numerator, | ||
786 | uint32_t denominator); | ||
787 | extern struct usb_host_endpoint *uvc_find_endpoint( | ||
788 | struct usb_host_interface *alts, __u8 epaddr); | ||
789 | |||
790 | /* Quirks support */ | ||
791 | void uvc_video_decode_isight(struct urb *urb, struct uvc_video_device *video, | ||
792 | struct uvc_buffer *buf); | ||
793 | |||
794 | #endif /* __KERNEL__ */ | ||
795 | |||
796 | #endif | ||
diff --git a/drivers/media/video/videodev.c b/drivers/media/video/videodev.c index 31e8af0ba278..67a661cf5219 100644 --- a/drivers/media/video/videodev.c +++ b/drivers/media/video/videodev.c | |||
@@ -51,12 +51,51 @@ | |||
51 | #define VIDEO_NUM_DEVICES 256 | 51 | #define VIDEO_NUM_DEVICES 256 |
52 | #define VIDEO_NAME "video4linux" | 52 | #define VIDEO_NAME "video4linux" |
53 | 53 | ||
54 | struct std_descr { | ||
55 | v4l2_std_id std; | ||
56 | const char *descr; | ||
57 | }; | ||
58 | |||
59 | static const struct std_descr standards[] = { | ||
60 | { V4L2_STD_NTSC, "NTSC" }, | ||
61 | { V4L2_STD_NTSC_M, "NTSC-M" }, | ||
62 | { V4L2_STD_NTSC_M_JP, "NTSC-M-JP" }, | ||
63 | { V4L2_STD_NTSC_M_KR, "NTSC-M-KR" }, | ||
64 | { V4L2_STD_NTSC_443, "NTSC-443" }, | ||
65 | { V4L2_STD_PAL, "PAL" }, | ||
66 | { V4L2_STD_PAL_BG, "PAL-BG" }, | ||
67 | { V4L2_STD_PAL_B, "PAL-B" }, | ||
68 | { V4L2_STD_PAL_B1, "PAL-B1" }, | ||
69 | { V4L2_STD_PAL_G, "PAL-G" }, | ||
70 | { V4L2_STD_PAL_H, "PAL-H" }, | ||
71 | { V4L2_STD_PAL_I, "PAL-I" }, | ||
72 | { V4L2_STD_PAL_DK, "PAL-DK" }, | ||
73 | { V4L2_STD_PAL_D, "PAL-D" }, | ||
74 | { V4L2_STD_PAL_D1, "PAL-D1" }, | ||
75 | { V4L2_STD_PAL_K, "PAL-K" }, | ||
76 | { V4L2_STD_PAL_M, "PAL-M" }, | ||
77 | { V4L2_STD_PAL_N, "PAL-N" }, | ||
78 | { V4L2_STD_PAL_Nc, "PAL-Nc" }, | ||
79 | { V4L2_STD_PAL_60, "PAL-60" }, | ||
80 | { V4L2_STD_SECAM, "SECAM" }, | ||
81 | { V4L2_STD_SECAM_B, "SECAM-B" }, | ||
82 | { V4L2_STD_SECAM_G, "SECAM-G" }, | ||
83 | { V4L2_STD_SECAM_H, "SECAM-H" }, | ||
84 | { V4L2_STD_SECAM_DK, "SECAM-DK" }, | ||
85 | { V4L2_STD_SECAM_D, "SECAM-D" }, | ||
86 | { V4L2_STD_SECAM_K, "SECAM-K" }, | ||
87 | { V4L2_STD_SECAM_K1, "SECAM-K1" }, | ||
88 | { V4L2_STD_SECAM_L, "SECAM-L" }, | ||
89 | { V4L2_STD_SECAM_LC, "SECAM-Lc" }, | ||
90 | { 0, "Unknown" } | ||
91 | }; | ||
92 | |||
54 | /* video4linux standard ID conversion to standard name | 93 | /* video4linux standard ID conversion to standard name |
55 | */ | 94 | */ |
56 | char *v4l2_norm_to_name(v4l2_std_id id) | 95 | const char *v4l2_norm_to_name(v4l2_std_id id) |
57 | { | 96 | { |
58 | char *name; | ||
59 | u32 myid = id; | 97 | u32 myid = id; |
98 | int i; | ||
60 | 99 | ||
61 | /* HACK: ppc32 architecture doesn't have __ucmpdi2 function to handle | 100 | /* HACK: ppc32 architecture doesn't have __ucmpdi2 function to handle |
62 | 64 bit comparations. So, on that architecture, with some gcc | 101 | 64 bit comparations. So, on that architecture, with some gcc |
@@ -64,110 +103,17 @@ char *v4l2_norm_to_name(v4l2_std_id id) | |||
64 | */ | 103 | */ |
65 | BUG_ON(myid != id); | 104 | BUG_ON(myid != id); |
66 | 105 | ||
67 | switch (myid) { | 106 | for (i = 0; standards[i].std; i++) |
68 | case V4L2_STD_PAL: | 107 | if (myid == standards[i].std) |
69 | name = "PAL"; | 108 | break; |
70 | break; | 109 | return standards[i].descr; |
71 | case V4L2_STD_PAL_BG: | ||
72 | name = "PAL-BG"; | ||
73 | break; | ||
74 | case V4L2_STD_PAL_DK: | ||
75 | name = "PAL-DK"; | ||
76 | break; | ||
77 | case V4L2_STD_PAL_B: | ||
78 | name = "PAL-B"; | ||
79 | break; | ||
80 | case V4L2_STD_PAL_B1: | ||
81 | name = "PAL-B1"; | ||
82 | break; | ||
83 | case V4L2_STD_PAL_G: | ||
84 | name = "PAL-G"; | ||
85 | break; | ||
86 | case V4L2_STD_PAL_H: | ||
87 | name = "PAL-H"; | ||
88 | break; | ||
89 | case V4L2_STD_PAL_I: | ||
90 | name = "PAL-I"; | ||
91 | break; | ||
92 | case V4L2_STD_PAL_D: | ||
93 | name = "PAL-D"; | ||
94 | break; | ||
95 | case V4L2_STD_PAL_D1: | ||
96 | name = "PAL-D1"; | ||
97 | break; | ||
98 | case V4L2_STD_PAL_K: | ||
99 | name = "PAL-K"; | ||
100 | break; | ||
101 | case V4L2_STD_PAL_M: | ||
102 | name = "PAL-M"; | ||
103 | break; | ||
104 | case V4L2_STD_PAL_N: | ||
105 | name = "PAL-N"; | ||
106 | break; | ||
107 | case V4L2_STD_PAL_Nc: | ||
108 | name = "PAL-Nc"; | ||
109 | break; | ||
110 | case V4L2_STD_PAL_60: | ||
111 | name = "PAL-60"; | ||
112 | break; | ||
113 | case V4L2_STD_NTSC: | ||
114 | name = "NTSC"; | ||
115 | break; | ||
116 | case V4L2_STD_NTSC_M: | ||
117 | name = "NTSC-M"; | ||
118 | break; | ||
119 | case V4L2_STD_NTSC_M_JP: | ||
120 | name = "NTSC-M-JP"; | ||
121 | break; | ||
122 | case V4L2_STD_NTSC_443: | ||
123 | name = "NTSC-443"; | ||
124 | break; | ||
125 | case V4L2_STD_NTSC_M_KR: | ||
126 | name = "NTSC-M-KR"; | ||
127 | break; | ||
128 | case V4L2_STD_SECAM: | ||
129 | name = "SECAM"; | ||
130 | break; | ||
131 | case V4L2_STD_SECAM_DK: | ||
132 | name = "SECAM-DK"; | ||
133 | break; | ||
134 | case V4L2_STD_SECAM_B: | ||
135 | name = "SECAM-B"; | ||
136 | break; | ||
137 | case V4L2_STD_SECAM_D: | ||
138 | name = "SECAM-D"; | ||
139 | break; | ||
140 | case V4L2_STD_SECAM_G: | ||
141 | name = "SECAM-G"; | ||
142 | break; | ||
143 | case V4L2_STD_SECAM_H: | ||
144 | name = "SECAM-H"; | ||
145 | break; | ||
146 | case V4L2_STD_SECAM_K: | ||
147 | name = "SECAM-K"; | ||
148 | break; | ||
149 | case V4L2_STD_SECAM_K1: | ||
150 | name = "SECAM-K1"; | ||
151 | break; | ||
152 | case V4L2_STD_SECAM_L: | ||
153 | name = "SECAM-L"; | ||
154 | break; | ||
155 | case V4L2_STD_SECAM_LC: | ||
156 | name = "SECAM-LC"; | ||
157 | break; | ||
158 | default: | ||
159 | name = "Unknown"; | ||
160 | break; | ||
161 | } | ||
162 | |||
163 | return name; | ||
164 | } | 110 | } |
165 | EXPORT_SYMBOL(v4l2_norm_to_name); | 111 | EXPORT_SYMBOL(v4l2_norm_to_name); |
166 | 112 | ||
167 | /* Fill in the fields of a v4l2_standard structure according to the | 113 | /* Fill in the fields of a v4l2_standard structure according to the |
168 | 'id' and 'transmission' parameters. Returns negative on error. */ | 114 | 'id' and 'transmission' parameters. Returns negative on error. */ |
169 | int v4l2_video_std_construct(struct v4l2_standard *vs, | 115 | int v4l2_video_std_construct(struct v4l2_standard *vs, |
170 | int id, char *name) | 116 | int id, const char *name) |
171 | { | 117 | { |
172 | u32 index = vs->index; | 118 | u32 index = vs->index; |
173 | 119 | ||
@@ -1218,95 +1164,40 @@ static int __video_do_ioctl(struct inode *inode, struct file *file, | |||
1218 | case VIDIOC_ENUMSTD: | 1164 | case VIDIOC_ENUMSTD: |
1219 | { | 1165 | { |
1220 | struct v4l2_standard *p = arg; | 1166 | struct v4l2_standard *p = arg; |
1221 | v4l2_std_id id = vfd->tvnorms,curr_id=0; | 1167 | v4l2_std_id id = vfd->tvnorms, curr_id = 0; |
1222 | unsigned int index = p->index,i; | 1168 | unsigned int index = p->index, i, j = 0; |
1223 | 1169 | const char *descr = ""; | |
1224 | if (index<0) { | 1170 | |
1225 | ret=-EINVAL; | 1171 | /* Return norm array in a canonical way */ |
1226 | break; | 1172 | for (i = 0; i <= index && id; i++) { |
1227 | } | 1173 | /* last std value in the standards array is 0, so this |
1228 | 1174 | while always ends there since (id & 0) == 0. */ | |
1229 | /* Return norm array on a canonical way */ | 1175 | while ((id & standards[j].std) != standards[j].std) |
1230 | for (i=0;i<= index && id; i++) { | 1176 | j++; |
1231 | if ( (id & V4L2_STD_PAL) == V4L2_STD_PAL) { | 1177 | curr_id = standards[j].std; |
1232 | curr_id = V4L2_STD_PAL; | 1178 | descr = standards[j].descr; |
1233 | } else if ( (id & V4L2_STD_PAL_BG) == V4L2_STD_PAL_BG) { | 1179 | j++; |
1234 | curr_id = V4L2_STD_PAL_BG; | 1180 | if (curr_id == 0) |
1235 | } else if ( (id & V4L2_STD_PAL_DK) == V4L2_STD_PAL_DK) { | ||
1236 | curr_id = V4L2_STD_PAL_DK; | ||
1237 | } else if ( (id & V4L2_STD_PAL_B) == V4L2_STD_PAL_B) { | ||
1238 | curr_id = V4L2_STD_PAL_B; | ||
1239 | } else if ( (id & V4L2_STD_PAL_B1) == V4L2_STD_PAL_B1) { | ||
1240 | curr_id = V4L2_STD_PAL_B1; | ||
1241 | } else if ( (id & V4L2_STD_PAL_G) == V4L2_STD_PAL_G) { | ||
1242 | curr_id = V4L2_STD_PAL_G; | ||
1243 | } else if ( (id & V4L2_STD_PAL_H) == V4L2_STD_PAL_H) { | ||
1244 | curr_id = V4L2_STD_PAL_H; | ||
1245 | } else if ( (id & V4L2_STD_PAL_I) == V4L2_STD_PAL_I) { | ||
1246 | curr_id = V4L2_STD_PAL_I; | ||
1247 | } else if ( (id & V4L2_STD_PAL_D) == V4L2_STD_PAL_D) { | ||
1248 | curr_id = V4L2_STD_PAL_D; | ||
1249 | } else if ( (id & V4L2_STD_PAL_D1) == V4L2_STD_PAL_D1) { | ||
1250 | curr_id = V4L2_STD_PAL_D1; | ||
1251 | } else if ( (id & V4L2_STD_PAL_K) == V4L2_STD_PAL_K) { | ||
1252 | curr_id = V4L2_STD_PAL_K; | ||
1253 | } else if ( (id & V4L2_STD_PAL_M) == V4L2_STD_PAL_M) { | ||
1254 | curr_id = V4L2_STD_PAL_M; | ||
1255 | } else if ( (id & V4L2_STD_PAL_N) == V4L2_STD_PAL_N) { | ||
1256 | curr_id = V4L2_STD_PAL_N; | ||
1257 | } else if ( (id & V4L2_STD_PAL_Nc) == V4L2_STD_PAL_Nc) { | ||
1258 | curr_id = V4L2_STD_PAL_Nc; | ||
1259 | } else if ( (id & V4L2_STD_PAL_60) == V4L2_STD_PAL_60) { | ||
1260 | curr_id = V4L2_STD_PAL_60; | ||
1261 | } else if ( (id & V4L2_STD_NTSC) == V4L2_STD_NTSC) { | ||
1262 | curr_id = V4L2_STD_NTSC; | ||
1263 | } else if ( (id & V4L2_STD_NTSC_M) == V4L2_STD_NTSC_M) { | ||
1264 | curr_id = V4L2_STD_NTSC_M; | ||
1265 | } else if ( (id & V4L2_STD_NTSC_M_JP) == V4L2_STD_NTSC_M_JP) { | ||
1266 | curr_id = V4L2_STD_NTSC_M_JP; | ||
1267 | } else if ( (id & V4L2_STD_NTSC_443) == V4L2_STD_NTSC_443) { | ||
1268 | curr_id = V4L2_STD_NTSC_443; | ||
1269 | } else if ( (id & V4L2_STD_NTSC_M_KR) == V4L2_STD_NTSC_M_KR) { | ||
1270 | curr_id = V4L2_STD_NTSC_M_KR; | ||
1271 | } else if ( (id & V4L2_STD_SECAM) == V4L2_STD_SECAM) { | ||
1272 | curr_id = V4L2_STD_SECAM; | ||
1273 | } else if ( (id & V4L2_STD_SECAM_DK) == V4L2_STD_SECAM_DK) { | ||
1274 | curr_id = V4L2_STD_SECAM_DK; | ||
1275 | } else if ( (id & V4L2_STD_SECAM_B) == V4L2_STD_SECAM_B) { | ||
1276 | curr_id = V4L2_STD_SECAM_B; | ||
1277 | } else if ( (id & V4L2_STD_SECAM_D) == V4L2_STD_SECAM_D) { | ||
1278 | curr_id = V4L2_STD_SECAM_D; | ||
1279 | } else if ( (id & V4L2_STD_SECAM_G) == V4L2_STD_SECAM_G) { | ||
1280 | curr_id = V4L2_STD_SECAM_G; | ||
1281 | } else if ( (id & V4L2_STD_SECAM_H) == V4L2_STD_SECAM_H) { | ||
1282 | curr_id = V4L2_STD_SECAM_H; | ||
1283 | } else if ( (id & V4L2_STD_SECAM_K) == V4L2_STD_SECAM_K) { | ||
1284 | curr_id = V4L2_STD_SECAM_K; | ||
1285 | } else if ( (id & V4L2_STD_SECAM_K1) == V4L2_STD_SECAM_K1) { | ||
1286 | curr_id = V4L2_STD_SECAM_K1; | ||
1287 | } else if ( (id & V4L2_STD_SECAM_L) == V4L2_STD_SECAM_L) { | ||
1288 | curr_id = V4L2_STD_SECAM_L; | ||
1289 | } else if ( (id & V4L2_STD_SECAM_LC) == V4L2_STD_SECAM_LC) { | ||
1290 | curr_id = V4L2_STD_SECAM_LC; | ||
1291 | } else { | ||
1292 | break; | 1181 | break; |
1293 | } | 1182 | if (curr_id != V4L2_STD_PAL && |
1294 | id &= ~curr_id; | 1183 | curr_id != V4L2_STD_SECAM && |
1184 | curr_id != V4L2_STD_NTSC) | ||
1185 | id &= ~curr_id; | ||
1295 | } | 1186 | } |
1296 | if (i<=index) | 1187 | if (i <= index) |
1297 | return -EINVAL; | 1188 | return -EINVAL; |
1298 | 1189 | ||
1299 | v4l2_video_std_construct(p, curr_id,v4l2_norm_to_name(curr_id)); | 1190 | v4l2_video_std_construct(p, curr_id, descr); |
1300 | p->index = index; | 1191 | p->index = index; |
1301 | 1192 | ||
1302 | dbgarg (cmd, "index=%d, id=%Ld, name=%s, fps=%d/%d, " | 1193 | dbgarg(cmd, "index=%d, id=%Ld, name=%s, fps=%d/%d, " |
1303 | "framelines=%d\n", p->index, | 1194 | "framelines=%d\n", p->index, |
1304 | (unsigned long long)p->id, p->name, | 1195 | (unsigned long long)p->id, p->name, |
1305 | p->frameperiod.numerator, | 1196 | p->frameperiod.numerator, |
1306 | p->frameperiod.denominator, | 1197 | p->frameperiod.denominator, |
1307 | p->framelines); | 1198 | p->framelines); |
1308 | 1199 | ||
1309 | ret=0; | 1200 | ret = 0; |
1310 | break; | 1201 | break; |
1311 | } | 1202 | } |
1312 | case VIDIOC_G_STD: | 1203 | case VIDIOC_G_STD: |
diff --git a/drivers/media/video/vivi.c b/drivers/media/video/vivi.c index 845be1864f68..5ff9a58b6135 100644 --- a/drivers/media/video/vivi.c +++ b/drivers/media/video/vivi.c | |||
@@ -327,13 +327,14 @@ static void vivi_fillbuff(struct vivi_dev *dev, struct vivi_buffer *buf) | |||
327 | int hmax = buf->vb.height; | 327 | int hmax = buf->vb.height; |
328 | int wmax = buf->vb.width; | 328 | int wmax = buf->vb.width; |
329 | struct timeval ts; | 329 | struct timeval ts; |
330 | char *tmpbuf = kmalloc(wmax * 2, GFP_ATOMIC); | 330 | char *tmpbuf; |
331 | void *vbuf = videobuf_to_vmalloc(&buf->vb); | 331 | void *vbuf = videobuf_to_vmalloc(&buf->vb); |
332 | 332 | ||
333 | if (!tmpbuf) | 333 | if (!vbuf) |
334 | return; | 334 | return; |
335 | 335 | ||
336 | if (!vbuf) | 336 | tmpbuf = kmalloc(wmax * 2, GFP_ATOMIC); |
337 | if (!tmpbuf) | ||
337 | return; | 338 | return; |
338 | 339 | ||
339 | for (h = 0; h < hmax; h++) { | 340 | for (h = 0; h < hmax; h++) { |
diff --git a/drivers/net/ehea/ehea.h b/drivers/net/ehea/ehea.h index fe872fbd671e..e01926b7b5b7 100644 --- a/drivers/net/ehea/ehea.h +++ b/drivers/net/ehea/ehea.h | |||
@@ -40,7 +40,7 @@ | |||
40 | #include <asm/io.h> | 40 | #include <asm/io.h> |
41 | 41 | ||
42 | #define DRV_NAME "ehea" | 42 | #define DRV_NAME "ehea" |
43 | #define DRV_VERSION "EHEA_0091" | 43 | #define DRV_VERSION "EHEA_0092" |
44 | 44 | ||
45 | /* eHEA capability flags */ | 45 | /* eHEA capability flags */ |
46 | #define DLPAR_PORT_ADD_REM 1 | 46 | #define DLPAR_PORT_ADD_REM 1 |
@@ -452,7 +452,7 @@ struct ehea_bcmc_reg_entry { | |||
452 | struct ehea_bcmc_reg_array { | 452 | struct ehea_bcmc_reg_array { |
453 | struct ehea_bcmc_reg_entry *arr; | 453 | struct ehea_bcmc_reg_entry *arr; |
454 | int num_entries; | 454 | int num_entries; |
455 | struct mutex lock; | 455 | spinlock_t lock; |
456 | }; | 456 | }; |
457 | 457 | ||
458 | #define EHEA_PORT_UP 1 | 458 | #define EHEA_PORT_UP 1 |
@@ -478,6 +478,7 @@ struct ehea_port { | |||
478 | int num_add_tx_qps; | 478 | int num_add_tx_qps; |
479 | int num_mcs; | 479 | int num_mcs; |
480 | int resets; | 480 | int resets; |
481 | u64 flags; | ||
481 | u64 mac_addr; | 482 | u64 mac_addr; |
482 | u32 logical_port_id; | 483 | u32 logical_port_id; |
483 | u32 port_speed; | 484 | u32 port_speed; |
@@ -501,7 +502,8 @@ struct port_res_cfg { | |||
501 | }; | 502 | }; |
502 | 503 | ||
503 | enum ehea_flag_bits { | 504 | enum ehea_flag_bits { |
504 | __EHEA_STOP_XFER | 505 | __EHEA_STOP_XFER, |
506 | __EHEA_DISABLE_PORT_RESET | ||
505 | }; | 507 | }; |
506 | 508 | ||
507 | void ehea_set_ethtool_ops(struct net_device *netdev); | 509 | void ehea_set_ethtool_ops(struct net_device *netdev); |
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c index 075fd547421e..0920b796bd78 100644 --- a/drivers/net/ehea/ehea_main.c +++ b/drivers/net/ehea/ehea_main.c | |||
@@ -118,6 +118,7 @@ static struct of_device_id ehea_device_table[] = { | |||
118 | }, | 118 | }, |
119 | {}, | 119 | {}, |
120 | }; | 120 | }; |
121 | MODULE_DEVICE_TABLE(of, ehea_device_table); | ||
121 | 122 | ||
122 | static struct of_platform_driver ehea_driver = { | 123 | static struct of_platform_driver ehea_driver = { |
123 | .name = "ehea", | 124 | .name = "ehea", |
@@ -137,6 +138,12 @@ void ehea_dump(void *adr, int len, char *msg) | |||
137 | } | 138 | } |
138 | } | 139 | } |
139 | 140 | ||
141 | void ehea_schedule_port_reset(struct ehea_port *port) | ||
142 | { | ||
143 | if (!test_bit(__EHEA_DISABLE_PORT_RESET, &port->flags)) | ||
144 | schedule_work(&port->reset_task); | ||
145 | } | ||
146 | |||
140 | static void ehea_update_firmware_handles(void) | 147 | static void ehea_update_firmware_handles(void) |
141 | { | 148 | { |
142 | struct ehea_fw_handle_entry *arr = NULL; | 149 | struct ehea_fw_handle_entry *arr = NULL; |
@@ -241,7 +248,7 @@ static void ehea_update_bcmc_registrations(void) | |||
241 | } | 248 | } |
242 | 249 | ||
243 | if (num_registrations) { | 250 | if (num_registrations) { |
244 | arr = kzalloc(num_registrations * sizeof(*arr), GFP_KERNEL); | 251 | arr = kzalloc(num_registrations * sizeof(*arr), GFP_ATOMIC); |
245 | if (!arr) | 252 | if (!arr) |
246 | return; /* Keep the existing array */ | 253 | return; /* Keep the existing array */ |
247 | } else | 254 | } else |
@@ -301,7 +308,7 @@ static struct net_device_stats *ehea_get_stats(struct net_device *dev) | |||
301 | 308 | ||
302 | memset(stats, 0, sizeof(*stats)); | 309 | memset(stats, 0, sizeof(*stats)); |
303 | 310 | ||
304 | cb2 = kzalloc(PAGE_SIZE, GFP_KERNEL); | 311 | cb2 = kzalloc(PAGE_SIZE, GFP_ATOMIC); |
305 | if (!cb2) { | 312 | if (!cb2) { |
306 | ehea_error("no mem for cb2"); | 313 | ehea_error("no mem for cb2"); |
307 | goto out; | 314 | goto out; |
@@ -587,7 +594,7 @@ static int ehea_treat_poll_error(struct ehea_port_res *pr, int rq, | |||
587 | "Resetting port.", pr->qp->init_attr.qp_nr); | 594 | "Resetting port.", pr->qp->init_attr.qp_nr); |
588 | ehea_dump(cqe, sizeof(*cqe), "CQE"); | 595 | ehea_dump(cqe, sizeof(*cqe), "CQE"); |
589 | } | 596 | } |
590 | schedule_work(&pr->port->reset_task); | 597 | ehea_schedule_port_reset(pr->port); |
591 | return 1; | 598 | return 1; |
592 | } | 599 | } |
593 | 600 | ||
@@ -616,7 +623,7 @@ static int get_skb_hdr(struct sk_buff *skb, void **iphdr, | |||
616 | *tcph = tcp_hdr(skb); | 623 | *tcph = tcp_hdr(skb); |
617 | 624 | ||
618 | /* check if ip header and tcp header are complete */ | 625 | /* check if ip header and tcp header are complete */ |
619 | if (iph->tot_len < ip_len + tcp_hdrlen(skb)) | 626 | if (ntohs(iph->tot_len) < ip_len + tcp_hdrlen(skb)) |
620 | return -1; | 627 | return -1; |
621 | 628 | ||
622 | *hdr_flags = LRO_IPV4 | LRO_TCP; | 629 | *hdr_flags = LRO_IPV4 | LRO_TCP; |
@@ -765,7 +772,7 @@ static struct ehea_cqe *ehea_proc_cqes(struct ehea_port_res *pr, int my_quota) | |||
765 | ehea_error("Send Completion Error: Resetting port"); | 772 | ehea_error("Send Completion Error: Resetting port"); |
766 | if (netif_msg_tx_err(pr->port)) | 773 | if (netif_msg_tx_err(pr->port)) |
767 | ehea_dump(cqe, sizeof(*cqe), "Send CQE"); | 774 | ehea_dump(cqe, sizeof(*cqe), "Send CQE"); |
768 | schedule_work(&pr->port->reset_task); | 775 | ehea_schedule_port_reset(pr->port); |
769 | break; | 776 | break; |
770 | } | 777 | } |
771 | 778 | ||
@@ -885,7 +892,7 @@ static irqreturn_t ehea_qp_aff_irq_handler(int irq, void *param) | |||
885 | eqe = ehea_poll_eq(port->qp_eq); | 892 | eqe = ehea_poll_eq(port->qp_eq); |
886 | } | 893 | } |
887 | 894 | ||
888 | schedule_work(&port->reset_task); | 895 | ehea_schedule_port_reset(port); |
889 | 896 | ||
890 | return IRQ_HANDLED; | 897 | return IRQ_HANDLED; |
891 | } | 898 | } |
@@ -1763,7 +1770,7 @@ static int ehea_set_mac_addr(struct net_device *dev, void *sa) | |||
1763 | 1770 | ||
1764 | memcpy(dev->dev_addr, mac_addr->sa_data, dev->addr_len); | 1771 | memcpy(dev->dev_addr, mac_addr->sa_data, dev->addr_len); |
1765 | 1772 | ||
1766 | mutex_lock(&ehea_bcmc_regs.lock); | 1773 | spin_lock(&ehea_bcmc_regs.lock); |
1767 | 1774 | ||
1768 | /* Deregister old MAC in pHYP */ | 1775 | /* Deregister old MAC in pHYP */ |
1769 | if (port->state == EHEA_PORT_UP) { | 1776 | if (port->state == EHEA_PORT_UP) { |
@@ -1785,7 +1792,7 @@ static int ehea_set_mac_addr(struct net_device *dev, void *sa) | |||
1785 | 1792 | ||
1786 | out_upregs: | 1793 | out_upregs: |
1787 | ehea_update_bcmc_registrations(); | 1794 | ehea_update_bcmc_registrations(); |
1788 | mutex_unlock(&ehea_bcmc_regs.lock); | 1795 | spin_unlock(&ehea_bcmc_regs.lock); |
1789 | out_free: | 1796 | out_free: |
1790 | kfree(cb0); | 1797 | kfree(cb0); |
1791 | out: | 1798 | out: |
@@ -1947,7 +1954,7 @@ static void ehea_set_multicast_list(struct net_device *dev) | |||
1947 | } | 1954 | } |
1948 | ehea_promiscuous(dev, 0); | 1955 | ehea_promiscuous(dev, 0); |
1949 | 1956 | ||
1950 | mutex_lock(&ehea_bcmc_regs.lock); | 1957 | spin_lock(&ehea_bcmc_regs.lock); |
1951 | 1958 | ||
1952 | if (dev->flags & IFF_ALLMULTI) { | 1959 | if (dev->flags & IFF_ALLMULTI) { |
1953 | ehea_allmulti(dev, 1); | 1960 | ehea_allmulti(dev, 1); |
@@ -1978,7 +1985,7 @@ static void ehea_set_multicast_list(struct net_device *dev) | |||
1978 | } | 1985 | } |
1979 | out: | 1986 | out: |
1980 | ehea_update_bcmc_registrations(); | 1987 | ehea_update_bcmc_registrations(); |
1981 | mutex_unlock(&ehea_bcmc_regs.lock); | 1988 | spin_unlock(&ehea_bcmc_regs.lock); |
1982 | return; | 1989 | return; |
1983 | } | 1990 | } |
1984 | 1991 | ||
@@ -2497,7 +2504,7 @@ static int ehea_up(struct net_device *dev) | |||
2497 | } | 2504 | } |
2498 | } | 2505 | } |
2499 | 2506 | ||
2500 | mutex_lock(&ehea_bcmc_regs.lock); | 2507 | spin_lock(&ehea_bcmc_regs.lock); |
2501 | 2508 | ||
2502 | ret = ehea_broadcast_reg_helper(port, H_REG_BCMC); | 2509 | ret = ehea_broadcast_reg_helper(port, H_REG_BCMC); |
2503 | if (ret) { | 2510 | if (ret) { |
@@ -2520,7 +2527,7 @@ out: | |||
2520 | ehea_info("Failed starting %s. ret=%i", dev->name, ret); | 2527 | ehea_info("Failed starting %s. ret=%i", dev->name, ret); |
2521 | 2528 | ||
2522 | ehea_update_bcmc_registrations(); | 2529 | ehea_update_bcmc_registrations(); |
2523 | mutex_unlock(&ehea_bcmc_regs.lock); | 2530 | spin_unlock(&ehea_bcmc_regs.lock); |
2524 | 2531 | ||
2525 | ehea_update_firmware_handles(); | 2532 | ehea_update_firmware_handles(); |
2526 | mutex_unlock(&ehea_fw_handles.lock); | 2533 | mutex_unlock(&ehea_fw_handles.lock); |
@@ -2575,7 +2582,7 @@ static int ehea_down(struct net_device *dev) | |||
2575 | 2582 | ||
2576 | mutex_lock(&ehea_fw_handles.lock); | 2583 | mutex_lock(&ehea_fw_handles.lock); |
2577 | 2584 | ||
2578 | mutex_lock(&ehea_bcmc_regs.lock); | 2585 | spin_lock(&ehea_bcmc_regs.lock); |
2579 | ehea_drop_multicast_list(dev); | 2586 | ehea_drop_multicast_list(dev); |
2580 | ehea_broadcast_reg_helper(port, H_DEREG_BCMC); | 2587 | ehea_broadcast_reg_helper(port, H_DEREG_BCMC); |
2581 | 2588 | ||
@@ -2584,7 +2591,7 @@ static int ehea_down(struct net_device *dev) | |||
2584 | port->state = EHEA_PORT_DOWN; | 2591 | port->state = EHEA_PORT_DOWN; |
2585 | 2592 | ||
2586 | ehea_update_bcmc_registrations(); | 2593 | ehea_update_bcmc_registrations(); |
2587 | mutex_unlock(&ehea_bcmc_regs.lock); | 2594 | spin_unlock(&ehea_bcmc_regs.lock); |
2588 | 2595 | ||
2589 | ret = ehea_clean_all_portres(port); | 2596 | ret = ehea_clean_all_portres(port); |
2590 | if (ret) | 2597 | if (ret) |
@@ -2605,13 +2612,14 @@ static int ehea_stop(struct net_device *dev) | |||
2605 | if (netif_msg_ifdown(port)) | 2612 | if (netif_msg_ifdown(port)) |
2606 | ehea_info("disabling port %s", dev->name); | 2613 | ehea_info("disabling port %s", dev->name); |
2607 | 2614 | ||
2615 | set_bit(__EHEA_DISABLE_PORT_RESET, &port->flags); | ||
2608 | cancel_work_sync(&port->reset_task); | 2616 | cancel_work_sync(&port->reset_task); |
2609 | |||
2610 | mutex_lock(&port->port_lock); | 2617 | mutex_lock(&port->port_lock); |
2611 | netif_stop_queue(dev); | 2618 | netif_stop_queue(dev); |
2612 | port_napi_disable(port); | 2619 | port_napi_disable(port); |
2613 | ret = ehea_down(dev); | 2620 | ret = ehea_down(dev); |
2614 | mutex_unlock(&port->port_lock); | 2621 | mutex_unlock(&port->port_lock); |
2622 | clear_bit(__EHEA_DISABLE_PORT_RESET, &port->flags); | ||
2615 | return ret; | 2623 | return ret; |
2616 | } | 2624 | } |
2617 | 2625 | ||
@@ -2941,7 +2949,7 @@ static void ehea_tx_watchdog(struct net_device *dev) | |||
2941 | 2949 | ||
2942 | if (netif_carrier_ok(dev) && | 2950 | if (netif_carrier_ok(dev) && |
2943 | !test_bit(__EHEA_STOP_XFER, &ehea_driver_flags)) | 2951 | !test_bit(__EHEA_STOP_XFER, &ehea_driver_flags)) |
2944 | schedule_work(&port->reset_task); | 2952 | ehea_schedule_port_reset(port); |
2945 | } | 2953 | } |
2946 | 2954 | ||
2947 | int ehea_sense_adapter_attr(struct ehea_adapter *adapter) | 2955 | int ehea_sense_adapter_attr(struct ehea_adapter *adapter) |
@@ -3590,7 +3598,7 @@ int __init ehea_module_init(void) | |||
3590 | memset(&ehea_bcmc_regs, 0, sizeof(ehea_bcmc_regs)); | 3598 | memset(&ehea_bcmc_regs, 0, sizeof(ehea_bcmc_regs)); |
3591 | 3599 | ||
3592 | mutex_init(&ehea_fw_handles.lock); | 3600 | mutex_init(&ehea_fw_handles.lock); |
3593 | mutex_init(&ehea_bcmc_regs.lock); | 3601 | spin_lock_init(&ehea_bcmc_regs.lock); |
3594 | 3602 | ||
3595 | ret = check_module_parm(); | 3603 | ret = check_module_parm(); |
3596 | if (ret) | 3604 | if (ret) |
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c index afd063fe11af..786d668c612e 100644 --- a/drivers/net/forcedeth.c +++ b/drivers/net/forcedeth.c | |||
@@ -4198,12 +4198,23 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |||
4198 | 4198 | ||
4199 | netif_carrier_off(dev); | 4199 | netif_carrier_off(dev); |
4200 | if (netif_running(dev)) { | 4200 | if (netif_running(dev)) { |
4201 | unsigned long flags; | ||
4202 | |||
4201 | nv_disable_irq(dev); | 4203 | nv_disable_irq(dev); |
4202 | netif_tx_lock_bh(dev); | 4204 | netif_tx_lock_bh(dev); |
4203 | spin_lock(&np->lock); | 4205 | /* with plain spinlock lockdep complains */ |
4206 | spin_lock_irqsave(&np->lock, flags); | ||
4204 | /* stop engines */ | 4207 | /* stop engines */ |
4208 | /* FIXME: | ||
4209 | * this can take some time, and interrupts are disabled | ||
4210 | * due to spin_lock_irqsave, but let's hope no daemon | ||
4211 | * is going to change the settings very often... | ||
4212 | * Worst case: | ||
4213 | * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX | ||
4214 | * + some minor delays, which is up to a second approximately | ||
4215 | */ | ||
4205 | nv_stop_rxtx(dev); | 4216 | nv_stop_rxtx(dev); |
4206 | spin_unlock(&np->lock); | 4217 | spin_unlock_irqrestore(&np->lock, flags); |
4207 | netif_tx_unlock_bh(dev); | 4218 | netif_tx_unlock_bh(dev); |
4208 | } | 4219 | } |
4209 | 4220 | ||
diff --git a/drivers/net/fs_enet/mac-fcc.c b/drivers/net/fs_enet/mac-fcc.c index e36321152d50..8268b3535b30 100644 --- a/drivers/net/fs_enet/mac-fcc.c +++ b/drivers/net/fs_enet/mac-fcc.c | |||
@@ -463,6 +463,9 @@ static void restart(struct net_device *dev) | |||
463 | else | 463 | else |
464 | C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); | 464 | C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB); |
465 | 465 | ||
466 | /* Restore multicast and promiscuous settings */ | ||
467 | set_multicast_list(dev); | ||
468 | |||
466 | S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); | 469 | S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT); |
467 | } | 470 | } |
468 | 471 | ||
diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c index 5d2108c5ac7c..babc79ad490b 100644 --- a/drivers/net/ibm_newemac/core.c +++ b/drivers/net/ibm_newemac/core.c | |||
@@ -1636,6 +1636,12 @@ static int emac_poll_rx(void *param, int budget) | |||
1636 | goto next; | 1636 | goto next; |
1637 | } | 1637 | } |
1638 | 1638 | ||
1639 | if (len < ETH_HLEN) { | ||
1640 | ++dev->estats.rx_dropped_stack; | ||
1641 | emac_recycle_rx_skb(dev, slot, len); | ||
1642 | goto next; | ||
1643 | } | ||
1644 | |||
1639 | if (len && len < EMAC_RX_COPY_THRESH) { | 1645 | if (len && len < EMAC_RX_COPY_THRESH) { |
1640 | struct sk_buff *copy_skb = | 1646 | struct sk_buff *copy_skb = |
1641 | alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC); | 1647 | alloc_skb(len + EMAC_RX_SKB_HEADROOM + 2, GFP_ATOMIC); |
@@ -2719,6 +2725,8 @@ static int __devinit emac_probe(struct of_device *ofdev, | |||
2719 | /* Clean rings */ | 2725 | /* Clean rings */ |
2720 | memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor)); | 2726 | memset(dev->tx_desc, 0, NUM_TX_BUFF * sizeof(struct mal_descriptor)); |
2721 | memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor)); | 2727 | memset(dev->rx_desc, 0, NUM_RX_BUFF * sizeof(struct mal_descriptor)); |
2728 | memset(dev->tx_skb, 0, NUM_TX_BUFF * sizeof(struct sk_buff *)); | ||
2729 | memset(dev->rx_skb, 0, NUM_RX_BUFF * sizeof(struct sk_buff *)); | ||
2722 | 2730 | ||
2723 | /* Attach to ZMII, if needed */ | 2731 | /* Attach to ZMII, if needed */ |
2724 | if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) && | 2732 | if (emac_has_feature(dev, EMAC_FTR_HAS_ZMII) && |
diff --git a/drivers/net/pasemi_mac.c b/drivers/net/pasemi_mac.c index 3b2a6c598088..993d87c9296f 100644 --- a/drivers/net/pasemi_mac.c +++ b/drivers/net/pasemi_mac.c | |||
@@ -277,7 +277,7 @@ static int get_skb_hdr(struct sk_buff *skb, void **iphdr, | |||
277 | *tcph = tcp_hdr(skb); | 277 | *tcph = tcp_hdr(skb); |
278 | 278 | ||
279 | /* check if ip header and tcp header are complete */ | 279 | /* check if ip header and tcp header are complete */ |
280 | if (iph->tot_len < ip_len + tcp_hdrlen(skb)) | 280 | if (ntohs(iph->tot_len) < ip_len + tcp_hdrlen(skb)) |
281 | return -1; | 281 | return -1; |
282 | 282 | ||
283 | *hdr_flags = LRO_IPV4 | LRO_TCP; | 283 | *hdr_flags = LRO_IPV4 | LRO_TCP; |
diff --git a/drivers/net/wan/hdlc_fr.c b/drivers/net/wan/hdlc_fr.c index 109bab34094d..62e93dac6b13 100644 --- a/drivers/net/wan/hdlc_fr.c +++ b/drivers/net/wan/hdlc_fr.c | |||
@@ -992,6 +992,7 @@ static int fr_rx(struct sk_buff *skb) | |||
992 | dev->stats.rx_bytes += skb->len; | 992 | dev->stats.rx_bytes += skb->len; |
993 | if (pvc->state.becn) | 993 | if (pvc->state.becn) |
994 | dev->stats.rx_compressed++; | 994 | dev->stats.rx_compressed++; |
995 | skb->dev = dev; | ||
995 | netif_rx(skb); | 996 | netif_rx(skb); |
996 | return NET_RX_SUCCESS; | 997 | return NET_RX_SUCCESS; |
997 | } else { | 998 | } else { |
diff --git a/drivers/net/wireless/hostap/hostap_80211_rx.c b/drivers/net/wireless/hostap/hostap_80211_rx.c index d669e5956ce7..f106bc1585a4 100644 --- a/drivers/net/wireless/hostap/hostap_80211_rx.c +++ b/drivers/net/wireless/hostap/hostap_80211_rx.c | |||
@@ -64,7 +64,7 @@ int prism2_rx_80211(struct net_device *dev, struct sk_buff *skb, | |||
64 | int hdrlen, phdrlen, head_need, tail_need; | 64 | int hdrlen, phdrlen, head_need, tail_need; |
65 | u16 fc; | 65 | u16 fc; |
66 | int prism_header, ret; | 66 | int prism_header, ret; |
67 | struct ieee80211_hdr_4addr *hdr; | 67 | struct ieee80211_hdr_4addr *fhdr; |
68 | 68 | ||
69 | iface = netdev_priv(dev); | 69 | iface = netdev_priv(dev); |
70 | local = iface->local; | 70 | local = iface->local; |
@@ -86,8 +86,8 @@ int prism2_rx_80211(struct net_device *dev, struct sk_buff *skb, | |||
86 | phdrlen = 0; | 86 | phdrlen = 0; |
87 | } | 87 | } |
88 | 88 | ||
89 | hdr = (struct ieee80211_hdr_4addr *) skb->data; | 89 | fhdr = (struct ieee80211_hdr_4addr *) skb->data; |
90 | fc = le16_to_cpu(hdr->frame_ctl); | 90 | fc = le16_to_cpu(fhdr->frame_ctl); |
91 | 91 | ||
92 | if (type == PRISM2_RX_MGMT && (fc & IEEE80211_FCTL_VERS)) { | 92 | if (type == PRISM2_RX_MGMT && (fc & IEEE80211_FCTL_VERS)) { |
93 | printk(KERN_DEBUG "%s: dropped management frame with header " | 93 | printk(KERN_DEBUG "%s: dropped management frame with header " |
@@ -572,7 +572,7 @@ hostap_rx_frame_wds(local_info_t *local, struct ieee80211_hdr_4addr *hdr, | |||
572 | hdr->addr1[2] != 0xff || hdr->addr1[3] != 0xff || | 572 | hdr->addr1[2] != 0xff || hdr->addr1[3] != 0xff || |
573 | hdr->addr1[4] != 0xff || hdr->addr1[5] != 0xff)) { | 573 | hdr->addr1[4] != 0xff || hdr->addr1[5] != 0xff)) { |
574 | /* RA (or BSSID) is not ours - drop */ | 574 | /* RA (or BSSID) is not ours - drop */ |
575 | PDEBUG(DEBUG_EXTRA, "%s: received WDS frame with " | 575 | PDEBUG(DEBUG_EXTRA2, "%s: received WDS frame with " |
576 | "not own or broadcast %s=%s\n", | 576 | "not own or broadcast %s=%s\n", |
577 | local->dev->name, | 577 | local->dev->name, |
578 | fc & IEEE80211_FCTL_FROMDS ? "RA" : "BSSID", | 578 | fc & IEEE80211_FCTL_FROMDS ? "RA" : "BSSID", |
diff --git a/drivers/net/wireless/hostap/hostap_ap.c b/drivers/net/wireless/hostap/hostap_ap.c index 06b23df8f69b..af3d4ef2a80b 100644 --- a/drivers/net/wireless/hostap/hostap_ap.c +++ b/drivers/net/wireless/hostap/hostap_ap.c | |||
@@ -1930,7 +1930,7 @@ static void handle_pspoll(local_info_t *local, | |||
1930 | PDEBUG(DEBUG_PS, " PSPOLL and AID[15:14] not set\n"); | 1930 | PDEBUG(DEBUG_PS, " PSPOLL and AID[15:14] not set\n"); |
1931 | return; | 1931 | return; |
1932 | } | 1932 | } |
1933 | aid &= ~BIT(15) & ~BIT(14); | 1933 | aid &= ~(BIT(15) | BIT(14)); |
1934 | if (aid == 0 || aid > MAX_AID_TABLE_SIZE) { | 1934 | if (aid == 0 || aid > MAX_AID_TABLE_SIZE) { |
1935 | PDEBUG(DEBUG_PS, " invalid aid=%d\n", aid); | 1935 | PDEBUG(DEBUG_PS, " invalid aid=%d\n", aid); |
1936 | return; | 1936 | return; |
diff --git a/drivers/net/wireless/hostap/hostap_cs.c b/drivers/net/wireless/hostap/hostap_cs.c index ed4317a17cbb..80039a0ae027 100644 --- a/drivers/net/wireless/hostap/hostap_cs.c +++ b/drivers/net/wireless/hostap/hostap_cs.c | |||
@@ -533,10 +533,10 @@ static void prism2_detach(struct pcmcia_device *link) | |||
533 | do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0) | 533 | do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0) |
534 | 534 | ||
535 | #define CFG_CHECK2(fn, retf) \ | 535 | #define CFG_CHECK2(fn, retf) \ |
536 | do { int ret = (retf); \ | 536 | do { int _ret = (retf); \ |
537 | if (ret != 0) { \ | 537 | if (_ret != 0) { \ |
538 | PDEBUG(DEBUG_EXTRA, "CardServices(" #fn ") returned %d\n", ret); \ | 538 | PDEBUG(DEBUG_EXTRA, "CardServices(" #fn ") returned %d\n", _ret); \ |
539 | cs_error(link, fn, ret); \ | 539 | cs_error(link, fn, _ret); \ |
540 | goto next_entry; \ | 540 | goto next_entry; \ |
541 | } \ | 541 | } \ |
542 | } while (0) | 542 | } while (0) |
diff --git a/drivers/net/wireless/hostap/hostap_hw.c b/drivers/net/wireless/hostap/hostap_hw.c index 79a9bc95d2a7..6c158a569485 100644 --- a/drivers/net/wireless/hostap/hostap_hw.c +++ b/drivers/net/wireless/hostap/hostap_hw.c | |||
@@ -2835,7 +2835,7 @@ static void hostap_passive_scan(unsigned long data) | |||
2835 | { | 2835 | { |
2836 | local_info_t *local = (local_info_t *) data; | 2836 | local_info_t *local = (local_info_t *) data; |
2837 | struct net_device *dev = local->dev; | 2837 | struct net_device *dev = local->dev; |
2838 | u16 channel; | 2838 | u16 chan; |
2839 | 2839 | ||
2840 | if (local->passive_scan_interval <= 0) | 2840 | if (local->passive_scan_interval <= 0) |
2841 | return; | 2841 | return; |
@@ -2872,11 +2872,11 @@ static void hostap_passive_scan(unsigned long data) | |||
2872 | 2872 | ||
2873 | printk(KERN_DEBUG "%s: passive scan channel %d\n", | 2873 | printk(KERN_DEBUG "%s: passive scan channel %d\n", |
2874 | dev->name, local->passive_scan_channel); | 2874 | dev->name, local->passive_scan_channel); |
2875 | channel = local->passive_scan_channel; | 2875 | chan = local->passive_scan_channel; |
2876 | local->passive_scan_state = PASSIVE_SCAN_WAIT; | 2876 | local->passive_scan_state = PASSIVE_SCAN_WAIT; |
2877 | local->passive_scan_timer.expires = jiffies + HZ / 10; | 2877 | local->passive_scan_timer.expires = jiffies + HZ / 10; |
2878 | } else { | 2878 | } else { |
2879 | channel = local->channel; | 2879 | chan = local->channel; |
2880 | local->passive_scan_state = PASSIVE_SCAN_LISTEN; | 2880 | local->passive_scan_state = PASSIVE_SCAN_LISTEN; |
2881 | local->passive_scan_timer.expires = jiffies + | 2881 | local->passive_scan_timer.expires = jiffies + |
2882 | local->passive_scan_interval * HZ; | 2882 | local->passive_scan_interval * HZ; |
@@ -2884,9 +2884,9 @@ static void hostap_passive_scan(unsigned long data) | |||
2884 | 2884 | ||
2885 | if (hfa384x_cmd_callback(dev, HFA384X_CMDCODE_TEST | | 2885 | if (hfa384x_cmd_callback(dev, HFA384X_CMDCODE_TEST | |
2886 | (HFA384X_TEST_CHANGE_CHANNEL << 8), | 2886 | (HFA384X_TEST_CHANGE_CHANNEL << 8), |
2887 | channel, NULL, 0)) | 2887 | chan, NULL, 0)) |
2888 | printk(KERN_ERR "%s: passive scan channel set %d " | 2888 | printk(KERN_ERR "%s: passive scan channel set %d " |
2889 | "failed\n", dev->name, channel); | 2889 | "failed\n", dev->name, chan); |
2890 | 2890 | ||
2891 | add_timer(&local->passive_scan_timer); | 2891 | add_timer(&local->passive_scan_timer); |
2892 | } | 2892 | } |
diff --git a/drivers/net/wireless/hostap/hostap_main.c b/drivers/net/wireless/hostap/hostap_main.c index b5213f61fb0b..756ab56c1f40 100644 --- a/drivers/net/wireless/hostap/hostap_main.c +++ b/drivers/net/wireless/hostap/hostap_main.c | |||
@@ -594,7 +594,8 @@ void hostap_dump_tx_header(const char *name, const struct hfa384x_tx_frame *tx) | |||
594 | } | 594 | } |
595 | 595 | ||
596 | 596 | ||
597 | int hostap_80211_header_parse(const struct sk_buff *skb, unsigned char *haddr) | 597 | static int hostap_80211_header_parse(const struct sk_buff *skb, |
598 | unsigned char *haddr) | ||
598 | { | 599 | { |
599 | memcpy(haddr, skb_mac_header(skb) + 10, ETH_ALEN); /* addr2 */ | 600 | memcpy(haddr, skb_mac_header(skb) + 10, ETH_ALEN); /* addr2 */ |
600 | return ETH_ALEN; | 601 | return ETH_ALEN; |
@@ -839,7 +840,6 @@ const struct header_ops hostap_80211_ops = { | |||
839 | .rebuild = eth_rebuild_header, | 840 | .rebuild = eth_rebuild_header, |
840 | .cache = eth_header_cache, | 841 | .cache = eth_header_cache, |
841 | .cache_update = eth_header_cache_update, | 842 | .cache_update = eth_header_cache_update, |
842 | |||
843 | .parse = hostap_80211_header_parse, | 843 | .parse = hostap_80211_header_parse, |
844 | }; | 844 | }; |
845 | EXPORT_SYMBOL(hostap_80211_ops); | 845 | EXPORT_SYMBOL(hostap_80211_ops); |
@@ -1132,7 +1132,6 @@ EXPORT_SYMBOL(hostap_set_roaming); | |||
1132 | EXPORT_SYMBOL(hostap_set_auth_algs); | 1132 | EXPORT_SYMBOL(hostap_set_auth_algs); |
1133 | EXPORT_SYMBOL(hostap_dump_rx_header); | 1133 | EXPORT_SYMBOL(hostap_dump_rx_header); |
1134 | EXPORT_SYMBOL(hostap_dump_tx_header); | 1134 | EXPORT_SYMBOL(hostap_dump_tx_header); |
1135 | EXPORT_SYMBOL(hostap_80211_header_parse); | ||
1136 | EXPORT_SYMBOL(hostap_80211_get_hdrlen); | 1135 | EXPORT_SYMBOL(hostap_80211_get_hdrlen); |
1137 | EXPORT_SYMBOL(hostap_get_stats); | 1136 | EXPORT_SYMBOL(hostap_get_stats); |
1138 | EXPORT_SYMBOL(hostap_setup_dev); | 1137 | EXPORT_SYMBOL(hostap_setup_dev); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c index 63f20370032d..38866ab0040f 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945.c +++ b/drivers/net/wireless/iwlwifi/iwl-3945.c | |||
@@ -590,8 +590,12 @@ static void iwl3945_add_radiotap(struct iwl3945_priv *priv, | |||
590 | 590 | ||
591 | if (rate == -1) | 591 | if (rate == -1) |
592 | iwl3945_rt->rt_rate = 0; | 592 | iwl3945_rt->rt_rate = 0; |
593 | else | 593 | else { |
594 | if (stats->band == IEEE80211_BAND_5GHZ) | ||
595 | rate += IWL_FIRST_OFDM_RATE; | ||
596 | |||
594 | iwl3945_rt->rt_rate = iwl3945_rates[rate].ieee; | 597 | iwl3945_rt->rt_rate = iwl3945_rates[rate].ieee; |
598 | } | ||
595 | 599 | ||
596 | /* antenna number */ | 600 | /* antenna number */ |
597 | antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK; | 601 | antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK; |
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c index 3bc2644039f0..baa1abd5a14d 100644 --- a/drivers/net/wireless/iwlwifi/iwl3945-base.c +++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c | |||
@@ -6694,6 +6694,12 @@ static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
6694 | 6694 | ||
6695 | IWL_DEBUG_MAC80211("enter\n"); | 6695 | IWL_DEBUG_MAC80211("enter\n"); |
6696 | 6696 | ||
6697 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | ||
6698 | IWL_DEBUG_MAC80211("leave - monitor\n"); | ||
6699 | dev_kfree_skb_any(skb); | ||
6700 | return 0; | ||
6701 | } | ||
6702 | |||
6697 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, | 6703 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
6698 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); | 6704 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
6699 | 6705 | ||
diff --git a/drivers/net/wireless/iwlwifi/iwl4965-base.c b/drivers/net/wireless/iwlwifi/iwl4965-base.c index ba0f28945eb1..60b7a6498fe8 100644 --- a/drivers/net/wireless/iwlwifi/iwl4965-base.c +++ b/drivers/net/wireless/iwlwifi/iwl4965-base.c | |||
@@ -2682,7 +2682,8 @@ static int iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
2682 | 2682 | ||
2683 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | 2683 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { |
2684 | IWL_DEBUG_MAC80211("leave - monitor\n"); | 2684 | IWL_DEBUG_MAC80211("leave - monitor\n"); |
2685 | return -1; | 2685 | dev_kfree_skb_any(skb); |
2686 | return 0; | ||
2686 | } | 2687 | } |
2687 | 2688 | ||
2688 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, | 2689 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
diff --git a/drivers/net/wireless/libertas/if_usb.c b/drivers/net/wireless/libertas/if_usb.c index 24783103a7dd..a8b4abce5bfa 100644 --- a/drivers/net/wireless/libertas/if_usb.c +++ b/drivers/net/wireless/libertas/if_usb.c | |||
@@ -947,6 +947,7 @@ static struct usb_driver if_usb_driver = { | |||
947 | .id_table = if_usb_table, | 947 | .id_table = if_usb_table, |
948 | .suspend = if_usb_suspend, | 948 | .suspend = if_usb_suspend, |
949 | .resume = if_usb_resume, | 949 | .resume = if_usb_resume, |
950 | .reset_resume = if_usb_resume, | ||
950 | }; | 951 | }; |
951 | 952 | ||
952 | static int __init if_usb_init_module(void) | 953 | static int __init if_usb_init_module(void) |
diff --git a/drivers/pci/access.c b/drivers/pci/access.c index ec8f7002b09d..39bb96b413ef 100644 --- a/drivers/pci/access.c +++ b/drivers/pci/access.c | |||
@@ -178,8 +178,7 @@ static int pci_vpd_pci22_read(struct pci_dev *dev, int pos, int size, | |||
178 | int ret; | 178 | int ret; |
179 | int begin, end, i; | 179 | int begin, end, i; |
180 | 180 | ||
181 | if (pos < 0 || pos > PCI_VPD_PCI22_SIZE || | 181 | if (pos < 0 || pos > vpd->base.len || size > vpd->base.len - pos) |
182 | size > PCI_VPD_PCI22_SIZE - pos) | ||
183 | return -EINVAL; | 182 | return -EINVAL; |
184 | if (size == 0) | 183 | if (size == 0) |
185 | return 0; | 184 | return 0; |
@@ -223,8 +222,8 @@ static int pci_vpd_pci22_write(struct pci_dev *dev, int pos, int size, | |||
223 | u32 val; | 222 | u32 val; |
224 | int ret; | 223 | int ret; |
225 | 224 | ||
226 | if (pos < 0 || pos > PCI_VPD_PCI22_SIZE || pos & 3 || | 225 | if (pos < 0 || pos > vpd->base.len || pos & 3 || |
227 | size > PCI_VPD_PCI22_SIZE - pos || size < 4) | 226 | size > vpd->base.len - pos || size < 4) |
228 | return -EINVAL; | 227 | return -EINVAL; |
229 | 228 | ||
230 | val = (u8) *buf++; | 229 | val = (u8) *buf++; |
@@ -255,11 +254,6 @@ out: | |||
255 | return 4; | 254 | return 4; |
256 | } | 255 | } |
257 | 256 | ||
258 | static int pci_vpd_pci22_get_size(struct pci_dev *dev) | ||
259 | { | ||
260 | return PCI_VPD_PCI22_SIZE; | ||
261 | } | ||
262 | |||
263 | static void pci_vpd_pci22_release(struct pci_dev *dev) | 257 | static void pci_vpd_pci22_release(struct pci_dev *dev) |
264 | { | 258 | { |
265 | kfree(container_of(dev->vpd, struct pci_vpd_pci22, base)); | 259 | kfree(container_of(dev->vpd, struct pci_vpd_pci22, base)); |
@@ -268,7 +262,6 @@ static void pci_vpd_pci22_release(struct pci_dev *dev) | |||
268 | static struct pci_vpd_ops pci_vpd_pci22_ops = { | 262 | static struct pci_vpd_ops pci_vpd_pci22_ops = { |
269 | .read = pci_vpd_pci22_read, | 263 | .read = pci_vpd_pci22_read, |
270 | .write = pci_vpd_pci22_write, | 264 | .write = pci_vpd_pci22_write, |
271 | .get_size = pci_vpd_pci22_get_size, | ||
272 | .release = pci_vpd_pci22_release, | 265 | .release = pci_vpd_pci22_release, |
273 | }; | 266 | }; |
274 | 267 | ||
@@ -284,6 +277,7 @@ int pci_vpd_pci22_init(struct pci_dev *dev) | |||
284 | if (!vpd) | 277 | if (!vpd) |
285 | return -ENOMEM; | 278 | return -ENOMEM; |
286 | 279 | ||
280 | vpd->base.len = PCI_VPD_PCI22_SIZE; | ||
287 | vpd->base.ops = &pci_vpd_pci22_ops; | 281 | vpd->base.ops = &pci_vpd_pci22_ops; |
288 | spin_lock_init(&vpd->lock); | 282 | spin_lock_init(&vpd->lock); |
289 | vpd->cap = cap; | 283 | vpd->cap = cap; |
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c index 648596d469f6..91156f85a926 100644 --- a/drivers/pci/hotplug/acpiphp_glue.c +++ b/drivers/pci/hotplug/acpiphp_glue.c | |||
@@ -700,9 +700,10 @@ cleanup_p2p_bridge(acpi_handle handle, u32 lvl, void *context, void **rv) | |||
700 | acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, (u32)1, | 700 | acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, (u32)1, |
701 | cleanup_p2p_bridge, NULL, NULL); | 701 | cleanup_p2p_bridge, NULL, NULL); |
702 | 702 | ||
703 | if (!(bridge = acpiphp_handle_to_bridge(handle))) | 703 | bridge = acpiphp_handle_to_bridge(handle); |
704 | return AE_OK; | 704 | if (bridge) |
705 | cleanup_bridge(bridge); | 705 | cleanup_bridge(bridge); |
706 | |||
706 | return AE_OK; | 707 | return AE_OK; |
707 | } | 708 | } |
708 | 709 | ||
@@ -715,9 +716,19 @@ static void remove_bridge(acpi_handle handle) | |||
715 | acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, | 716 | acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, |
716 | (u32)1, cleanup_p2p_bridge, NULL, NULL); | 717 | (u32)1, cleanup_p2p_bridge, NULL, NULL); |
717 | 718 | ||
719 | /* | ||
720 | * On root bridges with hotplug slots directly underneath (ie, | ||
721 | * no p2p bridge inbetween), we call cleanup_bridge(). | ||
722 | * | ||
723 | * The else clause cleans up root bridges that either had no | ||
724 | * hotplug slots at all, or had a p2p bridge underneath. | ||
725 | */ | ||
718 | bridge = acpiphp_handle_to_bridge(handle); | 726 | bridge = acpiphp_handle_to_bridge(handle); |
719 | if (bridge) | 727 | if (bridge) |
720 | cleanup_bridge(bridge); | 728 | cleanup_bridge(bridge); |
729 | else | ||
730 | acpi_remove_notify_handler(handle, ACPI_SYSTEM_NOTIFY, | ||
731 | handle_hotplug_event_bridge); | ||
721 | } | 732 | } |
722 | 733 | ||
723 | static struct pci_dev * get_apic_pci_info(acpi_handle handle) | 734 | static struct pci_dev * get_apic_pci_info(acpi_handle handle) |
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 72cf61ed8f96..e1637bd82b8e 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c | |||
@@ -181,7 +181,7 @@ static int pci_call_probe(struct pci_driver *drv, struct pci_dev *dev, | |||
181 | any need to change it. */ | 181 | any need to change it. */ |
182 | struct mempolicy *oldpol; | 182 | struct mempolicy *oldpol; |
183 | cpumask_t oldmask = current->cpus_allowed; | 183 | cpumask_t oldmask = current->cpus_allowed; |
184 | int node = pcibus_to_node(dev->bus); | 184 | int node = dev_to_node(&dev->dev); |
185 | 185 | ||
186 | if (node >= 0) { | 186 | if (node >= 0) { |
187 | node_to_cpumask_ptr(nodecpumask, node); | 187 | node_to_cpumask_ptr(nodecpumask, node); |
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 271d41cc05ab..9c718583a237 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c | |||
@@ -489,13 +489,13 @@ pci_mmap_legacy_mem(struct kobject *kobj, struct bin_attribute *attr, | |||
489 | * @kobj: kobject for mapping | 489 | * @kobj: kobject for mapping |
490 | * @attr: struct bin_attribute for the file being mapped | 490 | * @attr: struct bin_attribute for the file being mapped |
491 | * @vma: struct vm_area_struct passed into the mmap | 491 | * @vma: struct vm_area_struct passed into the mmap |
492 | * @write_combine: 1 for write_combine mapping | ||
492 | * | 493 | * |
493 | * Use the regular PCI mapping routines to map a PCI resource into userspace. | 494 | * Use the regular PCI mapping routines to map a PCI resource into userspace. |
494 | * FIXME: write combining? maybe automatic for prefetchable regions? | ||
495 | */ | 495 | */ |
496 | static int | 496 | static int |
497 | pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr, | 497 | pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr, |
498 | struct vm_area_struct *vma) | 498 | struct vm_area_struct *vma, int write_combine) |
499 | { | 499 | { |
500 | struct pci_dev *pdev = to_pci_dev(container_of(kobj, | 500 | struct pci_dev *pdev = to_pci_dev(container_of(kobj, |
501 | struct device, kobj)); | 501 | struct device, kobj)); |
@@ -518,7 +518,21 @@ pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr, | |||
518 | vma->vm_pgoff += start >> PAGE_SHIFT; | 518 | vma->vm_pgoff += start >> PAGE_SHIFT; |
519 | mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io; | 519 | mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io; |
520 | 520 | ||
521 | return pci_mmap_page_range(pdev, vma, mmap_type, 0); | 521 | return pci_mmap_page_range(pdev, vma, mmap_type, write_combine); |
522 | } | ||
523 | |||
524 | static int | ||
525 | pci_mmap_resource_uc(struct kobject *kobj, struct bin_attribute *attr, | ||
526 | struct vm_area_struct *vma) | ||
527 | { | ||
528 | return pci_mmap_resource(kobj, attr, vma, 0); | ||
529 | } | ||
530 | |||
531 | static int | ||
532 | pci_mmap_resource_wc(struct kobject *kobj, struct bin_attribute *attr, | ||
533 | struct vm_area_struct *vma) | ||
534 | { | ||
535 | return pci_mmap_resource(kobj, attr, vma, 1); | ||
522 | } | 536 | } |
523 | 537 | ||
524 | /** | 538 | /** |
@@ -541,9 +555,46 @@ pci_remove_resource_files(struct pci_dev *pdev) | |||
541 | sysfs_remove_bin_file(&pdev->dev.kobj, res_attr); | 555 | sysfs_remove_bin_file(&pdev->dev.kobj, res_attr); |
542 | kfree(res_attr); | 556 | kfree(res_attr); |
543 | } | 557 | } |
558 | |||
559 | res_attr = pdev->res_attr_wc[i]; | ||
560 | if (res_attr) { | ||
561 | sysfs_remove_bin_file(&pdev->dev.kobj, res_attr); | ||
562 | kfree(res_attr); | ||
563 | } | ||
544 | } | 564 | } |
545 | } | 565 | } |
546 | 566 | ||
567 | static int pci_create_attr(struct pci_dev *pdev, int num, int write_combine) | ||
568 | { | ||
569 | /* allocate attribute structure, piggyback attribute name */ | ||
570 | int name_len = write_combine ? 13 : 10; | ||
571 | struct bin_attribute *res_attr; | ||
572 | int retval; | ||
573 | |||
574 | res_attr = kzalloc(sizeof(*res_attr) + name_len, GFP_ATOMIC); | ||
575 | if (res_attr) { | ||
576 | char *res_attr_name = (char *)(res_attr + 1); | ||
577 | |||
578 | if (write_combine) { | ||
579 | pdev->res_attr_wc[num] = res_attr; | ||
580 | sprintf(res_attr_name, "resource%d_wc", num); | ||
581 | res_attr->mmap = pci_mmap_resource_wc; | ||
582 | } else { | ||
583 | pdev->res_attr[num] = res_attr; | ||
584 | sprintf(res_attr_name, "resource%d", num); | ||
585 | res_attr->mmap = pci_mmap_resource_uc; | ||
586 | } | ||
587 | res_attr->attr.name = res_attr_name; | ||
588 | res_attr->attr.mode = S_IRUSR | S_IWUSR; | ||
589 | res_attr->size = pci_resource_len(pdev, num); | ||
590 | res_attr->private = &pdev->resource[num]; | ||
591 | retval = sysfs_create_bin_file(&pdev->dev.kobj, res_attr); | ||
592 | } else | ||
593 | retval = -ENOMEM; | ||
594 | |||
595 | return retval; | ||
596 | } | ||
597 | |||
547 | /** | 598 | /** |
548 | * pci_create_resource_files - create resource files in sysfs for @dev | 599 | * pci_create_resource_files - create resource files in sysfs for @dev |
549 | * @dev: dev in question | 600 | * @dev: dev in question |
@@ -557,31 +608,19 @@ static int pci_create_resource_files(struct pci_dev *pdev) | |||
557 | 608 | ||
558 | /* Expose the PCI resources from this device as files */ | 609 | /* Expose the PCI resources from this device as files */ |
559 | for (i = 0; i < PCI_ROM_RESOURCE; i++) { | 610 | for (i = 0; i < PCI_ROM_RESOURCE; i++) { |
560 | struct bin_attribute *res_attr; | ||
561 | 611 | ||
562 | /* skip empty resources */ | 612 | /* skip empty resources */ |
563 | if (!pci_resource_len(pdev, i)) | 613 | if (!pci_resource_len(pdev, i)) |
564 | continue; | 614 | continue; |
565 | 615 | ||
566 | /* allocate attribute structure, piggyback attribute name */ | 616 | retval = pci_create_attr(pdev, i, 0); |
567 | res_attr = kzalloc(sizeof(*res_attr) + 10, GFP_ATOMIC); | 617 | /* for prefetchable resources, create a WC mappable file */ |
568 | if (res_attr) { | 618 | if (!retval && pdev->resource[i].flags & IORESOURCE_PREFETCH) |
569 | char *res_attr_name = (char *)(res_attr + 1); | 619 | retval = pci_create_attr(pdev, i, 1); |
570 | 620 | ||
571 | pdev->res_attr[i] = res_attr; | 621 | if (retval) { |
572 | sprintf(res_attr_name, "resource%d", i); | 622 | pci_remove_resource_files(pdev); |
573 | res_attr->attr.name = res_attr_name; | 623 | return retval; |
574 | res_attr->attr.mode = S_IRUSR | S_IWUSR; | ||
575 | res_attr->size = pci_resource_len(pdev, i); | ||
576 | res_attr->mmap = pci_mmap_resource; | ||
577 | res_attr->private = &pdev->resource[i]; | ||
578 | retval = sysfs_create_bin_file(&pdev->dev.kobj, res_attr); | ||
579 | if (retval) { | ||
580 | pci_remove_resource_files(pdev); | ||
581 | return retval; | ||
582 | } | ||
583 | } else { | ||
584 | return -ENOMEM; | ||
585 | } | 624 | } |
586 | } | 625 | } |
587 | return 0; | 626 | return 0; |
@@ -697,9 +736,9 @@ int __must_check pci_create_sysfs_dev_files (struct pci_dev *pdev) | |||
697 | attr = kzalloc(sizeof(*attr), GFP_ATOMIC); | 736 | attr = kzalloc(sizeof(*attr), GFP_ATOMIC); |
698 | if (attr) { | 737 | if (attr) { |
699 | pdev->vpd->attr = attr; | 738 | pdev->vpd->attr = attr; |
700 | attr->size = pdev->vpd->ops->get_size(pdev); | 739 | attr->size = pdev->vpd->len; |
701 | attr->attr.name = "vpd"; | 740 | attr->attr.name = "vpd"; |
702 | attr->attr.mode = S_IRUGO | S_IWUSR; | 741 | attr->attr.mode = S_IRUSR | S_IWUSR; |
703 | attr->read = pci_read_vpd; | 742 | attr->read = pci_read_vpd; |
704 | attr->write = pci_write_vpd; | 743 | attr->write = pci_write_vpd; |
705 | retval = sysfs_create_bin_file(&pdev->dev.kobj, attr); | 744 | retval = sysfs_create_bin_file(&pdev->dev.kobj, attr); |
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 0a497c1b4227..00408c97e5fc 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h | |||
@@ -21,11 +21,11 @@ extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); | |||
21 | struct pci_vpd_ops { | 21 | struct pci_vpd_ops { |
22 | int (*read)(struct pci_dev *dev, int pos, int size, char *buf); | 22 | int (*read)(struct pci_dev *dev, int pos, int size, char *buf); |
23 | int (*write)(struct pci_dev *dev, int pos, int size, const char *buf); | 23 | int (*write)(struct pci_dev *dev, int pos, int size, const char *buf); |
24 | int (*get_size)(struct pci_dev *dev); | ||
25 | void (*release)(struct pci_dev *dev); | 24 | void (*release)(struct pci_dev *dev); |
26 | }; | 25 | }; |
27 | 26 | ||
28 | struct pci_vpd { | 27 | struct pci_vpd { |
28 | unsigned int len; | ||
29 | struct pci_vpd_ops *ops; | 29 | struct pci_vpd_ops *ops; |
30 | struct bin_attribute *attr; /* descriptor for sysfs VPD entry */ | 30 | struct bin_attribute *attr; /* descriptor for sysfs VPD entry */ |
31 | }; | 31 | }; |
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index dabb563f51d9..a3497dc6ebcf 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c | |||
@@ -1670,6 +1670,48 @@ static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) | |||
1670 | } | 1670 | } |
1671 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); | 1671 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); |
1672 | 1672 | ||
1673 | /* | ||
1674 | * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the | ||
1675 | * VPD end tag will hang the device. This problem was initially | ||
1676 | * observed when a vpd entry was created in sysfs | ||
1677 | * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry | ||
1678 | * will dump 32k of data. Reading a full 32k will cause an access | ||
1679 | * beyond the VPD end tag causing the device to hang. Once the device | ||
1680 | * is hung, the bnx2 driver will not be able to reset the device. | ||
1681 | * We believe that it is legal to read beyond the end tag and | ||
1682 | * therefore the solution is to limit the read/write length. | ||
1683 | */ | ||
1684 | static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev) | ||
1685 | { | ||
1686 | /* Only disable the VPD capability for 5706, 5708, and 5709 rev. A */ | ||
1687 | if ((dev->device == PCI_DEVICE_ID_NX2_5706) || | ||
1688 | (dev->device == PCI_DEVICE_ID_NX2_5708) || | ||
1689 | ((dev->device == PCI_DEVICE_ID_NX2_5709) && | ||
1690 | (dev->revision & 0xf0) == 0x0)) { | ||
1691 | if (dev->vpd) | ||
1692 | dev->vpd->len = 0x80; | ||
1693 | } | ||
1694 | } | ||
1695 | |||
1696 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, | ||
1697 | PCI_DEVICE_ID_NX2_5706, | ||
1698 | quirk_brcm_570x_limit_vpd); | ||
1699 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, | ||
1700 | PCI_DEVICE_ID_NX2_5706S, | ||
1701 | quirk_brcm_570x_limit_vpd); | ||
1702 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, | ||
1703 | PCI_DEVICE_ID_NX2_5708, | ||
1704 | quirk_brcm_570x_limit_vpd); | ||
1705 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, | ||
1706 | PCI_DEVICE_ID_NX2_5708S, | ||
1707 | quirk_brcm_570x_limit_vpd); | ||
1708 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, | ||
1709 | PCI_DEVICE_ID_NX2_5709, | ||
1710 | quirk_brcm_570x_limit_vpd); | ||
1711 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, | ||
1712 | PCI_DEVICE_ID_NX2_5709S, | ||
1713 | quirk_brcm_570x_limit_vpd); | ||
1714 | |||
1673 | #ifdef CONFIG_PCI_MSI | 1715 | #ifdef CONFIG_PCI_MSI |
1674 | /* Some chipsets do not support MSI. We cannot easily rely on setting | 1716 | /* Some chipsets do not support MSI. We cannot easily rely on setting |
1675 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually | 1717 | * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually |
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c index 82f62d25f921..67421b0d3a7b 100644 --- a/drivers/rtc/rtc-sa1100.c +++ b/drivers/rtc/rtc-sa1100.c | |||
@@ -331,14 +331,14 @@ static int sa1100_rtc_probe(struct platform_device *pdev) | |||
331 | RCNR = 0; | 331 | RCNR = 0; |
332 | } | 332 | } |
333 | 333 | ||
334 | device_init_wakeup(&pdev->dev, 1); | ||
335 | |||
334 | rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops, | 336 | rtc = rtc_device_register(pdev->name, &pdev->dev, &sa1100_rtc_ops, |
335 | THIS_MODULE); | 337 | THIS_MODULE); |
336 | 338 | ||
337 | if (IS_ERR(rtc)) | 339 | if (IS_ERR(rtc)) |
338 | return PTR_ERR(rtc); | 340 | return PTR_ERR(rtc); |
339 | 341 | ||
340 | device_init_wakeup(&pdev->dev, 1); | ||
341 | |||
342 | platform_set_drvdata(pdev, rtc); | 342 | platform_set_drvdata(pdev, rtc); |
343 | 343 | ||
344 | return 0; | 344 | return 0; |
diff --git a/drivers/scsi/dpt/dptsig.h b/drivers/scsi/dpt/dptsig.h index 72c8992fdf21..a6644b332b53 100644 --- a/drivers/scsi/dpt/dptsig.h +++ b/drivers/scsi/dpt/dptsig.h | |||
@@ -85,7 +85,7 @@ typedef unsigned int sigINT; | |||
85 | /* ------------------------------------------------------------------ */ | 85 | /* ------------------------------------------------------------------ */ |
86 | /* What type of processor the file is meant to run on. */ | 86 | /* What type of processor the file is meant to run on. */ |
87 | /* This will let us know whether to read sigWORDs as high/low or low/high. */ | 87 | /* This will let us know whether to read sigWORDs as high/low or low/high. */ |
88 | #define PROC_INTEL 0x00 /* Intel 80x86 */ | 88 | #define PROC_INTEL 0x00 /* Intel 80x86/ia64 */ |
89 | #define PROC_MOTOROLA 0x01 /* Motorola 68K */ | 89 | #define PROC_MOTOROLA 0x01 /* Motorola 68K */ |
90 | #define PROC_MIPS4000 0x02 /* MIPS RISC 4000 */ | 90 | #define PROC_MIPS4000 0x02 /* MIPS RISC 4000 */ |
91 | #define PROC_ALPHA 0x03 /* DEC Alpha */ | 91 | #define PROC_ALPHA 0x03 /* DEC Alpha */ |
@@ -104,6 +104,7 @@ typedef unsigned int sigINT; | |||
104 | #define PROC_486 0x08 /* Intel 80486 */ | 104 | #define PROC_486 0x08 /* Intel 80486 */ |
105 | #define PROC_PENTIUM 0x10 /* Intel 586 aka P5 aka Pentium */ | 105 | #define PROC_PENTIUM 0x10 /* Intel 586 aka P5 aka Pentium */ |
106 | #define PROC_SEXIUM 0x20 /* Intel 686 aka P6 aka Pentium Pro or MMX */ | 106 | #define PROC_SEXIUM 0x20 /* Intel 686 aka P6 aka Pentium Pro or MMX */ |
107 | #define PROC_IA64 0x40 /* Intel IA64 processor */ | ||
107 | 108 | ||
108 | /* PROC_i960: */ | 109 | /* PROC_i960: */ |
109 | #define PROC_960RX 0x01 /* Intel 80960RC/RD */ | 110 | #define PROC_960RX 0x01 /* Intel 80960RC/RD */ |
diff --git a/drivers/scsi/esp_scsi.c b/drivers/scsi/esp_scsi.c index a0b6d414953d..59fbef08d690 100644 --- a/drivers/scsi/esp_scsi.c +++ b/drivers/scsi/esp_scsi.c | |||
@@ -2359,6 +2359,24 @@ void scsi_esp_unregister(struct esp *esp) | |||
2359 | } | 2359 | } |
2360 | EXPORT_SYMBOL(scsi_esp_unregister); | 2360 | EXPORT_SYMBOL(scsi_esp_unregister); |
2361 | 2361 | ||
2362 | static int esp_target_alloc(struct scsi_target *starget) | ||
2363 | { | ||
2364 | struct esp *esp = shost_priv(dev_to_shost(&starget->dev)); | ||
2365 | struct esp_target_data *tp = &esp->target[starget->id]; | ||
2366 | |||
2367 | tp->starget = starget; | ||
2368 | |||
2369 | return 0; | ||
2370 | } | ||
2371 | |||
2372 | static void esp_target_destroy(struct scsi_target *starget) | ||
2373 | { | ||
2374 | struct esp *esp = shost_priv(dev_to_shost(&starget->dev)); | ||
2375 | struct esp_target_data *tp = &esp->target[starget->id]; | ||
2376 | |||
2377 | tp->starget = NULL; | ||
2378 | } | ||
2379 | |||
2362 | static int esp_slave_alloc(struct scsi_device *dev) | 2380 | static int esp_slave_alloc(struct scsi_device *dev) |
2363 | { | 2381 | { |
2364 | struct esp *esp = shost_priv(dev->host); | 2382 | struct esp *esp = shost_priv(dev->host); |
@@ -2370,8 +2388,6 @@ static int esp_slave_alloc(struct scsi_device *dev) | |||
2370 | return -ENOMEM; | 2388 | return -ENOMEM; |
2371 | dev->hostdata = lp; | 2389 | dev->hostdata = lp; |
2372 | 2390 | ||
2373 | tp->starget = dev->sdev_target; | ||
2374 | |||
2375 | spi_min_period(tp->starget) = esp->min_period; | 2391 | spi_min_period(tp->starget) = esp->min_period; |
2376 | spi_max_offset(tp->starget) = 15; | 2392 | spi_max_offset(tp->starget) = 15; |
2377 | 2393 | ||
@@ -2608,6 +2624,8 @@ struct scsi_host_template scsi_esp_template = { | |||
2608 | .name = "esp", | 2624 | .name = "esp", |
2609 | .info = esp_info, | 2625 | .info = esp_info, |
2610 | .queuecommand = esp_queuecommand, | 2626 | .queuecommand = esp_queuecommand, |
2627 | .target_alloc = esp_target_alloc, | ||
2628 | .target_destroy = esp_target_destroy, | ||
2611 | .slave_alloc = esp_slave_alloc, | 2629 | .slave_alloc = esp_slave_alloc, |
2612 | .slave_configure = esp_slave_configure, | 2630 | .slave_configure = esp_slave_configure, |
2613 | .slave_destroy = esp_slave_destroy, | 2631 | .slave_destroy = esp_slave_destroy, |
diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c index 3690360d7a79..c6457bfc8a49 100644 --- a/drivers/scsi/hosts.c +++ b/drivers/scsi/hosts.c | |||
@@ -456,6 +456,10 @@ static int __scsi_host_match(struct device *dev, void *data) | |||
456 | * | 456 | * |
457 | * Return value: | 457 | * Return value: |
458 | * A pointer to located Scsi_Host or NULL. | 458 | * A pointer to located Scsi_Host or NULL. |
459 | * | ||
460 | * The caller must do a scsi_host_put() to drop the reference | ||
461 | * that scsi_host_get() took. The put_device() below dropped | ||
462 | * the reference from class_find_device(). | ||
459 | **/ | 463 | **/ |
460 | struct Scsi_Host *scsi_host_lookup(unsigned short hostnum) | 464 | struct Scsi_Host *scsi_host_lookup(unsigned short hostnum) |
461 | { | 465 | { |
@@ -463,9 +467,10 @@ struct Scsi_Host *scsi_host_lookup(unsigned short hostnum) | |||
463 | struct Scsi_Host *shost = ERR_PTR(-ENXIO); | 467 | struct Scsi_Host *shost = ERR_PTR(-ENXIO); |
464 | 468 | ||
465 | cdev = class_find_device(&shost_class, &hostnum, __scsi_host_match); | 469 | cdev = class_find_device(&shost_class, &hostnum, __scsi_host_match); |
466 | if (cdev) | 470 | if (cdev) { |
467 | shost = scsi_host_get(class_to_shost(cdev)); | 471 | shost = scsi_host_get(class_to_shost(cdev)); |
468 | 472 | put_device(cdev); | |
473 | } | ||
469 | return shost; | 474 | return shost; |
470 | } | 475 | } |
471 | EXPORT_SYMBOL(scsi_host_lookup); | 476 | EXPORT_SYMBOL(scsi_host_lookup); |
diff --git a/drivers/scsi/ses.c b/drivers/scsi/ses.c index 45df83b9d847..0fe031f003e7 100644 --- a/drivers/scsi/ses.c +++ b/drivers/scsi/ses.c | |||
@@ -61,7 +61,7 @@ static int ses_probe(struct device *dev) | |||
61 | return err; | 61 | return err; |
62 | } | 62 | } |
63 | 63 | ||
64 | #define SES_TIMEOUT 30 | 64 | #define SES_TIMEOUT (30 * HZ) |
65 | #define SES_RETRIES 3 | 65 | #define SES_RETRIES 3 |
66 | 66 | ||
67 | static int ses_recv_diag(struct scsi_device *sdev, int page_code, | 67 | static int ses_recv_diag(struct scsi_device *sdev, int page_code, |
diff --git a/drivers/scsi/sr.c b/drivers/scsi/sr.c index 7ee86d4a7618..c82df8bd4d89 100644 --- a/drivers/scsi/sr.c +++ b/drivers/scsi/sr.c | |||
@@ -178,6 +178,9 @@ int sr_test_unit_ready(struct scsi_device *sdev, struct scsi_sense_hdr *sshdr) | |||
178 | the_result = scsi_execute_req(sdev, cmd, DMA_NONE, NULL, | 178 | the_result = scsi_execute_req(sdev, cmd, DMA_NONE, NULL, |
179 | 0, sshdr, SR_TIMEOUT, | 179 | 0, sshdr, SR_TIMEOUT, |
180 | retries--); | 180 | retries--); |
181 | if (scsi_sense_valid(sshdr) && | ||
182 | sshdr->sense_key == UNIT_ATTENTION) | ||
183 | sdev->changed = 1; | ||
181 | 184 | ||
182 | } while (retries > 0 && | 185 | } while (retries > 0 && |
183 | (!scsi_status_is_good(the_result) || | 186 | (!scsi_status_is_good(the_result) || |
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c index f20952c43cb8..fd9bb777df28 100644 --- a/drivers/serial/bfin_5xx.c +++ b/drivers/serial/bfin_5xx.c | |||
@@ -49,6 +49,7 @@ | |||
49 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | 49 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) |
50 | 50 | ||
51 | #define DMA_RX_FLUSH_JIFFIES (HZ / 50) | 51 | #define DMA_RX_FLUSH_JIFFIES (HZ / 50) |
52 | #define CTS_CHECK_JIFFIES (HZ / 50) | ||
52 | 53 | ||
53 | #ifdef CONFIG_SERIAL_BFIN_DMA | 54 | #ifdef CONFIG_SERIAL_BFIN_DMA |
54 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | 55 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); |
@@ -290,11 +291,6 @@ static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |||
290 | { | 291 | { |
291 | struct circ_buf *xmit = &uart->port.info->xmit; | 292 | struct circ_buf *xmit = &uart->port.info->xmit; |
292 | 293 | ||
293 | if (uart->port.x_char) { | ||
294 | UART_PUT_CHAR(uart, uart->port.x_char); | ||
295 | uart->port.icount.tx++; | ||
296 | uart->port.x_char = 0; | ||
297 | } | ||
298 | /* | 294 | /* |
299 | * Check the modem control lines before | 295 | * Check the modem control lines before |
300 | * transmitting anything. | 296 | * transmitting anything. |
@@ -306,6 +302,12 @@ static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |||
306 | return; | 302 | return; |
307 | } | 303 | } |
308 | 304 | ||
305 | if (uart->port.x_char) { | ||
306 | UART_PUT_CHAR(uart, uart->port.x_char); | ||
307 | uart->port.icount.tx++; | ||
308 | uart->port.x_char = 0; | ||
309 | } | ||
310 | |||
309 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { | 311 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { |
310 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); | 312 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); |
311 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | 313 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
@@ -345,15 +347,6 @@ static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |||
345 | } | 347 | } |
346 | #endif | 348 | #endif |
347 | 349 | ||
348 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
349 | static void bfin_serial_do_work(struct work_struct *work) | ||
350 | { | ||
351 | struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue); | ||
352 | |||
353 | bfin_serial_mctrl_check(uart); | ||
354 | } | ||
355 | #endif | ||
356 | |||
357 | #ifdef CONFIG_SERIAL_BFIN_DMA | 350 | #ifdef CONFIG_SERIAL_BFIN_DMA |
358 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | 351 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) |
359 | { | 352 | { |
@@ -361,6 +354,12 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |||
361 | 354 | ||
362 | uart->tx_done = 0; | 355 | uart->tx_done = 0; |
363 | 356 | ||
357 | /* | ||
358 | * Check the modem control lines before | ||
359 | * transmitting anything. | ||
360 | */ | ||
361 | bfin_serial_mctrl_check(uart); | ||
362 | |||
364 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { | 363 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
365 | uart->tx_count = 0; | 364 | uart->tx_count = 0; |
366 | uart->tx_done = 1; | 365 | uart->tx_done = 1; |
@@ -373,12 +372,6 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |||
373 | uart->port.x_char = 0; | 372 | uart->port.x_char = 0; |
374 | } | 373 | } |
375 | 374 | ||
376 | /* | ||
377 | * Check the modem control lines before | ||
378 | * transmitting anything. | ||
379 | */ | ||
380 | bfin_serial_mctrl_check(uart); | ||
381 | |||
382 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); | 375 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); |
383 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | 376 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) |
384 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | 377 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; |
@@ -565,7 +558,10 @@ static void bfin_serial_mctrl_check(struct bfin_serial_port *uart) | |||
565 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); | 558 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); |
566 | if (!(status & TIOCM_CTS)) { | 559 | if (!(status & TIOCM_CTS)) { |
567 | tty->hw_stopped = 1; | 560 | tty->hw_stopped = 1; |
568 | schedule_work(&uart->cts_workqueue); | 561 | uart->cts_timer.data = (unsigned long)(uart); |
562 | uart->cts_timer.function = (void *)bfin_serial_mctrl_check; | ||
563 | uart->cts_timer.expires = jiffies + CTS_CHECK_JIFFIES; | ||
564 | add_timer(&(uart->cts_timer)); | ||
569 | } else { | 565 | } else { |
570 | tty->hw_stopped = 0; | 566 | tty->hw_stopped = 0; |
571 | } | 567 | } |
@@ -885,7 +881,7 @@ static void __init bfin_serial_init_ports(void) | |||
885 | init_timer(&(bfin_serial_ports[i].rx_dma_timer)); | 881 | init_timer(&(bfin_serial_ports[i].rx_dma_timer)); |
886 | #endif | 882 | #endif |
887 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | 883 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
888 | INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work); | 884 | init_timer(&(bfin_serial_ports[i].cts_timer)); |
889 | bfin_serial_ports[i].cts_pin = | 885 | bfin_serial_ports[i].cts_pin = |
890 | bfin_serial_resource[i].uart_cts_pin; | 886 | bfin_serial_resource[i].uart_cts_pin; |
891 | bfin_serial_ports[i].rts_pin = | 887 | bfin_serial_ports[i].rts_pin = |
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 4b628526df09..a86e952ed4ca 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig | |||
@@ -12,3 +12,12 @@ menuconfig THERMAL | |||
12 | cooling devices. | 12 | cooling devices. |
13 | All platforms with ACPI thermal support can use this driver. | 13 | All platforms with ACPI thermal support can use this driver. |
14 | If you want this support, you should say Y or M here. | 14 | If you want this support, you should say Y or M here. |
15 | |||
16 | config THERMAL_HWMON | ||
17 | bool "Hardware monitoring support" | ||
18 | depends on HWMON=y || HWMON=THERMAL | ||
19 | help | ||
20 | The generic thermal sysfs driver's hardware monitoring support | ||
21 | requires a 2.10.7/3.0.2 or later lm-sensors userspace. | ||
22 | |||
23 | Say Y if your user-space is new enough. | ||
diff --git a/drivers/thermal/thermal_sys.c b/drivers/thermal/thermal_sys.c index 6098787341f3..fe07462d5947 100644 --- a/drivers/thermal/thermal_sys.c +++ b/drivers/thermal/thermal_sys.c | |||
@@ -295,8 +295,8 @@ thermal_cooling_device_trip_point_show(struct device *dev, | |||
295 | 295 | ||
296 | /* Device management */ | 296 | /* Device management */ |
297 | 297 | ||
298 | #if defined(CONFIG_HWMON) || \ | 298 | #if defined(CONFIG_THERMAL_HWMON) |
299 | (defined(CONFIG_HWMON_MODULE) && defined(CONFIG_THERMAL_MODULE)) | 299 | |
300 | /* hwmon sys I/F */ | 300 | /* hwmon sys I/F */ |
301 | #include <linux/hwmon.h> | 301 | #include <linux/hwmon.h> |
302 | static LIST_HEAD(thermal_hwmon_list); | 302 | static LIST_HEAD(thermal_hwmon_list); |
diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c index 3da1ab4b389d..c070b34b669d 100644 --- a/drivers/usb/core/quirks.c +++ b/drivers/usb/core/quirks.c | |||
@@ -47,6 +47,9 @@ static const struct usb_device_id usb_quirk_list[] = { | |||
47 | /* Edirol SD-20 */ | 47 | /* Edirol SD-20 */ |
48 | { USB_DEVICE(0x0582, 0x0027), .driver_info = USB_QUIRK_RESET_RESUME }, | 48 | { USB_DEVICE(0x0582, 0x0027), .driver_info = USB_QUIRK_RESET_RESUME }, |
49 | 49 | ||
50 | /* appletouch */ | ||
51 | { USB_DEVICE(0x05ac, 0x021a), .driver_info = USB_QUIRK_RESET_RESUME }, | ||
52 | |||
50 | /* Avision AV600U */ | 53 | /* Avision AV600U */ |
51 | { USB_DEVICE(0x0638, 0x0a13), .driver_info = | 54 | { USB_DEVICE(0x0638, 0x0a13), .driver_info = |
52 | USB_QUIRK_STRING_FETCH_255 }, | 55 | USB_QUIRK_STRING_FETCH_255 }, |
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 7dcda187d9ba..fafe7db20d6d 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c | |||
@@ -1246,7 +1246,7 @@ static int pxafb_resume(struct platform_device *dev) | |||
1246 | * cache. Once this area is remapped, all virtual memory | 1246 | * cache. Once this area is remapped, all virtual memory |
1247 | * access to the video memory should occur at the new region. | 1247 | * access to the video memory should occur at the new region. |
1248 | */ | 1248 | */ |
1249 | static int __init pxafb_map_video_memory(struct pxafb_info *fbi) | 1249 | static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi) |
1250 | { | 1250 | { |
1251 | /* | 1251 | /* |
1252 | * We reserve one page for the palette, plus the size | 1252 | * We reserve one page for the palette, plus the size |
@@ -1348,7 +1348,7 @@ decode_mode: | |||
1348 | pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes); | 1348 | pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes); |
1349 | } | 1349 | } |
1350 | 1350 | ||
1351 | static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev) | 1351 | static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev) |
1352 | { | 1352 | { |
1353 | struct pxafb_info *fbi; | 1353 | struct pxafb_info *fbi; |
1354 | void *addr; | 1354 | void *addr; |
@@ -1410,7 +1410,7 @@ static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev) | |||
1410 | } | 1410 | } |
1411 | 1411 | ||
1412 | #ifdef CONFIG_FB_PXA_PARAMETERS | 1412 | #ifdef CONFIG_FB_PXA_PARAMETERS |
1413 | static int __init parse_opt_mode(struct device *dev, const char *this_opt) | 1413 | static int __devinit parse_opt_mode(struct device *dev, const char *this_opt) |
1414 | { | 1414 | { |
1415 | struct pxafb_mach_info *inf = dev->platform_data; | 1415 | struct pxafb_mach_info *inf = dev->platform_data; |
1416 | 1416 | ||
@@ -1469,7 +1469,7 @@ done: | |||
1469 | return 0; | 1469 | return 0; |
1470 | } | 1470 | } |
1471 | 1471 | ||
1472 | static int __init parse_opt(struct device *dev, char *this_opt) | 1472 | static int __devinit parse_opt(struct device *dev, char *this_opt) |
1473 | { | 1473 | { |
1474 | struct pxafb_mach_info *inf = dev->platform_data; | 1474 | struct pxafb_mach_info *inf = dev->platform_data; |
1475 | struct pxafb_mode_info *mode = &inf->modes[0]; | 1475 | struct pxafb_mode_info *mode = &inf->modes[0]; |
@@ -1567,7 +1567,7 @@ static int __init parse_opt(struct device *dev, char *this_opt) | |||
1567 | return 0; | 1567 | return 0; |
1568 | } | 1568 | } |
1569 | 1569 | ||
1570 | static int __init pxafb_parse_options(struct device *dev, char *options) | 1570 | static int __devinit pxafb_parse_options(struct device *dev, char *options) |
1571 | { | 1571 | { |
1572 | char *this_opt; | 1572 | char *this_opt; |
1573 | int ret; | 1573 | int ret; |
@@ -1588,8 +1588,8 @@ static int __init pxafb_parse_options(struct device *dev, char *options) | |||
1588 | 1588 | ||
1589 | static char g_options[256] __devinitdata = ""; | 1589 | static char g_options[256] __devinitdata = ""; |
1590 | 1590 | ||
1591 | #ifndef CONFIG_MODULES | 1591 | #ifndef MODULE |
1592 | static int __devinit pxafb_setup_options(void) | 1592 | static int __init pxafb_setup_options(void) |
1593 | { | 1593 | { |
1594 | char *options = NULL; | 1594 | char *options = NULL; |
1595 | 1595 | ||
@@ -1613,7 +1613,7 @@ MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)"); | |||
1613 | #define pxafb_setup_options() (0) | 1613 | #define pxafb_setup_options() (0) |
1614 | #endif | 1614 | #endif |
1615 | 1615 | ||
1616 | static int __init pxafb_probe(struct platform_device *dev) | 1616 | static int __devinit pxafb_probe(struct platform_device *dev) |
1617 | { | 1617 | { |
1618 | struct pxafb_info *fbi; | 1618 | struct pxafb_info *fbi; |
1619 | struct pxafb_mach_info *inf; | 1619 | struct pxafb_mach_info *inf; |
@@ -1685,14 +1685,14 @@ static int __init pxafb_probe(struct platform_device *dev) | |||
1685 | if (r == NULL) { | 1685 | if (r == NULL) { |
1686 | dev_err(&dev->dev, "no I/O memory resource defined\n"); | 1686 | dev_err(&dev->dev, "no I/O memory resource defined\n"); |
1687 | ret = -ENODEV; | 1687 | ret = -ENODEV; |
1688 | goto failed; | 1688 | goto failed_fbi; |
1689 | } | 1689 | } |
1690 | 1690 | ||
1691 | r = request_mem_region(r->start, r->end - r->start + 1, dev->name); | 1691 | r = request_mem_region(r->start, r->end - r->start + 1, dev->name); |
1692 | if (r == NULL) { | 1692 | if (r == NULL) { |
1693 | dev_err(&dev->dev, "failed to request I/O memory\n"); | 1693 | dev_err(&dev->dev, "failed to request I/O memory\n"); |
1694 | ret = -EBUSY; | 1694 | ret = -EBUSY; |
1695 | goto failed; | 1695 | goto failed_fbi; |
1696 | } | 1696 | } |
1697 | 1697 | ||
1698 | fbi->mmio_base = ioremap(r->start, r->end - r->start + 1); | 1698 | fbi->mmio_base = ioremap(r->start, r->end - r->start + 1); |
@@ -1735,8 +1735,17 @@ static int __init pxafb_probe(struct platform_device *dev) | |||
1735 | * This makes sure that our colour bitfield | 1735 | * This makes sure that our colour bitfield |
1736 | * descriptors are correctly initialised. | 1736 | * descriptors are correctly initialised. |
1737 | */ | 1737 | */ |
1738 | pxafb_check_var(&fbi->fb.var, &fbi->fb); | 1738 | ret = pxafb_check_var(&fbi->fb.var, &fbi->fb); |
1739 | pxafb_set_par(&fbi->fb); | 1739 | if (ret) { |
1740 | dev_err(&dev->dev, "failed to get suitable mode\n"); | ||
1741 | goto failed_free_irq; | ||
1742 | } | ||
1743 | |||
1744 | ret = pxafb_set_par(&fbi->fb); | ||
1745 | if (ret) { | ||
1746 | dev_err(&dev->dev, "Failed to set parameters\n"); | ||
1747 | goto failed_free_irq; | ||
1748 | } | ||
1740 | 1749 | ||
1741 | platform_set_drvdata(dev, fbi); | 1750 | platform_set_drvdata(dev, fbi); |
1742 | 1751 | ||
@@ -1744,7 +1753,7 @@ static int __init pxafb_probe(struct platform_device *dev) | |||
1744 | if (ret < 0) { | 1753 | if (ret < 0) { |
1745 | dev_err(&dev->dev, | 1754 | dev_err(&dev->dev, |
1746 | "Failed to register framebuffer device: %d\n", ret); | 1755 | "Failed to register framebuffer device: %d\n", ret); |
1747 | goto failed_free_irq; | 1756 | goto failed_free_cmap; |
1748 | } | 1757 | } |
1749 | 1758 | ||
1750 | #ifdef CONFIG_CPU_FREQ | 1759 | #ifdef CONFIG_CPU_FREQ |
@@ -1763,18 +1772,23 @@ static int __init pxafb_probe(struct platform_device *dev) | |||
1763 | 1772 | ||
1764 | return 0; | 1773 | return 0; |
1765 | 1774 | ||
1775 | failed_free_cmap: | ||
1776 | if (fbi->fb.cmap.len) | ||
1777 | fb_dealloc_cmap(&fbi->fb.cmap); | ||
1766 | failed_free_irq: | 1778 | failed_free_irq: |
1767 | free_irq(irq, fbi); | 1779 | free_irq(irq, fbi); |
1768 | failed_free_res: | ||
1769 | release_mem_region(r->start, r->end - r->start + 1); | ||
1770 | failed_free_io: | ||
1771 | iounmap(fbi->mmio_base); | ||
1772 | failed_free_mem: | 1780 | failed_free_mem: |
1773 | dma_free_writecombine(&dev->dev, fbi->map_size, | 1781 | dma_free_writecombine(&dev->dev, fbi->map_size, |
1774 | fbi->map_cpu, fbi->map_dma); | 1782 | fbi->map_cpu, fbi->map_dma); |
1775 | failed: | 1783 | failed_free_io: |
1784 | iounmap(fbi->mmio_base); | ||
1785 | failed_free_res: | ||
1786 | release_mem_region(r->start, r->end - r->start + 1); | ||
1787 | failed_fbi: | ||
1788 | clk_put(fbi->clk); | ||
1776 | platform_set_drvdata(dev, NULL); | 1789 | platform_set_drvdata(dev, NULL); |
1777 | kfree(fbi); | 1790 | kfree(fbi); |
1791 | failed: | ||
1778 | return ret; | 1792 | return ret; |
1779 | } | 1793 | } |
1780 | 1794 | ||
@@ -1787,7 +1801,7 @@ static struct platform_driver pxafb_driver = { | |||
1787 | }, | 1801 | }, |
1788 | }; | 1802 | }; |
1789 | 1803 | ||
1790 | static int __devinit pxafb_init(void) | 1804 | static int __init pxafb_init(void) |
1791 | { | 1805 | { |
1792 | if (pxafb_setup_options()) | 1806 | if (pxafb_setup_options()) |
1793 | return -EINVAL; | 1807 | return -EINVAL; |
diff --git a/drivers/virtio/virtio.c b/drivers/virtio/virtio.c index 0f3c2bb7bf35..7084e7e146c0 100644 --- a/drivers/virtio/virtio.c +++ b/drivers/virtio/virtio.c | |||
@@ -124,9 +124,9 @@ static int virtio_dev_probe(struct device *_d) | |||
124 | if (err) | 124 | if (err) |
125 | add_status(dev, VIRTIO_CONFIG_S_FAILED); | 125 | add_status(dev, VIRTIO_CONFIG_S_FAILED); |
126 | else { | 126 | else { |
127 | add_status(dev, VIRTIO_CONFIG_S_DRIVER_OK); | ||
128 | /* They should never have set feature bits beyond 32 */ | 127 | /* They should never have set feature bits beyond 32 */ |
129 | dev->config->set_features(dev, dev->features[0]); | 128 | dev->config->set_features(dev, dev->features[0]); |
129 | add_status(dev, VIRTIO_CONFIG_S_DRIVER_OK); | ||
130 | } | 130 | } |
131 | return err; | 131 | return err; |
132 | } | 132 | } |
diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c index 6a63535fc04d..eaa3f2a79ff5 100644 --- a/drivers/watchdog/hpwdt.c +++ b/drivers/watchdog/hpwdt.c | |||
@@ -140,49 +140,53 @@ static struct pci_device_id hpwdt_devices[] = { | |||
140 | }; | 140 | }; |
141 | MODULE_DEVICE_TABLE(pci, hpwdt_devices); | 141 | MODULE_DEVICE_TABLE(pci, hpwdt_devices); |
142 | 142 | ||
143 | extern asmlinkage void asminline_call(struct cmn_registers *pi86Regs, unsigned long *pRomEntry); | ||
144 | |||
143 | #ifndef CONFIG_X86_64 | 145 | #ifndef CONFIG_X86_64 |
144 | /* --32 Bit Bios------------------------------------------------------------ */ | 146 | /* --32 Bit Bios------------------------------------------------------------ */ |
145 | 147 | ||
146 | #define HPWDT_ARCH 32 | 148 | #define HPWDT_ARCH 32 |
147 | 149 | ||
148 | static void asminline_call(struct cmn_registers *pi86Regs, | 150 | asm(".text \n\t" |
149 | unsigned long *pRomEntry) | 151 | ".align 4 \n" |
150 | { | 152 | "asminline_call: \n\t" |
151 | asm("pushl %ebp \n\t" | 153 | "pushl %ebp \n\t" |
152 | "movl %esp, %ebp \n\t" | 154 | "movl %esp, %ebp \n\t" |
153 | "pusha \n\t" | 155 | "pusha \n\t" |
154 | "pushf \n\t" | 156 | "pushf \n\t" |
155 | "push %es \n\t" | 157 | "push %es \n\t" |
156 | "push %ds \n\t" | 158 | "push %ds \n\t" |
157 | "pop %es \n\t" | 159 | "pop %es \n\t" |
158 | "movl 8(%ebp),%eax \n\t" | 160 | "movl 8(%ebp),%eax \n\t" |
159 | "movl 4(%eax),%ebx \n\t" | 161 | "movl 4(%eax),%ebx \n\t" |
160 | "movl 8(%eax),%ecx \n\t" | 162 | "movl 8(%eax),%ecx \n\t" |
161 | "movl 12(%eax),%edx \n\t" | 163 | "movl 12(%eax),%edx \n\t" |
162 | "movl 16(%eax),%esi \n\t" | 164 | "movl 16(%eax),%esi \n\t" |
163 | "movl 20(%eax),%edi \n\t" | 165 | "movl 20(%eax),%edi \n\t" |
164 | "movl (%eax),%eax \n\t" | 166 | "movl (%eax),%eax \n\t" |
165 | "push %cs \n\t" | 167 | "push %cs \n\t" |
166 | "call *12(%ebp) \n\t" | 168 | "call *12(%ebp) \n\t" |
167 | "pushf \n\t" | 169 | "pushf \n\t" |
168 | "pushl %eax \n\t" | 170 | "pushl %eax \n\t" |
169 | "movl 8(%ebp),%eax \n\t" | 171 | "movl 8(%ebp),%eax \n\t" |
170 | "movl %ebx,4(%eax) \n\t" | 172 | "movl %ebx,4(%eax) \n\t" |
171 | "movl %ecx,8(%eax) \n\t" | 173 | "movl %ecx,8(%eax) \n\t" |
172 | "movl %edx,12(%eax) \n\t" | 174 | "movl %edx,12(%eax) \n\t" |
173 | "movl %esi,16(%eax) \n\t" | 175 | "movl %esi,16(%eax) \n\t" |
174 | "movl %edi,20(%eax) \n\t" | 176 | "movl %edi,20(%eax) \n\t" |
175 | "movw %ds,24(%eax) \n\t" | 177 | "movw %ds,24(%eax) \n\t" |
176 | "movw %es,26(%eax) \n\t" | 178 | "movw %es,26(%eax) \n\t" |
177 | "popl %ebx \n\t" | 179 | "popl %ebx \n\t" |
178 | "movl %ebx,(%eax) \n\t" | 180 | "movl %ebx,(%eax) \n\t" |
179 | "popl %ebx \n\t" | 181 | "popl %ebx \n\t" |
180 | "movl %ebx,28(%eax) \n\t" | 182 | "movl %ebx,28(%eax) \n\t" |
181 | "pop %es \n\t" | 183 | "pop %es \n\t" |
182 | "popf \n\t" | 184 | "popf \n\t" |
183 | "popa \n\t" | 185 | "popa \n\t" |
184 | "leave \n\t" "ret"); | 186 | "leave \n\t" |
185 | } | 187 | "ret \n\t" |
188 | ".previous"); | ||
189 | |||
186 | 190 | ||
187 | /* | 191 | /* |
188 | * cru_detect | 192 | * cru_detect |
@@ -333,43 +337,44 @@ static int __devinit detect_cru_service(void) | |||
333 | 337 | ||
334 | #define HPWDT_ARCH 64 | 338 | #define HPWDT_ARCH 64 |
335 | 339 | ||
336 | static void asminline_call(struct cmn_registers *pi86Regs, | 340 | asm(".text \n\t" |
337 | unsigned long *pRomEntry) | 341 | ".align 4 \n" |
338 | { | 342 | "asminline_call: \n\t" |
339 | asm("pushq %rbp \n\t" | 343 | "pushq %rbp \n\t" |
340 | "movq %rsp, %rbp \n\t" | 344 | "movq %rsp, %rbp \n\t" |
341 | "pushq %rax \n\t" | 345 | "pushq %rax \n\t" |
342 | "pushq %rbx \n\t" | 346 | "pushq %rbx \n\t" |
343 | "pushq %rdx \n\t" | 347 | "pushq %rdx \n\t" |
344 | "pushq %r12 \n\t" | 348 | "pushq %r12 \n\t" |
345 | "pushq %r9 \n\t" | 349 | "pushq %r9 \n\t" |
346 | "movq %rsi, %r12 \n\t" | 350 | "movq %rsi, %r12 \n\t" |
347 | "movq %rdi, %r9 \n\t" | 351 | "movq %rdi, %r9 \n\t" |
348 | "movl 4(%r9),%ebx \n\t" | 352 | "movl 4(%r9),%ebx \n\t" |
349 | "movl 8(%r9),%ecx \n\t" | 353 | "movl 8(%r9),%ecx \n\t" |
350 | "movl 12(%r9),%edx \n\t" | 354 | "movl 12(%r9),%edx \n\t" |
351 | "movl 16(%r9),%esi \n\t" | 355 | "movl 16(%r9),%esi \n\t" |
352 | "movl 20(%r9),%edi \n\t" | 356 | "movl 20(%r9),%edi \n\t" |
353 | "movl (%r9),%eax \n\t" | 357 | "movl (%r9),%eax \n\t" |
354 | "call *%r12 \n\t" | 358 | "call *%r12 \n\t" |
355 | "pushfq \n\t" | 359 | "pushfq \n\t" |
356 | "popq %r12 \n\t" | 360 | "popq %r12 \n\t" |
357 | "popfq \n\t" | 361 | "popfq \n\t" |
358 | "movl %eax, (%r9) \n\t" | 362 | "movl %eax, (%r9) \n\t" |
359 | "movl %ebx, 4(%r9) \n\t" | 363 | "movl %ebx, 4(%r9) \n\t" |
360 | "movl %ecx, 8(%r9) \n\t" | 364 | "movl %ecx, 8(%r9) \n\t" |
361 | "movl %edx, 12(%r9) \n\t" | 365 | "movl %edx, 12(%r9) \n\t" |
362 | "movl %esi, 16(%r9) \n\t" | 366 | "movl %esi, 16(%r9) \n\t" |
363 | "movl %edi, 20(%r9) \n\t" | 367 | "movl %edi, 20(%r9) \n\t" |
364 | "movq %r12, %rax \n\t" | 368 | "movq %r12, %rax \n\t" |
365 | "movl %eax, 28(%r9) \n\t" | 369 | "movl %eax, 28(%r9) \n\t" |
366 | "popq %r9 \n\t" | 370 | "popq %r9 \n\t" |
367 | "popq %r12 \n\t" | 371 | "popq %r12 \n\t" |
368 | "popq %rdx \n\t" | 372 | "popq %rdx \n\t" |
369 | "popq %rbx \n\t" | 373 | "popq %rbx \n\t" |
370 | "popq %rax \n\t" | 374 | "popq %rax \n\t" |
371 | "leave \n\t" "ret"); | 375 | "leave \n\t" |
372 | } | 376 | "ret \n\t" |
377 | ".previous"); | ||
373 | 378 | ||
374 | /* | 379 | /* |
375 | * dmi_find_cru | 380 | * dmi_find_cru |
@@ -418,20 +423,23 @@ static int hpwdt_pretimeout(struct notifier_block *nb, unsigned long ulReason, | |||
418 | static unsigned long rom_pl; | 423 | static unsigned long rom_pl; |
419 | static int die_nmi_called; | 424 | static int die_nmi_called; |
420 | 425 | ||
421 | if (ulReason == DIE_NMI || ulReason == DIE_NMI_IPI) { | 426 | if (ulReason != DIE_NMI && ulReason != DIE_NMI_IPI) |
422 | spin_lock_irqsave(&rom_lock, rom_pl); | 427 | return NOTIFY_OK; |
423 | if (!die_nmi_called) | 428 | |
424 | asminline_call(&cmn_regs, cru_rom_addr); | 429 | spin_lock_irqsave(&rom_lock, rom_pl); |
425 | die_nmi_called = 1; | 430 | if (!die_nmi_called) |
426 | spin_unlock_irqrestore(&rom_lock, rom_pl); | 431 | asminline_call(&cmn_regs, cru_rom_addr); |
427 | if (cmn_regs.u1.ral != 0) { | 432 | die_nmi_called = 1; |
428 | panic("An NMI occurred, please see the Integrated " | 433 | spin_unlock_irqrestore(&rom_lock, rom_pl); |
429 | "Management Log for details.\n"); | 434 | if (cmn_regs.u1.ral == 0) { |
430 | } | 435 | printk(KERN_WARNING "hpwdt: An NMI occurred, " |
436 | "but unable to determine source.\n"); | ||
437 | } else { | ||
438 | panic("An NMI occurred, please see the Integrated " | ||
439 | "Management Log for details.\n"); | ||
431 | } | 440 | } |
432 | 441 | ||
433 | die_nmi_called = 0; | 442 | return NOTIFY_STOP; |
434 | return NOTIFY_DONE; | ||
435 | } | 443 | } |
436 | 444 | ||
437 | /* | 445 | /* |
diff --git a/drivers/xen/events.c b/drivers/xen/events.c index 4f0f22b020ea..76e5b7386af9 100644 --- a/drivers/xen/events.c +++ b/drivers/xen/events.c | |||
@@ -529,7 +529,7 @@ void xen_evtchn_do_upcall(struct pt_regs *regs) | |||
529 | 529 | ||
530 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ | 530 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
531 | /* Clear master flag /before/ clearing selector flag. */ | 531 | /* Clear master flag /before/ clearing selector flag. */ |
532 | rmb(); | 532 | wmb(); |
533 | #endif | 533 | #endif |
534 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); | 534 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
535 | while (pending_words != 0) { | 535 | while (pending_words != 0) { |