diff options
author | Florian Fainelli <florian.fainelli@telecomint.eu> | 2008-07-13 08:34:15 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@redhat.com> | 2008-07-22 19:59:35 -0400 |
commit | 32f565df9ba451a24117db67003ed2ae21bab88c (patch) | |
tree | 4d464ef718ac064b3ca2ecadbe69a2b96670e0ea /drivers | |
parent | 9ca28dc4c75f018201e21b10e34b8161bcb0ffb2 (diff) |
r6040: use definitions for magic values in descriptor status
Define all the descriptor status the MAC can set.
Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/r6040.c | 37 |
1 files changed, 26 insertions, 11 deletions
diff --git a/drivers/net/r6040.c b/drivers/net/r6040.c index 9061ec1aa4f7..973f1e81667a 100644 --- a/drivers/net/r6040.c +++ b/drivers/net/r6040.c | |||
@@ -138,6 +138,21 @@ | |||
138 | #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */ | 138 | #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */ |
139 | #define MCAST_MAX 4 /* Max number multicast addresses to filter */ | 139 | #define MCAST_MAX 4 /* Max number multicast addresses to filter */ |
140 | 140 | ||
141 | /* Descriptor status */ | ||
142 | #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */ | ||
143 | #define DSC_RX_OK 0x4000 /* RX was successful */ | ||
144 | #define DSC_RX_ERR 0x0800 /* RX PHY error */ | ||
145 | #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */ | ||
146 | #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */ | ||
147 | #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */ | ||
148 | #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */ | ||
149 | #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */ | ||
150 | #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */ | ||
151 | #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */ | ||
152 | #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */ | ||
153 | #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */ | ||
154 | #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */ | ||
155 | |||
141 | /* PHY settings */ | 156 | /* PHY settings */ |
142 | #define ICPLUS_PHY_ID 0x0243 | 157 | #define ICPLUS_PHY_ID 0x0243 |
143 | 158 | ||
@@ -324,7 +339,7 @@ static int r6040_alloc_rxbufs(struct net_device *dev) | |||
324 | desc->buf = cpu_to_le32(pci_map_single(lp->pdev, | 339 | desc->buf = cpu_to_le32(pci_map_single(lp->pdev, |
325 | desc->skb_ptr->data, | 340 | desc->skb_ptr->data, |
326 | MAX_BUF_SIZE, PCI_DMA_FROMDEVICE)); | 341 | MAX_BUF_SIZE, PCI_DMA_FROMDEVICE)); |
327 | desc->status = 0x8000; | 342 | desc->status = DSC_OWNER_MAC; |
328 | desc = desc->vndescp; | 343 | desc = desc->vndescp; |
329 | } while (desc != lp->rx_ring); | 344 | } while (desc != lp->rx_ring); |
330 | 345 | ||
@@ -541,25 +556,25 @@ static int r6040_rx(struct net_device *dev, int limit) | |||
541 | u16 err; | 556 | u16 err; |
542 | 557 | ||
543 | /* Limit not reached and the descriptor belongs to the CPU */ | 558 | /* Limit not reached and the descriptor belongs to the CPU */ |
544 | while (count < limit && !(descptr->status & 0x8000)) { | 559 | while (count < limit && !(descptr->status & DSC_OWNER_MAC)) { |
545 | /* Read the descriptor status */ | 560 | /* Read the descriptor status */ |
546 | err = descptr->status; | 561 | err = descptr->status; |
547 | /* Global error status set */ | 562 | /* Global error status set */ |
548 | if (err & 0x0800) { | 563 | if (err & DSC_RX_ERR) { |
549 | /* RX dribble */ | 564 | /* RX dribble */ |
550 | if (err & 0x0400) | 565 | if (err & DSC_RX_ERR_DRI) |
551 | dev->stats.rx_frame_errors++; | 566 | dev->stats.rx_frame_errors++; |
552 | /* Buffer lenght exceeded */ | 567 | /* Buffer lenght exceeded */ |
553 | if (err & 0x0200) | 568 | if (err & DSC_RX_ERR_BUF) |
554 | dev->stats.rx_length_errors++; | 569 | dev->stats.rx_length_errors++; |
555 | /* Packet too long */ | 570 | /* Packet too long */ |
556 | if (err & 0x0100) | 571 | if (err & DSC_RX_ERR_LONG) |
557 | dev->stats.rx_length_errors++; | 572 | dev->stats.rx_length_errors++; |
558 | /* Packet < 64 bytes */ | 573 | /* Packet < 64 bytes */ |
559 | if (err & 0x0080) | 574 | if (err & DSC_RX_ERR_RUNT) |
560 | dev->stats.rx_length_errors++; | 575 | dev->stats.rx_length_errors++; |
561 | /* CRC error */ | 576 | /* CRC error */ |
562 | if (err & 0x0040) { | 577 | if (err & DSC_RX_ERR_CRC) { |
563 | spin_lock(&priv->lock); | 578 | spin_lock(&priv->lock); |
564 | dev->stats.rx_crc_errors++; | 579 | dev->stats.rx_crc_errors++; |
565 | spin_unlock(&priv->lock); | 580 | spin_unlock(&priv->lock); |
@@ -596,7 +611,7 @@ static int r6040_rx(struct net_device *dev, int limit) | |||
596 | 611 | ||
597 | next_descr: | 612 | next_descr: |
598 | /* put the descriptor back to the MAC */ | 613 | /* put the descriptor back to the MAC */ |
599 | descptr->status = 0x8000; | 614 | descptr->status = DSC_OWNER_MAC; |
600 | descptr = descptr->vndescp; | 615 | descptr = descptr->vndescp; |
601 | count++; | 616 | count++; |
602 | } | 617 | } |
@@ -624,7 +639,7 @@ static void r6040_tx(struct net_device *dev) | |||
624 | if (err & (0x2000 | 0x4000)) | 639 | if (err & (0x2000 | 0x4000)) |
625 | dev->stats.tx_carrier_errors++; | 640 | dev->stats.tx_carrier_errors++; |
626 | 641 | ||
627 | if (descptr->status & 0x8000) | 642 | if (descptr->status & DSC_OWNER_MAC) |
628 | break; /* Not complete */ | 643 | break; /* Not complete */ |
629 | skb_ptr = descptr->skb_ptr; | 644 | skb_ptr = descptr->skb_ptr; |
630 | pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf), | 645 | pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf), |
@@ -874,7 +889,7 @@ static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
874 | descptr->skb_ptr = skb; | 889 | descptr->skb_ptr = skb; |
875 | descptr->buf = cpu_to_le32(pci_map_single(lp->pdev, | 890 | descptr->buf = cpu_to_le32(pci_map_single(lp->pdev, |
876 | skb->data, skb->len, PCI_DMA_TODEVICE)); | 891 | skb->data, skb->len, PCI_DMA_TODEVICE)); |
877 | descptr->status = 0x8000; | 892 | descptr->status = DSC_OWNER_MAC; |
878 | /* Trigger the MAC to check the TX descriptor */ | 893 | /* Trigger the MAC to check the TX descriptor */ |
879 | iowrite16(0x01, ioaddr + MTPR); | 894 | iowrite16(0x01, ioaddr + MTPR); |
880 | lp->tx_insert_ptr = descptr->vndescp; | 895 | lp->tx_insert_ptr = descptr->vndescp; |