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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2007-02-07 12:18:11 -0500
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-02-07 12:18:11 -0500
commit26ccb802ee3f9a1f1fd5bc6abf38f124bfbd9cb2 (patch)
tree3403058200cf6d4a8eb9bfbdea3de38ad799d648 /drivers
parentabc4ad4c6b3c6a51a0aa633e3d3fbc80b0ecabfe (diff)
hpt366: merge HPT37x speedproc handlers
Continue with the driver rewrite: - move the interrupt twiddling code from the speedproc handlers into the init_hwif_hpt366 which allows to merge the two HPT37x speedproc handlers into one; - get rid of in init_hpt366 which solely consists of the duplicate code, then fold init_hpt37x() into init_chipset_hpt366(); - fix hpt3xx_tune_drive() to always set the PIO mode requested, not the best possible one, change hpt366_config_drive_xfer_rate() accordingly, simplify it a bit; - group all the DMA related code together init_hwif_hpt366(), and generally clean up and beautify it. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ide/pci/hpt366.c258
1 files changed, 88 insertions, 170 deletions
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index fd15329d953f..7317defd8210 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/hpt366.c Version 0.50 May 28, 2006 2 * linux/drivers/ide/pci/hpt366.c Version 0.51 Jun 04, 2006
3 * 3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
@@ -83,13 +83,16 @@
83 * - cache the channel's MCRs' offset; only touch the relevant MCR when detecting 83 * - cache the channel's MCRs' offset; only touch the relevant MCR when detecting
84 * the cable type on HPT374's function 1 84 * the cable type on HPT374's function 1
85 * - rename all the register related variables consistently 85 * - rename all the register related variables consistently
86 * - make HPT36x's speedproc handler look the same way as HPT37x ones; fix the 86 * - move the interrupt twiddling code from the speedproc handlers into the
87 * PIO timing register mask for HPT37x 87 * init_hwif handler, also grouping all the DMA related code together there;
88 * simplify the init_chipset handler
89 * - merge two HPT37x speedproc handlers and fix the PIO timing register mask
90 * there; make HPT36x speedproc handler look the same way as the HPT37x one
91 * - fix the tuneproc handler to always set the PIO mode requested, not the
92 * best possible one
88 * <source@mvista.com> 93 * <source@mvista.com>
89 *
90 */ 94 */
91 95
92
93#include <linux/types.h> 96#include <linux/types.h>
94#include <linux/module.h> 97#include <linux/module.h>
95#include <linux/kernel.h> 98#include <linux/kernel.h>
@@ -507,19 +510,9 @@ static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
507 struct hpt_info *info = ide_get_hwifdata (hwif); 510 struct hpt_info *info = ide_get_hwifdata (hwif);
508 u8 speed = hpt3xx_ratefilter(drive, xferspeed); 511 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
509 u8 itr_addr = drive->dn ? 0x44 : 0x40; 512 u8 itr_addr = drive->dn ? 0x44 : 0x40;
510 u8 mcr_addr = hwif->select_data + 1;
511 u8 mcr = 0;
512 u32 new_itr, old_itr = 0;
513 u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x30070000 : 0xc0000000; 513 u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x30070000 : 0xc0000000;
514 514 u32 new_itr = pci_bus_clock_list(speed, info->speed);
515 /* 515 u32 old_itr = 0;
516 * Disable the "fast interrupt" prediction.
517 */
518 pci_read_config_byte(dev, mcr_addr, &mcr);
519 if (mcr & 0x80)
520 pci_write_config_byte(dev, mcr_addr, mcr & ~0x80);
521
522 new_itr = pci_bus_clock_list(speed, info->speed);
523 516
524 /* 517 /*
525 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) 518 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
@@ -534,38 +527,16 @@ static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
534 return ide_config_drive_speed(drive, speed); 527 return ide_config_drive_speed(drive, speed);
535} 528}
536 529
537static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed) 530static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
538{ 531{
539 ide_hwif_t *hwif = HWIF(drive); 532 ide_hwif_t *hwif = HWIF(drive);
540 struct pci_dev *dev = hwif->pci_dev; 533 struct pci_dev *dev = hwif->pci_dev;
541 struct hpt_info *info = ide_get_hwifdata (hwif); 534 struct hpt_info *info = ide_get_hwifdata (hwif);
542 u8 speed = hpt3xx_ratefilter(drive, xferspeed); 535 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
543 u8 mcr_addr = hwif->select_data + 1;
544 u8 itr_addr = 0x40 + (drive->dn * 4); 536 u8 itr_addr = 0x40 + (drive->dn * 4);
545 u8 new_mcr = 0, old_mcr = 0;
546 u32 new_itr, old_itr = 0;
547 u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000; 537 u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000;
548 538 u32 new_itr = pci_bus_clock_list(speed, info->speed);
549 /* 539 u32 old_itr = 0;
550 * Disable the "fast interrupt" prediction.
551 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
552 */
553 pci_read_config_byte(dev, mcr_addr, &old_mcr);
554 new_mcr = old_mcr;
555 if (new_mcr & 0x02)
556 new_mcr &= ~0x02;
557
558#ifdef HPT_DELAY_INTERRUPT
559 if (new_mcr & 0x01)
560 new_mcr &= ~0x01;
561#else
562 if ((new_mcr & 0x01) == 0)
563 new_mcr |= 0x01;
564#endif
565 if (new_mcr != old_mcr)
566 pci_write_config_byte(dev, mcr_addr, new_mcr);
567
568 new_itr = pci_bus_clock_list(speed, info->speed);
569 540
570 pci_read_config_dword(dev, itr_addr, &old_itr); 541 pci_read_config_dword(dev, itr_addr, &old_itr);
571 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask); 542 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
@@ -577,71 +548,34 @@ static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
577 return ide_config_drive_speed(drive, speed); 548 return ide_config_drive_speed(drive, speed);
578} 549}
579 550
580static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed) 551static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
581{ 552{
582 ide_hwif_t *hwif = HWIF(drive); 553 ide_hwif_t *hwif = HWIF(drive);
583 struct pci_dev *dev = hwif->pci_dev;
584 struct hpt_info *info = ide_get_hwifdata (hwif);
585 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
586 u8 mcr_addr = hwif->select_data + 1;
587 u8 itr_addr = 0x40 + (drive->dn * 4);
588 u8 mcr = 0;
589 u32 new_itr, old_itr = 0;
590 u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000;
591
592 /*
593 * Disable the "fast interrupt" prediction.
594 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
595 */
596 pci_read_config_byte (dev, mcr_addr, &mcr);
597 pci_write_config_byte(dev, mcr_addr, (mcr & ~0x07));
598
599 new_itr = pci_bus_clock_list(speed, info->speed);
600 pci_read_config_dword(dev, itr_addr, &old_itr);
601 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
602 if (speed < XFER_MW_DMA_0)
603 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
604 pci_write_config_dword(dev, itr_addr, new_itr);
605
606 return ide_config_drive_speed(drive, speed);
607}
608
609static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
610{
611 ide_hwif_t *hwif = drive->hwif;
612 struct hpt_info *info = ide_get_hwifdata(hwif); 554 struct hpt_info *info = ide_get_hwifdata(hwif);
613 555
614 if (info->revision >= 8) 556 if (info->revision >= 3)
615 return hpt372_tune_chipset(drive, speed); /* not a typo */ 557 return hpt37x_tune_chipset(drive, speed);
616 else if (info->revision >= 5)
617 return hpt372_tune_chipset(drive, speed);
618 else if (info->revision >= 3)
619 return hpt370_tune_chipset(drive, speed);
620 else /* hpt368: hpt_minimum_revision(dev, 2) */ 558 else /* hpt368: hpt_minimum_revision(dev, 2) */
621 return hpt36x_tune_chipset(drive, speed); 559 return hpt36x_tune_chipset(drive, speed);
622} 560}
623 561
624static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio) 562static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
625{ 563{
626 pio = ide_get_best_pio_mode(drive, 255, pio, NULL); 564 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
627 (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio)); 565 (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
628} 566}
629 567
630/* 568/*
631 * This allows the configuration of ide_pci chipset registers 569 * This allows the configuration of ide_pci chipset registers
632 * for cards that learn about the drive's UDMA, DMA, PIO capabilities 570 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
633 * after the drive is reported by the OS. Initially for designed for 571 * after the drive is reported by the OS. Initially designed for
634 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc. 572 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
635 * 573 *
636 * check_in_drive_lists(drive, bad_ata66_4)
637 * check_in_drive_lists(drive, bad_ata66_3)
638 * check_in_drive_lists(drive, bad_ata33)
639 *
640 */ 574 */
641static int config_chipset_for_dma (ide_drive_t *drive) 575static int config_chipset_for_dma(ide_drive_t *drive)
642{ 576{
643 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive)); 577 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
644 ide_hwif_t *hwif = drive->hwif; 578 ide_hwif_t *hwif = HWIF(drive);
645 struct hpt_info *info = ide_get_hwifdata(hwif); 579 struct hpt_info *info = ide_get_hwifdata(hwif);
646 580
647 if (!speed) 581 if (!speed)
@@ -666,7 +600,7 @@ static int hpt3xx_quirkproc(ide_drive_t *drive)
666 return 0; 600 return 0;
667} 601}
668 602
669static void hpt3xx_intrproc (ide_drive_t *drive) 603static void hpt3xx_intrproc(ide_drive_t *drive)
670{ 604{
671 ide_hwif_t *hwif = HWIF(drive); 605 ide_hwif_t *hwif = HWIF(drive);
672 606
@@ -676,7 +610,7 @@ static void hpt3xx_intrproc (ide_drive_t *drive)
676 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG); 610 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
677} 611}
678 612
679static void hpt3xx_maskproc (ide_drive_t *drive, int mask) 613static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
680{ 614{
681 ide_hwif_t *hwif = HWIF(drive); 615 ide_hwif_t *hwif = HWIF(drive);
682 struct pci_dev *dev = hwif->pci_dev; 616 struct pci_dev *dev = hwif->pci_dev;
@@ -705,25 +639,22 @@ static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
705 IDE_CONTROL_REG); 639 IDE_CONTROL_REG);
706} 640}
707 641
708static int hpt366_config_drive_xfer_rate (ide_drive_t *drive) 642static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
709{ 643{
710 ide_hwif_t *hwif = drive->hwif; 644 ide_hwif_t *hwif = HWIF(drive);
711 struct hd_driveid *id = drive->id; 645 struct hd_driveid *id = drive->id;
712 646
713 drive->init_speed = 0; 647 drive->init_speed = 0;
714 648
715 if ((id->capability & 1) && drive->autodma) { 649 if ((id->capability & 1) && drive->autodma) {
716 650 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
717 if (ide_use_dma(drive)) { 651 return hwif->ide_dma_on(drive);
718 if (config_chipset_for_dma(drive))
719 return hwif->ide_dma_on(drive);
720 }
721 652
722 goto fast_ata_pio; 653 goto fast_ata_pio;
723 654
724 } else if ((id->capability & 8) || (id->field_valid & 2)) { 655 } else if ((id->capability & 8) || (id->field_valid & 2)) {
725fast_ata_pio: 656fast_ata_pio:
726 hpt3xx_tune_drive(drive, 5); 657 hpt3xx_tune_drive(drive, 255);
727 return hwif->ide_dma_off_quietly(drive); 658 return hwif->ide_dma_off_quietly(drive);
728 } 659 }
729 /* IORDY not supported */ 660 /* IORDY not supported */
@@ -1154,34 +1085,8 @@ init_hpt37X_done:
1154 udelay(100); 1085 udelay(100);
1155} 1086}
1156 1087
1157static int __devinit init_hpt37x(struct pci_dev *dev)
1158{
1159 u8 scr1;
1160
1161 pci_read_config_byte (dev, 0x5a, &scr1);
1162 /* interrupt force enable */
1163 pci_write_config_byte(dev, 0x5a, (scr1 & ~0x10));
1164 return 0;
1165}
1166
1167static int __devinit init_hpt366(struct pci_dev *dev)
1168{
1169 u8 mcr = 0;
1170
1171 /*
1172 * Disable the "fast interrupt" prediction.
1173 */
1174 pci_read_config_byte(dev, 0x51, &mcr);
1175 if (mcr & 0x80)
1176 pci_write_config_byte(dev, 0x51, mcr & ~0x80);
1177
1178 return 0;
1179}
1180
1181static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name) 1088static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1182{ 1089{
1183 int ret = 0;
1184
1185 /* 1090 /*
1186 * FIXME: Not portable. Also, why do we enable the ROM in the first place? 1091 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1187 * We don't seem to be using it. 1092 * We don't seem to be using it.
@@ -1195,23 +1100,25 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
1195 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 1100 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1196 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 1101 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1197 1102
1198 if (hpt_revision(dev) >= 3) 1103 if (hpt_revision(dev) >= 3) {
1199 ret = init_hpt37x(dev); 1104 u8 scr1 = 0;
1200 else
1201 ret = init_hpt366(dev);
1202 1105
1203 if (ret) 1106 /* Interrupt force enable. */
1204 return ret; 1107 pci_read_config_byte(dev, 0x5a, &scr1);
1108 if (scr1 & 0x10)
1109 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1110 }
1205 1111
1206 return dev->irq; 1112 return dev->irq;
1207} 1113}
1208 1114
1209static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) 1115static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1210{ 1116{
1211 struct pci_dev *dev = hwif->pci_dev; 1117 struct pci_dev *dev = hwif->pci_dev;
1212 struct hpt_info *info = ide_get_hwifdata(hwif); 1118 struct hpt_info *info = ide_get_hwifdata(hwif);
1213 int serialize = HPT_SERIALIZE_IO; 1119 int serialize = HPT_SERIALIZE_IO;
1214 u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02; 1120 u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02;
1121 u8 new_mcr, old_mcr = 0;
1215 1122
1216 /* Cache the channel's MISC. control registers' offset */ 1123 /* Cache the channel's MISC. control registers' offset */
1217 hwif->select_data = hwif->channel ? 0x54 : 0x50; 1124 hwif->select_data = hwif->channel ? 0x54 : 0x50;
@@ -1238,6 +1145,41 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1238 hwif->rw_disk = &hpt3xxn_rw_disk; 1145 hwif->rw_disk = &hpt3xxn_rw_disk;
1239 } 1146 }
1240 1147
1148 /* Serialize access to this device if needed */
1149 if (serialize && hwif->mate)
1150 hwif->serialized = hwif->mate->serialized = 1;
1151
1152 /*
1153 * Disable the "fast interrupt" prediction. Don't hold off
1154 * on interrupts. (== 0x01 despite what the docs say)
1155 */
1156 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1157
1158 if (info->revision >= 5) /* HPT372 and newer */
1159 new_mcr = old_mcr & ~0x07;
1160 else if (info->revision >= 3) { /* HPT370 and HPT370A */
1161 new_mcr = old_mcr;
1162 new_mcr &= ~0x02;
1163
1164#ifdef HPT_DELAY_INTERRUPT
1165 new_mcr &= ~0x01;
1166#else
1167 new_mcr |= 0x01;
1168#endif
1169 } else /* HPT366 and HPT368 */
1170 new_mcr = old_mcr & ~0x80;
1171
1172 if (new_mcr != old_mcr)
1173 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1174
1175 if (!hwif->dma_base) {
1176 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1177 return;
1178 }
1179
1180 hwif->ultra_mask = 0x7f;
1181 hwif->mwdma_mask = 0x07;
1182
1241 /* 1183 /*
1242 * The HPT37x uses the CBLID pins as outputs for MA15/MA16 1184 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1243 * address lines to access an external EEPROM. To read valid 1185 * address lines to access an external EEPROM. To read valid
@@ -1272,54 +1214,30 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1272 } else 1214 } else
1273 pci_read_config_byte (dev, 0x5a, &scr1); 1215 pci_read_config_byte (dev, 0x5a, &scr1);
1274 1216
1275 /* Serialize access to this device */ 1217 if (!hwif->udma_four)
1276 if (serialize && hwif->mate) 1218 hwif->udma_four = (scr1 & ata66) ? 0 : 1;
1277 hwif->serialized = hwif->mate->serialized = 1;
1278 1219
1279 /* 1220 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1280 * Set up ioctl for power status.
1281 * NOTE: power affects both drives on each channel.
1282 */
1283 hwif->busproc = &hpt3xx_busproc;
1284
1285 if (!hwif->dma_base) {
1286 hwif->drives[0].autotune = 1;
1287 hwif->drives[1].autotune = 1;
1288 return;
1289 }
1290 1221
1291 hwif->ultra_mask = 0x7f; 1222 if (info->revision >= 5) {
1292 hwif->mwdma_mask = 0x07; 1223 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1293 1224 hwif->ide_dma_end = &hpt374_ide_dma_end;
1294 if (!(hwif->udma_four))
1295 hwif->udma_four = ((scr1 & ata66) ? 0 : 1);
1296 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1297
1298 if (info->revision >= 8) {
1299 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1300 hwif->ide_dma_end = &hpt374_ide_dma_end;
1301 } else if (info->revision >= 5) {
1302 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1303 hwif->ide_dma_end = &hpt374_ide_dma_end;
1304 } else if (info->revision >= 3) { 1225 } else if (info->revision >= 3) {
1305 hwif->dma_start = &hpt370_ide_dma_start; 1226 hwif->dma_start = &hpt370_ide_dma_start;
1306 hwif->ide_dma_end = &hpt370_ide_dma_end; 1227 hwif->ide_dma_end = &hpt370_ide_dma_end;
1307 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout; 1228 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1308 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq; 1229 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1309 } else if (info->revision >= 2) 1230 } else
1310 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq; 1231 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1311 else
1312 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1313 1232
1314 if (!noautodma) 1233 if (!noautodma)
1315 hwif->autodma = 1; 1234 hwif->autodma = 1;
1316 hwif->drives[0].autodma = hwif->autodma; 1235 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1317 hwif->drives[1].autodma = hwif->autodma;
1318} 1236}
1319 1237
1320static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase) 1238static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1321{ 1239{
1322 struct pci_dev *dev = hwif->pci_dev; 1240 struct pci_dev *dev = hwif->pci_dev;
1323 struct hpt_info *info = ide_get_hwifdata(hwif); 1241 struct hpt_info *info = ide_get_hwifdata(hwif);
1324 u8 masterdma = 0, slavedma = 0; 1242 u8 masterdma = 0, slavedma = 0;
1325 u8 dma_new = 0, dma_old = 0; 1243 u8 dma_new = 0, dma_old = 0;
@@ -1334,7 +1252,7 @@ static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1334 return; 1252 return;
1335 } 1253 }
1336 1254
1337 dma_old = hwif->INB(dmabase+2); 1255 dma_old = hwif->INB(dmabase + 2);
1338 1256
1339 local_irq_save(flags); 1257 local_irq_save(flags);
1340 1258