Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (407 commits)
  [ARM] pxafb: add support for overlay1 and overlay2 as framebuffer devices
  [ARM] pxafb: cleanup of the timing checking code
  [ARM] pxafb: cleanup of the color format manipulation code
  [ARM] pxafb: add palette format support for LCCR4_PAL_FOR_3
  [ARM] pxafb: add support for FBIOPAN_DISPLAY by dma braching
  [ARM] pxafb: allow pxafb_set_par() to start from arbitrary yoffset
  [ARM] pxafb: allow video memory size to be configurable
  [ARM] pxa: add document on the MFP design and how to use it
  [ARM] sa1100_wdt: don't assume CLOCK_TICK_RATE to be a constant
  [ARM] rtc-sa1100: don't assume CLOCK_TICK_RATE to be a constant
  [ARM] pxa/tavorevb: update board support (smartpanel LCD + keypad)
  [ARM] pxa: Update eseries defconfig
  [ARM] 5352/1: add w90p910-plat config file
  [ARM] s3c: S3C options should depend on PLAT_S3C
  [ARM] mv78xx0: implement GPIO and GPIO interrupt support
  [ARM] Kirkwood: implement GPIO and GPIO interrupt support
  [ARM] Orion: share GPIO IRQ handling code
  [ARM] Orion: share GPIO handling code
  [ARM] s3c: define __io using the typesafe version
  [ARM] S3C64XX: Ensure CPU_V6 is selected
  ...

70 files changed, 2145 insertions, 1016 deletions

diff --git a/drivers/char/ds1620.c b/drivers/char/ds1620.c
index 74e9cd81b5b2..61f0146e215d 100644
--- a/drivers/char/ds1620.c
+++ b/drivers/char/ds1620.c
@@ -43,52 +43,51 @@ static const char *fan_state[] = { "off", "on", "on (hardwired)" };
  *  chance that the WaveArtist driver could touch these bits to
  *  enable or disable the speaker.
  */
-extern spinlock_t gpio_lock;
 extern unsigned int system_rev;
 
 static inline void netwinder_ds1620_set_clk(int clk)
 {
-        gpio_modify_op(GPIO_DSCLK, clk ? GPIO_DSCLK : 0);
+        nw_gpio_modify_op(GPIO_DSCLK, clk ? GPIO_DSCLK : 0);
 }
 
 static inline void netwinder_ds1620_set_data(int dat)
 {
-        gpio_modify_op(GPIO_DATA, dat ? GPIO_DATA : 0);
+        nw_gpio_modify_op(GPIO_DATA, dat ? GPIO_DATA : 0);
 }
 
 static inline int netwinder_ds1620_get_data(void)
 {
-        return gpio_read() & GPIO_DATA;
+        return nw_gpio_read() & GPIO_DATA;
 }
 
 static inline void netwinder_ds1620_set_data_dir(int dir)
 {
-        gpio_modify_io(GPIO_DATA, dir ? GPIO_DATA : 0);
+        nw_gpio_modify_io(GPIO_DATA, dir ? GPIO_DATA : 0);
 }
 
 static inline void netwinder_ds1620_reset(void)
 {
-        cpld_modify(CPLD_DS_ENABLE, 0);
-        cpld_modify(CPLD_DS_ENABLE, CPLD_DS_ENABLE);
+        nw_cpld_modify(CPLD_DS_ENABLE, 0);
+        nw_cpld_modify(CPLD_DS_ENABLE, CPLD_DS_ENABLE);
 }
 
 static inline void netwinder_lock(unsigned long *flags)
 {
-        spin_lock_irqsave(&gpio_lock, *flags);
+        spin_lock_irqsave(&nw_gpio_lock, *flags);
 }
 
 static inline void netwinder_unlock(unsigned long *flags)
 {
-        spin_unlock_irqrestore(&gpio_lock, *flags);
+        spin_unlock_irqrestore(&nw_gpio_lock, *flags);
 }
 
 static inline void netwinder_set_fan(int i)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&gpio_lock, flags);
-        gpio_modify_op(GPIO_FAN, i ? GPIO_FAN : 0);
-        spin_unlock_irqrestore(&gpio_lock, flags);
+        spin_lock_irqsave(&nw_gpio_lock, flags);
+        nw_gpio_modify_op(GPIO_FAN, i ? GPIO_FAN : 0);
+        spin_unlock_irqrestore(&nw_gpio_lock, flags);
 }
 
 static inline int netwinder_get_fan(void)
@@ -96,7 +95,7 @@ static inline int netwinder_get_fan(void)
         if ((system_rev & 0xf000) == 0x4000)
                 return FAN_ALWAYS_ON;
 
-        return (gpio_read() & GPIO_FAN) ? FAN_ON : FAN_OFF;
+        return (nw_gpio_read() & GPIO_FAN) ? FAN_ON : FAN_OFF;
 }
 
 /*
diff --git a/drivers/char/nwflash.c b/drivers/char/nwflash.c
index 006be92ee3f3..8c7df5ba088f 100644
--- a/drivers/char/nwflash.c
+++ b/drivers/char/nwflash.c
@@ -58,8 +58,6 @@ static volatile unsigned char *FLASH_BASE;
 static int gbFlashSize = KFLASH_SIZE;
 static DEFINE_MUTEX(nwflash_mutex);
 
-extern spinlock_t gpio_lock;
-
 static int get_flash_id(void)
 {
         volatile unsigned int c1, c2;
@@ -616,9 +614,9 @@ static void kick_open(void)
          * we want to write a bit pattern XXX1 to Xilinx to enable
          * the write gate, which will be open for about the next 2ms.
          */
-        spin_lock_irqsave(&gpio_lock, flags);
-        cpld_modify(1, 1);
-        spin_unlock_irqrestore(&gpio_lock, flags);
+        spin_lock_irqsave(&nw_gpio_lock, flags);
+        nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
+        spin_unlock_irqrestore(&nw_gpio_lock, flags);
 
         /*
          * let the ISA bus to catch on...
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 906f9b9d715d..587f5b2380d4 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -1016,7 +1016,7 @@ static int i2c_pxa_probe(struct platform_device *dev)
         snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
                  i2c->adap.nr);
 
-        i2c->clk = clk_get(&dev->dev, "I2CCLK");
+        i2c->clk = clk_get(&dev->dev, NULL);
         if (IS_ERR(i2c->clk)) {
                 ret = PTR_ERR(i2c->clk);
                 goto eclk;
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index b7434d24904e..c39079f9c73f 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -40,8 +40,8 @@
 #include <asm/io.h>
 
 #include <mach/regs-gpio.h>
-#include <asm/plat-s3c/regs-iic.h>
-#include <asm/plat-s3c/iic.h>
+#include <plat/regs-iic.h>
+#include <plat/iic.h>
 
 /* i2c controller state */
 
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 7a0a84b042c9..c9f21e3d4ead 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -727,7 +727,7 @@ config BLK_DEV_IDE_TX4939
 
 config IDE_ARM
         tristate "ARM IDE support"
-        depends on ARM && (ARCH_CLPS7500 || ARCH_RPC || ARCH_SHARK)
+        depends on ARM && (ARCH_RPC || ARCH_SHARK)
         default y
 
 config BLK_DEV_IDE_ICSIDE
diff --git a/drivers/ide/ide_arm.c b/drivers/ide/ide_arm.c
index f728f2927b5a..bdcac94d7c1f 100644
--- a/drivers/ide/ide_arm.c
+++ b/drivers/ide/ide_arm.c
@@ -15,15 +15,8 @@
 
 #define DRV_NAME "ide_arm"
 
-#ifdef CONFIG_ARCH_CLPS7500
-# include <mach/hardware.h>
-#
-# define IDE_ARM_IO     (ISASLOT_IO + 0x1f0)
-# define IDE_ARM_IRQ    IRQ_ISA_14
-#else
-# define IDE_ARM_IO     0x1f0
-# define IDE_ARM_IRQ    IRQ_HARDDISK
-#endif
+#define IDE_ARM_IO      0x1f0
+#define IDE_ARM_IRQ     IRQ_HARDDISK
 
 static int __init ide_arm_init(void)
 {
diff --git a/drivers/input/keyboard/omap-keypad.c b/drivers/input/keyboard/omap-keypad.c
index 69e674ecf19a..db22fd9b4cf2 100644
--- a/drivers/input/keyboard/omap-keypad.c
+++ b/drivers/input/keyboard/omap-keypad.c
@@ -101,7 +101,7 @@ static irqreturn_t omap_kp_interrupt(int irq, void *dev_id)
         if (cpu_is_omap24xx()) {
                 int i;
                 for (i = 0; i < omap_kp->rows; i++)
-                        disable_irq(OMAP_GPIO_IRQ(row_gpios[i]));
+                        disable_irq(gpio_to_irq(row_gpios[i]));
         } else
                 /* disable keyboard interrupt and schedule for handling */
                 omap_writew(1, OMAP_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
@@ -224,7 +224,7 @@ static void omap_kp_tasklet(unsigned long data)
                 if (cpu_is_omap24xx()) {
                         int i;
                         for (i = 0; i < omap_kp_data->rows; i++)
-                                enable_irq(OMAP_GPIO_IRQ(row_gpios[i]));
+                                enable_irq(gpio_to_irq(row_gpios[i]));
                 } else {
                         omap_writew(0, OMAP_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
                         kp_cur_group = -1;
@@ -397,7 +397,7 @@ static int __init omap_kp_probe(struct platform_device *pdev)
                 omap_writew(0, OMAP_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
         } else {
                 for (irq_idx = 0; irq_idx < omap_kp->rows; irq_idx++) {
-                        if (request_irq(OMAP_GPIO_IRQ(row_gpios[irq_idx]),
+                        if (request_irq(gpio_to_irq(row_gpios[irq_idx]),
                                         omap_kp_interrupt,
                                         IRQF_TRIGGER_FALLING,
                                         "omap-keypad", omap_kp) < 0)
@@ -438,7 +438,7 @@ static int omap_kp_remove(struct platform_device *pdev)
                         gpio_free(col_gpios[i]);
                 for (i = 0; i < omap_kp->rows; i++) {
                         gpio_free(row_gpios[i]);
-                        free_irq(OMAP_GPIO_IRQ(row_gpios[i]), 0);
+                        free_irq(gpio_to_irq(row_gpios[i]), 0);
                 }
         } else {
                 omap_writew(1, OMAP_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
diff --git a/drivers/input/keyboard/pxa27x_keypad.c b/drivers/input/keyboard/pxa27x_keypad.c
index 6d30c6d334c3..0d2fc64a5e1c 100644
--- a/drivers/input/keyboard/pxa27x_keypad.c
+++ b/drivers/input/keyboard/pxa27x_keypad.c
@@ -475,7 +475,7 @@ static int __devinit pxa27x_keypad_probe(struct platform_device *pdev)
                 goto failed_free_mem;
         }
 
-        keypad->clk = clk_get(&pdev->dev, "KBDCLK");
+        keypad->clk = clk_get(&pdev->dev, NULL);
         if (IS_ERR(keypad->clk)) {
                 dev_err(&pdev->dev, "failed to get keypad clock\n");
                 error = PTR_ERR(keypad->clk);
diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig
index 27d70d326ff3..da3c3a5d2689 100644
--- a/drivers/input/serio/Kconfig
+++ b/drivers/input/serio/Kconfig
@@ -79,7 +79,7 @@ config SERIO_PARKBD
 
 config SERIO_RPCKBD
         tristate "Acorn RiscPC keyboard controller"
-        depends on ARCH_ACORN || ARCH_CLPS7500
+        depends on ARCH_ACORN
         default y
         help
           Say Y here if you have the Acorn RiscPC and want to use an AT
diff --git a/drivers/input/touchscreen/mainstone-wm97xx.c b/drivers/input/touchscreen/mainstone-wm97xx.c
index ba648750a8d9..1d11e2be9ef8 100644
--- a/drivers/input/touchscreen/mainstone-wm97xx.c
+++ b/drivers/input/touchscreen/mainstone-wm97xx.c
@@ -31,7 +31,7 @@
 #include <linux/interrupt.h>
 #include <linux/wm97xx.h>
 #include <linux/io.h>
-#include <mach/pxa-regs.h>
+#include <mach/regs-ac97.h>
 
 #define VERSION         "0.13"
 
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index eb6be5802928..70a77625107d 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -39,6 +39,8 @@
 #include <mach/pxa-regs.h>
 #include <mach/camera.h>
 
+#include "pxa_camera.h"
+
 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
 #define PXA_CAM_DRV_NAME "pxa27x-camera"
 
@@ -1071,7 +1073,7 @@ static int pxa_camera_probe(struct platform_device *pdev)
                 goto exit;
         }
 
-        pcdev->clk = clk_get(&pdev->dev, "CAMCLK");
+        pcdev->clk = clk_get(&pdev->dev, NULL);
         if (IS_ERR(pcdev->clk)) {
                 err = PTR_ERR(pcdev->clk);
                 goto exit_kfree;
diff --git a/drivers/media/video/pxa_camera.h b/drivers/media/video/pxa_camera.h
new file mode 100644
index 000000000000..89cbfc9a35c5
--- /dev/null
+++ b/drivers/media/video/pxa_camera.h
@@ -0,0 +1,95 @@
+/* Camera Interface */
+#define CICR0           __REG(0x50000000)
+#define CICR1           __REG(0x50000004)
+#define CICR2           __REG(0x50000008)
+#define CICR3           __REG(0x5000000C)
+#define CICR4           __REG(0x50000010)
+#define CISR            __REG(0x50000014)
+#define CIFR            __REG(0x50000018)
+#define CITOR           __REG(0x5000001C)
+#define CIBR0           __REG(0x50000028)
+#define CIBR1           __REG(0x50000030)
+#define CIBR2           __REG(0x50000038)
+
+#define CICR0_DMAEN     (1 << 31)       /* DMA request enable */
+#define CICR0_PAR_EN    (1 << 30)       /* Parity enable */
+#define CICR0_SL_CAP_EN (1 << 29)       /* Capture enable for slave mode */
+#define CICR0_ENB       (1 << 28)       /* Camera interface enable */
+#define CICR0_DIS       (1 << 27)       /* Camera interface disable */
+#define CICR0_SIM       (0x7 << 24)     /* Sensor interface mode mask */
+#define CICR0_TOM       (1 << 9)        /* Time-out mask */
+#define CICR0_RDAVM     (1 << 8)        /* Receive-data-available mask */
+#define CICR0_FEM       (1 << 7)        /* FIFO-empty mask */
+#define CICR0_EOLM      (1 << 6)        /* End-of-line mask */
+#define CICR0_PERRM     (1 << 5)        /* Parity-error mask */
+#define CICR0_QDM       (1 << 4)        /* Quick-disable mask */
+#define CICR0_CDM       (1 << 3)        /* Disable-done mask */
+#define CICR0_SOFM      (1 << 2)        /* Start-of-frame mask */
+#define CICR0_EOFM      (1 << 1)        /* End-of-frame mask */
+#define CICR0_FOM       (1 << 0)        /* FIFO-overrun mask */
+
+#define CICR1_TBIT      (1 << 31)       /* Transparency bit */
+#define CICR1_RGBT_CONV (0x3 << 29)     /* RGBT conversion mask */
+#define CICR1_PPL       (0x7ff << 15)   /* Pixels per line mask */
+#define CICR1_RGB_CONV  (0x7 << 12)     /* RGB conversion mask */
+#define CICR1_RGB_F     (1 << 11)       /* RGB format */
+#define CICR1_YCBCR_F   (1 << 10)       /* YCbCr format */
+#define CICR1_RGB_BPP   (0x7 << 7)      /* RGB bis per pixel mask */
+#define CICR1_RAW_BPP   (0x3 << 5)      /* Raw bis per pixel mask */
+#define CICR1_COLOR_SP  (0x3 << 3)      /* Color space mask */
+#define CICR1_DW        (0x7 << 0)      /* Data width mask */
+
+#define CICR2_BLW       (0xff << 24)    /* Beginning-of-line pixel clock
+                                           wait count mask */
+#define CICR2_ELW       (0xff << 16)    /* End-of-line pixel clock
+                                           wait count mask */
+#define CICR2_HSW       (0x3f << 10)    /* Horizontal sync pulse width mask */
+#define CICR2_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
+                                           wait count mask */
+#define CICR2_FSW       (0x7 << 0)      /* Frame stabilization
+                                           wait count mask */
+
+#define CICR3_BFW       (0xff << 24)    /* Beginning-of-frame line clock
+                                           wait count mask */
+#define CICR3_EFW       (0xff << 16)    /* End-of-frame line clock
+                                           wait count mask */
+#define CICR3_VSW       (0x3f << 10)    /* Vertical sync pulse width mask */
+#define CICR3_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
+                                           wait count mask */
+#define CICR3_LPF       (0x7ff << 0)    /* Lines per frame mask */
+
+#define CICR4_MCLK_DLY  (0x3 << 24)     /* MCLK Data Capture Delay mask */
+#define CICR4_PCLK_EN   (1 << 23)       /* Pixel clock enable */
+#define CICR4_PCP       (1 << 22)       /* Pixel clock polarity */
+#define CICR4_HSP       (1 << 21)       /* Horizontal sync polarity */
+#define CICR4_VSP       (1 << 20)       /* Vertical sync polarity */
+#define CICR4_MCLK_EN   (1 << 19)       /* MCLK enable */
+#define CICR4_FR_RATE   (0x7 << 8)      /* Frame rate mask */
+#define CICR4_DIV       (0xff << 0)     /* Clock divisor mask */
+
+#define CISR_FTO        (1 << 15)       /* FIFO time-out */
+#define CISR_RDAV_2     (1 << 14)       /* Channel 2 receive data available */
+#define CISR_RDAV_1     (1 << 13)       /* Channel 1 receive data available */
+#define CISR_RDAV_0     (1 << 12)       /* Channel 0 receive data available */
+#define CISR_FEMPTY_2   (1 << 11)       /* Channel 2 FIFO empty */
+#define CISR_FEMPTY_1   (1 << 10)       /* Channel 1 FIFO empty */
+#define CISR_FEMPTY_0   (1 << 9)        /* Channel 0 FIFO empty */
+#define CISR_EOL        (1 << 8)        /* End of line */
+#define CISR_PAR_ERR    (1 << 7)        /* Parity error */
+#define CISR_CQD        (1 << 6)        /* Camera interface quick disable */
+#define CISR_CDD        (1 << 5)        /* Camera interface disable done */
+#define CISR_SOF        (1 << 4)        /* Start of frame */
+#define CISR_EOF        (1 << 3)        /* End of frame */
+#define CISR_IFO_2      (1 << 2)        /* FIFO overrun for Channel 2 */
+#define CISR_IFO_1      (1 << 1)        /* FIFO overrun for Channel 1 */
+#define CISR_IFO_0      (1 << 0)        /* FIFO overrun for Channel 0 */
+
+#define CIFR_FLVL2      (0x7f << 23)    /* FIFO 2 level mask */
+#define CIFR_FLVL1      (0x7f << 16)    /* FIFO 1 level mask */
+#define CIFR_FLVL0      (0xff << 8)     /* FIFO 0 level mask */
+#define CIFR_THL_0      (0x3 << 4)      /* Threshold Level for Channel 0 FIFO */
+#define CIFR_RESET_F    (1 << 3)        /* Reset input FIFOs */
+#define CIFR_FEN2       (1 << 2)        /* FIFO enable for channel 2 */
+#define CIFR_FEN1       (1 << 1)        /* FIFO enable for channel 1 */
+#define CIFR_FEN0       (1 << 0)        /* FIFO enable for channel 0 */
+
diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c
index e4c0db4dc7b1..9e485459f63b 100644
--- a/drivers/mfd/asic3.c
+++ b/drivers/mfd/asic3.c
@@ -474,9 +474,9 @@ static __init int asic3_gpio_probe(struct platform_device *pdev,
         u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
         int i;
 
-        memzero(alt_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
-        memzero(out_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
-        memzero(dir_reg, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
+        memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
+        memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
+        memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
 
         /* Enable all GPIOs */
         asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
diff --git a/drivers/mfd/mcp-core.c b/drivers/mfd/mcp-core.c
index b4ed57e02729..6063dc2b52e8 100644
--- a/drivers/mfd/mcp-core.c
+++ b/drivers/mfd/mcp-core.c
@@ -18,7 +18,7 @@
 #include <linux/slab.h>
 #include <linux/string.h>
 
-#include <asm/dma.h>
+#include <mach/dma.h>
 #include <asm/system.h>
 
 #include "mcp.h"
diff --git a/drivers/mfd/mcp-sa11x0.c b/drivers/mfd/mcp-sa11x0.c
index 28380b20bc70..62b32dabf629 100644
--- a/drivers/mfd/mcp-sa11x0.c
+++ b/drivers/mfd/mcp-sa11x0.c
@@ -20,7 +20,7 @@
 #include <linux/slab.h>
 #include <linux/platform_device.h>
 
-#include <asm/dma.h>
+#include <mach/dma.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/system.h>
diff --git a/drivers/mfd/ucb1x00-assabet.c b/drivers/mfd/ucb1x00-assabet.c
index 61aeaf79640d..86fed4870f93 100644
--- a/drivers/mfd/ucb1x00-assabet.c
+++ b/drivers/mfd/ucb1x00-assabet.c
@@ -15,7 +15,7 @@
 #include <linux/proc_fs.h>
 #include <linux/device.h>
 
-#include <asm/dma.h>
+#include <mach/dma.h>
 
 #include "ucb1x00.h"
 
diff --git a/drivers/mfd/ucb1x00-core.c b/drivers/mfd/ucb1x00-core.c
index a316f1b75933..6860c924f364 100644
--- a/drivers/mfd/ucb1x00-core.c
+++ b/drivers/mfd/ucb1x00-core.c
@@ -25,7 +25,7 @@
 #include <linux/device.h>
 #include <linux/mutex.h>
 
-#include <asm/dma.h>
+#include <mach/dma.h>
 #include <mach/hardware.h>
 
 #include "ucb1x00.h"
diff --git a/drivers/mfd/ucb1x00-ts.c b/drivers/mfd/ucb1x00-ts.c
index 44762ca86a8d..61b7d3eb9a2f 100644
--- a/drivers/mfd/ucb1x00-ts.c
+++ b/drivers/mfd/ucb1x00-ts.c
@@ -31,7 +31,7 @@
 #include <linux/slab.h>
 #include <linux/kthread.h>
 
-#include <asm/dma.h>
+#include <mach/dma.h>
 #include <mach/collie.h>
 #include <asm/mach-types.h>
 
diff --git a/drivers/mmc/host/imxmmc.c b/drivers/mmc/host/imxmmc.c
index 2f0fcdb869b7..eb29b1d933ac 100644
--- a/drivers/mmc/host/imxmmc.c
+++ b/drivers/mmc/host/imxmmc.c
@@ -10,20 +10,6 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  *
- *  2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- *             Changed to conform redesigned i.MX scatter gather DMA interface
- *
- *  2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- *             Updated for 2.6.14 kernel
- *
- *  2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
- *             Found and corrected problems in the write path
- *
- *  2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
- *             The event handling rewritten right way in softirq.
- *             Added many ugly hacks and delays to overcome SDHC
- *             deficiencies
- *
  */
 
 #include <linux/module.h>
@@ -37,9 +23,9 @@
 #include <linux/mmc/card.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
+#include <linux/io.h>
 
 #include <asm/dma.h>
-#include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
 #include <mach/mmc.h>
@@ -50,17 +36,16 @@
 #define DRIVER_NAME "imx-mmc"
 
 #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
-                      INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
-                      INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
+                                 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
+                                 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
 
 struct imxmci_host {
         struct mmc_host         *mmc;
         spinlock_t              lock;
         struct resource         *res;
+        void __iomem            *base;
         int                     irq;
         imx_dmach_t             dma;
-        unsigned int            clkrt;
-        unsigned int            cmdat;
         volatile unsigned int   imask;
         unsigned int            power_mode;
         unsigned int            present;
@@ -74,7 +59,7 @@ struct imxmci_host {
         struct tasklet_struct   tasklet;
         unsigned int            status_reg;
         unsigned long           pending_events;
-        /* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */
+        /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
         u16                     *data_ptr;
         unsigned int            data_cnt;
         atomic_t                stuck_timeout;
@@ -114,14 +99,22 @@ struct imxmci_host {
 static void imxmci_stop_clock(struct imxmci_host *host)
 {
         int i = 0;
-        MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
-        while(i < 0x1000) {
-                if(!(i & 0x7f))
-                        MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
+        u16 reg;
+
+        reg = readw(host->base + MMC_REG_STR_STP_CLK);
+        writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
+        while (i < 0x1000) {
+                if (!(i & 0x7f)) {
+                        reg = readw(host->base + MMC_REG_STR_STP_CLK);
+                        writew(reg | STR_STP_CLK_STOP_CLK,
+                                        host->base + MMC_REG_STR_STP_CLK);
+                }
 
-                if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
+                reg = readw(host->base + MMC_REG_STATUS);
+                if (!(reg & STATUS_CARD_BUS_CLK_RUN)) {
                         /* Check twice before cut */
-                        if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
+                        reg = readw(host->base + MMC_REG_STATUS);
+                        if (!(reg & STATUS_CARD_BUS_CLK_RUN))
                                 return;
                 }
 
@@ -135,8 +128,10 @@ static int imxmci_start_clock(struct imxmci_host *host)
         unsigned int trials = 0;
         unsigned int delay_limit = 128;
         unsigned long flags;
+        u16 reg;
 
-        MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
+        reg = readw(host->base + MMC_REG_STR_STP_CLK);
+        writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
 
         clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
 
@@ -145,18 +140,21 @@ static int imxmci_start_clock(struct imxmci_host *host)
          * then 6 delay loops, but during card detection (low clockrate)
          * it takes up to 5000 delay loops and sometimes fails for the first time
          */
-        MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
+        reg = readw(host->base + MMC_REG_STR_STP_CLK);
+        writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
 
         do {
                 unsigned int delay = delay_limit;
 
-                while(delay--){
-                        if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
+                while (delay--) {
+                        reg = readw(host->base + MMC_REG_STATUS);
+                        if (reg & STATUS_CARD_BUS_CLK_RUN)
                                 /* Check twice before cut */
-                                if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
+                                reg = readw(host->base + MMC_REG_STATUS);
+                                if (reg & STATUS_CARD_BUS_CLK_RUN)
                                         return 0;
 
-                        if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
+                        if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
                                 return 0;
                 }
 
@@ -167,58 +165,59 @@ static int imxmci_start_clock(struct imxmci_host *host)
                  * IRQ or schedule delays this function execution and the clocks has
                  * been already stopped by other means (response processing, SDHC HW)
                  */
-                if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
-                        MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
+                if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) {
+                        reg = readw(host->base + MMC_REG_STR_STP_CLK);
+                        writew(reg | STR_STP_CLK_START_CLK,
+                                        host->base + MMC_REG_STR_STP_CLK);
+                }
                 local_irq_restore(flags);
 
-        } while(++trials<256);
+        } while (++trials < 256);
 
         dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
 
         return -1;
 }
 
-static void imxmci_softreset(void)
+static void imxmci_softreset(struct imxmci_host *host)
 {
+        int i;
+
         /* reset sequence */
-        MMC_STR_STP_CLK = 0x8;
-        MMC_STR_STP_CLK = 0xD;
-        MMC_STR_STP_CLK = 0x5;
-        MMC_STR_STP_CLK = 0x5;
-        MMC_STR_STP_CLK = 0x5;
-        MMC_STR_STP_CLK = 0x5;
-        MMC_STR_STP_CLK = 0x5;
-        MMC_STR_STP_CLK = 0x5;
-        MMC_STR_STP_CLK = 0x5;
-        MMC_STR_STP_CLK = 0x5;
-
-        MMC_RES_TO = 0xff;
-        MMC_BLK_LEN = 512;
-        MMC_NOB = 1;
+        writew(0x08, host->base + MMC_REG_STR_STP_CLK);
+        writew(0x0D, host->base + MMC_REG_STR_STP_CLK);
+
+        for (i = 0; i < 8; i++)
+                writew(0x05, host->base + MMC_REG_STR_STP_CLK);
+
+        writew(0xff, host->base + MMC_REG_RES_TO);
+        writew(512, host->base + MMC_REG_BLK_LEN);
+        writew(1, host->base + MMC_REG_NOB);
 }
 
 static int imxmci_busy_wait_for_status(struct imxmci_host *host,
-                        unsigned int *pstat, unsigned int stat_mask,
-                        int timeout, const char *where)
+                                       unsigned int *pstat, unsigned int stat_mask,
+                                       int timeout, const char *where)
 {
-        int loops=0;
-        while(!(*pstat & stat_mask)) {
-                loops+=2;
-                if(loops >= timeout) {
+        int loops = 0;
+
+        while (!(*pstat & stat_mask)) {
+                loops += 2;
+                if (loops >= timeout) {
                         dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
                                 where, *pstat, stat_mask);
                         return -1;
                 }
                 udelay(2);
-                *pstat |= MMC_STATUS;
+                *pstat |= readw(host->base + MMC_REG_STATUS);
         }
-        if(!loops)
+        if (!loops)
                 return 0;
 
         /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
-        if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000))
+        if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
                 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
-                        loops, where, *pstat, stat_mask);
+                         loops, where, *pstat, stat_mask);
         return loops;
 }
 
@@ -235,8 +234,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
         host->data = data;
         data->bytes_xfered = 0;
 
-        MMC_NOB = nob;
-        MMC_BLK_LEN = blksz;
+        writew(nob, host->base + MMC_REG_NOB);
+        writew(blksz, host->base + MMC_REG_BLK_LEN);
 
         /*
          * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
@@ -252,14 +251,14 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
                         host->dma_dir = DMA_FROM_DEVICE;
 
                         /* Hack to enable read SCR */
-                        MMC_NOB = 1;
-                        MMC_BLK_LEN = 512;
+                        writew(1, host->base + MMC_REG_NOB);
+                        writew(512, host->base + MMC_REG_BLK_LEN);
                 } else {
                         host->dma_dir = DMA_TO_DEVICE;
                 }
 
                 /* Convert back to virtual address */
-                host->data_ptr = (u16*)sg_virt(data->sg);
+                host->data_ptr = (u16 *)sg_virt(data->sg);
                 host->data_cnt = 0;
 
                 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
@@ -271,10 +270,11 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
         if (data->flags & MMC_DATA_READ) {
                 host->dma_dir = DMA_FROM_DEVICE;
                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
-                                                data->sg_len,  host->dma_dir);
+                                             data->sg_len,  host->dma_dir);
 
                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
-                        host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
+                                 host->res->start + MMC_REG_BUFFER_ACCESS,
+                                 DMA_MODE_READ);
 
                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
                 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
@@ -282,10 +282,11 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
                 host->dma_dir = DMA_TO_DEVICE;
 
                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
-                                                data->sg_len,  host->dma_dir);
+                                             data->sg_len,  host->dma_dir);
 
                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
-                        host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
+                                 host->res->start + MMC_REG_BUFFER_ACCESS,
+                                 DMA_MODE_WRITE);
 
                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
                 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
@@ -293,12 +294,12 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
 
 #if 1   /* This code is there only for consistency checking and can be disabled in future */
         host->dma_size = 0;
-        for(i=0; i<host->dma_nents; i++)
-                host->dma_size+=data->sg[i].length;
+        for (i = 0; i < host->dma_nents; i++)
+                host->dma_size += data->sg[i].length;
 
         if (datasz > host->dma_size) {
                 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
-                       datasz, host->dma_size);
+                        datasz, host->dma_size);
         }
 #endif
 
@@ -306,7 +307,7 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
 
         wmb();
 
-        if(host->actual_bus_width == MMC_BUS_WIDTH_4)
+        if (host->actual_bus_width == MMC_BUS_WIDTH_4)
                 BLR(host->dma) = 0;     /* burst 64 byte read / 64 bytes write */
         else
                 BLR(host->dma) = 16;    /* burst 16 byte read / 16 bytes write */
@@ -317,9 +318,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
         clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
 
         /* start DMA engine for read, write is delayed after initial response */
-        if (host->dma_dir == DMA_FROM_DEVICE) {
+        if (host->dma_dir == DMA_FROM_DEVICE)
                 imx_dma_enable(host->dma);
-        }
 }
 
 static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
@@ -351,16 +351,16 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
                 break;
         }
 
-        if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) )
+        if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
                 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
 
-        if ( host->actual_bus_width == MMC_BUS_WIDTH_4 )
+        if (host->actual_bus_width == MMC_BUS_WIDTH_4)
                 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
 
-        MMC_CMD = cmd->opcode;
-        MMC_ARGH = cmd->arg >> 16;
-        MMC_ARGL = cmd->arg & 0xffff;
-        MMC_CMD_DAT_CONT = cmdat;
+        writew(cmd->opcode, host->base + MMC_REG_CMD);
+        writew(cmd->arg >> 16, host->base + MMC_REG_ARGH);
+        writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL);
+        writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
 
         atomic_set(&host->stuck_timeout, 0);
         set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
@@ -368,18 +368,18 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
 
         imask = IMXMCI_INT_MASK_DEFAULT;
         imask &= ~INT_MASK_END_CMD_RES;
-        if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) {
-                /*imask &= ~INT_MASK_BUF_READY;*/
+        if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
+                /* imask &= ~INT_MASK_BUF_READY; */
                 imask &= ~INT_MASK_DATA_TRAN;
-                if ( cmdat & CMD_DAT_CONT_WRITE )
+                if (cmdat & CMD_DAT_CONT_WRITE)
                         imask &= ~INT_MASK_WRITE_OP_DONE;
-                if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
+                if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
                         imask &= ~INT_MASK_BUF_READY;
         }
 
         spin_lock_irqsave(&host->lock, flags);
         host->imask = imask;
-        MMC_INT_MASK = host->imask;
+        writew(host->imask, host->base + MMC_REG_INT_MASK);
         spin_unlock_irqrestore(&host->lock, flags);
 
         dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
@@ -395,14 +395,14 @@ static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *
         spin_lock_irqsave(&host->lock, flags);
 
         host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
-                        IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
+                                  IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
 
         host->imask = IMXMCI_INT_MASK_DEFAULT;
-        MMC_INT_MASK = host->imask;
+        writew(host->imask, host->base + MMC_REG_INT_MASK);
 
         spin_unlock_irqrestore(&host->lock, flags);
 
-        if(req && req->cmd)
+        if (req && req->cmd)
                 host->prev_cmd_code = req->cmd->opcode;
 
         host->req = NULL;
@@ -416,17 +416,17 @@ static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
         struct mmc_data *data = host->data;
         int data_error;
 
-        if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){
+        if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
                 imx_dma_disable(host->dma);
                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
                              host->dma_dir);
         }
 
-        if ( stat & STATUS_ERR_MASK ) {
-                dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat);
-                if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
+        if (stat & STATUS_ERR_MASK) {
+                dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
+                if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
                         data->error = -EILSEQ;
-                else if(stat & STATUS_TIME_OUT_READ)
+                else if (stat & STATUS_TIME_OUT_READ)
                         data->error = -ETIMEDOUT;
                 else
                         data->error = -EIO;
@@ -445,7 +445,7 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
 {
         struct mmc_command *cmd = host->cmd;
         int i;
-        u32 a,b,c;
+        u32 a, b, c;
         struct mmc_data *data = host->data;
 
         if (!cmd)
@@ -461,18 +461,18 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
                 cmd->error = -EILSEQ;
         }
 
-        if(cmd->flags & MMC_RSP_PRESENT) {
-                if(cmd->flags & MMC_RSP_136) {
+        if (cmd->flags & MMC_RSP_PRESENT) {
+                if (cmd->flags & MMC_RSP_136) {
                         for (i = 0; i < 4; i++) {
-                                u32 a = MMC_RES_FIFO & 0xffff;
-                                u32 b = MMC_RES_FIFO & 0xffff;
-                                cmd->resp[i] = a<<16 | b;
+                                a = readw(host->base + MMC_REG_RES_FIFO);
+                                b = readw(host->base + MMC_REG_RES_FIFO);
+                                cmd->resp[i] = a << 16 | b;
                         }
                 } else {
-                        a = MMC_RES_FIFO & 0xffff;
-                        b = MMC_RES_FIFO & 0xffff;
-                        c = MMC_RES_FIFO & 0xffff;
-                        cmd->resp[0] = a<<24 | b<<8 | c>>8;
+                        a = readw(host->base + MMC_REG_RES_FIFO);
+                        b = readw(host->base + MMC_REG_RES_FIFO);
+                        c = readw(host->base + MMC_REG_RES_FIFO);
+                        cmd->resp[0] = a << 24 | b << 8 | c >> 8;
                 }
         }
 
@@ -484,36 +484,34 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
 
                         /* Wait for FIFO to be empty before starting DMA write */
 
-                        stat = MMC_STATUS;
-                        if(imxmci_busy_wait_for_status(host, &stat,
-                                STATUS_APPL_BUFF_FE,
-                                40, "imxmci_cmd_done DMA WR") < 0) {
+                        stat = readw(host->base + MMC_REG_STATUS);
+                        if (imxmci_busy_wait_for_status(host, &stat,
+                                                        STATUS_APPL_BUFF_FE,
+                                                        40, "imxmci_cmd_done DMA WR") < 0) {
                                 cmd->error = -EIO;
                                 imxmci_finish_data(host, stat);
-                                if(host->req)
+                                if (host->req)
                                         imxmci_finish_request(host, host->req);
                                 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
-                                       stat);
+                                         stat);
                                 return 0;
                         }
 
-                        if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
+                        if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
                                 imx_dma_enable(host->dma);
-                        }
                 }
         } else {
                 struct mmc_request *req;
                 imxmci_stop_clock(host);
                 req = host->req;
 
-                if(data)
+                if (data)
                         imxmci_finish_data(host, stat);
 
-                if( req ) {
+                if (req)
                         imxmci_finish_request(host, req);
-                } else {
+                else
                         dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
-                }
         }
 
         return 1;
@@ -535,11 +533,10 @@ static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
         } else {
                 struct mmc_request *req;
                 req = host->req;
-                if( req ) {
+                if (req)
                         imxmci_finish_request(host, req);
-                } else {
+                else
                         dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
-                }
         }
 
         return 1;
@@ -552,7 +549,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
         int trans_done = 0;
         unsigned int stat = *pstat;
 
-        if(host->actual_bus_width != MMC_BUS_WIDTH_4)
+        if (host->actual_bus_width != MMC_BUS_WIDTH_4)
                 burst_len = 16;
         else
                 burst_len = 64;
@@ -563,44 +560,44 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
 
         udelay(20);     /* required for clocks < 8MHz*/
 
-        if(host->dma_dir == DMA_FROM_DEVICE) {
+        if (host->dma_dir == DMA_FROM_DEVICE) {
                 imxmci_busy_wait_for_status(host, &stat,
-                                STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
-                                STATUS_TIME_OUT_READ,
-                                50, "imxmci_cpu_driven_data read");
+                                            STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
+                                            STATUS_TIME_OUT_READ,
+                                            50, "imxmci_cpu_driven_data read");
 
-                while((stat & (STATUS_APPL_BUFF_FF |  STATUS_DATA_TRANS_DONE)) &&
-                      !(stat & STATUS_TIME_OUT_READ) &&
-                      (host->data_cnt < 512)) {
+                while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
+                       !(stat & STATUS_TIME_OUT_READ) &&
+                       (host->data_cnt < 512)) {
 
                         udelay(20);     /* required for clocks < 8MHz*/
 
-                        for(i = burst_len; i>=2 ; i-=2) {
+                        for (i = burst_len; i >= 2 ; i -= 2) {
                                 u16 data;
-                                data = MMC_BUFFER_ACCESS;
+                                data = readw(host->base + MMC_REG_BUFFER_ACCESS);
                                 udelay(10);     /* required for clocks < 8MHz*/
-                                if(host->data_cnt+2 <= host->dma_size) {
+                                if (host->data_cnt+2 <= host->dma_size) {
                                         *(host->data_ptr++) = data;
                                 } else {
-                                        if(host->data_cnt < host->dma_size)
-                                                *(u8*)(host->data_ptr) = data;
+                                        if (host->data_cnt < host->dma_size)
+                                                *(u8 *)(host->data_ptr) = data;
                                 }
                                 host->data_cnt += 2;
                         }
 
-                        stat = MMC_STATUS;
+                        stat = readw(host->base + MMC_REG_STATUS);
 
                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
                                 host->data_cnt, burst_len, stat);
                 }
 
-                if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
+                if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
                         trans_done = 1;
 
-                if(host->dma_size & 0x1ff)
+                if (host->dma_size & 0x1ff)
                         stat &= ~STATUS_CRC_READ_ERR;
 
-                if(stat & STATUS_TIME_OUT_READ) {
+                if (stat & STATUS_TIME_OUT_READ) {
                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
                                 stat);
                         trans_done = -1;
@@ -608,12 +605,12 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
 
         } else {
                 imxmci_busy_wait_for_status(host, &stat,
-                                STATUS_APPL_BUFF_FE,
-                                20, "imxmci_cpu_driven_data write");
+                                            STATUS_APPL_BUFF_FE,
+                                            20, "imxmci_cpu_driven_data write");
 
-                while((stat & STATUS_APPL_BUFF_FE) &&
-                      (host->data_cnt < host->dma_size)) {
-                        if(burst_len >= host->dma_size - host->data_cnt) {
+                while ((stat & STATUS_APPL_BUFF_FE) &&
+                       (host->data_cnt < host->dma_size)) {
+                        if (burst_len >= host->dma_size - host->data_cnt) {
                                 burst_len = host->dma_size - host->data_cnt;
                                 host->data_cnt = host->dma_size;
                                 trans_done = 1;
@@ -621,10 +618,10 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
                                 host->data_cnt += burst_len;
                         }
 
-                        for(i = burst_len; i>0 ; i-=2)
-                                MMC_BUFFER_ACCESS = *(host->data_ptr++);
+                        for (i = burst_len; i > 0 ; i -= 2)
+                                writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS);
 
-                        stat = MMC_STATUS;
+                        stat = readw(host->base + MMC_REG_STATUS);
 
                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
                                 burst_len, stat);
@@ -639,7 +636,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
 static void imxmci_dma_irq(int dma, void *devid)
 {
         struct imxmci_host *host = devid;
-        uint32_t stat = MMC_STATUS;
+        u32 stat = readw(host->base + MMC_REG_STATUS);
 
         atomic_set(&host->stuck_timeout, 0);
         host->status_reg = stat;
@@ -650,10 +647,11 @@ static void imxmci_dma_irq(int dma, void *devid)
 static irqreturn_t imxmci_irq(int irq, void *devid)
 {
         struct imxmci_host *host = devid;
-        uint32_t stat = MMC_STATUS;
+        u32 stat = readw(host->base + MMC_REG_STATUS);
         int handled = 1;
 
-        MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
+        writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT,
+                        host->base + MMC_REG_INT_MASK);
 
         atomic_set(&host->stuck_timeout, 0);
         host->status_reg = stat;
@@ -671,10 +669,10 @@ static void imxmci_tasklet_fnc(unsigned long data)
         unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
         int timeout = 0;
 
-        if(atomic_read(&host->stuck_timeout) > 4) {
+        if (atomic_read(&host->stuck_timeout) > 4) {
                 char *what;
                 timeout = 1;
-                stat = MMC_STATUS;
+                stat = readw(host->base + MMC_REG_STATUS);
                 host->status_reg = stat;
                 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
@@ -683,29 +681,37 @@ static void imxmci_tasklet_fnc(unsigned long data)
                                 what = "RESP";
                 else
                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
-                                if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
+                                if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
                                         what = "DATA";
                                 else
                                         what = "DMA";
                         else
                                 what = "???";
 
-                dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
-                       what, stat, MMC_INT_MASK);
-                dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
-                       MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
+                dev_err(mmc_dev(host->mmc),
+                        "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
+                        what, stat,
+                        readw(host->base + MMC_REG_INT_MASK));
+                dev_err(mmc_dev(host->mmc),
+                        "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
+                        readw(host->base + MMC_REG_CMD_DAT_CONT),
+                        readw(host->base + MMC_REG_BLK_LEN),
+                        readw(host->base + MMC_REG_NOB),
+                        CCR(host->dma));
                 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
-                       host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size);
+                        host->cmd ? host->cmd->opcode : 0,
+                        host->prev_cmd_code,
+                        1 << host->actual_bus_width, host->dma_size);
         }
 
-        if(!host->present || timeout)
+        if (!host->present || timeout)
                 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
-                                    STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
+                        STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
 
-        if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
+        if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
                 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
 
-                stat = MMC_STATUS;
+                stat = readw(host->base + MMC_REG_STATUS);
                 /*
                  * This is not required in theory, but there is chance to miss some flag
                  * which clears automatically by mask write, FreeScale original code keeps
@@ -713,63 +719,62 @@ static void imxmci_tasklet_fnc(unsigned long data)
                  */
                 stat |= host->status_reg;
 
-                if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
+                if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
                         stat &= ~STATUS_CRC_READ_ERR;
 
-                if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
+                if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
                         imxmci_busy_wait_for_status(host, &stat,
-                                        STATUS_END_CMD_RESP | STATUS_ERR_MASK,
-                                        20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
+                                                    STATUS_END_CMD_RESP | STATUS_ERR_MASK,
+                                                    20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
                 }
 
-                if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
-                        if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
+                if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
+                        if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
                                 imxmci_cmd_done(host, stat);
-                        if(host->data && (stat & STATUS_ERR_MASK))
+                        if (host->data && (stat & STATUS_ERR_MASK))
                                 imxmci_data_done(host, stat);
                 }
 
-                if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
-                        stat |= MMC_STATUS;
-                        if(imxmci_cpu_driven_data(host, &stat)){
-                                if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
+                if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
+                        stat |= readw(host->base + MMC_REG_STATUS);
+                        if (imxmci_cpu_driven_data(host, &stat)) {
+                                if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
                                         imxmci_cmd_done(host, stat);
                                 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
-                                                        &host->pending_events);
+                                                  &host->pending_events);
                                 imxmci_data_done(host, stat);
                         }
                 }
         }
 
-        if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
-           !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
+        if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
+            !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
 
-                stat = MMC_STATUS;
+                stat = readw(host->base + MMC_REG_STATUS);
                 /* Same as above */
                 stat |= host->status_reg;
 
-                if(host->dma_dir == DMA_TO_DEVICE) {
+                if (host->dma_dir == DMA_TO_DEVICE)
                         data_dir_mask = STATUS_WRITE_OP_DONE;
-                } else {
+                else
                         data_dir_mask = STATUS_DATA_TRANS_DONE;
-                }
 
-                if(stat & data_dir_mask) {
+                if (stat & data_dir_mask) {
                         clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
                         imxmci_data_done(host, stat);
                 }
         }
 
-        if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
+        if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
 
-                if(host->cmd)
+                if (host->cmd)
                         imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
 
-                if(host->data)
+                if (host->data)
                         imxmci_data_done(host, STATUS_TIME_OUT_READ |
                                          STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
 
-                if(host->req)
+                if (host->req)
                         imxmci_finish_request(host, host->req);
 
                 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
@@ -796,9 +801,8 @@ static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
                 if (req->data->flags & MMC_DATA_WRITE)
                         cmdat |= CMD_DAT_CONT_WRITE;
 
-                if (req->data->flags & MMC_DATA_STREAM) {
+                if (req->data->flags & MMC_DATA_STREAM)
                         cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
-                }
         }
 
         imxmci_start_cmd(host, req->cmd, cmdat);
@@ -811,36 +815,37 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
         struct imxmci_host *host = mmc_priv(mmc);
         int prescaler;
 
-        if( ios->bus_width==MMC_BUS_WIDTH_4 ) {
+        if (ios->bus_width == MMC_BUS_WIDTH_4) {
                 host->actual_bus_width = MMC_BUS_WIDTH_4;
                 imx_gpio_mode(PB11_PF_SD_DAT3);
-        }else{
+        } else {
                 host->actual_bus_width = MMC_BUS_WIDTH_1;
                 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
         }
 
-        if ( host->power_mode != ios->power_mode ) {
+        if (host->power_mode != ios->power_mode) {
                 switch (ios->power_mode) {
                 case MMC_POWER_OFF:
-                        break;
+                        break;
                 case MMC_POWER_UP:
                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
-                        break;
+                        break;
                 case MMC_POWER_ON:
-                        break;
+                        break;
                 }
                 host->power_mode = ios->power_mode;
         }
 
-        if ( ios->clock ) {
+        if (ios->clock) {
                 unsigned int clk;
+                u16 reg;
 
                 /* The prescaler is 5 for PERCLK2 equal to 96MHz
                  * then 96MHz / 5 = 19.2 MHz
                  */
                 clk = clk_get_rate(host->clk);
-                prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE;
-                switch(prescaler) {
+                prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
+                switch (prescaler) {
                 case 0:
                 case 1: prescaler = 0;
                         break;
@@ -858,24 +863,29 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
                 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
                         clk, prescaler);
 
-                for(clk=0; clk<8; clk++) {
+                for (clk = 0; clk < 8; clk++) {
                         int x;
-                        x = CLK_RATE / (1<<clk);
-                        if( x <= ios->clock)
+                        x = CLK_RATE / (1 << clk);
+                        if (x <= ios->clock)
                                 break;
                 }
 
-                MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
+                /* enable controller */
+                reg = readw(host->base + MMC_REG_STR_STP_CLK);
+                writew(reg | STR_STP_CLK_ENABLE,
+                                host->base + MMC_REG_STR_STP_CLK);
 
                 imxmci_stop_clock(host);
-                MMC_CLK_RATE = (prescaler<<3) | clk;
+                writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE);
                 /*
                  * Under my understanding, clock should not be started there, because it would
                  * initiate SDHC sequencer and send last or random command into card
                  */
-                /*imxmci_start_clock(host);*/
+                /* imxmci_start_clock(host); */
 
-                dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
+                dev_dbg(mmc_dev(host->mmc),
+                        "MMC_CLK_RATE: 0x%08x\n",
+                        readw(host->base + MMC_REG_CLK_RATE));
         } else {
                 imxmci_stop_clock(host);
         }
@@ -915,10 +925,10 @@ static void imxmci_check_status(unsigned long data)
                 tasklet_schedule(&host->tasklet);
         }
 
-        if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
-           test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
+        if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
+            test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
                 atomic_inc(&host->stuck_timeout);
-                if(atomic_read(&host->stuck_timeout) > 4)
+                if (atomic_read(&host->stuck_timeout) > 4)
                         tasklet_schedule(&host->tasklet);
         } else {
                 atomic_set(&host->stuck_timeout, 0);
@@ -934,6 +944,7 @@ static int imxmci_probe(struct platform_device *pdev)
         struct imxmci_host *host = NULL;
         struct resource *r;
         int ret = 0, irq;
+        u16 rev_no;
 
         printk(KERN_INFO "i.MX mmc driver\n");
 
@@ -942,7 +953,8 @@ static int imxmci_probe(struct platform_device *pdev)
         if (!r || irq < 0)
                 return -ENXIO;
 
-        if (!request_mem_region(r->start, 0x100, pdev->name))
+        r = request_mem_region(r->start, resource_size(r), pdev->name);
+        if (!r)
                 return -EBUSY;
 
         mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
@@ -966,6 +978,12 @@ static int imxmci_probe(struct platform_device *pdev)
         mmc->max_blk_count = 65535;
 
         host = mmc_priv(mmc);
+        host->base = ioremap(r->start, resource_size(r));
+        if (!host->base) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
         host->mmc = mmc;
         host->dma_allocated = 0;
         host->pdata = pdev->dev.platform_data;
@@ -993,18 +1011,20 @@ static int imxmci_probe(struct platform_device *pdev)
         imx_gpio_mode(PB12_PF_SD_CLK);
         imx_gpio_mode(PB13_PF_SD_CMD);
 
-        imxmci_softreset();
+        imxmci_softreset(host);
 
-        if ( MMC_REV_NO != 0x390 ) {
+        rev_no = readw(host->base + MMC_REG_REV_NO);
+        if (rev_no != 0x390) {
                 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
-                        MMC_REV_NO);
+                        readw(host->base + MMC_REG_REV_NO));
                 goto out;
         }
 
-        MMC_READ_TO = 0x2db4; /* recommended in data sheet */
+        /* recommended in data sheet */
+        writew(0x2db4, host->base + MMC_REG_READ_TO);
 
         host->imask = IMXMCI_INT_MASK_DEFAULT;
-        MMC_INT_MASK = host->imask;
+        writew(host->imask, host->base + MMC_REG_INT_MASK);
 
         host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
         if(host->dma < 0) {
@@ -1012,7 +1032,7 @@ static int imxmci_probe(struct platform_device *pdev)
                 ret = -EBUSY;
                 goto out;
         }
-        host->dma_allocated=1;
+        host->dma_allocated = 1;
         imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
 
         tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
@@ -1032,7 +1052,7 @@ static int imxmci_probe(struct platform_device *pdev)
         host->timer.data = (unsigned long)host;
         host->timer.function = imxmci_check_status;
         add_timer(&host->timer);
-        mod_timer(&host->timer, jiffies + (HZ>>1));
+        mod_timer(&host->timer, jiffies + (HZ >> 1));
 
         platform_set_drvdata(pdev, mmc);
 
@@ -1042,18 +1062,20 @@ static int imxmci_probe(struct platform_device *pdev)
 
 out:
         if (host) {
-                if(host->dma_allocated){
+                if (host->dma_allocated) {
                         imx_dma_free(host->dma);
-                        host->dma_allocated=0;
+                        host->dma_allocated = 0;
                 }
                 if (host->clk) {
                         clk_disable(host->clk);
                         clk_put(host->clk);
                 }
+                if (host->base)
+                        iounmap(host->base);
         }
         if (mmc)
                 mmc_free_host(mmc);
-        release_mem_region(r->start, 0x100);
+        release_mem_region(r->start, resource_size(r));
         return ret;
 }
 
@@ -1072,9 +1094,10 @@ static int imxmci_remove(struct platform_device *pdev)
                 mmc_remove_host(mmc);
 
                 free_irq(host->irq, host);
-                if(host->dma_allocated){
+                iounmap(host->base);
+                if (host->dma_allocated) {
                         imx_dma_free(host->dma);
-                        host->dma_allocated=0;
+                        host->dma_allocated = 0;
                 }
 
                 tasklet_kill(&host->tasklet);
@@ -1082,7 +1105,7 @@ static int imxmci_remove(struct platform_device *pdev)
                 clk_disable(host->clk);
                 clk_put(host->clk);
 
-                release_mem_region(host->res->start, 0x100);
+                release_mem_region(host->res->start, resource_size(host->res));
 
                 mmc_free_host(mmc);
         }
@@ -1109,7 +1132,7 @@ static int imxmci_resume(struct platform_device *dev)
 
         if (mmc) {
                 host = mmc_priv(mmc);
-                if(host)
+                if (host)
                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
                 ret = mmc_resume_host(mmc);
         }
diff --git a/drivers/mmc/host/imxmmc.h b/drivers/mmc/host/imxmmc.h
index e5339e334dbb..09d5d4ee3a77 100644
--- a/drivers/mmc/host/imxmmc.h
+++ b/drivers/mmc/host/imxmmc.h
@@ -1,24 +1,21 @@
+#define MMC_REG_STR_STP_CLK             0x00
+#define MMC_REG_STATUS                  0x04
+#define MMC_REG_CLK_RATE                0x08
+#define MMC_REG_CMD_DAT_CONT            0x0C
+#define MMC_REG_RES_TO                  0x10
+#define MMC_REG_READ_TO                 0x14
+#define MMC_REG_BLK_LEN                 0x18
+#define MMC_REG_NOB                     0x1C
+#define MMC_REG_REV_NO                  0x20
+#define MMC_REG_INT_MASK                0x24
+#define MMC_REG_CMD                     0x28
+#define MMC_REG_ARGH                    0x2C
+#define MMC_REG_ARGL                    0x30
+#define MMC_REG_RES_FIFO                0x34
+#define MMC_REG_BUFFER_ACCESS           0x38
 
-# define __REG16(x)     (*((volatile u16 *)IO_ADDRESS(x)))
-
-#define MMC_STR_STP_CLK  __REG16(IMX_MMC_BASE + 0x00)
-#define MMC_STATUS       __REG16(IMX_MMC_BASE + 0x04)
-#define MMC_CLK_RATE     __REG16(IMX_MMC_BASE + 0x08)
-#define MMC_CMD_DAT_CONT __REG16(IMX_MMC_BASE + 0x0C)
-#define MMC_RES_TO       __REG16(IMX_MMC_BASE + 0x10)
-#define MMC_READ_TO      __REG16(IMX_MMC_BASE + 0x14)
-#define MMC_BLK_LEN      __REG16(IMX_MMC_BASE + 0x18)
-#define MMC_NOB          __REG16(IMX_MMC_BASE + 0x1C)
-#define MMC_REV_NO       __REG16(IMX_MMC_BASE + 0x20)
-#define MMC_INT_MASK     __REG16(IMX_MMC_BASE + 0x24)
-#define MMC_CMD          __REG16(IMX_MMC_BASE + 0x28)
-#define MMC_ARGH         __REG16(IMX_MMC_BASE + 0x2C)
-#define MMC_ARGL         __REG16(IMX_MMC_BASE + 0x30)
-#define MMC_RES_FIFO     __REG16(IMX_MMC_BASE + 0x34)
-#define MMC_BUFFER_ACCESS __REG16(IMX_MMC_BASE + 0x38)
-#define MMC_BUFFER_ACCESS_OFS 0x38
-
-
+#define STR_STP_CLK_IPG_CLK_GATE_DIS    (1<<15)
+#define STR_STP_CLK_IPG_PERCLK_GATE_DIS (1<<14)
 #define STR_STP_CLK_ENDIAN              (1<<5)
 #define STR_STP_CLK_RESET               (1<<3)
 #define STR_STP_CLK_ENABLE              (1<<2)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 2fadf323c696..1bcbdd6763ac 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -500,7 +500,7 @@ static int mmci_probe(struct amba_device *dev, void *id)
         }
 
         host = mmc_priv(mmc);
-        host->clk = clk_get(&dev->dev, "MCLK");
+        host->clk = clk_get(&dev->dev, NULL);
         if (IS_ERR(host->clk)) {
                 ret = PTR_ERR(host->clk);
                 host->clk = NULL;
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index 1b9fc3c6b875..67d7b7fef084 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -1015,7 +1015,7 @@ static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data
         }
 
         if (is_read) {
-                if (host->id == 1) {
+                if (host->id == 0) {
                         sync_dev = OMAP_DMA_MMC_RX;
                         dma_dev_name = "MMC1 read";
                 } else {
@@ -1023,7 +1023,7 @@ static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data
                         dma_dev_name = "MMC2 read";
                 }
         } else {
-                if (host->id == 1) {
+                if (host->id == 0) {
                         sync_dev = OMAP_DMA_MMC_TX;
                         dma_dev_name = "MMC1 write";
                 } else {
@@ -1317,7 +1317,7 @@ static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
         host->slots[id] = slot;
 
         mmc->caps = 0;
-        if (host->pdata->conf.wire4)
+        if (host->pdata->slots[id].wires >= 4)
                 mmc->caps |= MMC_CAP_4_BIT_DATA;
 
         mmc->ops = &mmc_omap_ops;
@@ -1451,6 +1451,7 @@ static int __init mmc_omap_probe(struct platform_device *pdev)
         host->irq = irq;
 
         host->use_dma = 1;
+        host->dev->dma_mask = &pdata->dma_mask;
         host->dma_ch = -1;
 
         host->irq = irq;
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index ebfaa9960939..f88cc7406354 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -26,11 +26,12 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/mmc/host.h>
+#include <linux/io.h>
 
-#include <asm/dma.h>
-#include <asm/io.h>
 #include <asm/sizes.h>
 
+#include <mach/dma.h>
+#include <mach/hardware.h>
 #include <mach/pxa-regs.h>
 #include <mach/mmc.h>
 
@@ -533,7 +534,7 @@ static int pxamci_probe(struct platform_device *pdev)
         host->pdata = pdev->dev.platform_data;
         host->clkrt = CLKRT_OFF;
 
-        host->clk = clk_get(&pdev->dev, "MMCCLK");
+        host->clk = clk_get(&pdev->dev, NULL);
         if (IS_ERR(host->clk)) {
                 ret = PTR_ERR(host->clk);
                 host->clk = NULL;
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 3b2085b57769..fcc98a4cce3c 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -25,7 +25,7 @@
 #include <mach/regs-sdi.h>
 #include <mach/regs-gpio.h>
 
-#include <asm/plat-s3c24xx/mci.h>
+#include <plat/mci.h>
 
 #include "s3cmci.h"
 
diff --git a/drivers/mtd/maps/dc21285.c b/drivers/mtd/maps/dc21285.c
index 3aa018c092f8..42969fe051b2 100644
--- a/drivers/mtd/maps/dc21285.c
+++ b/drivers/mtd/maps/dc21285.c
@@ -32,16 +32,15 @@ static struct mtd_info *dc21285_mtd;
  */
 static void nw_en_write(void)
 {
-        extern spinlock_t gpio_lock;
         unsigned long flags;
 
         /*
          * we want to write a bit pattern XXX1 to Xilinx to enable
          * the write gate, which will be open for about the next 2ms.
          */
-        spin_lock_irqsave(&gpio_lock, flags);
-        cpld_modify(1, 1);
-        spin_unlock_irqrestore(&gpio_lock, flags);
+        spin_lock_irqsave(&nw_gpio_lock, flags);
+        nw_cpld_modify(CPLD_FLASH_WR_ENABLE, CPLD_FLASH_WR_ENABLE);
+        spin_unlock_irqrestore(&nw_gpio_lock, flags);
 
         /*
          * let the ISA bus to catch on...
diff --git a/drivers/mtd/maps/ixp2000.c b/drivers/mtd/maps/ixp2000.c
index dcdb1f17577d..3ea1de9be720 100644
--- a/drivers/mtd/maps/ixp2000.c
+++ b/drivers/mtd/maps/ixp2000.c
@@ -170,7 +170,7 @@ static int ixp2000_flash_probe(struct platform_device *dev)
                 err = -ENOMEM;
                 goto Error;
         }
-        memzero(info, sizeof(struct ixp2000_flash_info));
+        memset(info, 0, sizeof(struct ixp2000_flash_info));
 
         platform_set_drvdata(dev, info);
 
diff --git a/drivers/mtd/maps/ixp4xx.c b/drivers/mtd/maps/ixp4xx.c
index 9c7a5fbd4e51..16555cbeaea4 100644
--- a/drivers/mtd/maps/ixp4xx.c
+++ b/drivers/mtd/maps/ixp4xx.c
@@ -201,7 +201,7 @@ static int ixp4xx_flash_probe(struct platform_device *dev)
                 err = -ENOMEM;
                 goto Error;
         }
-        memzero(info, sizeof(struct ixp4xx_flash_info));
+        memset(info, 0, sizeof(struct ixp4xx_flash_info));
 
         platform_set_drvdata(dev, info);
 
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 1c2e9450d663..f8ae0400c49c 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -408,7 +408,7 @@ config MTD_NAND_FSL_UPM
 
 config MTD_NAND_MXC
         tristate "MXC NAND support"
-        depends on ARCH_MX2
+        depends on ARCH_MX2 || ARCH_MX3
         help
           This enables the driver for the NAND flash controller on the
           MXC processors.
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 15f0a26730ae..fc4144495610 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -20,8 +20,8 @@
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
 #include <linux/irq.h>
-#include <asm/dma.h>
 
+#include <mach/dma.h>
 #include <mach/pxa-regs.h>
 #include <mach/pxa3xx_nand.h>
 
@@ -1080,7 +1080,7 @@ static int pxa3xx_nand_probe(struct platform_device *pdev)
         this = &info->nand_chip;
         mtd->priv = info;
 
-        info->clk = clk_get(&pdev->dev, "NANDCLK");
+        info->clk = clk_get(&pdev->dev, NULL);
         if (IS_ERR(info->clk)) {
                 dev_err(&pdev->dev, "failed to get nand clock\n");
                 ret = PTR_ERR(info->clk);
diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
index 556139ed1fdf..8e375d5fe231 100644
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -45,8 +45,8 @@
 
 #include <asm/io.h>
 
-#include <asm/plat-s3c/regs-nand.h>
-#include <asm/plat-s3c/nand.h>
+#include <plat/regs-nand.h>
+#include <plat/nand.h>
 
 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
 static int hardware_ecc = 1;
@@ -818,7 +818,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev,
                 goto exit_error;
         }
 
-        memzero(info, sizeof(*info));
+        memset(info, 0, sizeof(*info));
         platform_set_drvdata(pdev, info);
 
         spin_lock_init(&info->controller.lock);
@@ -883,7 +883,7 @@ static int s3c24xx_nand_probe(struct platform_device *pdev,
                 goto exit_error;
         }
 
-        memzero(info->mtds, size);
+        memset(info->mtds, 0, size);
 
         /* initialise all possible chips */
 
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index a7e4d985f5ef..d1e0b8e7224b 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -149,7 +149,7 @@ static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 
                 INIT_COMPLETION(c->irq_done);
                 if (c->gpio_irq) {
-                        result = omap_get_gpio_datain(c->gpio_irq);
+                        result = gpio_get_value(c->gpio_irq);
                         if (result == -1) {
                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
@@ -634,9 +634,9 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
                                 "OneNAND\n", c->gpio_irq);
                         goto err_iounmap;
         }
-        omap_set_gpio_direction(c->gpio_irq, 1);
+        gpio_direction_input(c->gpio_irq);
 
-        if ((r = request_irq(OMAP_GPIO_IRQ(c->gpio_irq),
+        if ((r = request_irq(gpio_to_irq(c->gpio_irq),
                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
                              pdev->dev.driver->name, c)) < 0)
                 goto err_release_gpio;
@@ -723,7 +723,7 @@ err_release_dma:
         if (c->dma_channel != -1)
                 omap_free_dma(c->dma_channel);
         if (c->gpio_irq)
-                free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
+                free_irq(gpio_to_irq(c->gpio_irq), c);
 err_release_gpio:
         if (c->gpio_irq)
                 omap_free_gpio(c->gpio_irq);
@@ -760,7 +760,7 @@ static int __devexit omap2_onenand_remove(struct platform_device *pdev)
         omap2_onenand_shutdown(pdev);
         platform_set_drvdata(pdev, NULL);
         if (c->gpio_irq) {
-                free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
+                free_irq(gpio_to_irq(c->gpio_irq), c);
                 omap_free_gpio(c->gpio_irq);
         }
         iounmap(c->onenand.base);
diff --git a/drivers/net/cs89x0.c b/drivers/net/cs89x0.c
index d548a45d59d5..ff6497658a45 100644
--- a/drivers/net/cs89x0.c
+++ b/drivers/net/cs89x0.c
@@ -170,11 +170,7 @@ static char version[] __initdata =
 /* The cs8900 has 4 IRQ pins, software selectable. cs8900_irq_map maps
    them to system IRQ numbers. This mapping is card specific and is set to
    the configuration of the Cirrus Eval board for this chip. */
-#ifdef CONFIG_ARCH_CLPS7500
-static unsigned int netcard_portlist[] __used __initdata =
-   { 0x80090303, 0x300, 0x320, 0x340, 0x360, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0, 0};
-static unsigned int cs8900_irq_map[] = {12,0,0,0};
-#elif defined(CONFIG_SH_HICOSH4)
+#if defined(CONFIG_SH_HICOSH4)
 static unsigned int netcard_portlist[] __used __initdata =
    { 0x0300, 0};
 static unsigned int cs8900_irq_map[] = {1,0,0,0};
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index a0ee05318155..004a9aab3a50 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -22,9 +22,53 @@
 #include <net/irda/wrapper.h>
 #include <net/irda/irda_device.h>
 
-#include <asm/dma.h>
+#include <mach/dma.h>
 #include <mach/irda.h>
+#include <mach/hardware.h>
 #include <mach/pxa-regs.h>
+#include <mach/regs-uart.h>
+
+#define FICP            __REG(0x40800000)  /* Start of FICP area */
+#define ICCR0           __REG(0x40800000)  /* ICP Control Register 0 */
+#define ICCR1           __REG(0x40800004)  /* ICP Control Register 1 */
+#define ICCR2           __REG(0x40800008)  /* ICP Control Register 2 */
+#define ICDR            __REG(0x4080000c)  /* ICP Data Register */
+#define ICSR0           __REG(0x40800014)  /* ICP Status Register 0 */
+#define ICSR1           __REG(0x40800018)  /* ICP Status Register 1 */
+
+#define ICCR0_AME       (1 << 7)        /* Address match enable */
+#define ICCR0_TIE       (1 << 6)        /* Transmit FIFO interrupt enable */
+#define ICCR0_RIE       (1 << 5)        /* Recieve FIFO interrupt enable */
+#define ICCR0_RXE       (1 << 4)        /* Receive enable */
+#define ICCR0_TXE       (1 << 3)        /* Transmit enable */
+#define ICCR0_TUS       (1 << 2)        /* Transmit FIFO underrun select */
+#define ICCR0_LBM       (1 << 1)        /* Loopback mode */
+#define ICCR0_ITR       (1 << 0)        /* IrDA transmission */
+
+#define ICCR2_RXP       (1 << 3)        /* Receive Pin Polarity select */
+#define ICCR2_TXP       (1 << 2)        /* Transmit Pin Polarity select */
+#define ICCR2_TRIG      (3 << 0)        /* Receive FIFO Trigger threshold */
+#define ICCR2_TRIG_8    (0 << 0)        /*      >= 8 bytes */
+#define ICCR2_TRIG_16   (1 << 0)        /*      >= 16 bytes */
+#define ICCR2_TRIG_32   (2 << 0)        /*      >= 32 bytes */
+
+#ifdef CONFIG_PXA27x
+#define ICSR0_EOC       (1 << 6)        /* DMA End of Descriptor Chain */
+#endif
+#define ICSR0_FRE       (1 << 5)        /* Framing error */
+#define ICSR0_RFS       (1 << 4)        /* Receive FIFO service request */
+#define ICSR0_TFS       (1 << 3)        /* Transnit FIFO service request */
+#define ICSR0_RAB       (1 << 2)        /* Receiver abort */
+#define ICSR0_TUR       (1 << 1)        /* Trunsmit FIFO underun */
+#define ICSR0_EIF       (1 << 0)        /* End/Error in FIFO */
+
+#define ICSR1_ROR       (1 << 6)        /* Receiver FIFO underrun  */
+#define ICSR1_CRE       (1 << 5)        /* CRC error */
+#define ICSR1_EOF       (1 << 4)        /* End of frame */
+#define ICSR1_TNF       (1 << 3)        /* Transmit FIFO not full */
+#define ICSR1_RNE       (1 << 2)        /* Receive FIFO not empty */
+#define ICSR1_TBY       (1 << 1)        /* Tramsmiter busy flag */
+#define ICSR1_RSY       (1 << 0)        /* Recevier synchronized flag */
 
 #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
 #define IrSR_RXPL_POS_IS_ZERO 0x0
diff --git a/drivers/net/irda/sa1100_ir.c b/drivers/net/irda/sa1100_ir.c
index ccde5829ba21..d302bcf4c148 100644
--- a/drivers/net/irda/sa1100_ir.c
+++ b/drivers/net/irda/sa1100_ir.c
@@ -36,7 +36,7 @@
 #include <net/irda/irda_device.h>
 
 #include <asm/irq.h>
-#include <asm/dma.h>
+#include <mach/dma.h>
 #include <mach/hardware.h>
 #include <asm/mach/irda.h>
 
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index cc7d85bdfb3e..870b4c33f108 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -200,6 +200,9 @@ static inline void SMC_outsl(struct smc911x_local *lp, int reg,
 
 
 #ifdef SMC_USE_PXA_DMA
+
+#include <mach/dma.h>
+
 /*
  * Define the request and free functions
  * These are unfortunately architecture specific as no generic allocation
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index 3e7c6a3cbc65..c4ccd121bc9c 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -493,7 +493,8 @@ struct smc_local {
  * as RX which can overrun memory and lose packets.
  */
 #include <linux/dma-mapping.h>
-#include <asm/dma.h>
+#include <mach/dma.h>
+#include <mach/hardware.h>
 #include <mach/pxa-regs.h>
 
 #ifdef SMC_insl
diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index 222904411a13..276473543982 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -217,7 +217,7 @@ config PCMCIA_PXA2XX
         depends on ARM && ARCH_PXA && PCMCIA
         depends on (ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL \
                     || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \
-                    || ARCH_VIPER)
+                    || ARCH_VIPER || ARCH_PXA_ESERIES)
         help
           Say Y here to include support for the PXA2xx PCMCIA controller
 
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 238629ad7f7c..bbac46327227 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -72,5 +72,6 @@ pxa2xx-obj-$(CONFIG_ARCH_VIPER)			+= pxa2xx_viper.o
 pxa2xx-obj-$(CONFIG_TRIZEPS_PCMCIA)             += pxa2xx_trizeps4.o
 pxa2xx-obj-$(CONFIG_MACH_PALMTX)                += pxa2xx_palmtx.o
 pxa2xx-obj-$(CONFIG_MACH_PALMLD)                += pxa2xx_palmld.o
+pxa2xx-obj-$(CONFIG_MACH_E740)                  += pxa2xx_e740.o
 
 obj-$(CONFIG_PCMCIA_PXA2XX)                     += pxa2xx_core.o $(pxa2xx-obj-y)
diff --git a/drivers/pcmcia/pxa2xx_e740.c b/drivers/pcmcia/pxa2xx_e740.c
new file mode 100644
index 000000000000..f663a011bf4a
--- /dev/null
+++ b/drivers/pcmcia/pxa2xx_e740.c
@@ -0,0 +1,176 @@
+/*
+ * Toshiba e740 PCMCIA specific routines.
+ *
+ * (c) 2004 Ian Molton <spyro@f2s.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <mach/pxa-regs.h>
+#include <mach/eseries-gpio.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include "soc_common.h"
+
+static struct pcmcia_irqs cd_irqs[] = {
+        {
+                .sock = 0,
+                .irq  = IRQ_GPIO(GPIO_E740_PCMCIA_CD0),
+                .str  = "CF card detect"
+        },
+        {
+                .sock = 1,
+                .irq  = IRQ_GPIO(GPIO_E740_PCMCIA_CD1),
+                .str  = "Wifi switch"
+        },
+};
+
+static int e740_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
+{
+        skt->irq = skt->nr == 0 ? IRQ_GPIO(GPIO_E740_PCMCIA_RDY0) :
+                                IRQ_GPIO(GPIO_E740_PCMCIA_RDY1);
+
+        return soc_pcmcia_request_irqs(skt, &cd_irqs[skt->nr], 1);
+}
+
+/*
+ * Release all resources.
+ */
+static void e740_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
+{
+        soc_pcmcia_free_irqs(skt, &cd_irqs[skt->nr], 1);
+}
+
+static void e740_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
+                                        struct pcmcia_state *state)
+{
+        if (skt->nr == 0) {
+                state->detect = gpio_get_value(GPIO_E740_PCMCIA_CD0) ? 0 : 1;
+                state->ready  = gpio_get_value(GPIO_E740_PCMCIA_RDY0) ? 1 : 0;
+        } else {
+                state->detect = gpio_get_value(GPIO_E740_PCMCIA_CD1) ? 0 : 1;
+                state->ready  = gpio_get_value(GPIO_E740_PCMCIA_RDY1) ? 1 : 0;
+        }
+
+        state->vs_3v  = 1;
+        state->bvd1   = 1;
+        state->bvd2   = 1;
+        state->wrprot = 0;
+        state->vs_Xv  = 0;
+}
+
+static int e740_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
+                                        const socket_state_t *state)
+{
+        if (state->flags & SS_RESET) {
+                if (skt->nr == 0)
+                        gpio_set_value(GPIO_E740_PCMCIA_RST0, 1);
+                else
+                        gpio_set_value(GPIO_E740_PCMCIA_RST1, 1);
+        } else {
+                if (skt->nr == 0)
+                        gpio_set_value(GPIO_E740_PCMCIA_RST0, 0);
+                else
+                        gpio_set_value(GPIO_E740_PCMCIA_RST1, 0);
+        }
+
+        switch (state->Vcc) {
+        case 0: /* Socket off */
+                if (skt->nr == 0)
+                        gpio_set_value(GPIO_E740_PCMCIA_PWR0, 0);
+                else
+                        gpio_set_value(GPIO_E740_PCMCIA_PWR1, 1);
+                break;
+        case 50:
+        case 33: /* socket on */
+                if (skt->nr == 0)
+                        gpio_set_value(GPIO_E740_PCMCIA_PWR0, 1);
+                else
+                        gpio_set_value(GPIO_E740_PCMCIA_PWR1, 0);
+                break;
+        default:
+                printk(KERN_ERR "e740_cs: Unsupported Vcc: %d\n", state->Vcc);
+        }
+
+        return 0;
+}
+
+/*
+ * Enable card status IRQs on (re-)initialisation.  This can
+ * be called at initialisation, power management event, or
+ * pcmcia event.
+ */
+static void e740_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
+{
+        soc_pcmcia_enable_irqs(skt, cd_irqs, ARRAY_SIZE(cd_irqs));
+}
+
+/*
+ * Disable card status IRQs on suspend.
+ */
+static void e740_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
+{
+        soc_pcmcia_disable_irqs(skt, cd_irqs, ARRAY_SIZE(cd_irqs));
+}
+
+static struct pcmcia_low_level e740_pcmcia_ops = {
+        .owner            = THIS_MODULE,
+        .hw_init          = e740_pcmcia_hw_init,
+        .hw_shutdown      = e740_pcmcia_hw_shutdown,
+        .socket_state     = e740_pcmcia_socket_state,
+        .configure_socket = e740_pcmcia_configure_socket,
+        .socket_init      = e740_pcmcia_socket_init,
+        .socket_suspend   = e740_pcmcia_socket_suspend,
+        .nr               = 2,
+};
+
+static struct platform_device *e740_pcmcia_device;
+
+static int __init e740_pcmcia_init(void)
+{
+        int ret;
+
+        if (!machine_is_e740())
+                return -ENODEV;
+
+        e740_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
+        if (!e740_pcmcia_device)
+                return -ENOMEM;
+
+        ret = platform_device_add_data(e740_pcmcia_device, &e740_pcmcia_ops,
+                                        sizeof(e740_pcmcia_ops));
+
+        if (!ret)
+                ret = platform_device_add(e740_pcmcia_device);
+
+        if (ret)
+                platform_device_put(e740_pcmcia_device);
+
+        return ret;
+}
+
+static void __exit e740_pcmcia_exit(void)
+{
+        platform_device_unregister(e740_pcmcia_device);
+}
+
+module_init(e740_pcmcia_init);
+module_exit(e740_pcmcia_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
+MODULE_ALIAS("platform:pxa2xx-pcmcia");
+MODULE_DESCRIPTION("e740 PCMCIA platform support");
diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c
index 2133f37906f2..d5e4e637ddec 100644
--- a/drivers/rtc/rtc-at91sam9.c
+++ b/drivers/rtc/rtc-at91sam9.c
@@ -21,6 +21,7 @@
 
 #include <mach/board.h>
 #include <mach/at91_rtt.h>
+#include <mach/cpu.h>
 
 
 /*
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c
index f59277bbedaa..7a568beba3f0 100644
--- a/drivers/rtc/rtc-s3c.c
+++ b/drivers/rtc/rtc-s3c.c
@@ -26,7 +26,7 @@
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/plat-s3c/regs-rtc.h>
+#include <plat/regs-rtc.h>
 
 /* I have yet to find an S3C implementation with more than one
  * of these rtc blocks in */
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c
index 66a9bb85bbe8..d26a5f82aaba 100644
--- a/drivers/rtc/rtc-sa1100.c
+++ b/drivers/rtc/rtc-sa1100.c
@@ -38,11 +38,11 @@
 #include <mach/pxa-regs.h>
 #endif
 
-#define TIMER_FREQ              CLOCK_TICK_RATE
 #define RTC_DEF_DIVIDER         32768 - 1
 #define RTC_DEF_TRIM            0
 
 static unsigned long rtc_freq = 1024;
+static unsigned long timer_freq;
 static struct rtc_time rtc_alarm;
 static DEFINE_SPINLOCK(sa1100_rtc_lock);
 
@@ -157,7 +157,7 @@ static irqreturn_t timer1_interrupt(int irq, void *dev_id)
         rtc_update_irq(rtc, rtc_timer1_count, RTC_PF | RTC_IRQF);
 
         if (rtc_timer1_count == 1)
-                rtc_timer1_count = (rtc_freq * ((1<<30)/(TIMER_FREQ>>2)));
+                rtc_timer1_count = (rtc_freq * ((1 << 30) / (timer_freq >> 2)));
 
         return IRQ_HANDLED;
 }
@@ -166,7 +166,7 @@ static int sa1100_rtc_read_callback(struct device *dev, int data)
 {
         if (data & RTC_PF) {
                 /* interpolate missed periods and set match for the next */
-                unsigned long period = TIMER_FREQ/rtc_freq;
+                unsigned long period = timer_freq / rtc_freq;
                 unsigned long oscr = OSCR;
                 unsigned long osmr1 = OSMR1;
                 unsigned long missed = (oscr - osmr1)/period;
@@ -263,7 +263,7 @@ static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd,
                 return 0;
         case RTC_PIE_ON:
                 spin_lock_irq(&sa1100_rtc_lock);
-                OSMR1 = TIMER_FREQ/rtc_freq + OSCR;
+                OSMR1 = timer_freq / rtc_freq + OSCR;
                 OIER |= OIER_E1;
                 rtc_timer1_count = 1;
                 spin_unlock_irq(&sa1100_rtc_lock);
@@ -271,7 +271,7 @@ static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd,
         case RTC_IRQP_READ:
                 return put_user(rtc_freq, (unsigned long *)arg);
         case RTC_IRQP_SET:
-                if (arg < 1 || arg > TIMER_FREQ)
+                if (arg < 1 || arg > timer_freq)
                         return -EINVAL;
                 rtc_freq = arg;
                 return 0;
@@ -352,6 +352,8 @@ static int sa1100_rtc_probe(struct platform_device *pdev)
 {
         struct rtc_device *rtc;
 
+        timer_freq = get_clock_tick_rate();
+
         /*
          * According to the manual we should be able to let RTTR be zero
          * and then a default diviser for a 32.768KHz clock is used.
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 579d63a81aa2..b695ab3142d8 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -447,7 +447,7 @@ config SERIAL_CLPS711X_CONSOLE
 
 config SERIAL_SAMSUNG
         tristate "Samsung SoC serial support"
-        depends on ARM && PLAT_S3C24XX
+        depends on ARM && PLAT_S3C
         select SERIAL_CORE
         help
           Support for the on-chip UARTs on the Samsung S3C24XX series CPUs,
@@ -455,6 +455,16 @@ config SERIAL_SAMSUNG
           provide all of these ports, depending on how the serial port
           pins are configured.
 
+config SERIAL_SAMSUNG_UARTS
+        int
+        depends on SERIAL_SAMSUNG
+        default 2 if ARCH_S3C2400
+        default 4 if ARCH_S3C64XX || CPU_S3C2443
+        default 3
+        help
+          Select the number of available UART ports for the Samsung S3C
+          serial driver
+        
 config SERIAL_SAMSUNG_DEBUG
         bool "Samsung SoC serial debug"
         depends on SERIAL_SAMSUNG && DEBUG_LL
@@ -508,7 +518,20 @@ config SERIAL_S3C2440
         help
           Serial port support for the Samsung S3C2440 and S3C2442 SoC
 
+config SERIAL_S3C24A0
+        tristate "Samsung S3C24A0 Serial port support"
+        depends on SERIAL_SAMSUNG && CPU_S3C24A0
+        default y if CPU_S3C24A0
+        help
+          Serial port support for the Samsung S3C24A0 SoC
 
+config SERIAL_S3C6400
+        tristate "Samsung S3C6400/S3C6410 Serial port support"
+        depends on SERIAL_SAMSUNG && (CPU_S3C600 || CPU_S3C6410)
+        default y
+        help
+          Serial port support for the Samsung S3C6400 and S3C6410
+          SoCs
 
 config SERIAL_DZ
         bool "DECstation DZ serial driver"
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 0c17c8ddb19d..dfe775ac45b2 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -41,6 +41,8 @@ obj-$(CONFIG_SERIAL_S3C2400) += s3c2400.o
 obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o
 obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o
 obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
+obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
+obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
 obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
 obj-$(CONFIG_SERIAL_MUX) += mux.o
 obj-$(CONFIG_SERIAL_68328) += 68328serial.o
diff --git a/drivers/serial/amba-pl010.c b/drivers/serial/amba-pl010.c
index 71562689116f..e3a5ad5ef1d6 100644
--- a/drivers/serial/amba-pl010.c
+++ b/drivers/serial/amba-pl010.c
@@ -692,7 +692,7 @@ static int pl010_probe(struct amba_device *dev, void *id)
                 goto free;
         }
 
-        uap->clk = clk_get(&dev->dev, "UARTCLK");
+        uap->clk = clk_get(&dev->dev, NULL);
         if (IS_ERR(uap->clk)) {
                 ret = PTR_ERR(uap->clk);
                 goto unmap;
diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c
index b7180046f8db..8b2b9700f3e4 100644
--- a/drivers/serial/amba-pl011.c
+++ b/drivers/serial/amba-pl011.c
@@ -756,7 +756,7 @@ static int pl011_probe(struct amba_device *dev, void *id)
                 goto free;
         }
 
-        uap->clk = clk_get(&dev->dev, "UARTCLK");
+        uap->clk = clk_get(&dev->dev, NULL);
         if (IS_ERR(uap->clk)) {
                 ret = PTR_ERR(uap->clk);
                 goto unmap;
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c
index 3f90f1bbbbcd..a50954612b60 100644
--- a/drivers/serial/imx.c
+++ b/drivers/serial/imx.c
@@ -66,7 +66,7 @@
 #define ONEMS 0xb0 /* One Millisecond register */
 #define UTS   0xb4 /* UART Test Register */
 #endif
-#ifdef CONFIG_ARCH_IMX
+#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
 #define BIPR1 0xb0 /* Incremental Preset Register 1 */
 #define BIPR2 0xb4 /* Incremental Preset Register 2 */
 #define BIPR3 0xb8 /* Incremental Preset Register 3 */
@@ -96,7 +96,7 @@
 #define  UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
 #define  UCR1_SNDBRK     (1<<4)  /* Send break */
 #define  UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
-#ifdef CONFIG_ARCH_IMX
+#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
 #define  UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled */
 #endif
 #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
@@ -187,11 +187,11 @@
 #define MAX_INTERNAL_IRQ        IMX_IRQS
 #endif
 
-#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
+#ifdef CONFIG_ARCH_MXC
 #define SERIAL_IMX_MAJOR        207
 #define MINOR_START             16
 #define DEV_NAME                "ttymxc"
-#define MAX_INTERNAL_IRQ        MXC_MAX_INT_LINES
+#define MAX_INTERNAL_IRQ        MXC_INTERNAL_IRQS
 #endif
 
 /*
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
index abc00be55433..f6e3b86bb0be 100644
--- a/drivers/serial/pxa.c
+++ b/drivers/serial/pxa.c
@@ -48,6 +48,7 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <mach/pxa-regs.h>
+#include <mach/regs-uart.h>
 
 
 struct uart_pxa_port {
@@ -766,7 +767,7 @@ static int serial_pxa_probe(struct platform_device *dev)
         if (!sport)
                 return -ENOMEM;
 
-        sport->clk = clk_get(&dev->dev, "UARTCLK");
+        sport->clk = clk_get(&dev->dev, NULL);
         if (IS_ERR(sport->clk)) {
                 ret = PTR_ERR(sport->clk);
                 goto err_free;
diff --git a/drivers/serial/s3c24a0.c b/drivers/serial/s3c24a0.c
new file mode 100644
index 000000000000..ebf2fd3c8f7d
--- /dev/null
+++ b/drivers/serial/s3c24a0.c
@@ -0,0 +1,118 @@
+/* linux/drivers/serial/s3c24a0.c
+ *
+ * Driver for Samsung S3C24A0 SoC onboard UARTs.
+ *
+ * Based on drivers/serial/s3c2410.c
+ *
+ * Author: Sandeep Patil <sandeep.patil@azingo.com>
+ *
+ * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+
+#include "samsung.h"
+
+static int s3c24a0_serial_setsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        if (strcmp(clk->name, "uclk") == 0)
+                ucon |= S3C2410_UCON_UCLK;
+        else
+                ucon &= ~S3C2410_UCON_UCLK;
+
+        wr_regl(port, S3C2410_UCON, ucon);
+        return 0;
+}
+
+static int s3c24a0_serial_getsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        clk->divisor = 1;
+        clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
+
+        return 0;
+}
+
+static int s3c24a0_serial_resetport(struct uart_port *port,
+                                    struct s3c2410_uartcfg *cfg)
+{
+        dbg("s3c24a0_serial_resetport: port=%p (%08lx), cfg=%p\n",
+            port, port->mapbase, cfg);
+
+        wr_regl(port, S3C2410_UCON,  cfg->ucon);
+        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+        /* reset both fifos */
+
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+        return 0;
+}
+
+static struct s3c24xx_uart_info s3c24a0_uart_inf = {
+        .name           = "Samsung S3C24A0 UART",
+        .type           = PORT_S3C2410,
+        .fifosize       = 16,
+        .rx_fifomask    = S3C24A0_UFSTAT_RXMASK,
+        .rx_fifoshift   = S3C24A0_UFSTAT_RXSHIFT,
+        .rx_fifofull    = S3C24A0_UFSTAT_RXFULL,
+        .tx_fifofull    = S3C24A0_UFSTAT_TXFULL,
+        .tx_fifomask    = S3C24A0_UFSTAT_TXMASK,
+        .tx_fifoshift   = S3C24A0_UFSTAT_TXSHIFT,
+        .get_clksrc     = s3c24a0_serial_getsource,
+        .set_clksrc     = s3c24a0_serial_setsource,
+        .reset_port     = s3c24a0_serial_resetport,
+};
+
+static int s3c24a0_serial_probe(struct platform_device *dev)
+{
+        return s3c24xx_serial_probe(dev, &s3c24a0_uart_inf);
+}
+
+static struct platform_driver s3c24a0_serial_drv = {
+        .probe          = s3c24a0_serial_probe,
+        .remove         = s3c24xx_serial_remove,
+        .driver         = {
+                .name   = "s3c24a0-uart",
+                .owner  = THIS_MODULE,
+        },
+};
+
+s3c24xx_console_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
+
+static int __init s3c24a0_serial_init(void)
+{
+        return s3c24xx_serial_init(&s3c24a0_serial_drv, &s3c24a0_uart_inf);
+}
+
+static void __exit s3c24a0_serial_exit(void)
+{
+        platform_driver_unregister(&s3c24a0_serial_drv);
+}
+
+module_init(s3c24a0_serial_init);
+module_exit(s3c24a0_serial_exit);
+
diff --git a/drivers/serial/s3c6400.c b/drivers/serial/s3c6400.c
new file mode 100644
index 000000000000..06936d13393f
--- /dev/null
+++ b/drivers/serial/s3c6400.c
@@ -0,0 +1,151 @@
+/* linux/drivers/serial/s3c6400.c
+ *
+ * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs.
+ *
+ * Copyright 2008 Openmoko,  Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+
+#include "samsung.h"
+
+static int s3c6400_serial_setsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        if (strcmp(clk->name, "uclk0") == 0) {
+                ucon &= ~S3C6400_UCON_CLKMASK;
+                ucon |= S3C6400_UCON_UCLK0;
+        } else if (strcmp(clk->name, "uclk1") == 0)
+                ucon |= S3C6400_UCON_UCLK1;
+        else if (strcmp(clk->name, "pclk") == 0) {
+                /* See notes about transitioning from UCLK to PCLK */
+                ucon &= ~S3C6400_UCON_UCLK0;
+        } else {
+                printk(KERN_ERR "unknown clock source %s\n", clk->name);
+                return -EINVAL;
+        }
+
+        wr_regl(port, S3C2410_UCON, ucon);
+        return 0;
+}
+
+
+static int s3c6400_serial_getsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        u32 ucon = rd_regl(port, S3C2410_UCON);
+
+        clk->divisor = 1;
+
+        switch (ucon & S3C6400_UCON_CLKMASK) {
+        case S3C6400_UCON_UCLK0:
+                clk->name = "uclk0";
+                break;
+
+        case S3C6400_UCON_UCLK1:
+                clk->name = "uclk1";
+                break;
+
+        case S3C6400_UCON_PCLK:
+        case S3C6400_UCON_PCLK2:
+                clk->name = "pclk";
+                break;
+        }
+
+        return 0;
+}
+
+static int s3c6400_serial_resetport(struct uart_port *port,
+                                    struct s3c2410_uartcfg *cfg)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n",
+            port, port->mapbase, cfg);
+
+        /* ensure we don't change the clock settings... */
+
+        ucon &= S3C6400_UCON_CLKMASK;
+
+        wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
+        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+        /* reset both fifos */
+
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+        return 0;
+}
+
+static struct s3c24xx_uart_info s3c6400_uart_inf = {
+        .name           = "Samsung S3C6400 UART",
+        .type           = PORT_S3C6400,
+        .fifosize       = 64,
+        .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
+        .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
+        .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
+        .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
+        .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
+        .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
+        .get_clksrc     = s3c6400_serial_getsource,
+        .set_clksrc     = s3c6400_serial_setsource,
+        .reset_port     = s3c6400_serial_resetport,
+};
+
+/* device management */
+
+static int s3c6400_serial_probe(struct platform_device *dev)
+{
+        dbg("s3c6400_serial_probe: dev=%p\n", dev);
+        return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
+}
+
+static struct platform_driver s3c6400_serial_drv = {
+        .probe          = s3c6400_serial_probe,
+        .remove         = s3c24xx_serial_remove,
+        .driver         = {
+                .name   = "s3c6400-uart",
+                .owner  = THIS_MODULE,
+        },
+};
+
+s3c24xx_console_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
+
+static int __init s3c6400_serial_init(void)
+{
+        return s3c24xx_serial_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
+}
+
+static void __exit s3c6400_serial_exit(void)
+{
+        platform_driver_unregister(&s3c6400_serial_drv);
+}
+
+module_init(s3c6400_serial_init);
+module_exit(s3c6400_serial_exit);
+
+MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:s3c6400-uart");
diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c
index 1e219d3d0352..41ac94872b8d 100644
--- a/drivers/serial/samsung.c
+++ b/drivers/serial/samsung.c
@@ -42,13 +42,14 @@
 #include <linux/serial.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
+#include <linux/cpufreq.h>
 
 #include <asm/irq.h>
 
 #include <mach/hardware.h>
+#include <mach/map.h>
 
 #include <plat/regs-serial.h>
-#include <mach/regs-gpio.h>
 
 #include "samsung.h"
 
@@ -58,19 +59,6 @@
 #define S3C24XX_SERIAL_MAJOR    204
 #define S3C24XX_SERIAL_MINOR    64
 
-/* we can support 3 uarts, but not always use them */
-
-#ifdef CONFIG_CPU_S3C2400
-#define NR_PORTS (2)
-#else
-#define NR_PORTS (3)
-#endif
-
-/* port irq numbers */
-
-#define TX_IRQ(port) ((port)->irq + 1)
-#define RX_IRQ(port) ((port)->irq)
-
 /* macros to change one thing to another */
 
 #define tx_enabled(port) ((port)->unused[0])
@@ -136,8 +124,10 @@ static void s3c24xx_serial_rx_disable(struct uart_port *port)
 
 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 {
+        struct s3c24xx_uart_port *ourport = to_ourport(port);
+
         if (tx_enabled(port)) {
-                disable_irq(TX_IRQ(port));
+                disable_irq(ourport->tx_irq);
                 tx_enabled(port) = 0;
                 if (port->flags & UPF_CONS_FLOW)
                         s3c24xx_serial_rx_enable(port);
@@ -146,11 +136,13 @@ static void s3c24xx_serial_stop_tx(struct uart_port *port)
 
 static void s3c24xx_serial_start_tx(struct uart_port *port)
 {
+        struct s3c24xx_uart_port *ourport = to_ourport(port);
+
         if (!tx_enabled(port)) {
                 if (port->flags & UPF_CONS_FLOW)
                         s3c24xx_serial_rx_disable(port);
 
-                enable_irq(TX_IRQ(port));
+                enable_irq(ourport->tx_irq);
                 tx_enabled(port) = 1;
         }
 }
@@ -158,9 +150,11 @@ static void s3c24xx_serial_start_tx(struct uart_port *port)
 
 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 {
+        struct s3c24xx_uart_port *ourport = to_ourport(port);
+
         if (rx_enabled(port)) {
                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
-                disable_irq(RX_IRQ(port));
+                disable_irq(ourport->rx_irq);
                 rx_enabled(port) = 0;
         }
 }
@@ -384,13 +378,13 @@ static void s3c24xx_serial_shutdown(struct uart_port *port)
         struct s3c24xx_uart_port *ourport = to_ourport(port);
 
         if (ourport->tx_claimed) {
-                free_irq(TX_IRQ(port), ourport);
+                free_irq(ourport->tx_irq, ourport);
                 tx_enabled(port) = 0;
                 ourport->tx_claimed = 0;
         }
 
         if (ourport->rx_claimed) {
-                free_irq(RX_IRQ(port), ourport);
+                free_irq(ourport->rx_irq, ourport);
                 ourport->rx_claimed = 0;
                 rx_enabled(port) = 0;
         }
@@ -407,12 +401,11 @@ static int s3c24xx_serial_startup(struct uart_port *port)
 
         rx_enabled(port) = 1;
 
-        ret = request_irq(RX_IRQ(port),
-                          s3c24xx_serial_rx_chars, 0,
+        ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
                           s3c24xx_serial_portname(port), ourport);
 
         if (ret != 0) {
-                printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
+                printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
                 return ret;
         }
 
@@ -422,12 +415,11 @@ static int s3c24xx_serial_startup(struct uart_port *port)
 
         tx_enabled(port) = 1;
 
-        ret = request_irq(TX_IRQ(port),
-                          s3c24xx_serial_tx_chars, 0,
+        ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
                           s3c24xx_serial_portname(port), ourport);
 
         if (ret) {
-                printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
+                printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
                 goto err;
         }
 
@@ -452,6 +444,8 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
 {
         struct s3c24xx_uart_port *ourport = to_ourport(port);
 
+        ourport->pm_level = level;
+
         switch (level) {
         case 3:
                 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
@@ -661,6 +655,7 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
 
                 ourport->clksrc = clksrc;
                 ourport->baudclk = clk;
+                ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
         }
 
         switch (termios->c_cflag & CSIZE) {
@@ -752,6 +747,8 @@ static const char *s3c24xx_serial_type(struct uart_port *port)
                 return "S3C2440";
         case PORT_S3C2412:
                 return "S3C2412";
+        case PORT_S3C6400:
+                return "S3C6400/10";
         default:
                 return NULL;
         }
@@ -827,14 +824,14 @@ static struct uart_ops s3c24xx_serial_ops = {
 static struct uart_driver s3c24xx_uart_drv = {
         .owner          = THIS_MODULE,
         .dev_name       = "s3c2410_serial",
-        .nr             = 3,
+        .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
         .cons           = S3C24XX_SERIAL_CONSOLE,
         .driver_name    = S3C24XX_SERIAL_NAME,
         .major          = S3C24XX_SERIAL_MAJOR,
         .minor          = S3C24XX_SERIAL_MINOR,
 };
 
-static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
+static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
         [0] = {
                 .port = {
                         .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
@@ -859,7 +856,7 @@ static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
                         .line           = 1,
                 }
         },
-#if NR_PORTS > 2
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
 
         [2] = {
                 .port = {
@@ -872,6 +869,20 @@ static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
                         .flags          = UPF_BOOT_AUTOCONF,
                         .line           = 2,
                 }
+        },
+#endif
+#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
+        [3] = {
+                .port = {
+                        .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
+                        .iotype         = UPIO_MEM,
+                        .irq            = IRQ_S3CUART_RX3,
+                        .uartclk        = 0,
+                        .fifosize       = 16,
+                        .ops            = &s3c24xx_serial_ops,
+                        .flags          = UPF_BOOT_AUTOCONF,
+                        .line           = 3,
+                }
         }
 #endif
 };
@@ -890,6 +901,89 @@ static inline int s3c24xx_serial_resetport(struct uart_port *port,
         return (info->reset_port)(port, cfg);
 }
 
+
+#ifdef CONFIG_CPU_FREQ
+
+static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
+                                             unsigned long val, void *data)
+{
+        struct s3c24xx_uart_port *port;
+        struct uart_port *uport;
+
+        port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
+        uport = &port->port;
+
+        /* check to see if port is enabled */
+
+        if (port->pm_level != 0)
+                return 0;
+
+        /* try and work out if the baudrate is changing, we can detect
+         * a change in rate, but we do not have support for detecting
+         * a disturbance in the clock-rate over the change.
+         */
+
+        if (IS_ERR(port->clk))
+                goto exit;
+
+        if (port->baudclk_rate == clk_get_rate(port->clk))
+                goto exit;
+
+        if (val == CPUFREQ_PRECHANGE) {
+                /* we should really shut the port down whilst the
+                 * frequency change is in progress. */
+
+        } else if (val == CPUFREQ_POSTCHANGE) {
+                struct ktermios *termios;
+                struct tty_struct *tty;
+
+                if (uport->info == NULL)
+                        goto exit;
+
+                tty = uport->info->port.tty;
+
+                if (tty == NULL)
+                        goto exit;
+
+                termios = tty->termios;
+
+                if (termios == NULL) {
+                        printk(KERN_WARNING "%s: no termios?\n", __func__);
+                        goto exit;
+                }
+
+                s3c24xx_serial_set_termios(uport, termios, NULL);
+        }
+
+ exit:
+        return 0;
+}
+
+static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
+{
+        port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
+
+        return cpufreq_register_notifier(&port->freq_transition,
+                                         CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
+{
+        cpufreq_unregister_notifier(&port->freq_transition,
+                                    CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+#else
+static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
+{
+        return 0;
+}
+
+static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
+{
+}
+#endif
+
 /* s3c24xx_serial_init_port
  *
  * initialise a single serial port from the platform device given
@@ -914,8 +1008,11 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
         if (port->mapbase != 0)
                 return 0;
 
-        if (cfg->hwport > 3)
-                return -EINVAL;
+        if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
+                printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
+                       cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
+                return -ERANGE;
+        }
 
         /* setup info for port */
         port->dev       = &platdev->dev;
@@ -943,18 +1040,26 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
 
         dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
 
-        port->mapbase   = res->start;
-        port->membase   = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
+        port->mapbase = res->start;
+        port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000);
         ret = platform_get_irq(platdev, 0);
         if (ret < 0)
                 port->irq = 0;
-        else
+        else {
                 port->irq = ret;
+                ourport->rx_irq = ret;
+                ourport->tx_irq = ret + 1;
+        }
+        
+        ret = platform_get_irq(platdev, 1);
+        if (ret > 0)
+                ourport->tx_irq = ret;
 
         ourport->clk    = clk_get(&platdev->dev, "uart");
 
-        dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
-            port->mapbase, port->membase, port->irq, port->uartclk);
+        dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
+            port->mapbase, port->membase, port->irq,
+            ourport->rx_irq, ourport->tx_irq, port->uartclk);
 
         /* reset the fifos (and setup the uart) */
         s3c24xx_serial_resetport(port, cfg);
@@ -1002,6 +1107,10 @@ int s3c24xx_serial_probe(struct platform_device *dev,
         if (ret < 0)
                 printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__);
 
+        ret = s3c24xx_serial_cpufreq_register(ourport);
+        if (ret < 0)
+                dev_err(&dev->dev, "failed to add cpufreq notifier\n");
+
         return 0;
 
  probe_err:
@@ -1015,6 +1124,7 @@ int s3c24xx_serial_remove(struct platform_device *dev)
         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
 
         if (port) {
+                s3c24xx_serial_cpufreq_deregister(to_ourport(port));
                 device_remove_file(&dev->dev, &dev_attr_clock_source);
                 uart_remove_one_port(&s3c24xx_uart_drv, port);
         }
@@ -1219,7 +1329,7 @@ static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
 
         platdev_ptr = s3c24xx_uart_devs;
 
-        for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
+        for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) {
                 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
         }
 
@@ -1240,7 +1350,7 @@ s3c24xx_serial_console_setup(struct console *co, char *options)
 
         /* is this a valid port */
 
-        if (co->index == -1 || co->index >= NR_PORTS)
+        if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
                 co->index = 0;
 
         port = &s3c24xx_serial_ports[co->index].port;
diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h
index 5c92ebbe7d9e..571d6b90d206 100644
--- a/drivers/serial/samsung.h
+++ b/drivers/serial/samsung.h
@@ -33,12 +33,21 @@ struct s3c24xx_uart_info {
 struct s3c24xx_uart_port {
         unsigned char                   rx_claimed;
         unsigned char                   tx_claimed;
+        unsigned int                    pm_level;
+        unsigned long                   baudclk_rate;
+
+        unsigned int                    rx_irq;
+        unsigned int                    tx_irq;
 
         struct s3c24xx_uart_info        *info;
         struct s3c24xx_uart_clksrc      *clksrc;
         struct clk                      *clk;
         struct clk                      *baudclk;
         struct uart_port                port;
+
+#ifdef CONFIG_CPU_FREQ
+        struct notifier_block           freq_transition;
+#endif
 };
 
 /* conversion functions */
diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c
index 61dc8b3daa26..a7bf024a8286 100644
--- a/drivers/serial/serial_lh7a40x.c
+++ b/drivers/serial/serial_lh7a40x.c
@@ -41,9 +41,10 @@
 #include <linux/tty_flip.h>
 #include <linux/serial_core.h>
 #include <linux/serial.h>
+#include <linux/io.h>
 
-#include <asm/io.h>
 #include <asm/irq.h>
+#include <mach/hardware.h>
 
 #define DEV_MAJOR       204
 #define DEV_MINOR       16
diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c
index cf12f2d84be2..6104f461a3cd 100644
--- a/drivers/spi/pxa2xx_spi.c
+++ b/drivers/spi/pxa2xx_spi.c
@@ -32,8 +32,8 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/delay.h>
-#include <asm/dma.h>
 
+#include <mach/dma.h>
 #include <mach/hardware.h>
 #include <mach/pxa-regs.h>
 #include <mach/regs-ssp.h>
diff --git a/drivers/spi/spi_s3c24xx.c b/drivers/spi/spi_s3c24xx.c
index c252cbac00f1..256d18395a23 100644
--- a/drivers/spi/spi_s3c24xx.c
+++ b/drivers/spi/spi_s3c24xx.c
@@ -28,7 +28,7 @@
 #include <mach/hardware.h>
 
 #include <mach/regs-gpio.h>
-#include <asm/plat-s3c24xx/regs-spi.h>
+#include <plat/regs-spi.h>
 #include <mach/spi.h>
 
 struct s3c24xx_spi {
diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c
index 2dbc0db0b46c..8c5026be79d4 100644
--- a/drivers/usb/gadget/pxa25x_udc.c
+++ b/drivers/usb/gadget/pxa25x_udc.c
@@ -2145,7 +2145,7 @@ static int __init pxa25x_udc_probe(struct platform_device *pdev)
         if (irq < 0)
                 return -ENODEV;
 
-        dev->clk = clk_get(&pdev->dev, "UDCCLK");
+        dev->clk = clk_get(&pdev->dev, NULL);
         if (IS_ERR(dev->clk)) {
                 retval = PTR_ERR(dev->clk);
                 goto err_clk;
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index caa37c95802c..944e4ff641df 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -2226,7 +2226,7 @@ static int __init pxa_udc_probe(struct platform_device *pdev)
         udc->dev = &pdev->dev;
         udc->mach = pdev->dev.platform_data;
 
-        udc->clk = clk_get(&pdev->dev, "UDCCLK");
+        udc->clk = clk_get(&pdev->dev, NULL);
         if (IS_ERR(udc->clk)) {
                 retval = PTR_ERR(udc->clk);
                 goto err_clk;
diff --git a/drivers/usb/gadget/s3c2410_udc.c b/drivers/usb/gadget/s3c2410_udc.c
index 00ba06b44752..8d8d65165983 100644
--- a/drivers/usb/gadget/s3c2410_udc.c
+++ b/drivers/usb/gadget/s3c2410_udc.c
@@ -53,8 +53,8 @@
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 
-#include <asm/plat-s3c24xx/regs-udc.h>
-#include <asm/plat-s3c24xx/udc.h>
+#include <plat/regs-udc.h>
+#include <plat/udc.h>
 
 
 #include "s3c2410_udc.h"
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
index 5416cf969005..9d487908012e 100644
--- a/drivers/usb/host/ehci-orion.c
+++ b/drivers/usb/host/ehci-orion.c
@@ -33,8 +33,9 @@
 /*
  * Implement Orion USB controller specification guidelines
  */
-static void orion_usb_setup(struct usb_hcd *hcd)
+static void orion_usb_phy_v1_setup(struct usb_hcd *hcd)
 {
+        /* The below GLs are according to the Orion Errata document */
         /*
          * Clear interrupt cause and mask
          */
@@ -258,9 +259,19 @@ static int __init ehci_orion_drv_probe(struct platform_device *pdev)
                 ehci_orion_conf_mbus_windows(hcd, pd->dram);
 
         /*
-         * setup Orion USB controller
+         * setup Orion USB controller.
          */
-        orion_usb_setup(hcd);
+        switch (pd->phy_version) {
+        case EHCI_PHY_NA:       /* dont change USB phy settings */
+                break;
+        case EHCI_PHY_ORION:
+                orion_usb_phy_v1_setup(hcd);
+                break;
+        case EHCI_PHY_DD:
+        case EHCI_PHY_KW:
+        default:
+                printk(KERN_WARNING "Orion ehci -USB phy version isn't supported.\n");
+        }
 
         err = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_DISABLED);
         if (err)
diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
index 91697bdb399f..4bbddb73abd9 100644
--- a/drivers/usb/host/ohci-omap.c
+++ b/drivers/usb/host/ohci-omap.c
@@ -18,6 +18,7 @@
 #include <linux/jiffies.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/gpio.h>
 
 #include <mach/hardware.h>
 #include <asm/io.h>
@@ -25,7 +26,6 @@
 
 #include <mach/mux.h>
 #include <mach/irqs.h>
-#include <mach/gpio.h>
 #include <mach/fpga.h>
 #include <mach/usb.h>
 
@@ -254,8 +254,8 @@ static int ohci_omap_init(struct usb_hcd *hcd)
 
                         /* gpio9 for overcurrent detction */
                         omap_cfg_reg(W8_1610_GPIO9);
-                        omap_request_gpio(9);
-                        omap_set_gpio_direction(9, 1 /* IN */);
+                        gpio_request(9, "OHCI overcurrent");
+                        gpio_direction_input(9);
 
                         /* for paranoia's sake:  disable USB.PUEN */
                         omap_cfg_reg(W4_USB_HIGHZ);
@@ -407,7 +407,7 @@ usb_hcd_omap_remove (struct usb_hcd *hcd, struct platform_device *pdev)
                 put_device(ohci->transceiver->dev);
         }
         if (machine_is_omap_osk())
-                omap_free_gpio(9);
+                gpio_free(9);
         iounmap(hcd->regs);
         release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
         usb_put_hcd(hcd);
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index e294d430733b..e44dc2cbca24 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -296,7 +296,7 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
                 return -ENXIO;
         }
 
-        usb_clk = clk_get(&pdev->dev, "USBCLK");
+        usb_clk = clk_get(&pdev->dev, NULL);
         if (IS_ERR(usb_clk))
                 return PTR_ERR(usb_clk);
 
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d0c821992a99..6372f8b17b45 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -362,7 +362,7 @@ endchoice
 
 config FB_ACORN
         bool "Acorn VIDC support"
-        depends on (FB = y) && ARM && (ARCH_ACORN || ARCH_CLPS7500)
+        depends on (FB = y) && ARM && ARCH_ACORN
         select FB_CFB_FILLRECT
         select FB_CFB_COPYAREA
         select FB_CFB_IMAGEBLIT
@@ -1817,6 +1817,11 @@ config FB_PXA
 
           If unsure, say N.
 
+config FB_PXA_OVERLAY
+        bool "Support PXA27x/PXA3xx Overlay(s) as framebuffer"
+        default n
+        depends on FB_PXA && (PXA27x || PXA3xx)
+
 config FB_PXA_SMARTPANEL
         bool "PXA Smartpanel LCD support"
         default n
diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c
index a7a1c891bfa2..2ac52fd8cc11 100644
--- a/drivers/video/amba-clcd.c
+++ b/drivers/video/amba-clcd.c
@@ -343,14 +343,14 @@ static int clcdfb_register(struct clcd_fb *fb)
 {
         int ret;
 
-        fb->clk = clk_get(&fb->dev->dev, "CLCDCLK");
+        fb->clk = clk_get(&fb->dev->dev, NULL);
         if (IS_ERR(fb->clk)) {
                 ret = PTR_ERR(fb->clk);
                 goto out;
         }
 
         fb->fb.fix.mmio_start   = fb->dev->res.start;
-        fb->fb.fix.mmio_len     = SZ_4K;
+        fb->fb.fix.mmio_len     = 4096;
 
         fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
         if (!fb->regs) {
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index ccd986140c95..d58c68cd456e 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -1,6 +1,4 @@
 /*
- *  linux/drivers/video/imxfb.c
- *
  *  Freescale i.MX Frame Buffer device driver
  *
  *  Copyright (C) 2004 Sascha Hauer, Pengutronix
@@ -16,7 +14,6 @@
  *      linux-arm-kernel@lists.arm.linux.org.uk
  */
 
-//#define DEBUG 1
 
 #include <linux/module.h>
 #include <linux/kernel.h>
@@ -32,9 +29,8 @@
 #include <linux/cpufreq.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
+#include <linux/io.h>
 
-#include <mach/hardware.h>
-#include <asm/io.h>
 #include <mach/imxfb.h>
 
 /*
@@ -42,23 +38,150 @@
  */
 #define DEBUG_VAR 1
 
-#include "imxfb.h"
+#define DRIVER_NAME "imx-fb"
+
+#define LCDC_SSA        0x00
+
+#define LCDC_SIZE       0x04
+#define SIZE_XMAX(x)    ((((x) >> 4) & 0x3f) << 20)
+#define SIZE_YMAX(y)    ((y) & 0x1ff)
+
+#define LCDC_VPW        0x08
+#define VPW_VPW(x)      ((x) & 0x3ff)
+
+#define LCDC_CPOS       0x0C
+#define CPOS_CC1        (1<<31)
+#define CPOS_CC0        (1<<30)
+#define CPOS_OP         (1<<28)
+#define CPOS_CXP(x)     (((x) & 3ff) << 16)
+#define CPOS_CYP(y)     ((y) & 0x1ff)
+
+#define LCDC_LCWHB      0x10
+#define LCWHB_BK_EN     (1<<31)
+#define LCWHB_CW(w)     (((w) & 0x1f) << 24)
+#define LCWHB_CH(h)     (((h) & 0x1f) << 16)
+#define LCWHB_BD(x)     ((x) & 0xff)
+
+#define LCDC_LCHCC      0x14
+#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
+#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
+#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
+
+#define LCDC_PCR        0x18
+
+#define LCDC_HCR        0x1C
+#define HCR_H_WIDTH(x)  (((x) & 0x3f) << 26)
+#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
+#define HCR_H_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_VCR        0x20
+#define VCR_V_WIDTH(x)  (((x) & 0x3f) << 26)
+#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
+#define VCR_V_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_POS        0x24
+#define POS_POS(x)      ((x) & 1f)
+
+#define LCDC_LSCR1      0x28
+/* bit fields in imxfb.h */
+
+#define LCDC_PWMR       0x2C
+/* bit fields in imxfb.h */
+
+#define LCDC_DMACR      0x30
+/* bit fields in imxfb.h */
+
+#define LCDC_RMCR       0x34
+#define RMCR_LCDC_EN    (1<<1)
+#define RMCR_SELF_REF   (1<<0)
+
+#define LCDC_LCDICR     0x38
+#define LCDICR_INT_SYN  (1<<2)
+#define LCDICR_INT_CON  (1)
+
+#define LCDC_LCDISR     0x40
+#define LCDISR_UDR_ERR  (1<<3)
+#define LCDISR_ERR_RES  (1<<2)
+#define LCDISR_EOF      (1<<1)
+#define LCDISR_BOF      (1<<0)
+
+/*
+ * These are the bitfields for each
+ * display depth that we support.
+ */
+struct imxfb_rgb {
+        struct fb_bitfield      red;
+        struct fb_bitfield      green;
+        struct fb_bitfield      blue;
+        struct fb_bitfield      transp;
+};
+
+struct imxfb_info {
+        struct platform_device  *pdev;
+        void __iomem            *regs;
 
-static struct imxfb_rgb def_rgb_16 = {
-        .red    = { .offset = 8,  .length = 4, },
-        .green  = { .offset = 4,  .length = 4, },
-        .blue   = { .offset = 0,  .length = 4, },
-        .transp = { .offset = 0,  .length = 0, },
+        u_int                   max_bpp;
+        u_int                   max_xres;
+        u_int                   max_yres;
+
+        /*
+         * These are the addresses we mapped
+         * the framebuffer memory region to.
+         */
+        dma_addr_t              map_dma;
+        u_char                  *map_cpu;
+        u_int                   map_size;
+
+        u_char                  *screen_cpu;
+        dma_addr_t              screen_dma;
+        u_int                   palette_size;
+
+        dma_addr_t              dbar1;
+        dma_addr_t              dbar2;
+
+        u_int                   pcr;
+        u_int                   pwmr;
+        u_int                   lscr1;
+        u_int                   dmacr;
+        u_int                   cmap_inverse:1,
+                                cmap_static:1,
+                                unused:30;
+
+        void (*lcd_power)(int);
+        void (*backlight_power)(int);
+};
+
+#define IMX_NAME        "IMX"
+
+/*
+ * Minimum X and Y resolutions
+ */
+#define MIN_XRES        64
+#define MIN_YRES        64
+
+static struct imxfb_rgb def_rgb_16_tft = {
+        .red    = {.offset = 11, .length = 5,},
+        .green  = {.offset = 5, .length = 6,},
+        .blue   = {.offset = 0, .length = 5,},
+        .transp = {.offset = 0, .length = 0,},
+};
+
+static struct imxfb_rgb def_rgb_16_stn = {
+        .red    = {.offset = 8, .length = 4,},
+        .green  = {.offset = 4, .length = 4,},
+        .blue   = {.offset = 0, .length = 4,},
+        .transp = {.offset = 0, .length = 0,},
 };
 
 static struct imxfb_rgb def_rgb_8 = {
-        .red    = { .offset = 0,  .length = 8, },
-        .green  = { .offset = 0,  .length = 8, },
-        .blue   = { .offset = 0,  .length = 8, },
-        .transp = { .offset = 0,  .length = 0, },
+        .red    = {.offset = 0, .length = 8,},
+        .green  = {.offset = 0, .length = 8,},
+        .blue   = {.offset = 0, .length = 8,},
+        .transp = {.offset = 0, .length = 0,},
 };
 
-static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info);
+static int imxfb_activate_var(struct fb_var_screeninfo *var,
+                struct fb_info *info);
 
 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
 {
@@ -67,10 +190,8 @@ static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
         return chan << bf->offset;
 }
 
-#define LCDC_PALETTE(x) __REG2(IMX_LCDC_BASE+0x800, (x)<<2)
-static int
-imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
-                       u_int trans, struct fb_info *info)
+static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
+                u_int trans, struct fb_info *info)
 {
         struct imxfb_info *fbi = info->par;
         u_int val, ret = 1;
@@ -81,14 +202,13 @@ imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
                       (CNVT_TOHW(green,4) << 4) |
                       CNVT_TOHW(blue,  4);
 
-                LCDC_PALETTE(regno) = val;
+                writel(val, fbi->regs + 0x800 + (regno << 2));
                 ret = 0;
         }
         return ret;
 }
 
-static int
-imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
+static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
                    u_int trans, struct fb_info *info)
 {
         struct imxfb_info *fbi = info->par;
@@ -148,11 +268,10 @@ imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
  *    bitfields, horizontal timing, vertical timing.
  */
-static int
-imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 {
         struct imxfb_info *fbi = info->par;
-        int rgbidx;
+        struct imxfb_rgb *rgb;
 
         if (var->xres < MIN_XRES)
                 var->xres = MIN_XRES;
@@ -168,23 +287,25 @@ imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
         pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel);
         switch (var->bits_per_pixel) {
         case 16:
-                rgbidx = RGB_16;
+        default:
+                if (readl(fbi->regs + LCDC_PCR) & PCR_TFT)
+                        rgb = &def_rgb_16_tft;
+                else
+                        rgb = &def_rgb_16_stn;
                 break;
         case 8:
-                rgbidx = RGB_8;
+                rgb = &def_rgb_8;
                 break;
-        default:
-                rgbidx = RGB_16;
         }
 
         /*
          * Copy the RGB parameters for this display
          * from the machine specific parameters.
          */
-        var->red    = fbi->rgb[rgbidx]->red;
-        var->green  = fbi->rgb[rgbidx]->green;
-        var->blue   = fbi->rgb[rgbidx]->blue;
-        var->transp = fbi->rgb[rgbidx]->transp;
+        var->red    = rgb->red;
+        var->green  = rgb->green;
+        var->blue   = rgb->blue;
+        var->transp = rgb->transp;
 
         pr_debug("RGBT length = %d:%d:%d:%d\n",
                 var->red.length, var->green.length, var->blue.length,
@@ -221,8 +342,7 @@ static int imxfb_set_par(struct fb_info *info)
                 info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
         }
 
-        info->fix.line_length = var->xres_virtual *
-                                  var->bits_per_pixel / 8;
+        info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8;
         fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
 
         imxfb_activate_var(var, info);
@@ -235,22 +355,27 @@ static void imxfb_enable_controller(struct imxfb_info *fbi)
         pr_debug("Enabling LCD controller\n");
 
         /* initialize LCDC */
-        LCDC_RMCR &= ~RMCR_LCDC_EN;             /* just to be safe... */
+        writel(readl(fbi->regs + LCDC_RMCR) & ~RMCR_LCDC_EN,
+                fbi->regs + LCDC_RMCR); /* just to be safe... */
+
+        writel(fbi->screen_dma, fbi->regs + LCDC_SSA);
 
-        LCDC_SSA        = fbi->screen_dma;
         /* physical screen start address            */
-        LCDC_VPW        = VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4);
+        writel(VPW_VPW(fbi->max_xres * fbi->max_bpp / 8 / 4),
+                fbi->regs + LCDC_VPW);
 
-        LCDC_POS        = 0x00000000;   /* panning offset 0 (0 pixel offset)        */
+        /* panning offset 0 (0 pixel offset)        */
+        writel(0x00000000, fbi->regs + LCDC_POS);
 
         /* disable hardware cursor */
-        LCDC_CPOS       &= ~(CPOS_CC0 | CPOS_CC1);
+        writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
+                fbi->regs + LCDC_CPOS);
 
-        LCDC_RMCR = RMCR_LCDC_EN;
+        writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
 
-        if(fbi->backlight_power)
+        if (fbi->backlight_power)
                 fbi->backlight_power(1);
-        if(fbi->lcd_power)
+        if (fbi->lcd_power)
                 fbi->lcd_power(1);
 }
 
@@ -258,12 +383,12 @@ static void imxfb_disable_controller(struct imxfb_info *fbi)
 {
         pr_debug("Disabling LCD controller\n");
 
-        if(fbi->backlight_power)
+        if (fbi->backlight_power)
                 fbi->backlight_power(0);
-        if(fbi->lcd_power)
+        if (fbi->lcd_power)
                 fbi->lcd_power(0);
 
-        LCDC_RMCR = 0;
+        writel(0, fbi->regs + LCDC_RMCR);
 }
 
 static int imxfb_blank(int blank, struct fb_info *info)
@@ -340,74 +465,26 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf
                         info->fix.id, var->lower_margin);
 #endif
 
-        LCDC_HCR        = HCR_H_WIDTH(var->hsync_len) |
-                          HCR_H_WAIT_1(var->left_margin) |
-                          HCR_H_WAIT_2(var->right_margin);
+        writel(HCR_H_WIDTH(var->hsync_len) |
+                HCR_H_WAIT_1(var->right_margin) |
+                HCR_H_WAIT_2(var->left_margin),
+                fbi->regs + LCDC_HCR);
 
-        LCDC_VCR        = VCR_V_WIDTH(var->vsync_len) |
-                          VCR_V_WAIT_1(var->upper_margin) |
-                          VCR_V_WAIT_2(var->lower_margin);
+        writel(VCR_V_WIDTH(var->vsync_len) |
+                VCR_V_WAIT_1(var->lower_margin) |
+                VCR_V_WAIT_2(var->upper_margin),
+                fbi->regs + LCDC_VCR);
 
-        LCDC_SIZE       = SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres);
-        LCDC_PCR        = fbi->pcr;
-        LCDC_PWMR       = fbi->pwmr;
-        LCDC_LSCR1      = fbi->lscr1;
-        LCDC_DMACR      = fbi->dmacr;
+        writel(SIZE_XMAX(var->xres) | SIZE_YMAX(var->yres),
+                        fbi->regs + LCDC_SIZE);
+        writel(fbi->pcr, fbi->regs + LCDC_PCR);
+        writel(fbi->pwmr, fbi->regs + LCDC_PWMR);
+        writel(fbi->lscr1, fbi->regs + LCDC_LSCR1);
+        writel(fbi->dmacr, fbi->regs + LCDC_DMACR);
 
         return 0;
 }
 
-static void imxfb_setup_gpio(struct imxfb_info *fbi)
-{
-        int width;
-
-        LCDC_RMCR       &= ~(RMCR_LCDC_EN | RMCR_SELF_REF);
-
-        if( fbi->pcr & PCR_TFT )
-                width = 16;
-        else
-                width = 1 << ((fbi->pcr >> 28) & 0x3);
-
-        switch(width) {
-        case 16:
-                imx_gpio_mode(PD30_PF_LD15);
-                imx_gpio_mode(PD29_PF_LD14);
-                imx_gpio_mode(PD28_PF_LD13);
-                imx_gpio_mode(PD27_PF_LD12);
-                imx_gpio_mode(PD26_PF_LD11);
-                imx_gpio_mode(PD25_PF_LD10);
-                imx_gpio_mode(PD24_PF_LD9);
-                imx_gpio_mode(PD23_PF_LD8);
-        case 8:
-                imx_gpio_mode(PD22_PF_LD7);
-                imx_gpio_mode(PD21_PF_LD6);
-                imx_gpio_mode(PD20_PF_LD5);
-                imx_gpio_mode(PD19_PF_LD4);
-        case 4:
-                imx_gpio_mode(PD18_PF_LD3);
-                imx_gpio_mode(PD17_PF_LD2);
-        case 2:
-                imx_gpio_mode(PD16_PF_LD1);
-        case 1:
-                imx_gpio_mode(PD15_PF_LD0);
-        }
-
-        /* initialize GPIOs */
-        imx_gpio_mode(PD6_PF_LSCLK);
-        imx_gpio_mode(PD11_PF_CONTRAST);
-        imx_gpio_mode(PD14_PF_FLM_VSYNC);
-        imx_gpio_mode(PD13_PF_LP_HSYNC);
-        imx_gpio_mode(PD12_PF_ACD_OE);
-
-        /* These are only needed for Sharp HR TFT displays */
-        if (fbi->pcr & PCR_SHARP) {
-                imx_gpio_mode(PD7_PF_REV);
-                imx_gpio_mode(PD8_PF_CLS);
-                imx_gpio_mode(PD9_PF_PS);
-                imx_gpio_mode(PD10_PF_SPL_SPR);
-        }
-}
-
 #ifdef CONFIG_PM
 /*
  * Power management hooks.  Note that we won't be called from IRQ context,
@@ -416,7 +493,8 @@ static void imxfb_setup_gpio(struct imxfb_info *fbi)
 static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
 {
         struct imxfb_info *fbi = platform_get_drvdata(dev);
-        pr_debug("%s\n",__func__);
+
+        pr_debug("%s\n", __func__);
 
         imxfb_disable_controller(fbi);
         return 0;
@@ -425,7 +503,8 @@ static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
 static int imxfb_resume(struct platform_device *dev)
 {
         struct imxfb_info *fbi = platform_get_drvdata(dev);
-        pr_debug("%s\n",__func__);
+
+        pr_debug("%s\n", __func__);
 
         imxfb_enable_controller(fbi);
         return 0;
@@ -435,149 +514,136 @@ static int imxfb_resume(struct platform_device *dev)
 #define imxfb_resume    NULL
 #endif
 
-static int __init imxfb_init_fbinfo(struct device *dev)
+static int __init imxfb_init_fbinfo(struct platform_device *pdev)
 {
-        struct imxfb_mach_info *inf = dev->platform_data;
-        struct fb_info *info = dev_get_drvdata(dev);
+        struct imx_fb_platform_data *pdata = pdev->dev.platform_data;
+        struct fb_info *info = dev_get_drvdata(&pdev->dev);
         struct imxfb_info *fbi = info->par;
 
         pr_debug("%s\n",__func__);
 
-        info->pseudo_palette = kmalloc( sizeof(u32) * 16, GFP_KERNEL);
+        info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
         if (!info->pseudo_palette)
                 return -ENOMEM;
 
         memset(fbi, 0, sizeof(struct imxfb_info));
-        fbi->dev = dev;
 
         strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id));
 
-        info->fix.type  = FB_TYPE_PACKED_PIXELS;
+        info->fix.type                  = FB_TYPE_PACKED_PIXELS;
         info->fix.type_aux              = 0;
         info->fix.xpanstep              = 0;
         info->fix.ypanstep              = 0;
         info->fix.ywrapstep             = 0;
-        info->fix.accel = FB_ACCEL_NONE;
+        info->fix.accel                 = FB_ACCEL_NONE;
 
         info->var.nonstd                = 0;
         info->var.activate              = FB_ACTIVATE_NOW;
         info->var.height                = -1;
         info->var.width = -1;
         info->var.accel_flags           = 0;
-        info->var.vmode = FB_VMODE_NONINTERLACED;
+        info->var.vmode                 = FB_VMODE_NONINTERLACED;
 
         info->fbops                     = &imxfb_ops;
-        info->flags                     = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
-
-        fbi->rgb[RGB_16]                = &def_rgb_16;
-        fbi->rgb[RGB_8]                 = &def_rgb_8;
-
-        fbi->max_xres                   = inf->xres;
-        info->var.xres                  = inf->xres;
-        info->var.xres_virtual          = inf->xres;
-        fbi->max_yres                   = inf->yres;
-        info->var.yres                  = inf->yres;
-        info->var.yres_virtual          = inf->yres;
-        fbi->max_bpp                    = inf->bpp;
-        info->var.bits_per_pixel        = inf->bpp;
-        info->var.nonstd                = inf->nonstd;
-        info->var.pixclock              = inf->pixclock;
-        info->var.hsync_len             = inf->hsync_len;
-        info->var.left_margin           = inf->left_margin;
-        info->var.right_margin          = inf->right_margin;
-        info->var.vsync_len             = inf->vsync_len;
-        info->var.upper_margin          = inf->upper_margin;
-        info->var.lower_margin          = inf->lower_margin;
-        info->var.sync                  = inf->sync;
-        info->var.grayscale             = inf->cmap_greyscale;
-        fbi->cmap_inverse               = inf->cmap_inverse;
-        fbi->cmap_static                = inf->cmap_static;
-        fbi->pcr                        = inf->pcr;
-        fbi->lscr1                      = inf->lscr1;
-        fbi->dmacr                      = inf->dmacr;
-        fbi->pwmr                       = inf->pwmr;
-        fbi->lcd_power                  = inf->lcd_power;
-        fbi->backlight_power            = inf->backlight_power;
+        info->flags                     = FBINFO_FLAG_DEFAULT |
+                                          FBINFO_READS_FAST;
+
+        fbi->max_xres                   = pdata->xres;
+        info->var.xres                  = pdata->xres;
+        info->var.xres_virtual          = pdata->xres;
+        fbi->max_yres                   = pdata->yres;
+        info->var.yres                  = pdata->yres;
+        info->var.yres_virtual          = pdata->yres;
+        fbi->max_bpp                    = pdata->bpp;
+        info->var.bits_per_pixel        = pdata->bpp;
+        info->var.nonstd                = pdata->nonstd;
+        info->var.pixclock              = pdata->pixclock;
+        info->var.hsync_len             = pdata->hsync_len;
+        info->var.left_margin           = pdata->left_margin;
+        info->var.right_margin          = pdata->right_margin;
+        info->var.vsync_len             = pdata->vsync_len;
+        info->var.upper_margin          = pdata->upper_margin;
+        info->var.lower_margin          = pdata->lower_margin;
+        info->var.sync                  = pdata->sync;
+        info->var.grayscale             = pdata->cmap_greyscale;
+        fbi->cmap_inverse               = pdata->cmap_inverse;
+        fbi->cmap_static                = pdata->cmap_static;
+        fbi->pcr                        = pdata->pcr;
+        fbi->lscr1                      = pdata->lscr1;
+        fbi->dmacr                      = pdata->dmacr;
+        fbi->pwmr                       = pdata->pwmr;
+        fbi->lcd_power                  = pdata->lcd_power;
+        fbi->backlight_power            = pdata->backlight_power;
         info->fix.smem_len              = fbi->max_xres * fbi->max_yres *
                                           fbi->max_bpp / 8;
 
         return 0;
 }
 
-/*
- *      Allocates the DRAM memory for the frame buffer.  This buffer is
- *      remapped into a non-cached, non-buffered, memory region to
- *      allow pixel writes to occur without flushing the cache.
- *      Once this area is remapped, all virtual memory access to the
- *      video memory should occur at the new region.
- */
-static int __init imxfb_map_video_memory(struct fb_info *info)
-{
-        struct imxfb_info *fbi = info->par;
-
-        fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
-        fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
-                                        &fbi->map_dma,GFP_KERNEL);
-
-        if (fbi->map_cpu) {
-                info->screen_base = fbi->map_cpu;
-                fbi->screen_cpu = fbi->map_cpu;
-                fbi->screen_dma = fbi->map_dma;
-                info->fix.smem_start = fbi->screen_dma;
-        }
-
-        return fbi->map_cpu ? 0 : -ENOMEM;
-}
-
 static int __init imxfb_probe(struct platform_device *pdev)
 {
         struct imxfb_info *fbi;
         struct fb_info *info;
-        struct imxfb_mach_info *inf;
+        struct imx_fb_platform_data *pdata;
         struct resource *res;
         int ret;
 
         printk("i.MX Framebuffer driver\n");
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if(!res)
+        if (!res)
                 return -ENODEV;
 
-        inf = pdev->dev.platform_data;
-        if(!inf) {
+        pdata = pdev->dev.platform_data;
+        if (!pdata) {
                 dev_err(&pdev->dev,"No platform_data available\n");
                 return -ENOMEM;
         }
 
         info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev);
-        if(!info)
+        if (!info)
                 return -ENOMEM;
 
         fbi = info->par;
 
         platform_set_drvdata(pdev, info);
 
-        ret = imxfb_init_fbinfo(&pdev->dev);
-        if( ret < 0 )
+        ret = imxfb_init_fbinfo(pdev);
+        if (ret < 0)
                 goto failed_init;
 
-        res = request_mem_region(res->start, res->end - res->start + 1, "IMXFB");
+        res = request_mem_region(res->start, resource_size(res),
+                                DRIVER_NAME);
         if (!res) {
                 ret = -EBUSY;
-                goto failed_regs;
+                goto failed_req;
+        }
+
+        fbi->regs = ioremap(res->start, resource_size(res));
+        if (fbi->regs == NULL) {
+                printk(KERN_ERR"Cannot map frame buffer registers\n");
+                goto failed_ioremap;
         }
 
-        if (!inf->fixed_screen_cpu) {
-                ret = imxfb_map_video_memory(info);
-                if (ret) {
+        if (!pdata->fixed_screen_cpu) {
+                fbi->map_size = PAGE_ALIGN(info->fix.smem_len);
+                fbi->map_cpu = dma_alloc_writecombine(&pdev->dev,
+                                fbi->map_size, &fbi->map_dma, GFP_KERNEL);
+
+                if (!fbi->map_cpu) {
                         dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret);
                         ret = -ENOMEM;
                         goto failed_map;
                 }
+
+                info->screen_base = fbi->map_cpu;
+                fbi->screen_cpu = fbi->map_cpu;
+                fbi->screen_dma = fbi->map_dma;
+                info->fix.smem_start = fbi->screen_dma;
         } else {
                 /* Fixed framebuffer mapping enables location of the screen in eSRAM */
-                fbi->map_cpu = inf->fixed_screen_cpu;
-                fbi->map_dma = inf->fixed_screen_dma;
+                fbi->map_cpu = pdata->fixed_screen_cpu;
+                fbi->map_dma = pdata->fixed_screen_dma;
                 info->screen_base = fbi->map_cpu;
                 fbi->screen_cpu = fbi->map_cpu;
                 fbi->screen_dma = fbi->map_dma;
@@ -590,12 +656,10 @@ static int __init imxfb_probe(struct platform_device *pdev)
          */
         imxfb_check_var(&info->var, info);
 
-        ret = fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
+        ret = fb_alloc_cmap(&info->cmap, 1 << info->var.bits_per_pixel, 0);
         if (ret < 0)
                 goto failed_cmap;
 
-        imxfb_setup_gpio(fbi);
-
         imxfb_set_par(info);
         ret = register_framebuffer(info);
         if (ret < 0) {
@@ -610,20 +674,22 @@ static int __init imxfb_probe(struct platform_device *pdev)
 failed_register:
         fb_dealloc_cmap(&info->cmap);
 failed_cmap:
-        if (!inf->fixed_screen_cpu)
+        if (!pdata->fixed_screen_cpu)
                 dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu,
-                           fbi->map_dma);
+                        fbi->map_dma);
 failed_map:
-        kfree(info->pseudo_palette);
-failed_regs:
+        iounmap(fbi->regs);
+failed_ioremap:
         release_mem_region(res->start, res->end - res->start);
+failed_req:
+        kfree(info->pseudo_palette);
 failed_init:
         platform_set_drvdata(pdev, NULL);
         framebuffer_release(info);
         return ret;
 }
 
-static int imxfb_remove(struct platform_device *pdev)
+static int __devexit imxfb_remove(struct platform_device *pdev)
 {
         struct fb_info *info = platform_get_drvdata(pdev);
         struct imxfb_info *fbi = info->par;
@@ -639,6 +705,7 @@ static int imxfb_remove(struct platform_device *pdev)
         kfree(info->pseudo_palette);
         framebuffer_release(info);
 
+        iounmap(fbi->regs);
         release_mem_region(res->start, res->end - res->start + 1);
         platform_set_drvdata(pdev, NULL);
 
@@ -653,19 +720,18 @@ void  imxfb_shutdown(struct platform_device * dev)
 }
 
 static struct platform_driver imxfb_driver = {
-        .probe          = imxfb_probe,
         .suspend        = imxfb_suspend,
         .resume         = imxfb_resume,
-        .remove         = imxfb_remove,
+        .remove         = __devexit_p(imxfb_remove),
         .shutdown       = imxfb_shutdown,
         .driver         = {
-                .name   = "imx-fb",
+                .name   = DRIVER_NAME,
         },
 };
 
 int __init imxfb_init(void)
 {
-        return platform_driver_register(&imxfb_driver);
+        return platform_driver_probe(&imxfb_driver, imxfb_probe);
 }
 
 static void __exit imxfb_cleanup(void)
diff --git a/drivers/video/imxfb.h b/drivers/video/imxfb.h
deleted file mode 100644
index e837a8b48eb8..000000000000
--- a/drivers/video/imxfb.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * linux/drivers/video/imxfb.h
- *
- *  Freescale i.MX Frame Buffer device driver
- *
- *  Copyright (C) 2004 S.Hauer, Pengutronix
- *
- *  Copyright (C) 1999 Eric A. Thomas
- *   Based on acornfb.c Copyright (C) Russell King.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-/*
- * These are the bitfields for each
- * display depth that we support.
- */
-struct imxfb_rgb {
-        struct fb_bitfield      red;
-        struct fb_bitfield      green;
-        struct fb_bitfield      blue;
-        struct fb_bitfield      transp;
-};
-
-#define RGB_16  (0)
-#define RGB_8   (1)
-#define NR_RGB  2
-
-struct imxfb_info {
-        struct device           *dev;
-        struct imxfb_rgb        *rgb[NR_RGB];
-
-        u_int                   max_bpp;
-        u_int                   max_xres;
-        u_int                   max_yres;
-
-        /*
-         * These are the addresses we mapped
-         * the framebuffer memory region to.
-         */
-        dma_addr_t              map_dma;
-        u_char *                map_cpu;
-        u_int                   map_size;
-
-        u_char *                screen_cpu;
-        dma_addr_t              screen_dma;
-        u_int                   palette_size;
-
-        dma_addr_t              dbar1;
-        dma_addr_t              dbar2;
-
-        u_int                   pcr;
-        u_int                   pwmr;
-        u_int                   lscr1;
-        u_int                   dmacr;
-        u_int                   cmap_inverse:1,
-                                cmap_static:1,
-                                unused:30;
-
-        void (*lcd_power)(int);
-        void (*backlight_power)(int);
-};
-
-#define IMX_NAME        "IMX"
-
-/*
- * Minimum X and Y resolutions
- */
-#define MIN_XRES        64
-#define MIN_YRES        64
-
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index cc59c52e1103..48ff701d3a72 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -20,6 +20,16 @@
  *
  *      linux-arm-kernel@lists.arm.linux.org.uk
  *
+ * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
+ *
+ *   Copyright (C) 2004, Intel Corporation
+ *
+ *     2003/08/27: <yu.tang@intel.com>
+ *     2004/03/10: <stanley.cai@intel.com>
+ *     2004/10/28: <yan.yin@intel.com>
+ *
+ *   Copyright (C) 2006-2008 Marvell International Ltd.
+ *   All Rights Reserved
  */
 
 #include <linux/module.h>
@@ -50,7 +60,6 @@
 #include <asm/irq.h>
 #include <asm/div64.h>
 #include <mach/pxa-regs.h>
-#include <mach/pxa2xx-gpio.h>
 #include <mach/bitfield.h>
 #include <mach/pxafb.h>
 
@@ -67,14 +76,16 @@
                                          LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
 
 #define LCCR3_INVALID_CONFIG_MASK       (LCCR3_HSP | LCCR3_VSP |\
-                                         LCCR3_PCD | LCCR3_BPP)
-
-static void (*pxafb_backlight_power)(int);
-static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
+                                         LCCR3_PCD | LCCR3_BPP(0xf))
 
 static int pxafb_activate_var(struct fb_var_screeninfo *var,
                                 struct pxafb_info *);
 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
+static void setup_base_frame(struct pxafb_info *fbi, int branch);
+static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
+                           unsigned long offset, size_t size);
+
+static unsigned long video_mem_size = 0;
 
 static inline unsigned long
 lcd_readl(struct pxafb_info *fbi, unsigned int off)
@@ -156,6 +167,12 @@ pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
                 val |= ((blue  >> 8) & 0x000000fc);
                 ((u32 *)(fbi->palette_cpu))[regno] = val;
                 break;
+        case LCCR4_PAL_FOR_3:
+                val  = ((red   << 8) & 0x00ff0000);
+                val |= ((green >> 0) & 0x0000ff00);
+                val |= ((blue  >> 8) & 0x000000ff);
+                ((u32 *)(fbi->palette_cpu))[regno] = val;
+                break;
         }
 
         return 0;
@@ -216,37 +233,110 @@ pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
         return ret;
 }
 
-/*
- *  pxafb_bpp_to_lccr3():
- *    Convert a bits per pixel value to the correct bit pattern for LCCR3
- */
-static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
+/* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
+static inline int var_to_depth(struct fb_var_screeninfo *var)
 {
-        int ret = 0;
+        return var->red.length + var->green.length +
+                var->blue.length + var->transp.length;
+}
+
+/* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
+static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
+{
+        int bpp = -EINVAL;
+
         switch (var->bits_per_pixel) {
-        case 1:  ret = LCCR3_1BPP; break;
-        case 2:  ret = LCCR3_2BPP; break;
-        case 4:  ret = LCCR3_4BPP; break;
-        case 8:  ret = LCCR3_8BPP; break;
-        case 16: ret = LCCR3_16BPP; break;
+        case 1:  bpp = 0; break;
+        case 2:  bpp = 1; break;
+        case 4:  bpp = 2; break;
+        case 8:  bpp = 3; break;
+        case 16: bpp = 4; break;
         case 24:
-                switch (var->red.length + var->green.length +
-                                var->blue.length + var->transp.length) {
-                case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
-                case 19: ret = LCCR3_19BPP_P; break;
+                switch (var_to_depth(var)) {
+                case 18: bpp = 6; break; /* 18-bits/pixel packed */
+                case 19: bpp = 8; break; /* 19-bits/pixel packed */
+                case 24: bpp = 9; break;
                 }
                 break;
         case 32:
-                switch (var->red.length + var->green.length +
-                                var->blue.length + var->transp.length) {
-                case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
-                case 19: ret = LCCR3_19BPP; break;
-                case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
-                case 25: ret = LCCR3_25BPP; break;
+                switch (var_to_depth(var)) {
+                case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
+                case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
+                case 25: bpp = 10; break;
                 }
                 break;
         }
-        return ret;
+        return bpp;
+}
+
+/*
+ *  pxafb_var_to_lccr3():
+ *    Convert a bits per pixel value to the correct bit pattern for LCCR3
+ *
+ *  NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
+ *  implication of the acutal use of transparency bit,  which we handle it
+ *  here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
+ *  Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
+ *
+ *  Transparency for palette pixel formats is not supported at the moment.
+ */
+static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
+{
+        int bpp = pxafb_var_to_bpp(var);
+        uint32_t lccr3;
+
+        if (bpp < 0)
+                return 0;
+
+        lccr3 = LCCR3_BPP(bpp);
+
+        switch (var_to_depth(var)) {
+        case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
+        case 18: lccr3 |= LCCR3_PDFOR_3; break;
+        case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
+                 break;
+        case 19:
+        case 25: lccr3 |= LCCR3_PDFOR_0; break;
+        }
+        return lccr3;
+}
+
+#define SET_PIXFMT(v, r, g, b, t)                               \
+({                                                              \
+        (v)->transp.offset = (t) ? (r) + (g) + (b) : 0;         \
+        (v)->transp.length = (t) ? (t) : 0;                     \
+        (v)->blue.length   = (b); (v)->blue.offset = 0;         \
+        (v)->green.length  = (g); (v)->green.offset = (b);      \
+        (v)->red.length    = (r); (v)->red.offset = (b) + (g);  \
+})
+
+/* set the RGBT bitfields of fb_var_screeninf according to
+ * var->bits_per_pixel and given depth
+ */
+static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
+{
+        if (depth == 0)
+                depth = var->bits_per_pixel;
+
+        if (var->bits_per_pixel < 16) {
+                /* indexed pixel formats */
+                var->red.offset    = 0; var->red.length    = 8;
+                var->green.offset  = 0; var->green.length  = 8;
+                var->blue.offset   = 0; var->blue.length   = 8;
+                var->transp.offset = 0; var->transp.length = 8;
+        }
+
+        switch (depth) {
+        case 16: var->transp.length ?
+                 SET_PIXFMT(var, 5, 5, 5, 1) :          /* RGBT555 */
+                 SET_PIXFMT(var, 5, 6, 5, 0); break;    /* RGB565 */
+        case 18: SET_PIXFMT(var, 6, 6, 6, 0); break;    /* RGB666 */
+        case 19: SET_PIXFMT(var, 6, 6, 6, 1); break;    /* RGBT666 */
+        case 24: var->transp.length ?
+                 SET_PIXFMT(var, 8, 8, 7, 1) :          /* RGBT887 */
+                 SET_PIXFMT(var, 8, 8, 8, 0); break;    /* RGB888 */
+        case 25: SET_PIXFMT(var, 8, 8, 8, 1); break;    /* RGBT888 */
+        }
 }
 
 #ifdef CONFIG_CPU_FREQ
@@ -308,8 +398,49 @@ static void pxafb_setmode(struct fb_var_screeninfo *var,
         var->lower_margin       = mode->lower_margin;
         var->sync               = mode->sync;
         var->grayscale          = mode->cmap_greyscale;
-        var->xres_virtual       = var->xres;
-        var->yres_virtual       = var->yres;
+
+        /* set the initial RGBA bitfields */
+        pxafb_set_pixfmt(var, mode->depth);
+}
+
+static int pxafb_adjust_timing(struct pxafb_info *fbi,
+                               struct fb_var_screeninfo *var)
+{
+        int line_length;
+
+        var->xres = max_t(int, var->xres, MIN_XRES);
+        var->yres = max_t(int, var->yres, MIN_YRES);
+
+        if (!(fbi->lccr0 & LCCR0_LCDT)) {
+                clamp_val(var->hsync_len, 1, 64);
+                clamp_val(var->vsync_len, 1, 64);
+                clamp_val(var->left_margin,  1, 255);
+                clamp_val(var->right_margin, 1, 255);
+                clamp_val(var->upper_margin, 1, 255);
+                clamp_val(var->lower_margin, 1, 255);
+        }
+
+        /* make sure each line is aligned on word boundary */
+        line_length = var->xres * var->bits_per_pixel / 8;
+        line_length = ALIGN(line_length, 4);
+        var->xres = line_length * 8 / var->bits_per_pixel;
+
+        /* we don't support xpan, force xres_virtual to be equal to xres */
+        var->xres_virtual = var->xres;
+
+        if (var->accel_flags & FB_ACCELF_TEXT)
+                var->yres_virtual = fbi->fb.fix.smem_len / line_length;
+        else
+                var->yres_virtual = max(var->yres_virtual, var->yres);
+
+        /* check for limits */
+        if (var->xres > MAX_XRES || var->yres > MAX_YRES)
+                return -EINVAL;
+
+        if (var->yres > var->yres_virtual)
+                return -EINVAL;
+
+        return 0;
 }
 
 /*
@@ -325,11 +456,7 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 {
         struct pxafb_info *fbi = (struct pxafb_info *)info;
         struct pxafb_mach_info *inf = fbi->dev->platform_data;
-
-        if (var->xres < MIN_XRES)
-                var->xres = MIN_XRES;
-        if (var->yres < MIN_YRES)
-                var->yres = MIN_YRES;
+        int err;
 
         if (inf->fixed_modes) {
                 struct pxafb_mode_info *mode;
@@ -338,74 +465,18 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
                 if (!mode)
                         return -EINVAL;
                 pxafb_setmode(var, mode);
-        } else {
-                if (var->xres > inf->modes->xres)
-                        return -EINVAL;
-                if (var->yres > inf->modes->yres)
-                        return -EINVAL;
-                if (var->bits_per_pixel > inf->modes->bpp)
-                        return -EINVAL;
         }
 
-        var->xres_virtual =
-                max(var->xres_virtual, var->xres);
-        var->yres_virtual =
-                max(var->yres_virtual, var->yres);
+        /* do a test conversion to BPP fields to check the color formats */
+        err = pxafb_var_to_bpp(var);
+        if (err < 0)
+                return err;
 
-        /*
-         * Setup the RGB parameters for this display.
-         *
-         * The pixel packing format is described on page 7-11 of the
-         * PXA2XX Developer's Manual.
-         */
-        if (var->bits_per_pixel == 16) {
-                var->red.offset   = 11; var->red.length   = 5;
-                var->green.offset = 5;  var->green.length = 6;
-                var->blue.offset  = 0;  var->blue.length  = 5;
-                var->transp.offset = var->transp.length = 0;
-        } else if (var->bits_per_pixel > 16) {
-                struct pxafb_mode_info *mode;
+        pxafb_set_pixfmt(var, var_to_depth(var));
 
-                mode = pxafb_getmode(inf, var);
-                if (!mode)
-                        return -EINVAL;
-
-                switch (mode->depth) {
-                case 18: /* RGB666 */
-                        var->transp.offset = var->transp.length     = 0;
-                        var->red.offset    = 12; var->red.length    = 6;
-                        var->green.offset  = 6;  var->green.length  = 6;
-                        var->blue.offset   = 0;  var->blue.length   = 6;
-                        break;
-                case 19: /* RGBT666 */
-                        var->transp.offset = 18; var->transp.length = 1;
-                        var->red.offset    = 12; var->red.length    = 6;
-                        var->green.offset  = 6;  var->green.length  = 6;
-                        var->blue.offset   = 0;  var->blue.length   = 6;
-                        break;
-                case 24: /* RGB888 */
-                        var->transp.offset = var->transp.length     = 0;
-                        var->red.offset    = 16; var->red.length    = 8;
-                        var->green.offset  = 8;  var->green.length  = 8;
-                        var->blue.offset   = 0;  var->blue.length   = 8;
-                        break;
-                case 25: /* RGBT888 */
-                        var->transp.offset = 24; var->transp.length = 1;
-                        var->red.offset    = 16; var->red.length    = 8;
-                        var->green.offset  = 8;  var->green.length  = 8;
-                        var->blue.offset   = 0;  var->blue.length   = 8;
-                        break;
-                default:
-                        return -EINVAL;
-                }
-        } else {
-                var->red.offset = var->green.offset = 0;
-                var->blue.offset = var->transp.offset = 0;
-                var->red.length   = 8;
-                var->green.length = 8;
-                var->blue.length  = 8;
-                var->transp.length = 0;
-        }
+        err = pxafb_adjust_timing(fbi, var);
+        if (err)
+                return err;
 
 #ifdef CONFIG_CPU_FREQ
         pr_debug("pxafb: dma period = %d ps\n",
@@ -415,11 +486,6 @@ static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
         return 0;
 }
 
-static inline void pxafb_set_truecolor(u_int is_true_color)
-{
-        /* do your machine-specific setup if needed */
-}
-
 /*
  * pxafb_set_par():
  *      Set the user defined part of the display for the specified console
@@ -452,11 +518,6 @@ static int pxafb_set_par(struct fb_info *info)
 
         fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
 
-        /*
-         * Set (any) board control register to handle new color depth
-         */
-        pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
-
         if (fbi->fb.var.bits_per_pixel >= 16)
                 fb_dealloc_cmap(&fbi->fb.cmap);
         else
@@ -467,6 +528,24 @@ static int pxafb_set_par(struct fb_info *info)
         return 0;
 }
 
+static int pxafb_pan_display(struct fb_var_screeninfo *var,
+                             struct fb_info *info)
+{
+        struct pxafb_info *fbi = (struct pxafb_info *)info;
+        int dma = DMA_MAX + DMA_BASE;
+
+        if (fbi->state != C_ENABLE)
+                return 0;
+
+        setup_base_frame(fbi, 1);
+
+        if (fbi->lccr0 & LCCR0_SDS)
+                lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
+
+        lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
+        return 0;
+}
+
 /*
  * pxafb_blank():
  *      Blank the display by setting all palette values to zero.  Note, the
@@ -502,32 +581,342 @@ static int pxafb_blank(int blank, struct fb_info *info)
         return 0;
 }
 
-static int pxafb_mmap(struct fb_info *info,
-                      struct vm_area_struct *vma)
-{
-        struct pxafb_info *fbi = (struct pxafb_info *)info;
-        unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
-
-        if (off < info->fix.smem_len) {
-                vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
-                return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
-                                             fbi->map_dma, fbi->map_size);
-        }
-        return -EINVAL;
-}
-
 static struct fb_ops pxafb_ops = {
         .owner          = THIS_MODULE,
         .fb_check_var   = pxafb_check_var,
         .fb_set_par     = pxafb_set_par,
+        .fb_pan_display = pxafb_pan_display,
         .fb_setcolreg   = pxafb_setcolreg,
         .fb_fillrect    = cfb_fillrect,
         .fb_copyarea    = cfb_copyarea,
         .fb_imageblit   = cfb_imageblit,
         .fb_blank       = pxafb_blank,
-        .fb_mmap        = pxafb_mmap,
 };
 
+#ifdef CONFIG_FB_PXA_OVERLAY
+static void overlay1fb_setup(struct pxafb_layer *ofb)
+{
+        int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
+        unsigned long start = ofb->video_mem_phys;
+        setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
+}
+
+/* Depending on the enable status of overlay1/2, the DMA should be
+ * updated from FDADRx (when disabled) or FBRx (when enabled).
+ */
+static void overlay1fb_enable(struct pxafb_layer *ofb)
+{
+        int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
+        uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
+
+        lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
+        lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
+        lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
+}
+
+static void overlay1fb_disable(struct pxafb_layer *ofb)
+{
+        uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
+
+        lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
+
+        lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
+        lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
+        lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
+
+        if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
+                pr_warning("%s: timeout disabling overlay1\n", __func__);
+
+        lcd_writel(ofb->fbi, LCCR5, lccr5);
+}
+
+static void overlay2fb_setup(struct pxafb_layer *ofb)
+{
+        int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
+        unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
+
+        if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
+                size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
+                setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
+        } else {
+                size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
+                switch (pfor) {
+                case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
+                case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
+                case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
+                }
+                start[1] = start[0] + size;
+                start[2] = start[1] + size / div;
+                setup_frame_dma(ofb->fbi, DMA_OV2_Y,  -1, start[0], size);
+                setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
+                setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
+        }
+}
+
+static void overlay2fb_enable(struct pxafb_layer *ofb)
+{
+        int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
+        int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
+        uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y]  | (enabled ? 0x1 : 0);
+        uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
+        uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
+
+        if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
+                lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
+        else {
+                lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
+                lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
+                lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
+        }
+        lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
+        lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
+}
+
+static void overlay2fb_disable(struct pxafb_layer *ofb)
+{
+        uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
+
+        lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
+
+        lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
+        lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
+        lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y]  | 0x3);
+        lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
+        lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
+
+        if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
+                pr_warning("%s: timeout disabling overlay2\n", __func__);
+}
+
+static struct pxafb_layer_ops ofb_ops[] = {
+        [0] = {
+                .enable         = overlay1fb_enable,
+                .disable        = overlay1fb_disable,
+                .setup          = overlay1fb_setup,
+        },
+        [1] = {
+                .enable         = overlay2fb_enable,
+                .disable        = overlay2fb_disable,
+                .setup          = overlay2fb_setup,
+        },
+};
+
+static int overlayfb_open(struct fb_info *info, int user)
+{
+        struct pxafb_layer *ofb = (struct pxafb_layer *)info;
+
+        /* no support for framebuffer console on overlay */
+        if (user == 0)
+                return -ENODEV;
+
+        /* allow only one user at a time */
+        if (atomic_inc_and_test(&ofb->usage))
+                return -EBUSY;
+
+        /* unblank the base framebuffer */
+        fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
+        return 0;
+}
+
+static int overlayfb_release(struct fb_info *info, int user)
+{
+        struct pxafb_layer *ofb = (struct pxafb_layer*) info;
+
+        atomic_dec(&ofb->usage);
+        ofb->ops->disable(ofb);
+
+        free_pages_exact(ofb->video_mem, ofb->video_mem_size);
+        ofb->video_mem = NULL;
+        ofb->video_mem_size = 0;
+        return 0;
+}
+
+static int overlayfb_check_var(struct fb_var_screeninfo *var,
+                               struct fb_info *info)
+{
+        struct pxafb_layer *ofb = (struct pxafb_layer *)info;
+        struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
+        int xpos, ypos, pfor, bpp;
+
+        xpos = NONSTD_TO_XPOS(var->nonstd);
+        ypos = NONSTD_TO_XPOS(var->nonstd);
+        pfor = NONSTD_TO_PFOR(var->nonstd);
+
+        bpp = pxafb_var_to_bpp(var);
+        if (bpp < 0)
+                return -EINVAL;
+
+        /* no support for YUV format on overlay1 */
+        if (ofb->id == OVERLAY1 && pfor != 0)
+                return -EINVAL;
+
+        /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
+        switch (pfor) {
+        case OVERLAY_FORMAT_RGB:
+                bpp = pxafb_var_to_bpp(var);
+                if (bpp < 0)
+                        return -EINVAL;
+
+                pxafb_set_pixfmt(var, var_to_depth(var));
+                break;
+        case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
+        case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
+        case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
+        case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
+        default:
+                return -EINVAL;
+        }
+
+        /* each line must start at a 32-bit word boundary */
+        if ((xpos * bpp) % 32)
+                return -EINVAL;
+
+        /* xres must align on 32-bit word boundary */
+        var->xres = roundup(var->xres * bpp, 32) / bpp;
+
+        if ((xpos + var->xres > base_var->xres) ||
+            (ypos + var->yres > base_var->yres))
+                return -EINVAL;
+
+        var->xres_virtual = var->xres;
+        var->yres_virtual = max(var->yres, var->yres_virtual);
+        return 0;
+}
+
+static int overlayfb_map_video_memory(struct pxafb_layer *ofb)
+{
+        struct fb_var_screeninfo *var = &ofb->fb.var;
+        int pfor = NONSTD_TO_PFOR(var->nonstd);
+        int size, bpp = 0;
+
+        switch (pfor) {
+        case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
+        case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
+        case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
+        case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
+        case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
+        }
+
+        ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
+
+        size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
+
+        /* don't re-allocate if the original video memory is enough */
+        if (ofb->video_mem) {
+                if (ofb->video_mem_size >= size)
+                        return 0;
+
+                free_pages_exact(ofb->video_mem, ofb->video_mem_size);
+        }
+
+        ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
+        if (ofb->video_mem == NULL)
+                return -ENOMEM;
+
+        ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
+        ofb->video_mem_size = size;
+
+        ofb->fb.fix.smem_start  = ofb->video_mem_phys;
+        ofb->fb.fix.smem_len    = ofb->fb.fix.line_length * var->yres_virtual;
+        ofb->fb.screen_base     = ofb->video_mem;
+        return 0;
+}
+
+static int overlayfb_set_par(struct fb_info *info)
+{
+        struct pxafb_layer *ofb = (struct pxafb_layer *)info;
+        struct fb_var_screeninfo *var = &info->var;
+        int xpos, ypos, pfor, bpp, ret;
+
+        ret = overlayfb_map_video_memory(ofb);
+        if (ret)
+                return ret;
+
+        bpp  = pxafb_var_to_bpp(var);
+        xpos = NONSTD_TO_XPOS(var->nonstd);
+        ypos = NONSTD_TO_XPOS(var->nonstd);
+        pfor = NONSTD_TO_PFOR(var->nonstd);
+
+        ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
+                          OVLxC1_BPP(bpp);
+        ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
+
+        if (ofb->id == OVERLAY2)
+                ofb->control[1] |= OVL2C2_PFOR(pfor);
+
+        ofb->ops->setup(ofb);
+        ofb->ops->enable(ofb);
+        return 0;
+}
+
+static struct fb_ops overlay_fb_ops = {
+        .owner                  = THIS_MODULE,
+        .fb_open                = overlayfb_open,
+        .fb_release             = overlayfb_release,
+        .fb_check_var           = overlayfb_check_var,
+        .fb_set_par             = overlayfb_set_par,
+};
+
+static void __devinit init_pxafb_overlay(struct pxafb_info *fbi,
+                                         struct pxafb_layer *ofb, int id)
+{
+        sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
+
+        ofb->fb.fix.type                = FB_TYPE_PACKED_PIXELS;
+        ofb->fb.fix.xpanstep            = 0;
+        ofb->fb.fix.ypanstep            = 1;
+
+        ofb->fb.var.activate            = FB_ACTIVATE_NOW;
+        ofb->fb.var.height              = -1;
+        ofb->fb.var.width               = -1;
+        ofb->fb.var.vmode               = FB_VMODE_NONINTERLACED;
+
+        ofb->fb.fbops                   = &overlay_fb_ops;
+        ofb->fb.flags                   = FBINFO_FLAG_DEFAULT;
+        ofb->fb.node                    = -1;
+        ofb->fb.pseudo_palette          = NULL;
+
+        ofb->id = id;
+        ofb->ops = &ofb_ops[id];
+        atomic_set(&ofb->usage, 0);
+        ofb->fbi = fbi;
+        init_completion(&ofb->branch_done);
+}
+
+static int __devinit pxafb_overlay_init(struct pxafb_info *fbi)
+{
+        int i, ret;
+
+        for (i = 0; i < 2; i++) {
+                init_pxafb_overlay(fbi, &fbi->overlay[i], i);
+                ret = register_framebuffer(&fbi->overlay[i].fb);
+                if (ret) {
+                        dev_err(fbi->dev, "failed to register overlay %d\n", i);
+                        return ret;
+                }
+        }
+
+        /* mask all IU/BS/EOF/SOF interrupts */
+        lcd_writel(fbi, LCCR5, ~0);
+
+        /* place overlay(s) on top of base */
+        fbi->lccr0 |= LCCR0_OUC;
+        pr_info("PXA Overlay driver loaded successfully!\n");
+        return 0;
+}
+
+static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi)
+{
+        int i;
+
+        for (i = 0; i < 2; i++)
+                unregister_framebuffer(&fbi->overlay[i].fb);
+}
+#else
+static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
+static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
+#endif /* CONFIG_FB_PXA_OVERLAY */
+
 /*
  * Calculate the PCD value from the clock rate (in picoseconds).
  * We take account of the PPCR clock setting.
@@ -607,22 +996,22 @@ unsigned long pxafb_get_hsync_time(struct device *dev)
 EXPORT_SYMBOL(pxafb_get_hsync_time);
 
 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
-                unsigned int offset, size_t size)
+                           unsigned long start, size_t size)
 {
         struct pxafb_dma_descriptor *dma_desc, *pal_desc;
         unsigned int dma_desc_off, pal_desc_off;
 
-        if (dma < 0 || dma >= DMA_MAX)
+        if (dma < 0 || dma >= DMA_MAX * 2)
                 return -EINVAL;
 
         dma_desc = &fbi->dma_buff->dma_desc[dma];
         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
 
-        dma_desc->fsadr = fbi->screen_dma + offset;
+        dma_desc->fsadr = start;
         dma_desc->fidr  = 0;
         dma_desc->ldcmd = size;
 
-        if (pal < 0 || pal >= PAL_MAX) {
+        if (pal < 0 || pal >= PAL_MAX * 2) {
                 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
         } else {
@@ -648,6 +1037,27 @@ static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
         return 0;
 }
 
+static void setup_base_frame(struct pxafb_info *fbi, int branch)
+{
+        struct fb_var_screeninfo *var = &fbi->fb.var;
+        struct fb_fix_screeninfo *fix = &fbi->fb.fix;
+        int nbytes, dma, pal, bpp = var->bits_per_pixel;
+        unsigned long offset;
+
+        dma = DMA_BASE + (branch ? DMA_MAX : 0);
+        pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
+
+        nbytes = fix->line_length * var->yres;
+        offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
+
+        if (fbi->lccr0 & LCCR0_SDS) {
+                nbytes = nbytes / 2;
+                setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
+        }
+
+        setup_frame_dma(fbi, dma, pal, offset, nbytes);
+}
+
 #ifdef CONFIG_FB_PXA_SMARTPANEL
 static int setup_smart_dma(struct pxafb_info *fbi)
 {
@@ -701,6 +1111,7 @@ int pxafb_smart_flush(struct fb_info *info)
         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
+        lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
         lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
 
@@ -727,12 +1138,19 @@ int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
         int i;
         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 
-        /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
-        for (i = 0; i < n_cmds; i++) {
+        for (i = 0; i < n_cmds; i++, cmds++) {
+                /* if it is a software delay, flush and delay */
+                if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
+                        pxafb_smart_flush(info);
+                        mdelay(*cmds & 0xff);
+                        continue;
+                }
+
+                /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
                 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
                         pxafb_smart_flush(info);
 
-                fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++;
+                fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
         }
 
         return 0;
@@ -764,7 +1182,9 @@ static void setup_smart_timing(struct pxafb_info *fbi,
                 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
 
         fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
-        fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));
+        fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
+        fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
+        fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
 
         /* FIXME: make this configurable */
         fbi->reg_cmdcr = 1;
@@ -789,11 +1209,15 @@ static int pxafb_smart_thread(void *arg)
                 if (try_to_freeze())
                         continue;
 
+                mutex_lock(&fbi->ctrlr_lock);
+
                 if (fbi->state == C_ENABLE) {
                         inf->smart_update(&fbi->fb);
                         complete(&fbi->refresh_done);
                 }
 
+                mutex_unlock(&fbi->ctrlr_lock);
+
                 set_current_state(TASK_INTERRUPTIBLE);
                 schedule_timeout(30 * HZ / 1000);
         }
@@ -804,16 +1228,22 @@ static int pxafb_smart_thread(void *arg)
 
 static int pxafb_smart_init(struct pxafb_info *fbi)
 {
-        if (!(fbi->lccr0 | LCCR0_LCDT))
+        if (!(fbi->lccr0 & LCCR0_LCDT))
                 return 0;
 
+        fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
+        fbi->n_smart_cmds = 0;
+
+        init_completion(&fbi->command_done);
+        init_completion(&fbi->refresh_done);
+
         fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
                                         "lcd_refresh");
         if (IS_ERR(fbi->smart_thread)) {
-                printk(KERN_ERR "%s: unable to create kernel thread\n",
-                                __func__);
+                pr_err("%s: unable to create kernel thread\n", __func__);
                 return PTR_ERR(fbi->smart_thread);
         }
+
         return 0;
 }
 #else
@@ -826,7 +1256,9 @@ int pxafb_smart_flush(struct fb_info *info)
 {
         return 0;
 }
-#endif /* CONFIG_FB_SMART_PANEL */
+
+static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
+#endif /* CONFIG_FB_PXA_SMARTPANEL */
 
 static void setup_parallel_timing(struct pxafb_info *fbi,
                                   struct fb_var_screeninfo *var)
@@ -874,51 +1306,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
                               struct pxafb_info *fbi)
 {
         u_long flags;
-        size_t nbytes;
-
-#if DEBUG_VAR
-        if (!(fbi->lccr0 & LCCR0_LCDT)) {
-                if (var->xres < 16 || var->xres > 1024)
-                        printk(KERN_ERR "%s: invalid xres %d\n",
-                                fbi->fb.fix.id, var->xres);
-                switch (var->bits_per_pixel) {
-                case 1:
-                case 2:
-                case 4:
-                case 8:
-                case 16:
-                case 24:
-                case 32:
-                        break;
-                default:
-                        printk(KERN_ERR "%s: invalid bit depth %d\n",
-                               fbi->fb.fix.id, var->bits_per_pixel);
-                        break;
-                }
 
-                if (var->hsync_len < 1 || var->hsync_len > 64)
-                        printk(KERN_ERR "%s: invalid hsync_len %d\n",
-                                fbi->fb.fix.id, var->hsync_len);
-                if (var->left_margin < 1 || var->left_margin > 255)
-                        printk(KERN_ERR "%s: invalid left_margin %d\n",
-                                fbi->fb.fix.id, var->left_margin);
-                if (var->right_margin < 1 || var->right_margin > 255)
-                        printk(KERN_ERR "%s: invalid right_margin %d\n",
-                                fbi->fb.fix.id, var->right_margin);
-                if (var->yres < 1 || var->yres > 1024)
-                        printk(KERN_ERR "%s: invalid yres %d\n",
-                                fbi->fb.fix.id, var->yres);
-                if (var->vsync_len < 1 || var->vsync_len > 64)
-                        printk(KERN_ERR "%s: invalid vsync_len %d\n",
-                                fbi->fb.fix.id, var->vsync_len);
-                if (var->upper_margin < 0 || var->upper_margin > 255)
-                        printk(KERN_ERR "%s: invalid upper_margin %d\n",
-                                fbi->fb.fix.id, var->upper_margin);
-                if (var->lower_margin < 0 || var->lower_margin > 255)
-                        printk(KERN_ERR "%s: invalid lower_margin %d\n",
-                                fbi->fb.fix.id, var->lower_margin);
-        }
-#endif
         /* Update shadow copy atomically */
         local_irq_save(flags);
 
@@ -929,23 +1317,13 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
 #endif
                 setup_parallel_timing(fbi, var);
 
+        setup_base_frame(fbi, 0);
+
         fbi->reg_lccr0 = fbi->lccr0 |
                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
 
-        fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
-
-        nbytes = var->yres * fbi->fb.fix.line_length;
-
-        if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
-                nbytes = nbytes / 2;
-                setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
-        }
-
-        if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
-                setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
-        else
-                setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
+        fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
 
         fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
         fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
@@ -959,6 +1337,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var,
             (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
             (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
             (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
+            (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
             (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
             (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
                 pxafb_schedule_work(fbi, C_REENABLE);
@@ -976,67 +1355,16 @@ static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
 {
         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
 
-        if (pxafb_backlight_power)
-                pxafb_backlight_power(on);
+        if (fbi->backlight_power)
+                fbi->backlight_power(on);
 }
 
 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
 {
         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
 
-        if (pxafb_lcd_power)
-                pxafb_lcd_power(on, &fbi->fb.var);
-}
-
-static void pxafb_setup_gpio(struct pxafb_info *fbi)
-{
-        int gpio, ldd_bits;
-        unsigned int lccr0 = fbi->lccr0;
-
-        /*
-         * setup is based on type of panel supported
-         */
-
-        /* 4 bit interface */
-        if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
-            (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
-            (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
-                ldd_bits = 4;
-
-        /* 8 bit interface */
-        else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
-                  ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
-                   (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
-                 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
-                  (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
-                  (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
-                ldd_bits = 8;
-
-        /* 16 bit interface */
-        else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
-                 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
-                  (lccr0 & LCCR0_PAS) == LCCR0_Act))
-                ldd_bits = 16;
-
-        else {
-                printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
-                               "bits per pixel\n");
-                return;
-        }
-
-        for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
-                pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
-        /* 18 bit interface */
-        if (fbi->fb.var.bits_per_pixel > 16) {
-                pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT);
-                pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT);
-        }
-        pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
-        pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
-        pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
-
-        if ((lccr0 & LCCR0_PAS) == 0)
-                pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
+        if (fbi->lcd_power)
+                fbi->lcd_power(on, &fbi->fb.var);
 }
 
 static void pxafb_enable_controller(struct pxafb_info *fbi)
@@ -1056,6 +1384,7 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
                 return;
 
         /* Sequence from 11.7.10 */
+        lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
@@ -1097,8 +1426,9 @@ static void pxafb_disable_controller(struct pxafb_info *fbi)
 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
 {
         struct pxafb_info *fbi = dev_id;
-        unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
+        unsigned int lccr0, lcsr, lcsr1;
 
+        lcsr = lcd_readl(fbi, LCSR);
         if (lcsr & LCSR_LDD) {
                 lccr0 = lcd_readl(fbi, LCCR0);
                 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
@@ -1109,8 +1439,18 @@ static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
         if (lcsr & LCSR_CMD_INT)
                 complete(&fbi->command_done);
 #endif
-
         lcd_writel(fbi, LCSR, lcsr);
+
+#ifdef CONFIG_FB_PXA_OVERLAY
+        lcsr1 = lcd_readl(fbi, LCSR1);
+        if (lcsr1 & LCSR1_BS(1))
+                complete(&fbi->overlay[0].branch_done);
+
+        if (lcsr1 & LCSR1_BS(2))
+                complete(&fbi->overlay[1].branch_done);
+
+        lcd_writel(fbi, LCSR1, lcsr1);
+#endif
         return IRQ_HANDLED;
 }
 
@@ -1181,7 +1521,6 @@ static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
                 if (old_state == C_ENABLE) {
                         __pxafb_lcd_power(fbi, 0);
                         pxafb_disable_controller(fbi);
-                        pxafb_setup_gpio(fbi);
                         pxafb_enable_controller(fbi);
                         __pxafb_lcd_power(fbi, 1);
                 }
@@ -1204,7 +1543,6 @@ static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
                  */
                 if (old_state != C_ENABLE) {
                         fbi->state = C_ENABLE;
-                        pxafb_setup_gpio(fbi);
                         pxafb_enable_controller(fbi);
                         __pxafb_lcd_power(fbi, 1);
                         __pxafb_backlight_power(fbi, 1);
@@ -1303,77 +1641,34 @@ static int pxafb_resume(struct platform_device *dev)
 #define pxafb_resume    NULL
 #endif
 
-/*
- * pxafb_map_video_memory():
- *      Allocates the DRAM memory for the frame buffer.  This buffer is
- *      remapped into a non-cached, non-buffered, memory region to
- *      allow palette and pixel writes to occur without flushing the
- *      cache.  Once this area is remapped, all virtual memory
- *      access to the video memory should occur at the new region.
- */
-static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
+static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
 {
-        /*
-         * We reserve one page for the palette, plus the size
-         * of the framebuffer.
-         */
-        fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
-        fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
-        fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
-                                              &fbi->map_dma, GFP_KERNEL);
-
-        if (fbi->map_cpu) {
-                /* prevent initial garbage on screen */
-                memset(fbi->map_cpu, 0, fbi->map_size);
-                fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
-                fbi->screen_dma = fbi->map_dma + fbi->video_offset;
-
-                /*
-                 * FIXME: this is actually the wrong thing to place in
-                 * smem_start.  But fbdev suffers from the problem that
-                 * it needs an API which doesn't exist (in this case,
-                 * dma_writecombine_mmap)
-                 */
-                fbi->fb.fix.smem_start = fbi->screen_dma;
-                fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
-
-                fbi->dma_buff = (void *) fbi->map_cpu;
-                fbi->dma_buff_phys = fbi->map_dma;
-                fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
+        int size = PAGE_ALIGN(fbi->video_mem_size);
 
-                pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16));
+        fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
+        if (fbi->video_mem == NULL)
+                return -ENOMEM;
 
-#ifdef CONFIG_FB_PXA_SMARTPANEL
-                fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
-                fbi->n_smart_cmds = 0;
-#endif
-        }
-
-        return fbi->map_cpu ? 0 : -ENOMEM;
-}
+        fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
+        fbi->video_mem_size = size;
 
-static void pxafb_decode_mode_info(struct pxafb_info *fbi,
-                                   struct pxafb_mode_info *modes,
-                                   unsigned int num_modes)
-{
-        unsigned int i, smemlen;
-
-        pxafb_setmode(&fbi->fb.var, &modes[0]);
+        fbi->fb.fix.smem_start  = fbi->video_mem_phys;
+        fbi->fb.fix.smem_len    = fbi->video_mem_size;
+        fbi->fb.screen_base     = fbi->video_mem;
 
-        for (i = 0; i < num_modes; i++) {
-                smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
-                if (smemlen > fbi->fb.fix.smem_len)
-                        fbi->fb.fix.smem_len = smemlen;
-        }
+        return fbi->video_mem ? 0 : -ENOMEM;
 }
 
 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
                                    struct pxafb_mach_info *inf)
 {
         unsigned int lcd_conn = inf->lcd_conn;
+        struct pxafb_mode_info *m;
+        int i;
 
         fbi->cmap_inverse       = inf->cmap_inverse;
         fbi->cmap_static        = inf->cmap_static;
+        fbi->lccr4              = inf->lccr4;
 
         switch (lcd_conn & LCD_TYPE_MASK) {
         case LCD_TYPE_MONO_STN:
@@ -1398,7 +1693,6 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
                 /* fall back to backward compatibility way */
                 fbi->lccr0 = inf->lccr0;
                 fbi->lccr3 = inf->lccr3;
-                fbi->lccr4 = inf->lccr4;
                 goto decode_mode;
         }
 
@@ -1412,7 +1706,22 @@ static void pxafb_decode_mach_info(struct pxafb_info *fbi,
         fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL)  ? LCCR3_PCP : 0;
 
 decode_mode:
-        pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
+        pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
+
+        /* decide video memory size as follows:
+         * 1. default to mode of maximum resolution
+         * 2. allow platform to override
+         * 3. allow module parameter to override
+         */
+        for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
+                fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
+                                m->xres * m->yres * m->bpp / 8);
+
+        if (inf->video_mem_size > fbi->video_mem_size)
+                fbi->video_mem_size = inf->video_mem_size;
+
+        if (video_mem_size > fbi->video_mem_size)
+                fbi->video_mem_size = video_mem_size;
 }
 
 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
@@ -1429,7 +1738,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
         memset(fbi, 0, sizeof(struct pxafb_info));
         fbi->dev = dev;
 
-        fbi->clk = clk_get(dev, "LCDCLK");
+        fbi->clk = clk_get(dev, NULL);
         if (IS_ERR(fbi->clk)) {
                 kfree(fbi);
                 return NULL;
@@ -1440,7 +1749,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
         fbi->fb.fix.type_aux    = 0;
         fbi->fb.fix.xpanstep    = 0;
-        fbi->fb.fix.ypanstep    = 0;
+        fbi->fb.fix.ypanstep    = 1;
         fbi->fb.fix.ywrapstep   = 0;
         fbi->fb.fix.accel       = FB_ACCEL_NONE;
 
@@ -1448,7 +1757,7 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
         fbi->fb.var.height      = -1;
         fbi->fb.var.width       = -1;
-        fbi->fb.var.accel_flags = 0;
+        fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
 
         fbi->fb.fbops           = &pxafb_ops;
@@ -1468,10 +1777,6 @@ static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
         INIT_WORK(&fbi->task, pxafb_task);
         mutex_init(&fbi->ctrlr_lock);
         init_completion(&fbi->disable_done);
-#ifdef CONFIG_FB_PXA_SMARTPANEL
-        init_completion(&fbi->command_done);
-        init_completion(&fbi->refresh_done);
-#endif
 
         return fbi;
 }
@@ -1544,7 +1849,9 @@ static int __devinit parse_opt(struct device *dev, char *this_opt)
 
         s[0] = '\0';
 
-        if (!strncmp(this_opt, "mode:", 5)) {
+        if (!strncmp(this_opt, "vmem:", 5)) {
+                video_mem_size = memparse(this_opt + 5, NULL);
+        } else if (!strncmp(this_opt, "mode:", 5)) {
                 return parse_opt_mode(dev, this_opt);
         } else if (!strncmp(this_opt, "pixclock:", 9)) {
                 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
@@ -1748,8 +2055,7 @@ static int __devinit pxafb_probe(struct platform_device *dev)
                 ret = -EINVAL;
                 goto failed;
         }
-        pxafb_backlight_power = inf->pxafb_backlight_power;
-        pxafb_lcd_power = inf->pxafb_lcd_power;
+
         fbi = pxafb_init_fbinfo(&dev->dev);
         if (!fbi) {
                 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
@@ -1758,6 +2064,9 @@ static int __devinit pxafb_probe(struct platform_device *dev)
                 goto failed;
         }
 
+        fbi->backlight_power = inf->pxafb_backlight_power;
+        fbi->lcd_power = inf->pxafb_lcd_power;
+
         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
         if (r == NULL) {
                 dev_err(&dev->dev, "no I/O memory resource defined\n");
@@ -1779,12 +2088,20 @@ static int __devinit pxafb_probe(struct platform_device *dev)
                 goto failed_free_res;
         }
 
-        /* Initialize video memory */
-        ret = pxafb_map_video_memory(fbi);
+        fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
+        fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
+                                &fbi->dma_buff_phys, GFP_KERNEL);
+        if (fbi->dma_buff == NULL) {
+                dev_err(&dev->dev, "failed to allocate memory for DMA\n");
+                ret = -ENOMEM;
+                goto failed_free_io;
+        }
+
+        ret = pxafb_init_video_memory(fbi);
         if (ret) {
                 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
                 ret = -ENOMEM;
-                goto failed_free_io;
+                goto failed_free_dma;
         }
 
         irq = platform_get_irq(dev, 0);
@@ -1801,13 +2118,12 @@ static int __devinit pxafb_probe(struct platform_device *dev)
                 goto failed_free_mem;
         }
 
-#ifdef CONFIG_FB_PXA_SMARTPANEL
         ret = pxafb_smart_init(fbi);
         if (ret) {
                 dev_err(&dev->dev, "failed to initialize smartpanel\n");
                 goto failed_free_irq;
         }
-#endif
+
         /*
          * This makes sure that our colour bitfield
          * descriptors are correctly initialised.
@@ -1833,6 +2149,8 @@ static int __devinit pxafb_probe(struct platform_device *dev)
                 goto failed_free_cmap;
         }
 
+        pxafb_overlay_init(fbi);
+
 #ifdef CONFIG_CPU_FREQ
         fbi->freq_transition.notifier_call = pxafb_freq_transition;
         fbi->freq_policy.notifier_call = pxafb_freq_policy;
@@ -1855,8 +2173,10 @@ failed_free_cmap:
 failed_free_irq:
         free_irq(irq, fbi);
 failed_free_mem:
-        dma_free_writecombine(&dev->dev, fbi->map_size,
-                        fbi->map_cpu, fbi->map_dma);
+        free_pages_exact(fbi->video_mem, fbi->video_mem_size);
+failed_free_dma:
+        dma_free_coherent(&dev->dev, fbi->dma_buff_size,
+                        fbi->dma_buff, fbi->dma_buff_phys);
 failed_free_io:
         iounmap(fbi->mmio_base);
 failed_free_res:
@@ -1881,6 +2201,7 @@ static int __devexit pxafb_remove(struct platform_device *dev)
 
         info = &fbi->fb;
 
+        pxafb_overlay_exit(fbi);
         unregister_framebuffer(info);
 
         pxafb_disable_controller(fbi);
@@ -1891,8 +2212,10 @@ static int __devexit pxafb_remove(struct platform_device *dev)
         irq = platform_get_irq(dev, 0);
         free_irq(irq, fbi);
 
-        dma_free_writecombine(&dev->dev, fbi->map_size,
-                                        fbi->map_cpu, fbi->map_dma);
+        free_pages_exact(fbi->video_mem, fbi->video_mem_size);
+
+        dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
+                        fbi->dma_buff, fbi->dma_buff_phys);
 
         iounmap(fbi->mmio_base);
 
diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h
index 31541b86f13d..2353521c5c8c 100644
--- a/drivers/video/pxafb.h
+++ b/drivers/video/pxafb.h
@@ -54,11 +54,55 @@ enum {
 #define PALETTE_SIZE    (256 * 4)
 #define CMD_BUFF_SIZE   (1024 * 50)
 
+/* NOTE: the palette and frame dma descriptors are doubled to allow
+ * the 2nd set for branch settings (FBRx)
+ */
 struct pxafb_dma_buff {
         unsigned char palette[PAL_MAX * PALETTE_SIZE];
         uint16_t cmd_buff[CMD_BUFF_SIZE];
-        struct pxafb_dma_descriptor pal_desc[PAL_MAX];
-        struct pxafb_dma_descriptor dma_desc[DMA_MAX];
+        struct pxafb_dma_descriptor pal_desc[PAL_MAX * 2];
+        struct pxafb_dma_descriptor dma_desc[DMA_MAX * 2];
+};
+
+enum {
+        OVERLAY1,
+        OVERLAY2,
+};
+
+enum {
+        OVERLAY_FORMAT_RGB = 0,
+        OVERLAY_FORMAT_YUV444_PACKED,
+        OVERLAY_FORMAT_YUV444_PLANAR,
+        OVERLAY_FORMAT_YUV422_PLANAR,
+        OVERLAY_FORMAT_YUV420_PLANAR,
+};
+
+#define NONSTD_TO_XPOS(x)       (((x) >> 0)  & 0x3ff)
+#define NONSTD_TO_YPOS(x)       (((x) >> 10) & 0x3ff)
+#define NONSTD_TO_PFOR(x)       (((x) >> 20) & 0x7)
+
+struct pxafb_layer;
+
+struct pxafb_layer_ops {
+        void (*enable)(struct pxafb_layer *);
+        void (*disable)(struct pxafb_layer *);
+        void (*setup)(struct pxafb_layer *);
+};
+
+struct pxafb_layer {
+        struct fb_info          fb;
+        int                     id;
+        atomic_t                usage;
+        uint32_t                control[2];
+
+        struct pxafb_layer_ops  *ops;
+
+        void __iomem            *video_mem;
+        unsigned long           video_mem_phys;
+        size_t                  video_mem_size;
+        struct completion       branch_done;
+
+        struct pxafb_info       *fbi;
 };
 
 struct pxafb_info {
@@ -69,24 +113,15 @@ struct pxafb_info {
         void __iomem            *mmio_base;
 
         struct pxafb_dma_buff   *dma_buff;
+        size_t                  dma_buff_size;
         dma_addr_t              dma_buff_phys;
-        dma_addr_t              fdadr[DMA_MAX];
-
-        /*
-         * These are the addresses we mapped
-         * the framebuffer memory region to.
-         */
-        /* raw memory addresses */
-        dma_addr_t              map_dma;        /* physical */
-        u_char *                map_cpu;        /* virtual */
-        u_int                   map_size;
-
-        /* addresses of pieces placed in raw buffer */
-        u_char *                screen_cpu;     /* virtual address of frame buffer */
-        dma_addr_t              screen_dma;     /* physical address of frame buffer */
+        dma_addr_t              fdadr[DMA_MAX * 2];
+
+        void __iomem            *video_mem;     /* virtual address of frame buffer */
+        unsigned long           video_mem_phys; /* physical address of frame buffer */
+        size_t                  video_mem_size; /* size of the frame buffer */
         u16 *                   palette_cpu;    /* virtual address of palette memory */
         u_int                   palette_size;
-        ssize_t                 video_offset;
 
         u_int                   lccr0;
         u_int                   lccr3;
@@ -120,10 +155,17 @@ struct pxafb_info {
         struct task_struct      *smart_thread;
 #endif
 
+#ifdef CONFIG_FB_PXA_OVERLAY
+        struct pxafb_layer      overlay[2];
+#endif
+
 #ifdef CONFIG_CPU_FREQ
         struct notifier_block   freq_transition;
         struct notifier_block   freq_policy;
 #endif
+
+        void (*lcd_power)(int, struct fb_var_screeninfo *);
+        void (*backlight_power)(int);
 };
 
 #define TO_INF(ptr,member) container_of(ptr,struct pxafb_info,member)
@@ -148,4 +190,10 @@ struct pxafb_info {
 #define MIN_XRES        64
 #define MIN_YRES        64
 
+/* maximum X and Y resolutions - note these are limits from the register
+ * bits length instead of the real ones
+ */
+#define MAX_XRES        1024
+#define MAX_YRES        1024
+
 #endif /* __PXAFB_H__ */
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c
index c052bd4c0b06..076f946fa0f5 100644
--- a/drivers/video/sa1100fb.c
+++ b/drivers/video/sa1100fb.c
@@ -114,7 +114,7 @@
  *      - convert dma address types to dma_addr_t
  *      - remove unused 'montype' stuff
  *      - remove redundant zero inits of init_var after the initial
- *        memzero.
+ *        memset.
  *      - remove allow_modeset (acornfb idea does not belong here)
  *
  * 2001/05/28: <rmk@arm.linux.org.uk>
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index f7f6ce82a5e2..e31925ee8346 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -42,7 +42,7 @@
 #undef S3C_VA_WATCHDOG
 #define S3C_VA_WATCHDOG (0)
 
-#include <asm/plat-s3c/regs-watchdog.h>
+#include <plat/regs-watchdog.h>
 
 #define PFX "s3c2410-wdt: "
 
diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c
index ed01e4c2beff..e19b45794717 100644
--- a/drivers/watchdog/sa1100_wdt.c
+++ b/drivers/watchdog/sa1100_wdt.c
@@ -27,6 +27,7 @@
 #include <linux/init.h>
 #include <linux/bitops.h>
 #include <linux/uaccess.h>
+#include <linux/timex.h>
 
 #ifdef CONFIG_ARCH_PXA
 #include <mach/pxa-regs.h>
@@ -35,8 +36,7 @@
 #include <mach/reset.h>
 #include <mach/hardware.h>
 
-#define OSCR_FREQ               CLOCK_TICK_RATE
-
+static unsigned long oscr_freq;
 static unsigned long sa1100wdt_users;
 static int pre_margin;
 static int boot_status;
@@ -123,12 +123,12 @@ static long sa1100dog_ioctl(struct file *file, unsigned int cmd,
                         break;
                 }
 
-                pre_margin = OSCR_FREQ * time;
+                pre_margin = oscr_freq * time;
                 OSMR3 = OSCR + pre_margin;
                 /*fall through*/
 
         case WDIOC_GETTIMEOUT:
-                ret = put_user(pre_margin / OSCR_FREQ, p);
+                ret = put_user(pre_margin / oscr_freq, p);
                 break;
         }
         return ret;
@@ -155,6 +155,8 @@ static int __init sa1100dog_init(void)
 {
         int ret;
 
+        oscr_freq = get_clock_tick_rate();
+
         /*
          * Read the reset status, and save it for later.  If
          * we suspend, RCSR will be cleared, and the watchdog
@@ -162,7 +164,7 @@ static int __init sa1100dog_init(void)
          */
         boot_status = (reset_status & RESET_STATUS_WATCHDOG) ?
                                 WDIOF_CARDRESET : 0;
-        pre_margin = OSCR_FREQ * margin;
+        pre_margin = oscr_freq * margin;
 
         ret = misc_register(&sa1100dog_miscdev);
         if (ret == 0)