diff options
author | Stephen Hemminger <shemminger@osdl.org> | 2005-09-09 15:54:56 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-09-14 08:32:07 -0400 |
commit | 46a60f2d718d56bba8695d6f1145eb40548d86f8 (patch) | |
tree | 2d4ef2035baac15a36dbad636ac84922c021f97f /drivers | |
parent | c535a9dd26d1a4c6dcbd486cbe181a9e71237af1 (diff) |
[PATCH] skge: gmac register access errors in dual port
Merge of four previous patches and the Kconfig fix
* Remove debug printk's
* whitespace cleanup and version number change
* clear interrupts, reset phy, and reset hardware on shutdown
* ignore 64bit counter overflow interrupts
* fix a couple of places where second port could clobber state
of first port.
Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/Kconfig | 2 | ||||
-rw-r--r-- | drivers/net/skge.c | 98 | ||||
-rw-r--r-- | drivers/net/skge.h | 2 |
3 files changed, 56 insertions, 46 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 54fff9c2e802..96f14ab1c1f5 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
@@ -1951,7 +1951,7 @@ config SKGE | |||
1951 | ---help--- | 1951 | ---help--- |
1952 | This driver support the Marvell Yukon or SysKonnect SK-98xx/SK-95xx | 1952 | This driver support the Marvell Yukon or SysKonnect SK-98xx/SK-95xx |
1953 | and related Gigabit Ethernet adapters. It is a new smaller driver | 1953 | and related Gigabit Ethernet adapters. It is a new smaller driver |
1954 | driver with better performance and more complete ethtool support. | 1954 | with better performance and more complete ethtool support. |
1955 | 1955 | ||
1956 | It does not support the link failover and network management | 1956 | It does not support the link failover and network management |
1957 | features that "portable" vendor supplied sk98lin driver does. | 1957 | features that "portable" vendor supplied sk98lin driver does. |
diff --git a/drivers/net/skge.c b/drivers/net/skge.c index d7c98515fdfd..0208258e7826 100644 --- a/drivers/net/skge.c +++ b/drivers/net/skge.c | |||
@@ -42,7 +42,7 @@ | |||
42 | #include "skge.h" | 42 | #include "skge.h" |
43 | 43 | ||
44 | #define DRV_NAME "skge" | 44 | #define DRV_NAME "skge" |
45 | #define DRV_VERSION "0.9" | 45 | #define DRV_VERSION "1.0" |
46 | #define PFX DRV_NAME " " | 46 | #define PFX DRV_NAME " " |
47 | 47 | ||
48 | #define DEFAULT_TX_RING_SIZE 128 | 48 | #define DEFAULT_TX_RING_SIZE 128 |
@@ -669,7 +669,7 @@ static void skge_led(struct skge_port *skge, enum led_mode mode) | |||
669 | PHY_M_LED_BLINK_RT(BLINK_84MS) | | 669 | PHY_M_LED_BLINK_RT(BLINK_84MS) | |
670 | PHY_M_LEDC_TX_CTRL | | 670 | PHY_M_LEDC_TX_CTRL | |
671 | PHY_M_LEDC_DP_CTRL); | 671 | PHY_M_LEDC_DP_CTRL); |
672 | 672 | ||
673 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, | 673 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
674 | PHY_M_LED_MO_RX(MO_LED_OFF) | | 674 | PHY_M_LED_MO_RX(MO_LED_OFF) | |
675 | (skge->speed == SPEED_100 ? | 675 | (skge->speed == SPEED_100 ? |
@@ -876,7 +876,7 @@ static int skge_rx_fill(struct skge_port *skge) | |||
876 | 876 | ||
877 | static void skge_link_up(struct skge_port *skge) | 877 | static void skge_link_up(struct skge_port *skge) |
878 | { | 878 | { |
879 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), | 879 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), |
880 | LED_BLK_OFF|LED_SYNC_OFF|LED_ON); | 880 | LED_BLK_OFF|LED_SYNC_OFF|LED_ON); |
881 | 881 | ||
882 | netif_carrier_on(skge->netdev); | 882 | netif_carrier_on(skge->netdev); |
@@ -987,6 +987,8 @@ static void genesis_reset(struct skge_hw *hw, int port) | |||
987 | { | 987 | { |
988 | const u8 zero[8] = { 0 }; | 988 | const u8 zero[8] = { 0 }; |
989 | 989 | ||
990 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | ||
991 | |||
990 | /* reset the statistics module */ | 992 | /* reset the statistics module */ |
991 | xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); | 993 | xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); |
992 | xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */ | 994 | xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */ |
@@ -1021,8 +1023,6 @@ static void bcom_check_link(struct skge_hw *hw, int port) | |||
1021 | (void) xm_phy_read(hw, port, PHY_BCOM_STAT); | 1023 | (void) xm_phy_read(hw, port, PHY_BCOM_STAT); |
1022 | status = xm_phy_read(hw, port, PHY_BCOM_STAT); | 1024 | status = xm_phy_read(hw, port, PHY_BCOM_STAT); |
1023 | 1025 | ||
1024 | pr_debug("bcom_check_link status=0x%x\n", status); | ||
1025 | |||
1026 | if ((status & PHY_ST_LSYNC) == 0) { | 1026 | if ((status & PHY_ST_LSYNC) == 0) { |
1027 | u16 cmd = xm_read16(hw, port, XM_MMU_CMD); | 1027 | u16 cmd = xm_read16(hw, port, XM_MMU_CMD); |
1028 | cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); | 1028 | cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); |
@@ -1106,8 +1106,6 @@ static void bcom_phy_init(struct skge_port *skge, int jumbo) | |||
1106 | { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, | 1106 | { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, |
1107 | }; | 1107 | }; |
1108 | 1108 | ||
1109 | pr_debug("bcom_phy_init\n"); | ||
1110 | |||
1111 | /* read Id from external PHY (all have the same address) */ | 1109 | /* read Id from external PHY (all have the same address) */ |
1112 | id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); | 1110 | id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); |
1113 | 1111 | ||
@@ -1340,6 +1338,8 @@ static void genesis_stop(struct skge_port *skge) | |||
1340 | int port = skge->port; | 1338 | int port = skge->port; |
1341 | u32 reg; | 1339 | u32 reg; |
1342 | 1340 | ||
1341 | genesis_reset(hw, port); | ||
1342 | |||
1343 | /* Clear Tx packet arbiter timeout IRQ */ | 1343 | /* Clear Tx packet arbiter timeout IRQ */ |
1344 | skge_write16(hw, B3_PA_CTRL, | 1344 | skge_write16(hw, B3_PA_CTRL, |
1345 | port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); | 1345 | port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); |
@@ -1465,7 +1465,6 @@ static void genesis_link_up(struct skge_port *skge) | |||
1465 | u16 cmd; | 1465 | u16 cmd; |
1466 | u32 mode, msk; | 1466 | u32 mode, msk; |
1467 | 1467 | ||
1468 | pr_debug("genesis_link_up\n"); | ||
1469 | cmd = xm_read16(hw, port, XM_MMU_CMD); | 1468 | cmd = xm_read16(hw, port, XM_MMU_CMD); |
1470 | 1469 | ||
1471 | /* | 1470 | /* |
@@ -1578,7 +1577,6 @@ static void yukon_init(struct skge_hw *hw, int port) | |||
1578 | struct skge_port *skge = netdev_priv(hw->dev[port]); | 1577 | struct skge_port *skge = netdev_priv(hw->dev[port]); |
1579 | u16 ctrl, ct1000, adv; | 1578 | u16 ctrl, ct1000, adv; |
1580 | 1579 | ||
1581 | pr_debug("yukon_init\n"); | ||
1582 | if (skge->autoneg == AUTONEG_ENABLE) { | 1580 | if (skge->autoneg == AUTONEG_ENABLE) { |
1583 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); | 1581 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
1584 | 1582 | ||
@@ -1677,9 +1675,11 @@ static void yukon_mac_init(struct skge_hw *hw, int port) | |||
1677 | 1675 | ||
1678 | /* WA code for COMA mode -- set PHY reset */ | 1676 | /* WA code for COMA mode -- set PHY reset */ |
1679 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | 1677 | if (hw->chip_id == CHIP_ID_YUKON_LITE && |
1680 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) | 1678 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
1681 | skge_write32(hw, B2_GP_IO, | 1679 | reg = skge_read32(hw, B2_GP_IO); |
1682 | (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9)); | 1680 | reg |= GP_DIR_9 | GP_IO_9; |
1681 | skge_write32(hw, B2_GP_IO, reg); | ||
1682 | } | ||
1683 | 1683 | ||
1684 | /* hard reset */ | 1684 | /* hard reset */ |
1685 | skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | 1685 | skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
@@ -1687,10 +1687,12 @@ static void yukon_mac_init(struct skge_hw *hw, int port) | |||
1687 | 1687 | ||
1688 | /* WA code for COMA mode -- clear PHY reset */ | 1688 | /* WA code for COMA mode -- clear PHY reset */ |
1689 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | 1689 | if (hw->chip_id == CHIP_ID_YUKON_LITE && |
1690 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) | 1690 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
1691 | skge_write32(hw, B2_GP_IO, | 1691 | reg = skge_read32(hw, B2_GP_IO); |
1692 | (skge_read32(hw, B2_GP_IO) | GP_DIR_9) | 1692 | reg |= GP_DIR_9; |
1693 | & ~GP_IO_9); | 1693 | reg &= ~GP_IO_9; |
1694 | skge_write32(hw, B2_GP_IO, reg); | ||
1695 | } | ||
1694 | 1696 | ||
1695 | /* Set hardware config mode */ | 1697 | /* Set hardware config mode */ |
1696 | reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | | 1698 | reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | |
@@ -1729,7 +1731,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port) | |||
1729 | } | 1731 | } |
1730 | 1732 | ||
1731 | gma_write16(hw, port, GM_GP_CTRL, reg); | 1733 | gma_write16(hw, port, GM_GP_CTRL, reg); |
1732 | skge_read16(hw, GMAC_IRQ_SRC); | 1734 | skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
1733 | 1735 | ||
1734 | yukon_init(hw, port); | 1736 | yukon_init(hw, port); |
1735 | 1737 | ||
@@ -1801,20 +1803,26 @@ static void yukon_stop(struct skge_port *skge) | |||
1801 | struct skge_hw *hw = skge->hw; | 1803 | struct skge_hw *hw = skge->hw; |
1802 | int port = skge->port; | 1804 | int port = skge->port; |
1803 | 1805 | ||
1804 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | 1806 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
1805 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { | 1807 | yukon_reset(hw, port); |
1806 | skge_write32(hw, B2_GP_IO, | ||
1807 | skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9); | ||
1808 | } | ||
1809 | 1808 | ||
1810 | gma_write16(hw, port, GM_GP_CTRL, | 1809 | gma_write16(hw, port, GM_GP_CTRL, |
1811 | gma_read16(hw, port, GM_GP_CTRL) | 1810 | gma_read16(hw, port, GM_GP_CTRL) |
1812 | & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); | 1811 | & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); |
1813 | gma_read16(hw, port, GM_GP_CTRL); | 1812 | gma_read16(hw, port, GM_GP_CTRL); |
1814 | 1813 | ||
1814 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | ||
1815 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { | ||
1816 | u32 io = skge_read32(hw, B2_GP_IO); | ||
1817 | |||
1818 | io |= GP_DIR_9 | GP_IO_9; | ||
1819 | skge_write32(hw, B2_GP_IO, io); | ||
1820 | skge_read32(hw, B2_GP_IO); | ||
1821 | } | ||
1822 | |||
1815 | /* set GPHY Control reset */ | 1823 | /* set GPHY Control reset */ |
1816 | skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | 1824 | skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
1817 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); | 1825 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1818 | } | 1826 | } |
1819 | 1827 | ||
1820 | static void yukon_get_stats(struct skge_port *skge, u64 *data) | 1828 | static void yukon_get_stats(struct skge_port *skge, u64 *data) |
@@ -1873,10 +1881,8 @@ static void yukon_link_up(struct skge_port *skge) | |||
1873 | int port = skge->port; | 1881 | int port = skge->port; |
1874 | u16 reg; | 1882 | u16 reg; |
1875 | 1883 | ||
1876 | pr_debug("yukon_link_up\n"); | ||
1877 | |||
1878 | /* Enable Transmit FIFO Underrun */ | 1884 | /* Enable Transmit FIFO Underrun */ |
1879 | skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK); | 1885 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
1880 | 1886 | ||
1881 | reg = gma_read16(hw, port, GM_GP_CTRL); | 1887 | reg = gma_read16(hw, port, GM_GP_CTRL); |
1882 | if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) | 1888 | if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) |
@@ -1896,7 +1902,6 @@ static void yukon_link_down(struct skge_port *skge) | |||
1896 | int port = skge->port; | 1902 | int port = skge->port; |
1897 | u16 ctrl; | 1903 | u16 ctrl; |
1898 | 1904 | ||
1899 | pr_debug("yukon_link_down\n"); | ||
1900 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | 1905 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); |
1901 | 1906 | ||
1902 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | 1907 | ctrl = gma_read16(hw, port, GM_GP_CTRL); |
@@ -2112,7 +2117,6 @@ static int skge_up(struct net_device *dev) | |||
2112 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); | 2117 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); |
2113 | skge_led(skge, LED_MODE_ON); | 2118 | skge_led(skge, LED_MODE_ON); |
2114 | 2119 | ||
2115 | pr_debug("skge_up completed\n"); | ||
2116 | return 0; | 2120 | return 0; |
2117 | 2121 | ||
2118 | free_rx_ring: | 2122 | free_rx_ring: |
@@ -2135,15 +2139,20 @@ static int skge_down(struct net_device *dev) | |||
2135 | 2139 | ||
2136 | netif_stop_queue(dev); | 2140 | netif_stop_queue(dev); |
2137 | 2141 | ||
2142 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); | ||
2143 | if (hw->chip_id == CHIP_ID_GENESIS) | ||
2144 | genesis_stop(skge); | ||
2145 | else | ||
2146 | yukon_stop(skge); | ||
2147 | |||
2148 | hw->intr_mask &= ~portirqmask[skge->port]; | ||
2149 | skge_write32(hw, B0_IMSK, hw->intr_mask); | ||
2150 | |||
2138 | /* Stop transmitter */ | 2151 | /* Stop transmitter */ |
2139 | skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); | 2152 | skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); |
2140 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | 2153 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), |
2141 | RB_RST_SET|RB_DIS_OP_MD); | 2154 | RB_RST_SET|RB_DIS_OP_MD); |
2142 | 2155 | ||
2143 | if (hw->chip_id == CHIP_ID_GENESIS) | ||
2144 | genesis_stop(skge); | ||
2145 | else | ||
2146 | yukon_stop(skge); | ||
2147 | 2156 | ||
2148 | /* Disable Force Sync bit and Enable Alloc bit */ | 2157 | /* Disable Force Sync bit and Enable Alloc bit */ |
2149 | skge_write8(hw, SK_REG(port, TXA_CTRL), | 2158 | skge_write8(hw, SK_REG(port, TXA_CTRL), |
@@ -2367,8 +2376,6 @@ static void genesis_set_multicast(struct net_device *dev) | |||
2367 | u32 mode; | 2376 | u32 mode; |
2368 | u8 filter[8]; | 2377 | u8 filter[8]; |
2369 | 2378 | ||
2370 | pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count); | ||
2371 | |||
2372 | mode = xm_read32(hw, port, XM_MODE); | 2379 | mode = xm_read32(hw, port, XM_MODE); |
2373 | mode |= XM_MD_ENA_HASH; | 2380 | mode |= XM_MD_ENA_HASH; |
2374 | if (dev->flags & IFF_PROMISC) | 2381 | if (dev->flags & IFF_PROMISC) |
@@ -2530,8 +2537,6 @@ static int skge_poll(struct net_device *dev, int *budget) | |||
2530 | unsigned int to_do = min(dev->quota, *budget); | 2537 | unsigned int to_do = min(dev->quota, *budget); |
2531 | unsigned int work_done = 0; | 2538 | unsigned int work_done = 0; |
2532 | 2539 | ||
2533 | pr_debug("skge_poll\n"); | ||
2534 | |||
2535 | for (e = ring->to_clean; work_done < to_do; e = e->next) { | 2540 | for (e = ring->to_clean; work_done < to_do; e = e->next) { |
2536 | struct skge_rx_desc *rd = e->desc; | 2541 | struct skge_rx_desc *rd = e->desc; |
2537 | struct sk_buff *skb; | 2542 | struct sk_buff *skb; |
@@ -2672,9 +2677,9 @@ static void skge_error_irq(struct skge_hw *hw) | |||
2672 | if (hw->chip_id == CHIP_ID_GENESIS) { | 2677 | if (hw->chip_id == CHIP_ID_GENESIS) { |
2673 | /* clear xmac errors */ | 2678 | /* clear xmac errors */ |
2674 | if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) | 2679 | if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) |
2675 | skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT); | 2680 | skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); |
2676 | if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) | 2681 | if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) |
2677 | skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT); | 2682 | skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); |
2678 | } else { | 2683 | } else { |
2679 | /* Timestamp (unused) overflow */ | 2684 | /* Timestamp (unused) overflow */ |
2680 | if (hwstatus & IS_IRQ_TIST_OV) | 2685 | if (hwstatus & IS_IRQ_TIST_OV) |
@@ -3000,9 +3005,6 @@ static int skge_reset(struct skge_hw *hw) | |||
3000 | 3005 | ||
3001 | skge_write32(hw, B0_IMSK, hw->intr_mask); | 3006 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
3002 | 3007 | ||
3003 | if (hw->chip_id != CHIP_ID_GENESIS) | ||
3004 | skge_write8(hw, GMAC_IRQ_MSK, 0); | ||
3005 | |||
3006 | spin_lock_bh(&hw->phy_lock); | 3008 | spin_lock_bh(&hw->phy_lock); |
3007 | for (i = 0; i < hw->ports; i++) { | 3009 | for (i = 0; i < hw->ports; i++) { |
3008 | if (hw->chip_id == CHIP_ID_GENESIS) | 3010 | if (hw->chip_id == CHIP_ID_GENESIS) |
@@ -3230,6 +3232,11 @@ static void __devexit skge_remove(struct pci_dev *pdev) | |||
3230 | dev0 = hw->dev[0]; | 3232 | dev0 = hw->dev[0]; |
3231 | unregister_netdev(dev0); | 3233 | unregister_netdev(dev0); |
3232 | 3234 | ||
3235 | skge_write32(hw, B0_IMSK, 0); | ||
3236 | skge_write16(hw, B0_LED, LED_STAT_OFF); | ||
3237 | skge_pci_clear(hw); | ||
3238 | skge_write8(hw, B0_CTST, CS_RST_SET); | ||
3239 | |||
3233 | tasklet_kill(&hw->ext_tasklet); | 3240 | tasklet_kill(&hw->ext_tasklet); |
3234 | 3241 | ||
3235 | free_irq(pdev->irq, hw); | 3242 | free_irq(pdev->irq, hw); |
@@ -3238,7 +3245,7 @@ static void __devexit skge_remove(struct pci_dev *pdev) | |||
3238 | if (dev1) | 3245 | if (dev1) |
3239 | free_netdev(dev1); | 3246 | free_netdev(dev1); |
3240 | free_netdev(dev0); | 3247 | free_netdev(dev0); |
3241 | skge_write16(hw, B0_LED, LED_STAT_OFF); | 3248 | |
3242 | iounmap(hw->regs); | 3249 | iounmap(hw->regs); |
3243 | kfree(hw); | 3250 | kfree(hw); |
3244 | pci_set_drvdata(pdev, NULL); | 3251 | pci_set_drvdata(pdev, NULL); |
@@ -3257,7 +3264,10 @@ static int skge_suspend(struct pci_dev *pdev, pm_message_t state) | |||
3257 | struct skge_port *skge = netdev_priv(dev); | 3264 | struct skge_port *skge = netdev_priv(dev); |
3258 | if (netif_running(dev)) { | 3265 | if (netif_running(dev)) { |
3259 | netif_carrier_off(dev); | 3266 | netif_carrier_off(dev); |
3260 | skge_down(dev); | 3267 | if (skge->wol) |
3268 | netif_stop_queue(dev); | ||
3269 | else | ||
3270 | skge_down(dev); | ||
3261 | } | 3271 | } |
3262 | netif_device_detach(dev); | 3272 | netif_device_detach(dev); |
3263 | wol |= skge->wol; | 3273 | wol |= skge->wol; |
diff --git a/drivers/net/skge.h b/drivers/net/skge.h index f1680beb8e68..efbf98c675d2 100644 --- a/drivers/net/skge.h +++ b/drivers/net/skge.h | |||
@@ -2008,7 +2008,7 @@ enum { | |||
2008 | GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */ | 2008 | GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */ |
2009 | GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */ | 2009 | GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */ |
2010 | 2010 | ||
2011 | #define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | GM_IS_TX_FF_UR) | 2011 | #define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR) |
2012 | 2012 | ||
2013 | /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ | 2013 | /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ |
2014 | /* Bits 15.. 2: reserved */ | 2014 | /* Bits 15.. 2: reserved */ |