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authorRoland Dreier <roland@topspin.com>2005-06-27 17:36:42 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-06-27 18:11:45 -0400
commit9e6970b5e96c3281e26b7d2e4e1839f356d5f5ff (patch)
tree79ab7364de036a1b40c43bd3d664744c78cc5618 /drivers
parent34a4a753d15f905158d77fb81adc9c19a02a4639 (diff)
[PATCH] IB/mthca: Enable unreliable connected transport
Add support for unreliable connected (UC) transport to mthca driver: - Add attributes for UC to modify QP table. - Add support for posting UC work requests. Signed-off-by: Roland Dreier <roland@topspin.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/infiniband/hw/mthca/mthca_qp.c79
1 files changed, 78 insertions, 1 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_qp.c b/drivers/infiniband/hw/mthca/mthca_qp.c
index 6bed9a3e3f0f..c62e7cf0ca3c 100644
--- a/drivers/infiniband/hw/mthca/mthca_qp.c
+++ b/drivers/infiniband/hw/mthca/mthca_qp.c
@@ -357,6 +357,9 @@ static const struct {
357 [UD] = (IB_QP_PKEY_INDEX | 357 [UD] = (IB_QP_PKEY_INDEX |
358 IB_QP_PORT | 358 IB_QP_PORT |
359 IB_QP_QKEY), 359 IB_QP_QKEY),
360 [UC] = (IB_QP_PKEY_INDEX |
361 IB_QP_PORT |
362 IB_QP_ACCESS_FLAGS),
360 [RC] = (IB_QP_PKEY_INDEX | 363 [RC] = (IB_QP_PKEY_INDEX |
361 IB_QP_PORT | 364 IB_QP_PORT |
362 IB_QP_ACCESS_FLAGS), 365 IB_QP_ACCESS_FLAGS),
@@ -378,6 +381,9 @@ static const struct {
378 [UD] = (IB_QP_PKEY_INDEX | 381 [UD] = (IB_QP_PKEY_INDEX |
379 IB_QP_PORT | 382 IB_QP_PORT |
380 IB_QP_QKEY), 383 IB_QP_QKEY),
384 [UC] = (IB_QP_PKEY_INDEX |
385 IB_QP_PORT |
386 IB_QP_ACCESS_FLAGS),
381 [RC] = (IB_QP_PKEY_INDEX | 387 [RC] = (IB_QP_PKEY_INDEX |
382 IB_QP_PORT | 388 IB_QP_PORT |
383 IB_QP_ACCESS_FLAGS), 389 IB_QP_ACCESS_FLAGS),
@@ -388,6 +394,11 @@ static const struct {
388 [IB_QPS_RTR] = { 394 [IB_QPS_RTR] = {
389 .trans = MTHCA_TRANS_INIT2RTR, 395 .trans = MTHCA_TRANS_INIT2RTR,
390 .req_param = { 396 .req_param = {
397 [UC] = (IB_QP_AV |
398 IB_QP_PATH_MTU |
399 IB_QP_DEST_QPN |
400 IB_QP_RQ_PSN |
401 IB_QP_MAX_DEST_RD_ATOMIC),
391 [RC] = (IB_QP_AV | 402 [RC] = (IB_QP_AV |
392 IB_QP_PATH_MTU | 403 IB_QP_PATH_MTU |
393 IB_QP_DEST_QPN | 404 IB_QP_DEST_QPN |
@@ -398,6 +409,9 @@ static const struct {
398 .opt_param = { 409 .opt_param = {
399 [UD] = (IB_QP_PKEY_INDEX | 410 [UD] = (IB_QP_PKEY_INDEX |
400 IB_QP_QKEY), 411 IB_QP_QKEY),
412 [UC] = (IB_QP_ALT_PATH |
413 IB_QP_ACCESS_FLAGS |
414 IB_QP_PKEY_INDEX),
401 [RC] = (IB_QP_ALT_PATH | 415 [RC] = (IB_QP_ALT_PATH |
402 IB_QP_ACCESS_FLAGS | 416 IB_QP_ACCESS_FLAGS |
403 IB_QP_PKEY_INDEX), 417 IB_QP_PKEY_INDEX),
@@ -413,6 +427,8 @@ static const struct {
413 .trans = MTHCA_TRANS_RTR2RTS, 427 .trans = MTHCA_TRANS_RTR2RTS,
414 .req_param = { 428 .req_param = {
415 [UD] = IB_QP_SQ_PSN, 429 [UD] = IB_QP_SQ_PSN,
430 [UC] = (IB_QP_SQ_PSN |
431 IB_QP_MAX_QP_RD_ATOMIC),
416 [RC] = (IB_QP_TIMEOUT | 432 [RC] = (IB_QP_TIMEOUT |
417 IB_QP_RETRY_CNT | 433 IB_QP_RETRY_CNT |
418 IB_QP_RNR_RETRY | 434 IB_QP_RNR_RETRY |
@@ -423,6 +439,11 @@ static const struct {
423 .opt_param = { 439 .opt_param = {
424 [UD] = (IB_QP_CUR_STATE | 440 [UD] = (IB_QP_CUR_STATE |
425 IB_QP_QKEY), 441 IB_QP_QKEY),
442 [UC] = (IB_QP_CUR_STATE |
443 IB_QP_ALT_PATH |
444 IB_QP_ACCESS_FLAGS |
445 IB_QP_PKEY_INDEX |
446 IB_QP_PATH_MIG_STATE),
426 [RC] = (IB_QP_CUR_STATE | 447 [RC] = (IB_QP_CUR_STATE |
427 IB_QP_ALT_PATH | 448 IB_QP_ALT_PATH |
428 IB_QP_ACCESS_FLAGS | 449 IB_QP_ACCESS_FLAGS |
@@ -442,6 +463,9 @@ static const struct {
442 .opt_param = { 463 .opt_param = {
443 [UD] = (IB_QP_CUR_STATE | 464 [UD] = (IB_QP_CUR_STATE |
444 IB_QP_QKEY), 465 IB_QP_QKEY),
466 [UC] = (IB_QP_ACCESS_FLAGS |
467 IB_QP_ALT_PATH |
468 IB_QP_PATH_MIG_STATE),
445 [RC] = (IB_QP_ACCESS_FLAGS | 469 [RC] = (IB_QP_ACCESS_FLAGS |
446 IB_QP_ALT_PATH | 470 IB_QP_ALT_PATH |
447 IB_QP_PATH_MIG_STATE | 471 IB_QP_PATH_MIG_STATE |
@@ -462,6 +486,10 @@ static const struct {
462 .opt_param = { 486 .opt_param = {
463 [UD] = (IB_QP_CUR_STATE | 487 [UD] = (IB_QP_CUR_STATE |
464 IB_QP_QKEY), 488 IB_QP_QKEY),
489 [UC] = (IB_QP_CUR_STATE |
490 IB_QP_ALT_PATH |
491 IB_QP_ACCESS_FLAGS |
492 IB_QP_PATH_MIG_STATE),
465 [RC] = (IB_QP_CUR_STATE | 493 [RC] = (IB_QP_CUR_STATE |
466 IB_QP_ALT_PATH | 494 IB_QP_ALT_PATH |
467 IB_QP_ACCESS_FLAGS | 495 IB_QP_ACCESS_FLAGS |
@@ -476,6 +504,14 @@ static const struct {
476 .opt_param = { 504 .opt_param = {
477 [UD] = (IB_QP_PKEY_INDEX | 505 [UD] = (IB_QP_PKEY_INDEX |
478 IB_QP_QKEY), 506 IB_QP_QKEY),
507 [UC] = (IB_QP_AV |
508 IB_QP_MAX_QP_RD_ATOMIC |
509 IB_QP_MAX_DEST_RD_ATOMIC |
510 IB_QP_CUR_STATE |
511 IB_QP_ALT_PATH |
512 IB_QP_ACCESS_FLAGS |
513 IB_QP_PKEY_INDEX |
514 IB_QP_PATH_MIG_STATE),
479 [RC] = (IB_QP_AV | 515 [RC] = (IB_QP_AV |
480 IB_QP_TIMEOUT | 516 IB_QP_TIMEOUT |
481 IB_QP_RETRY_CNT | 517 IB_QP_RETRY_CNT |
@@ -501,6 +537,7 @@ static const struct {
501 .opt_param = { 537 .opt_param = {
502 [UD] = (IB_QP_CUR_STATE | 538 [UD] = (IB_QP_CUR_STATE |
503 IB_QP_QKEY), 539 IB_QP_QKEY),
540 [UC] = (IB_QP_CUR_STATE),
504 [RC] = (IB_QP_CUR_STATE | 541 [RC] = (IB_QP_CUR_STATE |
505 IB_QP_MIN_RNR_TIMER), 542 IB_QP_MIN_RNR_TIMER),
506 [MLX] = (IB_QP_CUR_STATE | 543 [MLX] = (IB_QP_CUR_STATE |
@@ -1530,6 +1567,26 @@ int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1530 1567
1531 break; 1568 break;
1532 1569
1570 case UC:
1571 switch (wr->opcode) {
1572 case IB_WR_RDMA_WRITE:
1573 case IB_WR_RDMA_WRITE_WITH_IMM:
1574 ((struct mthca_raddr_seg *) wqe)->raddr =
1575 cpu_to_be64(wr->wr.rdma.remote_addr);
1576 ((struct mthca_raddr_seg *) wqe)->rkey =
1577 cpu_to_be32(wr->wr.rdma.rkey);
1578 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1579 wqe += sizeof (struct mthca_raddr_seg);
1580 size += sizeof (struct mthca_raddr_seg) / 16;
1581 break;
1582
1583 default:
1584 /* No extra segments required for sends */
1585 break;
1586 }
1587
1588 break;
1589
1533 case UD: 1590 case UD:
1534 ((struct mthca_tavor_ud_seg *) wqe)->lkey = 1591 ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1535 cpu_to_be32(to_mah(wr->wr.ud.ah)->key); 1592 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
@@ -1815,9 +1872,29 @@ int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1815 sizeof (struct mthca_atomic_seg); 1872 sizeof (struct mthca_atomic_seg);
1816 break; 1873 break;
1817 1874
1875 case IB_WR_RDMA_READ:
1876 case IB_WR_RDMA_WRITE:
1877 case IB_WR_RDMA_WRITE_WITH_IMM:
1878 ((struct mthca_raddr_seg *) wqe)->raddr =
1879 cpu_to_be64(wr->wr.rdma.remote_addr);
1880 ((struct mthca_raddr_seg *) wqe)->rkey =
1881 cpu_to_be32(wr->wr.rdma.rkey);
1882 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1883 wqe += sizeof (struct mthca_raddr_seg);
1884 size += sizeof (struct mthca_raddr_seg) / 16;
1885 break;
1886
1887 default:
1888 /* No extra segments required for sends */
1889 break;
1890 }
1891
1892 break;
1893
1894 case UC:
1895 switch (wr->opcode) {
1818 case IB_WR_RDMA_WRITE: 1896 case IB_WR_RDMA_WRITE:
1819 case IB_WR_RDMA_WRITE_WITH_IMM: 1897 case IB_WR_RDMA_WRITE_WITH_IMM:
1820 case IB_WR_RDMA_READ:
1821 ((struct mthca_raddr_seg *) wqe)->raddr = 1898 ((struct mthca_raddr_seg *) wqe)->raddr =
1822 cpu_to_be64(wr->wr.rdma.remote_addr); 1899 cpu_to_be64(wr->wr.rdma.remote_addr);
1823 ((struct mthca_raddr_seg *) wqe)->rkey = 1900 ((struct mthca_raddr_seg *) wqe)->rkey =
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 20:12:33 -0500