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authorJeff Garzik <jeff@garzik.org>2006-12-07 17:56:06 -0500
committerJeff Garzik <jeff@garzik.org>2006-12-07 17:56:06 -0500
commit1769b46a3ed9ce68c835f84493be46e606e58ef1 (patch)
tree28188bdf8ac4a7562ef896b7013c29f6a3b9bf30 /drivers
parentff51a98799931256b555446b2f5675db08de6229 (diff)
PCI MSI: always toggle legacy-INTx-enable bit upon MSI entry/exit
The current code (prior to this change) would disable the PCI INTx legacy interrupt when enabling MSI... but only on PCI Express. We should do this for all MSI devices, for safety's sake. Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/msi.c12
1 files changed, 4 insertions, 8 deletions
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 9fc9a34ef24a..c2828a37c2f7 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -255,10 +255,8 @@ static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
255 pci_write_config_word(dev, msi_control_reg(pos), control); 255 pci_write_config_word(dev, msi_control_reg(pos), control);
256 dev->msix_enabled = 1; 256 dev->msix_enabled = 1;
257 } 257 }
258 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { 258
259 /* PCI Express Endpoint device detected */ 259 pci_intx(dev, 0); /* disable intx */
260 pci_intx(dev, 0); /* disable intx */
261 }
262} 260}
263 261
264void disable_msi_mode(struct pci_dev *dev, int pos, int type) 262void disable_msi_mode(struct pci_dev *dev, int pos, int type)
@@ -276,10 +274,8 @@ void disable_msi_mode(struct pci_dev *dev, int pos, int type)
276 pci_write_config_word(dev, msi_control_reg(pos), control); 274 pci_write_config_word(dev, msi_control_reg(pos), control);
277 dev->msix_enabled = 0; 275 dev->msix_enabled = 0;
278 } 276 }
279 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) { 277
280 /* PCI Express Endpoint device detected */ 278 pci_intx(dev, 1); /* enable intx */
281 pci_intx(dev, 1); /* enable intx */
282 }
283} 279}
284 280
285static int msi_lookup_irq(struct pci_dev *dev, int type) 281static int msi_lookup_irq(struct pci_dev *dev, int type)