diff options
author | Jeff Garzik <jeff@garzik.org> | 2006-04-12 18:04:32 -0400 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2006-04-12 18:04:32 -0400 |
commit | 10badc215493a435e2dbdc691386f2650a1778de (patch) | |
tree | b8525258892ee56c3ceb7e0d9e2e74a4ecf0f88d /drivers | |
parent | 8056bfafb8a845f3035e7aae5ffe405df118bc12 (diff) |
[netdrvr b44] trim trailing whitespace
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/b44.c | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/net/b44.c b/drivers/net/b44.c index aa1ef74792c6..3d306681919e 100644 --- a/drivers/net/b44.c +++ b/drivers/net/b44.c | |||
@@ -137,7 +137,7 @@ static inline unsigned long br32(const struct b44 *bp, unsigned long reg) | |||
137 | return readl(bp->regs + reg); | 137 | return readl(bp->regs + reg); |
138 | } | 138 | } |
139 | 139 | ||
140 | static inline void bw32(const struct b44 *bp, | 140 | static inline void bw32(const struct b44 *bp, |
141 | unsigned long reg, unsigned long val) | 141 | unsigned long reg, unsigned long val) |
142 | { | 142 | { |
143 | writel(val, bp->regs + reg); | 143 | writel(val, bp->regs + reg); |
@@ -287,13 +287,13 @@ static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index) | |||
287 | val |= ((u32) data[4]) << 8; | 287 | val |= ((u32) data[4]) << 8; |
288 | val |= ((u32) data[5]) << 0; | 288 | val |= ((u32) data[5]) << 0; |
289 | bw32(bp, B44_CAM_DATA_LO, val); | 289 | bw32(bp, B44_CAM_DATA_LO, val); |
290 | val = (CAM_DATA_HI_VALID | | 290 | val = (CAM_DATA_HI_VALID | |
291 | (((u32) data[0]) << 8) | | 291 | (((u32) data[0]) << 8) | |
292 | (((u32) data[1]) << 0)); | 292 | (((u32) data[1]) << 0)); |
293 | bw32(bp, B44_CAM_DATA_HI, val); | 293 | bw32(bp, B44_CAM_DATA_HI, val); |
294 | bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE | | 294 | bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE | |
295 | (index << CAM_CTRL_INDEX_SHIFT))); | 295 | (index << CAM_CTRL_INDEX_SHIFT))); |
296 | b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1); | 296 | b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1); |
297 | } | 297 | } |
298 | 298 | ||
299 | static inline void __b44_disable_ints(struct b44 *bp) | 299 | static inline void __b44_disable_ints(struct b44 *bp) |
@@ -411,15 +411,15 @@ static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags) | |||
411 | 411 | ||
412 | static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote) | 412 | static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote) |
413 | { | 413 | { |
414 | u32 pause_enab = 0; | 414 | u32 pause_enab = 0; |
415 | 415 | ||
416 | /* The driver supports only rx pause by default because | 416 | /* The driver supports only rx pause by default because |
417 | the b44 mac tx pause mechanism generates excessive | 417 | the b44 mac tx pause mechanism generates excessive |
418 | pause frames. | 418 | pause frames. |
419 | Use ethtool to turn on b44 tx pause if necessary. | 419 | Use ethtool to turn on b44 tx pause if necessary. |
420 | */ | 420 | */ |
421 | if ((local & ADVERTISE_PAUSE_CAP) && | 421 | if ((local & ADVERTISE_PAUSE_CAP) && |
422 | (local & ADVERTISE_PAUSE_ASYM)){ | 422 | (local & ADVERTISE_PAUSE_ASYM)){ |
423 | if ((remote & LPA_PAUSE_ASYM) && | 423 | if ((remote & LPA_PAUSE_ASYM) && |
424 | !(remote & LPA_PAUSE_CAP)) | 424 | !(remote & LPA_PAUSE_CAP)) |
425 | pause_enab |= B44_FLAG_RX_PAUSE; | 425 | pause_enab |= B44_FLAG_RX_PAUSE; |
@@ -1057,7 +1057,7 @@ static int b44_change_mtu(struct net_device *dev, int new_mtu) | |||
1057 | spin_unlock_irq(&bp->lock); | 1057 | spin_unlock_irq(&bp->lock); |
1058 | 1058 | ||
1059 | b44_enable_ints(bp); | 1059 | b44_enable_ints(bp); |
1060 | 1060 | ||
1061 | return 0; | 1061 | return 0; |
1062 | } | 1062 | } |
1063 | 1063 | ||
@@ -1375,7 +1375,7 @@ static void b44_init_hw(struct b44 *bp) | |||
1375 | bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset); | 1375 | bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset); |
1376 | 1376 | ||
1377 | bw32(bp, B44_DMARX_PTR, bp->rx_pending); | 1377 | bw32(bp, B44_DMARX_PTR, bp->rx_pending); |
1378 | bp->rx_prod = bp->rx_pending; | 1378 | bp->rx_prod = bp->rx_pending; |
1379 | 1379 | ||
1380 | bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ); | 1380 | bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ); |
1381 | 1381 | ||
@@ -1547,9 +1547,9 @@ static void __b44_set_rx_mode(struct net_device *dev) | |||
1547 | val |= RXCONFIG_ALLMULTI; | 1547 | val |= RXCONFIG_ALLMULTI; |
1548 | else | 1548 | else |
1549 | i = __b44_load_mcast(bp, dev); | 1549 | i = __b44_load_mcast(bp, dev); |
1550 | 1550 | ||
1551 | for (; i < 64; i++) { | 1551 | for (; i < 64; i++) { |
1552 | __b44_cam_write(bp, zero, i); | 1552 | __b44_cam_write(bp, zero, i); |
1553 | } | 1553 | } |
1554 | bw32(bp, B44_RXCONFIG, val); | 1554 | bw32(bp, B44_RXCONFIG, val); |
1555 | val = br32(bp, B44_CAM_CTRL); | 1555 | val = br32(bp, B44_CAM_CTRL); |
@@ -1731,7 +1731,7 @@ static int b44_set_ringparam(struct net_device *dev, | |||
1731 | spin_unlock_irq(&bp->lock); | 1731 | spin_unlock_irq(&bp->lock); |
1732 | 1732 | ||
1733 | b44_enable_ints(bp); | 1733 | b44_enable_ints(bp); |
1734 | 1734 | ||
1735 | return 0; | 1735 | return 0; |
1736 | } | 1736 | } |
1737 | 1737 | ||
@@ -1776,7 +1776,7 @@ static int b44_set_pauseparam(struct net_device *dev, | |||
1776 | spin_unlock_irq(&bp->lock); | 1776 | spin_unlock_irq(&bp->lock); |
1777 | 1777 | ||
1778 | b44_enable_ints(bp); | 1778 | b44_enable_ints(bp); |
1779 | 1779 | ||
1780 | return 0; | 1780 | return 0; |
1781 | } | 1781 | } |
1782 | 1782 | ||
@@ -1892,7 +1892,7 @@ static int __devinit b44_get_invariants(struct b44 *bp) | |||
1892 | bp->core_unit = ssb_core_unit(bp); | 1892 | bp->core_unit = ssb_core_unit(bp); |
1893 | bp->dma_offset = SB_PCI_DMA; | 1893 | bp->dma_offset = SB_PCI_DMA; |
1894 | 1894 | ||
1895 | /* XXX - really required? | 1895 | /* XXX - really required? |
1896 | bp->flags |= B44_FLAG_BUGGY_TXPTR; | 1896 | bp->flags |= B44_FLAG_BUGGY_TXPTR; |
1897 | */ | 1897 | */ |
1898 | out: | 1898 | out: |
@@ -1940,7 +1940,7 @@ static int __devinit b44_init_one(struct pci_dev *pdev, | |||
1940 | "aborting.\n"); | 1940 | "aborting.\n"); |
1941 | goto err_out_free_res; | 1941 | goto err_out_free_res; |
1942 | } | 1942 | } |
1943 | 1943 | ||
1944 | err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK); | 1944 | err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK); |
1945 | if (err) { | 1945 | if (err) { |
1946 | printk(KERN_ERR PFX "No usable DMA configuration, " | 1946 | printk(KERN_ERR PFX "No usable DMA configuration, " |
@@ -2035,9 +2035,9 @@ static int __devinit b44_init_one(struct pci_dev *pdev, | |||
2035 | 2035 | ||
2036 | pci_save_state(bp->pdev); | 2036 | pci_save_state(bp->pdev); |
2037 | 2037 | ||
2038 | /* Chip reset provides power to the b44 MAC & PCI cores, which | 2038 | /* Chip reset provides power to the b44 MAC & PCI cores, which |
2039 | * is necessary for MAC register access. | 2039 | * is necessary for MAC register access. |
2040 | */ | 2040 | */ |
2041 | b44_chip_reset(bp); | 2041 | b44_chip_reset(bp); |
2042 | 2042 | ||
2043 | printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name); | 2043 | printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name); |
@@ -2085,10 +2085,10 @@ static int b44_suspend(struct pci_dev *pdev, pm_message_t state) | |||
2085 | 2085 | ||
2086 | del_timer_sync(&bp->timer); | 2086 | del_timer_sync(&bp->timer); |
2087 | 2087 | ||
2088 | spin_lock_irq(&bp->lock); | 2088 | spin_lock_irq(&bp->lock); |
2089 | 2089 | ||
2090 | b44_halt(bp); | 2090 | b44_halt(bp); |
2091 | netif_carrier_off(bp->dev); | 2091 | netif_carrier_off(bp->dev); |
2092 | netif_device_detach(bp->dev); | 2092 | netif_device_detach(bp->dev); |
2093 | b44_free_rings(bp); | 2093 | b44_free_rings(bp); |
2094 | 2094 | ||