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authorAlan Cox <alan@linux.intel.com>2009-08-27 06:01:57 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2009-09-15 15:02:28 -0400
commit356c74b401f6b05ae5d793e9d1a9ba8297b8e3ff (patch)
tree9c5aaad97326bbaf453b825b024b32756d2a951c /drivers
parentf2c98d27b8e88cd17bb3e77f8fccf70f8d2ebd2f (diff)
Staging: et131x: clean up DMA10/DMA4 types
Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/staging/et131x/et1310_address_map.h150
-rw-r--r--drivers/staging/et131x/et1310_rx.c60
-rw-r--r--drivers/staging/et131x/et1310_rx.h4
-rw-r--r--drivers/staging/et131x/et1310_tx.c93
-rw-r--r--drivers/staging/et131x/et1310_tx.h6
-rw-r--r--drivers/staging/et131x/et131x_netdev.c8
6 files changed, 120 insertions, 201 deletions
diff --git a/drivers/staging/et131x/et1310_address_map.h b/drivers/staging/et131x/et1310_address_map.h
index 8aaa62bc1138..285c4a8987a0 100644
--- a/drivers/staging/et131x/et1310_address_map.h
+++ b/drivers/staging/et131x/et1310_address_map.h
@@ -329,94 +329,40 @@ typedef union _TXDMA_PR_NUM_DES_t {
329} TXDMA_PR_NUM_DES_t, *PTXDMA_PR_NUM_DES_t; 329} TXDMA_PR_NUM_DES_t, *PTXDMA_PR_NUM_DES_t;
330 330
331 331
332typedef union _DMA10W_t { 332#define ET_DMA10_MASK 0x3FF /* 10 bit mask for DMA10W types */
333 u32 value; 333#define ET_DMA10_WRAP 0x400
334 struct { 334#define ET_DMA4_MASK 0x00F /* 4 bit mask for DMA4W types */
335#ifdef _BIT_FIELDS_HTOL 335#define ET_DMA4_WRAP 0x010
336 u32 unused:21; /* bits 11-31 */
337 u32 wrap:1; /* bit 10 */
338 u32 val:10; /* bits 0-9 */
339#else
340 u32 val:10; /* bits 0-9 */
341 u32 wrap:1; /* bit 10 */
342 u32 unused:21; /* bits 11-31 */
343#endif
344 } bits;
345} DMA10W_t, *PDMA10W_t;
346
347/*
348 * structure for txdma tx queue write address reg in txdma address map
349 * located at address 0x1010
350 * Defined earlier (DMA10W_t)
351 */
352
353/*
354 * structure for txdma tx queue write address external reg in txdma address map
355 * located at address 0x1014
356 * Defined earlier (DMA10W_t)
357 */
358
359/*
360 * structure for txdma tx queue read address reg in txdma address map
361 * located at address 0x1018
362 * Defined earlier (DMA10W_t)
363 */
364
365/*
366 * structure for txdma status writeback address hi reg in txdma address map
367 * located at address 0x101C
368 * Defined earlier (u32)
369 */
370
371/*
372 * structure for txdma status writeback address lo reg in txdma address map
373 * located at address 0x1020
374 * Defined earlier (u32)
375 */
376
377/*
378 * structure for txdma service request reg in txdma address map
379 * located at address 0x1024
380 * Defined earlier (DMA10W_t)
381 */
382 336
383/* 337#define INDEX10(x) ((x) & ET_DMA10_MASK)
384 * structure for txdma service complete reg in txdma address map 338#define INDEX4(x) ((x) & ET_DMA4_MASK)
385 * located at address 0x1028
386 * Defined earlier (DMA10W_t)
387 */
388 339
389typedef union _DMA4W_t { 340extern inline void add_10bit(u32 *v, int n)
390 u32 value; 341{
391 struct { 342 *v = INDEX10(*v + n);
392#ifdef _BIT_FIELDS_HTOL 343}
393 u32 unused:27; /* bits 5-31 */
394 u32 wrap:1; /* bit 4 */
395 u32 val:4; /* bit 0-3 */
396#else
397 u32 val:4; /* bits 0-3 */
398 u32 wrap:1; /* bit 4 */
399 u32 unused:27; /* bits 5-31 */
400#endif
401 } bits;
402} DMA4W_t, *PDMA4W_t;
403 344
404/* 345/*
405 * structure for txdma tx descriptor cache read index reg in txdma address map 346 * 10bit DMA with wrap
406 * located at address 0x102C 347 * txdma tx queue write address reg in txdma address map at 0x1010
407 * Defined earlier (DMA4W_t) 348 * txdma tx queue write address external reg in txdma address map at 0x1014
408 */ 349 * txdma tx queue read address reg in txdma address map at 0x1018
409 350 *
410/* 351 * u32
411 * structure for txdma tx descriptor cache write index reg in txdma address map 352 * txdma status writeback address hi reg in txdma address map at0x101C
412 * located at address 0x1030 353 * txdma status writeback address lo reg in txdma address map at 0x1020
413 * Defined earlier (DMA4W_t) 354 *
355 * 10bit DMA with wrap
356 * txdma service request reg in txdma address map at 0x1024
357 * structure for txdma service complete reg in txdma address map at 0x1028
358 *
359 * 4bit DMA with wrap
360 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
361 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
362 *
363 * txdma error reg in txdma address map at address 0x1034
414 */ 364 */
415 365
416/*
417 * structure for txdma error reg in txdma address map
418 * located at address 0x1034
419 */
420typedef union _TXDMA_ERROR_t { 366typedef union _TXDMA_ERROR_t {
421 u32 value; 367 u32 value;
422 struct { 368 struct {
@@ -453,15 +399,15 @@ typedef struct _TXDMA_t { /* Location: */
453 u32 pr_base_hi; /* 0x1004 */ 399 u32 pr_base_hi; /* 0x1004 */
454 u32 pr_base_lo; /* 0x1008 */ 400 u32 pr_base_lo; /* 0x1008 */
455 TXDMA_PR_NUM_DES_t pr_num_des; /* 0x100C */ 401 TXDMA_PR_NUM_DES_t pr_num_des; /* 0x100C */
456 DMA10W_t txq_wr_addr; /* 0x1010 */ 402 u32 txq_wr_addr; /* 0x1010 */
457 DMA10W_t txq_wr_addr_ext; /* 0x1014 */ 403 u32 txq_wr_addr_ext; /* 0x1014 */
458 DMA10W_t txq_rd_addr; /* 0x1018 */ 404 u32 txq_rd_addr; /* 0x1018 */
459 u32 dma_wb_base_hi; /* 0x101C */ 405 u32 dma_wb_base_hi; /* 0x101C */
460 u32 dma_wb_base_lo; /* 0x1020 */ 406 u32 dma_wb_base_lo; /* 0x1020 */
461 DMA10W_t service_request; /* 0x1024 */ 407 u32 service_request; /* 0x1024 */
462 DMA10W_t service_complete; /* 0x1028 */ 408 u32 service_complete; /* 0x1028 */
463 DMA4W_t cache_rd_index; /* 0x102C */ 409 u32 cache_rd_index; /* 0x102C */
464 DMA4W_t cache_wr_index; /* 0x1030 */ 410 u32 cache_wr_index; /* 0x1030 */
465 TXDMA_ERROR_t TxDmaError; /* 0x1034 */ 411 TXDMA_ERROR_t TxDmaError; /* 0x1034 */
466 u32 DescAbortCount; /* 0x1038 */ 412 u32 DescAbortCount; /* 0x1038 */
467 u32 PayloadAbortCnt; /* 0x103c */ 413 u32 PayloadAbortCnt; /* 0x103c */
@@ -473,7 +419,7 @@ typedef struct _TXDMA_t { /* Location: */
473 u32 PayloadErrorCnt; /* 0x1054 */ 419 u32 PayloadErrorCnt; /* 0x1054 */
474 u32 WriteBackErrorCnt; /* 0x1058 */ 420 u32 WriteBackErrorCnt; /* 0x1058 */
475 u32 DroppedTLPCount; /* 0x105c */ 421 u32 DroppedTLPCount; /* 0x105c */
476 DMA10W_t NewServiceComplete; /* 0x1060 */ 422 u32 NewServiceComplete; /* 0x1060 */
477 u32 EthernetPacketCount; /* 0x1064 */ 423 u32 EthernetPacketCount; /* 0x1064 */
478} TXDMA_t, *PTXDMA_t; 424} TXDMA_t, *PTXDMA_t;
479 425
@@ -574,19 +520,19 @@ typedef union _RXDMA_MAX_PKT_TIME_t {
574/* 520/*
575 * structure for rx queue read address reg in rxdma address map 521 * structure for rx queue read address reg in rxdma address map
576 * located at address 0x2014 522 * located at address 0x2014
577 * Defined earlier (DMA10W_t) 523 * Defined earlier (u32)
578 */ 524 */
579 525
580/* 526/*
581 * structure for rx queue read address external reg in rxdma address map 527 * structure for rx queue read address external reg in rxdma address map
582 * located at address 0x2018 528 * located at address 0x2018
583 * Defined earlier (DMA10W_t) 529 * Defined earlier (u32)
584 */ 530 */
585 531
586/* 532/*
587 * structure for rx queue write address reg in rxdma address map 533 * structure for rx queue write address reg in rxdma address map
588 * located at address 0x201C 534 * located at address 0x201C
589 * Defined earlier (DMA10W_t) 535 * Defined earlier (u32)
590 */ 536 */
591 537
592/* 538/*
@@ -722,13 +668,13 @@ typedef union _RXDMA_FBR_NUM_DES_t {
722/* 668/*
723 * structure for free buffer ring 0 available offset reg in rxdma address map 669 * structure for free buffer ring 0 available offset reg in rxdma address map
724 * located at address 0x2048 670 * located at address 0x2048
725 * Defined earlier (DMA10W_t) 671 * Defined earlier (u32)
726 */ 672 */
727 673
728/* 674/*
729 * structure for free buffer ring 0 full offset reg in rxdma address map 675 * structure for free buffer ring 0 full offset reg in rxdma address map
730 * located at address 0x204C 676 * located at address 0x204C
731 * Defined earlier (DMA10W_t) 677 * Defined earlier (u32)
732 */ 678 */
733 679
734/* 680/*
@@ -811,9 +757,9 @@ typedef struct _RXDMA_t { /* Location: */
811 u32 dma_wb_base_hi; /* 0x2008 */ 757 u32 dma_wb_base_hi; /* 0x2008 */
812 RXDMA_NUM_PKT_DONE_t num_pkt_done; /* 0x200C */ 758 RXDMA_NUM_PKT_DONE_t num_pkt_done; /* 0x200C */
813 RXDMA_MAX_PKT_TIME_t max_pkt_time; /* 0x2010 */ 759 RXDMA_MAX_PKT_TIME_t max_pkt_time; /* 0x2010 */
814 DMA10W_t rxq_rd_addr; /* 0x2014 */ 760 u32 rxq_rd_addr; /* 0x2014 */
815 DMA10W_t rxq_rd_addr_ext; /* 0x2018 */ 761 u32 rxq_rd_addr_ext; /* 0x2018 */
816 DMA10W_t rxq_wr_addr; /* 0x201C */ 762 u32 rxq_wr_addr; /* 0x201C */
817 u32 psr_base_lo; /* 0x2020 */ 763 u32 psr_base_lo; /* 0x2020 */
818 u32 psr_base_hi; /* 0x2024 */ 764 u32 psr_base_hi; /* 0x2024 */
819 RXDMA_PSR_NUM_DES_t psr_num_des; /* 0x2028 */ 765 RXDMA_PSR_NUM_DES_t psr_num_des; /* 0x2028 */
@@ -824,15 +770,15 @@ typedef struct _RXDMA_t { /* Location: */
824 u32 fbr0_base_lo; /* 0x203C */ 770 u32 fbr0_base_lo; /* 0x203C */
825 u32 fbr0_base_hi; /* 0x2040 */ 771 u32 fbr0_base_hi; /* 0x2040 */
826 RXDMA_FBR_NUM_DES_t fbr0_num_des; /* 0x2044 */ 772 RXDMA_FBR_NUM_DES_t fbr0_num_des; /* 0x2044 */
827 DMA10W_t fbr0_avail_offset; /* 0x2048 */ 773 u32 fbr0_avail_offset; /* 0x2048 */
828 DMA10W_t fbr0_full_offset; /* 0x204C */ 774 u32 fbr0_full_offset; /* 0x204C */
829 RXDMA_FBC_RD_INDEX_t fbr0_rd_index; /* 0x2050 */ 775 RXDMA_FBC_RD_INDEX_t fbr0_rd_index; /* 0x2050 */
830 RXDMA_FBR_MIN_DES_t fbr0_min_des; /* 0x2054 */ 776 RXDMA_FBR_MIN_DES_t fbr0_min_des; /* 0x2054 */
831 u32 fbr1_base_lo; /* 0x2058 */ 777 u32 fbr1_base_lo; /* 0x2058 */
832 u32 fbr1_base_hi; /* 0x205C */ 778 u32 fbr1_base_hi; /* 0x205C */
833 RXDMA_FBR_NUM_DES_t fbr1_num_des; /* 0x2060 */ 779 RXDMA_FBR_NUM_DES_t fbr1_num_des; /* 0x2060 */
834 DMA10W_t fbr1_avail_offset; /* 0x2064 */ 780 u32 fbr1_avail_offset; /* 0x2064 */
835 DMA10W_t fbr1_full_offset; /* 0x2068 */ 781 u32 fbr1_full_offset; /* 0x2068 */
836 RXDMA_FBC_RD_INDEX_t fbr1_rd_index; /* 0x206C */ 782 RXDMA_FBC_RD_INDEX_t fbr1_rd_index; /* 0x206C */
837 RXDMA_FBR_MIN_DES_t fbr1_min_des; /* 0x2070 */ 783 RXDMA_FBR_MIN_DES_t fbr1_min_des; /* 0x2070 */
838} RXDMA_t, *PRXDMA_t; 784} RXDMA_t, *PRXDMA_t;
diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c
index 7f36de04703b..757a8cd45416 100644
--- a/drivers/staging/et131x/et1310_rx.c
+++ b/drivers/staging/et131x/et1310_rx.c
@@ -739,20 +739,12 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev)
739 writel((uint32_t) (pRxLocal->Fbr1Realpa >> 32), &rx_dma->fbr1_base_hi); 739 writel((uint32_t) (pRxLocal->Fbr1Realpa >> 32), &rx_dma->fbr1_base_hi);
740 writel((uint32_t) pRxLocal->Fbr1Realpa, &rx_dma->fbr1_base_lo); 740 writel((uint32_t) pRxLocal->Fbr1Realpa, &rx_dma->fbr1_base_lo);
741 writel(pRxLocal->Fbr1NumEntries - 1, &rx_dma->fbr1_num_des.value); 741 writel(pRxLocal->Fbr1NumEntries - 1, &rx_dma->fbr1_num_des.value);
742 742 writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
743 {
744 DMA10W_t fbr1_full = { 0 };
745
746 fbr1_full.bits.val = 0;
747 fbr1_full.bits.wrap = 1;
748 writel(fbr1_full.value, &rx_dma->fbr1_full_offset.value);
749 }
750 743
751 /* This variable tracks the free buffer ring 1 full position, so it 744 /* This variable tracks the free buffer ring 1 full position, so it
752 * has to match the above. 745 * has to match the above.
753 */ 746 */
754 pRxLocal->local_Fbr1_full.bits.val = 0; 747 pRxLocal->local_Fbr1_full = ET_DMA10_WRAP;
755 pRxLocal->local_Fbr1_full.bits.wrap = 1;
756 writel(((pRxLocal->Fbr1NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1, 748 writel(((pRxLocal->Fbr1NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
757 &rx_dma->fbr1_min_des.value); 749 &rx_dma->fbr1_min_des.value);
758 750
@@ -769,20 +761,12 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev)
769 writel((uint32_t) (pRxLocal->Fbr0Realpa >> 32), &rx_dma->fbr0_base_hi); 761 writel((uint32_t) (pRxLocal->Fbr0Realpa >> 32), &rx_dma->fbr0_base_hi);
770 writel((uint32_t) pRxLocal->Fbr0Realpa, &rx_dma->fbr0_base_lo); 762 writel((uint32_t) pRxLocal->Fbr0Realpa, &rx_dma->fbr0_base_lo);
771 writel(pRxLocal->Fbr0NumEntries - 1, &rx_dma->fbr0_num_des.value); 763 writel(pRxLocal->Fbr0NumEntries - 1, &rx_dma->fbr0_num_des.value);
772 764 writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
773 {
774 DMA10W_t fbr0_full = { 0 };
775
776 fbr0_full.bits.val = 0;
777 fbr0_full.bits.wrap = 1;
778 writel(fbr0_full.value, &rx_dma->fbr0_full_offset.value);
779 }
780 765
781 /* This variable tracks the free buffer ring 0 full position, so it 766 /* This variable tracks the free buffer ring 0 full position, so it
782 * has to match the above. 767 * has to match the above.
783 */ 768 */
784 pRxLocal->local_Fbr0_full.bits.val = 0; 769 pRxLocal->local_Fbr0_full = ET_DMA10_WRAP;
785 pRxLocal->local_Fbr0_full.bits.wrap = 1;
786 writel(((pRxLocal->Fbr0NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1, 770 writel(((pRxLocal->Fbr0NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
787 &rx_dma->fbr0_min_des.value); 771 &rx_dma->fbr0_min_des.value);
788#endif 772#endif
@@ -1282,6 +1266,16 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
1282 DBG_RX_LEAVE(et131x_dbginfo); 1266 DBG_RX_LEAVE(et131x_dbginfo);
1283} 1267}
1284 1268
1269static inline u32 bump_fbr(u32 *fbr, u32 limit)
1270{
1271 u32 v = *fbr;
1272 add_10bit(&v, 1);
1273 if (v > limit)
1274 v = (*fbr & ~ET_DMA10_MASK) ^ ET_DMA10_WRAP;
1275 *fbr = v;
1276 return v;
1277}
1278
1285/** 1279/**
1286 * NICReturnRFD - Recycle a RFD and put it back onto the receive list 1280 * NICReturnRFD - Recycle a RFD and put it back onto the receive list
1287 * @etdev: pointer to our adapter 1281 * @etdev: pointer to our adapter
@@ -1310,7 +1304,7 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd)
1310 if (ri == 1) { 1304 if (ri == 1) {
1311 PFBR_DESC_t pNextDesc = 1305 PFBR_DESC_t pNextDesc =
1312 (PFBR_DESC_t) (rx_local->pFbr1RingVa) + 1306 (PFBR_DESC_t) (rx_local->pFbr1RingVa) +
1313 rx_local->local_Fbr1_full.bits.val; 1307 INDEX10(rx_local->local_Fbr1_full);
1314 1308
1315 /* Handle the Free Buffer Ring advancement here. Write 1309 /* Handle the Free Buffer Ring advancement here. Write
1316 * the PA / Buffer Index for the returned buffer into 1310 * the PA / Buffer Index for the returned buffer into
@@ -1320,20 +1314,15 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd)
1320 pNextDesc->addr_lo = rx_local->Fbr[1]->PALow[bi]; 1314 pNextDesc->addr_lo = rx_local->Fbr[1]->PALow[bi];
1321 pNextDesc->word2.value = bi; 1315 pNextDesc->word2.value = bi;
1322 1316
1323 if (++rx_local->local_Fbr1_full.bits.val > 1317 writel(bump_fbr(&rx_local->local_Fbr1_full,
1324 (rx_local->Fbr1NumEntries - 1)) { 1318 rx_local->Fbr1NumEntries - 1),
1325 rx_local->local_Fbr1_full.bits.val = 0; 1319 &rx_dma->fbr1_full_offset);
1326 rx_local->local_Fbr1_full.bits.wrap ^= 1;
1327 }
1328
1329 writel(rx_local->local_Fbr1_full.value,
1330 &rx_dma->fbr1_full_offset.value);
1331 } 1320 }
1332#ifdef USE_FBR0 1321#ifdef USE_FBR0
1333 else { 1322 else {
1334 PFBR_DESC_t pNextDesc = 1323 PFBR_DESC_t pNextDesc =
1335 (PFBR_DESC_t) rx_local->pFbr0RingVa + 1324 (PFBR_DESC_t) rx_local->pFbr0RingVa +
1336 rx_local->local_Fbr0_full.bits.val; 1325 INDEX10(rx_local->local_Fbr0_full);
1337 1326
1338 /* Handle the Free Buffer Ring advancement here. Write 1327 /* Handle the Free Buffer Ring advancement here. Write
1339 * the PA / Buffer Index for the returned buffer into 1328 * the PA / Buffer Index for the returned buffer into
@@ -1343,14 +1332,9 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd)
1343 pNextDesc->addr_lo = rx_local->Fbr[0]->PALow[bi]; 1332 pNextDesc->addr_lo = rx_local->Fbr[0]->PALow[bi];
1344 pNextDesc->word2.value = bi; 1333 pNextDesc->word2.value = bi;
1345 1334
1346 if (++rx_local->local_Fbr0_full.bits.val > 1335 writel(bump_fbr(&rx_local->local_Fbr0_full,
1347 (rx_local->Fbr0NumEntries - 1)) { 1336 rx_local->Fbr0NumEntries - 1),
1348 rx_local->local_Fbr0_full.bits.val = 0; 1337 &rx_dma->fbr0_full_offset);
1349 rx_local->local_Fbr0_full.bits.wrap ^= 1;
1350 }
1351
1352 writel(rx_local->local_Fbr0_full.value,
1353 &rx_dma->fbr0_full_offset.value);
1354 } 1338 }
1355#endif 1339#endif
1356 spin_unlock_irqrestore(&etdev->FbrLock, flags); 1340 spin_unlock_irqrestore(&etdev->FbrLock, flags);
diff --git a/drivers/staging/et131x/et1310_rx.h b/drivers/staging/et131x/et1310_rx.h
index 3bfabd8f9671..72a522985270 100644
--- a/drivers/staging/et131x/et1310_rx.h
+++ b/drivers/staging/et131x/et1310_rx.h
@@ -302,7 +302,7 @@ typedef struct _rx_ring_t {
302 dma_addr_t Fbr0MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; 302 dma_addr_t Fbr0MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
303 uint64_t Fbr0Realpa; 303 uint64_t Fbr0Realpa;
304 uint64_t Fbr0offset; 304 uint64_t Fbr0offset;
305 DMA10W_t local_Fbr0_full; 305 u32 local_Fbr0_full;
306 u32 Fbr0NumEntries; 306 u32 Fbr0NumEntries;
307 u32 Fbr0BufferSize; 307 u32 Fbr0BufferSize;
308#endif 308#endif
@@ -313,7 +313,7 @@ typedef struct _rx_ring_t {
313 uint64_t Fbr1Realpa; 313 uint64_t Fbr1Realpa;
314 uint64_t Fbr1offset; 314 uint64_t Fbr1offset;
315 FBRLOOKUPTABLE *Fbr[2]; 315 FBRLOOKUPTABLE *Fbr[2];
316 DMA10W_t local_Fbr1_full; 316 u32 local_Fbr1_full;
317 u32 Fbr1NumEntries; 317 u32 Fbr1NumEntries;
318 u32 Fbr1BufferSize; 318 u32 Fbr1BufferSize;
319 319
diff --git a/drivers/staging/et131x/et1310_tx.c b/drivers/staging/et131x/et1310_tx.c
index 16aef44d9e0d..2782771ac49f 100644
--- a/drivers/staging/et131x/et1310_tx.c
+++ b/drivers/staging/et131x/et1310_tx.c
@@ -275,8 +275,8 @@ void ConfigTxDmaRegs(struct et131x_adapter *etdev)
275 275
276 memset(etdev->TxRing.pTxStatusVa, 0, sizeof(TX_STATUS_BLOCK_t)); 276 memset(etdev->TxRing.pTxStatusVa, 0, sizeof(TX_STATUS_BLOCK_t));
277 277
278 writel(0, &txdma->service_request.value); 278 writel(0, &txdma->service_request);
279 etdev->TxRing.txDmaReadyToSend.value = 0; 279 etdev->TxRing.txDmaReadyToSend = 0;
280 280
281 DBG_LEAVE(et131x_dbginfo); 281 DBG_LEAVE(et131x_dbginfo);
282} 282}
@@ -601,8 +601,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
601 "filling desc entry %d, " 601 "filling desc entry %d, "
602 "TCB: 0x%p\n", 602 "TCB: 0x%p\n",
603 (pPacket->len - pPacket->data_len), 603 (pPacket->len - pPacket->data_len),
604 etdev->TxRing.txDmaReadyToSend.bits. 604 etdev->TxRing.txDmaReadyToSend, pMpTcb);
605 val, pMpTcb);
606 605
607 CurDesc[FragmentNumber].DataBufferPtrHigh = 0; 606 CurDesc[FragmentNumber].DataBufferPtrHigh = 0;
608 607
@@ -630,8 +629,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
630 "filling desc entry %d, " 629 "filling desc entry %d, "
631 "TCB: 0x%p\n", 630 "TCB: 0x%p\n",
632 (pPacket->len - pPacket->data_len), 631 (pPacket->len - pPacket->data_len),
633 etdev->TxRing.txDmaReadyToSend.bits. 632 etdev->TxRing.txDmaReadyToSend, pMpTcb);
634 val, pMpTcb);
635 633
636 CurDesc[FragmentNumber].DataBufferPtrHigh = 0; 634 CurDesc[FragmentNumber].DataBufferPtrHigh = 0;
637 635
@@ -682,7 +680,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
682 "filling desc entry %d\n" 680 "filling desc entry %d\n"
683 "TCB: 0x%p\n", 681 "TCB: 0x%p\n",
684 pFragList[loopIndex].size, 682 pFragList[loopIndex].size,
685 etdev->TxRing.txDmaReadyToSend.bits.val, 683 etdev->TxRing.txDmaReadyToSend,
686 pMpTcb); 684 pMpTcb);
687 685
688 CurDesc[FragmentNumber].DataBufferPtrHigh = 0; 686 CurDesc[FragmentNumber].DataBufferPtrHigh = 0;
@@ -729,8 +727,8 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
729 727
730 spin_lock_irqsave(&etdev->SendHWLock, flags); 728 spin_lock_irqsave(&etdev->SendHWLock, flags);
731 729
732 thiscopy = 730 thiscopy = NUM_DESC_PER_RING_TX -
733 NUM_DESC_PER_RING_TX - etdev->TxRing.txDmaReadyToSend.bits.val; 731 INDEX10(etdev->TxRing.txDmaReadyToSend);
734 732
735 if (thiscopy >= FragmentNumber) { 733 if (thiscopy >= FragmentNumber) {
736 remainder = 0; 734 remainder = 0;
@@ -740,18 +738,15 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
740 } 738 }
741 739
742 memcpy(etdev->TxRing.pTxDescRingVa + 740 memcpy(etdev->TxRing.pTxDescRingVa +
743 etdev->TxRing.txDmaReadyToSend.bits.val, CurDesc, 741 INDEX10(etdev->TxRing.txDmaReadyToSend), CurDesc,
744 sizeof(TX_DESC_ENTRY_t) * thiscopy); 742 sizeof(TX_DESC_ENTRY_t) * thiscopy);
745 743
746 etdev->TxRing.txDmaReadyToSend.bits.val += thiscopy; 744 add_10bit(&etdev->TxRing.txDmaReadyToSend, thiscopy);
747 745
748 if ((etdev->TxRing.txDmaReadyToSend.bits.val == 0) || 746 if (INDEX10(etdev->TxRing.txDmaReadyToSend)== 0 ||
749 (etdev->TxRing.txDmaReadyToSend.bits.val == 747 INDEX10(etdev->TxRing.txDmaReadyToSend) == NUM_DESC_PER_RING_TX) {
750 NUM_DESC_PER_RING_TX)) { 748 etdev->TxRing.txDmaReadyToSend &= ~ET_DMA10_MASK;
751 if (etdev->TxRing.txDmaReadyToSend.bits.wrap) 749 etdev->TxRing.txDmaReadyToSend ^= ET_DMA10_WRAP;
752 etdev->TxRing.txDmaReadyToSend.value = 0;
753 else
754 etdev->TxRing.txDmaReadyToSend.value = 0x400;
755 } 750 }
756 751
757 if (remainder) { 752 if (remainder) {
@@ -759,18 +754,16 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
759 CurDesc + thiscopy, 754 CurDesc + thiscopy,
760 sizeof(TX_DESC_ENTRY_t) * remainder); 755 sizeof(TX_DESC_ENTRY_t) * remainder);
761 756
762 etdev->TxRing.txDmaReadyToSend.bits.val += remainder; 757 add_10bit(&etdev->TxRing.txDmaReadyToSend, remainder);
763 } 758 }
764 759
765 if (etdev->TxRing.txDmaReadyToSend.bits.val == 0) { 760 if (INDEX10(etdev->TxRing.txDmaReadyToSend) == 0) {
766 if (etdev->TxRing.txDmaReadyToSend.value) 761 if (etdev->TxRing.txDmaReadyToSend)
767 pMpTcb->WrIndex.value = NUM_DESC_PER_RING_TX - 1; 762 pMpTcb->WrIndex = NUM_DESC_PER_RING_TX - 1;
768 else 763 else
769 pMpTcb->WrIndex.value = 764 pMpTcb->WrIndex= ET_DMA10_WRAP | (NUM_DESC_PER_RING_TX - 1);
770 0x400 | (NUM_DESC_PER_RING_TX - 1);
771 } else 765 } else
772 pMpTcb->WrIndex.value = 766 pMpTcb->WrIndex = etdev->TxRing.txDmaReadyToSend - 1;
773 etdev->TxRing.txDmaReadyToSend.value - 1;
774 767
775 spin_lock(&etdev->TCBSendQLock); 768 spin_lock(&etdev->TCBSendQLock);
776 769
@@ -788,8 +781,8 @@ static int nic_send_packet(struct et131x_adapter *etdev, PMP_TCB pMpTcb)
788 spin_unlock(&etdev->TCBSendQLock); 781 spin_unlock(&etdev->TCBSendQLock);
789 782
790 /* Write the new write pointer back to the device. */ 783 /* Write the new write pointer back to the device. */
791 writel(etdev->TxRing.txDmaReadyToSend.value, 784 writel(etdev->TxRing.txDmaReadyToSend,
792 &etdev->regs->txdma.service_request.value); 785 &etdev->regs->txdma.service_request);
793 786
794 /* For Gig only, we use Tx Interrupt coalescing. Enable the software 787 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
795 * timer to wake us up if this packet isn't followed by N more. 788 * timer to wake us up if this packet isn't followed by N more.
@@ -1258,23 +1251,18 @@ inline void et131x_free_send_packet(struct et131x_adapter *etdev,
1258 "TCB : 0x%p\n" 1251 "TCB : 0x%p\n"
1259 "TCB Next : 0x%p\n" 1252 "TCB Next : 0x%p\n"
1260 "TCB PacketLength : %d\n" 1253 "TCB PacketLength : %d\n"
1261 "TCB WrIndex.value : 0x%08x\n" 1254 "TCB WrIndexS.value : 0x%08x\n"
1262 "TCB WrIndex.bits.val : %d\n" 1255 "TCB WrIndex.value : 0x%08x\n",
1263 "TCB WrIndex.value : 0x%08x\n"
1264 "TCB WrIndex.bits.val : %d\n",
1265 pMpTcb, 1256 pMpTcb,
1266 pMpTcb->Next, 1257 pMpTcb->Next,
1267 pMpTcb->PacketLength, 1258 pMpTcb->PacketLength,
1268 pMpTcb->WrIndexStart.value, 1259 pMpTcb->WrIndexStart,
1269 pMpTcb->WrIndexStart.bits.val, 1260 pMpTcb->WrIndex);
1270 pMpTcb->WrIndex.value,
1271 pMpTcb->WrIndex.bits.val);
1272 1261
1273 do { 1262 do {
1274 desc = 1263 desc =
1275 (TX_DESC_ENTRY_t *) (etdev->TxRing. 1264 (TX_DESC_ENTRY_t *) (etdev->TxRing.pTxDescRingVa +
1276 pTxDescRingVa + 1265 INDEX10(pMpTcb->WrIndexStart));
1277 pMpTcb->WrIndexStart.bits.val);
1278 1266
1279 DBG_TX(et131x_dbginfo, 1267 DBG_TX(et131x_dbginfo,
1280 "CURRENT DESCRIPTOR\n" 1268 "CURRENT DESCRIPTOR\n"
@@ -1293,15 +1281,14 @@ inline void et131x_free_send_packet(struct et131x_adapter *etdev,
1293 desc->DataBufferPtrLow, 1281 desc->DataBufferPtrLow,
1294 desc->word2.value, PCI_DMA_TODEVICE); 1282 desc->word2.value, PCI_DMA_TODEVICE);
1295 1283
1296 if (++pMpTcb->WrIndexStart.bits.val >= 1284 add_10bit(&pMpTcb->WrIndexStart, 1);
1285 if (INDEX10(pMpTcb->WrIndexStart) >=
1297 NUM_DESC_PER_RING_TX) { 1286 NUM_DESC_PER_RING_TX) {
1298 if (pMpTcb->WrIndexStart.bits.wrap) 1287 pMpTcb->WrIndexStart &= ~ET_DMA10_MASK;
1299 pMpTcb->WrIndexStart.value = 0; 1288 pMpTcb->WrIndexStart ^= ET_DMA10_WRAP;
1300 else
1301 pMpTcb->WrIndexStart.value = 0x400;
1302 } 1289 }
1303 } while (desc != (etdev->TxRing.pTxDescRingVa + 1290 } while (desc != (etdev->TxRing.pTxDescRingVa +
1304 pMpTcb->WrIndex.bits.val)); 1291 INDEX10(pMpTcb->WrIndex)));
1305 1292
1306 DBG_TX(et131x_dbginfo, 1293 DBG_TX(et131x_dbginfo,
1307 "Free Packet (SKB) : 0x%p\n", pMpTcb->Packet); 1294 "Free Packet (SKB) : 0x%p\n", pMpTcb->Packet);
@@ -1431,11 +1418,12 @@ void et131x_handle_send_interrupt(struct et131x_adapter *etdev)
1431static void et131x_update_tcb_list(struct et131x_adapter *etdev) 1418static void et131x_update_tcb_list(struct et131x_adapter *etdev)
1432{ 1419{
1433 unsigned long flags; 1420 unsigned long flags;
1434 DMA10W_t ServiceComplete; 1421 u32 ServiceComplete;
1435 PMP_TCB pMpTcb; 1422 PMP_TCB pMpTcb;
1423 u32 index;
1436 1424
1437 ServiceComplete.value = 1425 ServiceComplete = readl(&etdev->regs->txdma.NewServiceComplete);
1438 readl(&etdev->regs->txdma.NewServiceComplete.value); 1426 index = INDEX10(ServiceComplete);
1439 1427
1440 /* Has the ring wrapped? Process any descriptors that do not have 1428 /* Has the ring wrapped? Process any descriptors that do not have
1441 * the same "wrap" indicator as the current completion indicator 1429 * the same "wrap" indicator as the current completion indicator
@@ -1443,9 +1431,10 @@ static void et131x_update_tcb_list(struct et131x_adapter *etdev)
1443 spin_lock_irqsave(&etdev->TCBSendQLock, flags); 1431 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
1444 1432
1445 pMpTcb = etdev->TxRing.CurrSendHead; 1433 pMpTcb = etdev->TxRing.CurrSendHead;
1434
1446 while (pMpTcb && 1435 while (pMpTcb &&
1447 ServiceComplete.bits.wrap != pMpTcb->WrIndex.bits.wrap && 1436 ((ServiceComplete ^ pMpTcb->WrIndex) & ET_DMA10_WRAP) &&
1448 ServiceComplete.bits.val < pMpTcb->WrIndex.bits.val) { 1437 index < INDEX10(pMpTcb->WrIndex)) {
1449 etdev->TxRing.nBusySend--; 1438 etdev->TxRing.nBusySend--;
1450 etdev->TxRing.CurrSendHead = pMpTcb->Next; 1439 etdev->TxRing.CurrSendHead = pMpTcb->Next;
1451 if (pMpTcb->Next == NULL) 1440 if (pMpTcb->Next == NULL)
@@ -1459,8 +1448,8 @@ static void et131x_update_tcb_list(struct et131x_adapter *etdev)
1459 pMpTcb = etdev->TxRing.CurrSendHead; 1448 pMpTcb = etdev->TxRing.CurrSendHead;
1460 } 1449 }
1461 while (pMpTcb && 1450 while (pMpTcb &&
1462 ServiceComplete.bits.wrap == pMpTcb->WrIndex.bits.wrap && 1451 !((ServiceComplete ^ pMpTcb->WrIndex) & ET_DMA10_WRAP)
1463 ServiceComplete.bits.val > pMpTcb->WrIndex.bits.val) { 1452 && index > (pMpTcb->WrIndex & ET_DMA10_MASK)) {
1464 etdev->TxRing.nBusySend--; 1453 etdev->TxRing.nBusySend--;
1465 etdev->TxRing.CurrSendHead = pMpTcb->Next; 1454 etdev->TxRing.CurrSendHead = pMpTcb->Next;
1466 if (pMpTcb->Next == NULL) 1455 if (pMpTcb->Next == NULL)
diff --git a/drivers/staging/et131x/et1310_tx.h b/drivers/staging/et131x/et1310_tx.h
index 107292840556..ad0372121de0 100644
--- a/drivers/staging/et131x/et1310_tx.h
+++ b/drivers/staging/et131x/et1310_tx.h
@@ -166,8 +166,8 @@ typedef struct _MP_TCB {
166 u32 PacketStaleCount; 166 u32 PacketStaleCount;
167 struct sk_buff *Packet; 167 struct sk_buff *Packet;
168 u32 PacketLength; 168 u32 PacketLength;
169 DMA10W_t WrIndex; 169 u32 WrIndex;
170 DMA10W_t WrIndexStart; 170 u32 WrIndexStart;
171} MP_TCB, *PMP_TCB; 171} MP_TCB, *PMP_TCB;
172 172
173/* Structure to hold the skb's in a list */ 173/* Structure to hold the skb's in a list */
@@ -206,7 +206,7 @@ typedef struct _tx_ring_t {
206 uint64_t TxDescOffset; 206 uint64_t TxDescOffset;
207 207
208 /* ReadyToSend indicates where we last wrote to in the descriptor ring. */ 208 /* ReadyToSend indicates where we last wrote to in the descriptor ring. */
209 DMA10W_t txDmaReadyToSend; 209 u32 txDmaReadyToSend;
210 210
211 /* The location of the write-back status block */ 211 /* The location of the write-back status block */
212 PTX_STATUS_BLOCK_t pTxStatusVa; 212 PTX_STATUS_BLOCK_t pTxStatusVa;
diff --git a/drivers/staging/et131x/et131x_netdev.c b/drivers/staging/et131x/et131x_netdev.c
index fec3f8693656..62febe9f8e01 100644
--- a/drivers/staging/et131x/et131x_netdev.c
+++ b/drivers/staging/et131x/et131x_netdev.c
@@ -648,14 +648,14 @@ void et131x_tx_timeout(struct net_device *netdev)
648 *(etdev->TxRing.pTxStatusVa); 648 *(etdev->TxRing.pTxStatusVa);
649 PTX_DESC_ENTRY_t pDesc = 649 PTX_DESC_ENTRY_t pDesc =
650 etdev->TxRing.pTxDescRingVa + 650 etdev->TxRing.pTxDescRingVa +
651 pMpTcb->WrIndex.bits.val; 651 INDEX10(pMpTcb->WrIndex);
652#endif 652#endif
653 TX_DESC_ENTRY_t StuckDescriptors[10]; 653 TX_DESC_ENTRY_t StuckDescriptors[10];
654 654
655 if (pMpTcb->WrIndex.bits.val > 7) { 655 if (INDEX10(pMpTcb->WrIndex) > 7) {
656 memcpy(StuckDescriptors, 656 memcpy(StuckDescriptors,
657 etdev->TxRing.pTxDescRingVa + 657 etdev->TxRing.pTxDescRingVa +
658 pMpTcb->WrIndex.bits.val - 6, 658 INDEX10(pMpTcb->WrIndex) - 6,
659 sizeof(TX_DESC_ENTRY_t) * 10); 659 sizeof(TX_DESC_ENTRY_t) * 10);
660 } 660 }
661 661
@@ -664,7 +664,7 @@ void et131x_tx_timeout(struct net_device *netdev)
664 664
665 DBG_WARNING(et131x_dbginfo, 665 DBG_WARNING(et131x_dbginfo,
666 "Send stuck - reset. pMpTcb->WrIndex %x, Flags 0x%08x\n", 666 "Send stuck - reset. pMpTcb->WrIndex %x, Flags 0x%08x\n",
667 pMpTcb->WrIndex.bits.val, 667 pMpTcb->WrIndex,
668 pMpTcb->Flags); 668 pMpTcb->Flags);
669 669
670 DBG_WARNING(et131x_dbginfo, 670 DBG_WARNING(et131x_dbginfo,
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-02 20:59:36 -0500