aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorBryan Wu <bryan.wu@analog.com>2007-06-11 05:34:17 -0400
committerBryan Wu <bryan.wu@analog.com>2007-06-11 05:34:17 -0400
commitd6fe89b0630080e2bd6ece20ff7b1b5c2647ed62 (patch)
treeebccbeacb2e2fa2c5ee5319e60465cdcb7194999 /drivers
parent27bb9e79bcfedc1888d23c3c212c189fa8534fe7 (diff)
Blackfin SPI driver: fix bug SPI DMA incomplete transmission
SPI writes intermittently drop bytes at end of DMA transfer http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3205 http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=2892 Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/spi_bfin5xx.c15
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/spi/spi_bfin5xx.c b/drivers/spi/spi_bfin5xx.c
index a2d4884752ef..48587c27050d 100644
--- a/drivers/spi/spi_bfin5xx.c
+++ b/drivers/spi/spi_bfin5xx.c
@@ -582,14 +582,19 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
582 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n"); 582 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
583 clear_dma_irqstat(CH_SPI); 583 clear_dma_irqstat(CH_SPI);
584 584
585 /* Wait for DMA to complete */
586 while (get_dma_curr_irqstat(CH_SPI) & DMA_RUN)
587 continue;
588
585 /* 589 /*
586 * wait for the last transaction shifted out. yes, these two 590 * wait for the last transaction shifted out. HRM states:
587 * while loops are supposed to be the same (see the HRM). 591 * at this point there may still be data in the SPI DMA FIFO waiting
592 * to be transmitted ... software needs to poll TXS in the SPI_STAT
593 * register until it goes low for 2 successive reads
588 */ 594 */
589 if (drv_data->tx != NULL) { 595 if (drv_data->tx != NULL) {
590 while (bfin_read_SPI_STAT() & TXS) 596 while ((bfin_read_SPI_STAT() & TXS) ||
591 continue; 597 (bfin_read_SPI_STAT() & TXS))
592 while (bfin_read_SPI_STAT() & TXS)
593 continue; 598 continue;
594 } 599 }
595 600