diff options
author | Jeff Garzik <jeff@garzik.org> | 2007-02-25 02:53:41 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2007-02-26 05:42:31 -0500 |
commit | e728eabea110da90e69c05855e3a11174edb77ef (patch) | |
tree | db96a9c4cd1dcb9926a0b2ef8cfd78007610aedc /drivers | |
parent | 616ece2e7e5363574d172d64b19ffe9535606a1b (diff) |
[libata] sata_mv: don't touch reserved bits in EDMA config register
The code in mv_edma_cfg() reflected its 60xx origins, by doing things
[slightly] incorrectly on the older 50xx and newer 6042/7042 chips.
Clean up the EDMA configuration setup such that, each chip family
carefully initializes its own EDMA setup.
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/ata/sata_mv.c | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index d724bc799b1a..cc59aca12d42 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c | |||
@@ -814,23 +814,27 @@ static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio) | |||
814 | u32 cfg = readl(port_mmio + EDMA_CFG_OFS); | 814 | u32 cfg = readl(port_mmio + EDMA_CFG_OFS); |
815 | 815 | ||
816 | /* set up non-NCQ EDMA configuration */ | 816 | /* set up non-NCQ EDMA configuration */ |
817 | cfg &= ~0x1f; /* clear queue depth */ | ||
818 | cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */ | ||
819 | cfg &= ~(1 << 9); /* disable equeue */ | 817 | cfg &= ~(1 << 9); /* disable equeue */ |
820 | 818 | ||
821 | if (IS_GEN_I(hpriv)) | 819 | if (IS_GEN_I(hpriv)) { |
820 | cfg &= ~0x1f; /* clear queue depth */ | ||
822 | cfg |= (1 << 8); /* enab config burst size mask */ | 821 | cfg |= (1 << 8); /* enab config burst size mask */ |
822 | } | ||
823 | 823 | ||
824 | else if (IS_GEN_II(hpriv)) | 824 | else if (IS_GEN_II(hpriv)) { |
825 | cfg &= ~0x1f; /* clear queue depth */ | ||
825 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; | 826 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; |
827 | cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */ | ||
828 | } | ||
826 | 829 | ||
827 | else if (IS_GEN_IIE(hpriv)) { | 830 | else if (IS_GEN_IIE(hpriv)) { |
828 | cfg |= (1 << 23); /* dis RX PM port mask */ | 831 | cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ |
829 | cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */ | 832 | cfg |= (1 << 22); /* enab 4-entry host queue cache */ |
830 | cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */ | 833 | cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */ |
831 | cfg |= (1 << 18); /* enab early completion */ | 834 | cfg |= (1 << 18); /* enab early completion */ |
832 | cfg |= (1 << 17); /* enab host q cache */ | 835 | cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */ |
833 | cfg |= (1 << 22); /* enab cutthrough */ | 836 | cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */ |
837 | cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */ | ||
834 | } | 838 | } |
835 | 839 | ||
836 | writelfl(cfg, port_mmio + EDMA_CFG_OFS); | 840 | writelfl(cfg, port_mmio + EDMA_CFG_OFS); |