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authorraghavendra.koushik@neterion.com <raghavendra.koushik@neterion.com>2005-08-03 15:24:33 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-08-11 00:10:44 -0400
commit20346722ec474245446bcbf460594a935a5c0512 (patch)
treeab907a8c754fce58a97a0da9b4f19424c64eefde /drivers
parentcd04b947bc674f8fc9cac38ec30497bae5d664ad (diff)
[PATCH] S2io: Code cleanup
Hi, We are submitting a series of 13 patches to support our Xframe I and Xframe II line of products. The patches can be categorized as follows: Patches 1-8 : Changes applicable to both Xframe I and II Patches 9-11: Xframe II specific features Patch 12: Addresses issues found during testing cycle. Patch 13: Incorpoates mostly the review comments from community and some last moment bug fixes. Please review the patches and let us know your comments. Starting with patch 1 below. This patch involves cosmetic changes(tabs and indentation, regrouping of transmit and receive data structures, typecasting, code cleanup). Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com> Signed-off-by: Raghavendra Koushik <raghavendra.koushik@neterion.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/s2io-regs.h19
-rw-r--r--drivers/net/s2io.c1800
-rw-r--r--drivers/net/s2io.h286
3 files changed, 1003 insertions, 1102 deletions
diff --git a/drivers/net/s2io-regs.h b/drivers/net/s2io-regs.h
index 7092ca6b277e..8746740e6efd 100644
--- a/drivers/net/s2io-regs.h
+++ b/drivers/net/s2io-regs.h
@@ -77,19 +77,18 @@ typedef struct _XENA_dev_config {
77#define ADAPTER_ECC_EN BIT(55) 77#define ADAPTER_ECC_EN BIT(55)
78 78
79 u64 serr_source; 79 u64 serr_source;
80#define SERR_SOURCE_PIC BIT(0) 80#define SERR_SOURCE_PIC BIT(0)
81#define SERR_SOURCE_TXDMA BIT(1) 81#define SERR_SOURCE_TXDMA BIT(1)
82#define SERR_SOURCE_RXDMA BIT(2) 82#define SERR_SOURCE_RXDMA BIT(2)
83#define SERR_SOURCE_MAC BIT(3) 83#define SERR_SOURCE_MAC BIT(3)
84#define SERR_SOURCE_MC BIT(4) 84#define SERR_SOURCE_MC BIT(4)
85#define SERR_SOURCE_XGXS BIT(5) 85#define SERR_SOURCE_XGXS BIT(5)
86#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \ 86#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
87 SERR_SOURCE_TXDMA | \ 87 SERR_SOURCE_TXDMA | \
88 SERR_SOURCE_RXDMA | \ 88 SERR_SOURCE_RXDMA | \
89 SERR_SOURCE_MAC | \ 89 SERR_SOURCE_MAC | \
90 SERR_SOURCE_MC | \ 90 SERR_SOURCE_MC | \
91 SERR_SOURCE_XGXS) 91 SERR_SOURCE_XGXS)
92
93 92
94 u8 unused_0[0x800 - 0x120]; 93 u8 unused_0[0x800 - 0x120];
95 94
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index ea638b162d3f..0721e78dd8b0 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -11,29 +11,28 @@
11 * See the file COPYING in this distribution for more information. 11 * See the file COPYING in this distribution for more information.
12 * 12 *
13 * Credits: 13 * Credits:
14 * Jeff Garzik : For pointing out the improper error condition 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some 15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for 16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable 17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues. 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some 19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel. 20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were 21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments. 22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture 23 * Grant Grundler : For helping me get rid of some Architecture
24 * dependent code. 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver. 25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
26 * 26 *
27 * The module loadable parameters that are supported by the driver and a brief 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables. 28 * explaination of all the variables.
29 * rx_ring_num : This can be used to program the number of receive rings used 29 * rx_ring_num : This can be used to program the number of receive rings used
30 * in the driver. 30 * in the driver.
31 * rx_ring_len: This defines the number of descriptors each ring can have. This 31 * rx_ring_len: This defines the number of descriptors each ring can have. This
32 * is also an array of size 8. 32 * is also an array of size 8.
33 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver. 33 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
34 * tx_fifo_len: This too is an array of 8. Each element defines the number of 34 * tx_fifo_len: This too is an array of 8. Each element defines the number of
35 * Tx descriptors that can be associated with each corresponding FIFO. 35 * Tx descriptors that can be associated with each corresponding FIFO.
36 * in PCI Configuration space.
37 ************************************************************************/ 36 ************************************************************************/
38 37
39#include <linux/config.h> 38#include <linux/config.h>
@@ -57,19 +56,19 @@
57#include <linux/version.h> 56#include <linux/version.h>
58#include <linux/workqueue.h> 57#include <linux/workqueue.h>
59 58
60#include <asm/io.h>
61#include <asm/system.h> 59#include <asm/system.h>
62#include <asm/uaccess.h> 60#include <asm/uaccess.h>
61#include <asm/io.h>
63 62
64/* local include */ 63/* local include */
65#include "s2io.h" 64#include "s2io.h"
66#include "s2io-regs.h" 65#include "s2io-regs.h"
67 66
68/* S2io Driver name & version. */ 67/* S2io Driver name & version. */
69static char s2io_driver_name[] = "s2io"; 68static char s2io_driver_name[] = "Neterion";
70static char s2io_driver_version[] = "Version 1.7.7.1"; 69static char s2io_driver_version[] = "Version 1.7.7";
71 70
72/* 71/*
73 * Cards with following subsystem_id have a link state indication 72 * Cards with following subsystem_id have a link state indication
74 * problem, 600B, 600C, 600D, 640B, 640C and 640D. 73 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
75 * macro below identifies these cards given the subsystem_id. 74 * macro below identifies these cards given the subsystem_id.
@@ -86,9 +85,13 @@ static char s2io_driver_version[] = "Version 1.7.7.1";
86static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring) 85static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
87{ 86{
88 int level = 0; 87 int level = 0;
89 if ((sp->pkt_cnt[ring] - rxb_size) > 16) { 88 mac_info_t *mac_control;
89
90 mac_control = &sp->mac_control;
91 if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16) {
90 level = LOW; 92 level = LOW;
91 if ((sp->pkt_cnt[ring] - rxb_size) < MAX_RXDS_PER_BLOCK) { 93 if ((mac_control->rings[ring].pkt_cnt - rxb_size) <
94 MAX_RXDS_PER_BLOCK) {
92 level = PANIC; 95 level = PANIC;
93 } 96 }
94 } 97 }
@@ -153,8 +156,7 @@ static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
153#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN 156#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
154#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN 157#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
155 158
156 159/*
157/*
158 * Constants to be programmed into the Xena's registers, to configure 160 * Constants to be programmed into the Xena's registers, to configure
159 * the XAUI. 161 * the XAUI.
160 */ 162 */
@@ -196,8 +198,7 @@ static u64 default_dtx_cfg[] = {
196 END_SIGN 198 END_SIGN
197}; 199};
198 200
199 201/*
200/*
201 * Constants for Fixing the MacAddress problem seen mostly on 202 * Constants for Fixing the MacAddress problem seen mostly on
202 * Alpha machines. 203 * Alpha machines.
203 */ 204 */
@@ -227,6 +228,8 @@ static unsigned int rx_ring_num = 1;
227static unsigned int rx_ring_sz[MAX_RX_RINGS] = 228static unsigned int rx_ring_sz[MAX_RX_RINGS] =
228 {[0 ...(MAX_RX_RINGS - 1)] = 0 }; 229 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
229static unsigned int Stats_refresh_time = 4; 230static unsigned int Stats_refresh_time = 4;
231static unsigned int rts_frm_len[MAX_RX_RINGS] =
232 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
230static unsigned int rmac_pause_time = 65535; 233static unsigned int rmac_pause_time = 65535;
231static unsigned int mc_pause_threshold_q0q3 = 187; 234static unsigned int mc_pause_threshold_q0q3 = 187;
232static unsigned int mc_pause_threshold_q4q7 = 187; 235static unsigned int mc_pause_threshold_q4q7 = 187;
@@ -237,9 +240,9 @@ static unsigned int rmac_util_period = 5;
237static unsigned int indicate_max_pkts; 240static unsigned int indicate_max_pkts;
238#endif 241#endif
239 242
240/* 243/*
241 * S2IO device table. 244 * S2IO device table.
242 * This table lists all the devices that this driver supports. 245 * This table lists all the devices that this driver supports.
243 */ 246 */
244static struct pci_device_id s2io_tbl[] __devinitdata = { 247static struct pci_device_id s2io_tbl[] __devinitdata = {
245 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN, 248 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
@@ -247,9 +250,9 @@ static struct pci_device_id s2io_tbl[] __devinitdata = {
247 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI, 250 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
248 PCI_ANY_ID, PCI_ANY_ID}, 251 PCI_ANY_ID, PCI_ANY_ID},
249 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN, 252 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
250 PCI_ANY_ID, PCI_ANY_ID}, 253 PCI_ANY_ID, PCI_ANY_ID},
251 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI, 254 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
252 PCI_ANY_ID, PCI_ANY_ID}, 255 PCI_ANY_ID, PCI_ANY_ID},
253 {0,} 256 {0,}
254}; 257};
255 258
@@ -268,8 +271,8 @@ static struct pci_driver s2io_driver = {
268/** 271/**
269 * init_shared_mem - Allocation and Initialization of Memory 272 * init_shared_mem - Allocation and Initialization of Memory
270 * @nic: Device private variable. 273 * @nic: Device private variable.
271 * Description: The function allocates all the memory areas shared 274 * Description: The function allocates all the memory areas shared
272 * between the NIC and the driver. This includes Tx descriptors, 275 * between the NIC and the driver. This includes Tx descriptors,
273 * Rx descriptors and the statistics block. 276 * Rx descriptors and the statistics block.
274 */ 277 */
275 278
@@ -279,11 +282,11 @@ static int init_shared_mem(struct s2io_nic *nic)
279 void *tmp_v_addr, *tmp_v_addr_next; 282 void *tmp_v_addr, *tmp_v_addr_next;
280 dma_addr_t tmp_p_addr, tmp_p_addr_next; 283 dma_addr_t tmp_p_addr, tmp_p_addr_next;
281 RxD_block_t *pre_rxd_blk = NULL; 284 RxD_block_t *pre_rxd_blk = NULL;
282 int i, j, blk_cnt; 285 int i, j, blk_cnt, rx_sz, tx_sz;
283 int lst_size, lst_per_page; 286 int lst_size, lst_per_page;
284 struct net_device *dev = nic->dev; 287 struct net_device *dev = nic->dev;
285#ifdef CONFIG_2BUFF_MODE 288#ifdef CONFIG_2BUFF_MODE
286 unsigned long tmp; 289 u64 tmp;
287 buffAdd_t *ba; 290 buffAdd_t *ba;
288#endif 291#endif
289 292
@@ -308,28 +311,34 @@ static int init_shared_mem(struct s2io_nic *nic)
308 } 311 }
309 312
310 lst_size = (sizeof(TxD_t) * config->max_txds); 313 lst_size = (sizeof(TxD_t) * config->max_txds);
314 tx_sz = lst_size * size;
311 lst_per_page = PAGE_SIZE / lst_size; 315 lst_per_page = PAGE_SIZE / lst_size;
312 316
313 for (i = 0; i < config->tx_fifo_num; i++) { 317 for (i = 0; i < config->tx_fifo_num; i++) {
314 int fifo_len = config->tx_cfg[i].fifo_len; 318 int fifo_len = config->tx_cfg[i].fifo_len;
315 int list_holder_size = fifo_len * sizeof(list_info_hold_t); 319 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
316 nic->list_info[i] = kmalloc(list_holder_size, GFP_KERNEL); 320 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
317 if (!nic->list_info[i]) { 321 GFP_KERNEL);
322 if (!mac_control->fifos[i].list_info) {
318 DBG_PRINT(ERR_DBG, 323 DBG_PRINT(ERR_DBG,
319 "Malloc failed for list_info\n"); 324 "Malloc failed for list_info\n");
320 return -ENOMEM; 325 return -ENOMEM;
321 } 326 }
322 memset(nic->list_info[i], 0, list_holder_size); 327 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
323 } 328 }
324 for (i = 0; i < config->tx_fifo_num; i++) { 329 for (i = 0; i < config->tx_fifo_num; i++) {
325 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len, 330 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
326 lst_per_page); 331 lst_per_page);
327 mac_control->tx_curr_put_info[i].offset = 0; 332 mac_control->fifos[i].tx_curr_put_info.offset = 0;
328 mac_control->tx_curr_put_info[i].fifo_len = 333 mac_control->fifos[i].tx_curr_put_info.fifo_len =
329 config->tx_cfg[i].fifo_len - 1; 334 config->tx_cfg[i].fifo_len - 1;
330 mac_control->tx_curr_get_info[i].offset = 0; 335 mac_control->fifos[i].tx_curr_get_info.offset = 0;
331 mac_control->tx_curr_get_info[i].fifo_len = 336 mac_control->fifos[i].tx_curr_get_info.fifo_len =
332 config->tx_cfg[i].fifo_len - 1; 337 config->tx_cfg[i].fifo_len - 1;
338 mac_control->fifos[i].fifo_no = i;
339 mac_control->fifos[i].nic = nic;
340 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS;
341
333 for (j = 0; j < page_num; j++) { 342 for (j = 0; j < page_num; j++) {
334 int k = 0; 343 int k = 0;
335 dma_addr_t tmp_p; 344 dma_addr_t tmp_p;
@@ -345,16 +354,15 @@ static int init_shared_mem(struct s2io_nic *nic)
345 while (k < lst_per_page) { 354 while (k < lst_per_page) {
346 int l = (j * lst_per_page) + k; 355 int l = (j * lst_per_page) + k;
347 if (l == config->tx_cfg[i].fifo_len) 356 if (l == config->tx_cfg[i].fifo_len)
348 goto end_txd_alloc; 357 break;
349 nic->list_info[i][l].list_virt_addr = 358 mac_control->fifos[i].list_info[l].list_virt_addr =
350 tmp_v + (k * lst_size); 359 tmp_v + (k * lst_size);
351 nic->list_info[i][l].list_phy_addr = 360 mac_control->fifos[i].list_info[l].list_phy_addr =
352 tmp_p + (k * lst_size); 361 tmp_p + (k * lst_size);
353 k++; 362 k++;
354 } 363 }
355 } 364 }
356 } 365 }
357 end_txd_alloc:
358 366
359 /* Allocation and initialization of RXDs in Rings */ 367 /* Allocation and initialization of RXDs in Rings */
360 size = 0; 368 size = 0;
@@ -367,21 +375,26 @@ static int init_shared_mem(struct s2io_nic *nic)
367 return FAILURE; 375 return FAILURE;
368 } 376 }
369 size += config->rx_cfg[i].num_rxd; 377 size += config->rx_cfg[i].num_rxd;
370 nic->block_count[i] = 378 mac_control->rings[i].block_count =
371 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); 379 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
372 nic->pkt_cnt[i] = 380 mac_control->rings[i].pkt_cnt =
373 config->rx_cfg[i].num_rxd - nic->block_count[i]; 381 config->rx_cfg[i].num_rxd - mac_control->rings[i].block_count;
374 } 382 }
383 size = (size * (sizeof(RxD_t)));
384 rx_sz = size;
375 385
376 for (i = 0; i < config->rx_ring_num; i++) { 386 for (i = 0; i < config->rx_ring_num; i++) {
377 mac_control->rx_curr_get_info[i].block_index = 0; 387 mac_control->rings[i].rx_curr_get_info.block_index = 0;
378 mac_control->rx_curr_get_info[i].offset = 0; 388 mac_control->rings[i].rx_curr_get_info.offset = 0;
379 mac_control->rx_curr_get_info[i].ring_len = 389 mac_control->rings[i].rx_curr_get_info.ring_len =
380 config->rx_cfg[i].num_rxd - 1; 390 config->rx_cfg[i].num_rxd - 1;
381 mac_control->rx_curr_put_info[i].block_index = 0; 391 mac_control->rings[i].rx_curr_put_info.block_index = 0;
382 mac_control->rx_curr_put_info[i].offset = 0; 392 mac_control->rings[i].rx_curr_put_info.offset = 0;
383 mac_control->rx_curr_put_info[i].ring_len = 393 mac_control->rings[i].rx_curr_put_info.ring_len =
384 config->rx_cfg[i].num_rxd - 1; 394 config->rx_cfg[i].num_rxd - 1;
395 mac_control->rings[i].nic = nic;
396 mac_control->rings[i].ring_no = i;
397
385 blk_cnt = 398 blk_cnt =
386 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); 399 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
387 /* Allocating all the Rx blocks */ 400 /* Allocating all the Rx blocks */
@@ -395,32 +408,36 @@ static int init_shared_mem(struct s2io_nic *nic)
395 &tmp_p_addr); 408 &tmp_p_addr);
396 if (tmp_v_addr == NULL) { 409 if (tmp_v_addr == NULL) {
397 /* 410 /*
398 * In case of failure, free_shared_mem() 411 * In case of failure, free_shared_mem()
399 * is called, which should free any 412 * is called, which should free any
400 * memory that was alloced till the 413 * memory that was alloced till the
401 * failure happened. 414 * failure happened.
402 */ 415 */
403 nic->rx_blocks[i][j].block_virt_addr = 416 mac_control->rings[i].rx_blocks[j].block_virt_addr =
404 tmp_v_addr; 417 tmp_v_addr;
405 return -ENOMEM; 418 return -ENOMEM;
406 } 419 }
407 memset(tmp_v_addr, 0, size); 420 memset(tmp_v_addr, 0, size);
408 nic->rx_blocks[i][j].block_virt_addr = tmp_v_addr; 421 mac_control->rings[i].rx_blocks[j].block_virt_addr =
409 nic->rx_blocks[i][j].block_dma_addr = tmp_p_addr; 422 tmp_v_addr;
423 mac_control->rings[i].rx_blocks[j].block_dma_addr =
424 tmp_p_addr;
410 } 425 }
411 /* Interlinking all Rx Blocks */ 426 /* Interlinking all Rx Blocks */
412 for (j = 0; j < blk_cnt; j++) { 427 for (j = 0; j < blk_cnt; j++) {
413 tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr; 428 tmp_v_addr =
429 mac_control->rings[i].rx_blocks[j].block_virt_addr;
414 tmp_v_addr_next = 430 tmp_v_addr_next =
415 nic->rx_blocks[i][(j + 1) % 431 mac_control->rings[i].rx_blocks[(j + 1) %
416 blk_cnt].block_virt_addr; 432 blk_cnt].block_virt_addr;
417 tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr; 433 tmp_p_addr =
434 mac_control->rings[i].rx_blocks[j].block_dma_addr;
418 tmp_p_addr_next = 435 tmp_p_addr_next =
419 nic->rx_blocks[i][(j + 1) % 436 mac_control->rings[i].rx_blocks[(j + 1) %
420 blk_cnt].block_dma_addr; 437 blk_cnt].block_dma_addr;
421 438
422 pre_rxd_blk = (RxD_block_t *) tmp_v_addr; 439 pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
423 pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD 440 pre_rxd_blk->reserved_1 = END_OF_BLOCK; /* last RxD
424 * marker. 441 * marker.
425 */ 442 */
426#ifndef CONFIG_2BUFF_MODE 443#ifndef CONFIG_2BUFF_MODE
@@ -433,43 +450,43 @@ static int init_shared_mem(struct s2io_nic *nic)
433 } 450 }
434 451
435#ifdef CONFIG_2BUFF_MODE 452#ifdef CONFIG_2BUFF_MODE
436 /* 453 /*
437 * Allocation of Storages for buffer addresses in 2BUFF mode 454 * Allocation of Storages for buffer addresses in 2BUFF mode
438 * and the buffers as well. 455 * and the buffers as well.
439 */ 456 */
440 for (i = 0; i < config->rx_ring_num; i++) { 457 for (i = 0; i < config->rx_ring_num; i++) {
441 blk_cnt = 458 blk_cnt =
442 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); 459 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
443 nic->ba[i] = kmalloc((sizeof(buffAdd_t *) * blk_cnt), 460 mac_control->rings[i].ba = kmalloc((sizeof(buffAdd_t *) * blk_cnt),
444 GFP_KERNEL); 461 GFP_KERNEL);
445 if (!nic->ba[i]) 462 if (!mac_control->rings[i].ba)
446 return -ENOMEM; 463 return -ENOMEM;
447 for (j = 0; j < blk_cnt; j++) { 464 for (j = 0; j < blk_cnt; j++) {
448 int k = 0; 465 int k = 0;
449 nic->ba[i][j] = kmalloc((sizeof(buffAdd_t) * 466 mac_control->rings[i].ba[j] = kmalloc((sizeof(buffAdd_t) *
450 (MAX_RXDS_PER_BLOCK + 1)), 467 (MAX_RXDS_PER_BLOCK + 1)),
451 GFP_KERNEL); 468 GFP_KERNEL);
452 if (!nic->ba[i][j]) 469 if (!mac_control->rings[i].ba[j])
453 return -ENOMEM; 470 return -ENOMEM;
454 while (k != MAX_RXDS_PER_BLOCK) { 471 while (k != MAX_RXDS_PER_BLOCK) {
455 ba = &nic->ba[i][j][k]; 472 ba = &mac_control->rings[i].ba[j][k];
456 473
457 ba->ba_0_org = kmalloc 474 ba->ba_0_org = (void *) kmalloc
458 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL); 475 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
459 if (!ba->ba_0_org) 476 if (!ba->ba_0_org)
460 return -ENOMEM; 477 return -ENOMEM;
461 tmp = (unsigned long) ba->ba_0_org; 478 tmp = (u64) ba->ba_0_org;
462 tmp += ALIGN_SIZE; 479 tmp += ALIGN_SIZE;
463 tmp &= ~((unsigned long) ALIGN_SIZE); 480 tmp &= ~((u64) ALIGN_SIZE);
464 ba->ba_0 = (void *) tmp; 481 ba->ba_0 = (void *) tmp;
465 482
466 ba->ba_1_org = kmalloc 483 ba->ba_1_org = (void *) kmalloc
467 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL); 484 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
468 if (!ba->ba_1_org) 485 if (!ba->ba_1_org)
469 return -ENOMEM; 486 return -ENOMEM;
470 tmp = (unsigned long) ba->ba_1_org; 487 tmp = (u64) ba->ba_1_org;
471 tmp += ALIGN_SIZE; 488 tmp += ALIGN_SIZE;
472 tmp &= ~((unsigned long) ALIGN_SIZE); 489 tmp &= ~((u64) ALIGN_SIZE);
473 ba->ba_1 = (void *) tmp; 490 ba->ba_1 = (void *) tmp;
474 k++; 491 k++;
475 } 492 }
@@ -483,9 +500,9 @@ static int init_shared_mem(struct s2io_nic *nic)
483 (nic->pdev, size, &mac_control->stats_mem_phy); 500 (nic->pdev, size, &mac_control->stats_mem_phy);
484 501
485 if (!mac_control->stats_mem) { 502 if (!mac_control->stats_mem) {
486 /* 503 /*
487 * In case of failure, free_shared_mem() is called, which 504 * In case of failure, free_shared_mem() is called, which
488 * should free any memory that was alloced till the 505 * should free any memory that was alloced till the
489 * failure happened. 506 * failure happened.
490 */ 507 */
491 return -ENOMEM; 508 return -ENOMEM;
@@ -495,15 +512,14 @@ static int init_shared_mem(struct s2io_nic *nic)
495 tmp_v_addr = mac_control->stats_mem; 512 tmp_v_addr = mac_control->stats_mem;
496 mac_control->stats_info = (StatInfo_t *) tmp_v_addr; 513 mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
497 memset(tmp_v_addr, 0, size); 514 memset(tmp_v_addr, 0, size);
498
499 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name, 515 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
500 (unsigned long long) tmp_p_addr); 516 (unsigned long long) tmp_p_addr);
501 517
502 return SUCCESS; 518 return SUCCESS;
503} 519}
504 520
505/** 521/**
506 * free_shared_mem - Free the allocated Memory 522 * free_shared_mem - Free the allocated Memory
507 * @nic: Device private variable. 523 * @nic: Device private variable.
508 * Description: This function is to free all memory locations allocated by 524 * Description: This function is to free all memory locations allocated by
509 * the init_shared_mem() function and return it to the kernel. 525 * the init_shared_mem() function and return it to the kernel.
@@ -533,15 +549,18 @@ static void free_shared_mem(struct s2io_nic *nic)
533 lst_per_page); 549 lst_per_page);
534 for (j = 0; j < page_num; j++) { 550 for (j = 0; j < page_num; j++) {
535 int mem_blks = (j * lst_per_page); 551 int mem_blks = (j * lst_per_page);
536 if (!nic->list_info[i][mem_blks].list_virt_addr) 552 if (!mac_control->fifos[i].list_info[mem_blks].
553 list_virt_addr)
537 break; 554 break;
538 pci_free_consistent(nic->pdev, PAGE_SIZE, 555 pci_free_consistent(nic->pdev, PAGE_SIZE,
539 nic->list_info[i][mem_blks]. 556 mac_control->fifos[i].
557 list_info[mem_blks].
540 list_virt_addr, 558 list_virt_addr,
541 nic->list_info[i][mem_blks]. 559 mac_control->fifos[i].
560 list_info[mem_blks].
542 list_phy_addr); 561 list_phy_addr);
543 } 562 }
544 kfree(nic->list_info[i]); 563 kfree(mac_control->fifos[i].list_info);
545 } 564 }
546 565
547#ifndef CONFIG_2BUFF_MODE 566#ifndef CONFIG_2BUFF_MODE
@@ -550,10 +569,12 @@ static void free_shared_mem(struct s2io_nic *nic)
550 size = SIZE_OF_BLOCK; 569 size = SIZE_OF_BLOCK;
551#endif 570#endif
552 for (i = 0; i < config->rx_ring_num; i++) { 571 for (i = 0; i < config->rx_ring_num; i++) {
553 blk_cnt = nic->block_count[i]; 572 blk_cnt = mac_control->rings[i].block_count;
554 for (j = 0; j < blk_cnt; j++) { 573 for (j = 0; j < blk_cnt; j++) {
555 tmp_v_addr = nic->rx_blocks[i][j].block_virt_addr; 574 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
556 tmp_p_addr = nic->rx_blocks[i][j].block_dma_addr; 575 block_virt_addr;
576 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
577 block_dma_addr;
557 if (tmp_v_addr == NULL) 578 if (tmp_v_addr == NULL)
558 break; 579 break;
559 pci_free_consistent(nic->pdev, size, 580 pci_free_consistent(nic->pdev, size,
@@ -566,35 +587,21 @@ static void free_shared_mem(struct s2io_nic *nic)
566 for (i = 0; i < config->rx_ring_num; i++) { 587 for (i = 0; i < config->rx_ring_num; i++) {
567 blk_cnt = 588 blk_cnt =
568 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1); 589 config->rx_cfg[i].num_rxd / (MAX_RXDS_PER_BLOCK + 1);
569 if (!nic->ba[i])
570 goto end_free;
571 for (j = 0; j < blk_cnt; j++) { 590 for (j = 0; j < blk_cnt; j++) {
572 int k = 0; 591 int k = 0;
573 if (!nic->ba[i][j]) { 592 if (!mac_control->rings[i].ba[j])
574 kfree(nic->ba[i]); 593 continue;
575 goto end_free;
576 }
577 while (k != MAX_RXDS_PER_BLOCK) { 594 while (k != MAX_RXDS_PER_BLOCK) {
578 buffAdd_t *ba = &nic->ba[i][j][k]; 595 buffAdd_t *ba = &mac_control->rings[i].ba[j][k];
579 if (!ba || !ba->ba_0_org || !ba->ba_1_org)
580 {
581 kfree(nic->ba[i]);
582 kfree(nic->ba[i][j]);
583 if(ba->ba_0_org)
584 kfree(ba->ba_0_org);
585 if(ba->ba_1_org)
586 kfree(ba->ba_1_org);
587 goto end_free;
588 }
589 kfree(ba->ba_0_org); 596 kfree(ba->ba_0_org);
590 kfree(ba->ba_1_org); 597 kfree(ba->ba_1_org);
591 k++; 598 k++;
592 } 599 }
593 kfree(nic->ba[i][j]); 600 kfree(mac_control->rings[i].ba[j]);
594 } 601 }
595 kfree(nic->ba[i]); 602 if (mac_control->rings[i].ba)
603 kfree(mac_control->rings[i].ba);
596 } 604 }
597end_free:
598#endif 605#endif
599 606
600 if (mac_control->stats_mem) { 607 if (mac_control->stats_mem) {
@@ -605,12 +612,12 @@ end_free:
605 } 612 }
606} 613}
607 614
608/** 615/**
609 * init_nic - Initialization of hardware 616 * init_nic - Initialization of hardware
610 * @nic: device peivate variable 617 * @nic: device peivate variable
611 * Description: The function sequentially configures every block 618 * Description: The function sequentially configures every block
612 * of the H/W from their reset values. 619 * of the H/W from their reset values.
613 * Return Value: SUCCESS on success and 620 * Return Value: SUCCESS on success and
614 * '-1' on failure (endian settings incorrect). 621 * '-1' on failure (endian settings incorrect).
615 */ 622 */
616 623
@@ -626,12 +633,13 @@ static int init_nic(struct s2io_nic *nic)
626 struct config_param *config; 633 struct config_param *config;
627 int mdio_cnt = 0, dtx_cnt = 0; 634 int mdio_cnt = 0, dtx_cnt = 0;
628 unsigned long long mem_share; 635 unsigned long long mem_share;
636 int mem_size;
629 637
630 mac_control = &nic->mac_control; 638 mac_control = &nic->mac_control;
631 config = &nic->config; 639 config = &nic->config;
632 640
633 /* Initialize swapper control register */ 641 /* to set the swapper control on the card */
634 if (s2io_set_swapper(nic)) { 642 if(s2io_set_swapper(nic)) {
635 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n"); 643 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
636 return -1; 644 return -1;
637 } 645 }
@@ -639,8 +647,8 @@ static int init_nic(struct s2io_nic *nic)
639 /* Remove XGXS from reset state */ 647 /* Remove XGXS from reset state */
640 val64 = 0; 648 val64 = 0;
641 writeq(val64, &bar0->sw_reset); 649 writeq(val64, &bar0->sw_reset);
642 val64 = readq(&bar0->sw_reset);
643 msleep(500); 650 msleep(500);
651 val64 = readq(&bar0->sw_reset);
644 652
645 /* Enable Receiving broadcasts */ 653 /* Enable Receiving broadcasts */
646 add = &bar0->mac_cfg; 654 add = &bar0->mac_cfg;
@@ -660,18 +668,18 @@ static int init_nic(struct s2io_nic *nic)
660 val64 = dev->mtu; 668 val64 = dev->mtu;
661 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); 669 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
662 670
663 /* 671 /*
664 * Configuring the XAUI Interface of Xena. 672 * Configuring the XAUI Interface of Xena.
665 * *************************************** 673 * ***************************************
666 * To Configure the Xena's XAUI, one has to write a series 674 * To Configure the Xena's XAUI, one has to write a series
667 * of 64 bit values into two registers in a particular 675 * of 64 bit values into two registers in a particular
668 * sequence. Hence a macro 'SWITCH_SIGN' has been defined 676 * sequence. Hence a macro 'SWITCH_SIGN' has been defined
669 * which will be defined in the array of configuration values 677 * which will be defined in the array of configuration values
670 * (default_dtx_cfg & default_mdio_cfg) at appropriate places 678 * (default_dtx_cfg & default_mdio_cfg) at appropriate places
671 * to switch writing from one regsiter to another. We continue 679 * to switch writing from one regsiter to another. We continue
672 * writing these values until we encounter the 'END_SIGN' macro. 680 * writing these values until we encounter the 'END_SIGN' macro.
673 * For example, After making a series of 21 writes into 681 * For example, After making a series of 21 writes into
674 * dtx_control register the 'SWITCH_SIGN' appears and hence we 682 * dtx_control register the 'SWITCH_SIGN' appears and hence we
675 * start writing into mdio_control until we encounter END_SIGN. 683 * start writing into mdio_control until we encounter END_SIGN.
676 */ 684 */
677 while (1) { 685 while (1) {
@@ -752,8 +760,8 @@ static int init_nic(struct s2io_nic *nic)
752 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n", 760 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
753 &bar0->tx_fifo_partition_0, (unsigned long long) val64); 761 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
754 762
755 /* 763 /*
756 * Initialization of Tx_PA_CONFIG register to ignore packet 764 * Initialization of Tx_PA_CONFIG register to ignore packet
757 * integrity checking. 765 * integrity checking.
758 */ 766 */
759 val64 = readq(&bar0->tx_pa_cfg); 767 val64 = readq(&bar0->tx_pa_cfg);
@@ -770,54 +778,54 @@ static int init_nic(struct s2io_nic *nic)
770 } 778 }
771 writeq(val64, &bar0->rx_queue_priority); 779 writeq(val64, &bar0->rx_queue_priority);
772 780
773 /* 781 /*
774 * Allocating equal share of memory to all the 782 * Allocating equal share of memory to all the
775 * configured Rings. 783 * configured Rings.
776 */ 784 */
777 val64 = 0; 785 val64 = 0;
786 mem_size = 64;
778 for (i = 0; i < config->rx_ring_num; i++) { 787 for (i = 0; i < config->rx_ring_num; i++) {
779 switch (i) { 788 switch (i) {
780 case 0: 789 case 0:
781 mem_share = (64 / config->rx_ring_num + 790 mem_share = (mem_size / config->rx_ring_num +
782 64 % config->rx_ring_num); 791 mem_size % config->rx_ring_num);
783 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share); 792 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
784 continue; 793 continue;
785 case 1: 794 case 1:
786 mem_share = (64 / config->rx_ring_num); 795 mem_share = (mem_size / config->rx_ring_num);
787 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share); 796 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
788 continue; 797 continue;
789 case 2: 798 case 2:
790 mem_share = (64 / config->rx_ring_num); 799 mem_share = (mem_size / config->rx_ring_num);
791 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share); 800 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
792 continue; 801 continue;
793 case 3: 802 case 3:
794 mem_share = (64 / config->rx_ring_num); 803 mem_share = (mem_size / config->rx_ring_num);
795 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share); 804 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
796 continue; 805 continue;
797 case 4: 806 case 4:
798 mem_share = (64 / config->rx_ring_num); 807 mem_share = (mem_size / config->rx_ring_num);
799 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share); 808 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
800 continue; 809 continue;
801 case 5: 810 case 5:
802 mem_share = (64 / config->rx_ring_num); 811 mem_share = (mem_size / config->rx_ring_num);
803 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share); 812 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
804 continue; 813 continue;
805 case 6: 814 case 6:
806 mem_share = (64 / config->rx_ring_num); 815 mem_share = (mem_size / config->rx_ring_num);
807 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share); 816 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
808 continue; 817 continue;
809 case 7: 818 case 7:
810 mem_share = (64 / config->rx_ring_num); 819 mem_share = (mem_size / config->rx_ring_num);
811 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share); 820 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
812 continue; 821 continue;
813 } 822 }
814 } 823 }
815 writeq(val64, &bar0->rx_queue_cfg); 824 writeq(val64, &bar0->rx_queue_cfg);
816 825
817 /* 826 /* Initializing the Tx round robin registers to 0
818 * Initializing the Tx round robin registers to 0. 827 * filling tx and rx round robin registers as per
819 * Filling Tx and Rx round robin registers as per the 828 * the number of FIFOs and Rings is still TODO
820 * number of FIFOs and Rings is still TODO.
821 */ 829 */
822 writeq(0, &bar0->tx_w_round_robin_0); 830 writeq(0, &bar0->tx_w_round_robin_0);
823 writeq(0, &bar0->tx_w_round_robin_1); 831 writeq(0, &bar0->tx_w_round_robin_1);
@@ -825,30 +833,30 @@ static int init_nic(struct s2io_nic *nic)
825 writeq(0, &bar0->tx_w_round_robin_3); 833 writeq(0, &bar0->tx_w_round_robin_3);
826 writeq(0, &bar0->tx_w_round_robin_4); 834 writeq(0, &bar0->tx_w_round_robin_4);
827 835
828 /* 836 /*
829 * TODO 837 * TODO
830 * Disable Rx steering. Hard coding all packets be steered to 838 * Disable Rx steering. Hard coding all packets to be steered to
831 * Queue 0 for now. 839 * Queue 0 for now.
832 */ 840 */
833 val64 = 0x8080808080808080ULL; 841 val64 = 0x8080808080808080ULL;
834 writeq(val64, &bar0->rts_qos_steering); 842 writeq(val64, &bar0->rts_qos_steering);
835 843
836 /* UDP Fix */ 844 /* UDP Fix */
837 val64 = 0; 845 val64 = 0;
838 for (i = 1; i < 8; i++) 846 for (i = 0; i < 8; i++)
839 writeq(val64, &bar0->rts_frm_len_n[i]); 847 writeq(val64, &bar0->rts_frm_len_n[i]);
840 848
841 /* Set rts_frm_len register for fifo 0 */ 849 /* Set the default rts frame length for ring0 */
842 writeq(MAC_RTS_FRM_LEN_SET(dev->mtu + 22), 850 writeq(MAC_RTS_FRM_LEN_SET(dev->mtu+22),
843 &bar0->rts_frm_len_n[0]); 851 &bar0->rts_frm_len_n[0]);
844 852
845 /* Enable statistics */ 853 /* Program statistics memory */
846 writeq(mac_control->stats_mem_phy, &bar0->stat_addr); 854 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
847 val64 = SET_UPDT_PERIOD(Stats_refresh_time) | 855 val64 = SET_UPDT_PERIOD(Stats_refresh_time) |
848 STAT_CFG_STAT_RO | STAT_CFG_STAT_EN; 856 STAT_CFG_STAT_RO | STAT_CFG_STAT_EN;
849 writeq(val64, &bar0->stat_cfg); 857 writeq(val64, &bar0->stat_cfg);
850 858
851 /* 859 /*
852 * Initializing the sampling rate for the device to calculate the 860 * Initializing the sampling rate for the device to calculate the
853 * bandwidth utilization. 861 * bandwidth utilization.
854 */ 862 */
@@ -857,11 +865,12 @@ static int init_nic(struct s2io_nic *nic)
857 writeq(val64, &bar0->mac_link_util); 865 writeq(val64, &bar0->mac_link_util);
858 866
859 867
860 /* 868 /*
861 * Initializing the Transmit and Receive Traffic Interrupt 869 * Initializing the Transmit and Receive Traffic Interrupt
862 * Scheme. 870 * Scheme.
863 */ 871 */
864 /* TTI Initialization. Default Tx timer gets us about 872 /*
873 * TTI Initialization. Default Tx timer gets us about
865 * 250 interrupts per sec. Continuous interrupts are enabled 874 * 250 interrupts per sec. Continuous interrupts are enabled
866 * by default. 875 * by default.
867 */ 876 */
@@ -880,7 +889,7 @@ static int init_nic(struct s2io_nic *nic)
880 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD; 889 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
881 writeq(val64, &bar0->tti_command_mem); 890 writeq(val64, &bar0->tti_command_mem);
882 891
883 /* 892 /*
884 * Once the operation completes, the Strobe bit of the command 893 * Once the operation completes, the Strobe bit of the command
885 * register will be reset. We poll for this particular condition 894 * register will be reset. We poll for this particular condition
886 * We wait for a maximum of 500ms for the operation to complete, 895 * We wait for a maximum of 500ms for the operation to complete,
@@ -917,7 +926,7 @@ static int init_nic(struct s2io_nic *nic)
917 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD; 926 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD;
918 writeq(val64, &bar0->rti_command_mem); 927 writeq(val64, &bar0->rti_command_mem);
919 928
920 /* 929 /*
921 * Once the operation completes, the Strobe bit of the command 930 * Once the operation completes, the Strobe bit of the command
922 * register will be reset. We poll for this particular condition 931 * register will be reset. We poll for this particular condition
923 * We wait for a maximum of 500ms for the operation to complete, 932 * We wait for a maximum of 500ms for the operation to complete,
@@ -926,7 +935,7 @@ static int init_nic(struct s2io_nic *nic)
926 time = 0; 935 time = 0;
927 while (TRUE) { 936 while (TRUE) {
928 val64 = readq(&bar0->rti_command_mem); 937 val64 = readq(&bar0->rti_command_mem);
929 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) { 938 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
930 break; 939 break;
931 } 940 }
932 if (time > 10) { 941 if (time > 10) {
@@ -938,15 +947,15 @@ static int init_nic(struct s2io_nic *nic)
938 msleep(50); 947 msleep(50);
939 } 948 }
940 949
941 /* 950 /*
942 * Initializing proper values as Pause threshold into all 951 * Initializing proper values as Pause threshold into all
943 * the 8 Queues on Rx side. 952 * the 8 Queues on Rx side.
944 */ 953 */
945 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3); 954 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
946 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7); 955 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
947 956
948 /* Disable RMAC PAD STRIPPING */ 957 /* Disable RMAC PAD STRIPPING */
949 add = &bar0->mac_cfg; 958 add = (void *) &bar0->mac_cfg;
950 val64 = readq(&bar0->mac_cfg); 959 val64 = readq(&bar0->mac_cfg);
951 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD); 960 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
952 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); 961 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
@@ -955,8 +964,8 @@ static int init_nic(struct s2io_nic *nic)
955 writel((u32) (val64 >> 32), (add + 4)); 964 writel((u32) (val64 >> 32), (add + 4));
956 val64 = readq(&bar0->mac_cfg); 965 val64 = readq(&bar0->mac_cfg);
957 966
958 /* 967 /*
959 * Set the time value to be inserted in the pause frame 968 * Set the time value to be inserted in the pause frame
960 * generated by xena. 969 * generated by xena.
961 */ 970 */
962 val64 = readq(&bar0->rmac_pause_cfg); 971 val64 = readq(&bar0->rmac_pause_cfg);
@@ -964,7 +973,7 @@ static int init_nic(struct s2io_nic *nic)
964 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time); 973 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
965 writeq(val64, &bar0->rmac_pause_cfg); 974 writeq(val64, &bar0->rmac_pause_cfg);
966 975
967 /* 976 /*
968 * Set the Threshold Limit for Generating the pause frame 977 * Set the Threshold Limit for Generating the pause frame
969 * If the amount of data in any Queue exceeds ratio of 978 * If the amount of data in any Queue exceeds ratio of
970 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256 979 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
@@ -988,8 +997,8 @@ static int init_nic(struct s2io_nic *nic)
988 } 997 }
989 writeq(val64, &bar0->mc_pause_thresh_q4q7); 998 writeq(val64, &bar0->mc_pause_thresh_q4q7);
990 999
991 /* 1000 /*
992 * TxDMA will stop Read request if the number of read split has 1001 * TxDMA will stop Read request if the number of read split has
993 * exceeded the limit pointed by shared_splits 1002 * exceeded the limit pointed by shared_splits
994 */ 1003 */
995 val64 = readq(&bar0->pic_control); 1004 val64 = readq(&bar0->pic_control);
@@ -999,14 +1008,14 @@ static int init_nic(struct s2io_nic *nic)
999 return SUCCESS; 1008 return SUCCESS;
1000} 1009}
1001 1010
1002/** 1011/**
1003 * en_dis_able_nic_intrs - Enable or Disable the interrupts 1012 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1004 * @nic: device private variable, 1013 * @nic: device private variable,
1005 * @mask: A mask indicating which Intr block must be modified and, 1014 * @mask: A mask indicating which Intr block must be modified and,
1006 * @flag: A flag indicating whether to enable or disable the Intrs. 1015 * @flag: A flag indicating whether to enable or disable the Intrs.
1007 * Description: This function will either disable or enable the interrupts 1016 * Description: This function will either disable or enable the interrupts
1008 * depending on the flag argument. The mask argument can be used to 1017 * depending on the flag argument. The mask argument can be used to
1009 * enable/disable any Intr block. 1018 * enable/disable any Intr block.
1010 * Return Value: NONE. 1019 * Return Value: NONE.
1011 */ 1020 */
1012 1021
@@ -1024,20 +1033,20 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1024 temp64 = readq(&bar0->general_int_mask); 1033 temp64 = readq(&bar0->general_int_mask);
1025 temp64 &= ~((u64) val64); 1034 temp64 &= ~((u64) val64);
1026 writeq(temp64, &bar0->general_int_mask); 1035 writeq(temp64, &bar0->general_int_mask);
1027 /* 1036 /*
1028 * Disabled all PCIX, Flash, MDIO, IIC and GPIO 1037 * Disabled all PCIX, Flash, MDIO, IIC and GPIO
1029 * interrupts for now. 1038 * interrupts for now.
1030 * TODO 1039 * TODO
1031 */ 1040 */
1032 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); 1041 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1033 /* 1042 /*
1034 * No MSI Support is available presently, so TTI and 1043 * No MSI Support is available presently, so TTI and
1035 * RTI interrupts are also disabled. 1044 * RTI interrupts are also disabled.
1036 */ 1045 */
1037 } else if (flag == DISABLE_INTRS) { 1046 } else if (flag == DISABLE_INTRS) {
1038 /* 1047 /*
1039 * Disable PIC Intrs in the general 1048 * Disable PIC Intrs in the general
1040 * intr mask register 1049 * intr mask register
1041 */ 1050 */
1042 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); 1051 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1043 temp64 = readq(&bar0->general_int_mask); 1052 temp64 = readq(&bar0->general_int_mask);
@@ -1055,27 +1064,27 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1055 temp64 = readq(&bar0->general_int_mask); 1064 temp64 = readq(&bar0->general_int_mask);
1056 temp64 &= ~((u64) val64); 1065 temp64 &= ~((u64) val64);
1057 writeq(temp64, &bar0->general_int_mask); 1066 writeq(temp64, &bar0->general_int_mask);
1058 /* 1067 /*
1059 * Keep all interrupts other than PFC interrupt 1068 * Keep all interrupts other than PFC interrupt
1060 * and PCC interrupt disabled in DMA level. 1069 * and PCC interrupt disabled in DMA level.
1061 */ 1070 */
1062 val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M | 1071 val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1063 TXDMA_PCC_INT_M); 1072 TXDMA_PCC_INT_M);
1064 writeq(val64, &bar0->txdma_int_mask); 1073 writeq(val64, &bar0->txdma_int_mask);
1065 /* 1074 /*
1066 * Enable only the MISC error 1 interrupt in PFC block 1075 * Enable only the MISC error 1 interrupt in PFC block
1067 */ 1076 */
1068 val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1); 1077 val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1069 writeq(val64, &bar0->pfc_err_mask); 1078 writeq(val64, &bar0->pfc_err_mask);
1070 /* 1079 /*
1071 * Enable only the FB_ECC error interrupt in PCC block 1080 * Enable only the FB_ECC error interrupt in PCC block
1072 */ 1081 */
1073 val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR); 1082 val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1074 writeq(val64, &bar0->pcc_err_mask); 1083 writeq(val64, &bar0->pcc_err_mask);
1075 } else if (flag == DISABLE_INTRS) { 1084 } else if (flag == DISABLE_INTRS) {
1076 /* 1085 /*
1077 * Disable TxDMA Intrs in the general intr mask 1086 * Disable TxDMA Intrs in the general intr mask
1078 * register 1087 * register
1079 */ 1088 */
1080 writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask); 1089 writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1081 writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask); 1090 writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
@@ -1093,15 +1102,15 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1093 temp64 = readq(&bar0->general_int_mask); 1102 temp64 = readq(&bar0->general_int_mask);
1094 temp64 &= ~((u64) val64); 1103 temp64 &= ~((u64) val64);
1095 writeq(temp64, &bar0->general_int_mask); 1104 writeq(temp64, &bar0->general_int_mask);
1096 /* 1105 /*
1097 * All RxDMA block interrupts are disabled for now 1106 * All RxDMA block interrupts are disabled for now
1098 * TODO 1107 * TODO
1099 */ 1108 */
1100 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask); 1109 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1101 } else if (flag == DISABLE_INTRS) { 1110 } else if (flag == DISABLE_INTRS) {
1102 /* 1111 /*
1103 * Disable RxDMA Intrs in the general intr mask 1112 * Disable RxDMA Intrs in the general intr mask
1104 * register 1113 * register
1105 */ 1114 */
1106 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask); 1115 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1107 temp64 = readq(&bar0->general_int_mask); 1116 temp64 = readq(&bar0->general_int_mask);
@@ -1118,8 +1127,8 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1118 temp64 = readq(&bar0->general_int_mask); 1127 temp64 = readq(&bar0->general_int_mask);
1119 temp64 &= ~((u64) val64); 1128 temp64 &= ~((u64) val64);
1120 writeq(temp64, &bar0->general_int_mask); 1129 writeq(temp64, &bar0->general_int_mask);
1121 /* 1130 /*
1122 * All MAC block error interrupts are disabled for now 1131 * All MAC block error interrupts are disabled for now
1123 * except the link status change interrupt. 1132 * except the link status change interrupt.
1124 * TODO 1133 * TODO
1125 */ 1134 */
@@ -1132,8 +1141,8 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1132 val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT); 1141 val64 &= ~((u64) RMAC_LINK_STATE_CHANGE_INT);
1133 writeq(val64, &bar0->mac_rmac_err_mask); 1142 writeq(val64, &bar0->mac_rmac_err_mask);
1134 } else if (flag == DISABLE_INTRS) { 1143 } else if (flag == DISABLE_INTRS) {
1135 /* 1144 /*
1136 * Disable MAC Intrs in the general intr mask register 1145 * Disable MAC Intrs in the general intr mask register
1137 */ 1146 */
1138 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask); 1147 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1139 writeq(DISABLE_ALL_INTRS, 1148 writeq(DISABLE_ALL_INTRS,
@@ -1152,14 +1161,14 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1152 temp64 = readq(&bar0->general_int_mask); 1161 temp64 = readq(&bar0->general_int_mask);
1153 temp64 &= ~((u64) val64); 1162 temp64 &= ~((u64) val64);
1154 writeq(temp64, &bar0->general_int_mask); 1163 writeq(temp64, &bar0->general_int_mask);
1155 /* 1164 /*
1156 * All XGXS block error interrupts are disabled for now 1165 * All XGXS block error interrupts are disabled for now
1157 * TODO 1166 * TODO
1158 */ 1167 */
1159 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask); 1168 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1160 } else if (flag == DISABLE_INTRS) { 1169 } else if (flag == DISABLE_INTRS) {
1161 /* 1170 /*
1162 * Disable MC Intrs in the general intr mask register 1171 * Disable MC Intrs in the general intr mask register
1163 */ 1172 */
1164 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask); 1173 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1165 temp64 = readq(&bar0->general_int_mask); 1174 temp64 = readq(&bar0->general_int_mask);
@@ -1175,9 +1184,9 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1175 temp64 = readq(&bar0->general_int_mask); 1184 temp64 = readq(&bar0->general_int_mask);
1176 temp64 &= ~((u64) val64); 1185 temp64 &= ~((u64) val64);
1177 writeq(temp64, &bar0->general_int_mask); 1186 writeq(temp64, &bar0->general_int_mask);
1178 /* 1187 /*
1179 * All MC block error interrupts are disabled for now 1188 * All MC block error interrupts are disabled for now.
1180 * TODO 1189 * TODO
1181 */ 1190 */
1182 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask); 1191 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1183 } else if (flag == DISABLE_INTRS) { 1192 } else if (flag == DISABLE_INTRS) {
@@ -1199,14 +1208,14 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1199 temp64 = readq(&bar0->general_int_mask); 1208 temp64 = readq(&bar0->general_int_mask);
1200 temp64 &= ~((u64) val64); 1209 temp64 &= ~((u64) val64);
1201 writeq(temp64, &bar0->general_int_mask); 1210 writeq(temp64, &bar0->general_int_mask);
1202 /* 1211 /*
1203 * Enable all the Tx side interrupts 1212 * Enable all the Tx side interrupts
1204 * writing 0 Enables all 64 TX interrupt levels 1213 * writing 0 Enables all 64 TX interrupt levels
1205 */ 1214 */
1206 writeq(0x0, &bar0->tx_traffic_mask); 1215 writeq(0x0, &bar0->tx_traffic_mask);
1207 } else if (flag == DISABLE_INTRS) { 1216 } else if (flag == DISABLE_INTRS) {
1208 /* 1217 /*
1209 * Disable Tx Traffic Intrs in the general intr mask 1218 * Disable Tx Traffic Intrs in the general intr mask
1210 * register. 1219 * register.
1211 */ 1220 */
1212 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); 1221 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
@@ -1226,8 +1235,8 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1226 /* writing 0 Enables all 8 RX interrupt levels */ 1235 /* writing 0 Enables all 8 RX interrupt levels */
1227 writeq(0x0, &bar0->rx_traffic_mask); 1236 writeq(0x0, &bar0->rx_traffic_mask);
1228 } else if (flag == DISABLE_INTRS) { 1237 } else if (flag == DISABLE_INTRS) {
1229 /* 1238 /*
1230 * Disable Rx Traffic Intrs in the general intr mask 1239 * Disable Rx Traffic Intrs in the general intr mask
1231 * register. 1240 * register.
1232 */ 1241 */
1233 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); 1242 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
@@ -1238,20 +1247,42 @@ static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1238 } 1247 }
1239} 1248}
1240 1249
1241/** 1250static int check_prc_pcc_state(u64 val64, int flag)
1242 * verify_xena_quiescence - Checks whether the H/W is ready 1251{
1252 int ret = 0;
1253
1254 if (flag == FALSE) {
1255 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1256 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1257 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1258 ret = 1;
1259 }
1260 } else {
1261 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1262 ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1263 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1264 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1265 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1266 ret = 1;
1267 }
1268 }
1269
1270 return ret;
1271}
1272/**
1273 * verify_xena_quiescence - Checks whether the H/W is ready
1243 * @val64 : Value read from adapter status register. 1274 * @val64 : Value read from adapter status register.
1244 * @flag : indicates if the adapter enable bit was ever written once 1275 * @flag : indicates if the adapter enable bit was ever written once
1245 * before. 1276 * before.
1246 * Description: Returns whether the H/W is ready to go or not. Depending 1277 * Description: Returns whether the H/W is ready to go or not. Depending
1247 * on whether adapter enable bit was written or not the comparison 1278 * on whether adapter enable bit was written or not the comparison
1248 * differs and the calling function passes the input argument flag to 1279 * differs and the calling function passes the input argument flag to
1249 * indicate this. 1280 * indicate this.
1250 * Return: 1 If xena is quiescence 1281 * Return: 1 If xena is quiescence
1251 * 0 If Xena is not quiescence 1282 * 0 If Xena is not quiescence
1252 */ 1283 */
1253 1284
1254static int verify_xena_quiescence(u64 val64, int flag) 1285static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1255{ 1286{
1256 int ret = 0; 1287 int ret = 0;
1257 u64 tmp64 = ~((u64) val64); 1288 u64 tmp64 = ~((u64) val64);
@@ -1263,25 +1294,7 @@ static int verify_xena_quiescence(u64 val64, int flag)
1263 ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY | 1294 ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1264 ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK | 1295 ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1265 ADAPTER_STATUS_P_PLL_LOCK))) { 1296 ADAPTER_STATUS_P_PLL_LOCK))) {
1266 if (flag == FALSE) { 1297 ret = check_prc_pcc_state(val64, flag);
1267 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1268 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1269 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1270
1271 ret = 1;
1272
1273 }
1274 } else {
1275 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1276 ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1277 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1278 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1279 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1280
1281 ret = 1;
1282
1283 }
1284 }
1285 } 1298 }
1286 1299
1287 return ret; 1300 return ret;
@@ -1290,12 +1303,12 @@ static int verify_xena_quiescence(u64 val64, int flag)
1290/** 1303/**
1291 * fix_mac_address - Fix for Mac addr problem on Alpha platforms 1304 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1292 * @sp: Pointer to device specifc structure 1305 * @sp: Pointer to device specifc structure
1293 * Description : 1306 * Description :
1294 * New procedure to clear mac address reading problems on Alpha platforms 1307 * New procedure to clear mac address reading problems on Alpha platforms
1295 * 1308 *
1296 */ 1309 */
1297 1310
1298static void fix_mac_address(nic_t * sp) 1311void fix_mac_address(nic_t * sp)
1299{ 1312{
1300 XENA_dev_config_t __iomem *bar0 = sp->bar0; 1313 XENA_dev_config_t __iomem *bar0 = sp->bar0;
1301 u64 val64; 1314 u64 val64;
@@ -1303,20 +1316,21 @@ static void fix_mac_address(nic_t * sp)
1303 1316
1304 while (fix_mac[i] != END_SIGN) { 1317 while (fix_mac[i] != END_SIGN) {
1305 writeq(fix_mac[i++], &bar0->gpio_control); 1318 writeq(fix_mac[i++], &bar0->gpio_control);
1319 udelay(10);
1306 val64 = readq(&bar0->gpio_control); 1320 val64 = readq(&bar0->gpio_control);
1307 } 1321 }
1308} 1322}
1309 1323
1310/** 1324/**
1311 * start_nic - Turns the device on 1325 * start_nic - Turns the device on
1312 * @nic : device private variable. 1326 * @nic : device private variable.
1313 * Description: 1327 * Description:
1314 * This function actually turns the device on. Before this function is 1328 * This function actually turns the device on. Before this function is
1315 * called,all Registers are configured from their reset states 1329 * called,all Registers are configured from their reset states
1316 * and shared memory is allocated but the NIC is still quiescent. On 1330 * and shared memory is allocated but the NIC is still quiescent. On
1317 * calling this function, the device interrupts are cleared and the NIC is 1331 * calling this function, the device interrupts are cleared and the NIC is
1318 * literally switched on by writing into the adapter control register. 1332 * literally switched on by writing into the adapter control register.
1319 * Return Value: 1333 * Return Value:
1320 * SUCCESS on success and -1 on failure. 1334 * SUCCESS on success and -1 on failure.
1321 */ 1335 */
1322 1336
@@ -1325,8 +1339,8 @@ static int start_nic(struct s2io_nic *nic)
1325 XENA_dev_config_t __iomem *bar0 = nic->bar0; 1339 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1326 struct net_device *dev = nic->dev; 1340 struct net_device *dev = nic->dev;
1327 register u64 val64 = 0; 1341 register u64 val64 = 0;
1328 u16 interruptible, i; 1342 u16 interruptible;
1329 u16 subid; 1343 u16 subid, i;
1330 mac_info_t *mac_control; 1344 mac_info_t *mac_control;
1331 struct config_param *config; 1345 struct config_param *config;
1332 1346
@@ -1335,7 +1349,7 @@ static int start_nic(struct s2io_nic *nic)
1335 1349
1336 /* PRC Initialization and configuration */ 1350 /* PRC Initialization and configuration */
1337 for (i = 0; i < config->rx_ring_num; i++) { 1351 for (i = 0; i < config->rx_ring_num; i++) {
1338 writeq((u64) nic->rx_blocks[i][0].block_dma_addr, 1352 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1339 &bar0->prc_rxd0_n[i]); 1353 &bar0->prc_rxd0_n[i]);
1340 1354
1341 val64 = readq(&bar0->prc_ctrl_n[i]); 1355 val64 = readq(&bar0->prc_ctrl_n[i]);
@@ -1354,7 +1368,7 @@ static int start_nic(struct s2io_nic *nic)
1354 writeq(val64, &bar0->rx_pa_cfg); 1368 writeq(val64, &bar0->rx_pa_cfg);
1355#endif 1369#endif
1356 1370
1357 /* 1371 /*
1358 * Enabling MC-RLDRAM. After enabling the device, we timeout 1372 * Enabling MC-RLDRAM. After enabling the device, we timeout
1359 * for around 100ms, which is approximately the time required 1373 * for around 100ms, which is approximately the time required
1360 * for the device to be ready for operation. 1374 * for the device to be ready for operation.
@@ -1364,27 +1378,27 @@ static int start_nic(struct s2io_nic *nic)
1364 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); 1378 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1365 val64 = readq(&bar0->mc_rldram_mrs); 1379 val64 = readq(&bar0->mc_rldram_mrs);
1366 1380
1367 msleep(100); /* Delay by around 100 ms. */ 1381 msleep(100); /* Delay by around 100 ms. */
1368 1382
1369 /* Enabling ECC Protection. */ 1383 /* Enabling ECC Protection. */
1370 val64 = readq(&bar0->adapter_control); 1384 val64 = readq(&bar0->adapter_control);
1371 val64 &= ~ADAPTER_ECC_EN; 1385 val64 &= ~ADAPTER_ECC_EN;
1372 writeq(val64, &bar0->adapter_control); 1386 writeq(val64, &bar0->adapter_control);
1373 1387
1374 /* 1388 /*
1375 * Clearing any possible Link state change interrupts that 1389 * Clearing any possible Link state change interrupts that
1376 * could have popped up just before Enabling the card. 1390 * could have popped up just before Enabling the card.
1377 */ 1391 */
1378 val64 = readq(&bar0->mac_rmac_err_reg); 1392 val64 = readq(&bar0->mac_rmac_err_reg);
1379 if (val64) 1393 if (val64)
1380 writeq(val64, &bar0->mac_rmac_err_reg); 1394 writeq(val64, &bar0->mac_rmac_err_reg);
1381 1395
1382 /* 1396 /*
1383 * Verify if the device is ready to be enabled, if so enable 1397 * Verify if the device is ready to be enabled, if so enable
1384 * it. 1398 * it.
1385 */ 1399 */
1386 val64 = readq(&bar0->adapter_status); 1400 val64 = readq(&bar0->adapter_status);
1387 if (!verify_xena_quiescence(val64, nic->device_enabled_once)) { 1401 if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
1388 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name); 1402 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
1389 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n", 1403 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
1390 (unsigned long long) val64); 1404 (unsigned long long) val64);
@@ -1396,12 +1410,12 @@ static int start_nic(struct s2io_nic *nic)
1396 RX_MAC_INTR; 1410 RX_MAC_INTR;
1397 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS); 1411 en_dis_able_nic_intrs(nic, interruptible, ENABLE_INTRS);
1398 1412
1399 /* 1413 /*
1400 * With some switches, link might be already up at this point. 1414 * With some switches, link might be already up at this point.
1401 * Because of this weird behavior, when we enable laser, 1415 * Because of this weird behavior, when we enable laser,
1402 * we may not get link. We need to handle this. We cannot 1416 * we may not get link. We need to handle this. We cannot
1403 * figure out which switch is misbehaving. So we are forced to 1417 * figure out which switch is misbehaving. So we are forced to
1404 * make a global change. 1418 * make a global change.
1405 */ 1419 */
1406 1420
1407 /* Enabling Laser. */ 1421 /* Enabling Laser. */
@@ -1416,17 +1430,17 @@ static int start_nic(struct s2io_nic *nic)
1416 val64 |= 0x0000800000000000ULL; 1430 val64 |= 0x0000800000000000ULL;
1417 writeq(val64, &bar0->gpio_control); 1431 writeq(val64, &bar0->gpio_control);
1418 val64 = 0x0411040400000000ULL; 1432 val64 = 0x0411040400000000ULL;
1419 writeq(val64, (void __iomem *) bar0 + 0x2700); 1433 writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));
1420 } 1434 }
1421 1435
1422 /* 1436 /*
1423 * Don't see link state interrupts on certain switches, so 1437 * Don't see link state interrupts on certain switches, so
1424 * directly scheduling a link state task from here. 1438 * directly scheduling a link state task from here.
1425 */ 1439 */
1426 schedule_work(&nic->set_link_task); 1440 schedule_work(&nic->set_link_task);
1427 1441
1428 /* 1442 /*
1429 * Here we are performing soft reset on XGXS to 1443 * Here we are performing soft reset on XGXS to
1430 * force link down. Since link is already up, we will get 1444 * force link down. Since link is already up, we will get
1431 * link state change interrupt after this reset 1445 * link state change interrupt after this reset
1432 */ 1446 */
@@ -1443,12 +1457,12 @@ static int start_nic(struct s2io_nic *nic)
1443 return SUCCESS; 1457 return SUCCESS;
1444} 1458}
1445 1459
1446/** 1460/**
1447 * free_tx_buffers - Free all queued Tx buffers 1461 * free_tx_buffers - Free all queued Tx buffers
1448 * @nic : device private variable. 1462 * @nic : device private variable.
1449 * Description: 1463 * Description:
1450 * Free all queued Tx buffers. 1464 * Free all queued Tx buffers.
1451 * Return Value: void 1465 * Return Value: void
1452*/ 1466*/
1453 1467
1454static void free_tx_buffers(struct s2io_nic *nic) 1468static void free_tx_buffers(struct s2io_nic *nic)
@@ -1466,7 +1480,7 @@ static void free_tx_buffers(struct s2io_nic *nic)
1466 1480
1467 for (i = 0; i < config->tx_fifo_num; i++) { 1481 for (i = 0; i < config->tx_fifo_num; i++) {
1468 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) { 1482 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
1469 txdp = (TxD_t *) nic->list_info[i][j]. 1483 txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
1470 list_virt_addr; 1484 list_virt_addr;
1471 skb = 1485 skb =
1472 (struct sk_buff *) ((unsigned long) txdp-> 1486 (struct sk_buff *) ((unsigned long) txdp->
@@ -1482,16 +1496,16 @@ static void free_tx_buffers(struct s2io_nic *nic)
1482 DBG_PRINT(INTR_DBG, 1496 DBG_PRINT(INTR_DBG,
1483 "%s:forcibly freeing %d skbs on FIFO%d\n", 1497 "%s:forcibly freeing %d skbs on FIFO%d\n",
1484 dev->name, cnt, i); 1498 dev->name, cnt, i);
1485 mac_control->tx_curr_get_info[i].offset = 0; 1499 mac_control->fifos[i].tx_curr_get_info.offset = 0;
1486 mac_control->tx_curr_put_info[i].offset = 0; 1500 mac_control->fifos[i].tx_curr_put_info.offset = 0;
1487 } 1501 }
1488} 1502}
1489 1503
1490/** 1504/**
1491 * stop_nic - To stop the nic 1505 * stop_nic - To stop the nic
1492 * @nic ; device private variable. 1506 * @nic ; device private variable.
1493 * Description: 1507 * Description:
1494 * This function does exactly the opposite of what the start_nic() 1508 * This function does exactly the opposite of what the start_nic()
1495 * function does. This function is called to stop the device. 1509 * function does. This function is called to stop the device.
1496 * Return Value: 1510 * Return Value:
1497 * void. 1511 * void.
@@ -1521,11 +1535,11 @@ static void stop_nic(struct s2io_nic *nic)
1521 } 1535 }
1522} 1536}
1523 1537
1524/** 1538/**
1525 * fill_rx_buffers - Allocates the Rx side skbs 1539 * fill_rx_buffers - Allocates the Rx side skbs
1526 * @nic: device private variable 1540 * @nic: device private variable
1527 * @ring_no: ring number 1541 * @ring_no: ring number
1528 * Description: 1542 * Description:
1529 * The function allocates Rx side skbs and puts the physical 1543 * The function allocates Rx side skbs and puts the physical
1530 * address of these buffers into the RxD buffer pointers, so that the NIC 1544 * address of these buffers into the RxD buffer pointers, so that the NIC
1531 * can DMA the received frame into these locations. 1545 * can DMA the received frame into these locations.
@@ -1533,8 +1547,8 @@ static void stop_nic(struct s2io_nic *nic)
1533 * 1. single buffer, 1547 * 1. single buffer,
1534 * 2. three buffer and 1548 * 2. three buffer and
1535 * 3. Five buffer modes. 1549 * 3. Five buffer modes.
1536 * Each mode defines how many fragments the received frame will be split 1550 * Each mode defines how many fragments the received frame will be split
1537 * up into by the NIC. The frame is split into L3 header, L4 Header, 1551 * up into by the NIC. The frame is split into L3 header, L4 Header,
1538 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself 1552 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
1539 * is split into 3 fragments. As of now only single buffer mode is 1553 * is split into 3 fragments. As of now only single buffer mode is
1540 * supported. 1554 * supported.
@@ -1542,7 +1556,7 @@ static void stop_nic(struct s2io_nic *nic)
1542 * SUCCESS on success or an appropriate -ve value on failure. 1556 * SUCCESS on success or an appropriate -ve value on failure.
1543 */ 1557 */
1544 1558
1545static int fill_rx_buffers(struct s2io_nic *nic, int ring_no) 1559int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1546{ 1560{
1547 struct net_device *dev = nic->dev; 1561 struct net_device *dev = nic->dev;
1548 struct sk_buff *skb; 1562 struct sk_buff *skb;
@@ -1550,14 +1564,13 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1550 int off, off1, size, block_no, block_no1; 1564 int off, off1, size, block_no, block_no1;
1551 int offset, offset1; 1565 int offset, offset1;
1552 u32 alloc_tab = 0; 1566 u32 alloc_tab = 0;
1553 u32 alloc_cnt = nic->pkt_cnt[ring_no] - 1567 u32 alloc_cnt;
1554 atomic_read(&nic->rx_bufs_left[ring_no]);
1555 mac_info_t *mac_control; 1568 mac_info_t *mac_control;
1556 struct config_param *config; 1569 struct config_param *config;
1557#ifdef CONFIG_2BUFF_MODE 1570#ifdef CONFIG_2BUFF_MODE
1558 RxD_t *rxdpnext; 1571 RxD_t *rxdpnext;
1559 int nextblk; 1572 int nextblk;
1560 unsigned long tmp; 1573 u64 tmp;
1561 buffAdd_t *ba; 1574 buffAdd_t *ba;
1562 dma_addr_t rxdpphys; 1575 dma_addr_t rxdpphys;
1563#endif 1576#endif
@@ -1567,17 +1580,18 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1567 1580
1568 mac_control = &nic->mac_control; 1581 mac_control = &nic->mac_control;
1569 config = &nic->config; 1582 config = &nic->config;
1570 1583 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
1584 atomic_read(&nic->rx_bufs_left[ring_no]);
1571 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE + 1585 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
1572 HEADER_802_2_SIZE + HEADER_SNAP_SIZE; 1586 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
1573 1587
1574 while (alloc_tab < alloc_cnt) { 1588 while (alloc_tab < alloc_cnt) {
1575 block_no = mac_control->rx_curr_put_info[ring_no]. 1589 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1576 block_index; 1590 block_index;
1577 block_no1 = mac_control->rx_curr_get_info[ring_no]. 1591 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.
1578 block_index; 1592 block_index;
1579 off = mac_control->rx_curr_put_info[ring_no].offset; 1593 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1580 off1 = mac_control->rx_curr_get_info[ring_no].offset; 1594 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1581#ifndef CONFIG_2BUFF_MODE 1595#ifndef CONFIG_2BUFF_MODE
1582 offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off; 1596 offset = block_no * (MAX_RXDS_PER_BLOCK + 1) + off;
1583 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1; 1597 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK + 1) + off1;
@@ -1586,7 +1600,7 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1586 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1; 1600 offset1 = block_no1 * (MAX_RXDS_PER_BLOCK) + off1;
1587#endif 1601#endif
1588 1602
1589 rxdp = nic->rx_blocks[ring_no][block_no]. 1603 rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
1590 block_virt_addr + off; 1604 block_virt_addr + off;
1591 if ((offset == offset1) && (rxdp->Host_Control)) { 1605 if ((offset == offset1) && (rxdp->Host_Control)) {
1592 DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name); 1606 DBG_PRINT(INTR_DBG, "%s: Get and Put", dev->name);
@@ -1595,15 +1609,15 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1595 } 1609 }
1596#ifndef CONFIG_2BUFF_MODE 1610#ifndef CONFIG_2BUFF_MODE
1597 if (rxdp->Control_1 == END_OF_BLOCK) { 1611 if (rxdp->Control_1 == END_OF_BLOCK) {
1598 mac_control->rx_curr_put_info[ring_no]. 1612 mac_control->rings[ring_no].rx_curr_put_info.
1599 block_index++; 1613 block_index++;
1600 mac_control->rx_curr_put_info[ring_no]. 1614 mac_control->rings[ring_no].rx_curr_put_info.
1601 block_index %= nic->block_count[ring_no]; 1615 block_index %= mac_control->rings[ring_no].block_count;
1602 block_no = mac_control->rx_curr_put_info 1616 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1603 [ring_no].block_index; 1617 block_index;
1604 off++; 1618 off++;
1605 off %= (MAX_RXDS_PER_BLOCK + 1); 1619 off %= (MAX_RXDS_PER_BLOCK + 1);
1606 mac_control->rx_curr_put_info[ring_no].offset = 1620 mac_control->rings[ring_no].rx_curr_put_info.offset =
1607 off; 1621 off;
1608 rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2); 1622 rxdp = (RxD_t *) ((unsigned long) rxdp->Control_2);
1609 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n", 1623 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
@@ -1611,30 +1625,30 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1611 } 1625 }
1612#ifndef CONFIG_S2IO_NAPI 1626#ifndef CONFIG_S2IO_NAPI
1613 spin_lock_irqsave(&nic->put_lock, flags); 1627 spin_lock_irqsave(&nic->put_lock, flags);
1614 nic->put_pos[ring_no] = 1628 mac_control->rings[ring_no].put_pos =
1615 (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off; 1629 (block_no * (MAX_RXDS_PER_BLOCK + 1)) + off;
1616 spin_unlock_irqrestore(&nic->put_lock, flags); 1630 spin_unlock_irqrestore(&nic->put_lock, flags);
1617#endif 1631#endif
1618#else 1632#else
1619 if (rxdp->Host_Control == END_OF_BLOCK) { 1633 if (rxdp->Host_Control == END_OF_BLOCK) {
1620 mac_control->rx_curr_put_info[ring_no]. 1634 mac_control->rings[ring_no].rx_curr_put_info.
1621 block_index++; 1635 block_index++;
1622 mac_control->rx_curr_put_info[ring_no]. 1636 mac_control->rings[ring_no].rx_curr_put_info.block_index
1623 block_index %= nic->block_count[ring_no]; 1637 %= mac_control->rings[ring_no].block_count;
1624 block_no = mac_control->rx_curr_put_info 1638 block_no = mac_control->rings[ring_no].rx_curr_put_info
1625 [ring_no].block_index; 1639 .block_index;
1626 off = 0; 1640 off = 0;
1627 DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n", 1641 DBG_PRINT(INTR_DBG, "%s: block%d at: 0x%llx\n",
1628 dev->name, block_no, 1642 dev->name, block_no,
1629 (unsigned long long) rxdp->Control_1); 1643 (unsigned long long) rxdp->Control_1);
1630 mac_control->rx_curr_put_info[ring_no].offset = 1644 mac_control->rings[ring_no].rx_curr_put_info.offset =
1631 off; 1645 off;
1632 rxdp = nic->rx_blocks[ring_no][block_no]. 1646 rxdp = mac_control->rings[ring_no].rx_blocks[block_no].
1633 block_virt_addr; 1647 block_virt_addr;
1634 } 1648 }
1635#ifndef CONFIG_S2IO_NAPI 1649#ifndef CONFIG_S2IO_NAPI
1636 spin_lock_irqsave(&nic->put_lock, flags); 1650 spin_lock_irqsave(&nic->put_lock, flags);
1637 nic->put_pos[ring_no] = (block_no * 1651 mac_control->rings[ring_no].put_pos = (block_no *
1638 (MAX_RXDS_PER_BLOCK + 1)) + off; 1652 (MAX_RXDS_PER_BLOCK + 1)) + off;
1639 spin_unlock_irqrestore(&nic->put_lock, flags); 1653 spin_unlock_irqrestore(&nic->put_lock, flags);
1640#endif 1654#endif
@@ -1646,27 +1660,27 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1646 if (rxdp->Control_2 & BIT(0)) 1660 if (rxdp->Control_2 & BIT(0))
1647#endif 1661#endif
1648 { 1662 {
1649 mac_control->rx_curr_put_info[ring_no]. 1663 mac_control->rings[ring_no].rx_curr_put_info.
1650 offset = off; 1664 offset = off;
1651 goto end; 1665 goto end;
1652 } 1666 }
1653#ifdef CONFIG_2BUFF_MODE 1667#ifdef CONFIG_2BUFF_MODE
1654 /* 1668 /*
1655 * RxDs Spanning cache lines will be replenished only 1669 * RxDs Spanning cache lines will be replenished only
1656 * if the succeeding RxD is also owned by Host. It 1670 * if the succeeding RxD is also owned by Host. It
1657 * will always be the ((8*i)+3) and ((8*i)+6) 1671 * will always be the ((8*i)+3) and ((8*i)+6)
1658 * descriptors for the 48 byte descriptor. The offending 1672 * descriptors for the 48 byte descriptor. The offending
1659 * decsriptor is of-course the 3rd descriptor. 1673 * decsriptor is of-course the 3rd descriptor.
1660 */ 1674 */
1661 rxdpphys = nic->rx_blocks[ring_no][block_no]. 1675 rxdpphys = mac_control->rings[ring_no].rx_blocks[block_no].
1662 block_dma_addr + (off * sizeof(RxD_t)); 1676 block_dma_addr + (off * sizeof(RxD_t));
1663 if (((u64) (rxdpphys)) % 128 > 80) { 1677 if (((u64) (rxdpphys)) % 128 > 80) {
1664 rxdpnext = nic->rx_blocks[ring_no][block_no]. 1678 rxdpnext = mac_control->rings[ring_no].rx_blocks[block_no].
1665 block_virt_addr + (off + 1); 1679 block_virt_addr + (off + 1);
1666 if (rxdpnext->Host_Control == END_OF_BLOCK) { 1680 if (rxdpnext->Host_Control == END_OF_BLOCK) {
1667 nextblk = (block_no + 1) % 1681 nextblk = (block_no + 1) %
1668 (nic->block_count[ring_no]); 1682 (mac_control->rings[ring_no].block_count);
1669 rxdpnext = nic->rx_blocks[ring_no] 1683 rxdpnext = mac_control->rings[ring_no].rx_blocks
1670 [nextblk].block_virt_addr; 1684 [nextblk].block_virt_addr;
1671 } 1685 }
1672 if (rxdpnext->Control_2 & BIT(0)) 1686 if (rxdpnext->Control_2 & BIT(0))
@@ -1695,9 +1709,9 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1695 rxdp->Control_1 |= RXD_OWN_XENA; 1709 rxdp->Control_1 |= RXD_OWN_XENA;
1696 off++; 1710 off++;
1697 off %= (MAX_RXDS_PER_BLOCK + 1); 1711 off %= (MAX_RXDS_PER_BLOCK + 1);
1698 mac_control->rx_curr_put_info[ring_no].offset = off; 1712 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
1699#else 1713#else
1700 ba = &nic->ba[ring_no][block_no][off]; 1714 ba = &mac_control->rings[ring_no].ba[block_no][off];
1701 skb_reserve(skb, BUF0_LEN); 1715 skb_reserve(skb, BUF0_LEN);
1702 tmp = ((unsigned long) skb->data & ALIGN_SIZE); 1716 tmp = ((unsigned long) skb->data & ALIGN_SIZE);
1703 if (tmp) 1717 if (tmp)
@@ -1721,8 +1735,9 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1721 rxdp->Host_Control = (u64) ((unsigned long) (skb)); 1735 rxdp->Host_Control = (u64) ((unsigned long) (skb));
1722 rxdp->Control_1 |= RXD_OWN_XENA; 1736 rxdp->Control_1 |= RXD_OWN_XENA;
1723 off++; 1737 off++;
1724 mac_control->rx_curr_put_info[ring_no].offset = off; 1738 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
1725#endif 1739#endif
1740
1726 atomic_inc(&nic->rx_bufs_left[ring_no]); 1741 atomic_inc(&nic->rx_bufs_left[ring_no]);
1727 alloc_tab++; 1742 alloc_tab++;
1728 } 1743 }
@@ -1732,9 +1747,9 @@ static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1732} 1747}
1733 1748
1734/** 1749/**
1735 * free_rx_buffers - Frees all Rx buffers 1750 * free_rx_buffers - Frees all Rx buffers
1736 * @sp: device private variable. 1751 * @sp: device private variable.
1737 * Description: 1752 * Description:
1738 * This function will free all Rx buffers allocated by host. 1753 * This function will free all Rx buffers allocated by host.
1739 * Return Value: 1754 * Return Value:
1740 * NONE. 1755 * NONE.
@@ -1758,7 +1773,8 @@ static void free_rx_buffers(struct s2io_nic *sp)
1758 for (i = 0; i < config->rx_ring_num; i++) { 1773 for (i = 0; i < config->rx_ring_num; i++) {
1759 for (j = 0, blk = 0; j < config->rx_cfg[i].num_rxd; j++) { 1774 for (j = 0, blk = 0; j < config->rx_cfg[i].num_rxd; j++) {
1760 off = j % (MAX_RXDS_PER_BLOCK + 1); 1775 off = j % (MAX_RXDS_PER_BLOCK + 1);
1761 rxdp = sp->rx_blocks[i][blk].block_virt_addr + off; 1776 rxdp = mac_control->rings[i].rx_blocks[blk].
1777 block_virt_addr + off;
1762 1778
1763#ifndef CONFIG_2BUFF_MODE 1779#ifndef CONFIG_2BUFF_MODE
1764 if (rxdp->Control_1 == END_OF_BLOCK) { 1780 if (rxdp->Control_1 == END_OF_BLOCK) {
@@ -1793,7 +1809,7 @@ static void free_rx_buffers(struct s2io_nic *sp)
1793 HEADER_SNAP_SIZE, 1809 HEADER_SNAP_SIZE,
1794 PCI_DMA_FROMDEVICE); 1810 PCI_DMA_FROMDEVICE);
1795#else 1811#else
1796 ba = &sp->ba[i][blk][off]; 1812 ba = &mac_control->rings[i].ba[blk][off];
1797 pci_unmap_single(sp->pdev, (dma_addr_t) 1813 pci_unmap_single(sp->pdev, (dma_addr_t)
1798 rxdp->Buffer0_ptr, 1814 rxdp->Buffer0_ptr,
1799 BUF0_LEN, 1815 BUF0_LEN,
@@ -1813,10 +1829,10 @@ static void free_rx_buffers(struct s2io_nic *sp)
1813 } 1829 }
1814 memset(rxdp, 0, sizeof(RxD_t)); 1830 memset(rxdp, 0, sizeof(RxD_t));
1815 } 1831 }
1816 mac_control->rx_curr_put_info[i].block_index = 0; 1832 mac_control->rings[i].rx_curr_put_info.block_index = 0;
1817 mac_control->rx_curr_get_info[i].block_index = 0; 1833 mac_control->rings[i].rx_curr_get_info.block_index = 0;
1818 mac_control->rx_curr_put_info[i].offset = 0; 1834 mac_control->rings[i].rx_curr_put_info.offset = 0;
1819 mac_control->rx_curr_get_info[i].offset = 0; 1835 mac_control->rings[i].rx_curr_get_info.offset = 0;
1820 atomic_set(&sp->rx_bufs_left[i], 0); 1836 atomic_set(&sp->rx_bufs_left[i], 0);
1821 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n", 1837 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
1822 dev->name, buf_cnt, i); 1838 dev->name, buf_cnt, i);
@@ -1826,7 +1842,7 @@ static void free_rx_buffers(struct s2io_nic *sp)
1826/** 1842/**
1827 * s2io_poll - Rx interrupt handler for NAPI support 1843 * s2io_poll - Rx interrupt handler for NAPI support
1828 * @dev : pointer to the device structure. 1844 * @dev : pointer to the device structure.
1829 * @budget : The number of packets that were budgeted to be processed 1845 * @budget : The number of packets that were budgeted to be processed
1830 * during one pass through the 'Poll" function. 1846 * during one pass through the 'Poll" function.
1831 * Description: 1847 * Description:
1832 * Comes into picture only if NAPI support has been incorporated. It does 1848 * Comes into picture only if NAPI support has been incorporated. It does
@@ -1836,160 +1852,35 @@ static void free_rx_buffers(struct s2io_nic *sp)
1836 * 0 on success and 1 if there are No Rx packets to be processed. 1852 * 0 on success and 1 if there are No Rx packets to be processed.
1837 */ 1853 */
1838 1854
1839#ifdef CONFIG_S2IO_NAPI 1855#if defined(CONFIG_S2IO_NAPI)
1840static int s2io_poll(struct net_device *dev, int *budget) 1856static int s2io_poll(struct net_device *dev, int *budget)
1841{ 1857{
1842 nic_t *nic = dev->priv; 1858 nic_t *nic = dev->priv;
1843 XENA_dev_config_t __iomem *bar0 = nic->bar0; 1859 int pkt_cnt = 0, org_pkts_to_process;
1844 int pkts_to_process = *budget, pkt_cnt = 0;
1845 register u64 val64 = 0;
1846 rx_curr_get_info_t get_info, put_info;
1847 int i, get_block, put_block, get_offset, put_offset, ring_bufs;
1848#ifndef CONFIG_2BUFF_MODE
1849 u16 val16, cksum;
1850#endif
1851 struct sk_buff *skb;
1852 RxD_t *rxdp;
1853 mac_info_t *mac_control; 1860 mac_info_t *mac_control;
1854 struct config_param *config; 1861 struct config_param *config;
1855#ifdef CONFIG_2BUFF_MODE 1862 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
1856 buffAdd_t *ba; 1863 u64 val64;
1857#endif 1864 int i;
1858 1865
1859 mac_control = &nic->mac_control; 1866 mac_control = &nic->mac_control;
1860 config = &nic->config; 1867 config = &nic->config;
1861 1868
1862 if (pkts_to_process > dev->quota) 1869 nic->pkts_to_process = *budget;
1863 pkts_to_process = dev->quota; 1870 if (nic->pkts_to_process > dev->quota)
1871 nic->pkts_to_process = dev->quota;
1872 org_pkts_to_process = nic->pkts_to_process;
1864 1873
1865 val64 = readq(&bar0->rx_traffic_int); 1874 val64 = readq(&bar0->rx_traffic_int);
1866 writeq(val64, &bar0->rx_traffic_int); 1875 writeq(val64, &bar0->rx_traffic_int);
1867 1876
1868 for (i = 0; i < config->rx_ring_num; i++) { 1877 for (i = 0; i < config->rx_ring_num; i++) {
1869 get_info = mac_control->rx_curr_get_info[i]; 1878 rx_intr_handler(&mac_control->rings[i]);
1870 get_block = get_info.block_index; 1879 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
1871 put_info = mac_control->rx_curr_put_info[i]; 1880 if (!nic->pkts_to_process) {
1872 put_block = put_info.block_index; 1881 /* Quota for the current iteration has been met */
1873 ring_bufs = config->rx_cfg[i].num_rxd; 1882 goto no_rx;
1874 rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
1875 get_info.offset;
1876#ifndef CONFIG_2BUFF_MODE
1877 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
1878 get_info.offset;
1879 put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
1880 put_info.offset;
1881 while ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
1882 (((get_offset + 1) % ring_bufs) != put_offset)) {
1883 if (--pkts_to_process < 0) {
1884 goto no_rx;
1885 }
1886 if (rxdp->Control_1 == END_OF_BLOCK) {
1887 rxdp =
1888 (RxD_t *) ((unsigned long) rxdp->
1889 Control_2);
1890 get_info.offset++;
1891 get_info.offset %=
1892 (MAX_RXDS_PER_BLOCK + 1);
1893 get_block++;
1894 get_block %= nic->block_count[i];
1895 mac_control->rx_curr_get_info[i].
1896 offset = get_info.offset;
1897 mac_control->rx_curr_get_info[i].
1898 block_index = get_block;
1899 continue;
1900 }
1901 get_offset =
1902 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
1903 get_info.offset;
1904 skb =
1905 (struct sk_buff *) ((unsigned long) rxdp->
1906 Host_Control);
1907 if (skb == NULL) {
1908 DBG_PRINT(ERR_DBG, "%s: The skb is ",
1909 dev->name);
1910 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
1911 goto no_rx;
1912 }
1913 val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
1914 val16 = (u16) (val64 >> 48);
1915 cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
1916 pci_unmap_single(nic->pdev, (dma_addr_t)
1917 rxdp->Buffer0_ptr,
1918 dev->mtu +
1919 HEADER_ETHERNET_II_802_3_SIZE +
1920 HEADER_802_2_SIZE +
1921 HEADER_SNAP_SIZE,
1922 PCI_DMA_FROMDEVICE);
1923 rx_osm_handler(nic, val16, rxdp, i);
1924 pkt_cnt++;
1925 get_info.offset++;
1926 get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
1927 rxdp =
1928 nic->rx_blocks[i][get_block].block_virt_addr +
1929 get_info.offset;
1930 mac_control->rx_curr_get_info[i].offset =
1931 get_info.offset;
1932 } 1883 }
1933#else
1934 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
1935 get_info.offset;
1936 put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
1937 put_info.offset;
1938 while (((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
1939 !(rxdp->Control_2 & BIT(0))) &&
1940 (((get_offset + 1) % ring_bufs) != put_offset)) {
1941 if (--pkts_to_process < 0) {
1942 goto no_rx;
1943 }
1944 skb = (struct sk_buff *) ((unsigned long)
1945 rxdp->Host_Control);
1946 if (skb == NULL) {
1947 DBG_PRINT(ERR_DBG, "%s: The skb is ",
1948 dev->name);
1949 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
1950 goto no_rx;
1951 }
1952
1953 pci_unmap_single(nic->pdev, (dma_addr_t)
1954 rxdp->Buffer0_ptr,
1955 BUF0_LEN, PCI_DMA_FROMDEVICE);
1956 pci_unmap_single(nic->pdev, (dma_addr_t)
1957 rxdp->Buffer1_ptr,
1958 BUF1_LEN, PCI_DMA_FROMDEVICE);
1959 pci_unmap_single(nic->pdev, (dma_addr_t)
1960 rxdp->Buffer2_ptr,
1961 dev->mtu + BUF0_LEN + 4,
1962 PCI_DMA_FROMDEVICE);
1963 ba = &nic->ba[i][get_block][get_info.offset];
1964
1965 rx_osm_handler(nic, rxdp, i, ba);
1966
1967 get_info.offset++;
1968 mac_control->rx_curr_get_info[i].offset =
1969 get_info.offset;
1970 rxdp =
1971 nic->rx_blocks[i][get_block].block_virt_addr +
1972 get_info.offset;
1973
1974 if (get_info.offset &&
1975 (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
1976 get_info.offset = 0;
1977 mac_control->rx_curr_get_info[i].
1978 offset = get_info.offset;
1979 get_block++;
1980 get_block %= nic->block_count[i];
1981 mac_control->rx_curr_get_info[i].
1982 block_index = get_block;
1983 rxdp =
1984 nic->rx_blocks[i][get_block].
1985 block_virt_addr;
1986 }
1987 get_offset =
1988 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
1989 get_info.offset;
1990 pkt_cnt++;
1991 }
1992#endif
1993 } 1884 }
1994 if (!pkt_cnt) 1885 if (!pkt_cnt)
1995 pkt_cnt = 1; 1886 pkt_cnt = 1;
@@ -2009,7 +1900,7 @@ static int s2io_poll(struct net_device *dev, int *budget)
2009 en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS); 1900 en_dis_able_nic_intrs(nic, RX_TRAFFIC_INTR, ENABLE_INTRS);
2010 return 0; 1901 return 0;
2011 1902
2012 no_rx: 1903no_rx:
2013 dev->quota -= pkt_cnt; 1904 dev->quota -= pkt_cnt;
2014 *budget -= pkt_cnt; 1905 *budget -= pkt_cnt;
2015 1906
@@ -2022,277 +1913,213 @@ static int s2io_poll(struct net_device *dev, int *budget)
2022 } 1913 }
2023 return 1; 1914 return 1;
2024} 1915}
2025#else 1916#endif
2026/** 1917
1918/**
2027 * rx_intr_handler - Rx interrupt handler 1919 * rx_intr_handler - Rx interrupt handler
2028 * @nic: device private variable. 1920 * @nic: device private variable.
2029 * Description: 1921 * Description:
2030 * If the interrupt is because of a received frame or if the 1922 * If the interrupt is because of a received frame or if the
2031 * receive ring contains fresh as yet un-processed frames,this function is 1923 * receive ring contains fresh as yet un-processed frames,this function is
2032 * called. It picks out the RxD at which place the last Rx processing had 1924 * called. It picks out the RxD at which place the last Rx processing had
2033 * stopped and sends the skb to the OSM's Rx handler and then increments 1925 * stopped and sends the skb to the OSM's Rx handler and then increments
2034 * the offset. 1926 * the offset.
2035 * Return Value: 1927 * Return Value:
2036 * NONE. 1928 * NONE.
2037 */ 1929 */
2038 1930static void rx_intr_handler(ring_info_t *ring_data)
2039static void rx_intr_handler(struct s2io_nic *nic)
2040{ 1931{
1932 nic_t *nic = ring_data->nic;
2041 struct net_device *dev = (struct net_device *) nic->dev; 1933 struct net_device *dev = (struct net_device *) nic->dev;
2042 XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0; 1934 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1935 int get_block, get_offset, put_block, put_offset, ring_bufs;
2043 rx_curr_get_info_t get_info, put_info; 1936 rx_curr_get_info_t get_info, put_info;
2044 RxD_t *rxdp; 1937 RxD_t *rxdp;
2045 struct sk_buff *skb; 1938 struct sk_buff *skb;
2046#ifndef CONFIG_2BUFF_MODE 1939#ifndef CONFIG_S2IO_NAPI
2047 u16 val16, cksum; 1940 int pkt_cnt = 0;
2048#endif
2049 register u64 val64 = 0;
2050 int get_block, get_offset, put_block, put_offset, ring_bufs;
2051 int i, pkt_cnt = 0;
2052 mac_info_t *mac_control;
2053 struct config_param *config;
2054#ifdef CONFIG_2BUFF_MODE
2055 buffAdd_t *ba;
2056#endif 1941#endif
1942 register u64 val64;
2057 1943
2058 mac_control = &nic->mac_control; 1944 /*
2059 config = &nic->config; 1945 * rx_traffic_int reg is an R1 register, hence we read and write
2060 1946 * back the same value in the register to clear it
2061 /*
2062 * rx_traffic_int reg is an R1 register, hence we read and write back
2063 * the samevalue in the register to clear it.
2064 */ 1947 */
2065 val64 = readq(&bar0->rx_traffic_int); 1948 val64 = readq(&bar0->tx_traffic_int);
2066 writeq(val64, &bar0->rx_traffic_int); 1949 writeq(val64, &bar0->tx_traffic_int);
2067 1950
2068 for (i = 0; i < config->rx_ring_num; i++) { 1951 get_info = ring_data->rx_curr_get_info;
2069 get_info = mac_control->rx_curr_get_info[i]; 1952 get_block = get_info.block_index;
2070 get_block = get_info.block_index; 1953 put_info = ring_data->rx_curr_put_info;
2071 put_info = mac_control->rx_curr_put_info[i]; 1954 put_block = put_info.block_index;
2072 put_block = put_info.block_index; 1955 ring_bufs = get_info.ring_len+1;
2073 ring_bufs = config->rx_cfg[i].num_rxd; 1956 rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
2074 rxdp = nic->rx_blocks[i][get_block].block_virt_addr +
2075 get_info.offset; 1957 get_info.offset;
2076#ifndef CONFIG_2BUFF_MODE 1958 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2077 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) + 1959 get_info.offset;
2078 get_info.offset; 1960#ifndef CONFIG_S2IO_NAPI
2079 spin_lock(&nic->put_lock); 1961 spin_lock(&nic->put_lock);
2080 put_offset = nic->put_pos[i]; 1962 put_offset = ring_data->put_pos;
2081 spin_unlock(&nic->put_lock); 1963 spin_unlock(&nic->put_lock);
2082 while ((!(rxdp->Control_1 & RXD_OWN_XENA)) && 1964#else
2083 (((get_offset + 1) % ring_bufs) != put_offset)) { 1965 put_offset = (put_block * (MAX_RXDS_PER_BLOCK + 1)) +
2084 if (rxdp->Control_1 == END_OF_BLOCK) { 1966 put_info.offset;
2085 rxdp = (RxD_t *) ((unsigned long) 1967#endif
2086 rxdp->Control_2); 1968 while ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
2087 get_info.offset++; 1969#ifdef CONFIG_2BUFF_MODE
2088 get_info.offset %= 1970 (!rxdp->Control_2 & BIT(0)) &&
2089 (MAX_RXDS_PER_BLOCK + 1); 1971#endif
2090 get_block++; 1972 (((get_offset + 1) % ring_bufs) != put_offset)) {
2091 get_block %= nic->block_count[i]; 1973 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2092 mac_control->rx_curr_get_info[i]. 1974 if (skb == NULL) {
2093 offset = get_info.offset; 1975 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2094 mac_control->rx_curr_get_info[i]. 1976 dev->name);
2095 block_index = get_block; 1977 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2096 continue; 1978 return;
2097 }
2098 get_offset =
2099 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2100 get_info.offset;
2101 skb = (struct sk_buff *) ((unsigned long)
2102 rxdp->Host_Control);
2103 if (skb == NULL) {
2104 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2105 dev->name);
2106 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2107 return;
2108 }
2109 val64 = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
2110 val16 = (u16) (val64 >> 48);
2111 cksum = RXD_GET_L4_CKSUM(rxdp->Control_1);
2112 pci_unmap_single(nic->pdev, (dma_addr_t)
2113 rxdp->Buffer0_ptr,
2114 dev->mtu +
2115 HEADER_ETHERNET_II_802_3_SIZE +
2116 HEADER_802_2_SIZE +
2117 HEADER_SNAP_SIZE,
2118 PCI_DMA_FROMDEVICE);
2119 rx_osm_handler(nic, val16, rxdp, i);
2120 get_info.offset++;
2121 get_info.offset %= (MAX_RXDS_PER_BLOCK + 1);
2122 rxdp =
2123 nic->rx_blocks[i][get_block].block_virt_addr +
2124 get_info.offset;
2125 mac_control->rx_curr_get_info[i].offset =
2126 get_info.offset;
2127 pkt_cnt++;
2128 if ((indicate_max_pkts)
2129 && (pkt_cnt > indicate_max_pkts))
2130 break;
2131 } 1979 }
1980#ifndef CONFIG_2BUFF_MODE
1981 pci_unmap_single(nic->pdev, (dma_addr_t)
1982 rxdp->Buffer0_ptr,
1983 dev->mtu +
1984 HEADER_ETHERNET_II_802_3_SIZE +
1985 HEADER_802_2_SIZE +
1986 HEADER_SNAP_SIZE,
1987 PCI_DMA_FROMDEVICE);
2132#else 1988#else
2133 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) + 1989 pci_unmap_single(nic->pdev, (dma_addr_t)
1990 rxdp->Buffer0_ptr,
1991 BUF0_LEN, PCI_DMA_FROMDEVICE);
1992 pci_unmap_single(nic->pdev, (dma_addr_t)
1993 rxdp->Buffer1_ptr,
1994 BUF1_LEN, PCI_DMA_FROMDEVICE);
1995 pci_unmap_single(nic->pdev, (dma_addr_t)
1996 rxdp->Buffer2_ptr,
1997 dev->mtu + BUF0_LEN + 4,
1998 PCI_DMA_FROMDEVICE);
1999#endif
2000 rx_osm_handler(ring_data, rxdp);
2001 get_info.offset++;
2002 ring_data->rx_curr_get_info.offset =
2134 get_info.offset; 2003 get_info.offset;
2135 spin_lock(&nic->put_lock); 2004 rxdp = ring_data->rx_blocks[get_block].block_virt_addr +
2136 put_offset = nic->put_pos[i]; 2005 get_info.offset;
2137 spin_unlock(&nic->put_lock); 2006 if (get_info.offset &&
2138 while (((!(rxdp->Control_1 & RXD_OWN_XENA)) && 2007 (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
2139 !(rxdp->Control_2 & BIT(0))) && 2008 get_info.offset = 0;
2140 (((get_offset + 1) % ring_bufs) != put_offset)) { 2009 ring_data->rx_curr_get_info.offset
2141 skb = (struct sk_buff *) ((unsigned long) 2010 = get_info.offset;
2142 rxdp->Host_Control); 2011 get_block++;
2143 if (skb == NULL) { 2012 get_block %= ring_data->block_count;
2144 DBG_PRINT(ERR_DBG, "%s: The skb is ", 2013 ring_data->rx_curr_get_info.block_index
2145 dev->name); 2014 = get_block;
2146 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n"); 2015 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2147 return; 2016 }
2148 }
2149
2150 pci_unmap_single(nic->pdev, (dma_addr_t)
2151 rxdp->Buffer0_ptr,
2152 BUF0_LEN, PCI_DMA_FROMDEVICE);
2153 pci_unmap_single(nic->pdev, (dma_addr_t)
2154 rxdp->Buffer1_ptr,
2155 BUF1_LEN, PCI_DMA_FROMDEVICE);
2156 pci_unmap_single(nic->pdev, (dma_addr_t)
2157 rxdp->Buffer2_ptr,
2158 dev->mtu + BUF0_LEN + 4,
2159 PCI_DMA_FROMDEVICE);
2160 ba = &nic->ba[i][get_block][get_info.offset];
2161
2162 rx_osm_handler(nic, rxdp, i, ba);
2163
2164 get_info.offset++;
2165 mac_control->rx_curr_get_info[i].offset =
2166 get_info.offset;
2167 rxdp =
2168 nic->rx_blocks[i][get_block].block_virt_addr +
2169 get_info.offset;
2170 2017
2171 if (get_info.offset && 2018 get_offset = (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2172 (!(get_info.offset % MAX_RXDS_PER_BLOCK))) {
2173 get_info.offset = 0;
2174 mac_control->rx_curr_get_info[i].
2175 offset = get_info.offset;
2176 get_block++;
2177 get_block %= nic->block_count[i];
2178 mac_control->rx_curr_get_info[i].
2179 block_index = get_block;
2180 rxdp =
2181 nic->rx_blocks[i][get_block].
2182 block_virt_addr;
2183 }
2184 get_offset =
2185 (get_block * (MAX_RXDS_PER_BLOCK + 1)) +
2186 get_info.offset; 2019 get_info.offset;
2187 pkt_cnt++; 2020#ifdef CONFIG_S2IO_NAPI
2188 if ((indicate_max_pkts) 2021 nic->pkts_to_process -= 1;
2189 && (pkt_cnt > indicate_max_pkts)) 2022 if (!nic->pkts_to_process)
2190 break; 2023 break;
2191 } 2024#else
2192#endif 2025 pkt_cnt++;
2193 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts)) 2026 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2194 break; 2027 break;
2028#endif
2195 } 2029 }
2196} 2030}
2197#endif 2031
2198/** 2032/**
2199 * tx_intr_handler - Transmit interrupt handler 2033 * tx_intr_handler - Transmit interrupt handler
2200 * @nic : device private variable 2034 * @nic : device private variable
2201 * Description: 2035 * Description:
2202 * If an interrupt was raised to indicate DMA complete of the 2036 * If an interrupt was raised to indicate DMA complete of the
2203 * Tx packet, this function is called. It identifies the last TxD 2037 * Tx packet, this function is called. It identifies the last TxD
2204 * whose buffer was freed and frees all skbs whose data have already 2038 * whose buffer was freed and frees all skbs whose data have already
2205 * DMA'ed into the NICs internal memory. 2039 * DMA'ed into the NICs internal memory.
2206 * Return Value: 2040 * Return Value:
2207 * NONE 2041 * NONE
2208 */ 2042 */
2209 2043
2210static void tx_intr_handler(struct s2io_nic *nic) 2044static void tx_intr_handler(fifo_info_t *fifo_data)
2211{ 2045{
2046 nic_t *nic = fifo_data->nic;
2212 XENA_dev_config_t __iomem *bar0 = nic->bar0; 2047 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2213 struct net_device *dev = (struct net_device *) nic->dev; 2048 struct net_device *dev = (struct net_device *) nic->dev;
2214 tx_curr_get_info_t get_info, put_info; 2049 tx_curr_get_info_t get_info, put_info;
2215 struct sk_buff *skb; 2050 struct sk_buff *skb;
2216 TxD_t *txdlp; 2051 TxD_t *txdlp;
2217 register u64 val64 = 0;
2218 int i;
2219 u16 j, frg_cnt; 2052 u16 j, frg_cnt;
2220 mac_info_t *mac_control; 2053 register u64 val64 = 0;
2221 struct config_param *config;
2222
2223 mac_control = &nic->mac_control;
2224 config = &nic->config;
2225 2054
2226 /* 2055 /*
2227 * tx_traffic_int reg is an R1 register, hence we read and write 2056 * tx_traffic_int reg is an R1 register, hence we read and write
2228 * back the samevalue in the register to clear it. 2057 * back the same value in the register to clear it
2229 */ 2058 */
2230 val64 = readq(&bar0->tx_traffic_int); 2059 val64 = readq(&bar0->tx_traffic_int);
2231 writeq(val64, &bar0->tx_traffic_int); 2060 writeq(val64, &bar0->tx_traffic_int);
2232 2061
2233 for (i = 0; i < config->tx_fifo_num; i++) { 2062 get_info = fifo_data->tx_curr_get_info;
2234 get_info = mac_control->tx_curr_get_info[i]; 2063 put_info = fifo_data->tx_curr_put_info;
2235 put_info = mac_control->tx_curr_put_info[i]; 2064 txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2236 txdlp = (TxD_t *) nic->list_info[i][get_info.offset]. 2065 list_virt_addr;
2237 list_virt_addr; 2066 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2238 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) && 2067 (get_info.offset != put_info.offset) &&
2239 (get_info.offset != put_info.offset) && 2068 (txdlp->Host_Control)) {
2240 (txdlp->Host_Control)) { 2069 /* Check for TxD errors */
2241 /* Check for TxD errors */ 2070 if (txdlp->Control_1 & TXD_T_CODE) {
2242 if (txdlp->Control_1 & TXD_T_CODE) { 2071 unsigned long long err;
2243 unsigned long long err; 2072 err = txdlp->Control_1 & TXD_T_CODE;
2244 err = txdlp->Control_1 & TXD_T_CODE; 2073 DBG_PRINT(ERR_DBG, "***TxD error %llx\n",
2245 DBG_PRINT(ERR_DBG, "***TxD error %llx\n", 2074 err);
2246 err); 2075 }
2247 }
2248 2076
2249 skb = (struct sk_buff *) ((unsigned long) 2077 skb = (struct sk_buff *) ((unsigned long)
2250 txdlp->Host_Control); 2078 txdlp->Host_Control);
2251 if (skb == NULL) { 2079 if (skb == NULL) {
2252 DBG_PRINT(ERR_DBG, "%s: Null skb ", 2080 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2253 dev->name); 2081 __FUNCTION__);
2254 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n"); 2082 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2255 return; 2083 return;
2256 } 2084 }
2257 nic->tx_pkt_count++; 2085
2258 2086 frg_cnt = skb_shinfo(skb)->nr_frags;
2259 frg_cnt = skb_shinfo(skb)->nr_frags; 2087 nic->tx_pkt_count++;
2260 2088
2261 /* For unfragmented skb */ 2089 pci_unmap_single(nic->pdev, (dma_addr_t)
2262 pci_unmap_single(nic->pdev, (dma_addr_t) 2090 txdlp->Buffer_Pointer,
2263 txdlp->Buffer_Pointer, 2091 skb->len - skb->data_len,
2264 skb->len - skb->data_len, 2092 PCI_DMA_TODEVICE);
2265 PCI_DMA_TODEVICE); 2093 if (frg_cnt) {
2266 if (frg_cnt) { 2094 TxD_t *temp;
2267 TxD_t *temp = txdlp; 2095 temp = txdlp;
2268 txdlp++; 2096 txdlp++;
2269 for (j = 0; j < frg_cnt; j++, txdlp++) { 2097 for (j = 0; j < frg_cnt; j++, txdlp++) {
2270 skb_frag_t *frag = 2098 skb_frag_t *frag =
2271 &skb_shinfo(skb)->frags[j]; 2099 &skb_shinfo(skb)->frags[j];
2272 pci_unmap_page(nic->pdev, 2100 pci_unmap_page(nic->pdev,
2273 (dma_addr_t) 2101 (dma_addr_t)
2274 txdlp-> 2102 txdlp->
2275 Buffer_Pointer, 2103 Buffer_Pointer,
2276 frag->size, 2104 frag->size,
2277 PCI_DMA_TODEVICE); 2105 PCI_DMA_TODEVICE);
2278 }
2279 txdlp = temp;
2280 } 2106 }
2281 memset(txdlp, 0, 2107 txdlp = temp;
2282 (sizeof(TxD_t) * config->max_txds));
2283
2284 /* Updating the statistics block */
2285 nic->stats.tx_packets++;
2286 nic->stats.tx_bytes += skb->len;
2287 dev_kfree_skb_irq(skb);
2288
2289 get_info.offset++;
2290 get_info.offset %= get_info.fifo_len + 1;
2291 txdlp = (TxD_t *) nic->list_info[i]
2292 [get_info.offset].list_virt_addr;
2293 mac_control->tx_curr_get_info[i].offset =
2294 get_info.offset;
2295 } 2108 }
2109 memset(txdlp, 0,
2110 (sizeof(TxD_t) * fifo_data->max_txds));
2111
2112 /* Updating the statistics block */
2113 nic->stats.tx_packets++;
2114 nic->stats.tx_bytes += skb->len;
2115 dev_kfree_skb_irq(skb);
2116
2117 get_info.offset++;
2118 get_info.offset %= get_info.fifo_len + 1;
2119 txdlp = (TxD_t *) fifo_data->list_info
2120 [get_info.offset].list_virt_addr;
2121 fifo_data->tx_curr_get_info.offset =
2122 get_info.offset;
2296 } 2123 }
2297 2124
2298 spin_lock(&nic->tx_lock); 2125 spin_lock(&nic->tx_lock);
@@ -2301,13 +2128,13 @@ static void tx_intr_handler(struct s2io_nic *nic)
2301 spin_unlock(&nic->tx_lock); 2128 spin_unlock(&nic->tx_lock);
2302} 2129}
2303 2130
2304/** 2131/**
2305 * alarm_intr_handler - Alarm Interrrupt handler 2132 * alarm_intr_handler - Alarm Interrrupt handler
2306 * @nic: device private variable 2133 * @nic: device private variable
2307 * Description: If the interrupt was neither because of Rx packet or Tx 2134 * Description: If the interrupt was neither because of Rx packet or Tx
2308 * complete, this function is called. If the interrupt was to indicate 2135 * complete, this function is called. If the interrupt was to indicate
2309 * a loss of link, the OSM link status handler is invoked for any other 2136 * a loss of link, the OSM link status handler is invoked for any other
2310 * alarm interrupt the block that raised the interrupt is displayed 2137 * alarm interrupt the block that raised the interrupt is displayed
2311 * and a H/W reset is issued. 2138 * and a H/W reset is issued.
2312 * Return Value: 2139 * Return Value:
2313 * NONE 2140 * NONE
@@ -2338,7 +2165,7 @@ static void alarm_intr_handler(struct s2io_nic *nic)
2338 /* 2165 /*
2339 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC 2166 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
2340 * Error occurs, the adapter will be recycled by disabling the 2167 * Error occurs, the adapter will be recycled by disabling the
2341 * adapter enable bit and enabling it again after the device 2168 * adapter enable bit and enabling it again after the device
2342 * becomes Quiescent. 2169 * becomes Quiescent.
2343 */ 2170 */
2344 val64 = readq(&bar0->pcc_err_reg); 2171 val64 = readq(&bar0->pcc_err_reg);
@@ -2354,18 +2181,18 @@ static void alarm_intr_handler(struct s2io_nic *nic)
2354 /* Other type of interrupts are not being handled now, TODO */ 2181 /* Other type of interrupts are not being handled now, TODO */
2355} 2182}
2356 2183
2357/** 2184/**
2358 * wait_for_cmd_complete - waits for a command to complete. 2185 * wait_for_cmd_complete - waits for a command to complete.
2359 * @sp : private member of the device structure, which is a pointer to the 2186 * @sp : private member of the device structure, which is a pointer to the
2360 * s2io_nic structure. 2187 * s2io_nic structure.
2361 * Description: Function that waits for a command to Write into RMAC 2188 * Description: Function that waits for a command to Write into RMAC
2362 * ADDR DATA registers to be completed and returns either success or 2189 * ADDR DATA registers to be completed and returns either success or
2363 * error depending on whether the command was complete or not. 2190 * error depending on whether the command was complete or not.
2364 * Return value: 2191 * Return value:
2365 * SUCCESS on success and FAILURE on failure. 2192 * SUCCESS on success and FAILURE on failure.
2366 */ 2193 */
2367 2194
2368static int wait_for_cmd_complete(nic_t * sp) 2195int wait_for_cmd_complete(nic_t * sp)
2369{ 2196{
2370 XENA_dev_config_t __iomem *bar0 = sp->bar0; 2197 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2371 int ret = FAILURE, cnt = 0; 2198 int ret = FAILURE, cnt = 0;
@@ -2385,17 +2212,17 @@ static int wait_for_cmd_complete(nic_t * sp)
2385 return ret; 2212 return ret;
2386} 2213}
2387 2214
2388/** 2215/**
2389 * s2io_reset - Resets the card. 2216 * s2io_reset - Resets the card.
2390 * @sp : private member of the device structure. 2217 * @sp : private member of the device structure.
2391 * Description: Function to Reset the card. This function then also 2218 * Description: Function to Reset the card. This function then also
2392 * restores the previously saved PCI configuration space registers as 2219 * restores the previously saved PCI configuration space registers as
2393 * the card reset also resets the configuration space. 2220 * the card reset also resets the configuration space.
2394 * Return value: 2221 * Return value:
2395 * void. 2222 * void.
2396 */ 2223 */
2397 2224
2398static void s2io_reset(nic_t * sp) 2225void s2io_reset(nic_t * sp)
2399{ 2226{
2400 XENA_dev_config_t __iomem *bar0 = sp->bar0; 2227 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2401 u64 val64; 2228 u64 val64;
@@ -2404,10 +2231,10 @@ static void s2io_reset(nic_t * sp)
2404 val64 = SW_RESET_ALL; 2231 val64 = SW_RESET_ALL;
2405 writeq(val64, &bar0->sw_reset); 2232 writeq(val64, &bar0->sw_reset);
2406 2233
2407 /* 2234 /*
2408 * At this stage, if the PCI write is indeed completed, the 2235 * At this stage, if the PCI write is indeed completed, the
2409 * card is reset and so is the PCI Config space of the device. 2236 * card is reset and so is the PCI Config space of the device.
2410 * So a read cannot be issued at this stage on any of the 2237 * So a read cannot be issued at this stage on any of the
2411 * registers to ensure the write into "sw_reset" register 2238 * registers to ensure the write into "sw_reset" register
2412 * has gone through. 2239 * has gone through.
2413 * Question: Is there any system call that will explicitly force 2240 * Question: Is there any system call that will explicitly force
@@ -2420,10 +2247,17 @@ static void s2io_reset(nic_t * sp)
2420 2247
2421 /* Restore the PCI state saved during initializarion. */ 2248 /* Restore the PCI state saved during initializarion. */
2422 pci_restore_state(sp->pdev); 2249 pci_restore_state(sp->pdev);
2250
2423 s2io_init_pci(sp); 2251 s2io_init_pci(sp);
2424 2252
2425 msleep(250); 2253 msleep(250);
2426 2254
2255 /* Set swapper to enable I/O register access */
2256 s2io_set_swapper(sp);
2257
2258 /* Reset device statistics maintained by OS */
2259 memset(&sp->stats, 0, sizeof (struct net_device_stats));
2260
2427 /* SXE-002: Configure link and activity LED to turn it off */ 2261 /* SXE-002: Configure link and activity LED to turn it off */
2428 subid = sp->pdev->subsystem_device; 2262 subid = sp->pdev->subsystem_device;
2429 if ((subid & 0xFF) >= 0x07) { 2263 if ((subid & 0xFF) >= 0x07) {
@@ -2431,29 +2265,29 @@ static void s2io_reset(nic_t * sp)
2431 val64 |= 0x0000800000000000ULL; 2265 val64 |= 0x0000800000000000ULL;
2432 writeq(val64, &bar0->gpio_control); 2266 writeq(val64, &bar0->gpio_control);
2433 val64 = 0x0411040400000000ULL; 2267 val64 = 0x0411040400000000ULL;
2434 writeq(val64, (void __iomem *) bar0 + 0x2700); 2268 writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));
2435 } 2269 }
2436 2270
2437 sp->device_enabled_once = FALSE; 2271 sp->device_enabled_once = FALSE;
2438} 2272}
2439 2273
2440/** 2274/**
2441 * s2io_set_swapper - to set the swapper controle on the card 2275 * s2io_set_swapper - to set the swapper controle on the card
2442 * @sp : private member of the device structure, 2276 * @sp : private member of the device structure,
2443 * pointer to the s2io_nic structure. 2277 * pointer to the s2io_nic structure.
2444 * Description: Function to set the swapper control on the card 2278 * Description: Function to set the swapper control on the card
2445 * correctly depending on the 'endianness' of the system. 2279 * correctly depending on the 'endianness' of the system.
2446 * Return value: 2280 * Return value:
2447 * SUCCESS on success and FAILURE on failure. 2281 * SUCCESS on success and FAILURE on failure.
2448 */ 2282 */
2449 2283
2450static int s2io_set_swapper(nic_t * sp) 2284int s2io_set_swapper(nic_t * sp)
2451{ 2285{
2452 struct net_device *dev = sp->dev; 2286 struct net_device *dev = sp->dev;
2453 XENA_dev_config_t __iomem *bar0 = sp->bar0; 2287 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2454 u64 val64, valt, valr; 2288 u64 val64, valt, valr;
2455 2289
2456 /* 2290 /*
2457 * Set proper endian settings and verify the same by reading 2291 * Set proper endian settings and verify the same by reading
2458 * the PIF Feed-back register. 2292 * the PIF Feed-back register.
2459 */ 2293 */
@@ -2505,8 +2339,9 @@ static int s2io_set_swapper(nic_t * sp)
2505 i++; 2339 i++;
2506 } 2340 }
2507 if(i == 4) { 2341 if(i == 4) {
2342 unsigned long long x = val64;
2508 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr "); 2343 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
2509 DBG_PRINT(ERR_DBG, "reads:0x%llx\n",val64); 2344 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
2510 return FAILURE; 2345 return FAILURE;
2511 } 2346 }
2512 } 2347 }
@@ -2514,8 +2349,8 @@ static int s2io_set_swapper(nic_t * sp)
2514 val64 &= 0xFFFF000000000000ULL; 2349 val64 &= 0xFFFF000000000000ULL;
2515 2350
2516#ifdef __BIG_ENDIAN 2351#ifdef __BIG_ENDIAN
2517 /* 2352 /*
2518 * The device by default set to a big endian format, so a 2353 * The device by default set to a big endian format, so a
2519 * big endian driver need not set anything. 2354 * big endian driver need not set anything.
2520 */ 2355 */
2521 val64 |= (SWAPPER_CTRL_TXP_FE | 2356 val64 |= (SWAPPER_CTRL_TXP_FE |
@@ -2531,9 +2366,9 @@ static int s2io_set_swapper(nic_t * sp)
2531 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE); 2366 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
2532 writeq(val64, &bar0->swapper_ctrl); 2367 writeq(val64, &bar0->swapper_ctrl);
2533#else 2368#else
2534 /* 2369 /*
2535 * Initially we enable all bits to make it accessible by the 2370 * Initially we enable all bits to make it accessible by the
2536 * driver, then we selectively enable only those bits that 2371 * driver, then we selectively enable only those bits that
2537 * we want to set. 2372 * we want to set.
2538 */ 2373 */
2539 val64 |= (SWAPPER_CTRL_TXP_FE | 2374 val64 |= (SWAPPER_CTRL_TXP_FE |
@@ -2555,8 +2390,8 @@ static int s2io_set_swapper(nic_t * sp)
2555#endif 2390#endif
2556 val64 = readq(&bar0->swapper_ctrl); 2391 val64 = readq(&bar0->swapper_ctrl);
2557 2392
2558 /* 2393 /*
2559 * Verifying if endian settings are accurate by reading a 2394 * Verifying if endian settings are accurate by reading a
2560 * feedback register. 2395 * feedback register.
2561 */ 2396 */
2562 val64 = readq(&bar0->pif_rd_swapper_fb); 2397 val64 = readq(&bar0->pif_rd_swapper_fb);
@@ -2576,25 +2411,25 @@ static int s2io_set_swapper(nic_t * sp)
2576 * Functions defined below concern the OS part of the driver * 2411 * Functions defined below concern the OS part of the driver *
2577 * ********************************************************* */ 2412 * ********************************************************* */
2578 2413
2579/** 2414/**
2580 * s2io_open - open entry point of the driver 2415 * s2io_open - open entry point of the driver
2581 * @dev : pointer to the device structure. 2416 * @dev : pointer to the device structure.
2582 * Description: 2417 * Description:
2583 * This function is the open entry point of the driver. It mainly calls a 2418 * This function is the open entry point of the driver. It mainly calls a
2584 * function to allocate Rx buffers and inserts them into the buffer 2419 * function to allocate Rx buffers and inserts them into the buffer
2585 * descriptors and then enables the Rx part of the NIC. 2420 * descriptors and then enables the Rx part of the NIC.
2586 * Return value: 2421 * Return value:
2587 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2422 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2588 * file on failure. 2423 * file on failure.
2589 */ 2424 */
2590 2425
2591static int s2io_open(struct net_device *dev) 2426int s2io_open(struct net_device *dev)
2592{ 2427{
2593 nic_t *sp = dev->priv; 2428 nic_t *sp = dev->priv;
2594 int err = 0; 2429 int err = 0;
2595 2430
2596 /* 2431 /*
2597 * Make sure you have link off by default every time 2432 * Make sure you have link off by default every time
2598 * Nic is initialized 2433 * Nic is initialized
2599 */ 2434 */
2600 netif_carrier_off(dev); 2435 netif_carrier_off(dev);
@@ -2604,27 +2439,34 @@ static int s2io_open(struct net_device *dev)
2604 if (s2io_card_up(sp)) { 2439 if (s2io_card_up(sp)) {
2605 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", 2440 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
2606 dev->name); 2441 dev->name);
2607 return -ENODEV; 2442 err = -ENODEV;
2443 goto hw_init_failed;
2608 } 2444 }
2609 2445
2610 /* After proper initialization of H/W, register ISR */ 2446 /* After proper initialization of H/W, register ISR */
2611 err = request_irq((int) sp->irq, s2io_isr, SA_SHIRQ, 2447 err = request_irq((int) sp->pdev->irq, s2io_isr, SA_SHIRQ,
2612 sp->name, dev); 2448 sp->name, dev);
2613 if (err) { 2449 if (err) {
2614 s2io_reset(sp);
2615 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n", 2450 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
2616 dev->name); 2451 dev->name);
2617 return err; 2452 goto isr_registration_failed;
2618 } 2453 }
2619 2454
2620 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) { 2455 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
2621 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n"); 2456 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
2622 s2io_reset(sp); 2457 err = -ENODEV;
2623 return -ENODEV; 2458 goto setting_mac_address_failed;
2624 } 2459 }
2625 2460
2626 netif_start_queue(dev); 2461 netif_start_queue(dev);
2627 return 0; 2462 return 0;
2463
2464setting_mac_address_failed:
2465 free_irq(sp->pdev->irq, dev);
2466isr_registration_failed:
2467 s2io_reset(sp);
2468hw_init_failed:
2469 return err;
2628} 2470}
2629 2471
2630/** 2472/**
@@ -2640,16 +2482,15 @@ static int s2io_open(struct net_device *dev)
2640 * file on failure. 2482 * file on failure.
2641 */ 2483 */
2642 2484
2643static int s2io_close(struct net_device *dev) 2485int s2io_close(struct net_device *dev)
2644{ 2486{
2645 nic_t *sp = dev->priv; 2487 nic_t *sp = dev->priv;
2646
2647 flush_scheduled_work(); 2488 flush_scheduled_work();
2648 netif_stop_queue(dev); 2489 netif_stop_queue(dev);
2649 /* Reset card, kill tasklet and free Tx and Rx buffers. */ 2490 /* Reset card, kill tasklet and free Tx and Rx buffers. */
2650 s2io_card_down(sp); 2491 s2io_card_down(sp);
2651 2492
2652 free_irq(dev->irq, dev); 2493 free_irq(sp->pdev->irq, dev);
2653 sp->device_close_flag = TRUE; /* Device is shut down. */ 2494 sp->device_close_flag = TRUE; /* Device is shut down. */
2654 return 0; 2495 return 0;
2655} 2496}
@@ -2667,7 +2508,7 @@ static int s2io_close(struct net_device *dev)
2667 * 0 on success & 1 on failure. 2508 * 0 on success & 1 on failure.
2668 */ 2509 */
2669 2510
2670static int s2io_xmit(struct sk_buff *skb, struct net_device *dev) 2511int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2671{ 2512{
2672 nic_t *sp = dev->priv; 2513 nic_t *sp = dev->priv;
2673 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off; 2514 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
@@ -2685,22 +2526,24 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2685 mac_control = &sp->mac_control; 2526 mac_control = &sp->mac_control;
2686 config = &sp->config; 2527 config = &sp->config;
2687 2528
2688 DBG_PRINT(TX_DBG, "%s: In S2IO Tx routine\n", dev->name); 2529 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
2689 spin_lock_irqsave(&sp->tx_lock, flags); 2530 spin_lock_irqsave(&sp->tx_lock, flags);
2690
2691 if (atomic_read(&sp->card_state) == CARD_DOWN) { 2531 if (atomic_read(&sp->card_state) == CARD_DOWN) {
2692 DBG_PRINT(ERR_DBG, "%s: Card going down for reset\n", 2532 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
2693 dev->name); 2533 dev->name);
2694 spin_unlock_irqrestore(&sp->tx_lock, flags); 2534 spin_unlock_irqrestore(&sp->tx_lock, flags);
2695 return 1; 2535 dev_kfree_skb(skb);
2536 return 0;
2696 } 2537 }
2697 2538
2698 queue = 0; 2539 queue = 0;
2699 put_off = (u16) mac_control->tx_curr_put_info[queue].offset;
2700 get_off = (u16) mac_control->tx_curr_get_info[queue].offset;
2701 txdp = (TxD_t *) sp->list_info[queue][put_off].list_virt_addr;
2702 2540
2703 queue_len = mac_control->tx_curr_put_info[queue].fifo_len + 1; 2541 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
2542 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
2543 txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
2544 list_virt_addr;
2545
2546 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
2704 /* Avoid "put" pointer going beyond "get" pointer */ 2547 /* Avoid "put" pointer going beyond "get" pointer */
2705 if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) { 2548 if (txdp->Host_Control || (((put_off + 1) % queue_len) == get_off)) {
2706 DBG_PRINT(ERR_DBG, "Error in xmit, No free TXDs.\n"); 2549 DBG_PRINT(ERR_DBG, "Error in xmit, No free TXDs.\n");
@@ -2720,9 +2563,9 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2720 frg_cnt = skb_shinfo(skb)->nr_frags; 2563 frg_cnt = skb_shinfo(skb)->nr_frags;
2721 frg_len = skb->len - skb->data_len; 2564 frg_len = skb->len - skb->data_len;
2722 2565
2723 txdp->Host_Control = (unsigned long) skb;
2724 txdp->Buffer_Pointer = pci_map_single 2566 txdp->Buffer_Pointer = pci_map_single
2725 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE); 2567 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
2568 txdp->Host_Control = (unsigned long) skb;
2726 if (skb->ip_summed == CHECKSUM_HW) { 2569 if (skb->ip_summed == CHECKSUM_HW) {
2727 txdp->Control_2 |= 2570 txdp->Control_2 |=
2728 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN | 2571 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
@@ -2747,11 +2590,12 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2747 txdp->Control_1 |= TXD_GATHER_CODE_LAST; 2590 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
2748 2591
2749 tx_fifo = mac_control->tx_FIFO_start[queue]; 2592 tx_fifo = mac_control->tx_FIFO_start[queue];
2750 val64 = sp->list_info[queue][put_off].list_phy_addr; 2593 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
2751 writeq(val64, &tx_fifo->TxDL_Pointer); 2594 writeq(val64, &tx_fifo->TxDL_Pointer);
2752 2595
2753 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | 2596 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
2754 TX_FIFO_LAST_LIST); 2597 TX_FIFO_LAST_LIST);
2598
2755#ifdef NETIF_F_TSO 2599#ifdef NETIF_F_TSO
2756 if (mss) 2600 if (mss)
2757 val64 |= TX_FIFO_SPECIAL_FUNC; 2601 val64 |= TX_FIFO_SPECIAL_FUNC;
@@ -2762,8 +2606,8 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2762 val64 = readq(&bar0->general_int_status); 2606 val64 = readq(&bar0->general_int_status);
2763 2607
2764 put_off++; 2608 put_off++;
2765 put_off %= mac_control->tx_curr_put_info[queue].fifo_len + 1; 2609 put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
2766 mac_control->tx_curr_put_info[queue].offset = put_off; 2610 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
2767 2611
2768 /* Avoid "put" pointer going beyond "get" pointer */ 2612 /* Avoid "put" pointer going beyond "get" pointer */
2769 if (((put_off + 1) % queue_len) == get_off) { 2613 if (((put_off + 1) % queue_len) == get_off) {
@@ -2784,13 +2628,13 @@ static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
2784 * @irq: the irq of the device. 2628 * @irq: the irq of the device.
2785 * @dev_id: a void pointer to the dev structure of the NIC. 2629 * @dev_id: a void pointer to the dev structure of the NIC.
2786 * @pt_regs: pointer to the registers pushed on the stack. 2630 * @pt_regs: pointer to the registers pushed on the stack.
2787 * Description: This function is the ISR handler of the device. It 2631 * Description: This function is the ISR handler of the device. It
2788 * identifies the reason for the interrupt and calls the relevant 2632 * identifies the reason for the interrupt and calls the relevant
2789 * service routines. As a contongency measure, this ISR allocates the 2633 * service routines. As a contongency measure, this ISR allocates the
2790 * recv buffers, if their numbers are below the panic value which is 2634 * recv buffers, if their numbers are below the panic value which is
2791 * presently set to 25% of the original number of rcv buffers allocated. 2635 * presently set to 25% of the original number of rcv buffers allocated.
2792 * Return value: 2636 * Return value:
2793 * IRQ_HANDLED: will be returned if IRQ was handled by this routine 2637 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
2794 * IRQ_NONE: will be returned if interrupt is not from our device 2638 * IRQ_NONE: will be returned if interrupt is not from our device
2795 */ 2639 */
2796static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs) 2640static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
@@ -2798,9 +2642,7 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
2798 struct net_device *dev = (struct net_device *) dev_id; 2642 struct net_device *dev = (struct net_device *) dev_id;
2799 nic_t *sp = dev->priv; 2643 nic_t *sp = dev->priv;
2800 XENA_dev_config_t __iomem *bar0 = sp->bar0; 2644 XENA_dev_config_t __iomem *bar0 = sp->bar0;
2801#ifndef CONFIG_S2IO_NAPI 2645 int i;
2802 int i, ret;
2803#endif
2804 u64 reason = 0; 2646 u64 reason = 0;
2805 mac_info_t *mac_control; 2647 mac_info_t *mac_control;
2806 struct config_param *config; 2648 struct config_param *config;
@@ -2808,13 +2650,13 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
2808 mac_control = &sp->mac_control; 2650 mac_control = &sp->mac_control;
2809 config = &sp->config; 2651 config = &sp->config;
2810 2652
2811 /* 2653 /*
2812 * Identify the cause for interrupt and call the appropriate 2654 * Identify the cause for interrupt and call the appropriate
2813 * interrupt handler. Causes for the interrupt could be; 2655 * interrupt handler. Causes for the interrupt could be;
2814 * 1. Rx of packet. 2656 * 1. Rx of packet.
2815 * 2. Tx complete. 2657 * 2. Tx complete.
2816 * 3. Link down. 2658 * 3. Link down.
2817 * 4. Error in any functional blocks of the NIC. 2659 * 4. Error in any functional blocks of the NIC.
2818 */ 2660 */
2819 reason = readq(&bar0->general_int_status); 2661 reason = readq(&bar0->general_int_status);
2820 2662
@@ -2823,12 +2665,6 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
2823 return IRQ_NONE; 2665 return IRQ_NONE;
2824 } 2666 }
2825 2667
2826 /* If Intr is because of Tx Traffic */
2827 if (reason & GEN_INTR_TXTRAFFIC) {
2828 tx_intr_handler(sp);
2829 }
2830
2831 /* If Intr is because of an error */
2832 if (reason & (GEN_ERROR_INTR)) 2668 if (reason & (GEN_ERROR_INTR))
2833 alarm_intr_handler(sp); 2669 alarm_intr_handler(sp);
2834 2670
@@ -2843,17 +2679,26 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
2843#else 2679#else
2844 /* If Intr is because of Rx Traffic */ 2680 /* If Intr is because of Rx Traffic */
2845 if (reason & GEN_INTR_RXTRAFFIC) { 2681 if (reason & GEN_INTR_RXTRAFFIC) {
2846 rx_intr_handler(sp); 2682 for (i = 0; i < config->rx_ring_num; i++) {
2683 rx_intr_handler(&mac_control->rings[i]);
2684 }
2847 } 2685 }
2848#endif 2686#endif
2849 2687
2850 /* 2688 /* If Intr is because of Tx Traffic */
2851 * If the Rx buffer count is below the panic threshold then 2689 if (reason & GEN_INTR_TXTRAFFIC) {
2852 * reallocate the buffers from the interrupt handler itself, 2690 for (i = 0; i < config->tx_fifo_num; i++)
2691 tx_intr_handler(&mac_control->fifos[i]);
2692 }
2693
2694 /*
2695 * If the Rx buffer count is below the panic threshold then
2696 * reallocate the buffers from the interrupt handler itself,
2853 * else schedule a tasklet to reallocate the buffers. 2697 * else schedule a tasklet to reallocate the buffers.
2854 */ 2698 */
2855#ifndef CONFIG_S2IO_NAPI 2699#ifndef CONFIG_S2IO_NAPI
2856 for (i = 0; i < config->rx_ring_num; i++) { 2700 for (i = 0; i < config->rx_ring_num; i++) {
2701 int ret;
2857 int rxb_size = atomic_read(&sp->rx_bufs_left[i]); 2702 int rxb_size = atomic_read(&sp->rx_bufs_left[i]);
2858 int level = rx_buffer_level(sp, rxb_size, i); 2703 int level = rx_buffer_level(sp, rxb_size, i);
2859 2704
@@ -2878,29 +2723,33 @@ static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
2878} 2723}
2879 2724
2880/** 2725/**
2881 * s2io_get_stats - Updates the device statistics structure. 2726 * s2io_get_stats - Updates the device statistics structure.
2882 * @dev : pointer to the device structure. 2727 * @dev : pointer to the device structure.
2883 * Description: 2728 * Description:
2884 * This function updates the device statistics structure in the s2io_nic 2729 * This function updates the device statistics structure in the s2io_nic
2885 * structure and returns a pointer to the same. 2730 * structure and returns a pointer to the same.
2886 * Return value: 2731 * Return value:
2887 * pointer to the updated net_device_stats structure. 2732 * pointer to the updated net_device_stats structure.
2888 */ 2733 */
2889 2734
2890static struct net_device_stats *s2io_get_stats(struct net_device *dev) 2735struct net_device_stats *s2io_get_stats(struct net_device *dev)
2891{ 2736{
2892 nic_t *sp = dev->priv; 2737 nic_t *sp = dev->priv;
2893 mac_info_t *mac_control; 2738 mac_info_t *mac_control;
2894 struct config_param *config; 2739 struct config_param *config;
2895 2740
2741
2896 mac_control = &sp->mac_control; 2742 mac_control = &sp->mac_control;
2897 config = &sp->config; 2743 config = &sp->config;
2898 2744
2899 sp->stats.tx_errors = mac_control->stats_info->tmac_any_err_frms; 2745 sp->stats.tx_errors =
2900 sp->stats.rx_errors = mac_control->stats_info->rmac_drop_frms; 2746 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
2901 sp->stats.multicast = mac_control->stats_info->rmac_vld_mcst_frms; 2747 sp->stats.rx_errors =
2748 le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
2749 sp->stats.multicast =
2750 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
2902 sp->stats.rx_length_errors = 2751 sp->stats.rx_length_errors =
2903 mac_control->stats_info->rmac_long_frms; 2752 le32_to_cpu(mac_control->stats_info->rmac_long_frms);
2904 2753
2905 return (&sp->stats); 2754 return (&sp->stats);
2906} 2755}
@@ -2909,8 +2758,8 @@ static struct net_device_stats *s2io_get_stats(struct net_device *dev)
2909 * s2io_set_multicast - entry point for multicast address enable/disable. 2758 * s2io_set_multicast - entry point for multicast address enable/disable.
2910 * @dev : pointer to the device structure 2759 * @dev : pointer to the device structure
2911 * Description: 2760 * Description:
2912 * This function is a driver entry point which gets called by the kernel 2761 * This function is a driver entry point which gets called by the kernel
2913 * whenever multicast addresses must be enabled/disabled. This also gets 2762 * whenever multicast addresses must be enabled/disabled. This also gets
2914 * called to set/reset promiscuous mode. Depending on the deivce flag, we 2763 * called to set/reset promiscuous mode. Depending on the deivce flag, we
2915 * determine, if multicast address must be enabled or if promiscuous mode 2764 * determine, if multicast address must be enabled or if promiscuous mode
2916 * is to be disabled etc. 2765 * is to be disabled etc.
@@ -3010,7 +2859,7 @@ static void s2io_set_multicast(struct net_device *dev)
3010 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), 2859 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
3011 &bar0->rmac_addr_data0_mem); 2860 &bar0->rmac_addr_data0_mem);
3012 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), 2861 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
3013 &bar0->rmac_addr_data1_mem); 2862 &bar0->rmac_addr_data1_mem);
3014 val64 = RMAC_ADDR_CMD_MEM_WE | 2863 val64 = RMAC_ADDR_CMD_MEM_WE |
3015 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | 2864 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3016 RMAC_ADDR_CMD_MEM_OFFSET 2865 RMAC_ADDR_CMD_MEM_OFFSET
@@ -3039,8 +2888,7 @@ static void s2io_set_multicast(struct net_device *dev)
3039 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr), 2888 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
3040 &bar0->rmac_addr_data0_mem); 2889 &bar0->rmac_addr_data0_mem);
3041 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), 2890 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
3042 &bar0->rmac_addr_data1_mem); 2891 &bar0->rmac_addr_data1_mem);
3043
3044 val64 = RMAC_ADDR_CMD_MEM_WE | 2892 val64 = RMAC_ADDR_CMD_MEM_WE |
3045 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | 2893 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
3046 RMAC_ADDR_CMD_MEM_OFFSET 2894 RMAC_ADDR_CMD_MEM_OFFSET
@@ -3059,12 +2907,12 @@ static void s2io_set_multicast(struct net_device *dev)
3059} 2907}
3060 2908
3061/** 2909/**
3062 * s2io_set_mac_addr - Programs the Xframe mac address 2910 * s2io_set_mac_addr - Programs the Xframe mac address
3063 * @dev : pointer to the device structure. 2911 * @dev : pointer to the device structure.
3064 * @addr: a uchar pointer to the new mac address which is to be set. 2912 * @addr: a uchar pointer to the new mac address which is to be set.
3065 * Description : This procedure will program the Xframe to receive 2913 * Description : This procedure will program the Xframe to receive
3066 * frames with new Mac Address 2914 * frames with new Mac Address
3067 * Return value: SUCCESS on success and an appropriate (-)ve integer 2915 * Return value: SUCCESS on success and an appropriate (-)ve integer
3068 * as defined in errno.h file on failure. 2916 * as defined in errno.h file on failure.
3069 */ 2917 */
3070 2918
@@ -3075,10 +2923,10 @@ int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
3075 register u64 val64, mac_addr = 0; 2923 register u64 val64, mac_addr = 0;
3076 int i; 2924 int i;
3077 2925
3078 /* 2926 /*
3079 * Set the new MAC address as the new unicast filter and reflect this 2927 * Set the new MAC address as the new unicast filter and reflect this
3080 * change on the device address registered with the OS. It will be 2928 * change on the device address registered with the OS. It will be
3081 * at offset 0. 2929 * at offset 0.
3082 */ 2930 */
3083 for (i = 0; i < ETH_ALEN; i++) { 2931 for (i = 0; i < ETH_ALEN; i++) {
3084 mac_addr <<= 8; 2932 mac_addr <<= 8;
@@ -3102,12 +2950,12 @@ int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
3102} 2950}
3103 2951
3104/** 2952/**
3105 * s2io_ethtool_sset - Sets different link parameters. 2953 * s2io_ethtool_sset - Sets different link parameters.
3106 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. 2954 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
3107 * @info: pointer to the structure with parameters given by ethtool to set 2955 * @info: pointer to the structure with parameters given by ethtool to set
3108 * link information. 2956 * link information.
3109 * Description: 2957 * Description:
3110 * The function sets different link parameters provided by the user onto 2958 * The function sets different link parameters provided by the user onto
3111 * the NIC. 2959 * the NIC.
3112 * Return value: 2960 * Return value:
3113 * 0 on success. 2961 * 0 on success.
@@ -3129,7 +2977,7 @@ static int s2io_ethtool_sset(struct net_device *dev,
3129} 2977}
3130 2978
3131/** 2979/**
3132 * s2io_ethtol_gset - Return link specific information. 2980 * s2io_ethtol_gset - Return link specific information.
3133 * @sp : private member of the device structure, pointer to the 2981 * @sp : private member of the device structure, pointer to the
3134 * s2io_nic structure. 2982 * s2io_nic structure.
3135 * @info : pointer to the structure with parameters given by ethtool 2983 * @info : pointer to the structure with parameters given by ethtool
@@ -3161,8 +3009,8 @@ static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
3161} 3009}
3162 3010
3163/** 3011/**
3164 * s2io_ethtool_gdrvinfo - Returns driver specific information. 3012 * s2io_ethtool_gdrvinfo - Returns driver specific information.
3165 * @sp : private member of the device structure, which is a pointer to the 3013 * @sp : private member of the device structure, which is a pointer to the
3166 * s2io_nic structure. 3014 * s2io_nic structure.
3167 * @info : pointer to the structure with parameters given by ethtool to 3015 * @info : pointer to the structure with parameters given by ethtool to
3168 * return driver information. 3016 * return driver information.
@@ -3190,9 +3038,9 @@ static void s2io_ethtool_gdrvinfo(struct net_device *dev,
3190 3038
3191/** 3039/**
3192 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer. 3040 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
3193 * @sp: private member of the device structure, which is a pointer to the 3041 * @sp: private member of the device structure, which is a pointer to the
3194 * s2io_nic structure. 3042 * s2io_nic structure.
3195 * @regs : pointer to the structure with parameters given by ethtool for 3043 * @regs : pointer to the structure with parameters given by ethtool for
3196 * dumping the registers. 3044 * dumping the registers.
3197 * @reg_space: The input argumnet into which all the registers are dumped. 3045 * @reg_space: The input argumnet into which all the registers are dumped.
3198 * Description: 3046 * Description:
@@ -3221,11 +3069,11 @@ static void s2io_ethtool_gregs(struct net_device *dev,
3221 3069
3222/** 3070/**
3223 * s2io_phy_id - timer function that alternates adapter LED. 3071 * s2io_phy_id - timer function that alternates adapter LED.
3224 * @data : address of the private member of the device structure, which 3072 * @data : address of the private member of the device structure, which
3225 * is a pointer to the s2io_nic structure, provided as an u32. 3073 * is a pointer to the s2io_nic structure, provided as an u32.
3226 * Description: This is actually the timer function that alternates the 3074 * Description: This is actually the timer function that alternates the
3227 * adapter LED bit of the adapter control bit to set/reset every time on 3075 * adapter LED bit of the adapter control bit to set/reset every time on
3228 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks 3076 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
3229 * once every second. 3077 * once every second.
3230*/ 3078*/
3231static void s2io_phy_id(unsigned long data) 3079static void s2io_phy_id(unsigned long data)
@@ -3253,12 +3101,12 @@ static void s2io_phy_id(unsigned long data)
3253 * s2io_ethtool_idnic - To physically identify the nic on the system. 3101 * s2io_ethtool_idnic - To physically identify the nic on the system.
3254 * @sp : private member of the device structure, which is a pointer to the 3102 * @sp : private member of the device structure, which is a pointer to the
3255 * s2io_nic structure. 3103 * s2io_nic structure.
3256 * @id : pointer to the structure with identification parameters given by 3104 * @id : pointer to the structure with identification parameters given by
3257 * ethtool. 3105 * ethtool.
3258 * Description: Used to physically identify the NIC on the system. 3106 * Description: Used to physically identify the NIC on the system.
3259 * The Link LED will blink for a time specified by the user for 3107 * The Link LED will blink for a time specified by the user for
3260 * identification. 3108 * identification.
3261 * NOTE: The Link has to be Up to be able to blink the LED. Hence 3109 * NOTE: The Link has to be Up to be able to blink the LED. Hence
3262 * identification is possible only if it's link is up. 3110 * identification is possible only if it's link is up.
3263 * Return value: 3111 * Return value:
3264 * int , returns 0 on success 3112 * int , returns 0 on success
@@ -3288,9 +3136,9 @@ static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
3288 } 3136 }
3289 mod_timer(&sp->id_timer, jiffies); 3137 mod_timer(&sp->id_timer, jiffies);
3290 if (data) 3138 if (data)
3291 msleep(data * 1000); 3139 msleep_interruptible(data * HZ);
3292 else 3140 else
3293 msleep(0xFFFFFFFF); 3141 msleep_interruptible(MAX_FLICKER_TIME);
3294 del_timer_sync(&sp->id_timer); 3142 del_timer_sync(&sp->id_timer);
3295 3143
3296 if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) { 3144 if (CARDS_WITH_FAULTY_LINK_INDICATORS(subid)) {
@@ -3303,7 +3151,8 @@ static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
3303 3151
3304/** 3152/**
3305 * s2io_ethtool_getpause_data -Pause frame frame generation and reception. 3153 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
3306 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. 3154 * @sp : private member of the device structure, which is a pointer to the
3155 * s2io_nic structure.
3307 * @ep : pointer to the structure with pause parameters given by ethtool. 3156 * @ep : pointer to the structure with pause parameters given by ethtool.
3308 * Description: 3157 * Description:
3309 * Returns the Pause frame generation and reception capability of the NIC. 3158 * Returns the Pause frame generation and reception capability of the NIC.
@@ -3327,7 +3176,7 @@ static void s2io_ethtool_getpause_data(struct net_device *dev,
3327 3176
3328/** 3177/**
3329 * s2io_ethtool_setpause_data - set/reset pause frame generation. 3178 * s2io_ethtool_setpause_data - set/reset pause frame generation.
3330 * @sp : private member of the device structure, which is a pointer to the 3179 * @sp : private member of the device structure, which is a pointer to the
3331 * s2io_nic structure. 3180 * s2io_nic structure.
3332 * @ep : pointer to the structure with pause parameters given by ethtool. 3181 * @ep : pointer to the structure with pause parameters given by ethtool.
3333 * Description: 3182 * Description:
@@ -3338,7 +3187,7 @@ static void s2io_ethtool_getpause_data(struct net_device *dev,
3338 */ 3187 */
3339 3188
3340static int s2io_ethtool_setpause_data(struct net_device *dev, 3189static int s2io_ethtool_setpause_data(struct net_device *dev,
3341 struct ethtool_pauseparam *ep) 3190 struct ethtool_pauseparam *ep)
3342{ 3191{
3343 u64 val64; 3192 u64 val64;
3344 nic_t *sp = dev->priv; 3193 nic_t *sp = dev->priv;
@@ -3359,13 +3208,13 @@ static int s2io_ethtool_setpause_data(struct net_device *dev,
3359 3208
3360/** 3209/**
3361 * read_eeprom - reads 4 bytes of data from user given offset. 3210 * read_eeprom - reads 4 bytes of data from user given offset.
3362 * @sp : private member of the device structure, which is a pointer to the 3211 * @sp : private member of the device structure, which is a pointer to the
3363 * s2io_nic structure. 3212 * s2io_nic structure.
3364 * @off : offset at which the data must be written 3213 * @off : offset at which the data must be written
3365 * @data : Its an output parameter where the data read at the given 3214 * @data : Its an output parameter where the data read at the given
3366 * offset is stored. 3215 * offset is stored.
3367 * Description: 3216 * Description:
3368 * Will read 4 bytes of data from the user given offset and return the 3217 * Will read 4 bytes of data from the user given offset and return the
3369 * read data. 3218 * read data.
3370 * NOTE: Will allow to read only part of the EEPROM visible through the 3219 * NOTE: Will allow to read only part of the EEPROM visible through the
3371 * I2C bus. 3220 * I2C bus.
@@ -3406,7 +3255,7 @@ static int read_eeprom(nic_t * sp, int off, u32 * data)
3406 * s2io_nic structure. 3255 * s2io_nic structure.
3407 * @off : offset at which the data must be written 3256 * @off : offset at which the data must be written
3408 * @data : The data that is to be written 3257 * @data : The data that is to be written
3409 * @cnt : Number of bytes of the data that are actually to be written into 3258 * @cnt : Number of bytes of the data that are actually to be written into
3410 * the Eeprom. (max of 3) 3259 * the Eeprom. (max of 3)
3411 * Description: 3260 * Description:
3412 * Actually writes the relevant part of the data value into the Eeprom 3261 * Actually writes the relevant part of the data value into the Eeprom
@@ -3443,7 +3292,7 @@ static int write_eeprom(nic_t * sp, int off, u32 data, int cnt)
3443/** 3292/**
3444 * s2io_ethtool_geeprom - reads the value stored in the Eeprom. 3293 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
3445 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. 3294 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
3446 * @eeprom : pointer to the user level structure provided by ethtool, 3295 * @eeprom : pointer to the user level structure provided by ethtool,
3447 * containing all relevant information. 3296 * containing all relevant information.
3448 * @data_buf : user defined value to be written into Eeprom. 3297 * @data_buf : user defined value to be written into Eeprom.
3449 * Description: Reads the values stored in the Eeprom at given offset 3298 * Description: Reads the values stored in the Eeprom at given offset
@@ -3454,7 +3303,7 @@ static int write_eeprom(nic_t * sp, int off, u32 data, int cnt)
3454 */ 3303 */
3455 3304
3456static int s2io_ethtool_geeprom(struct net_device *dev, 3305static int s2io_ethtool_geeprom(struct net_device *dev,
3457 struct ethtool_eeprom *eeprom, u8 * data_buf) 3306 struct ethtool_eeprom *eeprom, u8 * data_buf)
3458{ 3307{
3459 u32 data, i, valid; 3308 u32 data, i, valid;
3460 nic_t *sp = dev->priv; 3309 nic_t *sp = dev->priv;
@@ -3479,7 +3328,7 @@ static int s2io_ethtool_geeprom(struct net_device *dev,
3479 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom 3328 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
3480 * @sp : private member of the device structure, which is a pointer to the 3329 * @sp : private member of the device structure, which is a pointer to the
3481 * s2io_nic structure. 3330 * s2io_nic structure.
3482 * @eeprom : pointer to the user level structure provided by ethtool, 3331 * @eeprom : pointer to the user level structure provided by ethtool,
3483 * containing all relevant information. 3332 * containing all relevant information.
3484 * @data_buf ; user defined value to be written into Eeprom. 3333 * @data_buf ; user defined value to be written into Eeprom.
3485 * Description: 3334 * Description:
@@ -3527,8 +3376,8 @@ static int s2io_ethtool_seeprom(struct net_device *dev,
3527} 3376}
3528 3377
3529/** 3378/**
3530 * s2io_register_test - reads and writes into all clock domains. 3379 * s2io_register_test - reads and writes into all clock domains.
3531 * @sp : private member of the device structure, which is a pointer to the 3380 * @sp : private member of the device structure, which is a pointer to the
3532 * s2io_nic structure. 3381 * s2io_nic structure.
3533 * @data : variable that returns the result of each of the test conducted b 3382 * @data : variable that returns the result of each of the test conducted b
3534 * by the driver. 3383 * by the driver.
@@ -3545,8 +3394,8 @@ static int s2io_register_test(nic_t * sp, uint64_t * data)
3545 u64 val64 = 0; 3394 u64 val64 = 0;
3546 int fail = 0; 3395 int fail = 0;
3547 3396
3548 val64 = readq(&bar0->pcc_enable); 3397 val64 = readq(&bar0->pif_rd_swapper_fb);
3549 if (val64 != 0xff00000000000000ULL) { 3398 if (val64 != 0x123456789abcdefULL) {
3550 fail = 1; 3399 fail = 1;
3551 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n"); 3400 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
3552 } 3401 }
@@ -3590,13 +3439,13 @@ static int s2io_register_test(nic_t * sp, uint64_t * data)
3590} 3439}
3591 3440
3592/** 3441/**
3593 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed. 3442 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
3594 * @sp : private member of the device structure, which is a pointer to the 3443 * @sp : private member of the device structure, which is a pointer to the
3595 * s2io_nic structure. 3444 * s2io_nic structure.
3596 * @data:variable that returns the result of each of the test conducted by 3445 * @data:variable that returns the result of each of the test conducted by
3597 * the driver. 3446 * the driver.
3598 * Description: 3447 * Description:
3599 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL 3448 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
3600 * register. 3449 * register.
3601 * Return value: 3450 * Return value:
3602 * 0 on success. 3451 * 0 on success.
@@ -3661,14 +3510,14 @@ static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
3661 3510
3662/** 3511/**
3663 * s2io_bist_test - invokes the MemBist test of the card . 3512 * s2io_bist_test - invokes the MemBist test of the card .
3664 * @sp : private member of the device structure, which is a pointer to the 3513 * @sp : private member of the device structure, which is a pointer to the
3665 * s2io_nic structure. 3514 * s2io_nic structure.
3666 * @data:variable that returns the result of each of the test conducted by 3515 * @data:variable that returns the result of each of the test conducted by
3667 * the driver. 3516 * the driver.
3668 * Description: 3517 * Description:
3669 * This invokes the MemBist test of the card. We give around 3518 * This invokes the MemBist test of the card. We give around
3670 * 2 secs time for the Test to complete. If it's still not complete 3519 * 2 secs time for the Test to complete. If it's still not complete
3671 * within this peiod, we consider that the test failed. 3520 * within this peiod, we consider that the test failed.
3672 * Return value: 3521 * Return value:
3673 * 0 on success and -1 on failure. 3522 * 0 on success and -1 on failure.
3674 */ 3523 */
@@ -3697,13 +3546,13 @@ static int s2io_bist_test(nic_t * sp, uint64_t * data)
3697} 3546}
3698 3547
3699/** 3548/**
3700 * s2io-link_test - verifies the link state of the nic 3549 * s2io-link_test - verifies the link state of the nic
3701 * @sp ; private member of the device structure, which is a pointer to the 3550 * @sp ; private member of the device structure, which is a pointer to the
3702 * s2io_nic structure. 3551 * s2io_nic structure.
3703 * @data: variable that returns the result of each of the test conducted by 3552 * @data: variable that returns the result of each of the test conducted by
3704 * the driver. 3553 * the driver.
3705 * Description: 3554 * Description:
3706 * The function verifies the link state of the NIC and updates the input 3555 * The function verifies the link state of the NIC and updates the input
3707 * argument 'data' appropriately. 3556 * argument 'data' appropriately.
3708 * Return value: 3557 * Return value:
3709 * 0 on success. 3558 * 0 on success.
@@ -3722,13 +3571,13 @@ static int s2io_link_test(nic_t * sp, uint64_t * data)
3722} 3571}
3723 3572
3724/** 3573/**
3725 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC 3574 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
3726 * @sp - private member of the device structure, which is a pointer to the 3575 * @sp - private member of the device structure, which is a pointer to the
3727 * s2io_nic structure. 3576 * s2io_nic structure.
3728 * @data - variable that returns the result of each of the test 3577 * @data - variable that returns the result of each of the test
3729 * conducted by the driver. 3578 * conducted by the driver.
3730 * Description: 3579 * Description:
3731 * This is one of the offline test that tests the read and write 3580 * This is one of the offline test that tests the read and write
3732 * access to the RldRam chip on the NIC. 3581 * access to the RldRam chip on the NIC.
3733 * Return value: 3582 * Return value:
3734 * 0 on success. 3583 * 0 on success.
@@ -3833,7 +3682,7 @@ static int s2io_rldram_test(nic_t * sp, uint64_t * data)
3833 * s2io_nic structure. 3682 * s2io_nic structure.
3834 * @ethtest : pointer to a ethtool command specific structure that will be 3683 * @ethtest : pointer to a ethtool command specific structure that will be
3835 * returned to the user. 3684 * returned to the user.
3836 * @data : variable that returns the result of each of the test 3685 * @data : variable that returns the result of each of the test
3837 * conducted by the driver. 3686 * conducted by the driver.
3838 * Description: 3687 * Description:
3839 * This function conducts 6 tests ( 4 offline and 2 online) to determine 3688 * This function conducts 6 tests ( 4 offline and 2 online) to determine
@@ -3851,23 +3700,18 @@ static void s2io_ethtool_test(struct net_device *dev,
3851 3700
3852 if (ethtest->flags == ETH_TEST_FL_OFFLINE) { 3701 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
3853 /* Offline Tests. */ 3702 /* Offline Tests. */
3854 if (orig_state) { 3703 if (orig_state)
3855 s2io_close(sp->dev); 3704 s2io_close(sp->dev);
3856 s2io_set_swapper(sp);
3857 } else
3858 s2io_set_swapper(sp);
3859 3705
3860 if (s2io_register_test(sp, &data[0])) 3706 if (s2io_register_test(sp, &data[0]))
3861 ethtest->flags |= ETH_TEST_FL_FAILED; 3707 ethtest->flags |= ETH_TEST_FL_FAILED;
3862 3708
3863 s2io_reset(sp); 3709 s2io_reset(sp);
3864 s2io_set_swapper(sp);
3865 3710
3866 if (s2io_rldram_test(sp, &data[3])) 3711 if (s2io_rldram_test(sp, &data[3]))
3867 ethtest->flags |= ETH_TEST_FL_FAILED; 3712 ethtest->flags |= ETH_TEST_FL_FAILED;
3868 3713
3869 s2io_reset(sp); 3714 s2io_reset(sp);
3870 s2io_set_swapper(sp);
3871 3715
3872 if (s2io_eeprom_test(sp, &data[1])) 3716 if (s2io_eeprom_test(sp, &data[1]))
3873 ethtest->flags |= ETH_TEST_FL_FAILED; 3717 ethtest->flags |= ETH_TEST_FL_FAILED;
@@ -3951,20 +3795,19 @@ static void s2io_get_ethtool_stats(struct net_device *dev,
3951 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp); 3795 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
3952} 3796}
3953 3797
3954static int s2io_ethtool_get_regs_len(struct net_device *dev) 3798int s2io_ethtool_get_regs_len(struct net_device *dev)
3955{ 3799{
3956 return (XENA_REG_SPACE); 3800 return (XENA_REG_SPACE);
3957} 3801}
3958 3802
3959 3803
3960static u32 s2io_ethtool_get_rx_csum(struct net_device * dev) 3804u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
3961{ 3805{
3962 nic_t *sp = dev->priv; 3806 nic_t *sp = dev->priv;
3963 3807
3964 return (sp->rx_csum); 3808 return (sp->rx_csum);
3965} 3809}
3966 3810int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
3967static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
3968{ 3811{
3969 nic_t *sp = dev->priv; 3812 nic_t *sp = dev->priv;
3970 3813
@@ -3975,19 +3818,17 @@ static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
3975 3818
3976 return 0; 3819 return 0;
3977} 3820}
3978 3821int s2io_get_eeprom_len(struct net_device *dev)
3979static int s2io_get_eeprom_len(struct net_device *dev)
3980{ 3822{
3981 return (XENA_EEPROM_SPACE); 3823 return (XENA_EEPROM_SPACE);
3982} 3824}
3983 3825
3984static int s2io_ethtool_self_test_count(struct net_device *dev) 3826int s2io_ethtool_self_test_count(struct net_device *dev)
3985{ 3827{
3986 return (S2IO_TEST_LEN); 3828 return (S2IO_TEST_LEN);
3987} 3829}
3988 3830void s2io_ethtool_get_strings(struct net_device *dev,
3989static void s2io_ethtool_get_strings(struct net_device *dev, 3831 u32 stringset, u8 * data)
3990 u32 stringset, u8 * data)
3991{ 3832{
3992 switch (stringset) { 3833 switch (stringset) {
3993 case ETH_SS_TEST: 3834 case ETH_SS_TEST:
@@ -3998,13 +3839,12 @@ static void s2io_ethtool_get_strings(struct net_device *dev,
3998 sizeof(ethtool_stats_keys)); 3839 sizeof(ethtool_stats_keys));
3999 } 3840 }
4000} 3841}
4001
4002static int s2io_ethtool_get_stats_count(struct net_device *dev) 3842static int s2io_ethtool_get_stats_count(struct net_device *dev)
4003{ 3843{
4004 return (S2IO_STAT_LEN); 3844 return (S2IO_STAT_LEN);
4005} 3845}
4006 3846
4007static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data) 3847int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
4008{ 3848{
4009 if (data) 3849 if (data)
4010 dev->features |= NETIF_F_IP_CSUM; 3850 dev->features |= NETIF_F_IP_CSUM;
@@ -4046,21 +3886,18 @@ static struct ethtool_ops netdev_ethtool_ops = {
4046}; 3886};
4047 3887
4048/** 3888/**
4049 * s2io_ioctl - Entry point for the Ioctl 3889 * s2io_ioctl - Entry point for the Ioctl
4050 * @dev : Device pointer. 3890 * @dev : Device pointer.
4051 * @ifr : An IOCTL specefic structure, that can contain a pointer to 3891 * @ifr : An IOCTL specefic structure, that can contain a pointer to
4052 * a proprietary structure used to pass information to the driver. 3892 * a proprietary structure used to pass information to the driver.
4053 * @cmd : This is used to distinguish between the different commands that 3893 * @cmd : This is used to distinguish between the different commands that
4054 * can be passed to the IOCTL functions. 3894 * can be passed to the IOCTL functions.
4055 * Description: 3895 * Description:
4056 * This function has support for ethtool, adding multiple MAC addresses on 3896 * Currently there are no special functionality supported in IOCTL, hence
4057 * the NIC and some DBG commands for the util tool. 3897 * function always return EOPNOTSUPPORTED
4058 * Return value:
4059 * Currently the IOCTL supports no operations, hence by default this
4060 * function returns OP NOT SUPPORTED value.
4061 */ 3898 */
4062 3899
4063static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3900int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4064{ 3901{
4065 return -EOPNOTSUPP; 3902 return -EOPNOTSUPP;
4066} 3903}
@@ -4076,7 +3913,7 @@ static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
4076 * file on failure. 3913 * file on failure.
4077 */ 3914 */
4078 3915
4079static int s2io_change_mtu(struct net_device *dev, int new_mtu) 3916int s2io_change_mtu(struct net_device *dev, int new_mtu)
4080{ 3917{
4081 nic_t *sp = dev->priv; 3918 nic_t *sp = dev->priv;
4082 XENA_dev_config_t __iomem *bar0 = sp->bar0; 3919 XENA_dev_config_t __iomem *bar0 = sp->bar0;
@@ -4084,7 +3921,7 @@ static int s2io_change_mtu(struct net_device *dev, int new_mtu)
4084 3921
4085 if (netif_running(dev)) { 3922 if (netif_running(dev)) {
4086 DBG_PRINT(ERR_DBG, "%s: Must be stopped to ", dev->name); 3923 DBG_PRINT(ERR_DBG, "%s: Must be stopped to ", dev->name);
4087 DBG_PRINT(ERR_DBG, "change its MTU \n"); 3924 DBG_PRINT(ERR_DBG, "change its MTU\n");
4088 return -EBUSY; 3925 return -EBUSY;
4089 } 3926 }
4090 3927
@@ -4108,9 +3945,9 @@ static int s2io_change_mtu(struct net_device *dev, int new_mtu)
4108 * @dev_adr : address of the device structure in dma_addr_t format. 3945 * @dev_adr : address of the device structure in dma_addr_t format.
4109 * Description: 3946 * Description:
4110 * This is the tasklet or the bottom half of the ISR. This is 3947 * This is the tasklet or the bottom half of the ISR. This is
4111 * an extension of the ISR which is scheduled by the scheduler to be run 3948 * an extension of the ISR which is scheduled by the scheduler to be run
4112 * when the load on the CPU is low. All low priority tasks of the ISR can 3949 * when the load on the CPU is low. All low priority tasks of the ISR can
4113 * be pushed into the tasklet. For now the tasklet is used only to 3950 * be pushed into the tasklet. For now the tasklet is used only to
4114 * replenish the Rx buffers in the Rx buffer descriptors. 3951 * replenish the Rx buffers in the Rx buffer descriptors.
4115 * Return value: 3952 * Return value:
4116 * void. 3953 * void.
@@ -4166,14 +4003,14 @@ static void s2io_set_link(unsigned long data)
4166 } 4003 }
4167 4004
4168 subid = nic->pdev->subsystem_device; 4005 subid = nic->pdev->subsystem_device;
4169 /* 4006 /*
4170 * Allow a small delay for the NICs self initiated 4007 * Allow a small delay for the NICs self initiated
4171 * cleanup to complete. 4008 * cleanup to complete.
4172 */ 4009 */
4173 msleep(100); 4010 msleep(100);
4174 4011
4175 val64 = readq(&bar0->adapter_status); 4012 val64 = readq(&bar0->adapter_status);
4176 if (verify_xena_quiescence(val64, nic->device_enabled_once)) { 4013 if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
4177 if (LINK_IS_UP(val64)) { 4014 if (LINK_IS_UP(val64)) {
4178 val64 = readq(&bar0->adapter_control); 4015 val64 = readq(&bar0->adapter_control);
4179 val64 |= ADAPTER_CNTL_EN; 4016 val64 |= ADAPTER_CNTL_EN;
@@ -4224,8 +4061,9 @@ static void s2io_card_down(nic_t * sp)
4224 register u64 val64 = 0; 4061 register u64 val64 = 0;
4225 4062
4226 /* If s2io_set_link task is executing, wait till it completes. */ 4063 /* If s2io_set_link task is executing, wait till it completes. */
4227 while (test_and_set_bit(0, &(sp->link_state))) 4064 while (test_and_set_bit(0, &(sp->link_state))) {
4228 msleep(50); 4065 msleep(50);
4066 }
4229 atomic_set(&sp->card_state, CARD_DOWN); 4067 atomic_set(&sp->card_state, CARD_DOWN);
4230 4068
4231 /* disable Tx and Rx traffic on the NIC */ 4069 /* disable Tx and Rx traffic on the NIC */
@@ -4237,7 +4075,7 @@ static void s2io_card_down(nic_t * sp)
4237 /* Check if the device is Quiescent and then Reset the NIC */ 4075 /* Check if the device is Quiescent and then Reset the NIC */
4238 do { 4076 do {
4239 val64 = readq(&bar0->adapter_status); 4077 val64 = readq(&bar0->adapter_status);
4240 if (verify_xena_quiescence(val64, sp->device_enabled_once)) { 4078 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
4241 break; 4079 break;
4242 } 4080 }
4243 4081
@@ -4276,8 +4114,8 @@ static int s2io_card_up(nic_t * sp)
4276 return -ENODEV; 4114 return -ENODEV;
4277 } 4115 }
4278 4116
4279 /* 4117 /*
4280 * Initializing the Rx buffers. For now we are considering only 1 4118 * Initializing the Rx buffers. For now we are considering only 1
4281 * Rx ring and initializing buffers into 30 Rx blocks 4119 * Rx ring and initializing buffers into 30 Rx blocks
4282 */ 4120 */
4283 mac_control = &sp->mac_control; 4121 mac_control = &sp->mac_control;
@@ -4315,12 +4153,12 @@ static int s2io_card_up(nic_t * sp)
4315 return 0; 4153 return 0;
4316} 4154}
4317 4155
4318/** 4156/**
4319 * s2io_restart_nic - Resets the NIC. 4157 * s2io_restart_nic - Resets the NIC.
4320 * @data : long pointer to the device private structure 4158 * @data : long pointer to the device private structure
4321 * Description: 4159 * Description:
4322 * This function is scheduled to be run by the s2io_tx_watchdog 4160 * This function is scheduled to be run by the s2io_tx_watchdog
4323 * function after 0.5 secs to reset the NIC. The idea is to reduce 4161 * function after 0.5 secs to reset the NIC. The idea is to reduce
4324 * the run time of the watch dog routine which is run holding a 4162 * the run time of the watch dog routine which is run holding a
4325 * spin lock. 4163 * spin lock.
4326 */ 4164 */
@@ -4338,10 +4176,11 @@ static void s2io_restart_nic(unsigned long data)
4338 netif_wake_queue(dev); 4176 netif_wake_queue(dev);
4339 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", 4177 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
4340 dev->name); 4178 dev->name);
4179
4341} 4180}
4342 4181
4343/** 4182/**
4344 * s2io_tx_watchdog - Watchdog for transmit side. 4183 * s2io_tx_watchdog - Watchdog for transmit side.
4345 * @dev : Pointer to net device structure 4184 * @dev : Pointer to net device structure
4346 * Description: 4185 * Description:
4347 * This function is triggered if the Tx Queue is stopped 4186 * This function is triggered if the Tx Queue is stopped
@@ -4369,7 +4208,7 @@ static void s2io_tx_watchdog(struct net_device *dev)
4369 * @len : length of the packet 4208 * @len : length of the packet
4370 * @cksum : FCS checksum of the frame. 4209 * @cksum : FCS checksum of the frame.
4371 * @ring_no : the ring from which this RxD was extracted. 4210 * @ring_no : the ring from which this RxD was extracted.
4372 * Description: 4211 * Description:
4373 * This function is called by the Tx interrupt serivce routine to perform 4212 * This function is called by the Tx interrupt serivce routine to perform
4374 * some OS related operations on the SKB before passing it to the upper 4213 * some OS related operations on the SKB before passing it to the upper
4375 * layers. It mainly checks if the checksum is OK, if so adds it to the 4214 * layers. It mainly checks if the checksum is OK, if so adds it to the
@@ -4379,35 +4218,63 @@ static void s2io_tx_watchdog(struct net_device *dev)
4379 * Return value: 4218 * Return value:
4380 * SUCCESS on success and -1 on failure. 4219 * SUCCESS on success and -1 on failure.
4381 */ 4220 */
4382#ifndef CONFIG_2BUFF_MODE 4221static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
4383static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no)
4384#else
4385static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
4386 buffAdd_t * ba)
4387#endif
4388{ 4222{
4223 nic_t *sp = ring_data->nic;
4389 struct net_device *dev = (struct net_device *) sp->dev; 4224 struct net_device *dev = (struct net_device *) sp->dev;
4390 struct sk_buff *skb = 4225 struct sk_buff *skb = (struct sk_buff *)
4391 (struct sk_buff *) ((unsigned long) rxdp->Host_Control); 4226 ((unsigned long) rxdp->Host_Control);
4227 int ring_no = ring_data->ring_no;
4392 u16 l3_csum, l4_csum; 4228 u16 l3_csum, l4_csum;
4393#ifdef CONFIG_2BUFF_MODE 4229#ifdef CONFIG_2BUFF_MODE
4394 int buf0_len, buf2_len; 4230 int buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
4231 int buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
4232 int get_block = ring_data->rx_curr_get_info.block_index;
4233 int get_off = ring_data->rx_curr_get_info.offset;
4234 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
4395 unsigned char *buff; 4235 unsigned char *buff;
4236#else
4237 u16 len = (u16) ((RXD_GET_BUFFER0_SIZE(rxdp->Control_2)) >> 48);;
4396#endif 4238#endif
4239 skb->dev = dev;
4240 if (rxdp->Control_1 & RXD_T_CODE) {
4241 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
4242 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
4243 dev->name, err);
4244 }
4397 4245
4398 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1); 4246 /* Updating statistics */
4399 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && (sp->rx_csum)) { 4247 rxdp->Host_Control = 0;
4248 sp->rx_pkt_count++;
4249 sp->stats.rx_packets++;
4250#ifndef CONFIG_2BUFF_MODE
4251 sp->stats.rx_bytes += len;
4252#else
4253 sp->stats.rx_bytes += buf0_len + buf2_len;
4254#endif
4255
4256#ifndef CONFIG_2BUFF_MODE
4257 skb_put(skb, len);
4258#else
4259 buff = skb_push(skb, buf0_len);
4260 memcpy(buff, ba->ba_0, buf0_len);
4261 skb_put(skb, buf2_len);
4262#endif
4263
4264 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
4265 (sp->rx_csum)) {
4266 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
4400 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1); 4267 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
4401 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) { 4268 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
4402 /* 4269 /*
4403 * NIC verifies if the Checksum of the received 4270 * NIC verifies if the Checksum of the received
4404 * frame is Ok or not and accordingly returns 4271 * frame is Ok or not and accordingly returns
4405 * a flag in the RxD. 4272 * a flag in the RxD.
4406 */ 4273 */
4407 skb->ip_summed = CHECKSUM_UNNECESSARY; 4274 skb->ip_summed = CHECKSUM_UNNECESSARY;
4408 } else { 4275 } else {
4409 /* 4276 /*
4410 * Packet with erroneous checksum, let the 4277 * Packet with erroneous checksum, let the
4411 * upper layers deal with it. 4278 * upper layers deal with it.
4412 */ 4279 */
4413 skb->ip_summed = CHECKSUM_NONE; 4280 skb->ip_summed = CHECKSUM_NONE;
@@ -4416,44 +4283,14 @@ static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
4416 skb->ip_summed = CHECKSUM_NONE; 4283 skb->ip_summed = CHECKSUM_NONE;
4417 } 4284 }
4418 4285
4419 if (rxdp->Control_1 & RXD_T_CODE) {
4420 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
4421 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
4422 dev->name, err);
4423 }
4424#ifdef CONFIG_2BUFF_MODE
4425 buf0_len = RXD_GET_BUFFER0_SIZE(rxdp->Control_2);
4426 buf2_len = RXD_GET_BUFFER2_SIZE(rxdp->Control_2);
4427#endif
4428
4429 skb->dev = dev;
4430#ifndef CONFIG_2BUFF_MODE
4431 skb_put(skb, len);
4432 skb->protocol = eth_type_trans(skb, dev); 4286 skb->protocol = eth_type_trans(skb, dev);
4433#else
4434 buff = skb_push(skb, buf0_len);
4435 memcpy(buff, ba->ba_0, buf0_len);
4436 skb_put(skb, buf2_len);
4437 skb->protocol = eth_type_trans(skb, dev);
4438#endif
4439
4440#ifdef CONFIG_S2IO_NAPI 4287#ifdef CONFIG_S2IO_NAPI
4441 netif_receive_skb(skb); 4288 netif_receive_skb(skb);
4442#else 4289#else
4443 netif_rx(skb); 4290 netif_rx(skb);
4444#endif 4291#endif
4445
4446 dev->last_rx = jiffies; 4292 dev->last_rx = jiffies;
4447 sp->rx_pkt_count++;
4448 sp->stats.rx_packets++;
4449#ifndef CONFIG_2BUFF_MODE
4450 sp->stats.rx_bytes += len;
4451#else
4452 sp->stats.rx_bytes += buf0_len + buf2_len;
4453#endif
4454
4455 atomic_dec(&sp->rx_bufs_left[ring_no]); 4293 atomic_dec(&sp->rx_bufs_left[ring_no]);
4456 rxdp->Host_Control = 0;
4457 return SUCCESS; 4294 return SUCCESS;
4458} 4295}
4459 4296
@@ -4464,13 +4301,13 @@ static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
4464 * @link : inidicates whether link is UP/DOWN. 4301 * @link : inidicates whether link is UP/DOWN.
4465 * Description: 4302 * Description:
4466 * This function stops/starts the Tx queue depending on whether the link 4303 * This function stops/starts the Tx queue depending on whether the link
4467 * status of the NIC is is down or up. This is called by the Alarm 4304 * status of the NIC is is down or up. This is called by the Alarm
4468 * interrupt handler whenever a link change interrupt comes up. 4305 * interrupt handler whenever a link change interrupt comes up.
4469 * Return value: 4306 * Return value:
4470 * void. 4307 * void.
4471 */ 4308 */
4472 4309
4473static void s2io_link(nic_t * sp, int link) 4310void s2io_link(nic_t * sp, int link)
4474{ 4311{
4475 struct net_device *dev = (struct net_device *) sp->dev; 4312 struct net_device *dev = (struct net_device *) sp->dev;
4476 4313
@@ -4487,8 +4324,25 @@ static void s2io_link(nic_t * sp, int link)
4487} 4324}
4488 4325
4489/** 4326/**
4490 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers . 4327 * get_xena_rev_id - to identify revision ID of xena.
4491 * @sp : private member of the device structure, which is a pointer to the 4328 * @pdev : PCI Dev structure
4329 * Description:
4330 * Function to identify the Revision ID of xena.
4331 * Return value:
4332 * returns the revision ID of the device.
4333 */
4334
4335int get_xena_rev_id(struct pci_dev *pdev)
4336{
4337 u8 id = 0;
4338 int ret;
4339 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
4340 return id;
4341}
4342
4343/**
4344 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
4345 * @sp : private member of the device structure, which is a pointer to the
4492 * s2io_nic structure. 4346 * s2io_nic structure.
4493 * Description: 4347 * Description:
4494 * This function initializes a few of the PCI and PCI-X configuration registers 4348 * This function initializes a few of the PCI and PCI-X configuration registers
@@ -4499,15 +4353,15 @@ static void s2io_link(nic_t * sp, int link)
4499 4353
4500static void s2io_init_pci(nic_t * sp) 4354static void s2io_init_pci(nic_t * sp)
4501{ 4355{
4502 u16 pci_cmd = 0; 4356 u16 pci_cmd = 0, pcix_cmd = 0;
4503 4357
4504 /* Enable Data Parity Error Recovery in PCI-X command register. */ 4358 /* Enable Data Parity Error Recovery in PCI-X command register. */
4505 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 4359 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4506 &(sp->pcix_cmd)); 4360 &(pcix_cmd));
4507 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 4361 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4508 (sp->pcix_cmd | 1)); 4362 (pcix_cmd | 1));
4509 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 4363 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4510 &(sp->pcix_cmd)); 4364 &(pcix_cmd));
4511 4365
4512 /* Set the PErr Response bit in PCI command register. */ 4366 /* Set the PErr Response bit in PCI command register. */
4513 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); 4367 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
@@ -4516,34 +4370,36 @@ static void s2io_init_pci(nic_t * sp)
4516 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); 4370 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
4517 4371
4518 /* Set MMRB count to 1024 in PCI-X Command register. */ 4372 /* Set MMRB count to 1024 in PCI-X Command register. */
4519 sp->pcix_cmd &= 0xFFF3; 4373 pcix_cmd &= 0xFFF3;
4520 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, (sp->pcix_cmd | (0x1 << 2))); /* MMRBC 1K */ 4374 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4375 (pcix_cmd | (0x1 << 2))); /* MMRBC 1K */
4521 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 4376 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4522 &(sp->pcix_cmd)); 4377 &(pcix_cmd));
4523 4378
4524 /* Setting Maximum outstanding splits based on system type. */ 4379 /* Setting Maximum outstanding splits based on system type. */
4525 sp->pcix_cmd &= 0xFF8F; 4380 pcix_cmd &= 0xFF8F;
4526 4381 pcix_cmd |= XENA_MAX_OUTSTANDING_SPLITS(0x1); /* 2 splits. */
4527 sp->pcix_cmd |= XENA_MAX_OUTSTANDING_SPLITS(0x1); /* 2 splits. */
4528 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 4382 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4529 sp->pcix_cmd); 4383 pcix_cmd);
4530 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 4384 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4531 &(sp->pcix_cmd)); 4385 &(pcix_cmd));
4386
4532 /* Forcibly disabling relaxed ordering capability of the card. */ 4387 /* Forcibly disabling relaxed ordering capability of the card. */
4533 sp->pcix_cmd &= 0xfffd; 4388 pcix_cmd &= 0xfffd;
4534 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 4389 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4535 sp->pcix_cmd); 4390 pcix_cmd);
4536 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, 4391 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
4537 &(sp->pcix_cmd)); 4392 &(pcix_cmd));
4538} 4393}
4539 4394
4540MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>"); 4395MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
4541MODULE_LICENSE("GPL"); 4396MODULE_LICENSE("GPL");
4542module_param(tx_fifo_num, int, 0); 4397module_param(tx_fifo_num, int, 0);
4543module_param_array(tx_fifo_len, int, NULL, 0);
4544module_param(rx_ring_num, int, 0); 4398module_param(rx_ring_num, int, 0);
4545module_param_array(rx_ring_sz, int, NULL, 0); 4399module_param_array(tx_fifo_len, uint, NULL, 0);
4400module_param_array(rx_ring_sz, uint, NULL, 0);
4546module_param(Stats_refresh_time, int, 0); 4401module_param(Stats_refresh_time, int, 0);
4402module_param_array(rts_frm_len, uint, NULL, 0);
4547module_param(rmac_pause_time, int, 0); 4403module_param(rmac_pause_time, int, 0);
4548module_param(mc_pause_threshold_q0q3, int, 0); 4404module_param(mc_pause_threshold_q0q3, int, 0);
4549module_param(mc_pause_threshold_q4q7, int, 0); 4405module_param(mc_pause_threshold_q4q7, int, 0);
@@ -4553,15 +4409,16 @@ module_param(rmac_util_period, int, 0);
4553#ifndef CONFIG_S2IO_NAPI 4409#ifndef CONFIG_S2IO_NAPI
4554module_param(indicate_max_pkts, int, 0); 4410module_param(indicate_max_pkts, int, 0);
4555#endif 4411#endif
4412
4556/** 4413/**
4557 * s2io_init_nic - Initialization of the adapter . 4414 * s2io_init_nic - Initialization of the adapter .
4558 * @pdev : structure containing the PCI related information of the device. 4415 * @pdev : structure containing the PCI related information of the device.
4559 * @pre: List of PCI devices supported by the driver listed in s2io_tbl. 4416 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
4560 * Description: 4417 * Description:
4561 * The function initializes an adapter identified by the pci_dec structure. 4418 * The function initializes an adapter identified by the pci_dec structure.
4562 * All OS related initialization including memory and device structure and 4419 * All OS related initialization including memory and device structure and
4563 * initlaization of the device private variable is done. Also the swapper 4420 * initlaization of the device private variable is done. Also the swapper
4564 * control register is initialized to enable read and write into the I/O 4421 * control register is initialized to enable read and write into the I/O
4565 * registers of the device. 4422 * registers of the device.
4566 * Return value: 4423 * Return value:
4567 * returns 0 on success and negative on failure. 4424 * returns 0 on success and negative on failure.
@@ -4572,7 +4429,6 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4572{ 4429{
4573 nic_t *sp; 4430 nic_t *sp;
4574 struct net_device *dev; 4431 struct net_device *dev;
4575 char *dev_name = "S2IO 10GE NIC";
4576 int i, j, ret; 4432 int i, j, ret;
4577 int dma_flag = FALSE; 4433 int dma_flag = FALSE;
4578 u32 mac_up, mac_down; 4434 u32 mac_up, mac_down;
@@ -4582,9 +4438,9 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4582 mac_info_t *mac_control; 4438 mac_info_t *mac_control;
4583 struct config_param *config; 4439 struct config_param *config;
4584 4440
4585 4441#ifdef CONFIG_S2IO_NAPI
4586 DBG_PRINT(ERR_DBG, "Loading S2IO driver with %s\n", 4442 DBG_PRINT(ERR_DBG, "NAPI support has been enabled\n");
4587 s2io_driver_version); 4443#endif
4588 4444
4589 if ((ret = pci_enable_device(pdev))) { 4445 if ((ret = pci_enable_device(pdev))) {
4590 DBG_PRINT(ERR_DBG, 4446 DBG_PRINT(ERR_DBG,
@@ -4595,7 +4451,6 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4595 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 4451 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
4596 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n"); 4452 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
4597 dma_flag = TRUE; 4453 dma_flag = TRUE;
4598
4599 if (pci_set_consistent_dma_mask 4454 if (pci_set_consistent_dma_mask
4600 (pdev, DMA_64BIT_MASK)) { 4455 (pdev, DMA_64BIT_MASK)) {
4601 DBG_PRINT(ERR_DBG, 4456 DBG_PRINT(ERR_DBG,
@@ -4635,21 +4490,17 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4635 memset(sp, 0, sizeof(nic_t)); 4490 memset(sp, 0, sizeof(nic_t));
4636 sp->dev = dev; 4491 sp->dev = dev;
4637 sp->pdev = pdev; 4492 sp->pdev = pdev;
4638 sp->vendor_id = pdev->vendor;
4639 sp->device_id = pdev->device;
4640 sp->high_dma_flag = dma_flag; 4493 sp->high_dma_flag = dma_flag;
4641 sp->irq = pdev->irq;
4642 sp->device_enabled_once = FALSE; 4494 sp->device_enabled_once = FALSE;
4643 strcpy(sp->name, dev_name);
4644 4495
4645 /* Initialize some PCI/PCI-X fields of the NIC. */ 4496 /* Initialize some PCI/PCI-X fields of the NIC. */
4646 s2io_init_pci(sp); 4497 s2io_init_pci(sp);
4647 4498
4648 /* 4499 /*
4649 * Setting the device configuration parameters. 4500 * Setting the device configuration parameters.
4650 * Most of these parameters can be specified by the user during 4501 * Most of these parameters can be specified by the user during
4651 * module insertion as they are module loadable parameters. If 4502 * module insertion as they are module loadable parameters. If
4652 * these parameters are not not specified during load time, they 4503 * these parameters are not not specified during load time, they
4653 * are initialized with default values. 4504 * are initialized with default values.
4654 */ 4505 */
4655 mac_control = &sp->mac_control; 4506 mac_control = &sp->mac_control;
@@ -4663,6 +4514,10 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4663 config->tx_cfg[i].fifo_priority = i; 4514 config->tx_cfg[i].fifo_priority = i;
4664 } 4515 }
4665 4516
4517 /* mapping the QoS priority to the configured fifos */
4518 for (i = 0; i < MAX_TX_FIFOS; i++)
4519 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
4520
4666 config->tx_intr_type = TXD_INT_TYPE_UTILZ; 4521 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
4667 for (i = 0; i < config->tx_fifo_num; i++) { 4522 for (i = 0; i < config->tx_fifo_num; i++) {
4668 config->tx_cfg[i].f_no_snoop = 4523 config->tx_cfg[i].f_no_snoop =
@@ -4743,13 +4598,14 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4743 dev->do_ioctl = &s2io_ioctl; 4598 dev->do_ioctl = &s2io_ioctl;
4744 dev->change_mtu = &s2io_change_mtu; 4599 dev->change_mtu = &s2io_change_mtu;
4745 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops); 4600 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
4601
4746 /* 4602 /*
4747 * will use eth_mac_addr() for dev->set_mac_address 4603 * will use eth_mac_addr() for dev->set_mac_address
4748 * mac address will be set every time dev->open() is called 4604 * mac address will be set every time dev->open() is called
4749 */ 4605 */
4750#ifdef CONFIG_S2IO_NAPI 4606#if defined(CONFIG_S2IO_NAPI)
4751 dev->poll = s2io_poll; 4607 dev->poll = s2io_poll;
4752 dev->weight = 90; 4608 dev->weight = 32;
4753#endif 4609#endif
4754 4610
4755 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; 4611 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
@@ -4776,22 +4632,14 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4776 goto set_swap_failed; 4632 goto set_swap_failed;
4777 } 4633 }
4778 4634
4779 /* Fix for all "FFs" MAC address problems observed on Alpha platforms */ 4635 /*
4636 * Fix for all "FFs" MAC address problems observed on
4637 * Alpha platforms
4638 */
4780 fix_mac_address(sp); 4639 fix_mac_address(sp);
4781 s2io_reset(sp); 4640 s2io_reset(sp);
4782 4641
4783 /* 4642 /*
4784 * Setting swapper control on the NIC, so the MAC address can be read.
4785 */
4786 if (s2io_set_swapper(sp)) {
4787 DBG_PRINT(ERR_DBG,
4788 "%s: S2IO: swapper settings are wrong\n",
4789 dev->name);
4790 ret = -EAGAIN;
4791 goto set_swap_failed;
4792 }
4793
4794 /*
4795 * MAC address initialization. 4643 * MAC address initialization.
4796 * For now only one mac address will be read and used. 4644 * For now only one mac address will be read and used.
4797 */ 4645 */
@@ -4828,23 +4676,22 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4828 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN); 4676 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
4829 4677
4830 /* 4678 /*
4831 * Initialize the tasklet status and link state flags 4679 * Initialize the tasklet status and link state flags
4832 * and the card statte parameter 4680 * and the card statte parameter
4833 */ 4681 */
4834 atomic_set(&(sp->card_state), 0); 4682 atomic_set(&(sp->card_state), 0);
4835 sp->tasklet_status = 0; 4683 sp->tasklet_status = 0;
4836 sp->link_state = 0; 4684 sp->link_state = 0;
4837 4685
4838
4839 /* Initialize spinlocks */ 4686 /* Initialize spinlocks */
4840 spin_lock_init(&sp->tx_lock); 4687 spin_lock_init(&sp->tx_lock);
4841#ifndef CONFIG_S2IO_NAPI 4688#ifndef CONFIG_S2IO_NAPI
4842 spin_lock_init(&sp->put_lock); 4689 spin_lock_init(&sp->put_lock);
4843#endif 4690#endif
4844 4691
4845 /* 4692 /*
4846 * SXE-002: Configure link and activity LED to init state 4693 * SXE-002: Configure link and activity LED to init state
4847 * on driver load. 4694 * on driver load.
4848 */ 4695 */
4849 subid = sp->pdev->subsystem_device; 4696 subid = sp->pdev->subsystem_device;
4850 if ((subid & 0xFF) >= 0x07) { 4697 if ((subid & 0xFF) >= 0x07) {
@@ -4864,9 +4711,9 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4864 goto register_failed; 4711 goto register_failed;
4865 } 4712 }
4866 4713
4867 /* 4714 /*
4868 * Make Link state as off at this point, when the Link change 4715 * Make Link state as off at this point, when the Link change
4869 * interrupt comes the state will be automatically changed to 4716 * interrupt comes the state will be automatically changed to
4870 * the right state. 4717 * the right state.
4871 */ 4718 */
4872 netif_carrier_off(dev); 4719 netif_carrier_off(dev);
@@ -4891,11 +4738,11 @@ s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
4891} 4738}
4892 4739
4893/** 4740/**
4894 * s2io_rem_nic - Free the PCI device 4741 * s2io_rem_nic - Free the PCI device
4895 * @pdev: structure containing the PCI related information of the device. 4742 * @pdev: structure containing the PCI related information of the device.
4896 * Description: This function is called by the Pci subsystem to release a 4743 * Description: This function is called by the Pci subsystem to release a
4897 * PCI device and free up all resource held up by the device. This could 4744 * PCI device and free up all resource held up by the device. This could
4898 * be in response to a Hot plug event or when the driver is to be removed 4745 * be in response to a Hot plug event or when the driver is to be removed
4899 * from memory. 4746 * from memory.
4900 */ 4747 */
4901 4748
@@ -4919,7 +4766,6 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev)
4919 pci_disable_device(pdev); 4766 pci_disable_device(pdev);
4920 pci_release_regions(pdev); 4767 pci_release_regions(pdev);
4921 pci_set_drvdata(pdev, NULL); 4768 pci_set_drvdata(pdev, NULL);
4922
4923 free_netdev(dev); 4769 free_netdev(dev);
4924} 4770}
4925 4771
@@ -4935,11 +4781,11 @@ int __init s2io_starter(void)
4935} 4781}
4936 4782
4937/** 4783/**
4938 * s2io_closer - Cleanup routine for the driver 4784 * s2io_closer - Cleanup routine for the driver
4939 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver. 4785 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
4940 */ 4786 */
4941 4787
4942static void s2io_closer(void) 4788void s2io_closer(void)
4943{ 4789{
4944 pci_unregister_driver(&s2io_driver); 4790 pci_unregister_driver(&s2io_driver);
4945 DBG_PRINT(INIT_DBG, "cleanup done\n"); 4791 DBG_PRINT(INIT_DBG, "cleanup done\n");
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index 1711c8c3dc99..4d2fc7a40434 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -31,6 +31,9 @@
31#define SUCCESS 0 31#define SUCCESS 0
32#define FAILURE -1 32#define FAILURE -1
33 33
34/* Maximum time to flicker LED when asked to identify NIC using ethtool */
35#define MAX_FLICKER_TIME 60000 /* 60 Secs */
36
34/* Maximum outstanding splits to be configured into xena. */ 37/* Maximum outstanding splits to be configured into xena. */
35typedef enum xena_max_outstanding_splits { 38typedef enum xena_max_outstanding_splits {
36 XENA_ONE_SPLIT_TRANSACTION = 0, 39 XENA_ONE_SPLIT_TRANSACTION = 0,
@@ -45,10 +48,10 @@ typedef enum xena_max_outstanding_splits {
45#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4) 48#define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4)
46 49
47/* OS concerned variables and constants */ 50/* OS concerned variables and constants */
48#define WATCH_DOG_TIMEOUT 5*HZ 51#define WATCH_DOG_TIMEOUT 15*HZ
49#define EFILL 0x1234 52#define EFILL 0x1234
50#define ALIGN_SIZE 127 53#define ALIGN_SIZE 127
51#define PCIX_COMMAND_REGISTER 0x62 54#define PCIX_COMMAND_REGISTER 0x62
52 55
53/* 56/*
54 * Debug related variables. 57 * Debug related variables.
@@ -61,7 +64,7 @@ typedef enum xena_max_outstanding_splits {
61#define INTR_DBG 4 64#define INTR_DBG 4
62 65
63/* Global variable that defines the present debug level of the driver. */ 66/* Global variable that defines the present debug level of the driver. */
64static int debug_level = ERR_DBG; /* Default level. */ 67int debug_level = ERR_DBG; /* Default level. */
65 68
66/* DEBUG message print. */ 69/* DEBUG message print. */
67#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args) 70#define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args)
@@ -71,6 +74,12 @@ static int debug_level = ERR_DBG; /* Default level. */
71#define L4_CKSUM_OK 0xFFFF 74#define L4_CKSUM_OK 0xFFFF
72#define S2IO_JUMBO_SIZE 9600 75#define S2IO_JUMBO_SIZE 9600
73 76
77/* Driver statistics maintained by driver */
78typedef struct {
79 unsigned long long single_ecc_errs;
80 unsigned long long double_ecc_errs;
81} swStat_t;
82
74/* The statistics block of Xena */ 83/* The statistics block of Xena */
75typedef struct stat_block { 84typedef struct stat_block {
76/* Tx MAC statistics counters. */ 85/* Tx MAC statistics counters. */
@@ -188,10 +197,26 @@ typedef struct stat_block {
188 u32 txf_rd_cnt; 197 u32 txf_rd_cnt;
189} StatInfo_t; 198} StatInfo_t;
190 199
191/* Structures representing different init time configuration 200/*
201 * Structures representing different init time configuration
192 * parameters of the NIC. 202 * parameters of the NIC.
193 */ 203 */
194 204
205#define MAX_TX_FIFOS 8
206#define MAX_RX_RINGS 8
207
208/* FIFO mappings for all possible number of fifos configured */
209int fifo_map[][MAX_TX_FIFOS] = {
210 {0, 0, 0, 0, 0, 0, 0, 0},
211 {0, 0, 0, 0, 1, 1, 1, 1},
212 {0, 0, 0, 1, 1, 1, 2, 2},
213 {0, 0, 1, 1, 2, 2, 3, 3},
214 {0, 0, 1, 1, 2, 2, 3, 4},
215 {0, 0, 1, 1, 2, 3, 4, 5},
216 {0, 0, 1, 2, 3, 4, 5, 6},
217 {0, 1, 2, 3, 4, 5, 6, 7},
218};
219
195/* Maintains Per FIFO related information. */ 220/* Maintains Per FIFO related information. */
196typedef struct tx_fifo_config { 221typedef struct tx_fifo_config {
197#define MAX_AVAILABLE_TXDS 8192 222#define MAX_AVAILABLE_TXDS 8192
@@ -237,14 +262,14 @@ typedef struct rx_ring_config {
237#define NO_SNOOP_RXD_BUFFER 0x02 262#define NO_SNOOP_RXD_BUFFER 0x02
238} rx_ring_config_t; 263} rx_ring_config_t;
239 264
240/* This structure provides contains values of the tunable parameters 265/* This structure provides contains values of the tunable parameters
241 * of the H/W 266 * of the H/W
242 */ 267 */
243struct config_param { 268struct config_param {
244/* Tx Side */ 269/* Tx Side */
245 u32 tx_fifo_num; /*Number of Tx FIFOs */ 270 u32 tx_fifo_num; /*Number of Tx FIFOs */
246#define MAX_TX_FIFOS 8
247 271
272 u8 fifo_mapping[MAX_TX_FIFOS];
248 tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */ 273 tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
249 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */ 274 u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
250 u64 tx_intr_type; 275 u64 tx_intr_type;
@@ -252,7 +277,6 @@ struct config_param {
252 277
253/* Rx Side */ 278/* Rx Side */
254 u32 rx_ring_num; /*Number of receive rings */ 279 u32 rx_ring_num; /*Number of receive rings */
255#define MAX_RX_RINGS 8
256#define MAX_RX_BLOCKS_PER_RING 150 280#define MAX_RX_BLOCKS_PER_RING 150
257 281
258 rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */ 282 rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
@@ -269,6 +293,7 @@ struct config_param {
269#define MAX_PYLD_JUMBO 9600 293#define MAX_PYLD_JUMBO 9600
270#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18) 294#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
271#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22) 295#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
296 u16 bus_speed;
272}; 297};
273 298
274/* Structure representing MAC Addrs */ 299/* Structure representing MAC Addrs */
@@ -277,7 +302,7 @@ typedef struct mac_addr {
277} macaddr_t; 302} macaddr_t;
278 303
279/* Structure that represent every FIFO element in the BAR1 304/* Structure that represent every FIFO element in the BAR1
280 * Address location. 305 * Address location.
281 */ 306 */
282typedef struct _TxFIFO_element { 307typedef struct _TxFIFO_element {
283 u64 TxDL_Pointer; 308 u64 TxDL_Pointer;
@@ -339,6 +364,7 @@ typedef struct _RxD_t {
339#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8) 364#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
340#define RXD_FRAME_PROTO_IPV4 BIT(27) 365#define RXD_FRAME_PROTO_IPV4 BIT(27)
341#define RXD_FRAME_PROTO_IPV6 BIT(28) 366#define RXD_FRAME_PROTO_IPV6 BIT(28)
367#define RXD_FRAME_IP_FRAG BIT(29)
342#define RXD_FRAME_PROTO_TCP BIT(30) 368#define RXD_FRAME_PROTO_TCP BIT(30)
343#define RXD_FRAME_PROTO_UDP BIT(31) 369#define RXD_FRAME_PROTO_UDP BIT(31)
344#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP) 370#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
@@ -347,10 +373,10 @@ typedef struct _RxD_t {
347 373
348 u64 Control_2; 374 u64 Control_2;
349#ifndef CONFIG_2BUFF_MODE 375#ifndef CONFIG_2BUFF_MODE
350#define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16) 376#define MASK_BUFFER0_SIZE vBIT(0x3FFF,2,14)
351#define SET_BUFFER0_SIZE(val) vBIT(val,0,16) 377#define SET_BUFFER0_SIZE(val) vBIT(val,2,14)
352#else 378#else
353#define MASK_BUFFER0_SIZE vBIT(0xFF,0,16) 379#define MASK_BUFFER0_SIZE vBIT(0xFF,2,14)
354#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16) 380#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
355#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16) 381#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
356#define SET_BUFFER0_SIZE(val) vBIT(val,8,8) 382#define SET_BUFFER0_SIZE(val) vBIT(val,8,8)
@@ -363,7 +389,7 @@ typedef struct _RxD_t {
363#define SET_NUM_TAG(val) vBIT(val,16,32) 389#define SET_NUM_TAG(val) vBIT(val,16,32)
364 390
365#ifndef CONFIG_2BUFF_MODE 391#ifndef CONFIG_2BUFF_MODE
366#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16))) 392#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0x3FFF,2,14)))
367#else 393#else
368#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \ 394#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
369 >> 48) 395 >> 48)
@@ -382,7 +408,7 @@ typedef struct _RxD_t {
382#endif 408#endif
383} RxD_t; 409} RxD_t;
384 410
385/* Structure that represents the Rx descriptor block which contains 411/* Structure that represents the Rx descriptor block which contains
386 * 128 Rx descriptors. 412 * 128 Rx descriptors.
387 */ 413 */
388#ifndef CONFIG_2BUFF_MODE 414#ifndef CONFIG_2BUFF_MODE
@@ -392,11 +418,11 @@ typedef struct _RxD_block {
392 418
393 u64 reserved_0; 419 u64 reserved_0;
394#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL 420#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
395 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last 421 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
396 * Rxd in this blk */ 422 * Rxd in this blk */
397 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */ 423 u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
398 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch 424 u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
399 * the upper 32 bits should 425 * the upper 32 bits should
400 * be 0 */ 426 * be 0 */
401} RxD_block_t; 427} RxD_block_t;
402#else 428#else
@@ -405,13 +431,13 @@ typedef struct _RxD_block {
405 RxD_t rxd[MAX_RXDS_PER_BLOCK]; 431 RxD_t rxd[MAX_RXDS_PER_BLOCK];
406 432
407#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL 433#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
408 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd 434 u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
409 * in this blk */ 435 * in this blk */
410 u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */ 436 u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */
411} RxD_block_t; 437} RxD_block_t;
412#define SIZE_OF_BLOCK 4096 438#define SIZE_OF_BLOCK 4096
413 439
414/* Structure to hold virtual addresses of Buf0 and Buf1 in 440/* Structure to hold virtual addresses of Buf0 and Buf1 in
415 * 2buf mode. */ 441 * 2buf mode. */
416typedef struct bufAdd { 442typedef struct bufAdd {
417 void *ba_0_org; 443 void *ba_0_org;
@@ -423,8 +449,8 @@ typedef struct bufAdd {
423 449
424/* Structure which stores all the MAC control parameters */ 450/* Structure which stores all the MAC control parameters */
425 451
426/* This structure stores the offset of the RxD in the ring 452/* This structure stores the offset of the RxD in the ring
427 * from which the Rx Interrupt processor can start picking 453 * from which the Rx Interrupt processor can start picking
428 * up the RxDs for processing. 454 * up the RxDs for processing.
429 */ 455 */
430typedef struct _rx_curr_get_info_t { 456typedef struct _rx_curr_get_info_t {
@@ -436,7 +462,7 @@ typedef struct _rx_curr_get_info_t {
436typedef rx_curr_get_info_t rx_curr_put_info_t; 462typedef rx_curr_get_info_t rx_curr_put_info_t;
437 463
438/* This structure stores the offset of the TxDl in the FIFO 464/* This structure stores the offset of the TxDl in the FIFO
439 * from which the Tx Interrupt processor can start picking 465 * from which the Tx Interrupt processor can start picking
440 * up the TxDLs for send complete interrupt processing. 466 * up the TxDLs for send complete interrupt processing.
441 */ 467 */
442typedef struct { 468typedef struct {
@@ -446,32 +472,96 @@ typedef struct {
446 472
447typedef tx_curr_get_info_t tx_curr_put_info_t; 473typedef tx_curr_get_info_t tx_curr_put_info_t;
448 474
449/* Infomation related to the Tx and Rx FIFOs and Rings of Xena 475/* Structure that holds the Phy and virt addresses of the Blocks */
450 * is maintained in this structure. 476typedef struct rx_block_info {
451 */ 477 RxD_t *block_virt_addr;
452typedef struct mac_info { 478 dma_addr_t block_dma_addr;
453/* rx side stuff */ 479} rx_block_info_t;
454 /* Put pointer info which indictes which RxD has to be replenished 480
481/* pre declaration of the nic structure */
482typedef struct s2io_nic nic_t;
483
484/* Ring specific structure */
485typedef struct ring_info {
486 /* The ring number */
487 int ring_no;
488
489 /*
490 * Place holders for the virtual and physical addresses of
491 * all the Rx Blocks
492 */
493 rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING];
494 int block_count;
495 int pkt_cnt;
496
497 /*
498 * Put pointer info which indictes which RxD has to be replenished
455 * with a new buffer. 499 * with a new buffer.
456 */ 500 */
457 rx_curr_put_info_t rx_curr_put_info[MAX_RX_RINGS]; 501 rx_curr_put_info_t rx_curr_put_info;
458 502
459 /* Get pointer info which indictes which is the last RxD that was 503 /*
504 * Get pointer info which indictes which is the last RxD that was
460 * processed by the driver. 505 * processed by the driver.
461 */ 506 */
462 rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS]; 507 rx_curr_get_info_t rx_curr_get_info;
463 508
464 u16 rmac_pause_time; 509#ifndef CONFIG_S2IO_NAPI
465 u16 mc_pause_threshold_q0q3; 510 /* Index to the absolute position of the put pointer of Rx ring */
466 u16 mc_pause_threshold_q4q7; 511 int put_pos;
512#endif
513
514#ifdef CONFIG_2BUFF_MODE
515 /* Buffer Address store. */
516 buffAdd_t **ba;
517#endif
518 nic_t *nic;
519} ring_info_t;
467 520
521/* Fifo specific structure */
522typedef struct fifo_info {
523 /* FIFO number */
524 int fifo_no;
525
526 /* Maximum TxDs per TxDL */
527 int max_txds;
528
529 /* Place holder of all the TX List's Phy and Virt addresses. */
530 list_info_hold_t *list_info;
531
532 /*
533 * Current offset within the tx FIFO where driver would write
534 * new Tx frame
535 */
536 tx_curr_put_info_t tx_curr_put_info;
537
538 /*
539 * Current offset within tx FIFO from where the driver would start freeing
540 * the buffers
541 */
542 tx_curr_get_info_t tx_curr_get_info;
543
544 nic_t *nic;
545}fifo_info_t;
546
547/* Infomation related to the Tx and Rx FIFOs and Rings of Xena
548 * is maintained in this structure.
549 */
550typedef struct mac_info {
468/* tx side stuff */ 551/* tx side stuff */
469 /* logical pointer of start of each Tx FIFO */ 552 /* logical pointer of start of each Tx FIFO */
470 TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS]; 553 TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS];
471 554
472/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/ 555 /* Fifo specific structure */
473 tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS]; 556 fifo_info_t fifos[MAX_TX_FIFOS];
474 tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS]; 557
558/* rx side stuff */
559 /* Ring specific structure */
560 ring_info_t rings[MAX_RX_RINGS];
561
562 u16 rmac_pause_time;
563 u16 mc_pause_threshold_q0q3;
564 u16 mc_pause_threshold_q4q7;
475 565
476 void *stats_mem; /* orignal pointer to allocated mem */ 566 void *stats_mem; /* orignal pointer to allocated mem */
477 dma_addr_t stats_mem_phy; /* Physical address of the stat block */ 567 dma_addr_t stats_mem_phy; /* Physical address of the stat block */
@@ -485,12 +575,6 @@ typedef struct {
485 int usage_cnt; 575 int usage_cnt;
486} usr_addr_t; 576} usr_addr_t;
487 577
488/* Structure that holds the Phy and virt addresses of the Blocks */
489typedef struct rx_block_info {
490 RxD_t *block_virt_addr;
491 dma_addr_t block_dma_addr;
492} rx_block_info_t;
493
494/* Default Tunable parameters of the NIC. */ 578/* Default Tunable parameters of the NIC. */
495#define DEFAULT_FIFO_LEN 4096 579#define DEFAULT_FIFO_LEN 4096
496#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1) 580#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)
@@ -499,7 +583,20 @@ typedef struct rx_block_info {
499#define LARGE_BLK_CNT 100 583#define LARGE_BLK_CNT 100
500 584
501/* Structure representing one instance of the NIC */ 585/* Structure representing one instance of the NIC */
502typedef struct s2io_nic { 586struct s2io_nic {
587#ifdef CONFIG_S2IO_NAPI
588 /*
589 * Count of packets to be processed in a given iteration, it will be indicated
590 * by the quota field of the device structure when NAPI is enabled.
591 */
592 int pkts_to_process;
593#endif
594 struct net_device *dev;
595 mac_info_t mac_control;
596 struct config_param config;
597 struct pci_dev *pdev;
598 void __iomem *bar0;
599 void __iomem *bar1;
503#define MAX_MAC_SUPPORTED 16 600#define MAX_MAC_SUPPORTED 16
504#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED 601#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
505 602
@@ -507,33 +604,17 @@ typedef struct s2io_nic {
507 macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED]; 604 macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
508 605
509 struct net_device_stats stats; 606 struct net_device_stats stats;
510 void __iomem *bar0;
511 void __iomem *bar1;
512 struct config_param config;
513 mac_info_t mac_control;
514 int high_dma_flag; 607 int high_dma_flag;
515 int device_close_flag; 608 int device_close_flag;
516 int device_enabled_once; 609 int device_enabled_once;
517 610
518 char name[32]; 611 char name[50];
519 struct tasklet_struct task; 612 struct tasklet_struct task;
520 volatile unsigned long tasklet_status; 613 volatile unsigned long tasklet_status;
521 struct timer_list timer;
522 struct net_device *dev;
523 struct pci_dev *pdev;
524 614
525 u16 vendor_id; 615 /* Space to back up the PCI config space */
526 u16 device_id; 616 u32 config_space[256 / sizeof(u32)];
527 u16 ccmd; 617
528 u32 cbar0_1;
529 u32 cbar0_2;
530 u32 cbar1_1;
531 u32 cbar1_2;
532 u32 cirq;
533 u8 cache_line;
534 u32 rom_expansion;
535 u16 pcix_cmd;
536 u32 irq;
537 atomic_t rx_bufs_left[MAX_RX_RINGS]; 618 atomic_t rx_bufs_left[MAX_RX_RINGS];
538 619
539 spinlock_t tx_lock; 620 spinlock_t tx_lock;
@@ -558,27 +639,11 @@ typedef struct s2io_nic {
558 u16 tx_err_count; 639 u16 tx_err_count;
559 u16 rx_err_count; 640 u16 rx_err_count;
560 641
561#ifndef CONFIG_S2IO_NAPI
562 /* Index to the absolute position of the put pointer of Rx ring. */
563 int put_pos[MAX_RX_RINGS];
564#endif
565
566 /*
567 * Place holders for the virtual and physical addresses of
568 * all the Rx Blocks
569 */
570 rx_block_info_t rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
571 int block_count[MAX_RX_RINGS];
572 int pkt_cnt[MAX_RX_RINGS];
573
574 /* Place holder of all the TX List's Phy and Virt addresses. */
575 list_info_hold_t *list_info[MAX_TX_FIFOS];
576
577 /* Id timer, used to blink NIC to physically identify NIC. */ 642 /* Id timer, used to blink NIC to physically identify NIC. */
578 struct timer_list id_timer; 643 struct timer_list id_timer;
579 644
580 /* Restart timer, used to restart NIC if the device is stuck and 645 /* Restart timer, used to restart NIC if the device is stuck and
581 * a schedule task that will set the correct Link state once the 646 * a schedule task that will set the correct Link state once the
582 * NIC's PHY has stabilized after a state change. 647 * NIC's PHY has stabilized after a state change.
583 */ 648 */
584#ifdef INIT_TQUEUE 649#ifdef INIT_TQUEUE
@@ -589,12 +654,12 @@ typedef struct s2io_nic {
589 struct work_struct set_link_task; 654 struct work_struct set_link_task;
590#endif 655#endif
591 656
592 /* Flag that can be used to turn on or turn off the Rx checksum 657 /* Flag that can be used to turn on or turn off the Rx checksum
593 * offload feature. 658 * offload feature.
594 */ 659 */
595 int rx_csum; 660 int rx_csum;
596 661
597 /* after blink, the adapter must be restored with original 662 /* after blink, the adapter must be restored with original
598 * values. 663 * values.
599 */ 664 */
600 u64 adapt_ctrl_org; 665 u64 adapt_ctrl_org;
@@ -604,16 +669,12 @@ typedef struct s2io_nic {
604#define LINK_DOWN 1 669#define LINK_DOWN 1
605#define LINK_UP 2 670#define LINK_UP 2
606 671
607#ifdef CONFIG_2BUFF_MODE
608 /* Buffer Address store. */
609 buffAdd_t **ba[MAX_RX_RINGS];
610#endif
611 int task_flag; 672 int task_flag;
612#define CARD_DOWN 1 673#define CARD_DOWN 1
613#define CARD_UP 2 674#define CARD_UP 2
614 atomic_t card_state; 675 atomic_t card_state;
615 volatile unsigned long link_state; 676 volatile unsigned long link_state;
616} nic_t; 677};
617 678
618#define RESET_ERROR 1; 679#define RESET_ERROR 1;
619#define CMD_ERROR 2; 680#define CMD_ERROR 2;
@@ -622,9 +683,10 @@ typedef struct s2io_nic {
622#ifndef readq 683#ifndef readq
623static inline u64 readq(void __iomem *addr) 684static inline u64 readq(void __iomem *addr)
624{ 685{
625 u64 ret = readl(addr + 4); 686 u64 ret = 0;
626 ret <<= 32; 687 ret = readl(addr + 4);
627 ret |= readl(addr); 688 (u64) ret <<= 32;
689 (u64) ret |= readl(addr);
628 690
629 return ret; 691 return ret;
630} 692}
@@ -637,10 +699,10 @@ static inline void writeq(u64 val, void __iomem *addr)
637 writel((u32) (val >> 32), (addr + 4)); 699 writel((u32) (val >> 32), (addr + 4));
638} 700}
639 701
640/* In 32 bit modes, some registers have to be written in a 702/* In 32 bit modes, some registers have to be written in a
641 * particular order to expect correct hardware operation. The 703 * particular order to expect correct hardware operation. The
642 * macro SPECIAL_REG_WRITE is used to perform such ordered 704 * macro SPECIAL_REG_WRITE is used to perform such ordered
643 * writes. Defines UF (Upper First) and LF (Lower First) will 705 * writes. Defines UF (Upper First) and LF (Lower First) will
644 * be used to specify the required write order. 706 * be used to specify the required write order.
645 */ 707 */
646#define UF 1 708#define UF 1
@@ -716,6 +778,7 @@ static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
716#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate 778#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
717 PCC_FB_ECC Error. */ 779 PCC_FB_ECC Error. */
718 780
781#define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG)
719/* 782/*
720 * Prototype declaration. 783 * Prototype declaration.
721 */ 784 */
@@ -725,36 +788,29 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev);
725static int init_shared_mem(struct s2io_nic *sp); 788static int init_shared_mem(struct s2io_nic *sp);
726static void free_shared_mem(struct s2io_nic *sp); 789static void free_shared_mem(struct s2io_nic *sp);
727static int init_nic(struct s2io_nic *nic); 790static int init_nic(struct s2io_nic *nic);
728#ifndef CONFIG_S2IO_NAPI 791static void rx_intr_handler(ring_info_t *ring_data);
729static void rx_intr_handler(struct s2io_nic *sp); 792static void tx_intr_handler(fifo_info_t *fifo_data);
730#endif
731static void tx_intr_handler(struct s2io_nic *sp);
732static void alarm_intr_handler(struct s2io_nic *sp); 793static void alarm_intr_handler(struct s2io_nic *sp);
733 794
734static int s2io_starter(void); 795static int s2io_starter(void);
735static void s2io_closer(void); 796void s2io_closer(void);
736static void s2io_tx_watchdog(struct net_device *dev); 797static void s2io_tx_watchdog(struct net_device *dev);
737static void s2io_tasklet(unsigned long dev_addr); 798static void s2io_tasklet(unsigned long dev_addr);
738static void s2io_set_multicast(struct net_device *dev); 799static void s2io_set_multicast(struct net_device *dev);
739#ifndef CONFIG_2BUFF_MODE 800static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp);
740static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no); 801void s2io_link(nic_t * sp, int link);
741#else 802void s2io_reset(nic_t * sp);
742static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no, 803#if defined(CONFIG_S2IO_NAPI)
743 buffAdd_t * ba);
744#endif
745static void s2io_link(nic_t * sp, int link);
746static void s2io_reset(nic_t * sp);
747#ifdef CONFIG_S2IO_NAPI
748static int s2io_poll(struct net_device *dev, int *budget); 804static int s2io_poll(struct net_device *dev, int *budget);
749#endif 805#endif
750static void s2io_init_pci(nic_t * sp); 806static void s2io_init_pci(nic_t * sp);
751static int s2io_set_mac_addr(struct net_device *dev, u8 * addr); 807int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
752static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs); 808static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
753static int verify_xena_quiescence(u64 val64, int flag); 809static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
754static struct ethtool_ops netdev_ethtool_ops; 810static struct ethtool_ops netdev_ethtool_ops;
755static void s2io_set_link(unsigned long data); 811static void s2io_set_link(unsigned long data);
756static int s2io_set_swapper(nic_t * sp); 812int s2io_set_swapper(nic_t * sp);
757static void s2io_card_down(nic_t * nic); 813static void s2io_card_down(nic_t *nic);
758static int s2io_card_up(nic_t * nic); 814static int s2io_card_up(nic_t *nic);
759 815int get_xena_rev_id(struct pci_dev *pdev);
760#endif /* _S2IO_H */ 816#endif /* _S2IO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 11:06:53 -0500