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authorSteven Toth <stoth@hauppauge.com>2008-05-01 04:02:58 -0400
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-05-14 01:56:37 -0400
commita8214d48e6d41f3a16c1023ca4f30bbd140ba756 (patch)
treeb75eb3be887e4a6e3f95195132e4603af9406a74 /drivers
parent2637d5b498b979b46a01690d22ecca1e5b79b903 (diff)
V4L/DVB (7865): mxl5005s: Cleanup #2
Cleanup #2 Signed-off-by: Steven Toth <stoth@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/media/common/tuners/mxl5005s.c907
1 files changed, 271 insertions, 636 deletions
diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c
index 3c4330614faf..2af14de737e9 100644
--- a/drivers/media/common/tuners/mxl5005s.c
+++ b/drivers/media/common/tuners/mxl5005s.c
@@ -22,71 +22,10 @@
22 * Revision: 080314 - original version 22 * Revision: 080314 - original version
23 */ 23 */
24 24
25
26/**
27
28@file
29
30@brief MxL5005S tuner module definition
31
32One can manipulate MxL5005S tuner through MxL5005S module.
33MxL5005S module is derived from tuner module.
34
35*/
36
37
38#include "mxl5005s.h" 25#include "mxl5005s.h"
39 26
40/**
41
42@defgroup MXL5005S_TUNER_MODULE MxL5005S tuner module
43
44MxL5005S tuner module is drived from tuner base module.
45
46@see TUNER_BASE_MODULE
47
48*/
49
50
51
52
53
54/**
55 27
56@defgroup MXL5005S_MODULE_BUILDER MxL5005S module builder 28void BuildMxl5005sModule(
57@ingroup MXL5005S_TUNER_MODULE
58
59One should call MxL5005S module builder before using MxL5005S module.
60
61*/
62/// @{
63
64
65
66
67
68/**
69
70@brief MxL5005S tuner module builder
71
72Use BuildMxl5005sModule() to build MxL5005S module, set all module function pointers with the corresponding functions,
73and initialize module private variables.
74
75
76@param [in] ppTuner Pointer to MxL5005S tuner module pointer
77@param [in] pTunerModuleMemory Pointer to an allocated tuner module memory
78@param [in] pMxl5005sExtraModuleMemory Pointer to an allocated MxL5005S extra module memory
79@param [in] pI2cBridgeModuleMemory Pointer to an allocated I2C bridge module memory
80@param [in] DeviceAddr MxL5005S I2C device address
81@param [in] CrystalFreqHz MxL5005S crystal frequency in Hz
82
83
84@note \n
85 -# One should call BuildMxl5005sModule() to build MxL5005S module before using it.
86
87*/
88void
89BuildMxl5005sModule(
90 TUNER_MODULE **ppTuner, 29 TUNER_MODULE **ppTuner,
91 TUNER_MODULE *pTunerModuleMemory, 30 TUNER_MODULE *pTunerModuleMemory,
92 MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory, 31 MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory,
@@ -200,43 +139,7 @@ BuildMxl5005sModule(
200 return; 139 return;
201} 140}
202 141
203 142void mxl5005s_SetDeviceAddr(
204
205
206
207/// @}
208
209
210
211
212
213/**
214
215@defgroup MXL5005S_MANIPULATING_FUNCTIONS MxL5005S manipulating functions derived from tuner base module
216@ingroup MXL5005S_TUNER_MODULE
217
218One can use the MxL5005S tuner module manipulating interface implemented by MxL5005S manipulating functions to
219manipulate MxL5005S tuner.
220
221*/
222/// @{
223
224
225
226
227
228/**
229
230@brief Set MxL5005S tuner I2C device address.
231
232@note \n
233 -# MxL5005S tuner builder will set TUNER_FP_SET_DEVICE_ADDR() function pointer with mxl5005s_SetDeviceAddr().
234
235@see TUNER_FP_SET_DEVICE_ADDR
236
237*/
238void
239mxl5005s_SetDeviceAddr(
240 TUNER_MODULE *pTuner, 143 TUNER_MODULE *pTuner,
241 unsigned char DeviceAddr 144 unsigned char DeviceAddr
242 ) 145 )
@@ -249,22 +152,7 @@ mxl5005s_SetDeviceAddr(
249 return; 152 return;
250} 153}
251 154
252 155void mxl5005s_GetTunerType(
253
254
255
256/**
257
258@brief Get MxL5005S tuner type.
259
260@note \n
261 -# MxL5005S tuner builder will set TUNER_FP_GET_TUNER_TYPE() function pointer with mxl5005s_GetTunerType().
262
263@see TUNER_FP_GET_TUNER_TYPE
264
265*/
266void
267mxl5005s_GetTunerType(
268 TUNER_MODULE *pTuner, 156 TUNER_MODULE *pTuner,
269 int *pTunerType 157 int *pTunerType
270 ) 158 )
@@ -276,22 +164,7 @@ mxl5005s_GetTunerType(
276 return; 164 return;
277} 165}
278 166
279 167int mxl5005s_GetDeviceAddr(
280
281
282
283/**
284
285@brief Get MxL5005S tuner I2C device address.
286
287@note \n
288 -# MxL5005S tuner builder will set TUNER_FP_GET_DEVICE_ADDR() function pointer with mxl5005s_GetDeviceAddr().
289
290@see TUNER_FP_GET_DEVICE_ADDR
291
292*/
293int
294mxl5005s_GetDeviceAddr(
295 TUNER_MODULE *pTuner, 168 TUNER_MODULE *pTuner,
296 unsigned char *pDeviceAddr 169 unsigned char *pDeviceAddr
297 ) 170 )
@@ -310,22 +183,7 @@ error_status_get_tuner_i2c_device_addr:
310 return FUNCTION_ERROR; 183 return FUNCTION_ERROR;
311} 184}
312 185
313 186int mxl5005s_Initialize(
314
315
316
317/**
318
319@brief Initialize MxL5005S tuner.
320
321@note \n
322 -# MxL5005S tuner builder will set TUNER_FP_INITIALIZE() function pointer with mxl5005s_Initialize().
323
324@see TUNER_FP_INITIALIZE
325
326*/
327int
328mxl5005s_Initialize(
329 struct dvb_usb_device* dib, 187 struct dvb_usb_device* dib,
330 TUNER_MODULE *pTuner 188 TUNER_MODULE *pTuner
331 ) 189 )
@@ -337,16 +195,12 @@ mxl5005s_Initialize(
337 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX]; 195 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
338 int TableLen; 196 int TableLen;
339 197
340
341
342 // Get tuner extra module. 198 // Get tuner extra module.
343 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; 199 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
344 200
345
346 // Get AGC master byte 201 // Get AGC master byte
347 AgcMasterByte = pExtra->AgcMasterByte; 202 AgcMasterByte = pExtra->AgcMasterByte;
348 203
349
350 // Initialize MxL5005S tuner according to MxL5005S tuner example code. 204 // Initialize MxL5005S tuner according to MxL5005S tuner example code.
351 205
352 // Tuner initialization stage 0 206 // Tuner initialization stage 0
@@ -357,37 +211,19 @@ mxl5005s_Initialize(
357 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS) 211 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, LEN_1_BYTE) != FUNCTION_SUCCESS)
358 goto error_status_set_tuner_registers; 212 goto error_status_set_tuner_registers;
359 213
360
361 // Tuner initialization stage 1 214 // Tuner initialization stage 1
362 MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen); 215 MXL_GetInitRegister(&pExtra->MxlDefinedTunerStructure, AddrTable, ByteTable, &TableLen);
363 216
364 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS) 217 if(pExtra->SetRegsWithTable( dib,pTuner, AddrTable, ByteTable, TableLen) != FUNCTION_SUCCESS)
365 goto error_status_set_tuner_registers; 218 goto error_status_set_tuner_registers;
366 219
367
368 return FUNCTION_SUCCESS; 220 return FUNCTION_SUCCESS;
369 221
370
371error_status_set_tuner_registers: 222error_status_set_tuner_registers:
372 return FUNCTION_ERROR; 223 return FUNCTION_ERROR;
373} 224}
374 225
375 226int mxl5005s_SetRfFreqHz(
376
377
378
379/**
380
381@brief Set MxL5005S tuner RF frequency in Hz.
382
383@note \n
384 -# MxL5005S tuner builder will set TUNER_FP_SET_RF_FREQ_HZ() function pointer with mxl5005s_SetRfFreqHz().
385
386@see TUNER_FP_SET_RF_FREQ_HZ
387
388*/
389int
390mxl5005s_SetRfFreqHz(
391 struct dvb_usb_device* dib, 227 struct dvb_usb_device* dib,
392 TUNER_MODULE *pTuner, 228 TUNER_MODULE *pTuner,
393 unsigned long RfFreqHz 229 unsigned long RfFreqHz
@@ -404,8 +240,6 @@ mxl5005s_SetRfFreqHz(
404 unsigned long IfDivval; 240 unsigned long IfDivval;
405 unsigned char MasterControlByte; 241 unsigned char MasterControlByte;
406 242
407
408
409 // Get tuner extra module and base interface module. 243 // Get tuner extra module and base interface module.
410 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra; 244 pExtra = (MXL5005S_EXTRA_MODULE *)pTuner->pExtra;
411 pBaseInterface = pTuner->pBaseInterface; 245 pBaseInterface = pTuner->pBaseInterface;
@@ -476,22 +310,7 @@ error_status_set_tuner_registers:
476 return FUNCTION_ERROR; 310 return FUNCTION_ERROR;
477} 311}
478 312
479 313int mxl5005s_GetRfFreqHz(
480
481
482
483/**
484
485@brief Get MxL5005S tuner RF frequency in Hz.
486
487@note \n
488 -# MxL5005S tuner builder will set TUNER_FP_GET_RF_FREQ_HZ() function pointer with mxl5005s_GetRfFreqHz().
489
490@see TUNER_FP_GET_RF_FREQ_HZ
491
492*/
493int
494mxl5005s_GetRfFreqHz(
495 struct dvb_usb_device* dib, 314 struct dvb_usb_device* dib,
496 TUNER_MODULE *pTuner, 315 TUNER_MODULE *pTuner,
497 unsigned long *pRfFreqHz 316 unsigned long *pRfFreqHz
@@ -511,18 +330,7 @@ error_status_get_tuner_rf_frequency:
511 return FUNCTION_ERROR; 330 return FUNCTION_ERROR;
512} 331}
513 332
514 333int mxl5005s_SetRegsWithTable(
515
516
517
518/**
519
520@brief Set MxL5005S tuner registers with table.
521
522*/
523/*
524int
525mxl5005s_SetRegsWithTable(
526 struct dvb_usb_device* dib, 334 struct dvb_usb_device* dib,
527 TUNER_MODULE *pTuner, 335 TUNER_MODULE *pTuner,
528 unsigned char *pAddrTable, 336 unsigned char *pAddrTable,
@@ -585,11 +393,8 @@ mxl5005s_SetRegsWithTable(
585error_status_set_tuner_registers: 393error_status_set_tuner_registers:
586 return FUNCTION_ERROR; 394 return FUNCTION_ERROR;
587} 395}
588*/
589
590 396
591int 397int mxl5005s_SetRegsWithTable(
592mxl5005s_SetRegsWithTable(
593 struct dvb_usb_device* dib, 398 struct dvb_usb_device* dib,
594 TUNER_MODULE *pTuner, 399 TUNER_MODULE *pTuner,
595 unsigned char *pAddrTable, 400 unsigned char *pAddrTable,
@@ -618,17 +423,7 @@ mxl5005s_SetRegsWithTable(
618 return FUNCTION_SUCCESS; 423 return FUNCTION_SUCCESS;
619} 424}
620 425
621 426int mxl5005s_SetRegMaskBits(
622
623
624
625/**
626
627@brief Set MxL5005S tuner register bits.
628
629*/
630int
631mxl5005s_SetRegMaskBits(
632 struct dvb_usb_device* dib, 427 struct dvb_usb_device* dib,
633 TUNER_MODULE *pTuner, 428 TUNER_MODULE *pTuner,
634 unsigned char RegAddr, 429 unsigned char RegAddr,
@@ -685,17 +480,7 @@ error_status_set_tuner_registers:
685 return FUNCTION_ERROR; 480 return FUNCTION_ERROR;
686} 481}
687 482
688 483int mxl5005s_SetSpectrumMode(
689
690
691
692/**
693
694@brief Set MxL5005S tuner spectrum mode.
695
696*/
697int
698mxl5005s_SetSpectrumMode(
699 struct dvb_usb_device* dib, 484 struct dvb_usb_device* dib,
700 TUNER_MODULE *pTuner, 485 TUNER_MODULE *pTuner,
701 int SpectrumMode 486 int SpectrumMode
@@ -730,17 +515,7 @@ error_status_set_tuner_registers:
730 return FUNCTION_ERROR; 515 return FUNCTION_ERROR;
731} 516}
732 517
733 518int mxl5005s_SetBandwidthHz(
734
735
736
737/**
738
739@brief Set MxL5005S tuner bandwidth in Hz.
740
741*/
742int
743mxl5005s_SetBandwidthHz(
744 struct dvb_usb_device* dib, 519 struct dvb_usb_device* dib,
745 TUNER_MODULE *pTuner, 520 TUNER_MODULE *pTuner,
746 unsigned long BandwidthHz 521 unsigned long BandwidthHz
@@ -777,48 +552,7 @@ error_status_set_tuner_registers:
777 return FUNCTION_ERROR; 552 return FUNCTION_ERROR;
778} 553}
779 554
780 555void mxl5005s_SetI2cBridgeModuleTunerArg(TUNER_MODULE *pTuner)
781
782
783
784/// @}
785
786
787
788
789
790/**
791
792@defgroup MXL5005S_DEPENDENCE MxL5005S dependence
793@ingroup MXL5005S_TUNER_MODULE
794
795MxL5005S dependence is the related functions for MxL5005S tuner module interface.
796One should not use MxL5005S dependence directly.
797
798*/
799/// @{
800
801
802
803
804
805/**
806
807@brief Set I2C bridge module tuner arguments.
808
809MxL5005S builder will use mxl5005s_SetI2cBridgeModuleTunerArg() to set I2C bridge module tuner arguments.
810
811
812@param [in] pTuner The tuner module pointer
813
814
815@see BuildMxl5005sModule()
816
817*/
818void
819mxl5005s_SetI2cBridgeModuleTunerArg(
820 TUNER_MODULE *pTuner
821 )
822{ 556{
823 I2C_BRIDGE_MODULE *pI2cBridge; 557 I2C_BRIDGE_MODULE *pI2cBridge;
824 558
@@ -834,50 +568,9 @@ mxl5005s_SetI2cBridgeModuleTunerArg(
834 return; 568 return;
835} 569}
836 570
837
838
839
840
841/// @}
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865// The following context is source code provided by MaxLinear. 571// The following context is source code provided by MaxLinear.
866
867
868
869
870
871// MaxLinear source code - MXL5005_Initialize.cpp 572// MaxLinear source code - MXL5005_Initialize.cpp
872 573u16 MXL5005_RegisterInit(Tuner_struct *Tuner)
873
874
875//#ifdef _MXL_HEADER
876//#include "stdafx.h"
877//#endif
878//#include "MXL5005_c.h"
879
880_u16 MXL5005_RegisterInit (Tuner_struct * Tuner)
881{ 574{
882 Tuner->TunerRegs_Num = TUNER_REGS_NUM ; 575 Tuner->TunerRegs_Num = TUNER_REGS_NUM ;
883// Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ; 576// Tuner->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ;
@@ -1197,7 +890,7 @@ _u16 MXL5005_RegisterInit (Tuner_struct * Tuner)
1197 return 0 ; 890 return 0 ;
1198} 891}
1199 892
1200_u16 MXL5005_ControlInit (Tuner_struct *Tuner) 893u16 MXL5005_ControlInit(Tuner_struct *Tuner)
1201{ 894{
1202 Tuner->Init_Ctrl_Num = INITCTRL_NUM ; 895 Tuner->Init_Ctrl_Num = INITCTRL_NUM ;
1203 896
@@ -2136,34 +1829,10 @@ _u16 MXL5005_ControlInit (Tuner_struct *Tuner)
2136 return 0 ; 1829 return 0 ;
2137} 1830}
2138 1831
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153// MaxLinear source code - MXL5005_c.cpp 1832// MaxLinear source code - MXL5005_c.cpp
2154
2155
2156
2157// MXL5005.cpp : Defines the initialization routines for the DLL. 1833// MXL5005.cpp : Defines the initialization routines for the DLL.
2158// 2.6.12 1834// 2.6.12
2159 1835
2160
2161//#ifdef _MXL_HEADER
2162//#include "stdafx.h"
2163//#endif
2164//#include "MXL5005_c.h"
2165
2166
2167void InitTunerControls(Tuner_struct *Tuner) 1836void InitTunerControls(Tuner_struct *Tuner)
2168{ 1837{
2169 MXL5005_RegisterInit(Tuner) ; 1838 MXL5005_RegisterInit(Tuner) ;
@@ -2173,8 +1842,6 @@ void InitTunerControls(Tuner_struct *Tuner)
2173#endif 1842#endif
2174} 1843}
2175 1844
2176
2177
2178/////////////////////////////////////////////////////////////////////////////// 1845///////////////////////////////////////////////////////////////////////////////
2179// // 1846// //
2180// Function: MXL_ConfigTuner // 1847// Function: MXL_ConfigTuner //
@@ -2184,7 +1851,7 @@ void InitTunerControls(Tuner_struct *Tuner)
2184// // 1851// //
2185// // 1852// //
2186// Functions used: // 1853// Functions used: //
2187// MXL_SynthIFLO_Calc // 1854// MXL_SynthIFLO_Calc //
2188// // 1855// //
2189// Inputs: // 1856// Inputs: //
2190// Tuner_struct: structure defined at higher level // 1857// Tuner_struct: structure defined at higher level //
@@ -2193,12 +1860,12 @@ void InitTunerControls(Tuner_struct *Tuner)
2193// Bandwidth: Filter Channel Bandwidth (in Hz) // 1860// Bandwidth: Filter Channel Bandwidth (in Hz) //
2194// IF_out: Desired IF out Frequency (in Hz) // 1861// IF_out: Desired IF out Frequency (in Hz) //
2195// Fxtal: Crystal Frerquency (in Hz) // 1862// Fxtal: Crystal Frerquency (in Hz) //
2196// TOP: 0: Dual AGC; Value: take over point // 1863// TOP: 0: Dual AGC; Value: take over point //
2197// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) // 1864// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) //
2198// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out // 1865// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out //
2199// DIV_OUT: 0: Div-1; 1: Div-4 // 1866// DIV_OUT: 0: Div-1; 1: Div-4 //
2200// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable // 1867// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable //
2201// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI // 1868// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI //
2202// // 1869// //
2203// Outputs: // 1870// Outputs: //
2204// Tuner // 1871// Tuner //
@@ -2208,26 +1875,26 @@ void InitTunerControls(Tuner_struct *Tuner)
2208// > 0 : Failed // 1875// > 0 : Failed //
2209// // 1876// //
2210/////////////////////////////////////////////////////////////////////////////// 1877///////////////////////////////////////////////////////////////////////////////
2211_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, 1878u16 MXL5005_TunerConfig(Tuner_struct *Tuner,
2212 _u8 Mode, // 0: Analog Mode ; 1: Digital Mode 1879 u8 Mode, // 0: Analog Mode ; 1: Digital Mode
2213 _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF 1880 u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF
2214 _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) 1881 u32 Bandwidth, // filter channel bandwidth (6, 7, 8)
2215 _u32 IF_out, // Desired IF Out Frequency 1882 u32 IF_out, // Desired IF Out Frequency
2216 _u32 Fxtal, // XTAL Frequency 1883 u32 Fxtal, // XTAL Frequency
2217 _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 1884 u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1
2218 _u16 TOP, // 0: Dual AGC; Value: take over point 1885 u16 TOP, // 0: Dual AGC; Value: take over point
2219 _u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms) 1886 u16 IF_OUT_LOAD, // IF Out Load Resistor (200 / 300 Ohms)
2220 _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out 1887 u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out
2221 _u8 DIV_OUT, // 0: Div-1; 1: Div-4 1888 u8 DIV_OUT, // 0: Div-1; 1: Div-4
2222 _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable 1889 u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable
2223 _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI 1890 u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI
2224 _u8 Mod_Type, // Modulation Type; 1891 u8 Mod_Type, // Modulation Type;
2225 // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable 1892 // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable
2226 _u8 TF_Type // Tracking Filter 1893 u8 TF_Type // Tracking Filter
2227 // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H 1894 // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H
2228 ) 1895 )
2229{ 1896{
2230 _u16 status = 0 ; 1897 u16 status = 0 ;
2231 1898
2232 Tuner->Mode = Mode ; 1899 Tuner->Mode = Mode ;
2233 Tuner->IF_Mode = IF_mode ; 1900 Tuner->IF_Mode = IF_mode ;
@@ -2244,15 +1911,10 @@ _u16 MXL5005_TunerConfig(Tuner_struct *Tuner,
2244 Tuner->Mod_Type = Mod_Type ; 1911 Tuner->Mod_Type = Mod_Type ;
2245 Tuner->TF_Type = TF_Type ; 1912 Tuner->TF_Type = TF_Type ;
2246 1913
2247 1914 /* Initialize all the controls and registers */
2248
2249 //
2250 // Initialize all the controls and registers
2251 //
2252 InitTunerControls (Tuner) ; 1915 InitTunerControls (Tuner) ;
2253 // 1916
2254 // Synthesizer LO frequency calculation 1917 /* Synthesizer LO frequency calculation */
2255 //
2256 MXL_SynthIFLO_Calc( Tuner ) ; 1918 MXL_SynthIFLO_Calc( Tuner ) ;
2257 1919
2258 return status ; 1920 return status ;
@@ -2366,9 +2028,9 @@ void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner)
2366// > 0 : Failed // 2028// > 0 : Failed //
2367// // 2029// //
2368/////////////////////////////////////////////////////////////////////////////// 2030///////////////////////////////////////////////////////////////////////////////
2369_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) 2031u16 MXL_OverwriteICDefault( Tuner_struct *Tuner)
2370{ 2032{
2371 _u16 status = 0 ; 2033 u16 status = 0 ;
2372 2034
2373 status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ; 2035 status += MXL_ControlWrite(Tuner, OVERRIDE_1, 1) ;
2374 status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ; 2036 status += MXL_ControlWrite(Tuner, OVERRIDE_2, 1) ;
@@ -2403,20 +2065,20 @@ _u16 MXL_OverwriteICDefault( Tuner_struct *Tuner)
2403// > 0 : Failed // 2065// > 0 : Failed //
2404// // 2066// //
2405/////////////////////////////////////////////////////////////////////////////// 2067///////////////////////////////////////////////////////////////////////////////
2406_u16 MXL_BlockInit( Tuner_struct *Tuner ) 2068u16 MXL_BlockInit( Tuner_struct *Tuner )
2407{ 2069{
2408 _u16 status = 0 ; 2070 u16 status = 0 ;
2409 2071
2410 status += MXL_OverwriteICDefault(Tuner) ; 2072 status += MXL_OverwriteICDefault(Tuner) ;
2411 2073
2412 // 2074 //
2413 // Downconverter Control 2075 // Downconverter Control
2414 // Dig Ana 2076 // Dig Ana
2415 status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ; 2077 status += MXL_ControlWrite(Tuner, DN_IQTN_AMP_CUT, Tuner->Mode ? 1 : 0) ;
2416 2078
2417 // 2079 //
2418 // Filter Control 2080 // Filter Control
2419 // Dig Ana 2081 // Dig Ana
2420 status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ; 2082 status += MXL_ControlWrite(Tuner, BB_MODE, Tuner->Mode ? 0 : 1) ;
2421 status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ; 2083 status += MXL_ControlWrite(Tuner, BB_BUF, Tuner->Mode ? 3 : 2) ;
2422 status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ; 2084 status += MXL_ControlWrite(Tuner, BB_BUF_OA, Tuner->Mode ? 1 : 0) ;
@@ -2439,7 +2101,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner )
2439 } 2101 }
2440 } else { // Analog Mode 2102 } else { // Analog Mode
2441 switch (Tuner->Chan_Bandwidth) { 2103 switch (Tuner->Chan_Bandwidth) {
2442 case 8000000: // Low Zero 2104 case 8000000: // Low Zero
2443 status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ; 2105 status += MXL_ControlWrite(Tuner, BB_ALPF_BANDSELECT, (Tuner->IF_Mode ? 0 : 3)) ;
2444 break ; 2106 break ;
2445 case 7000000: 2107 case 7000000:
@@ -2453,7 +2115,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner )
2453 2115
2454 // 2116 //
2455 // Charge Pump Control 2117 // Charge Pump Control
2456 // Dig Ana 2118 // Dig Ana
2457 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ; 2119 status += MXL_ControlWrite(Tuner, RFSYN_CHP_GAIN, Tuner->Mode ? 5 : 8) ;
2458 status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ; 2120 status += MXL_ControlWrite(Tuner, RFSYN_EN_CHP_HIGAIN, Tuner->Mode ? 1 : 1) ;
2459 status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ; 2121 status += MXL_ControlWrite(Tuner, EN_CHP_LIN_B, Tuner->Mode ? 0 : 0) ;
@@ -2621,8 +2283,6 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner )
2621 // Apply Default value to BB_INITSTATE_DLPF_TUNE 2283 // Apply Default value to BB_INITSTATE_DLPF_TUNE
2622 // 2284 //
2623 2285
2624
2625
2626 // 2286 //
2627 // RSSI Control 2287 // RSSI Control
2628 // 2288 //
@@ -2697,7 +2357,7 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner )
2697 2357
2698 //Tuner->AGC_Mode = 1 ; // Single AGC Mode 2358 //Tuner->AGC_Mode = 1 ; // Single AGC Mode
2699 2359
2700 // Disable RSSI //change here for v2.6.5 2360 // Disable RSSI //change here for v2.6.5
2701 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ; 2361 status += MXL_ControlWrite(Tuner, SEQ_EXTSYNTHCALIF, 1) ;
2702 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ; 2362 status += MXL_ControlWrite(Tuner, SEQ_EXTDCCAL, 1) ;
2703 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ; 2363 status += MXL_ControlWrite(Tuner, AGC_EN_RSSI, 0) ;
@@ -2787,13 +2447,13 @@ _u16 MXL_BlockInit( Tuner_struct *Tuner )
2787// > 0 : Failed // 2447// > 0 : Failed //
2788// // 2448// //
2789/////////////////////////////////////////////////////////////////////////////// 2449///////////////////////////////////////////////////////////////////////////////
2790_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) 2450u16 MXL_IFSynthInit(Tuner_struct * Tuner)
2791{ 2451{
2792 _u16 status = 0 ; 2452 u16 status = 0 ;
2793 // Declare Local Variables 2453 // Declare Local Variables
2794 _u32 Fref = 0 ; 2454 u32 Fref = 0 ;
2795 _u32 Kdbl, intModVal ; 2455 u32 Kdbl, intModVal ;
2796 _u32 fracModVal ; 2456 u32 fracModVal ;
2797 Kdbl = 2 ; 2457 Kdbl = 2 ;
2798 2458
2799 if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL) 2459 if (Tuner->Fxtal >= 12000000UL && Tuner->Fxtal <= 16000000UL)
@@ -2999,8 +2659,6 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner )
2999 fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ; 2659 fracModVal = fracModVal / ((Tuner->Fxtal * Kdbl/2)/1000) ;
3000 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ; 2660 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_IF, fracModVal) ;
3001 2661
3002
3003
3004 return status ; 2662 return status ;
3005} 2663}
3006 2664
@@ -3008,14 +2666,14 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner )
3008// // 2666// //
3009// Function: MXL_GetXtalInt // 2667// Function: MXL_GetXtalInt //
3010// // 2668// //
3011// Description: return the Crystal Integration Value for // 2669// Description: return the Crystal Integration Value for //
3012// TG_VCO_BIAS calculation // 2670// TG_VCO_BIAS calculation //
3013// // 2671// //
3014// Globals: // 2672// Globals: //
3015// NONE // 2673// NONE //
3016// // 2674// //
3017// Functions used: // 2675// Functions used: //
3018// NONE // 2676// NONE //
3019// // 2677// //
3020// Inputs: // 2678// Inputs: //
3021// Crystal Frequency Value in Hz // 2679// Crystal Frequency Value in Hz //
@@ -3028,7 +2686,7 @@ _u16 MXL_IFSynthInit( Tuner_struct * Tuner )
3028// > 0 : Failed // 2686// > 0 : Failed //
3029// // 2687// //
3030/////////////////////////////////////////////////////////////////////////////// 2688///////////////////////////////////////////////////////////////////////////////
3031_u32 MXL_GetXtalInt(_u32 Xtal_Freq) 2689u32 MXL_GetXtalInt(u32 Xtal_Freq)
3032{ 2690{
3033 if ((Xtal_Freq % 1000000) == 0) 2691 if ((Xtal_Freq % 1000000) == 0)
3034 return (Xtal_Freq / 10000) ; 2692 return (Xtal_Freq / 10000) ;
@@ -3048,7 +2706,7 @@ _u32 MXL_GetXtalInt(_u32 Xtal_Freq)
3048// Functions used: // 2706// Functions used: //
3049// MXL_SynthRFTGLO_Calc // 2707// MXL_SynthRFTGLO_Calc //
3050// MXL5005_ControlWrite // 2708// MXL5005_ControlWrite //
3051// MXL_GetXtalInt // 2709// MXL_GetXtalInt //
3052// // 2710// //
3053// Inputs: // 2711// Inputs: //
3054// Tuner : Tuner structure defined at higher level // 2712// Tuner : Tuner structure defined at higher level //
@@ -3060,20 +2718,20 @@ _u32 MXL_GetXtalInt(_u32 Xtal_Freq)
3060// 0 : Successful // 2718// 0 : Successful //
3061// 1 : Unsuccessful // 2719// 1 : Unsuccessful //
3062/////////////////////////////////////////////////////////////////////////////// 2720///////////////////////////////////////////////////////////////////////////////
3063_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) 2721u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq)
3064{ 2722{
3065 // Declare Local Variables 2723 // Declare Local Variables
3066 _u16 status = 0 ; 2724 u16 status = 0 ;
3067 _u32 divider_val, E3, E4, E5, E5A ; 2725 u32 divider_val, E3, E4, E5, E5A ;
3068 _u32 Fmax, Fmin, FmaxBin, FminBin ; 2726 u32 Fmax, Fmin, FmaxBin, FminBin ;
3069 _u32 Kdbl_RF = 2; 2727 u32 Kdbl_RF = 2;
3070 _u32 tg_divval ; 2728 u32 tg_divval ;
3071 _u32 tg_lo ; 2729 u32 tg_lo ;
3072 _u32 Xtal_Int ; 2730 u32 Xtal_Int ;
3073 2731
3074 _u32 Fref_TG; 2732 u32 Fref_TG;
3075 _u32 Fvco; 2733 u32 Fvco;
3076// _u32 temp; 2734// u32 temp;
3077 2735
3078 2736
3079 Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ; 2737 Xtal_Int = MXL_GetXtalInt(Tuner->Fxtal ) ;
@@ -3774,7 +3432,8 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq)
3774 { 3432 {
3775 status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ; 3433 status += MXL_ControlWrite(Tuner, DAC_DIN_A, 0) ;
3776 3434
3777 if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) // if UHF and terrestrial => Turn off Tracking Filter 3435 // if UHF and terrestrial => Turn off Tracking Filter
3436 if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0)
3778 { 3437 {
3779 // Turn off all the banks 3438 // Turn off all the banks
3780 status += MXL_SetGPIO(Tuner, 3, 1) ; 3439 status += MXL_SetGPIO(Tuner, 3, 1) ;
@@ -4089,7 +3748,8 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq)
4089 { 3748 {
4090 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ; 3749 status += MXL_ControlWrite(Tuner, DAC_DIN_B, 0) ;
4091 3750
4092 if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0) //if UHF and terrestrial=> Turn off Tracking Filter 3751 // if UHF and terrestrial=> Turn off Tracking Filter
3752 if (Tuner->RF_IN >= 471000000 && (Tuner->RF_IN - 471000000)%6000000 != 0)
4093 { 3753 {
4094 // Turn off all the banks 3754 // Turn off all the banks
4095 status += MXL_SetGPIO(Tuner, 3, 1) ; 3755 status += MXL_SetGPIO(Tuner, 3, 1) ;
@@ -4181,9 +3841,9 @@ _u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq)
4181 return status ; 3841 return status ;
4182} 3842}
4183 3843
4184_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) 3844u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val)
4185{ 3845{
4186 _u16 status = 0 ; 3846 u16 status = 0 ;
4187 3847
4188 if (GPIO_Num == 1) 3848 if (GPIO_Num == 1)
4189 status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ; 3849 status += MXL_ControlWrite(Tuner, GPIO_1B, GPIO_Val ? 0 : 1) ;
@@ -4247,9 +3907,9 @@ _u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val)
4247// >0 : Value exceed maximum allowed for control number // 3907// >0 : Value exceed maximum allowed for control number //
4248// // 3908// //
4249/////////////////////////////////////////////////////////////////////////////// 3909///////////////////////////////////////////////////////////////////////////////
4250_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) 3910u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value)
4251{ 3911{
4252 _u16 status = 0 ; 3912 u16 status = 0 ;
4253 // Will write ALL Matching Control Name 3913 // Will write ALL Matching Control Name
4254 status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control 3914 status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 1 ) ; // Write Matching INIT Control
4255 status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control 3915 status += MXL_ControlWrite_Group( Tuner, ControlNum, value, 2 ) ; // Write Matching CH Control
@@ -4287,11 +3947,11 @@ _u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value)
4287// 2 : Control name not found // 3947// 2 : Control name not found //
4288// // 3948// //
4289/////////////////////////////////////////////////////////////////////////////// 3949///////////////////////////////////////////////////////////////////////////////
4290_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u16 controlGroup) 3950u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 controlNum, u32 value, u16 controlGroup)
4291{ 3951{
4292 _u16 i, j, k ; 3952 u16 i, j, k ;
4293 _u32 highLimit ; 3953 u32 highLimit ;
4294 _u32 ctrlVal ; 3954 u32 ctrlVal ;
4295 3955
4296 if( controlGroup == 1) // Initial Control 3956 if( controlGroup == 1) // Initial Control
4297 { 3957 {
@@ -4304,11 +3964,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u
4304 { 3964 {
4305 for( j=0; j<Tuner->Init_Ctrl[i].size; j++) 3965 for( j=0; j<Tuner->Init_Ctrl[i].size; j++)
4306 { 3966 {
4307 Tuner->Init_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; 3967 Tuner->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ;
4308 // change the register map accordingly 3968 // change the register map accordingly
4309 MXL_RegWriteBit( Tuner, (_u8)(Tuner->Init_Ctrl[i].addr[j]), 3969 MXL_RegWriteBit( Tuner, (u8)(Tuner->Init_Ctrl[i].addr[j]),
4310 (_u8)(Tuner->Init_Ctrl[i].bit[j]), 3970 (u8)(Tuner->Init_Ctrl[i].bit[j]),
4311 (_u8)((value>>j) & 0x01) ) ; 3971 (u8)((value>>j) & 0x01) ) ;
4312 } 3972 }
4313 ctrlVal = 0 ; 3973 ctrlVal = 0 ;
4314 for(k=0; k<Tuner->Init_Ctrl[i].size; k++) 3974 for(k=0; k<Tuner->Init_Ctrl[i].size; k++)
@@ -4334,11 +3994,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u
4334 { 3994 {
4335 for( j=0; j<Tuner->CH_Ctrl[i].size; j++) 3995 for( j=0; j<Tuner->CH_Ctrl[i].size; j++)
4336 { 3996 {
4337 Tuner->CH_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; 3997 Tuner->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ;
4338 // change the register map accordingly 3998 // change the register map accordingly
4339 MXL_RegWriteBit( Tuner, (_u8)(Tuner->CH_Ctrl[i].addr[j]), 3999 MXL_RegWriteBit( Tuner, (u8)(Tuner->CH_Ctrl[i].addr[j]),
4340 (_u8)(Tuner->CH_Ctrl[i].bit[j]), 4000 (u8)(Tuner->CH_Ctrl[i].bit[j]),
4341 (_u8)((value>>j) & 0x01) ) ; 4001 (u8)((value>>j) & 0x01) ) ;
4342 } 4002 }
4343 ctrlVal = 0 ; 4003 ctrlVal = 0 ;
4344 for(k=0; k<Tuner->CH_Ctrl[i].size; k++) 4004 for(k=0; k<Tuner->CH_Ctrl[i].size; k++)
@@ -4365,11 +4025,11 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u
4365 { 4025 {
4366 for( j=0; j<Tuner->MXL_Ctrl[i].size; j++) 4026 for( j=0; j<Tuner->MXL_Ctrl[i].size; j++)
4367 { 4027 {
4368 Tuner->MXL_Ctrl[i].val[j] = (_u8)((value >> j) & 0x01) ; 4028 Tuner->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01) ;
4369 // change the register map accordingly 4029 // change the register map accordingly
4370 MXL_RegWriteBit( Tuner, (_u8)(Tuner->MXL_Ctrl[i].addr[j]), 4030 MXL_RegWriteBit( Tuner, (u8)(Tuner->MXL_Ctrl[i].addr[j]),
4371 (_u8)(Tuner->MXL_Ctrl[i].bit[j]), 4031 (u8)(Tuner->MXL_Ctrl[i].bit[j]),
4372 (_u8)((value>>j) & 0x01) ) ; 4032 (u8)((value>>j) & 0x01) ) ;
4373 } 4033 }
4374 ctrlVal = 0 ; 4034 ctrlVal = 0 ;
4375 for(k=0; k<Tuner->MXL_Ctrl[i].size; k++) 4035 for(k=0; k<Tuner->MXL_Ctrl[i].size; k++)
@@ -4413,7 +4073,7 @@ _u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 controlNum, _u32 value, _u
4413// -1 : Invalid Register Address // 4073// -1 : Invalid Register Address //
4414// // 4074// //
4415/////////////////////////////////////////////////////////////////////////////// 4075///////////////////////////////////////////////////////////////////////////////
4416_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) 4076u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal)
4417{ 4077{
4418 int i ; 4078 int i ;
4419 4079
@@ -4453,7 +4113,7 @@ _u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal)
4453// -1 : Invalid Register Address // 4113// -1 : Invalid Register Address //
4454// // 4114// //
4455/////////////////////////////////////////////////////////////////////////////// 4115///////////////////////////////////////////////////////////////////////////////
4456_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) 4116u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal)
4457{ 4117{
4458 int i ; 4118 int i ;
4459 4119
@@ -4461,7 +4121,7 @@ _u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal)
4461 { 4121 {
4462 if (RegNum == Tuner->TunerRegs[i].Reg_Num ) 4122 if (RegNum == Tuner->TunerRegs[i].Reg_Num )
4463 { 4123 {
4464 *RegVal = (_u8)(Tuner->TunerRegs[i].Reg_Val) ; 4124 *RegVal = (u8)(Tuner->TunerRegs[i].Reg_Val) ;
4465 return 0 ; 4125 return 0 ;
4466 } 4126 }
4467 } 4127 }
@@ -4490,10 +4150,10 @@ _u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal)
4490// -1 : Invalid control name // 4150// -1 : Invalid control name //
4491// // 4151// //
4492/////////////////////////////////////////////////////////////////////////////// 4152///////////////////////////////////////////////////////////////////////////////
4493_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value) 4153u16 MXL_ControlRead(Tuner_struct *Tuner, u16 controlNum, u32 * value)
4494{ 4154{
4495 _u32 ctrlVal ; 4155 u32 ctrlVal ;
4496 _u16 i, k ; 4156 u16 i, k ;
4497 4157
4498 for (i=0; i<Tuner->Init_Ctrl_Num ; i++) 4158 for (i=0; i<Tuner->Init_Ctrl_Num ; i++)
4499 { 4159 {
@@ -4539,7 +4199,7 @@ _u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value)
4539// Function: MXL_ControlRegRead // 4199// Function: MXL_ControlRegRead //
4540// // 4200// //
4541// Description: Retrieve the register addresses and count related to a // 4201// Description: Retrieve the register addresses and count related to a //
4542// a specific control name // 4202// a specific control name //
4543// // 4203// //
4544// Globals: // 4204// Globals: //
4545// NONE // 4205// NONE //
@@ -4550,24 +4210,24 @@ _u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 controlNum, _u32 * value)
4550// // 4210// //
4551// Outputs: // 4211// Outputs: //
4552// RegNum : returned register address array // 4212// RegNum : returned register address array //
4553// count : returned register count related to a control // 4213// count : returned register count related to a control //
4554// // 4214// //
4555// Return: // 4215// Return: //
4556// 0 : Successful read // 4216// 0 : Successful read //
4557// -1 : Invalid control name // 4217// -1 : Invalid control name //
4558// // 4218// //
4559/////////////////////////////////////////////////////////////////////////////// 4219///////////////////////////////////////////////////////////////////////////////
4560_u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int * count) 4220u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 controlNum, u8 *RegNum, int * count)
4561{ 4221{
4562 _u16 i, j, k ; 4222 u16 i, j, k ;
4563 _u16 Count ; 4223 u16 Count ;
4564 4224
4565 for (i=0; i<Tuner->Init_Ctrl_Num ; i++) 4225 for (i=0; i<Tuner->Init_Ctrl_Num ; i++)
4566 { 4226 {
4567 if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num ) 4227 if ( controlNum == Tuner->Init_Ctrl[i].Ctrl_Num )
4568 { 4228 {
4569 Count = 1 ; 4229 Count = 1 ;
4570 RegNum[0] = (_u8)(Tuner->Init_Ctrl[i].addr[0]) ; 4230 RegNum[0] = (u8)(Tuner->Init_Ctrl[i].addr[0]) ;
4571 4231
4572 for(k=1; k<Tuner->Init_Ctrl[i].size; k++) 4232 for(k=1; k<Tuner->Init_Ctrl[i].size; k++)
4573 { 4233 {
@@ -4576,7 +4236,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int *
4576 if (Tuner->Init_Ctrl[i].addr[k] != RegNum[j]) 4236 if (Tuner->Init_Ctrl[i].addr[k] != RegNum[j])
4577 { 4237 {
4578 Count ++ ; 4238 Count ++ ;
4579 RegNum[Count-1] = (_u8)(Tuner->Init_Ctrl[i].addr[k]) ; 4239 RegNum[Count-1] = (u8)(Tuner->Init_Ctrl[i].addr[k]) ;
4580 } 4240 }
4581 } 4241 }
4582 4242
@@ -4590,7 +4250,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int *
4590 if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num ) 4250 if ( controlNum == Tuner->CH_Ctrl[i].Ctrl_Num )
4591 { 4251 {
4592 Count = 1 ; 4252 Count = 1 ;
4593 RegNum[0] = (_u8)(Tuner->CH_Ctrl[i].addr[0]) ; 4253 RegNum[0] = (u8)(Tuner->CH_Ctrl[i].addr[0]) ;
4594 4254
4595 for(k=1; k<Tuner->CH_Ctrl[i].size; k++) 4255 for(k=1; k<Tuner->CH_Ctrl[i].size; k++)
4596 { 4256 {
@@ -4599,7 +4259,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int *
4599 if (Tuner->CH_Ctrl[i].addr[k] != RegNum[j]) 4259 if (Tuner->CH_Ctrl[i].addr[k] != RegNum[j])
4600 { 4260 {
4601 Count ++ ; 4261 Count ++ ;
4602 RegNum[Count-1] = (_u8)(Tuner->CH_Ctrl[i].addr[k]) ; 4262 RegNum[Count-1] = (u8)(Tuner->CH_Ctrl[i].addr[k]) ;
4603 } 4263 }
4604 } 4264 }
4605 } 4265 }
@@ -4613,7 +4273,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int *
4613 if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num ) 4273 if ( controlNum == Tuner->MXL_Ctrl[i].Ctrl_Num )
4614 { 4274 {
4615 Count = 1 ; 4275 Count = 1 ;
4616 RegNum[0] = (_u8)(Tuner->MXL_Ctrl[i].addr[0]) ; 4276 RegNum[0] = (u8)(Tuner->MXL_Ctrl[i].addr[0]) ;
4617 4277
4618 for(k=1; k<Tuner->MXL_Ctrl[i].size; k++) 4278 for(k=1; k<Tuner->MXL_Ctrl[i].size; k++)
4619 { 4279 {
@@ -4622,7 +4282,7 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int *
4622 if (Tuner->MXL_Ctrl[i].addr[k] != RegNum[j]) 4282 if (Tuner->MXL_Ctrl[i].addr[k] != RegNum[j])
4623 { 4283 {
4624 Count ++ ; 4284 Count ++ ;
4625 RegNum[Count-1] = (_u8)Tuner->MXL_Ctrl[i].addr[k] ; 4285 RegNum[Count-1] = (u8)Tuner->MXL_Ctrl[i].addr[k] ;
4626 } 4286 }
4627 } 4287 }
4628 } 4288 }
@@ -4648,8 +4308,8 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int *
4648// Inputs: // 4308// Inputs: //
4649// Tuner_struct : structure defined at higher level // 4309// Tuner_struct : structure defined at higher level //
4650// address : register address // 4310// address : register address //
4651// bit : register bit number // 4311// bit : register bit number //
4652// bitVal : register bit value // 4312// bitVal : register bit value //
4653// // 4313// //
4654// Outputs: // 4314// Outputs: //
4655// NONE // 4315// NONE //
@@ -4659,16 +4319,16 @@ _u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 controlNum, _u8 *RegNum, int *
4659// // 4319// //
4660/////////////////////////////////////////////////////////////////////////////// 4320///////////////////////////////////////////////////////////////////////////////
4661 4321
4662void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal) 4322void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal)
4663{ 4323{
4664 int i ; 4324 int i ;
4665 4325
4666 // Declare Local Constants 4326 // Declare Local Constants
4667 const _u8 AND_MAP[8] = { 4327 const u8 AND_MAP[8] = {
4668 0xFE, 0xFD, 0xFB, 0xF7, 4328 0xFE, 0xFD, 0xFB, 0xF7,
4669 0xEF, 0xDF, 0xBF, 0x7F } ; 4329 0xEF, 0xDF, 0xBF, 0x7F } ;
4670 4330
4671 const _u8 OR_MAP[8] = { 4331 const u8 OR_MAP[8] = {
4672 0x01, 0x02, 0x04, 0x08, 4332 0x01, 0x02, 0x04, 0x08,
4673 0x10, 0x20, 0x40, 0x80 } ; 4333 0x10, 0x20, 0x40, 0x80 } ;
4674 4334
@@ -4707,7 +4367,7 @@ void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal)
4707// Computed value // 4367// Computed value //
4708// // 4368// //
4709/////////////////////////////////////////////////////////////////////////////// 4369///////////////////////////////////////////////////////////////////////////////
4710_u32 MXL_Ceiling( _u32 value, _u32 resolution ) 4370u32 MXL_Ceiling( u32 value, u32 resolution )
4711{ 4371{
4712 return (value/resolution + (value%resolution > 0 ? 1 : 0)) ; 4372 return (value/resolution + (value%resolution > 0 ? 1 : 0)) ;
4713}; 4373};
@@ -4715,15 +4375,15 @@ _u32 MXL_Ceiling( _u32 value, _u32 resolution )
4715// 4375//
4716// Retrieve the Initialzation Registers 4376// Retrieve the Initialzation Registers
4717// 4377//
4718_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) 4378u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count)
4719{ 4379{
4720 _u16 status = 0; 4380 u16 status = 0;
4721 int i ; 4381 int i ;
4722 4382
4723 _u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73, 4383 u8 RegAddr[] = {11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
4724 76, 77, 91, 134, 135, 137, 147, 4384 76, 77, 91, 134, 135, 137, 147,
4725 156, 166, 167, 168, 25 } ; 4385 156, 166, 167, 168, 25 } ;
4726 *count = sizeof(RegAddr) / sizeof(_u8) ; 4386 *count = sizeof(RegAddr) / sizeof(u8) ;
4727 4387
4728 status += MXL_BlockInit(Tuner) ; 4388 status += MXL_BlockInit(Tuner) ;
4729 4389
@@ -4736,24 +4396,24 @@ _u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *co
4736 return status ; 4396 return status ;
4737} 4397}
4738 4398
4739_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) 4399u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count)
4740{ 4400{
4741 _u16 status = 0; 4401 u16 status = 0;
4742 int i ; 4402 int i ;
4743 4403
4744//add 77, 166, 167, 168 register for 2.6.12 4404//add 77, 166, 167, 168 register for 2.6.12
4745#ifdef _MXL_PRODUCTION 4405#ifdef _MXL_PRODUCTION
4746 _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106, 4406 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
4747 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; 4407 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
4748#else 4408#else
4749 _u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106, 4409 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
4750 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ; 4410 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
4751 //_u8 RegAddr[171]; 4411 //u8 RegAddr[171];
4752 //for (i=0; i<=170; i++) 4412 //for (i=0; i<=170; i++)
4753 // RegAddr[i] = i; 4413 // RegAddr[i] = i;
4754#endif 4414#endif
4755 4415
4756 *count = sizeof(RegAddr) / sizeof(_u8) ; 4416 *count = sizeof(RegAddr) / sizeof(u8) ;
4757 4417
4758 for (i=0 ; i< *count; i++) 4418 for (i=0 ; i< *count; i++)
4759 { 4419 {
@@ -4765,14 +4425,14 @@ _u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *coun
4765 4425
4766} 4426}
4767 4427
4768_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) 4428u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count)
4769{ 4429{
4770 _u16 status = 0 ; 4430 u16 status = 0 ;
4771 int i ; 4431 int i ;
4772 4432
4773 _u8 RegAddr[] = {43, 136} ; 4433 u8 RegAddr[] = {43, 136} ;
4774 4434
4775 *count = sizeof(RegAddr) / sizeof(_u8) ; 4435 *count = sizeof(RegAddr) / sizeof(u8) ;
4776 4436
4777 for (i=0; i<*count; i++) 4437 for (i=0; i<*count; i++)
4778 { 4438 {
@@ -4783,14 +4443,14 @@ _u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, in
4783 4443
4784} 4444}
4785 4445
4786_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) 4446u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count)
4787{ 4447{
4788 _u16 status = 0 ; 4448 u16 status = 0 ;
4789 int i ; 4449 int i ;
4790 4450
4791 _u8 RegAddr[] = {138} ; 4451 u8 RegAddr[] = {138} ;
4792 4452
4793 *count = sizeof(RegAddr) / sizeof(_u8) ; 4453 *count = sizeof(RegAddr) / sizeof(u8) ;
4794 4454
4795 for (i=0; i<*count; i++) 4455 for (i=0; i<*count; i++)
4796 { 4456 {
@@ -4801,7 +4461,7 @@ _u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int
4801 4461
4802} 4462}
4803 4463
4804_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) 4464u16 MXL_GetMasterControl(u8 *MasterReg, int state)
4805{ 4465{
4806 if (state == 1) // Load_Start 4466 if (state == 1) // Load_Start
4807 *MasterReg = 0xF3 ; 4467 *MasterReg = 0xF3 ;
@@ -4816,168 +4476,143 @@ _u16 MXL_GetMasterControl(_u8 *MasterReg, int state)
4816} 4476}
4817 4477
4818#ifdef _MXL_PRODUCTION 4478#ifdef _MXL_PRODUCTION
4819_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) 4479u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range)
4820{
4821 _u16 status = 0 ;
4822
4823 if (VCO_Range == 1) {
4824 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ;
4825 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ;
4826 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ;
4827 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ;
4828 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ;
4829 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ;
4830 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ;
4831 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode
4832 {
4833 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4834 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4835 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ;
4836 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224 ) ;
4837 }
4838 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode
4839 {
4840 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4841 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4842 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ;
4843 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ;
4844 }
4845 if (Tuner->Mode == 1) // Digital Mode
4846 {
4847 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4848 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4849 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ;
4850 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ;
4851 }
4852 }
4853
4854 if (VCO_Range == 2) {
4855 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ;
4856 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ;
4857 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ;
4858 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ;
4859 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ;
4860 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ;
4861 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ;
4862 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4863 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4864 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ;
4865 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode
4866 {
4867 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4868 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4869 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ;
4870 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ;
4871 }
4872 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode
4873 {
4874 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4875 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4876 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ;
4877 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ;
4878 }
4879 if (Tuner->Mode == 1) // Digital Mode
4880 {
4881 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4882 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4883 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41 ) ;
4884 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384 ) ;
4885 }
4886 }
4887
4888 if (VCO_Range == 3) {
4889 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ;
4890 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ;
4891 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ;
4892 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ;
4893 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ;
4894 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ;
4895 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ;
4896 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4897 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4898 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ;
4899 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode
4900 {
4901 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4902 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4903 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ;
4904 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ;
4905 }
4906 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode
4907 {
4908 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4909 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4910 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44 ) ;
4911 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670 ) ;
4912 }
4913 if (Tuner->Mode == 1) // Digital Mode
4914 {
4915 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4916 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4917 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42 ) ;
4918 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760 ) ;
4919 }
4920 }
4921
4922 if (VCO_Range == 4) {
4923 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1) ;
4924 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0 ) ;
4925 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0 ) ;
4926 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1 ) ;
4927 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1 ) ;
4928 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1 ) ;
4929 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0 ) ;
4930 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4931 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4932 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ;
4933 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode
4934 {
4935 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4936 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4937 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ;
4938 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ;
4939 }
4940 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode
4941 {
4942 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4943 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4944 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ;
4945 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438 ) ;
4946 }
4947 if (Tuner->Mode == 1) // Digital Mode
4948 {
4949 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0 ) ;
4950 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40 ) ;
4951 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27 ) ;
4952 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992 ) ;
4953 }
4954 }
4955
4956 return status ;
4957}
4958
4959_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis)
4960{ 4480{
4961 _u16 status = 0 ; 4481 u16 status = 0 ;
4962 4482
4963 if (Hystersis == 1) 4483 if (VCO_Range == 1) {
4964 status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1) ; 4484 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1);
4965 4485 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0);
4966 return status ; 4486 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0);
4967} 4487 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1);
4968#endif 4488 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1);
4969 4489 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1);
4970 4490 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0);
4971 4491 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode {
4972 4492 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1);
4973 4493 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8);
4974 4494 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56);
4495 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 180224);
4496 }
4497 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode {
4498 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4499 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4500 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ;
4501 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 222822 ) ;
4502 }
4503 if (Tuner->Mode == 1) // Digital Mode {
4504 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1 ) ;
4505 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8 ) ;
4506 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 56 ) ;
4507 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 229376 ) ;
4508 }
4509 }
4975 4510
4511 if (VCO_Range == 2) {
4512 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1);
4513 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0);
4514 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0);
4515 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1);
4516 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1);
4517 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1);
4518 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0);
4519 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1);
4520 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4521 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41);
4522 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode {
4523 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1);
4524 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4525 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42);
4526 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438);
4527 }
4528 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode {
4529 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1);
4530 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4531 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42);
4532 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438);
4533 }
4534 if (Tuner->Mode == 1) // Digital Mode {
4535 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 1);
4536 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4537 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 41);
4538 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 16384);
4539 }
4540 }
4976 4541
4542 if (VCO_Range == 3) {
4543 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1);
4544 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0);
4545 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0);
4546 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1);
4547 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1);
4548 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1);
4549 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0);
4550 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4551 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8);
4552 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42);
4553 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode {
4554 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4555 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8);
4556 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44);
4557 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670);
4558 }
4559 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode {
4560 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4561 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8);
4562 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 44);
4563 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 173670);
4564 }
4565 if (Tuner->Mode == 1) // Digital Mode {
4566 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4567 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 8);
4568 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 42);
4569 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 245760);
4570 }
4571 }
4977 4572
4573 if (VCO_Range == 4) {
4574 status += MXL_ControlWrite(Tuner, RFSYN_EN_DIV, 1);
4575 status += MXL_ControlWrite(Tuner, RFSYN_EN_OUTMUX, 0);
4576 status += MXL_ControlWrite(Tuner, RFSYN_SEL_DIVM, 0);
4577 status += MXL_ControlWrite(Tuner, RFSYN_DIVM, 1);
4578 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_OUT, 1);
4579 status += MXL_ControlWrite(Tuner, RFSYN_RF_DIV_BIAS, 1);
4580 status += MXL_ControlWrite(Tuner, DN_SEL_FREQ, 0);
4581 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4582 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4583 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27);
4584 if (Tuner->Mode == 0 && Tuner->IF_Mode == 1) // Analog Low IF Mode {
4585 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4586 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4587 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27);
4588 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438);
4589 }
4590 if (Tuner->Mode == 0 && Tuner->IF_Mode == 0) // Analog Zero IF Mode {
4591 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4592 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4593 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27);
4594 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 206438);
4595 }
4596 if (Tuner->Mode == 1) // Digital Mode {
4597 status += MXL_ControlWrite(Tuner, RFSYN_SEL_VCO_HI, 0);
4598 status += MXL_ControlWrite(Tuner, RFSYN_VCO_BIAS, 40);
4599 status += MXL_ControlWrite(Tuner, CHCAL_INT_MOD_RF, 27);
4600 status += MXL_ControlWrite(Tuner, CHCAL_FRAC_MOD_RF, 212992);
4601 }
4602 }
4978 4603
4604 return status;
4605}
4979 4606
4607u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis)
4608{
4609 u16 status = 0;
4980 4610
4611 if (Hystersis == 1)
4612 status += MXL_ControlWrite(Tuner, DN_BYPASS_AGC_I2C, 1);
4981 4613
4614 return status;
4615}
4982 4616
4617#endif
4983 4618
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 10:25:51 -0500