diff options
author | Doug Anderson <dianders@chromium.org> | 2011-08-30 13:46:10 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2011-09-06 19:13:40 -0400 |
commit | 96219c3a257cc8ba3b3cae67efdc88be37cf7c9d (patch) | |
tree | 9b46e7ee94f9db13a414ec2e445c8a0551aa3982 /drivers | |
parent | 048e29cff95168ea3a9f176e84cc0bae54d0ae64 (diff) |
i2c-tegra: fix possible race condition after tx
In tegra_i2c_fill_tx_fifo, once we have finished pushing all the bytes
to the I2C hardware controller, the interrupt might happen before we
have updated i2c_dev->msg_buf_remaining at the end of the function.
Then, in tegra_i2c_isr, we will call again tegra_i2c_fill_tx_fifo
triggering weird behaviour. This has been shown to happen under real
conditions.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/i2c/busses/i2c-tegra.c | 46 |
1 files changed, 32 insertions, 14 deletions
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 17ded1d2f11d..3c94c4a81a55 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c | |||
@@ -270,14 +270,30 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) | |||
270 | 270 | ||
271 | /* Rounds down to not include partial word at the end of buf */ | 271 | /* Rounds down to not include partial word at the end of buf */ |
272 | words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; | 272 | words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; |
273 | if (words_to_transfer > tx_fifo_avail) | ||
274 | words_to_transfer = tx_fifo_avail; | ||
275 | 273 | ||
276 | i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); | 274 | /* It's very common to have < 4 bytes, so optimize that case. */ |
277 | 275 | if (words_to_transfer) { | |
278 | buf += words_to_transfer * BYTES_PER_FIFO_WORD; | 276 | if (words_to_transfer > tx_fifo_avail) |
279 | buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; | 277 | words_to_transfer = tx_fifo_avail; |
280 | tx_fifo_avail -= words_to_transfer; | 278 | |
279 | /* | ||
280 | * Update state before writing to FIFO. If this casues us | ||
281 | * to finish writing all bytes (AKA buf_remaining goes to 0) we | ||
282 | * have a potential for an interrupt (PACKET_XFER_COMPLETE is | ||
283 | * not maskable). We need to make sure that the isr sees | ||
284 | * buf_remaining as 0 and doesn't call us back re-entrantly. | ||
285 | */ | ||
286 | buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; | ||
287 | tx_fifo_avail -= words_to_transfer; | ||
288 | i2c_dev->msg_buf_remaining = buf_remaining; | ||
289 | i2c_dev->msg_buf = buf + | ||
290 | words_to_transfer * BYTES_PER_FIFO_WORD; | ||
291 | barrier(); | ||
292 | |||
293 | i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); | ||
294 | |||
295 | buf += words_to_transfer * BYTES_PER_FIFO_WORD; | ||
296 | } | ||
281 | 297 | ||
282 | /* | 298 | /* |
283 | * If there is a partial word at the end of buf, handle it manually to | 299 | * If there is a partial word at the end of buf, handle it manually to |
@@ -287,14 +303,15 @@ static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) | |||
287 | if (tx_fifo_avail > 0 && buf_remaining > 0) { | 303 | if (tx_fifo_avail > 0 && buf_remaining > 0) { |
288 | BUG_ON(buf_remaining > 3); | 304 | BUG_ON(buf_remaining > 3); |
289 | memcpy(&val, buf, buf_remaining); | 305 | memcpy(&val, buf, buf_remaining); |
306 | |||
307 | /* Again update before writing to FIFO to make sure isr sees. */ | ||
308 | i2c_dev->msg_buf_remaining = 0; | ||
309 | i2c_dev->msg_buf = NULL; | ||
310 | barrier(); | ||
311 | |||
290 | i2c_writel(i2c_dev, val, I2C_TX_FIFO); | 312 | i2c_writel(i2c_dev, val, I2C_TX_FIFO); |
291 | buf_remaining = 0; | ||
292 | tx_fifo_avail--; | ||
293 | } | 313 | } |
294 | 314 | ||
295 | BUG_ON(tx_fifo_avail > 0 && buf_remaining > 0); | ||
296 | i2c_dev->msg_buf_remaining = buf_remaining; | ||
297 | i2c_dev->msg_buf = buf; | ||
298 | return 0; | 315 | return 0; |
299 | } | 316 | } |
300 | 317 | ||
@@ -411,9 +428,10 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) | |||
411 | tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); | 428 | tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ); |
412 | } | 429 | } |
413 | 430 | ||
414 | if ((status & I2C_INT_PACKET_XFER_COMPLETE) && | 431 | if (status & I2C_INT_PACKET_XFER_COMPLETE) { |
415 | !i2c_dev->msg_buf_remaining) | 432 | BUG_ON(i2c_dev->msg_buf_remaining); |
416 | complete(&i2c_dev->msg_complete); | 433 | complete(&i2c_dev->msg_complete); |
434 | } | ||
417 | 435 | ||
418 | i2c_writel(i2c_dev, status, I2C_INT_STATUS); | 436 | i2c_writel(i2c_dev, status, I2C_INT_STATUS); |
419 | if (i2c_dev->is_dvc) | 437 | if (i2c_dev->is_dvc) |