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authorDave Liu <daveliu@freescale.com>2010-01-06 23:32:38 -0500
committerDavid S. Miller <davem@davemloft.net>2010-01-06 23:32:38 -0500
commit58933c643f86651decc4818cf680f9ec3b0460d2 (patch)
treef243887c20ae3f77c14dde00b923cda147ce4f9b /drivers
parentd3af9dd04f8795dc2761ecfa56632e4d0df0dae2 (diff)
ucc_geth: Fix the wrong the Rx/Tx FIFO size
current the Rx/Tx FIFO size settings cause problem when four UEC ethernets work simultaneously. eg: GETH1, UEM-J15, GETH2, UEC-J5 on 8569MDS board $ ifconfig eth0 10.193.20.166 $ ifconfig eth1 10.193.20.167 $ ifconfig eth2 10.193.20.168 then $ ifconfig eth3 10.193.20.169 The fourth ethernet will cause all of interface broken, you cann't ping successfully any more. The patch fix this issue for MPC8569 Rev1.0 and Rev2.0 Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/ucc_geth.h13
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h
index a007e2acf651..ef1fbeb11c6e 100644
--- a/drivers/net/ucc_geth.h
+++ b/drivers/net/ucc_geth.h
@@ -838,13 +838,13 @@ struct ucc_geth_hardware_statistics {
838 using the maximum is 838 using the maximum is
839 easier */ 839 easier */
840#define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 840#define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
841#define UCC_GETH_SCHEDULER_ALIGNMENT 4 /* This is a guess */ 841#define UCC_GETH_SCHEDULER_ALIGNMENT 8 /* This is a guess */
842#define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */ 842#define UCC_GETH_TX_STATISTICS_ALIGNMENT 4 /* This is a guess */
843#define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */ 843#define UCC_GETH_RX_STATISTICS_ALIGNMENT 4 /* This is a guess */
844#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64 844#define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT 64
845#define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */ 845#define UCC_GETH_RX_BD_QUEUES_ALIGNMENT 8 /* This is a guess */
846#define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */ 846#define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT 128 /* This is a guess */
847#define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 /* This 847#define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 8 /* This
848 is a 848 is a
849 guess 849 guess
850 */ 850 */
@@ -899,16 +899,17 @@ struct ucc_geth_hardware_statistics {
899#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size 899#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size
900 */ 900 */
901#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */ 901#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */
902#define UCC_GETH_UTFTT_INIT 128 902#define UCC_GETH_UTFTT_INIT 512
903/* Gigabit Ethernet (1000 Mbps) */ 903/* Gigabit Ethernet (1000 Mbps) */
904#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual 904#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual
905 FIFO size */ 905 FIFO size */
906#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */ 906#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */
907#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */ 907#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */
908#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual 908#define UCC_GETH_UTFS_GIGA_INIT 4096/*2048*/ /* Tx virtual
909 FIFO size */
910#define UCC_GETH_UTFET_GIGA_INIT 2048/*1024*/ /* 1/2 utfs */
911#define UCC_GETH_UTFTT_GIGA_INIT 4096/*0x40*/ /* Tx virtual
909 FIFO size */ 912 FIFO size */
910#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */
911#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */
912 913
913#define UCC_GETH_REMODER_INIT 0 /* bits that must be 914#define UCC_GETH_REMODER_INIT 0 /* bits that must be
914 set */ 915 set */