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authorSteven Toth <stoth@hauppauge.com>2008-05-01 04:01:31 -0400
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-05-14 01:56:37 -0400
commit2637d5b498b979b46a01690d22ecca1e5b79b903 (patch)
tree9a9a743b1949e4d86b8364d96dda3468e40b3091 /drivers
parent52c99bda04d8bb1fb390821695b0f9efc1e1db44 (diff)
V4L/DVB (7864): mxl5005s: Cleanup #1
Cleanup #1 Signed-off-by: Steven Toth <stoth@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/media/common/tuners/mxl5005s.c8
-rw-r--r--drivers/media/common/tuners/mxl5005s.h773
2 files changed, 260 insertions, 521 deletions
diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c
index a32475fa1472..3c4330614faf 100644
--- a/drivers/media/common/tuners/mxl5005s.c
+++ b/drivers/media/common/tuners/mxl5005s.c
@@ -35,13 +35,7 @@ MxL5005S module is derived from tuner module.
35*/ 35*/
36 36
37 37
38#include "tuner_mxl5005s.h" 38#include "mxl5005s.h"
39#include "tuner_demod_io.h"
40
41
42
43
44
45 39
46/** 40/**
47 41
diff --git a/drivers/media/common/tuners/mxl5005s.h b/drivers/media/common/tuners/mxl5005s.h
index 8542fc10a9bb..1944d9e94427 100644
--- a/drivers/media/common/tuners/mxl5005s.h
+++ b/drivers/media/common/tuners/mxl5005s.h
@@ -23,138 +23,104 @@
23 */ 23 */
24 24
25 25
26#ifndef __TUNER_MXL5005S_H 26#ifndef __MXL5005S_H
27#define __TUNER_MXL5005S_H 27#define __MXL5005S_H
28 28
29/*
30 * The following context is source code provided by MaxLinear.
31 * MaxLinear source code - Common.h
32 */
29 33
30 34typedef void *HANDLE; /* Pointer to memory location */
31// The following context is source code provided by MaxLinear.
32
33
34// MaxLinear source code - Common.h
35
36
37
38//#pragma once
39
40typedef unsigned char _u8; // At least 1 Byte
41typedef unsigned short _u16; // At least 2 Bytes
42typedef signed short _s16;
43typedef unsigned long _u32; // At least 4 Bytes
44typedef void * HANDLE; // Pointer to memory location
45 35
46#define TUNER_REGS_NUM 104 36#define TUNER_REGS_NUM 104
47#define INITCTRL_NUM 40 37#define INITCTRL_NUM 40
38
48#ifdef _MXL_PRODUCTION 39#ifdef _MXL_PRODUCTION
49#define CHCTRL_NUM 39 40#define CHCTRL_NUM 39
50#else 41#else
51#define CHCTRL_NUM 36 42#define CHCTRL_NUM 36
52#endif 43#endif
53 44
54#define MXLCTRL_NUM 189 45#define MXLCTRL_NUM 189
55 46#define MASTER_CONTROL_ADDR 9
56#define MASTER_CONTROL_ADDR 9
57
58 47
59 48/* Enumeration of AGC Mode */
60
61// Enumeration of AGC Mode
62typedef enum 49typedef enum
63{ 50{
64 MXL_DUAL_AGC = 0 , 51 MXL_DUAL_AGC = 0,
65 MXL_SINGLE_AGC 52 MXL_SINGLE_AGC
66} AGC_Mode ; 53} AGC_Mode;
67 54
68// 55/* Enumeration of Master Control Register State */
69// Enumeration of Master Control Register State
70//
71typedef enum 56typedef enum
72{ 57{
73 MC_LOAD_START = 1 , 58 MC_LOAD_START = 1,
74 MC_POWER_DOWN , 59 MC_POWER_DOWN,
75 MC_SYNTH_RESET , 60 MC_SYNTH_RESET,
76 MC_SEQ_OFF 61 MC_SEQ_OFF
77} Master_Control_State ; 62} Master_Control_State;
78 63
79// 64/* Enumeration of MXL5005 Tuner Mode */
80// Enumeration of MXL5005 Tuner Mode
81//
82typedef enum 65typedef enum
83{ 66{
84 MXL_ANALOG_MODE = 0 , 67 MXL_ANALOG_MODE = 0,
85 MXL_DIGITAL_MODE 68 MXL_DIGITAL_MODE
69} Tuner_Mode;
86 70
87} Tuner_Mode ; 71/* Enumeration of MXL5005 Tuner IF Mode */
88
89//
90// Enumeration of MXL5005 Tuner IF Mode
91//
92typedef enum 72typedef enum
93{ 73{
94 MXL_ZERO_IF = 0 , 74 MXL_ZERO_IF = 0,
95 MXL_LOW_IF 75 MXL_LOW_IF
76} Tuner_IF_Mode;
96 77
97} Tuner_IF_Mode ; 78/* Enumeration of MXL5005 Tuner Clock Out Mode */
98
99//
100// Enumeration of MXL5005 Tuner Clock Out Mode
101//
102typedef enum 79typedef enum
103{ 80{
104 MXL_CLOCK_OUT_DISABLE = 0 , 81 MXL_CLOCK_OUT_DISABLE = 0,
105 MXL_CLOCK_OUT_ENABLE 82 MXL_CLOCK_OUT_ENABLE
106} Tuner_Clock_Out ; 83} Tuner_Clock_Out;
107 84
108// 85/* Enumeration of MXL5005 Tuner Div Out Mode */
109// Enumeration of MXL5005 Tuner Div Out Mode
110//
111typedef enum 86typedef enum
112{ 87{
113 MXL_DIV_OUT_1 = 0 , 88 MXL_DIV_OUT_1 = 0,
114 MXL_DIV_OUT_4 89 MXL_DIV_OUT_4
115 90
116} Tuner_Div_Out ; 91} Tuner_Div_Out;
117 92
118// 93/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */
119// Enumeration of MXL5005 Tuner Pull-up Cap Select Mode
120//
121typedef enum 94typedef enum
122{ 95{
123 MXL_CAP_SEL_DISABLE = 0 , 96 MXL_CAP_SEL_DISABLE = 0,
124 MXL_CAP_SEL_ENABLE 97 MXL_CAP_SEL_ENABLE
125 98
126} Tuner_Cap_Select ; 99} Tuner_Cap_Select;
127 100
128// 101/* Enumeration of MXL5005 Tuner RSSI Mode */
129// Enumeration of MXL5005 Tuner RSSI Mode
130//
131typedef enum 102typedef enum
132{ 103{
133 MXL_RSSI_DISABLE = 0 , 104 MXL_RSSI_DISABLE = 0,
134 MXL_RSSI_ENABLE 105 MXL_RSSI_ENABLE
135 106
136} Tuner_RSSI ; 107} Tuner_RSSI;
137 108
138// 109/* Enumeration of MXL5005 Tuner Modulation Type */
139// Enumeration of MXL5005 Tuner Modulation Type
140//
141typedef enum 110typedef enum
142{ 111{
143 MXL_DEFAULT_MODULATION = 0 , 112 MXL_DEFAULT_MODULATION = 0,
144 MXL_DVBT, 113 MXL_DVBT,
145 MXL_ATSC, 114 MXL_ATSC,
146 MXL_QAM, 115 MXL_QAM,
147 MXL_ANALOG_CABLE, 116 MXL_ANALOG_CABLE,
148 MXL_ANALOG_OTA 117 MXL_ANALOG_OTA
118} Tuner_Modu_Type;
149 119
150} Tuner_Modu_Type ; 120/* Enumeration of MXL5005 Tuner Tracking Filter Type */
151
152//
153// Enumeration of MXL5005 Tuner Tracking Filter Type
154//
155typedef enum 121typedef enum
156{ 122{
157 MXL_TF_DEFAULT = 0 , 123 MXL_TF_DEFAULT = 0,
158 MXL_TF_OFF, 124 MXL_TF_OFF,
159 MXL_TF_C, 125 MXL_TF_C,
160 MXL_TF_C_H, 126 MXL_TF_C_H,
@@ -165,316 +131,233 @@ typedef enum
165 MXL_TF_E_2, 131 MXL_TF_E_2,
166 MXL_TF_E_NA, 132 MXL_TF_E_NA,
167 MXL_TF_G 133 MXL_TF_G
134} Tuner_TF_Type;
168 135
169 136/* MXL5005 Tuner Register Struct */
170} Tuner_TF_Type ;
171
172
173//
174// MXL5005 Tuner Register Struct
175//
176typedef struct _TunerReg_struct 137typedef struct _TunerReg_struct
177{ 138{
178 _u16 Reg_Num ; // Tuner Register Address 139 u16 Reg_Num; /* Tuner Register Address */
179 _u16 Reg_Val ; // Current sofware programmed value waiting to be writen 140 u16 Reg_Val; /* Current sofware programmed value waiting to be writen */
180} TunerReg_struct ; 141} TunerReg_struct;
181 142
182// 143/* MXL5005 Tuner Control Struct */
183// MXL5005 Tuner Control Struct
184//
185typedef struct _TunerControl_struct { 144typedef struct _TunerControl_struct {
186 _u16 Ctrl_Num ; // Control Number 145 u16 Ctrl_Num; /* Control Number */
187 _u16 size ; // Number of bits to represent Value 146 u16 size; /* Number of bits to represent Value */
188 _u16 addr[25] ; // Array of Tuner Register Address for each bit position 147 u16 addr[25]; /* Array of Tuner Register Address for each bit position */
189 _u16 bit[25] ; // Array of bit position in Register Address for each bit position 148 u16 bit[25]; /* Array of bit position in Register Address for each bit position */
190 _u16 val[25] ; // Binary representation of Value 149 u16 val[25]; /* Binary representation of Value */
191} TunerControl_struct ; 150} TunerControl_struct;
192 151
193// 152/* MXL5005 Tuner Struct */
194// MXL5005 Tuner Struct
195//
196typedef struct _Tuner_struct 153typedef struct _Tuner_struct
197{ 154{
198 _u8 Mode ; // 0: Analog Mode ; 1: Digital Mode 155 u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */
199 _u8 IF_Mode ; // for Analog Mode, 0: zero IF; 1: low IF 156 u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */
200 _u32 Chan_Bandwidth ; // filter channel bandwidth (6, 7, 8) 157 u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */
201 _u32 IF_OUT ; // Desired IF Out Frequency 158 u32 IF_OUT; /* Desired IF Out Frequency */
202 _u16 IF_OUT_LOAD ; // IF Out Load Resistor (200/300 Ohms) 159 u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */
203 _u32 RF_IN ; // RF Input Frequency 160 u32 RF_IN; /* RF Input Frequency */
204 _u32 Fxtal ; // XTAL Frequency 161 u32 Fxtal; /* XTAL Frequency */
205 _u8 AGC_Mode ; // AGC Mode 0: Dual AGC; 1: Single AGC 162 u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */
206 _u16 TOP ; // Value: take over point 163 u16 TOP; /* Value: take over point */
207 _u8 CLOCK_OUT ; // 0: turn off clock out; 1: turn on clock out 164 u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */
208 _u8 DIV_OUT ; // 4MHz or 16MHz 165 u8 DIV_OUT; /* 4MHz or 16MHz */
209 _u8 CAPSELECT ; // 0: disable On-Chip pulling cap; 1: enable 166 u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */
210 _u8 EN_RSSI ; // 0: disable RSSI; 1: enable RSSI 167 u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */
211 _u8 Mod_Type ; // Modulation Type; 168 u8 Mod_Type; /* Modulation Type; */
212 // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable 169 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
213 _u8 TF_Type ; // Tracking Filter Type 170 u8 TF_Type; /* Tracking Filter Type */
214 // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H 171 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
215 172
216 // Calculated Settings 173 /* Calculated Settings */
217 _u32 RF_LO ; // Synth RF LO Frequency 174 u32 RF_LO; /* Synth RF LO Frequency */
218 _u32 IF_LO ; // Synth IF LO Frequency 175 u32 IF_LO; /* Synth IF LO Frequency */
219 _u32 TG_LO ; // Synth TG_LO Frequency 176 u32 TG_LO; /* Synth TG_LO Frequency */
220 177
221 // Pointers to ControlName Arrays 178 /* Pointers to ControlName Arrays */
222 _u16 Init_Ctrl_Num ; // Number of INIT Control Names 179 u16 Init_Ctrl_Num; /* Number of INIT Control Names */
223 TunerControl_struct Init_Ctrl[INITCTRL_NUM] ; // INIT Control Names Array Pointer 180 TunerControl_struct
224 _u16 CH_Ctrl_Num ; // Number of CH Control Names 181 Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
225 TunerControl_struct CH_Ctrl[CHCTRL_NUM] ; // CH Control Name Array Pointer 182
226 _u16 MXL_Ctrl_Num ; // Number of MXL Control Names 183 u16 CH_Ctrl_Num; /* Number of CH Control Names */
227 TunerControl_struct MXL_Ctrl[MXLCTRL_NUM] ; // MXL Control Name Array Pointer 184 TunerControl_struct
228 185 CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */
229 // Pointer to Tuner Register Array 186
230 _u16 TunerRegs_Num ; // Number of Tuner Registers 187 u16 MXL_Ctrl_Num; /* Number of MXL Control Names */
231 TunerReg_struct TunerRegs[TUNER_REGS_NUM] ; // Tuner Register Array Pointer 188 TunerControl_struct
232} Tuner_struct ; 189 MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */
233 190
234 191 /* Pointer to Tuner Register Array */
192 u16 TunerRegs_Num; /* Number of Tuner Registers */
193 TunerReg_struct
194 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
195
196} Tuner_struct;
235 197
236typedef enum 198typedef enum
237{ 199{
238 // 200 /* Initialization Control Names */
239 // Initialization Control Names 201 DN_IQTN_AMP_CUT = 1, /* 1 */
240 // 202 BB_MODE, /* 2 */
241 DN_IQTN_AMP_CUT = 1 , // 1 203 BB_BUF, /* 3 */
242 BB_MODE , // 2 204 BB_BUF_OA, /* 4 */
243 BB_BUF , // 3 205 BB_ALPF_BANDSELECT, /* 5 */
244 BB_BUF_OA , // 4 206 BB_IQSWAP, /* 6 */
245 BB_ALPF_BANDSELECT , // 5 207 BB_DLPF_BANDSEL, /* 7 */
246 BB_IQSWAP , // 6 208 RFSYN_CHP_GAIN, /* 8 */
247 BB_DLPF_BANDSEL , // 7 209 RFSYN_EN_CHP_HIGAIN, /* 9 */
248 RFSYN_CHP_GAIN , // 8 210 AGC_IF, /* 10 */
249 RFSYN_EN_CHP_HIGAIN , // 9 211 AGC_RF, /* 11 */
250 AGC_IF , // 10 212 IF_DIVVAL, /* 12 */
251 AGC_RF , // 11 213 IF_VCO_BIAS, /* 13 */
252 IF_DIVVAL , // 12 214 CHCAL_INT_MOD_IF, /* 14 */
253 IF_VCO_BIAS , // 13 215 CHCAL_FRAC_MOD_IF, /* 15 */
254 CHCAL_INT_MOD_IF , // 14 216 DRV_RES_SEL, /* 16 */
255 CHCAL_FRAC_MOD_IF , // 15 217 I_DRIVER, /* 17 */
256 DRV_RES_SEL , // 16 218 EN_AAF, /* 18 */
257 I_DRIVER , // 17 219 EN_3P, /* 19 */
258 EN_AAF , // 18 220 EN_AUX_3P, /* 20 */
259 EN_3P , // 19 221 SEL_AAF_BAND, /* 21 */
260 EN_AUX_3P , // 20 222 SEQ_ENCLK16_CLK_OUT, /* 22 */
261 SEL_AAF_BAND , // 21 223 SEQ_SEL4_16B, /* 23 */
262 SEQ_ENCLK16_CLK_OUT , // 22 224 XTAL_CAPSELECT, /* 24 */
263 SEQ_SEL4_16B , // 23 225 IF_SEL_DBL, /* 25 */
264 XTAL_CAPSELECT , // 24 226 RFSYN_R_DIV, /* 26 */
265 IF_SEL_DBL , // 25 227 SEQ_EXTSYNTHCALIF, /* 27 */
266 RFSYN_R_DIV , // 26 228 SEQ_EXTDCCAL, /* 28 */
267 SEQ_EXTSYNTHCALIF , // 27 229 AGC_EN_RSSI, /* 29 */
268 SEQ_EXTDCCAL , // 28 230 RFA_ENCLKRFAGC, /* 30 */
269 AGC_EN_RSSI , // 29 231 RFA_RSSI_REFH, /* 31 */
270 RFA_ENCLKRFAGC , // 30 232 RFA_RSSI_REF, /* 32 */
271 RFA_RSSI_REFH , // 31 233 RFA_RSSI_REFL, /* 33 */
272 RFA_RSSI_REF , // 32 234 RFA_FLR, /* 34 */
273 RFA_RSSI_REFL , // 33 235 RFA_CEIL, /* 35 */
274 RFA_FLR , // 34 236 SEQ_EXTIQFSMPULSE, /* 36 */
275 RFA_CEIL , // 35 237 OVERRIDE_1, /* 37 */
276 SEQ_EXTIQFSMPULSE , // 36 238 BB_INITSTATE_DLPF_TUNE, /* 38 */
277 OVERRIDE_1 , // 37 239 TG_R_DIV, /* 39 */
278 BB_INITSTATE_DLPF_TUNE, // 38 240 EN_CHP_LIN_B, /* 40 */
279 TG_R_DIV, // 39 241
280 EN_CHP_LIN_B , // 40 242 /* Channel Change Control Names */
281 243 DN_POLY = 51, /* 51 */
282 // 244 DN_RFGAIN, /* 52 */
283 // Channel Change Control Names 245 DN_CAP_RFLPF, /* 53 */
284 // 246 DN_EN_VHFUHFBAR, /* 54 */
285 DN_POLY = 51 , // 51 247 DN_GAIN_ADJUST, /* 55 */
286 DN_RFGAIN , // 52 248 DN_IQTNBUF_AMP, /* 56 */
287 DN_CAP_RFLPF , // 53 249 DN_IQTNGNBFBIAS_BST, /* 57 */
288 DN_EN_VHFUHFBAR , // 54 250 RFSYN_EN_OUTMUX, /* 58 */
289 DN_GAIN_ADJUST , // 55 251 RFSYN_SEL_VCO_OUT, /* 59 */
290 DN_IQTNBUF_AMP , // 56 252 RFSYN_SEL_VCO_HI, /* 60 */
291 DN_IQTNGNBFBIAS_BST , // 57 253 RFSYN_SEL_DIVM, /* 61 */
292 RFSYN_EN_OUTMUX , // 58 254 RFSYN_RF_DIV_BIAS, /* 62 */
293 RFSYN_SEL_VCO_OUT , // 59 255 DN_SEL_FREQ, /* 63 */
294 RFSYN_SEL_VCO_HI , // 60 256 RFSYN_VCO_BIAS, /* 64 */
295 RFSYN_SEL_DIVM , // 61 257 CHCAL_INT_MOD_RF, /* 65 */
296 RFSYN_RF_DIV_BIAS , // 62 258 CHCAL_FRAC_MOD_RF, /* 66 */
297 DN_SEL_FREQ , // 63 259 RFSYN_LPF_R, /* 67 */
298 RFSYN_VCO_BIAS , // 64 260 CHCAL_EN_INT_RF, /* 68 */
299 CHCAL_INT_MOD_RF , // 65 261 TG_LO_DIVVAL, /* 69 */
300 CHCAL_FRAC_MOD_RF , // 66 262 TG_LO_SELVAL, /* 70 */
301 RFSYN_LPF_R , // 67 263 TG_DIV_VAL, /* 71 */
302 CHCAL_EN_INT_RF , // 68 264 TG_VCO_BIAS, /* 72 */
303 TG_LO_DIVVAL , // 69 265 SEQ_EXTPOWERUP, /* 73 */
304 TG_LO_SELVAL , // 70 266 OVERRIDE_2, /* 74 */
305 TG_DIV_VAL , // 71 267 OVERRIDE_3, /* 75 */
306 TG_VCO_BIAS , // 72 268 OVERRIDE_4, /* 76 */
307 SEQ_EXTPOWERUP , // 73 269 SEQ_FSM_PULSE, /* 77 */
308 OVERRIDE_2 , // 74 270 GPIO_4B, /* 78 */
309 OVERRIDE_3 , // 75 271 GPIO_3B, /* 79 */
310 OVERRIDE_4 , // 76 272 GPIO_4, /* 80 */
311 SEQ_FSM_PULSE , // 77 273 GPIO_3, /* 81 */
312 GPIO_4B, // 78 274 GPIO_1B, /* 82 */
313 GPIO_3B, // 79 275 DAC_A_ENABLE, /* 83 */
314 GPIO_4, // 80 276 DAC_B_ENABLE, /* 84 */
315 GPIO_3, // 81 277 DAC_DIN_A, /* 85 */
316 GPIO_1B, // 82 278 DAC_DIN_B, /* 86 */
317 DAC_A_ENABLE , // 83
318 DAC_B_ENABLE , // 84
319 DAC_DIN_A , // 85
320 DAC_DIN_B , // 86
321#ifdef _MXL_PRODUCTION 279#ifdef _MXL_PRODUCTION
322 RFSYN_EN_DIV, // 87 280 RFSYN_EN_DIV, /* 87 */
323 RFSYN_DIVM, // 88 281 RFSYN_DIVM, /* 88 */
324 DN_BYPASS_AGC_I2C // 89 282 DN_BYPASS_AGC_I2C /* 89 */
325#endif 283#endif
284} MXL5005_ControlName;
326 285
327} MXL5005_ControlName ; 286/* End of common.h */
328
329
330 287
288/*
289 * The following context is source code provided by MaxLinear.
290 * MaxLinear source code - Common_MXL.h (?)
291 */
331 292
332 293void InitTunerControls(Tuner_struct *Tuner);
333 294u16 MXL_BlockInit(Tuner_struct *Tuner);
334 295u16 MXL5005_RegisterInit(Tuner_struct *Tuner);
335 296u16 MXL5005_ControlInit(Tuner_struct *Tuner);
336
337
338
339
340
341
342
343// MaxLinear source code - MXL5005_c.h
344
345
346
347// MXL5005.h : main header file for the MXL5005 DLL
348//
349//#pragma once
350
351//#include "Common.h"
352#ifdef _MXL_INTERNAL 297#ifdef _MXL_INTERNAL
353#include "Common_MXL.h" 298u16 MXL5005_MXLControlInit(Tuner_struct *Tuner);
354#endif 299#endif
355 300
356void InitTunerControls( Tuner_struct *Tuner) ; 301u16 MXL5005_TunerConfig(Tuner_struct *Tuner,
357 302 u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */
358_u16 MXL_BlockInit( Tuner_struct *Tuner ) ; 303 u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */
359 304 u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */
360_u16 MXL5005_RegisterInit (Tuner_struct * Tuner) ; 305 u32 IF_out, /* Desired IF Out Frequency */
361_u16 MXL5005_ControlInit (Tuner_struct *Tuner) ; 306 u32 Fxtal, /* XTAL Frequency */
362 307 u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
363#ifdef _MXL_INTERNAL 308 u16 TOP, /* 0: Dual AGC; Value: take over point */
364 _u16 MXL5005_MXLControlInit(Tuner_struct *Tuner) ; 309 u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */
365#endif 310 u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */
311 u8 DIV_OUT, /* 4MHz or 16MHz */
312 u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */
313 u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */
314 u8 Mod_Type, /* Modulation Type; */
315 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
316 u8 TF_Type /* Tracking Filter Type */
317 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
318 );
366 319
367_u16 MXL5005_TunerConfig(Tuner_struct *Tuner, 320void MXL_SynthIFLO_Calc(Tuner_struct *Tuner);
368 _u8 Mode, // 0: Analog Mode ; 1: Digital Mode 321void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner);
369 _u8 IF_mode, // for Analog Mode, 0: zero IF; 1: low IF 322u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal);
370 _u32 Bandwidth, // filter channel bandwidth (6, 7, 8) 323u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal);
371 _u32 IF_out, // Desired IF Out Frequency 324u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value);
372 _u32 Fxtal, // XTAL Frequency 325u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 ControlNum, u32 value, u16 controlGroup);
373 _u8 AGC_Mode, // AGC Mode - Dual AGC: 0, Single AGC: 1 326u16 MXL_ControlRead(Tuner_struct *Tuner, u16 ControlNum, u32 * value);
374 _u16 TOP, // 0: Dual AGC; Value: take over point 327u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 ControlNum, u8 *RegNum, int *count);
375 _u16 IF_OUT_LOAD,// IF Out Load Resistor (200 / 300 Ohms) 328void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal);
376 _u8 CLOCK_OUT, // 0: turn off clock out; 1: turn on clock out 329u16 MXL_IFSynthInit(Tuner_struct * Tuner );
377 _u8 DIV_OUT, // 4MHz or 16MHz 330u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq);
378 _u8 CAPSELECT, // 0: disable On-Chip pulling cap; 1: enable 331u16 MXL_OverwriteICDefault(Tuner_struct *Tuner);
379 _u8 EN_RSSI, // 0: disable RSSI; 1: enable RSSI 332u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val);
380 _u8 Mod_Type, // Modulation Type; 333u32 MXL_Ceiling(u32 value, u32 resolution);
381 // 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable 334u32 MXL_GetXtalInt(u32 Xtal_Freq);
382 _u8 TF_Type // Tracking Filter Type 335
383 // 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H 336u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count);
384 ) ; 337u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count);
385 338u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count);
386void MXL_SynthIFLO_Calc(Tuner_struct *Tuner) ; 339u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count);
387void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner) ; 340u16 MXL_GetMasterControl(u8 *MasterReg, int state);
388_u16 MXL_RegWrite(Tuner_struct *Tuner, _u8 RegNum, _u8 RegVal) ;
389_u16 MXL_RegRead(Tuner_struct *Tuner, _u8 RegNum, _u8 *RegVal) ;
390_u16 MXL_ControlWrite(Tuner_struct *Tuner, _u16 ControlNum, _u32 value) ;
391_u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, _u16 ControlNum, _u32 value, _u16 controlGroup) ;
392_u16 MXL_ControlRead(Tuner_struct *Tuner, _u16 ControlNum, _u32 * value) ;
393_u16 MXL_ControlRegRead(Tuner_struct *Tuner, _u16 ControlNum, _u8 *RegNum, int * count) ;
394void MXL_RegWriteBit(Tuner_struct *Tuner, _u8 address, _u8 bit, _u8 bitVal);
395_u16 MXL_IFSynthInit( Tuner_struct * Tuner ) ;
396_u16 MXL_TuneRF(Tuner_struct *Tuner, _u32 RF_Freq) ;
397_u16 MXL_OverwriteICDefault( Tuner_struct *Tuner) ;
398_u16 MXL_SetGPIO(Tuner_struct *Tuner, _u8 GPIO_Num, _u8 GPIO_Val) ;
399_u32 MXL_Ceiling( _u32 value, _u32 resolution ) ;
400_u32 MXL_GetXtalInt(_u32 Xtal_Freq) ;
401
402_u16 MXL_GetInitRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ;
403_u16 MXL_GetCHRegister(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ;
404_u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ;
405_u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, _u8 * RegNum, _u8 *RegVal, int *count) ;
406_u16 MXL_GetMasterControl(_u8 *MasterReg, int state) ;
407 341
408#ifdef _MXL_PRODUCTION 342#ifdef _MXL_PRODUCTION
409_u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range) ; 343u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range);
410_u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis) ; 344u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis);
411#endif 345#endif
412 346
347/* Constants */
348#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
349#define MXL5005S_LATCH_BYTE 0xfe
413 350
414 351/* Register address, MSB, and LSB */
415 352#define MXL5005S_BB_IQSWAP_ADDR 59
416 353#define MXL5005S_BB_IQSWAP_MSB 0
417 354#define MXL5005S_BB_IQSWAP_LSB 0
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435// The following context is MxL5005S tuner API source code
436
437
438
439
440
441/**
442
443@file
444
445@brief MxL5005S tuner module declaration
446
447One can manipulate MxL5005S tuner through MxL5005S module.
448MxL5005S module is derived from tuner module.
449
450*/
451
452
453
454#include "tuner_base.h"
455
456
457
458
459
460// Definitions
461
462// Constants
463#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
464#define MXL5005S_LATCH_BYTE 0xfe
465
466// Register address, MSB, and LSB
467#define MXL5005S_BB_IQSWAP_ADDR 59
468#define MXL5005S_BB_IQSWAP_MSB 0
469#define MXL5005S_BB_IQSWAP_LSB 0
470 355
471#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53 356#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
472#define MXL5005S_BB_DLPF_BANDSEL_MSB 4 357#define MXL5005S_BB_DLPF_BANDSEL_MSB 4
473#define MXL5005S_BB_DLPF_BANDSEL_LSB 3 358#define MXL5005S_BB_DLPF_BANDSEL_LSB 3
474 359
475 360/* Standard modes */
476
477// Standard modes
478enum 361enum
479{ 362{
480 MXL5005S_STANDARD_DVBT, 363 MXL5005S_STANDARD_DVBT,
@@ -482,8 +365,7 @@ enum
482}; 365};
483#define MXL5005S_STANDARD_MODE_NUM 2 366#define MXL5005S_STANDARD_MODE_NUM 2
484 367
485 368/* Bandwidth modes */
486// Bandwidth modes
487enum 369enum
488{ 370{
489 MXL5005S_BANDWIDTH_6MHZ = 6000000, 371 MXL5005S_BANDWIDTH_6MHZ = 6000000,
@@ -492,8 +374,7 @@ enum
492}; 374};
493#define MXL5005S_BANDWIDTH_MODE_NUM 3 375#define MXL5005S_BANDWIDTH_MODE_NUM 3
494 376
495 377/* Top modes */
496// Top modes
497enum 378enum
498{ 379{
499 MXL5005S_TOP_5P5 = 55, 380 MXL5005S_TOP_5P5 = 55,
@@ -513,29 +394,20 @@ enum
513 MXL5005S_TOP_34P9 = 349, 394 MXL5005S_TOP_34P9 = 349,
514}; 395};
515 396
516 397/* IF output load */
517// IF output load
518enum 398enum
519{ 399{
520 MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200, 400 MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200,
521 MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300, 401 MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300,
522}; 402};
523 403
524 404/* MxL5005S extra module alias */
525
526
527
528/// MxL5005S extra module alias
529typedef struct MXL5005S_EXTRA_MODULE_TAG MXL5005S_EXTRA_MODULE; 405typedef struct MXL5005S_EXTRA_MODULE_TAG MXL5005S_EXTRA_MODULE;
530 406
531 407/* MxL5005S register setting function pointer */
532
533
534
535// MxL5005S register setting function pointer
536typedef int 408typedef int
537(*MXL5005S_FP_SET_REGS_WITH_TABLE)( 409(*MXL5005S_FP_SET_REGS_WITH_TABLE)(
538 struct dvb_usb_device* dib, 410 struct dvb_usb_device* dib,
539 TUNER_MODULE *pTuner, 411 TUNER_MODULE *pTuner,
540 unsigned char *pAddrTable, 412 unsigned char *pAddrTable,
541 unsigned char *pByteTable, 413 unsigned char *pByteTable,
@@ -543,10 +415,10 @@ typedef int
543 ); 415 );
544 416
545 417
546// MxL5005S register mask bits setting function pointer 418/* MxL5005S register mask bits setting function pointer */
547typedef int 419typedef int
548(*MXL5005S_FP_SET_REG_MASK_BITS)( 420(*MXL5005S_FP_SET_REG_MASK_BITS)(
549 struct dvb_usb_device* dib, 421 struct dvb_usb_device* dib,
550 TUNER_MODULE *pTuner, 422 TUNER_MODULE *pTuner,
551 unsigned char RegAddr, 423 unsigned char RegAddr,
552 unsigned char Msb, 424 unsigned char Msb,
@@ -554,17 +426,15 @@ typedef int
554 const unsigned char WritingValue 426 const unsigned char WritingValue
555 ); 427 );
556 428
557 429/* MxL5005S spectrum mode setting function pointer */
558// MxL5005S spectrum mode setting function pointer
559typedef int 430typedef int
560(*MXL5005S_FP_SET_SPECTRUM_MODE)( 431(*MXL5005S_FP_SET_SPECTRUM_MODE)(
561 struct dvb_usb_device* dib, 432 struct dvb_usb_device* dib,
562 TUNER_MODULE *pTuner, 433 TUNER_MODULE *pTuner,
563 int SpectrumMode 434 int SpectrumMode
564 ); 435 );
565 436
566 437/* MxL5005S bandwidth setting function pointer */
567// MxL5005S bandwidth setting function pointer
568typedef int 438typedef int
569(*MXL5005S_FP_SET_BANDWIDTH_HZ)( 439(*MXL5005S_FP_SET_BANDWIDTH_HZ)(
570 struct dvb_usb_device* dib, 440 struct dvb_usb_device* dib,
@@ -572,147 +442,22 @@ typedef int
572 unsigned long BandwidthHz 442 unsigned long BandwidthHz
573 ); 443 );
574 444
575 445/* MxL5005S extra module */
576
577
578
579// MxL5005S extra module
580struct MXL5005S_EXTRA_MODULE_TAG 446struct MXL5005S_EXTRA_MODULE_TAG
581{ 447{
582 // MxL5005S function pointers 448 /* MxL5005S function pointers */
583 MXL5005S_FP_SET_REGS_WITH_TABLE SetRegsWithTable; 449 MXL5005S_FP_SET_REGS_WITH_TABLE SetRegsWithTable;
584 MXL5005S_FP_SET_REG_MASK_BITS SetRegMaskBits; 450 MXL5005S_FP_SET_REG_MASK_BITS SetRegMaskBits;
585 MXL5005S_FP_SET_SPECTRUM_MODE SetSpectrumMode; 451 MXL5005S_FP_SET_SPECTRUM_MODE SetSpectrumMode;
586 MXL5005S_FP_SET_BANDWIDTH_HZ SetBandwidthHz; 452 MXL5005S_FP_SET_BANDWIDTH_HZ SetBandwidthHz;
587 453
454 /* MxL5005S extra data */
455 unsigned char AgcMasterByte; /* Variable name in MaxLinear source code: AGC_MASTER_BYTE */
588 456
589 // MxL5005S extra data 457 /* MaxLinear defined struct */
590 unsigned char AgcMasterByte; // Variable name in MaxLinear source code: AGC_MASTER_BYTE
591
592 // MaxLinear defined struct
593 Tuner_struct MxlDefinedTunerStructure; 458 Tuner_struct MxlDefinedTunerStructure;
594}; 459};
460/* End of common_mxl.h (?) */
595 461
596 462#endif /* __MXL5005S_H */
597
598
599
600// Builder
601void
602BuildMxl5005sModule(
603 TUNER_MODULE **ppTuner,
604 TUNER_MODULE *pTunerModuleMemory,
605 MXL5005S_EXTRA_MODULE *pMxl5005sExtraModuleMemory,
606 BASE_INTERFACE_MODULE *pBaseInterfaceModuleMemory,
607 I2C_BRIDGE_MODULE *pI2cBridgeModuleMemory,
608 unsigned char DeviceAddr,
609 int StandardMode
610 );
611
612
613
614
615
616// Manipulaing functions
617void
618mxl5005s_SetDeviceAddr(
619 TUNER_MODULE *pTuner,
620 unsigned char DeviceAddr
621 );
622
623void
624mxl5005s_GetTunerType(
625 TUNER_MODULE *pTuner,
626 int *pTunerType
627 );
628
629int
630mxl5005s_GetDeviceAddr(
631 TUNER_MODULE *pTuner,
632 unsigned char *pDeviceAddr
633 );
634
635int
636mxl5005s_Initialize(
637 struct dvb_usb_device* dib,
638 TUNER_MODULE *pTuner
639 );
640
641int
642mxl5005s_SetRfFreqHz(
643 struct dvb_usb_device* dib,
644 TUNER_MODULE *pTuner,
645 unsigned long RfFreqHz
646 );
647
648int
649mxl5005s_GetRfFreqHz(
650 struct dvb_usb_device* dib,
651 TUNER_MODULE *pTuner,
652 unsigned long *pRfFreqHz
653 );
654
655
656
657
658
659// Extra manipulaing functions
660int
661mxl5005s_SetRegsWithTable(
662 struct dvb_usb_device* dib,
663 TUNER_MODULE *pTuner,
664 unsigned char *pAddrTable,
665 unsigned char *pByteTable,
666 int TableLen
667 );
668
669int
670mxl5005s_SetRegMaskBits(
671 struct dvb_usb_device* dib,
672 TUNER_MODULE *pTuner,
673 unsigned char RegAddr,
674 unsigned char Msb,
675 unsigned char Lsb,
676 const unsigned char WritingValue
677 );
678
679int
680mxl5005s_SetSpectrumMode(
681 struct dvb_usb_device* dib,
682 TUNER_MODULE *pTuner,
683 int SpectrumMode
684 );
685
686int
687mxl5005s_SetBandwidthHz(
688 struct dvb_usb_device* dib,
689 TUNER_MODULE *pTuner,
690 unsigned long BandwidthHz
691 );
692
693
694
695
696
697// I2C birdge module demod argument setting
698void
699mxl5005s_SetI2cBridgeModuleTunerArg(
700 TUNER_MODULE *pTuner
701 );
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717#endif
718 463
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 00:36:05 -0500