diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-08-05 22:37:42 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-08-05 22:37:42 -0400 |
commit | e63e03273b89f7248baa56cf242474f661e776e1 (patch) | |
tree | 7e0a000ed3b252849b9002306ba479074c165330 /drivers | |
parent | 37193fb4639fa94f91cbbab1e8aca596300e1d94 (diff) | |
parent | ffb208479bd62ab26c29a242faeb1de1c6d5fcdc (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (78 commits)
AX.25: Fix sysctl registration if !CONFIG_AX25_DAMA_SLAVE
pktgen: mac count
pktgen: random flow
bridge: Eliminate unnecessary forward delay
bridge: fix compile warning in net/bridge/br_netfilter.c
ipv4: remove unused field in struct flowi (include/net/flow.h).
tg3: Fix 'scheduling while atomic' errors
net: Kill plain NET_XMIT_BYPASS.
net_sched: Add qdisc __NET_XMIT_BYPASS flag
net_sched: Add qdisc __NET_XMIT_STOLEN flag
iwl3945: fix merge mistake for packet injection
iwlwifi: grap nic access before accessing periphery registers
iwlwifi: decrement rx skb counter in scan abort handler
iwlwifi: fix unhandled interrupt when HW rfkill is on
iwlwifi: implement iwl5000_calc_rssi
iwlwifi: memory allocation optimization
iwlwifi: HW bug fixes
p54: Fix potential concurrent access to private data
rt2x00: Disable link tuning in rt2500usb
iwlwifi: Don't use buffer allocated on the stack for led names
...
Diffstat (limited to 'drivers')
56 files changed, 1834 insertions, 1121 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 26aa37aa531f..d2439b85a790 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -7687,21 +7687,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
7687 | */ | 7687 | */ |
7688 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) | 7688 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
7689 | { | 7689 | { |
7690 | int err; | ||
7691 | |||
7692 | /* Force the chip into D0. */ | ||
7693 | err = tg3_set_power_state(tp, PCI_D0); | ||
7694 | if (err) | ||
7695 | goto out; | ||
7696 | |||
7697 | tg3_switch_clocks(tp); | 7690 | tg3_switch_clocks(tp); |
7698 | 7691 | ||
7699 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | 7692 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); |
7700 | 7693 | ||
7701 | err = tg3_reset_hw(tp, reset_phy); | 7694 | return tg3_reset_hw(tp, reset_phy); |
7702 | |||
7703 | out: | ||
7704 | return err; | ||
7705 | } | 7695 | } |
7706 | 7696 | ||
7707 | #define TG3_STAT_ADD32(PSTAT, REG) \ | 7697 | #define TG3_STAT_ADD32(PSTAT, REG) \ |
@@ -8016,13 +8006,11 @@ static int tg3_open(struct net_device *dev) | |||
8016 | 8006 | ||
8017 | netif_carrier_off(tp->dev); | 8007 | netif_carrier_off(tp->dev); |
8018 | 8008 | ||
8019 | tg3_full_lock(tp, 0); | ||
8020 | |||
8021 | err = tg3_set_power_state(tp, PCI_D0); | 8009 | err = tg3_set_power_state(tp, PCI_D0); |
8022 | if (err) { | 8010 | if (err) |
8023 | tg3_full_unlock(tp); | ||
8024 | return err; | 8011 | return err; |
8025 | } | 8012 | |
8013 | tg3_full_lock(tp, 0); | ||
8026 | 8014 | ||
8027 | tg3_disable_ints(tp); | 8015 | tg3_disable_ints(tp); |
8028 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | 8016 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig index 91fc2c765d90..4c7ff61a1a9c 100644 --- a/drivers/net/wireless/Kconfig +++ b/drivers/net/wireless/Kconfig | |||
@@ -649,6 +649,7 @@ config RTL8187 | |||
649 | Trendnet TEW-424UB | 649 | Trendnet TEW-424UB |
650 | ASUS P5B Deluxe | 650 | ASUS P5B Deluxe |
651 | Toshiba Satellite Pro series of laptops | 651 | Toshiba Satellite Pro series of laptops |
652 | Asus Wireless Link | ||
652 | 653 | ||
653 | Thanks to Realtek for their support! | 654 | Thanks to Realtek for their support! |
654 | 655 | ||
diff --git a/drivers/net/wireless/ath5k/ath5k.h b/drivers/net/wireless/ath5k/ath5k.h index ba35c30d203c..9102eea3c8bf 100644 --- a/drivers/net/wireless/ath5k/ath5k.h +++ b/drivers/net/wireless/ath5k/ath5k.h | |||
@@ -186,11 +186,13 @@ struct ath5k_srev_name { | |||
186 | #define AR5K_SREV_RAD_2111 0x20 | 186 | #define AR5K_SREV_RAD_2111 0x20 |
187 | #define AR5K_SREV_RAD_5112 0x30 | 187 | #define AR5K_SREV_RAD_5112 0x30 |
188 | #define AR5K_SREV_RAD_5112A 0x35 | 188 | #define AR5K_SREV_RAD_5112A 0x35 |
189 | #define AR5K_SREV_RAD_5112B 0x36 | ||
189 | #define AR5K_SREV_RAD_2112 0x40 | 190 | #define AR5K_SREV_RAD_2112 0x40 |
190 | #define AR5K_SREV_RAD_2112A 0x45 | 191 | #define AR5K_SREV_RAD_2112A 0x45 |
191 | #define AR5K_SREV_RAD_SC0 0x56 /* Found on 2413/2414 */ | 192 | #define AR5K_SREV_RAD_2112B 0x46 |
192 | #define AR5K_SREV_RAD_SC1 0x63 /* Found on 5413/5414 */ | 193 | #define AR5K_SREV_RAD_SC0 0x50 /* Found on 2413/2414 */ |
193 | #define AR5K_SREV_RAD_SC2 0xa2 /* Found on 2424-5/5424 */ | 194 | #define AR5K_SREV_RAD_SC1 0x60 /* Found on 5413/5414 */ |
195 | #define AR5K_SREV_RAD_SC2 0xa0 /* Found on 2424-5/5424 */ | ||
194 | #define AR5K_SREV_RAD_5133 0xc0 /* MIMO found on 5418 */ | 196 | #define AR5K_SREV_RAD_5133 0xc0 /* MIMO found on 5418 */ |
195 | 197 | ||
196 | /* IEEE defs */ | 198 | /* IEEE defs */ |
diff --git a/drivers/net/wireless/ath5k/base.c b/drivers/net/wireless/ath5k/base.c index ff3fad794b61..ebf19bc11f5b 100644 --- a/drivers/net/wireless/ath5k/base.c +++ b/drivers/net/wireless/ath5k/base.c | |||
@@ -2170,6 +2170,7 @@ ath5k_beacon_config(struct ath5k_softc *sc) | |||
2170 | 2170 | ||
2171 | ath5k_hw_set_intr(ah, 0); | 2171 | ath5k_hw_set_intr(ah, 0); |
2172 | sc->bmisscount = 0; | 2172 | sc->bmisscount = 0; |
2173 | sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); | ||
2173 | 2174 | ||
2174 | if (sc->opmode == IEEE80211_IF_TYPE_STA) { | 2175 | if (sc->opmode == IEEE80211_IF_TYPE_STA) { |
2175 | sc->imask |= AR5K_INT_BMISS; | 2176 | sc->imask |= AR5K_INT_BMISS; |
diff --git a/drivers/net/wireless/ath5k/debug.c b/drivers/net/wireless/ath5k/debug.c index 41d5fa34b544..6fa6c8e04ff0 100644 --- a/drivers/net/wireless/ath5k/debug.c +++ b/drivers/net/wireless/ath5k/debug.c | |||
@@ -129,7 +129,7 @@ static struct reg regs[] = { | |||
129 | REG_STRUCT_INIT(AR5K_CPC1), | 129 | REG_STRUCT_INIT(AR5K_CPC1), |
130 | REG_STRUCT_INIT(AR5K_CPC2), | 130 | REG_STRUCT_INIT(AR5K_CPC2), |
131 | REG_STRUCT_INIT(AR5K_CPC3), | 131 | REG_STRUCT_INIT(AR5K_CPC3), |
132 | REG_STRUCT_INIT(AR5K_CPCORN), | 132 | REG_STRUCT_INIT(AR5K_CPCOVF), |
133 | REG_STRUCT_INIT(AR5K_RESET_CTL), | 133 | REG_STRUCT_INIT(AR5K_RESET_CTL), |
134 | REG_STRUCT_INIT(AR5K_SLEEP_CTL), | 134 | REG_STRUCT_INIT(AR5K_SLEEP_CTL), |
135 | REG_STRUCT_INIT(AR5K_INTPEND), | 135 | REG_STRUCT_INIT(AR5K_INTPEND), |
diff --git a/drivers/net/wireless/ath5k/debug.h b/drivers/net/wireless/ath5k/debug.h index 2cf8d18b10e3..ffc529393306 100644 --- a/drivers/net/wireless/ath5k/debug.h +++ b/drivers/net/wireless/ath5k/debug.h | |||
@@ -63,7 +63,6 @@ | |||
63 | 63 | ||
64 | struct ath5k_softc; | 64 | struct ath5k_softc; |
65 | struct ath5k_hw; | 65 | struct ath5k_hw; |
66 | struct ieee80211_hw_mode; | ||
67 | struct sk_buff; | 66 | struct sk_buff; |
68 | struct ath5k_buf; | 67 | struct ath5k_buf; |
69 | 68 | ||
diff --git a/drivers/net/wireless/ath5k/hw.c b/drivers/net/wireless/ath5k/hw.c index 7ca87a557312..ad1a5b422c8c 100644 --- a/drivers/net/wireless/ath5k/hw.c +++ b/drivers/net/wireless/ath5k/hw.c | |||
@@ -139,6 +139,8 @@ static int ath5k_hw_post(struct ath5k_hw *ah) | |||
139 | for (c = 0; c < 2; c++) { | 139 | for (c = 0; c < 2; c++) { |
140 | 140 | ||
141 | cur_reg = regs[c]; | 141 | cur_reg = regs[c]; |
142 | |||
143 | /* Save previous value */ | ||
142 | init_val = ath5k_hw_reg_read(ah, cur_reg); | 144 | init_val = ath5k_hw_reg_read(ah, cur_reg); |
143 | 145 | ||
144 | for (i = 0; i < 256; i++) { | 146 | for (i = 0; i < 256; i++) { |
@@ -170,6 +172,10 @@ static int ath5k_hw_post(struct ath5k_hw *ah) | |||
170 | var_pattern = 0x003b080f; | 172 | var_pattern = 0x003b080f; |
171 | ath5k_hw_reg_write(ah, var_pattern, cur_reg); | 173 | ath5k_hw_reg_write(ah, var_pattern, cur_reg); |
172 | } | 174 | } |
175 | |||
176 | /* Restore previous value */ | ||
177 | ath5k_hw_reg_write(ah, init_val, cur_reg); | ||
178 | |||
173 | } | 179 | } |
174 | 180 | ||
175 | return 0; | 181 | return 0; |
@@ -287,67 +293,42 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version) | |||
287 | /* Identify the radio chip*/ | 293 | /* Identify the radio chip*/ |
288 | if (ah->ah_version == AR5K_AR5210) { | 294 | if (ah->ah_version == AR5K_AR5210) { |
289 | ah->ah_radio = AR5K_RF5110; | 295 | ah->ah_radio = AR5K_RF5110; |
296 | /* | ||
297 | * Register returns 0x0/0x04 for radio revision | ||
298 | * so ath5k_hw_radio_revision doesn't parse the value | ||
299 | * correctly. For now we are based on mac's srev to | ||
300 | * identify RF2425 radio. | ||
301 | */ | ||
302 | } else if (srev == AR5K_SREV_VER_AR2425) { | ||
303 | ah->ah_radio = AR5K_RF2425; | ||
304 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425; | ||
290 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) { | 305 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) { |
291 | ah->ah_radio = AR5K_RF5111; | 306 | ah->ah_radio = AR5K_RF5111; |
292 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111; | 307 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111; |
293 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) { | 308 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) { |
294 | |||
295 | ah->ah_radio = AR5K_RF5112; | 309 | ah->ah_radio = AR5K_RF5112; |
296 | 310 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112; | |
297 | if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { | ||
298 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112; | ||
299 | } else { | ||
300 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A; | ||
301 | } | ||
302 | |||
303 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) { | 311 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) { |
304 | ah->ah_radio = AR5K_RF2413; | 312 | ah->ah_radio = AR5K_RF2413; |
305 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A; | 313 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413; |
306 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) { | 314 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) { |
307 | ah->ah_radio = AR5K_RF5413; | 315 | ah->ah_radio = AR5K_RF5413; |
308 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A; | 316 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413; |
309 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) { | 317 | } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) { |
310 | |||
311 | /* AR5424 */ | 318 | /* AR5424 */ |
312 | if (srev >= AR5K_SREV_VER_AR5424) { | 319 | if (srev >= AR5K_SREV_VER_AR5424) { |
313 | ah->ah_radio = AR5K_RF5413; | 320 | ah->ah_radio = AR5K_RF5413; |
314 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5424; | 321 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413; |
315 | /* AR2424 */ | 322 | /* AR2424 */ |
316 | } else { | 323 | } else { |
317 | ah->ah_radio = AR5K_RF2413; /* For testing */ | 324 | ah->ah_radio = AR5K_RF2413; /* For testing */ |
318 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A; | 325 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413; |
319 | } | 326 | } |
320 | |||
321 | /* | ||
322 | * Register returns 0x4 for radio revision | ||
323 | * so ath5k_hw_radio_revision doesn't parse the value | ||
324 | * correctly. For now we are based on mac's srev to | ||
325 | * identify RF2425 radio. | ||
326 | */ | ||
327 | } else if (srev == AR5K_SREV_VER_AR2425) { | ||
328 | ah->ah_radio = AR5K_RF2425; | ||
329 | ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112; | ||
330 | } | 327 | } |
331 | |||
332 | ah->ah_phy = AR5K_PHY(0); | 328 | ah->ah_phy = AR5K_PHY(0); |
333 | 329 | ||
334 | /* | 330 | /* |
335 | * Identify AR5212-based PCI-E cards | 331 | * Write PCI-E power save settings |
336 | * And write some initial settings. | ||
337 | * | ||
338 | * (doing a "strings" on ndis driver | ||
339 | * -ar5211.sys- reveals the following | ||
340 | * pci-e related functions: | ||
341 | * | ||
342 | * pcieClockReq | ||
343 | * pcieRxErrNotify | ||
344 | * pcieL1SKPEnable | ||
345 | * pcieAspm | ||
346 | * pcieDisableAspmOnRfWake | ||
347 | * pciePowerSaveEnable | ||
348 | * | ||
349 | * I guess these point to ClockReq but | ||
350 | * i'm not sure.) | ||
351 | */ | 332 | */ |
352 | if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) { | 333 | if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) { |
353 | ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080); | 334 | ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080); |
@@ -369,10 +350,15 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version) | |||
369 | if (ret) | 350 | if (ret) |
370 | goto err_free; | 351 | goto err_free; |
371 | 352 | ||
353 | /* Write AR5K_PCICFG_UNK on 2112B and later chips */ | ||
354 | if (ah->ah_radio_5ghz_revision > AR5K_SREV_RAD_2112B || | ||
355 | srev > AR5K_SREV_VER_AR2413) { | ||
356 | ath5k_hw_reg_write(ah, AR5K_PCICFG_UNK, AR5K_PCICFG); | ||
357 | } | ||
358 | |||
372 | /* | 359 | /* |
373 | * Get card capabilities, values, ... | 360 | * Get card capabilities, values, ... |
374 | */ | 361 | */ |
375 | |||
376 | ret = ath5k_eeprom_init(ah); | 362 | ret = ath5k_eeprom_init(ah); |
377 | if (ret) { | 363 | if (ret) { |
378 | ATH5K_ERR(sc, "unable to init EEPROM\n"); | 364 | ATH5K_ERR(sc, "unable to init EEPROM\n"); |
@@ -843,27 +829,41 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
843 | * Write some more initial register settings | 829 | * Write some more initial register settings |
844 | */ | 830 | */ |
845 | if (ah->ah_version == AR5K_AR5212) { | 831 | if (ah->ah_version == AR5K_AR5212) { |
846 | ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11)); | 832 | ath5k_hw_reg_write(ah, 0x0002a002, 0x982c); |
847 | 833 | ||
848 | if (channel->hw_value == CHANNEL_G) | 834 | if (channel->hw_value == CHANNEL_G) |
849 | if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413) | 835 | if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413) |
850 | ath5k_hw_reg_write(ah, 0x00f80d80, | 836 | ath5k_hw_reg_write(ah, 0x00f80d80, |
851 | AR5K_PHY(83)); | 837 | 0x994c); |
852 | else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424) | 838 | else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424) |
853 | ath5k_hw_reg_write(ah, 0x00380140, | 839 | ath5k_hw_reg_write(ah, 0x00380140, |
854 | AR5K_PHY(83)); | 840 | 0x994c); |
855 | else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425) | 841 | else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425) |
856 | ath5k_hw_reg_write(ah, 0x00fc0ec0, | 842 | ath5k_hw_reg_write(ah, 0x00fc0ec0, |
857 | AR5K_PHY(83)); | 843 | 0x994c); |
858 | else /* 2425 */ | 844 | else /* 2425 */ |
859 | ath5k_hw_reg_write(ah, 0x00fc0fc0, | 845 | ath5k_hw_reg_write(ah, 0x00fc0fc0, |
860 | AR5K_PHY(83)); | 846 | 0x994c); |
861 | else | 847 | else |
862 | ath5k_hw_reg_write(ah, 0x00000000, | 848 | ath5k_hw_reg_write(ah, 0x00000000, 0x994c); |
863 | AR5K_PHY(83)); | 849 | |
864 | 850 | /* Some bits are disabled here, we know nothing about | |
865 | ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); | 851 | * register 0xa228 yet, most of the times this ends up |
866 | ath5k_hw_reg_write(ah, 0x0000000f, 0x8060); | 852 | * with a value 0x9b5 -haven't seen any dump with |
853 | * a different value- */ | ||
854 | /* Got this from decompiling binary HAL */ | ||
855 | data = ath5k_hw_reg_read(ah, 0xa228); | ||
856 | data &= 0xfffffdff; | ||
857 | ath5k_hw_reg_write(ah, data, 0xa228); | ||
858 | |||
859 | data = ath5k_hw_reg_read(ah, 0xa228); | ||
860 | data &= 0xfffe03ff; | ||
861 | ath5k_hw_reg_write(ah, data, 0xa228); | ||
862 | data = 0; | ||
863 | |||
864 | /* Just write 0x9b5 ? */ | ||
865 | /* ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); */ | ||
866 | ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK); | ||
867 | ath5k_hw_reg_write(ah, 0x00000000, 0xa254); | 867 | ath5k_hw_reg_write(ah, 0x00000000, 0xa254); |
868 | ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL); | 868 | ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL); |
869 | } | 869 | } |
@@ -879,6 +879,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
879 | else | 879 | else |
880 | data = 0xffb80d20; | 880 | data = 0xffb80d20; |
881 | ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL); | 881 | ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL); |
882 | data = 0; | ||
882 | } | 883 | } |
883 | 884 | ||
884 | /* | 885 | /* |
@@ -898,7 +899,6 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
898 | 899 | ||
899 | /* | 900 | /* |
900 | * Write RF registers | 901 | * Write RF registers |
901 | * TODO:Does this work on 5211 (5111) ? | ||
902 | */ | 902 | */ |
903 | ret = ath5k_hw_rfregs(ah, channel, mode); | 903 | ret = ath5k_hw_rfregs(ah, channel, mode); |
904 | if (ret) | 904 | if (ret) |
@@ -935,7 +935,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
935 | return ret; | 935 | return ret; |
936 | 936 | ||
937 | /* Set antenna mode */ | 937 | /* Set antenna mode */ |
938 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x44), | 938 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY_ANT_CTL, |
939 | ah->ah_antenna[ee_mode][0], 0xfffffc06); | 939 | ah->ah_antenna[ee_mode][0], 0xfffffc06); |
940 | 940 | ||
941 | /* | 941 | /* |
@@ -965,15 +965,15 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
965 | 965 | ||
966 | ath5k_hw_reg_write(ah, | 966 | ath5k_hw_reg_write(ah, |
967 | AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), | 967 | AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]), |
968 | AR5K_PHY(0x5a)); | 968 | AR5K_PHY_NFTHRES); |
969 | 969 | ||
970 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x11), | 970 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY_SETTLING, |
971 | (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, | 971 | (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80, |
972 | 0xffffc07f); | 972 | 0xffffc07f); |
973 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x12), | 973 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY_GAIN, |
974 | (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, | 974 | (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000, |
975 | 0xfffc0fff); | 975 | 0xfffc0fff); |
976 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x14), | 976 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY_DESIRED_SIZE, |
977 | (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | | 977 | (ee->ee_adc_desired_size[ee_mode] & 0x00ff) | |
978 | ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), | 978 | ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00), |
979 | 0xffff0000); | 979 | 0xffff0000); |
@@ -982,13 +982,13 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
982 | (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | | 982 | (ee->ee_tx_end2xpa_disable[ee_mode] << 24) | |
983 | (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | | 983 | (ee->ee_tx_end2xpa_disable[ee_mode] << 16) | |
984 | (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | | 984 | (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) | |
985 | (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d)); | 985 | (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4); |
986 | 986 | ||
987 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x0a), | 987 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY_RF_CTL3, |
988 | ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); | 988 | ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff); |
989 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x19), | 989 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY_NF, |
990 | (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); | 990 | (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff); |
991 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x49), 4, 0xffffff01); | 991 | AR5K_REG_MASKED_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 4, 0xffffff01); |
992 | 992 | ||
993 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, | 993 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, |
994 | AR5K_PHY_IQ_CORR_ENABLE | | 994 | AR5K_PHY_IQ_CORR_ENABLE | |
@@ -1063,7 +1063,8 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
1063 | ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); | 1063 | ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); |
1064 | 1064 | ||
1065 | /* | 1065 | /* |
1066 | * 5111/5112 Specific | 1066 | * On 5211+ read activation -> rx delay |
1067 | * and use it. | ||
1067 | */ | 1068 | */ |
1068 | if (ah->ah_version != AR5K_AR5210) { | 1069 | if (ah->ah_version != AR5K_AR5210) { |
1069 | data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & | 1070 | data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & |
@@ -1071,40 +1072,77 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
1071 | data = (channel->hw_value & CHANNEL_CCK) ? | 1072 | data = (channel->hw_value & CHANNEL_CCK) ? |
1072 | ((data << 2) / 22) : (data / 10); | 1073 | ((data << 2) / 22) : (data / 10); |
1073 | 1074 | ||
1074 | udelay(100 + data); | 1075 | udelay(100 + (2 * data)); |
1076 | data = 0; | ||
1075 | } else { | 1077 | } else { |
1076 | mdelay(1); | 1078 | mdelay(1); |
1077 | } | 1079 | } |
1078 | 1080 | ||
1079 | /* | 1081 | /* |
1080 | * Enable calibration and wait until completion | 1082 | * Perform ADC test (?) |
1083 | */ | ||
1084 | data = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); | ||
1085 | ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); | ||
1086 | for (i = 0; i <= 20; i++) { | ||
1087 | if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) | ||
1088 | break; | ||
1089 | udelay(200); | ||
1090 | } | ||
1091 | ath5k_hw_reg_write(ah, data, AR5K_PHY_TST1); | ||
1092 | data = 0; | ||
1093 | |||
1094 | /* | ||
1095 | * Start automatic gain calibration | ||
1096 | * | ||
1097 | * During AGC calibration RX path is re-routed to | ||
1098 | * a signal detector so we don't receive anything. | ||
1099 | * | ||
1100 | * This method is used to calibrate some static offsets | ||
1101 | * used together with on-the fly I/Q calibration (the | ||
1102 | * one performed via ath5k_hw_phy_calibrate), that doesn't | ||
1103 | * interrupt rx path. | ||
1104 | * | ||
1105 | * If we are in a noisy environment AGC calibration may time | ||
1106 | * out. | ||
1081 | */ | 1107 | */ |
1082 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, | 1108 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, |
1083 | AR5K_PHY_AGCCTL_CAL); | 1109 | AR5K_PHY_AGCCTL_CAL); |
1084 | 1110 | ||
1111 | /* At the same time start I/Q calibration for QAM constellation | ||
1112 | * -no need for CCK- */ | ||
1113 | ah->ah_calibration = false; | ||
1114 | if (!(mode == AR5K_MODE_11B)) { | ||
1115 | ah->ah_calibration = true; | ||
1116 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, | ||
1117 | AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); | ||
1118 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, | ||
1119 | AR5K_PHY_IQ_RUN); | ||
1120 | } | ||
1121 | |||
1122 | /* Wait for gain calibration to finish (we check for I/Q calibration | ||
1123 | * during ath5k_phy_calibrate) */ | ||
1085 | if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, | 1124 | if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, |
1086 | AR5K_PHY_AGCCTL_CAL, 0, false)) { | 1125 | AR5K_PHY_AGCCTL_CAL, 0, false)) { |
1087 | ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n", | 1126 | ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n", |
1088 | channel->center_freq); | 1127 | channel->center_freq); |
1089 | return -EAGAIN; | 1128 | return -EAGAIN; |
1090 | } | 1129 | } |
1091 | 1130 | ||
1131 | /* | ||
1132 | * Start noise floor calibration | ||
1133 | * | ||
1134 | * If we run NF calibration before AGC, it always times out. | ||
1135 | * Binary HAL starts NF and AGC calibration at the same time | ||
1136 | * and only waits for AGC to finish. I believe that's wrong because | ||
1137 | * during NF calibration, rx path is also routed to a detector, so if | ||
1138 | * it doesn't finish we won't have RX. | ||
1139 | * | ||
1140 | * XXX: Find an interval that's OK for all cards... | ||
1141 | */ | ||
1092 | ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq); | 1142 | ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq); |
1093 | if (ret) | 1143 | if (ret) |
1094 | return ret; | 1144 | return ret; |
1095 | 1145 | ||
1096 | ah->ah_calibration = false; | ||
1097 | |||
1098 | /* A and G modes can use QAM modulation which requires enabling | ||
1099 | * I and Q calibration. Don't bother in B mode. */ | ||
1100 | if (!(mode == AR5K_MODE_11B)) { | ||
1101 | ah->ah_calibration = true; | ||
1102 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, | ||
1103 | AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); | ||
1104 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, | ||
1105 | AR5K_PHY_IQ_RUN); | ||
1106 | } | ||
1107 | |||
1108 | /* | 1146 | /* |
1109 | * Reset queues and start beacon timers at the end of the reset routine | 1147 | * Reset queues and start beacon timers at the end of the reset routine |
1110 | */ | 1148 | */ |
@@ -1154,6 +1192,12 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode, | |||
1154 | ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); | 1192 | ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); |
1155 | ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); | 1193 | ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); |
1156 | ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING); | 1194 | ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING); |
1195 | |||
1196 | data = ath5k_hw_reg_read(ah, AR5K_USEC_5211) & 0xffffc07f ; | ||
1197 | data |= (ah->ah_phy_spending == AR5K_PHY_SPENDING_18) ? | ||
1198 | 0x00000f80 : 0x00001380 ; | ||
1199 | ath5k_hw_reg_write(ah, data, AR5K_USEC_5211); | ||
1200 | data = 0; | ||
1157 | } | 1201 | } |
1158 | 1202 | ||
1159 | if (ah->ah_version == AR5K_AR5212) { | 1203 | if (ah->ah_version == AR5K_AR5212) { |
@@ -1226,7 +1270,7 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, | |||
1226 | bool set_chip, u16 sleep_duration) | 1270 | bool set_chip, u16 sleep_duration) |
1227 | { | 1271 | { |
1228 | unsigned int i; | 1272 | unsigned int i; |
1229 | u32 staid; | 1273 | u32 staid, data; |
1230 | 1274 | ||
1231 | ATH5K_TRACE(ah->ah_sc); | 1275 | ATH5K_TRACE(ah->ah_sc); |
1232 | staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1); | 1276 | staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1); |
@@ -1238,7 +1282,8 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, | |||
1238 | case AR5K_PM_NETWORK_SLEEP: | 1282 | case AR5K_PM_NETWORK_SLEEP: |
1239 | if (set_chip) | 1283 | if (set_chip) |
1240 | ath5k_hw_reg_write(ah, | 1284 | ath5k_hw_reg_write(ah, |
1241 | AR5K_SLEEP_CTL_SLE | sleep_duration, | 1285 | AR5K_SLEEP_CTL_SLE_ALLOW | |
1286 | sleep_duration, | ||
1242 | AR5K_SLEEP_CTL); | 1287 | AR5K_SLEEP_CTL); |
1243 | 1288 | ||
1244 | staid |= AR5K_STA_ID1_PWR_SV; | 1289 | staid |= AR5K_STA_ID1_PWR_SV; |
@@ -1253,13 +1298,24 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, | |||
1253 | break; | 1298 | break; |
1254 | 1299 | ||
1255 | case AR5K_PM_AWAKE: | 1300 | case AR5K_PM_AWAKE: |
1301 | |||
1302 | staid &= ~AR5K_STA_ID1_PWR_SV; | ||
1303 | |||
1256 | if (!set_chip) | 1304 | if (!set_chip) |
1257 | goto commit; | 1305 | goto commit; |
1258 | 1306 | ||
1259 | ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE, | 1307 | /* Preserve sleep duration */ |
1260 | AR5K_SLEEP_CTL); | 1308 | data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL); |
1309 | if( data & 0xffc00000 ){ | ||
1310 | data = 0; | ||
1311 | } else { | ||
1312 | data = data & 0xfffcffff; | ||
1313 | } | ||
1314 | |||
1315 | ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL); | ||
1316 | udelay(15); | ||
1261 | 1317 | ||
1262 | for (i = 5000; i > 0; i--) { | 1318 | for (i = 50; i > 0; i--) { |
1263 | /* Check if the chip did wake up */ | 1319 | /* Check if the chip did wake up */ |
1264 | if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) & | 1320 | if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) & |
1265 | AR5K_PCICFG_SPWR_DN) == 0) | 1321 | AR5K_PCICFG_SPWR_DN) == 0) |
@@ -1267,15 +1323,13 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, | |||
1267 | 1323 | ||
1268 | /* Wait a bit and retry */ | 1324 | /* Wait a bit and retry */ |
1269 | udelay(200); | 1325 | udelay(200); |
1270 | ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE, | 1326 | ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL); |
1271 | AR5K_SLEEP_CTL); | ||
1272 | } | 1327 | } |
1273 | 1328 | ||
1274 | /* Fail if the chip didn't wake up */ | 1329 | /* Fail if the chip didn't wake up */ |
1275 | if (i <= 0) | 1330 | if (i <= 0) |
1276 | return -EIO; | 1331 | return -EIO; |
1277 | 1332 | ||
1278 | staid &= ~AR5K_STA_ID1_PWR_SV; | ||
1279 | break; | 1333 | break; |
1280 | 1334 | ||
1281 | default: | 1335 | default: |
@@ -1304,6 +1358,7 @@ void ath5k_hw_start_rx(struct ath5k_hw *ah) | |||
1304 | { | 1358 | { |
1305 | ATH5K_TRACE(ah->ah_sc); | 1359 | ATH5K_TRACE(ah->ah_sc); |
1306 | ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); | 1360 | ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); |
1361 | ath5k_hw_reg_read(ah, AR5K_CR); | ||
1307 | } | 1362 | } |
1308 | 1363 | ||
1309 | /* | 1364 | /* |
@@ -1390,6 +1445,7 @@ int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue) | |||
1390 | } | 1445 | } |
1391 | /* Start queue */ | 1446 | /* Start queue */ |
1392 | ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); | 1447 | ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); |
1448 | ath5k_hw_reg_read(ah, AR5K_CR); | ||
1393 | } else { | 1449 | } else { |
1394 | /* Return if queue is disabled */ | 1450 | /* Return if queue is disabled */ |
1395 | if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue)) | 1451 | if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue)) |
@@ -1687,6 +1743,7 @@ enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask) | |||
1687 | * (they will be re-enabled afterwards). | 1743 | * (they will be re-enabled afterwards). |
1688 | */ | 1744 | */ |
1689 | ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER); | 1745 | ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER); |
1746 | ath5k_hw_reg_read(ah, AR5K_IER); | ||
1690 | 1747 | ||
1691 | old_mask = ah->ah_imr; | 1748 | old_mask = ah->ah_imr; |
1692 | 1749 | ||
@@ -3363,11 +3420,13 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue) | |||
3363 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 3420 | ath5k_hw_reg_write(ah, ah->ah_turbo ? |
3364 | AR5K_INIT_PROTO_TIME_CNTRL_TURBO : | 3421 | AR5K_INIT_PROTO_TIME_CNTRL_TURBO : |
3365 | AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); | 3422 | AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); |
3366 | /* Set PHY register 0x9844 (??) */ | 3423 | /* Set AR5K_PHY_SETTLING */ |
3367 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 3424 | ath5k_hw_reg_write(ah, ah->ah_turbo ? |
3368 | (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 : | 3425 | (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) |
3369 | (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C, | 3426 | | 0x38 : |
3370 | AR5K_PHY(17)); | 3427 | (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) |
3428 | | 0x1C, | ||
3429 | AR5K_PHY_SETTLING); | ||
3371 | /* Set Frame Control Register */ | 3430 | /* Set Frame Control Register */ |
3372 | ath5k_hw_reg_write(ah, ah->ah_turbo ? | 3431 | ath5k_hw_reg_write(ah, ah->ah_turbo ? |
3373 | (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | | 3432 | (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | |
@@ -3488,7 +3547,7 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue) | |||
3488 | if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) | 3547 | if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) |
3489 | AR5K_REG_ENABLE_BITS(ah, | 3548 | AR5K_REG_ENABLE_BITS(ah, |
3490 | AR5K_QUEUE_MISC(queue), | 3549 | AR5K_QUEUE_MISC(queue), |
3491 | AR5K_QCU_MISC_TXE); | 3550 | AR5K_QCU_MISC_RDY_VEOL_POLICY); |
3492 | } | 3551 | } |
3493 | 3552 | ||
3494 | if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) | 3553 | if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) |
diff --git a/drivers/net/wireless/ath5k/initvals.c b/drivers/net/wireless/ath5k/initvals.c index 04c84e9da89d..2806b21bf90b 100644 --- a/drivers/net/wireless/ath5k/initvals.c +++ b/drivers/net/wireless/ath5k/initvals.c | |||
@@ -489,7 +489,7 @@ static const struct ath5k_ini ar5212_ini[] = { | |||
489 | { AR5K_QUEUE_TXDP(9), 0x00000000 }, | 489 | { AR5K_QUEUE_TXDP(9), 0x00000000 }, |
490 | { AR5K_DCU_FP, 0x00000000 }, | 490 | { AR5K_DCU_FP, 0x00000000 }, |
491 | { AR5K_DCU_TXP, 0x00000000 }, | 491 | { AR5K_DCU_TXP, 0x00000000 }, |
492 | { AR5K_DCU_TX_FILTER, 0x00000000 }, | 492 | { AR5K_DCU_TX_FILTER_0_BASE, 0x00000000 }, |
493 | /* Unknown table */ | 493 | /* Unknown table */ |
494 | { 0x1078, 0x00000000 }, | 494 | { 0x1078, 0x00000000 }, |
495 | { 0x10b8, 0x00000000 }, | 495 | { 0x10b8, 0x00000000 }, |
@@ -679,7 +679,7 @@ static const struct ath5k_ini ar5212_ini[] = { | |||
679 | { AR5K_PHY(645), 0x00106c10 }, | 679 | { AR5K_PHY(645), 0x00106c10 }, |
680 | { AR5K_PHY(646), 0x009c4060 }, | 680 | { AR5K_PHY(646), 0x009c4060 }, |
681 | { AR5K_PHY(647), 0x1483800a }, | 681 | { AR5K_PHY(647), 0x1483800a }, |
682 | /* { AR5K_PHY(648), 0x018830c6 },*/ /* 2413 */ | 682 | /* { AR5K_PHY(648), 0x018830c6 },*/ /* 2413/2425 */ |
683 | { AR5K_PHY(648), 0x01831061 }, | 683 | { AR5K_PHY(648), 0x01831061 }, |
684 | { AR5K_PHY(649), 0x00000400 }, | 684 | { AR5K_PHY(649), 0x00000400 }, |
685 | /*{ AR5K_PHY(650), 0x000001b5 },*/ | 685 | /*{ AR5K_PHY(650), 0x000001b5 },*/ |
diff --git a/drivers/net/wireless/ath5k/phy.c b/drivers/net/wireless/ath5k/phy.c index afd8689e5c03..fa0d47faf574 100644 --- a/drivers/net/wireless/ath5k/phy.c +++ b/drivers/net/wireless/ath5k/phy.c | |||
@@ -1020,6 +1020,74 @@ static const struct ath5k_ini_rfgain rfgain_2413[] = { | |||
1020 | { AR5K_RF_GAIN(63), { 0x000000f9 } }, | 1020 | { AR5K_RF_GAIN(63), { 0x000000f9 } }, |
1021 | }; | 1021 | }; |
1022 | 1022 | ||
1023 | /* Initial RF Gain settings for RF2425 */ | ||
1024 | static const struct ath5k_ini_rfgain rfgain_2425[] = { | ||
1025 | { AR5K_RF_GAIN(0), { 0x00000000 } }, | ||
1026 | { AR5K_RF_GAIN(1), { 0x00000040 } }, | ||
1027 | { AR5K_RF_GAIN(2), { 0x00000080 } }, | ||
1028 | { AR5K_RF_GAIN(3), { 0x00000181 } }, | ||
1029 | { AR5K_RF_GAIN(4), { 0x000001c1 } }, | ||
1030 | { AR5K_RF_GAIN(5), { 0x00000001 } }, | ||
1031 | { AR5K_RF_GAIN(6), { 0x00000041 } }, | ||
1032 | { AR5K_RF_GAIN(7), { 0x00000081 } }, | ||
1033 | { AR5K_RF_GAIN(8), { 0x00000188 } }, | ||
1034 | { AR5K_RF_GAIN(9), { 0x000001c8 } }, | ||
1035 | { AR5K_RF_GAIN(10), { 0x00000008 } }, | ||
1036 | { AR5K_RF_GAIN(11), { 0x00000048 } }, | ||
1037 | { AR5K_RF_GAIN(12), { 0x00000088 } }, | ||
1038 | { AR5K_RF_GAIN(13), { 0x00000189 } }, | ||
1039 | { AR5K_RF_GAIN(14), { 0x000001c9 } }, | ||
1040 | { AR5K_RF_GAIN(15), { 0x00000009 } }, | ||
1041 | { AR5K_RF_GAIN(16), { 0x00000049 } }, | ||
1042 | { AR5K_RF_GAIN(17), { 0x00000089 } }, | ||
1043 | { AR5K_RF_GAIN(18), { 0x000001b0 } }, | ||
1044 | { AR5K_RF_GAIN(19), { 0x000001f0 } }, | ||
1045 | { AR5K_RF_GAIN(20), { 0x00000030 } }, | ||
1046 | { AR5K_RF_GAIN(21), { 0x00000070 } }, | ||
1047 | { AR5K_RF_GAIN(22), { 0x00000171 } }, | ||
1048 | { AR5K_RF_GAIN(23), { 0x000001b1 } }, | ||
1049 | { AR5K_RF_GAIN(24), { 0x000001f1 } }, | ||
1050 | { AR5K_RF_GAIN(25), { 0x00000031 } }, | ||
1051 | { AR5K_RF_GAIN(26), { 0x00000071 } }, | ||
1052 | { AR5K_RF_GAIN(27), { 0x000001b8 } }, | ||
1053 | { AR5K_RF_GAIN(28), { 0x000001f8 } }, | ||
1054 | { AR5K_RF_GAIN(29), { 0x00000038 } }, | ||
1055 | { AR5K_RF_GAIN(30), { 0x00000078 } }, | ||
1056 | { AR5K_RF_GAIN(31), { 0x000000b8 } }, | ||
1057 | { AR5K_RF_GAIN(32), { 0x000001b9 } }, | ||
1058 | { AR5K_RF_GAIN(33), { 0x000001f9 } }, | ||
1059 | { AR5K_RF_GAIN(34), { 0x00000039 } }, | ||
1060 | { AR5K_RF_GAIN(35), { 0x00000079 } }, | ||
1061 | { AR5K_RF_GAIN(36), { 0x000000b9 } }, | ||
1062 | { AR5K_RF_GAIN(37), { 0x000000f9 } }, | ||
1063 | { AR5K_RF_GAIN(38), { 0x000000f9 } }, | ||
1064 | { AR5K_RF_GAIN(39), { 0x000000f9 } }, | ||
1065 | { AR5K_RF_GAIN(40), { 0x000000f9 } }, | ||
1066 | { AR5K_RF_GAIN(41), { 0x000000f9 } }, | ||
1067 | { AR5K_RF_GAIN(42), { 0x000000f9 } }, | ||
1068 | { AR5K_RF_GAIN(43), { 0x000000f9 } }, | ||
1069 | { AR5K_RF_GAIN(44), { 0x000000f9 } }, | ||
1070 | { AR5K_RF_GAIN(45), { 0x000000f9 } }, | ||
1071 | { AR5K_RF_GAIN(46), { 0x000000f9 } }, | ||
1072 | { AR5K_RF_GAIN(47), { 0x000000f9 } }, | ||
1073 | { AR5K_RF_GAIN(48), { 0x000000f9 } }, | ||
1074 | { AR5K_RF_GAIN(49), { 0x000000f9 } }, | ||
1075 | { AR5K_RF_GAIN(50), { 0x000000f9 } }, | ||
1076 | { AR5K_RF_GAIN(51), { 0x000000f9 } }, | ||
1077 | { AR5K_RF_GAIN(52), { 0x000000f9 } }, | ||
1078 | { AR5K_RF_GAIN(53), { 0x000000f9 } }, | ||
1079 | { AR5K_RF_GAIN(54), { 0x000000f9 } }, | ||
1080 | { AR5K_RF_GAIN(55), { 0x000000f9 } }, | ||
1081 | { AR5K_RF_GAIN(56), { 0x000000f9 } }, | ||
1082 | { AR5K_RF_GAIN(57), { 0x000000f9 } }, | ||
1083 | { AR5K_RF_GAIN(58), { 0x000000f9 } }, | ||
1084 | { AR5K_RF_GAIN(59), { 0x000000f9 } }, | ||
1085 | { AR5K_RF_GAIN(60), { 0x000000f9 } }, | ||
1086 | { AR5K_RF_GAIN(61), { 0x000000f9 } }, | ||
1087 | { AR5K_RF_GAIN(62), { 0x000000f9 } }, | ||
1088 | { AR5K_RF_GAIN(63), { 0x000000f9 } }, | ||
1089 | }; | ||
1090 | |||
1023 | static const struct ath5k_gain_opt rfgain_opt_5112 = { | 1091 | static const struct ath5k_gain_opt rfgain_opt_5112 = { |
1024 | 1, | 1092 | 1, |
1025 | 8, | 1093 | 8, |
@@ -1588,8 +1656,8 @@ int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq) | |||
1588 | freq = 0; /* only 2Ghz */ | 1656 | freq = 0; /* only 2Ghz */ |
1589 | break; | 1657 | break; |
1590 | case AR5K_RF2425: | 1658 | case AR5K_RF2425: |
1591 | ath5k_rfg = rfgain_2413; | 1659 | ath5k_rfg = rfgain_2425; |
1592 | size = ARRAY_SIZE(rfgain_2413); | 1660 | size = ARRAY_SIZE(rfgain_2425); |
1593 | freq = 0; /* only 2Ghz */ | 1661 | freq = 0; /* only 2Ghz */ |
1594 | break; | 1662 | break; |
1595 | default: | 1663 | default: |
@@ -1830,9 +1898,6 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, | |||
1830 | data = data0 = data1 = data2 = 0; | 1898 | data = data0 = data1 = data2 = 0; |
1831 | c = channel->center_freq; | 1899 | c = channel->center_freq; |
1832 | 1900 | ||
1833 | /* | ||
1834 | * Set the channel on the RF5112 or newer | ||
1835 | */ | ||
1836 | if (c < 4800) { | 1901 | if (c < 4800) { |
1837 | if (!((c - 2224) % 5)) { | 1902 | if (!((c - 2224) % 5)) { |
1838 | data0 = ((2 * (c - 704)) - 3040) / 10; | 1903 | data0 = ((2 * (c - 704)) - 3040) / 10; |
@@ -1844,7 +1909,7 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, | |||
1844 | return -EINVAL; | 1909 | return -EINVAL; |
1845 | 1910 | ||
1846 | data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); | 1911 | data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8); |
1847 | } else { | 1912 | } else if ((c - (c % 5)) != 2 || c > 5435) { |
1848 | if (!(c % 20) && c >= 5120) { | 1913 | if (!(c % 20) && c >= 5120) { |
1849 | data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); | 1914 | data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); |
1850 | data2 = ath5k_hw_bitswap(3, 2); | 1915 | data2 = ath5k_hw_bitswap(3, 2); |
@@ -1856,6 +1921,9 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, | |||
1856 | data2 = ath5k_hw_bitswap(1, 2); | 1921 | data2 = ath5k_hw_bitswap(1, 2); |
1857 | } else | 1922 | } else |
1858 | return -EINVAL; | 1923 | return -EINVAL; |
1924 | } else { | ||
1925 | data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); | ||
1926 | data2 = ath5k_hw_bitswap(0, 2); | ||
1859 | } | 1927 | } |
1860 | 1928 | ||
1861 | data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; | 1929 | data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001; |
@@ -1867,6 +1935,45 @@ static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah, | |||
1867 | } | 1935 | } |
1868 | 1936 | ||
1869 | /* | 1937 | /* |
1938 | * Set the channel on the RF2425 | ||
1939 | */ | ||
1940 | static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah, | ||
1941 | struct ieee80211_channel *channel) | ||
1942 | { | ||
1943 | u32 data, data0, data2; | ||
1944 | u16 c; | ||
1945 | |||
1946 | data = data0 = data2 = 0; | ||
1947 | c = channel->center_freq; | ||
1948 | |||
1949 | if (c < 4800) { | ||
1950 | data0 = ath5k_hw_bitswap((c - 2272), 8); | ||
1951 | data2 = 0; | ||
1952 | /* ? 5GHz ? */ | ||
1953 | } else if ((c - (c % 5)) != 2 || c > 5435) { | ||
1954 | if (!(c % 20) && c < 5120) | ||
1955 | data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8); | ||
1956 | else if (!(c % 10)) | ||
1957 | data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8); | ||
1958 | else if (!(c % 5)) | ||
1959 | data0 = ath5k_hw_bitswap((c - 4800) / 5, 8); | ||
1960 | else | ||
1961 | return -EINVAL; | ||
1962 | data2 = ath5k_hw_bitswap(1, 2); | ||
1963 | } else { | ||
1964 | data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8); | ||
1965 | data2 = ath5k_hw_bitswap(0, 2); | ||
1966 | } | ||
1967 | |||
1968 | data = (data0 << 4) | data2 << 2 | 0x1001; | ||
1969 | |||
1970 | ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); | ||
1971 | ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); | ||
1972 | |||
1973 | return 0; | ||
1974 | } | ||
1975 | |||
1976 | /* | ||
1870 | * Set a channel on the radio chip | 1977 | * Set a channel on the radio chip |
1871 | */ | 1978 | */ |
1872 | int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) | 1979 | int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) |
@@ -1895,6 +2002,9 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) | |||
1895 | case AR5K_RF5111: | 2002 | case AR5K_RF5111: |
1896 | ret = ath5k_hw_rf5111_channel(ah, channel); | 2003 | ret = ath5k_hw_rf5111_channel(ah, channel); |
1897 | break; | 2004 | break; |
2005 | case AR5K_RF2425: | ||
2006 | ret = ath5k_hw_rf2425_channel(ah, channel); | ||
2007 | break; | ||
1898 | default: | 2008 | default: |
1899 | ret = ath5k_hw_rf5112_channel(ah, channel); | 2009 | ret = ath5k_hw_rf5112_channel(ah, channel); |
1900 | break; | 2010 | break; |
@@ -1903,6 +2013,15 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) | |||
1903 | if (ret) | 2013 | if (ret) |
1904 | return ret; | 2014 | return ret; |
1905 | 2015 | ||
2016 | /* Set JAPAN setting for channel 14 */ | ||
2017 | if (channel->center_freq == 2484) { | ||
2018 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, | ||
2019 | AR5K_PHY_CCKTXCTL_JAPAN); | ||
2020 | } else { | ||
2021 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, | ||
2022 | AR5K_PHY_CCKTXCTL_WORLD); | ||
2023 | } | ||
2024 | |||
1906 | ah->ah_current_channel.center_freq = channel->center_freq; | 2025 | ah->ah_current_channel.center_freq = channel->center_freq; |
1907 | ah->ah_current_channel.hw_value = channel->hw_value; | 2026 | ah->ah_current_channel.hw_value = channel->hw_value; |
1908 | ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; | 2027 | ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false; |
@@ -1933,6 +2052,8 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel) | |||
1933 | * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \ | 2052 | * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \ |
1934 | * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7 | 2053 | * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7 |
1935 | * | 2054 | * |
2055 | * XXX: Since during noise floor calibration antennas are detached according to | ||
2056 | * the patent, we should stop tx queues here. | ||
1936 | */ | 2057 | */ |
1937 | int | 2058 | int |
1938 | ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq) | 2059 | ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq) |
@@ -1942,7 +2063,7 @@ ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq) | |||
1942 | s32 noise_floor; | 2063 | s32 noise_floor; |
1943 | 2064 | ||
1944 | /* | 2065 | /* |
1945 | * Enable noise floor calibration and wait until completion | 2066 | * Enable noise floor calibration |
1946 | */ | 2067 | */ |
1947 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, | 2068 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, |
1948 | AR5K_PHY_AGCCTL_NF); | 2069 | AR5K_PHY_AGCCTL_NF); |
@@ -1952,7 +2073,7 @@ ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq) | |||
1952 | if (ret) { | 2073 | if (ret) { |
1953 | ATH5K_ERR(ah->ah_sc, | 2074 | ATH5K_ERR(ah->ah_sc, |
1954 | "noise floor calibration timeout (%uMHz)\n", freq); | 2075 | "noise floor calibration timeout (%uMHz)\n", freq); |
1955 | return ret; | 2076 | return -EAGAIN; |
1956 | } | 2077 | } |
1957 | 2078 | ||
1958 | /* Wait until the noise floor is calibrated and read the value */ | 2079 | /* Wait until the noise floor is calibrated and read the value */ |
@@ -1974,7 +2095,7 @@ ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq) | |||
1974 | if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { | 2095 | if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { |
1975 | ATH5K_ERR(ah->ah_sc, | 2096 | ATH5K_ERR(ah->ah_sc, |
1976 | "noise floor calibration failed (%uMHz)\n", freq); | 2097 | "noise floor calibration failed (%uMHz)\n", freq); |
1977 | return -EIO; | 2098 | return -EAGAIN; |
1978 | } | 2099 | } |
1979 | 2100 | ||
1980 | ah->ah_noise_floor = noise_floor; | 2101 | ah->ah_noise_floor = noise_floor; |
@@ -2087,38 +2208,66 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, | |||
2087 | } | 2208 | } |
2088 | 2209 | ||
2089 | /* | 2210 | /* |
2090 | * Perform a PHY calibration on RF5111/5112 | 2211 | * Perform a PHY calibration on RF5111/5112 and newer chips |
2091 | */ | 2212 | */ |
2092 | static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, | 2213 | static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah, |
2093 | struct ieee80211_channel *channel) | 2214 | struct ieee80211_channel *channel) |
2094 | { | 2215 | { |
2095 | u32 i_pwr, q_pwr; | 2216 | u32 i_pwr, q_pwr; |
2096 | s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; | 2217 | s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd; |
2218 | int i; | ||
2097 | ATH5K_TRACE(ah->ah_sc); | 2219 | ATH5K_TRACE(ah->ah_sc); |
2098 | 2220 | ||
2099 | if (!ah->ah_calibration || | 2221 | if (!ah->ah_calibration || |
2100 | ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) | 2222 | ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) |
2101 | goto done; | 2223 | goto done; |
2102 | 2224 | ||
2103 | ah->ah_calibration = false; | 2225 | /* Calibration has finished, get the results and re-run */ |
2226 | for (i = 0; i <= 10; i++) { | ||
2227 | iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); | ||
2228 | i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); | ||
2229 | q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); | ||
2230 | } | ||
2104 | 2231 | ||
2105 | iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); | ||
2106 | i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); | ||
2107 | q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); | ||
2108 | i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; | 2232 | i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7; |
2109 | q_coffd = q_pwr >> 6; | 2233 | q_coffd = q_pwr >> 7; |
2110 | 2234 | ||
2235 | /* No correction */ | ||
2111 | if (i_coffd == 0 || q_coffd == 0) | 2236 | if (i_coffd == 0 || q_coffd == 0) |
2112 | goto done; | 2237 | goto done; |
2113 | 2238 | ||
2114 | i_coff = ((-iq_corr) / i_coffd) & 0x3f; | 2239 | i_coff = ((-iq_corr) / i_coffd) & 0x3f; |
2115 | q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f; | ||
2116 | 2240 | ||
2117 | /* Commit new IQ value */ | 2241 | /* Boundary check */ |
2242 | if (i_coff > 31) | ||
2243 | i_coff = 31; | ||
2244 | if (i_coff < -32) | ||
2245 | i_coff = -32; | ||
2246 | |||
2247 | q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f; | ||
2248 | |||
2249 | /* Boundary check */ | ||
2250 | if (q_coff > 15) | ||
2251 | q_coff = 15; | ||
2252 | if (q_coff < -16) | ||
2253 | q_coff = -16; | ||
2254 | |||
2255 | /* Commit new I/Q value */ | ||
2118 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | | 2256 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE | |
2119 | ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); | 2257 | ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S)); |
2120 | 2258 | ||
2259 | /* Re-enable calibration -if we don't we'll commit | ||
2260 | * the same values again and again */ | ||
2261 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, | ||
2262 | AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); | ||
2263 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); | ||
2264 | |||
2121 | done: | 2265 | done: |
2266 | |||
2267 | /* TODO: Separate noise floor calibration from I/Q calibration | ||
2268 | * since noise floor calibration interrupts rx path while I/Q | ||
2269 | * calibration doesn't. We don't need to run noise floor calibration | ||
2270 | * as often as I/Q calibration.*/ | ||
2122 | ath5k_hw_noise_floor_calibration(ah, channel->center_freq); | 2271 | ath5k_hw_noise_floor_calibration(ah, channel->center_freq); |
2123 | 2272 | ||
2124 | /* Request RF gain */ | 2273 | /* Request RF gain */ |
diff --git a/drivers/net/wireless/ath5k/reg.h b/drivers/net/wireless/ath5k/reg.h index 30629b3e37c2..7562bf173d3e 100644 --- a/drivers/net/wireless/ath5k/reg.h +++ b/drivers/net/wireless/ath5k/reg.h | |||
@@ -53,7 +53,7 @@ | |||
53 | #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ | 53 | #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ |
54 | #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ | 54 | #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ |
55 | #define AR5K_CR_RXD 0x00000020 /* RX Disable */ | 55 | #define AR5K_CR_RXD 0x00000020 /* RX Disable */ |
56 | #define AR5K_CR_SWI 0x00000040 | 56 | #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */ |
57 | 57 | ||
58 | /* | 58 | /* |
59 | * RX Descriptor Pointer register | 59 | * RX Descriptor Pointer register |
@@ -65,19 +65,19 @@ | |||
65 | */ | 65 | */ |
66 | #define AR5K_CFG 0x0014 /* Register Address */ | 66 | #define AR5K_CFG 0x0014 /* Register Address */ |
67 | #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */ | 67 | #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */ |
68 | #define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer (?) */ | 68 | #define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */ |
69 | #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ | 69 | #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ |
70 | #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer (?) */ | 70 | #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */ |
71 | #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register values (?) */ | 71 | #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */ |
72 | #define AR5K_CFG_ADHOC 0x00000020 /* [5211+] */ | 72 | #define AR5K_CFG_ADHOC 0x00000020 /* AP/Adhoc indication [5211+] */ |
73 | #define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ | 73 | #define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ |
74 | #define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ | 74 | #define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ |
75 | #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (?) */ | 75 | #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */ |
76 | #define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */ | 76 | #define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */ |
77 | #define AR5K_CFG_TXCNT_S 11 | 77 | #define AR5K_CFG_TXCNT_S 11 |
78 | #define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ | 78 | #define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ |
79 | #define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ | 79 | #define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ |
80 | #define AR5K_CFG_PCI_THRES 0x00060000 /* [5211+] */ | 80 | #define AR5K_CFG_PCI_THRES 0x00060000 /* PCI Master req q threshold [5211+] */ |
81 | #define AR5K_CFG_PCI_THRES_S 17 | 81 | #define AR5K_CFG_PCI_THRES_S 17 |
82 | 82 | ||
83 | /* | 83 | /* |
@@ -162,35 +162,40 @@ | |||
162 | /* | 162 | /* |
163 | * Transmit configuration register | 163 | * Transmit configuration register |
164 | */ | 164 | */ |
165 | #define AR5K_TXCFG 0x0030 /* Register Address */ | 165 | #define AR5K_TXCFG 0x0030 /* Register Address */ |
166 | #define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size */ | 166 | #define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size (read) */ |
167 | #define AR5K_TXCFG_SDMAMR_S 0 | 167 | #define AR5K_TXCFG_SDMAMR_S 0 |
168 | #define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ | 168 | #define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ |
169 | #define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ | 169 | #define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ |
170 | #define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ | 170 | #define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ |
171 | #define AR5K_TXCFG_TXFULL_S 4 | 171 | #define AR5K_TXCFG_TXFULL_S 4 |
172 | #define AR5K_TXCFG_TXFULL_0B 0x00000000 | 172 | #define AR5K_TXCFG_TXFULL_0B 0x00000000 |
173 | #define AR5K_TXCFG_TXFULL_64B 0x00000010 | 173 | #define AR5K_TXCFG_TXFULL_64B 0x00000010 |
174 | #define AR5K_TXCFG_TXFULL_128B 0x00000020 | 174 | #define AR5K_TXCFG_TXFULL_128B 0x00000020 |
175 | #define AR5K_TXCFG_TXFULL_192B 0x00000030 | 175 | #define AR5K_TXCFG_TXFULL_192B 0x00000030 |
176 | #define AR5K_TXCFG_TXFULL_256B 0x00000040 | 176 | #define AR5K_TXCFG_TXFULL_256B 0x00000040 |
177 | #define AR5K_TXCFG_TXCONT_EN 0x00000080 | 177 | #define AR5K_TXCFG_TXCONT_EN 0x00000080 |
178 | #define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ | 178 | #define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ |
179 | #define AR5K_TXCFG_JUMBO_TXE 0x00000400 /* Enable jumbo frames transmition (?) [5211+] */ | 179 | #define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */ |
180 | #define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ | 180 | #define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 /* Adhoc Beacon ATIM Policy */ |
181 | #define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ | 181 | #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 /* Disable ATIM window defer [5211+] */ |
182 | #define AR5K_TXCFG_RDY_DIS 0x00004000 /* [5211+] */ | 182 | #define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ |
183 | #define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ | ||
184 | #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */ | ||
185 | #define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */ | ||
186 | #define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */ | ||
183 | 187 | ||
184 | /* | 188 | /* |
185 | * Receive configuration register | 189 | * Receive configuration register |
186 | */ | 190 | */ |
187 | #define AR5K_RXCFG 0x0034 /* Register Address */ | 191 | #define AR5K_RXCFG 0x0034 /* Register Address */ |
188 | #define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size */ | 192 | #define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size (write) */ |
189 | #define AR5K_RXCFG_SDMAMW_S 0 | 193 | #define AR5K_RXCFG_SDMAMW_S 0 |
190 | #define AR5K_RXCFG_DEF_ANTENNA 0x00000008 /* Default antenna */ | 194 | #define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */ |
191 | #define AR5K_RXCFG_ZLFDMA 0x00000010 /* Zero-length DMA */ | 195 | #define AR5K_RXCFG_DEF_ANTENNA 0x00000010 /* Default antenna (?) */ |
192 | #define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo frames reception (?) [5211+] */ | 196 | #define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo rx descriptors [5211+] */ |
193 | #define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames (?) [5211+] */ | 197 | #define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames [5211+] */ |
198 | #define AR5K_RXCFG_SLE_ENTRY 0x00000080 /* Sleep entry policy */ | ||
194 | 199 | ||
195 | /* | 200 | /* |
196 | * Receive jumbo descriptor last address register | 201 | * Receive jumbo descriptor last address register |
@@ -202,35 +207,35 @@ | |||
202 | * MIB control register | 207 | * MIB control register |
203 | */ | 208 | */ |
204 | #define AR5K_MIBC 0x0040 /* Register Address */ | 209 | #define AR5K_MIBC 0x0040 /* Register Address */ |
205 | #define AR5K_MIBC_COW 0x00000001 | 210 | #define AR5K_MIBC_COW 0x00000001 /* Warn test indicator */ |
206 | #define AR5K_MIBC_FMC 0x00000002 /* Freeze Mib Counters (?) */ | 211 | #define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */ |
207 | #define AR5K_MIBC_CMC 0x00000004 /* Clean Mib Counters (?) */ | 212 | #define AR5K_MIBC_CMC 0x00000004 /* Clean MIB Counters */ |
208 | #define AR5K_MIBC_MCS 0x00000008 | 213 | #define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe */ |
209 | 214 | ||
210 | /* | 215 | /* |
211 | * Timeout prescale register | 216 | * Timeout prescale register |
212 | */ | 217 | */ |
213 | #define AR5K_TOPS 0x0044 | 218 | #define AR5K_TOPS 0x0044 |
214 | #define AR5K_TOPS_M 0x0000ffff /* [5211+] (?) */ | 219 | #define AR5K_TOPS_M 0x0000ffff |
215 | 220 | ||
216 | /* | 221 | /* |
217 | * Receive timeout register (no frame received) | 222 | * Receive timeout register (no frame received) |
218 | */ | 223 | */ |
219 | #define AR5K_RXNOFRM 0x0048 | 224 | #define AR5K_RXNOFRM 0x0048 |
220 | #define AR5K_RXNOFRM_M 0x000003ff /* [5211+] (?) */ | 225 | #define AR5K_RXNOFRM_M 0x000003ff |
221 | 226 | ||
222 | /* | 227 | /* |
223 | * Transmit timeout register (no frame sent) | 228 | * Transmit timeout register (no frame sent) |
224 | */ | 229 | */ |
225 | #define AR5K_TXNOFRM 0x004c | 230 | #define AR5K_TXNOFRM 0x004c |
226 | #define AR5K_TXNOFRM_M 0x000003ff /* [5211+] (?) */ | 231 | #define AR5K_TXNOFRM_M 0x000003ff |
227 | #define AR5K_TXNOFRM_QCU 0x000ffc00 /* [5211+] (?) */ | 232 | #define AR5K_TXNOFRM_QCU 0x000ffc00 |
228 | 233 | ||
229 | /* | 234 | /* |
230 | * Receive frame gap timeout register | 235 | * Receive frame gap timeout register |
231 | */ | 236 | */ |
232 | #define AR5K_RPGTO 0x0050 | 237 | #define AR5K_RPGTO 0x0050 |
233 | #define AR5K_RPGTO_M 0x000003ff /* [5211+] (?) */ | 238 | #define AR5K_RPGTO_M 0x000003ff |
234 | 239 | ||
235 | /* | 240 | /* |
236 | * Receive frame count limit register | 241 | * Receive frame count limit register |
@@ -241,6 +246,7 @@ | |||
241 | 246 | ||
242 | /* | 247 | /* |
243 | * Misc settings register | 248 | * Misc settings register |
249 | * (reserved0-3) | ||
244 | */ | 250 | */ |
245 | #define AR5K_MISC 0x0058 /* Register Address */ | 251 | #define AR5K_MISC 0x0058 /* Register Address */ |
246 | #define AR5K_MISC_DMA_OBS_M 0x000001e0 | 252 | #define AR5K_MISC_DMA_OBS_M 0x000001e0 |
@@ -256,6 +262,7 @@ | |||
256 | 262 | ||
257 | /* | 263 | /* |
258 | * QCU/DCU clock gating register (5311) | 264 | * QCU/DCU clock gating register (5311) |
265 | * (reserved4-5) | ||
259 | */ | 266 | */ |
260 | #define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */ | 267 | #define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */ |
261 | #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */ | 268 | #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */ |
@@ -284,18 +291,18 @@ | |||
284 | #define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ | 291 | #define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ |
285 | #define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ | 292 | #define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ |
286 | #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ | 293 | #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ |
287 | #define AR5K_ISR_SWI 0x00002000 /* Software interrupt (?) */ | 294 | #define AR5K_ISR_SWI 0x00002000 /* Software interrupt */ |
288 | #define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ | 295 | #define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ |
289 | #define AR5K_ISR_RXKCM 0x00008000 | 296 | #define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */ |
290 | #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ | 297 | #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ |
291 | #define AR5K_ISR_BRSSI 0x00020000 | 298 | #define AR5K_ISR_BRSSI 0x00020000 |
292 | #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ | 299 | #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ |
293 | #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ | 300 | #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ |
294 | #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ | 301 | #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ |
295 | #define AR5K_ISR_MCABT 0x00100000 /* [5210] */ | 302 | #define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ |
296 | #define AR5K_ISR_RXCHIRP 0x00200000 /* [5212+] */ | 303 | #define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ |
297 | #define AR5K_ISR_SSERR 0x00200000 /* [5210] */ | 304 | #define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ |
298 | #define AR5K_ISR_DPERR 0x00400000 /* [5210] */ | 305 | #define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */ |
299 | #define AR5K_ISR_TIM 0x00800000 /* [5210] */ | 306 | #define AR5K_ISR_TIM 0x00800000 /* [5210] */ |
300 | #define AR5K_ISR_BCNMISC 0x00800000 /* [5212+] */ | 307 | #define AR5K_ISR_BCNMISC 0x00800000 /* [5212+] */ |
301 | #define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill)*/ | 308 | #define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill)*/ |
@@ -320,14 +327,14 @@ | |||
320 | 327 | ||
321 | #define AR5K_SISR2 0x008c /* Register Address [5211+] */ | 328 | #define AR5K_SISR2 0x008c /* Register Address [5211+] */ |
322 | #define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ | 329 | #define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ |
323 | #define AR5K_SISR2_MCABT 0x00100000 | 330 | #define AR5K_SISR2_MCABT 0x00100000 /* Master Cycle Abort */ |
324 | #define AR5K_SISR2_SSERR 0x00200000 | 331 | #define AR5K_SISR2_SSERR 0x00200000 /* Signaled System Error */ |
325 | #define AR5K_SISR2_DPERR 0x00400000 | 332 | #define AR5K_SISR2_DPERR 0x00400000 /* Det par Error (?) */ |
326 | #define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ | 333 | #define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ |
327 | #define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ | 334 | #define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ |
328 | #define AR5K_SISR2_DTIM_SYNC 0x04000000 /* [5212+] */ | 335 | #define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */ |
329 | #define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ | 336 | #define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ |
330 | #define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ | 337 | #define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ |
331 | #define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ | 338 | #define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ |
332 | 339 | ||
333 | #define AR5K_SISR3 0x0090 /* Register Address [5211+] */ | 340 | #define AR5K_SISR3 0x0090 /* Register Address [5211+] */ |
@@ -368,18 +375,18 @@ | |||
368 | #define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ | 375 | #define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ |
369 | #define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ | 376 | #define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ |
370 | #define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ | 377 | #define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ |
371 | #define AR5K_IMR_SWI 0x00002000 | 378 | #define AR5K_IMR_SWI 0x00002000 /* Software interrupt */ |
372 | #define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ | 379 | #define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ |
373 | #define AR5K_IMR_RXKCM 0x00008000 | 380 | #define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */ |
374 | #define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ | 381 | #define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ |
375 | #define AR5K_IMR_BRSSI 0x00020000 | 382 | #define AR5K_IMR_BRSSI 0x00020000 |
376 | #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ | 383 | #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ |
377 | #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ | 384 | #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ |
378 | #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ | 385 | #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ |
379 | #define AR5K_IMR_MCABT 0x00100000 /* [5210] */ | 386 | #define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ |
380 | #define AR5K_IMR_RXCHIRP 0x00200000 /* [5212+]*/ | 387 | #define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/ |
381 | #define AR5K_IMR_SSERR 0x00200000 /* [5210] */ | 388 | #define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */ |
382 | #define AR5K_IMR_DPERR 0x00400000 /* [5210] */ | 389 | #define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */ |
383 | #define AR5K_IMR_TIM 0x00800000 /* [5211+] */ | 390 | #define AR5K_IMR_TIM 0x00800000 /* [5211+] */ |
384 | #define AR5K_IMR_BCNMISC 0x00800000 /* [5212+] */ | 391 | #define AR5K_IMR_BCNMISC 0x00800000 /* [5212+] */ |
385 | #define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ | 392 | #define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ |
@@ -405,14 +412,14 @@ | |||
405 | #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ | 412 | #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ |
406 | #define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ | 413 | #define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ |
407 | #define AR5K_SIMR2_QCU_TXURN_S 0 | 414 | #define AR5K_SIMR2_QCU_TXURN_S 0 |
408 | #define AR5K_SIMR2_MCABT 0x00100000 | 415 | #define AR5K_SIMR2_MCABT 0x00100000 /* Master Cycle Abort */ |
409 | #define AR5K_SIMR2_SSERR 0x00200000 | 416 | #define AR5K_SIMR2_SSERR 0x00200000 /* Signaled System Error */ |
410 | #define AR5K_SIMR2_DPERR 0x00400000 | 417 | #define AR5K_SIMR2_DPERR 0x00400000 /* Det par Error (?) */ |
411 | #define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ | 418 | #define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ |
412 | #define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ | 419 | #define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ |
413 | #define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* [5212+] */ | 420 | #define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */ |
414 | #define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* [5212+] */ | 421 | #define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ |
415 | #define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* [5212+] */ | 422 | #define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ |
416 | #define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ | 423 | #define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ |
417 | 424 | ||
418 | #define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ | 425 | #define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ |
@@ -425,23 +432,69 @@ | |||
425 | #define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */ | 432 | #define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */ |
426 | #define AR5K_SIMR4_QTRIG_S 0 | 433 | #define AR5K_SIMR4_QTRIG_S 0 |
427 | 434 | ||
435 | /* | ||
436 | * DMA Debug registers 0-7 | ||
437 | * 0xe0 - 0xfc | ||
438 | */ | ||
428 | 439 | ||
429 | /* | 440 | /* |
430 | * Decompression mask registers [5212+] | 441 | * Decompression mask registers [5212+] |
431 | */ | 442 | */ |
432 | #define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (?)*/ | 443 | #define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (index) */ |
433 | #define AR5K_DCM_DATA 0x0404 /*Decompression mask data (?)*/ | 444 | #define AR5K_DCM_DATA 0x0404 /*Decompression mask data */ |
445 | |||
446 | /* | ||
447 | * Wake On Wireless pattern control register [5212+] | ||
448 | */ | ||
449 | #define AR5K_WOW_PCFG 0x0410 /* Register Address */ | ||
450 | #define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 /* Pattern match enable */ | ||
451 | #define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 /* Long frame policy */ | ||
452 | #define AR5K_WOW_PCFG_WOBMISS 0x00000004 /* Wake on bea(con) miss (?) */ | ||
453 | #define AR5K_WOW_PCFG_PAT_0_EN 0x00000100 /* Enable pattern 0 */ | ||
454 | #define AR5K_WOW_PCFG_PAT_1_EN 0x00000200 /* Enable pattern 1 */ | ||
455 | #define AR5K_WOW_PCFG_PAT_2_EN 0x00000400 /* Enable pattern 2 */ | ||
456 | #define AR5K_WOW_PCFG_PAT_3_EN 0x00000800 /* Enable pattern 3 */ | ||
457 | #define AR5K_WOW_PCFG_PAT_4_EN 0x00001000 /* Enable pattern 4 */ | ||
458 | #define AR5K_WOW_PCFG_PAT_5_EN 0x00002000 /* Enable pattern 5 */ | ||
459 | |||
460 | /* | ||
461 | * Wake On Wireless pattern index register (?) [5212+] | ||
462 | */ | ||
463 | #define AR5K_WOW_PAT_IDX 0x0414 | ||
464 | |||
465 | /* | ||
466 | * Wake On Wireless pattern data register [5212+] | ||
467 | */ | ||
468 | #define AR5K_WOW_PAT_DATA 0x0418 /* Register Address */ | ||
469 | #define AR5K_WOW_PAT_DATA_0_3_V 0x00000001 /* Pattern 0, 3 value */ | ||
470 | #define AR5K_WOW_PAT_DATA_1_4_V 0x00000100 /* Pattern 1, 4 value */ | ||
471 | #define AR5K_WOW_PAT_DATA_2_5_V 0x00010000 /* Pattern 2, 5 value */ | ||
472 | #define AR5K_WOW_PAT_DATA_0_3_M 0x01000000 /* Pattern 0, 3 mask */ | ||
473 | #define AR5K_WOW_PAT_DATA_1_4_M 0x04000000 /* Pattern 1, 4 mask */ | ||
474 | #define AR5K_WOW_PAT_DATA_2_5_M 0x10000000 /* Pattern 2, 5 mask */ | ||
434 | 475 | ||
435 | /* | 476 | /* |
436 | * Decompression configuration registers [5212+] | 477 | * Decompression configuration registers [5212+] |
437 | */ | 478 | */ |
438 | #define AR5K_DCCFG 0x0420 | 479 | #define AR5K_DCCFG 0x0420 /* Register Address */ |
480 | #define AR5K_DCCFG_GLOBAL_EN 0x00000001 /* Enable decompression on all queues */ | ||
481 | #define AR5K_DCCFG_BYPASS_EN 0x00000002 /* Bypass decompression */ | ||
482 | #define AR5K_DCCFG_BCAST_EN 0x00000004 /* Enable decompression for bcast frames */ | ||
483 | #define AR5K_DCCFG_MCAST_EN 0x00000008 /* Enable decompression for mcast frames */ | ||
439 | 484 | ||
440 | /* | 485 | /* |
441 | * Compression configuration registers [5212+] | 486 | * Compression configuration registers [5212+] |
442 | */ | 487 | */ |
443 | #define AR5K_CCFG 0x0600 | 488 | #define AR5K_CCFG 0x0600 /* Register Address */ |
444 | #define AR5K_CCFG_CUP 0x0604 | 489 | #define AR5K_CCFG_WINDOW_SIZE 0x00000007 /* Compression window size */ |
490 | #define AR5K_CCFG_CPC_EN 0x00000008 /* Enable performance counters */ | ||
491 | |||
492 | #define AR5K_CCFG_CCU 0x0604 /* Register Address */ | ||
493 | #define AR5K_CCFG_CCU_CUP_EN 0x00000001 /* CCU Catchup enable */ | ||
494 | #define AR5K_CCFG_CCU_CREDIT 0x00000002 /* CCU Credit (field) */ | ||
495 | #define AR5K_CCFG_CCU_CD_THRES 0x00000080 /* CCU Cyc(lic?) debt threshold (field) */ | ||
496 | #define AR5K_CCFG_CCU_CUP_LCNT 0x00010000 /* CCU Catchup lit(?) count */ | ||
497 | #define AR5K_CCFG_CCU_INIT 0x00100200 /* Initial value during reset */ | ||
445 | 498 | ||
446 | /* | 499 | /* |
447 | * Compression performance counter registers [5212+] | 500 | * Compression performance counter registers [5212+] |
@@ -450,7 +503,7 @@ | |||
450 | #define AR5K_CPC1 0x0614 /* Compression performance counter 1*/ | 503 | #define AR5K_CPC1 0x0614 /* Compression performance counter 1*/ |
451 | #define AR5K_CPC2 0x0618 /* Compression performance counter 2 */ | 504 | #define AR5K_CPC2 0x0618 /* Compression performance counter 2 */ |
452 | #define AR5K_CPC3 0x061c /* Compression performance counter 3 */ | 505 | #define AR5K_CPC3 0x061c /* Compression performance counter 3 */ |
453 | #define AR5K_CPCORN 0x0620 /* Compression performance overrun (?) */ | 506 | #define AR5K_CPCOVF 0x0620 /* Compression performance overflow */ |
454 | 507 | ||
455 | 508 | ||
456 | /* | 509 | /* |
@@ -466,8 +519,6 @@ | |||
466 | * set/clear, which contain status for all queues (we shift by 1 for each | 519 | * set/clear, which contain status for all queues (we shift by 1 for each |
467 | * queue). To access these registers easily we define some macros here | 520 | * queue). To access these registers easily we define some macros here |
468 | * that are used inside HAL. For more infos check out *_tx_queue functs. | 521 | * that are used inside HAL. For more infos check out *_tx_queue functs. |
469 | * | ||
470 | * TODO: Boundary checking on macros (here?) | ||
471 | */ | 522 | */ |
472 | 523 | ||
473 | /* | 524 | /* |
@@ -513,7 +564,6 @@ | |||
513 | #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */ | 564 | #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */ |
514 | #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */ | 565 | #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */ |
515 | #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 | 566 | #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 |
516 | #define AR5K_QCU_RDYTIMECFG_DURATION 0x00ffffff /* Ready time duration mask */ | ||
517 | #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */ | 567 | #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */ |
518 | #define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) | 568 | #define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) |
519 | 569 | ||
@@ -534,19 +584,20 @@ | |||
534 | */ | 584 | */ |
535 | #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ | 585 | #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ |
536 | #define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ | 586 | #define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ |
537 | #define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ | 587 | #define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ |
538 | #define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ | 588 | #define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ |
539 | #define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated (?) */ | 589 | #define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated (?) */ |
540 | #define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* Time gated (?) */ | 590 | #define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* Time gated (?) */ |
541 | #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated (?) */ | 591 | #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated (?) */ |
542 | #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ | 592 | #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ |
543 | #define AR5K_QCU_MISC_CBREXP 0x00000020 /* CBR expired (normal queue) */ | 593 | #define AR5K_QCU_MISC_CBREXP 0x00000020 /* CBR expired (normal queue) */ |
544 | #define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /* CBR expired (beacon queue) */ | 594 | #define AR5K_QCU_MISC_CBREXP_BCN 0x00000040 /* CBR expired (beacon queue) */ |
545 | #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Beacons enabled */ | 595 | #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */ |
546 | #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR threshold enabled (?) */ | 596 | #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR threshold enabled */ |
547 | #define AR5K_QCU_MISC_TXE 0x00000200 /* TXE reset when RDYTIME enalbed (?) */ | 597 | #define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME enalbed */ |
548 | #define AR5K_QCU_MISC_CBR 0x00000400 /* CBR threshold reset (?) */ | 598 | #define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */ |
549 | #define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU reset (?) */ | 599 | #define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */ |
600 | #define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */ | ||
550 | #define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) | 601 | #define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) |
551 | 602 | ||
552 | 603 | ||
@@ -555,7 +606,7 @@ | |||
555 | */ | 606 | */ |
556 | #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */ | 607 | #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */ |
557 | #define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */ | 608 | #define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */ |
558 | #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter (?) */ | 609 | #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter */ |
559 | #define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) | 610 | #define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) |
560 | 611 | ||
561 | /* | 612 | /* |
@@ -569,9 +620,11 @@ | |||
569 | */ | 620 | */ |
570 | #define AR5K_QCU_CBB_SELECT 0x0b00 | 621 | #define AR5K_QCU_CBB_SELECT 0x0b00 |
571 | #define AR5K_QCU_CBB_ADDR 0x0b04 | 622 | #define AR5K_QCU_CBB_ADDR 0x0b04 |
623 | #define AR5K_QCU_CBB_ADDR_S 9 | ||
572 | 624 | ||
573 | /* | 625 | /* |
574 | * QCU compression buffer configuration register [5212+] | 626 | * QCU compression buffer configuration register [5212+] |
627 | * (buffer size) | ||
575 | */ | 628 | */ |
576 | #define AR5K_QCU_CBCFG 0x0b08 | 629 | #define AR5K_QCU_CBCFG 0x0b08 |
577 | 630 | ||
@@ -652,80 +705,100 @@ | |||
652 | * No lockout means there is no special handling. | 705 | * No lockout means there is no special handling. |
653 | */ | 706 | */ |
654 | #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ | 707 | #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ |
655 | #define AR5K_DCU_MISC_BACKOFF 0x000007ff /* Mask for backoff setting (?) */ | 708 | #define AR5K_DCU_MISC_BACKOFF 0x000007ff /* Mask for backoff threshold */ |
656 | #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ | 709 | #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ |
657 | #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll (?) */ | 710 | #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */ |
658 | #define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff (?) */ | 711 | #define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */ |
659 | #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch (?) */ | 712 | #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */ |
660 | #define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ | 713 | #define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ |
661 | #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 | 714 | #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 |
662 | #define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1 | 715 | #define AR5K_DCU_MISC_VIRTCOL_MODIFIED 1 |
663 | #define AR5K_DCU_MISC_VIRTCOL_IGNORE 2 | 716 | #define AR5K_DCU_MISC_VIRTCOL_IGNORE 2 |
664 | #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Beacon enable (?) */ | 717 | #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */ |
665 | #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ | 718 | #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ |
666 | #define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 | 719 | #define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 |
667 | #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ | 720 | #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ |
668 | #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ | 721 | #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ |
669 | #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ | 722 | #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ |
670 | #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 | 723 | #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 /* Ignore Arbiter lockout */ |
671 | #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment (?) */ | 724 | #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment */ |
672 | #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff (?) */ | 725 | #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */ |
673 | #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision policy (?) */ | 726 | #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision cw policy */ |
674 | #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 | 727 | #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS policy (?) */ |
675 | #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ | 728 | #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ |
676 | #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) | 729 | #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) |
677 | 730 | ||
678 | /* | 731 | /* |
679 | * DCU frame sequence number registers | 732 | * DCU frame sequence number registers |
680 | */ | 733 | */ |
681 | #define AR5K_DCU_SEQNUM_BASE 0x1140 | 734 | #define AR5K_DCU_SEQNUM_BASE 0x1140 |
682 | #define AR5K_DCU_SEQNUM_M 0x00000fff | 735 | #define AR5K_DCU_SEQNUM_M 0x00000fff |
683 | #define AR5K_QUEUE_DFS_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) | 736 | #define AR5K_QUEUE_DFS_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) |
684 | 737 | ||
685 | /* | 738 | /* |
686 | * DCU global IFS SIFS registers | 739 | * DCU global IFS SIFS register |
687 | */ | 740 | */ |
688 | #define AR5K_DCU_GBL_IFS_SIFS 0x1030 | 741 | #define AR5K_DCU_GBL_IFS_SIFS 0x1030 |
689 | #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff | 742 | #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff |
690 | 743 | ||
691 | /* | 744 | /* |
692 | * DCU global IFS slot interval registers | 745 | * DCU global IFS slot interval register |
693 | */ | 746 | */ |
694 | #define AR5K_DCU_GBL_IFS_SLOT 0x1070 | 747 | #define AR5K_DCU_GBL_IFS_SLOT 0x1070 |
695 | #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff | 748 | #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff |
696 | 749 | ||
697 | /* | 750 | /* |
698 | * DCU global IFS EIFS registers | 751 | * DCU global IFS EIFS register |
699 | */ | 752 | */ |
700 | #define AR5K_DCU_GBL_IFS_EIFS 0x10b0 | 753 | #define AR5K_DCU_GBL_IFS_EIFS 0x10b0 |
701 | #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff | 754 | #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff |
702 | 755 | ||
703 | /* | 756 | /* |
704 | * DCU global IFS misc registers | 757 | * DCU global IFS misc register |
758 | * | ||
759 | * LFSR stands for Linear Feedback Shift Register | ||
760 | * and it's used for generating pseudo-random | ||
761 | * number sequences. | ||
762 | * | ||
763 | * (If i understand corectly, random numbers are | ||
764 | * used for idle sensing -multiplied with cwmin/max etc-) | ||
705 | */ | 765 | */ |
706 | #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ | 766 | #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ |
707 | #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 | 767 | #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 /* LFSR Slice Select */ |
708 | #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode (?) */ | 768 | #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */ |
709 | #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask (?) */ | 769 | #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */ |
710 | #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 | 770 | #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */ |
711 | #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 | 771 | #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */ |
772 | #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFC cnt reset policy (?) */ | ||
773 | #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */ | ||
774 | #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */ | ||
712 | 775 | ||
713 | /* | 776 | /* |
714 | * DCU frame prefetch control register | 777 | * DCU frame prefetch control register |
715 | */ | 778 | */ |
716 | #define AR5K_DCU_FP 0x1230 | 779 | #define AR5K_DCU_FP 0x1230 /* Register Address */ |
780 | #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */ | ||
781 | #define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */ | ||
782 | #define AR5K_DCU_FP_BURST_DCU_EN 0x00000020 /* Enable burst prefetch on DCU (?) */ | ||
717 | 783 | ||
718 | /* | 784 | /* |
719 | * DCU transmit pause control/status register | 785 | * DCU transmit pause control/status register |
720 | */ | 786 | */ |
721 | #define AR5K_DCU_TXP 0x1270 /* Register Address */ | 787 | #define AR5K_DCU_TXP 0x1270 /* Register Address */ |
722 | #define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask (?) */ | 788 | #define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */ |
723 | #define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status (?) */ | 789 | #define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status */ |
790 | |||
791 | /* | ||
792 | * DCU transmit filter table 0 (32 entries) | ||
793 | */ | ||
794 | #define AR5K_DCU_TX_FILTER_0_BASE 0x1038 | ||
795 | #define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64)) | ||
724 | 796 | ||
725 | /* | 797 | /* |
726 | * DCU transmit filter register | 798 | * DCU transmit filter table 1 (16 entries) |
727 | */ | 799 | */ |
728 | #define AR5K_DCU_TX_FILTER 0x1038 | 800 | #define AR5K_DCU_TX_FILTER_1_BASE 0x103c |
801 | #define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + ((_n - 32) * 64)) | ||
729 | 802 | ||
730 | /* | 803 | /* |
731 | * DCU clear transmit filter register | 804 | * DCU clear transmit filter register |
@@ -739,9 +812,6 @@ | |||
739 | 812 | ||
740 | /* | 813 | /* |
741 | * Reset control register | 814 | * Reset control register |
742 | * | ||
743 | * 4 and 8 are not used in 5211/5212 and | ||
744 | * 2 means "baseband reset" on 5211/5212. | ||
745 | */ | 815 | */ |
746 | #define AR5K_RESET_CTL 0x4000 /* Register Address */ | 816 | #define AR5K_RESET_CTL 0x4000 /* Register Address */ |
747 | #define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */ | 817 | #define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */ |
@@ -765,6 +835,7 @@ | |||
765 | #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ | 835 | #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ |
766 | #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 | 836 | #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 |
767 | #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ | 837 | #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ |
838 | /* more bits */ | ||
768 | 839 | ||
769 | /* | 840 | /* |
770 | * Interrupt pending register | 841 | * Interrupt pending register |
@@ -776,13 +847,14 @@ | |||
776 | * Sleep force register | 847 | * Sleep force register |
777 | */ | 848 | */ |
778 | #define AR5K_SFR 0x400c | 849 | #define AR5K_SFR 0x400c |
779 | #define AR5K_SFR_M 0x00000001 | 850 | #define AR5K_SFR_EN 0x00000001 |
780 | 851 | ||
781 | /* | 852 | /* |
782 | * PCI configuration register | 853 | * PCI configuration register |
783 | */ | 854 | */ |
784 | #define AR5K_PCICFG 0x4010 /* Register Address */ | 855 | #define AR5K_PCICFG 0x4010 /* Register Address */ |
785 | #define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ | 856 | #define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ |
857 | #define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock (?) */ | ||
786 | #define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ | 858 | #define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ |
787 | #define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ | 859 | #define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ |
788 | #define AR5K_PCICFG_EESIZE_S 3 | 860 | #define AR5K_PCICFG_EESIZE_S 3 |
@@ -798,19 +870,21 @@ | |||
798 | #define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix (?) */ | 870 | #define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix (?) */ |
799 | #define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep (?) */ | 871 | #define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep (?) */ |
800 | #define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ | 872 | #define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ |
801 | #define AR5K_PCICFG_SL_INPEN 0x00002800 /* Sleep even whith pending interrupts (?) */ | 873 | #define AR5K_PCICFG_UNK 0x00001000 /* Passed on some parts durring attach (?) */ |
874 | #define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even whith pending interrupts (?) */ | ||
802 | #define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ | 875 | #define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ |
803 | #define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ | 876 | #define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ |
804 | #define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ | 877 | #define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ |
805 | #define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ | 878 | #define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ |
806 | #define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ | 879 | #define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ |
807 | #define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ | 880 | #define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ |
808 | #define AR5K_PCICFG_LEDBLINK 0x00700000 | 881 | #define AR5K_PCICFG_LEDBLINK 0x00700000 /* Led blink rate */ |
809 | #define AR5K_PCICFG_LEDBLINK_S 20 | 882 | #define AR5K_PCICFG_LEDBLINK_S 20 |
810 | #define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slow led blink rate (?) [5211+] */ | 883 | #define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slowest led blink rate [5211+] */ |
811 | #define AR5K_PCICFG_LEDSTATE \ | 884 | #define AR5K_PCICFG_LEDSTATE \ |
812 | (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ | 885 | (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ |
813 | AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) | 886 | AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) |
887 | #define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate (field) */ | ||
814 | 888 | ||
815 | /* | 889 | /* |
816 | * "General Purpose Input/Output" (GPIO) control register | 890 | * "General Purpose Input/Output" (GPIO) control register |
@@ -947,7 +1021,7 @@ | |||
947 | #define AR5K_EEPROM_VERSION_4_4 0x4004 | 1021 | #define AR5K_EEPROM_VERSION_4_4 0x4004 |
948 | #define AR5K_EEPROM_VERSION_4_5 0x4005 | 1022 | #define AR5K_EEPROM_VERSION_4_5 0x4005 |
949 | #define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */ | 1023 | #define AR5K_EEPROM_VERSION_4_6 0x4006 /* has ee_scaled_cck_delta */ |
950 | #define AR5K_EEPROM_VERSION_4_7 0x3007 | 1024 | #define AR5K_EEPROM_VERSION_4_7 0x4007 |
951 | 1025 | ||
952 | #define AR5K_EEPROM_MODE_11A 0 | 1026 | #define AR5K_EEPROM_MODE_11A 0 |
953 | #define AR5K_EEPROM_MODE_11B 1 | 1027 | #define AR5K_EEPROM_MODE_11B 1 |
@@ -1023,10 +1097,14 @@ | |||
1023 | #define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */ | 1097 | #define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */ |
1024 | 1098 | ||
1025 | /* | 1099 | /* |
1026 | * EEPROM config register (?) | 1100 | * EEPROM config register |
1027 | */ | 1101 | */ |
1028 | #define AR5K_EEPROM_CFG 0x6010 | 1102 | #define AR5K_EEPROM_CFG 0x6010 /* Register Addres */ |
1029 | 1103 | #define AR5K_EEPROM_CFG_SIZE_OVR 0x00000001 | |
1104 | #define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */ | ||
1105 | #define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */ | ||
1106 | #define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protectio key */ | ||
1107 | #define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */ | ||
1030 | 1108 | ||
1031 | 1109 | ||
1032 | /* | 1110 | /* |
@@ -1050,7 +1128,7 @@ | |||
1050 | #define AR5K_STA_ID1 0x8004 /* Register Address */ | 1128 | #define AR5K_STA_ID1 0x8004 /* Register Address */ |
1051 | #define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */ | 1129 | #define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */ |
1052 | #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */ | 1130 | #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */ |
1053 | #define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting (?) */ | 1131 | #define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting */ |
1054 | #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */ | 1132 | #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */ |
1055 | #define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */ | 1133 | #define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */ |
1056 | #define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */ | 1134 | #define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */ |
@@ -1059,9 +1137,13 @@ | |||
1059 | AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) | 1137 | AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) |
1060 | #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ | 1138 | #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ |
1061 | #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ | 1139 | #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ |
1062 | #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS (?) */ | 1140 | #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */ |
1063 | #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS (?) */ | 1141 | #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS */ |
1064 | #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */ | 1142 | #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate (for ACK/CTS ?) [5211+] */ |
1143 | #define AR5K_STA_ID1_SELF_GEN_SECTORE 0x04000000 /* Self generate sectore (?) */ | ||
1144 | #define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */ | ||
1145 | #define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Keysearch mode (?) */ | ||
1146 | #define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */ | ||
1065 | 1147 | ||
1066 | /* | 1148 | /* |
1067 | * First BSSID register (MAC address, lower 32bits) | 1149 | * First BSSID register (MAC address, lower 32bits) |
@@ -1117,7 +1199,7 @@ | |||
1117 | * | 1199 | * |
1118 | * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) | 1200 | * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) |
1119 | */ | 1201 | */ |
1120 | #define AR5K_NODCU_RETRY_LMT 0x801c /*Register Address */ | 1202 | #define AR5K_NODCU_RETRY_LMT 0x801c /* Register Address */ |
1121 | #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ | 1203 | #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ |
1122 | #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 | 1204 | #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 |
1123 | #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */ | 1205 | #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */ |
@@ -1136,9 +1218,9 @@ | |||
1136 | #define AR5K_USEC_5211 0x801c /* Register Address [5211+] */ | 1218 | #define AR5K_USEC_5211 0x801c /* Register Address [5211+] */ |
1137 | #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \ | 1219 | #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \ |
1138 | AR5K_USEC_5210 : AR5K_USEC_5211) | 1220 | AR5K_USEC_5210 : AR5K_USEC_5211) |
1139 | #define AR5K_USEC_1 0x0000007f | 1221 | #define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */ |
1140 | #define AR5K_USEC_1_S 0 | 1222 | #define AR5K_USEC_1_S 0 |
1141 | #define AR5K_USEC_32 0x00003f80 | 1223 | #define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32Mhz clock */ |
1142 | #define AR5K_USEC_32_S 7 | 1224 | #define AR5K_USEC_32_S 7 |
1143 | #define AR5K_USEC_TX_LATENCY_5211 0x007fc000 | 1225 | #define AR5K_USEC_TX_LATENCY_5211 0x007fc000 |
1144 | #define AR5K_USEC_TX_LATENCY_5211_S 14 | 1226 | #define AR5K_USEC_TX_LATENCY_5211_S 14 |
@@ -1152,16 +1234,16 @@ | |||
1152 | /* | 1234 | /* |
1153 | * PCU beacon control register | 1235 | * PCU beacon control register |
1154 | */ | 1236 | */ |
1155 | #define AR5K_BEACON_5210 0x8024 | 1237 | #define AR5K_BEACON_5210 0x8024 /*Register Address [5210] */ |
1156 | #define AR5K_BEACON_5211 0x8020 | 1238 | #define AR5K_BEACON_5211 0x8020 /*Register Address [5211+] */ |
1157 | #define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \ | 1239 | #define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \ |
1158 | AR5K_BEACON_5210 : AR5K_BEACON_5211) | 1240 | AR5K_BEACON_5210 : AR5K_BEACON_5211) |
1159 | #define AR5K_BEACON_PERIOD 0x0000ffff | 1241 | #define AR5K_BEACON_PERIOD 0x0000ffff /* Mask for beacon period */ |
1160 | #define AR5K_BEACON_PERIOD_S 0 | 1242 | #define AR5K_BEACON_PERIOD_S 0 |
1161 | #define AR5K_BEACON_TIM 0x007f0000 | 1243 | #define AR5K_BEACON_TIM 0x007f0000 /* Mask for TIM offset */ |
1162 | #define AR5K_BEACON_TIM_S 16 | 1244 | #define AR5K_BEACON_TIM_S 16 |
1163 | #define AR5K_BEACON_ENABLE 0x00800000 | 1245 | #define AR5K_BEACON_ENABLE 0x00800000 /* Enable beacons */ |
1164 | #define AR5K_BEACON_RESET_TSF 0x01000000 | 1246 | #define AR5K_BEACON_RESET_TSF 0x01000000 /* Force TSF reset */ |
1165 | 1247 | ||
1166 | /* | 1248 | /* |
1167 | * CFP period register | 1249 | * CFP period register |
@@ -1234,7 +1316,6 @@ | |||
1234 | 1316 | ||
1235 | /* | 1317 | /* |
1236 | * Receive filter register | 1318 | * Receive filter register |
1237 | * TODO: Get these out of ar5xxx.h on ath5k | ||
1238 | */ | 1319 | */ |
1239 | #define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ | 1320 | #define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ |
1240 | #define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ | 1321 | #define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ |
@@ -1307,11 +1388,11 @@ | |||
1307 | #define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ | 1388 | #define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ |
1308 | #define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \ | 1389 | #define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \ |
1309 | AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) | 1390 | AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) |
1310 | #define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 | 1391 | #define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 /* Disable ACKs if WEP key is invalid */ |
1311 | #define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs (?) */ | 1392 | #define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs */ |
1312 | #define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs (?) */ | 1393 | #define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs */ |
1313 | #define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption (?) */ | 1394 | #define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption */ |
1314 | #define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption (?) */ | 1395 | #define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption */ |
1315 | #define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */ | 1396 | #define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */ |
1316 | #define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */ | 1397 | #define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */ |
1317 | #define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 | 1398 | #define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 |
@@ -1329,13 +1410,13 @@ | |||
1329 | #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 | 1410 | #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 |
1330 | #define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ | 1411 | #define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ |
1331 | AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) | 1412 | AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) |
1332 | #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /* Scrambler seed (?) */ | 1413 | #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 /* Enable scrambler seed */ |
1333 | #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 | 1414 | #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 |
1334 | #define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ | 1415 | #define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ |
1335 | AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) | 1416 | AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) |
1336 | #define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ | 1417 | #define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ |
1337 | #define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ | 1418 | #define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ |
1338 | #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask (?) */ | 1419 | #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */ |
1339 | #define AR5K_DIAG_SW_SCRAM_SEED_S 10 | 1420 | #define AR5K_DIAG_SW_SCRAM_SEED_S 10 |
1340 | #define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ | 1421 | #define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ |
1341 | #define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 | 1422 | #define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 |
@@ -1344,6 +1425,7 @@ | |||
1344 | AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) | 1425 | AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) |
1345 | #define AR5K_DIAG_SW_OBSPT_M 0x000c0000 | 1426 | #define AR5K_DIAG_SW_OBSPT_M 0x000c0000 |
1346 | #define AR5K_DIAG_SW_OBSPT_S 18 | 1427 | #define AR5K_DIAG_SW_OBSPT_S 18 |
1428 | /* more bits */ | ||
1347 | 1429 | ||
1348 | /* | 1430 | /* |
1349 | * TSF (clock) register (lower 32 bits) | 1431 | * TSF (clock) register (lower 32 bits) |
@@ -1369,15 +1451,34 @@ | |||
1369 | /* | 1451 | /* |
1370 | * ADDAC test register [5211+] | 1452 | * ADDAC test register [5211+] |
1371 | */ | 1453 | */ |
1372 | #define AR5K_ADDAC_TEST 0x8054 | 1454 | #define AR5K_ADDAC_TEST 0x8054 /* Register Address */ |
1373 | #define AR5K_ADDAC_TEST_TXCONT 0x00000001 | 1455 | #define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */ |
1456 | #define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */ | ||
1457 | #define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */ | ||
1458 | #define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */ | ||
1459 | #define AR5K_ADDAC_TEST_USE_U8 0x00004000 /* Use upper 8 bits */ | ||
1460 | #define AR5K_ADDAC_TEST_MSB 0x00008000 /* State of MSB */ | ||
1461 | #define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000 /* Trigger select */ | ||
1462 | #define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */ | ||
1463 | #define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */ | ||
1464 | #define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */ | ||
1465 | #define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* Test ARM (Adaptive Radio Mode ?) */ | ||
1374 | 1466 | ||
1375 | /* | 1467 | /* |
1376 | * Default antenna register [5211+] | 1468 | * Default antenna register [5211+] |
1377 | */ | 1469 | */ |
1378 | #define AR5K_DEFAULT_ANTENNA 0x8058 | 1470 | #define AR5K_DEFAULT_ANTENNA 0x8058 |
1379 | 1471 | ||
1472 | /* | ||
1473 | * Frame control QoS mask register (?) [5211+] | ||
1474 | * (FC_QOS_MASK) | ||
1475 | */ | ||
1476 | #define AR5K_FRAME_CTL_QOSM 0x805c | ||
1380 | 1477 | ||
1478 | /* | ||
1479 | * Seq mask register (?) [5211+] | ||
1480 | */ | ||
1481 | #define AR5K_SEQ_MASK 0x8060 | ||
1381 | 1482 | ||
1382 | /* | 1483 | /* |
1383 | * Retry count register [5210] | 1484 | * Retry count register [5210] |
@@ -1449,124 +1550,242 @@ | |||
1449 | /* | 1550 | /* |
1450 | * XR (eXtended Range) mode register | 1551 | * XR (eXtended Range) mode register |
1451 | */ | 1552 | */ |
1452 | #define AR5K_XRMODE 0x80c0 | 1553 | #define AR5K_XRMODE 0x80c0 /* Register Address */ |
1453 | #define AR5K_XRMODE_POLL_TYPE_M 0x0000003f | 1554 | #define AR5K_XRMODE_POLL_TYPE_M 0x0000003f /* Mask for Poll type (?) */ |
1454 | #define AR5K_XRMODE_POLL_TYPE_S 0 | 1555 | #define AR5K_XRMODE_POLL_TYPE_S 0 |
1455 | #define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c | 1556 | #define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c /* Mask for Poll subtype (?) */ |
1456 | #define AR5K_XRMODE_POLL_SUBTYPE_S 2 | 1557 | #define AR5K_XRMODE_POLL_SUBTYPE_S 2 |
1457 | #define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 | 1558 | #define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 /* Wait for poll */ |
1458 | #define AR5K_XRMODE_SIFS_DELAY 0x000fff00 | 1559 | #define AR5K_XRMODE_SIFS_DELAY 0x000fff00 /* Mask for SIFS delay */ |
1459 | #define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 | 1560 | #define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 /* Mask for frame hold (?) */ |
1460 | #define AR5K_XRMODE_FRAME_HOLD_S 20 | 1561 | #define AR5K_XRMODE_FRAME_HOLD_S 20 |
1461 | 1562 | ||
1462 | /* | 1563 | /* |
1463 | * XR delay register | 1564 | * XR delay register |
1464 | */ | 1565 | */ |
1465 | #define AR5K_XRDELAY 0x80c4 | 1566 | #define AR5K_XRDELAY 0x80c4 /* Register Address */ |
1466 | #define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff | 1567 | #define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff /* Mask for slot delay */ |
1467 | #define AR5K_XRDELAY_SLOT_DELAY_S 0 | 1568 | #define AR5K_XRDELAY_SLOT_DELAY_S 0 |
1468 | #define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 | 1569 | #define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 /* Mask for CHIRP data delay */ |
1469 | #define AR5K_XRDELAY_CHIRP_DELAY_S 16 | 1570 | #define AR5K_XRDELAY_CHIRP_DELAY_S 16 |
1470 | 1571 | ||
1471 | /* | 1572 | /* |
1472 | * XR timeout register | 1573 | * XR timeout register |
1473 | */ | 1574 | */ |
1474 | #define AR5K_XRTIMEOUT 0x80c8 | 1575 | #define AR5K_XRTIMEOUT 0x80c8 /* Register Address */ |
1475 | #define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff | 1576 | #define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff /* Mask for CHIRP timeout */ |
1476 | #define AR5K_XRTIMEOUT_CHIRP_S 0 | 1577 | #define AR5K_XRTIMEOUT_CHIRP_S 0 |
1477 | #define AR5K_XRTIMEOUT_POLL_M 0xffff0000 | 1578 | #define AR5K_XRTIMEOUT_POLL_M 0xffff0000 /* Mask for Poll timeout */ |
1478 | #define AR5K_XRTIMEOUT_POLL_S 16 | 1579 | #define AR5K_XRTIMEOUT_POLL_S 16 |
1479 | 1580 | ||
1480 | /* | 1581 | /* |
1481 | * XR chirp register | 1582 | * XR chirp register |
1482 | */ | 1583 | */ |
1483 | #define AR5K_XRCHIRP 0x80cc | 1584 | #define AR5K_XRCHIRP 0x80cc /* Register Address */ |
1484 | #define AR5K_XRCHIRP_SEND 0x00000001 | 1585 | #define AR5K_XRCHIRP_SEND 0x00000001 /* Send CHIRP */ |
1485 | #define AR5K_XRCHIRP_GAP 0xffff0000 | 1586 | #define AR5K_XRCHIRP_GAP 0xffff0000 /* Mask for CHIRP gap (?) */ |
1486 | 1587 | ||
1487 | /* | 1588 | /* |
1488 | * XR stomp register | 1589 | * XR stomp register |
1489 | */ | 1590 | */ |
1490 | #define AR5K_XRSTOMP 0x80d0 | 1591 | #define AR5K_XRSTOMP 0x80d0 /* Register Address */ |
1491 | #define AR5K_XRSTOMP_TX 0x00000001 | 1592 | #define AR5K_XRSTOMP_TX 0x00000001 /* Stomp Tx (?) */ |
1492 | #define AR5K_XRSTOMP_RX_ABORT 0x00000002 | 1593 | #define AR5K_XRSTOMP_RX 0x00000002 /* Stomp Rx (?) */ |
1493 | #define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 | 1594 | #define AR5K_XRSTOMP_TX_RSSI 0x00000004 /* Stomp Tx RSSI (?) */ |
1595 | #define AR5K_XRSTOMP_TX_BSSID 0x00000008 /* Stomp Tx BSSID (?) */ | ||
1596 | #define AR5K_XRSTOMP_DATA 0x00000010 /* Stomp data (?)*/ | ||
1597 | #define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 /* Mask for XR RSSI threshold */ | ||
1494 | 1598 | ||
1495 | /* | 1599 | /* |
1496 | * First enhanced sleep register | 1600 | * First enhanced sleep register |
1497 | */ | 1601 | */ |
1498 | #define AR5K_SLEEP0 0x80d4 | 1602 | #define AR5K_SLEEP0 0x80d4 /* Register Address */ |
1499 | #define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff | 1603 | #define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff /* Mask for next DTIM (?) */ |
1500 | #define AR5K_SLEEP0_NEXT_DTIM_S 0 | 1604 | #define AR5K_SLEEP0_NEXT_DTIM_S 0 |
1501 | #define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 | 1605 | #define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 /* Assume DTIM */ |
1502 | #define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 | 1606 | #define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 /* Enable enchanced sleep control */ |
1503 | #define AR5K_SLEEP0_CABTO 0xff000000 | 1607 | #define AR5K_SLEEP0_CABTO 0xff000000 /* Mask for CAB Time Out */ |
1504 | #define AR5K_SLEEP0_CABTO_S 24 | 1608 | #define AR5K_SLEEP0_CABTO_S 24 |
1505 | 1609 | ||
1506 | /* | 1610 | /* |
1507 | * Second enhanced sleep register | 1611 | * Second enhanced sleep register |
1508 | */ | 1612 | */ |
1509 | #define AR5K_SLEEP1 0x80d8 | 1613 | #define AR5K_SLEEP1 0x80d8 /* Register Address */ |
1510 | #define AR5K_SLEEP1_NEXT_TIM 0x0007ffff | 1614 | #define AR5K_SLEEP1_NEXT_TIM 0x0007ffff /* Mask for next TIM (?) */ |
1511 | #define AR5K_SLEEP1_NEXT_TIM_S 0 | 1615 | #define AR5K_SLEEP1_NEXT_TIM_S 0 |
1512 | #define AR5K_SLEEP1_BEACON_TO 0xff000000 | 1616 | #define AR5K_SLEEP1_BEACON_TO 0xff000000 /* Mask for Beacon Time Out */ |
1513 | #define AR5K_SLEEP1_BEACON_TO_S 24 | 1617 | #define AR5K_SLEEP1_BEACON_TO_S 24 |
1514 | 1618 | ||
1515 | /* | 1619 | /* |
1516 | * Third enhanced sleep register | 1620 | * Third enhanced sleep register |
1517 | */ | 1621 | */ |
1518 | #define AR5K_SLEEP2 0x80dc | 1622 | #define AR5K_SLEEP2 0x80dc /* Register Address */ |
1519 | #define AR5K_SLEEP2_TIM_PER 0x0000ffff | 1623 | #define AR5K_SLEEP2_TIM_PER 0x0000ffff /* Mask for TIM period (?) */ |
1520 | #define AR5K_SLEEP2_TIM_PER_S 0 | 1624 | #define AR5K_SLEEP2_TIM_PER_S 0 |
1521 | #define AR5K_SLEEP2_DTIM_PER 0xffff0000 | 1625 | #define AR5K_SLEEP2_DTIM_PER 0xffff0000 /* Mask for DTIM period (?) */ |
1522 | #define AR5K_SLEEP2_DTIM_PER_S 16 | 1626 | #define AR5K_SLEEP2_DTIM_PER_S 16 |
1523 | 1627 | ||
1524 | /* | 1628 | /* |
1525 | * BSSID mask registers | 1629 | * BSSID mask registers |
1526 | */ | 1630 | */ |
1527 | #define AR5K_BSS_IDM0 0x80e0 | 1631 | #define AR5K_BSS_IDM0 0x80e0 /* Upper bits */ |
1528 | #define AR5K_BSS_IDM1 0x80e4 | 1632 | #define AR5K_BSS_IDM1 0x80e4 /* Lower bits */ |
1529 | 1633 | ||
1530 | /* | 1634 | /* |
1531 | * TX power control (TPC) register | 1635 | * TX power control (TPC) register |
1636 | * | ||
1637 | * XXX: PCDAC steps (0.5dbm) or DBM ? | ||
1638 | * | ||
1639 | * XXX: Mask changes for newer chips to 7f | ||
1640 | * like tx power table ? | ||
1532 | */ | 1641 | */ |
1533 | #define AR5K_TXPC 0x80e8 | 1642 | #define AR5K_TXPC 0x80e8 /* Register Address */ |
1534 | #define AR5K_TXPC_ACK_M 0x0000003f | 1643 | #define AR5K_TXPC_ACK_M 0x0000003f /* Mask for ACK tx power */ |
1535 | #define AR5K_TXPC_ACK_S 0 | 1644 | #define AR5K_TXPC_ACK_S 0 |
1536 | #define AR5K_TXPC_CTS_M 0x00003f00 | 1645 | #define AR5K_TXPC_CTS_M 0x00003f00 /* Mask for CTS tx power */ |
1537 | #define AR5K_TXPC_CTS_S 8 | 1646 | #define AR5K_TXPC_CTS_S 8 |
1538 | #define AR5K_TXPC_CHIRP_M 0x003f0000 | 1647 | #define AR5K_TXPC_CHIRP_M 0x003f0000 /* Mask for CHIRP tx power */ |
1539 | #define AR5K_TXPC_CHIRP_S 22 | 1648 | #define AR5K_TXPC_CHIRP_S 22 |
1540 | 1649 | ||
1541 | /* | 1650 | /* |
1542 | * Profile count registers | 1651 | * Profile count registers |
1543 | */ | 1652 | */ |
1544 | #define AR5K_PROFCNT_TX 0x80ec | 1653 | #define AR5K_PROFCNT_TX 0x80ec /* Tx count */ |
1545 | #define AR5K_PROFCNT_RX 0x80f0 | 1654 | #define AR5K_PROFCNT_RX 0x80f0 /* Rx count */ |
1546 | #define AR5K_PROFCNT_RXCLR 0x80f4 | 1655 | #define AR5K_PROFCNT_RXCLR 0x80f4 /* Clear Rx count */ |
1547 | #define AR5K_PROFCNT_CYCLE 0x80f8 | 1656 | #define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle count (?) */ |
1657 | |||
1658 | /* | ||
1659 | * Quiet (period) control registers (?) | ||
1660 | */ | ||
1661 | #define AR5K_QUIET_CTL1 0x80fc /* Register Address */ | ||
1662 | #define AR5K_QUIET_CTL1_NEXT_QT 0x0000ffff /* Mask for next quiet (period?) (?) */ | ||
1663 | #define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet (period?) */ | ||
1664 | #define AR5K_QUIET_CTL2 0x8100 /* Register Address */ | ||
1665 | #define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period (?) */ | ||
1666 | #define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet duration (?) */ | ||
1548 | 1667 | ||
1549 | /* | 1668 | /* |
1550 | * TSF parameter register | 1669 | * TSF parameter register |
1551 | */ | 1670 | */ |
1552 | #define AR5K_TSF_PARM 0x8104 | 1671 | #define AR5K_TSF_PARM 0x8104 /* Register Address */ |
1553 | #define AR5K_TSF_PARM_INC_M 0x000000ff | 1672 | #define AR5K_TSF_PARM_INC_M 0x000000ff /* Mask for TSF increment */ |
1554 | #define AR5K_TSF_PARM_INC_S 0 | 1673 | #define AR5K_TSF_PARM_INC_S 0 |
1555 | 1674 | ||
1556 | /* | 1675 | /* |
1676 | * QoS register (?) | ||
1677 | */ | ||
1678 | #define AR5K_QOS 0x8108 /* Register Address */ | ||
1679 | #define AR5K_QOS_NOACK_2BIT_VALUES 0x00000000 /* (field) */ | ||
1680 | #define AR5K_QOS_NOACK_BIT_OFFSET 0x00000020 /* (field) */ | ||
1681 | #define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000080 /* (field) */ | ||
1682 | |||
1683 | /* | ||
1557 | * PHY error filter register | 1684 | * PHY error filter register |
1558 | */ | 1685 | */ |
1559 | #define AR5K_PHY_ERR_FIL 0x810c | 1686 | #define AR5K_PHY_ERR_FIL 0x810c |
1560 | #define AR5K_PHY_ERR_FIL_RADAR 0x00000020 | 1687 | #define AR5K_PHY_ERR_FIL_RADAR 0x00000020 /* Radar signal */ |
1561 | #define AR5K_PHY_ERR_FIL_OFDM 0x00020000 | 1688 | #define AR5K_PHY_ERR_FIL_OFDM 0x00020000 /* OFDM false detect (ANI) */ |
1562 | #define AR5K_PHY_ERR_FIL_CCK 0x02000000 | 1689 | #define AR5K_PHY_ERR_FIL_CCK 0x02000000 /* CCK false detect (ANI) */ |
1690 | |||
1691 | /* | ||
1692 | * XR latency register | ||
1693 | */ | ||
1694 | #define AR5K_XRLAT_TX 0x8110 | ||
1563 | 1695 | ||
1564 | /* | 1696 | /* |
1565 | * Rate duration register | 1697 | * ACK SIFS register |
1698 | */ | ||
1699 | #define AR5K_ACKSIFS 0x8114 /* Register Address */ | ||
1700 | #define AR5K_ACKSIFS_INC 0x00000000 /* ACK SIFS Increment (field) */ | ||
1701 | |||
1702 | /* | ||
1703 | * MIC QoS control register (?) | ||
1704 | */ | ||
1705 | #define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */ | ||
1706 | #define AR5K_MIC_QOS_CTL_0 0x00000001 /* MIC QoS control 0 (?) */ | ||
1707 | #define AR5K_MIC_QOS_CTL_1 0x00000004 /* MIC QoS control 1 (?) */ | ||
1708 | #define AR5K_MIC_QOS_CTL_2 0x00000010 /* MIC QoS control 2 (?) */ | ||
1709 | #define AR5K_MIC_QOS_CTL_3 0x00000040 /* MIC QoS control 3 (?) */ | ||
1710 | #define AR5K_MIC_QOS_CTL_4 0x00000100 /* MIC QoS control 4 (?) */ | ||
1711 | #define AR5K_MIC_QOS_CTL_5 0x00000400 /* MIC QoS control 5 (?) */ | ||
1712 | #define AR5K_MIC_QOS_CTL_6 0x00001000 /* MIC QoS control 6 (?) */ | ||
1713 | #define AR5K_MIC_QOS_CTL_7 0x00004000 /* MIC QoS control 7 (?) */ | ||
1714 | #define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */ | ||
1715 | |||
1716 | /* | ||
1717 | * MIC QoS select register (?) | ||
1718 | */ | ||
1719 | #define AR5K_MIC_QOS_SEL 0x811c | ||
1720 | #define AR5K_MIC_QOS_SEL_0 0x00000001 | ||
1721 | #define AR5K_MIC_QOS_SEL_1 0x00000010 | ||
1722 | #define AR5K_MIC_QOS_SEL_2 0x00000100 | ||
1723 | #define AR5K_MIC_QOS_SEL_3 0x00001000 | ||
1724 | #define AR5K_MIC_QOS_SEL_4 0x00010000 | ||
1725 | #define AR5K_MIC_QOS_SEL_5 0x00100000 | ||
1726 | #define AR5K_MIC_QOS_SEL_6 0x01000000 | ||
1727 | #define AR5K_MIC_QOS_SEL_7 0x10000000 | ||
1728 | |||
1729 | /* | ||
1730 | * Misc mode control register (?) | ||
1731 | */ | ||
1732 | #define AR5K_MISC_MODE 0x8120 /* Register Address */ | ||
1733 | #define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001 /* Force BSSID match */ | ||
1734 | #define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002 /* ACK SIFS memory (?) */ | ||
1735 | /* more bits */ | ||
1736 | |||
1737 | /* | ||
1738 | * OFDM Filter counter | ||
1739 | */ | ||
1740 | #define AR5K_OFDM_FIL_CNT 0x8124 | ||
1741 | |||
1742 | /* | ||
1743 | * CCK Filter counter | ||
1744 | */ | ||
1745 | #define AR5K_CCK_FIL_CNT 0x8128 | ||
1746 | |||
1747 | /* | ||
1748 | * PHY Error Counters (?) | ||
1749 | */ | ||
1750 | #define AR5K_PHYERR_CNT1 0x812c | ||
1751 | #define AR5K_PHYERR_CNT1_MASK 0x8130 | ||
1752 | |||
1753 | #define AR5K_PHYERR_CNT2 0x8134 | ||
1754 | #define AR5K_PHYERR_CNT2_MASK 0x8138 | ||
1755 | |||
1756 | /* | ||
1757 | * TSF Threshold register (?) | ||
1758 | */ | ||
1759 | #define AR5K_TSF_THRES 0x813c | ||
1760 | |||
1761 | /* | ||
1762 | * Rate -> ACK SIFS mapping table (32 entries) | ||
1763 | */ | ||
1764 | #define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */ | ||
1765 | #define AR5K_RATE_ACKSIFS(_n) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2)) | ||
1766 | #define AR5K_RATE_ACKSIFS_NORMAL 0x00000001 /* Normal SIFS (field) */ | ||
1767 | #define AR5K_RATE_ACKSIFS_TURBO 0x00000400 /* Turbo SIFS (field) */ | ||
1768 | |||
1769 | /* | ||
1770 | * Rate -> duration mapping table (32 entries) | ||
1566 | */ | 1771 | */ |
1567 | #define AR5K_RATE_DUR_BASE 0x8700 | 1772 | #define AR5K_RATE_DUR_BASE 0x8700 |
1568 | #define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) | 1773 | #define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) |
1569 | 1774 | ||
1775 | /* | ||
1776 | * Rate -> db mapping table | ||
1777 | * (8 entries, each one has 4 8bit fields) | ||
1778 | */ | ||
1779 | #define AR5K_RATE2DB_BASE 0x87c0 | ||
1780 | #define AR5K_RATE2DB(_n) (AR5K_RATE2DB_BASE + ((_n) << 2)) | ||
1781 | |||
1782 | /* | ||
1783 | * db -> Rate mapping table | ||
1784 | * (8 entries, each one has 4 8bit fields) | ||
1785 | */ | ||
1786 | #define AR5K_DB2RATE_BASE 0x87e0 | ||
1787 | #define AR5K_DB2RATE(_n) (AR5K_DB2RATE_BASE + ((_n) << 2)) | ||
1788 | |||
1570 | /*===5212 end===*/ | 1789 | /*===5212 end===*/ |
1571 | 1790 | ||
1572 | /* | 1791 | /* |
@@ -1613,12 +1832,34 @@ | |||
1613 | /*===PHY REGISTERS===*/ | 1832 | /*===PHY REGISTERS===*/ |
1614 | 1833 | ||
1615 | /* | 1834 | /* |
1616 | * PHY register | 1835 | * PHY registers start |
1617 | */ | 1836 | */ |
1618 | #define AR5K_PHY_BASE 0x9800 | 1837 | #define AR5K_PHY_BASE 0x9800 |
1619 | #define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2)) | 1838 | #define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2)) |
1620 | #define AR5K_PHY_SHIFT_2GHZ 0x00004007 | 1839 | |
1621 | #define AR5K_PHY_SHIFT_5GHZ 0x00000007 | 1840 | /* |
1841 | * TST_2 (Misc config parameters) | ||
1842 | */ | ||
1843 | #define AR5K_PHY_TST2 0x9800 /* Register Address */ | ||
1844 | #define AR5K_PHY_TST2_TRIG_SEL 0x00000001 /* Trigger select (?) (field ?) */ | ||
1845 | #define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) (field ?) */ | ||
1846 | #define AR5K_PHY_TST2_CBUS_MODE 0x00000100 /* Cardbus mode (?) */ | ||
1847 | /* bit reserved */ | ||
1848 | #define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32Khz external) */ | ||
1849 | #define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */ | ||
1850 | #define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */ | ||
1851 | #define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */ | ||
1852 | #define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch) */ | ||
1853 | #define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */ | ||
1854 | #define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */ | ||
1855 | #define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */ | ||
1856 | #define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000 /* AGC OBS Select 3 (?) */ | ||
1857 | #define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000 /* BB OBS Select (field ?) */ | ||
1858 | #define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000 /* ADC OBS Select (field ?) */ | ||
1859 | #define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000 /* RX Clear Select (?) */ | ||
1860 | #define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000 /* Force AGC clear (?) */ | ||
1861 | #define AR5K_PHY_SHIFT_2GHZ 0x00004007 /* Used to access 2GHz radios */ | ||
1862 | #define AR5K_PHY_SHIFT_5GHZ 0x00000007 /* Used to access 5GHz radios (default) */ | ||
1622 | 1863 | ||
1623 | /* | 1864 | /* |
1624 | * PHY frame control register [5110] /turbo mode register [5111+] | 1865 | * PHY frame control register [5110] /turbo mode register [5111+] |
@@ -1630,18 +1871,21 @@ | |||
1630 | * a "turbo mode register" for 5110. We treat this one as | 1871 | * a "turbo mode register" for 5110. We treat this one as |
1631 | * a frame control register for 5110 below. | 1872 | * a frame control register for 5110 below. |
1632 | */ | 1873 | */ |
1633 | #define AR5K_PHY_TURBO 0x9804 | 1874 | #define AR5K_PHY_TURBO 0x9804 /* Register Address */ |
1634 | #define AR5K_PHY_TURBO_MODE 0x00000001 | 1875 | #define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */ |
1635 | #define AR5K_PHY_TURBO_SHORT 0x00000002 | 1876 | #define AR5K_PHY_TURBO_SHORT 0x00000002 /* Short mode (20Mhz channels) (?) */ |
1636 | 1877 | ||
1637 | /* | 1878 | /* |
1638 | * PHY agility command register | 1879 | * PHY agility command register |
1880 | * (aka TST_1) | ||
1639 | */ | 1881 | */ |
1640 | #define AR5K_PHY_AGC 0x9808 | 1882 | #define AR5K_PHY_AGC 0x9808 /* Register Address */ |
1641 | #define AR5K_PHY_AGC_DISABLE 0x08000000 | 1883 | #define AR5K_PHY_TST1 0x9808 |
1884 | #define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/ | ||
1885 | #define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */ | ||
1642 | 1886 | ||
1643 | /* | 1887 | /* |
1644 | * PHY timing register [5112+] | 1888 | * PHY timing register 3 [5112+] |
1645 | */ | 1889 | */ |
1646 | #define AR5K_PHY_TIMING_3 0x9814 | 1890 | #define AR5K_PHY_TIMING_3 0x9814 |
1647 | #define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 | 1891 | #define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 |
@@ -1657,26 +1901,81 @@ | |||
1657 | /* | 1901 | /* |
1658 | * PHY activation register | 1902 | * PHY activation register |
1659 | */ | 1903 | */ |
1660 | #define AR5K_PHY_ACT 0x981c | 1904 | #define AR5K_PHY_ACT 0x981c /* Register Address */ |
1661 | #define AR5K_PHY_ACT_ENABLE 0x00000001 | 1905 | #define AR5K_PHY_ACT_ENABLE 0x00000001 /* Activate PHY */ |
1662 | #define AR5K_PHY_ACT_DISABLE 0x00000002 | 1906 | #define AR5K_PHY_ACT_DISABLE 0x00000002 /* Deactivate PHY */ |
1907 | |||
1908 | /* | ||
1909 | * PHY RF control registers | ||
1910 | * (i think these are delay times, | ||
1911 | * these calibration values exist | ||
1912 | * in EEPROM) | ||
1913 | */ | ||
1914 | #define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */ | ||
1915 | #define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* Mask for TX frame to TX d(esc?) start */ | ||
1916 | |||
1917 | #define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */ | ||
1918 | #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000000f /* Mask for TX end to XLNA on */ | ||
1919 | |||
1920 | #define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */ | ||
1921 | #define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */ | ||
1922 | #define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 /* TX frame to XPA B on (field) */ | ||
1923 | #define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 /* TX end to XPA A off (field) */ | ||
1924 | #define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 /* TX end to XPA B off (field) */ | ||
1925 | |||
1926 | /* | ||
1927 | * Pre-Amplifier control register | ||
1928 | * (XPA -> external pre-amplifier) | ||
1929 | */ | ||
1930 | #define AR5K_PHY_PA_CTL 0x9838 /* Register Address */ | ||
1931 | #define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001 /* XPA A high (?) */ | ||
1932 | #define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002 /* XPA B high (?) */ | ||
1933 | #define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 /* Enable XPA A */ | ||
1934 | #define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 /* Enable XPA B */ | ||
1935 | |||
1936 | /* | ||
1937 | * PHY settling register | ||
1938 | */ | ||
1939 | #define AR5K_PHY_SETTLING 0x9844 /* Register Address */ | ||
1940 | #define AR5K_PHY_SETTLING_AGC 0x0000007f /* Mask for AGC settling time */ | ||
1941 | #define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Mask for Switch settlig time */ | ||
1942 | |||
1943 | /* | ||
1944 | * PHY Gain registers | ||
1945 | */ | ||
1946 | #define AR5K_PHY_GAIN 0x9848 /* Register Address */ | ||
1947 | #define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* Mask for TX-RX Attenuation */ | ||
1948 | |||
1949 | #define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */ | ||
1950 | #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */ | ||
1951 | |||
1952 | /* | ||
1953 | * Desired size register | ||
1954 | * (for more infos read ANI patent) | ||
1955 | */ | ||
1956 | #define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */ | ||
1957 | #define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* Mask for ADC desired size */ | ||
1958 | #define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* Mask for PGA desired size */ | ||
1959 | #define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Mask for Total desired size (?) */ | ||
1663 | 1960 | ||
1664 | /* | 1961 | /* |
1665 | * PHY signal register | 1962 | * PHY signal register |
1963 | * (for more infos read ANI patent) | ||
1666 | */ | 1964 | */ |
1667 | #define AR5K_PHY_SIG 0x9858 | 1965 | #define AR5K_PHY_SIG 0x9858 /* Register Address */ |
1668 | #define AR5K_PHY_SIG_FIRSTEP 0x0003f000 | 1966 | #define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* Mask for FIRSTEP */ |
1669 | #define AR5K_PHY_SIG_FIRSTEP_S 12 | 1967 | #define AR5K_PHY_SIG_FIRSTEP_S 12 |
1670 | #define AR5K_PHY_SIG_FIRPWR 0x03fc0000 | 1968 | #define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* Mask for FIPWR */ |
1671 | #define AR5K_PHY_SIG_FIRPWR_S 18 | 1969 | #define AR5K_PHY_SIG_FIRPWR_S 18 |
1672 | 1970 | ||
1673 | /* | 1971 | /* |
1674 | * PHY coarse agility control register | 1972 | * PHY coarse agility control register |
1973 | * (for more infos read ANI patent) | ||
1675 | */ | 1974 | */ |
1676 | #define AR5K_PHY_AGCCOARSE 0x985c | 1975 | #define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */ |
1677 | #define AR5K_PHY_AGCCOARSE_LO 0x00007f80 | 1976 | #define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* Mask for AGC Coarse low */ |
1678 | #define AR5K_PHY_AGCCOARSE_LO_S 7 | 1977 | #define AR5K_PHY_AGCCOARSE_LO_S 7 |
1679 | #define AR5K_PHY_AGCCOARSE_HI 0x003f8000 | 1978 | #define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* Mask for AGC Coarse high */ |
1680 | #define AR5K_PHY_AGCCOARSE_HI_S 15 | 1979 | #define AR5K_PHY_AGCCOARSE_HI_S 15 |
1681 | 1980 | ||
1682 | /* | 1981 | /* |
@@ -1689,12 +1988,13 @@ | |||
1689 | /* | 1988 | /* |
1690 | * PHY noise floor status register | 1989 | * PHY noise floor status register |
1691 | */ | 1990 | */ |
1692 | #define AR5K_PHY_NF 0x9864 | 1991 | #define AR5K_PHY_NF 0x9864 /* Register address */ |
1693 | #define AR5K_PHY_NF_M 0x000001ff | 1992 | #define AR5K_PHY_NF_M 0x000001ff /* Noise floor mask */ |
1694 | #define AR5K_PHY_NF_ACTIVE 0x00000100 | 1993 | #define AR5K_PHY_NF_ACTIVE 0x00000100 /* Noise floor calibration still active */ |
1695 | #define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) | 1994 | #define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) |
1696 | #define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) | 1995 | #define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) |
1697 | #define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) | 1996 | #define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) |
1997 | #define AR5K_PHY_NF_THRESH62 0x00001000 /* Thresh62 -check ANI patent- (field) */ | ||
1698 | 1998 | ||
1699 | /* | 1999 | /* |
1700 | * PHY ADC saturation register [5110] | 2000 | * PHY ADC saturation register [5110] |
@@ -1706,6 +2006,30 @@ | |||
1706 | #define AR5K_PHY_ADCSAT_THR_S 5 | 2006 | #define AR5K_PHY_ADCSAT_THR_S 5 |
1707 | 2007 | ||
1708 | /* | 2008 | /* |
2009 | * PHY Weak ofdm signal detection threshold registers (ANI) [5212+] | ||
2010 | */ | ||
2011 | |||
2012 | /* High thresholds */ | ||
2013 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868 | ||
2014 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f | ||
2015 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0 | ||
2016 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000 | ||
2017 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 17 | ||
2018 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000 | ||
2019 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24 | ||
2020 | |||
2021 | /* Low thresholds */ | ||
2022 | #define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c | ||
2023 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001 | ||
2024 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00 | ||
2025 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8 | ||
2026 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000 | ||
2027 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14 | ||
2028 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000 | ||
2029 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21 | ||
2030 | |||
2031 | |||
2032 | /* | ||
1709 | * PHY sleep registers [5112+] | 2033 | * PHY sleep registers [5112+] |
1710 | */ | 2034 | */ |
1711 | #define AR5K_PHY_SCR 0x9870 | 2035 | #define AR5K_PHY_SCR 0x9870 |
@@ -1730,6 +2054,8 @@ | |||
1730 | AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) | 2054 | AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) |
1731 | #define AR5K_PHY_PLL_RF5111 0x00000000 | 2055 | #define AR5K_PHY_PLL_RF5111 0x00000000 |
1732 | #define AR5K_PHY_PLL_RF5112 0x00000040 | 2056 | #define AR5K_PHY_PLL_RF5112 0x00000040 |
2057 | #define AR5K_PHY_PLL_HALF_RATE 0x00000100 | ||
2058 | #define AR5K_PHY_PLL_QUARTER_RATE 0x00000200 | ||
1733 | 2059 | ||
1734 | /* | 2060 | /* |
1735 | * RF Buffer register | 2061 | * RF Buffer register |
@@ -1792,23 +2118,74 @@ | |||
1792 | #define AR5K_PHY_RFSTG_DISABLE 0x00000021 | 2118 | #define AR5K_PHY_RFSTG_DISABLE 0x00000021 |
1793 | 2119 | ||
1794 | /* | 2120 | /* |
2121 | * PHY Antenna control register | ||
2122 | */ | ||
2123 | #define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */ | ||
2124 | #define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */ | ||
2125 | #define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */ | ||
2126 | #define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */ | ||
2127 | #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x00000010 /* Switch table idle (?) */ | ||
2128 | |||
2129 | /* | ||
1795 | * PHY receiver delay register [5111+] | 2130 | * PHY receiver delay register [5111+] |
1796 | */ | 2131 | */ |
1797 | #define AR5K_PHY_RX_DELAY 0x9914 | 2132 | #define AR5K_PHY_RX_DELAY 0x9914 /* Register Address */ |
1798 | #define AR5K_PHY_RX_DELAY_M 0x00003fff | 2133 | #define AR5K_PHY_RX_DELAY_M 0x00003fff /* Mask for RX activate to receive delay (/100ns) */ |
2134 | |||
2135 | /* | ||
2136 | * PHY max rx length register (?) [5111] | ||
2137 | */ | ||
2138 | #define AR5K_PHY_MAX_RX_LEN 0x991c | ||
1799 | 2139 | ||
1800 | /* | 2140 | /* |
1801 | * PHY timing I(nphase) Q(adrature) control register [5111+] | 2141 | * PHY timing register 4 |
2142 | * I(nphase)/Q(adrature) calibration register [5111+] | ||
1802 | */ | 2143 | */ |
1803 | #define AR5K_PHY_IQ 0x9920 /* Register address */ | 2144 | #define AR5K_PHY_IQ 0x9920 /* Register Address */ |
1804 | #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ | 2145 | #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ |
1805 | #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ | 2146 | #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ |
1806 | #define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 | 2147 | #define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 |
1807 | #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ | 2148 | #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ |
1808 | #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 | 2149 | #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 /* Mask for max number of samples in log scale */ |
1809 | #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 | 2150 | #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 |
1810 | #define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */ | 2151 | #define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */ |
2152 | #define AR5K_PHY_IQ_USE_PT_DF 0x00020000 /* Use pilot track df (?) */ | ||
2153 | #define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 /* Early trigger threshold (?) (field) */ | ||
2154 | #define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 /* Enable pilot mask (?) */ | ||
2155 | #define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 /* Enable channel mask (?) */ | ||
2156 | #define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 /* Enable spur filter */ | ||
2157 | #define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 /* Enable spur rssi */ | ||
1811 | 2158 | ||
2159 | /* | ||
2160 | * PHY timing register 5 | ||
2161 | * OFDM Self-correlator Cyclic RSSI threshold params | ||
2162 | * (Check out bb_cycpwr_thr1 on ANI patent) | ||
2163 | */ | ||
2164 | #define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */ | ||
2165 | #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */ | ||
2166 | #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */ | ||
2167 | #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */ | ||
2168 | #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */ | ||
2169 | #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */ | ||
2170 | #define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000 /* Long sc threshold hi rssi (?) */ | ||
2171 | |||
2172 | /* | ||
2173 | * PHY-only warm reset register | ||
2174 | */ | ||
2175 | #define AR5K_PHY_WARM_RESET 0x9928 | ||
2176 | |||
2177 | /* | ||
2178 | * PHY-only control register | ||
2179 | */ | ||
2180 | #define AR5K_PHY_CTL 0x992c /* Register Address */ | ||
2181 | #define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001 /* RX drain rate (?) */ | ||
2182 | #define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 /* Late tx signal symbol (?) */ | ||
2183 | #define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004 /* Generate scrambler */ | ||
2184 | #define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008 /* TX antenna select */ | ||
2185 | #define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 /* Static TX antenna */ | ||
2186 | #define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020 /* RX antenna select */ | ||
2187 | #define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040 /* Static RX antenna */ | ||
2188 | #define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */ | ||
1812 | 2189 | ||
1813 | /* | 2190 | /* |
1814 | * PHY PAPD probe register [5111+ (?)] | 2191 | * PHY PAPD probe register [5111+ (?)] |
@@ -1816,9 +2193,13 @@ | |||
1816 | * Because it's always 0 in 5211 initialization code | 2193 | * Because it's always 0 in 5211 initialization code |
1817 | */ | 2194 | */ |
1818 | #define AR5K_PHY_PAPD_PROBE 0x9930 | 2195 | #define AR5K_PHY_PAPD_PROBE 0x9930 |
2196 | #define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001 | ||
2197 | #define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002 | ||
2198 | #define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040 | ||
1819 | #define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 | 2199 | #define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 |
1820 | #define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 | 2200 | #define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 |
1821 | #define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 | 2201 | #define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 |
2202 | #define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000 | ||
1822 | #define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */ | 2203 | #define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */ |
1823 | #define AR5K_PHY_PAPD_PROBE_TYPE_S 23 | 2204 | #define AR5K_PHY_PAPD_PROBE_TYPE_S 23 |
1824 | #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 | 2205 | #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 |
@@ -1848,15 +2229,16 @@ | |||
1848 | #define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \ | 2229 | #define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \ |
1849 | AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) | 2230 | AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) |
1850 | /*---[5111+]---*/ | 2231 | /*---[5111+]---*/ |
1851 | #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 | 2232 | #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */ |
1852 | #define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 | 2233 | #define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 |
2234 | #define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */ | ||
1853 | /*---[5110/5111]---*/ | 2235 | /*---[5110/5111]---*/ |
1854 | #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 | 2236 | #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */ |
1855 | #define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 | 2237 | #define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */ |
1856 | #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 /* illegal rate */ | 2238 | #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 /* Illegal rate */ |
1857 | #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* illegal length */ | 2239 | #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* Illegal length */ |
1858 | #define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 | 2240 | #define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 |
1859 | #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* tx underrun */ | 2241 | #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* TX underrun */ |
1860 | #define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ | 2242 | #define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ |
1861 | AR5K_PHY_FRAME_CTL_TXURN_ERR | \ | 2243 | AR5K_PHY_FRAME_CTL_TXURN_ERR | \ |
1862 | AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ | 2244 | AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ |
@@ -1915,6 +2297,11 @@ after DFS is enabled */ | |||
1915 | #define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 | 2297 | #define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 |
1916 | 2298 | ||
1917 | /* | 2299 | /* |
2300 | * PHY Noise floor threshold | ||
2301 | */ | ||
2302 | #define AR5K_PHY_NFTHRES 0x9968 | ||
2303 | |||
2304 | /* | ||
1918 | * PHY clock sleep registers [5112+] | 2305 | * PHY clock sleep registers [5112+] |
1919 | */ | 2306 | */ |
1920 | #define AR5K_PHY_SCLOCK 0x99f0 | 2307 | #define AR5K_PHY_SCLOCK 0x99f0 |
@@ -1922,56 +2309,116 @@ after DFS is enabled */ | |||
1922 | #define AR5K_PHY_SDELAY 0x99f4 | 2309 | #define AR5K_PHY_SDELAY 0x99f4 |
1923 | #define AR5K_PHY_SDELAY_32MHZ 0x000000ff | 2310 | #define AR5K_PHY_SDELAY_32MHZ 0x000000ff |
1924 | #define AR5K_PHY_SPENDING 0x99f8 | 2311 | #define AR5K_PHY_SPENDING 0x99f8 |
2312 | #define AR5K_PHY_SPENDING_14 0x00000014 | ||
2313 | #define AR5K_PHY_SPENDING_18 0x00000018 | ||
1925 | #define AR5K_PHY_SPENDING_RF5111 0x00000018 | 2314 | #define AR5K_PHY_SPENDING_RF5111 0x00000018 |
1926 | #define AR5K_PHY_SPENDING_RF5112 0x00000014 /* <- i 've only seen this on 2425 dumps ! */ | 2315 | #define AR5K_PHY_SPENDING_RF5112 0x00000014 |
1927 | #define AR5K_PHY_SPENDING_RF5112A 0x0000000e /* but since i only have 5112A-based chips */ | 2316 | /* #define AR5K_PHY_SPENDING_RF5112A 0x0000000e */ |
1928 | #define AR5K_PHY_SPENDING_RF5424 0x00000012 /* to test it might be also for old 5112. */ | 2317 | /* #define AR5K_PHY_SPENDING_RF5424 0x00000012 */ |
2318 | #define AR5K_PHY_SPENDING_RF5413 0x00000014 | ||
2319 | #define AR5K_PHY_SPENDING_RF2413 0x00000014 | ||
2320 | #define AR5K_PHY_SPENDING_RF2425 0x00000018 | ||
1929 | 2321 | ||
1930 | /* | 2322 | /* |
1931 | * Misc PHY/radio registers [5110 - 5111] | 2323 | * Misc PHY/radio registers [5110 - 5111] |
1932 | */ | 2324 | */ |
1933 | #define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ | 2325 | #define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ |
1934 | #define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) | 2326 | #define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) |
1935 | #define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */ | 2327 | #define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */ |
1936 | #define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) | 2328 | #define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) |
1937 | 2329 | ||
1938 | /* | 2330 | /* |
1939 | * PHY timing IQ calibration result register [5111+] | 2331 | * PHY timing IQ calibration result register [5111+] |
1940 | */ | 2332 | */ |
1941 | #define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */ | 2333 | #define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */ |
1942 | #define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */ | 2334 | #define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */ |
1943 | #define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* I/Q Correlation */ | 2335 | #define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* I/Q Correlation */ |
1944 | 2336 | ||
1945 | /* | 2337 | /* |
1946 | * PHY current RSSI register [5111+] | 2338 | * PHY current RSSI register [5111+] |
1947 | */ | 2339 | */ |
1948 | #define AR5K_PHY_CURRENT_RSSI 0x9c1c | 2340 | #define AR5K_PHY_CURRENT_RSSI 0x9c1c |
2341 | |||
2342 | /* | ||
2343 | * PHY RF Bus grant register (?) | ||
2344 | */ | ||
2345 | #define AR5K_PHY_RFBUS_GRANT 0x9c20 | ||
2346 | |||
2347 | /* | ||
2348 | * PHY ADC test register | ||
2349 | */ | ||
2350 | #define AR5K_PHY_ADC_TEST 0x9c24 | ||
2351 | #define AR5K_PHY_ADC_TEST_I 0x00000001 | ||
2352 | #define AR5K_PHY_ADC_TEST_Q 0x00000200 | ||
2353 | |||
2354 | /* | ||
2355 | * PHY DAC test register | ||
2356 | */ | ||
2357 | #define AR5K_PHY_DAC_TEST 0x9c28 | ||
2358 | #define AR5K_PHY_DAC_TEST_I 0x00000001 | ||
2359 | #define AR5K_PHY_DAC_TEST_Q 0x00000200 | ||
2360 | |||
2361 | /* | ||
2362 | * PHY PTAT register (?) | ||
2363 | */ | ||
2364 | #define AR5K_PHY_PTAT 0x9c2c | ||
2365 | |||
2366 | /* | ||
2367 | * PHY Illegal TX rate register [5112+] | ||
2368 | */ | ||
2369 | #define AR5K_PHY_BAD_TX_RATE 0x9c30 | ||
2370 | |||
2371 | /* | ||
2372 | * PHY SPUR Power register [5112+] | ||
2373 | */ | ||
2374 | #define AR5K_PHY_SPUR_PWR 0x9c34 /* Register Address */ | ||
2375 | #define AR5K_PHY_SPUR_PWR_I 0x00000001 /* SPUR Power estimate for I (field) */ | ||
2376 | #define AR5K_PHY_SPUR_PWR_Q 0x00000100 /* SPUR Power estimate for Q (field) */ | ||
2377 | #define AR5K_PHY_SPUR_PWR_FILT 0x00010000 /* Power with SPUR removed (field) */ | ||
2378 | |||
2379 | /* | ||
2380 | * PHY Channel status register [5112+] (?) | ||
2381 | */ | ||
2382 | #define AR5K_PHY_CHAN_STATUS 0x9c38 | ||
2383 | #define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001 | ||
2384 | #define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002 | ||
2385 | #define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004 | ||
2386 | #define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008 | ||
2387 | |||
2388 | /* | ||
2389 | * PHY PAPD I (power?) table (?) | ||
2390 | * (92! entries) | ||
2391 | */ | ||
2392 | #define AR5K_PHY_PAPD_I_BASE 0xa000 | ||
2393 | #define AR5K_PHY_PAPD_I(_n) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2)) | ||
1949 | 2394 | ||
1950 | /* | 2395 | /* |
1951 | * PHY PCDAC TX power table | 2396 | * PHY PCDAC TX power table |
1952 | */ | 2397 | */ |
1953 | #define AR5K_PHY_PCDAC_TXPOWER_BASE_5211 0xa180 | 2398 | #define AR5K_PHY_PCDAC_TXPOWER_BASE_5211 0xa180 |
1954 | #define AR5K_PHY_PCDAC_TXPOWER_BASE_5413 0xa280 | 2399 | #define AR5K_PHY_PCDAC_TXPOWER_BASE_2413 0xa280 |
1955 | #define AR5K_PHY_PCDAC_TXPOWER_BASE (ah->ah_radio >= AR5K_RF5413 ? \ | 2400 | #define AR5K_PHY_PCDAC_TXPOWER_BASE (ah->ah_radio >= AR5K_RF2413 ? \ |
1956 | AR5K_PHY_PCDAC_TXPOWER_BASE_5413 :\ | 2401 | AR5K_PHY_PCDAC_TXPOWER_BASE_2413 :\ |
1957 | AR5K_PHY_PCDAC_TXPOWER_BASE_5211) | 2402 | AR5K_PHY_PCDAC_TXPOWER_BASE_5211) |
1958 | #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) | 2403 | #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) |
1959 | 2404 | ||
1960 | /* | 2405 | /* |
1961 | * PHY mode register [5111+] | 2406 | * PHY mode register [5111+] |
1962 | */ | 2407 | */ |
1963 | #define AR5K_PHY_MODE 0x0a200 /* Register address */ | 2408 | #define AR5K_PHY_MODE 0x0a200 /* Register Address */ |
1964 | #define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation mask*/ | 2409 | #define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation bit */ |
1965 | #define AR5K_PHY_MODE_MOD_OFDM 0 | 2410 | #define AR5K_PHY_MODE_MOD_OFDM 0 |
1966 | #define AR5K_PHY_MODE_MOD_CCK 1 | 2411 | #define AR5K_PHY_MODE_MOD_CCK 1 |
1967 | #define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode mask */ | 2412 | #define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode bit */ |
1968 | #define AR5K_PHY_MODE_FREQ_5GHZ 0 | 2413 | #define AR5K_PHY_MODE_FREQ_5GHZ 0 |
1969 | #define AR5K_PHY_MODE_FREQ_2GHZ 2 | 2414 | #define AR5K_PHY_MODE_FREQ_2GHZ 2 |
1970 | #define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Dynamic OFDM/CCK mode mask [5112+] */ | 2415 | #define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Enable Dynamic OFDM/CCK mode [5112+] */ |
1971 | #define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */ | 2416 | #define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */ |
1972 | #define AR5K_PHY_MODE_RAD_RF5111 0 | 2417 | #define AR5K_PHY_MODE_RAD_RF5111 0 |
1973 | #define AR5K_PHY_MODE_RAD_RF5112 8 | 2418 | #define AR5K_PHY_MODE_RAD_RF5112 8 |
1974 | #define AR5K_PHY_MODE_XR 0x00000010 /* [5112+] */ | 2419 | #define AR5K_PHY_MODE_XR 0x00000010 /* Enable XR mode [5112+] */ |
2420 | #define AR5K_PHY_MODE_HALF_RATE 0x00000020 /* Enable Half rate (test) */ | ||
2421 | #define AR5K_PHY_MODE_QUARTER_RATE 0x00000040 /* Enable Quarter rat (test) */ | ||
1975 | 2422 | ||
1976 | /* | 2423 | /* |
1977 | * PHY CCK transmit control register [5111+ (?)] | 2424 | * PHY CCK transmit control register [5111+ (?)] |
@@ -1979,6 +2426,15 @@ after DFS is enabled */ | |||
1979 | #define AR5K_PHY_CCKTXCTL 0xa204 | 2426 | #define AR5K_PHY_CCKTXCTL 0xa204 |
1980 | #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 | 2427 | #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 |
1981 | #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 | 2428 | #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 |
2429 | #define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001 | ||
2430 | #define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004 | ||
2431 | |||
2432 | /* | ||
2433 | * PHY CCK Cross-correlator Barker RSSI threshold register [5212+] | ||
2434 | */ | ||
2435 | #define AR5K_PHY_CCK_CROSSCORR 0xa208 | ||
2436 | #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000000f | ||
2437 | #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0 | ||
1982 | 2438 | ||
1983 | /* | 2439 | /* |
1984 | * PHY 2GHz gain register [5111+] | 2440 | * PHY 2GHz gain register [5111+] |
diff --git a/drivers/net/wireless/ipw2200.c b/drivers/net/wireless/ipw2200.c index 846a7d051851..36e8d2f6e7b4 100644 --- a/drivers/net/wireless/ipw2200.c +++ b/drivers/net/wireless/ipw2200.c | |||
@@ -305,9 +305,10 @@ static inline void ipw_write_reg32(struct ipw_priv *a, u32 b, u32 c) | |||
305 | #define _ipw_write8(ipw, ofs, val) writeb((val), (ipw)->hw_base + (ofs)) | 305 | #define _ipw_write8(ipw, ofs, val) writeb((val), (ipw)->hw_base + (ofs)) |
306 | 306 | ||
307 | /* 8-bit direct write (for low 4K of SRAM/regs), with debug wrapper */ | 307 | /* 8-bit direct write (for low 4K of SRAM/regs), with debug wrapper */ |
308 | #define ipw_write8(ipw, ofs, val) \ | 308 | #define ipw_write8(ipw, ofs, val) do { \ |
309 | IPW_DEBUG_IO("%s %d: write_direct8(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \ | 309 | IPW_DEBUG_IO("%s %d: write_direct8(0x%08X, 0x%08X)\n", __FILE__, __LINE__, (u32)(ofs), (u32)(val)); \ |
310 | _ipw_write8(ipw, ofs, val) | 310 | _ipw_write8(ipw, ofs, val); \ |
311 | } while (0) | ||
311 | 312 | ||
312 | /* 16-bit direct write (low 4K) */ | 313 | /* 16-bit direct write (low 4K) */ |
313 | #define _ipw_write16(ipw, ofs, val) writew((val), (ipw)->hw_base + (ofs)) | 314 | #define _ipw_write16(ipw, ofs, val) writew((val), (ipw)->hw_base + (ofs)) |
diff --git a/drivers/net/wireless/iwlwifi/Kconfig b/drivers/net/wireless/iwlwifi/Kconfig index 82b66a3d3a5d..b0ac0ce3fb9f 100644 --- a/drivers/net/wireless/iwlwifi/Kconfig +++ b/drivers/net/wireless/iwlwifi/Kconfig | |||
@@ -14,18 +14,49 @@ config IWLWIFI_LEDS | |||
14 | default n | 14 | default n |
15 | 15 | ||
16 | config IWLWIFI_RFKILL | 16 | config IWLWIFI_RFKILL |
17 | boolean "IWLWIFI RF kill support" | 17 | boolean "Iwlwifi RF kill support" |
18 | depends on IWLCORE | 18 | depends on IWLCORE |
19 | 19 | ||
20 | config IWL4965 | 20 | config IWLWIFI_DEBUG |
21 | tristate "Intel Wireless WiFi 4965AGN" | 21 | bool "Enable full debugging output in iwlagn driver" |
22 | depends on IWLCORE | ||
23 | ---help--- | ||
24 | This option will enable debug tracing output for the iwlwifi drivers | ||
25 | |||
26 | This will result in the kernel module being ~100k larger. You can | ||
27 | control which debug output is sent to the kernel log by setting the | ||
28 | value in | ||
29 | |||
30 | /sys/class/net/wlan0/device/debug_level | ||
31 | |||
32 | This entry will only exist if this option is enabled. | ||
33 | |||
34 | To set a value, simply echo an 8-byte hex value to the same file: | ||
35 | |||
36 | % echo 0x43fff > /sys/class/net/wlan0/device/debug_level | ||
37 | |||
38 | You can find the list of debug mask values in: | ||
39 | drivers/net/wireless/iwlwifi/iwl-debug.h | ||
40 | |||
41 | If this is your first time using this driver, you should say Y here | ||
42 | as the debug information can assist others in helping you resolve | ||
43 | any problems you may encounter. | ||
44 | |||
45 | config IWLWIFI_DEBUGFS | ||
46 | bool "Iwlwifi debugfs support" | ||
47 | depends on IWLCORE && IWLWIFI_DEBUG && MAC80211_DEBUGFS | ||
48 | ---help--- | ||
49 | Enable creation of debugfs files for the iwlwifi drivers. | ||
50 | |||
51 | config IWLAGN | ||
52 | tristate "Intel Wireless WiFi Next Gen AGN" | ||
22 | depends on PCI && MAC80211 && WLAN_80211 && EXPERIMENTAL | 53 | depends on PCI && MAC80211 && WLAN_80211 && EXPERIMENTAL |
23 | select FW_LOADER | 54 | select FW_LOADER |
24 | select IWLCORE | 55 | select IWLCORE |
25 | ---help--- | 56 | ---help--- |
26 | Select to build the driver supporting the: | 57 | Select to build the driver supporting the: |
27 | 58 | ||
28 | Intel Wireless WiFi Link 4965AGN | 59 | Intel Wireless WiFi Link Next-Gen AGN |
29 | 60 | ||
30 | This driver uses the kernel's mac80211 subsystem. | 61 | This driver uses the kernel's mac80211 subsystem. |
31 | 62 | ||
@@ -42,60 +73,33 @@ config IWL4965 | |||
42 | If you want to compile the driver as a module ( = code which can be | 73 | If you want to compile the driver as a module ( = code which can be |
43 | inserted in and removed from the running kernel whenever you want), | 74 | inserted in and removed from the running kernel whenever you want), |
44 | say M here and read <file:Documentation/kbuild/modules.txt>. The | 75 | say M here and read <file:Documentation/kbuild/modules.txt>. The |
45 | module will be called iwl4965.ko. | 76 | module will be called iwlagn.ko. |
46 | |||
47 | config IWL4965_LEDS | ||
48 | bool "Enable LEDS features in iwl4965 driver" | ||
49 | depends on IWL4965 | ||
50 | select IWLWIFI_LEDS | ||
51 | ---help--- | ||
52 | This option enables LEDS for the iwlwifi drivers | ||
53 | 77 | ||
54 | 78 | config IWLAGN_SPECTRUM_MEASUREMENT | |
55 | config IWL4965_SPECTRUM_MEASUREMENT | 79 | bool "Enable Spectrum Measurement in iwlagn driver" |
56 | bool "Enable Spectrum Measurement in iwl4965 driver" | 80 | depends on IWLAGN |
57 | depends on IWL4965 | ||
58 | ---help--- | 81 | ---help--- |
59 | This option will enable spectrum measurement for the iwl4965 driver. | 82 | This option will enable spectrum measurement for the iwlagn driver. |
60 | 83 | ||
61 | config IWLWIFI_DEBUG | 84 | config IWLAGN_LEDS |
62 | bool "Enable full debugging output in iwl4965 driver" | 85 | bool "Enable LEDS features in iwlagn driver" |
63 | depends on IWL4965 | 86 | depends on IWLAGN |
87 | select IWLWIFI_LEDS | ||
64 | ---help--- | 88 | ---help--- |
65 | This option will enable debug tracing output for the iwl4965 | 89 | This option enables LEDS for the iwlagn drivers |
66 | driver. | ||
67 | |||
68 | This will result in the kernel module being ~100k larger. You can | ||
69 | control which debug output is sent to the kernel log by setting the | ||
70 | value in | ||
71 | |||
72 | /sys/class/net/wlan0/device/debug_level | ||
73 | |||
74 | This entry will only exist if this option is enabled. | ||
75 | |||
76 | To set a value, simply echo an 8-byte hex value to the same file: | ||
77 | |||
78 | % echo 0x43fff > /sys/class/net/wlan0/device/debug_level | ||
79 | 90 | ||
80 | You can find the list of debug mask values in: | ||
81 | drivers/net/wireless/iwlwifi/iwl-4965-debug.h | ||
82 | 91 | ||
83 | If this is your first time using this driver, you should say Y here | 92 | config IWL4965 |
84 | as the debug information can assist others in helping you resolve | 93 | bool "Intel Wireless WiFi 4965AGN" |
85 | any problems you may encounter. | 94 | depends on IWLAGN |
95 | ---help--- | ||
96 | This option enables support for Intel Wireless WiFi Link 4965AGN | ||
86 | 97 | ||
87 | config IWL5000 | 98 | config IWL5000 |
88 | bool "Intel Wireless WiFi 5000AGN" | 99 | bool "Intel Wireless WiFi 5000AGN" |
89 | depends on IWL4965 | 100 | depends on IWLAGN |
90 | ---help--- | 101 | ---help--- |
91 | This option enables support for Intel Wireless WiFi Link 5000AGN Family | 102 | This option enables support for Intel Wireless WiFi Link 5000AGN Family |
92 | Dependency on 4965 is temporary | ||
93 | |||
94 | config IWLWIFI_DEBUGFS | ||
95 | bool "Iwlwifi debugfs support" | ||
96 | depends on IWLCORE && IWLWIFI_DEBUG && MAC80211_DEBUGFS | ||
97 | ---help--- | ||
98 | Enable creation of debugfs files for the iwlwifi drivers. | ||
99 | 103 | ||
100 | config IWL3945 | 104 | config IWL3945 |
101 | tristate "Intel PRO/Wireless 3945ABG/BG Network Connection" | 105 | tristate "Intel PRO/Wireless 3945ABG/BG Network Connection" |
diff --git a/drivers/net/wireless/iwlwifi/Makefile b/drivers/net/wireless/iwlwifi/Makefile index 1f52b92f08b5..47aa28f6a513 100644 --- a/drivers/net/wireless/iwlwifi/Makefile +++ b/drivers/net/wireless/iwlwifi/Makefile | |||
@@ -6,15 +6,14 @@ iwlcore-$(CONFIG_IWLWIFI_DEBUGFS) += iwl-debugfs.o | |||
6 | iwlcore-$(CONFIG_IWLWIFI_LEDS) += iwl-led.o | 6 | iwlcore-$(CONFIG_IWLWIFI_LEDS) += iwl-led.o |
7 | iwlcore-$(CONFIG_IWLWIFI_RFKILL) += iwl-rfkill.o | 7 | iwlcore-$(CONFIG_IWLWIFI_RFKILL) += iwl-rfkill.o |
8 | 8 | ||
9 | obj-$(CONFIG_IWLAGN) += iwlagn.o | ||
10 | iwlagn-objs := iwl-agn.o iwl-agn-rs.o | ||
11 | |||
12 | iwlagn-$(CONFIG_IWL4965) += iwl-4965.o | ||
13 | iwlagn-$(CONFIG_IWL5000) += iwl-5000.o | ||
14 | |||
9 | obj-$(CONFIG_IWL3945) += iwl3945.o | 15 | obj-$(CONFIG_IWL3945) += iwl3945.o |
10 | iwl3945-objs := iwl3945-base.o iwl-3945.o iwl-3945-rs.o | 16 | iwl3945-objs := iwl3945-base.o iwl-3945.o iwl-3945-rs.o |
11 | iwl3945-$(CONFIG_IWL3945_LEDS) += iwl-3945-led.o | 17 | iwl3945-$(CONFIG_IWL3945_LEDS) += iwl-3945-led.o |
12 | 18 | ||
13 | obj-$(CONFIG_IWL4965) += iwl4965.o | ||
14 | iwl4965-objs := iwl4965-base.o iwl-4965.o iwl-4965-rs.o | ||
15 | |||
16 | ifeq ($(CONFIG_IWL5000),y) | ||
17 | iwl4965-objs += iwl-5000.o | ||
18 | endif | ||
19 | |||
20 | 19 | ||
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-led.c b/drivers/net/wireless/iwlwifi/iwl-3945-led.c index 6be1fe13fa57..d3336966b6b5 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945-led.c +++ b/drivers/net/wireless/iwlwifi/iwl-3945-led.c | |||
@@ -206,12 +206,12 @@ static void iwl3945_led_brightness_set(struct led_classdev *led_cdev, | |||
206 | static int iwl3945_led_register_led(struct iwl3945_priv *priv, | 206 | static int iwl3945_led_register_led(struct iwl3945_priv *priv, |
207 | struct iwl3945_led *led, | 207 | struct iwl3945_led *led, |
208 | enum led_type type, u8 set_led, | 208 | enum led_type type, u8 set_led, |
209 | const char *name, char *trigger) | 209 | char *trigger) |
210 | { | 210 | { |
211 | struct device *device = wiphy_dev(priv->hw->wiphy); | 211 | struct device *device = wiphy_dev(priv->hw->wiphy); |
212 | int ret; | 212 | int ret; |
213 | 213 | ||
214 | led->led_dev.name = name; | 214 | led->led_dev.name = led->name; |
215 | led->led_dev.brightness_set = iwl3945_led_brightness_set; | 215 | led->led_dev.brightness_set = iwl3945_led_brightness_set; |
216 | led->led_dev.default_trigger = trigger; | 216 | led->led_dev.default_trigger = trigger; |
217 | 217 | ||
@@ -308,7 +308,6 @@ void iwl3945_led_background(struct iwl3945_priv *priv) | |||
308 | int iwl3945_led_register(struct iwl3945_priv *priv) | 308 | int iwl3945_led_register(struct iwl3945_priv *priv) |
309 | { | 309 | { |
310 | char *trigger; | 310 | char *trigger; |
311 | char name[32]; | ||
312 | int ret; | 311 | int ret; |
313 | 312 | ||
314 | priv->last_blink_rate = 0; | 313 | priv->last_blink_rate = 0; |
@@ -318,7 +317,8 @@ int iwl3945_led_register(struct iwl3945_priv *priv) | |||
318 | priv->allow_blinking = 0; | 317 | priv->allow_blinking = 0; |
319 | 318 | ||
320 | trigger = ieee80211_get_radio_led_name(priv->hw); | 319 | trigger = ieee80211_get_radio_led_name(priv->hw); |
321 | snprintf(name, sizeof(name), "iwl-%s:radio", | 320 | snprintf(priv->led[IWL_LED_TRG_RADIO].name, |
321 | sizeof(priv->led[IWL_LED_TRG_RADIO].name), "iwl-%s:radio", | ||
322 | wiphy_name(priv->hw->wiphy)); | 322 | wiphy_name(priv->hw->wiphy)); |
323 | 323 | ||
324 | priv->led[IWL_LED_TRG_RADIO].led_on = iwl3945_led_on; | 324 | priv->led[IWL_LED_TRG_RADIO].led_on = iwl3945_led_on; |
@@ -327,19 +327,20 @@ int iwl3945_led_register(struct iwl3945_priv *priv) | |||
327 | 327 | ||
328 | ret = iwl3945_led_register_led(priv, | 328 | ret = iwl3945_led_register_led(priv, |
329 | &priv->led[IWL_LED_TRG_RADIO], | 329 | &priv->led[IWL_LED_TRG_RADIO], |
330 | IWL_LED_TRG_RADIO, 1, | 330 | IWL_LED_TRG_RADIO, 1, trigger); |
331 | name, trigger); | 331 | |
332 | if (ret) | 332 | if (ret) |
333 | goto exit_fail; | 333 | goto exit_fail; |
334 | 334 | ||
335 | trigger = ieee80211_get_assoc_led_name(priv->hw); | 335 | trigger = ieee80211_get_assoc_led_name(priv->hw); |
336 | snprintf(name, sizeof(name), "iwl-%s:assoc", | 336 | snprintf(priv->led[IWL_LED_TRG_ASSOC].name, |
337 | sizeof(priv->led[IWL_LED_TRG_ASSOC].name), "iwl-%s:assoc", | ||
337 | wiphy_name(priv->hw->wiphy)); | 338 | wiphy_name(priv->hw->wiphy)); |
338 | 339 | ||
339 | ret = iwl3945_led_register_led(priv, | 340 | ret = iwl3945_led_register_led(priv, |
340 | &priv->led[IWL_LED_TRG_ASSOC], | 341 | &priv->led[IWL_LED_TRG_ASSOC], |
341 | IWL_LED_TRG_ASSOC, 0, | 342 | IWL_LED_TRG_ASSOC, 0, trigger); |
342 | name, trigger); | 343 | |
343 | /* for assoc always turn led on */ | 344 | /* for assoc always turn led on */ |
344 | priv->led[IWL_LED_TRG_ASSOC].led_on = iwl3945_led_on; | 345 | priv->led[IWL_LED_TRG_ASSOC].led_on = iwl3945_led_on; |
345 | priv->led[IWL_LED_TRG_ASSOC].led_off = iwl3945_led_on; | 346 | priv->led[IWL_LED_TRG_ASSOC].led_off = iwl3945_led_on; |
@@ -349,14 +350,13 @@ int iwl3945_led_register(struct iwl3945_priv *priv) | |||
349 | goto exit_fail; | 350 | goto exit_fail; |
350 | 351 | ||
351 | trigger = ieee80211_get_rx_led_name(priv->hw); | 352 | trigger = ieee80211_get_rx_led_name(priv->hw); |
352 | snprintf(name, sizeof(name), "iwl-%s:RX", | 353 | snprintf(priv->led[IWL_LED_TRG_RX].name, |
354 | sizeof(priv->led[IWL_LED_TRG_RX].name), "iwl-%s:RX", | ||
353 | wiphy_name(priv->hw->wiphy)); | 355 | wiphy_name(priv->hw->wiphy)); |
354 | 356 | ||
355 | |||
356 | ret = iwl3945_led_register_led(priv, | 357 | ret = iwl3945_led_register_led(priv, |
357 | &priv->led[IWL_LED_TRG_RX], | 358 | &priv->led[IWL_LED_TRG_RX], |
358 | IWL_LED_TRG_RX, 0, | 359 | IWL_LED_TRG_RX, 0, trigger); |
359 | name, trigger); | ||
360 | 360 | ||
361 | priv->led[IWL_LED_TRG_RX].led_on = iwl3945_led_associated; | 361 | priv->led[IWL_LED_TRG_RX].led_on = iwl3945_led_associated; |
362 | priv->led[IWL_LED_TRG_RX].led_off = iwl3945_led_associated; | 362 | priv->led[IWL_LED_TRG_RX].led_off = iwl3945_led_associated; |
@@ -366,13 +366,14 @@ int iwl3945_led_register(struct iwl3945_priv *priv) | |||
366 | goto exit_fail; | 366 | goto exit_fail; |
367 | 367 | ||
368 | trigger = ieee80211_get_tx_led_name(priv->hw); | 368 | trigger = ieee80211_get_tx_led_name(priv->hw); |
369 | snprintf(name, sizeof(name), "iwl-%s:TX", | 369 | snprintf(priv->led[IWL_LED_TRG_TX].name, |
370 | sizeof(priv->led[IWL_LED_TRG_TX].name), "iwl-%s:TX", | ||
370 | wiphy_name(priv->hw->wiphy)); | 371 | wiphy_name(priv->hw->wiphy)); |
371 | 372 | ||
372 | ret = iwl3945_led_register_led(priv, | 373 | ret = iwl3945_led_register_led(priv, |
373 | &priv->led[IWL_LED_TRG_TX], | 374 | &priv->led[IWL_LED_TRG_TX], |
374 | IWL_LED_TRG_TX, 0, | 375 | IWL_LED_TRG_TX, 0, trigger); |
375 | name, trigger); | 376 | |
376 | priv->led[IWL_LED_TRG_TX].led_on = iwl3945_led_associated; | 377 | priv->led[IWL_LED_TRG_TX].led_on = iwl3945_led_associated; |
377 | priv->led[IWL_LED_TRG_TX].led_off = iwl3945_led_associated; | 378 | priv->led[IWL_LED_TRG_TX].led_off = iwl3945_led_associated; |
378 | priv->led[IWL_LED_TRG_TX].led_pattern = iwl3945_led_pattern; | 379 | priv->led[IWL_LED_TRG_TX].led_pattern = iwl3945_led_pattern; |
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-led.h b/drivers/net/wireless/iwlwifi/iwl-3945-led.h index 47b7e0bac802..2fbd126c1347 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945-led.h +++ b/drivers/net/wireless/iwlwifi/iwl-3945-led.h | |||
@@ -50,6 +50,7 @@ enum led_type { | |||
50 | struct iwl3945_led { | 50 | struct iwl3945_led { |
51 | struct iwl3945_priv *priv; | 51 | struct iwl3945_priv *priv; |
52 | struct led_classdev led_dev; | 52 | struct led_classdev led_dev; |
53 | char name[32]; | ||
53 | 54 | ||
54 | int (*led_on) (struct iwl3945_priv *priv, int led_id); | 55 | int (*led_on) (struct iwl3945_priv *priv, int led_id); |
55 | int (*led_off) (struct iwl3945_priv *priv, int led_id); | 56 | int (*led_off) (struct iwl3945_priv *priv, int led_id); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c index a51e0eaa1334..b3931f6135a4 100644 --- a/drivers/net/wireless/iwlwifi/iwl-3945.c +++ b/drivers/net/wireless/iwlwifi/iwl-3945.c | |||
@@ -710,10 +710,7 @@ static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv, | |||
710 | return; | 710 | return; |
711 | } | 711 | } |
712 | 712 | ||
713 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | 713 | |
714 | iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status); | ||
715 | return; | ||
716 | } | ||
717 | 714 | ||
718 | /* Convert 3945's rssi indicator to dBm */ | 715 | /* Convert 3945's rssi indicator to dBm */ |
719 | rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET; | 716 | rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET; |
@@ -775,6 +772,11 @@ static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv, | |||
775 | priv->last_rx_noise = rx_status.noise; | 772 | priv->last_rx_noise = rx_status.noise; |
776 | } | 773 | } |
777 | 774 | ||
775 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | ||
776 | iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status); | ||
777 | return; | ||
778 | } | ||
779 | |||
778 | switch (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FTYPE) { | 780 | switch (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FTYPE) { |
779 | case IEEE80211_FTYPE_MGMT: | 781 | case IEEE80211_FTYPE_MGMT: |
780 | switch (le16_to_cpu(header->frame_control) & | 782 | switch (le16_to_cpu(header->frame_control) & |
@@ -793,8 +795,7 @@ static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv, | |||
793 | struct ieee80211_mgmt *mgmt = | 795 | struct ieee80211_mgmt *mgmt = |
794 | (struct ieee80211_mgmt *)header; | 796 | (struct ieee80211_mgmt *)header; |
795 | __le32 *pos; | 797 | __le32 *pos; |
796 | pos = | 798 | pos = (__le32 *)&mgmt->u.beacon. |
797 | (__le32 *) & mgmt->u.beacon. | ||
798 | timestamp; | 799 | timestamp; |
799 | priv->timestamp0 = le32_to_cpu(pos[0]); | 800 | priv->timestamp0 = le32_to_cpu(pos[0]); |
800 | priv->timestamp1 = le32_to_cpu(pos[1]); | 801 | priv->timestamp1 = le32_to_cpu(pos[1]); |
@@ -1507,7 +1508,7 @@ static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading) | |||
1507 | */ | 1508 | */ |
1508 | static inline int iwl3945_hw_reg_temp_out_of_range(int temperature) | 1509 | static inline int iwl3945_hw_reg_temp_out_of_range(int temperature) |
1509 | { | 1510 | { |
1510 | return (((temperature < -260) || (temperature > 25)) ? 1 : 0); | 1511 | return ((temperature < -260) || (temperature > 25)) ? 1 : 0; |
1511 | } | 1512 | } |
1512 | 1513 | ||
1513 | int iwl3945_hw_get_temperature(struct iwl3945_priv *priv) | 1514 | int iwl3945_hw_get_temperature(struct iwl3945_priv *priv) |
@@ -2628,7 +2629,7 @@ unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv, | |||
2628 | tx_beacon_cmd->tx.supp_rates[1] = | 2629 | tx_beacon_cmd->tx.supp_rates[1] = |
2629 | (IWL_CCK_BASIC_RATES_MASK & 0xF); | 2630 | (IWL_CCK_BASIC_RATES_MASK & 0xF); |
2630 | 2631 | ||
2631 | return (sizeof(struct iwl3945_tx_beacon_cmd) + frame_size); | 2632 | return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size; |
2632 | } | 2633 | } |
2633 | 2634 | ||
2634 | void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv) | 2635 | void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv) |
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c index ba2df1ba32d2..22bb26985c2e 100644 --- a/drivers/net/wireless/iwlwifi/iwl-4965.c +++ b/drivers/net/wireless/iwlwifi/iwl-4965.c | |||
@@ -341,39 +341,6 @@ err: | |||
341 | return -EINVAL; | 341 | return -EINVAL; |
342 | 342 | ||
343 | } | 343 | } |
344 | int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) | ||
345 | { | ||
346 | int ret; | ||
347 | unsigned long flags; | ||
348 | |||
349 | spin_lock_irqsave(&priv->lock, flags); | ||
350 | ret = iwl_grab_nic_access(priv); | ||
351 | if (ret) { | ||
352 | spin_unlock_irqrestore(&priv->lock, flags); | ||
353 | return ret; | ||
354 | } | ||
355 | |||
356 | if (src == IWL_PWR_SRC_VAUX) { | ||
357 | u32 val; | ||
358 | ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE, | ||
359 | &val); | ||
360 | |||
361 | if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) { | ||
362 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | ||
363 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | ||
364 | ~APMG_PS_CTRL_MSK_PWR_SRC); | ||
365 | } | ||
366 | } else { | ||
367 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | ||
368 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | ||
369 | ~APMG_PS_CTRL_MSK_PWR_SRC); | ||
370 | } | ||
371 | |||
372 | iwl_release_nic_access(priv); | ||
373 | spin_unlock_irqrestore(&priv->lock, flags); | ||
374 | |||
375 | return ret; | ||
376 | } | ||
377 | 344 | ||
378 | /* | 345 | /* |
379 | * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask | 346 | * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask |
@@ -875,18 +842,6 @@ static int iwl4965_hw_set_hw_params(struct iwl_priv *priv) | |||
875 | return 0; | 842 | return 0; |
876 | } | 843 | } |
877 | 844 | ||
878 | /* set card power command */ | ||
879 | static int iwl4965_set_power(struct iwl_priv *priv, | ||
880 | void *cmd) | ||
881 | { | ||
882 | int ret = 0; | ||
883 | |||
884 | ret = iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD, | ||
885 | sizeof(struct iwl4965_powertable_cmd), | ||
886 | cmd, NULL); | ||
887 | return ret; | ||
888 | } | ||
889 | |||
890 | static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res) | 845 | static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res) |
891 | { | 846 | { |
892 | s32 sign = 1; | 847 | s32 sign = 1; |
@@ -1560,11 +1515,11 @@ static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel, | |||
1560 | c, atten_value, power_index, | 1515 | c, atten_value, power_index, |
1561 | tx_power.s.radio_tx_gain[c], | 1516 | tx_power.s.radio_tx_gain[c], |
1562 | tx_power.s.dsp_predis_atten[c]); | 1517 | tx_power.s.dsp_predis_atten[c]); |
1563 | }/* for each chain */ | 1518 | } /* for each chain */ |
1564 | 1519 | ||
1565 | tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw); | 1520 | tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw); |
1566 | 1521 | ||
1567 | }/* for each rate */ | 1522 | } /* for each rate */ |
1568 | 1523 | ||
1569 | return 0; | 1524 | return 0; |
1570 | } | 1525 | } |
@@ -1701,38 +1656,6 @@ static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv) | |||
1701 | return le32_to_cpu(s->rb_closed) & 0xFFF; | 1656 | return le32_to_cpu(s->rb_closed) & 0xFFF; |
1702 | } | 1657 | } |
1703 | 1658 | ||
1704 | unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv, | ||
1705 | struct iwl_frame *frame, u8 rate) | ||
1706 | { | ||
1707 | struct iwl4965_tx_beacon_cmd *tx_beacon_cmd; | ||
1708 | unsigned int frame_size; | ||
1709 | |||
1710 | tx_beacon_cmd = &frame->u.beacon; | ||
1711 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | ||
1712 | |||
1713 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; | ||
1714 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | ||
1715 | |||
1716 | frame_size = iwl4965_fill_beacon_frame(priv, | ||
1717 | tx_beacon_cmd->frame, | ||
1718 | iwl_bcast_addr, | ||
1719 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); | ||
1720 | |||
1721 | BUG_ON(frame_size > MAX_MPDU_SIZE); | ||
1722 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); | ||
1723 | |||
1724 | if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP)) | ||
1725 | tx_beacon_cmd->tx.rate_n_flags = | ||
1726 | iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK); | ||
1727 | else | ||
1728 | tx_beacon_cmd->tx.rate_n_flags = | ||
1729 | iwl_hw_set_rate_n_flags(rate, 0); | ||
1730 | |||
1731 | tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK | | ||
1732 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK); | ||
1733 | return (sizeof(*tx_beacon_cmd) + frame_size); | ||
1734 | } | ||
1735 | |||
1736 | static int iwl4965_alloc_shared_mem(struct iwl_priv *priv) | 1659 | static int iwl4965_alloc_shared_mem(struct iwl_priv *priv) |
1737 | { | 1660 | { |
1738 | priv->shared_virt = pci_alloc_consistent(priv->pci_dev, | 1661 | priv->shared_virt = pci_alloc_consistent(priv->pci_dev, |
@@ -2079,39 +2002,6 @@ static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id, | |||
2079 | return 0; | 2002 | return 0; |
2080 | } | 2003 | } |
2081 | 2004 | ||
2082 | int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw, | ||
2083 | enum ieee80211_ampdu_mlme_action action, | ||
2084 | const u8 *addr, u16 tid, u16 *ssn) | ||
2085 | { | ||
2086 | struct iwl_priv *priv = hw->priv; | ||
2087 | DECLARE_MAC_BUF(mac); | ||
2088 | |||
2089 | IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n", | ||
2090 | print_mac(mac, addr), tid); | ||
2091 | |||
2092 | if (!(priv->cfg->sku & IWL_SKU_N)) | ||
2093 | return -EACCES; | ||
2094 | |||
2095 | switch (action) { | ||
2096 | case IEEE80211_AMPDU_RX_START: | ||
2097 | IWL_DEBUG_HT("start Rx\n"); | ||
2098 | return iwl_rx_agg_start(priv, addr, tid, *ssn); | ||
2099 | case IEEE80211_AMPDU_RX_STOP: | ||
2100 | IWL_DEBUG_HT("stop Rx\n"); | ||
2101 | return iwl_rx_agg_stop(priv, addr, tid); | ||
2102 | case IEEE80211_AMPDU_TX_START: | ||
2103 | IWL_DEBUG_HT("start Tx\n"); | ||
2104 | return iwl_tx_agg_start(priv, addr, tid, ssn); | ||
2105 | case IEEE80211_AMPDU_TX_STOP: | ||
2106 | IWL_DEBUG_HT("stop Tx\n"); | ||
2107 | return iwl_tx_agg_stop(priv, addr, tid); | ||
2108 | default: | ||
2109 | IWL_DEBUG_HT("unknown\n"); | ||
2110 | return -EINVAL; | ||
2111 | break; | ||
2112 | } | ||
2113 | return 0; | ||
2114 | } | ||
2115 | 2005 | ||
2116 | static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len) | 2006 | static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len) |
2117 | { | 2007 | { |
@@ -2240,9 +2130,9 @@ static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv, | |||
2240 | bitmap = bitmap << sh; | 2130 | bitmap = bitmap << sh; |
2241 | sh = 0; | 2131 | sh = 0; |
2242 | } | 2132 | } |
2243 | bitmap |= (1 << sh); | 2133 | bitmap |= 1ULL << sh; |
2244 | IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n", | 2134 | IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n", |
2245 | start, (u32)(bitmap & 0xFFFFFFFF)); | 2135 | start, (unsigned long long)bitmap); |
2246 | } | 2136 | } |
2247 | 2137 | ||
2248 | agg->bitmap = bitmap; | 2138 | agg->bitmap = bitmap; |
@@ -2368,6 +2258,40 @@ static void iwl4965_rx_reply_tx(struct iwl_priv *priv, | |||
2368 | IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); | 2258 | IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); |
2369 | } | 2259 | } |
2370 | 2260 | ||
2261 | static int iwl4965_calc_rssi(struct iwl_priv *priv, | ||
2262 | struct iwl_rx_phy_res *rx_resp) | ||
2263 | { | ||
2264 | /* data from PHY/DSP regarding signal strength, etc., | ||
2265 | * contents are always there, not configurable by host. */ | ||
2266 | struct iwl4965_rx_non_cfg_phy *ncphy = | ||
2267 | (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf; | ||
2268 | u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK) | ||
2269 | >> IWL49_AGC_DB_POS; | ||
2270 | |||
2271 | u32 valid_antennae = | ||
2272 | (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK) | ||
2273 | >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET; | ||
2274 | u8 max_rssi = 0; | ||
2275 | u32 i; | ||
2276 | |||
2277 | /* Find max rssi among 3 possible receivers. | ||
2278 | * These values are measured by the digital signal processor (DSP). | ||
2279 | * They should stay fairly constant even as the signal strength varies, | ||
2280 | * if the radio's automatic gain control (AGC) is working right. | ||
2281 | * AGC value (see below) will provide the "interesting" info. */ | ||
2282 | for (i = 0; i < 3; i++) | ||
2283 | if (valid_antennae & (1 << i)) | ||
2284 | max_rssi = max(ncphy->rssi_info[i << 1], max_rssi); | ||
2285 | |||
2286 | IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", | ||
2287 | ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4], | ||
2288 | max_rssi, agc); | ||
2289 | |||
2290 | /* dBm = max_rssi dB - agc dB - constant. | ||
2291 | * Higher AGC (higher radio gain) means lower signal. */ | ||
2292 | return max_rssi - agc - IWL_RSSI_OFFSET; | ||
2293 | } | ||
2294 | |||
2371 | 2295 | ||
2372 | /* Set up 4965-specific Rx frame reply handlers */ | 2296 | /* Set up 4965-specific Rx frame reply handlers */ |
2373 | static void iwl4965_rx_handler_setup(struct iwl_priv *priv) | 2297 | static void iwl4965_rx_handler_setup(struct iwl_priv *priv) |
@@ -2399,6 +2323,7 @@ static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = { | |||
2399 | .chain_noise_reset = iwl4965_chain_noise_reset, | 2323 | .chain_noise_reset = iwl4965_chain_noise_reset, |
2400 | .gain_computation = iwl4965_gain_computation, | 2324 | .gain_computation = iwl4965_gain_computation, |
2401 | .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag, | 2325 | .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag, |
2326 | .calc_rssi = iwl4965_calc_rssi, | ||
2402 | }; | 2327 | }; |
2403 | 2328 | ||
2404 | static struct iwl_lib_ops iwl4965_lib = { | 2329 | static struct iwl_lib_ops iwl4965_lib = { |
@@ -2440,7 +2365,6 @@ static struct iwl_lib_ops iwl4965_lib = { | |||
2440 | .check_version = iwl4965_eeprom_check_version, | 2365 | .check_version = iwl4965_eeprom_check_version, |
2441 | .query_addr = iwlcore_eeprom_query_addr, | 2366 | .query_addr = iwlcore_eeprom_query_addr, |
2442 | }, | 2367 | }, |
2443 | .set_power = iwl4965_set_power, | ||
2444 | .send_tx_power = iwl4965_send_tx_power, | 2368 | .send_tx_power = iwl4965_send_tx_power, |
2445 | .update_chain_flags = iwl4965_update_chain_flags, | 2369 | .update_chain_flags = iwl4965_update_chain_flags, |
2446 | .temperature = iwl4965_temperature_calib, | 2370 | .temperature = iwl4965_temperature_calib, |
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c index 878d6193b232..f3d139b663e6 100644 --- a/drivers/net/wireless/iwlwifi/iwl-5000.c +++ b/drivers/net/wireless/iwlwifi/iwl-5000.c | |||
@@ -93,6 +93,13 @@ static int iwl5000_apm_init(struct iwl_priv *priv) | |||
93 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | 93 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
94 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | 94 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
95 | 95 | ||
96 | /* Set FH wait treshold to maximum (HW error during stress W/A) */ | ||
97 | iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | ||
98 | |||
99 | /* enable HAP INTA to move device L1a -> L0s */ | ||
100 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | ||
101 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | ||
102 | |||
96 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); | 103 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); |
97 | 104 | ||
98 | /* set "initialization complete" bit to move adapter | 105 | /* set "initialization complete" bit to move adapter |
@@ -230,6 +237,16 @@ static void iwl5000_nic_config(struct iwl_priv *priv) | |||
230 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | | 237 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | |
231 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); | 238 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); |
232 | 239 | ||
240 | /* W/A : NIC is stuck in a reset state after Early PCIe power off | ||
241 | * (PCIe power is lost before PERST# is asserted), | ||
242 | * causing ME FW to lose ownership and not being able to obtain it back. | ||
243 | */ | ||
244 | iwl_grab_nic_access(priv); | ||
245 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | ||
246 | APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, | ||
247 | ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); | ||
248 | iwl_release_nic_access(priv); | ||
249 | |||
233 | spin_unlock_irqrestore(&priv->lock, flags); | 250 | spin_unlock_irqrestore(&priv->lock, flags); |
234 | } | 251 | } |
235 | 252 | ||
@@ -924,8 +941,8 @@ static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, | |||
924 | len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | 941 | len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; |
925 | 942 | ||
926 | if (txq_id != IWL_CMD_QUEUE_NUM) { | 943 | if (txq_id != IWL_CMD_QUEUE_NUM) { |
927 | sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id; | 944 | sta = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; |
928 | sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl; | 945 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; |
929 | 946 | ||
930 | switch (sec_ctl & TX_CMD_SEC_MSK) { | 947 | switch (sec_ctl & TX_CMD_SEC_MSK) { |
931 | case TX_CMD_SEC_CCM: | 948 | case TX_CMD_SEC_CCM: |
@@ -964,7 +981,7 @@ static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, | |||
964 | u8 sta = 0; | 981 | u8 sta = 0; |
965 | 982 | ||
966 | if (txq_id != IWL_CMD_QUEUE_NUM) | 983 | if (txq_id != IWL_CMD_QUEUE_NUM) |
967 | sta = txq->cmd[txq->q.read_ptr].cmd.tx.sta_id; | 984 | sta = txq->cmd[txq->q.read_ptr]->cmd.tx.sta_id; |
968 | 985 | ||
969 | shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr]. | 986 | shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr]. |
970 | val = cpu_to_le16(1 | (sta << 12)); | 987 | val = cpu_to_le16(1 | (sta << 12)); |
@@ -1131,7 +1148,7 @@ static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) | |||
1131 | 1148 | ||
1132 | static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) | 1149 | static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) |
1133 | { | 1150 | { |
1134 | return le32_to_cpup((__le32*)&tx_resp->status + | 1151 | return le32_to_cpup((__le32 *)&tx_resp->status + |
1135 | tx_resp->frame_count) & MAX_SN; | 1152 | tx_resp->frame_count) & MAX_SN; |
1136 | } | 1153 | } |
1137 | 1154 | ||
@@ -1228,9 +1245,9 @@ static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, | |||
1228 | bitmap = bitmap << sh; | 1245 | bitmap = bitmap << sh; |
1229 | sh = 0; | 1246 | sh = 0; |
1230 | } | 1247 | } |
1231 | bitmap |= (1 << sh); | 1248 | bitmap |= 1ULL << sh; |
1232 | IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n", | 1249 | IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n", |
1233 | start, (u32)(bitmap & 0xFFFFFFFF)); | 1250 | start, (unsigned long long)bitmap); |
1234 | } | 1251 | } |
1235 | 1252 | ||
1236 | agg->bitmap = bitmap; | 1253 | agg->bitmap = bitmap; |
@@ -1444,6 +1461,44 @@ static void iwl5000_temperature(struct iwl_priv *priv) | |||
1444 | priv->temperature = le32_to_cpu(priv->statistics.general.temperature); | 1461 | priv->temperature = le32_to_cpu(priv->statistics.general.temperature); |
1445 | } | 1462 | } |
1446 | 1463 | ||
1464 | /* Calc max signal level (dBm) among 3 possible receivers */ | ||
1465 | static int iwl5000_calc_rssi(struct iwl_priv *priv, | ||
1466 | struct iwl_rx_phy_res *rx_resp) | ||
1467 | { | ||
1468 | /* data from PHY/DSP regarding signal strength, etc., | ||
1469 | * contents are always there, not configurable by host | ||
1470 | */ | ||
1471 | struct iwl5000_non_cfg_phy *ncphy = | ||
1472 | (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; | ||
1473 | u32 val, rssi_a, rssi_b, rssi_c, max_rssi; | ||
1474 | u8 agc; | ||
1475 | |||
1476 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); | ||
1477 | agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; | ||
1478 | |||
1479 | /* Find max rssi among 3 possible receivers. | ||
1480 | * These values are measured by the digital signal processor (DSP). | ||
1481 | * They should stay fairly constant even as the signal strength varies, | ||
1482 | * if the radio's automatic gain control (AGC) is working right. | ||
1483 | * AGC value (see below) will provide the "interesting" info. | ||
1484 | */ | ||
1485 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); | ||
1486 | rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; | ||
1487 | rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; | ||
1488 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); | ||
1489 | rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; | ||
1490 | |||
1491 | max_rssi = max_t(u32, rssi_a, rssi_b); | ||
1492 | max_rssi = max_t(u32, max_rssi, rssi_c); | ||
1493 | |||
1494 | IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", | ||
1495 | rssi_a, rssi_b, rssi_c, max_rssi, agc); | ||
1496 | |||
1497 | /* dBm = max_rssi dB - agc dB - constant. | ||
1498 | * Higher AGC (higher radio gain) means lower signal. */ | ||
1499 | return max_rssi - agc - IWL_RSSI_OFFSET; | ||
1500 | } | ||
1501 | |||
1447 | static struct iwl_hcmd_ops iwl5000_hcmd = { | 1502 | static struct iwl_hcmd_ops iwl5000_hcmd = { |
1448 | .rxon_assoc = iwl5000_send_rxon_assoc, | 1503 | .rxon_assoc = iwl5000_send_rxon_assoc, |
1449 | }; | 1504 | }; |
@@ -1454,6 +1509,7 @@ static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { | |||
1454 | .gain_computation = iwl5000_gain_computation, | 1509 | .gain_computation = iwl5000_gain_computation, |
1455 | .chain_noise_reset = iwl5000_chain_noise_reset, | 1510 | .chain_noise_reset = iwl5000_chain_noise_reset, |
1456 | .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, | 1511 | .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, |
1512 | .calc_rssi = iwl5000_calc_rssi, | ||
1457 | }; | 1513 | }; |
1458 | 1514 | ||
1459 | static struct iwl_lib_ops iwl5000_lib = { | 1515 | static struct iwl_lib_ops iwl5000_lib = { |
@@ -1474,6 +1530,7 @@ static struct iwl_lib_ops iwl5000_lib = { | |||
1474 | .alive_notify = iwl5000_alive_notify, | 1530 | .alive_notify = iwl5000_alive_notify, |
1475 | .send_tx_power = iwl5000_send_tx_power, | 1531 | .send_tx_power = iwl5000_send_tx_power, |
1476 | .temperature = iwl5000_temperature, | 1532 | .temperature = iwl5000_temperature, |
1533 | .update_chain_flags = iwl4965_update_chain_flags, | ||
1477 | .apm_ops = { | 1534 | .apm_ops = { |
1478 | .init = iwl5000_apm_init, | 1535 | .init = iwl5000_apm_init, |
1479 | .reset = iwl5000_apm_reset, | 1536 | .reset = iwl5000_apm_reset, |
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-rs.c b/drivers/net/wireless/iwlwifi/iwl-agn-rs.c index 3ccb84aa5dbc..754fef5b592f 100644 --- a/drivers/net/wireless/iwlwifi/iwl-4965-rs.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn-rs.c | |||
@@ -42,7 +42,7 @@ | |||
42 | #include "iwl-core.h" | 42 | #include "iwl-core.h" |
43 | #include "iwl-helpers.h" | 43 | #include "iwl-helpers.h" |
44 | 44 | ||
45 | #define RS_NAME "iwl-4965-rs" | 45 | #define RS_NAME "iwl-agn-rs" |
46 | 46 | ||
47 | #define NUM_TRY_BEFORE_ANT_TOGGLE 1 | 47 | #define NUM_TRY_BEFORE_ANT_TOGGLE 1 |
48 | #define IWL_NUMBER_TRY 1 | 48 | #define IWL_NUMBER_TRY 1 |
@@ -77,9 +77,9 @@ static const u8 ant_toggle_lookup[] = { | |||
77 | }; | 77 | }; |
78 | 78 | ||
79 | /** | 79 | /** |
80 | * struct iwl4965_rate_scale_data -- tx success history for one rate | 80 | * struct iwl_rate_scale_data -- tx success history for one rate |
81 | */ | 81 | */ |
82 | struct iwl4965_rate_scale_data { | 82 | struct iwl_rate_scale_data { |
83 | u64 data; /* bitmap of successful frames */ | 83 | u64 data; /* bitmap of successful frames */ |
84 | s32 success_counter; /* number of frames successful */ | 84 | s32 success_counter; /* number of frames successful */ |
85 | s32 success_ratio; /* per-cent * 128 */ | 85 | s32 success_ratio; /* per-cent * 128 */ |
@@ -89,12 +89,12 @@ struct iwl4965_rate_scale_data { | |||
89 | }; | 89 | }; |
90 | 90 | ||
91 | /** | 91 | /** |
92 | * struct iwl4965_scale_tbl_info -- tx params and success history for all rates | 92 | * struct iwl_scale_tbl_info -- tx params and success history for all rates |
93 | * | 93 | * |
94 | * There are two of these in struct iwl4965_lq_sta, | 94 | * There are two of these in struct iwl_lq_sta, |
95 | * one for "active", and one for "search". | 95 | * one for "active", and one for "search". |
96 | */ | 96 | */ |
97 | struct iwl4965_scale_tbl_info { | 97 | struct iwl_scale_tbl_info { |
98 | enum iwl_table_type lq_type; | 98 | enum iwl_table_type lq_type; |
99 | u8 ant_type; | 99 | u8 ant_type; |
100 | u8 is_SGI; /* 1 = short guard interval */ | 100 | u8 is_SGI; /* 1 = short guard interval */ |
@@ -103,10 +103,10 @@ struct iwl4965_scale_tbl_info { | |||
103 | u8 action; /* change modulation; IWL_[LEGACY/SISO/MIMO]_SWITCH_* */ | 103 | u8 action; /* change modulation; IWL_[LEGACY/SISO/MIMO]_SWITCH_* */ |
104 | s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */ | 104 | s32 *expected_tpt; /* throughput metrics; expected_tpt_G, etc. */ |
105 | u32 current_rate; /* rate_n_flags, uCode API format */ | 105 | u32 current_rate; /* rate_n_flags, uCode API format */ |
106 | struct iwl4965_rate_scale_data win[IWL_RATE_COUNT]; /* rate histories */ | 106 | struct iwl_rate_scale_data win[IWL_RATE_COUNT]; /* rate histories */ |
107 | }; | 107 | }; |
108 | 108 | ||
109 | struct iwl4965_traffic_load { | 109 | struct iwl_traffic_load { |
110 | unsigned long time_stamp; /* age of the oldest statistics */ | 110 | unsigned long time_stamp; /* age of the oldest statistics */ |
111 | u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time | 111 | u32 packet_count[TID_QUEUE_MAX_SIZE]; /* packet count in this time |
112 | * slice */ | 112 | * slice */ |
@@ -118,11 +118,11 @@ struct iwl4965_traffic_load { | |||
118 | }; | 118 | }; |
119 | 119 | ||
120 | /** | 120 | /** |
121 | * struct iwl4965_lq_sta -- driver's rate scaling private structure | 121 | * struct iwl_lq_sta -- driver's rate scaling private structure |
122 | * | 122 | * |
123 | * Pointer to this gets passed back and forth between driver and mac80211. | 123 | * Pointer to this gets passed back and forth between driver and mac80211. |
124 | */ | 124 | */ |
125 | struct iwl4965_lq_sta { | 125 | struct iwl_lq_sta { |
126 | u8 active_tbl; /* index of active table, range 0-1 */ | 126 | u8 active_tbl; /* index of active table, range 0-1 */ |
127 | u8 enable_counter; /* indicates HT mode */ | 127 | u8 enable_counter; /* indicates HT mode */ |
128 | u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */ | 128 | u8 stay_in_tbl; /* 1: disallow, 0: allow search for new mode */ |
@@ -153,8 +153,8 @@ struct iwl4965_lq_sta { | |||
153 | u16 active_rate_basic; | 153 | u16 active_rate_basic; |
154 | 154 | ||
155 | struct iwl_link_quality_cmd lq; | 155 | struct iwl_link_quality_cmd lq; |
156 | struct iwl4965_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */ | 156 | struct iwl_scale_tbl_info lq_info[LQ_SIZE]; /* "active", "search" */ |
157 | struct iwl4965_traffic_load load[TID_MAX_LOAD_COUNT]; | 157 | struct iwl_traffic_load load[TID_MAX_LOAD_COUNT]; |
158 | u8 tx_agg_tid_en; | 158 | u8 tx_agg_tid_en; |
159 | #ifdef CONFIG_MAC80211_DEBUGFS | 159 | #ifdef CONFIG_MAC80211_DEBUGFS |
160 | struct dentry *rs_sta_dbgfs_scale_table_file; | 160 | struct dentry *rs_sta_dbgfs_scale_table_file; |
@@ -170,16 +170,15 @@ static void rs_rate_scale_perform(struct iwl_priv *priv, | |||
170 | struct ieee80211_hdr *hdr, | 170 | struct ieee80211_hdr *hdr, |
171 | struct sta_info *sta); | 171 | struct sta_info *sta); |
172 | static void rs_fill_link_cmd(const struct iwl_priv *priv, | 172 | static void rs_fill_link_cmd(const struct iwl_priv *priv, |
173 | struct iwl4965_lq_sta *lq_sta, | 173 | struct iwl_lq_sta *lq_sta, u32 rate_n_flags); |
174 | u32 rate_n_flags); | ||
175 | 174 | ||
176 | 175 | ||
177 | #ifdef CONFIG_MAC80211_DEBUGFS | 176 | #ifdef CONFIG_MAC80211_DEBUGFS |
178 | static void rs_dbgfs_set_mcs(struct iwl4965_lq_sta *lq_sta, | 177 | static void rs_dbgfs_set_mcs(struct iwl_lq_sta *lq_sta, |
179 | u32 *rate_n_flags, int index); | 178 | u32 *rate_n_flags, int index); |
180 | #else | 179 | #else |
181 | static void rs_dbgfs_set_mcs(struct iwl4965_lq_sta *lq_sta, | 180 | static void rs_dbgfs_set_mcs(struct iwl_lq_sta *lq_sta, |
182 | u32 *rate_n_flags, int index) | 181 | u32 *rate_n_flags, int index) |
183 | {} | 182 | {} |
184 | #endif | 183 | #endif |
185 | 184 | ||
@@ -234,7 +233,7 @@ static inline u8 rs_extract_rate(u32 rate_n_flags) | |||
234 | return (u8)(rate_n_flags & 0xFF); | 233 | return (u8)(rate_n_flags & 0xFF); |
235 | } | 234 | } |
236 | 235 | ||
237 | static void rs_rate_scale_clear_window(struct iwl4965_rate_scale_data *window) | 236 | static void rs_rate_scale_clear_window(struct iwl_rate_scale_data *window) |
238 | { | 237 | { |
239 | window->data = 0; | 238 | window->data = 0; |
240 | window->success_counter = 0; | 239 | window->success_counter = 0; |
@@ -246,14 +245,14 @@ static void rs_rate_scale_clear_window(struct iwl4965_rate_scale_data *window) | |||
246 | 245 | ||
247 | static inline u8 rs_is_valid_ant(u8 valid_antenna, u8 ant_type) | 246 | static inline u8 rs_is_valid_ant(u8 valid_antenna, u8 ant_type) |
248 | { | 247 | { |
249 | return ((ant_type & valid_antenna) == ant_type); | 248 | return (ant_type & valid_antenna) == ant_type; |
250 | } | 249 | } |
251 | 250 | ||
252 | /* | 251 | /* |
253 | * removes the old data from the statistics. All data that is older than | 252 | * removes the old data from the statistics. All data that is older than |
254 | * TID_MAX_TIME_DIFF, will be deleted. | 253 | * TID_MAX_TIME_DIFF, will be deleted. |
255 | */ | 254 | */ |
256 | static void rs_tl_rm_old_stats(struct iwl4965_traffic_load *tl, u32 curr_time) | 255 | static void rs_tl_rm_old_stats(struct iwl_traffic_load *tl, u32 curr_time) |
257 | { | 256 | { |
258 | /* The oldest age we want to keep */ | 257 | /* The oldest age we want to keep */ |
259 | u32 oldest_time = curr_time - TID_MAX_TIME_DIFF; | 258 | u32 oldest_time = curr_time - TID_MAX_TIME_DIFF; |
@@ -274,13 +273,13 @@ static void rs_tl_rm_old_stats(struct iwl4965_traffic_load *tl, u32 curr_time) | |||
274 | * increment traffic load value for tid and also remove | 273 | * increment traffic load value for tid and also remove |
275 | * any old values if passed the certain time period | 274 | * any old values if passed the certain time period |
276 | */ | 275 | */ |
277 | static u8 rs_tl_add_packet(struct iwl4965_lq_sta *lq_data, | 276 | static u8 rs_tl_add_packet(struct iwl_lq_sta *lq_data, |
278 | struct ieee80211_hdr *hdr) | 277 | struct ieee80211_hdr *hdr) |
279 | { | 278 | { |
280 | u32 curr_time = jiffies_to_msecs(jiffies); | 279 | u32 curr_time = jiffies_to_msecs(jiffies); |
281 | u32 time_diff; | 280 | u32 time_diff; |
282 | s32 index; | 281 | s32 index; |
283 | struct iwl4965_traffic_load *tl = NULL; | 282 | struct iwl_traffic_load *tl = NULL; |
284 | __le16 fc = hdr->frame_control; | 283 | __le16 fc = hdr->frame_control; |
285 | u8 tid; | 284 | u8 tid; |
286 | 285 | ||
@@ -325,12 +324,12 @@ static u8 rs_tl_add_packet(struct iwl4965_lq_sta *lq_data, | |||
325 | /* | 324 | /* |
326 | get the traffic load value for tid | 325 | get the traffic load value for tid |
327 | */ | 326 | */ |
328 | static u32 rs_tl_get_load(struct iwl4965_lq_sta *lq_data, u8 tid) | 327 | static u32 rs_tl_get_load(struct iwl_lq_sta *lq_data, u8 tid) |
329 | { | 328 | { |
330 | u32 curr_time = jiffies_to_msecs(jiffies); | 329 | u32 curr_time = jiffies_to_msecs(jiffies); |
331 | u32 time_diff; | 330 | u32 time_diff; |
332 | s32 index; | 331 | s32 index; |
333 | struct iwl4965_traffic_load *tl = NULL; | 332 | struct iwl_traffic_load *tl = NULL; |
334 | 333 | ||
335 | if (tid >= TID_MAX_LOAD_COUNT) | 334 | if (tid >= TID_MAX_LOAD_COUNT) |
336 | return 0; | 335 | return 0; |
@@ -354,8 +353,8 @@ static u32 rs_tl_get_load(struct iwl4965_lq_sta *lq_data, u8 tid) | |||
354 | } | 353 | } |
355 | 354 | ||
356 | static void rs_tl_turn_on_agg_for_tid(struct iwl_priv *priv, | 355 | static void rs_tl_turn_on_agg_for_tid(struct iwl_priv *priv, |
357 | struct iwl4965_lq_sta *lq_data, u8 tid, | 356 | struct iwl_lq_sta *lq_data, u8 tid, |
358 | struct sta_info *sta) | 357 | struct sta_info *sta) |
359 | { | 358 | { |
360 | unsigned long state; | 359 | unsigned long state; |
361 | DECLARE_MAC_BUF(mac); | 360 | DECLARE_MAC_BUF(mac); |
@@ -373,8 +372,8 @@ static void rs_tl_turn_on_agg_for_tid(struct iwl_priv *priv, | |||
373 | } | 372 | } |
374 | 373 | ||
375 | static void rs_tl_turn_on_agg(struct iwl_priv *priv, u8 tid, | 374 | static void rs_tl_turn_on_agg(struct iwl_priv *priv, u8 tid, |
376 | struct iwl4965_lq_sta *lq_data, | 375 | struct iwl_lq_sta *lq_data, |
377 | struct sta_info *sta) | 376 | struct sta_info *sta) |
378 | { | 377 | { |
379 | if ((tid < TID_MAX_LOAD_COUNT)) | 378 | if ((tid < TID_MAX_LOAD_COUNT)) |
380 | rs_tl_turn_on_agg_for_tid(priv, lq_data, tid, sta); | 379 | rs_tl_turn_on_agg_for_tid(priv, lq_data, tid, sta); |
@@ -385,9 +384,9 @@ static void rs_tl_turn_on_agg(struct iwl_priv *priv, u8 tid, | |||
385 | 384 | ||
386 | static inline int get_num_of_ant_from_rate(u32 rate_n_flags) | 385 | static inline int get_num_of_ant_from_rate(u32 rate_n_flags) |
387 | { | 386 | { |
388 | return (!!(rate_n_flags & RATE_MCS_ANT_A_MSK) + | 387 | return !!(rate_n_flags & RATE_MCS_ANT_A_MSK) + |
389 | !!(rate_n_flags & RATE_MCS_ANT_B_MSK) + | 388 | !!(rate_n_flags & RATE_MCS_ANT_B_MSK) + |
390 | !!(rate_n_flags & RATE_MCS_ANT_C_MSK)); | 389 | !!(rate_n_flags & RATE_MCS_ANT_C_MSK); |
391 | } | 390 | } |
392 | 391 | ||
393 | /** | 392 | /** |
@@ -397,11 +396,11 @@ static inline int get_num_of_ant_from_rate(u32 rate_n_flags) | |||
397 | * at this rate. window->data contains the bitmask of successful | 396 | * at this rate. window->data contains the bitmask of successful |
398 | * packets. | 397 | * packets. |
399 | */ | 398 | */ |
400 | static int rs_collect_tx_data(struct iwl4965_rate_scale_data *windows, | 399 | static int rs_collect_tx_data(struct iwl_rate_scale_data *windows, |
401 | int scale_index, s32 tpt, int retries, | 400 | int scale_index, s32 tpt, int retries, |
402 | int successes) | 401 | int successes) |
403 | { | 402 | { |
404 | struct iwl4965_rate_scale_data *window = NULL; | 403 | struct iwl_rate_scale_data *window = NULL; |
405 | static const u64 mask = (((u64)1) << (IWL_RATE_MAX_WINDOW - 1)); | 404 | static const u64 mask = (((u64)1) << (IWL_RATE_MAX_WINDOW - 1)); |
406 | s32 fail_count; | 405 | s32 fail_count; |
407 | 406 | ||
@@ -473,7 +472,7 @@ static int rs_collect_tx_data(struct iwl4965_rate_scale_data *windows, | |||
473 | * Fill uCode API rate_n_flags field, based on "search" or "active" table. | 472 | * Fill uCode API rate_n_flags field, based on "search" or "active" table. |
474 | */ | 473 | */ |
475 | /* FIXME:RS:remove this function and put the flags statically in the table */ | 474 | /* FIXME:RS:remove this function and put the flags statically in the table */ |
476 | static u32 rate_n_flags_from_tbl(struct iwl4965_scale_tbl_info *tbl, | 475 | static u32 rate_n_flags_from_tbl(struct iwl_scale_tbl_info *tbl, |
477 | int index, u8 use_green) | 476 | int index, u8 use_green) |
478 | { | 477 | { |
479 | u32 rate_n_flags = 0; | 478 | u32 rate_n_flags = 0; |
@@ -530,7 +529,7 @@ static u32 rate_n_flags_from_tbl(struct iwl4965_scale_tbl_info *tbl, | |||
530 | */ | 529 | */ |
531 | static int rs_get_tbl_info_from_mcs(const u32 rate_n_flags, | 530 | static int rs_get_tbl_info_from_mcs(const u32 rate_n_flags, |
532 | enum ieee80211_band band, | 531 | enum ieee80211_band band, |
533 | struct iwl4965_scale_tbl_info *tbl, | 532 | struct iwl_scale_tbl_info *tbl, |
534 | int *rate_idx) | 533 | int *rate_idx) |
535 | { | 534 | { |
536 | u32 ant_msk = (rate_n_flags & RATE_MCS_ANT_ABC_MSK); | 535 | u32 ant_msk = (rate_n_flags & RATE_MCS_ANT_ABC_MSK); |
@@ -591,7 +590,7 @@ static int rs_get_tbl_info_from_mcs(const u32 rate_n_flags, | |||
591 | /* switch to another antenna/antennas and return 1 */ | 590 | /* switch to another antenna/antennas and return 1 */ |
592 | /* if no other valid antenna found, return 0 */ | 591 | /* if no other valid antenna found, return 0 */ |
593 | static int rs_toggle_antenna(u32 valid_ant, u32 *rate_n_flags, | 592 | static int rs_toggle_antenna(u32 valid_ant, u32 *rate_n_flags, |
594 | struct iwl4965_scale_tbl_info *tbl) | 593 | struct iwl_scale_tbl_info *tbl) |
595 | { | 594 | { |
596 | u8 new_ant_type; | 595 | u8 new_ant_type; |
597 | 596 | ||
@@ -621,9 +620,9 @@ static int rs_toggle_antenna(u32 valid_ant, u32 *rate_n_flags, | |||
621 | #if 0 | 620 | #if 0 |
622 | static inline u8 rs_use_green(struct iwl_priv *priv, struct ieee80211_conf *conf) | 621 | static inline u8 rs_use_green(struct iwl_priv *priv, struct ieee80211_conf *conf) |
623 | { | 622 | { |
624 | return ((conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) && | 623 | return (conf->flags & IEEE80211_CONF_SUPPORT_HT_MODE) && |
625 | priv->current_ht_config.is_green_field && | 624 | priv->current_ht_config.is_green_field && |
626 | !priv->current_ht_config.non_GF_STA_present); | 625 | !priv->current_ht_config.non_GF_STA_present; |
627 | } | 626 | } |
628 | #endif | 627 | #endif |
629 | static inline u8 rs_use_green(struct iwl_priv *priv, struct ieee80211_conf *conf) | 628 | static inline u8 rs_use_green(struct iwl_priv *priv, struct ieee80211_conf *conf) |
@@ -638,9 +637,9 @@ static inline u8 rs_use_green(struct iwl_priv *priv, struct ieee80211_conf *conf | |||
638 | * basic available rates. | 637 | * basic available rates. |
639 | * | 638 | * |
640 | */ | 639 | */ |
641 | static u16 rs_get_supported_rates(struct iwl4965_lq_sta *lq_sta, | 640 | static u16 rs_get_supported_rates(struct iwl_lq_sta *lq_sta, |
642 | struct ieee80211_hdr *hdr, | 641 | struct ieee80211_hdr *hdr, |
643 | enum iwl_table_type rate_type) | 642 | enum iwl_table_type rate_type) |
644 | { | 643 | { |
645 | if (hdr && is_multicast_ether_addr(hdr->addr1) && | 644 | if (hdr && is_multicast_ether_addr(hdr->addr1) && |
646 | lq_sta->active_rate_basic) | 645 | lq_sta->active_rate_basic) |
@@ -714,9 +713,9 @@ static u16 rs_get_adjacent_rate(struct iwl_priv *priv, u8 index, u16 rate_mask, | |||
714 | return (high << 8) | low; | 713 | return (high << 8) | low; |
715 | } | 714 | } |
716 | 715 | ||
717 | static u32 rs_get_lower_rate(struct iwl4965_lq_sta *lq_sta, | 716 | static u32 rs_get_lower_rate(struct iwl_lq_sta *lq_sta, |
718 | struct iwl4965_scale_tbl_info *tbl, u8 scale_index, | 717 | struct iwl_scale_tbl_info *tbl, |
719 | u8 ht_possible) | 718 | u8 scale_index, u8 ht_possible) |
720 | { | 719 | { |
721 | s32 low; | 720 | s32 low; |
722 | u16 rate_mask; | 721 | u16 rate_mask; |
@@ -780,7 +779,7 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev, | |||
780 | int status; | 779 | int status; |
781 | u8 retries; | 780 | u8 retries; |
782 | int rs_index, index = 0; | 781 | int rs_index, index = 0; |
783 | struct iwl4965_lq_sta *lq_sta; | 782 | struct iwl_lq_sta *lq_sta; |
784 | struct iwl_link_quality_cmd *table; | 783 | struct iwl_link_quality_cmd *table; |
785 | struct sta_info *sta; | 784 | struct sta_info *sta; |
786 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | 785 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
@@ -788,11 +787,11 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev, | |||
788 | struct ieee80211_local *local = wdev_priv(dev->ieee80211_ptr); | 787 | struct ieee80211_local *local = wdev_priv(dev->ieee80211_ptr); |
789 | struct ieee80211_hw *hw = local_to_hw(local); | 788 | struct ieee80211_hw *hw = local_to_hw(local); |
790 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | 789 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
791 | struct iwl4965_rate_scale_data *window = NULL; | 790 | struct iwl_rate_scale_data *window = NULL; |
792 | struct iwl4965_rate_scale_data *search_win = NULL; | 791 | struct iwl_rate_scale_data *search_win = NULL; |
793 | u32 tx_rate; | 792 | u32 tx_rate; |
794 | struct iwl4965_scale_tbl_info tbl_type; | 793 | struct iwl_scale_tbl_info tbl_type; |
795 | struct iwl4965_scale_tbl_info *curr_tbl, *search_tbl; | 794 | struct iwl_scale_tbl_info *curr_tbl, *search_tbl; |
796 | u8 active_index = 0; | 795 | u8 active_index = 0; |
797 | __le16 fc = hdr->frame_control; | 796 | __le16 fc = hdr->frame_control; |
798 | s32 tpt = 0; | 797 | s32 tpt = 0; |
@@ -820,7 +819,7 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev, | |||
820 | goto out; | 819 | goto out; |
821 | 820 | ||
822 | 821 | ||
823 | lq_sta = (struct iwl4965_lq_sta *)sta->rate_ctrl_priv; | 822 | lq_sta = (struct iwl_lq_sta *)sta->rate_ctrl_priv; |
824 | 823 | ||
825 | if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && | 824 | if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && |
826 | !lq_sta->ibss_sta_added) | 825 | !lq_sta->ibss_sta_added) |
@@ -831,10 +830,8 @@ static void rs_tx_status(void *priv_rate, struct net_device *dev, | |||
831 | 830 | ||
832 | curr_tbl = &(lq_sta->lq_info[active_index]); | 831 | curr_tbl = &(lq_sta->lq_info[active_index]); |
833 | search_tbl = &(lq_sta->lq_info[(1 - active_index)]); | 832 | search_tbl = &(lq_sta->lq_info[(1 - active_index)]); |
834 | window = (struct iwl4965_rate_scale_data *) | 833 | window = (struct iwl_rate_scale_data *)&(curr_tbl->win[0]); |
835 | &(curr_tbl->win[0]); | 834 | search_win = (struct iwl_rate_scale_data *)&(search_tbl->win[0]); |
836 | search_win = (struct iwl4965_rate_scale_data *) | ||
837 | &(search_tbl->win[0]); | ||
838 | 835 | ||
839 | /* | 836 | /* |
840 | * Ignore this Tx frame response if its initial rate doesn't match | 837 | * Ignore this Tx frame response if its initial rate doesn't match |
@@ -983,7 +980,7 @@ out: | |||
983 | * searching for a new mode. | 980 | * searching for a new mode. |
984 | */ | 981 | */ |
985 | static void rs_set_stay_in_table(struct iwl_priv *priv, u8 is_legacy, | 982 | static void rs_set_stay_in_table(struct iwl_priv *priv, u8 is_legacy, |
986 | struct iwl4965_lq_sta *lq_sta) | 983 | struct iwl_lq_sta *lq_sta) |
987 | { | 984 | { |
988 | IWL_DEBUG_RATE("we are staying in the same table\n"); | 985 | IWL_DEBUG_RATE("we are staying in the same table\n"); |
989 | lq_sta->stay_in_tbl = 1; /* only place this gets set */ | 986 | lq_sta->stay_in_tbl = 1; /* only place this gets set */ |
@@ -1004,8 +1001,8 @@ static void rs_set_stay_in_table(struct iwl_priv *priv, u8 is_legacy, | |||
1004 | /* | 1001 | /* |
1005 | * Find correct throughput table for given mode of modulation | 1002 | * Find correct throughput table for given mode of modulation |
1006 | */ | 1003 | */ |
1007 | static void rs_set_expected_tpt_table(struct iwl4965_lq_sta *lq_sta, | 1004 | static void rs_set_expected_tpt_table(struct iwl_lq_sta *lq_sta, |
1008 | struct iwl4965_scale_tbl_info *tbl) | 1005 | struct iwl_scale_tbl_info *tbl) |
1009 | { | 1006 | { |
1010 | if (is_legacy(tbl->lq_type)) { | 1007 | if (is_legacy(tbl->lq_type)) { |
1011 | if (!is_a_band(tbl->lq_type)) | 1008 | if (!is_a_band(tbl->lq_type)) |
@@ -1050,12 +1047,12 @@ static void rs_set_expected_tpt_table(struct iwl4965_lq_sta *lq_sta, | |||
1050 | * bit rate will typically need to increase, but not if performance was bad. | 1047 | * bit rate will typically need to increase, but not if performance was bad. |
1051 | */ | 1048 | */ |
1052 | static s32 rs_get_best_rate(struct iwl_priv *priv, | 1049 | static s32 rs_get_best_rate(struct iwl_priv *priv, |
1053 | struct iwl4965_lq_sta *lq_sta, | 1050 | struct iwl_lq_sta *lq_sta, |
1054 | struct iwl4965_scale_tbl_info *tbl, /* "search" */ | 1051 | struct iwl_scale_tbl_info *tbl, /* "search" */ |
1055 | u16 rate_mask, s8 index) | 1052 | u16 rate_mask, s8 index) |
1056 | { | 1053 | { |
1057 | /* "active" values */ | 1054 | /* "active" values */ |
1058 | struct iwl4965_scale_tbl_info *active_tbl = | 1055 | struct iwl_scale_tbl_info *active_tbl = |
1059 | &(lq_sta->lq_info[lq_sta->active_tbl]); | 1056 | &(lq_sta->lq_info[lq_sta->active_tbl]); |
1060 | s32 active_sr = active_tbl->win[index].success_ratio; | 1057 | s32 active_sr = active_tbl->win[index].success_ratio; |
1061 | s32 active_tpt = active_tbl->expected_tpt[index]; | 1058 | s32 active_tpt = active_tbl->expected_tpt[index]; |
@@ -1143,10 +1140,10 @@ static s32 rs_get_best_rate(struct iwl_priv *priv, | |||
1143 | * Set up search table for MIMO | 1140 | * Set up search table for MIMO |
1144 | */ | 1141 | */ |
1145 | static int rs_switch_to_mimo2(struct iwl_priv *priv, | 1142 | static int rs_switch_to_mimo2(struct iwl_priv *priv, |
1146 | struct iwl4965_lq_sta *lq_sta, | 1143 | struct iwl_lq_sta *lq_sta, |
1147 | struct ieee80211_conf *conf, | 1144 | struct ieee80211_conf *conf, |
1148 | struct sta_info *sta, | 1145 | struct sta_info *sta, |
1149 | struct iwl4965_scale_tbl_info *tbl, int index) | 1146 | struct iwl_scale_tbl_info *tbl, int index) |
1150 | { | 1147 | { |
1151 | u16 rate_mask; | 1148 | u16 rate_mask; |
1152 | s32 rate; | 1149 | s32 rate; |
@@ -1210,10 +1207,10 @@ static int rs_switch_to_mimo2(struct iwl_priv *priv, | |||
1210 | * Set up search table for SISO | 1207 | * Set up search table for SISO |
1211 | */ | 1208 | */ |
1212 | static int rs_switch_to_siso(struct iwl_priv *priv, | 1209 | static int rs_switch_to_siso(struct iwl_priv *priv, |
1213 | struct iwl4965_lq_sta *lq_sta, | 1210 | struct iwl_lq_sta *lq_sta, |
1214 | struct ieee80211_conf *conf, | 1211 | struct ieee80211_conf *conf, |
1215 | struct sta_info *sta, | 1212 | struct sta_info *sta, |
1216 | struct iwl4965_scale_tbl_info *tbl, int index) | 1213 | struct iwl_scale_tbl_info *tbl, int index) |
1217 | { | 1214 | { |
1218 | u16 rate_mask; | 1215 | u16 rate_mask; |
1219 | u8 is_green = lq_sta->is_green; | 1216 | u8 is_green = lq_sta->is_green; |
@@ -1270,18 +1267,17 @@ static int rs_switch_to_siso(struct iwl_priv *priv, | |||
1270 | * Try to switch to new modulation mode from legacy | 1267 | * Try to switch to new modulation mode from legacy |
1271 | */ | 1268 | */ |
1272 | static int rs_move_legacy_other(struct iwl_priv *priv, | 1269 | static int rs_move_legacy_other(struct iwl_priv *priv, |
1273 | struct iwl4965_lq_sta *lq_sta, | 1270 | struct iwl_lq_sta *lq_sta, |
1274 | struct ieee80211_conf *conf, | 1271 | struct ieee80211_conf *conf, |
1275 | struct sta_info *sta, | 1272 | struct sta_info *sta, |
1276 | int index) | 1273 | int index) |
1277 | { | 1274 | { |
1278 | struct iwl4965_scale_tbl_info *tbl = | 1275 | struct iwl_scale_tbl_info *tbl = &(lq_sta->lq_info[lq_sta->active_tbl]); |
1279 | &(lq_sta->lq_info[lq_sta->active_tbl]); | 1276 | struct iwl_scale_tbl_info *search_tbl = |
1280 | struct iwl4965_scale_tbl_info *search_tbl = | 1277 | &(lq_sta->lq_info[(1 - lq_sta->active_tbl)]); |
1281 | &(lq_sta->lq_info[(1 - lq_sta->active_tbl)]); | 1278 | struct iwl_rate_scale_data *window = &(tbl->win[index]); |
1282 | struct iwl4965_rate_scale_data *window = &(tbl->win[index]); | 1279 | u32 sz = (sizeof(struct iwl_scale_tbl_info) - |
1283 | u32 sz = (sizeof(struct iwl4965_scale_tbl_info) - | 1280 | (sizeof(struct iwl_rate_scale_data) * IWL_RATE_COUNT)); |
1284 | (sizeof(struct iwl4965_rate_scale_data) * IWL_RATE_COUNT)); | ||
1285 | u8 start_action = tbl->action; | 1281 | u8 start_action = tbl->action; |
1286 | u8 valid_tx_ant = priv->hw_params.valid_tx_ant; | 1282 | u8 valid_tx_ant = priv->hw_params.valid_tx_ant; |
1287 | int ret = 0; | 1283 | int ret = 0; |
@@ -1360,19 +1356,17 @@ static int rs_move_legacy_other(struct iwl_priv *priv, | |||
1360 | * Try to switch to new modulation mode from SISO | 1356 | * Try to switch to new modulation mode from SISO |
1361 | */ | 1357 | */ |
1362 | static int rs_move_siso_to_other(struct iwl_priv *priv, | 1358 | static int rs_move_siso_to_other(struct iwl_priv *priv, |
1363 | struct iwl4965_lq_sta *lq_sta, | 1359 | struct iwl_lq_sta *lq_sta, |
1364 | struct ieee80211_conf *conf, | 1360 | struct ieee80211_conf *conf, |
1365 | struct sta_info *sta, | 1361 | struct sta_info *sta, int index) |
1366 | int index) | ||
1367 | { | 1362 | { |
1368 | u8 is_green = lq_sta->is_green; | 1363 | u8 is_green = lq_sta->is_green; |
1369 | struct iwl4965_scale_tbl_info *tbl = | 1364 | struct iwl_scale_tbl_info *tbl = &(lq_sta->lq_info[lq_sta->active_tbl]); |
1370 | &(lq_sta->lq_info[lq_sta->active_tbl]); | 1365 | struct iwl_scale_tbl_info *search_tbl = |
1371 | struct iwl4965_scale_tbl_info *search_tbl = | 1366 | &(lq_sta->lq_info[(1 - lq_sta->active_tbl)]); |
1372 | &(lq_sta->lq_info[(1 - lq_sta->active_tbl)]); | 1367 | struct iwl_rate_scale_data *window = &(tbl->win[index]); |
1373 | struct iwl4965_rate_scale_data *window = &(tbl->win[index]); | 1368 | u32 sz = (sizeof(struct iwl_scale_tbl_info) - |
1374 | u32 sz = (sizeof(struct iwl4965_scale_tbl_info) - | 1369 | (sizeof(struct iwl_rate_scale_data) * IWL_RATE_COUNT)); |
1375 | (sizeof(struct iwl4965_rate_scale_data) * IWL_RATE_COUNT)); | ||
1376 | u8 start_action = tbl->action; | 1370 | u8 start_action = tbl->action; |
1377 | u8 valid_tx_ant = priv->hw_params.valid_tx_ant; | 1371 | u8 valid_tx_ant = priv->hw_params.valid_tx_ant; |
1378 | int ret; | 1372 | int ret; |
@@ -1455,18 +1449,16 @@ static int rs_move_siso_to_other(struct iwl_priv *priv, | |||
1455 | * Try to switch to new modulation mode from MIMO | 1449 | * Try to switch to new modulation mode from MIMO |
1456 | */ | 1450 | */ |
1457 | static int rs_move_mimo_to_other(struct iwl_priv *priv, | 1451 | static int rs_move_mimo_to_other(struct iwl_priv *priv, |
1458 | struct iwl4965_lq_sta *lq_sta, | 1452 | struct iwl_lq_sta *lq_sta, |
1459 | struct ieee80211_conf *conf, | 1453 | struct ieee80211_conf *conf, |
1460 | struct sta_info *sta, | 1454 | struct sta_info *sta, int index) |
1461 | int index) | ||
1462 | { | 1455 | { |
1463 | s8 is_green = lq_sta->is_green; | 1456 | s8 is_green = lq_sta->is_green; |
1464 | struct iwl4965_scale_tbl_info *tbl = | 1457 | struct iwl_scale_tbl_info *tbl = &(lq_sta->lq_info[lq_sta->active_tbl]); |
1465 | &(lq_sta->lq_info[lq_sta->active_tbl]); | 1458 | struct iwl_scale_tbl_info *search_tbl = |
1466 | struct iwl4965_scale_tbl_info *search_tbl = | 1459 | &(lq_sta->lq_info[(1 - lq_sta->active_tbl)]); |
1467 | &(lq_sta->lq_info[(1 - lq_sta->active_tbl)]); | 1460 | u32 sz = (sizeof(struct iwl_scale_tbl_info) - |
1468 | u32 sz = (sizeof(struct iwl4965_scale_tbl_info) - | 1461 | (sizeof(struct iwl_rate_scale_data) * IWL_RATE_COUNT)); |
1469 | (sizeof(struct iwl4965_rate_scale_data) * IWL_RATE_COUNT)); | ||
1470 | u8 start_action = tbl->action; | 1462 | u8 start_action = tbl->action; |
1471 | /*u8 valid_tx_ant = priv->hw_params.valid_tx_ant;*/ | 1463 | /*u8 valid_tx_ant = priv->hw_params.valid_tx_ant;*/ |
1472 | int ret; | 1464 | int ret; |
@@ -1552,9 +1544,9 @@ static int rs_move_mimo_to_other(struct iwl_priv *priv, | |||
1552 | * 2) # times calling this function | 1544 | * 2) # times calling this function |
1553 | * 3) elapsed time in this mode (not used, for now) | 1545 | * 3) elapsed time in this mode (not used, for now) |
1554 | */ | 1546 | */ |
1555 | static void rs_stay_in_table(struct iwl4965_lq_sta *lq_sta) | 1547 | static void rs_stay_in_table(struct iwl_lq_sta *lq_sta) |
1556 | { | 1548 | { |
1557 | struct iwl4965_scale_tbl_info *tbl; | 1549 | struct iwl_scale_tbl_info *tbl; |
1558 | int i; | 1550 | int i; |
1559 | int active_tbl; | 1551 | int active_tbl; |
1560 | int flush_interval_passed = 0; | 1552 | int flush_interval_passed = 0; |
@@ -1642,7 +1634,7 @@ static void rs_rate_scale_perform(struct iwl_priv *priv, | |||
1642 | int high = IWL_RATE_INVALID; | 1634 | int high = IWL_RATE_INVALID; |
1643 | int index; | 1635 | int index; |
1644 | int i; | 1636 | int i; |
1645 | struct iwl4965_rate_scale_data *window = NULL; | 1637 | struct iwl_rate_scale_data *window = NULL; |
1646 | int current_tpt = IWL_INVALID_VALUE; | 1638 | int current_tpt = IWL_INVALID_VALUE; |
1647 | int low_tpt = IWL_INVALID_VALUE; | 1639 | int low_tpt = IWL_INVALID_VALUE; |
1648 | int high_tpt = IWL_INVALID_VALUE; | 1640 | int high_tpt = IWL_INVALID_VALUE; |
@@ -1651,8 +1643,8 @@ static void rs_rate_scale_perform(struct iwl_priv *priv, | |||
1651 | __le16 fc; | 1643 | __le16 fc; |
1652 | u16 rate_mask; | 1644 | u16 rate_mask; |
1653 | u8 update_lq = 0; | 1645 | u8 update_lq = 0; |
1654 | struct iwl4965_lq_sta *lq_sta; | 1646 | struct iwl_lq_sta *lq_sta; |
1655 | struct iwl4965_scale_tbl_info *tbl, *tbl1; | 1647 | struct iwl_scale_tbl_info *tbl, *tbl1; |
1656 | u16 rate_scale_index_msk = 0; | 1648 | u16 rate_scale_index_msk = 0; |
1657 | u32 rate; | 1649 | u32 rate; |
1658 | u8 is_green = 0; | 1650 | u8 is_green = 0; |
@@ -1675,7 +1667,7 @@ static void rs_rate_scale_perform(struct iwl_priv *priv, | |||
1675 | if (!sta || !sta->rate_ctrl_priv) | 1667 | if (!sta || !sta->rate_ctrl_priv) |
1676 | return; | 1668 | return; |
1677 | 1669 | ||
1678 | lq_sta = (struct iwl4965_lq_sta *)sta->rate_ctrl_priv; | 1670 | lq_sta = (struct iwl_lq_sta *)sta->rate_ctrl_priv; |
1679 | 1671 | ||
1680 | tid = rs_tl_add_packet(lq_sta, hdr); | 1672 | tid = rs_tl_add_packet(lq_sta, hdr); |
1681 | 1673 | ||
@@ -2030,8 +2022,8 @@ static void rs_initialize_lq(struct iwl_priv *priv, | |||
2030 | struct ieee80211_conf *conf, | 2022 | struct ieee80211_conf *conf, |
2031 | struct sta_info *sta) | 2023 | struct sta_info *sta) |
2032 | { | 2024 | { |
2033 | struct iwl4965_lq_sta *lq_sta; | 2025 | struct iwl_lq_sta *lq_sta; |
2034 | struct iwl4965_scale_tbl_info *tbl; | 2026 | struct iwl_scale_tbl_info *tbl; |
2035 | int rate_idx; | 2027 | int rate_idx; |
2036 | int i; | 2028 | int i; |
2037 | u32 rate; | 2029 | u32 rate; |
@@ -2042,7 +2034,7 @@ static void rs_initialize_lq(struct iwl_priv *priv, | |||
2042 | if (!sta || !sta->rate_ctrl_priv) | 2034 | if (!sta || !sta->rate_ctrl_priv) |
2043 | goto out; | 2035 | goto out; |
2044 | 2036 | ||
2045 | lq_sta = (struct iwl4965_lq_sta *)sta->rate_ctrl_priv; | 2037 | lq_sta = (struct iwl_lq_sta *)sta->rate_ctrl_priv; |
2046 | i = sta->last_txrate_idx; | 2038 | i = sta->last_txrate_idx; |
2047 | 2039 | ||
2048 | if ((lq_sta->lq.sta_id == 0xff) && | 2040 | if ((lq_sta->lq.sta_id == 0xff) && |
@@ -2096,7 +2088,7 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev, | |||
2096 | struct sta_info *sta; | 2088 | struct sta_info *sta; |
2097 | __le16 fc; | 2089 | __le16 fc; |
2098 | struct iwl_priv *priv = (struct iwl_priv *)priv_rate; | 2090 | struct iwl_priv *priv = (struct iwl_priv *)priv_rate; |
2099 | struct iwl4965_lq_sta *lq_sta; | 2091 | struct iwl_lq_sta *lq_sta; |
2100 | 2092 | ||
2101 | IWL_DEBUG_RATE_LIMIT("rate scale calculate new rate for skb\n"); | 2093 | IWL_DEBUG_RATE_LIMIT("rate scale calculate new rate for skb\n"); |
2102 | 2094 | ||
@@ -2113,7 +2105,7 @@ static void rs_get_rate(void *priv_rate, struct net_device *dev, | |||
2113 | goto out; | 2105 | goto out; |
2114 | } | 2106 | } |
2115 | 2107 | ||
2116 | lq_sta = (struct iwl4965_lq_sta *)sta->rate_ctrl_priv; | 2108 | lq_sta = (struct iwl_lq_sta *)sta->rate_ctrl_priv; |
2117 | i = sta->last_txrate_idx; | 2109 | i = sta->last_txrate_idx; |
2118 | 2110 | ||
2119 | if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && | 2111 | if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && |
@@ -2149,14 +2141,14 @@ out: | |||
2149 | 2141 | ||
2150 | static void *rs_alloc_sta(void *priv_rate, gfp_t gfp) | 2142 | static void *rs_alloc_sta(void *priv_rate, gfp_t gfp) |
2151 | { | 2143 | { |
2152 | struct iwl4965_lq_sta *lq_sta; | 2144 | struct iwl_lq_sta *lq_sta; |
2153 | struct iwl_priv *priv; | 2145 | struct iwl_priv *priv; |
2154 | int i, j; | 2146 | int i, j; |
2155 | 2147 | ||
2156 | priv = (struct iwl_priv *)priv_rate; | 2148 | priv = (struct iwl_priv *)priv_rate; |
2157 | IWL_DEBUG_RATE("create station rate scale window\n"); | 2149 | IWL_DEBUG_RATE("create station rate scale window\n"); |
2158 | 2150 | ||
2159 | lq_sta = kzalloc(sizeof(struct iwl4965_lq_sta), gfp); | 2151 | lq_sta = kzalloc(sizeof(struct iwl_lq_sta), gfp); |
2160 | 2152 | ||
2161 | if (lq_sta == NULL) | 2153 | if (lq_sta == NULL) |
2162 | return NULL; | 2154 | return NULL; |
@@ -2165,7 +2157,7 @@ static void *rs_alloc_sta(void *priv_rate, gfp_t gfp) | |||
2165 | 2157 | ||
2166 | for (j = 0; j < LQ_SIZE; j++) | 2158 | for (j = 0; j < LQ_SIZE; j++) |
2167 | for (i = 0; i < IWL_RATE_COUNT; i++) | 2159 | for (i = 0; i < IWL_RATE_COUNT; i++) |
2168 | rs_rate_scale_clear_window(&(lq_sta->lq_info[j].win[i])); | 2160 | rs_rate_scale_clear_window(&lq_sta->lq_info[j].win[i]); |
2169 | 2161 | ||
2170 | return lq_sta; | 2162 | return lq_sta; |
2171 | } | 2163 | } |
@@ -2178,7 +2170,7 @@ static void rs_rate_init(void *priv_rate, void *priv_sta, | |||
2178 | struct ieee80211_conf *conf = &local->hw.conf; | 2170 | struct ieee80211_conf *conf = &local->hw.conf; |
2179 | struct ieee80211_supported_band *sband; | 2171 | struct ieee80211_supported_band *sband; |
2180 | struct iwl_priv *priv = (struct iwl_priv *)priv_rate; | 2172 | struct iwl_priv *priv = (struct iwl_priv *)priv_rate; |
2181 | struct iwl4965_lq_sta *lq_sta = priv_sta; | 2173 | struct iwl_lq_sta *lq_sta = priv_sta; |
2182 | 2174 | ||
2183 | sband = local->hw.wiphy->bands[local->hw.conf.channel->band]; | 2175 | sband = local->hw.wiphy->bands[local->hw.conf.channel->band]; |
2184 | 2176 | ||
@@ -2187,7 +2179,7 @@ static void rs_rate_init(void *priv_rate, void *priv_sta, | |||
2187 | sta->txrate_idx = 3; | 2179 | sta->txrate_idx = 3; |
2188 | for (j = 0; j < LQ_SIZE; j++) | 2180 | for (j = 0; j < LQ_SIZE; j++) |
2189 | for (i = 0; i < IWL_RATE_COUNT; i++) | 2181 | for (i = 0; i < IWL_RATE_COUNT; i++) |
2190 | rs_rate_scale_clear_window(&(lq_sta->lq_info[j].win[i])); | 2182 | rs_rate_scale_clear_window(&lq_sta->lq_info[j].win[i]); |
2191 | 2183 | ||
2192 | IWL_DEBUG_RATE("LQ: *** rate scale global init ***\n"); | 2184 | IWL_DEBUG_RATE("LQ: *** rate scale global init ***\n"); |
2193 | /* TODO: what is a good starting rate for STA? About middle? Maybe not | 2185 | /* TODO: what is a good starting rate for STA? About middle? Maybe not |
@@ -2271,10 +2263,9 @@ static void rs_rate_init(void *priv_rate, void *priv_sta, | |||
2271 | } | 2263 | } |
2272 | 2264 | ||
2273 | static void rs_fill_link_cmd(const struct iwl_priv *priv, | 2265 | static void rs_fill_link_cmd(const struct iwl_priv *priv, |
2274 | struct iwl4965_lq_sta *lq_sta, | 2266 | struct iwl_lq_sta *lq_sta, u32 new_rate) |
2275 | u32 new_rate) | ||
2276 | { | 2267 | { |
2277 | struct iwl4965_scale_tbl_info tbl_type; | 2268 | struct iwl_scale_tbl_info tbl_type; |
2278 | int index = 0; | 2269 | int index = 0; |
2279 | int rate_idx; | 2270 | int rate_idx; |
2280 | int repeat_rate = 0; | 2271 | int repeat_rate = 0; |
@@ -2402,6 +2393,7 @@ static void rs_free(void *priv_rate) | |||
2402 | 2393 | ||
2403 | static void rs_clear(void *priv_rate) | 2394 | static void rs_clear(void *priv_rate) |
2404 | { | 2395 | { |
2396 | #ifdef CONFIG_IWLWIFI_DEBUG | ||
2405 | struct iwl_priv *priv = (struct iwl_priv *) priv_rate; | 2397 | struct iwl_priv *priv = (struct iwl_priv *) priv_rate; |
2406 | 2398 | ||
2407 | IWL_DEBUG_RATE("enter\n"); | 2399 | IWL_DEBUG_RATE("enter\n"); |
@@ -2409,11 +2401,12 @@ static void rs_clear(void *priv_rate) | |||
2409 | /* TODO - add rate scale state reset */ | 2401 | /* TODO - add rate scale state reset */ |
2410 | 2402 | ||
2411 | IWL_DEBUG_RATE("leave\n"); | 2403 | IWL_DEBUG_RATE("leave\n"); |
2404 | #endif /* CONFIG_IWLWIFI_DEBUG */ | ||
2412 | } | 2405 | } |
2413 | 2406 | ||
2414 | static void rs_free_sta(void *priv_rate, void *priv_sta) | 2407 | static void rs_free_sta(void *priv_rate, void *priv_sta) |
2415 | { | 2408 | { |
2416 | struct iwl4965_lq_sta *lq_sta = priv_sta; | 2409 | struct iwl_lq_sta *lq_sta = priv_sta; |
2417 | struct iwl_priv *priv; | 2410 | struct iwl_priv *priv; |
2418 | 2411 | ||
2419 | priv = (struct iwl_priv *)priv_rate; | 2412 | priv = (struct iwl_priv *)priv_rate; |
@@ -2429,8 +2422,8 @@ static int open_file_generic(struct inode *inode, struct file *file) | |||
2429 | file->private_data = inode->i_private; | 2422 | file->private_data = inode->i_private; |
2430 | return 0; | 2423 | return 0; |
2431 | } | 2424 | } |
2432 | static void rs_dbgfs_set_mcs(struct iwl4965_lq_sta *lq_sta, | 2425 | static void rs_dbgfs_set_mcs(struct iwl_lq_sta *lq_sta, |
2433 | u32 *rate_n_flags, int index) | 2426 | u32 *rate_n_flags, int index) |
2434 | { | 2427 | { |
2435 | struct iwl_priv *priv; | 2428 | struct iwl_priv *priv; |
2436 | 2429 | ||
@@ -2453,7 +2446,7 @@ static void rs_dbgfs_set_mcs(struct iwl4965_lq_sta *lq_sta, | |||
2453 | static ssize_t rs_sta_dbgfs_scale_table_write(struct file *file, | 2446 | static ssize_t rs_sta_dbgfs_scale_table_write(struct file *file, |
2454 | const char __user *user_buf, size_t count, loff_t *ppos) | 2447 | const char __user *user_buf, size_t count, loff_t *ppos) |
2455 | { | 2448 | { |
2456 | struct iwl4965_lq_sta *lq_sta = file->private_data; | 2449 | struct iwl_lq_sta *lq_sta = file->private_data; |
2457 | struct iwl_priv *priv; | 2450 | struct iwl_priv *priv; |
2458 | char buf[64]; | 2451 | char buf[64]; |
2459 | int buf_size; | 2452 | int buf_size; |
@@ -2493,7 +2486,7 @@ static ssize_t rs_sta_dbgfs_scale_table_read(struct file *file, | |||
2493 | int desc = 0; | 2486 | int desc = 0; |
2494 | int i = 0; | 2487 | int i = 0; |
2495 | 2488 | ||
2496 | struct iwl4965_lq_sta *lq_sta = file->private_data; | 2489 | struct iwl_lq_sta *lq_sta = file->private_data; |
2497 | 2490 | ||
2498 | desc += sprintf(buff+desc, "sta_id %d\n", lq_sta->lq.sta_id); | 2491 | desc += sprintf(buff+desc, "sta_id %d\n", lq_sta->lq.sta_id); |
2499 | desc += sprintf(buff+desc, "failed=%d success=%d rate=0%X\n", | 2492 | desc += sprintf(buff+desc, "failed=%d success=%d rate=0%X\n", |
@@ -2541,7 +2534,7 @@ static ssize_t rs_sta_dbgfs_stats_table_read(struct file *file, | |||
2541 | int desc = 0; | 2534 | int desc = 0; |
2542 | int i, j; | 2535 | int i, j; |
2543 | 2536 | ||
2544 | struct iwl4965_lq_sta *lq_sta = file->private_data; | 2537 | struct iwl_lq_sta *lq_sta = file->private_data; |
2545 | for (i = 0; i < LQ_SIZE; i++) { | 2538 | for (i = 0; i < LQ_SIZE; i++) { |
2546 | desc += sprintf(buff+desc, "%s type=%d SGI=%d FAT=%d DUP=%d\n" | 2539 | desc += sprintf(buff+desc, "%s type=%d SGI=%d FAT=%d DUP=%d\n" |
2547 | "rate=0x%X\n", | 2540 | "rate=0x%X\n", |
@@ -2570,7 +2563,7 @@ static const struct file_operations rs_sta_dbgfs_stats_table_ops = { | |||
2570 | static void rs_add_debugfs(void *priv, void *priv_sta, | 2563 | static void rs_add_debugfs(void *priv, void *priv_sta, |
2571 | struct dentry *dir) | 2564 | struct dentry *dir) |
2572 | { | 2565 | { |
2573 | struct iwl4965_lq_sta *lq_sta = priv_sta; | 2566 | struct iwl_lq_sta *lq_sta = priv_sta; |
2574 | lq_sta->rs_sta_dbgfs_scale_table_file = | 2567 | lq_sta->rs_sta_dbgfs_scale_table_file = |
2575 | debugfs_create_file("rate_scale_table", 0600, dir, | 2568 | debugfs_create_file("rate_scale_table", 0600, dir, |
2576 | lq_sta, &rs_sta_dbgfs_scale_table_ops); | 2569 | lq_sta, &rs_sta_dbgfs_scale_table_ops); |
@@ -2585,7 +2578,7 @@ static void rs_add_debugfs(void *priv, void *priv_sta, | |||
2585 | 2578 | ||
2586 | static void rs_remove_debugfs(void *priv, void *priv_sta) | 2579 | static void rs_remove_debugfs(void *priv, void *priv_sta) |
2587 | { | 2580 | { |
2588 | struct iwl4965_lq_sta *lq_sta = priv_sta; | 2581 | struct iwl_lq_sta *lq_sta = priv_sta; |
2589 | debugfs_remove(lq_sta->rs_sta_dbgfs_scale_table_file); | 2582 | debugfs_remove(lq_sta->rs_sta_dbgfs_scale_table_file); |
2590 | debugfs_remove(lq_sta->rs_sta_dbgfs_stats_table_file); | 2583 | debugfs_remove(lq_sta->rs_sta_dbgfs_stats_table_file); |
2591 | debugfs_remove(lq_sta->rs_sta_dbgfs_tx_agg_tid_en_file); | 2584 | debugfs_remove(lq_sta->rs_sta_dbgfs_tx_agg_tid_en_file); |
@@ -2609,104 +2602,12 @@ static struct rate_control_ops rs_ops = { | |||
2609 | #endif | 2602 | #endif |
2610 | }; | 2603 | }; |
2611 | 2604 | ||
2612 | int iwl4965_fill_rs_info(struct ieee80211_hw *hw, char *buf, u8 sta_id) | 2605 | int iwlagn_rate_control_register(void) |
2613 | { | ||
2614 | struct ieee80211_local *local = hw_to_local(hw); | ||
2615 | struct iwl_priv *priv = hw->priv; | ||
2616 | struct iwl4965_lq_sta *lq_sta; | ||
2617 | struct sta_info *sta; | ||
2618 | int cnt = 0, i; | ||
2619 | u32 samples = 0, success = 0, good = 0; | ||
2620 | unsigned long now = jiffies; | ||
2621 | u32 max_time = 0; | ||
2622 | u8 lq_type, antenna; | ||
2623 | |||
2624 | rcu_read_lock(); | ||
2625 | |||
2626 | sta = sta_info_get(local, priv->stations[sta_id].sta.sta.addr); | ||
2627 | if (!sta || !sta->rate_ctrl_priv) { | ||
2628 | if (sta) | ||
2629 | IWL_DEBUG_RATE("leave - no private rate data!\n"); | ||
2630 | else | ||
2631 | IWL_DEBUG_RATE("leave - no station!\n"); | ||
2632 | rcu_read_unlock(); | ||
2633 | return sprintf(buf, "station %d not found\n", sta_id); | ||
2634 | } | ||
2635 | |||
2636 | lq_sta = (void *)sta->rate_ctrl_priv; | ||
2637 | |||
2638 | lq_type = lq_sta->lq_info[lq_sta->active_tbl].lq_type; | ||
2639 | antenna = lq_sta->lq_info[lq_sta->active_tbl].ant_type; | ||
2640 | |||
2641 | if (is_legacy(lq_type)) | ||
2642 | i = IWL_RATE_54M_INDEX; | ||
2643 | else | ||
2644 | i = IWL_RATE_60M_INDEX; | ||
2645 | while (1) { | ||
2646 | u64 mask; | ||
2647 | int j; | ||
2648 | int active = lq_sta->active_tbl; | ||
2649 | |||
2650 | cnt += | ||
2651 | sprintf(&buf[cnt], " %2dMbs: ", iwl_rates[i].ieee / 2); | ||
2652 | |||
2653 | mask = (1ULL << (IWL_RATE_MAX_WINDOW - 1)); | ||
2654 | for (j = 0; j < IWL_RATE_MAX_WINDOW; j++, mask >>= 1) | ||
2655 | buf[cnt++] = | ||
2656 | (lq_sta->lq_info[active].win[i].data & mask) | ||
2657 | ? '1' : '0'; | ||
2658 | |||
2659 | samples += lq_sta->lq_info[active].win[i].counter; | ||
2660 | good += lq_sta->lq_info[active].win[i].success_counter; | ||
2661 | success += lq_sta->lq_info[active].win[i].success_counter * | ||
2662 | iwl_rates[i].ieee; | ||
2663 | |||
2664 | if (lq_sta->lq_info[active].win[i].stamp) { | ||
2665 | int delta = | ||
2666 | jiffies_to_msecs(now - | ||
2667 | lq_sta->lq_info[active].win[i].stamp); | ||
2668 | |||
2669 | if (delta > max_time) | ||
2670 | max_time = delta; | ||
2671 | |||
2672 | cnt += sprintf(&buf[cnt], "%5dms\n", delta); | ||
2673 | } else | ||
2674 | buf[cnt++] = '\n'; | ||
2675 | |||
2676 | j = iwl4965_get_prev_ieee_rate(i); | ||
2677 | if (j == i) | ||
2678 | break; | ||
2679 | i = j; | ||
2680 | } | ||
2681 | |||
2682 | /* | ||
2683 | * Display the average rate of all samples taken. | ||
2684 | * NOTE: We multiply # of samples by 2 since the IEEE measurement | ||
2685 | * added from iwl_rates is actually 2X the rate. | ||
2686 | */ | ||
2687 | if (samples) | ||
2688 | cnt += sprintf(&buf[cnt], | ||
2689 | "\nAverage rate is %3d.%02dMbs over last %4dms\n" | ||
2690 | "%3d%% success (%d good packets over %d tries)\n", | ||
2691 | success / (2 * samples), (success * 5 / samples) % 10, | ||
2692 | max_time, good * 100 / samples, good, samples); | ||
2693 | else | ||
2694 | cnt += sprintf(&buf[cnt], "\nAverage rate: 0Mbs\n"); | ||
2695 | |||
2696 | cnt += sprintf(&buf[cnt], "\nrate scale type %d antenna %d " | ||
2697 | "active_search %d rate index %d\n", lq_type, antenna, | ||
2698 | lq_sta->search_better_tbl, sta->last_txrate_idx); | ||
2699 | |||
2700 | rcu_read_unlock(); | ||
2701 | return cnt; | ||
2702 | } | ||
2703 | |||
2704 | int iwl4965_rate_control_register(void) | ||
2705 | { | 2606 | { |
2706 | return ieee80211_rate_control_register(&rs_ops); | 2607 | return ieee80211_rate_control_register(&rs_ops); |
2707 | } | 2608 | } |
2708 | 2609 | ||
2709 | void iwl4965_rate_control_unregister(void) | 2610 | void iwlagn_rate_control_unregister(void) |
2710 | { | 2611 | { |
2711 | ieee80211_rate_control_unregister(&rs_ops); | 2612 | ieee80211_rate_control_unregister(&rs_ops); |
2712 | } | 2613 | } |
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-rs.h b/drivers/net/wireless/iwlwifi/iwl-agn-rs.h index 9b9972885aa5..84d4d1e33755 100644 --- a/drivers/net/wireless/iwlwifi/iwl-4965-rs.h +++ b/drivers/net/wireless/iwlwifi/iwl-agn-rs.h | |||
@@ -24,8 +24,8 @@ | |||
24 | * | 24 | * |
25 | *****************************************************************************/ | 25 | *****************************************************************************/ |
26 | 26 | ||
27 | #ifndef __iwl_4965_rs_h__ | 27 | #ifndef __iwl_agn_rs_h__ |
28 | #define __iwl_4965_rs_h__ | 28 | #define __iwl_agn_rs_h__ |
29 | 29 | ||
30 | #include "iwl-dev.h" | 30 | #include "iwl-dev.h" |
31 | 31 | ||
@@ -88,7 +88,7 @@ enum { | |||
88 | #define IWL_RATE_5M_MASK (1 << IWL_RATE_5M_INDEX) | 88 | #define IWL_RATE_5M_MASK (1 << IWL_RATE_5M_INDEX) |
89 | #define IWL_RATE_11M_MASK (1 << IWL_RATE_11M_INDEX) | 89 | #define IWL_RATE_11M_MASK (1 << IWL_RATE_11M_INDEX) |
90 | 90 | ||
91 | /* 4965 uCode API values for legacy bit rates, both OFDM and CCK */ | 91 | /* uCode API values for legacy bit rates, both OFDM and CCK */ |
92 | enum { | 92 | enum { |
93 | IWL_RATE_6M_PLCP = 13, | 93 | IWL_RATE_6M_PLCP = 13, |
94 | IWL_RATE_9M_PLCP = 15, | 94 | IWL_RATE_9M_PLCP = 15, |
@@ -107,7 +107,7 @@ enum { | |||
107 | /*FIXME:RS:add IWL_RATE_LEGACY_INVM_PLCP = 0,*/ | 107 | /*FIXME:RS:add IWL_RATE_LEGACY_INVM_PLCP = 0,*/ |
108 | }; | 108 | }; |
109 | 109 | ||
110 | /* 4965 uCode API values for OFDM high-throughput (HT) bit rates */ | 110 | /* uCode API values for OFDM high-throughput (HT) bit rates */ |
111 | enum { | 111 | enum { |
112 | IWL_RATE_SISO_6M_PLCP = 0, | 112 | IWL_RATE_SISO_6M_PLCP = 0, |
113 | IWL_RATE_SISO_12M_PLCP = 1, | 113 | IWL_RATE_SISO_12M_PLCP = 1, |
@@ -287,15 +287,6 @@ static inline u8 iwl4965_get_prev_ieee_rate(u8 rate_index) | |||
287 | } | 287 | } |
288 | 288 | ||
289 | /** | 289 | /** |
290 | * iwl4965_fill_rs_info - Fill an output text buffer with the rate representation | ||
291 | * | ||
292 | * NOTE: This is provided as a quick mechanism for a user to visualize | ||
293 | * the performance of the rate control algorithm and is not meant to be | ||
294 | * parsed software. | ||
295 | */ | ||
296 | extern int iwl4965_fill_rs_info(struct ieee80211_hw *, char *buf, u8 sta_id); | ||
297 | |||
298 | /** | ||
299 | * iwl4965_rate_control_register - Register the rate control algorithm callbacks | 290 | * iwl4965_rate_control_register - Register the rate control algorithm callbacks |
300 | * | 291 | * |
301 | * Since the rate control algorithm is hardware specific, there is no need | 292 | * Since the rate control algorithm is hardware specific, there is no need |
@@ -305,7 +296,7 @@ extern int iwl4965_fill_rs_info(struct ieee80211_hw *, char *buf, u8 sta_id); | |||
305 | * ieee80211_register_hw | 296 | * ieee80211_register_hw |
306 | * | 297 | * |
307 | */ | 298 | */ |
308 | extern int iwl4965_rate_control_register(void); | 299 | extern int iwlagn_rate_control_register(void); |
309 | 300 | ||
310 | /** | 301 | /** |
311 | * iwl4965_rate_control_unregister - Unregister the rate control callbacks | 302 | * iwl4965_rate_control_unregister - Unregister the rate control callbacks |
@@ -313,6 +304,6 @@ extern int iwl4965_rate_control_register(void); | |||
313 | * This should be called after calling ieee80211_unregister_hw, but before | 304 | * This should be called after calling ieee80211_unregister_hw, but before |
314 | * the driver is unloaded. | 305 | * the driver is unloaded. |
315 | */ | 306 | */ |
316 | extern void iwl4965_rate_control_unregister(void); | 307 | extern void iwlagn_rate_control_unregister(void); |
317 | 308 | ||
318 | #endif | 309 | #endif /* __iwl_agn__rs__ */ |
diff --git a/drivers/net/wireless/iwlwifi/iwl4965-base.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index 71f5da3fe5c4..b8407d5704a1 100644 --- a/drivers/net/wireless/iwlwifi/iwl4965-base.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c | |||
@@ -65,7 +65,7 @@ | |||
65 | * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk | 65 | * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk |
66 | */ | 66 | */ |
67 | 67 | ||
68 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link 4965AGN driver for Linux" | 68 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux" |
69 | 69 | ||
70 | #ifdef CONFIG_IWLWIFI_DEBUG | 70 | #ifdef CONFIG_IWLWIFI_DEBUG |
71 | #define VD "d" | 71 | #define VD "d" |
@@ -73,7 +73,7 @@ | |||
73 | #define VD | 73 | #define VD |
74 | #endif | 74 | #endif |
75 | 75 | ||
76 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT | 76 | #ifdef CONFIG_IWLAGN_SPECTRUM_MEASUREMENT |
77 | #define VS "s" | 77 | #define VS "s" |
78 | #else | 78 | #else |
79 | #define VS | 79 | #define VS |
@@ -86,6 +86,7 @@ MODULE_DESCRIPTION(DRV_DESCRIPTION); | |||
86 | MODULE_VERSION(DRV_VERSION); | 86 | MODULE_VERSION(DRV_VERSION); |
87 | MODULE_AUTHOR(DRV_COPYRIGHT); | 87 | MODULE_AUTHOR(DRV_COPYRIGHT); |
88 | MODULE_LICENSE("GPL"); | 88 | MODULE_LICENSE("GPL"); |
89 | MODULE_ALIAS("iwl4965"); | ||
89 | 90 | ||
90 | /*************** STATION TABLE MANAGEMENT **** | 91 | /*************** STATION TABLE MANAGEMENT **** |
91 | * mac80211 should be examined to determine if sta_info is duplicating | 92 | * mac80211 should be examined to determine if sta_info is duplicating |
@@ -444,11 +445,10 @@ static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame) | |||
444 | list_add(&frame->list, &priv->free_frames); | 445 | list_add(&frame->list, &priv->free_frames); |
445 | } | 446 | } |
446 | 447 | ||
447 | unsigned int iwl4965_fill_beacon_frame(struct iwl_priv *priv, | 448 | static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv, |
448 | struct ieee80211_hdr *hdr, | 449 | struct ieee80211_hdr *hdr, |
449 | const u8 *dest, int left) | 450 | const u8 *dest, int left) |
450 | { | 451 | { |
451 | |||
452 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || | 452 | if (!iwl_is_associated(priv) || !priv->ibss_beacon || |
453 | ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) && | 453 | ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) && |
454 | (priv->iw_mode != IEEE80211_IF_TYPE_AP))) | 454 | (priv->iw_mode != IEEE80211_IF_TYPE_AP))) |
@@ -487,6 +487,38 @@ static u8 iwl4965_rate_get_lowest_plcp(struct iwl_priv *priv) | |||
487 | return IWL_RATE_6M_PLCP; | 487 | return IWL_RATE_6M_PLCP; |
488 | } | 488 | } |
489 | 489 | ||
490 | unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv, | ||
491 | struct iwl_frame *frame, u8 rate) | ||
492 | { | ||
493 | struct iwl_tx_beacon_cmd *tx_beacon_cmd; | ||
494 | unsigned int frame_size; | ||
495 | |||
496 | tx_beacon_cmd = &frame->u.beacon; | ||
497 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | ||
498 | |||
499 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; | ||
500 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | ||
501 | |||
502 | frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame, | ||
503 | iwl_bcast_addr, | ||
504 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); | ||
505 | |||
506 | BUG_ON(frame_size > MAX_MPDU_SIZE); | ||
507 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); | ||
508 | |||
509 | if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP)) | ||
510 | tx_beacon_cmd->tx.rate_n_flags = | ||
511 | iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK); | ||
512 | else | ||
513 | tx_beacon_cmd->tx.rate_n_flags = | ||
514 | iwl_hw_set_rate_n_flags(rate, 0); | ||
515 | |||
516 | tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK | | ||
517 | TX_CMD_FLG_TSF_MSK | | ||
518 | TX_CMD_FLG_STA_RATE_MSK; | ||
519 | |||
520 | return sizeof(*tx_beacon_cmd) + frame_size; | ||
521 | } | ||
490 | static int iwl4965_send_beacon_cmd(struct iwl_priv *priv) | 522 | static int iwl4965_send_beacon_cmd(struct iwl_priv *priv) |
491 | { | 523 | { |
492 | struct iwl_frame *frame; | 524 | struct iwl_frame *frame; |
@@ -608,7 +640,6 @@ static void iwl_activate_qos(struct iwl_priv *priv, u8 force) | |||
608 | } | 640 | } |
609 | 641 | ||
610 | #define MAX_UCODE_BEACON_INTERVAL 4096 | 642 | #define MAX_UCODE_BEACON_INTERVAL 4096 |
611 | #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA) | ||
612 | 643 | ||
613 | static __le16 iwl4965_adjust_beacon_interval(u16 beacon_val) | 644 | static __le16 iwl4965_adjust_beacon_interval(u16 beacon_val) |
614 | { | 645 | { |
@@ -638,7 +669,7 @@ static void iwl4965_setup_rxon_timing(struct iwl_priv *priv) | |||
638 | priv->rxon_timing.timestamp.dw[0] = | 669 | priv->rxon_timing.timestamp.dw[0] = |
639 | cpu_to_le32(priv->timestamp & 0xFFFFFFFF); | 670 | cpu_to_le32(priv->timestamp & 0xFFFFFFFF); |
640 | 671 | ||
641 | priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL; | 672 | priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval); |
642 | 673 | ||
643 | tsf = priv->timestamp; | 674 | tsf = priv->timestamp; |
644 | 675 | ||
@@ -853,7 +884,7 @@ static void iwl4965_set_rate(struct iwl_priv *priv) | |||
853 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | 884 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; |
854 | } | 885 | } |
855 | 886 | ||
856 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT | 887 | #ifdef CONFIG_IWLAGN_SPECTRUM_MEASUREMENT |
857 | 888 | ||
858 | #include "iwl-spectrum.h" | 889 | #include "iwl-spectrum.h" |
859 | 890 | ||
@@ -1057,7 +1088,7 @@ static void iwl4965_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |||
1057 | static void iwl4965_rx_spectrum_measure_notif(struct iwl_priv *priv, | 1088 | static void iwl4965_rx_spectrum_measure_notif(struct iwl_priv *priv, |
1058 | struct iwl_rx_mem_buffer *rxb) | 1089 | struct iwl_rx_mem_buffer *rxb) |
1059 | { | 1090 | { |
1060 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT | 1091 | #ifdef CONFIG_IWLAGN_SPECTRUM_MEASUREMENT |
1061 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | 1092 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
1062 | struct iwl4965_spectrum_notification *report = &(pkt->u.spectrum_notif); | 1093 | struct iwl4965_spectrum_notification *report = &(pkt->u.spectrum_notif); |
1063 | 1094 | ||
@@ -1231,6 +1262,37 @@ static void iwl4965_rx_card_state_notif(struct iwl_priv *priv, | |||
1231 | wake_up_interruptible(&priv->wait_command_queue); | 1262 | wake_up_interruptible(&priv->wait_command_queue); |
1232 | } | 1263 | } |
1233 | 1264 | ||
1265 | int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) | ||
1266 | { | ||
1267 | int ret; | ||
1268 | unsigned long flags; | ||
1269 | |||
1270 | spin_lock_irqsave(&priv->lock, flags); | ||
1271 | ret = iwl_grab_nic_access(priv); | ||
1272 | if (ret) | ||
1273 | goto err; | ||
1274 | |||
1275 | if (src == IWL_PWR_SRC_VAUX) { | ||
1276 | u32 val; | ||
1277 | ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE, | ||
1278 | &val); | ||
1279 | |||
1280 | if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) | ||
1281 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | ||
1282 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | ||
1283 | ~APMG_PS_CTRL_MSK_PWR_SRC); | ||
1284 | } else { | ||
1285 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | ||
1286 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, | ||
1287 | ~APMG_PS_CTRL_MSK_PWR_SRC); | ||
1288 | } | ||
1289 | |||
1290 | iwl_release_nic_access(priv); | ||
1291 | err: | ||
1292 | spin_unlock_irqrestore(&priv->lock, flags); | ||
1293 | return ret; | ||
1294 | } | ||
1295 | |||
1234 | /** | 1296 | /** |
1235 | * iwl4965_setup_rx_handlers - Initialize Rx handler callbacks | 1297 | * iwl4965_setup_rx_handlers - Initialize Rx handler callbacks |
1236 | * | 1298 | * |
@@ -2170,17 +2232,16 @@ static int __iwl4965_up(struct iwl_priv *priv) | |||
2170 | } | 2232 | } |
2171 | 2233 | ||
2172 | /* If platform's RF_KILL switch is NOT set to KILL */ | 2234 | /* If platform's RF_KILL switch is NOT set to KILL */ |
2173 | if (iwl_read32(priv, CSR_GP_CNTRL) & | 2235 | if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
2174 | CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) | ||
2175 | clear_bit(STATUS_RF_KILL_HW, &priv->status); | 2236 | clear_bit(STATUS_RF_KILL_HW, &priv->status); |
2176 | else | 2237 | else |
2177 | set_bit(STATUS_RF_KILL_HW, &priv->status); | 2238 | set_bit(STATUS_RF_KILL_HW, &priv->status); |
2178 | 2239 | ||
2179 | if (!test_bit(STATUS_IN_SUSPEND, &priv->status) && | 2240 | if (iwl_is_rfkill(priv)) { |
2180 | iwl_is_rfkill(priv)) { | 2241 | iwl4965_enable_interrupts(priv); |
2181 | IWL_WARNING("Radio disabled by %s RF Kill switch\n", | 2242 | IWL_WARNING("Radio disabled by %s RF Kill switch\n", |
2182 | test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW"); | 2243 | test_bit(STATUS_RF_KILL_HW, &priv->status) ? "HW" : "SW"); |
2183 | return -ENODEV; | 2244 | return 0; |
2184 | } | 2245 | } |
2185 | 2246 | ||
2186 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); | 2247 | iwl_write32(priv, CSR_INT, 0xFFFFFFFF); |
@@ -2216,11 +2277,6 @@ static int __iwl4965_up(struct iwl_priv *priv) | |||
2216 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, | 2277 | memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr, |
2217 | priv->ucode_data.len); | 2278 | priv->ucode_data.len); |
2218 | 2279 | ||
2219 | /* We return success when we resume from suspend and rf_kill is on. */ | ||
2220 | if (test_bit(STATUS_RF_KILL_HW, &priv->status) || | ||
2221 | test_bit(STATUS_RF_KILL_SW, &priv->status)) | ||
2222 | return 0; | ||
2223 | |||
2224 | for (i = 0; i < MAX_HW_RESTARTS; i++) { | 2280 | for (i = 0; i < MAX_HW_RESTARTS; i++) { |
2225 | 2281 | ||
2226 | iwl_clear_stations_table(priv); | 2282 | iwl_clear_stations_table(priv); |
@@ -2415,7 +2471,7 @@ static void iwl4965_post_associate(struct iwl_priv *priv) | |||
2415 | unsigned long flags; | 2471 | unsigned long flags; |
2416 | 2472 | ||
2417 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | 2473 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { |
2418 | IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__); | 2474 | IWL_ERROR("%s Should not be called in AP mode\n", __func__); |
2419 | return; | 2475 | return; |
2420 | } | 2476 | } |
2421 | 2477 | ||
@@ -2491,7 +2547,7 @@ static void iwl4965_post_associate(struct iwl_priv *priv) | |||
2491 | 2547 | ||
2492 | default: | 2548 | default: |
2493 | IWL_ERROR("%s Should not be called in %d mode\n", | 2549 | IWL_ERROR("%s Should not be called in %d mode\n", |
2494 | __FUNCTION__, priv->iw_mode); | 2550 | __func__, priv->iw_mode); |
2495 | break; | 2551 | break; |
2496 | } | 2552 | } |
2497 | 2553 | ||
@@ -2589,6 +2645,9 @@ static int iwl4965_mac_start(struct ieee80211_hw *hw) | |||
2589 | if (ret) | 2645 | if (ret) |
2590 | goto out_release_irq; | 2646 | goto out_release_irq; |
2591 | 2647 | ||
2648 | if (iwl_is_rfkill(priv)) | ||
2649 | goto out; | ||
2650 | |||
2592 | IWL_DEBUG_INFO("Start UP work done.\n"); | 2651 | IWL_DEBUG_INFO("Start UP work done.\n"); |
2593 | 2652 | ||
2594 | if (test_bit(STATUS_IN_SUSPEND, &priv->status)) | 2653 | if (test_bit(STATUS_IN_SUSPEND, &priv->status)) |
@@ -2608,6 +2667,7 @@ static int iwl4965_mac_start(struct ieee80211_hw *hw) | |||
2608 | } | 2667 | } |
2609 | } | 2668 | } |
2610 | 2669 | ||
2670 | out: | ||
2611 | priv->is_open = 1; | 2671 | priv->is_open = 1; |
2612 | IWL_DEBUG_MAC80211("leave\n"); | 2672 | IWL_DEBUG_MAC80211("leave\n"); |
2613 | return 0; | 2673 | return 0; |
@@ -2773,6 +2833,7 @@ static int iwl4965_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *co | |||
2773 | 2833 | ||
2774 | spin_lock_irqsave(&priv->lock, flags); | 2834 | spin_lock_irqsave(&priv->lock, flags); |
2775 | 2835 | ||
2836 | |||
2776 | /* if we are switching from ht to 2.4 clear flags | 2837 | /* if we are switching from ht to 2.4 clear flags |
2777 | * from any ht related info since 2.4 does not | 2838 | * from any ht related info since 2.4 does not |
2778 | * support ht */ | 2839 | * support ht */ |
@@ -3102,6 +3163,7 @@ static void iwl4965_bss_info_changed(struct ieee80211_hw *hw, | |||
3102 | if (bss_conf->assoc) { | 3163 | if (bss_conf->assoc) { |
3103 | priv->assoc_id = bss_conf->aid; | 3164 | priv->assoc_id = bss_conf->aid; |
3104 | priv->beacon_int = bss_conf->beacon_int; | 3165 | priv->beacon_int = bss_conf->beacon_int; |
3166 | priv->power_data.dtim_period = bss_conf->dtim_period; | ||
3105 | priv->timestamp = bss_conf->timestamp; | 3167 | priv->timestamp = bss_conf->timestamp; |
3106 | priv->assoc_capability = bss_conf->assoc_capability; | 3168 | priv->assoc_capability = bss_conf->assoc_capability; |
3107 | priv->next_scan_jiffies = jiffies + | 3169 | priv->next_scan_jiffies = jiffies + |
@@ -3345,6 +3407,39 @@ static int iwl4965_mac_conf_tx(struct ieee80211_hw *hw, u16 queue, | |||
3345 | return 0; | 3407 | return 0; |
3346 | } | 3408 | } |
3347 | 3409 | ||
3410 | static int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw, | ||
3411 | enum ieee80211_ampdu_mlme_action action, | ||
3412 | const u8 *addr, u16 tid, u16 *ssn) | ||
3413 | { | ||
3414 | struct iwl_priv *priv = hw->priv; | ||
3415 | DECLARE_MAC_BUF(mac); | ||
3416 | |||
3417 | IWL_DEBUG_HT("A-MPDU action on addr %s tid %d\n", | ||
3418 | print_mac(mac, addr), tid); | ||
3419 | |||
3420 | if (!(priv->cfg->sku & IWL_SKU_N)) | ||
3421 | return -EACCES; | ||
3422 | |||
3423 | switch (action) { | ||
3424 | case IEEE80211_AMPDU_RX_START: | ||
3425 | IWL_DEBUG_HT("start Rx\n"); | ||
3426 | return iwl_rx_agg_start(priv, addr, tid, *ssn); | ||
3427 | case IEEE80211_AMPDU_RX_STOP: | ||
3428 | IWL_DEBUG_HT("stop Rx\n"); | ||
3429 | return iwl_rx_agg_stop(priv, addr, tid); | ||
3430 | case IEEE80211_AMPDU_TX_START: | ||
3431 | IWL_DEBUG_HT("start Tx\n"); | ||
3432 | return iwl_tx_agg_start(priv, addr, tid, ssn); | ||
3433 | case IEEE80211_AMPDU_TX_STOP: | ||
3434 | IWL_DEBUG_HT("stop Tx\n"); | ||
3435 | return iwl_tx_agg_stop(priv, addr, tid); | ||
3436 | default: | ||
3437 | IWL_DEBUG_HT("unknown\n"); | ||
3438 | return -EINVAL; | ||
3439 | break; | ||
3440 | } | ||
3441 | return 0; | ||
3442 | } | ||
3348 | static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw, | 3443 | static int iwl4965_mac_get_tx_stats(struct ieee80211_hw *hw, |
3349 | struct ieee80211_tx_queue_stats *stats) | 3444 | struct ieee80211_tx_queue_stats *stats) |
3350 | { | 3445 | { |
@@ -3592,15 +3687,6 @@ static ssize_t show_temperature(struct device *d, | |||
3592 | 3687 | ||
3593 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); | 3688 | static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL); |
3594 | 3689 | ||
3595 | static ssize_t show_rs_window(struct device *d, | ||
3596 | struct device_attribute *attr, | ||
3597 | char *buf) | ||
3598 | { | ||
3599 | struct iwl_priv *priv = d->driver_data; | ||
3600 | return iwl4965_fill_rs_info(priv->hw, buf, IWL_AP_ID); | ||
3601 | } | ||
3602 | static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL); | ||
3603 | |||
3604 | static ssize_t show_tx_power(struct device *d, | 3690 | static ssize_t show_tx_power(struct device *d, |
3605 | struct device_attribute *attr, char *buf) | 3691 | struct device_attribute *attr, char *buf) |
3606 | { | 3692 | { |
@@ -3699,7 +3785,7 @@ static ssize_t store_filter_flags(struct device *d, | |||
3699 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, | 3785 | static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags, |
3700 | store_filter_flags); | 3786 | store_filter_flags); |
3701 | 3787 | ||
3702 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT | 3788 | #ifdef CONFIG_IWLAGN_SPECTRUM_MEASUREMENT |
3703 | 3789 | ||
3704 | static ssize_t show_measurement(struct device *d, | 3790 | static ssize_t show_measurement(struct device *d, |
3705 | struct device_attribute *attr, char *buf) | 3791 | struct device_attribute *attr, char *buf) |
@@ -3707,7 +3793,7 @@ static ssize_t show_measurement(struct device *d, | |||
3707 | struct iwl_priv *priv = dev_get_drvdata(d); | 3793 | struct iwl_priv *priv = dev_get_drvdata(d); |
3708 | struct iwl4965_spectrum_notification measure_report; | 3794 | struct iwl4965_spectrum_notification measure_report; |
3709 | u32 size = sizeof(measure_report), len = 0, ofs = 0; | 3795 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
3710 | u8 *data = (u8 *) & measure_report; | 3796 | u8 *data = (u8 *)&measure_report; |
3711 | unsigned long flags; | 3797 | unsigned long flags; |
3712 | 3798 | ||
3713 | spin_lock_irqsave(&priv->lock, flags); | 3799 | spin_lock_irqsave(&priv->lock, flags); |
@@ -3770,7 +3856,7 @@ static ssize_t store_measurement(struct device *d, | |||
3770 | 3856 | ||
3771 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, | 3857 | static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR, |
3772 | show_measurement, store_measurement); | 3858 | show_measurement, store_measurement); |
3773 | #endif /* CONFIG_IWL4965_SPECTRUM_MEASUREMENT */ | 3859 | #endif /* CONFIG_IWLAGN_SPECTRUM_MEASUREMENT */ |
3774 | 3860 | ||
3775 | static ssize_t store_retry_rate(struct device *d, | 3861 | static ssize_t store_retry_rate(struct device *d, |
3776 | struct device_attribute *attr, | 3862 | struct device_attribute *attr, |
@@ -3800,77 +3886,54 @@ static ssize_t store_power_level(struct device *d, | |||
3800 | const char *buf, size_t count) | 3886 | const char *buf, size_t count) |
3801 | { | 3887 | { |
3802 | struct iwl_priv *priv = dev_get_drvdata(d); | 3888 | struct iwl_priv *priv = dev_get_drvdata(d); |
3803 | int rc; | 3889 | int ret; |
3804 | int mode; | 3890 | int mode; |
3805 | 3891 | ||
3806 | mode = simple_strtoul(buf, NULL, 0); | 3892 | mode = simple_strtoul(buf, NULL, 0); |
3807 | mutex_lock(&priv->mutex); | 3893 | mutex_lock(&priv->mutex); |
3808 | 3894 | ||
3809 | if (!iwl_is_ready(priv)) { | 3895 | if (!iwl_is_ready(priv)) { |
3810 | rc = -EAGAIN; | 3896 | ret = -EAGAIN; |
3811 | goto out; | 3897 | goto out; |
3812 | } | 3898 | } |
3813 | 3899 | ||
3814 | rc = iwl_power_set_user_mode(priv, mode); | 3900 | ret = iwl_power_set_user_mode(priv, mode); |
3815 | if (rc) { | 3901 | if (ret) { |
3816 | IWL_DEBUG_MAC80211("failed setting power mode.\n"); | 3902 | IWL_DEBUG_MAC80211("failed setting power mode.\n"); |
3817 | goto out; | 3903 | goto out; |
3818 | } | 3904 | } |
3819 | rc = count; | 3905 | ret = count; |
3820 | 3906 | ||
3821 | out: | 3907 | out: |
3822 | mutex_unlock(&priv->mutex); | 3908 | mutex_unlock(&priv->mutex); |
3823 | return rc; | 3909 | return ret; |
3824 | } | 3910 | } |
3825 | 3911 | ||
3826 | #define MAX_WX_STRING 80 | ||
3827 | |||
3828 | /* Values are in microsecond */ | ||
3829 | static const s32 timeout_duration[] = { | ||
3830 | 350000, | ||
3831 | 250000, | ||
3832 | 75000, | ||
3833 | 37000, | ||
3834 | 25000, | ||
3835 | }; | ||
3836 | static const s32 period_duration[] = { | ||
3837 | 400000, | ||
3838 | 700000, | ||
3839 | 1000000, | ||
3840 | 1000000, | ||
3841 | 1000000 | ||
3842 | }; | ||
3843 | |||
3844 | static ssize_t show_power_level(struct device *d, | 3912 | static ssize_t show_power_level(struct device *d, |
3845 | struct device_attribute *attr, char *buf) | 3913 | struct device_attribute *attr, char *buf) |
3846 | { | 3914 | { |
3847 | struct iwl_priv *priv = dev_get_drvdata(d); | 3915 | struct iwl_priv *priv = dev_get_drvdata(d); |
3916 | int mode = priv->power_data.user_power_setting; | ||
3917 | int system = priv->power_data.system_power_setting; | ||
3848 | int level = priv->power_data.power_mode; | 3918 | int level = priv->power_data.power_mode; |
3849 | char *p = buf; | 3919 | char *p = buf; |
3850 | 3920 | ||
3851 | p += sprintf(p, "%d ", level); | 3921 | switch (system) { |
3852 | switch (level) { | 3922 | case IWL_POWER_SYS_AUTO: |
3853 | case IWL_POWER_MODE_CAM: | 3923 | p += sprintf(p, "SYSTEM:auto"); |
3854 | case IWL_POWER_AC: | ||
3855 | p += sprintf(p, "(AC)"); | ||
3856 | break; | 3924 | break; |
3857 | case IWL_POWER_BATTERY: | 3925 | case IWL_POWER_SYS_AC: |
3858 | p += sprintf(p, "(BATTERY)"); | 3926 | p += sprintf(p, "SYSTEM:ac"); |
3927 | break; | ||
3928 | case IWL_POWER_SYS_BATTERY: | ||
3929 | p += sprintf(p, "SYSTEM:battery"); | ||
3859 | break; | 3930 | break; |
3860 | default: | ||
3861 | p += sprintf(p, | ||
3862 | "(Timeout %dms, Period %dms)", | ||
3863 | timeout_duration[level - 1] / 1000, | ||
3864 | period_duration[level - 1] / 1000); | ||
3865 | } | 3931 | } |
3866 | /* | 3932 | |
3867 | if (!(priv->power_mode & IWL_POWER_ENABLED)) | 3933 | p += sprintf(p, "\tMODE:%s", (mode < IWL_POWER_AUTO)?"fixed":"auto"); |
3868 | p += sprintf(p, " OFF\n"); | 3934 | p += sprintf(p, "\tINDEX:%d", level); |
3869 | else | 3935 | p += sprintf(p, "\n"); |
3870 | p += sprintf(p, " \n"); | 3936 | return p - buf + 1; |
3871 | */ | ||
3872 | p += sprintf(p, " \n"); | ||
3873 | return (p - buf + 1); | ||
3874 | } | 3937 | } |
3875 | 3938 | ||
3876 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, | 3939 | static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level, |
@@ -3945,7 +4008,7 @@ static ssize_t show_statistics(struct device *d, | |||
3945 | struct iwl_priv *priv = dev_get_drvdata(d); | 4008 | struct iwl_priv *priv = dev_get_drvdata(d); |
3946 | u32 size = sizeof(struct iwl_notif_statistics); | 4009 | u32 size = sizeof(struct iwl_notif_statistics); |
3947 | u32 len = 0, ofs = 0; | 4010 | u32 len = 0, ofs = 0; |
3948 | u8 *data = (u8 *) & priv->statistics; | 4011 | u8 *data = (u8 *)&priv->statistics; |
3949 | int rc = 0; | 4012 | int rc = 0; |
3950 | 4013 | ||
3951 | if (!iwl_is_alive(priv)) | 4014 | if (!iwl_is_alive(priv)) |
@@ -4041,12 +4104,11 @@ static struct attribute *iwl4965_sysfs_entries[] = { | |||
4041 | &dev_attr_channels.attr, | 4104 | &dev_attr_channels.attr, |
4042 | &dev_attr_flags.attr, | 4105 | &dev_attr_flags.attr, |
4043 | &dev_attr_filter_flags.attr, | 4106 | &dev_attr_filter_flags.attr, |
4044 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT | 4107 | #ifdef CONFIG_IWLAGN_SPECTRUM_MEASUREMENT |
4045 | &dev_attr_measurement.attr, | 4108 | &dev_attr_measurement.attr, |
4046 | #endif | 4109 | #endif |
4047 | &dev_attr_power_level.attr, | 4110 | &dev_attr_power_level.attr, |
4048 | &dev_attr_retry_rate.attr, | 4111 | &dev_attr_retry_rate.attr, |
4049 | &dev_attr_rs_window.attr, | ||
4050 | &dev_attr_statistics.attr, | 4112 | &dev_attr_statistics.attr, |
4051 | &dev_attr_status.attr, | 4113 | &dev_attr_status.attr, |
4052 | &dev_attr_temperature.attr, | 4114 | &dev_attr_temperature.attr, |
@@ -4394,8 +4456,10 @@ static int iwl4965_pci_resume(struct pci_dev *pdev) | |||
4394 | 4456 | ||
4395 | /* Hardware specific file defines the PCI IDs table for that hardware module */ | 4457 | /* Hardware specific file defines the PCI IDs table for that hardware module */ |
4396 | static struct pci_device_id iwl_hw_card_ids[] = { | 4458 | static struct pci_device_id iwl_hw_card_ids[] = { |
4459 | #ifdef CONFIG_IWL4965 | ||
4397 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, | 4460 | {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)}, |
4398 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, | 4461 | {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)}, |
4462 | #endif /* CONFIG_IWL4965 */ | ||
4399 | #ifdef CONFIG_IWL5000 | 4463 | #ifdef CONFIG_IWL5000 |
4400 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)}, | 4464 | {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)}, |
4401 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)}, | 4465 | {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)}, |
@@ -4431,7 +4495,7 @@ static int __init iwl4965_init(void) | |||
4431 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); | 4495 | printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n"); |
4432 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); | 4496 | printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n"); |
4433 | 4497 | ||
4434 | ret = iwl4965_rate_control_register(); | 4498 | ret = iwlagn_rate_control_register(); |
4435 | if (ret) { | 4499 | if (ret) { |
4436 | IWL_ERROR("Unable to register rate control algorithm: %d\n", ret); | 4500 | IWL_ERROR("Unable to register rate control algorithm: %d\n", ret); |
4437 | return ret; | 4501 | return ret; |
@@ -4446,14 +4510,14 @@ static int __init iwl4965_init(void) | |||
4446 | return ret; | 4510 | return ret; |
4447 | 4511 | ||
4448 | error_register: | 4512 | error_register: |
4449 | iwl4965_rate_control_unregister(); | 4513 | iwlagn_rate_control_unregister(); |
4450 | return ret; | 4514 | return ret; |
4451 | } | 4515 | } |
4452 | 4516 | ||
4453 | static void __exit iwl4965_exit(void) | 4517 | static void __exit iwl4965_exit(void) |
4454 | { | 4518 | { |
4455 | pci_unregister_driver(&iwl_driver); | 4519 | pci_unregister_driver(&iwl_driver); |
4456 | iwl4965_rate_control_unregister(); | 4520 | iwlagn_rate_control_unregister(); |
4457 | } | 4521 | } |
4458 | 4522 | ||
4459 | module_exit(iwl4965_exit); | 4523 | module_exit(iwl4965_exit); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-commands.h b/drivers/net/wireless/iwlwifi/iwl-commands.h index e9bb1de0ce3f..28b5b09996ed 100644 --- a/drivers/net/wireless/iwlwifi/iwl-commands.h +++ b/drivers/net/wireless/iwlwifi/iwl-commands.h | |||
@@ -666,8 +666,7 @@ struct iwl4965_rxon_assoc_cmd { | |||
666 | __le16 reserved; | 666 | __le16 reserved; |
667 | } __attribute__ ((packed)); | 667 | } __attribute__ ((packed)); |
668 | 668 | ||
669 | 669 | #define IWL_CONN_MAX_LISTEN_INTERVAL 10 | |
670 | |||
671 | 670 | ||
672 | /* | 671 | /* |
673 | * REPLY_RXON_TIMING = 0x14 (command, has simple generic response) | 672 | * REPLY_RXON_TIMING = 0x14 (command, has simple generic response) |
@@ -1076,10 +1075,12 @@ struct iwl4965_rx_frame { | |||
1076 | } __attribute__ ((packed)); | 1075 | } __attribute__ ((packed)); |
1077 | 1076 | ||
1078 | /* Fixed (non-configurable) rx data from phy */ | 1077 | /* Fixed (non-configurable) rx data from phy */ |
1079 | #define RX_PHY_FLAGS_ANTENNAE_OFFSET (4) | 1078 | |
1080 | #define RX_PHY_FLAGS_ANTENNAE_MASK (0x70) | 1079 | #define IWL49_RX_RES_PHY_CNT 14 |
1081 | #define IWL_AGC_DB_MASK (0x3f80) /* MASK(7,13) */ | 1080 | #define IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET (4) |
1082 | #define IWL_AGC_DB_POS (7) | 1081 | #define IWL49_RX_PHY_FLAGS_ANTENNAE_MASK (0x70) |
1082 | #define IWL49_AGC_DB_MASK (0x3f80) /* MASK(7,13) */ | ||
1083 | #define IWL49_AGC_DB_POS (7) | ||
1083 | struct iwl4965_rx_non_cfg_phy { | 1084 | struct iwl4965_rx_non_cfg_phy { |
1084 | __le16 ant_selection; /* ant A bit 4, ant B bit 5, ant C bit 6 */ | 1085 | __le16 ant_selection; /* ant A bit 4, ant B bit 5, ant C bit 6 */ |
1085 | __le16 agc_info; /* agc code 0:6, agc dB 7:13, reserved 14:15 */ | 1086 | __le16 agc_info; /* agc code 0:6, agc dB 7:13, reserved 14:15 */ |
@@ -1087,12 +1088,30 @@ struct iwl4965_rx_non_cfg_phy { | |||
1087 | u8 pad[0]; | 1088 | u8 pad[0]; |
1088 | } __attribute__ ((packed)); | 1089 | } __attribute__ ((packed)); |
1089 | 1090 | ||
1091 | |||
1092 | #define IWL50_RX_RES_PHY_CNT 8 | ||
1093 | #define IWL50_RX_RES_AGC_IDX 1 | ||
1094 | #define IWL50_RX_RES_RSSI_AB_IDX 2 | ||
1095 | #define IWL50_RX_RES_RSSI_C_IDX 3 | ||
1096 | #define IWL50_OFDM_AGC_MSK 0xfe00 | ||
1097 | #define IWL50_OFDM_AGC_BIT_POS 9 | ||
1098 | #define IWL50_OFDM_RSSI_A_MSK 0x00ff | ||
1099 | #define IWL50_OFDM_RSSI_A_BIT_POS 0 | ||
1100 | #define IWL50_OFDM_RSSI_B_MSK 0xff0000 | ||
1101 | #define IWL50_OFDM_RSSI_B_BIT_POS 16 | ||
1102 | #define IWL50_OFDM_RSSI_C_MSK 0x00ff | ||
1103 | #define IWL50_OFDM_RSSI_C_BIT_POS 0 | ||
1104 | |||
1105 | struct iwl5000_non_cfg_phy { | ||
1106 | __le32 non_cfg_phy[IWL50_RX_RES_PHY_CNT]; /* upto 8 phy entries */ | ||
1107 | } __attribute__ ((packed)); | ||
1108 | |||
1109 | |||
1090 | /* | 1110 | /* |
1091 | * REPLY_RX = 0xc3 (response only, not a command) | 1111 | * REPLY_RX = 0xc3 (response only, not a command) |
1092 | * Used only for legacy (non 11n) frames. | 1112 | * Used only for legacy (non 11n) frames. |
1093 | */ | 1113 | */ |
1094 | #define RX_RES_PHY_CNT 14 | 1114 | struct iwl_rx_phy_res { |
1095 | struct iwl4965_rx_phy_res { | ||
1096 | u8 non_cfg_phy_cnt; /* non configurable DSP phy data byte count */ | 1115 | u8 non_cfg_phy_cnt; /* non configurable DSP phy data byte count */ |
1097 | u8 cfg_phy_cnt; /* configurable DSP phy data byte count */ | 1116 | u8 cfg_phy_cnt; /* configurable DSP phy data byte count */ |
1098 | u8 stat_id; /* configurable DSP phy data set ID */ | 1117 | u8 stat_id; /* configurable DSP phy data set ID */ |
@@ -1101,8 +1120,7 @@ struct iwl4965_rx_phy_res { | |||
1101 | __le32 beacon_time_stamp; /* beacon at on-air rise */ | 1120 | __le32 beacon_time_stamp; /* beacon at on-air rise */ |
1102 | __le16 phy_flags; /* general phy flags: band, modulation, ... */ | 1121 | __le16 phy_flags; /* general phy flags: band, modulation, ... */ |
1103 | __le16 channel; /* channel number */ | 1122 | __le16 channel; /* channel number */ |
1104 | __le16 non_cfg_phy[RX_RES_PHY_CNT]; /* upto 14 phy entries */ | 1123 | u8 non_cfg_phy_buf[32]; /* for various implementations of non_cfg_phy */ |
1105 | __le32 reserved2; | ||
1106 | __le32 rate_n_flags; /* RATE_MCS_* */ | 1124 | __le32 rate_n_flags; /* RATE_MCS_* */ |
1107 | __le16 byte_count; /* frame's byte-count */ | 1125 | __le16 byte_count; /* frame's byte-count */ |
1108 | __le16 reserved3; | 1126 | __le16 reserved3; |
@@ -1993,7 +2011,7 @@ struct iwl4965_spectrum_notification { | |||
1993 | *****************************************************************************/ | 2011 | *****************************************************************************/ |
1994 | 2012 | ||
1995 | /** | 2013 | /** |
1996 | * struct iwl4965_powertable_cmd - Power Table Command | 2014 | * struct iwl_powertable_cmd - Power Table Command |
1997 | * @flags: See below: | 2015 | * @flags: See below: |
1998 | * | 2016 | * |
1999 | * POWER_TABLE_CMD = 0x77 (command, has simple generic response) | 2017 | * POWER_TABLE_CMD = 0x77 (command, has simple generic response) |
@@ -2027,7 +2045,7 @@ struct iwl4965_spectrum_notification { | |||
2027 | #define IWL_POWER_PCI_PM_MSK __constant_cpu_to_le16(1 << 3) | 2045 | #define IWL_POWER_PCI_PM_MSK __constant_cpu_to_le16(1 << 3) |
2028 | #define IWL_POWER_FAST_PD __constant_cpu_to_le16(1 << 4) | 2046 | #define IWL_POWER_FAST_PD __constant_cpu_to_le16(1 << 4) |
2029 | 2047 | ||
2030 | struct iwl4965_powertable_cmd { | 2048 | struct iwl_powertable_cmd { |
2031 | __le16 flags; | 2049 | __le16 flags; |
2032 | u8 keep_alive_seconds; | 2050 | u8 keep_alive_seconds; |
2033 | u8 debug_flags; | 2051 | u8 debug_flags; |
@@ -2324,7 +2342,7 @@ struct iwl4965_beacon_notif { | |||
2324 | /* | 2342 | /* |
2325 | * REPLY_TX_BEACON = 0x91 (command, has simple generic response) | 2343 | * REPLY_TX_BEACON = 0x91 (command, has simple generic response) |
2326 | */ | 2344 | */ |
2327 | struct iwl4965_tx_beacon_cmd { | 2345 | struct iwl_tx_beacon_cmd { |
2328 | struct iwl_tx_cmd tx; | 2346 | struct iwl_tx_cmd tx; |
2329 | __le16 tim_idx; | 2347 | __le16 tim_idx; |
2330 | u8 tim_size; | 2348 | u8 tim_size; |
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c index e3427c205ccf..9bd61809129f 100644 --- a/drivers/net/wireless/iwlwifi/iwl-core.c +++ b/drivers/net/wireless/iwlwifi/iwl-core.c | |||
@@ -383,8 +383,8 @@ void iwl_reset_qos(struct iwl_priv *priv) | |||
383 | } | 383 | } |
384 | EXPORT_SYMBOL(iwl_reset_qos); | 384 | EXPORT_SYMBOL(iwl_reset_qos); |
385 | 385 | ||
386 | #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */ | 386 | #define MAX_BIT_RATE_40_MHZ 0x96 /* 150 Mbps */ |
387 | #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */ | 387 | #define MAX_BIT_RATE_20_MHZ 0x48 /* 72 Mbps */ |
388 | static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, | 388 | static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv, |
389 | struct ieee80211_ht_info *ht_info, | 389 | struct ieee80211_ht_info *ht_info, |
390 | enum ieee80211_band band) | 390 | enum ieee80211_band band) |
@@ -815,7 +815,7 @@ int iwl_setup_mac(struct iwl_priv *priv) | |||
815 | { | 815 | { |
816 | int ret; | 816 | int ret; |
817 | struct ieee80211_hw *hw = priv->hw; | 817 | struct ieee80211_hw *hw = priv->hw; |
818 | hw->rate_control_algorithm = "iwl-4965-rs"; | 818 | hw->rate_control_algorithm = "iwl-agn-rs"; |
819 | 819 | ||
820 | /* Tell mac80211 our characteristics */ | 820 | /* Tell mac80211 our characteristics */ |
821 | hw->flags = IEEE80211_HW_SIGNAL_DBM | | 821 | hw->flags = IEEE80211_HW_SIGNAL_DBM | |
@@ -827,6 +827,7 @@ int iwl_setup_mac(struct iwl_priv *priv) | |||
827 | hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues; | 827 | hw->ampdu_queues = priv->cfg->mod_params->num_of_ampdu_queues; |
828 | 828 | ||
829 | hw->conf.beacon_int = 100; | 829 | hw->conf.beacon_int = 100; |
830 | hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL; | ||
830 | 831 | ||
831 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) | 832 | if (priv->bands[IEEE80211_BAND_2GHZ].n_channels) |
832 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | 833 | priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.h b/drivers/net/wireless/iwlwifi/iwl-core.h index db66114f1e56..64f139e97444 100644 --- a/drivers/net/wireless/iwlwifi/iwl-core.h +++ b/drivers/net/wireless/iwlwifi/iwl-core.h | |||
@@ -95,6 +95,8 @@ struct iwl_hcmd_utils_ops { | |||
95 | void (*chain_noise_reset)(struct iwl_priv *priv); | 95 | void (*chain_noise_reset)(struct iwl_priv *priv); |
96 | void (*rts_tx_cmd_flag)(struct ieee80211_tx_info *info, | 96 | void (*rts_tx_cmd_flag)(struct ieee80211_tx_info *info, |
97 | __le32 *tx_flags); | 97 | __le32 *tx_flags); |
98 | int (*calc_rssi)(struct iwl_priv *priv, | ||
99 | struct iwl_rx_phy_res *rx_resp); | ||
98 | }; | 100 | }; |
99 | 101 | ||
100 | struct iwl_lib_ops { | 102 | struct iwl_lib_ops { |
@@ -139,7 +141,6 @@ struct iwl_lib_ops { | |||
139 | int (*set_pwr_src)(struct iwl_priv *priv, enum iwl_pwr_src src); | 141 | int (*set_pwr_src)(struct iwl_priv *priv, enum iwl_pwr_src src); |
140 | } apm_ops; | 142 | } apm_ops; |
141 | /* power */ | 143 | /* power */ |
142 | int (*set_power)(struct iwl_priv *priv, void *cmd); | ||
143 | int (*send_tx_power) (struct iwl_priv *priv); | 144 | int (*send_tx_power) (struct iwl_priv *priv); |
144 | void (*update_chain_flags)(struct iwl_priv *priv); | 145 | void (*update_chain_flags)(struct iwl_priv *priv); |
145 | void (*temperature) (struct iwl_priv *priv); | 146 | void (*temperature) (struct iwl_priv *priv); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h index 545ed692d889..52629fbd835a 100644 --- a/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/drivers/net/wireless/iwlwifi/iwl-csr.h | |||
@@ -104,6 +104,7 @@ | |||
104 | * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step | 104 | * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step |
105 | */ | 105 | */ |
106 | #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) | 106 | #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) |
107 | #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) | ||
107 | 108 | ||
108 | /* Bits for CSR_HW_IF_CONFIG_REG */ | 109 | /* Bits for CSR_HW_IF_CONFIG_REG */ |
109 | #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010) | 110 | #define CSR49_HW_IF_CONFIG_REG_BIT_4965_R (0x00000010) |
@@ -118,7 +119,12 @@ | |||
118 | #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) | 119 | #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000) |
119 | #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) | 120 | #define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000) |
120 | 121 | ||
121 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) | 122 | #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) |
123 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) | ||
124 | #define CSR_HW_IF_CONFIG_REG_BIT_PCI_OWN_SEM (0x00400000) | ||
125 | #define CSR_HW_IF_CONFIG_REG_BIT_ME_OWN (0x02000000) | ||
126 | #define CSR_HW_IF_CONFIG_REG_BIT_WAKE_ME (0x08000000) | ||
127 | |||
122 | 128 | ||
123 | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), | 129 | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), |
124 | * acknowledged (reset) by host writing "1" to flagged bits. */ | 130 | * acknowledged (reset) by host writing "1" to flagged bits. */ |
@@ -236,6 +242,8 @@ | |||
236 | #define CSR39_ANA_PLL_CFG_VAL (0x01000000) | 242 | #define CSR39_ANA_PLL_CFG_VAL (0x01000000) |
237 | #define CSR50_ANA_PLL_CFG_VAL (0x00880300) | 243 | #define CSR50_ANA_PLL_CFG_VAL (0x00880300) |
238 | 244 | ||
245 | /* HPET MEM debug */ | ||
246 | #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) | ||
239 | /*=== HBUS (Host-side Bus) ===*/ | 247 | /*=== HBUS (Host-side Bus) ===*/ |
240 | #define HBUS_BASE (0x400) | 248 | #define HBUS_BASE (0x400) |
241 | /* | 249 | /* |
diff --git a/drivers/net/wireless/iwlwifi/iwl-debug.h b/drivers/net/wireless/iwlwifi/iwl-debug.h index d6d729e86bdb..b4ffd33ef98c 100644 --- a/drivers/net/wireless/iwlwifi/iwl-debug.h +++ b/drivers/net/wireless/iwlwifi/iwl-debug.h | |||
@@ -33,12 +33,12 @@ | |||
33 | #define IWL_DEBUG(level, fmt, args...) \ | 33 | #define IWL_DEBUG(level, fmt, args...) \ |
34 | do { if (priv->debug_level & (level)) \ | 34 | do { if (priv->debug_level & (level)) \ |
35 | dev_printk(KERN_ERR, &(priv->hw->wiphy->dev), "%c %s " fmt, \ | 35 | dev_printk(KERN_ERR, &(priv->hw->wiphy->dev), "%c %s " fmt, \ |
36 | in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0) | 36 | in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0) |
37 | 37 | ||
38 | #define IWL_DEBUG_LIMIT(level, fmt, args...) \ | 38 | #define IWL_DEBUG_LIMIT(level, fmt, args...) \ |
39 | do { if ((priv->debug_level & (level)) && net_ratelimit()) \ | 39 | do { if ((priv->debug_level & (level)) && net_ratelimit()) \ |
40 | dev_printk(KERN_ERR, &(priv->hw->wiphy->dev), "%c %s " fmt, \ | 40 | dev_printk(KERN_ERR, &(priv->hw->wiphy->dev), "%c %s " fmt, \ |
41 | in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0) | 41 | in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0) |
42 | 42 | ||
43 | #ifdef CONFIG_IWLWIFI_DEBUGFS | 43 | #ifdef CONFIG_IWLWIFI_DEBUGFS |
44 | struct iwl_debugfs { | 44 | struct iwl_debugfs { |
diff --git a/drivers/net/wireless/iwlwifi/iwl-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-debugfs.c index ed948dc59b3d..20db0eb636a8 100644 --- a/drivers/net/wireless/iwlwifi/iwl-debugfs.c +++ b/drivers/net/wireless/iwlwifi/iwl-debugfs.c | |||
@@ -231,7 +231,7 @@ static ssize_t iwl_dbgfs_stations_read(struct file *file, char __user *user_buf, | |||
231 | DECLARE_MAC_BUF(mac); | 231 | DECLARE_MAC_BUF(mac); |
232 | 232 | ||
233 | buf = kmalloc(bufsz, GFP_KERNEL); | 233 | buf = kmalloc(bufsz, GFP_KERNEL); |
234 | if(!buf) | 234 | if (!buf) |
235 | return -ENOMEM; | 235 | return -ENOMEM; |
236 | 236 | ||
237 | pos += scnprintf(buf + pos, bufsz - pos, "num of stations: %d\n\n", | 237 | pos += scnprintf(buf + pos, bufsz - pos, "num of stations: %d\n\n", |
@@ -364,16 +364,19 @@ int iwl_dbgfs_register(struct iwl_priv *priv, const char *name) | |||
364 | { | 364 | { |
365 | struct iwl_debugfs *dbgfs; | 365 | struct iwl_debugfs *dbgfs; |
366 | struct dentry *phyd = priv->hw->wiphy->debugfsdir; | 366 | struct dentry *phyd = priv->hw->wiphy->debugfsdir; |
367 | int ret = 0; | ||
367 | 368 | ||
368 | dbgfs = kzalloc(sizeof(struct iwl_debugfs), GFP_KERNEL); | 369 | dbgfs = kzalloc(sizeof(struct iwl_debugfs), GFP_KERNEL); |
369 | if (!dbgfs) { | 370 | if (!dbgfs) { |
371 | ret = -ENOMEM; | ||
370 | goto err; | 372 | goto err; |
371 | } | 373 | } |
372 | 374 | ||
373 | priv->dbgfs = dbgfs; | 375 | priv->dbgfs = dbgfs; |
374 | dbgfs->name = name; | 376 | dbgfs->name = name; |
375 | dbgfs->dir_drv = debugfs_create_dir(name, phyd); | 377 | dbgfs->dir_drv = debugfs_create_dir(name, phyd); |
376 | if (!dbgfs->dir_drv || IS_ERR(dbgfs->dir_drv)){ | 378 | if (!dbgfs->dir_drv || IS_ERR(dbgfs->dir_drv)) { |
379 | ret = -ENOENT; | ||
377 | goto err; | 380 | goto err; |
378 | } | 381 | } |
379 | 382 | ||
@@ -394,7 +397,7 @@ int iwl_dbgfs_register(struct iwl_priv *priv, const char *name) | |||
394 | err: | 397 | err: |
395 | IWL_ERROR("Can't open the debugfs directory\n"); | 398 | IWL_ERROR("Can't open the debugfs directory\n"); |
396 | iwl_dbgfs_unregister(priv); | 399 | iwl_dbgfs_unregister(priv); |
397 | return -ENOENT; | 400 | return ret; |
398 | } | 401 | } |
399 | EXPORT_SYMBOL(iwl_dbgfs_register); | 402 | EXPORT_SYMBOL(iwl_dbgfs_register); |
400 | 403 | ||
@@ -404,7 +407,7 @@ EXPORT_SYMBOL(iwl_dbgfs_register); | |||
404 | */ | 407 | */ |
405 | void iwl_dbgfs_unregister(struct iwl_priv *priv) | 408 | void iwl_dbgfs_unregister(struct iwl_priv *priv) |
406 | { | 409 | { |
407 | if (!(priv->dbgfs)) | 410 | if (!priv->dbgfs) |
408 | return; | 411 | return; |
409 | 412 | ||
410 | DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_eeprom); | 413 | DEBUGFS_REMOVE(priv->dbgfs->dbgfs_data_files.file_eeprom); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-dev.h b/drivers/net/wireless/iwlwifi/iwl-dev.h index 4d789e353e3a..c19db438306c 100644 --- a/drivers/net/wireless/iwlwifi/iwl-dev.h +++ b/drivers/net/wireless/iwlwifi/iwl-dev.h | |||
@@ -36,7 +36,7 @@ | |||
36 | #include <linux/kernel.h> | 36 | #include <linux/kernel.h> |
37 | #include <net/ieee80211_radiotap.h> | 37 | #include <net/ieee80211_radiotap.h> |
38 | 38 | ||
39 | #define DRV_NAME "iwl4965" | 39 | #define DRV_NAME "iwlagn" |
40 | #include "iwl-rfkill.h" | 40 | #include "iwl-rfkill.h" |
41 | #include "iwl-eeprom.h" | 41 | #include "iwl-eeprom.h" |
42 | #include "iwl-4965-hw.h" | 42 | #include "iwl-4965-hw.h" |
@@ -45,6 +45,7 @@ | |||
45 | #include "iwl-debug.h" | 45 | #include "iwl-debug.h" |
46 | #include "iwl-led.h" | 46 | #include "iwl-led.h" |
47 | #include "iwl-power.h" | 47 | #include "iwl-power.h" |
48 | #include "iwl-agn-rs.h" | ||
48 | 49 | ||
49 | /* configuration for the iwl4965 */ | 50 | /* configuration for the iwl4965 */ |
50 | extern struct iwl_cfg iwl4965_agn_cfg; | 51 | extern struct iwl_cfg iwl4965_agn_cfg; |
@@ -134,8 +135,7 @@ struct iwl_tx_info { | |||
134 | struct iwl_tx_queue { | 135 | struct iwl_tx_queue { |
135 | struct iwl_queue q; | 136 | struct iwl_queue q; |
136 | struct iwl_tfd_frame *bd; | 137 | struct iwl_tfd_frame *bd; |
137 | struct iwl_cmd *cmd; | 138 | struct iwl_cmd *cmd[TFD_TX_CMD_SLOTS]; |
138 | dma_addr_t dma_addr_cmd; | ||
139 | struct iwl_tx_info *txb; | 139 | struct iwl_tx_info *txb; |
140 | int need_update; | 140 | int need_update; |
141 | int sched_retry; | 141 | int sched_retry; |
@@ -191,7 +191,6 @@ struct iwl4965_clip_group { | |||
191 | const s8 clip_powers[IWL_MAX_RATES]; | 191 | const s8 clip_powers[IWL_MAX_RATES]; |
192 | }; | 192 | }; |
193 | 193 | ||
194 | #include "iwl-4965-rs.h" | ||
195 | 194 | ||
196 | #define IWL_TX_FIFO_AC0 0 | 195 | #define IWL_TX_FIFO_AC0 0 |
197 | #define IWL_TX_FIFO_AC1 1 | 196 | #define IWL_TX_FIFO_AC1 1 |
@@ -219,7 +218,7 @@ enum iwl_pwr_src { | |||
219 | struct iwl_frame { | 218 | struct iwl_frame { |
220 | union { | 219 | union { |
221 | struct ieee80211_hdr frame; | 220 | struct ieee80211_hdr frame; |
222 | struct iwl4965_tx_beacon_cmd beacon; | 221 | struct iwl_tx_beacon_cmd beacon; |
223 | u8 raw[IEEE80211_FRAME_LEN]; | 222 | u8 raw[IEEE80211_FRAME_LEN]; |
224 | u8 cmd[360]; | 223 | u8 cmd[360]; |
225 | } u; | 224 | } u; |
@@ -283,10 +282,9 @@ struct iwl_cmd { | |||
283 | u32 val32; | 282 | u32 val32; |
284 | struct iwl4965_bt_cmd bt; | 283 | struct iwl4965_bt_cmd bt; |
285 | struct iwl4965_rxon_time_cmd rxon_time; | 284 | struct iwl4965_rxon_time_cmd rxon_time; |
286 | struct iwl4965_powertable_cmd powertable; | 285 | struct iwl_powertable_cmd powertable; |
287 | struct iwl_qosparam_cmd qosparam; | 286 | struct iwl_qosparam_cmd qosparam; |
288 | struct iwl_tx_cmd tx; | 287 | struct iwl_tx_cmd tx; |
289 | struct iwl4965_tx_beacon_cmd tx_beacon; | ||
290 | struct iwl4965_rxon_assoc_cmd rxon_assoc; | 288 | struct iwl4965_rxon_assoc_cmd rxon_assoc; |
291 | struct iwl_rem_sta_cmd rm_sta; | 289 | struct iwl_rem_sta_cmd rm_sta; |
292 | u8 *indirect; | 290 | u8 *indirect; |
@@ -590,6 +588,7 @@ extern unsigned int iwl4965_fill_beacon_frame(struct iwl_priv *priv, | |||
590 | const u8 *dest, int left); | 588 | const u8 *dest, int left); |
591 | extern void iwl4965_update_chain_flags(struct iwl_priv *priv); | 589 | extern void iwl4965_update_chain_flags(struct iwl_priv *priv); |
592 | int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src); | 590 | int iwl4965_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src); |
591 | extern int iwl4965_set_power(struct iwl_priv *priv, void *cmd); | ||
593 | 592 | ||
594 | extern const u8 iwl_bcast_addr[ETH_ALEN]; | 593 | extern const u8 iwl_bcast_addr[ETH_ALEN]; |
595 | 594 | ||
@@ -642,10 +641,6 @@ struct iwl_priv; | |||
642 | * Forward declare iwl-4965.c functions for iwl-base.c | 641 | * Forward declare iwl-4965.c functions for iwl-base.c |
643 | */ | 642 | */ |
644 | extern void iwl4965_rf_kill_ct_config(struct iwl_priv *priv); | 643 | extern void iwl4965_rf_kill_ct_config(struct iwl_priv *priv); |
645 | |||
646 | int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw, | ||
647 | enum ieee80211_ampdu_mlme_action action, | ||
648 | const u8 *addr, u16 tid, u16 *ssn); | ||
649 | int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id, | 644 | int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id, |
650 | u8 tid, int txq_id); | 645 | u8 tid, int txq_id); |
651 | 646 | ||
@@ -812,14 +807,11 @@ struct iwl_chain_noise_data { | |||
812 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ | 807 | #define EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ |
813 | 808 | ||
814 | 809 | ||
815 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT | ||
816 | |||
817 | enum { | 810 | enum { |
818 | MEASUREMENT_READY = (1 << 0), | 811 | MEASUREMENT_READY = (1 << 0), |
819 | MEASUREMENT_ACTIVE = (1 << 1), | 812 | MEASUREMENT_ACTIVE = (1 << 1), |
820 | }; | 813 | }; |
821 | 814 | ||
822 | #endif | ||
823 | 815 | ||
824 | #define IWL_MAX_NUM_QUEUES 20 /* FIXME: do dynamic allocation */ | 816 | #define IWL_MAX_NUM_QUEUES 20 /* FIXME: do dynamic allocation */ |
825 | 817 | ||
@@ -844,7 +836,7 @@ struct iwl_priv { | |||
844 | 836 | ||
845 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; | 837 | struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS]; |
846 | 838 | ||
847 | #ifdef CONFIG_IWL4965_SPECTRUM_MEASUREMENT | 839 | #ifdef CONFIG_IWLAGN_SPECTRUM_MEASUREMENT |
848 | /* spectrum measurement report caching */ | 840 | /* spectrum measurement report caching */ |
849 | struct iwl4965_spectrum_notification measure_report; | 841 | struct iwl4965_spectrum_notification measure_report; |
850 | u8 measurement_status; | 842 | u8 measurement_status; |
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c index 4a08a1b50979..bce53830b301 100644 --- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c +++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c | |||
@@ -273,8 +273,7 @@ EXPORT_SYMBOL(iwl_eeprom_init); | |||
273 | 273 | ||
274 | void iwl_eeprom_free(struct iwl_priv *priv) | 274 | void iwl_eeprom_free(struct iwl_priv *priv) |
275 | { | 275 | { |
276 | if(priv->eeprom) | 276 | kfree(priv->eeprom); |
277 | kfree(priv->eeprom); | ||
278 | priv->eeprom = NULL; | 277 | priv->eeprom = NULL; |
279 | } | 278 | } |
280 | EXPORT_SYMBOL(iwl_eeprom_free); | 279 | EXPORT_SYMBOL(iwl_eeprom_free); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-hcmd.c b/drivers/net/wireless/iwlwifi/iwl-hcmd.c index 8fa991b7202a..6512834bb916 100644 --- a/drivers/net/wireless/iwlwifi/iwl-hcmd.c +++ b/drivers/net/wireless/iwlwifi/iwl-hcmd.c | |||
@@ -228,7 +228,7 @@ cancel: | |||
228 | * TX cmd queue. Otherwise in case the cmd comes | 228 | * TX cmd queue. Otherwise in case the cmd comes |
229 | * in later, it will possibly set an invalid | 229 | * in later, it will possibly set an invalid |
230 | * address (cmd->meta.source). */ | 230 | * address (cmd->meta.source). */ |
231 | qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx]; | 231 | qcmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx]; |
232 | qcmd->meta.flags &= ~CMD_WANT_SKB; | 232 | qcmd->meta.flags &= ~CMD_WANT_SKB; |
233 | } | 233 | } |
234 | fail: | 234 | fail: |
diff --git a/drivers/net/wireless/iwlwifi/iwl-led.c b/drivers/net/wireless/iwlwifi/iwl-led.c index 61250e6a7d1b..cb11c4a4d691 100644 --- a/drivers/net/wireless/iwlwifi/iwl-led.c +++ b/drivers/net/wireless/iwlwifi/iwl-led.c | |||
@@ -161,12 +161,32 @@ int iwl4965_led_off(struct iwl_priv *priv, int led_id) | |||
161 | /* Set led register off */ | 161 | /* Set led register off */ |
162 | static int iwl4965_led_off_reg(struct iwl_priv *priv, int led_id) | 162 | static int iwl4965_led_off_reg(struct iwl_priv *priv, int led_id) |
163 | { | 163 | { |
164 | IWL_DEBUG_LED("radio off\n"); | 164 | IWL_DEBUG_LED("LED Reg off\n"); |
165 | iwl_write32(priv, CSR_LED_REG, CSR_LED_REG_TRUN_OFF); | 165 | iwl_write32(priv, CSR_LED_REG, CSR_LED_REG_TRUN_OFF); |
166 | return 0; | 166 | return 0; |
167 | } | 167 | } |
168 | 168 | ||
169 | /* | 169 | /* |
170 | * Set led register in case of disassociation according to rfkill state | ||
171 | */ | ||
172 | static int iwl_led_associate(struct iwl_priv *priv, int led_id) | ||
173 | { | ||
174 | IWL_DEBUG_LED("Associated\n"); | ||
175 | priv->allow_blinking = 1; | ||
176 | return iwl4965_led_on_reg(priv, led_id); | ||
177 | } | ||
178 | static int iwl_led_disassociate(struct iwl_priv *priv, int led_id) | ||
179 | { | ||
180 | priv->allow_blinking = 0; | ||
181 | if (iwl_is_rfkill(priv)) | ||
182 | iwl4965_led_off_reg(priv, led_id); | ||
183 | else | ||
184 | iwl4965_led_on_reg(priv, led_id); | ||
185 | |||
186 | return 0; | ||
187 | } | ||
188 | |||
189 | /* | ||
170 | * brightness call back function for Tx/Rx LED | 190 | * brightness call back function for Tx/Rx LED |
171 | */ | 191 | */ |
172 | static int iwl_led_associated(struct iwl_priv *priv, int led_id) | 192 | static int iwl_led_associated(struct iwl_priv *priv, int led_id) |
@@ -199,16 +219,10 @@ static void iwl_led_brightness_set(struct led_classdev *led_cdev, | |||
199 | led_type_str[led->type], brightness); | 219 | led_type_str[led->type], brightness); |
200 | switch (brightness) { | 220 | switch (brightness) { |
201 | case LED_FULL: | 221 | case LED_FULL: |
202 | if (led->type == IWL_LED_TRG_ASSOC) | ||
203 | priv->allow_blinking = 1; | ||
204 | |||
205 | if (led->led_on) | 222 | if (led->led_on) |
206 | led->led_on(priv, IWL_LED_LINK); | 223 | led->led_on(priv, IWL_LED_LINK); |
207 | break; | 224 | break; |
208 | case LED_OFF: | 225 | case LED_OFF: |
209 | if (led->type == IWL_LED_TRG_ASSOC) | ||
210 | priv->allow_blinking = 0; | ||
211 | |||
212 | if (led->led_off) | 226 | if (led->led_off) |
213 | led->led_off(priv, IWL_LED_LINK); | 227 | led->led_off(priv, IWL_LED_LINK); |
214 | break; | 228 | break; |
@@ -228,12 +242,12 @@ static void iwl_led_brightness_set(struct led_classdev *led_cdev, | |||
228 | */ | 242 | */ |
229 | static int iwl_leds_register_led(struct iwl_priv *priv, struct iwl_led *led, | 243 | static int iwl_leds_register_led(struct iwl_priv *priv, struct iwl_led *led, |
230 | enum led_type type, u8 set_led, | 244 | enum led_type type, u8 set_led, |
231 | const char *name, char *trigger) | 245 | char *trigger) |
232 | { | 246 | { |
233 | struct device *device = wiphy_dev(priv->hw->wiphy); | 247 | struct device *device = wiphy_dev(priv->hw->wiphy); |
234 | int ret; | 248 | int ret; |
235 | 249 | ||
236 | led->led_dev.name = name; | 250 | led->led_dev.name = led->name; |
237 | led->led_dev.brightness_set = iwl_led_brightness_set; | 251 | led->led_dev.brightness_set = iwl_led_brightness_set; |
238 | led->led_dev.default_trigger = trigger; | 252 | led->led_dev.default_trigger = trigger; |
239 | 253 | ||
@@ -284,12 +298,6 @@ static int iwl_get_blink_rate(struct iwl_priv *priv) | |||
284 | return i; | 298 | return i; |
285 | } | 299 | } |
286 | 300 | ||
287 | static inline int is_rf_kill(struct iwl_priv *priv) | ||
288 | { | ||
289 | return test_bit(STATUS_RF_KILL_HW, &priv->status) || | ||
290 | test_bit(STATUS_RF_KILL_SW, &priv->status); | ||
291 | } | ||
292 | |||
293 | /* | 301 | /* |
294 | * this function called from handler. Since setting Led command can | 302 | * this function called from handler. Since setting Led command can |
295 | * happen very frequent we postpone led command to be called from | 303 | * happen very frequent we postpone led command to be called from |
@@ -303,7 +311,7 @@ void iwl_leds_background(struct iwl_priv *priv) | |||
303 | priv->last_blink_time = 0; | 311 | priv->last_blink_time = 0; |
304 | return; | 312 | return; |
305 | } | 313 | } |
306 | if (is_rf_kill(priv)) { | 314 | if (iwl_is_rfkill(priv)) { |
307 | priv->last_blink_time = 0; | 315 | priv->last_blink_time = 0; |
308 | return; | 316 | return; |
309 | } | 317 | } |
@@ -337,7 +345,6 @@ EXPORT_SYMBOL(iwl_leds_background); | |||
337 | int iwl_leds_register(struct iwl_priv *priv) | 345 | int iwl_leds_register(struct iwl_priv *priv) |
338 | { | 346 | { |
339 | char *trigger; | 347 | char *trigger; |
340 | char name[32]; | ||
341 | int ret; | 348 | int ret; |
342 | 349 | ||
343 | priv->last_blink_rate = 0; | 350 | priv->last_blink_rate = 0; |
@@ -346,7 +353,8 @@ int iwl_leds_register(struct iwl_priv *priv) | |||
346 | priv->allow_blinking = 0; | 353 | priv->allow_blinking = 0; |
347 | 354 | ||
348 | trigger = ieee80211_get_radio_led_name(priv->hw); | 355 | trigger = ieee80211_get_radio_led_name(priv->hw); |
349 | snprintf(name, sizeof(name), "iwl-%s:radio", | 356 | snprintf(priv->led[IWL_LED_TRG_RADIO].name, |
357 | sizeof(priv->led[IWL_LED_TRG_RADIO].name), "iwl-%s:radio", | ||
350 | wiphy_name(priv->hw->wiphy)); | 358 | wiphy_name(priv->hw->wiphy)); |
351 | 359 | ||
352 | priv->led[IWL_LED_TRG_RADIO].led_on = iwl4965_led_on_reg; | 360 | priv->led[IWL_LED_TRG_RADIO].led_on = iwl4965_led_on_reg; |
@@ -354,31 +362,33 @@ int iwl_leds_register(struct iwl_priv *priv) | |||
354 | priv->led[IWL_LED_TRG_RADIO].led_pattern = NULL; | 362 | priv->led[IWL_LED_TRG_RADIO].led_pattern = NULL; |
355 | 363 | ||
356 | ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_RADIO], | 364 | ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_RADIO], |
357 | IWL_LED_TRG_RADIO, 1, name, trigger); | 365 | IWL_LED_TRG_RADIO, 1, trigger); |
358 | if (ret) | 366 | if (ret) |
359 | goto exit_fail; | 367 | goto exit_fail; |
360 | 368 | ||
361 | trigger = ieee80211_get_assoc_led_name(priv->hw); | 369 | trigger = ieee80211_get_assoc_led_name(priv->hw); |
362 | snprintf(name, sizeof(name), "iwl-%s:assoc", | 370 | snprintf(priv->led[IWL_LED_TRG_ASSOC].name, |
371 | sizeof(priv->led[IWL_LED_TRG_ASSOC].name), "iwl-%s:assoc", | ||
363 | wiphy_name(priv->hw->wiphy)); | 372 | wiphy_name(priv->hw->wiphy)); |
364 | 373 | ||
365 | ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_ASSOC], | 374 | ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_ASSOC], |
366 | IWL_LED_TRG_ASSOC, 0, name, trigger); | 375 | IWL_LED_TRG_ASSOC, 0, trigger); |
367 | 376 | ||
368 | /* for assoc always turn led on */ | 377 | /* for assoc always turn led on */ |
369 | priv->led[IWL_LED_TRG_ASSOC].led_on = iwl4965_led_on_reg; | 378 | priv->led[IWL_LED_TRG_ASSOC].led_on = iwl_led_associate; |
370 | priv->led[IWL_LED_TRG_ASSOC].led_off = iwl4965_led_on_reg; | 379 | priv->led[IWL_LED_TRG_ASSOC].led_off = iwl_led_disassociate; |
371 | priv->led[IWL_LED_TRG_ASSOC].led_pattern = NULL; | 380 | priv->led[IWL_LED_TRG_ASSOC].led_pattern = NULL; |
372 | 381 | ||
373 | if (ret) | 382 | if (ret) |
374 | goto exit_fail; | 383 | goto exit_fail; |
375 | 384 | ||
376 | trigger = ieee80211_get_rx_led_name(priv->hw); | 385 | trigger = ieee80211_get_rx_led_name(priv->hw); |
377 | snprintf(name, sizeof(name), "iwl-%s:RX", wiphy_name(priv->hw->wiphy)); | 386 | snprintf(priv->led[IWL_LED_TRG_RX].name, |
378 | 387 | sizeof(priv->led[IWL_LED_TRG_RX].name), "iwl-%s:RX", | |
388 | wiphy_name(priv->hw->wiphy)); | ||
379 | 389 | ||
380 | ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_RX], | 390 | ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_RX], |
381 | IWL_LED_TRG_RX, 0, name, trigger); | 391 | IWL_LED_TRG_RX, 0, trigger); |
382 | 392 | ||
383 | priv->led[IWL_LED_TRG_RX].led_on = iwl_led_associated; | 393 | priv->led[IWL_LED_TRG_RX].led_on = iwl_led_associated; |
384 | priv->led[IWL_LED_TRG_RX].led_off = iwl_led_associated; | 394 | priv->led[IWL_LED_TRG_RX].led_off = iwl_led_associated; |
@@ -388,9 +398,12 @@ int iwl_leds_register(struct iwl_priv *priv) | |||
388 | goto exit_fail; | 398 | goto exit_fail; |
389 | 399 | ||
390 | trigger = ieee80211_get_tx_led_name(priv->hw); | 400 | trigger = ieee80211_get_tx_led_name(priv->hw); |
391 | snprintf(name, sizeof(name), "iwl-%s:TX", wiphy_name(priv->hw->wiphy)); | 401 | snprintf(priv->led[IWL_LED_TRG_TX].name, |
402 | sizeof(priv->led[IWL_LED_TRG_TX].name), "iwl-%s:TX", | ||
403 | wiphy_name(priv->hw->wiphy)); | ||
404 | |||
392 | ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_TX], | 405 | ret = iwl_leds_register_led(priv, &priv->led[IWL_LED_TRG_TX], |
393 | IWL_LED_TRG_TX, 0, name, trigger); | 406 | IWL_LED_TRG_TX, 0, trigger); |
394 | 407 | ||
395 | priv->led[IWL_LED_TRG_TX].led_on = iwl_led_associated; | 408 | priv->led[IWL_LED_TRG_TX].led_on = iwl_led_associated; |
396 | priv->led[IWL_LED_TRG_TX].led_off = iwl_led_associated; | 409 | priv->led[IWL_LED_TRG_TX].led_off = iwl_led_associated; |
diff --git a/drivers/net/wireless/iwlwifi/iwl-led.h b/drivers/net/wireless/iwlwifi/iwl-led.h index 1980ae5a7e82..588c9ad20e83 100644 --- a/drivers/net/wireless/iwlwifi/iwl-led.h +++ b/drivers/net/wireless/iwlwifi/iwl-led.h | |||
@@ -52,6 +52,7 @@ enum led_type { | |||
52 | struct iwl_led { | 52 | struct iwl_led { |
53 | struct iwl_priv *priv; | 53 | struct iwl_priv *priv; |
54 | struct led_classdev led_dev; | 54 | struct led_classdev led_dev; |
55 | char name[32]; | ||
55 | 56 | ||
56 | int (*led_on) (struct iwl_priv *priv, int led_id); | 57 | int (*led_on) (struct iwl_priv *priv, int led_id); |
57 | int (*led_off) (struct iwl_priv *priv, int led_id); | 58 | int (*led_off) (struct iwl_priv *priv, int led_id); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-power.c b/drivers/net/wireless/iwlwifi/iwl-power.c index 2e71803e09ba..028e3053c0ca 100644 --- a/drivers/net/wireless/iwlwifi/iwl-power.c +++ b/drivers/net/wireless/iwlwifi/iwl-power.c | |||
@@ -82,7 +82,7 @@ | |||
82 | 82 | ||
83 | /* default power management (not Tx power) table values */ | 83 | /* default power management (not Tx power) table values */ |
84 | /* for tim 0-10 */ | 84 | /* for tim 0-10 */ |
85 | static struct iwl_power_vec_entry range_0[IWL_POWER_AC] = { | 85 | static struct iwl_power_vec_entry range_0[IWL_POWER_MAX] = { |
86 | {{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, | 86 | {{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
87 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0}, | 87 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0}, |
88 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0}, | 88 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 2, 2, 0xFF)}, 0}, |
@@ -93,7 +93,7 @@ static struct iwl_power_vec_entry range_0[IWL_POWER_AC] = { | |||
93 | 93 | ||
94 | 94 | ||
95 | /* for tim = 3-10 */ | 95 | /* for tim = 3-10 */ |
96 | static struct iwl_power_vec_entry range_1[IWL_POWER_AC] = { | 96 | static struct iwl_power_vec_entry range_1[IWL_POWER_MAX] = { |
97 | {{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, | 97 | {{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
98 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, | 98 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0}, |
99 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0}, | 99 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(1, 2, 3, 4, 7)}, 0}, |
@@ -103,7 +103,7 @@ static struct iwl_power_vec_entry range_1[IWL_POWER_AC] = { | |||
103 | }; | 103 | }; |
104 | 104 | ||
105 | /* for tim > 11 */ | 105 | /* for tim > 11 */ |
106 | static struct iwl_power_vec_entry range_2[IWL_POWER_AC] = { | 106 | static struct iwl_power_vec_entry range_2[IWL_POWER_MAX] = { |
107 | {{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, | 107 | {{NOSLP, SLP_TOUT(0), SLP_TOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0}, |
108 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, | 108 | {{SLP, SLP_TOUT(200), SLP_TOUT(500), SLP_VEC(1, 2, 3, 4, 0xFF)}, 0}, |
109 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, | 109 | {{SLP, SLP_TOUT(200), SLP_TOUT(300), SLP_VEC(2, 4, 6, 7, 0xFF)}, 0}, |
@@ -112,12 +112,19 @@ static struct iwl_power_vec_entry range_2[IWL_POWER_AC] = { | |||
112 | {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} | 112 | {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0} |
113 | }; | 113 | }; |
114 | 114 | ||
115 | /* set card power command */ | ||
116 | static int iwl_set_power(struct iwl_priv *priv, void *cmd) | ||
117 | { | ||
118 | return iwl_send_cmd_pdu_async(priv, POWER_TABLE_CMD, | ||
119 | sizeof(struct iwl_powertable_cmd), | ||
120 | cmd, NULL); | ||
121 | } | ||
115 | /* decide the right power level according to association status | 122 | /* decide the right power level according to association status |
116 | * and battery status | 123 | * and battery status |
117 | */ | 124 | */ |
118 | static u16 iwl_get_auto_power_mode(struct iwl_priv *priv) | 125 | static u16 iwl_get_auto_power_mode(struct iwl_priv *priv) |
119 | { | 126 | { |
120 | u16 mode = priv->power_data.user_power_setting; | 127 | u16 mode; |
121 | 128 | ||
122 | switch (priv->power_data.user_power_setting) { | 129 | switch (priv->power_data.user_power_setting) { |
123 | case IWL_POWER_AUTO: | 130 | case IWL_POWER_AUTO: |
@@ -129,12 +136,16 @@ static u16 iwl_get_auto_power_mode(struct iwl_priv *priv) | |||
129 | else | 136 | else |
130 | mode = IWL_POWER_ON_AC_DISASSOC; | 137 | mode = IWL_POWER_ON_AC_DISASSOC; |
131 | break; | 138 | break; |
139 | /* FIXME: remove battery and ac from here */ | ||
132 | case IWL_POWER_BATTERY: | 140 | case IWL_POWER_BATTERY: |
133 | mode = IWL_POWER_INDEX_3; | 141 | mode = IWL_POWER_INDEX_3; |
134 | break; | 142 | break; |
135 | case IWL_POWER_AC: | 143 | case IWL_POWER_AC: |
136 | mode = IWL_POWER_MODE_CAM; | 144 | mode = IWL_POWER_MODE_CAM; |
137 | break; | 145 | break; |
146 | default: | ||
147 | mode = priv->power_data.user_power_setting; | ||
148 | break; | ||
138 | } | 149 | } |
139 | return mode; | 150 | return mode; |
140 | } | 151 | } |
@@ -144,7 +155,7 @@ static int iwl_power_init_handle(struct iwl_priv *priv) | |||
144 | { | 155 | { |
145 | int ret = 0, i; | 156 | int ret = 0, i; |
146 | struct iwl_power_mgr *pow_data; | 157 | struct iwl_power_mgr *pow_data; |
147 | int size = sizeof(struct iwl_power_vec_entry) * IWL_POWER_AC; | 158 | int size = sizeof(struct iwl_power_vec_entry) * IWL_POWER_MAX; |
148 | u16 pci_pm; | 159 | u16 pci_pm; |
149 | 160 | ||
150 | IWL_DEBUG_POWER("Initialize power \n"); | 161 | IWL_DEBUG_POWER("Initialize power \n"); |
@@ -162,11 +173,11 @@ static int iwl_power_init_handle(struct iwl_priv *priv) | |||
162 | if (ret != 0) | 173 | if (ret != 0) |
163 | return 0; | 174 | return 0; |
164 | else { | 175 | else { |
165 | struct iwl4965_powertable_cmd *cmd; | 176 | struct iwl_powertable_cmd *cmd; |
166 | 177 | ||
167 | IWL_DEBUG_POWER("adjust power command flags\n"); | 178 | IWL_DEBUG_POWER("adjust power command flags\n"); |
168 | 179 | ||
169 | for (i = 0; i < IWL_POWER_AC; i++) { | 180 | for (i = 0; i < IWL_POWER_MAX; i++) { |
170 | cmd = &pow_data->pwr_range_0[i].cmd; | 181 | cmd = &pow_data->pwr_range_0[i].cmd; |
171 | 182 | ||
172 | if (pci_pm & 0x1) | 183 | if (pci_pm & 0x1) |
@@ -180,7 +191,7 @@ static int iwl_power_init_handle(struct iwl_priv *priv) | |||
180 | 191 | ||
181 | /* adjust power command according to dtim period and power level*/ | 192 | /* adjust power command according to dtim period and power level*/ |
182 | static int iwl_update_power_command(struct iwl_priv *priv, | 193 | static int iwl_update_power_command(struct iwl_priv *priv, |
183 | struct iwl4965_powertable_cmd *cmd, | 194 | struct iwl_powertable_cmd *cmd, |
184 | u16 mode) | 195 | u16 mode) |
185 | { | 196 | { |
186 | int ret = 0, i; | 197 | int ret = 0, i; |
@@ -204,7 +215,7 @@ static int iwl_update_power_command(struct iwl_priv *priv, | |||
204 | range = &pow_data->pwr_range_2[0]; | 215 | range = &pow_data->pwr_range_2[0]; |
205 | 216 | ||
206 | period = pow_data->dtim_period; | 217 | period = pow_data->dtim_period; |
207 | memcpy(cmd, &range[mode].cmd, sizeof(struct iwl4965_powertable_cmd)); | 218 | memcpy(cmd, &range[mode].cmd, sizeof(struct iwl_powertable_cmd)); |
208 | 219 | ||
209 | if (period == 0) { | 220 | if (period == 0) { |
210 | period = 1; | 221 | period = 1; |
@@ -258,17 +269,18 @@ int iwl_power_update_mode(struct iwl_priv *priv, u8 refresh) | |||
258 | * else user level */ | 269 | * else user level */ |
259 | 270 | ||
260 | switch (setting->system_power_setting) { | 271 | switch (setting->system_power_setting) { |
261 | case IWL_POWER_AUTO: | 272 | case IWL_POWER_SYS_AUTO: |
262 | final_mode = iwl_get_auto_power_mode(priv); | 273 | final_mode = iwl_get_auto_power_mode(priv); |
263 | break; | 274 | break; |
264 | case IWL_POWER_BATTERY: | 275 | case IWL_POWER_SYS_BATTERY: |
265 | final_mode = IWL_POWER_INDEX_3; | 276 | final_mode = IWL_POWER_INDEX_3; |
266 | break; | 277 | break; |
267 | case IWL_POWER_AC: | 278 | case IWL_POWER_SYS_AC: |
268 | final_mode = IWL_POWER_MODE_CAM; | 279 | final_mode = IWL_POWER_MODE_CAM; |
269 | break; | 280 | break; |
270 | default: | 281 | default: |
271 | final_mode = setting->system_power_setting; | 282 | final_mode = IWL_POWER_INDEX_3; |
283 | WARN_ON(1); | ||
272 | } | 284 | } |
273 | 285 | ||
274 | if (setting->critical_power_setting > final_mode) | 286 | if (setting->critical_power_setting > final_mode) |
@@ -280,7 +292,7 @@ int iwl_power_update_mode(struct iwl_priv *priv, u8 refresh) | |||
280 | 292 | ||
281 | if (!iwl_is_rfkill(priv) && !setting->power_disabled && | 293 | if (!iwl_is_rfkill(priv) && !setting->power_disabled && |
282 | ((setting->power_mode != final_mode) || refresh)) { | 294 | ((setting->power_mode != final_mode) || refresh)) { |
283 | struct iwl4965_powertable_cmd cmd; | 295 | struct iwl_powertable_cmd cmd; |
284 | 296 | ||
285 | if (final_mode != IWL_POWER_MODE_CAM) | 297 | if (final_mode != IWL_POWER_MODE_CAM) |
286 | set_bit(STATUS_POWER_PMI, &priv->status); | 298 | set_bit(STATUS_POWER_PMI, &priv->status); |
@@ -291,8 +303,7 @@ int iwl_power_update_mode(struct iwl_priv *priv, u8 refresh) | |||
291 | if (final_mode == IWL_POWER_INDEX_5) | 303 | if (final_mode == IWL_POWER_INDEX_5) |
292 | cmd.flags |= IWL_POWER_FAST_PD; | 304 | cmd.flags |= IWL_POWER_FAST_PD; |
293 | 305 | ||
294 | if (priv->cfg->ops->lib->set_power) | 306 | ret = iwl_set_power(priv, &cmd); |
295 | ret = priv->cfg->ops->lib->set_power(priv, &cmd); | ||
296 | 307 | ||
297 | if (final_mode == IWL_POWER_MODE_CAM) | 308 | if (final_mode == IWL_POWER_MODE_CAM) |
298 | clear_bit(STATUS_POWER_PMI, &priv->status); | 309 | clear_bit(STATUS_POWER_PMI, &priv->status); |
@@ -388,7 +399,7 @@ void iwl_power_initialize(struct iwl_priv *priv) | |||
388 | iwl_power_init_handle(priv); | 399 | iwl_power_init_handle(priv); |
389 | priv->power_data.user_power_setting = IWL_POWER_AUTO; | 400 | priv->power_data.user_power_setting = IWL_POWER_AUTO; |
390 | priv->power_data.power_disabled = 0; | 401 | priv->power_data.power_disabled = 0; |
391 | priv->power_data.system_power_setting = IWL_POWER_AUTO; | 402 | priv->power_data.system_power_setting = IWL_POWER_SYS_AUTO; |
392 | priv->power_data.is_battery_active = 0; | 403 | priv->power_data.is_battery_active = 0; |
393 | priv->power_data.power_disabled = 0; | 404 | priv->power_data.power_disabled = 0; |
394 | priv->power_data.critical_power_setting = 0; | 405 | priv->power_data.critical_power_setting = 0; |
diff --git a/drivers/net/wireless/iwlwifi/iwl-power.h b/drivers/net/wireless/iwlwifi/iwl-power.h index b066724a1c2b..abcbbf96a84e 100644 --- a/drivers/net/wireless/iwlwifi/iwl-power.h +++ b/drivers/net/wireless/iwlwifi/iwl-power.h | |||
@@ -33,12 +33,25 @@ | |||
33 | 33 | ||
34 | struct iwl_priv; | 34 | struct iwl_priv; |
35 | 35 | ||
36 | #define IWL_POWER_MODE_CAM 0x00 /* Continuously Aware Mode, always on */ | 36 | enum { |
37 | #define IWL_POWER_INDEX_3 0x03 | 37 | IWL_POWER_MODE_CAM, /* Continuously Aware Mode, always on */ |
38 | #define IWL_POWER_INDEX_5 0x05 | 38 | IWL_POWER_INDEX_1, |
39 | #define IWL_POWER_AC 0x06 | 39 | IWL_POWER_INDEX_2, |
40 | #define IWL_POWER_BATTERY 0x07 | 40 | IWL_POWER_INDEX_3, |
41 | #define IWL_POWER_AUTO 0x08 | 41 | IWL_POWER_INDEX_4, |
42 | IWL_POWER_INDEX_5, | ||
43 | IWL_POWER_AUTO, | ||
44 | IWL_POWER_MAX = IWL_POWER_AUTO, | ||
45 | IWL_POWER_AC, | ||
46 | IWL_POWER_BATTERY, | ||
47 | }; | ||
48 | |||
49 | enum { | ||
50 | IWL_POWER_SYS_AUTO, | ||
51 | IWL_POWER_SYS_AC, | ||
52 | IWL_POWER_SYS_BATTERY, | ||
53 | }; | ||
54 | |||
42 | #define IWL_POWER_LIMIT 0x08 | 55 | #define IWL_POWER_LIMIT 0x08 |
43 | #define IWL_POWER_MASK 0x0F | 56 | #define IWL_POWER_MASK 0x0F |
44 | #define IWL_POWER_ENABLED 0x10 | 57 | #define IWL_POWER_ENABLED 0x10 |
@@ -46,15 +59,15 @@ struct iwl_priv; | |||
46 | /* Power management (not Tx power) structures */ | 59 | /* Power management (not Tx power) structures */ |
47 | 60 | ||
48 | struct iwl_power_vec_entry { | 61 | struct iwl_power_vec_entry { |
49 | struct iwl4965_powertable_cmd cmd; | 62 | struct iwl_powertable_cmd cmd; |
50 | u8 no_dtim; | 63 | u8 no_dtim; |
51 | }; | 64 | }; |
52 | 65 | ||
53 | struct iwl_power_mgr { | 66 | struct iwl_power_mgr { |
54 | spinlock_t lock; | 67 | spinlock_t lock; |
55 | struct iwl_power_vec_entry pwr_range_0[IWL_POWER_AC]; | 68 | struct iwl_power_vec_entry pwr_range_0[IWL_POWER_MAX]; |
56 | struct iwl_power_vec_entry pwr_range_1[IWL_POWER_AC]; | 69 | struct iwl_power_vec_entry pwr_range_1[IWL_POWER_MAX]; |
57 | struct iwl_power_vec_entry pwr_range_2[IWL_POWER_AC]; | 70 | struct iwl_power_vec_entry pwr_range_2[IWL_POWER_MAX]; |
58 | u32 dtim_period; | 71 | u32 dtim_period; |
59 | /* final power level that used to calculate final power command */ | 72 | /* final power level that used to calculate final power command */ |
60 | u8 power_mode; | 73 | u8 power_mode; |
diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h index 70d9c7568b98..ee5afd48d3af 100644 --- a/drivers/net/wireless/iwlwifi/iwl-prph.h +++ b/drivers/net/wireless/iwlwifi/iwl-prph.h | |||
@@ -84,14 +84,16 @@ | |||
84 | #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) | 84 | #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) |
85 | #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) | 85 | #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) |
86 | 86 | ||
87 | #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) | ||
88 | 87 | ||
89 | #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) | 88 | #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) |
89 | #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) | ||
90 | #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) | ||
91 | #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) | ||
92 | #define APMG_PS_CTRL_VAL_PWR_SRC_MAX (0x01000000) /* 3945 only */ | ||
93 | #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) | ||
90 | 94 | ||
91 | #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) | ||
92 | #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) | ||
93 | #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x01000000) | ||
94 | 95 | ||
96 | #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) | ||
95 | 97 | ||
96 | /** | 98 | /** |
97 | * BSM (Bootstrap State Machine) | 99 | * BSM (Bootstrap State Machine) |
diff --git a/drivers/net/wireless/iwlwifi/iwl-rx.c b/drivers/net/wireless/iwlwifi/iwl-rx.c index e2d9afba38a5..f3f6ea49fdd2 100644 --- a/drivers/net/wireless/iwlwifi/iwl-rx.c +++ b/drivers/net/wireless/iwlwifi/iwl-rx.c | |||
@@ -791,7 +791,7 @@ static inline void iwl_dbg_report_frame(struct iwl_priv *priv, | |||
791 | 791 | ||
792 | static void iwl_add_radiotap(struct iwl_priv *priv, | 792 | static void iwl_add_radiotap(struct iwl_priv *priv, |
793 | struct sk_buff *skb, | 793 | struct sk_buff *skb, |
794 | struct iwl4965_rx_phy_res *rx_start, | 794 | struct iwl_rx_phy_res *rx_start, |
795 | struct ieee80211_rx_status *stats, | 795 | struct ieee80211_rx_status *stats, |
796 | u32 ampdu_status) | 796 | u32 ampdu_status) |
797 | { | 797 | { |
@@ -1010,8 +1010,8 @@ static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv, | |||
1010 | struct ieee80211_rx_status *stats) | 1010 | struct ieee80211_rx_status *stats) |
1011 | { | 1011 | { |
1012 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | 1012 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
1013 | struct iwl4965_rx_phy_res *rx_start = (include_phy) ? | 1013 | struct iwl_rx_phy_res *rx_start = (include_phy) ? |
1014 | (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL; | 1014 | (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) : NULL; |
1015 | struct ieee80211_hdr *hdr; | 1015 | struct ieee80211_hdr *hdr; |
1016 | u16 len; | 1016 | u16 len; |
1017 | __le32 *rx_end; | 1017 | __le32 *rx_end; |
@@ -1020,7 +1020,7 @@ static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv, | |||
1020 | u32 ampdu_status_legacy; | 1020 | u32 ampdu_status_legacy; |
1021 | 1021 | ||
1022 | if (!include_phy && priv->last_phy_res[0]) | 1022 | if (!include_phy && priv->last_phy_res[0]) |
1023 | rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1]; | 1023 | rx_start = (struct iwl_rx_phy_res *)&priv->last_phy_res[1]; |
1024 | 1024 | ||
1025 | if (!rx_start) { | 1025 | if (!rx_start) { |
1026 | IWL_ERROR("MPDU frame without a PHY data\n"); | 1026 | IWL_ERROR("MPDU frame without a PHY data\n"); |
@@ -1032,8 +1032,8 @@ static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv, | |||
1032 | 1032 | ||
1033 | len = le16_to_cpu(rx_start->byte_count); | 1033 | len = le16_to_cpu(rx_start->byte_count); |
1034 | 1034 | ||
1035 | rx_end = (__le32 *) ((u8 *) &pkt->u.raw[0] + | 1035 | rx_end = (__le32 *)((u8 *) &pkt->u.raw[0] + |
1036 | sizeof(struct iwl4965_rx_phy_res) + | 1036 | sizeof(struct iwl_rx_phy_res) + |
1037 | rx_start->cfg_phy_cnt + len); | 1037 | rx_start->cfg_phy_cnt + len); |
1038 | 1038 | ||
1039 | } else { | 1039 | } else { |
@@ -1084,40 +1084,13 @@ static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv, | |||
1084 | } | 1084 | } |
1085 | 1085 | ||
1086 | /* Calc max signal level (dBm) among 3 possible receivers */ | 1086 | /* Calc max signal level (dBm) among 3 possible receivers */ |
1087 | static int iwl_calc_rssi(struct iwl_priv *priv, | 1087 | static inline int iwl_calc_rssi(struct iwl_priv *priv, |
1088 | struct iwl4965_rx_phy_res *rx_resp) | 1088 | struct iwl_rx_phy_res *rx_resp) |
1089 | { | 1089 | { |
1090 | /* data from PHY/DSP regarding signal strength, etc., | 1090 | return priv->cfg->ops->utils->calc_rssi(priv, rx_resp); |
1091 | * contents are always there, not configurable by host. */ | ||
1092 | struct iwl4965_rx_non_cfg_phy *ncphy = | ||
1093 | (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy; | ||
1094 | u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK) | ||
1095 | >> IWL_AGC_DB_POS; | ||
1096 | |||
1097 | u32 valid_antennae = | ||
1098 | (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK) | ||
1099 | >> RX_PHY_FLAGS_ANTENNAE_OFFSET; | ||
1100 | u8 max_rssi = 0; | ||
1101 | u32 i; | ||
1102 | |||
1103 | /* Find max rssi among 3 possible receivers. | ||
1104 | * These values are measured by the digital signal processor (DSP). | ||
1105 | * They should stay fairly constant even as the signal strength varies, | ||
1106 | * if the radio's automatic gain control (AGC) is working right. | ||
1107 | * AGC value (see below) will provide the "interesting" info. */ | ||
1108 | for (i = 0; i < 3; i++) | ||
1109 | if (valid_antennae & (1 << i)) | ||
1110 | max_rssi = max(ncphy->rssi_info[i << 1], max_rssi); | ||
1111 | |||
1112 | IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", | ||
1113 | ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4], | ||
1114 | max_rssi, agc); | ||
1115 | |||
1116 | /* dBm = max_rssi dB - agc dB - constant. | ||
1117 | * Higher AGC (higher radio gain) means lower signal. */ | ||
1118 | return max_rssi - agc - IWL_RSSI_OFFSET; | ||
1119 | } | 1091 | } |
1120 | 1092 | ||
1093 | |||
1121 | static void iwl_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id) | 1094 | static void iwl_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id) |
1122 | { | 1095 | { |
1123 | unsigned long flags; | 1096 | unsigned long flags; |
@@ -1180,9 +1153,9 @@ void iwl_rx_reply_rx(struct iwl_priv *priv, | |||
1180 | * this rx packet for legacy frames, | 1153 | * this rx packet for legacy frames, |
1181 | * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */ | 1154 | * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */ |
1182 | int include_phy = (pkt->hdr.cmd == REPLY_RX); | 1155 | int include_phy = (pkt->hdr.cmd == REPLY_RX); |
1183 | struct iwl4965_rx_phy_res *rx_start = (include_phy) ? | 1156 | struct iwl_rx_phy_res *rx_start = (include_phy) ? |
1184 | (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : | 1157 | (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) : |
1185 | (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1]; | 1158 | (struct iwl_rx_phy_res *)&priv->last_phy_res[1]; |
1186 | __le32 *rx_end; | 1159 | __le32 *rx_end; |
1187 | unsigned int len = 0; | 1160 | unsigned int len = 0; |
1188 | u16 fc; | 1161 | u16 fc; |
@@ -1210,7 +1183,7 @@ void iwl_rx_reply_rx(struct iwl_priv *priv, | |||
1210 | 1183 | ||
1211 | if (!include_phy) { | 1184 | if (!include_phy) { |
1212 | if (priv->last_phy_res[0]) | 1185 | if (priv->last_phy_res[0]) |
1213 | rx_start = (struct iwl4965_rx_phy_res *) | 1186 | rx_start = (struct iwl_rx_phy_res *) |
1214 | &priv->last_phy_res[1]; | 1187 | &priv->last_phy_res[1]; |
1215 | else | 1188 | else |
1216 | rx_start = NULL; | 1189 | rx_start = NULL; |
@@ -1227,7 +1200,7 @@ void iwl_rx_reply_rx(struct iwl_priv *priv, | |||
1227 | 1200 | ||
1228 | len = le16_to_cpu(rx_start->byte_count); | 1201 | len = le16_to_cpu(rx_start->byte_count); |
1229 | rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt + | 1202 | rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt + |
1230 | sizeof(struct iwl4965_rx_phy_res) + len); | 1203 | sizeof(struct iwl_rx_phy_res) + len); |
1231 | } else { | 1204 | } else { |
1232 | struct iwl4965_rx_mpdu_res_start *amsdu = | 1205 | struct iwl4965_rx_mpdu_res_start *amsdu = |
1233 | (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw; | 1206 | (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw; |
@@ -1316,6 +1289,6 @@ void iwl_rx_reply_rx_phy(struct iwl_priv *priv, | |||
1316 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | 1289 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
1317 | priv->last_phy_res[0] = 1; | 1290 | priv->last_phy_res[0] = 1; |
1318 | memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]), | 1291 | memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]), |
1319 | sizeof(struct iwl4965_rx_phy_res)); | 1292 | sizeof(struct iwl_rx_phy_res)); |
1320 | } | 1293 | } |
1321 | EXPORT_SYMBOL(iwl_rx_reply_rx_phy); | 1294 | EXPORT_SYMBOL(iwl_rx_reply_rx_phy); |
diff --git a/drivers/net/wireless/iwlwifi/iwl-scan.c b/drivers/net/wireless/iwlwifi/iwl-scan.c index 5a00ac23e2d0..9bb6adb28b73 100644 --- a/drivers/net/wireless/iwlwifi/iwl-scan.c +++ b/drivers/net/wireless/iwlwifi/iwl-scan.c | |||
@@ -202,6 +202,7 @@ static int iwl_send_scan_abort(struct iwl_priv *priv) | |||
202 | clear_bit(STATUS_SCAN_HW, &priv->status); | 202 | clear_bit(STATUS_SCAN_HW, &priv->status); |
203 | } | 203 | } |
204 | 204 | ||
205 | priv->alloc_rxb_skb--; | ||
205 | dev_kfree_skb_any(cmd.meta.u.skb); | 206 | dev_kfree_skb_any(cmd.meta.u.skb); |
206 | 207 | ||
207 | return ret; | 208 | return ret; |
diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.c b/drivers/net/wireless/iwlwifi/iwl-sta.c index 6d1467d0bd9d..60a6e0106036 100644 --- a/drivers/net/wireless/iwlwifi/iwl-sta.c +++ b/drivers/net/wireless/iwlwifi/iwl-sta.c | |||
@@ -823,7 +823,7 @@ int iwl_send_lq_cmd(struct iwl_priv *priv, | |||
823 | if (lq->sta_id == 0xFF) | 823 | if (lq->sta_id == 0xFF) |
824 | lq->sta_id = IWL_AP_ID; | 824 | lq->sta_id = IWL_AP_ID; |
825 | 825 | ||
826 | iwl_dump_lq_cmd(priv,lq); | 826 | iwl_dump_lq_cmd(priv, lq); |
827 | 827 | ||
828 | if (iwl_is_associated(priv) && priv->assoc_station_added) | 828 | if (iwl_is_associated(priv) && priv->assoc_station_added) |
829 | return iwl_send_cmd(priv, &cmd); | 829 | return iwl_send_cmd(priv, &cmd); |
@@ -839,7 +839,7 @@ EXPORT_SYMBOL(iwl_send_lq_cmd); | |||
839 | * for automatic fallback during transmission. | 839 | * for automatic fallback during transmission. |
840 | * | 840 | * |
841 | * NOTE: This sets up a default set of values. These will be replaced later | 841 | * NOTE: This sets up a default set of values. These will be replaced later |
842 | * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of | 842 | * if the driver's iwl-agn-rs rate scaling algorithm is used, instead of |
843 | * rc80211_simple. | 843 | * rc80211_simple. |
844 | * | 844 | * |
845 | * NOTE: Run REPLY_ADD_STA command to set up station table entry, before | 845 | * NOTE: Run REPLY_ADD_STA command to set up station table entry, before |
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c index f72cd0bf6aa3..aa98c76d8195 100644 --- a/drivers/net/wireless/iwlwifi/iwl-tx.c +++ b/drivers/net/wireless/iwlwifi/iwl-tx.c | |||
@@ -208,11 +208,12 @@ EXPORT_SYMBOL(iwl_txq_update_write_ptr); | |||
208 | * Free all buffers. | 208 | * Free all buffers. |
209 | * 0-fill, but do not free "txq" descriptor structure. | 209 | * 0-fill, but do not free "txq" descriptor structure. |
210 | */ | 210 | */ |
211 | static void iwl_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq) | 211 | static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id) |
212 | { | 212 | { |
213 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | ||
213 | struct iwl_queue *q = &txq->q; | 214 | struct iwl_queue *q = &txq->q; |
214 | struct pci_dev *dev = priv->pci_dev; | 215 | struct pci_dev *dev = priv->pci_dev; |
215 | int len; | 216 | int i, slots_num, len; |
216 | 217 | ||
217 | if (q->n_bd == 0) | 218 | if (q->n_bd == 0) |
218 | return; | 219 | return; |
@@ -227,7 +228,12 @@ static void iwl_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq) | |||
227 | len += IWL_MAX_SCAN_SIZE; | 228 | len += IWL_MAX_SCAN_SIZE; |
228 | 229 | ||
229 | /* De-alloc array of command/tx buffers */ | 230 | /* De-alloc array of command/tx buffers */ |
230 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | 231 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? |
232 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | ||
233 | for (i = 0; i < slots_num; i++) | ||
234 | kfree(txq->cmd[i]); | ||
235 | if (txq_id == IWL_CMD_QUEUE_NUM) | ||
236 | kfree(txq->cmd[slots_num]); | ||
231 | 237 | ||
232 | /* De-alloc circular buffer of TFDs */ | 238 | /* De-alloc circular buffer of TFDs */ |
233 | if (txq->q.n_bd) | 239 | if (txq->q.n_bd) |
@@ -400,8 +406,7 @@ static int iwl_tx_queue_init(struct iwl_priv *priv, | |||
400 | struct iwl_tx_queue *txq, | 406 | struct iwl_tx_queue *txq, |
401 | int slots_num, u32 txq_id) | 407 | int slots_num, u32 txq_id) |
402 | { | 408 | { |
403 | struct pci_dev *dev = priv->pci_dev; | 409 | int i, len; |
404 | int len; | ||
405 | int rc = 0; | 410 | int rc = 0; |
406 | 411 | ||
407 | /* | 412 | /* |
@@ -412,17 +417,25 @@ static int iwl_tx_queue_init(struct iwl_priv *priv, | |||
412 | * For normal Tx queues (all other queues), no super-size command | 417 | * For normal Tx queues (all other queues), no super-size command |
413 | * space is needed. | 418 | * space is needed. |
414 | */ | 419 | */ |
415 | len = sizeof(struct iwl_cmd) * slots_num; | 420 | len = sizeof(struct iwl_cmd); |
416 | if (txq_id == IWL_CMD_QUEUE_NUM) | 421 | for (i = 0; i <= slots_num; i++) { |
417 | len += IWL_MAX_SCAN_SIZE; | 422 | if (i == slots_num) { |
418 | txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd); | 423 | if (txq_id == IWL_CMD_QUEUE_NUM) |
419 | if (!txq->cmd) | 424 | len += IWL_MAX_SCAN_SIZE; |
420 | return -ENOMEM; | 425 | else |
426 | continue; | ||
427 | } | ||
428 | |||
429 | txq->cmd[i] = kmalloc(len, GFP_KERNEL | GFP_DMA); | ||
430 | if (!txq->cmd[i]) | ||
431 | return -ENOMEM; | ||
432 | } | ||
421 | 433 | ||
422 | /* Alloc driver data array and TFD circular buffer */ | 434 | /* Alloc driver data array and TFD circular buffer */ |
423 | rc = iwl_tx_queue_alloc(priv, txq, txq_id); | 435 | rc = iwl_tx_queue_alloc(priv, txq, txq_id); |
424 | if (rc) { | 436 | if (rc) { |
425 | pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd); | 437 | for (i = 0; i < slots_num; i++) |
438 | kfree(txq->cmd[i]); | ||
426 | 439 | ||
427 | return -ENOMEM; | 440 | return -ENOMEM; |
428 | } | 441 | } |
@@ -451,7 +464,7 @@ void iwl_hw_txq_ctx_free(struct iwl_priv *priv) | |||
451 | 464 | ||
452 | /* Tx queues */ | 465 | /* Tx queues */ |
453 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) | 466 | for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) |
454 | iwl_tx_queue_free(priv, &priv->txq[txq_id]); | 467 | iwl_tx_queue_free(priv, txq_id); |
455 | 468 | ||
456 | /* Keep-warm buffer */ | 469 | /* Keep-warm buffer */ |
457 | iwl_kw_free(priv); | 470 | iwl_kw_free(priv); |
@@ -859,7 +872,7 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) | |||
859 | txq->txb[q->write_ptr].skb[0] = skb; | 872 | txq->txb[q->write_ptr].skb[0] = skb; |
860 | 873 | ||
861 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | 874 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ |
862 | out_cmd = &txq->cmd[idx]; | 875 | out_cmd = txq->cmd[idx]; |
863 | tx_cmd = &out_cmd->cmd.tx; | 876 | tx_cmd = &out_cmd->cmd.tx; |
864 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | 877 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); |
865 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); | 878 | memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd)); |
@@ -899,8 +912,9 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) | |||
899 | 912 | ||
900 | /* Physical address of this Tx command's header (not MAC header!), | 913 | /* Physical address of this Tx command's header (not MAC header!), |
901 | * within command buffer array. */ | 914 | * within command buffer array. */ |
902 | txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl_cmd) * idx + | 915 | txcmd_phys = pci_map_single(priv->pci_dev, out_cmd, |
903 | offsetof(struct iwl_cmd, hdr); | 916 | sizeof(struct iwl_cmd), PCI_DMA_TODEVICE); |
917 | txcmd_phys += offsetof(struct iwl_cmd, hdr); | ||
904 | 918 | ||
905 | /* Add buffer containing Tx command and MAC(!) header to TFD's | 919 | /* Add buffer containing Tx command and MAC(!) header to TFD's |
906 | * first entry */ | 920 | * first entry */ |
@@ -962,16 +976,16 @@ int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb) | |||
962 | if (ret) | 976 | if (ret) |
963 | return ret; | 977 | return ret; |
964 | 978 | ||
965 | if ((iwl_queue_space(q) < q->high_mark) | 979 | if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) { |
966 | && priv->mac80211_registered) { | ||
967 | if (wait_write_ptr) { | 980 | if (wait_write_ptr) { |
968 | spin_lock_irqsave(&priv->lock, flags); | 981 | spin_lock_irqsave(&priv->lock, flags); |
969 | txq->need_update = 1; | 982 | txq->need_update = 1; |
970 | iwl_txq_update_write_ptr(priv, txq); | 983 | iwl_txq_update_write_ptr(priv, txq); |
971 | spin_unlock_irqrestore(&priv->lock, flags); | 984 | spin_unlock_irqrestore(&priv->lock, flags); |
985 | } else { | ||
986 | ieee80211_stop_queue(priv->hw, | ||
987 | skb_get_queue_mapping(skb)); | ||
972 | } | 988 | } |
973 | |||
974 | ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb)); | ||
975 | } | 989 | } |
976 | 990 | ||
977 | return 0; | 991 | return 0; |
@@ -1004,7 +1018,7 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |||
1004 | u32 idx; | 1018 | u32 idx; |
1005 | u16 fix_size; | 1019 | u16 fix_size; |
1006 | dma_addr_t phys_addr; | 1020 | dma_addr_t phys_addr; |
1007 | int ret; | 1021 | int len, ret; |
1008 | unsigned long flags; | 1022 | unsigned long flags; |
1009 | 1023 | ||
1010 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | 1024 | cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); |
@@ -1034,7 +1048,7 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |||
1034 | control_flags = (u32 *) tfd; | 1048 | control_flags = (u32 *) tfd; |
1035 | 1049 | ||
1036 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); | 1050 | idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE); |
1037 | out_cmd = &txq->cmd[idx]; | 1051 | out_cmd = txq->cmd[idx]; |
1038 | 1052 | ||
1039 | out_cmd->hdr.cmd = cmd->id; | 1053 | out_cmd->hdr.cmd = cmd->id; |
1040 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); | 1054 | memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta)); |
@@ -1048,9 +1062,11 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd) | |||
1048 | INDEX_TO_SEQ(q->write_ptr)); | 1062 | INDEX_TO_SEQ(q->write_ptr)); |
1049 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) | 1063 | if (out_cmd->meta.flags & CMD_SIZE_HUGE) |
1050 | out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME); | 1064 | out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME); |
1051 | 1065 | len = (idx == TFD_CMD_SLOTS) ? | |
1052 | phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx + | 1066 | IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd); |
1053 | offsetof(struct iwl_cmd, hdr); | 1067 | phys_addr = pci_map_single(priv->pci_dev, out_cmd, len, |
1068 | PCI_DMA_TODEVICE); | ||
1069 | phys_addr += offsetof(struct iwl_cmd, hdr); | ||
1054 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); | 1070 | iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size); |
1055 | 1071 | ||
1056 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " | 1072 | IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, " |
@@ -1115,6 +1131,9 @@ static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) | |||
1115 | { | 1131 | { |
1116 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | 1132 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
1117 | struct iwl_queue *q = &txq->q; | 1133 | struct iwl_queue *q = &txq->q; |
1134 | struct iwl_tfd_frame *bd = &txq->bd[index]; | ||
1135 | dma_addr_t dma_addr; | ||
1136 | int is_odd, buf_len; | ||
1118 | int nfreed = 0; | 1137 | int nfreed = 0; |
1119 | 1138 | ||
1120 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { | 1139 | if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) { |
@@ -1132,6 +1151,19 @@ static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id, int index) | |||
1132 | q->write_ptr, q->read_ptr); | 1151 | q->write_ptr, q->read_ptr); |
1133 | queue_work(priv->workqueue, &priv->restart); | 1152 | queue_work(priv->workqueue, &priv->restart); |
1134 | } | 1153 | } |
1154 | is_odd = (index/2) & 0x1; | ||
1155 | if (is_odd) { | ||
1156 | dma_addr = IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) | | ||
1157 | (IWL_GET_BITS(bd->pa[index], | ||
1158 | tb2_addr_hi20) << 16); | ||
1159 | buf_len = IWL_GET_BITS(bd->pa[index], tb2_len); | ||
1160 | } else { | ||
1161 | dma_addr = le32_to_cpu(bd->pa[index].tb1_addr); | ||
1162 | buf_len = IWL_GET_BITS(bd->pa[index], tb1_len); | ||
1163 | } | ||
1164 | |||
1165 | pci_unmap_single(priv->pci_dev, dma_addr, buf_len, | ||
1166 | PCI_DMA_TODEVICE); | ||
1135 | nfreed++; | 1167 | nfreed++; |
1136 | } | 1168 | } |
1137 | } | 1169 | } |
@@ -1163,7 +1195,7 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |||
1163 | BUG_ON(txq_id != IWL_CMD_QUEUE_NUM); | 1195 | BUG_ON(txq_id != IWL_CMD_QUEUE_NUM); |
1164 | 1196 | ||
1165 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); | 1197 | cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge); |
1166 | cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; | 1198 | cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index]; |
1167 | 1199 | ||
1168 | /* Input error checking is done when commands are added to queue. */ | 1200 | /* Input error checking is done when commands are added to queue. */ |
1169 | if (cmd->meta.flags & CMD_WANT_SKB) { | 1201 | if (cmd->meta.flags & CMD_WANT_SKB) { |
@@ -1391,7 +1423,7 @@ static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv, | |||
1391 | /* For each frame attempted in aggregation, | 1423 | /* For each frame attempted in aggregation, |
1392 | * update driver's record of tx frame's status. */ | 1424 | * update driver's record of tx frame's status. */ |
1393 | for (i = 0; i < agg->frame_count ; i++) { | 1425 | for (i = 0; i < agg->frame_count ; i++) { |
1394 | ack = bitmap & (1 << i); | 1426 | ack = bitmap & (1ULL << i); |
1395 | successes += !!ack; | 1427 | successes += !!ack; |
1396 | IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", | 1428 | IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", |
1397 | ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff, | 1429 | ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff, |
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c index 7c82ecfa30a4..444847ab1b5a 100644 --- a/drivers/net/wireless/iwlwifi/iwl3945-base.c +++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c | |||
@@ -275,10 +275,8 @@ static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv, | |||
275 | return 0; | 275 | return 0; |
276 | 276 | ||
277 | error: | 277 | error: |
278 | if (txq->txb) { | 278 | kfree(txq->txb); |
279 | kfree(txq->txb); | 279 | txq->txb = NULL; |
280 | txq->txb = NULL; | ||
281 | } | ||
282 | 280 | ||
283 | return -ENOMEM; | 281 | return -ENOMEM; |
284 | } | 282 | } |
@@ -365,10 +363,8 @@ void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *t | |||
365 | txq->q.n_bd, txq->bd, txq->q.dma_addr); | 363 | txq->q.n_bd, txq->bd, txq->q.dma_addr); |
366 | 364 | ||
367 | /* De-alloc array of per-TFD driver data */ | 365 | /* De-alloc array of per-TFD driver data */ |
368 | if (txq->txb) { | 366 | kfree(txq->txb); |
369 | kfree(txq->txb); | 367 | txq->txb = NULL; |
370 | txq->txb = NULL; | ||
371 | } | ||
372 | 368 | ||
373 | /* 0-fill queue descriptor structure */ | 369 | /* 0-fill queue descriptor structure */ |
374 | memset(txq, 0, sizeof(*txq)); | 370 | memset(txq, 0, sizeof(*txq)); |
@@ -2703,9 +2699,8 @@ static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb) | |||
2703 | 2699 | ||
2704 | if (!ieee80211_has_morefrags(hdr->frame_control)) { | 2700 | if (!ieee80211_has_morefrags(hdr->frame_control)) { |
2705 | txq->need_update = 1; | 2701 | txq->need_update = 1; |
2706 | if (qc) { | 2702 | if (qc) |
2707 | priv->stations[sta_id].tid[tid].seq_number = seq_number; | 2703 | priv->stations[sta_id].tid[tid].seq_number = seq_number; |
2708 | } | ||
2709 | } else { | 2704 | } else { |
2710 | wait_write_ptr = 1; | 2705 | wait_write_ptr = 1; |
2711 | txq->need_update = 0; | 2706 | txq->need_update = 0; |
@@ -3813,7 +3808,7 @@ int iwl3945_calc_db_from_ratio(int sig_ratio) | |||
3813 | /* 100:1 or higher, divide by 10 and use table, | 3808 | /* 100:1 or higher, divide by 10 and use table, |
3814 | * add 20 dB to make up for divide by 10 */ | 3809 | * add 20 dB to make up for divide by 10 */ |
3815 | if (sig_ratio >= 100) | 3810 | if (sig_ratio >= 100) |
3816 | return (20 + (int)ratio2dB[sig_ratio/10]); | 3811 | return 20 + (int)ratio2dB[sig_ratio/10]; |
3817 | 3812 | ||
3818 | /* We shouldn't see this */ | 3813 | /* We shouldn't see this */ |
3819 | if (sig_ratio < 1) | 3814 | if (sig_ratio < 1) |
@@ -5088,7 +5083,7 @@ static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv) | |||
5088 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, | 5083 | * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host, |
5089 | * looking at all data. | 5084 | * looking at all data. |
5090 | */ | 5085 | */ |
5091 | static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len) | 5086 | static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 *image, u32 len) |
5092 | { | 5087 | { |
5093 | u32 val; | 5088 | u32 val; |
5094 | u32 save_len = len; | 5089 | u32 save_len = len; |
@@ -5237,7 +5232,7 @@ static int iwl3945_verify_bsm(struct iwl3945_priv *priv) | |||
5237 | val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG); | 5232 | val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG); |
5238 | for (reg = BSM_SRAM_LOWER_BOUND; | 5233 | for (reg = BSM_SRAM_LOWER_BOUND; |
5239 | reg < BSM_SRAM_LOWER_BOUND + len; | 5234 | reg < BSM_SRAM_LOWER_BOUND + len; |
5240 | reg += sizeof(u32), image ++) { | 5235 | reg += sizeof(u32), image++) { |
5241 | val = iwl3945_read_prph(priv, reg); | 5236 | val = iwl3945_read_prph(priv, reg); |
5242 | if (val != le32_to_cpu(*image)) { | 5237 | if (val != le32_to_cpu(*image)) { |
5243 | IWL_ERROR("BSM uCode verification failed at " | 5238 | IWL_ERROR("BSM uCode verification failed at " |
@@ -6336,7 +6331,7 @@ static void iwl3945_bg_post_associate(struct work_struct *data) | |||
6336 | DECLARE_MAC_BUF(mac); | 6331 | DECLARE_MAC_BUF(mac); |
6337 | 6332 | ||
6338 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { | 6333 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { |
6339 | IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__); | 6334 | IWL_ERROR("%s Should not be called in AP mode\n", __func__); |
6340 | return; | 6335 | return; |
6341 | } | 6336 | } |
6342 | 6337 | ||
@@ -6417,7 +6412,7 @@ static void iwl3945_bg_post_associate(struct work_struct *data) | |||
6417 | 6412 | ||
6418 | default: | 6413 | default: |
6419 | IWL_ERROR("%s Should not be called in %d mode\n", | 6414 | IWL_ERROR("%s Should not be called in %d mode\n", |
6420 | __FUNCTION__, priv->iw_mode); | 6415 | __func__, priv->iw_mode); |
6421 | break; | 6416 | break; |
6422 | } | 6417 | } |
6423 | 6418 | ||
@@ -6594,12 +6589,6 @@ static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
6594 | 6589 | ||
6595 | IWL_DEBUG_MAC80211("enter\n"); | 6590 | IWL_DEBUG_MAC80211("enter\n"); |
6596 | 6591 | ||
6597 | if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) { | ||
6598 | IWL_DEBUG_MAC80211("leave - monitor\n"); | ||
6599 | dev_kfree_skb_any(skb); | ||
6600 | return 0; | ||
6601 | } | ||
6602 | |||
6603 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, | 6592 | IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
6604 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); | 6593 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
6605 | 6594 | ||
@@ -7456,7 +7445,7 @@ static ssize_t show_measurement(struct device *d, | |||
7456 | struct iwl3945_priv *priv = dev_get_drvdata(d); | 7445 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
7457 | struct iwl3945_spectrum_notification measure_report; | 7446 | struct iwl3945_spectrum_notification measure_report; |
7458 | u32 size = sizeof(measure_report), len = 0, ofs = 0; | 7447 | u32 size = sizeof(measure_report), len = 0, ofs = 0; |
7459 | u8 *data = (u8 *) & measure_report; | 7448 | u8 *data = (u8 *)&measure_report; |
7460 | unsigned long flags; | 7449 | unsigned long flags; |
7461 | 7450 | ||
7462 | spin_lock_irqsave(&priv->lock, flags); | 7451 | spin_lock_irqsave(&priv->lock, flags); |
@@ -7627,7 +7616,7 @@ static ssize_t show_power_level(struct device *d, | |||
7627 | else | 7616 | else |
7628 | p += sprintf(p, " \n"); | 7617 | p += sprintf(p, " \n"); |
7629 | 7618 | ||
7630 | return (p - buf + 1); | 7619 | return p - buf + 1; |
7631 | 7620 | ||
7632 | } | 7621 | } |
7633 | 7622 | ||
@@ -7649,7 +7638,7 @@ static ssize_t show_statistics(struct device *d, | |||
7649 | struct iwl3945_priv *priv = dev_get_drvdata(d); | 7638 | struct iwl3945_priv *priv = dev_get_drvdata(d); |
7650 | u32 size = sizeof(struct iwl3945_notif_statistics); | 7639 | u32 size = sizeof(struct iwl3945_notif_statistics); |
7651 | u32 len = 0, ofs = 0; | 7640 | u32 len = 0, ofs = 0; |
7652 | u8 *data = (u8 *) & priv->statistics; | 7641 | u8 *data = (u8 *)&priv->statistics; |
7653 | int rc = 0; | 7642 | int rc = 0; |
7654 | 7643 | ||
7655 | if (!iwl3945_is_alive(priv)) | 7644 | if (!iwl3945_is_alive(priv)) |
@@ -8003,16 +7992,16 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e | |||
8003 | 7992 | ||
8004 | /* nic init */ | 7993 | /* nic init */ |
8005 | iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, | 7994 | iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
8006 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | 7995 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
8007 | 7996 | ||
8008 | iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | 7997 | iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
8009 | err = iwl3945_poll_bit(priv, CSR_GP_CNTRL, | 7998 | err = iwl3945_poll_bit(priv, CSR_GP_CNTRL, |
8010 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | 7999 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
8011 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | 8000 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); |
8012 | if (err < 0) { | 8001 | if (err < 0) { |
8013 | IWL_DEBUG_INFO("Failed to init the card\n"); | 8002 | IWL_DEBUG_INFO("Failed to init the card\n"); |
8014 | goto out_remove_sysfs; | 8003 | goto out_remove_sysfs; |
8015 | } | 8004 | } |
8016 | /* Read the EEPROM */ | 8005 | /* Read the EEPROM */ |
8017 | err = iwl3945_eeprom_init(priv); | 8006 | err = iwl3945_eeprom_init(priv); |
8018 | if (err) { | 8007 | if (err) { |
@@ -8114,9 +8103,8 @@ static void __devexit iwl3945_pci_remove(struct pci_dev *pdev) | |||
8114 | iwl3945_unset_hw_setting(priv); | 8103 | iwl3945_unset_hw_setting(priv); |
8115 | iwl3945_clear_stations_table(priv); | 8104 | iwl3945_clear_stations_table(priv); |
8116 | 8105 | ||
8117 | if (priv->mac80211_registered) { | 8106 | if (priv->mac80211_registered) |
8118 | ieee80211_unregister_hw(priv->hw); | 8107 | ieee80211_unregister_hw(priv->hw); |
8119 | } | ||
8120 | 8108 | ||
8121 | /*netif_stop_queue(dev); */ | 8109 | /*netif_stop_queue(dev); */ |
8122 | flush_workqueue(priv->workqueue); | 8110 | flush_workqueue(priv->workqueue); |
diff --git a/drivers/net/wireless/libertas/main.c b/drivers/net/wireless/libertas/main.c index 14d5d61cec4c..bd32ac0b4e07 100644 --- a/drivers/net/wireless/libertas/main.c +++ b/drivers/net/wireless/libertas/main.c | |||
@@ -297,9 +297,7 @@ static ssize_t lbs_rtap_set(struct device *dev, | |||
297 | lbs_add_rtap(priv); | 297 | lbs_add_rtap(priv); |
298 | } | 298 | } |
299 | priv->monitormode = monitor_mode; | 299 | priv->monitormode = monitor_mode; |
300 | } | 300 | } else { |
301 | |||
302 | else { | ||
303 | if (!priv->monitormode) | 301 | if (!priv->monitormode) |
304 | return strlen(buf); | 302 | return strlen(buf); |
305 | priv->monitormode = 0; | 303 | priv->monitormode = 0; |
@@ -1242,8 +1240,6 @@ int lbs_start_card(struct lbs_private *priv) | |||
1242 | lbs_pr_err("cannot register ethX device\n"); | 1240 | lbs_pr_err("cannot register ethX device\n"); |
1243 | goto done; | 1241 | goto done; |
1244 | } | 1242 | } |
1245 | if (device_create_file(&dev->dev, &dev_attr_lbs_rtap)) | ||
1246 | lbs_pr_err("cannot register lbs_rtap attribute\n"); | ||
1247 | 1243 | ||
1248 | lbs_update_channel(priv); | 1244 | lbs_update_channel(priv); |
1249 | 1245 | ||
@@ -1275,6 +1271,13 @@ int lbs_start_card(struct lbs_private *priv) | |||
1275 | 1271 | ||
1276 | if (device_create_file(&dev->dev, &dev_attr_lbs_mesh)) | 1272 | if (device_create_file(&dev->dev, &dev_attr_lbs_mesh)) |
1277 | lbs_pr_err("cannot register lbs_mesh attribute\n"); | 1273 | lbs_pr_err("cannot register lbs_mesh attribute\n"); |
1274 | |||
1275 | /* While rtap isn't related to mesh, only mesh-enabled | ||
1276 | * firmware implements the rtap functionality via | ||
1277 | * CMD_802_11_MONITOR_MODE. | ||
1278 | */ | ||
1279 | if (device_create_file(&dev->dev, &dev_attr_lbs_rtap)) | ||
1280 | lbs_pr_err("cannot register lbs_rtap attribute\n"); | ||
1278 | } | 1281 | } |
1279 | } | 1282 | } |
1280 | 1283 | ||
@@ -1306,9 +1309,9 @@ void lbs_stop_card(struct lbs_private *priv) | |||
1306 | netif_carrier_off(priv->dev); | 1309 | netif_carrier_off(priv->dev); |
1307 | 1310 | ||
1308 | lbs_debugfs_remove_one(priv); | 1311 | lbs_debugfs_remove_one(priv); |
1309 | device_remove_file(&dev->dev, &dev_attr_lbs_rtap); | ||
1310 | if (priv->mesh_tlv) { | 1312 | if (priv->mesh_tlv) { |
1311 | device_remove_file(&dev->dev, &dev_attr_lbs_mesh); | 1313 | device_remove_file(&dev->dev, &dev_attr_lbs_mesh); |
1314 | device_remove_file(&dev->dev, &dev_attr_lbs_rtap); | ||
1312 | } | 1315 | } |
1313 | 1316 | ||
1314 | /* Flush pending command nodes */ | 1317 | /* Flush pending command nodes */ |
diff --git a/drivers/net/wireless/p54/p54.h b/drivers/net/wireless/p54/p54.h index c6f27b9022f9..cac9a515b82d 100644 --- a/drivers/net/wireless/p54/p54.h +++ b/drivers/net/wireless/p54/p54.h | |||
@@ -52,6 +52,7 @@ struct p54_common { | |||
52 | int (*open)(struct ieee80211_hw *dev); | 52 | int (*open)(struct ieee80211_hw *dev); |
53 | void (*stop)(struct ieee80211_hw *dev); | 53 | void (*stop)(struct ieee80211_hw *dev); |
54 | int mode; | 54 | int mode; |
55 | struct mutex conf_mutex; | ||
55 | u8 mac_addr[ETH_ALEN]; | 56 | u8 mac_addr[ETH_ALEN]; |
56 | u8 bssid[ETH_ALEN]; | 57 | u8 bssid[ETH_ALEN]; |
57 | struct pda_iq_autocal_entry *iq_autocal; | 58 | struct pda_iq_autocal_entry *iq_autocal; |
diff --git a/drivers/net/wireless/p54/p54common.c b/drivers/net/wireless/p54/p54common.c index ffaf7a6b6810..4da89ea9b561 100644 --- a/drivers/net/wireless/p54/p54common.c +++ b/drivers/net/wireless/p54/p54common.c | |||
@@ -886,9 +886,12 @@ static void p54_remove_interface(struct ieee80211_hw *dev, | |||
886 | static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf) | 886 | static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf) |
887 | { | 887 | { |
888 | int ret; | 888 | int ret; |
889 | struct p54_common *priv = dev->priv; | ||
889 | 890 | ||
891 | mutex_lock(&priv->conf_mutex); | ||
890 | ret = p54_set_freq(dev, cpu_to_le16(conf->channel->center_freq)); | 892 | ret = p54_set_freq(dev, cpu_to_le16(conf->channel->center_freq)); |
891 | p54_set_vdcf(dev); | 893 | p54_set_vdcf(dev); |
894 | mutex_unlock(&priv->conf_mutex); | ||
892 | return ret; | 895 | return ret; |
893 | } | 896 | } |
894 | 897 | ||
@@ -898,10 +901,12 @@ static int p54_config_interface(struct ieee80211_hw *dev, | |||
898 | { | 901 | { |
899 | struct p54_common *priv = dev->priv; | 902 | struct p54_common *priv = dev->priv; |
900 | 903 | ||
904 | mutex_lock(&priv->conf_mutex); | ||
901 | p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 0, 1, 0, 0xF642); | 905 | p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 0, 1, 0, 0xF642); |
902 | p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 2, 0, 0, 0); | 906 | p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 2, 0, 0, 0); |
903 | p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0); | 907 | p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0); |
904 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); | 908 | memcpy(priv->bssid, conf->bssid, ETH_ALEN); |
909 | mutex_unlock(&priv->conf_mutex); | ||
905 | return 0; | 910 | return 0; |
906 | } | 911 | } |
907 | 912 | ||
@@ -1009,6 +1014,7 @@ struct ieee80211_hw *p54_init_common(size_t priv_data_len) | |||
1009 | } | 1014 | } |
1010 | 1015 | ||
1011 | p54_init_vdcf(dev); | 1016 | p54_init_vdcf(dev); |
1017 | mutex_init(&priv->conf_mutex); | ||
1012 | 1018 | ||
1013 | return dev; | 1019 | return dev; |
1014 | } | 1020 | } |
diff --git a/drivers/net/wireless/prism54/isl_ioctl.c b/drivers/net/wireless/prism54/isl_ioctl.c index 97fa14e0a479..3d75a7137d3c 100644 --- a/drivers/net/wireless/prism54/isl_ioctl.c +++ b/drivers/net/wireless/prism54/isl_ioctl.c | |||
@@ -2518,7 +2518,7 @@ enum { | |||
2518 | 2518 | ||
2519 | #define PRISM2_HOSTAPD_MAX_BUF_SIZE 1024 | 2519 | #define PRISM2_HOSTAPD_MAX_BUF_SIZE 1024 |
2520 | #define PRISM2_HOSTAPD_GENERIC_ELEMENT_HDR_LEN \ | 2520 | #define PRISM2_HOSTAPD_GENERIC_ELEMENT_HDR_LEN \ |
2521 | ((int) (&((struct prism2_hostapd_param *) 0)->u.generic_elem.data)) | 2521 | offsetof(struct prism2_hostapd_param, u.generic_elem.data) |
2522 | 2522 | ||
2523 | /* Maximum length for algorithm names (-1 for nul termination) | 2523 | /* Maximum length for algorithm names (-1 for nul termination) |
2524 | * used in ioctl() */ | 2524 | * used in ioctl() */ |
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c index aa6dfb811c71..181a146b4768 100644 --- a/drivers/net/wireless/rt2x00/rt2500pci.c +++ b/drivers/net/wireless/rt2x00/rt2500pci.c | |||
@@ -1220,6 +1220,7 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, | |||
1220 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); | 1220 | rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); |
1221 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, | 1221 | rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, |
1222 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); | 1222 | test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); |
1223 | rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len); | ||
1223 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); | 1224 | rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); |
1224 | rt2x00_desc_write(txd, 0, word); | 1225 | rt2x00_desc_write(txd, 0, word); |
1225 | } | 1226 | } |
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c index 3078417b326b..cd5af656932d 100644 --- a/drivers/net/wireless/rt2x00/rt2500usb.c +++ b/drivers/net/wireless/rt2x00/rt2500usb.c | |||
@@ -633,6 +633,16 @@ static void rt2500usb_reset_tuner(struct rt2x00_dev *rt2x00dev) | |||
633 | rt2x00dev->link.vgc_level = value; | 633 | rt2x00dev->link.vgc_level = value; |
634 | } | 634 | } |
635 | 635 | ||
636 | /* | ||
637 | * NOTE: This function is directly ported from legacy driver, but | ||
638 | * despite it being declared it was never called. Although link tuning | ||
639 | * sounds like a good idea, and usually works well for the other drivers, | ||
640 | * it does _not_ work with rt2500usb. Enabling this function will result | ||
641 | * in TX capabilities only until association kicks in. Immediately | ||
642 | * after the successful association all TX frames will be kept in the | ||
643 | * hardware queue and never transmitted. | ||
644 | */ | ||
645 | #if 0 | ||
636 | static void rt2500usb_link_tuner(struct rt2x00_dev *rt2x00dev) | 646 | static void rt2500usb_link_tuner(struct rt2x00_dev *rt2x00dev) |
637 | { | 647 | { |
638 | int rssi = rt2x00_get_link_rssi(&rt2x00dev->link); | 648 | int rssi = rt2x00_get_link_rssi(&rt2x00dev->link); |
@@ -752,6 +762,9 @@ dynamic_cca_tune: | |||
752 | rt2x00dev->link.vgc_level = r17; | 762 | rt2x00dev->link.vgc_level = r17; |
753 | } | 763 | } |
754 | } | 764 | } |
765 | #else | ||
766 | #define rt2500usb_link_tuner NULL | ||
767 | #endif | ||
755 | 768 | ||
756 | /* | 769 | /* |
757 | * Initialization functions. | 770 | * Initialization functions. |
@@ -1376,6 +1389,9 @@ static int rt2500usb_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |||
1376 | rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp); | 1389 | rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp); |
1377 | rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word); | 1390 | rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word); |
1378 | EEPROM(rt2x00dev, "BBPtune vgc: 0x%04x\n", word); | 1391 | EEPROM(rt2x00dev, "BBPtune vgc: 0x%04x\n", word); |
1392 | } else { | ||
1393 | rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp); | ||
1394 | rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word); | ||
1379 | } | 1395 | } |
1380 | 1396 | ||
1381 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R17, &word); | 1397 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R17, &word); |
@@ -1384,9 +1400,6 @@ static int rt2500usb_validate_eeprom(struct rt2x00_dev *rt2x00dev) | |||
1384 | rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_HIGH, 0x41); | 1400 | rt2x00_set_field16(&word, EEPROM_BBPTUNE_R17_HIGH, 0x41); |
1385 | rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R17, word); | 1401 | rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_R17, word); |
1386 | EEPROM(rt2x00dev, "BBPtune r17: 0x%04x\n", word); | 1402 | EEPROM(rt2x00dev, "BBPtune r17: 0x%04x\n", word); |
1387 | } else { | ||
1388 | rt2x00_set_field16(&word, EEPROM_BBPTUNE_VGCLOWER, bbp); | ||
1389 | rt2x00_eeprom_write(rt2x00dev, EEPROM_BBPTUNE_VGC, word); | ||
1390 | } | 1403 | } |
1391 | 1404 | ||
1392 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &word); | 1405 | rt2x00_eeprom_read(rt2x00dev, EEPROM_BBPTUNE_R24, &word); |
@@ -1737,6 +1750,7 @@ static int rt2500usb_probe_hw(struct rt2x00_dev *rt2x00dev) | |||
1737 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); | 1750 | __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags); |
1738 | __set_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags); | 1751 | __set_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags); |
1739 | __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags); | 1752 | __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags); |
1753 | __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags); | ||
1740 | 1754 | ||
1741 | /* | 1755 | /* |
1742 | * Set the rssi offset. | 1756 | * Set the rssi offset. |
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h index db2dc976d831..8b10ea41b204 100644 --- a/drivers/net/wireless/rt2x00/rt2x00.h +++ b/drivers/net/wireless/rt2x00/rt2x00.h | |||
@@ -368,6 +368,12 @@ struct rt2x00_intf { | |||
368 | #define DELAYED_CONFIG_ERP 0x00000002 | 368 | #define DELAYED_CONFIG_ERP 0x00000002 |
369 | #define DELAYED_LED_ASSOC 0x00000004 | 369 | #define DELAYED_LED_ASSOC 0x00000004 |
370 | 370 | ||
371 | /* | ||
372 | * Software sequence counter, this is only required | ||
373 | * for hardware which doesn't support hardware | ||
374 | * sequence counting. | ||
375 | */ | ||
376 | spinlock_t seqlock; | ||
371 | u16 seqno; | 377 | u16 seqno; |
372 | }; | 378 | }; |
373 | 379 | ||
diff --git a/drivers/net/wireless/rt2x00/rt2x00config.c b/drivers/net/wireless/rt2x00/rt2x00config.c index 3f89516e8332..d134c3be539a 100644 --- a/drivers/net/wireless/rt2x00/rt2x00config.c +++ b/drivers/net/wireless/rt2x00/rt2x00config.c | |||
@@ -254,6 +254,8 @@ config: | |||
254 | libconf.ant.rx = default_ant->rx; | 254 | libconf.ant.rx = default_ant->rx; |
255 | else if (active_ant->rx == ANTENNA_SW_DIVERSITY) | 255 | else if (active_ant->rx == ANTENNA_SW_DIVERSITY) |
256 | libconf.ant.rx = ANTENNA_B; | 256 | libconf.ant.rx = ANTENNA_B; |
257 | else | ||
258 | libconf.ant.rx = active_ant->rx; | ||
257 | 259 | ||
258 | if (conf->antenna_sel_tx) | 260 | if (conf->antenna_sel_tx) |
259 | libconf.ant.tx = conf->antenna_sel_tx; | 261 | libconf.ant.tx = conf->antenna_sel_tx; |
@@ -261,6 +263,8 @@ config: | |||
261 | libconf.ant.tx = default_ant->tx; | 263 | libconf.ant.tx = default_ant->tx; |
262 | else if (active_ant->tx == ANTENNA_SW_DIVERSITY) | 264 | else if (active_ant->tx == ANTENNA_SW_DIVERSITY) |
263 | libconf.ant.tx = ANTENNA_B; | 265 | libconf.ant.tx = ANTENNA_B; |
266 | else | ||
267 | libconf.ant.tx = active_ant->tx; | ||
264 | } | 268 | } |
265 | 269 | ||
266 | if (flags & CONFIG_UPDATE_SLOT_TIME) { | 270 | if (flags & CONFIG_UPDATE_SLOT_TIME) { |
diff --git a/drivers/net/wireless/rt2x00/rt2x00debug.c b/drivers/net/wireless/rt2x00/rt2x00debug.c index 300cf061035f..6bee1d611bbf 100644 --- a/drivers/net/wireless/rt2x00/rt2x00debug.c +++ b/drivers/net/wireless/rt2x00/rt2x00debug.c | |||
@@ -372,9 +372,6 @@ static ssize_t rt2x00debug_write_##__name(struct file *file, \ | |||
372 | if (*offset) \ | 372 | if (*offset) \ |
373 | return 0; \ | 373 | return 0; \ |
374 | \ | 374 | \ |
375 | if (!capable(CAP_NET_ADMIN)) \ | ||
376 | return -EPERM; \ | ||
377 | \ | ||
378 | if (intf->offset_##__name >= debug->__name.word_count) \ | 375 | if (intf->offset_##__name >= debug->__name.word_count) \ |
379 | return -EINVAL; \ | 376 | return -EINVAL; \ |
380 | \ | 377 | \ |
@@ -454,7 +451,7 @@ static struct dentry *rt2x00debug_create_file_driver(const char *name, | |||
454 | data += sprintf(data, "compiled: %s %s\n", __DATE__, __TIME__); | 451 | data += sprintf(data, "compiled: %s %s\n", __DATE__, __TIME__); |
455 | blob->size = strlen(blob->data); | 452 | blob->size = strlen(blob->data); |
456 | 453 | ||
457 | return debugfs_create_blob(name, S_IRUGO, intf->driver_folder, blob); | 454 | return debugfs_create_blob(name, S_IRUSR, intf->driver_folder, blob); |
458 | } | 455 | } |
459 | 456 | ||
460 | static struct dentry *rt2x00debug_create_file_chipset(const char *name, | 457 | static struct dentry *rt2x00debug_create_file_chipset(const char *name, |
@@ -482,7 +479,7 @@ static struct dentry *rt2x00debug_create_file_chipset(const char *name, | |||
482 | data += sprintf(data, "rf length: %d\n", debug->rf.word_count); | 479 | data += sprintf(data, "rf length: %d\n", debug->rf.word_count); |
483 | blob->size = strlen(blob->data); | 480 | blob->size = strlen(blob->data); |
484 | 481 | ||
485 | return debugfs_create_blob(name, S_IRUGO, intf->driver_folder, blob); | 482 | return debugfs_create_blob(name, S_IRUSR, intf->driver_folder, blob); |
486 | } | 483 | } |
487 | 484 | ||
488 | void rt2x00debug_register(struct rt2x00_dev *rt2x00dev) | 485 | void rt2x00debug_register(struct rt2x00_dev *rt2x00dev) |
@@ -517,7 +514,7 @@ void rt2x00debug_register(struct rt2x00_dev *rt2x00dev) | |||
517 | if (IS_ERR(intf->chipset_entry)) | 514 | if (IS_ERR(intf->chipset_entry)) |
518 | goto exit; | 515 | goto exit; |
519 | 516 | ||
520 | intf->dev_flags = debugfs_create_file("dev_flags", S_IRUGO, | 517 | intf->dev_flags = debugfs_create_file("dev_flags", S_IRUSR, |
521 | intf->driver_folder, intf, | 518 | intf->driver_folder, intf, |
522 | &rt2x00debug_fop_dev_flags); | 519 | &rt2x00debug_fop_dev_flags); |
523 | if (IS_ERR(intf->dev_flags)) | 520 | if (IS_ERR(intf->dev_flags)) |
@@ -532,7 +529,7 @@ void rt2x00debug_register(struct rt2x00_dev *rt2x00dev) | |||
532 | ({ \ | 529 | ({ \ |
533 | (__intf)->__name##_off_entry = \ | 530 | (__intf)->__name##_off_entry = \ |
534 | debugfs_create_u32(__stringify(__name) "_offset", \ | 531 | debugfs_create_u32(__stringify(__name) "_offset", \ |
535 | S_IRUGO | S_IWUSR, \ | 532 | S_IRUSR | S_IWUSR, \ |
536 | (__intf)->register_folder, \ | 533 | (__intf)->register_folder, \ |
537 | &(__intf)->offset_##__name); \ | 534 | &(__intf)->offset_##__name); \ |
538 | if (IS_ERR((__intf)->__name##_off_entry)) \ | 535 | if (IS_ERR((__intf)->__name##_off_entry)) \ |
@@ -540,7 +537,7 @@ void rt2x00debug_register(struct rt2x00_dev *rt2x00dev) | |||
540 | \ | 537 | \ |
541 | (__intf)->__name##_val_entry = \ | 538 | (__intf)->__name##_val_entry = \ |
542 | debugfs_create_file(__stringify(__name) "_value", \ | 539 | debugfs_create_file(__stringify(__name) "_value", \ |
543 | S_IRUGO | S_IWUSR, \ | 540 | S_IRUSR | S_IWUSR, \ |
544 | (__intf)->register_folder, \ | 541 | (__intf)->register_folder, \ |
545 | (__intf), &rt2x00debug_fop_##__name);\ | 542 | (__intf), &rt2x00debug_fop_##__name);\ |
546 | if (IS_ERR((__intf)->__name##_val_entry)) \ | 543 | if (IS_ERR((__intf)->__name##_val_entry)) \ |
@@ -560,7 +557,7 @@ void rt2x00debug_register(struct rt2x00_dev *rt2x00dev) | |||
560 | goto exit; | 557 | goto exit; |
561 | 558 | ||
562 | intf->queue_frame_dump_entry = | 559 | intf->queue_frame_dump_entry = |
563 | debugfs_create_file("dump", S_IRUGO, intf->queue_folder, | 560 | debugfs_create_file("dump", S_IRUSR, intf->queue_folder, |
564 | intf, &rt2x00debug_fop_queue_dump); | 561 | intf, &rt2x00debug_fop_queue_dump); |
565 | if (IS_ERR(intf->queue_frame_dump_entry)) | 562 | if (IS_ERR(intf->queue_frame_dump_entry)) |
566 | goto exit; | 563 | goto exit; |
@@ -569,7 +566,7 @@ void rt2x00debug_register(struct rt2x00_dev *rt2x00dev) | |||
569 | init_waitqueue_head(&intf->frame_dump_waitqueue); | 566 | init_waitqueue_head(&intf->frame_dump_waitqueue); |
570 | 567 | ||
571 | intf->queue_stats_entry = | 568 | intf->queue_stats_entry = |
572 | debugfs_create_file("queue", S_IRUGO, intf->queue_folder, | 569 | debugfs_create_file("queue", S_IRUSR, intf->queue_folder, |
573 | intf, &rt2x00debug_fop_queue_stats); | 570 | intf, &rt2x00debug_fop_queue_stats); |
574 | 571 | ||
575 | return; | 572 | return; |
diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c index c3ee4ecba792..bd422fd6a894 100644 --- a/drivers/net/wireless/rt2x00/rt2x00mac.c +++ b/drivers/net/wireless/rt2x00/rt2x00mac.c | |||
@@ -247,6 +247,7 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw, | |||
247 | rt2x00dev->intf_sta_count++; | 247 | rt2x00dev->intf_sta_count++; |
248 | 248 | ||
249 | spin_lock_init(&intf->lock); | 249 | spin_lock_init(&intf->lock); |
250 | spin_lock_init(&intf->seqlock); | ||
250 | intf->beacon = entry; | 251 | intf->beacon = entry; |
251 | 252 | ||
252 | if (conf->type == IEEE80211_IF_TYPE_AP) | 253 | if (conf->type == IEEE80211_IF_TYPE_AP) |
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c index 3b27f6aa860c..898cdd7f57d9 100644 --- a/drivers/net/wireless/rt2x00/rt2x00queue.c +++ b/drivers/net/wireless/rt2x00/rt2x00queue.c | |||
@@ -128,6 +128,7 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry, | |||
128 | unsigned int data_length; | 128 | unsigned int data_length; |
129 | unsigned int duration; | 129 | unsigned int duration; |
130 | unsigned int residual; | 130 | unsigned int residual; |
131 | unsigned long irqflags; | ||
131 | 132 | ||
132 | memset(txdesc, 0, sizeof(*txdesc)); | 133 | memset(txdesc, 0, sizeof(*txdesc)); |
133 | 134 | ||
@@ -213,14 +214,14 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry, | |||
213 | * sequence counter given by mac80211. | 214 | * sequence counter given by mac80211. |
214 | */ | 215 | */ |
215 | if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | 216 | if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
216 | spin_lock(&intf->lock); | 217 | spin_lock_irqsave(&intf->seqlock, irqflags); |
217 | 218 | ||
218 | if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)) | 219 | if (test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags)) |
219 | intf->seqno += 0x10; | 220 | intf->seqno += 0x10; |
220 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | 221 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
221 | hdr->seq_ctrl |= cpu_to_le16(intf->seqno); | 222 | hdr->seq_ctrl |= cpu_to_le16(intf->seqno); |
222 | 223 | ||
223 | spin_unlock(&intf->lock); | 224 | spin_unlock_irqrestore(&intf->seqlock, irqflags); |
224 | 225 | ||
225 | __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags); | 226 | __set_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags); |
226 | } | 227 | } |
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c index 933e6cc9359d..8d76bb2e0312 100644 --- a/drivers/net/wireless/rt2x00/rt2x00usb.c +++ b/drivers/net/wireless/rt2x00/rt2x00usb.c | |||
@@ -124,7 +124,7 @@ EXPORT_SYMBOL_GPL(rt2x00usb_vendor_request_buff); | |||
124 | 124 | ||
125 | int rt2x00usb_vendor_request_large_buff(struct rt2x00_dev *rt2x00dev, | 125 | int rt2x00usb_vendor_request_large_buff(struct rt2x00_dev *rt2x00dev, |
126 | const u8 request, const u8 requesttype, | 126 | const u8 request, const u8 requesttype, |
127 | const u16 offset, void *buffer, | 127 | const u16 offset, const void *buffer, |
128 | const u16 buffer_length, | 128 | const u16 buffer_length, |
129 | const int timeout) | 129 | const int timeout) |
130 | { | 130 | { |
@@ -134,7 +134,7 @@ int rt2x00usb_vendor_request_large_buff(struct rt2x00_dev *rt2x00dev, | |||
134 | 134 | ||
135 | mutex_lock(&rt2x00dev->usb_cache_mutex); | 135 | mutex_lock(&rt2x00dev->usb_cache_mutex); |
136 | 136 | ||
137 | tb = buffer; | 137 | tb = (char *)buffer; |
138 | off = offset; | 138 | off = offset; |
139 | len = buffer_length; | 139 | len = buffer_length; |
140 | while (len && !status) { | 140 | while (len && !status) { |
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.h b/drivers/net/wireless/rt2x00/rt2x00usb.h index ee3875f894aa..3b4a67417f95 100644 --- a/drivers/net/wireless/rt2x00/rt2x00usb.h +++ b/drivers/net/wireless/rt2x00/rt2x00usb.h | |||
@@ -185,7 +185,7 @@ int rt2x00usb_vendor_req_buff_lock(struct rt2x00_dev *rt2x00dev, | |||
185 | */ | 185 | */ |
186 | int rt2x00usb_vendor_request_large_buff(struct rt2x00_dev *rt2x00dev, | 186 | int rt2x00usb_vendor_request_large_buff(struct rt2x00_dev *rt2x00dev, |
187 | const u8 request, const u8 requesttype, | 187 | const u8 request, const u8 requesttype, |
188 | const u16 offset, void *buffer, | 188 | const u16 offset, const void *buffer, |
189 | const u16 buffer_length, | 189 | const u16 buffer_length, |
190 | const int timeout); | 190 | const int timeout); |
191 | 191 | ||
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c index fbe2a652e014..087e90b328cd 100644 --- a/drivers/net/wireless/rt2x00/rt61pci.c +++ b/drivers/net/wireless/rt2x00/rt61pci.c | |||
@@ -1004,6 +1004,11 @@ static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data, | |||
1004 | } | 1004 | } |
1005 | 1005 | ||
1006 | /* | 1006 | /* |
1007 | * Hardware needs another millisecond before it is ready. | ||
1008 | */ | ||
1009 | msleep(1); | ||
1010 | |||
1011 | /* | ||
1007 | * Reset MAC and BBP registers. | 1012 | * Reset MAC and BBP registers. |
1008 | */ | 1013 | */ |
1009 | reg = 0; | 1014 | reg = 0; |
diff --git a/drivers/net/wireless/rtl8187.h b/drivers/net/wireless/rtl8187.h index 1b0d750f6623..5a9515c99960 100644 --- a/drivers/net/wireless/rtl8187.h +++ b/drivers/net/wireless/rtl8187.h | |||
@@ -94,6 +94,10 @@ struct rtl8187_priv { | |||
94 | const struct rtl818x_rf_ops *rf; | 94 | const struct rtl818x_rf_ops *rf; |
95 | struct ieee80211_vif *vif; | 95 | struct ieee80211_vif *vif; |
96 | int mode; | 96 | int mode; |
97 | /* The mutex protects the TX loopback state. | ||
98 | * Any attempt to set channels concurrently locks the device. | ||
99 | */ | ||
100 | struct mutex conf_mutex; | ||
97 | 101 | ||
98 | /* rtl8187 specific */ | 102 | /* rtl8187 specific */ |
99 | struct ieee80211_channel channels[14]; | 103 | struct ieee80211_channel channels[14]; |
diff --git a/drivers/net/wireless/rtl8187_dev.c b/drivers/net/wireless/rtl8187_dev.c index 177988efd660..57376fb993ed 100644 --- a/drivers/net/wireless/rtl8187_dev.c +++ b/drivers/net/wireless/rtl8187_dev.c | |||
@@ -31,6 +31,8 @@ MODULE_DESCRIPTION("RTL8187/RTL8187B USB wireless driver"); | |||
31 | MODULE_LICENSE("GPL"); | 31 | MODULE_LICENSE("GPL"); |
32 | 32 | ||
33 | static struct usb_device_id rtl8187_table[] __devinitdata = { | 33 | static struct usb_device_id rtl8187_table[] __devinitdata = { |
34 | /* Asus */ | ||
35 | {USB_DEVICE(0x0b05, 0x171d), .driver_info = DEVICE_RTL8187}, | ||
34 | /* Realtek */ | 36 | /* Realtek */ |
35 | {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187}, | 37 | {USB_DEVICE(0x0bda, 0x8187), .driver_info = DEVICE_RTL8187}, |
36 | {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B}, | 38 | {USB_DEVICE(0x0bda, 0x8189), .driver_info = DEVICE_RTL8187B}, |
@@ -726,6 +728,7 @@ static int rtl8187_start(struct ieee80211_hw *dev) | |||
726 | if (ret) | 728 | if (ret) |
727 | return ret; | 729 | return ret; |
728 | 730 | ||
731 | mutex_lock(&priv->conf_mutex); | ||
729 | if (priv->is_rtl8187b) { | 732 | if (priv->is_rtl8187b) { |
730 | reg = RTL818X_RX_CONF_MGMT | | 733 | reg = RTL818X_RX_CONF_MGMT | |
731 | RTL818X_RX_CONF_DATA | | 734 | RTL818X_RX_CONF_DATA | |
@@ -747,6 +750,7 @@ static int rtl8187_start(struct ieee80211_hw *dev) | |||
747 | (7 << 0 /* long retry limit */) | | 750 | (7 << 0 /* long retry limit */) | |
748 | (7 << 21 /* MAX TX DMA */)); | 751 | (7 << 21 /* MAX TX DMA */)); |
749 | rtl8187_init_urbs(dev); | 752 | rtl8187_init_urbs(dev); |
753 | mutex_unlock(&priv->conf_mutex); | ||
750 | return 0; | 754 | return 0; |
751 | } | 755 | } |
752 | 756 | ||
@@ -790,6 +794,7 @@ static int rtl8187_start(struct ieee80211_hw *dev) | |||
790 | reg |= RTL818X_CMD_TX_ENABLE; | 794 | reg |= RTL818X_CMD_TX_ENABLE; |
791 | reg |= RTL818X_CMD_RX_ENABLE; | 795 | reg |= RTL818X_CMD_RX_ENABLE; |
792 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); | 796 | rtl818x_iowrite8(priv, &priv->map->CMD, reg); |
797 | mutex_unlock(&priv->conf_mutex); | ||
793 | 798 | ||
794 | return 0; | 799 | return 0; |
795 | } | 800 | } |
@@ -801,6 +806,7 @@ static void rtl8187_stop(struct ieee80211_hw *dev) | |||
801 | struct sk_buff *skb; | 806 | struct sk_buff *skb; |
802 | u32 reg; | 807 | u32 reg; |
803 | 808 | ||
809 | mutex_lock(&priv->conf_mutex); | ||
804 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); | 810 | rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); |
805 | 811 | ||
806 | reg = rtl818x_ioread8(priv, &priv->map->CMD); | 812 | reg = rtl818x_ioread8(priv, &priv->map->CMD); |
@@ -820,7 +826,7 @@ static void rtl8187_stop(struct ieee80211_hw *dev) | |||
820 | usb_kill_urb(info->urb); | 826 | usb_kill_urb(info->urb); |
821 | kfree_skb(skb); | 827 | kfree_skb(skb); |
822 | } | 828 | } |
823 | return; | 829 | mutex_unlock(&priv->conf_mutex); |
824 | } | 830 | } |
825 | 831 | ||
826 | static int rtl8187_add_interface(struct ieee80211_hw *dev, | 832 | static int rtl8187_add_interface(struct ieee80211_hw *dev, |
@@ -840,6 +846,7 @@ static int rtl8187_add_interface(struct ieee80211_hw *dev, | |||
840 | return -EOPNOTSUPP; | 846 | return -EOPNOTSUPP; |
841 | } | 847 | } |
842 | 848 | ||
849 | mutex_lock(&priv->conf_mutex); | ||
843 | priv->vif = conf->vif; | 850 | priv->vif = conf->vif; |
844 | 851 | ||
845 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); | 852 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG); |
@@ -848,6 +855,7 @@ static int rtl8187_add_interface(struct ieee80211_hw *dev, | |||
848 | ((u8 *)conf->mac_addr)[i]); | 855 | ((u8 *)conf->mac_addr)[i]); |
849 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); | 856 | rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL); |
850 | 857 | ||
858 | mutex_unlock(&priv->conf_mutex); | ||
851 | return 0; | 859 | return 0; |
852 | } | 860 | } |
853 | 861 | ||
@@ -855,8 +863,10 @@ static void rtl8187_remove_interface(struct ieee80211_hw *dev, | |||
855 | struct ieee80211_if_init_conf *conf) | 863 | struct ieee80211_if_init_conf *conf) |
856 | { | 864 | { |
857 | struct rtl8187_priv *priv = dev->priv; | 865 | struct rtl8187_priv *priv = dev->priv; |
866 | mutex_lock(&priv->conf_mutex); | ||
858 | priv->mode = IEEE80211_IF_TYPE_MNTR; | 867 | priv->mode = IEEE80211_IF_TYPE_MNTR; |
859 | priv->vif = NULL; | 868 | priv->vif = NULL; |
869 | mutex_unlock(&priv->conf_mutex); | ||
860 | } | 870 | } |
861 | 871 | ||
862 | static int rtl8187_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf) | 872 | static int rtl8187_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf) |
@@ -864,6 +874,7 @@ static int rtl8187_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf) | |||
864 | struct rtl8187_priv *priv = dev->priv; | 874 | struct rtl8187_priv *priv = dev->priv; |
865 | u32 reg; | 875 | u32 reg; |
866 | 876 | ||
877 | mutex_lock(&priv->conf_mutex); | ||
867 | reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); | 878 | reg = rtl818x_ioread32(priv, &priv->map->TX_CONF); |
868 | /* Enable TX loopback on MAC level to avoid TX during channel | 879 | /* Enable TX loopback on MAC level to avoid TX during channel |
869 | * changes, as this has be seen to causes problems and the | 880 | * changes, as this has be seen to causes problems and the |
@@ -896,6 +907,7 @@ static int rtl8187_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf) | |||
896 | rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100); | 907 | rtl818x_iowrite16(priv, &priv->map->ATIMTR_INTERVAL, 100); |
897 | rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100); | 908 | rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100); |
898 | rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100); | 909 | rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL_TIME, 100); |
910 | mutex_unlock(&priv->conf_mutex); | ||
899 | return 0; | 911 | return 0; |
900 | } | 912 | } |
901 | 913 | ||
@@ -907,6 +919,7 @@ static int rtl8187_config_interface(struct ieee80211_hw *dev, | |||
907 | int i; | 919 | int i; |
908 | u8 reg; | 920 | u8 reg; |
909 | 921 | ||
922 | mutex_lock(&priv->conf_mutex); | ||
910 | for (i = 0; i < ETH_ALEN; i++) | 923 | for (i = 0; i < ETH_ALEN; i++) |
911 | rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]); | 924 | rtl818x_iowrite8(priv, &priv->map->BSSID[i], conf->bssid[i]); |
912 | 925 | ||
@@ -920,6 +933,7 @@ static int rtl8187_config_interface(struct ieee80211_hw *dev, | |||
920 | rtl818x_iowrite8(priv, &priv->map->MSR, reg); | 933 | rtl818x_iowrite8(priv, &priv->map->MSR, reg); |
921 | } | 934 | } |
922 | 935 | ||
936 | mutex_unlock(&priv->conf_mutex); | ||
923 | return 0; | 937 | return 0; |
924 | } | 938 | } |
925 | 939 | ||
@@ -1187,6 +1201,7 @@ static int __devinit rtl8187_probe(struct usb_interface *intf, | |||
1187 | printk(KERN_ERR "rtl8187: Cannot register device\n"); | 1201 | printk(KERN_ERR "rtl8187: Cannot register device\n"); |
1188 | goto err_free_dev; | 1202 | goto err_free_dev; |
1189 | } | 1203 | } |
1204 | mutex_init(&priv->conf_mutex); | ||
1190 | 1205 | ||
1191 | printk(KERN_INFO "%s: hwaddr %s, %s V%d + %s\n", | 1206 | printk(KERN_INFO "%s: hwaddr %s, %s V%d + %s\n", |
1192 | wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr), | 1207 | wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr), |