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authorLennert Buytenhek <buytenh@wantstofly.org>2007-10-18 22:11:47 -0400
committerDale Farnsworth <dale@farnsworth.org>2007-10-23 11:23:13 -0400
commitb45d9147f1582333e180e1023624c003874b7312 (patch)
tree0dba64f6b1a977a2057b7eb2d7816032624bcad7 /drivers
parent5688fe87a458a73d5066eee3d5c9891459ba70bf (diff)
mv643xx_eth: Remove unused register defines
Most of the register defines in drivers/net/mv643xx_eth.h aren't used at all. Nuke them -- we can always re-add them if/when we need them, and meanwhile, they unnecessarily clutter up the header file. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Tzachi Perelstein <tzachi@marvell.com> Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/mv643xx_eth.h87
1 files changed, 0 insertions, 87 deletions
diff --git a/drivers/net/mv643xx_eth.h b/drivers/net/mv643xx_eth.h
index ed8539762a64..318183e6da87 100644
--- a/drivers/net/mv643xx_eth.h
+++ b/drivers/net/mv643xx_eth.h
@@ -57,115 +57,28 @@
57 */ 57 */
58#define PHY_ADDR_REG 0x0000 58#define PHY_ADDR_REG 0x0000
59#define SMI_REG 0x0004 59#define SMI_REG 0x0004
60#define UNIT_DEFAULT_ADDR_REG 0x0008
61#define UNIT_DEFAULTID_REG 0x000c
62#define UNIT_INTERRUPT_CAUSE_REG 0x0080
63#define UNIT_INTERRUPT_MASK_REG 0x0084
64#define UNIT_INTERNAL_USE_REG 0x04fc
65#define UNIT_ERROR_ADDR_REG 0x0094
66#define BAR_0 0x0200
67#define BAR_1 0x0208
68#define BAR_2 0x0210
69#define BAR_3 0x0218
70#define BAR_4 0x0220
71#define BAR_5 0x0228
72#define SIZE_REG_0 0x0204
73#define SIZE_REG_1 0x020c
74#define SIZE_REG_2 0x0214
75#define SIZE_REG_3 0x021c
76#define SIZE_REG_4 0x0224
77#define SIZE_REG_5 0x022c
78#define HEADERS_RETARGET_BASE_REG 0x0230
79#define HEADERS_RETARGET_CONTROL_REG 0x0234
80#define HIGH_ADDR_REMAP_REG_0 0x0280
81#define HIGH_ADDR_REMAP_REG_1 0x0284
82#define HIGH_ADDR_REMAP_REG_2 0x0288
83#define HIGH_ADDR_REMAP_REG_3 0x028c
84#define BASE_ADDR_ENABLE_REG 0x0290
85 60
86 61
87/* 62/*
88 * Per-port registers. 63 * Per-port registers.
89 */ 64 */
90#define ACCESS_PROTECTION_REG(p) (0x0294 + ((p) << 2))
91#define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10)) 65#define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10))
92#define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10)) 66#define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10))
93#define MII_SERIAL_PARAMETRS_REG(p) (0x0408 + ((p) << 10))
94#define GMII_SERIAL_PARAMETRS_REG(p) (0x040c + ((p) << 10))
95#define VLAN_ETHERTYPE_REG(p) (0x0410 + ((p) << 10))
96#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10)) 67#define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
97#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10)) 68#define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
98#define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10)) 69#define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10))
99#define DSCP_0(p) (0x0420 + ((p) << 10))
100#define DSCP_1(p) (0x0424 + ((p) << 10))
101#define DSCP_2(p) (0x0428 + ((p) << 10))
102#define DSCP_3(p) (0x042c + ((p) << 10))
103#define DSCP_4(p) (0x0430 + ((p) << 10))
104#define DSCP_5(p) (0x0434 + ((p) << 10))
105#define DSCP_6(p) (0x0438 + ((p) << 10))
106#define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10)) 70#define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10))
107#define VLAN_PRIORITY_TAG_TO_PRIORITY(p) (0x0440 + ((p) << 10))
108#define PORT_STATUS_REG(p) (0x0444 + ((p) << 10)) 71#define PORT_STATUS_REG(p) (0x0444 + ((p) << 10))
109#define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10)) 72#define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10))
110#define TX_QUEUE_FIXED_PRIORITY(p) (0x044c + ((p) << 10))
111#define PORT_TX_TOKEN_BUCKET_RATE_CONFIG(p) (0x0450 + ((p) << 10))
112#define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10)) 73#define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10))
113#define PORT_MAXIMUM_TOKEN_BUCKET_SIZE(p) (0x045c + ((p) << 10))
114#define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10)) 74#define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10))
115#define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10)) 75#define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10))
116#define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10)) 76#define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10))
117#define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10)) 77#define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10))
118#define RX_FIFO_URGENT_THRESHOLD_REG(p) (0x0470 + ((p) << 10))
119#define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10)) 78#define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10))
120#define RX_MINIMAL_FRAME_SIZE_REG(p) (0x047c + ((p) << 10))
121#define RX_DISCARDED_FRAMES_COUNTER(p) (0x0484 + ((p) << 10))
122#define PORT_DEBUG_0_REG(p) (0x048c + ((p) << 10))
123#define PORT_DEBUG_1_REG(p) (0x0490 + ((p) << 10))
124#define PORT_INTERNAL_ADDR_ERROR_REG(p) (0x0494 + ((p) << 10))
125#define INTERNAL_USE_REG(p) (0x04fc + ((p) << 10))
126#define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10)) 79#define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10))
127#define RX_CURRENT_QUEUE_DESC_PTR_1(p) (0x061c + ((p) << 10))
128#define RX_CURRENT_QUEUE_DESC_PTR_2(p) (0x062c + ((p) << 10))
129#define RX_CURRENT_QUEUE_DESC_PTR_3(p) (0x063c + ((p) << 10))
130#define RX_CURRENT_QUEUE_DESC_PTR_4(p) (0x064c + ((p) << 10))
131#define RX_CURRENT_QUEUE_DESC_PTR_5(p) (0x065c + ((p) << 10))
132#define RX_CURRENT_QUEUE_DESC_PTR_6(p) (0x066c + ((p) << 10))
133#define RX_CURRENT_QUEUE_DESC_PTR_7(p) (0x067c + ((p) << 10))
134#define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10)) 80#define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10))
135#define CURRENT_SERVED_TX_DESC_PTR(p) (0x0684 + ((p) << 10))
136#define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10)) 81#define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10))
137#define TX_CURRENT_QUEUE_DESC_PTR_1(p) (0x06c4 + ((p) << 10))
138#define TX_CURRENT_QUEUE_DESC_PTR_2(p) (0x06c8 + ((p) << 10))
139#define TX_CURRENT_QUEUE_DESC_PTR_3(p) (0x06cc + ((p) << 10))
140#define TX_CURRENT_QUEUE_DESC_PTR_4(p) (0x06d0 + ((p) << 10))
141#define TX_CURRENT_QUEUE_DESC_PTR_5(p) (0x06d4 + ((p) << 10))
142#define TX_CURRENT_QUEUE_DESC_PTR_6(p) (0x06d8 + ((p) << 10))
143#define TX_CURRENT_QUEUE_DESC_PTR_7(p) (0x06dc + ((p) << 10))
144#define TX_QUEUE_0_TOKEN_BUCKET_COUNT(p) (0x0700 + ((p) << 10))
145#define TX_QUEUE_0_TOKEN_BUCKET_CONFIG(p) (0x0704 + ((p) << 10))
146#define TX_QUEUE_0_ARBITER_CONFIG(p) (0x0708 + ((p) << 10))
147#define TX_QUEUE_1_TOKEN_BUCKET_COUNT(p) (0x0710 + ((p) << 10))
148#define TX_QUEUE_1_TOKEN_BUCKET_CONFIG(p) (0x0714 + ((p) << 10))
149#define TX_QUEUE_1_ARBITER_CONFIG(p) (0x0718 + ((p) << 10))
150#define TX_QUEUE_2_TOKEN_BUCKET_COUNT(p) (0x0720 + ((p) << 10))
151#define TX_QUEUE_2_TOKEN_BUCKET_CONFIG(p) (0x0724 + ((p) << 10))
152#define TX_QUEUE_2_ARBITER_CONFIG(p) (0x0728 + ((p) << 10))
153#define TX_QUEUE_3_TOKEN_BUCKET_COUNT(p) (0x0730 + ((p) << 10))
154#define TX_QUEUE_3_TOKEN_BUCKET_CONFIG(p) (0x0734 + ((p) << 10))
155#define TX_QUEUE_3_ARBITER_CONFIG(p) (0x0738 + ((p) << 10))
156#define TX_QUEUE_4_TOKEN_BUCKET_COUNT(p) (0x0740 + ((p) << 10))
157#define TX_QUEUE_4_TOKEN_BUCKET_CONFIG(p) (0x0744 + ((p) << 10))
158#define TX_QUEUE_4_ARBITER_CONFIG(p) (0x0748 + ((p) << 10))
159#define TX_QUEUE_5_TOKEN_BUCKET_COUNT(p) (0x0750 + ((p) << 10))
160#define TX_QUEUE_5_TOKEN_BUCKET_CONFIG(p) (0x0754 + ((p) << 10))
161#define TX_QUEUE_5_ARBITER_CONFIG(p) (0x0758 + ((p) << 10))
162#define TX_QUEUE_6_TOKEN_BUCKET_COUNT(p) (0x0760 + ((p) << 10))
163#define TX_QUEUE_6_TOKEN_BUCKET_CONFIG(p) (0x0764 + ((p) << 10))
164#define TX_QUEUE_6_ARBITER_CONFIG(p) (0x0768 + ((p) << 10))
165#define TX_QUEUE_7_TOKEN_BUCKET_COUNT(p) (0x0770 + ((p) << 10))
166#define TX_QUEUE_7_TOKEN_BUCKET_CONFIG(p) (0x0774 + ((p) << 10))
167#define TX_QUEUE_7_ARBITER_CONFIG(p) (0x0778 + ((p) << 10))
168#define PORT_TX_TOKEN_BUCKET_COUNT(p) (0x0780 + ((p) << 10))
169#define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7)) 82#define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7))
170#define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10)) 83#define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10))
171#define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10)) 84#define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10))
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