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authorBen Cahill <ben.m.cahill@intel.com>2007-11-28 22:09:57 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:05:24 -0500
commit9948b5445614a75112b85ae3bc8f6e2f6655c7df (patch)
tree55940055c51516ff7fe61190f14e4d975ee164ec /drivers
parent6440adb5760a897497c2b1ebdccc32c7944fd57f (diff)
iwlwifi: Clean up unused definitions in iwl-3945-hw.h
Clean up unused definitions in iwl-3945-hw.h Signed-off-by: Ben Cahill <ben.m.cahill@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945-hw.h130
1 files changed, 1 insertions, 129 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
index 97bffb1a029b..4fa947d7bad5 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945-hw.h
@@ -102,10 +102,6 @@
102#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ 102#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
103#define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */ 103#define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */
104 104
105/* EEPROM field values */
106#define ANTENNA_SWITCH_NORMAL 0
107#define ANTENNA_SWITCH_INVERSE 1
108
109/* 105/*
110 * Regulatory channel usage flags in EEPROM struct iwl_eeprom_channel.flags. 106 * Regulatory channel usage flags in EEPROM struct iwl_eeprom_channel.flags.
111 * 107 *
@@ -127,31 +123,10 @@ enum {
127 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ 123 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
128 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ 124 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
129 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ 125 EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
130 EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel, not used */ 126 EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel (not used) */
131 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ 127 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
132}; 128};
133 129
134/* EEPROM field lengths */
135#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
136
137/* EEPROM field lengths */
138#define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
139#define EEPROM_REGULATORY_SKU_ID_LENGTH 4
140#define EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH 14
141#define EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH 13
142#define EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH 12
143#define EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH 11
144#define EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH 6
145
146#define EEPROM_REGULATORY_CHANNELS_LENGTH ( \
147 EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH + \
148 EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH + \
149 EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH + \
150 EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH + \
151 EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH)
152
153#define EEPROM_REGULATORY_NUMBER_OF_BANDS 5
154
155/* SKU Capabilities */ 130/* SKU Capabilities */
156#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) 131#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
157#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) 132#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
@@ -646,15 +621,7 @@ struct iwl3945_eeprom {
646/* spectrum and channel data structures */ 621/* spectrum and channel data structures */
647#define IWL_NUM_SCAN_RATES (2) 622#define IWL_NUM_SCAN_RATES (2)
648 623
649#define IWL_SCAN_FLAG_24GHZ (1<<0)
650#define IWL_SCAN_FLAG_52GHZ (1<<1)
651#define IWL_SCAN_FLAG_ACTIVE (1<<2)
652#define IWL_SCAN_FLAG_DIRECT (1<<3)
653
654#define IWL_MAX_CMD_SIZE 1024
655
656#define IWL_DEFAULT_TX_RETRY 15 624#define IWL_DEFAULT_TX_RETRY 15
657#define IWL_MAX_TX_RETRY 16
658 625
659/*********************************************/ 626/*********************************************/
660 627
@@ -665,101 +632,6 @@ struct iwl3945_eeprom {
665#define RX_QUEUE_MASK 255 632#define RX_QUEUE_MASK 255
666#define RX_QUEUE_SIZE_LOG 8 633#define RX_QUEUE_SIZE_LOG 8
667 634
668/* QoS definitions */
669
670#define CW_MIN_OFDM 15
671#define CW_MAX_OFDM 1023
672#define CW_MIN_CCK 31
673#define CW_MAX_CCK 1023
674
675#define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM
676#define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM
677#define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
678#define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1)
679
680#define QOS_TX0_CW_MIN_CCK CW_MIN_CCK
681#define QOS_TX1_CW_MIN_CCK CW_MIN_CCK
682#define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1)
683#define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1)
684
685#define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM
686#define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM
687#define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM
688#define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
689
690#define QOS_TX0_CW_MAX_CCK CW_MAX_CCK
691#define QOS_TX1_CW_MAX_CCK CW_MAX_CCK
692#define QOS_TX2_CW_MAX_CCK CW_MIN_CCK
693#define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1)
694
695#define QOS_TX0_AIFS 3
696#define QOS_TX1_AIFS 7
697#define QOS_TX2_AIFS 2
698#define QOS_TX3_AIFS 2
699
700#define QOS_TX0_ACM 0
701#define QOS_TX1_ACM 0
702#define QOS_TX2_ACM 0
703#define QOS_TX3_ACM 0
704
705#define QOS_TX0_TXOP_LIMIT_CCK 0
706#define QOS_TX1_TXOP_LIMIT_CCK 0
707#define QOS_TX2_TXOP_LIMIT_CCK 6016
708#define QOS_TX3_TXOP_LIMIT_CCK 3264
709
710#define QOS_TX0_TXOP_LIMIT_OFDM 0
711#define QOS_TX1_TXOP_LIMIT_OFDM 0
712#define QOS_TX2_TXOP_LIMIT_OFDM 3008
713#define QOS_TX3_TXOP_LIMIT_OFDM 1504
714
715#define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM
716#define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM
717#define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM
718#define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM
719
720#define DEF_TX0_CW_MIN_CCK CW_MIN_CCK
721#define DEF_TX1_CW_MIN_CCK CW_MIN_CCK
722#define DEF_TX2_CW_MIN_CCK CW_MIN_CCK
723#define DEF_TX3_CW_MIN_CCK CW_MIN_CCK
724
725#define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM
726#define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM
727#define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM
728#define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM
729
730#define DEF_TX0_CW_MAX_CCK CW_MAX_CCK
731#define DEF_TX1_CW_MAX_CCK CW_MAX_CCK
732#define DEF_TX2_CW_MAX_CCK CW_MAX_CCK
733#define DEF_TX3_CW_MAX_CCK CW_MAX_CCK
734
735#define DEF_TX0_AIFS (2)
736#define DEF_TX1_AIFS (2)
737#define DEF_TX2_AIFS (2)
738#define DEF_TX3_AIFS (2)
739
740#define DEF_TX0_ACM 0
741#define DEF_TX1_ACM 0
742#define DEF_TX2_ACM 0
743#define DEF_TX3_ACM 0
744
745#define DEF_TX0_TXOP_LIMIT_CCK 0
746#define DEF_TX1_TXOP_LIMIT_CCK 0
747#define DEF_TX2_TXOP_LIMIT_CCK 0
748#define DEF_TX3_TXOP_LIMIT_CCK 0
749
750#define DEF_TX0_TXOP_LIMIT_OFDM 0
751#define DEF_TX1_TXOP_LIMIT_OFDM 0
752#define DEF_TX2_TXOP_LIMIT_OFDM 0
753#define DEF_TX3_TXOP_LIMIT_OFDM 0
754
755#define QOS_QOS_SETS 3
756#define QOS_PARAM_SET_ACTIVE 0
757#define QOS_PARAM_SET_DEF_CCK 1
758#define QOS_PARAM_SET_DEF_OFDM 2
759
760#define CTRL_QOS_NO_ACK (0x0020)
761#define DCT_FLAG_EXT_QOS_ENABLED (0x10)
762
763#define U32_PAD(n) ((4-(n))&0x3) 635#define U32_PAD(n) ((4-(n))&0x3)
764 636
765/* 637/*