Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (21 commits)
  x86/PCI: use dev_printk when possible
  PCI: add D3 power state avoidance quirk
  PCI: fix bogus "'device' may be used uninitialized" warning in pci_slot
  PCI: add an option to allow ASPM enabled forcibly
  PCI: disable ASPM on pre-1.1 PCIe devices
  PCI: disable ASPM per ACPI FADT setting
  PCI MSI: Don't disable MSIs if the mask bit isn't supported
  PCI: handle 64-bit resources better on 32-bit machines
  PCI: rewrite PCI BAR reading code
  PCI: document pci_target_state
  PCI hotplug: fix typo in pcie hotplug output
  x86 gart: replace to_pages macro with iommu_num_pages
  x86, AMD IOMMU: replace to_pages macro with iommu_num_pages
  iommu: add iommu_num_pages helper function
  dma-coherent: add documentation to new interfaces
  Cris: convert to using generic dma-coherent mem allocator
  Sh: use generic per-device coherent dma allocator
  ARM: support generic per-device coherent dma mem
  Generic dma-coherent: fix DMA_MEMORY_EXCLUSIVE
  x86: use generic per-device dma coherent allocator
  ...

8 files changed, 204 insertions, 138 deletions

diff --git a/drivers/acpi/pci_slot.c b/drivers/acpi/pci_slot.c
index dd376f7ad090..d5b4ef898879 100644
--- a/drivers/acpi/pci_slot.c
+++ b/drivers/acpi/pci_slot.c
@@ -76,9 +76,9 @@ static struct acpi_pci_driver acpi_pci_slot_driver = {
 };
 
 static int
-check_slot(acpi_handle handle, int *device, unsigned long *sun)
+check_slot(acpi_handle handle, unsigned long *sun)
 {
-        int retval = 0;
+        int device = -1;
         unsigned long adr, sta;
         acpi_status status;
         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
@@ -89,32 +89,27 @@ check_slot(acpi_handle handle, int *device, unsigned long *sun)
         if (check_sta_before_sun) {
                 /* If SxFy doesn't have _STA, we just assume it's there */
                 status = acpi_evaluate_integer(handle, "_STA", NULL, &sta);
-                if (ACPI_SUCCESS(status) && !(sta & ACPI_STA_DEVICE_PRESENT)) {
-                        retval = -1;
+                if (ACPI_SUCCESS(status) && !(sta & ACPI_STA_DEVICE_PRESENT))
                         goto out;
-                }
         }
 
         status = acpi_evaluate_integer(handle, "_ADR", NULL, &adr);
         if (ACPI_FAILURE(status)) {
                 dbg("_ADR returned %d on %s\n", status, (char *)buffer.pointer);
-                retval = -1;
                 goto out;
         }
 
-        *device = (adr >> 16) & 0xffff;
-
         /* No _SUN == not a slot == bail */
         status = acpi_evaluate_integer(handle, "_SUN", NULL, sun);
         if (ACPI_FAILURE(status)) {
                 dbg("_SUN returned %d on %s\n", status, (char *)buffer.pointer);
-                retval = -1;
                 goto out;
         }
 
+        device = (adr >> 16) & 0xffff;
 out:
         kfree(buffer.pointer);
-        return retval;
+        return device;
 }
 
 struct callback_args {
@@ -144,7 +139,8 @@ register_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
         struct callback_args *parent_context = context;
         struct pci_bus *pci_bus = parent_context->pci_bus;
 
-        if (check_slot(handle, &device, &sun))
+        device = check_slot(handle, &sun);
+        if (device < 0)
                 return AE_OK;
 
         slot = kmalloc(sizeof(*slot), GFP_KERNEL);
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 1323a43285d7..ad27e9e225a6 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -1103,7 +1103,7 @@ static inline void dbg_ctrl(struct controller *ctrl)
         dbg("  Power Indicator      : %3s\n", PWR_LED(ctrl)    ? "yes" : "no");
         dbg("  Hot-Plug Surprise    : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no");
         dbg("  EMI Present          : %3s\n", EMI(ctrl)        ? "yes" : "no");
-        dbg("  Comamnd Completed    : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes");
+        dbg("  Command Completed    : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes");
         pciehp_readw(ctrl, SLOTSTATUS, &reg16);
         dbg("Slot Status            : 0x%04x\n", reg16);
         pciehp_readw(ctrl, SLOTCTRL, &reg16);
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 15af618d36e2..18354817173c 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -126,7 +126,16 @@ static void msix_flush_writes(unsigned int irq)
         }
 }
 
-static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
+/*
+ * PCI 2.3 does not specify mask bits for each MSI interrupt.  Attempting to
+ * mask all MSI interrupts by clearing the MSI enable bit does not work
+ * reliably as devices without an INTx disable bit will then generate a
+ * level IRQ which will never be cleared.
+ *
+ * Returns 1 if it succeeded in masking the interrupt and 0 if the device
+ * doesn't support MSI masking.
+ */
+static int msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
 {
         struct msi_desc *entry;
 
@@ -144,8 +153,7 @@ static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
                         mask_bits |= flag & mask;
                         pci_write_config_dword(entry->dev, pos, mask_bits);
                 } else {
-                        __msi_set_enable(entry->dev, entry->msi_attrib.pos,
-                                         !flag);
+                        return 0;
                 }
                 break;
         case PCI_CAP_ID_MSIX:
@@ -161,6 +169,7 @@ static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
                 break;
         }
         entry->msi_attrib.masked = !!flag;
+        return 1;
 }
 
 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 7764768b6a0e..89a2f0fa10f9 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/module.h>
+#include <linux/pci-aspm.h>
 #include <acpi/acpi.h>
 #include <acpi/acnamesp.h>
 #include <acpi/acresrc.h>
@@ -372,6 +373,12 @@ static int __init acpi_pci_init(void)
                 printk(KERN_INFO"ACPI FADT declares the system doesn't support MSI, so disable it\n");
                 pci_no_msi();
         }
+
+        if (acpi_gbl_FADT.boot_flags & BAF_PCIE_ASPM_CONTROL) {
+                printk(KERN_INFO"ACPI FADT declares the system doesn't support PCIe ASPM, so disable it\n");
+                pcie_no_aspm();
+        }
+
         ret = register_acpi_bus_type(&acpi_pci_bus);
         if (ret)
                 return 0;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index e9c356236d27..0a3d856833fc 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -572,6 +572,10 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
                 if (!ret)
                         pci_update_current_state(dev);
         }
+        /* This device is quirked not to be put into D3, so
+           don't put it in D3 */
+        if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
+                return 0;
 
         error = pci_raw_set_power_state(dev, state);
 
@@ -1123,6 +1127,12 @@ int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
 }
 
 /**
+ * pci_target_state - find an appropriate low power state for a given PCI dev
+ * @dev: PCI device
+ *
+ * Use underlying platform code to find a supported low power state for @dev.
+ * If the platform can't manage @dev, return the deepest state from which it
+ * can generate wake events, based on any available PME info.
  */
 pci_power_t pci_target_state(struct pci_dev *dev)
 {
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index f82495583e63..9a7c9e1408a4 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -55,7 +55,7 @@ struct pcie_link_state {
         struct endpoint_state endpoints[8];
 };
 
-static int aspm_disabled;
+static int aspm_disabled, aspm_force;
 static DEFINE_MUTEX(aspm_lock);
 static LIST_HEAD(link_list);
 
@@ -510,6 +510,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
 {
         struct pci_dev *child_dev;
         int child_pos;
+        u32 reg32;
 
         /*
          * Some functions in a slot might not all be PCIE functions, very
@@ -519,6 +520,19 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
                 child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
                 if (!child_pos)
                         return -EINVAL;
+
+                /*
+                 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
+                 * RBER bit to determine if a function is 1.1 version device
+                 */
+                pci_read_config_dword(child_dev, child_pos + PCI_EXP_DEVCAP,
+                        &reg32);
+                if (!(reg32 & PCI_EXP_DEVCAP_RBER && !aspm_force)) {
+                        printk("Pre-1.1 PCIe device detected, "
+                                "disable ASPM for %s. It can be enabled forcedly"
+                                " with 'pcie_aspm=force'\n", pci_name(pdev));
+                        return -EINVAL;
+                }
         }
         return 0;
 }
@@ -802,11 +816,23 @@ void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
 
 static int __init pcie_aspm_disable(char *str)
 {
-        aspm_disabled = 1;
+        if (!strcmp(str, "off")) {
+                aspm_disabled = 1;
+                printk(KERN_INFO "PCIe ASPM is disabled\n");
+        } else if (!strcmp(str, "force")) {
+                aspm_force = 1;
+                printk(KERN_INFO "PCIe ASPM is forcedly enabled\n");
+        }
         return 1;
 }
 
-__setup("pcie_noaspm", pcie_aspm_disable);
+__setup("pcie_aspm=", pcie_aspm_disable);
+
+void pcie_no_aspm(void)
+{
+        if (!aspm_force)
+                aspm_disabled = 1;
+}
 
 #ifdef CONFIG_ACPI
 #include <acpi/acpi_bus.h>
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index b1724cf31b66..7098dfb07449 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -163,12 +163,9 @@ static inline unsigned int pci_calc_resource_flags(unsigned int flags)
         return IORESOURCE_MEM;
 }
 
-/*
- * Find the extent of a PCI decode..
- */
-static u32 pci_size(u32 base, u32 maxbase, u32 mask)
+static u64 pci_size(u64 base, u64 maxbase, u64 mask)
 {
-        u32 size = mask & maxbase;      /* Find the significant bits */
+        u64 size = mask & maxbase;      /* Find the significant bits */
         if (!size)
                 return 0;
 
@@ -184,135 +181,142 @@ static u32 pci_size(u32 base, u32 maxbase, u32 mask)
         return size;
 }
 
-static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
-{
-        u64 size = mask & maxbase;      /* Find the significant bits */
-        if (!size)
-                return 0;
+enum pci_bar_type {
+        pci_bar_unknown,        /* Standard PCI BAR probe */
+        pci_bar_io,             /* An io port BAR */
+        pci_bar_mem32,          /* A 32-bit memory BAR */
+        pci_bar_mem64,          /* A 64-bit memory BAR */
+};
 
-        /* Get the lowest of them to find the decode size, and
-           from that the extent.  */
-        size = (size & ~(size-1)) - 1;
+static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
+{
+        if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
+                res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
+                return pci_bar_io;
+        }
 
-        /* base == maxbase can be valid only if the BAR has
-           already been programmed with all 1s.  */
-        if (base == maxbase && ((base | size) & mask) != mask)
-                return 0;
+        res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
 
-        return size;
+        if (res->flags == PCI_BASE_ADDRESS_MEM_TYPE_64)
+                return pci_bar_mem64;
+        return pci_bar_mem32;
 }
 
-static inline int is_64bit_memory(u32 mask)
+/*
+ * If the type is not unknown, we assume that the lowest bit is 'enable'.
+ * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
+ */
+static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
+                        struct resource *res, unsigned int pos)
 {
-        if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
-            (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
-                return 1;
-        return 0;
-}
+        u32 l, sz, mask;
 
-static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
-{
-        unsigned int pos, reg, next;
-        u32 l, sz;
-        struct resource *res;
+        mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
 
-        for(pos=0; pos<howmany; pos = next) {
-                u64 l64;
-                u64 sz64;
-                u32 raw_sz;
+        res->name = pci_name(dev);
 
-                next = pos+1;
-                res = &dev->resource[pos];
-                res->name = pci_name(dev);
-                reg = PCI_BASE_ADDRESS_0 + (pos << 2);
-                pci_read_config_dword(dev, reg, &l);
-                pci_write_config_dword(dev, reg, ~0);
-                pci_read_config_dword(dev, reg, &sz);
-                pci_write_config_dword(dev, reg, l);
-                if (!sz || sz == 0xffffffff)
-                        continue;
-                if (l == 0xffffffff)
-                        l = 0;
-                raw_sz = sz;
-                if ((l & PCI_BASE_ADDRESS_SPACE) ==
-                                PCI_BASE_ADDRESS_SPACE_MEMORY) {
-                        sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
-                        /*
-                         * For 64bit prefetchable memory sz could be 0, if the
-                         * real size is bigger than 4G, so we need to check
-                         * szhi for that.
-                         */
-                        if (!is_64bit_memory(l) && !sz)
-                                continue;
-                        res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
-                        res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
+        pci_read_config_dword(dev, pos, &l);
+        pci_write_config_dword(dev, pos, mask);
+        pci_read_config_dword(dev, pos, &sz);
+        pci_write_config_dword(dev, pos, l);
+
+        /*
+         * All bits set in sz means the device isn't working properly.
+         * If the BAR isn't implemented, all bits must be 0.  If it's a
+         * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
+         * 1 must be clear.
+         */
+        if (!sz || sz == 0xffffffff)
+                goto fail;
+
+        /*
+         * I don't know how l can have all bits set.  Copied from old code.
+         * Maybe it fixes a bug on some ancient platform.
+         */
+        if (l == 0xffffffff)
+                l = 0;
+
+        if (type == pci_bar_unknown) {
+                type = decode_bar(res, l);
+                res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
+                if (type == pci_bar_io) {
+                        l &= PCI_BASE_ADDRESS_IO_MASK;
+                        mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
                 } else {
-                        sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
-                        if (!sz)
-                                continue;
-                        res->start = l & PCI_BASE_ADDRESS_IO_MASK;
-                        res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
+                        l &= PCI_BASE_ADDRESS_MEM_MASK;
+                        mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
                 }
-                res->end = res->start + (unsigned long) sz;
-                res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
-                if (is_64bit_memory(l)) {
-                        u32 szhi, lhi;
-
-                        pci_read_config_dword(dev, reg+4, &lhi);
-                        pci_write_config_dword(dev, reg+4, ~0);
-                        pci_read_config_dword(dev, reg+4, &szhi);
-                        pci_write_config_dword(dev, reg+4, lhi);
-                        sz64 = ((u64)szhi << 32) | raw_sz;
-                        l64 = ((u64)lhi << 32) | l;
-                        sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
-                        next++;
-#if BITS_PER_LONG == 64
-                        if (!sz64) {
-                                res->start = 0;
-                                res->end = 0;
-                                res->flags = 0;
-                                continue;
-                        }
-                        res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
-                        res->end = res->start + sz64;
-#else
-                        if (sz64 > 0x100000000ULL) {
-                                dev_err(&dev->dev, "BAR %d: can't handle 64-bit"
-                                        " BAR\n", pos);
-                                res->start = 0;
-                                res->flags = 0;
-                        } else if (lhi) {
-                                /* 64-bit wide address, treat as disabled */
-                                pci_write_config_dword(dev, reg,
-                                        l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
-                                pci_write_config_dword(dev, reg+4, 0);
-                                res->start = 0;
-                                res->end = sz;
-                        }
-#endif
+        } else {
+                res->flags |= (l & IORESOURCE_ROM_ENABLE);
+                l &= PCI_ROM_ADDRESS_MASK;
+                mask = (u32)PCI_ROM_ADDRESS_MASK;
+        }
+
+        if (type == pci_bar_mem64) {
+                u64 l64 = l;
+                u64 sz64 = sz;
+                u64 mask64 = mask | (u64)~0 << 32;
+
+                pci_read_config_dword(dev, pos + 4, &l);
+                pci_write_config_dword(dev, pos + 4, ~0);
+                pci_read_config_dword(dev, pos + 4, &sz);
+                pci_write_config_dword(dev, pos + 4, l);
+
+                l64 |= ((u64)l << 32);
+                sz64 |= ((u64)sz << 32);
+
+                sz64 = pci_size(l64, sz64, mask64);
+
+                if (!sz64)
+                        goto fail;
+
+                if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
+                        dev_err(&dev->dev, "can't handle 64-bit BAR\n");
+                        goto fail;
+                } else if ((sizeof(resource_size_t) < 8) && l) {
+                        /* Address above 32-bit boundary; disable the BAR */
+                        pci_write_config_dword(dev, pos, 0);
+                        pci_write_config_dword(dev, pos + 4, 0);
+                        res->start = 0;
+                        res->end = sz64;
+                } else {
+                        res->start = l64;
+                        res->end = l64 + sz64;
                 }
+        } else {
+                sz = pci_size(l, sz, mask);
+
+                if (!sz)
+                        goto fail;
+
+                res->start = l;
+                res->end = l + sz;
         }
+
+ out:
+        return (type == pci_bar_mem64) ? 1 : 0;
+ fail:
+        res->flags = 0;
+        goto out;
+}
+
+static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
+{
+        unsigned int pos, reg;
+
+        for (pos = 0; pos < howmany; pos++) {
+                struct resource *res = &dev->resource[pos];
+                reg = PCI_BASE_ADDRESS_0 + (pos << 2);
+                pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
+        }
+
         if (rom) {
+                struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
                 dev->rom_base_reg = rom;
-                res = &dev->resource[PCI_ROM_RESOURCE];
-                res->name = pci_name(dev);
-                pci_read_config_dword(dev, rom, &l);
-                pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
-                pci_read_config_dword(dev, rom, &sz);
-                pci_write_config_dword(dev, rom, l);
-                if (l == 0xffffffff)
-                        l = 0;
-                if (sz && sz != 0xffffffff) {
-                        sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
-                        if (sz) {
-                                res->flags = (l & IORESOURCE_ROM_ENABLE) |
-                                  IORESOURCE_MEM | IORESOURCE_PREFETCH |
-                                  IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
-                                  IORESOURCE_SIZEALIGN;
-                                res->start = l & PCI_ROM_ADDRESS_MASK;
-                                res->end = res->start + (unsigned long) sz;
-                        }
-                }
+                res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
+                                IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
+                                IORESOURCE_SIZEALIGN;
+                __pci_read_base(dev, pci_bar_mem32, res, rom);
         }
 }
 
@@ -1053,7 +1057,8 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
                 }
         }
 
-        if (bus->self)
+        /* only one slot has pcie device */
+        if (bus->self && nr)
                 pcie_aspm_init_link_state(bus->self);
 
         return nr;
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 12d489395fad..0fb365074288 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -923,6 +923,19 @@ static void __init quirk_ide_samemode(struct pci_dev *pdev)
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
 
+/*
+ * Some ATA devices break if put into D3
+ */
+
+static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
+{
+        /* Quirk the legacy ATA devices only. The AHCI ones are ok */
+        if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
+                pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
+
 /* This was originally an Alpha specific thing, but it really fits here.
  * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
  */