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authorNaresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>2014-03-12 07:09:41 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-03-12 11:04:19 -0400
commite9fea5747d2b3dbff47a8790c1cc4d7af80051d6 (patch)
treed6292f9a6b121589682365bfc24c5dcd368f7f05 /drivers
parenta51435a3137ad8ae75c288c39bd2d8b2696bae8f (diff)
drm/i915: wait for rings to become idle once disabled
make sure we wait for rings to become idle once they are disabled. In case of timeout print an error message Signed-off-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com> [danvet: Frob patch as suggested by Chris.] Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c2
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h2
3 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 146609ab42bb..6174fda4d58e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -748,6 +748,7 @@ enum punit_power_well {
748#define RING_INSTPS(base) ((base)+0x70) 748#define RING_INSTPS(base) ((base)+0x70)
749#define RING_DMA_FADD(base) ((base)+0x78) 749#define RING_DMA_FADD(base) ((base)+0x78)
750#define RING_INSTPM(base) ((base)+0xc0) 750#define RING_INSTPM(base) ((base)+0xc0)
751#define RING_MI_MODE(base) ((base)+0x9c)
751#define INSTPS 0x02070 /* 965+ only */ 752#define INSTPS 0x02070 /* 965+ only */
752#define INSTDONE1 0x0207c /* 965+ only */ 753#define INSTDONE1 0x0207c /* 965+ only */
753#define ACTHD_I965 0x02074 754#define ACTHD_I965 0x02074
@@ -824,6 +825,7 @@ enum punit_power_well {
824# define VS_TIMER_DISPATCH (1 << 6) 825# define VS_TIMER_DISPATCH (1 << 6)
825# define MI_FLUSH_ENABLE (1 << 12) 826# define MI_FLUSH_ENABLE (1 << 12)
826# define ASYNC_FLIP_PERF_DISABLE (1 << 14) 827# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
828# define MODE_IDLE (1 << 9)
827 829
828#define GEN6_GT_MODE 0x20d0 830#define GEN6_GT_MODE 0x20d0
829#define GEN7_GT_MODE 0x7008 831#define GEN7_GT_MODE 0x7008
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 42b400144379..617634b6a6c2 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -444,6 +444,8 @@ static int init_ring_common(struct intel_ring_buffer *ring)
444 I915_WRITE_CTL(ring, 0); 444 I915_WRITE_CTL(ring, 0);
445 I915_WRITE_HEAD(ring, 0); 445 I915_WRITE_HEAD(ring, 0);
446 ring->write_tail(ring, 0); 446 ring->write_tail(ring, 0);
447 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000))
448 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name);
447 449
448 if (I915_NEED_GFX_HWS(dev)) 450 if (I915_NEED_GFX_HWS(dev))
449 intel_ring_setup_status_page(ring); 451 intel_ring_setup_status_page(ring);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 09af92099c1b..f11ceb230db4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -33,6 +33,8 @@ struct intel_hw_status_page {
33#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) 33#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
34#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) 34#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
35 35
36#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
37
36enum intel_ring_hangcheck_action { 38enum intel_ring_hangcheck_action {
37 HANGCHECK_IDLE = 0, 39 HANGCHECK_IDLE = 0,
38 HANGCHECK_WAIT, 40 HANGCHECK_WAIT,