aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorSujith <Sujith.Manoharan@atheros.com>2009-08-07 00:15:15 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-08-14 09:13:34 -0400
commitb5aec950eeb433d4850c1e5fcf14b666048e647d (patch)
tree4d38f9f64c0ff9bbededed207a5c92c1646ebdd6 /drivers
parent6780ccf5652a04493f72fafd9af0d9964ee977ad (diff)
ath9k: Split eeprom.c into manageable pieces
Add eeprom_def.c, eeprom_4k.c and eeprom_9287.c This improves maintainability. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/ath/ath9k/Makefile3
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.c3776
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom.h31
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c1181
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c1183
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c1385
6 files changed, 3814 insertions, 3745 deletions
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 783bc39eb2ff..28443e05ec10 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -1,5 +1,8 @@
1ath9k-y += hw.o \ 1ath9k-y += hw.o \
2 eeprom.o \ 2 eeprom.o \
3 eeprom_def.o \
4 eeprom_4k.o \
5 eeprom_9287.o \
3 mac.o \ 6 mac.o \
4 calib.o \ 7 calib.o \
5 ani.o \ 8 ani.o \
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index 79310225d3ab..958948bc73fd 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -16,9 +16,16 @@
16 16
17#include "ath9k.h" 17#include "ath9k.h"
18 18
19static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, 19static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
20 u32 reg, u32 mask, 20{
21 u32 shift, u32 val) 21 if (fbin == AR5416_BCHAN_UNUSED)
22 return fbin;
23
24 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
25}
26
27void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
28 u32 shift, u32 val)
22{ 29{
23 u32 regVal; 30 u32 regVal;
24 31
@@ -33,18 +40,8 @@ static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah,
33 return; 40 return;
34} 41}
35 42
36static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) 43int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
37{ 44 int16_t targetLeft, int16_t targetRight)
38 if (fbin == AR5416_BCHAN_UNUSED)
39 return fbin;
40
41 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
42}
43
44static inline int16_t ath9k_hw_interpolate(u16 target,
45 u16 srcLeft, u16 srcRight,
46 int16_t targetLeft,
47 int16_t targetRight)
48{ 45{
49 int16_t rv; 46 int16_t rv;
50 47
@@ -58,9 +55,8 @@ static inline int16_t ath9k_hw_interpolate(u16 target,
58 return rv; 55 return rv;
59} 56}
60 57
61static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, 58bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
62 u16 listSize, u16 *indexL, 59 u16 *indexL, u16 *indexR)
63 u16 *indexR)
64{ 60{
65 u16 i; 61 u16 i;
66 62
@@ -87,16 +83,16 @@ static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList,
87 return false; 83 return false;
88} 84}
89 85
90static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data) 86bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
91{ 87{
92 struct ath_softc *sc = ah->ah_sc; 88 struct ath_softc *sc = ah->ah_sc;
93 89
94 return sc->bus_ops->eeprom_read(ah, off, data); 90 return sc->bus_ops->eeprom_read(ah, off, data);
95} 91}
96 92
97static inline void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 93void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
98 u8 *pVpdList, u16 numIntercepts, 94 u8 *pVpdList, u16 numIntercepts,
99 u8 *pRetVpdList) 95 u8 *pRetVpdList)
100{ 96{
101 u16 i, k; 97 u16 i, k;
102 u8 currPwr = pwrMin; 98 u8 currPwr = pwrMin;
@@ -121,12 +117,12 @@ static inline void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
121 } 117 }
122} 118}
123 119
124static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, 120void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
125 struct ath9k_channel *chan, 121 struct ath9k_channel *chan,
126 struct cal_target_power_leg *powInfo, 122 struct cal_target_power_leg *powInfo,
127 u16 numChannels, 123 u16 numChannels,
128 struct cal_target_power_leg *pNewPower, 124 struct cal_target_power_leg *pNewPower,
129 u16 numRates, bool isExtTarget) 125 u16 numRates, bool isExtTarget)
130{ 126{
131 struct chan_centers centers; 127 struct chan_centers centers;
132 u16 clo, chi; 128 u16 clo, chi;
@@ -176,72 +172,12 @@ static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
176 } 172 }
177} 173}
178 174
179static void ath9k_get_txgain_index(struct ath_hw *ah, 175void ath9k_hw_get_target_powers(struct ath_hw *ah,
180 struct ath9k_channel *chan, 176 struct ath9k_channel *chan,
181 struct calDataPerFreqOpLoop *rawDatasetOpLoop, 177 struct cal_target_power_ht *powInfo,
182 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx) 178 u16 numChannels,
183{ 179 struct cal_target_power_ht *pNewPower,
184 u8 pcdac, i = 0; 180 u16 numRates, bool isHt40Target)
185 u16 idxL = 0, idxR = 0, numPiers;
186 bool match;
187 struct chan_centers centers;
188
189 ath9k_hw_get_channel_centers(ah, chan, &centers);
190
191 for (numPiers = 0; numPiers < availPiers; numPiers++)
192 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
193 break;
194
195 match = ath9k_hw_get_lower_upper_index(
196 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
197 calChans, numPiers, &idxL, &idxR);
198 if (match) {
199 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
200 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
201 } else {
202 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
203 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
204 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
205 }
206
207 while (pcdac > ah->originalGain[i] &&
208 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
209 i++;
210
211 *pcdacIdx = i;
212 return;
213}
214
215static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
216 u32 initTxGain,
217 int txPower,
218 u8 *pPDADCValues)
219{
220 u32 i;
221 u32 offset;
222
223 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
224 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
225 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
226 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
227
228 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
229 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
230
231 offset = txPower;
232 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
233 if (i < offset)
234 pPDADCValues[i] = 0x0;
235 else
236 pPDADCValues[i] = 0xFF;
237}
238
239static void ath9k_hw_get_target_powers(struct ath_hw *ah,
240 struct ath9k_channel *chan,
241 struct cal_target_power_ht *powInfo,
242 u16 numChannels,
243 struct cal_target_power_ht *pNewPower,
244 u16 numRates, bool isHt40Target)
245{ 181{
246 struct chan_centers centers; 182 struct chan_centers centers;
247 u16 clo, chi; 183 u16 clo, chi;
@@ -291,9 +227,8 @@ static void ath9k_hw_get_target_powers(struct ath_hw *ah,
291 } 227 }
292} 228}
293 229
294static u16 ath9k_hw_get_max_edge_power(u16 freq, 230u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
295 struct cal_ctl_edges *pRdEdgesPower, 231 bool is2GHz, int num_band_edges)
296 bool is2GHz, int num_band_edges)
297{ 232{
298 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 233 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
299 int i; 234 int i;
@@ -319,3653 +254,6 @@ static u16 ath9k_hw_get_max_edge_power(u16 freq,
319 return twiceMaxEdgePower; 254 return twiceMaxEdgePower;
320} 255}
321 256
322/****************************************/
323/* EEPROM Operations for 4K sized cards */
324/****************************************/
325
326static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
327{
328 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
329}
330
331static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
332{
333 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
334}
335
336static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
337{
338#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
339 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
340 int addr, eep_start_loc = 0;
341
342 eep_start_loc = 64;
343
344 if (!ath9k_hw_use_flash(ah)) {
345 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
346 "Reading from EEPROM, not flash\n");
347 }
348
349 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
350 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
351 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
352 "Unable to read eeprom region \n");
353 return false;
354 }
355 eep_data++;
356 }
357
358 return true;
359#undef SIZE_EEPROM_4K
360}
361
362static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
363{
364#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
365 struct ar5416_eeprom_4k *eep =
366 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
367 u16 *eepdata, temp, magic, magic2;
368 u32 sum = 0, el;
369 bool need_swap = false;
370 int i, addr;
371
372
373 if (!ath9k_hw_use_flash(ah)) {
374 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
375 &magic)) {
376 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
377 "Reading Magic # failed\n");
378 return false;
379 }
380
381 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
382 "Read Magic = 0x%04X\n", magic);
383
384 if (magic != AR5416_EEPROM_MAGIC) {
385 magic2 = swab16(magic);
386
387 if (magic2 == AR5416_EEPROM_MAGIC) {
388 need_swap = true;
389 eepdata = (u16 *) (&ah->eeprom);
390
391 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
392 temp = swab16(*eepdata);
393 *eepdata = temp;
394 eepdata++;
395 }
396 } else {
397 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
398 "Invalid EEPROM Magic. "
399 "endianness mismatch.\n");
400 return -EINVAL;
401 }
402 }
403 }
404
405 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
406 need_swap ? "True" : "False");
407
408 if (need_swap)
409 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
410 else
411 el = ah->eeprom.map4k.baseEepHeader.length;
412
413 if (el > sizeof(struct ar5416_eeprom_4k))
414 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
415 else
416 el = el / sizeof(u16);
417
418 eepdata = (u16 *)(&ah->eeprom);
419
420 for (i = 0; i < el; i++)
421 sum ^= *eepdata++;
422
423 if (need_swap) {
424 u32 integer;
425 u16 word;
426
427 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
428 "EEPROM Endianness is not native.. Changing\n");
429
430 word = swab16(eep->baseEepHeader.length);
431 eep->baseEepHeader.length = word;
432
433 word = swab16(eep->baseEepHeader.checksum);
434 eep->baseEepHeader.checksum = word;
435
436 word = swab16(eep->baseEepHeader.version);
437 eep->baseEepHeader.version = word;
438
439 word = swab16(eep->baseEepHeader.regDmn[0]);
440 eep->baseEepHeader.regDmn[0] = word;
441
442 word = swab16(eep->baseEepHeader.regDmn[1]);
443 eep->baseEepHeader.regDmn[1] = word;
444
445 word = swab16(eep->baseEepHeader.rfSilent);
446 eep->baseEepHeader.rfSilent = word;
447
448 word = swab16(eep->baseEepHeader.blueToothOptions);
449 eep->baseEepHeader.blueToothOptions = word;
450
451 word = swab16(eep->baseEepHeader.deviceCap);
452 eep->baseEepHeader.deviceCap = word;
453
454 integer = swab32(eep->modalHeader.antCtrlCommon);
455 eep->modalHeader.antCtrlCommon = integer;
456
457 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
458 integer = swab32(eep->modalHeader.antCtrlChain[i]);
459 eep->modalHeader.antCtrlChain[i] = integer;
460 }
461
462 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
463 word = swab16(eep->modalHeader.spurChans[i].spurChan);
464 eep->modalHeader.spurChans[i].spurChan = word;
465 }
466 }
467
468 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
469 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
470 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
471 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
472 sum, ah->eep_ops->get_eeprom_ver(ah));
473 return -EINVAL;
474 }
475
476 return 0;
477#undef EEPROM_4K_SIZE
478}
479
480static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
481 enum eeprom_param param)
482{
483 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
484 struct modal_eep_4k_header *pModal = &eep->modalHeader;
485 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
486
487 switch (param) {
488 case EEP_NFTHRESH_2:
489 return pModal->noiseFloorThreshCh[0];
490 case AR_EEPROM_MAC(0):
491 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
492 case AR_EEPROM_MAC(1):
493 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
494 case AR_EEPROM_MAC(2):
495 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
496 case EEP_REG_0:
497 return pBase->regDmn[0];
498 case EEP_REG_1:
499 return pBase->regDmn[1];
500 case EEP_OP_CAP:
501 return pBase->deviceCap;
502 case EEP_OP_MODE:
503 return pBase->opCapFlags;
504 case EEP_RF_SILENT:
505 return pBase->rfSilent;
506 case EEP_OB_2:
507 return pModal->ob_01;
508 case EEP_DB_2:
509 return pModal->db1_01;
510 case EEP_MINOR_REV:
511 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
512 case EEP_TX_MASK:
513 return pBase->txMask;
514 case EEP_RX_MASK:
515 return pBase->rxMask;
516 case EEP_FRAC_N_5G:
517 return 0;
518 default:
519 return 0;
520 }
521}
522
523static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
524 struct ath9k_channel *chan,
525 struct cal_data_per_freq_4k *pRawDataSet,
526 u8 *bChans, u16 availPiers,
527 u16 tPdGainOverlap, int16_t *pMinCalPower,
528 u16 *pPdGainBoundaries, u8 *pPDADCValues,
529 u16 numXpdGains)
530{
531#define TMP_VAL_VPD_TABLE \
532 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
533 int i, j, k;
534 int16_t ss;
535 u16 idxL = 0, idxR = 0, numPiers;
536 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
537 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
538 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
539 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
540 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
541 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
542
543 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
544 u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
545 u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
546 int16_t vpdStep;
547 int16_t tmpVal;
548 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
549 bool match;
550 int16_t minDelta = 0;
551 struct chan_centers centers;
552#define PD_GAIN_BOUNDARY_DEFAULT 58;
553
554 ath9k_hw_get_channel_centers(ah, chan, &centers);
555
556 for (numPiers = 0; numPiers < availPiers; numPiers++) {
557 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
558 break;
559 }
560
561 match = ath9k_hw_get_lower_upper_index(
562 (u8)FREQ2FBIN(centers.synth_center,
563 IS_CHAN_2GHZ(chan)), bChans, numPiers,
564 &idxL, &idxR);
565
566 if (match) {
567 for (i = 0; i < numXpdGains; i++) {
568 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
569 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
570 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
571 pRawDataSet[idxL].pwrPdg[i],
572 pRawDataSet[idxL].vpdPdg[i],
573 AR5416_EEP4K_PD_GAIN_ICEPTS,
574 vpdTableI[i]);
575 }
576 } else {
577 for (i = 0; i < numXpdGains; i++) {
578 pVpdL = pRawDataSet[idxL].vpdPdg[i];
579 pPwrL = pRawDataSet[idxL].pwrPdg[i];
580 pVpdR = pRawDataSet[idxR].vpdPdg[i];
581 pPwrR = pRawDataSet[idxR].pwrPdg[i];
582
583 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
584
585 maxPwrT4[i] =
586 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
587 pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
588
589
590 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
591 pPwrL, pVpdL,
592 AR5416_EEP4K_PD_GAIN_ICEPTS,
593 vpdTableL[i]);
594 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
595 pPwrR, pVpdR,
596 AR5416_EEP4K_PD_GAIN_ICEPTS,
597 vpdTableR[i]);
598
599 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
600 vpdTableI[i][j] =
601 (u8)(ath9k_hw_interpolate((u16)
602 FREQ2FBIN(centers.
603 synth_center,
604 IS_CHAN_2GHZ
605 (chan)),
606 bChans[idxL], bChans[idxR],
607 vpdTableL[i][j], vpdTableR[i][j]));
608 }
609 }
610 }
611
612 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
613
614 k = 0;
615
616 for (i = 0; i < numXpdGains; i++) {
617 if (i == (numXpdGains - 1))
618 pPdGainBoundaries[i] =
619 (u16)(maxPwrT4[i] / 2);
620 else
621 pPdGainBoundaries[i] =
622 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
623
624 pPdGainBoundaries[i] =
625 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
626
627 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
628 minDelta = pPdGainBoundaries[0] - 23;
629 pPdGainBoundaries[0] = 23;
630 } else {
631 minDelta = 0;
632 }
633
634 if (i == 0) {
635 if (AR_SREV_9280_10_OR_LATER(ah))
636 ss = (int16_t)(0 - (minPwrT4[i] / 2));
637 else
638 ss = 0;
639 } else {
640 ss = (int16_t)((pPdGainBoundaries[i - 1] -
641 (minPwrT4[i] / 2)) -
642 tPdGainOverlap + 1 + minDelta);
643 }
644 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
645 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
646
647 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
648 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
649 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
650 ss++;
651 }
652
653 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
654 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
655 (minPwrT4[i] / 2));
656 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
657 tgtIndex : sizeCurrVpdTable;
658
659 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
660 pPDADCValues[k++] = vpdTableI[i][ss++];
661
662 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
663 vpdTableI[i][sizeCurrVpdTable - 2]);
664 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
665
666 if (tgtIndex >= maxIndex) {
667 while ((ss <= tgtIndex) &&
668 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
669 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
670 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
671 255 : tmpVal);
672 ss++;
673 }
674 }
675 }
676
677 while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
678 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
679 i++;
680 }
681
682 while (k < AR5416_NUM_PDADC_VALUES) {
683 pPDADCValues[k] = pPDADCValues[k - 1];
684 k++;
685 }
686
687 return;
688#undef TMP_VAL_VPD_TABLE
689}
690
691static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
692 struct ath9k_channel *chan,
693 int16_t *pTxPowerIndexOffset)
694{
695 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
696 struct cal_data_per_freq_4k *pRawDataset;
697 u8 *pCalBChans = NULL;
698 u16 pdGainOverlap_t2;
699 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
700 u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
701 u16 numPiers, i, j;
702 int16_t tMinCalPower;
703 u16 numXpdGain, xpdMask;
704 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
705 u32 reg32, regOffset, regChainOffset;
706
707 xpdMask = pEepData->modalHeader.xpdGain;
708
709 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
710 AR5416_EEP_MINOR_VER_2) {
711 pdGainOverlap_t2 =
712 pEepData->modalHeader.pdGainOverlap;
713 } else {
714 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
715 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
716 }
717
718 pCalBChans = pEepData->calFreqPier2G;
719 numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
720
721 numXpdGain = 0;
722
723 for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
724 if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
725 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
726 break;
727 xpdGainValues[numXpdGain] =
728 (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
729 numXpdGain++;
730 }
731 }
732
733 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
734 (numXpdGain - 1) & 0x3);
735 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
736 xpdGainValues[0]);
737 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
738 xpdGainValues[1]);
739 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
740
741 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
742 if (AR_SREV_5416_20_OR_LATER(ah) &&
743 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
744 (i != 0)) {
745 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
746 } else
747 regChainOffset = i * 0x1000;
748
749 if (pEepData->baseEepHeader.txMask & (1 << i)) {
750 pRawDataset = pEepData->calPierData2G[i];
751
752 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
753 pRawDataset, pCalBChans,
754 numPiers, pdGainOverlap_t2,
755 &tMinCalPower, gainBoundaries,
756 pdadcValues, numXpdGain);
757
758 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
759 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
760 SM(pdGainOverlap_t2,
761 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
762 | SM(gainBoundaries[0],
763 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
764 | SM(gainBoundaries[1],
765 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
766 | SM(gainBoundaries[2],
767 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
768 | SM(gainBoundaries[3],
769 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
770 }
771
772 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
773 for (j = 0; j < 32; j++) {
774 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
775 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
776 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
777 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
778 REG_WRITE(ah, regOffset, reg32);
779
780 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
781 "PDADC (%d,%4x): %4.4x %8.8x\n",
782 i, regChainOffset, regOffset,
783 reg32);
784 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
785 "PDADC: Chain %d | "
786 "PDADC %3d Value %3d | "
787 "PDADC %3d Value %3d | "
788 "PDADC %3d Value %3d | "
789 "PDADC %3d Value %3d |\n",
790 i, 4 * j, pdadcValues[4 * j],
791 4 * j + 1, pdadcValues[4 * j + 1],
792 4 * j + 2, pdadcValues[4 * j + 2],
793 4 * j + 3,
794 pdadcValues[4 * j + 3]);
795
796 regOffset += 4;
797 }
798 }
799 }
800
801 *pTxPowerIndexOffset = 0;
802}
803
804static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
805 struct ath9k_channel *chan,
806 int16_t *ratesArray,
807 u16 cfgCtl,
808 u16 AntennaReduction,
809 u16 twiceMaxRegulatoryPower,
810 u16 powerLimit)
811{
812 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
813 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
814 static const u16 tpScaleReductionTable[5] =
815 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
816
817 int i;
818 int16_t twiceLargestAntenna;
819 struct cal_ctl_data_4k *rep;
820 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
821 0, { 0, 0, 0, 0}
822 };
823 struct cal_target_power_leg targetPowerOfdmExt = {
824 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
825 0, { 0, 0, 0, 0 }
826 };
827 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
828 0, {0, 0, 0, 0}
829 };
830 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
831 u16 ctlModesFor11g[] =
832 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
833 CTL_2GHT40
834 };
835 u16 numCtlModes, *pCtlMode, ctlMode, freq;
836 struct chan_centers centers;
837 int tx_chainmask;
838 u16 twiceMinEdgePower;
839
840 tx_chainmask = ah->txchainmask;
841
842 ath9k_hw_get_channel_centers(ah, chan, &centers);
843
844 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
845
846 twiceLargestAntenna = (int16_t)min(AntennaReduction -
847 twiceLargestAntenna, 0);
848
849 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
850
851 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
852 maxRegAllowedPower -=
853 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
854 }
855
856 scaledPower = min(powerLimit, maxRegAllowedPower);
857 scaledPower = max((u16)0, scaledPower);
858
859 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
860 pCtlMode = ctlModesFor11g;
861
862 ath9k_hw_get_legacy_target_powers(ah, chan,
863 pEepData->calTargetPowerCck,
864 AR5416_NUM_2G_CCK_TARGET_POWERS,
865 &targetPowerCck, 4, false);
866 ath9k_hw_get_legacy_target_powers(ah, chan,
867 pEepData->calTargetPower2G,
868 AR5416_NUM_2G_20_TARGET_POWERS,
869 &targetPowerOfdm, 4, false);
870 ath9k_hw_get_target_powers(ah, chan,
871 pEepData->calTargetPower2GHT20,
872 AR5416_NUM_2G_20_TARGET_POWERS,
873 &targetPowerHt20, 8, false);
874
875 if (IS_CHAN_HT40(chan)) {
876 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
877 ath9k_hw_get_target_powers(ah, chan,
878 pEepData->calTargetPower2GHT40,
879 AR5416_NUM_2G_40_TARGET_POWERS,
880 &targetPowerHt40, 8, true);
881 ath9k_hw_get_legacy_target_powers(ah, chan,
882 pEepData->calTargetPowerCck,
883 AR5416_NUM_2G_CCK_TARGET_POWERS,
884 &targetPowerCckExt, 4, true);
885 ath9k_hw_get_legacy_target_powers(ah, chan,
886 pEepData->calTargetPower2G,
887 AR5416_NUM_2G_20_TARGET_POWERS,
888 &targetPowerOfdmExt, 4, true);
889 }
890
891 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
892 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
893 (pCtlMode[ctlMode] == CTL_2GHT40);
894 if (isHt40CtlMode)
895 freq = centers.synth_center;
896 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
897 freq = centers.ext_center;
898 else
899 freq = centers.ctl_center;
900
901 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
902 ah->eep_ops->get_eeprom_rev(ah) <= 2)
903 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
904
905 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
906 pEepData->ctlIndex[i]; i++) {
907
908 if ((((cfgCtl & ~CTL_MODE_M) |
909 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
910 pEepData->ctlIndex[i]) ||
911 (((cfgCtl & ~CTL_MODE_M) |
912 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
913 ((pEepData->ctlIndex[i] & CTL_MODE_M) |
914 SD_NO_CTL))) {
915 rep = &(pEepData->ctlData[i]);
916
917 twiceMinEdgePower =
918 ath9k_hw_get_max_edge_power(freq,
919 rep->ctlEdges[ar5416_get_ntxchains
920 (tx_chainmask) - 1],
921 IS_CHAN_2GHZ(chan),
922 AR5416_EEP4K_NUM_BAND_EDGES);
923
924 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
925 twiceMaxEdgePower =
926 min(twiceMaxEdgePower,
927 twiceMinEdgePower);
928 } else {
929 twiceMaxEdgePower = twiceMinEdgePower;
930 break;
931 }
932 }
933 }
934
935 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
936
937 switch (pCtlMode[ctlMode]) {
938 case CTL_11B:
939 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
940 i++) {
941 targetPowerCck.tPow2x[i] =
942 min((u16)targetPowerCck.tPow2x[i],
943 minCtlPower);
944 }
945 break;
946 case CTL_11G:
947 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
948 i++) {
949 targetPowerOfdm.tPow2x[i] =
950 min((u16)targetPowerOfdm.tPow2x[i],
951 minCtlPower);
952 }
953 break;
954 case CTL_2GHT20:
955 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
956 i++) {
957 targetPowerHt20.tPow2x[i] =
958 min((u16)targetPowerHt20.tPow2x[i],
959 minCtlPower);
960 }
961 break;
962 case CTL_11B_EXT:
963 targetPowerCckExt.tPow2x[0] = min((u16)
964 targetPowerCckExt.tPow2x[0],
965 minCtlPower);
966 break;
967 case CTL_11G_EXT:
968 targetPowerOfdmExt.tPow2x[0] = min((u16)
969 targetPowerOfdmExt.tPow2x[0],
970 minCtlPower);
971 break;
972 case CTL_2GHT40:
973 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
974 i++) {
975 targetPowerHt40.tPow2x[i] =
976 min((u16)targetPowerHt40.tPow2x[i],
977 minCtlPower);
978 }
979 break;
980 default:
981 break;
982 }
983 }
984
985 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
986 ratesArray[rate18mb] = ratesArray[rate24mb] =
987 targetPowerOfdm.tPow2x[0];
988 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
989 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
990 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
991 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
992
993 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
994 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
995
996 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
997 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
998 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
999 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
1000
1001 if (IS_CHAN_HT40(chan)) {
1002 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1003 ratesArray[rateHt40_0 + i] =
1004 targetPowerHt40.tPow2x[i];
1005 }
1006 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1007 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1008 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1009 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1010 }
1011}
1012
1013static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1014 struct ath9k_channel *chan,
1015 u16 cfgCtl,
1016 u8 twiceAntennaReduction,
1017 u8 twiceMaxRegulatoryPower,
1018 u8 powerLimit)
1019{
1020 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
1021 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
1022 int16_t ratesArray[Ar5416RateSize];
1023 int16_t txPowerIndexOffset = 0;
1024 u8 ht40PowerIncForPdadc = 2;
1025 int i;
1026
1027 memset(ratesArray, 0, sizeof(ratesArray));
1028
1029 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1030 AR5416_EEP_MINOR_VER_2) {
1031 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1032 }
1033
1034 ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1035 &ratesArray[0], cfgCtl,
1036 twiceAntennaReduction,
1037 twiceMaxRegulatoryPower,
1038 powerLimit);
1039
1040 ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
1041
1042 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1043 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1044 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1045 ratesArray[i] = AR5416_MAX_RATE_POWER;
1046 }
1047
1048 if (AR_SREV_9280_10_OR_LATER(ah)) {
1049 for (i = 0; i < Ar5416RateSize; i++)
1050 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1051 }
1052
1053 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1054 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1055 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1056 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1057 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1058 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1059 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1060 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1061 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1062 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1063
1064 if (IS_CHAN_2GHZ(chan)) {
1065 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1066 ATH9K_POW_SM(ratesArray[rate2s], 24)
1067 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1068 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1069 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1070 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1071 ATH9K_POW_SM(ratesArray[rate11s], 24)
1072 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1073 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1074 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1075 }
1076
1077 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1078 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1079 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1080 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1081 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1082 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1083 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1084 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1085 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1086 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1087
1088 if (IS_CHAN_HT40(chan)) {
1089 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1090 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1091 ht40PowerIncForPdadc, 24)
1092 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1093 ht40PowerIncForPdadc, 16)
1094 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1095 ht40PowerIncForPdadc, 8)
1096 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1097 ht40PowerIncForPdadc, 0));
1098 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1099 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1100 ht40PowerIncForPdadc, 24)
1101 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1102 ht40PowerIncForPdadc, 16)
1103 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1104 ht40PowerIncForPdadc, 8)
1105 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1106 ht40PowerIncForPdadc, 0));
1107
1108 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1109 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1110 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1111 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1112 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1113 }
1114
1115 i = rate6mb;
1116
1117 if (IS_CHAN_HT40(chan))
1118 i = rateHt40_0;
1119 else if (IS_CHAN_HT20(chan))
1120 i = rateHt20_0;
1121
1122 if (AR_SREV_9280_10_OR_LATER(ah))
1123 ah->regulatory.max_power_level =
1124 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1125 else
1126 ah->regulatory.max_power_level = ratesArray[i];
1127
1128}
1129
1130static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1131 struct ath9k_channel *chan)
1132{
1133 struct modal_eep_4k_header *pModal;
1134 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1135 u8 biaslevel;
1136
1137 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1138 return;
1139
1140 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1141 return;
1142
1143 pModal = &eep->modalHeader;
1144
1145 if (pModal->xpaBiasLvl != 0xff) {
1146 biaslevel = pModal->xpaBiasLvl;
1147 INI_RA(&ah->iniAddac, 7, 1) =
1148 (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
1149 }
1150}
1151
1152static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
1153 struct modal_eep_4k_header *pModal,
1154 struct ar5416_eeprom_4k *eep,
1155 u8 txRxAttenLocal, int regChainOffset)
1156{
1157 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1158 pModal->antCtrlChain[0]);
1159
1160 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1161 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1162 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1163 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1164 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1165 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1166
1167 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1168 AR5416_EEP_MINOR_VER_3) {
1169 txRxAttenLocal = pModal->txRxAttenCh[0];
1170
1171 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1172 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
1173 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1174 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
1175 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1176 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1177 pModal->xatten2Margin[0]);
1178 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1179 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
1180
1181 /* Set the block 1 value to block 0 value */
1182 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
1183 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1184 pModal->bswMargin[0]);
1185 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
1186 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
1187 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
1188 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1189 pModal->xatten2Margin[0]);
1190 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
1191 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1192 pModal->xatten2Db[0]);
1193 }
1194
1195 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1196 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1197 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1198 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
1199
1200 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
1201 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1202 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
1203 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
1204
1205 if (AR_SREV_9285_11(ah))
1206 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
1207}
1208
1209/*
1210 * Read EEPROM header info and program the device for correct operation
1211 * given the channel value.
1212 */
1213static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1214 struct ath9k_channel *chan)
1215{
1216 struct modal_eep_4k_header *pModal;
1217 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1218 u8 txRxAttenLocal;
1219 u8 ob[5], db1[5], db2[5];
1220 u8 ant_div_control1, ant_div_control2;
1221 u32 regVal;
1222
1223 pModal = &eep->modalHeader;
1224 txRxAttenLocal = 23;
1225
1226 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1227 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1228
1229 /* Single chain for 4K EEPROM*/
1230 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal, 0);
1231
1232 /* Initialize Ant Diversity settings from EEPROM */
1233 if (pModal->version >= 3) {
1234 ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf);
1235 ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf);
1236 regVal = REG_READ(ah, 0x99ac);
1237 regVal &= (~(0x7f000000));
1238 regVal |= ((ant_div_control1 & 0x1) << 24);
1239 regVal |= (((ant_div_control1 >> 1) & 0x1) << 29);
1240 regVal |= (((ant_div_control1 >> 2) & 0x1) << 30);
1241 regVal |= ((ant_div_control2 & 0x3) << 25);
1242 regVal |= (((ant_div_control2 >> 2) & 0x3) << 27);
1243 REG_WRITE(ah, 0x99ac, regVal);
1244 regVal = REG_READ(ah, 0x99ac);
1245 regVal = REG_READ(ah, 0xa208);
1246 regVal &= (~(0x1 << 13));
1247 regVal |= (((ant_div_control1 >> 3) & 0x1) << 13);
1248 REG_WRITE(ah, 0xa208, regVal);
1249 regVal = REG_READ(ah, 0xa208);
1250 }
1251
1252 if (pModal->version >= 2) {
1253 ob[0] = (pModal->ob_01 & 0xf);
1254 ob[1] = (pModal->ob_01 >> 4) & 0xf;
1255 ob[2] = (pModal->ob_234 & 0xf);
1256 ob[3] = ((pModal->ob_234 >> 4) & 0xf);
1257 ob[4] = ((pModal->ob_234 >> 8) & 0xf);
1258
1259 db1[0] = (pModal->db1_01 & 0xf);
1260 db1[1] = ((pModal->db1_01 >> 4) & 0xf);
1261 db1[2] = (pModal->db1_234 & 0xf);
1262 db1[3] = ((pModal->db1_234 >> 4) & 0xf);
1263 db1[4] = ((pModal->db1_234 >> 8) & 0xf);
1264
1265 db2[0] = (pModal->db2_01 & 0xf);
1266 db2[1] = ((pModal->db2_01 >> 4) & 0xf);
1267 db2[2] = (pModal->db2_234 & 0xf);
1268 db2[3] = ((pModal->db2_234 >> 4) & 0xf);
1269 db2[4] = ((pModal->db2_234 >> 8) & 0xf);
1270
1271 } else if (pModal->version == 1) {
1272 ob[0] = (pModal->ob_01 & 0xf);
1273 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf;
1274 db1[0] = (pModal->db1_01 & 0xf);
1275 db1[1] = db1[2] = db1[3] =
1276 db1[4] = ((pModal->db1_01 >> 4) & 0xf);
1277 db2[0] = (pModal->db2_01 & 0xf);
1278 db2[1] = db2[2] = db2[3] =
1279 db2[4] = ((pModal->db2_01 >> 4) & 0xf);
1280 } else {
1281 int i;
1282 for (i = 0; i < 5; i++) {
1283 ob[i] = pModal->ob_01;
1284 db1[i] = pModal->db1_01;
1285 db2[i] = pModal->db1_01;
1286 }
1287 }
1288
1289 if (AR_SREV_9271(ah)) {
1290 ath9k_hw_analog_shift_rmw(ah,
1291 AR9285_AN_RF2G3,
1292 AR9271_AN_RF2G3_OB_cck,
1293 AR9271_AN_RF2G3_OB_cck_S,
1294 ob[0]);
1295 ath9k_hw_analog_shift_rmw(ah,
1296 AR9285_AN_RF2G3,
1297 AR9271_AN_RF2G3_OB_psk,
1298 AR9271_AN_RF2G3_OB_psk_S,
1299 ob[1]);
1300 ath9k_hw_analog_shift_rmw(ah,
1301 AR9285_AN_RF2G3,
1302 AR9271_AN_RF2G3_OB_qam,
1303 AR9271_AN_RF2G3_OB_qam_S,
1304 ob[2]);
1305 ath9k_hw_analog_shift_rmw(ah,
1306 AR9285_AN_RF2G3,
1307 AR9271_AN_RF2G3_DB_1,
1308 AR9271_AN_RF2G3_DB_1_S,
1309 db1[0]);
1310 ath9k_hw_analog_shift_rmw(ah,
1311 AR9285_AN_RF2G4,
1312 AR9271_AN_RF2G4_DB_2,
1313 AR9271_AN_RF2G4_DB_2_S,
1314 db2[0]);
1315 } else {
1316 ath9k_hw_analog_shift_rmw(ah,
1317 AR9285_AN_RF2G3,
1318 AR9285_AN_RF2G3_OB_0,
1319 AR9285_AN_RF2G3_OB_0_S,
1320 ob[0]);
1321 ath9k_hw_analog_shift_rmw(ah,
1322 AR9285_AN_RF2G3,
1323 AR9285_AN_RF2G3_OB_1,
1324 AR9285_AN_RF2G3_OB_1_S,
1325 ob[1]);
1326 ath9k_hw_analog_shift_rmw(ah,
1327 AR9285_AN_RF2G3,
1328 AR9285_AN_RF2G3_OB_2,
1329 AR9285_AN_RF2G3_OB_2_S,
1330 ob[2]);
1331 ath9k_hw_analog_shift_rmw(ah,
1332 AR9285_AN_RF2G3,
1333 AR9285_AN_RF2G3_OB_3,
1334 AR9285_AN_RF2G3_OB_3_S,
1335 ob[3]);
1336 ath9k_hw_analog_shift_rmw(ah,
1337 AR9285_AN_RF2G3,
1338 AR9285_AN_RF2G3_OB_4,
1339 AR9285_AN_RF2G3_OB_4_S,
1340 ob[4]);
1341
1342 ath9k_hw_analog_shift_rmw(ah,
1343 AR9285_AN_RF2G3,
1344 AR9285_AN_RF2G3_DB1_0,
1345 AR9285_AN_RF2G3_DB1_0_S,
1346 db1[0]);
1347 ath9k_hw_analog_shift_rmw(ah,
1348 AR9285_AN_RF2G3,
1349 AR9285_AN_RF2G3_DB1_1,
1350 AR9285_AN_RF2G3_DB1_1_S,
1351 db1[1]);
1352 ath9k_hw_analog_shift_rmw(ah,
1353 AR9285_AN_RF2G3,
1354 AR9285_AN_RF2G3_DB1_2,
1355 AR9285_AN_RF2G3_DB1_2_S,
1356 db1[2]);
1357 ath9k_hw_analog_shift_rmw(ah,
1358 AR9285_AN_RF2G4,
1359 AR9285_AN_RF2G4_DB1_3,
1360 AR9285_AN_RF2G4_DB1_3_S,
1361 db1[3]);
1362 ath9k_hw_analog_shift_rmw(ah,
1363 AR9285_AN_RF2G4,
1364 AR9285_AN_RF2G4_DB1_4,
1365 AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1366
1367 ath9k_hw_analog_shift_rmw(ah,
1368 AR9285_AN_RF2G4,
1369 AR9285_AN_RF2G4_DB2_0,
1370 AR9285_AN_RF2G4_DB2_0_S,
1371 db2[0]);
1372 ath9k_hw_analog_shift_rmw(ah,
1373 AR9285_AN_RF2G4,
1374 AR9285_AN_RF2G4_DB2_1,
1375 AR9285_AN_RF2G4_DB2_1_S,
1376 db2[1]);
1377 ath9k_hw_analog_shift_rmw(ah,
1378 AR9285_AN_RF2G4,
1379 AR9285_AN_RF2G4_DB2_2,
1380 AR9285_AN_RF2G4_DB2_2_S,
1381 db2[2]);
1382 ath9k_hw_analog_shift_rmw(ah,
1383 AR9285_AN_RF2G4,
1384 AR9285_AN_RF2G4_DB2_3,
1385 AR9285_AN_RF2G4_DB2_3_S,
1386 db2[3]);
1387 ath9k_hw_analog_shift_rmw(ah,
1388 AR9285_AN_RF2G4,
1389 AR9285_AN_RF2G4_DB2_4,
1390 AR9285_AN_RF2G4_DB2_4_S,
1391 db2[4]);
1392 }
1393
1394
1395 if (AR_SREV_9285_11(ah))
1396 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1397
1398 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1399 pModal->switchSettling);
1400 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1401 pModal->adcDesiredSize);
1402
1403 REG_WRITE(ah, AR_PHY_RF_CTL4,
1404 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1405 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1406 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
1407 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1408
1409 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1410 pModal->txEndToRxOn);
1411 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1412 pModal->thresh62);
1413 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1414 pModal->thresh62);
1415
1416 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1417 AR5416_EEP_MINOR_VER_2) {
1418 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1419 pModal->txFrameToDataStart);
1420 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1421 pModal->txFrameToPaOn);
1422 }
1423
1424 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1425 AR5416_EEP_MINOR_VER_3) {
1426 if (IS_CHAN_HT40(chan))
1427 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1428 AR_PHY_SETTLING_SWITCH,
1429 pModal->swSettleHt40);
1430 }
1431}
1432
1433static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1434 struct ath9k_channel *chan)
1435{
1436 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1437 struct modal_eep_4k_header *pModal = &eep->modalHeader;
1438
1439 return pModal->antCtrlCommon & 0xFFFF;
1440}
1441
1442static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1443 enum ieee80211_band freq_band)
1444{
1445 return 1;
1446}
1447
1448static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1449{
1450#define EEP_MAP4K_SPURCHAN \
1451 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1452
1453 u16 spur_val = AR_NO_SPUR;
1454
1455 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1456 "Getting spur idx %d is2Ghz. %d val %x\n",
1457 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1458
1459 switch (ah->config.spurmode) {
1460 case SPUR_DISABLE:
1461 break;
1462 case SPUR_ENABLE_IOCTL:
1463 spur_val = ah->config.spurchans[i][is2GHz];
1464 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1465 "Getting spur val from new loc. %d\n", spur_val);
1466 break;
1467 case SPUR_ENABLE_EEPROM:
1468 spur_val = EEP_MAP4K_SPURCHAN;
1469 break;
1470 }
1471
1472 return spur_val;
1473
1474#undef EEP_MAP4K_SPURCHAN
1475}
1476
1477static struct eeprom_ops eep_4k_ops = {
1478 .check_eeprom = ath9k_hw_4k_check_eeprom,
1479 .get_eeprom = ath9k_hw_4k_get_eeprom,
1480 .fill_eeprom = ath9k_hw_4k_fill_eeprom,
1481 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
1482 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
1483 .get_num_ant_config = ath9k_hw_4k_get_num_ant_config,
1484 .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1485 .set_board_values = ath9k_hw_4k_set_board_values,
1486 .set_addac = ath9k_hw_4k_set_addac,
1487 .set_txpower = ath9k_hw_4k_set_txpower,
1488 .get_spur_channel = ath9k_hw_4k_get_spur_channel
1489};
1490
1491/************************************************/
1492/* EEPROM Operations for non-4K (Default) cards */
1493/************************************************/
1494
1495static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
1496{
1497 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
1498}
1499
1500static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
1501{
1502 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
1503}
1504
1505static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
1506{
1507#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
1508 u16 *eep_data = (u16 *)&ah->eeprom.def;
1509 int addr, ar5416_eep_start_loc = 0x100;
1510
1511 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
1512 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
1513 eep_data)) {
1514 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1515 "Unable to read eeprom region\n");
1516 return false;
1517 }
1518 eep_data++;
1519 }
1520 return true;
1521#undef SIZE_EEPROM_DEF
1522}
1523
1524static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1525{
1526 struct ar5416_eeprom_def *eep =
1527 (struct ar5416_eeprom_def *) &ah->eeprom.def;
1528 u16 *eepdata, temp, magic, magic2;
1529 u32 sum = 0, el;
1530 bool need_swap = false;
1531 int i, addr, size;
1532
1533 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
1534 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Reading Magic # failed\n");
1535 return false;
1536 }
1537
1538 if (!ath9k_hw_use_flash(ah)) {
1539 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1540 "Read Magic = 0x%04X\n", magic);
1541
1542 if (magic != AR5416_EEPROM_MAGIC) {
1543 magic2 = swab16(magic);
1544
1545 if (magic2 == AR5416_EEPROM_MAGIC) {
1546 size = sizeof(struct ar5416_eeprom_def);
1547 need_swap = true;
1548 eepdata = (u16 *) (&ah->eeprom);
1549
1550 for (addr = 0; addr < size / sizeof(u16); addr++) {
1551 temp = swab16(*eepdata);
1552 *eepdata = temp;
1553 eepdata++;
1554 }
1555 } else {
1556 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1557 "Invalid EEPROM Magic. "
1558 "Endianness mismatch.\n");
1559 return -EINVAL;
1560 }
1561 }
1562 }
1563
1564 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
1565 need_swap ? "True" : "False");
1566
1567 if (need_swap)
1568 el = swab16(ah->eeprom.def.baseEepHeader.length);
1569 else
1570 el = ah->eeprom.def.baseEepHeader.length;
1571
1572 if (el > sizeof(struct ar5416_eeprom_def))
1573 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
1574 else
1575 el = el / sizeof(u16);
1576
1577 eepdata = (u16 *)(&ah->eeprom);
1578
1579 for (i = 0; i < el; i++)
1580 sum ^= *eepdata++;
1581
1582 if (need_swap) {
1583 u32 integer, j;
1584 u16 word;
1585
1586 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1587 "EEPROM Endianness is not native.. Changing.\n");
1588
1589 word = swab16(eep->baseEepHeader.length);
1590 eep->baseEepHeader.length = word;
1591
1592 word = swab16(eep->baseEepHeader.checksum);
1593 eep->baseEepHeader.checksum = word;
1594
1595 word = swab16(eep->baseEepHeader.version);
1596 eep->baseEepHeader.version = word;
1597
1598 word = swab16(eep->baseEepHeader.regDmn[0]);
1599 eep->baseEepHeader.regDmn[0] = word;
1600
1601 word = swab16(eep->baseEepHeader.regDmn[1]);
1602 eep->baseEepHeader.regDmn[1] = word;
1603
1604 word = swab16(eep->baseEepHeader.rfSilent);
1605 eep->baseEepHeader.rfSilent = word;
1606
1607 word = swab16(eep->baseEepHeader.blueToothOptions);
1608 eep->baseEepHeader.blueToothOptions = word;
1609
1610 word = swab16(eep->baseEepHeader.deviceCap);
1611 eep->baseEepHeader.deviceCap = word;
1612
1613 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
1614 struct modal_eep_header *pModal =
1615 &eep->modalHeader[j];
1616 integer = swab32(pModal->antCtrlCommon);
1617 pModal->antCtrlCommon = integer;
1618
1619 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1620 integer = swab32(pModal->antCtrlChain[i]);
1621 pModal->antCtrlChain[i] = integer;
1622 }
1623
1624 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
1625 word = swab16(pModal->spurChans[i].spurChan);
1626 pModal->spurChans[i].spurChan = word;
1627 }
1628 }
1629 }
1630
1631 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
1632 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
1633 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1634 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
1635 sum, ah->eep_ops->get_eeprom_ver(ah));
1636 return -EINVAL;
1637 }
1638
1639 return 0;
1640}
1641
1642static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
1643 enum eeprom_param param)
1644{
1645 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1646 struct modal_eep_header *pModal = eep->modalHeader;
1647 struct base_eep_header *pBase = &eep->baseEepHeader;
1648
1649 switch (param) {
1650 case EEP_NFTHRESH_5:
1651 return pModal[0].noiseFloorThreshCh[0];
1652 case EEP_NFTHRESH_2:
1653 return pModal[1].noiseFloorThreshCh[0];
1654 case AR_EEPROM_MAC(0):
1655 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1656 case AR_EEPROM_MAC(1):
1657 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1658 case AR_EEPROM_MAC(2):
1659 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1660 case EEP_REG_0:
1661 return pBase->regDmn[0];
1662 case EEP_REG_1:
1663 return pBase->regDmn[1];
1664 case EEP_OP_CAP:
1665 return pBase->deviceCap;
1666 case EEP_OP_MODE:
1667 return pBase->opCapFlags;
1668 case EEP_RF_SILENT:
1669 return pBase->rfSilent;
1670 case EEP_OB_5:
1671 return pModal[0].ob;
1672 case EEP_DB_5:
1673 return pModal[0].db;
1674 case EEP_OB_2:
1675 return pModal[1].ob;
1676 case EEP_DB_2:
1677 return pModal[1].db;
1678 case EEP_MINOR_REV:
1679 return AR5416_VER_MASK;
1680 case EEP_TX_MASK:
1681 return pBase->txMask;
1682 case EEP_RX_MASK:
1683 return pBase->rxMask;
1684 case EEP_RXGAIN_TYPE:
1685 return pBase->rxGainType;
1686 case EEP_TXGAIN_TYPE:
1687 return pBase->txGainType;
1688 case EEP_OL_PWRCTRL:
1689 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1690 return pBase->openLoopPwrCntl ? true : false;
1691 else
1692 return false;
1693 case EEP_RC_CHAIN_MASK:
1694 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1695 return pBase->rcChainMask;
1696 else
1697 return 0;
1698 case EEP_DAC_HPWR_5G:
1699 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
1700 return pBase->dacHiPwrMode_5G;
1701 else
1702 return 0;
1703 case EEP_FRAC_N_5G:
1704 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
1705 return pBase->frac_n_5g;
1706 else
1707 return 0;
1708 default:
1709 return 0;
1710 }
1711}
1712
1713static void ath9k_hw_def_set_gain(struct ath_hw *ah,
1714 struct modal_eep_header *pModal,
1715 struct ar5416_eeprom_def *eep,
1716 u8 txRxAttenLocal, int regChainOffset, int i)
1717{
1718 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1719 txRxAttenLocal = pModal->txRxAttenCh[i];
1720
1721 if (AR_SREV_9280_10_OR_LATER(ah)) {
1722 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1723 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1724 pModal->bswMargin[i]);
1725 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1726 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1727 pModal->bswAtten[i]);
1728 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1729 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1730 pModal->xatten2Margin[i]);
1731 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1732 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1733 pModal->xatten2Db[i]);
1734 } else {
1735 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1736 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1737 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
1738 | SM(pModal-> bswMargin[i],
1739 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1740 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1741 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1742 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
1743 | SM(pModal->bswAtten[i],
1744 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1745 }
1746 }
1747
1748 if (AR_SREV_9280_10_OR_LATER(ah)) {
1749 REG_RMW_FIELD(ah,
1750 AR_PHY_RXGAIN + regChainOffset,
1751 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1752 REG_RMW_FIELD(ah,
1753 AR_PHY_RXGAIN + regChainOffset,
1754 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
1755 } else {
1756 REG_WRITE(ah,
1757 AR_PHY_RXGAIN + regChainOffset,
1758 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
1759 ~AR_PHY_RXGAIN_TXRX_ATTEN)
1760 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
1761 REG_WRITE(ah,
1762 AR_PHY_GAIN_2GHZ + regChainOffset,
1763 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
1764 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1765 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1766 }
1767}
1768
1769static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
1770 struct ath9k_channel *chan)
1771{
1772 struct modal_eep_header *pModal;
1773 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1774 int i, regChainOffset;
1775 u8 txRxAttenLocal;
1776
1777 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1778 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
1779
1780 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1781 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1782
1783 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1784 if (AR_SREV_9280(ah)) {
1785 if (i >= 2)
1786 break;
1787 }
1788
1789 if (AR_SREV_5416_20_OR_LATER(ah) &&
1790 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
1791 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1792 else
1793 regChainOffset = i * 0x1000;
1794
1795 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1796 pModal->antCtrlChain[i]);
1797
1798 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1799 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1800 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1801 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1802 SM(pModal->iqCalICh[i],
1803 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1804 SM(pModal->iqCalQCh[i],
1805 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1806
1807 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
1808 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
1809 regChainOffset, i);
1810 }
1811
1812 if (AR_SREV_9280_10_OR_LATER(ah)) {
1813 if (IS_CHAN_2GHZ(chan)) {
1814 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1815 AR_AN_RF2G1_CH0_OB,
1816 AR_AN_RF2G1_CH0_OB_S,
1817 pModal->ob);
1818 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1819 AR_AN_RF2G1_CH0_DB,
1820 AR_AN_RF2G1_CH0_DB_S,
1821 pModal->db);
1822 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1823 AR_AN_RF2G1_CH1_OB,
1824 AR_AN_RF2G1_CH1_OB_S,
1825 pModal->ob_ch1);
1826 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1827 AR_AN_RF2G1_CH1_DB,
1828 AR_AN_RF2G1_CH1_DB_S,
1829 pModal->db_ch1);
1830 } else {
1831 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1832 AR_AN_RF5G1_CH0_OB5,
1833 AR_AN_RF5G1_CH0_OB5_S,
1834 pModal->ob);
1835 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1836 AR_AN_RF5G1_CH0_DB5,
1837 AR_AN_RF5G1_CH0_DB5_S,
1838 pModal->db);
1839 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1840 AR_AN_RF5G1_CH1_OB5,
1841 AR_AN_RF5G1_CH1_OB5_S,
1842 pModal->ob_ch1);
1843 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1844 AR_AN_RF5G1_CH1_DB5,
1845 AR_AN_RF5G1_CH1_DB5_S,
1846 pModal->db_ch1);
1847 }
1848 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1849 AR_AN_TOP2_XPABIAS_LVL,
1850 AR_AN_TOP2_XPABIAS_LVL_S,
1851 pModal->xpaBiasLvl);
1852 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1853 AR_AN_TOP2_LOCALBIAS,
1854 AR_AN_TOP2_LOCALBIAS_S,
1855 pModal->local_bias);
1856 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
1857 pModal->force_xpaon);
1858 }
1859
1860 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1861 pModal->switchSettling);
1862 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1863 pModal->adcDesiredSize);
1864
1865 if (!AR_SREV_9280_10_OR_LATER(ah))
1866 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1867 AR_PHY_DESIRED_SZ_PGA,
1868 pModal->pgaDesiredSize);
1869
1870 REG_WRITE(ah, AR_PHY_RF_CTL4,
1871 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1872 | SM(pModal->txEndToXpaOff,
1873 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1874 | SM(pModal->txFrameToXpaOn,
1875 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1876 | SM(pModal->txFrameToXpaOn,
1877 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1878
1879 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1880 pModal->txEndToRxOn);
1881
1882 if (AR_SREV_9280_10_OR_LATER(ah)) {
1883 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1884 pModal->thresh62);
1885 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
1886 AR_PHY_EXT_CCA0_THRESH62,
1887 pModal->thresh62);
1888 } else {
1889 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
1890 pModal->thresh62);
1891 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1892 AR_PHY_EXT_CCA_THRESH62,
1893 pModal->thresh62);
1894 }
1895
1896 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
1897 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1898 AR_PHY_TX_END_DATA_START,
1899 pModal->txFrameToDataStart);
1900 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1901 pModal->txFrameToPaOn);
1902 }
1903
1904 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1905 if (IS_CHAN_HT40(chan))
1906 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1907 AR_PHY_SETTLING_SWITCH,
1908 pModal->swSettleHt40);
1909 }
1910
1911 if (AR_SREV_9280_20_OR_LATER(ah) &&
1912 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1913 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
1914 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
1915 pModal->miscBits);
1916
1917
1918 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
1919 if (IS_CHAN_2GHZ(chan))
1920 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
1921 eep->baseEepHeader.dacLpMode);
1922 else if (eep->baseEepHeader.dacHiPwrMode_5G)
1923 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
1924 else
1925 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
1926 eep->baseEepHeader.dacLpMode);
1927
1928 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
1929 pModal->miscBits >> 2);
1930
1931 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
1932 AR_PHY_TX_DESIRED_SCALE_CCK,
1933 eep->baseEepHeader.desiredScaleCCK);
1934 }
1935}
1936
1937static void ath9k_hw_def_set_addac(struct ath_hw *ah,
1938 struct ath9k_channel *chan)
1939{
1940#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
1941 struct modal_eep_header *pModal;
1942 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1943 u8 biaslevel;
1944
1945 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1946 return;
1947
1948 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1949 return;
1950
1951 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1952
1953 if (pModal->xpaBiasLvl != 0xff) {
1954 biaslevel = pModal->xpaBiasLvl;
1955 } else {
1956 u16 resetFreqBin, freqBin, freqCount = 0;
1957 struct chan_centers centers;
1958
1959 ath9k_hw_get_channel_centers(ah, chan, &centers);
1960
1961 resetFreqBin = FREQ2FBIN(centers.synth_center,
1962 IS_CHAN_2GHZ(chan));
1963 freqBin = XPA_LVL_FREQ(0) & 0xff;
1964 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
1965
1966 freqCount++;
1967
1968 while (freqCount < 3) {
1969 if (XPA_LVL_FREQ(freqCount) == 0x0)
1970 break;
1971
1972 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
1973 if (resetFreqBin >= freqBin)
1974 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
1975 else
1976 break;
1977 freqCount++;
1978 }
1979 }
1980
1981 if (IS_CHAN_2GHZ(chan)) {
1982 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
1983 7, 1) & (~0x18)) | biaslevel << 3;
1984 } else {
1985 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
1986 6, 1) & (~0xc0)) | biaslevel << 6;
1987 }
1988#undef XPA_LVL_FREQ
1989}
1990
1991static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
1992 struct ath9k_channel *chan,
1993 struct cal_data_per_freq *pRawDataSet,
1994 u8 *bChans, u16 availPiers,
1995 u16 tPdGainOverlap, int16_t *pMinCalPower,
1996 u16 *pPdGainBoundaries, u8 *pPDADCValues,
1997 u16 numXpdGains)
1998{
1999 int i, j, k;
2000 int16_t ss;
2001 u16 idxL = 0, idxR = 0, numPiers;
2002 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
2003 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2004 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
2005 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2006 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
2007 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2008
2009 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
2010 u8 minPwrT4[AR5416_NUM_PD_GAINS];
2011 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
2012 int16_t vpdStep;
2013 int16_t tmpVal;
2014 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
2015 bool match;
2016 int16_t minDelta = 0;
2017 struct chan_centers centers;
2018
2019 ath9k_hw_get_channel_centers(ah, chan, &centers);
2020
2021 for (numPiers = 0; numPiers < availPiers; numPiers++) {
2022 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
2023 break;
2024 }
2025
2026 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
2027 IS_CHAN_2GHZ(chan)),
2028 bChans, numPiers, &idxL, &idxR);
2029
2030 if (match) {
2031 for (i = 0; i < numXpdGains; i++) {
2032 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
2033 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
2034 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2035 pRawDataSet[idxL].pwrPdg[i],
2036 pRawDataSet[idxL].vpdPdg[i],
2037 AR5416_PD_GAIN_ICEPTS,
2038 vpdTableI[i]);
2039 }
2040 } else {
2041 for (i = 0; i < numXpdGains; i++) {
2042 pVpdL = pRawDataSet[idxL].vpdPdg[i];
2043 pPwrL = pRawDataSet[idxL].pwrPdg[i];
2044 pVpdR = pRawDataSet[idxR].vpdPdg[i];
2045 pPwrR = pRawDataSet[idxR].pwrPdg[i];
2046
2047 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
2048
2049 maxPwrT4[i] =
2050 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
2051 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
2052
2053
2054 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2055 pPwrL, pVpdL,
2056 AR5416_PD_GAIN_ICEPTS,
2057 vpdTableL[i]);
2058 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2059 pPwrR, pVpdR,
2060 AR5416_PD_GAIN_ICEPTS,
2061 vpdTableR[i]);
2062
2063 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
2064 vpdTableI[i][j] =
2065 (u8)(ath9k_hw_interpolate((u16)
2066 FREQ2FBIN(centers.
2067 synth_center,
2068 IS_CHAN_2GHZ
2069 (chan)),
2070 bChans[idxL], bChans[idxR],
2071 vpdTableL[i][j], vpdTableR[i][j]));
2072 }
2073 }
2074 }
2075
2076 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
2077
2078 k = 0;
2079
2080 for (i = 0; i < numXpdGains; i++) {
2081 if (i == (numXpdGains - 1))
2082 pPdGainBoundaries[i] =
2083 (u16)(maxPwrT4[i] / 2);
2084 else
2085 pPdGainBoundaries[i] =
2086 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
2087
2088 pPdGainBoundaries[i] =
2089 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
2090
2091 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
2092 minDelta = pPdGainBoundaries[0] - 23;
2093 pPdGainBoundaries[0] = 23;
2094 } else {
2095 minDelta = 0;
2096 }
2097
2098 if (i == 0) {
2099 if (AR_SREV_9280_10_OR_LATER(ah))
2100 ss = (int16_t)(0 - (minPwrT4[i] / 2));
2101 else
2102 ss = 0;
2103 } else {
2104 ss = (int16_t)((pPdGainBoundaries[i - 1] -
2105 (minPwrT4[i] / 2)) -
2106 tPdGainOverlap + 1 + minDelta);
2107 }
2108 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
2109 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2110
2111 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2112 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
2113 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
2114 ss++;
2115 }
2116
2117 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
2118 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
2119 (minPwrT4[i] / 2));
2120 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
2121 tgtIndex : sizeCurrVpdTable;
2122
2123 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2124 pPDADCValues[k++] = vpdTableI[i][ss++];
2125 }
2126
2127 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
2128 vpdTableI[i][sizeCurrVpdTable - 2]);
2129 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2130
2131 if (tgtIndex > maxIndex) {
2132 while ((ss <= tgtIndex) &&
2133 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2134 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
2135 (ss - maxIndex + 1) * vpdStep));
2136 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
2137 255 : tmpVal);
2138 ss++;
2139 }
2140 }
2141 }
2142
2143 while (i < AR5416_PD_GAINS_IN_MASK) {
2144 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
2145 i++;
2146 }
2147
2148 while (k < AR5416_NUM_PDADC_VALUES) {
2149 pPDADCValues[k] = pPDADCValues[k - 1];
2150 k++;
2151 }
2152
2153 return;
2154}
2155
2156static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2157 struct ath9k_channel *chan,
2158 int16_t *pTxPowerIndexOffset)
2159{
2160#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
2161#define SM_PDGAIN_B(x, y) \
2162 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
2163
2164 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2165 struct cal_data_per_freq *pRawDataset;
2166 u8 *pCalBChans = NULL;
2167 u16 pdGainOverlap_t2;
2168 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
2169 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
2170 u16 numPiers, i, j;
2171 int16_t tMinCalPower;
2172 u16 numXpdGain, xpdMask;
2173 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
2174 u32 reg32, regOffset, regChainOffset;
2175 int16_t modalIdx;
2176
2177 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
2178 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
2179
2180 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2181 AR5416_EEP_MINOR_VER_2) {
2182 pdGainOverlap_t2 =
2183 pEepData->modalHeader[modalIdx].pdGainOverlap;
2184 } else {
2185 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
2186 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
2187 }
2188
2189 if (IS_CHAN_2GHZ(chan)) {
2190 pCalBChans = pEepData->calFreqPier2G;
2191 numPiers = AR5416_NUM_2G_CAL_PIERS;
2192 } else {
2193 pCalBChans = pEepData->calFreqPier5G;
2194 numPiers = AR5416_NUM_5G_CAL_PIERS;
2195 }
2196
2197 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
2198 pRawDataset = pEepData->calPierData2G[0];
2199 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
2200 pRawDataset)->vpdPdg[0][0];
2201 }
2202
2203 numXpdGain = 0;
2204
2205 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
2206 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
2207 if (numXpdGain >= AR5416_NUM_PD_GAINS)
2208 break;
2209 xpdGainValues[numXpdGain] =
2210 (u16)(AR5416_PD_GAINS_IN_MASK - i);
2211 numXpdGain++;
2212 }
2213 }
2214
2215 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
2216 (numXpdGain - 1) & 0x3);
2217 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
2218 xpdGainValues[0]);
2219 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
2220 xpdGainValues[1]);
2221 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
2222 xpdGainValues[2]);
2223
2224 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2225 if (AR_SREV_5416_20_OR_LATER(ah) &&
2226 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
2227 (i != 0)) {
2228 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2229 } else
2230 regChainOffset = i * 0x1000;
2231
2232 if (pEepData->baseEepHeader.txMask & (1 << i)) {
2233 if (IS_CHAN_2GHZ(chan))
2234 pRawDataset = pEepData->calPierData2G[i];
2235 else
2236 pRawDataset = pEepData->calPierData5G[i];
2237
2238
2239 if (OLC_FOR_AR9280_20_LATER) {
2240 u8 pcdacIdx;
2241 u8 txPower;
2242
2243 ath9k_get_txgain_index(ah, chan,
2244 (struct calDataPerFreqOpLoop *)pRawDataset,
2245 pCalBChans, numPiers, &txPower, &pcdacIdx);
2246 ath9k_olc_get_pdadcs(ah, pcdacIdx,
2247 txPower/2, pdadcValues);
2248 } else {
2249 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
2250 chan, pRawDataset,
2251 pCalBChans, numPiers,
2252 pdGainOverlap_t2,
2253 &tMinCalPower,
2254 gainBoundaries,
2255 pdadcValues,
2256 numXpdGain);
2257 }
2258
2259 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
2260 if (OLC_FOR_AR9280_20_LATER) {
2261 REG_WRITE(ah,
2262 AR_PHY_TPCRG5 + regChainOffset,
2263 SM(0x6,
2264 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
2265 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
2266 SM_PD_GAIN(3) | SM_PD_GAIN(4));
2267 } else {
2268 REG_WRITE(ah,
2269 AR_PHY_TPCRG5 + regChainOffset,
2270 SM(pdGainOverlap_t2,
2271 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
2272 SM_PDGAIN_B(0, 1) |
2273 SM_PDGAIN_B(1, 2) |
2274 SM_PDGAIN_B(2, 3) |
2275 SM_PDGAIN_B(3, 4));
2276 }
2277 }
2278
2279 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
2280 for (j = 0; j < 32; j++) {
2281 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
2282 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
2283 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
2284 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
2285 REG_WRITE(ah, regOffset, reg32);
2286
2287 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2288 "PDADC (%d,%4x): %4.4x %8.8x\n",
2289 i, regChainOffset, regOffset,
2290 reg32);
2291 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2292 "PDADC: Chain %d | PDADC %3d "
2293 "Value %3d | PDADC %3d Value %3d | "
2294 "PDADC %3d Value %3d | PDADC %3d "
2295 "Value %3d |\n",
2296 i, 4 * j, pdadcValues[4 * j],
2297 4 * j + 1, pdadcValues[4 * j + 1],
2298 4 * j + 2, pdadcValues[4 * j + 2],
2299 4 * j + 3,
2300 pdadcValues[4 * j + 3]);
2301
2302 regOffset += 4;
2303 }
2304 }
2305 }
2306
2307 *pTxPowerIndexOffset = 0;
2308#undef SM_PD_GAIN
2309#undef SM_PDGAIN_B
2310}
2311
2312static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2313 struct ath9k_channel *chan,
2314 int16_t *ratesArray,
2315 u16 cfgCtl,
2316 u16 AntennaReduction,
2317 u16 twiceMaxRegulatoryPower,
2318 u16 powerLimit)
2319{
2320#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
2321#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
2322
2323 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2324 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2325 static const u16 tpScaleReductionTable[5] =
2326 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
2327
2328 int i;
2329 int16_t twiceLargestAntenna;
2330 struct cal_ctl_data *rep;
2331 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
2332 0, { 0, 0, 0, 0}
2333 };
2334 struct cal_target_power_leg targetPowerOfdmExt = {
2335 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
2336 0, { 0, 0, 0, 0 }
2337 };
2338 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
2339 0, {0, 0, 0, 0}
2340 };
2341 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
2342 u16 ctlModesFor11a[] =
2343 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
2344 u16 ctlModesFor11g[] =
2345 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
2346 CTL_2GHT40
2347 };
2348 u16 numCtlModes, *pCtlMode, ctlMode, freq;
2349 struct chan_centers centers;
2350 int tx_chainmask;
2351 u16 twiceMinEdgePower;
2352
2353 tx_chainmask = ah->txchainmask;
2354
2355 ath9k_hw_get_channel_centers(ah, chan, &centers);
2356
2357 twiceLargestAntenna = max(
2358 pEepData->modalHeader
2359 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
2360 pEepData->modalHeader
2361 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
2362
2363 twiceLargestAntenna = max((u8)twiceLargestAntenna,
2364 pEepData->modalHeader
2365 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
2366
2367 twiceLargestAntenna = (int16_t)min(AntennaReduction -
2368 twiceLargestAntenna, 0);
2369
2370 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
2371
2372 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
2373 maxRegAllowedPower -=
2374 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
2375 }
2376
2377 scaledPower = min(powerLimit, maxRegAllowedPower);
2378
2379 switch (ar5416_get_ntxchains(tx_chainmask)) {
2380 case 1:
2381 break;
2382 case 2:
2383 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
2384 break;
2385 case 3:
2386 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
2387 break;
2388 }
2389
2390 scaledPower = max((u16)0, scaledPower);
2391
2392 if (IS_CHAN_2GHZ(chan)) {
2393 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
2394 SUB_NUM_CTL_MODES_AT_2G_40;
2395 pCtlMode = ctlModesFor11g;
2396
2397 ath9k_hw_get_legacy_target_powers(ah, chan,
2398 pEepData->calTargetPowerCck,
2399 AR5416_NUM_2G_CCK_TARGET_POWERS,
2400 &targetPowerCck, 4, false);
2401 ath9k_hw_get_legacy_target_powers(ah, chan,
2402 pEepData->calTargetPower2G,
2403 AR5416_NUM_2G_20_TARGET_POWERS,
2404 &targetPowerOfdm, 4, false);
2405 ath9k_hw_get_target_powers(ah, chan,
2406 pEepData->calTargetPower2GHT20,
2407 AR5416_NUM_2G_20_TARGET_POWERS,
2408 &targetPowerHt20, 8, false);
2409
2410 if (IS_CHAN_HT40(chan)) {
2411 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
2412 ath9k_hw_get_target_powers(ah, chan,
2413 pEepData->calTargetPower2GHT40,
2414 AR5416_NUM_2G_40_TARGET_POWERS,
2415 &targetPowerHt40, 8, true);
2416 ath9k_hw_get_legacy_target_powers(ah, chan,
2417 pEepData->calTargetPowerCck,
2418 AR5416_NUM_2G_CCK_TARGET_POWERS,
2419 &targetPowerCckExt, 4, true);
2420 ath9k_hw_get_legacy_target_powers(ah, chan,
2421 pEepData->calTargetPower2G,
2422 AR5416_NUM_2G_20_TARGET_POWERS,
2423 &targetPowerOfdmExt, 4, true);
2424 }
2425 } else {
2426 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
2427 SUB_NUM_CTL_MODES_AT_5G_40;
2428 pCtlMode = ctlModesFor11a;
2429
2430 ath9k_hw_get_legacy_target_powers(ah, chan,
2431 pEepData->calTargetPower5G,
2432 AR5416_NUM_5G_20_TARGET_POWERS,
2433 &targetPowerOfdm, 4, false);
2434 ath9k_hw_get_target_powers(ah, chan,
2435 pEepData->calTargetPower5GHT20,
2436 AR5416_NUM_5G_20_TARGET_POWERS,
2437 &targetPowerHt20, 8, false);
2438
2439 if (IS_CHAN_HT40(chan)) {
2440 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
2441 ath9k_hw_get_target_powers(ah, chan,
2442 pEepData->calTargetPower5GHT40,
2443 AR5416_NUM_5G_40_TARGET_POWERS,
2444 &targetPowerHt40, 8, true);
2445 ath9k_hw_get_legacy_target_powers(ah, chan,
2446 pEepData->calTargetPower5G,
2447 AR5416_NUM_5G_20_TARGET_POWERS,
2448 &targetPowerOfdmExt, 4, true);
2449 }
2450 }
2451
2452 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
2453 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
2454 (pCtlMode[ctlMode] == CTL_2GHT40);
2455 if (isHt40CtlMode)
2456 freq = centers.synth_center;
2457 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
2458 freq = centers.ext_center;
2459 else
2460 freq = centers.ctl_center;
2461
2462 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
2463 ah->eep_ops->get_eeprom_rev(ah) <= 2)
2464 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2465
2466 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
2467 if ((((cfgCtl & ~CTL_MODE_M) |
2468 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2469 pEepData->ctlIndex[i]) ||
2470 (((cfgCtl & ~CTL_MODE_M) |
2471 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2472 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
2473 rep = &(pEepData->ctlData[i]);
2474
2475 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
2476 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
2477 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
2478
2479 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
2480 twiceMaxEdgePower = min(twiceMaxEdgePower,
2481 twiceMinEdgePower);
2482 } else {
2483 twiceMaxEdgePower = twiceMinEdgePower;
2484 break;
2485 }
2486 }
2487 }
2488
2489 minCtlPower = min(twiceMaxEdgePower, scaledPower);
2490
2491 switch (pCtlMode[ctlMode]) {
2492 case CTL_11B:
2493 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
2494 targetPowerCck.tPow2x[i] =
2495 min((u16)targetPowerCck.tPow2x[i],
2496 minCtlPower);
2497 }
2498 break;
2499 case CTL_11A:
2500 case CTL_11G:
2501 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
2502 targetPowerOfdm.tPow2x[i] =
2503 min((u16)targetPowerOfdm.tPow2x[i],
2504 minCtlPower);
2505 }
2506 break;
2507 case CTL_5GHT20:
2508 case CTL_2GHT20:
2509 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
2510 targetPowerHt20.tPow2x[i] =
2511 min((u16)targetPowerHt20.tPow2x[i],
2512 minCtlPower);
2513 }
2514 break;
2515 case CTL_11B_EXT:
2516 targetPowerCckExt.tPow2x[0] = min((u16)
2517 targetPowerCckExt.tPow2x[0],
2518 minCtlPower);
2519 break;
2520 case CTL_11A_EXT:
2521 case CTL_11G_EXT:
2522 targetPowerOfdmExt.tPow2x[0] = min((u16)
2523 targetPowerOfdmExt.tPow2x[0],
2524 minCtlPower);
2525 break;
2526 case CTL_5GHT40:
2527 case CTL_2GHT40:
2528 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2529 targetPowerHt40.tPow2x[i] =
2530 min((u16)targetPowerHt40.tPow2x[i],
2531 minCtlPower);
2532 }
2533 break;
2534 default:
2535 break;
2536 }
2537 }
2538
2539 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
2540 ratesArray[rate18mb] = ratesArray[rate24mb] =
2541 targetPowerOfdm.tPow2x[0];
2542 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
2543 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
2544 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
2545 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
2546
2547 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
2548 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
2549
2550 if (IS_CHAN_2GHZ(chan)) {
2551 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
2552 ratesArray[rate2s] = ratesArray[rate2l] =
2553 targetPowerCck.tPow2x[1];
2554 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
2555 targetPowerCck.tPow2x[2];
2556 ratesArray[rate11s] = ratesArray[rate11l] =
2557 targetPowerCck.tPow2x[3];
2558 }
2559 if (IS_CHAN_HT40(chan)) {
2560 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2561 ratesArray[rateHt40_0 + i] =
2562 targetPowerHt40.tPow2x[i];
2563 }
2564 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
2565 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
2566 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
2567 if (IS_CHAN_2GHZ(chan)) {
2568 ratesArray[rateExtCck] =
2569 targetPowerCckExt.tPow2x[0];
2570 }
2571 }
2572}
2573
2574static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
2575 struct ath9k_channel *chan,
2576 u16 cfgCtl,
2577 u8 twiceAntennaReduction,
2578 u8 twiceMaxRegulatoryPower,
2579 u8 powerLimit)
2580{
2581#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
2582 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2583 struct modal_eep_header *pModal =
2584 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
2585 int16_t ratesArray[Ar5416RateSize];
2586 int16_t txPowerIndexOffset = 0;
2587 u8 ht40PowerIncForPdadc = 2;
2588 int i, cck_ofdm_delta = 0;
2589
2590 memset(ratesArray, 0, sizeof(ratesArray));
2591
2592 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2593 AR5416_EEP_MINOR_VER_2) {
2594 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
2595 }
2596
2597 ath9k_hw_set_def_power_per_rate_table(ah, chan,
2598 &ratesArray[0], cfgCtl,
2599 twiceAntennaReduction,
2600 twiceMaxRegulatoryPower,
2601 powerLimit);
2602
2603 ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
2604
2605 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
2606 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
2607 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
2608 ratesArray[i] = AR5416_MAX_RATE_POWER;
2609 }
2610
2611 if (AR_SREV_9280_10_OR_LATER(ah)) {
2612 for (i = 0; i < Ar5416RateSize; i++)
2613 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
2614 }
2615
2616 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
2617 ATH9K_POW_SM(ratesArray[rate18mb], 24)
2618 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
2619 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
2620 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
2621 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
2622 ATH9K_POW_SM(ratesArray[rate54mb], 24)
2623 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
2624 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
2625 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
2626
2627 if (IS_CHAN_2GHZ(chan)) {
2628 if (OLC_FOR_AR9280_20_LATER) {
2629 cck_ofdm_delta = 2;
2630 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2631 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
2632 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
2633 | ATH9K_POW_SM(ratesArray[rateXr], 8)
2634 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
2635 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2636 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
2637 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
2638 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
2639 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
2640 } else {
2641 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2642 ATH9K_POW_SM(ratesArray[rate2s], 24)
2643 | ATH9K_POW_SM(ratesArray[rate2l], 16)
2644 | ATH9K_POW_SM(ratesArray[rateXr], 8)
2645 | ATH9K_POW_SM(ratesArray[rate1l], 0));
2646 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2647 ATH9K_POW_SM(ratesArray[rate11s], 24)
2648 | ATH9K_POW_SM(ratesArray[rate11l], 16)
2649 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
2650 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
2651 }
2652 }
2653
2654 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
2655 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
2656 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
2657 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
2658 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
2659 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
2660 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
2661 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
2662 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
2663 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
2664
2665 if (IS_CHAN_HT40(chan)) {
2666 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
2667 ATH9K_POW_SM(ratesArray[rateHt40_3] +
2668 ht40PowerIncForPdadc, 24)
2669 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
2670 ht40PowerIncForPdadc, 16)
2671 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
2672 ht40PowerIncForPdadc, 8)
2673 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
2674 ht40PowerIncForPdadc, 0));
2675 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
2676 ATH9K_POW_SM(ratesArray[rateHt40_7] +
2677 ht40PowerIncForPdadc, 24)
2678 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
2679 ht40PowerIncForPdadc, 16)
2680 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
2681 ht40PowerIncForPdadc, 8)
2682 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
2683 ht40PowerIncForPdadc, 0));
2684 if (OLC_FOR_AR9280_20_LATER) {
2685 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2686 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
2687 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
2688 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
2689 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
2690 } else {
2691 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2692 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
2693 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
2694 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
2695 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
2696 }
2697 }
2698
2699 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2700 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
2701 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
2702
2703 i = rate6mb;
2704
2705 if (IS_CHAN_HT40(chan))
2706 i = rateHt40_0;
2707 else if (IS_CHAN_HT20(chan))
2708 i = rateHt20_0;
2709
2710 if (AR_SREV_9280_10_OR_LATER(ah))
2711 ah->regulatory.max_power_level =
2712 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
2713 else
2714 ah->regulatory.max_power_level = ratesArray[i];
2715
2716 switch(ar5416_get_ntxchains(ah->txchainmask)) {
2717 case 1:
2718 break;
2719 case 2:
2720 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
2721 break;
2722 case 3:
2723 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
2724 break;
2725 default:
2726 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2727 "Invalid chainmask configuration\n");
2728 break;
2729 }
2730}
2731
2732static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
2733 enum ieee80211_band freq_band)
2734{
2735 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2736 struct modal_eep_header *pModal =
2737 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
2738 struct base_eep_header *pBase = &eep->baseEepHeader;
2739 u8 num_ant_config;
2740
2741 num_ant_config = 1;
2742
2743 if (pBase->version >= 0x0E0D)
2744 if (pModal->useAnt1)
2745 num_ant_config += 1;
2746
2747 return num_ant_config;
2748}
2749
2750static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
2751 struct ath9k_channel *chan)
2752{
2753 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2754 struct modal_eep_header *pModal =
2755 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2756
2757 return pModal->antCtrlCommon & 0xFFFF;
2758}
2759
2760static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
2761{
2762#define EEP_DEF_SPURCHAN \
2763 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
2764
2765 u16 spur_val = AR_NO_SPUR;
2766
2767 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2768 "Getting spur idx %d is2Ghz. %d val %x\n",
2769 i, is2GHz, ah->config.spurchans[i][is2GHz]);
2770
2771 switch (ah->config.spurmode) {
2772 case SPUR_DISABLE:
2773 break;
2774 case SPUR_ENABLE_IOCTL:
2775 spur_val = ah->config.spurchans[i][is2GHz];
2776 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2777 "Getting spur val from new loc. %d\n", spur_val);
2778 break;
2779 case SPUR_ENABLE_EEPROM:
2780 spur_val = EEP_DEF_SPURCHAN;
2781 break;
2782 }
2783
2784 return spur_val;
2785
2786#undef EEP_DEF_SPURCHAN
2787}
2788
2789static struct eeprom_ops eep_def_ops = {
2790 .check_eeprom = ath9k_hw_def_check_eeprom,
2791 .get_eeprom = ath9k_hw_def_get_eeprom,
2792 .fill_eeprom = ath9k_hw_def_fill_eeprom,
2793 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
2794 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
2795 .get_num_ant_config = ath9k_hw_def_get_num_ant_config,
2796 .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
2797 .set_board_values = ath9k_hw_def_set_board_values,
2798 .set_addac = ath9k_hw_def_set_addac,
2799 .set_txpower = ath9k_hw_def_set_txpower,
2800 .get_spur_channel = ath9k_hw_def_get_spur_channel
2801};
2802
2803static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
2804{
2805 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
2806}
2807
2808static int ath9k_hw_AR9287_get_eeprom_rev(struct ath_hw *ah)
2809{
2810 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
2811}
2812
2813static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
2814{
2815 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
2816 u16 *eep_data;
2817 int addr, eep_start_loc = AR9287_EEP_START_LOC;
2818 eep_data = (u16 *)eep;
2819
2820 if (!ath9k_hw_use_flash(ah)) {
2821 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2822 "Reading from EEPROM, not flash\n");
2823 }
2824
2825 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
2826 addr++) {
2827 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
2828 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2829 "Unable to read eeprom region \n");
2830 return false;
2831 }
2832 eep_data++;
2833 }
2834 return true;
2835}
2836
2837static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
2838{
2839 u32 sum = 0, el, integer;
2840 u16 temp, word, magic, magic2, *eepdata;
2841 int i, addr;
2842 bool need_swap = false;
2843 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
2844
2845 if (!ath9k_hw_use_flash(ah)) {
2846 if (!ath9k_hw_nvram_read
2847 (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
2848 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2849 "Reading Magic # failed\n");
2850 return false;
2851 }
2852
2853 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2854 "Read Magic = 0x%04X\n", magic);
2855 if (magic != AR5416_EEPROM_MAGIC) {
2856 magic2 = swab16(magic);
2857
2858 if (magic2 == AR5416_EEPROM_MAGIC) {
2859 need_swap = true;
2860 eepdata = (u16 *)(&ah->eeprom);
2861
2862 for (addr = 0;
2863 addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
2864 addr++) {
2865 temp = swab16(*eepdata);
2866 *eepdata = temp;
2867 eepdata++;
2868 }
2869 } else {
2870 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2871 "Invalid EEPROM Magic. "
2872 "endianness mismatch.\n");
2873 return -EINVAL;
2874 }
2875 }
2876 }
2877 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ?
2878 "True" : "False");
2879
2880 if (need_swap)
2881 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
2882 else
2883 el = ah->eeprom.map9287.baseEepHeader.length;
2884
2885 if (el > sizeof(struct ar9287_eeprom))
2886 el = sizeof(struct ar9287_eeprom) / sizeof(u16);
2887 else
2888 el = el / sizeof(u16);
2889
2890 eepdata = (u16 *)(&ah->eeprom);
2891 for (i = 0; i < el; i++)
2892 sum ^= *eepdata++;
2893
2894 if (need_swap) {
2895 word = swab16(eep->baseEepHeader.length);
2896 eep->baseEepHeader.length = word;
2897
2898 word = swab16(eep->baseEepHeader.checksum);
2899 eep->baseEepHeader.checksum = word;
2900
2901 word = swab16(eep->baseEepHeader.version);
2902 eep->baseEepHeader.version = word;
2903
2904 word = swab16(eep->baseEepHeader.regDmn[0]);
2905 eep->baseEepHeader.regDmn[0] = word;
2906
2907 word = swab16(eep->baseEepHeader.regDmn[1]);
2908 eep->baseEepHeader.regDmn[1] = word;
2909
2910 word = swab16(eep->baseEepHeader.rfSilent);
2911 eep->baseEepHeader.rfSilent = word;
2912
2913 word = swab16(eep->baseEepHeader.blueToothOptions);
2914 eep->baseEepHeader.blueToothOptions = word;
2915
2916 word = swab16(eep->baseEepHeader.deviceCap);
2917 eep->baseEepHeader.deviceCap = word;
2918
2919 integer = swab32(eep->modalHeader.antCtrlCommon);
2920 eep->modalHeader.antCtrlCommon = integer;
2921
2922 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
2923 integer = swab32(eep->modalHeader.antCtrlChain[i]);
2924 eep->modalHeader.antCtrlChain[i] = integer;
2925 }
2926
2927 for (i = 0; i < AR9287_EEPROM_MODAL_SPURS; i++) {
2928 word = swab16(eep->modalHeader.spurChans[i].spurChan);
2929 eep->modalHeader.spurChans[i].spurChan = word;
2930 }
2931 }
2932
2933 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
2934 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
2935 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2936 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
2937 sum, ah->eep_ops->get_eeprom_ver(ah));
2938 return -EINVAL;
2939 }
2940
2941 return 0;
2942}
2943
2944static u32 ath9k_hw_AR9287_get_eeprom(struct ath_hw *ah,
2945 enum eeprom_param param)
2946{
2947 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
2948 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
2949 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
2950 u16 ver_minor;
2951
2952 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
2953 switch (param) {
2954 case EEP_NFTHRESH_2:
2955 return pModal->noiseFloorThreshCh[0];
2956 case AR_EEPROM_MAC(0):
2957 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
2958 case AR_EEPROM_MAC(1):
2959 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
2960 case AR_EEPROM_MAC(2):
2961 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
2962 case EEP_REG_0:
2963 return pBase->regDmn[0];
2964 case EEP_REG_1:
2965 return pBase->regDmn[1];
2966 case EEP_OP_CAP:
2967 return pBase->deviceCap;
2968 case EEP_OP_MODE:
2969 return pBase->opCapFlags;
2970 case EEP_RF_SILENT:
2971 return pBase->rfSilent;
2972 case EEP_MINOR_REV:
2973 return ver_minor;
2974 case EEP_TX_MASK:
2975 return pBase->txMask;
2976 case EEP_RX_MASK:
2977 return pBase->rxMask;
2978 case EEP_DEV_TYPE:
2979 return pBase->deviceType;
2980 case EEP_OL_PWRCTRL:
2981 return pBase->openLoopPwrCntl;
2982 case EEP_TEMPSENSE_SLOPE:
2983 if (ver_minor >= AR9287_EEP_MINOR_VER_2)
2984 return pBase->tempSensSlope;
2985 else
2986 return 0;
2987 case EEP_TEMPSENSE_SLOPE_PAL_ON:
2988 if (ver_minor >= AR9287_EEP_MINOR_VER_3)
2989 return pBase->tempSensSlopePalOn;
2990 else
2991 return 0;
2992 default:
2993 return 0;
2994 }
2995}
2996
2997
2998static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
2999 struct ath9k_channel *chan,
3000 struct cal_data_per_freq_ar9287 *pRawDataSet,
3001 u8 *bChans, u16 availPiers,
3002 u16 tPdGainOverlap, int16_t *pMinCalPower,
3003 u16 *pPdGainBoundaries, u8 *pPDADCValues,
3004 u16 numXpdGains)
3005{
3006#define TMP_VAL_VPD_TABLE \
3007 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
3008
3009 int i, j, k;
3010 int16_t ss;
3011 u16 idxL = 0, idxR = 0, numPiers;
3012 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
3013 u8 minPwrT4[AR9287_NUM_PD_GAINS];
3014 u8 maxPwrT4[AR9287_NUM_PD_GAINS];
3015 int16_t vpdStep;
3016 int16_t tmpVal;
3017 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
3018 bool match;
3019 int16_t minDelta = 0;
3020 struct chan_centers centers;
3021 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
3022 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3023 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
3024 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3025 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
3026 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3027
3028 ath9k_hw_get_channel_centers(ah, chan, &centers);
3029
3030 for (numPiers = 0; numPiers < availPiers; numPiers++) {
3031 if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
3032 break;
3033 }
3034
3035 match = ath9k_hw_get_lower_upper_index(
3036 (u8)FREQ2FBIN(centers.synth_center,
3037 IS_CHAN_2GHZ(chan)), bChans, numPiers,
3038 &idxL, &idxR);
3039
3040 if (match) {
3041 for (i = 0; i < numXpdGains; i++) {
3042 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
3043 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
3044 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3045 pRawDataSet[idxL].pwrPdg[i],
3046 pRawDataSet[idxL].vpdPdg[i],
3047 AR9287_PD_GAIN_ICEPTS, vpdTableI[i]);
3048 }
3049 } else {
3050 for (i = 0; i < numXpdGains; i++) {
3051 pVpdL = pRawDataSet[idxL].vpdPdg[i];
3052 pPwrL = pRawDataSet[idxL].pwrPdg[i];
3053 pVpdR = pRawDataSet[idxR].vpdPdg[i];
3054 pPwrR = pRawDataSet[idxR].pwrPdg[i];
3055
3056 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
3057
3058 maxPwrT4[i] =
3059 min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1],
3060 pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
3061
3062 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3063 pPwrL, pVpdL,
3064 AR9287_PD_GAIN_ICEPTS,
3065 vpdTableL[i]);
3066 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3067 pPwrR, pVpdR,
3068 AR9287_PD_GAIN_ICEPTS,
3069 vpdTableR[i]);
3070
3071 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
3072 vpdTableI[i][j] =
3073 (u8)(ath9k_hw_interpolate((u16)
3074 FREQ2FBIN(centers. synth_center,
3075 IS_CHAN_2GHZ(chan)),
3076 bChans[idxL], bChans[idxR],
3077 vpdTableL[i][j], vpdTableR[i][j]));
3078 }
3079 }
3080 }
3081 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
3082
3083 k = 0;
3084 for (i = 0; i < numXpdGains; i++) {
3085 if (i == (numXpdGains - 1))
3086 pPdGainBoundaries[i] = (u16)(maxPwrT4[i] / 2);
3087 else
3088 pPdGainBoundaries[i] = (u16)((maxPwrT4[i] +
3089 minPwrT4[i+1]) / 4);
3090
3091 pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER,
3092 pPdGainBoundaries[i]);
3093
3094
3095 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
3096 minDelta = pPdGainBoundaries[0] - 23;
3097 pPdGainBoundaries[0] = 23;
3098 } else
3099 minDelta = 0;
3100
3101 if (i == 0) {
3102 if (AR_SREV_9280_10_OR_LATER(ah))
3103 ss = (int16_t)(0 - (minPwrT4[i] / 2));
3104 else
3105 ss = 0;
3106 } else
3107 ss = (int16_t)((pPdGainBoundaries[i-1] -
3108 (minPwrT4[i] / 2)) -
3109 tPdGainOverlap + 1 + minDelta);
3110
3111 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
3112 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
3113 while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) {
3114 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
3115 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
3116 ss++;
3117 }
3118
3119 sizeCurrVpdTable = (u8)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
3120 tgtIndex = (u8)(pPdGainBoundaries[i] +
3121 tPdGainOverlap - (minPwrT4[i] / 2));
3122 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
3123 tgtIndex : sizeCurrVpdTable;
3124
3125 while ((ss < maxIndex) && (k < (AR9287_NUM_PDADC_VALUES - 1)))
3126 pPDADCValues[k++] = vpdTableI[i][ss++];
3127
3128 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
3129 vpdTableI[i][sizeCurrVpdTable - 2]);
3130 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
3131 if (tgtIndex > maxIndex) {
3132 while ((ss <= tgtIndex) &&
3133 (k < (AR9287_NUM_PDADC_VALUES - 1))) {
3134 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
3135 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
3136 255 : tmpVal);
3137 ss++;
3138 }
3139 }
3140 }
3141
3142 while (i < AR9287_PD_GAINS_IN_MASK) {
3143 pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
3144 i++;
3145 }
3146
3147 while (k < AR9287_NUM_PDADC_VALUES) {
3148 pPDADCValues[k] = pPDADCValues[k-1];
3149 k++;
3150 }
3151
3152#undef TMP_VAL_VPD_TABLE
3153}
3154
3155static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
3156 struct ath9k_channel *chan,
3157 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
3158 u8 *pCalChans, u16 availPiers,
3159 int8_t *pPwr)
3160{
3161 u8 pcdac, i = 0;
3162 u16 idxL = 0, idxR = 0, numPiers;
3163 bool match;
3164 struct chan_centers centers;
3165
3166 ath9k_hw_get_channel_centers(ah, chan, &centers);
3167
3168 for (numPiers = 0; numPiers < availPiers; numPiers++) {
3169 if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED)
3170 break;
3171 }
3172
3173 match = ath9k_hw_get_lower_upper_index(
3174 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
3175 pCalChans, numPiers,
3176 &idxL, &idxR);
3177
3178 if (match) {
3179 pcdac = pRawDatasetOpLoop[idxL].pcdac[0][0];
3180 *pPwr = pRawDatasetOpLoop[idxL].pwrPdg[0][0];
3181 } else {
3182 pcdac = pRawDatasetOpLoop[idxR].pcdac[0][0];
3183 *pPwr = (pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
3184 pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
3185 }
3186
3187 while ((pcdac > ah->originalGain[i]) &&
3188 (i < (AR9280_TX_GAIN_TABLE_SIZE - 1)))
3189 i++;
3190}
3191
3192static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
3193 int32_t txPower, u16 chain)
3194{
3195 u32 tmpVal;
3196 u32 a;
3197
3198 tmpVal = REG_READ(ah, 0xa270);
3199 tmpVal = tmpVal & 0xFCFFFFFF;
3200 tmpVal = tmpVal | (0x3 << 24);
3201 REG_WRITE(ah, 0xa270, tmpVal);
3202
3203 tmpVal = REG_READ(ah, 0xb270);
3204 tmpVal = tmpVal & 0xFCFFFFFF;
3205 tmpVal = tmpVal | (0x3 << 24);
3206 REG_WRITE(ah, 0xb270, tmpVal);
3207
3208 if (chain == 0) {
3209 tmpVal = REG_READ(ah, 0xa398);
3210 tmpVal = tmpVal & 0xff00ffff;
3211 a = (txPower)&0xff;
3212 tmpVal = tmpVal | (a << 16);
3213 REG_WRITE(ah, 0xa398, tmpVal);
3214 }
3215
3216 if (chain == 1) {
3217 tmpVal = REG_READ(ah, 0xb398);
3218 tmpVal = tmpVal & 0xff00ffff;
3219 a = (txPower)&0xff;
3220 tmpVal = tmpVal | (a << 16);
3221 REG_WRITE(ah, 0xb398, tmpVal);
3222 }
3223}
3224
3225static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
3226 struct ath9k_channel *chan,
3227 int16_t *pTxPowerIndexOffset)
3228{
3229 struct cal_data_per_freq_ar9287 *pRawDataset;
3230 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
3231 u8 *pCalBChans = NULL;
3232 u16 pdGainOverlap_t2;
3233 u8 pdadcValues[AR9287_NUM_PDADC_VALUES];
3234 u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK];
3235 u16 numPiers = 0, i, j;
3236 int16_t tMinCalPower;
3237 u16 numXpdGain, xpdMask;
3238 u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0};
3239 u32 reg32, regOffset, regChainOffset;
3240 int16_t modalIdx, diff = 0;
3241 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
3242 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
3243 xpdMask = pEepData->modalHeader.xpdGain;
3244 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
3245 AR9287_EEP_MINOR_VER_2)
3246 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
3247 else
3248 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
3249 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
3250
3251 if (IS_CHAN_2GHZ(chan)) {
3252 pCalBChans = pEepData->calFreqPier2G;
3253 numPiers = AR9287_NUM_2G_CAL_PIERS;
3254 if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
3255 pRawDatasetOpenLoop =
3256 (struct cal_data_op_loop_ar9287 *)
3257 pEepData->calPierData2G[0];
3258 ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
3259 }
3260 }
3261
3262 numXpdGain = 0;
3263 for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) {
3264 if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) {
3265 if (numXpdGain >= AR9287_NUM_PD_GAINS)
3266 break;
3267 xpdGainValues[numXpdGain] =
3268 (u16)(AR9287_PD_GAINS_IN_MASK-i);
3269 numXpdGain++;
3270 }
3271 }
3272
3273 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
3274 (numXpdGain - 1) & 0x3);
3275 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
3276 xpdGainValues[0]);
3277 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
3278 xpdGainValues[1]);
3279 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
3280 xpdGainValues[2]);
3281
3282 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
3283 regChainOffset = i * 0x1000;
3284 if (pEepData->baseEepHeader.txMask & (1 << i)) {
3285 pRawDatasetOpenLoop = (struct cal_data_op_loop_ar9287 *)
3286 pEepData->calPierData2G[i];
3287 if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
3288 int8_t txPower;
3289 ar9287_eeprom_get_tx_gain_index(ah, chan,
3290 pRawDatasetOpenLoop,
3291 pCalBChans, numPiers,
3292 &txPower);
3293 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
3294 } else {
3295 pRawDataset =
3296 (struct cal_data_per_freq_ar9287 *)
3297 pEepData->calPierData2G[i];
3298 ath9k_hw_get_AR9287_gain_boundaries_pdadcs(
3299 ah, chan, pRawDataset,
3300 pCalBChans, numPiers,
3301 pdGainOverlap_t2,
3302 &tMinCalPower, gainBoundaries,
3303 pdadcValues, numXpdGain);
3304 }
3305
3306 if (i == 0) {
3307 if (!ath9k_hw_AR9287_get_eeprom(
3308 ah, EEP_OL_PWRCTRL)) {
3309 REG_WRITE(ah, AR_PHY_TPCRG5 +
3310 regChainOffset,
3311 SM(pdGainOverlap_t2,
3312 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
3313 SM(gainBoundaries[0],
3314 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
3315 | SM(gainBoundaries[1],
3316 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
3317 | SM(gainBoundaries[2],
3318 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
3319 | SM(gainBoundaries[3],
3320 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
3321 }
3322 }
3323
3324 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB !=
3325 pEepData->baseEepHeader.pwrTableOffset) {
3326 diff = (u16)
3327 (pEepData->baseEepHeader.pwrTableOffset
3328 - (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
3329 diff *= 2;
3330
3331 for (j = 0;
3332 j < ((u16)AR9287_NUM_PDADC_VALUES-diff);
3333 j++)
3334 pdadcValues[j] = pdadcValues[j+diff];
3335
3336 for (j = (u16)(AR9287_NUM_PDADC_VALUES-diff);
3337 j < AR9287_NUM_PDADC_VALUES; j++)
3338 pdadcValues[j] =
3339 pdadcValues[
3340 AR9287_NUM_PDADC_VALUES-diff];
3341 }
3342
3343 if (!ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
3344 regOffset = AR_PHY_BASE + (672 << 2) +
3345 regChainOffset;
3346 for (j = 0; j < 32; j++) {
3347 reg32 = ((pdadcValues[4*j + 0]
3348 & 0xFF) << 0) |
3349 ((pdadcValues[4*j + 1]
3350 & 0xFF) << 8) |
3351 ((pdadcValues[4*j + 2]
3352 & 0xFF) << 16) |
3353 ((pdadcValues[4*j + 3]
3354 & 0xFF) << 24) ;
3355 REG_WRITE(ah, regOffset, reg32);
3356
3357 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
3358 "PDADC (%d,%4x): %4.4x %8.8x\n",
3359 i, regChainOffset, regOffset,
3360 reg32);
3361
3362 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
3363 "PDADC: Chain %d | "
3364 "PDADC %3d Value %3d | "
3365 "PDADC %3d Value %3d | "
3366 "PDADC %3d Value %3d | "
3367 "PDADC %3d Value %3d |\n",
3368 i, 4 * j, pdadcValues[4 * j],
3369 4 * j + 1,
3370 pdadcValues[4 * j + 1],
3371 4 * j + 2,
3372 pdadcValues[4 * j + 2],
3373 4 * j + 3,
3374 pdadcValues[4 * j + 3]);
3375
3376 regOffset += 4;
3377 }
3378 }
3379 }
3380 }
3381
3382 *pTxPowerIndexOffset = 0;
3383}
3384
3385static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
3386 struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl,
3387 u16 AntennaReduction, u16 twiceMaxRegulatoryPower,
3388 u16 powerLimit)
3389{
3390#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
3391#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
3392
3393 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
3394 static const u16 tpScaleReductionTable[5] =
3395 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
3396 int i;
3397 int16_t twiceLargestAntenna;
3398 struct cal_ctl_data_ar9287 *rep;
3399 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
3400 targetPowerCck = {0, {0, 0, 0, 0} };
3401 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
3402 targetPowerCckExt = {0, {0, 0, 0, 0} };
3403 struct cal_target_power_ht targetPowerHt20,
3404 targetPowerHt40 = {0, {0, 0, 0, 0} };
3405 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
3406 u16 ctlModesFor11g[] =
3407 {CTL_11B, CTL_11G, CTL_2GHT20,
3408 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40};
3409 u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq;
3410 struct chan_centers centers;
3411 int tx_chainmask;
3412 u16 twiceMinEdgePower;
3413 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
3414 tx_chainmask = ah->txchainmask;
3415
3416 ath9k_hw_get_channel_centers(ah, chan, &centers);
3417
3418 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
3419 pEepData->modalHeader.antennaGainCh[1]);
3420
3421 twiceLargestAntenna = (int16_t)min((AntennaReduction) -
3422 twiceLargestAntenna, 0);
3423
3424 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
3425 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX)
3426 maxRegAllowedPower -=
3427 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
3428
3429 scaledPower = min(powerLimit, maxRegAllowedPower);
3430
3431 switch (ar5416_get_ntxchains(tx_chainmask)) {
3432 case 1:
3433 break;
3434 case 2:
3435 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
3436 break;
3437 case 3:
3438 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
3439 break;
3440 }
3441 scaledPower = max((u16)0, scaledPower);
3442
3443 if (IS_CHAN_2GHZ(chan)) {
3444 numCtlModes =
3445 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
3446 pCtlMode = ctlModesFor11g;
3447
3448 ath9k_hw_get_legacy_target_powers(ah, chan,
3449 pEepData->calTargetPowerCck,
3450 AR9287_NUM_2G_CCK_TARGET_POWERS,
3451 &targetPowerCck, 4, false);
3452 ath9k_hw_get_legacy_target_powers(ah, chan,
3453 pEepData->calTargetPower2G,
3454 AR9287_NUM_2G_20_TARGET_POWERS,
3455 &targetPowerOfdm, 4, false);
3456 ath9k_hw_get_target_powers(ah, chan,
3457 pEepData->calTargetPower2GHT20,
3458 AR9287_NUM_2G_20_TARGET_POWERS,
3459 &targetPowerHt20, 8, false);
3460
3461 if (IS_CHAN_HT40(chan)) {
3462 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
3463 ath9k_hw_get_target_powers(ah, chan,
3464 pEepData->calTargetPower2GHT40,
3465 AR9287_NUM_2G_40_TARGET_POWERS,
3466 &targetPowerHt40, 8, true);
3467 ath9k_hw_get_legacy_target_powers(ah, chan,
3468 pEepData->calTargetPowerCck,
3469 AR9287_NUM_2G_CCK_TARGET_POWERS,
3470 &targetPowerCckExt, 4, true);
3471 ath9k_hw_get_legacy_target_powers(ah, chan,
3472 pEepData->calTargetPower2G,
3473 AR9287_NUM_2G_20_TARGET_POWERS,
3474 &targetPowerOfdmExt, 4, true);
3475 }
3476 }
3477
3478 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
3479 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
3480 (pCtlMode[ctlMode] == CTL_2GHT40);
3481 if (isHt40CtlMode)
3482 freq = centers.synth_center;
3483 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
3484 freq = centers.ext_center;
3485 else
3486 freq = centers.ctl_center;
3487
3488 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
3489 ah->eep_ops->get_eeprom_rev(ah) <= 2)
3490 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
3491
3492 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
3493 if ((((cfgCtl & ~CTL_MODE_M) |
3494 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
3495 pEepData->ctlIndex[i]) ||
3496 (((cfgCtl & ~CTL_MODE_M) |
3497 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
3498 ((pEepData->ctlIndex[i] &
3499 CTL_MODE_M) | SD_NO_CTL))) {
3500
3501 rep = &(pEepData->ctlData[i]);
3502 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
3503 freq,
3504 rep->ctlEdges[ar5416_get_ntxchains(
3505 tx_chainmask) - 1],
3506 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
3507
3508 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
3509 twiceMaxEdgePower = min(
3510 twiceMaxEdgePower,
3511 twiceMinEdgePower);
3512 else {
3513 twiceMaxEdgePower = twiceMinEdgePower;
3514 break;
3515 }
3516 }
3517 }
3518
3519 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
3520
3521 switch (pCtlMode[ctlMode]) {
3522 case CTL_11B:
3523 for (i = 0;
3524 i < ARRAY_SIZE(targetPowerCck.tPow2x);
3525 i++) {
3526 targetPowerCck.tPow2x[i] = (u8)min(
3527 (u16)targetPowerCck.tPow2x[i],
3528 minCtlPower);
3529 }
3530 break;
3531 case CTL_11A:
3532 case CTL_11G:
3533 for (i = 0;
3534 i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
3535 i++) {
3536 targetPowerOfdm.tPow2x[i] = (u8)min(
3537 (u16)targetPowerOfdm.tPow2x[i],
3538 minCtlPower);
3539 }
3540 break;
3541 case CTL_5GHT20:
3542 case CTL_2GHT20:
3543 for (i = 0;
3544 i < ARRAY_SIZE(targetPowerHt20.tPow2x);
3545 i++) {
3546 targetPowerHt20.tPow2x[i] = (u8)min(
3547 (u16)targetPowerHt20.tPow2x[i],
3548 minCtlPower);
3549 }
3550 break;
3551 case CTL_11B_EXT:
3552 targetPowerCckExt.tPow2x[0] = (u8)min(
3553 (u16)targetPowerCckExt.tPow2x[0],
3554 minCtlPower);
3555 break;
3556 case CTL_11A_EXT:
3557 case CTL_11G_EXT:
3558 targetPowerOfdmExt.tPow2x[0] = (u8)min(
3559 (u16)targetPowerOfdmExt.tPow2x[0],
3560 minCtlPower);
3561 break;
3562 case CTL_5GHT40:
3563 case CTL_2GHT40:
3564 for (i = 0;
3565 i < ARRAY_SIZE(targetPowerHt40.tPow2x);
3566 i++) {
3567 targetPowerHt40.tPow2x[i] = (u8)min(
3568 (u16)targetPowerHt40.tPow2x[i],
3569 minCtlPower);
3570 }
3571 break;
3572 default:
3573 break;
3574 }
3575 }
3576
3577 ratesArray[rate6mb] =
3578 ratesArray[rate9mb] =
3579 ratesArray[rate12mb] =
3580 ratesArray[rate18mb] =
3581 ratesArray[rate24mb] =
3582 targetPowerOfdm.tPow2x[0];
3583
3584 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
3585 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
3586 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
3587 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
3588
3589 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
3590 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
3591
3592 if (IS_CHAN_2GHZ(chan)) {
3593 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
3594 ratesArray[rate2s] = ratesArray[rate2l] =
3595 targetPowerCck.tPow2x[1];
3596 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
3597 targetPowerCck.tPow2x[2];
3598 ratesArray[rate11s] = ratesArray[rate11l] =
3599 targetPowerCck.tPow2x[3];
3600 }
3601 if (IS_CHAN_HT40(chan)) {
3602 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
3603 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
3604
3605 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
3606 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
3607 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
3608 if (IS_CHAN_2GHZ(chan))
3609 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
3610 }
3611
3612#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
3613#undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
3614}
3615
3616static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
3617 struct ath9k_channel *chan, u16 cfgCtl,
3618 u8 twiceAntennaReduction,
3619 u8 twiceMaxRegulatoryPower,
3620 u8 powerLimit)
3621{
3622#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
3623#define INCREASE_MAXPOW_BY_THREE_CHAIN 10
3624
3625 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
3626 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
3627 int16_t ratesArray[Ar5416RateSize];
3628 int16_t txPowerIndexOffset = 0;
3629 u8 ht40PowerIncForPdadc = 2;
3630 int i;
3631
3632 memset(ratesArray, 0, sizeof(ratesArray));
3633
3634 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
3635 AR9287_EEP_MINOR_VER_2)
3636 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
3637
3638 ath9k_hw_set_AR9287_power_per_rate_table(ah, chan,
3639 &ratesArray[0], cfgCtl,
3640 twiceAntennaReduction,
3641 twiceMaxRegulatoryPower,
3642 powerLimit);
3643
3644 ath9k_hw_set_AR9287_power_cal_table(ah, chan, &txPowerIndexOffset);
3645
3646 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
3647 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
3648 if (ratesArray[i] > AR9287_MAX_RATE_POWER)
3649 ratesArray[i] = AR9287_MAX_RATE_POWER;
3650 }
3651
3652 if (AR_SREV_9280_10_OR_LATER(ah)) {
3653 for (i = 0; i < Ar5416RateSize; i++)
3654 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
3655 }
3656
3657 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
3658 ATH9K_POW_SM(ratesArray[rate18mb], 24)
3659 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
3660 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
3661 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
3662
3663 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
3664 ATH9K_POW_SM(ratesArray[rate54mb], 24)
3665 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
3666 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
3667 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
3668
3669 if (IS_CHAN_2GHZ(chan)) {
3670 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
3671 ATH9K_POW_SM(ratesArray[rate2s], 24)
3672 | ATH9K_POW_SM(ratesArray[rate2l], 16)
3673 | ATH9K_POW_SM(ratesArray[rateXr], 8)
3674 | ATH9K_POW_SM(ratesArray[rate1l], 0));
3675 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
3676 ATH9K_POW_SM(ratesArray[rate11s], 24)
3677 | ATH9K_POW_SM(ratesArray[rate11l], 16)
3678 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
3679 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
3680 }
3681
3682 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
3683 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
3684 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
3685 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
3686 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
3687
3688 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
3689 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
3690 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
3691 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
3692 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
3693
3694 if (IS_CHAN_HT40(chan)) {
3695 if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
3696 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
3697 ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
3698 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
3699 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
3700 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
3701
3702 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
3703 ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
3704 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
3705 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
3706 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
3707 } else {
3708 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
3709 ATH9K_POW_SM(ratesArray[rateHt40_3] +
3710 ht40PowerIncForPdadc, 24)
3711 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
3712 ht40PowerIncForPdadc, 16)
3713 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
3714 ht40PowerIncForPdadc, 8)
3715 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
3716 ht40PowerIncForPdadc, 0));
3717
3718 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
3719 ATH9K_POW_SM(ratesArray[rateHt40_7] +
3720 ht40PowerIncForPdadc, 24)
3721 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
3722 ht40PowerIncForPdadc, 16)
3723 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
3724 ht40PowerIncForPdadc, 8)
3725 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
3726 ht40PowerIncForPdadc, 0));
3727 }
3728
3729 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
3730 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
3731 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
3732 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
3733 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
3734 }
3735
3736 if (IS_CHAN_2GHZ(chan))
3737 i = rate1l;
3738 else
3739 i = rate6mb;
3740
3741 if (AR_SREV_9280_10_OR_LATER(ah))
3742 ah->regulatory.max_power_level =
3743 ratesArray[i] + AR9287_PWR_TABLE_OFFSET_DB * 2;
3744 else
3745 ah->regulatory.max_power_level = ratesArray[i];
3746
3747 switch (ar5416_get_ntxchains(ah->txchainmask)) {
3748 case 1:
3749 break;
3750 case 2:
3751 ah->regulatory.max_power_level +=
3752 INCREASE_MAXPOW_BY_TWO_CHAIN;
3753 break;
3754 case 3:
3755 ah->regulatory.max_power_level +=
3756 INCREASE_MAXPOW_BY_THREE_CHAIN;
3757 break;
3758 default:
3759 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
3760 "Invalid chainmask configuration\n");
3761 break;
3762 }
3763}
3764
3765static void ath9k_hw_AR9287_set_addac(struct ath_hw *ah,
3766 struct ath9k_channel *chan)
3767{
3768}
3769
3770static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
3771 struct ath9k_channel *chan)
3772{
3773 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
3774 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
3775 u16 antWrites[AR9287_ANT_16S];
3776 u32 regChainOffset;
3777 u8 txRxAttenLocal;
3778 int i, j, offset_num;
3779
3780 pModal = &eep->modalHeader;
3781
3782 antWrites[0] = (u16)((pModal->antCtrlCommon >> 28) & 0xF);
3783 antWrites[1] = (u16)((pModal->antCtrlCommon >> 24) & 0xF);
3784 antWrites[2] = (u16)((pModal->antCtrlCommon >> 20) & 0xF);
3785 antWrites[3] = (u16)((pModal->antCtrlCommon >> 16) & 0xF);
3786 antWrites[4] = (u16)((pModal->antCtrlCommon >> 12) & 0xF);
3787 antWrites[5] = (u16)((pModal->antCtrlCommon >> 8) & 0xF);
3788 antWrites[6] = (u16)((pModal->antCtrlCommon >> 4) & 0xF);
3789 antWrites[7] = (u16)(pModal->antCtrlCommon & 0xF);
3790
3791 offset_num = 8;
3792
3793 for (i = 0, j = offset_num; i < AR9287_MAX_CHAINS; i++) {
3794 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 28) & 0xf);
3795 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 10) & 0x3);
3796 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 8) & 0x3);
3797 antWrites[j++] = 0;
3798 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 6) & 0x3);
3799 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 4) & 0x3);
3800 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 2) & 0x3);
3801 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
3802 }
3803
3804 REG_WRITE(ah, AR_PHY_SWITCH_COM,
3805 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
3806
3807 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
3808 regChainOffset = i * 0x1000;
3809
3810 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
3811 pModal->antCtrlChain[i]);
3812
3813 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
3814 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
3815 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
3816 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
3817 SM(pModal->iqCalICh[i],
3818 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
3819 SM(pModal->iqCalQCh[i],
3820 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
3821
3822 txRxAttenLocal = pModal->txRxAttenCh[i];
3823
3824 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
3825 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
3826 pModal->bswMargin[i]);
3827 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
3828 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
3829 pModal->bswAtten[i]);
3830 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
3831 AR9280_PHY_RXGAIN_TXRX_ATTEN,
3832 txRxAttenLocal);
3833 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
3834 AR9280_PHY_RXGAIN_TXRX_MARGIN,
3835 pModal->rxTxMarginCh[i]);
3836 }
3837
3838
3839 if (IS_CHAN_HT40(chan))
3840 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
3841 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
3842 else
3843 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
3844 AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
3845
3846 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
3847 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
3848
3849 REG_WRITE(ah, AR_PHY_RF_CTL4,
3850 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
3851 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
3852 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
3853 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
3854
3855 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
3856 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
3857
3858 REG_RMW_FIELD(ah, AR_PHY_CCA,
3859 AR9280_PHY_CCA_THRESH62, pModal->thresh62);
3860 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
3861 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
3862
3863 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, AR9287_AN_RF2G3_DB1,
3864 AR9287_AN_RF2G3_DB1_S, pModal->db1);
3865 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, AR9287_AN_RF2G3_DB2,
3866 AR9287_AN_RF2G3_DB2_S, pModal->db2);
3867 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0,
3868 AR9287_AN_RF2G3_OB_CCK,
3869 AR9287_AN_RF2G3_OB_CCK_S, pModal->ob_cck);
3870 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0,
3871 AR9287_AN_RF2G3_OB_PSK,
3872 AR9287_AN_RF2G3_OB_PSK_S, pModal->ob_psk);
3873 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0,
3874 AR9287_AN_RF2G3_OB_QAM,
3875 AR9287_AN_RF2G3_OB_QAM_S, pModal->ob_qam);
3876 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0,
3877 AR9287_AN_RF2G3_OB_PAL_OFF,
3878 AR9287_AN_RF2G3_OB_PAL_OFF_S,
3879 pModal->ob_pal_off);
3880
3881 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1,
3882 AR9287_AN_RF2G3_DB1, AR9287_AN_RF2G3_DB1_S,
3883 pModal->db1);
3884 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, AR9287_AN_RF2G3_DB2,
3885 AR9287_AN_RF2G3_DB2_S, pModal->db2);
3886 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1,
3887 AR9287_AN_RF2G3_OB_CCK,
3888 AR9287_AN_RF2G3_OB_CCK_S, pModal->ob_cck);
3889 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1,
3890 AR9287_AN_RF2G3_OB_PSK,
3891 AR9287_AN_RF2G3_OB_PSK_S, pModal->ob_psk);
3892 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1,
3893 AR9287_AN_RF2G3_OB_QAM,
3894 AR9287_AN_RF2G3_OB_QAM_S, pModal->ob_qam);
3895 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1,
3896 AR9287_AN_RF2G3_OB_PAL_OFF,
3897 AR9287_AN_RF2G3_OB_PAL_OFF_S,
3898 pModal->ob_pal_off);
3899
3900 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
3901 AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);
3902 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
3903 AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn);
3904
3905 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2,
3906 AR9287_AN_TOP2_XPABIAS_LVL,
3907 AR9287_AN_TOP2_XPABIAS_LVL_S,
3908 pModal->xpaBiasLvl);
3909}
3910
3911static u8 ath9k_hw_AR9287_get_num_ant_config(struct ath_hw *ah,
3912 enum ieee80211_band freq_band)
3913{
3914 return 1;
3915}
3916
3917static u16 ath9k_hw_AR9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
3918 struct ath9k_channel *chan)
3919{
3920 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
3921 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
3922
3923 return pModal->antCtrlCommon & 0xFFFF;
3924}
3925
3926static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
3927 u16 i, bool is2GHz)
3928{
3929#define EEP_MAP9287_SPURCHAN \
3930 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
3931 u16 spur_val = AR_NO_SPUR;
3932
3933 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
3934 "Getting spur idx %d is2Ghz. %d val %x\n",
3935 i, is2GHz, ah->config.spurchans[i][is2GHz]);
3936
3937 switch (ah->config.spurmode) {
3938 case SPUR_DISABLE:
3939 break;
3940 case SPUR_ENABLE_IOCTL:
3941 spur_val = ah->config.spurchans[i][is2GHz];
3942 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
3943 "Getting spur val from new loc. %d\n", spur_val);
3944 break;
3945 case SPUR_ENABLE_EEPROM:
3946 spur_val = EEP_MAP9287_SPURCHAN;
3947 break;
3948 }
3949
3950 return spur_val;
3951
3952#undef EEP_MAP9287_SPURCHAN
3953}
3954
3955static struct eeprom_ops eep_AR9287_ops = {
3956 .check_eeprom = ath9k_hw_AR9287_check_eeprom,
3957 .get_eeprom = ath9k_hw_AR9287_get_eeprom,
3958 .fill_eeprom = ath9k_hw_AR9287_fill_eeprom,
3959 .get_eeprom_ver = ath9k_hw_AR9287_get_eeprom_ver,
3960 .get_eeprom_rev = ath9k_hw_AR9287_get_eeprom_rev,
3961 .get_num_ant_config = ath9k_hw_AR9287_get_num_ant_config,
3962 .get_eeprom_antenna_cfg = ath9k_hw_AR9287_get_eeprom_antenna_cfg,
3963 .set_board_values = ath9k_hw_AR9287_set_board_values,
3964 .set_addac = ath9k_hw_AR9287_set_addac,
3965 .set_txpower = ath9k_hw_AR9287_set_txpower,
3966 .get_spur_channel = ath9k_hw_AR9287_get_spur_channel
3967};
3968
3969int ath9k_hw_eeprom_init(struct ath_hw *ah) 257int ath9k_hw_eeprom_init(struct ath_hw *ah)
3970{ 258{
3971 int status; 259 int status;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index a6447096fd14..7d825b6d9c8c 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -656,10 +656,39 @@ struct eeprom_ops {
656 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); 656 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
657}; 657};
658 658
659void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
660 u32 shift, u32 val);
661int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
662 int16_t targetLeft,
663 int16_t targetRight);
664bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
665 u16 *indexL, u16 *indexR);
666bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data);
667void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
668 u8 *pVpdList, u16 numIntercepts,
669 u8 *pRetVpdList);
670void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
671 struct ath9k_channel *chan,
672 struct cal_target_power_leg *powInfo,
673 u16 numChannels,
674 struct cal_target_power_leg *pNewPower,
675 u16 numRates, bool isExtTarget);
676void ath9k_hw_get_target_powers(struct ath_hw *ah,
677 struct ath9k_channel *chan,
678 struct cal_target_power_ht *powInfo,
679 u16 numChannels,
680 struct cal_target_power_ht *pNewPower,
681 u16 numRates, bool isHt40Target);
682u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
683 bool is2GHz, int num_band_edges);
684int ath9k_hw_eeprom_init(struct ath_hw *ah);
685
659#define ar5416_get_ntxchains(_txchainmask) \ 686#define ar5416_get_ntxchains(_txchainmask) \
660 (((_txchainmask >> 2) & 1) + \ 687 (((_txchainmask >> 2) & 1) + \
661 ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 688 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
662 689
663int ath9k_hw_eeprom_init(struct ath_hw *ah); 690extern const struct eeprom_ops eep_def_ops;
691extern const struct eeprom_ops eep_4k_ops;
692extern const struct eeprom_ops eep_AR9287_ops;
664 693
665#endif /* EEPROM_H */ 694#endif /* EEPROM_H */
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
new file mode 100644
index 000000000000..111f4d72092b
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -0,0 +1,1181 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "ath9k.h"
18
19static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
20{
21 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
22}
23
24static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
25{
26 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
27}
28
29static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
30{
31#define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
32 u16 *eep_data = (u16 *)&ah->eeprom.map4k;
33 int addr, eep_start_loc = 0;
34
35 eep_start_loc = 64;
36
37 if (!ath9k_hw_use_flash(ah)) {
38 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
39 "Reading from EEPROM, not flash\n");
40 }
41
42 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
44 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
45 "Unable to read eeprom region \n");
46 return false;
47 }
48 eep_data++;
49 }
50
51 return true;
52#undef SIZE_EEPROM_4K
53}
54
55static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
56{
57#define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
58 struct ar5416_eeprom_4k *eep =
59 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
60 u16 *eepdata, temp, magic, magic2;
61 u32 sum = 0, el;
62 bool need_swap = false;
63 int i, addr;
64
65
66 if (!ath9k_hw_use_flash(ah)) {
67 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
68 &magic)) {
69 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
70 "Reading Magic # failed\n");
71 return false;
72 }
73
74 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
75 "Read Magic = 0x%04X\n", magic);
76
77 if (magic != AR5416_EEPROM_MAGIC) {
78 magic2 = swab16(magic);
79
80 if (magic2 == AR5416_EEPROM_MAGIC) {
81 need_swap = true;
82 eepdata = (u16 *) (&ah->eeprom);
83
84 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
85 temp = swab16(*eepdata);
86 *eepdata = temp;
87 eepdata++;
88 }
89 } else {
90 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
91 "Invalid EEPROM Magic. "
92 "endianness mismatch.\n");
93 return -EINVAL;
94 }
95 }
96 }
97
98 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
99 need_swap ? "True" : "False");
100
101 if (need_swap)
102 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
103 else
104 el = ah->eeprom.map4k.baseEepHeader.length;
105
106 if (el > sizeof(struct ar5416_eeprom_4k))
107 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
108 else
109 el = el / sizeof(u16);
110
111 eepdata = (u16 *)(&ah->eeprom);
112
113 for (i = 0; i < el; i++)
114 sum ^= *eepdata++;
115
116 if (need_swap) {
117 u32 integer;
118 u16 word;
119
120 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
121 "EEPROM Endianness is not native.. Changing\n");
122
123 word = swab16(eep->baseEepHeader.length);
124 eep->baseEepHeader.length = word;
125
126 word = swab16(eep->baseEepHeader.checksum);
127 eep->baseEepHeader.checksum = word;
128
129 word = swab16(eep->baseEepHeader.version);
130 eep->baseEepHeader.version = word;
131
132 word = swab16(eep->baseEepHeader.regDmn[0]);
133 eep->baseEepHeader.regDmn[0] = word;
134
135 word = swab16(eep->baseEepHeader.regDmn[1]);
136 eep->baseEepHeader.regDmn[1] = word;
137
138 word = swab16(eep->baseEepHeader.rfSilent);
139 eep->baseEepHeader.rfSilent = word;
140
141 word = swab16(eep->baseEepHeader.blueToothOptions);
142 eep->baseEepHeader.blueToothOptions = word;
143
144 word = swab16(eep->baseEepHeader.deviceCap);
145 eep->baseEepHeader.deviceCap = word;
146
147 integer = swab32(eep->modalHeader.antCtrlCommon);
148 eep->modalHeader.antCtrlCommon = integer;
149
150 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
151 integer = swab32(eep->modalHeader.antCtrlChain[i]);
152 eep->modalHeader.antCtrlChain[i] = integer;
153 }
154
155 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
156 word = swab16(eep->modalHeader.spurChans[i].spurChan);
157 eep->modalHeader.spurChans[i].spurChan = word;
158 }
159 }
160
161 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
162 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
163 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
164 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
165 sum, ah->eep_ops->get_eeprom_ver(ah));
166 return -EINVAL;
167 }
168
169 return 0;
170#undef EEPROM_4K_SIZE
171}
172
173static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
174 enum eeprom_param param)
175{
176 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
177 struct modal_eep_4k_header *pModal = &eep->modalHeader;
178 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
179
180 switch (param) {
181 case EEP_NFTHRESH_2:
182 return pModal->noiseFloorThreshCh[0];
183 case AR_EEPROM_MAC(0):
184 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
185 case AR_EEPROM_MAC(1):
186 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
187 case AR_EEPROM_MAC(2):
188 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
189 case EEP_REG_0:
190 return pBase->regDmn[0];
191 case EEP_REG_1:
192 return pBase->regDmn[1];
193 case EEP_OP_CAP:
194 return pBase->deviceCap;
195 case EEP_OP_MODE:
196 return pBase->opCapFlags;
197 case EEP_RF_SILENT:
198 return pBase->rfSilent;
199 case EEP_OB_2:
200 return pModal->ob_01;
201 case EEP_DB_2:
202 return pModal->db1_01;
203 case EEP_MINOR_REV:
204 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
205 case EEP_TX_MASK:
206 return pBase->txMask;
207 case EEP_RX_MASK:
208 return pBase->rxMask;
209 case EEP_FRAC_N_5G:
210 return 0;
211 default:
212 return 0;
213 }
214}
215
216static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
217 struct ath9k_channel *chan,
218 struct cal_data_per_freq_4k *pRawDataSet,
219 u8 *bChans, u16 availPiers,
220 u16 tPdGainOverlap, int16_t *pMinCalPower,
221 u16 *pPdGainBoundaries, u8 *pPDADCValues,
222 u16 numXpdGains)
223{
224#define TMP_VAL_VPD_TABLE \
225 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
226 int i, j, k;
227 int16_t ss;
228 u16 idxL = 0, idxR = 0, numPiers;
229 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
230 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
231 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
232 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
233 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
234 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
235
236 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
237 u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
238 u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
239 int16_t vpdStep;
240 int16_t tmpVal;
241 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
242 bool match;
243 int16_t minDelta = 0;
244 struct chan_centers centers;
245#define PD_GAIN_BOUNDARY_DEFAULT 58;
246
247 ath9k_hw_get_channel_centers(ah, chan, &centers);
248
249 for (numPiers = 0; numPiers < availPiers; numPiers++) {
250 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
251 break;
252 }
253
254 match = ath9k_hw_get_lower_upper_index(
255 (u8)FREQ2FBIN(centers.synth_center,
256 IS_CHAN_2GHZ(chan)), bChans, numPiers,
257 &idxL, &idxR);
258
259 if (match) {
260 for (i = 0; i < numXpdGains; i++) {
261 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
262 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
263 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
264 pRawDataSet[idxL].pwrPdg[i],
265 pRawDataSet[idxL].vpdPdg[i],
266 AR5416_EEP4K_PD_GAIN_ICEPTS,
267 vpdTableI[i]);
268 }
269 } else {
270 for (i = 0; i < numXpdGains; i++) {
271 pVpdL = pRawDataSet[idxL].vpdPdg[i];
272 pPwrL = pRawDataSet[idxL].pwrPdg[i];
273 pVpdR = pRawDataSet[idxR].vpdPdg[i];
274 pPwrR = pRawDataSet[idxR].pwrPdg[i];
275
276 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
277
278 maxPwrT4[i] =
279 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
280 pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
281
282
283 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
284 pPwrL, pVpdL,
285 AR5416_EEP4K_PD_GAIN_ICEPTS,
286 vpdTableL[i]);
287 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
288 pPwrR, pVpdR,
289 AR5416_EEP4K_PD_GAIN_ICEPTS,
290 vpdTableR[i]);
291
292 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
293 vpdTableI[i][j] =
294 (u8)(ath9k_hw_interpolate((u16)
295 FREQ2FBIN(centers.
296 synth_center,
297 IS_CHAN_2GHZ
298 (chan)),
299 bChans[idxL], bChans[idxR],
300 vpdTableL[i][j], vpdTableR[i][j]));
301 }
302 }
303 }
304
305 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
306
307 k = 0;
308
309 for (i = 0; i < numXpdGains; i++) {
310 if (i == (numXpdGains - 1))
311 pPdGainBoundaries[i] =
312 (u16)(maxPwrT4[i] / 2);
313 else
314 pPdGainBoundaries[i] =
315 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
316
317 pPdGainBoundaries[i] =
318 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
319
320 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
321 minDelta = pPdGainBoundaries[0] - 23;
322 pPdGainBoundaries[0] = 23;
323 } else {
324 minDelta = 0;
325 }
326
327 if (i == 0) {
328 if (AR_SREV_9280_10_OR_LATER(ah))
329 ss = (int16_t)(0 - (minPwrT4[i] / 2));
330 else
331 ss = 0;
332 } else {
333 ss = (int16_t)((pPdGainBoundaries[i - 1] -
334 (minPwrT4[i] / 2)) -
335 tPdGainOverlap + 1 + minDelta);
336 }
337 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
338 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
339
340 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
341 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
342 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
343 ss++;
344 }
345
346 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
347 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
348 (minPwrT4[i] / 2));
349 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
350 tgtIndex : sizeCurrVpdTable;
351
352 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
353 pPDADCValues[k++] = vpdTableI[i][ss++];
354
355 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
356 vpdTableI[i][sizeCurrVpdTable - 2]);
357 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
358
359 if (tgtIndex >= maxIndex) {
360 while ((ss <= tgtIndex) &&
361 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
362 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
363 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
364 255 : tmpVal);
365 ss++;
366 }
367 }
368 }
369
370 while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
371 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
372 i++;
373 }
374
375 while (k < AR5416_NUM_PDADC_VALUES) {
376 pPDADCValues[k] = pPDADCValues[k - 1];
377 k++;
378 }
379
380 return;
381#undef TMP_VAL_VPD_TABLE
382}
383
384static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
385 struct ath9k_channel *chan,
386 int16_t *pTxPowerIndexOffset)
387{
388 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
389 struct cal_data_per_freq_4k *pRawDataset;
390 u8 *pCalBChans = NULL;
391 u16 pdGainOverlap_t2;
392 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
393 u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
394 u16 numPiers, i, j;
395 int16_t tMinCalPower;
396 u16 numXpdGain, xpdMask;
397 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
398 u32 reg32, regOffset, regChainOffset;
399
400 xpdMask = pEepData->modalHeader.xpdGain;
401
402 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
403 AR5416_EEP_MINOR_VER_2) {
404 pdGainOverlap_t2 =
405 pEepData->modalHeader.pdGainOverlap;
406 } else {
407 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
408 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
409 }
410
411 pCalBChans = pEepData->calFreqPier2G;
412 numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
413
414 numXpdGain = 0;
415
416 for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
417 if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
418 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
419 break;
420 xpdGainValues[numXpdGain] =
421 (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
422 numXpdGain++;
423 }
424 }
425
426 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
427 (numXpdGain - 1) & 0x3);
428 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
429 xpdGainValues[0]);
430 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
431 xpdGainValues[1]);
432 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
433
434 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
435 if (AR_SREV_5416_20_OR_LATER(ah) &&
436 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
437 (i != 0)) {
438 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
439 } else
440 regChainOffset = i * 0x1000;
441
442 if (pEepData->baseEepHeader.txMask & (1 << i)) {
443 pRawDataset = pEepData->calPierData2G[i];
444
445 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
446 pRawDataset, pCalBChans,
447 numPiers, pdGainOverlap_t2,
448 &tMinCalPower, gainBoundaries,
449 pdadcValues, numXpdGain);
450
451 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
452 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
453 SM(pdGainOverlap_t2,
454 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
455 | SM(gainBoundaries[0],
456 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
457 | SM(gainBoundaries[1],
458 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
459 | SM(gainBoundaries[2],
460 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
461 | SM(gainBoundaries[3],
462 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
463 }
464
465 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
466 for (j = 0; j < 32; j++) {
467 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
468 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
469 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
470 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
471 REG_WRITE(ah, regOffset, reg32);
472
473 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
474 "PDADC (%d,%4x): %4.4x %8.8x\n",
475 i, regChainOffset, regOffset,
476 reg32);
477 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
478 "PDADC: Chain %d | "
479 "PDADC %3d Value %3d | "
480 "PDADC %3d Value %3d | "
481 "PDADC %3d Value %3d | "
482 "PDADC %3d Value %3d |\n",
483 i, 4 * j, pdadcValues[4 * j],
484 4 * j + 1, pdadcValues[4 * j + 1],
485 4 * j + 2, pdadcValues[4 * j + 2],
486 4 * j + 3,
487 pdadcValues[4 * j + 3]);
488
489 regOffset += 4;
490 }
491 }
492 }
493
494 *pTxPowerIndexOffset = 0;
495}
496
497static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
498 struct ath9k_channel *chan,
499 int16_t *ratesArray,
500 u16 cfgCtl,
501 u16 AntennaReduction,
502 u16 twiceMaxRegulatoryPower,
503 u16 powerLimit)
504{
505 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
506 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
507 static const u16 tpScaleReductionTable[5] =
508 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
509
510 int i;
511 int16_t twiceLargestAntenna;
512 struct cal_ctl_data_4k *rep;
513 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
514 0, { 0, 0, 0, 0}
515 };
516 struct cal_target_power_leg targetPowerOfdmExt = {
517 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
518 0, { 0, 0, 0, 0 }
519 };
520 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
521 0, {0, 0, 0, 0}
522 };
523 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
524 u16 ctlModesFor11g[] =
525 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
526 CTL_2GHT40
527 };
528 u16 numCtlModes, *pCtlMode, ctlMode, freq;
529 struct chan_centers centers;
530 int tx_chainmask;
531 u16 twiceMinEdgePower;
532
533 tx_chainmask = ah->txchainmask;
534
535 ath9k_hw_get_channel_centers(ah, chan, &centers);
536
537 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
538
539 twiceLargestAntenna = (int16_t)min(AntennaReduction -
540 twiceLargestAntenna, 0);
541
542 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
543
544 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
545 maxRegAllowedPower -=
546 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
547 }
548
549 scaledPower = min(powerLimit, maxRegAllowedPower);
550 scaledPower = max((u16)0, scaledPower);
551
552 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
553 pCtlMode = ctlModesFor11g;
554
555 ath9k_hw_get_legacy_target_powers(ah, chan,
556 pEepData->calTargetPowerCck,
557 AR5416_NUM_2G_CCK_TARGET_POWERS,
558 &targetPowerCck, 4, false);
559 ath9k_hw_get_legacy_target_powers(ah, chan,
560 pEepData->calTargetPower2G,
561 AR5416_NUM_2G_20_TARGET_POWERS,
562 &targetPowerOfdm, 4, false);
563 ath9k_hw_get_target_powers(ah, chan,
564 pEepData->calTargetPower2GHT20,
565 AR5416_NUM_2G_20_TARGET_POWERS,
566 &targetPowerHt20, 8, false);
567
568 if (IS_CHAN_HT40(chan)) {
569 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
570 ath9k_hw_get_target_powers(ah, chan,
571 pEepData->calTargetPower2GHT40,
572 AR5416_NUM_2G_40_TARGET_POWERS,
573 &targetPowerHt40, 8, true);
574 ath9k_hw_get_legacy_target_powers(ah, chan,
575 pEepData->calTargetPowerCck,
576 AR5416_NUM_2G_CCK_TARGET_POWERS,
577 &targetPowerCckExt, 4, true);
578 ath9k_hw_get_legacy_target_powers(ah, chan,
579 pEepData->calTargetPower2G,
580 AR5416_NUM_2G_20_TARGET_POWERS,
581 &targetPowerOfdmExt, 4, true);
582 }
583
584 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
585 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
586 (pCtlMode[ctlMode] == CTL_2GHT40);
587 if (isHt40CtlMode)
588 freq = centers.synth_center;
589 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
590 freq = centers.ext_center;
591 else
592 freq = centers.ctl_center;
593
594 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
595 ah->eep_ops->get_eeprom_rev(ah) <= 2)
596 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
597
598 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
599 pEepData->ctlIndex[i]; i++) {
600 if ((((cfgCtl & ~CTL_MODE_M) |
601 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
602 pEepData->ctlIndex[i]) ||
603 (((cfgCtl & ~CTL_MODE_M) |
604 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
605 ((pEepData->ctlIndex[i] & CTL_MODE_M) |
606 SD_NO_CTL))) {
607 rep = &(pEepData->ctlData[i]);
608
609 twiceMinEdgePower =
610 ath9k_hw_get_max_edge_power(freq,
611 rep->ctlEdges[ar5416_get_ntxchains
612 (tx_chainmask) - 1],
613 IS_CHAN_2GHZ(chan),
614 AR5416_EEP4K_NUM_BAND_EDGES);
615
616 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
617 twiceMaxEdgePower =
618 min(twiceMaxEdgePower,
619 twiceMinEdgePower);
620 } else {
621 twiceMaxEdgePower = twiceMinEdgePower;
622 break;
623 }
624 }
625 }
626
627 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
628
629 switch (pCtlMode[ctlMode]) {
630 case CTL_11B:
631 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
632 i++) {
633 targetPowerCck.tPow2x[i] =
634 min((u16)targetPowerCck.tPow2x[i],
635 minCtlPower);
636 }
637 break;
638 case CTL_11G:
639 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
640 i++) {
641 targetPowerOfdm.tPow2x[i] =
642 min((u16)targetPowerOfdm.tPow2x[i],
643 minCtlPower);
644 }
645 break;
646 case CTL_2GHT20:
647 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
648 i++) {
649 targetPowerHt20.tPow2x[i] =
650 min((u16)targetPowerHt20.tPow2x[i],
651 minCtlPower);
652 }
653 break;
654 case CTL_11B_EXT:
655 targetPowerCckExt.tPow2x[0] = min((u16)
656 targetPowerCckExt.tPow2x[0],
657 minCtlPower);
658 break;
659 case CTL_11G_EXT:
660 targetPowerOfdmExt.tPow2x[0] = min((u16)
661 targetPowerOfdmExt.tPow2x[0],
662 minCtlPower);
663 break;
664 case CTL_2GHT40:
665 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
666 i++) {
667 targetPowerHt40.tPow2x[i] =
668 min((u16)targetPowerHt40.tPow2x[i],
669 minCtlPower);
670 }
671 break;
672 default:
673 break;
674 }
675 }
676
677 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
678 ratesArray[rate18mb] = ratesArray[rate24mb] =
679 targetPowerOfdm.tPow2x[0];
680 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
681 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
682 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
683 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
684
685 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
686 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
687
688 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
689 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
690 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
691 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
692
693 if (IS_CHAN_HT40(chan)) {
694 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
695 ratesArray[rateHt40_0 + i] =
696 targetPowerHt40.tPow2x[i];
697 }
698 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
699 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
700 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
701 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
702 }
703}
704
705static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
706 struct ath9k_channel *chan,
707 u16 cfgCtl,
708 u8 twiceAntennaReduction,
709 u8 twiceMaxRegulatoryPower,
710 u8 powerLimit)
711{
712 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
713 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
714 int16_t ratesArray[Ar5416RateSize];
715 int16_t txPowerIndexOffset = 0;
716 u8 ht40PowerIncForPdadc = 2;
717 int i;
718
719 memset(ratesArray, 0, sizeof(ratesArray));
720
721 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
722 AR5416_EEP_MINOR_VER_2) {
723 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
724 }
725
726 ath9k_hw_set_4k_power_per_rate_table(ah, chan,
727 &ratesArray[0], cfgCtl,
728 twiceAntennaReduction,
729 twiceMaxRegulatoryPower,
730 powerLimit);
731
732 ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
733
734 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
735 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
736 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
737 ratesArray[i] = AR5416_MAX_RATE_POWER;
738 }
739
740 if (AR_SREV_9280_10_OR_LATER(ah)) {
741 for (i = 0; i < Ar5416RateSize; i++)
742 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
743 }
744
745 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
746 ATH9K_POW_SM(ratesArray[rate18mb], 24)
747 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
748 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
749 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
750 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
751 ATH9K_POW_SM(ratesArray[rate54mb], 24)
752 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
753 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
754 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
755
756 if (IS_CHAN_2GHZ(chan)) {
757 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
758 ATH9K_POW_SM(ratesArray[rate2s], 24)
759 | ATH9K_POW_SM(ratesArray[rate2l], 16)
760 | ATH9K_POW_SM(ratesArray[rateXr], 8)
761 | ATH9K_POW_SM(ratesArray[rate1l], 0));
762 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
763 ATH9K_POW_SM(ratesArray[rate11s], 24)
764 | ATH9K_POW_SM(ratesArray[rate11l], 16)
765 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
766 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
767 }
768
769 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
770 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
771 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
772 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
773 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
774 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
775 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
776 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
777 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
778 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
779
780 if (IS_CHAN_HT40(chan)) {
781 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
782 ATH9K_POW_SM(ratesArray[rateHt40_3] +
783 ht40PowerIncForPdadc, 24)
784 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
785 ht40PowerIncForPdadc, 16)
786 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
787 ht40PowerIncForPdadc, 8)
788 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
789 ht40PowerIncForPdadc, 0));
790 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
791 ATH9K_POW_SM(ratesArray[rateHt40_7] +
792 ht40PowerIncForPdadc, 24)
793 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
794 ht40PowerIncForPdadc, 16)
795 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
796 ht40PowerIncForPdadc, 8)
797 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
798 ht40PowerIncForPdadc, 0));
799
800 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
801 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
802 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
803 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
804 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
805 }
806
807 i = rate6mb;
808
809 if (IS_CHAN_HT40(chan))
810 i = rateHt40_0;
811 else if (IS_CHAN_HT20(chan))
812 i = rateHt20_0;
813
814 if (AR_SREV_9280_10_OR_LATER(ah))
815 ah->regulatory.max_power_level =
816 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
817 else
818 ah->regulatory.max_power_level = ratesArray[i];
819
820}
821
822static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
823 struct ath9k_channel *chan)
824{
825 struct modal_eep_4k_header *pModal;
826 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
827 u8 biaslevel;
828
829 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
830 return;
831
832 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
833 return;
834
835 pModal = &eep->modalHeader;
836
837 if (pModal->xpaBiasLvl != 0xff) {
838 biaslevel = pModal->xpaBiasLvl;
839 INI_RA(&ah->iniAddac, 7, 1) =
840 (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
841 }
842}
843
844static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
845 struct modal_eep_4k_header *pModal,
846 struct ar5416_eeprom_4k *eep,
847 u8 txRxAttenLocal, int regChainOffset)
848{
849 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
850 pModal->antCtrlChain[0]);
851
852 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
853 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
854 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
855 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
856 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
857 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
858
859 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
860 AR5416_EEP_MINOR_VER_3) {
861 txRxAttenLocal = pModal->txRxAttenCh[0];
862
863 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
864 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
865 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
866 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
867 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
868 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
869 pModal->xatten2Margin[0]);
870 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
871 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
872
873 /* Set the block 1 value to block 0 value */
874 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
875 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
876 pModal->bswMargin[0]);
877 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
878 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
879 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
880 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
881 pModal->xatten2Margin[0]);
882 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
883 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
884 pModal->xatten2Db[0]);
885 }
886
887 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
888 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
889 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
890 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
891
892 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
893 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
894 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
895 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
896
897 if (AR_SREV_9285_11(ah))
898 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
899}
900
901/*
902 * Read EEPROM header info and program the device for correct operation
903 * given the channel value.
904 */
905static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
906 struct ath9k_channel *chan)
907{
908 struct modal_eep_4k_header *pModal;
909 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
910 u8 txRxAttenLocal;
911 u8 ob[5], db1[5], db2[5];
912 u8 ant_div_control1, ant_div_control2;
913 u32 regVal;
914
915 pModal = &eep->modalHeader;
916 txRxAttenLocal = 23;
917
918 REG_WRITE(ah, AR_PHY_SWITCH_COM,
919 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
920
921 /* Single chain for 4K EEPROM*/
922 ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal, 0);
923
924 /* Initialize Ant Diversity settings from EEPROM */
925 if (pModal->version >= 3) {
926 ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf);
927 ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf);
928 regVal = REG_READ(ah, 0x99ac);
929 regVal &= (~(0x7f000000));
930 regVal |= ((ant_div_control1 & 0x1) << 24);
931 regVal |= (((ant_div_control1 >> 1) & 0x1) << 29);
932 regVal |= (((ant_div_control1 >> 2) & 0x1) << 30);
933 regVal |= ((ant_div_control2 & 0x3) << 25);
934 regVal |= (((ant_div_control2 >> 2) & 0x3) << 27);
935 REG_WRITE(ah, 0x99ac, regVal);
936 regVal = REG_READ(ah, 0x99ac);
937 regVal = REG_READ(ah, 0xa208);
938 regVal &= (~(0x1 << 13));
939 regVal |= (((ant_div_control1 >> 3) & 0x1) << 13);
940 REG_WRITE(ah, 0xa208, regVal);
941 regVal = REG_READ(ah, 0xa208);
942 }
943
944 if (pModal->version >= 2) {
945 ob[0] = (pModal->ob_01 & 0xf);
946 ob[1] = (pModal->ob_01 >> 4) & 0xf;
947 ob[2] = (pModal->ob_234 & 0xf);
948 ob[3] = ((pModal->ob_234 >> 4) & 0xf);
949 ob[4] = ((pModal->ob_234 >> 8) & 0xf);
950
951 db1[0] = (pModal->db1_01 & 0xf);
952 db1[1] = ((pModal->db1_01 >> 4) & 0xf);
953 db1[2] = (pModal->db1_234 & 0xf);
954 db1[3] = ((pModal->db1_234 >> 4) & 0xf);
955 db1[4] = ((pModal->db1_234 >> 8) & 0xf);
956
957 db2[0] = (pModal->db2_01 & 0xf);
958 db2[1] = ((pModal->db2_01 >> 4) & 0xf);
959 db2[2] = (pModal->db2_234 & 0xf);
960 db2[3] = ((pModal->db2_234 >> 4) & 0xf);
961 db2[4] = ((pModal->db2_234 >> 8) & 0xf);
962
963 } else if (pModal->version == 1) {
964 ob[0] = (pModal->ob_01 & 0xf);
965 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf;
966 db1[0] = (pModal->db1_01 & 0xf);
967 db1[1] = db1[2] = db1[3] =
968 db1[4] = ((pModal->db1_01 >> 4) & 0xf);
969 db2[0] = (pModal->db2_01 & 0xf);
970 db2[1] = db2[2] = db2[3] =
971 db2[4] = ((pModal->db2_01 >> 4) & 0xf);
972 } else {
973 int i;
974 for (i = 0; i < 5; i++) {
975 ob[i] = pModal->ob_01;
976 db1[i] = pModal->db1_01;
977 db2[i] = pModal->db1_01;
978 }
979 }
980
981 if (AR_SREV_9271(ah)) {
982 ath9k_hw_analog_shift_rmw(ah,
983 AR9285_AN_RF2G3,
984 AR9271_AN_RF2G3_OB_cck,
985 AR9271_AN_RF2G3_OB_cck_S,
986 ob[0]);
987 ath9k_hw_analog_shift_rmw(ah,
988 AR9285_AN_RF2G3,
989 AR9271_AN_RF2G3_OB_psk,
990 AR9271_AN_RF2G3_OB_psk_S,
991 ob[1]);
992 ath9k_hw_analog_shift_rmw(ah,
993 AR9285_AN_RF2G3,
994 AR9271_AN_RF2G3_OB_qam,
995 AR9271_AN_RF2G3_OB_qam_S,
996 ob[2]);
997 ath9k_hw_analog_shift_rmw(ah,
998 AR9285_AN_RF2G3,
999 AR9271_AN_RF2G3_DB_1,
1000 AR9271_AN_RF2G3_DB_1_S,
1001 db1[0]);
1002 ath9k_hw_analog_shift_rmw(ah,
1003 AR9285_AN_RF2G4,
1004 AR9271_AN_RF2G4_DB_2,
1005 AR9271_AN_RF2G4_DB_2_S,
1006 db2[0]);
1007 } else {
1008 ath9k_hw_analog_shift_rmw(ah,
1009 AR9285_AN_RF2G3,
1010 AR9285_AN_RF2G3_OB_0,
1011 AR9285_AN_RF2G3_OB_0_S,
1012 ob[0]);
1013 ath9k_hw_analog_shift_rmw(ah,
1014 AR9285_AN_RF2G3,
1015 AR9285_AN_RF2G3_OB_1,
1016 AR9285_AN_RF2G3_OB_1_S,
1017 ob[1]);
1018 ath9k_hw_analog_shift_rmw(ah,
1019 AR9285_AN_RF2G3,
1020 AR9285_AN_RF2G3_OB_2,
1021 AR9285_AN_RF2G3_OB_2_S,
1022 ob[2]);
1023 ath9k_hw_analog_shift_rmw(ah,
1024 AR9285_AN_RF2G3,
1025 AR9285_AN_RF2G3_OB_3,
1026 AR9285_AN_RF2G3_OB_3_S,
1027 ob[3]);
1028 ath9k_hw_analog_shift_rmw(ah,
1029 AR9285_AN_RF2G3,
1030 AR9285_AN_RF2G3_OB_4,
1031 AR9285_AN_RF2G3_OB_4_S,
1032 ob[4]);
1033
1034 ath9k_hw_analog_shift_rmw(ah,
1035 AR9285_AN_RF2G3,
1036 AR9285_AN_RF2G3_DB1_0,
1037 AR9285_AN_RF2G3_DB1_0_S,
1038 db1[0]);
1039 ath9k_hw_analog_shift_rmw(ah,
1040 AR9285_AN_RF2G3,
1041 AR9285_AN_RF2G3_DB1_1,
1042 AR9285_AN_RF2G3_DB1_1_S,
1043 db1[1]);
1044 ath9k_hw_analog_shift_rmw(ah,
1045 AR9285_AN_RF2G3,
1046 AR9285_AN_RF2G3_DB1_2,
1047 AR9285_AN_RF2G3_DB1_2_S,
1048 db1[2]);
1049 ath9k_hw_analog_shift_rmw(ah,
1050 AR9285_AN_RF2G4,
1051 AR9285_AN_RF2G4_DB1_3,
1052 AR9285_AN_RF2G4_DB1_3_S,
1053 db1[3]);
1054 ath9k_hw_analog_shift_rmw(ah,
1055 AR9285_AN_RF2G4,
1056 AR9285_AN_RF2G4_DB1_4,
1057 AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1058
1059 ath9k_hw_analog_shift_rmw(ah,
1060 AR9285_AN_RF2G4,
1061 AR9285_AN_RF2G4_DB2_0,
1062 AR9285_AN_RF2G4_DB2_0_S,
1063 db2[0]);
1064 ath9k_hw_analog_shift_rmw(ah,
1065 AR9285_AN_RF2G4,
1066 AR9285_AN_RF2G4_DB2_1,
1067 AR9285_AN_RF2G4_DB2_1_S,
1068 db2[1]);
1069 ath9k_hw_analog_shift_rmw(ah,
1070 AR9285_AN_RF2G4,
1071 AR9285_AN_RF2G4_DB2_2,
1072 AR9285_AN_RF2G4_DB2_2_S,
1073 db2[2]);
1074 ath9k_hw_analog_shift_rmw(ah,
1075 AR9285_AN_RF2G4,
1076 AR9285_AN_RF2G4_DB2_3,
1077 AR9285_AN_RF2G4_DB2_3_S,
1078 db2[3]);
1079 ath9k_hw_analog_shift_rmw(ah,
1080 AR9285_AN_RF2G4,
1081 AR9285_AN_RF2G4_DB2_4,
1082 AR9285_AN_RF2G4_DB2_4_S,
1083 db2[4]);
1084 }
1085
1086
1087 if (AR_SREV_9285_11(ah))
1088 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1089
1090 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1091 pModal->switchSettling);
1092 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1093 pModal->adcDesiredSize);
1094
1095 REG_WRITE(ah, AR_PHY_RF_CTL4,
1096 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1097 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1098 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
1099 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1100
1101 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1102 pModal->txEndToRxOn);
1103 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1104 pModal->thresh62);
1105 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1106 pModal->thresh62);
1107
1108 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1109 AR5416_EEP_MINOR_VER_2) {
1110 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1111 pModal->txFrameToDataStart);
1112 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1113 pModal->txFrameToPaOn);
1114 }
1115
1116 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1117 AR5416_EEP_MINOR_VER_3) {
1118 if (IS_CHAN_HT40(chan))
1119 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1120 AR_PHY_SETTLING_SWITCH,
1121 pModal->swSettleHt40);
1122 }
1123}
1124
1125static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1126 struct ath9k_channel *chan)
1127{
1128 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1129 struct modal_eep_4k_header *pModal = &eep->modalHeader;
1130
1131 return pModal->antCtrlCommon & 0xFFFF;
1132}
1133
1134static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1135 enum ieee80211_band freq_band)
1136{
1137 return 1;
1138}
1139
1140static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1141{
1142#define EEP_MAP4K_SPURCHAN \
1143 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1144
1145 u16 spur_val = AR_NO_SPUR;
1146
1147 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1148 "Getting spur idx %d is2Ghz. %d val %x\n",
1149 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1150
1151 switch (ah->config.spurmode) {
1152 case SPUR_DISABLE:
1153 break;
1154 case SPUR_ENABLE_IOCTL:
1155 spur_val = ah->config.spurchans[i][is2GHz];
1156 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1157 "Getting spur val from new loc. %d\n", spur_val);
1158 break;
1159 case SPUR_ENABLE_EEPROM:
1160 spur_val = EEP_MAP4K_SPURCHAN;
1161 break;
1162 }
1163
1164 return spur_val;
1165
1166#undef EEP_MAP4K_SPURCHAN
1167}
1168
1169const struct eeprom_ops eep_4k_ops = {
1170 .check_eeprom = ath9k_hw_4k_check_eeprom,
1171 .get_eeprom = ath9k_hw_4k_get_eeprom,
1172 .fill_eeprom = ath9k_hw_4k_fill_eeprom,
1173 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
1174 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
1175 .get_num_ant_config = ath9k_hw_4k_get_num_ant_config,
1176 .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1177 .set_board_values = ath9k_hw_4k_set_board_values,
1178 .set_addac = ath9k_hw_4k_set_addac,
1179 .set_txpower = ath9k_hw_4k_set_txpower,
1180 .get_spur_channel = ath9k_hw_4k_get_spur_channel
1181};
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
new file mode 100644
index 000000000000..aeb7f484b6e1
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -0,0 +1,1183 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "ath9k.h"
18
19static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
20{
21 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
22}
23
24static int ath9k_hw_AR9287_get_eeprom_rev(struct ath_hw *ah)
25{
26 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
27}
28
29static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
30{
31 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
32 u16 *eep_data;
33 int addr, eep_start_loc = AR9287_EEP_START_LOC;
34 eep_data = (u16 *)eep;
35
36 if (!ath9k_hw_use_flash(ah)) {
37 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
38 "Reading from EEPROM, not flash\n");
39 }
40
41 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
42 addr++) {
43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
44 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
45 "Unable to read eeprom region \n");
46 return false;
47 }
48 eep_data++;
49 }
50 return true;
51}
52
53static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
54{
55 u32 sum = 0, el, integer;
56 u16 temp, word, magic, magic2, *eepdata;
57 int i, addr;
58 bool need_swap = false;
59 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
60
61 if (!ath9k_hw_use_flash(ah)) {
62 if (!ath9k_hw_nvram_read
63 (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
64 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
65 "Reading Magic # failed\n");
66 return false;
67 }
68
69 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
70 "Read Magic = 0x%04X\n", magic);
71 if (magic != AR5416_EEPROM_MAGIC) {
72 magic2 = swab16(magic);
73
74 if (magic2 == AR5416_EEPROM_MAGIC) {
75 need_swap = true;
76 eepdata = (u16 *)(&ah->eeprom);
77
78 for (addr = 0;
79 addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
80 addr++) {
81 temp = swab16(*eepdata);
82 *eepdata = temp;
83 eepdata++;
84 }
85 } else {
86 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
87 "Invalid EEPROM Magic. "
88 "endianness mismatch.\n");
89 return -EINVAL;
90 }
91 }
92 }
93 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ?
94 "True" : "False");
95
96 if (need_swap)
97 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
98 else
99 el = ah->eeprom.map9287.baseEepHeader.length;
100
101 if (el > sizeof(struct ar9287_eeprom))
102 el = sizeof(struct ar9287_eeprom) / sizeof(u16);
103 else
104 el = el / sizeof(u16);
105
106 eepdata = (u16 *)(&ah->eeprom);
107 for (i = 0; i < el; i++)
108 sum ^= *eepdata++;
109
110 if (need_swap) {
111 word = swab16(eep->baseEepHeader.length);
112 eep->baseEepHeader.length = word;
113
114 word = swab16(eep->baseEepHeader.checksum);
115 eep->baseEepHeader.checksum = word;
116
117 word = swab16(eep->baseEepHeader.version);
118 eep->baseEepHeader.version = word;
119
120 word = swab16(eep->baseEepHeader.regDmn[0]);
121 eep->baseEepHeader.regDmn[0] = word;
122
123 word = swab16(eep->baseEepHeader.regDmn[1]);
124 eep->baseEepHeader.regDmn[1] = word;
125
126 word = swab16(eep->baseEepHeader.rfSilent);
127 eep->baseEepHeader.rfSilent = word;
128
129 word = swab16(eep->baseEepHeader.blueToothOptions);
130 eep->baseEepHeader.blueToothOptions = word;
131
132 word = swab16(eep->baseEepHeader.deviceCap);
133 eep->baseEepHeader.deviceCap = word;
134
135 integer = swab32(eep->modalHeader.antCtrlCommon);
136 eep->modalHeader.antCtrlCommon = integer;
137
138 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
139 integer = swab32(eep->modalHeader.antCtrlChain[i]);
140 eep->modalHeader.antCtrlChain[i] = integer;
141 }
142
143 for (i = 0; i < AR9287_EEPROM_MODAL_SPURS; i++) {
144 word = swab16(eep->modalHeader.spurChans[i].spurChan);
145 eep->modalHeader.spurChans[i].spurChan = word;
146 }
147 }
148
149 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
150 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
151 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
152 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
153 sum, ah->eep_ops->get_eeprom_ver(ah));
154 return -EINVAL;
155 }
156
157 return 0;
158}
159
160static u32 ath9k_hw_AR9287_get_eeprom(struct ath_hw *ah,
161 enum eeprom_param param)
162{
163 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
164 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
165 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
166 u16 ver_minor;
167
168 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
169 switch (param) {
170 case EEP_NFTHRESH_2:
171 return pModal->noiseFloorThreshCh[0];
172 case AR_EEPROM_MAC(0):
173 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
174 case AR_EEPROM_MAC(1):
175 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
176 case AR_EEPROM_MAC(2):
177 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
178 case EEP_REG_0:
179 return pBase->regDmn[0];
180 case EEP_REG_1:
181 return pBase->regDmn[1];
182 case EEP_OP_CAP:
183 return pBase->deviceCap;
184 case EEP_OP_MODE:
185 return pBase->opCapFlags;
186 case EEP_RF_SILENT:
187 return pBase->rfSilent;
188 case EEP_MINOR_REV:
189 return ver_minor;
190 case EEP_TX_MASK:
191 return pBase->txMask;
192 case EEP_RX_MASK:
193 return pBase->rxMask;
194 case EEP_DEV_TYPE:
195 return pBase->deviceType;
196 case EEP_OL_PWRCTRL:
197 return pBase->openLoopPwrCntl;
198 case EEP_TEMPSENSE_SLOPE:
199 if (ver_minor >= AR9287_EEP_MINOR_VER_2)
200 return pBase->tempSensSlope;
201 else
202 return 0;
203 case EEP_TEMPSENSE_SLOPE_PAL_ON:
204 if (ver_minor >= AR9287_EEP_MINOR_VER_3)
205 return pBase->tempSensSlopePalOn;
206 else
207 return 0;
208 default:
209 return 0;
210 }
211}
212
213
214static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah,
215 struct ath9k_channel *chan,
216 struct cal_data_per_freq_ar9287 *pRawDataSet,
217 u8 *bChans, u16 availPiers,
218 u16 tPdGainOverlap, int16_t *pMinCalPower,
219 u16 *pPdGainBoundaries, u8 *pPDADCValues,
220 u16 numXpdGains)
221{
222#define TMP_VAL_VPD_TABLE \
223 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
224
225 int i, j, k;
226 int16_t ss;
227 u16 idxL = 0, idxR = 0, numPiers;
228 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
229 u8 minPwrT4[AR9287_NUM_PD_GAINS];
230 u8 maxPwrT4[AR9287_NUM_PD_GAINS];
231 int16_t vpdStep;
232 int16_t tmpVal;
233 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
234 bool match;
235 int16_t minDelta = 0;
236 struct chan_centers centers;
237 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
238 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
239 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
240 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
241 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
242 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
243
244 ath9k_hw_get_channel_centers(ah, chan, &centers);
245
246 for (numPiers = 0; numPiers < availPiers; numPiers++) {
247 if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
248 break;
249 }
250
251 match = ath9k_hw_get_lower_upper_index(
252 (u8)FREQ2FBIN(centers.synth_center,
253 IS_CHAN_2GHZ(chan)), bChans, numPiers,
254 &idxL, &idxR);
255
256 if (match) {
257 for (i = 0; i < numXpdGains; i++) {
258 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
259 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
260 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
261 pRawDataSet[idxL].pwrPdg[i],
262 pRawDataSet[idxL].vpdPdg[i],
263 AR9287_PD_GAIN_ICEPTS, vpdTableI[i]);
264 }
265 } else {
266 for (i = 0; i < numXpdGains; i++) {
267 pVpdL = pRawDataSet[idxL].vpdPdg[i];
268 pPwrL = pRawDataSet[idxL].pwrPdg[i];
269 pVpdR = pRawDataSet[idxR].vpdPdg[i];
270 pPwrR = pRawDataSet[idxR].pwrPdg[i];
271
272 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
273
274 maxPwrT4[i] =
275 min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1],
276 pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
277
278 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
279 pPwrL, pVpdL,
280 AR9287_PD_GAIN_ICEPTS,
281 vpdTableL[i]);
282 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
283 pPwrR, pVpdR,
284 AR9287_PD_GAIN_ICEPTS,
285 vpdTableR[i]);
286
287 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
288 vpdTableI[i][j] =
289 (u8)(ath9k_hw_interpolate((u16)
290 FREQ2FBIN(centers. synth_center,
291 IS_CHAN_2GHZ(chan)),
292 bChans[idxL], bChans[idxR],
293 vpdTableL[i][j], vpdTableR[i][j]));
294 }
295 }
296 }
297 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
298
299 k = 0;
300 for (i = 0; i < numXpdGains; i++) {
301 if (i == (numXpdGains - 1))
302 pPdGainBoundaries[i] = (u16)(maxPwrT4[i] / 2);
303 else
304 pPdGainBoundaries[i] = (u16)((maxPwrT4[i] +
305 minPwrT4[i+1]) / 4);
306
307 pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER,
308 pPdGainBoundaries[i]);
309
310
311 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
312 minDelta = pPdGainBoundaries[0] - 23;
313 pPdGainBoundaries[0] = 23;
314 } else
315 minDelta = 0;
316
317 if (i == 0) {
318 if (AR_SREV_9280_10_OR_LATER(ah))
319 ss = (int16_t)(0 - (minPwrT4[i] / 2));
320 else
321 ss = 0;
322 } else
323 ss = (int16_t)((pPdGainBoundaries[i-1] -
324 (minPwrT4[i] / 2)) -
325 tPdGainOverlap + 1 + minDelta);
326
327 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
328 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
329 while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) {
330 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
331 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
332 ss++;
333 }
334
335 sizeCurrVpdTable = (u8)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
336 tgtIndex = (u8)(pPdGainBoundaries[i] +
337 tPdGainOverlap - (minPwrT4[i] / 2));
338 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
339 tgtIndex : sizeCurrVpdTable;
340
341 while ((ss < maxIndex) && (k < (AR9287_NUM_PDADC_VALUES - 1)))
342 pPDADCValues[k++] = vpdTableI[i][ss++];
343
344 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
345 vpdTableI[i][sizeCurrVpdTable - 2]);
346 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
347 if (tgtIndex > maxIndex) {
348 while ((ss <= tgtIndex) &&
349 (k < (AR9287_NUM_PDADC_VALUES - 1))) {
350 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
351 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
352 255 : tmpVal);
353 ss++;
354 }
355 }
356 }
357
358 while (i < AR9287_PD_GAINS_IN_MASK) {
359 pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
360 i++;
361 }
362
363 while (k < AR9287_NUM_PDADC_VALUES) {
364 pPDADCValues[k] = pPDADCValues[k-1];
365 k++;
366 }
367
368#undef TMP_VAL_VPD_TABLE
369}
370
371static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
372 struct ath9k_channel *chan,
373 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
374 u8 *pCalChans, u16 availPiers,
375 int8_t *pPwr)
376{
377 u8 pcdac, i = 0;
378 u16 idxL = 0, idxR = 0, numPiers;
379 bool match;
380 struct chan_centers centers;
381
382 ath9k_hw_get_channel_centers(ah, chan, &centers);
383
384 for (numPiers = 0; numPiers < availPiers; numPiers++) {
385 if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED)
386 break;
387 }
388
389 match = ath9k_hw_get_lower_upper_index(
390 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
391 pCalChans, numPiers,
392 &idxL, &idxR);
393
394 if (match) {
395 pcdac = pRawDatasetOpLoop[idxL].pcdac[0][0];
396 *pPwr = pRawDatasetOpLoop[idxL].pwrPdg[0][0];
397 } else {
398 pcdac = pRawDatasetOpLoop[idxR].pcdac[0][0];
399 *pPwr = (pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
400 pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
401 }
402
403 while ((pcdac > ah->originalGain[i]) &&
404 (i < (AR9280_TX_GAIN_TABLE_SIZE - 1)))
405 i++;
406}
407
408static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
409 int32_t txPower, u16 chain)
410{
411 u32 tmpVal;
412 u32 a;
413
414 tmpVal = REG_READ(ah, 0xa270);
415 tmpVal = tmpVal & 0xFCFFFFFF;
416 tmpVal = tmpVal | (0x3 << 24);
417 REG_WRITE(ah, 0xa270, tmpVal);
418
419 tmpVal = REG_READ(ah, 0xb270);
420 tmpVal = tmpVal & 0xFCFFFFFF;
421 tmpVal = tmpVal | (0x3 << 24);
422 REG_WRITE(ah, 0xb270, tmpVal);
423
424 if (chain == 0) {
425 tmpVal = REG_READ(ah, 0xa398);
426 tmpVal = tmpVal & 0xff00ffff;
427 a = (txPower)&0xff;
428 tmpVal = tmpVal | (a << 16);
429 REG_WRITE(ah, 0xa398, tmpVal);
430 }
431
432 if (chain == 1) {
433 tmpVal = REG_READ(ah, 0xb398);
434 tmpVal = tmpVal & 0xff00ffff;
435 a = (txPower)&0xff;
436 tmpVal = tmpVal | (a << 16);
437 REG_WRITE(ah, 0xb398, tmpVal);
438 }
439}
440
441static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
442 struct ath9k_channel *chan,
443 int16_t *pTxPowerIndexOffset)
444{
445 struct cal_data_per_freq_ar9287 *pRawDataset;
446 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
447 u8 *pCalBChans = NULL;
448 u16 pdGainOverlap_t2;
449 u8 pdadcValues[AR9287_NUM_PDADC_VALUES];
450 u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK];
451 u16 numPiers = 0, i, j;
452 int16_t tMinCalPower;
453 u16 numXpdGain, xpdMask;
454 u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0};
455 u32 reg32, regOffset, regChainOffset;
456 int16_t modalIdx, diff = 0;
457 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
458 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
459 xpdMask = pEepData->modalHeader.xpdGain;
460 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
461 AR9287_EEP_MINOR_VER_2)
462 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
463 else
464 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
465 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
466
467 if (IS_CHAN_2GHZ(chan)) {
468 pCalBChans = pEepData->calFreqPier2G;
469 numPiers = AR9287_NUM_2G_CAL_PIERS;
470 if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
471 pRawDatasetOpenLoop =
472 (struct cal_data_op_loop_ar9287 *)
473 pEepData->calPierData2G[0];
474 ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
475 }
476 }
477
478 numXpdGain = 0;
479 for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) {
480 if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) {
481 if (numXpdGain >= AR9287_NUM_PD_GAINS)
482 break;
483 xpdGainValues[numXpdGain] =
484 (u16)(AR9287_PD_GAINS_IN_MASK-i);
485 numXpdGain++;
486 }
487 }
488
489 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
490 (numXpdGain - 1) & 0x3);
491 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
492 xpdGainValues[0]);
493 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
494 xpdGainValues[1]);
495 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
496 xpdGainValues[2]);
497
498 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
499 regChainOffset = i * 0x1000;
500 if (pEepData->baseEepHeader.txMask & (1 << i)) {
501 pRawDatasetOpenLoop = (struct cal_data_op_loop_ar9287 *)
502 pEepData->calPierData2G[i];
503 if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
504 int8_t txPower;
505 ar9287_eeprom_get_tx_gain_index(ah, chan,
506 pRawDatasetOpenLoop,
507 pCalBChans, numPiers,
508 &txPower);
509 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
510 } else {
511 pRawDataset =
512 (struct cal_data_per_freq_ar9287 *)
513 pEepData->calPierData2G[i];
514 ath9k_hw_get_AR9287_gain_boundaries_pdadcs(
515 ah, chan, pRawDataset,
516 pCalBChans, numPiers,
517 pdGainOverlap_t2,
518 &tMinCalPower, gainBoundaries,
519 pdadcValues, numXpdGain);
520 }
521
522 if (i == 0) {
523 if (!ath9k_hw_AR9287_get_eeprom(
524 ah, EEP_OL_PWRCTRL)) {
525 REG_WRITE(ah, AR_PHY_TPCRG5 +
526 regChainOffset,
527 SM(pdGainOverlap_t2,
528 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
529 SM(gainBoundaries[0],
530 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
531 | SM(gainBoundaries[1],
532 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
533 | SM(gainBoundaries[2],
534 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
535 | SM(gainBoundaries[3],
536 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
537 }
538 }
539
540 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB !=
541 pEepData->baseEepHeader.pwrTableOffset) {
542 diff = (u16)
543 (pEepData->baseEepHeader.pwrTableOffset
544 - (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
545 diff *= 2;
546
547 for (j = 0;
548 j < ((u16)AR9287_NUM_PDADC_VALUES-diff);
549 j++)
550 pdadcValues[j] = pdadcValues[j+diff];
551
552 for (j = (u16)(AR9287_NUM_PDADC_VALUES-diff);
553 j < AR9287_NUM_PDADC_VALUES; j++)
554 pdadcValues[j] =
555 pdadcValues[
556 AR9287_NUM_PDADC_VALUES-diff];
557 }
558
559 if (!ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
560 regOffset = AR_PHY_BASE + (672 << 2) +
561 regChainOffset;
562 for (j = 0; j < 32; j++) {
563 reg32 = ((pdadcValues[4*j + 0]
564 & 0xFF) << 0) |
565 ((pdadcValues[4*j + 1]
566 & 0xFF) << 8) |
567 ((pdadcValues[4*j + 2]
568 & 0xFF) << 16) |
569 ((pdadcValues[4*j + 3]
570 & 0xFF) << 24) ;
571 REG_WRITE(ah, regOffset, reg32);
572
573 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
574 "PDADC (%d,%4x): %4.4x %8.8x\n",
575 i, regChainOffset, regOffset,
576 reg32);
577
578 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
579 "PDADC: Chain %d | "
580 "PDADC %3d Value %3d | "
581 "PDADC %3d Value %3d | "
582 "PDADC %3d Value %3d | "
583 "PDADC %3d Value %3d |\n",
584 i, 4 * j, pdadcValues[4 * j],
585 4 * j + 1,
586 pdadcValues[4 * j + 1],
587 4 * j + 2,
588 pdadcValues[4 * j + 2],
589 4 * j + 3,
590 pdadcValues[4 * j + 3]);
591
592 regOffset += 4;
593 }
594 }
595 }
596 }
597
598 *pTxPowerIndexOffset = 0;
599}
600
601static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah,
602 struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl,
603 u16 AntennaReduction, u16 twiceMaxRegulatoryPower,
604 u16 powerLimit)
605{
606#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
607#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
608
609 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
610 static const u16 tpScaleReductionTable[5] =
611 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
612 int i;
613 int16_t twiceLargestAntenna;
614 struct cal_ctl_data_ar9287 *rep;
615 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
616 targetPowerCck = {0, {0, 0, 0, 0} };
617 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
618 targetPowerCckExt = {0, {0, 0, 0, 0} };
619 struct cal_target_power_ht targetPowerHt20,
620 targetPowerHt40 = {0, {0, 0, 0, 0} };
621 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
622 u16 ctlModesFor11g[] =
623 {CTL_11B, CTL_11G, CTL_2GHT20,
624 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40};
625 u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq;
626 struct chan_centers centers;
627 int tx_chainmask;
628 u16 twiceMinEdgePower;
629 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
630 tx_chainmask = ah->txchainmask;
631
632 ath9k_hw_get_channel_centers(ah, chan, &centers);
633
634 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
635 pEepData->modalHeader.antennaGainCh[1]);
636
637 twiceLargestAntenna = (int16_t)min((AntennaReduction) -
638 twiceLargestAntenna, 0);
639
640 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
641 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX)
642 maxRegAllowedPower -=
643 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
644
645 scaledPower = min(powerLimit, maxRegAllowedPower);
646
647 switch (ar5416_get_ntxchains(tx_chainmask)) {
648 case 1:
649 break;
650 case 2:
651 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
652 break;
653 case 3:
654 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
655 break;
656 }
657 scaledPower = max((u16)0, scaledPower);
658
659 if (IS_CHAN_2GHZ(chan)) {
660 numCtlModes =
661 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
662 pCtlMode = ctlModesFor11g;
663
664 ath9k_hw_get_legacy_target_powers(ah, chan,
665 pEepData->calTargetPowerCck,
666 AR9287_NUM_2G_CCK_TARGET_POWERS,
667 &targetPowerCck, 4, false);
668 ath9k_hw_get_legacy_target_powers(ah, chan,
669 pEepData->calTargetPower2G,
670 AR9287_NUM_2G_20_TARGET_POWERS,
671 &targetPowerOfdm, 4, false);
672 ath9k_hw_get_target_powers(ah, chan,
673 pEepData->calTargetPower2GHT20,
674 AR9287_NUM_2G_20_TARGET_POWERS,
675 &targetPowerHt20, 8, false);
676
677 if (IS_CHAN_HT40(chan)) {
678 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
679 ath9k_hw_get_target_powers(ah, chan,
680 pEepData->calTargetPower2GHT40,
681 AR9287_NUM_2G_40_TARGET_POWERS,
682 &targetPowerHt40, 8, true);
683 ath9k_hw_get_legacy_target_powers(ah, chan,
684 pEepData->calTargetPowerCck,
685 AR9287_NUM_2G_CCK_TARGET_POWERS,
686 &targetPowerCckExt, 4, true);
687 ath9k_hw_get_legacy_target_powers(ah, chan,
688 pEepData->calTargetPower2G,
689 AR9287_NUM_2G_20_TARGET_POWERS,
690 &targetPowerOfdmExt, 4, true);
691 }
692 }
693
694 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
695 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
696 (pCtlMode[ctlMode] == CTL_2GHT40);
697 if (isHt40CtlMode)
698 freq = centers.synth_center;
699 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
700 freq = centers.ext_center;
701 else
702 freq = centers.ctl_center;
703
704 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
705 ah->eep_ops->get_eeprom_rev(ah) <= 2)
706 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
707
708 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
709 if ((((cfgCtl & ~CTL_MODE_M) |
710 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
711 pEepData->ctlIndex[i]) ||
712 (((cfgCtl & ~CTL_MODE_M) |
713 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
714 ((pEepData->ctlIndex[i] &
715 CTL_MODE_M) | SD_NO_CTL))) {
716
717 rep = &(pEepData->ctlData[i]);
718 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
719 freq,
720 rep->ctlEdges[ar5416_get_ntxchains(
721 tx_chainmask) - 1],
722 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
723
724 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
725 twiceMaxEdgePower = min(
726 twiceMaxEdgePower,
727 twiceMinEdgePower);
728 else {
729 twiceMaxEdgePower = twiceMinEdgePower;
730 break;
731 }
732 }
733 }
734
735 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
736
737 switch (pCtlMode[ctlMode]) {
738 case CTL_11B:
739 for (i = 0;
740 i < ARRAY_SIZE(targetPowerCck.tPow2x);
741 i++) {
742 targetPowerCck.tPow2x[i] = (u8)min(
743 (u16)targetPowerCck.tPow2x[i],
744 minCtlPower);
745 }
746 break;
747 case CTL_11A:
748 case CTL_11G:
749 for (i = 0;
750 i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
751 i++) {
752 targetPowerOfdm.tPow2x[i] = (u8)min(
753 (u16)targetPowerOfdm.tPow2x[i],
754 minCtlPower);
755 }
756 break;
757 case CTL_5GHT20:
758 case CTL_2GHT20:
759 for (i = 0;
760 i < ARRAY_SIZE(targetPowerHt20.tPow2x);
761 i++) {
762 targetPowerHt20.tPow2x[i] = (u8)min(
763 (u16)targetPowerHt20.tPow2x[i],
764 minCtlPower);
765 }
766 break;
767 case CTL_11B_EXT:
768 targetPowerCckExt.tPow2x[0] = (u8)min(
769 (u16)targetPowerCckExt.tPow2x[0],
770 minCtlPower);
771 break;
772 case CTL_11A_EXT:
773 case CTL_11G_EXT:
774 targetPowerOfdmExt.tPow2x[0] = (u8)min(
775 (u16)targetPowerOfdmExt.tPow2x[0],
776 minCtlPower);
777 break;
778 case CTL_5GHT40:
779 case CTL_2GHT40:
780 for (i = 0;
781 i < ARRAY_SIZE(targetPowerHt40.tPow2x);
782 i++) {
783 targetPowerHt40.tPow2x[i] = (u8)min(
784 (u16)targetPowerHt40.tPow2x[i],
785 minCtlPower);
786 }
787 break;
788 default:
789 break;
790 }
791 }
792
793 ratesArray[rate6mb] =
794 ratesArray[rate9mb] =
795 ratesArray[rate12mb] =
796 ratesArray[rate18mb] =
797 ratesArray[rate24mb] =
798 targetPowerOfdm.tPow2x[0];
799
800 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
801 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
802 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
803 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
804
805 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
806 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
807
808 if (IS_CHAN_2GHZ(chan)) {
809 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
810 ratesArray[rate2s] = ratesArray[rate2l] =
811 targetPowerCck.tPow2x[1];
812 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
813 targetPowerCck.tPow2x[2];
814 ratesArray[rate11s] = ratesArray[rate11l] =
815 targetPowerCck.tPow2x[3];
816 }
817 if (IS_CHAN_HT40(chan)) {
818 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
819 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
820
821 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
822 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
823 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
824 if (IS_CHAN_2GHZ(chan))
825 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
826 }
827
828#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
829#undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
830}
831
832static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
833 struct ath9k_channel *chan, u16 cfgCtl,
834 u8 twiceAntennaReduction,
835 u8 twiceMaxRegulatoryPower,
836 u8 powerLimit)
837{
838#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
839#define INCREASE_MAXPOW_BY_THREE_CHAIN 10
840
841 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
842 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
843 int16_t ratesArray[Ar5416RateSize];
844 int16_t txPowerIndexOffset = 0;
845 u8 ht40PowerIncForPdadc = 2;
846 int i;
847
848 memset(ratesArray, 0, sizeof(ratesArray));
849
850 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
851 AR9287_EEP_MINOR_VER_2)
852 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
853
854 ath9k_hw_set_AR9287_power_per_rate_table(ah, chan,
855 &ratesArray[0], cfgCtl,
856 twiceAntennaReduction,
857 twiceMaxRegulatoryPower,
858 powerLimit);
859
860 ath9k_hw_set_AR9287_power_cal_table(ah, chan, &txPowerIndexOffset);
861
862 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
863 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
864 if (ratesArray[i] > AR9287_MAX_RATE_POWER)
865 ratesArray[i] = AR9287_MAX_RATE_POWER;
866 }
867
868 if (AR_SREV_9280_10_OR_LATER(ah)) {
869 for (i = 0; i < Ar5416RateSize; i++)
870 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
871 }
872
873 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
874 ATH9K_POW_SM(ratesArray[rate18mb], 24)
875 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
876 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
877 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
878
879 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
880 ATH9K_POW_SM(ratesArray[rate54mb], 24)
881 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
882 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
883 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
884
885 if (IS_CHAN_2GHZ(chan)) {
886 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
887 ATH9K_POW_SM(ratesArray[rate2s], 24)
888 | ATH9K_POW_SM(ratesArray[rate2l], 16)
889 | ATH9K_POW_SM(ratesArray[rateXr], 8)
890 | ATH9K_POW_SM(ratesArray[rate1l], 0));
891 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
892 ATH9K_POW_SM(ratesArray[rate11s], 24)
893 | ATH9K_POW_SM(ratesArray[rate11l], 16)
894 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
895 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
896 }
897
898 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
899 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
900 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
901 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
902 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
903
904 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
905 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
906 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
907 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
908 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
909
910 if (IS_CHAN_HT40(chan)) {
911 if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
912 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
913 ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
914 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
915 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
916 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
917
918 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
919 ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
920 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
921 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
922 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
923 } else {
924 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
925 ATH9K_POW_SM(ratesArray[rateHt40_3] +
926 ht40PowerIncForPdadc, 24)
927 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
928 ht40PowerIncForPdadc, 16)
929 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
930 ht40PowerIncForPdadc, 8)
931 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
932 ht40PowerIncForPdadc, 0));
933
934 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
935 ATH9K_POW_SM(ratesArray[rateHt40_7] +
936 ht40PowerIncForPdadc, 24)
937 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
938 ht40PowerIncForPdadc, 16)
939 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
940 ht40PowerIncForPdadc, 8)
941 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
942 ht40PowerIncForPdadc, 0));
943 }
944
945 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
946 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
947 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
948 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
949 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
950 }
951
952 if (IS_CHAN_2GHZ(chan))
953 i = rate1l;
954 else
955 i = rate6mb;
956
957 if (AR_SREV_9280_10_OR_LATER(ah))
958 ah->regulatory.max_power_level =
959 ratesArray[i] + AR9287_PWR_TABLE_OFFSET_DB * 2;
960 else
961 ah->regulatory.max_power_level = ratesArray[i];
962
963 switch (ar5416_get_ntxchains(ah->txchainmask)) {
964 case 1:
965 break;
966 case 2:
967 ah->regulatory.max_power_level +=
968 INCREASE_MAXPOW_BY_TWO_CHAIN;
969 break;
970 case 3:
971 ah->regulatory.max_power_level +=
972 INCREASE_MAXPOW_BY_THREE_CHAIN;
973 break;
974 default:
975 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
976 "Invalid chainmask configuration\n");
977 break;
978 }
979}
980
981static void ath9k_hw_AR9287_set_addac(struct ath_hw *ah,
982 struct ath9k_channel *chan)
983{
984}
985
986static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah,
987 struct ath9k_channel *chan)
988{
989 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
990 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
991 u16 antWrites[AR9287_ANT_16S];
992 u32 regChainOffset;
993 u8 txRxAttenLocal;
994 int i, j, offset_num;
995
996 pModal = &eep->modalHeader;
997
998 antWrites[0] = (u16)((pModal->antCtrlCommon >> 28) & 0xF);
999 antWrites[1] = (u16)((pModal->antCtrlCommon >> 24) & 0xF);
1000 antWrites[2] = (u16)((pModal->antCtrlCommon >> 20) & 0xF);
1001 antWrites[3] = (u16)((pModal->antCtrlCommon >> 16) & 0xF);
1002 antWrites[4] = (u16)((pModal->antCtrlCommon >> 12) & 0xF);
1003 antWrites[5] = (u16)((pModal->antCtrlCommon >> 8) & 0xF);
1004 antWrites[6] = (u16)((pModal->antCtrlCommon >> 4) & 0xF);
1005 antWrites[7] = (u16)(pModal->antCtrlCommon & 0xF);
1006
1007 offset_num = 8;
1008
1009 for (i = 0, j = offset_num; i < AR9287_MAX_CHAINS; i++) {
1010 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 28) & 0xf);
1011 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 10) & 0x3);
1012 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 8) & 0x3);
1013 antWrites[j++] = 0;
1014 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 6) & 0x3);
1015 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 4) & 0x3);
1016 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 2) & 0x3);
1017 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
1018 }
1019
1020 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1021 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1022
1023 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
1024 regChainOffset = i * 0x1000;
1025
1026 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1027 pModal->antCtrlChain[i]);
1028
1029 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1030 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
1031 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1032 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1033 SM(pModal->iqCalICh[i],
1034 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1035 SM(pModal->iqCalQCh[i],
1036 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1037
1038 txRxAttenLocal = pModal->txRxAttenCh[i];
1039
1040 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1041 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1042 pModal->bswMargin[i]);
1043 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1044 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1045 pModal->bswAtten[i]);
1046 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1047 AR9280_PHY_RXGAIN_TXRX_ATTEN,
1048 txRxAttenLocal);
1049 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1050 AR9280_PHY_RXGAIN_TXRX_MARGIN,
1051 pModal->rxTxMarginCh[i]);
1052 }
1053
1054
1055 if (IS_CHAN_HT40(chan))
1056 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1057 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
1058 else
1059 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1060 AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
1061
1062 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1063 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
1064
1065 REG_WRITE(ah, AR_PHY_RF_CTL4,
1066 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1067 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1068 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1069 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1070
1071 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
1072 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
1073
1074 REG_RMW_FIELD(ah, AR_PHY_CCA,
1075 AR9280_PHY_CCA_THRESH62, pModal->thresh62);
1076 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
1077 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
1078
1079 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, AR9287_AN_RF2G3_DB1,
1080 AR9287_AN_RF2G3_DB1_S, pModal->db1);
1081 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, AR9287_AN_RF2G3_DB2,
1082 AR9287_AN_RF2G3_DB2_S, pModal->db2);
1083 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0,
1084 AR9287_AN_RF2G3_OB_CCK,
1085 AR9287_AN_RF2G3_OB_CCK_S, pModal->ob_cck);
1086 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0,
1087 AR9287_AN_RF2G3_OB_PSK,
1088 AR9287_AN_RF2G3_OB_PSK_S, pModal->ob_psk);
1089 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0,
1090 AR9287_AN_RF2G3_OB_QAM,
1091 AR9287_AN_RF2G3_OB_QAM_S, pModal->ob_qam);
1092 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0,
1093 AR9287_AN_RF2G3_OB_PAL_OFF,
1094 AR9287_AN_RF2G3_OB_PAL_OFF_S,
1095 pModal->ob_pal_off);
1096
1097 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1,
1098 AR9287_AN_RF2G3_DB1, AR9287_AN_RF2G3_DB1_S,
1099 pModal->db1);
1100 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, AR9287_AN_RF2G3_DB2,
1101 AR9287_AN_RF2G3_DB2_S, pModal->db2);
1102 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1,
1103 AR9287_AN_RF2G3_OB_CCK,
1104 AR9287_AN_RF2G3_OB_CCK_S, pModal->ob_cck);
1105 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1,
1106 AR9287_AN_RF2G3_OB_PSK,
1107 AR9287_AN_RF2G3_OB_PSK_S, pModal->ob_psk);
1108 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1,
1109 AR9287_AN_RF2G3_OB_QAM,
1110 AR9287_AN_RF2G3_OB_QAM_S, pModal->ob_qam);
1111 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1,
1112 AR9287_AN_RF2G3_OB_PAL_OFF,
1113 AR9287_AN_RF2G3_OB_PAL_OFF_S,
1114 pModal->ob_pal_off);
1115
1116 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1117 AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);
1118 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1119 AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn);
1120
1121 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2,
1122 AR9287_AN_TOP2_XPABIAS_LVL,
1123 AR9287_AN_TOP2_XPABIAS_LVL_S,
1124 pModal->xpaBiasLvl);
1125}
1126
1127static u8 ath9k_hw_AR9287_get_num_ant_config(struct ath_hw *ah,
1128 enum ieee80211_band freq_band)
1129{
1130 return 1;
1131}
1132
1133static u16 ath9k_hw_AR9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
1134 struct ath9k_channel *chan)
1135{
1136 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
1137 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
1138
1139 return pModal->antCtrlCommon & 0xFFFF;
1140}
1141
1142static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
1143 u16 i, bool is2GHz)
1144{
1145#define EEP_MAP9287_SPURCHAN \
1146 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
1147 u16 spur_val = AR_NO_SPUR;
1148
1149 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1150 "Getting spur idx %d is2Ghz. %d val %x\n",
1151 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1152
1153 switch (ah->config.spurmode) {
1154 case SPUR_DISABLE:
1155 break;
1156 case SPUR_ENABLE_IOCTL:
1157 spur_val = ah->config.spurchans[i][is2GHz];
1158 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1159 "Getting spur val from new loc. %d\n", spur_val);
1160 break;
1161 case SPUR_ENABLE_EEPROM:
1162 spur_val = EEP_MAP9287_SPURCHAN;
1163 break;
1164 }
1165
1166 return spur_val;
1167
1168#undef EEP_MAP9287_SPURCHAN
1169}
1170
1171const struct eeprom_ops eep_AR9287_ops = {
1172 .check_eeprom = ath9k_hw_AR9287_check_eeprom,
1173 .get_eeprom = ath9k_hw_AR9287_get_eeprom,
1174 .fill_eeprom = ath9k_hw_AR9287_fill_eeprom,
1175 .get_eeprom_ver = ath9k_hw_AR9287_get_eeprom_ver,
1176 .get_eeprom_rev = ath9k_hw_AR9287_get_eeprom_rev,
1177 .get_num_ant_config = ath9k_hw_AR9287_get_num_ant_config,
1178 .get_eeprom_antenna_cfg = ath9k_hw_AR9287_get_eeprom_antenna_cfg,
1179 .set_board_values = ath9k_hw_AR9287_set_board_values,
1180 .set_addac = ath9k_hw_AR9287_set_addac,
1181 .set_txpower = ath9k_hw_AR9287_set_txpower,
1182 .get_spur_channel = ath9k_hw_AR9287_get_spur_channel
1183};
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
new file mode 100644
index 000000000000..5211ad94c8fb
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -0,0 +1,1385 @@
1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "ath9k.h"
18
19static void ath9k_get_txgain_index(struct ath_hw *ah,
20 struct ath9k_channel *chan,
21 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
22 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
23{
24 u8 pcdac, i = 0;
25 u16 idxL = 0, idxR = 0, numPiers;
26 bool match;
27 struct chan_centers centers;
28
29 ath9k_hw_get_channel_centers(ah, chan, &centers);
30
31 for (numPiers = 0; numPiers < availPiers; numPiers++)
32 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
33 break;
34
35 match = ath9k_hw_get_lower_upper_index(
36 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
37 calChans, numPiers, &idxL, &idxR);
38 if (match) {
39 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
40 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
41 } else {
42 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
43 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
44 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
45 }
46
47 while (pcdac > ah->originalGain[i] &&
48 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
49 i++;
50
51 *pcdacIdx = i;
52 return;
53}
54
55static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
56 u32 initTxGain,
57 int txPower,
58 u8 *pPDADCValues)
59{
60 u32 i;
61 u32 offset;
62
63 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
64 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
65 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
66 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
67
68 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
69 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
70
71 offset = txPower;
72 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
73 if (i < offset)
74 pPDADCValues[i] = 0x0;
75 else
76 pPDADCValues[i] = 0xFF;
77}
78
79static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
80{
81 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
82}
83
84static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
85{
86 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
87}
88
89static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
90{
91#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
92 u16 *eep_data = (u16 *)&ah->eeprom.def;
93 int addr, ar5416_eep_start_loc = 0x100;
94
95 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
96 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
97 eep_data)) {
98 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
99 "Unable to read eeprom region\n");
100 return false;
101 }
102 eep_data++;
103 }
104 return true;
105#undef SIZE_EEPROM_DEF
106}
107
108static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
109{
110 struct ar5416_eeprom_def *eep =
111 (struct ar5416_eeprom_def *) &ah->eeprom.def;
112 u16 *eepdata, temp, magic, magic2;
113 u32 sum = 0, el;
114 bool need_swap = false;
115 int i, addr, size;
116
117 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
118 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Reading Magic # failed\n");
119 return false;
120 }
121
122 if (!ath9k_hw_use_flash(ah)) {
123 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
124 "Read Magic = 0x%04X\n", magic);
125
126 if (magic != AR5416_EEPROM_MAGIC) {
127 magic2 = swab16(magic);
128
129 if (magic2 == AR5416_EEPROM_MAGIC) {
130 size = sizeof(struct ar5416_eeprom_def);
131 need_swap = true;
132 eepdata = (u16 *) (&ah->eeprom);
133
134 for (addr = 0; addr < size / sizeof(u16); addr++) {
135 temp = swab16(*eepdata);
136 *eepdata = temp;
137 eepdata++;
138 }
139 } else {
140 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
141 "Invalid EEPROM Magic. "
142 "Endianness mismatch.\n");
143 return -EINVAL;
144 }
145 }
146 }
147
148 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
149 need_swap ? "True" : "False");
150
151 if (need_swap)
152 el = swab16(ah->eeprom.def.baseEepHeader.length);
153 else
154 el = ah->eeprom.def.baseEepHeader.length;
155
156 if (el > sizeof(struct ar5416_eeprom_def))
157 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
158 else
159 el = el / sizeof(u16);
160
161 eepdata = (u16 *)(&ah->eeprom);
162
163 for (i = 0; i < el; i++)
164 sum ^= *eepdata++;
165
166 if (need_swap) {
167 u32 integer, j;
168 u16 word;
169
170 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
171 "EEPROM Endianness is not native.. Changing.\n");
172
173 word = swab16(eep->baseEepHeader.length);
174 eep->baseEepHeader.length = word;
175
176 word = swab16(eep->baseEepHeader.checksum);
177 eep->baseEepHeader.checksum = word;
178
179 word = swab16(eep->baseEepHeader.version);
180 eep->baseEepHeader.version = word;
181
182 word = swab16(eep->baseEepHeader.regDmn[0]);
183 eep->baseEepHeader.regDmn[0] = word;
184
185 word = swab16(eep->baseEepHeader.regDmn[1]);
186 eep->baseEepHeader.regDmn[1] = word;
187
188 word = swab16(eep->baseEepHeader.rfSilent);
189 eep->baseEepHeader.rfSilent = word;
190
191 word = swab16(eep->baseEepHeader.blueToothOptions);
192 eep->baseEepHeader.blueToothOptions = word;
193
194 word = swab16(eep->baseEepHeader.deviceCap);
195 eep->baseEepHeader.deviceCap = word;
196
197 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
198 struct modal_eep_header *pModal =
199 &eep->modalHeader[j];
200 integer = swab32(pModal->antCtrlCommon);
201 pModal->antCtrlCommon = integer;
202
203 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
204 integer = swab32(pModal->antCtrlChain[i]);
205 pModal->antCtrlChain[i] = integer;
206 }
207
208 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
209 word = swab16(pModal->spurChans[i].spurChan);
210 pModal->spurChans[i].spurChan = word;
211 }
212 }
213 }
214
215 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
216 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
217 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
218 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
219 sum, ah->eep_ops->get_eeprom_ver(ah));
220 return -EINVAL;
221 }
222
223 return 0;
224}
225
226static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
227 enum eeprom_param param)
228{
229 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
230 struct modal_eep_header *pModal = eep->modalHeader;
231 struct base_eep_header *pBase = &eep->baseEepHeader;
232
233 switch (param) {
234 case EEP_NFTHRESH_5:
235 return pModal[0].noiseFloorThreshCh[0];
236 case EEP_NFTHRESH_2:
237 return pModal[1].noiseFloorThreshCh[0];
238 case AR_EEPROM_MAC(0):
239 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
240 case AR_EEPROM_MAC(1):
241 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
242 case AR_EEPROM_MAC(2):
243 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
244 case EEP_REG_0:
245 return pBase->regDmn[0];
246 case EEP_REG_1:
247 return pBase->regDmn[1];
248 case EEP_OP_CAP:
249 return pBase->deviceCap;
250 case EEP_OP_MODE:
251 return pBase->opCapFlags;
252 case EEP_RF_SILENT:
253 return pBase->rfSilent;
254 case EEP_OB_5:
255 return pModal[0].ob;
256 case EEP_DB_5:
257 return pModal[0].db;
258 case EEP_OB_2:
259 return pModal[1].ob;
260 case EEP_DB_2:
261 return pModal[1].db;
262 case EEP_MINOR_REV:
263 return AR5416_VER_MASK;
264 case EEP_TX_MASK:
265 return pBase->txMask;
266 case EEP_RX_MASK:
267 return pBase->rxMask;
268 case EEP_RXGAIN_TYPE:
269 return pBase->rxGainType;
270 case EEP_TXGAIN_TYPE:
271 return pBase->txGainType;
272 case EEP_OL_PWRCTRL:
273 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
274 return pBase->openLoopPwrCntl ? true : false;
275 else
276 return false;
277 case EEP_RC_CHAIN_MASK:
278 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
279 return pBase->rcChainMask;
280 else
281 return 0;
282 case EEP_DAC_HPWR_5G:
283 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
284 return pBase->dacHiPwrMode_5G;
285 else
286 return 0;
287 case EEP_FRAC_N_5G:
288 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
289 return pBase->frac_n_5g;
290 else
291 return 0;
292 default:
293 return 0;
294 }
295}
296
297static void ath9k_hw_def_set_gain(struct ath_hw *ah,
298 struct modal_eep_header *pModal,
299 struct ar5416_eeprom_def *eep,
300 u8 txRxAttenLocal, int regChainOffset, int i)
301{
302 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
303 txRxAttenLocal = pModal->txRxAttenCh[i];
304
305 if (AR_SREV_9280_10_OR_LATER(ah)) {
306 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
307 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
308 pModal->bswMargin[i]);
309 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
310 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
311 pModal->bswAtten[i]);
312 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
313 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
314 pModal->xatten2Margin[i]);
315 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
316 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
317 pModal->xatten2Db[i]);
318 } else {
319 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
320 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
321 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
322 | SM(pModal-> bswMargin[i],
323 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
324 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
325 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
326 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
327 | SM(pModal->bswAtten[i],
328 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
329 }
330 }
331
332 if (AR_SREV_9280_10_OR_LATER(ah)) {
333 REG_RMW_FIELD(ah,
334 AR_PHY_RXGAIN + regChainOffset,
335 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
336 REG_RMW_FIELD(ah,
337 AR_PHY_RXGAIN + regChainOffset,
338 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
339 } else {
340 REG_WRITE(ah,
341 AR_PHY_RXGAIN + regChainOffset,
342 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
343 ~AR_PHY_RXGAIN_TXRX_ATTEN)
344 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
345 REG_WRITE(ah,
346 AR_PHY_GAIN_2GHZ + regChainOffset,
347 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
348 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
349 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
350 }
351}
352
353static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
354 struct ath9k_channel *chan)
355{
356 struct modal_eep_header *pModal;
357 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
358 int i, regChainOffset;
359 u8 txRxAttenLocal;
360
361 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
362 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
363
364 REG_WRITE(ah, AR_PHY_SWITCH_COM,
365 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
366
367 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
368 if (AR_SREV_9280(ah)) {
369 if (i >= 2)
370 break;
371 }
372
373 if (AR_SREV_5416_20_OR_LATER(ah) &&
374 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
375 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
376 else
377 regChainOffset = i * 0x1000;
378
379 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
380 pModal->antCtrlChain[i]);
381
382 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
383 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
384 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
385 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
386 SM(pModal->iqCalICh[i],
387 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
388 SM(pModal->iqCalQCh[i],
389 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
390
391 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
392 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
393 regChainOffset, i);
394 }
395
396 if (AR_SREV_9280_10_OR_LATER(ah)) {
397 if (IS_CHAN_2GHZ(chan)) {
398 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
399 AR_AN_RF2G1_CH0_OB,
400 AR_AN_RF2G1_CH0_OB_S,
401 pModal->ob);
402 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
403 AR_AN_RF2G1_CH0_DB,
404 AR_AN_RF2G1_CH0_DB_S,
405 pModal->db);
406 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
407 AR_AN_RF2G1_CH1_OB,
408 AR_AN_RF2G1_CH1_OB_S,
409 pModal->ob_ch1);
410 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
411 AR_AN_RF2G1_CH1_DB,
412 AR_AN_RF2G1_CH1_DB_S,
413 pModal->db_ch1);
414 } else {
415 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
416 AR_AN_RF5G1_CH0_OB5,
417 AR_AN_RF5G1_CH0_OB5_S,
418 pModal->ob);
419 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
420 AR_AN_RF5G1_CH0_DB5,
421 AR_AN_RF5G1_CH0_DB5_S,
422 pModal->db);
423 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
424 AR_AN_RF5G1_CH1_OB5,
425 AR_AN_RF5G1_CH1_OB5_S,
426 pModal->ob_ch1);
427 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
428 AR_AN_RF5G1_CH1_DB5,
429 AR_AN_RF5G1_CH1_DB5_S,
430 pModal->db_ch1);
431 }
432 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
433 AR_AN_TOP2_XPABIAS_LVL,
434 AR_AN_TOP2_XPABIAS_LVL_S,
435 pModal->xpaBiasLvl);
436 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
437 AR_AN_TOP2_LOCALBIAS,
438 AR_AN_TOP2_LOCALBIAS_S,
439 pModal->local_bias);
440 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
441 pModal->force_xpaon);
442 }
443
444 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
445 pModal->switchSettling);
446 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
447 pModal->adcDesiredSize);
448
449 if (!AR_SREV_9280_10_OR_LATER(ah))
450 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
451 AR_PHY_DESIRED_SZ_PGA,
452 pModal->pgaDesiredSize);
453
454 REG_WRITE(ah, AR_PHY_RF_CTL4,
455 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
456 | SM(pModal->txEndToXpaOff,
457 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
458 | SM(pModal->txFrameToXpaOn,
459 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
460 | SM(pModal->txFrameToXpaOn,
461 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
462
463 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
464 pModal->txEndToRxOn);
465
466 if (AR_SREV_9280_10_OR_LATER(ah)) {
467 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
468 pModal->thresh62);
469 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
470 AR_PHY_EXT_CCA0_THRESH62,
471 pModal->thresh62);
472 } else {
473 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
474 pModal->thresh62);
475 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
476 AR_PHY_EXT_CCA_THRESH62,
477 pModal->thresh62);
478 }
479
480 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
481 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
482 AR_PHY_TX_END_DATA_START,
483 pModal->txFrameToDataStart);
484 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
485 pModal->txFrameToPaOn);
486 }
487
488 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
489 if (IS_CHAN_HT40(chan))
490 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
491 AR_PHY_SETTLING_SWITCH,
492 pModal->swSettleHt40);
493 }
494
495 if (AR_SREV_9280_20_OR_LATER(ah) &&
496 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
497 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
498 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
499 pModal->miscBits);
500
501
502 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
503 if (IS_CHAN_2GHZ(chan))
504 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
505 eep->baseEepHeader.dacLpMode);
506 else if (eep->baseEepHeader.dacHiPwrMode_5G)
507 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
508 else
509 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
510 eep->baseEepHeader.dacLpMode);
511
512 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
513 pModal->miscBits >> 2);
514
515 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
516 AR_PHY_TX_DESIRED_SCALE_CCK,
517 eep->baseEepHeader.desiredScaleCCK);
518 }
519}
520
521static void ath9k_hw_def_set_addac(struct ath_hw *ah,
522 struct ath9k_channel *chan)
523{
524#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
525 struct modal_eep_header *pModal;
526 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
527 u8 biaslevel;
528
529 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
530 return;
531
532 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
533 return;
534
535 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
536
537 if (pModal->xpaBiasLvl != 0xff) {
538 biaslevel = pModal->xpaBiasLvl;
539 } else {
540 u16 resetFreqBin, freqBin, freqCount = 0;
541 struct chan_centers centers;
542
543 ath9k_hw_get_channel_centers(ah, chan, &centers);
544
545 resetFreqBin = FREQ2FBIN(centers.synth_center,
546 IS_CHAN_2GHZ(chan));
547 freqBin = XPA_LVL_FREQ(0) & 0xff;
548 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
549
550 freqCount++;
551
552 while (freqCount < 3) {
553 if (XPA_LVL_FREQ(freqCount) == 0x0)
554 break;
555
556 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
557 if (resetFreqBin >= freqBin)
558 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
559 else
560 break;
561 freqCount++;
562 }
563 }
564
565 if (IS_CHAN_2GHZ(chan)) {
566 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
567 7, 1) & (~0x18)) | biaslevel << 3;
568 } else {
569 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
570 6, 1) & (~0xc0)) | biaslevel << 6;
571 }
572#undef XPA_LVL_FREQ
573}
574
575static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
576 struct ath9k_channel *chan,
577 struct cal_data_per_freq *pRawDataSet,
578 u8 *bChans, u16 availPiers,
579 u16 tPdGainOverlap, int16_t *pMinCalPower,
580 u16 *pPdGainBoundaries, u8 *pPDADCValues,
581 u16 numXpdGains)
582{
583 int i, j, k;
584 int16_t ss;
585 u16 idxL = 0, idxR = 0, numPiers;
586 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
587 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
588 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
589 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
590 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
591 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
592
593 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
594 u8 minPwrT4[AR5416_NUM_PD_GAINS];
595 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
596 int16_t vpdStep;
597 int16_t tmpVal;
598 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
599 bool match;
600 int16_t minDelta = 0;
601 struct chan_centers centers;
602
603 ath9k_hw_get_channel_centers(ah, chan, &centers);
604
605 for (numPiers = 0; numPiers < availPiers; numPiers++) {
606 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
607 break;
608 }
609
610 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
611 IS_CHAN_2GHZ(chan)),
612 bChans, numPiers, &idxL, &idxR);
613
614 if (match) {
615 for (i = 0; i < numXpdGains; i++) {
616 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
617 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
618 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
619 pRawDataSet[idxL].pwrPdg[i],
620 pRawDataSet[idxL].vpdPdg[i],
621 AR5416_PD_GAIN_ICEPTS,
622 vpdTableI[i]);
623 }
624 } else {
625 for (i = 0; i < numXpdGains; i++) {
626 pVpdL = pRawDataSet[idxL].vpdPdg[i];
627 pPwrL = pRawDataSet[idxL].pwrPdg[i];
628 pVpdR = pRawDataSet[idxR].vpdPdg[i];
629 pPwrR = pRawDataSet[idxR].pwrPdg[i];
630
631 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
632
633 maxPwrT4[i] =
634 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
635 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
636
637
638 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
639 pPwrL, pVpdL,
640 AR5416_PD_GAIN_ICEPTS,
641 vpdTableL[i]);
642 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
643 pPwrR, pVpdR,
644 AR5416_PD_GAIN_ICEPTS,
645 vpdTableR[i]);
646
647 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
648 vpdTableI[i][j] =
649 (u8)(ath9k_hw_interpolate((u16)
650 FREQ2FBIN(centers.
651 synth_center,
652 IS_CHAN_2GHZ
653 (chan)),
654 bChans[idxL], bChans[idxR],
655 vpdTableL[i][j], vpdTableR[i][j]));
656 }
657 }
658 }
659
660 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
661
662 k = 0;
663
664 for (i = 0; i < numXpdGains; i++) {
665 if (i == (numXpdGains - 1))
666 pPdGainBoundaries[i] =
667 (u16)(maxPwrT4[i] / 2);
668 else
669 pPdGainBoundaries[i] =
670 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
671
672 pPdGainBoundaries[i] =
673 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
674
675 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
676 minDelta = pPdGainBoundaries[0] - 23;
677 pPdGainBoundaries[0] = 23;
678 } else {
679 minDelta = 0;
680 }
681
682 if (i == 0) {
683 if (AR_SREV_9280_10_OR_LATER(ah))
684 ss = (int16_t)(0 - (minPwrT4[i] / 2));
685 else
686 ss = 0;
687 } else {
688 ss = (int16_t)((pPdGainBoundaries[i - 1] -
689 (minPwrT4[i] / 2)) -
690 tPdGainOverlap + 1 + minDelta);
691 }
692 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
693 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
694
695 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
696 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
697 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
698 ss++;
699 }
700
701 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
702 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
703 (minPwrT4[i] / 2));
704 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
705 tgtIndex : sizeCurrVpdTable;
706
707 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
708 pPDADCValues[k++] = vpdTableI[i][ss++];
709 }
710
711 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
712 vpdTableI[i][sizeCurrVpdTable - 2]);
713 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
714
715 if (tgtIndex > maxIndex) {
716 while ((ss <= tgtIndex) &&
717 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
718 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
719 (ss - maxIndex + 1) * vpdStep));
720 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
721 255 : tmpVal);
722 ss++;
723 }
724 }
725 }
726
727 while (i < AR5416_PD_GAINS_IN_MASK) {
728 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
729 i++;
730 }
731
732 while (k < AR5416_NUM_PDADC_VALUES) {
733 pPDADCValues[k] = pPDADCValues[k - 1];
734 k++;
735 }
736
737 return;
738}
739
740static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
741 struct ath9k_channel *chan,
742 int16_t *pTxPowerIndexOffset)
743{
744#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
745#define SM_PDGAIN_B(x, y) \
746 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
747
748 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
749 struct cal_data_per_freq *pRawDataset;
750 u8 *pCalBChans = NULL;
751 u16 pdGainOverlap_t2;
752 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
753 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
754 u16 numPiers, i, j;
755 int16_t tMinCalPower;
756 u16 numXpdGain, xpdMask;
757 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
758 u32 reg32, regOffset, regChainOffset;
759 int16_t modalIdx;
760
761 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
762 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
763
764 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
765 AR5416_EEP_MINOR_VER_2) {
766 pdGainOverlap_t2 =
767 pEepData->modalHeader[modalIdx].pdGainOverlap;
768 } else {
769 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
770 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
771 }
772
773 if (IS_CHAN_2GHZ(chan)) {
774 pCalBChans = pEepData->calFreqPier2G;
775 numPiers = AR5416_NUM_2G_CAL_PIERS;
776 } else {
777 pCalBChans = pEepData->calFreqPier5G;
778 numPiers = AR5416_NUM_5G_CAL_PIERS;
779 }
780
781 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
782 pRawDataset = pEepData->calPierData2G[0];
783 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
784 pRawDataset)->vpdPdg[0][0];
785 }
786
787 numXpdGain = 0;
788
789 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
790 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
791 if (numXpdGain >= AR5416_NUM_PD_GAINS)
792 break;
793 xpdGainValues[numXpdGain] =
794 (u16)(AR5416_PD_GAINS_IN_MASK - i);
795 numXpdGain++;
796 }
797 }
798
799 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
800 (numXpdGain - 1) & 0x3);
801 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
802 xpdGainValues[0]);
803 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
804 xpdGainValues[1]);
805 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
806 xpdGainValues[2]);
807
808 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
809 if (AR_SREV_5416_20_OR_LATER(ah) &&
810 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
811 (i != 0)) {
812 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
813 } else
814 regChainOffset = i * 0x1000;
815
816 if (pEepData->baseEepHeader.txMask & (1 << i)) {
817 if (IS_CHAN_2GHZ(chan))
818 pRawDataset = pEepData->calPierData2G[i];
819 else
820 pRawDataset = pEepData->calPierData5G[i];
821
822
823 if (OLC_FOR_AR9280_20_LATER) {
824 u8 pcdacIdx;
825 u8 txPower;
826
827 ath9k_get_txgain_index(ah, chan,
828 (struct calDataPerFreqOpLoop *)pRawDataset,
829 pCalBChans, numPiers, &txPower, &pcdacIdx);
830 ath9k_olc_get_pdadcs(ah, pcdacIdx,
831 txPower/2, pdadcValues);
832 } else {
833 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
834 chan, pRawDataset,
835 pCalBChans, numPiers,
836 pdGainOverlap_t2,
837 &tMinCalPower,
838 gainBoundaries,
839 pdadcValues,
840 numXpdGain);
841 }
842
843 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
844 if (OLC_FOR_AR9280_20_LATER) {
845 REG_WRITE(ah,
846 AR_PHY_TPCRG5 + regChainOffset,
847 SM(0x6,
848 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
849 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
850 SM_PD_GAIN(3) | SM_PD_GAIN(4));
851 } else {
852 REG_WRITE(ah,
853 AR_PHY_TPCRG5 + regChainOffset,
854 SM(pdGainOverlap_t2,
855 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
856 SM_PDGAIN_B(0, 1) |
857 SM_PDGAIN_B(1, 2) |
858 SM_PDGAIN_B(2, 3) |
859 SM_PDGAIN_B(3, 4));
860 }
861 }
862
863 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
864 for (j = 0; j < 32; j++) {
865 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
866 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
867 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
868 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
869 REG_WRITE(ah, regOffset, reg32);
870
871 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
872 "PDADC (%d,%4x): %4.4x %8.8x\n",
873 i, regChainOffset, regOffset,
874 reg32);
875 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
876 "PDADC: Chain %d | PDADC %3d "
877 "Value %3d | PDADC %3d Value %3d | "
878 "PDADC %3d Value %3d | PDADC %3d "
879 "Value %3d |\n",
880 i, 4 * j, pdadcValues[4 * j],
881 4 * j + 1, pdadcValues[4 * j + 1],
882 4 * j + 2, pdadcValues[4 * j + 2],
883 4 * j + 3,
884 pdadcValues[4 * j + 3]);
885
886 regOffset += 4;
887 }
888 }
889 }
890
891 *pTxPowerIndexOffset = 0;
892#undef SM_PD_GAIN
893#undef SM_PDGAIN_B
894}
895
896static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
897 struct ath9k_channel *chan,
898 int16_t *ratesArray,
899 u16 cfgCtl,
900 u16 AntennaReduction,
901 u16 twiceMaxRegulatoryPower,
902 u16 powerLimit)
903{
904#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
905#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
906
907 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
908 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
909 static const u16 tpScaleReductionTable[5] =
910 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
911
912 int i;
913 int16_t twiceLargestAntenna;
914 struct cal_ctl_data *rep;
915 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
916 0, { 0, 0, 0, 0}
917 };
918 struct cal_target_power_leg targetPowerOfdmExt = {
919 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
920 0, { 0, 0, 0, 0 }
921 };
922 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
923 0, {0, 0, 0, 0}
924 };
925 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
926 u16 ctlModesFor11a[] =
927 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
928 u16 ctlModesFor11g[] =
929 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
930 CTL_2GHT40
931 };
932 u16 numCtlModes, *pCtlMode, ctlMode, freq;
933 struct chan_centers centers;
934 int tx_chainmask;
935 u16 twiceMinEdgePower;
936
937 tx_chainmask = ah->txchainmask;
938
939 ath9k_hw_get_channel_centers(ah, chan, &centers);
940
941 twiceLargestAntenna = max(
942 pEepData->modalHeader
943 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
944 pEepData->modalHeader
945 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
946
947 twiceLargestAntenna = max((u8)twiceLargestAntenna,
948 pEepData->modalHeader
949 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
950
951 twiceLargestAntenna = (int16_t)min(AntennaReduction -
952 twiceLargestAntenna, 0);
953
954 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
955
956 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
957 maxRegAllowedPower -=
958 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
959 }
960
961 scaledPower = min(powerLimit, maxRegAllowedPower);
962
963 switch (ar5416_get_ntxchains(tx_chainmask)) {
964 case 1:
965 break;
966 case 2:
967 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
968 break;
969 case 3:
970 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
971 break;
972 }
973
974 scaledPower = max((u16)0, scaledPower);
975
976 if (IS_CHAN_2GHZ(chan)) {
977 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
978 SUB_NUM_CTL_MODES_AT_2G_40;
979 pCtlMode = ctlModesFor11g;
980
981 ath9k_hw_get_legacy_target_powers(ah, chan,
982 pEepData->calTargetPowerCck,
983 AR5416_NUM_2G_CCK_TARGET_POWERS,
984 &targetPowerCck, 4, false);
985 ath9k_hw_get_legacy_target_powers(ah, chan,
986 pEepData->calTargetPower2G,
987 AR5416_NUM_2G_20_TARGET_POWERS,
988 &targetPowerOfdm, 4, false);
989 ath9k_hw_get_target_powers(ah, chan,
990 pEepData->calTargetPower2GHT20,
991 AR5416_NUM_2G_20_TARGET_POWERS,
992 &targetPowerHt20, 8, false);
993
994 if (IS_CHAN_HT40(chan)) {
995 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
996 ath9k_hw_get_target_powers(ah, chan,
997 pEepData->calTargetPower2GHT40,
998 AR5416_NUM_2G_40_TARGET_POWERS,
999 &targetPowerHt40, 8, true);
1000 ath9k_hw_get_legacy_target_powers(ah, chan,
1001 pEepData->calTargetPowerCck,
1002 AR5416_NUM_2G_CCK_TARGET_POWERS,
1003 &targetPowerCckExt, 4, true);
1004 ath9k_hw_get_legacy_target_powers(ah, chan,
1005 pEepData->calTargetPower2G,
1006 AR5416_NUM_2G_20_TARGET_POWERS,
1007 &targetPowerOfdmExt, 4, true);
1008 }
1009 } else {
1010 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1011 SUB_NUM_CTL_MODES_AT_5G_40;
1012 pCtlMode = ctlModesFor11a;
1013
1014 ath9k_hw_get_legacy_target_powers(ah, chan,
1015 pEepData->calTargetPower5G,
1016 AR5416_NUM_5G_20_TARGET_POWERS,
1017 &targetPowerOfdm, 4, false);
1018 ath9k_hw_get_target_powers(ah, chan,
1019 pEepData->calTargetPower5GHT20,
1020 AR5416_NUM_5G_20_TARGET_POWERS,
1021 &targetPowerHt20, 8, false);
1022
1023 if (IS_CHAN_HT40(chan)) {
1024 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1025 ath9k_hw_get_target_powers(ah, chan,
1026 pEepData->calTargetPower5GHT40,
1027 AR5416_NUM_5G_40_TARGET_POWERS,
1028 &targetPowerHt40, 8, true);
1029 ath9k_hw_get_legacy_target_powers(ah, chan,
1030 pEepData->calTargetPower5G,
1031 AR5416_NUM_5G_20_TARGET_POWERS,
1032 &targetPowerOfdmExt, 4, true);
1033 }
1034 }
1035
1036 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1037 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1038 (pCtlMode[ctlMode] == CTL_2GHT40);
1039 if (isHt40CtlMode)
1040 freq = centers.synth_center;
1041 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1042 freq = centers.ext_center;
1043 else
1044 freq = centers.ctl_center;
1045
1046 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1047 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1048 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1049
1050 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1051 if ((((cfgCtl & ~CTL_MODE_M) |
1052 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1053 pEepData->ctlIndex[i]) ||
1054 (((cfgCtl & ~CTL_MODE_M) |
1055 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1056 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1057 rep = &(pEepData->ctlData[i]);
1058
1059 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1060 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1061 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1062
1063 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1064 twiceMaxEdgePower = min(twiceMaxEdgePower,
1065 twiceMinEdgePower);
1066 } else {
1067 twiceMaxEdgePower = twiceMinEdgePower;
1068 break;
1069 }
1070 }
1071 }
1072
1073 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1074
1075 switch (pCtlMode[ctlMode]) {
1076 case CTL_11B:
1077 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1078 targetPowerCck.tPow2x[i] =
1079 min((u16)targetPowerCck.tPow2x[i],
1080 minCtlPower);
1081 }
1082 break;
1083 case CTL_11A:
1084 case CTL_11G:
1085 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1086 targetPowerOfdm.tPow2x[i] =
1087 min((u16)targetPowerOfdm.tPow2x[i],
1088 minCtlPower);
1089 }
1090 break;
1091 case CTL_5GHT20:
1092 case CTL_2GHT20:
1093 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1094 targetPowerHt20.tPow2x[i] =
1095 min((u16)targetPowerHt20.tPow2x[i],
1096 minCtlPower);
1097 }
1098 break;
1099 case CTL_11B_EXT:
1100 targetPowerCckExt.tPow2x[0] = min((u16)
1101 targetPowerCckExt.tPow2x[0],
1102 minCtlPower);
1103 break;
1104 case CTL_11A_EXT:
1105 case CTL_11G_EXT:
1106 targetPowerOfdmExt.tPow2x[0] = min((u16)
1107 targetPowerOfdmExt.tPow2x[0],
1108 minCtlPower);
1109 break;
1110 case CTL_5GHT40:
1111 case CTL_2GHT40:
1112 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1113 targetPowerHt40.tPow2x[i] =
1114 min((u16)targetPowerHt40.tPow2x[i],
1115 minCtlPower);
1116 }
1117 break;
1118 default:
1119 break;
1120 }
1121 }
1122
1123 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1124 ratesArray[rate18mb] = ratesArray[rate24mb] =
1125 targetPowerOfdm.tPow2x[0];
1126 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1127 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1128 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1129 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1130
1131 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1132 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1133
1134 if (IS_CHAN_2GHZ(chan)) {
1135 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1136 ratesArray[rate2s] = ratesArray[rate2l] =
1137 targetPowerCck.tPow2x[1];
1138 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1139 targetPowerCck.tPow2x[2];
1140 ratesArray[rate11s] = ratesArray[rate11l] =
1141 targetPowerCck.tPow2x[3];
1142 }
1143 if (IS_CHAN_HT40(chan)) {
1144 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1145 ratesArray[rateHt40_0 + i] =
1146 targetPowerHt40.tPow2x[i];
1147 }
1148 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1149 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1150 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1151 if (IS_CHAN_2GHZ(chan)) {
1152 ratesArray[rateExtCck] =
1153 targetPowerCckExt.tPow2x[0];
1154 }
1155 }
1156}
1157
1158static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1159 struct ath9k_channel *chan,
1160 u16 cfgCtl,
1161 u8 twiceAntennaReduction,
1162 u8 twiceMaxRegulatoryPower,
1163 u8 powerLimit)
1164{
1165#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1166 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1167 struct modal_eep_header *pModal =
1168 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1169 int16_t ratesArray[Ar5416RateSize];
1170 int16_t txPowerIndexOffset = 0;
1171 u8 ht40PowerIncForPdadc = 2;
1172 int i, cck_ofdm_delta = 0;
1173
1174 memset(ratesArray, 0, sizeof(ratesArray));
1175
1176 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1177 AR5416_EEP_MINOR_VER_2) {
1178 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1179 }
1180
1181 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1182 &ratesArray[0], cfgCtl,
1183 twiceAntennaReduction,
1184 twiceMaxRegulatoryPower,
1185 powerLimit);
1186
1187 ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1188
1189 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1190 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1191 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1192 ratesArray[i] = AR5416_MAX_RATE_POWER;
1193 }
1194
1195 if (AR_SREV_9280_10_OR_LATER(ah)) {
1196 for (i = 0; i < Ar5416RateSize; i++)
1197 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1198 }
1199
1200 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1201 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1202 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1203 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1204 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1205 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1206 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1207 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1208 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1209 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1210
1211 if (IS_CHAN_2GHZ(chan)) {
1212 if (OLC_FOR_AR9280_20_LATER) {
1213 cck_ofdm_delta = 2;
1214 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1215 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1216 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1217 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1218 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1219 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1220 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1221 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1222 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1223 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1224 } else {
1225 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1226 ATH9K_POW_SM(ratesArray[rate2s], 24)
1227 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1228 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1229 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1230 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1231 ATH9K_POW_SM(ratesArray[rate11s], 24)
1232 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1233 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1234 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1235 }
1236 }
1237
1238 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1239 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1240 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1241 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1242 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1243 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1244 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1245 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1246 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1247 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1248
1249 if (IS_CHAN_HT40(chan)) {
1250 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1251 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1252 ht40PowerIncForPdadc, 24)
1253 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1254 ht40PowerIncForPdadc, 16)
1255 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1256 ht40PowerIncForPdadc, 8)
1257 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1258 ht40PowerIncForPdadc, 0));
1259 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1260 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1261 ht40PowerIncForPdadc, 24)
1262 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1263 ht40PowerIncForPdadc, 16)
1264 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1265 ht40PowerIncForPdadc, 8)
1266 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1267 ht40PowerIncForPdadc, 0));
1268 if (OLC_FOR_AR9280_20_LATER) {
1269 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1270 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1271 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1272 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1273 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1274 } else {
1275 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1276 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1277 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1278 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1279 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1280 }
1281 }
1282
1283 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1284 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1285 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1286
1287 i = rate6mb;
1288
1289 if (IS_CHAN_HT40(chan))
1290 i = rateHt40_0;
1291 else if (IS_CHAN_HT20(chan))
1292 i = rateHt20_0;
1293
1294 if (AR_SREV_9280_10_OR_LATER(ah))
1295 ah->regulatory.max_power_level =
1296 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1297 else
1298 ah->regulatory.max_power_level = ratesArray[i];
1299
1300 switch(ar5416_get_ntxchains(ah->txchainmask)) {
1301 case 1:
1302 break;
1303 case 2:
1304 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1305 break;
1306 case 3:
1307 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1308 break;
1309 default:
1310 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1311 "Invalid chainmask configuration\n");
1312 break;
1313 }
1314}
1315
1316static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1317 enum ieee80211_band freq_band)
1318{
1319 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1320 struct modal_eep_header *pModal =
1321 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
1322 struct base_eep_header *pBase = &eep->baseEepHeader;
1323 u8 num_ant_config;
1324
1325 num_ant_config = 1;
1326
1327 if (pBase->version >= 0x0E0D)
1328 if (pModal->useAnt1)
1329 num_ant_config += 1;
1330
1331 return num_ant_config;
1332}
1333
1334static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1335 struct ath9k_channel *chan)
1336{
1337 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1338 struct modal_eep_header *pModal =
1339 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1340
1341 return pModal->antCtrlCommon & 0xFFFF;
1342}
1343
1344static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1345{
1346#define EEP_DEF_SPURCHAN \
1347 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1348
1349 u16 spur_val = AR_NO_SPUR;
1350
1351 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1352 "Getting spur idx %d is2Ghz. %d val %x\n",
1353 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1354
1355 switch (ah->config.spurmode) {
1356 case SPUR_DISABLE:
1357 break;
1358 case SPUR_ENABLE_IOCTL:
1359 spur_val = ah->config.spurchans[i][is2GHz];
1360 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1361 "Getting spur val from new loc. %d\n", spur_val);
1362 break;
1363 case SPUR_ENABLE_EEPROM:
1364 spur_val = EEP_DEF_SPURCHAN;
1365 break;
1366 }
1367
1368 return spur_val;
1369
1370#undef EEP_DEF_SPURCHAN
1371}
1372
1373const struct eeprom_ops eep_def_ops = {
1374 .check_eeprom = ath9k_hw_def_check_eeprom,
1375 .get_eeprom = ath9k_hw_def_get_eeprom,
1376 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1377 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1378 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
1379 .get_num_ant_config = ath9k_hw_def_get_num_ant_config,
1380 .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1381 .set_board_values = ath9k_hw_def_set_board_values,
1382 .set_addac = ath9k_hw_def_set_addac,
1383 .set_txpower = ath9k_hw_def_set_txpower,
1384 .get_spur_channel = ath9k_hw_def_get_spur_channel
1385};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-21 17:24:37 -0500