Merge tag 'for-v3.19/omap-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into tmp

Some OMAP clock/hwmod patches for v3.19.

Most of the patches are clock-related.  The DPLL implementation is
changed to better align to the common clock framework.
There is also a patch that removes a few lines from the hwmod code -
this patch should have no functional effect.

Basic build, boot, and PM test logs for these patches can be found here:

http://www.pwsan.com/omap/testlogs/omap-a-for-v3.19/20141113094101/

1 files changed, 15 insertions, 0 deletions

diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 79791e1bf282..85ac0dd501de 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -33,6 +33,9 @@ static const struct clk_ops dpll_m4xen_ck_ops = {
         .recalc_rate    = &omap4_dpll_regm4xen_recalc,
         .round_rate     = &omap4_dpll_regm4xen_round_rate,
         .set_rate       = &omap3_noncore_dpll_set_rate,
+        .set_parent     = &omap3_noncore_dpll_set_parent,
+        .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
+        .determine_rate = &omap4_dpll_regm4xen_determine_rate,
         .get_parent     = &omap2_init_dpll_parent,
 };
 #else
@@ -53,6 +56,9 @@ static const struct clk_ops dpll_ck_ops = {
         .recalc_rate    = &omap3_dpll_recalc,
         .round_rate     = &omap2_dpll_round_rate,
         .set_rate       = &omap3_noncore_dpll_set_rate,
+        .set_parent     = &omap3_noncore_dpll_set_parent,
+        .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
+        .determine_rate = &omap3_noncore_dpll_determine_rate,
         .get_parent     = &omap2_init_dpll_parent,
 };
 
@@ -61,6 +67,9 @@ static const struct clk_ops dpll_no_gate_ck_ops = {
         .get_parent     = &omap2_init_dpll_parent,
         .round_rate     = &omap2_dpll_round_rate,
         .set_rate       = &omap3_noncore_dpll_set_rate,
+        .set_parent     = &omap3_noncore_dpll_set_parent,
+        .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
+        .determine_rate = &omap3_noncore_dpll_determine_rate,
 };
 #else
 static const struct clk_ops dpll_core_ck_ops = {};
@@ -97,6 +106,9 @@ static const struct clk_ops omap3_dpll_ck_ops = {
         .get_parent     = &omap2_init_dpll_parent,
         .recalc_rate    = &omap3_dpll_recalc,
         .set_rate       = &omap3_noncore_dpll_set_rate,
+        .set_parent     = &omap3_noncore_dpll_set_parent,
+        .set_rate_and_parent    = &omap3_noncore_dpll_set_rate_and_parent,
+        .determine_rate = &omap3_noncore_dpll_determine_rate,
         .round_rate     = &omap2_dpll_round_rate,
 };
 
@@ -106,6 +118,9 @@ static const struct clk_ops omap3_dpll_per_ck_ops = {
         .get_parent     = &omap2_init_dpll_parent,
         .recalc_rate    = &omap3_dpll_recalc,
         .set_rate       = &omap3_dpll4_set_rate,
+        .set_parent     = &omap3_noncore_dpll_set_parent,
+        .set_rate_and_parent    = &omap3_dpll4_set_rate_and_parent,
+        .determine_rate = &omap3_noncore_dpll_determine_rate,
         .round_rate     = &omap2_dpll_round_rate,
 };
 #endif