drm/i915: Disable M2 frac division for integer case

v2 : Handle M2 frac division for both M2 frac and int cases

v3 : Addressed Ville's review comments. Cleared the old bits for RMW

v4 : Fix feedfwd gain (Ville)

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 11 insertions, 4 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f700922bcb56..17b662f0849d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1029,6 +1029,7 @@ enum skl_disp_power_wells {
 #define  DPIO_CHV_FIRST_MOD             (0 << 8)
 #define  DPIO_CHV_SECOND_MOD            (1 << 8)
 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT    0
+#define  DPIO_CHV_FEEDFWD_GAIN_MASK             (0xF << 0)
 #define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
 
 #define _CHV_PLL_DW6_CH0                0x8018
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c3a58886b32f..8676cb8deaf8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6161,6 +6161,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
         enum dpio_channel port = vlv_pipe_to_channel(pipe);
         u32 loopfilter, intcoeff;
         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
+        u32 dpio_val;
         int refclk;
 
         bestn = pipe_config->dpll.n;
@@ -6169,6 +6170,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
         bestm2 = pipe_config->dpll.m2 >> 22;
         bestp1 = pipe_config->dpll.p1;
         bestp2 = pipe_config->dpll.p2;
+        dpio_val = 0;
 
         /*
          * Enable Refclk and SSC
@@ -6194,12 +6196,16 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
                         1 << DPIO_CHV_N_DIV_SHIFT);
 
         /* M2 fraction division */
-        vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
+        if (bestm2_frac)
+                vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
 
         /* M2 fraction division enable */
-        vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
-                       DPIO_CHV_FRAC_DIV_EN |
-                       (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
+        dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
+        dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
+        dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+        if (bestm2_frac)
+                dpio_val |= DPIO_CHV_FRAC_DIV_EN;
+        vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
 
         /* Loop filter */
         refclk = i9xx_get_refclk(crtc, 0);