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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 12:03:55 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-02 12:03:55 -0400
commita7726350e06401929eac0aa0677a5467106565fc (patch)
treee189513e5014bdfccd73a3af731a6b57733743fa /drivers
parent4d26aa305414dbb33b3c32fb205b68004cda8ffc (diff)
parentafcf7924ecab726dab0227188783c4a40d9f0eec (diff)
Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanup from Olof Johansson: "Here is a collection of cleanup patches. Among the pieces that stand out are: - The deletion of h720x platforms - Split of at91 non-dt platforms to their own Kconfig file to keep them separate - General cleanups and refactoring of i.MX and MXS platforms - Some restructuring of clock tables for OMAP - Convertion of PMC driver for Tegra to dt-only - Some renames of sunxi -> sun4i (Allwinner A10) - ... plus a bunch of other stuff that I haven't mentioned" * tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (119 commits) ARM: i.MX: remove unused ARCH_* configs ARM i.MX53: remove platform ahci support ARM: sunxi: Rework the restart code irqchip: sunxi: Rename sunxi to sun4i irqchip: sunxi: Make use of the IRQCHIP_DECLARE macro clocksource: sunxi: Rename sunxi to sun4i clocksource: sunxi: make use of CLKSRC_OF clocksource: sunxi: Cleanup the timer code ARM: at91: remove trailing semicolon from macros ARM: at91/setup: fix trivial typos ARM: EXYNOS: remove "config EXYNOS_DEV_DRM" ARM: EXYNOS: change the name of USB ohci header ARM: SAMSUNG: Remove unnecessary code for dma ARM: S3C24XX: Remove unused GPIO drive strength register definitions ARM: OMAP4+: PM: Restore CPU power state to ON with clockdomain force wakeup method ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2412 ARM: S3C24XX: Removed unneeded dependency on CPU_S3C2410 ARM: S3C24XX: Removed unneeded dependency on ARCH_S3C24XX for boards ARM: SAMSUNG: Fix typo "CONFIG_SAMSUNG_DEV_RTC" ARM: S5P64X0: Fix typo "CONFIG_S5P64X0_SETUP_SDHCI" ...
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/mxs/clk-imx23.c42
-rw-r--r--drivers/clk/mxs/clk-imx28.c42
-rw-r--r--drivers/clocksource/Kconfig2
-rw-r--r--drivers/clocksource/Makefile3
-rw-r--r--drivers/clocksource/bcm2835_timer.c12
-rw-r--r--drivers/clocksource/clksrc-of.c5
-rw-r--r--drivers/clocksource/mxs_timer.c304
-rw-r--r--drivers/clocksource/sun4i_timer.c (renamed from drivers/clocksource/sunxi_timer.c)94
-rw-r--r--drivers/clocksource/tegra20_timer.c75
-rw-r--r--drivers/clocksource/vt8500_timer.c16
-rw-r--r--drivers/gpio/gpio-msm-v1.c220
-rw-r--r--drivers/gpio/gpio-msm-v2.c3
-rw-r--r--drivers/gpio/gpio-mxc.c2
-rw-r--r--drivers/gpio/gpio-omap.c3
-rw-r--r--drivers/gpio/gpio-pl061.c2
-rw-r--r--drivers/gpio/gpio-pxa.c3
-rw-r--r--drivers/gpio/gpio-tegra.c3
-rw-r--r--drivers/irqchip/Makefile3
-rw-r--r--drivers/irqchip/exynos-combiner.c1
-rw-r--r--drivers/irqchip/irq-gic.c36
-rw-r--r--drivers/irqchip/irq-mxs.c121
-rw-r--r--drivers/irqchip/irq-sun4i.c149
-rw-r--r--drivers/irqchip/irq-sunxi.c151
-rw-r--r--drivers/irqchip/irq-vic.c3
-rw-r--r--drivers/mmc/host/msm_sdcc.c1
-rw-r--r--drivers/mmc/host/s3cmci.c83
-rw-r--r--drivers/pinctrl/pinctrl-at91.c3
-rw-r--r--drivers/pinctrl/pinctrl-exynos.c3
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c2
-rw-r--r--drivers/pinctrl/pinctrl-sirf.c2
-rw-r--r--drivers/pinctrl/spear/pinctrl-plgpio.c2
-rw-r--r--drivers/rtc/rtc-stmp3xxx.c6
-rw-r--r--drivers/staging/iio/adc/mxs-lradc.c3
-rw-r--r--drivers/staging/imx-drm/ipu-v3/ipu-common.c2
-rw-r--r--drivers/usb/host/ohci-exynos.c2
35 files changed, 973 insertions, 431 deletions
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index b5c06f9766f6..f6a74872f14e 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -15,12 +15,15 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/of.h> 17#include <linux/of.h>
18#include <mach/common.h> 18#include <linux/of_address.h>
19#include <mach/mx23.h>
20#include "clk.h" 19#include "clk.h"
21 20
22#define DIGCTRL MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR) 21static void __iomem *clkctrl;
23#define CLKCTRL MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR) 22static void __iomem *digctrl;
23
24#define CLKCTRL clkctrl
25#define DIGCTRL digctrl
26
24#define PLLCTRL0 (CLKCTRL + 0x0000) 27#define PLLCTRL0 (CLKCTRL + 0x0000)
25#define CPU (CLKCTRL + 0x0020) 28#define CPU (CLKCTRL + 0x0020)
26#define HBUS (CLKCTRL + 0x0030) 29#define HBUS (CLKCTRL + 0x0030)
@@ -48,10 +51,10 @@ static void __init clk_misc_init(void)
48 u32 val; 51 u32 val;
49 52
50 /* Gate off cpu clock in WFI for power saving */ 53 /* Gate off cpu clock in WFI for power saving */
51 __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU); 54 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
52 55
53 /* Clear BYPASS for SAIF */ 56 /* Clear BYPASS for SAIF */
54 __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ); 57 writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR);
55 58
56 /* SAIF has to use frac div for functional operation */ 59 /* SAIF has to use frac div for functional operation */
57 val = readl_relaxed(SAIF); 60 val = readl_relaxed(SAIF);
@@ -62,14 +65,14 @@ static void __init clk_misc_init(void)
62 * Source ssp clock from ref_io than ref_xtal, 65 * Source ssp clock from ref_io than ref_xtal,
63 * as ref_xtal only provides 24 MHz as maximum. 66 * as ref_xtal only provides 24 MHz as maximum.
64 */ 67 */
65 __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ); 68 writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR);
66 69
67 /* 70 /*
68 * 480 MHz seems too high to be ssp clock source directly, 71 * 480 MHz seems too high to be ssp clock source directly,
69 * so set frac to get a 288 MHz ref_io. 72 * so set frac to get a 288 MHz ref_io.
70 */ 73 */
71 __mxs_clrl(0x3f << BP_FRAC_IOFRAC, FRAC); 74 writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
72 __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC); 75 writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
73} 76}
74 77
75static const char *sel_pll[] __initconst = { "pll", "ref_xtal", }; 78static const char *sel_pll[] __initconst = { "pll", "ref_xtal", };
@@ -101,6 +104,14 @@ int __init mx23_clocks_init(void)
101 struct device_node *np; 104 struct device_node *np;
102 u32 i; 105 u32 i;
103 106
107 np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
108 digctrl = of_iomap(np, 0);
109 WARN_ON(!digctrl);
110
111 np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
112 clkctrl = of_iomap(np, 0);
113 WARN_ON(!clkctrl);
114
104 clk_misc_init(); 115 clk_misc_init();
105 116
106 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); 117 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
@@ -153,19 +164,12 @@ int __init mx23_clocks_init(void)
153 return PTR_ERR(clks[i]); 164 return PTR_ERR(clks[i]);
154 } 165 }
155 166
156 np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl"); 167 clk_data.clks = clks;
157 if (np) { 168 clk_data.clk_num = ARRAY_SIZE(clks);
158 clk_data.clks = clks; 169 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
159 clk_data.clk_num = ARRAY_SIZE(clks);
160 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
161 }
162
163 clk_register_clkdev(clks[clk32k], NULL, "timrot");
164 170
165 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 171 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
166 clk_prepare_enable(clks[clks_init_on[i]]); 172 clk_prepare_enable(clks[clks_init_on[i]]);
167 173
168 mxs_timer_init();
169
170 return 0; 174 return 0;
171} 175}
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 76ce6c6d1113..d0e5eed146de 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -15,11 +15,12 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/of.h> 17#include <linux/of.h>
18#include <mach/common.h> 18#include <linux/of_address.h>
19#include <mach/mx28.h>
20#include "clk.h" 19#include "clk.h"
21 20
22#define CLKCTRL MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR) 21static void __iomem *clkctrl;
22#define CLKCTRL clkctrl
23
23#define PLL0CTRL0 (CLKCTRL + 0x0000) 24#define PLL0CTRL0 (CLKCTRL + 0x0000)
24#define PLL1CTRL0 (CLKCTRL + 0x0020) 25#define PLL1CTRL0 (CLKCTRL + 0x0020)
25#define PLL2CTRL0 (CLKCTRL + 0x0040) 26#define PLL2CTRL0 (CLKCTRL + 0x0040)
@@ -53,7 +54,8 @@
53#define BP_FRAC0_IO1FRAC 16 54#define BP_FRAC0_IO1FRAC 16
54#define BP_FRAC0_IO0FRAC 24 55#define BP_FRAC0_IO0FRAC 24
55 56
56#define DIGCTRL MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR) 57static void __iomem *digctrl;
58#define DIGCTRL digctrl
57#define BP_SAIF_CLKMUX 10 59#define BP_SAIF_CLKMUX 10
58 60
59/* 61/*
@@ -72,8 +74,8 @@ int mxs_saif_clkmux_select(unsigned int clkmux)
72 if (clkmux > 0x3) 74 if (clkmux > 0x3)
73 return -EINVAL; 75 return -EINVAL;
74 76
75 __mxs_clrl(0x3 << BP_SAIF_CLKMUX, DIGCTRL); 77 writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR);
76 __mxs_setl(clkmux << BP_SAIF_CLKMUX, DIGCTRL); 78 writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET);
77 79
78 return 0; 80 return 0;
79} 81}
@@ -83,13 +85,13 @@ static void __init clk_misc_init(void)
83 u32 val; 85 u32 val;
84 86
85 /* Gate off cpu clock in WFI for power saving */ 87 /* Gate off cpu clock in WFI for power saving */
86 __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU); 88 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
87 89
88 /* 0 is a bad default value for a divider */ 90 /* 0 is a bad default value for a divider */
89 __mxs_setl(1 << BP_ENET_DIV_TIME, ENET); 91 writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
90 92
91 /* Clear BYPASS for SAIF */ 93 /* Clear BYPASS for SAIF */
92 __mxs_clrl(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ); 94 writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR);
93 95
94 /* SAIF has to use frac div for functional operation */ 96 /* SAIF has to use frac div for functional operation */
95 val = readl_relaxed(SAIF0); 97 val = readl_relaxed(SAIF0);
@@ -109,7 +111,7 @@ static void __init clk_misc_init(void)
109 * Source ssp clock from ref_io than ref_xtal, 111 * Source ssp clock from ref_io than ref_xtal,
110 * as ref_xtal only provides 24 MHz as maximum. 112 * as ref_xtal only provides 24 MHz as maximum.
111 */ 113 */
112 __mxs_clrl(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ); 114 writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
113 115
114 /* 116 /*
115 * 480 MHz seems too high to be ssp clock source directly, 117 * 480 MHz seems too high to be ssp clock source directly,
@@ -156,6 +158,14 @@ int __init mx28_clocks_init(void)
156 struct device_node *np; 158 struct device_node *np;
157 u32 i; 159 u32 i;
158 160
161 np = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl");
162 digctrl = of_iomap(np, 0);
163 WARN_ON(!digctrl);
164
165 np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
166 clkctrl = of_iomap(np, 0);
167 WARN_ON(!clkctrl);
168
159 clk_misc_init(); 169 clk_misc_init();
160 170
161 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000); 171 clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
@@ -231,20 +241,14 @@ int __init mx28_clocks_init(void)
231 return PTR_ERR(clks[i]); 241 return PTR_ERR(clks[i]);
232 } 242 }
233 243
234 np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl"); 244 clk_data.clks = clks;
235 if (np) { 245 clk_data.clk_num = ARRAY_SIZE(clks);
236 clk_data.clks = clks; 246 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
237 clk_data.clk_num = ARRAY_SIZE(clks);
238 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
239 }
240 247
241 clk_register_clkdev(clks[xbus], NULL, "timrot");
242 clk_register_clkdev(clks[enet_out], NULL, "enet_out"); 248 clk_register_clkdev(clks[enet_out], NULL, "enet_out");
243 249
244 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 250 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
245 clk_prepare_enable(clks[clks_init_on[i]]); 251 clk_prepare_enable(clks[clks_init_on[i]]);
246 252
247 mxs_timer_init();
248
249 return 0; 253 return 0;
250} 254}
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e507ab7df60b..9002185a0a1a 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -25,7 +25,7 @@ config DW_APB_TIMER_OF
25config ARMADA_370_XP_TIMER 25config ARMADA_370_XP_TIMER
26 bool 26 bool
27 27
28config SUNXI_TIMER 28config SUN4I_TIMER
29 bool 29 bool
30 30
31config VT8500_TIMER 31config VT8500_TIMER
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 96e25319659b..4897f243a000 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -16,7 +16,8 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o
16obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o 16obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
17obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o 17obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
18obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o 18obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
19obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o 19obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
20obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o
20obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o 21obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o
21obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o 22obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o
22obj-$(CONFIG_ARCH_BCM) += bcm_kona_timer.o 23obj-$(CONFIG_ARCH_BCM) += bcm_kona_timer.o
diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c
index 50c68fef944b..766611d29945 100644
--- a/drivers/clocksource/bcm2835_timer.c
+++ b/drivers/clocksource/bcm2835_timer.c
@@ -95,23 +95,13 @@ static irqreturn_t bcm2835_time_interrupt(int irq, void *dev_id)
95 } 95 }
96} 96}
97 97
98static struct of_device_id bcm2835_time_match[] __initconst = { 98static void __init bcm2835_timer_init(struct device_node *node)
99 { .compatible = "brcm,bcm2835-system-timer" },
100 {}
101};
102
103static void __init bcm2835_timer_init(void)
104{ 99{
105 struct device_node *node;
106 void __iomem *base; 100 void __iomem *base;
107 u32 freq; 101 u32 freq;
108 int irq; 102 int irq;
109 struct bcm2835_timer *timer; 103 struct bcm2835_timer *timer;
110 104
111 node = of_find_matching_node(NULL, bcm2835_time_match);
112 if (!node)
113 panic("No bcm2835 timer node");
114
115 base = of_iomap(node, 0); 105 base = of_iomap(node, 0);
116 if (!base) 106 if (!base)
117 panic("Can't remap registers"); 107 panic("Can't remap registers");
diff --git a/drivers/clocksource/clksrc-of.c b/drivers/clocksource/clksrc-of.c
index bdabdaa8d00f..37f5325bec95 100644
--- a/drivers/clocksource/clksrc-of.c
+++ b/drivers/clocksource/clksrc-of.c
@@ -16,6 +16,7 @@
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/of.h> 18#include <linux/of.h>
19#include <linux/clocksource.h>
19 20
20extern struct of_device_id __clksrc_of_table[]; 21extern struct of_device_id __clksrc_of_table[];
21 22
@@ -26,10 +27,10 @@ void __init clocksource_of_init(void)
26{ 27{
27 struct device_node *np; 28 struct device_node *np;
28 const struct of_device_id *match; 29 const struct of_device_id *match;
29 void (*init_func)(void); 30 clocksource_of_init_fn init_func;
30 31
31 for_each_matching_node_and_match(np, __clksrc_of_table, &match) { 32 for_each_matching_node_and_match(np, __clksrc_of_table, &match) {
32 init_func = match->data; 33 init_func = match->data;
33 init_func(); 34 init_func(np);
34 } 35 }
35} 36}
diff --git a/drivers/clocksource/mxs_timer.c b/drivers/clocksource/mxs_timer.c
new file mode 100644
index 000000000000..02af4204af86
--- /dev/null
+++ b/drivers/clocksource/mxs_timer.c
@@ -0,0 +1,304 @@
1/*
2 * Copyright (C) 2000-2001 Deep Blue Solutions
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#include <linux/err.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/clockchips.h>
27#include <linux/clk.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/stmp_device.h>
32
33#include <asm/mach/time.h>
34#include <asm/sched_clock.h>
35
36/*
37 * There are 2 versions of the timrot on Freescale MXS-based SoCs.
38 * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
39 * extends the counter to 32 bits.
40 *
41 * The implementation uses two timers, one for clock_event and
42 * another for clocksource. MX28 uses timrot 0 and 1, while MX23
43 * uses 0 and 2.
44 */
45
46#define MX23_TIMROT_VERSION_OFFSET 0x0a0
47#define MX28_TIMROT_VERSION_OFFSET 0x120
48#define BP_TIMROT_MAJOR_VERSION 24
49#define BV_TIMROT_VERSION_1 0x01
50#define BV_TIMROT_VERSION_2 0x02
51#define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1)
52
53/*
54 * There are 4 registers for each timrotv2 instance, and 2 registers
55 * for each timrotv1. So address step 0x40 in macros below strides
56 * one instance of timrotv2 while two instances of timrotv1.
57 *
58 * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
59 * on MX28 while timrot2 on MX23.
60 */
61/* common between v1 and v2 */
62#define HW_TIMROT_ROTCTRL 0x00
63#define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40)
64/* v1 only */
65#define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40)
66/* v2 only */
67#define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40)
68#define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40)
69
70#define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6)
71#define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7)
72#define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
73#define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
74#define BP_TIMROT_TIMCTRLn_SELECT 0
75#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
76#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
77#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS 0xf
78
79static struct clock_event_device mxs_clockevent_device;
80static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
81
82static void __iomem *mxs_timrot_base;
83static u32 timrot_major_version;
84
85static inline void timrot_irq_disable(void)
86{
87 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
88 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
89}
90
91static inline void timrot_irq_enable(void)
92{
93 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
94 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
95}
96
97static void timrot_irq_acknowledge(void)
98{
99 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
100 HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
101}
102
103static cycle_t timrotv1_get_cycles(struct clocksource *cs)
104{
105 return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
106 & 0xffff0000) >> 16);
107}
108
109static int timrotv1_set_next_event(unsigned long evt,
110 struct clock_event_device *dev)
111{
112 /* timrot decrements the count */
113 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
114
115 return 0;
116}
117
118static int timrotv2_set_next_event(unsigned long evt,
119 struct clock_event_device *dev)
120{
121 /* timrot decrements the count */
122 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
123
124 return 0;
125}
126
127static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
128{
129 struct clock_event_device *evt = dev_id;
130
131 timrot_irq_acknowledge();
132 evt->event_handler(evt);
133
134 return IRQ_HANDLED;
135}
136
137static struct irqaction mxs_timer_irq = {
138 .name = "MXS Timer Tick",
139 .dev_id = &mxs_clockevent_device,
140 .flags = IRQF_TIMER | IRQF_IRQPOLL,
141 .handler = mxs_timer_interrupt,
142};
143
144#ifdef DEBUG
145static const char *clock_event_mode_label[] const = {
146 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
147 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
148 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
149 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
150};
151#endif /* DEBUG */
152
153static void mxs_set_mode(enum clock_event_mode mode,
154 struct clock_event_device *evt)
155{
156 /* Disable interrupt in timer module */
157 timrot_irq_disable();
158
159 if (mode != mxs_clockevent_mode) {
160 /* Set event time into the furthest future */
161 if (timrot_is_v1())
162 __raw_writel(0xffff,
163 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
164 else
165 __raw_writel(0xffffffff,
166 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
167
168 /* Clear pending interrupt */
169 timrot_irq_acknowledge();
170 }
171
172#ifdef DEBUG
173 pr_info("%s: changing mode from %s to %s\n", __func__,
174 clock_event_mode_label[mxs_clockevent_mode],
175 clock_event_mode_label[mode]);
176#endif /* DEBUG */
177
178 /* Remember timer mode */
179 mxs_clockevent_mode = mode;
180
181 switch (mode) {
182 case CLOCK_EVT_MODE_PERIODIC:
183 pr_err("%s: Periodic mode is not implemented\n", __func__);
184 break;
185 case CLOCK_EVT_MODE_ONESHOT:
186 timrot_irq_enable();
187 break;
188 case CLOCK_EVT_MODE_SHUTDOWN:
189 case CLOCK_EVT_MODE_UNUSED:
190 case CLOCK_EVT_MODE_RESUME:
191 /* Left event sources disabled, no more interrupts appear */
192 break;
193 }
194}
195
196static struct clock_event_device mxs_clockevent_device = {
197 .name = "mxs_timrot",
198 .features = CLOCK_EVT_FEAT_ONESHOT,
199 .set_mode = mxs_set_mode,
200 .set_next_event = timrotv2_set_next_event,
201 .rating = 200,
202};
203
204static int __init mxs_clockevent_init(struct clk *timer_clk)
205{
206 if (timrot_is_v1())
207 mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
208 mxs_clockevent_device.cpumask = cpumask_of(0);
209 clockevents_config_and_register(&mxs_clockevent_device,
210 clk_get_rate(timer_clk),
211 timrot_is_v1() ? 0xf : 0x2,
212 timrot_is_v1() ? 0xfffe : 0xfffffffe);
213
214 return 0;
215}
216
217static struct clocksource clocksource_mxs = {
218 .name = "mxs_timer",
219 .rating = 200,
220 .read = timrotv1_get_cycles,
221 .mask = CLOCKSOURCE_MASK(16),
222 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
223};
224
225static u32 notrace mxs_read_sched_clock_v2(void)
226{
227 return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
228}
229
230static int __init mxs_clocksource_init(struct clk *timer_clk)
231{
232 unsigned int c = clk_get_rate(timer_clk);
233
234 if (timrot_is_v1())
235 clocksource_register_hz(&clocksource_mxs, c);
236 else {
237 clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
238 "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
239 setup_sched_clock(mxs_read_sched_clock_v2, 32, c);
240 }
241
242 return 0;
243}
244
245static void __init mxs_timer_init(struct device_node *np)
246{
247 struct clk *timer_clk;
248 int irq;
249
250 mxs_timrot_base = of_iomap(np, 0);
251 WARN_ON(!mxs_timrot_base);
252
253 timer_clk = of_clk_get(np, 0);
254 if (IS_ERR(timer_clk)) {
255 pr_err("%s: failed to get clk\n", __func__);
256 return;
257 }
258
259 clk_prepare_enable(timer_clk);
260
261 /*
262 * Initialize timers to a known state
263 */
264 stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
265
266 /* get timrot version */
267 timrot_major_version = __raw_readl(mxs_timrot_base +
268 (of_device_is_compatible(np, "fsl,imx23-timrot") ?
269 MX23_TIMROT_VERSION_OFFSET :
270 MX28_TIMROT_VERSION_OFFSET));
271 timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
272
273 /* one for clock_event */
274 __raw_writel((timrot_is_v1() ?
275 BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
276 BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
277 BM_TIMROT_TIMCTRLn_UPDATE |
278 BM_TIMROT_TIMCTRLn_IRQ_EN,
279 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
280
281 /* another for clocksource */
282 __raw_writel((timrot_is_v1() ?
283 BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
284 BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
285 BM_TIMROT_TIMCTRLn_RELOAD,
286 mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
287
288 /* set clocksource timer fixed count to the maximum */
289 if (timrot_is_v1())
290 __raw_writel(0xffff,
291 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
292 else
293 __raw_writel(0xffffffff,
294 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
295
296 /* init and register the timer to the framework */
297 mxs_clocksource_init(timer_clk);
298 mxs_clockevent_init(timer_clk);
299
300 /* Make irqs happen */
301 irq = irq_of_parse_and_map(np, 0);
302 setup_irq(irq, &mxs_timer_irq);
303}
304CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);
diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sun4i_timer.c
index 0ce85e29769b..d4674e78ef35 100644
--- a/drivers/clocksource/sunxi_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -22,66 +22,64 @@
22#include <linux/of.h> 22#include <linux/of.h>
23#include <linux/of_address.h> 23#include <linux/of_address.h>
24#include <linux/of_irq.h> 24#include <linux/of_irq.h>
25#include <linux/sunxi_timer.h>
26#include <linux/clk/sunxi.h>
27 25
28#define TIMER_CTL_REG 0x00 26#define TIMER_IRQ_EN_REG 0x00
29#define TIMER_CTL_ENABLE (1 << 0) 27#define TIMER_IRQ_EN(val) (1 << val)
30#define TIMER_IRQ_ST_REG 0x04 28#define TIMER_IRQ_ST_REG 0x04
31#define TIMER0_CTL_REG 0x10 29#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
32#define TIMER0_CTL_ENABLE (1 << 0) 30#define TIMER_CTL_ENABLE (1 << 0)
33#define TIMER0_CTL_AUTORELOAD (1 << 1) 31#define TIMER_CTL_AUTORELOAD (1 << 1)
34#define TIMER0_CTL_ONESHOT (1 << 7) 32#define TIMER_CTL_ONESHOT (1 << 7)
35#define TIMER0_INTVAL_REG 0x14 33#define TIMER_INTVAL_REG(val) (0x10 * val + 0x14)
36#define TIMER0_CNTVAL_REG 0x18 34#define TIMER_CNTVAL_REG(val) (0x10 * val + 0x18)
37 35
38#define TIMER_SCAL 16 36#define TIMER_SCAL 16
39 37
40static void __iomem *timer_base; 38static void __iomem *timer_base;
41 39
42static void sunxi_clkevt_mode(enum clock_event_mode mode, 40static void sun4i_clkevt_mode(enum clock_event_mode mode,
43 struct clock_event_device *clk) 41 struct clock_event_device *clk)
44{ 42{
45 u32 u = readl(timer_base + TIMER0_CTL_REG); 43 u32 u = readl(timer_base + TIMER_CTL_REG(0));
46 44
47 switch (mode) { 45 switch (mode) {
48 case CLOCK_EVT_MODE_PERIODIC: 46 case CLOCK_EVT_MODE_PERIODIC:
49 u &= ~(TIMER0_CTL_ONESHOT); 47 u &= ~(TIMER_CTL_ONESHOT);
50 writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG); 48 writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
51 break; 49 break;
52 50
53 case CLOCK_EVT_MODE_ONESHOT: 51 case CLOCK_EVT_MODE_ONESHOT:
54 writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG); 52 writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
55 break; 53 break;
56 case CLOCK_EVT_MODE_UNUSED: 54 case CLOCK_EVT_MODE_UNUSED:
57 case CLOCK_EVT_MODE_SHUTDOWN: 55 case CLOCK_EVT_MODE_SHUTDOWN:
58 default: 56 default:
59 writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG); 57 writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
60 break; 58 break;
61 } 59 }
62} 60}
63 61
64static int sunxi_clkevt_next_event(unsigned long evt, 62static int sun4i_clkevt_next_event(unsigned long evt,
65 struct clock_event_device *unused) 63 struct clock_event_device *unused)
66{ 64{
67 u32 u = readl(timer_base + TIMER0_CTL_REG); 65 u32 u = readl(timer_base + TIMER_CTL_REG(0));
68 writel(evt, timer_base + TIMER0_CNTVAL_REG); 66 writel(evt, timer_base + TIMER_CNTVAL_REG(0));
69 writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD, 67 writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
70 timer_base + TIMER0_CTL_REG); 68 timer_base + TIMER_CTL_REG(0));
71 69
72 return 0; 70 return 0;
73} 71}
74 72
75static struct clock_event_device sunxi_clockevent = { 73static struct clock_event_device sun4i_clockevent = {
76 .name = "sunxi_tick", 74 .name = "sun4i_tick",
77 .rating = 300, 75 .rating = 300,
78 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 76 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
79 .set_mode = sunxi_clkevt_mode, 77 .set_mode = sun4i_clkevt_mode,
80 .set_next_event = sunxi_clkevt_next_event, 78 .set_next_event = sun4i_clkevt_next_event,
81}; 79};
82 80
83 81
84static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id) 82static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
85{ 83{
86 struct clock_event_device *evt = (struct clock_event_device *)dev_id; 84 struct clock_event_device *evt = (struct clock_event_device *)dev_id;
87 85
@@ -91,30 +89,20 @@ static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
91 return IRQ_HANDLED; 89 return IRQ_HANDLED;
92} 90}
93 91
94static struct irqaction sunxi_timer_irq = { 92static struct irqaction sun4i_timer_irq = {
95 .name = "sunxi_timer0", 93 .name = "sun4i_timer0",
96 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 94 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
97 .handler = sunxi_timer_interrupt, 95 .handler = sun4i_timer_interrupt,
98 .dev_id = &sunxi_clockevent, 96 .dev_id = &sun4i_clockevent,
99};
100
101static struct of_device_id sunxi_timer_dt_ids[] = {
102 { .compatible = "allwinner,sunxi-timer" },
103 { }
104}; 97};
105 98
106void __init sunxi_timer_init(void) 99static void __init sun4i_timer_init(struct device_node *node)
107{ 100{
108 struct device_node *node;
109 unsigned long rate = 0; 101 unsigned long rate = 0;
110 struct clk *clk; 102 struct clk *clk;
111 int ret, irq; 103 int ret, irq;
112 u32 val; 104 u32 val;
113 105
114 node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
115 if (!node)
116 panic("No sunxi timer node");
117
118 timer_base = of_iomap(node, 0); 106 timer_base = of_iomap(node, 0);
119 if (!timer_base) 107 if (!timer_base)
120 panic("Can't map registers"); 108 panic("Can't map registers");
@@ -123,8 +111,6 @@ void __init sunxi_timer_init(void)
123 if (irq <= 0) 111 if (irq <= 0)
124 panic("Can't parse IRQ"); 112 panic("Can't parse IRQ");
125 113
126 sunxi_init_clocks();
127
128 clk = of_clk_get(node, 0); 114 clk = of_clk_get(node, 0);
129 if (IS_ERR(clk)) 115 if (IS_ERR(clk))
130 panic("Can't get timer clock"); 116 panic("Can't get timer clock");
@@ -132,29 +118,31 @@ void __init sunxi_timer_init(void)
132 rate = clk_get_rate(clk); 118 rate = clk_get_rate(clk);
133 119
134 writel(rate / (TIMER_SCAL * HZ), 120 writel(rate / (TIMER_SCAL * HZ),
135 timer_base + TIMER0_INTVAL_REG); 121 timer_base + TIMER_INTVAL_REG(0));
136 122
137 /* set clock source to HOSC, 16 pre-division */ 123 /* set clock source to HOSC, 16 pre-division */
138 val = readl(timer_base + TIMER0_CTL_REG); 124 val = readl(timer_base + TIMER_CTL_REG(0));
139 val &= ~(0x07 << 4); 125 val &= ~(0x07 << 4);
140 val &= ~(0x03 << 2); 126 val &= ~(0x03 << 2);
141 val |= (4 << 4) | (1 << 2); 127 val |= (4 << 4) | (1 << 2);
142 writel(val, timer_base + TIMER0_CTL_REG); 128 writel(val, timer_base + TIMER_CTL_REG(0));
143 129
144 /* set mode to auto reload */ 130 /* set mode to auto reload */
145 val = readl(timer_base + TIMER0_CTL_REG); 131 val = readl(timer_base + TIMER_CTL_REG(0));
146 writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG); 132 writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0));
147 133
148 ret = setup_irq(irq, &sunxi_timer_irq); 134 ret = setup_irq(irq, &sun4i_timer_irq);
149 if (ret) 135 if (ret)
150 pr_warn("failed to setup irq %d\n", irq); 136 pr_warn("failed to setup irq %d\n", irq);
151 137
152 /* Enable timer0 interrupt */ 138 /* Enable timer0 interrupt */
153 val = readl(timer_base + TIMER_CTL_REG); 139 val = readl(timer_base + TIMER_IRQ_EN_REG);
154 writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG); 140 writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
155 141
156 sunxi_clockevent.cpumask = cpumask_of(0); 142 sun4i_clockevent.cpumask = cpumask_of(0);
157 143
158 clockevents_config_and_register(&sunxi_clockevent, rate / TIMER_SCAL, 144 clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
159 0x1, 0xff); 145 0x1, 0xff);
160} 146}
147CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
148 sun4i_timer_init);
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index 0bde03feb095..ae877b021b54 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -154,29 +154,12 @@ static struct irqaction tegra_timer_irq = {
154 .dev_id = &tegra_clockevent, 154 .dev_id = &tegra_clockevent,
155}; 155};
156 156
157static const struct of_device_id timer_match[] __initconst = { 157static void __init tegra20_init_timer(struct device_node *np)
158 { .compatible = "nvidia,tegra20-timer" },
159 {}
160};
161
162static const struct of_device_id rtc_match[] __initconst = {
163 { .compatible = "nvidia,tegra20-rtc" },
164 {}
165};
166
167static void __init tegra20_init_timer(void)
168{ 158{
169 struct device_node *np;
170 struct clk *clk; 159 struct clk *clk;
171 unsigned long rate; 160 unsigned long rate;
172 int ret; 161 int ret;
173 162
174 np = of_find_matching_node(NULL, timer_match);
175 if (!np) {
176 pr_err("Failed to find timer DT node\n");
177 BUG();
178 }
179
180 timer_reg_base = of_iomap(np, 0); 163 timer_reg_base = of_iomap(np, 0);
181 if (!timer_reg_base) { 164 if (!timer_reg_base) {
182 pr_err("Can't map timer registers\n"); 165 pr_err("Can't map timer registers\n");
@@ -189,7 +172,7 @@ static void __init tegra20_init_timer(void)
189 BUG(); 172 BUG();
190 } 173 }
191 174
192 clk = clk_get_sys("timer", NULL); 175 clk = of_clk_get(np, 0);
193 if (IS_ERR(clk)) { 176 if (IS_ERR(clk)) {
194 pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); 177 pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
195 rate = 12000000; 178 rate = 12000000;
@@ -200,30 +183,6 @@ static void __init tegra20_init_timer(void)
200 183
201 of_node_put(np); 184 of_node_put(np);
202 185
203 np = of_find_matching_node(NULL, rtc_match);
204 if (!np) {
205 pr_err("Failed to find RTC DT node\n");
206 BUG();
207 }
208
209 rtc_base = of_iomap(np, 0);
210 if (!rtc_base) {
211 pr_err("Can't map RTC registers");
212 BUG();
213 }
214
215 /*
216 * rtc registers are used by read_persistent_clock, keep the rtc clock
217 * enabled
218 */
219 clk = clk_get_sys("rtc-tegra", NULL);
220 if (IS_ERR(clk))
221 pr_warn("Unable to get rtc-tegra clock\n");
222 else
223 clk_prepare_enable(clk);
224
225 of_node_put(np);
226
227 switch (rate) { 186 switch (rate) {
228 case 12000000: 187 case 12000000:
229 timer_writel(0x000b, TIMERUS_USEC_CFG); 188 timer_writel(0x000b, TIMERUS_USEC_CFG);
@@ -259,12 +218,34 @@ static void __init tegra20_init_timer(void)
259 tegra_clockevent.irq = tegra_timer_irq.irq; 218 tegra_clockevent.irq = tegra_timer_irq.irq;
260 clockevents_config_and_register(&tegra_clockevent, 1000000, 219 clockevents_config_and_register(&tegra_clockevent, 1000000,
261 0x1, 0x1fffffff); 220 0x1, 0x1fffffff);
262#ifdef CONFIG_HAVE_ARM_TWD 221}
263 twd_local_timer_of_register(); 222CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
264#endif 223
224static void __init tegra20_init_rtc(struct device_node *np)
225{
226 struct clk *clk;
227
228 rtc_base = of_iomap(np, 0);
229 if (!rtc_base) {
230 pr_err("Can't map RTC registers");
231 BUG();
232 }
233
234 /*
235 * rtc registers are used by read_persistent_clock, keep the rtc clock
236 * enabled
237 */
238 clk = of_clk_get(np, 0);
239 if (IS_ERR(clk))
240 pr_warn("Unable to get rtc-tegra clock\n");
241 else
242 clk_prepare_enable(clk);
243
244 of_node_put(np);
245
265 register_persistent_clock(NULL, tegra_read_persistent_clock); 246 register_persistent_clock(NULL, tegra_read_persistent_clock);
266} 247}
267CLOCKSOURCE_OF_DECLARE(tegra20, "nvidia,tegra20-timer", tegra20_init_timer); 248CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
268 249
269#ifdef CONFIG_PM 250#ifdef CONFIG_PM
270static u32 usec_config; 251static u32 usec_config;
diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/vt8500_timer.c
index 8efc86b5b5dd..64f553f04fa4 100644
--- a/drivers/clocksource/vt8500_timer.c
+++ b/drivers/clocksource/vt8500_timer.c
@@ -129,22 +129,10 @@ static struct irqaction irq = {
129 .dev_id = &clockevent, 129 .dev_id = &clockevent,
130}; 130};
131 131
132static struct of_device_id vt8500_timer_ids[] = { 132static void __init vt8500_timer_init(struct device_node *np)
133 { .compatible = "via,vt8500-timer" },
134 { }
135};
136
137static void __init vt8500_timer_init(void)
138{ 133{
139 struct device_node *np;
140 int timer_irq; 134 int timer_irq;
141 135
142 np = of_find_matching_node(NULL, vt8500_timer_ids);
143 if (!np) {
144 pr_err("%s: Timer description missing from Device Tree\n",
145 __func__);
146 return;
147 }
148 regbase = of_iomap(np, 0); 136 regbase = of_iomap(np, 0);
149 if (!regbase) { 137 if (!regbase) {
150 pr_err("%s: Missing iobase description in Device Tree\n", 138 pr_err("%s: Missing iobase description in Device Tree\n",
@@ -177,4 +165,4 @@ static void __init vt8500_timer_init(void)
177 4, 0xf0000000); 165 4, 0xf0000000);
178} 166}
179 167
180CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init) 168CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init);
diff --git a/drivers/gpio/gpio-msm-v1.c b/drivers/gpio/gpio-msm-v1.c
index 52a4d4286eba..c798585a3fe5 100644
--- a/drivers/gpio/gpio-msm-v1.c
+++ b/drivers/gpio/gpio-msm-v1.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
4 * 4 *
5 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and 6 * License version 2, as published by the Free Software Foundation, and
@@ -19,9 +19,10 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/module.h> 21#include <linux/module.h>
22#include <mach/cpu.h> 22#include <linux/device.h>
23#include <linux/platform_device.h>
24
23#include <mach/msm_gpiomux.h> 25#include <mach/msm_gpiomux.h>
24#include <mach/msm_iomap.h>
25 26
26/* see 80-VA736-2 Rev C pp 695-751 27/* see 80-VA736-2 Rev C pp 695-751
27** 28**
@@ -34,10 +35,10 @@
34** macros. 35** macros.
35*/ 36*/
36 37
37#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off)) 38#define MSM_GPIO1_REG(off) (off)
38#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off)) 39#define MSM_GPIO2_REG(off) (off)
39#define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off)) 40#define MSM_GPIO1_SHADOW_REG(off) (off)
40#define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off)) 41#define MSM_GPIO2_SHADOW_REG(off) (off)
41 42
42/* 43/*
43 * MSM7X00 registers 44 * MSM7X00 registers
@@ -276,16 +277,14 @@
276 277
277#define MSM_GPIO_BANK(soc, bank, first, last) \ 278#define MSM_GPIO_BANK(soc, bank, first, last) \
278 { \ 279 { \
279 .regs = { \ 280 .regs[MSM_GPIO_OUT] = soc##_GPIO_OUT_##bank, \
280 .out = soc##_GPIO_OUT_##bank, \ 281 .regs[MSM_GPIO_IN] = soc##_GPIO_IN_##bank, \
281 .in = soc##_GPIO_IN_##bank, \ 282 .regs[MSM_GPIO_INT_STATUS] = soc##_GPIO_INT_STATUS_##bank, \
282 .int_status = soc##_GPIO_INT_STATUS_##bank, \ 283 .regs[MSM_GPIO_INT_CLEAR] = soc##_GPIO_INT_CLEAR_##bank, \
283 .int_clear = soc##_GPIO_INT_CLEAR_##bank, \ 284 .regs[MSM_GPIO_INT_EN] = soc##_GPIO_INT_EN_##bank, \
284 .int_en = soc##_GPIO_INT_EN_##bank, \ 285 .regs[MSM_GPIO_INT_EDGE] = soc##_GPIO_INT_EDGE_##bank, \
285 .int_edge = soc##_GPIO_INT_EDGE_##bank, \ 286 .regs[MSM_GPIO_INT_POS] = soc##_GPIO_INT_POS_##bank, \
286 .int_pos = soc##_GPIO_INT_POS_##bank, \ 287 .regs[MSM_GPIO_OE] = soc##_GPIO_OE_##bank, \
287 .oe = soc##_GPIO_OE_##bank, \
288 }, \
289 .chip = { \ 288 .chip = { \
290 .base = (first), \ 289 .base = (first), \
291 .ngpio = (last) - (first) + 1, \ 290 .ngpio = (last) - (first) + 1, \
@@ -301,39 +300,57 @@
301 300
302#define MSM_GPIO_BROKEN_INT_CLEAR 1 301#define MSM_GPIO_BROKEN_INT_CLEAR 1
303 302
304struct msm_gpio_regs { 303enum msm_gpio_reg {
305 void __iomem *out; 304 MSM_GPIO_IN,
306 void __iomem *in; 305 MSM_GPIO_OUT,
307 void __iomem *int_status; 306 MSM_GPIO_INT_STATUS,
308 void __iomem *int_clear; 307 MSM_GPIO_INT_CLEAR,
309 void __iomem *int_en; 308 MSM_GPIO_INT_EN,
310 void __iomem *int_edge; 309 MSM_GPIO_INT_EDGE,
311 void __iomem *int_pos; 310 MSM_GPIO_INT_POS,
312 void __iomem *oe; 311 MSM_GPIO_OE,
312 MSM_GPIO_REG_NR
313}; 313};
314 314
315struct msm_gpio_chip { 315struct msm_gpio_chip {
316 spinlock_t lock; 316 spinlock_t lock;
317 struct gpio_chip chip; 317 struct gpio_chip chip;
318 struct msm_gpio_regs regs; 318 unsigned long regs[MSM_GPIO_REG_NR];
319#if MSM_GPIO_BROKEN_INT_CLEAR 319#if MSM_GPIO_BROKEN_INT_CLEAR
320 unsigned int_status_copy; 320 unsigned int_status_copy;
321#endif 321#endif
322 unsigned int both_edge_detect; 322 unsigned int both_edge_detect;
323 unsigned int int_enable[2]; /* 0: awake, 1: sleep */ 323 unsigned int int_enable[2]; /* 0: awake, 1: sleep */
324 void __iomem *base;
325};
326
327struct msm_gpio_initdata {
328 struct msm_gpio_chip *chips;
329 int count;
324}; 330};
325 331
332static void msm_gpio_writel(struct msm_gpio_chip *chip, u32 val,
333 enum msm_gpio_reg reg)
334{
335 writel(val, chip->base + chip->regs[reg]);
336}
337
338static u32 msm_gpio_readl(struct msm_gpio_chip *chip, enum msm_gpio_reg reg)
339{
340 return readl(chip->base + chip->regs[reg]);
341}
342
326static int msm_gpio_write(struct msm_gpio_chip *msm_chip, 343static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
327 unsigned offset, unsigned on) 344 unsigned offset, unsigned on)
328{ 345{
329 unsigned mask = BIT(offset); 346 unsigned mask = BIT(offset);
330 unsigned val; 347 unsigned val;
331 348
332 val = readl(msm_chip->regs.out); 349 val = msm_gpio_readl(msm_chip, MSM_GPIO_OUT);
333 if (on) 350 if (on)
334 writel(val | mask, msm_chip->regs.out); 351 msm_gpio_writel(msm_chip, val | mask, MSM_GPIO_OUT);
335 else 352 else
336 writel(val & ~mask, msm_chip->regs.out); 353 msm_gpio_writel(msm_chip, val & ~mask, MSM_GPIO_OUT);
337 return 0; 354 return 0;
338} 355}
339 356
@@ -342,13 +359,13 @@ static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
342 int loop_limit = 100; 359 int loop_limit = 100;
343 unsigned pol, val, val2, intstat; 360 unsigned pol, val, val2, intstat;
344 do { 361 do {
345 val = readl(msm_chip->regs.in); 362 val = msm_gpio_readl(msm_chip, MSM_GPIO_IN);
346 pol = readl(msm_chip->regs.int_pos); 363 pol = msm_gpio_readl(msm_chip, MSM_GPIO_INT_POS);
347 pol = (pol & ~msm_chip->both_edge_detect) | 364 pol = (pol & ~msm_chip->both_edge_detect) |
348 (~val & msm_chip->both_edge_detect); 365 (~val & msm_chip->both_edge_detect);
349 writel(pol, msm_chip->regs.int_pos); 366 msm_gpio_writel(msm_chip, pol, MSM_GPIO_INT_POS);
350 intstat = readl(msm_chip->regs.int_status); 367 intstat = msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
351 val2 = readl(msm_chip->regs.in); 368 val2 = msm_gpio_readl(msm_chip, MSM_GPIO_IN);
352 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0) 369 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
353 return; 370 return;
354 } while (loop_limit-- > 0); 371 } while (loop_limit-- > 0);
@@ -365,10 +382,11 @@ static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
365 /* Save interrupts that already triggered before we loose them. */ 382 /* Save interrupts that already triggered before we loose them. */
366 /* Any interrupt that triggers between the read of int_status */ 383 /* Any interrupt that triggers between the read of int_status */
367 /* and the write to int_clear will still be lost though. */ 384 /* and the write to int_clear will still be lost though. */
368 msm_chip->int_status_copy |= readl(msm_chip->regs.int_status); 385 msm_chip->int_status_copy |=
386 msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
369 msm_chip->int_status_copy &= ~bit; 387 msm_chip->int_status_copy &= ~bit;
370#endif 388#endif
371 writel(bit, msm_chip->regs.int_clear); 389 msm_gpio_writel(msm_chip, bit, MSM_GPIO_INT_CLEAR);
372 msm_gpio_update_both_edge_detect(msm_chip); 390 msm_gpio_update_both_edge_detect(msm_chip);
373 return 0; 391 return 0;
374} 392}
@@ -377,10 +395,12 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
377{ 395{
378 struct msm_gpio_chip *msm_chip; 396 struct msm_gpio_chip *msm_chip;
379 unsigned long irq_flags; 397 unsigned long irq_flags;
398 u32 val;
380 399
381 msm_chip = container_of(chip, struct msm_gpio_chip, chip); 400 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
382 spin_lock_irqsave(&msm_chip->lock, irq_flags); 401 spin_lock_irqsave(&msm_chip->lock, irq_flags);
383 writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe); 402 val = msm_gpio_readl(msm_chip, MSM_GPIO_OE) & ~BIT(offset);
403 msm_gpio_writel(msm_chip, val, MSM_GPIO_OE);
384 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); 404 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
385 return 0; 405 return 0;
386} 406}
@@ -390,11 +410,13 @@ msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
390{ 410{
391 struct msm_gpio_chip *msm_chip; 411 struct msm_gpio_chip *msm_chip;
392 unsigned long irq_flags; 412 unsigned long irq_flags;
413 u32 val;
393 414
394 msm_chip = container_of(chip, struct msm_gpio_chip, chip); 415 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
395 spin_lock_irqsave(&msm_chip->lock, irq_flags); 416 spin_lock_irqsave(&msm_chip->lock, irq_flags);
396 msm_gpio_write(msm_chip, offset, value); 417 msm_gpio_write(msm_chip, offset, value);
397 writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe); 418 val = msm_gpio_readl(msm_chip, MSM_GPIO_OE) | BIT(offset);
419 msm_gpio_writel(msm_chip, val, MSM_GPIO_OE);
398 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); 420 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
399 return 0; 421 return 0;
400} 422}
@@ -404,7 +426,7 @@ static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
404 struct msm_gpio_chip *msm_chip; 426 struct msm_gpio_chip *msm_chip;
405 427
406 msm_chip = container_of(chip, struct msm_gpio_chip, chip); 428 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
407 return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0; 429 return (msm_gpio_readl(msm_chip, MSM_GPIO_IN) & (1U << offset)) ? 1 : 0;
408} 430}
409 431
410static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 432static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -450,6 +472,11 @@ static struct msm_gpio_chip msm_gpio_chips_msm7x01[] = {
450 MSM_GPIO_BANK(MSM7X00, 5, 107, 121), 472 MSM_GPIO_BANK(MSM7X00, 5, 107, 121),
451}; 473};
452 474
475static struct msm_gpio_initdata msm_gpio_7x01_init = {
476 .chips = msm_gpio_chips_msm7x01,
477 .count = ARRAY_SIZE(msm_gpio_chips_msm7x01),
478};
479
453static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = { 480static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = {
454 MSM_GPIO_BANK(MSM7X30, 0, 0, 15), 481 MSM_GPIO_BANK(MSM7X30, 0, 0, 15),
455 MSM_GPIO_BANK(MSM7X30, 1, 16, 43), 482 MSM_GPIO_BANK(MSM7X30, 1, 16, 43),
@@ -461,6 +488,11 @@ static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = {
461 MSM_GPIO_BANK(MSM7X30, 7, 151, 181), 488 MSM_GPIO_BANK(MSM7X30, 7, 151, 181),
462}; 489};
463 490
491static struct msm_gpio_initdata msm_gpio_7x30_init = {
492 .chips = msm_gpio_chips_msm7x30,
493 .count = ARRAY_SIZE(msm_gpio_chips_msm7x30),
494};
495
464static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = { 496static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = {
465 MSM_GPIO_BANK(QSD8X50, 0, 0, 15), 497 MSM_GPIO_BANK(QSD8X50, 0, 0, 15),
466 MSM_GPIO_BANK(QSD8X50, 1, 16, 42), 498 MSM_GPIO_BANK(QSD8X50, 1, 16, 42),
@@ -472,6 +504,11 @@ static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = {
472 MSM_GPIO_BANK(QSD8X50, 7, 153, 164), 504 MSM_GPIO_BANK(QSD8X50, 7, 153, 164),
473}; 505};
474 506
507static struct msm_gpio_initdata msm_gpio_8x50_init = {
508 .chips = msm_gpio_chips_qsd8x50,
509 .count = ARRAY_SIZE(msm_gpio_chips_qsd8x50),
510};
511
475static void msm_gpio_irq_ack(struct irq_data *d) 512static void msm_gpio_irq_ack(struct irq_data *d)
476{ 513{
477 unsigned long irq_flags; 514 unsigned long irq_flags;
@@ -490,10 +527,10 @@ static void msm_gpio_irq_mask(struct irq_data *d)
490 527
491 spin_lock_irqsave(&msm_chip->lock, irq_flags); 528 spin_lock_irqsave(&msm_chip->lock, irq_flags);
492 /* level triggered interrupts are also latched */ 529 /* level triggered interrupts are also latched */
493 if (!(readl(msm_chip->regs.int_edge) & BIT(offset))) 530 if (!(msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE) & BIT(offset)))
494 msm_gpio_clear_detect_status(msm_chip, offset); 531 msm_gpio_clear_detect_status(msm_chip, offset);
495 msm_chip->int_enable[0] &= ~BIT(offset); 532 msm_chip->int_enable[0] &= ~BIT(offset);
496 writel(msm_chip->int_enable[0], msm_chip->regs.int_en); 533 msm_gpio_writel(msm_chip, msm_chip->int_enable[0], MSM_GPIO_INT_EN);
497 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); 534 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
498} 535}
499 536
@@ -505,10 +542,10 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
505 542
506 spin_lock_irqsave(&msm_chip->lock, irq_flags); 543 spin_lock_irqsave(&msm_chip->lock, irq_flags);
507 /* level triggered interrupts are also latched */ 544 /* level triggered interrupts are also latched */
508 if (!(readl(msm_chip->regs.int_edge) & BIT(offset))) 545 if (!(msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE) & BIT(offset)))
509 msm_gpio_clear_detect_status(msm_chip, offset); 546 msm_gpio_clear_detect_status(msm_chip, offset);
510 msm_chip->int_enable[0] |= BIT(offset); 547 msm_chip->int_enable[0] |= BIT(offset);
511 writel(msm_chip->int_enable[0], msm_chip->regs.int_en); 548 msm_gpio_writel(msm_chip, msm_chip->int_enable[0], MSM_GPIO_INT_EN);
512 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); 549 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
513} 550}
514 551
@@ -537,12 +574,12 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
537 unsigned val, mask = BIT(offset); 574 unsigned val, mask = BIT(offset);
538 575
539 spin_lock_irqsave(&msm_chip->lock, irq_flags); 576 spin_lock_irqsave(&msm_chip->lock, irq_flags);
540 val = readl(msm_chip->regs.int_edge); 577 val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE);
541 if (flow_type & IRQ_TYPE_EDGE_BOTH) { 578 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
542 writel(val | mask, msm_chip->regs.int_edge); 579 msm_gpio_writel(msm_chip, val | mask, MSM_GPIO_INT_EDGE);
543 __irq_set_handler_locked(d->irq, handle_edge_irq); 580 __irq_set_handler_locked(d->irq, handle_edge_irq);
544 } else { 581 } else {
545 writel(val & ~mask, msm_chip->regs.int_edge); 582 msm_gpio_writel(msm_chip, val & ~mask, MSM_GPIO_INT_EDGE);
546 __irq_set_handler_locked(d->irq, handle_level_irq); 583 __irq_set_handler_locked(d->irq, handle_level_irq);
547 } 584 }
548 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 585 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
@@ -550,11 +587,12 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
550 msm_gpio_update_both_edge_detect(msm_chip); 587 msm_gpio_update_both_edge_detect(msm_chip);
551 } else { 588 } else {
552 msm_chip->both_edge_detect &= ~mask; 589 msm_chip->both_edge_detect &= ~mask;
553 val = readl(msm_chip->regs.int_pos); 590 val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_POS);
554 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) 591 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
555 writel(val | mask, msm_chip->regs.int_pos); 592 val |= mask;
556 else 593 else
557 writel(val & ~mask, msm_chip->regs.int_pos); 594 val &= ~mask;
595 msm_gpio_writel(msm_chip, val, MSM_GPIO_INT_POS);
558 } 596 }
559 spin_unlock_irqrestore(&msm_chip->lock, irq_flags); 597 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
560 return 0; 598 return 0;
@@ -567,7 +605,7 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
567 605
568 for (i = 0; i < msm_gpio_count; i++) { 606 for (i = 0; i < msm_gpio_count; i++) {
569 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i]; 607 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
570 val = readl(msm_chip->regs.int_status); 608 val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
571 val &= msm_chip->int_enable[0]; 609 val &= msm_chip->int_enable[0];
572 while (val) { 610 while (val) {
573 mask = val & -val; 611 mask = val & -val;
@@ -592,22 +630,36 @@ static struct irq_chip msm_gpio_irq_chip = {
592 .irq_set_type = msm_gpio_irq_set_type, 630 .irq_set_type = msm_gpio_irq_set_type,
593}; 631};
594 632
595static int __init msm_init_gpio(void) 633static int __devinit gpio_msm_v1_probe(struct platform_device *pdev)
596{ 634{
597 int i, j = 0; 635 int i, j = 0;
598 636 const struct platform_device_id *dev_id = platform_get_device_id(pdev);
599 if (cpu_is_msm7x01()) { 637 struct msm_gpio_initdata *data;
600 msm_gpio_chips = msm_gpio_chips_msm7x01; 638 int irq1, irq2;
601 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x01); 639 struct resource *res;
602 } else if (cpu_is_msm7x30()) { 640 void __iomem *base1, __iomem *base2;
603 msm_gpio_chips = msm_gpio_chips_msm7x30; 641
604 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x30); 642 data = (struct msm_gpio_initdata *)dev_id->driver_data;
605 } else if (cpu_is_qsd8x50()) { 643 msm_gpio_chips = data->chips;
606 msm_gpio_chips = msm_gpio_chips_qsd8x50; 644 msm_gpio_count = data->count;
607 msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_qsd8x50); 645
608 } else { 646 irq1 = platform_get_irq(pdev, 0);
609 return 0; 647 if (irq1 < 0)
610 } 648 return irq1;
649
650 irq2 = platform_get_irq(pdev, 1);
651 if (irq2 < 0)
652 return irq2;
653
654 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
655 base1 = devm_request_and_ioremap(&pdev->dev, res);
656 if (!base1)
657 return -EADDRNOTAVAIL;
658
659 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
660 base2 = devm_request_and_ioremap(&pdev->dev, res);
661 if (!base2)
662 return -EADDRNOTAVAIL;
611 663
612 for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { 664 for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
613 if (i - FIRST_GPIO_IRQ >= 665 if (i - FIRST_GPIO_IRQ >=
@@ -621,16 +673,42 @@ static int __init msm_init_gpio(void)
621 } 673 }
622 674
623 for (i = 0; i < msm_gpio_count; i++) { 675 for (i = 0; i < msm_gpio_count; i++) {
676 if (i == 1)
677 msm_gpio_chips[i].base = base2;
678 else
679 msm_gpio_chips[i].base = base1;
624 spin_lock_init(&msm_gpio_chips[i].lock); 680 spin_lock_init(&msm_gpio_chips[i].lock);
625 writel(0, msm_gpio_chips[i].regs.int_en); 681 msm_gpio_writel(&msm_gpio_chips[i], 0, MSM_GPIO_INT_EN);
626 gpiochip_add(&msm_gpio_chips[i].chip); 682 gpiochip_add(&msm_gpio_chips[i].chip);
627 } 683 }
628 684
629 irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); 685 irq_set_chained_handler(irq1, msm_gpio_irq_handler);
630 irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); 686 irq_set_chained_handler(irq2, msm_gpio_irq_handler);
631 irq_set_irq_wake(INT_GPIO_GROUP1, 1); 687 irq_set_irq_wake(irq1, 1);
632 irq_set_irq_wake(INT_GPIO_GROUP2, 2); 688 irq_set_irq_wake(irq2, 2);
633 return 0; 689 return 0;
634} 690}
635 691
636postcore_initcall(msm_init_gpio); 692static struct platform_device_id gpio_msm_v1_device_ids[] = {
693 { "gpio-msm-7201", (unsigned long)&msm_gpio_7x01_init },
694 { "gpio-msm-7x30", (unsigned long)&msm_gpio_7x30_init },
695 { "gpio-msm-8x50", (unsigned long)&msm_gpio_8x50_init },
696 { }
697};
698MODULE_DEVICE_TABLE(platform, gpio_msm_v1_device_ids);
699
700static struct platform_driver gpio_msm_v1_driver = {
701 .driver = {
702 .name = "gpio-msm-v1",
703 .owner = THIS_MODULE,
704 },
705 .probe = gpio_msm_v1_probe,
706 .id_table = gpio_msm_v1_device_ids,
707};
708
709static int __init gpio_msm_v1_init(void)
710{
711 return platform_driver_register(&gpio_msm_v1_driver);
712}
713postcore_initcall(gpio_msm_v1_init);
714MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-msm-v2.c b/drivers/gpio/gpio-msm-v2.c
index 55a7e7769af6..dd2eddeb1e0c 100644
--- a/drivers/gpio/gpio-msm-v2.c
+++ b/drivers/gpio/gpio-msm-v2.c
@@ -23,13 +23,12 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/irqchip/chained_irq.h>
26#include <linux/irq.h> 27#include <linux/irq.h>
27#include <linux/module.h> 28#include <linux/module.h>
28#include <linux/platform_device.h> 29#include <linux/platform_device.h>
29#include <linux/spinlock.h> 30#include <linux/spinlock.h>
30 31
31#include <asm/mach/irq.h>
32
33#include <mach/msm_gpiomux.h> 32#include <mach/msm_gpiomux.h>
34#include <mach/msm_iomap.h> 33#include <mach/msm_iomap.h>
35 34
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 7877335c4cc8..7176743915d3 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -24,6 +24,7 @@
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/irq.h> 25#include <linux/irq.h>
26#include <linux/irqdomain.h> 26#include <linux/irqdomain.h>
27#include <linux/irqchip/chained_irq.h>
27#include <linux/gpio.h> 28#include <linux/gpio.h>
28#include <linux/platform_device.h> 29#include <linux/platform_device.h>
29#include <linux/slab.h> 30#include <linux/slab.h>
@@ -32,7 +33,6 @@
32#include <linux/of_device.h> 33#include <linux/of_device.h>
33#include <linux/module.h> 34#include <linux/module.h>
34#include <asm-generic/bug.h> 35#include <asm-generic/bug.h>
35#include <asm/mach/irq.h>
36 36
37enum mxc_gpio_hwtype { 37enum mxc_gpio_hwtype {
38 IMX1_GPIO, /* runs on i.mx1 */ 38 IMX1_GPIO, /* runs on i.mx1 */
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 159f5c57eb45..a612ea1c53cb 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -25,11 +25,10 @@
25#include <linux/of.h> 25#include <linux/of.h>
26#include <linux/of_device.h> 26#include <linux/of_device.h>
27#include <linux/irqdomain.h> 27#include <linux/irqdomain.h>
28#include <linux/irqchip/chained_irq.h>
28#include <linux/gpio.h> 29#include <linux/gpio.h>
29#include <linux/platform_data/gpio-omap.h> 30#include <linux/platform_data/gpio-omap.h>
30 31
31#include <asm/mach/irq.h>
32
33#define OFF_MODE 1 32#define OFF_MODE 1
34 33
35static LIST_HEAD(omap_gpio_list); 34static LIST_HEAD(omap_gpio_list);
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index d7008dfdd6f0..6a4bd0dae0ce 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -16,6 +16,7 @@
16#include <linux/ioport.h> 16#include <linux/ioport.h>
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/irqdomain.h> 18#include <linux/irqdomain.h>
19#include <linux/irqchip/chained_irq.h>
19#include <linux/bitops.h> 20#include <linux/bitops.h>
20#include <linux/workqueue.h> 21#include <linux/workqueue.h>
21#include <linux/gpio.h> 22#include <linux/gpio.h>
@@ -25,7 +26,6 @@
25#include <linux/slab.h> 26#include <linux/slab.h>
26#include <linux/pinctrl/consumer.h> 27#include <linux/pinctrl/consumer.h>
27#include <linux/pm.h> 28#include <linux/pm.h>
28#include <asm/mach/irq.h>
29 29
30#define GPIODIR 0x400 30#define GPIODIR 0x400
31#define GPIOIS 0x404 31#define GPIOIS 0x404
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 8325f580c0f1..2d3af981641e 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -19,6 +19,7 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/irqdomain.h> 21#include <linux/irqdomain.h>
22#include <linux/irqchip/chained_irq.h>
22#include <linux/io.h> 23#include <linux/io.h>
23#include <linux/of.h> 24#include <linux/of.h>
24#include <linux/of_device.h> 25#include <linux/of_device.h>
@@ -26,8 +27,6 @@
26#include <linux/syscore_ops.h> 27#include <linux/syscore_ops.h>
27#include <linux/slab.h> 28#include <linux/slab.h>
28 29
29#include <asm/mach/irq.h>
30
31#include <mach/irqs.h> 30#include <mach/irqs.h>
32 31
33/* 32/*
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 414ad912232f..8e2155548888 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -27,11 +27,10 @@
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/irqdomain.h> 29#include <linux/irqdomain.h>
30#include <linux/irqchip/chained_irq.h>
30#include <linux/pinctrl/consumer.h> 31#include <linux/pinctrl/consumer.h>
31#include <linux/pm.h> 32#include <linux/pm.h>
32 33
33#include <asm/mach/irq.h>
34
35#define GPIO_BANK(x) ((x) >> 5) 34#define GPIO_BANK(x) ((x) >> 5)
36#define GPIO_PORT(x) (((x) >> 3) & 0x3) 35#define GPIO_PORT(x) (((x) >> 3) & 0x3)
37#define GPIO_BIT(x) ((x) & 0x7) 36#define GPIO_BIT(x) ((x) & 0x7)
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 98e3b87bdf1b..d5e119ca9425 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -2,9 +2,10 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
2 2
3obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o 3obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
4obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o 4obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
5obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
5obj-$(CONFIG_METAG) += irq-metag-ext.o 6obj-$(CONFIG_METAG) += irq-metag-ext.o
6obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o 7obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
7obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o 8obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
8obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o 9obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
9obj-$(CONFIG_ARM_GIC) += irq-gic.o 10obj-$(CONFIG_ARM_GIC) += irq-gic.o
10obj-$(CONFIG_ARM_VIC) += irq-vic.o 11obj-$(CONFIG_ARM_VIC) += irq-vic.o
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index 04d86a9803f4..6a5201351507 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -13,6 +13,7 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/irqdomain.h> 15#include <linux/irqdomain.h>
16#include <linux/irqchip/chained_irq.h>
16#include <linux/of_address.h> 17#include <linux/of_address.h>
17#include <linux/of_irq.h> 18#include <linux/of_irq.h>
18#include <asm/mach/irq.h> 19#include <asm/mach/irq.h>
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index fc6aebf1e4b2..1760ceb68b7b 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -28,6 +28,7 @@
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/list.h> 29#include <linux/list.h>
30#include <linux/smp.h> 30#include <linux/smp.h>
31#include <linux/cpu.h>
31#include <linux/cpu_pm.h> 32#include <linux/cpu_pm.h>
32#include <linux/cpumask.h> 33#include <linux/cpumask.h>
33#include <linux/io.h> 34#include <linux/io.h>
@@ -38,12 +39,12 @@
38#include <linux/interrupt.h> 39#include <linux/interrupt.h>
39#include <linux/percpu.h> 40#include <linux/percpu.h>
40#include <linux/slab.h> 41#include <linux/slab.h>
42#include <linux/irqchip/chained_irq.h>
41#include <linux/irqchip/arm-gic.h> 43#include <linux/irqchip/arm-gic.h>
42 44
43#include <asm/irq.h> 45#include <asm/irq.h>
44#include <asm/exception.h> 46#include <asm/exception.h>
45#include <asm/smp_plat.h> 47#include <asm/smp_plat.h>
46#include <asm/mach/irq.h>
47 48
48#include "irqchip.h" 49#include "irqchip.h"
49 50
@@ -127,7 +128,7 @@ static inline void gic_set_base_accessor(struct gic_chip_data *data,
127#else 128#else
128#define gic_data_dist_base(d) ((d)->dist_base.common_base) 129#define gic_data_dist_base(d) ((d)->dist_base.common_base)
129#define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 130#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
130#define gic_set_base_accessor(d,f) 131#define gic_set_base_accessor(d, f)
131#endif 132#endif
132 133
133static inline void __iomem *gic_dist_base(struct irq_data *d) 134static inline void __iomem *gic_dist_base(struct irq_data *d)
@@ -324,7 +325,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
324 325
325 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 326 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
326 if (unlikely(gic_irq < 32 || gic_irq > 1020)) 327 if (unlikely(gic_irq < 32 || gic_irq > 1020))
327 do_bad_IRQ(cascade_irq, desc); 328 handle_bad_irq(cascade_irq, desc);
328 else 329 else
329 generic_handle_irq(cascade_irq); 330 generic_handle_irq(cascade_irq);
330 331
@@ -700,6 +701,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
700 return 0; 701 return 0;
701} 702}
702 703
704#ifdef CONFIG_SMP
705static int __cpuinit gic_secondary_init(struct notifier_block *nfb,
706 unsigned long action, void *hcpu)
707{
708 if (action == CPU_STARTING)
709 gic_cpu_init(&gic_data[0]);
710 return NOTIFY_OK;
711}
712
713/*
714 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
715 * priority because the GIC needs to be up before the ARM generic timers.
716 */
717static struct notifier_block __cpuinitdata gic_cpu_notifier = {
718 .notifier_call = gic_secondary_init,
719 .priority = 100,
720};
721#endif
722
703const struct irq_domain_ops gic_irq_domain_ops = { 723const struct irq_domain_ops gic_irq_domain_ops = {
704 .map = gic_irq_domain_map, 724 .map = gic_irq_domain_map,
705 .xlate = gic_irq_domain_xlate, 725 .xlate = gic_irq_domain_xlate,
@@ -790,6 +810,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
790 810
791#ifdef CONFIG_SMP 811#ifdef CONFIG_SMP
792 set_smp_cross_call(gic_raise_softirq); 812 set_smp_cross_call(gic_raise_softirq);
813 register_cpu_notifier(&gic_cpu_notifier);
793#endif 814#endif
794 815
795 set_handle_irq(gic_handle_irq); 816 set_handle_irq(gic_handle_irq);
@@ -800,15 +821,8 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
800 gic_pm_init(gic); 821 gic_pm_init(gic);
801} 822}
802 823
803void __cpuinit gic_secondary_init(unsigned int gic_nr)
804{
805 BUG_ON(gic_nr >= MAX_GIC_NR);
806
807 gic_cpu_init(&gic_data[gic_nr]);
808}
809
810#ifdef CONFIG_OF 824#ifdef CONFIG_OF
811static int gic_cnt __initdata = 0; 825static int gic_cnt __initdata;
812 826
813int __init gic_of_init(struct device_node *node, struct device_node *parent) 827int __init gic_of_init(struct device_node *node, struct device_node *parent)
814{ 828{
diff --git a/drivers/irqchip/irq-mxs.c b/drivers/irqchip/irq-mxs.c
new file mode 100644
index 000000000000..29889bbdcc6d
--- /dev/null
+++ b/drivers/irqchip/irq-mxs.c
@@ -0,0 +1,121 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/irq.h>
22#include <linux/irqdomain.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/stmp_device.h>
28#include <asm/exception.h>
29
30#include "irqchip.h"
31
32#define HW_ICOLL_VECTOR 0x0000
33#define HW_ICOLL_LEVELACK 0x0010
34#define HW_ICOLL_CTRL 0x0020
35#define HW_ICOLL_STAT_OFFSET 0x0070
36#define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10)
37#define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10)
38#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
39#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
40
41#define ICOLL_NUM_IRQS 128
42
43static void __iomem *icoll_base;
44static struct irq_domain *icoll_domain;
45
46static void icoll_ack_irq(struct irq_data *d)
47{
48 /*
49 * The Interrupt Collector is able to prioritize irqs.
50 * Currently only level 0 is used. So acking can use
51 * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
52 */
53 __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
54 icoll_base + HW_ICOLL_LEVELACK);
55}
56
57static void icoll_mask_irq(struct irq_data *d)
58{
59 __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
60 icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq));
61}
62
63static void icoll_unmask_irq(struct irq_data *d)
64{
65 __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
66 icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq));
67}
68
69static struct irq_chip mxs_icoll_chip = {
70 .irq_ack = icoll_ack_irq,
71 .irq_mask = icoll_mask_irq,
72 .irq_unmask = icoll_unmask_irq,
73};
74
75asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
76{
77 u32 irqnr;
78
79 do {
80 irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
81 if (irqnr != 0x7f) {
82 __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
83 irqnr = irq_find_mapping(icoll_domain, irqnr);
84 handle_IRQ(irqnr, regs);
85 continue;
86 }
87 break;
88 } while (1);
89}
90
91static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
92 irq_hw_number_t hw)
93{
94 irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq);
95 set_irq_flags(virq, IRQF_VALID);
96
97 return 0;
98}
99
100static struct irq_domain_ops icoll_irq_domain_ops = {
101 .map = icoll_irq_domain_map,
102 .xlate = irq_domain_xlate_onecell,
103};
104
105static void __init icoll_of_init(struct device_node *np,
106 struct device_node *interrupt_parent)
107{
108 icoll_base = of_iomap(np, 0);
109 WARN_ON(!icoll_base);
110
111 /*
112 * Interrupt Collector reset, which initializes the priority
113 * for each irq to level 0.
114 */
115 stmp_reset_block(icoll_base + HW_ICOLL_CTRL);
116
117 icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS,
118 &icoll_irq_domain_ops, NULL);
119 WARN_ON(!icoll_domain);
120}
121IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);
diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c
new file mode 100644
index 000000000000..b66d4ae06898
--- /dev/null
+++ b/drivers/irqchip/irq-sun4i.c
@@ -0,0 +1,149 @@
1/*
2 * Allwinner A1X SoCs IRQ chip driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code from
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * Benn Huang <benn@allwinnertech.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22
23#include <asm/exception.h>
24#include <asm/mach/irq.h>
25
26#include "irqchip.h"
27
28#define SUN4I_IRQ_VECTOR_REG 0x00
29#define SUN4I_IRQ_PROTECTION_REG 0x08
30#define SUN4I_IRQ_NMI_CTRL_REG 0x0c
31#define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
32#define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
33#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
34#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
35
36static void __iomem *sun4i_irq_base;
37static struct irq_domain *sun4i_irq_domain;
38
39static asmlinkage void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
40
41void sun4i_irq_ack(struct irq_data *irqd)
42{
43 unsigned int irq = irqd_to_hwirq(irqd);
44 unsigned int irq_off = irq % 32;
45 int reg = irq / 32;
46 u32 val;
47
48 val = readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
49 writel(val | (1 << irq_off),
50 sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
51}
52
53static void sun4i_irq_mask(struct irq_data *irqd)
54{
55 unsigned int irq = irqd_to_hwirq(irqd);
56 unsigned int irq_off = irq % 32;
57 int reg = irq / 32;
58 u32 val;
59
60 val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
61 writel(val & ~(1 << irq_off),
62 sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
63}
64
65static void sun4i_irq_unmask(struct irq_data *irqd)
66{
67 unsigned int irq = irqd_to_hwirq(irqd);
68 unsigned int irq_off = irq % 32;
69 int reg = irq / 32;
70 u32 val;
71
72 val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
73 writel(val | (1 << irq_off),
74 sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
75}
76
77static struct irq_chip sun4i_irq_chip = {
78 .name = "sun4i_irq",
79 .irq_ack = sun4i_irq_ack,
80 .irq_mask = sun4i_irq_mask,
81 .irq_unmask = sun4i_irq_unmask,
82};
83
84static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
85 irq_hw_number_t hw)
86{
87 irq_set_chip_and_handler(virq, &sun4i_irq_chip,
88 handle_level_irq);
89 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
90
91 return 0;
92}
93
94static struct irq_domain_ops sun4i_irq_ops = {
95 .map = sun4i_irq_map,
96 .xlate = irq_domain_xlate_onecell,
97};
98
99static int __init sun4i_of_init(struct device_node *node,
100 struct device_node *parent)
101{
102 sun4i_irq_base = of_iomap(node, 0);
103 if (!sun4i_irq_base)
104 panic("%s: unable to map IC registers\n",
105 node->full_name);
106
107 /* Disable all interrupts */
108 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
109 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
110 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
111
112 /* Mask all the interrupts */
113 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
114 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
115 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
116
117 /* Clear all the pending interrupts */
118 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
119 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
120 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
121
122 /* Enable protection mode */
123 writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
124
125 /* Configure the external interrupt source type */
126 writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
127
128 sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
129 &sun4i_irq_ops, NULL);
130 if (!sun4i_irq_domain)
131 panic("%s: unable to create IRQ domain\n", node->full_name);
132
133 set_handle_irq(sun4i_handle_irq);
134
135 return 0;
136}
137IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-ic", sun4i_of_init);
138
139static asmlinkage void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
140{
141 u32 irq, hwirq;
142
143 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
144 while (hwirq != 0) {
145 irq = irq_find_mapping(sun4i_irq_domain, hwirq);
146 handle_IRQ(irq, regs);
147 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
148 }
149}
diff --git a/drivers/irqchip/irq-sunxi.c b/drivers/irqchip/irq-sunxi.c
deleted file mode 100644
index 10974fa42653..000000000000
--- a/drivers/irqchip/irq-sunxi.c
+++ /dev/null
@@ -1,151 +0,0 @@
1/*
2 * Allwinner A1X SoCs IRQ chip driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code from
9 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * Benn Huang <benn@allwinnertech.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22
23#include <linux/irqchip/sunxi.h>
24
25#define SUNXI_IRQ_VECTOR_REG 0x00
26#define SUNXI_IRQ_PROTECTION_REG 0x08
27#define SUNXI_IRQ_NMI_CTRL_REG 0x0c
28#define SUNXI_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
29#define SUNXI_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
30#define SUNXI_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
31#define SUNXI_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
32
33static void __iomem *sunxi_irq_base;
34static struct irq_domain *sunxi_irq_domain;
35
36void sunxi_irq_ack(struct irq_data *irqd)
37{
38 unsigned int irq = irqd_to_hwirq(irqd);
39 unsigned int irq_off = irq % 32;
40 int reg = irq / 32;
41 u32 val;
42
43 val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
44 writel(val | (1 << irq_off),
45 sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
46}
47
48static void sunxi_irq_mask(struct irq_data *irqd)
49{
50 unsigned int irq = irqd_to_hwirq(irqd);
51 unsigned int irq_off = irq % 32;
52 int reg = irq / 32;
53 u32 val;
54
55 val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
56 writel(val & ~(1 << irq_off),
57 sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
58}
59
60static void sunxi_irq_unmask(struct irq_data *irqd)
61{
62 unsigned int irq = irqd_to_hwirq(irqd);
63 unsigned int irq_off = irq % 32;
64 int reg = irq / 32;
65 u32 val;
66
67 val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
68 writel(val | (1 << irq_off),
69 sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
70}
71
72static struct irq_chip sunxi_irq_chip = {
73 .name = "sunxi_irq",
74 .irq_ack = sunxi_irq_ack,
75 .irq_mask = sunxi_irq_mask,
76 .irq_unmask = sunxi_irq_unmask,
77};
78
79static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
80 irq_hw_number_t hw)
81{
82 irq_set_chip_and_handler(virq, &sunxi_irq_chip,
83 handle_level_irq);
84 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
85
86 return 0;
87}
88
89static struct irq_domain_ops sunxi_irq_ops = {
90 .map = sunxi_irq_map,
91 .xlate = irq_domain_xlate_onecell,
92};
93
94static int __init sunxi_of_init(struct device_node *node,
95 struct device_node *parent)
96{
97 sunxi_irq_base = of_iomap(node, 0);
98 if (!sunxi_irq_base)
99 panic("%s: unable to map IC registers\n",
100 node->full_name);
101
102 /* Disable all interrupts */
103 writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
104 writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
105 writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
106
107 /* Mask all the interrupts */
108 writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
109 writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
110 writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
111
112 /* Clear all the pending interrupts */
113 writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
114 writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
115 writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
116
117 /* Enable protection mode */
118 writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
119
120 /* Configure the external interrupt source type */
121 writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
122
123 sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
124 &sunxi_irq_ops, NULL);
125 if (!sunxi_irq_domain)
126 panic("%s: unable to create IRQ domain\n", node->full_name);
127
128 return 0;
129}
130
131static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
132 { .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init },
133 { }
134};
135
136void __init sunxi_init_irq(void)
137{
138 of_irq_init(sunxi_irq_dt_ids);
139}
140
141asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
142{
143 u32 irq, hwirq;
144
145 hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
146 while (hwirq != 0) {
147 irq = irq_find_mapping(sunxi_irq_domain, hwirq);
148 handle_IRQ(irq, regs);
149 hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
150 }
151}
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index 3cf97aaebe40..884d11c7355f 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -23,6 +23,7 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/list.h> 24#include <linux/list.h>
25#include <linux/io.h> 25#include <linux/io.h>
26#include <linux/irq.h>
26#include <linux/irqdomain.h> 27#include <linux/irqdomain.h>
27#include <linux/of.h> 28#include <linux/of.h>
28#include <linux/of_address.h> 29#include <linux/of_address.h>
@@ -33,7 +34,7 @@
33#include <linux/irqchip/arm-vic.h> 34#include <linux/irqchip/arm-vic.h>
34 35
35#include <asm/exception.h> 36#include <asm/exception.h>
36#include <asm/mach/irq.h> 37#include <asm/irq.h>
37 38
38#include "irqchip.h" 39#include "irqchip.h"
39 40
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 7c0af0e80047..0ee4a57fe6b2 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -43,7 +43,6 @@
43#include <asm/sizes.h> 43#include <asm/sizes.h>
44 44
45#include <linux/platform_data/mmc-msm_sdcc.h> 45#include <linux/platform_data/mmc-msm_sdcc.h>
46#include <mach/msm_iomap.h>
47#include <mach/dma.h> 46#include <mach/dma.h>
48#include <mach/clk.h> 47#include <mach/clk.h>
49 48
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 63fb265e0da6..8d6794cdf899 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -25,14 +25,93 @@
25 25
26#include <mach/dma.h> 26#include <mach/dma.h>
27 27
28#include <mach/regs-sdi.h>
29
30#include <linux/platform_data/mmc-s3cmci.h> 28#include <linux/platform_data/mmc-s3cmci.h>
31 29
32#include "s3cmci.h" 30#include "s3cmci.h"
33 31
34#define DRIVER_NAME "s3c-mci" 32#define DRIVER_NAME "s3c-mci"
35 33
34#define S3C2410_SDICON (0x00)
35#define S3C2410_SDIPRE (0x04)
36#define S3C2410_SDICMDARG (0x08)
37#define S3C2410_SDICMDCON (0x0C)
38#define S3C2410_SDICMDSTAT (0x10)
39#define S3C2410_SDIRSP0 (0x14)
40#define S3C2410_SDIRSP1 (0x18)
41#define S3C2410_SDIRSP2 (0x1C)
42#define S3C2410_SDIRSP3 (0x20)
43#define S3C2410_SDITIMER (0x24)
44#define S3C2410_SDIBSIZE (0x28)
45#define S3C2410_SDIDCON (0x2C)
46#define S3C2410_SDIDCNT (0x30)
47#define S3C2410_SDIDSTA (0x34)
48#define S3C2410_SDIFSTA (0x38)
49
50#define S3C2410_SDIDATA (0x3C)
51#define S3C2410_SDIIMSK (0x40)
52
53#define S3C2440_SDIDATA (0x40)
54#define S3C2440_SDIIMSK (0x3C)
55
56#define S3C2440_SDICON_SDRESET (1 << 8)
57#define S3C2410_SDICON_SDIOIRQ (1 << 3)
58#define S3C2410_SDICON_FIFORESET (1 << 1)
59#define S3C2410_SDICON_CLOCKTYPE (1 << 0)
60
61#define S3C2410_SDICMDCON_LONGRSP (1 << 10)
62#define S3C2410_SDICMDCON_WAITRSP (1 << 9)
63#define S3C2410_SDICMDCON_CMDSTART (1 << 8)
64#define S3C2410_SDICMDCON_SENDERHOST (1 << 6)
65#define S3C2410_SDICMDCON_INDEX (0x3f)
66
67#define S3C2410_SDICMDSTAT_CRCFAIL (1 << 12)
68#define S3C2410_SDICMDSTAT_CMDSENT (1 << 11)
69#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1 << 10)
70#define S3C2410_SDICMDSTAT_RSPFIN (1 << 9)
71
72#define S3C2440_SDIDCON_DS_WORD (2 << 22)
73#define S3C2410_SDIDCON_TXAFTERRESP (1 << 20)
74#define S3C2410_SDIDCON_RXAFTERCMD (1 << 19)
75#define S3C2410_SDIDCON_BLOCKMODE (1 << 17)
76#define S3C2410_SDIDCON_WIDEBUS (1 << 16)
77#define S3C2410_SDIDCON_DMAEN (1 << 15)
78#define S3C2410_SDIDCON_STOP (1 << 14)
79#define S3C2440_SDIDCON_DATSTART (1 << 14)
80
81#define S3C2410_SDIDCON_XFER_RXSTART (2 << 12)
82#define S3C2410_SDIDCON_XFER_TXSTART (3 << 12)
83
84#define S3C2410_SDIDCON_BLKNUM_MASK (0xFFF)
85
86#define S3C2410_SDIDSTA_SDIOIRQDETECT (1 << 9)
87#define S3C2410_SDIDSTA_FIFOFAIL (1 << 8)
88#define S3C2410_SDIDSTA_CRCFAIL (1 << 7)
89#define S3C2410_SDIDSTA_RXCRCFAIL (1 << 6)
90#define S3C2410_SDIDSTA_DATATIMEOUT (1 << 5)
91#define S3C2410_SDIDSTA_XFERFINISH (1 << 4)
92#define S3C2410_SDIDSTA_TXDATAON (1 << 1)
93#define S3C2410_SDIDSTA_RXDATAON (1 << 0)
94
95#define S3C2440_SDIFSTA_FIFORESET (1 << 16)
96#define S3C2440_SDIFSTA_FIFOFAIL (3 << 14)
97#define S3C2410_SDIFSTA_TFDET (1 << 13)
98#define S3C2410_SDIFSTA_RFDET (1 << 12)
99#define S3C2410_SDIFSTA_COUNTMASK (0x7f)
100
101#define S3C2410_SDIIMSK_RESPONSECRC (1 << 17)
102#define S3C2410_SDIIMSK_CMDSENT (1 << 16)
103#define S3C2410_SDIIMSK_CMDTIMEOUT (1 << 15)
104#define S3C2410_SDIIMSK_RESPONSEND (1 << 14)
105#define S3C2410_SDIIMSK_SDIOIRQ (1 << 12)
106#define S3C2410_SDIIMSK_FIFOFAIL (1 << 11)
107#define S3C2410_SDIIMSK_CRCSTATUS (1 << 10)
108#define S3C2410_SDIIMSK_DATACRC (1 << 9)
109#define S3C2410_SDIIMSK_DATATIMEOUT (1 << 8)
110#define S3C2410_SDIIMSK_DATAFINISH (1 << 7)
111#define S3C2410_SDIIMSK_TXFIFOHALF (1 << 4)
112#define S3C2410_SDIIMSK_RXFIFOLAST (1 << 2)
113#define S3C2410_SDIIMSK_RXFIFOHALF (1 << 0)
114
36enum dbg_channels { 115enum dbg_channels {
37 dbg_err = (1 << 0), 116 dbg_err = (1 << 0),
38 dbg_debug = (1 << 1), 117 dbg_debug = (1 << 1),
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 4d7f531e945d..5d7529ed5392 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -18,6 +18,7 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/irq.h> 19#include <linux/irq.h>
20#include <linux/irqdomain.h> 20#include <linux/irqdomain.h>
21#include <linux/irqchip/chained_irq.h>
21#include <linux/io.h> 22#include <linux/io.h>
22#include <linux/gpio.h> 23#include <linux/gpio.h>
23#include <linux/pinctrl/machine.h> 24#include <linux/pinctrl/machine.h>
@@ -27,8 +28,6 @@
27/* Since we request GPIOs from ourself */ 28/* Since we request GPIOs from ourself */
28#include <linux/pinctrl/consumer.h> 29#include <linux/pinctrl/consumer.h>
29 30
30#include <asm/mach/irq.h>
31
32#include <mach/hardware.h> 31#include <mach/hardware.h>
33#include <mach/at91_pio.h> 32#include <mach/at91_pio.h>
34 33
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 8b10b1ac9071..ec1567842a7e 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -23,14 +23,13 @@
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irqdomain.h> 24#include <linux/irqdomain.h>
25#include <linux/irq.h> 25#include <linux/irq.h>
26#include <linux/irqchip/chained_irq.h>
26#include <linux/of_irq.h> 27#include <linux/of_irq.h>
27#include <linux/io.h> 28#include <linux/io.h>
28#include <linux/slab.h> 29#include <linux/slab.h>
29#include <linux/spinlock.h> 30#include <linux/spinlock.h>
30#include <linux/err.h> 31#include <linux/err.h>
31 32
32#include <asm/mach/irq.h>
33
34#include "pinctrl-samsung.h" 33#include "pinctrl-samsung.h"
35#include "pinctrl-exynos.h" 34#include "pinctrl-exynos.h"
36 35
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 435bf3078d2c..34281754b629 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -23,6 +23,7 @@
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/irqdomain.h> 25#include <linux/irqdomain.h>
26#include <linux/irqchip/chained_irq.h>
26#include <linux/slab.h> 27#include <linux/slab.h>
27#include <linux/of_device.h> 28#include <linux/of_device.h>
28#include <linux/of_address.h> 29#include <linux/of_address.h>
@@ -33,7 +34,6 @@
33/* Since we request GPIOs from ourself */ 34/* Since we request GPIOs from ourself */
34#include <linux/pinctrl/consumer.h> 35#include <linux/pinctrl/consumer.h>
35#include <linux/platform_data/pinctrl-nomadik.h> 36#include <linux/platform_data/pinctrl-nomadik.h>
36#include <asm/mach/irq.h>
37#include "pinctrl-nomadik.h" 37#include "pinctrl-nomadik.h"
38#include "core.h" 38#include "core.h"
39 39
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index fb9062570745..1ed23d02011e 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -14,6 +14,7 @@
14#include <linux/slab.h> 14#include <linux/slab.h>
15#include <linux/err.h> 15#include <linux/err.h>
16#include <linux/irqdomain.h> 16#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h>
17#include <linux/pinctrl/pinctrl.h> 18#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h> 19#include <linux/pinctrl/pinmux.h>
19#include <linux/pinctrl/consumer.h> 20#include <linux/pinctrl/consumer.h>
@@ -25,7 +26,6 @@
25#include <linux/bitops.h> 26#include <linux/bitops.h>
26#include <linux/gpio.h> 27#include <linux/gpio.h>
27#include <linux/of_gpio.h> 28#include <linux/of_gpio.h>
28#include <asm/mach/irq.h>
29 29
30#define DRIVER_NAME "pinmux-sirf" 30#define DRIVER_NAME "pinmux-sirf"
31 31
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
index 295b349a05cf..a4908ecd74fb 100644
--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
+++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
@@ -15,12 +15,12 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/irqdomain.h> 17#include <linux/irqdomain.h>
18#include <linux/irqchip/chained_irq.h>
18#include <linux/module.h> 19#include <linux/module.h>
19#include <linux/pinctrl/consumer.h> 20#include <linux/pinctrl/consumer.h>
20#include <linux/platform_device.h> 21#include <linux/platform_device.h>
21#include <linux/pm.h> 22#include <linux/pm.h>
22#include <linux/spinlock.h> 23#include <linux/spinlock.h>
23#include <asm/mach/irq.h>
24 24
25#define MAX_GPIO_PER_REG 32 25#define MAX_GPIO_PER_REG 32
26#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG) 26#define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c
index a9cd26a26dc0..483ce086990b 100644
--- a/drivers/rtc/rtc-stmp3xxx.c
+++ b/drivers/rtc/rtc-stmp3xxx.c
@@ -30,8 +30,6 @@
30#include <linux/stmp_device.h> 30#include <linux/stmp_device.h>
31#include <linux/stmp3xxx_rtc_wdt.h> 31#include <linux/stmp3xxx_rtc_wdt.h>
32 32
33#include <mach/common.h>
34
35#define STMP3XXX_RTC_CTRL 0x0 33#define STMP3XXX_RTC_CTRL 0x0
36#define STMP3XXX_RTC_CTRL_SET 0x4 34#define STMP3XXX_RTC_CTRL_SET 0x4
37#define STMP3XXX_RTC_CTRL_CLR 0x8 35#define STMP3XXX_RTC_CTRL_CLR 0x8
@@ -264,7 +262,7 @@ static int stmp3xxx_rtc_probe(struct platform_device *pdev)
264 262
265 platform_set_drvdata(pdev, rtc_data); 263 platform_set_drvdata(pdev, rtc_data);
266 264
267 mxs_reset_block(rtc_data->io); 265 stmp_reset_block(rtc_data->io);
268 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | 266 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
269 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN | 267 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
270 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE, 268 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
@@ -307,7 +305,7 @@ static int stmp3xxx_rtc_resume(struct device *dev)
307{ 305{
308 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev); 306 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
309 307
310 mxs_reset_block(rtc_data->io); 308 stmp_reset_block(rtc_data->io);
311 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | 309 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
312 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN | 310 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
313 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE, 311 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
diff --git a/drivers/staging/iio/adc/mxs-lradc.c b/drivers/staging/iio/adc/mxs-lradc.c
index 6044e1717b20..2856b8fd44ad 100644
--- a/drivers/staging/iio/adc/mxs-lradc.c
+++ b/drivers/staging/iio/adc/mxs-lradc.c
@@ -36,9 +36,6 @@
36#include <linux/delay.h> 36#include <linux/delay.h>
37#include <linux/input.h> 37#include <linux/input.h>
38 38
39#include <mach/mxs.h>
40#include <mach/common.h>
41
42#include <linux/iio/iio.h> 39#include <linux/iio/iio.h>
43#include <linux/iio/buffer.h> 40#include <linux/iio/buffer.h>
44#include <linux/iio/trigger.h> 41#include <linux/iio/trigger.h>
diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-common.c b/drivers/staging/imx-drm/ipu-v3/ipu-common.c
index 055b99db50ff..0880ef1a01ba 100644
--- a/drivers/staging/imx-drm/ipu-v3/ipu-common.c
+++ b/drivers/staging/imx-drm/ipu-v3/ipu-common.c
@@ -25,8 +25,8 @@
25#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/list.h> 26#include <linux/list.h>
27#include <linux/irq.h> 27#include <linux/irq.h>
28#include <linux/irqchip/chained_irq.h>
28#include <linux/of_device.h> 29#include <linux/of_device.h>
29#include <asm/mach/irq.h>
30 30
31#include "imx-ipu-v3.h" 31#include "imx-ipu-v3.h"
32#include "ipu-prv.h" 32#include "ipu-prv.h"
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 114583a8e92b..07592c00af26 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -14,7 +14,7 @@
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/platform_data/usb-exynos.h> 17#include <linux/platform_data/usb-ohci-exynos.h>
18#include <linux/usb/phy.h> 18#include <linux/usb/phy.h>
19#include <linux/usb/samsung_usb_phy.h> 19#include <linux/usb/samsung_usb_phy.h>
20 20
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-31 17:33:41 -0500