intel_idle: Broadwell support

Broadwell (BDW) is similar to Haswell (HSW), the preceding processor generation.

Currently, the only difference in their C-state tables is that PC3 max exit latency
is 33usec on HSW and 40usec on BDW.

Signed-off-by: Len Brown <len.brown@intel.com>

1 files changed, 69 insertions, 1 deletions

diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 2d23cf8279f0..9b7ee7e427df 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -443,6 +443,66 @@ static struct cpuidle_state hsw_cstates[] = {
         {
                 .enter = NULL }
 };
+static struct cpuidle_state bdw_cstates[] = {
+        {
+                .name = "C1-BDW",
+                .desc = "MWAIT 0x00",
+                .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
+                .exit_latency = 2,
+                .target_residency = 2,
+                .enter = &intel_idle },
+        {
+                .name = "C1E-BDW",
+                .desc = "MWAIT 0x01",
+                .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
+                .exit_latency = 10,
+                .target_residency = 20,
+                .enter = &intel_idle },
+        {
+                .name = "C3-BDW",
+                .desc = "MWAIT 0x10",
+                .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+                .exit_latency = 40,
+                .target_residency = 100,
+                .enter = &intel_idle },
+        {
+                .name = "C6-BDW",
+                .desc = "MWAIT 0x20",
+                .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+                .exit_latency = 133,
+                .target_residency = 400,
+                .enter = &intel_idle },
+        {
+                .name = "C7s-BDW",
+                .desc = "MWAIT 0x32",
+                .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+                .exit_latency = 166,
+                .target_residency = 500,
+                .enter = &intel_idle },
+        {
+                .name = "C8-BDW",
+                .desc = "MWAIT 0x40",
+                .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+                .exit_latency = 300,
+                .target_residency = 900,
+                .enter = &intel_idle },
+        {
+                .name = "C9-BDW",
+                .desc = "MWAIT 0x50",
+                .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+                .exit_latency = 600,
+                .target_residency = 1800,
+                .enter = &intel_idle },
+        {
+                .name = "C10-BDW",
+                .desc = "MWAIT 0x60",
+                .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+                .exit_latency = 2600,
+                .target_residency = 7700,
+                .enter = &intel_idle },
+        {
+                .enter = NULL }
+};
 
 static struct cpuidle_state atom_cstates[] = {
         {
@@ -632,6 +692,11 @@ static const struct idle_cpu idle_cpu_hsw = {
         .disable_promotion_to_c1e = true,
 };
 
+static const struct idle_cpu idle_cpu_bdw = {
+        .state_table = bdw_cstates,
+        .disable_promotion_to_c1e = true,
+};
+
 static const struct idle_cpu idle_cpu_avn = {
         .state_table = avn_cstates,
         .disable_promotion_to_c1e = true,
@@ -660,7 +725,10 @@ static const struct x86_cpu_id intel_idle_ids[] = {
         ICPU(0x3f, idle_cpu_hsw),
         ICPU(0x45, idle_cpu_hsw),
         ICPU(0x46, idle_cpu_hsw),
-        ICPU(0x4D, idle_cpu_avn),
+        ICPU(0x4d, idle_cpu_avn),
+        ICPU(0x3d, idle_cpu_bdw),
+        ICPU(0x4f, idle_cpu_bdw),
+        ICPU(0x56, idle_cpu_bdw),
         {}
 };
 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);