diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2012-02-23 17:53:42 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2012-02-29 05:14:14 -0500 |
commit | 27cd77694bfa2e123cb7440507f8ddd762de6c38 (patch) | |
tree | 5637c08e93bbd589cb684388be7420a87b28948e /drivers | |
parent | 293f9fd53aa1529500ba16d89850100a058b11c1 (diff) |
drm/radeon/kms: reorganize copy callbacks
tidy up the radeon_asic struct, handle multiple
rings better.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/ni.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 50 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 190 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_benchmark.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_ttm.c | 15 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 2 |
8 files changed, 185 insertions, 90 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index c8dae3f9fa09..4350a3fe4ec5 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -3197,7 +3197,7 @@ static int evergreen_startup(struct radeon_device *rdev) | |||
3197 | r = evergreen_blit_init(rdev); | 3197 | r = evergreen_blit_init(rdev); |
3198 | if (r) { | 3198 | if (r) { |
3199 | r600_blit_fini(rdev); | 3199 | r600_blit_fini(rdev); |
3200 | rdev->asic->copy = NULL; | 3200 | rdev->asic->copy.copy = NULL; |
3201 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); | 3201 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
3202 | } | 3202 | } |
3203 | 3203 | ||
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index db09065e68fd..6863a0538615 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
@@ -1466,7 +1466,7 @@ static int cayman_startup(struct radeon_device *rdev) | |||
1466 | r = evergreen_blit_init(rdev); | 1466 | r = evergreen_blit_init(rdev); |
1467 | if (r) { | 1467 | if (r) { |
1468 | r600_blit_fini(rdev); | 1468 | r600_blit_fini(rdev); |
1469 | rdev->asic->copy = NULL; | 1469 | rdev->asic->copy.copy = NULL; |
1470 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); | 1470 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
1471 | } | 1471 | } |
1472 | 1472 | ||
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 4a4ac8fb7b70..4cfb90be7241 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -2449,7 +2449,7 @@ int r600_startup(struct radeon_device *rdev) | |||
2449 | r = r600_blit_init(rdev); | 2449 | r = r600_blit_init(rdev); |
2450 | if (r) { | 2450 | if (r) { |
2451 | r600_blit_fini(rdev); | 2451 | r600_blit_fini(rdev); |
2452 | rdev->asic->copy = NULL; | 2452 | rdev->asic->copy.copy = NULL; |
2453 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); | 2453 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
2454 | } | 2454 | } |
2455 | 2455 | ||
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 80548b6a86a1..b4dea5c79847 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -1154,21 +1154,30 @@ struct radeon_asic { | |||
1154 | int (*irq_set)(struct radeon_device *rdev); | 1154 | int (*irq_set)(struct radeon_device *rdev); |
1155 | int (*irq_process)(struct radeon_device *rdev); | 1155 | int (*irq_process)(struct radeon_device *rdev); |
1156 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); | 1156 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
1157 | int (*copy_blit)(struct radeon_device *rdev, | 1157 | |
1158 | uint64_t src_offset, | 1158 | struct { |
1159 | uint64_t dst_offset, | 1159 | int (*blit)(struct radeon_device *rdev, |
1160 | unsigned num_gpu_pages, | 1160 | uint64_t src_offset, |
1161 | struct radeon_fence *fence); | 1161 | uint64_t dst_offset, |
1162 | int (*copy_dma)(struct radeon_device *rdev, | 1162 | unsigned num_gpu_pages, |
1163 | uint64_t src_offset, | 1163 | struct radeon_fence *fence); |
1164 | uint64_t dst_offset, | 1164 | u32 blit_ring_index; |
1165 | unsigned num_gpu_pages, | 1165 | int (*dma)(struct radeon_device *rdev, |
1166 | struct radeon_fence *fence); | 1166 | uint64_t src_offset, |
1167 | int (*copy)(struct radeon_device *rdev, | 1167 | uint64_t dst_offset, |
1168 | uint64_t src_offset, | 1168 | unsigned num_gpu_pages, |
1169 | uint64_t dst_offset, | 1169 | struct radeon_fence *fence); |
1170 | unsigned num_gpu_pages, | 1170 | u32 dma_ring_index; |
1171 | struct radeon_fence *fence); | 1171 | /* method used for bo copy */ |
1172 | int (*copy)(struct radeon_device *rdev, | ||
1173 | uint64_t src_offset, | ||
1174 | uint64_t dst_offset, | ||
1175 | unsigned num_gpu_pages, | ||
1176 | struct radeon_fence *fence); | ||
1177 | /* ring used for bo copies */ | ||
1178 | u32 copy_ring_index; | ||
1179 | } copy; | ||
1180 | |||
1172 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); | 1181 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1173 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); | 1182 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1174 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); | 1183 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
@@ -1505,8 +1514,6 @@ struct radeon_device { | |||
1505 | unsigned debugfs_count; | 1514 | unsigned debugfs_count; |
1506 | /* virtual memory */ | 1515 | /* virtual memory */ |
1507 | struct radeon_vm_manager vm_manager; | 1516 | struct radeon_vm_manager vm_manager; |
1508 | /* ring used for bo copies */ | ||
1509 | u32 copy_ring; | ||
1510 | }; | 1517 | }; |
1511 | 1518 | ||
1512 | int radeon_device_init(struct radeon_device *rdev, | 1519 | int radeon_device_init(struct radeon_device *rdev, |
@@ -1677,9 +1684,12 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); | |||
1677 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) | 1684 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
1678 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) | 1685 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) |
1679 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) | 1686 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
1680 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) | 1687 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
1681 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) | 1688 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) |
1682 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) | 1689 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) |
1690 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index | ||
1691 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index | ||
1692 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index | ||
1683 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) | 1693 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
1684 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) | 1694 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1685 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) | 1695 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 38a29bcac5d1..6bd15254f643 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -151,9 +151,14 @@ static struct radeon_asic r100_asic = { | |||
151 | .irq_set = &r100_irq_set, | 151 | .irq_set = &r100_irq_set, |
152 | .irq_process = &r100_irq_process, | 152 | .irq_process = &r100_irq_process, |
153 | .get_vblank_counter = &r100_get_vblank_counter, | 153 | .get_vblank_counter = &r100_get_vblank_counter, |
154 | .copy_blit = &r100_copy_blit, | 154 | .copy = { |
155 | .copy_dma = NULL, | 155 | .blit = &r100_copy_blit, |
156 | .copy = &r100_copy_blit, | 156 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
157 | .dma = NULL, | ||
158 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
159 | .copy = &r100_copy_blit, | ||
160 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
161 | }, | ||
157 | .get_engine_clock = &radeon_legacy_get_engine_clock, | 162 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
158 | .set_engine_clock = &radeon_legacy_set_engine_clock, | 163 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
159 | .get_memory_clock = &radeon_legacy_get_memory_clock, | 164 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
@@ -211,9 +216,14 @@ static struct radeon_asic r200_asic = { | |||
211 | .irq_set = &r100_irq_set, | 216 | .irq_set = &r100_irq_set, |
212 | .irq_process = &r100_irq_process, | 217 | .irq_process = &r100_irq_process, |
213 | .get_vblank_counter = &r100_get_vblank_counter, | 218 | .get_vblank_counter = &r100_get_vblank_counter, |
214 | .copy_blit = &r100_copy_blit, | 219 | .copy = { |
215 | .copy_dma = &r200_copy_dma, | 220 | .blit = &r100_copy_blit, |
216 | .copy = &r100_copy_blit, | 221 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
222 | .dma = &r200_copy_dma, | ||
223 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
224 | .copy = &r100_copy_blit, | ||
225 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
226 | }, | ||
217 | .get_engine_clock = &radeon_legacy_get_engine_clock, | 227 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
218 | .set_engine_clock = &radeon_legacy_set_engine_clock, | 228 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
219 | .get_memory_clock = &radeon_legacy_get_memory_clock, | 229 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
@@ -270,9 +280,14 @@ static struct radeon_asic r300_asic = { | |||
270 | .irq_set = &r100_irq_set, | 280 | .irq_set = &r100_irq_set, |
271 | .irq_process = &r100_irq_process, | 281 | .irq_process = &r100_irq_process, |
272 | .get_vblank_counter = &r100_get_vblank_counter, | 282 | .get_vblank_counter = &r100_get_vblank_counter, |
273 | .copy_blit = &r100_copy_blit, | 283 | .copy = { |
274 | .copy_dma = &r200_copy_dma, | 284 | .blit = &r100_copy_blit, |
275 | .copy = &r100_copy_blit, | 285 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
286 | .dma = &r200_copy_dma, | ||
287 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
288 | .copy = &r100_copy_blit, | ||
289 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
290 | }, | ||
276 | .get_engine_clock = &radeon_legacy_get_engine_clock, | 291 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
277 | .set_engine_clock = &radeon_legacy_set_engine_clock, | 292 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
278 | .get_memory_clock = &radeon_legacy_get_memory_clock, | 293 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
@@ -330,9 +345,14 @@ static struct radeon_asic r300_asic_pcie = { | |||
330 | .irq_set = &r100_irq_set, | 345 | .irq_set = &r100_irq_set, |
331 | .irq_process = &r100_irq_process, | 346 | .irq_process = &r100_irq_process, |
332 | .get_vblank_counter = &r100_get_vblank_counter, | 347 | .get_vblank_counter = &r100_get_vblank_counter, |
333 | .copy_blit = &r100_copy_blit, | 348 | .copy = { |
334 | .copy_dma = &r200_copy_dma, | 349 | .blit = &r100_copy_blit, |
335 | .copy = &r100_copy_blit, | 350 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
351 | .dma = &r200_copy_dma, | ||
352 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
353 | .copy = &r100_copy_blit, | ||
354 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
355 | }, | ||
336 | .get_engine_clock = &radeon_legacy_get_engine_clock, | 356 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
337 | .set_engine_clock = &radeon_legacy_set_engine_clock, | 357 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
338 | .get_memory_clock = &radeon_legacy_get_memory_clock, | 358 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
@@ -389,9 +409,14 @@ static struct radeon_asic r420_asic = { | |||
389 | .irq_set = &r100_irq_set, | 409 | .irq_set = &r100_irq_set, |
390 | .irq_process = &r100_irq_process, | 410 | .irq_process = &r100_irq_process, |
391 | .get_vblank_counter = &r100_get_vblank_counter, | 411 | .get_vblank_counter = &r100_get_vblank_counter, |
392 | .copy_blit = &r100_copy_blit, | 412 | .copy = { |
393 | .copy_dma = &r200_copy_dma, | 413 | .blit = &r100_copy_blit, |
394 | .copy = &r100_copy_blit, | 414 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
415 | .dma = &r200_copy_dma, | ||
416 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
417 | .copy = &r100_copy_blit, | ||
418 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
419 | }, | ||
395 | .get_engine_clock = &radeon_atom_get_engine_clock, | 420 | .get_engine_clock = &radeon_atom_get_engine_clock, |
396 | .set_engine_clock = &radeon_atom_set_engine_clock, | 421 | .set_engine_clock = &radeon_atom_set_engine_clock, |
397 | .get_memory_clock = &radeon_atom_get_memory_clock, | 422 | .get_memory_clock = &radeon_atom_get_memory_clock, |
@@ -449,9 +474,14 @@ static struct radeon_asic rs400_asic = { | |||
449 | .irq_set = &r100_irq_set, | 474 | .irq_set = &r100_irq_set, |
450 | .irq_process = &r100_irq_process, | 475 | .irq_process = &r100_irq_process, |
451 | .get_vblank_counter = &r100_get_vblank_counter, | 476 | .get_vblank_counter = &r100_get_vblank_counter, |
452 | .copy_blit = &r100_copy_blit, | 477 | .copy = { |
453 | .copy_dma = &r200_copy_dma, | 478 | .blit = &r100_copy_blit, |
454 | .copy = &r100_copy_blit, | 479 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
480 | .dma = &r200_copy_dma, | ||
481 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
482 | .copy = &r100_copy_blit, | ||
483 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
484 | }, | ||
455 | .get_engine_clock = &radeon_legacy_get_engine_clock, | 485 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
456 | .set_engine_clock = &radeon_legacy_set_engine_clock, | 486 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
457 | .get_memory_clock = &radeon_legacy_get_memory_clock, | 487 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
@@ -509,9 +539,14 @@ static struct radeon_asic rs600_asic = { | |||
509 | .irq_set = &rs600_irq_set, | 539 | .irq_set = &rs600_irq_set, |
510 | .irq_process = &rs600_irq_process, | 540 | .irq_process = &rs600_irq_process, |
511 | .get_vblank_counter = &rs600_get_vblank_counter, | 541 | .get_vblank_counter = &rs600_get_vblank_counter, |
512 | .copy_blit = &r100_copy_blit, | 542 | .copy = { |
513 | .copy_dma = &r200_copy_dma, | 543 | .blit = &r100_copy_blit, |
514 | .copy = &r100_copy_blit, | 544 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
545 | .dma = &r200_copy_dma, | ||
546 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
547 | .copy = &r100_copy_blit, | ||
548 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
549 | }, | ||
515 | .get_engine_clock = &radeon_atom_get_engine_clock, | 550 | .get_engine_clock = &radeon_atom_get_engine_clock, |
516 | .set_engine_clock = &radeon_atom_set_engine_clock, | 551 | .set_engine_clock = &radeon_atom_set_engine_clock, |
517 | .get_memory_clock = &radeon_atom_get_memory_clock, | 552 | .get_memory_clock = &radeon_atom_get_memory_clock, |
@@ -569,9 +604,14 @@ static struct radeon_asic rs690_asic = { | |||
569 | .irq_set = &rs600_irq_set, | 604 | .irq_set = &rs600_irq_set, |
570 | .irq_process = &rs600_irq_process, | 605 | .irq_process = &rs600_irq_process, |
571 | .get_vblank_counter = &rs600_get_vblank_counter, | 606 | .get_vblank_counter = &rs600_get_vblank_counter, |
572 | .copy_blit = &r100_copy_blit, | 607 | .copy = { |
573 | .copy_dma = &r200_copy_dma, | 608 | .blit = &r100_copy_blit, |
574 | .copy = &r200_copy_dma, | 609 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
610 | .dma = &r200_copy_dma, | ||
611 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
612 | .copy = &r200_copy_dma, | ||
613 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
614 | }, | ||
575 | .get_engine_clock = &radeon_atom_get_engine_clock, | 615 | .get_engine_clock = &radeon_atom_get_engine_clock, |
576 | .set_engine_clock = &radeon_atom_set_engine_clock, | 616 | .set_engine_clock = &radeon_atom_set_engine_clock, |
577 | .get_memory_clock = &radeon_atom_get_memory_clock, | 617 | .get_memory_clock = &radeon_atom_get_memory_clock, |
@@ -629,9 +669,14 @@ static struct radeon_asic rv515_asic = { | |||
629 | .irq_set = &rs600_irq_set, | 669 | .irq_set = &rs600_irq_set, |
630 | .irq_process = &rs600_irq_process, | 670 | .irq_process = &rs600_irq_process, |
631 | .get_vblank_counter = &rs600_get_vblank_counter, | 671 | .get_vblank_counter = &rs600_get_vblank_counter, |
632 | .copy_blit = &r100_copy_blit, | 672 | .copy = { |
633 | .copy_dma = &r200_copy_dma, | 673 | .blit = &r100_copy_blit, |
634 | .copy = &r100_copy_blit, | 674 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
675 | .dma = &r200_copy_dma, | ||
676 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
677 | .copy = &r100_copy_blit, | ||
678 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
679 | }, | ||
635 | .get_engine_clock = &radeon_atom_get_engine_clock, | 680 | .get_engine_clock = &radeon_atom_get_engine_clock, |
636 | .set_engine_clock = &radeon_atom_set_engine_clock, | 681 | .set_engine_clock = &radeon_atom_set_engine_clock, |
637 | .get_memory_clock = &radeon_atom_get_memory_clock, | 682 | .get_memory_clock = &radeon_atom_get_memory_clock, |
@@ -689,9 +734,14 @@ static struct radeon_asic r520_asic = { | |||
689 | .irq_set = &rs600_irq_set, | 734 | .irq_set = &rs600_irq_set, |
690 | .irq_process = &rs600_irq_process, | 735 | .irq_process = &rs600_irq_process, |
691 | .get_vblank_counter = &rs600_get_vblank_counter, | 736 | .get_vblank_counter = &rs600_get_vblank_counter, |
692 | .copy_blit = &r100_copy_blit, | 737 | .copy = { |
693 | .copy_dma = &r200_copy_dma, | 738 | .blit = &r100_copy_blit, |
694 | .copy = &r100_copy_blit, | 739 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
740 | .dma = &r200_copy_dma, | ||
741 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
742 | .copy = &r100_copy_blit, | ||
743 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
744 | }, | ||
695 | .get_engine_clock = &radeon_atom_get_engine_clock, | 745 | .get_engine_clock = &radeon_atom_get_engine_clock, |
696 | .set_engine_clock = &radeon_atom_set_engine_clock, | 746 | .set_engine_clock = &radeon_atom_set_engine_clock, |
697 | .get_memory_clock = &radeon_atom_get_memory_clock, | 747 | .get_memory_clock = &radeon_atom_get_memory_clock, |
@@ -748,9 +798,14 @@ static struct radeon_asic r600_asic = { | |||
748 | .irq_set = &r600_irq_set, | 798 | .irq_set = &r600_irq_set, |
749 | .irq_process = &r600_irq_process, | 799 | .irq_process = &r600_irq_process, |
750 | .get_vblank_counter = &rs600_get_vblank_counter, | 800 | .get_vblank_counter = &rs600_get_vblank_counter, |
751 | .copy_blit = &r600_copy_blit, | 801 | .copy = { |
752 | .copy_dma = NULL, | 802 | .blit = &r600_copy_blit, |
753 | .copy = &r600_copy_blit, | 803 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
804 | .dma = NULL, | ||
805 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
806 | .copy = &r600_copy_blit, | ||
807 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
808 | }, | ||
754 | .get_engine_clock = &radeon_atom_get_engine_clock, | 809 | .get_engine_clock = &radeon_atom_get_engine_clock, |
755 | .set_engine_clock = &radeon_atom_set_engine_clock, | 810 | .set_engine_clock = &radeon_atom_set_engine_clock, |
756 | .get_memory_clock = &radeon_atom_get_memory_clock, | 811 | .get_memory_clock = &radeon_atom_get_memory_clock, |
@@ -807,9 +862,14 @@ static struct radeon_asic rs780_asic = { | |||
807 | .irq_set = &r600_irq_set, | 862 | .irq_set = &r600_irq_set, |
808 | .irq_process = &r600_irq_process, | 863 | .irq_process = &r600_irq_process, |
809 | .get_vblank_counter = &rs600_get_vblank_counter, | 864 | .get_vblank_counter = &rs600_get_vblank_counter, |
810 | .copy_blit = &r600_copy_blit, | 865 | .copy = { |
811 | .copy_dma = NULL, | 866 | .blit = &r600_copy_blit, |
812 | .copy = &r600_copy_blit, | 867 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
868 | .dma = NULL, | ||
869 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
870 | .copy = &r600_copy_blit, | ||
871 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
872 | }, | ||
813 | .get_engine_clock = &radeon_atom_get_engine_clock, | 873 | .get_engine_clock = &radeon_atom_get_engine_clock, |
814 | .set_engine_clock = &radeon_atom_set_engine_clock, | 874 | .set_engine_clock = &radeon_atom_set_engine_clock, |
815 | .get_memory_clock = NULL, | 875 | .get_memory_clock = NULL, |
@@ -866,9 +926,14 @@ static struct radeon_asic rv770_asic = { | |||
866 | .irq_set = &r600_irq_set, | 926 | .irq_set = &r600_irq_set, |
867 | .irq_process = &r600_irq_process, | 927 | .irq_process = &r600_irq_process, |
868 | .get_vblank_counter = &rs600_get_vblank_counter, | 928 | .get_vblank_counter = &rs600_get_vblank_counter, |
869 | .copy_blit = &r600_copy_blit, | 929 | .copy = { |
870 | .copy_dma = NULL, | 930 | .blit = &r600_copy_blit, |
871 | .copy = &r600_copy_blit, | 931 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
932 | .dma = NULL, | ||
933 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
934 | .copy = &r600_copy_blit, | ||
935 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
936 | }, | ||
872 | .get_engine_clock = &radeon_atom_get_engine_clock, | 937 | .get_engine_clock = &radeon_atom_get_engine_clock, |
873 | .set_engine_clock = &radeon_atom_set_engine_clock, | 938 | .set_engine_clock = &radeon_atom_set_engine_clock, |
874 | .get_memory_clock = &radeon_atom_get_memory_clock, | 939 | .get_memory_clock = &radeon_atom_get_memory_clock, |
@@ -925,9 +990,14 @@ static struct radeon_asic evergreen_asic = { | |||
925 | .irq_set = &evergreen_irq_set, | 990 | .irq_set = &evergreen_irq_set, |
926 | .irq_process = &evergreen_irq_process, | 991 | .irq_process = &evergreen_irq_process, |
927 | .get_vblank_counter = &evergreen_get_vblank_counter, | 992 | .get_vblank_counter = &evergreen_get_vblank_counter, |
928 | .copy_blit = &r600_copy_blit, | 993 | .copy = { |
929 | .copy_dma = NULL, | 994 | .blit = &r600_copy_blit, |
930 | .copy = &r600_copy_blit, | 995 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
996 | .dma = NULL, | ||
997 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
998 | .copy = &r600_copy_blit, | ||
999 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
1000 | }, | ||
931 | .get_engine_clock = &radeon_atom_get_engine_clock, | 1001 | .get_engine_clock = &radeon_atom_get_engine_clock, |
932 | .set_engine_clock = &radeon_atom_set_engine_clock, | 1002 | .set_engine_clock = &radeon_atom_set_engine_clock, |
933 | .get_memory_clock = &radeon_atom_get_memory_clock, | 1003 | .get_memory_clock = &radeon_atom_get_memory_clock, |
@@ -984,9 +1054,14 @@ static struct radeon_asic sumo_asic = { | |||
984 | .irq_set = &evergreen_irq_set, | 1054 | .irq_set = &evergreen_irq_set, |
985 | .irq_process = &evergreen_irq_process, | 1055 | .irq_process = &evergreen_irq_process, |
986 | .get_vblank_counter = &evergreen_get_vblank_counter, | 1056 | .get_vblank_counter = &evergreen_get_vblank_counter, |
987 | .copy_blit = &r600_copy_blit, | 1057 | .copy = { |
988 | .copy_dma = NULL, | 1058 | .blit = &r600_copy_blit, |
989 | .copy = &r600_copy_blit, | 1059 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1060 | .dma = NULL, | ||
1061 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
1062 | .copy = &r600_copy_blit, | ||
1063 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
1064 | }, | ||
990 | .get_engine_clock = &radeon_atom_get_engine_clock, | 1065 | .get_engine_clock = &radeon_atom_get_engine_clock, |
991 | .set_engine_clock = &radeon_atom_set_engine_clock, | 1066 | .set_engine_clock = &radeon_atom_set_engine_clock, |
992 | .get_memory_clock = NULL, | 1067 | .get_memory_clock = NULL, |
@@ -1043,9 +1118,14 @@ static struct radeon_asic btc_asic = { | |||
1043 | .irq_set = &evergreen_irq_set, | 1118 | .irq_set = &evergreen_irq_set, |
1044 | .irq_process = &evergreen_irq_process, | 1119 | .irq_process = &evergreen_irq_process, |
1045 | .get_vblank_counter = &evergreen_get_vblank_counter, | 1120 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1046 | .copy_blit = &r600_copy_blit, | 1121 | .copy = { |
1047 | .copy_dma = NULL, | 1122 | .blit = &r600_copy_blit, |
1048 | .copy = &r600_copy_blit, | 1123 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1124 | .dma = NULL, | ||
1125 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
1126 | .copy = &r600_copy_blit, | ||
1127 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
1128 | }, | ||
1049 | .get_engine_clock = &radeon_atom_get_engine_clock, | 1129 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1050 | .set_engine_clock = &radeon_atom_set_engine_clock, | 1130 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1051 | .get_memory_clock = &radeon_atom_get_memory_clock, | 1131 | .get_memory_clock = &radeon_atom_get_memory_clock, |
@@ -1127,9 +1207,14 @@ static struct radeon_asic cayman_asic = { | |||
1127 | .irq_set = &evergreen_irq_set, | 1207 | .irq_set = &evergreen_irq_set, |
1128 | .irq_process = &evergreen_irq_process, | 1208 | .irq_process = &evergreen_irq_process, |
1129 | .get_vblank_counter = &evergreen_get_vblank_counter, | 1209 | .get_vblank_counter = &evergreen_get_vblank_counter, |
1130 | .copy_blit = &r600_copy_blit, | 1210 | .copy = { |
1131 | .copy_dma = NULL, | 1211 | .blit = &r600_copy_blit, |
1132 | .copy = &r600_copy_blit, | 1212 | .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX, |
1213 | .dma = NULL, | ||
1214 | .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
1215 | .copy = &r600_copy_blit, | ||
1216 | .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX, | ||
1217 | }, | ||
1133 | .get_engine_clock = &radeon_atom_get_engine_clock, | 1218 | .get_engine_clock = &radeon_atom_get_engine_clock, |
1134 | .set_engine_clock = &radeon_atom_set_engine_clock, | 1219 | .set_engine_clock = &radeon_atom_set_engine_clock, |
1135 | .get_memory_clock = &radeon_atom_get_memory_clock, | 1220 | .get_memory_clock = &radeon_atom_get_memory_clock, |
@@ -1174,9 +1259,6 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
1174 | else | 1259 | else |
1175 | rdev->num_crtc = 2; | 1260 | rdev->num_crtc = 2; |
1176 | 1261 | ||
1177 | /* set the ring used for bo copies */ | ||
1178 | rdev->copy_ring = RADEON_RING_TYPE_GFX_INDEX; | ||
1179 | |||
1180 | switch (rdev->family) { | 1262 | switch (rdev->family) { |
1181 | case CHIP_R100: | 1263 | case CHIP_R100: |
1182 | case CHIP_RV100: | 1264 | case CHIP_RV100: |
diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c index 58cee89215c7..fef7b722b05d 100644 --- a/drivers/gpu/drm/radeon/radeon_benchmark.c +++ b/drivers/gpu/drm/radeon/radeon_benchmark.c | |||
@@ -43,17 +43,19 @@ static int radeon_benchmark_do_move(struct radeon_device *rdev, unsigned size, | |||
43 | 43 | ||
44 | start_jiffies = jiffies; | 44 | start_jiffies = jiffies; |
45 | for (i = 0; i < n; i++) { | 45 | for (i = 0; i < n; i++) { |
46 | r = radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); | ||
47 | if (r) | ||
48 | return r; | ||
49 | |||
50 | switch (flag) { | 46 | switch (flag) { |
51 | case RADEON_BENCHMARK_COPY_DMA: | 47 | case RADEON_BENCHMARK_COPY_DMA: |
48 | r = radeon_fence_create(rdev, &fence, radeon_copy_dma_ring_index(rdev)); | ||
49 | if (r) | ||
50 | return r; | ||
52 | r = radeon_copy_dma(rdev, saddr, daddr, | 51 | r = radeon_copy_dma(rdev, saddr, daddr, |
53 | size / RADEON_GPU_PAGE_SIZE, | 52 | size / RADEON_GPU_PAGE_SIZE, |
54 | fence); | 53 | fence); |
55 | break; | 54 | break; |
56 | case RADEON_BENCHMARK_COPY_BLIT: | 55 | case RADEON_BENCHMARK_COPY_BLIT: |
56 | r = radeon_fence_create(rdev, &fence, radeon_copy_blit_ring_index(rdev)); | ||
57 | if (r) | ||
58 | return r; | ||
57 | r = radeon_copy_blit(rdev, saddr, daddr, | 59 | r = radeon_copy_blit(rdev, saddr, daddr, |
58 | size / RADEON_GPU_PAGE_SIZE, | 60 | size / RADEON_GPU_PAGE_SIZE, |
59 | fence); | 61 | fence); |
@@ -129,7 +131,7 @@ static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size, | |||
129 | /* r100 doesn't have dma engine so skip the test */ | 131 | /* r100 doesn't have dma engine so skip the test */ |
130 | /* also, VRAM-to-VRAM test doesn't make much sense for DMA */ | 132 | /* also, VRAM-to-VRAM test doesn't make much sense for DMA */ |
131 | /* skip it as well if domains are the same */ | 133 | /* skip it as well if domains are the same */ |
132 | if ((rdev->asic->copy_dma) && (sdomain != ddomain)) { | 134 | if ((rdev->asic->copy.dma) && (sdomain != ddomain)) { |
133 | time = radeon_benchmark_do_move(rdev, size, saddr, daddr, | 135 | time = radeon_benchmark_do_move(rdev, size, saddr, daddr, |
134 | RADEON_BENCHMARK_COPY_DMA, n); | 136 | RADEON_BENCHMARK_COPY_DMA, n); |
135 | if (time < 0) | 137 | if (time < 0) |
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index c421e77ace71..f493c6403af5 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c | |||
@@ -226,7 +226,7 @@ static int radeon_move_blit(struct ttm_buffer_object *bo, | |||
226 | int r, i; | 226 | int r, i; |
227 | 227 | ||
228 | rdev = radeon_get_rdev(bo->bdev); | 228 | rdev = radeon_get_rdev(bo->bdev); |
229 | r = radeon_fence_create(rdev, &fence, rdev->copy_ring); | 229 | r = radeon_fence_create(rdev, &fence, radeon_copy_ring_index(rdev)); |
230 | if (unlikely(r)) { | 230 | if (unlikely(r)) { |
231 | return r; | 231 | return r; |
232 | } | 232 | } |
@@ -255,7 +255,7 @@ static int radeon_move_blit(struct ttm_buffer_object *bo, | |||
255 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); | 255 | DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); |
256 | return -EINVAL; | 256 | return -EINVAL; |
257 | } | 257 | } |
258 | if (!rdev->ring[rdev->copy_ring].ready) { | 258 | if (!rdev->ring[radeon_copy_ring_index(rdev)].ready) { |
259 | DRM_ERROR("Trying to move memory with ring turned off.\n"); | 259 | DRM_ERROR("Trying to move memory with ring turned off.\n"); |
260 | return -EINVAL; | 260 | return -EINVAL; |
261 | } | 261 | } |
@@ -266,7 +266,7 @@ static int radeon_move_blit(struct ttm_buffer_object *bo, | |||
266 | if (rdev->family >= CHIP_R600) { | 266 | if (rdev->family >= CHIP_R600) { |
267 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | 267 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
268 | /* no need to sync to our own or unused rings */ | 268 | /* no need to sync to our own or unused rings */ |
269 | if (i == rdev->copy_ring || !rdev->ring[i].ready) | 269 | if (i == radeon_copy_ring_index(rdev) || !rdev->ring[i].ready) |
270 | continue; | 270 | continue; |
271 | 271 | ||
272 | if (!fence->semaphore) { | 272 | if (!fence->semaphore) { |
@@ -283,12 +283,12 @@ static int radeon_move_blit(struct ttm_buffer_object *bo, | |||
283 | radeon_semaphore_emit_signal(rdev, i, fence->semaphore); | 283 | radeon_semaphore_emit_signal(rdev, i, fence->semaphore); |
284 | radeon_ring_unlock_commit(rdev, &rdev->ring[i]); | 284 | radeon_ring_unlock_commit(rdev, &rdev->ring[i]); |
285 | 285 | ||
286 | r = radeon_ring_lock(rdev, &rdev->ring[rdev->copy_ring], 3); | 286 | r = radeon_ring_lock(rdev, &rdev->ring[radeon_copy_ring_index(rdev)], 3); |
287 | /* FIXME: handle ring lock error */ | 287 | /* FIXME: handle ring lock error */ |
288 | if (r) | 288 | if (r) |
289 | continue; | 289 | continue; |
290 | radeon_semaphore_emit_wait(rdev, rdev->copy_ring, fence->semaphore); | 290 | radeon_semaphore_emit_wait(rdev, radeon_copy_ring_index(rdev), fence->semaphore); |
291 | radeon_ring_unlock_commit(rdev, &rdev->ring[rdev->copy_ring]); | 291 | radeon_ring_unlock_commit(rdev, &rdev->ring[radeon_copy_ring_index(rdev)]); |
292 | } | 292 | } |
293 | } | 293 | } |
294 | 294 | ||
@@ -410,7 +410,8 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, | |||
410 | radeon_move_null(bo, new_mem); | 410 | radeon_move_null(bo, new_mem); |
411 | return 0; | 411 | return 0; |
412 | } | 412 | } |
413 | if (!rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready || rdev->asic->copy == NULL) { | 413 | if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || |
414 | rdev->asic->copy.copy == NULL) { | ||
414 | /* use memcpy */ | 415 | /* use memcpy */ |
415 | goto memcpy; | 416 | goto memcpy; |
416 | } | 417 | } |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index a1668b659ddd..a86698137df4 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -1074,7 +1074,7 @@ static int rv770_startup(struct radeon_device *rdev) | |||
1074 | r = r600_blit_init(rdev); | 1074 | r = r600_blit_init(rdev); |
1075 | if (r) { | 1075 | if (r) { |
1076 | r600_blit_fini(rdev); | 1076 | r600_blit_fini(rdev); |
1077 | rdev->asic->copy = NULL; | 1077 | rdev->asic->copy.copy = NULL; |
1078 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); | 1078 | dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
1079 | } | 1079 | } |
1080 | 1080 | ||