diff options
author | Gabor Juhos <juhosg@openwrt.org> | 2009-03-06 03:08:53 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-03-16 18:09:32 -0400 |
commit | 6b765deb01dd076e64a4b01d2101d74206e7df84 (patch) | |
tree | eb9069c2982de78d040331ab134bf45ace94f98a /drivers | |
parent | d4376ebe168024695f15bfdf603ea6f083dc80f8 (diff) |
ath9k: fix AR_SREV_9100_OR_LATER macro
The current macro is wrong, because detects some AR5416 devices as an
AR9100 device. The AR5416 devices would have performance issues after
this change, because the contents of the ar5416 specific and of the
ar9100 specificinitval arrays are swapped. Fortunately we can correct
this with the rename of the arrays simply.
Changes-licesed-under: ISC
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/wireless/ath9k/initvals.h | 44 | ||||
-rw-r--r-- | drivers/net/wireless/ath9k/reg.h | 2 |
2 files changed, 23 insertions, 23 deletions
diff --git a/drivers/net/wireless/ath9k/initvals.h b/drivers/net/wireless/ath9k/initvals.h index c32bc3b00d95..1d60c3706f1c 100644 --- a/drivers/net/wireless/ath9k/initvals.h +++ b/drivers/net/wireless/ath9k/initvals.h | |||
@@ -14,7 +14,7 @@ | |||
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
15 | */ | 15 | */ |
16 | 16 | ||
17 | static const u32 ar5416Modes_9100[][6] = { | 17 | static const u32 ar5416Modes[][6] = { |
18 | { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, | 18 | { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, |
19 | { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, | 19 | { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, |
20 | { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, | 20 | { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, |
@@ -78,7 +78,7 @@ static const u32 ar5416Modes_9100[][6] = { | |||
78 | { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | 78 | { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, |
79 | }; | 79 | }; |
80 | 80 | ||
81 | static const u32 ar5416Common_9100[][2] = { | 81 | static const u32 ar5416Common[][2] = { |
82 | { 0x0000000c, 0x00000000 }, | 82 | { 0x0000000c, 0x00000000 }, |
83 | { 0x00000030, 0x00020015 }, | 83 | { 0x00000030, 0x00020015 }, |
84 | { 0x00000034, 0x00000005 }, | 84 | { 0x00000034, 0x00000005 }, |
@@ -456,12 +456,12 @@ static const u32 ar5416Common_9100[][2] = { | |||
456 | { 0x0000a3e0, 0x000001ce }, | 456 | { 0x0000a3e0, 0x000001ce }, |
457 | }; | 457 | }; |
458 | 458 | ||
459 | static const u32 ar5416Bank0_9100[][2] = { | 459 | static const u32 ar5416Bank0[][2] = { |
460 | { 0x000098b0, 0x1e5795e5 }, | 460 | { 0x000098b0, 0x1e5795e5 }, |
461 | { 0x000098e0, 0x02008020 }, | 461 | { 0x000098e0, 0x02008020 }, |
462 | }; | 462 | }; |
463 | 463 | ||
464 | static const u32 ar5416BB_RfGain_9100[][3] = { | 464 | static const u32 ar5416BB_RfGain[][3] = { |
465 | { 0x00009a00, 0x00000000, 0x00000000 }, | 465 | { 0x00009a00, 0x00000000, 0x00000000 }, |
466 | { 0x00009a04, 0x00000040, 0x00000040 }, | 466 | { 0x00009a04, 0x00000040, 0x00000040 }, |
467 | { 0x00009a08, 0x00000080, 0x00000080 }, | 467 | { 0x00009a08, 0x00000080, 0x00000080 }, |
@@ -528,21 +528,21 @@ static const u32 ar5416BB_RfGain_9100[][3] = { | |||
528 | { 0x00009afc, 0x000000f9, 0x000000f9 }, | 528 | { 0x00009afc, 0x000000f9, 0x000000f9 }, |
529 | }; | 529 | }; |
530 | 530 | ||
531 | static const u32 ar5416Bank1_9100[][2] = { | 531 | static const u32 ar5416Bank1[][2] = { |
532 | { 0x000098b0, 0x02108421 }, | 532 | { 0x000098b0, 0x02108421 }, |
533 | { 0x000098ec, 0x00000008 }, | 533 | { 0x000098ec, 0x00000008 }, |
534 | }; | 534 | }; |
535 | 535 | ||
536 | static const u32 ar5416Bank2_9100[][2] = { | 536 | static const u32 ar5416Bank2[][2] = { |
537 | { 0x000098b0, 0x0e73ff17 }, | 537 | { 0x000098b0, 0x0e73ff17 }, |
538 | { 0x000098e0, 0x00000420 }, | 538 | { 0x000098e0, 0x00000420 }, |
539 | }; | 539 | }; |
540 | 540 | ||
541 | static const u32 ar5416Bank3_9100[][3] = { | 541 | static const u32 ar5416Bank3[][3] = { |
542 | { 0x000098f0, 0x01400018, 0x01c00018 }, | 542 | { 0x000098f0, 0x01400018, 0x01c00018 }, |
543 | }; | 543 | }; |
544 | 544 | ||
545 | static const u32 ar5416Bank6_9100[][3] = { | 545 | static const u32 ar5416Bank6[][3] = { |
546 | 546 | ||
547 | { 0x0000989c, 0x00000000, 0x00000000 }, | 547 | { 0x0000989c, 0x00000000, 0x00000000 }, |
548 | { 0x0000989c, 0x00000000, 0x00000000 }, | 548 | { 0x0000989c, 0x00000000, 0x00000000 }, |
@@ -579,7 +579,7 @@ static const u32 ar5416Bank6_9100[][3] = { | |||
579 | { 0x000098d0, 0x0000000f, 0x0010000f }, | 579 | { 0x000098d0, 0x0000000f, 0x0010000f }, |
580 | }; | 580 | }; |
581 | 581 | ||
582 | static const u32 ar5416Bank6TPC_9100[][3] = { | 582 | static const u32 ar5416Bank6TPC[][3] = { |
583 | { 0x0000989c, 0x00000000, 0x00000000 }, | 583 | { 0x0000989c, 0x00000000, 0x00000000 }, |
584 | { 0x0000989c, 0x00000000, 0x00000000 }, | 584 | { 0x0000989c, 0x00000000, 0x00000000 }, |
585 | { 0x0000989c, 0x00000000, 0x00000000 }, | 585 | { 0x0000989c, 0x00000000, 0x00000000 }, |
@@ -615,13 +615,13 @@ static const u32 ar5416Bank6TPC_9100[][3] = { | |||
615 | { 0x000098d0, 0x0000000f, 0x0010000f }, | 615 | { 0x000098d0, 0x0000000f, 0x0010000f }, |
616 | }; | 616 | }; |
617 | 617 | ||
618 | static const u32 ar5416Bank7_9100[][2] = { | 618 | static const u32 ar5416Bank7[][2] = { |
619 | { 0x0000989c, 0x00000500 }, | 619 | { 0x0000989c, 0x00000500 }, |
620 | { 0x0000989c, 0x00000800 }, | 620 | { 0x0000989c, 0x00000800 }, |
621 | { 0x000098cc, 0x0000000e }, | 621 | { 0x000098cc, 0x0000000e }, |
622 | }; | 622 | }; |
623 | 623 | ||
624 | static const u32 ar5416Addac_9100[][2] = { | 624 | static const u32 ar5416Addac[][2] = { |
625 | {0x0000989c, 0x00000000 }, | 625 | {0x0000989c, 0x00000000 }, |
626 | {0x0000989c, 0x00000003 }, | 626 | {0x0000989c, 0x00000003 }, |
627 | {0x0000989c, 0x00000000 }, | 627 | {0x0000989c, 0x00000000 }, |
@@ -661,7 +661,7 @@ static const u32 ar5416Addac_9100[][2] = { | |||
661 | {0x000098cc, 0x00000000 }, | 661 | {0x000098cc, 0x00000000 }, |
662 | }; | 662 | }; |
663 | 663 | ||
664 | static const u32 ar5416Modes[][6] = { | 664 | static const u32 ar5416Modes_9100[][6] = { |
665 | { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, | 665 | { 0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0 }, |
666 | { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, | 666 | { 0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0 }, |
667 | { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, | 667 | { 0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180 }, |
@@ -735,7 +735,7 @@ static const u32 ar5416Modes[][6] = { | |||
735 | { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, | 735 | { 0x0000a334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, |
736 | }; | 736 | }; |
737 | 737 | ||
738 | static const u32 ar5416Common[][2] = { | 738 | static const u32 ar5416Common_9100[][2] = { |
739 | { 0x0000000c, 0x00000000 }, | 739 | { 0x0000000c, 0x00000000 }, |
740 | { 0x00000030, 0x00020015 }, | 740 | { 0x00000030, 0x00020015 }, |
741 | { 0x00000034, 0x00000005 }, | 741 | { 0x00000034, 0x00000005 }, |
@@ -1109,12 +1109,12 @@ static const u32 ar5416Common[][2] = { | |||
1109 | { 0x0000a3e0, 0x000001ce }, | 1109 | { 0x0000a3e0, 0x000001ce }, |
1110 | }; | 1110 | }; |
1111 | 1111 | ||
1112 | static const u32 ar5416Bank0[][2] = { | 1112 | static const u32 ar5416Bank0_9100[][2] = { |
1113 | { 0x000098b0, 0x1e5795e5 }, | 1113 | { 0x000098b0, 0x1e5795e5 }, |
1114 | { 0x000098e0, 0x02008020 }, | 1114 | { 0x000098e0, 0x02008020 }, |
1115 | }; | 1115 | }; |
1116 | 1116 | ||
1117 | static const u32 ar5416BB_RfGain[][3] = { | 1117 | static const u32 ar5416BB_RfGain_9100[][3] = { |
1118 | { 0x00009a00, 0x00000000, 0x00000000 }, | 1118 | { 0x00009a00, 0x00000000, 0x00000000 }, |
1119 | { 0x00009a04, 0x00000040, 0x00000040 }, | 1119 | { 0x00009a04, 0x00000040, 0x00000040 }, |
1120 | { 0x00009a08, 0x00000080, 0x00000080 }, | 1120 | { 0x00009a08, 0x00000080, 0x00000080 }, |
@@ -1181,21 +1181,21 @@ static const u32 ar5416BB_RfGain[][3] = { | |||
1181 | { 0x00009afc, 0x000000f9, 0x000000f9 }, | 1181 | { 0x00009afc, 0x000000f9, 0x000000f9 }, |
1182 | }; | 1182 | }; |
1183 | 1183 | ||
1184 | static const u32 ar5416Bank1[][2] = { | 1184 | static const u32 ar5416Bank1_9100[][2] = { |
1185 | { 0x000098b0, 0x02108421}, | 1185 | { 0x000098b0, 0x02108421}, |
1186 | { 0x000098ec, 0x00000008}, | 1186 | { 0x000098ec, 0x00000008}, |
1187 | }; | 1187 | }; |
1188 | 1188 | ||
1189 | static const u32 ar5416Bank2[][2] = { | 1189 | static const u32 ar5416Bank2_9100[][2] = { |
1190 | { 0x000098b0, 0x0e73ff17}, | 1190 | { 0x000098b0, 0x0e73ff17}, |
1191 | { 0x000098e0, 0x00000420}, | 1191 | { 0x000098e0, 0x00000420}, |
1192 | }; | 1192 | }; |
1193 | 1193 | ||
1194 | static const u32 ar5416Bank3[][3] = { | 1194 | static const u32 ar5416Bank3_9100[][3] = { |
1195 | { 0x000098f0, 0x01400018, 0x01c00018 }, | 1195 | { 0x000098f0, 0x01400018, 0x01c00018 }, |
1196 | }; | 1196 | }; |
1197 | 1197 | ||
1198 | static const u32 ar5416Bank6[][3] = { | 1198 | static const u32 ar5416Bank6_9100[][3] = { |
1199 | 1199 | ||
1200 | { 0x0000989c, 0x00000000, 0x00000000 }, | 1200 | { 0x0000989c, 0x00000000, 0x00000000 }, |
1201 | { 0x0000989c, 0x00000000, 0x00000000 }, | 1201 | { 0x0000989c, 0x00000000, 0x00000000 }, |
@@ -1233,7 +1233,7 @@ static const u32 ar5416Bank6[][3] = { | |||
1233 | }; | 1233 | }; |
1234 | 1234 | ||
1235 | 1235 | ||
1236 | static const u32 ar5416Bank6TPC[][3] = { | 1236 | static const u32 ar5416Bank6TPC_9100[][3] = { |
1237 | 1237 | ||
1238 | { 0x0000989c, 0x00000000, 0x00000000 }, | 1238 | { 0x0000989c, 0x00000000, 0x00000000 }, |
1239 | { 0x0000989c, 0x00000000, 0x00000000 }, | 1239 | { 0x0000989c, 0x00000000, 0x00000000 }, |
@@ -1270,13 +1270,13 @@ static const u32 ar5416Bank6TPC[][3] = { | |||
1270 | { 0x000098d0, 0x0000000f, 0x0010000f }, | 1270 | { 0x000098d0, 0x0000000f, 0x0010000f }, |
1271 | }; | 1271 | }; |
1272 | 1272 | ||
1273 | static const u32 ar5416Bank7[][2] = { | 1273 | static const u32 ar5416Bank7_9100[][2] = { |
1274 | { 0x0000989c, 0x00000500 }, | 1274 | { 0x0000989c, 0x00000500 }, |
1275 | { 0x0000989c, 0x00000800 }, | 1275 | { 0x0000989c, 0x00000800 }, |
1276 | { 0x000098cc, 0x0000000e }, | 1276 | { 0x000098cc, 0x0000000e }, |
1277 | }; | 1277 | }; |
1278 | 1278 | ||
1279 | static const u32 ar5416Addac[][2] = { | 1279 | static const u32 ar5416Addac_9100[][2] = { |
1280 | {0x0000989c, 0x00000000 }, | 1280 | {0x0000989c, 0x00000000 }, |
1281 | {0x0000989c, 0x00000000 }, | 1281 | {0x0000989c, 0x00000000 }, |
1282 | {0x0000989c, 0x00000000 }, | 1282 | {0x0000989c, 0x00000000 }, |
diff --git a/drivers/net/wireless/ath9k/reg.h b/drivers/net/wireless/ath9k/reg.h index 1be4c71935ea..d86e90e38173 100644 --- a/drivers/net/wireless/ath9k/reg.h +++ b/drivers/net/wireless/ath9k/reg.h | |||
@@ -754,7 +754,7 @@ | |||
754 | #define AR_SREV_9100(ah) \ | 754 | #define AR_SREV_9100(ah) \ |
755 | ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100) | 755 | ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100) |
756 | #define AR_SREV_9100_OR_LATER(_ah) \ | 756 | #define AR_SREV_9100_OR_LATER(_ah) \ |
757 | (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_5416_PCIE)) | 757 | (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) |
758 | 758 | ||
759 | #define AR_SREV_9160(_ah) \ | 759 | #define AR_SREV_9160(_ah) \ |
760 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160)) | 760 | (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160)) |