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authorKrzysztof Helt <krzysztof.h1@wp.pl>2007-10-16 04:28:48 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-16 12:43:15 -0400
commit4f05b53b28cc7a2b868bc13d19d88cd858e759b6 (patch)
tree9f4bcdd3aff5d00523e25d080c4677bc98e5b18d /drivers
parent9d775e17b5b9a204a0cb746f1f7f6ef11f4d869d (diff)
tdfxfb: code improvements
This patch improves source code mainly by killing redundant variable loads, reducing number of variables, simplifying conditional branches, etc. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Antonino Daplas <adaplas@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/video/tdfxfb.c161
1 files changed, 47 insertions, 114 deletions
diff --git a/drivers/video/tdfxfb.c b/drivers/video/tdfxfb.c
index c032f6feb13e..7d0c50e3a40b 100644
--- a/drivers/video/tdfxfb.c
+++ b/drivers/video/tdfxfb.c
@@ -63,12 +63,9 @@
63#include <linux/string.h> 63#include <linux/string.h>
64#include <linux/mm.h> 64#include <linux/mm.h>
65#include <linux/slab.h> 65#include <linux/slab.h>
66#include <linux/delay.h>
67#include <linux/interrupt.h>
68#include <linux/fb.h> 66#include <linux/fb.h>
69#include <linux/init.h> 67#include <linux/init.h>
70#include <linux/pci.h> 68#include <linux/pci.h>
71#include <linux/nvram.h>
72#include <asm/io.h> 69#include <asm/io.h>
73#include <linux/timer.h> 70#include <linux/timer.h>
74#include <linux/spinlock.h> 71#include <linux/spinlock.h>
@@ -159,26 +156,15 @@ static char *mode_option __devinitdata = NULL;
159 * Hardware-specific funcions 156 * Hardware-specific funcions
160 * ------------------------------------------------------------------------- */ 157 * ------------------------------------------------------------------------- */
161 158
162#ifdef VGA_REG_IO
163static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
164{
165 return inb(reg);
166}
167
168static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
169{
170 outb(val, reg);
171}
172#else
173static inline u8 vga_inb(struct tdfx_par *par, u32 reg) 159static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
174{ 160{
175 return inb(par->iobase + reg - 0x300); 161 return inb(par->iobase + reg - 0x300);
176} 162}
163
177static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) 164static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
178{ 165{
179 outb(val, par->iobase + reg - 0x300); 166 outb(val, par->iobase + reg - 0x300);
180} 167}
181#endif
182 168
183static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) 169static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val)
184{ 170{
@@ -279,11 +265,11 @@ static int banshee_wait_idle(struct fb_info *info)
279 banshee_make_room(par, 1); 265 banshee_make_room(par, 1);
280 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP); 266 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
281 267
282 while (1) { 268 do {
283 i = (tdfx_inl(par, STATUS) & STATUS_BUSY) ? 0 : i + 1; 269 if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0)
284 if (i == 3) 270 i++;
285 break; 271 } while (i < 3);
286 } 272
287 return 0; 273 return 0;
288} 274}
289 275
@@ -313,16 +299,17 @@ static u32 do_calc_pll(int freq, int *freq_out)
313 * Estimate value of n that produces target frequency 299 * Estimate value of n that produces target frequency
314 * with current m and k 300 * with current m and k
315 */ 301 */
316 int n_estimated = (freq * (m + 2) * (1 << k) / fref) - 2; 302 int n_estimated = ((freq * (m + 2) << k) / fref) - 2;
317 303
318 /* Search neighborhood of estimated n */ 304 /* Search neighborhood of estimated n */
319 for (n = max(0, n_estimated - 1); 305 for (n = max(0, n_estimated);
320 n <= min(255, n_estimated + 1); n++) { 306 n <= min(255, n_estimated + 1);
307 n++) {
321 /* 308 /*
322 * Calculate PLL freqency with current m, k and 309 * Calculate PLL freqency with current m, k and
323 * estimated n 310 * estimated n
324 */ 311 */
325 int f = fref * (n + 2) / (m + 2) / (1 << k); 312 int f = (fref * (n + 2) / (m + 2)) >> k;
326 int error = abs(f - freq); 313 int error = abs(f - freq);
327 314
328 /* 315 /*
@@ -342,7 +329,7 @@ static u32 do_calc_pll(int freq, int *freq_out)
342 n = best_n; 329 n = best_n;
343 m = best_m; 330 m = best_m;
344 k = best_k; 331 k = best_k;
345 *freq_out = fref * (n + 2) / (m + 2) / (1 << k); 332 *freq_out = (fref * (n + 2) / (m + 2)) >> k;
346 333
347 return (n << 8) | (m << 2) | k; 334 return (n << 8) | (m << 2) | k;
348} 335}
@@ -387,7 +374,7 @@ static void do_write_regs(struct fb_info *info, struct banshee_reg *reg)
387 vga_enable_palette(par); 374 vga_enable_palette(par);
388 vga_enable_video(par); 375 vga_enable_video(par);
389 376
390 banshee_make_room(par, 11); 377 banshee_make_room(par, 9);
391 tdfx_outl(par, VGAINIT0, reg->vgainit0); 378 tdfx_outl(par, VGAINIT0, reg->vgainit0);
392 tdfx_outl(par, DACMODE, reg->dacmode); 379 tdfx_outl(par, DACMODE, reg->dacmode);
393 tdfx_outl(par, VIDDESKSTRIDE, reg->stride); 380 tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
@@ -400,8 +387,8 @@ static void do_write_regs(struct fb_info *info, struct banshee_reg *reg)
400 tdfx_outl(par, MISCINIT0, reg->miscinit0); 387 tdfx_outl(par, MISCINIT0, reg->miscinit0);
401 388
402 banshee_make_room(par, 8); 389 banshee_make_room(par, 8);
403 tdfx_outl(par, SRCBASE, reg->srcbase); 390 tdfx_outl(par, SRCBASE, reg->startaddr);
404 tdfx_outl(par, DSTBASE, reg->dstbase); 391 tdfx_outl(par, DSTBASE, reg->startaddr);
405 tdfx_outl(par, COMMANDEXTRA_2D, 0); 392 tdfx_outl(par, COMMANDEXTRA_2D, 0);
406 tdfx_outl(par, CLIP0MIN, 0); 393 tdfx_outl(par, CLIP0MIN, 0);
407 tdfx_outl(par, CLIP0MAX, 0x0fff0fff); 394 tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
@@ -414,32 +401,24 @@ static void do_write_regs(struct fb_info *info, struct banshee_reg *reg)
414 401
415static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id) 402static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
416{ 403{
417 u32 draminit0; 404 u32 draminit0 = tdfx_inl(par, DRAMINIT0);
418 u32 draminit1; 405 u32 draminit1 = tdfx_inl(par, DRAMINIT1);
419 u32 miscinit1; 406 u32 miscinit1;
420 407 int num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
421 int num_chips;
422 int chip_size; /* in MB */ 408 int chip_size; /* in MB */
423 u32 lfbsize; 409 int has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
424 int has_sgram;
425
426 draminit0 = tdfx_inl(par, DRAMINIT0);
427 draminit1 = tdfx_inl(par, DRAMINIT1);
428
429 num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
430 410
431 if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) { 411 if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
432 /* Banshee/Voodoo3 */ 412 /* Banshee/Voodoo3 */
433 has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
434 chip_size = 2; 413 chip_size = 2;
435 if (has_sgram) 414 if (has_sgram && (draminit0 & DRAMINIT0_SGRAM_TYPE))
436 chip_size = (draminit0 & DRAMINIT0_SGRAM_TYPE) ? 2 : 1; 415 chip_size = 1;
437 } else { 416 } else {
438 /* Voodoo4/5 */ 417 /* Voodoo4/5 */
439 has_sgram = 0; 418 has_sgram = 0;
440 chip_size = 1 << ((draminit0 & DRAMINIT0_SGRAM_TYPE_MASK) >> DRAMINIT0_SGRAM_TYPE_SHIFT); 419 chip_size = draminit0 & DRAMINIT0_SGRAM_TYPE_MASK;
420 chip_size = 1 << (chip_size >> DRAMINIT0_SGRAM_TYPE_SHIFT);
441 } 421 }
442 lfbsize = num_chips * chip_size * 1024 * 1024;
443 422
444 /* disable block writes for SDRAM */ 423 /* disable block writes for SDRAM */
445 miscinit1 = tdfx_inl(par, MISCINIT1); 424 miscinit1 = tdfx_inl(par, MISCINIT1);
@@ -448,7 +427,7 @@ static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
448 427
449 banshee_make_room(par, 1); 428 banshee_make_room(par, 1);
450 tdfx_outl(par, MISCINIT1, miscinit1); 429 tdfx_outl(par, MISCINIT1, miscinit1);
451 return lfbsize; 430 return num_chips * chip_size * 1024l * 1024;
452} 431}
453 432
454/* ------------------------------------------------------------------------- */ 433/* ------------------------------------------------------------------------- */
@@ -548,17 +527,18 @@ static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
548static int tdfxfb_set_par(struct fb_info *info) 527static int tdfxfb_set_par(struct fb_info *info)
549{ 528{
550 struct tdfx_par *par = info->par; 529 struct tdfx_par *par = info->par;
551 u32 hdispend, hsyncsta, hsyncend, htotal; 530 u32 hdispend = info->var.xres;
531 u32 hsyncsta = hdispend + info->var.right_margin;
532 u32 hsyncend = hsyncsta + info->var.hsync_len;
533 u32 htotal = hsyncend + info->var.left_margin;
552 u32 hd, hs, he, ht, hbs, hbe; 534 u32 hd, hs, he, ht, hbs, hbe;
553 u32 vd, vs, ve, vt, vbs, vbe; 535 u32 vd, vs, ve, vt, vbs, vbe;
554 struct banshee_reg reg; 536 struct banshee_reg reg;
555 int fout, freq; 537 int fout, freq;
556 u32 wd, cpp; 538 u32 wd;
557 539 u32 cpp = (info->var.bits_per_pixel + 7) >> 3;
558 par->baseline = 0;
559 540
560 memset(&reg, 0, sizeof(reg)); 541 memset(&reg, 0, sizeof(reg));
561 cpp = (info->var.bits_per_pixel + 7) / 8;
562 542
563 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | 543 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE |
564 VIDCFG_CURS_X11 | 544 VIDCFG_CURS_X11 |
@@ -568,14 +548,8 @@ static int tdfxfb_set_par(struct fb_info *info)
568 /* PLL settings */ 548 /* PLL settings */
569 freq = PICOS2KHZ(info->var.pixclock); 549 freq = PICOS2KHZ(info->var.pixclock);
570 550
571 reg.dacmode = 0;
572 reg.vidcfg &= ~VIDCFG_2X; 551 reg.vidcfg &= ~VIDCFG_2X;
573 552
574 hdispend = info->var.xres;
575 hsyncsta = hdispend + info->var.right_margin;
576 hsyncend = hsyncsta + info->var.hsync_len;
577 htotal = hsyncend + info->var.left_margin;
578
579 if (freq > par->max_pixclock / 2) { 553 if (freq > par->max_pixclock / 2) {
580 freq = freq > par->max_pixclock ? par->max_pixclock : freq; 554 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
581 reg.dacmode |= DACMODE_2X; 555 reg.dacmode |= DACMODE_2X;
@@ -598,11 +572,16 @@ static int tdfxfb_set_par(struct fb_info *info)
598 vs = vd + (info->var.lower_margin << 1); 572 vs = vd + (info->var.lower_margin << 1);
599 ve = vs + (info->var.vsync_len << 1); 573 ve = vs + (info->var.vsync_len << 1);
600 vbe = vt = ve + (info->var.upper_margin << 1) - 1; 574 vbe = vt = ve + (info->var.upper_margin << 1) - 1;
575 reg.screensize = info->var.xres | (info->var.yres << 13);
576 reg.vidcfg |= VIDCFG_HALF_MODE;
577 reg.crt[0x09] = 0x80;
601 } else { 578 } else {
602 vbs = vd = info->var.yres - 1; 579 vbs = vd = info->var.yres - 1;
603 vs = vd + info->var.lower_margin; 580 vs = vd + info->var.lower_margin;
604 ve = vs + info->var.vsync_len; 581 ve = vs + info->var.vsync_len;
605 vbe = vt = ve + info->var.upper_margin - 1; 582 vbe = vt = ve + info->var.upper_margin - 1;
583 reg.screensize = info->var.xres | (info->var.yres << 12);
584 reg.vidcfg &= ~VIDCFG_HALF_MODE;
606 } 585 }
607 586
608 /* this is all pretty standard VGA register stuffing */ 587 /* this is all pretty standard VGA register stuffing */
@@ -611,11 +590,6 @@ static int tdfxfb_set_par(struct fb_info *info)
611 info->var.xres < 480 ? 0x60 : 590 info->var.xres < 480 ? 0x60 :
612 info->var.xres < 768 ? 0xe0 : 0x20); 591 info->var.xres < 768 ? 0xe0 : 0x20);
613 592
614 reg.gra[0x00] = 0x00;
615 reg.gra[0x01] = 0x00;
616 reg.gra[0x02] = 0x00;
617 reg.gra[0x03] = 0x00;
618 reg.gra[0x04] = 0x00;
619 reg.gra[0x05] = 0x40; 593 reg.gra[0x05] = 0x40;
620 reg.gra[0x06] = 0x05; 594 reg.gra[0x06] = 0x05;
621 reg.gra[0x07] = 0x0f; 595 reg.gra[0x07] = 0x0f;
@@ -638,10 +612,7 @@ static int tdfxfb_set_par(struct fb_info *info)
638 reg.att[0x0e] = 0x0e; 612 reg.att[0x0e] = 0x0e;
639 reg.att[0x0f] = 0x0f; 613 reg.att[0x0f] = 0x0f;
640 reg.att[0x10] = 0x41; 614 reg.att[0x10] = 0x41;
641 reg.att[0x11] = 0x00;
642 reg.att[0x12] = 0x0f; 615 reg.att[0x12] = 0x0f;
643 reg.att[0x13] = 0x00;
644 reg.att[0x14] = 0x00;
645 616
646 reg.seq[0x00] = 0x03; 617 reg.seq[0x00] = 0x03;
647 reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */ 618 reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
@@ -663,19 +634,11 @@ static int tdfxfb_set_par(struct fb_info *info)
663 ((vs & 0x100) >> 6) | 634 ((vs & 0x100) >> 6) |
664 ((vd & 0x100) >> 7) | 635 ((vd & 0x100) >> 7) |
665 ((vt & 0x100) >> 8); 636 ((vt & 0x100) >> 8);
666 reg.crt[0x08] = 0x00; 637 reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4);
667 reg.crt[0x09] = 0x40 | ((vbs & 0x200) >> 4);
668 reg.crt[0x0a] = 0x00;
669 reg.crt[0x0b] = 0x00;
670 reg.crt[0x0c] = 0x00;
671 reg.crt[0x0d] = 0x00;
672 reg.crt[0x0e] = 0x00;
673 reg.crt[0x0f] = 0x00;
674 reg.crt[0x10] = vs; 638 reg.crt[0x10] = vs;
675 reg.crt[0x11] = (ve & 0x0f) | 0x20; 639 reg.crt[0x11] = (ve & 0x0f) | 0x20;
676 reg.crt[0x12] = vd; 640 reg.crt[0x12] = vd;
677 reg.crt[0x13] = wd; 641 reg.crt[0x13] = wd;
678 reg.crt[0x14] = 0x00;
679 reg.crt[0x15] = vbs; 642 reg.crt[0x15] = vbs;
680 reg.crt[0x16] = vbe + 1; 643 reg.crt[0x16] = vbe + 1;
681 reg.crt[0x17] = 0xc3; 644 reg.crt[0x17] = 0xc3;
@@ -706,34 +669,15 @@ static int tdfxfb_set_par(struct fb_info *info)
706 reg.cursc1 = 0xffffff; 669 reg.cursc1 = 0xffffff;
707 670
708 reg.stride = info->var.xres * cpp; 671 reg.stride = info->var.xres * cpp;
709 reg.startaddr = par->baseline * reg.stride; 672 reg.startaddr = info->var.yoffset * reg.stride
710 reg.srcbase = reg.startaddr; 673 + info->var.xoffset * cpp;
711 reg.dstbase = reg.startaddr;
712
713 /* PLL settings */
714 freq = PICOS2KHZ(info->var.pixclock);
715 674
716 reg.dacmode &= ~DACMODE_2X;
717 reg.vidcfg &= ~VIDCFG_2X;
718 if (freq > par->max_pixclock / 2) {
719 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
720 reg.dacmode |= DACMODE_2X;
721 reg.vidcfg |= VIDCFG_2X;
722 }
723 reg.vidpll = do_calc_pll(freq, &fout); 675 reg.vidpll = do_calc_pll(freq, &fout);
724#if 0 676#if 0
725 reg.mempll = do_calc_pll(..., &fout); 677 reg.mempll = do_calc_pll(..., &fout);
726 reg.gfxpll = do_calc_pll(..., &fout); 678 reg.gfxpll = do_calc_pll(..., &fout);
727#endif 679#endif
728 680
729 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
730 reg.screensize = info->var.xres | (info->var.yres << 13);
731 reg.vidcfg |= VIDCFG_HALF_MODE;
732 reg.crt[0x09] |= 0x80;
733 } else {
734 reg.screensize = info->var.xres | (info->var.yres << 12);
735 reg.vidcfg &= ~VIDCFG_HALF_MODE;
736 }
737 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) 681 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
738 reg.vidcfg |= VIDCFG_INTERLACE; 682 reg.vidcfg |= VIDCFG_INTERLACE;
739 reg.miscinit0 = tdfx_inl(par, MISCINIT0); 683 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
@@ -758,8 +702,7 @@ static int tdfxfb_set_par(struct fb_info *info)
758 do_write_regs(info, &reg); 702 do_write_regs(info, &reg);
759 703
760 /* Now change fb_fix_screeninfo according to changes in par */ 704 /* Now change fb_fix_screeninfo according to changes in par */
761 info->fix.line_length = 705 info->fix.line_length = reg.stride;
762 info->var.xres * ((info->var.bits_per_pixel + 7) >> 3);
763 info->fix.visual = (info->var.bits_per_pixel == 8) 706 info->fix.visual = (info->var.bits_per_pixel == 8)
764 ? FB_VISUAL_PSEUDOCOLOR 707 ? FB_VISUAL_PSEUDOCOLOR
765 : FB_VISUAL_TRUECOLOR; 708 : FB_VISUAL_TRUECOLOR;
@@ -821,35 +764,28 @@ static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
821static int tdfxfb_blank(int blank, struct fb_info *info) 764static int tdfxfb_blank(int blank, struct fb_info *info)
822{ 765{
823 struct tdfx_par *par = info->par; 766 struct tdfx_par *par = info->par;
824 u32 dacmode, state = 0, vgablank = 0; 767 int vgablank = 1;
768 u32 dacmode = tdfx_inl(par, DACMODE);
825 769
826 dacmode = tdfx_inl(par, DACMODE); 770 dacmode &= ~(BIT(1) | BIT(3));
827 771
828 switch (blank) { 772 switch (blank) {
829 case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */ 773 case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
830 state = 0;
831 vgablank = 0; 774 vgablank = 0;
832 break; 775 break;
833 case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */ 776 case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
834 state = 0;
835 vgablank = 1;
836 break; 777 break;
837 case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */ 778 case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
838 state = BIT(3); 779 dacmode |= BIT(3);
839 vgablank = 1;
840 break; 780 break;
841 case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */ 781 case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
842 state = BIT(1); 782 dacmode |= BIT(1);
843 vgablank = 1;
844 break; 783 break;
845 case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */ 784 case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
846 state = BIT(1) | BIT(3); 785 dacmode |= BIT(1) | BIT(3);
847 vgablank = 1;
848 break; 786 break;
849 } 787 }
850 788
851 dacmode &= ~(BIT(1) | BIT(3));
852 dacmode |= state;
853 banshee_make_room(par, 1); 789 banshee_make_room(par, 1);
854 tdfx_outl(par, DACMODE, dacmode); 790 tdfx_outl(par, DACMODE, dacmode);
855 if (vgablank) 791 if (vgablank)
@@ -866,14 +802,13 @@ static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
866 struct fb_info *info) 802 struct fb_info *info)
867{ 803{
868 struct tdfx_par *par = info->par; 804 struct tdfx_par *par = info->par;
869 u32 addr; 805 u32 addr = var->yoffset * info->fix.line_length;
870 806
871 if (nopan || var->xoffset || (var->yoffset > var->yres_virtual)) 807 if (nopan || var->xoffset || (var->yoffset > var->yres_virtual))
872 return -EINVAL; 808 return -EINVAL;
873 if ((var->yoffset + var->yres > var->yres_virtual && nowrap)) 809 if ((var->yoffset + var->yres > var->yres_virtual && nowrap))
874 return -EINVAL; 810 return -EINVAL;
875 811
876 addr = var->yoffset * info->fix.line_length;
877 banshee_make_room(par, 1); 812 banshee_make_room(par, 1);
878 tdfx_outl(par, VIDDESKSTART, addr); 813 tdfx_outl(par, VIDDESKSTART, addr);
879 814
@@ -962,7 +897,6 @@ static void tdfxfb_copyarea(struct fb_info *info,
962 dx = 0; 897 dx = 0;
963 } 898 }
964 899
965
966 if (area->sx <= area->dx) { 900 if (area->sx <= area->dx) {
967 //-X 901 //-X
968 blitcmd |= BIT(14); 902 blitcmd |= BIT(14);
@@ -1061,8 +995,7 @@ static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
1061 995
1062 /* Send the leftovers now */ 996 /* Send the leftovers now */
1063 banshee_make_room(par, 3); 997 banshee_make_room(par, 3);
1064 i = size % 4; 998 switch (size % 4) {
1065 switch (i) {
1066 case 0: 999 case 0:
1067 break; 1000 break;
1068 case 1: 1001 case 1: