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authorTejun Heo <htejun@gmail.com>2007-04-17 10:44:08 -0400
committerJeff Garzik <jeff@garzik.org>2007-04-28 14:16:06 -0400
commit4447d35156169cf136e829eb6b5cac2d6370f2d9 (patch)
tree20be4c582ea4ce1cce1b0f8dbea949a410a72e3c /drivers
parent9a829ccfc833269bdb85751f5048288ab93678ac (diff)
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv, sata_sx4, sata_vsc and sata_inic162x to new init model. Now that host and ap are available during intialization, functions are converted to take either host or ap instead of low level parameters which were inevitable for functions shared between init and other paths. This simplifies code quite a bit. * init_one()'s now follow more consistent init order * ahci_setup_port() and ahci_host_init() collapsed into ahci_init_one() for init order consistency * sata_vsc uses port_info instead of setting fields manually * in sata_svw, k2_board_info converted to port_info (info is now in port flags). port number is honored now. Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ata/ahci.c327
-rw-r--r--drivers/ata/sata_inic162x.c78
-rw-r--r--drivers/ata/sata_mv.c105
-rw-r--r--drivers/ata/sata_qstor.c62
-rw-r--r--drivers/ata/sata_sil.c89
-rw-r--r--drivers/ata/sata_sil24.c111
-rw-r--r--drivers/ata/sata_svw.c107
-rw-r--r--drivers/ata/sata_sx4.c150
-rw-r--r--drivers/ata/sata_vsc.c72
9 files changed, 444 insertions, 657 deletions
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index fe4f0fe36bfb..7c61bc7ebd71 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -211,7 +211,6 @@ static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
211static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 211static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
212static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 212static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
213static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); 213static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
214static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
215static void ahci_irq_clear(struct ata_port *ap); 214static void ahci_irq_clear(struct ata_port *ap);
216static int ahci_port_start(struct ata_port *ap); 215static int ahci_port_start(struct ata_port *ap);
217static void ahci_port_stop(struct ata_port *ap); 216static void ahci_port_stop(struct ata_port *ap);
@@ -265,7 +264,6 @@ static const struct ata_port_operations ahci_ops = {
265 .qc_prep = ahci_qc_prep, 264 .qc_prep = ahci_qc_prep,
266 .qc_issue = ahci_qc_issue, 265 .qc_issue = ahci_qc_issue,
267 266
268 .irq_handler = ahci_interrupt,
269 .irq_clear = ahci_irq_clear, 267 .irq_clear = ahci_irq_clear,
270 .irq_on = ata_dummy_irq_on, 268 .irq_on = ata_dummy_irq_on,
271 .irq_ack = ata_dummy_irq_ack, 269 .irq_ack = ata_dummy_irq_ack,
@@ -300,7 +298,6 @@ static const struct ata_port_operations ahci_vt8251_ops = {
300 .qc_prep = ahci_qc_prep, 298 .qc_prep = ahci_qc_prep,
301 .qc_issue = ahci_qc_issue, 299 .qc_issue = ahci_qc_issue,
302 300
303 .irq_handler = ahci_interrupt,
304 .irq_clear = ahci_irq_clear, 301 .irq_clear = ahci_irq_clear,
305 .irq_on = ata_dummy_irq_on, 302 .irq_on = ata_dummy_irq_on,
306 .irq_ack = ata_dummy_irq_ack, 303 .irq_ack = ata_dummy_irq_ack,
@@ -326,7 +323,6 @@ static const struct ata_port_operations ahci_vt8251_ops = {
326static const struct ata_port_info ahci_port_info[] = { 323static const struct ata_port_info ahci_port_info[] = {
327 /* board_ahci */ 324 /* board_ahci */
328 { 325 {
329 .sht = &ahci_sht,
330 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 326 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
331 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 327 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
332 ATA_FLAG_SKIP_D2H_BSY, 328 ATA_FLAG_SKIP_D2H_BSY,
@@ -336,7 +332,6 @@ static const struct ata_port_info ahci_port_info[] = {
336 }, 332 },
337 /* board_ahci_pi */ 333 /* board_ahci_pi */
338 { 334 {
339 .sht = &ahci_sht,
340 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 335 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
341 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 336 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
342 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI, 337 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
@@ -346,7 +341,6 @@ static const struct ata_port_info ahci_port_info[] = {
346 }, 341 },
347 /* board_ahci_vt8251 */ 342 /* board_ahci_vt8251 */
348 { 343 {
349 .sht = &ahci_sht,
350 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 344 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
351 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 345 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
352 ATA_FLAG_SKIP_D2H_BSY | 346 ATA_FLAG_SKIP_D2H_BSY |
@@ -357,7 +351,6 @@ static const struct ata_port_info ahci_port_info[] = {
357 }, 351 },
358 /* board_ahci_ign_iferr */ 352 /* board_ahci_ign_iferr */
359 { 353 {
360 .sht = &ahci_sht,
361 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 354 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
362 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | 355 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
363 ATA_FLAG_SKIP_D2H_BSY | 356 ATA_FLAG_SKIP_D2H_BSY |
@@ -473,15 +466,18 @@ static inline int ahci_nr_ports(u32 cap)
473 return (cap & 0x1f) + 1; 466 return (cap & 0x1f) + 1;
474} 467}
475 468
476static inline void __iomem *ahci_port_base(void __iomem *base, 469static inline void __iomem *ahci_port_base(struct ata_port *ap)
477 unsigned int port)
478{ 470{
479 return base + 0x100 + (port * 0x80); 471 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
472
473 return mmio + 0x100 + (ap->port_no * 0x80);
480} 474}
481 475
482/** 476/**
483 * ahci_save_initial_config - Save and fixup initial config values 477 * ahci_save_initial_config - Save and fixup initial config values
484 * @probe_ent: probe_ent of target device 478 * @pdev: target PCI device
479 * @pi: associated ATA port info
480 * @hpriv: host private area to store config values
485 * 481 *
486 * Some registers containing configuration info might be setup by 482 * Some registers containing configuration info might be setup by
487 * BIOS and might be cleared on reset. This function saves the 483 * BIOS and might be cleared on reset. This function saves the
@@ -493,10 +489,11 @@ static inline void __iomem *ahci_port_base(void __iomem *base,
493 * LOCKING: 489 * LOCKING:
494 * None. 490 * None.
495 */ 491 */
496static void ahci_save_initial_config(struct ata_probe_ent *probe_ent) 492static void ahci_save_initial_config(struct pci_dev *pdev,
493 const struct ata_port_info *pi,
494 struct ahci_host_priv *hpriv)
497{ 495{
498 struct ahci_host_priv *hpriv = probe_ent->private_data; 496 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
499 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
500 u32 cap, port_map; 497 u32 cap, port_map;
501 int i; 498 int i;
502 499
@@ -509,7 +506,7 @@ static void ahci_save_initial_config(struct ata_probe_ent *probe_ent)
509 /* fixup zero port_map */ 506 /* fixup zero port_map */
510 if (!port_map) { 507 if (!port_map) {
511 port_map = (1 << ahci_nr_ports(hpriv->cap)) - 1; 508 port_map = (1 << ahci_nr_ports(hpriv->cap)) - 1;
512 dev_printk(KERN_WARNING, probe_ent->dev, 509 dev_printk(KERN_WARNING, &pdev->dev,
513 "PORTS_IMPL is zero, forcing 0x%x\n", port_map); 510 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
514 511
515 /* write the fixed up value to the PI register */ 512 /* write the fixed up value to the PI register */
@@ -517,7 +514,7 @@ static void ahci_save_initial_config(struct ata_probe_ent *probe_ent)
517 } 514 }
518 515
519 /* cross check port_map and cap.n_ports */ 516 /* cross check port_map and cap.n_ports */
520 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) { 517 if (pi->flags & AHCI_FLAG_HONOR_PI) {
521 u32 tmp_port_map = port_map; 518 u32 tmp_port_map = port_map;
522 int n_ports = ahci_nr_ports(cap); 519 int n_ports = ahci_nr_ports(cap);
523 520
@@ -532,7 +529,7 @@ static void ahci_save_initial_config(struct ata_probe_ent *probe_ent)
532 * port_map is used to determine number of ports. 529 * port_map is used to determine number of ports.
533 */ 530 */
534 if (n_ports || tmp_port_map) 531 if (n_ports || tmp_port_map)
535 dev_printk(KERN_WARNING, probe_ent->dev, 532 dev_printk(KERN_WARNING, &pdev->dev,
536 "nr_ports (%u) and implemented port map " 533 "nr_ports (%u) and implemented port map "
537 "(0x%x) don't match\n", 534 "(0x%x) don't match\n",
538 ahci_nr_ports(cap), port_map); 535 ahci_nr_ports(cap), port_map);
@@ -548,17 +545,18 @@ static void ahci_save_initial_config(struct ata_probe_ent *probe_ent)
548 545
549/** 546/**
550 * ahci_restore_initial_config - Restore initial config 547 * ahci_restore_initial_config - Restore initial config
551 * @mmio: MMIO base for the host 548 * @host: target ATA host
552 * @hpriv: host private data
553 * 549 *
554 * Restore initial config stored by ahci_save_initial_config(). 550 * Restore initial config stored by ahci_save_initial_config().
555 * 551 *
556 * LOCKING: 552 * LOCKING:
557 * None. 553 * None.
558 */ 554 */
559static void ahci_restore_initial_config(void __iomem *mmio, 555static void ahci_restore_initial_config(struct ata_host *host)
560 struct ahci_host_priv *hpriv)
561{ 556{
557 struct ahci_host_priv *hpriv = host->private_data;
558 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
559
562 writel(hpriv->saved_cap, mmio + HOST_CAP); 560 writel(hpriv->saved_cap, mmio + HOST_CAP);
563 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL); 561 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
564 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ 562 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
@@ -598,8 +596,9 @@ static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
598 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); 596 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
599} 597}
600 598
601static void ahci_start_engine(void __iomem *port_mmio) 599static void ahci_start_engine(struct ata_port *ap)
602{ 600{
601 void __iomem *port_mmio = ahci_port_base(ap);
603 u32 tmp; 602 u32 tmp;
604 603
605 /* start DMA */ 604 /* start DMA */
@@ -609,8 +608,9 @@ static void ahci_start_engine(void __iomem *port_mmio)
609 readl(port_mmio + PORT_CMD); /* flush */ 608 readl(port_mmio + PORT_CMD); /* flush */
610} 609}
611 610
612static int ahci_stop_engine(void __iomem *port_mmio) 611static int ahci_stop_engine(struct ata_port *ap)
613{ 612{
613 void __iomem *port_mmio = ahci_port_base(ap);
614 u32 tmp; 614 u32 tmp;
615 615
616 tmp = readl(port_mmio + PORT_CMD); 616 tmp = readl(port_mmio + PORT_CMD);
@@ -632,19 +632,23 @@ static int ahci_stop_engine(void __iomem *port_mmio)
632 return 0; 632 return 0;
633} 633}
634 634
635static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap, 635static void ahci_start_fis_rx(struct ata_port *ap)
636 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
637{ 636{
637 void __iomem *port_mmio = ahci_port_base(ap);
638 struct ahci_host_priv *hpriv = ap->host->private_data;
639 struct ahci_port_priv *pp = ap->private_data;
638 u32 tmp; 640 u32 tmp;
639 641
640 /* set FIS registers */ 642 /* set FIS registers */
641 if (cap & HOST_CAP_64) 643 if (hpriv->cap & HOST_CAP_64)
642 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); 644 writel((pp->cmd_slot_dma >> 16) >> 16,
643 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); 645 port_mmio + PORT_LST_ADDR_HI);
646 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
644 647
645 if (cap & HOST_CAP_64) 648 if (hpriv->cap & HOST_CAP_64)
646 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); 649 writel((pp->rx_fis_dma >> 16) >> 16,
647 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); 650 port_mmio + PORT_FIS_ADDR_HI);
651 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
648 652
649 /* enable FIS reception */ 653 /* enable FIS reception */
650 tmp = readl(port_mmio + PORT_CMD); 654 tmp = readl(port_mmio + PORT_CMD);
@@ -655,8 +659,9 @@ static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
655 readl(port_mmio + PORT_CMD); 659 readl(port_mmio + PORT_CMD);
656} 660}
657 661
658static int ahci_stop_fis_rx(void __iomem *port_mmio) 662static int ahci_stop_fis_rx(struct ata_port *ap)
659{ 663{
664 void __iomem *port_mmio = ahci_port_base(ap);
660 u32 tmp; 665 u32 tmp;
661 666
662 /* disable FIS reception */ 667 /* disable FIS reception */
@@ -673,14 +678,16 @@ static int ahci_stop_fis_rx(void __iomem *port_mmio)
673 return 0; 678 return 0;
674} 679}
675 680
676static void ahci_power_up(void __iomem *port_mmio, u32 cap) 681static void ahci_power_up(struct ata_port *ap)
677{ 682{
683 struct ahci_host_priv *hpriv = ap->host->private_data;
684 void __iomem *port_mmio = ahci_port_base(ap);
678 u32 cmd; 685 u32 cmd;
679 686
680 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; 687 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
681 688
682 /* spin up device */ 689 /* spin up device */
683 if (cap & HOST_CAP_SSS) { 690 if (hpriv->cap & HOST_CAP_SSS) {
684 cmd |= PORT_CMD_SPIN_UP; 691 cmd |= PORT_CMD_SPIN_UP;
685 writel(cmd, port_mmio + PORT_CMD); 692 writel(cmd, port_mmio + PORT_CMD);
686 } 693 }
@@ -690,11 +697,13 @@ static void ahci_power_up(void __iomem *port_mmio, u32 cap)
690} 697}
691 698
692#ifdef CONFIG_PM 699#ifdef CONFIG_PM
693static void ahci_power_down(void __iomem *port_mmio, u32 cap) 700static void ahci_power_down(struct ata_port *ap)
694{ 701{
702 struct ahci_host_priv *hpriv = ap->host->private_data;
703 void __iomem *port_mmio = ahci_port_base(ap);
695 u32 cmd, scontrol; 704 u32 cmd, scontrol;
696 705
697 if (!(cap & HOST_CAP_SSS)) 706 if (!(hpriv->cap & HOST_CAP_SSS))
698 return; 707 return;
699 708
700 /* put device into listen mode, first set PxSCTL.DET to 0 */ 709 /* put device into listen mode, first set PxSCTL.DET to 0 */
@@ -709,29 +718,28 @@ static void ahci_power_down(void __iomem *port_mmio, u32 cap)
709} 718}
710#endif 719#endif
711 720
712static void ahci_init_port(void __iomem *port_mmio, u32 cap, 721static void ahci_init_port(struct ata_port *ap)
713 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
714{ 722{
715 /* enable FIS reception */ 723 /* enable FIS reception */
716 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma); 724 ahci_start_fis_rx(ap);
717 725
718 /* enable DMA */ 726 /* enable DMA */
719 ahci_start_engine(port_mmio); 727 ahci_start_engine(ap);
720} 728}
721 729
722static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg) 730static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
723{ 731{
724 int rc; 732 int rc;
725 733
726 /* disable DMA */ 734 /* disable DMA */
727 rc = ahci_stop_engine(port_mmio); 735 rc = ahci_stop_engine(ap);
728 if (rc) { 736 if (rc) {
729 *emsg = "failed to stop engine"; 737 *emsg = "failed to stop engine";
730 return rc; 738 return rc;
731 } 739 }
732 740
733 /* disable FIS reception */ 741 /* disable FIS reception */
734 rc = ahci_stop_fis_rx(port_mmio); 742 rc = ahci_stop_fis_rx(ap);
735 if (rc) { 743 if (rc) {
736 *emsg = "failed stop FIS RX"; 744 *emsg = "failed stop FIS RX";
737 return rc; 745 return rc;
@@ -740,9 +748,10 @@ static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
740 return 0; 748 return 0;
741} 749}
742 750
743static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev, 751static int ahci_reset_controller(struct ata_host *host)
744 struct ahci_host_priv *hpriv)
745{ 752{
753 struct pci_dev *pdev = to_pci_dev(host->dev);
754 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
746 u32 tmp; 755 u32 tmp;
747 756
748 /* global controller reset */ 757 /* global controller reset */
@@ -759,7 +768,7 @@ static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev,
759 768
760 tmp = readl(mmio + HOST_CTL); 769 tmp = readl(mmio + HOST_CTL);
761 if (tmp & HOST_RESET) { 770 if (tmp & HOST_RESET) {
762 dev_printk(KERN_ERR, &pdev->dev, 771 dev_printk(KERN_ERR, host->dev,
763 "controller reset failed (0x%x)\n", tmp); 772 "controller reset failed (0x%x)\n", tmp);
764 return -EIO; 773 return -EIO;
765 } 774 }
@@ -769,7 +778,7 @@ static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev,
769 (void) readl(mmio + HOST_CTL); /* flush */ 778 (void) readl(mmio + HOST_CTL); /* flush */
770 779
771 /* some registers might be cleared on reset. restore initial values */ 780 /* some registers might be cleared on reset. restore initial values */
772 ahci_restore_initial_config(mmio, hpriv); 781 ahci_restore_initial_config(host);
773 782
774 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 783 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
775 u16 tmp16; 784 u16 tmp16;
@@ -783,23 +792,23 @@ static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev,
783 return 0; 792 return 0;
784} 793}
785 794
786static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev, 795static void ahci_init_controller(struct ata_host *host)
787 int n_ports, unsigned int port_flags,
788 struct ahci_host_priv *hpriv)
789{ 796{
797 struct pci_dev *pdev = to_pci_dev(host->dev);
798 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
790 int i, rc; 799 int i, rc;
791 u32 tmp; 800 u32 tmp;
792 801
793 for (i = 0; i < n_ports; i++) { 802 for (i = 0; i < host->n_ports; i++) {
794 void __iomem *port_mmio = ahci_port_base(mmio, i); 803 struct ata_port *ap = host->ports[i];
804 void __iomem *port_mmio = ahci_port_base(ap);
795 const char *emsg = NULL; 805 const char *emsg = NULL;
796 806
797 if ((port_flags & AHCI_FLAG_HONOR_PI) && 807 if (ata_port_is_dummy(ap))
798 !(hpriv->port_map & (1 << i)))
799 continue; 808 continue;
800 809
801 /* make sure port is not active */ 810 /* make sure port is not active */
802 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); 811 rc = ahci_deinit_port(ap, &emsg);
803 if (rc) 812 if (rc)
804 dev_printk(KERN_WARNING, &pdev->dev, 813 dev_printk(KERN_WARNING, &pdev->dev,
805 "%s (%d)\n", emsg, rc); 814 "%s (%d)\n", emsg, rc);
@@ -827,7 +836,7 @@ static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
827 836
828static unsigned int ahci_dev_classify(struct ata_port *ap) 837static unsigned int ahci_dev_classify(struct ata_port *ap)
829{ 838{
830 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 839 void __iomem *port_mmio = ahci_port_base(ap);
831 struct ata_taskfile tf; 840 struct ata_taskfile tf;
832 u32 tmp; 841 u32 tmp;
833 842
@@ -877,8 +886,7 @@ static int ahci_clo(struct ata_port *ap)
877static int ahci_softreset(struct ata_port *ap, unsigned int *class) 886static int ahci_softreset(struct ata_port *ap, unsigned int *class)
878{ 887{
879 struct ahci_port_priv *pp = ap->private_data; 888 struct ahci_port_priv *pp = ap->private_data;
880 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 889 void __iomem *port_mmio = ahci_port_base(ap);
881 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
882 const u32 cmd_fis_len = 5; /* five dwords */ 890 const u32 cmd_fis_len = 5; /* five dwords */
883 const char *reason = NULL; 891 const char *reason = NULL;
884 struct ata_taskfile tf; 892 struct ata_taskfile tf;
@@ -895,7 +903,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
895 } 903 }
896 904
897 /* prepare for SRST (AHCI-1.1 10.4.1) */ 905 /* prepare for SRST (AHCI-1.1 10.4.1) */
898 rc = ahci_stop_engine(port_mmio); 906 rc = ahci_stop_engine(ap);
899 if (rc) { 907 if (rc) {
900 reason = "failed to stop engine"; 908 reason = "failed to stop engine";
901 goto fail_restart; 909 goto fail_restart;
@@ -915,7 +923,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
915 } 923 }
916 924
917 /* restart engine */ 925 /* restart engine */
918 ahci_start_engine(port_mmio); 926 ahci_start_engine(ap);
919 927
920 ata_tf_init(ap->device, &tf); 928 ata_tf_init(ap->device, &tf);
921 fis = pp->cmd_tbl; 929 fis = pp->cmd_tbl;
@@ -974,7 +982,7 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
974 return 0; 982 return 0;
975 983
976 fail_restart: 984 fail_restart:
977 ahci_start_engine(port_mmio); 985 ahci_start_engine(ap);
978 fail: 986 fail:
979 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); 987 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
980 return rc; 988 return rc;
@@ -985,13 +993,11 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
985 struct ahci_port_priv *pp = ap->private_data; 993 struct ahci_port_priv *pp = ap->private_data;
986 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; 994 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
987 struct ata_taskfile tf; 995 struct ata_taskfile tf;
988 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
989 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
990 int rc; 996 int rc;
991 997
992 DPRINTK("ENTER\n"); 998 DPRINTK("ENTER\n");
993 999
994 ahci_stop_engine(port_mmio); 1000 ahci_stop_engine(ap);
995 1001
996 /* clear D2H reception area to properly wait for D2H FIS */ 1002 /* clear D2H reception area to properly wait for D2H FIS */
997 ata_tf_init(ap->device, &tf); 1003 ata_tf_init(ap->device, &tf);
@@ -1000,7 +1006,7 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
1000 1006
1001 rc = sata_std_hardreset(ap, class); 1007 rc = sata_std_hardreset(ap, class);
1002 1008
1003 ahci_start_engine(port_mmio); 1009 ahci_start_engine(ap);
1004 1010
1005 if (rc == 0 && ata_port_online(ap)) 1011 if (rc == 0 && ata_port_online(ap))
1006 *class = ahci_dev_classify(ap); 1012 *class = ahci_dev_classify(ap);
@@ -1013,20 +1019,18 @@ static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
1013 1019
1014static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class) 1020static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
1015{ 1021{
1016 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1017 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1018 int rc; 1022 int rc;
1019 1023
1020 DPRINTK("ENTER\n"); 1024 DPRINTK("ENTER\n");
1021 1025
1022 ahci_stop_engine(port_mmio); 1026 ahci_stop_engine(ap);
1023 1027
1024 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context)); 1028 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
1025 1029
1026 /* vt8251 needs SError cleared for the port to operate */ 1030 /* vt8251 needs SError cleared for the port to operate */
1027 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR)); 1031 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
1028 1032
1029 ahci_start_engine(port_mmio); 1033 ahci_start_engine(ap);
1030 1034
1031 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); 1035 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1032 1036
@@ -1038,7 +1042,7 @@ static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
1038 1042
1039static void ahci_postreset(struct ata_port *ap, unsigned int *class) 1043static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1040{ 1044{
1041 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 1045 void __iomem *port_mmio = ahci_port_base(ap);
1042 u32 new_tmp, tmp; 1046 u32 new_tmp, tmp;
1043 1047
1044 ata_std_postreset(ap, class); 1048 ata_std_postreset(ap, class);
@@ -1206,8 +1210,7 @@ static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1206 1210
1207static void ahci_host_intr(struct ata_port *ap) 1211static void ahci_host_intr(struct ata_port *ap)
1208{ 1212{
1209 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1213 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1210 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1211 struct ata_eh_info *ehi = &ap->eh_info; 1214 struct ata_eh_info *ehi = &ap->eh_info;
1212 struct ahci_port_priv *pp = ap->private_data; 1215 struct ahci_port_priv *pp = ap->private_data;
1213 u32 status, qc_active; 1216 u32 status, qc_active;
@@ -1358,7 +1361,7 @@ static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1358static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) 1361static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1359{ 1362{
1360 struct ata_port *ap = qc->ap; 1363 struct ata_port *ap = qc->ap;
1361 void __iomem *port_mmio = ap->ioaddr.cmd_addr; 1364 void __iomem *port_mmio = ahci_port_base(ap);
1362 1365
1363 if (qc->tf.protocol == ATA_PROT_NCQ) 1366 if (qc->tf.protocol == ATA_PROT_NCQ)
1364 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); 1367 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
@@ -1370,8 +1373,7 @@ static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1370 1373
1371static void ahci_freeze(struct ata_port *ap) 1374static void ahci_freeze(struct ata_port *ap)
1372{ 1375{
1373 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1376 void __iomem *port_mmio = ahci_port_base(ap);
1374 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1375 1377
1376 /* turn IRQ off */ 1378 /* turn IRQ off */
1377 writel(0, port_mmio + PORT_IRQ_MASK); 1379 writel(0, port_mmio + PORT_IRQ_MASK);
@@ -1380,7 +1382,7 @@ static void ahci_freeze(struct ata_port *ap)
1380static void ahci_thaw(struct ata_port *ap) 1382static void ahci_thaw(struct ata_port *ap)
1381{ 1383{
1382 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR]; 1384 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1383 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); 1385 void __iomem *port_mmio = ahci_port_base(ap);
1384 u32 tmp; 1386 u32 tmp;
1385 1387
1386 /* clear IRQ */ 1388 /* clear IRQ */
@@ -1394,13 +1396,10 @@ static void ahci_thaw(struct ata_port *ap)
1394 1396
1395static void ahci_error_handler(struct ata_port *ap) 1397static void ahci_error_handler(struct ata_port *ap)
1396{ 1398{
1397 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1398 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1399
1400 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1399 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1401 /* restart engine */ 1400 /* restart engine */
1402 ahci_stop_engine(port_mmio); 1401 ahci_stop_engine(ap);
1403 ahci_start_engine(port_mmio); 1402 ahci_start_engine(ap);
1404 } 1403 }
1405 1404
1406 /* perform recovery */ 1405 /* perform recovery */
@@ -1410,13 +1409,10 @@ static void ahci_error_handler(struct ata_port *ap)
1410 1409
1411static void ahci_vt8251_error_handler(struct ata_port *ap) 1410static void ahci_vt8251_error_handler(struct ata_port *ap)
1412{ 1411{
1413 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1414 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1415
1416 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 1412 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1417 /* restart engine */ 1413 /* restart engine */
1418 ahci_stop_engine(port_mmio); 1414 ahci_stop_engine(ap);
1419 ahci_start_engine(port_mmio); 1415 ahci_start_engine(ap);
1420 } 1416 }
1421 1417
1422 /* perform recovery */ 1418 /* perform recovery */
@@ -1427,33 +1423,26 @@ static void ahci_vt8251_error_handler(struct ata_port *ap)
1427static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) 1423static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1428{ 1424{
1429 struct ata_port *ap = qc->ap; 1425 struct ata_port *ap = qc->ap;
1430 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1431 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1432 1426
1433 if (qc->flags & ATA_QCFLAG_FAILED) { 1427 if (qc->flags & ATA_QCFLAG_FAILED) {
1434 /* make DMA engine forget about the failed command */ 1428 /* make DMA engine forget about the failed command */
1435 ahci_stop_engine(port_mmio); 1429 ahci_stop_engine(ap);
1436 ahci_start_engine(port_mmio); 1430 ahci_start_engine(ap);
1437 } 1431 }
1438} 1432}
1439 1433
1440#ifdef CONFIG_PM 1434#ifdef CONFIG_PM
1441static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) 1435static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1442{ 1436{
1443 struct ahci_host_priv *hpriv = ap->host->private_data;
1444 struct ahci_port_priv *pp = ap->private_data;
1445 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1446 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1447 const char *emsg = NULL; 1437 const char *emsg = NULL;
1448 int rc; 1438 int rc;
1449 1439
1450 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); 1440 rc = ahci_deinit_port(ap, &emsg);
1451 if (rc == 0) 1441 if (rc == 0)
1452 ahci_power_down(port_mmio, hpriv->cap); 1442 ahci_power_down(ap);
1453 else { 1443 else {
1454 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); 1444 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1455 ahci_init_port(port_mmio, hpriv->cap, 1445 ahci_init_port(ap);
1456 pp->cmd_slot_dma, pp->rx_fis_dma);
1457 } 1446 }
1458 1447
1459 return rc; 1448 return rc;
@@ -1461,13 +1450,8 @@ static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1461 1450
1462static int ahci_port_resume(struct ata_port *ap) 1451static int ahci_port_resume(struct ata_port *ap)
1463{ 1452{
1464 struct ahci_port_priv *pp = ap->private_data; 1453 ahci_power_up(ap);
1465 struct ahci_host_priv *hpriv = ap->host->private_data; 1454 ahci_init_port(ap);
1466 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1467 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1468
1469 ahci_power_up(port_mmio, hpriv->cap);
1470 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1471 1455
1472 return 0; 1456 return 0;
1473} 1457}
@@ -1495,8 +1479,6 @@ static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1495static int ahci_pci_device_resume(struct pci_dev *pdev) 1479static int ahci_pci_device_resume(struct pci_dev *pdev)
1496{ 1480{
1497 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1481 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1498 struct ahci_host_priv *hpriv = host->private_data;
1499 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1500 int rc; 1482 int rc;
1501 1483
1502 rc = ata_pci_device_do_resume(pdev); 1484 rc = ata_pci_device_do_resume(pdev);
@@ -1504,12 +1486,11 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
1504 return rc; 1486 return rc;
1505 1487
1506 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 1488 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1507 rc = ahci_reset_controller(mmio, pdev, hpriv); 1489 rc = ahci_reset_controller(host);
1508 if (rc) 1490 if (rc)
1509 return rc; 1491 return rc;
1510 1492
1511 ahci_init_controller(mmio, pdev, host->n_ports, 1493 ahci_init_controller(host);
1512 host->ports[0]->flags, hpriv);
1513 } 1494 }
1514 1495
1515 ata_host_resume(host); 1496 ata_host_resume(host);
@@ -1521,10 +1502,7 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
1521static int ahci_port_start(struct ata_port *ap) 1502static int ahci_port_start(struct ata_port *ap)
1522{ 1503{
1523 struct device *dev = ap->host->dev; 1504 struct device *dev = ap->host->dev;
1524 struct ahci_host_priv *hpriv = ap->host->private_data;
1525 struct ahci_port_priv *pp; 1505 struct ahci_port_priv *pp;
1526 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1527 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1528 void *mem; 1506 void *mem;
1529 dma_addr_t mem_dma; 1507 dma_addr_t mem_dma;
1530 int rc; 1508 int rc;
@@ -1572,60 +1550,29 @@ static int ahci_port_start(struct ata_port *ap)
1572 ap->private_data = pp; 1550 ap->private_data = pp;
1573 1551
1574 /* power up port */ 1552 /* power up port */
1575 ahci_power_up(port_mmio, hpriv->cap); 1553 ahci_power_up(ap);
1576 1554
1577 /* initialize port */ 1555 /* initialize port */
1578 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); 1556 ahci_init_port(ap);
1579 1557
1580 return 0; 1558 return 0;
1581} 1559}
1582 1560
1583static void ahci_port_stop(struct ata_port *ap) 1561static void ahci_port_stop(struct ata_port *ap)
1584{ 1562{
1585 struct ahci_host_priv *hpriv = ap->host->private_data;
1586 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1587 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1588 const char *emsg = NULL; 1563 const char *emsg = NULL;
1589 int rc; 1564 int rc;
1590 1565
1591 /* de-initialize port */ 1566 /* de-initialize port */
1592 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); 1567 rc = ahci_deinit_port(ap, &emsg);
1593 if (rc) 1568 if (rc)
1594 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); 1569 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1595} 1570}
1596 1571
1597static void ahci_setup_port(struct ata_ioports *port, void __iomem *base, 1572static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1598 unsigned int port_idx)
1599{ 1573{
1600 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1601 base = ahci_port_base(base, port_idx);
1602 VPRINTK("base now==0x%lx\n", base);
1603
1604 port->cmd_addr = base;
1605 port->scr_addr = base + PORT_SCR;
1606
1607 VPRINTK("EXIT\n");
1608}
1609
1610static int ahci_host_init(struct ata_probe_ent *probe_ent)
1611{
1612 struct ahci_host_priv *hpriv = probe_ent->private_data;
1613 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1614 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
1615 unsigned int i, using_dac;
1616 int rc; 1574 int rc;
1617 1575
1618 rc = ahci_reset_controller(mmio, pdev, hpriv);
1619 if (rc)
1620 return rc;
1621
1622 probe_ent->n_ports = fls(hpriv->port_map);
1623 probe_ent->dummy_port_mask = ~hpriv->port_map;
1624
1625 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1626 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1627
1628 using_dac = hpriv->cap & HOST_CAP_64;
1629 if (using_dac && 1576 if (using_dac &&
1630 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 1577 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1631 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 1578 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
@@ -1651,23 +1598,14 @@ static int ahci_host_init(struct ata_probe_ent *probe_ent)
1651 return rc; 1598 return rc;
1652 } 1599 }
1653 } 1600 }
1654
1655 for (i = 0; i < probe_ent->n_ports; i++)
1656 ahci_setup_port(&probe_ent->port[i], mmio, i);
1657
1658 ahci_init_controller(mmio, pdev, probe_ent->n_ports,
1659 probe_ent->port_flags, hpriv);
1660
1661 pci_set_master(pdev);
1662
1663 return 0; 1601 return 0;
1664} 1602}
1665 1603
1666static void ahci_print_info(struct ata_probe_ent *probe_ent) 1604static void ahci_print_info(struct ata_host *host)
1667{ 1605{
1668 struct ahci_host_priv *hpriv = probe_ent->private_data; 1606 struct ahci_host_priv *hpriv = host->private_data;
1669 struct pci_dev *pdev = to_pci_dev(probe_ent->dev); 1607 struct pci_dev *pdev = to_pci_dev(host->dev);
1670 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR]; 1608 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1671 u32 vers, cap, impl, speed; 1609 u32 vers, cap, impl, speed;
1672 const char *speed_s; 1610 const char *speed_s;
1673 u16 cc; 1611 u16 cc;
@@ -1737,11 +1675,12 @@ static void ahci_print_info(struct ata_probe_ent *probe_ent)
1737static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1675static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1738{ 1676{
1739 static int printed_version; 1677 static int printed_version;
1740 unsigned int board_idx = (unsigned int) ent->driver_data; 1678 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1679 const struct ata_port_info *ppi[] = { &pi, NULL };
1741 struct device *dev = &pdev->dev; 1680 struct device *dev = &pdev->dev;
1742 struct ata_probe_ent *probe_ent;
1743 struct ahci_host_priv *hpriv; 1681 struct ahci_host_priv *hpriv;
1744 int rc; 1682 struct ata_host *host;
1683 int i, rc;
1745 1684
1746 VPRINTK("ENTER\n"); 1685 VPRINTK("ENTER\n");
1747 1686
@@ -1750,6 +1689,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1750 if (!printed_version++) 1689 if (!printed_version++)
1751 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1690 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1752 1691
1692 /* acquire resources */
1753 rc = pcim_enable_device(pdev); 1693 rc = pcim_enable_device(pdev);
1754 if (rc) 1694 if (rc)
1755 return rc; 1695 return rc;
@@ -1763,46 +1703,49 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1763 if (pci_enable_msi(pdev)) 1703 if (pci_enable_msi(pdev))
1764 pci_intx(pdev, 1); 1704 pci_intx(pdev, 1);
1765 1705
1766 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
1767 if (probe_ent == NULL)
1768 return -ENOMEM;
1769
1770 probe_ent->dev = pci_dev_to_dev(pdev);
1771 INIT_LIST_HEAD(&probe_ent->node);
1772
1773 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); 1706 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1774 if (!hpriv) 1707 if (!hpriv)
1775 return -ENOMEM; 1708 return -ENOMEM;
1776 1709
1777 probe_ent->sht = ahci_port_info[board_idx].sht; 1710 /* save initial config */
1778 probe_ent->port_flags = ahci_port_info[board_idx].flags; 1711 ahci_save_initial_config(pdev, &pi, hpriv);
1779 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1780 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1781 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1782 1712
1783 probe_ent->irq = pdev->irq; 1713 /* prepare host */
1784 probe_ent->irq_flags = IRQF_SHARED; 1714 if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ))
1785 probe_ent->iomap = pcim_iomap_table(pdev); 1715 pi.flags |= ATA_FLAG_NCQ;
1786 probe_ent->private_data = hpriv;
1787 1716
1788 /* initialize adapter */ 1717 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1789 ahci_save_initial_config(probe_ent); 1718 if (!host)
1719 return -ENOMEM;
1720 host->iomap = pcim_iomap_table(pdev);
1721 host->private_data = hpriv;
1722
1723 for (i = 0; i < host->n_ports; i++) {
1724 if (hpriv->port_map & (1 << i)) {
1725 struct ata_port *ap = host->ports[i];
1726 void __iomem *port_mmio = ahci_port_base(ap);
1727
1728 ap->ioaddr.cmd_addr = port_mmio;
1729 ap->ioaddr.scr_addr = port_mmio + PORT_SCR;
1730 } else
1731 host->ports[i]->ops = &ata_dummy_port_ops;
1732 }
1790 1733
1791 rc = ahci_host_init(probe_ent); 1734 /* initialize adapter */
1735 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1792 if (rc) 1736 if (rc)
1793 return rc; 1737 return rc;
1794 1738
1795 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) && 1739 rc = ahci_reset_controller(host);
1796 (hpriv->cap & HOST_CAP_NCQ)) 1740 if (rc)
1797 probe_ent->port_flags |= ATA_FLAG_NCQ; 1741 return rc;
1798
1799 ahci_print_info(probe_ent);
1800 1742
1801 if (!ata_device_add(probe_ent)) 1743 ahci_init_controller(host);
1802 return -ENODEV; 1744 ahci_print_info(host);
1803 1745
1804 devm_kfree(dev, probe_ent); 1746 pci_set_master(pdev);
1805 return 0; 1747 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1748 &ahci_sht);
1806} 1749}
1807 1750
1808static int __init ahci_init(void) 1751static int __init ahci_init(void)
diff --git a/drivers/ata/sata_inic162x.c b/drivers/ata/sata_inic162x.c
index ca4092aaae5b..f099a1d83a00 100644
--- a/drivers/ata/sata_inic162x.c
+++ b/drivers/ata/sata_inic162x.c
@@ -559,7 +559,6 @@ static struct ata_port_operations inic_port_ops = {
559 .bmdma_stop = inic_bmdma_stop, 559 .bmdma_stop = inic_bmdma_stop,
560 .bmdma_status = inic_bmdma_status, 560 .bmdma_status = inic_bmdma_status,
561 561
562 .irq_handler = inic_interrupt,
563 .irq_clear = inic_irq_clear, 562 .irq_clear = inic_irq_clear,
564 .irq_on = ata_irq_on, 563 .irq_on = ata_irq_on,
565 .irq_ack = ata_irq_ack, 564 .irq_ack = ata_irq_ack,
@@ -580,7 +579,6 @@ static struct ata_port_operations inic_port_ops = {
580}; 579};
581 580
582static struct ata_port_info inic_port_info = { 581static struct ata_port_info inic_port_info = {
583 .sht = &inic_sht,
584 /* For some reason, ATA_PROT_ATAPI is broken on this 582 /* For some reason, ATA_PROT_ATAPI is broken on this
585 * controller, and no, PIO_POLLING does't fix it. It somehow 583 * controller, and no, PIO_POLLING does't fix it. It somehow
586 * manages to report the wrong ireason and ignoring ireason 584 * manages to report the wrong ireason and ignoring ireason
@@ -661,8 +659,8 @@ static int inic_pci_device_resume(struct pci_dev *pdev)
661static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 659static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
662{ 660{
663 static int printed_version; 661 static int printed_version;
664 struct ata_port_info *pinfo = &inic_port_info; 662 const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
665 struct ata_probe_ent *probe_ent; 663 struct ata_host *host;
666 struct inic_host_priv *hpriv; 664 struct inic_host_priv *hpriv;
667 void __iomem * const *iomap; 665 void __iomem * const *iomap;
668 int i, rc; 666 int i, rc;
@@ -670,6 +668,15 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
670 if (!printed_version++) 668 if (!printed_version++)
671 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 669 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
672 670
671 /* alloc host */
672 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
673 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
674 if (!host || !hpriv)
675 return -ENOMEM;
676
677 host->private_data = hpriv;
678
679 /* acquire resources and fill host */
673 rc = pcim_enable_device(pdev); 680 rc = pcim_enable_device(pdev);
674 if (rc) 681 if (rc)
675 return rc; 682 return rc;
@@ -677,7 +684,22 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
677 rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME); 684 rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
678 if (rc) 685 if (rc)
679 return rc; 686 return rc;
680 iomap = pcim_iomap_table(pdev); 687 host->iomap = iomap = pcim_iomap_table(pdev);
688
689 for (i = 0; i < NR_PORTS; i++) {
690 struct ata_ioports *port = &host->ports[i]->ioaddr;
691 void __iomem *port_base = iomap[MMIO_BAR] + i * PORT_SIZE;
692
693 port->cmd_addr = iomap[2 * i];
694 port->altstatus_addr =
695 port->ctl_addr = (void __iomem *)
696 ((unsigned long)iomap[2 * i + 1] | ATA_PCI_CTL_OFS);
697 port->scr_addr = port_base + PORT_SCR;
698
699 ata_std_ports(port);
700 }
701
702 hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL);
681 703
682 /* Set dma_mask. This devices doesn't support 64bit addressing. */ 704 /* Set dma_mask. This devices doesn't support 64bit addressing. */
683 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 705 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
@@ -694,43 +716,6 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
694 return rc; 716 return rc;
695 } 717 }
696 718
697 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
698 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
699 if (!probe_ent || !hpriv)
700 return -ENOMEM;
701
702 probe_ent->dev = &pdev->dev;
703 INIT_LIST_HEAD(&probe_ent->node);
704
705 probe_ent->sht = pinfo->sht;
706 probe_ent->port_flags = pinfo->flags;
707 probe_ent->pio_mask = pinfo->pio_mask;
708 probe_ent->mwdma_mask = pinfo->mwdma_mask;
709 probe_ent->udma_mask = pinfo->udma_mask;
710 probe_ent->port_ops = pinfo->port_ops;
711 probe_ent->n_ports = NR_PORTS;
712
713 probe_ent->irq = pdev->irq;
714 probe_ent->irq_flags = IRQF_SHARED;
715
716 probe_ent->iomap = iomap;
717
718 for (i = 0; i < NR_PORTS; i++) {
719 struct ata_ioports *port = &probe_ent->port[i];
720 void __iomem *port_base = iomap[MMIO_BAR] + i * PORT_SIZE;
721
722 port->cmd_addr = iomap[2 * i];
723 port->altstatus_addr =
724 port->ctl_addr = (void __iomem *)
725 ((unsigned long)iomap[2 * i + 1] | ATA_PCI_CTL_OFS);
726 port->scr_addr = port_base + PORT_SCR;
727
728 ata_std_ports(port);
729 }
730
731 probe_ent->private_data = hpriv;
732 hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL);
733
734 rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl); 719 rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl);
735 if (rc) { 720 if (rc) {
736 dev_printk(KERN_ERR, &pdev->dev, 721 dev_printk(KERN_ERR, &pdev->dev,
@@ -739,13 +724,8 @@ static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
739 } 724 }
740 725
741 pci_set_master(pdev); 726 pci_set_master(pdev);
742 727 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
743 if (!ata_device_add(probe_ent)) 728 &inic_sht);
744 return -ENODEV;
745
746 devm_kfree(&pdev->dev, probe_ent);
747
748 return 0;
749} 729}
750 730
751static const struct pci_device_id inic_pci_tbl[] = { 731static const struct pci_device_id inic_pci_tbl[] = {
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 10cad5d9a76d..cb9b9ac12b4c 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -347,7 +347,6 @@ static void mv_port_stop(struct ata_port *ap);
347static void mv_qc_prep(struct ata_queued_cmd *qc); 347static void mv_qc_prep(struct ata_queued_cmd *qc);
348static void mv_qc_prep_iie(struct ata_queued_cmd *qc); 348static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
349static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); 349static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
350static irqreturn_t mv_interrupt(int irq, void *dev_instance);
351static void mv_eng_timeout(struct ata_port *ap); 350static void mv_eng_timeout(struct ata_port *ap);
352static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 351static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
353 352
@@ -410,7 +409,6 @@ static const struct ata_port_operations mv5_ops = {
410 409
411 .eng_timeout = mv_eng_timeout, 410 .eng_timeout = mv_eng_timeout,
412 411
413 .irq_handler = mv_interrupt,
414 .irq_clear = mv_irq_clear, 412 .irq_clear = mv_irq_clear,
415 .irq_on = ata_irq_on, 413 .irq_on = ata_irq_on,
416 .irq_ack = ata_irq_ack, 414 .irq_ack = ata_irq_ack,
@@ -440,7 +438,6 @@ static const struct ata_port_operations mv6_ops = {
440 438
441 .eng_timeout = mv_eng_timeout, 439 .eng_timeout = mv_eng_timeout,
442 440
443 .irq_handler = mv_interrupt,
444 .irq_clear = mv_irq_clear, 441 .irq_clear = mv_irq_clear,
445 .irq_on = ata_irq_on, 442 .irq_on = ata_irq_on,
446 .irq_ack = ata_irq_ack, 443 .irq_ack = ata_irq_ack,
@@ -470,7 +467,6 @@ static const struct ata_port_operations mv_iie_ops = {
470 467
471 .eng_timeout = mv_eng_timeout, 468 .eng_timeout = mv_eng_timeout,
472 469
473 .irq_handler = mv_interrupt,
474 .irq_clear = mv_irq_clear, 470 .irq_clear = mv_irq_clear,
475 .irq_on = ata_irq_on, 471 .irq_on = ata_irq_on,
476 .irq_ack = ata_irq_ack, 472 .irq_ack = ata_irq_ack,
@@ -484,35 +480,30 @@ static const struct ata_port_operations mv_iie_ops = {
484 480
485static const struct ata_port_info mv_port_info[] = { 481static const struct ata_port_info mv_port_info[] = {
486 { /* chip_504x */ 482 { /* chip_504x */
487 .sht = &mv_sht,
488 .flags = MV_COMMON_FLAGS, 483 .flags = MV_COMMON_FLAGS,
489 .pio_mask = 0x1f, /* pio0-4 */ 484 .pio_mask = 0x1f, /* pio0-4 */
490 .udma_mask = 0x7f, /* udma0-6 */ 485 .udma_mask = 0x7f, /* udma0-6 */
491 .port_ops = &mv5_ops, 486 .port_ops = &mv5_ops,
492 }, 487 },
493 { /* chip_508x */ 488 { /* chip_508x */
494 .sht = &mv_sht,
495 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), 489 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
496 .pio_mask = 0x1f, /* pio0-4 */ 490 .pio_mask = 0x1f, /* pio0-4 */
497 .udma_mask = 0x7f, /* udma0-6 */ 491 .udma_mask = 0x7f, /* udma0-6 */
498 .port_ops = &mv5_ops, 492 .port_ops = &mv5_ops,
499 }, 493 },
500 { /* chip_5080 */ 494 { /* chip_5080 */
501 .sht = &mv_sht,
502 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), 495 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
503 .pio_mask = 0x1f, /* pio0-4 */ 496 .pio_mask = 0x1f, /* pio0-4 */
504 .udma_mask = 0x7f, /* udma0-6 */ 497 .udma_mask = 0x7f, /* udma0-6 */
505 .port_ops = &mv5_ops, 498 .port_ops = &mv5_ops,
506 }, 499 },
507 { /* chip_604x */ 500 { /* chip_604x */
508 .sht = &mv_sht,
509 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), 501 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
510 .pio_mask = 0x1f, /* pio0-4 */ 502 .pio_mask = 0x1f, /* pio0-4 */
511 .udma_mask = 0x7f, /* udma0-6 */ 503 .udma_mask = 0x7f, /* udma0-6 */
512 .port_ops = &mv6_ops, 504 .port_ops = &mv6_ops,
513 }, 505 },
514 { /* chip_608x */ 506 { /* chip_608x */
515 .sht = &mv_sht,
516 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | 507 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
517 MV_FLAG_DUAL_HC), 508 MV_FLAG_DUAL_HC),
518 .pio_mask = 0x1f, /* pio0-4 */ 509 .pio_mask = 0x1f, /* pio0-4 */
@@ -520,14 +511,12 @@ static const struct ata_port_info mv_port_info[] = {
520 .port_ops = &mv6_ops, 511 .port_ops = &mv6_ops,
521 }, 512 },
522 { /* chip_6042 */ 513 { /* chip_6042 */
523 .sht = &mv_sht,
524 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), 514 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
525 .pio_mask = 0x1f, /* pio0-4 */ 515 .pio_mask = 0x1f, /* pio0-4 */
526 .udma_mask = 0x7f, /* udma0-6 */ 516 .udma_mask = 0x7f, /* udma0-6 */
527 .port_ops = &mv_iie_ops, 517 .port_ops = &mv_iie_ops,
528 }, 518 },
529 { /* chip_7042 */ 519 { /* chip_7042 */
530 .sht = &mv_sht,
531 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), 520 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
532 .pio_mask = 0x1f, /* pio0-4 */ 521 .pio_mask = 0x1f, /* pio0-4 */
533 .udma_mask = 0x7f, /* udma0-6 */ 522 .udma_mask = 0x7f, /* udma0-6 */
@@ -2099,9 +2088,10 @@ static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2099 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); 2088 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2100} 2089}
2101 2090
2102static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv, 2091static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2103 unsigned int board_idx)
2104{ 2092{
2093 struct pci_dev *pdev = to_pci_dev(host->dev);
2094 struct mv_host_priv *hpriv = host->private_data;
2105 u8 rev_id; 2095 u8 rev_id;
2106 u32 hp_flags = hpriv->hp_flags; 2096 u32 hp_flags = hpriv->hp_flags;
2107 2097
@@ -2199,8 +2189,8 @@ static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
2199 2189
2200/** 2190/**
2201 * mv_init_host - Perform some early initialization of the host. 2191 * mv_init_host - Perform some early initialization of the host.
2202 * @pdev: host PCI device 2192 * @host: ATA host to initialize
2203 * @probe_ent: early data struct representing the host 2193 * @board_idx: controller index
2204 * 2194 *
2205 * If possible, do an early global reset of the host. Then do 2195 * If possible, do an early global reset of the host. Then do
2206 * our port init and clear/unmask all/relevant host interrupts. 2196 * our port init and clear/unmask all/relevant host interrupts.
@@ -2208,24 +2198,23 @@ static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
2208 * LOCKING: 2198 * LOCKING:
2209 * Inherited from caller. 2199 * Inherited from caller.
2210 */ 2200 */
2211static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent, 2201static int mv_init_host(struct ata_host *host, unsigned int board_idx)
2212 unsigned int board_idx)
2213{ 2202{
2214 int rc = 0, n_hc, port, hc; 2203 int rc = 0, n_hc, port, hc;
2215 void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR]; 2204 struct pci_dev *pdev = to_pci_dev(host->dev);
2216 struct mv_host_priv *hpriv = probe_ent->private_data; 2205 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
2206 struct mv_host_priv *hpriv = host->private_data;
2217 2207
2218 /* global interrupt mask */ 2208 /* global interrupt mask */
2219 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS); 2209 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2220 2210
2221 rc = mv_chip_id(pdev, hpriv, board_idx); 2211 rc = mv_chip_id(host, board_idx);
2222 if (rc) 2212 if (rc)
2223 goto done; 2213 goto done;
2224 2214
2225 n_hc = mv_get_hc_count(probe_ent->port_flags); 2215 n_hc = mv_get_hc_count(host->ports[0]->flags);
2226 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2227 2216
2228 for (port = 0; port < probe_ent->n_ports; port++) 2217 for (port = 0; port < host->n_ports; port++)
2229 hpriv->ops->read_preamp(hpriv, port, mmio); 2218 hpriv->ops->read_preamp(hpriv, port, mmio);
2230 2219
2231 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); 2220 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
@@ -2236,7 +2225,7 @@ static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2236 hpriv->ops->reset_bus(pdev, mmio); 2225 hpriv->ops->reset_bus(pdev, mmio);
2237 hpriv->ops->enable_leds(hpriv, mmio); 2226 hpriv->ops->enable_leds(hpriv, mmio);
2238 2227
2239 for (port = 0; port < probe_ent->n_ports; port++) { 2228 for (port = 0; port < host->n_ports; port++) {
2240 if (IS_60XX(hpriv)) { 2229 if (IS_60XX(hpriv)) {
2241 void __iomem *port_mmio = mv_port_base(mmio, port); 2230 void __iomem *port_mmio = mv_port_base(mmio, port);
2242 2231
@@ -2249,9 +2238,9 @@ static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2249 hpriv->ops->phy_errata(hpriv, mmio, port); 2238 hpriv->ops->phy_errata(hpriv, mmio, port);
2250 } 2239 }
2251 2240
2252 for (port = 0; port < probe_ent->n_ports; port++) { 2241 for (port = 0; port < host->n_ports; port++) {
2253 void __iomem *port_mmio = mv_port_base(mmio, port); 2242 void __iomem *port_mmio = mv_port_base(mmio, port);
2254 mv_port_init(&probe_ent->port[port], port_mmio); 2243 mv_port_init(&host->ports[port]->ioaddr, port_mmio);
2255 } 2244 }
2256 2245
2257 for (hc = 0; hc < n_hc; hc++) { 2246 for (hc = 0; hc < n_hc; hc++) {
@@ -2290,17 +2279,17 @@ done:
2290 2279
2291/** 2280/**
2292 * mv_print_info - Dump key info to kernel log for perusal. 2281 * mv_print_info - Dump key info to kernel log for perusal.
2293 * @probe_ent: early data struct representing the host 2282 * @host: ATA host to print info about
2294 * 2283 *
2295 * FIXME: complete this. 2284 * FIXME: complete this.
2296 * 2285 *
2297 * LOCKING: 2286 * LOCKING:
2298 * Inherited from caller. 2287 * Inherited from caller.
2299 */ 2288 */
2300static void mv_print_info(struct ata_probe_ent *probe_ent) 2289static void mv_print_info(struct ata_host *host)
2301{ 2290{
2302 struct pci_dev *pdev = to_pci_dev(probe_ent->dev); 2291 struct pci_dev *pdev = to_pci_dev(host->dev);
2303 struct mv_host_priv *hpriv = probe_ent->private_data; 2292 struct mv_host_priv *hpriv = host->private_data;
2304 u8 rev_id, scc; 2293 u8 rev_id, scc;
2305 const char *scc_s; 2294 const char *scc_s;
2306 2295
@@ -2319,7 +2308,7 @@ static void mv_print_info(struct ata_probe_ent *probe_ent)
2319 2308
2320 dev_printk(KERN_INFO, &pdev->dev, 2309 dev_printk(KERN_INFO, &pdev->dev,
2321 "%u slots %u ports %s mode IRQ via %s\n", 2310 "%u slots %u ports %s mode IRQ via %s\n",
2322 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports, 2311 (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
2323 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); 2312 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2324} 2313}
2325 2314
@@ -2334,54 +2323,42 @@ static void mv_print_info(struct ata_probe_ent *probe_ent)
2334static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 2323static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2335{ 2324{
2336 static int printed_version = 0; 2325 static int printed_version = 0;
2337 struct device *dev = &pdev->dev;
2338 struct ata_probe_ent *probe_ent;
2339 struct mv_host_priv *hpriv;
2340 unsigned int board_idx = (unsigned int)ent->driver_data; 2326 unsigned int board_idx = (unsigned int)ent->driver_data;
2341 int rc; 2327 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
2328 struct ata_host *host;
2329 struct mv_host_priv *hpriv;
2330 int n_ports, rc;
2342 2331
2343 if (!printed_version++) 2332 if (!printed_version++)
2344 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); 2333 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2345 2334
2335 /* allocate host */
2336 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
2337
2338 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2339 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
2340 if (!host || !hpriv)
2341 return -ENOMEM;
2342 host->private_data = hpriv;
2343
2344 /* acquire resources */
2346 rc = pcim_enable_device(pdev); 2345 rc = pcim_enable_device(pdev);
2347 if (rc) 2346 if (rc)
2348 return rc; 2347 return rc;
2349 pci_set_master(pdev);
2350 2348
2351 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); 2349 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
2352 if (rc == -EBUSY) 2350 if (rc == -EBUSY)
2353 pcim_pin_device(pdev); 2351 pcim_pin_device(pdev);
2354 if (rc) 2352 if (rc)
2355 return rc; 2353 return rc;
2354 host->iomap = pcim_iomap_table(pdev);
2356 2355
2357 rc = pci_go_64(pdev); 2356 rc = pci_go_64(pdev);
2358 if (rc) 2357 if (rc)
2359 return rc; 2358 return rc;
2360 2359
2361 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
2362 if (probe_ent == NULL)
2363 return -ENOMEM;
2364
2365 probe_ent->dev = pci_dev_to_dev(pdev);
2366 INIT_LIST_HEAD(&probe_ent->node);
2367
2368 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2369 if (!hpriv)
2370 return -ENOMEM;
2371
2372 probe_ent->sht = mv_port_info[board_idx].sht;
2373 probe_ent->port_flags = mv_port_info[board_idx].flags;
2374 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2375 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2376 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2377
2378 probe_ent->irq = pdev->irq;
2379 probe_ent->irq_flags = IRQF_SHARED;
2380 probe_ent->iomap = pcim_iomap_table(pdev);
2381 probe_ent->private_data = hpriv;
2382
2383 /* initialize adapter */ 2360 /* initialize adapter */
2384 rc = mv_init_host(pdev, probe_ent, board_idx); 2361 rc = mv_init_host(host, board_idx);
2385 if (rc) 2362 if (rc)
2386 return rc; 2363 return rc;
2387 2364
@@ -2390,13 +2367,11 @@ static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2390 pci_intx(pdev, 1); 2367 pci_intx(pdev, 1);
2391 2368
2392 mv_dump_pci_cfg(pdev, 0x68); 2369 mv_dump_pci_cfg(pdev, 0x68);
2393 mv_print_info(probe_ent); 2370 mv_print_info(host);
2394
2395 if (ata_device_add(probe_ent) == 0)
2396 return -ENODEV;
2397 2371
2398 devm_kfree(dev, probe_ent); 2372 pci_set_master(pdev);
2399 return 0; 2373 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
2374 &mv_sht);
2400} 2375}
2401 2376
2402static int __init mv_init(void) 2377static int __init mv_init(void)
diff --git a/drivers/ata/sata_qstor.c b/drivers/ata/sata_qstor.c
index 8786b45f291b..f5a05de0093d 100644
--- a/drivers/ata/sata_qstor.c
+++ b/drivers/ata/sata_qstor.c
@@ -114,7 +114,6 @@ struct qs_port_priv {
114static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg); 114static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg);
115static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 115static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
116static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 116static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
117static irqreturn_t qs_intr (int irq, void *dev_instance);
118static int qs_port_start(struct ata_port *ap); 117static int qs_port_start(struct ata_port *ap);
119static void qs_host_stop(struct ata_host *host); 118static void qs_host_stop(struct ata_host *host);
120static void qs_phy_reset(struct ata_port *ap); 119static void qs_phy_reset(struct ata_port *ap);
@@ -158,7 +157,6 @@ static const struct ata_port_operations qs_ata_ops = {
158 .qc_issue = qs_qc_issue, 157 .qc_issue = qs_qc_issue,
159 .data_xfer = ata_data_xfer, 158 .data_xfer = ata_data_xfer,
160 .eng_timeout = qs_eng_timeout, 159 .eng_timeout = qs_eng_timeout,
161 .irq_handler = qs_intr,
162 .irq_clear = qs_irq_clear, 160 .irq_clear = qs_irq_clear,
163 .irq_on = ata_irq_on, 161 .irq_on = ata_irq_on,
164 .irq_ack = ata_irq_ack, 162 .irq_ack = ata_irq_ack,
@@ -173,7 +171,6 @@ static const struct ata_port_operations qs_ata_ops = {
173static const struct ata_port_info qs_port_info[] = { 171static const struct ata_port_info qs_port_info[] = {
174 /* board_2068_idx */ 172 /* board_2068_idx */
175 { 173 {
176 .sht = &qs_ata_sht,
177 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 174 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
178 ATA_FLAG_SATA_RESET | 175 ATA_FLAG_SATA_RESET |
179 //FIXME ATA_FLAG_SRST | 176 //FIXME ATA_FLAG_SRST |
@@ -530,16 +527,16 @@ static void qs_host_stop(struct ata_host *host)
530 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */ 527 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
531} 528}
532 529
533static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe) 530static void qs_host_init(struct ata_host *host, unsigned int chip_id)
534{ 531{
535 void __iomem *mmio_base = pe->iomap[QS_MMIO_BAR]; 532 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
536 unsigned int port_no; 533 unsigned int port_no;
537 534
538 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ 535 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
539 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */ 536 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
540 537
541 /* reset each channel in turn */ 538 /* reset each channel in turn */
542 for (port_no = 0; port_no < pe->n_ports; ++port_no) { 539 for (port_no = 0; port_no < host->n_ports; ++port_no) {
543 u8 __iomem *chan = mmio_base + (port_no * 0x4000); 540 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
544 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1); 541 writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1);
545 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0); 542 writeb(QS_CTR0_REG, chan + QS_CCT_CTR0);
@@ -547,7 +544,7 @@ static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
547 } 544 }
548 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */ 545 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
549 546
550 for (port_no = 0; port_no < pe->n_ports; ++port_no) { 547 for (port_no = 0; port_no < host->n_ports; ++port_no) {
551 u8 __iomem *chan = mmio_base + (port_no * 0x4000); 548 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
552 /* set FIFO depths to same settings as Windows driver */ 549 /* set FIFO depths to same settings as Windows driver */
553 writew(32, chan + QS_CFC_HUFT); 550 writew(32, chan + QS_CFC_HUFT);
@@ -607,14 +604,20 @@ static int qs_ata_init_one(struct pci_dev *pdev,
607 const struct pci_device_id *ent) 604 const struct pci_device_id *ent)
608{ 605{
609 static int printed_version; 606 static int printed_version;
610 struct ata_probe_ent *probe_ent;
611 void __iomem * const *iomap;
612 unsigned int board_idx = (unsigned int) ent->driver_data; 607 unsigned int board_idx = (unsigned int) ent->driver_data;
608 const struct ata_port_info *ppi[] = { &qs_port_info[board_idx], NULL };
609 struct ata_host *host;
613 int rc, port_no; 610 int rc, port_no;
614 611
615 if (!printed_version++) 612 if (!printed_version++)
616 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 613 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
617 614
615 /* alloc host */
616 host = ata_host_alloc_pinfo(&pdev->dev, ppi, QS_PORTS);
617 if (!host)
618 return -ENOMEM;
619
620 /* acquire resources and fill host */
618 rc = pcim_enable_device(pdev); 621 rc = pcim_enable_device(pdev);
619 if (rc) 622 if (rc)
620 return rc; 623 return rc;
@@ -625,47 +628,24 @@ static int qs_ata_init_one(struct pci_dev *pdev,
625 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME); 628 rc = pcim_iomap_regions(pdev, 1 << QS_MMIO_BAR, DRV_NAME);
626 if (rc) 629 if (rc)
627 return rc; 630 return rc;
628 iomap = pcim_iomap_table(pdev); 631 host->iomap = pcim_iomap_table(pdev);
629 632
630 rc = qs_set_dma_masks(pdev, iomap[QS_MMIO_BAR]); 633 rc = qs_set_dma_masks(pdev, host->iomap[QS_MMIO_BAR]);
631 if (rc) 634 if (rc)
632 return rc; 635 return rc;
633 636
634 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL); 637 for (port_no = 0; port_no < host->n_ports; ++port_no) {
635 if (probe_ent == NULL)
636 return -ENOMEM;
637
638 probe_ent->dev = pci_dev_to_dev(pdev);
639 INIT_LIST_HEAD(&probe_ent->node);
640
641 probe_ent->sht = qs_port_info[board_idx].sht;
642 probe_ent->port_flags = qs_port_info[board_idx].flags;
643 probe_ent->pio_mask = qs_port_info[board_idx].pio_mask;
644 probe_ent->mwdma_mask = qs_port_info[board_idx].mwdma_mask;
645 probe_ent->udma_mask = qs_port_info[board_idx].udma_mask;
646 probe_ent->port_ops = qs_port_info[board_idx].port_ops;
647
648 probe_ent->irq = pdev->irq;
649 probe_ent->irq_flags = IRQF_SHARED;
650 probe_ent->iomap = iomap;
651 probe_ent->n_ports = QS_PORTS;
652
653 for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) {
654 void __iomem *chan = 638 void __iomem *chan =
655 probe_ent->iomap[QS_MMIO_BAR] + (port_no * 0x4000); 639 host->iomap[QS_MMIO_BAR] + (port_no * 0x4000);
656 qs_ata_setup_port(&probe_ent->port[port_no], chan); 640 qs_ata_setup_port(&host->ports[port_no]->ioaddr, chan);
657 } 641 }
658 642
659 pci_set_master(pdev);
660
661 /* initialize adapter */ 643 /* initialize adapter */
662 qs_host_init(board_idx, probe_ent); 644 qs_host_init(host, board_idx);
663 645
664 if (ata_device_add(probe_ent) != QS_PORTS) 646 pci_set_master(pdev);
665 return -EIO; 647 return ata_host_activate(host, pdev->irq, qs_intr, IRQF_SHARED,
666 648 &qs_ata_sht);
667 devm_kfree(&pdev->dev, probe_ent);
668 return 0;
669} 649}
670 650
671static int __init qs_ata_init(void) 651static int __init qs_ata_init(void)
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index 466b05b67115..0a1e417f309c 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -118,7 +118,6 @@ static void sil_dev_config(struct ata_device *dev);
118static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg); 118static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
119static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 119static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed); 120static int sil_set_mode (struct ata_port *ap, struct ata_device **r_failed);
121static irqreturn_t sil_interrupt(int irq, void *dev_instance);
122static void sil_freeze(struct ata_port *ap); 121static void sil_freeze(struct ata_port *ap);
123static void sil_thaw(struct ata_port *ap); 122static void sil_thaw(struct ata_port *ap);
124 123
@@ -209,7 +208,6 @@ static const struct ata_port_operations sil_ops = {
209 .thaw = sil_thaw, 208 .thaw = sil_thaw,
210 .error_handler = ata_bmdma_error_handler, 209 .error_handler = ata_bmdma_error_handler,
211 .post_internal_cmd = ata_bmdma_post_internal_cmd, 210 .post_internal_cmd = ata_bmdma_post_internal_cmd,
212 .irq_handler = sil_interrupt,
213 .irq_clear = ata_bmdma_irq_clear, 211 .irq_clear = ata_bmdma_irq_clear,
214 .irq_on = ata_irq_on, 212 .irq_on = ata_irq_on,
215 .irq_ack = ata_irq_ack, 213 .irq_ack = ata_irq_ack,
@@ -221,7 +219,6 @@ static const struct ata_port_operations sil_ops = {
221static const struct ata_port_info sil_port_info[] = { 219static const struct ata_port_info sil_port_info[] = {
222 /* sil_3112 */ 220 /* sil_3112 */
223 { 221 {
224 .sht = &sil_sht,
225 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE, 222 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
226 .pio_mask = 0x1f, /* pio0-4 */ 223 .pio_mask = 0x1f, /* pio0-4 */
227 .mwdma_mask = 0x07, /* mwdma0-2 */ 224 .mwdma_mask = 0x07, /* mwdma0-2 */
@@ -230,7 +227,6 @@ static const struct ata_port_info sil_port_info[] = {
230 }, 227 },
231 /* sil_3112_no_sata_irq */ 228 /* sil_3112_no_sata_irq */
232 { 229 {
233 .sht = &sil_sht,
234 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE | 230 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
235 SIL_FLAG_NO_SATA_IRQ, 231 SIL_FLAG_NO_SATA_IRQ,
236 .pio_mask = 0x1f, /* pio0-4 */ 232 .pio_mask = 0x1f, /* pio0-4 */
@@ -240,7 +236,6 @@ static const struct ata_port_info sil_port_info[] = {
240 }, 236 },
241 /* sil_3512 */ 237 /* sil_3512 */
242 { 238 {
243 .sht = &sil_sht,
244 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 239 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
245 .pio_mask = 0x1f, /* pio0-4 */ 240 .pio_mask = 0x1f, /* pio0-4 */
246 .mwdma_mask = 0x07, /* mwdma0-2 */ 241 .mwdma_mask = 0x07, /* mwdma0-2 */
@@ -249,7 +244,6 @@ static const struct ata_port_info sil_port_info[] = {
249 }, 244 },
250 /* sil_3114 */ 245 /* sil_3114 */
251 { 246 {
252 .sht = &sil_sht,
253 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 247 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
254 .pio_mask = 0x1f, /* pio0-4 */ 248 .pio_mask = 0x1f, /* pio0-4 */
255 .mwdma_mask = 0x07, /* mwdma0-2 */ 249 .mwdma_mask = 0x07, /* mwdma0-2 */
@@ -598,10 +592,10 @@ static void sil_dev_config(struct ata_device *dev)
598 } 592 }
599} 593}
600 594
601static void sil_init_controller(struct pci_dev *pdev, 595static void sil_init_controller(struct ata_host *host)
602 int n_ports, unsigned long port_flags,
603 void __iomem *mmio_base)
604{ 596{
597 struct pci_dev *pdev = to_pci_dev(host->dev);
598 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR];
605 u8 cls; 599 u8 cls;
606 u32 tmp; 600 u32 tmp;
607 int i; 601 int i;
@@ -611,7 +605,7 @@ static void sil_init_controller(struct pci_dev *pdev,
611 if (cls) { 605 if (cls) {
612 cls >>= 3; 606 cls >>= 3;
613 cls++; /* cls = (line_size/8)+1 */ 607 cls++; /* cls = (line_size/8)+1 */
614 for (i = 0; i < n_ports; i++) 608 for (i = 0; i < host->n_ports; i++)
615 writew(cls << 8 | cls, 609 writew(cls << 8 | cls,
616 mmio_base + sil_port[i].fifo_cfg); 610 mmio_base + sil_port[i].fifo_cfg);
617 } else 611 } else
@@ -619,10 +613,10 @@ static void sil_init_controller(struct pci_dev *pdev,
619 "cache line size not set. Driver may not function\n"); 613 "cache line size not set. Driver may not function\n");
620 614
621 /* Apply R_ERR on DMA activate FIS errata workaround */ 615 /* Apply R_ERR on DMA activate FIS errata workaround */
622 if (port_flags & SIL_FLAG_RERR_ON_DMA_ACT) { 616 if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) {
623 int cnt; 617 int cnt;
624 618
625 for (i = 0, cnt = 0; i < n_ports; i++) { 619 for (i = 0, cnt = 0; i < host->n_ports; i++) {
626 tmp = readl(mmio_base + sil_port[i].sfis_cfg); 620 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
627 if ((tmp & 0x3) != 0x01) 621 if ((tmp & 0x3) != 0x01)
628 continue; 622 continue;
@@ -635,7 +629,7 @@ static void sil_init_controller(struct pci_dev *pdev,
635 } 629 }
636 } 630 }
637 631
638 if (n_ports == 4) { 632 if (host->n_ports == 4) {
639 /* flip the magic "make 4 ports work" bit */ 633 /* flip the magic "make 4 ports work" bit */
640 tmp = readl(mmio_base + sil_port[2].bmdma); 634 tmp = readl(mmio_base + sil_port[2].bmdma);
641 if ((tmp & SIL_INTR_STEERING) == 0) 635 if ((tmp & SIL_INTR_STEERING) == 0)
@@ -647,15 +641,26 @@ static void sil_init_controller(struct pci_dev *pdev,
647static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 641static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
648{ 642{
649 static int printed_version; 643 static int printed_version;
650 struct device *dev = &pdev->dev; 644 int board_id = ent->driver_data;
651 struct ata_probe_ent *probe_ent; 645 const struct ata_port_info *ppi[] = { &sil_port_info[board_id], NULL };
646 struct ata_host *host;
652 void __iomem *mmio_base; 647 void __iomem *mmio_base;
653 int rc; 648 int n_ports, rc;
654 unsigned int i; 649 unsigned int i;
655 650
656 if (!printed_version++) 651 if (!printed_version++)
657 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 652 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
658 653
654 /* allocate host */
655 n_ports = 2;
656 if (board_id == sil_3114)
657 n_ports = 4;
658
659 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
660 if (!host)
661 return -ENOMEM;
662
663 /* acquire resources and fill host */
659 rc = pcim_enable_device(pdev); 664 rc = pcim_enable_device(pdev);
660 if (rc) 665 if (rc)
661 return rc; 666 return rc;
@@ -665,6 +670,7 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
665 pcim_pin_device(pdev); 670 pcim_pin_device(pdev);
666 if (rc) 671 if (rc)
667 return rc; 672 return rc;
673 host->iomap = pcim_iomap_table(pdev);
668 674
669 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 675 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
670 if (rc) 676 if (rc)
@@ -673,45 +679,25 @@ static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
673 if (rc) 679 if (rc)
674 return rc; 680 return rc;
675 681
676 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); 682 mmio_base = host->iomap[SIL_MMIO_BAR];
677 if (probe_ent == NULL)
678 return -ENOMEM;
679 683
680 INIT_LIST_HEAD(&probe_ent->node); 684 for (i = 0; i < host->n_ports; i++) {
681 probe_ent->dev = pci_dev_to_dev(pdev); 685 struct ata_ioports *ioaddr = &host->ports[i]->ioaddr;
682 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops; 686
683 probe_ent->sht = sil_port_info[ent->driver_data].sht; 687 ioaddr->cmd_addr = mmio_base + sil_port[i].tf;
684 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2; 688 ioaddr->altstatus_addr =
685 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask; 689 ioaddr->ctl_addr = mmio_base + sil_port[i].ctl;
686 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask; 690 ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma;
687 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask; 691 ioaddr->scr_addr = mmio_base + sil_port[i].scr;
688 probe_ent->irq = pdev->irq; 692 ata_std_ports(ioaddr);
689 probe_ent->irq_flags = IRQF_SHARED;
690 probe_ent->port_flags = sil_port_info[ent->driver_data].flags;
691
692 probe_ent->iomap = pcim_iomap_table(pdev);
693
694 mmio_base = probe_ent->iomap[SIL_MMIO_BAR];
695
696 for (i = 0; i < probe_ent->n_ports; i++) {
697 probe_ent->port[i].cmd_addr = mmio_base + sil_port[i].tf;
698 probe_ent->port[i].altstatus_addr =
699 probe_ent->port[i].ctl_addr = mmio_base + sil_port[i].ctl;
700 probe_ent->port[i].bmdma_addr = mmio_base + sil_port[i].bmdma;
701 probe_ent->port[i].scr_addr = mmio_base + sil_port[i].scr;
702 ata_std_ports(&probe_ent->port[i]);
703 } 693 }
704 694
705 sil_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags, 695 /* initialize and activate */
706 mmio_base); 696 sil_init_controller(host);
707 697
708 pci_set_master(pdev); 698 pci_set_master(pdev);
709 699 return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED,
710 if (!ata_device_add(probe_ent)) 700 &sil_sht);
711 return -ENODEV;
712
713 devm_kfree(dev, probe_ent);
714 return 0;
715} 701}
716 702
717#ifdef CONFIG_PM 703#ifdef CONFIG_PM
@@ -724,8 +710,7 @@ static int sil_pci_device_resume(struct pci_dev *pdev)
724 if (rc) 710 if (rc)
725 return rc; 711 return rc;
726 712
727 sil_init_controller(pdev, host->n_ports, host->ports[0]->flags, 713 sil_init_controller(host);
728 host->iomap[SIL_MMIO_BAR]);
729 ata_host_resume(host); 714 ata_host_resume(host);
730 715
731 return 0; 716 return 0;
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c
index 4f522ec04049..e6223ba667da 100644
--- a/drivers/ata/sata_sil24.c
+++ b/drivers/ata/sata_sil24.c
@@ -331,7 +331,6 @@ static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
331static void sil24_qc_prep(struct ata_queued_cmd *qc); 331static void sil24_qc_prep(struct ata_queued_cmd *qc);
332static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); 332static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
333static void sil24_irq_clear(struct ata_port *ap); 333static void sil24_irq_clear(struct ata_port *ap);
334static irqreturn_t sil24_interrupt(int irq, void *dev_instance);
335static void sil24_freeze(struct ata_port *ap); 334static void sil24_freeze(struct ata_port *ap);
336static void sil24_thaw(struct ata_port *ap); 335static void sil24_thaw(struct ata_port *ap);
337static void sil24_error_handler(struct ata_port *ap); 336static void sil24_error_handler(struct ata_port *ap);
@@ -401,7 +400,6 @@ static const struct ata_port_operations sil24_ops = {
401 .qc_prep = sil24_qc_prep, 400 .qc_prep = sil24_qc_prep,
402 .qc_issue = sil24_qc_issue, 401 .qc_issue = sil24_qc_issue,
403 402
404 .irq_handler = sil24_interrupt,
405 .irq_clear = sil24_irq_clear, 403 .irq_clear = sil24_irq_clear,
406 .irq_on = ata_dummy_irq_on, 404 .irq_on = ata_dummy_irq_on,
407 .irq_ack = ata_dummy_irq_ack, 405 .irq_ack = ata_dummy_irq_ack,
@@ -424,10 +422,9 @@ static const struct ata_port_operations sil24_ops = {
424#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) 422#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
425#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) 423#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
426 424
427static struct ata_port_info sil24_port_info[] = { 425static const struct ata_port_info sil24_port_info[] = {
428 /* sil_3124 */ 426 /* sil_3124 */
429 { 427 {
430 .sht = &sil24_sht,
431 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | 428 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
432 SIL24_FLAG_PCIX_IRQ_WOC, 429 SIL24_FLAG_PCIX_IRQ_WOC,
433 .pio_mask = 0x1f, /* pio0-4 */ 430 .pio_mask = 0x1f, /* pio0-4 */
@@ -437,7 +434,6 @@ static struct ata_port_info sil24_port_info[] = {
437 }, 434 },
438 /* sil_3132 */ 435 /* sil_3132 */
439 { 436 {
440 .sht = &sil24_sht,
441 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), 437 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
442 .pio_mask = 0x1f, /* pio0-4 */ 438 .pio_mask = 0x1f, /* pio0-4 */
443 .mwdma_mask = 0x07, /* mwdma0-2 */ 439 .mwdma_mask = 0x07, /* mwdma0-2 */
@@ -446,7 +442,6 @@ static struct ata_port_info sil24_port_info[] = {
446 }, 442 },
447 /* sil_3131/sil_3531 */ 443 /* sil_3131/sil_3531 */
448 { 444 {
449 .sht = &sil24_sht,
450 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), 445 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
451 .pio_mask = 0x1f, /* pio0-4 */ 446 .pio_mask = 0x1f, /* pio0-4 */
452 .mwdma_mask = 0x07, /* mwdma0-2 */ 447 .mwdma_mask = 0x07, /* mwdma0-2 */
@@ -961,11 +956,10 @@ static int sil24_port_start(struct ata_port *ap)
961 return 0; 956 return 0;
962} 957}
963 958
964static void sil24_init_controller(struct pci_dev *pdev, int n_ports, 959static void sil24_init_controller(struct ata_host *host)
965 unsigned long port_flags,
966 void __iomem *host_base,
967 void __iomem *port_base)
968{ 960{
961 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
962 void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
969 u32 tmp; 963 u32 tmp;
970 int i; 964 int i;
971 965
@@ -976,7 +970,7 @@ static void sil24_init_controller(struct pci_dev *pdev, int n_ports,
976 writel(0, host_base + HOST_CTRL); 970 writel(0, host_base + HOST_CTRL);
977 971
978 /* init ports */ 972 /* init ports */
979 for (i = 0; i < n_ports; i++) { 973 for (i = 0; i < host->n_ports; i++) {
980 void __iomem *port = port_base + i * PORT_REGS_SIZE; 974 void __iomem *port = port_base + i * PORT_REGS_SIZE;
981 975
982 /* Initial PHY setting */ 976 /* Initial PHY setting */
@@ -990,12 +984,12 @@ static void sil24_init_controller(struct pci_dev *pdev, int n_ports,
990 PORT_CS_PORT_RST, 984 PORT_CS_PORT_RST,
991 PORT_CS_PORT_RST, 10, 100); 985 PORT_CS_PORT_RST, 10, 100);
992 if (tmp & PORT_CS_PORT_RST) 986 if (tmp & PORT_CS_PORT_RST)
993 dev_printk(KERN_ERR, &pdev->dev, 987 dev_printk(KERN_ERR, host->dev,
994 "failed to clear port RST\n"); 988 "failed to clear port RST\n");
995 } 989 }
996 990
997 /* Configure IRQ WoC */ 991 /* Configure IRQ WoC */
998 if (port_flags & SIL24_FLAG_PCIX_IRQ_WOC) 992 if (host->ports[0]->flags & SIL24_FLAG_PCIX_IRQ_WOC)
999 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); 993 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1000 else 994 else
1001 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); 995 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
@@ -1023,18 +1017,17 @@ static void sil24_init_controller(struct pci_dev *pdev, int n_ports,
1023static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 1017static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1024{ 1018{
1025 static int printed_version = 0; 1019 static int printed_version = 0;
1026 struct device *dev = &pdev->dev; 1020 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1027 unsigned int board_id = (unsigned int)ent->driver_data; 1021 const struct ata_port_info *ppi[] = { &pi, NULL };
1028 struct ata_port_info *pinfo = &sil24_port_info[board_id]; 1022 void __iomem * const *iomap;
1029 struct ata_probe_ent *probe_ent; 1023 struct ata_host *host;
1030 void __iomem *host_base;
1031 void __iomem *port_base;
1032 int i, rc; 1024 int i, rc;
1033 u32 tmp; 1025 u32 tmp;
1034 1026
1035 if (!printed_version++) 1027 if (!printed_version++)
1036 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1028 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1037 1029
1030 /* acquire resources */
1038 rc = pcim_enable_device(pdev); 1031 rc = pcim_enable_device(pdev);
1039 if (rc) 1032 if (rc)
1040 return rc; 1033 return rc;
@@ -1044,33 +1037,36 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1044 DRV_NAME); 1037 DRV_NAME);
1045 if (rc) 1038 if (rc)
1046 return rc; 1039 return rc;
1040 iomap = pcim_iomap_table(pdev);
1047 1041
1048 /* allocate & init probe_ent */ 1042 /* apply workaround for completion IRQ loss on PCI-X errata */
1049 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); 1043 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1050 if (!probe_ent) 1044 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1051 return -ENOMEM; 1045 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1046 dev_printk(KERN_INFO, &pdev->dev,
1047 "Applying completion IRQ loss on PCI-X "
1048 "errata fix\n");
1049 else
1050 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1051 }
1052 1052
1053 probe_ent->dev = pci_dev_to_dev(pdev); 1053 /* allocate and fill host */
1054 INIT_LIST_HEAD(&probe_ent->node); 1054 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1055 SIL24_FLAG2NPORTS(ppi[0]->flags));
1056 if (!host)
1057 return -ENOMEM;
1058 host->iomap = iomap;
1055 1059
1056 probe_ent->sht = pinfo->sht; 1060 for (i = 0; i < host->n_ports; i++) {
1057 probe_ent->port_flags = pinfo->flags; 1061 void __iomem *port = iomap[SIL24_PORT_BAR] + i * PORT_REGS_SIZE;
1058 probe_ent->pio_mask = pinfo->pio_mask;
1059 probe_ent->mwdma_mask = pinfo->mwdma_mask;
1060 probe_ent->udma_mask = pinfo->udma_mask;
1061 probe_ent->port_ops = pinfo->port_ops;
1062 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->flags);
1063 1062
1064 probe_ent->irq = pdev->irq; 1063 host->ports[i]->ioaddr.cmd_addr = port;
1065 probe_ent->irq_flags = IRQF_SHARED; 1064 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
1066 probe_ent->iomap = pcim_iomap_table(pdev);
1067 1065
1068 host_base = probe_ent->iomap[SIL24_HOST_BAR]; 1066 ata_std_ports(&host->ports[i]->ioaddr);
1069 port_base = probe_ent->iomap[SIL24_PORT_BAR]; 1067 }
1070 1068
1071 /* 1069 /* configure and activate the device */
1072 * Configure the device
1073 */
1074 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 1070 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1075 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); 1071 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1076 if (rc) { 1072 if (rc) {
@@ -1096,36 +1092,11 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1096 } 1092 }
1097 } 1093 }
1098 1094
1099 /* Apply workaround for completion IRQ loss on PCI-X errata */ 1095 sil24_init_controller(host);
1100 if (probe_ent->port_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1101 tmp = readl(host_base + HOST_CTRL);
1102 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1103 dev_printk(KERN_INFO, &pdev->dev,
1104 "Applying completion IRQ loss on PCI-X "
1105 "errata fix\n");
1106 else
1107 probe_ent->port_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1108 }
1109
1110 for (i = 0; i < probe_ent->n_ports; i++) {
1111 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1112
1113 probe_ent->port[i].cmd_addr = port;
1114 probe_ent->port[i].scr_addr = port + PORT_SCONTROL;
1115
1116 ata_std_ports(&probe_ent->port[i]);
1117 }
1118
1119 sil24_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags,
1120 host_base, port_base);
1121 1096
1122 pci_set_master(pdev); 1097 pci_set_master(pdev);
1123 1098 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1124 if (!ata_device_add(probe_ent)) 1099 &sil24_sht);
1125 return -ENODEV;
1126
1127 devm_kfree(dev, probe_ent);
1128 return 0;
1129} 1100}
1130 1101
1131#ifdef CONFIG_PM 1102#ifdef CONFIG_PM
@@ -1133,7 +1104,6 @@ static int sil24_pci_device_resume(struct pci_dev *pdev)
1133{ 1104{
1134 struct ata_host *host = dev_get_drvdata(&pdev->dev); 1105 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1135 void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; 1106 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1136 void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
1137 int rc; 1107 int rc;
1138 1108
1139 rc = ata_pci_device_do_resume(pdev); 1109 rc = ata_pci_device_do_resume(pdev);
@@ -1143,8 +1113,7 @@ static int sil24_pci_device_resume(struct pci_dev *pdev)
1143 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) 1113 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1144 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); 1114 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1145 1115
1146 sil24_init_controller(pdev, host->n_ports, host->ports[0]->flags, 1116 sil24_init_controller(host);
1147 host_base, port_base);
1148 1117
1149 ata_host_resume(host); 1118 ata_host_resume(host);
1150 1119
diff --git a/drivers/ata/sata_svw.c b/drivers/ata/sata_svw.c
index b121195cc598..cc07aac10e8c 100644
--- a/drivers/ata/sata_svw.c
+++ b/drivers/ata/sata_svw.c
@@ -56,7 +56,9 @@
56#define DRV_VERSION "2.1" 56#define DRV_VERSION "2.1"
57 57
58enum { 58enum {
59 K2_FLAG_NO_ATAPI_DMA = (1 << 29), 59 /* ap->flags bits */
60 K2_FLAG_SATA_8_PORTS = (1 << 24),
61 K2_FLAG_NO_ATAPI_DMA = (1 << 25),
60 62
61 /* Taskfile registers offsets */ 63 /* Taskfile registers offsets */
62 K2_SATA_TF_CMD_OFFSET = 0x00, 64 K2_SATA_TF_CMD_OFFSET = 0x00,
@@ -90,17 +92,6 @@ enum {
90 board_svw8 = 1, 92 board_svw8 = 1,
91}; 93};
92 94
93static const struct k2_board_info {
94 unsigned int n_ports;
95 unsigned long port_flags;
96} k2_board_info[] = {
97 /* board_svw4 */
98 { 4, K2_FLAG_NO_ATAPI_DMA },
99
100 /* board_svw8 */
101 { 8, K2_FLAG_NO_ATAPI_DMA },
102};
103
104static u8 k2_stat_check_status(struct ata_port *ap); 95static u8 k2_stat_check_status(struct ata_port *ap);
105 96
106 97
@@ -354,7 +345,6 @@ static const struct ata_port_operations k2_sata_ops = {
354 .thaw = ata_bmdma_thaw, 345 .thaw = ata_bmdma_thaw,
355 .error_handler = ata_bmdma_error_handler, 346 .error_handler = ata_bmdma_error_handler,
356 .post_internal_cmd = ata_bmdma_post_internal_cmd, 347 .post_internal_cmd = ata_bmdma_post_internal_cmd,
357 .irq_handler = ata_interrupt,
358 .irq_clear = ata_bmdma_irq_clear, 348 .irq_clear = ata_bmdma_irq_clear,
359 .irq_on = ata_irq_on, 349 .irq_on = ata_irq_on,
360 .irq_ack = ata_irq_ack, 350 .irq_ack = ata_irq_ack,
@@ -363,6 +353,28 @@ static const struct ata_port_operations k2_sata_ops = {
363 .port_start = ata_port_start, 353 .port_start = ata_port_start,
364}; 354};
365 355
356static const struct ata_port_info k2_port_info[] = {
357 /* board_svw4 */
358 {
359 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
360 ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA,
361 .pio_mask = 0x1f,
362 .mwdma_mask = 0x07,
363 .udma_mask = 0x7f,
364 .port_ops = &k2_sata_ops,
365 },
366 /* board_svw8 */
367 {
368 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
369 ATA_FLAG_MMIO | K2_FLAG_NO_ATAPI_DMA |
370 K2_FLAG_SATA_8_PORTS,
371 .pio_mask = 0x1f,
372 .mwdma_mask = 0x07,
373 .udma_mask = 0x7f,
374 .port_ops = &k2_sata_ops,
375 },
376};
377
366static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) 378static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
367{ 379{
368 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; 380 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
@@ -386,17 +398,24 @@ static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
386static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 398static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
387{ 399{
388 static int printed_version; 400 static int printed_version;
389 struct device *dev = &pdev->dev; 401 const struct ata_port_info *ppi[] =
390 struct ata_probe_ent *probe_ent; 402 { &k2_port_info[ent->driver_data], NULL };
403 struct ata_host *host;
391 void __iomem *mmio_base; 404 void __iomem *mmio_base;
392 const struct k2_board_info *board_info = 405 int n_ports, i, rc;
393 &k2_board_info[ent->driver_data];
394 int rc;
395 int i;
396 406
397 if (!printed_version++) 407 if (!printed_version++)
398 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 408 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
399 409
410 /* allocate host */
411 n_ports = 4;
412 if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
413 n_ports = 8;
414
415 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
416 if (!host)
417 return -ENOMEM;
418
400 /* 419 /*
401 * If this driver happens to only be useful on Apple's K2, then 420 * If this driver happens to only be useful on Apple's K2, then
402 * we should check that here as it has a normal Serverworks ID 421 * we should check that here as it has a normal Serverworks ID
@@ -404,6 +423,7 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
404 rc = pcim_enable_device(pdev); 423 rc = pcim_enable_device(pdev);
405 if (rc) 424 if (rc)
406 return rc; 425 return rc;
426
407 /* 427 /*
408 * Check if we have resources mapped at all (second function may 428 * Check if we have resources mapped at all (second function may
409 * have been disabled by firmware) 429 * have been disabled by firmware)
@@ -417,6 +437,15 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
417 pcim_pin_device(pdev); 437 pcim_pin_device(pdev);
418 if (rc) 438 if (rc)
419 return rc; 439 return rc;
440 host->iomap = pcim_iomap_table(pdev);
441 mmio_base = host->iomap[5];
442
443 /* different controllers have different number of ports - currently 4 or 8 */
444 /* All ports are on the same function. Multi-function device is no
445 * longer available. This should not be seen in any system. */
446 for (i = 0; i < host->n_ports; i++)
447 k2_sata_setup_port(&host->ports[i]->ioaddr,
448 mmio_base + i * K2_SATA_PORT_OFFSET);
420 449
421 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 450 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
422 if (rc) 451 if (rc)
@@ -425,38 +454,6 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
425 if (rc) 454 if (rc)
426 return rc; 455 return rc;
427 456
428 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
429 if (probe_ent == NULL)
430 return -ENOMEM;
431
432 probe_ent->dev = pci_dev_to_dev(pdev);
433 INIT_LIST_HEAD(&probe_ent->node);
434
435 probe_ent->sht = &k2_sata_sht;
436 probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
437 ATA_FLAG_MMIO | board_info->port_flags;
438 probe_ent->port_ops = &k2_sata_ops;
439 probe_ent->n_ports = 4;
440 probe_ent->irq = pdev->irq;
441 probe_ent->irq_flags = IRQF_SHARED;
442 probe_ent->iomap = pcim_iomap_table(pdev);
443
444 /* We don't care much about the PIO/UDMA masks, but the core won't like us
445 * if we don't fill these
446 */
447 probe_ent->pio_mask = 0x1f;
448 probe_ent->mwdma_mask = 0x7;
449 probe_ent->udma_mask = 0x7f;
450
451 mmio_base = probe_ent->iomap[5];
452
453 /* different controllers have different number of ports - currently 4 or 8 */
454 /* All ports are on the same function. Multi-function device is no
455 * longer available. This should not be seen in any system. */
456 for (i = 0; i < board_info->n_ports; i++)
457 k2_sata_setup_port(&probe_ent->port[i],
458 mmio_base + i * K2_SATA_PORT_OFFSET);
459
460 /* Clear a magic bit in SCR1 according to Darwin, those help 457 /* Clear a magic bit in SCR1 according to Darwin, those help
461 * some funky seagate drives (though so far, those were already 458 * some funky seagate drives (though so far, those were already
462 * set by the firmware on the machines I had access to) 459 * set by the firmware on the machines I had access to)
@@ -469,12 +466,8 @@ static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *e
469 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); 466 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
470 467
471 pci_set_master(pdev); 468 pci_set_master(pdev);
472 469 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
473 if (!ata_device_add(probe_ent)) 470 &k2_sata_sht);
474 return -ENODEV;
475
476 devm_kfree(dev, probe_ent);
477 return 0;
478} 471}
479 472
480/* 0x240 is device ID for Apple K2 device 473/* 0x240 is device ID for Apple K2 device
diff --git a/drivers/ata/sata_sx4.c b/drivers/ata/sata_sx4.c
index 1a081c3a8c06..3a4f44559d0a 100644
--- a/drivers/ata/sata_sx4.c
+++ b/drivers/ata/sata_sx4.c
@@ -151,24 +151,23 @@ struct pdc_host_priv {
151 151
152 152
153static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 153static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
154static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance);
155static void pdc_eng_timeout(struct ata_port *ap); 154static void pdc_eng_timeout(struct ata_port *ap);
156static void pdc_20621_phy_reset (struct ata_port *ap); 155static void pdc_20621_phy_reset (struct ata_port *ap);
157static int pdc_port_start(struct ata_port *ap); 156static int pdc_port_start(struct ata_port *ap);
158static void pdc20621_qc_prep(struct ata_queued_cmd *qc); 157static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
159static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 158static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
160static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); 159static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
161static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe); 160static unsigned int pdc20621_dimm_init(struct ata_host *host);
162static int pdc20621_detect_dimm(struct ata_probe_ent *pe); 161static int pdc20621_detect_dimm(struct ata_host *host);
163static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, 162static unsigned int pdc20621_i2c_read(struct ata_host *host,
164 u32 device, u32 subaddr, u32 *pdata); 163 u32 device, u32 subaddr, u32 *pdata);
165static int pdc20621_prog_dimm0(struct ata_probe_ent *pe); 164static int pdc20621_prog_dimm0(struct ata_host *host);
166static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe); 165static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
167#ifdef ATA_VERBOSE_DEBUG 166#ifdef ATA_VERBOSE_DEBUG
168static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, 167static void pdc20621_get_from_dimm(struct ata_host *host,
169 void *psource, u32 offset, u32 size); 168 void *psource, u32 offset, u32 size);
170#endif 169#endif
171static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, 170static void pdc20621_put_to_dimm(struct ata_host *host,
172 void *psource, u32 offset, u32 size); 171 void *psource, u32 offset, u32 size);
173static void pdc20621_irq_clear(struct ata_port *ap); 172static void pdc20621_irq_clear(struct ata_port *ap);
174static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc); 173static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
@@ -204,7 +203,6 @@ static const struct ata_port_operations pdc_20621_ops = {
204 .qc_issue = pdc20621_qc_issue_prot, 203 .qc_issue = pdc20621_qc_issue_prot,
205 .data_xfer = ata_data_xfer, 204 .data_xfer = ata_data_xfer,
206 .eng_timeout = pdc_eng_timeout, 205 .eng_timeout = pdc_eng_timeout,
207 .irq_handler = pdc20621_interrupt,
208 .irq_clear = pdc20621_irq_clear, 206 .irq_clear = pdc20621_irq_clear,
209 .irq_on = ata_irq_on, 207 .irq_on = ata_irq_on,
210 .irq_ack = ata_irq_ack, 208 .irq_ack = ata_irq_ack,
@@ -214,7 +212,6 @@ static const struct ata_port_operations pdc_20621_ops = {
214static const struct ata_port_info pdc_port_info[] = { 212static const struct ata_port_info pdc_port_info[] = {
215 /* board_20621 */ 213 /* board_20621 */
216 { 214 {
217 .sht = &pdc_sata_sht,
218 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 215 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
219 ATA_FLAG_SRST | ATA_FLAG_MMIO | 216 ATA_FLAG_SRST | ATA_FLAG_MMIO |
220 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING, 217 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
@@ -882,15 +879,15 @@ static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
882 879
883 880
884#ifdef ATA_VERBOSE_DEBUG 881#ifdef ATA_VERBOSE_DEBUG
885static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource, 882static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
886 u32 offset, u32 size) 883 u32 offset, u32 size)
887{ 884{
888 u32 window_size; 885 u32 window_size;
889 u16 idx; 886 u16 idx;
890 u8 page_mask; 887 u8 page_mask;
891 long dist; 888 long dist;
892 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 889 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
893 void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR]; 890 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
894 891
895 /* hard-code chip #0 */ 892 /* hard-code chip #0 */
896 mmio += PDC_CHIP0_OFS; 893 mmio += PDC_CHIP0_OFS;
@@ -937,15 +934,15 @@ static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
937#endif 934#endif
938 935
939 936
940static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource, 937static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
941 u32 offset, u32 size) 938 u32 offset, u32 size)
942{ 939{
943 u32 window_size; 940 u32 window_size;
944 u16 idx; 941 u16 idx;
945 u8 page_mask; 942 u8 page_mask;
946 long dist; 943 long dist;
947 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 944 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
948 void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR]; 945 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
949 946
950 /* hard-code chip #0 */ 947 /* hard-code chip #0 */
951 mmio += PDC_CHIP0_OFS; 948 mmio += PDC_CHIP0_OFS;
@@ -987,10 +984,10 @@ static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
987} 984}
988 985
989 986
990static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device, 987static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
991 u32 subaddr, u32 *pdata) 988 u32 subaddr, u32 *pdata)
992{ 989{
993 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 990 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
994 u32 i2creg = 0; 991 u32 i2creg = 0;
995 u32 status; 992 u32 status;
996 u32 count =0; 993 u32 count =0;
@@ -1023,17 +1020,17 @@ static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1023} 1020}
1024 1021
1025 1022
1026static int pdc20621_detect_dimm(struct ata_probe_ent *pe) 1023static int pdc20621_detect_dimm(struct ata_host *host)
1027{ 1024{
1028 u32 data=0 ; 1025 u32 data=0 ;
1029 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 1026 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1030 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) { 1027 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1031 if (data == 100) 1028 if (data == 100)
1032 return 100; 1029 return 100;
1033 } else 1030 } else
1034 return 0; 1031 return 0;
1035 1032
1036 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) { 1033 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1037 if(data <= 0x75) 1034 if(data <= 0x75)
1038 return 133; 1035 return 133;
1039 } else 1036 } else
@@ -1043,13 +1040,13 @@ static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1043} 1040}
1044 1041
1045 1042
1046static int pdc20621_prog_dimm0(struct ata_probe_ent *pe) 1043static int pdc20621_prog_dimm0(struct ata_host *host)
1047{ 1044{
1048 u32 spd0[50]; 1045 u32 spd0[50];
1049 u32 data = 0; 1046 u32 data = 0;
1050 int size, i; 1047 int size, i;
1051 u8 bdimmsize; 1048 u8 bdimmsize;
1052 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 1049 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1053 static const struct { 1050 static const struct {
1054 unsigned int reg; 1051 unsigned int reg;
1055 unsigned int ofs; 1052 unsigned int ofs;
@@ -1072,7 +1069,7 @@ static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1072 mmio += PDC_CHIP0_OFS; 1069 mmio += PDC_CHIP0_OFS;
1073 1070
1074 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++) 1071 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1075 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 1072 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1076 pdc_i2c_read_data[i].reg, 1073 pdc_i2c_read_data[i].reg,
1077 &spd0[pdc_i2c_read_data[i].ofs]); 1074 &spd0[pdc_i2c_read_data[i].ofs]);
1078 1075
@@ -1108,11 +1105,11 @@ static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1108} 1105}
1109 1106
1110 1107
1111static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe) 1108static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
1112{ 1109{
1113 u32 data, spd0; 1110 u32 data, spd0;
1114 int error, i; 1111 int error, i;
1115 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 1112 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1116 1113
1117 /* hard-code chip #0 */ 1114 /* hard-code chip #0 */
1118 mmio += PDC_CHIP0_OFS; 1115 mmio += PDC_CHIP0_OFS;
@@ -1129,7 +1126,7 @@ static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1129 readl(mmio + PDC_SDRAM_CONTROL_OFFSET); 1126 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1130 1127
1131 /* Turn on for ECC */ 1128 /* Turn on for ECC */
1132 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 1129 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1133 PDC_DIMM_SPD_TYPE, &spd0); 1130 PDC_DIMM_SPD_TYPE, &spd0);
1134 if (spd0 == 0x02) { 1131 if (spd0 == 0x02) {
1135 data |= (0x01 << 16); 1132 data |= (0x01 << 16);
@@ -1156,7 +1153,7 @@ static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1156} 1153}
1157 1154
1158 1155
1159static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe) 1156static unsigned int pdc20621_dimm_init(struct ata_host *host)
1160{ 1157{
1161 int speed, size, length; 1158 int speed, size, length;
1162 u32 addr,spd0,pci_status; 1159 u32 addr,spd0,pci_status;
@@ -1166,7 +1163,7 @@ static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1166 u32 ticks=0; 1163 u32 ticks=0;
1167 u32 clock=0; 1164 u32 clock=0;
1168 u32 fparam=0; 1165 u32 fparam=0;
1169 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 1166 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1170 1167
1171 /* hard-code chip #0 */ 1168 /* hard-code chip #0 */
1172 mmio += PDC_CHIP0_OFS; 1169 mmio += PDC_CHIP0_OFS;
@@ -1225,18 +1222,18 @@ static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1225 Read SPD of DIMM by I2C interface, 1222 Read SPD of DIMM by I2C interface,
1226 and program the DIMM Module Controller. 1223 and program the DIMM Module Controller.
1227 */ 1224 */
1228 if (!(speed = pdc20621_detect_dimm(pe))) { 1225 if (!(speed = pdc20621_detect_dimm(host))) {
1229 printk(KERN_ERR "Detect Local DIMM Fail\n"); 1226 printk(KERN_ERR "Detect Local DIMM Fail\n");
1230 return 1; /* DIMM error */ 1227 return 1; /* DIMM error */
1231 } 1228 }
1232 VPRINTK("Local DIMM Speed = %d\n", speed); 1229 VPRINTK("Local DIMM Speed = %d\n", speed);
1233 1230
1234 /* Programming DIMM0 Module Control Register (index_CID0:80h) */ 1231 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1235 size = pdc20621_prog_dimm0(pe); 1232 size = pdc20621_prog_dimm0(host);
1236 VPRINTK("Local DIMM Size = %dMB\n",size); 1233 VPRINTK("Local DIMM Size = %dMB\n",size);
1237 1234
1238 /* Programming DIMM Module Global Control Register (index_CID0:88h) */ 1235 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1239 if (pdc20621_prog_dimm_global(pe)) { 1236 if (pdc20621_prog_dimm_global(host)) {
1240 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n"); 1237 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1241 return 1; 1238 return 1;
1242 } 1239 }
@@ -1249,20 +1246,20 @@ static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1249 '9','8','0','3','1','6','1','2',0,0}; 1246 '9','8','0','3','1','6','1','2',0,0};
1250 u8 test_parttern2[40] = {0}; 1247 u8 test_parttern2[40] = {0};
1251 1248
1252 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40); 1249 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x10040, 40);
1253 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40); 1250 pdc20621_put_to_dimm(host, (void *) test_parttern2, 0x40, 40);
1254 1251
1255 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40); 1252 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x10040, 40);
1256 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40); 1253 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
1257 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], 1254 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1258 test_parttern2[1], &(test_parttern2[2])); 1255 test_parttern2[1], &(test_parttern2[2]));
1259 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040, 1256 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x10040,
1260 40); 1257 40);
1261 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], 1258 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1262 test_parttern2[1], &(test_parttern2[2])); 1259 test_parttern2[1], &(test_parttern2[2]));
1263 1260
1264 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40); 1261 pdc20621_put_to_dimm(host, (void *) test_parttern1, 0x40, 40);
1265 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40); 1262 pdc20621_get_from_dimm(host, (void *) test_parttern2, 0x40, 40);
1266 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0], 1263 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1267 test_parttern2[1], &(test_parttern2[2])); 1264 test_parttern2[1], &(test_parttern2[2]));
1268 } 1265 }
@@ -1270,14 +1267,14 @@ static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1270 1267
1271 /* ECC initiliazation. */ 1268 /* ECC initiliazation. */
1272 1269
1273 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 1270 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1274 PDC_DIMM_SPD_TYPE, &spd0); 1271 PDC_DIMM_SPD_TYPE, &spd0);
1275 if (spd0 == 0x02) { 1272 if (spd0 == 0x02) {
1276 VPRINTK("Start ECC initialization\n"); 1273 VPRINTK("Start ECC initialization\n");
1277 addr = 0; 1274 addr = 0;
1278 length = size * 1024 * 1024; 1275 length = size * 1024 * 1024;
1279 while (addr < length) { 1276 while (addr < length) {
1280 pdc20621_put_to_dimm(pe, (void *) &tmp, addr, 1277 pdc20621_put_to_dimm(host, (void *) &tmp, addr,
1281 sizeof(u32)); 1278 sizeof(u32));
1282 addr += sizeof(u32); 1279 addr += sizeof(u32);
1283 } 1280 }
@@ -1287,10 +1284,10 @@ static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1287} 1284}
1288 1285
1289 1286
1290static void pdc_20621_init(struct ata_probe_ent *pe) 1287static void pdc_20621_init(struct ata_host *host)
1291{ 1288{
1292 u32 tmp; 1289 u32 tmp;
1293 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR]; 1290 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1294 1291
1295 /* hard-code chip #0 */ 1292 /* hard-code chip #0 */
1296 mmio += PDC_CHIP0_OFS; 1293 mmio += PDC_CHIP0_OFS;
@@ -1321,15 +1318,25 @@ static void pdc_20621_init(struct ata_probe_ent *pe)
1321static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1318static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1322{ 1319{
1323 static int printed_version; 1320 static int printed_version;
1324 struct ata_probe_ent *probe_ent; 1321 const struct ata_port_info *ppi[] =
1322 { &pdc_port_info[ent->driver_data], NULL };
1323 struct ata_host *host;
1325 void __iomem *base; 1324 void __iomem *base;
1326 struct pdc_host_priv *hpriv; 1325 struct pdc_host_priv *hpriv;
1327 unsigned int board_idx = (unsigned int) ent->driver_data;
1328 int rc; 1326 int rc;
1329 1327
1330 if (!printed_version++) 1328 if (!printed_version++)
1331 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 1329 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1332 1330
1331 /* allocate host */
1332 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
1333 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1334 if (!host || !hpriv)
1335 return -ENOMEM;
1336
1337 host->private_data = hpriv;
1338
1339 /* acquire resources and fill host */
1333 rc = pcim_enable_device(pdev); 1340 rc = pcim_enable_device(pdev);
1334 if (rc) 1341 if (rc)
1335 return rc; 1342 return rc;
@@ -1340,7 +1347,15 @@ static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *
1340 pcim_pin_device(pdev); 1347 pcim_pin_device(pdev);
1341 if (rc) 1348 if (rc)
1342 return rc; 1349 return rc;
1350 host->iomap = pcim_iomap_table(pdev);
1351
1352 base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1353 pdc_sata_setup_port(&host->ports[0]->ioaddr, base + 0x200);
1354 pdc_sata_setup_port(&host->ports[1]->ioaddr, base + 0x280);
1355 pdc_sata_setup_port(&host->ports[2]->ioaddr, base + 0x300);
1356 pdc_sata_setup_port(&host->ports[3]->ioaddr, base + 0x380);
1343 1357
1358 /* configure and activate */
1344 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 1359 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1345 if (rc) 1360 if (rc)
1346 return rc; 1361 return rc;
@@ -1348,50 +1363,13 @@ static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *
1348 if (rc) 1363 if (rc)
1349 return rc; 1364 return rc;
1350 1365
1351 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL); 1366 if (pdc20621_dimm_init(host))
1352 if (probe_ent == NULL)
1353 return -ENOMEM; 1367 return -ENOMEM;
1354 1368 pdc_20621_init(host);
1355 probe_ent->dev = pci_dev_to_dev(pdev);
1356 INIT_LIST_HEAD(&probe_ent->node);
1357
1358 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1359 if (!hpriv)
1360 return -ENOMEM;
1361
1362 probe_ent->sht = pdc_port_info[board_idx].sht;
1363 probe_ent->port_flags = pdc_port_info[board_idx].flags;
1364 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1365 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
1366 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1367 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1368
1369 probe_ent->irq = pdev->irq;
1370 probe_ent->irq_flags = IRQF_SHARED;
1371 probe_ent->iomap = pcim_iomap_table(pdev);
1372
1373 probe_ent->private_data = hpriv;
1374 base = probe_ent->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1375
1376 probe_ent->n_ports = 4;
1377 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1378 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1379 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1380 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1381 1369
1382 pci_set_master(pdev); 1370 pci_set_master(pdev);
1383 1371 return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
1384 /* initialize adapter */ 1372 IRQF_SHARED, &pdc_sata_sht);
1385 /* initialize local dimm */
1386 if (pdc20621_dimm_init(probe_ent))
1387 return -ENOMEM;
1388 pdc_20621_init(probe_ent);
1389
1390 if (!ata_device_add(probe_ent))
1391 return -ENODEV;
1392
1393 devm_kfree(&pdev->dev, probe_ent);
1394 return 0;
1395} 1373}
1396 1374
1397 1375
diff --git a/drivers/ata/sata_vsc.c b/drivers/ata/sata_vsc.c
index 170bad1b415b..80126f835d32 100644
--- a/drivers/ata/sata_vsc.c
+++ b/drivers/ata/sata_vsc.c
@@ -333,7 +333,6 @@ static const struct ata_port_operations vsc_sata_ops = {
333 .thaw = vsc_thaw, 333 .thaw = vsc_thaw,
334 .error_handler = ata_bmdma_error_handler, 334 .error_handler = ata_bmdma_error_handler,
335 .post_internal_cmd = ata_bmdma_post_internal_cmd, 335 .post_internal_cmd = ata_bmdma_post_internal_cmd,
336 .irq_handler = vsc_sata_interrupt,
337 .irq_clear = ata_bmdma_irq_clear, 336 .irq_clear = ata_bmdma_irq_clear,
338 .irq_on = ata_irq_on, 337 .irq_on = ata_irq_on,
339 .irq_ack = ata_irq_ack, 338 .irq_ack = ata_irq_ack,
@@ -367,30 +366,50 @@ static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
367 366
368static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 367static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
369{ 368{
369 static const struct ata_port_info pi = {
370 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
371 ATA_FLAG_MMIO,
372 .pio_mask = 0x1f,
373 .mwdma_mask = 0x07,
374 .udma_mask = 0x7f,
375 .port_ops = &vsc_sata_ops,
376 };
377 const struct ata_port_info *ppi[] = { &pi, NULL };
370 static int printed_version; 378 static int printed_version;
371 struct ata_probe_ent *probe_ent; 379 struct ata_host *host;
372 void __iomem *mmio_base; 380 void __iomem *mmio_base;
373 int rc; 381 int i, rc;
374 u8 cls; 382 u8 cls;
375 383
376 if (!printed_version++) 384 if (!printed_version++)
377 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 385 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
378 386
387 /* allocate host */
388 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
389 if (!host)
390 return -ENOMEM;
391
379 rc = pcim_enable_device(pdev); 392 rc = pcim_enable_device(pdev);
380 if (rc) 393 if (rc)
381 return rc; 394 return rc;
382 395
383 /* 396 /* check if we have needed resource mapped */
384 * Check if we have needed resource mapped.
385 */
386 if (pci_resource_len(pdev, 0) == 0) 397 if (pci_resource_len(pdev, 0) == 0)
387 return -ENODEV; 398 return -ENODEV;
388 399
400 /* map IO regions and intialize host accordingly */
389 rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME); 401 rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
390 if (rc == -EBUSY) 402 if (rc == -EBUSY)
391 pcim_pin_device(pdev); 403 pcim_pin_device(pdev);
392 if (rc) 404 if (rc)
393 return rc; 405 return rc;
406 host->iomap = pcim_iomap_table(pdev);
407
408 mmio_base = host->iomap[VSC_MMIO_BAR];
409
410 for (i = 0; i < host->n_ports; i++)
411 vsc_sata_setup_port(&host->ports[i]->ioaddr,
412 mmio_base + (i + 1) * VSC_SATA_PORT_OFFSET);
394 413
395 /* 414 /*
396 * Use 32 bit DMA mask, because 64 bit address support is poor. 415 * Use 32 bit DMA mask, because 64 bit address support is poor.
@@ -402,12 +421,6 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
402 if (rc) 421 if (rc)
403 return rc; 422 return rc;
404 423
405 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
406 if (probe_ent == NULL)
407 return -ENOMEM;
408 probe_ent->dev = pci_dev_to_dev(pdev);
409 INIT_LIST_HEAD(&probe_ent->node);
410
411 /* 424 /*
412 * Due to a bug in the chip, the default cache line size can't be 425 * Due to a bug in the chip, the default cache line size can't be
413 * used (unless the default is non-zero). 426 * used (unless the default is non-zero).
@@ -418,33 +431,6 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
418 431
419 if (pci_enable_msi(pdev) == 0) 432 if (pci_enable_msi(pdev) == 0)
420 pci_intx(pdev, 0); 433 pci_intx(pdev, 0);
421 else
422 probe_ent->irq_flags = IRQF_SHARED;
423
424 probe_ent->sht = &vsc_sata_sht;
425 probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
426 ATA_FLAG_MMIO;
427 probe_ent->port_ops = &vsc_sata_ops;
428 probe_ent->n_ports = 4;
429 probe_ent->irq = pdev->irq;
430 probe_ent->iomap = pcim_iomap_table(pdev);
431
432 /* We don't care much about the PIO/UDMA masks, but the core won't like us
433 * if we don't fill these
434 */
435 probe_ent->pio_mask = 0x1f;
436 probe_ent->mwdma_mask = 0x07;
437 probe_ent->udma_mask = 0x7f;
438
439 mmio_base = probe_ent->iomap[VSC_MMIO_BAR];
440
441 /* We have 4 ports per PCI function */
442 vsc_sata_setup_port(&probe_ent->port[0], mmio_base + 1 * VSC_SATA_PORT_OFFSET);
443 vsc_sata_setup_port(&probe_ent->port[1], mmio_base + 2 * VSC_SATA_PORT_OFFSET);
444 vsc_sata_setup_port(&probe_ent->port[2], mmio_base + 3 * VSC_SATA_PORT_OFFSET);
445 vsc_sata_setup_port(&probe_ent->port[3], mmio_base + 4 * VSC_SATA_PORT_OFFSET);
446
447 pci_set_master(pdev);
448 434
449 /* 435 /*
450 * Config offset 0x98 is "Extended Control and Status Register 0" 436 * Config offset 0x98 is "Extended Control and Status Register 0"
@@ -454,11 +440,9 @@ static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_d
454 */ 440 */
455 pci_write_config_dword(pdev, 0x98, 0); 441 pci_write_config_dword(pdev, 0x98, 0);
456 442
457 if (!ata_device_add(probe_ent)) 443 pci_set_master(pdev);
458 return -ENODEV; 444 return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
459 445 IRQF_SHARED, &vsc_sata_sht);
460 devm_kfree(&pdev->dev, probe_ent);
461 return 0;
462} 446}
463 447
464static const struct pci_device_id vsc_sata_pci_tbl[] = { 448static const struct pci_device_id vsc_sata_pci_tbl[] = {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 21:09:14 -0500