sh: Add SH7785 Highlander board support (R7785RP).

This adds preliminary support for the SH7785-based Highlander board.
Some of the Highlander support code is reordered so that most of it
can be reused directly.

This also plugs in missing SH7785 checks in the places that need it,
as this is the first board to support the CPU.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

2 files changed, 53 insertions, 7 deletions

diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 4b17f845f5cd..94deebda6da0 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -62,7 +62,7 @@ struct sci_port {
         unsigned int            type;
 
         /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
-        unsigned int            irqs[SCIx_NR_IRQS]; 
+        unsigned int            irqs[SCIx_NR_IRQS];
 
         /* Port pin configuration */
         void                    (*init_pins)(struct uart_port *port,
@@ -351,7 +351,7 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
         } else {
 #ifdef CONFIG_CPU_SUBTYPE_SH7343
                 /* Nothing */
-#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
                 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
 #else
                 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
@@ -361,7 +361,9 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
 }
 #endif
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
+#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7780) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7785)
 static inline int scif_txroom(struct uart_port *port)
 {
         return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
@@ -1368,9 +1370,19 @@ static int __devinit sci_probe(struct platform_device *dev)
         struct plat_sci_port *p = dev->dev.platform_data;
         int i;
 
-        for (i = 0; p && p->flags != 0 && i < SCI_NPORTS; p++, i++) {
+        for (i = 0; p && p->flags != 0; p++, i++) {
                 struct sci_port *sciport = &sci_ports[i];
 
+                /* Sanity check */
+                if (unlikely(i == SCI_NPORTS)) {
+                        dev_notice(&dev->dev, "Attempting to register port "
+                                   "%d when only %d are available.\n",
+                                   i+1, SCI_NPORTS);
+                        dev_notice(&dev->dev, "Consider bumping "
+                                   "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
+                        break;
+                }
+
                 sciport->port.mapbase   = p->mapbase;
 
                 /*
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 77f7d6351ab1..854153a1d60a 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -140,6 +140,16 @@
 # define SCIF_ORER      0x0001          /* Overrun error bit */
 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 # define SCIF_ONLY
+#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
+# define SCSPTR0        0xffea0024      /* 16 bit SCIF */
+# define SCSPTR1        0xffeb0024      /* 16 bit SCIF */
+# define SCSPTR2        0xffec0024      /* 16 bit SCIF */
+# define SCSPTR3        0xffed0024      /* 16 bit SCIF */
+# define SCSPTR4        0xffee0024      /* 16 bit SCIF */
+# define SCSPTR5        0xffef0024      /* 16 bit SCIF */
+# define SCIF_OPER      0x0001          /* Overrun error bit */
+# define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+# define SCIF_ONLY
 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
@@ -163,7 +173,10 @@
 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
-#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7780)
+#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7751) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7780) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7785)
 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 #else
 #define SCI_CTRL_FLAGS_REIE 0
@@ -385,7 +398,9 @@ SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
-#if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
+#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7780) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7785)
 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
@@ -576,6 +591,23 @@ static inline int sci_rxd_in(struct uart_port *port)
                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
         return 1;
 }
+#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
+static inline int sci_rxd_in(struct uart_port *port)
+{
+        if (port->mapbase == 0xffea0000)
+                return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
+        if (port->mapbase == 0xffeb0000)
+                return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
+        if (port->mapbase == 0xffec0000)
+                return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
+        if (port->mapbase == 0xffed0000)
+                return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
+        if (port->mapbase == 0xffee0000)
+                return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
+        if (port->mapbase == 0xffef0000)
+                return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
+        return 1;
+}
 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
 static inline int sci_rxd_in(struct uart_port *port)
 {
@@ -634,7 +666,9 @@ static inline int sci_rxd_in(struct uart_port *port)
  * -- Mitch Davis - 15 Jul 2000
  */
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7780)
+#if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7780) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7785)
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)