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authorMichael Chan <mchan@broadcom.com>2005-04-21 20:12:05 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2005-04-21 20:12:05 -0400
commite6af301be3c129adbc8a7c8ffb76e62533ad9575 (patch)
tree02b2fd5de20468f5966cf3e73fbfa5e6f86baa63 /drivers
parent361b4ac29bc651c7612d4bf21434ae6fe06b78e4 (diff)
[TG3]: Add nvram lock-out support for 5752 TPM
Add support for the NVRAM lock-out feature for TPM in 5752. If lock-out is enabled, certain NVRAM registers cannot be written to. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/tg3.c70
-rw-r--r--drivers/net/tg3.h1
2 files changed, 37 insertions, 34 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index dbdd3ecafdc1..301546425736 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -3732,6 +3732,28 @@ static void tg3_nvram_unlock(struct tg3 *tp)
3732} 3732}
3733 3733
3734/* tp->lock is held. */ 3734/* tp->lock is held. */
3735static void tg3_enable_nvram_access(struct tg3 *tp)
3736{
3737 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3738 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3739 u32 nvaccess = tr32(NVRAM_ACCESS);
3740
3741 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3742 }
3743}
3744
3745/* tp->lock is held. */
3746static void tg3_disable_nvram_access(struct tg3 *tp)
3747{
3748 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
3749 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
3750 u32 nvaccess = tr32(NVRAM_ACCESS);
3751
3752 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3753 }
3754}
3755
3756/* tp->lock is held. */
3735static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) 3757static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
3736{ 3758{
3737 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) 3759 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
@@ -7102,6 +7124,10 @@ static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
7102 7124
7103 nvcfg1 = tr32(NVRAM_CFG1); 7125 nvcfg1 = tr32(NVRAM_CFG1);
7104 7126
7127 /* NVRAM protection for TPM */
7128 if (nvcfg1 & (1 << 27))
7129 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
7130
7105 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { 7131 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
7106 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: 7132 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
7107 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: 7133 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
@@ -7179,11 +7205,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
7179 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { 7205 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
7180 tp->tg3_flags |= TG3_FLAG_NVRAM; 7206 tp->tg3_flags |= TG3_FLAG_NVRAM;
7181 7207
7182 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { 7208 tg3_enable_nvram_access(tp);
7183 u32 nvaccess = tr32(NVRAM_ACCESS);
7184
7185 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
7186 }
7187 7209
7188 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) 7210 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7189 tg3_get_5752_nvram_info(tp); 7211 tg3_get_5752_nvram_info(tp);
@@ -7192,11 +7214,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
7192 7214
7193 tg3_get_nvram_size(tp); 7215 tg3_get_nvram_size(tp);
7194 7216
7195 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { 7217 tg3_disable_nvram_access(tp);
7196 u32 nvaccess = tr32(NVRAM_ACCESS);
7197
7198 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
7199 }
7200 7218
7201 } else { 7219 } else {
7202 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); 7220 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
@@ -7285,11 +7303,7 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
7285 7303
7286 tg3_nvram_lock(tp); 7304 tg3_nvram_lock(tp);
7287 7305
7288 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { 7306 tg3_enable_nvram_access(tp);
7289 u32 nvaccess = tr32(NVRAM_ACCESS);
7290
7291 tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
7292 }
7293 7307
7294 tw32(NVRAM_ADDR, offset); 7308 tw32(NVRAM_ADDR, offset);
7295 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | 7309 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
@@ -7300,11 +7314,7 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
7300 7314
7301 tg3_nvram_unlock(tp); 7315 tg3_nvram_unlock(tp);
7302 7316
7303 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { 7317 tg3_disable_nvram_access(tp);
7304 u32 nvaccess = tr32(NVRAM_ACCESS);
7305
7306 tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
7307 }
7308 7318
7309 return ret; 7319 return ret;
7310} 7320}
@@ -7367,7 +7377,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
7367 7377
7368 while (len) { 7378 while (len) {
7369 int j; 7379 int j;
7370 u32 phy_addr, page_off, size, nvaccess; 7380 u32 phy_addr, page_off, size;
7371 7381
7372 phy_addr = offset & ~pagemask; 7382 phy_addr = offset & ~pagemask;
7373 7383
@@ -7390,8 +7400,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
7390 7400
7391 offset = offset + (pagesize - page_off); 7401 offset = offset + (pagesize - page_off);
7392 7402
7393 nvaccess = tr32(NVRAM_ACCESS); 7403 tg3_enable_nvram_access(tp);
7394 tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
7395 7404
7396 /* 7405 /*
7397 * Before we can erase the flash page, we need 7406 * Before we can erase the flash page, we need
@@ -7528,13 +7537,10 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
7528 7537
7529 tg3_nvram_lock(tp); 7538 tg3_nvram_lock(tp);
7530 7539
7531 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { 7540 tg3_enable_nvram_access(tp);
7532 u32 nvaccess = tr32(NVRAM_ACCESS); 7541 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7533 7542 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
7534 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
7535
7536 tw32(NVRAM_WRITE1, 0x406); 7543 tw32(NVRAM_WRITE1, 0x406);
7537 }
7538 7544
7539 grc_mode = tr32(GRC_MODE); 7545 grc_mode = tr32(GRC_MODE);
7540 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); 7546 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
@@ -7553,11 +7559,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
7553 grc_mode = tr32(GRC_MODE); 7559 grc_mode = tr32(GRC_MODE);
7554 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); 7560 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
7555 7561
7556 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { 7562 tg3_disable_nvram_access(tp);
7557 u32 nvaccess = tr32(NVRAM_ACCESS);
7558
7559 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
7560 }
7561 tg3_nvram_unlock(tp); 7563 tg3_nvram_unlock(tp);
7562 } 7564 }
7563 7565
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 261c2db7ce17..d3f03f0f4c46 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2122,6 +2122,7 @@ struct tg3 {
2122#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000 2122#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
2123#define TG3_FLG2_5705_PLUS 0x00040000 2123#define TG3_FLG2_5705_PLUS 0x00040000
2124#define TG3_FLG2_5750_PLUS 0x00080000 2124#define TG3_FLG2_5750_PLUS 0x00080000
2125#define TG3_FLG2_PROTECTED_NVRAM 0x00100000
2125 2126
2126 u32 split_mode_max_reqs; 2127 u32 split_mode_max_reqs;
2127#define SPLIT_MODE_5704_MAX_REQ 3 2128#define SPLIT_MODE_5704_MAX_REQ 3