Merge commit 'origin/master' into next

730 files changed, 114224 insertions, 10761 deletions

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 00cf9553f740..a442c8f29fc1 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -104,6 +104,8 @@ source "drivers/auxdisplay/Kconfig"
 
 source "drivers/uio/Kconfig"
 
+source "drivers/vlynq/Kconfig"
+
 source "drivers/xen/Kconfig"
 
 source "drivers/staging/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 9e7d4e56c85b..00b44f4ccf03 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -105,6 +105,7 @@ obj-$(CONFIG_PPC_PS3)		+= ps3/
 obj-$(CONFIG_OF)                += of/
 obj-$(CONFIG_SSB)               += ssb/
 obj-$(CONFIG_VIRTIO)            += virtio/
+obj-$(CONFIG_VLYNQ)             += vlynq/
 obj-$(CONFIG_STAGING)           += staging/
 obj-y                           += platform/
 obj-y                           += ieee802154/
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 1977d4beb89e..7ecb1938e590 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -22,6 +22,7 @@
 #include <linux/kallsyms.h>
 #include <linux/semaphore.h>
 #include <linux/mutex.h>
+#include <linux/async.h>
 
 #include "base.h"
 #include "power/power.h"
@@ -161,10 +162,18 @@ static int dev_uevent(struct kset *kset, struct kobject *kobj,
         struct device *dev = to_dev(kobj);
         int retval = 0;
 
-        /* add the major/minor if present */
+        /* add device node properties if present */
         if (MAJOR(dev->devt)) {
+                const char *tmp;
+                const char *name;
+
                 add_uevent_var(env, "MAJOR=%u", MAJOR(dev->devt));
                 add_uevent_var(env, "MINOR=%u", MINOR(dev->devt));
+                name = device_get_nodename(dev, &tmp);
+                if (name) {
+                        add_uevent_var(env, "DEVNAME=%s", name);
+                        kfree(tmp);
+                }
         }
 
         if (dev->type && dev->type->name)
@@ -874,7 +883,7 @@ int device_add(struct device *dev)
          * the name, and force the use of dev_name()
          */
         if (dev->init_name) {
-                dev_set_name(dev, dev->init_name);
+                dev_set_name(dev, "%s", dev->init_name);
                 dev->init_name = NULL;
         }
 
@@ -1128,6 +1137,47 @@ static struct device *next_device(struct klist_iter *i)
 }
 
 /**
+ * device_get_nodename - path of device node file
+ * @dev: device
+ * @tmp: possibly allocated string
+ *
+ * Return the relative path of a possible device node.
+ * Non-default names may need to allocate a memory to compose
+ * a name. This memory is returned in tmp and needs to be
+ * freed by the caller.
+ */
+const char *device_get_nodename(struct device *dev, const char **tmp)
+{
+        char *s;
+
+        *tmp = NULL;
+
+        /* the device type may provide a specific name */
+        if (dev->type && dev->type->nodename)
+                *tmp = dev->type->nodename(dev);
+        if (*tmp)
+                return *tmp;
+
+        /* the class may provide a specific name */
+        if (dev->class && dev->class->nodename)
+                *tmp = dev->class->nodename(dev);
+        if (*tmp)
+                return *tmp;
+
+        /* return name without allocation, tmp == NULL */
+        if (strchr(dev_name(dev), '!') == NULL)
+                return dev_name(dev);
+
+        /* replace '!' in the name with '/' */
+        *tmp = kstrdup(dev_name(dev), GFP_KERNEL);
+        if (!*tmp)
+                return NULL;
+        while ((s = strchr(*tmp, '!')))
+                s[0] = '/';
+        return *tmp;
+}
+
+/**
  * device_for_each_child - device child iterator.
  * @parent: parent struct device.
  * @data: data for the callback.
@@ -1271,7 +1321,7 @@ struct device *__root_device_register(const char *name, struct module *owner)
         if (!root)
                 return ERR_PTR(err);
 
-        err = dev_set_name(&root->dev, name);
+        err = dev_set_name(&root->dev, "%s", name);
         if (err) {
                 kfree(root);
                 return ERR_PTR(err);
@@ -1665,4 +1715,5 @@ void device_shutdown(void)
         kobject_put(sysfs_dev_char_kobj);
         kobject_put(sysfs_dev_block_kobj);
         kobject_put(dev_kobj);
+        async_synchronize_full();
 }
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index 742cbe6b042b..f0106875f01d 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -226,7 +226,7 @@ static int __device_attach(struct device_driver *drv, void *data)
  * pair is found, break out and return.
  *
  * Returns 1 if the device was bound to a driver;
- * 0 if no matching device was found;
+ * 0 if no matching driver was found;
  * -ENODEV if the device is not registered.
  *
  * When called for a USB interface, @dev->parent->sem must be held.
@@ -320,6 +320,10 @@ static void __device_release_driver(struct device *dev)
                 devres_release_all(dev);
                 dev->driver = NULL;
                 klist_remove(&dev->p->knode_driver);
+                if (dev->bus)
+                        blocking_notifier_call_chain(&dev->bus->p->bus_notifier,
+                                                     BUS_NOTIFY_UNBOUND_DRIVER,
+                                                     dev);
         }
 }
 
diff --git a/drivers/base/firmware_class.c b/drivers/base/firmware_class.c
index 8a267c427629..ddeb819c8f87 100644
--- a/drivers/base/firmware_class.c
+++ b/drivers/base/firmware_class.c
@@ -40,7 +40,7 @@ static int loading_timeout = 60;	/* In seconds */
 static DEFINE_MUTEX(fw_lock);
 
 struct firmware_priv {
-        char fw_id[FIRMWARE_NAME_MAX];
+        char *fw_id;
         struct completion completion;
         struct bin_attribute attr_data;
         struct firmware *fw;
@@ -355,8 +355,9 @@ static void fw_dev_release(struct device *dev)
         for (i = 0; i < fw_priv->nr_pages; i++)
                 __free_page(fw_priv->pages[i]);
         kfree(fw_priv->pages);
+        kfree(fw_priv->fw_id);
         kfree(fw_priv);
-        kfree(dev);
+        put_device(dev);
 
         module_put(THIS_MODULE);
 }
@@ -386,13 +387,19 @@ static int fw_register_device(struct device **dev_p, const char *fw_name,
 
         init_completion(&fw_priv->completion);
         fw_priv->attr_data = firmware_attr_data_tmpl;
-        strlcpy(fw_priv->fw_id, fw_name, FIRMWARE_NAME_MAX);
+        fw_priv->fw_id = kstrdup(fw_name, GFP_KERNEL);
+        if (!fw_priv->fw_id) {
+                dev_err(device, "%s: Firmware name allocation failed\n",
+                        __func__);
+                retval = -ENOMEM;
+                goto error_kfree;
+        }
 
         fw_priv->timeout.function = firmware_class_timeout;
         fw_priv->timeout.data = (u_long) fw_priv;
         init_timer(&fw_priv->timeout);
 
-        dev_set_name(f_dev, dev_name(device));
+        dev_set_name(f_dev, "%s", dev_name(device));
         f_dev->parent = device;
         f_dev->class = &firmware_class;
         dev_set_drvdata(f_dev, fw_priv);
@@ -400,14 +407,17 @@ static int fw_register_device(struct device **dev_p, const char *fw_name,
         retval = device_register(f_dev);
         if (retval) {
                 dev_err(device, "%s: device_register failed\n", __func__);
-                goto error_kfree;
+                put_device(f_dev);
+                goto error_kfree_fw_id;
         }
         *dev_p = f_dev;
         return 0;
 
+error_kfree_fw_id:
+        kfree(fw_priv->fw_id);
 error_kfree:
-        kfree(fw_priv);
         kfree(f_dev);
+        kfree(fw_priv);
         return retval;
 }
 
@@ -615,8 +625,9 @@ request_firmware_work_func(void *arg)
  * @cont: function will be called asynchronously when the firmware
  *      request is over.
  *
- *      Asynchronous variant of request_firmware() for contexts where
- *      it is not possible to sleep.
+ *      Asynchronous variant of request_firmware() for user contexts where
+ *      it is not possible to sleep for long time. It can't be called
+ *      in atomic contexts.
  **/
 int
 request_firmware_nowait(
diff --git a/drivers/base/node.c b/drivers/base/node.c
index 40b809742a1c..91d4087b4039 100644
--- a/drivers/base/node.c
+++ b/drivers/base/node.c
@@ -72,10 +72,8 @@ static ssize_t node_read_meminfo(struct sys_device * dev,
                        "Node %d Inactive(anon): %8lu kB\n"
                        "Node %d Active(file):   %8lu kB\n"
                        "Node %d Inactive(file): %8lu kB\n"
-#ifdef CONFIG_UNEVICTABLE_LRU
                        "Node %d Unevictable:    %8lu kB\n"
                        "Node %d Mlocked:        %8lu kB\n"
-#endif
 #ifdef CONFIG_HIGHMEM
                        "Node %d HighTotal:      %8lu kB\n"
                        "Node %d HighFree:       %8lu kB\n"
@@ -105,10 +103,8 @@ static ssize_t node_read_meminfo(struct sys_device * dev,
                        nid, K(node_page_state(nid, NR_INACTIVE_ANON)),
                        nid, K(node_page_state(nid, NR_ACTIVE_FILE)),
                        nid, K(node_page_state(nid, NR_INACTIVE_FILE)),
-#ifdef CONFIG_UNEVICTABLE_LRU
                        nid, K(node_page_state(nid, NR_UNEVICTABLE)),
                        nid, K(node_page_state(nid, NR_MLOCK)),
-#endif
 #ifdef CONFIG_HIGHMEM
                        nid, K(i.totalhigh),
                        nid, K(i.freehigh),
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index ead3f64c41d0..81cb01bfc356 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -69,7 +69,8 @@ EXPORT_SYMBOL_GPL(platform_get_irq);
  * @name: resource name
  */
 struct resource *platform_get_resource_byname(struct platform_device *dev,
-                                              unsigned int type, char *name)
+                                              unsigned int type,
+                                              const char *name)
 {
         int i;
 
@@ -88,7 +89,7 @@ EXPORT_SYMBOL_GPL(platform_get_resource_byname);
  * @dev: platform device
  * @name: IRQ name
  */
-int platform_get_irq_byname(struct platform_device *dev, char *name)
+int platform_get_irq_byname(struct platform_device *dev, const char *name)
 {
         struct resource *r = platform_get_resource_byname(dev, IORESOURCE_IRQ,
                                                           name);
@@ -244,7 +245,7 @@ int platform_device_add(struct platform_device *pdev)
         if (pdev->id != -1)
                 dev_set_name(&pdev->dev, "%s.%d", pdev->name,  pdev->id);
         else
-                dev_set_name(&pdev->dev, pdev->name);
+                dev_set_name(&pdev->dev, "%s", pdev->name);
 
         for (i = 0; i < pdev->num_resources; i++) {
                 struct resource *p, *r = &pdev->resource[i];
diff --git a/drivers/base/sys.c b/drivers/base/sys.c
index 9742a78c9fe4..79a9ae5238ac 100644
--- a/drivers/base/sys.c
+++ b/drivers/base/sys.c
@@ -131,6 +131,8 @@ static struct kset *system_kset;
 
 int sysdev_class_register(struct sysdev_class *cls)
 {
+        int retval;
+
         pr_debug("Registering sysdev class '%s'\n", cls->name);
 
         INIT_LIST_HEAD(&cls->drivers);
@@ -138,7 +140,11 @@ int sysdev_class_register(struct sysdev_class *cls)
         cls->kset.kobj.parent = &system_kset->kobj;
         cls->kset.kobj.ktype = &ktype_sysdev_class;
         cls->kset.kobj.kset = system_kset;
-        kobject_set_name(&cls->kset.kobj, cls->name);
+
+        retval = kobject_set_name(&cls->kset.kobj, "%s", cls->name);
+        if (retval)
+                return retval;
+
         return kset_register(&cls->kset);
 }
 
diff --git a/drivers/block/aoe/aoechr.c b/drivers/block/aoe/aoechr.c
index 200efc4d2c1e..19888354188f 100644
--- a/drivers/block/aoe/aoechr.c
+++ b/drivers/block/aoe/aoechr.c
@@ -266,6 +266,11 @@ static const struct file_operations aoe_fops = {
         .owner = THIS_MODULE,
 };
 
+static char *aoe_nodename(struct device *dev)
+{
+        return kasprintf(GFP_KERNEL, "etherd/%s", dev_name(dev));
+}
+
 int __init
 aoechr_init(void)
 {
@@ -283,6 +288,8 @@ aoechr_init(void)
                 unregister_chrdev(AOE_MAJOR, "aoechr");
                 return PTR_ERR(aoe_class);
         }
+        aoe_class->nodename = aoe_nodename;
+
         for (i = 0; i < ARRAY_SIZE(chardevs); ++i)
                 device_create(aoe_class, NULL,
                               MKDEV(AOE_MAJOR, chardevs[i].minor), NULL,
diff --git a/drivers/block/pktcdvd.c b/drivers/block/pktcdvd.c
index d57f11759480..83650e00632d 100644
--- a/drivers/block/pktcdvd.c
+++ b/drivers/block/pktcdvd.c
@@ -430,7 +430,7 @@ static void pkt_sysfs_cleanup(void)
 /********************************************************************
   entries in debugfs
 
-  /debugfs/pktcdvd[0-7]/
+  /sys/kernel/debug/pktcdvd[0-7]/
                         info
 
  *******************************************************************/
@@ -2855,6 +2855,11 @@ static struct block_device_operations pktcdvd_ops = {
         .media_changed =        pkt_media_changed,
 };
 
+static char *pktcdvd_nodename(struct gendisk *gd)
+{
+        return kasprintf(GFP_KERNEL, "pktcdvd/%s", gd->disk_name);
+}
+
 /*
  * Set up mapping from pktcdvd device to CD-ROM device.
  */
@@ -2907,6 +2912,7 @@ static int pkt_setup_dev(dev_t dev, dev_t* pkt_dev)
         disk->fops = &pktcdvd_ops;
         disk->flags = GENHD_FL_REMOVABLE;
         strcpy(disk->disk_name, pd->name);
+        disk->nodename = pktcdvd_nodename;
         disk->private_data = pd;
         disk->queue = blk_alloc_queue(GFP_KERNEL);
         if (!disk->queue)
@@ -3062,6 +3068,7 @@ static const struct file_operations pkt_ctl_fops = {
 static struct miscdevice pkt_misc = {
         .minor          = MISC_DYNAMIC_MINOR,
         .name           = DRIVER_NAME,
+        .name           = "pktcdvd/control",
         .fops           = &pkt_ctl_fops
 };
 
diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c
index c1996829d5ec..e53284767f7c 100644
--- a/drivers/block/xen-blkfront.c
+++ b/drivers/block/xen-blkfront.c
@@ -753,12 +753,12 @@ static int blkfront_probe(struct xenbus_device *dev,
 
         /* Front end dir is a number, which is used as the id. */
         info->handle = simple_strtoul(strrchr(dev->nodename, '/')+1, NULL, 0);
-        dev->dev.driver_data = info;
+        dev_set_drvdata(&dev->dev, info);
 
         err = talk_to_backend(dev, info);
         if (err) {
                 kfree(info);
-                dev->dev.driver_data = NULL;
+                dev_set_drvdata(&dev->dev, NULL);
                 return err;
         }
 
@@ -843,7 +843,7 @@ static int blkif_recover(struct blkfront_info *info)
  */
 static int blkfront_resume(struct xenbus_device *dev)
 {
-        struct blkfront_info *info = dev->dev.driver_data;
+        struct blkfront_info *info = dev_get_drvdata(&dev->dev);
         int err;
 
         dev_dbg(&dev->dev, "blkfront_resume: %s\n", dev->nodename);
@@ -922,7 +922,7 @@ static void blkfront_connect(struct blkfront_info *info)
  */
 static void blkfront_closing(struct xenbus_device *dev)
 {
-        struct blkfront_info *info = dev->dev.driver_data;
+        struct blkfront_info *info = dev_get_drvdata(&dev->dev);
         unsigned long flags;
 
         dev_dbg(&dev->dev, "blkfront_closing: %s removed\n", dev->nodename);
@@ -957,7 +957,7 @@ static void blkfront_closing(struct xenbus_device *dev)
 static void backend_changed(struct xenbus_device *dev,
                             enum xenbus_state backend_state)
 {
-        struct blkfront_info *info = dev->dev.driver_data;
+        struct blkfront_info *info = dev_get_drvdata(&dev->dev);
         struct block_device *bd;
 
         dev_dbg(&dev->dev, "blkfront:backend_changed.\n");
@@ -997,7 +997,7 @@ static void backend_changed(struct xenbus_device *dev,
 
 static int blkfront_remove(struct xenbus_device *dev)
 {
-        struct blkfront_info *info = dev->dev.driver_data;
+        struct blkfront_info *info = dev_get_drvdata(&dev->dev);
 
         dev_dbg(&dev->dev, "blkfront_remove: %s removed\n", dev->nodename);
 
@@ -1010,7 +1010,7 @@ static int blkfront_remove(struct xenbus_device *dev)
 
 static int blkfront_is_ready(struct xenbus_device *dev)
 {
-        struct blkfront_info *info = dev->dev.driver_data;
+        struct blkfront_info *info = dev_get_drvdata(&dev->dev);
 
         return info->is_ready;
 }
diff --git a/drivers/char/hvcs.c b/drivers/char/hvcs.c
index 2724d628527f..266b858b8f85 100644
--- a/drivers/char/hvcs.c
+++ b/drivers/char/hvcs.c
@@ -347,7 +347,7 @@ static void __exit hvcs_module_exit(void);
 
 static inline struct hvcs_struct *from_vio_dev(struct vio_dev *viod)
 {
-        return viod->dev.driver_data;
+        return dev_get_drvdata(&viod->dev);
 }
 /* The sysfs interface for the driver and devices */
 
@@ -785,7 +785,7 @@ static int __devinit hvcs_probe(
         kref_init(&hvcsd->kref);
 
         hvcsd->vdev = dev;
-        dev->dev.driver_data = hvcsd;
+        dev_set_drvdata(&dev->dev, hvcsd);
 
         hvcsd->index = index;
 
@@ -831,7 +831,7 @@ static int __devinit hvcs_probe(
 
 static int __devexit hvcs_remove(struct vio_dev *dev)
 {
-        struct hvcs_struct *hvcsd = dev->dev.driver_data;
+        struct hvcs_struct *hvcsd = dev_get_drvdata(&dev->dev);
         unsigned long flags;
         struct tty_struct *tty;
 
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index f4b3f7293feb..ce66a70184f7 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -149,6 +149,19 @@ config HW_RANDOM_VIRTIO
           To compile this driver as a module, choose M here: the
           module will be called virtio-rng.  If unsure, say N.
 
+config HW_RANDOM_TX4939
+        tristate "TX4939 Random Number Generator support"
+        depends on HW_RANDOM && SOC_TX4939
+        default HW_RANDOM
+        ---help---
+          This driver provides kernel-side support for the Random Number
+          Generator hardware found on TX4939 SoC.
+
+          To compile this driver as a module, choose M here: the
+          module will be called tx4939-rng.
+
+          If unsure, say Y.
+
 config HW_RANDOM_MXC_RNGA
         tristate "Freescale i.MX RNGA Random Number Generator"
         depends on HW_RANDOM && ARCH_HAS_RNGA
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index fd1ecd2f6731..676828ba8123 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -15,4 +15,5 @@ obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o
 obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o
 obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o
 obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
+obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
 obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
diff --git a/drivers/char/hw_random/core.c b/drivers/char/hw_random/core.c
index e5d583c84e4f..fc93e2fc7c71 100644
--- a/drivers/char/hw_random/core.c
+++ b/drivers/char/hw_random/core.c
@@ -153,6 +153,7 @@ static const struct file_operations rng_chrdev_ops = {
 static struct miscdevice rng_miscdev = {
         .minor          = RNG_MISCDEV_MINOR,
         .name           = RNG_MODULE_NAME,
+        .devnode        = "hwrng",
         .fops           = &rng_chrdev_ops,
 };
 
diff --git a/drivers/char/hw_random/tx4939-rng.c b/drivers/char/hw_random/tx4939-rng.c
new file mode 100644
index 000000000000..544d9085a8e8
--- /dev/null
+++ b/drivers/char/hw_random/tx4939-rng.c
@@ -0,0 +1,184 @@
+/*
+ * RNG driver for TX4939 Random Number Generators (RNG)
+ *
+ * Copyright (C) 2009 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/hw_random.h>
+
+#define TX4939_RNG_RCSR         0x00000000
+#define TX4939_RNG_ROR(n)       (0x00000018 + (n) * 8)
+
+#define TX4939_RNG_RCSR_INTE    0x00000008
+#define TX4939_RNG_RCSR_RST     0x00000004
+#define TX4939_RNG_RCSR_FIN     0x00000002
+#define TX4939_RNG_RCSR_ST      0x00000001
+
+struct tx4939_rng {
+        struct hwrng rng;
+        void __iomem *base;
+        u64 databuf[3];
+        unsigned int data_avail;
+};
+
+static void rng_io_start(void)
+{
+#ifndef CONFIG_64BIT
+        /*
+         * readq is reading a 64-bit register using a 64-bit load.  On
+         * a 32-bit kernel however interrupts or any other processor
+         * exception would clobber the upper 32-bit of the processor
+         * register so interrupts need to be disabled.
+         */
+        local_irq_disable();
+#endif
+}
+
+static void rng_io_end(void)
+{
+#ifndef CONFIG_64BIT
+        local_irq_enable();
+#endif
+}
+
+static u64 read_rng(void __iomem *base, unsigned int offset)
+{
+        return ____raw_readq(base + offset);
+}
+
+static void write_rng(u64 val, void __iomem *base, unsigned int offset)
+{
+        return ____raw_writeq(val, base + offset);
+}
+
+static int tx4939_rng_data_present(struct hwrng *rng, int wait)
+{
+        struct tx4939_rng *rngdev = container_of(rng, struct tx4939_rng, rng);
+        int i;
+
+        if (rngdev->data_avail)
+                return rngdev->data_avail;
+        for (i = 0; i < 20; i++) {
+                rng_io_start();
+                if (!(read_rng(rngdev->base, TX4939_RNG_RCSR)
+                      & TX4939_RNG_RCSR_ST)) {
+                        rngdev->databuf[0] =
+                                read_rng(rngdev->base, TX4939_RNG_ROR(0));
+                        rngdev->databuf[1] =
+                                read_rng(rngdev->base, TX4939_RNG_ROR(1));
+                        rngdev->databuf[2] =
+                                read_rng(rngdev->base, TX4939_RNG_ROR(2));
+                        rngdev->data_avail =
+                                sizeof(rngdev->databuf) / sizeof(u32);
+                        /* Start RNG */
+                        write_rng(TX4939_RNG_RCSR_ST,
+                                  rngdev->base, TX4939_RNG_RCSR);
+                        wait = 0;
+                }
+                rng_io_end();
+                if (!wait)
+                        break;
+                /* 90 bus clock cycles by default for generation */
+                ndelay(90 * 5);
+        }
+        return rngdev->data_avail;
+}
+
+static int tx4939_rng_data_read(struct hwrng *rng, u32 *buffer)
+{
+        struct tx4939_rng *rngdev = container_of(rng, struct tx4939_rng, rng);
+
+        rngdev->data_avail--;
+        *buffer = *((u32 *)&rngdev->databuf + rngdev->data_avail);
+        return sizeof(u32);
+}
+
+static int __init tx4939_rng_probe(struct platform_device *dev)
+{
+        struct tx4939_rng *rngdev;
+        struct resource *r;
+        int i;
+
+        r = platform_get_resource(dev, IORESOURCE_MEM, 0);
+        if (!r)
+                return -EBUSY;
+        rngdev = devm_kzalloc(&dev->dev, sizeof(*rngdev), GFP_KERNEL);
+        if (!rngdev)
+                return -ENOMEM;
+        if (!devm_request_mem_region(&dev->dev, r->start, resource_size(r),
+                                     dev_name(&dev->dev)))
+                return -EBUSY;
+        rngdev->base = devm_ioremap(&dev->dev, r->start, resource_size(r));
+        if (!rngdev->base)
+                return -EBUSY;
+
+        rngdev->rng.name = dev_name(&dev->dev);
+        rngdev->rng.data_present = tx4939_rng_data_present;
+        rngdev->rng.data_read = tx4939_rng_data_read;
+
+        rng_io_start();
+        /* Reset RNG */
+        write_rng(TX4939_RNG_RCSR_RST, rngdev->base, TX4939_RNG_RCSR);
+        write_rng(0, rngdev->base, TX4939_RNG_RCSR);
+        /* Start RNG */
+        write_rng(TX4939_RNG_RCSR_ST, rngdev->base, TX4939_RNG_RCSR);
+        rng_io_end();
+        /*
+         * Drop first two results.  From the datasheet:
+         * The quality of the random numbers generated immediately
+         * after reset can be insufficient.  Therefore, do not use
+         * random numbers obtained from the first and second
+         * generations; use the ones from the third or subsequent
+         * generation.
+         */
+        for (i = 0; i < 2; i++) {
+                rngdev->data_avail = 0;
+                if (!tx4939_rng_data_present(&rngdev->rng, 1))
+                        return -EIO;
+        }
+
+        platform_set_drvdata(dev, rngdev);
+        return hwrng_register(&rngdev->rng);
+}
+
+static int __exit tx4939_rng_remove(struct platform_device *dev)
+{
+        struct tx4939_rng *rngdev = platform_get_drvdata(dev);
+
+        hwrng_unregister(&rngdev->rng);
+        platform_set_drvdata(dev, NULL);
+        return 0;
+}
+
+static struct platform_driver tx4939_rng_driver = {
+        .driver         = {
+                .name   = "tx4939-rng",
+                .owner  = THIS_MODULE,
+        },
+        .remove = tx4939_rng_remove,
+};
+
+static int __init tx4939rng_init(void)
+{
+        return platform_driver_probe(&tx4939_rng_driver, tx4939_rng_probe);
+}
+
+static void __exit tx4939rng_exit(void)
+{
+        platform_driver_unregister(&tx4939_rng_driver);
+}
+
+module_init(tx4939rng_init);
+module_exit(tx4939rng_exit);
+
+MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver for TX4939");
+MODULE_LICENSE("GPL");
diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c
index 259644646b82..d2e698096ace 100644
--- a/drivers/char/ipmi/ipmi_si_intf.c
+++ b/drivers/char/ipmi/ipmi_si_intf.c
@@ -2375,14 +2375,14 @@ static int __devinit ipmi_of_probe(struct of_device *dev,
                 info->io.addr_data, info->io.regsize, info->io.regspacing,
                 info->irq);
 
-        dev->dev.driver_data = (void *) info;
+        dev_set_drvdata(&dev->dev, info);
 
         return try_smi_init(info);
 }
 
 static int __devexit ipmi_of_remove(struct of_device *dev)
 {
-        cleanup_one_si(dev->dev.driver_data);
+        cleanup_one_si(dev_get_drvdata(&dev->dev));
         return 0;
 }
 
diff --git a/drivers/char/misc.c b/drivers/char/misc.c
index a5e0db9d7662..62c99fa59e2b 100644
--- a/drivers/char/misc.c
+++ b/drivers/char/misc.c
@@ -168,7 +168,6 @@ static const struct file_operations misc_fops = {
         .open           = misc_open,
 };
 
-
 /**
  *      misc_register   -       register a miscellaneous device
  *      @misc: device structure
@@ -217,8 +216,8 @@ int misc_register(struct miscdevice * misc)
                 misc_minors[misc->minor >> 3] |= 1 << (misc->minor & 7);
         dev = MKDEV(MISC_MAJOR, misc->minor);
 
-        misc->this_device = device_create(misc_class, misc->parent, dev, NULL,
-                                          "%s", misc->name);
+        misc->this_device = device_create(misc_class, misc->parent, dev,
+                                          misc, "%s", misc->name);
         if (IS_ERR(misc->this_device)) {
                 err = PTR_ERR(misc->this_device);
                 goto out;
@@ -264,6 +263,15 @@ int misc_deregister(struct miscdevice *misc)
 EXPORT_SYMBOL(misc_register);
 EXPORT_SYMBOL(misc_deregister);
 
+static char *misc_nodename(struct device *dev)
+{
+        struct miscdevice *c = dev_get_drvdata(dev);
+
+        if (c->devnode)
+                return kstrdup(c->devnode, GFP_KERNEL);
+        return NULL;
+}
+
 static int __init misc_init(void)
 {
         int err;
@@ -279,6 +287,7 @@ static int __init misc_init(void)
         err = -EIO;
         if (register_chrdev(MISC_MAJOR,"misc",&misc_fops))
                 goto fail_printk;
+        misc_class->nodename = misc_nodename;
         return 0;
 
 fail_printk:
diff --git a/drivers/char/raw.c b/drivers/char/raw.c
index db32f0e4c7dd..05f9d18b9361 100644
--- a/drivers/char/raw.c
+++ b/drivers/char/raw.c
@@ -261,6 +261,11 @@ static const struct file_operations raw_ctl_fops = {
 
 static struct cdev raw_cdev;
 
+static char *raw_nodename(struct device *dev)
+{
+        return kasprintf(GFP_KERNEL, "raw/%s", dev_name(dev));
+}
+
 static int __init raw_init(void)
 {
         dev_t dev = MKDEV(RAW_MAJOR, 0);
@@ -284,6 +289,7 @@ static int __init raw_init(void)
                 ret = PTR_ERR(raw_class);
                 goto error_region;
         }
+        raw_class->nodename = raw_nodename;
         device_create(raw_class, NULL, MKDEV(RAW_MAJOR, 0), NULL, "rawctl");
 
         return 0;
diff --git a/drivers/char/vt.c b/drivers/char/vt.c
index c796a86ab7f3..d9113b4c76e3 100644
--- a/drivers/char/vt.c
+++ b/drivers/char/vt.c
@@ -171,8 +171,9 @@ int do_poke_blanked_console;
 int console_blanked;
 
 static int vesa_blank_mode; /* 0:none 1:suspendV 2:suspendH 3:powerdown */
-static int blankinterval = 10*60*HZ;
 static int vesa_off_interval;
+static int blankinterval = 10*60;
+core_param(consoleblank, blankinterval, int, 0444);
 
 static DECLARE_WORK(console_work, console_callback);
 
@@ -1485,7 +1486,7 @@ static void setterm_command(struct vc_data *vc)
                         update_attr(vc);
                         break;
                 case 9: /* set blanking interval */
-                        blankinterval = ((vc->vc_par[1] < 60) ? vc->vc_par[1] : 60) * 60 * HZ;
+                        blankinterval = ((vc->vc_par[1] < 60) ? vc->vc_par[1] : 60) * 60;
                         poke_blanked_console();
                         break;
                 case 10: /* set bell frequency in Hz */
@@ -2871,7 +2872,7 @@ static int __init con_init(void)
 
         if (blankinterval) {
                 blank_state = blank_normal_wait;
-                mod_timer(&console_timer, jiffies + blankinterval);
+                mod_timer(&console_timer, jiffies + (blankinterval * HZ));
         }
 
         for (currcons = 0; currcons < MIN_NR_CONSOLES; currcons++) {
@@ -3677,7 +3678,7 @@ void do_unblank_screen(int leaving_gfx)
                 return; /* but leave console_blanked != 0 */
 
         if (blankinterval) {
-                mod_timer(&console_timer, jiffies + blankinterval);
+                mod_timer(&console_timer, jiffies + (blankinterval * HZ));
                 blank_state = blank_normal_wait;
         }
 
@@ -3711,7 +3712,7 @@ void unblank_screen(void)
 static void blank_screen_t(unsigned long dummy)
 {
         if (unlikely(!keventd_up())) {
-                mod_timer(&console_timer, jiffies + blankinterval);
+                mod_timer(&console_timer, jiffies + (blankinterval * HZ));
                 return;
         }
         blank_timer_expired = 1;
@@ -3741,7 +3742,7 @@ void poke_blanked_console(void)
         if (console_blanked)
                 unblank_screen();
         else if (blankinterval) {
-                mod_timer(&console_timer, jiffies + blankinterval);
+                mod_timer(&console_timer, jiffies + (blankinterval * HZ));
                 blank_state = blank_normal_wait;
         }
 }
diff --git a/drivers/clocksource/acpi_pm.c b/drivers/clocksource/acpi_pm.c
index 40bd8c61c7d7..72a633a6ec98 100644
--- a/drivers/clocksource/acpi_pm.c
+++ b/drivers/clocksource/acpi_pm.c
@@ -18,6 +18,7 @@
 
 #include <linux/acpi_pmtmr.h>
 #include <linux/clocksource.h>
+#include <linux/timex.h>
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/pci.h>
diff --git a/drivers/cpufreq/cpufreq_conservative.c b/drivers/cpufreq/cpufreq_conservative.c
index 7a74d175287b..7fc58af748b4 100644
--- a/drivers/cpufreq/cpufreq_conservative.c
+++ b/drivers/cpufreq/cpufreq_conservative.c
@@ -42,27 +42,12 @@
  * this governor will not work.
  * All times here are in uS.
  */
-static unsigned int def_sampling_rate;
 #define MIN_SAMPLING_RATE_RATIO                 (2)
-/* for correct statistics, we need at least 10 ticks between each measure */
-#define MIN_STAT_SAMPLING_RATE                  \
-                        (MIN_SAMPLING_RATE_RATIO * jiffies_to_usecs(10))
-#define MIN_SAMPLING_RATE                       \
-                        (def_sampling_rate / MIN_SAMPLING_RATE_RATIO)
-/* Above MIN_SAMPLING_RATE will vanish with its sysfs file soon
- * Define the minimal settable sampling rate to the greater of:
- *   - "HW transition latency" * 100 (same as default sampling / 10)
- *   - MIN_STAT_SAMPLING_RATE
- * To avoid that userspace shoots itself.
-*/
-static unsigned int minimum_sampling_rate(void)
-{
-        return max(def_sampling_rate / 10, MIN_STAT_SAMPLING_RATE);
-}
 
-/* This will also vanish soon with removing sampling_rate_max */
-#define MAX_SAMPLING_RATE                       (500 * def_sampling_rate)
+static unsigned int min_sampling_rate;
+
 #define LATENCY_MULTIPLIER                      (1000)
+#define MIN_LATENCY_MULTIPLIER                  (100)
 #define DEF_SAMPLING_DOWN_FACTOR                (1)
 #define MAX_SAMPLING_DOWN_FACTOR                (10)
 #define TRANSITION_LATENCY_LIMIT                (10 * 1000 * 1000)
@@ -182,27 +167,14 @@ static struct notifier_block dbs_cpufreq_notifier_block = {
 /************************** sysfs interface ************************/
 static ssize_t show_sampling_rate_max(struct cpufreq_policy *policy, char *buf)
 {
-        static int print_once;
-
-        if (!print_once) {
-                printk(KERN_INFO "CPUFREQ: conservative sampling_rate_max "
-                       "sysfs file is deprecated - used by: %s\n",
-                       current->comm);
-                print_once = 1;
-        }
-        return sprintf(buf, "%u\n", MAX_SAMPLING_RATE);
+        printk_once(KERN_INFO "CPUFREQ: conservative sampling_rate_max "
+                    "sysfs file is deprecated - used by: %s\n", current->comm);
+        return sprintf(buf, "%u\n", -1U);
 }
 
 static ssize_t show_sampling_rate_min(struct cpufreq_policy *policy, char *buf)
 {
-        static int print_once;
-
-        if (!print_once) {
-                printk(KERN_INFO "CPUFREQ: conservative sampling_rate_max "
-                       "sysfs file is deprecated - used by: %s\n", current->comm);
-                print_once = 1;
-        }
-        return sprintf(buf, "%u\n", MIN_SAMPLING_RATE);
+        return sprintf(buf, "%u\n", min_sampling_rate);
 }
 
 #define define_one_ro(_name)            \
@@ -254,7 +226,7 @@ static ssize_t store_sampling_rate(struct cpufreq_policy *unused,
                 return -EINVAL;
 
         mutex_lock(&dbs_mutex);
-        dbs_tuners_ins.sampling_rate = max(input, minimum_sampling_rate());
+        dbs_tuners_ins.sampling_rate = max(input, min_sampling_rate);
         mutex_unlock(&dbs_mutex);
 
         return count;
@@ -601,11 +573,18 @@ static int cpufreq_governor_dbs(struct cpufreq_policy *policy,
                         if (latency == 0)
                                 latency = 1;
 
-                        def_sampling_rate =
-                                max(latency * LATENCY_MULTIPLIER,
-                                    MIN_STAT_SAMPLING_RATE);
-
-                        dbs_tuners_ins.sampling_rate = def_sampling_rate;
+                        /*
+                         * conservative does not implement micro like ondemand
+                         * governor, thus we are bound to jiffes/HZ
+                         */
+                        min_sampling_rate =
+                                MIN_SAMPLING_RATE_RATIO * jiffies_to_usecs(10);
+                        /* Bring kernel and HW constraints together */
+                        min_sampling_rate = max(min_sampling_rate,
+                                        MIN_LATENCY_MULTIPLIER * latency);
+                        dbs_tuners_ins.sampling_rate =
+                                max(min_sampling_rate,
+                                    latency * LATENCY_MULTIPLIER);
 
                         cpufreq_register_notifier(
                                         &dbs_cpufreq_notifier_block,
diff --git a/drivers/cpufreq/cpufreq_ondemand.c b/drivers/cpufreq/cpufreq_ondemand.c
index e741c339df76..1911d1729353 100644
--- a/drivers/cpufreq/cpufreq_ondemand.c
+++ b/drivers/cpufreq/cpufreq_ondemand.c
@@ -32,6 +32,7 @@
 #define DEF_FREQUENCY_UP_THRESHOLD              (80)
 #define MICRO_FREQUENCY_DOWN_DIFFERENTIAL       (3)
 #define MICRO_FREQUENCY_UP_THRESHOLD            (95)
+#define MICRO_FREQUENCY_MIN_SAMPLE_RATE         (10000)
 #define MIN_FREQUENCY_UP_THRESHOLD              (11)
 #define MAX_FREQUENCY_UP_THRESHOLD              (100)
 
@@ -45,27 +46,12 @@
  * this governor will not work.
  * All times here are in uS.
  */
-static unsigned int def_sampling_rate;
 #define MIN_SAMPLING_RATE_RATIO                 (2)
-/* for correct statistics, we need at least 10 ticks between each measure */
-#define MIN_STAT_SAMPLING_RATE                  \
-                        (MIN_SAMPLING_RATE_RATIO * jiffies_to_usecs(10))
-#define MIN_SAMPLING_RATE                       \
-                        (def_sampling_rate / MIN_SAMPLING_RATE_RATIO)
-/* Above MIN_SAMPLING_RATE will vanish with its sysfs file soon
- * Define the minimal settable sampling rate to the greater of:
- *   - "HW transition latency" * 100 (same as default sampling / 10)
- *   - MIN_STAT_SAMPLING_RATE
- * To avoid that userspace shoots itself.
-*/
-static unsigned int minimum_sampling_rate(void)
-{
-        return max(def_sampling_rate / 10, MIN_STAT_SAMPLING_RATE);
-}
 
-/* This will also vanish soon with removing sampling_rate_max */
-#define MAX_SAMPLING_RATE                       (500 * def_sampling_rate)
+static unsigned int min_sampling_rate;
+
 #define LATENCY_MULTIPLIER                      (1000)
+#define MIN_LATENCY_MULTIPLIER                  (100)
 #define TRANSITION_LATENCY_LIMIT                (10 * 1000 * 1000)
 
 static void do_dbs_timer(struct work_struct *work);
@@ -219,28 +205,14 @@ static void ondemand_powersave_bias_init(void)
 /************************** sysfs interface ************************/
 static ssize_t show_sampling_rate_max(struct cpufreq_policy *policy, char *buf)
 {
-        static int print_once;
-
-        if (!print_once) {
-                printk(KERN_INFO "CPUFREQ: ondemand sampling_rate_max "
-                       "sysfs file is deprecated - used by: %s\n",
-                       current->comm);
-                print_once = 1;
-        }
-        return sprintf(buf, "%u\n", MAX_SAMPLING_RATE);
+        printk_once(KERN_INFO "CPUFREQ: ondemand sampling_rate_max "
+               "sysfs file is deprecated - used by: %s\n", current->comm);
+        return sprintf(buf, "%u\n", -1U);
 }
 
 static ssize_t show_sampling_rate_min(struct cpufreq_policy *policy, char *buf)
 {
-        static int print_once;
-
-        if (!print_once) {
-                printk(KERN_INFO "CPUFREQ: ondemand sampling_rate_min "
-                       "sysfs file is deprecated - used by: %s\n",
-                       current->comm);
-                print_once = 1;
-        }
-        return sprintf(buf, "%u\n", MIN_SAMPLING_RATE);
+        return sprintf(buf, "%u\n", min_sampling_rate);
 }
 
 #define define_one_ro(_name)            \
@@ -274,7 +246,7 @@ static ssize_t store_sampling_rate(struct cpufreq_policy *unused,
                 mutex_unlock(&dbs_mutex);
                 return -EINVAL;
         }
-        dbs_tuners_ins.sampling_rate = max(input, minimum_sampling_rate());
+        dbs_tuners_ins.sampling_rate = max(input, min_sampling_rate);
         mutex_unlock(&dbs_mutex);
 
         return count;
@@ -619,12 +591,12 @@ static int cpufreq_governor_dbs(struct cpufreq_policy *policy,
                         latency = policy->cpuinfo.transition_latency / 1000;
                         if (latency == 0)
                                 latency = 1;
-
-                        def_sampling_rate =
-                                max(latency * LATENCY_MULTIPLIER,
-                                    MIN_STAT_SAMPLING_RATE);
-
-                        dbs_tuners_ins.sampling_rate = def_sampling_rate;
+                        /* Bring kernel and HW constraints together */
+                        min_sampling_rate = max(min_sampling_rate,
+                                        MIN_LATENCY_MULTIPLIER * latency);
+                        dbs_tuners_ins.sampling_rate =
+                                max(min_sampling_rate,
+                                    latency * LATENCY_MULTIPLIER);
                 }
                 dbs_timer_init(this_dbs_info);
 
@@ -678,6 +650,16 @@ static int __init cpufreq_gov_dbs_init(void)
                 dbs_tuners_ins.up_threshold = MICRO_FREQUENCY_UP_THRESHOLD;
                 dbs_tuners_ins.down_differential =
                                         MICRO_FREQUENCY_DOWN_DIFFERENTIAL;
+                /*
+                 * In no_hz/micro accounting case we set the minimum frequency
+                 * not depending on HZ, but fixed (very low). The deferred
+                 * timer might skip some samples if idle/sleeping as needed.
+                */
+                min_sampling_rate = MICRO_FREQUENCY_MIN_SAMPLE_RATE;
+        } else {
+                /* For correct statistics, we need 10 ticks for each measure */
+                min_sampling_rate =
+                        MIN_SAMPLING_RATE_RATIO * jiffies_to_usecs(10);
         }
 
         kondemand_wq = create_workqueue("kondemand");
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 3b3c01b6f1ee..070357aaedbc 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -81,6 +81,14 @@ config MX3_IPU_IRQS
           To avoid bloating the irq_desc[] array we allocate a sufficient
           number of IRQ slots and map them dynamically to specific sources.
 
+config TXX9_DMAC
+        tristate "Toshiba TXx9 SoC DMA support"
+        depends on MACH_TX49XX || MACH_TX39XX
+        select DMA_ENGINE
+        help
+          Support the TXx9 SoC internal DMA controller.  This can be
+          integrated in chips such as the Toshiba TX4927/38/39.
+
 config DMA_ENGINE
         bool
 
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 2e5dc96700d2..a0b6564800c4 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_FSL_DMA) += fsldma.o
 obj-$(CONFIG_MV_XOR) += mv_xor.o
 obj-$(CONFIG_DW_DMAC) += dw_dmac.o
 obj-$(CONFIG_MX3_IPU) += ipu/
+obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
diff --git a/drivers/dma/txx9dmac.c b/drivers/dma/txx9dmac.c
new file mode 100644
index 000000000000..9aa9ea9822c8
--- /dev/null
+++ b/drivers/dma/txx9dmac.c
@@ -0,0 +1,1354 @@
+/*
+ * Driver for the TXx9 SoC DMA Controller
+ *
+ * Copyright (C) 2009 Atsushi Nemoto
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/scatterlist.h>
+#include "txx9dmac.h"
+
+static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
+{
+        return container_of(chan, struct txx9dmac_chan, chan);
+}
+
+static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
+{
+        return dc->ch_regs;
+}
+
+static struct txx9dmac_cregs32 __iomem *__dma_regs32(
+        const struct txx9dmac_chan *dc)
+{
+        return dc->ch_regs;
+}
+
+#define channel64_readq(dc, name) \
+        __raw_readq(&(__dma_regs(dc)->name))
+#define channel64_writeq(dc, name, val) \
+        __raw_writeq((val), &(__dma_regs(dc)->name))
+#define channel64_readl(dc, name) \
+        __raw_readl(&(__dma_regs(dc)->name))
+#define channel64_writel(dc, name, val) \
+        __raw_writel((val), &(__dma_regs(dc)->name))
+
+#define channel32_readl(dc, name) \
+        __raw_readl(&(__dma_regs32(dc)->name))
+#define channel32_writel(dc, name, val) \
+        __raw_writel((val), &(__dma_regs32(dc)->name))
+
+#define channel_readq(dc, name) channel64_readq(dc, name)
+#define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
+#define channel_readl(dc, name) \
+        (is_dmac64(dc) ? \
+         channel64_readl(dc, name) : channel32_readl(dc, name))
+#define channel_writel(dc, name, val) \
+        (is_dmac64(dc) ? \
+         channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
+
+static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
+{
+        if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
+                return channel64_readq(dc, CHAR);
+        else
+                return channel64_readl(dc, CHAR);
+}
+
+static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
+{
+        if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
+                channel64_writeq(dc, CHAR, val);
+        else
+                channel64_writel(dc, CHAR, val);
+}
+
+static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
+{
+#if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR)
+        channel64_writel(dc, CHAR, 0);
+        channel64_writel(dc, __pad_CHAR, 0);
+#else
+        channel64_writeq(dc, CHAR, 0);
+#endif
+}
+
+static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
+{
+        if (is_dmac64(dc))
+                return channel64_read_CHAR(dc);
+        else
+                return channel32_readl(dc, CHAR);
+}
+
+static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
+{
+        if (is_dmac64(dc))
+                channel64_write_CHAR(dc, val);
+        else
+                channel32_writel(dc, CHAR, val);
+}
+
+static struct txx9dmac_regs __iomem *__txx9dmac_regs(
+        const struct txx9dmac_dev *ddev)
+{
+        return ddev->regs;
+}
+
+static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
+        const struct txx9dmac_dev *ddev)
+{
+        return ddev->regs;
+}
+
+#define dma64_readl(ddev, name) \
+        __raw_readl(&(__txx9dmac_regs(ddev)->name))
+#define dma64_writel(ddev, name, val) \
+        __raw_writel((val), &(__txx9dmac_regs(ddev)->name))
+
+#define dma32_readl(ddev, name) \
+        __raw_readl(&(__txx9dmac_regs32(ddev)->name))
+#define dma32_writel(ddev, name, val) \
+        __raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
+
+#define dma_readl(ddev, name) \
+        (__is_dmac64(ddev) ? \
+        dma64_readl(ddev, name) : dma32_readl(ddev, name))
+#define dma_writel(ddev, name, val) \
+        (__is_dmac64(ddev) ? \
+        dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
+
+static struct device *chan2dev(struct dma_chan *chan)
+{
+        return &chan->dev->device;
+}
+static struct device *chan2parent(struct dma_chan *chan)
+{
+        return chan->dev->device.parent;
+}
+
+static struct txx9dmac_desc *
+txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
+{
+        return container_of(txd, struct txx9dmac_desc, txd);
+}
+
+static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
+                                 const struct txx9dmac_desc *desc)
+{
+        return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
+}
+
+static void desc_write_CHAR(const struct txx9dmac_chan *dc,
+                            struct txx9dmac_desc *desc, dma_addr_t val)
+{
+        if (is_dmac64(dc))
+                desc->hwdesc.CHAR = val;
+        else
+                desc->hwdesc32.CHAR = val;
+}
+
+#define TXX9_DMA_MAX_COUNT      0x04000000
+
+#define TXX9_DMA_INITIAL_DESC_COUNT     64
+
+static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
+{
+        return list_entry(dc->active_list.next,
+                          struct txx9dmac_desc, desc_node);
+}
+
+static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
+{
+        return list_entry(dc->active_list.prev,
+                          struct txx9dmac_desc, desc_node);
+}
+
+static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
+{
+        return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
+}
+
+static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
+{
+        if (!list_empty(&desc->txd.tx_list))
+                desc = list_entry(desc->txd.tx_list.prev,
+                                  struct txx9dmac_desc, desc_node);
+        return desc;
+}
+
+static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
+
+static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
+                                                 gfp_t flags)
+{
+        struct txx9dmac_dev *ddev = dc->ddev;
+        struct txx9dmac_desc *desc;
+
+        desc = kzalloc(sizeof(*desc), flags);
+        if (!desc)
+                return NULL;
+        dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
+        desc->txd.tx_submit = txx9dmac_tx_submit;
+        /* txd.flags will be overwritten in prep funcs */
+        desc->txd.flags = DMA_CTRL_ACK;
+        desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
+                                        ddev->descsize, DMA_TO_DEVICE);
+        return desc;
+}
+
+static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
+{
+        struct txx9dmac_desc *desc, *_desc;
+        struct txx9dmac_desc *ret = NULL;
+        unsigned int i = 0;
+
+        spin_lock_bh(&dc->lock);
+        list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
+                if (async_tx_test_ack(&desc->txd)) {
+                        list_del(&desc->desc_node);
+                        ret = desc;
+                        break;
+                }
+                dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
+                i++;
+        }
+        spin_unlock_bh(&dc->lock);
+
+        dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
+                 i);
+        if (!ret) {
+                ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
+                if (ret) {
+                        spin_lock_bh(&dc->lock);
+                        dc->descs_allocated++;
+                        spin_unlock_bh(&dc->lock);
+                } else
+                        dev_err(chan2dev(&dc->chan),
+                                "not enough descriptors available\n");
+        }
+        return ret;
+}
+
+static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
+                                       struct txx9dmac_desc *desc)
+{
+        struct txx9dmac_dev *ddev = dc->ddev;
+        struct txx9dmac_desc *child;
+
+        list_for_each_entry(child, &desc->txd.tx_list, desc_node)
+                dma_sync_single_for_cpu(chan2parent(&dc->chan),
+                                child->txd.phys, ddev->descsize,
+                                DMA_TO_DEVICE);
+        dma_sync_single_for_cpu(chan2parent(&dc->chan),
+                        desc->txd.phys, ddev->descsize,
+                        DMA_TO_DEVICE);
+}
+
+/*
+ * Move a descriptor, including any children, to the free list.
+ * `desc' must not be on any lists.
+ */
+static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
+                              struct txx9dmac_desc *desc)
+{
+        if (desc) {
+                struct txx9dmac_desc *child;
+
+                txx9dmac_sync_desc_for_cpu(dc, desc);
+
+                spin_lock_bh(&dc->lock);
+                list_for_each_entry(child, &desc->txd.tx_list, desc_node)
+                        dev_vdbg(chan2dev(&dc->chan),
+                                 "moving child desc %p to freelist\n",
+                                 child);
+                list_splice_init(&desc->txd.tx_list, &dc->free_list);
+                dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
+                         desc);
+                list_add(&desc->desc_node, &dc->free_list);
+                spin_unlock_bh(&dc->lock);
+        }
+}
+
+/* Called with dc->lock held and bh disabled */
+static dma_cookie_t
+txx9dmac_assign_cookie(struct txx9dmac_chan *dc, struct txx9dmac_desc *desc)
+{
+        dma_cookie_t cookie = dc->chan.cookie;
+
+        if (++cookie < 0)
+                cookie = 1;
+
+        dc->chan.cookie = cookie;
+        desc->txd.cookie = cookie;
+
+        return cookie;
+}
+
+/*----------------------------------------------------------------------*/
+
+static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
+{
+        if (is_dmac64(dc))
+                dev_err(chan2dev(&dc->chan),
+                        "  CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
+                        " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
+                        (u64)channel64_read_CHAR(dc),
+                        channel64_readq(dc, SAR),
+                        channel64_readq(dc, DAR),
+                        channel64_readl(dc, CNTR),
+                        channel64_readl(dc, SAIR),
+                        channel64_readl(dc, DAIR),
+                        channel64_readl(dc, CCR),
+                        channel64_readl(dc, CSR));
+        else
+                dev_err(chan2dev(&dc->chan),
+                        "  CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
+                        " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
+                        channel32_readl(dc, CHAR),
+                        channel32_readl(dc, SAR),
+                        channel32_readl(dc, DAR),
+                        channel32_readl(dc, CNTR),
+                        channel32_readl(dc, SAIR),
+                        channel32_readl(dc, DAIR),
+                        channel32_readl(dc, CCR),
+                        channel32_readl(dc, CSR));
+}
+
+static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
+{
+        channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
+        if (is_dmac64(dc)) {
+                channel64_clear_CHAR(dc);
+                channel_writeq(dc, SAR, 0);
+                channel_writeq(dc, DAR, 0);
+        } else {
+                channel_writel(dc, CHAR, 0);
+                channel_writel(dc, SAR, 0);
+                channel_writel(dc, DAR, 0);
+        }
+        channel_writel(dc, CNTR, 0);
+        channel_writel(dc, SAIR, 0);
+        channel_writel(dc, DAIR, 0);
+        channel_writel(dc, CCR, 0);
+        mmiowb();
+}
+
+/* Called with dc->lock held and bh disabled */
+static void txx9dmac_dostart(struct txx9dmac_chan *dc,
+                             struct txx9dmac_desc *first)
+{
+        struct txx9dmac_slave *ds = dc->chan.private;
+        u32 sai, dai;
+
+        dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
+                 first->txd.cookie, first);
+        /* ASSERT:  channel is idle */
+        if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
+                dev_err(chan2dev(&dc->chan),
+                        "BUG: Attempted to start non-idle channel\n");
+                txx9dmac_dump_regs(dc);
+                /* The tasklet will hopefully advance the queue... */
+                return;
+        }
+
+        if (is_dmac64(dc)) {
+                channel64_writel(dc, CNTR, 0);
+                channel64_writel(dc, CSR, 0xffffffff);
+                if (ds) {
+                        if (ds->tx_reg) {
+                                sai = ds->reg_width;
+                                dai = 0;
+                        } else {
+                                sai = 0;
+                                dai = ds->reg_width;
+                        }
+                } else {
+                        sai = 8;
+                        dai = 8;
+                }
+                channel64_writel(dc, SAIR, sai);
+                channel64_writel(dc, DAIR, dai);
+                /* All 64-bit DMAC supports SMPCHN */
+                channel64_writel(dc, CCR, dc->ccr);
+                /* Writing a non zero value to CHAR will assert XFACT */
+                channel64_write_CHAR(dc, first->txd.phys);
+        } else {
+                channel32_writel(dc, CNTR, 0);
+                channel32_writel(dc, CSR, 0xffffffff);
+                if (ds) {
+                        if (ds->tx_reg) {
+                                sai = ds->reg_width;
+                                dai = 0;
+                        } else {
+                                sai = 0;
+                                dai = ds->reg_width;
+                        }
+                } else {
+                        sai = 4;
+                        dai = 4;
+                }
+                channel32_writel(dc, SAIR, sai);
+                channel32_writel(dc, DAIR, dai);
+                if (txx9_dma_have_SMPCHN()) {
+                        channel32_writel(dc, CCR, dc->ccr);
+                        /* Writing a non zero value to CHAR will assert XFACT */
+                        channel32_writel(dc, CHAR, first->txd.phys);
+                } else {
+                        channel32_writel(dc, CHAR, first->txd.phys);
+                        channel32_writel(dc, CCR, dc->ccr);
+                }
+        }
+}
+
+/*----------------------------------------------------------------------*/
+
+static void
+txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
+                             struct txx9dmac_desc *desc)
+{
+        dma_async_tx_callback callback;
+        void *param;
+        struct dma_async_tx_descriptor *txd = &desc->txd;
+        struct txx9dmac_slave *ds = dc->chan.private;
+
+        dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
+                 txd->cookie, desc);
+
+        dc->completed = txd->cookie;
+        callback = txd->callback;
+        param = txd->callback_param;
+
+        txx9dmac_sync_desc_for_cpu(dc, desc);
+        list_splice_init(&txd->tx_list, &dc->free_list);
+        list_move(&desc->desc_node, &dc->free_list);
+
+        /*
+         * We use dma_unmap_page() regardless of how the buffers were
+         * mapped before they were submitted...
+         */
+        if (!ds) {
+                dma_addr_t dmaaddr;
+                if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
+                        dmaaddr = is_dmac64(dc) ?
+                                desc->hwdesc.DAR : desc->hwdesc32.DAR;
+                        dma_unmap_page(chan2parent(&dc->chan), dmaaddr,
+                                       desc->len, DMA_FROM_DEVICE);
+                }
+                if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
+                        dmaaddr = is_dmac64(dc) ?
+                                desc->hwdesc.SAR : desc->hwdesc32.SAR;
+                        dma_unmap_page(chan2parent(&dc->chan), dmaaddr,
+                                       desc->len, DMA_TO_DEVICE);
+                }
+        }
+
+        /*
+         * The API requires that no submissions are done from a
+         * callback, so we don't need to drop the lock here
+         */
+        if (callback)
+                callback(param);
+        dma_run_dependencies(txd);
+}
+
+static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
+{
+        struct txx9dmac_dev *ddev = dc->ddev;
+        struct txx9dmac_desc *desc;
+        struct txx9dmac_desc *prev = NULL;
+
+        BUG_ON(!list_empty(list));
+        do {
+                desc = txx9dmac_first_queued(dc);
+                if (prev) {
+                        desc_write_CHAR(dc, prev, desc->txd.phys);
+                        dma_sync_single_for_device(chan2parent(&dc->chan),
+                                prev->txd.phys, ddev->descsize,
+                                DMA_TO_DEVICE);
+                }
+                prev = txx9dmac_last_child(desc);
+                list_move_tail(&desc->desc_node, list);
+                /* Make chain-completion interrupt happen */
+                if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
+                    !txx9dmac_chan_INTENT(dc))
+                        break;
+        } while (!list_empty(&dc->queue));
+}
+
+static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
+{
+        struct txx9dmac_desc *desc, *_desc;
+        LIST_HEAD(list);
+
+        /*
+         * Submit queued descriptors ASAP, i.e. before we go through
+         * the completed ones.
+         */
+        list_splice_init(&dc->active_list, &list);
+        if (!list_empty(&dc->queue)) {
+                txx9dmac_dequeue(dc, &dc->active_list);
+                txx9dmac_dostart(dc, txx9dmac_first_active(dc));
+        }
+
+        list_for_each_entry_safe(desc, _desc, &list, desc_node)
+                txx9dmac_descriptor_complete(dc, desc);
+}
+
+static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
+                               struct txx9dmac_hwdesc *desc)
+{
+        if (is_dmac64(dc)) {
+#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
+                dev_crit(chan2dev(&dc->chan),
+                         "  desc: ch%#llx s%#llx d%#llx c%#x\n",
+                         (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
+#else
+                dev_crit(chan2dev(&dc->chan),
+                         "  desc: ch%#llx s%#llx d%#llx c%#x"
+                         " si%#x di%#x cc%#x cs%#x\n",
+                         (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
+                         desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
+#endif
+        } else {
+                struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
+#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
+                dev_crit(chan2dev(&dc->chan),
+                         "  desc: ch%#x s%#x d%#x c%#x\n",
+                         d->CHAR, d->SAR, d->DAR, d->CNTR);
+#else
+                dev_crit(chan2dev(&dc->chan),
+                         "  desc: ch%#x s%#x d%#x c%#x"
+                         " si%#x di%#x cc%#x cs%#x\n",
+                         d->CHAR, d->SAR, d->DAR, d->CNTR,
+                         d->SAIR, d->DAIR, d->CCR, d->CSR);
+#endif
+        }
+}
+
+static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
+{
+        struct txx9dmac_desc *bad_desc;
+        struct txx9dmac_desc *child;
+        u32 errors;
+
+        /*
+         * The descriptor currently at the head of the active list is
+         * borked. Since we don't have any way to report errors, we'll
+         * just have to scream loudly and try to carry on.
+         */
+        dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
+        txx9dmac_dump_regs(dc);
+
+        bad_desc = txx9dmac_first_active(dc);
+        list_del_init(&bad_desc->desc_node);
+
+        /* Clear all error flags and try to restart the controller */
+        errors = csr & (TXX9_DMA_CSR_ABCHC |
+                        TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
+                        TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
+        channel_writel(dc, CSR, errors);
+
+        if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
+                txx9dmac_dequeue(dc, &dc->active_list);
+        if (!list_empty(&dc->active_list))
+                txx9dmac_dostart(dc, txx9dmac_first_active(dc));
+
+        dev_crit(chan2dev(&dc->chan),
+                 "Bad descriptor submitted for DMA! (cookie: %d)\n",
+                 bad_desc->txd.cookie);
+        txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
+        list_for_each_entry(child, &bad_desc->txd.tx_list, desc_node)
+                txx9dmac_dump_desc(dc, &child->hwdesc);
+        /* Pretend the descriptor completed successfully */
+        txx9dmac_descriptor_complete(dc, bad_desc);
+}
+
+static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
+{
+        dma_addr_t chain;
+        struct txx9dmac_desc *desc, *_desc;
+        struct txx9dmac_desc *child;
+        u32 csr;
+
+        if (is_dmac64(dc)) {
+                chain = channel64_read_CHAR(dc);
+                csr = channel64_readl(dc, CSR);
+                channel64_writel(dc, CSR, csr);
+        } else {
+                chain = channel32_readl(dc, CHAR);
+                csr = channel32_readl(dc, CSR);
+                channel32_writel(dc, CSR, csr);
+        }
+        /* For dynamic chain, we should look at XFACT instead of NCHNC */
+        if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
+                /* Everything we've submitted is done */
+                txx9dmac_complete_all(dc);
+                return;
+        }
+        if (!(csr & TXX9_DMA_CSR_CHNEN))
+                chain = 0;      /* last descriptor of this chain */
+
+        dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
+                 (u64)chain);
+
+        list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
+                if (desc_read_CHAR(dc, desc) == chain) {
+                        /* This one is currently in progress */
+                        if (csr & TXX9_DMA_CSR_ABCHC)
+                                goto scan_done;
+                        return;
+                }
+
+                list_for_each_entry(child, &desc->txd.tx_list, desc_node)
+                        if (desc_read_CHAR(dc, child) == chain) {
+                                /* Currently in progress */
+                                if (csr & TXX9_DMA_CSR_ABCHC)
+                                        goto scan_done;
+                                return;
+                        }
+
+                /*
+                 * No descriptors so far seem to be in progress, i.e.
+                 * this one must be done.
+                 */
+                txx9dmac_descriptor_complete(dc, desc);
+        }
+scan_done:
+        if (csr & TXX9_DMA_CSR_ABCHC) {
+                txx9dmac_handle_error(dc, csr);
+                return;
+        }
+
+        dev_err(chan2dev(&dc->chan),
+                "BUG: All descriptors done, but channel not idle!\n");
+
+        /* Try to continue after resetting the channel... */
+        txx9dmac_reset_chan(dc);
+
+        if (!list_empty(&dc->queue)) {
+                txx9dmac_dequeue(dc, &dc->active_list);
+                txx9dmac_dostart(dc, txx9dmac_first_active(dc));
+        }
+}
+
+static void txx9dmac_chan_tasklet(unsigned long data)
+{
+        int irq;
+        u32 csr;
+        struct txx9dmac_chan *dc;
+
+        dc = (struct txx9dmac_chan *)data;
+        csr = channel_readl(dc, CSR);
+        dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
+
+        spin_lock(&dc->lock);
+        if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
+                   TXX9_DMA_CSR_NTRNFC))
+                txx9dmac_scan_descriptors(dc);
+        spin_unlock(&dc->lock);
+        irq = dc->irq;
+
+        enable_irq(irq);
+}
+
+static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
+{
+        struct txx9dmac_chan *dc = dev_id;
+
+        dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
+                        channel_readl(dc, CSR));
+
+        tasklet_schedule(&dc->tasklet);
+        /*
+         * Just disable the interrupts. We'll turn them back on in the
+         * softirq handler.
+         */
+        disable_irq_nosync(irq);
+
+        return IRQ_HANDLED;
+}
+
+static void txx9dmac_tasklet(unsigned long data)
+{
+        int irq;
+        u32 csr;
+        struct txx9dmac_chan *dc;
+
+        struct txx9dmac_dev *ddev = (struct txx9dmac_dev *)data;
+        u32 mcr;
+        int i;
+
+        mcr = dma_readl(ddev, MCR);
+        dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
+        for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
+                if ((mcr >> (24 + i)) & 0x11) {
+                        dc = ddev->chan[i];
+                        csr = channel_readl(dc, CSR);
+                        dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
+                                 csr);
+                        spin_lock(&dc->lock);
+                        if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
+                                   TXX9_DMA_CSR_NTRNFC))
+                                txx9dmac_scan_descriptors(dc);
+                        spin_unlock(&dc->lock);
+                }
+        }
+        irq = ddev->irq;
+
+        enable_irq(irq);
+}
+
+static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
+{
+        struct txx9dmac_dev *ddev = dev_id;
+
+        dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
+                        dma_readl(ddev, MCR));
+
+        tasklet_schedule(&ddev->tasklet);
+        /*
+         * Just disable the interrupts. We'll turn them back on in the
+         * softirq handler.
+         */
+        disable_irq_nosync(irq);
+
+        return IRQ_HANDLED;
+}
+
+/*----------------------------------------------------------------------*/
+
+static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+        struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
+        struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
+        dma_cookie_t cookie;
+
+        spin_lock_bh(&dc->lock);
+        cookie = txx9dmac_assign_cookie(dc, desc);
+
+        dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
+                 desc->txd.cookie, desc);
+
+        list_add_tail(&desc->desc_node, &dc->queue);
+        spin_unlock_bh(&dc->lock);
+
+        return cookie;
+}
+
+static struct dma_async_tx_descriptor *
+txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+                size_t len, unsigned long flags)
+{
+        struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
+        struct txx9dmac_dev *ddev = dc->ddev;
+        struct txx9dmac_desc *desc;
+        struct txx9dmac_desc *first;
+        struct txx9dmac_desc *prev;
+        size_t xfer_count;
+        size_t offset;
+
+        dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
+                 (u64)dest, (u64)src, len, flags);
+
+        if (unlikely(!len)) {
+                dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
+                return NULL;
+        }
+
+        prev = first = NULL;
+
+        for (offset = 0; offset < len; offset += xfer_count) {
+                xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
+                /*
+                 * Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
+                 * ERT-TX49H4-016 (slightly conservative)
+                 */
+                if (__is_dmac64(ddev)) {
+                        if (xfer_count > 0x100 &&
+                            (xfer_count & 0xff) >= 0xfa &&
+                            (xfer_count & 0xff) <= 0xff)
+                                xfer_count -= 0x20;
+                } else {
+                        if (xfer_count > 0x80 &&
+                            (xfer_count & 0x7f) >= 0x7e &&
+                            (xfer_count & 0x7f) <= 0x7f)
+                                xfer_count -= 0x20;
+                }
+
+                desc = txx9dmac_desc_get(dc);
+                if (!desc) {
+                        txx9dmac_desc_put(dc, first);
+                        return NULL;
+                }
+
+                if (__is_dmac64(ddev)) {
+                        desc->hwdesc.SAR = src + offset;
+                        desc->hwdesc.DAR = dest + offset;
+                        desc->hwdesc.CNTR = xfer_count;
+                        txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
+                                        dc->ccr | TXX9_DMA_CCR_XFACT);
+                } else {
+                        desc->hwdesc32.SAR = src + offset;
+                        desc->hwdesc32.DAR = dest + offset;
+                        desc->hwdesc32.CNTR = xfer_count;
+                        txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
+                                        dc->ccr | TXX9_DMA_CCR_XFACT);
+                }
+
+                /*
+                 * The descriptors on tx_list are not reachable from
+                 * the dc->queue list or dc->active_list after a
+                 * submit.  If we put all descriptors on active_list,
+                 * calling of callback on the completion will be more
+                 * complex.
+                 */
+                if (!first) {
+                        first = desc;
+                } else {
+                        desc_write_CHAR(dc, prev, desc->txd.phys);
+                        dma_sync_single_for_device(chan2parent(&dc->chan),
+                                        prev->txd.phys, ddev->descsize,
+                                        DMA_TO_DEVICE);
+                        list_add_tail(&desc->desc_node,
+                                        &first->txd.tx_list);
+                }
+                prev = desc;
+        }
+
+        /* Trigger interrupt after last block */
+        if (flags & DMA_PREP_INTERRUPT)
+                txx9dmac_desc_set_INTENT(ddev, prev);
+
+        desc_write_CHAR(dc, prev, 0);
+        dma_sync_single_for_device(chan2parent(&dc->chan),
+                        prev->txd.phys, ddev->descsize,
+                        DMA_TO_DEVICE);
+
+        first->txd.flags = flags;
+        first->len = len;
+
+        return &first->txd;
+}
+
+static struct dma_async_tx_descriptor *
+txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
+                unsigned int sg_len, enum dma_data_direction direction,
+                unsigned long flags)
+{
+        struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
+        struct txx9dmac_dev *ddev = dc->ddev;
+        struct txx9dmac_slave *ds = chan->private;
+        struct txx9dmac_desc *prev;
+        struct txx9dmac_desc *first;
+        unsigned int i;
+        struct scatterlist *sg;
+
+        dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
+
+        BUG_ON(!ds || !ds->reg_width);
+        if (ds->tx_reg)
+                BUG_ON(direction != DMA_TO_DEVICE);
+        else
+                BUG_ON(direction != DMA_FROM_DEVICE);
+        if (unlikely(!sg_len))
+                return NULL;
+
+        prev = first = NULL;
+
+        for_each_sg(sgl, sg, sg_len, i) {
+                struct txx9dmac_desc *desc;
+                dma_addr_t mem;
+                u32 sai, dai;
+
+                desc = txx9dmac_desc_get(dc);
+                if (!desc) {
+                        txx9dmac_desc_put(dc, first);
+                        return NULL;
+                }
+
+                mem = sg_dma_address(sg);
+
+                if (__is_dmac64(ddev)) {
+                        if (direction == DMA_TO_DEVICE) {
+                                desc->hwdesc.SAR = mem;
+                                desc->hwdesc.DAR = ds->tx_reg;
+                        } else {
+                                desc->hwdesc.SAR = ds->rx_reg;
+                                desc->hwdesc.DAR = mem;
+                        }
+                        desc->hwdesc.CNTR = sg_dma_len(sg);
+                } else {
+                        if (direction == DMA_TO_DEVICE) {
+                                desc->hwdesc32.SAR = mem;
+                                desc->hwdesc32.DAR = ds->tx_reg;
+                        } else {
+                                desc->hwdesc32.SAR = ds->rx_reg;
+                                desc->hwdesc32.DAR = mem;
+                        }
+                        desc->hwdesc32.CNTR = sg_dma_len(sg);
+                }
+                if (direction == DMA_TO_DEVICE) {
+                        sai = ds->reg_width;
+                        dai = 0;
+                } else {
+                        sai = 0;
+                        dai = ds->reg_width;
+                }
+                txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
+                                        dc->ccr | TXX9_DMA_CCR_XFACT);
+
+                if (!first) {
+                        first = desc;
+                } else {
+                        desc_write_CHAR(dc, prev, desc->txd.phys);
+                        dma_sync_single_for_device(chan2parent(&dc->chan),
+                                        prev->txd.phys,
+                                        ddev->descsize,
+                                        DMA_TO_DEVICE);
+                        list_add_tail(&desc->desc_node,
+                                        &first->txd.tx_list);
+                }
+                prev = desc;
+        }
+
+        /* Trigger interrupt after last block */
+        if (flags & DMA_PREP_INTERRUPT)
+                txx9dmac_desc_set_INTENT(ddev, prev);
+
+        desc_write_CHAR(dc, prev, 0);
+        dma_sync_single_for_device(chan2parent(&dc->chan),
+                        prev->txd.phys, ddev->descsize,
+                        DMA_TO_DEVICE);
+
+        first->txd.flags = flags;
+        first->len = 0;
+
+        return &first->txd;
+}
+
+static void txx9dmac_terminate_all(struct dma_chan *chan)
+{
+        struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
+        struct txx9dmac_desc *desc, *_desc;
+        LIST_HEAD(list);
+
+        dev_vdbg(chan2dev(chan), "terminate_all\n");
+        spin_lock_bh(&dc->lock);
+
+        txx9dmac_reset_chan(dc);
+
+        /* active_list entries will end up before queued entries */
+        list_splice_init(&dc->queue, &list);
+        list_splice_init(&dc->active_list, &list);
+
+        spin_unlock_bh(&dc->lock);
+
+        /* Flush all pending and queued descriptors */
+        list_for_each_entry_safe(desc, _desc, &list, desc_node)
+                txx9dmac_descriptor_complete(dc, desc);
+}
+
+static enum dma_status
+txx9dmac_is_tx_complete(struct dma_chan *chan,
+                        dma_cookie_t cookie,
+                dma_cookie_t *done, dma_cookie_t *used)
+{
+        struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
+        dma_cookie_t last_used;
+        dma_cookie_t last_complete;
+        int ret;
+
+        last_complete = dc->completed;
+        last_used = chan->cookie;
+
+        ret = dma_async_is_complete(cookie, last_complete, last_used);
+        if (ret != DMA_SUCCESS) {
+                spin_lock_bh(&dc->lock);
+                txx9dmac_scan_descriptors(dc);
+                spin_unlock_bh(&dc->lock);
+
+                last_complete = dc->completed;
+                last_used = chan->cookie;
+
+                ret = dma_async_is_complete(cookie, last_complete, last_used);
+        }
+
+        if (done)
+                *done = last_complete;
+        if (used)
+                *used = last_used;
+
+        return ret;
+}
+
+static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
+                                   struct txx9dmac_desc *prev)
+{
+        struct txx9dmac_dev *ddev = dc->ddev;
+        struct txx9dmac_desc *desc;
+        LIST_HEAD(list);
+
+        prev = txx9dmac_last_child(prev);
+        txx9dmac_dequeue(dc, &list);
+        desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
+        desc_write_CHAR(dc, prev, desc->txd.phys);
+        dma_sync_single_for_device(chan2parent(&dc->chan),
+                                   prev->txd.phys, ddev->descsize,
+                                   DMA_TO_DEVICE);
+        mmiowb();
+        if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
+            channel_read_CHAR(dc) == prev->txd.phys)
+                /* Restart chain DMA */
+                channel_write_CHAR(dc, desc->txd.phys);
+        list_splice_tail(&list, &dc->active_list);
+}
+
+static void txx9dmac_issue_pending(struct dma_chan *chan)
+{
+        struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
+
+        spin_lock_bh(&dc->lock);
+
+        if (!list_empty(&dc->active_list))
+                txx9dmac_scan_descriptors(dc);
+        if (!list_empty(&dc->queue)) {
+                if (list_empty(&dc->active_list)) {
+                        txx9dmac_dequeue(dc, &dc->active_list);
+                        txx9dmac_dostart(dc, txx9dmac_first_active(dc));
+                } else if (txx9_dma_have_SMPCHN()) {
+                        struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
+
+                        if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
+                            txx9dmac_chan_INTENT(dc))
+                                txx9dmac_chain_dynamic(dc, prev);
+                }
+        }
+
+        spin_unlock_bh(&dc->lock);
+}
+
+static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
+{
+        struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
+        struct txx9dmac_slave *ds = chan->private;
+        struct txx9dmac_desc *desc;
+        int i;
+
+        dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
+
+        /* ASSERT:  channel is idle */
+        if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
+                dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
+                return -EIO;
+        }
+
+        dc->completed = chan->cookie = 1;
+
+        dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
+        txx9dmac_chan_set_SMPCHN(dc);
+        if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
+                dc->ccr |= TXX9_DMA_CCR_INTENC;
+        if (chan->device->device_prep_dma_memcpy) {
+                if (ds)
+                        return -EINVAL;
+                dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
+        } else {
+                if (!ds ||
+                    (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg))
+                        return -EINVAL;
+                dc->ccr |= TXX9_DMA_CCR_EXTRQ |
+                        TXX9_DMA_CCR_XFSZ(__ffs(ds->reg_width));
+                txx9dmac_chan_set_INTENT(dc);
+        }
+
+        spin_lock_bh(&dc->lock);
+        i = dc->descs_allocated;
+        while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
+                spin_unlock_bh(&dc->lock);
+
+                desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
+                if (!desc) {
+                        dev_info(chan2dev(chan),
+                                "only allocated %d descriptors\n", i);
+                        spin_lock_bh(&dc->lock);
+                        break;
+                }
+                txx9dmac_desc_put(dc, desc);
+
+                spin_lock_bh(&dc->lock);
+                i = ++dc->descs_allocated;
+        }
+        spin_unlock_bh(&dc->lock);
+
+        dev_dbg(chan2dev(chan),
+                "alloc_chan_resources allocated %d descriptors\n", i);
+
+        return i;
+}
+
+static void txx9dmac_free_chan_resources(struct dma_chan *chan)
+{
+        struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
+        struct txx9dmac_dev *ddev = dc->ddev;
+        struct txx9dmac_desc *desc, *_desc;
+        LIST_HEAD(list);
+
+        dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
+                        dc->descs_allocated);
+
+        /* ASSERT:  channel is idle */
+        BUG_ON(!list_empty(&dc->active_list));
+        BUG_ON(!list_empty(&dc->queue));
+        BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
+
+        spin_lock_bh(&dc->lock);
+        list_splice_init(&dc->free_list, &list);
+        dc->descs_allocated = 0;
+        spin_unlock_bh(&dc->lock);
+
+        list_for_each_entry_safe(desc, _desc, &list, desc_node) {
+                dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
+                dma_unmap_single(chan2parent(chan), desc->txd.phys,
+                                 ddev->descsize, DMA_TO_DEVICE);
+                kfree(desc);
+        }
+
+        dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
+}
+
+/*----------------------------------------------------------------------*/
+
+static void txx9dmac_off(struct txx9dmac_dev *ddev)
+{
+        dma_writel(ddev, MCR, 0);
+        mmiowb();
+}
+
+static int __init txx9dmac_chan_probe(struct platform_device *pdev)
+{
+        struct txx9dmac_chan_platform_data *cpdata = pdev->dev.platform_data;
+        struct platform_device *dmac_dev = cpdata->dmac_dev;
+        struct txx9dmac_platform_data *pdata = dmac_dev->dev.platform_data;
+        struct txx9dmac_chan *dc;
+        int err;
+        int ch = pdev->id % TXX9_DMA_MAX_NR_CHANNELS;
+        int irq;
+
+        dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
+        if (!dc)
+                return -ENOMEM;
+
+        dc->dma.dev = &pdev->dev;
+        dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
+        dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
+        dc->dma.device_terminate_all = txx9dmac_terminate_all;
+        dc->dma.device_is_tx_complete = txx9dmac_is_tx_complete;
+        dc->dma.device_issue_pending = txx9dmac_issue_pending;
+        if (pdata && pdata->memcpy_chan == ch) {
+                dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
+                dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
+        } else {
+                dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
+                dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
+                dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
+        }
+
+        INIT_LIST_HEAD(&dc->dma.channels);
+        dc->ddev = platform_get_drvdata(dmac_dev);
+        if (dc->ddev->irq < 0) {
+                irq = platform_get_irq(pdev, 0);
+                if (irq < 0)
+                        return irq;
+                tasklet_init(&dc->tasklet, txx9dmac_chan_tasklet,
+                                (unsigned long)dc);
+                dc->irq = irq;
+                err = devm_request_irq(&pdev->dev, dc->irq,
+                        txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
+                if (err)
+                        return err;
+        } else
+                dc->irq = -1;
+        dc->ddev->chan[ch] = dc;
+        dc->chan.device = &dc->dma;
+        list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
+        dc->chan.cookie = dc->completed = 1;
+
+        if (is_dmac64(dc))
+                dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
+        else
+                dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
+        spin_lock_init(&dc->lock);
+
+        INIT_LIST_HEAD(&dc->active_list);
+        INIT_LIST_HEAD(&dc->queue);
+        INIT_LIST_HEAD(&dc->free_list);
+
+        txx9dmac_reset_chan(dc);
+
+        platform_set_drvdata(pdev, dc);
+
+        err = dma_async_device_register(&dc->dma);
+        if (err)
+                return err;
+        dev_dbg(&pdev->dev, "TXx9 DMA Channel (dma%d%s%s)\n",
+                dc->dma.dev_id,
+                dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
+                dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
+
+        return 0;
+}
+
+static int __exit txx9dmac_chan_remove(struct platform_device *pdev)
+{
+        struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
+
+        dma_async_device_unregister(&dc->dma);
+        if (dc->irq >= 0)
+                tasklet_kill(&dc->tasklet);
+        dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
+        return 0;
+}
+
+static int __init txx9dmac_probe(struct platform_device *pdev)
+{
+        struct txx9dmac_platform_data *pdata = pdev->dev.platform_data;
+        struct resource *io;
+        struct txx9dmac_dev *ddev;
+        u32 mcr;
+        int err;
+
+        io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!io)
+                return -EINVAL;
+
+        ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL);
+        if (!ddev)
+                return -ENOMEM;
+
+        if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io),
+                                     dev_name(&pdev->dev)))
+                return -EBUSY;
+
+        ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io));
+        if (!ddev->regs)
+                return -ENOMEM;
+        ddev->have_64bit_regs = pdata->have_64bit_regs;
+        if (__is_dmac64(ddev))
+                ddev->descsize = sizeof(struct txx9dmac_hwdesc);
+        else
+                ddev->descsize = sizeof(struct txx9dmac_hwdesc32);
+
+        /* force dma off, just in case */
+        txx9dmac_off(ddev);
+
+        ddev->irq = platform_get_irq(pdev, 0);
+        if (ddev->irq >= 0) {
+                tasklet_init(&ddev->tasklet, txx9dmac_tasklet,
+                                (unsigned long)ddev);
+                err = devm_request_irq(&pdev->dev, ddev->irq,
+                        txx9dmac_interrupt, 0, dev_name(&pdev->dev), ddev);
+                if (err)
+                        return err;
+        }
+
+        mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
+        if (pdata && pdata->memcpy_chan >= 0)
+                mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
+        dma_writel(ddev, MCR, mcr);
+
+        platform_set_drvdata(pdev, ddev);
+        return 0;
+}
+
+static int __exit txx9dmac_remove(struct platform_device *pdev)
+{
+        struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
+
+        txx9dmac_off(ddev);
+        if (ddev->irq >= 0)
+                tasklet_kill(&ddev->tasklet);
+        return 0;
+}
+
+static void txx9dmac_shutdown(struct platform_device *pdev)
+{
+        struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
+
+        txx9dmac_off(ddev);
+}
+
+static int txx9dmac_suspend_late(struct platform_device *pdev,
+                                 pm_message_t mesg)
+{
+        struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
+
+        txx9dmac_off(ddev);
+        return 0;
+}
+
+static int txx9dmac_resume_early(struct platform_device *pdev)
+{
+        struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
+        struct txx9dmac_platform_data *pdata = pdev->dev.platform_data;
+        u32 mcr;
+
+        mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
+        if (pdata && pdata->memcpy_chan >= 0)
+                mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
+        dma_writel(ddev, MCR, mcr);
+        return 0;
+
+}
+
+static struct platform_driver txx9dmac_chan_driver = {
+        .remove         = __exit_p(txx9dmac_chan_remove),
+        .driver = {
+                .name   = "txx9dmac-chan",
+        },
+};
+
+static struct platform_driver txx9dmac_driver = {
+        .remove         = __exit_p(txx9dmac_remove),
+        .shutdown       = txx9dmac_shutdown,
+        .suspend_late   = txx9dmac_suspend_late,
+        .resume_early   = txx9dmac_resume_early,
+        .driver = {
+                .name   = "txx9dmac",
+        },
+};
+
+static int __init txx9dmac_init(void)
+{
+        int rc;
+
+        rc = platform_driver_probe(&txx9dmac_driver, txx9dmac_probe);
+        if (!rc) {
+                rc = platform_driver_probe(&txx9dmac_chan_driver,
+                                           txx9dmac_chan_probe);
+                if (rc)
+                        platform_driver_unregister(&txx9dmac_driver);
+        }
+        return rc;
+}
+module_init(txx9dmac_init);
+
+static void __exit txx9dmac_exit(void)
+{
+        platform_driver_unregister(&txx9dmac_chan_driver);
+        platform_driver_unregister(&txx9dmac_driver);
+}
+module_exit(txx9dmac_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("TXx9 DMA Controller driver");
+MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
diff --git a/drivers/dma/txx9dmac.h b/drivers/dma/txx9dmac.h
new file mode 100644
index 000000000000..c907ff01d276
--- /dev/null
+++ b/drivers/dma/txx9dmac.h
@@ -0,0 +1,307 @@
+/*
+ * Driver for the TXx9 SoC DMA Controller
+ *
+ * Copyright (C) 2009 Atsushi Nemoto
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef TXX9DMAC_H
+#define TXX9DMAC_H
+
+#include <linux/dmaengine.h>
+#include <asm/txx9/dmac.h>
+
+/*
+ * Design Notes:
+ *
+ * This DMAC have four channels and one FIFO buffer.  Each channel can
+ * be configured for memory-memory or device-memory transfer, but only
+ * one channel can do alignment-free memory-memory transfer at a time
+ * while the channel should occupy the FIFO buffer for effective
+ * transfers.
+ *
+ * Instead of dynamically assign the FIFO buffer to channels, I chose
+ * make one dedicated channel for memory-memory transfer.  The
+ * dedicated channel is public.  Other channels are private and used
+ * for slave transfer.  Some devices in the SoC are wired to certain
+ * DMA channel.
+ */
+
+#ifdef CONFIG_MACH_TX49XX
+static inline bool txx9_dma_have_SMPCHN(void)
+{
+        return true;
+}
+#define TXX9_DMA_USE_SIMPLE_CHAIN
+#else
+static inline bool txx9_dma_have_SMPCHN(void)
+{
+        return false;
+}
+#endif
+
+#ifdef __LITTLE_ENDIAN
+#ifdef CONFIG_MACH_TX49XX
+#define CCR_LE  TXX9_DMA_CCR_LE
+#define MCR_LE  0
+#else
+#define CCR_LE  0
+#define MCR_LE  TXX9_DMA_MCR_LE
+#endif
+#else
+#define CCR_LE  0
+#define MCR_LE  0
+#endif
+
+/*
+ * Redefine this macro to handle differences between 32- and 64-bit
+ * addressing, big vs. little endian, etc.
+ */
+#ifdef __BIG_ENDIAN
+#define TXX9_DMA_REG32(name)            u32 __pad_##name; u32 name
+#else
+#define TXX9_DMA_REG32(name)            u32 name; u32 __pad_##name
+#endif
+
+/* Hardware register definitions. */
+struct txx9dmac_cregs {
+#if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR)
+        TXX9_DMA_REG32(CHAR);   /* Chain Address Register */
+#else
+        u64 CHAR;               /* Chain Address Register */
+#endif
+        u64 SAR;                /* Source Address Register */
+        u64 DAR;                /* Destination Address Register */
+        TXX9_DMA_REG32(CNTR);   /* Count Register */
+        TXX9_DMA_REG32(SAIR);   /* Source Address Increment Register */
+        TXX9_DMA_REG32(DAIR);   /* Destination Address Increment Register */
+        TXX9_DMA_REG32(CCR);    /* Channel Control Register */
+        TXX9_DMA_REG32(CSR);    /* Channel Status Register */
+};
+struct txx9dmac_cregs32 {
+        u32 CHAR;
+        u32 SAR;
+        u32 DAR;
+        u32 CNTR;
+        u32 SAIR;
+        u32 DAIR;
+        u32 CCR;
+        u32 CSR;
+};
+
+struct txx9dmac_regs {
+        /* per-channel registers */
+        struct txx9dmac_cregs   CHAN[TXX9_DMA_MAX_NR_CHANNELS];
+        u64     __pad[9];
+        u64     MFDR;           /* Memory Fill Data Register */
+        TXX9_DMA_REG32(MCR);    /* Master Control Register */
+};
+struct txx9dmac_regs32 {
+        struct txx9dmac_cregs32 CHAN[TXX9_DMA_MAX_NR_CHANNELS];
+        u32     __pad[9];
+        u32     MFDR;
+        u32     MCR;
+};
+
+/* bits for MCR */
+#define TXX9_DMA_MCR_EIS(ch)    (0x10000000<<(ch))
+#define TXX9_DMA_MCR_DIS(ch)    (0x01000000<<(ch))
+#define TXX9_DMA_MCR_RSFIF      0x00000080
+#define TXX9_DMA_MCR_FIFUM(ch)  (0x00000008<<(ch))
+#define TXX9_DMA_MCR_LE         0x00000004
+#define TXX9_DMA_MCR_RPRT       0x00000002
+#define TXX9_DMA_MCR_MSTEN      0x00000001
+
+/* bits for CCRn */
+#define TXX9_DMA_CCR_IMMCHN     0x20000000
+#define TXX9_DMA_CCR_USEXFSZ    0x10000000
+#define TXX9_DMA_CCR_LE         0x08000000
+#define TXX9_DMA_CCR_DBINH      0x04000000
+#define TXX9_DMA_CCR_SBINH      0x02000000
+#define TXX9_DMA_CCR_CHRST      0x01000000
+#define TXX9_DMA_CCR_RVBYTE     0x00800000
+#define TXX9_DMA_CCR_ACKPOL     0x00400000
+#define TXX9_DMA_CCR_REQPL      0x00200000
+#define TXX9_DMA_CCR_EGREQ      0x00100000
+#define TXX9_DMA_CCR_CHDN       0x00080000
+#define TXX9_DMA_CCR_DNCTL      0x00060000
+#define TXX9_DMA_CCR_EXTRQ      0x00010000
+#define TXX9_DMA_CCR_INTRQD     0x0000e000
+#define TXX9_DMA_CCR_INTENE     0x00001000
+#define TXX9_DMA_CCR_INTENC     0x00000800
+#define TXX9_DMA_CCR_INTENT     0x00000400
+#define TXX9_DMA_CCR_CHNEN      0x00000200
+#define TXX9_DMA_CCR_XFACT      0x00000100
+#define TXX9_DMA_CCR_SMPCHN     0x00000020
+#define TXX9_DMA_CCR_XFSZ(order)        (((order) << 2) & 0x0000001c)
+#define TXX9_DMA_CCR_XFSZ_1     TXX9_DMA_CCR_XFSZ(0)
+#define TXX9_DMA_CCR_XFSZ_2     TXX9_DMA_CCR_XFSZ(1)
+#define TXX9_DMA_CCR_XFSZ_4     TXX9_DMA_CCR_XFSZ(2)
+#define TXX9_DMA_CCR_XFSZ_8     TXX9_DMA_CCR_XFSZ(3)
+#define TXX9_DMA_CCR_XFSZ_X4    TXX9_DMA_CCR_XFSZ(4)
+#define TXX9_DMA_CCR_XFSZ_X8    TXX9_DMA_CCR_XFSZ(5)
+#define TXX9_DMA_CCR_XFSZ_X16   TXX9_DMA_CCR_XFSZ(6)
+#define TXX9_DMA_CCR_XFSZ_X32   TXX9_DMA_CCR_XFSZ(7)
+#define TXX9_DMA_CCR_MEMIO      0x00000002
+#define TXX9_DMA_CCR_SNGAD      0x00000001
+
+/* bits for CSRn */
+#define TXX9_DMA_CSR_CHNEN      0x00000400
+#define TXX9_DMA_CSR_STLXFER    0x00000200
+#define TXX9_DMA_CSR_XFACT      0x00000100
+#define TXX9_DMA_CSR_ABCHC      0x00000080
+#define TXX9_DMA_CSR_NCHNC      0x00000040
+#define TXX9_DMA_CSR_NTRNFC     0x00000020
+#define TXX9_DMA_CSR_EXTDN      0x00000010
+#define TXX9_DMA_CSR_CFERR      0x00000008
+#define TXX9_DMA_CSR_CHERR      0x00000004
+#define TXX9_DMA_CSR_DESERR     0x00000002
+#define TXX9_DMA_CSR_SORERR     0x00000001
+
+struct txx9dmac_chan {
+        struct dma_chan         chan;
+        struct dma_device       dma;
+        struct txx9dmac_dev     *ddev;
+        void __iomem            *ch_regs;
+        struct tasklet_struct   tasklet;
+        int                     irq;
+        u32                     ccr;
+
+        spinlock_t              lock;
+
+        /* these other elements are all protected by lock */
+        dma_cookie_t            completed;
+        struct list_head        active_list;
+        struct list_head        queue;
+        struct list_head        free_list;
+
+        unsigned int            descs_allocated;
+};
+
+struct txx9dmac_dev {
+        void __iomem            *regs;
+        struct tasklet_struct   tasklet;
+        int                     irq;
+        struct txx9dmac_chan    *chan[TXX9_DMA_MAX_NR_CHANNELS];
+        bool                    have_64bit_regs;
+        unsigned int            descsize;
+};
+
+static inline bool __is_dmac64(const struct txx9dmac_dev *ddev)
+{
+        return ddev->have_64bit_regs;
+}
+
+static inline bool is_dmac64(const struct txx9dmac_chan *dc)
+{
+        return __is_dmac64(dc->ddev);
+}
+
+#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
+/* Hardware descriptor definition. (for simple-chain) */
+struct txx9dmac_hwdesc {
+#if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR)
+        TXX9_DMA_REG32(CHAR);
+#else
+        u64 CHAR;
+#endif
+        u64 SAR;
+        u64 DAR;
+        TXX9_DMA_REG32(CNTR);
+};
+struct txx9dmac_hwdesc32 {
+        u32 CHAR;
+        u32 SAR;
+        u32 DAR;
+        u32 CNTR;
+};
+#else
+#define txx9dmac_hwdesc txx9dmac_cregs
+#define txx9dmac_hwdesc32 txx9dmac_cregs32
+#endif
+
+struct txx9dmac_desc {
+        /* FIRST values the hardware uses */
+        union {
+                struct txx9dmac_hwdesc hwdesc;
+                struct txx9dmac_hwdesc32 hwdesc32;
+        };
+
+        /* THEN values for driver housekeeping */
+        struct list_head                desc_node ____cacheline_aligned;
+        struct dma_async_tx_descriptor  txd;
+        size_t                          len;
+};
+
+#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
+
+static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc)
+{
+        return (dc->ccr & TXX9_DMA_CCR_INTENT) != 0;
+}
+
+static inline void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc)
+{
+        dc->ccr |= TXX9_DMA_CCR_INTENT;
+}
+
+static inline void txx9dmac_desc_set_INTENT(struct txx9dmac_dev *ddev,
+                                            struct txx9dmac_desc *desc)
+{
+}
+
+static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc)
+{
+        dc->ccr |= TXX9_DMA_CCR_SMPCHN;
+}
+
+static inline void txx9dmac_desc_set_nosimple(struct txx9dmac_dev *ddev,
+                                              struct txx9dmac_desc *desc,
+                                              u32 sair, u32 dair, u32 ccr)
+{
+}
+
+#else /* TXX9_DMA_USE_SIMPLE_CHAIN */
+
+static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc)
+{
+        return true;
+}
+
+static void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc)
+{
+}
+
+static inline void txx9dmac_desc_set_INTENT(struct txx9dmac_dev *ddev,
+                                            struct txx9dmac_desc *desc)
+{
+        if (__is_dmac64(ddev))
+                desc->hwdesc.CCR |= TXX9_DMA_CCR_INTENT;
+        else
+                desc->hwdesc32.CCR |= TXX9_DMA_CCR_INTENT;
+}
+
+static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc)
+{
+}
+
+static inline void txx9dmac_desc_set_nosimple(struct txx9dmac_dev *ddev,
+                                              struct txx9dmac_desc *desc,
+                                              u32 sai, u32 dai, u32 ccr)
+{
+        if (__is_dmac64(ddev)) {
+                desc->hwdesc.SAIR = sai;
+                desc->hwdesc.DAIR = dai;
+                desc->hwdesc.CCR = ccr;
+        } else {
+                desc->hwdesc32.SAIR = sai;
+                desc->hwdesc32.DAIR = dai;
+                desc->hwdesc32.CCR = ccr;
+        }
+}
+
+#endif /* TXX9_DMA_USE_SIMPLE_CHAIN */
+
+#endif /* TXX9DMAC_H */
diff --git a/drivers/eisa/eisa.ids b/drivers/eisa/eisa.ids
index ed69837d8b74..6cbb7a514436 100644
--- a/drivers/eisa/eisa.ids
+++ b/drivers/eisa/eisa.ids
@@ -1140,6 +1140,11 @@ NON0301 "c't Universale Graphic Adapter"
 NON0401 "c't Universal Ethernet Adapter"
 NON0501 "c't Universal 16-Bit Sound Adapter"
 NON0601 "c't Universal 8-Bit Adapter"
+NPI0120 "Network Peripherals NP-EISA-1 FDDI Interface"
+NPI0221 "Network Peripherals NP-EISA-2 FDDI Interface"
+NPI0223 "Network Peripherals NP-EISA-2E Enhanced FDDI Interface"
+NPI0301 "Network Peripherals NP-EISA-3 FDDI Interface"
+NPI0303 "Network Peripherals NP-EISA-3E Enhanced FDDI Interface"
 NSS0011 "Newport Systems Solutions WNIC Adapter"
 NVL0701 "Novell NE3200 Bus Master Ethernet"
 NVL0702 "Novell NE3200T Bus Master Ethernet"
diff --git a/drivers/eisa/pci_eisa.c b/drivers/eisa/pci_eisa.c
index 74edb1d0110f..0dd0f633b18d 100644
--- a/drivers/eisa/pci_eisa.c
+++ b/drivers/eisa/pci_eisa.c
@@ -31,11 +31,11 @@ static int __init pci_eisa_init(struct pci_dev *pdev,
         }
 
         pci_eisa_root.dev              = &pdev->dev;
-        pci_eisa_root.dev->driver_data = &pci_eisa_root;
         pci_eisa_root.res              = pdev->bus->resource[0];
         pci_eisa_root.bus_base_addr    = pdev->bus->resource[0]->start;
         pci_eisa_root.slots            = EISA_MAX_SLOTS;
         pci_eisa_root.dma_mask         = pdev->dma_mask;
+        dev_set_drvdata(pci_eisa_root.dev, &pci_eisa_root);
 
         if (eisa_root_register (&pci_eisa_root)) {
                 printk (KERN_ERR "pci_eisa : Could not register EISA root\n");
diff --git a/drivers/eisa/virtual_root.c b/drivers/eisa/virtual_root.c
index 3074879f231f..535e4f9c83f4 100644
--- a/drivers/eisa/virtual_root.c
+++ b/drivers/eisa/virtual_root.c
@@ -57,7 +57,7 @@ static int __init virtual_eisa_root_init (void)
 
         eisa_bus_root.force_probe = force_probe;
         
-        eisa_root_dev.dev.driver_data = &eisa_bus_root;
+        dev_set_drvdata(&eisa_root_dev.dev, &eisa_bus_root);
 
         if (eisa_root_register (&eisa_bus_root)) {
                 /* A real bridge may have been registered before
diff --git a/drivers/firewire/Makefile b/drivers/firewire/Makefile
index a7c31e9039c1..bc3b9bf822bf 100644
--- a/drivers/firewire/Makefile
+++ b/drivers/firewire/Makefile
@@ -2,10 +2,10 @@
 # Makefile for the Linux IEEE 1394 implementation
 #
 
-firewire-core-y += fw-card.o fw-topology.o fw-transaction.o fw-iso.o \
-                   fw-device.o fw-cdev.o
-firewire-ohci-y += fw-ohci.o
-firewire-sbp2-y += fw-sbp2.o
+firewire-core-y += core-card.o core-cdev.o core-device.o \
+                   core-iso.o core-topology.o core-transaction.o
+firewire-ohci-y += ohci.o
+firewire-sbp2-y += sbp2.o
 
 obj-$(CONFIG_FIREWIRE) += firewire-core.o
 obj-$(CONFIG_FIREWIRE_OHCI) += firewire-ohci.o
diff --git a/drivers/firewire/fw-card.c b/drivers/firewire/core-card.c
index 8b8c8c22f0fc..4c1be64fdddd 100644
--- a/drivers/firewire/fw-card.c
+++ b/drivers/firewire/core-card.c
@@ -16,18 +16,27 @@
  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
+#include <linux/bug.h>
 #include <linux/completion.h>
 #include <linux/crc-itu-t.h>
-#include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/errno.h>
+#include <linux/firewire.h>
+#include <linux/firewire-constants.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
 #include <linux/kref.h>
+#include <linux/list.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/timer.h>
+#include <linux/workqueue.h>
 
-#include "fw-transaction.h"
-#include "fw-topology.h"
-#include "fw-device.h"
+#include <asm/atomic.h>
+#include <asm/byteorder.h>
+
+#include "core.h"
 
 int fw_compute_block_crc(u32 *block)
 {
@@ -181,12 +190,6 @@ void fw_core_remove_descriptor(struct fw_descriptor *desc)
         mutex_unlock(&card_mutex);
 }
 
-static int set_broadcast_channel(struct device *dev, void *data)
-{
-        fw_device_set_broadcast_channel(fw_device(dev), (long)data);
-        return 0;
-}
-
 static void allocate_broadcast_channel(struct fw_card *card, int generation)
 {
         int channel, bandwidth = 0;
@@ -196,7 +199,7 @@ static void allocate_broadcast_channel(struct fw_card *card, int generation)
         if (channel == 31) {
                 card->broadcast_channel_allocated = true;
                 device_for_each_child(card->device, (void *)(long)generation,
-                                      set_broadcast_channel);
+                                      fw_device_set_broadcast_channel);
         }
 }
 
diff --git a/drivers/firewire/fw-cdev.c b/drivers/firewire/core-cdev.c
index 7eb6594cc3e5..d1d30c615b0f 100644
--- a/drivers/firewire/fw-cdev.c
+++ b/drivers/firewire/core-cdev.c
@@ -22,6 +22,7 @@
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/errno.h>
+#include <linux/firewire.h>
 #include <linux/firewire-cdev.h>
 #include <linux/idr.h>
 #include <linux/jiffies.h>
@@ -34,16 +35,14 @@
 #include <linux/preempt.h>
 #include <linux/spinlock.h>
 #include <linux/time.h>
+#include <linux/uaccess.h>
 #include <linux/vmalloc.h>
 #include <linux/wait.h>
 #include <linux/workqueue.h>
 
 #include <asm/system.h>
-#include <asm/uaccess.h>
 
-#include "fw-device.h"
-#include "fw-topology.h"
-#include "fw-transaction.h"
+#include "core.h"
 
 struct client {
         u32 version;
@@ -739,15 +738,11 @@ static void release_descriptor(struct client *client,
 static int ioctl_add_descriptor(struct client *client, void *buffer)
 {
         struct fw_cdev_add_descriptor *request = buffer;
-        struct fw_card *card = client->device->card;
         struct descriptor_resource *r;
         int ret;
 
         /* Access policy: Allow this ioctl only on local nodes' device files. */
-        spin_lock_irq(&card->lock);
-        ret = client->device->node_id != card->local_node->node_id;
-        spin_unlock_irq(&card->lock);
-        if (ret)
+        if (!client->device->is_local)
                 return -ENOSYS;
 
         if (request->length > 256)
diff --git a/drivers/firewire/fw-device.c b/drivers/firewire/core-device.c
index a47e2129d83d..97e656af2d22 100644
--- a/drivers/firewire/fw-device.c
+++ b/drivers/firewire/core-device.c
@@ -22,10 +22,14 @@
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/errno.h>
+#include <linux/firewire.h>
+#include <linux/firewire-constants.h>
 #include <linux/idr.h>
 #include <linux/jiffies.h>
 #include <linux/kobject.h>
 #include <linux/list.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/rwsem.h>
 #include <linux/semaphore.h>
@@ -33,11 +37,11 @@
 #include <linux/string.h>
 #include <linux/workqueue.h>
 
+#include <asm/atomic.h>
+#include <asm/byteorder.h>
 #include <asm/system.h>
 
-#include "fw-device.h"
-#include "fw-topology.h"
-#include "fw-transaction.h"
+#include "core.h"
 
 void fw_csr_iterator_init(struct fw_csr_iterator *ci, u32 * p)
 {
@@ -55,9 +59,10 @@ int fw_csr_iterator_next(struct fw_csr_iterator *ci, int *key, int *value)
 }
 EXPORT_SYMBOL(fw_csr_iterator_next);
 
-static int is_fw_unit(struct device *dev);
+static bool is_fw_unit(struct device *dev);
 
-static int match_unit_directory(u32 * directory, const struct fw_device_id *id)
+static int match_unit_directory(u32 *directory, u32 match_flags,
+                                const struct ieee1394_device_id *id)
 {
         struct fw_csr_iterator ci;
         int key, value, match;
@@ -65,31 +70,42 @@ static int match_unit_directory(u32 * directory, const struct fw_device_id *id)
         match = 0;
         fw_csr_iterator_init(&ci, directory);
         while (fw_csr_iterator_next(&ci, &key, &value)) {
-                if (key == CSR_VENDOR && value == id->vendor)
-                        match |= FW_MATCH_VENDOR;
-                if (key == CSR_MODEL && value == id->model)
-                        match |= FW_MATCH_MODEL;
+                if (key == CSR_VENDOR && value == id->vendor_id)
+                        match |= IEEE1394_MATCH_VENDOR_ID;
+                if (key == CSR_MODEL && value == id->model_id)
+                        match |= IEEE1394_MATCH_MODEL_ID;
                 if (key == CSR_SPECIFIER_ID && value == id->specifier_id)
-                        match |= FW_MATCH_SPECIFIER_ID;
+                        match |= IEEE1394_MATCH_SPECIFIER_ID;
                 if (key == CSR_VERSION && value == id->version)
-                        match |= FW_MATCH_VERSION;
+                        match |= IEEE1394_MATCH_VERSION;
         }
 
-        return (match & id->match_flags) == id->match_flags;
+        return (match & match_flags) == match_flags;
 }
 
 static int fw_unit_match(struct device *dev, struct device_driver *drv)
 {
         struct fw_unit *unit = fw_unit(dev);
-        struct fw_driver *driver = fw_driver(drv);
-        int i;
+        struct fw_device *device;
+        const struct ieee1394_device_id *id;
 
         /* We only allow binding to fw_units. */
         if (!is_fw_unit(dev))
                 return 0;
 
-        for (i = 0; driver->id_table[i].match_flags != 0; i++) {
-                if (match_unit_directory(unit->directory, &driver->id_table[i]))
+        device = fw_parent_device(unit);
+        id = container_of(drv, struct fw_driver, driver)->id_table;
+
+        for (; id->match_flags != 0; id++) {
+                if (match_unit_directory(unit->directory, id->match_flags, id))
+                        return 1;
+
+                /* Also check vendor ID in the root directory. */
+                if ((id->match_flags & IEEE1394_MATCH_VENDOR_ID) &&
+                    match_unit_directory(&device->config_rom[5],
+                                IEEE1394_MATCH_VENDOR_ID, id) &&
+                    match_unit_directory(unit->directory, id->match_flags
+                                & ~IEEE1394_MATCH_VENDOR_ID, id))
                         return 1;
         }
 
@@ -98,7 +114,7 @@ static int fw_unit_match(struct device *dev, struct device_driver *drv)
 
 static int get_modalias(struct fw_unit *unit, char *buffer, size_t buffer_size)
 {
-        struct fw_device *device = fw_device(unit->device.parent);
+        struct fw_device *device = fw_parent_device(unit);
         struct fw_csr_iterator ci;
 
         int key, value;
@@ -292,8 +308,7 @@ static void init_fw_attribute_group(struct device *dev,
                 group->attrs[j++] = &attr->attr;
         }
 
-        BUG_ON(j >= ARRAY_SIZE(group->attrs));
-        group->attrs[j++] = NULL;
+        group->attrs[j] = NULL;
         group->groups[0] = &group->group;
         group->groups[1] = NULL;
         group->group.attrs = group->attrs;
@@ -356,9 +371,56 @@ static ssize_t guid_show(struct device *dev,
         return ret;
 }
 
+static int units_sprintf(char *buf, u32 *directory)
+{
+        struct fw_csr_iterator ci;
+        int key, value;
+        int specifier_id = 0;
+        int version = 0;
+
+        fw_csr_iterator_init(&ci, directory);
+        while (fw_csr_iterator_next(&ci, &key, &value)) {
+                switch (key) {
+                case CSR_SPECIFIER_ID:
+                        specifier_id = value;
+                        break;
+                case CSR_VERSION:
+                        version = value;
+                        break;
+                }
+        }
+
+        return sprintf(buf, "0x%06x:0x%06x ", specifier_id, version);
+}
+
+static ssize_t units_show(struct device *dev,
+                          struct device_attribute *attr, char *buf)
+{
+        struct fw_device *device = fw_device(dev);
+        struct fw_csr_iterator ci;
+        int key, value, i = 0;
+
+        down_read(&fw_device_rwsem);
+        fw_csr_iterator_init(&ci, &device->config_rom[5]);
+        while (fw_csr_iterator_next(&ci, &key, &value)) {
+                if (key != (CSR_UNIT | CSR_DIRECTORY))
+                        continue;
+                i += units_sprintf(&buf[i], ci.p + value - 1);
+                if (i >= PAGE_SIZE - (8 + 1 + 8 + 1))
+                        break;
+        }
+        up_read(&fw_device_rwsem);
+
+        if (i)
+                buf[i - 1] = '\n';
+
+        return i;
+}
+
 static struct device_attribute fw_device_attributes[] = {
         __ATTR_RO(config_rom),
         __ATTR_RO(guid),
+        __ATTR_RO(units),
         __ATTR_NULL,
 };
 
@@ -518,7 +580,9 @@ static int read_bus_info_block(struct fw_device *device, int generation)
 
         kfree(old_rom);
         ret = 0;
-        device->cmc = rom[2] >> 30 & 1;
+        device->max_rec = rom[2] >> 12 & 0xf;
+        device->cmc     = rom[2] >> 30 & 1;
+        device->irmc    = rom[2] >> 31 & 1;
  out:
         kfree(rom);
 
@@ -537,7 +601,7 @@ static struct device_type fw_unit_type = {
         .release        = fw_unit_release,
 };
 
-static int is_fw_unit(struct device *dev)
+static bool is_fw_unit(struct device *dev)
 {
         return dev->type == &fw_unit_type;
 }
@@ -570,9 +634,13 @@ static void create_units(struct fw_device *device)
                 unit->device.parent = &device->device;
                 dev_set_name(&unit->device, "%s.%d", dev_name(&device->device), i++);
 
+                BUILD_BUG_ON(ARRAY_SIZE(unit->attribute_group.attrs) <
+                                ARRAY_SIZE(fw_unit_attributes) +
+                                ARRAY_SIZE(config_rom_attributes));
                 init_fw_attribute_group(&unit->device,
                                         fw_unit_attributes,
                                         &unit->attribute_group);
+
                 if (device_register(&unit->device) < 0)
                         goto skip_unit;
 
@@ -683,6 +751,11 @@ static struct device_type fw_device_type = {
         .release = fw_device_release,
 };
 
+static bool is_fw_device(struct device *dev)
+{
+        return dev->type == &fw_device_type;
+}
+
 static int update_unit(struct device *dev, void *data)
 {
         struct fw_unit *unit = fw_unit(dev);
@@ -719,6 +792,9 @@ static int lookup_existing_device(struct device *dev, void *data)
         struct fw_card *card = new->card;
         int match = 0;
 
+        if (!is_fw_device(dev))
+                return 0;
+
         down_read(&fw_device_rwsem); /* serialize config_rom access */
         spin_lock_irq(&card->lock);  /* serialize node access */
 
@@ -758,7 +834,7 @@ static int lookup_existing_device(struct device *dev, void *data)
 
 enum { BC_UNKNOWN = 0, BC_UNIMPLEMENTED, BC_IMPLEMENTED, };
 
-void fw_device_set_broadcast_channel(struct fw_device *device, int generation)
+static void set_broadcast_channel(struct fw_device *device, int generation)
 {
         struct fw_card *card = device->card;
         __be32 data;
@@ -767,6 +843,20 @@ void fw_device_set_broadcast_channel(struct fw_device *device, int generation)
         if (!card->broadcast_channel_allocated)
                 return;
 
+        /*
+         * The Broadcast_Channel Valid bit is required by nodes which want to
+         * transmit on this channel.  Such transmissions are practically
+         * exclusive to IP over 1394 (RFC 2734).  IP capable nodes are required
+         * to be IRM capable and have a max_rec of 8 or more.  We use this fact
+         * to narrow down to which nodes we send Broadcast_Channel updates.
+         */
+        if (!device->irmc || device->max_rec < 8)
+                return;
+
+        /*
+         * Some 1394-1995 nodes crash if this 1394a-2000 register is written.
+         * Perform a read test first.
+         */
         if (device->bc_implemented == BC_UNKNOWN) {
                 rcode = fw_run_transaction(card, TCODE_READ_QUADLET_REQUEST,
                                 device->node_id, generation, device->max_speed,
@@ -794,6 +884,14 @@ void fw_device_set_broadcast_channel(struct fw_device *device, int generation)
         }
 }
 
+int fw_device_set_broadcast_channel(struct device *dev, void *gen)
+{
+        if (is_fw_device(dev))
+                set_broadcast_channel(fw_device(dev), (long)gen);
+
+        return 0;
+}
+
 static void fw_device_init(struct work_struct *work)
 {
         struct fw_device *device =
@@ -849,9 +947,13 @@ static void fw_device_init(struct work_struct *work)
         device->device.devt = MKDEV(fw_cdev_major, minor);
         dev_set_name(&device->device, "fw%d", minor);
 
+        BUILD_BUG_ON(ARRAY_SIZE(device->attribute_group.attrs) <
+                        ARRAY_SIZE(fw_device_attributes) +
+                        ARRAY_SIZE(config_rom_attributes));
         init_fw_attribute_group(&device->device,
                                 fw_device_attributes,
                                 &device->attribute_group);
+
         if (device_add(&device->device)) {
                 fw_error("Failed to add device.\n");
                 goto error_with_cdev;
@@ -888,7 +990,7 @@ static void fw_device_init(struct work_struct *work)
                                   1 << device->max_speed);
                 device->config_rom_retries = 0;
 
-                fw_device_set_broadcast_channel(device, device->generation);
+                set_broadcast_channel(device, device->generation);
         }
 
         /*
@@ -993,6 +1095,9 @@ static void fw_device_refresh(struct work_struct *work)
 
         create_units(device);
 
+        /* Userspace may want to re-read attributes. */
+        kobject_uevent(&device->device.kobj, KOBJ_CHANGE);
+
         if (atomic_cmpxchg(&device->state,
                            FW_DEVICE_INITIALIZING,
                            FW_DEVICE_RUNNING) == FW_DEVICE_GONE)
@@ -1042,6 +1147,7 @@ void fw_node_event(struct fw_card *card, struct fw_node *node, int event)
                 device->node = fw_node_get(node);
                 device->node_id = node->node_id;
                 device->generation = card->generation;
+                device->is_local = node == card->local_node;
                 mutex_init(&device->client_list_mutex);
                 INIT_LIST_HEAD(&device->client_list);
 
@@ -1075,7 +1181,7 @@ void fw_node_event(struct fw_card *card, struct fw_node *node, int event)
                             FW_DEVICE_INITIALIZING) == FW_DEVICE_RUNNING) {
                         PREPARE_DELAYED_WORK(&device->work, fw_device_refresh);
                         schedule_delayed_work(&device->work,
-                                node == card->local_node ? 0 : INITIAL_DELAY);
+                                device->is_local ? 0 : INITIAL_DELAY);
                 }
                 break;
 
diff --git a/drivers/firewire/fw-iso.c b/drivers/firewire/core-iso.c
index 2baf1007253e..28076c892d7e 100644
--- a/drivers/firewire/fw-iso.c
+++ b/drivers/firewire/core-iso.c
@@ -22,14 +22,16 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/errno.h>
+#include <linux/firewire.h>
 #include <linux/firewire-constants.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
 #include <linux/spinlock.h>
 #include <linux/vmalloc.h>
 
-#include "fw-topology.h"
-#include "fw-transaction.h"
+#include <asm/byteorder.h>
+
+#include "core.h"
 
 /*
  * Isochronous DMA context management
diff --git a/drivers/firewire/fw-topology.c b/drivers/firewire/core-topology.c
index d0deecc4de93..fddf2b358936 100644
--- a/drivers/firewire/fw-topology.c
+++ b/drivers/firewire/core-topology.c
@@ -18,13 +18,22 @@
  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
-#include <linux/module.h>
-#include <linux/wait.h>
+#include <linux/bug.h>
 #include <linux/errno.h>
-#include <asm/bug.h>
+#include <linux/firewire.h>
+#include <linux/firewire-constants.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+
+#include <asm/atomic.h>
 #include <asm/system.h>
-#include "fw-transaction.h"
-#include "fw-topology.h"
+
+#include "core.h"
 
 #define SELF_ID_PHY_ID(q)               (((q) >> 24) & 0x3f)
 #define SELF_ID_EXTENDED(q)             (((q) >> 23) & 0x01)
@@ -37,6 +46,11 @@
 
 #define SELF_ID_EXT_SEQUENCE(q)         (((q) >> 20) & 0x07)
 
+#define SELFID_PORT_CHILD       0x3
+#define SELFID_PORT_PARENT      0x2
+#define SELFID_PORT_NCONN       0x1
+#define SELFID_PORT_NONE        0x0
+
 static u32 *count_ports(u32 *sid, int *total_port_count, int *child_port_count)
 {
         u32 q;
diff --git a/drivers/firewire/fw-transaction.c b/drivers/firewire/core-transaction.c
index 283dac6d327d..479b22f5a1eb 100644
--- a/drivers/firewire/fw-transaction.c
+++ b/drivers/firewire/core-transaction.c
@@ -18,24 +18,28 @@
  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  */
 
+#include <linux/bug.h>
 #include <linux/completion.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/firewire.h>
+#include <linux/firewire-constants.h>
+#include <linux/fs.h>
+#include <linux/init.h>
 #include <linux/idr.h>
+#include <linux/jiffies.h>
 #include <linux/kernel.h>
-#include <linux/kref.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/poll.h>
 #include <linux/list.h>
-#include <linux/kthread.h>
-#include <asm/uaccess.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/types.h>
 
-#include "fw-transaction.h"
-#include "fw-topology.h"
-#include "fw-device.h"
+#include <asm/byteorder.h>
+
+#include "core.h"
 
 #define HEADER_PRI(pri)                 ((pri) << 0)
 #define HEADER_TCODE(tcode)             ((tcode) << 4)
@@ -60,6 +64,10 @@
 #define HEADER_DESTINATION_IS_BROADCAST(q) \
         (((q) & HEADER_DESTINATION(0x3f)) == HEADER_DESTINATION(0x3f))
 
+#define PHY_PACKET_CONFIG       0x0
+#define PHY_PACKET_LINK_ON      0x1
+#define PHY_PACKET_SELF_ID      0x2
+
 #define PHY_CONFIG_GAP_COUNT(gap_count) (((gap_count) << 16) | (1 << 22))
 #define PHY_CONFIG_ROOT_ID(node_id)     ((((node_id) & 0x3f) << 24) | (1 << 23))
 #define PHY_IDENTIFIER(id)              ((id) << 30)
@@ -74,7 +82,7 @@ static int close_transaction(struct fw_transaction *transaction,
         list_for_each_entry(t, &card->transaction_list, link) {
                 if (t == transaction) {
                         list_del(&t->link);
-                        card->tlabel_mask &= ~(1 << t->tlabel);
+                        card->tlabel_mask &= ~(1ULL << t->tlabel);
                         break;
                 }
         }
@@ -280,14 +288,14 @@ void fw_send_request(struct fw_card *card, struct fw_transaction *t, int tcode,
         spin_lock_irqsave(&card->lock, flags);
 
         tlabel = card->current_tlabel;
-        if (card->tlabel_mask & (1 << tlabel)) {
+        if (card->tlabel_mask & (1ULL << tlabel)) {
                 spin_unlock_irqrestore(&card->lock, flags);
                 callback(card, RCODE_SEND_ERROR, NULL, 0, callback_data);
                 return;
         }
 
-        card->current_tlabel = (card->current_tlabel + 1) & 0x1f;
-        card->tlabel_mask |= (1 << tlabel);
+        card->current_tlabel = (card->current_tlabel + 1) & 0x3f;
+        card->tlabel_mask |= (1ULL << tlabel);
 
         t->node_id = destination_id;
         t->tlabel = tlabel;
diff --git a/drivers/firewire/core.h b/drivers/firewire/core.h
new file mode 100644
index 000000000000..0a25a7b38a80
--- /dev/null
+++ b/drivers/firewire/core.h
@@ -0,0 +1,293 @@
+#ifndef _FIREWIRE_CORE_H
+#define _FIREWIRE_CORE_H
+
+#include <linux/dma-mapping.h>
+#include <linux/fs.h>
+#include <linux/list.h>
+#include <linux/idr.h>
+#include <linux/mm_types.h>
+#include <linux/rwsem.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include <asm/atomic.h>
+
+struct device;
+struct fw_card;
+struct fw_device;
+struct fw_iso_buffer;
+struct fw_iso_context;
+struct fw_iso_packet;
+struct fw_node;
+struct fw_packet;
+
+
+/* -card */
+
+/* bitfields within the PHY registers */
+#define PHY_LINK_ACTIVE         0x80
+#define PHY_CONTENDER           0x40
+#define PHY_BUS_RESET           0x40
+#define PHY_BUS_SHORT_RESET     0x40
+
+#define BANDWIDTH_AVAILABLE_INITIAL     4915
+#define BROADCAST_CHANNEL_INITIAL       (1 << 31 | 31)
+#define BROADCAST_CHANNEL_VALID         (1 << 30)
+
+struct fw_card_driver {
+        /*
+         * Enable the given card with the given initial config rom.
+         * This function is expected to activate the card, and either
+         * enable the PHY or set the link_on bit and initiate a bus
+         * reset.
+         */
+        int (*enable)(struct fw_card *card, u32 *config_rom, size_t length);
+
+        int (*update_phy_reg)(struct fw_card *card, int address,
+                              int clear_bits, int set_bits);
+
+        /*
+         * Update the config rom for an enabled card.  This function
+         * should change the config rom that is presented on the bus
+         * an initiate a bus reset.
+         */
+        int (*set_config_rom)(struct fw_card *card,
+                              u32 *config_rom, size_t length);
+
+        void (*send_request)(struct fw_card *card, struct fw_packet *packet);
+        void (*send_response)(struct fw_card *card, struct fw_packet *packet);
+        /* Calling cancel is valid once a packet has been submitted. */
+        int (*cancel_packet)(struct fw_card *card, struct fw_packet *packet);
+
+        /*
+         * Allow the specified node ID to do direct DMA out and in of
+         * host memory.  The card will disable this for all node when
+         * a bus reset happens, so driver need to reenable this after
+         * bus reset.  Returns 0 on success, -ENODEV if the card
+         * doesn't support this, -ESTALE if the generation doesn't
+         * match.
+         */
+        int (*enable_phys_dma)(struct fw_card *card,
+                               int node_id, int generation);
+
+        u64 (*get_bus_time)(struct fw_card *card);
+
+        struct fw_iso_context *
+        (*allocate_iso_context)(struct fw_card *card,
+                                int type, int channel, size_t header_size);
+        void (*free_iso_context)(struct fw_iso_context *ctx);
+
+        int (*start_iso)(struct fw_iso_context *ctx,
+                         s32 cycle, u32 sync, u32 tags);
+
+        int (*queue_iso)(struct fw_iso_context *ctx,
+                         struct fw_iso_packet *packet,
+                         struct fw_iso_buffer *buffer,
+                         unsigned long payload);
+
+        int (*stop_iso)(struct fw_iso_context *ctx);
+};
+
+void fw_card_initialize(struct fw_card *card,
+                const struct fw_card_driver *driver, struct device *device);
+int fw_card_add(struct fw_card *card,
+                u32 max_receive, u32 link_speed, u64 guid);
+void fw_core_remove_card(struct fw_card *card);
+int fw_core_initiate_bus_reset(struct fw_card *card, int short_reset);
+int fw_compute_block_crc(u32 *block);
+void fw_schedule_bm_work(struct fw_card *card, unsigned long delay);
+
+struct fw_descriptor {
+        struct list_head link;
+        size_t length;
+        u32 immediate;
+        u32 key;
+        const u32 *data;
+};
+
+int fw_core_add_descriptor(struct fw_descriptor *desc);
+void fw_core_remove_descriptor(struct fw_descriptor *desc);
+
+
+/* -cdev */
+
+extern const struct file_operations fw_device_ops;
+
+void fw_device_cdev_update(struct fw_device *device);
+void fw_device_cdev_remove(struct fw_device *device);
+
+
+/* -device */
+
+extern struct rw_semaphore fw_device_rwsem;
+extern struct idr fw_device_idr;
+extern int fw_cdev_major;
+
+struct fw_device *fw_device_get_by_devt(dev_t devt);
+int fw_device_set_broadcast_channel(struct device *dev, void *gen);
+void fw_node_event(struct fw_card *card, struct fw_node *node, int event);
+
+
+/* -iso */
+
+/*
+ * The iso packet format allows for an immediate header/payload part
+ * stored in 'header' immediately after the packet info plus an
+ * indirect payload part that is pointer to by the 'payload' field.
+ * Applications can use one or the other or both to implement simple
+ * low-bandwidth streaming (e.g. audio) or more advanced
+ * scatter-gather streaming (e.g. assembling video frame automatically).
+ */
+struct fw_iso_packet {
+        u16 payload_length;     /* Length of indirect payload. */
+        u32 interrupt:1;        /* Generate interrupt on this packet */
+        u32 skip:1;             /* Set to not send packet at all. */
+        u32 tag:2;
+        u32 sy:4;
+        u32 header_length:8;    /* Length of immediate header. */
+        u32 header[0];
+};
+
+#define FW_ISO_CONTEXT_TRANSMIT 0
+#define FW_ISO_CONTEXT_RECEIVE  1
+
+#define FW_ISO_CONTEXT_MATCH_TAG0        1
+#define FW_ISO_CONTEXT_MATCH_TAG1        2
+#define FW_ISO_CONTEXT_MATCH_TAG2        4
+#define FW_ISO_CONTEXT_MATCH_TAG3        8
+#define FW_ISO_CONTEXT_MATCH_ALL_TAGS   15
+
+/*
+ * An iso buffer is just a set of pages mapped for DMA in the
+ * specified direction.  Since the pages are to be used for DMA, they
+ * are not mapped into the kernel virtual address space.  We store the
+ * DMA address in the page private. The helper function
+ * fw_iso_buffer_map() will map the pages into a given vma.
+ */
+struct fw_iso_buffer {
+        enum dma_data_direction direction;
+        struct page **pages;
+        int page_count;
+};
+
+typedef void (*fw_iso_callback_t)(struct fw_iso_context *context,
+                                  u32 cycle, size_t header_length,
+                                  void *header, void *data);
+
+struct fw_iso_context {
+        struct fw_card *card;
+        int type;
+        int channel;
+        int speed;
+        size_t header_size;
+        fw_iso_callback_t callback;
+        void *callback_data;
+};
+
+int fw_iso_buffer_init(struct fw_iso_buffer *buffer, struct fw_card *card,
+                       int page_count, enum dma_data_direction direction);
+int fw_iso_buffer_map(struct fw_iso_buffer *buffer, struct vm_area_struct *vma);
+void fw_iso_buffer_destroy(struct fw_iso_buffer *buffer, struct fw_card *card);
+
+struct fw_iso_context *fw_iso_context_create(struct fw_card *card,
+                int type, int channel, int speed, size_t header_size,
+                fw_iso_callback_t callback, void *callback_data);
+int fw_iso_context_queue(struct fw_iso_context *ctx,
+                         struct fw_iso_packet *packet,
+                         struct fw_iso_buffer *buffer,
+                         unsigned long payload);
+int fw_iso_context_start(struct fw_iso_context *ctx,
+                         int cycle, int sync, int tags);
+int fw_iso_context_stop(struct fw_iso_context *ctx);
+void fw_iso_context_destroy(struct fw_iso_context *ctx);
+
+void fw_iso_resource_manage(struct fw_card *card, int generation,
+                u64 channels_mask, int *channel, int *bandwidth, bool allocate);
+
+
+/* -topology */
+
+enum {
+        FW_NODE_CREATED,
+        FW_NODE_UPDATED,
+        FW_NODE_DESTROYED,
+        FW_NODE_LINK_ON,
+        FW_NODE_LINK_OFF,
+        FW_NODE_INITIATED_RESET,
+};
+
+struct fw_node {
+        u16 node_id;
+        u8 color;
+        u8 port_count;
+        u8 link_on:1;
+        u8 initiated_reset:1;
+        u8 b_path:1;
+        u8 phy_speed:2; /* As in the self ID packet. */
+        u8 max_speed:2; /* Minimum of all phy-speeds on the path from the
+                         * local node to this node. */
+        u8 max_depth:4; /* Maximum depth to any leaf node */
+        u8 max_hops:4;  /* Max hops in this sub tree */
+        atomic_t ref_count;
+
+        /* For serializing node topology into a list. */
+        struct list_head link;
+
+        /* Upper layer specific data. */
+        void *data;
+
+        struct fw_node *ports[0];
+};
+
+static inline struct fw_node *fw_node_get(struct fw_node *node)
+{
+        atomic_inc(&node->ref_count);
+
+        return node;
+}
+
+static inline void fw_node_put(struct fw_node *node)
+{
+        if (atomic_dec_and_test(&node->ref_count))
+                kfree(node);
+}
+
+void fw_core_handle_bus_reset(struct fw_card *card, int node_id,
+                              int generation, int self_id_count, u32 *self_ids);
+void fw_destroy_nodes(struct fw_card *card);
+
+/*
+ * Check whether new_generation is the immediate successor of old_generation.
+ * Take counter roll-over at 255 (as per OHCI) into account.
+ */
+static inline bool is_next_generation(int new_generation, int old_generation)
+{
+        return (new_generation & 0xff) == ((old_generation + 1) & 0xff);
+}
+
+
+/* -transaction */
+
+#define TCODE_IS_READ_REQUEST(tcode)    (((tcode) & ~1) == 4)
+#define TCODE_IS_BLOCK_PACKET(tcode)    (((tcode) &  1) != 0)
+#define TCODE_IS_REQUEST(tcode)         (((tcode) &  2) == 0)
+#define TCODE_IS_RESPONSE(tcode)        (((tcode) &  2) != 0)
+#define TCODE_HAS_REQUEST_DATA(tcode)   (((tcode) & 12) != 4)
+#define TCODE_HAS_RESPONSE_DATA(tcode)  (((tcode) & 12) != 0)
+
+#define LOCAL_BUS 0xffc0
+
+void fw_core_handle_request(struct fw_card *card, struct fw_packet *request);
+void fw_core_handle_response(struct fw_card *card, struct fw_packet *packet);
+void fw_fill_response(struct fw_packet *response, u32 *request_header,
+                      int rcode, void *payload, size_t length);
+void fw_flush_transactions(struct fw_card *card);
+void fw_send_phy_config(struct fw_card *card,
+                        int node_id, int generation, int gap_count);
+
+static inline int fw_stream_packet_destination_id(int tag, int channel, int sy)
+{
+        return tag << 14 | channel << 8 | sy;
+}
+
+#endif /* _FIREWIRE_CORE_H */
diff --git a/drivers/firewire/fw-device.h b/drivers/firewire/fw-device.h
deleted file mode 100644
index 97588937c018..000000000000
--- a/drivers/firewire/fw-device.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright (C) 2005-2006  Kristian Hoegsberg <krh@bitplanet.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef __fw_device_h
-#define __fw_device_h
-
-#include <linux/device.h>
-#include <linux/fs.h>
-#include <linux/idr.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/mutex.h>
-#include <linux/rwsem.h>
-#include <linux/sysfs.h>
-#include <linux/types.h>
-#include <linux/workqueue.h>
-
-#include <asm/atomic.h>
-
-enum fw_device_state {
-        FW_DEVICE_INITIALIZING,
-        FW_DEVICE_RUNNING,
-        FW_DEVICE_GONE,
-        FW_DEVICE_SHUTDOWN,
-};
-
-struct fw_attribute_group {
-        struct attribute_group *groups[2];
-        struct attribute_group group;
-        struct attribute *attrs[11];
-};
-
-struct fw_node;
-struct fw_card;
-
-/*
- * Note, fw_device.generation always has to be read before fw_device.node_id.
- * Use SMP memory barriers to ensure this.  Otherwise requests will be sent
- * to an outdated node_id if the generation was updated in the meantime due
- * to a bus reset.
- *
- * Likewise, fw-core will take care to update .node_id before .generation so
- * that whenever fw_device.generation is current WRT the actual bus generation,
- * fw_device.node_id is guaranteed to be current too.
- *
- * The same applies to fw_device.card->node_id vs. fw_device.generation.
- *
- * fw_device.config_rom and fw_device.config_rom_length may be accessed during
- * the lifetime of any fw_unit belonging to the fw_device, before device_del()
- * was called on the last fw_unit.  Alternatively, they may be accessed while
- * holding fw_device_rwsem.
- */
-struct fw_device {
-        atomic_t state;
-        struct fw_node *node;
-        int node_id;
-        int generation;
-        unsigned max_speed;
-        struct fw_card *card;
-        struct device device;
-
-        struct mutex client_list_mutex;
-        struct list_head client_list;
-
-        u32 *config_rom;
-        size_t config_rom_length;
-        int config_rom_retries;
-        unsigned cmc:1;
-        unsigned bc_implemented:2;
-
-        struct delayed_work work;
-        struct fw_attribute_group attribute_group;
-};
-
-static inline struct fw_device *fw_device(struct device *dev)
-{
-        return container_of(dev, struct fw_device, device);
-}
-
-static inline int fw_device_is_shutdown(struct fw_device *device)
-{
-        return atomic_read(&device->state) == FW_DEVICE_SHUTDOWN;
-}
-
-static inline struct fw_device *fw_device_get(struct fw_device *device)
-{
-        get_device(&device->device);
-
-        return device;
-}
-
-static inline void fw_device_put(struct fw_device *device)
-{
-        put_device(&device->device);
-}
-
-struct fw_device *fw_device_get_by_devt(dev_t devt);
-int fw_device_enable_phys_dma(struct fw_device *device);
-void fw_device_set_broadcast_channel(struct fw_device *device, int generation);
-
-void fw_device_cdev_update(struct fw_device *device);
-void fw_device_cdev_remove(struct fw_device *device);
-
-extern struct rw_semaphore fw_device_rwsem;
-extern struct idr fw_device_idr;
-extern int fw_cdev_major;
-
-/*
- * fw_unit.directory must not be accessed after device_del(&fw_unit.device).
- */
-struct fw_unit {
-        struct device device;
-        u32 *directory;
-        struct fw_attribute_group attribute_group;
-};
-
-static inline struct fw_unit *fw_unit(struct device *dev)
-{
-        return container_of(dev, struct fw_unit, device);
-}
-
-static inline struct fw_unit *fw_unit_get(struct fw_unit *unit)
-{
-        get_device(&unit->device);
-
-        return unit;
-}
-
-static inline void fw_unit_put(struct fw_unit *unit)
-{
-        put_device(&unit->device);
-}
-
-#define CSR_OFFSET      0x40
-#define CSR_LEAF        0x80
-#define CSR_DIRECTORY   0xc0
-
-#define CSR_DESCRIPTOR          0x01
-#define CSR_VENDOR              0x03
-#define CSR_HARDWARE_VERSION    0x04
-#define CSR_NODE_CAPABILITIES   0x0c
-#define CSR_UNIT                0x11
-#define CSR_SPECIFIER_ID        0x12
-#define CSR_VERSION             0x13
-#define CSR_DEPENDENT_INFO      0x14
-#define CSR_MODEL               0x17
-#define CSR_INSTANCE            0x18
-#define CSR_DIRECTORY_ID        0x20
-
-struct fw_csr_iterator {
-        u32 *p;
-        u32 *end;
-};
-
-void fw_csr_iterator_init(struct fw_csr_iterator *ci, u32 *p);
-int fw_csr_iterator_next(struct fw_csr_iterator *ci,
-                         int *key, int *value);
-
-#define FW_MATCH_VENDOR         0x0001
-#define FW_MATCH_MODEL          0x0002
-#define FW_MATCH_SPECIFIER_ID   0x0004
-#define FW_MATCH_VERSION        0x0008
-
-struct fw_device_id {
-        u32 match_flags;
-        u32 vendor;
-        u32 model;
-        u32 specifier_id;
-        u32 version;
-        void *driver_data;
-};
-
-struct fw_driver {
-        struct device_driver driver;
-        /* Called when the parent device sits through a bus reset. */
-        void (*update) (struct fw_unit *unit);
-        const struct fw_device_id *id_table;
-};
-
-static inline struct fw_driver *fw_driver(struct device_driver *drv)
-{
-        return container_of(drv, struct fw_driver, driver);
-}
-
-extern const struct file_operations fw_device_ops;
-
-#endif /* __fw_device_h */
diff --git a/drivers/firewire/fw-topology.h b/drivers/firewire/fw-topology.h
deleted file mode 100644
index 3c497bb4fae4..000000000000
--- a/drivers/firewire/fw-topology.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef __fw_topology_h
-#define __fw_topology_h
-
-#include <linux/list.h>
-#include <linux/slab.h>
-
-#include <asm/atomic.h>
-
-enum {
-        FW_NODE_CREATED,
-        FW_NODE_UPDATED,
-        FW_NODE_DESTROYED,
-        FW_NODE_LINK_ON,
-        FW_NODE_LINK_OFF,
-        FW_NODE_INITIATED_RESET,
-};
-
-struct fw_node {
-        u16 node_id;
-        u8 color;
-        u8 port_count;
-        u8 link_on : 1;
-        u8 initiated_reset : 1;
-        u8 b_path : 1;
-        u8 phy_speed : 2; /* As in the self ID packet. */
-        u8 max_speed : 2; /* Minimum of all phy-speeds on the path from the
-                           * local node to this node. */
-        u8 max_depth : 4; /* Maximum depth to any leaf node */
-        u8 max_hops : 4;  /* Max hops in this sub tree */
-        atomic_t ref_count;
-
-        /* For serializing node topology into a list. */
-        struct list_head link;
-
-        /* Upper layer specific data. */
-        void *data;
-
-        struct fw_node *ports[0];
-};
-
-static inline struct fw_node *fw_node_get(struct fw_node *node)
-{
-        atomic_inc(&node->ref_count);
-
-        return node;
-}
-
-static inline void fw_node_put(struct fw_node *node)
-{
-        if (atomic_dec_and_test(&node->ref_count))
-                kfree(node);
-}
-
-struct fw_card;
-void fw_destroy_nodes(struct fw_card *card);
-
-int fw_compute_block_crc(u32 *block);
-
-#endif /* __fw_topology_h */
diff --git a/drivers/firewire/fw-transaction.h b/drivers/firewire/fw-transaction.h
deleted file mode 100644
index dfa799068f89..000000000000
--- a/drivers/firewire/fw-transaction.h
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef __fw_transaction_h
-#define __fw_transaction_h
-
-#include <linux/completion.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/firewire-constants.h>
-#include <linux/kref.h>
-#include <linux/list.h>
-#include <linux/spinlock_types.h>
-#include <linux/timer.h>
-#include <linux/types.h>
-#include <linux/workqueue.h>
-
-#define TCODE_IS_READ_REQUEST(tcode)    (((tcode) & ~1) == 4)
-#define TCODE_IS_BLOCK_PACKET(tcode)    (((tcode) &  1) != 0)
-#define TCODE_IS_REQUEST(tcode)         (((tcode) &  2) == 0)
-#define TCODE_IS_RESPONSE(tcode)        (((tcode) &  2) != 0)
-#define TCODE_HAS_REQUEST_DATA(tcode)   (((tcode) & 12) != 4)
-#define TCODE_HAS_RESPONSE_DATA(tcode)  (((tcode) & 12) != 0)
-
-#define LOCAL_BUS 0xffc0
-
-#define SELFID_PORT_CHILD       0x3
-#define SELFID_PORT_PARENT      0x2
-#define SELFID_PORT_NCONN       0x1
-#define SELFID_PORT_NONE        0x0
-
-#define PHY_PACKET_CONFIG       0x0
-#define PHY_PACKET_LINK_ON      0x1
-#define PHY_PACKET_SELF_ID      0x2
-
-/* Bit fields _within_ the PHY registers. */
-#define PHY_LINK_ACTIVE         0x80
-#define PHY_CONTENDER           0x40
-#define PHY_BUS_RESET           0x40
-#define PHY_BUS_SHORT_RESET     0x40
-
-#define CSR_REGISTER_BASE               0xfffff0000000ULL
-
-/* register offsets relative to CSR_REGISTER_BASE */
-#define CSR_STATE_CLEAR                 0x0
-#define CSR_STATE_SET                   0x4
-#define CSR_NODE_IDS                    0x8
-#define CSR_RESET_START                 0xc
-#define CSR_SPLIT_TIMEOUT_HI            0x18
-#define CSR_SPLIT_TIMEOUT_LO            0x1c
-#define CSR_CYCLE_TIME                  0x200
-#define CSR_BUS_TIME                    0x204
-#define CSR_BUSY_TIMEOUT                0x210
-#define CSR_BUS_MANAGER_ID              0x21c
-#define CSR_BANDWIDTH_AVAILABLE         0x220
-#define CSR_CHANNELS_AVAILABLE          0x224
-#define CSR_CHANNELS_AVAILABLE_HI       0x224
-#define CSR_CHANNELS_AVAILABLE_LO       0x228
-#define CSR_BROADCAST_CHANNEL           0x234
-#define CSR_CONFIG_ROM                  0x400
-#define CSR_CONFIG_ROM_END              0x800
-#define CSR_FCP_COMMAND                 0xB00
-#define CSR_FCP_RESPONSE                0xD00
-#define CSR_FCP_END                     0xF00
-#define CSR_TOPOLOGY_MAP                0x1000
-#define CSR_TOPOLOGY_MAP_END            0x1400
-#define CSR_SPEED_MAP                   0x2000
-#define CSR_SPEED_MAP_END               0x3000
-
-#define BANDWIDTH_AVAILABLE_INITIAL     4915
-#define BROADCAST_CHANNEL_INITIAL       (1 << 31 | 31)
-#define BROADCAST_CHANNEL_VALID         (1 << 30)
-
-#define fw_notify(s, args...) printk(KERN_NOTICE KBUILD_MODNAME ": " s, ## args)
-#define fw_error(s, args...) printk(KERN_ERR KBUILD_MODNAME ": " s, ## args)
-
-static inline void fw_memcpy_from_be32(void *_dst, void *_src, size_t size)
-{
-        u32    *dst = _dst;
-        __be32 *src = _src;
-        int i;
-
-        for (i = 0; i < size / 4; i++)
-                dst[i] = be32_to_cpu(src[i]);
-}
-
-static inline void fw_memcpy_to_be32(void *_dst, void *_src, size_t size)
-{
-        fw_memcpy_from_be32(_dst, _src, size);
-}
-
-struct fw_card;
-struct fw_packet;
-struct fw_node;
-struct fw_request;
-
-struct fw_descriptor {
-        struct list_head link;
-        size_t length;
-        u32 immediate;
-        u32 key;
-        const u32 *data;
-};
-
-int fw_core_add_descriptor(struct fw_descriptor *desc);
-void fw_core_remove_descriptor(struct fw_descriptor *desc);
-
-typedef void (*fw_packet_callback_t)(struct fw_packet *packet,
-                                     struct fw_card *card, int status);
-
-typedef void (*fw_transaction_callback_t)(struct fw_card *card, int rcode,
-                                          void *data, size_t length,
-                                          void *callback_data);
-
-/*
- * Important note:  The callback must guarantee that either fw_send_response()
- * or kfree() is called on the @request.
- */
-typedef void (*fw_address_callback_t)(struct fw_card *card,
-                                      struct fw_request *request,
-                                      int tcode, int destination, int source,
-                                      int generation, int speed,
-                                      unsigned long long offset,
-                                      void *data, size_t length,
-                                      void *callback_data);
-
-struct fw_packet {
-        int speed;
-        int generation;
-        u32 header[4];
-        size_t header_length;
-        void *payload;
-        size_t payload_length;
-        dma_addr_t payload_bus;
-        u32 timestamp;
-
-        /*
-         * This callback is called when the packet transmission has
-         * completed; for successful transmission, the status code is
-         * the ack received from the destination, otherwise it's a
-         * negative errno: ENOMEM, ESTALE, ETIMEDOUT, ENODEV, EIO.
-         * The callback can be called from tasklet context and thus
-         * must never block.
-         */
-        fw_packet_callback_t callback;
-        int ack;
-        struct list_head link;
-        void *driver_data;
-};
-
-struct fw_transaction {
-        int node_id; /* The generation is implied; it is always the current. */
-        int tlabel;
-        int timestamp;
-        struct list_head link;
-
-        struct fw_packet packet;
-
-        /*
-         * The data passed to the callback is valid only during the
-         * callback.
-         */
-        fw_transaction_callback_t callback;
-        void *callback_data;
-};
-
-struct fw_address_handler {
-        u64 offset;
-        size_t length;
-        fw_address_callback_t address_callback;
-        void *callback_data;
-        struct list_head link;
-};
-
-struct fw_address_region {
-        u64 start;
-        u64 end;
-};
-
-extern const struct fw_address_region fw_high_memory_region;
-
-int fw_core_add_address_handler(struct fw_address_handler *handler,
-                                const struct fw_address_region *region);
-void fw_core_remove_address_handler(struct fw_address_handler *handler);
-void fw_fill_response(struct fw_packet *response, u32 *request_header,
-                      int rcode, void *payload, size_t length);
-void fw_send_response(struct fw_card *card,
-                      struct fw_request *request, int rcode);
-
-extern struct bus_type fw_bus_type;
-
-struct fw_card {
-        const struct fw_card_driver *driver;
-        struct device *device;
-        struct kref kref;
-        struct completion done;
-
-        int node_id;
-        int generation;
-        int current_tlabel, tlabel_mask;
-        struct list_head transaction_list;
-        struct timer_list flush_timer;
-        unsigned long reset_jiffies;
-
-        unsigned long long guid;
-        unsigned max_receive;
-        int link_speed;
-        int config_rom_generation;
-
-        spinlock_t lock; /* Take this lock when handling the lists in
-                          * this struct. */
-        struct fw_node *local_node;
-        struct fw_node *root_node;
-        struct fw_node *irm_node;
-        u8 color; /* must be u8 to match the definition in struct fw_node */
-        int gap_count;
-        bool beta_repeaters_present;
-
-        int index;
-
-        struct list_head link;
-
-        /* Work struct for BM duties. */
-        struct delayed_work work;
-        int bm_retries;
-        int bm_generation;
-
-        bool broadcast_channel_allocated;
-        u32 broadcast_channel;
-        u32 topology_map[(CSR_TOPOLOGY_MAP_END - CSR_TOPOLOGY_MAP) / 4];
-};
-
-static inline struct fw_card *fw_card_get(struct fw_card *card)
-{
-        kref_get(&card->kref);
-
-        return card;
-}
-
-void fw_card_release(struct kref *kref);
-
-static inline void fw_card_put(struct fw_card *card)
-{
-        kref_put(&card->kref, fw_card_release);
-}
-
-extern void fw_schedule_bm_work(struct fw_card *card, unsigned long delay);
-
-/*
- * Check whether new_generation is the immediate successor of old_generation.
- * Take counter roll-over at 255 (as per to OHCI) into account.
- */
-static inline bool is_next_generation(int new_generation, int old_generation)
-{
-        return (new_generation & 0xff) == ((old_generation + 1) & 0xff);
-}
-
-/*
- * The iso packet format allows for an immediate header/payload part
- * stored in 'header' immediately after the packet info plus an
- * indirect payload part that is pointer to by the 'payload' field.
- * Applications can use one or the other or both to implement simple
- * low-bandwidth streaming (e.g. audio) or more advanced
- * scatter-gather streaming (e.g. assembling video frame automatically).
- */
-
-struct fw_iso_packet {
-        u16 payload_length;     /* Length of indirect payload. */
-        u32 interrupt : 1;      /* Generate interrupt on this packet */
-        u32 skip : 1;           /* Set to not send packet at all. */
-        u32 tag : 2;
-        u32 sy : 4;
-        u32 header_length : 8;  /* Length of immediate header. */
-        u32 header[0];
-};
-
-#define FW_ISO_CONTEXT_TRANSMIT 0
-#define FW_ISO_CONTEXT_RECEIVE  1
-
-#define FW_ISO_CONTEXT_MATCH_TAG0        1
-#define FW_ISO_CONTEXT_MATCH_TAG1        2
-#define FW_ISO_CONTEXT_MATCH_TAG2        4
-#define FW_ISO_CONTEXT_MATCH_TAG3        8
-#define FW_ISO_CONTEXT_MATCH_ALL_TAGS   15
-
-struct fw_iso_context;
-
-typedef void (*fw_iso_callback_t)(struct fw_iso_context *context,
-                                  u32 cycle, size_t header_length,
-                                  void *header, void *data);
-
-/*
- * An iso buffer is just a set of pages mapped for DMA in the
- * specified direction.  Since the pages are to be used for DMA, they
- * are not mapped into the kernel virtual address space.  We store the
- * DMA address in the page private. The helper function
- * fw_iso_buffer_map() will map the pages into a given vma.
- */
-
-struct fw_iso_buffer {
-        enum dma_data_direction direction;
-        struct page **pages;
-        int page_count;
-};
-
-struct fw_iso_context {
-        struct fw_card *card;
-        int type;
-        int channel;
-        int speed;
-        size_t header_size;
-        fw_iso_callback_t callback;
-        void *callback_data;
-};
-
-int fw_iso_buffer_init(struct fw_iso_buffer *buffer, struct fw_card *card,
-                       int page_count, enum dma_data_direction direction);
-int fw_iso_buffer_map(struct fw_iso_buffer *buffer, struct vm_area_struct *vma);
-void fw_iso_buffer_destroy(struct fw_iso_buffer *buffer, struct fw_card *card);
-
-struct fw_iso_context *fw_iso_context_create(struct fw_card *card,
-                int type, int channel, int speed, size_t header_size,
-                fw_iso_callback_t callback, void *callback_data);
-int fw_iso_context_queue(struct fw_iso_context *ctx,
-                         struct fw_iso_packet *packet,
-                         struct fw_iso_buffer *buffer,
-                         unsigned long payload);
-int fw_iso_context_start(struct fw_iso_context *ctx,
-                         int cycle, int sync, int tags);
-int fw_iso_context_stop(struct fw_iso_context *ctx);
-void fw_iso_context_destroy(struct fw_iso_context *ctx);
-
-void fw_iso_resource_manage(struct fw_card *card, int generation,
-                u64 channels_mask, int *channel, int *bandwidth, bool allocate);
-
-struct fw_card_driver {
-        /*
-         * Enable the given card with the given initial config rom.
-         * This function is expected to activate the card, and either
-         * enable the PHY or set the link_on bit and initiate a bus
-         * reset.
-         */
-        int (*enable)(struct fw_card *card, u32 *config_rom, size_t length);
-
-        int (*update_phy_reg)(struct fw_card *card, int address,
-                              int clear_bits, int set_bits);
-
-        /*
-         * Update the config rom for an enabled card.  This function
-         * should change the config rom that is presented on the bus
-         * an initiate a bus reset.
-         */
-        int (*set_config_rom)(struct fw_card *card,
-                              u32 *config_rom, size_t length);
-
-        void (*send_request)(struct fw_card *card, struct fw_packet *packet);
-        void (*send_response)(struct fw_card *card, struct fw_packet *packet);
-        /* Calling cancel is valid once a packet has been submitted. */
-        int (*cancel_packet)(struct fw_card *card, struct fw_packet *packet);
-
-        /*
-         * Allow the specified node ID to do direct DMA out and in of
-         * host memory.  The card will disable this for all node when
-         * a bus reset happens, so driver need to reenable this after
-         * bus reset.  Returns 0 on success, -ENODEV if the card
-         * doesn't support this, -ESTALE if the generation doesn't
-         * match.
-         */
-        int (*enable_phys_dma)(struct fw_card *card,
-                               int node_id, int generation);
-
-        u64 (*get_bus_time)(struct fw_card *card);
-
-        struct fw_iso_context *
-        (*allocate_iso_context)(struct fw_card *card,
-                                int type, int channel, size_t header_size);
-        void (*free_iso_context)(struct fw_iso_context *ctx);
-
-        int (*start_iso)(struct fw_iso_context *ctx,
-                         s32 cycle, u32 sync, u32 tags);
-
-        int (*queue_iso)(struct fw_iso_context *ctx,
-                         struct fw_iso_packet *packet,
-                         struct fw_iso_buffer *buffer,
-                         unsigned long payload);
-
-        int (*stop_iso)(struct fw_iso_context *ctx);
-};
-
-int fw_core_initiate_bus_reset(struct fw_card *card, int short_reset);
-
-void fw_send_request(struct fw_card *card, struct fw_transaction *t,
-                int tcode, int destination_id, int generation, int speed,
-                unsigned long long offset, void *payload, size_t length,
-                fw_transaction_callback_t callback, void *callback_data);
-int fw_cancel_transaction(struct fw_card *card,
-                          struct fw_transaction *transaction);
-void fw_flush_transactions(struct fw_card *card);
-int fw_run_transaction(struct fw_card *card, int tcode, int destination_id,
-                       int generation, int speed, unsigned long long offset,
-                       void *payload, size_t length);
-void fw_send_phy_config(struct fw_card *card,
-                        int node_id, int generation, int gap_count);
-
-static inline int fw_stream_packet_destination_id(int tag, int channel, int sy)
-{
-        return tag << 14 | channel << 8 | sy;
-}
-
-/*
- * Called by the topology code to inform the device code of node
- * activity; found, lost, or updated nodes.
- */
-void fw_node_event(struct fw_card *card, struct fw_node *node, int event);
-
-/* API used by card level drivers */
-
-void fw_card_initialize(struct fw_card *card,
-                const struct fw_card_driver *driver, struct device *device);
-int fw_card_add(struct fw_card *card,
-                u32 max_receive, u32 link_speed, u64 guid);
-void fw_core_remove_card(struct fw_card *card);
-void fw_core_handle_bus_reset(struct fw_card *card, int node_id,
-                int generation, int self_id_count, u32 *self_ids);
-void fw_core_handle_request(struct fw_card *card, struct fw_packet *request);
-void fw_core_handle_response(struct fw_card *card, struct fw_packet *packet);
-
-extern int fw_irm_set_broadcast_channel_register(struct device *dev,
-                                                 void *data);
-
-#endif /* __fw_transaction_h */
diff --git a/drivers/firewire/fw-ohci.c b/drivers/firewire/ohci.c
index 1180d0be0bb4..ecddd11b797a 100644
--- a/drivers/firewire/fw-ohci.c
+++ b/drivers/firewire/ohci.c
@@ -20,17 +20,25 @@
 
 #include <linux/compiler.h>
 #include <linux/delay.h>
+#include <linux/device.h>
 #include <linux/dma-mapping.h>
+#include <linux/firewire.h>
+#include <linux/firewire-constants.h>
 #include <linux/gfp.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/list.h>
 #include <linux/mm.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/pci.h>
 #include <linux/spinlock.h>
+#include <linux/string.h>
 
+#include <asm/atomic.h>
+#include <asm/byteorder.h>
 #include <asm/page.h>
 #include <asm/system.h>
 
@@ -38,8 +46,8 @@
 #include <asm/pmac_feature.h>
 #endif
 
-#include "fw-ohci.h"
-#include "fw-transaction.h"
+#include "core.h"
+#include "ohci.h"
 
 #define DESCRIPTOR_OUTPUT_MORE          0
 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
@@ -178,7 +186,7 @@ struct fw_ohci {
         int node_id;
         int generation;
         int request_generation; /* for timestamping incoming requests */
-        u32 bus_seconds;
+        atomic_t bus_seconds;
 
         bool use_dualbuffer;
         bool old_uninorth;
@@ -231,7 +239,6 @@ static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 
-#define FW_OHCI_MAJOR                   240
 #define OHCI1394_REGISTER_SIZE          0x800
 #define OHCI_LOOP_COUNT                 500
 #define OHCI1394_PCI_HCI_Control        0x40
@@ -1434,7 +1441,7 @@ static irqreturn_t irq_handler(int irq, void *data)
         if (event & OHCI1394_cycle64Seconds) {
                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
                 if ((cycle_time & 0x80000000) == 0)
-                        ohci->bus_seconds++;
+                        atomic_inc(&ohci->bus_seconds);
         }
 
         return IRQ_HANDLED;
@@ -1770,7 +1777,7 @@ static u64 ohci_get_bus_time(struct fw_card *card)
         u64 bus_time;
 
         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
-        bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
+        bus_time = ((u64)atomic_read(&ohci->bus_seconds) << 32) | cycle_time;
 
         return bus_time;
 }
diff --git a/drivers/firewire/fw-ohci.h b/drivers/firewire/ohci.h
index a2fbb6240ca7..ba492d85c516 100644
--- a/drivers/firewire/fw-ohci.h
+++ b/drivers/firewire/ohci.h
@@ -1,5 +1,5 @@
-#ifndef __fw_ohci_h
-#define __fw_ohci_h
+#ifndef _FIREWIRE_OHCI_H
+#define _FIREWIRE_OHCI_H
 
 /* OHCI register map */
 
@@ -154,4 +154,4 @@
 
 #define OHCI1394_phy_tcode              0xe
 
-#endif /* __fw_ohci_h */
+#endif /* _FIREWIRE_OHCI_H */
diff --git a/drivers/firewire/fw-sbp2.c b/drivers/firewire/sbp2.c
index 2bcf51557c72..24c45635376a 100644
--- a/drivers/firewire/fw-sbp2.c
+++ b/drivers/firewire/sbp2.c
@@ -30,18 +30,28 @@
 
 #include <linux/blkdev.h>
 #include <linux/bug.h>
+#include <linux/completion.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
+#include <linux/firewire.h>
+#include <linux/firewire-constants.h>
+#include <linux/init.h>
+#include <linux/jiffies.h>
 #include <linux/kernel.h>
+#include <linux/kref.h>
+#include <linux/list.h>
 #include <linux/mod_devicetable.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
 #include <linux/scatterlist.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
 #include <linux/string.h>
 #include <linux/stringify.h>
-#include <linux/timer.h>
 #include <linux/workqueue.h>
+
+#include <asm/byteorder.h>
 #include <asm/system.h>
 
 #include <scsi/scsi.h>
@@ -49,10 +59,6 @@
 #include <scsi/scsi_device.h>
 #include <scsi/scsi_host.h>
 
-#include "fw-device.h"
-#include "fw-topology.h"
-#include "fw-transaction.h"
-
 /*
  * So far only bridges from Oxford Semiconductor are known to support
  * concurrent logins. Depending on firmware, four or two concurrent logins
@@ -174,6 +180,11 @@ struct sbp2_target {
         int blocked;    /* ditto */
 };
 
+static struct fw_device *target_device(struct sbp2_target *tgt)
+{
+        return fw_parent_device(tgt->unit);
+}
+
 /* Impossible login_id, to detect logout attempt before successful login */
 #define INVALID_LOGIN_ID 0x10000
 
@@ -482,7 +493,7 @@ static void complete_transaction(struct fw_card *card, int rcode,
 static void sbp2_send_orb(struct sbp2_orb *orb, struct sbp2_logical_unit *lu,
                           int node_id, int generation, u64 offset)
 {
-        struct fw_device *device = fw_device(lu->tgt->unit->device.parent);
+        struct fw_device *device = target_device(lu->tgt);
         unsigned long flags;
 
         orb->pointer.high = 0;
@@ -504,7 +515,7 @@ static void sbp2_send_orb(struct sbp2_orb *orb, struct sbp2_logical_unit *lu,
 
 static int sbp2_cancel_orbs(struct sbp2_logical_unit *lu)
 {
-        struct fw_device *device = fw_device(lu->tgt->unit->device.parent);
+        struct fw_device *device = target_device(lu->tgt);
         struct sbp2_orb *orb, *next;
         struct list_head list;
         unsigned long flags;
@@ -542,7 +553,7 @@ static int sbp2_send_management_orb(struct sbp2_logical_unit *lu, int node_id,
                                     int generation, int function,
                                     int lun_or_login_id, void *response)
 {
-        struct fw_device *device = fw_device(lu->tgt->unit->device.parent);
+        struct fw_device *device = target_device(lu->tgt);
         struct sbp2_management_orb *orb;
         unsigned int timeout;
         int retval = -ENOMEM;
@@ -638,7 +649,7 @@ static int sbp2_send_management_orb(struct sbp2_logical_unit *lu, int node_id,
 
 static void sbp2_agent_reset(struct sbp2_logical_unit *lu)
 {
-        struct fw_device *device = fw_device(lu->tgt->unit->device.parent);
+        struct fw_device *device = target_device(lu->tgt);
         __be32 d = 0;
 
         fw_run_transaction(device->card, TCODE_WRITE_QUADLET_REQUEST,
@@ -655,7 +666,7 @@ static void complete_agent_reset_write_no_wait(struct fw_card *card,
 
 static void sbp2_agent_reset_no_wait(struct sbp2_logical_unit *lu)
 {
-        struct fw_device *device = fw_device(lu->tgt->unit->device.parent);
+        struct fw_device *device = target_device(lu->tgt);
         struct fw_transaction *t;
         static __be32 d;
 
@@ -694,7 +705,7 @@ static inline void sbp2_allow_block(struct sbp2_logical_unit *lu)
 static void sbp2_conditionally_block(struct sbp2_logical_unit *lu)
 {
         struct sbp2_target *tgt = lu->tgt;
-        struct fw_card *card = fw_device(tgt->unit->device.parent)->card;
+        struct fw_card *card = target_device(tgt)->card;
         struct Scsi_Host *shost =
                 container_of((void *)tgt, struct Scsi_Host, hostdata[0]);
         unsigned long flags;
@@ -718,7 +729,7 @@ static void sbp2_conditionally_block(struct sbp2_logical_unit *lu)
 static void sbp2_conditionally_unblock(struct sbp2_logical_unit *lu)
 {
         struct sbp2_target *tgt = lu->tgt;
-        struct fw_card *card = fw_device(tgt->unit->device.parent)->card;
+        struct fw_card *card = target_device(tgt)->card;
         struct Scsi_Host *shost =
                 container_of((void *)tgt, struct Scsi_Host, hostdata[0]);
         unsigned long flags;
@@ -743,7 +754,7 @@ static void sbp2_conditionally_unblock(struct sbp2_logical_unit *lu)
  */
 static void sbp2_unblock(struct sbp2_target *tgt)
 {
-        struct fw_card *card = fw_device(tgt->unit->device.parent)->card;
+        struct fw_card *card = target_device(tgt)->card;
         struct Scsi_Host *shost =
                 container_of((void *)tgt, struct Scsi_Host, hostdata[0]);
         unsigned long flags;
@@ -773,7 +784,7 @@ static void sbp2_release_target(struct kref *kref)
         struct Scsi_Host *shost =
                 container_of((void *)tgt, struct Scsi_Host, hostdata[0]);
         struct scsi_device *sdev;
-        struct fw_device *device = fw_device(tgt->unit->device.parent);
+        struct fw_device *device = target_device(tgt);
 
         /* prevent deadlocks */
         sbp2_unblock(tgt);
@@ -846,7 +857,7 @@ static void sbp2_queue_work(struct sbp2_logical_unit *lu, unsigned long delay)
  */
 static void sbp2_set_busy_timeout(struct sbp2_logical_unit *lu)
 {
-        struct fw_device *device = fw_device(lu->tgt->unit->device.parent);
+        struct fw_device *device = target_device(lu->tgt);
         __be32 d = cpu_to_be32(SBP2_CYCLE_LIMIT | SBP2_RETRY_LIMIT);
 
         fw_run_transaction(device->card, TCODE_WRITE_QUADLET_REQUEST,
@@ -862,7 +873,7 @@ static void sbp2_login(struct work_struct *work)
         struct sbp2_logical_unit *lu =
                 container_of(work, struct sbp2_logical_unit, work.work);
         struct sbp2_target *tgt = lu->tgt;
-        struct fw_device *device = fw_device(tgt->unit->device.parent);
+        struct fw_device *device = target_device(tgt);
         struct Scsi_Host *shost;
         struct scsi_device *sdev;
         struct sbp2_login_response response;
@@ -1110,7 +1121,7 @@ static struct scsi_host_template scsi_driver_template;
 static int sbp2_probe(struct device *dev)
 {
         struct fw_unit *unit = fw_unit(dev);
-        struct fw_device *device = fw_device(unit->device.parent);
+        struct fw_device *device = fw_parent_device(unit);
         struct sbp2_target *tgt;
         struct sbp2_logical_unit *lu;
         struct Scsi_Host *shost;
@@ -1125,7 +1136,7 @@ static int sbp2_probe(struct device *dev)
                 return -ENOMEM;
 
         tgt = (struct sbp2_target *)shost->hostdata;
-        unit->device.driver_data = tgt;
+        dev_set_drvdata(&unit->device, tgt);
         tgt->unit = unit;
         kref_init(&tgt->kref);
         INIT_LIST_HEAD(&tgt->lu_list);
@@ -1180,7 +1191,7 @@ static int sbp2_probe(struct device *dev)
 static int sbp2_remove(struct device *dev)
 {
         struct fw_unit *unit = fw_unit(dev);
-        struct sbp2_target *tgt = unit->device.driver_data;
+        struct sbp2_target *tgt = dev_get_drvdata(&unit->device);
 
         sbp2_target_put(tgt);
         return 0;
@@ -1191,7 +1202,7 @@ static void sbp2_reconnect(struct work_struct *work)
         struct sbp2_logical_unit *lu =
                 container_of(work, struct sbp2_logical_unit, work.work);
         struct sbp2_target *tgt = lu->tgt;
-        struct fw_device *device = fw_device(tgt->unit->device.parent);
+        struct fw_device *device = target_device(tgt);
         int generation, node_id, local_node_id;
 
         if (fw_device_is_shutdown(device))
@@ -1240,10 +1251,10 @@ static void sbp2_reconnect(struct work_struct *work)
 
 static void sbp2_update(struct fw_unit *unit)
 {
-        struct sbp2_target *tgt = unit->device.driver_data;
+        struct sbp2_target *tgt = dev_get_drvdata(&unit->device);
         struct sbp2_logical_unit *lu;
 
-        fw_device_enable_phys_dma(fw_device(unit->device.parent));
+        fw_device_enable_phys_dma(fw_parent_device(unit));
 
         /*
          * Fw-core serializes sbp2_update() against sbp2_remove().
@@ -1259,9 +1270,10 @@ static void sbp2_update(struct fw_unit *unit)
 #define SBP2_UNIT_SPEC_ID_ENTRY 0x0000609e
 #define SBP2_SW_VERSION_ENTRY   0x00010483
 
-static const struct fw_device_id sbp2_id_table[] = {
+static const struct ieee1394_device_id sbp2_id_table[] = {
         {
-                .match_flags  = FW_MATCH_SPECIFIER_ID | FW_MATCH_VERSION,
+                .match_flags  = IEEE1394_MATCH_SPECIFIER_ID |
+                                IEEE1394_MATCH_VERSION,
                 .specifier_id = SBP2_UNIT_SPEC_ID_ENTRY,
                 .version      = SBP2_SW_VERSION_ENTRY,
         },
@@ -1335,7 +1347,7 @@ static void complete_command_orb(struct sbp2_orb *base_orb,
 {
         struct sbp2_command_orb *orb =
                 container_of(base_orb, struct sbp2_command_orb, base);
-        struct fw_device *device = fw_device(orb->lu->tgt->unit->device.parent);
+        struct fw_device *device = target_device(orb->lu->tgt);
         int result;
 
         if (status != NULL) {
@@ -1442,7 +1454,7 @@ static int sbp2_map_scatterlist(struct sbp2_command_orb *orb,
 static int sbp2_scsi_queuecommand(struct scsi_cmnd *cmd, scsi_done_fn_t done)
 {
         struct sbp2_logical_unit *lu = cmd->device->hostdata;
-        struct fw_device *device = fw_device(lu->tgt->unit->device.parent);
+        struct fw_device *device = target_device(lu->tgt);
         struct sbp2_command_orb *orb;
         int generation, retval = SCSI_MLQUEUE_HOST_BUSY;
 
diff --git a/drivers/firmware/memmap.c b/drivers/firmware/memmap.c
index 05aa2d406ac6..d5ea8a68d338 100644
--- a/drivers/firmware/memmap.c
+++ b/drivers/firmware/memmap.c
@@ -31,8 +31,12 @@
  * information is necessary as for the resource tree.
  */
 struct firmware_map_entry {
-        resource_size_t         start;  /* start of the memory range */
-        resource_size_t         end;    /* end of the memory range (incl.) */
+        /*
+         * start and end must be u64 rather than resource_size_t, because e820
+         * resources can lie at addresses above 4G.
+         */
+        u64                     start;  /* start of the memory range */
+        u64                     end;    /* end of the memory range (incl.) */
         const char              *type;  /* type of the memory range */
         struct list_head        list;   /* entry for the linked list */
         struct kobject          kobj;   /* kobject for each entry */
@@ -101,7 +105,7 @@ static LIST_HEAD(map_entries);
  * Common implementation of firmware_map_add() and firmware_map_add_early()
  * which expects a pre-allocated struct firmware_map_entry.
  **/
-static int firmware_map_add_entry(resource_size_t start, resource_size_t end,
+static int firmware_map_add_entry(u64 start, u64 end,
                                   const char *type,
                                   struct firmware_map_entry *entry)
 {
@@ -132,8 +136,7 @@ static int firmware_map_add_entry(resource_size_t start, resource_size_t end,
  *
  * Returns 0 on success, or -ENOMEM if no memory could be allocated.
  **/
-int firmware_map_add(resource_size_t start, resource_size_t end,
-                     const char *type)
+int firmware_map_add(u64 start, u64 end, const char *type)
 {
         struct firmware_map_entry *entry;
 
@@ -157,8 +160,7 @@ int firmware_map_add(resource_size_t start, resource_size_t end,
  *
  * Returns 0 on success, or -ENOMEM if no memory could be allocated.
  **/
-int __init firmware_map_add_early(resource_size_t start, resource_size_t end,
-                                  const char *type)
+int __init firmware_map_add_early(u64 start, u64 end, const char *type)
 {
         struct firmware_map_entry *entry;
 
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index f5d46e7199d4..c961fe415aef 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -18,6 +18,14 @@ menuconfig DRM
           details.  You should also select and configure AGP
           (/dev/agpgart) support.
 
+config DRM_TTM
+        tristate
+        depends on DRM
+        help
+          GPU memory management subsystem for devices with multiple
+          GPU memory types. Will be enabled automatically if a device driver
+          uses it.
+
 config DRM_TDFX
         tristate "3dfx Banshee/Voodoo3+"
         depends on DRM && PCI
@@ -36,6 +44,11 @@ config DRM_R128
 config DRM_RADEON
         tristate "ATI Radeon"
         depends on DRM && PCI
+        select FB_CFB_FILLRECT
+        select FB_CFB_COPYAREA
+        select FB_CFB_IMAGEBLIT
+        select FB
+        select FRAMEBUFFER_CONSOLE if !EMBEDDED
         help
           Choose this option if you have an ATI Radeon graphics card.  There
           are both PCI and AGP versions.  You don't need to choose this to
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 4ec5061fa584..4e89ab08b7b8 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -26,4 +26,4 @@ obj-$(CONFIG_DRM_I915)  += i915/
 obj-$(CONFIG_DRM_SIS)   += sis/
 obj-$(CONFIG_DRM_SAVAGE)+= savage/
 obj-$(CONFIG_DRM_VIA)   +=via/
-
+obj-$(CONFIG_DRM_TTM)   += ttm/
diff --git a/drivers/gpu/drm/drm_debugfs.c b/drivers/gpu/drm/drm_debugfs.c
index c77c6c6d9d2c..6ce0e2667a85 100644
--- a/drivers/gpu/drm/drm_debugfs.c
+++ b/drivers/gpu/drm/drm_debugfs.c
@@ -105,7 +105,7 @@ int drm_debugfs_create_files(struct drm_info_list *files, int count,
                 ent = debugfs_create_file(files[i].name, S_IFREG | S_IRUGO,
                                           root, tmp, &drm_debugfs_fops);
                 if (!ent) {
-                        DRM_ERROR("Cannot create /debugfs/dri/%s/%s\n",
+                        DRM_ERROR("Cannot create /sys/kernel/debug/dri/%s/%s\n",
                                   name, files[i].name);
                         drm_free(tmp, sizeof(struct drm_info_node),
                                  _DRM_DRIVER);
@@ -133,9 +133,9 @@ EXPORT_SYMBOL(drm_debugfs_create_files);
  * \param minor device minor number
  * \param root DRI debugfs dir entry.
  *
- * Create the DRI debugfs root entry "/debugfs/dri", the device debugfs root entry
- * "/debugfs/dri/%minor%/", and each entry in debugfs_list as
- * "/debugfs/dri/%minor%/%name%".
+ * Create the DRI debugfs root entry "/sys/kernel/debug/dri", the device debugfs root entry
+ * "/sys/kernel/debug/dri/%minor%/", and each entry in debugfs_list as
+ * "/sys/kernel/debug/dri/%minor%/%name%".
  */
 int drm_debugfs_init(struct drm_minor *minor, int minor_id,
                      struct dentry *root)
@@ -148,7 +148,7 @@ int drm_debugfs_init(struct drm_minor *minor, int minor_id,
         sprintf(name, "%d", minor_id);
         minor->debugfs_root = debugfs_create_dir(name, root);
         if (!minor->debugfs_root) {
-                DRM_ERROR("Cannot create /debugfs/dri/%s\n", name);
+                DRM_ERROR("Cannot create /sys/kernel/debug/dri/%s\n", name);
                 return -1;
         }
 
@@ -165,7 +165,7 @@ int drm_debugfs_init(struct drm_minor *minor, int minor_id,
                 ret = dev->driver->debugfs_init(minor);
                 if (ret) {
                         DRM_ERROR("DRM: Driver failed to initialize "
-                                  "/debugfs/dri.\n");
+                                  "/sys/kernel/debug/dri.\n");
                         return ret;
                 }
         }
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 019b7c578236..1bf7efd8d334 100644
--- a/drivers/gpu/drm/drm_drv.c
+++ b/drivers/gpu/drm/drm_drv.c
@@ -339,7 +339,7 @@ static int __init drm_core_init(void)
 
         drm_debugfs_root = debugfs_create_dir("dri", NULL);
         if (!drm_debugfs_root) {
-                DRM_ERROR("Cannot create /debugfs/dri\n");
+                DRM_ERROR("Cannot create /sys/kernel/debug/dri\n");
                 ret = -1;
                 goto err_p3;
         }
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index 7819fd930a51..a912a0ff11cc 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -188,36 +188,34 @@ static struct drm_mm_node *drm_mm_split_at_start(struct drm_mm_node *parent,
 
 
 
-struct drm_mm_node *drm_mm_get_block(struct drm_mm_node * parent,
-                                unsigned long size, unsigned alignment)
+struct drm_mm_node *drm_mm_get_block(struct drm_mm_node *node,
+                                     unsigned long size, unsigned alignment)
 {
 
         struct drm_mm_node *align_splitoff = NULL;
-        struct drm_mm_node *child;
         unsigned tmp = 0;
 
         if (alignment)
-                tmp = parent->start % alignment;
+                tmp = node->start % alignment;
 
         if (tmp) {
                 align_splitoff =
-                    drm_mm_split_at_start(parent, alignment - tmp, 0);
+                    drm_mm_split_at_start(node, alignment - tmp, 0);
                 if (unlikely(align_splitoff == NULL))
                         return NULL;
         }
 
-        if (parent->size == size) {
-                list_del_init(&parent->fl_entry);
-                parent->free = 0;
-                return parent;
+        if (node->size == size) {
+                list_del_init(&node->fl_entry);
+                node->free = 0;
         } else {
-                child = drm_mm_split_at_start(parent, size, 0);
+                node = drm_mm_split_at_start(node, size, 0);
         }
 
         if (align_splitoff)
                 drm_mm_put_block(align_splitoff);
 
-        return child;
+        return node;
 }
 
 EXPORT_SYMBOL(drm_mm_get_block);
diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
index 89050684fe0d..387a8de1bc7e 100644
--- a/drivers/gpu/drm/drm_stub.c
+++ b/drivers/gpu/drm/drm_stub.c
@@ -343,7 +343,7 @@ static int drm_get_minor(struct drm_device *dev, struct drm_minor **minor, int t
 #if defined(CONFIG_DEBUG_FS)
         ret = drm_debugfs_init(new_minor, minor_id, drm_debugfs_root);
         if (ret) {
-                DRM_ERROR("DRM: Failed to initialize /debugfs/dri.\n");
+                DRM_ERROR("DRM: Failed to initialize /sys/kernel/debug/dri.\n");
                 goto err_g2;
         }
 #endif
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index 9987ab880835..85ec31b3ff00 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -70,6 +70,11 @@ static ssize_t version_show(struct class *dev, char *buf)
                        CORE_MINOR, CORE_PATCHLEVEL, CORE_DATE);
 }
 
+static char *drm_nodename(struct device *dev)
+{
+        return kasprintf(GFP_KERNEL, "dri/%s", dev_name(dev));
+}
+
 static CLASS_ATTR(version, S_IRUGO, version_show, NULL);
 
 /**
@@ -101,6 +106,8 @@ struct class *drm_sysfs_create(struct module *owner, char *name)
         if (err)
                 goto err_out_class;
 
+        class->nodename = drm_nodename;
+
         return class;
 
 err_out_class:
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index 0ecf6b76a401..8e28e5993df5 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -504,6 +504,14 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width,
         info->fbops = &intelfb_ops;
 
         info->fix.line_length = fb->pitch;
+
+        /* setup aperture base/size for vesafb takeover */
+        info->aperture_base = dev->mode_config.fb_base;
+        if (IS_I9XX(dev))
+                info->aperture_size = pci_resource_len(dev->pdev, 2);
+        else
+                info->aperture_size = pci_resource_len(dev->pdev, 0);
+
         info->fix.smem_start = dev->mode_config.fb_base + obj_priv->gtt_offset;
         info->fix.smem_len = size;
 
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
new file mode 100644
index 000000000000..2168d67f09a6
--- /dev/null
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -0,0 +1,34 @@
+config DRM_RADEON_KMS
+        bool "Enable modesetting on radeon by default"
+        depends on DRM_RADEON
+        select DRM_TTM
+        help
+          Choose this option if you want kernel modesetting enabled by default,
+          and you have a new enough userspace to support this. Running old
+          userspaces with this enabled will cause pain.
+
+          When kernel modesetting is enabled the IOCTL of radeon/drm
+          driver are considered as invalid and an error message is printed
+          in the log and they return failure.
+
+          KMS enabled userspace will use new API to talk with the radeon/drm
+          driver. The new API provide functions to create/destroy/share/mmap
+          buffer object which are then managed by the kernel memory manager
+          (here TTM). In order to submit command to the GPU the userspace
+          provide a buffer holding the command stream, along this buffer
+          userspace have to provide a list of buffer object used by the
+          command stream. The kernel radeon driver will then place buffer
+          in GPU accessible memory and will update command stream to reflect
+          the position of the different buffers.
+
+          The kernel will also perform security check on command stream
+          provided by the user, we want to catch and forbid any illegal use
+          of the GPU such as DMA into random system memory or into memory
+          not owned by the process supplying the command stream. This part
+          of the code is still incomplete and this why we propose that patch
+          as a staging driver addition, future security might forbid current
+          experimental userspace to run.
+
+          This code support the following hardware : R1XX,R2XX,R3XX,R4XX,R5XX
+          (radeon up to X1950). Works is underway to provide support for R6XX,
+          R7XX and newer hardware (radeon from HD2XXX to HD4XXX).
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 52ce439a0f2e..5fae1e074b4b 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -3,7 +3,17 @@
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
 
 ccflags-y := -Iinclude/drm
-radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o r600_cp.o
+radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
+        radeon_irq.o r300_cmdbuf.o r600_cp.o
+
+radeon-$(CONFIG_DRM_RADEON_KMS) += radeon_device.o radeon_kms.o \
+        radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \
+        atom.o radeon_fence.o radeon_ttm.o radeon_object.o radeon_gart.o \
+        radeon_legacy_crtc.o radeon_legacy_encoders.o radeon_connectors.o \
+        radeon_encoders.o radeon_display.o radeon_cursor.o radeon_i2c.o \
+        radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \
+        radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
+        rs400.o rs600.o rs690.o rv515.o r520.o r600.o rs780.o rv770.o
 
 radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
 
diff --git a/drivers/gpu/drm/radeon/ObjectID.h b/drivers/gpu/drm/radeon/ObjectID.h
new file mode 100644
index 000000000000..6d0183c61d3b
--- /dev/null
+++ b/drivers/gpu/drm/radeon/ObjectID.h
@@ -0,0 +1,578 @@
+/*
+* Copyright 2006-2007 Advanced Micro Devices, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*/
+/* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */
+
+#ifndef _OBJECTID_H
+#define _OBJECTID_H
+
+#if defined(_X86_)
+#pragma pack(1)
+#endif
+
+/****************************************************/
+/* Graphics Object Type Definition                  */
+/****************************************************/
+#define GRAPH_OBJECT_TYPE_NONE                    0x0
+#define GRAPH_OBJECT_TYPE_GPU                     0x1
+#define GRAPH_OBJECT_TYPE_ENCODER                 0x2
+#define GRAPH_OBJECT_TYPE_CONNECTOR               0x3
+#define GRAPH_OBJECT_TYPE_ROUTER                  0x4
+/* deleted */
+
+/****************************************************/
+/* Encoder Object ID Definition                     */
+/****************************************************/
+#define ENCODER_OBJECT_ID_NONE                    0x00
+
+/* Radeon Class Display Hardware */
+#define ENCODER_OBJECT_ID_INTERNAL_LVDS           0x01
+#define ENCODER_OBJECT_ID_INTERNAL_TMDS1          0x02
+#define ENCODER_OBJECT_ID_INTERNAL_TMDS2          0x03
+#define ENCODER_OBJECT_ID_INTERNAL_DAC1           0x04
+#define ENCODER_OBJECT_ID_INTERNAL_DAC2           0x05  /* TV/CV DAC */
+#define ENCODER_OBJECT_ID_INTERNAL_SDVOA          0x06
+#define ENCODER_OBJECT_ID_INTERNAL_SDVOB          0x07
+
+/* External Third Party Encoders */
+#define ENCODER_OBJECT_ID_SI170B                  0x08
+#define ENCODER_OBJECT_ID_CH7303                  0x09
+#define ENCODER_OBJECT_ID_CH7301                  0x0A
+#define ENCODER_OBJECT_ID_INTERNAL_DVO1           0x0B  /* This belongs to Radeon Class Display Hardware */
+#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA          0x0C
+#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB          0x0D
+#define ENCODER_OBJECT_ID_TITFP513                0x0E
+#define ENCODER_OBJECT_ID_INTERNAL_LVTM1          0x0F  /* not used for Radeon */
+#define ENCODER_OBJECT_ID_VT1623                  0x10
+#define ENCODER_OBJECT_ID_HDMI_SI1930             0x11
+#define ENCODER_OBJECT_ID_HDMI_INTERNAL           0x12
+/* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1   0x13
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1    0x14
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1    0x15
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2    0x16  /* Shared with CV/TV and CRT */
+#define ENCODER_OBJECT_ID_SI178                   0X17  /* External TMDS (dual link, no HDCP.) */
+#define ENCODER_OBJECT_ID_MVPU_FPGA               0x18  /* MVPU FPGA chip */
+#define ENCODER_OBJECT_ID_INTERNAL_DDI            0x19
+#define ENCODER_OBJECT_ID_VT1625                  0x1A
+#define ENCODER_OBJECT_ID_HDMI_SI1932             0x1B
+#define ENCODER_OBJECT_ID_DP_AN9801               0x1C
+#define ENCODER_OBJECT_ID_DP_DP501                0x1D
+#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY         0x1E
+#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA   0x1F
+#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1        0x20
+#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2        0x21
+
+#define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO    0xFF
+
+/****************************************************/
+/* Connector Object ID Definition                   */
+/****************************************************/
+#define CONNECTOR_OBJECT_ID_NONE                  0x00
+#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I     0x01
+#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I       0x02
+#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D     0x03
+#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D       0x04
+#define CONNECTOR_OBJECT_ID_VGA                   0x05
+#define CONNECTOR_OBJECT_ID_COMPOSITE             0x06
+#define CONNECTOR_OBJECT_ID_SVIDEO                0x07
+#define CONNECTOR_OBJECT_ID_YPbPr                 0x08
+#define CONNECTOR_OBJECT_ID_D_CONNECTOR           0x09
+#define CONNECTOR_OBJECT_ID_9PIN_DIN              0x0A  /* Supports both CV & TV */
+#define CONNECTOR_OBJECT_ID_SCART                 0x0B
+#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A           0x0C
+#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B           0x0D
+#define CONNECTOR_OBJECT_ID_LVDS                  0x0E
+#define CONNECTOR_OBJECT_ID_7PIN_DIN              0x0F
+#define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR        0x10
+#define CONNECTOR_OBJECT_ID_CROSSFIRE             0x11
+#define CONNECTOR_OBJECT_ID_HARDCODE_DVI          0x12
+#define CONNECTOR_OBJECT_ID_DISPLAYPORT           0x13
+
+/* deleted */
+
+/****************************************************/
+/* Router Object ID Definition                      */
+/****************************************************/
+#define ROUTER_OBJECT_ID_NONE                                                                                   0x00
+#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL                              0x01
+
+/****************************************************/
+/* Graphics Object ENUM ID Definition               */
+/****************************************************/
+#define GRAPH_OBJECT_ENUM_ID1                     0x01
+#define GRAPH_OBJECT_ENUM_ID2                     0x02
+#define GRAPH_OBJECT_ENUM_ID3                     0x03
+#define GRAPH_OBJECT_ENUM_ID4                     0x04
+#define GRAPH_OBJECT_ENUM_ID5                     0x05
+#define GRAPH_OBJECT_ENUM_ID6                     0x06
+
+/****************************************************/
+/* Graphics Object ID Bit definition                */
+/****************************************************/
+#define OBJECT_ID_MASK                            0x00FF
+#define ENUM_ID_MASK                              0x0700
+#define RESERVED1_ID_MASK                         0x0800
+#define OBJECT_TYPE_MASK                          0x7000
+#define RESERVED2_ID_MASK                         0x8000
+
+#define OBJECT_ID_SHIFT                           0x00
+#define ENUM_ID_SHIFT                             0x08
+#define OBJECT_TYPE_SHIFT                         0x0C
+
+/****************************************************/
+/* Graphics Object family definition                */
+/****************************************************/
+#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) \
+        (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
+         GRAPHICS_OBJECT_ID   << OBJECT_ID_SHIFT)
+/****************************************************/
+/* GPU Object ID definition - Shared with BIOS      */
+/****************************************************/
+#define GPU_ENUM_ID1    (GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
+                         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
+
+/****************************************************/
+/* Encoder Object ID definition - Shared with BIOS  */
+/****************************************************/
+/*
+#define ENCODER_INTERNAL_LVDS_ENUM_ID1        0x2101
+#define ENCODER_INTERNAL_TMDS1_ENUM_ID1       0x2102
+#define ENCODER_INTERNAL_TMDS2_ENUM_ID1       0x2103
+#define ENCODER_INTERNAL_DAC1_ENUM_ID1        0x2104
+#define ENCODER_INTERNAL_DAC2_ENUM_ID1        0x2105
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID1       0x2106
+#define ENCODER_INTERNAL_SDVOB_ENUM_ID1       0x2107
+#define ENCODER_SIL170B_ENUM_ID1              0x2108
+#define ENCODER_CH7303_ENUM_ID1               0x2109
+#define ENCODER_CH7301_ENUM_ID1               0x210A
+#define ENCODER_INTERNAL_DVO1_ENUM_ID1        0x210B
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1       0x210C
+#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1       0x210D
+#define ENCODER_TITFP513_ENUM_ID1             0x210E
+#define ENCODER_INTERNAL_LVTM1_ENUM_ID1       0x210F
+#define ENCODER_VT1623_ENUM_ID1               0x2110
+#define ENCODER_HDMI_SI1930_ENUM_ID1          0x2111
+#define ENCODER_HDMI_INTERNAL_ENUM_ID1        0x2112
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1   0x2113
+#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1    0x2114
+#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1    0x2115
+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1    0x2116
+#define ENCODER_SI178_ENUM_ID1                   0x2117
+#define ENCODER_MVPU_FPGA_ENUM_ID1               0x2118
+#define ENCODER_INTERNAL_DDI_ENUM_ID1            0x2119
+#define ENCODER_VT1625_ENUM_ID1                  0x211A
+#define ENCODER_HDMI_SI1932_ENUM_ID1             0x211B
+#define ENCODER_ENCODER_DP_AN9801_ENUM_ID1       0x211C
+#define ENCODER_DP_DP501_ENUM_ID1                0x211D
+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1         0x211E
+*/
+#define ENCODER_INTERNAL_LVDS_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DAC1_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DAC2_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
+
+#define ENCODER_SIL170B_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
+
+#define ENCODER_CH7303_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
+
+#define ENCODER_CH7301_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DVO1_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
+
+#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
+
+#define ENCODER_TITFP513_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_VT1623_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_SI1930_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_INTERNAL_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) /* Shared with CV/TV and CRT */
+
+#define ENCODER_SI178_ENUM_ID1  \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
+
+#define ENCODER_MVPU_FPGA_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_DDI_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
+
+#define ENCODER_VT1625_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
+
+#define ENCODER_HDMI_SI1932_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
+
+#define ENCODER_DP_DP501_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
+
+#define ENCODER_DP_AN9801_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
+
+#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
+
+/****************************************************/
+/* Connector Object ID definition - Shared with BIOS */
+/****************************************************/
+/*
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1        0x3101
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1          0x3102
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1        0x3103
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1          0x3104
+#define CONNECTOR_VGA_ENUM_ID1                      0x3105
+#define CONNECTOR_COMPOSITE_ENUM_ID1                0x3106
+#define CONNECTOR_SVIDEO_ENUM_ID1                   0x3107
+#define CONNECTOR_YPbPr_ENUM_ID1                    0x3108
+#define CONNECTOR_D_CONNECTORE_ENUM_ID1             0x3109
+#define CONNECTOR_9PIN_DIN_ENUM_ID1                 0x310A
+#define CONNECTOR_SCART_ENUM_ID1                    0x310B
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1              0x310C
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1              0x310D
+#define CONNECTOR_LVDS_ENUM_ID1                     0x310E
+#define CONNECTOR_7PIN_DIN_ENUM_ID1                 0x310F
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1           0x3110
+*/
+#define CONNECTOR_LVDS_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_VGA_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_VGA_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_COMPOSITE_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SVIDEO_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_YPbPr_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_D_CONNECTOR_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_9PIN_DIN_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_SCART_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_7PIN_DIN_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_CROSSFIRE_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_CROSSFIRE_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID2 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID3 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+#define CONNECTOR_DISPLAYPORT_ENUM_ID4 \
+        (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
+         CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+
+/****************************************************/
+/* Router Object ID definition - Shared with BIOS   */
+/****************************************************/
+#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 \
+        (GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
+         GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+         ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
+
+/* deleted */
+
+/****************************************************/
+/* Object Cap definition - Shared with BIOS         */
+/****************************************************/
+#define GRAPHICS_OBJECT_CAP_I2C                 0x00000001L
+#define GRAPHICS_OBJECT_CAP_TABLE_ID            0x00000002L
+
+#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID                   0x01
+#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID     0x02
+#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID    0x03
+
+#if defined(_X86_)
+#pragma pack()
+#endif
+
+#endif /*GRAPHICTYPE */
diff --git a/drivers/gpu/drm/radeon/atom-bits.h b/drivers/gpu/drm/radeon/atom-bits.h
new file mode 100644
index 000000000000..e8fae5c77514
--- /dev/null
+++ b/drivers/gpu/drm/radeon/atom-bits.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Stanislaw Skowronek
+ */
+
+#ifndef ATOM_BITS_H
+#define ATOM_BITS_H
+
+static inline uint8_t get_u8(void *bios, int ptr)
+{
+    return ((unsigned char *)bios)[ptr];
+}
+#define U8(ptr) get_u8(ctx->ctx->bios, (ptr))
+#define CU8(ptr) get_u8(ctx->bios, (ptr))
+static inline uint16_t get_u16(void *bios, int ptr)
+{
+    return get_u8(bios ,ptr)|(((uint16_t)get_u8(bios, ptr+1))<<8);
+}
+#define U16(ptr) get_u16(ctx->ctx->bios, (ptr))
+#define CU16(ptr) get_u16(ctx->bios, (ptr))
+static inline uint32_t get_u32(void *bios, int ptr)
+{
+    return get_u16(bios, ptr)|(((uint32_t)get_u16(bios, ptr+2))<<16);
+}
+#define U32(ptr) get_u32(ctx->ctx->bios, (ptr))
+#define CU32(ptr) get_u32(ctx->bios, (ptr))
+#define CSTR(ptr) (((char *)(ctx->bios))+(ptr))
+
+#endif
diff --git a/drivers/gpu/drm/radeon/atom-names.h b/drivers/gpu/drm/radeon/atom-names.h
new file mode 100644
index 000000000000..6f907a5ffa5f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/atom-names.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Stanislaw Skowronek
+ */
+
+#ifndef ATOM_NAMES_H
+#define ATOM_NAMES_H
+
+#include "atom.h"
+
+#ifdef ATOM_DEBUG
+
+#define ATOM_OP_NAMES_CNT 123
+static char *atom_op_names[ATOM_OP_NAMES_CNT] = {
+"RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL",
+"MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC",
+"OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG",
+"SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL",
+"SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS",
+"SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG",
+"MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS",
+"DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS",
+"ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB",
+"SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT",
+"SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS",
+"COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH",
+"JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL",
+"JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS",
+"TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC",
+"CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB",
+"CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS",
+"MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG",
+"RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB",
+"XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL",
+"SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC",
+"DEBUG", "CTB_DS",
+};
+
+#define ATOM_TABLE_NAMES_CNT 74
+static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = {
+"ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit",
+"VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit",
+"GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl",
+"GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock",
+"DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice",
+"MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController",
+"EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange",
+"DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl",
+"DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl",
+"CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl",
+"TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl",
+"EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock",
+"EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing",
+"SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source",
+"EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters",
+"LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock",
+"GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection",
+"DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp",
+"ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C",
+"ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection",
+"MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion",
+"VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining",
+"EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl",
+"CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource",
+"MemoryDeviceInit", "EnableYUV",
+};
+
+#define ATOM_IO_NAMES_CNT 5
+static char *atom_io_names[ATOM_IO_NAMES_CNT] = {
+"MM", "PLL", "MC", "PCIE", "PCIE PORT",
+};
+
+#else
+
+#define ATOM_OP_NAMES_CNT 0
+#define ATOM_TABLE_NAMES_CNT 0
+#define ATOM_IO_NAMES_CNT 0
+
+#endif
+
+#endif
diff --git a/drivers/gpu/drm/radeon/atom-types.h b/drivers/gpu/drm/radeon/atom-types.h
new file mode 100644
index 000000000000..1125b866cdb0
--- /dev/null
+++ b/drivers/gpu/drm/radeon/atom-types.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Dave Airlie
+ */
+
+#ifndef ATOM_TYPES_H
+#define ATOM_TYPES_H
+
+/* sync atom types to kernel types */
+
+typedef uint16_t USHORT;
+typedef uint32_t ULONG;
+typedef uint8_t UCHAR;
+
+
+#ifndef ATOM_BIG_ENDIAN
+#if defined(__BIG_ENDIAN)
+#define ATOM_BIG_ENDIAN 1
+#else
+#define ATOM_BIG_ENDIAN 0
+#endif
+#endif
+#endif
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
new file mode 100644
index 000000000000..901befe03da2
--- /dev/null
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -0,0 +1,1215 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Stanislaw Skowronek
+ */
+
+#include <linux/module.h>
+#include <linux/sched.h>
+
+#define ATOM_DEBUG
+
+#include "atom.h"
+#include "atom-names.h"
+#include "atom-bits.h"
+
+#define ATOM_COND_ABOVE         0
+#define ATOM_COND_ABOVEOREQUAL  1
+#define ATOM_COND_ALWAYS        2
+#define ATOM_COND_BELOW         3
+#define ATOM_COND_BELOWOREQUAL  4
+#define ATOM_COND_EQUAL         5
+#define ATOM_COND_NOTEQUAL      6
+
+#define ATOM_PORT_ATI   0
+#define ATOM_PORT_PCI   1
+#define ATOM_PORT_SYSIO 2
+
+#define ATOM_UNIT_MICROSEC      0
+#define ATOM_UNIT_MILLISEC      1
+
+#define PLL_INDEX       2
+#define PLL_DATA        3
+
+typedef struct {
+        struct atom_context *ctx;
+
+        uint32_t *ps, *ws;
+        int ps_shift;
+        uint16_t start;
+} atom_exec_context;
+
+int atom_debug = 0;
+void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params);
+
+static uint32_t atom_arg_mask[8] =
+    { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
+0xFF000000 };
+static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
+
+static int atom_dst_to_src[8][4] = {
+        /* translate destination alignment field to the source alignment encoding */
+        {0, 0, 0, 0},
+        {1, 2, 3, 0},
+        {1, 2, 3, 0},
+        {1, 2, 3, 0},
+        {4, 5, 6, 7},
+        {4, 5, 6, 7},
+        {4, 5, 6, 7},
+        {4, 5, 6, 7},
+};
+static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
+
+static int debug_depth = 0;
+#ifdef ATOM_DEBUG
+static void debug_print_spaces(int n)
+{
+        while (n--)
+                printk("   ");
+}
+
+#define DEBUG(...) do if (atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
+#define SDEBUG(...) do if (atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
+#else
+#define DEBUG(...) do { } while (0)
+#define SDEBUG(...) do { } while (0)
+#endif
+
+static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
+                                 uint32_t index, uint32_t data)
+{
+        uint32_t temp = 0xCDCDCDCD;
+        while (1)
+                switch (CU8(base)) {
+                case ATOM_IIO_NOP:
+                        base++;
+                        break;
+                case ATOM_IIO_READ:
+                        temp = ctx->card->reg_read(ctx->card, CU16(base + 1));
+                        base += 3;
+                        break;
+                case ATOM_IIO_WRITE:
+                        ctx->card->reg_write(ctx->card, CU16(base + 1), temp);
+                        base += 3;
+                        break;
+                case ATOM_IIO_CLEAR:
+                        temp &=
+                            ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
+                              CU8(base + 2));
+                        base += 3;
+                        break;
+                case ATOM_IIO_SET:
+                        temp |=
+                            (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
+                                                                        2);
+                        base += 3;
+                        break;
+                case ATOM_IIO_MOVE_INDEX:
+                        temp &=
+                            ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
+                              CU8(base + 2));
+                        temp |=
+                            ((index >> CU8(base + 2)) &
+                             (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
+                                                                          3);
+                        base += 4;
+                        break;
+                case ATOM_IIO_MOVE_DATA:
+                        temp &=
+                            ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
+                              CU8(base + 2));
+                        temp |=
+                            ((data >> CU8(base + 2)) &
+                             (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
+                                                                          3);
+                        base += 4;
+                        break;
+                case ATOM_IIO_MOVE_ATTR:
+                        temp &=
+                            ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
+                              CU8(base + 2));
+                        temp |=
+                            ((ctx->
+                              io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
+                                                                          CU8
+                                                                          (base
+                                                                           +
+                                                                           1))))
+                            << CU8(base + 3);
+                        base += 4;
+                        break;
+                case ATOM_IIO_END:
+                        return temp;
+                default:
+                        printk(KERN_INFO "Unknown IIO opcode.\n");
+                        return 0;
+                }
+}
+
+static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
+                                 int *ptr, uint32_t *saved, int print)
+{
+        uint32_t idx, val = 0xCDCDCDCD, align, arg;
+        struct atom_context *gctx = ctx->ctx;
+        arg = attr & 7;
+        align = (attr >> 3) & 7;
+        switch (arg) {
+        case ATOM_ARG_REG:
+                idx = U16(*ptr);
+                (*ptr) += 2;
+                if (print)
+                        DEBUG("REG[0x%04X]", idx);
+                idx += gctx->reg_block;
+                switch (gctx->io_mode) {
+                case ATOM_IO_MM:
+                        val = gctx->card->reg_read(gctx->card, idx);
+                        break;
+                case ATOM_IO_PCI:
+                        printk(KERN_INFO
+                               "PCI registers are not implemented.\n");
+                        return 0;
+                case ATOM_IO_SYSIO:
+                        printk(KERN_INFO
+                               "SYSIO registers are not implemented.\n");
+                        return 0;
+                default:
+                        if (!(gctx->io_mode & 0x80)) {
+                                printk(KERN_INFO "Bad IO mode.\n");
+                                return 0;
+                        }
+                        if (!gctx->iio[gctx->io_mode & 0x7F]) {
+                                printk(KERN_INFO
+                                       "Undefined indirect IO read method %d.\n",
+                                       gctx->io_mode & 0x7F);
+                                return 0;
+                        }
+                        val =
+                            atom_iio_execute(gctx,
+                                             gctx->iio[gctx->io_mode & 0x7F],
+                                             idx, 0);
+                }
+                break;
+        case ATOM_ARG_PS:
+                idx = U8(*ptr);
+                (*ptr)++;
+                val = le32_to_cpu(ctx->ps[idx]);
+                if (print)
+                        DEBUG("PS[0x%02X,0x%04X]", idx, val);
+                break;
+        case ATOM_ARG_WS:
+                idx = U8(*ptr);
+                (*ptr)++;
+                if (print)
+                        DEBUG("WS[0x%02X]", idx);
+                switch (idx) {
+                case ATOM_WS_QUOTIENT:
+                        val = gctx->divmul[0];
+                        break;
+                case ATOM_WS_REMAINDER:
+                        val = gctx->divmul[1];
+                        break;
+                case ATOM_WS_DATAPTR:
+                        val = gctx->data_block;
+                        break;
+                case ATOM_WS_SHIFT:
+                        val = gctx->shift;
+                        break;
+                case ATOM_WS_OR_MASK:
+                        val = 1 << gctx->shift;
+                        break;
+                case ATOM_WS_AND_MASK:
+                        val = ~(1 << gctx->shift);
+                        break;
+                case ATOM_WS_FB_WINDOW:
+                        val = gctx->fb_base;
+                        break;
+                case ATOM_WS_ATTRIBUTES:
+                        val = gctx->io_attr;
+                        break;
+                default:
+                        val = ctx->ws[idx];
+                }
+                break;
+        case ATOM_ARG_ID:
+                idx = U16(*ptr);
+                (*ptr) += 2;
+                if (print) {
+                        if (gctx->data_block)
+                                DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
+                        else
+                                DEBUG("ID[0x%04X]", idx);
+                }
+                val = U32(idx + gctx->data_block);
+                break;
+        case ATOM_ARG_FB:
+                idx = U8(*ptr);
+                (*ptr)++;
+                if (print)
+                        DEBUG("FB[0x%02X]", idx);
+                printk(KERN_INFO "FB access is not implemented.\n");
+                return 0;
+        case ATOM_ARG_IMM:
+                switch (align) {
+                case ATOM_SRC_DWORD:
+                        val = U32(*ptr);
+                        (*ptr) += 4;
+                        if (print)
+                                DEBUG("IMM 0x%08X\n", val);
+                        return val;
+                case ATOM_SRC_WORD0:
+                case ATOM_SRC_WORD8:
+                case ATOM_SRC_WORD16:
+                        val = U16(*ptr);
+                        (*ptr) += 2;
+                        if (print)
+                                DEBUG("IMM 0x%04X\n", val);
+                        return val;
+                case ATOM_SRC_BYTE0:
+                case ATOM_SRC_BYTE8:
+                case ATOM_SRC_BYTE16:
+                case ATOM_SRC_BYTE24:
+                        val = U8(*ptr);
+                        (*ptr)++;
+                        if (print)
+                                DEBUG("IMM 0x%02X\n", val);
+                        return val;
+                }
+                return 0;
+        case ATOM_ARG_PLL:
+                idx = U8(*ptr);
+                (*ptr)++;
+                if (print)
+                        DEBUG("PLL[0x%02X]", idx);
+                val = gctx->card->pll_read(gctx->card, idx);
+                break;
+        case ATOM_ARG_MC:
+                idx = U8(*ptr);
+                (*ptr)++;
+                if (print)
+                        DEBUG("MC[0x%02X]", idx);
+                val = gctx->card->mc_read(gctx->card, idx);
+                break;
+        }
+        if (saved)
+                *saved = val;
+        val &= atom_arg_mask[align];
+        val >>= atom_arg_shift[align];
+        if (print)
+                switch (align) {
+                case ATOM_SRC_DWORD:
+                        DEBUG(".[31:0] -> 0x%08X\n", val);
+                        break;
+                case ATOM_SRC_WORD0:
+                        DEBUG(".[15:0] -> 0x%04X\n", val);
+                        break;
+                case ATOM_SRC_WORD8:
+                        DEBUG(".[23:8] -> 0x%04X\n", val);
+                        break;
+                case ATOM_SRC_WORD16:
+                        DEBUG(".[31:16] -> 0x%04X\n", val);
+                        break;
+                case ATOM_SRC_BYTE0:
+                        DEBUG(".[7:0] -> 0x%02X\n", val);
+                        break;
+                case ATOM_SRC_BYTE8:
+                        DEBUG(".[15:8] -> 0x%02X\n", val);
+                        break;
+                case ATOM_SRC_BYTE16:
+                        DEBUG(".[23:16] -> 0x%02X\n", val);
+                        break;
+                case ATOM_SRC_BYTE24:
+                        DEBUG(".[31:24] -> 0x%02X\n", val);
+                        break;
+                }
+        return val;
+}
+
+static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
+{
+        uint32_t align = (attr >> 3) & 7, arg = attr & 7;
+        switch (arg) {
+        case ATOM_ARG_REG:
+        case ATOM_ARG_ID:
+                (*ptr) += 2;
+                break;
+        case ATOM_ARG_PLL:
+        case ATOM_ARG_MC:
+        case ATOM_ARG_PS:
+        case ATOM_ARG_WS:
+        case ATOM_ARG_FB:
+                (*ptr)++;
+                break;
+        case ATOM_ARG_IMM:
+                switch (align) {
+                case ATOM_SRC_DWORD:
+                        (*ptr) += 4;
+                        return;
+                case ATOM_SRC_WORD0:
+                case ATOM_SRC_WORD8:
+                case ATOM_SRC_WORD16:
+                        (*ptr) += 2;
+                        return;
+                case ATOM_SRC_BYTE0:
+                case ATOM_SRC_BYTE8:
+                case ATOM_SRC_BYTE16:
+                case ATOM_SRC_BYTE24:
+                        (*ptr)++;
+                        return;
+                }
+                return;
+        }
+}
+
+static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
+{
+        return atom_get_src_int(ctx, attr, ptr, NULL, 1);
+}
+
+static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
+                             int *ptr, uint32_t *saved, int print)
+{
+        return atom_get_src_int(ctx,
+                                arg | atom_dst_to_src[(attr >> 3) &
+                                                      7][(attr >> 6) & 3] << 3,
+                                ptr, saved, print);
+}
+
+static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
+{
+        atom_skip_src_int(ctx,
+                          arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
+                                                                 3] << 3, ptr);
+}
+
+static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
+                         int *ptr, uint32_t val, uint32_t saved)
+{
+        uint32_t align =
+            atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
+            val, idx;
+        struct atom_context *gctx = ctx->ctx;
+        old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
+        val <<= atom_arg_shift[align];
+        val &= atom_arg_mask[align];
+        saved &= ~atom_arg_mask[align];
+        val |= saved;
+        switch (arg) {
+        case ATOM_ARG_REG:
+                idx = U16(*ptr);
+                (*ptr) += 2;
+                DEBUG("REG[0x%04X]", idx);
+                idx += gctx->reg_block;
+                switch (gctx->io_mode) {
+                case ATOM_IO_MM:
+                        if (idx == 0)
+                                gctx->card->reg_write(gctx->card, idx,
+                                                      val << 2);
+                        else
+                                gctx->card->reg_write(gctx->card, idx, val);
+                        break;
+                case ATOM_IO_PCI:
+                        printk(KERN_INFO
+                               "PCI registers are not implemented.\n");
+                        return;
+                case ATOM_IO_SYSIO:
+                        printk(KERN_INFO
+                               "SYSIO registers are not implemented.\n");
+                        return;
+                default:
+                        if (!(gctx->io_mode & 0x80)) {
+                                printk(KERN_INFO "Bad IO mode.\n");
+                                return;
+                        }
+                        if (!gctx->iio[gctx->io_mode & 0xFF]) {
+                                printk(KERN_INFO
+                                       "Undefined indirect IO write method %d.\n",
+                                       gctx->io_mode & 0x7F);
+                                return;
+                        }
+                        atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
+                                         idx, val);
+                }
+                break;
+        case ATOM_ARG_PS:
+                idx = U8(*ptr);
+                (*ptr)++;
+                DEBUG("PS[0x%02X]", idx);
+                ctx->ps[idx] = cpu_to_le32(val);
+                break;
+        case ATOM_ARG_WS:
+                idx = U8(*ptr);
+                (*ptr)++;
+                DEBUG("WS[0x%02X]", idx);
+                switch (idx) {
+                case ATOM_WS_QUOTIENT:
+                        gctx->divmul[0] = val;
+                        break;
+                case ATOM_WS_REMAINDER:
+                        gctx->divmul[1] = val;
+                        break;
+                case ATOM_WS_DATAPTR:
+                        gctx->data_block = val;
+                        break;
+                case ATOM_WS_SHIFT:
+                        gctx->shift = val;
+                        break;
+                case ATOM_WS_OR_MASK:
+                case ATOM_WS_AND_MASK:
+                        break;
+                case ATOM_WS_FB_WINDOW:
+                        gctx->fb_base = val;
+                        break;
+                case ATOM_WS_ATTRIBUTES:
+                        gctx->io_attr = val;
+                        break;
+                default:
+                        ctx->ws[idx] = val;
+                }
+                break;
+        case ATOM_ARG_FB:
+                idx = U8(*ptr);
+                (*ptr)++;
+                DEBUG("FB[0x%02X]", idx);
+                printk(KERN_INFO "FB access is not implemented.\n");
+                return;
+        case ATOM_ARG_PLL:
+                idx = U8(*ptr);
+                (*ptr)++;
+                DEBUG("PLL[0x%02X]", idx);
+                gctx->card->pll_write(gctx->card, idx, val);
+                break;
+        case ATOM_ARG_MC:
+                idx = U8(*ptr);
+                (*ptr)++;
+                DEBUG("MC[0x%02X]", idx);
+                gctx->card->mc_write(gctx->card, idx, val);
+                return;
+        }
+        switch (align) {
+        case ATOM_SRC_DWORD:
+                DEBUG(".[31:0] <- 0x%08X\n", old_val);
+                break;
+        case ATOM_SRC_WORD0:
+                DEBUG(".[15:0] <- 0x%04X\n", old_val);
+                break;
+        case ATOM_SRC_WORD8:
+                DEBUG(".[23:8] <- 0x%04X\n", old_val);
+                break;
+        case ATOM_SRC_WORD16:
+                DEBUG(".[31:16] <- 0x%04X\n", old_val);
+                break;
+        case ATOM_SRC_BYTE0:
+                DEBUG(".[7:0] <- 0x%02X\n", old_val);
+                break;
+        case ATOM_SRC_BYTE8:
+                DEBUG(".[15:8] <- 0x%02X\n", old_val);
+                break;
+        case ATOM_SRC_BYTE16:
+                DEBUG(".[23:16] <- 0x%02X\n", old_val);
+                break;
+        case ATOM_SRC_BYTE24:
+                DEBUG(".[31:24] <- 0x%02X\n", old_val);
+                break;
+        }
+}
+
+static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src, saved;
+        int dptr = *ptr;
+        SDEBUG("   dst: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        SDEBUG("   src: ");
+        src = atom_get_src(ctx, attr, ptr);
+        dst += src;
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src, saved;
+        int dptr = *ptr;
+        SDEBUG("   dst: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        SDEBUG("   src: ");
+        src = atom_get_src(ctx, attr, ptr);
+        dst &= src;
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
+{
+        printk("ATOM BIOS beeped!\n");
+}
+
+static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
+{
+        int idx = U8((*ptr)++);
+        if (idx < ATOM_TABLE_NAMES_CNT)
+                SDEBUG("   table: %d (%s)\n", idx, atom_table_names[idx]);
+        else
+                SDEBUG("   table: %d\n", idx);
+        if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
+                atom_execute_table(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
+}
+
+static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t saved;
+        int dptr = *ptr;
+        attr &= 0x38;
+        attr |= atom_def_dst[attr >> 3] << 6;
+        atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
+}
+
+static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src;
+        SDEBUG("   src1: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
+        SDEBUG("   src2: ");
+        src = atom_get_src(ctx, attr, ptr);
+        ctx->ctx->cs_equal = (dst == src);
+        ctx->ctx->cs_above = (dst > src);
+        SDEBUG("   result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
+               ctx->ctx->cs_above ? "GT" : "LE");
+}
+
+static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t count = U8((*ptr)++);
+        SDEBUG("   count: %d\n", count);
+        if (arg == ATOM_UNIT_MICROSEC)
+                schedule_timeout_uninterruptible(usecs_to_jiffies(count));
+        else
+                schedule_timeout_uninterruptible(msecs_to_jiffies(count));
+}
+
+static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src;
+        SDEBUG("   src1: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
+        SDEBUG("   src2: ");
+        src = atom_get_src(ctx, attr, ptr);
+        if (src != 0) {
+                ctx->ctx->divmul[0] = dst / src;
+                ctx->ctx->divmul[1] = dst % src;
+        } else {
+                ctx->ctx->divmul[0] = 0;
+                ctx->ctx->divmul[1] = 0;
+        }
+}
+
+static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
+{
+        /* functionally, a nop */
+}
+
+static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
+{
+        int execute = 0, target = U16(*ptr);
+        (*ptr) += 2;
+        switch (arg) {
+        case ATOM_COND_ABOVE:
+                execute = ctx->ctx->cs_above;
+                break;
+        case ATOM_COND_ABOVEOREQUAL:
+                execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
+                break;
+        case ATOM_COND_ALWAYS:
+                execute = 1;
+                break;
+        case ATOM_COND_BELOW:
+                execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
+                break;
+        case ATOM_COND_BELOWOREQUAL:
+                execute = !ctx->ctx->cs_above;
+                break;
+        case ATOM_COND_EQUAL:
+                execute = ctx->ctx->cs_equal;
+                break;
+        case ATOM_COND_NOTEQUAL:
+                execute = !ctx->ctx->cs_equal;
+                break;
+        }
+        if (arg != ATOM_COND_ALWAYS)
+                SDEBUG("   taken: %s\n", execute ? "yes" : "no");
+        SDEBUG("   target: 0x%04X\n", target);
+        if (execute)
+                *ptr = ctx->start + target;
+}
+
+static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src1, src2, saved;
+        int dptr = *ptr;
+        SDEBUG("   dst: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        SDEBUG("   src1: ");
+        src1 = atom_get_src(ctx, attr, ptr);
+        SDEBUG("   src2: ");
+        src2 = atom_get_src(ctx, attr, ptr);
+        dst &= src1;
+        dst |= src2;
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t src, saved;
+        int dptr = *ptr;
+        if (((attr >> 3) & 7) != ATOM_SRC_DWORD)
+                atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
+        else {
+                atom_skip_dst(ctx, arg, attr, ptr);
+                saved = 0xCDCDCDCD;
+        }
+        SDEBUG("   src: ");
+        src = atom_get_src(ctx, attr, ptr);
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, src, saved);
+}
+
+static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src;
+        SDEBUG("   src1: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
+        SDEBUG("   src2: ");
+        src = atom_get_src(ctx, attr, ptr);
+        ctx->ctx->divmul[0] = dst * src;
+}
+
+static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
+{
+        /* nothing */
+}
+
+static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src, saved;
+        int dptr = *ptr;
+        SDEBUG("   dst: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        SDEBUG("   src: ");
+        src = atom_get_src(ctx, attr, ptr);
+        dst |= src;
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t val = U8((*ptr)++);
+        SDEBUG("POST card output: 0x%02X\n", val);
+}
+
+static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
+{
+        printk(KERN_INFO "unimplemented!\n");
+}
+
+static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg)
+{
+        printk(KERN_INFO "unimplemented!\n");
+}
+
+static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg)
+{
+        printk(KERN_INFO "unimplemented!\n");
+}
+
+static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg)
+{
+        int idx = U8(*ptr);
+        (*ptr)++;
+        SDEBUG("   block: %d\n", idx);
+        if (!idx)
+                ctx->ctx->data_block = 0;
+        else if (idx == 255)
+                ctx->ctx->data_block = ctx->start;
+        else
+                ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
+        SDEBUG("   base: 0x%04X\n", ctx->ctx->data_block);
+}
+
+static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        SDEBUG("   fb_base: ");
+        ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
+}
+
+static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg)
+{
+        int port;
+        switch (arg) {
+        case ATOM_PORT_ATI:
+                port = U16(*ptr);
+                if (port < ATOM_IO_NAMES_CNT)
+                        SDEBUG("   port: %d (%s)\n", port, atom_io_names[port]);
+                else
+                        SDEBUG("   port: %d\n", port);
+                if (!port)
+                        ctx->ctx->io_mode = ATOM_IO_MM;
+                else
+                        ctx->ctx->io_mode = ATOM_IO_IIO | port;
+                (*ptr) += 2;
+                break;
+        case ATOM_PORT_PCI:
+                ctx->ctx->io_mode = ATOM_IO_PCI;
+                (*ptr)++;
+                break;
+        case ATOM_PORT_SYSIO:
+                ctx->ctx->io_mode = ATOM_IO_SYSIO;
+                (*ptr)++;
+                break;
+        }
+}
+
+static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
+{
+        ctx->ctx->reg_block = U16(*ptr);
+        (*ptr) += 2;
+        SDEBUG("   base: 0x%04X\n", ctx->ctx->reg_block);
+}
+
+static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++), shift;
+        uint32_t saved, dst;
+        int dptr = *ptr;
+        attr &= 0x38;
+        attr |= atom_def_dst[attr >> 3] << 6;
+        SDEBUG("   dst: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        shift = U8((*ptr)++);
+        SDEBUG("   shift: %d\n", shift);
+        dst <<= shift;
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++), shift;
+        uint32_t saved, dst;
+        int dptr = *ptr;
+        attr &= 0x38;
+        attr |= atom_def_dst[attr >> 3] << 6;
+        SDEBUG("   dst: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        shift = U8((*ptr)++);
+        SDEBUG("   shift: %d\n", shift);
+        dst >>= shift;
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src, saved;
+        int dptr = *ptr;
+        SDEBUG("   dst: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        SDEBUG("   src: ");
+        src = atom_get_src(ctx, attr, ptr);
+        dst -= src;
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t src, val, target;
+        SDEBUG("   switch: ");
+        src = atom_get_src(ctx, attr, ptr);
+        while (U16(*ptr) != ATOM_CASE_END)
+                if (U8(*ptr) == ATOM_CASE_MAGIC) {
+                        (*ptr)++;
+                        SDEBUG("   case: ");
+                        val =
+                            atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
+                                         ptr);
+                        target = U16(*ptr);
+                        if (val == src) {
+                                SDEBUG("   target: %04X\n", target);
+                                *ptr = ctx->start + target;
+                                return;
+                        }
+                        (*ptr) += 2;
+                } else {
+                        printk(KERN_INFO "Bad case.\n");
+                        return;
+                }
+        (*ptr) += 2;
+}
+
+static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src;
+        SDEBUG("   src1: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
+        SDEBUG("   src2: ");
+        src = atom_get_src(ctx, attr, ptr);
+        ctx->ctx->cs_equal = ((dst & src) == 0);
+        SDEBUG("   result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
+}
+
+static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src, saved;
+        int dptr = *ptr;
+        SDEBUG("   dst: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
+        SDEBUG("   src: ");
+        src = atom_get_src(ctx, attr, ptr);
+        dst ^= src;
+        SDEBUG("   dst: ");
+        atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
+}
+
+static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
+{
+        printk(KERN_INFO "unimplemented!\n");
+}
+
+static struct {
+        void (*func) (atom_exec_context *, int *, int);
+        int arg;
+} opcode_table[ATOM_OP_CNT] = {
+        {
+        NULL, 0}, {
+        atom_op_move, ATOM_ARG_REG}, {
+        atom_op_move, ATOM_ARG_PS}, {
+        atom_op_move, ATOM_ARG_WS}, {
+        atom_op_move, ATOM_ARG_FB}, {
+        atom_op_move, ATOM_ARG_PLL}, {
+        atom_op_move, ATOM_ARG_MC}, {
+        atom_op_and, ATOM_ARG_REG}, {
+        atom_op_and, ATOM_ARG_PS}, {
+        atom_op_and, ATOM_ARG_WS}, {
+        atom_op_and, ATOM_ARG_FB}, {
+        atom_op_and, ATOM_ARG_PLL}, {
+        atom_op_and, ATOM_ARG_MC}, {
+        atom_op_or, ATOM_ARG_REG}, {
+        atom_op_or, ATOM_ARG_PS}, {
+        atom_op_or, ATOM_ARG_WS}, {
+        atom_op_or, ATOM_ARG_FB}, {
+        atom_op_or, ATOM_ARG_PLL}, {
+        atom_op_or, ATOM_ARG_MC}, {
+        atom_op_shl, ATOM_ARG_REG}, {
+        atom_op_shl, ATOM_ARG_PS}, {
+        atom_op_shl, ATOM_ARG_WS}, {
+        atom_op_shl, ATOM_ARG_FB}, {
+        atom_op_shl, ATOM_ARG_PLL}, {
+        atom_op_shl, ATOM_ARG_MC}, {
+        atom_op_shr, ATOM_ARG_REG}, {
+        atom_op_shr, ATOM_ARG_PS}, {
+        atom_op_shr, ATOM_ARG_WS}, {
+        atom_op_shr, ATOM_ARG_FB}, {
+        atom_op_shr, ATOM_ARG_PLL}, {
+        atom_op_shr, ATOM_ARG_MC}, {
+        atom_op_mul, ATOM_ARG_REG}, {
+        atom_op_mul, ATOM_ARG_PS}, {
+        atom_op_mul, ATOM_ARG_WS}, {
+        atom_op_mul, ATOM_ARG_FB}, {
+        atom_op_mul, ATOM_ARG_PLL}, {
+        atom_op_mul, ATOM_ARG_MC}, {
+        atom_op_div, ATOM_ARG_REG}, {
+        atom_op_div, ATOM_ARG_PS}, {
+        atom_op_div, ATOM_ARG_WS}, {
+        atom_op_div, ATOM_ARG_FB}, {
+        atom_op_div, ATOM_ARG_PLL}, {
+        atom_op_div, ATOM_ARG_MC}, {
+        atom_op_add, ATOM_ARG_REG}, {
+        atom_op_add, ATOM_ARG_PS}, {
+        atom_op_add, ATOM_ARG_WS}, {
+        atom_op_add, ATOM_ARG_FB}, {
+        atom_op_add, ATOM_ARG_PLL}, {
+        atom_op_add, ATOM_ARG_MC}, {
+        atom_op_sub, ATOM_ARG_REG}, {
+        atom_op_sub, ATOM_ARG_PS}, {
+        atom_op_sub, ATOM_ARG_WS}, {
+        atom_op_sub, ATOM_ARG_FB}, {
+        atom_op_sub, ATOM_ARG_PLL}, {
+        atom_op_sub, ATOM_ARG_MC}, {
+        atom_op_setport, ATOM_PORT_ATI}, {
+        atom_op_setport, ATOM_PORT_PCI}, {
+        atom_op_setport, ATOM_PORT_SYSIO}, {
+        atom_op_setregblock, 0}, {
+        atom_op_setfbbase, 0}, {
+        atom_op_compare, ATOM_ARG_REG}, {
+        atom_op_compare, ATOM_ARG_PS}, {
+        atom_op_compare, ATOM_ARG_WS}, {
+        atom_op_compare, ATOM_ARG_FB}, {
+        atom_op_compare, ATOM_ARG_PLL}, {
+        atom_op_compare, ATOM_ARG_MC}, {
+        atom_op_switch, 0}, {
+        atom_op_jump, ATOM_COND_ALWAYS}, {
+        atom_op_jump, ATOM_COND_EQUAL}, {
+        atom_op_jump, ATOM_COND_BELOW}, {
+        atom_op_jump, ATOM_COND_ABOVE}, {
+        atom_op_jump, ATOM_COND_BELOWOREQUAL}, {
+        atom_op_jump, ATOM_COND_ABOVEOREQUAL}, {
+        atom_op_jump, ATOM_COND_NOTEQUAL}, {
+        atom_op_test, ATOM_ARG_REG}, {
+        atom_op_test, ATOM_ARG_PS}, {
+        atom_op_test, ATOM_ARG_WS}, {
+        atom_op_test, ATOM_ARG_FB}, {
+        atom_op_test, ATOM_ARG_PLL}, {
+        atom_op_test, ATOM_ARG_MC}, {
+        atom_op_delay, ATOM_UNIT_MILLISEC}, {
+        atom_op_delay, ATOM_UNIT_MICROSEC}, {
+        atom_op_calltable, 0}, {
+        atom_op_repeat, 0}, {
+        atom_op_clear, ATOM_ARG_REG}, {
+        atom_op_clear, ATOM_ARG_PS}, {
+        atom_op_clear, ATOM_ARG_WS}, {
+        atom_op_clear, ATOM_ARG_FB}, {
+        atom_op_clear, ATOM_ARG_PLL}, {
+        atom_op_clear, ATOM_ARG_MC}, {
+        atom_op_nop, 0}, {
+        atom_op_eot, 0}, {
+        atom_op_mask, ATOM_ARG_REG}, {
+        atom_op_mask, ATOM_ARG_PS}, {
+        atom_op_mask, ATOM_ARG_WS}, {
+        atom_op_mask, ATOM_ARG_FB}, {
+        atom_op_mask, ATOM_ARG_PLL}, {
+        atom_op_mask, ATOM_ARG_MC}, {
+        atom_op_postcard, 0}, {
+        atom_op_beep, 0}, {
+        atom_op_savereg, 0}, {
+        atom_op_restorereg, 0}, {
+        atom_op_setdatablock, 0}, {
+        atom_op_xor, ATOM_ARG_REG}, {
+        atom_op_xor, ATOM_ARG_PS}, {
+        atom_op_xor, ATOM_ARG_WS}, {
+        atom_op_xor, ATOM_ARG_FB}, {
+        atom_op_xor, ATOM_ARG_PLL}, {
+        atom_op_xor, ATOM_ARG_MC}, {
+        atom_op_shl, ATOM_ARG_REG}, {
+        atom_op_shl, ATOM_ARG_PS}, {
+        atom_op_shl, ATOM_ARG_WS}, {
+        atom_op_shl, ATOM_ARG_FB}, {
+        atom_op_shl, ATOM_ARG_PLL}, {
+        atom_op_shl, ATOM_ARG_MC}, {
+        atom_op_shr, ATOM_ARG_REG}, {
+        atom_op_shr, ATOM_ARG_PS}, {
+        atom_op_shr, ATOM_ARG_WS}, {
+        atom_op_shr, ATOM_ARG_FB}, {
+        atom_op_shr, ATOM_ARG_PLL}, {
+        atom_op_shr, ATOM_ARG_MC}, {
+atom_op_debug, 0},};
+
+void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
+{
+        int base = CU16(ctx->cmd_table + 4 + 2 * index);
+        int len, ws, ps, ptr;
+        unsigned char op;
+        atom_exec_context ectx;
+
+        if (!base)
+                return;
+
+        len = CU16(base + ATOM_CT_SIZE_PTR);
+        ws = CU8(base + ATOM_CT_WS_PTR);
+        ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
+        ptr = base + ATOM_CT_CODE_PTR;
+
+        SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
+
+        /* reset reg block */
+        ctx->reg_block = 0;
+        ectx.ctx = ctx;
+        ectx.ps_shift = ps / 4;
+        ectx.start = base;
+        ectx.ps = params;
+        if (ws)
+                ectx.ws = kzalloc(4 * ws, GFP_KERNEL);
+        else
+                ectx.ws = NULL;
+
+        debug_depth++;
+        while (1) {
+                op = CU8(ptr++);
+                if (op < ATOM_OP_NAMES_CNT)
+                        SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
+                else
+                        SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1);
+
+                if (op < ATOM_OP_CNT && op > 0)
+                        opcode_table[op].func(&ectx, &ptr,
+                                              opcode_table[op].arg);
+                else
+                        break;
+
+                if (op == ATOM_OP_EOT)
+                        break;
+        }
+        debug_depth--;
+        SDEBUG("<<\n");
+
+        if (ws)
+                kfree(ectx.ws);
+}
+
+static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
+
+static void atom_index_iio(struct atom_context *ctx, int base)
+{
+        ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
+        while (CU8(base) == ATOM_IIO_START) {
+                ctx->iio[CU8(base + 1)] = base + 2;
+                base += 2;
+                while (CU8(base) != ATOM_IIO_END)
+                        base += atom_iio_len[CU8(base)];
+                base += 3;
+        }
+}
+
+struct atom_context *atom_parse(struct card_info *card, void *bios)
+{
+        int base;
+        struct atom_context *ctx =
+            kzalloc(sizeof(struct atom_context), GFP_KERNEL);
+        char *str;
+        char name[512];
+        int i;
+
+        ctx->card = card;
+        ctx->bios = bios;
+
+        if (CU16(0) != ATOM_BIOS_MAGIC) {
+                printk(KERN_INFO "Invalid BIOS magic.\n");
+                kfree(ctx);
+                return NULL;
+        }
+        if (strncmp
+            (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC,
+             strlen(ATOM_ATI_MAGIC))) {
+                printk(KERN_INFO "Invalid ATI magic.\n");
+                kfree(ctx);
+                return NULL;
+        }
+
+        base = CU16(ATOM_ROM_TABLE_PTR);
+        if (strncmp
+            (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
+             strlen(ATOM_ROM_MAGIC))) {
+                printk(KERN_INFO "Invalid ATOM magic.\n");
+                kfree(ctx);
+                return NULL;
+        }
+
+        ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
+        ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
+        atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4);
+
+        str = CSTR(CU16(base + ATOM_ROM_MSG_PTR));
+        while (*str && ((*str == '\n') || (*str == '\r')))
+                str++;
+        /* name string isn't always 0 terminated */
+        for (i = 0; i < 511; i++) {
+                name[i] = str[i];
+                if (name[i] < '.' || name[i] > 'z') {
+                        name[i] = 0;
+                        break;
+                }
+        }
+        printk(KERN_INFO "ATOM BIOS: %s\n", name);
+
+        return ctx;
+}
+
+int atom_asic_init(struct atom_context *ctx)
+{
+        int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR);
+        uint32_t ps[16];
+        memset(ps, 0, 64);
+
+        ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR));
+        ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR));
+        if (!ps[0] || !ps[1])
+                return 1;
+
+        if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
+                return 1;
+        atom_execute_table(ctx, ATOM_CMD_INIT, ps);
+
+        return 0;
+}
+
+void atom_destroy(struct atom_context *ctx)
+{
+        if (ctx->iio)
+                kfree(ctx->iio);
+        kfree(ctx);
+}
+
+void atom_parse_data_header(struct atom_context *ctx, int index,
+                            uint16_t * size, uint8_t * frev, uint8_t * crev,
+                            uint16_t * data_start)
+{
+        int offset = index * 2 + 4;
+        int idx = CU16(ctx->data_table + offset);
+
+        if (size)
+                *size = CU16(idx);
+        if (frev)
+                *frev = CU8(idx + 2);
+        if (crev)
+                *crev = CU8(idx + 3);
+        *data_start = idx;
+        return;
+}
+
+void atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev,
+                           uint8_t * crev)
+{
+        int offset = index * 2 + 4;
+        int idx = CU16(ctx->cmd_table + offset);
+
+        if (frev)
+                *frev = CU8(idx + 2);
+        if (crev)
+                *crev = CU8(idx + 3);
+        return;
+}
diff --git a/drivers/gpu/drm/radeon/atom.h b/drivers/gpu/drm/radeon/atom.h
new file mode 100644
index 000000000000..e6eb38f2bcae
--- /dev/null
+++ b/drivers/gpu/drm/radeon/atom.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Stanislaw Skowronek
+ */
+
+#ifndef ATOM_H
+#define ATOM_H
+
+#include <linux/types.h>
+#include "drmP.h"
+
+#define ATOM_BIOS_MAGIC         0xAA55
+#define ATOM_ATI_MAGIC_PTR      0x30
+#define ATOM_ATI_MAGIC          " 761295520"
+#define ATOM_ROM_TABLE_PTR      0x48
+
+#define ATOM_ROM_MAGIC          "ATOM"
+#define ATOM_ROM_MAGIC_PTR      4
+
+#define ATOM_ROM_MSG_PTR        0x10
+#define ATOM_ROM_CMD_PTR        0x1E
+#define ATOM_ROM_DATA_PTR       0x20
+
+#define ATOM_CMD_INIT           0
+#define ATOM_CMD_SETSCLK        0x0A
+#define ATOM_CMD_SETMCLK        0x0B
+#define ATOM_CMD_SETPCLK        0x0C
+
+#define ATOM_DATA_FWI_PTR       0xC
+#define ATOM_DATA_IIO_PTR       0x32
+
+#define ATOM_FWI_DEFSCLK_PTR    8
+#define ATOM_FWI_DEFMCLK_PTR    0xC
+#define ATOM_FWI_MAXSCLK_PTR    0x24
+#define ATOM_FWI_MAXMCLK_PTR    0x28
+
+#define ATOM_CT_SIZE_PTR        0
+#define ATOM_CT_WS_PTR          4
+#define ATOM_CT_PS_PTR          5
+#define ATOM_CT_PS_MASK         0x7F
+#define ATOM_CT_CODE_PTR        6
+
+#define ATOM_OP_CNT             123
+#define ATOM_OP_EOT             91
+
+#define ATOM_CASE_MAGIC         0x63
+#define ATOM_CASE_END           0x5A5A
+
+#define ATOM_ARG_REG            0
+#define ATOM_ARG_PS             1
+#define ATOM_ARG_WS             2
+#define ATOM_ARG_FB             3
+#define ATOM_ARG_ID             4
+#define ATOM_ARG_IMM            5
+#define ATOM_ARG_PLL            6
+#define ATOM_ARG_MC             7
+
+#define ATOM_SRC_DWORD          0
+#define ATOM_SRC_WORD0          1
+#define ATOM_SRC_WORD8          2
+#define ATOM_SRC_WORD16         3
+#define ATOM_SRC_BYTE0          4
+#define ATOM_SRC_BYTE8          5
+#define ATOM_SRC_BYTE16         6
+#define ATOM_SRC_BYTE24         7
+
+#define ATOM_WS_QUOTIENT        0x40
+#define ATOM_WS_REMAINDER       0x41
+#define ATOM_WS_DATAPTR         0x42
+#define ATOM_WS_SHIFT           0x43
+#define ATOM_WS_OR_MASK         0x44
+#define ATOM_WS_AND_MASK        0x45
+#define ATOM_WS_FB_WINDOW       0x46
+#define ATOM_WS_ATTRIBUTES      0x47
+
+#define ATOM_IIO_NOP            0
+#define ATOM_IIO_START          1
+#define ATOM_IIO_READ           2
+#define ATOM_IIO_WRITE          3
+#define ATOM_IIO_CLEAR          4
+#define ATOM_IIO_SET            5
+#define ATOM_IIO_MOVE_INDEX     6
+#define ATOM_IIO_MOVE_ATTR      7
+#define ATOM_IIO_MOVE_DATA      8
+#define ATOM_IIO_END            9
+
+#define ATOM_IO_MM              0
+#define ATOM_IO_PCI             1
+#define ATOM_IO_SYSIO           2
+#define ATOM_IO_IIO             0x80
+
+struct card_info {
+        struct drm_device *dev;
+        void (* reg_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
+        uint32_t (* reg_read)(struct card_info *, uint32_t);          /*  filled by driver */
+        void (* mc_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
+        uint32_t (* mc_read)(struct card_info *, uint32_t);          /*  filled by driver */
+        void (* pll_write)(struct card_info *, uint32_t, uint32_t);   /*  filled by driver */
+        uint32_t (* pll_read)(struct card_info *, uint32_t);          /*  filled by driver */
+};
+
+struct atom_context {
+        struct card_info *card;
+        void *bios;
+        uint32_t cmd_table, data_table;
+        uint16_t *iio;
+
+        uint16_t data_block;
+        uint32_t fb_base;
+        uint32_t divmul[2];
+        uint16_t io_attr;
+        uint16_t reg_block;
+        uint8_t shift;
+        int cs_equal, cs_above;
+        int io_mode;
+};
+
+extern int atom_debug;
+
+struct atom_context *atom_parse(struct card_info *, void *);
+void atom_execute_table(struct atom_context *, int, uint32_t *);
+int atom_asic_init(struct atom_context *);
+void atom_destroy(struct atom_context *);
+void atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size, uint8_t *frev, uint8_t *crev, uint16_t *data_start);
+void atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev, uint8_t *crev);
+#include "atom-types.h"
+#include "atombios.h"
+#include "ObjectID.h"
+
+#endif
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
new file mode 100644
index 000000000000..cf67928abbc8
--- /dev/null
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -0,0 +1,4785 @@
+/*
+ * Copyright 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/****************************************************************************/
+/*Portion I: Definitions  shared between VBIOS and Driver                   */
+/****************************************************************************/
+
+#ifndef _ATOMBIOS_H
+#define _ATOMBIOS_H
+
+#define ATOM_VERSION_MAJOR                   0x00020000
+#define ATOM_VERSION_MINOR                   0x00000002
+
+#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
+
+/* Endianness should be specified before inclusion,
+ * default to little endian
+ */
+#ifndef ATOM_BIG_ENDIAN
+#error Endian not specified
+#endif
+
+#ifdef _H2INC
+#ifndef ULONG
+typedef unsigned long ULONG;
+#endif
+
+#ifndef UCHAR
+typedef unsigned char UCHAR;
+#endif
+
+#ifndef USHORT
+typedef unsigned short USHORT;
+#endif
+#endif
+
+#define ATOM_DAC_A            0
+#define ATOM_DAC_B            1
+#define ATOM_EXT_DAC          2
+
+#define ATOM_CRTC1            0
+#define ATOM_CRTC2            1
+
+#define ATOM_DIGA             0
+#define ATOM_DIGB             1
+
+#define ATOM_PPLL1            0
+#define ATOM_PPLL2            1
+
+#define ATOM_SCALER1          0
+#define ATOM_SCALER2          1
+
+#define ATOM_SCALER_DISABLE   0
+#define ATOM_SCALER_CENTER    1
+#define ATOM_SCALER_EXPANSION 2
+#define ATOM_SCALER_MULTI_EX  3
+
+#define ATOM_DISABLE          0
+#define ATOM_ENABLE           1
+#define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)
+#define ATOM_LCD_BLON                           (ATOM_ENABLE+2)
+#define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)
+#define ATOM_LCD_SELFTEST_START                                                                 (ATOM_DISABLE+5)
+#define ATOM_LCD_SELFTEST_STOP                                                                  (ATOM_ENABLE+5)
+#define ATOM_ENCODER_INIT                                         (ATOM_DISABLE+7)
+
+#define ATOM_BLANKING         1
+#define ATOM_BLANKING_OFF     0
+
+#define ATOM_CURSOR1          0
+#define ATOM_CURSOR2          1
+
+#define ATOM_ICON1            0
+#define ATOM_ICON2            1
+
+#define ATOM_CRT1             0
+#define ATOM_CRT2             1
+
+#define ATOM_TV_NTSC          1
+#define ATOM_TV_NTSCJ         2
+#define ATOM_TV_PAL           3
+#define ATOM_TV_PALM          4
+#define ATOM_TV_PALCN         5
+#define ATOM_TV_PALN          6
+#define ATOM_TV_PAL60         7
+#define ATOM_TV_SECAM         8
+#define ATOM_TV_CV            16
+
+#define ATOM_DAC1_PS2         1
+#define ATOM_DAC1_CV          2
+#define ATOM_DAC1_NTSC        3
+#define ATOM_DAC1_PAL         4
+
+#define ATOM_DAC2_PS2         ATOM_DAC1_PS2
+#define ATOM_DAC2_CV          ATOM_DAC1_CV
+#define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC
+#define ATOM_DAC2_PAL         ATOM_DAC1_PAL
+
+#define ATOM_PM_ON            0
+#define ATOM_PM_STANDBY       1
+#define ATOM_PM_SUSPEND       2
+#define ATOM_PM_OFF           3
+
+/* Bit0:{=0:single, =1:dual},
+   Bit1 {=0:666RGB, =1:888RGB},
+   Bit2:3:{Grey level}
+   Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
+
+#define ATOM_PANEL_MISC_DUAL               0x00000001
+#define ATOM_PANEL_MISC_888RGB             0x00000002
+#define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C
+#define ATOM_PANEL_MISC_FPDI               0x00000010
+#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
+#define ATOM_PANEL_MISC_SPATIAL            0x00000020
+#define ATOM_PANEL_MISC_TEMPORAL           0x00000040
+#define ATOM_PANEL_MISC_API_ENABLED        0x00000080
+
+#define MEMTYPE_DDR1              "DDR1"
+#define MEMTYPE_DDR2              "DDR2"
+#define MEMTYPE_DDR3              "DDR3"
+#define MEMTYPE_DDR4              "DDR4"
+
+#define ASIC_BUS_TYPE_PCI         "PCI"
+#define ASIC_BUS_TYPE_AGP         "AGP"
+#define ASIC_BUS_TYPE_PCIE        "PCI_EXPRESS"
+
+/* Maximum size of that FireGL flag string */
+
+#define ATOM_FIREGL_FLAG_STRING     "FGL"       /* Flag used to enable FireGL Support */
+#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING  3  /* sizeof( ATOM_FIREGL_FLAG_STRING ) */
+
+#define ATOM_FAKE_DESKTOP_STRING    "DSK"       /* Flag used to enable mobile ASIC on Desktop */
+#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING  ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
+
+#define ATOM_M54T_FLAG_STRING       "M54T"      /* Flag used to enable M54T Support */
+#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING    4  /* sizeof( ATOM_M54T_FLAG_STRING ) */
+
+#define HW_ASSISTED_I2C_STATUS_FAILURE          2
+#define HW_ASSISTED_I2C_STATUS_SUCCESS          1
+
+#pragma pack(1)                 /* BIOS data must use byte aligment */
+
+/*  Define offset to location of ROM header. */
+
+#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER            0x00000048L
+#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE                               0x00000002L
+
+#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE    0x94
+#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE   20      /* including the terminator 0x0! */
+#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER           0x002f
+#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START            0x006e
+
+/* Common header for all ROM Data tables.
+  Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header.
+  And the pointer actually points to this header. */
+
+typedef struct _ATOM_COMMON_TABLE_HEADER {
+        USHORT usStructureSize;
+        UCHAR ucTableFormatRevision;    /*Change it when the Parser is not backward compatible */
+        UCHAR ucTableContentRevision;   /*Change it only when the table needs to change but the firmware */
+        /*Image can't be updated, while Driver needs to carry the new table! */
+} ATOM_COMMON_TABLE_HEADER;
+
+typedef struct _ATOM_ROM_HEADER {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        UCHAR uaFirmWareSignature[4];   /*Signature to distinguish between Atombios and non-atombios,
+                                           atombios should init it as "ATOM", don't change the position */
+        USHORT usBiosRuntimeSegmentAddress;
+        USHORT usProtectedModeInfoOffset;
+        USHORT usConfigFilenameOffset;
+        USHORT usCRC_BlockOffset;
+        USHORT usBIOS_BootupMessageOffset;
+        USHORT usInt10Offset;
+        USHORT usPciBusDevInitCode;
+        USHORT usIoBaseAddress;
+        USHORT usSubsystemVendorID;
+        USHORT usSubsystemID;
+        USHORT usPCI_InfoOffset;
+        USHORT usMasterCommandTableOffset;      /*Offset for SW to get all command table offsets, Don't change the position */
+        USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */
+        UCHAR ucExtendedFunctionCode;
+        UCHAR ucReserved;
+} ATOM_ROM_HEADER;
+
+/*==============================Command Table Portion==================================== */
+
+#ifdef  UEFI_BUILD
+#define UTEMP   USHORT
+#define USHORT  void*
+#endif
+
+typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES {
+        USHORT ASIC_Init;       /* Function Table, used by various SW components,latest version 1.1 */
+        USHORT GetDisplaySurfaceSize;   /* Atomic Table,  Used by Bios when enabling HW ICON */
+        USHORT ASIC_RegistersInit;      /* Atomic Table,  indirectly used by various SW components,called from ASIC_Init */
+        USHORT VRAM_BlockVenderDetection;       /* Atomic Table,  used only by Bios */
+        USHORT DIGxEncoderControl;      /* Only used by Bios */
+        USHORT MemoryControllerInit;    /* Atomic Table,  indirectly used by various SW components,called from ASIC_Init */
+        USHORT EnableCRTCMemReq;        /* Function Table,directly used by various SW components,latest version 2.1 */
+        USHORT MemoryParamAdjust;       /* Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed */
+        USHORT DVOEncoderControl;       /* Function Table,directly used by various SW components,latest version 1.2 */
+        USHORT GPIOPinControl;  /* Atomic Table,  only used by Bios */
+        USHORT SetEngineClock;  /*Function Table,directly used by various SW components,latest version 1.1 */
+        USHORT SetMemoryClock;  /* Function Table,directly used by various SW components,latest version 1.1 */
+        USHORT SetPixelClock;   /*Function Table,directly used by various SW components,latest version 1.2 */
+        USHORT DynamicClockGating;      /* Atomic Table,  indirectly used by various SW components,called from ASIC_Init */
+        USHORT ResetMemoryDLL;  /* Atomic Table,  indirectly used by various SW components,called from SetMemoryClock */
+        USHORT ResetMemoryDevice;       /* Atomic Table,  indirectly used by various SW components,called from SetMemoryClock */
+        USHORT MemoryPLLInit;
+        USHORT AdjustDisplayPll;        /* only used by Bios */
+        USHORT AdjustMemoryController;  /* Atomic Table,  indirectly used by various SW components,called from SetMemoryClock */
+        USHORT EnableASIC_StaticPwrMgt; /* Atomic Table,  only used by Bios */
+        USHORT ASIC_StaticPwrMgtStatusChange;   /* Obsolete, only used by Bios */
+        USHORT DAC_LoadDetection;       /* Atomic Table,  directly used by various SW components,latest version 1.2 */
+        USHORT LVTMAEncoderControl;     /* Atomic Table,directly used by various SW components,latest version 1.3 */
+        USHORT LCD1OutputControl;       /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT DAC1EncoderControl;      /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT DAC2EncoderControl;      /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT DVOOutputControl;        /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT CV1OutputControl;        /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT GetConditionalGoldenSetting;     /* only used by Bios */
+        USHORT TVEncoderControl;        /* Function Table,directly used by various SW components,latest version 1.1 */
+        USHORT TMDSAEncoderControl;     /* Atomic Table,  directly used by various SW components,latest version 1.3 */
+        USHORT LVDSEncoderControl;      /* Atomic Table,  directly used by various SW components,latest version 1.3 */
+        USHORT TV1OutputControl;        /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT EnableScaler;    /* Atomic Table,  used only by Bios */
+        USHORT BlankCRTC;       /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT EnableCRTC;      /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT GetPixelClock;   /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT EnableVGA_Render;        /* Function Table,directly used by various SW components,latest version 1.1 */
+        USHORT EnableVGA_Access;        /* Obsolete ,     only used by Bios */
+        USHORT SetCRTC_Timing;  /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT SetCRTC_OverScan;        /* Atomic Table,  used by various SW components,latest version 1.1 */
+        USHORT SetCRTC_Replication;     /* Atomic Table,  used only by Bios */
+        USHORT SelectCRTC_Source;       /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT EnableGraphSurfaces;     /* Atomic Table,  used only by Bios */
+        USHORT UpdateCRTC_DoubleBufferRegisters;
+        USHORT LUT_AutoFill;    /* Atomic Table,  only used by Bios */
+        USHORT EnableHW_IconCursor;     /* Atomic Table,  only used by Bios */
+        USHORT GetMemoryClock;  /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT GetEngineClock;  /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT SetCRTC_UsingDTDTiming;  /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT ExternalEncoderControl;  /* Atomic Table,  directly used by various SW components,latest version 2.1 */
+        USHORT LVTMAOutputControl;      /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT VRAM_BlockDetectionByStrap;      /* Atomic Table,  used only by Bios */
+        USHORT MemoryCleanUp;   /* Atomic Table,  only used by Bios */
+        USHORT ProcessI2cChannelTransaction;    /* Function Table,only used by Bios */
+        USHORT WriteOneByteToHWAssistedI2C;     /* Function Table,indirectly used by various SW components */
+        USHORT ReadHWAssistedI2CStatus; /* Atomic Table,  indirectly used by various SW components */
+        USHORT SpeedFanControl; /* Function Table,indirectly used by various SW components,called from ASIC_Init */
+        USHORT PowerConnectorDetection; /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT MC_Synchronization;      /* Atomic Table,  indirectly used by various SW components,called from SetMemoryClock */
+        USHORT ComputeMemoryEnginePLL;  /* Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock */
+        USHORT MemoryRefreshConversion; /* Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock */
+        USHORT VRAM_GetCurrentInfoBlock;        /* Atomic Table,  used only by Bios */
+        USHORT DynamicMemorySettings;   /* Atomic Table,  indirectly used by various SW components,called from SetMemoryClock */
+        USHORT MemoryTraining;  /* Atomic Table,  used only by Bios */
+        USHORT EnableSpreadSpectrumOnPPLL;      /* Atomic Table,  directly used by various SW components,latest version 1.2 */
+        USHORT TMDSAOutputControl;      /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT SetVoltage;      /* Function Table,directly and/or indirectly used by various SW components,latest version 1.1 */
+        USHORT DAC1OutputControl;       /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT DAC2OutputControl;       /* Atomic Table,  directly used by various SW components,latest version 1.1 */
+        USHORT SetupHWAssistedI2CStatus;        /* Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" */
+        USHORT ClockSource;     /* Atomic Table,  indirectly used by various SW components,called from ASIC_Init */
+        USHORT MemoryDeviceInit;        /* Atomic Table,  indirectly used by various SW components,called from SetMemoryClock */
+        USHORT EnableYUV;       /* Atomic Table,  indirectly used by various SW components,called from EnableVGARender */
+        USHORT DIG1EncoderControl;      /* Atomic Table,directly used by various SW components,latest version 1.1 */
+        USHORT DIG2EncoderControl;      /* Atomic Table,directly used by various SW components,latest version 1.1 */
+        USHORT DIG1TransmitterControl;  /* Atomic Table,directly used by various SW components,latest version 1.1 */
+        USHORT DIG2TransmitterControl;  /* Atomic Table,directly used by various SW components,latest version 1.1 */
+        USHORT ProcessAuxChannelTransaction;    /* Function Table,only used by Bios */
+        USHORT DPEncoderService;        /* Function Table,only used by Bios */
+} ATOM_MASTER_LIST_OF_COMMAND_TABLES;
+
+/*  For backward compatible */
+#define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
+#define UNIPHYTransmitterControl                                                     DIG1TransmitterControl
+#define LVTMATransmitterControl                                                      DIG2TransmitterControl
+#define SetCRTC_DPM_State                        GetConditionalGoldenSetting
+#define SetUniphyInstance                        ASIC_StaticPwrMgtStatusChange
+
+typedef struct _ATOM_MASTER_COMMAND_TABLE {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
+} ATOM_MASTER_COMMAND_TABLE;
+
+/****************************************************************************/
+/*  Structures used in every command table */
+/****************************************************************************/
+typedef struct _ATOM_TABLE_ATTRIBUTE {
+#if ATOM_BIG_ENDIAN
+        USHORT UpdatedByUtility:1;      /* [15]=Table updated by utility flag */
+        USHORT PS_SizeInBytes:7;        /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */
+        USHORT WS_SizeInBytes:8;        /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */
+#else
+        USHORT WS_SizeInBytes:8;        /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */
+        USHORT PS_SizeInBytes:7;        /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */
+        USHORT UpdatedByUtility:1;      /* [15]=Table updated by utility flag */
+#endif
+} ATOM_TABLE_ATTRIBUTE;
+
+typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS {
+        ATOM_TABLE_ATTRIBUTE sbfAccess;
+        USHORT susAccess;
+} ATOM_TABLE_ATTRIBUTE_ACCESS;
+
+/****************************************************************************/
+/*  Common header for all command tables. */
+/*  Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. */
+/*  And the pointer actually points to this header. */
+/****************************************************************************/
+typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER {
+        ATOM_COMMON_TABLE_HEADER CommonHeader;
+        ATOM_TABLE_ATTRIBUTE TableAttribute;
+} ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
+
+/****************************************************************************/
+/*  Structures used by ComputeMemoryEnginePLLTable */
+/****************************************************************************/
+#define COMPUTE_MEMORY_PLL_PARAM        1
+#define COMPUTE_ENGINE_PLL_PARAM        2
+
+typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS {
+        ULONG ulClock;          /* When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div */
+        UCHAR ucAction;         /* 0:reserved //1:Memory //2:Engine */
+        UCHAR ucReserved;       /* may expand to return larger Fbdiv later */
+        UCHAR ucFbDiv;          /* return value */
+        UCHAR ucPostDiv;        /* return value */
+} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
+
+typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 {
+        ULONG ulClock;          /* When return, [23:0] return real clock */
+        UCHAR ucAction;         /* 0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register */
+        USHORT usFbDiv;         /* return Feedback value to be written to register */
+        UCHAR ucPostDiv;        /* return post div to be written to register */
+} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
+#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
+
+#define SET_CLOCK_FREQ_MASK                     0x00FFFFFF      /* Clock change tables only take bit [23:0] as the requested clock value */
+#define USE_NON_BUS_CLOCK_MASK                  0x01000000      /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */
+#define USE_MEMORY_SELF_REFRESH_MASK            0x02000000      /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */
+#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04000000      /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */
+#define FIRST_TIME_CHANGE_CLOCK                                                                 0x08000000      /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */
+#define SKIP_SW_PROGRAM_PLL                                                                                     0x10000000      /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */
+#define USE_SS_ENABLED_PIXEL_CLOCK  USE_NON_BUS_CLOCK_MASK
+
+#define b3USE_NON_BUS_CLOCK_MASK                  0x01  /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */
+#define b3USE_MEMORY_SELF_REFRESH                 0x02  /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */
+#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04  /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */
+#define b3FIRST_TIME_CHANGE_CLOCK                                                                       0x08    /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */
+#define b3SKIP_SW_PROGRAM_PLL                                                                                   0x10    /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */
+
+typedef struct _ATOM_COMPUTE_CLOCK_FREQ {
+#if ATOM_BIG_ENDIAN
+        ULONG ulComputeClockFlag:8;     /*  =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */
+        ULONG ulClockFreq:24;   /*  in unit of 10kHz */
+#else
+        ULONG ulClockFreq:24;   /*  in unit of 10kHz */
+        ULONG ulComputeClockFlag:8;     /*  =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */
+#endif
+} ATOM_COMPUTE_CLOCK_FREQ;
+
+typedef struct _ATOM_S_MPLL_FB_DIVIDER {
+        USHORT usFbDivFrac;
+        USHORT usFbDiv;
+} ATOM_S_MPLL_FB_DIVIDER;
+
+typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 {
+        union {
+                ATOM_COMPUTE_CLOCK_FREQ ulClock;        /* Input Parameter */
+                ATOM_S_MPLL_FB_DIVIDER ulFbDiv; /* Output Parameter */
+        };
+        UCHAR ucRefDiv;         /* Output Parameter */
+        UCHAR ucPostDiv;        /* Output Parameter */
+        UCHAR ucCntlFlag;       /* Output Parameter */
+        UCHAR ucReserved;
+} COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
+
+/*  ucCntlFlag */
+#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN          1
+#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE            2
+#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE         4
+
+typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER {
+        ATOM_COMPUTE_CLOCK_FREQ ulClock;
+        ULONG ulReserved[2];
+} DYNAMICE_MEMORY_SETTINGS_PARAMETER;
+
+typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER {
+        ATOM_COMPUTE_CLOCK_FREQ ulClock;
+        ULONG ulMemoryClock;
+        ULONG ulReserved;
+} DYNAMICE_ENGINE_SETTINGS_PARAMETER;
+
+/****************************************************************************/
+/*  Structures used by SetEngineClockTable */
+/****************************************************************************/
+typedef struct _SET_ENGINE_CLOCK_PARAMETERS {
+        ULONG ulTargetEngineClock;      /* In 10Khz unit */
+} SET_ENGINE_CLOCK_PARAMETERS;
+
+typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION {
+        ULONG ulTargetEngineClock;      /* In 10Khz unit */
+        COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
+} SET_ENGINE_CLOCK_PS_ALLOCATION;
+
+/****************************************************************************/
+/*  Structures used by SetMemoryClockTable */
+/****************************************************************************/
+typedef struct _SET_MEMORY_CLOCK_PARAMETERS {
+        ULONG ulTargetMemoryClock;      /* In 10Khz unit */
+} SET_MEMORY_CLOCK_PARAMETERS;
+
+typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION {
+        ULONG ulTargetMemoryClock;      /* In 10Khz unit */
+        COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
+} SET_MEMORY_CLOCK_PS_ALLOCATION;
+
+/****************************************************************************/
+/*  Structures used by ASIC_Init.ctb */
+/****************************************************************************/
+typedef struct _ASIC_INIT_PARAMETERS {
+        ULONG ulDefaultEngineClock;     /* In 10Khz unit */
+        ULONG ulDefaultMemoryClock;     /* In 10Khz unit */
+} ASIC_INIT_PARAMETERS;
+
+typedef struct _ASIC_INIT_PS_ALLOCATION {
+        ASIC_INIT_PARAMETERS sASICInitClocks;
+        SET_ENGINE_CLOCK_PS_ALLOCATION sReserved;       /* Caller doesn't need to init this structure */
+} ASIC_INIT_PS_ALLOCATION;
+
+/****************************************************************************/
+/*  Structure used by DynamicClockGatingTable.ctb */
+/****************************************************************************/
+typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS {
+        UCHAR ucEnable;         /*  ATOM_ENABLE or ATOM_DISABLE */
+        UCHAR ucPadding[3];
+} DYNAMIC_CLOCK_GATING_PARAMETERS;
+#define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS
+
+/****************************************************************************/
+/*  Structure used by EnableASIC_StaticPwrMgtTable.ctb */
+/****************************************************************************/
+typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS {
+        UCHAR ucEnable;         /*  ATOM_ENABLE or ATOM_DISABLE */
+        UCHAR ucPadding[3];
+} ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
+#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
+
+/****************************************************************************/
+/*  Structures used by DAC_LoadDetectionTable.ctb */
+/****************************************************************************/
+typedef struct _DAC_LOAD_DETECTION_PARAMETERS {
+        USHORT usDeviceID;      /* {ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} */
+        UCHAR ucDacType;        /* {ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} */
+        UCHAR ucMisc;           /* Valid only when table revision =1.3 and above */
+} DAC_LOAD_DETECTION_PARAMETERS;
+
+/*  DAC_LOAD_DETECTION_PARAMETERS.ucMisc */
+#define DAC_LOAD_MISC_YPrPb                                             0x01
+
+typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION {
+        DAC_LOAD_DETECTION_PARAMETERS sDacload;
+        ULONG Reserved[2];      /*  Don't set this one, allocation for EXT DAC */
+} DAC_LOAD_DETECTION_PS_ALLOCATION;
+
+/****************************************************************************/
+/*  Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb */
+/****************************************************************************/
+typedef struct _DAC_ENCODER_CONTROL_PARAMETERS {
+        USHORT usPixelClock;    /*  in 10KHz; for bios convenient */
+        UCHAR ucDacStandard;    /*  See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) */
+        UCHAR ucAction;         /*  0: turn off encoder */
+        /*  1: setup and turn on encoder */
+        /*  7: ATOM_ENCODER_INIT Initialize DAC */
+} DAC_ENCODER_CONTROL_PARAMETERS;
+
+#define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS
+
+/****************************************************************************/
+/*  Structures used by DIG1EncoderControlTable */
+/*                     DIG2EncoderControlTable */
+/*                     ExternalEncoderControlTable */
+/****************************************************************************/
+typedef struct _DIG_ENCODER_CONTROL_PARAMETERS {
+        USHORT usPixelClock;    /*  in 10KHz; for bios convenient */
+        UCHAR ucConfig;
+        /*  [2] Link Select: */
+        /*  =0: PHY linkA if bfLane<3 */
+        /*  =1: PHY linkB if bfLanes<3 */
+        /*  =0: PHY linkA+B if bfLanes=3 */
+        /*  [3] Transmitter Sel */
+        /*  =0: UNIPHY or PCIEPHY */
+        /*  =1: LVTMA */
+        UCHAR ucAction;         /*  =0: turn off encoder */
+        /*  =1: turn on encoder */
+        UCHAR ucEncoderMode;
+        /*  =0: DP   encoder */
+        /*  =1: LVDS encoder */
+        /*  =2: DVI  encoder */
+        /*  =3: HDMI encoder */
+        /*  =4: SDVO encoder */
+        UCHAR ucLaneNum;        /*  how many lanes to enable */
+        UCHAR ucReserved[2];
+} DIG_ENCODER_CONTROL_PARAMETERS;
+#define DIG_ENCODER_CONTROL_PS_ALLOCATION                         DIG_ENCODER_CONTROL_PARAMETERS
+#define EXTERNAL_ENCODER_CONTROL_PARAMETER                      DIG_ENCODER_CONTROL_PARAMETERS
+
+/* ucConfig */
+#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK                             0x01
+#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ          0x00
+#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ          0x01
+#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK                                 0x04
+#define ATOM_ENCODER_CONFIG_LINKA                                                                 0x00
+#define ATOM_ENCODER_CONFIG_LINKB                                                                 0x04
+#define ATOM_ENCODER_CONFIG_LINKA_B                                                       ATOM_TRANSMITTER_CONFIG_LINKA
+#define ATOM_ENCODER_CONFIG_LINKB_A                                                       ATOM_ENCODER_CONFIG_LINKB
+#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK        0x08
+#define ATOM_ENCODER_CONFIG_UNIPHY                                                        0x00
+#define ATOM_ENCODER_CONFIG_LVTMA                                                                 0x08
+#define ATOM_ENCODER_CONFIG_TRANSMITTER1                                  0x00
+#define ATOM_ENCODER_CONFIG_TRANSMITTER2                                  0x08
+#define ATOM_ENCODER_CONFIG_DIGB                                                                  0x80  /*  VBIOS Internal use, outside SW should set this bit=0 */
+/*  ucAction */
+/*  ATOM_ENABLE:  Enable Encoder */
+/*  ATOM_DISABLE: Disable Encoder */
+
+/* ucEncoderMode */
+#define ATOM_ENCODER_MODE_DP                                                                                    0
+#define ATOM_ENCODER_MODE_LVDS                                                                          1
+#define ATOM_ENCODER_MODE_DVI                                                                                   2
+#define ATOM_ENCODER_MODE_HDMI                                                                          3
+#define ATOM_ENCODER_MODE_SDVO                                                                          4
+#define ATOM_ENCODER_MODE_TV                                                                                    13
+#define ATOM_ENCODER_MODE_CV                                                                                    14
+#define ATOM_ENCODER_MODE_CRT                                                                                   15
+
+typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 {
+#if ATOM_BIG_ENDIAN
+        UCHAR ucReserved1:2;
+        UCHAR ucTransmitterSel:2;       /*  =0: UniphyAB, =1: UniphyCD  =2: UniphyEF */
+        UCHAR ucLinkSel:1;      /*  =0: linkA/C/E =1: linkB/D/F */
+        UCHAR ucReserved:1;
+        UCHAR ucDPLinkRate:1;   /*  =0: 1.62Ghz, =1: 2.7Ghz */
+#else
+        UCHAR ucDPLinkRate:1;   /*  =0: 1.62Ghz, =1: 2.7Ghz */
+        UCHAR ucReserved:1;
+        UCHAR ucLinkSel:1;      /*  =0: linkA/C/E =1: linkB/D/F */
+        UCHAR ucTransmitterSel:2;       /*  =0: UniphyAB, =1: UniphyCD  =2: UniphyEF */
+        UCHAR ucReserved1:2;
+#endif
+} ATOM_DIG_ENCODER_CONFIG_V2;
+
+typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 {
+        USHORT usPixelClock;    /*  in 10KHz; for bios convenient */
+        ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
+        UCHAR ucAction;
+        UCHAR ucEncoderMode;
+        /*  =0: DP   encoder */
+        /*  =1: LVDS encoder */
+        /*  =2: DVI  encoder */
+        /*  =3: HDMI encoder */
+        /*  =4: SDVO encoder */
+        UCHAR ucLaneNum;        /*  how many lanes to enable */
+        UCHAR ucReserved[2];
+} DIG_ENCODER_CONTROL_PARAMETERS_V2;
+
+/* ucConfig */
+#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK                          0x01
+#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ                 0x00
+#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ                 0x01
+#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK                              0x04
+#define ATOM_ENCODER_CONFIG_V2_LINKA                                                              0x00
+#define ATOM_ENCODER_CONFIG_V2_LINKB                                                              0x04
+#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK       0x18
+#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1                                 0x00
+#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2                                 0x08
+#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3                                 0x10
+
+/****************************************************************************/
+/*  Structures used by UNIPHYTransmitterControlTable */
+/*                     LVTMATransmitterControlTable */
+/*                     DVOOutputControlTable */
+/****************************************************************************/
+typedef struct _ATOM_DP_VS_MODE {
+        UCHAR ucLaneSel;
+        UCHAR ucLaneSet;
+} ATOM_DP_VS_MODE;
+
+typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS {
+        union {
+                USHORT usPixelClock;    /*  in 10KHz; for bios convenient */
+                USHORT usInitInfo;      /*  when init uniphy,lower 8bit is used for connector type defined in objectid.h */
+                ATOM_DP_VS_MODE asMode; /*  DP Voltage swing mode */
+        };
+        UCHAR ucConfig;
+        /*  [0]=0: 4 lane Link, */
+        /*     =1: 8 lane Link ( Dual Links TMDS ) */
+        /*  [1]=0: InCoherent mode */
+        /*     =1: Coherent Mode */
+        /*  [2] Link Select: */
+        /*  =0: PHY linkA   if bfLane<3 */
+        /*  =1: PHY linkB   if bfLanes<3 */
+        /*  =0: PHY linkA+B if bfLanes=3 */
+        /*  [5:4]PCIE lane Sel */
+        /*  =0: lane 0~3 or 0~7 */
+        /*  =1: lane 4~7 */
+        /*  =2: lane 8~11 or 8~15 */
+        /*  =3: lane 12~15 */
+        UCHAR ucAction;         /*  =0: turn off encoder */
+        /*  =1: turn on encoder */
+        UCHAR ucReserved[4];
+} DIG_TRANSMITTER_CONTROL_PARAMETERS;
+
+#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION           DIG_TRANSMITTER_CONTROL_PARAMETERS
+
+/* ucInitInfo */
+#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK  0x00ff
+
+/* ucConfig */
+#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK                      0x01
+#define ATOM_TRANSMITTER_CONFIG_COHERENT                                0x02
+#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK           0x04
+#define ATOM_TRANSMITTER_CONFIG_LINKA                                           0x00
+#define ATOM_TRANSMITTER_CONFIG_LINKB                                           0x04
+#define ATOM_TRANSMITTER_CONFIG_LINKA_B                                 0x00
+#define ATOM_TRANSMITTER_CONFIG_LINKB_A                                 0x04
+
+#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK        0x08    /*  only used when ATOM_TRANSMITTER_ACTION_ENABLE */
+#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER            0x00    /*  only used when ATOM_TRANSMITTER_ACTION_ENABLE */
+#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER            0x08    /*  only used when ATOM_TRANSMITTER_ACTION_ENABLE */
+
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK                     0x30
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL                     0x00
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE                     0x20
+#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN           0x30
+#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK           0xc0
+#define ATOM_TRANSMITTER_CONFIG_LANE_0_3                                0x00
+#define ATOM_TRANSMITTER_CONFIG_LANE_0_7                                0x00
+#define ATOM_TRANSMITTER_CONFIG_LANE_4_7                                0x40
+#define ATOM_TRANSMITTER_CONFIG_LANE_8_11                               0x80
+#define ATOM_TRANSMITTER_CONFIG_LANE_8_15                               0x80
+#define ATOM_TRANSMITTER_CONFIG_LANE_12_15                      0xc0
+
+/* ucAction */
+#define ATOM_TRANSMITTER_ACTION_DISABLE                                        0
+#define ATOM_TRANSMITTER_ACTION_ENABLE                                         1
+#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF                                      2
+#define ATOM_TRANSMITTER_ACTION_LCD_BLON                                       3
+#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4
+#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START               5
+#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP                        6
+#define ATOM_TRANSMITTER_ACTION_INIT                                                   7
+#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT         8
+#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT                  9
+#define ATOM_TRANSMITTER_ACTION_SETUP                                                  10
+#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11
+
+/*  Following are used for DigTransmitterControlTable ver1.2 */
+typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 {
+#if ATOM_BIG_ENDIAN
+        UCHAR ucTransmitterSel:2;       /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */
+        /*         =1 Dig Transmitter 2 ( Uniphy CD ) */
+        /*         =2 Dig Transmitter 3 ( Uniphy EF ) */
+        UCHAR ucReserved:1;
+        UCHAR fDPConnector:1;   /* bit4=0: DP connector  =1: None DP connector */
+        UCHAR ucEncoderSel:1;   /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */
+        UCHAR ucLinkSel:1;      /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */
+        /*     =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */
+
+        UCHAR fCoherentMode:1;  /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */
+        UCHAR fDualLinkConnector:1;     /* bit0=1: Dual Link DVI connector */
+#else
+        UCHAR fDualLinkConnector:1;     /* bit0=1: Dual Link DVI connector */
+        UCHAR fCoherentMode:1;  /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */
+        UCHAR ucLinkSel:1;      /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */
+        /*     =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */
+        UCHAR ucEncoderSel:1;   /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */
+        UCHAR fDPConnector:1;   /* bit4=0: DP connector  =1: None DP connector */
+        UCHAR ucReserved:1;
+        UCHAR ucTransmitterSel:2;       /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */
+        /*         =1 Dig Transmitter 2 ( Uniphy CD ) */
+        /*         =2 Dig Transmitter 3 ( Uniphy EF ) */
+#endif
+} ATOM_DIG_TRANSMITTER_CONFIG_V2;
+
+/* ucConfig */
+/* Bit0 */
+#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR                  0x01
+
+/* Bit1 */
+#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT                                       0x02
+
+/* Bit2 */
+#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK                        0x04
+#define ATOM_TRANSMITTER_CONFIG_V2_LINKA                                    0x00
+#define ATOM_TRANSMITTER_CONFIG_V2_LINKB                                            0x04
+
+/*  Bit3 */
+#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK             0x08
+#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER                   0x00  /*  only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */
+#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER                   0x08  /*  only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */
+
+/*  Bit4 */
+#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR                          0x10
+
+/*  Bit7:6 */
+#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK     0xC0
+#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1                 0x00    /* AB */
+#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2                 0x40    /* CD */
+#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3                 0x80    /* EF */
+
+typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 {
+        union {
+                USHORT usPixelClock;    /*  in 10KHz; for bios convenient */
+                USHORT usInitInfo;      /*  when init uniphy,lower 8bit is used for connector type defined in objectid.h */
+                ATOM_DP_VS_MODE asMode; /*  DP Voltage swing mode */
+        };
+        ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
+        UCHAR ucAction;         /*  define as ATOM_TRANSMITER_ACTION_XXX */
+        UCHAR ucReserved[4];
+} DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
+
+/****************************************************************************/
+/*  Structures used by DAC1OuputControlTable */
+/*                     DAC2OuputControlTable */
+/*                     LVTMAOutputControlTable  (Before DEC30) */
+/*                     TMDSAOutputControlTable  (Before DEC30) */
+/****************************************************************************/
+typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS {
+        UCHAR ucAction;         /*  Possible input:ATOM_ENABLE||ATOMDISABLE */
+        /*  When the display is LCD, in addition to above: */
+        /*  ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| */
+        /*  ATOM_LCD_SELFTEST_STOP */
+
+        UCHAR aucPadding[3];    /*  padding to DWORD aligned */
+} DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
+
+#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+
+#define CRT1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define CRT2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define CV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define TV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define DFP1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define DFP2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define LCD1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define DVO_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
+#define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
+#define DVO_OUTPUT_CONTROL_PARAMETERS_V3         DIG_TRANSMITTER_CONTROL_PARAMETERS
+
+/****************************************************************************/
+/*  Structures used by BlankCRTCTable */
+/****************************************************************************/
+typedef struct _BLANK_CRTC_PARAMETERS {
+        UCHAR ucCRTC;           /*  ATOM_CRTC1 or ATOM_CRTC2 */
+        UCHAR ucBlanking;       /*  ATOM_BLANKING or ATOM_BLANKINGOFF */
+        USHORT usBlackColorRCr;
+        USHORT usBlackColorGY;
+        USHORT usBlackColorBCb;
+} BLANK_CRTC_PARAMETERS;
+#define BLANK_CRTC_PS_ALLOCATION    BLANK_CRTC_PARAMETERS
+
+/****************************************************************************/
+/*  Structures used by EnableCRTCTable */
+/*                     EnableCRTCMemReqTable */
+/*                     UpdateCRTC_DoubleBufferRegistersTable */
+/****************************************************************************/
+typedef struct _ENABLE_CRTC_PARAMETERS {
+        UCHAR ucCRTC;           /*  ATOM_CRTC1 or ATOM_CRTC2 */
+        UCHAR ucEnable;         /*  ATOM_ENABLE or ATOM_DISABLE */
+        UCHAR ucPadding[2];
+} ENABLE_CRTC_PARAMETERS;
+#define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS
+
+/****************************************************************************/
+/*  Structures used by SetCRTC_OverScanTable */
+/****************************************************************************/
+typedef struct _SET_CRTC_OVERSCAN_PARAMETERS {
+        USHORT usOverscanRight; /*  right */
+        USHORT usOverscanLeft;  /*  left */
+        USHORT usOverscanBottom;        /*  bottom */
+        USHORT usOverscanTop;   /*  top */
+        UCHAR ucCRTC;           /*  ATOM_CRTC1 or ATOM_CRTC2 */
+        UCHAR ucPadding[3];
+} SET_CRTC_OVERSCAN_PARAMETERS;
+#define SET_CRTC_OVERSCAN_PS_ALLOCATION  SET_CRTC_OVERSCAN_PARAMETERS
+
+/****************************************************************************/
+/*  Structures used by SetCRTC_ReplicationTable */
+/****************************************************************************/
+typedef struct _SET_CRTC_REPLICATION_PARAMETERS {
+        UCHAR ucH_Replication;  /*  horizontal replication */
+        UCHAR ucV_Replication;  /*  vertical replication */
+        UCHAR usCRTC;           /*  ATOM_CRTC1 or ATOM_CRTC2 */
+        UCHAR ucPadding;
+} SET_CRTC_REPLICATION_PARAMETERS;
+#define SET_CRTC_REPLICATION_PS_ALLOCATION  SET_CRTC_REPLICATION_PARAMETERS
+
+/****************************************************************************/
+/*  Structures used by SelectCRTC_SourceTable */
+/****************************************************************************/
+typedef struct _SELECT_CRTC_SOURCE_PARAMETERS {
+        UCHAR ucCRTC;           /*  ATOM_CRTC1 or ATOM_CRTC2 */
+        UCHAR ucDevice;         /*  ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... */
+        UCHAR ucPadding[2];
+} SELECT_CRTC_SOURCE_PARAMETERS;
+#define SELECT_CRTC_SOURCE_PS_ALLOCATION  SELECT_CRTC_SOURCE_PARAMETERS
+
+typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 {
+        UCHAR ucCRTC;           /*  ATOM_CRTC1 or ATOM_CRTC2 */
+        UCHAR ucEncoderID;      /*  DAC1/DAC2/TVOUT/DIG1/DIG2/DVO */
+        UCHAR ucEncodeMode;     /*  Encoding mode, only valid when using DIG1/DIG2/DVO */
+        UCHAR ucPadding;
+} SELECT_CRTC_SOURCE_PARAMETERS_V2;
+
+/* ucEncoderID */
+/* #define ASIC_INT_DAC1_ENCODER_ID                                              0x00 */
+/* #define ASIC_INT_TV_ENCODER_ID                                                                        0x02 */
+/* #define ASIC_INT_DIG1_ENCODER_ID                                                              0x03 */
+/* #define ASIC_INT_DAC2_ENCODER_ID                                                              0x04 */
+/* #define ASIC_EXT_TV_ENCODER_ID                                                                        0x06 */
+/* #define ASIC_INT_DVO_ENCODER_ID                                                                       0x07 */
+/* #define ASIC_INT_DIG2_ENCODER_ID                                                              0x09 */
+/* #define ASIC_EXT_DIG_ENCODER_ID                                                                       0x05 */
+
+/* ucEncodeMode */
+/* #define ATOM_ENCODER_MODE_DP                                                                          0 */
+/* #define ATOM_ENCODER_MODE_LVDS                                                                        1 */
+/* #define ATOM_ENCODER_MODE_DVI                                                                         2 */
+/* #define ATOM_ENCODER_MODE_HDMI                                                                        3 */
+/* #define ATOM_ENCODER_MODE_SDVO                                                                        4 */
+/* #define ATOM_ENCODER_MODE_TV                                                                          13 */
+/* #define ATOM_ENCODER_MODE_CV                                                                          14 */
+/* #define ATOM_ENCODER_MODE_CRT                                                                         15 */
+
+/****************************************************************************/
+/*  Structures used by SetPixelClockTable */
+/*                     GetPixelClockTable */
+/****************************************************************************/
+/* Major revision=1., Minor revision=1 */
+typedef struct _PIXEL_CLOCK_PARAMETERS {
+        USHORT usPixelClock;    /*  in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */
+        /*  0 means disable PPLL */
+        USHORT usRefDiv;        /*  Reference divider */
+        USHORT usFbDiv;         /*  feedback divider */
+        UCHAR ucPostDiv;        /*  post divider */
+        UCHAR ucFracFbDiv;      /*  fractional feedback divider */
+        UCHAR ucPpll;           /*  ATOM_PPLL1 or ATOM_PPL2 */
+        UCHAR ucRefDivSrc;      /*  ATOM_PJITTER or ATO_NONPJITTER */
+        UCHAR ucCRTC;           /*  Which CRTC uses this Ppll */
+        UCHAR ucPadding;
+} PIXEL_CLOCK_PARAMETERS;
+
+/* Major revision=1., Minor revision=2, add ucMiscIfno */
+/* ucMiscInfo: */
+#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
+#define MISC_DEVICE_INDEX_MASK        0xF0
+#define MISC_DEVICE_INDEX_SHIFT       4
+
+typedef struct _PIXEL_CLOCK_PARAMETERS_V2 {
+        USHORT usPixelClock;    /*  in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */
+        /*  0 means disable PPLL */
+        USHORT usRefDiv;        /*  Reference divider */
+        USHORT usFbDiv;         /*  feedback divider */
+        UCHAR ucPostDiv;        /*  post divider */
+        UCHAR ucFracFbDiv;      /*  fractional feedback divider */
+        UCHAR ucPpll;           /*  ATOM_PPLL1 or ATOM_PPL2 */
+        UCHAR ucRefDivSrc;      /*  ATOM_PJITTER or ATO_NONPJITTER */
+        UCHAR ucCRTC;           /*  Which CRTC uses this Ppll */
+        UCHAR ucMiscInfo;       /*  Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog */
+} PIXEL_CLOCK_PARAMETERS_V2;
+
+/* Major revision=1., Minor revision=3, structure/definition change */
+/* ucEncoderMode: */
+/* ATOM_ENCODER_MODE_DP */
+/* ATOM_ENOCDER_MODE_LVDS */
+/* ATOM_ENOCDER_MODE_DVI */
+/* ATOM_ENOCDER_MODE_HDMI */
+/* ATOM_ENOCDER_MODE_SDVO */
+/* ATOM_ENCODER_MODE_TV                                                                          13 */
+/* ATOM_ENCODER_MODE_CV                                                                          14 */
+/* ATOM_ENCODER_MODE_CRT                                                                         15 */
+
+/* ucDVOConfig */
+/* #define DVO_ENCODER_CONFIG_RATE_SEL                                                   0x01 */
+/* #define DVO_ENCODER_CONFIG_DDR_SPEED                                          0x00 */
+/* #define DVO_ENCODER_CONFIG_SDR_SPEED                                          0x01 */
+/* #define DVO_ENCODER_CONFIG_OUTPUT_SEL                                         0x0c */
+/* #define DVO_ENCODER_CONFIG_LOW12BIT                                                   0x00 */
+/* #define DVO_ENCODER_CONFIG_UPPER12BIT                                         0x04 */
+/* #define DVO_ENCODER_CONFIG_24BIT                                                              0x08 */
+
+/* ucMiscInfo: also changed, see below */
+#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL                                                0x01
+#define PIXEL_CLOCK_MISC_VGA_MODE                                                                               0x02
+#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK                                                  0x04
+#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1                                                 0x00
+#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2                                                 0x04
+#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK                 0x08
+
+typedef struct _PIXEL_CLOCK_PARAMETERS_V3 {
+        USHORT usPixelClock;    /*  in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */
+        /*  0 means disable PPLL. For VGA PPLL,make sure this value is not 0. */
+        USHORT usRefDiv;        /*  Reference divider */
+        USHORT usFbDiv;         /*  feedback divider */
+        UCHAR ucPostDiv;        /*  post divider */
+        UCHAR ucFracFbDiv;      /*  fractional feedback divider */
+        UCHAR ucPpll;           /*  ATOM_PPLL1 or ATOM_PPL2 */
+        UCHAR ucTransmitterId;  /*  graphic encoder id defined in objectId.h */
+        union {
+                UCHAR ucEncoderMode;    /*  encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ */
+                UCHAR ucDVOConfig;      /*  when use DVO, need to know SDR/DDR, 12bit or 24bit */
+        };
+        UCHAR ucMiscInfo;       /*  bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel */
+        /*  bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source */
+} PIXEL_CLOCK_PARAMETERS_V3;
+
+#define PIXEL_CLOCK_PARAMETERS_LAST                     PIXEL_CLOCK_PARAMETERS_V2
+#define GET_PIXEL_CLOCK_PS_ALLOCATION           PIXEL_CLOCK_PARAMETERS_LAST
+
+/****************************************************************************/
+/*  Structures used by AdjustDisplayPllTable */
+/****************************************************************************/
+typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS {
+        USHORT usPixelClock;
+        UCHAR ucTransmitterID;
+        UCHAR ucEncodeMode;
+        union {
+                UCHAR ucDVOConfig;      /* if DVO, need passing link rate and output 12bitlow or 24bit */
+                UCHAR ucConfig; /* if none DVO, not defined yet */
+        };
+        UCHAR ucReserved[3];
+} ADJUST_DISPLAY_PLL_PARAMETERS;
+
+#define ADJUST_DISPLAY_CONFIG_SS_ENABLE       0x10
+
+#define ADJUST_DISPLAY_PLL_PS_ALLOCATION                        ADJUST_DISPLAY_PLL_PARAMETERS
+
+/****************************************************************************/
+/*  Structures used by EnableYUVTable */
+/****************************************************************************/
+typedef struct _ENABLE_YUV_PARAMETERS {
+        UCHAR ucEnable;         /*  ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) */
+        UCHAR ucCRTC;           /*  Which CRTC needs this YUV or RGB format */
+        UCHAR ucPadding[2];
+} ENABLE_YUV_PARAMETERS;
+#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
+
+/****************************************************************************/
+/*  Structures used by GetMemoryClockTable */
+/****************************************************************************/
+typedef struct _GET_MEMORY_CLOCK_PARAMETERS {
+        ULONG ulReturnMemoryClock;      /*  current memory speed in 10KHz unit */
+} GET_MEMORY_CLOCK_PARAMETERS;
+#define GET_MEMORY_CLOCK_PS_ALLOCATION  GET_MEMORY_CLOCK_PARAMETERS
+
+/****************************************************************************/
+/*  Structures used by GetEngineClockTable */
+/****************************************************************************/
+typedef struct _GET_ENGINE_CLOCK_PARAMETERS {
+        ULONG ulReturnEngineClock;      /*  current engine speed in 10KHz unit */
+} GET_ENGINE_CLOCK_PARAMETERS;
+#define GET_ENGINE_CLOCK_PS_ALLOCATION  GET_ENGINE_CLOCK_PARAMETERS
+
+/****************************************************************************/
+/*  Following Structures and constant may be obsolete */
+/****************************************************************************/
+/* Maxium 8 bytes,the data read in will be placed in the parameter space. */
+/* Read operaion successeful when the paramter space is non-zero, otherwise read operation failed */
+typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS {
+        USHORT usPrescale;      /* Ratio between Engine clock and I2C clock */
+        USHORT usVRAMAddress;   /* Adress in Frame Buffer where to pace raw EDID */
+        USHORT usStatus;        /* When use output: lower byte EDID checksum, high byte hardware status */
+        /* WHen use input:  lower byte as 'byte to read':currently limited to 128byte or 1byte */
+        UCHAR ucSlaveAddr;      /* Read from which slave */
+        UCHAR ucLineNumber;     /* Read from which HW assisted line */
+} READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
+#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION  READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
+
+#define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE                  0
+#define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES              1
+#define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK       2
+#define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK  3
+#define  ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK       4
+
+typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS {
+        USHORT usPrescale;      /* Ratio between Engine clock and I2C clock */
+        USHORT usByteOffset;    /* Write to which byte */
+        /* Upper portion of usByteOffset is Format of data */
+        /* 1bytePS+offsetPS */
+        /* 2bytesPS+offsetPS */
+        /* blockID+offsetPS */
+        /* blockID+offsetID */
+        /* blockID+counterID+offsetID */
+        UCHAR ucData;           /* PS data1 */
+        UCHAR ucStatus;         /* Status byte 1=success, 2=failure, Also is used as PS data2 */
+        UCHAR ucSlaveAddr;      /* Write to which slave */
+        UCHAR ucLineNumber;     /* Write from which HW assisted line */
+} WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
+
+#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION  WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
+
+typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS {
+        USHORT usPrescale;      /* Ratio between Engine clock and I2C clock */
+        UCHAR ucSlaveAddr;      /* Write to which slave */
+        UCHAR ucLineNumber;     /* Write from which HW assisted line */
+} SET_UP_HW_I2C_DATA_PARAMETERS;
+
+/**************************************************************************/
+#define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
+
+/****************************************************************************/
+/*  Structures used by PowerConnectorDetectionTable */
+/****************************************************************************/
+typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS {
+        UCHAR ucPowerConnectorStatus;   /* Used for return value 0: detected, 1:not detected */
+        UCHAR ucPwrBehaviorId;
+        USHORT usPwrBudget;     /* how much power currently boot to in unit of watt */
+} POWER_CONNECTOR_DETECTION_PARAMETERS;
+
+typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION {
+        UCHAR ucPowerConnectorStatus;   /* Used for return value 0: detected, 1:not detected */
+        UCHAR ucReserved;
+        USHORT usPwrBudget;     /* how much power currently boot to in unit of watt */
+        WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
+} POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
+
+/****************************LVDS SS Command Table Definitions**********************/
+
+/****************************************************************************/
+/*  Structures used by EnableSpreadSpectrumOnPPLLTable */
+/****************************************************************************/
+typedef struct _ENABLE_LVDS_SS_PARAMETERS {
+        USHORT usSpreadSpectrumPercentage;
+        UCHAR ucSpreadSpectrumType;     /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */
+        UCHAR ucSpreadSpectrumStepSize_Delay;   /* bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY */
+        UCHAR ucEnable;         /* ATOM_ENABLE or ATOM_DISABLE */
+        UCHAR ucPadding[3];
+} ENABLE_LVDS_SS_PARAMETERS;
+
+/* ucTableFormatRevision=1,ucTableContentRevision=2 */
+typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 {
+        USHORT usSpreadSpectrumPercentage;
+        UCHAR ucSpreadSpectrumType;     /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */
+        UCHAR ucSpreadSpectrumStep;     /*  */
+        UCHAR ucEnable;         /* ATOM_ENABLE or ATOM_DISABLE */
+        UCHAR ucSpreadSpectrumDelay;
+        UCHAR ucSpreadSpectrumRange;
+        UCHAR ucPadding;
+} ENABLE_LVDS_SS_PARAMETERS_V2;
+
+/* This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. */
+typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL {
+        USHORT usSpreadSpectrumPercentage;
+        UCHAR ucSpreadSpectrumType;     /*  Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */
+        UCHAR ucSpreadSpectrumStep;     /*  */
+        UCHAR ucEnable;         /*  ATOM_ENABLE or ATOM_DISABLE */
+        UCHAR ucSpreadSpectrumDelay;
+        UCHAR ucSpreadSpectrumRange;
+        UCHAR ucPpll;           /*  ATOM_PPLL1/ATOM_PPLL2 */
+} ENABLE_SPREAD_SPECTRUM_ON_PPLL;
+
+#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION  ENABLE_SPREAD_SPECTRUM_ON_PPLL
+
+/**************************************************************************/
+
+typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION {
+        PIXEL_CLOCK_PARAMETERS sPCLKInput;
+        ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;       /* Caller doesn't need to init this portion */
+} SET_PIXEL_CLOCK_PS_ALLOCATION;
+
+#define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION
+
+/****************************************************************************/
+/*  Structures used by ### */
+/****************************************************************************/
+typedef struct _MEMORY_TRAINING_PARAMETERS {
+        ULONG ulTargetMemoryClock;      /* In 10Khz unit */
+} MEMORY_TRAINING_PARAMETERS;
+#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
+
+/****************************LVDS and other encoder command table definitions **********************/
+
+/****************************************************************************/
+/*  Structures used by LVDSEncoderControlTable   (Before DCE30) */
+/*                     LVTMAEncoderControlTable  (Before DCE30) */
+/*                     TMDSAEncoderControlTable  (Before DCE30) */
+/****************************************************************************/
+typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS {
+        USHORT usPixelClock;    /*  in 10KHz; for bios convenient */
+        UCHAR ucMisc;           /*  bit0=0: Enable single link */
+        /*      =1: Enable dual link */
+        /*  Bit1=0: 666RGB */
+        /*      =1: 888RGB */
+        UCHAR ucAction;         /*  0: turn off encoder */
+        /*  1: setup and turn on encoder */
+} LVDS_ENCODER_CONTROL_PARAMETERS;
+
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION  LVDS_ENCODER_CONTROL_PARAMETERS
+
+#define TMDS1_ENCODER_CONTROL_PARAMETERS    LVDS_ENCODER_CONTROL_PARAMETERS
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
+
+#define TMDS2_ENCODER_CONTROL_PARAMETERS    TMDS1_ENCODER_CONTROL_PARAMETERS
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
+
+/* ucTableFormatRevision=1,ucTableContentRevision=2 */
+typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 {
+        USHORT usPixelClock;    /*  in 10KHz; for bios convenient */
+        UCHAR ucMisc;           /*  see PANEL_ENCODER_MISC_xx defintions below */
+        UCHAR ucAction;         /*  0: turn off encoder */
+        /*  1: setup and turn on encoder */
+        UCHAR ucTruncate;       /*  bit0=0: Disable truncate */
+        /*      =1: Enable truncate */
+        /*  bit4=0: 666RGB */
+        /*      =1: 888RGB */
+        UCHAR ucSpatial;        /*  bit0=0: Disable spatial dithering */
+        /*      =1: Enable spatial dithering */
+        /*  bit4=0: 666RGB */
+        /*      =1: 888RGB */
+        UCHAR ucTemporal;       /*  bit0=0: Disable temporal dithering */
+        /*      =1: Enable temporal dithering */
+        /*  bit4=0: 666RGB */
+        /*      =1: 888RGB */
+        /*  bit5=0: Gray level 2 */
+        /*      =1: Gray level 4 */
+        UCHAR ucFRC;            /*  bit4=0: 25FRC_SEL pattern E */
+        /*      =1: 25FRC_SEL pattern F */
+        /*  bit6:5=0: 50FRC_SEL pattern A */
+        /*        =1: 50FRC_SEL pattern B */
+        /*        =2: 50FRC_SEL pattern C */
+        /*        =3: 50FRC_SEL pattern D */
+        /*  bit7=0: 75FRC_SEL pattern E */
+        /*      =1: 75FRC_SEL pattern F */
+} LVDS_ENCODER_CONTROL_PARAMETERS_V2;
+
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
+
+#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2    LVDS_ENCODER_CONTROL_PARAMETERS_V2
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
+
+#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2    TMDS1_ENCODER_CONTROL_PARAMETERS_V2
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
+
+#define LVDS_ENCODER_CONTROL_PARAMETERS_V3     LVDS_ENCODER_CONTROL_PARAMETERS_V2
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3  LVDS_ENCODER_CONTROL_PARAMETERS_V3
+
+#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
+
+#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
+
+/****************************************************************************/
+/*  Structures used by ### */
+/****************************************************************************/
+typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS {
+        UCHAR ucEnable;         /*  Enable or Disable External TMDS encoder */
+        UCHAR ucMisc;           /*  Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} */
+        UCHAR ucPadding[2];
+} ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
+
+typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION {
+        ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
+        WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;     /* Caller doesn't need to init this portion */
+} ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
+
+#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
+
+typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 {
+        ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
+        WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;     /* Caller doesn't need to init this portion */
+} ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
+
+typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION {
+        DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;
+        WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
+} EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
+
+/****************************************************************************/
+/*  Structures used by DVOEncoderControlTable */
+/****************************************************************************/
+/* ucTableFormatRevision=1,ucTableContentRevision=3 */
+
+/* ucDVOConfig: */
+#define DVO_ENCODER_CONFIG_RATE_SEL                                                     0x01
+#define DVO_ENCODER_CONFIG_DDR_SPEED                                            0x00
+#define DVO_ENCODER_CONFIG_SDR_SPEED                                            0x01
+#define DVO_ENCODER_CONFIG_OUTPUT_SEL                                           0x0c
+#define DVO_ENCODER_CONFIG_LOW12BIT                                                     0x00
+#define DVO_ENCODER_CONFIG_UPPER12BIT                                           0x04
+#define DVO_ENCODER_CONFIG_24BIT                                                                0x08
+
+typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 {
+        USHORT usPixelClock;
+        UCHAR ucDVOConfig;
+        UCHAR ucAction;         /* ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT */
+        UCHAR ucReseved[4];
+} DVO_ENCODER_CONTROL_PARAMETERS_V3;
+#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3    DVO_ENCODER_CONTROL_PARAMETERS_V3
+
+/* ucTableFormatRevision=1 */
+/* ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for */
+/*  bit1=0: non-coherent mode */
+/*      =1: coherent mode */
+
+/* ========================================================================================== */
+/* Only change is here next time when changing encoder parameter definitions again! */
+#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST     LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST  LVDS_ENCODER_CONTROL_PARAMETERS_LAST
+
+#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
+
+#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
+#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
+
+#define DVO_ENCODER_CONTROL_PARAMETERS_LAST      DVO_ENCODER_CONTROL_PARAMETERS
+#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION
+
+/* ========================================================================================== */
+#define PANEL_ENCODER_MISC_DUAL                0x01
+#define PANEL_ENCODER_MISC_COHERENT            0x02
+#define PANEL_ENCODER_MISC_TMDS_LINKB                                    0x04
+#define PANEL_ENCODER_MISC_HDMI_TYPE                                     0x08
+
+#define PANEL_ENCODER_ACTION_DISABLE           ATOM_DISABLE
+#define PANEL_ENCODER_ACTION_ENABLE            ATOM_ENABLE
+#define PANEL_ENCODER_ACTION_COHERENTSEQ       (ATOM_ENABLE+1)
+
+#define PANEL_ENCODER_TRUNCATE_EN              0x01
+#define PANEL_ENCODER_TRUNCATE_DEPTH           0x10
+#define PANEL_ENCODER_SPATIAL_DITHER_EN        0x01
+#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH     0x10
+#define PANEL_ENCODER_TEMPORAL_DITHER_EN       0x01
+#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH    0x10
+#define PANEL_ENCODER_TEMPORAL_LEVEL_4         0x20
+#define PANEL_ENCODER_25FRC_MASK               0x10
+#define PANEL_ENCODER_25FRC_E                  0x00
+#define PANEL_ENCODER_25FRC_F                  0x10
+#define PANEL_ENCODER_50FRC_MASK               0x60
+#define PANEL_ENCODER_50FRC_A                  0x00
+#define PANEL_ENCODER_50FRC_B                  0x20
+#define PANEL_ENCODER_50FRC_C                  0x40
+#define PANEL_ENCODER_50FRC_D                  0x60
+#define PANEL_ENCODER_75FRC_MASK               0x80
+#define PANEL_ENCODER_75FRC_E                  0x00
+#define PANEL_ENCODER_75FRC_F                  0x80
+
+/****************************************************************************/
+/*  Structures used by SetVoltageTable */
+/****************************************************************************/
+#define SET_VOLTAGE_TYPE_ASIC_VDDC             1
+#define SET_VOLTAGE_TYPE_ASIC_MVDDC            2
+#define SET_VOLTAGE_TYPE_ASIC_MVDDQ            3
+#define SET_VOLTAGE_TYPE_ASIC_VDDCI            4
+#define SET_VOLTAGE_INIT_MODE                  5
+#define SET_VOLTAGE_GET_MAX_VOLTAGE            6        /* Gets the Max. voltage for the soldered Asic */
+
+#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE       0x1
+#define SET_ASIC_VOLTAGE_MODE_SOURCE_A         0x2
+#define SET_ASIC_VOLTAGE_MODE_SOURCE_B         0x4
+
+#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE      0x0
+#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL      0x1
+#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK     0x2
+
+typedef struct _SET_VOLTAGE_PARAMETERS {
+        UCHAR ucVoltageType;    /*  To tell which voltage to set up, VDDC/MVDDC/MVDDQ */
+        UCHAR ucVoltageMode;    /*  To set all, to set source A or source B or ... */
+        UCHAR ucVoltageIndex;   /*  An index to tell which voltage level */
+        UCHAR ucReserved;
+} SET_VOLTAGE_PARAMETERS;
+
+typedef struct _SET_VOLTAGE_PARAMETERS_V2 {
+        UCHAR ucVoltageType;    /*  To tell which voltage to set up, VDDC/MVDDC/MVDDQ */
+        UCHAR ucVoltageMode;    /*  Not used, maybe use for state machine for differen power mode */
+        USHORT usVoltageLevel;  /*  real voltage level */
+} SET_VOLTAGE_PARAMETERS_V2;
+
+typedef struct _SET_VOLTAGE_PS_ALLOCATION {
+        SET_VOLTAGE_PARAMETERS sASICSetVoltage;
+        WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
+} SET_VOLTAGE_PS_ALLOCATION;
+
+/****************************************************************************/
+/*  Structures used by TVEncoderControlTable */
+/****************************************************************************/
+typedef struct _TV_ENCODER_CONTROL_PARAMETERS {
+        USHORT usPixelClock;    /*  in 10KHz; for bios convenient */
+        UCHAR ucTvStandard;     /*  See definition "ATOM_TV_NTSC ..." */
+        UCHAR ucAction;         /*  0: turn off encoder */
+        /*  1: setup and turn on encoder */
+} TV_ENCODER_CONTROL_PARAMETERS;
+
+typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION {
+        TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
+        WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;     /*  Don't set this one */
+} TV_ENCODER_CONTROL_PS_ALLOCATION;
+
+/* ==============================Data Table Portion==================================== */
+
+#ifdef  UEFI_BUILD
+#define UTEMP   USHORT
+#define USHORT  void*
+#endif
+
+/****************************************************************************/
+/*  Structure used in Data.mtb */
+/****************************************************************************/
+typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES {
+        USHORT UtilityPipeLine; /*  Offest for the utility to get parser info,Don't change this position! */
+        USHORT MultimediaCapabilityInfo;        /*  Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios */
+        USHORT MultimediaConfigInfo;    /*  Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios */
+        USHORT StandardVESA_Timing;     /*  Only used by Bios */
+        USHORT FirmwareInfo;    /*  Shared by various SW components,latest version 1.4 */
+        USHORT DAC_Info;        /*  Will be obsolete from R600 */
+        USHORT LVDS_Info;       /*  Shared by various SW components,latest version 1.1 */
+        USHORT TMDS_Info;       /*  Will be obsolete from R600 */
+        USHORT AnalogTV_Info;   /*  Shared by various SW components,latest version 1.1 */
+        USHORT SupportedDevicesInfo;    /*  Will be obsolete from R600 */
+        USHORT GPIO_I2C_Info;   /*  Shared by various SW components,latest version 1.2 will be used from R600 */
+        USHORT VRAM_UsageByFirmware;    /*  Shared by various SW components,latest version 1.3 will be used from R600 */
+        USHORT GPIO_Pin_LUT;    /*  Shared by various SW components,latest version 1.1 */
+        USHORT VESA_ToInternalModeLUT;  /*  Only used by Bios */
+        USHORT ComponentVideoInfo;      /*  Shared by various SW components,latest version 2.1 will be used from R600 */
+        USHORT PowerPlayInfo;   /*  Shared by various SW components,latest version 2.1,new design from R600 */
+        USHORT CompassionateData;       /*  Will be obsolete from R600 */
+        USHORT SaveRestoreInfo; /*  Only used by Bios */
+        USHORT PPLL_SS_Info;    /*  Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info */
+        USHORT OemInfo;         /*  Defined and used by external SW, should be obsolete soon */
+        USHORT XTMDS_Info;      /*  Will be obsolete from R600 */
+        USHORT MclkSS_Info;     /*  Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used */
+        USHORT Object_Header;   /*  Shared by various SW components,latest version 1.1 */
+        USHORT IndirectIOAccess;        /*  Only used by Bios,this table position can't change at all!! */
+        USHORT MC_InitParameter;        /*  Only used by command table */
+        USHORT ASIC_VDDC_Info;  /*  Will be obsolete from R600 */
+        USHORT ASIC_InternalSS_Info;    /*  New tabel name from R600, used to be called "ASIC_MVDDC_Info" */
+        USHORT TV_VideoMode;    /*  Only used by command table */
+        USHORT VRAM_Info;       /*  Only used by command table, latest version 1.3 */
+        USHORT MemoryTrainingInfo;      /*  Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 */
+        USHORT IntegratedSystemInfo;    /*  Shared by various SW components */
+        USHORT ASIC_ProfilingInfo;      /*  New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 */
+        USHORT VoltageObjectInfo;       /*  Shared by various SW components, latest version 1.1 */
+        USHORT PowerSourceInfo; /*  Shared by various SW components, latest versoin 1.1 */
+} ATOM_MASTER_LIST_OF_DATA_TABLES;
+
+#ifdef  UEFI_BUILD
+#define USHORT  UTEMP
+#endif
+
+typedef struct _ATOM_MASTER_DATA_TABLE {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
+} ATOM_MASTER_DATA_TABLE;
+
+/****************************************************************************/
+/*  Structure used in MultimediaCapabilityInfoTable */
+/****************************************************************************/
+typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ULONG ulSignature;      /*  HW info table signature string "$ATI" */
+        UCHAR ucI2C_Type;       /*  I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) */
+        UCHAR ucTV_OutInfo;     /*  Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) */
+        UCHAR ucVideoPortInfo;  /*  Provides the video port capabilities */
+        UCHAR ucHostPortInfo;   /*  Provides host port configuration information */
+} ATOM_MULTIMEDIA_CAPABILITY_INFO;
+
+/****************************************************************************/
+/*  Structure used in MultimediaConfigInfoTable */
+/****************************************************************************/
+typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ULONG ulSignature;      /*  MM info table signature sting "$MMT" */
+        UCHAR ucTunerInfo;      /*  Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) */
+        UCHAR ucAudioChipInfo;  /*  List the audio chip type (3:0) product type (4) and OEM revision (7:5) */
+        UCHAR ucProductID;      /*  Defines as OEM ID or ATI board ID dependent on product type setting */
+        UCHAR ucMiscInfo1;      /*  Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) */
+        UCHAR ucMiscInfo2;      /*  I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) */
+        UCHAR ucMiscInfo3;      /*  Video Decoder Type (3:0) Video In Standard/Crystal (7:4) */
+        UCHAR ucMiscInfo4;      /*  Video Decoder Host Config (2:0) reserved (7:3) */
+        UCHAR ucVideoInput0Info;        /*  Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */
+        UCHAR ucVideoInput1Info;        /*  Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */
+        UCHAR ucVideoInput2Info;        /*  Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */
+        UCHAR ucVideoInput3Info;        /*  Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */
+        UCHAR ucVideoInput4Info;        /*  Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */
+} ATOM_MULTIMEDIA_CONFIG_INFO;
+
+/****************************************************************************/
+/*  Structures used in FirmwareInfoTable */
+/****************************************************************************/
+
+/*  usBIOSCapability Defintion: */
+/*  Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; */
+/*  Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; */
+/*  Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; */
+/*  Others: Reserved */
+#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED         0x0001
+#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT            0x0002
+#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT     0x0004
+#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT      0x0008
+#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT      0x0010
+#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU         0x0020
+#define ATOM_BIOS_INFO_WMI_SUPPORT                  0x0040
+#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080
+#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT          0x0100
+#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK        0x1E00
+#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
+#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE  0x4000
+
+#ifndef _H2INC
+
+/* Please don't add or expand this bitfield structure below, this one will retire soon.! */
+typedef struct _ATOM_FIRMWARE_CAPABILITY {
+#if ATOM_BIG_ENDIAN
+        USHORT Reserved:3;
+        USHORT HyperMemory_Size:4;
+        USHORT HyperMemory_Support:1;
+        USHORT PPMode_Assigned:1;
+        USHORT WMI_SUPPORT:1;
+        USHORT GPUControlsBL:1;
+        USHORT EngineClockSS_Support:1;
+        USHORT MemoryClockSS_Support:1;
+        USHORT ExtendedDesktopSupport:1;
+        USHORT DualCRTC_Support:1;
+        USHORT FirmwarePosted:1;
+#else
+        USHORT FirmwarePosted:1;
+        USHORT DualCRTC_Support:1;
+        USHORT ExtendedDesktopSupport:1;
+        USHORT MemoryClockSS_Support:1;
+        USHORT EngineClockSS_Support:1;
+        USHORT GPUControlsBL:1;
+        USHORT WMI_SUPPORT:1;
+        USHORT PPMode_Assigned:1;
+        USHORT HyperMemory_Support:1;
+        USHORT HyperMemory_Size:4;
+        USHORT Reserved:3;
+#endif
+} ATOM_FIRMWARE_CAPABILITY;
+
+typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS {
+        ATOM_FIRMWARE_CAPABILITY sbfAccess;
+        USHORT susAccess;
+} ATOM_FIRMWARE_CAPABILITY_ACCESS;
+
+#else
+
+typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS {
+        USHORT susAccess;
+} ATOM_FIRMWARE_CAPABILITY_ACCESS;
+
+#endif
+
+typedef struct _ATOM_FIRMWARE_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ULONG ulFirmwareRevision;
+        ULONG ulDefaultEngineClock;     /* In 10Khz unit */
+        ULONG ulDefaultMemoryClock;     /* In 10Khz unit */
+        ULONG ulDriverTargetEngineClock;        /* In 10Khz unit */
+        ULONG ulDriverTargetMemoryClock;        /* In 10Khz unit */
+        ULONG ulMaxEngineClockPLL_Output;       /* In 10Khz unit */
+        ULONG ulMaxMemoryClockPLL_Output;       /* In 10Khz unit */
+        ULONG ulMaxPixelClockPLL_Output;        /* In 10Khz unit */
+        ULONG ulASICMaxEngineClock;     /* In 10Khz unit */
+        ULONG ulASICMaxMemoryClock;     /* In 10Khz unit */
+        UCHAR ucASICMaxTemperature;
+        UCHAR ucPadding[3];     /* Don't use them */
+        ULONG aulReservedForBIOS[3];    /* Don't use them */
+        USHORT usMinEngineClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMaxEngineClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMinEngineClockPLL_Output;      /* In 10Khz unit */
+        USHORT usMinMemoryClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMaxMemoryClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMinMemoryClockPLL_Output;      /* In 10Khz unit */
+        USHORT usMaxPixelClock; /* In 10Khz unit, Max.  Pclk */
+        USHORT usMinPixelClockPLL_Input;        /* In 10Khz unit */
+        USHORT usMaxPixelClockPLL_Input;        /* In 10Khz unit */
+        USHORT usMinPixelClockPLL_Output;       /* In 10Khz unit, the definitions above can't change!!! */
+        ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+        USHORT usReferenceClock;        /* In 10Khz unit */
+        USHORT usPM_RTS_Location;       /* RTS PM4 starting location in ROM in 1Kb unit */
+        UCHAR ucPM_RTS_StreamSize;      /* RTS PM4 packets in Kb unit */
+        UCHAR ucDesign_ID;      /* Indicate what is the board design */
+        UCHAR ucMemoryModule_ID;        /* Indicate what is the board design */
+} ATOM_FIRMWARE_INFO;
+
+typedef struct _ATOM_FIRMWARE_INFO_V1_2 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ULONG ulFirmwareRevision;
+        ULONG ulDefaultEngineClock;     /* In 10Khz unit */
+        ULONG ulDefaultMemoryClock;     /* In 10Khz unit */
+        ULONG ulDriverTargetEngineClock;        /* In 10Khz unit */
+        ULONG ulDriverTargetMemoryClock;        /* In 10Khz unit */
+        ULONG ulMaxEngineClockPLL_Output;       /* In 10Khz unit */
+        ULONG ulMaxMemoryClockPLL_Output;       /* In 10Khz unit */
+        ULONG ulMaxPixelClockPLL_Output;        /* In 10Khz unit */
+        ULONG ulASICMaxEngineClock;     /* In 10Khz unit */
+        ULONG ulASICMaxMemoryClock;     /* In 10Khz unit */
+        UCHAR ucASICMaxTemperature;
+        UCHAR ucMinAllowedBL_Level;
+        UCHAR ucPadding[2];     /* Don't use them */
+        ULONG aulReservedForBIOS[2];    /* Don't use them */
+        ULONG ulMinPixelClockPLL_Output;        /* In 10Khz unit */
+        USHORT usMinEngineClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMaxEngineClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMinEngineClockPLL_Output;      /* In 10Khz unit */
+        USHORT usMinMemoryClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMaxMemoryClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMinMemoryClockPLL_Output;      /* In 10Khz unit */
+        USHORT usMaxPixelClock; /* In 10Khz unit, Max.  Pclk */
+        USHORT usMinPixelClockPLL_Input;        /* In 10Khz unit */
+        USHORT usMaxPixelClockPLL_Input;        /* In 10Khz unit */
+        USHORT usMinPixelClockPLL_Output;       /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */
+        ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+        USHORT usReferenceClock;        /* In 10Khz unit */
+        USHORT usPM_RTS_Location;       /* RTS PM4 starting location in ROM in 1Kb unit */
+        UCHAR ucPM_RTS_StreamSize;      /* RTS PM4 packets in Kb unit */
+        UCHAR ucDesign_ID;      /* Indicate what is the board design */
+        UCHAR ucMemoryModule_ID;        /* Indicate what is the board design */
+} ATOM_FIRMWARE_INFO_V1_2;
+
+typedef struct _ATOM_FIRMWARE_INFO_V1_3 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ULONG ulFirmwareRevision;
+        ULONG ulDefaultEngineClock;     /* In 10Khz unit */
+        ULONG ulDefaultMemoryClock;     /* In 10Khz unit */
+        ULONG ulDriverTargetEngineClock;        /* In 10Khz unit */
+        ULONG ulDriverTargetMemoryClock;        /* In 10Khz unit */
+        ULONG ulMaxEngineClockPLL_Output;       /* In 10Khz unit */
+        ULONG ulMaxMemoryClockPLL_Output;       /* In 10Khz unit */
+        ULONG ulMaxPixelClockPLL_Output;        /* In 10Khz unit */
+        ULONG ulASICMaxEngineClock;     /* In 10Khz unit */
+        ULONG ulASICMaxMemoryClock;     /* In 10Khz unit */
+        UCHAR ucASICMaxTemperature;
+        UCHAR ucMinAllowedBL_Level;
+        UCHAR ucPadding[2];     /* Don't use them */
+        ULONG aulReservedForBIOS;       /* Don't use them */
+        ULONG ul3DAccelerationEngineClock;      /* In 10Khz unit */
+        ULONG ulMinPixelClockPLL_Output;        /* In 10Khz unit */
+        USHORT usMinEngineClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMaxEngineClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMinEngineClockPLL_Output;      /* In 10Khz unit */
+        USHORT usMinMemoryClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMaxMemoryClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMinMemoryClockPLL_Output;      /* In 10Khz unit */
+        USHORT usMaxPixelClock; /* In 10Khz unit, Max.  Pclk */
+        USHORT usMinPixelClockPLL_Input;        /* In 10Khz unit */
+        USHORT usMaxPixelClockPLL_Input;        /* In 10Khz unit */
+        USHORT usMinPixelClockPLL_Output;       /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */
+        ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+        USHORT usReferenceClock;        /* In 10Khz unit */
+        USHORT usPM_RTS_Location;       /* RTS PM4 starting location in ROM in 1Kb unit */
+        UCHAR ucPM_RTS_StreamSize;      /* RTS PM4 packets in Kb unit */
+        UCHAR ucDesign_ID;      /* Indicate what is the board design */
+        UCHAR ucMemoryModule_ID;        /* Indicate what is the board design */
+} ATOM_FIRMWARE_INFO_V1_3;
+
+typedef struct _ATOM_FIRMWARE_INFO_V1_4 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ULONG ulFirmwareRevision;
+        ULONG ulDefaultEngineClock;     /* In 10Khz unit */
+        ULONG ulDefaultMemoryClock;     /* In 10Khz unit */
+        ULONG ulDriverTargetEngineClock;        /* In 10Khz unit */
+        ULONG ulDriverTargetMemoryClock;        /* In 10Khz unit */
+        ULONG ulMaxEngineClockPLL_Output;       /* In 10Khz unit */
+        ULONG ulMaxMemoryClockPLL_Output;       /* In 10Khz unit */
+        ULONG ulMaxPixelClockPLL_Output;        /* In 10Khz unit */
+        ULONG ulASICMaxEngineClock;     /* In 10Khz unit */
+        ULONG ulASICMaxMemoryClock;     /* In 10Khz unit */
+        UCHAR ucASICMaxTemperature;
+        UCHAR ucMinAllowedBL_Level;
+        USHORT usBootUpVDDCVoltage;     /* In MV unit */
+        USHORT usLcdMinPixelClockPLL_Output;    /*  In MHz unit */
+        USHORT usLcdMaxPixelClockPLL_Output;    /*  In MHz unit */
+        ULONG ul3DAccelerationEngineClock;      /* In 10Khz unit */
+        ULONG ulMinPixelClockPLL_Output;        /* In 10Khz unit */
+        USHORT usMinEngineClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMaxEngineClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMinEngineClockPLL_Output;      /* In 10Khz unit */
+        USHORT usMinMemoryClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMaxMemoryClockPLL_Input;       /* In 10Khz unit */
+        USHORT usMinMemoryClockPLL_Output;      /* In 10Khz unit */
+        USHORT usMaxPixelClock; /* In 10Khz unit, Max.  Pclk */
+        USHORT usMinPixelClockPLL_Input;        /* In 10Khz unit */
+        USHORT usMaxPixelClockPLL_Input;        /* In 10Khz unit */
+        USHORT usMinPixelClockPLL_Output;       /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */
+        ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
+        USHORT usReferenceClock;        /* In 10Khz unit */
+        USHORT usPM_RTS_Location;       /* RTS PM4 starting location in ROM in 1Kb unit */
+        UCHAR ucPM_RTS_StreamSize;      /* RTS PM4 packets in Kb unit */
+        UCHAR ucDesign_ID;      /* Indicate what is the board design */
+        UCHAR ucMemoryModule_ID;        /* Indicate what is the board design */
+} ATOM_FIRMWARE_INFO_V1_4;
+
+#define ATOM_FIRMWARE_INFO_LAST  ATOM_FIRMWARE_INFO_V1_4
+
+/****************************************************************************/
+/*  Structures used in IntegratedSystemInfoTable */
+/****************************************************************************/
+#define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN      0x2
+#define IGP_CAP_FLAG_AC_CARD               0x4
+#define IGP_CAP_FLAG_SDVO_CARD             0x8
+#define IGP_CAP_FLAG_POSTDIV_BY_2_MODE     0x10
+
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ULONG ulBootUpEngineClock;      /* in 10kHz unit */
+        ULONG ulBootUpMemoryClock;      /* in 10kHz unit */
+        ULONG ulMaxSystemMemoryClock;   /* in 10kHz unit */
+        ULONG ulMinSystemMemoryClock;   /* in 10kHz unit */
+        UCHAR ucNumberOfCyclesInPeriodHi;
+        UCHAR ucLCDTimingSel;   /* =0:not valid.!=0 sel this timing descriptor from LCD EDID. */
+        USHORT usReserved1;
+        USHORT usInterNBVoltageLow;     /* An intermidiate PMW value to set the voltage */
+        USHORT usInterNBVoltageHigh;    /* Another intermidiate PMW value to set the voltage */
+        ULONG ulReserved[2];
+
+        USHORT usFSBClock;      /* In MHz unit */
+        USHORT usCapabilityFlag;        /* Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable */
+        /* Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card */
+        /* Bit[4]==1: P/2 mode, ==0: P/1 mode */
+        USHORT usPCIENBCfgReg7; /* bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal */
+        USHORT usK8MemoryClock; /* in MHz unit */
+        USHORT usK8SyncStartDelay;      /* in 0.01 us unit */
+        USHORT usK8DataReturnTime;      /* in 0.01 us unit */
+        UCHAR ucMaxNBVoltage;
+        UCHAR ucMinNBVoltage;
+        UCHAR ucMemoryType;     /* [7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved */
+        UCHAR ucNumberOfCyclesInPeriod; /* CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod */
+        UCHAR ucStartingPWM_HighTime;   /* CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime */
+        UCHAR ucHTLinkWidth;    /* 16 bit vs. 8 bit */
+        UCHAR ucMaxNBVoltageHigh;
+        UCHAR ucMinNBVoltageHigh;
+} ATOM_INTEGRATED_SYSTEM_INFO;
+
+/* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
+ulBootUpMemoryClock:    For Intel IGP,it's the UMA system memory clock
+                        For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
+ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
+                        For AMD IGP,for now this can be 0
+ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
+                        For AMD IGP,for now this can be 0
+
+usFSBClock:             For Intel IGP,it's FSB Freq
+                        For AMD IGP,it's HT Link Speed
+
+usK8MemoryClock:        For AMD IGP only. For RevF CPU, set it to 200
+usK8SyncStartDelay:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
+usK8DataReturnTime:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
+
+VC:Voltage Control
+ucMaxNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
+ucMinNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
+
+ucNumberOfCyclesInPeriod:   Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
+ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
+
+ucMaxNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of  the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
+ucMinNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
+
+usInterNBVoltageLow:    Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
+usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
+*/
+
+/*
+The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
+Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
+The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
+
+SW components can access the IGP system infor structure in the same way as before
+*/
+
+typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ULONG ulBootUpEngineClock;      /* in 10kHz unit */
+        ULONG ulReserved1[2];   /* must be 0x0 for the reserved */
+        ULONG ulBootUpUMAClock; /* in 10kHz unit */
+        ULONG ulBootUpSidePortClock;    /* in 10kHz unit */
+        ULONG ulMinSidePortClock;       /* in 10kHz unit */
+        ULONG ulReserved2[6];   /* must be 0x0 for the reserved */
+        ULONG ulSystemConfig;   /* see explanation below */
+        ULONG ulBootUpReqDisplayVector;
+        ULONG ulOtherDisplayMisc;
+        ULONG ulDDISlot1Config;
+        ULONG ulDDISlot2Config;
+        UCHAR ucMemoryType;     /* [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved */
+        UCHAR ucUMAChannelNumber;
+        UCHAR ucDockingPinBit;
+        UCHAR ucDockingPinPolarity;
+        ULONG ulDockingPinCFGInfo;
+        ULONG ulCPUCapInfo;
+        USHORT usNumberOfCyclesInPeriod;
+        USHORT usMaxNBVoltage;
+        USHORT usMinNBVoltage;
+        USHORT usBootUpNBVoltage;
+        ULONG ulHTLinkFreq;     /* in 10Khz */
+        USHORT usMinHTLinkWidth;
+        USHORT usMaxHTLinkWidth;
+        USHORT usUMASyncStartDelay;
+        USHORT usUMADataReturnTime;
+        USHORT usLinkStatusZeroTime;
+        USHORT usReserved;
+        ULONG ulHighVoltageHTLinkFreq;  /*  in 10Khz */
+        ULONG ulLowVoltageHTLinkFreq;   /*  in 10Khz */
+        USHORT usMaxUpStreamHTLinkWidth;
+        USHORT usMaxDownStreamHTLinkWidth;
+        USHORT usMinUpStreamHTLinkWidth;
+        USHORT usMinDownStreamHTLinkWidth;
+        ULONG ulReserved3[97];  /* must be 0x0 */
+} ATOM_INTEGRATED_SYSTEM_INFO_V2;
+
+/*
+ulBootUpEngineClock:   Boot-up Engine Clock in 10Khz;
+ulBootUpUMAClock:      Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
+ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
+
+ulSystemConfig:
+Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
+Bit[1]=1: system boots up at AMD overdrived state or user customized  mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
+      =0: system boots up at driver control state. Power state depends on PowerPlay table.
+Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
+Bit[3]=1: Only one power state(Performance) will be supported.
+      =0: Multiple power states supported from PowerPlay table.
+Bit[4]=1: CLMC is supported and enabled on current system.
+      =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
+Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
+      =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
+Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
+      =0: Voltage settings is determined by powerplay table.
+Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
+      =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
+
+ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
+
+ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
+                                      [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
+
+ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
+      [3:0]  - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
+                        [7:4]  - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
+                        [15:8] - Lane configuration attribute;
+      [23:16]- Connector type, possible value:
+               CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
+               CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
+               CONNECTOR_OBJECT_ID_HDMI_TYPE_A
+               CONNECTOR_OBJECT_ID_DISPLAYPORT
+                        [31:24]- Reserved
+
+ulDDISlot2Config: Same as Slot1.
+ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
+For IGP, Hypermemory is the only memory type showed in CCC.
+
+ucUMAChannelNumber:  how many channels for the UMA;
+
+ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
+ucDockingPinBit:     which bit in this register to read the pin status;
+ucDockingPinPolarity:Polarity of the pin when docked;
+
+ulCPUCapInfo:        [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0
+
+usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
+usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
+usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
+                    GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
+                    PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
+                    GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
+usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
+
+ulHTLinkFreq:       Bootup HT link Frequency in 10Khz.
+usMinHTLinkWidth:   Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
+                    If CDLW enabled, both upstream and downstream width should be the same during bootup.
+usMaxHTLinkWidth:   Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
+                    If CDLW enabled, both upstream and downstream width should be the same during bootup.
+
+usUMASyncStartDelay: Memory access latency, required for watermark calculation
+usUMADataReturnTime: Memory access latency, required for watermark calculation
+usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
+for Griffin or Greyhound. SBIOS needs to convert to actual time by:
+                     if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
+                     if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
+                     if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
+                     if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
+
+ulHighVoltageHTLinkFreq:     HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
+                             This must be less than or equal to ulHTLinkFreq(bootup frequency).
+ulLowVoltageHTLinkFreq:      HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
+                             This must be less than or equal to ulHighVoltageHTLinkFreq.
+
+usMaxUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
+usMaxDownStreamHTLinkWidth:  same as above.
+usMinUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
+usMinDownStreamHTLinkWidth:  same as above.
+*/
+
+#define SYSTEM_CONFIG_POWEREXPRESS_ENABLE                 0x00000001
+#define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE             0x00000002
+#define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE                  0x00000004
+#define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY         0x00000008
+#define SYSTEM_CONFIG_CLMC_ENABLED                        0x00000010
+#define SYSTEM_CONFIG_CDLW_ENABLED                        0x00000020
+#define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED              0x00000040
+#define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED            0x00000080
+
+#define IGP_DDI_SLOT_LANE_CONFIG_MASK                     0x000000FF
+
+#define b0IGP_DDI_SLOT_LANE_MAP_MASK                      0x0F
+#define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK              0xF0
+#define b0IGP_DDI_SLOT_CONFIG_LANE_0_3                    0x01
+#define b0IGP_DDI_SLOT_CONFIG_LANE_4_7                    0x02
+#define b0IGP_DDI_SLOT_CONFIG_LANE_8_11                   0x04
+#define b0IGP_DDI_SLOT_CONFIG_LANE_12_15                  0x08
+
+#define IGP_DDI_SLOT_ATTRIBUTE_MASK                       0x0000FF00
+#define IGP_DDI_SLOT_CONFIG_REVERSED                      0x00000100
+#define b1IGP_DDI_SLOT_CONFIG_REVERSED                    0x01
+
+#define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK                  0x00FF0000
+
+#define ATOM_CRT_INT_ENCODER1_INDEX                       0x00000000
+#define ATOM_LCD_INT_ENCODER1_INDEX                       0x00000001
+#define ATOM_TV_INT_ENCODER1_INDEX                        0x00000002
+#define ATOM_DFP_INT_ENCODER1_INDEX                       0x00000003
+#define ATOM_CRT_INT_ENCODER2_INDEX                       0x00000004
+#define ATOM_LCD_EXT_ENCODER1_INDEX                       0x00000005
+#define ATOM_TV_EXT_ENCODER1_INDEX                        0x00000006
+#define ATOM_DFP_EXT_ENCODER1_INDEX                       0x00000007
+#define ATOM_CV_INT_ENCODER1_INDEX                        0x00000008
+#define ATOM_DFP_INT_ENCODER2_INDEX                       0x00000009
+#define ATOM_CRT_EXT_ENCODER1_INDEX                       0x0000000A
+#define ATOM_CV_EXT_ENCODER1_INDEX                        0x0000000B
+#define ATOM_DFP_INT_ENCODER3_INDEX                       0x0000000C
+#define ATOM_DFP_INT_ENCODER4_INDEX                       0x0000000D
+
+/*  define ASIC internal encoder id ( bit vector ) */
+#define ASIC_INT_DAC1_ENCODER_ID                                                                                        0x00
+#define ASIC_INT_TV_ENCODER_ID                                                                                                          0x02
+#define ASIC_INT_DIG1_ENCODER_ID                                                                                                        0x03
+#define ASIC_INT_DAC2_ENCODER_ID                                                                                                        0x04
+#define ASIC_EXT_TV_ENCODER_ID                                                                                                          0x06
+#define ASIC_INT_DVO_ENCODER_ID                                                                                                         0x07
+#define ASIC_INT_DIG2_ENCODER_ID                                                                                                        0x09
+#define ASIC_EXT_DIG_ENCODER_ID                                                                                                         0x05
+
+/* define Encoder attribute */
+#define ATOM_ANALOG_ENCODER                                                                                                                             0
+#define ATOM_DIGITAL_ENCODER                                                                                                                    1
+
+#define ATOM_DEVICE_CRT1_INDEX                            0x00000000
+#define ATOM_DEVICE_LCD1_INDEX                            0x00000001
+#define ATOM_DEVICE_TV1_INDEX                             0x00000002
+#define ATOM_DEVICE_DFP1_INDEX                            0x00000003
+#define ATOM_DEVICE_CRT2_INDEX                            0x00000004
+#define ATOM_DEVICE_LCD2_INDEX                            0x00000005
+#define ATOM_DEVICE_TV2_INDEX                             0x00000006
+#define ATOM_DEVICE_DFP2_INDEX                            0x00000007
+#define ATOM_DEVICE_CV_INDEX                              0x00000008
+#define ATOM_DEVICE_DFP3_INDEX                                                                                                          0x00000009
+#define ATOM_DEVICE_DFP4_INDEX                                                                                                          0x0000000A
+#define ATOM_DEVICE_DFP5_INDEX                                                                                                          0x0000000B
+#define ATOM_DEVICE_RESERVEDC_INDEX                       0x0000000C
+#define ATOM_DEVICE_RESERVEDD_INDEX                       0x0000000D
+#define ATOM_DEVICE_RESERVEDE_INDEX                       0x0000000E
+#define ATOM_DEVICE_RESERVEDF_INDEX                       0x0000000F
+#define ATOM_MAX_SUPPORTED_DEVICE_INFO                    (ATOM_DEVICE_DFP3_INDEX+1)
+#define ATOM_MAX_SUPPORTED_DEVICE_INFO_2                  ATOM_MAX_SUPPORTED_DEVICE_INFO
+#define ATOM_MAX_SUPPORTED_DEVICE_INFO_3                  (ATOM_DEVICE_DFP5_INDEX + 1)
+
+#define ATOM_MAX_SUPPORTED_DEVICE                         (ATOM_DEVICE_RESERVEDF_INDEX+1)
+
+#define ATOM_DEVICE_CRT1_SUPPORT                          (0x1L << ATOM_DEVICE_CRT1_INDEX)
+#define ATOM_DEVICE_LCD1_SUPPORT                          (0x1L << ATOM_DEVICE_LCD1_INDEX)
+#define ATOM_DEVICE_TV1_SUPPORT                           (0x1L << ATOM_DEVICE_TV1_INDEX)
+#define ATOM_DEVICE_DFP1_SUPPORT                          (0x1L << ATOM_DEVICE_DFP1_INDEX)
+#define ATOM_DEVICE_CRT2_SUPPORT                          (0x1L << ATOM_DEVICE_CRT2_INDEX)
+#define ATOM_DEVICE_LCD2_SUPPORT                          (0x1L << ATOM_DEVICE_LCD2_INDEX)
+#define ATOM_DEVICE_TV2_SUPPORT                           (0x1L << ATOM_DEVICE_TV2_INDEX)
+#define ATOM_DEVICE_DFP2_SUPPORT                          (0x1L << ATOM_DEVICE_DFP2_INDEX)
+#define ATOM_DEVICE_CV_SUPPORT                            (0x1L << ATOM_DEVICE_CV_INDEX)
+#define ATOM_DEVICE_DFP3_SUPPORT                                                                                                        (0x1L << ATOM_DEVICE_DFP3_INDEX)
+#define ATOM_DEVICE_DFP4_SUPPORT                                                                                                        (0x1L << ATOM_DEVICE_DFP4_INDEX )
+#define ATOM_DEVICE_DFP5_SUPPORT                                                                                                        (0x1L << ATOM_DEVICE_DFP5_INDEX)
+
+#define ATOM_DEVICE_CRT_SUPPORT \
+        (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
+#define ATOM_DEVICE_DFP_SUPPORT \
+        (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | \
+         ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | \
+         ATOM_DEVICE_DFP5_SUPPORT)
+#define ATOM_DEVICE_TV_SUPPORT \
+        (ATOM_DEVICE_TV1_SUPPORT  | ATOM_DEVICE_TV2_SUPPORT)
+#define ATOM_DEVICE_LCD_SUPPORT \
+        (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
+
+#define ATOM_DEVICE_CONNECTOR_TYPE_MASK                   0x000000F0
+#define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT                  0x00000004
+#define ATOM_DEVICE_CONNECTOR_VGA                         0x00000001
+#define ATOM_DEVICE_CONNECTOR_DVI_I                       0x00000002
+#define ATOM_DEVICE_CONNECTOR_DVI_D                       0x00000003
+#define ATOM_DEVICE_CONNECTOR_DVI_A                       0x00000004
+#define ATOM_DEVICE_CONNECTOR_SVIDEO                      0x00000005
+#define ATOM_DEVICE_CONNECTOR_COMPOSITE                   0x00000006
+#define ATOM_DEVICE_CONNECTOR_LVDS                        0x00000007
+#define ATOM_DEVICE_CONNECTOR_DIGI_LINK                   0x00000008
+#define ATOM_DEVICE_CONNECTOR_SCART                       0x00000009
+#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A                 0x0000000A
+#define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B                 0x0000000B
+#define ATOM_DEVICE_CONNECTOR_CASE_1                      0x0000000E
+#define ATOM_DEVICE_CONNECTOR_DISPLAYPORT                 0x0000000F
+
+#define ATOM_DEVICE_DAC_INFO_MASK                         0x0000000F
+#define ATOM_DEVICE_DAC_INFO_SHIFT                        0x00000000
+#define ATOM_DEVICE_DAC_INFO_NODAC                        0x00000000
+#define ATOM_DEVICE_DAC_INFO_DACA                         0x00000001
+#define ATOM_DEVICE_DAC_INFO_DACB                         0x00000002
+#define ATOM_DEVICE_DAC_INFO_EXDAC                        0x00000003
+
+#define ATOM_DEVICE_I2C_ID_NOI2C                          0x00000000
+
+#define ATOM_DEVICE_I2C_LINEMUX_MASK                      0x0000000F
+#define ATOM_DEVICE_I2C_LINEMUX_SHIFT                     0x00000000
+
+#define ATOM_DEVICE_I2C_ID_MASK                           0x00000070
+#define ATOM_DEVICE_I2C_ID_SHIFT                          0x00000004
+#define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE              0x00000001
+#define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE                  0x00000002
+#define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE                0x00000003    /* For IGP RS600 */
+#define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL                 0x00000004    /* For IGP RS690 */
+
+#define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK                 0x00000080
+#define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT                0x00000007
+#define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C            0x00000000
+#define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C            0x00000001
+
+/*   usDeviceSupport: */
+/*   Bits0       = 0 - no CRT1 support= 1- CRT1 is supported */
+/*   Bit 1       = 0 - no LCD1 support= 1- LCD1 is supported */
+/*   Bit 2       = 0 - no TV1  support= 1- TV1  is supported */
+/*   Bit 3       = 0 - no DFP1 support= 1- DFP1 is supported */
+/*   Bit 4       = 0 - no CRT2 support= 1- CRT2 is supported */
+/*   Bit 5       = 0 - no LCD2 support= 1- LCD2 is supported */
+/*   Bit 6       = 0 - no TV2  support= 1- TV2  is supported */
+/*   Bit 7       = 0 - no DFP2 support= 1- DFP2 is supported */
+/*   Bit 8       = 0 - no CV   support= 1- CV   is supported */
+/*   Bit 9       = 0 - no DFP3 support= 1- DFP3 is supported */
+/*   Byte1 (Supported Device Info) */
+/*   Bit 0       = = 0 - no CV support= 1- CV is supported */
+/*  */
+/*  */
+
+/*               ucI2C_ConfigID */
+/*     [7:0] - I2C LINE Associate ID */
+/*           = 0   - no I2C */
+/*     [7]               -       HW_Cap        = 1,  [6:0]=HW assisted I2C ID(HW line selection) */
+/*                           =   0,  [6:0]=SW assisted I2C ID */
+/*     [6-4]     - HW_ENGINE_ID  =       1,  HW engine for NON multimedia use */
+/*                           =   2,      HW engine for Multimedia use */
+/*                           =   3-7     Reserved for future I2C engines */
+/*               [3-0] - I2C_LINE_MUX  = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C */
+
+typedef struct _ATOM_I2C_ID_CONFIG {
+#if ATOM_BIG_ENDIAN
+        UCHAR bfHW_Capable:1;
+        UCHAR bfHW_EngineID:3;
+        UCHAR bfI2C_LineMux:4;
+#else
+        UCHAR bfI2C_LineMux:4;
+        UCHAR bfHW_EngineID:3;
+        UCHAR bfHW_Capable:1;
+#endif
+} ATOM_I2C_ID_CONFIG;
+
+typedef union _ATOM_I2C_ID_CONFIG_ACCESS {
+        ATOM_I2C_ID_CONFIG sbfAccess;
+        UCHAR ucAccess;
+} ATOM_I2C_ID_CONFIG_ACCESS;
+
+/****************************************************************************/
+/*  Structure used in GPIO_I2C_InfoTable */
+/****************************************************************************/
+typedef struct _ATOM_GPIO_I2C_ASSIGMENT {
+        USHORT usClkMaskRegisterIndex;
+        USHORT usClkEnRegisterIndex;
+        USHORT usClkY_RegisterIndex;
+        USHORT usClkA_RegisterIndex;
+        USHORT usDataMaskRegisterIndex;
+        USHORT usDataEnRegisterIndex;
+        USHORT usDataY_RegisterIndex;
+        USHORT usDataA_RegisterIndex;
+        ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
+        UCHAR ucClkMaskShift;
+        UCHAR ucClkEnShift;
+        UCHAR ucClkY_Shift;
+        UCHAR ucClkA_Shift;
+        UCHAR ucDataMaskShift;
+        UCHAR ucDataEnShift;
+        UCHAR ucDataY_Shift;
+        UCHAR ucDataA_Shift;
+        UCHAR ucReserved1;
+        UCHAR ucReserved2;
+} ATOM_GPIO_I2C_ASSIGMENT;
+
+typedef struct _ATOM_GPIO_I2C_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
+} ATOM_GPIO_I2C_INFO;
+
+/****************************************************************************/
+/*  Common Structure used in other structures */
+/****************************************************************************/
+
+#ifndef _H2INC
+
+/* Please don't add or expand this bitfield structure below, this one will retire soon.! */
+typedef struct _ATOM_MODE_MISC_INFO {
+#if ATOM_BIG_ENDIAN
+        USHORT Reserved:6;
+        USHORT RGB888:1;
+        USHORT DoubleClock:1;
+        USHORT Interlace:1;
+        USHORT CompositeSync:1;
+        USHORT V_ReplicationBy2:1;
+        USHORT H_ReplicationBy2:1;
+        USHORT VerticalCutOff:1;
+        USHORT VSyncPolarity:1; /* 0=Active High, 1=Active Low */
+        USHORT HSyncPolarity:1; /* 0=Active High, 1=Active Low */
+        USHORT HorizontalCutOff:1;
+#else
+        USHORT HorizontalCutOff:1;
+        USHORT HSyncPolarity:1; /* 0=Active High, 1=Active Low */
+        USHORT VSyncPolarity:1; /* 0=Active High, 1=Active Low */
+        USHORT VerticalCutOff:1;
+        USHORT H_ReplicationBy2:1;
+        USHORT V_ReplicationBy2:1;
+        USHORT CompositeSync:1;
+        USHORT Interlace:1;
+        USHORT DoubleClock:1;
+        USHORT RGB888:1;
+        USHORT Reserved:6;
+#endif
+} ATOM_MODE_MISC_INFO;
+
+typedef union _ATOM_MODE_MISC_INFO_ACCESS {
+        ATOM_MODE_MISC_INFO sbfAccess;
+        USHORT usAccess;
+} ATOM_MODE_MISC_INFO_ACCESS;
+
+#else
+
+typedef union _ATOM_MODE_MISC_INFO_ACCESS {
+        USHORT usAccess;
+} ATOM_MODE_MISC_INFO_ACCESS;
+
+#endif
+
+/*  usModeMiscInfo- */
+#define ATOM_H_CUTOFF           0x01
+#define ATOM_HSYNC_POLARITY     0x02    /* 0=Active High, 1=Active Low */
+#define ATOM_VSYNC_POLARITY     0x04    /* 0=Active High, 1=Active Low */
+#define ATOM_V_CUTOFF           0x08
+#define ATOM_H_REPLICATIONBY2   0x10
+#define ATOM_V_REPLICATIONBY2   0x20
+#define ATOM_COMPOSITESYNC      0x40
+#define ATOM_INTERLACE          0x80
+#define ATOM_DOUBLE_CLOCK_MODE  0x100
+#define ATOM_RGB888_MODE        0x200
+
+/* usRefreshRate- */
+#define ATOM_REFRESH_43         43
+#define ATOM_REFRESH_47         47
+#define ATOM_REFRESH_56         56
+#define ATOM_REFRESH_60         60
+#define ATOM_REFRESH_65         65
+#define ATOM_REFRESH_70         70
+#define ATOM_REFRESH_72         72
+#define ATOM_REFRESH_75         75
+#define ATOM_REFRESH_85         85
+
+/*  ATOM_MODE_TIMING data are exactly the same as VESA timing data. */
+/*  Translation from EDID to ATOM_MODE_TIMING, use the following formula. */
+/*  */
+/*       VESA_HTOTAL                     =       VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK */
+/*                                               =       EDID_HA + EDID_HBL */
+/*       VESA_HDISP                      =       VESA_ACTIVE     =       EDID_HA */
+/*       VESA_HSYNC_START        =       VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH */
+/*                                               =       EDID_HA + EDID_HSO */
+/*       VESA_HSYNC_WIDTH        =       VESA_HSYNC_TIME =       EDID_HSPW */
+/*       VESA_BORDER                     =       EDID_BORDER */
+
+/****************************************************************************/
+/*  Structure used in SetCRTC_UsingDTDTimingTable */
+/****************************************************************************/
+typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS {
+        USHORT usH_Size;
+        USHORT usH_Blanking_Time;
+        USHORT usV_Size;
+        USHORT usV_Blanking_Time;
+        USHORT usH_SyncOffset;
+        USHORT usH_SyncWidth;
+        USHORT usV_SyncOffset;
+        USHORT usV_SyncWidth;
+        ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
+        UCHAR ucH_Border;       /*  From DFP EDID */
+        UCHAR ucV_Border;
+        UCHAR ucCRTC;           /*  ATOM_CRTC1 or ATOM_CRTC2 */
+        UCHAR ucPadding[3];
+} SET_CRTC_USING_DTD_TIMING_PARAMETERS;
+
+/****************************************************************************/
+/*  Structure used in SetCRTC_TimingTable */
+/****************************************************************************/
+typedef struct _SET_CRTC_TIMING_PARAMETERS {
+        USHORT usH_Total;       /*  horizontal total */
+        USHORT usH_Disp;        /*  horizontal display */
+        USHORT usH_SyncStart;   /*  horozontal Sync start */
+        USHORT usH_SyncWidth;   /*  horizontal Sync width */
+        USHORT usV_Total;       /*  vertical total */
+        USHORT usV_Disp;        /*  vertical display */
+        USHORT usV_SyncStart;   /*  vertical Sync start */
+        USHORT usV_SyncWidth;   /*  vertical Sync width */
+        ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
+        UCHAR ucCRTC;           /*  ATOM_CRTC1 or ATOM_CRTC2 */
+        UCHAR ucOverscanRight;  /*  right */
+        UCHAR ucOverscanLeft;   /*  left */
+        UCHAR ucOverscanBottom; /*  bottom */
+        UCHAR ucOverscanTop;    /*  top */
+        UCHAR ucReserved;
+} SET_CRTC_TIMING_PARAMETERS;
+#define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
+
+/****************************************************************************/
+/*  Structure used in StandardVESA_TimingTable */
+/*                    AnalogTV_InfoTable */
+/*                    ComponentVideoInfoTable */
+/****************************************************************************/
+typedef struct _ATOM_MODE_TIMING {
+        USHORT usCRTC_H_Total;
+        USHORT usCRTC_H_Disp;
+        USHORT usCRTC_H_SyncStart;
+        USHORT usCRTC_H_SyncWidth;
+        USHORT usCRTC_V_Total;
+        USHORT usCRTC_V_Disp;
+        USHORT usCRTC_V_SyncStart;
+        USHORT usCRTC_V_SyncWidth;
+        USHORT usPixelClock;    /* in 10Khz unit */
+        ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
+        USHORT usCRTC_OverscanRight;
+        USHORT usCRTC_OverscanLeft;
+        USHORT usCRTC_OverscanBottom;
+        USHORT usCRTC_OverscanTop;
+        USHORT usReserve;
+        UCHAR ucInternalModeNumber;
+        UCHAR ucRefreshRate;
+} ATOM_MODE_TIMING;
+
+typedef struct _ATOM_DTD_FORMAT {
+        USHORT usPixClk;
+        USHORT usHActive;
+        USHORT usHBlanking_Time;
+        USHORT usVActive;
+        USHORT usVBlanking_Time;
+        USHORT usHSyncOffset;
+        USHORT usHSyncWidth;
+        USHORT usVSyncOffset;
+        USHORT usVSyncWidth;
+        USHORT usImageHSize;
+        USHORT usImageVSize;
+        UCHAR ucHBorder;
+        UCHAR ucVBorder;
+        ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
+        UCHAR ucInternalModeNumber;
+        UCHAR ucRefreshRate;
+} ATOM_DTD_FORMAT;
+
+/****************************************************************************/
+/*  Structure used in LVDS_InfoTable */
+/*   * Need a document to describe this table */
+/****************************************************************************/
+#define SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
+#define SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
+#define SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
+#define SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
+
+/* Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. */
+/* Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL */
+#define LCDPANEL_CAP_READ_EDID                                                                  0x1
+
+/* ucTableFormatRevision=1 */
+/* ucTableContentRevision=1 */
+typedef struct _ATOM_LVDS_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_DTD_FORMAT sLCDTiming;
+        USHORT usModePatchTableOffset;
+        USHORT usSupportedRefreshRate;  /* Refer to panel info table in ATOMBIOS extension Spec. */
+        USHORT usOffDelayInMs;
+        UCHAR ucPowerSequenceDigOntoDEin10Ms;
+        UCHAR ucPowerSequenceDEtoBLOnin10Ms;
+        UCHAR ucLVDS_Misc;      /*  Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} */
+        /*  Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} */
+        /*  Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} */
+        /*  Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} */
+        UCHAR ucPanelDefaultRefreshRate;
+        UCHAR ucPanelIdentification;
+        UCHAR ucSS_Id;
+} ATOM_LVDS_INFO;
+
+/* ucTableFormatRevision=1 */
+/* ucTableContentRevision=2 */
+typedef struct _ATOM_LVDS_INFO_V12 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_DTD_FORMAT sLCDTiming;
+        USHORT usExtInfoTableOffset;
+        USHORT usSupportedRefreshRate;  /* Refer to panel info table in ATOMBIOS extension Spec. */
+        USHORT usOffDelayInMs;
+        UCHAR ucPowerSequenceDigOntoDEin10Ms;
+        UCHAR ucPowerSequenceDEtoBLOnin10Ms;
+        UCHAR ucLVDS_Misc;      /*  Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} */
+        /*  Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} */
+        /*  Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} */
+        /*  Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} */
+        UCHAR ucPanelDefaultRefreshRate;
+        UCHAR ucPanelIdentification;
+        UCHAR ucSS_Id;
+        USHORT usLCDVenderID;
+        USHORT usLCDProductID;
+        UCHAR ucLCDPanel_SpecialHandlingCap;
+        UCHAR ucPanelInfoSize;  /*   start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable */
+        UCHAR ucReserved[2];
+} ATOM_LVDS_INFO_V12;
+
+#define ATOM_LVDS_INFO_LAST  ATOM_LVDS_INFO_V12
+
+typedef struct _ATOM_PATCH_RECORD_MODE {
+        UCHAR ucRecordType;
+        USHORT usHDisp;
+        USHORT usVDisp;
+} ATOM_PATCH_RECORD_MODE;
+
+typedef struct _ATOM_LCD_RTS_RECORD {
+        UCHAR ucRecordType;
+        UCHAR ucRTSValue;
+} ATOM_LCD_RTS_RECORD;
+
+/* !! If the record below exits, it shoud always be the first record for easy use in command table!!! */
+typedef struct _ATOM_LCD_MODE_CONTROL_CAP {
+        UCHAR ucRecordType;
+        USHORT usLCDCap;
+} ATOM_LCD_MODE_CONTROL_CAP;
+
+#define LCD_MODE_CAP_BL_OFF                   1
+#define LCD_MODE_CAP_CRTC_OFF                 2
+#define LCD_MODE_CAP_PANEL_OFF                4
+
+typedef struct _ATOM_FAKE_EDID_PATCH_RECORD {
+        UCHAR ucRecordType;
+        UCHAR ucFakeEDIDLength;
+        UCHAR ucFakeEDIDString[1];      /*  This actually has ucFakeEdidLength elements. */
+} ATOM_FAKE_EDID_PATCH_RECORD;
+
+typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD {
+        UCHAR ucRecordType;
+        USHORT usHSize;
+        USHORT usVSize;
+} ATOM_PANEL_RESOLUTION_PATCH_RECORD;
+
+#define LCD_MODE_PATCH_RECORD_MODE_TYPE       1
+#define LCD_RTS_RECORD_TYPE                   2
+#define LCD_CAP_RECORD_TYPE                   3
+#define LCD_FAKE_EDID_PATCH_RECORD_TYPE       4
+#define LCD_PANEL_RESOLUTION_RECORD_TYPE      5
+#define ATOM_RECORD_END_TYPE                  0xFF
+
+/****************************Spread Spectrum Info Table Definitions **********************/
+
+/* ucTableFormatRevision=1 */
+/* ucTableContentRevision=2 */
+typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT {
+        USHORT usSpreadSpectrumPercentage;
+        UCHAR ucSpreadSpectrumType;     /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */
+        UCHAR ucSS_Step;
+        UCHAR ucSS_Delay;
+        UCHAR ucSS_Id;
+        UCHAR ucRecommandedRef_Div;
+        UCHAR ucSS_Range;       /* it was reserved for V11 */
+} ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
+
+#define ATOM_MAX_SS_ENTRY                      16
+#define ATOM_DP_SS_ID1                                                                                           0x0f1  /*  SS modulation freq=30k */
+#define ATOM_DP_SS_ID2                                                                                           0x0f2  /*  SS modulation freq=33k */
+
+#define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
+#define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
+#define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
+#define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
+#define ATOM_INTERNAL_SS_MASK                  0x00000000
+#define ATOM_EXTERNAL_SS_MASK                  0x00000002
+#define EXEC_SS_STEP_SIZE_SHIFT                2
+#define EXEC_SS_DELAY_SHIFT                    4
+#define ACTIVEDATA_TO_BLON_DELAY_SHIFT         4
+
+typedef struct _ATOM_SPREAD_SPECTRUM_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
+} ATOM_SPREAD_SPECTRUM_INFO;
+
+/****************************************************************************/
+/*  Structure used in AnalogTV_InfoTable (Top level) */
+/****************************************************************************/
+/* ucTVBootUpDefaultStd definiton: */
+
+/* ATOM_TV_NTSC                1 */
+/* ATOM_TV_NTSCJ               2 */
+/* ATOM_TV_PAL                 3 */
+/* ATOM_TV_PALM                4 */
+/* ATOM_TV_PALCN               5 */
+/* ATOM_TV_PALN                6 */
+/* ATOM_TV_PAL60               7 */
+/* ATOM_TV_SECAM               8 */
+
+/* ucTVSuppportedStd definition: */
+#define NTSC_SUPPORT          0x1
+#define NTSCJ_SUPPORT         0x2
+
+#define PAL_SUPPORT           0x4
+#define PALM_SUPPORT          0x8
+#define PALCN_SUPPORT         0x10
+#define PALN_SUPPORT          0x20
+#define PAL60_SUPPORT         0x40
+#define SECAM_SUPPORT         0x80
+
+#define MAX_SUPPORTED_TV_TIMING    2
+
+typedef struct _ATOM_ANALOG_TV_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        UCHAR ucTV_SupportedStandard;
+        UCHAR ucTV_BootUpDefaultStandard;
+        UCHAR ucExt_TV_ASIC_ID;
+        UCHAR ucExt_TV_ASIC_SlaveAddr;
+        /*ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING]; */
+        ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
+} ATOM_ANALOG_TV_INFO;
+
+/**************************************************************************/
+/*  VRAM usage and their defintions */
+
+/*  One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. */
+/*  Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. */
+/*  All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! */
+/*  To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR */
+/*  To Bios:  ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX */
+
+#ifndef VESA_MEMORY_IN_64K_BLOCK
+#define VESA_MEMORY_IN_64K_BLOCK        0x100   /* 256*64K=16Mb (Max. VESA memory is 16Mb!) */
+#endif
+
+#define ATOM_EDID_RAW_DATASIZE          256     /* In Bytes */
+#define ATOM_HWICON_SURFACE_SIZE        4096    /* In Bytes */
+#define ATOM_HWICON_INFOTABLE_SIZE      32
+#define MAX_DTD_MODE_IN_VRAM            6
+#define ATOM_DTD_MODE_SUPPORT_TBL_SIZE  (MAX_DTD_MODE_IN_VRAM*28)       /* 28= (SIZEOF ATOM_DTD_FORMAT) */
+#define ATOM_STD_MODE_SUPPORT_TBL_SIZE  (32*8)  /* 32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) */
+#define DFP_ENCODER_TYPE_OFFSET                                 0x80
+#define DP_ENCODER_LANE_NUM_OFFSET                      0x84
+#define DP_ENCODER_LINK_RATE_OFFSET                     0x88
+
+#define ATOM_HWICON1_SURFACE_ADDR       0
+#define ATOM_HWICON2_SURFACE_ADDR       (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
+#define ATOM_HWICON_INFOTABLE_ADDR      (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
+#define ATOM_CRT1_EDID_ADDR             (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
+#define ATOM_CRT1_DTD_MODE_TBL_ADDR     (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_CRT1_STD_MODE_TBL_ADDR         (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_LCD1_EDID_ADDR             (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_LCD1_DTD_MODE_TBL_ADDR     (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_LCD1_STD_MODE_TBL_ADDR     (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_TV1_DTD_MODE_TBL_ADDR      (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_DFP1_EDID_ADDR             (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_DFP1_DTD_MODE_TBL_ADDR     (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_DFP1_STD_MODE_TBL_ADDR         (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_CRT2_EDID_ADDR             (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_CRT2_DTD_MODE_TBL_ADDR     (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_CRT2_STD_MODE_TBL_ADDR         (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_LCD2_EDID_ADDR             (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_LCD2_DTD_MODE_TBL_ADDR     (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_LCD2_STD_MODE_TBL_ADDR     (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_TV2_EDID_ADDR              (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_TV2_DTD_MODE_TBL_ADDR      (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_TV2_STD_MODE_TBL_ADDR        (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_DFP2_EDID_ADDR             (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_DFP2_DTD_MODE_TBL_ADDR     (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_DFP2_STD_MODE_TBL_ADDR     (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_CV_EDID_ADDR               (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_CV_DTD_MODE_TBL_ADDR       (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_CV_STD_MODE_TBL_ADDR       (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_DFP3_EDID_ADDR             (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_DFP3_DTD_MODE_TBL_ADDR     (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_DFP3_STD_MODE_TBL_ADDR     (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_DFP4_EDID_ADDR             (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_DFP4_DTD_MODE_TBL_ADDR     (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_DFP4_STD_MODE_TBL_ADDR     (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_DFP5_EDID_ADDR             (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+#define ATOM_DFP5_DTD_MODE_TBL_ADDR     (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
+#define ATOM_DFP5_STD_MODE_TBL_ADDR     (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_DP_TRAINING_TBL_ADDR       (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE)
+
+#define ATOM_STACK_STORAGE_START        (ATOM_DP_TRAINING_TBL_ADDR + 256)
+#define ATOM_STACK_STORAGE_END          (ATOM_STACK_STORAGE_START + 512)
+
+/* The size below is in Kb! */
+#define ATOM_VRAM_RESERVE_SIZE         ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
+
+#define ATOM_VRAM_OPERATION_FLAGS_MASK         0xC0000000L
+#define ATOM_VRAM_OPERATION_FLAGS_SHIFT        30
+#define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION   0x1
+#define ATOM_VRAM_BLOCK_NEEDS_RESERVATION      0x0
+
+/***********************************************************************************/
+/*  Structure used in VRAM_UsageByFirmwareTable */
+/*  Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm */
+/*         at running time. */
+/*  note2: From RV770, the memory is more than 32bit addressable, so we will change */
+/*         ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains */
+/*         exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware */
+/*         (in offset to start of memory address) is KB aligned instead of byte aligend. */
+/***********************************************************************************/
+#define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO                       1
+
+typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO {
+        ULONG ulStartAddrUsedByFirmware;
+        USHORT usFirmwareUseInKb;
+        USHORT usReserved;
+} ATOM_FIRMWARE_VRAM_RESERVE_INFO;
+
+typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_FIRMWARE_VRAM_RESERVE_INFO
+            asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
+} ATOM_VRAM_USAGE_BY_FIRMWARE;
+
+/****************************************************************************/
+/*  Structure used in GPIO_Pin_LUTTable */
+/****************************************************************************/
+typedef struct _ATOM_GPIO_PIN_ASSIGNMENT {
+        USHORT usGpioPin_AIndex;
+        UCHAR ucGpioPinBitShift;
+        UCHAR ucGPIO_ID;
+} ATOM_GPIO_PIN_ASSIGNMENT;
+
+typedef struct _ATOM_GPIO_PIN_LUT {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
+} ATOM_GPIO_PIN_LUT;
+
+/****************************************************************************/
+/*  Structure used in ComponentVideoInfoTable */
+/****************************************************************************/
+#define GPIO_PIN_ACTIVE_HIGH          0x1
+
+#define MAX_SUPPORTED_CV_STANDARDS    5
+
+/*  definitions for ATOM_D_INFO.ucSettings */
+#define ATOM_GPIO_SETTINGS_BITSHIFT_MASK  0x1F  /*  [4:0] */
+#define ATOM_GPIO_SETTINGS_RESERVED_MASK  0x60  /*  [6:5] = must be zeroed out */
+#define ATOM_GPIO_SETTINGS_ACTIVE_MASK    0x80  /*  [7] */
+
+typedef struct _ATOM_GPIO_INFO {
+        USHORT usAOffset;
+        UCHAR ucSettings;
+        UCHAR ucReserved;
+} ATOM_GPIO_INFO;
+
+/*  definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) */
+#define ATOM_CV_RESTRICT_FORMAT_SELECTION           0x2
+
+/*  definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i */
+#define ATOM_GPIO_DEFAULT_MODE_EN                   0x80        /* [7]; */
+#define ATOM_GPIO_SETTING_PERMODE_MASK              0x7F        /* [6:0] */
+
+/*  definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode */
+/* Line 3 out put 5V. */
+#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A       0x01        /* represent gpio 3 state for 16:9 */
+#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B       0x02        /* represent gpio 4 state for 16:9 */
+#define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT   0x0
+
+/* Line 3 out put 2.2V */
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04        /* represent gpio 3 state for 4:3 Letter box */
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08        /* represent gpio 4 state for 4:3 Letter box */
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
+
+/* Line 3 out put 0V */
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A        0x10        /* represent gpio 3 state for 4:3 */
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B        0x20        /* represent gpio 4 state for 4:3 */
+#define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT    0x4
+
+#define ATOM_CV_LINE3_ASPECTRATIO_MASK              0x3F        /*  bit [5:0] */
+
+#define ATOM_CV_LINE3_ASPECTRATIO_EXIST             0x80        /* bit 7 */
+
+/* GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. */
+#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A   3     /* bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. */
+#define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B   4     /* bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. */
+
+typedef struct _ATOM_COMPONENT_VIDEO_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usMask_PinRegisterIndex;
+        USHORT usEN_PinRegisterIndex;
+        USHORT usY_PinRegisterIndex;
+        USHORT usA_PinRegisterIndex;
+        UCHAR ucBitShift;
+        UCHAR ucPinActiveState; /* ucPinActiveState: Bit0=1 active high, =0 active low */
+        ATOM_DTD_FORMAT sReserved;      /*  must be zeroed out */
+        UCHAR ucMiscInfo;
+        UCHAR uc480i;
+        UCHAR uc480p;
+        UCHAR uc720p;
+        UCHAR uc1080i;
+        UCHAR ucLetterBoxMode;
+        UCHAR ucReserved[3];
+        UCHAR ucNumOfWbGpioBlocks;      /* For Component video D-Connector support. If zere, NTSC type connector */
+        ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
+        ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
+} ATOM_COMPONENT_VIDEO_INFO;
+
+/* ucTableFormatRevision=2 */
+/* ucTableContentRevision=1 */
+typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        UCHAR ucMiscInfo;
+        UCHAR uc480i;
+        UCHAR uc480p;
+        UCHAR uc720p;
+        UCHAR uc1080i;
+        UCHAR ucReserved;
+        UCHAR ucLetterBoxMode;
+        UCHAR ucNumOfWbGpioBlocks;      /* For Component video D-Connector support. If zere, NTSC type connector */
+        ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
+        ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
+} ATOM_COMPONENT_VIDEO_INFO_V21;
+
+#define ATOM_COMPONENT_VIDEO_INFO_LAST  ATOM_COMPONENT_VIDEO_INFO_V21
+
+/****************************************************************************/
+/*  Structure used in object_InfoTable */
+/****************************************************************************/
+typedef struct _ATOM_OBJECT_HEADER {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usDeviceSupport;
+        USHORT usConnectorObjectTableOffset;
+        USHORT usRouterObjectTableOffset;
+        USHORT usEncoderObjectTableOffset;
+        USHORT usProtectionObjectTableOffset;   /* only available when Protection block is independent. */
+        USHORT usDisplayPathTableOffset;
+} ATOM_OBJECT_HEADER;
+
+typedef struct _ATOM_DISPLAY_OBJECT_PATH {
+        USHORT usDeviceTag;     /* supported device */
+        USHORT usSize;          /* the size of ATOM_DISPLAY_OBJECT_PATH */
+        USHORT usConnObjectId;  /* Connector Object ID */
+        USHORT usGPUObjectId;   /* GPU ID */
+        USHORT usGraphicObjIds[1];      /* 1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. */
+} ATOM_DISPLAY_OBJECT_PATH;
+
+typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE {
+        UCHAR ucNumOfDispPath;
+        UCHAR ucVersion;
+        UCHAR ucPadding[2];
+        ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
+} ATOM_DISPLAY_OBJECT_PATH_TABLE;
+
+typedef struct _ATOM_OBJECT     /* each object has this structure */
+{
+        USHORT usObjectID;
+        USHORT usSrcDstTableOffset;
+        USHORT usRecordOffset;  /* this pointing to a bunch of records defined below */
+        USHORT usReserved;
+} ATOM_OBJECT;
+
+typedef struct _ATOM_OBJECT_TABLE       /* Above 4 object table offset pointing to a bunch of objects all have this structure */
+{
+        UCHAR ucNumberOfObjects;
+        UCHAR ucPadding[3];
+        ATOM_OBJECT asObjects[1];
+} ATOM_OBJECT_TABLE;
+
+typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT       /* usSrcDstTableOffset pointing to this structure */
+{
+        UCHAR ucNumberOfSrc;
+        USHORT usSrcObjectID[1];
+        UCHAR ucNumberOfDst;
+        USHORT usDstObjectID[1];
+} ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
+
+/* Related definitions, all records are differnt but they have a commond header */
+typedef struct _ATOM_COMMON_RECORD_HEADER {
+        UCHAR ucRecordType;     /* An emun to indicate the record type */
+        UCHAR ucRecordSize;     /* The size of the whole record in byte */
+} ATOM_COMMON_RECORD_HEADER;
+
+#define ATOM_I2C_RECORD_TYPE                           1
+#define ATOM_HPD_INT_RECORD_TYPE                       2
+#define ATOM_OUTPUT_PROTECTION_RECORD_TYPE             3
+#define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE          4
+#define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE             5  /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */
+#define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE          6        /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */
+#define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE      7
+#define ATOM_JTAG_RECORD_TYPE                          8        /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */
+#define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE              9
+#define ATOM_ENCODER_DVO_CF_RECORD_TYPE               10
+#define ATOM_CONNECTOR_CF_RECORD_TYPE                 11
+#define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE       12
+#define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE  13
+#define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE                         14
+#define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE                                  15
+
+/* Must be updated when new record type is added,equal to that record definition! */
+#define ATOM_MAX_OBJECT_RECORD_NUMBER             ATOM_CONNECTOR_CF_RECORD_TYPE
+
+typedef struct _ATOM_I2C_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        ATOM_I2C_ID_CONFIG sucI2cId;
+        UCHAR ucI2CAddr;        /* The slave address, it's 0 when the record is attached to connector for DDC */
+} ATOM_I2C_RECORD;
+
+typedef struct _ATOM_HPD_INT_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        UCHAR ucHPDIntGPIOID;   /* Corresponding block in GPIO_PIN_INFO table gives the pin info */
+        UCHAR ucPluggged_PinState;
+} ATOM_HPD_INT_RECORD;
+
+typedef struct _ATOM_OUTPUT_PROTECTION_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        UCHAR ucProtectionFlag;
+        UCHAR ucReserved;
+} ATOM_OUTPUT_PROTECTION_RECORD;
+
+typedef struct _ATOM_CONNECTOR_DEVICE_TAG {
+        ULONG ulACPIDeviceEnum; /* Reserved for now */
+        USHORT usDeviceID;      /* This Id is same as "ATOM_DEVICE_XXX_SUPPORT" */
+        USHORT usPadding;
+} ATOM_CONNECTOR_DEVICE_TAG;
+
+typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        UCHAR ucNumberOfDevice;
+        UCHAR ucReserved;
+        ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1];       /* This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation */
+} ATOM_CONNECTOR_DEVICE_TAG_RECORD;
+
+typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        UCHAR ucConfigGPIOID;
+        UCHAR ucConfigGPIOState;        /* Set to 1 when it's active high to enable external flow in */
+        UCHAR ucFlowinGPIPID;
+        UCHAR ucExtInGPIPID;
+} ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
+
+typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        UCHAR ucCTL1GPIO_ID;
+        UCHAR ucCTL1GPIOState;  /* Set to 1 when it's active high */
+        UCHAR ucCTL2GPIO_ID;
+        UCHAR ucCTL2GPIOState;  /* Set to 1 when it's active high */
+        UCHAR ucCTL3GPIO_ID;
+        UCHAR ucCTL3GPIOState;  /* Set to 1 when it's active high */
+        UCHAR ucCTLFPGA_IN_ID;
+        UCHAR ucPadding[3];
+} ATOM_ENCODER_FPGA_CONTROL_RECORD;
+
+typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        UCHAR ucGPIOID;         /* Corresponding block in GPIO_PIN_INFO table gives the pin info */
+        UCHAR ucTVActiveState;  /* Indicating when the pin==0 or 1 when TV is connected */
+} ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
+
+typedef struct _ATOM_JTAG_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        UCHAR ucTMSGPIO_ID;
+        UCHAR ucTMSGPIOState;   /* Set to 1 when it's active high */
+        UCHAR ucTCKGPIO_ID;
+        UCHAR ucTCKGPIOState;   /* Set to 1 when it's active high */
+        UCHAR ucTDOGPIO_ID;
+        UCHAR ucTDOGPIOState;   /* Set to 1 when it's active high */
+        UCHAR ucTDIGPIO_ID;
+        UCHAR ucTDIGPIOState;   /* Set to 1 when it's active high */
+        UCHAR ucPadding[2];
+} ATOM_JTAG_RECORD;
+
+/* The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually */
+typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR {
+        UCHAR ucGPIOID;         /*  GPIO_ID, find the corresponding ID in GPIO_LUT table */
+        UCHAR ucGPIO_PinState;  /*  Pin state showing how to set-up the pin */
+} ATOM_GPIO_PIN_CONTROL_PAIR;
+
+typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        UCHAR ucFlags;          /*  Future expnadibility */
+        UCHAR ucNumberOfPins;   /*  Number of GPIO pins used to control the object */
+        ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1];   /*  the real gpio pin pair determined by number of pins ucNumberOfPins */
+} ATOM_OBJECT_GPIO_CNTL_RECORD;
+
+/* Definitions for GPIO pin state */
+#define GPIO_PIN_TYPE_INPUT             0x00
+#define GPIO_PIN_TYPE_OUTPUT            0x10
+#define GPIO_PIN_TYPE_HW_CONTROL        0x20
+
+/* For GPIO_PIN_TYPE_OUTPUT the following is defined */
+#define GPIO_PIN_OUTPUT_STATE_MASK      0x01
+#define GPIO_PIN_OUTPUT_STATE_SHIFT     0
+#define GPIO_PIN_STATE_ACTIVE_LOW       0x0
+#define GPIO_PIN_STATE_ACTIVE_HIGH      0x1
+
+typedef struct _ATOM_ENCODER_DVO_CF_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        ULONG ulStrengthControl;        /*  DVOA strength control for CF */
+        UCHAR ucPadding[2];
+} ATOM_ENCODER_DVO_CF_RECORD;
+
+/*  value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle */
+#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA   1
+#define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB   2
+
+typedef struct _ATOM_CONNECTOR_CF_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        USHORT usMaxPixClk;
+        UCHAR ucFlowCntlGpioId;
+        UCHAR ucSwapCntlGpioId;
+        UCHAR ucConnectedDvoBundle;
+        UCHAR ucPadding;
+} ATOM_CONNECTOR_CF_RECORD;
+
+typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        ATOM_DTD_FORMAT asTiming;
+} ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
+
+typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;      /* ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE */
+        UCHAR ucSubConnectorType;       /* CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A */
+        UCHAR ucReserved;
+} ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
+
+typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        UCHAR ucMuxType;        /* decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state */
+        UCHAR ucMuxControlPin;
+        UCHAR ucMuxState[2];    /* for alligment purpose */
+} ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
+
+typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD {
+        ATOM_COMMON_RECORD_HEADER sheader;
+        UCHAR ucMuxType;
+        UCHAR ucMuxControlPin;
+        UCHAR ucMuxState[2];    /* for alligment purpose */
+} ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
+
+/*  define ucMuxType */
+#define ATOM_ROUTER_MUX_PIN_STATE_MASK                                                          0x0f
+#define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT             0x01
+
+/****************************************************************************/
+/*  ASIC voltage data table */
+/****************************************************************************/
+typedef struct _ATOM_VOLTAGE_INFO_HEADER {
+        USHORT usVDDCBaseLevel; /* In number of 50mv unit */
+        USHORT usReserved;      /* For possible extension table offset */
+        UCHAR ucNumOfVoltageEntries;
+        UCHAR ucBytesPerVoltageEntry;
+        UCHAR ucVoltageStep;    /* Indicating in how many mv increament is one step, 0.5mv unit */
+        UCHAR ucDefaultVoltageEntry;
+        UCHAR ucVoltageControlI2cLine;
+        UCHAR ucVoltageControlAddress;
+        UCHAR ucVoltageControlOffset;
+} ATOM_VOLTAGE_INFO_HEADER;
+
+typedef struct _ATOM_VOLTAGE_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_VOLTAGE_INFO_HEADER viHeader;
+        UCHAR ucVoltageEntries[64];     /* 64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry */
+} ATOM_VOLTAGE_INFO;
+
+typedef struct _ATOM_VOLTAGE_FORMULA {
+        USHORT usVoltageBaseLevel;      /*  In number of 1mv unit */
+        USHORT usVoltageStep;   /*  Indicating in how many mv increament is one step, 1mv unit */
+        UCHAR ucNumOfVoltageEntries;    /*  Number of Voltage Entry, which indicate max Voltage */
+        UCHAR ucFlag;           /*  bit0=0 :step is 1mv =1 0.5mv */
+        UCHAR ucBaseVID;        /*  if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep */
+        UCHAR ucReserved;
+        UCHAR ucVIDAdjustEntries[32];   /*  32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries */
+} ATOM_VOLTAGE_FORMULA;
+
+typedef struct _ATOM_VOLTAGE_CONTROL {
+        UCHAR ucVoltageControlId;       /* Indicate it is controlled by I2C or GPIO or HW state machine */
+        UCHAR ucVoltageControlI2cLine;
+        UCHAR ucVoltageControlAddress;
+        UCHAR ucVoltageControlOffset;
+        USHORT usGpioPin_AIndex;        /* GPIO_PAD register index */
+        UCHAR ucGpioPinBitShift[9];     /* at most 8 pin support 255 VIDs, termintate with 0xff */
+        UCHAR ucReserved;
+} ATOM_VOLTAGE_CONTROL;
+
+/*  Define ucVoltageControlId */
+#define VOLTAGE_CONTROLLED_BY_HW                                                        0x00
+#define VOLTAGE_CONTROLLED_BY_I2C_MASK                          0x7F
+#define VOLTAGE_CONTROLLED_BY_GPIO                                              0x80
+#define VOLTAGE_CONTROL_ID_LM64                                                         0x01    /* I2C control, used for R5xx Core Voltage */
+#define VOLTAGE_CONTROL_ID_DAC                                                          0x02    /* I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI */
+#define VOLTAGE_CONTROL_ID_VT116xM                                              0x03    /* I2C control, used for R6xx Core Voltage */
+#define VOLTAGE_CONTROL_ID_DS4402                                                       0x04
+
+typedef struct _ATOM_VOLTAGE_OBJECT {
+        UCHAR ucVoltageType;    /* Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI */
+        UCHAR ucSize;           /* Size of Object */
+        ATOM_VOLTAGE_CONTROL asControl; /* describ how to control */
+        ATOM_VOLTAGE_FORMULA asFormula; /* Indicate How to convert real Voltage to VID */
+} ATOM_VOLTAGE_OBJECT;
+
+typedef struct _ATOM_VOLTAGE_OBJECT_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_VOLTAGE_OBJECT asVoltageObj[3];    /* Info for Voltage control */
+} ATOM_VOLTAGE_OBJECT_INFO;
+
+typedef struct _ATOM_LEAKID_VOLTAGE {
+        UCHAR ucLeakageId;
+        UCHAR ucReserved;
+        USHORT usVoltage;
+} ATOM_LEAKID_VOLTAGE;
+
+typedef struct _ATOM_ASIC_PROFILE_VOLTAGE {
+        UCHAR ucProfileId;
+        UCHAR ucReserved;
+        USHORT usSize;
+        USHORT usEfuseSpareStartAddr;
+        USHORT usFuseIndex[8];  /* from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, */
+        ATOM_LEAKID_VOLTAGE asLeakVol[2];       /* Leakid and relatd voltage */
+} ATOM_ASIC_PROFILE_VOLTAGE;
+
+/* ucProfileId */
+#define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE                      1
+#define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE                  1
+#define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE                                      2
+
+typedef struct _ATOM_ASIC_PROFILING_INFO {
+        ATOM_COMMON_TABLE_HEADER asHeader;
+        ATOM_ASIC_PROFILE_VOLTAGE asVoltage;
+} ATOM_ASIC_PROFILING_INFO;
+
+typedef struct _ATOM_POWER_SOURCE_OBJECT {
+        UCHAR ucPwrSrcId;       /*  Power source */
+        UCHAR ucPwrSensorType;  /*  GPIO, I2C or none */
+        UCHAR ucPwrSensId;      /*  if GPIO detect, it is GPIO id,  if I2C detect, it is I2C id */
+        UCHAR ucPwrSensSlaveAddr;       /*  Slave address if I2C detect */
+        UCHAR ucPwrSensRegIndex;        /*  I2C register Index if I2C detect */
+        UCHAR ucPwrSensRegBitMask;      /*  detect which bit is used if I2C detect */
+        UCHAR ucPwrSensActiveState;     /*  high active or low active */
+        UCHAR ucReserve[3];     /*  reserve */
+        USHORT usSensPwr;       /*  in unit of watt */
+} ATOM_POWER_SOURCE_OBJECT;
+
+typedef struct _ATOM_POWER_SOURCE_INFO {
+        ATOM_COMMON_TABLE_HEADER asHeader;
+        UCHAR asPwrbehave[16];
+        ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
+} ATOM_POWER_SOURCE_INFO;
+
+/* Define ucPwrSrcId */
+#define POWERSOURCE_PCIE_ID1                                            0x00
+#define POWERSOURCE_6PIN_CONNECTOR_ID1  0x01
+#define POWERSOURCE_8PIN_CONNECTOR_ID1  0x02
+#define POWERSOURCE_6PIN_CONNECTOR_ID2  0x04
+#define POWERSOURCE_8PIN_CONNECTOR_ID2  0x08
+
+/* define ucPwrSensorId */
+#define POWER_SENSOR_ALWAYS                                                     0x00
+#define POWER_SENSOR_GPIO                                                               0x01
+#define POWER_SENSOR_I2C                                                                0x02
+
+/**************************************************************************/
+/*  This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design */
+/* Memory SS Info Table */
+/* Define Memory Clock SS chip ID */
+#define ICS91719  1
+#define ICS91720  2
+
+/* Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol */
+typedef struct _ATOM_I2C_DATA_RECORD {
+        UCHAR ucNunberOfBytes;  /* Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" */
+        UCHAR ucI2CData[1];     /* I2C data in bytes, should be less than 16 bytes usually */
+} ATOM_I2C_DATA_RECORD;
+
+/* Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information */
+typedef struct _ATOM_I2C_DEVICE_SETUP_INFO {
+        ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;     /* I2C line and HW/SW assisted cap. */
+        UCHAR ucSSChipID;       /* SS chip being used */
+        UCHAR ucSSChipSlaveAddr;        /* Slave Address to set up this SS chip */
+        UCHAR ucNumOfI2CDataRecords;    /* number of data block */
+        ATOM_I2C_DATA_RECORD asI2CData[1];
+} ATOM_I2C_DEVICE_SETUP_INFO;
+
+/* ========================================================================================== */
+typedef struct _ATOM_ASIC_MVDD_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
+} ATOM_ASIC_MVDD_INFO;
+
+/* ========================================================================================== */
+#define ATOM_MCLK_SS_INFO         ATOM_ASIC_MVDD_INFO
+
+/* ========================================================================================== */
+/**************************************************************************/
+
+typedef struct _ATOM_ASIC_SS_ASSIGNMENT {
+        ULONG ulTargetClockRange;       /* Clock Out frequence (VCO ), in unit of 10Khz */
+        USHORT usSpreadSpectrumPercentage;      /* in unit of 0.01% */
+        USHORT usSpreadRateInKhz;       /* in unit of kHz, modulation freq */
+        UCHAR ucClockIndication;        /* Indicate which clock source needs SS */
+        UCHAR ucSpreadSpectrumMode;     /* Bit1=0 Down Spread,=1 Center Spread. */
+        UCHAR ucReserved[2];
+} ATOM_ASIC_SS_ASSIGNMENT;
+
+/* Define ucSpreadSpectrumType */
+#define ASIC_INTERNAL_MEMORY_SS                 1
+#define ASIC_INTERNAL_ENGINE_SS                 2
+#define ASIC_INTERNAL_UVD_SS                            3
+
+typedef struct _ATOM_ASIC_INTERNAL_SS_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
+} ATOM_ASIC_INTERNAL_SS_INFO;
+
+/* ==============================Scratch Pad Definition Portion=============================== */
+#define ATOM_DEVICE_CONNECT_INFO_DEF  0
+#define ATOM_ROM_LOCATION_DEF         1
+#define ATOM_TV_STANDARD_DEF          2
+#define ATOM_ACTIVE_INFO_DEF          3
+#define ATOM_LCD_INFO_DEF             4
+#define ATOM_DOS_REQ_INFO_DEF         5
+#define ATOM_ACC_CHANGE_INFO_DEF      6
+#define ATOM_DOS_MODE_INFO_DEF        7
+#define ATOM_I2C_CHANNEL_STATUS_DEF   8
+#define ATOM_I2C_CHANNEL_STATUS1_DEF  9
+
+/*  BIOS_0_SCRATCH Definition */
+#define ATOM_S0_CRT1_MONO               0x00000001L
+#define ATOM_S0_CRT1_COLOR              0x00000002L
+#define ATOM_S0_CRT1_MASK               (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
+
+#define ATOM_S0_TV1_COMPOSITE_A         0x00000004L
+#define ATOM_S0_TV1_SVIDEO_A            0x00000008L
+#define ATOM_S0_TV1_MASK_A              (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
+
+#define ATOM_S0_CV_A                    0x00000010L
+#define ATOM_S0_CV_DIN_A                0x00000020L
+#define ATOM_S0_CV_MASK_A               (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
+
+#define ATOM_S0_CRT2_MONO               0x00000100L
+#define ATOM_S0_CRT2_COLOR              0x00000200L
+#define ATOM_S0_CRT2_MASK               (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
+
+#define ATOM_S0_TV1_COMPOSITE           0x00000400L
+#define ATOM_S0_TV1_SVIDEO              0x00000800L
+#define ATOM_S0_TV1_SCART               0x00004000L
+#define ATOM_S0_TV1_MASK                (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
+
+#define ATOM_S0_CV                      0x00001000L
+#define ATOM_S0_CV_DIN                  0x00002000L
+#define ATOM_S0_CV_MASK                 (ATOM_S0_CV+ATOM_S0_CV_DIN)
+
+#define ATOM_S0_DFP1                    0x00010000L
+#define ATOM_S0_DFP2                    0x00020000L
+#define ATOM_S0_LCD1                    0x00040000L
+#define ATOM_S0_LCD2                    0x00080000L
+#define ATOM_S0_TV2                     0x00100000L
+#define ATOM_S0_DFP3                    0x00200000L
+#define ATOM_S0_DFP4                    0x00400000L
+#define ATOM_S0_DFP5                    0x00800000L
+
+#define ATOM_S0_DFP_MASK \
+        (ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5)
+
+#define ATOM_S0_FAD_REGISTER_BUG        0x02000000L     /*  If set, indicates we are running a PCIE asic with */
+                                                    /*  the FAD/HDP reg access bug.  Bit is read by DAL */
+
+#define ATOM_S0_THERMAL_STATE_MASK      0x1C000000L
+#define ATOM_S0_THERMAL_STATE_SHIFT     26
+
+#define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
+#define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
+
+#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC     1
+#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC     2
+#define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
+
+/* Byte aligned defintion for BIOS usage */
+#define ATOM_S0_CRT1_MONOb0             0x01
+#define ATOM_S0_CRT1_COLORb0            0x02
+#define ATOM_S0_CRT1_MASKb0             (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
+
+#define ATOM_S0_TV1_COMPOSITEb0         0x04
+#define ATOM_S0_TV1_SVIDEOb0            0x08
+#define ATOM_S0_TV1_MASKb0              (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
+
+#define ATOM_S0_CVb0                    0x10
+#define ATOM_S0_CV_DINb0                0x20
+#define ATOM_S0_CV_MASKb0               (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
+
+#define ATOM_S0_CRT2_MONOb1             0x01
+#define ATOM_S0_CRT2_COLORb1            0x02
+#define ATOM_S0_CRT2_MASKb1             (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
+
+#define ATOM_S0_TV1_COMPOSITEb1         0x04
+#define ATOM_S0_TV1_SVIDEOb1            0x08
+#define ATOM_S0_TV1_SCARTb1             0x40
+#define ATOM_S0_TV1_MASKb1              (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
+
+#define ATOM_S0_CVb1                    0x10
+#define ATOM_S0_CV_DINb1                0x20
+#define ATOM_S0_CV_MASKb1               (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
+
+#define ATOM_S0_DFP1b2                  0x01
+#define ATOM_S0_DFP2b2                  0x02
+#define ATOM_S0_LCD1b2                  0x04
+#define ATOM_S0_LCD2b2                  0x08
+#define ATOM_S0_TV2b2                   0x10
+#define ATOM_S0_DFP3b2                                                                  0x20
+
+#define ATOM_S0_THERMAL_STATE_MASKb3    0x1C
+#define ATOM_S0_THERMAL_STATE_SHIFTb3   2
+
+#define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
+#define ATOM_S0_LCD1_SHIFT              18
+
+/*  BIOS_1_SCRATCH Definition */
+#define ATOM_S1_ROM_LOCATION_MASK       0x0000FFFFL
+#define ATOM_S1_PCI_BUS_DEV_MASK        0xFFFF0000L
+
+/*       BIOS_2_SCRATCH Definition */
+#define ATOM_S2_TV1_STANDARD_MASK       0x0000000FL
+#define ATOM_S2_CURRENT_BL_LEVEL_MASK   0x0000FF00L
+#define ATOM_S2_CURRENT_BL_LEVEL_SHIFT  8
+
+#define ATOM_S2_CRT1_DPMS_STATE         0x00010000L
+#define ATOM_S2_LCD1_DPMS_STATE         0x00020000L
+#define ATOM_S2_TV1_DPMS_STATE          0x00040000L
+#define ATOM_S2_DFP1_DPMS_STATE         0x00080000L
+#define ATOM_S2_CRT2_DPMS_STATE         0x00100000L
+#define ATOM_S2_LCD2_DPMS_STATE         0x00200000L
+#define ATOM_S2_TV2_DPMS_STATE          0x00400000L
+#define ATOM_S2_DFP2_DPMS_STATE         0x00800000L
+#define ATOM_S2_CV_DPMS_STATE           0x01000000L
+#define ATOM_S2_DFP3_DPMS_STATE                                 0x02000000L
+#define ATOM_S2_DFP4_DPMS_STATE                                 0x04000000L
+#define ATOM_S2_DFP5_DPMS_STATE                                 0x08000000L
+
+#define ATOM_S2_DFP_DPM_STATE \
+        (ATOM_S2_DFP1_DPMS_STATE | ATOM_S2_DFP2_DPMS_STATE | \
+         ATOM_S2_DFP3_DPMS_STATE | ATOM_S2_DFP4_DPMS_STATE | \
+         ATOM_S2_DFP5_DPMS_STATE)
+
+#define ATOM_S2_DEVICE_DPMS_STATE \
+        (ATOM_S2_CRT1_DPMS_STATE + ATOM_S2_LCD1_DPMS_STATE + \
+         ATOM_S2_TV1_DPMS_STATE + ATOM_S2_DFP_DPMS_STATE + \
+         ATOM_S2_CRT2_DPMS_STATE + ATOM_S2_LCD2_DPMS_STATE + \
+         ATOM_S2_TV2_DPMS_STATE + ATOM_S2_CV_DPMS_STATE)
+
+#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK       0x0C000000L
+#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
+#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE     0x10000000L
+
+#define ATOM_S2_VRI_BRIGHT_ENABLE       0x20000000L
+
+#define ATOM_S2_DISPLAY_ROTATION_0_DEGREE     0x0
+#define ATOM_S2_DISPLAY_ROTATION_90_DEGREE    0x1
+#define ATOM_S2_DISPLAY_ROTATION_180_DEGREE   0x2
+#define ATOM_S2_DISPLAY_ROTATION_270_DEGREE   0x3
+#define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
+#define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK   0xC0000000L
+
+/* Byte aligned defintion for BIOS usage */
+#define ATOM_S2_TV1_STANDARD_MASKb0     0x0F
+#define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
+#define ATOM_S2_CRT1_DPMS_STATEb2       0x01
+#define ATOM_S2_LCD1_DPMS_STATEb2       0x02
+#define ATOM_S2_TV1_DPMS_STATEb2        0x04
+#define ATOM_S2_DFP1_DPMS_STATEb2       0x08
+#define ATOM_S2_CRT2_DPMS_STATEb2       0x10
+#define ATOM_S2_LCD2_DPMS_STATEb2       0x20
+#define ATOM_S2_TV2_DPMS_STATEb2        0x40
+#define ATOM_S2_DFP2_DPMS_STATEb2       0x80
+#define ATOM_S2_CV_DPMS_STATEb3         0x01
+#define ATOM_S2_DFP3_DPMS_STATEb3                               0x02
+#define ATOM_S2_DFP4_DPMS_STATEb3                               0x04
+#define ATOM_S2_DFP5_DPMS_STATEb3                               0x08
+
+#define ATOM_S2_DEVICE_DPMS_MASKw1      0x3FF
+#define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3     0x0C
+#define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3   0x10
+#define ATOM_S2_VRI_BRIGHT_ENABLEb3     0x20
+#define ATOM_S2_ROTATION_STATE_MASKb3   0xC0
+
+/*  BIOS_3_SCRATCH Definition */
+#define ATOM_S3_CRT1_ACTIVE             0x00000001L
+#define ATOM_S3_LCD1_ACTIVE             0x00000002L
+#define ATOM_S3_TV1_ACTIVE              0x00000004L
+#define ATOM_S3_DFP1_ACTIVE             0x00000008L
+#define ATOM_S3_CRT2_ACTIVE             0x00000010L
+#define ATOM_S3_LCD2_ACTIVE             0x00000020L
+#define ATOM_S3_TV2_ACTIVE              0x00000040L
+#define ATOM_S3_DFP2_ACTIVE             0x00000080L
+#define ATOM_S3_CV_ACTIVE               0x00000100L
+#define ATOM_S3_DFP3_ACTIVE                                                     0x00000200L
+#define ATOM_S3_DFP4_ACTIVE                                                     0x00000400L
+#define ATOM_S3_DFP5_ACTIVE                                                     0x00000800L
+
+#define ATOM_S3_DEVICE_ACTIVE_MASK      0x000003FFL
+
+#define ATOM_S3_LCD_FULLEXPANSION_ACTIVE         0x00001000L
+#define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
+
+#define ATOM_S3_CRT1_CRTC_ACTIVE        0x00010000L
+#define ATOM_S3_LCD1_CRTC_ACTIVE        0x00020000L
+#define ATOM_S3_TV1_CRTC_ACTIVE         0x00040000L
+#define ATOM_S3_DFP1_CRTC_ACTIVE        0x00080000L
+#define ATOM_S3_CRT2_CRTC_ACTIVE        0x00100000L
+#define ATOM_S3_LCD2_CRTC_ACTIVE        0x00200000L
+#define ATOM_S3_TV2_CRTC_ACTIVE         0x00400000L
+#define ATOM_S3_DFP2_CRTC_ACTIVE        0x00800000L
+#define ATOM_S3_CV_CRTC_ACTIVE          0x01000000L
+#define ATOM_S3_DFP3_CRTC_ACTIVE                                0x02000000L
+#define ATOM_S3_DFP4_CRTC_ACTIVE                                0x04000000L
+#define ATOM_S3_DFP5_CRTC_ACTIVE                                0x08000000L
+
+#define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
+#define ATOM_S3_ASIC_GUI_ENGINE_HUNG    0x20000000L
+#define ATOM_S3_ALLOW_FAST_PWR_SWITCH   0x40000000L
+#define ATOM_S3_RQST_GPU_USE_MIN_PWR    0x80000000L
+
+/* Byte aligned defintion for BIOS usage */
+#define ATOM_S3_CRT1_ACTIVEb0           0x01
+#define ATOM_S3_LCD1_ACTIVEb0           0x02
+#define ATOM_S3_TV1_ACTIVEb0            0x04
+#define ATOM_S3_DFP1_ACTIVEb0           0x08
+#define ATOM_S3_CRT2_ACTIVEb0           0x10
+#define ATOM_S3_LCD2_ACTIVEb0           0x20
+#define ATOM_S3_TV2_ACTIVEb0            0x40
+#define ATOM_S3_DFP2_ACTIVEb0           0x80
+#define ATOM_S3_CV_ACTIVEb1             0x01
+#define ATOM_S3_DFP3_ACTIVEb1                                           0x02
+#define ATOM_S3_DFP4_ACTIVEb1                                           0x04
+#define ATOM_S3_DFP5_ACTIVEb1                                           0x08
+
+#define ATOM_S3_ACTIVE_CRTC1w0          0xFFF
+
+#define ATOM_S3_CRT1_CRTC_ACTIVEb2      0x01
+#define ATOM_S3_LCD1_CRTC_ACTIVEb2      0x02
+#define ATOM_S3_TV1_CRTC_ACTIVEb2       0x04
+#define ATOM_S3_DFP1_CRTC_ACTIVEb2      0x08
+#define ATOM_S3_CRT2_CRTC_ACTIVEb2      0x10
+#define ATOM_S3_LCD2_CRTC_ACTIVEb2      0x20
+#define ATOM_S3_TV2_CRTC_ACTIVEb2       0x40
+#define ATOM_S3_DFP2_CRTC_ACTIVEb2      0x80
+#define ATOM_S3_CV_CRTC_ACTIVEb3        0x01
+#define ATOM_S3_DFP3_CRTC_ACTIVEb3                      0x02
+#define ATOM_S3_DFP4_CRTC_ACTIVEb3                      0x04
+#define ATOM_S3_DFP5_CRTC_ACTIVEb3                      0x08
+
+#define ATOM_S3_ACTIVE_CRTC2w1          0xFFF
+
+#define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3  0x20
+#define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
+#define ATOM_S3_RQST_GPU_USE_MIN_PWRb3  0x80
+
+/*  BIOS_4_SCRATCH Definition */
+#define ATOM_S4_LCD1_PANEL_ID_MASK      0x000000FFL
+#define ATOM_S4_LCD1_REFRESH_MASK       0x0000FF00L
+#define ATOM_S4_LCD1_REFRESH_SHIFT      8
+
+/* Byte aligned defintion for BIOS usage */
+#define ATOM_S4_LCD1_PANEL_ID_MASKb0      0x0FF
+#define ATOM_S4_LCD1_REFRESH_MASKb1               ATOM_S4_LCD1_PANEL_ID_MASKb0
+#define ATOM_S4_VRAM_INFO_MASKb2        ATOM_S4_LCD1_PANEL_ID_MASKb0
+
+/*  BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! */
+#define ATOM_S5_DOS_REQ_CRT1b0          0x01
+#define ATOM_S5_DOS_REQ_LCD1b0          0x02
+#define ATOM_S5_DOS_REQ_TV1b0           0x04
+#define ATOM_S5_DOS_REQ_DFP1b0          0x08
+#define ATOM_S5_DOS_REQ_CRT2b0          0x10
+#define ATOM_S5_DOS_REQ_LCD2b0          0x20
+#define ATOM_S5_DOS_REQ_TV2b0           0x40
+#define ATOM_S5_DOS_REQ_DFP2b0          0x80
+#define ATOM_S5_DOS_REQ_CVb1            0x01
+#define ATOM_S5_DOS_REQ_DFP3b1                                  0x02
+#define ATOM_S5_DOS_REQ_DFP4b1                                  0x04
+#define ATOM_S5_DOS_REQ_DFP5b1                                  0x08
+
+#define ATOM_S5_DOS_REQ_DEVICEw0        0x03FF
+
+#define ATOM_S5_DOS_REQ_CRT1            0x0001
+#define ATOM_S5_DOS_REQ_LCD1            0x0002
+#define ATOM_S5_DOS_REQ_TV1             0x0004
+#define ATOM_S5_DOS_REQ_DFP1            0x0008
+#define ATOM_S5_DOS_REQ_CRT2            0x0010
+#define ATOM_S5_DOS_REQ_LCD2            0x0020
+#define ATOM_S5_DOS_REQ_TV2             0x0040
+#define ATOM_S5_DOS_REQ_DFP2            0x0080
+#define ATOM_S5_DOS_REQ_CV              0x0100
+#define ATOM_S5_DOS_REQ_DFP3                                            0x0200
+#define ATOM_S5_DOS_REQ_DFP4                                            0x0400
+#define ATOM_S5_DOS_REQ_DFP5                                            0x0800
+
+#define ATOM_S5_DOS_FORCE_CRT1b2        ATOM_S5_DOS_REQ_CRT1b0
+#define ATOM_S5_DOS_FORCE_TV1b2         ATOM_S5_DOS_REQ_TV1b0
+#define ATOM_S5_DOS_FORCE_CRT2b2        ATOM_S5_DOS_REQ_CRT2b0
+#define ATOM_S5_DOS_FORCE_CVb3          ATOM_S5_DOS_REQ_CVb1
+#define ATOM_S5_DOS_FORCE_DEVICEw1 \
+        (ATOM_S5_DOS_FORCE_CRT1b2 + ATOM_S5_DOS_FORCE_TV1b2 + \
+         ATOM_S5_DOS_FORCE_CRT2b2 + (ATOM_S5_DOS_FORCE_CVb3 << 8))
+
+/*  BIOS_6_SCRATCH Definition */
+#define ATOM_S6_DEVICE_CHANGE           0x00000001L
+#define ATOM_S6_SCALER_CHANGE           0x00000002L
+#define ATOM_S6_LID_CHANGE              0x00000004L
+#define ATOM_S6_DOCKING_CHANGE          0x00000008L
+#define ATOM_S6_ACC_MODE                0x00000010L
+#define ATOM_S6_EXT_DESKTOP_MODE        0x00000020L
+#define ATOM_S6_LID_STATE               0x00000040L
+#define ATOM_S6_DOCK_STATE              0x00000080L
+#define ATOM_S6_CRITICAL_STATE          0x00000100L
+#define ATOM_S6_HW_I2C_BUSY_STATE       0x00000200L
+#define ATOM_S6_THERMAL_STATE_CHANGE    0x00000400L
+#define ATOM_S6_INTERRUPT_SET_BY_BIOS   0x00000800L
+#define ATOM_S6_REQ_LCD_EXPANSION_FULL         0x00001000L      /* Normal expansion Request bit for LCD */
+#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO  0x00002000L      /* Aspect ratio expansion Request bit for LCD */
+
+#define ATOM_S6_DISPLAY_STATE_CHANGE    0x00004000L     /* This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion */
+#define ATOM_S6_I2C_STATE_CHANGE        0x00008000L     /* This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion */
+
+#define ATOM_S6_ACC_REQ_CRT1            0x00010000L
+#define ATOM_S6_ACC_REQ_LCD1            0x00020000L
+#define ATOM_S6_ACC_REQ_TV1             0x00040000L
+#define ATOM_S6_ACC_REQ_DFP1            0x00080000L
+#define ATOM_S6_ACC_REQ_CRT2            0x00100000L
+#define ATOM_S6_ACC_REQ_LCD2            0x00200000L
+#define ATOM_S6_ACC_REQ_TV2             0x00400000L
+#define ATOM_S6_ACC_REQ_DFP2            0x00800000L
+#define ATOM_S6_ACC_REQ_CV              0x01000000L
+#define ATOM_S6_ACC_REQ_DFP3                                            0x02000000L
+#define ATOM_S6_ACC_REQ_DFP4                                            0x04000000L
+#define ATOM_S6_ACC_REQ_DFP5                                            0x08000000L
+
+#define ATOM_S6_ACC_REQ_MASK                0x0FFF0000L
+#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE    0x10000000L
+#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH    0x20000000L
+#define ATOM_S6_VRI_BRIGHTNESS_CHANGE       0x40000000L
+#define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK  0x80000000L
+
+/* Byte aligned defintion for BIOS usage */
+#define ATOM_S6_DEVICE_CHANGEb0         0x01
+#define ATOM_S6_SCALER_CHANGEb0         0x02
+#define ATOM_S6_LID_CHANGEb0            0x04
+#define ATOM_S6_DOCKING_CHANGEb0        0x08
+#define ATOM_S6_ACC_MODEb0              0x10
+#define ATOM_S6_EXT_DESKTOP_MODEb0      0x20
+#define ATOM_S6_LID_STATEb0             0x40
+#define ATOM_S6_DOCK_STATEb0            0x80
+#define ATOM_S6_CRITICAL_STATEb1        0x01
+#define ATOM_S6_HW_I2C_BUSY_STATEb1     0x02
+#define ATOM_S6_THERMAL_STATE_CHANGEb1  0x04
+#define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
+#define ATOM_S6_REQ_LCD_EXPANSION_FULLb1        0x10
+#define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
+
+#define ATOM_S6_ACC_REQ_CRT1b2          0x01
+#define ATOM_S6_ACC_REQ_LCD1b2          0x02
+#define ATOM_S6_ACC_REQ_TV1b2           0x04
+#define ATOM_S6_ACC_REQ_DFP1b2          0x08
+#define ATOM_S6_ACC_REQ_CRT2b2          0x10
+#define ATOM_S6_ACC_REQ_LCD2b2          0x20
+#define ATOM_S6_ACC_REQ_TV2b2           0x40
+#define ATOM_S6_ACC_REQ_DFP2b2          0x80
+#define ATOM_S6_ACC_REQ_CVb3            0x01
+#define ATOM_S6_ACC_REQ_DFP3b3                                  0x02
+#define ATOM_S6_ACC_REQ_DFP4b3                                  0x04
+#define ATOM_S6_ACC_REQ_DFP5b3                                  0x08
+
+#define ATOM_S6_ACC_REQ_DEVICEw1        ATOM_S5_DOS_REQ_DEVICEw0
+#define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
+#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
+#define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3    0x40
+#define ATOM_S6_CONFIG_DISPLAY_CHANGEb3    0x80
+
+#define ATOM_S6_DEVICE_CHANGE_SHIFT             0
+#define ATOM_S6_SCALER_CHANGE_SHIFT             1
+#define ATOM_S6_LID_CHANGE_SHIFT                2
+#define ATOM_S6_DOCKING_CHANGE_SHIFT            3
+#define ATOM_S6_ACC_MODE_SHIFT                  4
+#define ATOM_S6_EXT_DESKTOP_MODE_SHIFT          5
+#define ATOM_S6_LID_STATE_SHIFT                 6
+#define ATOM_S6_DOCK_STATE_SHIFT                7
+#define ATOM_S6_CRITICAL_STATE_SHIFT            8
+#define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT         9
+#define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT      10
+#define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT     11
+#define ATOM_S6_REQ_SCALER_SHIFT                12
+#define ATOM_S6_REQ_SCALER_ARATIO_SHIFT         13
+#define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT      14
+#define ATOM_S6_I2C_STATE_CHANGE_SHIFT          15
+#define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT  28
+#define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT  29
+#define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT     30
+#define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT     31
+
+/*  BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! */
+#define ATOM_S7_DOS_MODE_TYPEb0             0x03
+#define ATOM_S7_DOS_MODE_VGAb0              0x00
+#define ATOM_S7_DOS_MODE_VESAb0             0x01
+#define ATOM_S7_DOS_MODE_EXTb0              0x02
+#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0      0x0C
+#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0     0xF0
+#define ATOM_S7_DOS_8BIT_DAC_ENb1           0x01
+#define ATOM_S7_DOS_MODE_NUMBERw1           0x0FFFF
+
+#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT       8
+
+/*  BIOS_8_SCRATCH Definition */
+#define ATOM_S8_I2C_CHANNEL_BUSY_MASK       0x00000FFFF
+#define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK     0x0FFFF0000
+
+#define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT      0
+#define ATOM_S8_I2C_ENGINE_BUSY_SHIFT       16
+
+/*  BIOS_9_SCRATCH Definition */
+#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
+#define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK  0x0000FFFF
+#endif
+#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
+#define ATOM_S9_I2C_CHANNEL_ABORTED_MASK    0xFFFF0000
+#endif
+#ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
+#define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
+#endif
+#ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
+#define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT   16
+#endif
+
+#define ATOM_FLAG_SET                         0x20
+#define ATOM_FLAG_CLEAR                       0
+#define CLEAR_ATOM_S6_ACC_MODE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
+#define SET_ATOM_S6_DEVICE_CHANGE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_SCALER_CHANGE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_LID_CHANGE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
+
+#define SET_ATOM_S6_LID_STATE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) |\
+         ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
+#define CLEAR_ATOM_S6_LID_STATE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
+
+#define SET_ATOM_S6_DOCK_CHANGE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8)| \
+         ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_DOCK_STATE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
+#define CLEAR_ATOM_S6_DOCK_STATE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
+
+#define SET_ATOM_S6_THERMAL_STATE_CHANGE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
+
+#define SET_ATOM_S6_CRITICAL_STATE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
+#define CLEAR_ATOM_S6_CRITICAL_STATE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
+
+#define SET_ATOM_S6_REQ_SCALER \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
+#define CLEAR_ATOM_S6_REQ_SCALER \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
+
+#define SET_ATOM_S6_REQ_SCALER_ARATIO \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
+#define CLEAR_ATOM_S6_REQ_SCALER_ARATIO \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
+
+#define SET_ATOM_S6_I2C_STATE_CHANGE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
+
+#define SET_ATOM_S6_DISPLAY_STATE_CHANGE \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
+
+#define SET_ATOM_S6_DEVICE_RECONFIG \
+        ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \
+         ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
+#define CLEAR_ATOM_S0_LCD1 \
+        ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 ) | \
+         ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
+#define SET_ATOM_S7_DOS_8BIT_DAC_EN \
+        ((ATOM_DOS_MODE_INFO_DEF << 8) | \
+         ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
+#define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN \
+        ((ATOM_DOS_MODE_INFO_DEF << 8) | \
+         ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
+
+/****************************************************************************/
+/* Portion II: Definitinos only used in Driver */
+/****************************************************************************/
+
+/*  Macros used by driver */
+
+#define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char *)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES *)0)->FieldName)-(char *)0)/sizeof(USHORT))
+
+#define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
+#define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
+
+#define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
+#define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
+
+/****************************************************************************/
+/* Portion III: Definitinos only used in VBIOS */
+/****************************************************************************/
+#define ATOM_DAC_SRC                                    0x80
+#define ATOM_SRC_DAC1                                   0
+#define ATOM_SRC_DAC2                                   0x80
+
+#ifdef  UEFI_BUILD
+#define USHORT  UTEMP
+#endif
+
+typedef struct _MEMORY_PLLINIT_PARAMETERS {
+        ULONG ulTargetMemoryClock;      /* In 10Khz unit */
+        UCHAR ucAction;         /* not define yet */
+        UCHAR ucFbDiv_Hi;       /* Fbdiv Hi byte */
+        UCHAR ucFbDiv;          /* FB value */
+        UCHAR ucPostDiv;        /* Post div */
+} MEMORY_PLLINIT_PARAMETERS;
+
+#define MEMORY_PLLINIT_PS_ALLOCATION  MEMORY_PLLINIT_PARAMETERS
+
+#define GPIO_PIN_WRITE                                                                                                  0x01
+#define GPIO_PIN_READ                                                                                                           0x00
+
+typedef struct _GPIO_PIN_CONTROL_PARAMETERS {
+        UCHAR ucGPIO_ID;        /* return value, read from GPIO pins */
+        UCHAR ucGPIOBitShift;   /* define which bit in uGPIOBitVal need to be update */
+        UCHAR ucGPIOBitVal;     /* Set/Reset corresponding bit defined in ucGPIOBitMask */
+        UCHAR ucAction;         /* =GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write */
+} GPIO_PIN_CONTROL_PARAMETERS;
+
+typedef struct _ENABLE_SCALER_PARAMETERS {
+        UCHAR ucScaler;         /*  ATOM_SCALER1, ATOM_SCALER2 */
+        UCHAR ucEnable;         /*  ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION */
+        UCHAR ucTVStandard;     /*  */
+        UCHAR ucPadding[1];
+} ENABLE_SCALER_PARAMETERS;
+#define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
+
+/* ucEnable: */
+#define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION    0
+#define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION  1
+#define SCALER_ENABLE_2TAP_ALPHA_MODE               2
+#define SCALER_ENABLE_MULTITAP_MODE                 3
+
+typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS {
+        ULONG usHWIconHorzVertPosn;     /*  Hardware Icon Vertical position */
+        UCHAR ucHWIconVertOffset;       /*  Hardware Icon Vertical offset */
+        UCHAR ucHWIconHorzOffset;       /*  Hardware Icon Horizontal offset */
+        UCHAR ucSelection;      /*  ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 */
+        UCHAR ucEnable;         /*  ATOM_ENABLE or ATOM_DISABLE */
+} ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
+
+typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION {
+        ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;
+        ENABLE_CRTC_PARAMETERS sReserved;
+} ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
+
+typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS {
+        USHORT usHight;         /*  Image Hight */
+        USHORT usWidth;         /*  Image Width */
+        UCHAR ucSurface;        /*  Surface 1 or 2 */
+        UCHAR ucPadding[3];
+} ENABLE_GRAPH_SURFACE_PARAMETERS;
+
+typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 {
+        USHORT usHight;         /*  Image Hight */
+        USHORT usWidth;         /*  Image Width */
+        UCHAR ucSurface;        /*  Surface 1 or 2 */
+        UCHAR ucEnable;         /*  ATOM_ENABLE or ATOM_DISABLE */
+        UCHAR ucPadding[2];
+} ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
+
+typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION {
+        ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
+        ENABLE_YUV_PS_ALLOCATION sReserved;     /*  Don't set this one */
+} ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
+
+typedef struct _MEMORY_CLEAN_UP_PARAMETERS {
+        USHORT usMemoryStart;   /* in 8Kb boundry, offset from memory base address */
+        USHORT usMemorySize;    /* 8Kb blocks aligned */
+} MEMORY_CLEAN_UP_PARAMETERS;
+#define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
+
+typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS {
+        USHORT usX_Size;        /* When use as input parameter, usX_Size indicates which CRTC */
+        USHORT usY_Size;
+} GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
+
+typedef struct _INDIRECT_IO_ACCESS {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        UCHAR IOAccessSequence[256];
+} INDIRECT_IO_ACCESS;
+
+#define INDIRECT_READ              0x00
+#define INDIRECT_WRITE             0x80
+
+#define INDIRECT_IO_MM             0
+#define INDIRECT_IO_PLL            1
+#define INDIRECT_IO_MC             2
+#define INDIRECT_IO_PCIE           3
+#define INDIRECT_IO_PCIEP          4
+#define INDIRECT_IO_NBMISC         5
+
+#define INDIRECT_IO_PLL_READ       INDIRECT_IO_PLL   | INDIRECT_READ
+#define INDIRECT_IO_PLL_WRITE      INDIRECT_IO_PLL   | INDIRECT_WRITE
+#define INDIRECT_IO_MC_READ        INDIRECT_IO_MC    | INDIRECT_READ
+#define INDIRECT_IO_MC_WRITE       INDIRECT_IO_MC    | INDIRECT_WRITE
+#define INDIRECT_IO_PCIE_READ      INDIRECT_IO_PCIE  | INDIRECT_READ
+#define INDIRECT_IO_PCIE_WRITE     INDIRECT_IO_PCIE  | INDIRECT_WRITE
+#define INDIRECT_IO_PCIEP_READ     INDIRECT_IO_PCIEP | INDIRECT_READ
+#define INDIRECT_IO_PCIEP_WRITE    INDIRECT_IO_PCIEP | INDIRECT_WRITE
+#define INDIRECT_IO_NBMISC_READ    INDIRECT_IO_NBMISC | INDIRECT_READ
+#define INDIRECT_IO_NBMISC_WRITE   INDIRECT_IO_NBMISC | INDIRECT_WRITE
+
+typedef struct _ATOM_OEM_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
+} ATOM_OEM_INFO;
+
+typedef struct _ATOM_TV_MODE {
+        UCHAR ucVMode_Num;      /* Video mode number */
+        UCHAR ucTV_Mode_Num;    /* Internal TV mode number */
+} ATOM_TV_MODE;
+
+typedef struct _ATOM_BIOS_INT_TVSTD_MODE {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usTV_Mode_LUT_Offset;    /*  Pointer to standard to internal number conversion table */
+        USHORT usTV_FIFO_Offset;        /*  Pointer to FIFO entry table */
+        USHORT usNTSC_Tbl_Offset;       /*  Pointer to SDTV_Mode_NTSC table */
+        USHORT usPAL_Tbl_Offset;        /*  Pointer to SDTV_Mode_PAL table */
+        USHORT usCV_Tbl_Offset; /*  Pointer to SDTV_Mode_PAL table */
+} ATOM_BIOS_INT_TVSTD_MODE;
+
+typedef struct _ATOM_TV_MODE_SCALER_PTR {
+        USHORT ucFilter0_Offset;        /* Pointer to filter format 0 coefficients */
+        USHORT usFilter1_Offset;        /* Pointer to filter format 0 coefficients */
+        UCHAR ucTV_Mode_Num;
+} ATOM_TV_MODE_SCALER_PTR;
+
+typedef struct _ATOM_STANDARD_VESA_TIMING {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_DTD_FORMAT aModeTimings[16];       /*  16 is not the real array number, just for initial allocation */
+} ATOM_STANDARD_VESA_TIMING;
+
+typedef struct _ATOM_STD_FORMAT {
+        USHORT usSTD_HDisp;
+        USHORT usSTD_VDisp;
+        USHORT usSTD_RefreshRate;
+        USHORT usReserved;
+} ATOM_STD_FORMAT;
+
+typedef struct _ATOM_VESA_TO_EXTENDED_MODE {
+        USHORT usVESA_ModeNumber;
+        USHORT usExtendedModeNumber;
+} ATOM_VESA_TO_EXTENDED_MODE;
+
+typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
+} ATOM_VESA_TO_INTENAL_MODE_LUT;
+
+/*************** ATOM Memory Related Data Structure ***********************/
+typedef struct _ATOM_MEMORY_VENDOR_BLOCK {
+        UCHAR ucMemoryType;
+        UCHAR ucMemoryVendor;
+        UCHAR ucAdjMCId;
+        UCHAR ucDynClkId;
+        ULONG ulDllResetClkRange;
+} ATOM_MEMORY_VENDOR_BLOCK;
+
+typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG {
+#if ATOM_BIG_ENDIAN
+        ULONG ucMemBlkId:8;
+        ULONG ulMemClockRange:24;
+#else
+        ULONG ulMemClockRange:24;
+        ULONG ucMemBlkId:8;
+#endif
+} ATOM_MEMORY_SETTING_ID_CONFIG;
+
+typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS {
+        ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
+        ULONG ulAccess;
+} ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
+
+typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK {
+        ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
+        ULONG aulMemData[1];
+} ATOM_MEMORY_SETTING_DATA_BLOCK;
+
+typedef struct _ATOM_INIT_REG_INDEX_FORMAT {
+        USHORT usRegIndex;      /*  MC register index */
+        UCHAR ucPreRegDataLength;       /*  offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf */
+} ATOM_INIT_REG_INDEX_FORMAT;
+
+typedef struct _ATOM_INIT_REG_BLOCK {
+        USHORT usRegIndexTblSize;       /* size of asRegIndexBuf */
+        USHORT usRegDataBlkSize;        /* size of ATOM_MEMORY_SETTING_DATA_BLOCK */
+        ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
+        ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
+} ATOM_INIT_REG_BLOCK;
+
+#define END_OF_REG_INDEX_BLOCK  0x0ffff
+#define END_OF_REG_DATA_BLOCK   0x00000000
+#define ATOM_INIT_REG_MASK_FLAG 0x80
+#define CLOCK_RANGE_HIGHEST                     0x00ffffff
+
+#define VALUE_DWORD             SIZEOF ULONG
+#define VALUE_SAME_AS_ABOVE     0
+#define VALUE_MASK_DWORD        0x84
+
+#define INDEX_ACCESS_RANGE_BEGIN            (VALUE_DWORD + 1)
+#define INDEX_ACCESS_RANGE_END              (INDEX_ACCESS_RANGE_BEGIN + 1)
+#define VALUE_INDEX_ACCESS_SINGLE           (INDEX_ACCESS_RANGE_END + 1)
+
+typedef struct _ATOM_MC_INIT_PARAM_TABLE {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usAdjustARB_SEQDataOffset;
+        USHORT usMCInitMemTypeTblOffset;
+        USHORT usMCInitCommonTblOffset;
+        USHORT usMCInitPowerDownTblOffset;
+        ULONG ulARB_SEQDataBuf[32];
+        ATOM_INIT_REG_BLOCK asMCInitMemType;
+        ATOM_INIT_REG_BLOCK asMCInitCommon;
+} ATOM_MC_INIT_PARAM_TABLE;
+
+#define _4Mx16              0x2
+#define _4Mx32              0x3
+#define _8Mx16              0x12
+#define _8Mx32              0x13
+#define _16Mx16             0x22
+#define _16Mx32             0x23
+#define _32Mx16             0x32
+#define _32Mx32             0x33
+#define _64Mx8              0x41
+#define _64Mx16             0x42
+
+#define SAMSUNG             0x1
+#define INFINEON            0x2
+#define ELPIDA              0x3
+#define ETRON               0x4
+#define NANYA               0x5
+#define HYNIX               0x6
+#define MOSEL               0x7
+#define WINBOND             0x8
+#define ESMT                0x9
+#define MICRON              0xF
+
+#define QIMONDA             INFINEON
+#define PROMOS              MOSEL
+
+/* ///////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// */
+
+#define UCODE_ROM_START_ADDRESS         0x1c000
+#define UCODE_SIGNATURE                 0x4375434d      /*  'MCuC' - MC uCode */
+
+/* uCode block header for reference */
+
+typedef struct _MCuCodeHeader {
+        ULONG ulSignature;
+        UCHAR ucRevision;
+        UCHAR ucChecksum;
+        UCHAR ucReserved1;
+        UCHAR ucReserved2;
+        USHORT usParametersLength;
+        USHORT usUCodeLength;
+        USHORT usReserved1;
+        USHORT usReserved2;
+} MCuCodeHeader;
+
+/* //////////////////////////////////////////////////////////////////////////////// */
+
+#define ATOM_MAX_NUMBER_OF_VRAM_MODULE  16
+
+#define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK  0xF
+typedef struct _ATOM_VRAM_MODULE_V1 {
+        ULONG ulReserved;
+        USHORT usEMRSValue;
+        USHORT usMRSValue;
+        USHORT usReserved;
+        UCHAR ucExtMemoryID;    /*  An external indicator (by hardcode, callback or pin) to tell what is the current memory module */
+        UCHAR ucMemoryType;     /*  [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; */
+        UCHAR ucMemoryVenderID; /*  Predefined,never change across designs or memory type/vender */
+        UCHAR ucMemoryDeviceCfg;        /*  [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... */
+        UCHAR ucRow;            /*  Number of Row,in power of 2; */
+        UCHAR ucColumn;         /*  Number of Column,in power of 2; */
+        UCHAR ucBank;           /*  Nunber of Bank; */
+        UCHAR ucRank;           /*  Number of Rank, in power of 2 */
+        UCHAR ucChannelNum;     /*  Number of channel; */
+        UCHAR ucChannelConfig;  /*  [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 */
+        UCHAR ucDefaultMVDDQ_ID;        /*  Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; */
+        UCHAR ucDefaultMVDDC_ID;        /*  Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; */
+        UCHAR ucReserved[2];
+} ATOM_VRAM_MODULE_V1;
+
+typedef struct _ATOM_VRAM_MODULE_V2 {
+        ULONG ulReserved;
+        ULONG ulFlags;          /*  To enable/disable functionalities based on memory type */
+        ULONG ulEngineClock;    /*  Override of default engine clock for particular memory type */
+        ULONG ulMemoryClock;    /*  Override of default memory clock for particular memory type */
+        USHORT usEMRS2Value;    /*  EMRS2 Value is used for GDDR2 and GDDR4 memory type */
+        USHORT usEMRS3Value;    /*  EMRS3 Value is used for GDDR2 and GDDR4 memory type */
+        USHORT usEMRSValue;
+        USHORT usMRSValue;
+        USHORT usReserved;
+        UCHAR ucExtMemoryID;    /*  An external indicator (by hardcode, callback or pin) to tell what is the current memory module */
+        UCHAR ucMemoryType;     /*  [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; */
+        UCHAR ucMemoryVenderID; /*  Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed */
+        UCHAR ucMemoryDeviceCfg;        /*  [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... */
+        UCHAR ucRow;            /*  Number of Row,in power of 2; */
+        UCHAR ucColumn;         /*  Number of Column,in power of 2; */
+        UCHAR ucBank;           /*  Nunber of Bank; */
+        UCHAR ucRank;           /*  Number of Rank, in power of 2 */
+        UCHAR ucChannelNum;     /*  Number of channel; */
+        UCHAR ucChannelConfig;  /*  [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 */
+        UCHAR ucDefaultMVDDQ_ID;        /*  Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; */
+        UCHAR ucDefaultMVDDC_ID;        /*  Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; */
+        UCHAR ucRefreshRateFactor;
+        UCHAR ucReserved[3];
+} ATOM_VRAM_MODULE_V2;
+
+typedef struct _ATOM_MEMORY_TIMING_FORMAT {
+        ULONG ulClkRange;       /*  memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing */
+        union {
+                USHORT usMRS;   /*  mode register */
+                USHORT usDDR3_MR0;
+        };
+        union {
+                USHORT usEMRS;  /*  extended mode register */
+                USHORT usDDR3_MR1;
+        };
+        UCHAR ucCL;             /*  CAS latency */
+        UCHAR ucWL;             /*  WRITE Latency */
+        UCHAR uctRAS;           /*  tRAS */
+        UCHAR uctRC;            /*  tRC */
+        UCHAR uctRFC;           /*  tRFC */
+        UCHAR uctRCDR;          /*  tRCDR */
+        UCHAR uctRCDW;          /*  tRCDW */
+        UCHAR uctRP;            /*  tRP */
+        UCHAR uctRRD;           /*  tRRD */
+        UCHAR uctWR;            /*  tWR */
+        UCHAR uctWTR;           /*  tWTR */
+        UCHAR uctPDIX;          /*  tPDIX */
+        UCHAR uctFAW;           /*  tFAW */
+        UCHAR uctAOND;          /*  tAOND */
+        union {
+                struct {
+                        UCHAR ucflag;   /*  flag to control memory timing calculation. bit0= control EMRS2 Infineon */
+                        UCHAR ucReserved;
+                };
+                USHORT usDDR3_MR2;
+        };
+} ATOM_MEMORY_TIMING_FORMAT;
+
+typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 {
+        ULONG ulClkRange;       /*  memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing */
+        USHORT usMRS;           /*  mode register */
+        USHORT usEMRS;          /*  extended mode register */
+        UCHAR ucCL;             /*  CAS latency */
+        UCHAR ucWL;             /*  WRITE Latency */
+        UCHAR uctRAS;           /*  tRAS */
+        UCHAR uctRC;            /*  tRC */
+        UCHAR uctRFC;           /*  tRFC */
+        UCHAR uctRCDR;          /*  tRCDR */
+        UCHAR uctRCDW;          /*  tRCDW */
+        UCHAR uctRP;            /*  tRP */
+        UCHAR uctRRD;           /*  tRRD */
+        UCHAR uctWR;            /*  tWR */
+        UCHAR uctWTR;           /*  tWTR */
+        UCHAR uctPDIX;          /*  tPDIX */
+        UCHAR uctFAW;           /*  tFAW */
+        UCHAR uctAOND;          /*  tAOND */
+        UCHAR ucflag;           /*  flag to control memory timing calculation. bit0= control EMRS2 Infineon */
+/* ///////////////////////GDDR parameters/////////////////////////////////// */
+        UCHAR uctCCDL;          /*  */
+        UCHAR uctCRCRL;         /*  */
+        UCHAR uctCRCWL;         /*  */
+        UCHAR uctCKE;           /*  */
+        UCHAR uctCKRSE;         /*  */
+        UCHAR uctCKRSX;         /*  */
+        UCHAR uctFAW32;         /*  */
+        UCHAR ucReserved1;      /*  */
+        UCHAR ucReserved2;      /*  */
+        UCHAR ucTerminator;
+} ATOM_MEMORY_TIMING_FORMAT_V1;
+
+typedef struct _ATOM_MEMORY_FORMAT {
+        ULONG ulDllDisClock;    /*  memory DLL will be disable when target memory clock is below this clock */
+        union {
+                USHORT usEMRS2Value;    /*  EMRS2 Value is used for GDDR2 and GDDR4 memory type */
+                USHORT usDDR3_Reserved; /*  Not used for DDR3 memory */
+        };
+        union {
+                USHORT usEMRS3Value;    /*  EMRS3 Value is used for GDDR2 and GDDR4 memory type */
+                USHORT usDDR3_MR3;      /*  Used for DDR3 memory */
+        };
+        UCHAR ucMemoryType;     /*  [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; */
+        UCHAR ucMemoryVenderID; /*  Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed */
+        UCHAR ucRow;            /*  Number of Row,in power of 2; */
+        UCHAR ucColumn;         /*  Number of Column,in power of 2; */
+        UCHAR ucBank;           /*  Nunber of Bank; */
+        UCHAR ucRank;           /*  Number of Rank, in power of 2 */
+        UCHAR ucBurstSize;      /*  burst size, 0= burst size=4  1= burst size=8 */
+        UCHAR ucDllDisBit;      /*  position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) */
+        UCHAR ucRefreshRateFactor;      /*  memory refresh rate in unit of ms */
+        UCHAR ucDensity;        /*  _8Mx32, _16Mx32, _16Mx16, _32Mx16 */
+        UCHAR ucPreamble;       /* [7:4] Write Preamble, [3:0] Read Preamble */
+        UCHAR ucMemAttrib;      /*  Memory Device Addribute, like RDBI/WDBI etc */
+        ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];       /* Memory Timing block sort from lower clock to higher clock */
+} ATOM_MEMORY_FORMAT;
+
+typedef struct _ATOM_VRAM_MODULE_V3 {
+        ULONG ulChannelMapCfg;  /*  board dependent paramenter:Channel combination */
+        USHORT usSize;          /*  size of ATOM_VRAM_MODULE_V3 */
+        USHORT usDefaultMVDDQ;  /*  board dependent parameter:Default Memory Core Voltage */
+        USHORT usDefaultMVDDC;  /*  board dependent parameter:Default Memory IO Voltage */
+        UCHAR ucExtMemoryID;    /*  An external indicator (by hardcode, callback or pin) to tell what is the current memory module */
+        UCHAR ucChannelNum;     /*  board dependent parameter:Number of channel; */
+        UCHAR ucChannelSize;    /*  board dependent parameter:32bit or 64bit */
+        UCHAR ucVREFI;          /*  board dependnt parameter: EXT or INT +160mv to -140mv */
+        UCHAR ucNPL_RT;         /*  board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */
+        UCHAR ucFlag;           /*  To enable/disable functionalities based on memory type */
+        ATOM_MEMORY_FORMAT asMemory;    /*  describ all of video memory parameters from memory spec */
+} ATOM_VRAM_MODULE_V3;
+
+/* ATOM_VRAM_MODULE_V3.ucNPL_RT */
+#define NPL_RT_MASK                                                                                                                     0x0f
+#define BATTERY_ODT_MASK                                                                                                0xc0
+
+#define ATOM_VRAM_MODULE                 ATOM_VRAM_MODULE_V3
+
+typedef struct _ATOM_VRAM_MODULE_V4 {
+        ULONG ulChannelMapCfg;  /*  board dependent parameter: Channel combination */
+        USHORT usModuleSize;    /*  size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE */
+        USHORT usPrivateReserved;       /*  BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */
+        /*  MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) */
+        USHORT usReserved;
+        UCHAR ucExtMemoryID;    /*  An external indicator (by hardcode, callback or pin) to tell what is the current memory module */
+        UCHAR ucMemoryType;     /*  [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; */
+        UCHAR ucChannelNum;     /*  Number of channels present in this module config */
+        UCHAR ucChannelWidth;   /*  0 - 32 bits; 1 - 64 bits */
+        UCHAR ucDensity;        /*  _8Mx32, _16Mx32, _16Mx16, _32Mx16 */
+        UCHAR ucFlag;           /*  To enable/disable functionalities based on memory type */
+        UCHAR ucMisc;           /*  bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8 */
+        UCHAR ucVREFI;          /*  board dependent parameter */
+        UCHAR ucNPL_RT;         /*  board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */
+        UCHAR ucPreamble;       /*  [7:4] Write Preamble, [3:0] Read Preamble */
+        UCHAR ucMemorySize;     /*  BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */
+        /*  Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros */
+        UCHAR ucReserved[3];
+
+/* compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level */
+        union {
+                USHORT usEMRS2Value;    /*  EMRS2 Value is used for GDDR2 and GDDR4 memory type */
+                USHORT usDDR3_Reserved;
+        };
+        union {
+                USHORT usEMRS3Value;    /*  EMRS3 Value is used for GDDR2 and GDDR4 memory type */
+                USHORT usDDR3_MR3;      /*  Used for DDR3 memory */
+        };
+        UCHAR ucMemoryVenderID; /*  Predefined, If not predefined, vendor detection table gets executed */
+        UCHAR ucRefreshRateFactor;      /*  [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) */
+        UCHAR ucReserved2[2];
+        ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];       /* Memory Timing block sort from lower clock to higher clock */
+} ATOM_VRAM_MODULE_V4;
+
+#define VRAM_MODULE_V4_MISC_RANK_MASK       0x3
+#define VRAM_MODULE_V4_MISC_DUAL_RANK       0x1
+#define VRAM_MODULE_V4_MISC_BL_MASK         0x4
+#define VRAM_MODULE_V4_MISC_BL8             0x4
+#define VRAM_MODULE_V4_MISC_DUAL_CS         0x10
+
+typedef struct _ATOM_VRAM_MODULE_V5 {
+        ULONG ulChannelMapCfg;  /*  board dependent parameter: Channel combination */
+        USHORT usModuleSize;    /*  size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE */
+        USHORT usPrivateReserved;       /*  BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */
+        /*  MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) */
+        USHORT usReserved;
+        UCHAR ucExtMemoryID;    /*  An external indicator (by hardcode, callback or pin) to tell what is the current memory module */
+        UCHAR ucMemoryType;     /*  [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; */
+        UCHAR ucChannelNum;     /*  Number of channels present in this module config */
+        UCHAR ucChannelWidth;   /*  0 - 32 bits; 1 - 64 bits */
+        UCHAR ucDensity;        /*  _8Mx32, _16Mx32, _16Mx16, _32Mx16 */
+        UCHAR ucFlag;           /*  To enable/disable functionalities based on memory type */
+        UCHAR ucMisc;           /*  bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8 */
+        UCHAR ucVREFI;          /*  board dependent parameter */
+        UCHAR ucNPL_RT;         /*  board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */
+        UCHAR ucPreamble;       /*  [7:4] Write Preamble, [3:0] Read Preamble */
+        UCHAR ucMemorySize;     /*  BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */
+        /*  Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros */
+        UCHAR ucReserved[3];
+
+/* compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level */
+        USHORT usEMRS2Value;    /*  EMRS2 Value is used for GDDR2 and GDDR4 memory type */
+        USHORT usEMRS3Value;    /*  EMRS3 Value is used for GDDR2 and GDDR4 memory type */
+        UCHAR ucMemoryVenderID; /*  Predefined, If not predefined, vendor detection table gets executed */
+        UCHAR ucRefreshRateFactor;      /*  [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) */
+        UCHAR ucFIFODepth;      /*  FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth */
+        UCHAR ucCDR_Bandwidth;  /*  [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth */
+        ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];    /* Memory Timing block sort from lower clock to higher clock */
+} ATOM_VRAM_MODULE_V5;
+
+typedef struct _ATOM_VRAM_INFO_V2 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        UCHAR ucNumOfVRAMModule;
+        ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];     /*  just for allocation, real number of blocks is in ucNumOfVRAMModule; */
+} ATOM_VRAM_INFO_V2;
+
+typedef struct _ATOM_VRAM_INFO_V3 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usMemAdjustTblOffset;    /*  offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting */
+        USHORT usMemClkPatchTblOffset;  /*      offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting */
+        USHORT usRerseved;
+        UCHAR aVID_PinsShift[9];        /*  8 bit strap maximum+terminator */
+        UCHAR ucNumOfVRAMModule;
+        ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];     /*  just for allocation, real number of blocks is in ucNumOfVRAMModule; */
+        ATOM_INIT_REG_BLOCK asMemPatch; /*  for allocation */
+        /*      ATOM_INIT_REG_BLOCK                              aMemAdjust; */
+} ATOM_VRAM_INFO_V3;
+
+#define ATOM_VRAM_INFO_LAST          ATOM_VRAM_INFO_V3
+
+typedef struct _ATOM_VRAM_INFO_V4 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usMemAdjustTblOffset;    /*  offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting */
+        USHORT usMemClkPatchTblOffset;  /*      offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting */
+        USHORT usRerseved;
+        UCHAR ucMemDQ7_0ByteRemap;      /*  DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 */
+        ULONG ulMemDQ7_0BitRemap;       /*  each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] */
+        UCHAR ucReservde[4];
+        UCHAR ucNumOfVRAMModule;
+        ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];  /*  just for allocation, real number of blocks is in ucNumOfVRAMModule; */
+        ATOM_INIT_REG_BLOCK asMemPatch; /*  for allocation */
+        /*      ATOM_INIT_REG_BLOCK                              aMemAdjust; */
+} ATOM_VRAM_INFO_V4;
+
+typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        UCHAR aVID_PinsShift[9];        /* 8 bit strap maximum+terminator */
+} ATOM_VRAM_GPIO_DETECTION_INFO;
+
+typedef struct _ATOM_MEMORY_TRAINING_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        UCHAR ucTrainingLoop;
+        UCHAR ucReserved[3];
+        ATOM_INIT_REG_BLOCK asMemTrainingSetting;
+} ATOM_MEMORY_TRAINING_INFO;
+
+typedef struct SW_I2C_CNTL_DATA_PARAMETERS {
+        UCHAR ucControl;
+        UCHAR ucData;
+        UCHAR ucSatus;
+        UCHAR ucTemp;
+} SW_I2C_CNTL_DATA_PARAMETERS;
+
+#define SW_I2C_CNTL_DATA_PS_ALLOCATION  SW_I2C_CNTL_DATA_PARAMETERS
+
+typedef struct _SW_I2C_IO_DATA_PARAMETERS {
+        USHORT GPIO_Info;
+        UCHAR ucAct;
+        UCHAR ucData;
+} SW_I2C_IO_DATA_PARAMETERS;
+
+#define SW_I2C_IO_DATA_PS_ALLOCATION  SW_I2C_IO_DATA_PARAMETERS
+
+/****************************SW I2C CNTL DEFINITIONS**********************/
+#define SW_I2C_IO_RESET       0
+#define SW_I2C_IO_GET         1
+#define SW_I2C_IO_DRIVE       2
+#define SW_I2C_IO_SET         3
+#define SW_I2C_IO_START       4
+
+#define SW_I2C_IO_CLOCK       0
+#define SW_I2C_IO_DATA        0x80
+
+#define SW_I2C_IO_ZERO        0
+#define SW_I2C_IO_ONE         0x100
+
+#define SW_I2C_CNTL_READ      0
+#define SW_I2C_CNTL_WRITE     1
+#define SW_I2C_CNTL_START     2
+#define SW_I2C_CNTL_STOP      3
+#define SW_I2C_CNTL_OPEN      4
+#define SW_I2C_CNTL_CLOSE     5
+#define SW_I2C_CNTL_WRITE1BIT 6
+
+/* ==============================VESA definition Portion=============================== */
+#define VESA_OEM_PRODUCT_REV                                '01.00'
+#define VESA_MODE_ATTRIBUTE_MODE_SUPPORT             0xBB       /* refer to VBE spec p.32, no TTY support */
+#define VESA_MODE_WIN_ATTRIBUTE                                              7
+#define VESA_WIN_SIZE                                                                                        64
+
+typedef struct _PTR_32_BIT_STRUCTURE {
+        USHORT Offset16;
+        USHORT Segment16;
+} PTR_32_BIT_STRUCTURE;
+
+typedef union _PTR_32_BIT_UNION {
+        PTR_32_BIT_STRUCTURE SegmentOffset;
+        ULONG Ptr32_Bit;
+} PTR_32_BIT_UNION;
+
+typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE {
+        UCHAR VbeSignature[4];
+        USHORT VbeVersion;
+        PTR_32_BIT_UNION OemStringPtr;
+        UCHAR Capabilities[4];
+        PTR_32_BIT_UNION VideoModePtr;
+        USHORT TotalMemory;
+} VBE_1_2_INFO_BLOCK_UPDATABLE;
+
+typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE {
+        VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;
+        USHORT OemSoftRev;
+        PTR_32_BIT_UNION OemVendorNamePtr;
+        PTR_32_BIT_UNION OemProductNamePtr;
+        PTR_32_BIT_UNION OemProductRevPtr;
+} VBE_2_0_INFO_BLOCK_UPDATABLE;
+
+typedef union _VBE_VERSION_UNION {
+        VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;
+        VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;
+} VBE_VERSION_UNION;
+
+typedef struct _VBE_INFO_BLOCK {
+        VBE_VERSION_UNION UpdatableVBE_Info;
+        UCHAR Reserved[222];
+        UCHAR OemData[256];
+} VBE_INFO_BLOCK;
+
+typedef struct _VBE_FP_INFO {
+        USHORT HSize;
+        USHORT VSize;
+        USHORT FPType;
+        UCHAR RedBPP;
+        UCHAR GreenBPP;
+        UCHAR BlueBPP;
+        UCHAR ReservedBPP;
+        ULONG RsvdOffScrnMemSize;
+        ULONG RsvdOffScrnMEmPtr;
+        UCHAR Reserved[14];
+} VBE_FP_INFO;
+
+typedef struct _VESA_MODE_INFO_BLOCK {
+/*  Mandatory information for all VBE revisions */
+        USHORT ModeAttributes;  /*                  dw      ?       ; mode attributes */
+        UCHAR WinAAttributes;   /*                    db      ?       ; window A attributes */
+        UCHAR WinBAttributes;   /*                    db      ?       ; window B attributes */
+        USHORT WinGranularity;  /*                    dw      ?       ; window granularity */
+        USHORT WinSize;         /*                    dw      ?       ; window size */
+        USHORT WinASegment;     /*                    dw      ?       ; window A start segment */
+        USHORT WinBSegment;     /*                    dw      ?       ; window B start segment */
+        ULONG WinFuncPtr;       /*                    dd      ?       ; real mode pointer to window function */
+        USHORT BytesPerScanLine;        /*                    dw      ?       ; bytes per scan line */
+
+/* ; Mandatory information for VBE 1.2 and above */
+        USHORT XResolution;     /*                         dw      ?       ; horizontal resolution in pixels or characters */
+        USHORT YResolution;     /*                   dw      ?       ; vertical resolution in pixels or characters */
+        UCHAR XCharSize;        /*                   db      ?       ; character cell width in pixels */
+        UCHAR YCharSize;        /*                   db      ?       ; character cell height in pixels */
+        UCHAR NumberOfPlanes;   /*                   db      ?       ; number of memory planes */
+        UCHAR BitsPerPixel;     /*                   db      ?       ; bits per pixel */
+        UCHAR NumberOfBanks;    /*                   db      ?       ; number of banks */
+        UCHAR MemoryModel;      /*                   db      ?       ; memory model type */
+        UCHAR BankSize;         /*                   db      ?       ; bank size in KB */
+        UCHAR NumberOfImagePages;       /*            db    ?       ; number of images */
+        UCHAR ReservedForPageFunction;  /* db  1       ; reserved for page function */
+
+/* ; Direct Color fields(required for direct/6 and YUV/7 memory models) */
+        UCHAR RedMaskSize;      /*           db      ?       ; size of direct color red mask in bits */
+        UCHAR RedFieldPosition; /*           db      ?       ; bit position of lsb of red mask */
+        UCHAR GreenMaskSize;    /*           db      ?       ; size of direct color green mask in bits */
+        UCHAR GreenFieldPosition;       /*           db      ?       ; bit position of lsb of green mask */
+        UCHAR BlueMaskSize;     /*           db      ?       ; size of direct color blue mask in bits */
+        UCHAR BlueFieldPosition;        /*           db      ?       ; bit position of lsb of blue mask */
+        UCHAR RsvdMaskSize;     /*           db      ?       ; size of direct color reserved mask in bits */
+        UCHAR RsvdFieldPosition;        /*           db      ?       ; bit position of lsb of reserved mask */
+        UCHAR DirectColorModeInfo;      /*           db      ?       ; direct color mode attributes */
+
+/* ; Mandatory information for VBE 2.0 and above */
+        ULONG PhysBasePtr;      /*           dd      ?       ; physical address for flat memory frame buffer */
+        ULONG Reserved_1;       /*           dd      0       ; reserved - always set to 0 */
+        USHORT Reserved_2;      /*     dw    0       ; reserved - always set to 0 */
+
+/* ; Mandatory information for VBE 3.0 and above */
+        USHORT LinBytesPerScanLine;     /*         dw      ?       ; bytes per scan line for linear modes */
+        UCHAR BnkNumberOfImagePages;    /*         db      ?       ; number of images for banked modes */
+        UCHAR LinNumberOfImagPages;     /*         db      ?       ; number of images for linear modes */
+        UCHAR LinRedMaskSize;   /*         db      ?       ; size of direct color red mask(linear modes) */
+        UCHAR LinRedFieldPosition;      /*         db      ?       ; bit position of lsb of red mask(linear modes) */
+        UCHAR LinGreenMaskSize; /*         db      ?       ; size of direct color green mask(linear modes) */
+        UCHAR LinGreenFieldPosition;    /*         db      ?       ; bit position of lsb of green mask(linear modes) */
+        UCHAR LinBlueMaskSize;  /*         db      ?       ; size of direct color blue mask(linear modes) */
+        UCHAR LinBlueFieldPosition;     /*         db      ?       ; bit position of lsb of blue mask(linear modes) */
+        UCHAR LinRsvdMaskSize;  /*         db      ?       ; size of direct color reserved mask(linear modes) */
+        UCHAR LinRsvdFieldPosition;     /*         db      ?       ; bit position of lsb of reserved mask(linear modes) */
+        ULONG MaxPixelClock;    /*         dd      ?       ; maximum pixel clock(in Hz) for graphics mode */
+        UCHAR Reserved;         /*         db      190 dup (0) */
+} VESA_MODE_INFO_BLOCK;
+
+/*  BIOS function CALLS */
+#define ATOM_BIOS_EXTENDED_FUNCTION_CODE        0xA0    /*  ATI Extended Function code */
+#define ATOM_BIOS_FUNCTION_COP_MODE             0x00
+#define ATOM_BIOS_FUNCTION_SHORT_QUERY1         0x04
+#define ATOM_BIOS_FUNCTION_SHORT_QUERY2         0x05
+#define ATOM_BIOS_FUNCTION_SHORT_QUERY3         0x06
+#define ATOM_BIOS_FUNCTION_GET_DDC              0x0B
+#define ATOM_BIOS_FUNCTION_ASIC_DSTATE          0x0E
+#define ATOM_BIOS_FUNCTION_DEBUG_PLAY           0x0F
+#define ATOM_BIOS_FUNCTION_STV_STD              0x16
+#define ATOM_BIOS_FUNCTION_DEVICE_DET           0x17
+#define ATOM_BIOS_FUNCTION_DEVICE_SWITCH        0x18
+
+#define ATOM_BIOS_FUNCTION_PANEL_CONTROL        0x82
+#define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET       0x83
+#define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH    0x84
+#define ATOM_BIOS_FUNCTION_HW_ICON              0x8A
+#define ATOM_BIOS_FUNCTION_SET_CMOS             0x8B
+#define SUB_FUNCTION_UPDATE_DISPLAY_INFO        0x8000  /*  Sub function 80 */
+#define SUB_FUNCTION_UPDATE_EXPANSION_INFO      0x8100  /*  Sub function 80 */
+
+#define ATOM_BIOS_FUNCTION_DISPLAY_INFO         0x8D
+#define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF        0x8E
+#define ATOM_BIOS_FUNCTION_VIDEO_STATE          0x8F
+#define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE    0x0300  /*  Sub function 03 */
+#define ATOM_SUB_FUNCTION_GET_LIDSTATE          0x0700  /*  Sub function 7 */
+#define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE  0x1400  /*  Notify caller the current thermal state */
+#define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300  /*  Notify caller the current critical state */
+#define ATOM_SUB_FUNCTION_SET_LIDSTATE          0x8500  /*  Sub function 85 */
+#define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900        /*  Sub function 89 */
+#define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT    0x9400  /*  Notify caller that ADC is supported */
+
+#define ATOM_BIOS_FUNCTION_VESA_DPMS            0x4F10  /*  Set DPMS */
+#define ATOM_SUB_FUNCTION_SET_DPMS              0x0001  /*  BL: Sub function 01 */
+#define ATOM_SUB_FUNCTION_GET_DPMS              0x0002  /*  BL: Sub function 02 */
+#define ATOM_PARAMETER_VESA_DPMS_ON             0x0000  /*  BH Parameter for DPMS ON. */
+#define ATOM_PARAMETER_VESA_DPMS_STANDBY        0x0100  /*  BH Parameter for DPMS STANDBY */
+#define ATOM_PARAMETER_VESA_DPMS_SUSPEND        0x0200  /*  BH Parameter for DPMS SUSPEND */
+#define ATOM_PARAMETER_VESA_DPMS_OFF            0x0400  /*  BH Parameter for DPMS OFF */
+#define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON      0x0800  /*  BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) */
+
+#define ATOM_BIOS_RETURN_CODE_MASK              0x0000FF00L
+#define ATOM_BIOS_REG_HIGH_MASK                 0x0000FF00L
+#define ATOM_BIOS_REG_LOW_MASK                  0x000000FFL
+
+/*  structure used for VBIOS only */
+
+/* DispOutInfoTable */
+typedef struct _ASIC_TRANSMITTER_INFO {
+        USHORT usTransmitterObjId;
+        USHORT usSupportDevice;
+        UCHAR ucTransmitterCmdTblId;
+        UCHAR ucConfig;
+        UCHAR ucEncoderID;      /* available 1st encoder ( default ) */
+        UCHAR ucOptionEncoderID;        /* available 2nd encoder ( optional ) */
+        UCHAR uc2ndEncoderID;
+        UCHAR ucReserved;
+} ASIC_TRANSMITTER_INFO;
+
+typedef struct _ASIC_ENCODER_INFO {
+        UCHAR ucEncoderID;
+        UCHAR ucEncoderConfig;
+        USHORT usEncoderCmdTblId;
+} ASIC_ENCODER_INFO;
+
+typedef struct _ATOM_DISP_OUT_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT ptrTransmitterInfo;
+        USHORT ptrEncoderInfo;
+        ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
+        ASIC_ENCODER_INFO asEncoderInfo[1];
+} ATOM_DISP_OUT_INFO;
+
+/*  DispDevicePriorityInfo */
+typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT asDevicePriority[16];
+} ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
+
+/* ProcessAuxChannelTransactionTable */
+typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS {
+        USHORT lpAuxRequest;
+        USHORT lpDataOut;
+        UCHAR ucChannelID;
+        union {
+                UCHAR ucReplyStatus;
+                UCHAR ucDelay;
+        };
+        UCHAR ucDataOutLen;
+        UCHAR ucReserved;
+} PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
+
+#define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION                   PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
+
+/* GetSinkType */
+
+typedef struct _DP_ENCODER_SERVICE_PARAMETERS {
+        USHORT ucLinkClock;
+        union {
+                UCHAR ucConfig; /*  for DP training command */
+                UCHAR ucI2cId;  /*  use for GET_SINK_TYPE command */
+        };
+        UCHAR ucAction;
+        UCHAR ucStatus;
+        UCHAR ucLaneNum;
+        UCHAR ucReserved[2];
+} DP_ENCODER_SERVICE_PARAMETERS;
+
+/*  ucAction */
+#define ATOM_DP_ACTION_GET_SINK_TYPE                                                    0x01
+#define ATOM_DP_ACTION_TRAINING_START                                                   0x02
+#define ATOM_DP_ACTION_TRAINING_COMPLETE                                        0x03
+#define ATOM_DP_ACTION_TRAINING_PATTERN_SEL                             0x04
+#define ATOM_DP_ACTION_SET_VSWING_PREEMP                                        0x05
+#define ATOM_DP_ACTION_GET_VSWING_PREEMP                                        0x06
+#define ATOM_DP_ACTION_BLANKING                   0x07
+
+/*  ucConfig */
+#define ATOM_DP_CONFIG_ENCODER_SEL_MASK                                         0x03
+#define ATOM_DP_CONFIG_DIG1_ENCODER                                                             0x00
+#define ATOM_DP_CONFIG_DIG2_ENCODER                                                             0x01
+#define ATOM_DP_CONFIG_EXTERNAL_ENCODER                                         0x02
+#define ATOM_DP_CONFIG_LINK_SEL_MASK                                                    0x04
+#define ATOM_DP_CONFIG_LINK_A                                                                                   0x00
+#define ATOM_DP_CONFIG_LINK_B                                                                                   0x04
+
+#define DP_ENCODER_SERVICE_PS_ALLOCATION                                WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
+
+/*  DP_TRAINING_TABLE */
+#define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR                             ATOM_DP_TRAINING_TBL_ADDR
+#define DPCD_SET_SS_CNTL_TBL_ADDR                                                                                                       (ATOM_DP_TRAINING_TBL_ADDR + 8 )
+#define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR                                                    (ATOM_DP_TRAINING_TBL_ADDR + 16)
+#define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 24)
+#define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 32)
+#define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR                                                   (ATOM_DP_TRAINING_TBL_ADDR + 40)
+#define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR                                                    (ATOM_DP_TRAINING_TBL_ADDR + 48)
+#define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 60)
+#define DP_I2C_AUX_DDC_WRITE_TBL_ADDR                                                                                   (ATOM_DP_TRAINING_TBL_ADDR + 64)
+#define DP_I2C_AUX_DDC_READ_START_TBL_ADDR                                                              (ATOM_DP_TRAINING_TBL_ADDR + 72)
+#define DP_I2C_AUX_DDC_READ_TBL_ADDR                                                                                    (ATOM_DP_TRAINING_TBL_ADDR + 76)
+#define DP_I2C_AUX_DDC_READ_END_TBL_ADDR                                                                        (ATOM_DP_TRAINING_TBL_ADDR + 80)
+
+typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS {
+        UCHAR ucI2CSpeed;
+        union {
+                UCHAR ucRegIndex;
+                UCHAR ucStatus;
+        };
+        USHORT lpI2CDataOut;
+        UCHAR ucFlag;
+        UCHAR ucTransBytes;
+        UCHAR ucSlaveAddr;
+        UCHAR ucLineNumber;
+} PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
+
+#define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION       PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
+
+/* ucFlag */
+#define HW_I2C_WRITE        1
+#define HW_I2C_READ         0
+
+/****************************************************************************/
+/* Portion VI: Definitinos being oboselete */
+/****************************************************************************/
+
+/* ========================================================================================== */
+/* Remove the definitions below when driver is ready! */
+typedef struct _ATOM_DAC_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usMaxFrequency;  /*  in 10kHz unit */
+        USHORT usReserved;
+} ATOM_DAC_INFO;
+
+typedef struct _COMPASSIONATE_DATA {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+
+        /* ==============================  DAC1 portion */
+        UCHAR ucDAC1_BG_Adjustment;
+        UCHAR ucDAC1_DAC_Adjustment;
+        USHORT usDAC1_FORCE_Data;
+        /* ==============================  DAC2 portion */
+        UCHAR ucDAC2_CRT2_BG_Adjustment;
+        UCHAR ucDAC2_CRT2_DAC_Adjustment;
+        USHORT usDAC2_CRT2_FORCE_Data;
+        USHORT usDAC2_CRT2_MUX_RegisterIndex;
+        UCHAR ucDAC2_CRT2_MUX_RegisterInfo;     /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */
+        UCHAR ucDAC2_NTSC_BG_Adjustment;
+        UCHAR ucDAC2_NTSC_DAC_Adjustment;
+        USHORT usDAC2_TV1_FORCE_Data;
+        USHORT usDAC2_TV1_MUX_RegisterIndex;
+        UCHAR ucDAC2_TV1_MUX_RegisterInfo;      /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */
+        UCHAR ucDAC2_CV_BG_Adjustment;
+        UCHAR ucDAC2_CV_DAC_Adjustment;
+        USHORT usDAC2_CV_FORCE_Data;
+        USHORT usDAC2_CV_MUX_RegisterIndex;
+        UCHAR ucDAC2_CV_MUX_RegisterInfo;       /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */
+        UCHAR ucDAC2_PAL_BG_Adjustment;
+        UCHAR ucDAC2_PAL_DAC_Adjustment;
+        USHORT usDAC2_TV2_FORCE_Data;
+} COMPASSIONATE_DATA;
+
+/****************************Supported Device Info Table Definitions**********************/
+/*   ucConnectInfo: */
+/*     [7:4] - connector type */
+/*       = 1   - VGA connector */
+/*       = 2   - DVI-I */
+/*       = 3   - DVI-D */
+/*       = 4   - DVI-A */
+/*       = 5   - SVIDEO */
+/*       = 6   - COMPOSITE */
+/*       = 7   - LVDS */
+/*       = 8   - DIGITAL LINK */
+/*       = 9   - SCART */
+/*       = 0xA - HDMI_type A */
+/*       = 0xB - HDMI_type B */
+/*       = 0xE - Special case1 (DVI+DIN) */
+/*       Others=TBD */
+/*     [3:0] - DAC Associated */
+/*       = 0   - no DAC */
+/*       = 1   - DACA */
+/*       = 2   - DACB */
+/*       = 3   - External DAC */
+/*       Others=TBD */
+/*  */
+
+typedef struct _ATOM_CONNECTOR_INFO {
+#if ATOM_BIG_ENDIAN
+        UCHAR bfConnectorType:4;
+        UCHAR bfAssociatedDAC:4;
+#else
+        UCHAR bfAssociatedDAC:4;
+        UCHAR bfConnectorType:4;
+#endif
+} ATOM_CONNECTOR_INFO;
+
+typedef union _ATOM_CONNECTOR_INFO_ACCESS {
+        ATOM_CONNECTOR_INFO sbfAccess;
+        UCHAR ucAccess;
+} ATOM_CONNECTOR_INFO_ACCESS;
+
+typedef struct _ATOM_CONNECTOR_INFO_I2C {
+        ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
+        ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
+} ATOM_CONNECTOR_INFO_I2C;
+
+typedef struct _ATOM_SUPPORTED_DEVICES_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usDeviceSupport;
+        ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
+} ATOM_SUPPORTED_DEVICES_INFO;
+
+#define NO_INT_SRC_MAPPED       0xFF
+
+typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP {
+        UCHAR ucIntSrcBitmap;
+} ATOM_CONNECTOR_INC_SRC_BITMAP;
+
+typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usDeviceSupport;
+        ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
+        ATOM_CONNECTOR_INC_SRC_BITMAP
+            asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
+} ATOM_SUPPORTED_DEVICES_INFO_2;
+
+typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usDeviceSupport;
+        ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
+        ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
+} ATOM_SUPPORTED_DEVICES_INFO_2d1;
+
+#define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
+
+typedef struct _ATOM_MISC_CONTROL_INFO {
+        USHORT usFrequency;
+        UCHAR ucPLL_ChargePump; /*  PLL charge-pump gain control */
+        UCHAR ucPLL_DutyCycle;  /*  PLL duty cycle control */
+        UCHAR ucPLL_VCO_Gain;   /*  PLL VCO gain control */
+        UCHAR ucPLL_VoltageSwing;       /*  PLL driver voltage swing control */
+} ATOM_MISC_CONTROL_INFO;
+
+#define ATOM_MAX_MISC_INFO       4
+
+typedef struct _ATOM_TMDS_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usMaxFrequency;  /*  in 10Khz */
+        ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];
+} ATOM_TMDS_INFO;
+
+typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE {
+        UCHAR ucTVStandard;     /* Same as TV standards defined above, */
+        UCHAR ucPadding[1];
+} ATOM_ENCODER_ANALOG_ATTRIBUTE;
+
+typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE {
+        UCHAR ucAttribute;      /* Same as other digital encoder attributes defined above */
+        UCHAR ucPadding[1];
+} ATOM_ENCODER_DIGITAL_ATTRIBUTE;
+
+typedef union _ATOM_ENCODER_ATTRIBUTE {
+        ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
+        ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
+} ATOM_ENCODER_ATTRIBUTE;
+
+typedef struct _DVO_ENCODER_CONTROL_PARAMETERS {
+        USHORT usPixelClock;
+        USHORT usEncoderID;
+        UCHAR ucDeviceType;     /* Use ATOM_DEVICE_xxx1_Index to indicate device type only. */
+        UCHAR ucAction;         /* ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT */
+        ATOM_ENCODER_ATTRIBUTE usDevAttr;
+} DVO_ENCODER_CONTROL_PARAMETERS;
+
+typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION {
+        DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
+        WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;     /* Caller doesn't need to init this portion */
+} DVO_ENCODER_CONTROL_PS_ALLOCATION;
+
+#define ATOM_XTMDS_ASIC_SI164_ID        1
+#define ATOM_XTMDS_ASIC_SI178_ID        2
+#define ATOM_XTMDS_ASIC_TFP513_ID       3
+#define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
+#define ATOM_XTMDS_SUPPORTED_DUALLINK   0x00000002
+#define ATOM_XTMDS_MVPU_FPGA            0x00000004
+
+typedef struct _ATOM_XTMDS_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        USHORT usSingleLinkMaxFrequency;
+        ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;     /* Point the ID on which I2C is used to control external chip */
+        UCHAR ucXtransimitterID;
+        UCHAR ucSupportedLink;  /*  Bit field, bit0=1, single link supported;bit1=1,dual link supported */
+        UCHAR ucSequnceAlterID; /*  Even with the same external TMDS asic, it's possible that the program seqence alters */
+        /*  due to design. This ID is used to alert driver that the sequence is not "standard"! */
+        UCHAR ucMasterAddress;  /*  Address to control Master xTMDS Chip */
+        UCHAR ucSlaveAddress;   /*  Address to control Slave xTMDS Chip */
+} ATOM_XTMDS_INFO;
+
+typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS {
+        UCHAR ucEnable;         /*  ATOM_ENABLE=On or ATOM_DISABLE=Off */
+        UCHAR ucDevice;         /*  ATOM_DEVICE_DFP1_INDEX.... */
+        UCHAR ucPadding[2];
+} DFP_DPMS_STATUS_CHANGE_PARAMETERS;
+
+/****************************Legacy Power Play Table Definitions **********************/
+
+/* Definitions for ulPowerPlayMiscInfo */
+#define ATOM_PM_MISCINFO_SPLIT_CLOCK                     0x00000000L
+#define ATOM_PM_MISCINFO_USING_MCLK_SRC                  0x00000001L
+#define ATOM_PM_MISCINFO_USING_SCLK_SRC                  0x00000002L
+
+#define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT            0x00000004L
+#define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH        0x00000008L
+
+#define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN             0x00000010L
+
+#define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN          0x00000020L
+#define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN          0x00000040L
+#define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE                 0x00000080L    /* When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program */
+
+#define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN      0x00000100L
+#define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN         0x00000200L
+#define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN              0x00000400L
+#define ATOM_PM_MISCINFO_LOAD_BALANCE_EN                 0x00000800L
+#define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE     0x00001000L
+#define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
+#define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE            0x00004000L
+
+#define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE             0x00008000L
+#define ATOM_PM_MISCINFO_OVER_CLOCK_MODE                 0x00010000L
+#define ATOM_PM_MISCINFO_OVER_DRIVE_MODE                 0x00020000L
+#define ATOM_PM_MISCINFO_POWER_SAVING_MODE               0x00040000L
+#define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE              0x00080000L
+
+#define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK           0x00300000L    /* 0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved */
+#define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT          20
+
+#define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE                 0x00400000L
+#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2      0x00800000L
+#define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4      0x01000000L
+#define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN            0x02000000L    /* When set, Dynamic */
+#define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN        0x04000000L    /* When set, Dynamic */
+#define ATOM_PM_MISCINFO_3D_ACCELERATION_EN              0x08000000L    /* When set, This mode is for acceleated 3D mode */
+
+#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK   0x70000000L    /* 1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) */
+#define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT  28
+#define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS                0x80000000L
+
+#define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE            0x00000001L
+#define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT          0x00000002L
+#define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN           0x00000004L
+#define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO            0x00000008L
+#define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE              0x00000010L
+#define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN       0x00000020L
+#define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE         0x00000040L    /* If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. */
+                                                                      /* If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback */
+#define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC                0x00000080L
+#define ATOM_PM_MISCINFO2_STUTTER_MODE_EN                0x00000100L
+#define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE               0x00000200L
+
+/* ucTableFormatRevision=1 */
+/* ucTableContentRevision=1 */
+typedef struct _ATOM_POWERMODE_INFO {
+        ULONG ulMiscInfo;       /* The power level should be arranged in ascending order */
+        ULONG ulReserved1;      /*  must set to 0 */
+        ULONG ulReserved2;      /*  must set to 0 */
+        USHORT usEngineClock;
+        USHORT usMemoryClock;
+        UCHAR ucVoltageDropIndex;       /*  index to GPIO table */
+        UCHAR ucSelectedPanel_RefreshRate;      /*  panel refresh rate */
+        UCHAR ucMinTemperature;
+        UCHAR ucMaxTemperature;
+        UCHAR ucNumPciELanes;   /*  number of PCIE lanes */
+} ATOM_POWERMODE_INFO;
+
+/* ucTableFormatRevision=2 */
+/* ucTableContentRevision=1 */
+typedef struct _ATOM_POWERMODE_INFO_V2 {
+        ULONG ulMiscInfo;       /* The power level should be arranged in ascending order */
+        ULONG ulMiscInfo2;
+        ULONG ulEngineClock;
+        ULONG ulMemoryClock;
+        UCHAR ucVoltageDropIndex;       /*  index to GPIO table */
+        UCHAR ucSelectedPanel_RefreshRate;      /*  panel refresh rate */
+        UCHAR ucMinTemperature;
+        UCHAR ucMaxTemperature;
+        UCHAR ucNumPciELanes;   /*  number of PCIE lanes */
+} ATOM_POWERMODE_INFO_V2;
+
+/* ucTableFormatRevision=2 */
+/* ucTableContentRevision=2 */
+typedef struct _ATOM_POWERMODE_INFO_V3 {
+        ULONG ulMiscInfo;       /* The power level should be arranged in ascending order */
+        ULONG ulMiscInfo2;
+        ULONG ulEngineClock;
+        ULONG ulMemoryClock;
+        UCHAR ucVoltageDropIndex;       /*  index to Core (VDDC) votage table */
+        UCHAR ucSelectedPanel_RefreshRate;      /*  panel refresh rate */
+        UCHAR ucMinTemperature;
+        UCHAR ucMaxTemperature;
+        UCHAR ucNumPciELanes;   /*  number of PCIE lanes */
+        UCHAR ucVDDCI_VoltageDropIndex; /*  index to VDDCI votage table */
+} ATOM_POWERMODE_INFO_V3;
+
+#define ATOM_MAX_NUMBEROF_POWER_BLOCK  8
+
+#define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN            0x01
+#define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE         0x02
+
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63      0x01
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032   0x02
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030   0x03
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649   0x04
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64      0x05
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375    0x06
+#define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512   0x07      /*  Andigilog */
+
+typedef struct _ATOM_POWERPLAY_INFO {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        UCHAR ucOverdriveThermalController;
+        UCHAR ucOverdriveI2cLine;
+        UCHAR ucOverdriveIntBitmap;
+        UCHAR ucOverdriveControllerAddress;
+        UCHAR ucSizeOfPowerModeEntry;
+        UCHAR ucNumOfPowerModeEntries;
+        ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
+} ATOM_POWERPLAY_INFO;
+
+typedef struct _ATOM_POWERPLAY_INFO_V2 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        UCHAR ucOverdriveThermalController;
+        UCHAR ucOverdriveI2cLine;
+        UCHAR ucOverdriveIntBitmap;
+        UCHAR ucOverdriveControllerAddress;
+        UCHAR ucSizeOfPowerModeEntry;
+        UCHAR ucNumOfPowerModeEntries;
+        ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
+} ATOM_POWERPLAY_INFO_V2;
+
+typedef struct _ATOM_POWERPLAY_INFO_V3 {
+        ATOM_COMMON_TABLE_HEADER sHeader;
+        UCHAR ucOverdriveThermalController;
+        UCHAR ucOverdriveI2cLine;
+        UCHAR ucOverdriveIntBitmap;
+        UCHAR ucOverdriveControllerAddress;
+        UCHAR ucSizeOfPowerModeEntry;
+        UCHAR ucNumOfPowerModeEntries;
+        ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
+} ATOM_POWERPLAY_INFO_V3;
+
+/**************************************************************************/
+
+/*  Following definitions are for compatiblity issue in different SW components. */
+#define ATOM_MASTER_DATA_TABLE_REVISION   0x01
+#define Object_Info                                                                                             Object_Header
+#define AdjustARB_SEQ                                                                                   MC_InitParameter
+#define VRAM_GPIO_DetectionInfo                                         VoltageObjectInfo
+#define ASIC_VDDCI_Info                   ASIC_ProfilingInfo
+#define ASIC_MVDDQ_Info                                                                         MemoryTrainingInfo
+#define SS_Info                           PPLL_SS_Info
+#define ASIC_MVDDC_Info                   ASIC_InternalSS_Info
+#define DispDevicePriorityInfo                                          SaveRestoreInfo
+#define DispOutInfo                                                                                             TV_VideoMode
+
+#define ATOM_ENCODER_OBJECT_TABLE         ATOM_OBJECT_TABLE
+#define ATOM_CONNECTOR_OBJECT_TABLE       ATOM_OBJECT_TABLE
+
+/* New device naming, remove them when both DAL/VBIOS is ready */
+#define DFP2I_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
+#define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
+
+#define DFP1X_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
+#define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
+
+#define DFP1I_OUTPUT_CONTROL_PARAMETERS    DFP1_OUTPUT_CONTROL_PARAMETERS
+#define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
+
+#define ATOM_DEVICE_DFP1I_SUPPORT          ATOM_DEVICE_DFP1_SUPPORT
+#define ATOM_DEVICE_DFP1X_SUPPORT          ATOM_DEVICE_DFP2_SUPPORT
+
+#define ATOM_DEVICE_DFP1I_INDEX            ATOM_DEVICE_DFP1_INDEX
+#define ATOM_DEVICE_DFP1X_INDEX            ATOM_DEVICE_DFP2_INDEX
+
+#define ATOM_DEVICE_DFP2I_INDEX            0x00000009
+#define ATOM_DEVICE_DFP2I_SUPPORT          (0x1L << ATOM_DEVICE_DFP2I_INDEX)
+
+#define ATOM_S0_DFP1I                      ATOM_S0_DFP1
+#define ATOM_S0_DFP1X                      ATOM_S0_DFP2
+
+#define ATOM_S0_DFP2I                      0x00200000L
+#define ATOM_S0_DFP2Ib2                    0x20
+
+#define ATOM_S2_DFP1I_DPMS_STATE           ATOM_S2_DFP1_DPMS_STATE
+#define ATOM_S2_DFP1X_DPMS_STATE           ATOM_S2_DFP2_DPMS_STATE
+
+#define ATOM_S2_DFP2I_DPMS_STATE           0x02000000L
+#define ATOM_S2_DFP2I_DPMS_STATEb3         0x02
+
+#define ATOM_S3_DFP2I_ACTIVEb1             0x02
+
+#define ATOM_S3_DFP1I_ACTIVE               ATOM_S3_DFP1_ACTIVE
+#define ATOM_S3_DFP1X_ACTIVE               ATOM_S3_DFP2_ACTIVE
+
+#define ATOM_S3_DFP2I_ACTIVE               0x00000200L
+
+#define ATOM_S3_DFP1I_CRTC_ACTIVE          ATOM_S3_DFP1_CRTC_ACTIVE
+#define ATOM_S3_DFP1X_CRTC_ACTIVE          ATOM_S3_DFP2_CRTC_ACTIVE
+#define ATOM_S3_DFP2I_CRTC_ACTIVE          0x02000000L
+
+#define ATOM_S3_DFP2I_CRTC_ACTIVEb3        0x02
+#define ATOM_S5_DOS_REQ_DFP2Ib1            0x02
+
+#define ATOM_S5_DOS_REQ_DFP2I              0x0200
+#define ATOM_S6_ACC_REQ_DFP1I              ATOM_S6_ACC_REQ_DFP1
+#define ATOM_S6_ACC_REQ_DFP1X              ATOM_S6_ACC_REQ_DFP2
+
+#define ATOM_S6_ACC_REQ_DFP2Ib3            0x02
+#define ATOM_S6_ACC_REQ_DFP2I              0x02000000L
+
+#define TMDS1XEncoderControl               DVOEncoderControl
+#define DFP1XOutputControl                 DVOOutputControl
+
+#define ExternalDFPOutputControl           DFP1XOutputControl
+#define EnableExternalTMDS_Encoder         TMDS1XEncoderControl
+
+#define DFP1IOutputControl                 TMDSAOutputControl
+#define DFP2IOutputControl                 LVTMAOutputControl
+
+#define DAC1_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
+#define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
+
+#define DAC2_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
+#define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
+
+#define ucDac1Standard  ucDacStandard
+#define ucDac2Standard  ucDacStandard
+
+#define TMDS1EncoderControl TMDSAEncoderControl
+#define TMDS2EncoderControl LVTMAEncoderControl
+
+#define DFP1OutputControl   TMDSAOutputControl
+#define DFP2OutputControl   LVTMAOutputControl
+#define CRT1OutputControl   DAC1OutputControl
+#define CRT2OutputControl   DAC2OutputControl
+
+/* These two lines will be removed for sure in a few days, will follow up with Michael V. */
+#define EnableLVDS_SS   EnableSpreadSpectrumOnPPLL
+#define ENABLE_LVDS_SS_PARAMETERS_V3  ENABLE_SPREAD_SPECTRUM_ON_PPLL
+
+/*********************************************************************************/
+
+#pragma pack()                  /*  BIOS data must use byte aligment */
+
+#endif /* _ATOMBIOS_H */
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
new file mode 100644
index 000000000000..c0080cc9bf8d
--- /dev/null
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -0,0 +1,695 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/radeon_drm.h>
+#include "radeon_fixed.h"
+#include "radeon.h"
+#include "atom.h"
+#include "atom-bits.h"
+
+static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        int index =
+            GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
+        ENABLE_CRTC_PS_ALLOCATION args;
+
+        memset(&args, 0, sizeof(args));
+
+        args.ucCRTC = radeon_crtc->crtc_id;
+        args.ucEnable = lock;
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+
+static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
+        ENABLE_CRTC_PS_ALLOCATION args;
+
+        memset(&args, 0, sizeof(args));
+
+        args.ucCRTC = radeon_crtc->crtc_id;
+        args.ucEnable = state;
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+
+static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
+        ENABLE_CRTC_PS_ALLOCATION args;
+
+        memset(&args, 0, sizeof(args));
+
+        args.ucCRTC = radeon_crtc->crtc_id;
+        args.ucEnable = state;
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+
+static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
+        BLANK_CRTC_PS_ALLOCATION args;
+
+        memset(&args, 0, sizeof(args));
+
+        args.ucCRTC = radeon_crtc->crtc_id;
+        args.ucBlanking = state;
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+
+void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
+{
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+
+        switch (mode) {
+        case DRM_MODE_DPMS_ON:
+                if (ASIC_IS_DCE3(rdev))
+                        atombios_enable_crtc_memreq(crtc, 1);
+                atombios_enable_crtc(crtc, 1);
+                atombios_blank_crtc(crtc, 0);
+                break;
+        case DRM_MODE_DPMS_STANDBY:
+        case DRM_MODE_DPMS_SUSPEND:
+        case DRM_MODE_DPMS_OFF:
+                atombios_blank_crtc(crtc, 1);
+                atombios_enable_crtc(crtc, 0);
+                if (ASIC_IS_DCE3(rdev))
+                        atombios_enable_crtc_memreq(crtc, 0);
+                break;
+        }
+
+        if (mode != DRM_MODE_DPMS_OFF) {
+                radeon_crtc_load_lut(crtc);
+        }
+}
+
+static void
+atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
+                             SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param)
+{
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param;
+        int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
+
+        conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size);
+        conv_param.usH_Blanking_Time =
+            cpu_to_le16(crtc_param->usH_Blanking_Time);
+        conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size);
+        conv_param.usV_Blanking_Time =
+            cpu_to_le16(crtc_param->usV_Blanking_Time);
+        conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset);
+        conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
+        conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset);
+        conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
+        conv_param.susModeMiscInfo.usAccess =
+            cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
+        conv_param.ucCRTC = crtc_param->ucCRTC;
+
+        printk("executing set crtc dtd timing\n");
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
+}
+
+void atombios_crtc_set_timing(struct drm_crtc *crtc,
+                              SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *
+                              crtc_param)
+{
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
+        int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
+
+        conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total);
+        conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp);
+        conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart);
+        conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
+        conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total);
+        conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp);
+        conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart);
+        conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
+        conv_param.susModeMiscInfo.usAccess =
+            cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
+        conv_param.ucCRTC = crtc_param->ucCRTC;
+        conv_param.ucOverscanRight = crtc_param->ucOverscanRight;
+        conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft;
+        conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom;
+        conv_param.ucOverscanTop = crtc_param->ucOverscanTop;
+        conv_param.ucReserved = crtc_param->ucReserved;
+
+        printk("executing set crtc timing\n");
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
+}
+
+void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_encoder *encoder = NULL;
+        struct radeon_encoder *radeon_encoder = NULL;
+        uint8_t frev, crev;
+        int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
+        SET_PIXEL_CLOCK_PS_ALLOCATION args;
+        PIXEL_CLOCK_PARAMETERS *spc1_ptr;
+        PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
+        PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
+        uint32_t sclock = mode->clock;
+        uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
+        struct radeon_pll *pll;
+        int pll_flags = 0;
+
+        memset(&args, 0, sizeof(args));
+
+        if (ASIC_IS_AVIVO(rdev)) {
+                uint32_t ss_cntl;
+
+                if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
+                        pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
+                else
+                        pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+
+                /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
+                if (radeon_crtc->crtc_id == 0) {
+                        ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
+                        WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
+                } else {
+                        ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
+                        WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
+                }
+        } else {
+                pll_flags |= RADEON_PLL_LEGACY;
+
+                if (mode->clock > 200000)       /* range limits??? */
+                        pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
+                else
+                        pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+
+        }
+
+        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                if (encoder->crtc == crtc) {
+                        if (!ASIC_IS_AVIVO(rdev)) {
+                                if (encoder->encoder_type !=
+                                    DRM_MODE_ENCODER_DAC)
+                                        pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
+                                if (!ASIC_IS_AVIVO(rdev)
+                                    && (encoder->encoder_type ==
+                                        DRM_MODE_ENCODER_LVDS))
+                                        pll_flags |= RADEON_PLL_USE_REF_DIV;
+                        }
+                        radeon_encoder = to_radeon_encoder(encoder);
+                }
+        }
+
+        if (radeon_crtc->crtc_id == 0)
+                pll = &rdev->clock.p1pll;
+        else
+                pll = &rdev->clock.p2pll;
+
+        radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div,
+                           &ref_div, &post_div, pll_flags);
+
+        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
+                              &crev);
+
+        switch (frev) {
+        case 1:
+                switch (crev) {
+                case 1:
+                        spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
+                        spc1_ptr->usPixelClock = cpu_to_le16(sclock);
+                        spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
+                        spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
+                        spc1_ptr->ucFracFbDiv = frac_fb_div;
+                        spc1_ptr->ucPostDiv = post_div;
+                        spc1_ptr->ucPpll =
+                            radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+                        spc1_ptr->ucCRTC = radeon_crtc->crtc_id;
+                        spc1_ptr->ucRefDivSrc = 1;
+                        break;
+                case 2:
+                        spc2_ptr =
+                            (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
+                        spc2_ptr->usPixelClock = cpu_to_le16(sclock);
+                        spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
+                        spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
+                        spc2_ptr->ucFracFbDiv = frac_fb_div;
+                        spc2_ptr->ucPostDiv = post_div;
+                        spc2_ptr->ucPpll =
+                            radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+                        spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
+                        spc2_ptr->ucRefDivSrc = 1;
+                        break;
+                case 3:
+                        if (!encoder)
+                                return;
+                        spc3_ptr =
+                            (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
+                        spc3_ptr->usPixelClock = cpu_to_le16(sclock);
+                        spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
+                        spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
+                        spc3_ptr->ucFracFbDiv = frac_fb_div;
+                        spc3_ptr->ucPostDiv = post_div;
+                        spc3_ptr->ucPpll =
+                            radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
+                        spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
+                        spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id;
+                        spc3_ptr->ucEncoderMode =
+                            atombios_get_encoder_mode(encoder);
+                        break;
+                default:
+                        DRM_ERROR("Unknown table version %d %d\n", frev, crev);
+                        return;
+                }
+                break;
+        default:
+                DRM_ERROR("Unknown table version %d %d\n", frev, crev);
+                return;
+        }
+
+        printk("executing set pll\n");
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+
+int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
+                           struct drm_framebuffer *old_fb)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_framebuffer *radeon_fb;
+        struct drm_gem_object *obj;
+        struct drm_radeon_gem_object *obj_priv;
+        uint64_t fb_location;
+        uint32_t fb_format, fb_pitch_pixels;
+
+        if (!crtc->fb)
+                return -EINVAL;
+
+        radeon_fb = to_radeon_framebuffer(crtc->fb);
+
+        obj = radeon_fb->obj;
+        obj_priv = obj->driver_private;
+
+        if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) {
+                return -EINVAL;
+        }
+
+        switch (crtc->fb->bits_per_pixel) {
+        case 15:
+                fb_format =
+                    AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
+                    AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
+                break;
+        case 16:
+                fb_format =
+                    AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
+                    AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
+                break;
+        case 24:
+        case 32:
+                fb_format =
+                    AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
+                    AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
+                break;
+        default:
+                DRM_ERROR("Unsupported screen depth %d\n",
+                          crtc->fb->bits_per_pixel);
+                return -EINVAL;
+        }
+
+        /* TODO tiling */
+        if (radeon_crtc->crtc_id == 0)
+                WREG32(AVIVO_D1VGA_CONTROL, 0);
+        else
+                WREG32(AVIVO_D2VGA_CONTROL, 0);
+        WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
+               (u32) fb_location);
+        WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
+               radeon_crtc->crtc_offset, (u32) fb_location);
+        WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
+
+        WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
+        WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
+        WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
+        WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
+        WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
+        WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
+
+        fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
+        WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
+        WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
+
+        WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
+               crtc->mode.vdisplay);
+        x &= ~3;
+        y &= ~1;
+        WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
+               (x << 16) | y);
+        WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
+               (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
+
+        if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
+                WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
+                       AVIVO_D1MODE_INTERLEAVE_EN);
+        else
+                WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
+
+        if (old_fb && old_fb != crtc->fb) {
+                radeon_fb = to_radeon_framebuffer(old_fb);
+                radeon_gem_object_unpin(radeon_fb->obj);
+        }
+        return 0;
+}
+
+int atombios_crtc_mode_set(struct drm_crtc *crtc,
+                           struct drm_display_mode *mode,
+                           struct drm_display_mode *adjusted_mode,
+                           int x, int y, struct drm_framebuffer *old_fb)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_encoder *encoder;
+        SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
+
+        /* TODO color tiling */
+        memset(&crtc_timing, 0, sizeof(crtc_timing));
+
+        /* TODO tv */
+        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+
+        }
+
+        crtc_timing.ucCRTC = radeon_crtc->crtc_id;
+        crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
+        crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
+        crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
+        crtc_timing.usH_SyncWidth =
+            adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
+
+        crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
+        crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
+        crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
+        crtc_timing.usV_SyncWidth =
+            adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
+
+        if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+                crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
+
+        if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+                crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
+
+        if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
+                crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
+
+        if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+                crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
+
+        if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
+                crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
+
+        atombios_crtc_set_pll(crtc, adjusted_mode);
+        atombios_crtc_set_timing(crtc, &crtc_timing);
+
+        if (ASIC_IS_AVIVO(rdev))
+                atombios_crtc_set_base(crtc, x, y, old_fb);
+        else {
+                if (radeon_crtc->crtc_id == 0) {
+                        SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing;
+                        memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing));
+
+                        /* setup FP shadow regs on R4xx */
+                        crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id;
+                        crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay;
+                        crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay;
+                        crtc_dtd_timing.usH_Blanking_Time =
+                            adjusted_mode->crtc_hblank_end -
+                            adjusted_mode->crtc_hdisplay;
+                        crtc_dtd_timing.usV_Blanking_Time =
+                            adjusted_mode->crtc_vblank_end -
+                            adjusted_mode->crtc_vdisplay;
+                        crtc_dtd_timing.usH_SyncOffset =
+                            adjusted_mode->crtc_hsync_start -
+                            adjusted_mode->crtc_hdisplay;
+                        crtc_dtd_timing.usV_SyncOffset =
+                            adjusted_mode->crtc_vsync_start -
+                            adjusted_mode->crtc_vdisplay;
+                        crtc_dtd_timing.usH_SyncWidth =
+                            adjusted_mode->crtc_hsync_end -
+                            adjusted_mode->crtc_hsync_start;
+                        crtc_dtd_timing.usV_SyncWidth =
+                            adjusted_mode->crtc_vsync_end -
+                            adjusted_mode->crtc_vsync_start;
+                        /* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */
+                        /* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */
+
+                        if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+                                crtc_dtd_timing.susModeMiscInfo.usAccess |=
+                                    ATOM_VSYNC_POLARITY;
+
+                        if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+                                crtc_dtd_timing.susModeMiscInfo.usAccess |=
+                                    ATOM_HSYNC_POLARITY;
+
+                        if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
+                                crtc_dtd_timing.susModeMiscInfo.usAccess |=
+                                    ATOM_COMPOSITESYNC;
+
+                        if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
+                                crtc_dtd_timing.susModeMiscInfo.usAccess |=
+                                    ATOM_INTERLACE;
+
+                        if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
+                                crtc_dtd_timing.susModeMiscInfo.usAccess |=
+                                    ATOM_DOUBLE_CLOCK_MODE;
+
+                        atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing);
+                }
+                radeon_crtc_set_base(crtc, x, y, old_fb);
+                radeon_legacy_atom_set_surface(crtc);
+        }
+        return 0;
+}
+
+static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
+                                     struct drm_display_mode *mode,
+                                     struct drm_display_mode *adjusted_mode)
+{
+        return true;
+}
+
+static void atombios_crtc_prepare(struct drm_crtc *crtc)
+{
+        atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
+        atombios_lock_crtc(crtc, 1);
+}
+
+static void atombios_crtc_commit(struct drm_crtc *crtc)
+{
+        atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
+        atombios_lock_crtc(crtc, 0);
+}
+
+static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
+        .dpms = atombios_crtc_dpms,
+        .mode_fixup = atombios_crtc_mode_fixup,
+        .mode_set = atombios_crtc_mode_set,
+        .mode_set_base = atombios_crtc_set_base,
+        .prepare = atombios_crtc_prepare,
+        .commit = atombios_crtc_commit,
+};
+
+void radeon_atombios_init_crtc(struct drm_device *dev,
+                               struct radeon_crtc *radeon_crtc)
+{
+        if (radeon_crtc->crtc_id == 1)
+                radeon_crtc->crtc_offset =
+                    AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
+        drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
+}
+
+void radeon_init_disp_bw_avivo(struct drm_device *dev,
+                               struct drm_display_mode *mode1,
+                               uint32_t pixel_bytes1,
+                               struct drm_display_mode *mode2,
+                               uint32_t pixel_bytes2)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        fixed20_12 min_mem_eff;
+        fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
+        fixed20_12 sclk_ff, mclk_ff;
+        uint32_t dc_lb_memory_split, temp;
+
+        min_mem_eff.full = rfixed_const_8(0);
+        if (rdev->disp_priority == 2) {
+                uint32_t mc_init_misc_lat_timer = 0;
+                if (rdev->family == CHIP_RV515)
+                        mc_init_misc_lat_timer =
+                            RREG32_MC(RV515_MC_INIT_MISC_LAT_TIMER);
+                else if (rdev->family == CHIP_RS690)
+                        mc_init_misc_lat_timer =
+                            RREG32_MC(RS690_MC_INIT_MISC_LAT_TIMER);
+
+                mc_init_misc_lat_timer &=
+                    ~(R300_MC_DISP1R_INIT_LAT_MASK <<
+                      R300_MC_DISP1R_INIT_LAT_SHIFT);
+                mc_init_misc_lat_timer &=
+                    ~(R300_MC_DISP0R_INIT_LAT_MASK <<
+                      R300_MC_DISP0R_INIT_LAT_SHIFT);
+
+                if (mode2)
+                        mc_init_misc_lat_timer |=
+                            (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
+                if (mode1)
+                        mc_init_misc_lat_timer |=
+                            (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
+
+                if (rdev->family == CHIP_RV515)
+                        WREG32_MC(RV515_MC_INIT_MISC_LAT_TIMER,
+                                  mc_init_misc_lat_timer);
+                else if (rdev->family == CHIP_RS690)
+                        WREG32_MC(RS690_MC_INIT_MISC_LAT_TIMER,
+                                  mc_init_misc_lat_timer);
+        }
+
+        /*
+         * determine is there is enough bw for current mode
+         */
+        temp_ff.full = rfixed_const(100);
+        mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
+        mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
+        sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
+        sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
+
+        temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
+        temp_ff.full = rfixed_const(temp);
+        mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
+        mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
+
+        pix_clk.full = 0;
+        pix_clk2.full = 0;
+        peak_disp_bw.full = 0;
+        if (mode1) {
+                temp_ff.full = rfixed_const(1000);
+                pix_clk.full = rfixed_const(mode1->clock);      /* convert to fixed point */
+                pix_clk.full = rfixed_div(pix_clk, temp_ff);
+                temp_ff.full = rfixed_const(pixel_bytes1);
+                peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
+        }
+        if (mode2) {
+                temp_ff.full = rfixed_const(1000);
+                pix_clk2.full = rfixed_const(mode2->clock);     /* convert to fixed point */
+                pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
+                temp_ff.full = rfixed_const(pixel_bytes2);
+                peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
+        }
+
+        if (peak_disp_bw.full >= mem_bw.full) {
+                DRM_ERROR
+                    ("You may not have enough display bandwidth for current mode\n"
+                     "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
+                printk("peak disp bw %d, mem_bw %d\n",
+                       rfixed_trunc(peak_disp_bw), rfixed_trunc(mem_bw));
+        }
+
+        /*
+         * Line Buffer Setup
+         * There is a single line buffer shared by both display controllers.
+         * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between the display
+         * controllers.  The paritioning can either be done manually or via one of four
+         * preset allocations specified in bits 1:0:
+         * 0 - line buffer is divided in half and shared between each display controller
+         * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
+         * 2 - D1 gets the whole buffer
+         * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
+         * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual allocation mode.
+         * In manual allocation mode, D1 always starts at 0, D1 end/2 is specified in bits
+         * 14:4; D2 allocation follows D1.
+         */
+
+        /* is auto or manual better ? */
+        dc_lb_memory_split =
+            RREG32(AVIVO_DC_LB_MEMORY_SPLIT) & ~AVIVO_DC_LB_MEMORY_SPLIT_MASK;
+        dc_lb_memory_split &= ~AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE;
+#if 1
+        /* auto */
+        if (mode1 && mode2) {
+                if (mode1->hdisplay > mode2->hdisplay) {
+                        if (mode1->hdisplay > 2560)
+                                dc_lb_memory_split |=
+                                    AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
+                        else
+                                dc_lb_memory_split |=
+                                    AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
+                } else if (mode2->hdisplay > mode1->hdisplay) {
+                        if (mode2->hdisplay > 2560)
+                                dc_lb_memory_split |=
+                                    AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
+                        else
+                                dc_lb_memory_split |=
+                                    AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
+                } else
+                        dc_lb_memory_split |=
+                            AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
+        } else if (mode1) {
+                dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY;
+        } else if (mode2) {
+                dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
+        }
+#else
+        /* manual */
+        dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE;
+        dc_lb_memory_split &=
+            ~(AVIVO_DC_LB_DISP1_END_ADR_MASK <<
+              AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
+        if (mode1) {
+                dc_lb_memory_split |=
+                    ((((mode1->hdisplay / 2) + 64) & AVIVO_DC_LB_DISP1_END_ADR_MASK)
+                     << AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
+        } else if (mode2) {
+                dc_lb_memory_split |= (0 << AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
+        }
+#endif
+        WREG32(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split);
+}
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
new file mode 100644
index 000000000000..5225f5be7ea7
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -0,0 +1,1524 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include <linux/seq_file.h>
+#include "drmP.h"
+#include "drm.h"
+#include "radeon_drm.h"
+#include "radeon_microcode.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+/* This files gather functions specifics to:
+ * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
+ *
+ * Some of these functions might be used by newer ASICs.
+ */
+void r100_hdp_reset(struct radeon_device *rdev);
+void r100_gpu_init(struct radeon_device *rdev);
+int r100_gui_wait_for_idle(struct radeon_device *rdev);
+int r100_mc_wait_for_idle(struct radeon_device *rdev);
+void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
+void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
+int r100_debugfs_mc_info_init(struct radeon_device *rdev);
+
+
+/*
+ * PCI GART
+ */
+void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
+{
+        /* TODO: can we do somethings here ? */
+        /* It seems hw only cache one entry so we should discard this
+         * entry otherwise if first GPU GART read hit this entry it
+         * could end up in wrong address. */
+}
+
+int r100_pci_gart_enable(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        int r;
+
+        /* Initialize common gart structure */
+        r = radeon_gart_init(rdev);
+        if (r) {
+                return r;
+        }
+        if (rdev->gart.table.ram.ptr == NULL) {
+                rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
+                r = radeon_gart_table_ram_alloc(rdev);
+                if (r) {
+                        return r;
+                }
+        }
+        /* discard memory request outside of configured range */
+        tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
+        WREG32(RADEON_AIC_CNTL, tmp);
+        /* set address range for PCI address translate */
+        WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
+        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
+        WREG32(RADEON_AIC_HI_ADDR, tmp);
+        /* Enable bus mastering */
+        tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
+        WREG32(RADEON_BUS_CNTL, tmp);
+        /* set PCI GART page-table base address */
+        WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
+        tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
+        WREG32(RADEON_AIC_CNTL, tmp);
+        r100_pci_gart_tlb_flush(rdev);
+        rdev->gart.ready = true;
+        return 0;
+}
+
+void r100_pci_gart_disable(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        /* discard memory request outside of configured range */
+        tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
+        WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
+        WREG32(RADEON_AIC_LO_ADDR, 0);
+        WREG32(RADEON_AIC_HI_ADDR, 0);
+}
+
+int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
+{
+        if (i < 0 || i > rdev->gart.num_gpu_pages) {
+                return -EINVAL;
+        }
+        rdev->gart.table.ram.ptr[i] = cpu_to_le32((uint32_t)addr);
+        return 0;
+}
+
+int r100_gart_enable(struct radeon_device *rdev)
+{
+        if (rdev->flags & RADEON_IS_AGP) {
+                r100_pci_gart_disable(rdev);
+                return 0;
+        }
+        return r100_pci_gart_enable(rdev);
+}
+
+
+/*
+ * MC
+ */
+void r100_mc_disable_clients(struct radeon_device *rdev)
+{
+        uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
+
+        /* FIXME: is this function correct for rs100,rs200,rs300 ? */
+        if (r100_gui_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait GUI idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+
+        /* stop display and memory access */
+        ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
+        WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
+        crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
+        WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
+        crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
+
+        r100_gpu_wait_for_vsync(rdev);
+
+        WREG32(RADEON_CRTC_GEN_CNTL,
+               (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
+               RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
+
+        if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+                crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
+
+                r100_gpu_wait_for_vsync2(rdev);
+                WREG32(RADEON_CRTC2_GEN_CNTL,
+                       (crtc2_gen_cntl &
+                        ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
+                       RADEON_CRTC2_DISP_REQ_EN_B);
+        }
+
+        udelay(500);
+}
+
+void r100_mc_setup(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        int r;
+
+        r = r100_debugfs_mc_info_init(rdev);
+        if (r) {
+                DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
+        }
+        /* Write VRAM size in case we are limiting it */
+        WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+        tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+        tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
+        tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
+        WREG32(RADEON_MC_FB_LOCATION, tmp);
+
+        /* Enable bus mastering */
+        tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
+        WREG32(RADEON_BUS_CNTL, tmp);
+
+        if (rdev->flags & RADEON_IS_AGP) {
+                tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
+                tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
+                tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
+                WREG32(RADEON_MC_AGP_LOCATION, tmp);
+                WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
+        } else {
+                WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
+                WREG32(RADEON_AGP_BASE, 0);
+        }
+
+        tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
+        tmp |= (7 << 28);
+        WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
+        (void)RREG32(RADEON_HOST_PATH_CNTL);
+        WREG32(RADEON_HOST_PATH_CNTL, tmp);
+        (void)RREG32(RADEON_HOST_PATH_CNTL);
+}
+
+int r100_mc_init(struct radeon_device *rdev)
+{
+        int r;
+
+        if (r100_debugfs_rbbm_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
+        }
+
+        r100_gpu_init(rdev);
+        /* Disable gart which also disable out of gart access */
+        r100_pci_gart_disable(rdev);
+
+        /* Setup GPU memory space */
+        rdev->mc.vram_location = 0xFFFFFFFFUL;
+        rdev->mc.gtt_location = 0xFFFFFFFFUL;
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r) {
+                        printk(KERN_WARNING "[drm] Disabling AGP\n");
+                        rdev->flags &= ~RADEON_IS_AGP;
+                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+                } else {
+                        rdev->mc.gtt_location = rdev->mc.agp_base;
+                }
+        }
+        r = radeon_mc_setup(rdev);
+        if (r) {
+                return r;
+        }
+
+        r100_mc_disable_clients(rdev);
+        if (r100_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+
+        r100_mc_setup(rdev);
+        return 0;
+}
+
+void r100_mc_fini(struct radeon_device *rdev)
+{
+        r100_pci_gart_disable(rdev);
+        radeon_gart_table_ram_free(rdev);
+        radeon_gart_fini(rdev);
+}
+
+
+/*
+ * Fence emission
+ */
+void r100_fence_ring_emit(struct radeon_device *rdev,
+                          struct radeon_fence *fence)
+{
+        /* Who ever call radeon_fence_emit should call ring_lock and ask
+         * for enough space (today caller are ib schedule and buffer move) */
+        /* Wait until IDLE & CLEAN */
+        radeon_ring_write(rdev, PACKET0(0x1720, 0));
+        radeon_ring_write(rdev, (1 << 16) | (1 << 17));
+        /* Emit fence sequence & fire IRQ */
+        radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
+        radeon_ring_write(rdev, fence->seq);
+        radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
+        radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
+}
+
+
+/*
+ * Writeback
+ */
+int r100_wb_init(struct radeon_device *rdev)
+{
+        int r;
+
+        if (rdev->wb.wb_obj == NULL) {
+                r = radeon_object_create(rdev, NULL, 4096,
+                                         true,
+                                         RADEON_GEM_DOMAIN_GTT,
+                                         false, &rdev->wb.wb_obj);
+                if (r) {
+                        DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
+                        return r;
+                }
+                r = radeon_object_pin(rdev->wb.wb_obj,
+                                      RADEON_GEM_DOMAIN_GTT,
+                                      &rdev->wb.gpu_addr);
+                if (r) {
+                        DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
+                        return r;
+                }
+                r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
+                if (r) {
+                        DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
+                        return r;
+                }
+        }
+        WREG32(0x774, rdev->wb.gpu_addr);
+        WREG32(0x70C, rdev->wb.gpu_addr + 1024);
+        WREG32(0x770, 0xff);
+        return 0;
+}
+
+void r100_wb_fini(struct radeon_device *rdev)
+{
+        if (rdev->wb.wb_obj) {
+                radeon_object_kunmap(rdev->wb.wb_obj);
+                radeon_object_unpin(rdev->wb.wb_obj);
+                radeon_object_unref(&rdev->wb.wb_obj);
+                rdev->wb.wb = NULL;
+                rdev->wb.wb_obj = NULL;
+        }
+}
+
+int r100_copy_blit(struct radeon_device *rdev,
+                   uint64_t src_offset,
+                   uint64_t dst_offset,
+                   unsigned num_pages,
+                   struct radeon_fence *fence)
+{
+        uint32_t cur_pages;
+        uint32_t stride_bytes = PAGE_SIZE;
+        uint32_t pitch;
+        uint32_t stride_pixels;
+        unsigned ndw;
+        int num_loops;
+        int r = 0;
+
+        /* radeon limited to 16k stride */
+        stride_bytes &= 0x3fff;
+        /* radeon pitch is /64 */
+        pitch = stride_bytes / 64;
+        stride_pixels = stride_bytes / 4;
+        num_loops = DIV_ROUND_UP(num_pages, 8191);
+
+        /* Ask for enough room for blit + flush + fence */
+        ndw = 64 + (10 * num_loops);
+        r = radeon_ring_lock(rdev, ndw);
+        if (r) {
+                DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
+                return -EINVAL;
+        }
+        while (num_pages > 0) {
+                cur_pages = num_pages;
+                if (cur_pages > 8191) {
+                        cur_pages = 8191;
+                }
+                num_pages -= cur_pages;
+
+                /* pages are in Y direction - height
+                   page width in X direction - width */
+                radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
+                radeon_ring_write(rdev,
+                                  RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
+                                  RADEON_GMC_DST_PITCH_OFFSET_CNTL |
+                                  RADEON_GMC_SRC_CLIPPING |
+                                  RADEON_GMC_DST_CLIPPING |
+                                  RADEON_GMC_BRUSH_NONE |
+                                  (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
+                                  RADEON_GMC_SRC_DATATYPE_COLOR |
+                                  RADEON_ROP3_S |
+                                  RADEON_DP_SRC_SOURCE_MEMORY |
+                                  RADEON_GMC_CLR_CMP_CNTL_DIS |
+                                  RADEON_GMC_WR_MSK_DIS);
+                radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
+                radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
+                radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
+                radeon_ring_write(rdev, 0);
+                radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
+                radeon_ring_write(rdev, num_pages);
+                radeon_ring_write(rdev, num_pages);
+                radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
+        }
+        radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
+        radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
+        radeon_ring_write(rdev,
+                          RADEON_WAIT_2D_IDLECLEAN |
+                          RADEON_WAIT_HOST_IDLECLEAN |
+                          RADEON_WAIT_DMA_GUI_IDLE);
+        if (fence) {
+                r = radeon_fence_emit(rdev, fence);
+        }
+        radeon_ring_unlock_commit(rdev);
+        return r;
+}
+
+
+/*
+ * CP
+ */
+void r100_ring_start(struct radeon_device *rdev)
+{
+        int r;
+
+        r = radeon_ring_lock(rdev, 2);
+        if (r) {
+                return;
+        }
+        radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
+        radeon_ring_write(rdev,
+                          RADEON_ISYNC_ANY2D_IDLE3D |
+                          RADEON_ISYNC_ANY3D_IDLE2D |
+                          RADEON_ISYNC_WAIT_IDLEGUI |
+                          RADEON_ISYNC_CPSCRATCH_IDLEGUI);
+        radeon_ring_unlock_commit(rdev);
+}
+
+static void r100_cp_load_microcode(struct radeon_device *rdev)
+{
+        int i;
+
+        if (r100_gui_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait GUI idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+
+        WREG32(RADEON_CP_ME_RAM_ADDR, 0);
+        if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
+            (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
+            (rdev->family == CHIP_RS200)) {
+                DRM_INFO("Loading R100 Microcode\n");
+                for (i = 0; i < 256; i++) {
+                        WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
+                        WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
+                }
+        } else if ((rdev->family == CHIP_R200) ||
+                   (rdev->family == CHIP_RV250) ||
+                   (rdev->family == CHIP_RV280) ||
+                   (rdev->family == CHIP_RS300)) {
+                DRM_INFO("Loading R200 Microcode\n");
+                for (i = 0; i < 256; i++) {
+                        WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
+                        WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
+                }
+        } else if ((rdev->family == CHIP_R300) ||
+                   (rdev->family == CHIP_R350) ||
+                   (rdev->family == CHIP_RV350) ||
+                   (rdev->family == CHIP_RV380) ||
+                   (rdev->family == CHIP_RS400) ||
+                   (rdev->family == CHIP_RS480)) {
+                DRM_INFO("Loading R300 Microcode\n");
+                for (i = 0; i < 256; i++) {
+                        WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
+                        WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
+                }
+        } else if ((rdev->family == CHIP_R420) ||
+                   (rdev->family == CHIP_R423) ||
+                   (rdev->family == CHIP_RV410)) {
+                DRM_INFO("Loading R400 Microcode\n");
+                for (i = 0; i < 256; i++) {
+                        WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
+                        WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
+                }
+        } else if ((rdev->family == CHIP_RS690) ||
+                   (rdev->family == CHIP_RS740)) {
+                DRM_INFO("Loading RS690/RS740 Microcode\n");
+                for (i = 0; i < 256; i++) {
+                        WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
+                        WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
+                }
+        } else if (rdev->family == CHIP_RS600) {
+                DRM_INFO("Loading RS600 Microcode\n");
+                for (i = 0; i < 256; i++) {
+                        WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
+                        WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
+                }
+        } else if ((rdev->family == CHIP_RV515) ||
+                   (rdev->family == CHIP_R520) ||
+                   (rdev->family == CHIP_RV530) ||
+                   (rdev->family == CHIP_R580) ||
+                   (rdev->family == CHIP_RV560) ||
+                   (rdev->family == CHIP_RV570)) {
+                DRM_INFO("Loading R500 Microcode\n");
+                for (i = 0; i < 256; i++) {
+                        WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
+                        WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
+                }
+        }
+}
+
+int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
+{
+        unsigned rb_bufsz;
+        unsigned rb_blksz;
+        unsigned max_fetch;
+        unsigned pre_write_timer;
+        unsigned pre_write_limit;
+        unsigned indirect2_start;
+        unsigned indirect1_start;
+        uint32_t tmp;
+        int r;
+
+        if (r100_debugfs_cp_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for CP !\n");
+        }
+        /* Reset CP */
+        tmp = RREG32(RADEON_CP_CSQ_STAT);
+        if ((tmp & (1 << 31))) {
+                DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
+                WREG32(RADEON_CP_CSQ_MODE, 0);
+                WREG32(RADEON_CP_CSQ_CNTL, 0);
+                WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
+                tmp = RREG32(RADEON_RBBM_SOFT_RESET);
+                mdelay(2);
+                WREG32(RADEON_RBBM_SOFT_RESET, 0);
+                tmp = RREG32(RADEON_RBBM_SOFT_RESET);
+                mdelay(2);
+                tmp = RREG32(RADEON_CP_CSQ_STAT);
+                if ((tmp & (1 << 31))) {
+                        DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
+                }
+        } else {
+                DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
+        }
+        /* Align ring size */
+        rb_bufsz = drm_order(ring_size / 8);
+        ring_size = (1 << (rb_bufsz + 1)) * 4;
+        r100_cp_load_microcode(rdev);
+        r = radeon_ring_init(rdev, ring_size);
+        if (r) {
+                return r;
+        }
+        /* Each time the cp read 1024 bytes (16 dword/quadword) update
+         * the rptr copy in system ram */
+        rb_blksz = 9;
+        /* cp will read 128bytes at a time (4 dwords) */
+        max_fetch = 1;
+        rdev->cp.align_mask = 16 - 1;
+        /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
+        pre_write_timer = 64;
+        /* Force CP_RB_WPTR write if written more than one time before the
+         * delay expire
+         */
+        pre_write_limit = 0;
+        /* Setup the cp cache like this (cache size is 96 dwords) :
+         *      RING            0  to 15
+         *      INDIRECT1       16 to 79
+         *      INDIRECT2       80 to 95
+         * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
+         *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
+         *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
+         * Idea being that most of the gpu cmd will be through indirect1 buffer
+         * so it gets the bigger cache.
+         */
+        indirect2_start = 80;
+        indirect1_start = 16;
+        /* cp setup */
+        WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
+        WREG32(RADEON_CP_RB_CNTL,
+               REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
+               REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
+               REG_SET(RADEON_MAX_FETCH, max_fetch) |
+               RADEON_RB_NO_UPDATE);
+        /* Set ring address */
+        DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
+        WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
+        /* Force read & write ptr to 0 */
+        tmp = RREG32(RADEON_CP_RB_CNTL);
+        WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
+        WREG32(RADEON_CP_RB_RPTR_WR, 0);
+        WREG32(RADEON_CP_RB_WPTR, 0);
+        WREG32(RADEON_CP_RB_CNTL, tmp);
+        udelay(10);
+        rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
+        rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
+        /* Set cp mode to bus mastering & enable cp*/
+        WREG32(RADEON_CP_CSQ_MODE,
+               REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
+               REG_SET(RADEON_INDIRECT1_START, indirect1_start));
+        WREG32(0x718, 0);
+        WREG32(0x744, 0x00004D4D);
+        WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
+        radeon_ring_start(rdev);
+        r = radeon_ring_test(rdev);
+        if (r) {
+                DRM_ERROR("radeon: cp isn't working (%d).\n", r);
+                return r;
+        }
+        rdev->cp.ready = true;
+        return 0;
+}
+
+void r100_cp_fini(struct radeon_device *rdev)
+{
+        /* Disable ring */
+        rdev->cp.ready = false;
+        WREG32(RADEON_CP_CSQ_CNTL, 0);
+        radeon_ring_fini(rdev);
+        DRM_INFO("radeon: cp finalized\n");
+}
+
+void r100_cp_disable(struct radeon_device *rdev)
+{
+        /* Disable ring */
+        rdev->cp.ready = false;
+        WREG32(RADEON_CP_CSQ_MODE, 0);
+        WREG32(RADEON_CP_CSQ_CNTL, 0);
+        if (r100_gui_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait GUI idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+}
+
+int r100_cp_reset(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        bool reinit_cp;
+        int i;
+
+        reinit_cp = rdev->cp.ready;
+        rdev->cp.ready = false;
+        WREG32(RADEON_CP_CSQ_MODE, 0);
+        WREG32(RADEON_CP_CSQ_CNTL, 0);
+        WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
+        (void)RREG32(RADEON_RBBM_SOFT_RESET);
+        udelay(200);
+        WREG32(RADEON_RBBM_SOFT_RESET, 0);
+        /* Wait to prevent race in RBBM_STATUS */
+        mdelay(1);
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                tmp = RREG32(RADEON_RBBM_STATUS);
+                if (!(tmp & (1 << 16))) {
+                        DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
+                                 tmp);
+                        if (reinit_cp) {
+                                return r100_cp_init(rdev, rdev->cp.ring_size);
+                        }
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        tmp = RREG32(RADEON_RBBM_STATUS);
+        DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
+        return -1;
+}
+
+
+/*
+ * CS functions
+ */
+int r100_cs_parse_packet0(struct radeon_cs_parser *p,
+                          struct radeon_cs_packet *pkt,
+                          unsigned *auth, unsigned n,
+                          radeon_packet0_check_t check)
+{
+        unsigned reg;
+        unsigned i, j, m;
+        unsigned idx;
+        int r;
+
+        idx = pkt->idx + 1;
+        reg = pkt->reg;
+        if (pkt->one_reg_wr) {
+                if ((reg >> 7) > n) {
+                        return -EINVAL;
+                }
+        } else {
+                if (((reg + (pkt->count << 2)) >> 7) > n) {
+                        return -EINVAL;
+                }
+        }
+        for (i = 0; i <= pkt->count; i++, idx++) {
+                j = (reg >> 7);
+                m = 1 << ((reg >> 2) & 31);
+                if (auth[j] & m) {
+                        r = check(p, pkt, idx, reg);
+                        if (r) {
+                                return r;
+                        }
+                }
+                if (pkt->one_reg_wr) {
+                        if (!(auth[j] & m)) {
+                                break;
+                        }
+                } else {
+                        reg += 4;
+                }
+        }
+        return 0;
+}
+
+int r100_cs_parse_packet3(struct radeon_cs_parser *p,
+                          struct radeon_cs_packet *pkt,
+                          unsigned *auth, unsigned n,
+                          radeon_packet3_check_t check)
+{
+        unsigned i, m;
+
+        if ((pkt->opcode >> 5) > n) {
+                return -EINVAL;
+        }
+        i = pkt->opcode >> 5;
+        m = 1 << (pkt->opcode & 31);
+        if (auth[i] & m) {
+                return check(p, pkt);
+        }
+        return 0;
+}
+
+void r100_cs_dump_packet(struct radeon_cs_parser *p,
+                         struct radeon_cs_packet *pkt)
+{
+        struct radeon_cs_chunk *ib_chunk;
+        volatile uint32_t *ib;
+        unsigned i;
+        unsigned idx;
+
+        ib = p->ib->ptr;
+        ib_chunk = &p->chunks[p->chunk_ib_idx];
+        idx = pkt->idx;
+        for (i = 0; i <= (pkt->count + 1); i++, idx++) {
+                DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
+        }
+}
+
+/**
+ * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
+ * @parser:     parser structure holding parsing context.
+ * @pkt:        where to store packet informations
+ *
+ * Assume that chunk_ib_index is properly set. Will return -EINVAL
+ * if packet is bigger than remaining ib size. or if packets is unknown.
+ **/
+int r100_cs_packet_parse(struct radeon_cs_parser *p,
+                         struct radeon_cs_packet *pkt,
+                         unsigned idx)
+{
+        struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
+        uint32_t header = ib_chunk->kdata[idx];
+
+        if (idx >= ib_chunk->length_dw) {
+                DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
+                          idx, ib_chunk->length_dw);
+                return -EINVAL;
+        }
+        pkt->idx = idx;
+        pkt->type = CP_PACKET_GET_TYPE(header);
+        pkt->count = CP_PACKET_GET_COUNT(header);
+        switch (pkt->type) {
+        case PACKET_TYPE0:
+                pkt->reg = CP_PACKET0_GET_REG(header);
+                pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
+                break;
+        case PACKET_TYPE3:
+                pkt->opcode = CP_PACKET3_GET_OPCODE(header);
+                break;
+        case PACKET_TYPE2:
+                pkt->count = -1;
+                break;
+        default:
+                DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
+                return -EINVAL;
+        }
+        if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
+                DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
+                          pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
+                return -EINVAL;
+        }
+        return 0;
+}
+
+/**
+ * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
+ * @parser:             parser structure holding parsing context.
+ * @data:               pointer to relocation data
+ * @offset_start:       starting offset
+ * @offset_mask:        offset mask (to align start offset on)
+ * @reloc:              reloc informations
+ *
+ * Check next packet is relocation packet3, do bo validation and compute
+ * GPU offset using the provided start.
+ **/
+int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
+                              struct radeon_cs_reloc **cs_reloc)
+{
+        struct radeon_cs_chunk *ib_chunk;
+        struct radeon_cs_chunk *relocs_chunk;
+        struct radeon_cs_packet p3reloc;
+        unsigned idx;
+        int r;
+
+        if (p->chunk_relocs_idx == -1) {
+                DRM_ERROR("No relocation chunk !\n");
+                return -EINVAL;
+        }
+        *cs_reloc = NULL;
+        ib_chunk = &p->chunks[p->chunk_ib_idx];
+        relocs_chunk = &p->chunks[p->chunk_relocs_idx];
+        r = r100_cs_packet_parse(p, &p3reloc, p->idx);
+        if (r) {
+                return r;
+        }
+        p->idx += p3reloc.count + 2;
+        if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
+                DRM_ERROR("No packet3 for relocation for packet at %d.\n",
+                          p3reloc.idx);
+                r100_cs_dump_packet(p, &p3reloc);
+                return -EINVAL;
+        }
+        idx = ib_chunk->kdata[p3reloc.idx + 1];
+        if (idx >= relocs_chunk->length_dw) {
+                DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
+                          idx, relocs_chunk->length_dw);
+                r100_cs_dump_packet(p, &p3reloc);
+                return -EINVAL;
+        }
+        /* FIXME: we assume reloc size is 4 dwords */
+        *cs_reloc = p->relocs_ptr[(idx / 4)];
+        return 0;
+}
+
+static int r100_packet0_check(struct radeon_cs_parser *p,
+                              struct radeon_cs_packet *pkt)
+{
+        struct radeon_cs_chunk *ib_chunk;
+        struct radeon_cs_reloc *reloc;
+        volatile uint32_t *ib;
+        uint32_t tmp;
+        unsigned reg;
+        unsigned i;
+        unsigned idx;
+        bool onereg;
+        int r;
+
+        ib = p->ib->ptr;
+        ib_chunk = &p->chunks[p->chunk_ib_idx];
+        idx = pkt->idx + 1;
+        reg = pkt->reg;
+        onereg = false;
+        if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) {
+                onereg = true;
+        }
+        for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
+                switch (reg) {
+                /* FIXME: only allow PACKET3 blit? easier to check for out of
+                 * range access */
+                case RADEON_DST_PITCH_OFFSET:
+                case RADEON_SRC_PITCH_OFFSET:
+                        r = r100_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+                                          idx, reg);
+                                r100_cs_dump_packet(p, pkt);
+                                return r;
+                        }
+                        tmp = ib_chunk->kdata[idx] & 0x003fffff;
+                        tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
+                        ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) | tmp;
+                        break;
+                case RADEON_RB3D_DEPTHOFFSET:
+                case RADEON_RB3D_COLOROFFSET:
+                case R300_RB3D_COLOROFFSET0:
+                case R300_ZB_DEPTHOFFSET:
+                case R200_PP_TXOFFSET_0:
+                case R200_PP_TXOFFSET_1:
+                case R200_PP_TXOFFSET_2:
+                case R200_PP_TXOFFSET_3:
+                case R200_PP_TXOFFSET_4:
+                case R200_PP_TXOFFSET_5:
+                case RADEON_PP_TXOFFSET_0:
+                case RADEON_PP_TXOFFSET_1:
+                case RADEON_PP_TXOFFSET_2:
+                case R300_TX_OFFSET_0:
+                case R300_TX_OFFSET_0+4:
+                case R300_TX_OFFSET_0+8:
+                case R300_TX_OFFSET_0+12:
+                case R300_TX_OFFSET_0+16:
+                case R300_TX_OFFSET_0+20:
+                case R300_TX_OFFSET_0+24:
+                case R300_TX_OFFSET_0+28:
+                case R300_TX_OFFSET_0+32:
+                case R300_TX_OFFSET_0+36:
+                case R300_TX_OFFSET_0+40:
+                case R300_TX_OFFSET_0+44:
+                case R300_TX_OFFSET_0+48:
+                case R300_TX_OFFSET_0+52:
+                case R300_TX_OFFSET_0+56:
+                case R300_TX_OFFSET_0+60:
+                        r = r100_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+                                          idx, reg);
+                                r100_cs_dump_packet(p, pkt);
+                                return r;
+                        }
+                        ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+                        break;
+                default:
+                        /* FIXME: we don't want to allow anyothers packet */
+                        break;
+                }
+                if (onereg) {
+                        /* FIXME: forbid onereg write to register on relocate */
+                        break;
+                }
+        }
+        return 0;
+}
+
+static int r100_packet3_check(struct radeon_cs_parser *p,
+                              struct radeon_cs_packet *pkt)
+{
+        struct radeon_cs_chunk *ib_chunk;
+        struct radeon_cs_reloc *reloc;
+        unsigned idx;
+        unsigned i, c;
+        volatile uint32_t *ib;
+        int r;
+
+        ib = p->ib->ptr;
+        ib_chunk = &p->chunks[p->chunk_ib_idx];
+        idx = pkt->idx + 1;
+        switch (pkt->opcode) {
+        case PACKET3_3D_LOAD_VBPNTR:
+                c = ib_chunk->kdata[idx++];
+                for (i = 0; i < (c - 1); i += 2, idx += 3) {
+                        r = r100_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("No reloc for packet3 %d\n",
+                                          pkt->opcode);
+                                r100_cs_dump_packet(p, pkt);
+                                return r;
+                        }
+                        ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
+                        r = r100_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("No reloc for packet3 %d\n",
+                                          pkt->opcode);
+                                r100_cs_dump_packet(p, pkt);
+                                return r;
+                        }
+                        ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
+                }
+                if (c & 1) {
+                        r = r100_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("No reloc for packet3 %d\n",
+                                          pkt->opcode);
+                                r100_cs_dump_packet(p, pkt);
+                                return r;
+                        }
+                        ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
+                }
+                break;
+        case PACKET3_INDX_BUFFER:
+                r = r100_cs_packet_next_reloc(p, &reloc);
+                if (r) {
+                        DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
+                        r100_cs_dump_packet(p, pkt);
+                        return r;
+                }
+                ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
+                break;
+        case 0x23:
+                /* FIXME: cleanup */
+                /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
+                r = r100_cs_packet_next_reloc(p, &reloc);
+                if (r) {
+                        DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
+                        r100_cs_dump_packet(p, pkt);
+                        return r;
+                }
+                ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+                break;
+        case PACKET3_3D_DRAW_IMMD:
+                /* triggers drawing using in-packet vertex data */
+        case PACKET3_3D_DRAW_IMMD_2:
+                /* triggers drawing using in-packet vertex data */
+        case PACKET3_3D_DRAW_VBUF_2:
+                /* triggers drawing of vertex buffers setup elsewhere */
+        case PACKET3_3D_DRAW_INDX_2:
+                /* triggers drawing using indices to vertex buffer */
+        case PACKET3_3D_DRAW_VBUF:
+                /* triggers drawing of vertex buffers setup elsewhere */
+        case PACKET3_3D_DRAW_INDX:
+                /* triggers drawing using indices to vertex buffer */
+        case PACKET3_NOP:
+                break;
+        default:
+                DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
+                return -EINVAL;
+        }
+        return 0;
+}
+
+int r100_cs_parse(struct radeon_cs_parser *p)
+{
+        struct radeon_cs_packet pkt;
+        int r;
+
+        do {
+                r = r100_cs_packet_parse(p, &pkt, p->idx);
+                if (r) {
+                        return r;
+                }
+                p->idx += pkt.count + 2;
+                switch (pkt.type) {
+                case PACKET_TYPE0:
+                        r = r100_packet0_check(p, &pkt);
+                        break;
+                case PACKET_TYPE2:
+                        break;
+                case PACKET_TYPE3:
+                        r = r100_packet3_check(p, &pkt);
+                        break;
+                default:
+                        DRM_ERROR("Unknown packet type %d !\n",
+                                        pkt.type);
+                        return -EINVAL;
+                }
+                if (r) {
+                        return r;
+                }
+        } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
+        return 0;
+}
+
+
+/*
+ * Global GPU functions
+ */
+void r100_errata(struct radeon_device *rdev)
+{
+        rdev->pll_errata = 0;
+
+        if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
+                rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
+        }
+
+        if (rdev->family == CHIP_RV100 ||
+            rdev->family == CHIP_RS100 ||
+            rdev->family == CHIP_RS200) {
+                rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
+        }
+}
+
+/* Wait for vertical sync on primary CRTC */
+void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
+{
+        uint32_t crtc_gen_cntl, tmp;
+        int i;
+
+        crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
+        if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
+            !(crtc_gen_cntl & RADEON_CRTC_EN)) {
+                return;
+        }
+        /* Clear the CRTC_VBLANK_SAVE bit */
+        WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                tmp = RREG32(RADEON_CRTC_STATUS);
+                if (tmp & RADEON_CRTC_VBLANK_SAVE) {
+                        return;
+                }
+                DRM_UDELAY(1);
+        }
+}
+
+/* Wait for vertical sync on secondary CRTC */
+void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
+{
+        uint32_t crtc2_gen_cntl, tmp;
+        int i;
+
+        crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
+        if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
+            !(crtc2_gen_cntl & RADEON_CRTC2_EN))
+                return;
+
+        /* Clear the CRTC_VBLANK_SAVE bit */
+        WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                tmp = RREG32(RADEON_CRTC2_STATUS);
+                if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
+                        return;
+                }
+                DRM_UDELAY(1);
+        }
+}
+
+int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
+{
+        unsigned i;
+        uint32_t tmp;
+
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
+                if (tmp >= n) {
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        return -1;
+}
+
+int r100_gui_wait_for_idle(struct radeon_device *rdev)
+{
+        unsigned i;
+        uint32_t tmp;
+
+        if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
+                printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
+                       " Bad things might happen.\n");
+        }
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                tmp = RREG32(RADEON_RBBM_STATUS);
+                if (!(tmp & (1 << 31))) {
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        return -1;
+}
+
+int r100_mc_wait_for_idle(struct radeon_device *rdev)
+{
+        unsigned i;
+        uint32_t tmp;
+
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                /* read MC_STATUS */
+                tmp = RREG32(0x0150);
+                if (tmp & (1 << 2)) {
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        return -1;
+}
+
+void r100_gpu_init(struct radeon_device *rdev)
+{
+        /* TODO: anythings to do here ? pipes ? */
+        r100_hdp_reset(rdev);
+}
+
+void r100_hdp_reset(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
+        tmp |= (7 << 28);
+        WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
+        (void)RREG32(RADEON_HOST_PATH_CNTL);
+        udelay(200);
+        WREG32(RADEON_RBBM_SOFT_RESET, 0);
+        WREG32(RADEON_HOST_PATH_CNTL, tmp);
+        (void)RREG32(RADEON_HOST_PATH_CNTL);
+}
+
+int r100_rb2d_reset(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        int i;
+
+        WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
+        (void)RREG32(RADEON_RBBM_SOFT_RESET);
+        udelay(200);
+        WREG32(RADEON_RBBM_SOFT_RESET, 0);
+        /* Wait to prevent race in RBBM_STATUS */
+        mdelay(1);
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                tmp = RREG32(RADEON_RBBM_STATUS);
+                if (!(tmp & (1 << 26))) {
+                        DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
+                                 tmp);
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        tmp = RREG32(RADEON_RBBM_STATUS);
+        DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
+        return -1;
+}
+
+int r100_gpu_reset(struct radeon_device *rdev)
+{
+        uint32_t status;
+
+        /* reset order likely matter */
+        status = RREG32(RADEON_RBBM_STATUS);
+        /* reset HDP */
+        r100_hdp_reset(rdev);
+        /* reset rb2d */
+        if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
+                r100_rb2d_reset(rdev);
+        }
+        /* TODO: reset 3D engine */
+        /* reset CP */
+        status = RREG32(RADEON_RBBM_STATUS);
+        if (status & (1 << 16)) {
+                r100_cp_reset(rdev);
+        }
+        /* Check if GPU is idle */
+        status = RREG32(RADEON_RBBM_STATUS);
+        if (status & (1 << 31)) {
+                DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
+                return -1;
+        }
+        DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
+        return 0;
+}
+
+
+/*
+ * VRAM info
+ */
+static void r100_vram_get_type(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        rdev->mc.vram_is_ddr = false;
+        if (rdev->flags & RADEON_IS_IGP)
+                rdev->mc.vram_is_ddr = true;
+        else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
+                rdev->mc.vram_is_ddr = true;
+        if ((rdev->family == CHIP_RV100) ||
+            (rdev->family == CHIP_RS100) ||
+            (rdev->family == CHIP_RS200)) {
+                tmp = RREG32(RADEON_MEM_CNTL);
+                if (tmp & RV100_HALF_MODE) {
+                        rdev->mc.vram_width = 32;
+                } else {
+                        rdev->mc.vram_width = 64;
+                }
+                if (rdev->flags & RADEON_SINGLE_CRTC) {
+                        rdev->mc.vram_width /= 4;
+                        rdev->mc.vram_is_ddr = true;
+                }
+        } else if (rdev->family <= CHIP_RV280) {
+                tmp = RREG32(RADEON_MEM_CNTL);
+                if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
+                        rdev->mc.vram_width = 128;
+                } else {
+                        rdev->mc.vram_width = 64;
+                }
+        } else {
+                /* newer IGPs */
+                rdev->mc.vram_width = 128;
+        }
+}
+
+void r100_vram_info(struct radeon_device *rdev)
+{
+        r100_vram_get_type(rdev);
+
+        if (rdev->flags & RADEON_IS_IGP) {
+                uint32_t tom;
+                /* read NB_TOM to get the amount of ram stolen for the GPU */
+                tom = RREG32(RADEON_NB_TOM);
+                rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
+                WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+        } else {
+                rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
+                /* Some production boards of m6 will report 0
+                 * if it's 8 MB
+                 */
+                if (rdev->mc.vram_size == 0) {
+                        rdev->mc.vram_size = 8192 * 1024;
+                        WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+                }
+        }
+
+        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+        if (rdev->mc.aper_size > rdev->mc.vram_size) {
+                /* Why does some hw doesn't have CONFIG_MEMSIZE properly
+                 * setup ? */
+                rdev->mc.vram_size = rdev->mc.aper_size;
+                WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+        }
+}
+
+
+/*
+ * Indirect registers accessor
+ */
+void r100_pll_errata_after_index(struct radeon_device *rdev)
+{
+        if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
+                return;
+        }
+        (void)RREG32(RADEON_CLOCK_CNTL_DATA);
+        (void)RREG32(RADEON_CRTC_GEN_CNTL);
+}
+
+static void r100_pll_errata_after_data(struct radeon_device *rdev)
+{
+        /* This workarounds is necessary on RV100, RS100 and RS200 chips
+         * or the chip could hang on a subsequent access
+         */
+        if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
+                udelay(5000);
+        }
+
+        /* This function is required to workaround a hardware bug in some (all?)
+         * revisions of the R300.  This workaround should be called after every
+         * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
+         * may not be correct.
+         */
+        if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
+                uint32_t save, tmp;
+
+                save = RREG32(RADEON_CLOCK_CNTL_INDEX);
+                tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
+                WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
+                tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
+                WREG32(RADEON_CLOCK_CNTL_INDEX, save);
+        }
+}
+
+uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        uint32_t data;
+
+        WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
+        r100_pll_errata_after_index(rdev);
+        data = RREG32(RADEON_CLOCK_CNTL_DATA);
+        r100_pll_errata_after_data(rdev);
+        return data;
+}
+
+void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
+        r100_pll_errata_after_index(rdev);
+        WREG32(RADEON_CLOCK_CNTL_DATA, v);
+        r100_pll_errata_after_data(rdev);
+}
+
+uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        if (reg < 0x10000)
+                return readl(((void __iomem *)rdev->rmmio) + reg);
+        else {
+                writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
+                return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
+        }
+}
+
+void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        if (reg < 0x10000)
+                writel(v, ((void __iomem *)rdev->rmmio) + reg);
+        else {
+                writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
+                writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
+        }
+}
+
+/*
+ * Debugfs info
+ */
+#if defined(CONFIG_DEBUG_FS)
+static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t reg, value;
+        unsigned i;
+
+        seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
+        seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
+        seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
+        for (i = 0; i < 64; i++) {
+                WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
+                reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
+                WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
+                value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
+                seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
+        }
+        return 0;
+}
+
+static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t rdp, wdp;
+        unsigned count, i, j;
+
+        radeon_ring_free_size(rdev);
+        rdp = RREG32(RADEON_CP_RB_RPTR);
+        wdp = RREG32(RADEON_CP_RB_WPTR);
+        count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
+        seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
+        seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
+        seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
+        seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
+        seq_printf(m, "%u dwords in ring\n", count);
+        for (j = 0; j <= count; j++) {
+                i = (rdp + j) & rdev->cp.ptr_mask;
+                seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
+        }
+        return 0;
+}
+
+
+static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t csq_stat, csq2_stat, tmp;
+        unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
+        unsigned i;
+
+        seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
+        seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
+        csq_stat = RREG32(RADEON_CP_CSQ_STAT);
+        csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
+        r_rptr = (csq_stat >> 0) & 0x3ff;
+        r_wptr = (csq_stat >> 10) & 0x3ff;
+        ib1_rptr = (csq_stat >> 20) & 0x3ff;
+        ib1_wptr = (csq2_stat >> 0) & 0x3ff;
+        ib2_rptr = (csq2_stat >> 10) & 0x3ff;
+        ib2_wptr = (csq2_stat >> 20) & 0x3ff;
+        seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
+        seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
+        seq_printf(m, "Ring rptr %u\n", r_rptr);
+        seq_printf(m, "Ring wptr %u\n", r_wptr);
+        seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
+        seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
+        seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
+        seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
+        /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
+         * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
+        seq_printf(m, "Ring fifo:\n");
+        for (i = 0; i < 256; i++) {
+                WREG32(RADEON_CP_CSQ_ADDR, i << 2);
+                tmp = RREG32(RADEON_CP_CSQ_DATA);
+                seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
+        }
+        seq_printf(m, "Indirect1 fifo:\n");
+        for (i = 256; i <= 512; i++) {
+                WREG32(RADEON_CP_CSQ_ADDR, i << 2);
+                tmp = RREG32(RADEON_CP_CSQ_DATA);
+                seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
+        }
+        seq_printf(m, "Indirect2 fifo:\n");
+        for (i = 640; i < ib1_wptr; i++) {
+                WREG32(RADEON_CP_CSQ_ADDR, i << 2);
+                tmp = RREG32(RADEON_CP_CSQ_DATA);
+                seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
+        }
+        return 0;
+}
+
+static int r100_debugfs_mc_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t tmp;
+
+        tmp = RREG32(RADEON_CONFIG_MEMSIZE);
+        seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
+        tmp = RREG32(RADEON_MC_FB_LOCATION);
+        seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
+        tmp = RREG32(RADEON_BUS_CNTL);
+        seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
+        tmp = RREG32(RADEON_MC_AGP_LOCATION);
+        seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
+        tmp = RREG32(RADEON_AGP_BASE);
+        seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
+        tmp = RREG32(RADEON_HOST_PATH_CNTL);
+        seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
+        tmp = RREG32(0x01D0);
+        seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
+        tmp = RREG32(RADEON_AIC_LO_ADDR);
+        seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
+        tmp = RREG32(RADEON_AIC_HI_ADDR);
+        seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
+        tmp = RREG32(0x01E4);
+        seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
+        return 0;
+}
+
+static struct drm_info_list r100_debugfs_rbbm_list[] = {
+        {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
+};
+
+static struct drm_info_list r100_debugfs_cp_list[] = {
+        {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
+        {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
+};
+
+static struct drm_info_list r100_debugfs_mc_info_list[] = {
+        {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
+};
+#endif
+
+int r100_debugfs_rbbm_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
+#else
+        return 0;
+#endif
+}
+
+int r100_debugfs_cp_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
+#else
+        return 0;
+#endif
+}
+
+int r100_debugfs_mc_info_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
+#else
+        return 0;
+#endif
+}
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
new file mode 100644
index 000000000000..f5870a099d4f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -0,0 +1,1116 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include <linux/seq_file.h>
+#include "drmP.h"
+#include "drm.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+/* r300,r350,rv350,rv370,rv380 depends on : */
+void r100_hdp_reset(struct radeon_device *rdev);
+int r100_cp_reset(struct radeon_device *rdev);
+int r100_rb2d_reset(struct radeon_device *rdev);
+int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
+int r100_pci_gart_enable(struct radeon_device *rdev);
+void r100_pci_gart_disable(struct radeon_device *rdev);
+void r100_mc_setup(struct radeon_device *rdev);
+void r100_mc_disable_clients(struct radeon_device *rdev);
+int r100_gui_wait_for_idle(struct radeon_device *rdev);
+int r100_cs_packet_parse(struct radeon_cs_parser *p,
+                         struct radeon_cs_packet *pkt,
+                         unsigned idx);
+int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
+                              struct radeon_cs_reloc **cs_reloc);
+int r100_cs_parse_packet0(struct radeon_cs_parser *p,
+                          struct radeon_cs_packet *pkt,
+                          unsigned *auth, unsigned n,
+                          radeon_packet0_check_t check);
+int r100_cs_parse_packet3(struct radeon_cs_parser *p,
+                          struct radeon_cs_packet *pkt,
+                          unsigned *auth, unsigned n,
+                          radeon_packet3_check_t check);
+void r100_cs_dump_packet(struct radeon_cs_parser *p,
+                         struct radeon_cs_packet *pkt);
+
+/* This files gather functions specifics to:
+ * r300,r350,rv350,rv370,rv380
+ *
+ * Some of these functions might be used by newer ASICs.
+ */
+void r300_gpu_init(struct radeon_device *rdev);
+int r300_mc_wait_for_idle(struct radeon_device *rdev);
+int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
+
+
+/*
+ * rv370,rv380 PCIE GART
+ */
+void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        int i;
+
+        /* Workaround HW bug do flush 2 times */
+        for (i = 0; i < 2; i++) {
+                tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
+                WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
+                (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
+                WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
+                mb();
+        }
+}
+
+int rv370_pcie_gart_enable(struct radeon_device *rdev)
+{
+        uint32_t table_addr;
+        uint32_t tmp;
+        int r;
+
+        /* Initialize common gart structure */
+        r = radeon_gart_init(rdev);
+        if (r) {
+                return r;
+        }
+        r = rv370_debugfs_pcie_gart_info_init(rdev);
+        if (r) {
+                DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
+        }
+        rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
+        r = radeon_gart_table_vram_alloc(rdev);
+        if (r) {
+                return r;
+        }
+        /* discard memory request outside of configured range */
+        tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
+        WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
+        WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
+        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096;
+        WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
+        WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
+        WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
+        table_addr = rdev->gart.table_addr;
+        WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
+        /* FIXME: setup default page */
+        WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
+        WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
+        /* Clear error */
+        WREG32_PCIE(0x18, 0);
+        tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
+        tmp |= RADEON_PCIE_TX_GART_EN;
+        tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
+        WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
+        rv370_pcie_gart_tlb_flush(rdev);
+        DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
+                 rdev->mc.gtt_size >> 20, table_addr);
+        rdev->gart.ready = true;
+        return 0;
+}
+
+void rv370_pcie_gart_disable(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
+        tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
+        WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
+        if (rdev->gart.table.vram.robj) {
+                radeon_object_kunmap(rdev->gart.table.vram.robj);
+                radeon_object_unpin(rdev->gart.table.vram.robj);
+        }
+}
+
+int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
+{
+        void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+
+        if (i < 0 || i > rdev->gart.num_gpu_pages) {
+                return -EINVAL;
+        }
+        addr = (((u32)addr) >> 8) | ((upper_32_bits(addr) & 0xff) << 4) | 0xC;
+        writel(cpu_to_le32(addr), ((void __iomem *)ptr) + (i * 4));
+        return 0;
+}
+
+int r300_gart_enable(struct radeon_device *rdev)
+{
+#if __OS_HAS_AGP
+        if (rdev->flags & RADEON_IS_AGP) {
+                if (rdev->family > CHIP_RV350) {
+                        rv370_pcie_gart_disable(rdev);
+                } else {
+                        r100_pci_gart_disable(rdev);
+                }
+                return 0;
+        }
+#endif
+        if (rdev->flags & RADEON_IS_PCIE) {
+                rdev->asic->gart_disable = &rv370_pcie_gart_disable;
+                rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
+                rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
+                return rv370_pcie_gart_enable(rdev);
+        }
+        return r100_pci_gart_enable(rdev);
+}
+
+
+/*
+ * MC
+ */
+int r300_mc_init(struct radeon_device *rdev)
+{
+        int r;
+
+        if (r100_debugfs_rbbm_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
+        }
+
+        r300_gpu_init(rdev);
+        r100_pci_gart_disable(rdev);
+        if (rdev->flags & RADEON_IS_PCIE) {
+                rv370_pcie_gart_disable(rdev);
+        }
+
+        /* Setup GPU memory space */
+        rdev->mc.vram_location = 0xFFFFFFFFUL;
+        rdev->mc.gtt_location = 0xFFFFFFFFUL;
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r) {
+                        printk(KERN_WARNING "[drm] Disabling AGP\n");
+                        rdev->flags &= ~RADEON_IS_AGP;
+                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+                } else {
+                        rdev->mc.gtt_location = rdev->mc.agp_base;
+                }
+        }
+        r = radeon_mc_setup(rdev);
+        if (r) {
+                return r;
+        }
+
+        /* Program GPU memory space */
+        r100_mc_disable_clients(rdev);
+        if (r300_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+        r100_mc_setup(rdev);
+        return 0;
+}
+
+void r300_mc_fini(struct radeon_device *rdev)
+{
+        if (rdev->flags & RADEON_IS_PCIE) {
+                rv370_pcie_gart_disable(rdev);
+                radeon_gart_table_vram_free(rdev);
+        } else {
+                r100_pci_gart_disable(rdev);
+                radeon_gart_table_ram_free(rdev);
+        }
+        radeon_gart_fini(rdev);
+}
+
+
+/*
+ * Fence emission
+ */
+void r300_fence_ring_emit(struct radeon_device *rdev,
+                          struct radeon_fence *fence)
+{
+        /* Who ever call radeon_fence_emit should call ring_lock and ask
+         * for enough space (today caller are ib schedule and buffer move) */
+        /* Write SC register so SC & US assert idle */
+        radeon_ring_write(rdev, PACKET0(0x43E0, 0));
+        radeon_ring_write(rdev, 0);
+        radeon_ring_write(rdev, PACKET0(0x43E4, 0));
+        radeon_ring_write(rdev, 0);
+        /* Flush 3D cache */
+        radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
+        radeon_ring_write(rdev, (2 << 0));
+        radeon_ring_write(rdev, PACKET0(0x4F18, 0));
+        radeon_ring_write(rdev, (1 << 0));
+        /* Wait until IDLE & CLEAN */
+        radeon_ring_write(rdev, PACKET0(0x1720, 0));
+        radeon_ring_write(rdev, (1 << 17) | (1 << 16)  | (1 << 9));
+        /* Emit fence sequence & fire IRQ */
+        radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
+        radeon_ring_write(rdev, fence->seq);
+        radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
+        radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
+}
+
+
+/*
+ * Global GPU functions
+ */
+int r300_copy_dma(struct radeon_device *rdev,
+                  uint64_t src_offset,
+                  uint64_t dst_offset,
+                  unsigned num_pages,
+                  struct radeon_fence *fence)
+{
+        uint32_t size;
+        uint32_t cur_size;
+        int i, num_loops;
+        int r = 0;
+
+        /* radeon pitch is /64 */
+        size = num_pages << PAGE_SHIFT;
+        num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
+        r = radeon_ring_lock(rdev, num_loops * 4 + 64);
+        if (r) {
+                DRM_ERROR("radeon: moving bo (%d).\n", r);
+                return r;
+        }
+        /* Must wait for 2D idle & clean before DMA or hangs might happen */
+        radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
+        radeon_ring_write(rdev, (1 << 16));
+        for (i = 0; i < num_loops; i++) {
+                cur_size = size;
+                if (cur_size > 0x1FFFFF) {
+                        cur_size = 0x1FFFFF;
+                }
+                size -= cur_size;
+                radeon_ring_write(rdev, PACKET0(0x720, 2));
+                radeon_ring_write(rdev, src_offset);
+                radeon_ring_write(rdev, dst_offset);
+                radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
+                src_offset += cur_size;
+                dst_offset += cur_size;
+        }
+        radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
+        radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
+        if (fence) {
+                r = radeon_fence_emit(rdev, fence);
+        }
+        radeon_ring_unlock_commit(rdev);
+        return r;
+}
+
+void r300_ring_start(struct radeon_device *rdev)
+{
+        unsigned gb_tile_config;
+        int r;
+
+        /* Sub pixel 1/12 so we can have 4K rendering according to doc */
+        gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
+        switch (rdev->num_gb_pipes) {
+        case 2:
+                gb_tile_config |= R300_PIPE_COUNT_R300;
+                break;
+        case 3:
+                gb_tile_config |= R300_PIPE_COUNT_R420_3P;
+                break;
+        case 4:
+                gb_tile_config |= R300_PIPE_COUNT_R420;
+                break;
+        case 1:
+        default:
+                gb_tile_config |= R300_PIPE_COUNT_RV350;
+                break;
+        }
+
+        r = radeon_ring_lock(rdev, 64);
+        if (r) {
+                return;
+        }
+        radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
+        radeon_ring_write(rdev,
+                          RADEON_ISYNC_ANY2D_IDLE3D |
+                          RADEON_ISYNC_ANY3D_IDLE2D |
+                          RADEON_ISYNC_WAIT_IDLEGUI |
+                          RADEON_ISYNC_CPSCRATCH_IDLEGUI);
+        radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
+        radeon_ring_write(rdev, gb_tile_config);
+        radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
+        radeon_ring_write(rdev,
+                          RADEON_WAIT_2D_IDLECLEAN |
+                          RADEON_WAIT_3D_IDLECLEAN);
+        radeon_ring_write(rdev, PACKET0(0x170C, 0));
+        radeon_ring_write(rdev, 1 << 31);
+        radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
+        radeon_ring_write(rdev, 0);
+        radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
+        radeon_ring_write(rdev, 0);
+        radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
+        radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
+        radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
+        radeon_ring_write(rdev,
+                          RADEON_WAIT_2D_IDLECLEAN |
+                          RADEON_WAIT_3D_IDLECLEAN);
+        radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
+        radeon_ring_write(rdev, 0);
+        radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
+        radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
+        radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
+        radeon_ring_write(rdev,
+                          ((6 << R300_MS_X0_SHIFT) |
+                           (6 << R300_MS_Y0_SHIFT) |
+                           (6 << R300_MS_X1_SHIFT) |
+                           (6 << R300_MS_Y1_SHIFT) |
+                           (6 << R300_MS_X2_SHIFT) |
+                           (6 << R300_MS_Y2_SHIFT) |
+                           (6 << R300_MSBD0_Y_SHIFT) |
+                           (6 << R300_MSBD0_X_SHIFT)));
+        radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
+        radeon_ring_write(rdev,
+                          ((6 << R300_MS_X3_SHIFT) |
+                           (6 << R300_MS_Y3_SHIFT) |
+                           (6 << R300_MS_X4_SHIFT) |
+                           (6 << R300_MS_Y4_SHIFT) |
+                           (6 << R300_MS_X5_SHIFT) |
+                           (6 << R300_MS_Y5_SHIFT) |
+                           (6 << R300_MSBD1_SHIFT)));
+        radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
+        radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
+        radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
+        radeon_ring_write(rdev,
+                          R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
+        radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
+        radeon_ring_write(rdev,
+                          R300_GEOMETRY_ROUND_NEAREST |
+                          R300_COLOR_ROUND_NEAREST);
+        radeon_ring_unlock_commit(rdev);
+}
+
+void r300_errata(struct radeon_device *rdev)
+{
+        rdev->pll_errata = 0;
+
+        if (rdev->family == CHIP_R300 &&
+            (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
+                rdev->pll_errata |= CHIP_ERRATA_R300_CG;
+        }
+}
+
+int r300_mc_wait_for_idle(struct radeon_device *rdev)
+{
+        unsigned i;
+        uint32_t tmp;
+
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                /* read MC_STATUS */
+                tmp = RREG32(0x0150);
+                if (tmp & (1 << 4)) {
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        return -1;
+}
+
+void r300_gpu_init(struct radeon_device *rdev)
+{
+        uint32_t gb_tile_config, tmp;
+
+        r100_hdp_reset(rdev);
+        /* FIXME: rv380 one pipes ? */
+        if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
+                /* r300,r350 */
+                rdev->num_gb_pipes = 2;
+        } else {
+                /* rv350,rv370,rv380 */
+                rdev->num_gb_pipes = 1;
+        }
+        gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
+        switch (rdev->num_gb_pipes) {
+        case 2:
+                gb_tile_config |= R300_PIPE_COUNT_R300;
+                break;
+        case 3:
+                gb_tile_config |= R300_PIPE_COUNT_R420_3P;
+                break;
+        case 4:
+                gb_tile_config |= R300_PIPE_COUNT_R420;
+                break;
+        case 1:
+        default:
+                gb_tile_config |= R300_PIPE_COUNT_RV350;
+                break;
+        }
+        WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
+
+        if (r100_gui_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait GUI idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+
+        tmp = RREG32(0x170C);
+        WREG32(0x170C, tmp | (1 << 31));
+
+        WREG32(R300_RB2D_DSTCACHE_MODE,
+               R300_DC_AUTOFLUSH_ENABLE |
+               R300_DC_DC_DISABLE_IGNORE_PE);
+
+        if (r100_gui_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait GUI idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+        if (r300_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+        DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);
+}
+
+int r300_ga_reset(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        bool reinit_cp;
+        int i;
+
+        reinit_cp = rdev->cp.ready;
+        rdev->cp.ready = false;
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                WREG32(RADEON_CP_CSQ_MODE, 0);
+                WREG32(RADEON_CP_CSQ_CNTL, 0);
+                WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
+                (void)RREG32(RADEON_RBBM_SOFT_RESET);
+                udelay(200);
+                WREG32(RADEON_RBBM_SOFT_RESET, 0);
+                /* Wait to prevent race in RBBM_STATUS */
+                mdelay(1);
+                tmp = RREG32(RADEON_RBBM_STATUS);
+                if (tmp & ((1 << 20) | (1 << 26))) {
+                        DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
+                        /* GA still busy soft reset it */
+                        WREG32(0x429C, 0x200);
+                        WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+                        WREG32(0x43E0, 0);
+                        WREG32(0x43E4, 0);
+                        WREG32(0x24AC, 0);
+                }
+                /* Wait to prevent race in RBBM_STATUS */
+                mdelay(1);
+                tmp = RREG32(RADEON_RBBM_STATUS);
+                if (!(tmp & ((1 << 20) | (1 << 26)))) {
+                        break;
+                }
+        }
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                tmp = RREG32(RADEON_RBBM_STATUS);
+                if (!(tmp & ((1 << 20) | (1 << 26)))) {
+                        DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
+                                 tmp);
+                        if (reinit_cp) {
+                                return r100_cp_init(rdev, rdev->cp.ring_size);
+                        }
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        tmp = RREG32(RADEON_RBBM_STATUS);
+        DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
+        return -1;
+}
+
+int r300_gpu_reset(struct radeon_device *rdev)
+{
+        uint32_t status;
+
+        /* reset order likely matter */
+        status = RREG32(RADEON_RBBM_STATUS);
+        /* reset HDP */
+        r100_hdp_reset(rdev);
+        /* reset rb2d */
+        if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
+                r100_rb2d_reset(rdev);
+        }
+        /* reset GA */
+        if (status & ((1 << 20) | (1 << 26))) {
+                r300_ga_reset(rdev);
+        }
+        /* reset CP */
+        status = RREG32(RADEON_RBBM_STATUS);
+        if (status & (1 << 16)) {
+                r100_cp_reset(rdev);
+        }
+        /* Check if GPU is idle */
+        status = RREG32(RADEON_RBBM_STATUS);
+        if (status & (1 << 31)) {
+                DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
+                return -1;
+        }
+        DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
+        return 0;
+}
+
+
+/*
+ * r300,r350,rv350,rv380 VRAM info
+ */
+void r300_vram_info(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        /* DDR for all card after R300 & IGP */
+        rdev->mc.vram_is_ddr = true;
+        tmp = RREG32(RADEON_MEM_CNTL);
+        if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
+                rdev->mc.vram_width = 128;
+        } else {
+                rdev->mc.vram_width = 64;
+        }
+        rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
+
+        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+}
+
+
+/*
+ * Indirect registers accessor
+ */
+uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        uint32_t r;
+
+        WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff));
+        (void)RREG32(RADEON_PCIE_INDEX);
+        r = RREG32(RADEON_PCIE_DATA);
+        return r;
+}
+
+void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff));
+        (void)RREG32(RADEON_PCIE_INDEX);
+        WREG32(RADEON_PCIE_DATA, (v));
+        (void)RREG32(RADEON_PCIE_DATA);
+}
+
+/*
+ * PCIE Lanes
+ */
+
+void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
+{
+        uint32_t link_width_cntl, mask;
+
+        if (rdev->flags & RADEON_IS_IGP)
+                return;
+
+        if (!(rdev->flags & RADEON_IS_PCIE))
+                return;
+
+        /* FIXME wait for idle */
+
+        switch (lanes) {
+        case 0:
+                mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
+                break;
+        case 1:
+                mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
+                break;
+        case 2:
+                mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
+                break;
+        case 4:
+                mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
+                break;
+        case 8:
+                mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
+                break;
+        case 12:
+                mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
+                break;
+        case 16:
+        default:
+                mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
+                break;
+        }
+
+        link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
+
+        if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
+            (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
+                return;
+
+        link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
+                             RADEON_PCIE_LC_RECONFIG_NOW |
+                             RADEON_PCIE_LC_RECONFIG_LATER |
+                             RADEON_PCIE_LC_SHORT_RECONFIG_EN);
+        link_width_cntl |= mask;
+        WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+        WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
+                                                     RADEON_PCIE_LC_RECONFIG_NOW));
+
+        /* wait for lane set to complete */
+        link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
+        while (link_width_cntl == 0xffffffff)
+                link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
+
+}
+
+
+/*
+ * Debugfs info
+ */
+#if defined(CONFIG_DEBUG_FS)
+static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t tmp;
+
+        tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
+        seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
+        tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
+        seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
+        tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
+        seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
+        tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
+        seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
+        tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
+        seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
+        tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
+        seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
+        tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
+        seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
+        return 0;
+}
+
+static struct drm_info_list rv370_pcie_gart_info_list[] = {
+        {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
+};
+#endif
+
+int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
+#else
+        return 0;
+#endif
+}
+
+
+/*
+ * CS functions
+ */
+struct r300_cs_track_cb {
+        struct radeon_object    *robj;
+        unsigned                pitch;
+        unsigned                cpp;
+        unsigned                offset;
+};
+
+struct r300_cs_track {
+        unsigned                num_cb;
+        unsigned                maxy;
+        struct r300_cs_track_cb cb[4];
+        struct r300_cs_track_cb zb;
+        bool                    z_enabled;
+};
+
+int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track)
+{
+        unsigned i;
+        unsigned long size;
+
+        for (i = 0; i < track->num_cb; i++) {
+                if (track->cb[i].robj == NULL) {
+                        DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
+                        return -EINVAL;
+                }
+                size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
+                size += track->cb[i].offset;
+                if (size > radeon_object_size(track->cb[i].robj)) {
+                        DRM_ERROR("[drm] Buffer too small for color buffer %d "
+                                  "(need %lu have %lu) !\n", i, size,
+                                  radeon_object_size(track->cb[i].robj));
+                        DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
+                                  i, track->cb[i].pitch, track->cb[i].cpp,
+                                  track->cb[i].offset, track->maxy);
+                        return -EINVAL;
+                }
+        }
+        if (track->z_enabled) {
+                if (track->zb.robj == NULL) {
+                        DRM_ERROR("[drm] No buffer for z buffer !\n");
+                        return -EINVAL;
+                }
+                size = track->zb.pitch * track->zb.cpp * track->maxy;
+                size += track->zb.offset;
+                if (size > radeon_object_size(track->zb.robj)) {
+                        DRM_ERROR("[drm] Buffer too small for z buffer "
+                                  "(need %lu have %lu) !\n", size,
+                                  radeon_object_size(track->zb.robj));
+                        return -EINVAL;
+                }
+        }
+        return 0;
+}
+
+static inline void r300_cs_track_clear(struct r300_cs_track *track)
+{
+        unsigned i;
+
+        track->num_cb = 4;
+        track->maxy = 4096;
+        for (i = 0; i < track->num_cb; i++) {
+                track->cb[i].robj = NULL;
+                track->cb[i].pitch = 8192;
+                track->cb[i].cpp = 16;
+                track->cb[i].offset = 0;
+        }
+        track->z_enabled = true;
+        track->zb.robj = NULL;
+        track->zb.pitch = 8192;
+        track->zb.cpp = 4;
+        track->zb.offset = 0;
+}
+
+static unsigned r300_auth_reg[] = {
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
+        0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFCFCC, 0xF00E9FFF, 0x007C0000,
+        0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
+        0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFC, 0xFFFFFFFF,
+        0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF,
+        0x00000000, 0x00000000, 0xFFFF0000, 0x00000000,
+        0x00000000, 0x0000C100, 0x00000000, 0x00000000,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
+        0x00000000, 0x00000000, 0x00000000, 0x00000000,
+        0x0003FC01, 0xFFFFFFF8, 0xFE800B19,
+};
+
+static int r300_packet0_check(struct radeon_cs_parser *p,
+                struct radeon_cs_packet *pkt,
+                unsigned idx, unsigned reg)
+{
+        struct radeon_cs_chunk *ib_chunk;
+        struct radeon_cs_reloc *reloc;
+        struct r300_cs_track *track;
+        volatile uint32_t *ib;
+        uint32_t tmp;
+        unsigned i;
+        int r;
+
+        ib = p->ib->ptr;
+        ib_chunk = &p->chunks[p->chunk_ib_idx];
+        track = (struct r300_cs_track *)p->track;
+        switch (reg) {
+        case RADEON_DST_PITCH_OFFSET:
+        case RADEON_SRC_PITCH_OFFSET:
+                r = r100_cs_packet_next_reloc(p, &reloc);
+                if (r) {
+                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+                                        idx, reg);
+                        r100_cs_dump_packet(p, pkt);
+                        return r;
+                }
+                tmp = ib_chunk->kdata[idx] & 0x003fffff;
+                tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
+                ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) | tmp;
+                break;
+        case R300_RB3D_COLOROFFSET0:
+        case R300_RB3D_COLOROFFSET1:
+        case R300_RB3D_COLOROFFSET2:
+        case R300_RB3D_COLOROFFSET3:
+                i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
+                r = r100_cs_packet_next_reloc(p, &reloc);
+                if (r) {
+                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+                                        idx, reg);
+                        r100_cs_dump_packet(p, pkt);
+                        return r;
+                }
+                track->cb[i].robj = reloc->robj;
+                track->cb[i].offset = ib_chunk->kdata[idx];
+                ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+                break;
+        case R300_ZB_DEPTHOFFSET:
+                r = r100_cs_packet_next_reloc(p, &reloc);
+                if (r) {
+                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+                                        idx, reg);
+                        r100_cs_dump_packet(p, pkt);
+                        return r;
+                }
+                track->zb.robj = reloc->robj;
+                track->zb.offset = ib_chunk->kdata[idx];
+                ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+                break;
+        case R300_TX_OFFSET_0:
+        case R300_TX_OFFSET_0+4:
+        case R300_TX_OFFSET_0+8:
+        case R300_TX_OFFSET_0+12:
+        case R300_TX_OFFSET_0+16:
+        case R300_TX_OFFSET_0+20:
+        case R300_TX_OFFSET_0+24:
+        case R300_TX_OFFSET_0+28:
+        case R300_TX_OFFSET_0+32:
+        case R300_TX_OFFSET_0+36:
+        case R300_TX_OFFSET_0+40:
+        case R300_TX_OFFSET_0+44:
+        case R300_TX_OFFSET_0+48:
+        case R300_TX_OFFSET_0+52:
+        case R300_TX_OFFSET_0+56:
+        case R300_TX_OFFSET_0+60:
+                r = r100_cs_packet_next_reloc(p, &reloc);
+                if (r) {
+                        DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
+                                        idx, reg);
+                        r100_cs_dump_packet(p, pkt);
+                        return r;
+                }
+                ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
+                break;
+        /* Tracked registers */
+        case 0x43E4:
+                /* SC_SCISSOR1 */
+
+                track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1;
+                if (p->rdev->family < CHIP_RV515) {
+                        track->maxy -= 1440;
+                }
+                break;
+        case 0x4E00:
+                /* RB3D_CCTL */
+                track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1;
+                break;
+        case 0x4E38:
+        case 0x4E3C:
+        case 0x4E40:
+        case 0x4E44:
+                /* RB3D_COLORPITCH0 */
+                /* RB3D_COLORPITCH1 */
+                /* RB3D_COLORPITCH2 */
+                /* RB3D_COLORPITCH3 */
+                i = (reg - 0x4E38) >> 2;
+                track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE;
+                switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) {
+                case 9:
+                case 11:
+                case 12:
+                        track->cb[i].cpp = 1;
+                        break;
+                case 3:
+                case 4:
+                case 13:
+                case 15:
+                        track->cb[i].cpp = 2;
+                        break;
+                case 6:
+                        track->cb[i].cpp = 4;
+                        break;
+                case 10:
+                        track->cb[i].cpp = 8;
+                        break;
+                case 7:
+                        track->cb[i].cpp = 16;
+                        break;
+                default:
+                        DRM_ERROR("Invalid color buffer format (%d) !\n",
+                                  ((ib_chunk->kdata[idx] >> 21) & 0xF));
+                        return -EINVAL;
+                }
+                break;
+        case 0x4F00:
+                /* ZB_CNTL */
+                if (ib_chunk->kdata[idx] & 2) {
+                        track->z_enabled = true;
+                } else {
+                        track->z_enabled = false;
+                }
+                break;
+        case 0x4F10:
+                /* ZB_FORMAT */
+                switch ((ib_chunk->kdata[idx] & 0xF)) {
+                case 0:
+                case 1:
+                        track->zb.cpp = 2;
+                        break;
+                case 2:
+                        track->zb.cpp = 4;
+                        break;
+                default:
+                        DRM_ERROR("Invalid z buffer format (%d) !\n",
+                                  (ib_chunk->kdata[idx] & 0xF));
+                        return -EINVAL;
+                }
+                break;
+        case 0x4F24:
+                /* ZB_DEPTHPITCH */
+                track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC;
+                break;
+        default:
+                printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", reg, idx);
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static int r300_packet3_check(struct radeon_cs_parser *p,
+                              struct radeon_cs_packet *pkt)
+{
+        struct radeon_cs_chunk *ib_chunk;
+        struct radeon_cs_reloc *reloc;
+        struct r300_cs_track *track;
+        volatile uint32_t *ib;
+        unsigned idx;
+        unsigned i, c;
+        int r;
+
+        ib = p->ib->ptr;
+        ib_chunk = &p->chunks[p->chunk_ib_idx];
+        idx = pkt->idx + 1;
+        track = (struct r300_cs_track *)p->track;
+        switch (pkt->opcode) {
+        case PACKET3_3D_LOAD_VBPNTR:
+                c = ib_chunk->kdata[idx++];
+                for (i = 0; i < (c - 1); i += 2, idx += 3) {
+                        r = r100_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("No reloc for packet3 %d\n",
+                                          pkt->opcode);
+                                r100_cs_dump_packet(p, pkt);
+                                return r;
+                        }
+                        ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
+                        r = r100_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("No reloc for packet3 %d\n",
+                                          pkt->opcode);
+                                r100_cs_dump_packet(p, pkt);
+                                return r;
+                        }
+                        ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
+                }
+                if (c & 1) {
+                        r = r100_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("No reloc for packet3 %d\n",
+                                          pkt->opcode);
+                                r100_cs_dump_packet(p, pkt);
+                                return r;
+                        }
+                        ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
+                }
+                break;
+        case PACKET3_INDX_BUFFER:
+                r = r100_cs_packet_next_reloc(p, &reloc);
+                if (r) {
+                        DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
+                        r100_cs_dump_packet(p, pkt);
+                        return r;
+                }
+                ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
+                break;
+        /* Draw packet */
+        case PACKET3_3D_DRAW_VBUF:
+        case PACKET3_3D_DRAW_IMMD:
+        case PACKET3_3D_DRAW_INDX:
+        case PACKET3_3D_DRAW_VBUF_2:
+        case PACKET3_3D_DRAW_IMMD_2:
+        case PACKET3_3D_DRAW_INDX_2:
+                r = r300_cs_track_check(p->rdev, track);
+                if (r) {
+                        return r;
+                }
+                break;
+        case PACKET3_NOP:
+                break;
+        default:
+                DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
+                return -EINVAL;
+        }
+        return 0;
+}
+
+int r300_cs_parse(struct radeon_cs_parser *p)
+{
+        struct radeon_cs_packet pkt;
+        struct r300_cs_track track;
+        int r;
+
+        r300_cs_track_clear(&track);
+        p->track = &track;
+        do {
+                r = r100_cs_packet_parse(p, &pkt, p->idx);
+                if (r) {
+                        return r;
+                }
+                p->idx += pkt.count + 2;
+                switch (pkt.type) {
+                case PACKET_TYPE0:
+                        r = r100_cs_parse_packet0(p, &pkt,
+                                                  r300_auth_reg,
+                                                  ARRAY_SIZE(r300_auth_reg),
+                                                  &r300_packet0_check);
+                        break;
+                case PACKET_TYPE2:
+                        break;
+                case PACKET_TYPE3:
+                        r = r300_packet3_check(p, &pkt);
+                        break;
+                default:
+                        DRM_ERROR("Unknown packet type %d !\n", pkt.type);
+                        return -EINVAL;
+                }
+                if (r) {
+                        return r;
+                }
+        } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
+        return 0;
+}
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
index bdbc95fa6721..70f48609515e 100644
--- a/drivers/gpu/drm/radeon/r300_reg.h
+++ b/drivers/gpu/drm/radeon/r300_reg.h
@@ -1,30 +1,34 @@
-/**************************************************************************
-
-Copyright (C) 2004-2005 Nicolai Haehnle et al.
-
-Permission is hereby granted, free of charge, to any person obtaining a
-copy of this software and associated documentation files (the "Software"),
-to deal in the Software without restriction, including without limitation
-on the rights to use, copy, modify, merge, publish, distribute, sub
-license, and/or sell copies of the Software, and to permit persons to whom
-the Software is furnished to do so, subject to the following conditions:
-
-The above copyright notice and this permission notice (including the next
-paragraph) shall be included in all copies or substantial portions of the
-Software.
+/*
+ * Copyright 2005 Nicolai Haehnle et al.
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Nicolai Haehnle
+ *          Jerome Glisse
+ */
+#ifndef _R300_REG_H_
+#define _R300_REG_H_
 
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
-THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
-DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
-USE OR OTHER DEALINGS IN THE SOFTWARE.
 
-**************************************************************************/
 
-#ifndef _R300_REG_H
-#define _R300_REG_H
 
 #define R300_MC_INIT_MISC_LAT_TIMER     0x180
 #       define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT      0
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
new file mode 100644
index 000000000000..dea497a979f2
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include <linux/seq_file.h>
+#include "drmP.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+/* r420,r423,rv410 depends on : */
+void r100_pci_gart_disable(struct radeon_device *rdev);
+void r100_hdp_reset(struct radeon_device *rdev);
+void r100_mc_setup(struct radeon_device *rdev);
+int r100_gui_wait_for_idle(struct radeon_device *rdev);
+void r100_mc_disable_clients(struct radeon_device *rdev);
+void r300_vram_info(struct radeon_device *rdev);
+int r300_mc_wait_for_idle(struct radeon_device *rdev);
+int rv370_pcie_gart_enable(struct radeon_device *rdev);
+void rv370_pcie_gart_disable(struct radeon_device *rdev);
+
+/* This files gather functions specifics to :
+ * r420,r423,rv410
+ *
+ * Some of these functions might be used by newer ASICs.
+ */
+void r420_gpu_init(struct radeon_device *rdev);
+int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
+
+
+/*
+ * MC
+ */
+int r420_mc_init(struct radeon_device *rdev)
+{
+        int r;
+
+        if (r100_debugfs_rbbm_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
+        }
+        if (r420_debugfs_pipes_info_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for pipes !\n");
+        }
+
+        r420_gpu_init(rdev);
+        r100_pci_gart_disable(rdev);
+        if (rdev->flags & RADEON_IS_PCIE) {
+                rv370_pcie_gart_disable(rdev);
+        }
+
+        /* Setup GPU memory space */
+        rdev->mc.vram_location = 0xFFFFFFFFUL;
+        rdev->mc.gtt_location = 0xFFFFFFFFUL;
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r) {
+                        printk(KERN_WARNING "[drm] Disabling AGP\n");
+                        rdev->flags &= ~RADEON_IS_AGP;
+                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+                } else {
+                        rdev->mc.gtt_location = rdev->mc.agp_base;
+                }
+        }
+        r = radeon_mc_setup(rdev);
+        if (r) {
+                return r;
+        }
+
+        /* Program GPU memory space */
+        r100_mc_disable_clients(rdev);
+        if (r300_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+        r100_mc_setup(rdev);
+        return 0;
+}
+
+void r420_mc_fini(struct radeon_device *rdev)
+{
+        rv370_pcie_gart_disable(rdev);
+        radeon_gart_table_vram_free(rdev);
+        radeon_gart_fini(rdev);
+}
+
+
+/*
+ * Global GPU functions
+ */
+void r420_errata(struct radeon_device *rdev)
+{
+        rdev->pll_errata = 0;
+}
+
+void r420_pipes_init(struct radeon_device *rdev)
+{
+        unsigned tmp;
+        unsigned gb_pipe_select;
+        unsigned num_pipes;
+
+        /* GA_ENHANCE workaround TCL deadlock issue */
+        WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
+        /* get max number of pipes */
+        gb_pipe_select = RREG32(0x402C);
+        num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
+        rdev->num_gb_pipes = num_pipes;
+        tmp = 0;
+        switch (num_pipes) {
+        default:
+                /* force to 1 pipe */
+                num_pipes = 1;
+        case 1:
+                tmp = (0 << 1);
+                break;
+        case 2:
+                tmp = (3 << 1);
+                break;
+        case 3:
+                tmp = (6 << 1);
+                break;
+        case 4:
+                tmp = (7 << 1);
+                break;
+        }
+        WREG32(0x42C8, (1 << num_pipes) - 1);
+        /* Sub pixel 1/12 so we can have 4K rendering according to doc */
+        tmp |= (1 << 4) | (1 << 0);
+        WREG32(0x4018, tmp);
+        if (r100_gui_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait GUI idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+
+        tmp = RREG32(0x170C);
+        WREG32(0x170C, tmp | (1 << 31));
+
+        WREG32(R300_RB2D_DSTCACHE_MODE,
+               RREG32(R300_RB2D_DSTCACHE_MODE) |
+               R300_DC_AUTOFLUSH_ENABLE |
+               R300_DC_DC_DISABLE_IGNORE_PE);
+
+        if (r100_gui_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait GUI idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+        DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);
+}
+
+void r420_gpu_init(struct radeon_device *rdev)
+{
+        r100_hdp_reset(rdev);
+        r420_pipes_init(rdev);
+        if (r300_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+}
+
+
+/*
+ * r420,r423,rv410 VRAM info
+ */
+void r420_vram_info(struct radeon_device *rdev)
+{
+        r300_vram_info(rdev);
+}
+
+
+/*
+ * Debugfs info
+ */
+#if defined(CONFIG_DEBUG_FS)
+static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t tmp;
+
+        tmp = RREG32(R400_GB_PIPE_SELECT);
+        seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
+        tmp = RREG32(R300_GB_TILE_CONFIG);
+        seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
+        tmp = RREG32(R300_DST_PIPE_CONFIG);
+        seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
+        return 0;
+}
+
+static struct drm_info_list r420_pipes_info_list[] = {
+        {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
+};
+#endif
+
+int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
+#else
+        return 0;
+#endif
+}
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
new file mode 100644
index 000000000000..9070a1c2ce23
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -0,0 +1,749 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __R500_REG_H__
+#define __R500_REG_H__
+
+/* pipe config regs */
+#define R300_GA_POLY_MODE                               0x4288
+#       define R300_FRONT_PTYPE_POINT                   (0 << 4)
+#       define R300_FRONT_PTYPE_LINE                    (1 << 4)
+#       define R300_FRONT_PTYPE_TRIANGE                 (2 << 4)
+#       define R300_BACK_PTYPE_POINT                    (0 << 7)
+#       define R300_BACK_PTYPE_LINE                     (1 << 7)
+#       define R300_BACK_PTYPE_TRIANGE                  (2 << 7)
+#define R300_GA_ROUND_MODE                              0x428c
+#       define R300_GEOMETRY_ROUND_TRUNC                (0 << 0)
+#       define R300_GEOMETRY_ROUND_NEAREST              (1 << 0)
+#       define R300_COLOR_ROUND_TRUNC                   (0 << 2)
+#       define R300_COLOR_ROUND_NEAREST                 (1 << 2)
+#define R300_GB_MSPOS0                                  0x4010
+#       define R300_MS_X0_SHIFT                         0
+#       define R300_MS_Y0_SHIFT                         4
+#       define R300_MS_X1_SHIFT                         8
+#       define R300_MS_Y1_SHIFT                         12
+#       define R300_MS_X2_SHIFT                         16
+#       define R300_MS_Y2_SHIFT                         20
+#       define R300_MSBD0_Y_SHIFT                       24
+#       define R300_MSBD0_X_SHIFT                       28
+#define R300_GB_MSPOS1                                  0x4014
+#       define R300_MS_X3_SHIFT                         0
+#       define R300_MS_Y3_SHIFT                         4
+#       define R300_MS_X4_SHIFT                         8
+#       define R300_MS_Y4_SHIFT                         12
+#       define R300_MS_X5_SHIFT                         16
+#       define R300_MS_Y5_SHIFT                         20
+#       define R300_MSBD1_SHIFT                         24
+
+#define R300_GA_ENHANCE                                 0x4274
+#       define R300_GA_DEADLOCK_CNTL                    (1 << 0)
+#       define R300_GA_FASTSYNC_CNTL                    (1 << 1)
+#define R300_RB3D_DSTCACHE_CTLSTAT              0x4e4c
+#       define R300_RB3D_DC_FLUSH               (2 << 0)
+#       define R300_RB3D_DC_FREE                (2 << 2)
+#       define R300_RB3D_DC_FINISH              (1 << 4)
+#define R300_RB3D_ZCACHE_CTLSTAT                        0x4f18
+#       define R300_ZC_FLUSH                            (1 << 0)
+#       define R300_ZC_FREE                             (1 << 1)
+#       define R300_ZC_FLUSH_ALL                        0x3
+#define R400_GB_PIPE_SELECT             0x402c
+#define R500_DYN_SCLK_PWMEM_PIPE        0x000d /* PLL */
+#define R500_SU_REG_DEST                0x42c8
+#define R300_GB_TILE_CONFIG             0x4018
+#       define R300_ENABLE_TILING       (1 << 0)
+#       define R300_PIPE_COUNT_RV350    (0 << 1)
+#       define R300_PIPE_COUNT_R300     (3 << 1)
+#       define R300_PIPE_COUNT_R420_3P  (6 << 1)
+#       define R300_PIPE_COUNT_R420     (7 << 1)
+#       define R300_TILE_SIZE_8         (0 << 4)
+#       define R300_TILE_SIZE_16        (1 << 4)
+#       define R300_TILE_SIZE_32        (2 << 4)
+#       define R300_SUBPIXEL_1_12       (0 << 16)
+#       define R300_SUBPIXEL_1_16       (1 << 16)
+#define R300_DST_PIPE_CONFIG            0x170c
+#       define R300_PIPE_AUTO_CONFIG    (1 << 31)
+#define R300_RB2D_DSTCACHE_MODE         0x3428
+#       define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
+#       define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
+
+#define RADEON_CP_STAT          0x7C0
+#define RADEON_RBBM_CMDFIFO_ADDR        0xE70
+#define RADEON_RBBM_CMDFIFO_DATA        0xE74
+#define RADEON_ISYNC_CNTL               0x1724
+#       define RADEON_ISYNC_ANY2D_IDLE3D        (1 << 0)
+#       define RADEON_ISYNC_ANY3D_IDLE2D        (1 << 1)
+#       define RADEON_ISYNC_TRIG2D_IDLE3D       (1 << 2)
+#       define RADEON_ISYNC_TRIG3D_IDLE2D       (1 << 3)
+#       define RADEON_ISYNC_WAIT_IDLEGUI        (1 << 4)
+#       define RADEON_ISYNC_CPSCRATCH_IDLEGUI   (1 << 5)
+
+#define RS480_NB_MC_INDEX               0x168
+#       define RS480_NB_MC_IND_WR_EN    (1 << 8)
+#define RS480_NB_MC_DATA                0x16c
+
+/*
+ * RS690
+ */
+#define RS690_MCCFG_FB_LOCATION         0x100
+#define         RS690_MC_FB_START_MASK          0x0000FFFF
+#define         RS690_MC_FB_START_SHIFT         0
+#define         RS690_MC_FB_TOP_MASK            0xFFFF0000
+#define         RS690_MC_FB_TOP_SHIFT           16
+#define RS690_MCCFG_AGP_LOCATION        0x101
+#define         RS690_MC_AGP_START_MASK         0x0000FFFF
+#define         RS690_MC_AGP_START_SHIFT        0
+#define         RS690_MC_AGP_TOP_MASK           0xFFFF0000
+#define         RS690_MC_AGP_TOP_SHIFT          16
+#define RS690_MCCFG_AGP_BASE            0x102
+#define RS690_MCCFG_AGP_BASE_2          0x103
+#define RS690_MC_INIT_MISC_LAT_TIMER            0x104
+#define RS690_HDP_FB_LOCATION           0x0134
+#define RS690_MC_INDEX                          0x78
+#       define RS690_MC_INDEX_MASK              0x1ff
+#       define RS690_MC_INDEX_WR_EN             (1 << 9)
+#       define RS690_MC_INDEX_WR_ACK            0x7f
+#define RS690_MC_DATA                           0x7c
+#define RS690_MC_STATUS                         0x90
+#define RS690_MC_STATUS_IDLE                    (1 << 0)
+#define RS480_AGP_BASE_2                0x0164
+#define RS480_MC_MISC_CNTL              0x18
+#       define RS480_DISABLE_GTW        (1 << 1)
+#       define RS480_GART_INDEX_REG_EN  (1 << 12)
+#       define RS690_BLOCK_GFX_D3_EN    (1 << 14)
+#define RS480_GART_FEATURE_ID           0x2b
+#       define RS480_HANG_EN            (1 << 11)
+#       define RS480_TLB_ENABLE         (1 << 18)
+#       define RS480_P2P_ENABLE         (1 << 19)
+#       define RS480_GTW_LAC_EN         (1 << 25)
+#       define RS480_2LEVEL_GART        (0 << 30)
+#       define RS480_1LEVEL_GART        (1 << 30)
+#       define RS480_PDC_EN             (1 << 31)
+#define RS480_GART_BASE                 0x2c
+#define RS480_GART_CACHE_CNTRL          0x2e
+#       define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
+#define RS480_AGP_ADDRESS_SPACE_SIZE    0x38
+#       define RS480_GART_EN            (1 << 0)
+#       define RS480_VA_SIZE_32MB       (0 << 1)
+#       define RS480_VA_SIZE_64MB       (1 << 1)
+#       define RS480_VA_SIZE_128MB      (2 << 1)
+#       define RS480_VA_SIZE_256MB      (3 << 1)
+#       define RS480_VA_SIZE_512MB      (4 << 1)
+#       define RS480_VA_SIZE_1GB        (5 << 1)
+#       define RS480_VA_SIZE_2GB        (6 << 1)
+#define RS480_AGP_MODE_CNTL             0x39
+#       define RS480_POST_GART_Q_SIZE   (1 << 18)
+#       define RS480_NONGART_SNOOP      (1 << 19)
+#       define RS480_AGP_RD_BUF_SIZE    (1 << 20)
+#       define RS480_REQ_TYPE_SNOOP_SHIFT 22
+#       define RS480_REQ_TYPE_SNOOP_MASK  0x3
+#       define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
+
+#define RS690_AIC_CTRL_SCRATCH          0x3A
+#       define RS690_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1)
+
+/*
+ * RS600
+ */
+#define RS600_MC_STATUS                         0x0
+#define RS600_MC_STATUS_IDLE                    (1 << 0)
+#define RS600_MC_INDEX                          0x70
+#       define RS600_MC_ADDR_MASK               0xffff
+#       define RS600_MC_IND_SEQ_RBS_0           (1 << 16)
+#       define RS600_MC_IND_SEQ_RBS_1           (1 << 17)
+#       define RS600_MC_IND_SEQ_RBS_2           (1 << 18)
+#       define RS600_MC_IND_SEQ_RBS_3           (1 << 19)
+#       define RS600_MC_IND_AIC_RBS             (1 << 20)
+#       define RS600_MC_IND_CITF_ARB0           (1 << 21)
+#       define RS600_MC_IND_CITF_ARB1           (1 << 22)
+#       define RS600_MC_IND_WR_EN               (1 << 23)
+#define RS600_MC_DATA                           0x74
+#define RS600_MC_STATUS                         0x0
+#       define RS600_MC_IDLE                    (1 << 1)
+#define RS600_MC_FB_LOCATION                    0x4
+#define         RS600_MC_FB_START_MASK          0x0000FFFF
+#define         RS600_MC_FB_START_SHIFT         0
+#define         RS600_MC_FB_TOP_MASK            0xFFFF0000
+#define         RS600_MC_FB_TOP_SHIFT           16
+#define RS600_MC_AGP_LOCATION                   0x5
+#define         RS600_MC_AGP_START_MASK         0x0000FFFF
+#define         RS600_MC_AGP_START_SHIFT        0
+#define         RS600_MC_AGP_TOP_MASK           0xFFFF0000
+#define         RS600_MC_AGP_TOP_SHIFT          16
+#define RS600_MC_AGP_BASE                          0x6
+#define RS600_MC_AGP_BASE_2                        0x7
+#define RS600_MC_CNTL1                          0x9
+#       define RS600_ENABLE_PAGE_TABLES         (1 << 26)
+#define RS600_MC_PT0_CNTL                       0x100
+#       define RS600_ENABLE_PT                  (1 << 0)
+#       define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15)
+#       define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21)
+#       define RS600_INVALIDATE_ALL_L1_TLBS     (1 << 28)
+#       define RS600_INVALIDATE_L2_CACHE        (1 << 29)
+#define RS600_MC_PT0_CONTEXT0_CNTL              0x102
+#       define RS600_ENABLE_PAGE_TABLE          (1 << 0)
+#       define RS600_PAGE_TABLE_TYPE_FLAT       (0 << 1)
+#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR   0x112
+#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR  0x114
+#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c
+#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR    0x12c
+#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR   0x13c
+#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR     0x14c
+#define RS600_MC_PT0_CLIENT0_CNTL               0x16c
+#       define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE       (1 << 0)
+#       define RS600_TRANSLATION_MODE_OVERRIDE              (1 << 1)
+#       define RS600_SYSTEM_ACCESS_MODE_MASK                (3 << 8)
+#       define RS600_SYSTEM_ACCESS_MODE_PA_ONLY             (0 << 8)
+#       define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP         (1 << 8)
+#       define RS600_SYSTEM_ACCESS_MODE_IN_SYS              (2 << 8)
+#       define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS          (3 << 8)
+#       define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH        (0 << 10)
+#       define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE       (1 << 10)
+#       define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11)
+#       define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)
+#       define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
+#       define RS600_INVALIDATE_L1_TLB          (1 << 20)
+/* rs600/rs690/rs740 */
+#       define RS600_BUS_MASTER_DIS             (1 << 14)
+#       define RS600_MSI_REARM                  (1 << 20)
+/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
+
+
+
+#define RV515_MC_FB_LOCATION            0x01
+#define         RV515_MC_FB_START_MASK          0x0000FFFF
+#define         RV515_MC_FB_START_SHIFT         0
+#define         RV515_MC_FB_TOP_MASK            0xFFFF0000
+#define         RV515_MC_FB_TOP_SHIFT           16
+#define RV515_MC_AGP_LOCATION           0x02
+#define         RV515_MC_AGP_START_MASK         0x0000FFFF
+#define         RV515_MC_AGP_START_SHIFT        0
+#define         RV515_MC_AGP_TOP_MASK           0xFFFF0000
+#define         RV515_MC_AGP_TOP_SHIFT          16
+#define RV515_MC_AGP_BASE               0x03
+#define RV515_MC_AGP_BASE_2             0x04
+
+#define R520_MC_FB_LOCATION             0x04
+#define         R520_MC_FB_START_MASK           0x0000FFFF
+#define         R520_MC_FB_START_SHIFT          0
+#define         R520_MC_FB_TOP_MASK             0xFFFF0000
+#define         R520_MC_FB_TOP_SHIFT            16
+#define R520_MC_AGP_LOCATION            0x05
+#define         R520_MC_AGP_START_MASK          0x0000FFFF
+#define         R520_MC_AGP_START_SHIFT         0
+#define         R520_MC_AGP_TOP_MASK            0xFFFF0000
+#define         R520_MC_AGP_TOP_SHIFT           16
+#define R520_MC_AGP_BASE                0x06
+#define R520_MC_AGP_BASE_2              0x07
+
+
+#define AVIVO_MC_INDEX                                          0x0070
+#define R520_MC_STATUS 0x00
+#define R520_MC_STATUS_IDLE (1<<1)
+#define RV515_MC_STATUS 0x08
+#define RV515_MC_STATUS_IDLE (1<<4)
+#define RV515_MC_INIT_MISC_LAT_TIMER            0x09
+#define AVIVO_MC_DATA                                           0x0074
+
+#define R520_MC_IND_INDEX 0x70
+#define R520_MC_IND_WR_EN (1 << 24)
+#define R520_MC_IND_DATA  0x74
+
+#define RV515_MC_CNTL          0x5
+#       define RV515_MEM_NUM_CHANNELS_MASK  0x3
+#define R520_MC_CNTL0          0x8
+#       define R520_MEM_NUM_CHANNELS_MASK  (0x3 << 24)
+#       define R520_MEM_NUM_CHANNELS_SHIFT  24
+#       define R520_MC_CHANNEL_SIZE  (1 << 23)
+
+#define AVIVO_CP_DYN_CNTL                              0x000f /* PLL */
+#       define AVIVO_CP_FORCEON                        (1 << 0)
+#define AVIVO_E2_DYN_CNTL                              0x0011 /* PLL */
+#       define AVIVO_E2_FORCEON                        (1 << 0)
+#define AVIVO_IDCT_DYN_CNTL                            0x0013 /* PLL */
+#       define AVIVO_IDCT_FORCEON                      (1 << 0)
+
+#define AVIVO_HDP_FB_LOCATION 0x134
+
+#define AVIVO_VGA_RENDER_CONTROL                                0x0300
+#       define AVIVO_VGA_VSTATUS_CNTL_MASK                      (3 << 16)
+#define AVIVO_D1VGA_CONTROL                                     0x0330
+#       define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)
+#       define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8)
+#       define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9)
+#       define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
+#       define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16)
+#       define AVIVO_DVGA_CONTROL_ROTATE (1<<24)
+#define AVIVO_D2VGA_CONTROL                                     0x0338
+
+#define AVIVO_EXT1_PPLL_REF_DIV_SRC                             0x400
+#define AVIVO_EXT1_PPLL_REF_DIV                                 0x404
+#define AVIVO_EXT1_PPLL_UPDATE_LOCK                             0x408
+#define AVIVO_EXT1_PPLL_UPDATE_CNTL                             0x40c
+
+#define AVIVO_EXT2_PPLL_REF_DIV_SRC                             0x410
+#define AVIVO_EXT2_PPLL_REF_DIV                                 0x414
+#define AVIVO_EXT2_PPLL_UPDATE_LOCK                             0x418
+#define AVIVO_EXT2_PPLL_UPDATE_CNTL                             0x41c
+
+#define AVIVO_EXT1_PPLL_FB_DIV                                   0x430
+#define AVIVO_EXT2_PPLL_FB_DIV                                   0x434
+
+#define AVIVO_EXT1_PPLL_POST_DIV_SRC                                 0x438
+#define AVIVO_EXT1_PPLL_POST_DIV                                     0x43c
+
+#define AVIVO_EXT2_PPLL_POST_DIV_SRC                                 0x440
+#define AVIVO_EXT2_PPLL_POST_DIV                                     0x444
+
+#define AVIVO_EXT1_PPLL_CNTL                                    0x448
+#define AVIVO_EXT2_PPLL_CNTL                                    0x44c
+
+#define AVIVO_P1PLL_CNTL                                        0x450
+#define AVIVO_P2PLL_CNTL                                        0x454
+#define AVIVO_P1PLL_INT_SS_CNTL                                 0x458
+#define AVIVO_P2PLL_INT_SS_CNTL                                 0x45c
+#define AVIVO_P1PLL_TMDSA_CNTL                                  0x460
+#define AVIVO_P2PLL_LVTMA_CNTL                                  0x464
+
+#define AVIVO_PCLK_CRTC1_CNTL                                   0x480
+#define AVIVO_PCLK_CRTC2_CNTL                                   0x484
+
+#define AVIVO_D1CRTC_H_TOTAL                                    0x6000
+#define AVIVO_D1CRTC_H_BLANK_START_END                          0x6004
+#define AVIVO_D1CRTC_H_SYNC_A                                   0x6008
+#define AVIVO_D1CRTC_H_SYNC_A_CNTL                              0x600c
+#define AVIVO_D1CRTC_H_SYNC_B                                   0x6010
+#define AVIVO_D1CRTC_H_SYNC_B_CNTL                              0x6014
+
+#define AVIVO_D1CRTC_V_TOTAL                                    0x6020
+#define AVIVO_D1CRTC_V_BLANK_START_END                          0x6024
+#define AVIVO_D1CRTC_V_SYNC_A                                   0x6028
+#define AVIVO_D1CRTC_V_SYNC_A_CNTL                              0x602c
+#define AVIVO_D1CRTC_V_SYNC_B                                   0x6030
+#define AVIVO_D1CRTC_V_SYNC_B_CNTL                              0x6034
+
+#define AVIVO_D1CRTC_CONTROL                                    0x6080
+#       define AVIVO_CRTC_EN                                    (1 << 0)
+#define AVIVO_D1CRTC_BLANK_CONTROL                              0x6084
+#define AVIVO_D1CRTC_INTERLACE_CONTROL                          0x6088
+#define AVIVO_D1CRTC_INTERLACE_STATUS                           0x608c
+#define AVIVO_D1CRTC_STEREO_CONTROL                             0x60c4
+
+/* master controls */
+#define AVIVO_DC_CRTC_MASTER_EN                                 0x60f8
+#define AVIVO_DC_CRTC_TV_CONTROL                                0x60fc
+
+#define AVIVO_D1GRPH_ENABLE                                     0x6100
+#define AVIVO_D1GRPH_CONTROL                                    0x6104
+#       define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP                  (0 << 0)
+#       define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP                 (1 << 0)
+#       define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP                 (2 << 0)
+#       define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP                 (3 << 0)
+
+#       define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED                (0 << 8)
+
+#       define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555              (0 << 8)
+#       define AVIVO_D1GRPH_CONTROL_16BPP_RGB565                (1 << 8)
+#       define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444              (2 << 8)
+#       define AVIVO_D1GRPH_CONTROL_16BPP_AI88                  (3 << 8)
+#       define AVIVO_D1GRPH_CONTROL_16BPP_MONO16                (4 << 8)
+
+#       define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888              (0 << 8)
+#       define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010           (1 << 8)
+#       define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL               (2 << 8)
+#       define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010        (3 << 8)
+
+
+#       define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616          (0 << 8)
+
+#       define AVIVO_D1GRPH_SWAP_RB                             (1 << 16)
+#       define AVIVO_D1GRPH_TILED                               (1 << 20)
+#       define AVIVO_D1GRPH_MACRO_ADDRESS_MODE                  (1 << 21)
+
+#define AVIVO_D1GRPH_LUT_SEL                                    0x6108
+#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS                    0x6110
+#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS                  0x6118
+#define AVIVO_D1GRPH_PITCH                                      0x6120
+#define AVIVO_D1GRPH_SURFACE_OFFSET_X                           0x6124
+#define AVIVO_D1GRPH_SURFACE_OFFSET_Y                           0x6128
+#define AVIVO_D1GRPH_X_START                                    0x612c
+#define AVIVO_D1GRPH_Y_START                                    0x6130
+#define AVIVO_D1GRPH_X_END                                      0x6134
+#define AVIVO_D1GRPH_Y_END                                      0x6138
+#define AVIVO_D1GRPH_UPDATE                                     0x6144
+#       define AVIVO_D1GRPH_UPDATE_LOCK                         (1 << 16)
+#define AVIVO_D1GRPH_FLIP_CONTROL                               0x6148
+
+#define AVIVO_D1CUR_CONTROL                     0x6400
+#       define AVIVO_D1CURSOR_EN                (1 << 0)
+#       define AVIVO_D1CURSOR_MODE_SHIFT        8
+#       define AVIVO_D1CURSOR_MODE_MASK         (3 << 8)
+#       define AVIVO_D1CURSOR_MODE_24BPP        2
+#define AVIVO_D1CUR_SURFACE_ADDRESS             0x6408
+#define AVIVO_D1CUR_SIZE                        0x6410
+#define AVIVO_D1CUR_POSITION                    0x6414
+#define AVIVO_D1CUR_HOT_SPOT                    0x6418
+#define AVIVO_D1CUR_UPDATE                      0x6424
+#       define AVIVO_D1CURSOR_UPDATE_LOCK       (1 << 16)
+
+#define AVIVO_DC_LUT_RW_SELECT                  0x6480
+#define AVIVO_DC_LUT_RW_MODE                    0x6484
+#define AVIVO_DC_LUT_RW_INDEX                   0x6488
+#define AVIVO_DC_LUT_SEQ_COLOR                  0x648c
+#define AVIVO_DC_LUT_PWL_DATA                   0x6490
+#define AVIVO_DC_LUT_30_COLOR                   0x6494
+#define AVIVO_DC_LUT_READ_PIPE_SELECT           0x6498
+#define AVIVO_DC_LUT_WRITE_EN_MASK              0x649c
+#define AVIVO_DC_LUT_AUTOFILL                   0x64a0
+
+#define AVIVO_DC_LUTA_CONTROL                   0x64c0
+#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE         0x64c4
+#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN        0x64c8
+#define AVIVO_DC_LUTA_BLACK_OFFSET_RED          0x64cc
+#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE         0x64d0
+#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN        0x64d4
+#define AVIVO_DC_LUTA_WHITE_OFFSET_RED          0x64d8
+
+#define AVIVO_DC_LB_MEMORY_SPLIT                0x6520
+#       define AVIVO_DC_LB_MEMORY_SPLIT_MASK    0x3
+#       define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT   0
+#       define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF  0
+#       define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q    1
+#       define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY        2
+#       define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q    3
+#       define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
+#       define AVIVO_DC_LB_DISP1_END_ADR_SHIFT  4
+#       define AVIVO_DC_LB_DISP1_END_ADR_MASK   0x7ff
+
+#define R500_DxMODE_INT_MASK 0x6540
+#define R500_D1MODE_INT_MASK (1<<0)
+#define R500_D2MODE_INT_MASK (1<<8)
+
+#define AVIVO_D1MODE_DATA_FORMAT                0x6528
+#       define AVIVO_D1MODE_INTERLEAVE_EN       (1 << 0)
+#define AVIVO_D1MODE_DESKTOP_HEIGHT             0x652C
+#define AVIVO_D1MODE_VIEWPORT_START             0x6580
+#define AVIVO_D1MODE_VIEWPORT_SIZE              0x6584
+#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT    0x6588
+#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM    0x658c
+
+#define AVIVO_D1SCL_SCALER_ENABLE               0x6590
+#define AVIVO_D1SCL_SCALER_TAP_CONTROL          0x6594
+#define AVIVO_D1SCL_UPDATE                      0x65cc
+#       define AVIVO_D1SCL_UPDATE_LOCK          (1 << 16)
+
+/* second crtc */
+#define AVIVO_D2CRTC_H_TOTAL                                    0x6800
+#define AVIVO_D2CRTC_H_BLANK_START_END                          0x6804
+#define AVIVO_D2CRTC_H_SYNC_A                                   0x6808
+#define AVIVO_D2CRTC_H_SYNC_A_CNTL                              0x680c
+#define AVIVO_D2CRTC_H_SYNC_B                                   0x6810
+#define AVIVO_D2CRTC_H_SYNC_B_CNTL                              0x6814
+
+#define AVIVO_D2CRTC_V_TOTAL                                    0x6820
+#define AVIVO_D2CRTC_V_BLANK_START_END                          0x6824
+#define AVIVO_D2CRTC_V_SYNC_A                                   0x6828
+#define AVIVO_D2CRTC_V_SYNC_A_CNTL                              0x682c
+#define AVIVO_D2CRTC_V_SYNC_B                                   0x6830
+#define AVIVO_D2CRTC_V_SYNC_B_CNTL                              0x6834
+
+#define AVIVO_D2CRTC_CONTROL                                    0x6880
+#define AVIVO_D2CRTC_BLANK_CONTROL                              0x6884
+#define AVIVO_D2CRTC_INTERLACE_CONTROL                          0x6888
+#define AVIVO_D2CRTC_INTERLACE_STATUS                           0x688c
+#define AVIVO_D2CRTC_STEREO_CONTROL                             0x68c4
+
+#define AVIVO_D2GRPH_ENABLE                                     0x6900
+#define AVIVO_D2GRPH_CONTROL                                    0x6904
+#define AVIVO_D2GRPH_LUT_SEL                                    0x6908
+#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS                    0x6910
+#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS                  0x6918
+#define AVIVO_D2GRPH_PITCH                                      0x6920
+#define AVIVO_D2GRPH_SURFACE_OFFSET_X                           0x6924
+#define AVIVO_D2GRPH_SURFACE_OFFSET_Y                           0x6928
+#define AVIVO_D2GRPH_X_START                                    0x692c
+#define AVIVO_D2GRPH_Y_START                                    0x6930
+#define AVIVO_D2GRPH_X_END                                      0x6934
+#define AVIVO_D2GRPH_Y_END                                      0x6938
+#define AVIVO_D2GRPH_UPDATE                                     0x6944
+#define AVIVO_D2GRPH_FLIP_CONTROL                               0x6948
+
+#define AVIVO_D2CUR_CONTROL                     0x6c00
+#define AVIVO_D2CUR_SURFACE_ADDRESS             0x6c08
+#define AVIVO_D2CUR_SIZE                        0x6c10
+#define AVIVO_D2CUR_POSITION                    0x6c14
+
+#define AVIVO_D2MODE_VIEWPORT_START             0x6d80
+#define AVIVO_D2MODE_VIEWPORT_SIZE              0x6d84
+#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT    0x6d88
+#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM    0x6d8c
+
+#define AVIVO_D2SCL_SCALER_ENABLE               0x6d90
+#define AVIVO_D2SCL_SCALER_TAP_CONTROL          0x6d94
+
+#define AVIVO_DDIA_BIT_DEPTH_CONTROL                            0x7214
+
+#define AVIVO_DACA_ENABLE                                       0x7800
+#       define AVIVO_DAC_ENABLE                         (1 << 0)
+#define AVIVO_DACA_SOURCE_SELECT                                0x7804
+#       define AVIVO_DAC_SOURCE_CRTC1                   (0 << 0)
+#       define AVIVO_DAC_SOURCE_CRTC2                   (1 << 0)
+#       define AVIVO_DAC_SOURCE_TV                      (2 << 0)
+
+#define AVIVO_DACA_FORCE_OUTPUT_CNTL                            0x783c
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN             (1 << 0)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT            (8)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE             (1 << 0)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN            (1 << 1)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED              (1 << 2)
+# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY       (1 << 24)
+#define AVIVO_DACA_POWERDOWN                                    0x7850
+# define AVIVO_DACA_POWERDOWN_POWERDOWN                         (1 << 0)
+# define AVIVO_DACA_POWERDOWN_BLUE                              (1 << 8)
+# define AVIVO_DACA_POWERDOWN_GREEN                             (1 << 16)
+# define AVIVO_DACA_POWERDOWN_RED                               (1 << 24)
+
+#define AVIVO_DACB_ENABLE                                       0x7a00
+#define AVIVO_DACB_SOURCE_SELECT                                0x7a04
+#define AVIVO_DACB_FORCE_OUTPUT_CNTL                            0x7a3c
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN             (1 << 0)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT            (8)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE             (1 << 0)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN            (1 << 1)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED              (1 << 2)
+# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY       (1 << 24)
+#define AVIVO_DACB_POWERDOWN                                    0x7a50
+# define AVIVO_DACB_POWERDOWN_POWERDOWN                         (1 << 0)
+# define AVIVO_DACB_POWERDOWN_BLUE                              (1 << 8)
+# define AVIVO_DACB_POWERDOWN_GREEN                             (1 << 16)
+# define AVIVO_DACB_POWERDOWN_RED
+
+#define AVIVO_TMDSA_CNTL                    0x7880
+#   define AVIVO_TMDSA_CNTL_ENABLE               (1 << 0)
+#   define AVIVO_TMDSA_CNTL_HPD_MASK             (1 << 4)
+#   define AVIVO_TMDSA_CNTL_HPD_SELECT           (1 << 8)
+#   define AVIVO_TMDSA_CNTL_SYNC_PHASE           (1 << 12)
+#   define AVIVO_TMDSA_CNTL_PIXEL_ENCODING       (1 << 16)
+#   define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE     (1 << 24)
+#   define AVIVO_TMDSA_CNTL_SWAP                 (1 << 28)
+#define AVIVO_TMDSA_SOURCE_SELECT                               0x7884
+/* 78a8 appears to be some kind of (reasonably tolerant) clock?
+ * 78d0 definitely hits the transmitter, definitely clock. */
+/* MYSTERY1 This appears to control dithering? */
+#define AVIVO_TMDSA_BIT_DEPTH_CONTROL           0x7894
+#   define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN           (1 << 0)
+#   define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH        (1 << 4)
+#   define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN     (1 << 8)
+#   define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH  (1 << 12)
+#   define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN    (1 << 16)
+#   define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
+#   define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL        (1 << 24)
+#   define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
+#define AVIVO_TMDSA_DCBALANCER_CONTROL                  0x78d0
+#   define AVIVO_TMDSA_DCBALANCER_CONTROL_EN                  (1 << 0)
+#   define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN             (1 << 8)
+#   define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT       (16)
+#   define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE               (1 << 24)
+#define AVIVO_TMDSA_DATA_SYNCHRONIZATION                0x78d8
+#   define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL           (1 << 0)
+#   define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG          (1 << 8)
+#define AVIVO_TMDSA_CLOCK_ENABLE            0x7900
+#define AVIVO_TMDSA_TRANSMITTER_ENABLE              0x7904
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE          (1 << 0)
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN             (1 << 1)
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN            (1 << 2)
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN            (1 << 3)
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN            (1 << 4)
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE          (1 << 8)
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN            (1 << 10)
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN            (1 << 11)
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN            (1 << 12)
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK  (1 << 16)
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK     (1 << 17)
+#   define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK     (1 << 18)
+
+#define AVIVO_TMDSA_TRANSMITTER_CONTROL                         0x7910
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE       (1 << 0)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET        (1 << 1)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT       (2)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL         (1 << 4)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP          (1 << 5)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK            (1 << 8)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS  (1 << 13)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK            (1 << 14)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS  (1 << 15)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL       (1 << 28)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA     (1 << 29)
+#       define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL       (1 << 31)
+
+#define AVIVO_LVTMA_CNTL                                        0x7a80
+#   define AVIVO_LVTMA_CNTL_ENABLE               (1 << 0)
+#   define AVIVO_LVTMA_CNTL_HPD_MASK             (1 << 4)
+#   define AVIVO_LVTMA_CNTL_HPD_SELECT           (1 << 8)
+#   define AVIVO_LVTMA_CNTL_SYNC_PHASE           (1 << 12)
+#   define AVIVO_LVTMA_CNTL_PIXEL_ENCODING       (1 << 16)
+#   define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE     (1 << 24)
+#   define AVIVO_LVTMA_CNTL_SWAP                 (1 << 28)
+#define AVIVO_LVTMA_SOURCE_SELECT                               0x7a84
+#define AVIVO_LVTMA_COLOR_FORMAT                                0x7a88
+#define AVIVO_LVTMA_BIT_DEPTH_CONTROL                           0x7a94
+#   define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN           (1 << 0)
+#   define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH        (1 << 4)
+#   define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN     (1 << 8)
+#   define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH  (1 << 12)
+#   define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN    (1 << 16)
+#   define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
+#   define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL        (1 << 24)
+#   define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
+
+
+
+#define AVIVO_LVTMA_DCBALANCER_CONTROL                  0x7ad0
+#   define AVIVO_LVTMA_DCBALANCER_CONTROL_EN                  (1 << 0)
+#   define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN             (1 << 8)
+#   define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT       (16)
+#   define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE               (1 << 24)
+
+#define AVIVO_LVTMA_DATA_SYNCHRONIZATION                0x78d8
+#   define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL           (1 << 0)
+#   define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG          (1 << 8)
+#define R500_LVTMA_CLOCK_ENABLE                 0x7b00
+#define R600_LVTMA_CLOCK_ENABLE                 0x7b04
+
+#define R500_LVTMA_TRANSMITTER_ENABLE              0x7b04
+#define R600_LVTMA_TRANSMITTER_ENABLE              0x7b08
+#   define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN             (1 << 1)
+#   define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN            (1 << 2)
+#   define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN            (1 << 3)
+#   define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN            (1 << 4)
+#   define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN            (1 << 5)
+#   define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN             (1 << 9)
+#   define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN            (1 << 10)
+#   define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN            (1 << 11)
+#   define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN            (1 << 12)
+#   define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK     (1 << 17)
+#   define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK     (1 << 18)
+
+#define R500_LVTMA_TRANSMITTER_CONTROL                          0x7b10
+#define R600_LVTMA_TRANSMITTER_CONTROL                          0x7b14
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE         (1 << 0)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET          (1 << 1)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL           (1 << 4)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP            (1 << 5)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN   (1 << 6)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK              (1 << 8)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS    (1 << 13)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK              (1 << 14)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS    (1 << 15)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT  (16)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL         (1 << 28)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA       (1 << 29)
+#       define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
+
+#define R500_LVTMA_PWRSEQ_CNTL                                          0x7af0
+#define R600_LVTMA_PWRSEQ_CNTL                                          0x7af4
+#       define AVIVO_LVTMA_PWRSEQ_EN                                        (1 << 0)
+#       define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK                           (1 << 2)
+#       define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK                            (1 << 3)
+#       define AVIVO_LVTMA_PWRSEQ_TARGET_STATE                              (1 << 4)
+#       define AVIVO_LVTMA_SYNCEN                                           (1 << 8)
+#       define AVIVO_LVTMA_SYNCEN_OVRD                                      (1 << 9)
+#       define AVIVO_LVTMA_SYNCEN_POL                                       (1 << 10)
+#       define AVIVO_LVTMA_DIGON                                            (1 << 16)
+#       define AVIVO_LVTMA_DIGON_OVRD                                       (1 << 17)
+#       define AVIVO_LVTMA_DIGON_POL                                        (1 << 18)
+#       define AVIVO_LVTMA_BLON                                             (1 << 24)
+#       define AVIVO_LVTMA_BLON_OVRD                                        (1 << 25)
+#       define AVIVO_LVTMA_BLON_POL                                         (1 << 26)
+
+#define R500_LVTMA_PWRSEQ_STATE                        0x7af4
+#define R600_LVTMA_PWRSEQ_STATE                        0x7af8
+#       define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R          (1 << 0)
+#       define AVIVO_LVTMA_PWRSEQ_STATE_DIGON                   (1 << 1)
+#       define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN                  (1 << 2)
+#       define AVIVO_LVTMA_PWRSEQ_STATE_BLON                    (1 << 3)
+#       define AVIVO_LVTMA_PWRSEQ_STATE_DONE                    (1 << 4)
+#       define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT            (8)
+
+#define AVIVO_LVDS_BACKLIGHT_CNTL                       0x7af8
+#       define AVIVO_LVDS_BACKLIGHT_CNTL_EN                     (1 << 0)
+#       define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK          0x0000ff00
+#       define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT         8
+
+#define AVIVO_DVOA_BIT_DEPTH_CONTROL                    0x7988
+
+#define AVIVO_GPIO_0                        0x7e30
+#define AVIVO_GPIO_1                        0x7e40
+#define AVIVO_GPIO_2                        0x7e50
+#define AVIVO_GPIO_3                        0x7e60
+
+#define AVIVO_DC_GPIO_HPD_Y                 0x7e9c
+
+#define AVIVO_I2C_STATUS                                        0x7d30
+#       define AVIVO_I2C_STATUS_DONE                            (1 << 0)
+#       define AVIVO_I2C_STATUS_NACK                            (1 << 1)
+#       define AVIVO_I2C_STATUS_HALT                            (1 << 2)
+#       define AVIVO_I2C_STATUS_GO                              (1 << 3)
+#       define AVIVO_I2C_STATUS_MASK                            0x7
+/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
+ * DONE? */
+#       define AVIVO_I2C_STATUS_CMD_RESET                       0x7
+#       define AVIVO_I2C_STATUS_CMD_WAIT                        (1 << 3)
+#define AVIVO_I2C_STOP                                          0x7d34
+#define AVIVO_I2C_START_CNTL                            0x7d38
+#       define AVIVO_I2C_START                                          (1 << 8)
+#       define AVIVO_I2C_CONNECTOR0                                     (0 << 16)
+#       define AVIVO_I2C_CONNECTOR1                                     (1 << 16)
+#define R520_I2C_START (1<<0)
+#define R520_I2C_STOP (1<<1)
+#define R520_I2C_RX (1<<2)
+#define R520_I2C_EN (1<<8)
+#define R520_I2C_DDC1 (0<<16)
+#define R520_I2C_DDC2 (1<<16)
+#define R520_I2C_DDC3 (2<<16)
+#define R520_I2C_DDC_MASK (3<<16)
+#define AVIVO_I2C_CONTROL2                                      0x7d3c
+#       define AVIVO_I2C_7D3C_SIZE_SHIFT                        8
+#       define AVIVO_I2C_7D3C_SIZE_MASK                         (0xf << 8)
+#define AVIVO_I2C_CONTROL3                                              0x7d40
+/* Reading is done 4 bytes at a time: read the bottom 8 bits from
+ * 7d44, four times in a row.
+ * Writing is a little more complex.  First write DATA with
+ * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
+ * magic number, zz is, I think, the slave address, and yy is the byte
+ * you want to write. */
+#define AVIVO_I2C_DATA                                          0x7d44
+#define R520_I2C_ADDR_COUNT_MASK (0x7)
+#define R520_I2C_DATA_COUNT_SHIFT (8)
+#define R520_I2C_DATA_COUNT_MASK (0xF00)
+#define AVIVO_I2C_CNTL                                          0x7d50
+#       define AVIVO_I2C_EN                                                     (1 << 0)
+#       define AVIVO_I2C_RESET                                          (1 << 8)
+
+#endif
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
new file mode 100644
index 000000000000..570a244bd88b
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+/* r520,rv530,rv560,rv570,r580 depends on : */
+void r100_hdp_reset(struct radeon_device *rdev);
+int rv370_pcie_gart_enable(struct radeon_device *rdev);
+void rv370_pcie_gart_disable(struct radeon_device *rdev);
+void r420_pipes_init(struct radeon_device *rdev);
+void rs600_mc_disable_clients(struct radeon_device *rdev);
+void rs600_disable_vga(struct radeon_device *rdev);
+int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
+int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
+
+/* This files gather functions specifics to:
+ * r520,rv530,rv560,rv570,r580
+ *
+ * Some of these functions might be used by newer ASICs.
+ */
+void r520_gpu_init(struct radeon_device *rdev);
+int r520_mc_wait_for_idle(struct radeon_device *rdev);
+
+
+/*
+ * MC
+ */
+int r520_mc_init(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        int r;
+
+        if (r100_debugfs_rbbm_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
+        }
+        if (rv515_debugfs_pipes_info_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for pipes !\n");
+        }
+        if (rv515_debugfs_ga_info_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for pipes !\n");
+        }
+
+        r520_gpu_init(rdev);
+        rv370_pcie_gart_disable(rdev);
+
+        /* Setup GPU memory space */
+        rdev->mc.vram_location = 0xFFFFFFFFUL;
+        rdev->mc.gtt_location = 0xFFFFFFFFUL;
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r) {
+                        printk(KERN_WARNING "[drm] Disabling AGP\n");
+                        rdev->flags &= ~RADEON_IS_AGP;
+                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+                } else {
+                        rdev->mc.gtt_location = rdev->mc.agp_base;
+                }
+        }
+        r = radeon_mc_setup(rdev);
+        if (r) {
+                return r;
+        }
+
+        /* Program GPU memory space */
+        rs600_mc_disable_clients(rdev);
+        if (r520_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+        /* Write VRAM size in case we are limiting it */
+        WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+        tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+        tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16);
+        tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16);
+        WREG32_MC(R520_MC_FB_LOCATION, tmp);
+        WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
+        WREG32(0x310, rdev->mc.vram_location);
+        if (rdev->flags & RADEON_IS_AGP) {
+                tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
+                tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16);
+                tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16);
+                WREG32_MC(R520_MC_AGP_LOCATION, tmp);
+                WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base);
+                WREG32_MC(R520_MC_AGP_BASE_2, 0);
+        } else {
+                WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF);
+                WREG32_MC(R520_MC_AGP_BASE, 0);
+                WREG32_MC(R520_MC_AGP_BASE_2, 0);
+        }
+        return 0;
+}
+
+void r520_mc_fini(struct radeon_device *rdev)
+{
+        rv370_pcie_gart_disable(rdev);
+        radeon_gart_table_vram_free(rdev);
+        radeon_gart_fini(rdev);
+}
+
+
+/*
+ * Global GPU functions
+ */
+void r520_errata(struct radeon_device *rdev)
+{
+        rdev->pll_errata = 0;
+}
+
+int r520_mc_wait_for_idle(struct radeon_device *rdev)
+{
+        unsigned i;
+        uint32_t tmp;
+
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                /* read MC_STATUS */
+                tmp = RREG32_MC(R520_MC_STATUS);
+                if (tmp & R520_MC_STATUS_IDLE) {
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        return -1;
+}
+
+void r520_gpu_init(struct radeon_device *rdev)
+{
+        unsigned pipe_select_current, gb_pipe_select, tmp;
+
+        r100_hdp_reset(rdev);
+        rs600_disable_vga(rdev);
+        /*
+         * DST_PIPE_CONFIG              0x170C
+         * GB_TILE_CONFIG               0x4018
+         * GB_FIFO_SIZE                 0x4024
+         * GB_PIPE_SELECT               0x402C
+         * GB_PIPE_SELECT2              0x4124
+         *      Z_PIPE_SHIFT                    0
+         *      Z_PIPE_MASK                     0x000000003
+         * GB_FIFO_SIZE2                0x4128
+         *      SC_SFIFO_SIZE_SHIFT             0
+         *      SC_SFIFO_SIZE_MASK              0x000000003
+         *      SC_MFIFO_SIZE_SHIFT             2
+         *      SC_MFIFO_SIZE_MASK              0x00000000C
+         *      FG_SFIFO_SIZE_SHIFT             4
+         *      FG_SFIFO_SIZE_MASK              0x000000030
+         *      ZB_MFIFO_SIZE_SHIFT             6
+         *      ZB_MFIFO_SIZE_MASK              0x0000000C0
+         * GA_ENHANCE                   0x4274
+         * SU_REG_DEST                  0x42C8
+         */
+        /* workaround for RV530 */
+        if (rdev->family == CHIP_RV530) {
+                WREG32(0x4124, 1);
+                WREG32(0x4128, 0xFF);
+        }
+        r420_pipes_init(rdev);
+        gb_pipe_select = RREG32(0x402C);
+        tmp = RREG32(0x170C);
+        pipe_select_current = (tmp >> 2) & 3;
+        tmp = (1 << pipe_select_current) |
+              (((gb_pipe_select >> 8) & 0xF) << 4);
+        WREG32_PLL(0x000D, tmp);
+        if (r520_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+}
+
+
+/*
+ * VRAM info
+ */
+static void r520_vram_get_type(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        rdev->mc.vram_width = 128;
+        rdev->mc.vram_is_ddr = true;
+        tmp = RREG32_MC(R520_MC_CNTL0);
+        switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
+        case 0:
+                rdev->mc.vram_width = 32;
+                break;
+        case 1:
+                rdev->mc.vram_width = 64;
+                break;
+        case 2:
+                rdev->mc.vram_width = 128;
+                break;
+        case 3:
+                rdev->mc.vram_width = 256;
+                break;
+        default:
+                rdev->mc.vram_width = 128;
+                break;
+        }
+        if (tmp & R520_MC_CHANNEL_SIZE)
+                rdev->mc.vram_width *= 2;
+}
+
+void r520_vram_info(struct radeon_device *rdev)
+{
+        r520_vram_get_type(rdev);
+        rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
+
+        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+}
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
new file mode 100644
index 000000000000..c45559fc97fd
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+/* r600,rv610,rv630,rv620,rv635,rv670 depends on : */
+void rs600_mc_disable_clients(struct radeon_device *rdev);
+
+/* This files gather functions specifics to:
+ * r600,rv610,rv630,rv620,rv635,rv670
+ *
+ * Some of these functions might be used by newer ASICs.
+ */
+int r600_mc_wait_for_idle(struct radeon_device *rdev);
+void r600_gpu_init(struct radeon_device *rdev);
+
+
+/*
+ * MC
+ */
+int r600_mc_init(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        r600_gpu_init(rdev);
+
+        /* setup the gart before changing location so we can ask to
+         * discard unmapped mc request
+         */
+        /* FIXME: disable out of gart access */
+        tmp = rdev->mc.gtt_location / 4096;
+        tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp);
+        WREG32(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp);
+        tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096;
+        tmp = REG_SET(R600_LOGICAL_PAGE_NUMBER, tmp);
+        WREG32(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp);
+
+        rs600_mc_disable_clients(rdev);
+        if (r600_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+
+        tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+        tmp = REG_SET(R600_MC_FB_TOP, tmp >> 24);
+        tmp |= REG_SET(R600_MC_FB_BASE, rdev->mc.vram_location >> 24);
+        WREG32(R600_MC_VM_FB_LOCATION, tmp);
+        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
+        tmp = REG_SET(R600_MC_AGP_TOP, tmp >> 22);
+        WREG32(R600_MC_VM_AGP_TOP, tmp);
+        tmp = REG_SET(R600_MC_AGP_BOT, rdev->mc.gtt_location >> 22);
+        WREG32(R600_MC_VM_AGP_BOT, tmp);
+        return 0;
+}
+
+void r600_mc_fini(struct radeon_device *rdev)
+{
+        /* FIXME: implement */
+}
+
+
+/*
+ * Global GPU functions
+ */
+void r600_errata(struct radeon_device *rdev)
+{
+        rdev->pll_errata = 0;
+}
+
+int r600_mc_wait_for_idle(struct radeon_device *rdev)
+{
+        /* FIXME: implement */
+        return 0;
+}
+
+void r600_gpu_init(struct radeon_device *rdev)
+{
+        /* FIXME: implement */
+}
+
+
+/*
+ * VRAM info
+ */
+void r600_vram_get_type(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        int chansize;
+
+        rdev->mc.vram_width = 128;
+        rdev->mc.vram_is_ddr = true;
+
+        tmp = RREG32(R600_RAMCFG);
+        if (tmp & R600_CHANSIZE_OVERRIDE) {
+                chansize = 16;
+        } else if (tmp & R600_CHANSIZE) {
+                chansize = 64;
+        } else {
+                chansize = 32;
+        }
+        if (rdev->family == CHIP_R600) {
+                rdev->mc.vram_width = 8 * chansize;
+        } else if (rdev->family == CHIP_RV670) {
+                rdev->mc.vram_width = 4 * chansize;
+        } else if ((rdev->family == CHIP_RV610) ||
+                        (rdev->family == CHIP_RV620)) {
+                rdev->mc.vram_width = chansize;
+        } else if ((rdev->family == CHIP_RV630) ||
+                        (rdev->family == CHIP_RV635)) {
+                rdev->mc.vram_width = 2 * chansize;
+        }
+}
+
+void r600_vram_info(struct radeon_device *rdev)
+{
+        r600_vram_get_type(rdev);
+        rdev->mc.vram_size = RREG32(R600_CONFIG_MEMSIZE);
+
+        /* Could aper size report 0 ? */
+        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+}
+
+/*
+ * Indirect registers accessor
+ */
+uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        uint32_t r;
+
+        WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff));
+        (void)RREG32(R600_PCIE_PORT_INDEX);
+        r = RREG32(R600_PCIE_PORT_DATA);
+        return r;
+}
+
+void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        WREG32(R600_PCIE_PORT_INDEX, ((reg) & 0xff));
+        (void)RREG32(R600_PCIE_PORT_INDEX);
+        WREG32(R600_PCIE_PORT_DATA, (v));
+        (void)RREG32(R600_PCIE_PORT_DATA);
+}
diff --git a/drivers/gpu/drm/radeon/r600_reg.h b/drivers/gpu/drm/radeon/r600_reg.h
new file mode 100644
index 000000000000..e2d1f5f33f7e
--- /dev/null
+++ b/drivers/gpu/drm/radeon/r600_reg.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __R600_REG_H__
+#define __R600_REG_H__
+
+#define R600_PCIE_PORT_INDEX                0x0038
+#define R600_PCIE_PORT_DATA                 0x003c
+
+#define R600_MC_VM_FB_LOCATION                  0x2180
+#define         R600_MC_FB_BASE_MASK                    0x0000FFFF
+#define         R600_MC_FB_BASE_SHIFT                   0
+#define         R600_MC_FB_TOP_MASK                     0xFFFF0000
+#define         R600_MC_FB_TOP_SHIFT                    16
+#define R600_MC_VM_AGP_TOP                      0x2184
+#define         R600_MC_AGP_TOP_MASK                    0x0003FFFF
+#define         R600_MC_AGP_TOP_SHIFT                   0
+#define R600_MC_VM_AGP_BOT                      0x2188
+#define         R600_MC_AGP_BOT_MASK                    0x0003FFFF
+#define         R600_MC_AGP_BOT_SHIFT                   0
+#define R600_MC_VM_AGP_BASE                     0x218c
+#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR     0x2190
+#define         R600_LOGICAL_PAGE_NUMBER_MASK           0x000FFFFF
+#define         R600_LOGICAL_PAGE_NUMBER_SHIFT          0
+#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR    0x2194
+#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
+
+#define R700_MC_VM_FB_LOCATION                  0x2024
+#define         R700_MC_FB_BASE_MASK                    0x0000FFFF
+#define         R700_MC_FB_BASE_SHIFT                   0
+#define         R700_MC_FB_TOP_MASK                     0xFFFF0000
+#define         R700_MC_FB_TOP_SHIFT                    16
+#define R700_MC_VM_AGP_TOP                      0x2028
+#define         R700_MC_AGP_TOP_MASK                    0x0003FFFF
+#define         R700_MC_AGP_TOP_SHIFT                   0
+#define R700_MC_VM_AGP_BOT                      0x202c
+#define         R700_MC_AGP_BOT_MASK                    0x0003FFFF
+#define         R700_MC_AGP_BOT_SHIFT                   0
+#define R700_MC_VM_AGP_BASE                     0x2030
+#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR     0x2034
+#define         R700_LOGICAL_PAGE_NUMBER_MASK           0x000FFFFF
+#define         R700_LOGICAL_PAGE_NUMBER_SHIFT          0
+#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR    0x2038
+#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
+
+#define R600_RAMCFG                                    0x2408
+#       define R600_CHANSIZE                           (1 << 7)
+#       define R600_CHANSIZE_OVERRIDE                  (1 << 10)
+
+
+#define R600_GENERAL_PWRMGT                                        0x618
+#       define R600_OPEN_DRAIN_PADS                                (1 << 11)
+
+#define R600_LOWER_GPIO_ENABLE                                     0x710
+#define R600_CTXSW_VID_LOWER_GPIO_CNTL                             0x718
+#define R600_HIGH_VID_LOWER_GPIO_CNTL                              0x71c
+#define R600_MEDIUM_VID_LOWER_GPIO_CNTL                            0x720
+#define R600_LOW_VID_LOWER_GPIO_CNTL                               0x724
+
+
+
+#define R600_HDP_NONSURFACE_BASE                                0x2c04
+
+#define R600_BUS_CNTL                                           0x5420
+#define R600_CONFIG_CNTL                                        0x5424
+#define R600_CONFIG_MEMSIZE                                     0x5428
+#define R600_CONFIG_F0_BASE                                     0x542C
+#define R600_CONFIG_APER_SIZE                                   0x5430
+
+#define R600_ROM_CNTL                              0x1600
+#       define R600_SCK_OVERWRITE                  (1 << 1)
+#       define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
+#       define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK  (0xf << 28)
+
+#define R600_CG_SPLL_FUNC_CNTL                     0x600
+#       define R600_SPLL_BYPASS_EN                 (1 << 3)
+#define R600_CG_SPLL_STATUS                        0x60c
+#       define R600_SPLL_CHG_STATUS                (1 << 1)
+
+#define R600_BIOS_0_SCRATCH               0x1724
+#define R600_BIOS_1_SCRATCH               0x1728
+#define R600_BIOS_2_SCRATCH               0x172c
+#define R600_BIOS_3_SCRATCH               0x1730
+#define R600_BIOS_4_SCRATCH               0x1734
+#define R600_BIOS_5_SCRATCH               0x1738
+#define R600_BIOS_6_SCRATCH               0x173c
+#define R600_BIOS_7_SCRATCH               0x1740
+
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
new file mode 100644
index 000000000000..c3f24cc56009
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -0,0 +1,793 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __RADEON_H__
+#define __RADEON_H__
+
+#include "radeon_object.h"
+
+/* TODO: Here are things that needs to be done :
+ *      - surface allocator & initializer : (bit like scratch reg) should
+ *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
+ *        related to surface
+ *      - WB : write back stuff (do it bit like scratch reg things)
+ *      - Vblank : look at Jesse's rework and what we should do
+ *      - r600/r700: gart & cp
+ *      - cs : clean cs ioctl use bitmap & things like that.
+ *      - power management stuff
+ *      - Barrier in gart code
+ *      - Unmappabled vram ?
+ *      - TESTING, TESTING, TESTING
+ */
+
+#include <asm/atomic.h>
+#include <linux/wait.h>
+#include <linux/list.h>
+#include <linux/kref.h>
+
+#include "radeon_mode.h"
+#include "radeon_reg.h"
+
+
+/*
+ * Modules parameters.
+ */
+extern int radeon_no_wb;
+extern int radeon_modeset;
+extern int radeon_dynclks;
+extern int radeon_r4xx_atom;
+extern int radeon_agpmode;
+extern int radeon_vram_limit;
+extern int radeon_gart_size;
+extern int radeon_benchmarking;
+extern int radeon_connector_table;
+
+/*
+ * Copy from radeon_drv.h so we don't have to include both and have conflicting
+ * symbol;
+ */
+#define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
+#define RADEON_IB_POOL_SIZE             16
+#define RADEON_DEBUGFS_MAX_NUM_FILES    32
+#define RADEONFB_CONN_LIMIT             4
+
+enum radeon_family {
+        CHIP_R100,
+        CHIP_RV100,
+        CHIP_RS100,
+        CHIP_RV200,
+        CHIP_RS200,
+        CHIP_R200,
+        CHIP_RV250,
+        CHIP_RS300,
+        CHIP_RV280,
+        CHIP_R300,
+        CHIP_R350,
+        CHIP_RV350,
+        CHIP_RV380,
+        CHIP_R420,
+        CHIP_R423,
+        CHIP_RV410,
+        CHIP_RS400,
+        CHIP_RS480,
+        CHIP_RS600,
+        CHIP_RS690,
+        CHIP_RS740,
+        CHIP_RV515,
+        CHIP_R520,
+        CHIP_RV530,
+        CHIP_RV560,
+        CHIP_RV570,
+        CHIP_R580,
+        CHIP_R600,
+        CHIP_RV610,
+        CHIP_RV630,
+        CHIP_RV620,
+        CHIP_RV635,
+        CHIP_RV670,
+        CHIP_RS780,
+        CHIP_RV770,
+        CHIP_RV730,
+        CHIP_RV710,
+        CHIP_LAST,
+};
+
+enum radeon_chip_flags {
+        RADEON_FAMILY_MASK = 0x0000ffffUL,
+        RADEON_FLAGS_MASK = 0xffff0000UL,
+        RADEON_IS_MOBILITY = 0x00010000UL,
+        RADEON_IS_IGP = 0x00020000UL,
+        RADEON_SINGLE_CRTC = 0x00040000UL,
+        RADEON_IS_AGP = 0x00080000UL,
+        RADEON_HAS_HIERZ = 0x00100000UL,
+        RADEON_IS_PCIE = 0x00200000UL,
+        RADEON_NEW_MEMMAP = 0x00400000UL,
+        RADEON_IS_PCI = 0x00800000UL,
+        RADEON_IS_IGPGART = 0x01000000UL,
+};
+
+
+/*
+ * Errata workarounds.
+ */
+enum radeon_pll_errata {
+        CHIP_ERRATA_R300_CG             = 0x00000001,
+        CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
+        CHIP_ERRATA_PLL_DELAY           = 0x00000004
+};
+
+
+struct radeon_device;
+
+
+/*
+ * BIOS.
+ */
+bool radeon_get_bios(struct radeon_device *rdev);
+
+/*
+ * Clocks
+ */
+
+struct radeon_clock {
+        struct radeon_pll p1pll;
+        struct radeon_pll p2pll;
+        struct radeon_pll spll;
+        struct radeon_pll mpll;
+        /* 10 Khz units */
+        uint32_t default_mclk;
+        uint32_t default_sclk;
+};
+
+/*
+ * Fences.
+ */
+struct radeon_fence_driver {
+        uint32_t                        scratch_reg;
+        atomic_t                        seq;
+        uint32_t                        last_seq;
+        unsigned long                   count_timeout;
+        wait_queue_head_t               queue;
+        rwlock_t                        lock;
+        struct list_head                created;
+        struct list_head                emited;
+        struct list_head                signaled;
+};
+
+struct radeon_fence {
+        struct radeon_device            *rdev;
+        struct kref                     kref;
+        struct list_head                list;
+        /* protected by radeon_fence.lock */
+        uint32_t                        seq;
+        unsigned long                   timeout;
+        bool                            emited;
+        bool                            signaled;
+};
+
+int radeon_fence_driver_init(struct radeon_device *rdev);
+void radeon_fence_driver_fini(struct radeon_device *rdev);
+int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
+int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
+void radeon_fence_process(struct radeon_device *rdev);
+bool radeon_fence_signaled(struct radeon_fence *fence);
+int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
+int radeon_fence_wait_next(struct radeon_device *rdev);
+int radeon_fence_wait_last(struct radeon_device *rdev);
+struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
+void radeon_fence_unref(struct radeon_fence **fence);
+
+
+/*
+ * Radeon buffer.
+ */
+struct radeon_object;
+
+struct radeon_object_list {
+        struct list_head        list;
+        struct radeon_object    *robj;
+        uint64_t                gpu_offset;
+        unsigned                rdomain;
+        unsigned                wdomain;
+};
+
+int radeon_object_init(struct radeon_device *rdev);
+void radeon_object_fini(struct radeon_device *rdev);
+int radeon_object_create(struct radeon_device *rdev,
+                         struct drm_gem_object *gobj,
+                         unsigned long size,
+                         bool kernel,
+                         uint32_t domain,
+                         bool interruptible,
+                         struct radeon_object **robj_ptr);
+int radeon_object_kmap(struct radeon_object *robj, void **ptr);
+void radeon_object_kunmap(struct radeon_object *robj);
+void radeon_object_unref(struct radeon_object **robj);
+int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
+                      uint64_t *gpu_addr);
+void radeon_object_unpin(struct radeon_object *robj);
+int radeon_object_wait(struct radeon_object *robj);
+int radeon_object_evict_vram(struct radeon_device *rdev);
+int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
+void radeon_object_force_delete(struct radeon_device *rdev);
+void radeon_object_list_add_object(struct radeon_object_list *lobj,
+                                   struct list_head *head);
+int radeon_object_list_validate(struct list_head *head, void *fence);
+void radeon_object_list_unvalidate(struct list_head *head);
+void radeon_object_list_clean(struct list_head *head);
+int radeon_object_fbdev_mmap(struct radeon_object *robj,
+                             struct vm_area_struct *vma);
+unsigned long radeon_object_size(struct radeon_object *robj);
+
+
+/*
+ * GEM objects.
+ */
+struct radeon_gem {
+        struct list_head        objects;
+};
+
+int radeon_gem_init(struct radeon_device *rdev);
+void radeon_gem_fini(struct radeon_device *rdev);
+int radeon_gem_object_create(struct radeon_device *rdev, int size,
+                             int alignment, int initial_domain,
+                             bool discardable, bool kernel,
+                             bool interruptible,
+                             struct drm_gem_object **obj);
+int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
+                          uint64_t *gpu_addr);
+void radeon_gem_object_unpin(struct drm_gem_object *obj);
+
+
+/*
+ * GART structures, functions & helpers
+ */
+struct radeon_mc;
+
+struct radeon_gart_table_ram {
+        volatile uint32_t               *ptr;
+};
+
+struct radeon_gart_table_vram {
+        struct radeon_object            *robj;
+        volatile uint32_t               *ptr;
+};
+
+union radeon_gart_table {
+        struct radeon_gart_table_ram    ram;
+        struct radeon_gart_table_vram   vram;
+};
+
+struct radeon_gart {
+        dma_addr_t                      table_addr;
+        unsigned                        num_gpu_pages;
+        unsigned                        num_cpu_pages;
+        unsigned                        table_size;
+        union radeon_gart_table         table;
+        struct page                     **pages;
+        dma_addr_t                      *pages_addr;
+        bool                            ready;
+};
+
+int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
+void radeon_gart_table_ram_free(struct radeon_device *rdev);
+int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
+void radeon_gart_table_vram_free(struct radeon_device *rdev);
+int radeon_gart_init(struct radeon_device *rdev);
+void radeon_gart_fini(struct radeon_device *rdev);
+void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
+                        int pages);
+int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
+                     int pages, struct page **pagelist);
+
+
+/*
+ * GPU MC structures, functions & helpers
+ */
+struct radeon_mc {
+        resource_size_t         aper_size;
+        resource_size_t         aper_base;
+        resource_size_t         agp_base;
+        unsigned                gtt_location;
+        unsigned                gtt_size;
+        unsigned                vram_location;
+        unsigned                vram_size;
+        unsigned                vram_width;
+        int                     vram_mtrr;
+        bool                    vram_is_ddr;
+};
+
+int radeon_mc_setup(struct radeon_device *rdev);
+
+
+/*
+ * GPU scratch registers structures, functions & helpers
+ */
+struct radeon_scratch {
+        unsigned                num_reg;
+        bool                    free[32];
+        uint32_t                reg[32];
+};
+
+int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
+void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
+
+
+/*
+ * IRQS.
+ */
+struct radeon_irq {
+        bool            installed;
+        bool            sw_int;
+        /* FIXME: use a define max crtc rather than hardcode it */
+        bool            crtc_vblank_int[2];
+};
+
+int radeon_irq_kms_init(struct radeon_device *rdev);
+void radeon_irq_kms_fini(struct radeon_device *rdev);
+
+
+/*
+ * CP & ring.
+ */
+struct radeon_ib {
+        struct list_head        list;
+        unsigned long           idx;
+        uint64_t                gpu_addr;
+        struct radeon_fence     *fence;
+        volatile uint32_t       *ptr;
+        uint32_t                length_dw;
+};
+
+struct radeon_ib_pool {
+        struct mutex            mutex;
+        struct radeon_object    *robj;
+        struct list_head        scheduled_ibs;
+        struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
+        bool                    ready;
+        DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
+};
+
+struct radeon_cp {
+        struct radeon_object    *ring_obj;
+        volatile uint32_t       *ring;
+        unsigned                rptr;
+        unsigned                wptr;
+        unsigned                wptr_old;
+        unsigned                ring_size;
+        unsigned                ring_free_dw;
+        int                     count_dw;
+        uint64_t                gpu_addr;
+        uint32_t                align_mask;
+        uint32_t                ptr_mask;
+        struct mutex            mutex;
+        bool                    ready;
+};
+
+int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
+void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
+int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
+int radeon_ib_pool_init(struct radeon_device *rdev);
+void radeon_ib_pool_fini(struct radeon_device *rdev);
+int radeon_ib_test(struct radeon_device *rdev);
+/* Ring access between begin & end cannot sleep */
+void radeon_ring_free_size(struct radeon_device *rdev);
+int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
+void radeon_ring_unlock_commit(struct radeon_device *rdev);
+void radeon_ring_unlock_undo(struct radeon_device *rdev);
+int radeon_ring_test(struct radeon_device *rdev);
+int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
+void radeon_ring_fini(struct radeon_device *rdev);
+
+
+/*
+ * CS.
+ */
+struct radeon_cs_reloc {
+        struct drm_gem_object           *gobj;
+        struct radeon_object            *robj;
+        struct radeon_object_list       lobj;
+        uint32_t                        handle;
+        uint32_t                        flags;
+};
+
+struct radeon_cs_chunk {
+        uint32_t                chunk_id;
+        uint32_t                length_dw;
+        uint32_t                *kdata;
+};
+
+struct radeon_cs_parser {
+        struct radeon_device    *rdev;
+        struct drm_file         *filp;
+        /* chunks */
+        unsigned                nchunks;
+        struct radeon_cs_chunk  *chunks;
+        uint64_t                *chunks_array;
+        /* IB */
+        unsigned                idx;
+        /* relocations */
+        unsigned                nrelocs;
+        struct radeon_cs_reloc  *relocs;
+        struct radeon_cs_reloc  **relocs_ptr;
+        struct list_head        validated;
+        /* indices of various chunks */
+        int                     chunk_ib_idx;
+        int                     chunk_relocs_idx;
+        struct radeon_ib        *ib;
+        void                    *track;
+};
+
+struct radeon_cs_packet {
+        unsigned        idx;
+        unsigned        type;
+        unsigned        reg;
+        unsigned        opcode;
+        int             count;
+        unsigned        one_reg_wr;
+};
+
+typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
+                                      struct radeon_cs_packet *pkt,
+                                      unsigned idx, unsigned reg);
+typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
+                                      struct radeon_cs_packet *pkt);
+
+
+/*
+ * AGP
+ */
+int radeon_agp_init(struct radeon_device *rdev);
+void radeon_agp_fini(struct radeon_device *rdev);
+
+
+/*
+ * Writeback
+ */
+struct radeon_wb {
+        struct radeon_object    *wb_obj;
+        volatile uint32_t       *wb;
+        uint64_t                gpu_addr;
+};
+
+
+/*
+ * Benchmarking
+ */
+void radeon_benchmark(struct radeon_device *rdev);
+
+
+/*
+ * Debugfs
+ */
+int radeon_debugfs_add_files(struct radeon_device *rdev,
+                             struct drm_info_list *files,
+                             unsigned nfiles);
+int radeon_debugfs_fence_init(struct radeon_device *rdev);
+int r100_debugfs_rbbm_init(struct radeon_device *rdev);
+int r100_debugfs_cp_init(struct radeon_device *rdev);
+
+
+/*
+ * ASIC specific functions.
+ */
+struct radeon_asic {
+        void (*errata)(struct radeon_device *rdev);
+        void (*vram_info)(struct radeon_device *rdev);
+        int (*gpu_reset)(struct radeon_device *rdev);
+        int (*mc_init)(struct radeon_device *rdev);
+        void (*mc_fini)(struct radeon_device *rdev);
+        int (*wb_init)(struct radeon_device *rdev);
+        void (*wb_fini)(struct radeon_device *rdev);
+        int (*gart_enable)(struct radeon_device *rdev);
+        void (*gart_disable)(struct radeon_device *rdev);
+        void (*gart_tlb_flush)(struct radeon_device *rdev);
+        int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
+        int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
+        void (*cp_fini)(struct radeon_device *rdev);
+        void (*cp_disable)(struct radeon_device *rdev);
+        void (*ring_start)(struct radeon_device *rdev);
+        int (*irq_set)(struct radeon_device *rdev);
+        int (*irq_process)(struct radeon_device *rdev);
+        void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
+        int (*cs_parse)(struct radeon_cs_parser *p);
+        int (*copy_blit)(struct radeon_device *rdev,
+                         uint64_t src_offset,
+                         uint64_t dst_offset,
+                         unsigned num_pages,
+                         struct radeon_fence *fence);
+        int (*copy_dma)(struct radeon_device *rdev,
+                        uint64_t src_offset,
+                        uint64_t dst_offset,
+                        unsigned num_pages,
+                        struct radeon_fence *fence);
+        int (*copy)(struct radeon_device *rdev,
+                    uint64_t src_offset,
+                    uint64_t dst_offset,
+                    unsigned num_pages,
+                    struct radeon_fence *fence);
+        void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
+        void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
+        void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
+        void (*set_clock_gating)(struct radeon_device *rdev, int enable);
+};
+
+
+/*
+ * IOCTL.
+ */
+int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
+                          struct drm_file *filp);
+int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
+                            struct drm_file *filp);
+int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
+                         struct drm_file *file_priv);
+int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
+                           struct drm_file *file_priv);
+int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
+                            struct drm_file *file_priv);
+int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
+                           struct drm_file *file_priv);
+int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
+                                struct drm_file *filp);
+int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
+                          struct drm_file *filp);
+int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
+                          struct drm_file *filp);
+int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
+                              struct drm_file *filp);
+int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+
+
+/*
+ * Core structure, functions and helpers.
+ */
+typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
+typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
+
+struct radeon_device {
+        struct drm_device               *ddev;
+        struct pci_dev                  *pdev;
+        /* ASIC */
+        enum radeon_family              family;
+        unsigned long                   flags;
+        int                             usec_timeout;
+        enum radeon_pll_errata          pll_errata;
+        int                             num_gb_pipes;
+        int                             disp_priority;
+        /* BIOS */
+        uint8_t                         *bios;
+        bool                            is_atom_bios;
+        uint16_t                        bios_header_start;
+        struct radeon_object            *stollen_vga_memory;
+        struct fb_info                  *fbdev_info;
+        struct radeon_object            *fbdev_robj;
+        struct radeon_framebuffer       *fbdev_rfb;
+        /* Register mmio */
+        unsigned long                   rmmio_base;
+        unsigned long                   rmmio_size;
+        void                            *rmmio;
+        radeon_rreg_t                   mm_rreg;
+        radeon_wreg_t                   mm_wreg;
+        radeon_rreg_t                   mc_rreg;
+        radeon_wreg_t                   mc_wreg;
+        radeon_rreg_t                   pll_rreg;
+        radeon_wreg_t                   pll_wreg;
+        radeon_rreg_t                   pcie_rreg;
+        radeon_wreg_t                   pcie_wreg;
+        radeon_rreg_t                   pciep_rreg;
+        radeon_wreg_t                   pciep_wreg;
+        struct radeon_clock             clock;
+        struct radeon_mc                mc;
+        struct radeon_gart              gart;
+        struct radeon_mode_info         mode_info;
+        struct radeon_scratch           scratch;
+        struct radeon_mman              mman;
+        struct radeon_fence_driver      fence_drv;
+        struct radeon_cp                cp;
+        struct radeon_ib_pool           ib_pool;
+        struct radeon_irq               irq;
+        struct radeon_asic              *asic;
+        struct radeon_gem               gem;
+        struct mutex                    cs_mutex;
+        struct radeon_wb                wb;
+        bool                            gpu_lockup;
+        bool                            shutdown;
+        bool                            suspend;
+};
+
+int radeon_device_init(struct radeon_device *rdev,
+                       struct drm_device *ddev,
+                       struct pci_dev *pdev,
+                       uint32_t flags);
+void radeon_device_fini(struct radeon_device *rdev);
+int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
+
+
+/*
+ * Registers read & write functions.
+ */
+#define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
+#define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
+#define RREG32(reg) rdev->mm_rreg(rdev, (reg))
+#define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v))
+#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
+#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
+#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
+#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
+#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
+#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
+#define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg))
+#define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v))
+#define WREG32_P(reg, val, mask)                                \
+        do {                                                    \
+                uint32_t tmp_ = RREG32(reg);                    \
+                tmp_ &= (mask);                                 \
+                tmp_ |= ((val) & ~(mask));                      \
+                WREG32(reg, tmp_);                              \
+        } while (0)
+#define WREG32_PLL_P(reg, val, mask)                            \
+        do {                                                    \
+                uint32_t tmp_ = RREG32_PLL(reg);                \
+                tmp_ &= (mask);                                 \
+                tmp_ |= ((val) & ~(mask));                      \
+                WREG32_PLL(reg, tmp_);                          \
+        } while (0)
+
+void r100_pll_errata_after_index(struct radeon_device *rdev);
+
+
+/*
+ * ASICs helpers.
+ */
+#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
+                (rdev->family == CHIP_RV200) || \
+                (rdev->family == CHIP_RS100) || \
+                (rdev->family == CHIP_RS200) || \
+                (rdev->family == CHIP_RV250) || \
+                (rdev->family == CHIP_RV280) || \
+                (rdev->family == CHIP_RS300))
+#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
+                (rdev->family == CHIP_RV350) ||                 \
+                (rdev->family == CHIP_R350)  ||                 \
+                (rdev->family == CHIP_RV380) ||                 \
+                (rdev->family == CHIP_R420)  ||                 \
+                (rdev->family == CHIP_R423)  ||                 \
+                (rdev->family == CHIP_RV410) ||                 \
+                (rdev->family == CHIP_RS400) ||                 \
+                (rdev->family == CHIP_RS480))
+#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
+#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
+#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
+
+
+/*
+ * BIOS helpers.
+ */
+#define RBIOS8(i) (rdev->bios[i])
+#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
+#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
+
+int radeon_combios_init(struct radeon_device *rdev);
+void radeon_combios_fini(struct radeon_device *rdev);
+int radeon_atombios_init(struct radeon_device *rdev);
+void radeon_atombios_fini(struct radeon_device *rdev);
+
+
+/*
+ * RING helpers.
+ */
+#define CP_PACKET0                      0x00000000
+#define         PACKET0_BASE_INDEX_SHIFT        0
+#define         PACKET0_BASE_INDEX_MASK         (0x1ffff << 0)
+#define         PACKET0_COUNT_SHIFT             16
+#define         PACKET0_COUNT_MASK              (0x3fff << 16)
+#define CP_PACKET1                      0x40000000
+#define CP_PACKET2                      0x80000000
+#define         PACKET2_PAD_SHIFT               0
+#define         PACKET2_PAD_MASK                (0x3fffffff << 0)
+#define CP_PACKET3                      0xC0000000
+#define         PACKET3_IT_OPCODE_SHIFT         8
+#define         PACKET3_IT_OPCODE_MASK          (0xff << 8)
+#define         PACKET3_COUNT_SHIFT             16
+#define         PACKET3_COUNT_MASK              (0x3fff << 16)
+/* PACKET3 op code */
+#define         PACKET3_NOP                     0x10
+#define         PACKET3_3D_DRAW_VBUF            0x28
+#define         PACKET3_3D_DRAW_IMMD            0x29
+#define         PACKET3_3D_DRAW_INDX            0x2A
+#define         PACKET3_3D_LOAD_VBPNTR          0x2F
+#define         PACKET3_INDX_BUFFER             0x33
+#define         PACKET3_3D_DRAW_VBUF_2          0x34
+#define         PACKET3_3D_DRAW_IMMD_2          0x35
+#define         PACKET3_3D_DRAW_INDX_2          0x36
+#define         PACKET3_BITBLT_MULTI            0x9B
+
+#define PACKET0(reg, n) (CP_PACKET0 |                                   \
+                         REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |      \
+                         REG_SET(PACKET0_COUNT, (n)))
+#define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
+#define PACKET3(op, n)  (CP_PACKET3 |                                   \
+                         REG_SET(PACKET3_IT_OPCODE, (op)) |             \
+                         REG_SET(PACKET3_COUNT, (n)))
+
+#define PACKET_TYPE0    0
+#define PACKET_TYPE1    1
+#define PACKET_TYPE2    2
+#define PACKET_TYPE3    3
+
+#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
+#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
+#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
+#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
+#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
+
+static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
+{
+#if DRM_DEBUG_CODE
+        if (rdev->cp.count_dw <= 0) {
+                DRM_ERROR("radeon: writting more dword to ring than expected !\n");
+        }
+#endif
+        rdev->cp.ring[rdev->cp.wptr++] = v;
+        rdev->cp.wptr &= rdev->cp.ptr_mask;
+        rdev->cp.count_dw--;
+        rdev->cp.ring_free_dw--;
+}
+
+
+/*
+ * ASICs macro.
+ */
+#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
+#define radeon_errata(rdev) (rdev)->asic->errata((rdev))
+#define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
+#define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
+#define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
+#define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
+#define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
+#define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
+#define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
+#define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
+#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
+#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
+#define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
+#define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
+#define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
+#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
+#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
+#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
+#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
+#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
+#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
+#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
+#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
+#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
+#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
+#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
new file mode 100644
index 000000000000..23ea9955ac59
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Dave Airlie
+ *    Jerome Glisse <glisse@freedesktop.org>
+ */
+#include "drmP.h"
+#include "drm.h"
+#include "radeon.h"
+#include "radeon_drm.h"
+
+#if __OS_HAS_AGP
+
+struct radeon_agpmode_quirk {
+        u32 hostbridge_vendor;
+        u32 hostbridge_device;
+        u32 chip_vendor;
+        u32 chip_device;
+        u32 subsys_vendor;
+        u32 subsys_device;
+        u32 default_mode;
+};
+
+static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = {
+        /* Intel E7505 Memory Controller Hub / RV350 AR [Radeon 9600XT] Needs AGPMode 4 (deb #515326) */
+        { PCI_VENDOR_ID_INTEL, 0x2550, PCI_VENDOR_ID_ATI, 0x4152, 0x1458, 0x4038, 4},
+        /* Intel 82865G/PE/P DRAM Controller/Host-Hub / Mobility 9800 Needs AGPMode 4 (deb #462590) */
+        { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x4a4e, PCI_VENDOR_ID_DELL, 0x5106, 4},
+        /* Intel 82865G/PE/P DRAM Controller/Host-Hub / RV280 [Radeon 9200 SE] Needs AGPMode 4 (lp #300304) */
+        { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x5964,
+                0x148c, 0x2073, 4},
+        /* Intel 82855PM Processor to I/O Controller / Mobility M6 LY Needs AGPMode 1 (deb #467235) */
+        { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c59,
+                PCI_VENDOR_ID_IBM, 0x052f, 1},
+        /* Intel 82855PM host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #195051) */
+        { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e50,
+                PCI_VENDOR_ID_IBM, 0x0550, 1},
+        /* Intel 82855PM host bridge / Mobility M7 needs AGPMode 1 */
+        { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c57,
+                PCI_VENDOR_ID_IBM, 0x0530, 1},
+        /* Intel 82855PM host bridge / FireGL Mobility T2 RV350 Needs AGPMode 2 (fdo #20647) */
+        { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e54,
+                PCI_VENDOR_ID_IBM, 0x054f, 2},
+        /* Intel 82855PM host bridge / Mobility M9+ / VaioPCG-V505DX Needs AGPMode 2 (fdo #17928) */
+        { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61,
+                PCI_VENDOR_ID_SONY, 0x816b, 2},
+        /* Intel 82855PM Processor to I/O Controller / Mobility M9+ Needs AGPMode 8 (phoronix forum) */
+        { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61,
+                PCI_VENDOR_ID_SONY, 0x8195, 8},
+        /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/
+        { PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59,
+                PCI_VENDOR_ID_DELL, 0x00e3, 2},
+        /* Intel 82852/82855 host bridge / Mobility FireGL 9000 R250 Needs AGPMode 1 (lp #296617) */
+        { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66,
+                PCI_VENDOR_ID_DELL, 0x0149, 1},
+        /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */
+        { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
+                0x1025, 0x0061, 1},
+        /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #203007) */
+        { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
+                0x1025, 0x0064, 1},
+        /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #141551) */
+        { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
+                PCI_VENDOR_ID_ASUSTEK, 0x1942, 1},
+        /* Intel 82852/82855 host bridge / Mobility 9600/9700 Needs AGPMode 1 (deb #510208) */
+        { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
+                0x10cf, 0x127f, 1},
+        /* ASRock K7VT4A+ AGP 8x / ATI Radeon 9250 AGP Needs AGPMode 4 (lp #133192) */
+        { 0x1849, 0x3189, PCI_VENDOR_ID_ATI, 0x5960,
+                0x1787, 0x5960, 4},
+        /* VIA K8M800 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (fdo #12544) */
+        { PCI_VENDOR_ID_VIA, 0x0204, PCI_VENDOR_ID_ATI, 0x5960,
+                0x17af, 0x2020, 4},
+        /* VIA KT880 Host Bridge / RV350 [Radeon 9550] Needs AGPMode 4 (fdo #19981) */
+        { PCI_VENDOR_ID_VIA, 0x0269, PCI_VENDOR_ID_ATI, 0x4153,
+                PCI_VENDOR_ID_ASUSTEK, 0x003c, 4},
+        /* VIA VT8363 Host Bridge / R200 QL [Radeon 8500] Needs AGPMode 2 (lp #141551) */
+        { PCI_VENDOR_ID_VIA, 0x0305, PCI_VENDOR_ID_ATI, 0x514c,
+                PCI_VENDOR_ID_ATI, 0x013a, 2},
+        /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 (deb #515512) */
+        { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960,
+                PCI_VENDOR_ID_ASUSTEK, 0x004c, 2},
+        /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 */
+        { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960,
+                PCI_VENDOR_ID_ASUSTEK, 0x0054, 2},
+        /* VIA VT8377 Host Bridge / R200 QM [Radeon 9100] Needs AGPMode 4 (deb #461144) */
+        { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x514d,
+                0x174b, 0x7149, 4},
+        /* VIA VT8377 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (lp #312693) */
+        { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5960,
+                0x1462, 0x0380, 4},
+        /* VIA VT8377 Host Bridge / RV280 Needs AGPMode 4 (ati ML) */
+        { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5964,
+                0x148c, 0x2073, 4},
+        /* ATI Host Bridge / RV280 [M9+] Needs AGPMode 1 (phoronix forum) */
+        { PCI_VENDOR_ID_ATI, 0xcbb2, PCI_VENDOR_ID_ATI, 0x5c61,
+                PCI_VENDOR_ID_SONY, 0x8175, 1},
+        /* HP Host Bridge / R300 [FireGL X1] Needs AGPMode 2 (fdo #7770) */
+        { PCI_VENDOR_ID_HP, 0x122e, PCI_VENDOR_ID_ATI, 0x4e47,
+                PCI_VENDOR_ID_ATI, 0x0152, 2},
+        { 0, 0, 0, 0, 0, 0, 0 },
+};
+#endif
+
+int radeon_agp_init(struct radeon_device *rdev)
+{
+#if __OS_HAS_AGP
+        struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list;
+        struct drm_agp_mode mode;
+        struct drm_agp_info info;
+        uint32_t agp_status;
+        int default_mode;
+        bool is_v3;
+        int ret;
+
+        /* Acquire AGP. */
+        if (!rdev->ddev->agp->acquired) {
+                ret = drm_agp_acquire(rdev->ddev);
+                if (ret) {
+                        DRM_ERROR("Unable to acquire AGP: %d\n", ret);
+                        return ret;
+                }
+        }
+
+        ret = drm_agp_info(rdev->ddev, &info);
+        if (ret) {
+                DRM_ERROR("Unable to get AGP info: %d\n", ret);
+                return ret;
+        }
+        mode.mode = info.mode;
+        agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
+        is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
+
+        if (is_v3) {
+                default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
+        } else {
+                if (agp_status & RADEON_AGP_4X_MODE) {
+                        default_mode = 4;
+                } else if (agp_status & RADEON_AGP_2X_MODE) {
+                        default_mode = 2;
+                } else {
+                        default_mode = 1;
+                }
+        }
+
+        /* Apply AGPMode Quirks */
+        while (p && p->chip_device != 0) {
+                if (info.id_vendor == p->hostbridge_vendor &&
+                    info.id_device == p->hostbridge_device &&
+                    rdev->pdev->vendor == p->chip_vendor &&
+                    rdev->pdev->device == p->chip_device &&
+                    rdev->pdev->subsystem_vendor == p->subsys_vendor &&
+                    rdev->pdev->subsystem_device == p->subsys_device) {
+                        default_mode = p->default_mode;
+                }
+                ++p;
+        }
+
+        if (radeon_agpmode > 0) {
+                if ((radeon_agpmode < (is_v3 ? 4 : 1)) ||
+                    (radeon_agpmode > (is_v3 ? 8 : 4)) ||
+                    (radeon_agpmode & (radeon_agpmode - 1))) {
+                        DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n",
+                                  radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4",
+                                  default_mode);
+                        radeon_agpmode = default_mode;
+                } else {
+                        DRM_INFO("AGP mode requested: %d\n", radeon_agpmode);
+                }
+        } else {
+                radeon_agpmode = default_mode;
+        }
+
+        mode.mode &= ~RADEON_AGP_MODE_MASK;
+        if (is_v3) {
+                switch (radeon_agpmode) {
+                case 8:
+                        mode.mode |= RADEON_AGPv3_8X_MODE;
+                        break;
+                case 4:
+                default:
+                        mode.mode |= RADEON_AGPv3_4X_MODE;
+                        break;
+                }
+        } else {
+                switch (radeon_agpmode) {
+                case 4:
+                        mode.mode |= RADEON_AGP_4X_MODE;
+                        break;
+                case 2:
+                        mode.mode |= RADEON_AGP_2X_MODE;
+                        break;
+                case 1:
+                default:
+                        mode.mode |= RADEON_AGP_1X_MODE;
+                        break;
+                }
+        }
+
+        mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */
+        ret = drm_agp_enable(rdev->ddev, mode);
+        if (ret) {
+                DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
+                return ret;
+        }
+
+        rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base;
+        rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20;
+
+        /* workaround some hw issues */
+        if (rdev->family < CHIP_R200) {
+                WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000);
+        }
+        return 0;
+#else
+        return 0;
+#endif
+}
+
+void radeon_agp_fini(struct radeon_device *rdev)
+{
+#if __OS_HAS_AGP
+        if (rdev->flags & RADEON_IS_AGP) {
+                if (rdev->ddev->agp && rdev->ddev->agp->acquired) {
+                        drm_agp_release(rdev->ddev);
+                }
+        }
+#endif
+}
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
new file mode 100644
index 000000000000..e57d8a784e9f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -0,0 +1,405 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __RADEON_ASIC_H__
+#define __RADEON_ASIC_H__
+
+/*
+ * common functions
+ */
+void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
+void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
+
+void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
+void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
+void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
+
+/*
+ * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
+ */
+uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
+void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+void r100_errata(struct radeon_device *rdev);
+void r100_vram_info(struct radeon_device *rdev);
+int r100_gpu_reset(struct radeon_device *rdev);
+int r100_mc_init(struct radeon_device *rdev);
+void r100_mc_fini(struct radeon_device *rdev);
+int r100_wb_init(struct radeon_device *rdev);
+void r100_wb_fini(struct radeon_device *rdev);
+int r100_gart_enable(struct radeon_device *rdev);
+void r100_pci_gart_disable(struct radeon_device *rdev);
+void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
+int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
+int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
+void r100_cp_fini(struct radeon_device *rdev);
+void r100_cp_disable(struct radeon_device *rdev);
+void r100_ring_start(struct radeon_device *rdev);
+int r100_irq_set(struct radeon_device *rdev);
+int r100_irq_process(struct radeon_device *rdev);
+void r100_fence_ring_emit(struct radeon_device *rdev,
+                          struct radeon_fence *fence);
+int r100_cs_parse(struct radeon_cs_parser *p);
+void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
+int r100_copy_blit(struct radeon_device *rdev,
+                   uint64_t src_offset,
+                   uint64_t dst_offset,
+                   unsigned num_pages,
+                   struct radeon_fence *fence);
+
+static struct radeon_asic r100_asic = {
+        .errata = &r100_errata,
+        .vram_info = &r100_vram_info,
+        .gpu_reset = &r100_gpu_reset,
+        .mc_init = &r100_mc_init,
+        .mc_fini = &r100_mc_fini,
+        .wb_init = &r100_wb_init,
+        .wb_fini = &r100_wb_fini,
+        .gart_enable = &r100_gart_enable,
+        .gart_disable = &r100_pci_gart_disable,
+        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
+        .gart_set_page = &r100_pci_gart_set_page,
+        .cp_init = &r100_cp_init,
+        .cp_fini = &r100_cp_fini,
+        .cp_disable = &r100_cp_disable,
+        .ring_start = &r100_ring_start,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .fence_ring_emit = &r100_fence_ring_emit,
+        .cs_parse = &r100_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = NULL,
+        .copy = &r100_copy_blit,
+        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .set_memory_clock = NULL,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = &radeon_legacy_set_clock_gating,
+};
+
+
+/*
+ * r300,r350,rv350,rv380
+ */
+void r300_errata(struct radeon_device *rdev);
+void r300_vram_info(struct radeon_device *rdev);
+int r300_gpu_reset(struct radeon_device *rdev);
+int r300_mc_init(struct radeon_device *rdev);
+void r300_mc_fini(struct radeon_device *rdev);
+void r300_ring_start(struct radeon_device *rdev);
+void r300_fence_ring_emit(struct radeon_device *rdev,
+                          struct radeon_fence *fence);
+int r300_cs_parse(struct radeon_cs_parser *p);
+int r300_gart_enable(struct radeon_device *rdev);
+void rv370_pcie_gart_disable(struct radeon_device *rdev);
+void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
+int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
+uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
+void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
+int r300_copy_dma(struct radeon_device *rdev,
+                  uint64_t src_offset,
+                  uint64_t dst_offset,
+                  unsigned num_pages,
+                  struct radeon_fence *fence);
+static struct radeon_asic r300_asic = {
+        .errata = &r300_errata,
+        .vram_info = &r300_vram_info,
+        .gpu_reset = &r300_gpu_reset,
+        .mc_init = &r300_mc_init,
+        .mc_fini = &r300_mc_fini,
+        .wb_init = &r100_wb_init,
+        .wb_fini = &r100_wb_fini,
+        .gart_enable = &r300_gart_enable,
+        .gart_disable = &r100_pci_gart_disable,
+        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
+        .gart_set_page = &r100_pci_gart_set_page,
+        .cp_init = &r100_cp_init,
+        .cp_fini = &r100_cp_fini,
+        .cp_disable = &r100_cp_disable,
+        .ring_start = &r300_ring_start,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r300_copy_dma,
+        .copy = &r100_copy_blit,
+        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .set_memory_clock = NULL,
+        .set_pcie_lanes = &rv370_set_pcie_lanes,
+        .set_clock_gating = &radeon_legacy_set_clock_gating,
+};
+
+/*
+ * r420,r423,rv410
+ */
+void r420_errata(struct radeon_device *rdev);
+void r420_vram_info(struct radeon_device *rdev);
+int r420_mc_init(struct radeon_device *rdev);
+void r420_mc_fini(struct radeon_device *rdev);
+static struct radeon_asic r420_asic = {
+        .errata = &r420_errata,
+        .vram_info = &r420_vram_info,
+        .gpu_reset = &r300_gpu_reset,
+        .mc_init = &r420_mc_init,
+        .mc_fini = &r420_mc_fini,
+        .wb_init = &r100_wb_init,
+        .wb_fini = &r100_wb_fini,
+        .gart_enable = &r300_gart_enable,
+        .gart_disable = &rv370_pcie_gart_disable,
+        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
+        .gart_set_page = &rv370_pcie_gart_set_page,
+        .cp_init = &r100_cp_init,
+        .cp_fini = &r100_cp_fini,
+        .cp_disable = &r100_cp_disable,
+        .ring_start = &r300_ring_start,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r300_copy_dma,
+        .copy = &r100_copy_blit,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .set_pcie_lanes = &rv370_set_pcie_lanes,
+        .set_clock_gating = &radeon_atom_set_clock_gating,
+};
+
+
+/*
+ * rs400,rs480
+ */
+void rs400_errata(struct radeon_device *rdev);
+void rs400_vram_info(struct radeon_device *rdev);
+int rs400_mc_init(struct radeon_device *rdev);
+void rs400_mc_fini(struct radeon_device *rdev);
+int rs400_gart_enable(struct radeon_device *rdev);
+void rs400_gart_disable(struct radeon_device *rdev);
+void rs400_gart_tlb_flush(struct radeon_device *rdev);
+int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
+uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
+void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+static struct radeon_asic rs400_asic = {
+        .errata = &rs400_errata,
+        .vram_info = &rs400_vram_info,
+        .gpu_reset = &r300_gpu_reset,
+        .mc_init = &rs400_mc_init,
+        .mc_fini = &rs400_mc_fini,
+        .wb_init = &r100_wb_init,
+        .wb_fini = &r100_wb_fini,
+        .gart_enable = &rs400_gart_enable,
+        .gart_disable = &rs400_gart_disable,
+        .gart_tlb_flush = &rs400_gart_tlb_flush,
+        .gart_set_page = &rs400_gart_set_page,
+        .cp_init = &r100_cp_init,
+        .cp_fini = &r100_cp_fini,
+        .cp_disable = &r100_cp_disable,
+        .ring_start = &r300_ring_start,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r300_copy_dma,
+        .copy = &r100_copy_blit,
+        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .set_memory_clock = NULL,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = &radeon_legacy_set_clock_gating,
+};
+
+
+/*
+ * rs600.
+ */
+void rs600_errata(struct radeon_device *rdev);
+void rs600_vram_info(struct radeon_device *rdev);
+int rs600_mc_init(struct radeon_device *rdev);
+void rs600_mc_fini(struct radeon_device *rdev);
+int rs600_irq_set(struct radeon_device *rdev);
+int rs600_gart_enable(struct radeon_device *rdev);
+void rs600_gart_disable(struct radeon_device *rdev);
+void rs600_gart_tlb_flush(struct radeon_device *rdev);
+int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
+uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
+void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+static struct radeon_asic rs600_asic = {
+        .errata = &rs600_errata,
+        .vram_info = &rs600_vram_info,
+        .gpu_reset = &r300_gpu_reset,
+        .mc_init = &rs600_mc_init,
+        .mc_fini = &rs600_mc_fini,
+        .wb_init = &r100_wb_init,
+        .wb_fini = &r100_wb_fini,
+        .gart_enable = &rs600_gart_enable,
+        .gart_disable = &rs600_gart_disable,
+        .gart_tlb_flush = &rs600_gart_tlb_flush,
+        .gart_set_page = &rs600_gart_set_page,
+        .cp_init = &r100_cp_init,
+        .cp_fini = &r100_cp_fini,
+        .cp_disable = &r100_cp_disable,
+        .ring_start = &r300_ring_start,
+        .irq_set = &rs600_irq_set,
+        .irq_process = &r100_irq_process,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r300_copy_dma,
+        .copy = &r100_copy_blit,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = &radeon_atom_set_clock_gating,
+};
+
+
+/*
+ * rs690,rs740
+ */
+void rs690_errata(struct radeon_device *rdev);
+void rs690_vram_info(struct radeon_device *rdev);
+int rs690_mc_init(struct radeon_device *rdev);
+void rs690_mc_fini(struct radeon_device *rdev);
+uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
+void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+static struct radeon_asic rs690_asic = {
+        .errata = &rs690_errata,
+        .vram_info = &rs690_vram_info,
+        .gpu_reset = &r300_gpu_reset,
+        .mc_init = &rs690_mc_init,
+        .mc_fini = &rs690_mc_fini,
+        .wb_init = &r100_wb_init,
+        .wb_fini = &r100_wb_fini,
+        .gart_enable = &rs400_gart_enable,
+        .gart_disable = &rs400_gart_disable,
+        .gart_tlb_flush = &rs400_gart_tlb_flush,
+        .gart_set_page = &rs400_gart_set_page,
+        .cp_init = &r100_cp_init,
+        .cp_fini = &r100_cp_fini,
+        .cp_disable = &r100_cp_disable,
+        .ring_start = &r300_ring_start,
+        .irq_set = &rs600_irq_set,
+        .irq_process = &r100_irq_process,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r300_copy_dma,
+        .copy = &r300_copy_dma,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = &radeon_atom_set_clock_gating,
+};
+
+
+/*
+ * rv515
+ */
+void rv515_errata(struct radeon_device *rdev);
+void rv515_vram_info(struct radeon_device *rdev);
+int rv515_gpu_reset(struct radeon_device *rdev);
+int rv515_mc_init(struct radeon_device *rdev);
+void rv515_mc_fini(struct radeon_device *rdev);
+uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
+void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+void rv515_ring_start(struct radeon_device *rdev);
+uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
+void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+static struct radeon_asic rv515_asic = {
+        .errata = &rv515_errata,
+        .vram_info = &rv515_vram_info,
+        .gpu_reset = &rv515_gpu_reset,
+        .mc_init = &rv515_mc_init,
+        .mc_fini = &rv515_mc_fini,
+        .wb_init = &r100_wb_init,
+        .wb_fini = &r100_wb_fini,
+        .gart_enable = &r300_gart_enable,
+        .gart_disable = &rv370_pcie_gart_disable,
+        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
+        .gart_set_page = &rv370_pcie_gart_set_page,
+        .cp_init = &r100_cp_init,
+        .cp_fini = &r100_cp_fini,
+        .cp_disable = &r100_cp_disable,
+        .ring_start = &rv515_ring_start,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r100_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r300_copy_dma,
+        .copy = &r100_copy_blit,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .set_pcie_lanes = &rv370_set_pcie_lanes,
+        .set_clock_gating = &radeon_atom_set_clock_gating,
+};
+
+
+/*
+ * r520,rv530,rv560,rv570,r580
+ */
+void r520_errata(struct radeon_device *rdev);
+void r520_vram_info(struct radeon_device *rdev);
+int r520_mc_init(struct radeon_device *rdev);
+void r520_mc_fini(struct radeon_device *rdev);
+static struct radeon_asic r520_asic = {
+        .errata = &r520_errata,
+        .vram_info = &r520_vram_info,
+        .gpu_reset = &rv515_gpu_reset,
+        .mc_init = &r520_mc_init,
+        .mc_fini = &r520_mc_fini,
+        .wb_init = &r100_wb_init,
+        .wb_fini = &r100_wb_fini,
+        .gart_enable = &r300_gart_enable,
+        .gart_disable = &rv370_pcie_gart_disable,
+        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
+        .gart_set_page = &rv370_pcie_gart_set_page,
+        .cp_init = &r100_cp_init,
+        .cp_fini = &r100_cp_fini,
+        .cp_disable = &r100_cp_disable,
+        .ring_start = &rv515_ring_start,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r100_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r300_copy_dma,
+        .copy = &r100_copy_blit,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .set_pcie_lanes = &rv370_set_pcie_lanes,
+        .set_clock_gating = &radeon_atom_set_clock_gating,
+};
+
+/*
+ * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710
+ */
+uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
+void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
new file mode 100644
index 000000000000..786632d3e378
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -0,0 +1,1298 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+
+#include "atom.h"
+#include "atom-bits.h"
+
+/* from radeon_encoder.c */
+extern uint32_t
+radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
+                      uint8_t dac);
+extern void radeon_link_encoder_connector(struct drm_device *dev);
+extern void
+radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
+                        uint32_t supported_device);
+
+/* from radeon_connector.c */
+extern void
+radeon_add_atom_connector(struct drm_device *dev,
+                          uint32_t connector_id,
+                          uint32_t supported_device,
+                          int connector_type,
+                          struct radeon_i2c_bus_rec *i2c_bus,
+                          bool linkb, uint32_t igp_lane_info);
+
+/* from radeon_legacy_encoder.c */
+extern void
+radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
+                          uint32_t supported_device);
+
+union atom_supported_devices {
+        struct _ATOM_SUPPORTED_DEVICES_INFO info;
+        struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
+        struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
+};
+
+static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device
+                                                           *dev, uint8_t id)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct atom_context *ctx = rdev->mode_info.atom_context;
+        ATOM_GPIO_I2C_ASSIGMENT gpio;
+        struct radeon_i2c_bus_rec i2c;
+        int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
+        struct _ATOM_GPIO_I2C_INFO *i2c_info;
+        uint16_t data_offset;
+
+        memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
+        i2c.valid = false;
+
+        atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset);
+
+        i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
+
+        gpio = i2c_info->asGPIO_Info[id];
+
+        i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4;
+        i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4;
+        i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4;
+        i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4;
+        i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4;
+        i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4;
+        i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4;
+        i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4;
+        i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift);
+        i2c.mask_data_mask = (1 << gpio.ucDataMaskShift);
+        i2c.put_clk_mask = (1 << gpio.ucClkEnShift);
+        i2c.put_data_mask = (1 << gpio.ucDataEnShift);
+        i2c.get_clk_mask = (1 << gpio.ucClkY_Shift);
+        i2c.get_data_mask = (1 << gpio.ucDataY_Shift);
+        i2c.a_clk_mask = (1 << gpio.ucClkA_Shift);
+        i2c.a_data_mask = (1 << gpio.ucDataA_Shift);
+        i2c.valid = true;
+
+        return i2c;
+}
+
+static bool radeon_atom_apply_quirks(struct drm_device *dev,
+                                     uint32_t supported_device,
+                                     int *connector_type,
+                                     struct radeon_i2c_bus_rec *i2c_bus)
+{
+
+        /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
+        if ((dev->pdev->device == 0x791e) &&
+            (dev->pdev->subsystem_vendor == 0x1043) &&
+            (dev->pdev->subsystem_device == 0x826d)) {
+                if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
+                    (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
+                        *connector_type = DRM_MODE_CONNECTOR_DVID;
+        }
+
+        /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
+        if ((dev->pdev->device == 0x7941) &&
+            (dev->pdev->subsystem_vendor == 0x147b) &&
+            (dev->pdev->subsystem_device == 0x2412)) {
+                if (*connector_type == DRM_MODE_CONNECTOR_DVII)
+                        return false;
+        }
+
+        /* Falcon NW laptop lists vga ddc line for LVDS */
+        if ((dev->pdev->device == 0x5653) &&
+            (dev->pdev->subsystem_vendor == 0x1462) &&
+            (dev->pdev->subsystem_device == 0x0291)) {
+                if (*connector_type == DRM_MODE_CONNECTOR_LVDS)
+                        i2c_bus->valid = false;
+        }
+
+        /* Funky macbooks */
+        if ((dev->pdev->device == 0x71C5) &&
+            (dev->pdev->subsystem_vendor == 0x106b) &&
+            (dev->pdev->subsystem_device == 0x0080)) {
+                if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
+                    (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
+                        return false;
+        }
+
+        /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */
+        if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
+            (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
+                if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
+                        return false;
+                }
+        }
+
+        /* ASUS HD 3600 XT board lists the DVI port as HDMI */
+        if ((dev->pdev->device == 0x9598) &&
+            (dev->pdev->subsystem_vendor == 0x1043) &&
+            (dev->pdev->subsystem_device == 0x01da)) {
+                if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) {
+                        *connector_type = DRM_MODE_CONNECTOR_DVID;
+                }
+        }
+
+        return true;
+}
+
+const int supported_devices_connector_convert[] = {
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_VGA,
+        DRM_MODE_CONNECTOR_DVII,
+        DRM_MODE_CONNECTOR_DVID,
+        DRM_MODE_CONNECTOR_DVIA,
+        DRM_MODE_CONNECTOR_SVIDEO,
+        DRM_MODE_CONNECTOR_Composite,
+        DRM_MODE_CONNECTOR_LVDS,
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_HDMIA,
+        DRM_MODE_CONNECTOR_HDMIB,
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_9PinDIN,
+        DRM_MODE_CONNECTOR_DisplayPort
+};
+
+const int object_connector_convert[] = {
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_DVII,
+        DRM_MODE_CONNECTOR_DVII,
+        DRM_MODE_CONNECTOR_DVID,
+        DRM_MODE_CONNECTOR_DVID,
+        DRM_MODE_CONNECTOR_VGA,
+        DRM_MODE_CONNECTOR_Composite,
+        DRM_MODE_CONNECTOR_SVIDEO,
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_9PinDIN,
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_HDMIA,
+        DRM_MODE_CONNECTOR_HDMIB,
+        DRM_MODE_CONNECTOR_HDMIB,
+        DRM_MODE_CONNECTOR_LVDS,
+        DRM_MODE_CONNECTOR_9PinDIN,
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_DisplayPort
+};
+
+bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        struct atom_context *ctx = mode_info->atom_context;
+        int index = GetIndexIntoMasterTable(DATA, Object_Header);
+        uint16_t size, data_offset;
+        uint8_t frev, crev, line_mux = 0;
+        ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
+        ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
+        ATOM_OBJECT_HEADER *obj_header;
+        int i, j, path_size, device_support;
+        int connector_type;
+        uint16_t igp_lane_info;
+        bool linkb;
+        struct radeon_i2c_bus_rec ddc_bus;
+
+        atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
+
+        if (data_offset == 0)
+                return false;
+
+        if (crev < 2)
+                return false;
+
+        obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
+        path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
+            (ctx->bios + data_offset +
+             le16_to_cpu(obj_header->usDisplayPathTableOffset));
+        con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
+            (ctx->bios + data_offset +
+             le16_to_cpu(obj_header->usConnectorObjectTableOffset));
+        device_support = le16_to_cpu(obj_header->usDeviceSupport);
+
+        path_size = 0;
+        for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
+                uint8_t *addr = (uint8_t *) path_obj->asDispPath;
+                ATOM_DISPLAY_OBJECT_PATH *path;
+                addr += path_size;
+                path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
+                path_size += le16_to_cpu(path->usSize);
+                linkb = false;
+
+                if (device_support & le16_to_cpu(path->usDeviceTag)) {
+                        uint8_t con_obj_id, con_obj_num, con_obj_type;
+
+                        con_obj_id =
+                            (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
+                            >> OBJECT_ID_SHIFT;
+                        con_obj_num =
+                            (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
+                            >> ENUM_ID_SHIFT;
+                        con_obj_type =
+                            (le16_to_cpu(path->usConnObjectId) &
+                             OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
+
+                        if ((le16_to_cpu(path->usDeviceTag) ==
+                             ATOM_DEVICE_TV1_SUPPORT)
+                            || (le16_to_cpu(path->usDeviceTag) ==
+                                ATOM_DEVICE_TV2_SUPPORT)
+                            || (le16_to_cpu(path->usDeviceTag) ==
+                                ATOM_DEVICE_CV_SUPPORT))
+                                continue;
+
+                        if ((rdev->family == CHIP_RS780) &&
+                            (con_obj_id ==
+                             CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
+                                uint16_t igp_offset = 0;
+                                ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
+
+                                index =
+                                    GetIndexIntoMasterTable(DATA,
+                                                            IntegratedSystemInfo);
+
+                                atom_parse_data_header(ctx, index, &size, &frev,
+                                                       &crev, &igp_offset);
+
+                                if (crev >= 2) {
+                                        igp_obj =
+                                            (ATOM_INTEGRATED_SYSTEM_INFO_V2
+                                             *) (ctx->bios + igp_offset);
+
+                                        if (igp_obj) {
+                                                uint32_t slot_config, ct;
+
+                                                if (con_obj_num == 1)
+                                                        slot_config =
+                                                            igp_obj->
+                                                            ulDDISlot1Config;
+                                                else
+                                                        slot_config =
+                                                            igp_obj->
+                                                            ulDDISlot2Config;
+
+                                                ct = (slot_config >> 16) & 0xff;
+                                                connector_type =
+                                                    object_connector_convert
+                                                    [ct];
+                                                igp_lane_info =
+                                                    slot_config & 0xffff;
+                                        } else
+                                                continue;
+                                } else
+                                        continue;
+                        } else {
+                                igp_lane_info = 0;
+                                connector_type =
+                                    object_connector_convert[con_obj_id];
+                        }
+
+                        if (connector_type == DRM_MODE_CONNECTOR_Unknown)
+                                continue;
+
+                        for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
+                             j++) {
+                                uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
+
+                                enc_obj_id =
+                                    (le16_to_cpu(path->usGraphicObjIds[j]) &
+                                     OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
+                                enc_obj_num =
+                                    (le16_to_cpu(path->usGraphicObjIds[j]) &
+                                     ENUM_ID_MASK) >> ENUM_ID_SHIFT;
+                                enc_obj_type =
+                                    (le16_to_cpu(path->usGraphicObjIds[j]) &
+                                     OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
+
+                                /* FIXME: add support for router objects */
+                                if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
+                                        if (enc_obj_num == 2)
+                                                linkb = true;
+                                        else
+                                                linkb = false;
+
+                                        radeon_add_atom_encoder(dev,
+                                                                enc_obj_id,
+                                                                le16_to_cpu
+                                                                (path->
+                                                                 usDeviceTag));
+
+                                }
+                        }
+
+                        /* look up gpio for ddc */
+                        if ((le16_to_cpu(path->usDeviceTag) &
+                             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
+                            == 0) {
+                                for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
+                                        if (le16_to_cpu(path->usConnObjectId) ==
+                                            le16_to_cpu(con_obj->asObjects[j].
+                                                        usObjectID)) {
+                                                ATOM_COMMON_RECORD_HEADER
+                                                    *record =
+                                                    (ATOM_COMMON_RECORD_HEADER
+                                                     *)
+                                                    (ctx->bios + data_offset +
+                                                     le16_to_cpu(con_obj->
+                                                                 asObjects[j].
+                                                                 usRecordOffset));
+                                                ATOM_I2C_RECORD *i2c_record;
+
+                                                while (record->ucRecordType > 0
+                                                       && record->
+                                                       ucRecordType <=
+                                                       ATOM_MAX_OBJECT_RECORD_NUMBER) {
+                                                        DRM_ERROR
+                                                            ("record type %d\n",
+                                                             record->
+                                                             ucRecordType);
+                                                        switch (record->
+                                                                ucRecordType) {
+                                                        case ATOM_I2C_RECORD_TYPE:
+                                                                i2c_record =
+                                                                    (ATOM_I2C_RECORD
+                                                                     *) record;
+                                                                line_mux =
+                                                                    i2c_record->
+                                                                    sucI2cId.
+                                                                    bfI2C_LineMux;
+                                                                break;
+                                                        }
+                                                        record =
+                                                            (ATOM_COMMON_RECORD_HEADER
+                                                             *) ((char *)record
+                                                                 +
+                                                                 record->
+                                                                 ucRecordSize);
+                                                }
+                                                break;
+                                        }
+                                }
+                        } else
+                                line_mux = 0;
+
+                        if ((le16_to_cpu(path->usDeviceTag) ==
+                             ATOM_DEVICE_TV1_SUPPORT)
+                            || (le16_to_cpu(path->usDeviceTag) ==
+                                ATOM_DEVICE_TV2_SUPPORT)
+                            || (le16_to_cpu(path->usDeviceTag) ==
+                                ATOM_DEVICE_CV_SUPPORT))
+                                ddc_bus.valid = false;
+                        else
+                                ddc_bus = radeon_lookup_gpio(dev, line_mux);
+
+                        radeon_add_atom_connector(dev,
+                                                  le16_to_cpu(path->
+                                                              usConnObjectId),
+                                                  le16_to_cpu(path->
+                                                              usDeviceTag),
+                                                  connector_type, &ddc_bus,
+                                                  linkb, igp_lane_info);
+
+                }
+        }
+
+        radeon_link_encoder_connector(dev);
+
+        return true;
+}
+
+struct bios_connector {
+        bool valid;
+        uint8_t line_mux;
+        uint16_t devices;
+        int connector_type;
+        struct radeon_i2c_bus_rec ddc_bus;
+};
+
+bool radeon_get_atom_connector_info_from_supported_devices_table(struct
+                                                                 drm_device
+                                                                 *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        struct atom_context *ctx = mode_info->atom_context;
+        int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
+        uint16_t size, data_offset;
+        uint8_t frev, crev;
+        uint16_t device_support;
+        uint8_t dac;
+        union atom_supported_devices *supported_devices;
+        int i, j;
+        struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
+
+        atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
+
+        supported_devices =
+            (union atom_supported_devices *)(ctx->bios + data_offset);
+
+        device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
+
+        for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+                ATOM_CONNECTOR_INFO_I2C ci =
+                    supported_devices->info.asConnInfo[i];
+
+                bios_connectors[i].valid = false;
+
+                if (!(device_support & (1 << i))) {
+                        continue;
+                }
+
+                if (i == ATOM_DEVICE_CV_INDEX) {
+                        DRM_DEBUG("Skipping Component Video\n");
+                        continue;
+                }
+
+                if (i == ATOM_DEVICE_TV1_INDEX) {
+                        DRM_DEBUG("Skipping TV Out\n");
+                        continue;
+                }
+
+                bios_connectors[i].connector_type =
+                    supported_devices_connector_convert[ci.sucConnectorInfo.
+                                                        sbfAccess.
+                                                        bfConnectorType];
+
+                if (bios_connectors[i].connector_type ==
+                    DRM_MODE_CONNECTOR_Unknown)
+                        continue;
+
+                dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
+
+                if ((rdev->family == CHIP_RS690) ||
+                    (rdev->family == CHIP_RS740)) {
+                        if ((i == ATOM_DEVICE_DFP2_INDEX)
+                            && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
+                                bios_connectors[i].line_mux =
+                                    ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
+                        else if ((i == ATOM_DEVICE_DFP3_INDEX)
+                                 && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
+                                bios_connectors[i].line_mux =
+                                    ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
+                        else
+                                bios_connectors[i].line_mux =
+                                    ci.sucI2cId.sbfAccess.bfI2C_LineMux;
+                } else
+                        bios_connectors[i].line_mux =
+                            ci.sucI2cId.sbfAccess.bfI2C_LineMux;
+
+                /* give tv unique connector ids */
+                if (i == ATOM_DEVICE_TV1_INDEX) {
+                        bios_connectors[i].ddc_bus.valid = false;
+                        bios_connectors[i].line_mux = 50;
+                } else if (i == ATOM_DEVICE_TV2_INDEX) {
+                        bios_connectors[i].ddc_bus.valid = false;
+                        bios_connectors[i].line_mux = 51;
+                } else if (i == ATOM_DEVICE_CV_INDEX) {
+                        bios_connectors[i].ddc_bus.valid = false;
+                        bios_connectors[i].line_mux = 52;
+                } else
+                        bios_connectors[i].ddc_bus =
+                            radeon_lookup_gpio(dev,
+                                               bios_connectors[i].line_mux);
+
+                /* Always set the connector type to VGA for CRT1/CRT2. if they are
+                 * shared with a DVI port, we'll pick up the DVI connector when we
+                 * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
+                 */
+                if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
+                        bios_connectors[i].connector_type =
+                            DRM_MODE_CONNECTOR_VGA;
+
+                if (!radeon_atom_apply_quirks
+                    (dev, (1 << i), &bios_connectors[i].connector_type,
+                     &bios_connectors[i].ddc_bus))
+                        continue;
+
+                bios_connectors[i].valid = true;
+                bios_connectors[i].devices = (1 << i);
+
+                if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
+                        radeon_add_atom_encoder(dev,
+                                                radeon_get_encoder_id(dev,
+                                                                      (1 << i),
+                                                                      dac),
+                                                (1 << i));
+                else
+                        radeon_add_legacy_encoder(dev,
+                                                  radeon_get_encoder_id(dev,
+                                                                        (1 <<
+                                                                         i),
+                                                                        dac),
+                                                  (1 << i));
+        }
+
+        /* combine shared connectors */
+        for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+                if (bios_connectors[i].valid) {
+                        for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
+                                if (bios_connectors[j].valid && (i != j)) {
+                                        if (bios_connectors[i].line_mux ==
+                                            bios_connectors[j].line_mux) {
+                                                if (((bios_connectors[i].
+                                                      devices &
+                                                      (ATOM_DEVICE_DFP_SUPPORT))
+                                                     && (bios_connectors[j].
+                                                         devices &
+                                                         (ATOM_DEVICE_CRT_SUPPORT)))
+                                                    ||
+                                                    ((bios_connectors[j].
+                                                      devices &
+                                                      (ATOM_DEVICE_DFP_SUPPORT))
+                                                     && (bios_connectors[i].
+                                                         devices &
+                                                         (ATOM_DEVICE_CRT_SUPPORT)))) {
+                                                        bios_connectors[i].
+                                                            devices |=
+                                                            bios_connectors[j].
+                                                            devices;
+                                                        bios_connectors[i].
+                                                            connector_type =
+                                                            DRM_MODE_CONNECTOR_DVII;
+                                                        bios_connectors[j].
+                                                            valid = false;
+                                                }
+                                        }
+                                }
+                        }
+                }
+        }
+
+        /* add the connectors */
+        for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+                if (bios_connectors[i].valid)
+                        radeon_add_atom_connector(dev,
+                                                  bios_connectors[i].line_mux,
+                                                  bios_connectors[i].devices,
+                                                  bios_connectors[i].
+                                                  connector_type,
+                                                  &bios_connectors[i].ddc_bus,
+                                                  false, 0);
+        }
+
+        radeon_link_encoder_connector(dev);
+
+        return true;
+}
+
+union firmware_info {
+        ATOM_FIRMWARE_INFO info;
+        ATOM_FIRMWARE_INFO_V1_2 info_12;
+        ATOM_FIRMWARE_INFO_V1_3 info_13;
+        ATOM_FIRMWARE_INFO_V1_4 info_14;
+};
+
+bool radeon_atom_get_clock_info(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
+        union firmware_info *firmware_info;
+        uint8_t frev, crev;
+        struct radeon_pll *p1pll = &rdev->clock.p1pll;
+        struct radeon_pll *p2pll = &rdev->clock.p2pll;
+        struct radeon_pll *spll = &rdev->clock.spll;
+        struct radeon_pll *mpll = &rdev->clock.mpll;
+        uint16_t data_offset;
+
+        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+                               &crev, &data_offset);
+
+        firmware_info =
+            (union firmware_info *)(mode_info->atom_context->bios +
+                                    data_offset);
+
+        if (firmware_info) {
+                /* pixel clocks */
+                p1pll->reference_freq =
+                    le16_to_cpu(firmware_info->info.usReferenceClock);
+                p1pll->reference_div = 0;
+
+                p1pll->pll_out_min =
+                    le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
+                p1pll->pll_out_max =
+                    le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
+
+                if (p1pll->pll_out_min == 0) {
+                        if (ASIC_IS_AVIVO(rdev))
+                                p1pll->pll_out_min = 64800;
+                        else
+                                p1pll->pll_out_min = 20000;
+                }
+
+                p1pll->pll_in_min =
+                    le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
+                p1pll->pll_in_max =
+                    le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
+
+                *p2pll = *p1pll;
+
+                /* system clock */
+                spll->reference_freq =
+                    le16_to_cpu(firmware_info->info.usReferenceClock);
+                spll->reference_div = 0;
+
+                spll->pll_out_min =
+                    le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
+                spll->pll_out_max =
+                    le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
+
+                /* ??? */
+                if (spll->pll_out_min == 0) {
+                        if (ASIC_IS_AVIVO(rdev))
+                                spll->pll_out_min = 64800;
+                        else
+                                spll->pll_out_min = 20000;
+                }
+
+                spll->pll_in_min =
+                    le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
+                spll->pll_in_max =
+                    le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
+
+                /* memory clock */
+                mpll->reference_freq =
+                    le16_to_cpu(firmware_info->info.usReferenceClock);
+                mpll->reference_div = 0;
+
+                mpll->pll_out_min =
+                    le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
+                mpll->pll_out_max =
+                    le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
+
+                /* ??? */
+                if (mpll->pll_out_min == 0) {
+                        if (ASIC_IS_AVIVO(rdev))
+                                mpll->pll_out_min = 64800;
+                        else
+                                mpll->pll_out_min = 20000;
+                }
+
+                mpll->pll_in_min =
+                    le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
+                mpll->pll_in_max =
+                    le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
+
+                rdev->clock.default_sclk =
+                    le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
+                rdev->clock.default_mclk =
+                    le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
+
+                return true;
+        }
+        return false;
+}
+
+struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct
+                                                              radeon_encoder
+                                                              *encoder)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
+        uint16_t data_offset;
+        struct _ATOM_TMDS_INFO *tmds_info;
+        uint8_t frev, crev;
+        uint16_t maxfreq;
+        int i;
+        struct radeon_encoder_int_tmds *tmds = NULL;
+
+        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+                               &crev, &data_offset);
+
+        tmds_info =
+            (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
+                                       data_offset);
+
+        if (tmds_info) {
+                tmds =
+                    kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
+
+                if (!tmds)
+                        return NULL;
+
+                maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
+                for (i = 0; i < 4; i++) {
+                        tmds->tmds_pll[i].freq =
+                            le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
+                        tmds->tmds_pll[i].value =
+                            tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
+                        tmds->tmds_pll[i].value |=
+                            (tmds_info->asMiscInfo[i].
+                             ucPLL_VCO_Gain & 0x3f) << 6;
+                        tmds->tmds_pll[i].value |=
+                            (tmds_info->asMiscInfo[i].
+                             ucPLL_DutyCycle & 0xf) << 12;
+                        tmds->tmds_pll[i].value |=
+                            (tmds_info->asMiscInfo[i].
+                             ucPLL_VoltageSwing & 0xf) << 16;
+
+                        DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
+                                  tmds->tmds_pll[i].freq,
+                                  tmds->tmds_pll[i].value);
+
+                        if (maxfreq == tmds->tmds_pll[i].freq) {
+                                tmds->tmds_pll[i].freq = 0xffffffff;
+                                break;
+                        }
+                }
+        }
+        return tmds;
+}
+
+union lvds_info {
+        struct _ATOM_LVDS_INFO info;
+        struct _ATOM_LVDS_INFO_V12 info_12;
+};
+
+struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
+                                                              radeon_encoder
+                                                              *encoder)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
+        uint16_t data_offset;
+        union lvds_info *lvds_info;
+        uint8_t frev, crev;
+        struct radeon_encoder_atom_dig *lvds = NULL;
+
+        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
+                               &crev, &data_offset);
+
+        lvds_info =
+            (union lvds_info *)(mode_info->atom_context->bios + data_offset);
+
+        if (lvds_info) {
+                lvds =
+                    kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
+
+                if (!lvds)
+                        return NULL;
+
+                lvds->native_mode.dotclock =
+                    le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
+                lvds->native_mode.panel_xres =
+                    le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
+                lvds->native_mode.panel_yres =
+                    le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
+                lvds->native_mode.hblank =
+                    le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
+                lvds->native_mode.hoverplus =
+                    le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
+                lvds->native_mode.hsync_width =
+                    le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
+                lvds->native_mode.vblank =
+                    le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
+                lvds->native_mode.voverplus =
+                    le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
+                lvds->native_mode.vsync_width =
+                    le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
+                lvds->panel_pwr_delay =
+                    le16_to_cpu(lvds_info->info.usOffDelayInMs);
+                lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
+
+                encoder->native_mode = lvds->native_mode;
+        }
+        return lvds;
+}
+
+struct radeon_encoder_primary_dac *
+radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        int index = GetIndexIntoMasterTable(DATA, CompassionateData);
+        uint16_t data_offset;
+        struct _COMPASSIONATE_DATA *dac_info;
+        uint8_t frev, crev;
+        uint8_t bg, dac;
+        int i;
+        struct radeon_encoder_primary_dac *p_dac = NULL;
+
+        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
+
+        dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
+
+        if (dac_info) {
+                p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
+
+                if (!p_dac)
+                        return NULL;
+
+                bg = dac_info->ucDAC1_BG_Adjustment;
+                dac = dac_info->ucDAC1_DAC_Adjustment;
+                p_dac->ps2_pdac_adj = (bg << 8) | (dac);
+
+        }
+        return p_dac;
+}
+
+struct radeon_encoder_tv_dac *
+radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_mode_info *mode_info = &rdev->mode_info;
+        int index = GetIndexIntoMasterTable(DATA, CompassionateData);
+        uint16_t data_offset;
+        struct _COMPASSIONATE_DATA *dac_info;
+        uint8_t frev, crev;
+        uint8_t bg, dac;
+        int i;
+        struct radeon_encoder_tv_dac *tv_dac = NULL;
+
+        atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset);
+
+        dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset);
+
+        if (dac_info) {
+                tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
+
+                if (!tv_dac)
+                        return NULL;
+
+                bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
+                dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
+                tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
+
+                bg = dac_info->ucDAC2_PAL_BG_Adjustment;
+                dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
+                tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
+
+                bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
+                dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
+                tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
+
+        }
+        return tv_dac;
+}
+
+void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
+{
+        DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
+        int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
+
+        args.ucEnable = enable;
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+
+void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
+{
+        ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args;
+        int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt);
+
+        args.ucEnable = enable;
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+
+void radeon_atom_set_engine_clock(struct radeon_device *rdev,
+                                  uint32_t eng_clock)
+{
+        SET_ENGINE_CLOCK_PS_ALLOCATION args;
+        int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
+
+        args.ulTargetEngineClock = eng_clock;   /* 10 khz */
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+
+void radeon_atom_set_memory_clock(struct radeon_device *rdev,
+                                  uint32_t mem_clock)
+{
+        SET_MEMORY_CLOCK_PS_ALLOCATION args;
+        int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
+
+        if (rdev->flags & RADEON_IS_IGP)
+                return;
+
+        args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+}
+
+void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t bios_2_scratch, bios_6_scratch;
+
+        if (rdev->family >= CHIP_R600) {
+                bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH);
+                bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
+        } else {
+                bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
+                bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
+        }
+
+        /* let the bios control the backlight */
+        bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
+
+        /* tell the bios not to handle mode switching */
+        bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
+
+        if (rdev->family >= CHIP_R600) {
+                WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
+                WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
+        } else {
+                WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
+                WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
+        }
+
+}
+
+void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t bios_6_scratch;
+
+        if (rdev->family >= CHIP_R600)
+                bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
+        else
+                bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
+
+        if (lock)
+                bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
+        else
+                bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
+
+        if (rdev->family >= CHIP_R600)
+                WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
+        else
+                WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
+}
+
+/* at some point we may want to break this out into individual functions */
+void
+radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
+                                       struct drm_encoder *encoder,
+                                       bool connected)
+{
+        struct drm_device *dev = connector->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_connector *radeon_connector =
+            to_radeon_connector(connector);
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
+
+        if (rdev->family >= CHIP_R600) {
+                bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
+                bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
+                bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
+        } else {
+                bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
+                bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
+                bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
+        }
+
+        if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("TV1 connected\n");
+                        bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
+                        bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
+                } else {
+                        DRM_DEBUG("TV1 disconnected\n");
+                        bios_0_scratch &= ~ATOM_S0_TV1_MASK;
+                        bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
+                        bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("CV connected\n");
+                        bios_3_scratch |= ATOM_S3_CV_ACTIVE;
+                        bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
+                } else {
+                        DRM_DEBUG("CV disconnected\n");
+                        bios_0_scratch &= ~ATOM_S0_CV_MASK;
+                        bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
+                        bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("LCD1 connected\n");
+                        bios_0_scratch |= ATOM_S0_LCD1;
+                        bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
+                        bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
+                } else {
+                        DRM_DEBUG("LCD1 disconnected\n");
+                        bios_0_scratch &= ~ATOM_S0_LCD1;
+                        bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
+                        bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("CRT1 connected\n");
+                        bios_0_scratch |= ATOM_S0_CRT1_COLOR;
+                        bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
+                        bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
+                } else {
+                        DRM_DEBUG("CRT1 disconnected\n");
+                        bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
+                        bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
+                        bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("CRT2 connected\n");
+                        bios_0_scratch |= ATOM_S0_CRT2_COLOR;
+                        bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
+                        bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
+                } else {
+                        DRM_DEBUG("CRT2 disconnected\n");
+                        bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
+                        bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
+                        bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("DFP1 connected\n");
+                        bios_0_scratch |= ATOM_S0_DFP1;
+                        bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
+                        bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
+                } else {
+                        DRM_DEBUG("DFP1 disconnected\n");
+                        bios_0_scratch &= ~ATOM_S0_DFP1;
+                        bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
+                        bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("DFP2 connected\n");
+                        bios_0_scratch |= ATOM_S0_DFP2;
+                        bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
+                        bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
+                } else {
+                        DRM_DEBUG("DFP2 disconnected\n");
+                        bios_0_scratch &= ~ATOM_S0_DFP2;
+                        bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
+                        bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("DFP3 connected\n");
+                        bios_0_scratch |= ATOM_S0_DFP3;
+                        bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
+                        bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
+                } else {
+                        DRM_DEBUG("DFP3 disconnected\n");
+                        bios_0_scratch &= ~ATOM_S0_DFP3;
+                        bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
+                        bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("DFP4 connected\n");
+                        bios_0_scratch |= ATOM_S0_DFP4;
+                        bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
+                        bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
+                } else {
+                        DRM_DEBUG("DFP4 disconnected\n");
+                        bios_0_scratch &= ~ATOM_S0_DFP4;
+                        bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
+                        bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("DFP5 connected\n");
+                        bios_0_scratch |= ATOM_S0_DFP5;
+                        bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
+                        bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
+                } else {
+                        DRM_DEBUG("DFP5 disconnected\n");
+                        bios_0_scratch &= ~ATOM_S0_DFP5;
+                        bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
+                        bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
+                }
+        }
+
+        if (rdev->family >= CHIP_R600) {
+                WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
+                WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
+                WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
+        } else {
+                WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
+                WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
+                WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
+        }
+}
+
+void
+radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t bios_3_scratch;
+
+        if (rdev->family >= CHIP_R600)
+                bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
+        else
+                bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
+
+        if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
+                bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
+                bios_3_scratch |= (crtc << 18);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
+                bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
+                bios_3_scratch |= (crtc << 24);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
+                bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
+                bios_3_scratch |= (crtc << 16);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
+                bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
+                bios_3_scratch |= (crtc << 20);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
+                bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
+                bios_3_scratch |= (crtc << 17);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
+                bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
+                bios_3_scratch |= (crtc << 19);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
+                bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
+                bios_3_scratch |= (crtc << 23);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
+                bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
+                bios_3_scratch |= (crtc << 25);
+        }
+
+        if (rdev->family >= CHIP_R600)
+                WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
+        else
+                WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
+}
+
+void
+radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t bios_2_scratch;
+
+        if (rdev->family >= CHIP_R600)
+                bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
+        else
+                bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
+
+        if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
+                if (on)
+                        bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
+                else
+                        bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
+                if (on)
+                        bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
+                else
+                        bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
+                if (on)
+                        bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
+                else
+                        bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
+                if (on)
+                        bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
+                else
+                        bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
+                if (on)
+                        bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
+                else
+                        bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
+                if (on)
+                        bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
+                else
+                        bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
+                if (on)
+                        bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
+                else
+                        bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
+                if (on)
+                        bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
+                else
+                        bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
+                if (on)
+                        bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
+                else
+                        bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
+                if (on)
+                        bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
+                else
+                        bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
+        }
+
+        if (rdev->family >= CHIP_R600)
+                WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
+        else
+                WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
+}
diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c
new file mode 100644
index 000000000000..c44403a2ca76
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Jerome Glisse
+ */
+#include <drm/drmP.h>
+#include <drm/radeon_drm.h>
+#include "radeon_reg.h"
+#include "radeon.h"
+
+void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
+                           unsigned sdomain, unsigned ddomain)
+{
+        struct radeon_object *dobj = NULL;
+        struct radeon_object *sobj = NULL;
+        struct radeon_fence *fence = NULL;
+        uint64_t saddr, daddr;
+        unsigned long start_jiffies;
+        unsigned long end_jiffies;
+        unsigned long time;
+        unsigned i, n, size;
+        int r;
+
+        size = bsize;
+        n = 1024;
+        r = radeon_object_create(rdev, NULL, size, true, sdomain, false, &sobj);
+        if (r) {
+                goto out_cleanup;
+        }
+        r = radeon_object_pin(sobj, sdomain, &saddr);
+        if (r) {
+                goto out_cleanup;
+        }
+        r = radeon_object_create(rdev, NULL, size, true, ddomain, false, &dobj);
+        if (r) {
+                goto out_cleanup;
+        }
+        r = radeon_object_pin(dobj, ddomain, &daddr);
+        if (r) {
+                goto out_cleanup;
+        }
+        start_jiffies = jiffies;
+        for (i = 0; i < n; i++) {
+                r = radeon_fence_create(rdev, &fence);
+                if (r) {
+                        goto out_cleanup;
+                }
+                r = radeon_copy_dma(rdev, saddr, daddr, size >> 14, fence);
+                if (r) {
+                        goto out_cleanup;
+                }
+                r = radeon_fence_wait(fence, false);
+                if (r) {
+                        goto out_cleanup;
+                }
+                radeon_fence_unref(&fence);
+        }
+        end_jiffies = jiffies;
+        time = end_jiffies - start_jiffies;
+        time = jiffies_to_msecs(time);
+        if (time > 0) {
+                i = ((n * size) >> 10) / time;
+                printk(KERN_INFO "radeon: dma %u bo moves of %ukb from %d to %d"
+                       " in %lums (%ukb/ms %ukb/s %uM/s)\n", n, size >> 10,
+                       sdomain, ddomain, time, i, i * 1000, (i * 1000) / 1024);
+        }
+        start_jiffies = jiffies;
+        for (i = 0; i < n; i++) {
+                r = radeon_fence_create(rdev, &fence);
+                if (r) {
+                        goto out_cleanup;
+                }
+                r = radeon_copy_blit(rdev, saddr, daddr, size >> 14, fence);
+                if (r) {
+                        goto out_cleanup;
+                }
+                r = radeon_fence_wait(fence, false);
+                if (r) {
+                        goto out_cleanup;
+                }
+                radeon_fence_unref(&fence);
+        }
+        end_jiffies = jiffies;
+        time = end_jiffies - start_jiffies;
+        time = jiffies_to_msecs(time);
+        if (time > 0) {
+                i = ((n * size) >> 10) / time;
+                printk(KERN_INFO "radeon: blit %u bo moves of %ukb from %d to %d"
+                       " in %lums (%ukb/ms %ukb/s %uM/s)\n", n, size >> 10,
+                       sdomain, ddomain, time, i, i * 1000, (i * 1000) / 1024);
+        }
+out_cleanup:
+        if (sobj) {
+                radeon_object_unpin(sobj);
+                radeon_object_unref(&sobj);
+        }
+        if (dobj) {
+                radeon_object_unpin(dobj);
+                radeon_object_unref(&dobj);
+        }
+        if (fence) {
+                radeon_fence_unref(&fence);
+        }
+        if (r) {
+                printk(KERN_WARNING "Error while benchmarking BO move.\n");
+        }
+}
+
+void radeon_benchmark(struct radeon_device *rdev)
+{
+        radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_GTT,
+                              RADEON_GEM_DOMAIN_VRAM);
+        radeon_benchmark_move(rdev, 1024*1024, RADEON_GEM_DOMAIN_VRAM,
+                              RADEON_GEM_DOMAIN_GTT);
+}
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
new file mode 100644
index 000000000000..96e37a6e7ce4
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -0,0 +1,390 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+#include "atom.h"
+
+/*
+ * BIOS.
+ */
+static bool radeon_read_bios(struct radeon_device *rdev)
+{
+        uint8_t __iomem *bios;
+        size_t size;
+
+        rdev->bios = NULL;
+        bios = pci_map_rom(rdev->pdev, &size);
+        if (!bios) {
+                return false;
+        }
+
+        if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
+                pci_unmap_rom(rdev->pdev, bios);
+                return false;
+        }
+        rdev->bios = kmalloc(size, GFP_KERNEL);
+        if (rdev->bios == NULL) {
+                pci_unmap_rom(rdev->pdev, bios);
+                return false;
+        }
+        memcpy(rdev->bios, bios, size);
+        pci_unmap_rom(rdev->pdev, bios);
+        return true;
+}
+
+static bool r700_read_disabled_bios(struct radeon_device *rdev)
+{
+        uint32_t viph_control;
+        uint32_t bus_cntl;
+        uint32_t d1vga_control;
+        uint32_t d2vga_control;
+        uint32_t vga_render_control;
+        uint32_t rom_cntl;
+        uint32_t cg_spll_func_cntl = 0;
+        uint32_t cg_spll_status;
+        bool r;
+
+        viph_control = RREG32(RADEON_VIPH_CONTROL);
+        bus_cntl = RREG32(RADEON_BUS_CNTL);
+        d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
+        d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
+        vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
+        rom_cntl = RREG32(R600_ROM_CNTL);
+
+        /* disable VIP */
+        WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
+        /* enable the rom */
+        WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
+        /* Disable VGA mode */
+        WREG32(AVIVO_D1VGA_CONTROL,
+               (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
+                AVIVO_DVGA_CONTROL_TIMING_SELECT)));
+        WREG32(AVIVO_D2VGA_CONTROL,
+               (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
+                AVIVO_DVGA_CONTROL_TIMING_SELECT)));
+        WREG32(AVIVO_VGA_RENDER_CONTROL,
+               (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
+
+        if (rdev->family == CHIP_RV730) {
+                cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
+
+                /* enable bypass mode */
+                WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
+                                                R600_SPLL_BYPASS_EN));
+
+                /* wait for SPLL_CHG_STATUS to change to 1 */
+                cg_spll_status = 0;
+                while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
+                        cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
+
+                WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
+        } else
+                WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
+
+        r = radeon_read_bios(rdev);
+
+        /* restore regs */
+        if (rdev->family == CHIP_RV730) {
+                WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
+
+                /* wait for SPLL_CHG_STATUS to change to 1 */
+                cg_spll_status = 0;
+                while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
+                        cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
+        }
+        WREG32(RADEON_VIPH_CONTROL, viph_control);
+        WREG32(RADEON_BUS_CNTL, bus_cntl);
+        WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
+        WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
+        WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
+        WREG32(R600_ROM_CNTL, rom_cntl);
+        return r;
+}
+
+static bool r600_read_disabled_bios(struct radeon_device *rdev)
+{
+        uint32_t viph_control;
+        uint32_t bus_cntl;
+        uint32_t d1vga_control;
+        uint32_t d2vga_control;
+        uint32_t vga_render_control;
+        uint32_t rom_cntl;
+        uint32_t general_pwrmgt;
+        uint32_t low_vid_lower_gpio_cntl;
+        uint32_t medium_vid_lower_gpio_cntl;
+        uint32_t high_vid_lower_gpio_cntl;
+        uint32_t ctxsw_vid_lower_gpio_cntl;
+        uint32_t lower_gpio_enable;
+        bool r;
+
+        viph_control = RREG32(RADEON_VIPH_CONTROL);
+        bus_cntl = RREG32(RADEON_BUS_CNTL);
+        d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
+        d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
+        vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
+        rom_cntl = RREG32(R600_ROM_CNTL);
+        general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
+        low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
+        medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
+        high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
+        ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
+        lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
+
+        /* disable VIP */
+        WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
+        /* enable the rom */
+        WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
+        /* Disable VGA mode */
+        WREG32(AVIVO_D1VGA_CONTROL,
+               (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
+                AVIVO_DVGA_CONTROL_TIMING_SELECT)));
+        WREG32(AVIVO_D2VGA_CONTROL,
+               (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
+                AVIVO_DVGA_CONTROL_TIMING_SELECT)));
+        WREG32(AVIVO_VGA_RENDER_CONTROL,
+               (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
+
+        WREG32(R600_ROM_CNTL,
+               ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
+                (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
+                R600_SCK_OVERWRITE));
+
+        WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
+        WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
+               (low_vid_lower_gpio_cntl & ~0x400));
+        WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
+               (medium_vid_lower_gpio_cntl & ~0x400));
+        WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
+               (high_vid_lower_gpio_cntl & ~0x400));
+        WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
+               (ctxsw_vid_lower_gpio_cntl & ~0x400));
+        WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
+
+        r = radeon_read_bios(rdev);
+
+        /* restore regs */
+        WREG32(RADEON_VIPH_CONTROL, viph_control);
+        WREG32(RADEON_BUS_CNTL, bus_cntl);
+        WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
+        WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
+        WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
+        WREG32(R600_ROM_CNTL, rom_cntl);
+        WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
+        WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
+        WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
+        WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
+        WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
+        WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
+        return r;
+}
+
+static bool avivo_read_disabled_bios(struct radeon_device *rdev)
+{
+        uint32_t seprom_cntl1;
+        uint32_t viph_control;
+        uint32_t bus_cntl;
+        uint32_t d1vga_control;
+        uint32_t d2vga_control;
+        uint32_t vga_render_control;
+        uint32_t gpiopad_a;
+        uint32_t gpiopad_en;
+        uint32_t gpiopad_mask;
+        bool r;
+
+        seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
+        viph_control = RREG32(RADEON_VIPH_CONTROL);
+        bus_cntl = RREG32(RADEON_BUS_CNTL);
+        d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
+        d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
+        vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
+        gpiopad_a = RREG32(RADEON_GPIOPAD_A);
+        gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
+        gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
+
+        WREG32(RADEON_SEPROM_CNTL1,
+               ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
+                (0xc << RADEON_SCK_PRESCALE_SHIFT)));
+        WREG32(RADEON_GPIOPAD_A, 0);
+        WREG32(RADEON_GPIOPAD_EN, 0);
+        WREG32(RADEON_GPIOPAD_MASK, 0);
+
+        /* disable VIP */
+        WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
+
+        /* enable the rom */
+        WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
+
+        /* Disable VGA mode */
+        WREG32(AVIVO_D1VGA_CONTROL,
+               (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
+                AVIVO_DVGA_CONTROL_TIMING_SELECT)));
+        WREG32(AVIVO_D2VGA_CONTROL,
+               (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
+                AVIVO_DVGA_CONTROL_TIMING_SELECT)));
+        WREG32(AVIVO_VGA_RENDER_CONTROL,
+               (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
+
+        r = radeon_read_bios(rdev);
+
+        /* restore regs */
+        WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
+        WREG32(RADEON_VIPH_CONTROL, viph_control);
+        WREG32(RADEON_BUS_CNTL, bus_cntl);
+        WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
+        WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
+        WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
+        WREG32(RADEON_GPIOPAD_A, gpiopad_a);
+        WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
+        WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
+        return r;
+}
+
+static bool legacy_read_disabled_bios(struct radeon_device *rdev)
+{
+        uint32_t seprom_cntl1;
+        uint32_t viph_control;
+        uint32_t bus_cntl;
+        uint32_t crtc_gen_cntl;
+        uint32_t crtc2_gen_cntl;
+        uint32_t crtc_ext_cntl;
+        uint32_t fp2_gen_cntl;
+        bool r;
+
+        seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
+        viph_control = RREG32(RADEON_VIPH_CONTROL);
+        bus_cntl = RREG32(RADEON_BUS_CNTL);
+        crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
+        crtc2_gen_cntl = 0;
+        crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
+        fp2_gen_cntl = 0;
+
+        if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
+                fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
+        }
+
+        if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+                crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
+        }
+
+        WREG32(RADEON_SEPROM_CNTL1,
+               ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
+                (0xc << RADEON_SCK_PRESCALE_SHIFT)));
+
+        /* disable VIP */
+        WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
+
+        /* enable the rom */
+        WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
+
+        /* Turn off mem requests and CRTC for both controllers */
+        WREG32(RADEON_CRTC_GEN_CNTL,
+               ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
+                (RADEON_CRTC_DISP_REQ_EN_B |
+                 RADEON_CRTC_EXT_DISP_EN)));
+        if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+                WREG32(RADEON_CRTC2_GEN_CNTL,
+                       ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
+                        RADEON_CRTC2_DISP_REQ_EN_B));
+        }
+        /* Turn off CRTC */
+        WREG32(RADEON_CRTC_EXT_CNTL,
+               ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
+                (RADEON_CRTC_SYNC_TRISTAT |
+                 RADEON_CRTC_DISPLAY_DIS)));
+
+        if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
+                WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
+        }
+
+        r = radeon_read_bios(rdev);
+
+        /* restore regs */
+        WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
+        WREG32(RADEON_VIPH_CONTROL, viph_control);
+        WREG32(RADEON_BUS_CNTL, bus_cntl);
+        WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
+        if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
+                WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+        }
+        WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
+        if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
+                WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+        }
+        return r;
+}
+
+static bool radeon_read_disabled_bios(struct radeon_device *rdev)
+{
+        if (rdev->family >= CHIP_RV770)
+                return r700_read_disabled_bios(rdev);
+        else if (rdev->family >= CHIP_R600)
+                return r600_read_disabled_bios(rdev);
+        else if (rdev->family >= CHIP_RS600)
+                return avivo_read_disabled_bios(rdev);
+        else
+                return legacy_read_disabled_bios(rdev);
+}
+
+bool radeon_get_bios(struct radeon_device *rdev)
+{
+        bool r;
+        uint16_t tmp;
+
+        r = radeon_read_bios(rdev);
+        if (r == false) {
+                r = radeon_read_disabled_bios(rdev);
+        }
+        if (r == false || rdev->bios == NULL) {
+                DRM_ERROR("Unable to locate a BIOS ROM\n");
+                rdev->bios = NULL;
+                return false;
+        }
+        if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
+                goto free_bios;
+        }
+
+        rdev->bios_header_start = RBIOS16(0x48);
+        if (!rdev->bios_header_start) {
+                goto free_bios;
+        }
+        tmp = rdev->bios_header_start + 4;
+        if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
+            !memcmp(rdev->bios + tmp, "MOTA", 4)) {
+                rdev->is_atom_bios = true;
+        } else {
+                rdev->is_atom_bios = false;
+        }
+
+        DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
+        return true;
+free_bios:
+        kfree(rdev->bios);
+        rdev->bios = NULL;
+        return false;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
new file mode 100644
index 000000000000..a37cbce53181
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -0,0 +1,833 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+#include "atom.h"
+
+/* 10 khz */
+static uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
+{
+        struct radeon_pll *spll = &rdev->clock.spll;
+        uint32_t fb_div, ref_div, post_div, sclk;
+
+        fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
+        fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK;
+        fb_div <<= 1;
+        fb_div *= spll->reference_freq;
+
+        ref_div =
+            RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
+        sclk = fb_div / ref_div;
+
+        post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK;
+        if (post_div == 2)
+                sclk >>= 1;
+        else if (post_div == 3)
+                sclk >>= 2;
+        else if (post_div == 4)
+                sclk >>= 4;
+
+        return sclk;
+}
+
+/* 10 khz */
+static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
+{
+        struct radeon_pll *mpll = &rdev->clock.mpll;
+        uint32_t fb_div, ref_div, post_div, mclk;
+
+        fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
+        fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK;
+        fb_div <<= 1;
+        fb_div *= mpll->reference_freq;
+
+        ref_div =
+            RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK;
+        mclk = fb_div / ref_div;
+
+        post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7;
+        if (post_div == 2)
+                mclk >>= 1;
+        else if (post_div == 3)
+                mclk >>= 2;
+        else if (post_div == 4)
+                mclk >>= 4;
+
+        return mclk;
+}
+
+void radeon_get_clock_info(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_pll *p1pll = &rdev->clock.p1pll;
+        struct radeon_pll *p2pll = &rdev->clock.p2pll;
+        struct radeon_pll *spll = &rdev->clock.spll;
+        struct radeon_pll *mpll = &rdev->clock.mpll;
+        int ret;
+
+        if (rdev->is_atom_bios)
+                ret = radeon_atom_get_clock_info(dev);
+        else
+                ret = radeon_combios_get_clock_info(dev);
+
+        if (ret) {
+                if (p1pll->reference_div < 2)
+                        p1pll->reference_div = 12;
+                if (p2pll->reference_div < 2)
+                        p2pll->reference_div = 12;
+                if (spll->reference_div < 2)
+                        spll->reference_div =
+                            RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
+                            RADEON_M_SPLL_REF_DIV_MASK;
+                if (mpll->reference_div < 2)
+                        mpll->reference_div = spll->reference_div;
+        } else {
+                if (ASIC_IS_AVIVO(rdev)) {
+                        /* TODO FALLBACK */
+                } else {
+                        DRM_INFO("Using generic clock info\n");
+
+                        if (rdev->flags & RADEON_IS_IGP) {
+                                p1pll->reference_freq = 1432;
+                                p2pll->reference_freq = 1432;
+                                spll->reference_freq = 1432;
+                                mpll->reference_freq = 1432;
+                        } else {
+                                p1pll->reference_freq = 2700;
+                                p2pll->reference_freq = 2700;
+                                spll->reference_freq = 2700;
+                                mpll->reference_freq = 2700;
+                        }
+                        p1pll->reference_div =
+                            RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
+                        if (p1pll->reference_div < 2)
+                                p1pll->reference_div = 12;
+                        p2pll->reference_div = p1pll->reference_div;
+
+                        if (rdev->family >= CHIP_R420) {
+                                p1pll->pll_in_min = 100;
+                                p1pll->pll_in_max = 1350;
+                                p1pll->pll_out_min = 20000;
+                                p1pll->pll_out_max = 50000;
+                                p2pll->pll_in_min = 100;
+                                p2pll->pll_in_max = 1350;
+                                p2pll->pll_out_min = 20000;
+                                p2pll->pll_out_max = 50000;
+                        } else {
+                                p1pll->pll_in_min = 40;
+                                p1pll->pll_in_max = 500;
+                                p1pll->pll_out_min = 12500;
+                                p1pll->pll_out_max = 35000;
+                                p2pll->pll_in_min = 40;
+                                p2pll->pll_in_max = 500;
+                                p2pll->pll_out_min = 12500;
+                                p2pll->pll_out_max = 35000;
+                        }
+
+                        spll->reference_div =
+                            RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
+                            RADEON_M_SPLL_REF_DIV_MASK;
+                        mpll->reference_div = spll->reference_div;
+                        rdev->clock.default_sclk =
+                            radeon_legacy_get_engine_clock(rdev);
+                        rdev->clock.default_mclk =
+                            radeon_legacy_get_memory_clock(rdev);
+                }
+        }
+
+        /* pixel clocks */
+        if (ASIC_IS_AVIVO(rdev)) {
+                p1pll->min_post_div = 2;
+                p1pll->max_post_div = 0x7f;
+                p1pll->min_frac_feedback_div = 0;
+                p1pll->max_frac_feedback_div = 9;
+                p2pll->min_post_div = 2;
+                p2pll->max_post_div = 0x7f;
+                p2pll->min_frac_feedback_div = 0;
+                p2pll->max_frac_feedback_div = 9;
+        } else {
+                p1pll->min_post_div = 1;
+                p1pll->max_post_div = 16;
+                p1pll->min_frac_feedback_div = 0;
+                p1pll->max_frac_feedback_div = 0;
+                p2pll->min_post_div = 1;
+                p2pll->max_post_div = 12;
+                p2pll->min_frac_feedback_div = 0;
+                p2pll->max_frac_feedback_div = 0;
+        }
+
+        p1pll->min_ref_div = 2;
+        p1pll->max_ref_div = 0x3ff;
+        p1pll->min_feedback_div = 4;
+        p1pll->max_feedback_div = 0x7ff;
+        p1pll->best_vco = 0;
+
+        p2pll->min_ref_div = 2;
+        p2pll->max_ref_div = 0x3ff;
+        p2pll->min_feedback_div = 4;
+        p2pll->max_feedback_div = 0x7ff;
+        p2pll->best_vco = 0;
+
+        /* system clock */
+        spll->min_post_div = 1;
+        spll->max_post_div = 1;
+        spll->min_ref_div = 2;
+        spll->max_ref_div = 0xff;
+        spll->min_feedback_div = 4;
+        spll->max_feedback_div = 0xff;
+        spll->best_vco = 0;
+
+        /* memory clock */
+        mpll->min_post_div = 1;
+        mpll->max_post_div = 1;
+        mpll->min_ref_div = 2;
+        mpll->max_ref_div = 0xff;
+        mpll->min_feedback_div = 4;
+        mpll->max_feedback_div = 0xff;
+        mpll->best_vco = 0;
+
+}
+
+/* 10 khz */
+static uint32_t calc_eng_mem_clock(struct radeon_device *rdev,
+                                   uint32_t req_clock,
+                                   int *fb_div, int *post_div)
+{
+        struct radeon_pll *spll = &rdev->clock.spll;
+        int ref_div = spll->reference_div;
+
+        if (!ref_div)
+                ref_div =
+                    RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) &
+                    RADEON_M_SPLL_REF_DIV_MASK;
+
+        if (req_clock < 15000) {
+                *post_div = 8;
+                req_clock *= 8;
+        } else if (req_clock < 30000) {
+                *post_div = 4;
+                req_clock *= 4;
+        } else if (req_clock < 60000) {
+                *post_div = 2;
+                req_clock *= 2;
+        } else
+                *post_div = 1;
+
+        req_clock *= ref_div;
+        req_clock += spll->reference_freq;
+        req_clock /= (2 * spll->reference_freq);
+
+        *fb_div = req_clock & 0xff;
+
+        req_clock = (req_clock & 0xffff) << 1;
+        req_clock *= spll->reference_freq;
+        req_clock /= ref_div;
+        req_clock /= *post_div;
+
+        return req_clock;
+}
+
+/* 10 khz */
+void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
+                                    uint32_t eng_clock)
+{
+        uint32_t tmp;
+        int fb_div, post_div;
+
+        /* XXX: wait for idle */
+
+        eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div);
+
+        tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
+        tmp &= ~RADEON_DONT_USE_XTALIN;
+        WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
+
+        tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+        tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
+        WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+
+        udelay(10);
+
+        tmp = RREG32_PLL(RADEON_SPLL_CNTL);
+        tmp |= RADEON_SPLL_SLEEP;
+        WREG32_PLL(RADEON_SPLL_CNTL, tmp);
+
+        udelay(2);
+
+        tmp = RREG32_PLL(RADEON_SPLL_CNTL);
+        tmp |= RADEON_SPLL_RESET;
+        WREG32_PLL(RADEON_SPLL_CNTL, tmp);
+
+        udelay(200);
+
+        tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
+        tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
+        tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT;
+        WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp);
+
+        /* XXX: verify on different asics */
+        tmp = RREG32_PLL(RADEON_SPLL_CNTL);
+        tmp &= ~RADEON_SPLL_PVG_MASK;
+        if ((eng_clock * post_div) >= 90000)
+                tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT);
+        else
+                tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT);
+        WREG32_PLL(RADEON_SPLL_CNTL, tmp);
+
+        tmp = RREG32_PLL(RADEON_SPLL_CNTL);
+        tmp &= ~RADEON_SPLL_SLEEP;
+        WREG32_PLL(RADEON_SPLL_CNTL, tmp);
+
+        udelay(2);
+
+        tmp = RREG32_PLL(RADEON_SPLL_CNTL);
+        tmp &= ~RADEON_SPLL_RESET;
+        WREG32_PLL(RADEON_SPLL_CNTL, tmp);
+
+        udelay(200);
+
+        tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+        tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
+        switch (post_div) {
+        case 1:
+        default:
+                tmp |= 1;
+                break;
+        case 2:
+                tmp |= 2;
+                break;
+        case 4:
+                tmp |= 3;
+                break;
+        case 8:
+                tmp |= 4;
+                break;
+        }
+        WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+
+        udelay(20);
+
+        tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
+        tmp |= RADEON_DONT_USE_XTALIN;
+        WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
+
+        udelay(10);
+}
+
+void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
+{
+        uint32_t tmp;
+
+        if (enable) {
+                if (rdev->flags & RADEON_SINGLE_CRTC) {
+                        tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+                        if ((RREG32(RADEON_CONFIG_CNTL) &
+                             RADEON_CFG_ATI_REV_ID_MASK) >
+                            RADEON_CFG_ATI_REV_A13) {
+                                tmp &=
+                                    ~(RADEON_SCLK_FORCE_CP |
+                                      RADEON_SCLK_FORCE_RB);
+                        }
+                        tmp &=
+                            ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
+                              RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE |
+                              RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE |
+                              RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM |
+                              RADEON_SCLK_FORCE_TDM);
+                        WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+                } else if (ASIC_IS_R300(rdev)) {
+                        if ((rdev->family == CHIP_RS400) ||
+                            (rdev->family == CHIP_RS480)) {
+                                tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+                                tmp &=
+                                    ~(RADEON_SCLK_FORCE_DISP2 |
+                                      RADEON_SCLK_FORCE_CP |
+                                      RADEON_SCLK_FORCE_HDP |
+                                      RADEON_SCLK_FORCE_DISP1 |
+                                      RADEON_SCLK_FORCE_TOP |
+                                      RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
+                                      | RADEON_SCLK_FORCE_IDCT |
+                                      RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
+                                      | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
+                                      | R300_SCLK_FORCE_US |
+                                      RADEON_SCLK_FORCE_TV_SCLK |
+                                      R300_SCLK_FORCE_SU |
+                                      RADEON_SCLK_FORCE_OV0);
+                                tmp |= RADEON_DYN_STOP_LAT_MASK;
+                                tmp |=
+                                    RADEON_SCLK_FORCE_TOP |
+                                    RADEON_SCLK_FORCE_VIP;
+                                WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+
+                                tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
+                                tmp &= ~RADEON_SCLK_MORE_FORCEON;
+                                tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
+                                WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
+
+                                tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
+                                tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
+                                        RADEON_PIXCLK_DAC_ALWAYS_ONb);
+                                WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
+
+                                tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
+                                tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
+                                        RADEON_PIX2CLK_DAC_ALWAYS_ONb |
+                                        RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
+                                        R300_DVOCLK_ALWAYS_ONb |
+                                        RADEON_PIXCLK_BLEND_ALWAYS_ONb |
+                                        RADEON_PIXCLK_GV_ALWAYS_ONb |
+                                        R300_PIXCLK_DVO_ALWAYS_ONb |
+                                        RADEON_PIXCLK_LVDS_ALWAYS_ONb |
+                                        RADEON_PIXCLK_TMDS_ALWAYS_ONb |
+                                        R300_PIXCLK_TRANS_ALWAYS_ONb |
+                                        R300_PIXCLK_TVO_ALWAYS_ONb |
+                                        R300_P2G2CLK_ALWAYS_ONb |
+                                        R300_P2G2CLK_ALWAYS_ONb);
+                                WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
+                        } else if (rdev->family >= CHIP_RV350) {
+                                tmp = RREG32_PLL(R300_SCLK_CNTL2);
+                                tmp &= ~(R300_SCLK_FORCE_TCL |
+                                         R300_SCLK_FORCE_GA |
+                                         R300_SCLK_FORCE_CBA);
+                                tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
+                                        R300_SCLK_GA_MAX_DYN_STOP_LAT |
+                                        R300_SCLK_CBA_MAX_DYN_STOP_LAT);
+                                WREG32_PLL(R300_SCLK_CNTL2, tmp);
+
+                                tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+                                tmp &=
+                                    ~(RADEON_SCLK_FORCE_DISP2 |
+                                      RADEON_SCLK_FORCE_CP |
+                                      RADEON_SCLK_FORCE_HDP |
+                                      RADEON_SCLK_FORCE_DISP1 |
+                                      RADEON_SCLK_FORCE_TOP |
+                                      RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP
+                                      | RADEON_SCLK_FORCE_IDCT |
+                                      RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR
+                                      | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX
+                                      | R300_SCLK_FORCE_US |
+                                      RADEON_SCLK_FORCE_TV_SCLK |
+                                      R300_SCLK_FORCE_SU |
+                                      RADEON_SCLK_FORCE_OV0);
+                                tmp |= RADEON_DYN_STOP_LAT_MASK;
+                                WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+
+                                tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
+                                tmp &= ~RADEON_SCLK_MORE_FORCEON;
+                                tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
+                                WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
+
+                                tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
+                                tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
+                                        RADEON_PIXCLK_DAC_ALWAYS_ONb);
+                                WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
+
+                                tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
+                                tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
+                                        RADEON_PIX2CLK_DAC_ALWAYS_ONb |
+                                        RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
+                                        R300_DVOCLK_ALWAYS_ONb |
+                                        RADEON_PIXCLK_BLEND_ALWAYS_ONb |
+                                        RADEON_PIXCLK_GV_ALWAYS_ONb |
+                                        R300_PIXCLK_DVO_ALWAYS_ONb |
+                                        RADEON_PIXCLK_LVDS_ALWAYS_ONb |
+                                        RADEON_PIXCLK_TMDS_ALWAYS_ONb |
+                                        R300_PIXCLK_TRANS_ALWAYS_ONb |
+                                        R300_PIXCLK_TVO_ALWAYS_ONb |
+                                        R300_P2G2CLK_ALWAYS_ONb |
+                                        R300_P2G2CLK_ALWAYS_ONb);
+                                WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
+
+                                tmp = RREG32_PLL(RADEON_MCLK_MISC);
+                                tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
+                                        RADEON_IO_MCLK_DYN_ENABLE);
+                                WREG32_PLL(RADEON_MCLK_MISC, tmp);
+
+                                tmp = RREG32_PLL(RADEON_MCLK_CNTL);
+                                tmp |= (RADEON_FORCEON_MCLKA |
+                                        RADEON_FORCEON_MCLKB);
+
+                                tmp &= ~(RADEON_FORCEON_YCLKA |
+                                         RADEON_FORCEON_YCLKB |
+                                         RADEON_FORCEON_MC);
+
+                                /* Some releases of vbios have set DISABLE_MC_MCLKA
+                                   and DISABLE_MC_MCLKB bits in the vbios table.  Setting these
+                                   bits will cause H/W hang when reading video memory with dynamic clocking
+                                   enabled. */
+                                if ((tmp & R300_DISABLE_MC_MCLKA) &&
+                                    (tmp & R300_DISABLE_MC_MCLKB)) {
+                                        /* If both bits are set, then check the active channels */
+                                        tmp = RREG32_PLL(RADEON_MCLK_CNTL);
+                                        if (rdev->mc.vram_width == 64) {
+                                                if (RREG32(RADEON_MEM_CNTL) &
+                                                    R300_MEM_USE_CD_CH_ONLY)
+                                                        tmp &=
+                                                            ~R300_DISABLE_MC_MCLKB;
+                                                else
+                                                        tmp &=
+                                                            ~R300_DISABLE_MC_MCLKA;
+                                        } else {
+                                                tmp &= ~(R300_DISABLE_MC_MCLKA |
+                                                         R300_DISABLE_MC_MCLKB);
+                                        }
+                                }
+
+                                WREG32_PLL(RADEON_MCLK_CNTL, tmp);
+                        } else {
+                                tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+                                tmp &= ~(R300_SCLK_FORCE_VAP);
+                                tmp |= RADEON_SCLK_FORCE_CP;
+                                WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+                                udelay(15000);
+
+                                tmp = RREG32_PLL(R300_SCLK_CNTL2);
+                                tmp &= ~(R300_SCLK_FORCE_TCL |
+                                         R300_SCLK_FORCE_GA |
+                                         R300_SCLK_FORCE_CBA);
+                                WREG32_PLL(R300_SCLK_CNTL2, tmp);
+                        }
+                } else {
+                        tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
+
+                        tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK |
+                                 RADEON_DISP_DYN_STOP_LAT_MASK |
+                                 RADEON_DYN_STOP_MODE_MASK);
+
+                        tmp |= (RADEON_ENGIN_DYNCLK_MODE |
+                                (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
+                        WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
+                        udelay(15000);
+
+                        tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
+                        tmp |= RADEON_SCLK_DYN_START_CNTL;
+                        WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
+                        udelay(15000);
+
+                        /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
+                           to lockup randomly, leave them as set by BIOS.
+                         */
+                        tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+                        /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */
+                        tmp &= ~RADEON_SCLK_FORCEON_MASK;
+
+                        /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */
+                        if (((rdev->family == CHIP_RV250) &&
+                             ((RREG32(RADEON_CONFIG_CNTL) &
+                               RADEON_CFG_ATI_REV_ID_MASK) <
+                              RADEON_CFG_ATI_REV_A13))
+                            || ((rdev->family == CHIP_RV100)
+                                &&
+                                ((RREG32(RADEON_CONFIG_CNTL) &
+                                  RADEON_CFG_ATI_REV_ID_MASK) <=
+                                 RADEON_CFG_ATI_REV_A13))) {
+                                tmp |= RADEON_SCLK_FORCE_CP;
+                                tmp |= RADEON_SCLK_FORCE_VIP;
+                        }
+
+                        WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+
+                        if ((rdev->family == CHIP_RV200) ||
+                            (rdev->family == CHIP_RV250) ||
+                            (rdev->family == CHIP_RV280)) {
+                                tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
+                                tmp &= ~RADEON_SCLK_MORE_FORCEON;
+
+                                /* RV200::A11 A12 RV250::A11 A12 */
+                                if (((rdev->family == CHIP_RV200) ||
+                                     (rdev->family == CHIP_RV250)) &&
+                                    ((RREG32(RADEON_CONFIG_CNTL) &
+                                      RADEON_CFG_ATI_REV_ID_MASK) <
+                                     RADEON_CFG_ATI_REV_A13)) {
+                                        tmp |= RADEON_SCLK_MORE_FORCEON;
+                                }
+                                WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
+                                udelay(15000);
+                        }
+
+                        /* RV200::A11 A12, RV250::A11 A12 */
+                        if (((rdev->family == CHIP_RV200) ||
+                             (rdev->family == CHIP_RV250)) &&
+                            ((RREG32(RADEON_CONFIG_CNTL) &
+                              RADEON_CFG_ATI_REV_ID_MASK) <
+                             RADEON_CFG_ATI_REV_A13)) {
+                                tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
+                                tmp |= RADEON_TCL_BYPASS_DISABLE;
+                                WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
+                        }
+                        udelay(15000);
+
+                        /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
+                        tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
+                        tmp |= (RADEON_PIX2CLK_ALWAYS_ONb |
+                                RADEON_PIX2CLK_DAC_ALWAYS_ONb |
+                                RADEON_PIXCLK_BLEND_ALWAYS_ONb |
+                                RADEON_PIXCLK_GV_ALWAYS_ONb |
+                                RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
+                                RADEON_PIXCLK_LVDS_ALWAYS_ONb |
+                                RADEON_PIXCLK_TMDS_ALWAYS_ONb);
+
+                        WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
+                        udelay(15000);
+
+                        tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
+                        tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
+                                RADEON_PIXCLK_DAC_ALWAYS_ONb);
+
+                        WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
+                        udelay(15000);
+                }
+        } else {
+                /* Turn everything OFF (ForceON to everything) */
+                if (rdev->flags & RADEON_SINGLE_CRTC) {
+                        tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+                        tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP |
+                                RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP
+                                | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE |
+                                RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
+                                RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB |
+                                RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM |
+                                RADEON_SCLK_FORCE_RB);
+                        WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+                } else if ((rdev->family == CHIP_RS400) ||
+                           (rdev->family == CHIP_RS480)) {
+                        tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+                        tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
+                                RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
+                                | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
+                                R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
+                                RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
+                                R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
+                                R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
+                                R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
+                        WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+
+                        tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
+                        tmp |= RADEON_SCLK_MORE_FORCEON;
+                        WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
+
+                        tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
+                        tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
+                                 RADEON_PIXCLK_DAC_ALWAYS_ONb |
+                                 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
+                        WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
+
+                        tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
+                        tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
+                                 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
+                                 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
+                                 R300_DVOCLK_ALWAYS_ONb |
+                                 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
+                                 RADEON_PIXCLK_GV_ALWAYS_ONb |
+                                 R300_PIXCLK_DVO_ALWAYS_ONb |
+                                 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
+                                 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
+                                 R300_PIXCLK_TRANS_ALWAYS_ONb |
+                                 R300_PIXCLK_TVO_ALWAYS_ONb |
+                                 R300_P2G2CLK_ALWAYS_ONb |
+                                 R300_P2G2CLK_ALWAYS_ONb |
+                                 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
+                        WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
+                } else if (rdev->family >= CHIP_RV350) {
+                        /* for RV350/M10, no delays are required. */
+                        tmp = RREG32_PLL(R300_SCLK_CNTL2);
+                        tmp |= (R300_SCLK_FORCE_TCL |
+                                R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA);
+                        WREG32_PLL(R300_SCLK_CNTL2, tmp);
+
+                        tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+                        tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP |
+                                RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1
+                                | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 |
+                                R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT |
+                                RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
+                                R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
+                                R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK |
+                                R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0);
+                        WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+
+                        tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
+                        tmp |= RADEON_SCLK_MORE_FORCEON;
+                        WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
+
+                        tmp = RREG32_PLL(RADEON_MCLK_CNTL);
+                        tmp |= (RADEON_FORCEON_MCLKA |
+                                RADEON_FORCEON_MCLKB |
+                                RADEON_FORCEON_YCLKA |
+                                RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC);
+                        WREG32_PLL(RADEON_MCLK_CNTL, tmp);
+
+                        tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
+                        tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
+                                 RADEON_PIXCLK_DAC_ALWAYS_ONb |
+                                 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF);
+                        WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
+
+                        tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
+                        tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
+                                 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
+                                 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
+                                 R300_DVOCLK_ALWAYS_ONb |
+                                 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
+                                 RADEON_PIXCLK_GV_ALWAYS_ONb |
+                                 R300_PIXCLK_DVO_ALWAYS_ONb |
+                                 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
+                                 RADEON_PIXCLK_TMDS_ALWAYS_ONb |
+                                 R300_PIXCLK_TRANS_ALWAYS_ONb |
+                                 R300_PIXCLK_TVO_ALWAYS_ONb |
+                                 R300_P2G2CLK_ALWAYS_ONb |
+                                 R300_P2G2CLK_ALWAYS_ONb |
+                                 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
+                        WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
+                } else {
+                        tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+                        tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
+                        tmp |= RADEON_SCLK_FORCE_SE;
+
+                        if (rdev->flags & RADEON_SINGLE_CRTC) {
+                                tmp |= (RADEON_SCLK_FORCE_RB |
+                                        RADEON_SCLK_FORCE_TDM |
+                                        RADEON_SCLK_FORCE_TAM |
+                                        RADEON_SCLK_FORCE_PB |
+                                        RADEON_SCLK_FORCE_RE |
+                                        RADEON_SCLK_FORCE_VIP |
+                                        RADEON_SCLK_FORCE_IDCT |
+                                        RADEON_SCLK_FORCE_TOP |
+                                        RADEON_SCLK_FORCE_DISP1 |
+                                        RADEON_SCLK_FORCE_DISP2 |
+                                        RADEON_SCLK_FORCE_HDP);
+                        } else if ((rdev->family == CHIP_R300) ||
+                                   (rdev->family == CHIP_R350)) {
+                                tmp |= (RADEON_SCLK_FORCE_HDP |
+                                        RADEON_SCLK_FORCE_DISP1 |
+                                        RADEON_SCLK_FORCE_DISP2 |
+                                        RADEON_SCLK_FORCE_TOP |
+                                        RADEON_SCLK_FORCE_IDCT |
+                                        RADEON_SCLK_FORCE_VIP);
+                        }
+                        WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+
+                        udelay(16000);
+
+                        if ((rdev->family == CHIP_R300) ||
+                            (rdev->family == CHIP_R350)) {
+                                tmp = RREG32_PLL(R300_SCLK_CNTL2);
+                                tmp |= (R300_SCLK_FORCE_TCL |
+                                        R300_SCLK_FORCE_GA |
+                                        R300_SCLK_FORCE_CBA);
+                                WREG32_PLL(R300_SCLK_CNTL2, tmp);
+                                udelay(16000);
+                        }
+
+                        if (rdev->flags & RADEON_IS_IGP) {
+                                tmp = RREG32_PLL(RADEON_MCLK_CNTL);
+                                tmp &= ~(RADEON_FORCEON_MCLKA |
+                                         RADEON_FORCEON_YCLKA);
+                                WREG32_PLL(RADEON_MCLK_CNTL, tmp);
+                                udelay(16000);
+                        }
+
+                        if ((rdev->family == CHIP_RV200) ||
+                            (rdev->family == CHIP_RV250) ||
+                            (rdev->family == CHIP_RV280)) {
+                                tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
+                                tmp |= RADEON_SCLK_MORE_FORCEON;
+                                WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
+                                udelay(16000);
+                        }
+
+                        tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
+                        tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb |
+                                 RADEON_PIX2CLK_DAC_ALWAYS_ONb |
+                                 RADEON_PIXCLK_BLEND_ALWAYS_ONb |
+                                 RADEON_PIXCLK_GV_ALWAYS_ONb |
+                                 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
+                                 RADEON_PIXCLK_LVDS_ALWAYS_ONb |
+                                 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
+
+                        WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
+                        udelay(16000);
+
+                        tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
+                        tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
+                                 RADEON_PIXCLK_DAC_ALWAYS_ONb);
+                        WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
+                }
+        }
+}
+
+static void radeon_apply_clock_quirks(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        /* XXX make sure engine is idle */
+
+        if (rdev->family < CHIP_RS600) {
+                tmp = RREG32_PLL(RADEON_SCLK_CNTL);
+                if (ASIC_IS_R300(rdev) || ASIC_IS_RV100(rdev))
+                        tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
+                if ((rdev->family == CHIP_RV250)
+                    || (rdev->family == CHIP_RV280))
+                        tmp |=
+                            RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2;
+                if ((rdev->family == CHIP_RV350)
+                    || (rdev->family == CHIP_RV380))
+                        tmp |= R300_SCLK_FORCE_VAP;
+                if (rdev->family == CHIP_R420)
+                        tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX;
+                WREG32_PLL(RADEON_SCLK_CNTL, tmp);
+        } else if (rdev->family < CHIP_R600) {
+                tmp = RREG32_PLL(AVIVO_CP_DYN_CNTL);
+                tmp |= AVIVO_CP_FORCEON;
+                WREG32_PLL(AVIVO_CP_DYN_CNTL, tmp);
+
+                tmp = RREG32_PLL(AVIVO_E2_DYN_CNTL);
+                tmp |= AVIVO_E2_FORCEON;
+                WREG32_PLL(AVIVO_E2_DYN_CNTL, tmp);
+
+                tmp = RREG32_PLL(AVIVO_IDCT_DYN_CNTL);
+                tmp |= AVIVO_IDCT_FORCEON;
+                WREG32_PLL(AVIVO_IDCT_DYN_CNTL, tmp);
+        }
+}
+
+int radeon_static_clocks_init(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+
+        /* XXX make sure engine is idle */
+
+        if (radeon_dynclks != -1) {
+                if (radeon_dynclks)
+                        radeon_set_clock_gating(rdev, 1);
+        }
+        radeon_apply_clock_quirks(rdev);
+        return 0;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
new file mode 100644
index 000000000000..06e8038bc4ac
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -0,0 +1,2481 @@
+/*
+ * Copyright 2004 ATI Technologies Inc., Markham, Ontario
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+#include "atom.h"
+
+#ifdef CONFIG_PPC_PMAC
+/* not sure which of these are needed */
+#include <asm/machdep.h>
+#include <asm/pmac_feature.h>
+#include <asm/prom.h>
+#include <asm/pci-bridge.h>
+#endif /* CONFIG_PPC_PMAC */
+
+/* from radeon_encoder.c */
+extern uint32_t
+radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
+                      uint8_t dac);
+extern void radeon_link_encoder_connector(struct drm_device *dev);
+
+/* from radeon_connector.c */
+extern void
+radeon_add_legacy_connector(struct drm_device *dev,
+                            uint32_t connector_id,
+                            uint32_t supported_device,
+                            int connector_type,
+                            struct radeon_i2c_bus_rec *i2c_bus);
+
+/* from radeon_legacy_encoder.c */
+extern void
+radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
+                          uint32_t supported_device);
+
+/* old legacy ATI BIOS routines */
+
+/* COMBIOS table offsets */
+enum radeon_combios_table_offset {
+        /* absolute offset tables */
+        COMBIOS_ASIC_INIT_1_TABLE,
+        COMBIOS_BIOS_SUPPORT_TABLE,
+        COMBIOS_DAC_PROGRAMMING_TABLE,
+        COMBIOS_MAX_COLOR_DEPTH_TABLE,
+        COMBIOS_CRTC_INFO_TABLE,
+        COMBIOS_PLL_INFO_TABLE,
+        COMBIOS_TV_INFO_TABLE,
+        COMBIOS_DFP_INFO_TABLE,
+        COMBIOS_HW_CONFIG_INFO_TABLE,
+        COMBIOS_MULTIMEDIA_INFO_TABLE,
+        COMBIOS_TV_STD_PATCH_TABLE,
+        COMBIOS_LCD_INFO_TABLE,
+        COMBIOS_MOBILE_INFO_TABLE,
+        COMBIOS_PLL_INIT_TABLE,
+        COMBIOS_MEM_CONFIG_TABLE,
+        COMBIOS_SAVE_MASK_TABLE,
+        COMBIOS_HARDCODED_EDID_TABLE,
+        COMBIOS_ASIC_INIT_2_TABLE,
+        COMBIOS_CONNECTOR_INFO_TABLE,
+        COMBIOS_DYN_CLK_1_TABLE,
+        COMBIOS_RESERVED_MEM_TABLE,
+        COMBIOS_EXT_TMDS_INFO_TABLE,
+        COMBIOS_MEM_CLK_INFO_TABLE,
+        COMBIOS_EXT_DAC_INFO_TABLE,
+        COMBIOS_MISC_INFO_TABLE,
+        COMBIOS_CRT_INFO_TABLE,
+        COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
+        COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
+        COMBIOS_FAN_SPEED_INFO_TABLE,
+        COMBIOS_OVERDRIVE_INFO_TABLE,
+        COMBIOS_OEM_INFO_TABLE,
+        COMBIOS_DYN_CLK_2_TABLE,
+        COMBIOS_POWER_CONNECTOR_INFO_TABLE,
+        COMBIOS_I2C_INFO_TABLE,
+        /* relative offset tables */
+        COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
+        COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
+        COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
+        COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
+        COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
+        COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
+        COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
+        COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
+        COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
+        COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
+        COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
+};
+
+enum radeon_combios_ddc {
+        DDC_NONE_DETECTED,
+        DDC_MONID,
+        DDC_DVI,
+        DDC_VGA,
+        DDC_CRT2,
+        DDC_LCD,
+        DDC_GPIO,
+};
+
+enum radeon_combios_connector {
+        CONNECTOR_NONE_LEGACY,
+        CONNECTOR_PROPRIETARY_LEGACY,
+        CONNECTOR_CRT_LEGACY,
+        CONNECTOR_DVI_I_LEGACY,
+        CONNECTOR_DVI_D_LEGACY,
+        CONNECTOR_CTV_LEGACY,
+        CONNECTOR_STV_LEGACY,
+        CONNECTOR_UNSUPPORTED_LEGACY
+};
+
+const int legacy_connector_convert[] = {
+        DRM_MODE_CONNECTOR_Unknown,
+        DRM_MODE_CONNECTOR_DVID,
+        DRM_MODE_CONNECTOR_VGA,
+        DRM_MODE_CONNECTOR_DVII,
+        DRM_MODE_CONNECTOR_DVID,
+        DRM_MODE_CONNECTOR_Composite,
+        DRM_MODE_CONNECTOR_SVIDEO,
+        DRM_MODE_CONNECTOR_Unknown,
+};
+
+static uint16_t combios_get_table_offset(struct drm_device *dev,
+                                         enum radeon_combios_table_offset table)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        int rev;
+        uint16_t offset = 0, check_offset;
+
+        switch (table) {
+                /* absolute offset tables */
+        case COMBIOS_ASIC_INIT_1_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0xc);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_BIOS_SUPPORT_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x14);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_DAC_PROGRAMMING_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_MAX_COLOR_DEPTH_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_CRTC_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_PLL_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x30);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_TV_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x32);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_DFP_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x34);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_HW_CONFIG_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x36);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_MULTIMEDIA_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x38);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_TV_STD_PATCH_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_LCD_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x40);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_MOBILE_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x42);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_PLL_INIT_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x46);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_MEM_CONFIG_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x48);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_SAVE_MASK_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_HARDCODED_EDID_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_ASIC_INIT_2_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_CONNECTOR_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x50);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_DYN_CLK_1_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x52);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_RESERVED_MEM_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x54);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_EXT_TMDS_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x58);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_MEM_CLK_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_EXT_DAC_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_MISC_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_CRT_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x60);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x62);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x64);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_FAN_SPEED_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x66);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_OVERDRIVE_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x68);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_OEM_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_DYN_CLK_2_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+        case COMBIOS_I2C_INFO_TABLE:
+                check_offset = RBIOS16(rdev->bios_header_start + 0x70);
+                if (check_offset)
+                        offset = check_offset;
+                break;
+                /* relative offset tables */
+        case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
+                check_offset =
+                    combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
+                if (check_offset) {
+                        rev = RBIOS8(check_offset);
+                        if (rev > 0) {
+                                check_offset = RBIOS16(check_offset + 0x3);
+                                if (check_offset)
+                                        offset = check_offset;
+                        }
+                }
+                break;
+        case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
+                check_offset =
+                    combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
+                if (check_offset) {
+                        rev = RBIOS8(check_offset);
+                        if (rev > 0) {
+                                check_offset = RBIOS16(check_offset + 0x5);
+                                if (check_offset)
+                                        offset = check_offset;
+                        }
+                }
+                break;
+        case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
+                check_offset =
+                    combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
+                if (check_offset) {
+                        rev = RBIOS8(check_offset);
+                        if (rev > 0) {
+                                check_offset = RBIOS16(check_offset + 0x7);
+                                if (check_offset)
+                                        offset = check_offset;
+                        }
+                }
+                break;
+        case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
+                check_offset =
+                    combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
+                if (check_offset) {
+                        rev = RBIOS8(check_offset);
+                        if (rev == 2) {
+                                check_offset = RBIOS16(check_offset + 0x9);
+                                if (check_offset)
+                                        offset = check_offset;
+                        }
+                }
+                break;
+        case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
+                check_offset =
+                    combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
+                if (check_offset) {
+                        while (RBIOS8(check_offset++));
+                        check_offset += 2;
+                        if (check_offset)
+                                offset = check_offset;
+                }
+                break;
+        case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
+                check_offset =
+                    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
+                if (check_offset) {
+                        check_offset = RBIOS16(check_offset + 0x11);
+                        if (check_offset)
+                                offset = check_offset;
+                }
+                break;
+        case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
+                check_offset =
+                    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
+                if (check_offset) {
+                        check_offset = RBIOS16(check_offset + 0x13);
+                        if (check_offset)
+                                offset = check_offset;
+                }
+                break;
+        case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
+                check_offset =
+                    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
+                if (check_offset) {
+                        check_offset = RBIOS16(check_offset + 0x15);
+                        if (check_offset)
+                                offset = check_offset;
+                }
+                break;
+        case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
+                check_offset =
+                    combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
+                if (check_offset) {
+                        check_offset = RBIOS16(check_offset + 0x17);
+                        if (check_offset)
+                                offset = check_offset;
+                }
+                break;
+        case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
+                check_offset =
+                    combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
+                if (check_offset) {
+                        check_offset = RBIOS16(check_offset + 0x2);
+                        if (check_offset)
+                                offset = check_offset;
+                }
+                break;
+        case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
+                check_offset =
+                    combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
+                if (check_offset) {
+                        check_offset = RBIOS16(check_offset + 0x4);
+                        if (check_offset)
+                                offset = check_offset;
+                }
+                break;
+        default:
+                break;
+        }
+
+        return offset;
+
+}
+
+struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
+{
+        struct radeon_i2c_bus_rec i2c;
+
+        i2c.mask_clk_mask = RADEON_GPIO_EN_1;
+        i2c.mask_data_mask = RADEON_GPIO_EN_0;
+        i2c.a_clk_mask = RADEON_GPIO_A_1;
+        i2c.a_data_mask = RADEON_GPIO_A_0;
+        i2c.put_clk_mask = RADEON_GPIO_EN_1;
+        i2c.put_data_mask = RADEON_GPIO_EN_0;
+        i2c.get_clk_mask = RADEON_GPIO_Y_1;
+        i2c.get_data_mask = RADEON_GPIO_Y_0;
+        if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
+            (ddc_line == RADEON_MDGPIO_EN_REG)) {
+                i2c.mask_clk_reg = ddc_line;
+                i2c.mask_data_reg = ddc_line;
+                i2c.a_clk_reg = ddc_line;
+                i2c.a_data_reg = ddc_line;
+                i2c.put_clk_reg = ddc_line;
+                i2c.put_data_reg = ddc_line;
+                i2c.get_clk_reg = ddc_line + 4;
+                i2c.get_data_reg = ddc_line + 4;
+        } else {
+                i2c.mask_clk_reg = ddc_line;
+                i2c.mask_data_reg = ddc_line;
+                i2c.a_clk_reg = ddc_line;
+                i2c.a_data_reg = ddc_line;
+                i2c.put_clk_reg = ddc_line;
+                i2c.put_data_reg = ddc_line;
+                i2c.get_clk_reg = ddc_line;
+                i2c.get_data_reg = ddc_line;
+        }
+
+        if (ddc_line)
+                i2c.valid = true;
+        else
+                i2c.valid = false;
+
+        return i2c;
+}
+
+bool radeon_combios_get_clock_info(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        uint16_t pll_info;
+        struct radeon_pll *p1pll = &rdev->clock.p1pll;
+        struct radeon_pll *p2pll = &rdev->clock.p2pll;
+        struct radeon_pll *spll = &rdev->clock.spll;
+        struct radeon_pll *mpll = &rdev->clock.mpll;
+        int8_t rev;
+        uint16_t sclk, mclk;
+
+        if (rdev->bios == NULL)
+                return NULL;
+
+        pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
+        if (pll_info) {
+                rev = RBIOS8(pll_info);
+
+                /* pixel clocks */
+                p1pll->reference_freq = RBIOS16(pll_info + 0xe);
+                p1pll->reference_div = RBIOS16(pll_info + 0x10);
+                p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
+                p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
+
+                if (rev > 9) {
+                        p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
+                        p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
+                } else {
+                        p1pll->pll_in_min = 40;
+                        p1pll->pll_in_max = 500;
+                }
+                *p2pll = *p1pll;
+
+                /* system clock */
+                spll->reference_freq = RBIOS16(pll_info + 0x1a);
+                spll->reference_div = RBIOS16(pll_info + 0x1c);
+                spll->pll_out_min = RBIOS32(pll_info + 0x1e);
+                spll->pll_out_max = RBIOS32(pll_info + 0x22);
+
+                if (rev > 10) {
+                        spll->pll_in_min = RBIOS32(pll_info + 0x48);
+                        spll->pll_in_max = RBIOS32(pll_info + 0x4c);
+                } else {
+                        /* ??? */
+                        spll->pll_in_min = 40;
+                        spll->pll_in_max = 500;
+                }
+
+                /* memory clock */
+                mpll->reference_freq = RBIOS16(pll_info + 0x26);
+                mpll->reference_div = RBIOS16(pll_info + 0x28);
+                mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
+                mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
+
+                if (rev > 10) {
+                        mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
+                        mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
+                } else {
+                        /* ??? */
+                        mpll->pll_in_min = 40;
+                        mpll->pll_in_max = 500;
+                }
+
+                /* default sclk/mclk */
+                sclk = RBIOS16(pll_info + 0xa);
+                mclk = RBIOS16(pll_info + 0x8);
+                if (sclk == 0)
+                        sclk = 200 * 100;
+                if (mclk == 0)
+                        mclk = 200 * 100;
+
+                rdev->clock.default_sclk = sclk;
+                rdev->clock.default_mclk = mclk;
+
+                return true;
+        }
+        return false;
+}
+
+struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
+                                                                       radeon_encoder
+                                                                       *encoder)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint16_t dac_info;
+        uint8_t rev, bg, dac;
+        struct radeon_encoder_primary_dac *p_dac = NULL;
+
+        if (rdev->bios == NULL)
+                return NULL;
+
+        /* check CRT table */
+        dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
+        if (dac_info) {
+                p_dac =
+                    kzalloc(sizeof(struct radeon_encoder_primary_dac),
+                            GFP_KERNEL);
+
+                if (!p_dac)
+                        return NULL;
+
+                rev = RBIOS8(dac_info) & 0x3;
+                if (rev < 2) {
+                        bg = RBIOS8(dac_info + 0x2) & 0xf;
+                        dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
+                        p_dac->ps2_pdac_adj = (bg << 8) | (dac);
+                } else {
+                        bg = RBIOS8(dac_info + 0x2) & 0xf;
+                        dac = RBIOS8(dac_info + 0x3) & 0xf;
+                        p_dac->ps2_pdac_adj = (bg << 8) | (dac);
+                }
+
+        }
+
+        return p_dac;
+}
+
+static enum radeon_tv_std
+radeon_combios_get_tv_info(struct radeon_encoder *encoder)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint16_t tv_info;
+        enum radeon_tv_std tv_std = TV_STD_NTSC;
+
+        tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
+        if (tv_info) {
+                if (RBIOS8(tv_info + 6) == 'T') {
+                        switch (RBIOS8(tv_info + 7) & 0xf) {
+                        case 1:
+                                tv_std = TV_STD_NTSC;
+                                DRM_INFO("Default TV standard: NTSC\n");
+                                break;
+                        case 2:
+                                tv_std = TV_STD_PAL;
+                                DRM_INFO("Default TV standard: PAL\n");
+                                break;
+                        case 3:
+                                tv_std = TV_STD_PAL_M;
+                                DRM_INFO("Default TV standard: PAL-M\n");
+                                break;
+                        case 4:
+                                tv_std = TV_STD_PAL_60;
+                                DRM_INFO("Default TV standard: PAL-60\n");
+                                break;
+                        case 5:
+                                tv_std = TV_STD_NTSC_J;
+                                DRM_INFO("Default TV standard: NTSC-J\n");
+                                break;
+                        case 6:
+                                tv_std = TV_STD_SCART_PAL;
+                                DRM_INFO("Default TV standard: SCART-PAL\n");
+                                break;
+                        default:
+                                tv_std = TV_STD_NTSC;
+                                DRM_INFO
+                                    ("Unknown TV standard; defaulting to NTSC\n");
+                                break;
+                        }
+
+                        switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
+                        case 0:
+                                DRM_INFO("29.498928713 MHz TV ref clk\n");
+                                break;
+                        case 1:
+                                DRM_INFO("28.636360000 MHz TV ref clk\n");
+                                break;
+                        case 2:
+                                DRM_INFO("14.318180000 MHz TV ref clk\n");
+                                break;
+                        case 3:
+                                DRM_INFO("27.000000000 MHz TV ref clk\n");
+                                break;
+                        default:
+                                break;
+                        }
+                }
+        }
+        return tv_std;
+}
+
+static const uint32_t default_tvdac_adj[CHIP_LAST] = {
+        0x00000000,             /* r100  */
+        0x00280000,             /* rv100 */
+        0x00000000,             /* rs100 */
+        0x00880000,             /* rv200 */
+        0x00000000,             /* rs200 */
+        0x00000000,             /* r200  */
+        0x00770000,             /* rv250 */
+        0x00290000,             /* rs300 */
+        0x00560000,             /* rv280 */
+        0x00780000,             /* r300  */
+        0x00770000,             /* r350  */
+        0x00780000,             /* rv350 */
+        0x00780000,             /* rv380 */
+        0x01080000,             /* r420  */
+        0x01080000,             /* r423  */
+        0x01080000,             /* rv410 */
+        0x00780000,             /* rs400 */
+        0x00780000,             /* rs480 */
+};
+
+static struct radeon_encoder_tv_dac
+    *radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev)
+{
+        struct radeon_encoder_tv_dac *tv_dac = NULL;
+
+        tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
+
+        if (!tv_dac)
+                return NULL;
+
+        tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
+        if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
+                tv_dac->ps2_tvdac_adj = 0x00880000;
+        tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
+        tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
+
+        return tv_dac;
+}
+
+struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
+                                                             radeon_encoder
+                                                             *encoder)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint16_t dac_info;
+        uint8_t rev, bg, dac;
+        struct radeon_encoder_tv_dac *tv_dac = NULL;
+
+        if (rdev->bios == NULL)
+                return radeon_legacy_get_tv_dac_info_from_table(rdev);
+
+        /* first check TV table */
+        dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
+        if (dac_info) {
+                tv_dac =
+                    kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
+
+                if (!tv_dac)
+                        return NULL;
+
+                rev = RBIOS8(dac_info + 0x3);
+                if (rev > 4) {
+                        bg = RBIOS8(dac_info + 0xc) & 0xf;
+                        dac = RBIOS8(dac_info + 0xd) & 0xf;
+                        tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
+
+                        bg = RBIOS8(dac_info + 0xe) & 0xf;
+                        dac = RBIOS8(dac_info + 0xf) & 0xf;
+                        tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
+
+                        bg = RBIOS8(dac_info + 0x10) & 0xf;
+                        dac = RBIOS8(dac_info + 0x11) & 0xf;
+                        tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
+                } else if (rev > 1) {
+                        bg = RBIOS8(dac_info + 0xc) & 0xf;
+                        dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
+                        tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
+
+                        bg = RBIOS8(dac_info + 0xd) & 0xf;
+                        dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
+                        tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
+
+                        bg = RBIOS8(dac_info + 0xe) & 0xf;
+                        dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
+                        tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
+                }
+
+                tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
+
+        } else {
+                /* then check CRT table */
+                dac_info =
+                    combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
+                if (dac_info) {
+                        tv_dac =
+                            kzalloc(sizeof(struct radeon_encoder_tv_dac),
+                                    GFP_KERNEL);
+
+                        if (!tv_dac)
+                                return NULL;
+
+                        rev = RBIOS8(dac_info) & 0x3;
+                        if (rev < 2) {
+                                bg = RBIOS8(dac_info + 0x3) & 0xf;
+                                dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
+                                tv_dac->ps2_tvdac_adj =
+                                    (bg << 16) | (dac << 20);
+                                tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
+                                tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
+                        } else {
+                                bg = RBIOS8(dac_info + 0x4) & 0xf;
+                                dac = RBIOS8(dac_info + 0x5) & 0xf;
+                                tv_dac->ps2_tvdac_adj =
+                                    (bg << 16) | (dac << 20);
+                                tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
+                                tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
+                        }
+                } else {
+                        DRM_INFO("No TV DAC info found in BIOS\n");
+                        return radeon_legacy_get_tv_dac_info_from_table(rdev);
+                }
+        }
+
+        return tv_dac;
+}
+
+static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
+                                                                         radeon_device
+                                                                         *rdev)
+{
+        struct radeon_encoder_lvds *lvds = NULL;
+        uint32_t fp_vert_stretch, fp_horz_stretch;
+        uint32_t ppll_div_sel, ppll_val;
+
+        lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
+
+        if (!lvds)
+                return NULL;
+
+        fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
+        fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
+
+        if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
+                lvds->native_mode.panel_yres =
+                    ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
+                     RADEON_VERT_PANEL_SHIFT) + 1;
+        else
+                lvds->native_mode.panel_yres =
+                    (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
+
+        if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
+                lvds->native_mode.panel_xres =
+                    (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
+                      RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
+        else
+                lvds->native_mode.panel_xres =
+                    ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
+
+        if ((lvds->native_mode.panel_xres < 640) ||
+            (lvds->native_mode.panel_yres < 480)) {
+                lvds->native_mode.panel_xres = 640;
+                lvds->native_mode.panel_yres = 480;
+        }
+
+        ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
+        ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
+        if ((ppll_val & 0x000707ff) == 0x1bb)
+                lvds->use_bios_dividers = false;
+        else {
+                lvds->panel_ref_divider =
+                    RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
+                lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
+                lvds->panel_fb_divider = ppll_val & 0x7ff;
+
+                if ((lvds->panel_ref_divider != 0) &&
+                    (lvds->panel_fb_divider > 3))
+                        lvds->use_bios_dividers = true;
+        }
+        lvds->panel_vcc_delay = 200;
+
+        DRM_INFO("Panel info derived from registers\n");
+        DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
+                 lvds->native_mode.panel_yres);
+
+        return lvds;
+}
+
+struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
+                                                         *encoder)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint16_t lcd_info;
+        uint32_t panel_setup;
+        char stmp[30];
+        int tmp, i;
+        struct radeon_encoder_lvds *lvds = NULL;
+
+        if (rdev->bios == NULL)
+                return radeon_legacy_get_lvds_info_from_regs(rdev);
+
+        lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
+
+        if (lcd_info) {
+                lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
+
+                if (!lvds)
+                        return NULL;
+
+                for (i = 0; i < 24; i++)
+                        stmp[i] = RBIOS8(lcd_info + i + 1);
+                stmp[24] = 0;
+
+                DRM_INFO("Panel ID String: %s\n", stmp);
+
+                lvds->native_mode.panel_xres = RBIOS16(lcd_info + 0x19);
+                lvds->native_mode.panel_yres = RBIOS16(lcd_info + 0x1b);
+
+                DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres,
+                         lvds->native_mode.panel_yres);
+
+                lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
+                if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
+                        lvds->panel_vcc_delay = 2000;
+
+                lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
+                lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
+                lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
+
+                lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
+                lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
+                lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
+                if ((lvds->panel_ref_divider != 0) &&
+                    (lvds->panel_fb_divider > 3))
+                        lvds->use_bios_dividers = true;
+
+                panel_setup = RBIOS32(lcd_info + 0x39);
+                lvds->lvds_gen_cntl = 0xff00;
+                if (panel_setup & 0x1)
+                        lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
+
+                if ((panel_setup >> 4) & 0x1)
+                        lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
+
+                switch ((panel_setup >> 8) & 0x7) {
+                case 0:
+                        lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
+                        break;
+                case 1:
+                        lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
+                        break;
+                case 2:
+                        lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
+                        break;
+                default:
+                        break;
+                }
+
+                if ((panel_setup >> 16) & 0x1)
+                        lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
+
+                if ((panel_setup >> 17) & 0x1)
+                        lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
+
+                if ((panel_setup >> 18) & 0x1)
+                        lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
+
+                if ((panel_setup >> 23) & 0x1)
+                        lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
+
+                lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
+
+                for (i = 0; i < 32; i++) {
+                        tmp = RBIOS16(lcd_info + 64 + i * 2);
+                        if (tmp == 0)
+                                break;
+
+                        if ((RBIOS16(tmp) == lvds->native_mode.panel_xres) &&
+                            (RBIOS16(tmp + 2) ==
+                             lvds->native_mode.panel_yres)) {
+                                lvds->native_mode.hblank =
+                                    (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
+                                lvds->native_mode.hoverplus =
+                                    (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) -
+                                     1) * 8;
+                                lvds->native_mode.hsync_width =
+                                    RBIOS8(tmp + 23) * 8;
+
+                                lvds->native_mode.vblank = (RBIOS16(tmp + 24) -
+                                                            RBIOS16(tmp + 26));
+                                lvds->native_mode.voverplus =
+                                    ((RBIOS16(tmp + 28) & 0x7ff) -
+                                     RBIOS16(tmp + 26));
+                                lvds->native_mode.vsync_width =
+                                    ((RBIOS16(tmp + 28) & 0xf800) >> 11);
+                                lvds->native_mode.dotclock =
+                                    RBIOS16(tmp + 9) * 10;
+                                lvds->native_mode.flags = 0;
+                        }
+                }
+                encoder->native_mode = lvds->native_mode;
+        } else {
+                DRM_INFO("No panel info found in BIOS\n");
+                return radeon_legacy_get_lvds_info_from_regs(rdev);
+        }
+        return lvds;
+}
+
+static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
+        {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
+        {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
+        {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
+        {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
+        {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
+        {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
+        {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
+        {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
+        {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
+        {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
+        {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
+        {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
+        {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
+        {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
+        {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
+        {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
+        {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RS400 */
+        {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RS480 */
+};
+
+static struct radeon_encoder_int_tmds
+    *radeon_legacy_get_tmds_info_from_table(struct radeon_device *rdev)
+{
+        int i;
+        struct radeon_encoder_int_tmds *tmds = NULL;
+
+        tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
+
+        if (!tmds)
+                return NULL;
+
+        for (i = 0; i < 4; i++) {
+                tmds->tmds_pll[i].value =
+                    default_tmds_pll[rdev->family][i].value;
+                tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
+        }
+
+        return tmds;
+}
+
+struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct
+                                                             radeon_encoder
+                                                             *encoder)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint16_t tmds_info;
+        int i, n;
+        uint8_t ver;
+        struct radeon_encoder_int_tmds *tmds = NULL;
+
+        if (rdev->bios == NULL)
+                return radeon_legacy_get_tmds_info_from_table(rdev);
+
+        tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
+
+        if (tmds_info) {
+                tmds =
+                    kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
+
+                if (!tmds)
+                        return NULL;
+
+                ver = RBIOS8(tmds_info);
+                DRM_INFO("DFP table revision: %d\n", ver);
+                if (ver == 3) {
+                        n = RBIOS8(tmds_info + 5) + 1;
+                        if (n > 4)
+                                n = 4;
+                        for (i = 0; i < n; i++) {
+                                tmds->tmds_pll[i].value =
+                                    RBIOS32(tmds_info + i * 10 + 0x08);
+                                tmds->tmds_pll[i].freq =
+                                    RBIOS16(tmds_info + i * 10 + 0x10);
+                                DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
+                                          tmds->tmds_pll[i].freq,
+                                          tmds->tmds_pll[i].value);
+                        }
+                } else if (ver == 4) {
+                        int stride = 0;
+                        n = RBIOS8(tmds_info + 5) + 1;
+                        if (n > 4)
+                                n = 4;
+                        for (i = 0; i < n; i++) {
+                                tmds->tmds_pll[i].value =
+                                    RBIOS32(tmds_info + stride + 0x08);
+                                tmds->tmds_pll[i].freq =
+                                    RBIOS16(tmds_info + stride + 0x10);
+                                if (i == 0)
+                                        stride += 10;
+                                else
+                                        stride += 6;
+                                DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
+                                          tmds->tmds_pll[i].freq,
+                                          tmds->tmds_pll[i].value);
+                        }
+                }
+        } else
+                DRM_INFO("No TMDS info found in BIOS\n");
+        return tmds;
+}
+
+void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint16_t ext_tmds_info;
+        uint8_t ver;
+
+        if (rdev->bios == NULL)
+                return;
+
+        ext_tmds_info =
+            combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
+        if (ext_tmds_info) {
+                ver = RBIOS8(ext_tmds_info);
+                DRM_INFO("External TMDS Table revision: %d\n", ver);
+                // TODO
+        }
+}
+
+bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_i2c_bus_rec ddc_i2c;
+
+        rdev->mode_info.connector_table = radeon_connector_table;
+        if (rdev->mode_info.connector_table == CT_NONE) {
+#ifdef CONFIG_PPC_PMAC
+                if (machine_is_compatible("PowerBook3,3")) {
+                        /* powerbook with VGA */
+                        rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
+                } else if (machine_is_compatible("PowerBook3,4") ||
+                           machine_is_compatible("PowerBook3,5")) {
+                        /* powerbook with internal tmds */
+                        rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
+                } else if (machine_is_compatible("PowerBook5,1") ||
+                           machine_is_compatible("PowerBook5,2") ||
+                           machine_is_compatible("PowerBook5,3") ||
+                           machine_is_compatible("PowerBook5,4") ||
+                           machine_is_compatible("PowerBook5,5")) {
+                        /* powerbook with external single link tmds (sil164) */
+                        rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
+                } else if (machine_is_compatible("PowerBook5,6")) {
+                        /* powerbook with external dual or single link tmds */
+                        rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
+                } else if (machine_is_compatible("PowerBook5,7") ||
+                           machine_is_compatible("PowerBook5,8") ||
+                           machine_is_compatible("PowerBook5,9")) {
+                        /* PowerBook6,2 ? */
+                        /* powerbook with external dual link tmds (sil1178?) */
+                        rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
+                } else if (machine_is_compatible("PowerBook4,1") ||
+                           machine_is_compatible("PowerBook4,2") ||
+                           machine_is_compatible("PowerBook4,3") ||
+                           machine_is_compatible("PowerBook6,3") ||
+                           machine_is_compatible("PowerBook6,5") ||
+                           machine_is_compatible("PowerBook6,7")) {
+                        /* ibook */
+                        rdev->mode_info.connector_table = CT_IBOOK;
+                } else if (machine_is_compatible("PowerMac4,4")) {
+                        /* emac */
+                        rdev->mode_info.connector_table = CT_EMAC;
+                } else if (machine_is_compatible("PowerMac10,1")) {
+                        /* mini with internal tmds */
+                        rdev->mode_info.connector_table = CT_MINI_INTERNAL;
+                } else if (machine_is_compatible("PowerMac10,2")) {
+                        /* mini with external tmds */
+                        rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
+                } else if (machine_is_compatible("PowerMac12,1")) {
+                        /* PowerMac8,1 ? */
+                        /* imac g5 isight */
+                        rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
+                } else
+#endif /* CONFIG_PPC_PMAC */
+                        rdev->mode_info.connector_table = CT_GENERIC;
+        }
+
+        switch (rdev->mode_info.connector_table) {
+        case CT_GENERIC:
+                DRM_INFO("Connector Table: %d (generic)\n",
+                         rdev->mode_info.connector_table);
+                /* these are the most common settings */
+                if (rdev->flags & RADEON_SINGLE_CRTC) {
+                        /* VGA - primary dac */
+                        ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
+                        radeon_add_legacy_encoder(dev,
+                                                  radeon_get_encoder_id(dev,
+                                                                        ATOM_DEVICE_CRT1_SUPPORT,
+                                                                        1),
+                                                  ATOM_DEVICE_CRT1_SUPPORT);
+                        radeon_add_legacy_connector(dev, 0,
+                                                    ATOM_DEVICE_CRT1_SUPPORT,
+                                                    DRM_MODE_CONNECTOR_VGA,
+                                                    &ddc_i2c);
+                } else if (rdev->flags & RADEON_IS_MOBILITY) {
+                        /* LVDS */
+                        ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
+                        radeon_add_legacy_encoder(dev,
+                                                  radeon_get_encoder_id(dev,
+                                                                        ATOM_DEVICE_LCD1_SUPPORT,
+                                                                        0),
+                                                  ATOM_DEVICE_LCD1_SUPPORT);
+                        radeon_add_legacy_connector(dev, 0,
+                                                    ATOM_DEVICE_LCD1_SUPPORT,
+                                                    DRM_MODE_CONNECTOR_LVDS,
+                                                    &ddc_i2c);
+
+                        /* VGA - primary dac */
+                        ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
+                        radeon_add_legacy_encoder(dev,
+                                                  radeon_get_encoder_id(dev,
+                                                                        ATOM_DEVICE_CRT1_SUPPORT,
+                                                                        1),
+                                                  ATOM_DEVICE_CRT1_SUPPORT);
+                        radeon_add_legacy_connector(dev, 1,
+                                                    ATOM_DEVICE_CRT1_SUPPORT,
+                                                    DRM_MODE_CONNECTOR_VGA,
+                                                    &ddc_i2c);
+                } else {
+                        /* DVI-I - tv dac, int tmds */
+                        ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
+                        radeon_add_legacy_encoder(dev,
+                                                  radeon_get_encoder_id(dev,
+                                                                        ATOM_DEVICE_DFP1_SUPPORT,
+                                                                        0),
+                                                  ATOM_DEVICE_DFP1_SUPPORT);
+                        radeon_add_legacy_encoder(dev,
+                                                  radeon_get_encoder_id(dev,
+                                                                        ATOM_DEVICE_CRT2_SUPPORT,
+                                                                        2),
+                                                  ATOM_DEVICE_CRT2_SUPPORT);
+                        radeon_add_legacy_connector(dev, 0,
+                                                    ATOM_DEVICE_DFP1_SUPPORT |
+                                                    ATOM_DEVICE_CRT2_SUPPORT,
+                                                    DRM_MODE_CONNECTOR_DVII,
+                                                    &ddc_i2c);
+
+                        /* VGA - primary dac */
+                        ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
+                        radeon_add_legacy_encoder(dev,
+                                                  radeon_get_encoder_id(dev,
+                                                                        ATOM_DEVICE_CRT1_SUPPORT,
+                                                                        1),
+                                                  ATOM_DEVICE_CRT1_SUPPORT);
+                        radeon_add_legacy_connector(dev, 1,
+                                                    ATOM_DEVICE_CRT1_SUPPORT,
+                                                    DRM_MODE_CONNECTOR_VGA,
+                                                    &ddc_i2c);
+                }
+
+                if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
+                        /* TV - tv dac */
+                        radeon_add_legacy_encoder(dev,
+                                                  radeon_get_encoder_id(dev,
+                                                                        ATOM_DEVICE_TV1_SUPPORT,
+                                                                        2),
+                                                  ATOM_DEVICE_TV1_SUPPORT);
+                        radeon_add_legacy_connector(dev, 2,
+                                                    ATOM_DEVICE_TV1_SUPPORT,
+                                                    DRM_MODE_CONNECTOR_SVIDEO,
+                                                    &ddc_i2c);
+                }
+                break;
+        case CT_IBOOK:
+                DRM_INFO("Connector Table: %d (ibook)\n",
+                         rdev->mode_info.connector_table);
+                /* LVDS */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_LCD1_SUPPORT,
+                                                                0),
+                                          ATOM_DEVICE_LCD1_SUPPORT);
+                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
+                /* VGA - TV DAC */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_CRT2_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_CRT2_SUPPORT);
+                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
+                /* TV - TV DAC */
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_TV1_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_TV1_SUPPORT);
+                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_SVIDEO,
+                                            &ddc_i2c);
+                break;
+        case CT_POWERBOOK_EXTERNAL:
+                DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
+                         rdev->mode_info.connector_table);
+                /* LVDS */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_LCD1_SUPPORT,
+                                                                0),
+                                          ATOM_DEVICE_LCD1_SUPPORT);
+                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
+                /* DVI-I - primary dac, ext tmds */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_DFP2_SUPPORT,
+                                                                0),
+                                          ATOM_DEVICE_DFP2_SUPPORT);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_CRT1_SUPPORT,
+                                                                1),
+                                          ATOM_DEVICE_CRT1_SUPPORT);
+                radeon_add_legacy_connector(dev, 1,
+                                            ATOM_DEVICE_DFP2_SUPPORT |
+                                            ATOM_DEVICE_CRT1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
+                /* TV - TV DAC */
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_TV1_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_TV1_SUPPORT);
+                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_SVIDEO,
+                                            &ddc_i2c);
+                break;
+        case CT_POWERBOOK_INTERNAL:
+                DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
+                         rdev->mode_info.connector_table);
+                /* LVDS */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_LCD1_SUPPORT,
+                                                                0),
+                                          ATOM_DEVICE_LCD1_SUPPORT);
+                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
+                /* DVI-I - primary dac, int tmds */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_DFP1_SUPPORT,
+                                                                0),
+                                          ATOM_DEVICE_DFP1_SUPPORT);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_CRT1_SUPPORT,
+                                                                1),
+                                          ATOM_DEVICE_CRT1_SUPPORT);
+                radeon_add_legacy_connector(dev, 1,
+                                            ATOM_DEVICE_DFP1_SUPPORT |
+                                            ATOM_DEVICE_CRT1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
+                /* TV - TV DAC */
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_TV1_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_TV1_SUPPORT);
+                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_SVIDEO,
+                                            &ddc_i2c);
+                break;
+        case CT_POWERBOOK_VGA:
+                DRM_INFO("Connector Table: %d (powerbook vga)\n",
+                         rdev->mode_info.connector_table);
+                /* LVDS */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_LCD1_SUPPORT,
+                                                                0),
+                                          ATOM_DEVICE_LCD1_SUPPORT);
+                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
+                /* VGA - primary dac */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_CRT1_SUPPORT,
+                                                                1),
+                                          ATOM_DEVICE_CRT1_SUPPORT);
+                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
+                /* TV - TV DAC */
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_TV1_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_TV1_SUPPORT);
+                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_SVIDEO,
+                                            &ddc_i2c);
+                break;
+        case CT_MINI_EXTERNAL:
+                DRM_INFO("Connector Table: %d (mini external tmds)\n",
+                         rdev->mode_info.connector_table);
+                /* DVI-I - tv dac, ext tmds */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_DFP2_SUPPORT,
+                                                                0),
+                                          ATOM_DEVICE_DFP2_SUPPORT);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_CRT2_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_CRT2_SUPPORT);
+                radeon_add_legacy_connector(dev, 0,
+                                            ATOM_DEVICE_DFP2_SUPPORT |
+                                            ATOM_DEVICE_CRT2_SUPPORT,
+                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
+                /* TV - TV DAC */
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_TV1_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_TV1_SUPPORT);
+                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_SVIDEO,
+                                            &ddc_i2c);
+                break;
+        case CT_MINI_INTERNAL:
+                DRM_INFO("Connector Table: %d (mini internal tmds)\n",
+                         rdev->mode_info.connector_table);
+                /* DVI-I - tv dac, int tmds */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_DFP1_SUPPORT,
+                                                                0),
+                                          ATOM_DEVICE_DFP1_SUPPORT);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_CRT2_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_CRT2_SUPPORT);
+                radeon_add_legacy_connector(dev, 0,
+                                            ATOM_DEVICE_DFP1_SUPPORT |
+                                            ATOM_DEVICE_CRT2_SUPPORT,
+                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
+                /* TV - TV DAC */
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_TV1_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_TV1_SUPPORT);
+                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_SVIDEO,
+                                            &ddc_i2c);
+                break;
+        case CT_IMAC_G5_ISIGHT:
+                DRM_INFO("Connector Table: %d (imac g5 isight)\n",
+                         rdev->mode_info.connector_table);
+                /* DVI-D - int tmds */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_DFP1_SUPPORT,
+                                                                0),
+                                          ATOM_DEVICE_DFP1_SUPPORT);
+                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_DVID, &ddc_i2c);
+                /* VGA - tv dac */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_CRT2_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_CRT2_SUPPORT);
+                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
+                /* TV - TV DAC */
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_TV1_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_TV1_SUPPORT);
+                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_SVIDEO,
+                                            &ddc_i2c);
+                break;
+        case CT_EMAC:
+                DRM_INFO("Connector Table: %d (emac)\n",
+                         rdev->mode_info.connector_table);
+                /* VGA - primary dac */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_CRT1_SUPPORT,
+                                                                1),
+                                          ATOM_DEVICE_CRT1_SUPPORT);
+                radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
+                /* VGA - tv dac */
+                ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_CRT2_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_CRT2_SUPPORT);
+                radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
+                                            DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
+                /* TV - TV DAC */
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_id(dev,
+                                                                ATOM_DEVICE_TV1_SUPPORT,
+                                                                2),
+                                          ATOM_DEVICE_TV1_SUPPORT);
+                radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_SVIDEO,
+                                            &ddc_i2c);
+                break;
+        default:
+                DRM_INFO("Connector table: %d (invalid)\n",
+                         rdev->mode_info.connector_table);
+                return false;
+        }
+
+        radeon_link_encoder_connector(dev);
+
+        return true;
+}
+
+static bool radeon_apply_legacy_quirks(struct drm_device *dev,
+                                       int bios_index,
+                                       enum radeon_combios_connector
+                                       *legacy_connector,
+                                       struct radeon_i2c_bus_rec *ddc_i2c)
+{
+        struct radeon_device *rdev = dev->dev_private;
+
+        /* XPRESS DDC quirks */
+        if ((rdev->family == CHIP_RS400 ||
+             rdev->family == CHIP_RS480) &&
+            ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
+                *ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
+        else if ((rdev->family == CHIP_RS400 ||
+                  rdev->family == CHIP_RS480) &&
+                 ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
+                ddc_i2c->valid = true;
+                ddc_i2c->mask_clk_mask = (0x20 << 8);
+                ddc_i2c->mask_data_mask = 0x80;
+                ddc_i2c->a_clk_mask = (0x20 << 8);
+                ddc_i2c->a_data_mask = 0x80;
+                ddc_i2c->put_clk_mask = (0x20 << 8);
+                ddc_i2c->put_data_mask = 0x80;
+                ddc_i2c->get_clk_mask = (0x20 << 8);
+                ddc_i2c->get_data_mask = 0x80;
+                ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK;
+                ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK;
+                ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A;
+                ddc_i2c->a_data_reg = RADEON_GPIOPAD_A;
+                ddc_i2c->put_clk_reg = RADEON_GPIOPAD_EN;
+                ddc_i2c->put_data_reg = RADEON_GPIOPAD_EN;
+                ddc_i2c->get_clk_reg = RADEON_LCD_GPIO_Y_REG;
+                ddc_i2c->get_data_reg = RADEON_LCD_GPIO_Y_REG;
+        }
+
+        /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
+           one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
+        if (dev->pdev->device == 0x515e &&
+            dev->pdev->subsystem_vendor == 0x1014) {
+                if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
+                    ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
+                        return false;
+        }
+
+        /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
+        if (dev->pdev->device == 0x5159 &&
+            dev->pdev->subsystem_vendor == 0x1002 &&
+            dev->pdev->subsystem_device == 0x013a) {
+                if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
+                        *legacy_connector = CONNECTOR_CRT_LEGACY;
+
+        }
+
+        /* X300 card with extra non-existent DVI port */
+        if (dev->pdev->device == 0x5B60 &&
+            dev->pdev->subsystem_vendor == 0x17af &&
+            dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
+                if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
+                        return false;
+        }
+
+        return true;
+}
+
+bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t conn_info, entry, devices;
+        uint16_t tmp;
+        enum radeon_combios_ddc ddc_type;
+        enum radeon_combios_connector connector;
+        int i = 0;
+        struct radeon_i2c_bus_rec ddc_i2c;
+
+        if (rdev->bios == NULL)
+                return false;
+
+        conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
+        if (conn_info) {
+                for (i = 0; i < 4; i++) {
+                        entry = conn_info + 2 + i * 2;
+
+                        if (!RBIOS16(entry))
+                                break;
+
+                        tmp = RBIOS16(entry);
+
+                        connector = (tmp >> 12) & 0xf;
+
+                        ddc_type = (tmp >> 8) & 0xf;
+                        switch (ddc_type) {
+                        case DDC_MONID:
+                                ddc_i2c =
+                                    combios_setup_i2c_bus(RADEON_GPIO_MONID);
+                                break;
+                        case DDC_DVI:
+                                ddc_i2c =
+                                    combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
+                                break;
+                        case DDC_VGA:
+                                ddc_i2c =
+                                    combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
+                                break;
+                        case DDC_CRT2:
+                                ddc_i2c =
+                                    combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
+                                break;
+                        default:
+                                break;
+                        }
+
+                        radeon_apply_legacy_quirks(dev, i, &connector,
+                                                   &ddc_i2c);
+
+                        switch (connector) {
+                        case CONNECTOR_PROPRIETARY_LEGACY:
+                                if ((tmp >> 4) & 0x1)
+                                        devices = ATOM_DEVICE_DFP2_SUPPORT;
+                                else
+                                        devices = ATOM_DEVICE_DFP1_SUPPORT;
+                                radeon_add_legacy_encoder(dev,
+                                                          radeon_get_encoder_id
+                                                          (dev, devices, 0),
+                                                          devices);
+                                radeon_add_legacy_connector(dev, i, devices,
+                                                            legacy_connector_convert
+                                                            [connector],
+                                                            &ddc_i2c);
+                                break;
+                        case CONNECTOR_CRT_LEGACY:
+                                if (tmp & 0x1) {
+                                        devices = ATOM_DEVICE_CRT2_SUPPORT;
+                                        radeon_add_legacy_encoder(dev,
+                                                                  radeon_get_encoder_id
+                                                                  (dev,
+                                                                   ATOM_DEVICE_CRT2_SUPPORT,
+                                                                   2),
+                                                                  ATOM_DEVICE_CRT2_SUPPORT);
+                                } else {
+                                        devices = ATOM_DEVICE_CRT1_SUPPORT;
+                                        radeon_add_legacy_encoder(dev,
+                                                                  radeon_get_encoder_id
+                                                                  (dev,
+                                                                   ATOM_DEVICE_CRT1_SUPPORT,
+                                                                   1),
+                                                                  ATOM_DEVICE_CRT1_SUPPORT);
+                                }
+                                radeon_add_legacy_connector(dev,
+                                                            i,
+                                                            devices,
+                                                            legacy_connector_convert
+                                                            [connector],
+                                                            &ddc_i2c);
+                                break;
+                        case CONNECTOR_DVI_I_LEGACY:
+                                devices = 0;
+                                if (tmp & 0x1) {
+                                        devices |= ATOM_DEVICE_CRT2_SUPPORT;
+                                        radeon_add_legacy_encoder(dev,
+                                                                  radeon_get_encoder_id
+                                                                  (dev,
+                                                                   ATOM_DEVICE_CRT2_SUPPORT,
+                                                                   2),
+                                                                  ATOM_DEVICE_CRT2_SUPPORT);
+                                } else {
+                                        devices |= ATOM_DEVICE_CRT1_SUPPORT;
+                                        radeon_add_legacy_encoder(dev,
+                                                                  radeon_get_encoder_id
+                                                                  (dev,
+                                                                   ATOM_DEVICE_CRT1_SUPPORT,
+                                                                   1),
+                                                                  ATOM_DEVICE_CRT1_SUPPORT);
+                                }
+                                if ((tmp >> 4) & 0x1) {
+                                        devices |= ATOM_DEVICE_DFP2_SUPPORT;
+                                        radeon_add_legacy_encoder(dev,
+                                                                  radeon_get_encoder_id
+                                                                  (dev,
+                                                                   ATOM_DEVICE_DFP2_SUPPORT,
+                                                                   0),
+                                                                  ATOM_DEVICE_DFP2_SUPPORT);
+                                } else {
+                                        devices |= ATOM_DEVICE_DFP1_SUPPORT;
+                                        radeon_add_legacy_encoder(dev,
+                                                                  radeon_get_encoder_id
+                                                                  (dev,
+                                                                   ATOM_DEVICE_DFP1_SUPPORT,
+                                                                   0),
+                                                                  ATOM_DEVICE_DFP1_SUPPORT);
+                                }
+                                radeon_add_legacy_connector(dev,
+                                                            i,
+                                                            devices,
+                                                            legacy_connector_convert
+                                                            [connector],
+                                                            &ddc_i2c);
+                                break;
+                        case CONNECTOR_DVI_D_LEGACY:
+                                if ((tmp >> 4) & 0x1)
+                                        devices = ATOM_DEVICE_DFP2_SUPPORT;
+                                else
+                                        devices = ATOM_DEVICE_DFP1_SUPPORT;
+                                radeon_add_legacy_encoder(dev,
+                                                          radeon_get_encoder_id
+                                                          (dev, devices, 0),
+                                                          devices);
+                                radeon_add_legacy_connector(dev, i, devices,
+                                                            legacy_connector_convert
+                                                            [connector],
+                                                            &ddc_i2c);
+                                break;
+                        case CONNECTOR_CTV_LEGACY:
+                        case CONNECTOR_STV_LEGACY:
+                                radeon_add_legacy_encoder(dev,
+                                                          radeon_get_encoder_id
+                                                          (dev,
+                                                           ATOM_DEVICE_TV1_SUPPORT,
+                                                           2),
+                                                          ATOM_DEVICE_TV1_SUPPORT);
+                                radeon_add_legacy_connector(dev, i,
+                                                            ATOM_DEVICE_TV1_SUPPORT,
+                                                            legacy_connector_convert
+                                                            [connector],
+                                                            &ddc_i2c);
+                                break;
+                        default:
+                                DRM_ERROR("Unknown connector type: %d\n",
+                                          connector);
+                                continue;
+                        }
+
+                }
+        } else {
+                uint16_t tmds_info =
+                    combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
+                if (tmds_info) {
+                        DRM_DEBUG("Found DFP table, assuming DVI connector\n");
+
+                        radeon_add_legacy_encoder(dev,
+                                                  radeon_get_encoder_id(dev,
+                                                                        ATOM_DEVICE_CRT1_SUPPORT,
+                                                                        1),
+                                                  ATOM_DEVICE_CRT1_SUPPORT);
+                        radeon_add_legacy_encoder(dev,
+                                                  radeon_get_encoder_id(dev,
+                                                                        ATOM_DEVICE_DFP1_SUPPORT,
+                                                                        0),
+                                                  ATOM_DEVICE_DFP1_SUPPORT);
+
+                        ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
+                        radeon_add_legacy_connector(dev,
+                                                    0,
+                                                    ATOM_DEVICE_CRT1_SUPPORT |
+                                                    ATOM_DEVICE_DFP1_SUPPORT,
+                                                    DRM_MODE_CONNECTOR_DVII,
+                                                    &ddc_i2c);
+                } else {
+                        DRM_DEBUG("No connector info found\n");
+                        return false;
+                }
+        }
+
+        if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
+                uint16_t lcd_info =
+                    combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
+                if (lcd_info) {
+                        uint16_t lcd_ddc_info =
+                            combios_get_table_offset(dev,
+                                                     COMBIOS_LCD_DDC_INFO_TABLE);
+
+                        radeon_add_legacy_encoder(dev,
+                                                  radeon_get_encoder_id(dev,
+                                                                        ATOM_DEVICE_LCD1_SUPPORT,
+                                                                        0),
+                                                  ATOM_DEVICE_LCD1_SUPPORT);
+
+                        if (lcd_ddc_info) {
+                                ddc_type = RBIOS8(lcd_ddc_info + 2);
+                                switch (ddc_type) {
+                                case DDC_MONID:
+                                        ddc_i2c =
+                                            combios_setup_i2c_bus
+                                            (RADEON_GPIO_MONID);
+                                        break;
+                                case DDC_DVI:
+                                        ddc_i2c =
+                                            combios_setup_i2c_bus
+                                            (RADEON_GPIO_DVI_DDC);
+                                        break;
+                                case DDC_VGA:
+                                        ddc_i2c =
+                                            combios_setup_i2c_bus
+                                            (RADEON_GPIO_VGA_DDC);
+                                        break;
+                                case DDC_CRT2:
+                                        ddc_i2c =
+                                            combios_setup_i2c_bus
+                                            (RADEON_GPIO_CRT2_DDC);
+                                        break;
+                                case DDC_LCD:
+                                        ddc_i2c =
+                                            combios_setup_i2c_bus
+                                            (RADEON_LCD_GPIO_MASK);
+                                        ddc_i2c.mask_clk_mask =
+                                            RBIOS32(lcd_ddc_info + 3);
+                                        ddc_i2c.mask_data_mask =
+                                            RBIOS32(lcd_ddc_info + 7);
+                                        ddc_i2c.a_clk_mask =
+                                            RBIOS32(lcd_ddc_info + 3);
+                                        ddc_i2c.a_data_mask =
+                                            RBIOS32(lcd_ddc_info + 7);
+                                        ddc_i2c.put_clk_mask =
+                                            RBIOS32(lcd_ddc_info + 3);
+                                        ddc_i2c.put_data_mask =
+                                            RBIOS32(lcd_ddc_info + 7);
+                                        ddc_i2c.get_clk_mask =
+                                            RBIOS32(lcd_ddc_info + 3);
+                                        ddc_i2c.get_data_mask =
+                                            RBIOS32(lcd_ddc_info + 7);
+                                        break;
+                                case DDC_GPIO:
+                                        ddc_i2c =
+                                            combios_setup_i2c_bus
+                                            (RADEON_MDGPIO_EN_REG);
+                                        ddc_i2c.mask_clk_mask =
+                                            RBIOS32(lcd_ddc_info + 3);
+                                        ddc_i2c.mask_data_mask =
+                                            RBIOS32(lcd_ddc_info + 7);
+                                        ddc_i2c.a_clk_mask =
+                                            RBIOS32(lcd_ddc_info + 3);
+                                        ddc_i2c.a_data_mask =
+                                            RBIOS32(lcd_ddc_info + 7);
+                                        ddc_i2c.put_clk_mask =
+                                            RBIOS32(lcd_ddc_info + 3);
+                                        ddc_i2c.put_data_mask =
+                                            RBIOS32(lcd_ddc_info + 7);
+                                        ddc_i2c.get_clk_mask =
+                                            RBIOS32(lcd_ddc_info + 3);
+                                        ddc_i2c.get_data_mask =
+                                            RBIOS32(lcd_ddc_info + 7);
+                                        break;
+                                default:
+                                        ddc_i2c.valid = false;
+                                        break;
+                                }
+                                DRM_DEBUG("LCD DDC Info Table found!\n");
+                        } else
+                                ddc_i2c.valid = false;
+
+                        radeon_add_legacy_connector(dev,
+                                                    5,
+                                                    ATOM_DEVICE_LCD1_SUPPORT,
+                                                    DRM_MODE_CONNECTOR_LVDS,
+                                                    &ddc_i2c);
+                }
+        }
+
+        /* check TV table */
+        if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
+                uint32_t tv_info =
+                    combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
+                if (tv_info) {
+                        if (RBIOS8(tv_info + 6) == 'T') {
+                                radeon_add_legacy_encoder(dev,
+                                                          radeon_get_encoder_id
+                                                          (dev,
+                                                           ATOM_DEVICE_TV1_SUPPORT,
+                                                           2),
+                                                          ATOM_DEVICE_TV1_SUPPORT);
+                                radeon_add_legacy_connector(dev, 6,
+                                                            ATOM_DEVICE_TV1_SUPPORT,
+                                                            DRM_MODE_CONNECTOR_SVIDEO,
+                                                            &ddc_i2c);
+                        }
+                }
+        }
+
+        radeon_link_encoder_connector(dev);
+
+        return true;
+}
+
+static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
+{
+        struct radeon_device *rdev = dev->dev_private;
+
+        if (offset) {
+                while (RBIOS16(offset)) {
+                        uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
+                        uint32_t addr = (RBIOS16(offset) & 0x1fff);
+                        uint32_t val, and_mask, or_mask;
+                        uint32_t tmp;
+
+                        offset += 2;
+                        switch (cmd) {
+                        case 0:
+                                val = RBIOS32(offset);
+                                offset += 4;
+                                WREG32(addr, val);
+                                break;
+                        case 1:
+                                val = RBIOS32(offset);
+                                offset += 4;
+                                WREG32(addr, val);
+                                break;
+                        case 2:
+                                and_mask = RBIOS32(offset);
+                                offset += 4;
+                                or_mask = RBIOS32(offset);
+                                offset += 4;
+                                tmp = RREG32(addr);
+                                tmp &= and_mask;
+                                tmp |= or_mask;
+                                WREG32(addr, tmp);
+                                break;
+                        case 3:
+                                and_mask = RBIOS32(offset);
+                                offset += 4;
+                                or_mask = RBIOS32(offset);
+                                offset += 4;
+                                tmp = RREG32(addr);
+                                tmp &= and_mask;
+                                tmp |= or_mask;
+                                WREG32(addr, tmp);
+                                break;
+                        case 4:
+                                val = RBIOS16(offset);
+                                offset += 2;
+                                udelay(val);
+                                break;
+                        case 5:
+                                val = RBIOS16(offset);
+                                offset += 2;
+                                switch (addr) {
+                                case 8:
+                                        while (val--) {
+                                                if (!
+                                                    (RREG32_PLL
+                                                     (RADEON_CLK_PWRMGT_CNTL) &
+                                                     RADEON_MC_BUSY))
+                                                        break;
+                                        }
+                                        break;
+                                case 9:
+                                        while (val--) {
+                                                if ((RREG32(RADEON_MC_STATUS) &
+                                                     RADEON_MC_IDLE))
+                                                        break;
+                                        }
+                                        break;
+                                default:
+                                        break;
+                                }
+                                break;
+                        default:
+                                break;
+                        }
+                }
+        }
+}
+
+static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
+{
+        struct radeon_device *rdev = dev->dev_private;
+
+        if (offset) {
+                while (RBIOS8(offset)) {
+                        uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
+                        uint8_t addr = (RBIOS8(offset) & 0x3f);
+                        uint32_t val, shift, tmp;
+                        uint32_t and_mask, or_mask;
+
+                        offset++;
+                        switch (cmd) {
+                        case 0:
+                                val = RBIOS32(offset);
+                                offset += 4;
+                                WREG32_PLL(addr, val);
+                                break;
+                        case 1:
+                                shift = RBIOS8(offset) * 8;
+                                offset++;
+                                and_mask = RBIOS8(offset) << shift;
+                                and_mask |= ~(0xff << shift);
+                                offset++;
+                                or_mask = RBIOS8(offset) << shift;
+                                offset++;
+                                tmp = RREG32_PLL(addr);
+                                tmp &= and_mask;
+                                tmp |= or_mask;
+                                WREG32_PLL(addr, tmp);
+                                break;
+                        case 2:
+                        case 3:
+                                tmp = 1000;
+                                switch (addr) {
+                                case 1:
+                                        udelay(150);
+                                        break;
+                                case 2:
+                                        udelay(1000);
+                                        break;
+                                case 3:
+                                        while (tmp--) {
+                                                if (!
+                                                    (RREG32_PLL
+                                                     (RADEON_CLK_PWRMGT_CNTL) &
+                                                     RADEON_MC_BUSY))
+                                                        break;
+                                        }
+                                        break;
+                                case 4:
+                                        while (tmp--) {
+                                                if (RREG32_PLL
+                                                    (RADEON_CLK_PWRMGT_CNTL) &
+                                                    RADEON_DLL_READY)
+                                                        break;
+                                        }
+                                        break;
+                                case 5:
+                                        tmp =
+                                            RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
+                                        if (tmp & RADEON_CG_NO1_DEBUG_0) {
+#if 0
+                                                uint32_t mclk_cntl =
+                                                    RREG32_PLL
+                                                    (RADEON_MCLK_CNTL);
+                                                mclk_cntl &= 0xffff0000;
+                                                /*mclk_cntl |= 0x00001111;*//* ??? */
+                                                WREG32_PLL(RADEON_MCLK_CNTL,
+                                                           mclk_cntl);
+                                                udelay(10000);
+#endif
+                                                WREG32_PLL
+                                                    (RADEON_CLK_PWRMGT_CNTL,
+                                                     tmp &
+                                                     ~RADEON_CG_NO1_DEBUG_0);
+                                                udelay(10000);
+                                        }
+                                        break;
+                                default:
+                                        break;
+                                }
+                                break;
+                        default:
+                                break;
+                        }
+                }
+        }
+}
+
+static void combios_parse_ram_reset_table(struct drm_device *dev,
+                                          uint16_t offset)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t tmp;
+
+        if (offset) {
+                uint8_t val = RBIOS8(offset);
+                while (val != 0xff) {
+                        offset++;
+
+                        if (val == 0x0f) {
+                                uint32_t channel_complete_mask;
+
+                                if (ASIC_IS_R300(rdev))
+                                        channel_complete_mask =
+                                            R300_MEM_PWRUP_COMPLETE;
+                                else
+                                        channel_complete_mask =
+                                            RADEON_MEM_PWRUP_COMPLETE;
+                                tmp = 20000;
+                                while (tmp--) {
+                                        if ((RREG32(RADEON_MEM_STR_CNTL) &
+                                             channel_complete_mask) ==
+                                            channel_complete_mask)
+                                                break;
+                                }
+                        } else {
+                                uint32_t or_mask = RBIOS16(offset);
+                                offset += 2;
+
+                                tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
+                                tmp &= RADEON_SDRAM_MODE_MASK;
+                                tmp |= or_mask;
+                                WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
+
+                                or_mask = val << 24;
+                                tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
+                                tmp &= RADEON_B3MEM_RESET_MASK;
+                                tmp |= or_mask;
+                                WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
+                        }
+                        val = RBIOS8(offset);
+                }
+        }
+}
+
+static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
+                                   int mem_addr_mapping)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t mem_cntl;
+        uint32_t mem_size;
+        uint32_t addr = 0;
+
+        mem_cntl = RREG32(RADEON_MEM_CNTL);
+        if (mem_cntl & RV100_HALF_MODE)
+                ram /= 2;
+        mem_size = ram;
+        mem_cntl &= ~(0xff << 8);
+        mem_cntl |= (mem_addr_mapping & 0xff) << 8;
+        WREG32(RADEON_MEM_CNTL, mem_cntl);
+        RREG32(RADEON_MEM_CNTL);
+
+        /* sdram reset ? */
+
+        /* something like this????  */
+        while (ram--) {
+                addr = ram * 1024 * 1024;
+                /* write to each page */
+                WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
+                WREG32(RADEON_MM_DATA, 0xdeadbeef);
+                /* read back and verify */
+                WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
+                if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
+                        return 0;
+        }
+
+        return mem_size;
+}
+
+static void combios_write_ram_size(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        uint8_t rev;
+        uint16_t offset;
+        uint32_t mem_size = 0;
+        uint32_t mem_cntl = 0;
+
+        /* should do something smarter here I guess... */
+        if (rdev->flags & RADEON_IS_IGP)
+                return;
+
+        /* first check detected mem table */
+        offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
+        if (offset) {
+                rev = RBIOS8(offset);
+                if (rev < 3) {
+                        mem_cntl = RBIOS32(offset + 1);
+                        mem_size = RBIOS16(offset + 5);
+                        if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
+                            ((dev->pdev->device != 0x515e)
+                             && (dev->pdev->device != 0x5969)))
+                                WREG32(RADEON_MEM_CNTL, mem_cntl);
+                }
+        }
+
+        if (!mem_size) {
+                offset =
+                    combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
+                if (offset) {
+                        rev = RBIOS8(offset - 1);
+                        if (rev < 1) {
+                                if (((rdev->flags & RADEON_FAMILY_MASK) <
+                                     CHIP_R200)
+                                    && ((dev->pdev->device != 0x515e)
+                                        && (dev->pdev->device != 0x5969))) {
+                                        int ram = 0;
+                                        int mem_addr_mapping = 0;
+
+                                        while (RBIOS8(offset)) {
+                                                ram = RBIOS8(offset);
+                                                mem_addr_mapping =
+                                                    RBIOS8(offset + 1);
+                                                if (mem_addr_mapping != 0x25)
+                                                        ram *= 2;
+                                                mem_size =
+                                                    combios_detect_ram(dev, ram,
+                                                                       mem_addr_mapping);
+                                                if (mem_size)
+                                                        break;
+                                                offset += 2;
+                                        }
+                                } else
+                                        mem_size = RBIOS8(offset);
+                        } else {
+                                mem_size = RBIOS8(offset);
+                                mem_size *= 2;  /* convert to MB */
+                        }
+                }
+        }
+
+        mem_size *= (1024 * 1024);      /* convert to bytes */
+        WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
+}
+
+void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
+{
+        uint16_t dyn_clk_info =
+            combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
+
+        if (dyn_clk_info)
+                combios_parse_pll_table(dev, dyn_clk_info);
+}
+
+void radeon_combios_asic_init(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        uint16_t table;
+
+        /* port hardcoded mac stuff from radeonfb */
+        if (rdev->bios == NULL)
+                return;
+
+        /* ASIC INIT 1 */
+        table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
+        if (table)
+                combios_parse_mmio_table(dev, table);
+
+        /* PLL INIT */
+        table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
+        if (table)
+                combios_parse_pll_table(dev, table);
+
+        /* ASIC INIT 2 */
+        table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
+        if (table)
+                combios_parse_mmio_table(dev, table);
+
+        if (!(rdev->flags & RADEON_IS_IGP)) {
+                /* ASIC INIT 4 */
+                table =
+                    combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
+                if (table)
+                        combios_parse_mmio_table(dev, table);
+
+                /* RAM RESET */
+                table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
+                if (table)
+                        combios_parse_ram_reset_table(dev, table);
+
+                /* ASIC INIT 3 */
+                table =
+                    combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
+                if (table)
+                        combios_parse_mmio_table(dev, table);
+
+                /* write CONFIG_MEMSIZE */
+                combios_write_ram_size(dev);
+        }
+
+        /* DYN CLK 1 */
+        table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
+        if (table)
+                combios_parse_pll_table(dev, table);
+
+}
+
+void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
+
+        bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
+        bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
+        bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
+
+        /* let the bios control the backlight */
+        bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
+
+        /* tell the bios not to handle mode switching */
+        bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
+                           RADEON_ACC_MODE_CHANGE);
+
+        /* tell the bios a driver is loaded */
+        bios_7_scratch |= RADEON_DRV_LOADED;
+
+        WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
+        WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
+        WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
+}
+
+void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t bios_6_scratch;
+
+        bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
+
+        if (lock)
+                bios_6_scratch |= RADEON_DRIVER_CRITICAL;
+        else
+                bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
+
+        WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
+}
+
+void
+radeon_combios_connected_scratch_regs(struct drm_connector *connector,
+                                      struct drm_encoder *encoder,
+                                      bool connected)
+{
+        struct drm_device *dev = connector->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_connector *radeon_connector =
+            to_radeon_connector(connector);
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
+        uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
+
+        if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("TV1 connected\n");
+                        /* fix me */
+                        bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
+                        /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
+                        bios_5_scratch |= RADEON_TV1_ON;
+                        bios_5_scratch |= RADEON_ACC_REQ_TV1;
+                } else {
+                        DRM_DEBUG("TV1 disconnected\n");
+                        bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
+                        bios_5_scratch &= ~RADEON_TV1_ON;
+                        bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("LCD1 connected\n");
+                        bios_4_scratch |= RADEON_LCD1_ATTACHED;
+                        bios_5_scratch |= RADEON_LCD1_ON;
+                        bios_5_scratch |= RADEON_ACC_REQ_LCD1;
+                } else {
+                        DRM_DEBUG("LCD1 disconnected\n");
+                        bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
+                        bios_5_scratch &= ~RADEON_LCD1_ON;
+                        bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("CRT1 connected\n");
+                        bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
+                        bios_5_scratch |= RADEON_CRT1_ON;
+                        bios_5_scratch |= RADEON_ACC_REQ_CRT1;
+                } else {
+                        DRM_DEBUG("CRT1 disconnected\n");
+                        bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
+                        bios_5_scratch &= ~RADEON_CRT1_ON;
+                        bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("CRT2 connected\n");
+                        bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
+                        bios_5_scratch |= RADEON_CRT2_ON;
+                        bios_5_scratch |= RADEON_ACC_REQ_CRT2;
+                } else {
+                        DRM_DEBUG("CRT2 disconnected\n");
+                        bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
+                        bios_5_scratch &= ~RADEON_CRT2_ON;
+                        bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("DFP1 connected\n");
+                        bios_4_scratch |= RADEON_DFP1_ATTACHED;
+                        bios_5_scratch |= RADEON_DFP1_ON;
+                        bios_5_scratch |= RADEON_ACC_REQ_DFP1;
+                } else {
+                        DRM_DEBUG("DFP1 disconnected\n");
+                        bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
+                        bios_5_scratch &= ~RADEON_DFP1_ON;
+                        bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
+                }
+        }
+        if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
+            (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
+                if (connected) {
+                        DRM_DEBUG("DFP2 connected\n");
+                        bios_4_scratch |= RADEON_DFP2_ATTACHED;
+                        bios_5_scratch |= RADEON_DFP2_ON;
+                        bios_5_scratch |= RADEON_ACC_REQ_DFP2;
+                } else {
+                        DRM_DEBUG("DFP2 disconnected\n");
+                        bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
+                        bios_5_scratch &= ~RADEON_DFP2_ON;
+                        bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
+                }
+        }
+        WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
+        WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
+}
+
+void
+radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
+
+        if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
+                bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
+                bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
+                bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
+                bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
+                bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
+                bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
+                bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
+                bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
+                bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
+                bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
+        }
+        if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
+                bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
+                bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
+        }
+        WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
+}
+
+void
+radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
+
+        if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
+                if (on)
+                        bios_6_scratch |= RADEON_TV_DPMS_ON;
+                else
+                        bios_6_scratch &= ~RADEON_TV_DPMS_ON;
+        }
+        if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
+                if (on)
+                        bios_6_scratch |= RADEON_CRT_DPMS_ON;
+                else
+                        bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
+        }
+        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+                if (on)
+                        bios_6_scratch |= RADEON_LCD_DPMS_ON;
+                else
+                        bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
+        }
+        if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+                if (on)
+                        bios_6_scratch |= RADEON_DFP_DPMS_ON;
+                else
+                        bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
+        }
+        WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
+}
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
new file mode 100644
index 000000000000..70ede6a52d4e
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -0,0 +1,603 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include "drmP.h"
+#include "drm_edid.h"
+#include "drm_crtc_helper.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+
+extern void
+radeon_combios_connected_scratch_regs(struct drm_connector *connector,
+                                      struct drm_encoder *encoder,
+                                      bool connected);
+extern void
+radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
+                                       struct drm_encoder *encoder,
+                                       bool connected);
+
+static void
+radeon_connector_update_scratch_regs(struct drm_connector *connector, enum drm_connector_status status)
+{
+        struct drm_device *dev = connector->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_encoder *best_encoder = NULL;
+        struct drm_encoder *encoder = NULL;
+        struct drm_connector_helper_funcs *connector_funcs = connector->helper_private;
+        struct drm_mode_object *obj;
+        bool connected;
+        int i;
+
+        best_encoder = connector_funcs->best_encoder(connector);
+
+        for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+                if (connector->encoder_ids[i] == 0)
+                        break;
+
+                obj = drm_mode_object_find(connector->dev,
+                                           connector->encoder_ids[i],
+                                           DRM_MODE_OBJECT_ENCODER);
+                if (!obj)
+                        continue;
+
+                encoder = obj_to_encoder(obj);
+
+                if ((encoder == best_encoder) && (status == connector_status_connected))
+                        connected = true;
+                else
+                        connected = false;
+
+                if (rdev->is_atom_bios)
+                        radeon_atombios_connected_scratch_regs(connector, encoder, connected);
+                else
+                        radeon_combios_connected_scratch_regs(connector, encoder, connected);
+
+        }
+}
+
+struct drm_encoder *radeon_best_single_encoder(struct drm_connector *connector)
+{
+        int enc_id = connector->encoder_ids[0];
+        struct drm_mode_object *obj;
+        struct drm_encoder *encoder;
+
+        /* pick the encoder ids */
+        if (enc_id) {
+                obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
+                if (!obj)
+                        return NULL;
+                encoder = obj_to_encoder(obj);
+                return encoder;
+        }
+        return NULL;
+}
+
+static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct drm_display_mode *mode = NULL;
+        struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
+
+        if (native_mode->panel_xres != 0 &&
+            native_mode->panel_yres != 0 &&
+            native_mode->dotclock != 0) {
+                mode = drm_mode_create(dev);
+
+                mode->hdisplay = native_mode->panel_xres;
+                mode->vdisplay = native_mode->panel_yres;
+
+                mode->htotal = mode->hdisplay + native_mode->hblank;
+                mode->hsync_start = mode->hdisplay + native_mode->hoverplus;
+                mode->hsync_end = mode->hsync_start + native_mode->hsync_width;
+                mode->vtotal = mode->vdisplay + native_mode->vblank;
+                mode->vsync_start = mode->vdisplay + native_mode->voverplus;
+                mode->vsync_end = mode->vsync_start + native_mode->vsync_width;
+                mode->clock = native_mode->dotclock;
+                mode->flags = 0;
+
+                mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
+                drm_mode_set_name(mode);
+
+                DRM_DEBUG("Adding native panel mode %s\n", mode->name);
+        }
+        return mode;
+}
+
+int radeon_connector_set_property(struct drm_connector *connector, struct drm_property *property,
+                                  uint64_t val)
+{
+        return 0;
+}
+
+
+static int radeon_lvds_get_modes(struct drm_connector *connector)
+{
+        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+        struct drm_encoder *encoder;
+        int ret = 0;
+        struct drm_display_mode *mode;
+
+        if (radeon_connector->ddc_bus) {
+                ret = radeon_ddc_get_modes(radeon_connector);
+                if (ret > 0) {
+                        return ret;
+                }
+        }
+
+        encoder = radeon_best_single_encoder(connector);
+        if (!encoder)
+                return 0;
+
+        /* we have no EDID modes */
+        mode = radeon_fp_native_mode(encoder);
+        if (mode) {
+                ret = 1;
+                drm_mode_probed_add(connector, mode);
+        }
+        return ret;
+}
+
+static int radeon_lvds_mode_valid(struct drm_connector *connector,
+                                  struct drm_display_mode *mode)
+{
+        return MODE_OK;
+}
+
+static enum drm_connector_status radeon_lvds_detect(struct drm_connector *connector)
+{
+        enum drm_connector_status ret = connector_status_connected;
+        /* check acpi lid status ??? */
+        radeon_connector_update_scratch_regs(connector, ret);
+        return ret;
+}
+
+static void radeon_connector_destroy(struct drm_connector *connector)
+{
+        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+
+        if (radeon_connector->ddc_bus)
+                radeon_i2c_destroy(radeon_connector->ddc_bus);
+        kfree(radeon_connector->con_priv);
+        drm_sysfs_connector_remove(connector);
+        drm_connector_cleanup(connector);
+        kfree(connector);
+}
+
+struct drm_connector_helper_funcs radeon_lvds_connector_helper_funcs = {
+        .get_modes = radeon_lvds_get_modes,
+        .mode_valid = radeon_lvds_mode_valid,
+        .best_encoder = radeon_best_single_encoder,
+};
+
+struct drm_connector_funcs radeon_lvds_connector_funcs = {
+        .dpms = drm_helper_connector_dpms,
+        .detect = radeon_lvds_detect,
+        .fill_modes = drm_helper_probe_single_connector_modes,
+        .destroy = radeon_connector_destroy,
+        .set_property = radeon_connector_set_property,
+};
+
+static int radeon_vga_get_modes(struct drm_connector *connector)
+{
+        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+        int ret;
+
+        ret = radeon_ddc_get_modes(radeon_connector);
+
+        return ret;
+}
+
+static int radeon_vga_mode_valid(struct drm_connector *connector,
+                                  struct drm_display_mode *mode)
+{
+
+        return MODE_OK;
+}
+
+static enum drm_connector_status radeon_vga_detect(struct drm_connector *connector)
+{
+        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+        struct drm_encoder *encoder;
+        struct drm_encoder_helper_funcs *encoder_funcs;
+        bool dret;
+        enum drm_connector_status ret = connector_status_disconnected;
+
+        radeon_i2c_do_lock(radeon_connector, 1);
+        dret = radeon_ddc_probe(radeon_connector);
+        radeon_i2c_do_lock(radeon_connector, 0);
+        if (dret)
+                ret = connector_status_connected;
+        else {
+                /* if EDID fails to a load detect */
+                encoder = radeon_best_single_encoder(connector);
+                if (!encoder)
+                        ret = connector_status_disconnected;
+                else {
+                        encoder_funcs = encoder->helper_private;
+                        ret = encoder_funcs->detect(encoder, connector);
+                }
+        }
+
+        radeon_connector_update_scratch_regs(connector, ret);
+        return ret;
+}
+
+struct drm_connector_helper_funcs radeon_vga_connector_helper_funcs = {
+        .get_modes = radeon_vga_get_modes,
+        .mode_valid = radeon_vga_mode_valid,
+        .best_encoder = radeon_best_single_encoder,
+};
+
+struct drm_connector_funcs radeon_vga_connector_funcs = {
+        .dpms = drm_helper_connector_dpms,
+        .detect = radeon_vga_detect,
+        .fill_modes = drm_helper_probe_single_connector_modes,
+        .destroy = radeon_connector_destroy,
+        .set_property = radeon_connector_set_property,
+};
+
+static int radeon_dvi_get_modes(struct drm_connector *connector)
+{
+        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+        int ret;
+
+        ret = radeon_ddc_get_modes(radeon_connector);
+        /* reset scratch regs here since radeon_dvi_detect doesn't check digital bit */
+        radeon_connector_update_scratch_regs(connector, connector_status_connected);
+        return ret;
+}
+
+static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connector)
+{
+        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+        struct drm_encoder *encoder;
+        struct drm_encoder_helper_funcs *encoder_funcs;
+        struct drm_mode_object *obj;
+        int i;
+        enum drm_connector_status ret = connector_status_disconnected;
+        bool dret;
+
+        radeon_i2c_do_lock(radeon_connector, 1);
+        dret = radeon_ddc_probe(radeon_connector);
+        radeon_i2c_do_lock(radeon_connector, 0);
+        if (dret)
+                ret = connector_status_connected;
+        else {
+                for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+                        if (connector->encoder_ids[i] == 0)
+                                break;
+
+                        obj = drm_mode_object_find(connector->dev,
+                                                   connector->encoder_ids[i],
+                                                   DRM_MODE_OBJECT_ENCODER);
+                        if (!obj)
+                                continue;
+
+                        encoder = obj_to_encoder(obj);
+
+                        encoder_funcs = encoder->helper_private;
+                        if (encoder_funcs->detect) {
+                                ret = encoder_funcs->detect(encoder, connector);
+                                if (ret == connector_status_connected) {
+                                        radeon_connector->use_digital = 0;
+                                        break;
+                                }
+                        }
+                }
+        }
+
+        /* updated in get modes as well since we need to know if it's analog or digital */
+        radeon_connector_update_scratch_regs(connector, ret);
+        return ret;
+}
+
+/* okay need to be smart in here about which encoder to pick */
+struct drm_encoder *radeon_dvi_encoder(struct drm_connector *connector)
+{
+        int enc_id = connector->encoder_ids[0];
+        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+        struct drm_mode_object *obj;
+        struct drm_encoder *encoder;
+        int i;
+        for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+                if (connector->encoder_ids[i] == 0)
+                        break;
+
+                obj = drm_mode_object_find(connector->dev, connector->encoder_ids[i], DRM_MODE_OBJECT_ENCODER);
+                if (!obj)
+                        continue;
+
+                encoder = obj_to_encoder(obj);
+
+                if (radeon_connector->use_digital) {
+                        if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
+                                return encoder;
+                } else {
+                        if (encoder->encoder_type == DRM_MODE_ENCODER_DAC ||
+                            encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
+                                return encoder;
+                }
+        }
+
+        /* see if we have a default encoder  TODO */
+
+        /* then check use digitial */
+        /* pick the first one */
+        if (enc_id) {
+                obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER);
+                if (!obj)
+                        return NULL;
+                encoder = obj_to_encoder(obj);
+                return encoder;
+        }
+        return NULL;
+}
+
+struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = {
+        .get_modes = radeon_dvi_get_modes,
+        .mode_valid = radeon_vga_mode_valid,
+        .best_encoder = radeon_dvi_encoder,
+};
+
+struct drm_connector_funcs radeon_dvi_connector_funcs = {
+        .dpms = drm_helper_connector_dpms,
+        .detect = radeon_dvi_detect,
+        .fill_modes = drm_helper_probe_single_connector_modes,
+        .set_property = radeon_connector_set_property,
+        .destroy = radeon_connector_destroy,
+};
+
+void
+radeon_add_atom_connector(struct drm_device *dev,
+                          uint32_t connector_id,
+                          uint32_t supported_device,
+                          int connector_type,
+                          struct radeon_i2c_bus_rec *i2c_bus,
+                          bool linkb,
+                          uint32_t igp_lane_info)
+{
+        struct drm_connector *connector;
+        struct radeon_connector *radeon_connector;
+        struct radeon_connector_atom_dig *radeon_dig_connector;
+        uint32_t subpixel_order = SubPixelNone;
+
+        /* fixme - tv/cv/din */
+        if ((connector_type == DRM_MODE_CONNECTOR_Unknown) ||
+            (connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
+            (connector_type == DRM_MODE_CONNECTOR_Composite) ||
+            (connector_type == DRM_MODE_CONNECTOR_9PinDIN))
+                return;
+
+        /* see if we already added it */
+        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+                radeon_connector = to_radeon_connector(connector);
+                if (radeon_connector->connector_id == connector_id) {
+                        radeon_connector->devices |= supported_device;
+                        return;
+                }
+        }
+
+        radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
+        if (!radeon_connector)
+                return;
+
+        connector = &radeon_connector->base;
+
+        radeon_connector->connector_id = connector_id;
+        radeon_connector->devices = supported_device;
+        switch (connector_type) {
+        case DRM_MODE_CONNECTOR_VGA:
+                drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
+                if (i2c_bus->valid) {
+                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA");
+                        if (!radeon_connector->ddc_bus)
+                                goto failed;
+                }
+                break;
+        case DRM_MODE_CONNECTOR_DVIA:
+                drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
+                if (i2c_bus->valid) {
+                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI");
+                        if (!radeon_connector->ddc_bus)
+                                goto failed;
+                }
+                break;
+        case DRM_MODE_CONNECTOR_DVII:
+        case DRM_MODE_CONNECTOR_DVID:
+                radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
+                if (!radeon_dig_connector)
+                        goto failed;
+                radeon_dig_connector->linkb = linkb;
+                radeon_dig_connector->igp_lane_info = igp_lane_info;
+                radeon_connector->con_priv = radeon_dig_connector;
+                drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
+                if (i2c_bus->valid) {
+                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI");
+                        if (!radeon_connector->ddc_bus)
+                                goto failed;
+                }
+                subpixel_order = SubPixelHorizontalRGB;
+                break;
+        case DRM_MODE_CONNECTOR_HDMIA:
+        case DRM_MODE_CONNECTOR_HDMIB:
+                radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
+                if (!radeon_dig_connector)
+                        goto failed;
+                radeon_dig_connector->linkb = linkb;
+                radeon_dig_connector->igp_lane_info = igp_lane_info;
+                radeon_connector->con_priv = radeon_dig_connector;
+                drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
+                if (i2c_bus->valid) {
+                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "HDMI");
+                        if (!radeon_connector->ddc_bus)
+                                goto failed;
+                }
+                subpixel_order = SubPixelHorizontalRGB;
+                break;
+        case DRM_MODE_CONNECTOR_DisplayPort:
+                radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
+                if (!radeon_dig_connector)
+                        goto failed;
+                radeon_dig_connector->linkb = linkb;
+                radeon_dig_connector->igp_lane_info = igp_lane_info;
+                radeon_connector->con_priv = radeon_dig_connector;
+                drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
+                if (i2c_bus->valid) {
+                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP");
+                        if (!radeon_connector->ddc_bus)
+                                goto failed;
+                }
+                subpixel_order = SubPixelHorizontalRGB;
+                break;
+        case DRM_MODE_CONNECTOR_SVIDEO:
+        case DRM_MODE_CONNECTOR_Composite:
+        case DRM_MODE_CONNECTOR_9PinDIN:
+                break;
+        case DRM_MODE_CONNECTOR_LVDS:
+                radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
+                if (!radeon_dig_connector)
+                        goto failed;
+                radeon_dig_connector->linkb = linkb;
+                radeon_dig_connector->igp_lane_info = igp_lane_info;
+                radeon_connector->con_priv = radeon_dig_connector;
+                drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
+                if (i2c_bus->valid) {
+                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS");
+                        if (!radeon_connector->ddc_bus)
+                                goto failed;
+                }
+                subpixel_order = SubPixelHorizontalRGB;
+                break;
+        }
+
+        connector->display_info.subpixel_order = subpixel_order;
+        drm_sysfs_connector_add(connector);
+        return;
+
+failed:
+        if (radeon_connector->ddc_bus)
+                radeon_i2c_destroy(radeon_connector->ddc_bus);
+        drm_connector_cleanup(connector);
+        kfree(connector);
+}
+
+void
+radeon_add_legacy_connector(struct drm_device *dev,
+                            uint32_t connector_id,
+                            uint32_t supported_device,
+                            int connector_type,
+                            struct radeon_i2c_bus_rec *i2c_bus)
+{
+        struct drm_connector *connector;
+        struct radeon_connector *radeon_connector;
+        uint32_t subpixel_order = SubPixelNone;
+
+        /* fixme - tv/cv/din */
+        if ((connector_type == DRM_MODE_CONNECTOR_Unknown) ||
+            (connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
+            (connector_type == DRM_MODE_CONNECTOR_Composite) ||
+            (connector_type == DRM_MODE_CONNECTOR_9PinDIN))
+                return;
+
+        /* see if we already added it */
+        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+                radeon_connector = to_radeon_connector(connector);
+                if (radeon_connector->connector_id == connector_id) {
+                        radeon_connector->devices |= supported_device;
+                        return;
+                }
+        }
+
+        radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
+        if (!radeon_connector)
+                return;
+
+        connector = &radeon_connector->base;
+
+        radeon_connector->connector_id = connector_id;
+        radeon_connector->devices = supported_device;
+        switch (connector_type) {
+        case DRM_MODE_CONNECTOR_VGA:
+                drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
+                if (i2c_bus->valid) {
+                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "VGA");
+                        if (!radeon_connector->ddc_bus)
+                                goto failed;
+                }
+                break;
+        case DRM_MODE_CONNECTOR_DVIA:
+                drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
+                if (i2c_bus->valid) {
+                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI");
+                        if (!radeon_connector->ddc_bus)
+                                goto failed;
+                }
+                break;
+        case DRM_MODE_CONNECTOR_DVII:
+        case DRM_MODE_CONNECTOR_DVID:
+                drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
+                if (i2c_bus->valid) {
+                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DVI");
+                        if (!radeon_connector->ddc_bus)
+                                goto failed;
+                }
+                subpixel_order = SubPixelHorizontalRGB;
+                break;
+        case DRM_MODE_CONNECTOR_SVIDEO:
+        case DRM_MODE_CONNECTOR_Composite:
+        case DRM_MODE_CONNECTOR_9PinDIN:
+                break;
+        case DRM_MODE_CONNECTOR_LVDS:
+                drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
+                if (i2c_bus->valid) {
+                        radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "LVDS");
+                        if (!radeon_connector->ddc_bus)
+                                goto failed;
+                }
+                subpixel_order = SubPixelHorizontalRGB;
+                break;
+        }
+
+        connector->display_info.subpixel_order = subpixel_order;
+        drm_sysfs_connector_add(connector);
+        return;
+
+failed:
+        if (radeon_connector->ddc_bus)
+                radeon_i2c_destroy(radeon_connector->ddc_bus);
+        drm_connector_cleanup(connector);
+        kfree(connector);
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
new file mode 100644
index 000000000000..b843f9bdfb14
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright 2008 Jerome Glisse.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Jerome Glisse <glisse@freedesktop.org>
+ */
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+void r100_cs_dump_packet(struct radeon_cs_parser *p,
+                         struct radeon_cs_packet *pkt);
+
+int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
+{
+        struct drm_device *ddev = p->rdev->ddev;
+        struct radeon_cs_chunk *chunk;
+        unsigned i, j;
+        bool duplicate;
+
+        if (p->chunk_relocs_idx == -1) {
+                return 0;
+        }
+        chunk = &p->chunks[p->chunk_relocs_idx];
+        /* FIXME: we assume that each relocs use 4 dwords */
+        p->nrelocs = chunk->length_dw / 4;
+        p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
+        if (p->relocs_ptr == NULL) {
+                return -ENOMEM;
+        }
+        p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
+        if (p->relocs == NULL) {
+                return -ENOMEM;
+        }
+        for (i = 0; i < p->nrelocs; i++) {
+                struct drm_radeon_cs_reloc *r;
+
+                duplicate = false;
+                r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
+                for (j = 0; j < p->nrelocs; j++) {
+                        if (r->handle == p->relocs[j].handle) {
+                                p->relocs_ptr[i] = &p->relocs[j];
+                                duplicate = true;
+                                break;
+                        }
+                }
+                if (!duplicate) {
+                        p->relocs[i].gobj = drm_gem_object_lookup(ddev,
+                                                                  p->filp,
+                                                                  r->handle);
+                        if (p->relocs[i].gobj == NULL) {
+                                DRM_ERROR("gem object lookup failed 0x%x\n",
+                                          r->handle);
+                                return -EINVAL;
+                        }
+                        p->relocs_ptr[i] = &p->relocs[i];
+                        p->relocs[i].robj = p->relocs[i].gobj->driver_private;
+                        p->relocs[i].lobj.robj = p->relocs[i].robj;
+                        p->relocs[i].lobj.rdomain = r->read_domains;
+                        p->relocs[i].lobj.wdomain = r->write_domain;
+                        p->relocs[i].handle = r->handle;
+                        p->relocs[i].flags = r->flags;
+                        INIT_LIST_HEAD(&p->relocs[i].lobj.list);
+                        radeon_object_list_add_object(&p->relocs[i].lobj,
+                                                      &p->validated);
+                }
+        }
+        return radeon_object_list_validate(&p->validated, p->ib->fence);
+}
+
+int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
+{
+        struct drm_radeon_cs *cs = data;
+        uint64_t *chunk_array_ptr;
+        unsigned size, i;
+
+        if (!cs->num_chunks) {
+                return 0;
+        }
+        /* get chunks */
+        INIT_LIST_HEAD(&p->validated);
+        p->idx = 0;
+        p->chunk_ib_idx = -1;
+        p->chunk_relocs_idx = -1;
+        p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
+        if (p->chunks_array == NULL) {
+                return -ENOMEM;
+        }
+        chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
+        if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
+                               sizeof(uint64_t)*cs->num_chunks)) {
+                return -EFAULT;
+        }
+        p->nchunks = cs->num_chunks;
+        p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
+        if (p->chunks == NULL) {
+                return -ENOMEM;
+        }
+        for (i = 0; i < p->nchunks; i++) {
+                struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
+                struct drm_radeon_cs_chunk user_chunk;
+                uint32_t __user *cdata;
+
+                chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
+                if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
+                                       sizeof(struct drm_radeon_cs_chunk))) {
+                        return -EFAULT;
+                }
+                p->chunks[i].chunk_id = user_chunk.chunk_id;
+                if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
+                        p->chunk_relocs_idx = i;
+                }
+                if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
+                        p->chunk_ib_idx = i;
+                }
+                p->chunks[i].length_dw = user_chunk.length_dw;
+                cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
+
+                p->chunks[i].kdata = NULL;
+                size = p->chunks[i].length_dw * sizeof(uint32_t);
+                p->chunks[i].kdata = kzalloc(size, GFP_KERNEL);
+                if (p->chunks[i].kdata == NULL) {
+                        return -ENOMEM;
+                }
+                if (DRM_COPY_FROM_USER(p->chunks[i].kdata, cdata, size)) {
+                        return -EFAULT;
+                }
+        }
+        if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
+                DRM_ERROR("cs IB too big: %d\n",
+                          p->chunks[p->chunk_ib_idx].length_dw);
+                return -EINVAL;
+        }
+        return 0;
+}
+
+/**
+ * cs_parser_fini() - clean parser states
+ * @parser:     parser structure holding parsing context.
+ * @error:      error number
+ *
+ * If error is set than unvalidate buffer, otherwise just free memory
+ * used by parsing context.
+ **/
+static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
+{
+        unsigned i;
+
+        if (error) {
+                radeon_object_list_unvalidate(&parser->validated);
+        } else {
+                radeon_object_list_clean(&parser->validated);
+        }
+        for (i = 0; i < parser->nrelocs; i++) {
+                if (parser->relocs[i].gobj) {
+                        mutex_lock(&parser->rdev->ddev->struct_mutex);
+                        drm_gem_object_unreference(parser->relocs[i].gobj);
+                        mutex_unlock(&parser->rdev->ddev->struct_mutex);
+                }
+        }
+        kfree(parser->relocs);
+        kfree(parser->relocs_ptr);
+        for (i = 0; i < parser->nchunks; i++) {
+                kfree(parser->chunks[i].kdata);
+        }
+        kfree(parser->chunks);
+        kfree(parser->chunks_array);
+        radeon_ib_free(parser->rdev, &parser->ib);
+}
+
+int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_cs_parser parser;
+        struct radeon_cs_chunk *ib_chunk;
+        int r;
+
+        mutex_lock(&rdev->cs_mutex);
+        if (rdev->gpu_lockup) {
+                mutex_unlock(&rdev->cs_mutex);
+                return -EINVAL;
+        }
+        /* initialize parser */
+        memset(&parser, 0, sizeof(struct radeon_cs_parser));
+        parser.filp = filp;
+        parser.rdev = rdev;
+        r = radeon_cs_parser_init(&parser, data);
+        if (r) {
+                DRM_ERROR("Failed to initialize parser !\n");
+                radeon_cs_parser_fini(&parser, r);
+                mutex_unlock(&rdev->cs_mutex);
+                return r;
+        }
+        r =  radeon_ib_get(rdev, &parser.ib);
+        if (r) {
+                DRM_ERROR("Failed to get ib !\n");
+                radeon_cs_parser_fini(&parser, r);
+                mutex_unlock(&rdev->cs_mutex);
+                return r;
+        }
+        r = radeon_cs_parser_relocs(&parser);
+        if (r) {
+                DRM_ERROR("Failed to parse relocation !\n");
+                radeon_cs_parser_fini(&parser, r);
+                mutex_unlock(&rdev->cs_mutex);
+                return r;
+        }
+        /* Copy the packet into the IB, the parser will read from the
+         * input memory (cached) and write to the IB (which can be
+         * uncached). */
+        ib_chunk = &parser.chunks[parser.chunk_ib_idx];
+        parser.ib->length_dw = ib_chunk->length_dw;
+        memcpy((void *)parser.ib->ptr, ib_chunk->kdata, ib_chunk->length_dw*4);
+        r = radeon_cs_parse(&parser);
+        if (r) {
+                DRM_ERROR("Invalid command stream !\n");
+                radeon_cs_parser_fini(&parser, r);
+                mutex_unlock(&rdev->cs_mutex);
+                return r;
+        }
+        r = radeon_ib_schedule(rdev, parser.ib);
+        if (r) {
+                DRM_ERROR("Faild to schedule IB !\n");
+        }
+        radeon_cs_parser_fini(&parser, r);
+        mutex_unlock(&rdev->cs_mutex);
+        return r;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
new file mode 100644
index 000000000000..5232441f119b
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+
+#define CURSOR_WIDTH 64
+#define CURSOR_HEIGHT 64
+
+static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
+{
+        struct radeon_device *rdev = crtc->dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        uint32_t cur_lock;
+
+        if (ASIC_IS_AVIVO(rdev)) {
+                cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
+                if (lock)
+                        cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
+                else
+                        cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
+                WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
+        } else {
+                cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
+                if (lock)
+                        cur_lock |= RADEON_CUR_LOCK;
+                else
+                        cur_lock &= ~RADEON_CUR_LOCK;
+                WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
+        }
+}
+
+static void radeon_hide_cursor(struct drm_crtc *crtc)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct radeon_device *rdev = crtc->dev->dev_private;
+
+        if (ASIC_IS_AVIVO(rdev)) {
+                WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
+                WREG32(RADEON_MM_DATA, (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
+        } else {
+                switch (radeon_crtc->crtc_id) {
+                case 0:
+                        WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
+                        break;
+                case 1:
+                        WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
+                        break;
+                default:
+                        return;
+                }
+                WREG32_P(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
+        }
+}
+
+static void radeon_show_cursor(struct drm_crtc *crtc)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct radeon_device *rdev = crtc->dev->dev_private;
+
+        if (ASIC_IS_AVIVO(rdev)) {
+                WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
+                WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
+                             (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
+        } else {
+                switch (radeon_crtc->crtc_id) {
+                case 0:
+                        WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
+                        break;
+                case 1:
+                        WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
+                        break;
+                default:
+                        return;
+                }
+
+                WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
+                                          (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
+                         ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
+        }
+}
+
+static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
+                              uint32_t gpu_addr)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct radeon_device *rdev = crtc->dev->dev_private;
+
+        if (ASIC_IS_AVIVO(rdev))
+                WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
+        else
+                /* offset is from DISP(2)_BASE_ADDRESS */
+                WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, gpu_addr);
+}
+
+int radeon_crtc_cursor_set(struct drm_crtc *crtc,
+                           struct drm_file *file_priv,
+                           uint32_t handle,
+                           uint32_t width,
+                           uint32_t height)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_gem_object *obj;
+        uint64_t gpu_addr;
+        int ret;
+
+        if (!handle) {
+                /* turn off cursor */
+                radeon_hide_cursor(crtc);
+                obj = NULL;
+                goto unpin;
+        }
+
+        if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
+                DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
+                return -EINVAL;
+        }
+
+        radeon_crtc->cursor_width = width;
+        radeon_crtc->cursor_height = height;
+
+        obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
+        if (!obj) {
+                DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
+                return -EINVAL;
+        }
+
+        ret = radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
+        if (ret)
+                goto fail;
+
+        radeon_lock_cursor(crtc, true);
+        /* XXX only 27 bit offset for legacy cursor */
+        radeon_set_cursor(crtc, obj, gpu_addr);
+        radeon_show_cursor(crtc);
+        radeon_lock_cursor(crtc, false);
+
+unpin:
+        if (radeon_crtc->cursor_bo) {
+                radeon_gem_object_unpin(radeon_crtc->cursor_bo);
+                mutex_lock(&crtc->dev->struct_mutex);
+                drm_gem_object_unreference(radeon_crtc->cursor_bo);
+                mutex_unlock(&crtc->dev->struct_mutex);
+        }
+
+        radeon_crtc->cursor_bo = obj;
+        return 0;
+fail:
+        mutex_lock(&crtc->dev->struct_mutex);
+        drm_gem_object_unreference(obj);
+        mutex_unlock(&crtc->dev->struct_mutex);
+
+        return 0;
+}
+
+int radeon_crtc_cursor_move(struct drm_crtc *crtc,
+                            int x, int y)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct radeon_device *rdev = crtc->dev->dev_private;
+        int xorigin = 0, yorigin = 0;
+
+        if (x < 0)
+                xorigin = -x + 1;
+        if (y < 0)
+                yorigin = -y + 1;
+        if (xorigin >= CURSOR_WIDTH)
+                xorigin = CURSOR_WIDTH - 1;
+        if (yorigin >= CURSOR_HEIGHT)
+                yorigin = CURSOR_HEIGHT - 1;
+
+        radeon_lock_cursor(crtc, true);
+        if (ASIC_IS_AVIVO(rdev)) {
+                int w = radeon_crtc->cursor_width;
+                int i = 0;
+                struct drm_crtc *crtc_p;
+
+                /* avivo cursor are offset into the total surface */
+                x += crtc->x;
+                y += crtc->y;
+                DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
+
+                /* avivo cursor image can't end on 128 pixel boundry or
+                 * go past the end of the frame if both crtcs are enabled
+                 */
+                list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
+                        if (crtc_p->enabled)
+                                i++;
+                }
+                if (i > 1) {
+                        int cursor_end, frame_end;
+
+                        cursor_end = x - xorigin + w;
+                        frame_end = crtc->x + crtc->mode.crtc_hdisplay;
+                        if (cursor_end >= frame_end) {
+                                w = w - (cursor_end - frame_end);
+                                if (!(frame_end & 0x7f))
+                                        w--;
+                        } else {
+                                if (!(cursor_end & 0x7f))
+                                        w--;
+                        }
+                        if (w <= 0)
+                                w = 1;
+                }
+
+                WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
+                             ((xorigin ? 0 : x) << 16) |
+                             (yorigin ? 0 : y));
+                WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
+                WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
+                       ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
+        } else {
+                if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
+                        y *= 2;
+
+                WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
+                       (RADEON_CUR_LOCK
+                        | (xorigin << 16)
+                        | yorigin));
+                WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
+                       (RADEON_CUR_LOCK
+                        | ((xorigin ? 0 : x) << 16)
+                        | (yorigin ? 0 : y)));
+        }
+        radeon_lock_cursor(crtc, false);
+
+        return 0;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
new file mode 100644
index 000000000000..5fd2b639bf66
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -0,0 +1,813 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include <linux/console.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/radeon_drm.h>
+#include "radeon_reg.h"
+#include "radeon.h"
+#include "radeon_asic.h"
+#include "atom.h"
+
+/*
+ * GPU scratch registers helpers function.
+ */
+static void radeon_scratch_init(struct radeon_device *rdev)
+{
+        int i;
+
+        /* FIXME: check this out */
+        if (rdev->family < CHIP_R300) {
+                rdev->scratch.num_reg = 5;
+        } else {
+                rdev->scratch.num_reg = 7;
+        }
+        for (i = 0; i < rdev->scratch.num_reg; i++) {
+                rdev->scratch.free[i] = true;
+                rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
+        }
+}
+
+int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
+{
+        int i;
+
+        for (i = 0; i < rdev->scratch.num_reg; i++) {
+                if (rdev->scratch.free[i]) {
+                        rdev->scratch.free[i] = false;
+                        *reg = rdev->scratch.reg[i];
+                        return 0;
+                }
+        }
+        return -EINVAL;
+}
+
+void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
+{
+        int i;
+
+        for (i = 0; i < rdev->scratch.num_reg; i++) {
+                if (rdev->scratch.reg[i] == reg) {
+                        rdev->scratch.free[i] = true;
+                        return;
+                }
+        }
+}
+
+/*
+ * MC common functions
+ */
+int radeon_mc_setup(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        /* Some chips have an "issue" with the memory controller, the
+         * location must be aligned to the size. We just align it down,
+         * too bad if we walk over the top of system memory, we don't
+         * use DMA without a remapped anyway.
+         * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
+         */
+        /* FGLRX seems to setup like this, VRAM a 0, then GART.
+         */
+        /*
+         * Note: from R6xx the address space is 40bits but here we only
+         * use 32bits (still have to see a card which would exhaust 4G
+         * address space).
+         */
+        if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
+                /* vram location was already setup try to put gtt after
+                 * if it fits */
+                tmp = rdev->mc.vram_location + rdev->mc.vram_size;
+                tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
+                if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
+                        rdev->mc.gtt_location = tmp;
+                } else {
+                        if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
+                                printk(KERN_ERR "[drm] GTT too big to fit "
+                                       "before or after vram location.\n");
+                                return -EINVAL;
+                        }
+                        rdev->mc.gtt_location = 0;
+                }
+        } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
+                /* gtt location was already setup try to put vram before
+                 * if it fits */
+                if (rdev->mc.vram_size < rdev->mc.gtt_location) {
+                        rdev->mc.vram_location = 0;
+                } else {
+                        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
+                        tmp += (rdev->mc.vram_size - 1);
+                        tmp &= ~(rdev->mc.vram_size - 1);
+                        if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
+                                rdev->mc.vram_location = tmp;
+                        } else {
+                                printk(KERN_ERR "[drm] vram too big to fit "
+                                       "before or after GTT location.\n");
+                                return -EINVAL;
+                        }
+                }
+        } else {
+                rdev->mc.vram_location = 0;
+                rdev->mc.gtt_location = rdev->mc.vram_size;
+        }
+        DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
+        DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
+                 rdev->mc.vram_location,
+                 rdev->mc.vram_location + rdev->mc.vram_size - 1);
+        DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
+        DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
+                 rdev->mc.gtt_location,
+                 rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
+        return 0;
+}
+
+
+/*
+ * GPU helpers function.
+ */
+static bool radeon_card_posted(struct radeon_device *rdev)
+{
+        uint32_t reg;
+
+        /* first check CRTCs */
+        if (ASIC_IS_AVIVO(rdev)) {
+                reg = RREG32(AVIVO_D1CRTC_CONTROL) |
+                      RREG32(AVIVO_D2CRTC_CONTROL);
+                if (reg & AVIVO_CRTC_EN) {
+                        return true;
+                }
+        } else {
+                reg = RREG32(RADEON_CRTC_GEN_CNTL) |
+                      RREG32(RADEON_CRTC2_GEN_CNTL);
+                if (reg & RADEON_CRTC_EN) {
+                        return true;
+                }
+        }
+
+        /* then check MEM_SIZE, in case the crtcs are off */
+        if (rdev->family >= CHIP_R600)
+                reg = RREG32(R600_CONFIG_MEMSIZE);
+        else
+                reg = RREG32(RADEON_CONFIG_MEMSIZE);
+
+        if (reg)
+                return true;
+
+        return false;
+
+}
+
+
+/*
+ * Registers accessors functions.
+ */
+uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
+        BUG_ON(1);
+        return 0;
+}
+
+void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
+                  reg, v);
+        BUG_ON(1);
+}
+
+void radeon_register_accessor_init(struct radeon_device *rdev)
+{
+        rdev->mm_rreg = &r100_mm_rreg;
+        rdev->mm_wreg = &r100_mm_wreg;
+        rdev->mc_rreg = &radeon_invalid_rreg;
+        rdev->mc_wreg = &radeon_invalid_wreg;
+        rdev->pll_rreg = &radeon_invalid_rreg;
+        rdev->pll_wreg = &radeon_invalid_wreg;
+        rdev->pcie_rreg = &radeon_invalid_rreg;
+        rdev->pcie_wreg = &radeon_invalid_wreg;
+        rdev->pciep_rreg = &radeon_invalid_rreg;
+        rdev->pciep_wreg = &radeon_invalid_wreg;
+
+        /* Don't change order as we are overridding accessor. */
+        if (rdev->family < CHIP_RV515) {
+                rdev->pcie_rreg = &rv370_pcie_rreg;
+                rdev->pcie_wreg = &rv370_pcie_wreg;
+        }
+        if (rdev->family >= CHIP_RV515) {
+                rdev->pcie_rreg = &rv515_pcie_rreg;
+                rdev->pcie_wreg = &rv515_pcie_wreg;
+        }
+        /* FIXME: not sure here */
+        if (rdev->family <= CHIP_R580) {
+                rdev->pll_rreg = &r100_pll_rreg;
+                rdev->pll_wreg = &r100_pll_wreg;
+        }
+        if (rdev->family >= CHIP_RV515) {
+                rdev->mc_rreg = &rv515_mc_rreg;
+                rdev->mc_wreg = &rv515_mc_wreg;
+        }
+        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
+                rdev->mc_rreg = &rs400_mc_rreg;
+                rdev->mc_wreg = &rs400_mc_wreg;
+        }
+        if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
+                rdev->mc_rreg = &rs690_mc_rreg;
+                rdev->mc_wreg = &rs690_mc_wreg;
+        }
+        if (rdev->family == CHIP_RS600) {
+                rdev->mc_rreg = &rs600_mc_rreg;
+                rdev->mc_wreg = &rs600_mc_wreg;
+        }
+        if (rdev->family >= CHIP_R600) {
+                rdev->pciep_rreg = &r600_pciep_rreg;
+                rdev->pciep_wreg = &r600_pciep_wreg;
+        }
+}
+
+
+/*
+ * ASIC
+ */
+int radeon_asic_init(struct radeon_device *rdev)
+{
+        radeon_register_accessor_init(rdev);
+        switch (rdev->family) {
+        case CHIP_R100:
+        case CHIP_RV100:
+        case CHIP_RS100:
+        case CHIP_RV200:
+        case CHIP_RS200:
+        case CHIP_R200:
+        case CHIP_RV250:
+        case CHIP_RS300:
+        case CHIP_RV280:
+                rdev->asic = &r100_asic;
+                break;
+        case CHIP_R300:
+        case CHIP_R350:
+        case CHIP_RV350:
+        case CHIP_RV380:
+                rdev->asic = &r300_asic;
+                break;
+        case CHIP_R420:
+        case CHIP_R423:
+        case CHIP_RV410:
+                rdev->asic = &r420_asic;
+                break;
+        case CHIP_RS400:
+        case CHIP_RS480:
+                rdev->asic = &rs400_asic;
+                break;
+        case CHIP_RS600:
+                rdev->asic = &rs600_asic;
+                break;
+        case CHIP_RS690:
+        case CHIP_RS740:
+                rdev->asic = &rs690_asic;
+                break;
+        case CHIP_RV515:
+                rdev->asic = &rv515_asic;
+                break;
+        case CHIP_R520:
+        case CHIP_RV530:
+        case CHIP_RV560:
+        case CHIP_RV570:
+        case CHIP_R580:
+                rdev->asic = &r520_asic;
+                break;
+        case CHIP_R600:
+        case CHIP_RV610:
+        case CHIP_RV630:
+        case CHIP_RV620:
+        case CHIP_RV635:
+        case CHIP_RV670:
+        case CHIP_RS780:
+        case CHIP_RV770:
+        case CHIP_RV730:
+        case CHIP_RV710:
+        default:
+                /* FIXME: not supported yet */
+                return -EINVAL;
+        }
+        return 0;
+}
+
+
+/*
+ * Wrapper around modesetting bits.
+ */
+int radeon_clocks_init(struct radeon_device *rdev)
+{
+        int r;
+
+        radeon_get_clock_info(rdev->ddev);
+        r = radeon_static_clocks_init(rdev->ddev);
+        if (r) {
+                return r;
+        }
+        DRM_INFO("Clocks initialized !\n");
+        return 0;
+}
+
+void radeon_clocks_fini(struct radeon_device *rdev)
+{
+}
+
+/* ATOM accessor methods */
+static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
+{
+        struct radeon_device *rdev = info->dev->dev_private;
+        uint32_t r;
+
+        r = rdev->pll_rreg(rdev, reg);
+        return r;
+}
+
+static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
+{
+        struct radeon_device *rdev = info->dev->dev_private;
+
+        rdev->pll_wreg(rdev, reg, val);
+}
+
+static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
+{
+        struct radeon_device *rdev = info->dev->dev_private;
+        uint32_t r;
+
+        r = rdev->mc_rreg(rdev, reg);
+        return r;
+}
+
+static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
+{
+        struct radeon_device *rdev = info->dev->dev_private;
+
+        rdev->mc_wreg(rdev, reg, val);
+}
+
+static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
+{
+        struct radeon_device *rdev = info->dev->dev_private;
+
+        WREG32(reg*4, val);
+}
+
+static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
+{
+        struct radeon_device *rdev = info->dev->dev_private;
+        uint32_t r;
+
+        r = RREG32(reg*4);
+        return r;
+}
+
+static struct card_info atom_card_info = {
+        .dev = NULL,
+        .reg_read = cail_reg_read,
+        .reg_write = cail_reg_write,
+        .mc_read = cail_mc_read,
+        .mc_write = cail_mc_write,
+        .pll_read = cail_pll_read,
+        .pll_write = cail_pll_write,
+};
+
+int radeon_atombios_init(struct radeon_device *rdev)
+{
+        atom_card_info.dev = rdev->ddev;
+        rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
+        radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
+        return 0;
+}
+
+void radeon_atombios_fini(struct radeon_device *rdev)
+{
+        kfree(rdev->mode_info.atom_context);
+}
+
+int radeon_combios_init(struct radeon_device *rdev)
+{
+        radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
+        return 0;
+}
+
+void radeon_combios_fini(struct radeon_device *rdev)
+{
+}
+
+int radeon_modeset_init(struct radeon_device *rdev);
+void radeon_modeset_fini(struct radeon_device *rdev);
+
+
+/*
+ * Radeon device.
+ */
+int radeon_device_init(struct radeon_device *rdev,
+                       struct drm_device *ddev,
+                       struct pci_dev *pdev,
+                       uint32_t flags)
+{
+        int r, ret;
+
+        DRM_INFO("radeon: Initializing kernel modesetting.\n");
+        rdev->shutdown = false;
+        rdev->ddev = ddev;
+        rdev->pdev = pdev;
+        rdev->flags = flags;
+        rdev->family = flags & RADEON_FAMILY_MASK;
+        rdev->is_atom_bios = false;
+        rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
+        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+        rdev->gpu_lockup = false;
+        /* mutex initialization are all done here so we
+         * can recall function without having locking issues */
+        mutex_init(&rdev->cs_mutex);
+        mutex_init(&rdev->ib_pool.mutex);
+        mutex_init(&rdev->cp.mutex);
+        rwlock_init(&rdev->fence_drv.lock);
+
+        if (radeon_agpmode == -1) {
+                rdev->flags &= ~RADEON_IS_AGP;
+                if (rdev->family > CHIP_RV515 ||
+                    rdev->family == CHIP_RV380 ||
+                    rdev->family == CHIP_RV410 ||
+                    rdev->family == CHIP_R423) {
+                        DRM_INFO("Forcing AGP to PCIE mode\n");
+                        rdev->flags |= RADEON_IS_PCIE;
+                } else {
+                        DRM_INFO("Forcing AGP to PCI mode\n");
+                        rdev->flags |= RADEON_IS_PCI;
+                }
+        }
+
+        /* Set asic functions */
+        r = radeon_asic_init(rdev);
+        if (r) {
+                return r;
+        }
+
+        /* Report DMA addressing limitation */
+        r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
+        if (r) {
+                printk(KERN_WARNING "radeon: No suitable DMA available.\n");
+        }
+
+        /* Registers mapping */
+        /* TODO: block userspace mapping of io register */
+        rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
+        rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
+        rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
+        if (rdev->rmmio == NULL) {
+                return -ENOMEM;
+        }
+        DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
+        DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
+
+        /* Setup errata flags */
+        radeon_errata(rdev);
+        /* Initialize scratch registers */
+        radeon_scratch_init(rdev);
+
+        /* TODO: disable VGA need to use VGA request */
+        /* BIOS*/
+        if (!radeon_get_bios(rdev)) {
+                if (ASIC_IS_AVIVO(rdev))
+                        return -EINVAL;
+        }
+        if (rdev->is_atom_bios) {
+                r = radeon_atombios_init(rdev);
+                if (r) {
+                        return r;
+                }
+        } else {
+                r = radeon_combios_init(rdev);
+                if (r) {
+                        return r;
+                }
+        }
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                /* FIXME: what do we want to do here ? */
+        }
+        /* check if cards are posted or not */
+        if (!radeon_card_posted(rdev) && rdev->bios) {
+                DRM_INFO("GPU not posted. posting now...\n");
+                if (rdev->is_atom_bios) {
+                        atom_asic_init(rdev->mode_info.atom_context);
+                } else {
+                        radeon_combios_asic_init(rdev->ddev);
+                }
+        }
+        /* Get vram informations */
+        radeon_vram_info(rdev);
+        /* Device is severly broken if aper size > vram size.
+         * for RN50/M6/M7 - Novell bug 204882 ?
+         */
+        if (rdev->mc.vram_size < rdev->mc.aper_size) {
+                rdev->mc.aper_size = rdev->mc.vram_size;
+        }
+        /* Add an MTRR for the VRAM */
+        rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
+                                      MTRR_TYPE_WRCOMB, 1);
+        DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
+                 rdev->mc.vram_size >> 20,
+                 (unsigned)rdev->mc.aper_size >> 20);
+        DRM_INFO("RAM width %dbits %cDR\n",
+                 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
+        /* Initialize clocks */
+        r = radeon_clocks_init(rdev);
+        if (r) {
+                return r;
+        }
+        /* Initialize memory controller (also test AGP) */
+        r = radeon_mc_init(rdev);
+        if (r) {
+                return r;
+        }
+        /* Fence driver */
+        r = radeon_fence_driver_init(rdev);
+        if (r) {
+                return r;
+        }
+        r = radeon_irq_kms_init(rdev);
+        if (r) {
+                return r;
+        }
+        /* Memory manager */
+        r = radeon_object_init(rdev);
+        if (r) {
+                return r;
+        }
+        /* Initialize GART (initialize after TTM so we can allocate
+         * memory through TTM but finalize after TTM) */
+        r = radeon_gart_enable(rdev);
+        if (!r) {
+                r = radeon_gem_init(rdev);
+        }
+
+        /* 1M ring buffer */
+        if (!r) {
+                r = radeon_cp_init(rdev, 1024 * 1024);
+        }
+        if (!r) {
+                r = radeon_wb_init(rdev);
+                if (r) {
+                        DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
+                        return r;
+                }
+        }
+        if (!r) {
+                r = radeon_ib_pool_init(rdev);
+                if (r) {
+                        DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
+                        return r;
+                }
+        }
+        if (!r) {
+                r = radeon_ib_test(rdev);
+                if (r) {
+                        DRM_ERROR("radeon: failled testing IB (%d).\n", r);
+                        return r;
+                }
+        }
+        ret = r;
+        r = radeon_modeset_init(rdev);
+        if (r) {
+                return r;
+        }
+        if (rdev->fbdev_rfb && rdev->fbdev_rfb->obj) {
+                rdev->fbdev_robj = rdev->fbdev_rfb->obj->driver_private;
+        }
+        if (!ret) {
+                DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
+        }
+        if (radeon_benchmarking) {
+                radeon_benchmark(rdev);
+        }
+        return ret;
+}
+
+void radeon_device_fini(struct radeon_device *rdev)
+{
+        if (rdev == NULL || rdev->rmmio == NULL) {
+                return;
+        }
+        DRM_INFO("radeon: finishing device.\n");
+        rdev->shutdown = true;
+        /* Order matter so becarefull if you rearrange anythings */
+        radeon_modeset_fini(rdev);
+        radeon_ib_pool_fini(rdev);
+        radeon_cp_fini(rdev);
+        radeon_wb_fini(rdev);
+        radeon_gem_fini(rdev);
+        radeon_object_fini(rdev);
+        /* mc_fini must be after object_fini */
+        radeon_mc_fini(rdev);
+#if __OS_HAS_AGP
+        radeon_agp_fini(rdev);
+#endif
+        radeon_irq_kms_fini(rdev);
+        radeon_fence_driver_fini(rdev);
+        radeon_clocks_fini(rdev);
+        if (rdev->is_atom_bios) {
+                radeon_atombios_fini(rdev);
+        } else {
+                radeon_combios_fini(rdev);
+        }
+        kfree(rdev->bios);
+        rdev->bios = NULL;
+        iounmap(rdev->rmmio);
+        rdev->rmmio = NULL;
+}
+
+
+/*
+ * Suspend & resume.
+ */
+int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_crtc *crtc;
+
+        if (dev == NULL || rdev == NULL) {
+                return -ENODEV;
+        }
+        if (state.event == PM_EVENT_PRETHAW) {
+                return 0;
+        }
+        /* unpin the front buffers */
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
+                struct radeon_object *robj;
+
+                if (rfb == NULL || rfb->obj == NULL) {
+                        continue;
+                }
+                robj = rfb->obj->driver_private;
+                if (robj != rdev->fbdev_robj) {
+                        radeon_object_unpin(robj);
+                }
+        }
+        /* evict vram memory */
+        radeon_object_evict_vram(rdev);
+        /* wait for gpu to finish processing current batch */
+        radeon_fence_wait_last(rdev);
+
+        radeon_cp_disable(rdev);
+        radeon_gart_disable(rdev);
+
+        /* evict remaining vram memory */
+        radeon_object_evict_vram(rdev);
+
+        rdev->irq.sw_int = false;
+        radeon_irq_set(rdev);
+
+        pci_save_state(dev->pdev);
+        if (state.event == PM_EVENT_SUSPEND) {
+                /* Shut down the device */
+                pci_disable_device(dev->pdev);
+                pci_set_power_state(dev->pdev, PCI_D3hot);
+        }
+        acquire_console_sem();
+        fb_set_suspend(rdev->fbdev_info, 1);
+        release_console_sem();
+        return 0;
+}
+
+int radeon_resume_kms(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        int r;
+
+        acquire_console_sem();
+        pci_set_power_state(dev->pdev, PCI_D0);
+        pci_restore_state(dev->pdev);
+        if (pci_enable_device(dev->pdev)) {
+                release_console_sem();
+                return -1;
+        }
+        pci_set_master(dev->pdev);
+        /* Reset gpu before posting otherwise ATOM will enter infinite loop */
+        if (radeon_gpu_reset(rdev)) {
+                /* FIXME: what do we want to do here ? */
+        }
+        /* post card */
+        if (rdev->is_atom_bios) {
+                atom_asic_init(rdev->mode_info.atom_context);
+        } else {
+                radeon_combios_asic_init(rdev->ddev);
+        }
+        /* Initialize clocks */
+        r = radeon_clocks_init(rdev);
+        if (r) {
+                release_console_sem();
+                return r;
+        }
+        /* Enable IRQ */
+        rdev->irq.sw_int = true;
+        radeon_irq_set(rdev);
+        /* Initialize GPU Memory Controller */
+        r = radeon_mc_init(rdev);
+        if (r) {
+                goto out;
+        }
+        r = radeon_gart_enable(rdev);
+        if (r) {
+                goto out;
+        }
+        r = radeon_cp_init(rdev, rdev->cp.ring_size);
+        if (r) {
+                goto out;
+        }
+out:
+        fb_set_suspend(rdev->fbdev_info, 0);
+        release_console_sem();
+
+        /* blat the mode back in */
+        drm_helper_resume_force_mode(dev);
+        return 0;
+}
+
+
+/*
+ * Debugfs
+ */
+struct radeon_debugfs {
+        struct drm_info_list    *files;
+        unsigned                num_files;
+};
+static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
+static unsigned _radeon_debugfs_count = 0;
+
+int radeon_debugfs_add_files(struct radeon_device *rdev,
+                             struct drm_info_list *files,
+                             unsigned nfiles)
+{
+        unsigned i;
+
+        for (i = 0; i < _radeon_debugfs_count; i++) {
+                if (_radeon_debugfs[i].files == files) {
+                        /* Already registered */
+                        return 0;
+                }
+        }
+        if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
+                DRM_ERROR("Reached maximum number of debugfs files.\n");
+                DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
+                return -EINVAL;
+        }
+        _radeon_debugfs[_radeon_debugfs_count].files = files;
+        _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
+        _radeon_debugfs_count++;
+#if defined(CONFIG_DEBUG_FS)
+        drm_debugfs_create_files(files, nfiles,
+                                 rdev->ddev->control->debugfs_root,
+                                 rdev->ddev->control);
+        drm_debugfs_create_files(files, nfiles,
+                                 rdev->ddev->primary->debugfs_root,
+                                 rdev->ddev->primary);
+#endif
+        return 0;
+}
+
+#if defined(CONFIG_DEBUG_FS)
+int radeon_debugfs_init(struct drm_minor *minor)
+{
+        return 0;
+}
+
+void radeon_debugfs_cleanup(struct drm_minor *minor)
+{
+        unsigned i;
+
+        for (i = 0; i < _radeon_debugfs_count; i++) {
+                drm_debugfs_remove_files(_radeon_debugfs[i].files,
+                                         _radeon_debugfs[i].num_files, minor);
+        }
+}
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
new file mode 100644
index 000000000000..5452bb9d925e
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -0,0 +1,692 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+
+#include "atom.h"
+#include <asm/div64.h>
+
+#include "drm_crtc_helper.h"
+#include "drm_edid.h"
+
+static int radeon_ddc_dump(struct drm_connector *connector);
+
+static void avivo_crtc_load_lut(struct drm_crtc *crtc)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        int i;
+
+        DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
+        WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
+
+        WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
+        WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
+        WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
+
+        WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
+        WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
+        WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
+
+        WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
+        WREG32(AVIVO_DC_LUT_RW_MODE, 0);
+        WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
+
+        WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
+        for (i = 0; i < 256; i++) {
+                WREG32(AVIVO_DC_LUT_30_COLOR,
+                             (radeon_crtc->lut_r[i] << 20) |
+                             (radeon_crtc->lut_g[i] << 10) |
+                             (radeon_crtc->lut_b[i] << 0));
+        }
+
+        WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
+}
+
+static void legacy_crtc_load_lut(struct drm_crtc *crtc)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        int i;
+        uint32_t dac2_cntl;
+
+        dac2_cntl = RREG32(RADEON_DAC_CNTL2);
+        if (radeon_crtc->crtc_id == 0)
+                dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
+        else
+                dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
+        WREG32(RADEON_DAC_CNTL2, dac2_cntl);
+
+        WREG8(RADEON_PALETTE_INDEX, 0);
+        for (i = 0; i < 256; i++) {
+                WREG32(RADEON_PALETTE_30_DATA,
+                             (radeon_crtc->lut_r[i] << 20) |
+                             (radeon_crtc->lut_g[i] << 10) |
+                             (radeon_crtc->lut_b[i] << 0));
+        }
+}
+
+void radeon_crtc_load_lut(struct drm_crtc *crtc)
+{
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+
+        if (!crtc->enabled)
+                return;
+
+        if (ASIC_IS_AVIVO(rdev))
+                avivo_crtc_load_lut(crtc);
+        else
+                legacy_crtc_load_lut(crtc);
+}
+
+/** Sets the color ramps on behalf of RandR */
+void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
+                              u16 blue, int regno)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+
+        if (regno == 0)
+                DRM_DEBUG("gamma set %d\n", radeon_crtc->crtc_id);
+        radeon_crtc->lut_r[regno] = red >> 6;
+        radeon_crtc->lut_g[regno] = green >> 6;
+        radeon_crtc->lut_b[regno] = blue >> 6;
+}
+
+static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
+                                  u16 *blue, uint32_t size)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        int i, j;
+
+        if (size != 256) {
+                return;
+        }
+        if (crtc->fb == NULL) {
+                return;
+        }
+
+        if (crtc->fb->depth == 16) {
+                for (i = 0; i < 64; i++) {
+                        if (i <= 31) {
+                                for (j = 0; j < 8; j++) {
+                                        radeon_crtc->lut_r[i * 8 + j] = red[i] >> 6;
+                                        radeon_crtc->lut_b[i * 8 + j] = blue[i] >> 6;
+                                }
+                        }
+                        for (j = 0; j < 4; j++)
+                                radeon_crtc->lut_g[i * 4 + j] = green[i] >> 6;
+                }
+        } else {
+                for (i = 0; i < 256; i++) {
+                        radeon_crtc->lut_r[i] = red[i] >> 6;
+                        radeon_crtc->lut_g[i] = green[i] >> 6;
+                        radeon_crtc->lut_b[i] = blue[i] >> 6;
+                }
+        }
+
+        radeon_crtc_load_lut(crtc);
+}
+
+static void radeon_crtc_destroy(struct drm_crtc *crtc)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+
+        if (radeon_crtc->mode_set.mode) {
+                drm_mode_destroy(crtc->dev, radeon_crtc->mode_set.mode);
+        }
+        drm_crtc_cleanup(crtc);
+        kfree(radeon_crtc);
+}
+
+static const struct drm_crtc_funcs radeon_crtc_funcs = {
+        .cursor_set = radeon_crtc_cursor_set,
+        .cursor_move = radeon_crtc_cursor_move,
+        .gamma_set = radeon_crtc_gamma_set,
+        .set_config = drm_crtc_helper_set_config,
+        .destroy = radeon_crtc_destroy,
+};
+
+static void radeon_crtc_init(struct drm_device *dev, int index)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc;
+        int i;
+
+        radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
+        if (radeon_crtc == NULL)
+                return;
+
+        drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
+
+        drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
+        radeon_crtc->crtc_id = index;
+
+        radeon_crtc->mode_set.crtc = &radeon_crtc->base;
+        radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
+        radeon_crtc->mode_set.num_connectors = 0;
+
+        for (i = 0; i < 256; i++) {
+                radeon_crtc->lut_r[i] = i << 2;
+                radeon_crtc->lut_g[i] = i << 2;
+                radeon_crtc->lut_b[i] = i << 2;
+        }
+
+        if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
+                radeon_atombios_init_crtc(dev, radeon_crtc);
+        else
+                radeon_legacy_init_crtc(dev, radeon_crtc);
+}
+
+static const char *encoder_names[34] = {
+        "NONE",
+        "INTERNAL_LVDS",
+        "INTERNAL_TMDS1",
+        "INTERNAL_TMDS2",
+        "INTERNAL_DAC1",
+        "INTERNAL_DAC2",
+        "INTERNAL_SDVOA",
+        "INTERNAL_SDVOB",
+        "SI170B",
+        "CH7303",
+        "CH7301",
+        "INTERNAL_DVO1",
+        "EXTERNAL_SDVOA",
+        "EXTERNAL_SDVOB",
+        "TITFP513",
+        "INTERNAL_LVTM1",
+        "VT1623",
+        "HDMI_SI1930",
+        "HDMI_INTERNAL",
+        "INTERNAL_KLDSCP_TMDS1",
+        "INTERNAL_KLDSCP_DVO1",
+        "INTERNAL_KLDSCP_DAC1",
+        "INTERNAL_KLDSCP_DAC2",
+        "SI178",
+        "MVPU_FPGA",
+        "INTERNAL_DDI",
+        "VT1625",
+        "HDMI_SI1932",
+        "DP_AN9801",
+        "DP_DP501",
+        "INTERNAL_UNIPHY",
+        "INTERNAL_KLDSCP_LVTMA",
+        "INTERNAL_UNIPHY1",
+        "INTERNAL_UNIPHY2",
+};
+
+static const char *connector_names[13] = {
+        "Unknown",
+        "VGA",
+        "DVI-I",
+        "DVI-D",
+        "DVI-A",
+        "Composite",
+        "S-video",
+        "LVDS",
+        "Component",
+        "DIN",
+        "DisplayPort",
+        "HDMI-A",
+        "HDMI-B",
+};
+
+static void radeon_print_display_setup(struct drm_device *dev)
+{
+        struct drm_connector *connector;
+        struct radeon_connector *radeon_connector;
+        struct drm_encoder *encoder;
+        struct radeon_encoder *radeon_encoder;
+        uint32_t devices;
+        int i = 0;
+
+        DRM_INFO("Radeon Display Connectors\n");
+        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+                radeon_connector = to_radeon_connector(connector);
+                DRM_INFO("Connector %d:\n", i);
+                DRM_INFO("  %s\n", connector_names[connector->connector_type]);
+                if (radeon_connector->ddc_bus)
+                        DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+                                 radeon_connector->ddc_bus->rec.mask_clk_reg,
+                                 radeon_connector->ddc_bus->rec.mask_data_reg,
+                                 radeon_connector->ddc_bus->rec.a_clk_reg,
+                                 radeon_connector->ddc_bus->rec.a_data_reg,
+                                 radeon_connector->ddc_bus->rec.put_clk_reg,
+                                 radeon_connector->ddc_bus->rec.put_data_reg,
+                                 radeon_connector->ddc_bus->rec.get_clk_reg,
+                                 radeon_connector->ddc_bus->rec.get_data_reg);
+                DRM_INFO("  Encoders:\n");
+                list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                        radeon_encoder = to_radeon_encoder(encoder);
+                        devices = radeon_encoder->devices & radeon_connector->devices;
+                        if (devices) {
+                                if (devices & ATOM_DEVICE_CRT1_SUPPORT)
+                                        DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
+                                if (devices & ATOM_DEVICE_CRT2_SUPPORT)
+                                        DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
+                                if (devices & ATOM_DEVICE_LCD1_SUPPORT)
+                                        DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
+                                if (devices & ATOM_DEVICE_DFP1_SUPPORT)
+                                        DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
+                                if (devices & ATOM_DEVICE_DFP2_SUPPORT)
+                                        DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
+                                if (devices & ATOM_DEVICE_DFP3_SUPPORT)
+                                        DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
+                                if (devices & ATOM_DEVICE_DFP4_SUPPORT)
+                                        DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
+                                if (devices & ATOM_DEVICE_DFP5_SUPPORT)
+                                        DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
+                                if (devices & ATOM_DEVICE_TV1_SUPPORT)
+                                        DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
+                                if (devices & ATOM_DEVICE_CV_SUPPORT)
+                                        DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
+                        }
+                }
+                i++;
+        }
+}
+
+bool radeon_setup_enc_conn(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_connector *drm_connector;
+        bool ret = false;
+
+        if (rdev->bios) {
+                if (rdev->is_atom_bios) {
+                        if (rdev->family >= CHIP_R600)
+                                ret = radeon_get_atom_connector_info_from_object_table(dev);
+                        else
+                                ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
+                } else
+                        ret = radeon_get_legacy_connector_info_from_bios(dev);
+        } else {
+                if (!ASIC_IS_AVIVO(rdev))
+                        ret = radeon_get_legacy_connector_info_from_table(dev);
+        }
+        if (ret) {
+                radeon_print_display_setup(dev);
+                list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
+                        radeon_ddc_dump(drm_connector);
+        }
+
+        return ret;
+}
+
+int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
+{
+        struct edid *edid;
+        int ret = 0;
+
+        if (!radeon_connector->ddc_bus)
+                return -1;
+        radeon_i2c_do_lock(radeon_connector, 1);
+        edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
+        radeon_i2c_do_lock(radeon_connector, 0);
+        if (edid) {
+                /* update digital bits here */
+                if (edid->digital)
+                        radeon_connector->use_digital = 1;
+                else
+                        radeon_connector->use_digital = 0;
+                drm_mode_connector_update_edid_property(&radeon_connector->base, edid);
+                ret = drm_add_edid_modes(&radeon_connector->base, edid);
+                kfree(edid);
+                return ret;
+        }
+        drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
+        return -1;
+}
+
+static int radeon_ddc_dump(struct drm_connector *connector)
+{
+        struct edid *edid;
+        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+        int ret = 0;
+
+        if (!radeon_connector->ddc_bus)
+                return -1;
+        radeon_i2c_do_lock(radeon_connector, 1);
+        edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
+        radeon_i2c_do_lock(radeon_connector, 0);
+        if (edid) {
+                kfree(edid);
+        }
+        return ret;
+}
+
+static inline uint32_t radeon_div(uint64_t n, uint32_t d)
+{
+        uint64_t mod;
+
+        n += d / 2;
+
+        mod = do_div(n, d);
+        return n;
+}
+
+void radeon_compute_pll(struct radeon_pll *pll,
+                        uint64_t freq,
+                        uint32_t *dot_clock_p,
+                        uint32_t *fb_div_p,
+                        uint32_t *frac_fb_div_p,
+                        uint32_t *ref_div_p,
+                        uint32_t *post_div_p,
+                        int flags)
+{
+        uint32_t min_ref_div = pll->min_ref_div;
+        uint32_t max_ref_div = pll->max_ref_div;
+        uint32_t min_fractional_feed_div = 0;
+        uint32_t max_fractional_feed_div = 0;
+        uint32_t best_vco = pll->best_vco;
+        uint32_t best_post_div = 1;
+        uint32_t best_ref_div = 1;
+        uint32_t best_feedback_div = 1;
+        uint32_t best_frac_feedback_div = 0;
+        uint32_t best_freq = -1;
+        uint32_t best_error = 0xffffffff;
+        uint32_t best_vco_diff = 1;
+        uint32_t post_div;
+
+        DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
+        freq = freq * 1000;
+
+        if (flags & RADEON_PLL_USE_REF_DIV)
+                min_ref_div = max_ref_div = pll->reference_div;
+        else {
+                while (min_ref_div < max_ref_div-1) {
+                        uint32_t mid = (min_ref_div + max_ref_div) / 2;
+                        uint32_t pll_in = pll->reference_freq / mid;
+                        if (pll_in < pll->pll_in_min)
+                                max_ref_div = mid;
+                        else if (pll_in > pll->pll_in_max)
+                                min_ref_div = mid;
+                        else
+                                break;
+                }
+        }
+
+        if (flags & RADEON_PLL_USE_FRAC_FB_DIV) {
+                min_fractional_feed_div = pll->min_frac_feedback_div;
+                max_fractional_feed_div = pll->max_frac_feedback_div;
+        }
+
+        for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) {
+                uint32_t ref_div;
+
+                if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
+                        continue;
+
+                /* legacy radeons only have a few post_divs */
+                if (flags & RADEON_PLL_LEGACY) {
+                        if ((post_div == 5) ||
+                            (post_div == 7) ||
+                            (post_div == 9) ||
+                            (post_div == 10) ||
+                            (post_div == 11) ||
+                            (post_div == 13) ||
+                            (post_div == 14) ||
+                            (post_div == 15))
+                                continue;
+                }
+
+                for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
+                        uint32_t feedback_div, current_freq = 0, error, vco_diff;
+                        uint32_t pll_in = pll->reference_freq / ref_div;
+                        uint32_t min_feed_div = pll->min_feedback_div;
+                        uint32_t max_feed_div = pll->max_feedback_div + 1;
+
+                        if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
+                                continue;
+
+                        while (min_feed_div < max_feed_div) {
+                                uint32_t vco;
+                                uint32_t min_frac_feed_div = min_fractional_feed_div;
+                                uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
+                                uint32_t frac_feedback_div;
+                                uint64_t tmp;
+
+                                feedback_div = (min_feed_div + max_feed_div) / 2;
+
+                                tmp = (uint64_t)pll->reference_freq * feedback_div;
+                                vco = radeon_div(tmp, ref_div);
+
+                                if (vco < pll->pll_out_min) {
+                                        min_feed_div = feedback_div + 1;
+                                        continue;
+                                } else if (vco > pll->pll_out_max) {
+                                        max_feed_div = feedback_div;
+                                        continue;
+                                }
+
+                                while (min_frac_feed_div < max_frac_feed_div) {
+                                        frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
+                                        tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
+                                        tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
+                                        current_freq = radeon_div(tmp, ref_div * post_div);
+
+                                        error = abs(current_freq - freq);
+                                        vco_diff = abs(vco - best_vco);
+
+                                        if ((best_vco == 0 && error < best_error) ||
+                                            (best_vco != 0 &&
+                                             (error < best_error - 100 ||
+                                              (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
+                                                best_post_div = post_div;
+                                                best_ref_div = ref_div;
+                                                best_feedback_div = feedback_div;
+                                                best_frac_feedback_div = frac_feedback_div;
+                                                best_freq = current_freq;
+                                                best_error = error;
+                                                best_vco_diff = vco_diff;
+                                        } else if (current_freq == freq) {
+                                                if (best_freq == -1) {
+                                                        best_post_div = post_div;
+                                                        best_ref_div = ref_div;
+                                                        best_feedback_div = feedback_div;
+                                                        best_frac_feedback_div = frac_feedback_div;
+                                                        best_freq = current_freq;
+                                                        best_error = error;
+                                                        best_vco_diff = vco_diff;
+                                                } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
+                                                           ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
+                                                           ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
+                                                           ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
+                                                           ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
+                                                           ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
+                                                        best_post_div = post_div;
+                                                        best_ref_div = ref_div;
+                                                        best_feedback_div = feedback_div;
+                                                        best_frac_feedback_div = frac_feedback_div;
+                                                        best_freq = current_freq;
+                                                        best_error = error;
+                                                        best_vco_diff = vco_diff;
+                                                }
+                                        }
+                                        if (current_freq < freq)
+                                                min_frac_feed_div = frac_feedback_div + 1;
+                                        else
+                                                max_frac_feed_div = frac_feedback_div;
+                                }
+                                if (current_freq < freq)
+                                        min_feed_div = feedback_div + 1;
+                                else
+                                        max_feed_div = feedback_div;
+                        }
+                }
+        }
+
+        *dot_clock_p = best_freq / 10000;
+        *fb_div_p = best_feedback_div;
+        *frac_fb_div_p = best_frac_feedback_div;
+        *ref_div_p = best_ref_div;
+        *post_div_p = best_post_div;
+}
+
+static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
+{
+        struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
+        struct drm_device *dev = fb->dev;
+
+        if (fb->fbdev)
+                radeonfb_remove(dev, fb);
+
+        if (radeon_fb->obj) {
+                radeon_gem_object_unpin(radeon_fb->obj);
+                mutex_lock(&dev->struct_mutex);
+                drm_gem_object_unreference(radeon_fb->obj);
+                mutex_unlock(&dev->struct_mutex);
+        }
+        drm_framebuffer_cleanup(fb);
+        kfree(radeon_fb);
+}
+
+static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
+                                                  struct drm_file *file_priv,
+                                                  unsigned int *handle)
+{
+        struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
+
+        return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
+}
+
+static const struct drm_framebuffer_funcs radeon_fb_funcs = {
+        .destroy = radeon_user_framebuffer_destroy,
+        .create_handle = radeon_user_framebuffer_create_handle,
+};
+
+struct drm_framebuffer *
+radeon_framebuffer_create(struct drm_device *dev,
+                          struct drm_mode_fb_cmd *mode_cmd,
+                          struct drm_gem_object *obj)
+{
+        struct radeon_framebuffer *radeon_fb;
+
+        radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
+        if (radeon_fb == NULL) {
+                return NULL;
+        }
+        drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
+        drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
+        radeon_fb->obj = obj;
+        return &radeon_fb->base;
+}
+
+static struct drm_framebuffer *
+radeon_user_framebuffer_create(struct drm_device *dev,
+                               struct drm_file *file_priv,
+                               struct drm_mode_fb_cmd *mode_cmd)
+{
+        struct drm_gem_object *obj;
+
+        obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
+
+        return radeon_framebuffer_create(dev, mode_cmd, obj);
+}
+
+static const struct drm_mode_config_funcs radeon_mode_funcs = {
+        .fb_create = radeon_user_framebuffer_create,
+        .fb_changed = radeonfb_probe,
+};
+
+int radeon_modeset_init(struct radeon_device *rdev)
+{
+        int num_crtc = 2, i;
+        int ret;
+
+        drm_mode_config_init(rdev->ddev);
+        rdev->mode_info.mode_config_initialized = true;
+
+        rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
+
+        if (ASIC_IS_AVIVO(rdev)) {
+                rdev->ddev->mode_config.max_width = 8192;
+                rdev->ddev->mode_config.max_height = 8192;
+        } else {
+                rdev->ddev->mode_config.max_width = 4096;
+                rdev->ddev->mode_config.max_height = 4096;
+        }
+
+        rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
+
+        /* allocate crtcs - TODO single crtc */
+        for (i = 0; i < num_crtc; i++) {
+                radeon_crtc_init(rdev->ddev, i);
+        }
+
+        /* okay we should have all the bios connectors */
+        ret = radeon_setup_enc_conn(rdev->ddev);
+        if (!ret) {
+                return ret;
+        }
+        drm_helper_initial_config(rdev->ddev);
+        return 0;
+}
+
+void radeon_modeset_fini(struct radeon_device *rdev)
+{
+        if (rdev->mode_info.mode_config_initialized) {
+                drm_mode_config_cleanup(rdev->ddev);
+                rdev->mode_info.mode_config_initialized = false;
+        }
+}
+
+void radeon_init_disp_bandwidth(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_display_mode *modes[2];
+        int pixel_bytes[2];
+        struct drm_crtc *crtc;
+
+        pixel_bytes[0] = pixel_bytes[1] = 0;
+        modes[0] = modes[1] = NULL;
+
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+
+                if (crtc->enabled && crtc->fb) {
+                        modes[radeon_crtc->crtc_id] = &crtc->mode;
+                        pixel_bytes[radeon_crtc->crtc_id] = crtc->fb->bits_per_pixel / 8;
+                }
+        }
+
+        if (ASIC_IS_AVIVO(rdev)) {
+                radeon_init_disp_bw_avivo(dev,
+                                          modes[0],
+                                          pixel_bytes[0],
+                                          modes[1],
+                                          pixel_bytes[1]);
+        } else {
+                radeon_init_disp_bw_legacy(dev,
+                                           modes[0],
+                                           pixel_bytes[0],
+                                           modes[1],
+                                           pixel_bytes[1]);
+        }
+}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 13a60f4d4227..c815a2cbf7b3 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -35,12 +35,92 @@
 #include "radeon_drv.h"
 
 #include "drm_pciids.h"
+#include <linux/console.h>
+
+
+#if defined(CONFIG_DRM_RADEON_KMS)
+/*
+ * KMS wrapper.
+ */
+#define KMS_DRIVER_MAJOR        2
+#define KMS_DRIVER_MINOR        0
+#define KMS_DRIVER_PATCHLEVEL   0
+int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
+int radeon_driver_unload_kms(struct drm_device *dev);
+int radeon_driver_firstopen_kms(struct drm_device *dev);
+void radeon_driver_lastclose_kms(struct drm_device *dev);
+int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
+void radeon_driver_postclose_kms(struct drm_device *dev,
+                                 struct drm_file *file_priv);
+void radeon_driver_preclose_kms(struct drm_device *dev,
+                                struct drm_file *file_priv);
+int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
+int radeon_resume_kms(struct drm_device *dev);
+u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
+int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
+void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
+void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
+int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
+void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
+irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS);
+int radeon_master_create_kms(struct drm_device *dev, struct drm_master *master);
+void radeon_master_destroy_kms(struct drm_device *dev,
+                               struct drm_master *master);
+int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
+                         struct drm_file *file_priv);
+int radeon_gem_object_init(struct drm_gem_object *obj);
+void radeon_gem_object_free(struct drm_gem_object *obj);
+extern struct drm_ioctl_desc radeon_ioctls_kms[];
+extern int radeon_max_kms_ioctl;
+int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
+#if defined(CONFIG_DEBUG_FS)
+int radeon_debugfs_init(struct drm_minor *minor);
+void radeon_debugfs_cleanup(struct drm_minor *minor);
+#endif
+#endif
+
 
 int radeon_no_wb;
+#if defined(CONFIG_DRM_RADEON_KMS)
+int radeon_modeset = -1;
+int radeon_dynclks = -1;
+int radeon_r4xx_atom = 0;
+int radeon_agpmode = 0;
+int radeon_vram_limit = 0;
+int radeon_gart_size = 512; /* default gart size */
+int radeon_benchmarking = 0;
+int radeon_connector_table = 0;
+#endif
 
 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
 module_param_named(no_wb, radeon_no_wb, int, 0444);
 
+#if defined(CONFIG_DRM_RADEON_KMS)
+MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
+module_param_named(modeset, radeon_modeset, int, 0400);
+
+MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
+module_param_named(dynclks, radeon_dynclks, int, 0444);
+
+MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
+module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
+
+MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing");
+module_param_named(vramlimit, radeon_vram_limit, int, 0600);
+
+MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
+module_param_named(agpmode, radeon_agpmode, int, 0444);
+
+MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32,64, etc)\n");
+module_param_named(gartsize, radeon_gart_size, int, 0600);
+
+MODULE_PARM_DESC(benchmark, "Run benchmark");
+module_param_named(benchmark, radeon_benchmarking, int, 0444);
+
+MODULE_PARM_DESC(connector_table, "Force connector table");
+module_param_named(connector_table, radeon_connector_table, int, 0444);
+#endif
+
 static int radeon_suspend(struct drm_device *dev, pm_message_t state)
 {
         drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -73,7 +153,11 @@ static struct pci_device_id pciidlist[] = {
         radeon_PCI_IDS
 };
 
-static struct drm_driver driver = {
+#if defined(CONFIG_DRM_RADEON_KMS)
+MODULE_DEVICE_TABLE(pci, pciidlist);
+#endif
+
+static struct drm_driver driver_old = {
         .driver_features =
             DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
             DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
@@ -127,18 +211,141 @@ static struct drm_driver driver = {
         .patchlevel = DRIVER_PATCHLEVEL,
 };
 
+#if defined(CONFIG_DRM_RADEON_KMS)
+static struct drm_driver kms_driver;
+
+static int __devinit
+radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
+{
+        return drm_get_dev(pdev, ent, &kms_driver);
+}
+
+static void
+radeon_pci_remove(struct pci_dev *pdev)
+{
+        struct drm_device *dev = pci_get_drvdata(pdev);
+
+        drm_put_dev(dev);
+}
+
+static int
+radeon_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+        struct drm_device *dev = pci_get_drvdata(pdev);
+        return radeon_suspend_kms(dev, state);
+}
+
+static int
+radeon_pci_resume(struct pci_dev *pdev)
+{
+        struct drm_device *dev = pci_get_drvdata(pdev);
+        return radeon_resume_kms(dev);
+}
+
+static struct drm_driver kms_driver = {
+        .driver_features =
+            DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
+            DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM,
+        .dev_priv_size = 0,
+        .load = radeon_driver_load_kms,
+        .firstopen = radeon_driver_firstopen_kms,
+        .open = radeon_driver_open_kms,
+        .preclose = radeon_driver_preclose_kms,
+        .postclose = radeon_driver_postclose_kms,
+        .lastclose = radeon_driver_lastclose_kms,
+        .unload = radeon_driver_unload_kms,
+        .suspend = radeon_suspend_kms,
+        .resume = radeon_resume_kms,
+        .get_vblank_counter = radeon_get_vblank_counter_kms,
+        .enable_vblank = radeon_enable_vblank_kms,
+        .disable_vblank = radeon_disable_vblank_kms,
+        .master_create = radeon_master_create_kms,
+        .master_destroy = radeon_master_destroy_kms,
+#if defined(CONFIG_DEBUG_FS)
+        .debugfs_init = radeon_debugfs_init,
+        .debugfs_cleanup = radeon_debugfs_cleanup,
+#endif
+        .irq_preinstall = radeon_driver_irq_preinstall_kms,
+        .irq_postinstall = radeon_driver_irq_postinstall_kms,
+        .irq_uninstall = radeon_driver_irq_uninstall_kms,
+        .irq_handler = radeon_driver_irq_handler_kms,
+        .reclaim_buffers = drm_core_reclaim_buffers,
+        .get_map_ofs = drm_core_get_map_ofs,
+        .get_reg_ofs = drm_core_get_reg_ofs,
+        .ioctls = radeon_ioctls_kms,
+        .gem_init_object = radeon_gem_object_init,
+        .gem_free_object = radeon_gem_object_free,
+        .dma_ioctl = radeon_dma_ioctl_kms,
+        .fops = {
+                 .owner = THIS_MODULE,
+                 .open = drm_open,
+                 .release = drm_release,
+                 .ioctl = drm_ioctl,
+                 .mmap = radeon_mmap,
+                 .poll = drm_poll,
+                 .fasync = drm_fasync,
+#ifdef CONFIG_COMPAT
+                 .compat_ioctl = NULL,
+#endif
+        },
+
+        .pci_driver = {
+                 .name = DRIVER_NAME,
+                 .id_table = pciidlist,
+                 .probe = radeon_pci_probe,
+                 .remove = radeon_pci_remove,
+                 .suspend = radeon_pci_suspend,
+                 .resume = radeon_pci_resume,
+        },
+
+        .name = DRIVER_NAME,
+        .desc = DRIVER_DESC,
+        .date = DRIVER_DATE,
+        .major = KMS_DRIVER_MAJOR,
+        .minor = KMS_DRIVER_MINOR,
+        .patchlevel = KMS_DRIVER_PATCHLEVEL,
+};
+#endif
+
+static struct drm_driver *driver;
+
 static int __init radeon_init(void)
 {
-        driver.num_ioctls = radeon_max_ioctl;
-        return drm_init(&driver);
+        driver = &driver_old;
+        driver->num_ioctls = radeon_max_ioctl;
+#if defined(CONFIG_DRM_RADEON_KMS) && defined(CONFIG_X86)
+        /* if enabled by default */
+        if (radeon_modeset == -1) {
+                DRM_INFO("radeon default to kernel modesetting.\n");
+                radeon_modeset = 1;
+        }
+        if (radeon_modeset == 1) {
+                DRM_INFO("radeon kernel modesetting enabled.\n");
+                driver = &kms_driver;
+                driver->driver_features |= DRIVER_MODESET;
+                driver->num_ioctls = radeon_max_kms_ioctl;
+        }
+
+        /* if the vga console setting is enabled still
+         * let modprobe override it */
+#ifdef CONFIG_VGA_CONSOLE
+        if (vgacon_text_force() && radeon_modeset == -1) {
+                DRM_INFO("VGACON disable radeon kernel modesetting.\n");
+                driver = &driver_old;
+                driver->driver_features &= ~DRIVER_MODESET;
+                radeon_modeset = 0;
+        }
+#endif
+#endif
+        return drm_init(driver);
 }
 
 static void __exit radeon_exit(void)
 {
-        drm_exit(&driver);
+        drm_exit(driver);
 }
 
-module_init(radeon_init);
+late_initcall(radeon_init);
 module_exit(radeon_exit);
 
 MODULE_AUTHOR(DRIVER_AUTHOR);
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
new file mode 100644
index 000000000000..c8ef0d14ffab
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -0,0 +1,1708 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include "drmP.h"
+#include "drm_crtc_helper.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+#include "atom.h"
+
+extern int atom_debug;
+
+uint32_t
+radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t ret = 0;
+
+        switch (supported_device) {
+        case ATOM_DEVICE_CRT1_SUPPORT:
+        case ATOM_DEVICE_TV1_SUPPORT:
+        case ATOM_DEVICE_TV2_SUPPORT:
+        case ATOM_DEVICE_CRT2_SUPPORT:
+        case ATOM_DEVICE_CV_SUPPORT:
+                switch (dac) {
+                case 1: /* dac a */
+                        if ((rdev->family == CHIP_RS300) ||
+                            (rdev->family == CHIP_RS400) ||
+                            (rdev->family == CHIP_RS480))
+                                ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
+                        else if (ASIC_IS_AVIVO(rdev))
+                                ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
+                        else
+                                ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
+                        break;
+                case 2: /* dac b */
+                        if (ASIC_IS_AVIVO(rdev))
+                                ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
+                        else {
+                                /*if (rdev->family == CHIP_R200)
+                                  ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
+                                  else*/
+                                ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
+                        }
+                        break;
+                case 3: /* external dac */
+                        if (ASIC_IS_AVIVO(rdev))
+                                ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
+                        else
+                                ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
+                        break;
+                }
+                break;
+        case ATOM_DEVICE_LCD1_SUPPORT:
+                if (ASIC_IS_AVIVO(rdev))
+                        ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
+                else
+                        ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
+                break;
+        case ATOM_DEVICE_DFP1_SUPPORT:
+                if ((rdev->family == CHIP_RS300) ||
+                    (rdev->family == CHIP_RS400) ||
+                    (rdev->family == CHIP_RS480))
+                        ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
+                else if (ASIC_IS_AVIVO(rdev))
+                        ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
+                else
+                        ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
+                break;
+        case ATOM_DEVICE_LCD2_SUPPORT:
+        case ATOM_DEVICE_DFP2_SUPPORT:
+                if ((rdev->family == CHIP_RS600) ||
+                    (rdev->family == CHIP_RS690) ||
+                    (rdev->family == CHIP_RS740))
+                        ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
+                else if (ASIC_IS_AVIVO(rdev))
+                        ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
+                else
+                        ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
+                break;
+        case ATOM_DEVICE_DFP3_SUPPORT:
+                ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
+                break;
+        }
+
+        return ret;
+}
+
+void
+radeon_link_encoder_connector(struct drm_device *dev)
+{
+        struct drm_connector *connector;
+        struct radeon_connector *radeon_connector;
+        struct drm_encoder *encoder;
+        struct radeon_encoder *radeon_encoder;
+
+        /* walk the list and link encoders to connectors */
+        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+                radeon_connector = to_radeon_connector(connector);
+                list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                        radeon_encoder = to_radeon_encoder(encoder);
+                        if (radeon_encoder->devices & radeon_connector->devices)
+                                drm_mode_connector_attach_encoder(connector, encoder);
+                }
+        }
+}
+
+static struct drm_connector *
+radeon_get_connector_for_encoder(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct drm_connector *connector;
+        struct radeon_connector *radeon_connector;
+
+        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+                radeon_connector = to_radeon_connector(connector);
+                if (radeon_encoder->devices & radeon_connector->devices)
+                        return connector;
+        }
+        return NULL;
+}
+
+/* used for both atom and legacy */
+void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
+                           struct drm_display_mode *mode,
+                           struct drm_display_mode *adjusted_mode)
+{
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
+
+        if (mode->hdisplay < native_mode->panel_xres ||
+            mode->vdisplay < native_mode->panel_yres) {
+                radeon_encoder->flags |= RADEON_USE_RMX;
+                if (ASIC_IS_AVIVO(rdev)) {
+                        adjusted_mode->hdisplay = native_mode->panel_xres;
+                        adjusted_mode->vdisplay = native_mode->panel_yres;
+                        adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
+                        adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
+                        adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
+                        adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
+                        adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
+                        adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
+                        /* update crtc values */
+                        drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
+                        /* adjust crtc values */
+                        adjusted_mode->crtc_hdisplay = native_mode->panel_xres;
+                        adjusted_mode->crtc_vdisplay = native_mode->panel_yres;
+                        adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
+                        adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
+                        adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
+                        adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
+                        adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
+                        adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
+                } else {
+                        adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
+                        adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
+                        adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
+                        adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
+                        adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
+                        adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
+                        /* update crtc values */
+                        drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
+                        /* adjust crtc values */
+                        adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
+                        adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
+                        adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
+                        adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
+                        adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
+                        adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
+                }
+                adjusted_mode->flags = native_mode->flags;
+                adjusted_mode->clock = native_mode->dotclock;
+        }
+}
+
+static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
+                                   struct drm_display_mode *mode,
+                                   struct drm_display_mode *adjusted_mode)
+{
+
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+
+        radeon_encoder->flags &= ~RADEON_USE_RMX;
+
+        drm_mode_set_crtcinfo(adjusted_mode, 0);
+
+        if (radeon_encoder->rmx_type != RMX_OFF)
+                radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
+
+        /* hw bug */
+        if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
+            && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
+                adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
+
+        return true;
+}
+
+static void
+atombios_dac_setup(struct drm_encoder *encoder, int action)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        DAC_ENCODER_CONTROL_PS_ALLOCATION args;
+        int index = 0, num = 0;
+        /* fixme - fill in enc_priv for atom dac */
+        enum radeon_tv_std tv_std = TV_STD_NTSC;
+
+        memset(&args, 0, sizeof(args));
+
+        switch (radeon_encoder->encoder_id) {
+        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+                index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
+                num = 1;
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+                index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
+                num = 2;
+                break;
+        }
+
+        args.ucAction = action;
+
+        if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
+                args.ucDacStandard = ATOM_DAC1_PS2;
+        else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+                args.ucDacStandard = ATOM_DAC1_CV;
+        else {
+                switch (tv_std) {
+                case TV_STD_PAL:
+                case TV_STD_PAL_M:
+                case TV_STD_SCART_PAL:
+                case TV_STD_SECAM:
+                case TV_STD_PAL_CN:
+                        args.ucDacStandard = ATOM_DAC1_PAL;
+                        break;
+                case TV_STD_NTSC:
+                case TV_STD_NTSC_J:
+                case TV_STD_PAL_60:
+                default:
+                        args.ucDacStandard = ATOM_DAC1_NTSC;
+                        break;
+                }
+        }
+        args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+}
+
+static void
+atombios_tv_setup(struct drm_encoder *encoder, int action)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        TV_ENCODER_CONTROL_PS_ALLOCATION args;
+        int index = 0;
+        /* fixme - fill in enc_priv for atom dac */
+        enum radeon_tv_std tv_std = TV_STD_NTSC;
+
+        memset(&args, 0, sizeof(args));
+
+        index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
+
+        args.sTVEncoder.ucAction = action;
+
+        if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+                args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
+        else {
+                switch (tv_std) {
+                case TV_STD_NTSC:
+                        args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
+                        break;
+                case TV_STD_PAL:
+                        args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
+                        break;
+                case TV_STD_PAL_M:
+                        args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
+                        break;
+                case TV_STD_PAL_60:
+                        args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
+                        break;
+                case TV_STD_NTSC_J:
+                        args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
+                        break;
+                case TV_STD_SCART_PAL:
+                        args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
+                        break;
+                case TV_STD_SECAM:
+                        args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
+                        break;
+                case TV_STD_PAL_CN:
+                        args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
+                        break;
+                default:
+                        args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
+                        break;
+                }
+        }
+
+        args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+}
+
+void
+atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
+        int index = 0;
+
+        memset(&args, 0, sizeof(args));
+
+        index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
+
+        args.sXTmdsEncoder.ucEnable = action;
+
+        if (radeon_encoder->pixel_clock > 165000)
+                args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
+
+        /*if (pScrn->rgbBits == 8)*/
+        args.sXTmdsEncoder.ucMisc |= (1 << 1);
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+}
+
+static void
+atombios_ddia_setup(struct drm_encoder *encoder, int action)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        DVO_ENCODER_CONTROL_PS_ALLOCATION args;
+        int index = 0;
+
+        memset(&args, 0, sizeof(args));
+
+        index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
+
+        args.sDVOEncoder.ucAction = action;
+        args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+
+        if (radeon_encoder->pixel_clock > 165000)
+                args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+}
+
+union lvds_encoder_control {
+        LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
+        LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
+};
+
+static void
+atombios_digital_setup(struct drm_encoder *encoder, int action)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        union lvds_encoder_control args;
+        int index = 0;
+        uint8_t frev, crev;
+        struct radeon_encoder_atom_dig *dig;
+        struct drm_connector *connector;
+        struct radeon_connector *radeon_connector;
+        struct radeon_connector_atom_dig *dig_connector;
+
+        connector = radeon_get_connector_for_encoder(encoder);
+        if (!connector)
+                return;
+
+        radeon_connector = to_radeon_connector(connector);
+
+        if (!radeon_encoder->enc_priv)
+                return;
+
+        dig = radeon_encoder->enc_priv;
+
+        if (!radeon_connector->con_priv)
+                return;
+
+        dig_connector = radeon_connector->con_priv;
+
+        memset(&args, 0, sizeof(args));
+
+        switch (radeon_encoder->encoder_id) {
+        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+                index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+                index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
+                        index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
+                else
+                        index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
+                break;
+        }
+
+        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
+
+        switch (frev) {
+        case 1:
+        case 2:
+                switch (crev) {
+                case 1:
+                        args.v1.ucMisc = 0;
+                        args.v1.ucAction = action;
+                        if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
+                                args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
+                        args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+                        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+                                if (dig->lvds_misc & (1 << 0))
+                                        args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
+                                if (dig->lvds_misc & (1 << 1))
+                                        args.v1.ucMisc |= (1 << 1);
+                        } else {
+                                if (dig_connector->linkb)
+                                        args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
+                                if (radeon_encoder->pixel_clock > 165000)
+                                        args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
+                                /*if (pScrn->rgbBits == 8) */
+                                args.v1.ucMisc |= (1 << 1);
+                        }
+                        break;
+                case 2:
+                case 3:
+                        args.v2.ucMisc = 0;
+                        args.v2.ucAction = action;
+                        if (crev == 3) {
+                                if (dig->coherent_mode)
+                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
+                        }
+                        if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
+                                args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
+                        args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+                        args.v2.ucTruncate = 0;
+                        args.v2.ucSpatial = 0;
+                        args.v2.ucTemporal = 0;
+                        args.v2.ucFRC = 0;
+                        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+                                if (dig->lvds_misc & (1 << 0))
+                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
+                                if (dig->lvds_misc & (1 << 5)) {
+                                        args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
+                                        if (dig->lvds_misc & (1 << 1))
+                                                args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
+                                }
+                                if (dig->lvds_misc & (1 << 6)) {
+                                        args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
+                                        if (dig->lvds_misc & (1 << 1))
+                                                args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
+                                        if (((dig->lvds_misc >> 2) & 0x3) == 2)
+                                                args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
+                                }
+                        } else {
+                                if (dig_connector->linkb)
+                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
+                                if (radeon_encoder->pixel_clock > 165000)
+                                        args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
+                        }
+                        break;
+                default:
+                        DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
+                        break;
+                }
+                break;
+        default:
+                DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
+                break;
+        }
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+}
+
+int
+atombios_get_encoder_mode(struct drm_encoder *encoder)
+{
+        struct drm_connector *connector;
+        struct radeon_connector *radeon_connector;
+
+        connector = radeon_get_connector_for_encoder(encoder);
+        if (!connector)
+                return 0;
+
+        radeon_connector = to_radeon_connector(connector);
+
+        switch (connector->connector_type) {
+        case DRM_MODE_CONNECTOR_DVII:
+                if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
+                        return ATOM_ENCODER_MODE_HDMI;
+                else if (radeon_connector->use_digital)
+                        return ATOM_ENCODER_MODE_DVI;
+                else
+                        return ATOM_ENCODER_MODE_CRT;
+                break;
+        case DRM_MODE_CONNECTOR_DVID:
+        case DRM_MODE_CONNECTOR_HDMIA:
+        case DRM_MODE_CONNECTOR_HDMIB:
+        default:
+                if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
+                        return ATOM_ENCODER_MODE_HDMI;
+                else
+                        return ATOM_ENCODER_MODE_DVI;
+                break;
+        case DRM_MODE_CONNECTOR_LVDS:
+                return ATOM_ENCODER_MODE_LVDS;
+                break;
+        case DRM_MODE_CONNECTOR_DisplayPort:
+                /*if (radeon_output->MonType == MT_DP)
+                  return ATOM_ENCODER_MODE_DP;
+                  else*/
+                if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr))
+                        return ATOM_ENCODER_MODE_HDMI;
+                else
+                        return ATOM_ENCODER_MODE_DVI;
+                break;
+        case CONNECTOR_DVI_A:
+        case CONNECTOR_VGA:
+                return ATOM_ENCODER_MODE_CRT;
+                break;
+        case CONNECTOR_STV:
+        case CONNECTOR_CTV:
+        case CONNECTOR_DIN:
+                /* fix me */
+                return ATOM_ENCODER_MODE_TV;
+                /*return ATOM_ENCODER_MODE_CV;*/
+                break;
+        }
+}
+
+static void
+atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        DIG_ENCODER_CONTROL_PS_ALLOCATION args;
+        int index = 0, num = 0;
+        uint8_t frev, crev;
+        struct radeon_encoder_atom_dig *dig;
+        struct drm_connector *connector;
+        struct radeon_connector *radeon_connector;
+        struct radeon_connector_atom_dig *dig_connector;
+
+        connector = radeon_get_connector_for_encoder(encoder);
+        if (!connector)
+                return;
+
+        radeon_connector = to_radeon_connector(connector);
+
+        if (!radeon_connector->con_priv)
+                return;
+
+        dig_connector = radeon_connector->con_priv;
+
+        if (!radeon_encoder->enc_priv)
+                return;
+
+        dig = radeon_encoder->enc_priv;
+
+        memset(&args, 0, sizeof(args));
+
+        if (ASIC_IS_DCE32(rdev)) {
+                if (dig->dig_block)
+                        index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
+                else
+                        index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
+                num = dig->dig_block + 1;
+        } else {
+                switch (radeon_encoder->encoder_id) {
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                        index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
+                        num = 1;
+                        break;
+                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+                        index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
+                        num = 2;
+                        break;
+                }
+        }
+
+        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
+
+        args.ucAction = action;
+        args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
+
+        if (ASIC_IS_DCE32(rdev)) {
+                switch (radeon_encoder->encoder_id) {
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                        args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
+                        break;
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                        args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
+                        break;
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                        args.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
+                        break;
+                }
+        } else {
+                switch (radeon_encoder->encoder_id) {
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                        args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER1;
+                        break;
+                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+                        args.ucConfig = ATOM_ENCODER_CONFIG_TRANSMITTER2;
+                        break;
+                }
+        }
+
+        if (radeon_encoder->pixel_clock > 165000) {
+                args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA_B;
+                args.ucLaneNum = 8;
+        } else {
+                if (dig_connector->linkb)
+                        args.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
+                else
+                        args.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
+                args.ucLaneNum = 4;
+        }
+
+        args.ucEncoderMode = atombios_get_encoder_mode(encoder);
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+}
+
+union dig_transmitter_control {
+        DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
+        DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
+};
+
+static void
+atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        union dig_transmitter_control args;
+        int index = 0, num = 0;
+        uint8_t frev, crev;
+        struct radeon_encoder_atom_dig *dig;
+        struct drm_connector *connector;
+        struct radeon_connector *radeon_connector;
+        struct radeon_connector_atom_dig *dig_connector;
+
+        connector = radeon_get_connector_for_encoder(encoder);
+        if (!connector)
+                return;
+
+        radeon_connector = to_radeon_connector(connector);
+
+        if (!radeon_encoder->enc_priv)
+                return;
+
+        dig = radeon_encoder->enc_priv;
+
+        if (!radeon_connector->con_priv)
+                return;
+
+        dig_connector = radeon_connector->con_priv;
+
+        memset(&args, 0, sizeof(args));
+
+        if (ASIC_IS_DCE32(rdev))
+                index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
+        else {
+                switch (radeon_encoder->encoder_id) {
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                        index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
+                        break;
+                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+                        index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
+                        break;
+                }
+        }
+
+        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
+
+        args.v1.ucAction = action;
+
+        if (ASIC_IS_DCE32(rdev)) {
+                if (radeon_encoder->pixel_clock > 165000) {
+                        args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100);
+                        args.v2.acConfig.fDualLinkConnector = 1;
+                } else {
+                        args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100);
+                }
+                if (dig->dig_block)
+                        args.v2.acConfig.ucEncoderSel = 1;
+
+                switch (radeon_encoder->encoder_id) {
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                        args.v2.acConfig.ucTransmitterSel = 0;
+                        num = 0;
+                        break;
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                        args.v2.acConfig.ucTransmitterSel = 1;
+                        num = 1;
+                        break;
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                        args.v2.acConfig.ucTransmitterSel = 2;
+                        num = 2;
+                        break;
+                }
+
+                if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+                        if (dig->coherent_mode)
+                                args.v2.acConfig.fCoherentMode = 1;
+                }
+        } else {
+                args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
+                args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10);
+
+                switch (radeon_encoder->encoder_id) {
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
+                        if (rdev->flags & RADEON_IS_IGP) {
+                                if (radeon_encoder->pixel_clock > 165000) {
+                                        args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
+                                                             ATOM_TRANSMITTER_CONFIG_LINKA_B);
+                                        if (dig_connector->igp_lane_info & 0x3)
+                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
+                                        else if (dig_connector->igp_lane_info & 0xc)
+                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
+                                } else {
+                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
+                                        if (dig_connector->igp_lane_info & 0x1)
+                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+                                        else if (dig_connector->igp_lane_info & 0x2)
+                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
+                                        else if (dig_connector->igp_lane_info & 0x4)
+                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
+                                        else if (dig_connector->igp_lane_info & 0x8)
+                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
+                                }
+                        } else {
+                                if (radeon_encoder->pixel_clock > 165000)
+                                        args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
+                                                             ATOM_TRANSMITTER_CONFIG_LINKA_B |
+                                                             ATOM_TRANSMITTER_CONFIG_LANE_0_7);
+                                else {
+                                        if (dig_connector->linkb)
+                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+                                        else
+                                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+                                }
+                        }
+                        break;
+                case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
+                        if (radeon_encoder->pixel_clock > 165000)
+                                args.v1.ucConfig |= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK |
+                                                     ATOM_TRANSMITTER_CONFIG_LINKA_B |
+                                                     ATOM_TRANSMITTER_CONFIG_LANE_0_7);
+                        else {
+                                if (dig_connector->linkb)
+                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+                                else
+                                        args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA | ATOM_TRANSMITTER_CONFIG_LANE_0_3;
+                        }
+                        break;
+                }
+
+                if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+                        if (dig->coherent_mode)
+                                args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
+                }
+        }
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+}
+
+static void atom_rv515_force_tv_scaler(struct radeon_device *rdev)
+{
+
+        WREG32(0x659C, 0x0);
+        WREG32(0x6594, 0x705);
+        WREG32(0x65A4, 0x10001);
+        WREG32(0x65D8, 0x0);
+        WREG32(0x65B0, 0x0);
+        WREG32(0x65C0, 0x0);
+        WREG32(0x65D4, 0x0);
+        WREG32(0x6578, 0x0);
+        WREG32(0x657C, 0x841880A8);
+        WREG32(0x6578, 0x1);
+        WREG32(0x657C, 0x84208680);
+        WREG32(0x6578, 0x2);
+        WREG32(0x657C, 0xBFF880B0);
+        WREG32(0x6578, 0x100);
+        WREG32(0x657C, 0x83D88088);
+        WREG32(0x6578, 0x101);
+        WREG32(0x657C, 0x84608680);
+        WREG32(0x6578, 0x102);
+        WREG32(0x657C, 0xBFF080D0);
+        WREG32(0x6578, 0x200);
+        WREG32(0x657C, 0x83988068);
+        WREG32(0x6578, 0x201);
+        WREG32(0x657C, 0x84A08680);
+        WREG32(0x6578, 0x202);
+        WREG32(0x657C, 0xBFF080F8);
+        WREG32(0x6578, 0x300);
+        WREG32(0x657C, 0x83588058);
+        WREG32(0x6578, 0x301);
+        WREG32(0x657C, 0x84E08660);
+        WREG32(0x6578, 0x302);
+        WREG32(0x657C, 0xBFF88120);
+        WREG32(0x6578, 0x400);
+        WREG32(0x657C, 0x83188040);
+        WREG32(0x6578, 0x401);
+        WREG32(0x657C, 0x85008660);
+        WREG32(0x6578, 0x402);
+        WREG32(0x657C, 0xBFF88150);
+        WREG32(0x6578, 0x500);
+        WREG32(0x657C, 0x82D88030);
+        WREG32(0x6578, 0x501);
+        WREG32(0x657C, 0x85408640);
+        WREG32(0x6578, 0x502);
+        WREG32(0x657C, 0xBFF88180);
+        WREG32(0x6578, 0x600);
+        WREG32(0x657C, 0x82A08018);
+        WREG32(0x6578, 0x601);
+        WREG32(0x657C, 0x85808620);
+        WREG32(0x6578, 0x602);
+        WREG32(0x657C, 0xBFF081B8);
+        WREG32(0x6578, 0x700);
+        WREG32(0x657C, 0x82608010);
+        WREG32(0x6578, 0x701);
+        WREG32(0x657C, 0x85A08600);
+        WREG32(0x6578, 0x702);
+        WREG32(0x657C, 0x800081F0);
+        WREG32(0x6578, 0x800);
+        WREG32(0x657C, 0x8228BFF8);
+        WREG32(0x6578, 0x801);
+        WREG32(0x657C, 0x85E085E0);
+        WREG32(0x6578, 0x802);
+        WREG32(0x657C, 0xBFF88228);
+        WREG32(0x6578, 0x10000);
+        WREG32(0x657C, 0x82A8BF00);
+        WREG32(0x6578, 0x10001);
+        WREG32(0x657C, 0x82A08CC0);
+        WREG32(0x6578, 0x10002);
+        WREG32(0x657C, 0x8008BEF8);
+        WREG32(0x6578, 0x10100);
+        WREG32(0x657C, 0x81F0BF28);
+        WREG32(0x6578, 0x10101);
+        WREG32(0x657C, 0x83608CA0);
+        WREG32(0x6578, 0x10102);
+        WREG32(0x657C, 0x8018BED0);
+        WREG32(0x6578, 0x10200);
+        WREG32(0x657C, 0x8148BF38);
+        WREG32(0x6578, 0x10201);
+        WREG32(0x657C, 0x84408C80);
+        WREG32(0x6578, 0x10202);
+        WREG32(0x657C, 0x8008BEB8);
+        WREG32(0x6578, 0x10300);
+        WREG32(0x657C, 0x80B0BF78);
+        WREG32(0x6578, 0x10301);
+        WREG32(0x657C, 0x85008C20);
+        WREG32(0x6578, 0x10302);
+        WREG32(0x657C, 0x8020BEA0);
+        WREG32(0x6578, 0x10400);
+        WREG32(0x657C, 0x8028BF90);
+        WREG32(0x6578, 0x10401);
+        WREG32(0x657C, 0x85E08BC0);
+        WREG32(0x6578, 0x10402);
+        WREG32(0x657C, 0x8018BE90);
+        WREG32(0x6578, 0x10500);
+        WREG32(0x657C, 0xBFB8BFB0);
+        WREG32(0x6578, 0x10501);
+        WREG32(0x657C, 0x86C08B40);
+        WREG32(0x6578, 0x10502);
+        WREG32(0x657C, 0x8010BE90);
+        WREG32(0x6578, 0x10600);
+        WREG32(0x657C, 0xBF58BFC8);
+        WREG32(0x6578, 0x10601);
+        WREG32(0x657C, 0x87A08AA0);
+        WREG32(0x6578, 0x10602);
+        WREG32(0x657C, 0x8010BE98);
+        WREG32(0x6578, 0x10700);
+        WREG32(0x657C, 0xBF10BFF0);
+        WREG32(0x6578, 0x10701);
+        WREG32(0x657C, 0x886089E0);
+        WREG32(0x6578, 0x10702);
+        WREG32(0x657C, 0x8018BEB0);
+        WREG32(0x6578, 0x10800);
+        WREG32(0x657C, 0xBED8BFE8);
+        WREG32(0x6578, 0x10801);
+        WREG32(0x657C, 0x89408940);
+        WREG32(0x6578, 0x10802);
+        WREG32(0x657C, 0xBFE8BED8);
+        WREG32(0x6578, 0x20000);
+        WREG32(0x657C, 0x80008000);
+        WREG32(0x6578, 0x20001);
+        WREG32(0x657C, 0x90008000);
+        WREG32(0x6578, 0x20002);
+        WREG32(0x657C, 0x80008000);
+        WREG32(0x6578, 0x20003);
+        WREG32(0x657C, 0x80008000);
+        WREG32(0x6578, 0x20100);
+        WREG32(0x657C, 0x80108000);
+        WREG32(0x6578, 0x20101);
+        WREG32(0x657C, 0x8FE0BF70);
+        WREG32(0x6578, 0x20102);
+        WREG32(0x657C, 0xBFE880C0);
+        WREG32(0x6578, 0x20103);
+        WREG32(0x657C, 0x80008000);
+        WREG32(0x6578, 0x20200);
+        WREG32(0x657C, 0x8018BFF8);
+        WREG32(0x6578, 0x20201);
+        WREG32(0x657C, 0x8F80BF08);
+        WREG32(0x6578, 0x20202);
+        WREG32(0x657C, 0xBFD081A0);
+        WREG32(0x6578, 0x20203);
+        WREG32(0x657C, 0xBFF88000);
+        WREG32(0x6578, 0x20300);
+        WREG32(0x657C, 0x80188000);
+        WREG32(0x6578, 0x20301);
+        WREG32(0x657C, 0x8EE0BEC0);
+        WREG32(0x6578, 0x20302);
+        WREG32(0x657C, 0xBFB082A0);
+        WREG32(0x6578, 0x20303);
+        WREG32(0x657C, 0x80008000);
+        WREG32(0x6578, 0x20400);
+        WREG32(0x657C, 0x80188000);
+        WREG32(0x6578, 0x20401);
+        WREG32(0x657C, 0x8E00BEA0);
+        WREG32(0x6578, 0x20402);
+        WREG32(0x657C, 0xBF8883C0);
+        WREG32(0x6578, 0x20403);
+        WREG32(0x657C, 0x80008000);
+        WREG32(0x6578, 0x20500);
+        WREG32(0x657C, 0x80188000);
+        WREG32(0x6578, 0x20501);
+        WREG32(0x657C, 0x8D00BE90);
+        WREG32(0x6578, 0x20502);
+        WREG32(0x657C, 0xBF588500);
+        WREG32(0x6578, 0x20503);
+        WREG32(0x657C, 0x80008008);
+        WREG32(0x6578, 0x20600);
+        WREG32(0x657C, 0x80188000);
+        WREG32(0x6578, 0x20601);
+        WREG32(0x657C, 0x8BC0BE98);
+        WREG32(0x6578, 0x20602);
+        WREG32(0x657C, 0xBF308660);
+        WREG32(0x6578, 0x20603);
+        WREG32(0x657C, 0x80008008);
+        WREG32(0x6578, 0x20700);
+        WREG32(0x657C, 0x80108000);
+        WREG32(0x6578, 0x20701);
+        WREG32(0x657C, 0x8A80BEB0);
+        WREG32(0x6578, 0x20702);
+        WREG32(0x657C, 0xBF0087C0);
+        WREG32(0x6578, 0x20703);
+        WREG32(0x657C, 0x80008008);
+        WREG32(0x6578, 0x20800);
+        WREG32(0x657C, 0x80108000);
+        WREG32(0x6578, 0x20801);
+        WREG32(0x657C, 0x8920BED0);
+        WREG32(0x6578, 0x20802);
+        WREG32(0x657C, 0xBED08920);
+        WREG32(0x6578, 0x20803);
+        WREG32(0x657C, 0x80008010);
+        WREG32(0x6578, 0x30000);
+        WREG32(0x657C, 0x90008000);
+        WREG32(0x6578, 0x30001);
+        WREG32(0x657C, 0x80008000);
+        WREG32(0x6578, 0x30100);
+        WREG32(0x657C, 0x8FE0BF90);
+        WREG32(0x6578, 0x30101);
+        WREG32(0x657C, 0xBFF880A0);
+        WREG32(0x6578, 0x30200);
+        WREG32(0x657C, 0x8F60BF40);
+        WREG32(0x6578, 0x30201);
+        WREG32(0x657C, 0xBFE88180);
+        WREG32(0x6578, 0x30300);
+        WREG32(0x657C, 0x8EC0BF00);
+        WREG32(0x6578, 0x30301);
+        WREG32(0x657C, 0xBFC88280);
+        WREG32(0x6578, 0x30400);
+        WREG32(0x657C, 0x8DE0BEE0);
+        WREG32(0x6578, 0x30401);
+        WREG32(0x657C, 0xBFA083A0);
+        WREG32(0x6578, 0x30500);
+        WREG32(0x657C, 0x8CE0BED0);
+        WREG32(0x6578, 0x30501);
+        WREG32(0x657C, 0xBF7884E0);
+        WREG32(0x6578, 0x30600);
+        WREG32(0x657C, 0x8BA0BED8);
+        WREG32(0x6578, 0x30601);
+        WREG32(0x657C, 0xBF508640);
+        WREG32(0x6578, 0x30700);
+        WREG32(0x657C, 0x8A60BEE8);
+        WREG32(0x6578, 0x30701);
+        WREG32(0x657C, 0xBF2087A0);
+        WREG32(0x6578, 0x30800);
+        WREG32(0x657C, 0x8900BF00);
+        WREG32(0x6578, 0x30801);
+        WREG32(0x657C, 0xBF008900);
+}
+
+static void
+atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        ENABLE_YUV_PS_ALLOCATION args;
+        int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
+        uint32_t temp, reg;
+
+        memset(&args, 0, sizeof(args));
+
+        if (rdev->family >= CHIP_R600)
+                reg = R600_BIOS_3_SCRATCH;
+        else
+                reg = RADEON_BIOS_3_SCRATCH;
+
+        /* XXX: fix up scratch reg handling */
+        temp = RREG32(reg);
+        if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+                WREG32(reg, (ATOM_S3_TV1_ACTIVE |
+                             (radeon_crtc->crtc_id << 18)));
+        else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+                WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
+        else
+                WREG32(reg, 0);
+
+        if (enable)
+                args.ucEnable = ATOM_ENABLE;
+        args.ucCRTC = radeon_crtc->crtc_id;
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+        WREG32(reg, temp);
+}
+
+static void
+atombios_overscan_setup(struct drm_encoder *encoder,
+                        struct drm_display_mode *mode,
+                        struct drm_display_mode *adjusted_mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        SET_CRTC_OVERSCAN_PS_ALLOCATION args;
+        int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
+
+        memset(&args, 0, sizeof(args));
+
+        args.usOverscanRight = 0;
+        args.usOverscanLeft = 0;
+        args.usOverscanBottom = 0;
+        args.usOverscanTop = 0;
+        args.ucCRTC = radeon_crtc->crtc_id;
+
+        if (radeon_encoder->flags & RADEON_USE_RMX) {
+                if (radeon_encoder->rmx_type == RMX_FULL) {
+                        args.usOverscanRight = 0;
+                        args.usOverscanLeft = 0;
+                        args.usOverscanBottom = 0;
+                        args.usOverscanTop = 0;
+                } else if (radeon_encoder->rmx_type == RMX_CENTER) {
+                        args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
+                        args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
+                        args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
+                        args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
+                } else if (radeon_encoder->rmx_type == RMX_ASPECT) {
+                        int a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
+                        int a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
+
+                        if (a1 > a2) {
+                                args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
+                                args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
+                        } else if (a2 > a1) {
+                                args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
+                                args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
+                        }
+                }
+        }
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+}
+
+static void
+atombios_scaler_setup(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        ENABLE_SCALER_PS_ALLOCATION args;
+        int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
+        /* fixme - fill in enc_priv for atom dac */
+        enum radeon_tv_std tv_std = TV_STD_NTSC;
+
+        if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
+                return;
+
+        memset(&args, 0, sizeof(args));
+
+        args.ucScaler = radeon_crtc->crtc_id;
+
+        if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
+                switch (tv_std) {
+                case TV_STD_NTSC:
+                default:
+                        args.ucTVStandard = ATOM_TV_NTSC;
+                        break;
+                case TV_STD_PAL:
+                        args.ucTVStandard = ATOM_TV_PAL;
+                        break;
+                case TV_STD_PAL_M:
+                        args.ucTVStandard = ATOM_TV_PALM;
+                        break;
+                case TV_STD_PAL_60:
+                        args.ucTVStandard = ATOM_TV_PAL60;
+                        break;
+                case TV_STD_NTSC_J:
+                        args.ucTVStandard = ATOM_TV_NTSCJ;
+                        break;
+                case TV_STD_SCART_PAL:
+                        args.ucTVStandard = ATOM_TV_PAL; /* ??? */
+                        break;
+                case TV_STD_SECAM:
+                        args.ucTVStandard = ATOM_TV_SECAM;
+                        break;
+                case TV_STD_PAL_CN:
+                        args.ucTVStandard = ATOM_TV_PALCN;
+                        break;
+                }
+                args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
+        } else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT)) {
+                args.ucTVStandard = ATOM_TV_CV;
+                args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
+        } else if (radeon_encoder->flags & RADEON_USE_RMX) {
+                if (radeon_encoder->rmx_type == RMX_FULL)
+                        args.ucEnable = ATOM_SCALER_EXPANSION;
+                else if (radeon_encoder->rmx_type == RMX_CENTER)
+                        args.ucEnable = ATOM_SCALER_CENTER;
+                else if (radeon_encoder->rmx_type == RMX_ASPECT)
+                        args.ucEnable = ATOM_SCALER_EXPANSION;
+        } else {
+                if (ASIC_IS_AVIVO(rdev))
+                        args.ucEnable = ATOM_SCALER_DISABLE;
+                else
+                        args.ucEnable = ATOM_SCALER_CENTER;
+        }
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+        if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)
+            && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_RV570) {
+                atom_rv515_force_tv_scaler(rdev);
+        }
+
+}
+
+static void
+radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
+        int index = 0;
+        bool is_dig = false;
+
+        memset(&args, 0, sizeof(args));
+
+        switch (radeon_encoder->encoder_id) {
+        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+                index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+                is_dig = true;
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
+        case ENCODER_OBJECT_ID_INTERNAL_DDI:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
+                index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+                index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
+                        index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
+                else
+                        index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+                        index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
+                else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+                        index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
+                else
+                        index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+                        index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
+                else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+                        index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
+                else
+                        index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
+                break;
+        }
+
+        if (is_dig) {
+                switch (mode) {
+                case DRM_MODE_DPMS_ON:
+                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
+                        break;
+                case DRM_MODE_DPMS_STANDBY:
+                case DRM_MODE_DPMS_SUSPEND:
+                case DRM_MODE_DPMS_OFF:
+                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
+                        break;
+                }
+        } else {
+                switch (mode) {
+                case DRM_MODE_DPMS_ON:
+                        args.ucAction = ATOM_ENABLE;
+                        break;
+                case DRM_MODE_DPMS_STANDBY:
+                case DRM_MODE_DPMS_SUSPEND:
+                case DRM_MODE_DPMS_OFF:
+                        args.ucAction = ATOM_DISABLE;
+                        break;
+                }
+                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+        }
+        radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
+}
+
+union crtc_sourc_param {
+        SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
+        SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
+};
+
+static void
+atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        union crtc_sourc_param args;
+        int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
+        uint8_t frev, crev;
+
+        memset(&args, 0, sizeof(args));
+
+        atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
+
+        switch (frev) {
+        case 1:
+                switch (crev) {
+                case 1:
+                default:
+                        if (ASIC_IS_AVIVO(rdev))
+                                args.v1.ucCRTC = radeon_crtc->crtc_id;
+                        else {
+                                if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
+                                        args.v1.ucCRTC = radeon_crtc->crtc_id;
+                                } else {
+                                        args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
+                                }
+                        }
+                        switch (radeon_encoder->encoder_id) {
+                        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+                                args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
+                                break;
+                        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+                        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+                                if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
+                                        args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
+                                else
+                                        args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
+                                break;
+                        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
+                        case ENCODER_OBJECT_ID_INTERNAL_DDI:
+                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
+                                args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
+                                break;
+                        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
+                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+                                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+                                        args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
+                                else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+                                        args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
+                                else
+                                        args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
+                                break;
+                        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+                                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+                                        args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
+                                else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+                                        args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
+                                else
+                                        args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
+                                break;
+                        }
+                        break;
+                case 2:
+                        args.v2.ucCRTC = radeon_crtc->crtc_id;
+                        args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
+                        switch (radeon_encoder->encoder_id) {
+                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                                if (ASIC_IS_DCE32(rdev)) {
+                                        if (radeon_crtc->crtc_id)
+                                                args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
+                                        else
+                                                args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
+                                } else
+                                        args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
+                                break;
+                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
+                                args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
+                                break;
+                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+                                args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
+                                break;
+                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+                                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
+                                else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
+                                else
+                                        args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
+                                break;
+                        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+                                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT))
+                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
+                                else if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT))
+                                        args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
+                                else
+                                        args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
+                                break;
+                        }
+                        break;
+                }
+                break;
+        default:
+                DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
+                break;
+        }
+
+        atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+}
+
+static void
+atombios_apply_encoder_quirks(struct drm_encoder *encoder,
+                              struct drm_display_mode *mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+
+        /* Funky macbooks */
+        if ((dev->pdev->device == 0x71C5) &&
+            (dev->pdev->subsystem_vendor == 0x106b) &&
+            (dev->pdev->subsystem_device == 0x0080)) {
+                if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
+                        uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
+
+                        lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
+                        lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
+
+                        WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
+                }
+        }
+
+        /* set scaler clears this on some chips */
+        if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
+                WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN);
+}
+
+static void
+radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
+                             struct drm_display_mode *mode,
+                             struct drm_display_mode *adjusted_mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+
+        if (radeon_encoder->enc_priv) {
+                struct radeon_encoder_atom_dig *dig;
+
+                dig = radeon_encoder->enc_priv;
+                dig->dig_block = radeon_crtc->crtc_id;
+        }
+        radeon_encoder->pixel_clock = adjusted_mode->clock;
+
+        radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
+        atombios_overscan_setup(encoder, mode, adjusted_mode);
+        atombios_scaler_setup(encoder);
+        atombios_set_encoder_crtc_source(encoder);
+
+        if (ASIC_IS_AVIVO(rdev)) {
+                if (radeon_encoder->devices & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
+                        atombios_yuv_setup(encoder, true);
+                else
+                        atombios_yuv_setup(encoder, false);
+        }
+
+        switch (radeon_encoder->encoder_id) {
+        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+                atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+                /* disable the encoder and transmitter */
+                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE);
+                atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
+
+                /* setup and enable the encoder and transmitter */
+                atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
+                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP);
+                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DDI:
+                atombios_ddia_setup(encoder, ATOM_ENABLE);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
+                atombios_external_tmds_setup(encoder, ATOM_ENABLE);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+                atombios_dac_setup(encoder, ATOM_ENABLE);
+                if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
+                        atombios_tv_setup(encoder, ATOM_ENABLE);
+                break;
+        }
+        atombios_apply_encoder_quirks(encoder, adjusted_mode);
+}
+
+static bool
+atombios_dac_load_detect(struct drm_encoder *encoder)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+
+        if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
+                                       ATOM_DEVICE_CV_SUPPORT |
+                                       ATOM_DEVICE_CRT_SUPPORT)) {
+                DAC_LOAD_DETECTION_PS_ALLOCATION args;
+                int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
+                uint8_t frev, crev;
+
+                memset(&args, 0, sizeof(args));
+
+                atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
+
+                args.sDacload.ucMisc = 0;
+
+                if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
+                    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
+                        args.sDacload.ucDacType = ATOM_DAC_A;
+                else
+                        args.sDacload.ucDacType = ATOM_DAC_B;
+
+                if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT)
+                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
+                else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT)
+                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
+                else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
+                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
+                        if (crev >= 3)
+                                args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
+                } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
+                        args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
+                        if (crev >= 3)
+                                args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
+                }
+
+                atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+                return true;
+        } else
+                return false;
+}
+
+static enum drm_connector_status
+radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t bios_0_scratch;
+
+        if (!atombios_dac_load_detect(encoder)) {
+                DRM_DEBUG("detect returned false \n");
+                return connector_status_unknown;
+        }
+
+        if (rdev->family >= CHIP_R600)
+                bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
+        else
+                bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
+
+        DRM_DEBUG("Bios 0 scratch %x\n", bios_0_scratch);
+        if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
+                if (bios_0_scratch & ATOM_S0_CRT1_MASK)
+                        return connector_status_connected;
+        } else if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
+                if (bios_0_scratch & ATOM_S0_CRT2_MASK)
+                        return connector_status_connected;
+        } else if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
+                if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
+                        return connector_status_connected;
+        } else if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
+                if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
+                        return connector_status_connected; /* CTV */
+                else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
+                        return connector_status_connected; /* STV */
+        }
+        return connector_status_disconnected;
+}
+
+static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
+{
+        radeon_atom_output_lock(encoder, true);
+        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
+{
+        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
+        radeon_atom_output_lock(encoder, false);
+}
+
+static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
+        .dpms = radeon_atom_encoder_dpms,
+        .mode_fixup = radeon_atom_mode_fixup,
+        .prepare = radeon_atom_encoder_prepare,
+        .mode_set = radeon_atom_encoder_mode_set,
+        .commit = radeon_atom_encoder_commit,
+        /* no detect for TMDS/LVDS yet */
+};
+
+static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
+        .dpms = radeon_atom_encoder_dpms,
+        .mode_fixup = radeon_atom_mode_fixup,
+        .prepare = radeon_atom_encoder_prepare,
+        .mode_set = radeon_atom_encoder_mode_set,
+        .commit = radeon_atom_encoder_commit,
+        .detect = radeon_atom_dac_detect,
+};
+
+void radeon_enc_destroy(struct drm_encoder *encoder)
+{
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        kfree(radeon_encoder->enc_priv);
+        drm_encoder_cleanup(encoder);
+        kfree(radeon_encoder);
+}
+
+static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
+        .destroy = radeon_enc_destroy,
+};
+
+struct radeon_encoder_atom_dig *
+radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
+{
+        struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
+
+        if (!dig)
+                return NULL;
+
+        /* coherent mode by default */
+        dig->coherent_mode = true;
+
+        return dig;
+}
+
+void
+radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
+{
+        struct drm_encoder *encoder;
+        struct radeon_encoder *radeon_encoder;
+
+        /* see if we already added it */
+        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                radeon_encoder = to_radeon_encoder(encoder);
+                if (radeon_encoder->encoder_id == encoder_id) {
+                        radeon_encoder->devices |= supported_device;
+                        return;
+                }
+
+        }
+
+        /* add a new one */
+        radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
+        if (!radeon_encoder)
+                return;
+
+        encoder = &radeon_encoder->base;
+        encoder->possible_crtcs = 0x3;
+        encoder->possible_clones = 0;
+
+        radeon_encoder->enc_priv = NULL;
+
+        radeon_encoder->encoder_id = encoder_id;
+        radeon_encoder->devices = supported_device;
+
+        switch (radeon_encoder->encoder_id) {
+        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
+        case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
+                if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+                        radeon_encoder->rmx_type = RMX_FULL;
+                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
+                        radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
+                } else {
+                        drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
+                        radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
+                }
+                drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
+                drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
+                drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
+                drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
+                drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
+        case ENCODER_OBJECT_ID_INTERNAL_DDI:
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+        case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+        case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
+                radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
+                drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
+                break;
+        }
+}
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
new file mode 100644
index 000000000000..fa86d398945e
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -0,0 +1,825 @@
+/*
+ * Copyright © 2007 David Airlie
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *     David Airlie
+ */
+    /*
+     *  Modularization
+     */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/tty.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+
+#include "drmP.h"
+#include "drm.h"
+#include "drm_crtc.h"
+#include "drm_crtc_helper.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+
+struct radeon_fb_device {
+        struct radeon_device            *rdev;
+        struct drm_display_mode         *mode;
+        struct radeon_framebuffer       *rfb;
+        int                             crtc_count;
+        /* crtc currently bound to this */
+        uint32_t                        crtc_ids[2];
+};
+
+static int radeonfb_setcolreg(unsigned regno,
+                              unsigned red,
+                              unsigned green,
+                              unsigned blue,
+                              unsigned transp,
+                              struct fb_info *info)
+{
+        struct radeon_fb_device *rfbdev = info->par;
+        struct drm_device *dev = rfbdev->rdev->ddev;
+        struct drm_crtc *crtc;
+        int i;
+
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+                struct drm_mode_set *modeset = &radeon_crtc->mode_set;
+                struct drm_framebuffer *fb = modeset->fb;
+
+                for (i = 0; i < rfbdev->crtc_count; i++) {
+                        if (crtc->base.id == rfbdev->crtc_ids[i]) {
+                                break;
+                        }
+                }
+                if (i == rfbdev->crtc_count) {
+                        continue;
+                }
+                if (regno > 255) {
+                        return 1;
+                }
+                if (fb->depth == 8) {
+                        radeon_crtc_fb_gamma_set(crtc, red, green, blue, regno);
+                        return 0;
+                }
+
+                if (regno < 16) {
+                        switch (fb->depth) {
+                        case 15:
+                                fb->pseudo_palette[regno] = ((red & 0xf800) >> 1) |
+                                        ((green & 0xf800) >>  6) |
+                                        ((blue & 0xf800) >> 11);
+                                break;
+                        case 16:
+                                fb->pseudo_palette[regno] = (red & 0xf800) |
+                                        ((green & 0xfc00) >>  5) |
+                                        ((blue  & 0xf800) >> 11);
+                                break;
+                        case 24:
+                        case 32:
+                                fb->pseudo_palette[regno] = ((red & 0xff00) << 8) |
+                                        (green & 0xff00) |
+                                        ((blue  & 0xff00) >> 8);
+                                break;
+                        }
+                }
+        }
+        return 0;
+}
+
+static int radeonfb_check_var(struct fb_var_screeninfo *var,
+                              struct fb_info *info)
+{
+        struct radeon_fb_device *rfbdev = info->par;
+        struct radeon_framebuffer *rfb = rfbdev->rfb;
+        struct drm_framebuffer *fb = &rfb->base;
+        int depth;
+
+        if (var->pixclock == -1 || !var->pixclock) {
+                return -EINVAL;
+        }
+        /* Need to resize the fb object !!! */
+        if (var->xres > fb->width || var->yres > fb->height) {
+                DRM_ERROR("Requested width/height is greater than current fb "
+                           "object %dx%d > %dx%d\n", var->xres, var->yres,
+                           fb->width, fb->height);
+                DRM_ERROR("Need resizing code.\n");
+                return -EINVAL;
+        }
+
+        switch (var->bits_per_pixel) {
+        case 16:
+                depth = (var->green.length == 6) ? 16 : 15;
+                break;
+        case 32:
+                depth = (var->transp.length > 0) ? 32 : 24;
+                break;
+        default:
+                depth = var->bits_per_pixel;
+                break;
+        }
+
+        switch (depth) {
+        case 8:
+                var->red.offset = 0;
+                var->green.offset = 0;
+                var->blue.offset = 0;
+                var->red.length = 8;
+                var->green.length = 8;
+                var->blue.length = 8;
+                var->transp.length = 0;
+                var->transp.offset = 0;
+                break;
+        case 15:
+                var->red.offset = 10;
+                var->green.offset = 5;
+                var->blue.offset = 0;
+                var->red.length = 5;
+                var->green.length = 5;
+                var->blue.length = 5;
+                var->transp.length = 1;
+                var->transp.offset = 15;
+                break;
+        case 16:
+                var->red.offset = 11;
+                var->green.offset = 5;
+                var->blue.offset = 0;
+                var->red.length = 5;
+                var->green.length = 6;
+                var->blue.length = 5;
+                var->transp.length = 0;
+                var->transp.offset = 0;
+                break;
+        case 24:
+                var->red.offset = 16;
+                var->green.offset = 8;
+                var->blue.offset = 0;
+                var->red.length = 8;
+                var->green.length = 8;
+                var->blue.length = 8;
+                var->transp.length = 0;
+                var->transp.offset = 0;
+                break;
+        case 32:
+                var->red.offset = 16;
+                var->green.offset = 8;
+                var->blue.offset = 0;
+                var->red.length = 8;
+                var->green.length = 8;
+                var->blue.length = 8;
+                var->transp.length = 8;
+                var->transp.offset = 24;
+                break;
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
+/* this will let fbcon do the mode init */
+static int radeonfb_set_par(struct fb_info *info)
+{
+        struct radeon_fb_device *rfbdev = info->par;
+        struct drm_device *dev = rfbdev->rdev->ddev;
+        struct fb_var_screeninfo *var = &info->var;
+        struct drm_crtc *crtc;
+        int ret;
+        int i;
+
+        if (var->pixclock != -1) {
+                DRM_ERROR("PIXEL CLCOK SET\n");
+                return -EINVAL;
+        }
+
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+
+                for (i = 0; i < rfbdev->crtc_count; i++) {
+                        if (crtc->base.id == rfbdev->crtc_ids[i]) {
+                                break;
+                        }
+                }
+                if (i == rfbdev->crtc_count) {
+                        continue;
+                }
+                if (crtc->fb == radeon_crtc->mode_set.fb) {
+                        mutex_lock(&dev->mode_config.mutex);
+                        ret = crtc->funcs->set_config(&radeon_crtc->mode_set);
+                        mutex_unlock(&dev->mode_config.mutex);
+                        if (ret) {
+                                return ret;
+                        }
+                }
+        }
+        return 0;
+}
+
+static int radeonfb_pan_display(struct fb_var_screeninfo *var,
+                                struct fb_info *info)
+{
+        struct radeon_fb_device *rfbdev = info->par;
+        struct drm_device *dev = rfbdev->rdev->ddev;
+        struct drm_mode_set *modeset;
+        struct drm_crtc *crtc;
+        struct radeon_crtc *radeon_crtc;
+        int ret = 0;
+        int i;
+
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                for (i = 0; i < rfbdev->crtc_count; i++) {
+                        if (crtc->base.id == rfbdev->crtc_ids[i]) {
+                                break;
+                        }
+                }
+
+                if (i == rfbdev->crtc_count) {
+                        continue;
+                }
+
+                radeon_crtc = to_radeon_crtc(crtc);
+                modeset = &radeon_crtc->mode_set;
+
+                modeset->x = var->xoffset;
+                modeset->y = var->yoffset;
+
+                if (modeset->num_connectors) {
+                        mutex_lock(&dev->mode_config.mutex);
+                        ret = crtc->funcs->set_config(modeset);
+                        mutex_unlock(&dev->mode_config.mutex);
+                        if (!ret) {
+                                info->var.xoffset = var->xoffset;
+                                info->var.yoffset = var->yoffset;
+                        }
+                }
+        }
+        return ret;
+}
+
+static void radeonfb_on(struct fb_info *info)
+{
+        struct radeon_fb_device *rfbdev = info->par;
+        struct drm_device *dev = rfbdev->rdev->ddev;
+        struct drm_crtc *crtc;
+        struct drm_encoder *encoder;
+        int i;
+
+        /*
+         * For each CRTC in this fb, find all associated encoders
+         * and turn them off, then turn off the CRTC.
+         */
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+                for (i = 0; i < rfbdev->crtc_count; i++) {
+                        if (crtc->base.id == rfbdev->crtc_ids[i]) {
+                                break;
+                        }
+                }
+
+                mutex_lock(&dev->mode_config.mutex);
+                crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
+                mutex_unlock(&dev->mode_config.mutex);
+
+                /* Found a CRTC on this fb, now find encoders */
+                list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                        if (encoder->crtc == crtc) {
+                                struct drm_encoder_helper_funcs *encoder_funcs;
+
+                                encoder_funcs = encoder->helper_private;
+                                mutex_lock(&dev->mode_config.mutex);
+                                encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
+                                mutex_unlock(&dev->mode_config.mutex);
+                        }
+                }
+        }
+}
+
+static void radeonfb_off(struct fb_info *info, int dpms_mode)
+{
+        struct radeon_fb_device *rfbdev = info->par;
+        struct drm_device *dev = rfbdev->rdev->ddev;
+        struct drm_crtc *crtc;
+        struct drm_encoder *encoder;
+        int i;
+
+        /*
+         * For each CRTC in this fb, find all associated encoders
+         * and turn them off, then turn off the CRTC.
+         */
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+                for (i = 0; i < rfbdev->crtc_count; i++) {
+                        if (crtc->base.id == rfbdev->crtc_ids[i]) {
+                                break;
+                        }
+                }
+
+                /* Found a CRTC on this fb, now find encoders */
+                list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                        if (encoder->crtc == crtc) {
+                                struct drm_encoder_helper_funcs *encoder_funcs;
+
+                                encoder_funcs = encoder->helper_private;
+                                mutex_lock(&dev->mode_config.mutex);
+                                encoder_funcs->dpms(encoder, dpms_mode);
+                                mutex_unlock(&dev->mode_config.mutex);
+                        }
+                }
+                if (dpms_mode == DRM_MODE_DPMS_OFF) {
+                        mutex_lock(&dev->mode_config.mutex);
+                        crtc_funcs->dpms(crtc, dpms_mode);
+                        mutex_unlock(&dev->mode_config.mutex);
+                }
+        }
+}
+
+int radeonfb_blank(int blank, struct fb_info *info)
+{
+        switch (blank) {
+        case FB_BLANK_UNBLANK:
+                radeonfb_on(info);
+                break;
+        case FB_BLANK_NORMAL:
+                radeonfb_off(info, DRM_MODE_DPMS_STANDBY);
+                break;
+        case FB_BLANK_HSYNC_SUSPEND:
+                radeonfb_off(info, DRM_MODE_DPMS_STANDBY);
+                break;
+        case FB_BLANK_VSYNC_SUSPEND:
+                radeonfb_off(info, DRM_MODE_DPMS_SUSPEND);
+                break;
+        case FB_BLANK_POWERDOWN:
+                radeonfb_off(info, DRM_MODE_DPMS_OFF);
+                break;
+        }
+        return 0;
+}
+
+static struct fb_ops radeonfb_ops = {
+        .owner = THIS_MODULE,
+        .fb_check_var = radeonfb_check_var,
+        .fb_set_par = radeonfb_set_par,
+        .fb_setcolreg = radeonfb_setcolreg,
+        .fb_fillrect = cfb_fillrect,
+        .fb_copyarea = cfb_copyarea,
+        .fb_imageblit = cfb_imageblit,
+        .fb_pan_display = radeonfb_pan_display,
+        .fb_blank = radeonfb_blank,
+};
+
+/**
+ * Curretly it is assumed that the old framebuffer is reused.
+ *
+ * LOCKING
+ * caller should hold the mode config lock.
+ *
+ */
+int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc)
+{
+        struct fb_info *info;
+        struct drm_framebuffer *fb;
+        struct drm_display_mode *mode = crtc->desired_mode;
+
+        fb = crtc->fb;
+        if (fb == NULL) {
+                return 1;
+        }
+        info = fb->fbdev;
+        if (info == NULL) {
+                return 1;
+        }
+        if (mode == NULL) {
+                return 1;
+        }
+        info->var.xres = mode->hdisplay;
+        info->var.right_margin = mode->hsync_start - mode->hdisplay;
+        info->var.hsync_len = mode->hsync_end - mode->hsync_start;
+        info->var.left_margin = mode->htotal - mode->hsync_end;
+        info->var.yres = mode->vdisplay;
+        info->var.lower_margin = mode->vsync_start - mode->vdisplay;
+        info->var.vsync_len = mode->vsync_end - mode->vsync_start;
+        info->var.upper_margin = mode->vtotal - mode->vsync_end;
+        info->var.pixclock = 10000000 / mode->htotal * 1000 / mode->vtotal * 100;
+        /* avoid overflow */
+        info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;
+
+        return 0;
+}
+EXPORT_SYMBOL(radeonfb_resize);
+
+static struct drm_mode_set panic_mode;
+
+int radeonfb_panic(struct notifier_block *n, unsigned long ununsed,
+                  void *panic_str)
+{
+        DRM_ERROR("panic occurred, switching back to text console\n");
+        drm_crtc_helper_set_config(&panic_mode);
+        return 0;
+}
+EXPORT_SYMBOL(radeonfb_panic);
+
+static struct notifier_block paniced = {
+        .notifier_call = radeonfb_panic,
+};
+
+static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp)
+{
+        int aligned = width;
+        int align_large = (ASIC_IS_AVIVO(rdev));
+        int pitch_mask = 0;
+
+        switch (bpp / 8) {
+        case 1:
+                pitch_mask = align_large ? 255 : 127;
+                break;
+        case 2:
+                pitch_mask = align_large ? 127 : 31;
+                break;
+        case 3:
+        case 4:
+                pitch_mask = align_large ? 63 : 15;
+                break;
+        }
+
+        aligned += pitch_mask;
+        aligned &= ~pitch_mask;
+        return aligned;
+}
+
+int radeonfb_create(struct radeon_device *rdev,
+                    uint32_t fb_width, uint32_t fb_height,
+                    uint32_t surface_width, uint32_t surface_height,
+                    struct radeon_framebuffer **rfb_p)
+{
+        struct fb_info *info;
+        struct radeon_fb_device *rfbdev;
+        struct drm_framebuffer *fb;
+        struct radeon_framebuffer *rfb;
+        struct drm_mode_fb_cmd mode_cmd;
+        struct drm_gem_object *gobj = NULL;
+        struct radeon_object *robj = NULL;
+        struct device *device = &rdev->pdev->dev;
+        int size, aligned_size, ret;
+        void *fbptr = NULL;
+
+        mode_cmd.width = surface_width;
+        mode_cmd.height = surface_height;
+        mode_cmd.bpp = 32;
+        /* need to align pitch with crtc limits */
+        mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp) * ((mode_cmd.bpp + 1) / 8);
+        mode_cmd.depth = 24;
+
+        size = mode_cmd.pitch * mode_cmd.height;
+        aligned_size = ALIGN(size, PAGE_SIZE);
+
+        ret = radeon_gem_object_create(rdev, aligned_size, 0,
+                                       RADEON_GEM_DOMAIN_VRAM,
+                                       false, ttm_bo_type_kernel,
+                                       false, &gobj);
+        if (ret) {
+                printk(KERN_ERR "failed to allocate framebuffer\n");
+                ret = -ENOMEM;
+                goto out;
+        }
+        robj = gobj->driver_private;
+
+        mutex_lock(&rdev->ddev->struct_mutex);
+        fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
+        if (fb == NULL) {
+                DRM_ERROR("failed to allocate fb.\n");
+                ret = -ENOMEM;
+                goto out_unref;
+        }
+
+        list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);
+
+        rfb = to_radeon_framebuffer(fb);
+        *rfb_p = rfb;
+        rdev->fbdev_rfb = rfb;
+
+        info = framebuffer_alloc(sizeof(struct radeon_fb_device), device);
+        if (info == NULL) {
+                ret = -ENOMEM;
+                goto out_unref;
+        }
+        rfbdev = info->par;
+
+        ret = radeon_object_kmap(robj, &fbptr);
+        if (ret) {
+                goto out_unref;
+        }
+
+        strcpy(info->fix.id, "radeondrmfb");
+        info->fix.type = FB_TYPE_PACKED_PIXELS;
+        info->fix.visual = FB_VISUAL_TRUECOLOR;
+        info->fix.type_aux = 0;
+        info->fix.xpanstep = 1; /* doing it in hw */
+        info->fix.ypanstep = 1; /* doing it in hw */
+        info->fix.ywrapstep = 0;
+        info->fix.accel = FB_ACCEL_I830;
+        info->fix.type_aux = 0;
+        info->flags = FBINFO_DEFAULT;
+        info->fbops = &radeonfb_ops;
+        info->fix.line_length = fb->pitch;
+        info->screen_base = fbptr;
+        info->fix.smem_start = (unsigned long)fbptr;
+        info->fix.smem_len = size;
+        info->screen_base = fbptr;
+        info->screen_size = size;
+        info->pseudo_palette = fb->pseudo_palette;
+        info->var.xres_virtual = fb->width;
+        info->var.yres_virtual = fb->height;
+        info->var.bits_per_pixel = fb->bits_per_pixel;
+        info->var.xoffset = 0;
+        info->var.yoffset = 0;
+        info->var.activate = FB_ACTIVATE_NOW;
+        info->var.height = -1;
+        info->var.width = -1;
+        info->var.xres = fb_width;
+        info->var.yres = fb_height;
+        info->fix.mmio_start = pci_resource_start(rdev->pdev, 2);
+        info->fix.mmio_len = pci_resource_len(rdev->pdev, 2);
+        info->pixmap.size = 64*1024;
+        info->pixmap.buf_align = 8;
+        info->pixmap.access_align = 32;
+        info->pixmap.flags = FB_PIXMAP_SYSTEM;
+        info->pixmap.scan_align = 1;
+        if (info->screen_base == NULL) {
+                ret = -ENOSPC;
+                goto out_unref;
+        }
+        DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
+        DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
+        DRM_INFO("size %lu\n", (unsigned long)size);
+        DRM_INFO("fb depth is %d\n", fb->depth);
+        DRM_INFO("   pitch is %d\n", fb->pitch);
+
+        switch (fb->depth) {
+        case 8:
+                info->var.red.offset = 0;
+                info->var.green.offset = 0;
+                info->var.blue.offset = 0;
+                info->var.red.length = 8; /* 8bit DAC */
+                info->var.green.length = 8;
+                info->var.blue.length = 8;
+                info->var.transp.offset = 0;
+                info->var.transp.length = 0;
+                break;
+        case 15:
+                info->var.red.offset = 10;
+                info->var.green.offset = 5;
+                info->var.blue.offset = 0;
+                info->var.red.length = 5;
+                info->var.green.length = 5;
+                info->var.blue.length = 5;
+                info->var.transp.offset = 15;
+                info->var.transp.length = 1;
+                break;
+        case 16:
+                info->var.red.offset = 11;
+                info->var.green.offset = 5;
+                info->var.blue.offset = 0;
+                info->var.red.length = 5;
+                info->var.green.length = 6;
+                info->var.blue.length = 5;
+                info->var.transp.offset = 0;
+                break;
+        case 24:
+                info->var.red.offset = 16;
+                info->var.green.offset = 8;
+                info->var.blue.offset = 0;
+                info->var.red.length = 8;
+                info->var.green.length = 8;
+                info->var.blue.length = 8;
+                info->var.transp.offset = 0;
+                info->var.transp.length = 0;
+                break;
+        case 32:
+                info->var.red.offset = 16;
+                info->var.green.offset = 8;
+                info->var.blue.offset = 0;
+                info->var.red.length = 8;
+                info->var.green.length = 8;
+                info->var.blue.length = 8;
+                info->var.transp.offset = 24;
+                info->var.transp.length = 8;
+                break;
+        default:
+                break;
+        }
+
+        fb->fbdev = info;
+        rfbdev->rfb = rfb;
+        rfbdev->rdev = rdev;
+
+        mutex_unlock(&rdev->ddev->struct_mutex);
+        return 0;
+
+out_unref:
+        if (robj) {
+                radeon_object_kunmap(robj);
+        }
+        if (ret) {
+                list_del(&fb->filp_head);
+                drm_gem_object_unreference(gobj);
+                drm_framebuffer_cleanup(fb);
+                kfree(fb);
+        }
+        drm_gem_object_unreference(gobj);
+        mutex_unlock(&rdev->ddev->struct_mutex);
+out:
+        return ret;
+}
+
+static int radeonfb_single_fb_probe(struct radeon_device *rdev)
+{
+        struct drm_crtc *crtc;
+        struct drm_connector *connector;
+        unsigned int fb_width = (unsigned)-1, fb_height = (unsigned)-1;
+        unsigned int surface_width = 0, surface_height = 0;
+        int new_fb = 0;
+        int crtc_count = 0;
+        int ret, i, conn_count = 0;
+        struct radeon_framebuffer *rfb;
+        struct fb_info *info;
+        struct radeon_fb_device *rfbdev;
+        struct drm_mode_set *modeset = NULL;
+
+        /* first up get a count of crtcs now in use and new min/maxes width/heights */
+        list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) {
+                if (drm_helper_crtc_in_use(crtc)) {
+                        if (crtc->desired_mode) {
+                                if (crtc->desired_mode->hdisplay < fb_width)
+                                        fb_width = crtc->desired_mode->hdisplay;
+
+                                if (crtc->desired_mode->vdisplay < fb_height)
+                                        fb_height = crtc->desired_mode->vdisplay;
+
+                                if (crtc->desired_mode->hdisplay > surface_width)
+                                        surface_width = crtc->desired_mode->hdisplay;
+
+                                if (crtc->desired_mode->vdisplay > surface_height)
+                                        surface_height = crtc->desired_mode->vdisplay;
+                        }
+                        crtc_count++;
+                }
+        }
+
+        if (crtc_count == 0 || fb_width == -1 || fb_height == -1) {
+                /* hmm everyone went away - assume VGA cable just fell out
+                   and will come back later. */
+                return 0;
+        }
+
+        /* do we have an fb already? */
+        if (list_empty(&rdev->ddev->mode_config.fb_kernel_list)) {
+                /* create an fb if we don't have one */
+                ret = radeonfb_create(rdev, fb_width, fb_height, surface_width, surface_height, &rfb);
+                if (ret) {
+                        return -EINVAL;
+                }
+                new_fb = 1;
+        } else {
+                struct drm_framebuffer *fb;
+                fb = list_first_entry(&rdev->ddev->mode_config.fb_kernel_list, struct drm_framebuffer, filp_head);
+                rfb = to_radeon_framebuffer(fb);
+
+                /* if someone hotplugs something bigger than we have already allocated, we are pwned.
+                   As really we can't resize an fbdev that is in the wild currently due to fbdev
+                   not really being designed for the lower layers moving stuff around under it.
+                   - so in the grand style of things - punt. */
+                if ((fb->width < surface_width) || (fb->height < surface_height)) {
+                        DRM_ERROR("Framebuffer not large enough to scale console onto.\n");
+                        return -EINVAL;
+                }
+        }
+
+        info = rfb->base.fbdev;
+        rdev->fbdev_info = info;
+        rfbdev = info->par;
+
+        crtc_count = 0;
+        /* okay we need to setup new connector sets in the crtcs */
+        list_for_each_entry(crtc, &rdev->ddev->mode_config.crtc_list, head) {
+                struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+                modeset = &radeon_crtc->mode_set;
+                modeset->fb = &rfb->base;
+                conn_count = 0;
+                list_for_each_entry(connector, &rdev->ddev->mode_config.connector_list, head) {
+                        if (connector->encoder)
+                                if (connector->encoder->crtc == modeset->crtc) {
+                                        modeset->connectors[conn_count] = connector;
+                                        conn_count++;
+                                        if (conn_count > RADEONFB_CONN_LIMIT)
+                                                BUG();
+                                }
+                }
+
+                for (i = conn_count; i < RADEONFB_CONN_LIMIT; i++)
+                        modeset->connectors[i] = NULL;
+
+
+                rfbdev->crtc_ids[crtc_count++] = crtc->base.id;
+
+                modeset->num_connectors = conn_count;
+                if (modeset->crtc->desired_mode) {
+                        if (modeset->mode) {
+                                drm_mode_destroy(rdev->ddev, modeset->mode);
+                        }
+                        modeset->mode = drm_mode_duplicate(rdev->ddev,
+                                                           modeset->crtc->desired_mode);
+                }
+        }
+        rfbdev->crtc_count = crtc_count;
+
+        if (new_fb) {
+                info->var.pixclock = -1;
+                if (register_framebuffer(info) < 0)
+                        return -EINVAL;
+        } else {
+                radeonfb_set_par(info);
+        }
+        printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node,
+               info->fix.id);
+
+        /* Switch back to kernel console on panic */
+        panic_mode = *modeset;
+        atomic_notifier_chain_register(&panic_notifier_list, &paniced);
+        printk(KERN_INFO "registered panic notifier\n");
+
+        return 0;
+}
+
+int radeonfb_probe(struct drm_device *dev)
+{
+        int ret;
+
+        /* something has changed in the lower levels of hell - deal with it
+           here */
+
+        /* two modes : a) 1 fb to rule all crtcs.
+                       b) one fb per crtc.
+           two actions 1) new connected device
+                       2) device removed.
+           case a/1 : if the fb surface isn't big enough - resize the surface fb.
+                      if the fb size isn't big enough - resize fb into surface.
+                      if everything big enough configure the new crtc/etc.
+           case a/2 : undo the configuration
+                      possibly resize down the fb to fit the new configuration.
+           case b/1 : see if it is on a new crtc - setup a new fb and add it.
+           case b/2 : teardown the new fb.
+        */
+        ret = radeonfb_single_fb_probe(dev->dev_private);
+        return ret;
+}
+EXPORT_SYMBOL(radeonfb_probe);
+
+int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
+{
+        struct fb_info *info;
+        struct radeon_framebuffer *rfb = to_radeon_framebuffer(fb);
+        struct radeon_object *robj;
+
+        if (!fb) {
+                return -EINVAL;
+        }
+        info = fb->fbdev;
+        if (info) {
+                robj = rfb->obj->driver_private;
+                unregister_framebuffer(info);
+                radeon_object_kunmap(robj);
+                framebuffer_release(info);
+        }
+
+        printk(KERN_INFO "unregistered panic notifier\n");
+        atomic_notifier_chain_unregister(&panic_notifier_list, &paniced);
+        memset(&panic_mode, 0, sizeof(struct drm_mode_set));
+        return 0;
+}
+EXPORT_SYMBOL(radeonfb_remove);
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
new file mode 100644
index 000000000000..96afbf5ae2ad
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -0,0 +1,387 @@
+/*
+ * Copyright 2009 Jerome Glisse.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ */
+/*
+ * Authors:
+ *    Jerome Glisse <glisse@freedesktop.org>
+ *    Dave Airlie
+ */
+#include <linux/seq_file.h>
+#include <asm/atomic.h>
+#include <linux/wait.h>
+#include <linux/list.h>
+#include <linux/kref.h>
+#include "drmP.h"
+#include "drm.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
+{
+        unsigned long irq_flags;
+
+        write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
+        if (fence->emited) {
+                write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
+                return 0;
+        }
+        fence->seq = atomic_add_return(1, &rdev->fence_drv.seq);
+        if (!rdev->cp.ready) {
+                /* FIXME: cp is not running assume everythings is done right
+                 * away
+                 */
+                WREG32(rdev->fence_drv.scratch_reg, fence->seq);
+        } else {
+                radeon_fence_ring_emit(rdev, fence);
+        }
+        fence->emited = true;
+        fence->timeout = jiffies + ((2000 * HZ) / 1000);
+        list_del(&fence->list);
+        list_add_tail(&fence->list, &rdev->fence_drv.emited);
+        write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
+        return 0;
+}
+
+static bool radeon_fence_poll_locked(struct radeon_device *rdev)
+{
+        struct radeon_fence *fence;
+        struct list_head *i, *n;
+        uint32_t seq;
+        bool wake = false;
+
+        if (rdev == NULL) {
+                return true;
+        }
+        if (rdev->shutdown) {
+                return true;
+        }
+        seq = RREG32(rdev->fence_drv.scratch_reg);
+        rdev->fence_drv.last_seq = seq;
+        n = NULL;
+        list_for_each(i, &rdev->fence_drv.emited) {
+                fence = list_entry(i, struct radeon_fence, list);
+                if (fence->seq == seq) {
+                        n = i;
+                        break;
+                }
+        }
+        /* all fence previous to this one are considered as signaled */
+        if (n) {
+                i = n;
+                do {
+                        n = i->prev;
+                        list_del(i);
+                        list_add_tail(i, &rdev->fence_drv.signaled);
+                        fence = list_entry(i, struct radeon_fence, list);
+                        fence->signaled = true;
+                        i = n;
+                } while (i != &rdev->fence_drv.emited);
+                wake = true;
+        }
+        return wake;
+}
+
+static void radeon_fence_destroy(struct kref *kref)
+{
+        unsigned long irq_flags;
+        struct radeon_fence *fence;
+
+        fence = container_of(kref, struct radeon_fence, kref);
+        write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
+        list_del(&fence->list);
+        fence->emited = false;
+        write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
+        kfree(fence);
+}
+
+int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence)
+{
+        unsigned long irq_flags;
+
+        *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
+        if ((*fence) == NULL) {
+                return -ENOMEM;
+        }
+        kref_init(&((*fence)->kref));
+        (*fence)->rdev = rdev;
+        (*fence)->emited = false;
+        (*fence)->signaled = false;
+        (*fence)->seq = 0;
+        INIT_LIST_HEAD(&(*fence)->list);
+
+        write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
+        list_add_tail(&(*fence)->list, &rdev->fence_drv.created);
+        write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
+        return 0;
+}
+
+
+bool radeon_fence_signaled(struct radeon_fence *fence)
+{
+        struct radeon_device *rdev = fence->rdev;
+        unsigned long irq_flags;
+        bool signaled = false;
+
+        if (rdev->gpu_lockup) {
+                return true;
+        }
+        if (fence == NULL) {
+                return true;
+        }
+        write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags);
+        signaled = fence->signaled;
+        /* if we are shuting down report all fence as signaled */
+        if (fence->rdev->shutdown) {
+                signaled = true;
+        }
+        if (!fence->emited) {
+                WARN(1, "Querying an unemited fence : %p !\n", fence);
+                signaled = true;
+        }
+        if (!signaled) {
+                radeon_fence_poll_locked(fence->rdev);
+                signaled = fence->signaled;
+        }
+        write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags);
+        return signaled;
+}
+
+int radeon_fence_wait(struct radeon_fence *fence, bool interruptible)
+{
+        struct radeon_device *rdev;
+        unsigned long cur_jiffies;
+        unsigned long timeout;
+        bool expired = false;
+        int r;
+
+
+        if (fence == NULL) {
+                WARN(1, "Querying an invalid fence : %p !\n", fence);
+                return 0;
+        }
+        rdev = fence->rdev;
+        if (radeon_fence_signaled(fence)) {
+                return 0;
+        }
+retry:
+        cur_jiffies = jiffies;
+        timeout = HZ / 100;
+        if (time_after(fence->timeout, cur_jiffies)) {
+                timeout = fence->timeout - cur_jiffies;
+        }
+        if (interruptible) {
+                r = wait_event_interruptible_timeout(rdev->fence_drv.queue,
+                                radeon_fence_signaled(fence), timeout);
+                if (unlikely(r == -ERESTARTSYS)) {
+                        return -ERESTART;
+                }
+        } else {
+                r = wait_event_timeout(rdev->fence_drv.queue,
+                         radeon_fence_signaled(fence), timeout);
+        }
+        if (unlikely(!radeon_fence_signaled(fence))) {
+                if (unlikely(r == 0)) {
+                        expired = true;
+                }
+                if (unlikely(expired)) {
+                        timeout = 1;
+                        if (time_after(cur_jiffies, fence->timeout)) {
+                                timeout = cur_jiffies - fence->timeout;
+                        }
+                        timeout = jiffies_to_msecs(timeout);
+                        if (timeout > 500) {
+                                DRM_ERROR("fence(%p:0x%08X) %lums timeout "
+                                          "going to reset GPU\n",
+                                          fence, fence->seq, timeout);
+                                radeon_gpu_reset(rdev);
+                                WREG32(rdev->fence_drv.scratch_reg, fence->seq);
+                        }
+                }
+                goto retry;
+        }
+        if (unlikely(expired)) {
+                rdev->fence_drv.count_timeout++;
+                cur_jiffies = jiffies;
+                timeout = 1;
+                if (time_after(cur_jiffies, fence->timeout)) {
+                        timeout = cur_jiffies - fence->timeout;
+                }
+                timeout = jiffies_to_msecs(timeout);
+                DRM_ERROR("fence(%p:0x%08X) %lums timeout\n",
+                          fence, fence->seq, timeout);
+                DRM_ERROR("last signaled fence(0x%08X)\n",
+                          rdev->fence_drv.last_seq);
+        }
+        return 0;
+}
+
+int radeon_fence_wait_next(struct radeon_device *rdev)
+{
+        unsigned long irq_flags;
+        struct radeon_fence *fence;
+        int r;
+
+        if (rdev->gpu_lockup) {
+                return 0;
+        }
+        write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
+        if (list_empty(&rdev->fence_drv.emited)) {
+                write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
+                return 0;
+        }
+        fence = list_entry(rdev->fence_drv.emited.next,
+                           struct radeon_fence, list);
+        radeon_fence_ref(fence);
+        write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
+        r = radeon_fence_wait(fence, false);
+        radeon_fence_unref(&fence);
+        return r;
+}
+
+int radeon_fence_wait_last(struct radeon_device *rdev)
+{
+        unsigned long irq_flags;
+        struct radeon_fence *fence;
+        int r;
+
+        if (rdev->gpu_lockup) {
+                return 0;
+        }
+        write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
+        if (list_empty(&rdev->fence_drv.emited)) {
+                write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
+                return 0;
+        }
+        fence = list_entry(rdev->fence_drv.emited.prev,
+                           struct radeon_fence, list);
+        radeon_fence_ref(fence);
+        write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
+        r = radeon_fence_wait(fence, false);
+        radeon_fence_unref(&fence);
+        return r;
+}
+
+struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
+{
+        kref_get(&fence->kref);
+        return fence;
+}
+
+void radeon_fence_unref(struct radeon_fence **fence)
+{
+        struct radeon_fence *tmp = *fence;
+
+        *fence = NULL;
+        if (tmp) {
+                kref_put(&tmp->kref, &radeon_fence_destroy);
+        }
+}
+
+void radeon_fence_process(struct radeon_device *rdev)
+{
+        unsigned long irq_flags;
+        bool wake;
+
+        write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
+        wake = radeon_fence_poll_locked(rdev);
+        write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
+        if (wake) {
+                wake_up_all(&rdev->fence_drv.queue);
+        }
+}
+
+int radeon_fence_driver_init(struct radeon_device *rdev)
+{
+        unsigned long irq_flags;
+        int r;
+
+        write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
+        r = radeon_scratch_get(rdev, &rdev->fence_drv.scratch_reg);
+        if (r) {
+                DRM_ERROR("Fence failed to get a scratch register.");
+                write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
+                return r;
+        }
+        WREG32(rdev->fence_drv.scratch_reg, 0);
+        atomic_set(&rdev->fence_drv.seq, 0);
+        INIT_LIST_HEAD(&rdev->fence_drv.created);
+        INIT_LIST_HEAD(&rdev->fence_drv.emited);
+        INIT_LIST_HEAD(&rdev->fence_drv.signaled);
+        rdev->fence_drv.count_timeout = 0;
+        init_waitqueue_head(&rdev->fence_drv.queue);
+        write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
+        if (radeon_debugfs_fence_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for fence !\n");
+        }
+        return 0;
+}
+
+void radeon_fence_driver_fini(struct radeon_device *rdev)
+{
+        unsigned long irq_flags;
+
+        wake_up_all(&rdev->fence_drv.queue);
+        write_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
+        radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg);
+        write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
+        DRM_INFO("radeon: fence finalized\n");
+}
+
+
+/*
+ * Fence debugfs
+ */
+#if defined(CONFIG_DEBUG_FS)
+static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *)m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_fence *fence;
+
+        seq_printf(m, "Last signaled fence 0x%08X\n",
+                   RREG32(rdev->fence_drv.scratch_reg));
+        if (!list_empty(&rdev->fence_drv.emited)) {
+                   fence = list_entry(rdev->fence_drv.emited.prev,
+                                      struct radeon_fence, list);
+                   seq_printf(m, "Last emited fence %p with 0x%08X\n",
+                              fence,  fence->seq);
+        }
+        return 0;
+}
+
+static struct drm_info_list radeon_debugfs_fence_list[] = {
+        {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
+};
+#endif
+
+int radeon_debugfs_fence_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1);
+#else
+        return 0;
+#endif
+}
diff --git a/drivers/gpu/drm/radeon/radeon_fixed.h b/drivers/gpu/drm/radeon/radeon_fixed.h
new file mode 100644
index 000000000000..90187d173847
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_fixed.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ */
+#ifndef RADEON_FIXED_H
+#define RADEON_FIXED_H
+
+typedef union rfixed {
+        u32 full;
+} fixed20_12;
+
+
+#define rfixed_const(A) (u32)(((A) << 12))/*  + ((B + 0.000122)*4096)) */
+#define rfixed_const_half(A) (u32)(((A) << 12) + 2048)
+#define rfixed_const_666(A) (u32)(((A) << 12) + 2731)
+#define rfixed_const_8(A) (u32)(((A) << 12) + 3277)
+#define rfixed_mul(A, B) ((u64)((u64)(A).full * (B).full + 2048) >> 12)
+#define fixed_init(A) { .full = rfixed_const((A)) }
+#define fixed_init_half(A) { .full = rfixed_const_half((A)) }
+#define rfixed_trunc(A) ((A).full >> 12)
+
+static inline u32 rfixed_div(fixed20_12 A, fixed20_12 B)
+{
+        u64 tmp = ((u64)A.full << 13);
+
+        do_div(tmp, B.full);
+        tmp += 1;
+        tmp /= 2;
+        return lower_32_bits(tmp);
+}
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
new file mode 100644
index 000000000000..d343a15316ec
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+#include "radeon_reg.h"
+
+/*
+ * Common GART table functions.
+ */
+int radeon_gart_table_ram_alloc(struct radeon_device *rdev)
+{
+        void *ptr;
+
+        ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size,
+                                   &rdev->gart.table_addr);
+        if (ptr == NULL) {
+                return -ENOMEM;
+        }
+#ifdef CONFIG_X86
+        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
+            rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
+                set_memory_uc((unsigned long)ptr,
+                              rdev->gart.table_size >> PAGE_SHIFT);
+        }
+#endif
+        rdev->gart.table.ram.ptr = ptr;
+        memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size);
+        return 0;
+}
+
+void radeon_gart_table_ram_free(struct radeon_device *rdev)
+{
+        if (rdev->gart.table.ram.ptr == NULL) {
+                return;
+        }
+#ifdef CONFIG_X86
+        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 ||
+            rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
+                set_memory_wb((unsigned long)rdev->gart.table.ram.ptr,
+                              rdev->gart.table_size >> PAGE_SHIFT);
+        }
+#endif
+        pci_free_consistent(rdev->pdev, rdev->gart.table_size,
+                            (void *)rdev->gart.table.ram.ptr,
+                            rdev->gart.table_addr);
+        rdev->gart.table.ram.ptr = NULL;
+        rdev->gart.table_addr = 0;
+}
+
+int radeon_gart_table_vram_alloc(struct radeon_device *rdev)
+{
+        uint64_t gpu_addr;
+        int r;
+
+        if (rdev->gart.table.vram.robj == NULL) {
+                r = radeon_object_create(rdev, NULL,
+                                         rdev->gart.table_size,
+                                         true,
+                                         RADEON_GEM_DOMAIN_VRAM,
+                                         false, &rdev->gart.table.vram.robj);
+                if (r) {
+                        return r;
+                }
+        }
+        r = radeon_object_pin(rdev->gart.table.vram.robj,
+                              RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
+        if (r) {
+                radeon_object_unref(&rdev->gart.table.vram.robj);
+                return r;
+        }
+        r = radeon_object_kmap(rdev->gart.table.vram.robj,
+                               (void **)&rdev->gart.table.vram.ptr);
+        if (r) {
+                radeon_object_unpin(rdev->gart.table.vram.robj);
+                radeon_object_unref(&rdev->gart.table.vram.robj);
+                DRM_ERROR("radeon: failed to map gart vram table.\n");
+                return r;
+        }
+        rdev->gart.table_addr = gpu_addr;
+        return 0;
+}
+
+void radeon_gart_table_vram_free(struct radeon_device *rdev)
+{
+        if (rdev->gart.table.vram.robj == NULL) {
+                return;
+        }
+        radeon_object_kunmap(rdev->gart.table.vram.robj);
+        radeon_object_unpin(rdev->gart.table.vram.robj);
+        radeon_object_unref(&rdev->gart.table.vram.robj);
+}
+
+
+
+
+/*
+ * Common gart functions.
+ */
+void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
+                        int pages)
+{
+        unsigned t;
+        unsigned p;
+        int i, j;
+
+        if (!rdev->gart.ready) {
+                WARN(1, "trying to unbind memory to unitialized GART !\n");
+                return;
+        }
+        t = offset / 4096;
+        p = t / (PAGE_SIZE / 4096);
+        for (i = 0; i < pages; i++, p++) {
+                if (rdev->gart.pages[p]) {
+                        pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
+                                       PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
+                        rdev->gart.pages[p] = NULL;
+                        rdev->gart.pages_addr[p] = 0;
+                        for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) {
+                                radeon_gart_set_page(rdev, t, 0);
+                        }
+                }
+        }
+        mb();
+        radeon_gart_tlb_flush(rdev);
+}
+
+int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
+                     int pages, struct page **pagelist)
+{
+        unsigned t;
+        unsigned p;
+        uint64_t page_base;
+        int i, j;
+
+        if (!rdev->gart.ready) {
+                DRM_ERROR("trying to bind memory to unitialized GART !\n");
+                return -EINVAL;
+        }
+        t = offset / 4096;
+        p = t / (PAGE_SIZE / 4096);
+
+        for (i = 0; i < pages; i++, p++) {
+                /* we need to support large memory configurations */
+                /* assume that unbind have already been call on the range */
+                rdev->gart.pages_addr[p] = pci_map_page(rdev->pdev, pagelist[i],
+                                                        0, PAGE_SIZE,
+                                                        PCI_DMA_BIDIRECTIONAL);
+                if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) {
+                        /* FIXME: failed to map page (return -ENOMEM?) */
+                        radeon_gart_unbind(rdev, offset, pages);
+                        return -ENOMEM;
+                }
+                rdev->gart.pages[p] = pagelist[i];
+                page_base = (uint32_t)rdev->gart.pages_addr[p];
+                for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) {
+                        radeon_gart_set_page(rdev, t, page_base);
+                        page_base += 4096;
+                }
+        }
+        mb();
+        radeon_gart_tlb_flush(rdev);
+        return 0;
+}
+
+int radeon_gart_init(struct radeon_device *rdev)
+{
+        if (rdev->gart.pages) {
+                return 0;
+        }
+        /* We need PAGE_SIZE >= 4096 */
+        if (PAGE_SIZE < 4096) {
+                DRM_ERROR("Page size is smaller than GPU page size!\n");
+                return -EINVAL;
+        }
+        /* Compute table size */
+        rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
+        rdev->gart.num_gpu_pages = rdev->mc.gtt_size / 4096;
+        DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
+                 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
+        /* Allocate pages table */
+        rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages,
+                                   GFP_KERNEL);
+        if (rdev->gart.pages == NULL) {
+                radeon_gart_fini(rdev);
+                return -ENOMEM;
+        }
+        rdev->gart.pages_addr = kzalloc(sizeof(dma_addr_t) *
+                                        rdev->gart.num_cpu_pages, GFP_KERNEL);
+        if (rdev->gart.pages_addr == NULL) {
+                radeon_gart_fini(rdev);
+                return -ENOMEM;
+        }
+        return 0;
+}
+
+void radeon_gart_fini(struct radeon_device *rdev)
+{
+        if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) {
+                /* unbind pages */
+                radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages);
+        }
+        rdev->gart.ready = false;
+        kfree(rdev->gart.pages);
+        kfree(rdev->gart.pages_addr);
+        rdev->gart.pages = NULL;
+        rdev->gart.pages_addr = NULL;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
new file mode 100644
index 000000000000..eb516034235d
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "drm.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+
+int radeon_gem_object_init(struct drm_gem_object *obj)
+{
+        /* we do nothings here */
+        return 0;
+}
+
+void radeon_gem_object_free(struct drm_gem_object *gobj)
+{
+        struct radeon_object *robj = gobj->driver_private;
+
+        gobj->driver_private = NULL;
+        if (robj) {
+                radeon_object_unref(&robj);
+        }
+}
+
+int radeon_gem_object_create(struct radeon_device *rdev, int size,
+                             int alignment, int initial_domain,
+                             bool discardable, bool kernel,
+                             bool interruptible,
+                             struct drm_gem_object **obj)
+{
+        struct drm_gem_object *gobj;
+        struct radeon_object *robj;
+        int r;
+
+        *obj = NULL;
+        gobj = drm_gem_object_alloc(rdev->ddev, size);
+        if (!gobj) {
+                return -ENOMEM;
+        }
+        /* At least align on page size */
+        if (alignment < PAGE_SIZE) {
+                alignment = PAGE_SIZE;
+        }
+        r = radeon_object_create(rdev, gobj, size, kernel, initial_domain,
+                                 interruptible, &robj);
+        if (r) {
+                DRM_ERROR("Failed to allocate GEM object (%d, %d, %u)\n",
+                          size, initial_domain, alignment);
+                mutex_lock(&rdev->ddev->struct_mutex);
+                drm_gem_object_unreference(gobj);
+                mutex_unlock(&rdev->ddev->struct_mutex);
+                return r;
+        }
+        gobj->driver_private = robj;
+        *obj = gobj;
+        return 0;
+}
+
+int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
+                          uint64_t *gpu_addr)
+{
+        struct radeon_object *robj = obj->driver_private;
+        uint32_t flags;
+
+        switch (pin_domain) {
+        case RADEON_GEM_DOMAIN_VRAM:
+                flags = TTM_PL_FLAG_VRAM;
+                break;
+        case RADEON_GEM_DOMAIN_GTT:
+                flags = TTM_PL_FLAG_TT;
+                break;
+        default:
+                flags = TTM_PL_FLAG_SYSTEM;
+                break;
+        }
+        return radeon_object_pin(robj, flags, gpu_addr);
+}
+
+void radeon_gem_object_unpin(struct drm_gem_object *obj)
+{
+        struct radeon_object *robj = obj->driver_private;
+        radeon_object_unpin(robj);
+}
+
+int radeon_gem_set_domain(struct drm_gem_object *gobj,
+                          uint32_t rdomain, uint32_t wdomain)
+{
+        struct radeon_object *robj;
+        uint32_t domain;
+        int r;
+
+        /* FIXME: reeimplement */
+        robj = gobj->driver_private;
+        /* work out where to validate the buffer to */
+        domain = wdomain;
+        if (!domain) {
+                domain = rdomain;
+        }
+        if (!domain) {
+                /* Do nothings */
+                printk(KERN_WARNING "Set domain withou domain !\n");
+                return 0;
+        }
+        if (domain == RADEON_GEM_DOMAIN_CPU) {
+                /* Asking for cpu access wait for object idle */
+                r = radeon_object_wait(robj);
+                if (r) {
+                        printk(KERN_ERR "Failed to wait for object !\n");
+                        return r;
+                }
+        }
+        return 0;
+}
+
+int radeon_gem_init(struct radeon_device *rdev)
+{
+        INIT_LIST_HEAD(&rdev->gem.objects);
+        return 0;
+}
+
+void radeon_gem_fini(struct radeon_device *rdev)
+{
+        radeon_object_force_delete(rdev);
+}
+
+
+/*
+ * GEM ioctls.
+ */
+int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
+                          struct drm_file *filp)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_radeon_gem_info *args = data;
+
+        args->vram_size = rdev->mc.vram_size;
+        /* FIXME: report somethings that makes sense */
+        args->vram_visible = rdev->mc.vram_size - (4 * 1024 * 1024);
+        args->gart_size = rdev->mc.gtt_size;
+        return 0;
+}
+
+int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
+                           struct drm_file *filp)
+{
+        /* TODO: implement */
+        DRM_ERROR("unimplemented %s\n", __func__);
+        return -ENOSYS;
+}
+
+int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
+                            struct drm_file *filp)
+{
+        /* TODO: implement */
+        DRM_ERROR("unimplemented %s\n", __func__);
+        return -ENOSYS;
+}
+
+int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
+                            struct drm_file *filp)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_radeon_gem_create *args = data;
+        struct drm_gem_object *gobj;
+        uint32_t handle;
+        int r;
+
+        /* create a gem object to contain this object in */
+        args->size = roundup(args->size, PAGE_SIZE);
+        r = radeon_gem_object_create(rdev, args->size, args->alignment,
+                                     args->initial_domain, false,
+                                     false, true, &gobj);
+        if (r) {
+                return r;
+        }
+        r = drm_gem_handle_create(filp, gobj, &handle);
+        if (r) {
+                mutex_lock(&dev->struct_mutex);
+                drm_gem_object_unreference(gobj);
+                mutex_unlock(&dev->struct_mutex);
+                return r;
+        }
+        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_handle_unreference(gobj);
+        mutex_unlock(&dev->struct_mutex);
+        args->handle = handle;
+        return 0;
+}
+
+int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
+                                struct drm_file *filp)
+{
+        /* transition the BO to a domain -
+         * just validate the BO into a certain domain */
+        struct drm_radeon_gem_set_domain *args = data;
+        struct drm_gem_object *gobj;
+        struct radeon_object *robj;
+        int r;
+
+        /* for now if someone requests domain CPU -
+         * just make sure the buffer is finished with */
+
+        /* just do a BO wait for now */
+        gobj = drm_gem_object_lookup(dev, filp, args->handle);
+        if (gobj == NULL) {
+                return -EINVAL;
+        }
+        robj = gobj->driver_private;
+
+        r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain);
+
+        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference(gobj);
+        mutex_unlock(&dev->struct_mutex);
+        return r;
+}
+
+int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
+                          struct drm_file *filp)
+{
+        struct drm_radeon_gem_mmap *args = data;
+        struct drm_gem_object *gobj;
+        struct radeon_object *robj;
+        int r;
+
+        gobj = drm_gem_object_lookup(dev, filp, args->handle);
+        if (gobj == NULL) {
+                return -EINVAL;
+        }
+        robj = gobj->driver_private;
+        r = radeon_object_mmap(robj, &args->addr_ptr);
+        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference(gobj);
+        mutex_unlock(&dev->struct_mutex);
+        return r;
+}
+
+int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
+                          struct drm_file *filp)
+{
+        /* FIXME: implement */
+        return 0;
+}
+
+int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
+                              struct drm_file *filp)
+{
+        struct drm_radeon_gem_wait_idle *args = data;
+        struct drm_gem_object *gobj;
+        struct radeon_object *robj;
+        int r;
+
+        gobj = drm_gem_object_lookup(dev, filp, args->handle);
+        if (gobj == NULL) {
+                return -EINVAL;
+        }
+        robj = gobj->driver_private;
+        r = radeon_object_wait(robj);
+        mutex_lock(&dev->struct_mutex);
+        drm_gem_object_unreference(gobj);
+        mutex_unlock(&dev->struct_mutex);
+        return r;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
new file mode 100644
index 000000000000..71465ed2688a
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+
+/**
+ * radeon_ddc_probe
+ *
+ */
+bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
+{
+        u8 out_buf[] = { 0x0, 0x0};
+        u8 buf[2];
+        int ret;
+        struct i2c_msg msgs[] = {
+                {
+                        .addr = 0x50,
+                        .flags = 0,
+                        .len = 1,
+                        .buf = out_buf,
+                },
+                {
+                        .addr = 0x50,
+                        .flags = I2C_M_RD,
+                        .len = 1,
+                        .buf = buf,
+                }
+        };
+
+        ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
+        if (ret == 2)
+                return true;
+
+        return false;
+}
+
+
+void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state)
+{
+        struct radeon_device *rdev = radeon_connector->base.dev->dev_private;
+        uint32_t temp;
+        struct radeon_i2c_bus_rec *rec = &radeon_connector->ddc_bus->rec;
+
+        /* RV410 appears to have a bug where the hw i2c in reset
+         * holds the i2c port in a bad state - switch hw i2c away before
+         * doing DDC - do this for all r200s/r300s/r400s for safety sake
+         */
+        if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
+                if (rec->a_clk_reg == RADEON_GPIO_MONID) {
+                        WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
+                                                R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
+                } else {
+                        WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
+                                                R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
+                }
+        }
+        if (lock_state) {
+                temp = RREG32(rec->a_clk_reg);
+                temp &= ~(rec->a_clk_mask);
+                WREG32(rec->a_clk_reg, temp);
+
+                temp = RREG32(rec->a_data_reg);
+                temp &= ~(rec->a_data_mask);
+                WREG32(rec->a_data_reg, temp);
+        }
+
+        temp = RREG32(rec->mask_clk_reg);
+        if (lock_state)
+                temp |= rec->mask_clk_mask;
+        else
+                temp &= ~rec->mask_clk_mask;
+        WREG32(rec->mask_clk_reg, temp);
+        temp = RREG32(rec->mask_clk_reg);
+
+        temp = RREG32(rec->mask_data_reg);
+        if (lock_state)
+                temp |= rec->mask_data_mask;
+        else
+                temp &= ~rec->mask_data_mask;
+        WREG32(rec->mask_data_reg, temp);
+        temp = RREG32(rec->mask_data_reg);
+}
+
+static int get_clock(void *i2c_priv)
+{
+        struct radeon_i2c_chan *i2c = i2c_priv;
+        struct radeon_device *rdev = i2c->dev->dev_private;
+        struct radeon_i2c_bus_rec *rec = &i2c->rec;
+        uint32_t val;
+
+        val = RREG32(rec->get_clk_reg);
+        val &= rec->get_clk_mask;
+
+        return (val != 0);
+}
+
+
+static int get_data(void *i2c_priv)
+{
+        struct radeon_i2c_chan *i2c = i2c_priv;
+        struct radeon_device *rdev = i2c->dev->dev_private;
+        struct radeon_i2c_bus_rec *rec = &i2c->rec;
+        uint32_t val;
+
+        val = RREG32(rec->get_data_reg);
+        val &= rec->get_data_mask;
+        return (val != 0);
+}
+
+static void set_clock(void *i2c_priv, int clock)
+{
+        struct radeon_i2c_chan *i2c = i2c_priv;
+        struct radeon_device *rdev = i2c->dev->dev_private;
+        struct radeon_i2c_bus_rec *rec = &i2c->rec;
+        uint32_t val;
+
+        val = RREG32(rec->put_clk_reg) & (uint32_t)~(rec->put_clk_mask);
+        val |= clock ? 0 : rec->put_clk_mask;
+        WREG32(rec->put_clk_reg, val);
+}
+
+static void set_data(void *i2c_priv, int data)
+{
+        struct radeon_i2c_chan *i2c = i2c_priv;
+        struct radeon_device *rdev = i2c->dev->dev_private;
+        struct radeon_i2c_bus_rec *rec = &i2c->rec;
+        uint32_t val;
+
+        val = RREG32(rec->put_data_reg) & (uint32_t)~(rec->put_data_mask);
+        val |= data ? 0 : rec->put_data_mask;
+        WREG32(rec->put_data_reg, val);
+}
+
+struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
+                struct radeon_i2c_bus_rec *rec,
+                const char *name)
+{
+        struct radeon_i2c_chan *i2c;
+        int ret;
+
+        i2c = drm_calloc(1, sizeof(struct radeon_i2c_chan), DRM_MEM_DRIVER);
+        if (i2c == NULL)
+                return NULL;
+
+        i2c->adapter.owner = THIS_MODULE;
+        i2c->adapter.algo_data = &i2c->algo;
+        i2c->dev = dev;
+        i2c->algo.setsda = set_data;
+        i2c->algo.setscl = set_clock;
+        i2c->algo.getsda = get_data;
+        i2c->algo.getscl = get_clock;
+        i2c->algo.udelay = 20;
+        /* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always
+         * make this, 2 jiffies is a lot more reliable */
+        i2c->algo.timeout = 2;
+        i2c->algo.data = i2c;
+        i2c->rec = *rec;
+        i2c_set_adapdata(&i2c->adapter, i2c);
+
+        ret = i2c_bit_add_bus(&i2c->adapter);
+        if (ret) {
+                DRM_INFO("Failed to register i2c %s\n", name);
+                goto out_free;
+        }
+
+        return i2c;
+out_free:
+        drm_free(i2c, sizeof(struct radeon_i2c_chan), DRM_MEM_DRIVER);
+        return NULL;
+
+}
+
+void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
+{
+        if (!i2c)
+                return;
+
+        i2c_del_adapter(&i2c->adapter);
+        drm_free(i2c, sizeof(struct radeon_i2c_chan), DRM_MEM_DRIVER);
+}
+
+struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
+{
+        return NULL;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
new file mode 100644
index 000000000000..491d569deb0e
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon_reg.h"
+#include "radeon_microcode.h"
+#include "radeon.h"
+#include "atom.h"
+
+static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
+{
+        uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
+        uint32_t irq_mask = RADEON_SW_INT_TEST;
+
+        if (irqs) {
+                WREG32(RADEON_GEN_INT_STATUS, irqs);
+        }
+        return irqs & irq_mask;
+}
+
+int r100_irq_set(struct radeon_device *rdev)
+{
+        uint32_t tmp = 0;
+
+        if (rdev->irq.sw_int) {
+                tmp |= RADEON_SW_INT_ENABLE;
+        }
+        /* Todo go through CRTC and enable vblank int or not */
+        WREG32(RADEON_GEN_INT_CNTL, tmp);
+        return 0;
+}
+
+int r100_irq_process(struct radeon_device *rdev)
+{
+        uint32_t status;
+
+        status = r100_irq_ack(rdev);
+        if (!status) {
+                return IRQ_NONE;
+        }
+        while (status) {
+                /* SW interrupt */
+                if (status & RADEON_SW_INT_TEST) {
+                        radeon_fence_process(rdev);
+                }
+                status = r100_irq_ack(rdev);
+        }
+        return IRQ_HANDLED;
+}
+
+int rs600_irq_set(struct radeon_device *rdev)
+{
+        uint32_t tmp = 0;
+
+        if (rdev->irq.sw_int) {
+                tmp |= RADEON_SW_INT_ENABLE;
+        }
+        WREG32(RADEON_GEN_INT_CNTL, tmp);
+        /* Todo go through CRTC and enable vblank int or not */
+        WREG32(R500_DxMODE_INT_MASK, 0);
+        return 0;
+}
+
+irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS)
+{
+        struct drm_device *dev = (struct drm_device *) arg;
+        struct radeon_device *rdev = dev->dev_private;
+
+        return radeon_irq_process(rdev);
+}
+
+void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        unsigned i;
+
+        /* Disable *all* interrupts */
+        rdev->irq.sw_int = false;
+        for (i = 0; i < 2; i++) {
+                rdev->irq.crtc_vblank_int[i] = false;
+        }
+        radeon_irq_set(rdev);
+        /* Clear bits */
+        radeon_irq_process(rdev);
+}
+
+int radeon_driver_irq_postinstall_kms(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+
+        dev->max_vblank_count = 0x001fffff;
+        rdev->irq.sw_int = true;
+        radeon_irq_set(rdev);
+        return 0;
+}
+
+void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        unsigned i;
+
+        if (rdev == NULL) {
+                return;
+        }
+        /* Disable *all* interrupts */
+        rdev->irq.sw_int = false;
+        for (i = 0; i < 2; i++) {
+                rdev->irq.crtc_vblank_int[i] = false;
+        }
+        radeon_irq_set(rdev);
+}
+
+int radeon_irq_kms_init(struct radeon_device *rdev)
+{
+        int r = 0;
+
+        r = drm_vblank_init(rdev->ddev, 2);
+        if (r) {
+                return r;
+        }
+        drm_irq_install(rdev->ddev);
+        rdev->irq.installed = true;
+        DRM_INFO("radeon: irq initialized.\n");
+        return 0;
+}
+
+void radeon_irq_kms_fini(struct radeon_device *rdev)
+{
+        if (rdev->irq.installed) {
+                rdev->irq.installed = false;
+                drm_irq_uninstall(rdev->ddev);
+        }
+}
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
new file mode 100644
index 000000000000..64f42b19cbfa
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -0,0 +1,295 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "drm_sarea.h"
+#include "radeon.h"
+#include "radeon_drm.h"
+
+
+/*
+ * Driver load/unload
+ */
+int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
+{
+        struct radeon_device *rdev;
+        int r;
+
+        rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
+        if (rdev == NULL) {
+                return -ENOMEM;
+        }
+        dev->dev_private = (void *)rdev;
+
+        /* update BUS flag */
+        if (drm_device_is_agp(dev)) {
+                flags |= RADEON_IS_AGP;
+        } else if (drm_device_is_pcie(dev)) {
+                flags |= RADEON_IS_PCIE;
+        } else {
+                flags |= RADEON_IS_PCI;
+        }
+
+        r = radeon_device_init(rdev, dev, dev->pdev, flags);
+        if (r) {
+                DRM_ERROR("Failed to initialize radeon, disabling IOCTL\n");
+                radeon_device_fini(rdev);
+                return r;
+        }
+        return 0;
+}
+
+int radeon_driver_unload_kms(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+
+        radeon_device_fini(rdev);
+        kfree(rdev);
+        dev->dev_private = NULL;
+        return 0;
+}
+
+
+/*
+ * Userspace get informations ioctl
+ */
+int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_radeon_info *info;
+        uint32_t *value_ptr;
+        uint32_t value;
+
+        info = data;
+        value_ptr = (uint32_t *)((unsigned long)info->value);
+        switch (info->request) {
+        case RADEON_INFO_DEVICE_ID:
+                value = dev->pci_device;
+                break;
+        case RADEON_INFO_NUM_GB_PIPES:
+                value = rdev->num_gb_pipes;
+                break;
+        default:
+                DRM_DEBUG("Invalid request %d\n", info->request);
+                return -EINVAL;
+        }
+        if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
+                DRM_ERROR("copy_to_user\n");
+                return -EFAULT;
+        }
+        return 0;
+}
+
+
+/*
+ * Outdated mess for old drm with Xorg being in charge (void function now).
+ */
+int radeon_driver_firstopen_kms(struct drm_device *dev)
+{
+        return 0;
+}
+
+
+void radeon_driver_lastclose_kms(struct drm_device *dev)
+{
+}
+
+int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
+{
+        return 0;
+}
+
+void radeon_driver_postclose_kms(struct drm_device *dev,
+                                 struct drm_file *file_priv)
+{
+}
+
+void radeon_driver_preclose_kms(struct drm_device *dev,
+                                struct drm_file *file_priv)
+{
+}
+
+
+/*
+ * VBlank related functions.
+ */
+u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
+{
+        /* FIXME: implement */
+        return 0;
+}
+
+int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
+{
+        /* FIXME: implement */
+        return 0;
+}
+
+void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
+{
+        /* FIXME: implement */
+}
+
+
+/*
+ * For multiple master (like multiple X).
+ */
+struct drm_radeon_master_private {
+        drm_local_map_t *sarea;
+        drm_radeon_sarea_t *sarea_priv;
+};
+
+int radeon_master_create_kms(struct drm_device *dev, struct drm_master *master)
+{
+        struct drm_radeon_master_private *master_priv;
+        unsigned long sareapage;
+        int ret;
+
+        master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
+        if (master_priv == NULL) {
+                return -ENOMEM;
+        }
+        /* prebuild the SAREA */
+        sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
+        ret = drm_addmap(dev, 0, sareapage, _DRM_SHM,
+                         _DRM_CONTAINS_LOCK,
+                         &master_priv->sarea);
+        if (ret) {
+                DRM_ERROR("SAREA setup failed\n");
+                return ret;
+        }
+        master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
+        master_priv->sarea_priv->pfCurrentPage = 0;
+        master->driver_priv = master_priv;
+        return 0;
+}
+
+void radeon_master_destroy_kms(struct drm_device *dev,
+                               struct drm_master *master)
+{
+        struct drm_radeon_master_private *master_priv = master->driver_priv;
+
+        if (master_priv == NULL) {
+                return;
+        }
+        if (master_priv->sarea) {
+                drm_rmmap_locked(dev, master_priv->sarea);
+        }
+        drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
+        master->driver_priv = NULL;
+}
+
+
+/*
+ * IOCTL.
+ */
+int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
+                         struct drm_file *file_priv)
+{
+        /* Not valid in KMS. */
+        return -EINVAL;
+}
+
+#define KMS_INVALID_IOCTL(name)                                         \
+int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
+{                                                                       \
+        DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
+        return -EINVAL;                                                 \
+}
+
+/*
+ * All these ioctls are invalid in kms world.
+ */
+KMS_INVALID_IOCTL(radeon_cp_init_kms)
+KMS_INVALID_IOCTL(radeon_cp_start_kms)
+KMS_INVALID_IOCTL(radeon_cp_stop_kms)
+KMS_INVALID_IOCTL(radeon_cp_reset_kms)
+KMS_INVALID_IOCTL(radeon_cp_idle_kms)
+KMS_INVALID_IOCTL(radeon_cp_resume_kms)
+KMS_INVALID_IOCTL(radeon_engine_reset_kms)
+KMS_INVALID_IOCTL(radeon_fullscreen_kms)
+KMS_INVALID_IOCTL(radeon_cp_swap_kms)
+KMS_INVALID_IOCTL(radeon_cp_clear_kms)
+KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
+KMS_INVALID_IOCTL(radeon_cp_indices_kms)
+KMS_INVALID_IOCTL(radeon_cp_texture_kms)
+KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
+KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
+KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
+KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
+KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
+KMS_INVALID_IOCTL(radeon_cp_flip_kms)
+KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
+KMS_INVALID_IOCTL(radeon_mem_free_kms)
+KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
+KMS_INVALID_IOCTL(radeon_irq_emit_kms)
+KMS_INVALID_IOCTL(radeon_irq_wait_kms)
+KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
+KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
+KMS_INVALID_IOCTL(radeon_surface_free_kms)
+
+
+struct drm_ioctl_desc radeon_ioctls_kms[] = {
+        DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+        DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+        DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+        DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+        DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+        DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+        DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
+        /* KMS */
+        DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH),
+        DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH),
+};
+int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
new file mode 100644
index 000000000000..8086ecf7f03d
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -0,0 +1,1276 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/radeon_drm.h>
+#include "radeon_fixed.h"
+#include "radeon.h"
+
+void radeon_restore_common_regs(struct drm_device *dev)
+{
+        /* don't need this yet */
+}
+
+static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        int i = 0;
+
+        /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
+           the cause yet, but this workaround will mask the problem for now.
+           Other chips usually will pass at the very first test, so the
+           workaround shouldn't have any effect on them. */
+        for (i = 0;
+             (i < 10000 &&
+              RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
+             i++);
+}
+
+static void radeon_pll_write_update(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+
+        while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
+
+        WREG32_PLL_P(RADEON_PPLL_REF_DIV,
+                           RADEON_PPLL_ATOMIC_UPDATE_W,
+                           ~(RADEON_PPLL_ATOMIC_UPDATE_W));
+}
+
+static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        int i = 0;
+
+
+        /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
+           the cause yet, but this workaround will mask the problem for now.
+           Other chips usually will pass at the very first test, so the
+           workaround shouldn't have any effect on them. */
+        for (i = 0;
+             (i < 10000 &&
+              RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
+             i++);
+}
+
+static void radeon_pll2_write_update(struct drm_device *dev)
+{
+        struct radeon_device *rdev = dev->dev_private;
+
+        while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
+
+        WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
+                           RADEON_P2PLL_ATOMIC_UPDATE_W,
+                           ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
+}
+
+static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
+                                       uint16_t fb_div)
+{
+        unsigned int vcoFreq;
+
+        if (!ref_div)
+                return 1;
+
+        vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
+
+        /*
+         * This is horribly crude: the VCO frequency range is divided into
+         * 3 parts, each part having a fixed PLL gain value.
+         */
+        if (vcoFreq >= 30000)
+                /*
+                 * [300..max] MHz : 7
+                 */
+                return 7;
+        else if (vcoFreq >= 18000)
+                /*
+                 * [180..300) MHz : 4
+                 */
+                return 4;
+        else
+                /*
+                 * [0..180) MHz : 1
+                 */
+                return 1;
+}
+
+void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
+{
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t mask;
+
+        if (radeon_crtc->crtc_id)
+                mask = (RADEON_CRTC2_EN |
+                        RADEON_CRTC2_DISP_DIS |
+                        RADEON_CRTC2_VSYNC_DIS |
+                        RADEON_CRTC2_HSYNC_DIS |
+                        RADEON_CRTC2_DISP_REQ_EN_B);
+        else
+                mask = (RADEON_CRTC_DISPLAY_DIS |
+                        RADEON_CRTC_VSYNC_DIS |
+                        RADEON_CRTC_HSYNC_DIS);
+
+        switch (mode) {
+        case DRM_MODE_DPMS_ON:
+                if (radeon_crtc->crtc_id)
+                        WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
+                else {
+                        WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
+                                                                         RADEON_CRTC_DISP_REQ_EN_B));
+                        WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
+                }
+                break;
+        case DRM_MODE_DPMS_STANDBY:
+        case DRM_MODE_DPMS_SUSPEND:
+        case DRM_MODE_DPMS_OFF:
+                if (radeon_crtc->crtc_id)
+                        WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
+                else {
+                        WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
+                                                                                    RADEON_CRTC_DISP_REQ_EN_B));
+                        WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
+                }
+                break;
+        }
+
+        if (mode != DRM_MODE_DPMS_OFF) {
+                radeon_crtc_load_lut(crtc);
+        }
+}
+
+/* properly set crtc bpp when using atombios */
+void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
+{
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        int format;
+        uint32_t crtc_gen_cntl;
+        uint32_t disp_merge_cntl;
+        uint32_t crtc_pitch;
+
+        switch (crtc->fb->bits_per_pixel) {
+        case 15:      /*  555 */
+                format = 3;
+                break;
+        case 16:      /*  565 */
+                format = 4;
+                break;
+        case 24:      /*  RGB */
+                format = 5;
+                break;
+        case 32:      /* xRGB */
+                format = 6;
+                break;
+        default:
+                return;
+        }
+
+        crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
+                        ((crtc->fb->bits_per_pixel * 8) - 1)) /
+                       (crtc->fb->bits_per_pixel * 8));
+        crtc_pitch |= crtc_pitch << 16;
+
+        WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
+
+        switch (radeon_crtc->crtc_id) {
+        case 0:
+                disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
+                disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
+                WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
+
+                crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
+                crtc_gen_cntl |= (format << 8);
+                crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
+                WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
+                break;
+        case 1:
+                disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
+                disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
+                WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
+
+                crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
+                crtc_gen_cntl |= (format << 8);
+                WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
+                WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
+                WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
+                break;
+        }
+}
+
+int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
+                         struct drm_framebuffer *old_fb)
+{
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct radeon_framebuffer *radeon_fb;
+        struct drm_gem_object *obj;
+        uint64_t base;
+        uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
+        uint32_t crtc_pitch, pitch_pixels;
+
+        DRM_DEBUG("\n");
+
+        radeon_fb = to_radeon_framebuffer(crtc->fb);
+
+        obj = radeon_fb->obj;
+        if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &base)) {
+                return -EINVAL;
+        }
+        crtc_offset = (u32)base;
+        crtc_offset_cntl = 0;
+
+        pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
+        crtc_pitch  = (((pitch_pixels * crtc->fb->bits_per_pixel) +
+                        ((crtc->fb->bits_per_pixel * 8) - 1)) /
+                       (crtc->fb->bits_per_pixel * 8));
+        crtc_pitch |= crtc_pitch << 16;
+
+        /* TODO tiling */
+        if (0) {
+                if (ASIC_IS_R300(rdev))
+                        crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
+                                             R300_CRTC_MICRO_TILE_BUFFER_DIS |
+                                             R300_CRTC_MACRO_TILE_EN);
+                else
+                        crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
+        } else {
+                if (ASIC_IS_R300(rdev))
+                        crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
+                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
+                                              R300_CRTC_MACRO_TILE_EN);
+                else
+                        crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
+        }
+
+
+        /* TODO more tiling */
+        if (0) {
+                if (ASIC_IS_R300(rdev)) {
+                        crtc_tile_x0_y0 = x | (y << 16);
+                        base &= ~0x7ff;
+                } else {
+                        int byteshift = crtc->fb->bits_per_pixel >> 4;
+                        int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
+                        base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
+                        crtc_offset_cntl |= (y % 16);
+                }
+        } else {
+                int offset = y * pitch_pixels + x;
+                switch (crtc->fb->bits_per_pixel) {
+                case 15:
+                case 16:
+                        offset *= 2;
+                        break;
+                case 24:
+                        offset *= 3;
+                        break;
+                case 32:
+                        offset *= 4;
+                        break;
+                default:
+                        return false;
+                }
+                base += offset;
+        }
+
+        base &= ~7;
+
+        /* update sarea TODO */
+
+        crtc_offset = (u32)base;
+
+        WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, rdev->mc.vram_location);
+
+        if (ASIC_IS_R300(rdev)) {
+                if (radeon_crtc->crtc_id)
+                        WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
+                else
+                        WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
+        }
+        WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
+        WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
+        WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
+
+        if (old_fb && old_fb != crtc->fb) {
+                radeon_fb = to_radeon_framebuffer(old_fb);
+                radeon_gem_object_unpin(radeon_fb->obj);
+        }
+        return 0;
+}
+
+static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
+{
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        int format;
+        int hsync_start;
+        int hsync_wid;
+        int vsync_wid;
+        uint32_t crtc_h_total_disp;
+        uint32_t crtc_h_sync_strt_wid;
+        uint32_t crtc_v_total_disp;
+        uint32_t crtc_v_sync_strt_wid;
+
+        DRM_DEBUG("\n");
+
+        switch (crtc->fb->bits_per_pixel) {
+        case 15:      /*  555 */
+                format = 3;
+                break;
+        case 16:      /*  565 */
+                format = 4;
+                break;
+        case 24:      /*  RGB */
+                format = 5;
+                break;
+        case 32:      /* xRGB */
+                format = 6;
+                break;
+        default:
+                return false;
+        }
+
+        crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
+                             | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
+
+        hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
+        if (!hsync_wid)
+                hsync_wid = 1;
+        hsync_start = mode->crtc_hsync_start - 8;
+
+        crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
+                                | ((hsync_wid & 0x3f) << 16)
+                                | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
+                                   ? RADEON_CRTC_H_SYNC_POL
+                                   : 0));
+
+        /* This works for double scan mode. */
+        crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
+                             | ((mode->crtc_vdisplay - 1) << 16));
+
+        vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
+        if (!vsync_wid)
+                vsync_wid = 1;
+
+        crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
+                                | ((vsync_wid & 0x1f) << 16)
+                                | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
+                                   ? RADEON_CRTC_V_SYNC_POL
+                                   : 0));
+
+        /* TODO -> Dell Server */
+        if (0) {
+                uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
+                uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
+                uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
+                uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
+
+                dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
+                dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
+
+                /* For CRT on DAC2, don't turn it on if BIOS didn't
+                   enable it, even it's detected.
+                */
+                disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+                tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
+                tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
+
+                WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+                WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
+                WREG32(RADEON_DAC_CNTL2, dac2_cntl);
+                WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+        }
+
+        if (radeon_crtc->crtc_id) {
+                uint32_t crtc2_gen_cntl;
+                uint32_t disp2_merge_cntl;
+
+                /* check to see if TV DAC is enabled for another crtc and keep it enabled */
+                if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
+                        crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
+                else
+                        crtc2_gen_cntl = 0;
+
+                crtc2_gen_cntl |= ((format << 8)
+                                   | RADEON_CRTC2_VSYNC_DIS
+                                   | RADEON_CRTC2_HSYNC_DIS
+                                   | RADEON_CRTC2_DISP_DIS
+                                   | RADEON_CRTC2_DISP_REQ_EN_B
+                                   | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
+                                      ? RADEON_CRTC2_DBL_SCAN_EN
+                                      : 0)
+                                   | ((mode->flags & DRM_MODE_FLAG_CSYNC)
+                                      ? RADEON_CRTC2_CSYNC_EN
+                                      : 0)
+                                   | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
+                                      ? RADEON_CRTC2_INTERLACE_EN
+                                      : 0));
+
+                disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
+                disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
+
+                WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
+                WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+        } else {
+                uint32_t crtc_gen_cntl;
+                uint32_t crtc_ext_cntl;
+                uint32_t disp_merge_cntl;
+
+                crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
+                                 | (format << 8)
+                                 | RADEON_CRTC_DISP_REQ_EN_B
+                                 | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
+                                    ? RADEON_CRTC_DBL_SCAN_EN
+                                    : 0)
+                                 | ((mode->flags & DRM_MODE_FLAG_CSYNC)
+                                    ? RADEON_CRTC_CSYNC_EN
+                                    : 0)
+                                 | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
+                                    ? RADEON_CRTC_INTERLACE_EN
+                                    : 0));
+
+                crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
+                crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
+                                  RADEON_CRTC_VSYNC_DIS |
+                                  RADEON_CRTC_HSYNC_DIS |
+                                  RADEON_CRTC_DISPLAY_DIS);
+
+                disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
+                disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
+
+                WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
+                WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
+                WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
+        }
+
+        WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
+        WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
+        WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
+        WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
+
+        return true;
+}
+
+static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
+{
+        struct drm_device *dev = crtc->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+        struct drm_encoder *encoder;
+        uint32_t feedback_div = 0;
+        uint32_t frac_fb_div = 0;
+        uint32_t reference_div = 0;
+        uint32_t post_divider = 0;
+        uint32_t freq = 0;
+        uint8_t pll_gain;
+        int pll_flags = RADEON_PLL_LEGACY;
+        bool use_bios_divs = false;
+        /* PLL registers */
+        uint32_t pll_ref_div = 0;
+        uint32_t pll_fb_post_div = 0;
+        uint32_t htotal_cntl = 0;
+
+        struct radeon_pll *pll;
+
+        struct {
+                int divider;
+                int bitvalue;
+        } *post_div, post_divs[]   = {
+                /* From RAGE 128 VR/RAGE 128 GL Register
+                 * Reference Manual (Technical Reference
+                 * Manual P/N RRG-G04100-C Rev. 0.04), page
+                 * 3-17 (PLL_DIV_[3:0]).
+                 */
+                {  1, 0 },              /* VCLK_SRC                 */
+                {  2, 1 },              /* VCLK_SRC/2               */
+                {  4, 2 },              /* VCLK_SRC/4               */
+                {  8, 3 },              /* VCLK_SRC/8               */
+                {  3, 4 },              /* VCLK_SRC/3               */
+                { 16, 5 },              /* VCLK_SRC/16              */
+                {  6, 6 },              /* VCLK_SRC/6               */
+                { 12, 7 },              /* VCLK_SRC/12              */
+                {  0, 0 }
+        };
+
+        if (radeon_crtc->crtc_id)
+                pll = &rdev->clock.p2pll;
+        else
+                pll = &rdev->clock.p1pll;
+
+        if (mode->clock > 200000) /* range limits??? */
+                pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
+        else
+                pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
+
+        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                if (encoder->crtc == crtc) {
+                        if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
+                                pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
+                        if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
+                                struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+                                struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
+                                if (lvds) {
+                                        if (lvds->use_bios_dividers) {
+                                                pll_ref_div = lvds->panel_ref_divider;
+                                                pll_fb_post_div   = (lvds->panel_fb_divider |
+                                                                     (lvds->panel_post_divider << 16));
+                                                htotal_cntl  = 0;
+                                                use_bios_divs = true;
+                                        }
+                                }
+                                pll_flags |= RADEON_PLL_USE_REF_DIV;
+                        }
+                }
+        }
+
+        DRM_DEBUG("\n");
+
+        if (!use_bios_divs) {
+                radeon_compute_pll(pll, mode->clock,
+                                   &freq, &feedback_div, &frac_fb_div,
+                                   &reference_div, &post_divider,
+                                   pll_flags);
+
+                for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
+                        if (post_div->divider == post_divider)
+                                break;
+                }
+
+                if (!post_div->divider)
+                        post_div = &post_divs[0];
+
+                DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
+                          (unsigned)freq,
+                          feedback_div,
+                          reference_div,
+                          post_divider);
+
+                pll_ref_div   = reference_div;
+#if defined(__powerpc__) && (0) /* TODO */
+                /* apparently programming this otherwise causes a hang??? */
+                if (info->MacModel == RADEON_MAC_IBOOK)
+                        pll_fb_post_div = 0x000600ad;
+                else
+#endif
+                        pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
+
+                htotal_cntl    = mode->htotal & 0x7;
+
+        }
+
+        pll_gain = radeon_compute_pll_gain(pll->reference_freq,
+                                           pll_ref_div & 0x3ff,
+                                           pll_fb_post_div & 0x7ff);
+
+        if (radeon_crtc->crtc_id) {
+                uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
+                                          ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
+                                         RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
+
+                WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
+                             RADEON_PIX2CLK_SRC_SEL_CPUCLK,
+                             ~(RADEON_PIX2CLK_SRC_SEL_MASK));
+
+                WREG32_PLL_P(RADEON_P2PLL_CNTL,
+                             RADEON_P2PLL_RESET
+                             | RADEON_P2PLL_ATOMIC_UPDATE_EN
+                             | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
+                             ~(RADEON_P2PLL_RESET
+                               | RADEON_P2PLL_ATOMIC_UPDATE_EN
+                               | RADEON_P2PLL_PVG_MASK));
+
+                WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
+                             pll_ref_div,
+                             ~RADEON_P2PLL_REF_DIV_MASK);
+
+                WREG32_PLL_P(RADEON_P2PLL_DIV_0,
+                             pll_fb_post_div,
+                             ~RADEON_P2PLL_FB0_DIV_MASK);
+
+                WREG32_PLL_P(RADEON_P2PLL_DIV_0,
+                             pll_fb_post_div,
+                             ~RADEON_P2PLL_POST0_DIV_MASK);
+
+                radeon_pll2_write_update(dev);
+                radeon_pll2_wait_for_read_update_complete(dev);
+
+                WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
+
+                WREG32_PLL_P(RADEON_P2PLL_CNTL,
+                             0,
+                             ~(RADEON_P2PLL_RESET
+                               | RADEON_P2PLL_SLEEP
+                               | RADEON_P2PLL_ATOMIC_UPDATE_EN));
+
+                DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
+                          (unsigned)pll_ref_div,
+                          (unsigned)pll_fb_post_div,
+                          (unsigned)htotal_cntl,
+                          RREG32_PLL(RADEON_P2PLL_CNTL));
+                DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
+                          (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
+                          (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
+                          (unsigned)((pll_fb_post_div &
+                                      RADEON_P2PLL_POST0_DIV_MASK) >> 16));
+
+                mdelay(50); /* Let the clock to lock */
+
+                WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
+                             RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
+                             ~(RADEON_PIX2CLK_SRC_SEL_MASK));
+
+                WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
+        } else {
+                if (rdev->flags & RADEON_IS_MOBILITY) {
+                        /* A temporal workaround for the occational blanking on certain laptop panels.
+                           This appears to related to the PLL divider registers (fail to lock?).
+                           It occurs even when all dividers are the same with their old settings.
+                           In this case we really don't need to fiddle with PLL registers.
+                           By doing this we can avoid the blanking problem with some panels.
+                        */
+                        if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
+                            (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
+                                                 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
+                                WREG32_P(RADEON_CLOCK_CNTL_INDEX,
+                                         RADEON_PLL_DIV_SEL,
+                                         ~(RADEON_PLL_DIV_SEL));
+                                r100_pll_errata_after_index(rdev);
+                                return;
+                        }
+                }
+
+                WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
+                             RADEON_VCLK_SRC_SEL_CPUCLK,
+                             ~(RADEON_VCLK_SRC_SEL_MASK));
+                WREG32_PLL_P(RADEON_PPLL_CNTL,
+                             RADEON_PPLL_RESET
+                             | RADEON_PPLL_ATOMIC_UPDATE_EN
+                             | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
+                             | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
+                             ~(RADEON_PPLL_RESET
+                               | RADEON_PPLL_ATOMIC_UPDATE_EN
+                               | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
+                               | RADEON_PPLL_PVG_MASK));
+
+                WREG32_P(RADEON_CLOCK_CNTL_INDEX,
+                         RADEON_PLL_DIV_SEL,
+                         ~(RADEON_PLL_DIV_SEL));
+                r100_pll_errata_after_index(rdev);
+
+                if (ASIC_IS_R300(rdev) ||
+                    (rdev->family == CHIP_RS300) ||
+                    (rdev->family == CHIP_RS400) ||
+                    (rdev->family == CHIP_RS480)) {
+                        if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
+                                /* When restoring console mode, use saved PPLL_REF_DIV
+                                 * setting.
+                                 */
+                                WREG32_PLL_P(RADEON_PPLL_REF_DIV,
+                                             pll_ref_div,
+                                             0);
+                        } else {
+                                /* R300 uses ref_div_acc field as real ref divider */
+                                WREG32_PLL_P(RADEON_PPLL_REF_DIV,
+                                             (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
+                                             ~R300_PPLL_REF_DIV_ACC_MASK);
+                        }
+                } else
+                        WREG32_PLL_P(RADEON_PPLL_REF_DIV,
+                                     pll_ref_div,
+                                     ~RADEON_PPLL_REF_DIV_MASK);
+
+                WREG32_PLL_P(RADEON_PPLL_DIV_3,
+                             pll_fb_post_div,
+                             ~RADEON_PPLL_FB3_DIV_MASK);
+
+                WREG32_PLL_P(RADEON_PPLL_DIV_3,
+                             pll_fb_post_div,
+                             ~RADEON_PPLL_POST3_DIV_MASK);
+
+                radeon_pll_write_update(dev);
+                radeon_pll_wait_for_read_update_complete(dev);
+
+                WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
+
+                WREG32_PLL_P(RADEON_PPLL_CNTL,
+                             0,
+                             ~(RADEON_PPLL_RESET
+                               | RADEON_PPLL_SLEEP
+                               | RADEON_PPLL_ATOMIC_UPDATE_EN
+                               | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
+
+                DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
+                          pll_ref_div,
+                          pll_fb_post_div,
+                          (unsigned)htotal_cntl,
+                          RREG32_PLL(RADEON_PPLL_CNTL));
+                DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
+                          pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
+                          pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
+                          (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
+
+                mdelay(50); /* Let the clock to lock */
+
+                WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
+                             RADEON_VCLK_SRC_SEL_PPLLCLK,
+                             ~(RADEON_VCLK_SRC_SEL_MASK));
+
+        }
+}
+
+static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
+                                   struct drm_display_mode *mode,
+                                   struct drm_display_mode *adjusted_mode)
+{
+        return true;
+}
+
+static int radeon_crtc_mode_set(struct drm_crtc *crtc,
+                                 struct drm_display_mode *mode,
+                                 struct drm_display_mode *adjusted_mode,
+                                 int x, int y, struct drm_framebuffer *old_fb)
+{
+
+        DRM_DEBUG("\n");
+
+        /* TODO TV */
+
+        radeon_crtc_set_base(crtc, x, y, old_fb);
+        radeon_set_crtc_timing(crtc, adjusted_mode);
+        radeon_set_pll(crtc, adjusted_mode);
+        radeon_init_disp_bandwidth(crtc->dev);
+
+        return 0;
+}
+
+static void radeon_crtc_prepare(struct drm_crtc *crtc)
+{
+        radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_crtc_commit(struct drm_crtc *crtc)
+{
+        radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
+}
+
+static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
+        .dpms = radeon_crtc_dpms,
+        .mode_fixup = radeon_crtc_mode_fixup,
+        .mode_set = radeon_crtc_mode_set,
+        .mode_set_base = radeon_crtc_set_base,
+        .prepare = radeon_crtc_prepare,
+        .commit = radeon_crtc_commit,
+};
+
+
+void radeon_legacy_init_crtc(struct drm_device *dev,
+                               struct radeon_crtc *radeon_crtc)
+{
+        if (radeon_crtc->crtc_id == 1)
+                radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
+        drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
+}
+
+void radeon_init_disp_bw_legacy(struct drm_device *dev,
+                                struct drm_display_mode *mode1,
+                                uint32_t pixel_bytes1,
+                                struct drm_display_mode *mode2,
+                                uint32_t pixel_bytes2)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
+        fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
+        fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
+        uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
+        fixed20_12 memtcas_ff[8] = {
+                fixed_init(1),
+                fixed_init(2),
+                fixed_init(3),
+                fixed_init(0),
+                fixed_init_half(1),
+                fixed_init_half(2),
+                fixed_init(0),
+        };
+        fixed20_12 memtcas_rs480_ff[8] = {
+                fixed_init(0),
+                fixed_init(1),
+                fixed_init(2),
+                fixed_init(3),
+                fixed_init(0),
+                fixed_init_half(1),
+                fixed_init_half(2),
+                fixed_init_half(3),
+        };
+        fixed20_12 memtcas2_ff[8] = {
+                fixed_init(0),
+                fixed_init(1),
+                fixed_init(2),
+                fixed_init(3),
+                fixed_init(4),
+                fixed_init(5),
+                fixed_init(6),
+                fixed_init(7),
+        };
+        fixed20_12 memtrbs[8] = {
+                fixed_init(1),
+                fixed_init_half(1),
+                fixed_init(2),
+                fixed_init_half(2),
+                fixed_init(3),
+                fixed_init_half(3),
+                fixed_init(4),
+                fixed_init_half(4)
+        };
+        fixed20_12 memtrbs_r4xx[8] = {
+                fixed_init(4),
+                fixed_init(5),
+                fixed_init(6),
+                fixed_init(7),
+                fixed_init(8),
+                fixed_init(9),
+                fixed_init(10),
+                fixed_init(11)
+        };
+        fixed20_12 min_mem_eff;
+        fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
+        fixed20_12 cur_latency_mclk, cur_latency_sclk;
+        fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
+                disp_drain_rate2, read_return_rate;
+        fixed20_12 time_disp1_drop_priority;
+        int c;
+        int cur_size = 16;       /* in octawords */
+        int critical_point = 0, critical_point2;
+/*      uint32_t read_return_rate, time_disp1_drop_priority; */
+        int stop_req, max_stop_req;
+
+        min_mem_eff.full = rfixed_const_8(0);
+        /* get modes */
+        if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
+                uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
+                mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
+                mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
+                /* check crtc enables */
+                if (mode2)
+                        mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
+                if (mode1)
+                        mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
+                WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
+        }
+
+        /*
+         * determine is there is enough bw for current mode
+         */
+        mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
+        temp_ff.full = rfixed_const(100);
+        mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
+        sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
+        sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
+
+        temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
+        temp_ff.full = rfixed_const(temp);
+        mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
+
+        pix_clk.full = 0;
+        pix_clk2.full = 0;
+        peak_disp_bw.full = 0;
+        if (mode1) {
+                temp_ff.full = rfixed_const(1000);
+                pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
+                pix_clk.full = rfixed_div(pix_clk, temp_ff);
+                temp_ff.full = rfixed_const(pixel_bytes1);
+                peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
+        }
+        if (mode2) {
+                temp_ff.full = rfixed_const(1000);
+                pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
+                pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
+                temp_ff.full = rfixed_const(pixel_bytes2);
+                peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
+        }
+
+        mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
+        if (peak_disp_bw.full >= mem_bw.full) {
+                DRM_ERROR("You may not have enough display bandwidth for current mode\n"
+                          "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
+        }
+
+        /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
+        temp = RREG32(RADEON_MEM_TIMING_CNTL);
+        if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
+                mem_trcd = ((temp >> 2) & 0x3) + 1;
+                mem_trp  = ((temp & 0x3)) + 1;
+                mem_tras = ((temp & 0x70) >> 4) + 1;
+        } else if (rdev->family == CHIP_R300 ||
+                   rdev->family == CHIP_R350) { /* r300, r350 */
+                mem_trcd = (temp & 0x7) + 1;
+                mem_trp = ((temp >> 8) & 0x7) + 1;
+                mem_tras = ((temp >> 11) & 0xf) + 4;
+        } else if (rdev->family == CHIP_RV350 ||
+                   rdev->family <= CHIP_RV380) {
+                /* rv3x0 */
+                mem_trcd = (temp & 0x7) + 3;
+                mem_trp = ((temp >> 8) & 0x7) + 3;
+                mem_tras = ((temp >> 11) & 0xf) + 6;
+        } else if (rdev->family == CHIP_R420 ||
+                   rdev->family == CHIP_R423 ||
+                   rdev->family == CHIP_RV410) {
+                /* r4xx */
+                mem_trcd = (temp & 0xf) + 3;
+                if (mem_trcd > 15)
+                        mem_trcd = 15;
+                mem_trp = ((temp >> 8) & 0xf) + 3;
+                if (mem_trp > 15)
+                        mem_trp = 15;
+                mem_tras = ((temp >> 12) & 0x1f) + 6;
+                if (mem_tras > 31)
+                        mem_tras = 31;
+        } else { /* RV200, R200 */
+                mem_trcd = (temp & 0x7) + 1;
+                mem_trp = ((temp >> 8) & 0x7) + 1;
+                mem_tras = ((temp >> 12) & 0xf) + 4;
+        }
+        /* convert to FF */
+        trcd_ff.full = rfixed_const(mem_trcd);
+        trp_ff.full = rfixed_const(mem_trp);
+        tras_ff.full = rfixed_const(mem_tras);
+
+        /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
+        temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
+        data = (temp & (7 << 20)) >> 20;
+        if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
+                if (rdev->family == CHIP_RS480) /* don't think rs400 */
+                        tcas_ff = memtcas_rs480_ff[data];
+                else
+                        tcas_ff = memtcas_ff[data];
+        } else
+                tcas_ff = memtcas2_ff[data];
+
+        if (rdev->family == CHIP_RS400 ||
+            rdev->family == CHIP_RS480) {
+                /* extra cas latency stored in bits 23-25 0-4 clocks */
+                data = (temp >> 23) & 0x7;
+                if (data < 5)
+                        tcas_ff.full += rfixed_const(data);
+        }
+
+        if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
+                /* on the R300, Tcas is included in Trbs.
+                 */
+                temp = RREG32(RADEON_MEM_CNTL);
+                data = (R300_MEM_NUM_CHANNELS_MASK & temp);
+                if (data == 1) {
+                        if (R300_MEM_USE_CD_CH_ONLY & temp) {
+                                temp = RREG32(R300_MC_IND_INDEX);
+                                temp &= ~R300_MC_IND_ADDR_MASK;
+                                temp |= R300_MC_READ_CNTL_CD_mcind;
+                                WREG32(R300_MC_IND_INDEX, temp);
+                                temp = RREG32(R300_MC_IND_DATA);
+                                data = (R300_MEM_RBS_POSITION_C_MASK & temp);
+                        } else {
+                                temp = RREG32(R300_MC_READ_CNTL_AB);
+                                data = (R300_MEM_RBS_POSITION_A_MASK & temp);
+                        }
+                } else {
+                        temp = RREG32(R300_MC_READ_CNTL_AB);
+                        data = (R300_MEM_RBS_POSITION_A_MASK & temp);
+                }
+                if (rdev->family == CHIP_RV410 ||
+                    rdev->family == CHIP_R420 ||
+                    rdev->family == CHIP_R423)
+                        trbs_ff = memtrbs_r4xx[data];
+                else
+                        trbs_ff = memtrbs[data];
+                tcas_ff.full += trbs_ff.full;
+        }
+
+        sclk_eff_ff.full = sclk_ff.full;
+
+        if (rdev->flags & RADEON_IS_AGP) {
+                fixed20_12 agpmode_ff;
+                agpmode_ff.full = rfixed_const(radeon_agpmode);
+                temp_ff.full = rfixed_const_666(16);
+                sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
+        }
+        /* TODO PCIE lanes may affect this - agpmode == 16?? */
+
+        if (ASIC_IS_R300(rdev)) {
+                sclk_delay_ff.full = rfixed_const(250);
+        } else {
+                if ((rdev->family == CHIP_RV100) ||
+                    rdev->flags & RADEON_IS_IGP) {
+                        if (rdev->mc.vram_is_ddr)
+                                sclk_delay_ff.full = rfixed_const(41);
+                        else
+                                sclk_delay_ff.full = rfixed_const(33);
+                } else {
+                        if (rdev->mc.vram_width == 128)
+                                sclk_delay_ff.full = rfixed_const(57);
+                        else
+                                sclk_delay_ff.full = rfixed_const(41);
+                }
+        }
+
+        mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
+
+        if (rdev->mc.vram_is_ddr) {
+                if (rdev->mc.vram_width == 32) {
+                        k1.full = rfixed_const(40);
+                        c  = 3;
+                } else {
+                        k1.full = rfixed_const(20);
+                        c  = 1;
+                }
+        } else {
+                k1.full = rfixed_const(40);
+                c  = 3;
+        }
+
+        temp_ff.full = rfixed_const(2);
+        mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
+        temp_ff.full = rfixed_const(c);
+        mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
+        temp_ff.full = rfixed_const(4);
+        mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
+        mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
+        mc_latency_mclk.full += k1.full;
+
+        mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
+        mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
+
+        /*
+          HW cursor time assuming worst case of full size colour cursor.
+        */
+        temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
+        temp_ff.full += trcd_ff.full;
+        if (temp_ff.full < tras_ff.full)
+                temp_ff.full = tras_ff.full;
+        cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
+
+        temp_ff.full = rfixed_const(cur_size);
+        cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
+        /*
+          Find the total latency for the display data.
+        */
+        disp_latency_overhead.full = rfixed_const(80);
+        disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
+        mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
+        mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
+
+        if (mc_latency_mclk.full > mc_latency_sclk.full)
+                disp_latency.full = mc_latency_mclk.full;
+        else
+                disp_latency.full = mc_latency_sclk.full;
+
+        /* setup Max GRPH_STOP_REQ default value */
+        if (ASIC_IS_RV100(rdev))
+                max_stop_req = 0x5c;
+        else
+                max_stop_req = 0x7c;
+
+        if (mode1) {
+                /*  CRTC1
+                    Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
+                    GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
+                */
+                stop_req = mode1->hdisplay * pixel_bytes1 / 16;
+
+                if (stop_req > max_stop_req)
+                        stop_req = max_stop_req;
+
+                /*
+                  Find the drain rate of the display buffer.
+                */
+                temp_ff.full = rfixed_const((16/pixel_bytes1));
+                disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
+
+                /*
+                  Find the critical point of the display buffer.
+                */
+                crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
+                crit_point_ff.full += rfixed_const_half(0);
+
+                critical_point = rfixed_trunc(crit_point_ff);
+
+                if (rdev->disp_priority == 2) {
+                        critical_point = 0;
+                }
+
+                /*
+                  The critical point should never be above max_stop_req-4.  Setting
+                  GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
+                */
+                if (max_stop_req - critical_point < 4)
+                        critical_point = 0;
+
+                if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
+                        /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
+                        critical_point = 0x10;
+                }
+
+                temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
+                temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
+                temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
+                temp &= ~(RADEON_GRPH_START_REQ_MASK);
+                if ((rdev->family == CHIP_R350) &&
+                    (stop_req > 0x15)) {
+                        stop_req -= 0x10;
+                }
+                temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
+                temp |= RADEON_GRPH_BUFFER_SIZE;
+                temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
+                          RADEON_GRPH_CRITICAL_AT_SOF |
+                          RADEON_GRPH_STOP_CNTL);
+                /*
+                  Write the result into the register.
+                */
+                WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
+                                                       (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
+
+#if 0
+                if ((rdev->family == CHIP_RS400) ||
+                    (rdev->family == CHIP_RS480)) {
+                        /* attempt to program RS400 disp regs correctly ??? */
+                        temp = RREG32(RS400_DISP1_REG_CNTL);
+                        temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
+                                  RS400_DISP1_STOP_REQ_LEVEL_MASK);
+                        WREG32(RS400_DISP1_REQ_CNTL1, (temp |
+                                                       (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
+                                                       (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
+                        temp = RREG32(RS400_DMIF_MEM_CNTL1);
+                        temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
+                                  RS400_DISP1_CRITICAL_POINT_STOP_MASK);
+                        WREG32(RS400_DMIF_MEM_CNTL1, (temp |
+                                                      (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
+                                                      (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
+                }
+#endif
+
+                DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
+                          /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
+                          (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
+        }
+
+        if (mode2) {
+                u32 grph2_cntl;
+                stop_req = mode2->hdisplay * pixel_bytes2 / 16;
+
+                if (stop_req > max_stop_req)
+                        stop_req = max_stop_req;
+
+                /*
+                  Find the drain rate of the display buffer.
+                */
+                temp_ff.full = rfixed_const((16/pixel_bytes2));
+                disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
+
+                grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
+                grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
+                grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
+                grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
+                if ((rdev->family == CHIP_R350) &&
+                    (stop_req > 0x15)) {
+                        stop_req -= 0x10;
+                }
+                grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
+                grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
+                grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
+                          RADEON_GRPH_CRITICAL_AT_SOF |
+                          RADEON_GRPH_STOP_CNTL);
+
+                if ((rdev->family == CHIP_RS100) ||
+                    (rdev->family == CHIP_RS200))
+                        critical_point2 = 0;
+                else {
+                        temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
+                        temp_ff.full = rfixed_const(temp);
+                        temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
+                        if (sclk_ff.full < temp_ff.full)
+                                temp_ff.full = sclk_ff.full;
+
+                        read_return_rate.full = temp_ff.full;
+
+                        if (mode1) {
+                                temp_ff.full = read_return_rate.full - disp_drain_rate.full;
+                                time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
+                        } else {
+                                time_disp1_drop_priority.full = 0;
+                        }
+                        crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
+                        crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
+                        crit_point_ff.full += rfixed_const_half(0);
+
+                        critical_point2 = rfixed_trunc(crit_point_ff);
+
+                        if (rdev->disp_priority == 2) {
+                                critical_point2 = 0;
+                        }
+
+                        if (max_stop_req - critical_point2 < 4)
+                                critical_point2 = 0;
+
+                }
+
+                if (critical_point2 == 0 && rdev->family == CHIP_R300) {
+                        /* some R300 cards have problem with this set to 0 */
+                        critical_point2 = 0x10;
+                }
+
+                WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
+                                                  (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
+
+                if ((rdev->family == CHIP_RS400) ||
+                    (rdev->family == CHIP_RS480)) {
+#if 0
+                        /* attempt to program RS400 disp2 regs correctly ??? */
+                        temp = RREG32(RS400_DISP2_REQ_CNTL1);
+                        temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
+                                  RS400_DISP2_STOP_REQ_LEVEL_MASK);
+                        WREG32(RS400_DISP2_REQ_CNTL1, (temp |
+                                                       (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
+                                                       (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
+                        temp = RREG32(RS400_DISP2_REQ_CNTL2);
+                        temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
+                                  RS400_DISP2_CRITICAL_POINT_STOP_MASK);
+                        WREG32(RS400_DISP2_REQ_CNTL2, (temp |
+                                                       (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
+                                                       (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
+#endif
+                        WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
+                        WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
+                        WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
+                        WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
+                }
+
+                DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
+                          (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
+        }
+}
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
new file mode 100644
index 000000000000..2c2f42de1d4c
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -0,0 +1,1288 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ */
+#include "drmP.h"
+#include "drm_crtc_helper.h"
+#include "radeon_drm.h"
+#include "radeon.h"
+#include "atom.h"
+
+
+static void radeon_legacy_rmx_mode_set(struct drm_encoder *encoder,
+                                       struct drm_display_mode *mode,
+                                       struct drm_display_mode *adjusted_mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        int    xres = mode->hdisplay;
+        int    yres = mode->vdisplay;
+        bool   hscale = true, vscale = true;
+        int    hsync_wid;
+        int    vsync_wid;
+        int    hsync_start;
+        uint32_t scale, inc;
+        uint32_t fp_horz_stretch, fp_vert_stretch, crtc_more_cntl, fp_horz_vert_active;
+        uint32_t fp_h_sync_strt_wid, fp_v_sync_strt_wid, fp_crtc_h_total_disp, fp_crtc_v_total_disp;
+        struct radeon_native_mode *native_mode = &radeon_encoder->native_mode;
+
+        DRM_DEBUG("\n");
+
+        fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
+                (RADEON_VERT_STRETCH_RESERVED |
+                 RADEON_VERT_AUTO_RATIO_INC);
+        fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
+                (RADEON_HORZ_FP_LOOP_STRETCH |
+                 RADEON_HORZ_AUTO_RATIO_INC);
+
+        crtc_more_cntl = 0;
+        if ((rdev->family == CHIP_RS100) ||
+            (rdev->family == CHIP_RS200)) {
+                /* This is to workaround the asic bug for RMX, some versions
+                   of BIOS dosen't have this register initialized correctly. */
+                crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
+        }
+
+
+        fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
+                                | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
+
+        hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
+        if (!hsync_wid)
+                hsync_wid = 1;
+        hsync_start = mode->crtc_hsync_start - 8;
+
+        fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
+                              | ((hsync_wid & 0x3f) << 16)
+                              | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
+                                 ? RADEON_CRTC_H_SYNC_POL
+                                 : 0));
+
+        fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
+                                | ((mode->crtc_vdisplay - 1) << 16));
+
+        vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
+        if (!vsync_wid)
+                vsync_wid = 1;
+
+        fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
+                              | ((vsync_wid & 0x1f) << 16)
+                              | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
+                                 ? RADEON_CRTC_V_SYNC_POL
+                                 : 0));
+
+        fp_horz_vert_active = 0;
+
+        if (native_mode->panel_xres == 0 ||
+            native_mode->panel_yres == 0) {
+                hscale = false;
+                vscale = false;
+        } else {
+                if (xres > native_mode->panel_xres)
+                        xres = native_mode->panel_xres;
+                if (yres > native_mode->panel_yres)
+                        yres = native_mode->panel_yres;
+
+                if (xres == native_mode->panel_xres)
+                        hscale = false;
+                if (yres == native_mode->panel_yres)
+                        vscale = false;
+        }
+
+        if (radeon_encoder->flags & RADEON_USE_RMX) {
+                if (radeon_encoder->rmx_type != RMX_CENTER) {
+                        if (!hscale)
+                                fp_horz_stretch |= ((xres/8-1) << 16);
+                        else {
+                                inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
+                                scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
+                                        / native_mode->panel_xres + 1;
+                                fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
+                                                    RADEON_HORZ_STRETCH_BLEND |
+                                                    RADEON_HORZ_STRETCH_ENABLE |
+                                                    ((native_mode->panel_xres/8-1) << 16));
+                        }
+
+                        if (!vscale)
+                                fp_vert_stretch |= ((yres-1) << 12);
+                        else {
+                                inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
+                                scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
+                                        / native_mode->panel_yres + 1;
+                                fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
+                                                    RADEON_VERT_STRETCH_ENABLE |
+                                                    RADEON_VERT_STRETCH_BLEND |
+                                                    ((native_mode->panel_yres-1) << 12));
+                        }
+                } else if (radeon_encoder->rmx_type == RMX_CENTER) {
+                        int    blank_width;
+
+                        fp_horz_stretch |= ((xres/8-1) << 16);
+                        fp_vert_stretch |= ((yres-1) << 12);
+
+                        crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
+                                           RADEON_CRTC_AUTO_VERT_CENTER_EN);
+
+                        blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
+                        if (blank_width > 110)
+                                blank_width = 110;
+
+                        fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
+                                                | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
+
+                        hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
+                        if (!hsync_wid)
+                                hsync_wid = 1;
+
+                        fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
+                                              | ((hsync_wid & 0x3f) << 16)
+                                              | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
+                                                 ? RADEON_CRTC_H_SYNC_POL
+                                                 : 0));
+
+                        fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
+                                                | ((mode->crtc_vdisplay - 1) << 16));
+
+                        vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
+                        if (!vsync_wid)
+                                vsync_wid = 1;
+
+                        fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
+                                               | ((vsync_wid & 0x1f) << 16)
+                                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
+                                                  ? RADEON_CRTC_V_SYNC_POL
+                                                  : 0)));
+
+                        fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) |
+                                               (((native_mode->panel_xres / 8) & 0x1ff) << 16));
+                }
+        } else {
+                fp_horz_stretch |= ((xres/8-1) << 16);
+                fp_vert_stretch |= ((yres-1) << 12);
+        }
+
+        WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
+        WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
+        WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
+        WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
+        WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
+        WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
+        WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
+        WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
+
+}
+
+static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
+        int panel_pwr_delay = 2000;
+        DRM_DEBUG("\n");
+
+        if (radeon_encoder->enc_priv) {
+                if (rdev->is_atom_bios) {
+                        struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
+                        panel_pwr_delay = lvds->panel_pwr_delay;
+                } else {
+                        struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
+                        panel_pwr_delay = lvds->panel_pwr_delay;
+                }
+        }
+
+        switch (mode) {
+        case DRM_MODE_DPMS_ON:
+                disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
+                disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
+                WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
+                lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
+                lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
+                WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
+                udelay(1000);
+
+                lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
+                lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
+                WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
+
+                lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
+                lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
+                lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
+                udelay(panel_pwr_delay * 1000);
+                WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+                break;
+        case DRM_MODE_DPMS_STANDBY:
+        case DRM_MODE_DPMS_SUSPEND:
+        case DRM_MODE_DPMS_OFF:
+                pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
+                WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+                lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
+                lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+                lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
+                udelay(panel_pwr_delay * 1000);
+                WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+                WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
+                break;
+        }
+
+        if (rdev->is_atom_bios)
+                radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
+        else
+                radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
+}
+
+static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
+{
+        struct radeon_device *rdev = encoder->dev->dev_private;
+
+        if (rdev->is_atom_bios)
+                radeon_atom_output_lock(encoder, true);
+        else
+                radeon_combios_output_lock(encoder, true);
+        radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
+{
+        struct radeon_device *rdev = encoder->dev->dev_private;
+
+        radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
+        if (rdev->is_atom_bios)
+                radeon_atom_output_lock(encoder, false);
+        else
+                radeon_combios_output_lock(encoder, false);
+}
+
+static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
+                                        struct drm_display_mode *mode,
+                                        struct drm_display_mode *adjusted_mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
+
+        DRM_DEBUG("\n");
+
+        if (radeon_crtc->crtc_id == 0)
+                radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
+
+        lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
+        lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
+
+        lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
+        if ((!rdev->is_atom_bios)) {
+                struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
+                if (lvds) {
+                        DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
+                        lvds_gen_cntl = lvds->lvds_gen_cntl;
+                        lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
+                                              (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
+                        lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
+                                             (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
+                } else
+                        lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
+        } else
+                lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
+        lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
+        lvds_gen_cntl &= ~(RADEON_LVDS_ON |
+                           RADEON_LVDS_BLON |
+                           RADEON_LVDS_EN |
+                           RADEON_LVDS_RST_FM);
+
+        if (ASIC_IS_R300(rdev))
+                lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
+
+        if (radeon_crtc->crtc_id == 0) {
+                if (ASIC_IS_R300(rdev)) {
+                        if (radeon_encoder->flags & RADEON_USE_RMX)
+                                lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
+                } else
+                        lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
+        } else {
+                if (ASIC_IS_R300(rdev))
+                        lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
+                else
+                        lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
+        }
+
+        WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
+        WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
+        WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
+
+        if (rdev->family == CHIP_RV410)
+                WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
+
+        if (rdev->is_atom_bios)
+                radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
+        else
+                radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
+}
+
+static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
+                                          struct drm_display_mode *mode,
+                                          struct drm_display_mode *adjusted_mode)
+{
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+
+        drm_mode_set_crtcinfo(adjusted_mode, 0);
+
+        radeon_encoder->flags &= ~RADEON_USE_RMX;
+
+        if (radeon_encoder->rmx_type != RMX_OFF)
+                radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
+
+        return true;
+}
+
+static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
+        .dpms = radeon_legacy_lvds_dpms,
+        .mode_fixup = radeon_legacy_lvds_mode_fixup,
+        .prepare = radeon_legacy_lvds_prepare,
+        .mode_set = radeon_legacy_lvds_mode_set,
+        .commit = radeon_legacy_lvds_commit,
+};
+
+
+static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
+        .destroy = radeon_enc_destroy,
+};
+
+static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
+                                                 struct drm_display_mode *mode,
+                                                 struct drm_display_mode *adjusted_mode)
+{
+
+        drm_mode_set_crtcinfo(adjusted_mode, 0);
+
+        return true;
+}
+
+static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
+        uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
+        uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
+
+        DRM_DEBUG("\n");
+
+        switch (mode) {
+        case DRM_MODE_DPMS_ON:
+                crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
+                dac_cntl &= ~RADEON_DAC_PDWN;
+                dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
+                                    RADEON_DAC_PDWN_G |
+                                    RADEON_DAC_PDWN_B);
+                break;
+        case DRM_MODE_DPMS_STANDBY:
+        case DRM_MODE_DPMS_SUSPEND:
+        case DRM_MODE_DPMS_OFF:
+                crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
+                dac_cntl |= RADEON_DAC_PDWN;
+                dac_macro_cntl |= (RADEON_DAC_PDWN_R |
+                                   RADEON_DAC_PDWN_G |
+                                   RADEON_DAC_PDWN_B);
+                break;
+        }
+
+        WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
+        WREG32(RADEON_DAC_CNTL, dac_cntl);
+        WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
+
+        if (rdev->is_atom_bios)
+                radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
+        else
+                radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
+}
+
+static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
+{
+        struct radeon_device *rdev = encoder->dev->dev_private;
+
+        if (rdev->is_atom_bios)
+                radeon_atom_output_lock(encoder, true);
+        else
+                radeon_combios_output_lock(encoder, true);
+        radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
+{
+        struct radeon_device *rdev = encoder->dev->dev_private;
+
+        radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
+
+        if (rdev->is_atom_bios)
+                radeon_atom_output_lock(encoder, false);
+        else
+                radeon_combios_output_lock(encoder, false);
+}
+
+static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
+                                               struct drm_display_mode *mode,
+                                               struct drm_display_mode *adjusted_mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
+
+        DRM_DEBUG("\n");
+
+        if (radeon_crtc->crtc_id == 0)
+                radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
+
+        if (radeon_crtc->crtc_id == 0) {
+                if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
+                        disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
+                                ~(RADEON_DISP_DAC_SOURCE_MASK);
+                        WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
+                } else {
+                        dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
+                        WREG32(RADEON_DAC_CNTL2, dac2_cntl);
+                }
+        } else {
+                if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
+                        disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
+                                ~(RADEON_DISP_DAC_SOURCE_MASK);
+                        disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
+                        WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
+                } else {
+                        dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
+                        WREG32(RADEON_DAC_CNTL2, dac2_cntl);
+                }
+        }
+
+        dac_cntl = (RADEON_DAC_MASK_ALL |
+                    RADEON_DAC_VGA_ADR_EN |
+                    /* TODO 6-bits */
+                    RADEON_DAC_8BIT_EN);
+
+        WREG32_P(RADEON_DAC_CNTL,
+                       dac_cntl,
+                       RADEON_DAC_RANGE_CNTL |
+                       RADEON_DAC_BLANKING);
+
+        if (radeon_encoder->enc_priv) {
+                struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
+                dac_macro_cntl = p_dac->ps2_pdac_adj;
+        } else
+                dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
+        dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
+        WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
+
+        if (rdev->is_atom_bios)
+                radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
+        else
+                radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
+}
+
+static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
+                                                                  struct drm_connector *connector)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t vclk_ecp_cntl, crtc_ext_cntl;
+        uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
+        enum drm_connector_status found = connector_status_disconnected;
+        bool color = true;
+
+        /* save the regs we need */
+        vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
+        crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
+        dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
+        dac_cntl = RREG32(RADEON_DAC_CNTL);
+        dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
+
+        tmp = vclk_ecp_cntl &
+                ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
+        WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
+
+        tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
+        WREG32(RADEON_CRTC_EXT_CNTL, tmp);
+
+        tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
+                RADEON_DAC_FORCE_DATA_EN;
+
+        if (color)
+                tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
+        else
+                tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
+
+        if (ASIC_IS_R300(rdev))
+                tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
+        else
+                tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
+
+        WREG32(RADEON_DAC_EXT_CNTL, tmp);
+
+        tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
+        tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
+        WREG32(RADEON_DAC_CNTL, tmp);
+
+        tmp &= ~(RADEON_DAC_PDWN_R |
+                 RADEON_DAC_PDWN_G |
+                 RADEON_DAC_PDWN_B);
+
+        WREG32(RADEON_DAC_MACRO_CNTL, tmp);
+
+        udelay(2000);
+
+        if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
+                found = connector_status_connected;
+
+        /* restore the regs we used */
+        WREG32(RADEON_DAC_CNTL, dac_cntl);
+        WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
+        WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
+        WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
+        WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
+
+        return found;
+}
+
+static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
+        .dpms = radeon_legacy_primary_dac_dpms,
+        .mode_fixup = radeon_legacy_primary_dac_mode_fixup,
+        .prepare = radeon_legacy_primary_dac_prepare,
+        .mode_set = radeon_legacy_primary_dac_mode_set,
+        .commit = radeon_legacy_primary_dac_commit,
+        .detect = radeon_legacy_primary_dac_detect,
+};
+
+
+static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
+        .destroy = radeon_enc_destroy,
+};
+
+static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
+                                              struct drm_display_mode *mode,
+                                              struct drm_display_mode *adjusted_mode)
+{
+
+        drm_mode_set_crtcinfo(adjusted_mode, 0);
+
+        return true;
+}
+
+static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
+        DRM_DEBUG("\n");
+
+        switch (mode) {
+        case DRM_MODE_DPMS_ON:
+                fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+                break;
+        case DRM_MODE_DPMS_STANDBY:
+        case DRM_MODE_DPMS_SUSPEND:
+        case DRM_MODE_DPMS_OFF:
+                fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+                break;
+        }
+
+        WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
+
+        if (rdev->is_atom_bios)
+                radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
+        else
+                radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
+}
+
+static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
+{
+        struct radeon_device *rdev = encoder->dev->dev_private;
+
+        if (rdev->is_atom_bios)
+                radeon_atom_output_lock(encoder, true);
+        else
+                radeon_combios_output_lock(encoder, true);
+        radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
+{
+        struct radeon_device *rdev = encoder->dev->dev_private;
+
+        radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
+
+        if (rdev->is_atom_bios)
+                radeon_atom_output_lock(encoder, true);
+        else
+                radeon_combios_output_lock(encoder, true);
+}
+
+static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
+                                            struct drm_display_mode *mode,
+                                            struct drm_display_mode *adjusted_mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
+        int i;
+
+        DRM_DEBUG("\n");
+
+        if (radeon_crtc->crtc_id == 0)
+                radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
+
+        tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
+        tmp &= 0xfffff;
+        if (rdev->family == CHIP_RV280) {
+                /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
+                tmp ^= (1 << 22);
+                tmds_pll_cntl ^= (1 << 22);
+        }
+
+        if (radeon_encoder->enc_priv) {
+                struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
+
+                for (i = 0; i < 4; i++) {
+                        if (tmds->tmds_pll[i].freq == 0)
+                                break;
+                        if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
+                                tmp = tmds->tmds_pll[i].value ;
+                                break;
+                        }
+                }
+        }
+
+        if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
+                if (tmp & 0xfff00000)
+                        tmds_pll_cntl = tmp;
+                else {
+                        tmds_pll_cntl &= 0xfff00000;
+                        tmds_pll_cntl |= tmp;
+                }
+        } else
+                tmds_pll_cntl = tmp;
+
+        tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
+                ~(RADEON_TMDS_TRANSMITTER_PLLRST);
+
+    if (rdev->family == CHIP_R200 ||
+        rdev->family == CHIP_R100 ||
+        ASIC_IS_R300(rdev))
+            tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
+    else /* RV chips got this bit reversed */
+            tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
+
+    fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
+                   (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
+                    RADEON_FP_CRTC_DONT_SHADOW_HEND));
+
+    fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
+
+    if (1) /*  FIXME rgbBits == 8 */
+            fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
+    else
+            fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
+
+    if (radeon_crtc->crtc_id == 0) {
+            if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
+                    fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
+                    if (radeon_encoder->flags & RADEON_USE_RMX)
+                            fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
+                    else
+                            fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
+            } else
+                    fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
+    } else {
+            if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
+                    fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
+                    fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
+            } else
+                    fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
+    }
+
+    WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
+    WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
+    WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
+
+        if (rdev->is_atom_bios)
+                radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
+        else
+                radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
+}
+
+static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
+        .dpms = radeon_legacy_tmds_int_dpms,
+        .mode_fixup = radeon_legacy_tmds_int_mode_fixup,
+        .prepare = radeon_legacy_tmds_int_prepare,
+        .mode_set = radeon_legacy_tmds_int_mode_set,
+        .commit = radeon_legacy_tmds_int_commit,
+};
+
+
+static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
+        .destroy = radeon_enc_destroy,
+};
+
+static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
+                                              struct drm_display_mode *mode,
+                                              struct drm_display_mode *adjusted_mode)
+{
+
+        drm_mode_set_crtcinfo(adjusted_mode, 0);
+
+        return true;
+}
+
+static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
+        DRM_DEBUG("\n");
+
+        switch (mode) {
+        case DRM_MODE_DPMS_ON:
+                fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
+                fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+                break;
+        case DRM_MODE_DPMS_STANDBY:
+        case DRM_MODE_DPMS_SUSPEND:
+        case DRM_MODE_DPMS_OFF:
+                fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
+                fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+                break;
+        }
+
+        WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+
+        if (rdev->is_atom_bios)
+                radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
+        else
+                radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
+}
+
+static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
+{
+        struct radeon_device *rdev = encoder->dev->dev_private;
+
+        if (rdev->is_atom_bios)
+                radeon_atom_output_lock(encoder, true);
+        else
+                radeon_combios_output_lock(encoder, true);
+        radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
+{
+        struct radeon_device *rdev = encoder->dev->dev_private;
+        radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
+
+        if (rdev->is_atom_bios)
+                radeon_atom_output_lock(encoder, false);
+        else
+                radeon_combios_output_lock(encoder, false);
+}
+
+static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
+                                            struct drm_display_mode *mode,
+                                            struct drm_display_mode *adjusted_mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t fp2_gen_cntl;
+
+        DRM_DEBUG("\n");
+
+        if (radeon_crtc->crtc_id == 0)
+                radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
+
+        if (rdev->is_atom_bios) {
+                radeon_encoder->pixel_clock = adjusted_mode->clock;
+                atombios_external_tmds_setup(encoder, ATOM_ENABLE);
+                fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
+        } else {
+                fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
+
+                if (1) /*  FIXME rgbBits == 8 */
+                        fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
+                else
+                        fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
+
+                fp2_gen_cntl &= ~(RADEON_FP2_ON |
+                                  RADEON_FP2_DVO_EN |
+                                  RADEON_FP2_DVO_RATE_SEL_SDR);
+
+                /* XXX: these are oem specific */
+                if (ASIC_IS_R300(rdev)) {
+                        if ((dev->pdev->device == 0x4850) &&
+                            (dev->pdev->subsystem_vendor == 0x1028) &&
+                            (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
+                                fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
+                        else
+                                fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
+
+                        /*if (mode->clock > 165000)
+                          fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
+                }
+        }
+
+        if (radeon_crtc->crtc_id == 0) {
+                if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
+                        fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
+                        if (radeon_encoder->flags & RADEON_USE_RMX)
+                                fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
+                        else
+                                fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
+                } else
+                        fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
+        } else {
+                if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
+                        fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
+                        fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
+                } else
+                        fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
+        }
+
+        WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+
+        if (rdev->is_atom_bios)
+                radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
+        else
+                radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
+}
+
+static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
+        .dpms = radeon_legacy_tmds_ext_dpms,
+        .mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
+        .prepare = radeon_legacy_tmds_ext_prepare,
+        .mode_set = radeon_legacy_tmds_ext_mode_set,
+        .commit = radeon_legacy_tmds_ext_commit,
+};
+
+
+static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
+        .destroy = radeon_enc_destroy,
+};
+
+static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
+                                            struct drm_display_mode *mode,
+                                            struct drm_display_mode *adjusted_mode)
+{
+
+        drm_mode_set_crtcinfo(adjusted_mode, 0);
+
+        return true;
+}
+
+static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
+        /* uint32_t tv_master_cntl = 0; */
+
+        DRM_DEBUG("\n");
+
+        if (rdev->family == CHIP_R200)
+                fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
+        else {
+                crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
+                /*  FIXME TV */
+                /* tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); */
+                tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
+        }
+
+        switch (mode) {
+        case DRM_MODE_DPMS_ON:
+                if (rdev->family == CHIP_R200) {
+                        fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+                } else {
+                        crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
+                        /* tv_master_cntl |= RADEON_TV_ON; */
+                        if (rdev->family == CHIP_R420 ||
+                                        rdev->family == CHIP_R423 ||
+                                        rdev->family == CHIP_RV410)
+                                tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
+                                                R420_TV_DAC_GDACPD |
+                                                R420_TV_DAC_BDACPD |
+                                                RADEON_TV_DAC_BGSLEEP);
+                        else
+                                tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
+                                                RADEON_TV_DAC_GDACPD |
+                                                RADEON_TV_DAC_BDACPD |
+                                                RADEON_TV_DAC_BGSLEEP);
+                }
+                break;
+        case DRM_MODE_DPMS_STANDBY:
+        case DRM_MODE_DPMS_SUSPEND:
+        case DRM_MODE_DPMS_OFF:
+                if (rdev->family == CHIP_R200)
+                        fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
+                else {
+                        crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+                        /* tv_master_cntl &= ~RADEON_TV_ON; */
+                        if (rdev->family == CHIP_R420 ||
+                                        rdev->family == CHIP_R423 ||
+                                        rdev->family == CHIP_RV410)
+                                tv_dac_cntl |= (R420_TV_DAC_RDACPD |
+                                                R420_TV_DAC_GDACPD |
+                                                R420_TV_DAC_BDACPD |
+                                                RADEON_TV_DAC_BGSLEEP);
+                        else
+                                tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
+                                                RADEON_TV_DAC_GDACPD |
+                                                RADEON_TV_DAC_BDACPD |
+                                                RADEON_TV_DAC_BGSLEEP);
+                }
+                break;
+        }
+
+        if (rdev->family == CHIP_R200) {
+                WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+        } else {
+                WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+                /* WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); */
+                WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+        }
+
+        if (rdev->is_atom_bios)
+                radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
+        else
+                radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
+}
+
+static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
+{
+        struct radeon_device *rdev = encoder->dev->dev_private;
+
+        if (rdev->is_atom_bios)
+                radeon_atom_output_lock(encoder, true);
+        else
+                radeon_combios_output_lock(encoder, true);
+        radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
+}
+
+static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
+{
+        struct radeon_device *rdev = encoder->dev->dev_private;
+
+        radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
+
+        if (rdev->is_atom_bios)
+                radeon_atom_output_lock(encoder, true);
+        else
+                radeon_combios_output_lock(encoder, true);
+}
+
+static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
+                struct drm_display_mode *mode,
+                struct drm_display_mode *adjusted_mode)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
+        uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0;
+
+        DRM_DEBUG("\n");
+
+        if (radeon_crtc->crtc_id == 0)
+                radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
+
+        if (rdev->family != CHIP_R200) {
+                tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
+                if (rdev->family == CHIP_R420 ||
+                                rdev->family == CHIP_R423 ||
+                                rdev->family == CHIP_RV410) {
+                        tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
+                                        RADEON_TV_DAC_BGADJ_MASK |
+                                        R420_TV_DAC_DACADJ_MASK |
+                                        R420_TV_DAC_RDACPD |
+                                        R420_TV_DAC_GDACPD |
+                                        R420_TV_DAC_GDACPD |
+                                        R420_TV_DAC_TVENABLE);
+                } else {
+                        tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
+                                        RADEON_TV_DAC_BGADJ_MASK |
+                                        RADEON_TV_DAC_DACADJ_MASK |
+                                        RADEON_TV_DAC_RDACPD |
+                                        RADEON_TV_DAC_GDACPD |
+                                        RADEON_TV_DAC_GDACPD);
+                }
+
+                /*  FIXME TV */
+                if (radeon_encoder->enc_priv) {
+                        struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
+                        tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
+                                        RADEON_TV_DAC_NHOLD |
+                                        RADEON_TV_DAC_STD_PS2 |
+                                        tv_dac->ps2_tvdac_adj);
+                } else
+                        tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
+                                        RADEON_TV_DAC_NHOLD |
+                                        RADEON_TV_DAC_STD_PS2);
+
+                WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+        }
+
+        if (ASIC_IS_R300(rdev)) {
+                gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
+                disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
+        } else if (rdev->family == CHIP_R200)
+                fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
+        else
+                disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
+
+        dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
+
+        if (radeon_crtc->crtc_id == 0) {
+                if (ASIC_IS_R300(rdev)) {
+                        disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+                        disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
+                } else if (rdev->family == CHIP_R200) {
+                        fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+                                          RADEON_FP2_DVO_RATE_SEL_SDR);
+                } else
+                        disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
+        } else {
+                if (ASIC_IS_R300(rdev)) {
+                        disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
+                        disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
+                } else if (rdev->family == CHIP_R200) {
+                        fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
+                                          RADEON_FP2_DVO_RATE_SEL_SDR);
+                        fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
+                } else
+                        disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
+        }
+
+        WREG32(RADEON_DAC_CNTL2, dac2_cntl);
+
+        if (ASIC_IS_R300(rdev)) {
+                WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
+                WREG32(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl);
+        } else if (rdev->family == CHIP_R200)
+                WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
+        else
+                WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
+
+        if (rdev->is_atom_bios)
+                radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
+        else
+                radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
+
+}
+
+static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
+                                                             struct drm_connector *connector)
+{
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
+        uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
+        enum drm_connector_status found = connector_status_disconnected;
+        bool color = true;
+
+        /*  FIXME tv */
+
+        /* save the regs we need */
+        pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
+        gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
+        disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
+        disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
+        crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
+        tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
+        dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
+        dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
+
+        tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
+                               | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
+        WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
+
+        if (ASIC_IS_R300(rdev))
+                WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
+
+        tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
+        tmp |= RADEON_CRTC2_CRT2_ON |
+                (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
+
+        WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
+
+        if (ASIC_IS_R300(rdev)) {
+                tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
+                tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
+                WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
+        } else {
+                tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
+                WREG32(RADEON_DISP_HW_DEBUG, tmp);
+        }
+
+        tmp = RADEON_TV_DAC_NBLANK |
+                RADEON_TV_DAC_NHOLD |
+                RADEON_TV_MONITOR_DETECT_EN |
+                RADEON_TV_DAC_STD_PS2;
+
+        WREG32(RADEON_TV_DAC_CNTL, tmp);
+
+        tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
+                RADEON_DAC2_FORCE_DATA_EN;
+
+        if (color)
+                tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
+        else
+                tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
+
+        if (ASIC_IS_R300(rdev))
+                tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
+        else
+                tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
+
+        WREG32(RADEON_DAC_EXT_CNTL, tmp);
+
+        tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
+        WREG32(RADEON_DAC_CNTL2, tmp);
+
+        udelay(10000);
+
+        if (ASIC_IS_R300(rdev)) {
+                if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
+                        found = connector_status_connected;
+        } else {
+                if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
+                        found = connector_status_connected;
+        }
+
+        /* restore regs we used */
+        WREG32(RADEON_DAC_CNTL2, dac_cntl2);
+        WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
+        WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
+        WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
+
+        if (ASIC_IS_R300(rdev)) {
+                WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
+                WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
+        } else {
+                WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
+        }
+        WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
+
+        /* return found; */
+        return connector_status_disconnected;
+
+}
+
+static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
+        .dpms = radeon_legacy_tv_dac_dpms,
+        .mode_fixup = radeon_legacy_tv_dac_mode_fixup,
+        .prepare = radeon_legacy_tv_dac_prepare,
+        .mode_set = radeon_legacy_tv_dac_mode_set,
+        .commit = radeon_legacy_tv_dac_commit,
+        .detect = radeon_legacy_tv_dac_detect,
+};
+
+
+static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
+        .destroy = radeon_enc_destroy,
+};
+
+void
+radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
+{
+        struct radeon_device *rdev = dev->dev_private;
+        struct drm_encoder *encoder;
+        struct radeon_encoder *radeon_encoder;
+
+        /* see if we already added it */
+        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                radeon_encoder = to_radeon_encoder(encoder);
+                if (radeon_encoder->encoder_id == encoder_id) {
+                        radeon_encoder->devices |= supported_device;
+                        return;
+                }
+
+        }
+
+        /* add a new one */
+        radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
+        if (!radeon_encoder)
+                return;
+
+        encoder = &radeon_encoder->base;
+        encoder->possible_crtcs = 0x3;
+        encoder->possible_clones = 0;
+
+        radeon_encoder->enc_priv = NULL;
+
+        radeon_encoder->encoder_id = encoder_id;
+        radeon_encoder->devices = supported_device;
+
+        switch (radeon_encoder->encoder_id) {
+        case ENCODER_OBJECT_ID_INTERNAL_LVDS:
+                drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
+                drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
+                if (rdev->is_atom_bios)
+                        radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
+                else
+                        radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
+                radeon_encoder->rmx_type = RMX_FULL;
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
+                drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
+                drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
+                if (rdev->is_atom_bios)
+                        radeon_encoder->enc_priv = radeon_atombios_get_tmds_info(radeon_encoder);
+                else
+                        radeon_encoder->enc_priv = radeon_combios_get_tmds_info(radeon_encoder);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DAC1:
+                drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
+                drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
+                if (rdev->is_atom_bios)
+                        radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
+                else
+                        radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DAC2:
+                drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
+                drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
+                if (rdev->is_atom_bios)
+                        radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
+                else
+                        radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
+                break;
+        case ENCODER_OBJECT_ID_INTERNAL_DVO1:
+                drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
+                drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
+                if (!rdev->is_atom_bios)
+                        radeon_combios_get_ext_tmds_info(radeon_encoder);
+                break;
+        }
+}
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
new file mode 100644
index 000000000000..9173b687462b
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -0,0 +1,398 @@
+/*
+ * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
+ *                VA Linux Systems Inc., Fremont, California.
+ * Copyright 2008 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Original Authors:
+ *   Kevin E. Martin, Rickard E. Faith, Alan Hourihane
+ *
+ * Kernel port Author: Dave Airlie
+ */
+
+#ifndef RADEON_MODE_H
+#define RADEON_MODE_H
+
+#include <drm_crtc.h>
+#include <drm_mode.h>
+#include <drm_edid.h>
+#include <linux/i2c.h>
+#include <linux/i2c-id.h>
+#include <linux/i2c-algo-bit.h>
+
+#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
+#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
+#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
+#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
+
+enum radeon_connector_type {
+        CONNECTOR_NONE,
+        CONNECTOR_VGA,
+        CONNECTOR_DVI_I,
+        CONNECTOR_DVI_D,
+        CONNECTOR_DVI_A,
+        CONNECTOR_STV,
+        CONNECTOR_CTV,
+        CONNECTOR_LVDS,
+        CONNECTOR_DIGITAL,
+        CONNECTOR_SCART,
+        CONNECTOR_HDMI_TYPE_A,
+        CONNECTOR_HDMI_TYPE_B,
+        CONNECTOR_0XC,
+        CONNECTOR_0XD,
+        CONNECTOR_DIN,
+        CONNECTOR_DISPLAY_PORT,
+        CONNECTOR_UNSUPPORTED
+};
+
+enum radeon_dvi_type {
+        DVI_AUTO,
+        DVI_DIGITAL,
+        DVI_ANALOG
+};
+
+enum radeon_rmx_type {
+        RMX_OFF,
+        RMX_FULL,
+        RMX_CENTER,
+        RMX_ASPECT
+};
+
+enum radeon_tv_std {
+        TV_STD_NTSC,
+        TV_STD_PAL,
+        TV_STD_PAL_M,
+        TV_STD_PAL_60,
+        TV_STD_NTSC_J,
+        TV_STD_SCART_PAL,
+        TV_STD_SECAM,
+        TV_STD_PAL_CN,
+};
+
+struct radeon_i2c_bus_rec {
+        bool valid;
+        uint32_t mask_clk_reg;
+        uint32_t mask_data_reg;
+        uint32_t a_clk_reg;
+        uint32_t a_data_reg;
+        uint32_t put_clk_reg;
+        uint32_t put_data_reg;
+        uint32_t get_clk_reg;
+        uint32_t get_data_reg;
+        uint32_t mask_clk_mask;
+        uint32_t mask_data_mask;
+        uint32_t put_clk_mask;
+        uint32_t put_data_mask;
+        uint32_t get_clk_mask;
+        uint32_t get_data_mask;
+        uint32_t a_clk_mask;
+        uint32_t a_data_mask;
+};
+
+struct radeon_tmds_pll {
+    uint32_t freq;
+    uint32_t value;
+};
+
+#define RADEON_MAX_BIOS_CONNECTOR 16
+
+#define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
+#define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
+#define RADEON_PLL_USE_REF_DIV          (1 << 2)
+#define RADEON_PLL_LEGACY               (1 << 3)
+#define RADEON_PLL_PREFER_LOW_REF_DIV   (1 << 4)
+#define RADEON_PLL_PREFER_HIGH_REF_DIV  (1 << 5)
+#define RADEON_PLL_PREFER_LOW_FB_DIV    (1 << 6)
+#define RADEON_PLL_PREFER_HIGH_FB_DIV   (1 << 7)
+#define RADEON_PLL_PREFER_LOW_POST_DIV  (1 << 8)
+#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
+#define RADEON_PLL_USE_FRAC_FB_DIV      (1 << 10)
+
+struct radeon_pll {
+        uint16_t reference_freq;
+        uint16_t reference_div;
+        uint32_t pll_in_min;
+        uint32_t pll_in_max;
+        uint32_t pll_out_min;
+        uint32_t pll_out_max;
+        uint16_t xclk;
+
+        uint32_t min_ref_div;
+        uint32_t max_ref_div;
+        uint32_t min_post_div;
+        uint32_t max_post_div;
+        uint32_t min_feedback_div;
+        uint32_t max_feedback_div;
+        uint32_t min_frac_feedback_div;
+        uint32_t max_frac_feedback_div;
+        uint32_t best_vco;
+};
+
+struct radeon_i2c_chan {
+        struct drm_device *dev;
+        struct i2c_adapter adapter;
+        struct i2c_algo_bit_data algo;
+        struct radeon_i2c_bus_rec rec;
+};
+
+/* mostly for macs, but really any system without connector tables */
+enum radeon_connector_table {
+        CT_NONE,
+        CT_GENERIC,
+        CT_IBOOK,
+        CT_POWERBOOK_EXTERNAL,
+        CT_POWERBOOK_INTERNAL,
+        CT_POWERBOOK_VGA,
+        CT_MINI_EXTERNAL,
+        CT_MINI_INTERNAL,
+        CT_IMAC_G5_ISIGHT,
+        CT_EMAC,
+};
+
+struct radeon_mode_info {
+        struct atom_context *atom_context;
+        enum radeon_connector_table connector_table;
+        bool mode_config_initialized;
+};
+
+struct radeon_crtc {
+        struct drm_crtc base;
+        int crtc_id;
+        u16 lut_r[256], lut_g[256], lut_b[256];
+        bool enabled;
+        bool can_tile;
+        uint32_t crtc_offset;
+        struct radeon_framebuffer *fbdev_fb;
+        struct drm_mode_set mode_set;
+        struct drm_gem_object *cursor_bo;
+        uint64_t cursor_addr;
+        int cursor_width;
+        int cursor_height;
+};
+
+#define RADEON_USE_RMX 1
+
+struct radeon_native_mode {
+        /* preferred mode */
+        uint32_t panel_xres, panel_yres;
+        uint32_t hoverplus, hsync_width;
+        uint32_t hblank;
+        uint32_t voverplus, vsync_width;
+        uint32_t vblank;
+        uint32_t dotclock;
+        uint32_t flags;
+};
+
+struct radeon_encoder_primary_dac {
+        /* legacy primary dac */
+        uint32_t ps2_pdac_adj;
+};
+
+struct radeon_encoder_lvds {
+        /* legacy lvds */
+        uint16_t panel_vcc_delay;
+        uint8_t  panel_pwr_delay;
+        uint8_t  panel_digon_delay;
+        uint8_t  panel_blon_delay;
+        uint16_t panel_ref_divider;
+        uint8_t  panel_post_divider;
+        uint16_t panel_fb_divider;
+        bool     use_bios_dividers;
+        uint32_t lvds_gen_cntl;
+        /* panel mode */
+        struct radeon_native_mode native_mode;
+};
+
+struct radeon_encoder_tv_dac {
+        /* legacy tv dac */
+        uint32_t ps2_tvdac_adj;
+        uint32_t ntsc_tvdac_adj;
+        uint32_t pal_tvdac_adj;
+
+        enum radeon_tv_std tv_std;
+};
+
+struct radeon_encoder_int_tmds {
+        /* legacy int tmds */
+        struct radeon_tmds_pll tmds_pll[4];
+};
+
+struct radeon_encoder_atom_dig {
+        /* atom dig */
+        bool coherent_mode;
+        int dig_block;
+        /* atom lvds */
+        uint32_t lvds_misc;
+        uint16_t panel_pwr_delay;
+        /* panel mode */
+        struct radeon_native_mode native_mode;
+};
+
+struct radeon_encoder {
+        struct drm_encoder base;
+        uint32_t encoder_id;
+        uint32_t devices;
+        uint32_t flags;
+        uint32_t pixel_clock;
+        enum radeon_rmx_type rmx_type;
+        struct radeon_native_mode native_mode;
+        void *enc_priv;
+};
+
+struct radeon_connector_atom_dig {
+        uint32_t igp_lane_info;
+        bool linkb;
+};
+
+struct radeon_connector {
+        struct drm_connector base;
+        uint32_t connector_id;
+        uint32_t devices;
+        struct radeon_i2c_chan *ddc_bus;
+        int use_digital;
+        void *con_priv;
+};
+
+struct radeon_framebuffer {
+        struct drm_framebuffer base;
+        struct drm_gem_object *obj;
+};
+
+extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
+                                                 struct radeon_i2c_bus_rec *rec,
+                                                 const char *name);
+extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
+extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
+extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
+
+extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
+
+extern void radeon_compute_pll(struct radeon_pll *pll,
+                               uint64_t freq,
+                               uint32_t *dot_clock_p,
+                               uint32_t *fb_div_p,
+                               uint32_t *frac_fb_div_p,
+                               uint32_t *ref_div_p,
+                               uint32_t *post_div_p,
+                               int flags);
+
+struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
+struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
+struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
+struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
+struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
+extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
+extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
+
+extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
+extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
+                                   struct drm_framebuffer *old_fb);
+extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
+                                   struct drm_display_mode *mode,
+                                   struct drm_display_mode *adjusted_mode,
+                                   int x, int y,
+                                   struct drm_framebuffer *old_fb);
+extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
+
+extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
+                                 struct drm_framebuffer *old_fb);
+extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
+
+extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
+                                  struct drm_file *file_priv,
+                                  uint32_t handle,
+                                  uint32_t width,
+                                  uint32_t height);
+extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
+                                   int x, int y);
+
+extern bool radeon_atom_get_clock_info(struct drm_device *dev);
+extern bool radeon_combios_get_clock_info(struct drm_device *dev);
+extern struct radeon_encoder_atom_dig *
+radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
+extern struct radeon_encoder_int_tmds *
+radeon_atombios_get_tmds_info(struct radeon_encoder *encoder);
+extern struct radeon_encoder_primary_dac *
+radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
+extern struct radeon_encoder_tv_dac *
+radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
+extern struct radeon_encoder_lvds *
+radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
+extern struct radeon_encoder_int_tmds *
+radeon_combios_get_tmds_info(struct radeon_encoder *encoder);
+extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
+extern struct radeon_encoder_tv_dac *
+radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
+extern struct radeon_encoder_primary_dac *
+radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
+extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
+extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
+extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
+extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
+extern void
+radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
+extern void
+radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
+extern void
+radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
+extern void
+radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
+extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
+                                     u16 blue, int regno);
+struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
+                                                  struct drm_mode_fb_cmd *mode_cmd,
+                                                  struct drm_gem_object *obj);
+
+int radeonfb_probe(struct drm_device *dev);
+
+int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
+bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
+bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
+void radeon_atombios_init_crtc(struct drm_device *dev,
+                               struct radeon_crtc *radeon_crtc);
+void radeon_legacy_init_crtc(struct drm_device *dev,
+                             struct radeon_crtc *radeon_crtc);
+void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state);
+
+void radeon_get_clock_info(struct drm_device *dev);
+
+extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
+extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
+
+void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
+                           struct drm_display_mode *mode,
+                           struct drm_display_mode *adjusted_mode);
+void radeon_enc_destroy(struct drm_encoder *encoder);
+void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
+void radeon_combios_asic_init(struct drm_device *dev);
+extern int radeon_static_clocks_init(struct drm_device *dev);
+void radeon_init_disp_bw_legacy(struct drm_device *dev,
+                                struct drm_display_mode *mode1,
+                                uint32_t pixel_bytes1,
+                                struct drm_display_mode *mode2,
+                                uint32_t pixel_bytes2);
+void radeon_init_disp_bw_avivo(struct drm_device *dev,
+                               struct drm_display_mode *mode1,
+                               uint32_t pixel_bytes1,
+                               struct drm_display_mode *mode2,
+                               uint32_t pixel_bytes2);
+void radeon_init_disp_bandwidth(struct drm_device *dev);
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
new file mode 100644
index 000000000000..983e8df5e000
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -0,0 +1,511 @@
+/*
+ * Copyright 2009 Jerome Glisse.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ */
+/*
+ * Authors:
+ *    Jerome Glisse <glisse@freedesktop.org>
+ *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
+ *    Dave Airlie
+ */
+#include <linux/list.h>
+#include <drm/drmP.h>
+#include "radeon_drm.h"
+#include "radeon.h"
+
+struct radeon_object {
+        struct ttm_buffer_object        tobj;
+        struct list_head                list;
+        struct radeon_device            *rdev;
+        struct drm_gem_object           *gobj;
+        struct ttm_bo_kmap_obj          kmap;
+        unsigned                        pin_count;
+        uint64_t                        gpu_addr;
+        void                            *kptr;
+        bool                            is_iomem;
+};
+
+int radeon_ttm_init(struct radeon_device *rdev);
+void radeon_ttm_fini(struct radeon_device *rdev);
+
+/*
+ * To exclude mutual BO access we rely on bo_reserve exclusion, as all
+ * function are calling it.
+ */
+
+static int radeon_object_reserve(struct radeon_object *robj, bool interruptible)
+{
+        return ttm_bo_reserve(&robj->tobj, interruptible, false, false, 0);
+}
+
+static void radeon_object_unreserve(struct radeon_object *robj)
+{
+        ttm_bo_unreserve(&robj->tobj);
+}
+
+static void radeon_ttm_object_object_destroy(struct ttm_buffer_object *tobj)
+{
+        struct radeon_object *robj;
+
+        robj = container_of(tobj, struct radeon_object, tobj);
+        list_del_init(&robj->list);
+        kfree(robj);
+}
+
+static inline void radeon_object_gpu_addr(struct radeon_object *robj)
+{
+        /* Default gpu address */
+        robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
+        if (robj->tobj.mem.mm_node == NULL) {
+                return;
+        }
+        robj->gpu_addr = ((u64)robj->tobj.mem.mm_node->start) << PAGE_SHIFT;
+        switch (robj->tobj.mem.mem_type) {
+        case TTM_PL_VRAM:
+                robj->gpu_addr += (u64)robj->rdev->mc.vram_location;
+                break;
+        case TTM_PL_TT:
+                robj->gpu_addr += (u64)robj->rdev->mc.gtt_location;
+                break;
+        default:
+                DRM_ERROR("Unknown placement %d\n", robj->tobj.mem.mem_type);
+                robj->gpu_addr = 0xFFFFFFFFFFFFFFFFULL;
+                return;
+        }
+}
+
+static inline uint32_t radeon_object_flags_from_domain(uint32_t domain)
+{
+        uint32_t flags = 0;
+        if (domain & RADEON_GEM_DOMAIN_VRAM) {
+                flags |= TTM_PL_FLAG_VRAM;
+        }
+        if (domain & RADEON_GEM_DOMAIN_GTT) {
+                flags |= TTM_PL_FLAG_TT;
+        }
+        if (domain & RADEON_GEM_DOMAIN_CPU) {
+                flags |= TTM_PL_FLAG_SYSTEM;
+        }
+        if (!flags) {
+                flags |= TTM_PL_FLAG_SYSTEM;
+        }
+        return flags;
+}
+
+int radeon_object_create(struct radeon_device *rdev,
+                         struct drm_gem_object *gobj,
+                         unsigned long size,
+                         bool kernel,
+                         uint32_t domain,
+                         bool interruptible,
+                         struct radeon_object **robj_ptr)
+{
+        struct radeon_object *robj;
+        enum ttm_bo_type type;
+        uint32_t flags;
+        int r;
+
+        if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
+                rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
+        }
+        if (kernel) {
+                type = ttm_bo_type_kernel;
+        } else {
+                type = ttm_bo_type_device;
+        }
+        *robj_ptr = NULL;
+        robj = kzalloc(sizeof(struct radeon_object), GFP_KERNEL);
+        if (robj == NULL) {
+                return -ENOMEM;
+        }
+        robj->rdev = rdev;
+        robj->gobj = gobj;
+        INIT_LIST_HEAD(&robj->list);
+
+        flags = radeon_object_flags_from_domain(domain);
+        r = ttm_buffer_object_init(&rdev->mman.bdev, &robj->tobj, size, type, flags,
+                                   0, 0, false, NULL, size,
+                                   &radeon_ttm_object_object_destroy);
+        if (unlikely(r != 0)) {
+                /* ttm call radeon_ttm_object_object_destroy if error happen */
+                DRM_ERROR("Failed to allocate TTM object (%ld, 0x%08X, %u)\n",
+                          size, flags, 0);
+                return r;
+        }
+        *robj_ptr = robj;
+        if (gobj) {
+                list_add_tail(&robj->list, &rdev->gem.objects);
+        }
+        return 0;
+}
+
+int radeon_object_kmap(struct radeon_object *robj, void **ptr)
+{
+        int r;
+
+        spin_lock(&robj->tobj.lock);
+        if (robj->kptr) {
+                if (ptr) {
+                        *ptr = robj->kptr;
+                }
+                spin_unlock(&robj->tobj.lock);
+                return 0;
+        }
+        spin_unlock(&robj->tobj.lock);
+        r = ttm_bo_kmap(&robj->tobj, 0, robj->tobj.num_pages, &robj->kmap);
+        if (r) {
+                return r;
+        }
+        spin_lock(&robj->tobj.lock);
+        robj->kptr = ttm_kmap_obj_virtual(&robj->kmap, &robj->is_iomem);
+        spin_unlock(&robj->tobj.lock);
+        if (ptr) {
+                *ptr = robj->kptr;
+        }
+        return 0;
+}
+
+void radeon_object_kunmap(struct radeon_object *robj)
+{
+        spin_lock(&robj->tobj.lock);
+        if (robj->kptr == NULL) {
+                spin_unlock(&robj->tobj.lock);
+                return;
+        }
+        robj->kptr = NULL;
+        spin_unlock(&robj->tobj.lock);
+        ttm_bo_kunmap(&robj->kmap);
+}
+
+void radeon_object_unref(struct radeon_object **robj)
+{
+        struct ttm_buffer_object *tobj;
+
+        if ((*robj) == NULL) {
+                return;
+        }
+        tobj = &((*robj)->tobj);
+        ttm_bo_unref(&tobj);
+        if (tobj == NULL) {
+                *robj = NULL;
+        }
+}
+
+int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset)
+{
+        *offset = robj->tobj.addr_space_offset;
+        return 0;
+}
+
+int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
+                      uint64_t *gpu_addr)
+{
+        uint32_t flags;
+        uint32_t tmp;
+        void *fbptr;
+        int r;
+
+        flags = radeon_object_flags_from_domain(domain);
+        spin_lock(&robj->tobj.lock);
+        if (robj->pin_count) {
+                robj->pin_count++;
+                if (gpu_addr != NULL) {
+                        *gpu_addr = robj->gpu_addr;
+                }
+                spin_unlock(&robj->tobj.lock);
+                return 0;
+        }
+        spin_unlock(&robj->tobj.lock);
+        r = radeon_object_reserve(robj, false);
+        if (unlikely(r != 0)) {
+                DRM_ERROR("radeon: failed to reserve object for pinning it.\n");
+                return r;
+        }
+        if (robj->rdev->fbdev_robj == robj) {
+                mutex_lock(&robj->rdev->fbdev_info->lock);
+                radeon_object_kunmap(robj);
+        }
+        tmp = robj->tobj.mem.placement;
+        ttm_flag_masked(&tmp, flags, TTM_PL_MASK_MEM);
+        robj->tobj.proposed_placement = tmp | TTM_PL_FLAG_NO_EVICT | TTM_PL_MASK_CACHING;
+        r = ttm_buffer_object_validate(&robj->tobj,
+                                       robj->tobj.proposed_placement,
+                                       false, false);
+        radeon_object_gpu_addr(robj);
+        if (gpu_addr != NULL) {
+                *gpu_addr = robj->gpu_addr;
+        }
+        robj->pin_count = 1;
+        if (unlikely(r != 0)) {
+                DRM_ERROR("radeon: failed to pin object.\n");
+        }
+        radeon_object_unreserve(robj);
+        if (robj->rdev->fbdev_robj == robj) {
+                if (!r) {
+                        r = radeon_object_kmap(robj, &fbptr);
+                }
+                if (!r) {
+                        robj->rdev->fbdev_info->screen_base = fbptr;
+                        robj->rdev->fbdev_info->fix.smem_start = (unsigned long)fbptr;
+                }
+                mutex_unlock(&robj->rdev->fbdev_info->lock);
+        }
+        return r;
+}
+
+void radeon_object_unpin(struct radeon_object *robj)
+{
+        uint32_t flags;
+        void *fbptr;
+        int r;
+
+        spin_lock(&robj->tobj.lock);
+        if (!robj->pin_count) {
+                spin_unlock(&robj->tobj.lock);
+                printk(KERN_WARNING "Unpin not necessary for %p !\n", robj);
+                return;
+        }
+        robj->pin_count--;
+        if (robj->pin_count) {
+                spin_unlock(&robj->tobj.lock);
+                return;
+        }
+        spin_unlock(&robj->tobj.lock);
+        r = radeon_object_reserve(robj, false);
+        if (unlikely(r != 0)) {
+                DRM_ERROR("radeon: failed to reserve object for unpinning it.\n");
+                return;
+        }
+        if (robj->rdev->fbdev_robj == robj) {
+                mutex_lock(&robj->rdev->fbdev_info->lock);
+                radeon_object_kunmap(robj);
+        }
+        flags = robj->tobj.mem.placement;
+        robj->tobj.proposed_placement = flags & ~TTM_PL_FLAG_NO_EVICT;
+        r = ttm_buffer_object_validate(&robj->tobj,
+                                       robj->tobj.proposed_placement,
+                                       false, false);
+        if (unlikely(r != 0)) {
+                DRM_ERROR("radeon: failed to unpin buffer.\n");
+        }
+        radeon_object_unreserve(robj);
+        if (robj->rdev->fbdev_robj == robj) {
+                if (!r) {
+                        r = radeon_object_kmap(robj, &fbptr);
+                }
+                if (!r) {
+                        robj->rdev->fbdev_info->screen_base = fbptr;
+                        robj->rdev->fbdev_info->fix.smem_start = (unsigned long)fbptr;
+                }
+                mutex_unlock(&robj->rdev->fbdev_info->lock);
+        }
+}
+
+int radeon_object_wait(struct radeon_object *robj)
+{
+        int r = 0;
+
+        /* FIXME: should use block reservation instead */
+        r = radeon_object_reserve(robj, true);
+        if (unlikely(r != 0)) {
+                DRM_ERROR("radeon: failed to reserve object for waiting.\n");
+                return r;
+        }
+        spin_lock(&robj->tobj.lock);
+        if (robj->tobj.sync_obj) {
+                r = ttm_bo_wait(&robj->tobj, true, false, false);
+        }
+        spin_unlock(&robj->tobj.lock);
+        radeon_object_unreserve(robj);
+        return r;
+}
+
+int radeon_object_evict_vram(struct radeon_device *rdev)
+{
+        if (rdev->flags & RADEON_IS_IGP) {
+                /* Useless to evict on IGP chips */
+                return 0;
+        }
+        return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
+}
+
+void radeon_object_force_delete(struct radeon_device *rdev)
+{
+        struct radeon_object *robj, *n;
+        struct drm_gem_object *gobj;
+
+        if (list_empty(&rdev->gem.objects)) {
+                return;
+        }
+        DRM_ERROR("Userspace still has active objects !\n");
+        list_for_each_entry_safe(robj, n, &rdev->gem.objects, list) {
+                mutex_lock(&rdev->ddev->struct_mutex);
+                gobj = robj->gobj;
+                DRM_ERROR("Force free for (%p,%p,%lu,%lu)\n",
+                          gobj, robj, (unsigned long)gobj->size,
+                          *((unsigned long *)&gobj->refcount));
+                list_del_init(&robj->list);
+                radeon_object_unref(&robj);
+                gobj->driver_private = NULL;
+                drm_gem_object_unreference(gobj);
+                mutex_unlock(&rdev->ddev->struct_mutex);
+        }
+}
+
+int radeon_object_init(struct radeon_device *rdev)
+{
+        return radeon_ttm_init(rdev);
+}
+
+void radeon_object_fini(struct radeon_device *rdev)
+{
+        radeon_ttm_fini(rdev);
+}
+
+void radeon_object_list_add_object(struct radeon_object_list *lobj,
+                                   struct list_head *head)
+{
+        if (lobj->wdomain) {
+                list_add(&lobj->list, head);
+        } else {
+                list_add_tail(&lobj->list, head);
+        }
+}
+
+int radeon_object_list_reserve(struct list_head *head)
+{
+        struct radeon_object_list *lobj;
+        struct list_head *i;
+        int r;
+
+        list_for_each(i, head) {
+                lobj = list_entry(i, struct radeon_object_list, list);
+                if (!lobj->robj->pin_count) {
+                        r = radeon_object_reserve(lobj->robj, true);
+                        if (unlikely(r != 0)) {
+                                DRM_ERROR("radeon: failed to reserve object.\n");
+                                return r;
+                        }
+                } else {
+                }
+        }
+        return 0;
+}
+
+void radeon_object_list_unreserve(struct list_head *head)
+{
+        struct radeon_object_list *lobj;
+        struct list_head *i;
+
+        list_for_each(i, head) {
+                lobj = list_entry(i, struct radeon_object_list, list);
+                if (!lobj->robj->pin_count) {
+                        radeon_object_unreserve(lobj->robj);
+                } else {
+                }
+        }
+}
+
+int radeon_object_list_validate(struct list_head *head, void *fence)
+{
+        struct radeon_object_list *lobj;
+        struct radeon_object *robj;
+        struct radeon_fence *old_fence = NULL;
+        struct list_head *i;
+        uint32_t flags;
+        int r;
+
+        r = radeon_object_list_reserve(head);
+        if (unlikely(r != 0)) {
+                radeon_object_list_unreserve(head);
+                return r;
+        }
+        list_for_each(i, head) {
+                lobj = list_entry(i, struct radeon_object_list, list);
+                robj = lobj->robj;
+                if (lobj->wdomain) {
+                        flags = radeon_object_flags_from_domain(lobj->wdomain);
+                        flags |= TTM_PL_FLAG_TT;
+                } else {
+                        flags = radeon_object_flags_from_domain(lobj->rdomain);
+                        flags |= TTM_PL_FLAG_TT;
+                        flags |= TTM_PL_FLAG_VRAM;
+                }
+                if (!robj->pin_count) {
+                        robj->tobj.proposed_placement = flags | TTM_PL_MASK_CACHING;
+                        r = ttm_buffer_object_validate(&robj->tobj,
+                                                       robj->tobj.proposed_placement,
+                                                       true, false);
+                        if (unlikely(r)) {
+                                radeon_object_list_unreserve(head);
+                                DRM_ERROR("radeon: failed to validate.\n");
+                                return r;
+                        }
+                        radeon_object_gpu_addr(robj);
+                }
+                lobj->gpu_offset = robj->gpu_addr;
+                if (fence) {
+                        old_fence = (struct radeon_fence *)robj->tobj.sync_obj;
+                        robj->tobj.sync_obj = radeon_fence_ref(fence);
+                        robj->tobj.sync_obj_arg = NULL;
+                }
+                if (old_fence) {
+                        radeon_fence_unref(&old_fence);
+                }
+        }
+        return 0;
+}
+
+void radeon_object_list_unvalidate(struct list_head *head)
+{
+        struct radeon_object_list *lobj;
+        struct radeon_fence *old_fence = NULL;
+        struct list_head *i;
+
+        list_for_each(i, head) {
+                lobj = list_entry(i, struct radeon_object_list, list);
+                old_fence = (struct radeon_fence *)lobj->robj->tobj.sync_obj;
+                lobj->robj->tobj.sync_obj = NULL;
+                if (old_fence) {
+                        radeon_fence_unref(&old_fence);
+                }
+        }
+        radeon_object_list_unreserve(head);
+}
+
+void radeon_object_list_clean(struct list_head *head)
+{
+        radeon_object_list_unreserve(head);
+}
+
+int radeon_object_fbdev_mmap(struct radeon_object *robj,
+                             struct vm_area_struct *vma)
+{
+        return ttm_fbdev_mmap(vma, &robj->tobj);
+}
+
+unsigned long radeon_object_size(struct radeon_object *robj)
+{
+        return robj->tobj.num_pages << PAGE_SHIFT;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h
new file mode 100644
index 000000000000..473e4775dc5a
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_object.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#ifndef __RADEON_OBJECT_H__
+#define __RADEON_OBJECT_H__
+
+#include <ttm/ttm_bo_api.h>
+#include <ttm/ttm_bo_driver.h>
+#include <ttm/ttm_placement.h>
+#include <ttm/ttm_module.h>
+
+/*
+ * TTM.
+ */
+struct radeon_mman {
+        struct ttm_global_reference     mem_global_ref;
+        bool                            mem_global_referenced;
+        struct ttm_bo_device            bdev;
+};
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
new file mode 100644
index 000000000000..6d3d90406a24
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -0,0 +1,3570 @@
+/*
+ * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
+ *                VA Linux Systems Inc., Fremont, California.
+ *
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation on the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
+ * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Authors:
+ *   Kevin E. Martin <martin@xfree86.org>
+ *   Rickard E. Faith <faith@valinux.com>
+ *   Alan Hourihane <alanh@fairlite.demon.co.uk>
+ *
+ * References:
+ *
+ * !!!! FIXME !!!!
+ *   RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
+ *   Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
+ *   1999.
+ *
+ * !!!! FIXME !!!!
+ *   RAGE 128 Software Development Manual (Technical Reference Manual P/N
+ *   SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
+ *
+ */
+
+/* !!!! FIXME !!!!  NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
+ * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
+ * ON THE RADEON.  A FULL AUDIT OF THIS CODE IS NEEDED!  */
+#ifndef _RADEON_REG_H_
+#define _RADEON_REG_H_
+
+#include "r300_reg.h"
+#include "r500_reg.h"
+#include "r600_reg.h"
+
+
+#define RADEON_MC_AGP_LOCATION          0x014c
+#define         RADEON_MC_AGP_START_MASK        0x0000FFFF
+#define         RADEON_MC_AGP_START_SHIFT       0
+#define         RADEON_MC_AGP_TOP_MASK          0xFFFF0000
+#define         RADEON_MC_AGP_TOP_SHIFT         16
+#define RADEON_MC_FB_LOCATION           0x0148
+#define         RADEON_MC_FB_START_MASK         0x0000FFFF
+#define         RADEON_MC_FB_START_SHIFT        0
+#define         RADEON_MC_FB_TOP_MASK           0xFFFF0000
+#define         RADEON_MC_FB_TOP_SHIFT          16
+#define RADEON_AGP_BASE_2               0x015c /* r200+ only */
+#define RADEON_AGP_BASE                 0x0170
+
+#define ATI_DATATYPE_VQ                         0
+#define ATI_DATATYPE_CI4                        1
+#define ATI_DATATYPE_CI8                        2
+#define ATI_DATATYPE_ARGB1555                   3
+#define ATI_DATATYPE_RGB565                     4
+#define ATI_DATATYPE_RGB888                     5
+#define ATI_DATATYPE_ARGB8888                   6
+#define ATI_DATATYPE_RGB332                     7
+#define ATI_DATATYPE_Y8                         8
+#define ATI_DATATYPE_RGB8                       9
+#define ATI_DATATYPE_CI16                       10
+#define ATI_DATATYPE_VYUY_422                   11
+#define ATI_DATATYPE_YVYU_422                   12
+#define ATI_DATATYPE_AYUV_444                   14
+#define ATI_DATATYPE_ARGB4444                   15
+
+                                /* Registers for 2D/Video/Overlay */
+#define RADEON_ADAPTER_ID                   0x0f2c /* PCI */
+#define RADEON_AGP_BASE                     0x0170
+#define RADEON_AGP_CNTL                     0x0174
+#       define RADEON_AGP_APER_SIZE_256MB   (0x00 << 0)
+#       define RADEON_AGP_APER_SIZE_128MB   (0x20 << 0)
+#       define RADEON_AGP_APER_SIZE_64MB    (0x30 << 0)
+#       define RADEON_AGP_APER_SIZE_32MB    (0x38 << 0)
+#       define RADEON_AGP_APER_SIZE_16MB    (0x3c << 0)
+#       define RADEON_AGP_APER_SIZE_8MB     (0x3e << 0)
+#       define RADEON_AGP_APER_SIZE_4MB     (0x3f << 0)
+#       define RADEON_AGP_APER_SIZE_MASK    (0x3f << 0)
+#define RADEON_STATUS_PCI_CONFIG            0x06
+#       define RADEON_CAP_LIST              0x100000
+#define RADEON_CAPABILITIES_PTR_PCI_CONFIG  0x34 /* offset in PCI config*/
+#       define RADEON_CAP_PTR_MASK          0xfc /* mask off reserved bits of CAP_PTR */
+#       define RADEON_CAP_ID_NULL           0x00 /* End of capability list */
+#       define RADEON_CAP_ID_AGP            0x02 /* AGP capability ID */
+#       define RADEON_CAP_ID_EXP            0x10 /* PCI Express */
+#define RADEON_AGP_COMMAND                  0x0f60 /* PCI */
+#define RADEON_AGP_COMMAND_PCI_CONFIG       0x0060 /* offset in PCI config*/
+#       define RADEON_AGP_ENABLE            (1<<8)
+#define RADEON_AGP_PLL_CNTL                 0x000b /* PLL */
+#define RADEON_AGP_STATUS                   0x0f5c /* PCI */
+#       define RADEON_AGP_1X_MODE           0x01
+#       define RADEON_AGP_2X_MODE           0x02
+#       define RADEON_AGP_4X_MODE           0x04
+#       define RADEON_AGP_FW_MODE           0x10
+#       define RADEON_AGP_MODE_MASK         0x17
+#       define RADEON_AGPv3_MODE            0x08
+#       define RADEON_AGPv3_4X_MODE         0x01
+#       define RADEON_AGPv3_8X_MODE         0x02
+#define RADEON_ATTRDR                       0x03c1 /* VGA */
+#define RADEON_ATTRDW                       0x03c0 /* VGA */
+#define RADEON_ATTRX                        0x03c0 /* VGA */
+#define RADEON_AUX_SC_CNTL                  0x1660
+#       define RADEON_AUX1_SC_EN            (1 << 0)
+#       define RADEON_AUX1_SC_MODE_OR       (0 << 1)
+#       define RADEON_AUX1_SC_MODE_NAND     (1 << 1)
+#       define RADEON_AUX2_SC_EN            (1 << 2)
+#       define RADEON_AUX2_SC_MODE_OR       (0 << 3)
+#       define RADEON_AUX2_SC_MODE_NAND     (1 << 3)
+#       define RADEON_AUX3_SC_EN            (1 << 4)
+#       define RADEON_AUX3_SC_MODE_OR       (0 << 5)
+#       define RADEON_AUX3_SC_MODE_NAND     (1 << 5)
+#define RADEON_AUX1_SC_BOTTOM               0x1670
+#define RADEON_AUX1_SC_LEFT                 0x1664
+#define RADEON_AUX1_SC_RIGHT                0x1668
+#define RADEON_AUX1_SC_TOP                  0x166c
+#define RADEON_AUX2_SC_BOTTOM               0x1680
+#define RADEON_AUX2_SC_LEFT                 0x1674
+#define RADEON_AUX2_SC_RIGHT                0x1678
+#define RADEON_AUX2_SC_TOP                  0x167c
+#define RADEON_AUX3_SC_BOTTOM               0x1690
+#define RADEON_AUX3_SC_LEFT                 0x1684
+#define RADEON_AUX3_SC_RIGHT                0x1688
+#define RADEON_AUX3_SC_TOP                  0x168c
+#define RADEON_AUX_WINDOW_HORZ_CNTL         0x02d8
+#define RADEON_AUX_WINDOW_VERT_CNTL         0x02dc
+
+#define RADEON_BASE_CODE                    0x0f0b
+#define RADEON_BIOS_0_SCRATCH               0x0010
+#       define RADEON_FP_PANEL_SCALABLE     (1 << 16)
+#       define RADEON_FP_PANEL_SCALE_EN     (1 << 17)
+#       define RADEON_FP_CHIP_SCALE_EN      (1 << 18)
+#       define RADEON_DRIVER_BRIGHTNESS_EN  (1 << 26)
+#       define RADEON_DISPLAY_ROT_MASK      (3 << 28)
+#       define RADEON_DISPLAY_ROT_00        (0 << 28)
+#       define RADEON_DISPLAY_ROT_90        (1 << 28)
+#       define RADEON_DISPLAY_ROT_180       (2 << 28)
+#       define RADEON_DISPLAY_ROT_270       (3 << 28)
+#define RADEON_BIOS_1_SCRATCH               0x0014
+#define RADEON_BIOS_2_SCRATCH               0x0018
+#define RADEON_BIOS_3_SCRATCH               0x001c
+#define RADEON_BIOS_4_SCRATCH               0x0020
+#       define RADEON_CRT1_ATTACHED_MASK    (3 << 0)
+#       define RADEON_CRT1_ATTACHED_MONO    (1 << 0)
+#       define RADEON_CRT1_ATTACHED_COLOR   (2 << 0)
+#       define RADEON_LCD1_ATTACHED         (1 << 2)
+#       define RADEON_DFP1_ATTACHED         (1 << 3)
+#       define RADEON_TV1_ATTACHED_MASK     (3 << 4)
+#       define RADEON_TV1_ATTACHED_COMP     (1 << 4)
+#       define RADEON_TV1_ATTACHED_SVIDEO   (2 << 4)
+#       define RADEON_CRT2_ATTACHED_MASK    (3 << 8)
+#       define RADEON_CRT2_ATTACHED_MONO    (1 << 8)
+#       define RADEON_CRT2_ATTACHED_COLOR   (2 << 8)
+#       define RADEON_DFP2_ATTACHED         (1 << 11)
+#define RADEON_BIOS_5_SCRATCH               0x0024
+#       define RADEON_LCD1_ON               (1 << 0)
+#       define RADEON_CRT1_ON               (1 << 1)
+#       define RADEON_TV1_ON                (1 << 2)
+#       define RADEON_DFP1_ON               (1 << 3)
+#       define RADEON_CRT2_ON               (1 << 5)
+#       define RADEON_CV1_ON                (1 << 6)
+#       define RADEON_DFP2_ON               (1 << 7)
+#       define RADEON_LCD1_CRTC_MASK        (1 << 8)
+#       define RADEON_LCD1_CRTC_SHIFT       8
+#       define RADEON_CRT1_CRTC_MASK        (1 << 9)
+#       define RADEON_CRT1_CRTC_SHIFT       9
+#       define RADEON_TV1_CRTC_MASK         (1 << 10)
+#       define RADEON_TV1_CRTC_SHIFT        10
+#       define RADEON_DFP1_CRTC_MASK        (1 << 11)
+#       define RADEON_DFP1_CRTC_SHIFT       11
+#       define RADEON_CRT2_CRTC_MASK        (1 << 12)
+#       define RADEON_CRT2_CRTC_SHIFT       12
+#       define RADEON_CV1_CRTC_MASK         (1 << 13)
+#       define RADEON_CV1_CRTC_SHIFT        13
+#       define RADEON_DFP2_CRTC_MASK        (1 << 14)
+#       define RADEON_DFP2_CRTC_SHIFT       14
+#       define RADEON_ACC_REQ_LCD1          (1 << 16)
+#       define RADEON_ACC_REQ_CRT1          (1 << 17)
+#       define RADEON_ACC_REQ_TV1           (1 << 18)
+#       define RADEON_ACC_REQ_DFP1          (1 << 19)
+#       define RADEON_ACC_REQ_CRT2          (1 << 21)
+#       define RADEON_ACC_REQ_TV2           (1 << 22)
+#       define RADEON_ACC_REQ_DFP2          (1 << 23)
+#define RADEON_BIOS_6_SCRATCH               0x0028
+#       define RADEON_ACC_MODE_CHANGE       (1 << 2)
+#       define RADEON_EXT_DESKTOP_MODE      (1 << 3)
+#       define RADEON_LCD_DPMS_ON           (1 << 20)
+#       define RADEON_CRT_DPMS_ON           (1 << 21)
+#       define RADEON_TV_DPMS_ON            (1 << 22)
+#       define RADEON_DFP_DPMS_ON           (1 << 23)
+#       define RADEON_DPMS_MASK             (3 << 24)
+#       define RADEON_DPMS_ON               (0 << 24)
+#       define RADEON_DPMS_STANDBY          (1 << 24)
+#       define RADEON_DPMS_SUSPEND          (2 << 24)
+#       define RADEON_DPMS_OFF              (3 << 24)
+#       define RADEON_SCREEN_BLANKING       (1 << 26)
+#       define RADEON_DRIVER_CRITICAL       (1 << 27)
+#       define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
+#define RADEON_BIOS_7_SCRATCH               0x002c
+#       define RADEON_SYS_HOTKEY            (1 << 10)
+#       define RADEON_DRV_LOADED            (1 << 12)
+#define RADEON_BIOS_ROM                     0x0f30 /* PCI */
+#define RADEON_BIST                         0x0f0f /* PCI */
+#define RADEON_BRUSH_DATA0                  0x1480
+#define RADEON_BRUSH_DATA1                  0x1484
+#define RADEON_BRUSH_DATA10                 0x14a8
+#define RADEON_BRUSH_DATA11                 0x14ac
+#define RADEON_BRUSH_DATA12                 0x14b0
+#define RADEON_BRUSH_DATA13                 0x14b4
+#define RADEON_BRUSH_DATA14                 0x14b8
+#define RADEON_BRUSH_DATA15                 0x14bc
+#define RADEON_BRUSH_DATA16                 0x14c0
+#define RADEON_BRUSH_DATA17                 0x14c4
+#define RADEON_BRUSH_DATA18                 0x14c8
+#define RADEON_BRUSH_DATA19                 0x14cc
+#define RADEON_BRUSH_DATA2                  0x1488
+#define RADEON_BRUSH_DATA20                 0x14d0
+#define RADEON_BRUSH_DATA21                 0x14d4
+#define RADEON_BRUSH_DATA22                 0x14d8
+#define RADEON_BRUSH_DATA23                 0x14dc
+#define RADEON_BRUSH_DATA24                 0x14e0
+#define RADEON_BRUSH_DATA25                 0x14e4
+#define RADEON_BRUSH_DATA26                 0x14e8
+#define RADEON_BRUSH_DATA27                 0x14ec
+#define RADEON_BRUSH_DATA28                 0x14f0
+#define RADEON_BRUSH_DATA29                 0x14f4
+#define RADEON_BRUSH_DATA3                  0x148c
+#define RADEON_BRUSH_DATA30                 0x14f8
+#define RADEON_BRUSH_DATA31                 0x14fc
+#define RADEON_BRUSH_DATA32                 0x1500
+#define RADEON_BRUSH_DATA33                 0x1504
+#define RADEON_BRUSH_DATA34                 0x1508
+#define RADEON_BRUSH_DATA35                 0x150c
+#define RADEON_BRUSH_DATA36                 0x1510
+#define RADEON_BRUSH_DATA37                 0x1514
+#define RADEON_BRUSH_DATA38                 0x1518
+#define RADEON_BRUSH_DATA39                 0x151c
+#define RADEON_BRUSH_DATA4                  0x1490
+#define RADEON_BRUSH_DATA40                 0x1520
+#define RADEON_BRUSH_DATA41                 0x1524
+#define RADEON_BRUSH_DATA42                 0x1528
+#define RADEON_BRUSH_DATA43                 0x152c
+#define RADEON_BRUSH_DATA44                 0x1530
+#define RADEON_BRUSH_DATA45                 0x1534
+#define RADEON_BRUSH_DATA46                 0x1538
+#define RADEON_BRUSH_DATA47                 0x153c
+#define RADEON_BRUSH_DATA48                 0x1540
+#define RADEON_BRUSH_DATA49                 0x1544
+#define RADEON_BRUSH_DATA5                  0x1494
+#define RADEON_BRUSH_DATA50                 0x1548
+#define RADEON_BRUSH_DATA51                 0x154c
+#define RADEON_BRUSH_DATA52                 0x1550
+#define RADEON_BRUSH_DATA53                 0x1554
+#define RADEON_BRUSH_DATA54                 0x1558
+#define RADEON_BRUSH_DATA55                 0x155c
+#define RADEON_BRUSH_DATA56                 0x1560
+#define RADEON_BRUSH_DATA57                 0x1564
+#define RADEON_BRUSH_DATA58                 0x1568
+#define RADEON_BRUSH_DATA59                 0x156c
+#define RADEON_BRUSH_DATA6                  0x1498
+#define RADEON_BRUSH_DATA60                 0x1570
+#define RADEON_BRUSH_DATA61                 0x1574
+#define RADEON_BRUSH_DATA62                 0x1578
+#define RADEON_BRUSH_DATA63                 0x157c
+#define RADEON_BRUSH_DATA7                  0x149c
+#define RADEON_BRUSH_DATA8                  0x14a0
+#define RADEON_BRUSH_DATA9                  0x14a4
+#define RADEON_BRUSH_SCALE                  0x1470
+#define RADEON_BRUSH_Y_X                    0x1474
+#define RADEON_BUS_CNTL                     0x0030
+#       define RADEON_BUS_MASTER_DIS         (1 << 6)
+#       define RADEON_BUS_BIOS_DIS_ROM       (1 << 12)
+#       define RADEON_BUS_RD_DISCARD_EN      (1 << 24)
+#       define RADEON_BUS_RD_ABORT_EN        (1 << 25)
+#       define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
+#       define RADEON_BUS_WRT_BURST          (1 << 29)
+#       define RADEON_BUS_READ_BURST         (1 << 30)
+#define RADEON_BUS_CNTL1                    0x0034
+#       define RADEON_BUS_WAIT_ON_LOCK_EN    (1 << 4)
+
+/* #define RADEON_PCIE_INDEX                   0x0030 */
+/* #define RADEON_PCIE_DATA                    0x0034 */
+#define RADEON_PCIE_LC_LINK_WIDTH_CNTL             0xa2 /* PCIE */
+#       define RADEON_PCIE_LC_LINK_WIDTH_SHIFT     0
+#       define RADEON_PCIE_LC_LINK_WIDTH_MASK      0x7
+#       define RADEON_PCIE_LC_LINK_WIDTH_X0        0
+#       define RADEON_PCIE_LC_LINK_WIDTH_X1        1
+#       define RADEON_PCIE_LC_LINK_WIDTH_X2        2
+#       define RADEON_PCIE_LC_LINK_WIDTH_X4        3
+#       define RADEON_PCIE_LC_LINK_WIDTH_X8        4
+#       define RADEON_PCIE_LC_LINK_WIDTH_X12       5
+#       define RADEON_PCIE_LC_LINK_WIDTH_X16       6
+#       define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT  4
+#       define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK   0x70
+#       define RADEON_PCIE_LC_RECONFIG_NOW         (1 << 8)
+#       define RADEON_PCIE_LC_RECONFIG_LATER       (1 << 9)
+#       define RADEON_PCIE_LC_SHORT_RECONFIG_EN    (1 << 10)
+
+#define RADEON_CACHE_CNTL                   0x1724
+#define RADEON_CACHE_LINE                   0x0f0c /* PCI */
+#define RADEON_CAPABILITIES_ID              0x0f50 /* PCI */
+#define RADEON_CAPABILITIES_PTR             0x0f34 /* PCI */
+#define RADEON_CLK_PIN_CNTL                 0x0001 /* PLL */
+#       define RADEON_DONT_USE_XTALIN       (1 << 4)
+#       define RADEON_SCLK_DYN_START_CNTL   (1 << 15)
+#define RADEON_CLOCK_CNTL_DATA              0x000c
+#define RADEON_CLOCK_CNTL_INDEX             0x0008
+#       define RADEON_PLL_WR_EN             (1 << 7)
+#       define RADEON_PLL_DIV_SEL           (3 << 8)
+#       define RADEON_PLL2_DIV_SEL_MASK     (~(3 << 8))
+#define RADEON_CLK_PWRMGT_CNTL              0x0014
+#       define RADEON_ENGIN_DYNCLK_MODE     (1 << 12)
+#       define RADEON_ACTIVE_HILO_LAT_MASK  (3 << 13)
+#       define RADEON_ACTIVE_HILO_LAT_SHIFT 13
+#       define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
+#       define RADEON_MC_BUSY               (1 << 16)
+#       define RADEON_DLL_READY             (1 << 19)
+#       define RADEON_CG_NO1_DEBUG_0        (1 << 24)
+#       define RADEON_CG_NO1_DEBUG_MASK     (0x1f << 24)
+#       define RADEON_DYN_STOP_MODE_MASK    (7 << 21)
+#       define RADEON_TVPLL_PWRMGT_OFF      (1 << 30)
+#       define RADEON_TVCLK_TURNOFF         (1 << 31)
+#define RADEON_PLL_PWRMGT_CNTL              0x0015 /* PLL */
+#       define RADEON_TCL_BYPASS_DISABLE    (1 << 20)
+#define RADEON_CLR_CMP_CLR_3D               0x1a24
+#define RADEON_CLR_CMP_CLR_DST              0x15c8
+#define RADEON_CLR_CMP_CLR_SRC              0x15c4
+#define RADEON_CLR_CMP_CNTL                 0x15c0
+#       define RADEON_SRC_CMP_EQ_COLOR      (4 <<  0)
+#       define RADEON_SRC_CMP_NEQ_COLOR     (5 <<  0)
+#       define RADEON_CLR_CMP_SRC_SOURCE    (1 << 24)
+#define RADEON_CLR_CMP_MASK                 0x15cc
+#       define RADEON_CLR_CMP_MSK           0xffffffff
+#define RADEON_CLR_CMP_MASK_3D              0x1A28
+#define RADEON_COMMAND                      0x0f04 /* PCI */
+#define RADEON_COMPOSITE_SHADOW_ID          0x1a0c
+#define RADEON_CONFIG_APER_0_BASE           0x0100
+#define RADEON_CONFIG_APER_1_BASE           0x0104
+#define RADEON_CONFIG_APER_SIZE             0x0108
+#define RADEON_CONFIG_BONDS                 0x00e8
+#define RADEON_CONFIG_CNTL                  0x00e0
+#       define RADEON_CFG_ATI_REV_A11       (0   << 16)
+#       define RADEON_CFG_ATI_REV_A12       (1   << 16)
+#       define RADEON_CFG_ATI_REV_A13       (2   << 16)
+#       define RADEON_CFG_ATI_REV_ID_MASK   (0xf << 16)
+#define RADEON_CONFIG_MEMSIZE               0x00f8
+#define RADEON_CONFIG_MEMSIZE_EMBEDDED      0x0114
+#define RADEON_CONFIG_REG_1_BASE            0x010c
+#define RADEON_CONFIG_REG_APER_SIZE         0x0110
+#define RADEON_CONFIG_XSTRAP                0x00e4
+#define RADEON_CONSTANT_COLOR_C             0x1d34
+#       define RADEON_CONSTANT_COLOR_MASK   0x00ffffff
+#       define RADEON_CONSTANT_COLOR_ONE    0x00ffffff
+#       define RADEON_CONSTANT_COLOR_ZERO   0x00000000
+#define RADEON_CRC_CMDFIFO_ADDR             0x0740
+#define RADEON_CRC_CMDFIFO_DOUT             0x0744
+#define RADEON_GRPH_BUFFER_CNTL             0x02f0
+#       define RADEON_GRPH_START_REQ_MASK          (0x7f)
+#       define RADEON_GRPH_START_REQ_SHIFT         0
+#       define RADEON_GRPH_STOP_REQ_MASK           (0x7f<<8)
+#       define RADEON_GRPH_STOP_REQ_SHIFT          8
+#       define RADEON_GRPH_CRITICAL_POINT_MASK     (0x7f<<16)
+#       define RADEON_GRPH_CRITICAL_POINT_SHIFT    16
+#       define RADEON_GRPH_CRITICAL_CNTL           (1<<28)
+#       define RADEON_GRPH_BUFFER_SIZE             (1<<29)
+#       define RADEON_GRPH_CRITICAL_AT_SOF         (1<<30)
+#       define RADEON_GRPH_STOP_CNTL               (1<<31)
+#define RADEON_GRPH2_BUFFER_CNTL            0x03f0
+#       define RADEON_GRPH2_START_REQ_MASK         (0x7f)
+#       define RADEON_GRPH2_START_REQ_SHIFT         0
+#       define RADEON_GRPH2_STOP_REQ_MASK          (0x7f<<8)
+#       define RADEON_GRPH2_STOP_REQ_SHIFT         8
+#       define RADEON_GRPH2_CRITICAL_POINT_MASK    (0x7f<<16)
+#       define RADEON_GRPH2_CRITICAL_POINT_SHIFT   16
+#       define RADEON_GRPH2_CRITICAL_CNTL          (1<<28)
+#       define RADEON_GRPH2_BUFFER_SIZE            (1<<29)
+#       define RADEON_GRPH2_CRITICAL_AT_SOF        (1<<30)
+#       define RADEON_GRPH2_STOP_CNTL              (1<<31)
+#define RADEON_CRTC_CRNT_FRAME              0x0214
+#define RADEON_CRTC_EXT_CNTL                0x0054
+#       define RADEON_CRTC_VGA_XOVERSCAN    (1 <<  0)
+#       define RADEON_VGA_ATI_LINEAR        (1 <<  3)
+#       define RADEON_XCRT_CNT_EN           (1 <<  6)
+#       define RADEON_CRTC_HSYNC_DIS        (1 <<  8)
+#       define RADEON_CRTC_VSYNC_DIS        (1 <<  9)
+#       define RADEON_CRTC_DISPLAY_DIS      (1 << 10)
+#       define RADEON_CRTC_SYNC_TRISTAT     (1 << 11)
+#       define RADEON_CRTC_CRT_ON           (1 << 15)
+#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE      0x0055
+#       define RADEON_CRTC_HSYNC_DIS_BYTE   (1 <<  0)
+#       define RADEON_CRTC_VSYNC_DIS_BYTE   (1 <<  1)
+#       define RADEON_CRTC_DISPLAY_DIS_BYTE (1 <<  2)
+#define RADEON_CRTC_GEN_CNTL                0x0050
+#       define RADEON_CRTC_DBL_SCAN_EN      (1 <<  0)
+#       define RADEON_CRTC_INTERLACE_EN     (1 <<  1)
+#       define RADEON_CRTC_CSYNC_EN         (1 <<  4)
+#       define RADEON_CRTC_ICON_EN          (1 << 15)
+#       define RADEON_CRTC_CUR_EN           (1 << 16)
+#       define RADEON_CRTC_CUR_MODE_MASK    (7 << 20)
+#       define RADEON_CRTC_CUR_MODE_SHIFT   20
+#       define RADEON_CRTC_CUR_MODE_MONO    0
+#       define RADEON_CRTC_CUR_MODE_24BPP   2
+#       define RADEON_CRTC_EXT_DISP_EN      (1 << 24)
+#       define RADEON_CRTC_EN               (1 << 25)
+#       define RADEON_CRTC_DISP_REQ_EN_B    (1 << 26)
+#define RADEON_CRTC2_GEN_CNTL               0x03f8
+#       define RADEON_CRTC2_DBL_SCAN_EN     (1 <<  0)
+#       define RADEON_CRTC2_INTERLACE_EN    (1 <<  1)
+#       define RADEON_CRTC2_SYNC_TRISTAT    (1 <<  4)
+#       define RADEON_CRTC2_HSYNC_TRISTAT   (1 <<  5)
+#       define RADEON_CRTC2_VSYNC_TRISTAT   (1 <<  6)
+#       define RADEON_CRTC2_CRT2_ON         (1 <<  7)
+#       define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
+#       define RADEON_CRTC2_PIX_WIDTH_MASK  (0xf << 8)
+#       define RADEON_CRTC2_ICON_EN         (1 << 15)
+#       define RADEON_CRTC2_CUR_EN          (1 << 16)
+#       define RADEON_CRTC2_CUR_MODE_MASK   (7 << 20)
+#       define RADEON_CRTC2_DISP_DIS        (1 << 23)
+#       define RADEON_CRTC2_EN              (1 << 25)
+#       define RADEON_CRTC2_DISP_REQ_EN_B   (1 << 26)
+#       define RADEON_CRTC2_CSYNC_EN        (1 << 27)
+#       define RADEON_CRTC2_HSYNC_DIS       (1 << 28)
+#       define RADEON_CRTC2_VSYNC_DIS       (1 << 29)
+#define RADEON_CRTC_MORE_CNTL               0x27c
+#       define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)
+#       define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)
+#       define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
+#       define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
+#define RADEON_CRTC_GUI_TRIG_VLINE          0x0218
+#define RADEON_CRTC_H_SYNC_STRT_WID         0x0204
+#       define RADEON_CRTC_H_SYNC_STRT_PIX        (0x07  <<  0)
+#       define RADEON_CRTC_H_SYNC_STRT_CHAR       (0x3ff <<  3)
+#       define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
+#       define RADEON_CRTC_H_SYNC_WID             (0x3f  << 16)
+#       define RADEON_CRTC_H_SYNC_WID_SHIFT       16
+#       define RADEON_CRTC_H_SYNC_POL             (1     << 23)
+#define RADEON_CRTC2_H_SYNC_STRT_WID        0x0304
+#       define RADEON_CRTC2_H_SYNC_STRT_PIX        (0x07  <<  0)
+#       define RADEON_CRTC2_H_SYNC_STRT_CHAR       (0x3ff <<  3)
+#       define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
+#       define RADEON_CRTC2_H_SYNC_WID             (0x3f  << 16)
+#       define RADEON_CRTC2_H_SYNC_WID_SHIFT       16
+#       define RADEON_CRTC2_H_SYNC_POL             (1     << 23)
+#define RADEON_CRTC_H_TOTAL_DISP            0x0200
+#       define RADEON_CRTC_H_TOTAL          (0x03ff << 0)
+#       define RADEON_CRTC_H_TOTAL_SHIFT    0
+#       define RADEON_CRTC_H_DISP           (0x01ff << 16)
+#       define RADEON_CRTC_H_DISP_SHIFT     16
+#define RADEON_CRTC2_H_TOTAL_DISP           0x0300
+#       define RADEON_CRTC2_H_TOTAL         (0x03ff << 0)
+#       define RADEON_CRTC2_H_TOTAL_SHIFT   0
+#       define RADEON_CRTC2_H_DISP          (0x01ff << 16)
+#       define RADEON_CRTC2_H_DISP_SHIFT    16
+
+#define RADEON_CRTC_OFFSET_RIGHT            0x0220
+#define RADEON_CRTC_OFFSET                  0x0224
+#       define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)
+#       define RADEON_CRTC_OFFSET__OFFSET_LOCK     (1<<31)
+
+#define RADEON_CRTC2_OFFSET                 0x0324
+#       define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)
+#       define RADEON_CRTC2_OFFSET__OFFSET_LOCK     (1<<31)
+#define RADEON_CRTC_OFFSET_CNTL             0x0228
+#       define RADEON_CRTC_TILE_LINE_SHIFT              0
+#       define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT        4
+#       define R300_CRTC_X_Y_MODE_EN_RIGHT              (1 << 6)
+#       define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK   (3 << 7)
+#       define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO   (0 << 7)
+#       define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)
+#       define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)
+#       define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS    (3 << 7)
+#       define R300_CRTC_X_Y_MODE_EN                    (1 << 9)
+#       define R300_CRTC_MICRO_TILE_BUFFER_MASK         (3 << 10)
+#       define R300_CRTC_MICRO_TILE_BUFFER_AUTO         (0 << 10)
+#       define R300_CRTC_MICRO_TILE_BUFFER_SINGLE       (1 << 10)
+#       define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE       (2 << 10)
+#       define R300_CRTC_MICRO_TILE_BUFFER_DIS          (3 << 10)
+#       define R300_CRTC_MICRO_TILE_EN_RIGHT            (1 << 12)
+#       define R300_CRTC_MICRO_TILE_EN                  (1 << 13)
+#       define R300_CRTC_MACRO_TILE_EN_RIGHT            (1 << 14)
+#       define R300_CRTC_MACRO_TILE_EN                  (1 << 15)
+#       define RADEON_CRTC_TILE_EN_RIGHT                (1 << 14)
+#       define RADEON_CRTC_TILE_EN                      (1 << 15)
+#       define RADEON_CRTC_OFFSET_FLIP_CNTL             (1 << 16)
+#       define RADEON_CRTC_STEREO_OFFSET_EN             (1 << 17)
+
+#define R300_CRTC_TILE_X0_Y0                0x0350
+#define R300_CRTC2_TILE_X0_Y0               0x0358
+
+#define RADEON_CRTC2_OFFSET_CNTL            0x0328
+#       define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)
+#       define RADEON_CRTC2_TILE_EN         (1 << 15)
+#define RADEON_CRTC_PITCH                   0x022c
+#       define RADEON_CRTC_PITCH__SHIFT          0
+#       define RADEON_CRTC_PITCH__RIGHT_SHIFT   16
+
+#define RADEON_CRTC2_PITCH                  0x032c
+#define RADEON_CRTC_STATUS                  0x005c
+#       define RADEON_CRTC_VBLANK_SAVE      (1 <<  1)
+#       define RADEON_CRTC_VBLANK_SAVE_CLEAR  (1 <<  1)
+#define RADEON_CRTC2_STATUS                  0x03fc
+#       define RADEON_CRTC2_VBLANK_SAVE      (1 <<  1)
+#       define RADEON_CRTC2_VBLANK_SAVE_CLEAR  (1 <<  1)
+#define RADEON_CRTC_V_SYNC_STRT_WID         0x020c
+#       define RADEON_CRTC_V_SYNC_STRT        (0x7ff <<  0)
+#       define RADEON_CRTC_V_SYNC_STRT_SHIFT  0
+#       define RADEON_CRTC_V_SYNC_WID         (0x1f  << 16)
+#       define RADEON_CRTC_V_SYNC_WID_SHIFT   16
+#       define RADEON_CRTC_V_SYNC_POL         (1     << 23)
+#define RADEON_CRTC2_V_SYNC_STRT_WID        0x030c
+#       define RADEON_CRTC2_V_SYNC_STRT       (0x7ff <<  0)
+#       define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
+#       define RADEON_CRTC2_V_SYNC_WID        (0x1f  << 16)
+#       define RADEON_CRTC2_V_SYNC_WID_SHIFT  16
+#       define RADEON_CRTC2_V_SYNC_POL        (1     << 23)
+#define RADEON_CRTC_V_TOTAL_DISP            0x0208
+#       define RADEON_CRTC_V_TOTAL          (0x07ff << 0)
+#       define RADEON_CRTC_V_TOTAL_SHIFT    0
+#       define RADEON_CRTC_V_DISP           (0x07ff << 16)
+#       define RADEON_CRTC_V_DISP_SHIFT     16
+#define RADEON_CRTC2_V_TOTAL_DISP           0x0308
+#       define RADEON_CRTC2_V_TOTAL         (0x07ff << 0)
+#       define RADEON_CRTC2_V_TOTAL_SHIFT   0
+#       define RADEON_CRTC2_V_DISP          (0x07ff << 16)
+#       define RADEON_CRTC2_V_DISP_SHIFT    16
+#define RADEON_CRTC_VLINE_CRNT_VLINE        0x0210
+#       define RADEON_CRTC_CRNT_VLINE_MASK  (0x7ff << 16)
+#define RADEON_CRTC2_CRNT_FRAME             0x0314
+#define RADEON_CRTC2_GUI_TRIG_VLINE         0x0318
+#define RADEON_CRTC2_STATUS                 0x03fc
+#define RADEON_CRTC2_VLINE_CRNT_VLINE       0x0310
+#define RADEON_CRTC8_DATA                   0x03d5 /* VGA, 0x3b5 */
+#define RADEON_CRTC8_IDX                    0x03d4 /* VGA, 0x3b4 */
+#define RADEON_CUR_CLR0                     0x026c
+#define RADEON_CUR_CLR1                     0x0270
+#define RADEON_CUR_HORZ_VERT_OFF            0x0268
+#define RADEON_CUR_HORZ_VERT_POSN           0x0264
+#define RADEON_CUR_OFFSET                   0x0260
+#       define RADEON_CUR_LOCK              (1 << 31)
+#define RADEON_CUR2_CLR0                    0x036c
+#define RADEON_CUR2_CLR1                    0x0370
+#define RADEON_CUR2_HORZ_VERT_OFF           0x0368
+#define RADEON_CUR2_HORZ_VERT_POSN          0x0364
+#define RADEON_CUR2_OFFSET                  0x0360
+#       define RADEON_CUR2_LOCK             (1 << 31)
+
+#define RADEON_DAC_CNTL                     0x0058
+#       define RADEON_DAC_RANGE_CNTL        (3 <<  0)
+#       define RADEON_DAC_RANGE_CNTL_PS2    (2 <<  0)
+#       define RADEON_DAC_RANGE_CNTL_MASK   0x03
+#       define RADEON_DAC_BLANKING          (1 <<  2)
+#       define RADEON_DAC_CMP_EN            (1 <<  3)
+#       define RADEON_DAC_CMP_OUTPUT        (1 <<  7)
+#       define RADEON_DAC_8BIT_EN           (1 <<  8)
+#       define RADEON_DAC_TVO_EN            (1 << 10)
+#       define RADEON_DAC_VGA_ADR_EN        (1 << 13)
+#       define RADEON_DAC_PDWN              (1 << 15)
+#       define RADEON_DAC_MASK_ALL          (0xff << 24)
+#define RADEON_DAC_CNTL2                    0x007c
+#       define RADEON_DAC2_TV_CLK_SEL       (0 <<  1)
+#       define RADEON_DAC2_DAC_CLK_SEL      (1 <<  0)
+#       define RADEON_DAC2_DAC2_CLK_SEL     (1 <<  1)
+#       define RADEON_DAC2_PALETTE_ACC_CTL  (1 <<  5)
+#       define RADEON_DAC2_CMP_EN           (1 <<  7)
+#       define RADEON_DAC2_CMP_OUT_R        (1 <<  8)
+#       define RADEON_DAC2_CMP_OUT_G        (1 <<  9)
+#       define RADEON_DAC2_CMP_OUT_B        (1 << 10)
+#       define RADEON_DAC2_CMP_OUTPUT       (1 << 11)
+#define RADEON_DAC_EXT_CNTL                 0x0280
+#       define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
+#       define RADEON_DAC2_FORCE_DATA_EN      (1 << 1)
+#       define RADEON_DAC_FORCE_BLANK_OFF_EN  (1 << 4)
+#       define RADEON_DAC_FORCE_DATA_EN       (1 << 5)
+#       define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
+#       define RADEON_DAC_FORCE_DATA_SEL_R    (0 << 6)
+#       define RADEON_DAC_FORCE_DATA_SEL_G    (1 << 6)
+#       define RADEON_DAC_FORCE_DATA_SEL_B    (2 << 6)
+#       define RADEON_DAC_FORCE_DATA_SEL_RGB  (3 << 6)
+#       define RADEON_DAC_FORCE_DATA_MASK   0x0003ff00
+#       define RADEON_DAC_FORCE_DATA_SHIFT  8
+#define RADEON_DAC_MACRO_CNTL               0x0d04
+#       define RADEON_DAC_PDWN_R            (1 << 16)
+#       define RADEON_DAC_PDWN_G            (1 << 17)
+#       define RADEON_DAC_PDWN_B            (1 << 18)
+#define RADEON_DISP_PWR_MAN                 0x0d08
+#       define RADEON_DISP_PWR_MAN_D3_CRTC_EN      (1 << 0)
+#       define RADEON_DISP_PWR_MAN_D3_CRTC2_EN     (1 << 4)
+#       define RADEON_DISP_PWR_MAN_DPMS_ON  (0 << 8)
+#       define RADEON_DISP_PWR_MAN_DPMS_STANDBY    (1 << 8)
+#       define RADEON_DISP_PWR_MAN_DPMS_SUSPEND    (2 << 8)
+#       define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8)
+#       define RADEON_DISP_D3_RST           (1 << 16)
+#       define RADEON_DISP_D3_REG_RST       (1 << 17)
+#       define RADEON_DISP_D3_GRPH_RST      (1 << 18)
+#       define RADEON_DISP_D3_SUBPIC_RST    (1 << 19)
+#       define RADEON_DISP_D3_OV0_RST       (1 << 20)
+#       define RADEON_DISP_D1D2_GRPH_RST    (1 << 21)
+#       define RADEON_DISP_D1D2_SUBPIC_RST  (1 << 22)
+#       define RADEON_DISP_D1D2_OV0_RST     (1 << 23)
+#       define RADEON_DIG_TMDS_ENABLE_RST   (1 << 24)
+#       define RADEON_TV_ENABLE_RST         (1 << 25)
+#       define RADEON_AUTO_PWRUP_EN         (1 << 26)
+#define RADEON_TV_DAC_CNTL                  0x088c
+#       define RADEON_TV_DAC_NBLANK         (1 << 0)
+#       define RADEON_TV_DAC_NHOLD          (1 << 1)
+#       define RADEON_TV_DAC_PEDESTAL       (1 <<  2)
+#       define RADEON_TV_MONITOR_DETECT_EN  (1 <<  4)
+#       define RADEON_TV_DAC_CMPOUT         (1 <<  5)
+#       define RADEON_TV_DAC_STD_MASK       (3 <<  8)
+#       define RADEON_TV_DAC_STD_PAL        (0 <<  8)
+#       define RADEON_TV_DAC_STD_NTSC       (1 <<  8)
+#       define RADEON_TV_DAC_STD_PS2        (2 <<  8)
+#       define RADEON_TV_DAC_STD_RS343      (3 <<  8)
+#       define RADEON_TV_DAC_BGSLEEP        (1 <<  6)
+#       define RADEON_TV_DAC_BGADJ_MASK     (0xf <<  16)
+#       define RADEON_TV_DAC_BGADJ_SHIFT    16
+#       define RADEON_TV_DAC_DACADJ_MASK    (0xf <<  20)
+#       define RADEON_TV_DAC_DACADJ_SHIFT   20
+#       define RADEON_TV_DAC_RDACPD         (1 <<  24)
+#       define RADEON_TV_DAC_GDACPD         (1 <<  25)
+#       define RADEON_TV_DAC_BDACPD         (1 <<  26)
+#       define RADEON_TV_DAC_RDACDET        (1 << 29)
+#       define RADEON_TV_DAC_GDACDET        (1 << 30)
+#       define RADEON_TV_DAC_BDACDET        (1 << 31)
+#       define R420_TV_DAC_DACADJ_MASK      (0x1f <<  20)
+#       define R420_TV_DAC_RDACPD           (1 <<  25)
+#       define R420_TV_DAC_GDACPD           (1 <<  26)
+#       define R420_TV_DAC_BDACPD           (1 <<  27)
+#       define R420_TV_DAC_TVENABLE         (1 <<  28)
+#define RADEON_DISP_HW_DEBUG                0x0d14
+#       define RADEON_CRT2_DISP1_SEL        (1 <<  5)
+#define RADEON_DISP_OUTPUT_CNTL             0x0d64
+#       define RADEON_DISP_DAC_SOURCE_MASK  0x03
+#       define RADEON_DISP_DAC2_SOURCE_MASK  0x0c
+#       define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
+#       define RADEON_DISP_DAC_SOURCE_RMX   0x02
+#       define RADEON_DISP_DAC_SOURCE_LTU   0x03
+#       define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
+#       define RADEON_DISP_TVDAC_SOURCE_MASK  (0x03 << 2)
+#       define RADEON_DISP_TVDAC_SOURCE_CRTC  0x0
+#       define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)
+#       define RADEON_DISP_TVDAC_SOURCE_RMX   (0x02 << 2)
+#       define RADEON_DISP_TVDAC_SOURCE_LTU   (0x03 << 2)
+#       define RADEON_DISP_TRANS_MATRIX_MASK  (0x03 << 4)
+#       define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)
+#       define RADEON_DISP_TRANS_MATRIX_GRAPHICS  (0x01 << 4)
+#       define RADEON_DISP_TRANS_MATRIX_VIDEO     (0x02 << 4)
+#       define RADEON_DISP_TV_SOURCE_CRTC   (1 << 16) /* crtc1 or crtc2 */
+#       define RADEON_DISP_TV_SOURCE_LTU    (0 << 16) /* linear transform unit */
+#define RADEON_DISP_TV_OUT_CNTL             0x0d6c
+#       define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)
+#       define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
+#define RADEON_DAC_CRC_SIG                  0x02cc
+#define RADEON_DAC_DATA                     0x03c9 /* VGA */
+#define RADEON_DAC_MASK                     0x03c6 /* VGA */
+#define RADEON_DAC_R_INDEX                  0x03c7 /* VGA */
+#define RADEON_DAC_W_INDEX                  0x03c8 /* VGA */
+#define RADEON_DDA_CONFIG                   0x02e0
+#define RADEON_DDA_ON_OFF                   0x02e4
+#define RADEON_DEFAULT_OFFSET               0x16e0
+#define RADEON_DEFAULT_PITCH                0x16e4
+#define RADEON_DEFAULT_SC_BOTTOM_RIGHT      0x16e8
+#       define RADEON_DEFAULT_SC_RIGHT_MAX  (0x1fff <<  0)
+#       define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
+#define RADEON_DESTINATION_3D_CLR_CMP_VAL   0x1820
+#define RADEON_DESTINATION_3D_CLR_CMP_MSK   0x1824
+#define RADEON_DEVICE_ID                    0x0f02 /* PCI */
+#define RADEON_DISP_MISC_CNTL               0x0d00
+#       define RADEON_SOFT_RESET_GRPH_PP    (1 << 0)
+#define RADEON_DISP_MERGE_CNTL            0x0d60
+#       define RADEON_DISP_ALPHA_MODE_MASK  0x03
+#       define RADEON_DISP_ALPHA_MODE_KEY   0
+#       define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
+#       define RADEON_DISP_ALPHA_MODE_GLOBAL 2
+#       define RADEON_DISP_RGB_OFFSET_EN    (1 << 8)
+#       define RADEON_DISP_GRPH_ALPHA_MASK  (0xff << 16)
+#       define RADEON_DISP_OV0_ALPHA_MASK   (0xff << 24)
+#       define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
+#define RADEON_DISP2_MERGE_CNTL             0x0d68
+#       define RADEON_DISP2_RGB_OFFSET_EN   (1 << 8)
+#define RADEON_DISP_LIN_TRANS_GRPH_A        0x0d80
+#define RADEON_DISP_LIN_TRANS_GRPH_B        0x0d84
+#define RADEON_DISP_LIN_TRANS_GRPH_C        0x0d88
+#define RADEON_DISP_LIN_TRANS_GRPH_D        0x0d8c
+#define RADEON_DISP_LIN_TRANS_GRPH_E        0x0d90
+#define RADEON_DISP_LIN_TRANS_GRPH_F        0x0d98
+#define RADEON_DP_BRUSH_BKGD_CLR            0x1478
+#define RADEON_DP_BRUSH_FRGD_CLR            0x147c
+#define RADEON_DP_CNTL                      0x16c0
+#       define RADEON_DST_X_LEFT_TO_RIGHT   (1 <<  0)
+#       define RADEON_DST_Y_TOP_TO_BOTTOM   (1 <<  1)
+#       define RADEON_DP_DST_TILE_LINEAR    (0 <<  3)
+#       define RADEON_DP_DST_TILE_MACRO     (1 <<  3)
+#       define RADEON_DP_DST_TILE_MICRO     (2 <<  3)
+#       define RADEON_DP_DST_TILE_BOTH      (3 <<  3)
+#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR     0x16d0
+#       define RADEON_DST_Y_MAJOR             (1 <<  2)
+#       define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
+#       define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
+#define RADEON_DP_DATATYPE                  0x16c4
+#       define RADEON_HOST_BIG_ENDIAN_EN    (1 << 29)
+#define RADEON_DP_GUI_MASTER_CNTL           0x146c
+#       define RADEON_GMC_SRC_PITCH_OFFSET_CNTL   (1    <<  0)
+#       define RADEON_GMC_DST_PITCH_OFFSET_CNTL   (1    <<  1)
+#       define RADEON_GMC_SRC_CLIPPING            (1    <<  2)
+#       define RADEON_GMC_DST_CLIPPING            (1    <<  3)
+#       define RADEON_GMC_BRUSH_DATATYPE_MASK     (0x0f <<  4)
+#       define RADEON_GMC_BRUSH_8X8_MONO_FG_BG    (0    <<  4)
+#       define RADEON_GMC_BRUSH_8X8_MONO_FG_LA    (1    <<  4)
+#       define RADEON_GMC_BRUSH_1X8_MONO_FG_BG    (4    <<  4)
+#       define RADEON_GMC_BRUSH_1X8_MONO_FG_LA    (5    <<  4)
+#       define RADEON_GMC_BRUSH_32x1_MONO_FG_BG   (6    <<  4)
+#       define RADEON_GMC_BRUSH_32x1_MONO_FG_LA   (7    <<  4)
+#       define RADEON_GMC_BRUSH_32x32_MONO_FG_BG  (8    <<  4)
+#       define RADEON_GMC_BRUSH_32x32_MONO_FG_LA  (9    <<  4)
+#       define RADEON_GMC_BRUSH_8x8_COLOR         (10   <<  4)
+#       define RADEON_GMC_BRUSH_1X8_COLOR         (12   <<  4)
+#       define RADEON_GMC_BRUSH_SOLID_COLOR       (13   <<  4)
+#       define RADEON_GMC_BRUSH_NONE              (15   <<  4)
+#       define RADEON_GMC_DST_8BPP_CI             (2    <<  8)
+#       define RADEON_GMC_DST_15BPP               (3    <<  8)
+#       define RADEON_GMC_DST_16BPP               (4    <<  8)
+#       define RADEON_GMC_DST_24BPP               (5    <<  8)
+#       define RADEON_GMC_DST_32BPP               (6    <<  8)
+#       define RADEON_GMC_DST_8BPP_RGB            (7    <<  8)
+#       define RADEON_GMC_DST_Y8                  (8    <<  8)
+#       define RADEON_GMC_DST_RGB8                (9    <<  8)
+#       define RADEON_GMC_DST_VYUY                (11   <<  8)
+#       define RADEON_GMC_DST_YVYU                (12   <<  8)
+#       define RADEON_GMC_DST_AYUV444             (14   <<  8)
+#       define RADEON_GMC_DST_ARGB4444            (15   <<  8)
+#       define RADEON_GMC_DST_DATATYPE_MASK       (0x0f <<  8)
+#       define RADEON_GMC_DST_DATATYPE_SHIFT      8
+#       define RADEON_GMC_SRC_DATATYPE_MASK       (3    << 12)
+#       define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0    << 12)
+#       define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1    << 12)
+#       define RADEON_GMC_SRC_DATATYPE_COLOR      (3    << 12)
+#       define RADEON_GMC_BYTE_PIX_ORDER          (1    << 14)
+#       define RADEON_GMC_BYTE_MSB_TO_LSB         (0    << 14)
+#       define RADEON_GMC_BYTE_LSB_TO_MSB         (1    << 14)
+#       define RADEON_GMC_CONVERSION_TEMP         (1    << 15)
+#       define RADEON_GMC_CONVERSION_TEMP_6500    (0    << 15)
+#       define RADEON_GMC_CONVERSION_TEMP_9300    (1    << 15)
+#       define RADEON_GMC_ROP3_MASK               (0xff << 16)
+#       define RADEON_DP_SRC_SOURCE_MASK          (7    << 24)
+#       define RADEON_DP_SRC_SOURCE_MEMORY        (2    << 24)
+#       define RADEON_DP_SRC_SOURCE_HOST_DATA     (3    << 24)
+#       define RADEON_GMC_3D_FCN_EN               (1    << 27)
+#       define RADEON_GMC_CLR_CMP_CNTL_DIS        (1    << 28)
+#       define RADEON_GMC_AUX_CLIP_DIS            (1    << 29)
+#       define RADEON_GMC_WR_MSK_DIS              (1    << 30)
+#       define RADEON_GMC_LD_BRUSH_Y_X            (1    << 31)
+#       define RADEON_ROP3_ZERO             0x00000000
+#       define RADEON_ROP3_DSa              0x00880000
+#       define RADEON_ROP3_SDna             0x00440000
+#       define RADEON_ROP3_S                0x00cc0000
+#       define RADEON_ROP3_DSna             0x00220000
+#       define RADEON_ROP3_D                0x00aa0000
+#       define RADEON_ROP3_DSx              0x00660000
+#       define RADEON_ROP3_DSo              0x00ee0000
+#       define RADEON_ROP3_DSon             0x00110000
+#       define RADEON_ROP3_DSxn             0x00990000
+#       define RADEON_ROP3_Dn               0x00550000
+#       define RADEON_ROP3_SDno             0x00dd0000
+#       define RADEON_ROP3_Sn               0x00330000
+#       define RADEON_ROP3_DSno             0x00bb0000
+#       define RADEON_ROP3_DSan             0x00770000
+#       define RADEON_ROP3_ONE              0x00ff0000
+#       define RADEON_ROP3_DPa              0x00a00000
+#       define RADEON_ROP3_PDna             0x00500000
+#       define RADEON_ROP3_P                0x00f00000
+#       define RADEON_ROP3_DPna             0x000a0000
+#       define RADEON_ROP3_D                0x00aa0000
+#       define RADEON_ROP3_DPx              0x005a0000
+#       define RADEON_ROP3_DPo              0x00fa0000
+#       define RADEON_ROP3_DPon             0x00050000
+#       define RADEON_ROP3_PDxn             0x00a50000
+#       define RADEON_ROP3_PDno             0x00f50000
+#       define RADEON_ROP3_Pn               0x000f0000
+#       define RADEON_ROP3_DPno             0x00af0000
+#       define RADEON_ROP3_DPan             0x005f0000
+#define RADEON_DP_GUI_MASTER_CNTL_C         0x1c84
+#define RADEON_DP_MIX                       0x16c8
+#define RADEON_DP_SRC_BKGD_CLR              0x15dc
+#define RADEON_DP_SRC_FRGD_CLR              0x15d8
+#define RADEON_DP_WRITE_MASK                0x16cc
+#define RADEON_DST_BRES_DEC                 0x1630
+#define RADEON_DST_BRES_ERR                 0x1628
+#define RADEON_DST_BRES_INC                 0x162c
+#define RADEON_DST_BRES_LNTH                0x1634
+#define RADEON_DST_BRES_LNTH_SUB            0x1638
+#define RADEON_DST_HEIGHT                   0x1410
+#define RADEON_DST_HEIGHT_WIDTH             0x143c
+#define RADEON_DST_HEIGHT_WIDTH_8           0x158c
+#define RADEON_DST_HEIGHT_WIDTH_BW          0x15b4
+#define RADEON_DST_HEIGHT_Y                 0x15a0
+#define RADEON_DST_LINE_START               0x1600
+#define RADEON_DST_LINE_END                 0x1604
+#define RADEON_DST_LINE_PATCOUNT            0x1608
+#       define RADEON_BRES_CNTL_SHIFT       8
+#define RADEON_DST_OFFSET                   0x1404
+#define RADEON_DST_PITCH                    0x1408
+#define RADEON_DST_PITCH_OFFSET             0x142c
+#define RADEON_DST_PITCH_OFFSET_C           0x1c80
+#       define RADEON_PITCH_SHIFT           21
+#       define RADEON_DST_TILE_LINEAR       (0 << 30)
+#       define RADEON_DST_TILE_MACRO        (1 << 30)
+#       define RADEON_DST_TILE_MICRO        (2 << 30)
+#       define RADEON_DST_TILE_BOTH         (3 << 30)
+#define RADEON_DST_WIDTH                    0x140c
+#define RADEON_DST_WIDTH_HEIGHT             0x1598
+#define RADEON_DST_WIDTH_X                  0x1588
+#define RADEON_DST_WIDTH_X_INCY             0x159c
+#define RADEON_DST_X                        0x141c
+#define RADEON_DST_X_SUB                    0x15a4
+#define RADEON_DST_X_Y                      0x1594
+#define RADEON_DST_Y                        0x1420
+#define RADEON_DST_Y_SUB                    0x15a8
+#define RADEON_DST_Y_X                      0x1438
+
+#define RADEON_FCP_CNTL                     0x0910
+#      define RADEON_FCP0_SRC_PCICLK             0
+#      define RADEON_FCP0_SRC_PCLK               1
+#      define RADEON_FCP0_SRC_PCLKb              2
+#      define RADEON_FCP0_SRC_HREF               3
+#      define RADEON_FCP0_SRC_GND                4
+#      define RADEON_FCP0_SRC_HREFb              5
+#define RADEON_FLUSH_1                      0x1704
+#define RADEON_FLUSH_2                      0x1708
+#define RADEON_FLUSH_3                      0x170c
+#define RADEON_FLUSH_4                      0x1710
+#define RADEON_FLUSH_5                      0x1714
+#define RADEON_FLUSH_6                      0x1718
+#define RADEON_FLUSH_7                      0x171c
+#define RADEON_FOG_3D_TABLE_START           0x1810
+#define RADEON_FOG_3D_TABLE_END             0x1814
+#define RADEON_FOG_3D_TABLE_DENSITY         0x181c
+#define RADEON_FOG_TABLE_INDEX              0x1a14
+#define RADEON_FOG_TABLE_DATA               0x1a18
+#define RADEON_FP_CRTC_H_TOTAL_DISP         0x0250
+#define RADEON_FP_CRTC_V_TOTAL_DISP         0x0254
+#       define RADEON_FP_CRTC_H_TOTAL_MASK      0x000003ff
+#       define RADEON_FP_CRTC_H_DISP_MASK       0x01ff0000
+#       define RADEON_FP_CRTC_V_TOTAL_MASK      0x00000fff
+#       define RADEON_FP_CRTC_V_DISP_MASK       0x0fff0000
+#       define RADEON_FP_H_SYNC_STRT_CHAR_MASK  0x00001ff8
+#       define RADEON_FP_H_SYNC_WID_MASK        0x003f0000
+#       define RADEON_FP_V_SYNC_STRT_MASK       0x00000fff
+#       define RADEON_FP_V_SYNC_WID_MASK        0x001f0000
+#       define RADEON_FP_CRTC_H_TOTAL_SHIFT     0x00000000
+#       define RADEON_FP_CRTC_H_DISP_SHIFT      0x00000010
+#       define RADEON_FP_CRTC_V_TOTAL_SHIFT     0x00000000
+#       define RADEON_FP_CRTC_V_DISP_SHIFT      0x00000010
+#       define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
+#       define RADEON_FP_H_SYNC_WID_SHIFT       0x00000010
+#       define RADEON_FP_V_SYNC_STRT_SHIFT      0x00000000
+#       define RADEON_FP_V_SYNC_WID_SHIFT       0x00000010
+#define RADEON_FP_GEN_CNTL                  0x0284
+#       define RADEON_FP_FPON                  (1 <<  0)
+#       define RADEON_FP_BLANK_EN              (1 <<  1)
+#       define RADEON_FP_TMDS_EN               (1 <<  2)
+#       define RADEON_FP_PANEL_FORMAT          (1 <<  3)
+#       define RADEON_FP_EN_TMDS               (1 <<  7)
+#       define RADEON_FP_DETECT_SENSE          (1 <<  8)
+#       define R200_FP_SOURCE_SEL_MASK         (3 <<  10)
+#       define R200_FP_SOURCE_SEL_CRTC1        (0 <<  10)
+#       define R200_FP_SOURCE_SEL_CRTC2        (1 <<  10)
+#       define R200_FP_SOURCE_SEL_RMX          (2 <<  10)
+#       define R200_FP_SOURCE_SEL_TRANS        (3 <<  10)
+#       define RADEON_FP_SEL_CRTC1             (0 << 13)
+#       define RADEON_FP_SEL_CRTC2             (1 << 13)
+#       define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
+#       define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
+#       define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
+#       define RADEON_FP_CRTC_USE_SHADOW_VEND  (1 << 18)
+#       define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
+#       define RADEON_FP_DFP_SYNC_SEL          (1 << 21)
+#       define RADEON_FP_CRTC_LOCK_8DOT        (1 << 22)
+#       define RADEON_FP_CRT_SYNC_SEL          (1 << 23)
+#       define RADEON_FP_USE_SHADOW_EN         (1 << 24)
+#       define RADEON_FP_CRT_SYNC_ALT          (1 << 26)
+#define RADEON_FP2_GEN_CNTL                 0x0288
+#       define RADEON_FP2_BLANK_EN             (1 <<  1)
+#       define RADEON_FP2_ON                   (1 <<  2)
+#       define RADEON_FP2_PANEL_FORMAT         (1 <<  3)
+#       define RADEON_FP2_DETECT_SENSE         (1 <<  8)
+#       define R200_FP2_SOURCE_SEL_MASK        (3 << 10)
+#       define R200_FP2_SOURCE_SEL_CRTC1       (0 << 10)
+#       define R200_FP2_SOURCE_SEL_CRTC2       (1 << 10)
+#       define R200_FP2_SOURCE_SEL_RMX         (2 << 10)
+#       define R200_FP2_SOURCE_SEL_TRANS_UNIT  (3 << 10)
+#       define RADEON_FP2_SRC_SEL_MASK         (3 << 13)
+#       define RADEON_FP2_SRC_SEL_CRTC2        (1 << 13)
+#       define RADEON_FP2_FP_POL               (1 << 16)
+#       define RADEON_FP2_LP_POL               (1 << 17)
+#       define RADEON_FP2_SCK_POL              (1 << 18)
+#       define RADEON_FP2_LCD_CNTL_MASK        (7 << 19)
+#       define RADEON_FP2_PAD_FLOP_EN          (1 << 22)
+#       define RADEON_FP2_CRC_EN               (1 << 23)
+#       define RADEON_FP2_CRC_READ_EN          (1 << 24)
+#       define RADEON_FP2_DVO_EN               (1 << 25)
+#       define RADEON_FP2_DVO_RATE_SEL_SDR     (1 << 26)
+#       define R200_FP2_DVO_RATE_SEL_SDR       (1 << 27)
+#       define R300_FP2_DVO_CLOCK_MODE_SINGLE  (1 << 28)
+#       define R300_FP2_DVO_DUAL_CHANNEL_EN    (1 << 29)
+#define RADEON_FP_H_SYNC_STRT_WID           0x02c4
+#define RADEON_FP_H2_SYNC_STRT_WID          0x03c4
+#define RADEON_FP_HORZ_STRETCH              0x028c
+#define RADEON_FP_HORZ2_STRETCH             0x038c
+#       define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
+#       define RADEON_HORZ_STRETCH_RATIO_MAX  4096
+#       define RADEON_HORZ_PANEL_SIZE         (0x1ff   << 16)
+#       define RADEON_HORZ_PANEL_SHIFT        16
+#       define RADEON_HORZ_STRETCH_PIXREP     (0      << 25)
+#       define RADEON_HORZ_STRETCH_BLEND      (1      << 26)
+#       define RADEON_HORZ_STRETCH_ENABLE     (1      << 25)
+#       define RADEON_HORZ_AUTO_RATIO         (1      << 27)
+#       define RADEON_HORZ_FP_LOOP_STRETCH    (0x7    << 28)
+#       define RADEON_HORZ_AUTO_RATIO_INC     (1      << 31)
+#define RADEON_FP_HORZ_VERT_ACTIVE          0x0278
+#define RADEON_FP_V_SYNC_STRT_WID           0x02c8
+#define RADEON_FP_VERT_STRETCH              0x0290
+#define RADEON_FP_V2_SYNC_STRT_WID          0x03c8
+#define RADEON_FP_VERT2_STRETCH             0x0390
+#       define RADEON_VERT_PANEL_SIZE          (0xfff << 12)
+#       define RADEON_VERT_PANEL_SHIFT         12
+#       define RADEON_VERT_STRETCH_RATIO_MASK  0xfff
+#       define RADEON_VERT_STRETCH_RATIO_SHIFT 0
+#       define RADEON_VERT_STRETCH_RATIO_MAX   4096
+#       define RADEON_VERT_STRETCH_ENABLE      (1     << 25)
+#       define RADEON_VERT_STRETCH_LINEREP     (0     << 26)
+#       define RADEON_VERT_STRETCH_BLEND       (1     << 26)
+#       define RADEON_VERT_AUTO_RATIO_EN       (1     << 27)
+#       define RADEON_VERT_AUTO_RATIO_INC      (1     << 31)
+#       define RADEON_VERT_STRETCH_RESERVED    0x71000000
+#define RS400_FP_2ND_GEN_CNTL               0x0384
+#       define RS400_FP_2ND_ON              (1 << 0)
+#       define RS400_FP_2ND_BLANK_EN        (1 << 1)
+#       define RS400_TMDS_2ND_EN            (1 << 2)
+#       define RS400_PANEL_FORMAT_2ND       (1 << 3)
+#       define RS400_FP_2ND_EN_TMDS         (1 << 7)
+#       define RS400_FP_2ND_DETECT_SENSE    (1 << 8)
+#       define RS400_FP_2ND_SOURCE_SEL_MASK        (3 << 10)
+#       define RS400_FP_2ND_SOURCE_SEL_CRTC1       (0 << 10)
+#       define RS400_FP_2ND_SOURCE_SEL_CRTC2       (1 << 10)
+#       define RS400_FP_2ND_SOURCE_SEL_RMX         (2 << 10)
+#       define RS400_FP_2ND_DETECT_EN       (1 << 12)
+#       define RS400_HPD_2ND_SEL            (1 << 13)
+#define RS400_FP2_2_GEN_CNTL                0x0388
+#       define RS400_FP2_2_BLANK_EN         (1 << 1)
+#       define RS400_FP2_2_ON               (1 << 2)
+#       define RS400_FP2_2_PANEL_FORMAT     (1 << 3)
+#       define RS400_FP2_2_DETECT_SENSE     (1 << 8)
+#       define RS400_FP2_2_SOURCE_SEL_MASK        (3 << 10)
+#       define RS400_FP2_2_SOURCE_SEL_CRTC1       (0 << 10)
+#       define RS400_FP2_2_SOURCE_SEL_CRTC2       (1 << 10)
+#       define RS400_FP2_2_SOURCE_SEL_RMX         (2 << 10)
+#       define RS400_FP2_2_DVO2_EN          (1 << 25)
+#define RS400_TMDS2_CNTL                    0x0394
+#define RS400_TMDS2_TRANSMITTER_CNTL        0x03a4
+#       define RS400_TMDS2_PLLEN            (1 << 0)
+#       define RS400_TMDS2_PLLRST           (1 << 1)
+
+#define RADEON_GEN_INT_CNTL                 0x0040
+#       define RADEON_SW_INT_ENABLE             (1 << 25)
+#define RADEON_GEN_INT_STATUS               0x0044
+#       define RADEON_VSYNC_INT_AK          (1 <<  2)
+#       define RADEON_VSYNC_INT             (1 <<  2)
+#       define RADEON_VSYNC2_INT_AK         (1 <<  6)
+#       define RADEON_VSYNC2_INT            (1 <<  6)
+#       define RADEON_SW_INT_FIRE               (1 << 26)
+#       define RADEON_SW_INT_TEST               (1 << 25)
+#       define RADEON_SW_INT_TEST_ACK           (1 << 25)
+#define RADEON_GENENB                       0x03c3 /* VGA */
+#define RADEON_GENFC_RD                     0x03ca /* VGA */
+#define RADEON_GENFC_WT                     0x03da /* VGA, 0x03ba */
+#define RADEON_GENMO_RD                     0x03cc /* VGA */
+#define RADEON_GENMO_WT                     0x03c2 /* VGA */
+#define RADEON_GENS0                        0x03c2 /* VGA */
+#define RADEON_GENS1                        0x03da /* VGA, 0x03ba */
+#define RADEON_GPIO_MONID                   0x0068 /* DDC interface via I2C */ /* DDC3 */
+#define RADEON_GPIO_MONIDB                  0x006c
+#define RADEON_GPIO_CRT2_DDC                0x006c
+#define RADEON_GPIO_DVI_DDC                 0x0064 /* DDC2 */
+#define RADEON_GPIO_VGA_DDC                 0x0060 /* DDC1 */
+#       define RADEON_GPIO_A_0              (1 <<  0)
+#       define RADEON_GPIO_A_1              (1 <<  1)
+#       define RADEON_GPIO_Y_0              (1 <<  8)
+#       define RADEON_GPIO_Y_1              (1 <<  9)
+#       define RADEON_GPIO_Y_SHIFT_0        8
+#       define RADEON_GPIO_Y_SHIFT_1        9
+#       define RADEON_GPIO_EN_0             (1 << 16)
+#       define RADEON_GPIO_EN_1             (1 << 17)
+#       define RADEON_GPIO_MASK_0           (1 << 24) /*??*/
+#       define RADEON_GPIO_MASK_1           (1 << 25) /*??*/
+#define RADEON_GRPH8_DATA                   0x03cf /* VGA */
+#define RADEON_GRPH8_IDX                    0x03ce /* VGA */
+#define RADEON_GUI_SCRATCH_REG0             0x15e0
+#define RADEON_GUI_SCRATCH_REG1             0x15e4
+#define RADEON_GUI_SCRATCH_REG2             0x15e8
+#define RADEON_GUI_SCRATCH_REG3             0x15ec
+#define RADEON_GUI_SCRATCH_REG4             0x15f0
+#define RADEON_GUI_SCRATCH_REG5             0x15f4
+
+#define RADEON_HEADER                       0x0f0e /* PCI */
+#define RADEON_HOST_DATA0                   0x17c0
+#define RADEON_HOST_DATA1                   0x17c4
+#define RADEON_HOST_DATA2                   0x17c8
+#define RADEON_HOST_DATA3                   0x17cc
+#define RADEON_HOST_DATA4                   0x17d0
+#define RADEON_HOST_DATA5                   0x17d4
+#define RADEON_HOST_DATA6                   0x17d8
+#define RADEON_HOST_DATA7                   0x17dc
+#define RADEON_HOST_DATA_LAST               0x17e0
+#define RADEON_HOST_PATH_CNTL               0x0130
+#       define RADEON_HP_LIN_RD_CACHE_DIS   (1 << 24)
+#       define RADEON_HDP_READ_BUFFER_INVALIDATE   (1 << 27)
+#       define RADEON_HDP_SOFT_RESET        (1 << 26)
+#       define RADEON_HDP_APER_CNTL         (1 << 23)
+#define RADEON_HTOTAL_CNTL                  0x0009 /* PLL */
+#       define RADEON_HTOT_CNTL_VGA_EN      (1 << 28)
+#define RADEON_HTOTAL2_CNTL                 0x002e /* PLL */
+
+       /* Multimedia I2C bus */
+#define RADEON_I2C_CNTL_0                   0x0090
+#define RADEON_I2C_DONE (1<<0)
+#define RADEON_I2C_NACK (1<<1)
+#define RADEON_I2C_HALT (1<<2)
+#define RADEON_I2C_SOFT_RST (1<<5)
+#define RADEON_I2C_DRIVE_EN (1<<6)
+#define RADEON_I2C_DRIVE_SEL (1<<7)
+#define RADEON_I2C_START (1<<8)
+#define RADEON_I2C_STOP (1<<9)
+#define RADEON_I2C_RECEIVE (1<<10)
+#define RADEON_I2C_ABORT (1<<11)
+#define RADEON_I2C_GO (1<<12)
+#define RADEON_I2C_CNTL_1                   0x0094
+#define RADEON_I2C_SEL         (1<<16)
+#define RADEON_I2C_EN          (1<<17)
+#define RADEON_I2C_DATA                     0x0098
+
+#define RADEON_DVI_I2C_CNTL_0               0x02e0
+#       define R200_DVI_I2C_PIN_SEL(x)      ((x) << 3)
+#       define R200_SEL_DDC1                0 /* 0x60 - VGA_DDC */
+#       define R200_SEL_DDC2                1 /* 0x64 - DVI_DDC */
+#       define R200_SEL_DDC3                2 /* 0x68 - MONID_DDC */
+#define RADEON_DVI_I2C_CNTL_1               0x02e4 /* ? */
+#define RADEON_DVI_I2C_DATA                 0x02e8
+
+#define RADEON_INTERRUPT_LINE               0x0f3c /* PCI */
+#define RADEON_INTERRUPT_PIN                0x0f3d /* PCI */
+#define RADEON_IO_BASE                      0x0f14 /* PCI */
+
+#define RADEON_LATENCY                      0x0f0d /* PCI */
+#define RADEON_LEAD_BRES_DEC                0x1608
+#define RADEON_LEAD_BRES_LNTH               0x161c
+#define RADEON_LEAD_BRES_LNTH_SUB           0x1624
+#define RADEON_LVDS_GEN_CNTL                0x02d0
+#       define RADEON_LVDS_ON               (1   <<  0)
+#       define RADEON_LVDS_DISPLAY_DIS      (1   <<  1)
+#       define RADEON_LVDS_PANEL_TYPE       (1   <<  2)
+#       define RADEON_LVDS_PANEL_FORMAT     (1   <<  3)
+#       define RADEON_LVDS_NO_FM            (0   <<  4)
+#       define RADEON_LVDS_2_GREY           (1   <<  4)
+#       define RADEON_LVDS_4_GREY           (2   <<  4)
+#       define RADEON_LVDS_RST_FM           (1   <<  6)
+#       define RADEON_LVDS_EN               (1   <<  7)
+#       define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
+#       define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
+#       define RADEON_LVDS_BL_MOD_EN        (1   << 16)
+#       define RADEON_LVDS_BL_CLK_SEL       (1   << 17)
+#       define RADEON_LVDS_DIGON            (1   << 18)
+#       define RADEON_LVDS_BLON             (1   << 19)
+#       define RADEON_LVDS_FP_POL_LOW       (1   << 20)
+#       define RADEON_LVDS_LP_POL_LOW       (1   << 21)
+#       define RADEON_LVDS_DTM_POL_LOW      (1   << 22)
+#       define RADEON_LVDS_SEL_CRTC2        (1   << 23)
+#       define RADEON_LVDS_FPDI_EN          (1   << 27)
+#       define RADEON_LVDS_HSYNC_DELAY_SHIFT        28
+#define RADEON_LVDS_PLL_CNTL                0x02d4
+#       define RADEON_HSYNC_DELAY_SHIFT     28
+#       define RADEON_HSYNC_DELAY_MASK      (0xf << 28)
+#       define RADEON_LVDS_PLL_EN           (1   << 16)
+#       define RADEON_LVDS_PLL_RESET        (1   << 17)
+#       define R300_LVDS_SRC_SEL_MASK       (3   << 18)
+#       define R300_LVDS_SRC_SEL_CRTC1      (0   << 18)
+#       define R300_LVDS_SRC_SEL_CRTC2      (1   << 18)
+#       define R300_LVDS_SRC_SEL_RMX        (2   << 18)
+#define RADEON_LVDS_SS_GEN_CNTL             0x02ec
+#       define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT     16
+#       define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT     20
+
+#define RADEON_MAX_LATENCY                  0x0f3f /* PCI */
+#define RADEON_DISPLAY_BASE_ADDR            0x23c
+#define RADEON_DISPLAY2_BASE_ADDR           0x33c
+#define RADEON_OV0_BASE_ADDR                0x43c
+#define RADEON_NB_TOM                       0x15c
+#define R300_MC_INIT_MISC_LAT_TIMER         0x180
+#       define R300_MC_DISP0R_INIT_LAT_SHIFT 8
+#       define R300_MC_DISP0R_INIT_LAT_MASK  0xf
+#       define R300_MC_DISP1R_INIT_LAT_SHIFT 12
+#       define R300_MC_DISP1R_INIT_LAT_MASK  0xf
+#define RADEON_MCLK_CNTL                    0x0012 /* PLL */
+#       define RADEON_MCLKA_SRC_SEL_MASK    0x7
+#       define RADEON_FORCEON_MCLKA         (1 << 16)
+#       define RADEON_FORCEON_MCLKB         (1 << 17)
+#       define RADEON_FORCEON_YCLKA         (1 << 18)
+#       define RADEON_FORCEON_YCLKB         (1 << 19)
+#       define RADEON_FORCEON_MC            (1 << 20)
+#       define RADEON_FORCEON_AIC           (1 << 21)
+#       define R300_DISABLE_MC_MCLKA        (1 << 21)
+#       define R300_DISABLE_MC_MCLKB        (1 << 21)
+#define RADEON_MCLK_MISC                    0x001f /* PLL */
+#       define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)
+#       define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)
+#       define RADEON_MC_MCLK_DYN_ENABLE    (1 << 14)
+#       define RADEON_IO_MCLK_DYN_ENABLE    (1 << 15)
+#define RADEON_LCD_GPIO_MASK                0x01a0
+#define RADEON_GPIOPAD_EN                   0x01a0
+#define RADEON_LCD_GPIO_Y_REG               0x01a4
+#define RADEON_MDGPIO_A_REG                 0x01ac
+#define RADEON_MDGPIO_EN_REG                0x01b0
+#define RADEON_MDGPIO_MASK                  0x0198
+#define RADEON_GPIOPAD_MASK                 0x0198
+#define RADEON_GPIOPAD_A                    0x019c
+#define RADEON_MDGPIO_Y_REG                 0x01b4
+#define RADEON_MEM_ADDR_CONFIG              0x0148
+#define RADEON_MEM_BASE                     0x0f10 /* PCI */
+#define RADEON_MEM_CNTL                     0x0140
+#       define RADEON_MEM_NUM_CHANNELS_MASK 0x01
+#       define RADEON_MEM_USE_B_CH_ONLY     (1 <<  1)
+#       define RV100_HALF_MODE              (1 <<  3)
+#       define R300_MEM_NUM_CHANNELS_MASK   0x03
+#       define R300_MEM_USE_CD_CH_ONLY      (1 <<  2)
+#define RADEON_MEM_TIMING_CNTL              0x0144 /* EXT_MEM_CNTL */
+#define RADEON_MEM_INIT_LAT_TIMER           0x0154
+#define RADEON_MEM_INTF_CNTL                0x014c
+#define RADEON_MEM_SDRAM_MODE_REG           0x0158
+#       define RADEON_SDRAM_MODE_MASK       0xffff0000
+#       define RADEON_B3MEM_RESET_MASK      0x6fffffff
+#       define RADEON_MEM_CFG_TYPE_DDR      (1 << 30)
+#define RADEON_MEM_STR_CNTL                 0x0150
+#       define RADEON_MEM_PWRUP_COMPL_A     (1 <<  0)
+#       define RADEON_MEM_PWRUP_COMPL_B     (1 <<  1)
+#       define R300_MEM_PWRUP_COMPL_C       (1 <<  2)
+#       define R300_MEM_PWRUP_COMPL_D       (1 <<  3)
+#       define RADEON_MEM_PWRUP_COMPLETE    0x03
+#       define R300_MEM_PWRUP_COMPLETE      0x0f
+#define RADEON_MC_STATUS                    0x0150
+#       define RADEON_MC_IDLE               (1 << 2)
+#       define R300_MC_IDLE                 (1 << 4)
+#define RADEON_MEM_VGA_RP_SEL               0x003c
+#define RADEON_MEM_VGA_WP_SEL               0x0038
+#define RADEON_MIN_GRANT                    0x0f3e /* PCI */
+#define RADEON_MM_DATA                      0x0004
+#define RADEON_MM_INDEX                     0x0000
+#       define RADEON_MM_APER           (1 << 31)
+#define RADEON_MPLL_CNTL                    0x000e /* PLL */
+#define RADEON_MPP_TB_CONFIG                0x01c0 /* ? */
+#define RADEON_MPP_GP_CONFIG                0x01c8 /* ? */
+#define RADEON_SEPROM_CNTL1                 0x01c0
+#       define RADEON_SCK_PRESCALE_SHIFT    24
+#       define RADEON_SCK_PRESCALE_MASK     (0xff << 24)
+#define R300_MC_IND_INDEX                   0x01f8
+#       define R300_MC_IND_ADDR_MASK        0x3f
+#       define R300_MC_IND_WR_EN            (1 << 8)
+#define R300_MC_IND_DATA                    0x01fc
+#define R300_MC_READ_CNTL_AB                0x017c
+#       define R300_MEM_RBS_POSITION_A_MASK 0x03
+#define R300_MC_READ_CNTL_CD_mcind          0x24
+#       define R300_MEM_RBS_POSITION_C_MASK 0x03
+
+#define RADEON_N_VIF_COUNT                  0x0248
+
+#define RADEON_OV0_AUTO_FLIP_CNTL           0x0470
+#       define  RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM        0x00000007
+#       define  RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD   0x00000008
+#       define  RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD        0x00000010
+#       define  RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020
+#       define  RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE     0x00000040
+#       define  RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT     0x00000300
+#       define  RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN  0x00010000
+#       define  RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN     0x00040000
+#       define  RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN      0x00080000
+#       define  RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE    0x00800000
+
+#define RADEON_OV0_COLOUR_CNTL              0x04E0
+#define RADEON_OV0_DEINTERLACE_PATTERN      0x0474
+#define RADEON_OV0_EXCLUSIVE_HORZ           0x0408
+#       define  RADEON_EXCL_HORZ_START_MASK        0x000000ff
+#       define  RADEON_EXCL_HORZ_END_MASK          0x0000ff00
+#       define  RADEON_EXCL_HORZ_BACK_PORCH_MASK   0x00ff0000
+#       define  RADEON_EXCL_HORZ_EXCLUSIVE_EN      0x80000000
+#define RADEON_OV0_EXCLUSIVE_VERT           0x040C
+#       define  RADEON_EXCL_VERT_START_MASK        0x000003ff
+#       define  RADEON_EXCL_VERT_END_MASK          0x03ff0000
+#define RADEON_OV0_FILTER_CNTL              0x04A0
+#       define RADEON_FILTER_PROGRAMMABLE_COEF            0x0
+#       define RADEON_FILTER_HC_COEF_HORZ_Y               0x1
+#       define RADEON_FILTER_HC_COEF_HORZ_UV              0x2
+#       define RADEON_FILTER_HC_COEF_VERT_Y               0x4
+#       define RADEON_FILTER_HC_COEF_VERT_UV              0x8
+#       define RADEON_FILTER_HARDCODED_COEF               0xf
+#       define RADEON_FILTER_COEF_MASK                    0xf
+
+#define RADEON_OV0_FOUR_TAP_COEF_0          0x04B0
+#define RADEON_OV0_FOUR_TAP_COEF_1          0x04B4
+#define RADEON_OV0_FOUR_TAP_COEF_2          0x04B8
+#define RADEON_OV0_FOUR_TAP_COEF_3          0x04BC
+#define RADEON_OV0_FOUR_TAP_COEF_4          0x04C0
+#define RADEON_OV0_FLAG_CNTL                0x04DC
+#define RADEON_OV0_GAMMA_000_00F            0x0d40
+#define RADEON_OV0_GAMMA_010_01F            0x0d44
+#define RADEON_OV0_GAMMA_020_03F            0x0d48
+#define RADEON_OV0_GAMMA_040_07F            0x0d4c
+#define RADEON_OV0_GAMMA_080_0BF            0x0e00
+#define RADEON_OV0_GAMMA_0C0_0FF            0x0e04
+#define RADEON_OV0_GAMMA_100_13F            0x0e08
+#define RADEON_OV0_GAMMA_140_17F            0x0e0c
+#define RADEON_OV0_GAMMA_180_1BF            0x0e10
+#define RADEON_OV0_GAMMA_1C0_1FF            0x0e14
+#define RADEON_OV0_GAMMA_200_23F            0x0e18
+#define RADEON_OV0_GAMMA_240_27F            0x0e1c
+#define RADEON_OV0_GAMMA_280_2BF            0x0e20
+#define RADEON_OV0_GAMMA_2C0_2FF            0x0e24
+#define RADEON_OV0_GAMMA_300_33F            0x0e28
+#define RADEON_OV0_GAMMA_340_37F            0x0e2c
+#define RADEON_OV0_GAMMA_380_3BF            0x0d50
+#define RADEON_OV0_GAMMA_3C0_3FF            0x0d54
+#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW     0x04EC
+#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH    0x04F0
+#define RADEON_OV0_H_INC                    0x0480
+#define RADEON_OV0_KEY_CNTL                 0x04F4
+#       define  RADEON_VIDEO_KEY_FN_MASK    0x00000003L
+#       define  RADEON_VIDEO_KEY_FN_FALSE   0x00000000L
+#       define  RADEON_VIDEO_KEY_FN_TRUE    0x00000001L
+#       define  RADEON_VIDEO_KEY_FN_EQ      0x00000002L
+#       define  RADEON_VIDEO_KEY_FN_NE      0x00000003L
+#       define  RADEON_GRAPHIC_KEY_FN_MASK  0x00000030L
+#       define  RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L
+#       define  RADEON_GRAPHIC_KEY_FN_TRUE  0x00000010L
+#       define  RADEON_GRAPHIC_KEY_FN_EQ    0x00000020L
+#       define  RADEON_GRAPHIC_KEY_FN_NE    0x00000030L
+#       define  RADEON_CMP_MIX_MASK         0x00000100L
+#       define  RADEON_CMP_MIX_OR           0x00000000L
+#       define  RADEON_CMP_MIX_AND          0x00000100L
+#define RADEON_OV0_LIN_TRANS_A              0x0d20
+#define RADEON_OV0_LIN_TRANS_B              0x0d24
+#define RADEON_OV0_LIN_TRANS_C              0x0d28
+#define RADEON_OV0_LIN_TRANS_D              0x0d2c
+#define RADEON_OV0_LIN_TRANS_E              0x0d30
+#define RADEON_OV0_LIN_TRANS_F              0x0d34
+#define RADEON_OV0_P1_BLANK_LINES_AT_TOP    0x0430
+#       define  RADEON_P1_BLNK_LN_AT_TOP_M1_MASK   0x00000fffL
+#       define  RADEON_P1_ACTIVE_LINES_M1          0x0fff0000L
+#define RADEON_OV0_P1_H_ACCUM_INIT          0x0488
+#define RADEON_OV0_P1_V_ACCUM_INIT          0x0428
+#       define  RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
+#       define  RADEON_OV0_P1_V_ACCUM_INIT_MASK    0x01ff8000L
+#define RADEON_OV0_P1_X_START_END           0x0494
+#define RADEON_OV0_P2_X_START_END           0x0498
+#define RADEON_OV0_P23_BLANK_LINES_AT_TOP   0x0434
+#       define  RADEON_P23_BLNK_LN_AT_TOP_M1_MASK  0x000007ffL
+#       define  RADEON_P23_ACTIVE_LINES_M1         0x07ff0000L
+#define RADEON_OV0_P23_H_ACCUM_INIT         0x048C
+#define RADEON_OV0_P23_V_ACCUM_INIT         0x042C
+#define RADEON_OV0_P3_X_START_END           0x049C
+#define RADEON_OV0_REG_LOAD_CNTL            0x0410
+#       define  RADEON_REG_LD_CTL_LOCK                 0x00000001L
+#       define  RADEON_REG_LD_CTL_VBLANK_DURING_LOCK   0x00000002L
+#       define  RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
+#       define  RADEON_REG_LD_CTL_LOCK_READBACK        0x00000008L
+#       define  RADEON_REG_LD_CTL_FLIP_READBACK        0x00000010L
+#define RADEON_OV0_SCALE_CNTL               0x0420
+#       define  RADEON_SCALER_HORZ_PICK_NEAREST    0x00000004L
+#       define  RADEON_SCALER_VERT_PICK_NEAREST    0x00000008L
+#       define  RADEON_SCALER_SIGNED_UV            0x00000010L
+#       define  RADEON_SCALER_GAMMA_SEL_MASK       0x00000060L
+#       define  RADEON_SCALER_GAMMA_SEL_BRIGHT     0x00000000L
+#       define  RADEON_SCALER_GAMMA_SEL_G22        0x00000020L
+#       define  RADEON_SCALER_GAMMA_SEL_G18        0x00000040L
+#       define  RADEON_SCALER_GAMMA_SEL_G14        0x00000060L
+#       define  RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
+#       define  RADEON_SCALER_SURFAC_FORMAT        0x00000f00L
+#       define  RADEON_SCALER_SOURCE_15BPP         0x00000300L
+#       define  RADEON_SCALER_SOURCE_16BPP         0x00000400L
+#       define  RADEON_SCALER_SOURCE_32BPP         0x00000600L
+#       define  RADEON_SCALER_SOURCE_YUV9          0x00000900L
+#       define  RADEON_SCALER_SOURCE_YUV12         0x00000A00L
+#       define  RADEON_SCALER_SOURCE_VYUY422       0x00000B00L
+#       define  RADEON_SCALER_SOURCE_YVYU422       0x00000C00L
+#       define  RADEON_SCALER_ADAPTIVE_DEINT       0x00001000L
+#       define  RADEON_SCALER_TEMPORAL_DEINT       0x00002000L
+#       define  RADEON_SCALER_CRTC_SEL             0x00004000L
+#       define  RADEON_SCALER_SMART_SWITCH         0x00008000L
+#       define  RADEON_SCALER_BURST_PER_PLANE      0x007F0000L
+#       define  RADEON_SCALER_DOUBLE_BUFFER        0x01000000L
+#       define  RADEON_SCALER_DIS_LIMIT            0x08000000L
+#       define  RADEON_SCALER_LIN_TRANS_BYPASS     0x10000000L
+#       define  RADEON_SCALER_INT_EMU              0x20000000L
+#       define  RADEON_SCALER_ENABLE               0x40000000L
+#       define  RADEON_SCALER_SOFT_RESET           0x80000000L
+#define RADEON_OV0_STEP_BY                  0x0484
+#define RADEON_OV0_TEST                     0x04F8
+#define RADEON_OV0_V_INC                    0x0424
+#define RADEON_OV0_VID_BUF_PITCH0_VALUE     0x0460
+#define RADEON_OV0_VID_BUF_PITCH1_VALUE     0x0464
+#define RADEON_OV0_VID_BUF0_BASE_ADRS       0x0440
+#       define  RADEON_VIF_BUF0_PITCH_SEL          0x00000001L
+#       define  RADEON_VIF_BUF0_TILE_ADRS          0x00000002L
+#       define  RADEON_VIF_BUF0_BASE_ADRS_MASK     0x03fffff0L
+#       define  RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
+#define RADEON_OV0_VID_BUF1_BASE_ADRS       0x0444
+#       define  RADEON_VIF_BUF1_PITCH_SEL          0x00000001L
+#       define  RADEON_VIF_BUF1_TILE_ADRS          0x00000002L
+#       define  RADEON_VIF_BUF1_BASE_ADRS_MASK     0x03fffff0L
+#       define  RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
+#define RADEON_OV0_VID_BUF2_BASE_ADRS       0x0448
+#       define  RADEON_VIF_BUF2_PITCH_SEL          0x00000001L
+#       define  RADEON_VIF_BUF2_TILE_ADRS          0x00000002L
+#       define  RADEON_VIF_BUF2_BASE_ADRS_MASK     0x03fffff0L
+#       define  RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
+#define RADEON_OV0_VID_BUF3_BASE_ADRS       0x044C
+#define RADEON_OV0_VID_BUF4_BASE_ADRS       0x0450
+#define RADEON_OV0_VID_BUF5_BASE_ADRS       0x0454
+#define RADEON_OV0_VIDEO_KEY_CLR_HIGH       0x04E8
+#define RADEON_OV0_VIDEO_KEY_CLR_LOW        0x04E4
+#define RADEON_OV0_Y_X_START                0x0400
+#define RADEON_OV0_Y_X_END                  0x0404
+#define RADEON_OV1_Y_X_START                0x0600
+#define RADEON_OV1_Y_X_END                  0x0604
+#define RADEON_OVR_CLR                      0x0230
+#define RADEON_OVR_WID_LEFT_RIGHT           0x0234
+#define RADEON_OVR_WID_TOP_BOTTOM           0x0238
+
+/* first capture unit */
+
+#define RADEON_CAP0_BUF0_OFFSET           0x0920
+#define RADEON_CAP0_BUF1_OFFSET           0x0924
+#define RADEON_CAP0_BUF0_EVEN_OFFSET      0x0928
+#define RADEON_CAP0_BUF1_EVEN_OFFSET      0x092C
+
+#define RADEON_CAP0_BUF_PITCH             0x0930
+#define RADEON_CAP0_V_WINDOW              0x0934
+#define RADEON_CAP0_H_WINDOW              0x0938
+#define RADEON_CAP0_VBI0_OFFSET           0x093C
+#define RADEON_CAP0_VBI1_OFFSET           0x0940
+#define RADEON_CAP0_VBI_V_WINDOW          0x0944
+#define RADEON_CAP0_VBI_H_WINDOW          0x0948
+#define RADEON_CAP0_PORT_MODE_CNTL        0x094C
+#define RADEON_CAP0_TRIG_CNTL             0x0950
+#define RADEON_CAP0_DEBUG                 0x0954
+#define RADEON_CAP0_CONFIG                0x0958
+#       define RADEON_CAP0_CONFIG_CONTINUOS          0x00000001
+#       define RADEON_CAP0_CONFIG_START_FIELD_EVEN   0x00000002
+#       define RADEON_CAP0_CONFIG_START_BUF_GET      0x00000004
+#       define RADEON_CAP0_CONFIG_START_BUF_SET      0x00000008
+#       define RADEON_CAP0_CONFIG_BUF_TYPE_ALT       0x00000010
+#       define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME     0x00000020
+#       define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
+#       define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE    0x00000080
+#       define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE    0x00000100
+#       define RADEON_CAP0_CONFIG_MIRROR_EN          0x00000200
+#       define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN  0x00000400
+#       define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV    0x00000800
+#       define RADEON_CAP0_CONFIG_ANC_DECODE_EN      0x00001000
+#       define RADEON_CAP0_CONFIG_VBI_EN             0x00002000
+#       define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN  0x00004000
+#       define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
+#       define RADEON_CAP0_CONFIG_FAKE_FIELD_EN      0x00010000
+#       define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE  0x00020000
+#       define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
+#       define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2      0x00080000
+#       define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4      0x00100000
+#       define RADEON_CAP0_CONFIG_VERT_DIVIDE_2      0x00200000
+#       define RADEON_CAP0_CONFIG_VERT_DIVIDE_4      0x00400000
+#       define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE   0x00000000
+#       define RADEON_CAP0_CONFIG_FORMAT_CCIR656     0x00800000
+#       define RADEON_CAP0_CONFIG_FORMAT_ZV          0x01000000
+#       define RADEON_CAP0_CONFIG_FORMAT_VIP         0x01800000
+#       define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT   0x02000000
+#       define RADEON_CAP0_CONFIG_HORZ_DECIMATOR     0x04000000
+#       define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422   0x00000000
+#       define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422   0x20000000
+#       define RADEON_CAP0_CONFIG_VBI_DIVIDE_2       0x40000000
+#       define RADEON_CAP0_CONFIG_VBI_DIVIDE_4       0x80000000
+#define RADEON_CAP0_ANC_ODD_OFFSET        0x095C
+#define RADEON_CAP0_ANC_EVEN_OFFSET       0x0960
+#define RADEON_CAP0_ANC_H_WINDOW          0x0964
+#define RADEON_CAP0_VIDEO_SYNC_TEST       0x0968
+#define RADEON_CAP0_ONESHOT_BUF_OFFSET    0x096C
+#define RADEON_CAP0_BUF_STATUS            0x0970
+/* #define RADEON_CAP0_DWNSC_XRATIO       0x0978 */
+/* #define RADEON_CAP0_XSHARPNESS                 0x097C */
+#define RADEON_CAP0_VBI2_OFFSET           0x0980
+#define RADEON_CAP0_VBI3_OFFSET           0x0984
+#define RADEON_CAP0_ANC2_OFFSET           0x0988
+#define RADEON_CAP0_ANC3_OFFSET           0x098C
+#define RADEON_VID_BUFFER_CONTROL         0x0900
+
+/* second capture unit */
+
+#define RADEON_CAP1_BUF0_OFFSET           0x0990
+#define RADEON_CAP1_BUF1_OFFSET           0x0994
+#define RADEON_CAP1_BUF0_EVEN_OFFSET      0x0998
+#define RADEON_CAP1_BUF1_EVEN_OFFSET      0x099C
+
+#define RADEON_CAP1_BUF_PITCH             0x09A0
+#define RADEON_CAP1_V_WINDOW              0x09A4
+#define RADEON_CAP1_H_WINDOW              0x09A8
+#define RADEON_CAP1_VBI_ODD_OFFSET        0x09AC
+#define RADEON_CAP1_VBI_EVEN_OFFSET       0x09B0
+#define RADEON_CAP1_VBI_V_WINDOW                  0x09B4
+#define RADEON_CAP1_VBI_H_WINDOW                  0x09B8
+#define RADEON_CAP1_PORT_MODE_CNTL        0x09BC
+#define RADEON_CAP1_TRIG_CNTL             0x09C0
+#define RADEON_CAP1_DEBUG                         0x09C4
+#define RADEON_CAP1_CONFIG                0x09C8
+#define RADEON_CAP1_ANC_ODD_OFFSET        0x09CC
+#define RADEON_CAP1_ANC_EVEN_OFFSET       0x09D0
+#define RADEON_CAP1_ANC_H_WINDOW                  0x09D4
+#define RADEON_CAP1_VIDEO_SYNC_TEST       0x09D8
+#define RADEON_CAP1_ONESHOT_BUF_OFFSET    0x09DC
+#define RADEON_CAP1_BUF_STATUS            0x09E0
+#define RADEON_CAP1_DWNSC_XRATIO                  0x09E8
+#define RADEON_CAP1_XSHARPNESS            0x09EC
+
+/* misc multimedia registers */
+
+#define RADEON_IDCT_RUNS                  0x1F80
+#define RADEON_IDCT_LEVELS                0x1F84
+#define RADEON_IDCT_CONTROL               0x1FBC
+#define RADEON_IDCT_AUTH_CONTROL          0x1F88
+#define RADEON_IDCT_AUTH                  0x1F8C
+
+#define RADEON_P2PLL_CNTL                   0x002a /* P2PLL */
+#       define RADEON_P2PLL_RESET                (1 <<  0)
+#       define RADEON_P2PLL_SLEEP                (1 <<  1)
+#       define RADEON_P2PLL_PVG_MASK             (7 << 11)
+#       define RADEON_P2PLL_PVG_SHIFT            11
+#       define RADEON_P2PLL_ATOMIC_UPDATE_EN     (1 << 16)
+#       define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
+#       define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC  (1 << 18)
+#define RADEON_P2PLL_DIV_0                  0x002c
+#       define RADEON_P2PLL_FB0_DIV_MASK    0x07ff
+#       define RADEON_P2PLL_POST0_DIV_MASK  0x00070000
+#define RADEON_P2PLL_REF_DIV                0x002B /* PLL */
+#       define RADEON_P2PLL_REF_DIV_MASK    0x03ff
+#       define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
+#       define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
+#       define R300_PPLL_REF_DIV_ACC_MASK   (0x3ff << 18)
+#       define R300_PPLL_REF_DIV_ACC_SHIFT  18
+#define RADEON_PALETTE_DATA                 0x00b4
+#define RADEON_PALETTE_30_DATA              0x00b8
+#define RADEON_PALETTE_INDEX                0x00b0
+#define RADEON_PCI_GART_PAGE                0x017c
+#define RADEON_PIXCLKS_CNTL                 0x002d
+#       define RADEON_PIX2CLK_SRC_SEL_MASK     0x03
+#       define RADEON_PIX2CLK_SRC_SEL_CPUCLK   0x00
+#       define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
+#       define RADEON_PIX2CLK_SRC_SEL_BYTECLK  0x02
+#       define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
+#       define RADEON_PIX2CLK_ALWAYS_ONb       (1<<6)
+#       define RADEON_PIX2CLK_DAC_ALWAYS_ONb   (1<<7)
+#       define RADEON_PIXCLK_TV_SRC_SEL        (1 << 8)
+#       define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
+#       define R300_DVOCLK_ALWAYS_ONb          (1 << 10)
+#       define RADEON_PIXCLK_BLEND_ALWAYS_ONb  (1 << 11)
+#       define RADEON_PIXCLK_GV_ALWAYS_ONb     (1 << 12)
+#       define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)
+#       define R300_PIXCLK_DVO_ALWAYS_ONb      (1 << 13)
+#       define RADEON_PIXCLK_LVDS_ALWAYS_ONb   (1 << 14)
+#       define RADEON_PIXCLK_TMDS_ALWAYS_ONb   (1 << 15)
+#       define R300_PIXCLK_TRANS_ALWAYS_ONb    (1 << 16)
+#       define R300_PIXCLK_TVO_ALWAYS_ONb      (1 << 17)
+#       define R300_P2G2CLK_ALWAYS_ONb         (1 << 18)
+#       define R300_P2G2CLK_DAC_ALWAYS_ONb     (1 << 19)
+#       define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
+#define RADEON_PLANE_3D_MASK_C              0x1d44
+#define RADEON_PLL_TEST_CNTL                0x0013 /* PLL */
+#       define RADEON_PLL_MASK_READ_B          (1 << 9)
+#define RADEON_PMI_CAP_ID                   0x0f5c /* PCI */
+#define RADEON_PMI_DATA                     0x0f63 /* PCI */
+#define RADEON_PMI_NXT_CAP_PTR              0x0f5d /* PCI */
+#define RADEON_PMI_PMC_REG                  0x0f5e /* PCI */
+#define RADEON_PMI_PMCSR_REG                0x0f60 /* PCI */
+#define RADEON_PMI_REGISTER                 0x0f5c /* PCI */
+#define RADEON_PPLL_CNTL                    0x0002 /* PLL */
+#       define RADEON_PPLL_RESET                (1 <<  0)
+#       define RADEON_PPLL_SLEEP                (1 <<  1)
+#       define RADEON_PPLL_PVG_MASK             (7 << 11)
+#       define RADEON_PPLL_PVG_SHIFT            11
+#       define RADEON_PPLL_ATOMIC_UPDATE_EN     (1 << 16)
+#       define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
+#       define RADEON_PPLL_ATOMIC_UPDATE_VSYNC  (1 << 18)
+#define RADEON_PPLL_DIV_0                   0x0004 /* PLL */
+#define RADEON_PPLL_DIV_1                   0x0005 /* PLL */
+#define RADEON_PPLL_DIV_2                   0x0006 /* PLL */
+#define RADEON_PPLL_DIV_3                   0x0007 /* PLL */
+#       define RADEON_PPLL_FB3_DIV_MASK     0x07ff
+#       define RADEON_PPLL_POST3_DIV_MASK   0x00070000
+#define RADEON_PPLL_REF_DIV                 0x0003 /* PLL */
+#       define RADEON_PPLL_REF_DIV_MASK     0x03ff
+#       define RADEON_PPLL_ATOMIC_UPDATE_R  (1 << 15) /* same as _W */
+#       define RADEON_PPLL_ATOMIC_UPDATE_W  (1 << 15) /* same as _R */
+#define RADEON_PWR_MNGMT_CNTL_STATUS        0x0f60 /* PCI */
+
+#define RADEON_RBBM_GUICNTL                 0x172c
+#       define RADEON_HOST_DATA_SWAP_NONE   (0 << 0)
+#       define RADEON_HOST_DATA_SWAP_16BIT  (1 << 0)
+#       define RADEON_HOST_DATA_SWAP_32BIT  (2 << 0)
+#       define RADEON_HOST_DATA_SWAP_HDW    (3 << 0)
+#define RADEON_RBBM_SOFT_RESET              0x00f0
+#       define RADEON_SOFT_RESET_CP         (1 <<  0)
+#       define RADEON_SOFT_RESET_HI         (1 <<  1)
+#       define RADEON_SOFT_RESET_SE         (1 <<  2)
+#       define RADEON_SOFT_RESET_RE         (1 <<  3)
+#       define RADEON_SOFT_RESET_PP         (1 <<  4)
+#       define RADEON_SOFT_RESET_E2         (1 <<  5)
+#       define RADEON_SOFT_RESET_RB         (1 <<  6)
+#       define RADEON_SOFT_RESET_HDP        (1 <<  7)
+#define RADEON_RBBM_STATUS                  0x0e40
+#       define RADEON_RBBM_FIFOCNT_MASK     0x007f
+#       define RADEON_RBBM_ACTIVE           (1 << 31)
+#define RADEON_RB2D_DSTCACHE_CTLSTAT        0x342c
+#       define RADEON_RB2D_DC_FLUSH         (3 << 0)
+#       define RADEON_RB2D_DC_FREE          (3 << 2)
+#       define RADEON_RB2D_DC_FLUSH_ALL     0xf
+#       define RADEON_RB2D_DC_BUSY          (1 << 31)
+#define RADEON_RB2D_DSTCACHE_MODE           0x3428
+#define RADEON_DSTCACHE_CTLSTAT             0x1714
+
+#define RADEON_RB3D_ZCACHE_MODE             0x3250
+#define RADEON_RB3D_ZCACHE_CTLSTAT          0x3254
+#       define RADEON_RB3D_ZC_FLUSH_ALL     0x5
+#define RADEON_RB3D_DSTCACHE_MODE           0x3258
+# define RADEON_RB3D_DC_CACHE_ENABLE            (0)
+# define RADEON_RB3D_DC_2D_CACHE_DISABLE        (1)
+# define RADEON_RB3D_DC_3D_CACHE_DISABLE        (2)
+# define RADEON_RB3D_DC_CACHE_DISABLE           (3)
+# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128   (1 << 2)
+# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128   (2 << 2)
+# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH      (1 << 8)
+# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH      (2 << 8)
+# define R200_RB3D_DC_2D_CACHE_AUTOFREE         (1 << 10)
+# define R200_RB3D_DC_3D_CACHE_AUTOFREE         (2 << 10)
+# define RADEON_RB3D_DC_FORCE_RMW               (1 << 16)
+# define RADEON_RB3D_DC_DISABLE_RI_FILL         (1 << 24)
+# define RADEON_RB3D_DC_DISABLE_RI_READ         (1 << 25)
+
+#define RADEON_RB3D_DSTCACHE_CTLSTAT            0x325C
+# define RADEON_RB3D_DC_FLUSH                   (3 << 0)
+# define RADEON_RB3D_DC_FREE                    (3 << 2)
+# define RADEON_RB3D_DC_FLUSH_ALL               0xf
+# define RADEON_RB3D_DC_BUSY                    (1 << 31)
+
+#define RADEON_REG_BASE                     0x0f18 /* PCI */
+#define RADEON_REGPROG_INF                  0x0f09 /* PCI */
+#define RADEON_REVISION_ID                  0x0f08 /* PCI */
+
+#define RADEON_SC_BOTTOM                    0x164c
+#define RADEON_SC_BOTTOM_RIGHT              0x16f0
+#define RADEON_SC_BOTTOM_RIGHT_C            0x1c8c
+#define RADEON_SC_LEFT                      0x1640
+#define RADEON_SC_RIGHT                     0x1644
+#define RADEON_SC_TOP                       0x1648
+#define RADEON_SC_TOP_LEFT                  0x16ec
+#define RADEON_SC_TOP_LEFT_C                0x1c88
+#       define RADEON_SC_SIGN_MASK_LO       0x8000
+#       define RADEON_SC_SIGN_MASK_HI       0x80000000
+#define RADEON_M_SPLL_REF_FB_DIV            0x000a /* PLL */
+#       define RADEON_M_SPLL_REF_DIV_SHIFT  0
+#       define RADEON_M_SPLL_REF_DIV_MASK   0xff
+#       define RADEON_MPLL_FB_DIV_SHIFT     8
+#       define RADEON_MPLL_FB_DIV_MASK      0xff
+#       define RADEON_SPLL_FB_DIV_SHIFT     16
+#       define RADEON_SPLL_FB_DIV_MASK      0xff
+#define RADEON_SPLL_CNTL                    0x000c /* PLL */
+#       define RADEON_SPLL_SLEEP            (1 << 0)
+#       define RADEON_SPLL_RESET            (1 << 1)
+#       define RADEON_SPLL_PCP_MASK         0x7
+#       define RADEON_SPLL_PCP_SHIFT        8
+#       define RADEON_SPLL_PVG_MASK         0x7
+#       define RADEON_SPLL_PVG_SHIFT        11
+#       define RADEON_SPLL_PDC_MASK         0x3
+#       define RADEON_SPLL_PDC_SHIFT        14
+#define RADEON_SCLK_CNTL                    0x000d /* PLL */
+#       define RADEON_SCLK_SRC_SEL_MASK     0x0007
+#       define RADEON_DYN_STOP_LAT_MASK     0x00007ff8
+#       define RADEON_CP_MAX_DYN_STOP_LAT   0x0008
+#       define RADEON_SCLK_FORCEON_MASK     0xffff8000
+#       define RADEON_SCLK_FORCE_DISP2      (1<<15)
+#       define RADEON_SCLK_FORCE_CP         (1<<16)
+#       define RADEON_SCLK_FORCE_HDP        (1<<17)
+#       define RADEON_SCLK_FORCE_DISP1      (1<<18)
+#       define RADEON_SCLK_FORCE_TOP        (1<<19)
+#       define RADEON_SCLK_FORCE_E2         (1<<20)
+#       define RADEON_SCLK_FORCE_SE         (1<<21)
+#       define RADEON_SCLK_FORCE_IDCT       (1<<22)
+#       define RADEON_SCLK_FORCE_VIP        (1<<23)
+#       define RADEON_SCLK_FORCE_RE         (1<<24)
+#       define RADEON_SCLK_FORCE_PB         (1<<25)
+#       define RADEON_SCLK_FORCE_TAM        (1<<26)
+#       define RADEON_SCLK_FORCE_TDM        (1<<27)
+#       define RADEON_SCLK_FORCE_RB         (1<<28)
+#       define RADEON_SCLK_FORCE_TV_SCLK    (1<<29)
+#       define RADEON_SCLK_FORCE_SUBPIC     (1<<30)
+#       define RADEON_SCLK_FORCE_OV0        (1<<31)
+#       define R300_SCLK_FORCE_VAP          (1<<21)
+#       define R300_SCLK_FORCE_SR           (1<<25)
+#       define R300_SCLK_FORCE_PX           (1<<26)
+#       define R300_SCLK_FORCE_TX           (1<<27)
+#       define R300_SCLK_FORCE_US           (1<<28)
+#       define R300_SCLK_FORCE_SU           (1<<30)
+#define R300_SCLK_CNTL2                     0x1e   /* PLL */
+#       define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)
+#       define R300_SCLK_GA_MAX_DYN_STOP_LAT  (1<<11)
+#       define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)
+#       define R300_SCLK_FORCE_TCL          (1<<13)
+#       define R300_SCLK_FORCE_CBA          (1<<14)
+#       define R300_SCLK_FORCE_GA           (1<<15)
+#define RADEON_SCLK_MORE_CNTL               0x0035 /* PLL */
+#       define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007
+#       define RADEON_SCLK_MORE_FORCEON     0x0700
+#define RADEON_SDRAM_MODE_REG               0x0158
+#define RADEON_SEQ8_DATA                    0x03c5 /* VGA */
+#define RADEON_SEQ8_IDX                     0x03c4 /* VGA */
+#define RADEON_SNAPSHOT_F_COUNT             0x0244
+#define RADEON_SNAPSHOT_VH_COUNTS           0x0240
+#define RADEON_SNAPSHOT_VIF_COUNT           0x024c
+#define RADEON_SRC_OFFSET                   0x15ac
+#define RADEON_SRC_PITCH                    0x15b0
+#define RADEON_SRC_PITCH_OFFSET             0x1428
+#define RADEON_SRC_SC_BOTTOM                0x165c
+#define RADEON_SRC_SC_BOTTOM_RIGHT          0x16f4
+#define RADEON_SRC_SC_RIGHT                 0x1654
+#define RADEON_SRC_X                        0x1414
+#define RADEON_SRC_X_Y                      0x1590
+#define RADEON_SRC_Y                        0x1418
+#define RADEON_SRC_Y_X                      0x1434
+#define RADEON_STATUS                       0x0f06 /* PCI */
+#define RADEON_SUBPIC_CNTL                  0x0540 /* ? */
+#define RADEON_SUB_CLASS                    0x0f0a /* PCI */
+#define RADEON_SURFACE_CNTL                 0x0b00
+#       define RADEON_SURF_TRANSLATION_DIS  (1 << 8)
+#       define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
+#       define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
+#       define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
+#       define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
+#define RADEON_SURFACE0_INFO                0x0b0c
+#       define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)
+#       define RADEON_SURF_TILE_COLOR_BOTH  (1 << 16)
+#       define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)
+#       define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)
+#       define R200_SURF_TILE_NONE          (0 << 16)
+#       define R200_SURF_TILE_COLOR_MACRO   (1 << 16)
+#       define R200_SURF_TILE_COLOR_MICRO   (2 << 16)
+#       define R200_SURF_TILE_COLOR_BOTH    (3 << 16)
+#       define R200_SURF_TILE_DEPTH_32BPP   (4 << 16)
+#       define R200_SURF_TILE_DEPTH_16BPP   (5 << 16)
+#       define R300_SURF_TILE_NONE          (0 << 16)
+#       define R300_SURF_TILE_COLOR_MACRO   (1 << 16)
+#       define R300_SURF_TILE_DEPTH_32BPP   (2 << 16)
+#       define RADEON_SURF_AP0_SWP_16BPP    (1 << 20)
+#       define RADEON_SURF_AP0_SWP_32BPP    (1 << 21)
+#       define RADEON_SURF_AP1_SWP_16BPP    (1 << 22)
+#       define RADEON_SURF_AP1_SWP_32BPP    (1 << 23)
+#define RADEON_SURFACE0_LOWER_BOUND         0x0b04
+#define RADEON_SURFACE0_UPPER_BOUND         0x0b08
+#define RADEON_SURFACE1_INFO                0x0b1c
+#define RADEON_SURFACE1_LOWER_BOUND         0x0b14
+#define RADEON_SURFACE1_UPPER_BOUND         0x0b18
+#define RADEON_SURFACE2_INFO                0x0b2c
+#define RADEON_SURFACE2_LOWER_BOUND         0x0b24
+#define RADEON_SURFACE2_UPPER_BOUND         0x0b28
+#define RADEON_SURFACE3_INFO                0x0b3c
+#define RADEON_SURFACE3_LOWER_BOUND         0x0b34
+#define RADEON_SURFACE3_UPPER_BOUND         0x0b38
+#define RADEON_SURFACE4_INFO                0x0b4c
+#define RADEON_SURFACE4_LOWER_BOUND         0x0b44
+#define RADEON_SURFACE4_UPPER_BOUND         0x0b48
+#define RADEON_SURFACE5_INFO                0x0b5c
+#define RADEON_SURFACE5_LOWER_BOUND         0x0b54
+#define RADEON_SURFACE5_UPPER_BOUND         0x0b58
+#define RADEON_SURFACE6_INFO                0x0b6c
+#define RADEON_SURFACE6_LOWER_BOUND         0x0b64
+#define RADEON_SURFACE6_UPPER_BOUND         0x0b68
+#define RADEON_SURFACE7_INFO                0x0b7c
+#define RADEON_SURFACE7_LOWER_BOUND         0x0b74
+#define RADEON_SURFACE7_UPPER_BOUND         0x0b78
+#define RADEON_SW_SEMAPHORE                 0x013c
+
+#define RADEON_TEST_DEBUG_CNTL              0x0120
+#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
+
+#define RADEON_TEST_DEBUG_MUX               0x0124
+#define RADEON_TEST_DEBUG_OUT               0x012c
+#define RADEON_TMDS_PLL_CNTL                0x02a8
+#define RADEON_TMDS_TRANSMITTER_CNTL        0x02a4
+#       define RADEON_TMDS_TRANSMITTER_PLLEN  1
+#       define RADEON_TMDS_TRANSMITTER_PLLRST 2
+#define RADEON_TRAIL_BRES_DEC               0x1614
+#define RADEON_TRAIL_BRES_ERR               0x160c
+#define RADEON_TRAIL_BRES_INC               0x1610
+#define RADEON_TRAIL_X                      0x1618
+#define RADEON_TRAIL_X_SUB                  0x1620
+
+#define RADEON_VCLK_ECP_CNTL                0x0008 /* PLL */
+#       define RADEON_VCLK_SRC_SEL_MASK     0x03
+#       define RADEON_VCLK_SRC_SEL_CPUCLK   0x00
+#       define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
+#       define RADEON_VCLK_SRC_SEL_BYTECLK  0x02
+#       define RADEON_VCLK_SRC_SEL_PPLLCLK  0x03
+#       define RADEON_PIXCLK_ALWAYS_ONb     (1<<6)
+#       define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
+#       define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
+
+#define RADEON_VENDOR_ID                    0x0f00 /* PCI */
+#define RADEON_VGA_DDA_CONFIG               0x02e8
+#define RADEON_VGA_DDA_ON_OFF               0x02ec
+#define RADEON_VID_BUFFER_CONTROL           0x0900
+#define RADEON_VIDEOMUX_CNTL                0x0190
+
+/* VIP bus */
+#define RADEON_VIPH_CH0_DATA                0x0c00
+#define RADEON_VIPH_CH1_DATA                0x0c04
+#define RADEON_VIPH_CH2_DATA                0x0c08
+#define RADEON_VIPH_CH3_DATA                0x0c0c
+#define RADEON_VIPH_CH0_ADDR                0x0c10
+#define RADEON_VIPH_CH1_ADDR                0x0c14
+#define RADEON_VIPH_CH2_ADDR                0x0c18
+#define RADEON_VIPH_CH3_ADDR                0x0c1c
+#define RADEON_VIPH_CH0_SBCNT               0x0c20
+#define RADEON_VIPH_CH1_SBCNT               0x0c24
+#define RADEON_VIPH_CH2_SBCNT               0x0c28
+#define RADEON_VIPH_CH3_SBCNT               0x0c2c
+#define RADEON_VIPH_CH0_ABCNT               0x0c30
+#define RADEON_VIPH_CH1_ABCNT               0x0c34
+#define RADEON_VIPH_CH2_ABCNT               0x0c38
+#define RADEON_VIPH_CH3_ABCNT               0x0c3c
+#define RADEON_VIPH_CONTROL                 0x0c40
+#       define RADEON_VIP_BUSY 0
+#       define RADEON_VIP_IDLE 1
+#       define RADEON_VIP_RESET 2
+#       define RADEON_VIPH_EN               (1 << 21)
+#define RADEON_VIPH_DV_LAT                  0x0c44
+#define RADEON_VIPH_BM_CHUNK                0x0c48
+#define RADEON_VIPH_DV_INT                  0x0c4c
+#define RADEON_VIPH_TIMEOUT_STAT            0x0c50
+#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
+#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK   0x00000010
+#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
+
+#define RADEON_VIPH_REG_DATA                0x0084
+#define RADEON_VIPH_REG_ADDR                0x0080
+
+
+#define RADEON_WAIT_UNTIL                   0x1720
+#       define RADEON_WAIT_CRTC_PFLIP       (1 << 0)
+#       define RADEON_WAIT_RE_CRTC_VLINE    (1 << 1)
+#       define RADEON_WAIT_FE_CRTC_VLINE    (1 << 2)
+#       define RADEON_WAIT_CRTC_VLINE       (1 << 3)
+#       define RADEON_WAIT_DMA_VID_IDLE     (1 << 8)
+#       define RADEON_WAIT_DMA_GUI_IDLE     (1 << 9)
+#       define RADEON_WAIT_CMDFIFO          (1 << 10) /* wait for CMDFIFO_ENTRIES */
+#       define RADEON_WAIT_OV0_FLIP         (1 << 11)
+#       define RADEON_WAIT_AGP_FLUSH        (1 << 13)
+#       define RADEON_WAIT_2D_IDLE          (1 << 14)
+#       define RADEON_WAIT_3D_IDLE          (1 << 15)
+#       define RADEON_WAIT_2D_IDLECLEAN     (1 << 16)
+#       define RADEON_WAIT_3D_IDLECLEAN     (1 << 17)
+#       define RADEON_WAIT_HOST_IDLECLEAN   (1 << 18)
+#       define RADEON_CMDFIFO_ENTRIES_SHIFT 10
+#       define RADEON_CMDFIFO_ENTRIES_MASK  0x7f
+#       define RADEON_WAIT_VAP_IDLE         (1 << 28)
+#       define RADEON_WAIT_BOTH_CRTC_PFLIP  (1 << 30)
+#       define RADEON_ENG_DISPLAY_SELECT_CRTC0    (0 << 31)
+#       define RADEON_ENG_DISPLAY_SELECT_CRTC1    (1 << 31)
+
+#define RADEON_X_MPLL_REF_FB_DIV            0x000a /* PLL */
+#define RADEON_XCLK_CNTL                    0x000d /* PLL */
+#define RADEON_XDLL_CNTL                    0x000c /* PLL */
+#define RADEON_XPLL_CNTL                    0x000b /* PLL */
+
+
+
+                                /* Registers for 3D/TCL */
+#define RADEON_PP_BORDER_COLOR_0            0x1d40
+#define RADEON_PP_BORDER_COLOR_1            0x1d44
+#define RADEON_PP_BORDER_COLOR_2            0x1d48
+#define RADEON_PP_CNTL                      0x1c38
+#       define RADEON_STIPPLE_ENABLE        (1 <<  0)
+#       define RADEON_SCISSOR_ENABLE        (1 <<  1)
+#       define RADEON_PATTERN_ENABLE        (1 <<  2)
+#       define RADEON_SHADOW_ENABLE         (1 <<  3)
+#       define RADEON_TEX_ENABLE_MASK       (0xf << 4)
+#       define RADEON_TEX_0_ENABLE          (1 <<  4)
+#       define RADEON_TEX_1_ENABLE          (1 <<  5)
+#       define RADEON_TEX_2_ENABLE          (1 <<  6)
+#       define RADEON_TEX_3_ENABLE          (1 <<  7)
+#       define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
+#       define RADEON_TEX_BLEND_0_ENABLE    (1 << 12)
+#       define RADEON_TEX_BLEND_1_ENABLE    (1 << 13)
+#       define RADEON_TEX_BLEND_2_ENABLE    (1 << 14)
+#       define RADEON_TEX_BLEND_3_ENABLE    (1 << 15)
+#       define RADEON_PLANAR_YUV_ENABLE     (1 << 20)
+#       define RADEON_SPECULAR_ENABLE       (1 << 21)
+#       define RADEON_FOG_ENABLE            (1 << 22)
+#       define RADEON_ALPHA_TEST_ENABLE     (1 << 23)
+#       define RADEON_ANTI_ALIAS_NONE       (0 << 24)
+#       define RADEON_ANTI_ALIAS_LINE       (1 << 24)
+#       define RADEON_ANTI_ALIAS_POLY       (2 << 24)
+#       define RADEON_ANTI_ALIAS_LINE_POLY  (3 << 24)
+#       define RADEON_BUMP_MAP_ENABLE       (1 << 26)
+#       define RADEON_BUMPED_MAP_T0         (0 << 27)
+#       define RADEON_BUMPED_MAP_T1         (1 << 27)
+#       define RADEON_BUMPED_MAP_T2         (2 << 27)
+#       define RADEON_TEX_3D_ENABLE_0       (1 << 29)
+#       define RADEON_TEX_3D_ENABLE_1       (1 << 30)
+#       define RADEON_MC_ENABLE             (1 << 31)
+#define RADEON_PP_FOG_COLOR                 0x1c18
+#       define RADEON_FOG_COLOR_MASK        0x00ffffff
+#       define RADEON_FOG_VERTEX            (0 << 24)
+#       define RADEON_FOG_TABLE             (1 << 24)
+#       define RADEON_FOG_USE_DEPTH         (0 << 25)
+#       define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)
+#       define RADEON_FOG_USE_SPEC_ALPHA    (3 << 25)
+#define RADEON_PP_LUM_MATRIX                0x1d00
+#define RADEON_PP_MISC                      0x1c14
+#       define RADEON_REF_ALPHA_MASK        0x000000ff
+#       define RADEON_ALPHA_TEST_FAIL       (0 << 8)
+#       define RADEON_ALPHA_TEST_LESS       (1 << 8)
+#       define RADEON_ALPHA_TEST_LEQUAL     (2 << 8)
+#       define RADEON_ALPHA_TEST_EQUAL      (3 << 8)
+#       define RADEON_ALPHA_TEST_GEQUAL     (4 << 8)
+#       define RADEON_ALPHA_TEST_GREATER    (5 << 8)
+#       define RADEON_ALPHA_TEST_NEQUAL     (6 << 8)
+#       define RADEON_ALPHA_TEST_PASS       (7 << 8)
+#       define RADEON_ALPHA_TEST_OP_MASK    (7 << 8)
+#       define RADEON_CHROMA_FUNC_FAIL      (0 << 16)
+#       define RADEON_CHROMA_FUNC_PASS      (1 << 16)
+#       define RADEON_CHROMA_FUNC_NEQUAL    (2 << 16)
+#       define RADEON_CHROMA_FUNC_EQUAL     (3 << 16)
+#       define RADEON_CHROMA_KEY_NEAREST    (0 << 18)
+#       define RADEON_CHROMA_KEY_ZERO       (1 << 18)
+#       define RADEON_SHADOW_ID_AUTO_INC    (1 << 20)
+#       define RADEON_SHADOW_FUNC_EQUAL     (0 << 21)
+#       define RADEON_SHADOW_FUNC_NEQUAL    (1 << 21)
+#       define RADEON_SHADOW_PASS_1         (0 << 22)
+#       define RADEON_SHADOW_PASS_2         (1 << 22)
+#       define RADEON_RIGHT_HAND_CUBE_D3D   (0 << 24)
+#       define RADEON_RIGHT_HAND_CUBE_OGL   (1 << 24)
+#define RADEON_PP_ROT_MATRIX_0              0x1d58
+#define RADEON_PP_ROT_MATRIX_1              0x1d5c
+#define RADEON_PP_TXFILTER_0                0x1c54
+#define RADEON_PP_TXFILTER_1                0x1c6c
+#define RADEON_PP_TXFILTER_2                0x1c84
+#       define RADEON_MAG_FILTER_NEAREST                   (0  <<  0)
+#       define RADEON_MAG_FILTER_LINEAR                    (1  <<  0)
+#       define RADEON_MAG_FILTER_MASK                      (1  <<  0)
+#       define RADEON_MIN_FILTER_NEAREST                   (0  <<  1)
+#       define RADEON_MIN_FILTER_LINEAR                    (1  <<  1)
+#       define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST       (2  <<  1)
+#       define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR        (3  <<  1)
+#       define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST        (6  <<  1)
+#       define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR         (7  <<  1)
+#       define RADEON_MIN_FILTER_ANISO_NEAREST             (8  <<  1)
+#       define RADEON_MIN_FILTER_ANISO_LINEAR              (9  <<  1)
+#       define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 <<  1)
+#       define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR  (11 <<  1)
+#       define RADEON_MIN_FILTER_MASK                      (15 <<  1)
+#       define RADEON_MAX_ANISO_1_TO_1                     (0  <<  5)
+#       define RADEON_MAX_ANISO_2_TO_1                     (1  <<  5)
+#       define RADEON_MAX_ANISO_4_TO_1                     (2  <<  5)
+#       define RADEON_MAX_ANISO_8_TO_1                     (3  <<  5)
+#       define RADEON_MAX_ANISO_16_TO_1                    (4  <<  5)
+#       define RADEON_MAX_ANISO_MASK                       (7  <<  5)
+#       define RADEON_LOD_BIAS_MASK                        (0xff <<  8)
+#       define RADEON_LOD_BIAS_SHIFT                       8
+#       define RADEON_MAX_MIP_LEVEL_MASK                   (0x0f << 16)
+#       define RADEON_MAX_MIP_LEVEL_SHIFT                  16
+#       define RADEON_YUV_TO_RGB                           (1  << 20)
+#       define RADEON_YUV_TEMPERATURE_COOL                 (0  << 21)
+#       define RADEON_YUV_TEMPERATURE_HOT                  (1  << 21)
+#       define RADEON_YUV_TEMPERATURE_MASK                 (1  << 21)
+#       define RADEON_WRAPEN_S                             (1  << 22)
+#       define RADEON_CLAMP_S_WRAP                         (0  << 23)
+#       define RADEON_CLAMP_S_MIRROR                       (1  << 23)
+#       define RADEON_CLAMP_S_CLAMP_LAST                   (2  << 23)
+#       define RADEON_CLAMP_S_MIRROR_CLAMP_LAST            (3  << 23)
+#       define RADEON_CLAMP_S_CLAMP_BORDER                 (4  << 23)
+#       define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER          (5  << 23)
+#       define RADEON_CLAMP_S_CLAMP_GL                     (6  << 23)
+#       define RADEON_CLAMP_S_MIRROR_CLAMP_GL              (7  << 23)
+#       define RADEON_CLAMP_S_MASK                         (7  << 23)
+#       define RADEON_WRAPEN_T                             (1  << 26)
+#       define RADEON_CLAMP_T_WRAP                         (0  << 27)
+#       define RADEON_CLAMP_T_MIRROR                       (1  << 27)
+#       define RADEON_CLAMP_T_CLAMP_LAST                   (2  << 27)
+#       define RADEON_CLAMP_T_MIRROR_CLAMP_LAST            (3  << 27)
+#       define RADEON_CLAMP_T_CLAMP_BORDER                 (4  << 27)
+#       define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER          (5  << 27)
+#       define RADEON_CLAMP_T_CLAMP_GL                     (6  << 27)
+#       define RADEON_CLAMP_T_MIRROR_CLAMP_GL              (7  << 27)
+#       define RADEON_CLAMP_T_MASK                         (7  << 27)
+#       define RADEON_BORDER_MODE_OGL                      (0  << 31)
+#       define RADEON_BORDER_MODE_D3D                      (1  << 31)
+#define RADEON_PP_TXFORMAT_0                0x1c58
+#define RADEON_PP_TXFORMAT_1                0x1c70
+#define RADEON_PP_TXFORMAT_2                0x1c88
+#       define RADEON_TXFORMAT_I8                 (0  <<  0)
+#       define RADEON_TXFORMAT_AI88               (1  <<  0)
+#       define RADEON_TXFORMAT_RGB332             (2  <<  0)
+#       define RADEON_TXFORMAT_ARGB1555           (3  <<  0)
+#       define RADEON_TXFORMAT_RGB565             (4  <<  0)
+#       define RADEON_TXFORMAT_ARGB4444           (5  <<  0)
+#       define RADEON_TXFORMAT_ARGB8888           (6  <<  0)
+#       define RADEON_TXFORMAT_RGBA8888           (7  <<  0)
+#       define RADEON_TXFORMAT_Y8                 (8  <<  0)
+#       define RADEON_TXFORMAT_VYUY422            (10 <<  0)
+#       define RADEON_TXFORMAT_YVYU422            (11 <<  0)
+#       define RADEON_TXFORMAT_DXT1               (12 <<  0)
+#       define RADEON_TXFORMAT_DXT23              (14 <<  0)
+#       define RADEON_TXFORMAT_DXT45              (15 <<  0)
+#       define RADEON_TXFORMAT_FORMAT_MASK        (31 <<  0)
+#       define RADEON_TXFORMAT_FORMAT_SHIFT       0
+#       define RADEON_TXFORMAT_APPLE_YUV_MODE     (1  <<  5)
+#       define RADEON_TXFORMAT_ALPHA_IN_MAP       (1  <<  6)
+#       define RADEON_TXFORMAT_NON_POWER2         (1  <<  7)
+#       define RADEON_TXFORMAT_WIDTH_MASK         (15 <<  8)
+#       define RADEON_TXFORMAT_WIDTH_SHIFT        8
+#       define RADEON_TXFORMAT_HEIGHT_MASK        (15 << 12)
+#       define RADEON_TXFORMAT_HEIGHT_SHIFT       12
+#       define RADEON_TXFORMAT_F5_WIDTH_MASK      (15 << 16)
+#       define RADEON_TXFORMAT_F5_WIDTH_SHIFT     16
+#       define RADEON_TXFORMAT_F5_HEIGHT_MASK     (15 << 20)
+#       define RADEON_TXFORMAT_F5_HEIGHT_SHIFT    20
+#       define RADEON_TXFORMAT_ST_ROUTE_STQ0      (0  << 24)
+#       define RADEON_TXFORMAT_ST_ROUTE_MASK      (3  << 24)
+#       define RADEON_TXFORMAT_ST_ROUTE_STQ1      (1  << 24)
+#       define RADEON_TXFORMAT_ST_ROUTE_STQ2      (2  << 24)
+#       define RADEON_TXFORMAT_ENDIAN_NO_SWAP     (0  << 26)
+#       define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP  (1  << 26)
+#       define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP  (2  << 26)
+#       define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3  << 26)
+#       define RADEON_TXFORMAT_ALPHA_MASK_ENABLE  (1  << 28)
+#       define RADEON_TXFORMAT_CHROMA_KEY_ENABLE  (1  << 29)
+#       define RADEON_TXFORMAT_CUBIC_MAP_ENABLE   (1  << 30)
+#       define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1  << 31)
+#define RADEON_PP_CUBIC_FACES_0             0x1d24
+#define RADEON_PP_CUBIC_FACES_1             0x1d28
+#define RADEON_PP_CUBIC_FACES_2             0x1d2c
+#       define RADEON_FACE_WIDTH_1_SHIFT          0
+#       define RADEON_FACE_HEIGHT_1_SHIFT         4
+#       define RADEON_FACE_WIDTH_1_MASK           (0xf << 0)
+#       define RADEON_FACE_HEIGHT_1_MASK          (0xf << 4)
+#       define RADEON_FACE_WIDTH_2_SHIFT          8
+#       define RADEON_FACE_HEIGHT_2_SHIFT         12
+#       define RADEON_FACE_WIDTH_2_MASK           (0xf << 8)
+#       define RADEON_FACE_HEIGHT_2_MASK          (0xf << 12)
+#       define RADEON_FACE_WIDTH_3_SHIFT          16
+#       define RADEON_FACE_HEIGHT_3_SHIFT         20
+#       define RADEON_FACE_WIDTH_3_MASK           (0xf << 16)
+#       define RADEON_FACE_HEIGHT_3_MASK          (0xf << 20)
+#       define RADEON_FACE_WIDTH_4_SHIFT          24
+#       define RADEON_FACE_HEIGHT_4_SHIFT         28
+#       define RADEON_FACE_WIDTH_4_MASK           (0xf << 24)
+#       define RADEON_FACE_HEIGHT_4_MASK          (0xf << 28)
+
+#define RADEON_PP_TXOFFSET_0                0x1c5c
+#define RADEON_PP_TXOFFSET_1                0x1c74
+#define RADEON_PP_TXOFFSET_2                0x1c8c
+#       define RADEON_TXO_ENDIAN_NO_SWAP     (0 << 0)
+#       define RADEON_TXO_ENDIAN_BYTE_SWAP   (1 << 0)
+#       define RADEON_TXO_ENDIAN_WORD_SWAP   (2 << 0)
+#       define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
+#       define RADEON_TXO_MACRO_LINEAR       (0 << 2)
+#       define RADEON_TXO_MACRO_TILE         (1 << 2)
+#       define RADEON_TXO_MICRO_LINEAR       (0 << 3)
+#       define RADEON_TXO_MICRO_TILE_X2      (1 << 3)
+#       define RADEON_TXO_MICRO_TILE_OPT     (2 << 3)
+#       define RADEON_TXO_OFFSET_MASK        0xffffffe0
+#       define RADEON_TXO_OFFSET_SHIFT       5
+
+#define RADEON_PP_CUBIC_OFFSET_T0_0         0x1dd0  /* bits [31:5] */
+#define RADEON_PP_CUBIC_OFFSET_T0_1         0x1dd4
+#define RADEON_PP_CUBIC_OFFSET_T0_2         0x1dd8
+#define RADEON_PP_CUBIC_OFFSET_T0_3         0x1ddc
+#define RADEON_PP_CUBIC_OFFSET_T0_4         0x1de0
+#define RADEON_PP_CUBIC_OFFSET_T1_0         0x1e00
+#define RADEON_PP_CUBIC_OFFSET_T1_1         0x1e04
+#define RADEON_PP_CUBIC_OFFSET_T1_2         0x1e08
+#define RADEON_PP_CUBIC_OFFSET_T1_3         0x1e0c
+#define RADEON_PP_CUBIC_OFFSET_T1_4         0x1e10
+#define RADEON_PP_CUBIC_OFFSET_T2_0         0x1e14
+#define RADEON_PP_CUBIC_OFFSET_T2_1         0x1e18
+#define RADEON_PP_CUBIC_OFFSET_T2_2         0x1e1c
+#define RADEON_PP_CUBIC_OFFSET_T2_3         0x1e20
+#define RADEON_PP_CUBIC_OFFSET_T2_4         0x1e24
+
+#define RADEON_PP_TEX_SIZE_0                0x1d04  /* NPOT */
+#define RADEON_PP_TEX_SIZE_1                0x1d0c
+#define RADEON_PP_TEX_SIZE_2                0x1d14
+#       define RADEON_TEX_USIZE_MASK        (0x7ff << 0)
+#       define RADEON_TEX_USIZE_SHIFT       0
+#       define RADEON_TEX_VSIZE_MASK        (0x7ff << 16)
+#       define RADEON_TEX_VSIZE_SHIFT       16
+#       define RADEON_SIGNED_RGB_MASK       (1 << 30)
+#       define RADEON_SIGNED_RGB_SHIFT      30
+#       define RADEON_SIGNED_ALPHA_MASK     (1 << 31)
+#       define RADEON_SIGNED_ALPHA_SHIFT    31
+#define RADEON_PP_TEX_PITCH_0               0x1d08  /* NPOT */
+#define RADEON_PP_TEX_PITCH_1               0x1d10  /* NPOT */
+#define RADEON_PP_TEX_PITCH_2               0x1d18  /* NPOT */
+/* note: bits 13-5: 32 byte aligned stride of texture map */
+
+#define RADEON_PP_TXCBLEND_0                0x1c60
+#define RADEON_PP_TXCBLEND_1                0x1c78
+#define RADEON_PP_TXCBLEND_2                0x1c90
+#       define RADEON_COLOR_ARG_A_SHIFT          0
+#       define RADEON_COLOR_ARG_A_MASK           (0x1f << 0)
+#       define RADEON_COLOR_ARG_A_ZERO           (0    << 0)
+#       define RADEON_COLOR_ARG_A_CURRENT_COLOR  (2    << 0)
+#       define RADEON_COLOR_ARG_A_CURRENT_ALPHA  (3    << 0)
+#       define RADEON_COLOR_ARG_A_DIFFUSE_COLOR  (4    << 0)
+#       define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA  (5    << 0)
+#       define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6    << 0)
+#       define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7    << 0)
+#       define RADEON_COLOR_ARG_A_TFACTOR_COLOR  (8    << 0)
+#       define RADEON_COLOR_ARG_A_TFACTOR_ALPHA  (9    << 0)
+#       define RADEON_COLOR_ARG_A_T0_COLOR       (10   << 0)
+#       define RADEON_COLOR_ARG_A_T0_ALPHA       (11   << 0)
+#       define RADEON_COLOR_ARG_A_T1_COLOR       (12   << 0)
+#       define RADEON_COLOR_ARG_A_T1_ALPHA       (13   << 0)
+#       define RADEON_COLOR_ARG_A_T2_COLOR       (14   << 0)
+#       define RADEON_COLOR_ARG_A_T2_ALPHA       (15   << 0)
+#       define RADEON_COLOR_ARG_A_T3_COLOR       (16   << 0)
+#       define RADEON_COLOR_ARG_A_T3_ALPHA       (17   << 0)
+#       define RADEON_COLOR_ARG_B_SHIFT          5
+#       define RADEON_COLOR_ARG_B_MASK           (0x1f << 5)
+#       define RADEON_COLOR_ARG_B_ZERO           (0    << 5)
+#       define RADEON_COLOR_ARG_B_CURRENT_COLOR  (2    << 5)
+#       define RADEON_COLOR_ARG_B_CURRENT_ALPHA  (3    << 5)
+#       define RADEON_COLOR_ARG_B_DIFFUSE_COLOR  (4    << 5)
+#       define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA  (5    << 5)
+#       define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6    << 5)
+#       define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7    << 5)
+#       define RADEON_COLOR_ARG_B_TFACTOR_COLOR  (8    << 5)
+#       define RADEON_COLOR_ARG_B_TFACTOR_ALPHA  (9    << 5)
+#       define RADEON_COLOR_ARG_B_T0_COLOR       (10   << 5)
+#       define RADEON_COLOR_ARG_B_T0_ALPHA       (11   << 5)
+#       define RADEON_COLOR_ARG_B_T1_COLOR       (12   << 5)
+#       define RADEON_COLOR_ARG_B_T1_ALPHA       (13   << 5)
+#       define RADEON_COLOR_ARG_B_T2_COLOR       (14   << 5)
+#       define RADEON_COLOR_ARG_B_T2_ALPHA       (15   << 5)
+#       define RADEON_COLOR_ARG_B_T3_COLOR       (16   << 5)
+#       define RADEON_COLOR_ARG_B_T3_ALPHA       (17   << 5)
+#       define RADEON_COLOR_ARG_C_SHIFT          10
+#       define RADEON_COLOR_ARG_C_MASK           (0x1f << 10)
+#       define RADEON_COLOR_ARG_C_ZERO           (0    << 10)
+#       define RADEON_COLOR_ARG_C_CURRENT_COLOR  (2    << 10)
+#       define RADEON_COLOR_ARG_C_CURRENT_ALPHA  (3    << 10)
+#       define RADEON_COLOR_ARG_C_DIFFUSE_COLOR  (4    << 10)
+#       define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA  (5    << 10)
+#       define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6    << 10)
+#       define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7    << 10)
+#       define RADEON_COLOR_ARG_C_TFACTOR_COLOR  (8    << 10)
+#       define RADEON_COLOR_ARG_C_TFACTOR_ALPHA  (9    << 10)
+#       define RADEON_COLOR_ARG_C_T0_COLOR       (10   << 10)
+#       define RADEON_COLOR_ARG_C_T0_ALPHA       (11   << 10)
+#       define RADEON_COLOR_ARG_C_T1_COLOR       (12   << 10)
+#       define RADEON_COLOR_ARG_C_T1_ALPHA       (13   << 10)
+#       define RADEON_COLOR_ARG_C_T2_COLOR       (14   << 10)
+#       define RADEON_COLOR_ARG_C_T2_ALPHA       (15   << 10)
+#       define RADEON_COLOR_ARG_C_T3_COLOR       (16   << 10)
+#       define RADEON_COLOR_ARG_C_T3_ALPHA       (17   << 10)
+#       define RADEON_COMP_ARG_A                 (1 << 15)
+#       define RADEON_COMP_ARG_A_SHIFT           15
+#       define RADEON_COMP_ARG_B                 (1 << 16)
+#       define RADEON_COMP_ARG_B_SHIFT           16
+#       define RADEON_COMP_ARG_C                 (1 << 17)
+#       define RADEON_COMP_ARG_C_SHIFT           17
+#       define RADEON_BLEND_CTL_MASK             (7 << 18)
+#       define RADEON_BLEND_CTL_ADD              (0 << 18)
+#       define RADEON_BLEND_CTL_SUBTRACT         (1 << 18)
+#       define RADEON_BLEND_CTL_ADDSIGNED        (2 << 18)
+#       define RADEON_BLEND_CTL_BLEND            (3 << 18)
+#       define RADEON_BLEND_CTL_DOT3             (4 << 18)
+#       define RADEON_SCALE_SHIFT                21
+#       define RADEON_SCALE_MASK                 (3 << 21)
+#       define RADEON_SCALE_1X                   (0 << 21)
+#       define RADEON_SCALE_2X                   (1 << 21)
+#       define RADEON_SCALE_4X                   (2 << 21)
+#       define RADEON_CLAMP_TX                   (1 << 23)
+#       define RADEON_T0_EQ_TCUR                 (1 << 24)
+#       define RADEON_T1_EQ_TCUR                 (1 << 25)
+#       define RADEON_T2_EQ_TCUR                 (1 << 26)
+#       define RADEON_T3_EQ_TCUR                 (1 << 27)
+#       define RADEON_COLOR_ARG_MASK             0x1f
+#       define RADEON_COMP_ARG_SHIFT             15
+#define RADEON_PP_TXABLEND_0                0x1c64
+#define RADEON_PP_TXABLEND_1                0x1c7c
+#define RADEON_PP_TXABLEND_2                0x1c94
+#       define RADEON_ALPHA_ARG_A_SHIFT          0
+#       define RADEON_ALPHA_ARG_A_MASK           (0xf << 0)
+#       define RADEON_ALPHA_ARG_A_ZERO           (0   << 0)
+#       define RADEON_ALPHA_ARG_A_CURRENT_ALPHA  (1   << 0)
+#       define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA  (2   << 0)
+#       define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3   << 0)
+#       define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA  (4   << 0)
+#       define RADEON_ALPHA_ARG_A_T0_ALPHA       (5   << 0)
+#       define RADEON_ALPHA_ARG_A_T1_ALPHA       (6   << 0)
+#       define RADEON_ALPHA_ARG_A_T2_ALPHA       (7   << 0)
+#       define RADEON_ALPHA_ARG_A_T3_ALPHA       (8   << 0)
+#       define RADEON_ALPHA_ARG_B_SHIFT          4
+#       define RADEON_ALPHA_ARG_B_MASK           (0xf << 4)
+#       define RADEON_ALPHA_ARG_B_ZERO           (0   << 4)
+#       define RADEON_ALPHA_ARG_B_CURRENT_ALPHA  (1   << 4)
+#       define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA  (2   << 4)
+#       define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3   << 4)
+#       define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA  (4   << 4)
+#       define RADEON_ALPHA_ARG_B_T0_ALPHA       (5   << 4)
+#       define RADEON_ALPHA_ARG_B_T1_ALPHA       (6   << 4)
+#       define RADEON_ALPHA_ARG_B_T2_ALPHA       (7   << 4)
+#       define RADEON_ALPHA_ARG_B_T3_ALPHA       (8   << 4)
+#       define RADEON_ALPHA_ARG_C_SHIFT          8
+#       define RADEON_ALPHA_ARG_C_MASK           (0xf << 8)
+#       define RADEON_ALPHA_ARG_C_ZERO           (0   << 8)
+#       define RADEON_ALPHA_ARG_C_CURRENT_ALPHA  (1   << 8)
+#       define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA  (2   << 8)
+#       define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3   << 8)
+#       define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA  (4   << 8)
+#       define RADEON_ALPHA_ARG_C_T0_ALPHA       (5   << 8)
+#       define RADEON_ALPHA_ARG_C_T1_ALPHA       (6   << 8)
+#       define RADEON_ALPHA_ARG_C_T2_ALPHA       (7   << 8)
+#       define RADEON_ALPHA_ARG_C_T3_ALPHA       (8   << 8)
+#       define RADEON_DOT_ALPHA_DONT_REPLICATE   (1   << 9)
+#       define RADEON_ALPHA_ARG_MASK             0xf
+
+#define RADEON_PP_TFACTOR_0                 0x1c68
+#define RADEON_PP_TFACTOR_1                 0x1c80
+#define RADEON_PP_TFACTOR_2                 0x1c98
+
+#define RADEON_RB3D_BLENDCNTL               0x1c20
+#       define RADEON_COMB_FCN_MASK                    (3  << 12)
+#       define RADEON_COMB_FCN_ADD_CLAMP               (0  << 12)
+#       define RADEON_COMB_FCN_ADD_NOCLAMP             (1  << 12)
+#       define RADEON_COMB_FCN_SUB_CLAMP               (2  << 12)
+#       define RADEON_COMB_FCN_SUB_NOCLAMP             (3  << 12)
+#       define RADEON_SRC_BLEND_GL_ZERO                (32 << 16)
+#       define RADEON_SRC_BLEND_GL_ONE                 (33 << 16)
+#       define RADEON_SRC_BLEND_GL_SRC_COLOR           (34 << 16)
+#       define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
+#       define RADEON_SRC_BLEND_GL_DST_COLOR           (36 << 16)
+#       define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
+#       define RADEON_SRC_BLEND_GL_SRC_ALPHA           (38 << 16)
+#       define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
+#       define RADEON_SRC_BLEND_GL_DST_ALPHA           (40 << 16)
+#       define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
+#       define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE  (42 << 16)
+#       define RADEON_SRC_BLEND_MASK                   (63 << 16)
+#       define RADEON_DST_BLEND_GL_ZERO                (32 << 24)
+#       define RADEON_DST_BLEND_GL_ONE                 (33 << 24)
+#       define RADEON_DST_BLEND_GL_SRC_COLOR           (34 << 24)
+#       define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
+#       define RADEON_DST_BLEND_GL_DST_COLOR           (36 << 24)
+#       define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
+#       define RADEON_DST_BLEND_GL_SRC_ALPHA           (38 << 24)
+#       define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
+#       define RADEON_DST_BLEND_GL_DST_ALPHA           (40 << 24)
+#       define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
+#       define RADEON_DST_BLEND_MASK                   (63 << 24)
+#define RADEON_RB3D_CNTL                    0x1c3c
+#       define RADEON_ALPHA_BLEND_ENABLE       (1  <<  0)
+#       define RADEON_PLANE_MASK_ENABLE        (1  <<  1)
+#       define RADEON_DITHER_ENABLE            (1  <<  2)
+#       define RADEON_ROUND_ENABLE             (1  <<  3)
+#       define RADEON_SCALE_DITHER_ENABLE      (1  <<  4)
+#       define RADEON_DITHER_INIT              (1  <<  5)
+#       define RADEON_ROP_ENABLE               (1  <<  6)
+#       define RADEON_STENCIL_ENABLE           (1  <<  7)
+#       define RADEON_Z_ENABLE                 (1  <<  8)
+#       define RADEON_DEPTH_XZ_OFFEST_ENABLE   (1  <<  9)
+#       define RADEON_RB3D_COLOR_FORMAT_SHIFT  10
+
+#       define RADEON_COLOR_FORMAT_ARGB1555    3
+#       define RADEON_COLOR_FORMAT_RGB565      4
+#       define RADEON_COLOR_FORMAT_ARGB8888    6
+#       define RADEON_COLOR_FORMAT_RGB332      7
+#       define RADEON_COLOR_FORMAT_Y8          8
+#       define RADEON_COLOR_FORMAT_RGB8        9
+#       define RADEON_COLOR_FORMAT_YUV422_VYUY 11
+#       define RADEON_COLOR_FORMAT_YUV422_YVYU 12
+#       define RADEON_COLOR_FORMAT_aYUV444     14
+#       define RADEON_COLOR_FORMAT_ARGB4444    15
+
+#       define RADEON_CLRCMP_FLIP_ENABLE       (1  << 14)
+#define RADEON_RB3D_COLOROFFSET             0x1c40
+#       define RADEON_COLOROFFSET_MASK      0xfffffff0
+#define RADEON_RB3D_COLORPITCH              0x1c48
+#       define RADEON_COLORPITCH_MASK         0x000001ff8
+#       define RADEON_COLOR_TILE_ENABLE       (1 << 16)
+#       define RADEON_COLOR_MICROTILE_ENABLE  (1 << 17)
+#       define RADEON_COLOR_ENDIAN_NO_SWAP    (0 << 18)
+#       define RADEON_COLOR_ENDIAN_WORD_SWAP  (1 << 18)
+#       define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
+#define RADEON_RB3D_DEPTHOFFSET             0x1c24
+#define RADEON_RB3D_DEPTHPITCH              0x1c28
+#       define RADEON_DEPTHPITCH_MASK         0x00001ff8
+#       define RADEON_DEPTH_ENDIAN_NO_SWAP    (0 << 18)
+#       define RADEON_DEPTH_ENDIAN_WORD_SWAP  (1 << 18)
+#       define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)
+#define RADEON_RB3D_PLANEMASK               0x1d84
+#define RADEON_RB3D_ROPCNTL                 0x1d80
+#       define RADEON_ROP_MASK              (15 << 8)
+#       define RADEON_ROP_CLEAR             (0  << 8)
+#       define RADEON_ROP_NOR               (1  << 8)
+#       define RADEON_ROP_AND_INVERTED      (2  << 8)
+#       define RADEON_ROP_COPY_INVERTED     (3  << 8)
+#       define RADEON_ROP_AND_REVERSE       (4  << 8)
+#       define RADEON_ROP_INVERT            (5  << 8)
+#       define RADEON_ROP_XOR               (6  << 8)
+#       define RADEON_ROP_NAND              (7  << 8)
+#       define RADEON_ROP_AND               (8  << 8)
+#       define RADEON_ROP_EQUIV             (9  << 8)
+#       define RADEON_ROP_NOOP              (10 << 8)
+#       define RADEON_ROP_OR_INVERTED       (11 << 8)
+#       define RADEON_ROP_COPY              (12 << 8)
+#       define RADEON_ROP_OR_REVERSE        (13 << 8)
+#       define RADEON_ROP_OR                (14 << 8)
+#       define RADEON_ROP_SET               (15 << 8)
+#define RADEON_RB3D_STENCILREFMASK          0x1d7c
+#       define RADEON_STENCIL_REF_SHIFT       0
+#       define RADEON_STENCIL_REF_MASK        (0xff << 0)
+#       define RADEON_STENCIL_MASK_SHIFT      16
+#       define RADEON_STENCIL_VALUE_MASK      (0xff << 16)
+#       define RADEON_STENCIL_WRITEMASK_SHIFT 24
+#       define RADEON_STENCIL_WRITE_MASK      (0xff << 24)
+#define RADEON_RB3D_ZSTENCILCNTL            0x1c2c
+#       define RADEON_DEPTH_FORMAT_MASK          (0xf << 0)
+#       define RADEON_DEPTH_FORMAT_16BIT_INT_Z   (0  <<  0)
+#       define RADEON_DEPTH_FORMAT_24BIT_INT_Z   (2  <<  0)
+#       define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3  <<  0)
+#       define RADEON_DEPTH_FORMAT_32BIT_INT_Z   (4  <<  0)
+#       define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5  <<  0)
+#       define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7  <<  0)
+#       define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9  <<  0)
+#       define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 <<  0)
+#       define RADEON_Z_TEST_NEVER               (0  <<  4)
+#       define RADEON_Z_TEST_LESS                (1  <<  4)
+#       define RADEON_Z_TEST_LEQUAL              (2  <<  4)
+#       define RADEON_Z_TEST_EQUAL               (3  <<  4)
+#       define RADEON_Z_TEST_GEQUAL              (4  <<  4)
+#       define RADEON_Z_TEST_GREATER             (5  <<  4)
+#       define RADEON_Z_TEST_NEQUAL              (6  <<  4)
+#       define RADEON_Z_TEST_ALWAYS              (7  <<  4)
+#       define RADEON_Z_TEST_MASK                (7  <<  4)
+#       define RADEON_STENCIL_TEST_NEVER         (0  << 12)
+#       define RADEON_STENCIL_TEST_LESS          (1  << 12)
+#       define RADEON_STENCIL_TEST_LEQUAL        (2  << 12)
+#       define RADEON_STENCIL_TEST_EQUAL         (3  << 12)
+#       define RADEON_STENCIL_TEST_GEQUAL        (4  << 12)
+#       define RADEON_STENCIL_TEST_GREATER       (5  << 12)
+#       define RADEON_STENCIL_TEST_NEQUAL        (6  << 12)
+#       define RADEON_STENCIL_TEST_ALWAYS        (7  << 12)
+#       define RADEON_STENCIL_TEST_MASK          (0x7 << 12)
+#       define RADEON_STENCIL_FAIL_KEEP          (0  << 16)
+#       define RADEON_STENCIL_FAIL_ZERO          (1  << 16)
+#       define RADEON_STENCIL_FAIL_REPLACE       (2  << 16)
+#       define RADEON_STENCIL_FAIL_INC           (3  << 16)
+#       define RADEON_STENCIL_FAIL_DEC           (4  << 16)
+#       define RADEON_STENCIL_FAIL_INVERT        (5  << 16)
+#       define RADEON_STENCIL_FAIL_MASK          (0x7 << 16)
+#       define RADEON_STENCIL_ZPASS_KEEP         (0  << 20)
+#       define RADEON_STENCIL_ZPASS_ZERO         (1  << 20)
+#       define RADEON_STENCIL_ZPASS_REPLACE      (2  << 20)
+#       define RADEON_STENCIL_ZPASS_INC          (3  << 20)
+#       define RADEON_STENCIL_ZPASS_DEC          (4  << 20)
+#       define RADEON_STENCIL_ZPASS_INVERT       (5  << 20)
+#       define RADEON_STENCIL_ZPASS_MASK         (0x7 << 20)
+#       define RADEON_STENCIL_ZFAIL_KEEP         (0  << 24)
+#       define RADEON_STENCIL_ZFAIL_ZERO         (1  << 24)
+#       define RADEON_STENCIL_ZFAIL_REPLACE      (2  << 24)
+#       define RADEON_STENCIL_ZFAIL_INC          (3  << 24)
+#       define RADEON_STENCIL_ZFAIL_DEC          (4  << 24)
+#       define RADEON_STENCIL_ZFAIL_INVERT       (5  << 24)
+#       define RADEON_STENCIL_ZFAIL_MASK         (0x7 << 24)
+#       define RADEON_Z_COMPRESSION_ENABLE       (1  << 28)
+#       define RADEON_FORCE_Z_DIRTY              (1  << 29)
+#       define RADEON_Z_WRITE_ENABLE             (1  << 30)
+#define RADEON_RE_LINE_PATTERN              0x1cd0
+#       define RADEON_LINE_PATTERN_MASK             0x0000ffff
+#       define RADEON_LINE_REPEAT_COUNT_SHIFT       16
+#       define RADEON_LINE_PATTERN_START_SHIFT      24
+#       define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)
+#       define RADEON_LINE_PATTERN_BIG_BIT_ORDER    (1 << 28)
+#       define RADEON_LINE_PATTERN_AUTO_RESET       (1 << 29)
+#define RADEON_RE_LINE_STATE                0x1cd4
+#       define RADEON_LINE_CURRENT_PTR_SHIFT   0
+#       define RADEON_LINE_CURRENT_COUNT_SHIFT 8
+#define RADEON_RE_MISC                      0x26c4
+#       define RADEON_STIPPLE_COORD_MASK       0x1f
+#       define RADEON_STIPPLE_X_OFFSET_SHIFT   0
+#       define RADEON_STIPPLE_X_OFFSET_MASK    (0x1f << 0)
+#       define RADEON_STIPPLE_Y_OFFSET_SHIFT   8
+#       define RADEON_STIPPLE_Y_OFFSET_MASK    (0x1f << 8)
+#       define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)
+#       define RADEON_STIPPLE_BIG_BIT_ORDER    (1 << 16)
+#define RADEON_RE_SOLID_COLOR               0x1c1c
+#define RADEON_RE_TOP_LEFT                  0x26c0
+#       define RADEON_RE_LEFT_SHIFT         0
+#       define RADEON_RE_TOP_SHIFT          16
+#define RADEON_RE_WIDTH_HEIGHT              0x1c44
+#       define RADEON_RE_WIDTH_SHIFT        0
+#       define RADEON_RE_HEIGHT_SHIFT       16
+
+#define RADEON_SE_CNTL                      0x1c4c
+#       define RADEON_FFACE_CULL_CW          (0 <<  0)
+#       define RADEON_FFACE_CULL_CCW         (1 <<  0)
+#       define RADEON_FFACE_CULL_DIR_MASK    (1 <<  0)
+#       define RADEON_BFACE_CULL             (0 <<  1)
+#       define RADEON_BFACE_SOLID            (3 <<  1)
+#       define RADEON_FFACE_CULL             (0 <<  3)
+#       define RADEON_FFACE_SOLID            (3 <<  3)
+#       define RADEON_FFACE_CULL_MASK        (3 <<  3)
+#       define RADEON_BADVTX_CULL_DISABLE    (1 <<  5)
+#       define RADEON_FLAT_SHADE_VTX_0       (0 <<  6)
+#       define RADEON_FLAT_SHADE_VTX_1       (1 <<  6)
+#       define RADEON_FLAT_SHADE_VTX_2       (2 <<  6)
+#       define RADEON_FLAT_SHADE_VTX_LAST    (3 <<  6)
+#       define RADEON_DIFFUSE_SHADE_SOLID    (0 <<  8)
+#       define RADEON_DIFFUSE_SHADE_FLAT     (1 <<  8)
+#       define RADEON_DIFFUSE_SHADE_GOURAUD  (2 <<  8)
+#       define RADEON_DIFFUSE_SHADE_MASK     (3 <<  8)
+#       define RADEON_ALPHA_SHADE_SOLID      (0 << 10)
+#       define RADEON_ALPHA_SHADE_FLAT       (1 << 10)
+#       define RADEON_ALPHA_SHADE_GOURAUD    (2 << 10)
+#       define RADEON_ALPHA_SHADE_MASK       (3 << 10)
+#       define RADEON_SPECULAR_SHADE_SOLID   (0 << 12)
+#       define RADEON_SPECULAR_SHADE_FLAT    (1 << 12)
+#       define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
+#       define RADEON_SPECULAR_SHADE_MASK    (3 << 12)
+#       define RADEON_FOG_SHADE_SOLID        (0 << 14)
+#       define RADEON_FOG_SHADE_FLAT         (1 << 14)
+#       define RADEON_FOG_SHADE_GOURAUD      (2 << 14)
+#       define RADEON_FOG_SHADE_MASK         (3 << 14)
+#       define RADEON_ZBIAS_ENABLE_POINT     (1 << 16)
+#       define RADEON_ZBIAS_ENABLE_LINE      (1 << 17)
+#       define RADEON_ZBIAS_ENABLE_TRI       (1 << 18)
+#       define RADEON_WIDELINE_ENABLE        (1 << 20)
+#       define RADEON_VPORT_XY_XFORM_ENABLE  (1 << 24)
+#       define RADEON_VPORT_Z_XFORM_ENABLE   (1 << 25)
+#       define RADEON_VTX_PIX_CENTER_D3D     (0 << 27)
+#       define RADEON_VTX_PIX_CENTER_OGL     (1 << 27)
+#       define RADEON_ROUND_MODE_TRUNC       (0 << 28)
+#       define RADEON_ROUND_MODE_ROUND       (1 << 28)
+#       define RADEON_ROUND_MODE_ROUND_EVEN  (2 << 28)
+#       define RADEON_ROUND_MODE_ROUND_ODD   (3 << 28)
+#       define RADEON_ROUND_PREC_16TH_PIX    (0 << 30)
+#       define RADEON_ROUND_PREC_8TH_PIX     (1 << 30)
+#       define RADEON_ROUND_PREC_4TH_PIX     (2 << 30)
+#       define RADEON_ROUND_PREC_HALF_PIX    (3 << 30)
+#define R200_RE_CNTL                            0x1c50
+#       define R200_STIPPLE_ENABLE              0x1
+#       define R200_SCISSOR_ENABLE              0x2
+#       define R200_PATTERN_ENABLE              0x4
+#       define R200_PERSPECTIVE_ENABLE          0x8
+#       define R200_POINT_SMOOTH                0x20
+#       define R200_VTX_STQ0_D3D                0x00010000
+#       define R200_VTX_STQ1_D3D                0x00040000
+#       define R200_VTX_STQ2_D3D                0x00100000
+#       define R200_VTX_STQ3_D3D                0x00400000
+#       define R200_VTX_STQ4_D3D                0x01000000
+#       define R200_VTX_STQ5_D3D                0x04000000
+#define RADEON_SE_CNTL_STATUS               0x2140
+#       define RADEON_VC_NO_SWAP            (0 << 0)
+#       define RADEON_VC_16BIT_SWAP         (1 << 0)
+#       define RADEON_VC_32BIT_SWAP         (2 << 0)
+#       define RADEON_VC_HALF_DWORD_SWAP    (3 << 0)
+#       define RADEON_TCL_BYPASS            (1 << 8)
+#define RADEON_SE_COORD_FMT                 0x1c50
+#       define RADEON_VTX_XY_PRE_MULT_1_OVER_W0  (1 <<  0)
+#       define RADEON_VTX_Z_PRE_MULT_1_OVER_W0   (1 <<  1)
+#       define RADEON_VTX_ST0_NONPARAMETRIC      (1 <<  8)
+#       define RADEON_VTX_ST1_NONPARAMETRIC      (1 <<  9)
+#       define RADEON_VTX_ST2_NONPARAMETRIC      (1 << 10)
+#       define RADEON_VTX_ST3_NONPARAMETRIC      (1 << 11)
+#       define RADEON_VTX_W0_NORMALIZE           (1 << 12)
+#       define RADEON_VTX_W0_IS_NOT_1_OVER_W0    (1 << 16)
+#       define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)
+#       define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)
+#       define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)
+#       define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)
+#       define RADEON_TEX1_W_ROUTING_USE_W0      (0 << 26)
+#       define RADEON_TEX1_W_ROUTING_USE_Q1      (1 << 26)
+#define RADEON_SE_LINE_WIDTH                0x1db8
+#define RADEON_SE_TCL_LIGHT_MODEL_CTL       0x226c
+#       define RADEON_LIGHTING_ENABLE              (1 << 0)
+#       define RADEON_LIGHT_IN_MODELSPACE          (1 << 1)
+#       define RADEON_LOCAL_VIEWER                 (1 << 2)
+#       define RADEON_NORMALIZE_NORMALS            (1 << 3)
+#       define RADEON_RESCALE_NORMALS              (1 << 4)
+#       define RADEON_SPECULAR_LIGHTS              (1 << 5)
+#       define RADEON_DIFFUSE_SPECULAR_COMBINE     (1 << 6)
+#       define RADEON_LIGHT_ALPHA                  (1 << 7)
+#       define RADEON_LOCAL_LIGHT_VEC_GL           (1 << 8)
+#       define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)
+#       define RADEON_LM_SOURCE_STATE_PREMULT      0
+#       define RADEON_LM_SOURCE_STATE_MULT         1
+#       define RADEON_LM_SOURCE_VERTEX_DIFFUSE     2
+#       define RADEON_LM_SOURCE_VERTEX_SPECULAR    3
+#       define RADEON_EMISSIVE_SOURCE_SHIFT        16
+#       define RADEON_AMBIENT_SOURCE_SHIFT         18
+#       define RADEON_DIFFUSE_SOURCE_SHIFT         20
+#       define RADEON_SPECULAR_SOURCE_SHIFT        22
+#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED     0x2220
+#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN   0x2224
+#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE    0x2228
+#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA   0x222c
+#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED     0x2230
+#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN   0x2234
+#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE    0x2238
+#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA   0x223c
+#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED   0x2210
+#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214
+#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE  0x2218
+#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c
+#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED    0x2240
+#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN  0x2244
+#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE   0x2248
+#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA  0x224c
+#define RADEON_SE_TCL_MATRIX_SELECT_0       0x225c
+#       define RADEON_MODELVIEW_0_SHIFT        0
+#       define RADEON_MODELVIEW_1_SHIFT        4
+#       define RADEON_MODELVIEW_2_SHIFT        8
+#       define RADEON_MODELVIEW_3_SHIFT        12
+#       define RADEON_IT_MODELVIEW_0_SHIFT     16
+#       define RADEON_IT_MODELVIEW_1_SHIFT     20
+#       define RADEON_IT_MODELVIEW_2_SHIFT     24
+#       define RADEON_IT_MODELVIEW_3_SHIFT     28
+#define RADEON_SE_TCL_MATRIX_SELECT_1       0x2260
+#       define RADEON_MODELPROJECT_0_SHIFT     0
+#       define RADEON_MODELPROJECT_1_SHIFT     4
+#       define RADEON_MODELPROJECT_2_SHIFT     8
+#       define RADEON_MODELPROJECT_3_SHIFT     12
+#       define RADEON_TEXMAT_0_SHIFT           16
+#       define RADEON_TEXMAT_1_SHIFT           20
+#       define RADEON_TEXMAT_2_SHIFT           24
+#       define RADEON_TEXMAT_3_SHIFT           28
+
+
+#define RADEON_SE_TCL_OUTPUT_VTX_FMT        0x2254
+#       define RADEON_TCL_VTX_W0                 (1 <<  0)
+#       define RADEON_TCL_VTX_FP_DIFFUSE         (1 <<  1)
+#       define RADEON_TCL_VTX_FP_ALPHA           (1 <<  2)
+#       define RADEON_TCL_VTX_PK_DIFFUSE         (1 <<  3)
+#       define RADEON_TCL_VTX_FP_SPEC            (1 <<  4)
+#       define RADEON_TCL_VTX_FP_FOG             (1 <<  5)
+#       define RADEON_TCL_VTX_PK_SPEC            (1 <<  6)
+#       define RADEON_TCL_VTX_ST0                (1 <<  7)
+#       define RADEON_TCL_VTX_ST1                (1 <<  8)
+#       define RADEON_TCL_VTX_Q1                 (1 <<  9)
+#       define RADEON_TCL_VTX_ST2                (1 << 10)
+#       define RADEON_TCL_VTX_Q2                 (1 << 11)
+#       define RADEON_TCL_VTX_ST3                (1 << 12)
+#       define RADEON_TCL_VTX_Q3                 (1 << 13)
+#       define RADEON_TCL_VTX_Q0                 (1 << 14)
+#       define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15
+#       define RADEON_TCL_VTX_NORM0              (1 << 18)
+#       define RADEON_TCL_VTX_XY1                (1 << 27)
+#       define RADEON_TCL_VTX_Z1                 (1 << 28)
+#       define RADEON_TCL_VTX_W1                 (1 << 29)
+#       define RADEON_TCL_VTX_NORM1              (1 << 30)
+#       define RADEON_TCL_VTX_Z0                 (1 << 31)
+
+#define RADEON_SE_TCL_OUTPUT_VTX_SEL        0x2258
+#       define RADEON_TCL_COMPUTE_XYZW           (1 << 0)
+#       define RADEON_TCL_COMPUTE_DIFFUSE        (1 << 1)
+#       define RADEON_TCL_COMPUTE_SPECULAR       (1 << 2)
+#       define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)
+#       define RADEON_TCL_FORCE_INORDER_PROC     (1 << 4)
+#       define RADEON_TCL_TEX_INPUT_TEX_0        0
+#       define RADEON_TCL_TEX_INPUT_TEX_1        1
+#       define RADEON_TCL_TEX_INPUT_TEX_2        2
+#       define RADEON_TCL_TEX_INPUT_TEX_3        3
+#       define RADEON_TCL_TEX_COMPUTED_TEX_0     8
+#       define RADEON_TCL_TEX_COMPUTED_TEX_1     9
+#       define RADEON_TCL_TEX_COMPUTED_TEX_2     10
+#       define RADEON_TCL_TEX_COMPUTED_TEX_3     11
+#       define RADEON_TCL_TEX_0_OUTPUT_SHIFT     16
+#       define RADEON_TCL_TEX_1_OUTPUT_SHIFT     20
+#       define RADEON_TCL_TEX_2_OUTPUT_SHIFT     24
+#       define RADEON_TCL_TEX_3_OUTPUT_SHIFT     28
+
+#define RADEON_SE_TCL_PER_LIGHT_CTL_0       0x2270
+#       define RADEON_LIGHT_0_ENABLE               (1 <<  0)
+#       define RADEON_LIGHT_0_ENABLE_AMBIENT       (1 <<  1)
+#       define RADEON_LIGHT_0_ENABLE_SPECULAR      (1 <<  2)
+#       define RADEON_LIGHT_0_IS_LOCAL             (1 <<  3)
+#       define RADEON_LIGHT_0_IS_SPOT              (1 <<  4)
+#       define RADEON_LIGHT_0_DUAL_CONE            (1 <<  5)
+#       define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN   (1 <<  6)
+#       define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 <<  7)
+#       define RADEON_LIGHT_0_SHIFT                0
+#       define RADEON_LIGHT_1_ENABLE               (1 << 16)
+#       define RADEON_LIGHT_1_ENABLE_AMBIENT       (1 << 17)
+#       define RADEON_LIGHT_1_ENABLE_SPECULAR      (1 << 18)
+#       define RADEON_LIGHT_1_IS_LOCAL             (1 << 19)
+#       define RADEON_LIGHT_1_IS_SPOT              (1 << 20)
+#       define RADEON_LIGHT_1_DUAL_CONE            (1 << 21)
+#       define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN   (1 << 22)
+#       define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)
+#       define RADEON_LIGHT_1_SHIFT                16
+#define RADEON_SE_TCL_PER_LIGHT_CTL_1       0x2274
+#       define RADEON_LIGHT_2_SHIFT            0
+#       define RADEON_LIGHT_3_SHIFT            16
+#define RADEON_SE_TCL_PER_LIGHT_CTL_2       0x2278
+#       define RADEON_LIGHT_4_SHIFT            0
+#       define RADEON_LIGHT_5_SHIFT            16
+#define RADEON_SE_TCL_PER_LIGHT_CTL_3       0x227c
+#       define RADEON_LIGHT_6_SHIFT            0
+#       define RADEON_LIGHT_7_SHIFT            16
+
+#define RADEON_SE_TCL_SHININESS             0x2250
+
+#define RADEON_SE_TCL_TEXTURE_PROC_CTL      0x2268
+#       define RADEON_TEXGEN_TEXMAT_0_ENABLE      (1 << 0)
+#       define RADEON_TEXGEN_TEXMAT_1_ENABLE      (1 << 1)
+#       define RADEON_TEXGEN_TEXMAT_2_ENABLE      (1 << 2)
+#       define RADEON_TEXGEN_TEXMAT_3_ENABLE      (1 << 3)
+#       define RADEON_TEXMAT_0_ENABLE             (1 << 4)
+#       define RADEON_TEXMAT_1_ENABLE             (1 << 5)
+#       define RADEON_TEXMAT_2_ENABLE             (1 << 6)
+#       define RADEON_TEXMAT_3_ENABLE             (1 << 7)
+#       define RADEON_TEXGEN_INPUT_MASK           0xf
+#       define RADEON_TEXGEN_INPUT_TEXCOORD_0     0
+#       define RADEON_TEXGEN_INPUT_TEXCOORD_1     1
+#       define RADEON_TEXGEN_INPUT_TEXCOORD_2     2
+#       define RADEON_TEXGEN_INPUT_TEXCOORD_3     3
+#       define RADEON_TEXGEN_INPUT_OBJ            4
+#       define RADEON_TEXGEN_INPUT_EYE            5
+#       define RADEON_TEXGEN_INPUT_EYE_NORMAL     6
+#       define RADEON_TEXGEN_INPUT_EYE_REFLECT    7
+#       define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8
+#       define RADEON_TEXGEN_0_INPUT_SHIFT        16
+#       define RADEON_TEXGEN_1_INPUT_SHIFT        20
+#       define RADEON_TEXGEN_2_INPUT_SHIFT        24
+#       define RADEON_TEXGEN_3_INPUT_SHIFT        28
+
+#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL    0x2264
+#       define RADEON_UCP_IN_CLIP_SPACE            (1 <<  0)
+#       define RADEON_UCP_IN_MODEL_SPACE           (1 <<  1)
+#       define RADEON_UCP_ENABLE_0                 (1 <<  2)
+#       define RADEON_UCP_ENABLE_1                 (1 <<  3)
+#       define RADEON_UCP_ENABLE_2                 (1 <<  4)
+#       define RADEON_UCP_ENABLE_3                 (1 <<  5)
+#       define RADEON_UCP_ENABLE_4                 (1 <<  6)
+#       define RADEON_UCP_ENABLE_5                 (1 <<  7)
+#       define RADEON_TCL_FOG_MASK                 (3 <<  8)
+#       define RADEON_TCL_FOG_DISABLE              (0 <<  8)
+#       define RADEON_TCL_FOG_EXP                  (1 <<  8)
+#       define RADEON_TCL_FOG_EXP2                 (2 <<  8)
+#       define RADEON_TCL_FOG_LINEAR               (3 <<  8)
+#       define RADEON_RNG_BASED_FOG                (1 << 10)
+#       define RADEON_LIGHT_TWOSIDE                (1 << 11)
+#       define RADEON_BLEND_OP_COUNT_MASK          (7 << 12)
+#       define RADEON_BLEND_OP_COUNT_SHIFT         12
+#       define RADEON_POSITION_BLEND_OP_ENABLE     (1 << 16)
+#       define RADEON_NORMAL_BLEND_OP_ENABLE       (1 << 17)
+#       define RADEON_VERTEX_BLEND_SRC_0_PRIMARY   (1 << 18)
+#       define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)
+#       define RADEON_VERTEX_BLEND_SRC_1_PRIMARY   (1 << 19)
+#       define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)
+#       define RADEON_VERTEX_BLEND_SRC_2_PRIMARY   (1 << 20)
+#       define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)
+#       define RADEON_VERTEX_BLEND_SRC_3_PRIMARY   (1 << 21)
+#       define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)
+#       define RADEON_VERTEX_BLEND_WGT_MINUS_ONE   (1 << 22)
+#       define RADEON_CULL_FRONT_IS_CW             (0 << 28)
+#       define RADEON_CULL_FRONT_IS_CCW            (1 << 28)
+#       define RADEON_CULL_FRONT                   (1 << 29)
+#       define RADEON_CULL_BACK                    (1 << 30)
+#       define RADEON_FORCE_W_TO_ONE               (1 << 31)
+
+#define RADEON_SE_VPORT_XSCALE              0x1d98
+#define RADEON_SE_VPORT_XOFFSET             0x1d9c
+#define RADEON_SE_VPORT_YSCALE              0x1da0
+#define RADEON_SE_VPORT_YOFFSET             0x1da4
+#define RADEON_SE_VPORT_ZSCALE              0x1da8
+#define RADEON_SE_VPORT_ZOFFSET             0x1dac
+#define RADEON_SE_ZBIAS_FACTOR              0x1db0
+#define RADEON_SE_ZBIAS_CONSTANT            0x1db4
+
+#define RADEON_SE_VTX_FMT                   0x2080
+#       define RADEON_SE_VTX_FMT_XY         0x00000000
+#       define RADEON_SE_VTX_FMT_W0         0x00000001
+#       define RADEON_SE_VTX_FMT_FPCOLOR    0x00000002
+#       define RADEON_SE_VTX_FMT_FPALPHA    0x00000004
+#       define RADEON_SE_VTX_FMT_PKCOLOR    0x00000008
+#       define RADEON_SE_VTX_FMT_FPSPEC     0x00000010
+#       define RADEON_SE_VTX_FMT_FPFOG      0x00000020
+#       define RADEON_SE_VTX_FMT_PKSPEC     0x00000040
+#       define RADEON_SE_VTX_FMT_ST0        0x00000080
+#       define RADEON_SE_VTX_FMT_ST1        0x00000100
+#       define RADEON_SE_VTX_FMT_Q1         0x00000200
+#       define RADEON_SE_VTX_FMT_ST2        0x00000400
+#       define RADEON_SE_VTX_FMT_Q2         0x00000800
+#       define RADEON_SE_VTX_FMT_ST3        0x00001000
+#       define RADEON_SE_VTX_FMT_Q3         0x00002000
+#       define RADEON_SE_VTX_FMT_Q0         0x00004000
+#       define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK  0x00038000
+#       define RADEON_SE_VTX_FMT_N0         0x00040000
+#       define RADEON_SE_VTX_FMT_XY1        0x08000000
+#       define RADEON_SE_VTX_FMT_Z1         0x10000000
+#       define RADEON_SE_VTX_FMT_W1         0x20000000
+#       define RADEON_SE_VTX_FMT_N1         0x40000000
+#       define RADEON_SE_VTX_FMT_Z          0x80000000
+
+#define RADEON_SE_VF_CNTL                             0x2084
+#       define RADEON_VF_PRIM_TYPE_POINT_LIST         1
+#       define RADEON_VF_PRIM_TYPE_LINE_LIST          2
+#       define RADEON_VF_PRIM_TYPE_LINE_STRIP         3
+#       define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST      4
+#       define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN       5
+#       define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP     6
+#       define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG      7
+#       define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST     8
+#       define RADEON_VF_PRIM_TYPE_POINT_LIST_3       9
+#       define RADEON_VF_PRIM_TYPE_LINE_LIST_3        10
+#       define RADEON_VF_PRIM_TYPE_SPIRIT_LIST        11
+#       define RADEON_VF_PRIM_TYPE_LINE_LOOP          12
+#       define RADEON_VF_PRIM_TYPE_QUAD_LIST          13
+#       define RADEON_VF_PRIM_TYPE_QUAD_STRIP         14
+#       define RADEON_VF_PRIM_TYPE_POLYGON            15
+#       define RADEON_VF_PRIM_WALK_STATE              (0<<4)
+#       define RADEON_VF_PRIM_WALK_INDEX              (1<<4)
+#       define RADEON_VF_PRIM_WALK_LIST               (2<<4)
+#       define RADEON_VF_PRIM_WALK_DATA               (3<<4)
+#       define RADEON_VF_COLOR_ORDER_RGBA             (1<<6)
+#       define RADEON_VF_RADEON_MODE                  (1<<8)
+#       define RADEON_VF_TCL_OUTPUT_CTL_ENA           (1<<9)
+#       define RADEON_VF_PROG_STREAM_ENA              (1<<10)
+#       define RADEON_VF_INDEX_SIZE_SHIFT             11
+#       define RADEON_VF_NUM_VERTICES_SHIFT           16
+
+#define RADEON_SE_PORT_DATA0                    0x2000
+
+#define R200_SE_VAP_CNTL                        0x2080
+#       define R200_VAP_TCL_ENABLE              0x00000001
+#       define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010
+#       define R200_VAP_FORCE_W_TO_ONE          0x00010000
+#       define R200_VAP_D3D_TEX_DEFAULT         0x00020000
+#       define R200_VAP_VF_MAX_VTX_NUM__SHIFT   18
+#       define R200_VAP_VF_MAX_VTX_NUM          (9 << 18)
+#       define R200_VAP_DX_CLIP_SPACE_DEF       0x00400000
+#define R200_VF_MAX_VTX_INDX                    0x210c
+#define R200_VF_MIN_VTX_INDX                    0x2110
+#define R200_SE_VTE_CNTL                        0x20b0
+#       define R200_VPORT_X_SCALE_ENA                   0x00000001
+#       define R200_VPORT_X_OFFSET_ENA                  0x00000002
+#       define R200_VPORT_Y_SCALE_ENA                   0x00000004
+#       define R200_VPORT_Y_OFFSET_ENA                  0x00000008
+#       define R200_VPORT_Z_SCALE_ENA                   0x00000010
+#       define R200_VPORT_Z_OFFSET_ENA                  0x00000020
+#       define R200_VTX_XY_FMT                          0x00000100
+#       define R200_VTX_Z_FMT                           0x00000200
+#       define R200_VTX_W0_FMT                          0x00000400
+#       define R200_VTX_W0_NORMALIZE                    0x00000800
+#       define R200_VTX_ST_DENORMALIZED         0x00001000
+#define R200_SE_VAP_CNTL_STATUS                 0x2140
+#       define R200_VC_NO_SWAP                  (0 << 0)
+#       define R200_VC_16BIT_SWAP               (1 << 0)
+#       define R200_VC_32BIT_SWAP               (2 << 0)
+#define R200_PP_TXFILTER_0                      0x2c00
+#define R200_PP_TXFILTER_1                      0x2c20
+#define R200_PP_TXFILTER_2                      0x2c40
+#define R200_PP_TXFILTER_3                      0x2c60
+#define R200_PP_TXFILTER_4                      0x2c80
+#define R200_PP_TXFILTER_5                      0x2ca0
+#       define R200_MAG_FILTER_NEAREST          (0  <<  0)
+#       define R200_MAG_FILTER_LINEAR           (1  <<  0)
+#       define R200_MAG_FILTER_MASK             (1  <<  0)
+#       define R200_MIN_FILTER_NEAREST          (0  <<  1)
+#       define R200_MIN_FILTER_LINEAR           (1  <<  1)
+#       define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2  <<  1)
+#       define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3  <<  1)
+#       define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6  <<  1)
+#       define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7  <<  1)
+#       define R200_MIN_FILTER_ANISO_NEAREST    (8  <<  1)
+#       define R200_MIN_FILTER_ANISO_LINEAR     (9  <<  1)
+#       define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 <<  1)
+#       define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 <<  1)
+#       define R200_MIN_FILTER_MASK             (15 <<  1)
+#       define R200_MAX_ANISO_1_TO_1            (0  <<  5)
+#       define R200_MAX_ANISO_2_TO_1            (1  <<  5)
+#       define R200_MAX_ANISO_4_TO_1            (2  <<  5)
+#       define R200_MAX_ANISO_8_TO_1            (3  <<  5)
+#       define R200_MAX_ANISO_16_TO_1           (4  <<  5)
+#       define R200_MAX_ANISO_MASK              (7  <<  5)
+#       define R200_MAX_MIP_LEVEL_MASK          (0x0f << 16)
+#       define R200_MAX_MIP_LEVEL_SHIFT         16
+#       define R200_YUV_TO_RGB                  (1  << 20)
+#       define R200_YUV_TEMPERATURE_COOL        (0  << 21)
+#       define R200_YUV_TEMPERATURE_HOT         (1  << 21)
+#       define R200_YUV_TEMPERATURE_MASK        (1  << 21)
+#       define R200_WRAPEN_S                    (1  << 22)
+#       define R200_CLAMP_S_WRAP                (0  << 23)
+#       define R200_CLAMP_S_MIRROR              (1  << 23)
+#       define R200_CLAMP_S_CLAMP_LAST          (2  << 23)
+#       define R200_CLAMP_S_MIRROR_CLAMP_LAST   (3  << 23)
+#       define R200_CLAMP_S_CLAMP_BORDER        (4  << 23)
+#       define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5  << 23)
+#       define R200_CLAMP_S_CLAMP_GL            (6  << 23)
+#       define R200_CLAMP_S_MIRROR_CLAMP_GL     (7  << 23)
+#       define R200_CLAMP_S_MASK                (7  << 23)
+#       define R200_WRAPEN_T                    (1  << 26)
+#       define R200_CLAMP_T_WRAP                (0  << 27)
+#       define R200_CLAMP_T_MIRROR              (1  << 27)
+#       define R200_CLAMP_T_CLAMP_LAST          (2  << 27)
+#       define R200_CLAMP_T_MIRROR_CLAMP_LAST   (3  << 27)
+#       define R200_CLAMP_T_CLAMP_BORDER        (4  << 27)
+#       define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5  << 27)
+#       define R200_CLAMP_T_CLAMP_GL            (6  << 27)
+#       define R200_CLAMP_T_MIRROR_CLAMP_GL     (7  << 27)
+#       define R200_CLAMP_T_MASK                (7  << 27)
+#       define R200_KILL_LT_ZERO                (1  << 30)
+#       define R200_BORDER_MODE_OGL             (0  << 31)
+#       define R200_BORDER_MODE_D3D             (1  << 31)
+#define R200_PP_TXFORMAT_0                      0x2c04
+#define R200_PP_TXFORMAT_1                      0x2c24
+#define R200_PP_TXFORMAT_2                      0x2c44
+#define R200_PP_TXFORMAT_3                      0x2c64
+#define R200_PP_TXFORMAT_4                      0x2c84
+#define R200_PP_TXFORMAT_5                      0x2ca4
+#       define R200_TXFORMAT_I8                 (0 << 0)
+#       define R200_TXFORMAT_AI88               (1 << 0)
+#       define R200_TXFORMAT_RGB332             (2 << 0)
+#       define R200_TXFORMAT_ARGB1555           (3 << 0)
+#       define R200_TXFORMAT_RGB565             (4 << 0)
+#       define R200_TXFORMAT_ARGB4444           (5 << 0)
+#       define R200_TXFORMAT_ARGB8888           (6 << 0)
+#       define R200_TXFORMAT_RGBA8888           (7 << 0)
+#       define R200_TXFORMAT_Y8                 (8 << 0)
+#       define R200_TXFORMAT_AVYU4444           (9 << 0)
+#       define R200_TXFORMAT_VYUY422            (10 << 0)
+#       define R200_TXFORMAT_YVYU422            (11 << 0)
+#       define R200_TXFORMAT_DXT1               (12 << 0)
+#       define R200_TXFORMAT_DXT23              (14 << 0)
+#       define R200_TXFORMAT_DXT45              (15 << 0)
+#       define R200_TXFORMAT_ABGR8888           (22 << 0)
+#       define R200_TXFORMAT_FORMAT_MASK        (31 <<  0)
+#       define R200_TXFORMAT_FORMAT_SHIFT       0
+#       define R200_TXFORMAT_ALPHA_IN_MAP       (1 << 6)
+#       define R200_TXFORMAT_NON_POWER2         (1 << 7)
+#       define R200_TXFORMAT_WIDTH_MASK         (15 <<  8)
+#       define R200_TXFORMAT_WIDTH_SHIFT        8
+#       define R200_TXFORMAT_HEIGHT_MASK        (15 << 12)
+#       define R200_TXFORMAT_HEIGHT_SHIFT       12
+#       define R200_TXFORMAT_F5_WIDTH_MASK      (15 << 16)      /* cube face 5 */
+#       define R200_TXFORMAT_F5_WIDTH_SHIFT     16
+#       define R200_TXFORMAT_F5_HEIGHT_MASK     (15 << 20)
+#       define R200_TXFORMAT_F5_HEIGHT_SHIFT    20
+#       define R200_TXFORMAT_ST_ROUTE_STQ0      (0 << 24)
+#       define R200_TXFORMAT_ST_ROUTE_STQ1      (1 << 24)
+#       define R200_TXFORMAT_ST_ROUTE_STQ2      (2 << 24)
+#       define R200_TXFORMAT_ST_ROUTE_STQ3      (3 << 24)
+#       define R200_TXFORMAT_ST_ROUTE_STQ4      (4 << 24)
+#       define R200_TXFORMAT_ST_ROUTE_STQ5      (5 << 24)
+#       define R200_TXFORMAT_ST_ROUTE_MASK      (7 << 24)
+#       define R200_TXFORMAT_ST_ROUTE_SHIFT     24
+#       define R200_TXFORMAT_ALPHA_MASK_ENABLE  (1 << 28)
+#       define R200_TXFORMAT_CHROMA_KEY_ENABLE  (1 << 29)
+#       define R200_TXFORMAT_CUBIC_MAP_ENABLE           (1 << 30)
+#define R200_PP_TXFORMAT_X_0                    0x2c08
+#define R200_PP_TXFORMAT_X_1                    0x2c28
+#define R200_PP_TXFORMAT_X_2                    0x2c48
+#define R200_PP_TXFORMAT_X_3                    0x2c68
+#define R200_PP_TXFORMAT_X_4                    0x2c88
+#define R200_PP_TXFORMAT_X_5                    0x2ca8
+
+#define R200_PP_TXSIZE_0                        0x2c0c /* NPOT only */
+#define R200_PP_TXSIZE_1                        0x2c2c /* NPOT only */
+#define R200_PP_TXSIZE_2                        0x2c4c /* NPOT only */
+#define R200_PP_TXSIZE_3                        0x2c6c /* NPOT only */
+#define R200_PP_TXSIZE_4                        0x2c8c /* NPOT only */
+#define R200_PP_TXSIZE_5                        0x2cac /* NPOT only */
+
+#define R200_PP_TXPITCH_0                       0x2c10 /* NPOT only */
+#define R200_PP_TXPITCH_1                       0x2c30 /* NPOT only */
+#define R200_PP_TXPITCH_2                       0x2c50 /* NPOT only */
+#define R200_PP_TXPITCH_3                       0x2c70 /* NPOT only */
+#define R200_PP_TXPITCH_4                       0x2c90 /* NPOT only */
+#define R200_PP_TXPITCH_5                       0x2cb0 /* NPOT only */
+
+#define R200_PP_TXOFFSET_0                      0x2d00
+#       define R200_TXO_ENDIAN_NO_SWAP          (0 << 0)
+#       define R200_TXO_ENDIAN_BYTE_SWAP        (1 << 0)
+#       define R200_TXO_ENDIAN_WORD_SWAP        (2 << 0)
+#       define R200_TXO_ENDIAN_HALFDW_SWAP      (3 << 0)
+#       define R200_TXO_MACRO_LINEAR            (0 << 2)
+#       define R200_TXO_MACRO_TILE              (1 << 2)
+#       define R200_TXO_MICRO_LINEAR            (0 << 3)
+#       define R200_TXO_MICRO_TILE              (1 << 3)
+#       define R200_TXO_OFFSET_MASK             0xffffffe0
+#       define R200_TXO_OFFSET_SHIFT            5
+#define R200_PP_TXOFFSET_1                      0x2d18
+#define R200_PP_TXOFFSET_2                      0x2d30
+#define R200_PP_TXOFFSET_3                      0x2d48
+#define R200_PP_TXOFFSET_4                      0x2d60
+#define R200_PP_TXOFFSET_5                      0x2d78
+
+#define R200_PP_TFACTOR_0                       0x2ee0
+#define R200_PP_TFACTOR_1                       0x2ee4
+#define R200_PP_TFACTOR_2                       0x2ee8
+#define R200_PP_TFACTOR_3                       0x2eec
+#define R200_PP_TFACTOR_4                       0x2ef0
+#define R200_PP_TFACTOR_5                       0x2ef4
+
+#define R200_PP_TXCBLEND_0                      0x2f00
+#       define R200_TXC_ARG_A_ZERO              (0)
+#       define R200_TXC_ARG_A_CURRENT_COLOR     (2)
+#       define R200_TXC_ARG_A_CURRENT_ALPHA     (3)
+#       define R200_TXC_ARG_A_DIFFUSE_COLOR     (4)
+#       define R200_TXC_ARG_A_DIFFUSE_ALPHA     (5)
+#       define R200_TXC_ARG_A_SPECULAR_COLOR    (6)
+#       define R200_TXC_ARG_A_SPECULAR_ALPHA    (7)
+#       define R200_TXC_ARG_A_TFACTOR_COLOR     (8)
+#       define R200_TXC_ARG_A_TFACTOR_ALPHA     (9)
+#       define R200_TXC_ARG_A_R0_COLOR          (10)
+#       define R200_TXC_ARG_A_R0_ALPHA          (11)
+#       define R200_TXC_ARG_A_R1_COLOR          (12)
+#       define R200_TXC_ARG_A_R1_ALPHA          (13)
+#       define R200_TXC_ARG_A_R2_COLOR          (14)
+#       define R200_TXC_ARG_A_R2_ALPHA          (15)
+#       define R200_TXC_ARG_A_R3_COLOR          (16)
+#       define R200_TXC_ARG_A_R3_ALPHA          (17)
+#       define R200_TXC_ARG_A_R4_COLOR          (18)
+#       define R200_TXC_ARG_A_R4_ALPHA          (19)
+#       define R200_TXC_ARG_A_R5_COLOR          (20)
+#       define R200_TXC_ARG_A_R5_ALPHA          (21)
+#       define R200_TXC_ARG_A_TFACTOR1_COLOR    (26)
+#       define R200_TXC_ARG_A_TFACTOR1_ALPHA    (27)
+#       define R200_TXC_ARG_A_MASK              (31 << 0)
+#       define R200_TXC_ARG_A_SHIFT             0
+#       define R200_TXC_ARG_B_ZERO              (0 << 5)
+#       define R200_TXC_ARG_B_CURRENT_COLOR     (2 << 5)
+#       define R200_TXC_ARG_B_CURRENT_ALPHA     (3 << 5)
+#       define R200_TXC_ARG_B_DIFFUSE_COLOR     (4 << 5)
+#       define R200_TXC_ARG_B_DIFFUSE_ALPHA     (5 << 5)
+#       define R200_TXC_ARG_B_SPECULAR_COLOR    (6 << 5)
+#       define R200_TXC_ARG_B_SPECULAR_ALPHA    (7 << 5)
+#       define R200_TXC_ARG_B_TFACTOR_COLOR     (8 << 5)
+#       define R200_TXC_ARG_B_TFACTOR_ALPHA     (9 << 5)
+#       define R200_TXC_ARG_B_R0_COLOR          (10 << 5)
+#       define R200_TXC_ARG_B_R0_ALPHA          (11 << 5)
+#       define R200_TXC_ARG_B_R1_COLOR          (12 << 5)
+#       define R200_TXC_ARG_B_R1_ALPHA          (13 << 5)
+#       define R200_TXC_ARG_B_R2_COLOR          (14 << 5)
+#       define R200_TXC_ARG_B_R2_ALPHA          (15 << 5)
+#       define R200_TXC_ARG_B_R3_COLOR          (16 << 5)
+#       define R200_TXC_ARG_B_R3_ALPHA          (17 << 5)
+#       define R200_TXC_ARG_B_R4_COLOR          (18 << 5)
+#       define R200_TXC_ARG_B_R4_ALPHA          (19 << 5)
+#       define R200_TXC_ARG_B_R5_COLOR          (20 << 5)
+#       define R200_TXC_ARG_B_R5_ALPHA          (21 << 5)
+#       define R200_TXC_ARG_B_TFACTOR1_COLOR    (26 << 5)
+#       define R200_TXC_ARG_B_TFACTOR1_ALPHA    (27 << 5)
+#       define R200_TXC_ARG_B_MASK              (31 << 5)
+#       define R200_TXC_ARG_B_SHIFT             5
+#       define R200_TXC_ARG_C_ZERO              (0 << 10)
+#       define R200_TXC_ARG_C_CURRENT_COLOR     (2 << 10)
+#       define R200_TXC_ARG_C_CURRENT_ALPHA     (3 << 10)
+#       define R200_TXC_ARG_C_DIFFUSE_COLOR     (4 << 10)
+#       define R200_TXC_ARG_C_DIFFUSE_ALPHA     (5 << 10)
+#       define R200_TXC_ARG_C_SPECULAR_COLOR    (6 << 10)
+#       define R200_TXC_ARG_C_SPECULAR_ALPHA    (7 << 10)
+#       define R200_TXC_ARG_C_TFACTOR_COLOR     (8 << 10)
+#       define R200_TXC_ARG_C_TFACTOR_ALPHA     (9 << 10)
+#       define R200_TXC_ARG_C_R0_COLOR          (10 << 10)
+#       define R200_TXC_ARG_C_R0_ALPHA          (11 << 10)
+#       define R200_TXC_ARG_C_R1_COLOR          (12 << 10)
+#       define R200_TXC_ARG_C_R1_ALPHA          (13 << 10)
+#       define R200_TXC_ARG_C_R2_COLOR          (14 << 10)
+#       define R200_TXC_ARG_C_R2_ALPHA          (15 << 10)
+#       define R200_TXC_ARG_C_R3_COLOR          (16 << 10)
+#       define R200_TXC_ARG_C_R3_ALPHA          (17 << 10)
+#       define R200_TXC_ARG_C_R4_COLOR          (18 << 10)
+#       define R200_TXC_ARG_C_R4_ALPHA          (19 << 10)
+#       define R200_TXC_ARG_C_R5_COLOR          (20 << 10)
+#       define R200_TXC_ARG_C_R5_ALPHA          (21 << 10)
+#       define R200_TXC_ARG_C_TFACTOR1_COLOR    (26 << 10)
+#       define R200_TXC_ARG_C_TFACTOR1_ALPHA    (27 << 10)
+#       define R200_TXC_ARG_C_MASK              (31 << 10)
+#       define R200_TXC_ARG_C_SHIFT             10
+#       define R200_TXC_COMP_ARG_A              (1 << 16)
+#       define R200_TXC_COMP_ARG_A_SHIFT        (16)
+#       define R200_TXC_BIAS_ARG_A              (1 << 17)
+#       define R200_TXC_SCALE_ARG_A             (1 << 18)
+#       define R200_TXC_NEG_ARG_A               (1 << 19)
+#       define R200_TXC_COMP_ARG_B              (1 << 20)
+#       define R200_TXC_COMP_ARG_B_SHIFT        (20)
+#       define R200_TXC_BIAS_ARG_B              (1 << 21)
+#       define R200_TXC_SCALE_ARG_B             (1 << 22)
+#       define R200_TXC_NEG_ARG_B               (1 << 23)
+#       define R200_TXC_COMP_ARG_C              (1 << 24)
+#       define R200_TXC_COMP_ARG_C_SHIFT        (24)
+#       define R200_TXC_BIAS_ARG_C              (1 << 25)
+#       define R200_TXC_SCALE_ARG_C             (1 << 26)
+#       define R200_TXC_NEG_ARG_C               (1 << 27)
+#       define R200_TXC_OP_MADD                 (0 << 28)
+#       define R200_TXC_OP_CND0                 (2 << 28)
+#       define R200_TXC_OP_LERP                 (3 << 28)
+#       define R200_TXC_OP_DOT3                 (4 << 28)
+#       define R200_TXC_OP_DOT4                 (5 << 28)
+#       define R200_TXC_OP_CONDITIONAL          (6 << 28)
+#       define R200_TXC_OP_DOT2_ADD             (7 << 28)
+#       define R200_TXC_OP_MASK                 (7 << 28)
+#define R200_PP_TXCBLEND2_0             0x2f04
+#       define R200_TXC_TFACTOR_SEL_SHIFT       0
+#       define R200_TXC_TFACTOR_SEL_MASK        0x7
+#       define R200_TXC_TFACTOR1_SEL_SHIFT      4
+#       define R200_TXC_TFACTOR1_SEL_MASK       (0x7 << 4)
+#       define R200_TXC_SCALE_SHIFT             8
+#       define R200_TXC_SCALE_MASK              (7 << 8)
+#       define R200_TXC_SCALE_1X                (0 << 8)
+#       define R200_TXC_SCALE_2X                (1 << 8)
+#       define R200_TXC_SCALE_4X                (2 << 8)
+#       define R200_TXC_SCALE_8X                (3 << 8)
+#       define R200_TXC_SCALE_INV2              (5 << 8)
+#       define R200_TXC_SCALE_INV4              (6 << 8)
+#       define R200_TXC_SCALE_INV8              (7 << 8)
+#       define R200_TXC_CLAMP_SHIFT             12
+#       define R200_TXC_CLAMP_MASK              (3 << 12)
+#       define R200_TXC_CLAMP_WRAP              (0 << 12)
+#       define R200_TXC_CLAMP_0_1               (1 << 12)
+#       define R200_TXC_CLAMP_8_8               (2 << 12)
+#       define R200_TXC_OUTPUT_REG_MASK         (7 << 16)
+#       define R200_TXC_OUTPUT_REG_NONE         (0 << 16)
+#       define R200_TXC_OUTPUT_REG_R0           (1 << 16)
+#       define R200_TXC_OUTPUT_REG_R1           (2 << 16)
+#       define R200_TXC_OUTPUT_REG_R2           (3 << 16)
+#       define R200_TXC_OUTPUT_REG_R3           (4 << 16)
+#       define R200_TXC_OUTPUT_REG_R4           (5 << 16)
+#       define R200_TXC_OUTPUT_REG_R5           (6 << 16)
+#       define R200_TXC_OUTPUT_MASK_MASK        (7 << 20)
+#       define R200_TXC_OUTPUT_MASK_RGB         (0 << 20)
+#       define R200_TXC_OUTPUT_MASK_RG          (1 << 20)
+#       define R200_TXC_OUTPUT_MASK_RB          (2 << 20)
+#       define R200_TXC_OUTPUT_MASK_R           (3 << 20)
+#       define R200_TXC_OUTPUT_MASK_GB          (4 << 20)
+#       define R200_TXC_OUTPUT_MASK_G           (5 << 20)
+#       define R200_TXC_OUTPUT_MASK_B           (6 << 20)
+#       define R200_TXC_OUTPUT_MASK_NONE        (7 << 20)
+#       define R200_TXC_REPL_NORMAL             0
+#       define R200_TXC_REPL_RED                1
+#       define R200_TXC_REPL_GREEN              2
+#       define R200_TXC_REPL_BLUE               3
+#       define R200_TXC_REPL_ARG_A_SHIFT        26
+#       define R200_TXC_REPL_ARG_A_MASK         (3 << 26)
+#       define R200_TXC_REPL_ARG_B_SHIFT        28
+#       define R200_TXC_REPL_ARG_B_MASK         (3 << 28)
+#       define R200_TXC_REPL_ARG_C_SHIFT        30
+#       define R200_TXC_REPL_ARG_C_MASK         (3 << 30)
+#define R200_PP_TXABLEND_0                      0x2f08
+#       define R200_TXA_ARG_A_ZERO              (0)
+#       define R200_TXA_ARG_A_CURRENT_ALPHA     (2) /* guess */
+#       define R200_TXA_ARG_A_CURRENT_BLUE      (3) /* guess */
+#       define R200_TXA_ARG_A_DIFFUSE_ALPHA     (4)
+#       define R200_TXA_ARG_A_DIFFUSE_BLUE      (5)
+#       define R200_TXA_ARG_A_SPECULAR_ALPHA    (6)
+#       define R200_TXA_ARG_A_SPECULAR_BLUE     (7)
+#       define R200_TXA_ARG_A_TFACTOR_ALPHA     (8)
+#       define R200_TXA_ARG_A_TFACTOR_BLUE      (9)
+#       define R200_TXA_ARG_A_R0_ALPHA          (10)
+#       define R200_TXA_ARG_A_R0_BLUE           (11)
+#       define R200_TXA_ARG_A_R1_ALPHA          (12)
+#       define R200_TXA_ARG_A_R1_BLUE           (13)
+#       define R200_TXA_ARG_A_R2_ALPHA          (14)
+#       define R200_TXA_ARG_A_R2_BLUE           (15)
+#       define R200_TXA_ARG_A_R3_ALPHA          (16)
+#       define R200_TXA_ARG_A_R3_BLUE           (17)
+#       define R200_TXA_ARG_A_R4_ALPHA          (18)
+#       define R200_TXA_ARG_A_R4_BLUE           (19)
+#       define R200_TXA_ARG_A_R5_ALPHA          (20)
+#       define R200_TXA_ARG_A_R5_BLUE           (21)
+#       define R200_TXA_ARG_A_TFACTOR1_ALPHA    (26)
+#       define R200_TXA_ARG_A_TFACTOR1_BLUE     (27)
+#       define R200_TXA_ARG_A_MASK              (31 << 0)
+#       define R200_TXA_ARG_A_SHIFT             0
+#       define R200_TXA_ARG_B_ZERO              (0 << 5)
+#       define R200_TXA_ARG_B_CURRENT_ALPHA     (2 << 5) /* guess */
+#       define R200_TXA_ARG_B_CURRENT_BLUE      (3 << 5) /* guess */
+#       define R200_TXA_ARG_B_DIFFUSE_ALPHA     (4 << 5)
+#       define R200_TXA_ARG_B_DIFFUSE_BLUE      (5 << 5)
+#       define R200_TXA_ARG_B_SPECULAR_ALPHA    (6 << 5)
+#       define R200_TXA_ARG_B_SPECULAR_BLUE     (7 << 5)
+#       define R200_TXA_ARG_B_TFACTOR_ALPHA     (8 << 5)
+#       define R200_TXA_ARG_B_TFACTOR_BLUE      (9 << 5)
+#       define R200_TXA_ARG_B_R0_ALPHA          (10 << 5)
+#       define R200_TXA_ARG_B_R0_BLUE           (11 << 5)
+#       define R200_TXA_ARG_B_R1_ALPHA          (12 << 5)
+#       define R200_TXA_ARG_B_R1_BLUE           (13 << 5)
+#       define R200_TXA_ARG_B_R2_ALPHA          (14 << 5)
+#       define R200_TXA_ARG_B_R2_BLUE           (15 << 5)
+#       define R200_TXA_ARG_B_R3_ALPHA          (16 << 5)
+#       define R200_TXA_ARG_B_R3_BLUE           (17 << 5)
+#       define R200_TXA_ARG_B_R4_ALPHA          (18 << 5)
+#       define R200_TXA_ARG_B_R4_BLUE           (19 << 5)
+#       define R200_TXA_ARG_B_R5_ALPHA          (20 << 5)
+#       define R200_TXA_ARG_B_R5_BLUE           (21 << 5)
+#       define R200_TXA_ARG_B_TFACTOR1_ALPHA    (26 << 5)
+#       define R200_TXA_ARG_B_TFACTOR1_BLUE     (27 << 5)
+#       define R200_TXA_ARG_B_MASK              (31 << 5)
+#       define R200_TXA_ARG_B_SHIFT                     5
+#       define R200_TXA_ARG_C_ZERO              (0 << 10)
+#       define R200_TXA_ARG_C_CURRENT_ALPHA     (2 << 10) /* guess */
+#       define R200_TXA_ARG_C_CURRENT_BLUE      (3 << 10) /* guess */
+#       define R200_TXA_ARG_C_DIFFUSE_ALPHA     (4 << 10)
+#       define R200_TXA_ARG_C_DIFFUSE_BLUE      (5 << 10)
+#       define R200_TXA_ARG_C_SPECULAR_ALPHA    (6 << 10)
+#       define R200_TXA_ARG_C_SPECULAR_BLUE     (7 << 10)
+#       define R200_TXA_ARG_C_TFACTOR_ALPHA     (8 << 10)
+#       define R200_TXA_ARG_C_TFACTOR_BLUE      (9 << 10)
+#       define R200_TXA_ARG_C_R0_ALPHA          (10 << 10)
+#       define R200_TXA_ARG_C_R0_BLUE           (11 << 10)
+#       define R200_TXA_ARG_C_R1_ALPHA          (12 << 10)
+#       define R200_TXA_ARG_C_R1_BLUE           (13 << 10)
+#       define R200_TXA_ARG_C_R2_ALPHA          (14 << 10)
+#       define R200_TXA_ARG_C_R2_BLUE           (15 << 10)
+#       define R200_TXA_ARG_C_R3_ALPHA          (16 << 10)
+#       define R200_TXA_ARG_C_R3_BLUE           (17 << 10)
+#       define R200_TXA_ARG_C_R4_ALPHA          (18 << 10)
+#       define R200_TXA_ARG_C_R4_BLUE           (19 << 10)
+#       define R200_TXA_ARG_C_R5_ALPHA          (20 << 10)
+#       define R200_TXA_ARG_C_R5_BLUE           (21 << 10)
+#       define R200_TXA_ARG_C_TFACTOR1_ALPHA    (26 << 10)
+#       define R200_TXA_ARG_C_TFACTOR1_BLUE     (27 << 10)
+#       define R200_TXA_ARG_C_MASK              (31 << 10)
+#       define R200_TXA_ARG_C_SHIFT             10
+#       define R200_TXA_COMP_ARG_A              (1 << 16)
+#       define R200_TXA_COMP_ARG_A_SHIFT        (16)
+#       define R200_TXA_BIAS_ARG_A              (1 << 17)
+#       define R200_TXA_SCALE_ARG_A             (1 << 18)
+#       define R200_TXA_NEG_ARG_A               (1 << 19)
+#       define R200_TXA_COMP_ARG_B              (1 << 20)
+#       define R200_TXA_COMP_ARG_B_SHIFT        (20)
+#       define R200_TXA_BIAS_ARG_B              (1 << 21)
+#       define R200_TXA_SCALE_ARG_B             (1 << 22)
+#       define R200_TXA_NEG_ARG_B               (1 << 23)
+#       define R200_TXA_COMP_ARG_C              (1 << 24)
+#       define R200_TXA_COMP_ARG_C_SHIFT        (24)
+#       define R200_TXA_BIAS_ARG_C              (1 << 25)
+#       define R200_TXA_SCALE_ARG_C             (1 << 26)
+#       define R200_TXA_NEG_ARG_C               (1 << 27)
+#       define R200_TXA_OP_MADD                 (0 << 28)
+#       define R200_TXA_OP_CND0                 (2 << 28)
+#       define R200_TXA_OP_LERP                 (3 << 28)
+#       define R200_TXA_OP_CONDITIONAL          (6 << 28)
+#       define R200_TXA_OP_MASK                 (7 << 28)
+#define R200_PP_TXABLEND2_0                     0x2f0c
+#       define R200_TXA_TFACTOR_SEL_SHIFT       0
+#       define R200_TXA_TFACTOR_SEL_MASK        0x7
+#       define R200_TXA_TFACTOR1_SEL_SHIFT      4
+#       define R200_TXA_TFACTOR1_SEL_MASK       (0x7 << 4)
+#       define R200_TXA_SCALE_SHIFT             8
+#       define R200_TXA_SCALE_MASK              (7 << 8)
+#       define R200_TXA_SCALE_1X                (0 << 8)
+#       define R200_TXA_SCALE_2X                (1 << 8)
+#       define R200_TXA_SCALE_4X                (2 << 8)
+#       define R200_TXA_SCALE_8X                (3 << 8)
+#       define R200_TXA_SCALE_INV2              (5 << 8)
+#       define R200_TXA_SCALE_INV4              (6 << 8)
+#       define R200_TXA_SCALE_INV8              (7 << 8)
+#       define R200_TXA_CLAMP_SHIFT             12
+#       define R200_TXA_CLAMP_MASK              (3 << 12)
+#       define R200_TXA_CLAMP_WRAP              (0 << 12)
+#       define R200_TXA_CLAMP_0_1               (1 << 12)
+#       define R200_TXA_CLAMP_8_8               (2 << 12)
+#       define R200_TXA_OUTPUT_REG_MASK         (7 << 16)
+#       define R200_TXA_OUTPUT_REG_NONE         (0 << 16)
+#       define R200_TXA_OUTPUT_REG_R0           (1 << 16)
+#       define R200_TXA_OUTPUT_REG_R1           (2 << 16)
+#       define R200_TXA_OUTPUT_REG_R2           (3 << 16)
+#       define R200_TXA_OUTPUT_REG_R3           (4 << 16)
+#       define R200_TXA_OUTPUT_REG_R4           (5 << 16)
+#       define R200_TXA_OUTPUT_REG_R5           (6 << 16)
+#       define R200_TXA_DOT_ALPHA               (1 << 20)
+#       define R200_TXA_REPL_NORMAL             0
+#       define R200_TXA_REPL_RED                1
+#       define R200_TXA_REPL_GREEN              2
+#       define R200_TXA_REPL_ARG_A_SHIFT        26
+#       define R200_TXA_REPL_ARG_A_MASK         (3 << 26)
+#       define R200_TXA_REPL_ARG_B_SHIFT        28
+#       define R200_TXA_REPL_ARG_B_MASK         (3 << 28)
+#       define R200_TXA_REPL_ARG_C_SHIFT        30
+#       define R200_TXA_REPL_ARG_C_MASK         (3 << 30)
+
+#define R200_SE_VTX_FMT_0                       0x2088
+#       define R200_VTX_XY                      0 /* always have xy */
+#       define R200_VTX_Z0                      (1<<0)
+#       define R200_VTX_W0                      (1<<1)
+#       define R200_VTX_WEIGHT_COUNT_SHIFT      (2)
+#       define R200_VTX_PV_MATRIX_SEL           (1<<5)
+#       define R200_VTX_N0                      (1<<6)
+#       define R200_VTX_POINT_SIZE              (1<<7)
+#       define R200_VTX_DISCRETE_FOG            (1<<8)
+#       define R200_VTX_SHININESS_0             (1<<9)
+#       define R200_VTX_SHININESS_1             (1<<10)
+#       define   R200_VTX_COLOR_NOT_PRESENT     0
+#       define   R200_VTX_PK_RGBA               1
+#       define   R200_VTX_FP_RGB                2
+#       define   R200_VTX_FP_RGBA               3
+#       define   R200_VTX_COLOR_MASK            3
+#       define R200_VTX_COLOR_0_SHIFT           11
+#       define R200_VTX_COLOR_1_SHIFT           13
+#       define R200_VTX_COLOR_2_SHIFT           15
+#       define R200_VTX_COLOR_3_SHIFT           17
+#       define R200_VTX_COLOR_4_SHIFT           19
+#       define R200_VTX_COLOR_5_SHIFT           21
+#       define R200_VTX_COLOR_6_SHIFT           23
+#       define R200_VTX_COLOR_7_SHIFT           25
+#       define R200_VTX_XY1                     (1<<28)
+#       define R200_VTX_Z1                      (1<<29)
+#       define R200_VTX_W1                      (1<<30)
+#       define R200_VTX_N1                      (1<<31)
+#define R200_SE_VTX_FMT_1                       0x208c
+#       define R200_VTX_TEX0_COMP_CNT_SHIFT     0
+#       define R200_VTX_TEX1_COMP_CNT_SHIFT     3
+#       define R200_VTX_TEX2_COMP_CNT_SHIFT     6
+#       define R200_VTX_TEX3_COMP_CNT_SHIFT     9
+#       define R200_VTX_TEX4_COMP_CNT_SHIFT     12
+#       define R200_VTX_TEX5_COMP_CNT_SHIFT     15
+
+#define R200_SE_TCL_OUTPUT_VTX_FMT_0            0x2090
+#define R200_SE_TCL_OUTPUT_VTX_FMT_1            0x2094
+#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL         0x2250
+#       define R200_OUTPUT_XYZW                 (1<<0)
+#       define R200_OUTPUT_COLOR_0              (1<<8)
+#       define R200_OUTPUT_COLOR_1              (1<<9)
+#       define R200_OUTPUT_TEX_0                (1<<16)
+#       define R200_OUTPUT_TEX_1                (1<<17)
+#       define R200_OUTPUT_TEX_2                (1<<18)
+#       define R200_OUTPUT_TEX_3                (1<<19)
+#       define R200_OUTPUT_TEX_4                (1<<20)
+#       define R200_OUTPUT_TEX_5                (1<<21)
+#       define R200_OUTPUT_TEX_MASK             (0x3f<<16)
+#       define R200_OUTPUT_DISCRETE_FOG         (1<<24)
+#       define R200_OUTPUT_PT_SIZE              (1<<25)
+#       define R200_FORCE_INORDER_PROC          (1<<31)
+#define R200_PP_CNTL_X                          0x2cc4
+#define R200_PP_TXMULTI_CTL_0                   0x2c1c
+#define R200_SE_VTX_STATE_CNTL                  0x2180
+#       define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
+
+                                /* Registers for CP and Microcode Engine */
+#define RADEON_CP_ME_RAM_ADDR               0x07d4
+#define RADEON_CP_ME_RAM_RADDR              0x07d8
+#define RADEON_CP_ME_RAM_DATAH              0x07dc
+#define RADEON_CP_ME_RAM_DATAL              0x07e0
+
+#define RADEON_CP_RB_BASE                   0x0700
+#define RADEON_CP_RB_CNTL                   0x0704
+#       define RADEON_RB_BUFSZ_SHIFT            0
+#       define RADEON_RB_BUFSZ_MASK             (0x3f << 0)
+#       define RADEON_RB_BLKSZ_SHIFT            8
+#       define RADEON_RB_BLKSZ_MASK             (0x3f << 8)
+#       define RADEON_MAX_FETCH_SHIFT           18
+#       define RADEON_MAX_FETCH_MASK            (0x3 << 18)
+#       define RADEON_RB_NO_UPDATE              (1 << 27)
+#       define RADEON_RB_RPTR_WR_ENA            (1 << 31)
+#define RADEON_CP_RB_RPTR_ADDR              0x070c
+#define RADEON_CP_RB_RPTR                   0x0710
+#define RADEON_CP_RB_WPTR                   0x0714
+#define RADEON_CP_RB_RPTR_WR                0x071c
+
+#define RADEON_CP_IB_BASE                   0x0738
+#define RADEON_CP_IB_BUFSZ                  0x073c
+
+#define RADEON_CP_CSQ_CNTL                  0x0740
+#       define RADEON_CSQ_CNT_PRIMARY_MASK     (0xff << 0)
+#       define RADEON_CSQ_PRIDIS_INDDIS        (0    << 28)
+#       define RADEON_CSQ_PRIPIO_INDDIS        (1    << 28)
+#       define RADEON_CSQ_PRIBM_INDDIS         (2    << 28)
+#       define RADEON_CSQ_PRIPIO_INDBM         (3    << 28)
+#       define RADEON_CSQ_PRIBM_INDBM          (4    << 28)
+#       define RADEON_CSQ_PRIPIO_INDPIO        (15   << 28)
+
+#define R300_CP_RESYNC_ADDR                 0x778
+#define R300_CP_RESYNC_DATA                 0x77c
+
+#define RADEON_CP_CSQ_STAT                  0x07f8
+#       define RADEON_CSQ_RPTR_PRIMARY_MASK    (0xff <<  0)
+#       define RADEON_CSQ_WPTR_PRIMARY_MASK    (0xff <<  8)
+#       define RADEON_CSQ_RPTR_INDIRECT_MASK   (0xff << 16)
+#       define RADEON_CSQ_WPTR_INDIRECT_MASK   (0xff << 24)
+#define RADEON_CP_CSQ2_STAT                  0x07fc
+#define RADEON_CP_CSQ_ADDR                  0x07f0
+#define RADEON_CP_CSQ_DATA                  0x07f4
+#define RADEON_CP_CSQ_APER_PRIMARY          0x1000
+#define RADEON_CP_CSQ_APER_INDIRECT         0x1300
+
+#define RADEON_CP_RB_WPTR_DELAY             0x0718
+#       define RADEON_PRE_WRITE_TIMER_SHIFT    0
+#       define RADEON_PRE_WRITE_LIMIT_SHIFT    23
+#define RADEON_CP_CSQ_MODE              0x0744
+#       define RADEON_INDIRECT2_START_SHIFT     0
+#       define RADEON_INDIRECT2_START_MASK      (0x7f << 0)
+#       define RADEON_INDIRECT1_START_SHIFT     8
+#       define RADEON_INDIRECT1_START_MASK      (0x7f << 8)
+
+#define RADEON_AIC_CNTL                     0x01d0
+#       define RADEON_PCIGART_TRANSLATE_EN     (1 << 0)
+#       define RADEON_DIS_OUT_OF_PCI_GART_ACCESS     (1 << 1)
+#define RADEON_AIC_LO_ADDR                  0x01dc
+#define RADEON_AIC_PT_BASE              0x01d8
+#define RADEON_AIC_HI_ADDR              0x01e0
+
+
+
+                                /* Constants */
+/* #define RADEON_LAST_FRAME_REG               RADEON_GUI_SCRATCH_REG0 */
+/* efine RADEON_LAST_CLEAR_REG               RADEON_GUI_SCRATCH_REG2 */
+
+
+
+                                /* CP packet types */
+#define RADEON_CP_PACKET0                           0x00000000
+#define RADEON_CP_PACKET1                           0x40000000
+#define RADEON_CP_PACKET2                           0x80000000
+#define RADEON_CP_PACKET3                           0xC0000000
+#       define RADEON_CP_PACKET_MASK                0xC0000000
+#       define RADEON_CP_PACKET_COUNT_MASK          0x3fff0000
+#       define RADEON_CP_PACKET_MAX_DWORDS          (1 << 12)
+#       define RADEON_CP_PACKET0_REG_MASK           0x000007ff
+#       define R300_CP_PACKET0_REG_MASK             0x00001fff
+#       define RADEON_CP_PACKET1_REG0_MASK          0x000007ff
+#       define RADEON_CP_PACKET1_REG1_MASK          0x003ff800
+
+#define RADEON_CP_PACKET0_ONE_REG_WR                0x00008000
+
+#define RADEON_CP_PACKET3_NOP                       0xC0001000
+#define RADEON_CP_PACKET3_NEXT_CHAR                 0xC0001900
+#define RADEON_CP_PACKET3_PLY_NEXTSCAN              0xC0001D00
+#define RADEON_CP_PACKET3_SET_SCISSORS              0xC0001E00
+#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM     0xC0002300
+#define RADEON_CP_PACKET3_LOAD_MICROCODE            0xC0002400
+#define RADEON_CP_PACKET3_WAIT_FOR_IDLE             0xC0002600
+#define RADEON_CP_PACKET3_3D_DRAW_VBUF              0xC0002800
+#define RADEON_CP_PACKET3_3D_DRAW_IMMD              0xC0002900
+#define RADEON_CP_PACKET3_3D_DRAW_INDX              0xC0002A00
+#define RADEON_CP_PACKET3_LOAD_PALETTE              0xC0002C00
+#define R200_CP_PACKET3_3D_DRAW_IMMD_2              0xc0003500
+#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR            0xC0002F00
+#define RADEON_CP_PACKET3_CNTL_PAINT                0xC0009100
+#define RADEON_CP_PACKET3_CNTL_BITBLT               0xC0009200
+#define RADEON_CP_PACKET3_CNTL_SMALLTEXT            0xC0009300
+#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT         0xC0009400
+#define RADEON_CP_PACKET3_CNTL_POLYLINE             0xC0009500
+#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES        0xC0009800
+#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI          0xC0009A00
+#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI         0xC0009B00
+#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT         0xC0009C00
+
+
+#define RADEON_CP_VC_FRMT_XY                        0x00000000
+#define RADEON_CP_VC_FRMT_W0                        0x00000001
+#define RADEON_CP_VC_FRMT_FPCOLOR                   0x00000002
+#define RADEON_CP_VC_FRMT_FPALPHA                   0x00000004
+#define RADEON_CP_VC_FRMT_PKCOLOR                   0x00000008
+#define RADEON_CP_VC_FRMT_FPSPEC                    0x00000010
+#define RADEON_CP_VC_FRMT_FPFOG                     0x00000020
+#define RADEON_CP_VC_FRMT_PKSPEC                    0x00000040
+#define RADEON_CP_VC_FRMT_ST0                       0x00000080
+#define RADEON_CP_VC_FRMT_ST1                       0x00000100
+#define RADEON_CP_VC_FRMT_Q1                        0x00000200
+#define RADEON_CP_VC_FRMT_ST2                       0x00000400
+#define RADEON_CP_VC_FRMT_Q2                        0x00000800
+#define RADEON_CP_VC_FRMT_ST3                       0x00001000
+#define RADEON_CP_VC_FRMT_Q3                        0x00002000
+#define RADEON_CP_VC_FRMT_Q0                        0x00004000
+#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK      0x00038000
+#define RADEON_CP_VC_FRMT_N0                        0x00040000
+#define RADEON_CP_VC_FRMT_XY1                       0x08000000
+#define RADEON_CP_VC_FRMT_Z1                        0x10000000
+#define RADEON_CP_VC_FRMT_W1                        0x20000000
+#define RADEON_CP_VC_FRMT_N1                        0x40000000
+#define RADEON_CP_VC_FRMT_Z                         0x80000000
+
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE            0x00000000
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT           0x00000001
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE            0x00000002
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP      0x00000003
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST        0x00000004
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN         0x00000005
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP       0x00000006
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2      0x00000007
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST       0x00000008
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
+#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST  0x0000000a
+#define RADEON_CP_VC_CNTL_PRIM_WALK_IND             0x00000010
+#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST            0x00000020
+#define RADEON_CP_VC_CNTL_PRIM_WALK_RING            0x00000030
+#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA          0x00000000
+#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA          0x00000040
+#define RADEON_CP_VC_CNTL_MAOS_ENABLE               0x00000080
+#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE   0x00000000
+#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE       0x00000100
+#define RADEON_CP_VC_CNTL_TCL_DISABLE               0x00000000
+#define RADEON_CP_VC_CNTL_TCL_ENABLE                0x00000200
+#define RADEON_CP_VC_CNTL_NUM_SHIFT                 16
+
+#define RADEON_VS_MATRIX_0_ADDR                   0
+#define RADEON_VS_MATRIX_1_ADDR                   4
+#define RADEON_VS_MATRIX_2_ADDR                   8
+#define RADEON_VS_MATRIX_3_ADDR                  12
+#define RADEON_VS_MATRIX_4_ADDR                  16
+#define RADEON_VS_MATRIX_5_ADDR                  20
+#define RADEON_VS_MATRIX_6_ADDR                  24
+#define RADEON_VS_MATRIX_7_ADDR                  28
+#define RADEON_VS_MATRIX_8_ADDR                  32
+#define RADEON_VS_MATRIX_9_ADDR                  36
+#define RADEON_VS_MATRIX_10_ADDR                 40
+#define RADEON_VS_MATRIX_11_ADDR                 44
+#define RADEON_VS_MATRIX_12_ADDR                 48
+#define RADEON_VS_MATRIX_13_ADDR                 52
+#define RADEON_VS_MATRIX_14_ADDR                 56
+#define RADEON_VS_MATRIX_15_ADDR                 60
+#define RADEON_VS_LIGHT_AMBIENT_ADDR             64
+#define RADEON_VS_LIGHT_DIFFUSE_ADDR             72
+#define RADEON_VS_LIGHT_SPECULAR_ADDR            80
+#define RADEON_VS_LIGHT_DIRPOS_ADDR              88
+#define RADEON_VS_LIGHT_HWVSPOT_ADDR             96
+#define RADEON_VS_LIGHT_ATTENUATION_ADDR        104
+#define RADEON_VS_MATRIX_EYE2CLIP_ADDR          112
+#define RADEON_VS_UCP_ADDR                      116
+#define RADEON_VS_GLOBAL_AMBIENT_ADDR           122
+#define RADEON_VS_FOG_PARAM_ADDR                123
+#define RADEON_VS_EYE_VECTOR_ADDR               124
+
+#define RADEON_SS_LIGHT_DCD_ADDR                  0
+#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR        8
+#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR         16
+#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR     24
+#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR        32
+#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR       48
+#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR    49
+#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR       50
+#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR    51
+#define RADEON_SS_SHININESS                      60
+
+#define RADEON_TV_MASTER_CNTL                    0x0800
+#       define RADEON_TV_ASYNC_RST               (1 <<  0)
+#       define RADEON_CRT_ASYNC_RST              (1 <<  1)
+#       define RADEON_RESTART_PHASE_FIX          (1 <<  3)
+#       define RADEON_TV_FIFO_ASYNC_RST          (1 <<  4)
+#       define RADEON_VIN_ASYNC_RST              (1 <<  5)
+#       define RADEON_AUD_ASYNC_RST              (1 <<  6)
+#       define RADEON_DVS_ASYNC_RST              (1 <<  7)
+#       define RADEON_CRT_FIFO_CE_EN             (1 <<  9)
+#       define RADEON_TV_FIFO_CE_EN              (1 << 10)
+#       define RADEON_RE_SYNC_NOW_SEL_MASK       (3 << 14)
+#       define RADEON_TVCLK_ALWAYS_ONb           (1 << 30)
+#       define RADEON_TV_ON                      (1 << 31)
+#define RADEON_TV_PRE_DAC_MUX_CNTL               0x0888
+#       define RADEON_Y_RED_EN                   (1 << 0)
+#       define RADEON_C_GRN_EN                   (1 << 1)
+#       define RADEON_CMP_BLU_EN                 (1 << 2)
+#       define RADEON_DAC_DITHER_EN              (1 << 3)
+#       define RADEON_RED_MX_FORCE_DAC_DATA      (6 << 4)
+#       define RADEON_GRN_MX_FORCE_DAC_DATA      (6 << 8)
+#       define RADEON_BLU_MX_FORCE_DAC_DATA      (6 << 12)
+#       define RADEON_TV_FORCE_DAC_DATA_SHIFT    16
+#define RADEON_TV_RGB_CNTL                           0x0804
+#       define RADEON_SWITCH_TO_BLUE              (1 <<  4)
+#       define RADEON_RGB_DITHER_EN               (1 <<  5)
+#       define RADEON_RGB_SRC_SEL_MASK            (3 <<  8)
+#       define RADEON_RGB_SRC_SEL_CRTC1           (0 <<  8)
+#       define RADEON_RGB_SRC_SEL_RMX             (1 <<  8)
+#       define RADEON_RGB_SRC_SEL_CRTC2           (2 <<  8)
+#       define RADEON_RGB_CONVERT_BY_PASS         (1 << 10)
+#       define RADEON_UVRAM_READ_MARGIN_SHIFT     16
+#       define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT   20
+#       define RADEON_TVOUT_SCALE_EN              (1 << 26)
+#define RADEON_TV_SYNC_CNTL                          0x0808
+#       define RADEON_SYNC_OE                     (1 <<  0)
+#       define RADEON_SYNC_OUT                    (1 <<  1)
+#       define RADEON_SYNC_IN                     (1 <<  2)
+#       define RADEON_SYNC_PUB                    (1 <<  3)
+#       define RADEON_SYNC_PD                     (1 <<  4)
+#       define RADEON_TV_SYNC_IO_DRIVE            (1 <<  5)
+#define RADEON_TV_HTOTAL                             0x080c
+#define RADEON_TV_HDISP                              0x0810
+#define RADEON_TV_HSTART                             0x0818
+#define RADEON_TV_HCOUNT                             0x081C
+#define RADEON_TV_VTOTAL                             0x0820
+#define RADEON_TV_VDISP                              0x0824
+#define RADEON_TV_VCOUNT                             0x0828
+#define RADEON_TV_FTOTAL                             0x082c
+#define RADEON_TV_FCOUNT                             0x0830
+#define RADEON_TV_FRESTART                           0x0834
+#define RADEON_TV_HRESTART                           0x0838
+#define RADEON_TV_VRESTART                           0x083c
+#define RADEON_TV_HOST_READ_DATA                     0x0840
+#define RADEON_TV_HOST_WRITE_DATA                    0x0844
+#define RADEON_TV_HOST_RD_WT_CNTL                    0x0848
+#       define RADEON_HOST_FIFO_RD               (1 << 12)
+#       define RADEON_HOST_FIFO_RD_ACK           (1 << 13)
+#       define RADEON_HOST_FIFO_WT               (1 << 14)
+#       define RADEON_HOST_FIFO_WT_ACK           (1 << 15)
+#define RADEON_TV_VSCALER_CNTL1                      0x084c
+#       define RADEON_UV_INC_MASK                0xffff
+#       define RADEON_UV_INC_SHIFT               0
+#       define RADEON_Y_W_EN                     (1 << 24)
+#       define RADEON_RESTART_FIELD              (1 << 29) /* restart on field 0 */
+#       define RADEON_Y_DEL_W_SIG_SHIFT          26
+#define RADEON_TV_TIMING_CNTL                        0x0850
+#       define RADEON_H_INC_MASK                 0xfff
+#       define RADEON_H_INC_SHIFT                0
+#       define RADEON_REQ_Y_FIRST                (1 << 19)
+#       define RADEON_FORCE_BURST_ALWAYS         (1 << 21)
+#       define RADEON_UV_POST_SCALE_BYPASS       (1 << 23)
+#       define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24
+#define RADEON_TV_VSCALER_CNTL2                      0x0854
+#       define RADEON_DITHER_MODE                (1 <<  0)
+#       define RADEON_Y_OUTPUT_DITHER_EN         (1 <<  1)
+#       define RADEON_UV_OUTPUT_DITHER_EN        (1 <<  2)
+#       define RADEON_UV_TO_BUF_DITHER_EN        (1 <<  3)
+#define RADEON_TV_Y_FALL_CNTL                        0x0858
+#       define RADEON_Y_FALL_PING_PONG           (1 << 16)
+#       define RADEON_Y_COEF_EN                  (1 << 17)
+#define RADEON_TV_Y_RISE_CNTL                        0x085c
+#       define RADEON_Y_RISE_PING_PONG           (1 << 16)
+#define RADEON_TV_Y_SAW_TOOTH_CNTL                   0x0860
+#define RADEON_TV_UPSAMP_AND_GAIN_CNTL               0x0864
+#       define RADEON_YUPSAMP_EN                 (1 <<  0)
+#       define RADEON_UVUPSAMP_EN                (1 <<  2)
+#define RADEON_TV_GAIN_LIMIT_SETTINGS                0x0868
+#       define RADEON_Y_GAIN_LIMIT_SHIFT         0
+#       define RADEON_UV_GAIN_LIMIT_SHIFT        16
+#define RADEON_TV_LINEAR_GAIN_SETTINGS               0x086c
+#       define RADEON_Y_GAIN_SHIFT               0
+#       define RADEON_UV_GAIN_SHIFT              16
+#define RADEON_TV_MODULATOR_CNTL1                    0x0870
+#       define RADEON_YFLT_EN                    (1 <<  2)
+#       define RADEON_UVFLT_EN                   (1 <<  3)
+#       define RADEON_ALT_PHASE_EN               (1 <<  6)
+#       define RADEON_SYNC_TIP_LEVEL             (1 <<  7)
+#       define RADEON_BLANK_LEVEL_SHIFT          8
+#       define RADEON_SET_UP_LEVEL_SHIFT         16
+#       define RADEON_SLEW_RATE_LIMIT            (1 << 23)
+#       define RADEON_CY_FILT_BLEND_SHIFT        28
+#define RADEON_TV_MODULATOR_CNTL2                    0x0874
+#       define RADEON_TV_U_BURST_LEVEL_MASK     0x1ff
+#       define RADEON_TV_V_BURST_LEVEL_MASK     0x1ff
+#       define RADEON_TV_V_BURST_LEVEL_SHIFT    16
+#define RADEON_TV_CRC_CNTL                           0x0890
+#define RADEON_TV_UV_ADR                             0x08ac
+#       define RADEON_MAX_UV_ADR_MASK            0x000000ff
+#       define RADEON_MAX_UV_ADR_SHIFT           0
+#       define RADEON_TABLE1_BOT_ADR_MASK        0x0000ff00
+#       define RADEON_TABLE1_BOT_ADR_SHIFT       8
+#       define RADEON_TABLE3_TOP_ADR_MASK        0x00ff0000
+#       define RADEON_TABLE3_TOP_ADR_SHIFT       16
+#       define RADEON_HCODE_TABLE_SEL_MASK       0x06000000
+#       define RADEON_HCODE_TABLE_SEL_SHIFT      25
+#       define RADEON_VCODE_TABLE_SEL_MASK       0x18000000
+#       define RADEON_VCODE_TABLE_SEL_SHIFT      27
+#       define RADEON_TV_MAX_FIFO_ADDR           0x1a7
+#       define RADEON_TV_MAX_FIFO_ADDR_INTERNAL  0x1ff
+#define RADEON_TV_PLL_FINE_CNTL                      0x0020     /* PLL */
+#define RADEON_TV_PLL_CNTL                           0x0021     /* PLL */
+#       define RADEON_TV_M0LO_MASK               0xff
+#       define RADEON_TV_M0HI_MASK               0x7
+#       define RADEON_TV_M0HI_SHIFT              18
+#       define RADEON_TV_N0LO_MASK               0x1ff
+#       define RADEON_TV_N0LO_SHIFT              8
+#       define RADEON_TV_N0HI_MASK               0x3
+#       define RADEON_TV_N0HI_SHIFT              21
+#       define RADEON_TV_P_MASK                  0xf
+#       define RADEON_TV_P_SHIFT                 24
+#       define RADEON_TV_SLIP_EN                 (1 << 23)
+#       define RADEON_TV_DTO_EN                  (1 << 28)
+#define RADEON_TV_PLL_CNTL1                          0x0022     /* PLL */
+#       define RADEON_TVPLL_RESET                (1 <<  1)
+#       define RADEON_TVPLL_SLEEP                (1 <<  3)
+#       define RADEON_TVPLL_REFCLK_SEL           (1 <<  4)
+#       define RADEON_TVPCP_SHIFT                8
+#       define RADEON_TVPCP_MASK                 (7 << 8)
+#       define RADEON_TVPVG_SHIFT                11
+#       define RADEON_TVPVG_MASK                 (7 << 11)
+#       define RADEON_TVPDC_SHIFT                14
+#       define RADEON_TVPDC_MASK                 (3 << 14)
+#       define RADEON_TVPLL_TEST_DIS             (1 << 31)
+#       define RADEON_TVCLK_SRC_SEL_TVPLL        (1 << 30)
+
+#define RS400_DISP2_REQ_CNTL1                   0xe30
+#       define RS400_DISP2_START_REQ_LEVEL_SHIFT   0
+#       define RS400_DISP2_START_REQ_LEVEL_MASK    0x3ff
+#       define RS400_DISP2_STOP_REQ_LEVEL_SHIFT    12
+#       define RS400_DISP2_STOP_REQ_LEVEL_MASK     0x3ff
+#       define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT   22
+#       define RS400_DISP2_ALLOW_FID_LEVEL_MASK    0x3ff
+#define RS400_DISP2_REQ_CNTL2                   0xe34
+#       define RS400_DISP2_CRITICAL_POINT_START_SHIFT    12
+#       define RS400_DISP2_CRITICAL_POINT_START_MASK     0x3ff
+#       define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT     22
+#       define RS400_DISP2_CRITICAL_POINT_STOP_MASK      0x3ff
+#define RS400_DMIF_MEM_CNTL1                    0xe38
+#       define RS400_DISP2_START_ADR_SHIFT      0
+#       define RS400_DISP2_START_ADR_MASK       0x3ff
+#       define RS400_DISP1_CRITICAL_POINT_START_SHIFT    12
+#       define RS400_DISP1_CRITICAL_POINT_START_MASK     0x3ff
+#       define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT     22
+#       define RS400_DISP1_CRITICAL_POINT_STOP_MASK      0x3ff
+#define RS400_DISP1_REQ_CNTL1                   0xe3c
+#       define RS400_DISP1_START_REQ_LEVEL_SHIFT   0
+#       define RS400_DISP1_START_REQ_LEVEL_MASK    0x3ff
+#       define RS400_DISP1_STOP_REQ_LEVEL_SHIFT    12
+#       define RS400_DISP1_STOP_REQ_LEVEL_MASK     0x3ff
+#       define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT   22
+#       define RS400_DISP1_ALLOW_FID_LEVEL_MASK    0x3ff
+
+#define RADEON_PCIE_INDEX               0x0030
+#define RADEON_PCIE_DATA                0x0034
+#define RADEON_PCIE_TX_GART_CNTL        0x10
+#       define RADEON_PCIE_TX_GART_EN           (1 << 0)
+#       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
+#       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO  (1 << 1)
+#       define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD   (3 << 1)
+#       define RADEON_PCIE_TX_GART_MODE_32_128_CACHE    (0 << 3)
+#       define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE   (1 << 3)
+#       define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN      (1 << 5)
+#       define RADEON_PCIE_TX_GART_INVALIDATE_TLB       (1 << 8)
+#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
+#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
+#define RADEON_PCIE_TX_GART_BASE        0x13
+#define RADEON_PCIE_TX_GART_START_LO    0x14
+#define RADEON_PCIE_TX_GART_START_HI    0x15
+#define RADEON_PCIE_TX_GART_END_LO      0x16
+#define RADEON_PCIE_TX_GART_END_HI      0x17
+#define RADEON_PCIE_TX_GART_ERROR       0x18
+
+#define RADEON_SCRATCH_REG0             0x15e0
+#define RADEON_SCRATCH_REG1             0x15e4
+#define RADEON_SCRATCH_REG2             0x15e8
+#define RADEON_SCRATCH_REG3             0x15ec
+#define RADEON_SCRATCH_REG4             0x15f0
+#define RADEON_SCRATCH_REG5             0x15f4
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
new file mode 100644
index 000000000000..a853261d1881
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -0,0 +1,485 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include <linux/seq_file.h>
+#include "drmP.h"
+#include "radeon_drm.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+#include "atom.h"
+
+int radeon_debugfs_ib_init(struct radeon_device *rdev);
+
+/*
+ * IB.
+ */
+int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
+{
+        struct radeon_fence *fence;
+        struct radeon_ib *nib;
+        unsigned long i;
+        int r = 0;
+
+        *ib = NULL;
+        r = radeon_fence_create(rdev, &fence);
+        if (r) {
+                DRM_ERROR("failed to create fence for new IB\n");
+                return r;
+        }
+        mutex_lock(&rdev->ib_pool.mutex);
+        i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
+        if (i < RADEON_IB_POOL_SIZE) {
+                set_bit(i, rdev->ib_pool.alloc_bm);
+                rdev->ib_pool.ibs[i].length_dw = 0;
+                *ib = &rdev->ib_pool.ibs[i];
+                goto out;
+        }
+        if (list_empty(&rdev->ib_pool.scheduled_ibs)) {
+                /* we go do nothings here */
+                DRM_ERROR("all IB allocated none scheduled.\n");
+                r = -EINVAL;
+                goto out;
+        }
+        /* get the first ib on the scheduled list */
+        nib = list_entry(rdev->ib_pool.scheduled_ibs.next,
+                         struct radeon_ib, list);
+        if (nib->fence == NULL) {
+                /* we go do nothings here */
+                DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx);
+                r = -EINVAL;
+                goto out;
+        }
+        r = radeon_fence_wait(nib->fence, false);
+        if (r) {
+                DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx,
+                          (unsigned long)nib->gpu_addr, nib->length_dw);
+                DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n");
+                goto out;
+        }
+        radeon_fence_unref(&nib->fence);
+        nib->length_dw = 0;
+        list_del(&nib->list);
+        INIT_LIST_HEAD(&nib->list);
+        *ib = nib;
+out:
+        mutex_unlock(&rdev->ib_pool.mutex);
+        if (r) {
+                radeon_fence_unref(&fence);
+        } else {
+                (*ib)->fence = fence;
+        }
+        return r;
+}
+
+void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
+{
+        struct radeon_ib *tmp = *ib;
+
+        *ib = NULL;
+        if (tmp == NULL) {
+                return;
+        }
+        mutex_lock(&rdev->ib_pool.mutex);
+        if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) {
+                /* IB is scheduled & not signaled don't do anythings */
+                mutex_unlock(&rdev->ib_pool.mutex);
+                return;
+        }
+        list_del(&tmp->list);
+        INIT_LIST_HEAD(&tmp->list);
+        if (tmp->fence) {
+                radeon_fence_unref(&tmp->fence);
+        }
+        tmp->length_dw = 0;
+        clear_bit(tmp->idx, rdev->ib_pool.alloc_bm);
+        mutex_unlock(&rdev->ib_pool.mutex);
+}
+
+static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib)
+{
+        while ((ib->length_dw & rdev->cp.align_mask)) {
+                ib->ptr[ib->length_dw++] = PACKET2(0);
+        }
+}
+
+static void radeon_ib_cpu_flush(struct radeon_device *rdev,
+                                struct radeon_ib *ib)
+{
+        unsigned long tmp;
+        unsigned i;
+
+        /* To force CPU cache flush ugly but seems reliable */
+        for (i = 0; i < ib->length_dw; i += (rdev->cp.align_mask + 1)) {
+                tmp = readl(&ib->ptr[i]);
+        }
+}
+
+int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
+{
+        int r = 0;
+
+        mutex_lock(&rdev->ib_pool.mutex);
+        radeon_ib_align(rdev, ib);
+        radeon_ib_cpu_flush(rdev, ib);
+        if (!ib->length_dw || !rdev->cp.ready) {
+                /* TODO: Nothings in the ib we should report. */
+                mutex_unlock(&rdev->ib_pool.mutex);
+                DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx);
+                return -EINVAL;
+        }
+        /* 64 dwords should be enought for fence too */
+        r = radeon_ring_lock(rdev, 64);
+        if (r) {
+                DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
+                mutex_unlock(&rdev->ib_pool.mutex);
+                return r;
+        }
+        radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
+        radeon_ring_write(rdev, ib->gpu_addr);
+        radeon_ring_write(rdev, ib->length_dw);
+        radeon_fence_emit(rdev, ib->fence);
+        radeon_ring_unlock_commit(rdev);
+        list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs);
+        mutex_unlock(&rdev->ib_pool.mutex);
+        return 0;
+}
+
+int radeon_ib_pool_init(struct radeon_device *rdev)
+{
+        void *ptr;
+        uint64_t gpu_addr;
+        int i;
+        int r = 0;
+
+        /* Allocate 1M object buffer */
+        INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs);
+        r = radeon_object_create(rdev, NULL,  RADEON_IB_POOL_SIZE*64*1024,
+                                 true, RADEON_GEM_DOMAIN_GTT,
+                                 false, &rdev->ib_pool.robj);
+        if (r) {
+                DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
+                return r;
+        }
+        r = radeon_object_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
+        if (r) {
+                DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
+                return r;
+        }
+        r = radeon_object_kmap(rdev->ib_pool.robj, &ptr);
+        if (r) {
+                DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
+                return r;
+        }
+        for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
+                unsigned offset;
+
+                offset = i * 64 * 1024;
+                rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
+                rdev->ib_pool.ibs[i].ptr = ptr + offset;
+                rdev->ib_pool.ibs[i].idx = i;
+                rdev->ib_pool.ibs[i].length_dw = 0;
+                INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list);
+        }
+        bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
+        rdev->ib_pool.ready = true;
+        DRM_INFO("radeon: ib pool ready.\n");
+        if (radeon_debugfs_ib_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for IB !\n");
+        }
+        return r;
+}
+
+void radeon_ib_pool_fini(struct radeon_device *rdev)
+{
+        if (!rdev->ib_pool.ready) {
+                return;
+        }
+        mutex_lock(&rdev->ib_pool.mutex);
+        bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE);
+        if (rdev->ib_pool.robj) {
+                radeon_object_kunmap(rdev->ib_pool.robj);
+                radeon_object_unref(&rdev->ib_pool.robj);
+                rdev->ib_pool.robj = NULL;
+        }
+        mutex_unlock(&rdev->ib_pool.mutex);
+}
+
+int radeon_ib_test(struct radeon_device *rdev)
+{
+        struct radeon_ib *ib;
+        uint32_t scratch;
+        uint32_t tmp = 0;
+        unsigned i;
+        int r;
+
+        r = radeon_scratch_get(rdev, &scratch);
+        if (r) {
+                DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
+                return r;
+        }
+        WREG32(scratch, 0xCAFEDEAD);
+        r = radeon_ib_get(rdev, &ib);
+        if (r) {
+                return r;
+        }
+        ib->ptr[0] = PACKET0(scratch, 0);
+        ib->ptr[1] = 0xDEADBEEF;
+        ib->ptr[2] = PACKET2(0);
+        ib->ptr[3] = PACKET2(0);
+        ib->ptr[4] = PACKET2(0);
+        ib->ptr[5] = PACKET2(0);
+        ib->ptr[6] = PACKET2(0);
+        ib->ptr[7] = PACKET2(0);
+        ib->length_dw = 8;
+        r = radeon_ib_schedule(rdev, ib);
+        if (r) {
+                radeon_scratch_free(rdev, scratch);
+                radeon_ib_free(rdev, &ib);
+                return r;
+        }
+        r = radeon_fence_wait(ib->fence, false);
+        if (r) {
+                return r;
+        }
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                tmp = RREG32(scratch);
+                if (tmp == 0xDEADBEEF) {
+                        break;
+                }
+                DRM_UDELAY(1);
+        }
+        if (i < rdev->usec_timeout) {
+                DRM_INFO("ib test succeeded in %u usecs\n", i);
+        } else {
+                DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
+                          scratch, tmp);
+                r = -EINVAL;
+        }
+        radeon_scratch_free(rdev, scratch);
+        radeon_ib_free(rdev, &ib);
+        return r;
+}
+
+
+/*
+ * Ring.
+ */
+void radeon_ring_free_size(struct radeon_device *rdev)
+{
+        rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
+        /* This works because ring_size is a power of 2 */
+        rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
+        rdev->cp.ring_free_dw -= rdev->cp.wptr;
+        rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
+        if (!rdev->cp.ring_free_dw) {
+                rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
+        }
+}
+
+int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
+{
+        int r;
+
+        /* Align requested size with padding so unlock_commit can
+         * pad safely */
+        ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
+        mutex_lock(&rdev->cp.mutex);
+        while (ndw > (rdev->cp.ring_free_dw - 1)) {
+                radeon_ring_free_size(rdev);
+                if (ndw < rdev->cp.ring_free_dw) {
+                        break;
+                }
+                r = radeon_fence_wait_next(rdev);
+                if (r) {
+                        mutex_unlock(&rdev->cp.mutex);
+                        return r;
+                }
+        }
+        rdev->cp.count_dw = ndw;
+        rdev->cp.wptr_old = rdev->cp.wptr;
+        return 0;
+}
+
+void radeon_ring_unlock_commit(struct radeon_device *rdev)
+{
+        unsigned count_dw_pad;
+        unsigned i;
+
+        /* We pad to match fetch size */
+        count_dw_pad = (rdev->cp.align_mask + 1) -
+                       (rdev->cp.wptr & rdev->cp.align_mask);
+        for (i = 0; i < count_dw_pad; i++) {
+                radeon_ring_write(rdev, PACKET2(0));
+        }
+        DRM_MEMORYBARRIER();
+        WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
+        (void)RREG32(RADEON_CP_RB_WPTR);
+        mutex_unlock(&rdev->cp.mutex);
+}
+
+void radeon_ring_unlock_undo(struct radeon_device *rdev)
+{
+        rdev->cp.wptr = rdev->cp.wptr_old;
+        mutex_unlock(&rdev->cp.mutex);
+}
+
+int radeon_ring_test(struct radeon_device *rdev)
+{
+        uint32_t scratch;
+        uint32_t tmp = 0;
+        unsigned i;
+        int r;
+
+        r = radeon_scratch_get(rdev, &scratch);
+        if (r) {
+                DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
+                return r;
+        }
+        WREG32(scratch, 0xCAFEDEAD);
+        r = radeon_ring_lock(rdev, 2);
+        if (r) {
+                DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+                radeon_scratch_free(rdev, scratch);
+                return r;
+        }
+        radeon_ring_write(rdev, PACKET0(scratch, 0));
+        radeon_ring_write(rdev, 0xDEADBEEF);
+        radeon_ring_unlock_commit(rdev);
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                tmp = RREG32(scratch);
+                if (tmp == 0xDEADBEEF) {
+                        break;
+                }
+                DRM_UDELAY(1);
+        }
+        if (i < rdev->usec_timeout) {
+                DRM_INFO("ring test succeeded in %d usecs\n", i);
+        } else {
+                DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
+                          scratch, tmp);
+                r = -EINVAL;
+        }
+        radeon_scratch_free(rdev, scratch);
+        return r;
+}
+
+int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
+{
+        int r;
+
+        rdev->cp.ring_size = ring_size;
+        /* Allocate ring buffer */
+        if (rdev->cp.ring_obj == NULL) {
+                r = radeon_object_create(rdev, NULL, rdev->cp.ring_size,
+                                         true,
+                                         RADEON_GEM_DOMAIN_GTT,
+                                         false,
+                                         &rdev->cp.ring_obj);
+                if (r) {
+                        DRM_ERROR("radeon: failed to create ring buffer (%d).\n", r);
+                        mutex_unlock(&rdev->cp.mutex);
+                        return r;
+                }
+                r = radeon_object_pin(rdev->cp.ring_obj,
+                                      RADEON_GEM_DOMAIN_GTT,
+                                      &rdev->cp.gpu_addr);
+                if (r) {
+                        DRM_ERROR("radeon: failed to pin ring buffer (%d).\n", r);
+                        mutex_unlock(&rdev->cp.mutex);
+                        return r;
+                }
+                r = radeon_object_kmap(rdev->cp.ring_obj,
+                                       (void **)&rdev->cp.ring);
+                if (r) {
+                        DRM_ERROR("radeon: failed to map ring buffer (%d).\n", r);
+                        mutex_unlock(&rdev->cp.mutex);
+                        return r;
+                }
+        }
+        rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
+        rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
+        return 0;
+}
+
+void radeon_ring_fini(struct radeon_device *rdev)
+{
+        mutex_lock(&rdev->cp.mutex);
+        if (rdev->cp.ring_obj) {
+                radeon_object_kunmap(rdev->cp.ring_obj);
+                radeon_object_unpin(rdev->cp.ring_obj);
+                radeon_object_unref(&rdev->cp.ring_obj);
+                rdev->cp.ring = NULL;
+                rdev->cp.ring_obj = NULL;
+        }
+        mutex_unlock(&rdev->cp.mutex);
+}
+
+
+/*
+ * Debugfs info
+ */
+#if defined(CONFIG_DEBUG_FS)
+static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct radeon_ib *ib = node->info_ent->data;
+        unsigned i;
+
+        if (ib == NULL) {
+                return 0;
+        }
+        seq_printf(m, "IB %04lu\n", ib->idx);
+        seq_printf(m, "IB fence %p\n", ib->fence);
+        seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
+        for (i = 0; i < ib->length_dw; i++) {
+                seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
+        }
+        return 0;
+}
+
+static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
+static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
+#endif
+
+int radeon_debugfs_ib_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        unsigned i;
+
+        for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
+                sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
+                radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
+                radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
+                radeon_debugfs_ib_list[i].driver_features = 0;
+                radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
+        }
+        return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
+                                        RADEON_IB_POOL_SIZE);
+#else
+        return 0;
+#endif
+}
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
new file mode 100644
index 000000000000..4c087c1510d7
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -0,0 +1,653 @@
+/*
+ * Copyright 2009 Jerome Glisse.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ */
+/*
+ * Authors:
+ *    Jerome Glisse <glisse@freedesktop.org>
+ *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
+ *    Dave Airlie
+ */
+#include <ttm/ttm_bo_api.h>
+#include <ttm/ttm_bo_driver.h>
+#include <ttm/ttm_placement.h>
+#include <ttm/ttm_module.h>
+#include <drm/drmP.h>
+#include <drm/radeon_drm.h>
+#include "radeon_reg.h"
+#include "radeon.h"
+
+#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
+
+static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
+{
+        struct radeon_mman *mman;
+        struct radeon_device *rdev;
+
+        mman = container_of(bdev, struct radeon_mman, bdev);
+        rdev = container_of(mman, struct radeon_device, mman);
+        return rdev;
+}
+
+
+/*
+ * Global memory.
+ */
+static int radeon_ttm_mem_global_init(struct ttm_global_reference *ref)
+{
+        return ttm_mem_global_init(ref->object);
+}
+
+static void radeon_ttm_mem_global_release(struct ttm_global_reference *ref)
+{
+        ttm_mem_global_release(ref->object);
+}
+
+static int radeon_ttm_global_init(struct radeon_device *rdev)
+{
+        struct ttm_global_reference *global_ref;
+        int r;
+
+        rdev->mman.mem_global_referenced = false;
+        global_ref = &rdev->mman.mem_global_ref;
+        global_ref->global_type = TTM_GLOBAL_TTM_MEM;
+        global_ref->size = sizeof(struct ttm_mem_global);
+        global_ref->init = &radeon_ttm_mem_global_init;
+        global_ref->release = &radeon_ttm_mem_global_release;
+        r = ttm_global_item_ref(global_ref);
+        if (r != 0) {
+                DRM_ERROR("Failed referencing a global TTM memory object.\n");
+                return r;
+        }
+        rdev->mman.mem_global_referenced = true;
+        return 0;
+}
+
+static void radeon_ttm_global_fini(struct radeon_device *rdev)
+{
+        if (rdev->mman.mem_global_referenced) {
+                ttm_global_item_unref(&rdev->mman.mem_global_ref);
+                rdev->mman.mem_global_referenced = false;
+        }
+}
+
+struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev);
+
+static struct ttm_backend*
+radeon_create_ttm_backend_entry(struct ttm_bo_device *bdev)
+{
+        struct radeon_device *rdev;
+
+        rdev = radeon_get_rdev(bdev);
+#if __OS_HAS_AGP
+        if (rdev->flags & RADEON_IS_AGP) {
+                return ttm_agp_backend_init(bdev, rdev->ddev->agp->bridge);
+        } else
+#endif
+        {
+                return radeon_ttm_backend_create(rdev);
+        }
+}
+
+static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
+{
+        return 0;
+}
+
+static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
+                                struct ttm_mem_type_manager *man)
+{
+        struct radeon_device *rdev;
+
+        rdev = radeon_get_rdev(bdev);
+
+        switch (type) {
+        case TTM_PL_SYSTEM:
+                /* System memory */
+                man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
+                man->available_caching = TTM_PL_MASK_CACHING;
+                man->default_caching = TTM_PL_FLAG_CACHED;
+                break;
+        case TTM_PL_TT:
+                man->gpu_offset = 0;
+                man->available_caching = TTM_PL_MASK_CACHING;
+                man->default_caching = TTM_PL_FLAG_CACHED;
+#if __OS_HAS_AGP
+                if (rdev->flags & RADEON_IS_AGP) {
+                        if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
+                                DRM_ERROR("AGP is not enabled for memory type %u\n",
+                                          (unsigned)type);
+                                return -EINVAL;
+                        }
+                        man->io_offset = rdev->mc.agp_base;
+                        man->io_size = rdev->mc.gtt_size;
+                        man->io_addr = NULL;
+                        man->flags = TTM_MEMTYPE_FLAG_NEEDS_IOREMAP |
+                                     TTM_MEMTYPE_FLAG_MAPPABLE;
+                        man->available_caching = TTM_PL_FLAG_UNCACHED |
+                                                 TTM_PL_FLAG_WC;
+                        man->default_caching = TTM_PL_FLAG_WC;
+                } else
+#endif
+                {
+                        man->io_offset = 0;
+                        man->io_size = 0;
+                        man->io_addr = NULL;
+                        man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
+                                     TTM_MEMTYPE_FLAG_CMA;
+                }
+                break;
+        case TTM_PL_VRAM:
+                /* "On-card" video ram */
+                man->gpu_offset = 0;
+                man->flags = TTM_MEMTYPE_FLAG_FIXED |
+                             TTM_MEMTYPE_FLAG_NEEDS_IOREMAP |
+                             TTM_MEMTYPE_FLAG_MAPPABLE;
+                man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
+                man->default_caching = TTM_PL_FLAG_WC;
+                man->io_addr = NULL;
+                man->io_offset = rdev->mc.aper_base;
+                man->io_size = rdev->mc.aper_size;
+                break;
+        default:
+                DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static uint32_t radeon_evict_flags(struct ttm_buffer_object *bo)
+{
+        uint32_t cur_placement = bo->mem.placement & ~TTM_PL_MASK_MEMTYPE;
+
+        switch (bo->mem.mem_type) {
+        default:
+                return (cur_placement & ~TTM_PL_MASK_CACHING) |
+                        TTM_PL_FLAG_SYSTEM |
+                        TTM_PL_FLAG_CACHED;
+        }
+}
+
+static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
+{
+        return 0;
+}
+
+static void radeon_move_null(struct ttm_buffer_object *bo,
+                             struct ttm_mem_reg *new_mem)
+{
+        struct ttm_mem_reg *old_mem = &bo->mem;
+
+        BUG_ON(old_mem->mm_node != NULL);
+        *old_mem = *new_mem;
+        new_mem->mm_node = NULL;
+}
+
+static int radeon_move_blit(struct ttm_buffer_object *bo,
+                            bool evict, int no_wait,
+                            struct ttm_mem_reg *new_mem,
+                            struct ttm_mem_reg *old_mem)
+{
+        struct radeon_device *rdev;
+        uint64_t old_start, new_start;
+        struct radeon_fence *fence;
+        int r;
+
+        rdev = radeon_get_rdev(bo->bdev);
+        r = radeon_fence_create(rdev, &fence);
+        if (unlikely(r)) {
+                return r;
+        }
+        old_start = old_mem->mm_node->start << PAGE_SHIFT;
+        new_start = new_mem->mm_node->start << PAGE_SHIFT;
+
+        switch (old_mem->mem_type) {
+        case TTM_PL_VRAM:
+                old_start += rdev->mc.vram_location;
+                break;
+        case TTM_PL_TT:
+                old_start += rdev->mc.gtt_location;
+                break;
+        default:
+                DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
+                return -EINVAL;
+        }
+        switch (new_mem->mem_type) {
+        case TTM_PL_VRAM:
+                new_start += rdev->mc.vram_location;
+                break;
+        case TTM_PL_TT:
+                new_start += rdev->mc.gtt_location;
+                break;
+        default:
+                DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
+                return -EINVAL;
+        }
+        if (!rdev->cp.ready) {
+                DRM_ERROR("Trying to move memory with CP turned off.\n");
+                return -EINVAL;
+        }
+        r = radeon_copy(rdev, old_start, new_start, new_mem->num_pages, fence);
+        /* FIXME: handle copy error */
+        r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
+                                      evict, no_wait, new_mem);
+        radeon_fence_unref(&fence);
+        return r;
+}
+
+static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
+                                bool evict, bool interruptible, bool no_wait,
+                                struct ttm_mem_reg *new_mem)
+{
+        struct radeon_device *rdev;
+        struct ttm_mem_reg *old_mem = &bo->mem;
+        struct ttm_mem_reg tmp_mem;
+        uint32_t proposed_placement;
+        int r;
+
+        rdev = radeon_get_rdev(bo->bdev);
+        tmp_mem = *new_mem;
+        tmp_mem.mm_node = NULL;
+        proposed_placement = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
+        r = ttm_bo_mem_space(bo, proposed_placement, &tmp_mem,
+                             interruptible, no_wait);
+        if (unlikely(r)) {
+                return r;
+        }
+        r = ttm_tt_bind(bo->ttm, &tmp_mem);
+        if (unlikely(r)) {
+                goto out_cleanup;
+        }
+        r = radeon_move_blit(bo, true, no_wait, &tmp_mem, old_mem);
+        if (unlikely(r)) {
+                goto out_cleanup;
+        }
+        r = ttm_bo_move_ttm(bo, true, no_wait, new_mem);
+out_cleanup:
+        if (tmp_mem.mm_node) {
+                spin_lock(&rdev->mman.bdev.lru_lock);
+                drm_mm_put_block(tmp_mem.mm_node);
+                spin_unlock(&rdev->mman.bdev.lru_lock);
+                return r;
+        }
+        return r;
+}
+
+static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
+                                bool evict, bool interruptible, bool no_wait,
+                                struct ttm_mem_reg *new_mem)
+{
+        struct radeon_device *rdev;
+        struct ttm_mem_reg *old_mem = &bo->mem;
+        struct ttm_mem_reg tmp_mem;
+        uint32_t proposed_flags;
+        int r;
+
+        rdev = radeon_get_rdev(bo->bdev);
+        tmp_mem = *new_mem;
+        tmp_mem.mm_node = NULL;
+        proposed_flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
+        r = ttm_bo_mem_space(bo, proposed_flags, &tmp_mem,
+                             interruptible, no_wait);
+        if (unlikely(r)) {
+                return r;
+        }
+        r = ttm_bo_move_ttm(bo, true, no_wait, &tmp_mem);
+        if (unlikely(r)) {
+                goto out_cleanup;
+        }
+        r = radeon_move_blit(bo, true, no_wait, new_mem, old_mem);
+        if (unlikely(r)) {
+                goto out_cleanup;
+        }
+out_cleanup:
+        if (tmp_mem.mm_node) {
+                spin_lock(&rdev->mman.bdev.lru_lock);
+                drm_mm_put_block(tmp_mem.mm_node);
+                spin_unlock(&rdev->mman.bdev.lru_lock);
+                return r;
+        }
+        return r;
+}
+
+static int radeon_bo_move(struct ttm_buffer_object *bo,
+                          bool evict, bool interruptible, bool no_wait,
+                          struct ttm_mem_reg *new_mem)
+{
+        struct radeon_device *rdev;
+        struct ttm_mem_reg *old_mem = &bo->mem;
+        int r;
+
+        rdev = radeon_get_rdev(bo->bdev);
+        if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
+                radeon_move_null(bo, new_mem);
+                return 0;
+        }
+        if ((old_mem->mem_type == TTM_PL_TT &&
+             new_mem->mem_type == TTM_PL_SYSTEM) ||
+            (old_mem->mem_type == TTM_PL_SYSTEM &&
+             new_mem->mem_type == TTM_PL_TT)) {
+                /* bind is enought */
+                radeon_move_null(bo, new_mem);
+                return 0;
+        }
+        if (!rdev->cp.ready) {
+                /* use memcpy */
+                DRM_ERROR("CP is not ready use memcpy.\n");
+                return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem);
+        }
+
+        if (old_mem->mem_type == TTM_PL_VRAM &&
+            new_mem->mem_type == TTM_PL_SYSTEM) {
+                return radeon_move_vram_ram(bo, evict, interruptible,
+                                            no_wait, new_mem);
+        } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
+                   new_mem->mem_type == TTM_PL_VRAM) {
+                return radeon_move_ram_vram(bo, evict, interruptible,
+                                            no_wait, new_mem);
+        } else {
+                r = radeon_move_blit(bo, evict, no_wait, new_mem, old_mem);
+                if (unlikely(r)) {
+                        return r;
+                }
+        }
+        return r;
+}
+
+const uint32_t radeon_mem_prios[] = {
+        TTM_PL_VRAM,
+        TTM_PL_TT,
+        TTM_PL_SYSTEM,
+};
+
+const uint32_t radeon_busy_prios[] = {
+        TTM_PL_TT,
+        TTM_PL_VRAM,
+        TTM_PL_SYSTEM,
+};
+
+static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg,
+                                bool lazy, bool interruptible)
+{
+        return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
+}
+
+static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg)
+{
+        return 0;
+}
+
+static void radeon_sync_obj_unref(void **sync_obj)
+{
+        radeon_fence_unref((struct radeon_fence **)sync_obj);
+}
+
+static void *radeon_sync_obj_ref(void *sync_obj)
+{
+        return radeon_fence_ref((struct radeon_fence *)sync_obj);
+}
+
+static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg)
+{
+        return radeon_fence_signaled((struct radeon_fence *)sync_obj);
+}
+
+static struct ttm_bo_driver radeon_bo_driver = {
+        .mem_type_prio = radeon_mem_prios,
+        .mem_busy_prio = radeon_busy_prios,
+        .num_mem_type_prio = ARRAY_SIZE(radeon_mem_prios),
+        .num_mem_busy_prio = ARRAY_SIZE(radeon_busy_prios),
+        .create_ttm_backend_entry = &radeon_create_ttm_backend_entry,
+        .invalidate_caches = &radeon_invalidate_caches,
+        .init_mem_type = &radeon_init_mem_type,
+        .evict_flags = &radeon_evict_flags,
+        .move = &radeon_bo_move,
+        .verify_access = &radeon_verify_access,
+        .sync_obj_signaled = &radeon_sync_obj_signaled,
+        .sync_obj_wait = &radeon_sync_obj_wait,
+        .sync_obj_flush = &radeon_sync_obj_flush,
+        .sync_obj_unref = &radeon_sync_obj_unref,
+        .sync_obj_ref = &radeon_sync_obj_ref,
+};
+
+int radeon_ttm_init(struct radeon_device *rdev)
+{
+        int r;
+
+        r = radeon_ttm_global_init(rdev);
+        if (r) {
+                return r;
+        }
+        /* No others user of address space so set it to 0 */
+        r = ttm_bo_device_init(&rdev->mman.bdev,
+                               rdev->mman.mem_global_ref.object,
+                               &radeon_bo_driver, DRM_FILE_PAGE_OFFSET);
+        if (r) {
+                DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
+                return r;
+        }
+        r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 0,
+                           ((rdev->mc.aper_size) >> PAGE_SHIFT));
+        if (r) {
+                DRM_ERROR("Failed initializing VRAM heap.\n");
+                return r;
+        }
+        r = radeon_object_create(rdev, NULL, 256 * 1024, true,
+                                 RADEON_GEM_DOMAIN_VRAM, false,
+                                 &rdev->stollen_vga_memory);
+        if (r) {
+                return r;
+        }
+        r = radeon_object_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
+        if (r) {
+                radeon_object_unref(&rdev->stollen_vga_memory);
+                return r;
+        }
+        DRM_INFO("radeon: %uM of VRAM memory ready\n",
+                 rdev->mc.vram_size / (1024 * 1024));
+        r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 0,
+                           ((rdev->mc.gtt_size) >> PAGE_SHIFT));
+        if (r) {
+                DRM_ERROR("Failed initializing GTT heap.\n");
+                return r;
+        }
+        DRM_INFO("radeon: %uM of GTT memory ready.\n",
+                 rdev->mc.gtt_size / (1024 * 1024));
+        if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
+                rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
+        }
+        return 0;
+}
+
+void radeon_ttm_fini(struct radeon_device *rdev)
+{
+        if (rdev->stollen_vga_memory) {
+                radeon_object_unpin(rdev->stollen_vga_memory);
+                radeon_object_unref(&rdev->stollen_vga_memory);
+        }
+        ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
+        ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
+        ttm_bo_device_release(&rdev->mman.bdev);
+        radeon_gart_fini(rdev);
+        radeon_ttm_global_fini(rdev);
+        DRM_INFO("radeon: ttm finalized\n");
+}
+
+static struct vm_operations_struct radeon_ttm_vm_ops;
+static struct vm_operations_struct *ttm_vm_ops = NULL;
+
+static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+{
+        struct ttm_buffer_object *bo;
+        int r;
+
+        bo = (struct ttm_buffer_object *)vma->vm_private_data;
+        if (bo == NULL) {
+                return VM_FAULT_NOPAGE;
+        }
+        r = ttm_vm_ops->fault(vma, vmf);
+        return r;
+}
+
+int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+        struct drm_file *file_priv;
+        struct radeon_device *rdev;
+        int r;
+
+        if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
+                return drm_mmap(filp, vma);
+        }
+
+        file_priv = (struct drm_file *)filp->private_data;
+        rdev = file_priv->minor->dev->dev_private;
+        if (rdev == NULL) {
+                return -EINVAL;
+        }
+        r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
+        if (unlikely(r != 0)) {
+                return r;
+        }
+        if (unlikely(ttm_vm_ops == NULL)) {
+                ttm_vm_ops = vma->vm_ops;
+                radeon_ttm_vm_ops = *ttm_vm_ops;
+                radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
+        }
+        vma->vm_ops = &radeon_ttm_vm_ops;
+        return 0;
+}
+
+
+/*
+ * TTM backend functions.
+ */
+struct radeon_ttm_backend {
+        struct ttm_backend              backend;
+        struct radeon_device            *rdev;
+        unsigned long                   num_pages;
+        struct page                     **pages;
+        struct page                     *dummy_read_page;
+        bool                            populated;
+        bool                            bound;
+        unsigned                        offset;
+};
+
+static int radeon_ttm_backend_populate(struct ttm_backend *backend,
+                                       unsigned long num_pages,
+                                       struct page **pages,
+                                       struct page *dummy_read_page)
+{
+        struct radeon_ttm_backend *gtt;
+
+        gtt = container_of(backend, struct radeon_ttm_backend, backend);
+        gtt->pages = pages;
+        gtt->num_pages = num_pages;
+        gtt->dummy_read_page = dummy_read_page;
+        gtt->populated = true;
+        return 0;
+}
+
+static void radeon_ttm_backend_clear(struct ttm_backend *backend)
+{
+        struct radeon_ttm_backend *gtt;
+
+        gtt = container_of(backend, struct radeon_ttm_backend, backend);
+        gtt->pages = NULL;
+        gtt->num_pages = 0;
+        gtt->dummy_read_page = NULL;
+        gtt->populated = false;
+        gtt->bound = false;
+}
+
+
+static int radeon_ttm_backend_bind(struct ttm_backend *backend,
+                                   struct ttm_mem_reg *bo_mem)
+{
+        struct radeon_ttm_backend *gtt;
+        int r;
+
+        gtt = container_of(backend, struct radeon_ttm_backend, backend);
+        gtt->offset = bo_mem->mm_node->start << PAGE_SHIFT;
+        if (!gtt->num_pages) {
+                WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", gtt->num_pages, bo_mem, backend);
+        }
+        r = radeon_gart_bind(gtt->rdev, gtt->offset,
+                             gtt->num_pages, gtt->pages);
+        if (r) {
+                DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
+                          gtt->num_pages, gtt->offset);
+                return r;
+        }
+        gtt->bound = true;
+        return 0;
+}
+
+static int radeon_ttm_backend_unbind(struct ttm_backend *backend)
+{
+        struct radeon_ttm_backend *gtt;
+
+        gtt = container_of(backend, struct radeon_ttm_backend, backend);
+        radeon_gart_unbind(gtt->rdev, gtt->offset, gtt->num_pages);
+        gtt->bound = false;
+        return 0;
+}
+
+static void radeon_ttm_backend_destroy(struct ttm_backend *backend)
+{
+        struct radeon_ttm_backend *gtt;
+
+        gtt = container_of(backend, struct radeon_ttm_backend, backend);
+        if (gtt->bound) {
+                radeon_ttm_backend_unbind(backend);
+        }
+        kfree(gtt);
+}
+
+static struct ttm_backend_func radeon_backend_func = {
+        .populate = &radeon_ttm_backend_populate,
+        .clear = &radeon_ttm_backend_clear,
+        .bind = &radeon_ttm_backend_bind,
+        .unbind = &radeon_ttm_backend_unbind,
+        .destroy = &radeon_ttm_backend_destroy,
+};
+
+struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev)
+{
+        struct radeon_ttm_backend *gtt;
+
+        gtt = kzalloc(sizeof(struct radeon_ttm_backend), GFP_KERNEL);
+        if (gtt == NULL) {
+                return NULL;
+        }
+        gtt->backend.bdev = &rdev->mman.bdev;
+        gtt->backend.flags = 0;
+        gtt->backend.func = &radeon_backend_func;
+        gtt->rdev = rdev;
+        gtt->pages = NULL;
+        gtt->num_pages = 0;
+        gtt->dummy_read_page = NULL;
+        gtt->populated = false;
+        gtt->bound = false;
+        return &gtt->backend;
+}
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
new file mode 100644
index 000000000000..cc074b5a8f74
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include <linux/seq_file.h>
+#include <drm/drmP.h>
+#include "radeon_reg.h"
+#include "radeon.h"
+
+/* rs400,rs480 depends on : */
+void r100_hdp_reset(struct radeon_device *rdev);
+void r100_mc_disable_clients(struct radeon_device *rdev);
+int r300_mc_wait_for_idle(struct radeon_device *rdev);
+void r420_pipes_init(struct radeon_device *rdev);
+
+/* This files gather functions specifics to :
+ * rs400,rs480
+ *
+ * Some of these functions might be used by newer ASICs.
+ */
+void rs400_gpu_init(struct radeon_device *rdev);
+int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
+
+
+/*
+ * GART functions.
+ */
+void rs400_gart_adjust_size(struct radeon_device *rdev)
+{
+        /* Check gart size */
+        switch (rdev->mc.gtt_size/(1024*1024)) {
+        case 32:
+        case 64:
+        case 128:
+        case 256:
+        case 512:
+        case 1024:
+        case 2048:
+                break;
+        default:
+                DRM_ERROR("Unable to use IGP GART size %uM\n",
+                          rdev->mc.gtt_size >> 20);
+                DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
+                DRM_ERROR("Forcing to 32M GART size\n");
+                rdev->mc.gtt_size = 32 * 1024 * 1024;
+                return;
+        }
+        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
+                /* FIXME: RS400 & RS480 seems to have issue with GART size
+                 * if 4G of system memory (needs more testing) */
+                rdev->mc.gtt_size = 32 * 1024 * 1024;
+                DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
+        }
+}
+
+void rs400_gart_tlb_flush(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        unsigned int timeout = rdev->usec_timeout;
+
+        WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
+        do {
+                tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
+                if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
+                        break;
+                DRM_UDELAY(1);
+                timeout--;
+        } while (timeout > 0);
+        WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
+}
+
+int rs400_gart_enable(struct radeon_device *rdev)
+{
+        uint32_t size_reg;
+        uint32_t tmp;
+        int r;
+
+        /* Initialize common gart structure */
+        r = radeon_gart_init(rdev);
+        if (r) {
+                return r;
+        }
+        if (rs400_debugfs_pcie_gart_info_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
+        }
+
+        tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
+        tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
+        WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
+        /* Check gart size */
+        switch(rdev->mc.gtt_size / (1024 * 1024)) {
+        case 32:
+                size_reg = RS480_VA_SIZE_32MB;
+                break;
+        case 64:
+                size_reg = RS480_VA_SIZE_64MB;
+                break;
+        case 128:
+                size_reg = RS480_VA_SIZE_128MB;
+                break;
+        case 256:
+                size_reg = RS480_VA_SIZE_256MB;
+                break;
+        case 512:
+                size_reg = RS480_VA_SIZE_512MB;
+                break;
+        case 1024:
+                size_reg = RS480_VA_SIZE_1GB;
+                break;
+        case 2048:
+                size_reg = RS480_VA_SIZE_2GB;
+                break;
+        default:
+                return -EINVAL;
+        }
+        if (rdev->gart.table.ram.ptr == NULL) {
+                rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
+                r = radeon_gart_table_ram_alloc(rdev);
+                if (r) {
+                        return r;
+                }
+        }
+        /* It should be fine to program it to max value */
+        if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
+                WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
+                WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
+        } else {
+                WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
+                WREG32(RS480_AGP_BASE_2, 0);
+        }
+        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
+        tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16);
+        tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16);
+        if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
+                WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
+                tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
+                WREG32(RADEON_BUS_CNTL, tmp);
+        } else {
+                WREG32(RADEON_MC_AGP_LOCATION, tmp);
+                tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
+                WREG32(RADEON_BUS_CNTL, tmp);
+        }
+        /* Table should be in 32bits address space so ignore bits above. */
+        tmp = rdev->gart.table_addr & 0xfffff000;
+        WREG32_MC(RS480_GART_BASE, tmp);
+        /* TODO: more tweaking here */
+        WREG32_MC(RS480_GART_FEATURE_ID,
+                  (RS480_TLB_ENABLE |
+                   RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
+        /* Disable snooping */
+        WREG32_MC(RS480_AGP_MODE_CNTL,
+                  (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
+        /* Disable AGP mode */
+        /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
+         * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
+        if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
+                WREG32_MC(RS480_MC_MISC_CNTL,
+                          (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
+        } else {
+                WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
+        }
+        /* Enable gart */
+        WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
+        rs400_gart_tlb_flush(rdev);
+        rdev->gart.ready = true;
+        return 0;
+}
+
+void rs400_gart_disable(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
+        tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
+        WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
+        WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
+}
+
+int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
+{
+        if (i < 0 || i > rdev->gart.num_gpu_pages) {
+                return -EINVAL;
+        }
+        rdev->gart.table.ram.ptr[i] = cpu_to_le32(((uint32_t)addr) | 0xC);
+        return 0;
+}
+
+
+/*
+ * MC functions.
+ */
+int rs400_mc_init(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        int r;
+
+        if (r100_debugfs_rbbm_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
+        }
+
+        rs400_gpu_init(rdev);
+        rs400_gart_disable(rdev);
+        rdev->mc.gtt_location = rdev->mc.vram_size;
+        rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
+        rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
+        rdev->mc.vram_location = 0xFFFFFFFFUL;
+        r = radeon_mc_setup(rdev);
+        if (r) {
+                return r;
+        }
+
+        r100_mc_disable_clients(rdev);
+        if (r300_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+
+        tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+        tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
+        tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
+        WREG32(RADEON_MC_FB_LOCATION, tmp);
+        tmp = RREG32(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS;
+        WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
+        (void)RREG32(RADEON_HOST_PATH_CNTL);
+        WREG32(RADEON_HOST_PATH_CNTL, tmp);
+        (void)RREG32(RADEON_HOST_PATH_CNTL);
+        return 0;
+}
+
+void rs400_mc_fini(struct radeon_device *rdev)
+{
+        rs400_gart_disable(rdev);
+        radeon_gart_table_ram_free(rdev);
+        radeon_gart_fini(rdev);
+}
+
+
+/*
+ * Global GPU functions
+ */
+void rs400_errata(struct radeon_device *rdev)
+{
+        rdev->pll_errata = 0;
+}
+
+void rs400_gpu_init(struct radeon_device *rdev)
+{
+        /* FIXME: HDP same place on rs400 ? */
+        r100_hdp_reset(rdev);
+        /* FIXME: is this correct ? */
+        r420_pipes_init(rdev);
+        if (r300_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+}
+
+
+/*
+ * VRAM info.
+ */
+void rs400_vram_info(struct radeon_device *rdev)
+{
+        uint32_t tom;
+
+        rs400_gart_adjust_size(rdev);
+        /* DDR for all card after R300 & IGP */
+        rdev->mc.vram_is_ddr = true;
+        rdev->mc.vram_width = 128;
+
+        /* read NB_TOM to get the amount of ram stolen for the GPU */
+        tom = RREG32(RADEON_NB_TOM);
+        rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
+        WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+
+        /* Could aper size report 0 ? */
+        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+}
+
+
+/*
+ * Indirect registers accessor
+ */
+uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        uint32_t r;
+
+        WREG32(RS480_NB_MC_INDEX, reg & 0xff);
+        r = RREG32(RS480_NB_MC_DATA);
+        WREG32(RS480_NB_MC_INDEX, 0xff);
+        return r;
+}
+
+void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
+        WREG32(RS480_NB_MC_DATA, (v));
+        WREG32(RS480_NB_MC_INDEX, 0xff);
+}
+
+
+/*
+ * Debugfs info
+ */
+#if defined(CONFIG_DEBUG_FS)
+static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t tmp;
+
+        tmp = RREG32(RADEON_HOST_PATH_CNTL);
+        seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
+        tmp = RREG32(RADEON_BUS_CNTL);
+        seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
+        tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
+        seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
+        if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
+                tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
+                seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
+                tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
+                seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
+                tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
+                seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
+                tmp = RREG32_MC(0x100);
+                seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
+                tmp = RREG32(0x134);
+                seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
+        } else {
+                tmp = RREG32(RADEON_AGP_BASE);
+                seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
+                tmp = RREG32(RS480_AGP_BASE_2);
+                seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
+                tmp = RREG32(RADEON_MC_AGP_LOCATION);
+                seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
+        }
+        tmp = RREG32_MC(RS480_GART_BASE);
+        seq_printf(m, "GART_BASE 0x%08x\n", tmp);
+        tmp = RREG32_MC(RS480_GART_FEATURE_ID);
+        seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
+        tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
+        seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
+        tmp = RREG32_MC(RS480_MC_MISC_CNTL);
+        seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
+        tmp = RREG32_MC(0x5F);
+        seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
+        tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
+        seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
+        tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
+        seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
+        tmp = RREG32_MC(0x3B);
+        seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
+        tmp = RREG32_MC(0x3C);
+        seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
+        tmp = RREG32_MC(0x30);
+        seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
+        tmp = RREG32_MC(0x31);
+        seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
+        tmp = RREG32_MC(0x32);
+        seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
+        tmp = RREG32_MC(0x33);
+        seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
+        tmp = RREG32_MC(0x34);
+        seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
+        tmp = RREG32_MC(0x35);
+        seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
+        tmp = RREG32_MC(0x36);
+        seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
+        tmp = RREG32_MC(0x37);
+        seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
+        return 0;
+}
+
+static struct drm_info_list rs400_gart_info_list[] = {
+        {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
+};
+#endif
+
+int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
+#else
+        return 0;
+#endif
+}
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
new file mode 100644
index 000000000000..ab0c967553e6
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+/* rs600 depends on : */
+void r100_hdp_reset(struct radeon_device *rdev);
+int r100_gui_wait_for_idle(struct radeon_device *rdev);
+int r300_mc_wait_for_idle(struct radeon_device *rdev);
+void r420_pipes_init(struct radeon_device *rdev);
+
+/* This files gather functions specifics to :
+ * rs600
+ *
+ * Some of these functions might be used by newer ASICs.
+ */
+void rs600_gpu_init(struct radeon_device *rdev);
+int rs600_mc_wait_for_idle(struct radeon_device *rdev);
+void rs600_disable_vga(struct radeon_device *rdev);
+
+
+/*
+ * GART.
+ */
+void rs600_gart_tlb_flush(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        tmp = RREG32_MC(RS600_MC_PT0_CNTL);
+        tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
+        WREG32_MC(RS600_MC_PT0_CNTL, tmp);
+
+        tmp = RREG32_MC(RS600_MC_PT0_CNTL);
+        tmp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
+        WREG32_MC(RS600_MC_PT0_CNTL, tmp);
+
+        tmp = RREG32_MC(RS600_MC_PT0_CNTL);
+        tmp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
+        WREG32_MC(RS600_MC_PT0_CNTL, tmp);
+        tmp = RREG32_MC(RS600_MC_PT0_CNTL);
+}
+
+int rs600_gart_enable(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        int i;
+        int r;
+
+        /* Initialize common gart structure */
+        r = radeon_gart_init(rdev);
+        if (r) {
+                return r;
+        }
+        rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
+        r = radeon_gart_table_vram_alloc(rdev);
+        if (r) {
+                return r;
+        }
+        /* FIXME: setup default page */
+        WREG32_MC(RS600_MC_PT0_CNTL,
+                 (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
+                  RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
+        for (i = 0; i < 19; i++) {
+                WREG32_MC(RS600_MC_PT0_CLIENT0_CNTL + i,
+                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
+                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
+                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE |
+                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
+                          RS600_ENABLE_FRAGMENT_PROCESSING |
+                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
+        }
+
+        /* System context map to GART space */
+        WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_location);
+        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
+        WREG32_MC(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, tmp);
+
+        /* enable first context */
+        WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_location);
+        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
+        WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, tmp);
+        WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL,
+                 (RS600_ENABLE_PAGE_TABLE | RS600_PAGE_TABLE_TYPE_FLAT));
+        /* disable all other contexts */
+        for (i = 1; i < 8; i++) {
+                WREG32_MC(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
+        }
+
+        /* setup the page table */
+        WREG32_MC(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
+                 rdev->gart.table_addr);
+        WREG32_MC(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
+
+        /* enable page tables */
+        tmp = RREG32_MC(RS600_MC_PT0_CNTL);
+        WREG32_MC(RS600_MC_PT0_CNTL, (tmp | RS600_ENABLE_PT));
+        tmp = RREG32_MC(RS600_MC_CNTL1);
+        WREG32_MC(RS600_MC_CNTL1, (tmp | RS600_ENABLE_PAGE_TABLES));
+        rs600_gart_tlb_flush(rdev);
+        rdev->gart.ready = true;
+        return 0;
+}
+
+void rs600_gart_disable(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        /* FIXME: disable out of gart access */
+        WREG32_MC(RS600_MC_PT0_CNTL, 0);
+        tmp = RREG32_MC(RS600_MC_CNTL1);
+        tmp &= ~RS600_ENABLE_PAGE_TABLES;
+        WREG32_MC(RS600_MC_CNTL1, tmp);
+        radeon_object_kunmap(rdev->gart.table.vram.robj);
+        radeon_object_unpin(rdev->gart.table.vram.robj);
+}
+
+#define R600_PTE_VALID     (1 << 0)
+#define R600_PTE_SYSTEM    (1 << 1)
+#define R600_PTE_SNOOPED   (1 << 2)
+#define R600_PTE_READABLE  (1 << 5)
+#define R600_PTE_WRITEABLE (1 << 6)
+
+int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
+{
+        void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+
+        if (i < 0 || i > rdev->gart.num_gpu_pages) {
+                return -EINVAL;
+        }
+        addr = addr & 0xFFFFFFFFFFFFF000ULL;
+        addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
+        addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
+        writeq(addr, ((void __iomem *)ptr) + (i * 8));
+        return 0;
+}
+
+
+/*
+ * MC.
+ */
+void rs600_mc_disable_clients(struct radeon_device *rdev)
+{
+        unsigned tmp;
+
+        if (r100_gui_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait GUI idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+
+        tmp = RREG32(AVIVO_D1VGA_CONTROL);
+        WREG32(AVIVO_D1VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
+        tmp = RREG32(AVIVO_D2VGA_CONTROL);
+        WREG32(AVIVO_D2VGA_CONTROL, tmp & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
+
+        tmp = RREG32(AVIVO_D1CRTC_CONTROL);
+        WREG32(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
+        tmp = RREG32(AVIVO_D2CRTC_CONTROL);
+        WREG32(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN);
+
+        /* make sure all previous write got through */
+        tmp = RREG32(AVIVO_D2CRTC_CONTROL);
+
+        mdelay(1);
+}
+
+int rs600_mc_init(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        int r;
+
+        if (r100_debugfs_rbbm_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
+        }
+
+        rs600_gpu_init(rdev);
+        rs600_gart_disable(rdev);
+
+        /* Setup GPU memory space */
+        rdev->mc.vram_location = 0xFFFFFFFFUL;
+        rdev->mc.gtt_location = 0xFFFFFFFFUL;
+        r = radeon_mc_setup(rdev);
+        if (r) {
+                return r;
+        }
+
+        /* Program GPU memory space */
+        /* Enable bus master */
+        tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
+        WREG32(RADEON_BUS_CNTL, tmp);
+        /* FIXME: What does AGP means for such chipset ? */
+        WREG32_MC(RS600_MC_AGP_LOCATION, 0x0FFFFFFF);
+        /* FIXME: are this AGP reg in indirect MC range ? */
+        WREG32_MC(RS600_MC_AGP_BASE, 0);
+        WREG32_MC(RS600_MC_AGP_BASE_2, 0);
+        rs600_mc_disable_clients(rdev);
+        if (rs600_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+        tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+        tmp = REG_SET(RS600_MC_FB_TOP, tmp >> 16);
+        tmp |= REG_SET(RS600_MC_FB_START, rdev->mc.vram_location >> 16);
+        WREG32_MC(RS600_MC_FB_LOCATION, tmp);
+        WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
+        return 0;
+}
+
+void rs600_mc_fini(struct radeon_device *rdev)
+{
+        rs600_gart_disable(rdev);
+        radeon_gart_table_vram_free(rdev);
+        radeon_gart_fini(rdev);
+}
+
+
+/*
+ * Global GPU functions
+ */
+void rs600_disable_vga(struct radeon_device *rdev)
+{
+        unsigned tmp;
+
+        WREG32(0x330, 0);
+        WREG32(0x338, 0);
+        tmp = RREG32(0x300);
+        tmp &= ~(3 << 16);
+        WREG32(0x300, tmp);
+        WREG32(0x308, (1 << 8));
+        WREG32(0x310, rdev->mc.vram_location);
+        WREG32(0x594, 0);
+}
+
+int rs600_mc_wait_for_idle(struct radeon_device *rdev)
+{
+        unsigned i;
+        uint32_t tmp;
+
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                /* read MC_STATUS */
+                tmp = RREG32_MC(RS600_MC_STATUS);
+                if (tmp & RS600_MC_STATUS_IDLE) {
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        return -1;
+}
+
+void rs600_errata(struct radeon_device *rdev)
+{
+        rdev->pll_errata = 0;
+}
+
+void rs600_gpu_init(struct radeon_device *rdev)
+{
+        /* FIXME: HDP same place on rs600 ? */
+        r100_hdp_reset(rdev);
+        rs600_disable_vga(rdev);
+        /* FIXME: is this correct ? */
+        r420_pipes_init(rdev);
+        if (rs600_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+}
+
+
+/*
+ * VRAM info.
+ */
+void rs600_vram_info(struct radeon_device *rdev)
+{
+        /* FIXME: to do or is these values sane ? */
+        rdev->mc.vram_is_ddr = true;
+        rdev->mc.vram_width = 128;
+}
+
+
+/*
+ * Indirect registers accessor
+ */
+uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        uint32_t r;
+
+        WREG32(RS600_MC_INDEX,
+               ((reg & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0));
+        r = RREG32(RS600_MC_DATA);
+        return r;
+}
+
+void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        WREG32(RS600_MC_INDEX,
+                RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 |
+                ((reg) & RS600_MC_ADDR_MASK));
+        WREG32(RS600_MC_DATA, v);
+}
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
new file mode 100644
index 000000000000..79ba85042b5f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+/* rs690,rs740 depends on : */
+void r100_hdp_reset(struct radeon_device *rdev);
+int r300_mc_wait_for_idle(struct radeon_device *rdev);
+void r420_pipes_init(struct radeon_device *rdev);
+void rs400_gart_disable(struct radeon_device *rdev);
+int rs400_gart_enable(struct radeon_device *rdev);
+void rs400_gart_adjust_size(struct radeon_device *rdev);
+void rs600_mc_disable_clients(struct radeon_device *rdev);
+void rs600_disable_vga(struct radeon_device *rdev);
+
+/* This files gather functions specifics to :
+ * rs690,rs740
+ *
+ * Some of these functions might be used by newer ASICs.
+ */
+void rs690_gpu_init(struct radeon_device *rdev);
+int rs690_mc_wait_for_idle(struct radeon_device *rdev);
+
+
+/*
+ * MC functions.
+ */
+int rs690_mc_init(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        int r;
+
+        if (r100_debugfs_rbbm_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
+        }
+
+        rs690_gpu_init(rdev);
+        rs400_gart_disable(rdev);
+
+        /* Setup GPU memory space */
+        rdev->mc.gtt_location = rdev->mc.vram_size;
+        rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
+        rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
+        rdev->mc.vram_location = 0xFFFFFFFFUL;
+        r = radeon_mc_setup(rdev);
+        if (r) {
+                return r;
+        }
+
+        /* Program GPU memory space */
+        rs600_mc_disable_clients(rdev);
+        if (rs690_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+        tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+        tmp = REG_SET(RS690_MC_FB_TOP, tmp >> 16);
+        tmp |= REG_SET(RS690_MC_FB_START, rdev->mc.vram_location >> 16);
+        WREG32_MC(RS690_MCCFG_FB_LOCATION, tmp);
+        /* FIXME: Does this reg exist on RS480,RS740 ? */
+        WREG32(0x310, rdev->mc.vram_location);
+        WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
+        return 0;
+}
+
+void rs690_mc_fini(struct radeon_device *rdev)
+{
+        rs400_gart_disable(rdev);
+        radeon_gart_table_ram_free(rdev);
+        radeon_gart_fini(rdev);
+}
+
+
+/*
+ * Global GPU functions
+ */
+int rs690_mc_wait_for_idle(struct radeon_device *rdev)
+{
+        unsigned i;
+        uint32_t tmp;
+
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                /* read MC_STATUS */
+                tmp = RREG32_MC(RS690_MC_STATUS);
+                if (tmp & RS690_MC_STATUS_IDLE) {
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        return -1;
+}
+
+void rs690_errata(struct radeon_device *rdev)
+{
+        rdev->pll_errata = 0;
+}
+
+void rs690_gpu_init(struct radeon_device *rdev)
+{
+        /* FIXME: HDP same place on rs690 ? */
+        r100_hdp_reset(rdev);
+        rs600_disable_vga(rdev);
+        /* FIXME: is this correct ? */
+        r420_pipes_init(rdev);
+        if (rs690_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+}
+
+
+/*
+ * VRAM info.
+ */
+void rs690_vram_info(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        rs400_gart_adjust_size(rdev);
+        /* DDR for all card after R300 & IGP */
+        rdev->mc.vram_is_ddr = true;
+        /* FIXME: is this correct for RS690/RS740 ? */
+        tmp = RREG32(RADEON_MEM_CNTL);
+        if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
+                rdev->mc.vram_width = 128;
+        } else {
+                rdev->mc.vram_width = 64;
+        }
+        rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
+
+        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+}
+
+
+/*
+ * Indirect registers accessor
+ */
+uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        uint32_t r;
+
+        WREG32(RS690_MC_INDEX, (reg & RS690_MC_INDEX_MASK));
+        r = RREG32(RS690_MC_DATA);
+        WREG32(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
+        return r;
+}
+
+void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        WREG32(RS690_MC_INDEX,
+               RS690_MC_INDEX_WR_EN | ((reg) & RS690_MC_INDEX_MASK));
+        WREG32(RS690_MC_DATA, v);
+        WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
+}
diff --git a/drivers/gpu/drm/radeon/rs780.c b/drivers/gpu/drm/radeon/rs780.c
new file mode 100644
index 000000000000..0affcff81825
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rs780.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+/* rs780  depends on : */
+void rs600_mc_disable_clients(struct radeon_device *rdev);
+
+/* This files gather functions specifics to:
+ * rs780
+ *
+ * Some of these functions might be used by newer ASICs.
+ */
+int rs780_mc_wait_for_idle(struct radeon_device *rdev);
+void rs780_gpu_init(struct radeon_device *rdev);
+
+
+/*
+ * MC
+ */
+int rs780_mc_init(struct radeon_device *rdev)
+{
+        rs780_gpu_init(rdev);
+        /* FIXME: implement */
+
+        rs600_mc_disable_clients(rdev);
+        if (rs780_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+        return 0;
+}
+
+void rs780_mc_fini(struct radeon_device *rdev)
+{
+        /* FIXME: implement */
+}
+
+
+/*
+ * Global GPU functions
+ */
+void rs780_errata(struct radeon_device *rdev)
+{
+        rdev->pll_errata = 0;
+}
+
+int rs780_mc_wait_for_idle(struct radeon_device *rdev)
+{
+        /* FIXME: implement */
+        return 0;
+}
+
+void rs780_gpu_init(struct radeon_device *rdev)
+{
+        /* FIXME: implement */
+}
+
+
+/*
+ * VRAM info
+ */
+void rs780_vram_get_type(struct radeon_device *rdev)
+{
+        /* FIXME: implement */
+}
+
+void rs780_vram_info(struct radeon_device *rdev)
+{
+        rs780_vram_get_type(rdev);
+
+        /* FIXME: implement */
+        /* Could aper size report 0 ? */
+        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+}
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
new file mode 100644
index 000000000000..7eab95db58ac
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include <linux/seq_file.h>
+#include "drmP.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+/* rv515 depends on : */
+void r100_hdp_reset(struct radeon_device *rdev);
+int r100_cp_reset(struct radeon_device *rdev);
+int r100_rb2d_reset(struct radeon_device *rdev);
+int r100_gui_wait_for_idle(struct radeon_device *rdev);
+int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
+int rv370_pcie_gart_enable(struct radeon_device *rdev);
+void rv370_pcie_gart_disable(struct radeon_device *rdev);
+void r420_pipes_init(struct radeon_device *rdev);
+void rs600_mc_disable_clients(struct radeon_device *rdev);
+void rs600_disable_vga(struct radeon_device *rdev);
+
+/* This files gather functions specifics to:
+ * rv515
+ *
+ * Some of these functions might be used by newer ASICs.
+ */
+int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
+int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
+void rv515_gpu_init(struct radeon_device *rdev);
+int rv515_mc_wait_for_idle(struct radeon_device *rdev);
+
+
+/*
+ * MC
+ */
+int rv515_mc_init(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        int r;
+
+        if (r100_debugfs_rbbm_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for RBBM !\n");
+        }
+        if (rv515_debugfs_pipes_info_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for pipes !\n");
+        }
+        if (rv515_debugfs_ga_info_init(rdev)) {
+                DRM_ERROR("Failed to register debugfs file for pipes !\n");
+        }
+
+        rv515_gpu_init(rdev);
+        rv370_pcie_gart_disable(rdev);
+
+        /* Setup GPU memory space */
+        rdev->mc.vram_location = 0xFFFFFFFFUL;
+        rdev->mc.gtt_location = 0xFFFFFFFFUL;
+        if (rdev->flags & RADEON_IS_AGP) {
+                r = radeon_agp_init(rdev);
+                if (r) {
+                        printk(KERN_WARNING "[drm] Disabling AGP\n");
+                        rdev->flags &= ~RADEON_IS_AGP;
+                        rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
+                } else {
+                        rdev->mc.gtt_location = rdev->mc.agp_base;
+                }
+        }
+        r = radeon_mc_setup(rdev);
+        if (r) {
+                return r;
+        }
+
+        /* Program GPU memory space */
+        rs600_mc_disable_clients(rdev);
+        if (rv515_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+        /* Write VRAM size in case we are limiting it */
+        WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
+        tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
+        WREG32(0x134, tmp);
+        tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+        tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16);
+        tmp |= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
+        WREG32_MC(RV515_MC_FB_LOCATION, tmp);
+        WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
+        WREG32(0x310, rdev->mc.vram_location);
+        if (rdev->flags & RADEON_IS_AGP) {
+                tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
+                tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16);
+                tmp |= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16);
+                WREG32_MC(RV515_MC_AGP_LOCATION, tmp);
+                WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base);
+                WREG32_MC(RV515_MC_AGP_BASE_2, 0);
+        } else {
+                WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF);
+                WREG32_MC(RV515_MC_AGP_BASE, 0);
+                WREG32_MC(RV515_MC_AGP_BASE_2, 0);
+        }
+        return 0;
+}
+
+void rv515_mc_fini(struct radeon_device *rdev)
+{
+        rv370_pcie_gart_disable(rdev);
+        radeon_gart_table_vram_free(rdev);
+        radeon_gart_fini(rdev);
+}
+
+
+/*
+ * Global GPU functions
+ */
+void rv515_ring_start(struct radeon_device *rdev)
+{
+        unsigned gb_tile_config;
+        int r;
+
+        /* Sub pixel 1/12 so we can have 4K rendering according to doc */
+        gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16;
+        switch (rdev->num_gb_pipes) {
+        case 2:
+                gb_tile_config |= R300_PIPE_COUNT_R300;
+                break;
+        case 3:
+                gb_tile_config |= R300_PIPE_COUNT_R420_3P;
+                break;
+        case 4:
+                gb_tile_config |= R300_PIPE_COUNT_R420;
+                break;
+        case 1:
+        default:
+                gb_tile_config |= R300_PIPE_COUNT_RV350;
+                break;
+        }
+
+        r = radeon_ring_lock(rdev, 64);
+        if (r) {
+                return;
+        }
+        radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
+        radeon_ring_write(rdev,
+                          RADEON_ISYNC_ANY2D_IDLE3D |
+                          RADEON_ISYNC_ANY3D_IDLE2D |
+                          RADEON_ISYNC_WAIT_IDLEGUI |
+                          RADEON_ISYNC_CPSCRATCH_IDLEGUI);
+        radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
+        radeon_ring_write(rdev, gb_tile_config);
+        radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
+        radeon_ring_write(rdev,
+                          RADEON_WAIT_2D_IDLECLEAN |
+                          RADEON_WAIT_3D_IDLECLEAN);
+        radeon_ring_write(rdev, PACKET0(0x170C, 0));
+        radeon_ring_write(rdev, 1 << 31);
+        radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
+        radeon_ring_write(rdev, 0);
+        radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
+        radeon_ring_write(rdev, 0);
+        radeon_ring_write(rdev, PACKET0(0x42C8, 0));
+        radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
+        radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0));
+        radeon_ring_write(rdev, 0);
+        radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
+        radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
+        radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
+        radeon_ring_write(rdev,
+                          RADEON_WAIT_2D_IDLECLEAN |
+                          RADEON_WAIT_3D_IDLECLEAN);
+        radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
+        radeon_ring_write(rdev, 0);
+        radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
+        radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
+        radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
+        radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
+        radeon_ring_write(rdev,
+                          ((6 << R300_MS_X0_SHIFT) |
+                           (6 << R300_MS_Y0_SHIFT) |
+                           (6 << R300_MS_X1_SHIFT) |
+                           (6 << R300_MS_Y1_SHIFT) |
+                           (6 << R300_MS_X2_SHIFT) |
+                           (6 << R300_MS_Y2_SHIFT) |
+                           (6 << R300_MSBD0_Y_SHIFT) |
+                           (6 << R300_MSBD0_X_SHIFT)));
+        radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
+        radeon_ring_write(rdev,
+                          ((6 << R300_MS_X3_SHIFT) |
+                           (6 << R300_MS_Y3_SHIFT) |
+                           (6 << R300_MS_X4_SHIFT) |
+                           (6 << R300_MS_Y4_SHIFT) |
+                           (6 << R300_MS_X5_SHIFT) |
+                           (6 << R300_MS_Y5_SHIFT) |
+                           (6 << R300_MSBD1_SHIFT)));
+        radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
+        radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
+        radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
+        radeon_ring_write(rdev,
+                          R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
+        radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
+        radeon_ring_write(rdev,
+                          R300_GEOMETRY_ROUND_NEAREST |
+                          R300_COLOR_ROUND_NEAREST);
+        radeon_ring_unlock_commit(rdev);
+}
+
+void rv515_errata(struct radeon_device *rdev)
+{
+        rdev->pll_errata = 0;
+}
+
+int rv515_mc_wait_for_idle(struct radeon_device *rdev)
+{
+        unsigned i;
+        uint32_t tmp;
+
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                /* read MC_STATUS */
+                tmp = RREG32_MC(RV515_MC_STATUS);
+                if (tmp & RV515_MC_STATUS_IDLE) {
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        return -1;
+}
+
+void rv515_gpu_init(struct radeon_device *rdev)
+{
+        unsigned pipe_select_current, gb_pipe_select, tmp;
+
+        r100_hdp_reset(rdev);
+        r100_rb2d_reset(rdev);
+
+        if (r100_gui_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait GUI idle while "
+                       "reseting GPU. Bad things might happen.\n");
+        }
+
+        rs600_disable_vga(rdev);
+
+        r420_pipes_init(rdev);
+        gb_pipe_select = RREG32(0x402C);
+        tmp = RREG32(0x170C);
+        pipe_select_current = (tmp >> 2) & 3;
+        tmp = (1 << pipe_select_current) |
+              (((gb_pipe_select >> 8) & 0xF) << 4);
+        WREG32_PLL(0x000D, tmp);
+        if (r100_gui_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait GUI idle while "
+                       "reseting GPU. Bad things might happen.\n");
+        }
+        if (rv515_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+}
+
+int rv515_ga_reset(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+        bool reinit_cp;
+        int i;
+
+        reinit_cp = rdev->cp.ready;
+        rdev->cp.ready = false;
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                WREG32(RADEON_CP_CSQ_MODE, 0);
+                WREG32(RADEON_CP_CSQ_CNTL, 0);
+                WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
+                (void)RREG32(RADEON_RBBM_SOFT_RESET);
+                udelay(200);
+                WREG32(RADEON_RBBM_SOFT_RESET, 0);
+                /* Wait to prevent race in RBBM_STATUS */
+                mdelay(1);
+                tmp = RREG32(RADEON_RBBM_STATUS);
+                if (tmp & ((1 << 20) | (1 << 26))) {
+                        DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
+                        /* GA still busy soft reset it */
+                        WREG32(0x429C, 0x200);
+                        WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+                        WREG32(0x43E0, 0);
+                        WREG32(0x43E4, 0);
+                        WREG32(0x24AC, 0);
+                }
+                /* Wait to prevent race in RBBM_STATUS */
+                mdelay(1);
+                tmp = RREG32(RADEON_RBBM_STATUS);
+                if (!(tmp & ((1 << 20) | (1 << 26)))) {
+                        break;
+                }
+        }
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                tmp = RREG32(RADEON_RBBM_STATUS);
+                if (!(tmp & ((1 << 20) | (1 << 26)))) {
+                        DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
+                                 tmp);
+                        DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
+                        DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
+                        DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
+                        if (reinit_cp) {
+                                return r100_cp_init(rdev, rdev->cp.ring_size);
+                        }
+                        return 0;
+                }
+                DRM_UDELAY(1);
+        }
+        tmp = RREG32(RADEON_RBBM_STATUS);
+        DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
+        return -1;
+}
+
+int rv515_gpu_reset(struct radeon_device *rdev)
+{
+        uint32_t status;
+
+        /* reset order likely matter */
+        status = RREG32(RADEON_RBBM_STATUS);
+        /* reset HDP */
+        r100_hdp_reset(rdev);
+        /* reset rb2d */
+        if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
+                r100_rb2d_reset(rdev);
+        }
+        /* reset GA */
+        if (status & ((1 << 20) | (1 << 26))) {
+                rv515_ga_reset(rdev);
+        }
+        /* reset CP */
+        status = RREG32(RADEON_RBBM_STATUS);
+        if (status & (1 << 16)) {
+                r100_cp_reset(rdev);
+        }
+        /* Check if GPU is idle */
+        status = RREG32(RADEON_RBBM_STATUS);
+        if (status & (1 << 31)) {
+                DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
+                return -1;
+        }
+        DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
+        return 0;
+}
+
+
+/*
+ * VRAM info
+ */
+static void rv515_vram_get_type(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        rdev->mc.vram_width = 128;
+        rdev->mc.vram_is_ddr = true;
+        tmp = RREG32_MC(RV515_MC_CNTL);
+        tmp &= RV515_MEM_NUM_CHANNELS_MASK;
+        switch (tmp) {
+        case 0:
+                rdev->mc.vram_width = 64;
+                break;
+        case 1:
+                rdev->mc.vram_width = 128;
+                break;
+        default:
+                rdev->mc.vram_width = 128;
+                break;
+        }
+}
+
+void rv515_vram_info(struct radeon_device *rdev)
+{
+        rv515_vram_get_type(rdev);
+        rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
+
+        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+}
+
+
+/*
+ * Indirect registers accessor
+ */
+uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        uint32_t r;
+
+        WREG32(R520_MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
+        r = RREG32(R520_MC_IND_DATA);
+        WREG32(R520_MC_IND_INDEX, 0);
+        return r;
+}
+
+void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        WREG32(R520_MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
+        WREG32(R520_MC_IND_DATA, (v));
+        WREG32(R520_MC_IND_INDEX, 0);
+}
+
+uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        uint32_t r;
+
+        WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
+        (void)RREG32(RADEON_PCIE_INDEX);
+        r = RREG32(RADEON_PCIE_DATA);
+        return r;
+}
+
+void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
+        (void)RREG32(RADEON_PCIE_INDEX);
+        WREG32(RADEON_PCIE_DATA, (v));
+        (void)RREG32(RADEON_PCIE_DATA);
+}
+
+
+/*
+ * Debugfs info
+ */
+#if defined(CONFIG_DEBUG_FS)
+static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t tmp;
+
+        tmp = RREG32(R400_GB_PIPE_SELECT);
+        seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
+        tmp = RREG32(R500_SU_REG_DEST);
+        seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
+        tmp = RREG32(R300_GB_TILE_CONFIG);
+        seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
+        tmp = RREG32(R300_DST_PIPE_CONFIG);
+        seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
+        return 0;
+}
+
+static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        struct radeon_device *rdev = dev->dev_private;
+        uint32_t tmp;
+
+        tmp = RREG32(0x2140);
+        seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
+        radeon_gpu_reset(rdev);
+        tmp = RREG32(0x425C);
+        seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
+        return 0;
+}
+
+static struct drm_info_list rv515_pipes_info_list[] = {
+        {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
+};
+
+static struct drm_info_list rv515_ga_info_list[] = {
+        {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
+};
+#endif
+
+int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
+#else
+        return 0;
+#endif
+}
+
+int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
+{
+#if defined(CONFIG_DEBUG_FS)
+        return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
+#else
+        return 0;
+#endif
+}
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
new file mode 100644
index 000000000000..da50cc51ede3
--- /dev/null
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2008 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
+ * Copyright 2009 Jerome Glisse.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Dave Airlie
+ *          Alex Deucher
+ *          Jerome Glisse
+ */
+#include "drmP.h"
+#include "radeon_reg.h"
+#include "radeon.h"
+
+/* rv770,rv730,rv710  depends on : */
+void rs600_mc_disable_clients(struct radeon_device *rdev);
+
+/* This files gather functions specifics to:
+ * rv770,rv730,rv710
+ *
+ * Some of these functions might be used by newer ASICs.
+ */
+int rv770_mc_wait_for_idle(struct radeon_device *rdev);
+void rv770_gpu_init(struct radeon_device *rdev);
+
+
+/*
+ * MC
+ */
+int rv770_mc_init(struct radeon_device *rdev)
+{
+        uint32_t tmp;
+
+        rv770_gpu_init(rdev);
+
+        /* setup the gart before changing location so we can ask to
+         * discard unmapped mc request
+         */
+        /* FIXME: disable out of gart access */
+        tmp = rdev->mc.gtt_location / 4096;
+        tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp);
+        WREG32(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, tmp);
+        tmp = (rdev->mc.gtt_location + rdev->mc.gtt_size) / 4096;
+        tmp = REG_SET(R700_LOGICAL_PAGE_NUMBER, tmp);
+        WREG32(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, tmp);
+
+        rs600_mc_disable_clients(rdev);
+        if (rv770_mc_wait_for_idle(rdev)) {
+                printk(KERN_WARNING "Failed to wait MC idle while "
+                       "programming pipes. Bad things might happen.\n");
+        }
+
+        tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
+        tmp = REG_SET(R700_MC_FB_TOP, tmp >> 24);
+        tmp |= REG_SET(R700_MC_FB_BASE, rdev->mc.vram_location >> 24);
+        WREG32(R700_MC_VM_FB_LOCATION, tmp);
+        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
+        tmp = REG_SET(R700_MC_AGP_TOP, tmp >> 22);
+        WREG32(R700_MC_VM_AGP_TOP, tmp);
+        tmp = REG_SET(R700_MC_AGP_BOT, rdev->mc.gtt_location >> 22);
+        WREG32(R700_MC_VM_AGP_BOT, tmp);
+        return 0;
+}
+
+void rv770_mc_fini(struct radeon_device *rdev)
+{
+        /* FIXME: implement */
+}
+
+
+/*
+ * Global GPU functions
+ */
+void rv770_errata(struct radeon_device *rdev)
+{
+        rdev->pll_errata = 0;
+}
+
+int rv770_mc_wait_for_idle(struct radeon_device *rdev)
+{
+        /* FIXME: implement */
+        return 0;
+}
+
+void rv770_gpu_init(struct radeon_device *rdev)
+{
+        /* FIXME: implement */
+}
+
+
+/*
+ * VRAM info
+ */
+void rv770_vram_get_type(struct radeon_device *rdev)
+{
+        /* FIXME: implement */
+}
+
+void rv770_vram_info(struct radeon_device *rdev)
+{
+        rv770_vram_get_type(rdev);
+
+        /* FIXME: implement */
+        /* Could aper size report 0 ? */
+        rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
+        rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
+}
diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile
new file mode 100644
index 000000000000..b0a9de7a57c2
--- /dev/null
+++ b/drivers/gpu/drm/ttm/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the drm device driver.  This driver provides support for the
+
+ccflags-y := -Iinclude/drm
+ttm-y := ttm_agp_backend.o ttm_memory.o ttm_tt.o ttm_bo.o \
+        ttm_bo_util.o ttm_bo_vm.o ttm_module.o ttm_global.o
+
+obj-$(CONFIG_DRM_TTM) += ttm.o
diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c b/drivers/gpu/drm/ttm/ttm_agp_backend.c
new file mode 100644
index 000000000000..e8f6d2229d8c
--- /dev/null
+++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c
@@ -0,0 +1,150 @@
+/**************************************************************************
+ *
+ * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+/*
+ * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
+ *          Keith Packard.
+ */
+
+#include "ttm/ttm_module.h"
+#include "ttm/ttm_bo_driver.h"
+#ifdef TTM_HAS_AGP
+#include "ttm/ttm_placement.h"
+#include <linux/agp_backend.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <asm/agp.h>
+
+struct ttm_agp_backend {
+        struct ttm_backend backend;
+        struct agp_memory *mem;
+        struct agp_bridge_data *bridge;
+};
+
+static int ttm_agp_populate(struct ttm_backend *backend,
+                            unsigned long num_pages, struct page **pages,
+                            struct page *dummy_read_page)
+{
+        struct ttm_agp_backend *agp_be =
+            container_of(backend, struct ttm_agp_backend, backend);
+        struct page **cur_page, **last_page = pages + num_pages;
+        struct agp_memory *mem;
+
+        mem = agp_allocate_memory(agp_be->bridge, num_pages, AGP_USER_MEMORY);
+        if (unlikely(mem == NULL))
+                return -ENOMEM;
+
+        mem->page_count = 0;
+        for (cur_page = pages; cur_page < last_page; ++cur_page) {
+                struct page *page = *cur_page;
+                if (!page)
+                        page = dummy_read_page;
+
+                mem->memory[mem->page_count++] =
+                    phys_to_gart(page_to_phys(page));
+        }
+        agp_be->mem = mem;
+        return 0;
+}
+
+static int ttm_agp_bind(struct ttm_backend *backend, struct ttm_mem_reg *bo_mem)
+{
+        struct ttm_agp_backend *agp_be =
+            container_of(backend, struct ttm_agp_backend, backend);
+        struct agp_memory *mem = agp_be->mem;
+        int cached = (bo_mem->placement & TTM_PL_FLAG_CACHED);
+        int ret;
+
+        mem->is_flushed = 1;
+        mem->type = (cached) ? AGP_USER_CACHED_MEMORY : AGP_USER_MEMORY;
+
+        ret = agp_bind_memory(mem, bo_mem->mm_node->start);
+        if (ret)
+                printk(KERN_ERR TTM_PFX "AGP Bind memory failed.\n");
+
+        return ret;
+}
+
+static int ttm_agp_unbind(struct ttm_backend *backend)
+{
+        struct ttm_agp_backend *agp_be =
+            container_of(backend, struct ttm_agp_backend, backend);
+
+        if (agp_be->mem->is_bound)
+                return agp_unbind_memory(agp_be->mem);
+        else
+                return 0;
+}
+
+static void ttm_agp_clear(struct ttm_backend *backend)
+{
+        struct ttm_agp_backend *agp_be =
+            container_of(backend, struct ttm_agp_backend, backend);
+        struct agp_memory *mem = agp_be->mem;
+
+        if (mem) {
+                ttm_agp_unbind(backend);
+                agp_free_memory(mem);
+        }
+        agp_be->mem = NULL;
+}
+
+static void ttm_agp_destroy(struct ttm_backend *backend)
+{
+        struct ttm_agp_backend *agp_be =
+            container_of(backend, struct ttm_agp_backend, backend);
+
+        if (agp_be->mem)
+                ttm_agp_clear(backend);
+        kfree(agp_be);
+}
+
+static struct ttm_backend_func ttm_agp_func = {
+        .populate = ttm_agp_populate,
+        .clear = ttm_agp_clear,
+        .bind = ttm_agp_bind,
+        .unbind = ttm_agp_unbind,
+        .destroy = ttm_agp_destroy,
+};
+
+struct ttm_backend *ttm_agp_backend_init(struct ttm_bo_device *bdev,
+                                         struct agp_bridge_data *bridge)
+{
+        struct ttm_agp_backend *agp_be;
+
+        agp_be = kmalloc(sizeof(*agp_be), GFP_KERNEL);
+        if (!agp_be)
+                return NULL;
+
+        agp_be->mem = NULL;
+        agp_be->bridge = bridge;
+        agp_be->backend.func = &ttm_agp_func;
+        agp_be->backend.bdev = bdev;
+        return &agp_be->backend;
+}
+EXPORT_SYMBOL(ttm_agp_backend_init);
+
+#endif
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
new file mode 100644
index 000000000000..1587aeca7bea
--- /dev/null
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -0,0 +1,1698 @@
+/**************************************************************************
+ *
+ * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+/*
+ * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
+ */
+
+#include "ttm/ttm_module.h"
+#include "ttm/ttm_bo_driver.h"
+#include "ttm/ttm_placement.h"
+#include <linux/jiffies.h>
+#include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/file.h>
+#include <linux/module.h>
+
+#define TTM_ASSERT_LOCKED(param)
+#define TTM_DEBUG(fmt, arg...)
+#define TTM_BO_HASH_ORDER 13
+
+static int ttm_bo_setup_vm(struct ttm_buffer_object *bo);
+static void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo);
+static int ttm_bo_swapout(struct ttm_mem_shrink *shrink);
+
+static inline uint32_t ttm_bo_type_flags(unsigned type)
+{
+        return 1 << (type);
+}
+
+static void ttm_bo_release_list(struct kref *list_kref)
+{
+        struct ttm_buffer_object *bo =
+            container_of(list_kref, struct ttm_buffer_object, list_kref);
+        struct ttm_bo_device *bdev = bo->bdev;
+
+        BUG_ON(atomic_read(&bo->list_kref.refcount));
+        BUG_ON(atomic_read(&bo->kref.refcount));
+        BUG_ON(atomic_read(&bo->cpu_writers));
+        BUG_ON(bo->sync_obj != NULL);
+        BUG_ON(bo->mem.mm_node != NULL);
+        BUG_ON(!list_empty(&bo->lru));
+        BUG_ON(!list_empty(&bo->ddestroy));
+
+        if (bo->ttm)
+                ttm_tt_destroy(bo->ttm);
+        if (bo->destroy)
+                bo->destroy(bo);
+        else {
+                ttm_mem_global_free(bdev->mem_glob, bo->acc_size, false);
+                kfree(bo);
+        }
+}
+
+int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo, bool interruptible)
+{
+
+        if (interruptible) {
+                int ret = 0;
+
+                ret = wait_event_interruptible(bo->event_queue,
+                                               atomic_read(&bo->reserved) == 0);
+                if (unlikely(ret != 0))
+                        return -ERESTART;
+        } else {
+                wait_event(bo->event_queue, atomic_read(&bo->reserved) == 0);
+        }
+        return 0;
+}
+
+static void ttm_bo_add_to_lru(struct ttm_buffer_object *bo)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        struct ttm_mem_type_manager *man;
+
+        BUG_ON(!atomic_read(&bo->reserved));
+
+        if (!(bo->mem.placement & TTM_PL_FLAG_NO_EVICT)) {
+
+                BUG_ON(!list_empty(&bo->lru));
+
+                man = &bdev->man[bo->mem.mem_type];
+                list_add_tail(&bo->lru, &man->lru);
+                kref_get(&bo->list_kref);
+
+                if (bo->ttm != NULL) {
+                        list_add_tail(&bo->swap, &bdev->swap_lru);
+                        kref_get(&bo->list_kref);
+                }
+        }
+}
+
+/**
+ * Call with the lru_lock held.
+ */
+
+static int ttm_bo_del_from_lru(struct ttm_buffer_object *bo)
+{
+        int put_count = 0;
+
+        if (!list_empty(&bo->swap)) {
+                list_del_init(&bo->swap);
+                ++put_count;
+        }
+        if (!list_empty(&bo->lru)) {
+                list_del_init(&bo->lru);
+                ++put_count;
+        }
+
+        /*
+         * TODO: Add a driver hook to delete from
+         * driver-specific LRU's here.
+         */
+
+        return put_count;
+}
+
+int ttm_bo_reserve_locked(struct ttm_buffer_object *bo,
+                          bool interruptible,
+                          bool no_wait, bool use_sequence, uint32_t sequence)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        int ret;
+
+        while (unlikely(atomic_cmpxchg(&bo->reserved, 0, 1) != 0)) {
+                if (use_sequence && bo->seq_valid &&
+                        (sequence - bo->val_seq < (1 << 31))) {
+                        return -EAGAIN;
+                }
+
+                if (no_wait)
+                        return -EBUSY;
+
+                spin_unlock(&bdev->lru_lock);
+                ret = ttm_bo_wait_unreserved(bo, interruptible);
+                spin_lock(&bdev->lru_lock);
+
+                if (unlikely(ret))
+                        return ret;
+        }
+
+        if (use_sequence) {
+                bo->val_seq = sequence;
+                bo->seq_valid = true;
+        } else {
+                bo->seq_valid = false;
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL(ttm_bo_reserve);
+
+static void ttm_bo_ref_bug(struct kref *list_kref)
+{
+        BUG();
+}
+
+int ttm_bo_reserve(struct ttm_buffer_object *bo,
+                   bool interruptible,
+                   bool no_wait, bool use_sequence, uint32_t sequence)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        int put_count = 0;
+        int ret;
+
+        spin_lock(&bdev->lru_lock);
+        ret = ttm_bo_reserve_locked(bo, interruptible, no_wait, use_sequence,
+                                    sequence);
+        if (likely(ret == 0))
+                put_count = ttm_bo_del_from_lru(bo);
+        spin_unlock(&bdev->lru_lock);
+
+        while (put_count--)
+                kref_put(&bo->list_kref, ttm_bo_ref_bug);
+
+        return ret;
+}
+
+void ttm_bo_unreserve(struct ttm_buffer_object *bo)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+
+        spin_lock(&bdev->lru_lock);
+        ttm_bo_add_to_lru(bo);
+        atomic_set(&bo->reserved, 0);
+        wake_up_all(&bo->event_queue);
+        spin_unlock(&bdev->lru_lock);
+}
+EXPORT_SYMBOL(ttm_bo_unreserve);
+
+/*
+ * Call bo->mutex locked.
+ */
+
+static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        int ret = 0;
+        uint32_t page_flags = 0;
+
+        TTM_ASSERT_LOCKED(&bo->mutex);
+        bo->ttm = NULL;
+
+        switch (bo->type) {
+        case ttm_bo_type_device:
+                if (zero_alloc)
+                        page_flags |= TTM_PAGE_FLAG_ZERO_ALLOC;
+        case ttm_bo_type_kernel:
+                bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT,
+                                        page_flags, bdev->dummy_read_page);
+                if (unlikely(bo->ttm == NULL))
+                        ret = -ENOMEM;
+                break;
+        case ttm_bo_type_user:
+                bo->ttm = ttm_tt_create(bdev, bo->num_pages << PAGE_SHIFT,
+                                        page_flags | TTM_PAGE_FLAG_USER,
+                                        bdev->dummy_read_page);
+                if (unlikely(bo->ttm == NULL))
+                        ret = -ENOMEM;
+                break;
+
+                ret = ttm_tt_set_user(bo->ttm, current,
+                                      bo->buffer_start, bo->num_pages);
+                if (unlikely(ret != 0))
+                        ttm_tt_destroy(bo->ttm);
+                break;
+        default:
+                printk(KERN_ERR TTM_PFX "Illegal buffer object type\n");
+                ret = -EINVAL;
+                break;
+        }
+
+        return ret;
+}
+
+static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo,
+                                  struct ttm_mem_reg *mem,
+                                  bool evict, bool interruptible, bool no_wait)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        bool old_is_pci = ttm_mem_reg_is_pci(bdev, &bo->mem);
+        bool new_is_pci = ttm_mem_reg_is_pci(bdev, mem);
+        struct ttm_mem_type_manager *old_man = &bdev->man[bo->mem.mem_type];
+        struct ttm_mem_type_manager *new_man = &bdev->man[mem->mem_type];
+        int ret = 0;
+
+        if (old_is_pci || new_is_pci ||
+            ((mem->placement & bo->mem.placement & TTM_PL_MASK_CACHING) == 0))
+                ttm_bo_unmap_virtual(bo);
+
+        /*
+         * Create and bind a ttm if required.
+         */
+
+        if (!(new_man->flags & TTM_MEMTYPE_FLAG_FIXED) && (bo->ttm == NULL)) {
+                ret = ttm_bo_add_ttm(bo, false);
+                if (ret)
+                        goto out_err;
+
+                ret = ttm_tt_set_placement_caching(bo->ttm, mem->placement);
+                if (ret)
+                        return ret;
+
+                if (mem->mem_type != TTM_PL_SYSTEM) {
+                        ret = ttm_tt_bind(bo->ttm, mem);
+                        if (ret)
+                                goto out_err;
+                }
+
+                if (bo->mem.mem_type == TTM_PL_SYSTEM) {
+
+                        struct ttm_mem_reg *old_mem = &bo->mem;
+                        uint32_t save_flags = old_mem->placement;
+
+                        *old_mem = *mem;
+                        mem->mm_node = NULL;
+                        ttm_flag_masked(&save_flags, mem->placement,
+                                        TTM_PL_MASK_MEMTYPE);
+                        goto moved;
+                }
+
+        }
+
+        if (!(old_man->flags & TTM_MEMTYPE_FLAG_FIXED) &&
+            !(new_man->flags & TTM_MEMTYPE_FLAG_FIXED))
+                ret = ttm_bo_move_ttm(bo, evict, no_wait, mem);
+        else if (bdev->driver->move)
+                ret = bdev->driver->move(bo, evict, interruptible,
+                                         no_wait, mem);
+        else
+                ret = ttm_bo_move_memcpy(bo, evict, no_wait, mem);
+
+        if (ret)
+                goto out_err;
+
+moved:
+        if (bo->evicted) {
+                ret = bdev->driver->invalidate_caches(bdev, bo->mem.placement);
+                if (ret)
+                        printk(KERN_ERR TTM_PFX "Can not flush read caches\n");
+                bo->evicted = false;
+        }
+
+        if (bo->mem.mm_node) {
+                spin_lock(&bo->lock);
+                bo->offset = (bo->mem.mm_node->start << PAGE_SHIFT) +
+                    bdev->man[bo->mem.mem_type].gpu_offset;
+                bo->cur_placement = bo->mem.placement;
+                spin_unlock(&bo->lock);
+        }
+
+        return 0;
+
+out_err:
+        new_man = &bdev->man[bo->mem.mem_type];
+        if ((new_man->flags & TTM_MEMTYPE_FLAG_FIXED) && bo->ttm) {
+                ttm_tt_unbind(bo->ttm);
+                ttm_tt_destroy(bo->ttm);
+                bo->ttm = NULL;
+        }
+
+        return ret;
+}
+
+/**
+ * If bo idle, remove from delayed- and lru lists, and unref.
+ * If not idle, and already on delayed list, do nothing.
+ * If not idle, and not on delayed list, put on delayed list,
+ *   up the list_kref and schedule a delayed list check.
+ */
+
+static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool remove_all)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        struct ttm_bo_driver *driver = bdev->driver;
+        int ret;
+
+        spin_lock(&bo->lock);
+        (void) ttm_bo_wait(bo, false, false, !remove_all);
+
+        if (!bo->sync_obj) {
+                int put_count;
+
+                spin_unlock(&bo->lock);
+
+                spin_lock(&bdev->lru_lock);
+                ret = ttm_bo_reserve_locked(bo, false, false, false, 0);
+                BUG_ON(ret);
+                if (bo->ttm)
+                        ttm_tt_unbind(bo->ttm);
+
+                if (!list_empty(&bo->ddestroy)) {
+                        list_del_init(&bo->ddestroy);
+                        kref_put(&bo->list_kref, ttm_bo_ref_bug);
+                }
+                if (bo->mem.mm_node) {
+                        drm_mm_put_block(bo->mem.mm_node);
+                        bo->mem.mm_node = NULL;
+                }
+                put_count = ttm_bo_del_from_lru(bo);
+                spin_unlock(&bdev->lru_lock);
+
+                atomic_set(&bo->reserved, 0);
+
+                while (put_count--)
+                        kref_put(&bo->list_kref, ttm_bo_release_list);
+
+                return 0;
+        }
+
+        spin_lock(&bdev->lru_lock);
+        if (list_empty(&bo->ddestroy)) {
+                void *sync_obj = bo->sync_obj;
+                void *sync_obj_arg = bo->sync_obj_arg;
+
+                kref_get(&bo->list_kref);
+                list_add_tail(&bo->ddestroy, &bdev->ddestroy);
+                spin_unlock(&bdev->lru_lock);
+                spin_unlock(&bo->lock);
+
+                if (sync_obj)
+                        driver->sync_obj_flush(sync_obj, sync_obj_arg);
+                schedule_delayed_work(&bdev->wq,
+                                      ((HZ / 100) < 1) ? 1 : HZ / 100);
+                ret = 0;
+
+        } else {
+                spin_unlock(&bdev->lru_lock);
+                spin_unlock(&bo->lock);
+                ret = -EBUSY;
+        }
+
+        return ret;
+}
+
+/**
+ * Traverse the delayed list, and call ttm_bo_cleanup_refs on all
+ * encountered buffers.
+ */
+
+static int ttm_bo_delayed_delete(struct ttm_bo_device *bdev, bool remove_all)
+{
+        struct ttm_buffer_object *entry, *nentry;
+        struct list_head *list, *next;
+        int ret;
+
+        spin_lock(&bdev->lru_lock);
+        list_for_each_safe(list, next, &bdev->ddestroy) {
+                entry = list_entry(list, struct ttm_buffer_object, ddestroy);
+                nentry = NULL;
+
+                /*
+                 * Protect the next list entry from destruction while we
+                 * unlock the lru_lock.
+                 */
+
+                if (next != &bdev->ddestroy) {
+                        nentry = list_entry(next, struct ttm_buffer_object,
+                                            ddestroy);
+                        kref_get(&nentry->list_kref);
+                }
+                kref_get(&entry->list_kref);
+
+                spin_unlock(&bdev->lru_lock);
+                ret = ttm_bo_cleanup_refs(entry, remove_all);
+                kref_put(&entry->list_kref, ttm_bo_release_list);
+
+                spin_lock(&bdev->lru_lock);
+                if (nentry) {
+                        bool next_onlist = !list_empty(next);
+                        spin_unlock(&bdev->lru_lock);
+                        kref_put(&nentry->list_kref, ttm_bo_release_list);
+                        spin_lock(&bdev->lru_lock);
+                        /*
+                         * Someone might have raced us and removed the
+                         * next entry from the list. We don't bother restarting
+                         * list traversal.
+                         */
+
+                        if (!next_onlist)
+                                break;
+                }
+                if (ret)
+                        break;
+        }
+        ret = !list_empty(&bdev->ddestroy);
+        spin_unlock(&bdev->lru_lock);
+
+        return ret;
+}
+
+static void ttm_bo_delayed_workqueue(struct work_struct *work)
+{
+        struct ttm_bo_device *bdev =
+            container_of(work, struct ttm_bo_device, wq.work);
+
+        if (ttm_bo_delayed_delete(bdev, false)) {
+                schedule_delayed_work(&bdev->wq,
+                                      ((HZ / 100) < 1) ? 1 : HZ / 100);
+        }
+}
+
+static void ttm_bo_release(struct kref *kref)
+{
+        struct ttm_buffer_object *bo =
+            container_of(kref, struct ttm_buffer_object, kref);
+        struct ttm_bo_device *bdev = bo->bdev;
+
+        if (likely(bo->vm_node != NULL)) {
+                rb_erase(&bo->vm_rb, &bdev->addr_space_rb);
+                drm_mm_put_block(bo->vm_node);
+                bo->vm_node = NULL;
+        }
+        write_unlock(&bdev->vm_lock);
+        ttm_bo_cleanup_refs(bo, false);
+        kref_put(&bo->list_kref, ttm_bo_release_list);
+        write_lock(&bdev->vm_lock);
+}
+
+void ttm_bo_unref(struct ttm_buffer_object **p_bo)
+{
+        struct ttm_buffer_object *bo = *p_bo;
+        struct ttm_bo_device *bdev = bo->bdev;
+
+        *p_bo = NULL;
+        write_lock(&bdev->vm_lock);
+        kref_put(&bo->kref, ttm_bo_release);
+        write_unlock(&bdev->vm_lock);
+}
+EXPORT_SYMBOL(ttm_bo_unref);
+
+static int ttm_bo_evict(struct ttm_buffer_object *bo, unsigned mem_type,
+                        bool interruptible, bool no_wait)
+{
+        int ret = 0;
+        struct ttm_bo_device *bdev = bo->bdev;
+        struct ttm_mem_reg evict_mem;
+        uint32_t proposed_placement;
+
+        if (bo->mem.mem_type != mem_type)
+                goto out;
+
+        spin_lock(&bo->lock);
+        ret = ttm_bo_wait(bo, false, interruptible, no_wait);
+        spin_unlock(&bo->lock);
+
+        if (ret && ret != -ERESTART) {
+                printk(KERN_ERR TTM_PFX "Failed to expire sync object before "
+                       "buffer eviction.\n");
+                goto out;
+        }
+
+        BUG_ON(!atomic_read(&bo->reserved));
+
+        evict_mem = bo->mem;
+        evict_mem.mm_node = NULL;
+
+        proposed_placement = bdev->driver->evict_flags(bo);
+
+        ret = ttm_bo_mem_space(bo, proposed_placement,
+                               &evict_mem, interruptible, no_wait);
+        if (unlikely(ret != 0 && ret != -ERESTART))
+                ret = ttm_bo_mem_space(bo, TTM_PL_FLAG_SYSTEM,
+                                       &evict_mem, interruptible, no_wait);
+
+        if (ret) {
+                if (ret != -ERESTART)
+                        printk(KERN_ERR TTM_PFX
+                               "Failed to find memory space for "
+                               "buffer 0x%p eviction.\n", bo);
+                goto out;
+        }
+
+        ret = ttm_bo_handle_move_mem(bo, &evict_mem, true, interruptible,
+                                     no_wait);
+        if (ret) {
+                if (ret != -ERESTART)
+                        printk(KERN_ERR TTM_PFX "Buffer eviction failed\n");
+                goto out;
+        }
+
+        spin_lock(&bdev->lru_lock);
+        if (evict_mem.mm_node) {
+                drm_mm_put_block(evict_mem.mm_node);
+                evict_mem.mm_node = NULL;
+        }
+        spin_unlock(&bdev->lru_lock);
+        bo->evicted = true;
+out:
+        return ret;
+}
+
+/**
+ * Repeatedly evict memory from the LRU for @mem_type until we create enough
+ * space, or we've evicted everything and there isn't enough space.
+ */
+static int ttm_bo_mem_force_space(struct ttm_bo_device *bdev,
+                                  struct ttm_mem_reg *mem,
+                                  uint32_t mem_type,
+                                  bool interruptible, bool no_wait)
+{
+        struct drm_mm_node *node;
+        struct ttm_buffer_object *entry;
+        struct ttm_mem_type_manager *man = &bdev->man[mem_type];
+        struct list_head *lru;
+        unsigned long num_pages = mem->num_pages;
+        int put_count = 0;
+        int ret;
+
+retry_pre_get:
+        ret = drm_mm_pre_get(&man->manager);
+        if (unlikely(ret != 0))
+                return ret;
+
+        spin_lock(&bdev->lru_lock);
+        do {
+                node = drm_mm_search_free(&man->manager, num_pages,
+                                          mem->page_alignment, 1);
+                if (node)
+                        break;
+
+                lru = &man->lru;
+                if (list_empty(lru))
+                        break;
+
+                entry = list_first_entry(lru, struct ttm_buffer_object, lru);
+                kref_get(&entry->list_kref);
+
+                ret =
+                    ttm_bo_reserve_locked(entry, interruptible, no_wait,
+                                          false, 0);
+
+                if (likely(ret == 0))
+                        put_count = ttm_bo_del_from_lru(entry);
+
+                spin_unlock(&bdev->lru_lock);
+
+                if (unlikely(ret != 0))
+                        return ret;
+
+                while (put_count--)
+                        kref_put(&entry->list_kref, ttm_bo_ref_bug);
+
+                ret = ttm_bo_evict(entry, mem_type, interruptible, no_wait);
+
+                ttm_bo_unreserve(entry);
+
+                kref_put(&entry->list_kref, ttm_bo_release_list);
+                if (ret)
+                        return ret;
+
+                spin_lock(&bdev->lru_lock);
+        } while (1);
+
+        if (!node) {
+                spin_unlock(&bdev->lru_lock);
+                return -ENOMEM;
+        }
+
+        node = drm_mm_get_block_atomic(node, num_pages, mem->page_alignment);
+        if (unlikely(!node)) {
+                spin_unlock(&bdev->lru_lock);
+                goto retry_pre_get;
+        }
+
+        spin_unlock(&bdev->lru_lock);
+        mem->mm_node = node;
+        mem->mem_type = mem_type;
+        return 0;
+}
+
+static bool ttm_bo_mt_compatible(struct ttm_mem_type_manager *man,
+                                 bool disallow_fixed,
+                                 uint32_t mem_type,
+                                 uint32_t mask, uint32_t *res_mask)
+{
+        uint32_t cur_flags = ttm_bo_type_flags(mem_type);
+
+        if ((man->flags & TTM_MEMTYPE_FLAG_FIXED) && disallow_fixed)
+                return false;
+
+        if ((cur_flags & mask & TTM_PL_MASK_MEM) == 0)
+                return false;
+
+        if ((mask & man->available_caching) == 0)
+                return false;
+        if (mask & man->default_caching)
+                cur_flags |= man->default_caching;
+        else if (mask & TTM_PL_FLAG_CACHED)
+                cur_flags |= TTM_PL_FLAG_CACHED;
+        else if (mask & TTM_PL_FLAG_WC)
+                cur_flags |= TTM_PL_FLAG_WC;
+        else
+                cur_flags |= TTM_PL_FLAG_UNCACHED;
+
+        *res_mask = cur_flags;
+        return true;
+}
+
+/**
+ * Creates space for memory region @mem according to its type.
+ *
+ * This function first searches for free space in compatible memory types in
+ * the priority order defined by the driver.  If free space isn't found, then
+ * ttm_bo_mem_force_space is attempted in priority order to evict and find
+ * space.
+ */
+int ttm_bo_mem_space(struct ttm_buffer_object *bo,
+                     uint32_t proposed_placement,
+                     struct ttm_mem_reg *mem,
+                     bool interruptible, bool no_wait)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        struct ttm_mem_type_manager *man;
+
+        uint32_t num_prios = bdev->driver->num_mem_type_prio;
+        const uint32_t *prios = bdev->driver->mem_type_prio;
+        uint32_t i;
+        uint32_t mem_type = TTM_PL_SYSTEM;
+        uint32_t cur_flags = 0;
+        bool type_found = false;
+        bool type_ok = false;
+        bool has_eagain = false;
+        struct drm_mm_node *node = NULL;
+        int ret;
+
+        mem->mm_node = NULL;
+        for (i = 0; i < num_prios; ++i) {
+                mem_type = prios[i];
+                man = &bdev->man[mem_type];
+
+                type_ok = ttm_bo_mt_compatible(man,
+                                               bo->type == ttm_bo_type_user,
+                                               mem_type, proposed_placement,
+                                               &cur_flags);
+
+                if (!type_ok)
+                        continue;
+
+                if (mem_type == TTM_PL_SYSTEM)
+                        break;
+
+                if (man->has_type && man->use_type) {
+                        type_found = true;
+                        do {
+                                ret = drm_mm_pre_get(&man->manager);
+                                if (unlikely(ret))
+                                        return ret;
+
+                                spin_lock(&bdev->lru_lock);
+                                node = drm_mm_search_free(&man->manager,
+                                                          mem->num_pages,
+                                                          mem->page_alignment,
+                                                          1);
+                                if (unlikely(!node)) {
+                                        spin_unlock(&bdev->lru_lock);
+                                        break;
+                                }
+                                node = drm_mm_get_block_atomic(node,
+                                                               mem->num_pages,
+                                                               mem->
+                                                               page_alignment);
+                                spin_unlock(&bdev->lru_lock);
+                        } while (!node);
+                }
+                if (node)
+                        break;
+        }
+
+        if ((type_ok && (mem_type == TTM_PL_SYSTEM)) || node) {
+                mem->mm_node = node;
+                mem->mem_type = mem_type;
+                mem->placement = cur_flags;
+                return 0;
+        }
+
+        if (!type_found)
+                return -EINVAL;
+
+        num_prios = bdev->driver->num_mem_busy_prio;
+        prios = bdev->driver->mem_busy_prio;
+
+        for (i = 0; i < num_prios; ++i) {
+                mem_type = prios[i];
+                man = &bdev->man[mem_type];
+
+                if (!man->has_type)
+                        continue;
+
+                if (!ttm_bo_mt_compatible(man,
+                                          bo->type == ttm_bo_type_user,
+                                          mem_type,
+                                          proposed_placement, &cur_flags))
+                        continue;
+
+                ret = ttm_bo_mem_force_space(bdev, mem, mem_type,
+                                             interruptible, no_wait);
+
+                if (ret == 0 && mem->mm_node) {
+                        mem->placement = cur_flags;
+                        return 0;
+                }
+
+                if (ret == -ERESTART)
+                        has_eagain = true;
+        }
+
+        ret = (has_eagain) ? -ERESTART : -ENOMEM;
+        return ret;
+}
+EXPORT_SYMBOL(ttm_bo_mem_space);
+
+int ttm_bo_wait_cpu(struct ttm_buffer_object *bo, bool no_wait)
+{
+        int ret = 0;
+
+        if ((atomic_read(&bo->cpu_writers) > 0) && no_wait)
+                return -EBUSY;
+
+        ret = wait_event_interruptible(bo->event_queue,
+                                       atomic_read(&bo->cpu_writers) == 0);
+
+        if (ret == -ERESTARTSYS)
+                ret = -ERESTART;
+
+        return ret;
+}
+
+int ttm_bo_move_buffer(struct ttm_buffer_object *bo,
+                       uint32_t proposed_placement,
+                       bool interruptible, bool no_wait)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        int ret = 0;
+        struct ttm_mem_reg mem;
+
+        BUG_ON(!atomic_read(&bo->reserved));
+
+        /*
+         * FIXME: It's possible to pipeline buffer moves.
+         * Have the driver move function wait for idle when necessary,
+         * instead of doing it here.
+         */
+
+        spin_lock(&bo->lock);
+        ret = ttm_bo_wait(bo, false, interruptible, no_wait);
+        spin_unlock(&bo->lock);
+
+        if (ret)
+                return ret;
+
+        mem.num_pages = bo->num_pages;
+        mem.size = mem.num_pages << PAGE_SHIFT;
+        mem.page_alignment = bo->mem.page_alignment;
+
+        /*
+         * Determine where to move the buffer.
+         */
+
+        ret = ttm_bo_mem_space(bo, proposed_placement, &mem,
+                               interruptible, no_wait);
+        if (ret)
+                goto out_unlock;
+
+        ret = ttm_bo_handle_move_mem(bo, &mem, false, interruptible, no_wait);
+
+out_unlock:
+        if (ret && mem.mm_node) {
+                spin_lock(&bdev->lru_lock);
+                drm_mm_put_block(mem.mm_node);
+                spin_unlock(&bdev->lru_lock);
+        }
+        return ret;
+}
+
+static int ttm_bo_mem_compat(uint32_t proposed_placement,
+                             struct ttm_mem_reg *mem)
+{
+        if ((proposed_placement & mem->placement & TTM_PL_MASK_MEM) == 0)
+                return 0;
+        if ((proposed_placement & mem->placement & TTM_PL_MASK_CACHING) == 0)
+                return 0;
+
+        return 1;
+}
+
+int ttm_buffer_object_validate(struct ttm_buffer_object *bo,
+                               uint32_t proposed_placement,
+                               bool interruptible, bool no_wait)
+{
+        int ret;
+
+        BUG_ON(!atomic_read(&bo->reserved));
+        bo->proposed_placement = proposed_placement;
+
+        TTM_DEBUG("Proposed placement 0x%08lx, Old flags 0x%08lx\n",
+                  (unsigned long)proposed_placement,
+                  (unsigned long)bo->mem.placement);
+
+        /*
+         * Check whether we need to move buffer.
+         */
+
+        if (!ttm_bo_mem_compat(bo->proposed_placement, &bo->mem)) {
+                ret = ttm_bo_move_buffer(bo, bo->proposed_placement,
+                                         interruptible, no_wait);
+                if (ret) {
+                        if (ret != -ERESTART)
+                                printk(KERN_ERR TTM_PFX
+                                       "Failed moving buffer. "
+                                       "Proposed placement 0x%08x\n",
+                                       bo->proposed_placement);
+                        if (ret == -ENOMEM)
+                                printk(KERN_ERR TTM_PFX
+                                       "Out of aperture space or "
+                                       "DRM memory quota.\n");
+                        return ret;
+                }
+        }
+
+        /*
+         * We might need to add a TTM.
+         */
+
+        if (bo->mem.mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
+                ret = ttm_bo_add_ttm(bo, true);
+                if (ret)
+                        return ret;
+        }
+        /*
+         * Validation has succeeded, move the access and other
+         * non-mapping-related flag bits from the proposed flags to
+         * the active flags
+         */
+
+        ttm_flag_masked(&bo->mem.placement, bo->proposed_placement,
+                        ~TTM_PL_MASK_MEMTYPE);
+
+        return 0;
+}
+EXPORT_SYMBOL(ttm_buffer_object_validate);
+
+int
+ttm_bo_check_placement(struct ttm_buffer_object *bo,
+                       uint32_t set_flags, uint32_t clr_flags)
+{
+        uint32_t new_mask = set_flags | clr_flags;
+
+        if ((bo->type == ttm_bo_type_user) &&
+            (clr_flags & TTM_PL_FLAG_CACHED)) {
+                printk(KERN_ERR TTM_PFX
+                       "User buffers require cache-coherent memory.\n");
+                return -EINVAL;
+        }
+
+        if (!capable(CAP_SYS_ADMIN)) {
+                if (new_mask & TTM_PL_FLAG_NO_EVICT) {
+                        printk(KERN_ERR TTM_PFX "Need to be root to modify"
+                               " NO_EVICT status.\n");
+                        return -EINVAL;
+                }
+
+                if ((clr_flags & bo->mem.placement & TTM_PL_MASK_MEMTYPE) &&
+                    (bo->mem.placement & TTM_PL_FLAG_NO_EVICT)) {
+                        printk(KERN_ERR TTM_PFX
+                               "Incompatible memory specification"
+                               " for NO_EVICT buffer.\n");
+                        return -EINVAL;
+                }
+        }
+        return 0;
+}
+
+int ttm_buffer_object_init(struct ttm_bo_device *bdev,
+                           struct ttm_buffer_object *bo,
+                           unsigned long size,
+                           enum ttm_bo_type type,
+                           uint32_t flags,
+                           uint32_t page_alignment,
+                           unsigned long buffer_start,
+                           bool interruptible,
+                           struct file *persistant_swap_storage,
+                           size_t acc_size,
+                           void (*destroy) (struct ttm_buffer_object *))
+{
+        int ret = 0;
+        unsigned long num_pages;
+
+        size += buffer_start & ~PAGE_MASK;
+        num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
+        if (num_pages == 0) {
+                printk(KERN_ERR TTM_PFX "Illegal buffer object size.\n");
+                return -EINVAL;
+        }
+        bo->destroy = destroy;
+
+        spin_lock_init(&bo->lock);
+        kref_init(&bo->kref);
+        kref_init(&bo->list_kref);
+        atomic_set(&bo->cpu_writers, 0);
+        atomic_set(&bo->reserved, 1);
+        init_waitqueue_head(&bo->event_queue);
+        INIT_LIST_HEAD(&bo->lru);
+        INIT_LIST_HEAD(&bo->ddestroy);
+        INIT_LIST_HEAD(&bo->swap);
+        bo->bdev = bdev;
+        bo->type = type;
+        bo->num_pages = num_pages;
+        bo->mem.mem_type = TTM_PL_SYSTEM;
+        bo->mem.num_pages = bo->num_pages;
+        bo->mem.mm_node = NULL;
+        bo->mem.page_alignment = page_alignment;
+        bo->buffer_start = buffer_start & PAGE_MASK;
+        bo->priv_flags = 0;
+        bo->mem.placement = (TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED);
+        bo->seq_valid = false;
+        bo->persistant_swap_storage = persistant_swap_storage;
+        bo->acc_size = acc_size;
+
+        ret = ttm_bo_check_placement(bo, flags, 0ULL);
+        if (unlikely(ret != 0))
+                goto out_err;
+
+        /*
+         * If no caching attributes are set, accept any form of caching.
+         */
+
+        if ((flags & TTM_PL_MASK_CACHING) == 0)
+                flags |= TTM_PL_MASK_CACHING;
+
+        /*
+         * For ttm_bo_type_device buffers, allocate
+         * address space from the device.
+         */
+
+        if (bo->type == ttm_bo_type_device) {
+                ret = ttm_bo_setup_vm(bo);
+                if (ret)
+                        goto out_err;
+        }
+
+        ret = ttm_buffer_object_validate(bo, flags, interruptible, false);
+        if (ret)
+                goto out_err;
+
+        ttm_bo_unreserve(bo);
+        return 0;
+
+out_err:
+        ttm_bo_unreserve(bo);
+        ttm_bo_unref(&bo);
+
+        return ret;
+}
+EXPORT_SYMBOL(ttm_buffer_object_init);
+
+static inline size_t ttm_bo_size(struct ttm_bo_device *bdev,
+                                 unsigned long num_pages)
+{
+        size_t page_array_size = (num_pages * sizeof(void *) + PAGE_SIZE - 1) &
+            PAGE_MASK;
+
+        return bdev->ttm_bo_size + 2 * page_array_size;
+}
+
+int ttm_buffer_object_create(struct ttm_bo_device *bdev,
+                             unsigned long size,
+                             enum ttm_bo_type type,
+                             uint32_t flags,
+                             uint32_t page_alignment,
+                             unsigned long buffer_start,
+                             bool interruptible,
+                             struct file *persistant_swap_storage,
+                             struct ttm_buffer_object **p_bo)
+{
+        struct ttm_buffer_object *bo;
+        int ret;
+        struct ttm_mem_global *mem_glob = bdev->mem_glob;
+
+        size_t acc_size =
+            ttm_bo_size(bdev, (size + PAGE_SIZE - 1) >> PAGE_SHIFT);
+        ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false, false);
+        if (unlikely(ret != 0))
+                return ret;
+
+        bo = kzalloc(sizeof(*bo), GFP_KERNEL);
+
+        if (unlikely(bo == NULL)) {
+                ttm_mem_global_free(mem_glob, acc_size, false);
+                return -ENOMEM;
+        }
+
+        ret = ttm_buffer_object_init(bdev, bo, size, type, flags,
+                                     page_alignment, buffer_start,
+                                     interruptible,
+                                     persistant_swap_storage, acc_size, NULL);
+        if (likely(ret == 0))
+                *p_bo = bo;
+
+        return ret;
+}
+
+static int ttm_bo_leave_list(struct ttm_buffer_object *bo,
+                             uint32_t mem_type, bool allow_errors)
+{
+        int ret;
+
+        spin_lock(&bo->lock);
+        ret = ttm_bo_wait(bo, false, false, false);
+        spin_unlock(&bo->lock);
+
+        if (ret && allow_errors)
+                goto out;
+
+        if (bo->mem.mem_type == mem_type)
+                ret = ttm_bo_evict(bo, mem_type, false, false);
+
+        if (ret) {
+                if (allow_errors) {
+                        goto out;
+                } else {
+                        ret = 0;
+                        printk(KERN_ERR TTM_PFX "Cleanup eviction failed\n");
+                }
+        }
+
+out:
+        return ret;
+}
+
+static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev,
+                                   struct list_head *head,
+                                   unsigned mem_type, bool allow_errors)
+{
+        struct ttm_buffer_object *entry;
+        int ret;
+        int put_count;
+
+        /*
+         * Can't use standard list traversal since we're unlocking.
+         */
+
+        spin_lock(&bdev->lru_lock);
+
+        while (!list_empty(head)) {
+                entry = list_first_entry(head, struct ttm_buffer_object, lru);
+                kref_get(&entry->list_kref);
+                ret = ttm_bo_reserve_locked(entry, false, false, false, 0);
+                put_count = ttm_bo_del_from_lru(entry);
+                spin_unlock(&bdev->lru_lock);
+                while (put_count--)
+                        kref_put(&entry->list_kref, ttm_bo_ref_bug);
+                BUG_ON(ret);
+                ret = ttm_bo_leave_list(entry, mem_type, allow_errors);
+                ttm_bo_unreserve(entry);
+                kref_put(&entry->list_kref, ttm_bo_release_list);
+                spin_lock(&bdev->lru_lock);
+        }
+
+        spin_unlock(&bdev->lru_lock);
+
+        return 0;
+}
+
+int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type)
+{
+        struct ttm_mem_type_manager *man = &bdev->man[mem_type];
+        int ret = -EINVAL;
+
+        if (mem_type >= TTM_NUM_MEM_TYPES) {
+                printk(KERN_ERR TTM_PFX "Illegal memory type %d\n", mem_type);
+                return ret;
+        }
+
+        if (!man->has_type) {
+                printk(KERN_ERR TTM_PFX "Trying to take down uninitialized "
+                       "memory manager type %u\n", mem_type);
+                return ret;
+        }
+
+        man->use_type = false;
+        man->has_type = false;
+
+        ret = 0;
+        if (mem_type > 0) {
+                ttm_bo_force_list_clean(bdev, &man->lru, mem_type, false);
+
+                spin_lock(&bdev->lru_lock);
+                if (drm_mm_clean(&man->manager))
+                        drm_mm_takedown(&man->manager);
+                else
+                        ret = -EBUSY;
+
+                spin_unlock(&bdev->lru_lock);
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(ttm_bo_clean_mm);
+
+int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type)
+{
+        struct ttm_mem_type_manager *man = &bdev->man[mem_type];
+
+        if (mem_type == 0 || mem_type >= TTM_NUM_MEM_TYPES) {
+                printk(KERN_ERR TTM_PFX
+                       "Illegal memory manager memory type %u.\n",
+                       mem_type);
+                return -EINVAL;
+        }
+
+        if (!man->has_type) {
+                printk(KERN_ERR TTM_PFX
+                       "Memory type %u has not been initialized.\n",
+                       mem_type);
+                return 0;
+        }
+
+        return ttm_bo_force_list_clean(bdev, &man->lru, mem_type, true);
+}
+EXPORT_SYMBOL(ttm_bo_evict_mm);
+
+int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type,
+                   unsigned long p_offset, unsigned long p_size)
+{
+        int ret = -EINVAL;
+        struct ttm_mem_type_manager *man;
+
+        if (type >= TTM_NUM_MEM_TYPES) {
+                printk(KERN_ERR TTM_PFX "Illegal memory type %d\n", type);
+                return ret;
+        }
+
+        man = &bdev->man[type];
+        if (man->has_type) {
+                printk(KERN_ERR TTM_PFX
+                       "Memory manager already initialized for type %d\n",
+                       type);
+                return ret;
+        }
+
+        ret = bdev->driver->init_mem_type(bdev, type, man);
+        if (ret)
+                return ret;
+
+        ret = 0;
+        if (type != TTM_PL_SYSTEM) {
+                if (!p_size) {
+                        printk(KERN_ERR TTM_PFX
+                               "Zero size memory manager type %d\n",
+                               type);
+                        return ret;
+                }
+                ret = drm_mm_init(&man->manager, p_offset, p_size);
+                if (ret)
+                        return ret;
+        }
+        man->has_type = true;
+        man->use_type = true;
+        man->size = p_size;
+
+        INIT_LIST_HEAD(&man->lru);
+
+        return 0;
+}
+EXPORT_SYMBOL(ttm_bo_init_mm);
+
+int ttm_bo_device_release(struct ttm_bo_device *bdev)
+{
+        int ret = 0;
+        unsigned i = TTM_NUM_MEM_TYPES;
+        struct ttm_mem_type_manager *man;
+
+        while (i--) {
+                man = &bdev->man[i];
+                if (man->has_type) {
+                        man->use_type = false;
+                        if ((i != TTM_PL_SYSTEM) && ttm_bo_clean_mm(bdev, i)) {
+                                ret = -EBUSY;
+                                printk(KERN_ERR TTM_PFX
+                                       "DRM memory manager type %d "
+                                       "is not clean.\n", i);
+                        }
+                        man->has_type = false;
+                }
+        }
+
+        if (!cancel_delayed_work(&bdev->wq))
+                flush_scheduled_work();
+
+        while (ttm_bo_delayed_delete(bdev, true))
+                ;
+
+        spin_lock(&bdev->lru_lock);
+        if (list_empty(&bdev->ddestroy))
+                TTM_DEBUG("Delayed destroy list was clean\n");
+
+        if (list_empty(&bdev->man[0].lru))
+                TTM_DEBUG("Swap list was clean\n");
+        spin_unlock(&bdev->lru_lock);
+
+        ttm_mem_unregister_shrink(bdev->mem_glob, &bdev->shrink);
+        BUG_ON(!drm_mm_clean(&bdev->addr_space_mm));
+        write_lock(&bdev->vm_lock);
+        drm_mm_takedown(&bdev->addr_space_mm);
+        write_unlock(&bdev->vm_lock);
+
+        __free_page(bdev->dummy_read_page);
+        return ret;
+}
+EXPORT_SYMBOL(ttm_bo_device_release);
+
+/*
+ * This function is intended to be called on drm driver load.
+ * If you decide to call it from firstopen, you must protect the call
+ * from a potentially racing ttm_bo_driver_finish in lastclose.
+ * (This may happen on X server restart).
+ */
+
+int ttm_bo_device_init(struct ttm_bo_device *bdev,
+                       struct ttm_mem_global *mem_glob,
+                       struct ttm_bo_driver *driver, uint64_t file_page_offset)
+{
+        int ret = -EINVAL;
+
+        bdev->dummy_read_page = NULL;
+        rwlock_init(&bdev->vm_lock);
+        spin_lock_init(&bdev->lru_lock);
+
+        bdev->driver = driver;
+        bdev->mem_glob = mem_glob;
+
+        memset(bdev->man, 0, sizeof(bdev->man));
+
+        bdev->dummy_read_page = alloc_page(__GFP_ZERO | GFP_DMA32);
+        if (unlikely(bdev->dummy_read_page == NULL)) {
+                ret = -ENOMEM;
+                goto out_err0;
+        }
+
+        /*
+         * Initialize the system memory buffer type.
+         * Other types need to be driver / IOCTL initialized.
+         */
+        ret = ttm_bo_init_mm(bdev, TTM_PL_SYSTEM, 0, 0);
+        if (unlikely(ret != 0))
+                goto out_err1;
+
+        bdev->addr_space_rb = RB_ROOT;
+        ret = drm_mm_init(&bdev->addr_space_mm, file_page_offset, 0x10000000);
+        if (unlikely(ret != 0))
+                goto out_err2;
+
+        INIT_DELAYED_WORK(&bdev->wq, ttm_bo_delayed_workqueue);
+        bdev->nice_mode = true;
+        INIT_LIST_HEAD(&bdev->ddestroy);
+        INIT_LIST_HEAD(&bdev->swap_lru);
+        bdev->dev_mapping = NULL;
+        ttm_mem_init_shrink(&bdev->shrink, ttm_bo_swapout);
+        ret = ttm_mem_register_shrink(mem_glob, &bdev->shrink);
+        if (unlikely(ret != 0)) {
+                printk(KERN_ERR TTM_PFX
+                       "Could not register buffer object swapout.\n");
+                goto out_err2;
+        }
+
+        bdev->ttm_bo_extra_size =
+                ttm_round_pot(sizeof(struct ttm_tt)) +
+                ttm_round_pot(sizeof(struct ttm_backend));
+
+        bdev->ttm_bo_size = bdev->ttm_bo_extra_size +
+                ttm_round_pot(sizeof(struct ttm_buffer_object));
+
+        return 0;
+out_err2:
+        ttm_bo_clean_mm(bdev, 0);
+out_err1:
+        __free_page(bdev->dummy_read_page);
+out_err0:
+        return ret;
+}
+EXPORT_SYMBOL(ttm_bo_device_init);
+
+/*
+ * buffer object vm functions.
+ */
+
+bool ttm_mem_reg_is_pci(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
+{
+        struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
+
+        if (!(man->flags & TTM_MEMTYPE_FLAG_FIXED)) {
+                if (mem->mem_type == TTM_PL_SYSTEM)
+                        return false;
+
+                if (man->flags & TTM_MEMTYPE_FLAG_CMA)
+                        return false;
+
+                if (mem->placement & TTM_PL_FLAG_CACHED)
+                        return false;
+        }
+        return true;
+}
+
+int ttm_bo_pci_offset(struct ttm_bo_device *bdev,
+                      struct ttm_mem_reg *mem,
+                      unsigned long *bus_base,
+                      unsigned long *bus_offset, unsigned long *bus_size)
+{
+        struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
+
+        *bus_size = 0;
+        if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
+                return -EINVAL;
+
+        if (ttm_mem_reg_is_pci(bdev, mem)) {
+                *bus_offset = mem->mm_node->start << PAGE_SHIFT;
+                *bus_size = mem->num_pages << PAGE_SHIFT;
+                *bus_base = man->io_offset;
+        }
+
+        return 0;
+}
+
+void ttm_bo_unmap_virtual(struct ttm_buffer_object *bo)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        loff_t offset = (loff_t) bo->addr_space_offset;
+        loff_t holelen = ((loff_t) bo->mem.num_pages) << PAGE_SHIFT;
+
+        if (!bdev->dev_mapping)
+                return;
+
+        unmap_mapping_range(bdev->dev_mapping, offset, holelen, 1);
+}
+
+static void ttm_bo_vm_insert_rb(struct ttm_buffer_object *bo)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        struct rb_node **cur = &bdev->addr_space_rb.rb_node;
+        struct rb_node *parent = NULL;
+        struct ttm_buffer_object *cur_bo;
+        unsigned long offset = bo->vm_node->start;
+        unsigned long cur_offset;
+
+        while (*cur) {
+                parent = *cur;
+                cur_bo = rb_entry(parent, struct ttm_buffer_object, vm_rb);
+                cur_offset = cur_bo->vm_node->start;
+                if (offset < cur_offset)
+                        cur = &parent->rb_left;
+                else if (offset > cur_offset)
+                        cur = &parent->rb_right;
+                else
+                        BUG();
+        }
+
+        rb_link_node(&bo->vm_rb, parent, cur);
+        rb_insert_color(&bo->vm_rb, &bdev->addr_space_rb);
+}
+
+/**
+ * ttm_bo_setup_vm:
+ *
+ * @bo: the buffer to allocate address space for
+ *
+ * Allocate address space in the drm device so that applications
+ * can mmap the buffer and access the contents. This only
+ * applies to ttm_bo_type_device objects as others are not
+ * placed in the drm device address space.
+ */
+
+static int ttm_bo_setup_vm(struct ttm_buffer_object *bo)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        int ret;
+
+retry_pre_get:
+        ret = drm_mm_pre_get(&bdev->addr_space_mm);
+        if (unlikely(ret != 0))
+                return ret;
+
+        write_lock(&bdev->vm_lock);
+        bo->vm_node = drm_mm_search_free(&bdev->addr_space_mm,
+                                         bo->mem.num_pages, 0, 0);
+
+        if (unlikely(bo->vm_node == NULL)) {
+                ret = -ENOMEM;
+                goto out_unlock;
+        }
+
+        bo->vm_node = drm_mm_get_block_atomic(bo->vm_node,
+                                              bo->mem.num_pages, 0);
+
+        if (unlikely(bo->vm_node == NULL)) {
+                write_unlock(&bdev->vm_lock);
+                goto retry_pre_get;
+        }
+
+        ttm_bo_vm_insert_rb(bo);
+        write_unlock(&bdev->vm_lock);
+        bo->addr_space_offset = ((uint64_t) bo->vm_node->start) << PAGE_SHIFT;
+
+        return 0;
+out_unlock:
+        write_unlock(&bdev->vm_lock);
+        return ret;
+}
+
+int ttm_bo_wait(struct ttm_buffer_object *bo,
+                bool lazy, bool interruptible, bool no_wait)
+{
+        struct ttm_bo_driver *driver = bo->bdev->driver;
+        void *sync_obj;
+        void *sync_obj_arg;
+        int ret = 0;
+
+        if (likely(bo->sync_obj == NULL))
+                return 0;
+
+        while (bo->sync_obj) {
+
+                if (driver->sync_obj_signaled(bo->sync_obj, bo->sync_obj_arg)) {
+                        void *tmp_obj = bo->sync_obj;
+                        bo->sync_obj = NULL;
+                        clear_bit(TTM_BO_PRIV_FLAG_MOVING, &bo->priv_flags);
+                        spin_unlock(&bo->lock);
+                        driver->sync_obj_unref(&tmp_obj);
+                        spin_lock(&bo->lock);
+                        continue;
+                }
+
+                if (no_wait)
+                        return -EBUSY;
+
+                sync_obj = driver->sync_obj_ref(bo->sync_obj);
+                sync_obj_arg = bo->sync_obj_arg;
+                spin_unlock(&bo->lock);
+                ret = driver->sync_obj_wait(sync_obj, sync_obj_arg,
+                                            lazy, interruptible);
+                if (unlikely(ret != 0)) {
+                        driver->sync_obj_unref(&sync_obj);
+                        spin_lock(&bo->lock);
+                        return ret;
+                }
+                spin_lock(&bo->lock);
+                if (likely(bo->sync_obj == sync_obj &&
+                           bo->sync_obj_arg == sync_obj_arg)) {
+                        void *tmp_obj = bo->sync_obj;
+                        bo->sync_obj = NULL;
+                        clear_bit(TTM_BO_PRIV_FLAG_MOVING,
+                                  &bo->priv_flags);
+                        spin_unlock(&bo->lock);
+                        driver->sync_obj_unref(&sync_obj);
+                        driver->sync_obj_unref(&tmp_obj);
+                        spin_lock(&bo->lock);
+                }
+        }
+        return 0;
+}
+EXPORT_SYMBOL(ttm_bo_wait);
+
+void ttm_bo_unblock_reservation(struct ttm_buffer_object *bo)
+{
+        atomic_set(&bo->reserved, 0);
+        wake_up_all(&bo->event_queue);
+}
+
+int ttm_bo_block_reservation(struct ttm_buffer_object *bo, bool interruptible,
+                             bool no_wait)
+{
+        int ret;
+
+        while (unlikely(atomic_cmpxchg(&bo->reserved, 0, 1) != 0)) {
+                if (no_wait)
+                        return -EBUSY;
+                else if (interruptible) {
+                        ret = wait_event_interruptible
+                            (bo->event_queue, atomic_read(&bo->reserved) == 0);
+                        if (unlikely(ret != 0))
+                                return -ERESTART;
+                } else {
+                        wait_event(bo->event_queue,
+                                   atomic_read(&bo->reserved) == 0);
+                }
+        }
+        return 0;
+}
+
+int ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait)
+{
+        int ret = 0;
+
+        /*
+         * Using ttm_bo_reserve instead of ttm_bo_block_reservation
+         * makes sure the lru lists are updated.
+         */
+
+        ret = ttm_bo_reserve(bo, true, no_wait, false, 0);
+        if (unlikely(ret != 0))
+                return ret;
+        spin_lock(&bo->lock);
+        ret = ttm_bo_wait(bo, false, true, no_wait);
+        spin_unlock(&bo->lock);
+        if (likely(ret == 0))
+                atomic_inc(&bo->cpu_writers);
+        ttm_bo_unreserve(bo);
+        return ret;
+}
+
+void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo)
+{
+        if (atomic_dec_and_test(&bo->cpu_writers))
+                wake_up_all(&bo->event_queue);
+}
+
+/**
+ * A buffer object shrink method that tries to swap out the first
+ * buffer object on the bo_global::swap_lru list.
+ */
+
+static int ttm_bo_swapout(struct ttm_mem_shrink *shrink)
+{
+        struct ttm_bo_device *bdev =
+            container_of(shrink, struct ttm_bo_device, shrink);
+        struct ttm_buffer_object *bo;
+        int ret = -EBUSY;
+        int put_count;
+        uint32_t swap_placement = (TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM);
+
+        spin_lock(&bdev->lru_lock);
+        while (ret == -EBUSY) {
+                if (unlikely(list_empty(&bdev->swap_lru))) {
+                        spin_unlock(&bdev->lru_lock);
+                        return -EBUSY;
+                }
+
+                bo = list_first_entry(&bdev->swap_lru,
+                                      struct ttm_buffer_object, swap);
+                kref_get(&bo->list_kref);
+
+                /**
+                 * Reserve buffer. Since we unlock while sleeping, we need
+                 * to re-check that nobody removed us from the swap-list while
+                 * we slept.
+                 */
+
+                ret = ttm_bo_reserve_locked(bo, false, true, false, 0);
+                if (unlikely(ret == -EBUSY)) {
+                        spin_unlock(&bdev->lru_lock);
+                        ttm_bo_wait_unreserved(bo, false);
+                        kref_put(&bo->list_kref, ttm_bo_release_list);
+                        spin_lock(&bdev->lru_lock);
+                }
+        }
+
+        BUG_ON(ret != 0);
+        put_count = ttm_bo_del_from_lru(bo);
+        spin_unlock(&bdev->lru_lock);
+
+        while (put_count--)
+                kref_put(&bo->list_kref, ttm_bo_ref_bug);
+
+        /**
+         * Wait for GPU, then move to system cached.
+         */
+
+        spin_lock(&bo->lock);
+        ret = ttm_bo_wait(bo, false, false, false);
+        spin_unlock(&bo->lock);
+
+        if (unlikely(ret != 0))
+                goto out;
+
+        if ((bo->mem.placement & swap_placement) != swap_placement) {
+                struct ttm_mem_reg evict_mem;
+
+                evict_mem = bo->mem;
+                evict_mem.mm_node = NULL;
+                evict_mem.placement = TTM_PL_FLAG_SYSTEM | TTM_PL_FLAG_CACHED;
+                evict_mem.mem_type = TTM_PL_SYSTEM;
+
+                ret = ttm_bo_handle_move_mem(bo, &evict_mem, true,
+                                             false, false);
+                if (unlikely(ret != 0))
+                        goto out;
+        }
+
+        ttm_bo_unmap_virtual(bo);
+
+        /**
+         * Swap out. Buffer will be swapped in again as soon as
+         * anyone tries to access a ttm page.
+         */
+
+        ret = ttm_tt_swapout(bo->ttm, bo->persistant_swap_storage);
+out:
+
+        /**
+         *
+         * Unreserve without putting on LRU to avoid swapping out an
+         * already swapped buffer.
+         */
+
+        atomic_set(&bo->reserved, 0);
+        wake_up_all(&bo->event_queue);
+        kref_put(&bo->list_kref, ttm_bo_release_list);
+        return ret;
+}
+
+void ttm_bo_swapout_all(struct ttm_bo_device *bdev)
+{
+        while (ttm_bo_swapout(&bdev->shrink) == 0)
+                ;
+}
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
new file mode 100644
index 000000000000..517c84559633
--- /dev/null
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -0,0 +1,561 @@
+/**************************************************************************
+ *
+ * Copyright (c) 2007-2009 VMware, Inc., Palo Alto, CA., USA
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+/*
+ * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
+ */
+
+#include "ttm/ttm_bo_driver.h"
+#include "ttm/ttm_placement.h"
+#include <linux/io.h>
+#include <linux/highmem.h>
+#include <linux/wait.h>
+#include <linux/vmalloc.h>
+#include <linux/version.h>
+#include <linux/module.h>
+
+void ttm_bo_free_old_node(struct ttm_buffer_object *bo)
+{
+        struct ttm_mem_reg *old_mem = &bo->mem;
+
+        if (old_mem->mm_node) {
+                spin_lock(&bo->bdev->lru_lock);
+                drm_mm_put_block(old_mem->mm_node);
+                spin_unlock(&bo->bdev->lru_lock);
+        }
+        old_mem->mm_node = NULL;
+}
+
+int ttm_bo_move_ttm(struct ttm_buffer_object *bo,
+                    bool evict, bool no_wait, struct ttm_mem_reg *new_mem)
+{
+        struct ttm_tt *ttm = bo->ttm;
+        struct ttm_mem_reg *old_mem = &bo->mem;
+        uint32_t save_flags = old_mem->placement;
+        int ret;
+
+        if (old_mem->mem_type != TTM_PL_SYSTEM) {
+                ttm_tt_unbind(ttm);
+                ttm_bo_free_old_node(bo);
+                ttm_flag_masked(&old_mem->placement, TTM_PL_FLAG_SYSTEM,
+                                TTM_PL_MASK_MEM);
+                old_mem->mem_type = TTM_PL_SYSTEM;
+                save_flags = old_mem->placement;
+        }
+
+        ret = ttm_tt_set_placement_caching(ttm, new_mem->placement);
+        if (unlikely(ret != 0))
+                return ret;
+
+        if (new_mem->mem_type != TTM_PL_SYSTEM) {
+                ret = ttm_tt_bind(ttm, new_mem);
+                if (unlikely(ret != 0))
+                        return ret;
+        }
+
+        *old_mem = *new_mem;
+        new_mem->mm_node = NULL;
+        ttm_flag_masked(&save_flags, new_mem->placement, TTM_PL_MASK_MEMTYPE);
+        return 0;
+}
+EXPORT_SYMBOL(ttm_bo_move_ttm);
+
+int ttm_mem_reg_ioremap(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem,
+                        void **virtual)
+{
+        struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
+        unsigned long bus_offset;
+        unsigned long bus_size;
+        unsigned long bus_base;
+        int ret;
+        void *addr;
+
+        *virtual = NULL;
+        ret = ttm_bo_pci_offset(bdev, mem, &bus_base, &bus_offset, &bus_size);
+        if (ret || bus_size == 0)
+                return ret;
+
+        if (!(man->flags & TTM_MEMTYPE_FLAG_NEEDS_IOREMAP))
+                addr = (void *)(((u8 *) man->io_addr) + bus_offset);
+        else {
+                if (mem->placement & TTM_PL_FLAG_WC)
+                        addr = ioremap_wc(bus_base + bus_offset, bus_size);
+                else
+                        addr = ioremap_nocache(bus_base + bus_offset, bus_size);
+                if (!addr)
+                        return -ENOMEM;
+        }
+        *virtual = addr;
+        return 0;
+}
+
+void ttm_mem_reg_iounmap(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem,
+                         void *virtual)
+{
+        struct ttm_mem_type_manager *man;
+
+        man = &bdev->man[mem->mem_type];
+
+        if (virtual && (man->flags & TTM_MEMTYPE_FLAG_NEEDS_IOREMAP))
+                iounmap(virtual);
+}
+
+static int ttm_copy_io_page(void *dst, void *src, unsigned long page)
+{
+        uint32_t *dstP =
+            (uint32_t *) ((unsigned long)dst + (page << PAGE_SHIFT));
+        uint32_t *srcP =
+            (uint32_t *) ((unsigned long)src + (page << PAGE_SHIFT));
+
+        int i;
+        for (i = 0; i < PAGE_SIZE / sizeof(uint32_t); ++i)
+                iowrite32(ioread32(srcP++), dstP++);
+        return 0;
+}
+
+static int ttm_copy_io_ttm_page(struct ttm_tt *ttm, void *src,
+                                unsigned long page)
+{
+        struct page *d = ttm_tt_get_page(ttm, page);
+        void *dst;
+
+        if (!d)
+                return -ENOMEM;
+
+        src = (void *)((unsigned long)src + (page << PAGE_SHIFT));
+        dst = kmap(d);
+        if (!dst)
+                return -ENOMEM;
+
+        memcpy_fromio(dst, src, PAGE_SIZE);
+        kunmap(d);
+        return 0;
+}
+
+static int ttm_copy_ttm_io_page(struct ttm_tt *ttm, void *dst,
+                                unsigned long page)
+{
+        struct page *s = ttm_tt_get_page(ttm, page);
+        void *src;
+
+        if (!s)
+                return -ENOMEM;
+
+        dst = (void *)((unsigned long)dst + (page << PAGE_SHIFT));
+        src = kmap(s);
+        if (!src)
+                return -ENOMEM;
+
+        memcpy_toio(dst, src, PAGE_SIZE);
+        kunmap(s);
+        return 0;
+}
+
+int ttm_bo_move_memcpy(struct ttm_buffer_object *bo,
+                       bool evict, bool no_wait, struct ttm_mem_reg *new_mem)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        struct ttm_mem_type_manager *man = &bdev->man[new_mem->mem_type];
+        struct ttm_tt *ttm = bo->ttm;
+        struct ttm_mem_reg *old_mem = &bo->mem;
+        struct ttm_mem_reg old_copy = *old_mem;
+        void *old_iomap;
+        void *new_iomap;
+        int ret;
+        uint32_t save_flags = old_mem->placement;
+        unsigned long i;
+        unsigned long page;
+        unsigned long add = 0;
+        int dir;
+
+        ret = ttm_mem_reg_ioremap(bdev, old_mem, &old_iomap);
+        if (ret)
+                return ret;
+        ret = ttm_mem_reg_ioremap(bdev, new_mem, &new_iomap);
+        if (ret)
+                goto out;
+
+        if (old_iomap == NULL && new_iomap == NULL)
+                goto out2;
+        if (old_iomap == NULL && ttm == NULL)
+                goto out2;
+
+        add = 0;
+        dir = 1;
+
+        if ((old_mem->mem_type == new_mem->mem_type) &&
+            (new_mem->mm_node->start <
+             old_mem->mm_node->start + old_mem->mm_node->size)) {
+                dir = -1;
+                add = new_mem->num_pages - 1;
+        }
+
+        for (i = 0; i < new_mem->num_pages; ++i) {
+                page = i * dir + add;
+                if (old_iomap == NULL)
+                        ret = ttm_copy_ttm_io_page(ttm, new_iomap, page);
+                else if (new_iomap == NULL)
+                        ret = ttm_copy_io_ttm_page(ttm, old_iomap, page);
+                else
+                        ret = ttm_copy_io_page(new_iomap, old_iomap, page);
+                if (ret)
+                        goto out1;
+        }
+        mb();
+out2:
+        ttm_bo_free_old_node(bo);
+
+        *old_mem = *new_mem;
+        new_mem->mm_node = NULL;
+        ttm_flag_masked(&save_flags, new_mem->placement, TTM_PL_MASK_MEMTYPE);
+
+        if ((man->flags & TTM_MEMTYPE_FLAG_FIXED) && (ttm != NULL)) {
+                ttm_tt_unbind(ttm);
+                ttm_tt_destroy(ttm);
+                bo->ttm = NULL;
+        }
+
+out1:
+        ttm_mem_reg_iounmap(bdev, new_mem, new_iomap);
+out:
+        ttm_mem_reg_iounmap(bdev, &old_copy, old_iomap);
+        return ret;
+}
+EXPORT_SYMBOL(ttm_bo_move_memcpy);
+
+static void ttm_transfered_destroy(struct ttm_buffer_object *bo)
+{
+        kfree(bo);
+}
+
+/**
+ * ttm_buffer_object_transfer
+ *
+ * @bo: A pointer to a struct ttm_buffer_object.
+ * @new_obj: A pointer to a pointer to a newly created ttm_buffer_object,
+ * holding the data of @bo with the old placement.
+ *
+ * This is a utility function that may be called after an accelerated move
+ * has been scheduled. A new buffer object is created as a placeholder for
+ * the old data while it's being copied. When that buffer object is idle,
+ * it can be destroyed, releasing the space of the old placement.
+ * Returns:
+ * !0: Failure.
+ */
+
+static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo,
+                                      struct ttm_buffer_object **new_obj)
+{
+        struct ttm_buffer_object *fbo;
+        struct ttm_bo_device *bdev = bo->bdev;
+        struct ttm_bo_driver *driver = bdev->driver;
+
+        fbo = kzalloc(sizeof(*fbo), GFP_KERNEL);
+        if (!fbo)
+                return -ENOMEM;
+
+        *fbo = *bo;
+
+        /**
+         * Fix up members that we shouldn't copy directly:
+         * TODO: Explicit member copy would probably be better here.
+         */
+
+        spin_lock_init(&fbo->lock);
+        init_waitqueue_head(&fbo->event_queue);
+        INIT_LIST_HEAD(&fbo->ddestroy);
+        INIT_LIST_HEAD(&fbo->lru);
+        INIT_LIST_HEAD(&fbo->swap);
+        fbo->vm_node = NULL;
+
+        fbo->sync_obj = driver->sync_obj_ref(bo->sync_obj);
+        if (fbo->mem.mm_node)
+                fbo->mem.mm_node->private = (void *)fbo;
+        kref_init(&fbo->list_kref);
+        kref_init(&fbo->kref);
+        fbo->destroy = &ttm_transfered_destroy;
+
+        *new_obj = fbo;
+        return 0;
+}
+
+pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp)
+{
+#if defined(__i386__) || defined(__x86_64__)
+        if (caching_flags & TTM_PL_FLAG_WC)
+                tmp = pgprot_writecombine(tmp);
+        else if (boot_cpu_data.x86 > 3)
+                tmp = pgprot_noncached(tmp);
+
+#elif defined(__powerpc__)
+        if (!(caching_flags & TTM_PL_FLAG_CACHED)) {
+                pgprot_val(tmp) |= _PAGE_NO_CACHE;
+                if (caching_flags & TTM_PL_FLAG_UNCACHED)
+                        pgprot_val(tmp) |= _PAGE_GUARDED;
+        }
+#endif
+#if defined(__ia64__)
+        if (caching_flags & TTM_PL_FLAG_WC)
+                tmp = pgprot_writecombine(tmp);
+        else
+                tmp = pgprot_noncached(tmp);
+#endif
+#if defined(__sparc__)
+        if (!(caching_flags & TTM_PL_FLAG_CACHED))
+                tmp = pgprot_noncached(tmp);
+#endif
+        return tmp;
+}
+
+static int ttm_bo_ioremap(struct ttm_buffer_object *bo,
+                          unsigned long bus_base,
+                          unsigned long bus_offset,
+                          unsigned long bus_size,
+                          struct ttm_bo_kmap_obj *map)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        struct ttm_mem_reg *mem = &bo->mem;
+        struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
+
+        if (!(man->flags & TTM_MEMTYPE_FLAG_NEEDS_IOREMAP)) {
+                map->bo_kmap_type = ttm_bo_map_premapped;
+                map->virtual = (void *)(((u8 *) man->io_addr) + bus_offset);
+        } else {
+                map->bo_kmap_type = ttm_bo_map_iomap;
+                if (mem->placement & TTM_PL_FLAG_WC)
+                        map->virtual = ioremap_wc(bus_base + bus_offset,
+                                                  bus_size);
+                else
+                        map->virtual = ioremap_nocache(bus_base + bus_offset,
+                                                       bus_size);
+        }
+        return (!map->virtual) ? -ENOMEM : 0;
+}
+
+static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo,
+                           unsigned long start_page,
+                           unsigned long num_pages,
+                           struct ttm_bo_kmap_obj *map)
+{
+        struct ttm_mem_reg *mem = &bo->mem; pgprot_t prot;
+        struct ttm_tt *ttm = bo->ttm;
+        struct page *d;
+        int i;
+
+        BUG_ON(!ttm);
+        if (num_pages == 1 && (mem->placement & TTM_PL_FLAG_CACHED)) {
+                /*
+                 * We're mapping a single page, and the desired
+                 * page protection is consistent with the bo.
+                 */
+
+                map->bo_kmap_type = ttm_bo_map_kmap;
+                map->page = ttm_tt_get_page(ttm, start_page);
+                map->virtual = kmap(map->page);
+        } else {
+            /*
+             * Populate the part we're mapping;
+             */
+                for (i = start_page; i < start_page + num_pages; ++i) {
+                        d = ttm_tt_get_page(ttm, i);
+                        if (!d)
+                                return -ENOMEM;
+                }
+
+                /*
+                 * We need to use vmap to get the desired page protection
+                 * or to make the buffer object look contigous.
+                 */
+                prot = (mem->placement & TTM_PL_FLAG_CACHED) ?
+                        PAGE_KERNEL :
+                        ttm_io_prot(mem->placement, PAGE_KERNEL);
+                map->bo_kmap_type = ttm_bo_map_vmap;
+                map->virtual = vmap(ttm->pages + start_page, num_pages,
+                                    0, prot);
+        }
+        return (!map->virtual) ? -ENOMEM : 0;
+}
+
+int ttm_bo_kmap(struct ttm_buffer_object *bo,
+                unsigned long start_page, unsigned long num_pages,
+                struct ttm_bo_kmap_obj *map)
+{
+        int ret;
+        unsigned long bus_base;
+        unsigned long bus_offset;
+        unsigned long bus_size;
+
+        BUG_ON(!list_empty(&bo->swap));
+        map->virtual = NULL;
+        if (num_pages > bo->num_pages)
+                return -EINVAL;
+        if (start_page > bo->num_pages)
+                return -EINVAL;
+#if 0
+        if (num_pages > 1 && !DRM_SUSER(DRM_CURPROC))
+                return -EPERM;
+#endif
+        ret = ttm_bo_pci_offset(bo->bdev, &bo->mem, &bus_base,
+                                &bus_offset, &bus_size);
+        if (ret)
+                return ret;
+        if (bus_size == 0) {
+                return ttm_bo_kmap_ttm(bo, start_page, num_pages, map);
+        } else {
+                bus_offset += start_page << PAGE_SHIFT;
+                bus_size = num_pages << PAGE_SHIFT;
+                return ttm_bo_ioremap(bo, bus_base, bus_offset, bus_size, map);
+        }
+}
+EXPORT_SYMBOL(ttm_bo_kmap);
+
+void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map)
+{
+        if (!map->virtual)
+                return;
+        switch (map->bo_kmap_type) {
+        case ttm_bo_map_iomap:
+                iounmap(map->virtual);
+                break;
+        case ttm_bo_map_vmap:
+                vunmap(map->virtual);
+                break;
+        case ttm_bo_map_kmap:
+                kunmap(map->page);
+                break;
+        case ttm_bo_map_premapped:
+                break;
+        default:
+                BUG();
+        }
+        map->virtual = NULL;
+        map->page = NULL;
+}
+EXPORT_SYMBOL(ttm_bo_kunmap);
+
+int ttm_bo_pfn_prot(struct ttm_buffer_object *bo,
+                    unsigned long dst_offset,
+                    unsigned long *pfn, pgprot_t *prot)
+{
+        struct ttm_mem_reg *mem = &bo->mem;
+        struct ttm_bo_device *bdev = bo->bdev;
+        unsigned long bus_offset;
+        unsigned long bus_size;
+        unsigned long bus_base;
+        int ret;
+        ret = ttm_bo_pci_offset(bdev, mem, &bus_base, &bus_offset,
+                        &bus_size);
+        if (ret)
+                return -EINVAL;
+        if (bus_size != 0)
+                *pfn = (bus_base + bus_offset + dst_offset) >> PAGE_SHIFT;
+        else
+                if (!bo->ttm)
+                        return -EINVAL;
+                else
+                        *pfn = page_to_pfn(ttm_tt_get_page(bo->ttm,
+                                                           dst_offset >>
+                                                           PAGE_SHIFT));
+        *prot = (mem->placement & TTM_PL_FLAG_CACHED) ?
+                PAGE_KERNEL : ttm_io_prot(mem->placement, PAGE_KERNEL);
+
+        return 0;
+}
+
+int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
+                              void *sync_obj,
+                              void *sync_obj_arg,
+                              bool evict, bool no_wait,
+                              struct ttm_mem_reg *new_mem)
+{
+        struct ttm_bo_device *bdev = bo->bdev;
+        struct ttm_bo_driver *driver = bdev->driver;
+        struct ttm_mem_type_manager *man = &bdev->man[new_mem->mem_type];
+        struct ttm_mem_reg *old_mem = &bo->mem;
+        int ret;
+        uint32_t save_flags = old_mem->placement;
+        struct ttm_buffer_object *ghost_obj;
+        void *tmp_obj = NULL;
+
+        spin_lock(&bo->lock);
+        if (bo->sync_obj) {
+                tmp_obj = bo->sync_obj;
+                bo->sync_obj = NULL;
+        }
+        bo->sync_obj = driver->sync_obj_ref(sync_obj);
+        bo->sync_obj_arg = sync_obj_arg;
+        if (evict) {
+                ret = ttm_bo_wait(bo, false, false, false);
+                spin_unlock(&bo->lock);
+                driver->sync_obj_unref(&bo->sync_obj);
+
+                if (ret)
+                        return ret;
+
+                ttm_bo_free_old_node(bo);
+                if ((man->flags & TTM_MEMTYPE_FLAG_FIXED) &&
+                    (bo->ttm != NULL)) {
+                        ttm_tt_unbind(bo->ttm);
+                        ttm_tt_destroy(bo->ttm);
+                        bo->ttm = NULL;
+                }
+        } else {
+                /**
+                 * This should help pipeline ordinary buffer moves.
+                 *
+                 * Hang old buffer memory on a new buffer object,
+                 * and leave it to be released when the GPU
+                 * operation has completed.
+                 */
+
+                set_bit(TTM_BO_PRIV_FLAG_MOVING, &bo->priv_flags);
+                spin_unlock(&bo->lock);
+
+                ret = ttm_buffer_object_transfer(bo, &ghost_obj);
+                if (ret)
+                        return ret;
+
+                /**
+                 * If we're not moving to fixed memory, the TTM object
+                 * needs to stay alive. Otherwhise hang it on the ghost
+                 * bo to be unbound and destroyed.
+                 */
+
+                if (!(man->flags & TTM_MEMTYPE_FLAG_FIXED))
+                        ghost_obj->ttm = NULL;
+                else
+                        bo->ttm = NULL;
+
+                ttm_bo_unreserve(ghost_obj);
+                ttm_bo_unref(&ghost_obj);
+        }
+
+        *old_mem = *new_mem;
+        new_mem->mm_node = NULL;
+        ttm_flag_masked(&save_flags, new_mem->placement, TTM_PL_MASK_MEMTYPE);
+        return 0;
+}
+EXPORT_SYMBOL(ttm_bo_move_accel_cleanup);
diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c
new file mode 100644
index 000000000000..27b146c54fbc
--- /dev/null
+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c
@@ -0,0 +1,454 @@
+/**************************************************************************
+ *
+ * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+/*
+ * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
+ */
+
+#include <ttm/ttm_module.h>
+#include <ttm/ttm_bo_driver.h>
+#include <ttm/ttm_placement.h>
+#include <linux/mm.h>
+#include <linux/version.h>
+#include <linux/rbtree.h>
+#include <linux/module.h>
+#include <linux/uaccess.h>
+
+#define TTM_BO_VM_NUM_PREFAULT 16
+
+static struct ttm_buffer_object *ttm_bo_vm_lookup_rb(struct ttm_bo_device *bdev,
+                                                     unsigned long page_start,
+                                                     unsigned long num_pages)
+{
+        struct rb_node *cur = bdev->addr_space_rb.rb_node;
+        unsigned long cur_offset;
+        struct ttm_buffer_object *bo;
+        struct ttm_buffer_object *best_bo = NULL;
+
+        while (likely(cur != NULL)) {
+                bo = rb_entry(cur, struct ttm_buffer_object, vm_rb);
+                cur_offset = bo->vm_node->start;
+                if (page_start >= cur_offset) {
+                        cur = cur->rb_right;
+                        best_bo = bo;
+                        if (page_start == cur_offset)
+                                break;
+                } else
+                        cur = cur->rb_left;
+        }
+
+        if (unlikely(best_bo == NULL))
+                return NULL;
+
+        if (unlikely((best_bo->vm_node->start + best_bo->num_pages) <
+                     (page_start + num_pages)))
+                return NULL;
+
+        return best_bo;
+}
+
+static int ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+{
+        struct ttm_buffer_object *bo = (struct ttm_buffer_object *)
+            vma->vm_private_data;
+        struct ttm_bo_device *bdev = bo->bdev;
+        unsigned long bus_base;
+        unsigned long bus_offset;
+        unsigned long bus_size;
+        unsigned long page_offset;
+        unsigned long page_last;
+        unsigned long pfn;
+        struct ttm_tt *ttm = NULL;
+        struct page *page;
+        int ret;
+        int i;
+        bool is_iomem;
+        unsigned long address = (unsigned long)vmf->virtual_address;
+        int retval = VM_FAULT_NOPAGE;
+
+        /*
+         * Work around locking order reversal in fault / nopfn
+         * between mmap_sem and bo_reserve: Perform a trylock operation
+         * for reserve, and if it fails, retry the fault after scheduling.
+         */
+
+        ret = ttm_bo_reserve(bo, true, true, false, 0);
+        if (unlikely(ret != 0)) {
+                if (ret == -EBUSY)
+                        set_need_resched();
+                return VM_FAULT_NOPAGE;
+        }
+
+        /*
+         * Wait for buffer data in transit, due to a pipelined
+         * move.
+         */
+
+        spin_lock(&bo->lock);
+        if (test_bit(TTM_BO_PRIV_FLAG_MOVING, &bo->priv_flags)) {
+                ret = ttm_bo_wait(bo, false, true, false);
+                spin_unlock(&bo->lock);
+                if (unlikely(ret != 0)) {
+                        retval = (ret != -ERESTART) ?
+                            VM_FAULT_SIGBUS : VM_FAULT_NOPAGE;
+                        goto out_unlock;
+                }
+        } else
+                spin_unlock(&bo->lock);
+
+
+        ret = ttm_bo_pci_offset(bdev, &bo->mem, &bus_base, &bus_offset,
+                                &bus_size);
+        if (unlikely(ret != 0)) {
+                retval = VM_FAULT_SIGBUS;
+                goto out_unlock;
+        }
+
+        is_iomem = (bus_size != 0);
+
+        page_offset = ((address - vma->vm_start) >> PAGE_SHIFT) +
+            bo->vm_node->start - vma->vm_pgoff;
+        page_last = ((vma->vm_end - vma->vm_start) >> PAGE_SHIFT) +
+            bo->vm_node->start - vma->vm_pgoff;
+
+        if (unlikely(page_offset >= bo->num_pages)) {
+                retval = VM_FAULT_SIGBUS;
+                goto out_unlock;
+        }
+
+        /*
+         * Strictly, we're not allowed to modify vma->vm_page_prot here,
+         * since the mmap_sem is only held in read mode. However, we
+         * modify only the caching bits of vma->vm_page_prot and
+         * consider those bits protected by
+         * the bo->mutex, as we should be the only writers.
+         * There shouldn't really be any readers of these bits except
+         * within vm_insert_mixed()? fork?
+         *
+         * TODO: Add a list of vmas to the bo, and change the
+         * vma->vm_page_prot when the object changes caching policy, with
+         * the correct locks held.
+         */
+
+        if (is_iomem) {
+                vma->vm_page_prot = ttm_io_prot(bo->mem.placement,
+                                                vma->vm_page_prot);
+        } else {
+                ttm = bo->ttm;
+                vma->vm_page_prot = (bo->mem.placement & TTM_PL_FLAG_CACHED) ?
+                    vm_get_page_prot(vma->vm_flags) :
+                    ttm_io_prot(bo->mem.placement, vma->vm_page_prot);
+        }
+
+        /*
+         * Speculatively prefault a number of pages. Only error on
+         * first page.
+         */
+
+        for (i = 0; i < TTM_BO_VM_NUM_PREFAULT; ++i) {
+
+                if (is_iomem)
+                        pfn = ((bus_base + bus_offset) >> PAGE_SHIFT) +
+                            page_offset;
+                else {
+                        page = ttm_tt_get_page(ttm, page_offset);
+                        if (unlikely(!page && i == 0)) {
+                                retval = VM_FAULT_OOM;
+                                goto out_unlock;
+                        } else if (unlikely(!page)) {
+                                break;
+                        }
+                        pfn = page_to_pfn(page);
+                }
+
+                ret = vm_insert_mixed(vma, address, pfn);
+                /*
+                 * Somebody beat us to this PTE or prefaulting to
+                 * an already populated PTE, or prefaulting error.
+                 */
+
+                if (unlikely((ret == -EBUSY) || (ret != 0 && i > 0)))
+                        break;
+                else if (unlikely(ret != 0)) {
+                        retval =
+                            (ret == -ENOMEM) ? VM_FAULT_OOM : VM_FAULT_SIGBUS;
+                        goto out_unlock;
+
+                }
+
+                address += PAGE_SIZE;
+                if (unlikely(++page_offset >= page_last))
+                        break;
+        }
+
+out_unlock:
+        ttm_bo_unreserve(bo);
+        return retval;
+}
+
+static void ttm_bo_vm_open(struct vm_area_struct *vma)
+{
+        struct ttm_buffer_object *bo =
+            (struct ttm_buffer_object *)vma->vm_private_data;
+
+        (void)ttm_bo_reference(bo);
+}
+
+static void ttm_bo_vm_close(struct vm_area_struct *vma)
+{
+        struct ttm_buffer_object *bo =
+            (struct ttm_buffer_object *)vma->vm_private_data;
+
+        ttm_bo_unref(&bo);
+        vma->vm_private_data = NULL;
+}
+
+static struct vm_operations_struct ttm_bo_vm_ops = {
+        .fault = ttm_bo_vm_fault,
+        .open = ttm_bo_vm_open,
+        .close = ttm_bo_vm_close
+};
+
+int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma,
+                struct ttm_bo_device *bdev)
+{
+        struct ttm_bo_driver *driver;
+        struct ttm_buffer_object *bo;
+        int ret;
+
+        read_lock(&bdev->vm_lock);
+        bo = ttm_bo_vm_lookup_rb(bdev, vma->vm_pgoff,
+                                 (vma->vm_end - vma->vm_start) >> PAGE_SHIFT);
+        if (likely(bo != NULL))
+                ttm_bo_reference(bo);
+        read_unlock(&bdev->vm_lock);
+
+        if (unlikely(bo == NULL)) {
+                printk(KERN_ERR TTM_PFX
+                       "Could not find buffer object to map.\n");
+                return -EINVAL;
+        }
+
+        driver = bo->bdev->driver;
+        if (unlikely(!driver->verify_access)) {
+                ret = -EPERM;
+                goto out_unref;
+        }
+        ret = driver->verify_access(bo, filp);
+        if (unlikely(ret != 0))
+                goto out_unref;
+
+        vma->vm_ops = &ttm_bo_vm_ops;
+
+        /*
+         * Note: We're transferring the bo reference to
+         * vma->vm_private_data here.
+         */
+
+        vma->vm_private_data = bo;
+        vma->vm_flags |= VM_RESERVED | VM_IO | VM_MIXEDMAP | VM_DONTEXPAND;
+        return 0;
+out_unref:
+        ttm_bo_unref(&bo);
+        return ret;
+}
+EXPORT_SYMBOL(ttm_bo_mmap);
+
+int ttm_fbdev_mmap(struct vm_area_struct *vma, struct ttm_buffer_object *bo)
+{
+        if (vma->vm_pgoff != 0)
+                return -EACCES;
+
+        vma->vm_ops = &ttm_bo_vm_ops;
+        vma->vm_private_data = ttm_bo_reference(bo);
+        vma->vm_flags |= VM_RESERVED | VM_IO | VM_MIXEDMAP | VM_DONTEXPAND;
+        return 0;
+}
+EXPORT_SYMBOL(ttm_fbdev_mmap);
+
+
+ssize_t ttm_bo_io(struct ttm_bo_device *bdev, struct file *filp,
+                  const char __user *wbuf, char __user *rbuf, size_t count,
+                  loff_t *f_pos, bool write)
+{
+        struct ttm_buffer_object *bo;
+        struct ttm_bo_driver *driver;
+        struct ttm_bo_kmap_obj map;
+        unsigned long dev_offset = (*f_pos >> PAGE_SHIFT);
+        unsigned long kmap_offset;
+        unsigned long kmap_end;
+        unsigned long kmap_num;
+        size_t io_size;
+        unsigned int page_offset;
+        char *virtual;
+        int ret;
+        bool no_wait = false;
+        bool dummy;
+
+        read_lock(&bdev->vm_lock);
+        bo = ttm_bo_vm_lookup_rb(bdev, dev_offset, 1);
+        if (likely(bo != NULL))
+                ttm_bo_reference(bo);
+        read_unlock(&bdev->vm_lock);
+
+        if (unlikely(bo == NULL))
+                return -EFAULT;
+
+        driver = bo->bdev->driver;
+        if (unlikely(driver->verify_access)) {
+                ret = -EPERM;
+                goto out_unref;
+        }
+
+        ret = driver->verify_access(bo, filp);
+        if (unlikely(ret != 0))
+                goto out_unref;
+
+        kmap_offset = dev_offset - bo->vm_node->start;
+        if (unlikely(kmap_offset) >= bo->num_pages) {
+                ret = -EFBIG;
+                goto out_unref;
+        }
+
+        page_offset = *f_pos & ~PAGE_MASK;
+        io_size = bo->num_pages - kmap_offset;
+        io_size = (io_size << PAGE_SHIFT) - page_offset;
+        if (count < io_size)
+                io_size = count;
+
+        kmap_end = (*f_pos + count - 1) >> PAGE_SHIFT;
+        kmap_num = kmap_end - kmap_offset + 1;
+
+        ret = ttm_bo_reserve(bo, true, no_wait, false, 0);
+
+        switch (ret) {
+        case 0:
+                break;
+        case -ERESTART:
+                ret = -EINTR;
+                goto out_unref;
+        case -EBUSY:
+                ret = -EAGAIN;
+                goto out_unref;
+        default:
+                goto out_unref;
+        }
+
+        ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
+        if (unlikely(ret != 0)) {
+                ttm_bo_unreserve(bo);
+                goto out_unref;
+        }
+
+        virtual = ttm_kmap_obj_virtual(&map, &dummy);
+        virtual += page_offset;
+
+        if (write)
+                ret = copy_from_user(virtual, wbuf, io_size);
+        else
+                ret = copy_to_user(rbuf, virtual, io_size);
+
+        ttm_bo_kunmap(&map);
+        ttm_bo_unreserve(bo);
+        ttm_bo_unref(&bo);
+
+        if (unlikely(ret != 0))
+                return -EFBIG;
+
+        *f_pos += io_size;
+
+        return io_size;
+out_unref:
+        ttm_bo_unref(&bo);
+        return ret;
+}
+
+ssize_t ttm_bo_fbdev_io(struct ttm_buffer_object *bo, const char __user *wbuf,
+                        char __user *rbuf, size_t count, loff_t *f_pos,
+                        bool write)
+{
+        struct ttm_bo_kmap_obj map;
+        unsigned long kmap_offset;
+        unsigned long kmap_end;
+        unsigned long kmap_num;
+        size_t io_size;
+        unsigned int page_offset;
+        char *virtual;
+        int ret;
+        bool no_wait = false;
+        bool dummy;
+
+        kmap_offset = (*f_pos >> PAGE_SHIFT);
+        if (unlikely(kmap_offset) >= bo->num_pages)
+                return -EFBIG;
+
+        page_offset = *f_pos & ~PAGE_MASK;
+        io_size = bo->num_pages - kmap_offset;
+        io_size = (io_size << PAGE_SHIFT) - page_offset;
+        if (count < io_size)
+                io_size = count;
+
+        kmap_end = (*f_pos + count - 1) >> PAGE_SHIFT;
+        kmap_num = kmap_end - kmap_offset + 1;
+
+        ret = ttm_bo_reserve(bo, true, no_wait, false, 0);
+
+        switch (ret) {
+        case 0:
+                break;
+        case -ERESTART:
+                return -EINTR;
+        case -EBUSY:
+                return -EAGAIN;
+        default:
+                return ret;
+        }
+
+        ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
+        if (unlikely(ret != 0)) {
+                ttm_bo_unreserve(bo);
+                return ret;
+        }
+
+        virtual = ttm_kmap_obj_virtual(&map, &dummy);
+        virtual += page_offset;
+
+        if (write)
+                ret = copy_from_user(virtual, wbuf, io_size);
+        else
+                ret = copy_to_user(rbuf, virtual, io_size);
+
+        ttm_bo_kunmap(&map);
+        ttm_bo_unreserve(bo);
+        ttm_bo_unref(&bo);
+
+        if (unlikely(ret != 0))
+                return ret;
+
+        *f_pos += io_size;
+
+        return io_size;
+}
diff --git a/drivers/gpu/drm/ttm/ttm_global.c b/drivers/gpu/drm/ttm/ttm_global.c
new file mode 100644
index 000000000000..0b14eb1972b8
--- /dev/null
+++ b/drivers/gpu/drm/ttm/ttm_global.c
@@ -0,0 +1,114 @@
+/**************************************************************************
+ *
+ * Copyright 2008-2009 VMware, Inc., Palo Alto, CA., USA
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+/*
+ * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
+ */
+
+#include "ttm/ttm_module.h"
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+
+struct ttm_global_item {
+        struct mutex mutex;
+        void *object;
+        int refcount;
+};
+
+static struct ttm_global_item glob[TTM_GLOBAL_NUM];
+
+void ttm_global_init(void)
+{
+        int i;
+
+        for (i = 0; i < TTM_GLOBAL_NUM; ++i) {
+                struct ttm_global_item *item = &glob[i];
+                mutex_init(&item->mutex);
+                item->object = NULL;
+                item->refcount = 0;
+        }
+}
+
+void ttm_global_release(void)
+{
+        int i;
+        for (i = 0; i < TTM_GLOBAL_NUM; ++i) {
+                struct ttm_global_item *item = &glob[i];
+                BUG_ON(item->object != NULL);
+                BUG_ON(item->refcount != 0);
+        }
+}
+
+int ttm_global_item_ref(struct ttm_global_reference *ref)
+{
+        int ret;
+        struct ttm_global_item *item = &glob[ref->global_type];
+        void *object;
+
+        mutex_lock(&item->mutex);
+        if (item->refcount == 0) {
+                item->object = kmalloc(ref->size, GFP_KERNEL);
+                if (unlikely(item->object == NULL)) {
+                        ret = -ENOMEM;
+                        goto out_err;
+                }
+
+                ref->object = item->object;
+                ret = ref->init(ref);
+                if (unlikely(ret != 0))
+                        goto out_err;
+
+                ++item->refcount;
+        }
+        ref->object = item->object;
+        object = item->object;
+        mutex_unlock(&item->mutex);
+        return 0;
+out_err:
+        kfree(item->object);
+        mutex_unlock(&item->mutex);
+        item->object = NULL;
+        return ret;
+}
+EXPORT_SYMBOL(ttm_global_item_ref);
+
+void ttm_global_item_unref(struct ttm_global_reference *ref)
+{
+        struct ttm_global_item *item = &glob[ref->global_type];
+
+        mutex_lock(&item->mutex);
+        BUG_ON(item->refcount == 0);
+        BUG_ON(ref->object != item->object);
+        if (--item->refcount == 0) {
+                ref->release(ref);
+                kfree(item->object);
+                item->object = NULL;
+        }
+        mutex_unlock(&item->mutex);
+}
+EXPORT_SYMBOL(ttm_global_item_unref);
+
diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c
new file mode 100644
index 000000000000..87323d4ff68d
--- /dev/null
+++ b/drivers/gpu/drm/ttm/ttm_memory.c
@@ -0,0 +1,234 @@
+/**************************************************************************
+ *
+ * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+#include "ttm/ttm_memory.h"
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+
+#define TTM_PFX "[TTM] "
+#define TTM_MEMORY_ALLOC_RETRIES 4
+
+/**
+ * At this point we only support a single shrink callback.
+ * Extend this if needed, perhaps using a linked list of callbacks.
+ * Note that this function is reentrant:
+ * many threads may try to swap out at any given time.
+ */
+
+static void ttm_shrink(struct ttm_mem_global *glob, bool from_workqueue,
+                       uint64_t extra)
+{
+        int ret;
+        struct ttm_mem_shrink *shrink;
+        uint64_t target;
+        uint64_t total_target;
+
+        spin_lock(&glob->lock);
+        if (glob->shrink == NULL)
+                goto out;
+
+        if (from_workqueue) {
+                target = glob->swap_limit;
+                total_target = glob->total_memory_swap_limit;
+        } else if (capable(CAP_SYS_ADMIN)) {
+                total_target = glob->emer_total_memory;
+                target = glob->emer_memory;
+        } else {
+                total_target = glob->max_total_memory;
+                target = glob->max_memory;
+        }
+
+        total_target = (extra >= total_target) ? 0 : total_target - extra;
+        target = (extra >= target) ? 0 : target - extra;
+
+        while (glob->used_memory > target ||
+               glob->used_total_memory > total_target) {
+                shrink = glob->shrink;
+                spin_unlock(&glob->lock);
+                ret = shrink->do_shrink(shrink);
+                spin_lock(&glob->lock);
+                if (unlikely(ret != 0))
+                        goto out;
+        }
+out:
+        spin_unlock(&glob->lock);
+}
+
+static void ttm_shrink_work(struct work_struct *work)
+{
+        struct ttm_mem_global *glob =
+            container_of(work, struct ttm_mem_global, work);
+
+        ttm_shrink(glob, true, 0ULL);
+}
+
+int ttm_mem_global_init(struct ttm_mem_global *glob)
+{
+        struct sysinfo si;
+        uint64_t mem;
+
+        spin_lock_init(&glob->lock);
+        glob->swap_queue = create_singlethread_workqueue("ttm_swap");
+        INIT_WORK(&glob->work, ttm_shrink_work);
+        init_waitqueue_head(&glob->queue);
+
+        si_meminfo(&si);
+
+        mem = si.totalram - si.totalhigh;
+        mem *= si.mem_unit;
+
+        glob->max_memory = mem >> 1;
+        glob->emer_memory = (mem >> 1) + (mem >> 2);
+        glob->swap_limit = glob->max_memory - (mem >> 3);
+        glob->used_memory = 0;
+        glob->used_total_memory = 0;
+        glob->shrink = NULL;
+
+        mem = si.totalram;
+        mem *= si.mem_unit;
+
+        glob->max_total_memory = mem >> 1;
+        glob->emer_total_memory = (mem >> 1) + (mem >> 2);
+
+        glob->total_memory_swap_limit = glob->max_total_memory - (mem >> 3);
+
+        printk(KERN_INFO TTM_PFX "TTM available graphics memory: %llu MiB\n",
+               glob->max_total_memory >> 20);
+        printk(KERN_INFO TTM_PFX "TTM available object memory: %llu MiB\n",
+               glob->max_memory >> 20);
+
+        return 0;
+}
+EXPORT_SYMBOL(ttm_mem_global_init);
+
+void ttm_mem_global_release(struct ttm_mem_global *glob)
+{
+        printk(KERN_INFO TTM_PFX "Used total memory is %llu bytes.\n",
+               (unsigned long long)glob->used_total_memory);
+        flush_workqueue(glob->swap_queue);
+        destroy_workqueue(glob->swap_queue);
+        glob->swap_queue = NULL;
+}
+EXPORT_SYMBOL(ttm_mem_global_release);
+
+static inline void ttm_check_swapping(struct ttm_mem_global *glob)
+{
+        bool needs_swapping;
+
+        spin_lock(&glob->lock);
+        needs_swapping = (glob->used_memory > glob->swap_limit ||
+                          glob->used_total_memory >
+                          glob->total_memory_swap_limit);
+        spin_unlock(&glob->lock);
+
+        if (unlikely(needs_swapping))
+                (void)queue_work(glob->swap_queue, &glob->work);
+
+}
+
+void ttm_mem_global_free(struct ttm_mem_global *glob,
+                         uint64_t amount, bool himem)
+{
+        spin_lock(&glob->lock);
+        glob->used_total_memory -= amount;
+        if (!himem)
+                glob->used_memory -= amount;
+        wake_up_all(&glob->queue);
+        spin_unlock(&glob->lock);
+}
+
+static int ttm_mem_global_reserve(struct ttm_mem_global *glob,
+                                  uint64_t amount, bool himem, bool reserve)
+{
+        uint64_t limit;
+        uint64_t lomem_limit;
+        int ret = -ENOMEM;
+
+        spin_lock(&glob->lock);
+
+        if (capable(CAP_SYS_ADMIN)) {
+                limit = glob->emer_total_memory;
+                lomem_limit = glob->emer_memory;
+        } else {
+                limit = glob->max_total_memory;
+                lomem_limit = glob->max_memory;
+        }
+
+        if (unlikely(glob->used_total_memory + amount > limit))
+                goto out_unlock;
+        if (unlikely(!himem && glob->used_memory + amount > lomem_limit))
+                goto out_unlock;
+
+        if (reserve) {
+                glob->used_total_memory += amount;
+                if (!himem)
+                        glob->used_memory += amount;
+        }
+        ret = 0;
+out_unlock:
+        spin_unlock(&glob->lock);
+        ttm_check_swapping(glob);
+
+        return ret;
+}
+
+int ttm_mem_global_alloc(struct ttm_mem_global *glob, uint64_t memory,
+                         bool no_wait, bool interruptible, bool himem)
+{
+        int count = TTM_MEMORY_ALLOC_RETRIES;
+
+        while (unlikely(ttm_mem_global_reserve(glob, memory, himem, true)
+                        != 0)) {
+                if (no_wait)
+                        return -ENOMEM;
+                if (unlikely(count-- == 0))
+                        return -ENOMEM;
+                ttm_shrink(glob, false, memory + (memory >> 2) + 16);
+        }
+
+        return 0;
+}
+
+size_t ttm_round_pot(size_t size)
+{
+        if ((size & (size - 1)) == 0)
+                return size;
+        else if (size > PAGE_SIZE)
+                return PAGE_ALIGN(size);
+        else {
+                size_t tmp_size = 4;
+
+                while (tmp_size < size)
+                        tmp_size <<= 1;
+
+                return tmp_size;
+        }
+        return 0;
+}
diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c
new file mode 100644
index 000000000000..59ce8191d584
--- /dev/null
+++ b/drivers/gpu/drm/ttm/ttm_module.c
@@ -0,0 +1,50 @@
+/**************************************************************************
+ *
+ * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+/*
+ * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
+ *          Jerome Glisse
+ */
+#include <linux/module.h>
+#include <ttm/ttm_module.h>
+
+static int __init ttm_init(void)
+{
+        ttm_global_init();
+        return 0;
+}
+
+static void __exit ttm_exit(void)
+{
+        ttm_global_release();
+}
+
+module_init(ttm_init);
+module_exit(ttm_exit);
+
+MODULE_AUTHOR("Thomas Hellstrom, Jerome Glisse");
+MODULE_DESCRIPTION("TTM memory manager subsystem (for DRM device)");
+MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
new file mode 100644
index 000000000000..c27ab3a877ad
--- /dev/null
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -0,0 +1,635 @@
+/**************************************************************************
+ *
+ * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+/*
+ * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
+ */
+
+#include <linux/version.h>
+#include <linux/vmalloc.h>
+#include <linux/sched.h>
+#include <linux/highmem.h>
+#include <linux/pagemap.h>
+#include <linux/file.h>
+#include <linux/swap.h>
+#include "ttm/ttm_module.h"
+#include "ttm/ttm_bo_driver.h"
+#include "ttm/ttm_placement.h"
+
+static int ttm_tt_swapin(struct ttm_tt *ttm);
+
+#if defined(CONFIG_X86)
+static void ttm_tt_clflush_page(struct page *page)
+{
+        uint8_t *page_virtual;
+        unsigned int i;
+
+        if (unlikely(page == NULL))
+                return;
+
+        page_virtual = kmap_atomic(page, KM_USER0);
+
+        for (i = 0; i < PAGE_SIZE; i += boot_cpu_data.x86_clflush_size)
+                clflush(page_virtual + i);
+
+        kunmap_atomic(page_virtual, KM_USER0);
+}
+
+static void ttm_tt_cache_flush_clflush(struct page *pages[],
+                                       unsigned long num_pages)
+{
+        unsigned long i;
+
+        mb();
+        for (i = 0; i < num_pages; ++i)
+                ttm_tt_clflush_page(*pages++);
+        mb();
+}
+#else
+static void ttm_tt_ipi_handler(void *null)
+{
+        ;
+}
+#endif
+
+void ttm_tt_cache_flush(struct page *pages[], unsigned long num_pages)
+{
+
+#if defined(CONFIG_X86)
+        if (cpu_has_clflush) {
+                ttm_tt_cache_flush_clflush(pages, num_pages);
+                return;
+        }
+#else
+        if (on_each_cpu(ttm_tt_ipi_handler, NULL, 1) != 0)
+                printk(KERN_ERR TTM_PFX
+                       "Timed out waiting for drm cache flush.\n");
+#endif
+}
+
+/**
+ * Allocates storage for pointers to the pages that back the ttm.
+ *
+ * Uses kmalloc if possible. Otherwise falls back to vmalloc.
+ */
+static void ttm_tt_alloc_page_directory(struct ttm_tt *ttm)
+{
+        unsigned long size = ttm->num_pages * sizeof(*ttm->pages);
+        ttm->pages = NULL;
+
+        if (size <= PAGE_SIZE)
+                ttm->pages = kzalloc(size, GFP_KERNEL);
+
+        if (!ttm->pages) {
+                ttm->pages = vmalloc_user(size);
+                if (ttm->pages)
+                        ttm->page_flags |= TTM_PAGE_FLAG_VMALLOC;
+        }
+}
+
+static void ttm_tt_free_page_directory(struct ttm_tt *ttm)
+{
+        if (ttm->page_flags & TTM_PAGE_FLAG_VMALLOC) {
+                vfree(ttm->pages);
+                ttm->page_flags &= ~TTM_PAGE_FLAG_VMALLOC;
+        } else {
+                kfree(ttm->pages);
+        }
+        ttm->pages = NULL;
+}
+
+static struct page *ttm_tt_alloc_page(unsigned page_flags)
+{
+        if (page_flags & TTM_PAGE_FLAG_ZERO_ALLOC)
+                return alloc_page(GFP_HIGHUSER | __GFP_ZERO);
+
+        return alloc_page(GFP_HIGHUSER);
+}
+
+static void ttm_tt_free_user_pages(struct ttm_tt *ttm)
+{
+        int write;
+        int dirty;
+        struct page *page;
+        int i;
+        struct ttm_backend *be = ttm->be;
+
+        BUG_ON(!(ttm->page_flags & TTM_PAGE_FLAG_USER));
+        write = ((ttm->page_flags & TTM_PAGE_FLAG_WRITE) != 0);
+        dirty = ((ttm->page_flags & TTM_PAGE_FLAG_USER_DIRTY) != 0);
+
+        if (be)
+                be->func->clear(be);
+
+        for (i = 0; i < ttm->num_pages; ++i) {
+                page = ttm->pages[i];
+                if (page == NULL)
+                        continue;
+
+                if (page == ttm->dummy_read_page) {
+                        BUG_ON(write);
+                        continue;
+                }
+
+                if (write && dirty && !PageReserved(page))
+                        set_page_dirty_lock(page);
+
+                ttm->pages[i] = NULL;
+                ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE, false);
+                put_page(page);
+        }
+        ttm->state = tt_unpopulated;
+        ttm->first_himem_page = ttm->num_pages;
+        ttm->last_lomem_page = -1;
+}
+
+static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index)
+{
+        struct page *p;
+        struct ttm_bo_device *bdev = ttm->bdev;
+        struct ttm_mem_global *mem_glob = bdev->mem_glob;
+        int ret;
+
+        while (NULL == (p = ttm->pages[index])) {
+                p = ttm_tt_alloc_page(ttm->page_flags);
+
+                if (!p)
+                        return NULL;
+
+                if (PageHighMem(p)) {
+                        ret =
+                            ttm_mem_global_alloc(mem_glob, PAGE_SIZE,
+                                                 false, false, true);
+                        if (unlikely(ret != 0))
+                                goto out_err;
+                        ttm->pages[--ttm->first_himem_page] = p;
+                } else {
+                        ret =
+                            ttm_mem_global_alloc(mem_glob, PAGE_SIZE,
+                                                 false, false, false);
+                        if (unlikely(ret != 0))
+                                goto out_err;
+                        ttm->pages[++ttm->last_lomem_page] = p;
+                }
+        }
+        return p;
+out_err:
+        put_page(p);
+        return NULL;
+}
+
+struct page *ttm_tt_get_page(struct ttm_tt *ttm, int index)
+{
+        int ret;
+
+        if (unlikely(ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)) {
+                ret = ttm_tt_swapin(ttm);
+                if (unlikely(ret != 0))
+                        return NULL;
+        }
+        return __ttm_tt_get_page(ttm, index);
+}
+
+int ttm_tt_populate(struct ttm_tt *ttm)
+{
+        struct page *page;
+        unsigned long i;
+        struct ttm_backend *be;
+        int ret;
+
+        if (ttm->state != tt_unpopulated)
+                return 0;
+
+        if (unlikely(ttm->page_flags & TTM_PAGE_FLAG_SWAPPED)) {
+                ret = ttm_tt_swapin(ttm);
+                if (unlikely(ret != 0))
+                        return ret;
+        }
+
+        be = ttm->be;
+
+        for (i = 0; i < ttm->num_pages; ++i) {
+                page = __ttm_tt_get_page(ttm, i);
+                if (!page)
+                        return -ENOMEM;
+        }
+
+        be->func->populate(be, ttm->num_pages, ttm->pages,
+                           ttm->dummy_read_page);
+        ttm->state = tt_unbound;
+        return 0;
+}
+
+#ifdef CONFIG_X86
+static inline int ttm_tt_set_page_caching(struct page *p,
+                                          enum ttm_caching_state c_state)
+{
+        if (PageHighMem(p))
+                return 0;
+
+        switch (c_state) {
+        case tt_cached:
+                return set_pages_wb(p, 1);
+        case tt_wc:
+            return set_memory_wc((unsigned long) page_address(p), 1);
+        default:
+                return set_pages_uc(p, 1);
+        }
+}
+#else /* CONFIG_X86 */
+static inline int ttm_tt_set_page_caching(struct page *p,
+                                          enum ttm_caching_state c_state)
+{
+        return 0;
+}
+#endif /* CONFIG_X86 */
+
+/*
+ * Change caching policy for the linear kernel map
+ * for range of pages in a ttm.
+ */
+
+static int ttm_tt_set_caching(struct ttm_tt *ttm,
+                              enum ttm_caching_state c_state)
+{
+        int i, j;
+        struct page *cur_page;
+        int ret;
+
+        if (ttm->caching_state == c_state)
+                return 0;
+
+        if (c_state != tt_cached) {
+                ret = ttm_tt_populate(ttm);
+                if (unlikely(ret != 0))
+                        return ret;
+        }
+
+        if (ttm->caching_state == tt_cached)
+                ttm_tt_cache_flush(ttm->pages, ttm->num_pages);
+
+        for (i = 0; i < ttm->num_pages; ++i) {
+                cur_page = ttm->pages[i];
+                if (likely(cur_page != NULL)) {
+                        ret = ttm_tt_set_page_caching(cur_page, c_state);
+                        if (unlikely(ret != 0))
+                                goto out_err;
+                }
+        }
+
+        ttm->caching_state = c_state;
+
+        return 0;
+
+out_err:
+        for (j = 0; j < i; ++j) {
+                cur_page = ttm->pages[j];
+                if (likely(cur_page != NULL)) {
+                        (void)ttm_tt_set_page_caching(cur_page,
+                                                      ttm->caching_state);
+                }
+        }
+
+        return ret;
+}
+
+int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement)
+{
+        enum ttm_caching_state state;
+
+        if (placement & TTM_PL_FLAG_WC)
+                state = tt_wc;
+        else if (placement & TTM_PL_FLAG_UNCACHED)
+                state = tt_uncached;
+        else
+                state = tt_cached;
+
+        return ttm_tt_set_caching(ttm, state);
+}
+
+static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm)
+{
+        int i;
+        struct page *cur_page;
+        struct ttm_backend *be = ttm->be;
+
+        if (be)
+                be->func->clear(be);
+        (void)ttm_tt_set_caching(ttm, tt_cached);
+        for (i = 0; i < ttm->num_pages; ++i) {
+                cur_page = ttm->pages[i];
+                ttm->pages[i] = NULL;
+                if (cur_page) {
+                        if (page_count(cur_page) != 1)
+                                printk(KERN_ERR TTM_PFX
+                                       "Erroneous page count. "
+                                       "Leaking pages.\n");
+                        ttm_mem_global_free(ttm->bdev->mem_glob, PAGE_SIZE,
+                                            PageHighMem(cur_page));
+                        __free_page(cur_page);
+                }
+        }
+        ttm->state = tt_unpopulated;
+        ttm->first_himem_page = ttm->num_pages;
+        ttm->last_lomem_page = -1;
+}
+
+void ttm_tt_destroy(struct ttm_tt *ttm)
+{
+        struct ttm_backend *be;
+
+        if (unlikely(ttm == NULL))
+                return;
+
+        be = ttm->be;
+        if (likely(be != NULL)) {
+                be->func->destroy(be);
+                ttm->be = NULL;
+        }
+
+        if (likely(ttm->pages != NULL)) {
+                if (ttm->page_flags & TTM_PAGE_FLAG_USER)
+                        ttm_tt_free_user_pages(ttm);
+                else
+                        ttm_tt_free_alloced_pages(ttm);
+
+                ttm_tt_free_page_directory(ttm);
+        }
+
+        if (!(ttm->page_flags & TTM_PAGE_FLAG_PERSISTANT_SWAP) &&
+            ttm->swap_storage)
+                fput(ttm->swap_storage);
+
+        kfree(ttm);
+}
+
+int ttm_tt_set_user(struct ttm_tt *ttm,
+                    struct task_struct *tsk,
+                    unsigned long start, unsigned long num_pages)
+{
+        struct mm_struct *mm = tsk->mm;
+        int ret;
+        int write = (ttm->page_flags & TTM_PAGE_FLAG_WRITE) != 0;
+        struct ttm_mem_global *mem_glob = ttm->bdev->mem_glob;
+
+        BUG_ON(num_pages != ttm->num_pages);
+        BUG_ON((ttm->page_flags & TTM_PAGE_FLAG_USER) == 0);
+
+        /**
+         * Account user pages as lowmem pages for now.
+         */
+
+        ret = ttm_mem_global_alloc(mem_glob, num_pages * PAGE_SIZE,
+                                   false, false, false);
+        if (unlikely(ret != 0))
+                return ret;
+
+        down_read(&mm->mmap_sem);
+        ret = get_user_pages(tsk, mm, start, num_pages,
+                             write, 0, ttm->pages, NULL);
+        up_read(&mm->mmap_sem);
+
+        if (ret != num_pages && write) {
+                ttm_tt_free_user_pages(ttm);
+                ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE, false);
+                return -ENOMEM;
+        }
+
+        ttm->tsk = tsk;
+        ttm->start = start;
+        ttm->state = tt_unbound;
+
+        return 0;
+}
+
+struct ttm_tt *ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
+                             uint32_t page_flags, struct page *dummy_read_page)
+{
+        struct ttm_bo_driver *bo_driver = bdev->driver;
+        struct ttm_tt *ttm;
+
+        if (!bo_driver)
+                return NULL;
+
+        ttm = kzalloc(sizeof(*ttm), GFP_KERNEL);
+        if (!ttm)
+                return NULL;
+
+        ttm->bdev = bdev;
+
+        ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
+        ttm->first_himem_page = ttm->num_pages;
+        ttm->last_lomem_page = -1;
+        ttm->caching_state = tt_cached;
+        ttm->page_flags = page_flags;
+
+        ttm->dummy_read_page = dummy_read_page;
+
+        ttm_tt_alloc_page_directory(ttm);
+        if (!ttm->pages) {
+                ttm_tt_destroy(ttm);
+                printk(KERN_ERR TTM_PFX "Failed allocating page table\n");
+                return NULL;
+        }
+        ttm->be = bo_driver->create_ttm_backend_entry(bdev);
+        if (!ttm->be) {
+                ttm_tt_destroy(ttm);
+                printk(KERN_ERR TTM_PFX "Failed creating ttm backend entry\n");
+                return NULL;
+        }
+        ttm->state = tt_unpopulated;
+        return ttm;
+}
+
+void ttm_tt_unbind(struct ttm_tt *ttm)
+{
+        int ret;
+        struct ttm_backend *be = ttm->be;
+
+        if (ttm->state == tt_bound) {
+                ret = be->func->unbind(be);
+                BUG_ON(ret);
+                ttm->state = tt_unbound;
+        }
+}
+
+int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem)
+{
+        int ret = 0;
+        struct ttm_backend *be;
+
+        if (!ttm)
+                return -EINVAL;
+
+        if (ttm->state == tt_bound)
+                return 0;
+
+        be = ttm->be;
+
+        ret = ttm_tt_populate(ttm);
+        if (ret)
+                return ret;
+
+        ret = be->func->bind(be, bo_mem);
+        if (ret) {
+                printk(KERN_ERR TTM_PFX "Couldn't bind backend.\n");
+                return ret;
+        }
+
+        ttm->state = tt_bound;
+
+        if (ttm->page_flags & TTM_PAGE_FLAG_USER)
+                ttm->page_flags |= TTM_PAGE_FLAG_USER_DIRTY;
+        return 0;
+}
+EXPORT_SYMBOL(ttm_tt_bind);
+
+static int ttm_tt_swapin(struct ttm_tt *ttm)
+{
+        struct address_space *swap_space;
+        struct file *swap_storage;
+        struct page *from_page;
+        struct page *to_page;
+        void *from_virtual;
+        void *to_virtual;
+        int i;
+        int ret;
+
+        if (ttm->page_flags & TTM_PAGE_FLAG_USER) {
+                ret = ttm_tt_set_user(ttm, ttm->tsk, ttm->start,
+                                      ttm->num_pages);
+                if (unlikely(ret != 0))
+                        return ret;
+
+                ttm->page_flags &= ~TTM_PAGE_FLAG_SWAPPED;
+                return 0;
+        }
+
+        swap_storage = ttm->swap_storage;
+        BUG_ON(swap_storage == NULL);
+
+        swap_space = swap_storage->f_path.dentry->d_inode->i_mapping;
+
+        for (i = 0; i < ttm->num_pages; ++i) {
+                from_page = read_mapping_page(swap_space, i, NULL);
+                if (IS_ERR(from_page))
+                        goto out_err;
+                to_page = __ttm_tt_get_page(ttm, i);
+                if (unlikely(to_page == NULL))
+                        goto out_err;
+
+                preempt_disable();
+                from_virtual = kmap_atomic(from_page, KM_USER0);
+                to_virtual = kmap_atomic(to_page, KM_USER1);
+                memcpy(to_virtual, from_virtual, PAGE_SIZE);
+                kunmap_atomic(to_virtual, KM_USER1);
+                kunmap_atomic(from_virtual, KM_USER0);
+                preempt_enable();
+                page_cache_release(from_page);
+        }
+
+        if (!(ttm->page_flags & TTM_PAGE_FLAG_PERSISTANT_SWAP))
+                fput(swap_storage);
+        ttm->swap_storage = NULL;
+        ttm->page_flags &= ~TTM_PAGE_FLAG_SWAPPED;
+
+        return 0;
+out_err:
+        ttm_tt_free_alloced_pages(ttm);
+        return -ENOMEM;
+}
+
+int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistant_swap_storage)
+{
+        struct address_space *swap_space;
+        struct file *swap_storage;
+        struct page *from_page;
+        struct page *to_page;
+        void *from_virtual;
+        void *to_virtual;
+        int i;
+
+        BUG_ON(ttm->state != tt_unbound && ttm->state != tt_unpopulated);
+        BUG_ON(ttm->caching_state != tt_cached);
+
+        /*
+         * For user buffers, just unpin the pages, as there should be
+         * vma references.
+         */
+
+        if (ttm->page_flags & TTM_PAGE_FLAG_USER) {
+                ttm_tt_free_user_pages(ttm);
+                ttm->page_flags |= TTM_PAGE_FLAG_SWAPPED;
+                ttm->swap_storage = NULL;
+                return 0;
+        }
+
+        if (!persistant_swap_storage) {
+                swap_storage = shmem_file_setup("ttm swap",
+                                                ttm->num_pages << PAGE_SHIFT,
+                                                0);
+                if (unlikely(IS_ERR(swap_storage))) {
+                        printk(KERN_ERR "Failed allocating swap storage.\n");
+                        return -ENOMEM;
+                }
+        } else
+                swap_storage = persistant_swap_storage;
+
+        swap_space = swap_storage->f_path.dentry->d_inode->i_mapping;
+
+        for (i = 0; i < ttm->num_pages; ++i) {
+                from_page = ttm->pages[i];
+                if (unlikely(from_page == NULL))
+                        continue;
+                to_page = read_mapping_page(swap_space, i, NULL);
+                if (unlikely(to_page == NULL))
+                        goto out_err;
+
+                preempt_disable();
+                from_virtual = kmap_atomic(from_page, KM_USER0);
+                to_virtual = kmap_atomic(to_page, KM_USER1);
+                memcpy(to_virtual, from_virtual, PAGE_SIZE);
+                kunmap_atomic(to_virtual, KM_USER1);
+                kunmap_atomic(from_virtual, KM_USER0);
+                preempt_enable();
+                set_page_dirty(to_page);
+                mark_page_accessed(to_page);
+                page_cache_release(to_page);
+        }
+
+        ttm_tt_free_alloced_pages(ttm);
+        ttm->swap_storage = swap_storage;
+        ttm->page_flags |= TTM_PAGE_FLAG_SWAPPED;
+        if (persistant_swap_storage)
+                ttm->page_flags |= TTM_PAGE_FLAG_PERSISTANT_SWAP;
+
+        return 0;
+out_err:
+        if (!persistant_swap_storage)
+                fput(swap_storage);
+
+        return -ENOMEM;
+}
diff --git a/drivers/hid/usbhid/hiddev.c b/drivers/hid/usbhid/hiddev.c
index e9b436d2d944..9e9421525fb9 100644
--- a/drivers/hid/usbhid/hiddev.c
+++ b/drivers/hid/usbhid/hiddev.c
@@ -850,8 +850,14 @@ static const struct file_operations hiddev_fops = {
 #endif
 };
 
+static char *hiddev_nodename(struct device *dev)
+{
+        return kasprintf(GFP_KERNEL, "usb/%s", dev_name(dev));
+}
+
 static struct usb_class_driver hiddev_class = {
         .name =         "hiddev%d",
+        .nodename =     hiddev_nodename,
         .fops =         &hiddev_fops,
         .minor_base =   HIDDEV_MINOR_BASE,
 };
@@ -955,7 +961,6 @@ static int hiddev_usbd_probe(struct usb_interface *intf,
         return -ENODEV;
 }
 
-
 static /* const */ struct usb_driver hiddev_driver = {
         .name =         "hiddev",
         .probe =        hiddev_usbd_probe,
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index f8090e137fef..2d5016691d40 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -950,6 +950,7 @@ config SENSORS_HDAPS
 config SENSORS_LIS3LV02D
         tristate "STMicroeletronics LIS3LV02Dx three-axis digital accelerometer"
         depends on ACPI && INPUT
+        select INPUT_POLLDEV
         select NEW_LEDS
         select LEDS_CLASS
         default n
@@ -977,6 +978,7 @@ config SENSORS_LIS3LV02D
 config SENSORS_LIS3_SPI
         tristate "STMicroeletronics LIS3LV02Dx three-axis digital accelerometer (SPI)"
         depends on !ACPI && SPI_MASTER && INPUT
+        select INPUT_POLLDEV
         default n
         help
           This driver provides support for the LIS3LV02Dx accelerometer connected
diff --git a/drivers/hwmon/hp_accel.c b/drivers/hwmon/hp_accel.c
index abca7e9f953b..6679854c85b0 100644
--- a/drivers/hwmon/hp_accel.c
+++ b/drivers/hwmon/hp_accel.c
@@ -27,9 +27,6 @@
 #include <linux/types.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
-#include <linux/input.h>
-#include <linux/kthread.h>
-#include <linux/semaphore.h>
 #include <linux/delay.h>
 #include <linux/wait.h>
 #include <linux/poll.h>
@@ -161,6 +158,7 @@ static struct axis_conversion lis3lv02d_axis_normal = {1, 2, 3};
 static struct axis_conversion lis3lv02d_axis_y_inverted = {1, -2, 3};
 static struct axis_conversion lis3lv02d_axis_x_inverted = {-1, 2, 3};
 static struct axis_conversion lis3lv02d_axis_z_inverted = {1, 2, -3};
+static struct axis_conversion lis3lv02d_axis_xy_swap = {2, 1, 3};
 static struct axis_conversion lis3lv02d_axis_xy_rotated_left = {-2, 1, 3};
 static struct axis_conversion lis3lv02d_axis_xy_rotated_left_usd = {-2, 1, -3};
 static struct axis_conversion lis3lv02d_axis_xy_swap_inverted = {-2, -1, 3};
@@ -194,13 +192,16 @@ static struct dmi_system_id lis3lv02d_dmi_ids[] = {
         AXIS_DMI_MATCH("NX9420", "HP Compaq nx9420", x_inverted),
         AXIS_DMI_MATCH("NW9440", "HP Compaq nw9440", x_inverted),
         AXIS_DMI_MATCH("NC2510", "HP Compaq 2510", y_inverted),
+        AXIS_DMI_MATCH("NC2710", "HP Compaq 2710", xy_swap),
         AXIS_DMI_MATCH("NC8510", "HP Compaq 8510", xy_swap_inverted),
         AXIS_DMI_MATCH("HP2133", "HP 2133", xy_rotated_left),
         AXIS_DMI_MATCH("HP2140", "HP 2140", xy_swap_inverted),
         AXIS_DMI_MATCH("NC653x", "HP Compaq 653", xy_rotated_left_usd),
         AXIS_DMI_MATCH("NC673x", "HP Compaq 673", xy_rotated_left_usd),
         AXIS_DMI_MATCH("NC651xx", "HP Compaq 651", xy_rotated_right),
-        AXIS_DMI_MATCH("NC671xx", "HP Compaq 671", xy_swap_yz_inverted),
+        AXIS_DMI_MATCH("NC6710x", "HP Compaq 6710", xy_swap_yz_inverted),
+        AXIS_DMI_MATCH("NC6715x", "HP Compaq 6715", y_inverted),
+        AXIS_DMI_MATCH("NC693xx", "HP EliteBook 693", xy_rotated_right),
         /* Intel-based HP Pavilion dv5 */
         AXIS_DMI_MATCH2("HPDV5_I",
                         PRODUCT_NAME, "HP Pavilion dv5",
@@ -216,7 +217,6 @@ static struct dmi_system_id lis3lv02d_dmi_ids[] = {
         { NULL, }
 /* Laptop models without axis info (yet):
  * "NC6910" "HP Compaq 6910"
- * HP Compaq 8710x Notebook PC / Mobile Workstation
  * "NC2400" "HP Compaq nc2400"
  * "NX74x0" "HP Compaq nx74"
  * "NX6325" "HP Compaq nx6325"
@@ -324,7 +324,7 @@ static int lis3lv02d_remove(struct acpi_device *device, int type)
         flush_work(&hpled_led.work);
         led_classdev_unregister(&hpled_led.led_classdev);
 
-        return lis3lv02d_remove_fs();
+        return lis3lv02d_remove_fs(&lis3_dev);
 }
 
 
@@ -338,13 +338,7 @@ static int lis3lv02d_suspend(struct acpi_device *device, pm_message_t state)
 
 static int lis3lv02d_resume(struct acpi_device *device)
 {
-        /* put back the device in the right state (ACPI might turn it on) */
-        mutex_lock(&lis3_dev.lock);
-        if (lis3_dev.usage > 0)
-                lis3lv02d_poweron(&lis3_dev);
-        else
-                lis3lv02d_poweroff(&lis3_dev);
-        mutex_unlock(&lis3_dev.lock);
+        lis3lv02d_poweron(&lis3_dev);
         return 0;
 }
 #else
diff --git a/drivers/hwmon/lis3lv02d.c b/drivers/hwmon/lis3lv02d.c
index 778eb7795983..271338bdb6be 100644
--- a/drivers/hwmon/lis3lv02d.c
+++ b/drivers/hwmon/lis3lv02d.c
@@ -27,9 +27,7 @@
 #include <linux/types.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
-#include <linux/input.h>
-#include <linux/kthread.h>
-#include <linux/semaphore.h>
+#include <linux/input-polldev.h>
 #include <linux/delay.h>
 #include <linux/wait.h>
 #include <linux/poll.h>
@@ -105,56 +103,39 @@ static void lis3lv02d_get_xyz(struct lis3lv02d *lis3, int *x, int *y, int *z)
 {
         int position[3];
 
-        position[0] = lis3_dev.read_data(lis3, OUTX);
-        position[1] = lis3_dev.read_data(lis3, OUTY);
-        position[2] = lis3_dev.read_data(lis3, OUTZ);
+        position[0] = lis3->read_data(lis3, OUTX);
+        position[1] = lis3->read_data(lis3, OUTY);
+        position[2] = lis3->read_data(lis3, OUTZ);
 
-        *x = lis3lv02d_get_axis(lis3_dev.ac.x, position);
-        *y = lis3lv02d_get_axis(lis3_dev.ac.y, position);
-        *z = lis3lv02d_get_axis(lis3_dev.ac.z, position);
+        *x = lis3lv02d_get_axis(lis3->ac.x, position);
+        *y = lis3lv02d_get_axis(lis3->ac.y, position);
+        *z = lis3lv02d_get_axis(lis3->ac.z, position);
 }
 
 void lis3lv02d_poweroff(struct lis3lv02d *lis3)
 {
-        lis3_dev.is_on = 0;
+        /* disable X,Y,Z axis and power down */
+        lis3->write(lis3, CTRL_REG1, 0x00);
 }
 EXPORT_SYMBOL_GPL(lis3lv02d_poweroff);
 
 void lis3lv02d_poweron(struct lis3lv02d *lis3)
 {
-        lis3_dev.is_on = 1;
-        lis3_dev.init(lis3);
-}
-EXPORT_SYMBOL_GPL(lis3lv02d_poweron);
+        u8 reg;
 
-/*
- * To be called before starting to use the device. It makes sure that the
- * device will always be on until a call to lis3lv02d_decrease_use(). Not to be
- * used from interrupt context.
- */
-static void lis3lv02d_increase_use(struct lis3lv02d *dev)
-{
-        mutex_lock(&dev->lock);
-        dev->usage++;
-        if (dev->usage == 1) {
-                if (!dev->is_on)
-                        lis3lv02d_poweron(dev);
-        }
-        mutex_unlock(&dev->lock);
-}
+        lis3->init(lis3);
 
-/*
- * To be called whenever a usage of the device is stopped.
- * It will make sure to turn off the device when there is not usage.
- */
-static void lis3lv02d_decrease_use(struct lis3lv02d *dev)
-{
-        mutex_lock(&dev->lock);
-        dev->usage--;
-        if (dev->usage == 0)
-                lis3lv02d_poweroff(dev);
-        mutex_unlock(&dev->lock);
+        /*
+         * Common configuration
+         * BDU: LSB and MSB values are not updated until both have been read.
+         *      So the value read will always be correct.
+         */
+        lis3->read(lis3, CTRL_REG2, &reg);
+        reg |= CTRL2_BDU;
+        lis3->write(lis3, CTRL_REG2, reg);
 }
+EXPORT_SYMBOL_GPL(lis3lv02d_poweron);
+
 
 static irqreturn_t lis302dl_interrupt(int irq, void *dummy)
 {
@@ -198,15 +179,12 @@ static int lis3lv02d_misc_open(struct inode *inode, struct file *file)
                 printk(KERN_ERR DRIVER_NAME ": IRQ%d allocation failed\n", lis3_dev.irq);
                 return -EBUSY;
         }
-        lis3lv02d_increase_use(&lis3_dev);
-        printk("lis3: registered interrupt %d\n", lis3_dev.irq);
         return 0;
 }
 
 static int lis3lv02d_misc_release(struct inode *inode, struct file *file)
 {
         fasync_helper(-1, file, 0, &lis3_dev.async_queue);
-        lis3lv02d_decrease_use(&lis3_dev);
         free_irq(lis3_dev.irq, &lis3_dev);
         clear_bit(0, &lis3_dev.misc_opened); /* release the device */
         return 0;
@@ -290,46 +268,16 @@ static struct miscdevice lis3lv02d_misc_device = {
         .fops    = &lis3lv02d_misc_fops,
 };
 
-/**
- * lis3lv02d_joystick_kthread - Kthread polling function
- * @data: unused - here to conform to threadfn prototype
- */
-static int lis3lv02d_joystick_kthread(void *data)
+static void lis3lv02d_joystick_poll(struct input_polled_dev *pidev)
 {
         int x, y, z;
 
-        while (!kthread_should_stop()) {
-                lis3lv02d_get_xyz(&lis3_dev, &x, &y, &z);
-                input_report_abs(lis3_dev.idev, ABS_X, x - lis3_dev.xcalib);
-                input_report_abs(lis3_dev.idev, ABS_Y, y - lis3_dev.ycalib);
-                input_report_abs(lis3_dev.idev, ABS_Z, z - lis3_dev.zcalib);
-
-                input_sync(lis3_dev.idev);
-
-                try_to_freeze();
-                msleep_interruptible(MDPS_POLL_INTERVAL);
-        }
-
-        return 0;
-}
-
-static int lis3lv02d_joystick_open(struct input_dev *input)
-{
-        lis3lv02d_increase_use(&lis3_dev);
-        lis3_dev.kthread = kthread_run(lis3lv02d_joystick_kthread, NULL, "klis3lv02d");
-        if (IS_ERR(lis3_dev.kthread)) {
-                lis3lv02d_decrease_use(&lis3_dev);
-                return PTR_ERR(lis3_dev.kthread);
-        }
-
-        return 0;
+        lis3lv02d_get_xyz(&lis3_dev, &x, &y, &z);
+        input_report_abs(pidev->input, ABS_X, x - lis3_dev.xcalib);
+        input_report_abs(pidev->input, ABS_Y, y - lis3_dev.ycalib);
+        input_report_abs(pidev->input, ABS_Z, z - lis3_dev.zcalib);
 }
 
-static void lis3lv02d_joystick_close(struct input_dev *input)
-{
-        kthread_stop(lis3_dev.kthread);
-        lis3lv02d_decrease_use(&lis3_dev);
-}
 
 static inline void lis3lv02d_calibrate_joystick(void)
 {
@@ -339,33 +287,36 @@ static inline void lis3lv02d_calibrate_joystick(void)
 
 int lis3lv02d_joystick_enable(void)
 {
+        struct input_dev *input_dev;
         int err;
 
         if (lis3_dev.idev)
                 return -EINVAL;
 
-        lis3_dev.idev = input_allocate_device();
+        lis3_dev.idev = input_allocate_polled_device();
         if (!lis3_dev.idev)
                 return -ENOMEM;
 
+        lis3_dev.idev->poll = lis3lv02d_joystick_poll;
+        lis3_dev.idev->poll_interval = MDPS_POLL_INTERVAL;
+        input_dev = lis3_dev.idev->input;
+
         lis3lv02d_calibrate_joystick();
 
-        lis3_dev.idev->name       = "ST LIS3LV02DL Accelerometer";
-        lis3_dev.idev->phys       = DRIVER_NAME "/input0";
-        lis3_dev.idev->id.bustype = BUS_HOST;
-        lis3_dev.idev->id.vendor  = 0;
-        lis3_dev.idev->dev.parent = &lis3_dev.pdev->dev;
-        lis3_dev.idev->open       = lis3lv02d_joystick_open;
-        lis3_dev.idev->close      = lis3lv02d_joystick_close;
+        input_dev->name       = "ST LIS3LV02DL Accelerometer";
+        input_dev->phys       = DRIVER_NAME "/input0";
+        input_dev->id.bustype = BUS_HOST;
+        input_dev->id.vendor  = 0;
+        input_dev->dev.parent = &lis3_dev.pdev->dev;
 
-        set_bit(EV_ABS, lis3_dev.idev->evbit);
-        input_set_abs_params(lis3_dev.idev, ABS_X, -lis3_dev.mdps_max_val, lis3_dev.mdps_max_val, 3, 3);
-        input_set_abs_params(lis3_dev.idev, ABS_Y, -lis3_dev.mdps_max_val, lis3_dev.mdps_max_val, 3, 3);
-        input_set_abs_params(lis3_dev.idev, ABS_Z, -lis3_dev.mdps_max_val, lis3_dev.mdps_max_val, 3, 3);
+        set_bit(EV_ABS, input_dev->evbit);
+        input_set_abs_params(input_dev, ABS_X, -lis3_dev.mdps_max_val, lis3_dev.mdps_max_val, 3, 3);
+        input_set_abs_params(input_dev, ABS_Y, -lis3_dev.mdps_max_val, lis3_dev.mdps_max_val, 3, 3);
+        input_set_abs_params(input_dev, ABS_Z, -lis3_dev.mdps_max_val, lis3_dev.mdps_max_val, 3, 3);
 
-        err = input_register_device(lis3_dev.idev);
+        err = input_register_polled_device(lis3_dev.idev);
         if (err) {
-                input_free_device(lis3_dev.idev);
+                input_free_polled_device(lis3_dev.idev);
                 lis3_dev.idev = NULL;
         }
 
@@ -378,8 +329,9 @@ void lis3lv02d_joystick_disable(void)
         if (!lis3_dev.idev)
                 return;
 
-        misc_deregister(&lis3lv02d_misc_device);
-        input_unregister_device(lis3_dev.idev);
+        if (lis3_dev.irq)
+                misc_deregister(&lis3lv02d_misc_device);
+        input_unregister_polled_device(lis3_dev.idev);
         lis3_dev.idev = NULL;
 }
 EXPORT_SYMBOL_GPL(lis3lv02d_joystick_disable);
@@ -390,9 +342,7 @@ static ssize_t lis3lv02d_position_show(struct device *dev,
 {
         int x, y, z;
 
-        lis3lv02d_increase_use(&lis3_dev);
         lis3lv02d_get_xyz(&lis3_dev, &x, &y, &z);
-        lis3lv02d_decrease_use(&lis3_dev);
         return sprintf(buf, "(%d,%d,%d)\n", x, y, z);
 }
 
@@ -406,9 +356,7 @@ static ssize_t lis3lv02d_calibrate_store(struct device *dev,
                                 struct device_attribute *attr,
                                 const char *buf, size_t count)
 {
-        lis3lv02d_increase_use(&lis3_dev);
         lis3lv02d_calibrate_joystick();
-        lis3lv02d_decrease_use(&lis3_dev);
         return count;
 }
 
@@ -420,9 +368,7 @@ static ssize_t lis3lv02d_rate_show(struct device *dev,
         u8 ctrl;
         int val;
 
-        lis3lv02d_increase_use(&lis3_dev);
         lis3_dev.read(&lis3_dev, CTRL_REG1, &ctrl);
-        lis3lv02d_decrease_use(&lis3_dev);
         val = (ctrl & (CTRL1_DF0 | CTRL1_DF1)) >> 4;
         return sprintf(buf, "%d\n", lis3lv02dl_df_val[val]);
 }
@@ -446,17 +392,17 @@ static struct attribute_group lis3lv02d_attribute_group = {
 
 static int lis3lv02d_add_fs(struct lis3lv02d *lis3)
 {
-        lis3_dev.pdev = platform_device_register_simple(DRIVER_NAME, -1, NULL, 0);
-        if (IS_ERR(lis3_dev.pdev))
-                return PTR_ERR(lis3_dev.pdev);
+        lis3->pdev = platform_device_register_simple(DRIVER_NAME, -1, NULL, 0);
+        if (IS_ERR(lis3->pdev))
+                return PTR_ERR(lis3->pdev);
 
-        return sysfs_create_group(&lis3_dev.pdev->dev.kobj, &lis3lv02d_attribute_group);
+        return sysfs_create_group(&lis3->pdev->dev.kobj, &lis3lv02d_attribute_group);
 }
 
-int lis3lv02d_remove_fs(void)
+int lis3lv02d_remove_fs(struct lis3lv02d *lis3)
 {
-        sysfs_remove_group(&lis3_dev.pdev->dev.kobj, &lis3lv02d_attribute_group);
-        platform_device_unregister(lis3_dev.pdev);
+        sysfs_remove_group(&lis3->pdev->dev.kobj, &lis3lv02d_attribute_group);
+        platform_device_unregister(lis3->pdev);
         return 0;
 }
 EXPORT_SYMBOL_GPL(lis3lv02d_remove_fs);
@@ -482,18 +428,35 @@ int lis3lv02d_init_device(struct lis3lv02d *dev)
                 break;
         default:
                 printk(KERN_ERR DRIVER_NAME
-                        ": unknown sensor type 0x%X\n", lis3_dev.whoami);
+                        ": unknown sensor type 0x%X\n", dev->whoami);
                 return -EINVAL;
         }
 
-        mutex_init(&dev->lock);
         lis3lv02d_add_fs(dev);
-        lis3lv02d_increase_use(dev);
+        lis3lv02d_poweron(dev);
 
         if (lis3lv02d_joystick_enable())
                 printk(KERN_ERR DRIVER_NAME ": joystick initialization failed\n");
 
-        printk("lis3_init_device: irq %d\n", dev->irq);
+        /* passing in platform specific data is purely optional and only
+         * used by the SPI transport layer at the moment */
+        if (dev->pdata) {
+                struct lis3lv02d_platform_data *p = dev->pdata;
+
+                if (p->click_flags && (dev->whoami == LIS_SINGLE_ID)) {
+                        dev->write(dev, CLICK_CFG, p->click_flags);
+                        dev->write(dev, CLICK_TIMELIMIT, p->click_time_limit);
+                        dev->write(dev, CLICK_LATENCY, p->click_latency);
+                        dev->write(dev, CLICK_WINDOW, p->click_window);
+                        dev->write(dev, CLICK_THSZ, p->click_thresh_z & 0xf);
+                        dev->write(dev, CLICK_THSY_X,
+                                        (p->click_thresh_x & 0xf) |
+                                        (p->click_thresh_y << 4));
+                }
+
+                if (p->irq_cfg)
+                        dev->write(dev, CTRL_REG3, p->irq_cfg);
+        }
 
         /* bail if we did not get an IRQ from the bus layer */
         if (!dev->irq) {
@@ -502,11 +465,9 @@ int lis3lv02d_init_device(struct lis3lv02d *dev)
                 goto out;
         }
 
-        printk("lis3: registering device\n");
         if (misc_register(&lis3lv02d_misc_device))
                 printk(KERN_ERR DRIVER_NAME ": misc_register failed\n");
 out:
-        lis3lv02d_decrease_use(dev);
         return 0;
 }
 EXPORT_SYMBOL_GPL(lis3lv02d_init_device);
diff --git a/drivers/hwmon/lis3lv02d.h b/drivers/hwmon/lis3lv02d.h
index 745ec96806d4..e320e2f511f1 100644
--- a/drivers/hwmon/lis3lv02d.h
+++ b/drivers/hwmon/lis3lv02d.h
@@ -18,6 +18,8 @@
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
+#include <linux/platform_device.h>
+#include <linux/input-polldev.h>
 
 /*
  * The actual chip is STMicroelectronics LIS3LV02DL or LIS3LV02DQ that seems to
@@ -27,12 +29,14 @@
  * They can also be connected via I²C.
  */
 
+#include <linux/lis3lv02d.h>
+
 /* 2-byte registers */
 #define LIS_DOUBLE_ID   0x3A /* LIS3LV02D[LQ] */
 /* 1-byte registers */
 #define LIS_SINGLE_ID   0x3B /* LIS[32]02DL and others */
 
-enum lis3lv02d_reg {
+enum lis3_reg {
         WHO_AM_I        = 0x0F,
         OFFSET_X        = 0x16,
         OFFSET_Y        = 0x17,
@@ -60,6 +64,19 @@ enum lis3lv02d_reg {
         FF_WU_THS_L     = 0x34,
         FF_WU_THS_H     = 0x35,
         FF_WU_DURATION  = 0x36,
+};
+
+enum lis302d_reg {
+        CLICK_CFG       = 0x38,
+        CLICK_SRC       = 0x39,
+        CLICK_THSY_X    = 0x3B,
+        CLICK_THSZ      = 0x3C,
+        CLICK_TIMELIMIT = 0x3D,
+        CLICK_LATENCY   = 0x3E,
+        CLICK_WINDOW    = 0x3F,
+};
+
+enum lis3lv02d_reg {
         DD_CFG          = 0x38,
         DD_SRC          = 0x39,
         DD_ACK          = 0x3A,
@@ -169,22 +186,20 @@ struct lis3lv02d {
         s16 (*read_data) (struct lis3lv02d *lis3, int reg);
         int                     mdps_max_val;
 
-        struct input_dev        *idev;     /* input device */
-        struct task_struct      *kthread;  /* kthread for input */
-        struct mutex            lock;
+        struct input_polled_dev *idev;     /* input device */
         struct platform_device  *pdev;     /* platform device */
         atomic_t                count;     /* interrupt count after last read */
         int                     xcalib;    /* calibrated null value for x */
         int                     ycalib;    /* calibrated null value for y */
         int                     zcalib;    /* calibrated null value for z */
-        unsigned char           is_on;     /* whether the device is on or off */
-        unsigned char           usage;     /* usage counter */
         struct axis_conversion  ac;        /* hw -> logical axis */
 
         u32                     irq;       /* IRQ number */
         struct fasync_struct    *async_queue; /* queue for the misc device */
         wait_queue_head_t       misc_wait; /* Wait queue for the misc device */
         unsigned long           misc_opened; /* bit0: whether the device is open */
+
+        struct lis3lv02d_platform_data *pdata;  /* for passing board config */
 };
 
 int lis3lv02d_init_device(struct lis3lv02d *lis3);
@@ -192,6 +207,6 @@ int lis3lv02d_joystick_enable(void);
 void lis3lv02d_joystick_disable(void);
 void lis3lv02d_poweroff(struct lis3lv02d *lis3);
 void lis3lv02d_poweron(struct lis3lv02d *lis3);
-int lis3lv02d_remove_fs(void);
+int lis3lv02d_remove_fs(struct lis3lv02d *lis3);
 
 extern struct lis3lv02d lis3_dev;
diff --git a/drivers/hwmon/lis3lv02d_spi.c b/drivers/hwmon/lis3lv02d_spi.c
index 07ae74b0e191..3827ff04485f 100644
--- a/drivers/hwmon/lis3lv02d_spi.c
+++ b/drivers/hwmon/lis3lv02d_spi.c
@@ -72,6 +72,7 @@ static int __devinit lis302dl_spi_probe(struct spi_device *spi)
         lis3_dev.write = lis3_spi_write;
         lis3_dev.irq = spi->irq;
         lis3_dev.ac = lis3lv02d_axis_normal;
+        lis3_dev.pdata = spi->dev.platform_data;
         spi_set_drvdata(spi, &lis3_dev);
 
         ret = lis3lv02d_init_device(&lis3_dev);
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 0d04d3ebfc2d..3c259ee7ddda 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -513,6 +513,19 @@ config I2C_SIMTEC
           This driver can also be built as a module. If so, the module
           will be called i2c-simtec.
 
+config I2C_STU300
+        tristate "ST Microelectronics DDC I2C interface"
+        depends on MACH_U300
+        default y if MACH_U300
+        help
+          If you say yes to this option, support will be included for the
+          I2C interface from ST Microelectronics simply called "DDC I2C"
+          supporting both I2C and DDC, used in e.g. the U300 series
+          mobile platforms.
+
+          This driver can also be built as a module. If so, the module
+          will be called i2c-stu300.
+
 config I2C_VERSATILE
         tristate "ARM Versatile/Realview I2C bus support"
         depends on ARCH_VERSATILE || ARCH_REALVIEW
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 776acb6403a7..edeabf003106 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_I2C_S6000)		+= i2c-s6000.o
 obj-$(CONFIG_I2C_SH7760)        += i2c-sh7760.o
 obj-$(CONFIG_I2C_SH_MOBILE)     += i2c-sh_mobile.o
 obj-$(CONFIG_I2C_SIMTEC)        += i2c-simtec.o
+obj-$(CONFIG_I2C_STU300)        += i2c-stu300.o
 obj-$(CONFIG_I2C_VERSATILE)     += i2c-versatile.o
 
 # External I2C/SMBus adapter drivers
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 67d9dc5b351b..06e1ecb4919f 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -200,10 +200,10 @@ static int __devinit at91_i2c_probe(struct platform_device *pdev)
         if (!res)
                 return -ENXIO;
 
-        if (!request_mem_region(res->start, res->end - res->start + 1, "at91_i2c"))
+        if (!request_mem_region(res->start, resource_size(res), "at91_i2c"))
                 return -EBUSY;
 
-        twi_base = ioremap(res->start, res->end - res->start + 1);
+        twi_base = ioremap(res->start, resource_size(res));
         if (!twi_base) {
                 rc = -ENOMEM;
                 goto fail0;
@@ -252,7 +252,7 @@ fail2:
 fail1:
         iounmap(twi_base);
 fail0:
-        release_mem_region(res->start, res->end - res->start + 1);
+        release_mem_region(res->start, resource_size(res));
 
         return rc;
 }
@@ -268,7 +268,7 @@ static int __devexit at91_i2c_remove(struct platform_device *pdev)
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         iounmap(twi_base);
-        release_mem_region(res->start, res->end - res->start + 1);
+        release_mem_region(res->start, resource_size(res));
 
         clk_disable(twi_clk);           /* disable peripheral clock */
         clk_put(twi_clk);
diff --git a/drivers/i2c/busses/i2c-au1550.c b/drivers/i2c/busses/i2c-au1550.c
index f78ce523e3db..532828bc50e6 100644
--- a/drivers/i2c/busses/i2c-au1550.c
+++ b/drivers/i2c/busses/i2c-au1550.c
@@ -389,7 +389,7 @@ i2c_au1550_probe(struct platform_device *pdev)
                 goto out;
         }
 
-        priv->ioarea = request_mem_region(r->start, r->end - r->start + 1,
+        priv->ioarea = request_mem_region(r->start, resource_size(r),
                                           pdev->name);
         if (!priv->ioarea) {
                 ret = -EBUSY;
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
index 26d8987e69bf..b309ac2c3d5c 100644
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ b/drivers/i2c/busses/i2c-bfin-twi.c
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/i2c.h>
+#include <linux/io.h>
 #include <linux/mm.h>
 #include <linux/timer.h>
 #include <linux/spinlock.h>
@@ -651,7 +652,7 @@ static int i2c_bfin_twi_probe(struct platform_device *pdev)
                 goto out_error_get_res;
         }
 
-        iface->regs_base = ioremap(res->start, res->end - res->start + 1);
+        iface->regs_base = ioremap(res->start, resource_size(res));
         if (iface->regs_base == NULL) {
                 dev_err(&pdev->dev, "Cannot map IO\n");
                 rc = -ENXIO;
diff --git a/drivers/i2c/busses/i2c-highlander.c b/drivers/i2c/busses/i2c-highlander.c
index e5a8dae4a289..87ecace415da 100644
--- a/drivers/i2c/busses/i2c-highlander.c
+++ b/drivers/i2c/busses/i2c-highlander.c
@@ -373,7 +373,7 @@ static int __devinit highlander_i2c_probe(struct platform_device *pdev)
         if (unlikely(!dev))
                 return -ENOMEM;
 
-        dev->base = ioremap_nocache(res->start, res->end - res->start + 1);
+        dev->base = ioremap_nocache(res->start, resource_size(res));
         if (unlikely(!dev->base)) {
                 ret = -ENXIO;
                 goto err;
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 5a4945d1dba4..c3869d94ad42 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -469,7 +469,7 @@ mv64xxx_i2c_map_regs(struct platform_device *pd,
         if (!r)
                 return -ENODEV;
 
-        size = r->end - r->start + 1;
+        size = resource_size(r);
 
         if (!request_mem_region(r->start, size, drv_data->adapter.name))
                 return -EBUSY;
diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index 3542c6ba98f1..0dabe643ec51 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c
@@ -234,14 +234,14 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
         if (!i2c)
                 return -ENOMEM;
 
-        if (!request_mem_region(res->start, res->end - res->start + 1,
+        if (!request_mem_region(res->start, resource_size(res),
                                 pdev->name)) {
                 dev_err(&pdev->dev, "Memory region busy\n");
                 ret = -EBUSY;
                 goto request_mem_failed;
         }
 
-        i2c->base = ioremap(res->start, res->end - res->start + 1);
+        i2c->base = ioremap(res->start, resource_size(res));
         if (!i2c->base) {
                 dev_err(&pdev->dev, "Unable to map registers\n");
                 ret = -EIO;
@@ -283,7 +283,7 @@ add_adapter_failed:
 request_irq_failed:
         iounmap(i2c->base);
 map_failed:
-        release_mem_region(res->start, res->end - res->start + 1);
+        release_mem_region(res->start, resource_size(res));
 request_mem_failed:
         kfree(i2c);
 
@@ -311,7 +311,7 @@ static int __devexit ocores_i2c_remove(struct platform_device* pdev)
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (res)
-                release_mem_region(res->start, res->end - res->start + 1);
+                release_mem_region(res->start, resource_size(res));
 
         kfree(i2c);
 
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index c73475dd0fba..b606db85525d 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -828,7 +828,7 @@ omap_i2c_probe(struct platform_device *pdev)
         dev->idle = 1;
         dev->dev = &pdev->dev;
         dev->irq = irq->start;
-        dev->base = ioremap(mem->start, mem->end - mem->start + 1);
+        dev->base = ioremap(mem->start, resource_size(mem));
         if (!dev->base) {
                 r = -ENOMEM;
                 goto err_free_mem;
diff --git a/drivers/i2c/busses/i2c-pca-platform.c b/drivers/i2c/busses/i2c-pca-platform.c
index 7b23891b7d59..c4df9d411cd5 100644
--- a/drivers/i2c/busses/i2c-pca-platform.c
+++ b/drivers/i2c/busses/i2c-pca-platform.c
@@ -27,8 +27,6 @@
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#define res_len(r)              ((r)->end - (r)->start + 1)
-
 struct i2c_pca_pf_data {
         void __iomem                    *reg_base;
         int                             irq;    /* if 0, use polling */
@@ -148,7 +146,7 @@ static int __devinit i2c_pca_pf_probe(struct platform_device *pdev)
                 goto e_print;
         }
 
-        if (!request_mem_region(res->start, res_len(res), res->name)) {
+        if (!request_mem_region(res->start, resource_size(res), res->name)) {
                 ret = -ENOMEM;
                 goto e_print;
         }
@@ -161,13 +159,13 @@ static int __devinit i2c_pca_pf_probe(struct platform_device *pdev)
 
         init_waitqueue_head(&i2c->wait);
 
-        i2c->reg_base = ioremap(res->start, res_len(res));
+        i2c->reg_base = ioremap(res->start, resource_size(res));
         if (!i2c->reg_base) {
                 ret = -ENOMEM;
                 goto e_remap;
         }
         i2c->io_base = res->start;
-        i2c->io_size = res_len(res);
+        i2c->io_size = resource_size(res);
         i2c->irq = irq;
 
         i2c->adap.nr = pdev->id >= 0 ? pdev->id : 0;
@@ -250,7 +248,7 @@ e_reqirq:
 e_remap:
         kfree(i2c);
 e_alloc:
-        release_mem_region(res->start, res_len(res));
+        release_mem_region(res->start, resource_size(res));
 e_print:
         printk(KERN_ERR "Registering PCA9564/PCA9665 FAILED! (%d)\n", ret);
         return ret;
diff --git a/drivers/i2c/busses/i2c-pmcmsp.c b/drivers/i2c/busses/i2c-pmcmsp.c
index 0bdb2d7f0570..7b57d5f267e1 100644
--- a/drivers/i2c/busses/i2c-pmcmsp.c
+++ b/drivers/i2c/busses/i2c-pmcmsp.c
@@ -283,7 +283,7 @@ static int __devinit pmcmsptwi_probe(struct platform_device *pldev)
         }
 
         /* reserve the memory region */
-        if (!request_mem_region(res->start, res->end - res->start + 1,
+        if (!request_mem_region(res->start, resource_size(res),
                                 pldev->name)) {
                 dev_err(&pldev->dev,
                         "Unable to get memory/io address region 0x%08x\n",
@@ -294,7 +294,7 @@ static int __devinit pmcmsptwi_probe(struct platform_device *pldev)
 
         /* remap the memory */
         pmcmsptwi_data.iobase = ioremap_nocache(res->start,
-                                                res->end - res->start + 1);
+                                                resource_size(res));
         if (!pmcmsptwi_data.iobase) {
                 dev_err(&pldev->dev,
                         "Unable to ioremap address 0x%08x\n", res->start);
@@ -360,7 +360,7 @@ ret_unmap:
         iounmap(pmcmsptwi_data.iobase);
 
 ret_unreserve:
-        release_mem_region(res->start, res->end - res->start + 1);
+        release_mem_region(res->start, resource_size(res));
 
 ret_err:
         return rc;
@@ -385,7 +385,7 @@ static int __devexit pmcmsptwi_remove(struct platform_device *pldev)
         iounmap(pmcmsptwi_data.iobase);
 
         res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
-        release_mem_region(res->start, res->end - res->start + 1);
+        release_mem_region(res->start, resource_size(res));
 
         return 0;
 }
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 035a6c7e59df..762e1e530882 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -993,7 +993,6 @@ static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
         .functionality  = i2c_pxa_functionality,
 };
 
-#define res_len(r)              ((r)->end - (r)->start + 1)
 static int i2c_pxa_probe(struct platform_device *dev)
 {
         struct pxa_i2c *i2c;
@@ -1008,7 +1007,7 @@ static int i2c_pxa_probe(struct platform_device *dev)
         if (res == NULL || irq < 0)
                 return -ENODEV;
 
-        if (!request_mem_region(res->start, res_len(res), res->name))
+        if (!request_mem_region(res->start, resource_size(res), res->name))
                 return -ENOMEM;
 
         i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
@@ -1038,7 +1037,7 @@ static int i2c_pxa_probe(struct platform_device *dev)
                 goto eclk;
         }
 
-        i2c->reg_base = ioremap(res->start, res_len(res));
+        i2c->reg_base = ioremap(res->start, resource_size(res));
         if (!i2c->reg_base) {
                 ret = -EIO;
                 goto eremap;
@@ -1046,7 +1045,7 @@ static int i2c_pxa_probe(struct platform_device *dev)
         i2c->reg_shift = REG_SHIFT(id->driver_data);
 
         i2c->iobase = res->start;
-        i2c->iosize = res_len(res);
+        i2c->iosize = resource_size(res);
 
         i2c->irq = irq;
 
@@ -1110,7 +1109,7 @@ eremap:
 eclk:
         kfree(i2c);
 emalloc:
-        release_mem_region(res->start, res_len(res));
+        release_mem_region(res->start, resource_size(res));
         return ret;
 }
 
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 079a312d36fd..8f42a4536cdf 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -828,7 +828,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
                 goto err_clk;
         }
 
-        i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
+        i2c->ioarea = request_mem_region(res->start, resource_size(res),
                                          pdev->name);
 
         if (i2c->ioarea == NULL) {
@@ -837,7 +837,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
                 goto err_clk;
         }
 
-        i2c->regs = ioremap(res->start, (res->end-res->start)+1);
+        i2c->regs = ioremap(res->start, resource_size(res));
 
         if (i2c->regs == NULL) {
                 dev_err(&pdev->dev, "cannot map IO\n");
diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
new file mode 100644
index 000000000000..182e711318ba
--- /dev/null
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -0,0 +1,1029 @@
+/*
+ * Copyright (C) 2007-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * ST DDC I2C master mode driver, used in e.g. U300 series platforms.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
+ */
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+/* the name of this kernel module */
+#define NAME "stu300"
+
+/* CR (Control Register) 8bit (R/W) */
+#define I2C_CR                                  (0x00000000)
+#define I2C_CR_RESET_VALUE                      (0x00)
+#define I2C_CR_RESET_UMASK                      (0x00)
+#define I2C_CR_DDC1_ENABLE                      (0x80)
+#define I2C_CR_TRANS_ENABLE                     (0x40)
+#define I2C_CR_PERIPHERAL_ENABLE                (0x20)
+#define I2C_CR_DDC2B_ENABLE                     (0x10)
+#define I2C_CR_START_ENABLE                     (0x08)
+#define I2C_CR_ACK_ENABLE                       (0x04)
+#define I2C_CR_STOP_ENABLE                      (0x02)
+#define I2C_CR_INTERRUPT_ENABLE                 (0x01)
+/* SR1 (Status Register 1) 8bit (R/-) */
+#define I2C_SR1                                 (0x00000004)
+#define I2C_SR1_RESET_VALUE                     (0x00)
+#define I2C_SR1_RESET_UMASK                     (0x00)
+#define I2C_SR1_EVF_IND                         (0x80)
+#define I2C_SR1_ADD10_IND                       (0x40)
+#define I2C_SR1_TRA_IND                         (0x20)
+#define I2C_SR1_BUSY_IND                        (0x10)
+#define I2C_SR1_BTF_IND                         (0x08)
+#define I2C_SR1_ADSL_IND                        (0x04)
+#define I2C_SR1_MSL_IND                         (0x02)
+#define I2C_SR1_SB_IND                          (0x01)
+/* SR2 (Status Register 2) 8bit (R/-) */
+#define I2C_SR2                                 (0x00000008)
+#define I2C_SR2_RESET_VALUE                     (0x00)
+#define I2C_SR2_RESET_UMASK                     (0x40)
+#define I2C_SR2_MASK                            (0xBF)
+#define I2C_SR2_SCLFAL_IND                      (0x80)
+#define I2C_SR2_ENDAD_IND                       (0x20)
+#define I2C_SR2_AF_IND                          (0x10)
+#define I2C_SR2_STOPF_IND                       (0x08)
+#define I2C_SR2_ARLO_IND                        (0x04)
+#define I2C_SR2_BERR_IND                        (0x02)
+#define I2C_SR2_DDC2BF_IND                      (0x01)
+/* CCR (Clock Control Register) 8bit (R/W) */
+#define I2C_CCR                                 (0x0000000C)
+#define I2C_CCR_RESET_VALUE                     (0x00)
+#define I2C_CCR_RESET_UMASK                     (0x00)
+#define I2C_CCR_MASK                            (0xFF)
+#define I2C_CCR_FMSM                            (0x80)
+#define I2C_CCR_CC_MASK                         (0x7F)
+/* OAR1 (Own Address Register 1) 8bit (R/W) */
+#define I2C_OAR1                                (0x00000010)
+#define I2C_OAR1_RESET_VALUE                    (0x00)
+#define I2C_OAR1_RESET_UMASK                    (0x00)
+#define I2C_OAR1_ADD_MASK                       (0xFF)
+/* OAR2 (Own Address Register 2) 8bit (R/W) */
+#define I2C_OAR2                                (0x00000014)
+#define I2C_OAR2_RESET_VALUE                    (0x40)
+#define I2C_OAR2_RESET_UMASK                    (0x19)
+#define I2C_OAR2_MASK                           (0xE6)
+#define I2C_OAR2_FR_25_10MHZ                    (0x00)
+#define I2C_OAR2_FR_10_1667MHZ                  (0x20)
+#define I2C_OAR2_FR_1667_2667MHZ                (0x40)
+#define I2C_OAR2_FR_2667_40MHZ                  (0x60)
+#define I2C_OAR2_FR_40_5333MHZ                  (0x80)
+#define I2C_OAR2_FR_5333_66MHZ                  (0xA0)
+#define I2C_OAR2_FR_66_80MHZ                    (0xC0)
+#define I2C_OAR2_FR_80_100MHZ                   (0xE0)
+#define I2C_OAR2_FR_MASK                        (0xE0)
+#define I2C_OAR2_ADD_MASK                       (0x06)
+/* DR (Data Register) 8bit (R/W) */
+#define I2C_DR                                  (0x00000018)
+#define I2C_DR_RESET_VALUE                      (0x00)
+#define I2C_DR_RESET_UMASK                      (0xFF)
+#define I2C_DR_D_MASK                           (0xFF)
+/* ECCR (Extended Clock Control Register) 8bit (R/W) */
+#define I2C_ECCR                                (0x0000001C)
+#define I2C_ECCR_RESET_VALUE                    (0x00)
+#define I2C_ECCR_RESET_UMASK                    (0xE0)
+#define I2C_ECCR_MASK                           (0x1F)
+#define I2C_ECCR_CC_MASK                        (0x1F)
+
+/*
+ * These events are more or less responses to commands
+ * sent into the hardware, presumably reflecting the state
+ * of an internal state machine.
+ */
+enum stu300_event {
+        STU300_EVENT_NONE = 0,
+        STU300_EVENT_1,
+        STU300_EVENT_2,
+        STU300_EVENT_3,
+        STU300_EVENT_4,
+        STU300_EVENT_5,
+        STU300_EVENT_6,
+        STU300_EVENT_7,
+        STU300_EVENT_8,
+        STU300_EVENT_9
+};
+
+enum stu300_error {
+        STU300_ERROR_NONE = 0,
+        STU300_ERROR_ACKNOWLEDGE_FAILURE,
+        STU300_ERROR_BUS_ERROR,
+        STU300_ERROR_ARBITRATION_LOST
+};
+
+/* timeout waiting for the controller to respond */
+#define STU300_TIMEOUT (msecs_to_jiffies(1000))
+
+/*
+ * The number of address send athemps tried before giving up.
+ * If the first one failes it seems like 5 to 8 attempts are required.
+ */
+#define NUM_ADDR_RESEND_ATTEMPTS 10
+
+/* I2C clock speed, in Hz 0-400kHz*/
+static unsigned int scl_frequency = 100000;
+module_param(scl_frequency, uint,  0644);
+
+/**
+ * struct stu300_dev - the stu300 driver state holder
+ * @pdev: parent platform device
+ * @adapter: corresponding I2C adapter
+ * @phybase: location of I/O area in memory
+ * @physize: size of I/O area in memory
+ * @clk: hardware block clock
+ * @irq: assigned interrupt line
+ * @cmd_issue_lock: this locks the following cmd_ variables
+ * @cmd_complete: acknowledge completion for an I2C command
+ * @cmd_event: expected event coming in as a response to a command
+ * @cmd_err: error code as response to a command
+ * @speed: current bus speed in Hz
+ * @msg_index: index of current message
+ * @msg_len: length of current message
+ */
+struct stu300_dev {
+        struct platform_device  *pdev;
+        struct i2c_adapter      adapter;
+        resource_size_t         phybase;
+        resource_size_t         physize;
+        void __iomem            *virtbase;
+        struct clk              *clk;
+        int                     irq;
+        spinlock_t              cmd_issue_lock;
+        struct completion       cmd_complete;
+        enum stu300_event       cmd_event;
+        enum stu300_error       cmd_err;
+        unsigned int            speed;
+        int                     msg_index;
+        int                     msg_len;
+};
+
+/* Local forward function declarations */
+static int stu300_init_hw(struct stu300_dev *dev);
+
+/*
+ * The block needs writes in both MSW and LSW in order
+ * for all data lines to reach their destination.
+ */
+static inline void stu300_wr8(u32 value, void __iomem *address)
+{
+        writel((value << 16) | value, address);
+}
+
+/*
+ * This merely masks off the duplicates which appear
+ * in bytes 1-3. You _MUST_ use 32-bit bus access on this
+ * device, else it will not work.
+ */
+static inline u32 stu300_r8(void __iomem *address)
+{
+        return readl(address) & 0x000000FFU;
+}
+
+/*
+ * Tells whether a certain event or events occurred in
+ * response to a command. The events represent states in
+ * the internal state machine of the hardware. The events
+ * are not very well described in the hardware
+ * documentation and can only be treated as abstract state
+ * machine states.
+ *
+ * @ret 0 = event has not occurred, any other value means
+ * the event occurred.
+ */
+static int stu300_event_occurred(struct stu300_dev *dev,
+                                   enum stu300_event mr_event) {
+        u32 status1;
+        u32 status2;
+
+        /* What event happened? */
+        status1 = stu300_r8(dev->virtbase + I2C_SR1);
+        if (!(status1 & I2C_SR1_EVF_IND))
+                /* No event at all */
+                return 0;
+        status2 = stu300_r8(dev->virtbase + I2C_SR2);
+
+        switch (mr_event) {
+        case STU300_EVENT_1:
+                if (status1 & I2C_SR1_ADSL_IND)
+                        return 1;
+                break;
+        case STU300_EVENT_2:
+        case STU300_EVENT_3:
+        case STU300_EVENT_7:
+        case STU300_EVENT_8:
+                if (status1 & I2C_SR1_BTF_IND) {
+                        if (status2 & I2C_SR2_AF_IND)
+                                dev->cmd_err = STU300_ERROR_ACKNOWLEDGE_FAILURE;
+                        else if (status2 & I2C_SR2_BERR_IND)
+                                dev->cmd_err = STU300_ERROR_BUS_ERROR;
+                        return 1;
+                }
+                break;
+        case STU300_EVENT_4:
+                if (status2 & I2C_SR2_STOPF_IND)
+                        return 1;
+                break;
+        case STU300_EVENT_5:
+                if (status1 & I2C_SR1_SB_IND)
+                        /* Clear start bit */
+                        return 1;
+                break;
+        case STU300_EVENT_6:
+                if (status2 & I2C_SR2_ENDAD_IND) {
+                        /* First check for any errors */
+                        if (status2 & I2C_SR2_AF_IND)
+                                dev->cmd_err = STU300_ERROR_ACKNOWLEDGE_FAILURE;
+                        return 1;
+                }
+                break;
+        case STU300_EVENT_9:
+                if (status1 & I2C_SR1_ADD10_IND)
+                        return 1;
+                break;
+        default:
+                break;
+        }
+        if (status2 & I2C_SR2_ARLO_IND)
+                dev->cmd_err = STU300_ERROR_ARBITRATION_LOST;
+        return 0;
+}
+
+static irqreturn_t stu300_irh(int irq, void *data)
+{
+        struct stu300_dev *dev = data;
+        int res;
+
+        /* See if this was what we were waiting for */
+        spin_lock(&dev->cmd_issue_lock);
+        if (dev->cmd_event != STU300_EVENT_NONE) {
+                res = stu300_event_occurred(dev, dev->cmd_event);
+                if (res || dev->cmd_err != STU300_ERROR_NONE) {
+                        u32 val;
+
+                        complete(&dev->cmd_complete);
+                        /* Block any multiple interrupts */
+                        val = stu300_r8(dev->virtbase + I2C_CR);
+                        val &= ~I2C_CR_INTERRUPT_ENABLE;
+                        stu300_wr8(val, dev->virtbase + I2C_CR);
+                }
+        }
+        spin_unlock(&dev->cmd_issue_lock);
+        return IRQ_HANDLED;
+}
+
+/*
+ * Sends a command and then waits for the bits masked by *flagmask*
+ * to go high or low by IRQ awaiting.
+ */
+static int stu300_start_and_await_event(struct stu300_dev *dev,
+                                          u8 cr_value,
+                                          enum stu300_event mr_event)
+{
+        int ret;
+
+        if (unlikely(irqs_disabled())) {
+                /* TODO: implement polling for this case if need be. */
+                WARN(1, "irqs are disabled, cannot poll for event\n");
+                return -EIO;
+        }
+
+        /* Lock command issue, fill in an event we wait for */
+        spin_lock_irq(&dev->cmd_issue_lock);
+        init_completion(&dev->cmd_complete);
+        dev->cmd_err = STU300_ERROR_NONE;
+        dev->cmd_event = mr_event;
+        spin_unlock_irq(&dev->cmd_issue_lock);
+
+        /* Turn on interrupt, send command and wait. */
+        cr_value |= I2C_CR_INTERRUPT_ENABLE;
+        stu300_wr8(cr_value, dev->virtbase + I2C_CR);
+        ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
+                                                        STU300_TIMEOUT);
+
+        if (ret < 0) {
+                dev_err(&dev->pdev->dev,
+                       "wait_for_completion_interruptible_timeout() "
+                       "returned %d waiting for event %04x\n", ret, mr_event);
+                return ret;
+        }
+
+        if (ret == 0) {
+                dev_err(&dev->pdev->dev, "controller timed out "
+                       "waiting for event %d, reinit hardware\n", mr_event);
+                (void) stu300_init_hw(dev);
+                return -ETIMEDOUT;
+        }
+
+        if (dev->cmd_err != STU300_ERROR_NONE) {
+                dev_err(&dev->pdev->dev, "controller (start) "
+                       "error %d waiting for event %d, reinit hardware\n",
+                       dev->cmd_err, mr_event);
+                (void) stu300_init_hw(dev);
+                return -EIO;
+        }
+
+        return 0;
+}
+
+/*
+ * This waits for a flag to be set, if it is not set on entry, an interrupt is
+ * configured to wait for the flag using a completion.
+ */
+static int stu300_await_event(struct stu300_dev *dev,
+                                enum stu300_event mr_event)
+{
+        int ret;
+        u32 val;
+
+        if (unlikely(irqs_disabled())) {
+                /* TODO: implement polling for this case if need be. */
+                dev_err(&dev->pdev->dev, "irqs are disabled on this "
+                        "system!\n");
+                return -EIO;
+        }
+
+        /* Is it already here? */
+        spin_lock_irq(&dev->cmd_issue_lock);
+        dev->cmd_err = STU300_ERROR_NONE;
+        if (stu300_event_occurred(dev, mr_event)) {
+                spin_unlock_irq(&dev->cmd_issue_lock);
+                goto exit_await_check_err;
+        }
+        init_completion(&dev->cmd_complete);
+        dev->cmd_err = STU300_ERROR_NONE;
+        dev->cmd_event = mr_event;
+
+        /* Turn on the I2C interrupt for current operation */
+        val = stu300_r8(dev->virtbase + I2C_CR);
+        val |= I2C_CR_INTERRUPT_ENABLE;
+        stu300_wr8(val, dev->virtbase + I2C_CR);
+
+        /* Twice paranoia (possible HW glitch) */
+        stu300_wr8(val, dev->virtbase + I2C_CR);
+
+        /* Check again: is it already here? */
+        if (unlikely(stu300_event_occurred(dev, mr_event))) {
+                /* Disable IRQ again. */
+                val &= ~I2C_CR_INTERRUPT_ENABLE;
+                stu300_wr8(val, dev->virtbase + I2C_CR);
+                spin_unlock_irq(&dev->cmd_issue_lock);
+                goto exit_await_check_err;
+        }
+
+        /* Unlock the command block and wait for the event to occur */
+        spin_unlock_irq(&dev->cmd_issue_lock);
+        ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
+                                                        STU300_TIMEOUT);
+
+        if (ret < 0) {
+                dev_err(&dev->pdev->dev,
+                       "wait_for_completion_interruptible_timeout()"
+                       "returned %d waiting for event %04x\n", ret, mr_event);
+                return ret;
+        }
+
+        if (ret == 0) {
+                if (mr_event != STU300_EVENT_6) {
+                        dev_err(&dev->pdev->dev, "controller "
+                                "timed out waiting for event %d, reinit "
+                                "hardware\n", mr_event);
+                        (void) stu300_init_hw(dev);
+                }
+                return -ETIMEDOUT;
+        }
+
+ exit_await_check_err:
+        if (dev->cmd_err != STU300_ERROR_NONE) {
+                if (mr_event != STU300_EVENT_6) {
+                        dev_err(&dev->pdev->dev, "controller "
+                                "error (await_event) %d waiting for event %d, "
+                               "reinit hardware\n", dev->cmd_err, mr_event);
+                        (void) stu300_init_hw(dev);
+                }
+                return -EIO;
+        }
+
+        return 0;
+}
+
+/*
+ * Waits for the busy bit to go low by repeated polling.
+ */
+#define BUSY_RELEASE_ATTEMPTS 10
+static int stu300_wait_while_busy(struct stu300_dev *dev)
+{
+        unsigned long timeout;
+        int i;
+
+        for (i = 0; i < BUSY_RELEASE_ATTEMPTS; i++) {
+                timeout = jiffies + STU300_TIMEOUT;
+
+                while (!time_after(jiffies, timeout)) {
+                        /* Is not busy? */
+                        if ((stu300_r8(dev->virtbase + I2C_SR1) &
+                             I2C_SR1_BUSY_IND) == 0)
+                                return 0;
+                        msleep(1);
+                }
+
+                dev_err(&dev->pdev->dev, "transaction timed out "
+                        "waiting for device to be free (not busy). "
+                       "Attempt: %d\n", i+1);
+
+                dev_err(&dev->pdev->dev, "base address = "
+                        "0x%08x, reinit hardware\n", (u32) dev->virtbase);
+
+                (void) stu300_init_hw(dev);
+        }
+
+        dev_err(&dev->pdev->dev, "giving up after %d attempts "
+                "to reset the bus.\n",  BUSY_RELEASE_ATTEMPTS);
+
+        return -ETIMEDOUT;
+}
+
+struct stu300_clkset {
+        unsigned long rate;
+        u32 setting;
+};
+
+static const struct stu300_clkset stu300_clktable[] = {
+        { 0, 0xFFU },
+        { 2500000, I2C_OAR2_FR_25_10MHZ },
+        { 10000000, I2C_OAR2_FR_10_1667MHZ },
+        { 16670000, I2C_OAR2_FR_1667_2667MHZ },
+        { 26670000, I2C_OAR2_FR_2667_40MHZ },
+        { 40000000, I2C_OAR2_FR_40_5333MHZ },
+        { 53330000, I2C_OAR2_FR_5333_66MHZ },
+        { 66000000, I2C_OAR2_FR_66_80MHZ },
+        { 80000000, I2C_OAR2_FR_80_100MHZ },
+        { 100000000, 0xFFU },
+};
+
+static int stu300_set_clk(struct stu300_dev *dev, unsigned long clkrate)
+{
+
+        u32 val;
+        int i = 0;
+
+        /* Locate the apropriate clock setting */
+        while (i < ARRAY_SIZE(stu300_clktable) &&
+               stu300_clktable[i].rate < clkrate)
+                i++;
+
+        if (stu300_clktable[i].setting == 0xFFU) {
+                dev_err(&dev->pdev->dev, "too %s clock rate requested "
+                        "(%lu Hz).\n", i ? "high" : "low", clkrate);
+                return -EINVAL;
+        }
+
+        stu300_wr8(stu300_clktable[i].setting,
+                   dev->virtbase + I2C_OAR2);
+
+        dev_dbg(&dev->pdev->dev, "Clock rate %lu Hz, I2C bus speed %d Hz "
+                "virtbase %p\n", clkrate, dev->speed, dev->virtbase);
+
+        if (dev->speed > 100000)
+                /* Fast Mode I2C */
+                val = ((clkrate/dev->speed)-9)/3;
+        else
+                /* Standard Mode I2C */
+                val = ((clkrate/dev->speed)-7)/2;
+
+        /* According to spec the divider must be > 2 */
+        if (val < 0x002) {
+                dev_err(&dev->pdev->dev, "too low clock rate (%lu Hz).\n",
+                        clkrate);
+                return -EINVAL;
+        }
+
+        /* We have 12 bits clock divider only! */
+        if (val & 0xFFFFF000U) {
+                dev_err(&dev->pdev->dev, "too high clock rate (%lu Hz).\n",
+                        clkrate);
+                return -EINVAL;
+        }
+
+        if (dev->speed > 100000) {
+                /* CC6..CC0 */
+                stu300_wr8((val & I2C_CCR_CC_MASK) | I2C_CCR_FMSM,
+                           dev->virtbase + I2C_CCR);
+                dev_dbg(&dev->pdev->dev, "set clock divider to 0x%08x, "
+                        "Fast Mode I2C\n", val);
+        } else {
+                /* CC6..CC0 */
+                stu300_wr8((val & I2C_CCR_CC_MASK),
+                           dev->virtbase + I2C_CCR);
+                dev_dbg(&dev->pdev->dev, "set clock divider to "
+                        "0x%08x, Standard Mode I2C\n", val);
+        }
+
+        /* CC11..CC7 */
+        stu300_wr8(((val >> 7) & 0x1F),
+                   dev->virtbase + I2C_ECCR);
+
+        return 0;
+}
+
+
+static int stu300_init_hw(struct stu300_dev *dev)
+{
+        u32 dummy;
+        unsigned long clkrate;
+        int ret;
+
+        /* Disable controller */
+        stu300_wr8(0x00, dev->virtbase + I2C_CR);
+        /*
+         * Set own address to some default value (0x00).
+         * We do not support slave mode anyway.
+         */
+        stu300_wr8(0x00, dev->virtbase + I2C_OAR1);
+        /*
+         * The I2C controller only operates properly in 26 MHz but we
+         * program this driver as if we didn't know. This will also set the two
+         * high bits of the own address to zero as well.
+         * There is no known hardware issue with running in 13 MHz
+         * However, speeds over 200 kHz are not used.
+         */
+        clkrate = clk_get_rate(dev->clk);
+        ret = stu300_set_clk(dev, clkrate);
+        if (ret)
+                return ret;
+        /*
+         * Enable block, do it TWICE (hardware glitch)
+         * Setting bit 7 can enable DDC mode. (Not used currently.)
+         */
+        stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
+                                  dev->virtbase + I2C_CR);
+        stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
+                                  dev->virtbase + I2C_CR);
+        /* Make a dummy read of the status register SR1 & SR2 */
+        dummy = stu300_r8(dev->virtbase + I2C_SR2);
+        dummy = stu300_r8(dev->virtbase + I2C_SR1);
+
+        return 0;
+}
+
+
+
+/* Send slave address. */
+static int stu300_send_address(struct stu300_dev *dev,
+                                 struct i2c_msg *msg, int resend)
+{
+        u32 val;
+        int ret;
+
+        if (msg->flags & I2C_M_TEN)
+                /* This is probably how 10 bit addresses look */
+                val = (0xf0 | (((u32) msg->addr & 0x300) >> 7)) &
+                        I2C_DR_D_MASK;
+        else
+                val = ((msg->addr << 1) & I2C_DR_D_MASK);
+
+        if (msg->flags & I2C_M_RD) {
+                /* This is the direction bit */
+                val |= 0x01;
+                if (resend)
+                        dev_dbg(&dev->pdev->dev, "read resend\n");
+        } else if (resend)
+                dev_dbg(&dev->pdev->dev, "write resend\n");
+        stu300_wr8(val, dev->virtbase + I2C_DR);
+
+        /* For 10bit addressing, await 10bit request (EVENT 9) */
+        if (msg->flags & I2C_M_TEN) {
+                ret = stu300_await_event(dev, STU300_EVENT_9);
+                /*
+                 * The slave device wants a 10bit address, send the rest
+                 * of the bits (the LSBits)
+                 */
+                val = msg->addr & I2C_DR_D_MASK;
+                /* This clears "event 9" */
+                stu300_wr8(val, dev->virtbase + I2C_DR);
+                if (ret != 0)
+                        return ret;
+        }
+        /* FIXME: Why no else here? two events for 10bit?
+         * Await event 6 (normal) or event 9 (10bit)
+         */
+
+        if (resend)
+                dev_dbg(&dev->pdev->dev, "await event 6\n");
+        ret = stu300_await_event(dev, STU300_EVENT_6);
+
+        /*
+         * Clear any pending EVENT 6 no matter what happend during
+         * await_event.
+         */
+        val = stu300_r8(dev->virtbase + I2C_CR);
+        val |= I2C_CR_PERIPHERAL_ENABLE;
+        stu300_wr8(val, dev->virtbase + I2C_CR);
+
+        return ret;
+}
+
+static int stu300_xfer_msg(struct i2c_adapter *adap,
+                             struct i2c_msg *msg, int stop)
+{
+        u32 cr;
+        u32 val;
+        u32 i;
+        int ret;
+        int attempts = 0;
+        struct stu300_dev *dev = i2c_get_adapdata(adap);
+
+
+        clk_enable(dev->clk);
+
+        /* Remove this if (0) to trace each and every message. */
+        if (0) {
+                dev_dbg(&dev->pdev->dev, "I2C message to: 0x%04x, len: %d, "
+                        "flags: 0x%04x, stop: %d\n",
+                        msg->addr, msg->len, msg->flags, stop);
+        }
+
+        /* Zero-length messages are not supported by this hardware */
+        if (msg->len == 0) {
+                ret = -EINVAL;
+                goto exit_disable;
+        }
+
+        /*
+         * For some reason, sending the address sometimes fails when running
+         * on  the 13 MHz clock. No interrupt arrives. This is a work around,
+         * which tries to restart and send the address up to 10 times before
+         * really giving up. Usually 5 to 8 attempts are enough.
+         */
+        do {
+                if (attempts)
+                        dev_dbg(&dev->pdev->dev, "wait while busy\n");
+                /* Check that the bus is free, or wait until some timeout */
+                ret = stu300_wait_while_busy(dev);
+                if (ret != 0)
+                        goto exit_disable;
+
+                if (attempts)
+                        dev_dbg(&dev->pdev->dev, "re-int hw\n");
+                /*
+                 * According to ST, there is no problem if the clock is
+                 * changed between 13 and 26 MHz during a transfer.
+                 */
+                ret = stu300_init_hw(dev);
+                if (ret)
+                        goto exit_disable;
+
+                /* Send a start condition */
+                cr = I2C_CR_PERIPHERAL_ENABLE;
+                /* Setting the START bit puts the block in master mode */
+                if (!(msg->flags & I2C_M_NOSTART))
+                        cr |= I2C_CR_START_ENABLE;
+                if ((msg->flags & I2C_M_RD) && (msg->len > 1))
+                        /* On read more than 1 byte, we need ack. */
+                        cr |= I2C_CR_ACK_ENABLE;
+                /* Check that it gets through */
+                if (!(msg->flags & I2C_M_NOSTART)) {
+                        if (attempts)
+                                dev_dbg(&dev->pdev->dev, "send start event\n");
+                        ret = stu300_start_and_await_event(dev, cr,
+                                                             STU300_EVENT_5);
+                }
+
+                if (attempts)
+                        dev_dbg(&dev->pdev->dev, "send address\n");
+
+                if (ret == 0)
+                        /* Send address */
+                        ret = stu300_send_address(dev, msg, attempts != 0);
+
+                if (ret != 0) {
+                        attempts++;
+                        dev_dbg(&dev->pdev->dev, "failed sending address, "
+                                "retrying. Attempt: %d msg_index: %d/%d\n",
+                               attempts, dev->msg_index, dev->msg_len);
+                }
+
+        } while (ret != 0 && attempts < NUM_ADDR_RESEND_ATTEMPTS);
+
+        if (attempts < NUM_ADDR_RESEND_ATTEMPTS && attempts > 0) {
+                dev_dbg(&dev->pdev->dev, "managed to get address "
+                       "through after %d attempts\n", attempts);
+        } else if (attempts == NUM_ADDR_RESEND_ATTEMPTS) {
+                dev_dbg(&dev->pdev->dev, "I give up, tried %d times "
+                       "to resend address.\n",
+                       NUM_ADDR_RESEND_ATTEMPTS);
+                goto exit_disable;
+        }
+
+        if (msg->flags & I2C_M_RD) {
+                /* READ: we read the actual bytes one at a time */
+                for (i = 0; i < msg->len; i++) {
+                        if (i == msg->len-1) {
+                                /*
+                                 * Disable ACK and set STOP condition before
+                                 * reading last byte
+                                 */
+                                val = I2C_CR_PERIPHERAL_ENABLE;
+
+                                if (stop)
+                                        val |= I2C_CR_STOP_ENABLE;
+
+                                stu300_wr8(val,
+                                           dev->virtbase + I2C_CR);
+                        }
+                        /* Wait for this byte... */
+                        ret = stu300_await_event(dev, STU300_EVENT_7);
+                        if (ret != 0)
+                                goto exit_disable;
+                        /* This clears event 7 */
+                        msg->buf[i] = (u8) stu300_r8(dev->virtbase + I2C_DR);
+                }
+        } else {
+                /* WRITE: we send the actual bytes one at a time */
+                for (i = 0; i < msg->len; i++) {
+                        /* Write the byte */
+                        stu300_wr8(msg->buf[i],
+                                   dev->virtbase + I2C_DR);
+                        /* Check status */
+                        ret = stu300_await_event(dev, STU300_EVENT_8);
+                        /* Next write to DR will clear event 8 */
+                        if (ret != 0) {
+                                dev_err(&dev->pdev->dev, "error awaiting "
+                                       "event 8 (%d)\n", ret);
+                                goto exit_disable;
+                        }
+                }
+                /* Check NAK */
+                if (!(msg->flags & I2C_M_IGNORE_NAK)) {
+                        if (stu300_r8(dev->virtbase + I2C_SR2) &
+                            I2C_SR2_AF_IND) {
+                                dev_err(&dev->pdev->dev, "I2C payload "
+                                       "send returned NAK!\n");
+                                ret = -EIO;
+                                goto exit_disable;
+                        }
+                }
+                if (stop) {
+                        /* Send stop condition */
+                        val = I2C_CR_PERIPHERAL_ENABLE;
+                        val |= I2C_CR_STOP_ENABLE;
+                        stu300_wr8(val, dev->virtbase + I2C_CR);
+                }
+        }
+
+        /* Check that the bus is free, or wait until some timeout occurs */
+        ret = stu300_wait_while_busy(dev);
+        if (ret != 0) {
+                dev_err(&dev->pdev->dev, "timout waiting for transfer "
+                       "to commence.\n");
+                goto exit_disable;
+        }
+
+        /* Dummy read status registers */
+        val = stu300_r8(dev->virtbase + I2C_SR2);
+        val = stu300_r8(dev->virtbase + I2C_SR1);
+        ret = 0;
+
+ exit_disable:
+        /* Disable controller */
+        stu300_wr8(0x00, dev->virtbase + I2C_CR);
+        clk_disable(dev->clk);
+        return ret;
+}
+
+static int stu300_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+                         int num)
+{
+        int ret = -1;
+        int i;
+        struct stu300_dev *dev = i2c_get_adapdata(adap);
+        dev->msg_len = num;
+        for (i = 0; i < num; i++) {
+                /*
+                 * Another driver appears to send stop for each message,
+                 * here we only do that for the last message. Possibly some
+                 * peripherals require this behaviour, then their drivers
+                 * have to send single messages in order to get "stop" for
+                 * each message.
+                 */
+                dev->msg_index = i;
+
+                ret = stu300_xfer_msg(adap, &msgs[i], (i == (num - 1)));
+                if (ret != 0) {
+                        num = ret;
+                        break;
+                }
+        }
+
+        return num;
+}
+
+static u32 stu300_func(struct i2c_adapter *adap)
+{
+        /* This is the simplest thing you can think of... */
+        return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
+}
+
+static const struct i2c_algorithm stu300_algo = {
+        .master_xfer    = stu300_xfer,
+        .functionality  = stu300_func,
+};
+
+static int __init
+stu300_probe(struct platform_device *pdev)
+{
+        struct stu300_dev *dev;
+        struct i2c_adapter *adap;
+        struct resource *res;
+        int bus_nr;
+        int ret = 0;
+
+        dev = kzalloc(sizeof(struct stu300_dev), GFP_KERNEL);
+        if (!dev) {
+                dev_err(&pdev->dev, "could not allocate device struct\n");
+                ret = -ENOMEM;
+                goto err_no_devmem;
+        }
+
+        bus_nr = pdev->id;
+        dev->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR(dev->clk)) {
+                ret = PTR_ERR(dev->clk);
+                dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
+                goto err_no_clk;
+        }
+
+        dev->pdev = pdev;
+        platform_set_drvdata(pdev, dev);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                ret = -ENOENT;
+                goto err_no_resource;
+        }
+
+        dev->phybase = res->start;
+        dev->physize = resource_size(res);
+
+        if (request_mem_region(dev->phybase, dev->physize,
+                               NAME " I/O Area") == NULL) {
+                ret = -EBUSY;
+                goto err_no_ioregion;
+        }
+
+        dev->virtbase = ioremap(dev->phybase, dev->physize);
+        dev_dbg(&pdev->dev, "initialize bus device I2C%d on virtual "
+                "base %p\n", bus_nr, dev->virtbase);
+        if (!dev->virtbase) {
+                ret = -ENOMEM;
+                goto err_no_ioremap;
+        }
+
+        dev->irq = platform_get_irq(pdev, 0);
+        if (request_irq(dev->irq, stu300_irh, IRQF_DISABLED,
+                        NAME, dev)) {
+                ret = -EIO;
+                goto err_no_irq;
+        }
+
+        dev->speed = scl_frequency;
+
+        clk_enable(dev->clk);
+        ret = stu300_init_hw(dev);
+        clk_disable(dev->clk);
+
+        if (ret != 0) {
+                dev_err(&dev->pdev->dev, "error initializing hardware.\n");
+                goto err_init_hw;
+        }
+
+        /* IRQ event handling initialization */
+        spin_lock_init(&dev->cmd_issue_lock);
+        dev->cmd_event = STU300_EVENT_NONE;
+        dev->cmd_err = STU300_ERROR_NONE;
+
+        adap = &dev->adapter;
+        adap->owner = THIS_MODULE;
+        /* DDC class but actually often used for more generic I2C */
+        adap->class = I2C_CLASS_DDC;
+        strncpy(adap->name, "ST Microelectronics DDC I2C adapter",
+                sizeof(adap->name));
+        adap->nr = bus_nr;
+        adap->algo = &stu300_algo;
+        adap->dev.parent = &pdev->dev;
+        i2c_set_adapdata(adap, dev);
+
+        /* i2c device drivers may be active on return from add_adapter() */
+        ret = i2c_add_numbered_adapter(adap);
+        if (ret) {
+                dev_err(&dev->pdev->dev, "failure adding ST Micro DDC "
+                       "I2C adapter\n");
+                goto err_add_adapter;
+        }
+        return 0;
+
+ err_add_adapter:
+ err_init_hw:
+        free_irq(dev->irq, dev);
+ err_no_irq:
+        iounmap(dev->virtbase);
+ err_no_ioremap:
+        release_mem_region(dev->phybase, dev->physize);
+ err_no_ioregion:
+        platform_set_drvdata(pdev, NULL);
+ err_no_resource:
+        clk_put(dev->clk);
+ err_no_clk:
+        kfree(dev);
+ err_no_devmem:
+        dev_err(&pdev->dev, "failed to add " NAME " adapter: %d\n",
+                pdev->id);
+        return ret;
+}
+
+#ifdef CONFIG_PM
+static int stu300_suspend(struct platform_device *pdev, pm_message_t state)
+{
+        struct stu300_dev *dev = platform_get_drvdata(pdev);
+
+        /* Turn off everything */
+        stu300_wr8(0x00, dev->virtbase + I2C_CR);
+        return 0;
+}
+
+static int stu300_resume(struct platform_device *pdev)
+{
+        int ret = 0;
+        struct stu300_dev *dev = platform_get_drvdata(pdev);
+
+        clk_enable(dev->clk);
+        ret = stu300_init_hw(dev);
+        clk_disable(dev->clk);
+
+        if (ret != 0)
+                dev_err(&pdev->dev, "error re-initializing hardware.\n");
+        return ret;
+}
+#else
+#define stu300_suspend NULL
+#define stu300_resume NULL
+#endif
+
+static int __exit
+stu300_remove(struct platform_device *pdev)
+{
+        struct stu300_dev *dev = platform_get_drvdata(pdev);
+
+        i2c_del_adapter(&dev->adapter);
+        /* Turn off everything */
+        stu300_wr8(0x00, dev->virtbase + I2C_CR);
+        free_irq(dev->irq, dev);
+        iounmap(dev->virtbase);
+        release_mem_region(dev->phybase, dev->physize);
+        clk_put(dev->clk);
+        platform_set_drvdata(pdev, NULL);
+        kfree(dev);
+        return 0;
+}
+
+static struct platform_driver stu300_i2c_driver = {
+        .driver = {
+                .name   = NAME,
+                .owner  = THIS_MODULE,
+        },
+        .remove         = __exit_p(stu300_remove),
+        .suspend        = stu300_suspend,
+        .resume         = stu300_resume,
+
+};
+
+static int __init stu300_init(void)
+{
+        return platform_driver_probe(&stu300_i2c_driver, stu300_probe);
+}
+
+static void __exit stu300_exit(void)
+{
+        platform_driver_unregister(&stu300_i2c_driver);
+}
+
+/*
+ * The systems using this bus often have very basic devices such
+ * as regulators on the I2C bus, so this needs to be loaded early.
+ * Therefore it is registered in the subsys_initcall().
+ */
+subsys_initcall(stu300_init);
+module_exit(stu300_exit);
+
+MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
+MODULE_DESCRIPTION("ST Micro DDC I2C adapter (" NAME ")");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" NAME);
diff --git a/drivers/i2c/busses/i2c-versatile.c b/drivers/i2c/busses/i2c-versatile.c
index fede619ba227..70de82163463 100644
--- a/drivers/i2c/busses/i2c-versatile.c
+++ b/drivers/i2c/busses/i2c-versatile.c
@@ -76,7 +76,7 @@ static int i2c_versatile_probe(struct platform_device *dev)
                 goto err_out;
         }
 
-        if (!request_mem_region(r->start, r->end - r->start + 1, "versatile-i2c")) {
+        if (!request_mem_region(r->start, resource_size(r), "versatile-i2c")) {
                 ret = -EBUSY;
                 goto err_out;
         }
@@ -87,7 +87,7 @@ static int i2c_versatile_probe(struct platform_device *dev)
                 goto err_release;
         }
 
-        i2c->base = ioremap(r->start, r->end - r->start + 1);
+        i2c->base = ioremap(r->start, resource_size(r));
         if (!i2c->base) {
                 ret = -ENOMEM;
                 goto err_free;
@@ -118,7 +118,7 @@ static int i2c_versatile_probe(struct platform_device *dev)
  err_free:
         kfree(i2c);
  err_release:
-        release_mem_region(r->start, r->end - r->start + 1);
+        release_mem_region(r->start, resource_size(r));
  err_out:
         return ret;
 }
diff --git a/drivers/ide/ide-pm.c b/drivers/ide/ide-pm.c
index ba1488bd8430..c14ca144cffe 100644
--- a/drivers/ide/ide-pm.c
+++ b/drivers/ide/ide-pm.c
@@ -3,7 +3,8 @@
 
 int generic_ide_suspend(struct device *dev, pm_message_t mesg)
 {
-        ide_drive_t *drive = dev->driver_data, *pair = ide_get_pair_dev(drive);
+        ide_drive_t *drive = dev_get_drvdata(dev);
+        ide_drive_t *pair = ide_get_pair_dev(drive);
         ide_hwif_t *hwif = drive->hwif;
         struct request *rq;
         struct request_pm_state rqpm;
@@ -34,7 +35,8 @@ int generic_ide_suspend(struct device *dev, pm_message_t mesg)
 
 int generic_ide_resume(struct device *dev)
 {
-        ide_drive_t *drive = dev->driver_data, *pair = ide_get_pair_dev(drive);
+        ide_drive_t *drive = dev_get_drvdata(dev);
+        ide_drive_t *pair = ide_get_pair_dev(drive);
         ide_hwif_t *hwif = drive->hwif;
         struct request *rq;
         struct request_pm_state rqpm;
diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c
index f371b0de314f..79e0af3fd158 100644
--- a/drivers/ide/ide-probe.c
+++ b/drivers/ide/ide-probe.c
@@ -535,7 +535,7 @@ static int ide_register_port(ide_hwif_t *hwif)
 
         /* register with global device tree */
         dev_set_name(&hwif->gendev, hwif->name);
-        hwif->gendev.driver_data = hwif;
+        dev_set_drvdata(&hwif->gendev, hwif);
         if (hwif->gendev.parent == NULL)
                 hwif->gendev.parent = hwif->dev;
         hwif->gendev.release = hwif_release_dev;
@@ -987,9 +987,9 @@ static void hwif_register_devices(ide_hwif_t *hwif)
                 int ret;
 
                 dev_set_name(dev, "%u.%u", hwif->index, i);
+                dev_set_drvdata(dev, drive);
                 dev->parent = &hwif->gendev;
                 dev->bus = &ide_bus_type;
-                dev->driver_data = drive;
                 dev->release = drive_release_dev;
 
                 ret = device_register(dev);
diff --git a/drivers/ide/ide_platform.c b/drivers/ide/ide_platform.c
index ee9b55ecc62b..b579fbe88370 100644
--- a/drivers/ide/ide_platform.c
+++ b/drivers/ide/ide_platform.c
@@ -112,7 +112,7 @@ out:
 
 static int __devexit plat_ide_remove(struct platform_device *pdev)
 {
-        struct ide_host *host = pdev->dev.driver_data;
+        struct ide_host *host = dev_get_drvdata(&pdev->dev);
 
         ide_host_remove(host);
 
diff --git a/drivers/ieee1394/csr1212.c b/drivers/ieee1394/csr1212.c
index a6dfeb0b3372..e76cac64c533 100644
--- a/drivers/ieee1394/csr1212.c
+++ b/drivers/ieee1394/csr1212.c
@@ -35,6 +35,7 @@
 
 #include <linux/errno.h>
 #include <linux/kernel.h>
+#include <linux/kmemcheck.h>
 #include <linux/string.h>
 #include <asm/bug.h>
 #include <asm/byteorder.h>
@@ -387,6 +388,7 @@ csr1212_new_descriptor_leaf(u8 dtype, u32 specifier_id,
         if (!kv)
                 return NULL;
 
+        kmemcheck_annotate_variable(kv->value.leaf.data[0]);
         CSR1212_DESCRIPTOR_LEAF_SET_TYPE(kv, dtype);
         CSR1212_DESCRIPTOR_LEAF_SET_SPECIFIER_ID(kv, specifier_id);
 
diff --git a/drivers/ieee1394/eth1394.c b/drivers/ieee1394/eth1394.c
index 4ca103577c0a..f5c586c2bba6 100644
--- a/drivers/ieee1394/eth1394.c
+++ b/drivers/ieee1394/eth1394.c
@@ -361,7 +361,7 @@ static int eth1394_new_node(struct eth1394_host_info *hi,
         node_info->pdg.sz = 0;
         node_info->fifo = CSR1212_INVALID_ADDR_SPACE;
 
-        ud->device.driver_data = node_info;
+        dev_set_drvdata(&ud->device, node_info);
         new_node->ud = ud;
 
         priv = netdev_priv(hi->dev);
@@ -406,7 +406,7 @@ static int eth1394_remove(struct device *dev)
         list_del(&old_node->list);
         kfree(old_node);
 
-        node_info = (struct eth1394_node_info*)ud->device.driver_data;
+        node_info = dev_get_drvdata(&ud->device);
 
         spin_lock_irqsave(&node_info->pdg.lock, flags);
         /* The partial datagram list should be empty, but we'll just
@@ -416,7 +416,7 @@ static int eth1394_remove(struct device *dev)
         spin_unlock_irqrestore(&node_info->pdg.lock, flags);
 
         kfree(node_info);
-        ud->device.driver_data = NULL;
+        dev_set_drvdata(&ud->device, NULL);
         return 0;
 }
 
@@ -688,7 +688,7 @@ static void ether1394_host_reset(struct hpsb_host *host)
         ether1394_reset_priv(dev, 0);
 
         list_for_each_entry(node, &priv->ip_node_list, list) {
-                node_info = node->ud->device.driver_data;
+                node_info = dev_get_drvdata(&node->ud->device);
 
                 spin_lock_irqsave(&node_info->pdg.lock, flags);
 
@@ -872,8 +872,7 @@ static __be16 ether1394_parse_encap(struct sk_buff *skb, struct net_device *dev,
                 if (!node)
                         return cpu_to_be16(0);
 
-                node_info =
-                    (struct eth1394_node_info *)node->ud->device.driver_data;
+                node_info = dev_get_drvdata(&node->ud->device);
 
                 /* Update our speed/payload/fifo_offset table */
                 node_info->maxpayload = maxpayload;
@@ -1080,7 +1079,7 @@ static int ether1394_data_handler(struct net_device *dev, int srcid, int destid,
                 priv->ud_list[NODEID_TO_NODE(srcid)] = ud;
         }
 
-        node_info = (struct eth1394_node_info *)ud->device.driver_data;
+        node_info = dev_get_drvdata(&ud->device);
 
         /* First, did we receive a fragmented or unfragmented datagram? */
         hdr->words.word1 = ntohs(hdr->words.word1);
@@ -1617,8 +1616,7 @@ static int ether1394_tx(struct sk_buff *skb, struct net_device *dev)
                 if (!node)
                         goto fail;
 
-                node_info =
-                    (struct eth1394_node_info *)node->ud->device.driver_data;
+                node_info = dev_get_drvdata(&node->ud->device);
                 if (node_info->fifo == CSR1212_INVALID_ADDR_SPACE)
                         goto fail;
 
diff --git a/drivers/ieee1394/nodemgr.c b/drivers/ieee1394/nodemgr.c
index a6d55bebe61a..5122b5a8aa2d 100644
--- a/drivers/ieee1394/nodemgr.c
+++ b/drivers/ieee1394/nodemgr.c
@@ -10,6 +10,7 @@
 
 #include <linux/bitmap.h>
 #include <linux/kernel.h>
+#include <linux/kmemcheck.h>
 #include <linux/list.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
@@ -39,7 +40,10 @@ struct nodemgr_csr_info {
         struct hpsb_host *host;
         nodeid_t nodeid;
         unsigned int generation;
+
+        kmemcheck_bitfield_begin(flags);
         unsigned int speed_unverified:1;
+        kmemcheck_bitfield_end(flags);
 };
 
 
@@ -1293,6 +1297,7 @@ static void nodemgr_node_scan_one(struct hpsb_host *host,
         u8 *speed;
 
         ci = kmalloc(sizeof(*ci), GFP_KERNEL);
+        kmemcheck_annotate_bitfield(ci, flags);
         if (!ci)
                 return;
 
diff --git a/drivers/ieee1394/sbp2.c b/drivers/ieee1394/sbp2.c
index a51ab233342d..83b734aec923 100644
--- a/drivers/ieee1394/sbp2.c
+++ b/drivers/ieee1394/sbp2.c
@@ -718,7 +718,7 @@ static int sbp2_remove(struct device *dev)
         struct scsi_device *sdev;
 
         ud = container_of(dev, struct unit_directory, device);
-        lu = ud->device.driver_data;
+        lu = dev_get_drvdata(&ud->device);
         if (!lu)
                 return 0;
 
@@ -746,7 +746,7 @@ static int sbp2_remove(struct device *dev)
 
 static int sbp2_update(struct unit_directory *ud)
 {
-        struct sbp2_lu *lu = ud->device.driver_data;
+        struct sbp2_lu *lu = dev_get_drvdata(&ud->device);
 
         if (sbp2_reconnect_device(lu) != 0) {
                 /*
@@ -815,7 +815,7 @@ static struct sbp2_lu *sbp2_alloc_device(struct unit_directory *ud)
         atomic_set(&lu->state, SBP2LU_STATE_RUNNING);
         INIT_WORK(&lu->protocol_work, NULL);
 
-        ud->device.driver_data = lu;
+        dev_set_drvdata(&ud->device, lu);
 
         hi = hpsb_get_hostinfo(&sbp2_highlevel, ud->ne->host);
         if (!hi) {
@@ -1051,7 +1051,7 @@ static void sbp2_remove_device(struct sbp2_lu *lu)
                 hpsb_unregister_addrspace(&sbp2_highlevel, hi->host,
                                           lu->status_fifo_addr);
 
-        lu->ud->device.driver_data = NULL;
+        dev_set_drvdata(&lu->ud->device, NULL);
 
         module_put(hi->host->driver->owner);
 no_hi:
diff --git a/drivers/infiniband/core/sysfs.c b/drivers/infiniband/core/sysfs.c
index 5c04cfb54cb9..158a214da2f7 100644
--- a/drivers/infiniband/core/sysfs.c
+++ b/drivers/infiniband/core/sysfs.c
@@ -760,9 +760,9 @@ int ib_device_register_sysfs(struct ib_device *device)
         int i;
 
         class_dev->class      = &ib_class;
-        class_dev->driver_data = device;
         class_dev->parent     = device->dma_device;
         dev_set_name(class_dev, device->name);
+        dev_set_drvdata(class_dev, device);
 
         INIT_LIST_HEAD(&device->port_list);
 
diff --git a/drivers/infiniband/hw/ehca/ehca_main.c b/drivers/infiniband/hw/ehca/ehca_main.c
index 85905ab9391f..ce4e6eff4792 100644
--- a/drivers/infiniband/hw/ehca/ehca_main.c
+++ b/drivers/infiniband/hw/ehca/ehca_main.c
@@ -636,7 +636,7 @@ static ssize_t  ehca_show_##name(struct device *dev,                       \
         struct hipz_query_hca *rblock;                                     \
         int data;                                                          \
                                                                            \
-        shca = dev->driver_data;                                           \
+        shca = dev_get_drvdata(dev);                                       \
                                                                            \
         rblock = ehca_alloc_fw_ctrlblock(GFP_KERNEL);                      \
         if (!rblock) {                                                     \
@@ -680,7 +680,7 @@ static ssize_t ehca_show_adapter_handle(struct device *dev,
                                         struct device_attribute *attr,
                                         char *buf)
 {
-        struct ehca_shca *shca = dev->driver_data;
+        struct ehca_shca *shca = dev_get_drvdata(dev);
 
         return sprintf(buf, "%llx\n", shca->ipz_hca_handle.handle);
 
@@ -749,7 +749,7 @@ static int __devinit ehca_probe(struct of_device *dev,
 
         shca->ofdev = dev;
         shca->ipz_hca_handle.handle = *handle;
-        dev->dev.driver_data = shca;
+        dev_set_drvdata(&dev->dev, shca);
 
         ret = ehca_sense_attributes(shca);
         if (ret < 0) {
@@ -878,7 +878,7 @@ probe1:
 
 static int __devexit ehca_remove(struct of_device *dev)
 {
-        struct ehca_shca *shca = dev->dev.driver_data;
+        struct ehca_shca *shca = dev_get_drvdata(&dev->dev);
         unsigned long flags;
         int ret;
 
diff --git a/drivers/input/input.c b/drivers/input/input.c
index 5d445f48789b..7c237e6ac711 100644
--- a/drivers/input/input.c
+++ b/drivers/input/input.c
@@ -1265,8 +1265,14 @@ static struct device_type input_dev_type = {
         .uevent         = input_dev_uevent,
 };
 
+static char *input_nodename(struct device *dev)
+{
+        return kasprintf(GFP_KERNEL, "input/%s", dev_name(dev));
+}
+
 struct class input_class = {
         .name           = "input",
+        .nodename       = input_nodename,
 };
 EXPORT_SYMBOL_GPL(input_class);
 
diff --git a/drivers/input/joystick/analog.c b/drivers/input/joystick/analog.c
index 356b3a25efa2..1c0b529c06aa 100644
--- a/drivers/input/joystick/analog.c
+++ b/drivers/input/joystick/analog.c
@@ -35,7 +35,7 @@
 #include <linux/input.h>
 #include <linux/gameport.h>
 #include <linux/jiffies.h>
-#include <asm/timex.h>
+#include <linux/timex.h>
 
 #define DRIVER_DESC     "Analog joystick and gamepad driver"
 
diff --git a/drivers/input/misc/pcspkr.c b/drivers/input/misc/pcspkr.c
index d6a30cee7bc7..6d67af5387ad 100644
--- a/drivers/input/misc/pcspkr.c
+++ b/drivers/input/misc/pcspkr.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/input.h>
 #include <linux/platform_device.h>
+#include <linux/timex.h>
 #include <asm/io.h>
 
 MODULE_AUTHOR("Vojtech Pavlik <vojtech@ucw.cz>");
diff --git a/drivers/input/touchscreen/wm97xx-core.c b/drivers/input/touchscreen/wm97xx-core.c
index 69af8385ab14..2957d48e0045 100644
--- a/drivers/input/touchscreen/wm97xx-core.c
+++ b/drivers/input/touchscreen/wm97xx-core.c
@@ -569,7 +569,7 @@ static int wm97xx_probe(struct device *dev)
         mutex_init(&wm->codec_mutex);
 
         wm->dev = dev;
-        dev->driver_data = wm;
+        dev_set_drvdata(dev, wm);
         wm->ac97 = to_ac97_t(dev);
 
         /* check that we have a supported codec */
diff --git a/drivers/input/xen-kbdfront.c b/drivers/input/xen-kbdfront.c
index 928d2ed8865f..b115726dc088 100644
--- a/drivers/input/xen-kbdfront.c
+++ b/drivers/input/xen-kbdfront.c
@@ -114,7 +114,7 @@ static int __devinit xenkbd_probe(struct xenbus_device *dev,
                 xenbus_dev_fatal(dev, -ENOMEM, "allocating info structure");
                 return -ENOMEM;
         }
-        dev->dev.driver_data = info;
+        dev_set_drvdata(&dev->dev, info);
         info->xbdev = dev;
         info->irq = -1;
         snprintf(info->phys, sizeof(info->phys), "xenbus/%s", dev->nodename);
@@ -186,7 +186,7 @@ static int __devinit xenkbd_probe(struct xenbus_device *dev,
 
 static int xenkbd_resume(struct xenbus_device *dev)
 {
-        struct xenkbd_info *info = dev->dev.driver_data;
+        struct xenkbd_info *info = dev_get_drvdata(&dev->dev);
 
         xenkbd_disconnect_backend(info);
         memset(info->page, 0, PAGE_SIZE);
@@ -195,7 +195,7 @@ static int xenkbd_resume(struct xenbus_device *dev)
 
 static int xenkbd_remove(struct xenbus_device *dev)
 {
-        struct xenkbd_info *info = dev->dev.driver_data;
+        struct xenkbd_info *info = dev_get_drvdata(&dev->dev);
 
         xenkbd_disconnect_backend(info);
         if (info->kbd)
@@ -266,7 +266,7 @@ static void xenkbd_disconnect_backend(struct xenkbd_info *info)
 static void xenkbd_backend_changed(struct xenbus_device *dev,
                                    enum xenbus_state backend_state)
 {
-        struct xenkbd_info *info = dev->dev.driver_data;
+        struct xenkbd_info *info = dev_get_drvdata(&dev->dev);
         int ret, val;
 
         switch (backend_state) {
diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c
index 823ceba6efa8..1128d3fba797 100644
--- a/drivers/md/dm-ioctl.c
+++ b/drivers/md/dm-ioctl.c
@@ -1513,6 +1513,7 @@ static const struct file_operations _ctl_fops = {
 static struct miscdevice _dm_misc = {
         .minor          = MISC_DYNAMIC_MINOR,
         .name           = DM_NAME,
+        .devnode        = "mapper/control",
         .fops           = &_ctl_fops
 };
 
diff --git a/drivers/media/Kconfig b/drivers/media/Kconfig
index 223c36ede5ae..ba69beeb0e21 100644
--- a/drivers/media/Kconfig
+++ b/drivers/media/Kconfig
@@ -2,8 +2,14 @@
 # Multimedia device configuration
 #
 
-menu "Multimedia devices"
+menuconfig MEDIA_SUPPORT
+        tristate "Multimedia support"
         depends on HAS_IOMEM
+        help
+          If you want to use Video for Linux, DVB for Linux, or DAB adapters,
+          enable this option and other options below.
+
+if MEDIA_SUPPORT
 
 comment "Multimedia core support"
 
@@ -136,4 +142,4 @@ config USB_DABUSB
           module will be called dabusb.
 endif # DAB
 
-endmenu
+endif # MEDIA_SUPPORT
diff --git a/drivers/media/common/tuners/tuner-simple.c b/drivers/media/common/tuners/tuner-simple.c
index 78412c9c424a..149d54cdf7b9 100644
--- a/drivers/media/common/tuners/tuner-simple.c
+++ b/drivers/media/common/tuners/tuner-simple.c
@@ -416,6 +416,24 @@ static int simple_std_setup(struct dvb_frontend *fe,
         return 0;
 }
 
+static int simple_set_aux_byte(struct dvb_frontend *fe, u8 config, u8 aux)
+{
+        struct tuner_simple_priv *priv = fe->tuner_priv;
+        int rc;
+        u8 buffer[2];
+
+        buffer[0] = (config & ~0x38) | 0x18;
+        buffer[1] = aux;
+
+        tuner_dbg("setting aux byte: 0x%02x 0x%02x\n", buffer[0], buffer[1]);
+
+        rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 2);
+        if (2 != rc)
+                tuner_warn("i2c i/o error: rc == %d (should be 2)\n", rc);
+
+        return rc == 2 ? 0 : rc;
+}
+
 static int simple_post_tune(struct dvb_frontend *fe, u8 *buffer,
                             u16 div, u8 config, u8 cb)
 {
@@ -424,17 +442,10 @@ static int simple_post_tune(struct dvb_frontend *fe, u8 *buffer,
 
         switch (priv->type) {
         case TUNER_LG_TDVS_H06XF:
-                /* Set the Auxiliary Byte. */
-                buffer[0] = buffer[2];
-                buffer[0] &= ~0x20;
-                buffer[0] |= 0x18;
-                buffer[1] = 0x20;
-                tuner_dbg("tv 0x%02x 0x%02x\n", buffer[0], buffer[1]);
-
-                rc = tuner_i2c_xfer_send(&priv->i2c_props, buffer, 2);
-                if (2 != rc)
-                        tuner_warn("i2c i/o error: rc == %d "
-                                   "(should be 2)\n", rc);
+                simple_set_aux_byte(fe, config, 0x20);
+                break;
+        case TUNER_PHILIPS_FQ1216LME_MK3:
+                simple_set_aux_byte(fe, config, 0x60); /* External AGC */
                 break;
         case TUNER_MICROTUNE_4042FI5:
         {
@@ -506,6 +517,11 @@ static int simple_radio_bandswitch(struct dvb_frontend *fe, u8 *buffer)
         case TUNER_THOMSON_DTT761X:
                 buffer[3] = 0x39;
                 break;
+        case TUNER_PHILIPS_FQ1216LME_MK3:
+                tuner_err("This tuner doesn't have FM\n");
+                /* Set the low band for sanity, since it covers 88-108 MHz */
+                buffer[3] = 0x01;
+                break;
         case TUNER_MICROTUNE_4049FM5:
         default:
                 buffer[3] = 0xa4;
@@ -678,12 +694,12 @@ static int simple_set_radio_freq(struct dvb_frontend *fe,
                 return 0;
         }
 
-        /* Bandswitch byte */
-        simple_radio_bandswitch(fe, &buffer[0]);
-
         buffer[2] = (t_params->ranges[0].config & ~TUNER_RATIO_MASK) |
                     TUNER_RATIO_SELECT_50; /* 50 kHz step */
 
+        /* Bandswitch byte */
+        simple_radio_bandswitch(fe, &buffer[0]);
+
         /* Convert from 1/16 kHz V4L steps to 1/20 MHz (=50 kHz) PLL steps
            freq * (1 Mhz / 16000 V4L steps) * (20 PLL steps / 1 MHz) =
            freq * (1/800) */
diff --git a/drivers/media/common/tuners/tuner-types.c b/drivers/media/common/tuners/tuner-types.c
index 7c0bc064c008..6a7f1a417c27 100644
--- a/drivers/media/common/tuners/tuner-types.c
+++ b/drivers/media/common/tuners/tuner-types.c
@@ -578,6 +578,31 @@ static struct tuner_params tuner_fm1216me_mk3_params[] = {
         },
 };
 
+/* ------------ TUNER_PHILIPS_FM1216MK5 - Philips PAL ------------ */
+
+static struct tuner_range tuner_fm1216mk5_pal_ranges[] = {
+        { 16 * 158.00 /*MHz*/, 0xce, 0x01, },
+        { 16 * 441.00 /*MHz*/, 0xce, 0x02, },
+        { 16 * 864.00        , 0xce, 0x04, },
+};
+
+static struct tuner_params tuner_fm1216mk5_params[] = {
+        {
+                .type   = TUNER_PARAM_TYPE_PAL,
+                .ranges = tuner_fm1216mk5_pal_ranges,
+                .count  = ARRAY_SIZE(tuner_fm1216mk5_pal_ranges),
+                .cb_first_if_lower_freq = 1,
+                .has_tda9887 = 1,
+                .port1_active = 1,
+                .port2_active = 1,
+                .port2_invert_for_secam_lc = 1,
+                .port1_fm_high_sensitivity = 1,
+                .default_top_mid = -2,
+                .default_top_secam_mid = -2,
+                .default_top_secam_high = -2,
+        },
+};
+
 /* ------------ TUNER_LG_NTSC_NEW_TAPC - LGINNOTEK NTSC ------------ */
 
 static struct tuner_params tuner_lg_ntsc_new_tapc_params[] = {
@@ -1254,6 +1279,28 @@ static struct tuner_params tuner_tcl_mf02gip_5n_params[] = {
         },
 };
 
+/* 80-89 */
+/* --------- TUNER_PHILIPS_FQ1216LME_MK3 -- active loopthrough, no FM ------- */
+
+static struct tuner_params tuner_fq1216lme_mk3_params[] = {
+        {
+                .type   = TUNER_PARAM_TYPE_PAL,
+                .ranges = tuner_fm1216me_mk3_pal_ranges,
+                .count  = ARRAY_SIZE(tuner_fm1216me_mk3_pal_ranges),
+                .cb_first_if_lower_freq = 1, /* not specified, but safe to do */
+                .has_tda9887 = 1, /* TDA9886 */
+                .port1_active = 1,
+                .port2_active = 1,
+                .port2_invert_for_secam_lc = 1,
+                .default_top_low = 4,
+                .default_top_mid = 4,
+                .default_top_high = 4,
+                .default_top_secam_low = 4,
+                .default_top_secam_mid = 4,
+                .default_top_secam_high = 4,
+        },
+};
+
 /* --------------------------------------------------------------------- */
 
 struct tunertype tuners[] = {
@@ -1694,6 +1741,18 @@ struct tunertype tuners[] = {
                 .initdata = tua603x_agc112,
                 .sleepdata = (u8[]){ 4, 0x9c, 0x60, 0x85, 0x54 },
         },
+                [TUNER_PHILIPS_FM1216MK5] = { /* Philips PAL */
+                .name   = "Philips PAL/SECAM multi (FM1216 MK5)",
+                .params = tuner_fm1216mk5_params,
+                .count  = ARRAY_SIZE(tuner_fm1216mk5_params),
+        },
+
+        /* 80-89 */
+        [TUNER_PHILIPS_FQ1216LME_MK3] = { /* PAL/SECAM, Loop-thru, no FM */
+                .name = "Philips FQ1216LME MK3 PAL/SECAM w/active loopthrough",
+                .params = tuner_fq1216lme_mk3_params,
+                .count  = ARRAY_SIZE(tuner_fq1216lme_mk3_params),
+        },
 };
 EXPORT_SYMBOL(tuners);
 
diff --git a/drivers/media/common/tuners/tuner-xc2028.c b/drivers/media/common/tuners/tuner-xc2028.c
index 1adce9ff52ce..b6da9c3873fe 100644
--- a/drivers/media/common/tuners/tuner-xc2028.c
+++ b/drivers/media/common/tuners/tuner-xc2028.c
@@ -30,7 +30,7 @@ MODULE_PARM_DESC(debug, "enable verbose debug messages");
 
 static int no_poweroff;
 module_param(no_poweroff, int, 0644);
-MODULE_PARM_DESC(debug, "0 (default) powers device off when not used.\n"
+MODULE_PARM_DESC(no_poweroff, "0 (default) powers device off when not used.\n"
         "1 keep device energized and with tuner ready all the times.\n"
         "  Faster, but consumes more power and keeps the device hotter\n");
 
@@ -48,7 +48,7 @@ MODULE_PARM_DESC(audio_std,
         "NICAM/A\n"
         "NICAM/B\n");
 
-static char firmware_name[FIRMWARE_NAME_MAX];
+static char firmware_name[30];
 module_param_string(firmware_name, firmware_name, sizeof(firmware_name), 0);
 MODULE_PARM_DESC(firmware_name, "Firmware file name. Allows overriding the "
                                 "default firmware name\n");
@@ -272,7 +272,7 @@ static int load_all_firmwares(struct dvb_frontend *fe)
                 fname = firmware_name;
 
         tuner_dbg("Reading firmware %s\n", fname);
-        rc = request_firmware(&fw, fname, &priv->i2c_props.adap->dev);
+        rc = request_firmware(&fw, fname, priv->i2c_props.adap->dev.parent);
         if (rc < 0) {
                 if (rc == -ENOENT)
                         tuner_err("Error: firmware %s not found.\n",
@@ -917,22 +917,29 @@ static int generic_set_freq(struct dvb_frontend *fe, u32 freq /* in HZ */,
          * that xc2028 will be in a safe state.
          * Maybe this might also be needed for DTV.
          */
-        if (new_mode == T_ANALOG_TV) {
+        if (new_mode == T_ANALOG_TV)
                 rc = send_seq(priv, {0x00, 0x00});
-        } else if (priv->cur_fw.type & ATSC) {
-                offset = 1750000;
-        } else {
-                offset = 2750000;
+
+        /*
+         * Digital modes require an offset to adjust to the
+         * proper frequency.
+         * Analog modes require offset = 0
+         */
+        if (new_mode == T_DIGITAL_TV) {
+                /* Sets the offset according with firmware */
+                if (priv->cur_fw.type & DTV6)
+                        offset = 1750000;
+                else if (priv->cur_fw.type & DTV7)
+                        offset = 2250000;
+                else    /* DTV8 or DTV78 */
+                        offset = 2750000;
+
                 /*
-                 * We must adjust the offset by 500kHz in two cases in order
-                 * to correctly center the IF output:
-                 * 1) When the ZARLINK456 or DIBCOM52 tables were explicitly
-                 *    selected and a 7MHz channel is tuned;
-                 * 2) When tuning a VHF channel with DTV78 firmware.
+                 * We must adjust the offset by 500kHz  when
+                 * tuning a 7MHz VHF channel with DTV78 firmware
+                 * (used in Australia, Italy and Germany)
                  */
-                if (((priv->cur_fw.type & DTV7) &&
-                     (priv->cur_fw.scode_table & (ZARLINK456 | DIBCOM52))) ||
-                    ((priv->cur_fw.type & DTV78) && freq < 470000000))
+                if ((priv->cur_fw.type & DTV78) && freq < 470000000)
                         offset -= 500000;
         }
 
@@ -991,7 +998,7 @@ static int xc2028_set_analog_freq(struct dvb_frontend *fe,
                 if (priv->ctrl.input1)
                         type |= INPUT1;
                 return generic_set_freq(fe, (625l * p->frequency) / 10,
-                                T_ANALOG_TV, type, 0, 0);
+                                T_RADIO, type, 0, 0);
         }
 
         /* if std is not defined, choose one */
@@ -1022,21 +1029,20 @@ static int xc2028_set_params(struct dvb_frontend *fe,
         switch(fe->ops.info.type) {
         case FE_OFDM:
                 bw = p->u.ofdm.bandwidth;
-                break;
-        case FE_QAM:
-                tuner_info("WARN: There are some reports that "
-                           "QAM 6 MHz doesn't work.\n"
-                           "If this works for you, please report by "
-                           "e-mail to: v4l-dvb-maintainer@linuxtv.org\n");
-                bw = BANDWIDTH_6_MHZ;
-                type |= QAM;
+                /*
+                 * The only countries with 6MHz seem to be Taiwan/Uruguay.
+                 * Both seem to require QAM firmware for OFDM decoding
+                 * Tested in Taiwan by Terry Wu <terrywu2009@gmail.com>
+                 */
+                if (bw == BANDWIDTH_6_MHZ)
+                        type |= QAM;
                 break;
         case FE_ATSC:
                 bw = BANDWIDTH_6_MHZ;
                 /* The only ATSC firmware (at least on v2.7) is D2633 */
                 type |= ATSC | D2633;
                 break;
-        /* DVB-S is not supported */
+        /* DVB-S and pure QAM (FE_QAM) are not supported */
         default:
                 return -EINVAL;
         }
diff --git a/drivers/media/common/tuners/xc5000.c b/drivers/media/common/tuners/xc5000.c
index b54598550dc4..f4ffcdc9b848 100644
--- a/drivers/media/common/tuners/xc5000.c
+++ b/drivers/media/common/tuners/xc5000.c
@@ -3,6 +3,7 @@
  *
  *  Copyright (c) 2007 Xceive Corporation
  *  Copyright (c) 2007 Steven Toth <stoth@linuxtv.org>
+ *  Copyright (c) 2009 Devin Heitmueller <dheitmueller@kernellabs.com>
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -36,14 +37,20 @@ static int debug;
 module_param(debug, int, 0644);
 MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
 
+static int no_poweroff;
+module_param(no_poweroff, int, 0644);
+MODULE_PARM_DESC(no_poweroff, "0 (default) powers device off when not used.\n"
+        "\t\t1 keep device energized and with tuner ready all the times.\n"
+        "\t\tFaster, but consumes more power and keeps the device hotter");
+
 static DEFINE_MUTEX(xc5000_list_mutex);
 static LIST_HEAD(hybrid_tuner_instance_list);
 
 #define dprintk(level, fmt, arg...) if (debug >= level) \
         printk(KERN_INFO "%s: " fmt, "xc5000", ## arg)
 
-#define XC5000_DEFAULT_FIRMWARE "dvb-fe-xc5000-1.1.fw"
-#define XC5000_DEFAULT_FIRMWARE_SIZE 12332
+#define XC5000_DEFAULT_FIRMWARE "dvb-fe-xc5000-1.6.114.fw"
+#define XC5000_DEFAULT_FIRMWARE_SIZE 12401
 
 struct xc5000_priv {
         struct tuner_i2c_props i2c_props;
@@ -83,11 +90,11 @@ struct xc5000_priv {
 #define XREG_D_CODE       0x04
 #define XREG_IF_OUT       0x05
 #define XREG_SEEK_MODE    0x07
-#define XREG_POWER_DOWN   0x0A
+#define XREG_POWER_DOWN   0x0A /* Obsolete */
 #define XREG_SIGNALSOURCE 0x0D /* 0=Air, 1=Cable */
 #define XREG_SMOOTHEDCVBS 0x0E
 #define XREG_XTALFREQ     0x0F
-#define XREG_FINERFFREQ   0x10
+#define XREG_FINERFREQ    0x10
 #define XREG_DDIMODE      0x11
 
 #define XREG_ADC_ENV      0x00
@@ -100,6 +107,7 @@ struct xc5000_priv {
 #define XREG_VERSION      0x07
 #define XREG_PRODUCT_ID   0x08
 #define XREG_BUSY         0x09
+#define XREG_BUILD        0x0D
 
 /*
    Basic firmware description. This will remain with
@@ -191,27 +199,36 @@ static struct XC_TV_STANDARD XC5000_Standard[MAX_TV_STANDARD] = {
         {"FM Radio-INPUT1",   0x0208, 0x9002}
 };
 
-static int  xc5000_is_firmware_loaded(struct dvb_frontend *fe);
-static int  xc5000_writeregs(struct xc5000_priv *priv, u8 *buf, u8 len);
-static int  xc5000_readregs(struct xc5000_priv *priv, u8 *buf, u8 len);
-static void xc5000_TunerReset(struct dvb_frontend *fe);
+static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe);
+static int xc5000_is_firmware_loaded(struct dvb_frontend *fe);
+static int xc5000_readreg(struct xc5000_priv *priv, u16 reg, u16 *val);
+static int xc5000_TunerReset(struct dvb_frontend *fe);
 
 static int xc_send_i2c_data(struct xc5000_priv *priv, u8 *buf, int len)
 {
-        return xc5000_writeregs(priv, buf, len)
-                ? XC_RESULT_I2C_WRITE_FAILURE : XC_RESULT_SUCCESS;
+        struct i2c_msg msg = { .addr = priv->i2c_props.addr,
+                               .flags = 0, .buf = buf, .len = len };
+
+        if (i2c_transfer(priv->i2c_props.adap, &msg, 1) != 1) {
+                printk(KERN_ERR "xc5000: I2C write failed (len=%i)\n", len);
+                return XC_RESULT_I2C_WRITE_FAILURE;
+        }
+        return XC_RESULT_SUCCESS;
 }
 
+/* This routine is never used because the only time we read data from the
+   i2c bus is when we read registers, and we want that to be an atomic i2c
+   transaction in case we are on a multi-master bus */
 static int xc_read_i2c_data(struct xc5000_priv *priv, u8 *buf, int len)
 {
-        return xc5000_readregs(priv, buf, len)
-                ? XC_RESULT_I2C_READ_FAILURE : XC_RESULT_SUCCESS;
-}
+        struct i2c_msg msg = { .addr = priv->i2c_props.addr,
+                .flags = I2C_M_RD, .buf = buf, .len = len };
 
-static int xc_reset(struct dvb_frontend *fe)
-{
-        xc5000_TunerReset(fe);
-        return XC_RESULT_SUCCESS;
+        if (i2c_transfer(priv->i2c_props.adap, &msg, 1) != 1) {
+                printk(KERN_ERR "xc5000 I2C read failed (len=%i)\n", len);
+                return -EREMOTEIO;
+        }
+        return 0;
 }
 
 static void xc_wait(int wait_ms)
@@ -219,7 +236,7 @@ static void xc_wait(int wait_ms)
         msleep(wait_ms);
 }
 
-static void xc5000_TunerReset(struct dvb_frontend *fe)
+static int xc5000_TunerReset(struct dvb_frontend *fe)
 {
         struct xc5000_priv *priv = fe->tuner_priv;
         int ret;
@@ -232,16 +249,21 @@ static void xc5000_TunerReset(struct dvb_frontend *fe)
                                            priv->i2c_props.adap->algo_data,
                                            DVB_FRONTEND_COMPONENT_TUNER,
                                            XC5000_TUNER_RESET, 0);
-                if (ret)
+                if (ret) {
                         printk(KERN_ERR "xc5000: reset failed\n");
-        } else
+                        return XC_RESULT_RESET_FAILURE;
+                }
+        } else {
                 printk(KERN_ERR "xc5000: no tuner reset callback function, fatal\n");
+                return XC_RESULT_RESET_FAILURE;
+        }
+        return XC_RESULT_SUCCESS;
 }
 
 static int xc_write_reg(struct xc5000_priv *priv, u16 regAddr, u16 i2cData)
 {
         u8 buf[4];
-        int WatchDogTimer = 5;
+        int WatchDogTimer = 100;
         int result;
 
         buf[0] = (regAddr >> 8) & 0xFF;
@@ -263,7 +285,7 @@ static int xc_write_reg(struct xc5000_priv *priv, u16 regAddr, u16 i2cData)
                                                 /* busy flag cleared */
                                         break;
                                         } else {
-                                                xc_wait(100); /* wait 5 ms */
+                                                xc_wait(5); /* wait 5 ms */
                                                 WatchDogTimer--;
                                         }
                                 }
@@ -276,25 +298,6 @@ static int xc_write_reg(struct xc5000_priv *priv, u16 regAddr, u16 i2cData)
         return result;
 }
 
-static int xc_read_reg(struct xc5000_priv *priv, u16 regAddr, u16 *i2cData)
-{
-        u8 buf[2];
-        int result;
-
-        buf[0] = (regAddr >> 8) & 0xFF;
-        buf[1] = regAddr & 0xFF;
-        result = xc_send_i2c_data(priv, buf, 2);
-        if (result != XC_RESULT_SUCCESS)
-                return result;
-
-        result = xc_read_i2c_data(priv, buf, 2);
-        if (result != XC_RESULT_SUCCESS)
-                return result;
-
-        *i2cData = buf[0] * 256 + buf[1];
-        return result;
-}
-
 static int xc_load_i2c_sequence(struct dvb_frontend *fe, const u8 *i2c_sequence)
 {
         struct xc5000_priv *priv = fe->tuner_priv;
@@ -309,7 +312,7 @@ static int xc_load_i2c_sequence(struct dvb_frontend *fe, const u8 *i2c_sequence)
                 len = i2c_sequence[index] * 256 + i2c_sequence[index+1];
                 if (len == 0x0000) {
                         /* RESET command */
-                        result = xc_reset(fe);
+                        result = xc5000_TunerReset(fe);
                         index += 2;
                         if (result != XC_RESULT_SUCCESS)
                                 return result;
@@ -371,15 +374,6 @@ static int xc_SetTVStandard(struct xc5000_priv *priv,
         return ret;
 }
 
-static int xc_shutdown(struct xc5000_priv *priv)
-{
-        return XC_RESULT_SUCCESS;
-        /* Fixme: cannot bring tuner back alive once shutdown
-         *        without reloading the driver modules.
-         *    return xc_write_reg(priv, XREG_POWER_DOWN, 0);
-         */
-}
-
 static int xc_SetSignalSource(struct xc5000_priv *priv, u16 rf_mode)
 {
         dprintk(1, "%s(%d) Source = %s\n", __func__, rf_mode,
@@ -408,7 +402,10 @@ static int xc_set_RF_frequency(struct xc5000_priv *priv, u32 freq_hz)
 
         freq_code = (u16)(freq_hz / 15625);
 
-        return xc_write_reg(priv, XREG_RF_FREQ, freq_code);
+        /* Starting in firmware version 1.1.44, Xceive recommends using the
+           FINERFREQ for all normal tuning (the doc indicates reg 0x03 should
+           only be used for fast scanning for channel lock) */
+        return xc_write_reg(priv, XREG_FINERFREQ, freq_code);
 }
 
 
@@ -424,7 +421,7 @@ static int xc_set_IF_frequency(struct xc5000_priv *priv, u32 freq_khz)
 
 static int xc_get_ADC_Envelope(struct xc5000_priv *priv, u16 *adc_envelope)
 {
-        return xc_read_reg(priv, XREG_ADC_ENV, adc_envelope);
+        return xc5000_readreg(priv, XREG_ADC_ENV, adc_envelope);
 }
 
 static int xc_get_frequency_error(struct xc5000_priv *priv, u32 *freq_error_hz)
@@ -433,8 +430,8 @@ static int xc_get_frequency_error(struct xc5000_priv *priv, u32 *freq_error_hz)
         u16 regData;
         u32 tmp;
 
-        result = xc_read_reg(priv, XREG_FREQ_ERROR, &regData);
-        if (result)
+        result = xc5000_readreg(priv, XREG_FREQ_ERROR, &regData);
+        if (result != XC_RESULT_SUCCESS)
                 return result;
 
         tmp = (u32)regData;
@@ -444,7 +441,7 @@ static int xc_get_frequency_error(struct xc5000_priv *priv, u32 *freq_error_hz)
 
 static int xc_get_lock_status(struct xc5000_priv *priv, u16 *lock_status)
 {
-        return xc_read_reg(priv, XREG_LOCK, lock_status);
+        return xc5000_readreg(priv, XREG_LOCK, lock_status);
 }
 
 static int xc_get_version(struct xc5000_priv *priv,
@@ -454,8 +451,8 @@ static int xc_get_version(struct xc5000_priv *priv,
         u16 data;
         int result;
 
-        result = xc_read_reg(priv, XREG_VERSION, &data);
-        if (result)
+        result = xc5000_readreg(priv, XREG_VERSION, &data);
+        if (result != XC_RESULT_SUCCESS)
                 return result;
 
         (*hw_majorversion) = (data >> 12) & 0x0F;
@@ -466,13 +463,18 @@ static int xc_get_version(struct xc5000_priv *priv,
         return 0;
 }
 
+static int xc_get_buildversion(struct xc5000_priv *priv, u16 *buildrev)
+{
+        return xc5000_readreg(priv, XREG_BUILD, buildrev);
+}
+
 static int xc_get_hsync_freq(struct xc5000_priv *priv, u32 *hsync_freq_hz)
 {
         u16 regData;
         int result;
 
-        result = xc_read_reg(priv, XREG_HSYNC_FREQ, &regData);
-        if (result)
+        result = xc5000_readreg(priv, XREG_HSYNC_FREQ, &regData);
+        if (result != XC_RESULT_SUCCESS)
                 return result;
 
         (*hsync_freq_hz) = ((regData & 0x0fff) * 763)/100;
@@ -481,12 +483,12 @@ static int xc_get_hsync_freq(struct xc5000_priv *priv, u32 *hsync_freq_hz)
 
 static int xc_get_frame_lines(struct xc5000_priv *priv, u16 *frame_lines)
 {
-        return xc_read_reg(priv, XREG_FRAME_LINES, frame_lines);
+        return xc5000_readreg(priv, XREG_FRAME_LINES, frame_lines);
 }
 
 static int xc_get_quality(struct xc5000_priv *priv, u16 *quality)
 {
-        return xc_read_reg(priv, XREG_QUALITY, quality);
+        return xc5000_readreg(priv, XREG_QUALITY, quality);
 }
 
 static u16 WaitForLock(struct xc5000_priv *priv)
@@ -504,7 +506,9 @@ static u16 WaitForLock(struct xc5000_priv *priv)
         return lockState;
 }
 
-static int xc_tune_channel(struct xc5000_priv *priv, u32 freq_hz)
+#define XC_TUNE_ANALOG  0
+#define XC_TUNE_DIGITAL 1
+static int xc_tune_channel(struct xc5000_priv *priv, u32 freq_hz, int mode)
 {
         int found = 0;
 
@@ -513,8 +517,10 @@ static int xc_tune_channel(struct xc5000_priv *priv, u32 freq_hz)
         if (xc_set_RF_frequency(priv, freq_hz) != XC_RESULT_SUCCESS)
                 return 0;
 
-        if (WaitForLock(priv) == 1)
-                found = 1;
+        if (mode == XC_TUNE_ANALOG) {
+                if (WaitForLock(priv) == 1)
+                        found = 1;
+        }
 
         return found;
 }
@@ -536,32 +542,7 @@ static int xc5000_readreg(struct xc5000_priv *priv, u16 reg, u16 *val)
         }
 
         *val = (bval[0] << 8) | bval[1];
-        return 0;
-}
-
-static int xc5000_writeregs(struct xc5000_priv *priv, u8 *buf, u8 len)
-{
-        struct i2c_msg msg = { .addr = priv->i2c_props.addr,
-                .flags = 0, .buf = buf, .len = len };
-
-        if (i2c_transfer(priv->i2c_props.adap, &msg, 1) != 1) {
-                printk(KERN_ERR "xc5000: I2C write failed (len=%i)\n",
-                        (int)len);
-                return -EREMOTEIO;
-        }
-        return 0;
-}
-
-static int xc5000_readregs(struct xc5000_priv *priv, u8 *buf, u8 len)
-{
-        struct i2c_msg msg = { .addr = priv->i2c_props.addr,
-                .flags = I2C_M_RD, .buf = buf, .len = len };
-
-        if (i2c_transfer(priv->i2c_props.adap, &msg, 1) != 1) {
-                printk(KERN_ERR "xc5000 I2C read failed (len=%i)\n", (int)len);
-                return -EREMOTEIO;
-        }
-        return 0;
+        return XC_RESULT_SUCCESS;
 }
 
 static int xc5000_fwupload(struct dvb_frontend *fe)
@@ -575,13 +556,13 @@ static int xc5000_fwupload(struct dvb_frontend *fe)
                 XC5000_DEFAULT_FIRMWARE);
 
         ret = request_firmware(&fw, XC5000_DEFAULT_FIRMWARE,
-                &priv->i2c_props.adap->dev);
+                priv->i2c_props.adap->dev.parent);
         if (ret) {
                 printk(KERN_ERR "xc5000: Upload failed. (file not found?)\n");
                 ret = XC_RESULT_RESET_FAILURE;
                 goto out;
         } else {
-                printk(KERN_INFO "xc5000: firmware read %Zu bytes.\n",
+                printk(KERN_DEBUG "xc5000: firmware read %Zu bytes.\n",
                        fw->size);
                 ret = XC_RESULT_SUCCESS;
         }
@@ -590,8 +571,9 @@ static int xc5000_fwupload(struct dvb_frontend *fe)
                 printk(KERN_ERR "xc5000: firmware incorrect size\n");
                 ret = XC_RESULT_RESET_FAILURE;
         } else {
-                printk(KERN_INFO "xc5000: firmware upload\n");
+                printk(KERN_INFO "xc5000: firmware uploading...\n");
                 ret = xc_load_i2c_sequence(fe,  fw->data);
+                printk(KERN_INFO "xc5000: firmware upload complete...\n");
         }
 
 out:
@@ -609,6 +591,7 @@ static void xc_debug_dump(struct xc5000_priv *priv)
         u16 quality;
         u8 hw_majorversion = 0, hw_minorversion = 0;
         u8 fw_majorversion = 0, fw_minorversion = 0;
+        u16 fw_buildversion = 0;
 
         /* Wait for stats to stabilize.
          * Frame Lines needs two frame times after initial lock
@@ -628,9 +611,10 @@ static void xc_debug_dump(struct xc5000_priv *priv)
 
         xc_get_version(priv,  &hw_majorversion, &hw_minorversion,
                 &fw_majorversion, &fw_minorversion);
-        dprintk(1, "*** HW: V%02x.%02x, FW: V%02x.%02x\n",
+        xc_get_buildversion(priv,  &fw_buildversion);
+        dprintk(1, "*** HW: V%02x.%02x, FW: V%02x.%02x.%04x\n",
                 hw_majorversion, hw_minorversion,
-                fw_majorversion, fw_minorversion);
+                fw_majorversion, fw_minorversion, fw_buildversion);
 
         xc_get_hsync_freq(priv,  &hsync_freq_hz);
         dprintk(1, "*** Horizontal sync frequency = %d Hz\n", hsync_freq_hz);
@@ -648,27 +632,57 @@ static int xc5000_set_params(struct dvb_frontend *fe,
         struct xc5000_priv *priv = fe->tuner_priv;
         int ret;
 
+        if (xc5000_is_firmware_loaded(fe) != XC_RESULT_SUCCESS)
+                xc_load_fw_and_init_tuner(fe);
+
         dprintk(1, "%s() frequency=%d (Hz)\n", __func__, params->frequency);
 
-        switch (params->u.vsb.modulation) {
-        case VSB_8:
-        case VSB_16:
-                dprintk(1, "%s() VSB modulation\n", __func__);
+        if (fe->ops.info.type == FE_ATSC) {
+                dprintk(1, "%s() ATSC\n", __func__);
+                switch (params->u.vsb.modulation) {
+                case VSB_8:
+                case VSB_16:
+                        dprintk(1, "%s() VSB modulation\n", __func__);
+                        priv->rf_mode = XC_RF_MODE_AIR;
+                        priv->freq_hz = params->frequency - 1750000;
+                        priv->bandwidth = BANDWIDTH_6_MHZ;
+                        priv->video_standard = DTV6;
+                        break;
+                case QAM_64:
+                case QAM_256:
+                case QAM_AUTO:
+                        dprintk(1, "%s() QAM modulation\n", __func__);
+                        priv->rf_mode = XC_RF_MODE_CABLE;
+                        priv->freq_hz = params->frequency - 1750000;
+                        priv->bandwidth = BANDWIDTH_6_MHZ;
+                        priv->video_standard = DTV6;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+        } else if (fe->ops.info.type == FE_OFDM) {
+                dprintk(1, "%s() OFDM\n", __func__);
+                switch (params->u.ofdm.bandwidth) {
+                case BANDWIDTH_6_MHZ:
+                        priv->bandwidth = BANDWIDTH_6_MHZ;
+                        priv->video_standard = DTV6;
+                        priv->freq_hz = params->frequency - 1750000;
+                        break;
+                case BANDWIDTH_7_MHZ:
+                        printk(KERN_ERR "xc5000 bandwidth 7MHz not supported\n");
+                        return -EINVAL;
+                case BANDWIDTH_8_MHZ:
+                        priv->bandwidth = BANDWIDTH_8_MHZ;
+                        priv->video_standard = DTV8;
+                        priv->freq_hz = params->frequency - 2750000;
+                        break;
+                default:
+                        printk(KERN_ERR "xc5000 bandwidth not set!\n");
+                        return -EINVAL;
+                }
                 priv->rf_mode = XC_RF_MODE_AIR;
-                priv->freq_hz = params->frequency - 1750000;
-                priv->bandwidth = BANDWIDTH_6_MHZ;
-                priv->video_standard = DTV6;
-                break;
-        case QAM_64:
-        case QAM_256:
-        case QAM_AUTO:
-                dprintk(1, "%s() QAM modulation\n", __func__);
-                priv->rf_mode = XC_RF_MODE_CABLE;
-                priv->freq_hz = params->frequency - 1750000;
-                priv->bandwidth = BANDWIDTH_6_MHZ;
-                priv->video_standard = DTV6;
-                break;
-        default:
+        } else {
+                printk(KERN_ERR "xc5000 modulation type not supported!\n");
                 return -EINVAL;
         }
 
@@ -698,7 +712,7 @@ static int xc5000_set_params(struct dvb_frontend *fe,
                 return -EIO;
         }
 
-        xc_tune_channel(priv, priv->freq_hz);
+        xc_tune_channel(priv, priv->freq_hz, XC_TUNE_DIGITAL);
 
         if (debug)
                 xc_debug_dump(priv);
@@ -725,8 +739,6 @@ static int xc5000_is_firmware_loaded(struct dvb_frontend *fe)
         return ret;
 }
 
-static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe);
-
 static int xc5000_set_analog_params(struct dvb_frontend *fe,
         struct analog_parameters *params)
 {
@@ -807,7 +819,7 @@ tune_channel:
                 return -EREMOTEIO;
         }
 
-        xc_tune_channel(priv, priv->freq_hz);
+        xc_tune_channel(priv, priv->freq_hz, XC_TUNE_ANALOG);
 
         if (debug)
                 xc_debug_dump(priv);
@@ -875,18 +887,18 @@ static int xc_load_fw_and_init_tuner(struct dvb_frontend *fe)
 
 static int xc5000_sleep(struct dvb_frontend *fe)
 {
-        struct xc5000_priv *priv = fe->tuner_priv;
         int ret;
 
         dprintk(1, "%s()\n", __func__);
 
-        /* On Pinnacle PCTV HD 800i, the tuner cannot be reinitialized
-         * once shutdown without reloading the driver. Maybe I am not
-         * doing something right.
-         *
-         */
+        /* Avoid firmware reload on slow devices */
+        if (no_poweroff)
+                return 0;
 
-        ret = xc_shutdown(priv);
+        /* According to Xceive technical support, the "powerdown" register
+           was removed in newer versions of the firmware.  The "supported"
+           way to sleep the tuner is to pull the reset pin low for 10ms */
+        ret = xc5000_TunerReset(fe);
         if (ret != XC_RESULT_SUCCESS) {
                 printk(KERN_ERR
                         "xc5000: %s() unable to shutdown tuner\n",
@@ -991,7 +1003,7 @@ struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe,
         /* Check if firmware has been loaded. It is possible that another
            instance of the driver has loaded the firmware.
          */
-        if (xc5000_readreg(priv, XREG_PRODUCT_ID, &id) != 0)
+        if (xc5000_readreg(priv, XREG_PRODUCT_ID, &id) != XC_RESULT_SUCCESS)
                 goto fail;
 
         switch (id) {
diff --git a/drivers/media/dvb/b2c2/flexcop-common.h b/drivers/media/dvb/b2c2/flexcop-common.h
index 3e1c472092ab..9e2148a19967 100644
--- a/drivers/media/dvb/b2c2/flexcop-common.h
+++ b/drivers/media/dvb/b2c2/flexcop-common.h
@@ -1,9 +1,7 @@
 /*
- * This file is part of linux driver the digital TV devices equipped with B2C2 FlexcopII(b)/III
- *
- * flexcop-common.h - common header file for device-specific source files also.
- *
- * see flexcop.c for copyright information.
+ * Linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
+ * flexcop-common.h - common header file for device-specific source files
+ * see flexcop.c for copyright information
  */
 #ifndef __FLEXCOP_COMMON_H__
 #define __FLEXCOP_COMMON_H__
diff --git a/drivers/media/dvb/b2c2/flexcop-fe-tuner.c b/drivers/media/dvb/b2c2/flexcop-fe-tuner.c
index f7afab5944cf..efb4a6c2b57a 100644
--- a/drivers/media/dvb/b2c2/flexcop-fe-tuner.c
+++ b/drivers/media/dvb/b2c2/flexcop-fe-tuner.c
@@ -1,34 +1,27 @@
 /*
- * This file is part of linux driver the digital TV devices equipped with B2C2 FlexcopII(b)/III
- *
- * flexcop-fe-tuner.c - methods for attaching a frontend and controlling DiSEqC.
- *
- * see flexcop.c for copyright information.
+ * Linux driver for digital TV devices equipped with B2C2 FlexcopII(b)/III
+ * flexcop-fe-tuner.c - methods for frontend attachment and DiSEqC controlling
+ * see flexcop.c for copyright information
  */
 #include <media/tuner.h>
-
 #include "flexcop.h"
-
-#include "stv0299.h"
-#include "mt352.h"
-#include "nxt200x.h"
-#include "bcm3510.h"
-#include "stv0297.h"
 #include "mt312.h"
-#include "lgdt330x.h"
-#include "dvb-pll.h"
-#include "tuner-simple.h"
-
+#include "stv0299.h"
 #include "s5h1420.h"
 #include "itd1000.h"
-
-#include "cx24123.h"
 #include "cx24113.h"
-
+#include "cx24123.h"
 #include "isl6421.h"
+#include "mt352.h"
+#include "bcm3510.h"
+#include "nxt200x.h"
+#include "dvb-pll.h"
+#include "lgdt330x.h"
+#include "tuner-simple.h"
+#include "stv0297.h"
 
 /* lnb control */
-
+#if defined(CONFIG_DVB_MT312_MODULE) || defined(CONFIG_DVB_STV0299_MODULE)
 static int flexcop_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
 {
         struct flexcop_device *fc = fe->dvb->priv;
@@ -37,65 +30,62 @@ static int flexcop_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage
 
         v = fc->read_ibi_reg(fc, misc_204);
         switch (voltage) {
-                case SEC_VOLTAGE_OFF:
-                        v.misc_204.ACPI1_sig = 1;
-                        break;
-                case SEC_VOLTAGE_13:
-                        v.misc_204.ACPI1_sig = 0;
-                        v.misc_204.LNB_L_H_sig = 0;
-                        break;
-                case SEC_VOLTAGE_18:
-                        v.misc_204.ACPI1_sig = 0;
-                        v.misc_204.LNB_L_H_sig = 1;
-                        break;
-                default:
-                        err("unknown SEC_VOLTAGE value");
-                        return -EINVAL;
+        case SEC_VOLTAGE_OFF:
+                v.misc_204.ACPI1_sig = 1;
+                break;
+        case SEC_VOLTAGE_13:
+                v.misc_204.ACPI1_sig = 0;
+                v.misc_204.LNB_L_H_sig = 0;
+                break;
+        case SEC_VOLTAGE_18:
+                v.misc_204.ACPI1_sig = 0;
+                v.misc_204.LNB_L_H_sig = 1;
+                break;
+        default:
+                err("unknown SEC_VOLTAGE value");
+                return -EINVAL;
         }
         return fc->write_ibi_reg(fc, misc_204, v);
 }
+#endif
 
+#if defined(CONFIG_DVB_S5H1420_MODULE) || defined(CONFIG_DVB_STV0299_MODULE) \
+        || defined(CONFIG_DVB_MT312_MODULE)
 static int flexcop_sleep(struct dvb_frontend* fe)
 {
         struct flexcop_device *fc = fe->dvb->priv;
-/*      flexcop_ibi_value v = fc->read_ibi_reg(fc,misc_204); */
-
         if (fc->fe_sleep)
                 return fc->fe_sleep(fe);
-
-/*      v.misc_204.ACPI3_sig = 1;
-        fc->write_ibi_reg(fc,misc_204,v);*/
-
         return 0;
 }
+#endif
 
+/* SkyStar2 DVB-S rev 2.3 */
+#if defined(CONFIG_DVB_MT312_MODULE)
 static int flexcop_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
 {
-        /* u16 wz_half_period_for_45_mhz[] = { 0x01ff, 0x0154, 0x00ff, 0x00cc }; */
+/* u16 wz_half_period_for_45_mhz[] = { 0x01ff, 0x0154, 0x00ff, 0x00cc }; */
         struct flexcop_device *fc = fe->dvb->priv;
         flexcop_ibi_value v;
         u16 ax;
         v.raw = 0;
-
         deb_tuner("tone = %u\n",tone);
 
         switch (tone) {
-                case SEC_TONE_ON:
-                        ax = 0x01ff;
-                        break;
-                case SEC_TONE_OFF:
-                        ax = 0;
-                        break;
-                default:
-                        err("unknown SEC_TONE value");
-                        return -EINVAL;
+        case SEC_TONE_ON:
+                ax = 0x01ff;
+                break;
+        case SEC_TONE_OFF:
+                ax = 0;
+                break;
+        default:
+                err("unknown SEC_TONE value");
+                return -EINVAL;
         }
 
         v.lnb_switch_freq_200.LNB_CTLPrescaler_sig = 1; /* divide by 2 */
-
         v.lnb_switch_freq_200.LNB_CTLHighCount_sig = ax;
         v.lnb_switch_freq_200.LNB_CTLLowCount_sig  = ax == 0 ? 0x1ff : ax;
-
         return fc->write_ibi_reg(fc,lnb_switch_freq_200,v);
 }
 
@@ -110,17 +100,16 @@ static void flexcop_diseqc_send_bit(struct dvb_frontend* fe, int data)
 static void flexcop_diseqc_send_byte(struct dvb_frontend* fe, int data)
 {
         int i, par = 1, d;
-
         for (i = 7; i >= 0; i--) {
                 d = (data >> i) & 1;
                 par ^= d;
                 flexcop_diseqc_send_bit(fe, d);
         }
-
         flexcop_diseqc_send_bit(fe, par);
 }
 
-static int flexcop_send_diseqc_msg(struct dvb_frontend* fe, int len, u8 *msg, unsigned long burst)
+static int flexcop_send_diseqc_msg(struct dvb_frontend *fe,
+        int len, u8 *msg, unsigned long burst)
 {
         int i;
 
@@ -129,7 +118,6 @@ static int flexcop_send_diseqc_msg(struct dvb_frontend* fe, int len, u8 *msg, un
 
         for (i = 0; i < len; i++)
                 flexcop_diseqc_send_byte(fe,msg[i]);
-
         mdelay(16);
 
         if (burst != -1) {
@@ -146,50 +134,110 @@ static int flexcop_send_diseqc_msg(struct dvb_frontend* fe, int len, u8 *msg, un
         return 0;
 }
 
-static int flexcop_diseqc_send_master_cmd(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd)
+static int flexcop_diseqc_send_master_cmd(struct dvb_frontend *fe,
+        struct dvb_diseqc_master_cmd *cmd)
 {
         return flexcop_send_diseqc_msg(fe, cmd->msg_len, cmd->msg, 0);
 }
 
-static int flexcop_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t minicmd)
+static int flexcop_diseqc_send_burst(struct dvb_frontend *fe,
+        fe_sec_mini_cmd_t minicmd)
 {
         return flexcop_send_diseqc_msg(fe, 0, NULL, minicmd);
 }
 
-/* dvb-s stv0299 */
-static int samsung_tbmu24112_set_symbol_rate(struct dvb_frontend* fe, u32 srate, u32 ratio)
+static struct mt312_config skystar23_samsung_tbdu18132_config = {
+        .demod_address = 0x0e,
+};
+
+static int skystar23_samsung_tbdu18132_tuner_set_params(struct dvb_frontend *fe,
+        struct dvb_frontend_parameters *params)
+{
+        u8 buf[4];
+        u32 div;
+        struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf,
+        .len = sizeof(buf) };
+        struct flexcop_device *fc = fe->dvb->priv;
+        div = (params->frequency + (125/2)) / 125;
+
+        buf[0] = (div >> 8) & 0x7f;
+        buf[1] = (div >> 0) & 0xff;
+        buf[2] = 0x84 | ((div >> 10) & 0x60);
+        buf[3] = 0x80;
+
+        if (params->frequency < 1550000)
+                buf[3] |= 0x02;
+
+        if (fe->ops.i2c_gate_ctrl)
+                fe->ops.i2c_gate_ctrl(fe, 1);
+        if (i2c_transfer(&fc->fc_i2c_adap[0].i2c_adap, &msg, 1) != 1)
+                return -EIO;
+        return 0;
+}
+
+static int skystar2_rev23_attach(struct flexcop_device *fc,
+        struct i2c_adapter *i2c)
+{
+        fc->fe = dvb_attach(mt312_attach, &skystar23_samsung_tbdu18132_config, i2c);
+        if (fc->fe != NULL) {
+                struct dvb_frontend_ops *ops = &fc->fe->ops;
+                ops->tuner_ops.set_params   =
+                        skystar23_samsung_tbdu18132_tuner_set_params;
+                ops->diseqc_send_master_cmd = flexcop_diseqc_send_master_cmd;
+                ops->diseqc_send_burst      = flexcop_diseqc_send_burst;
+                ops->set_tone               = flexcop_set_tone;
+                ops->set_voltage            = flexcop_set_voltage;
+                fc->fe_sleep                = ops->sleep;
+                ops->sleep                  = flexcop_sleep;
+                return 1;
+        }
+        return 0;
+}
+#endif
+
+/* SkyStar2 DVB-S rev 2.6 */
+#if defined(CONFIG_DVB_STV0299_MODULE)
+static int samsung_tbmu24112_set_symbol_rate(struct dvb_frontend *fe,
+        u32 srate, u32 ratio)
 {
         u8 aclk = 0;
         u8 bclk = 0;
 
-        if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; }
-        else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; }
-        else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; }
-        else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; }
-        else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; }
-        else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; }
-
-        stv0299_writereg (fe, 0x13, aclk);
-        stv0299_writereg (fe, 0x14, bclk);
-        stv0299_writereg (fe, 0x1f, (ratio >> 16) & 0xff);
-        stv0299_writereg (fe, 0x20, (ratio >>  8) & 0xff);
-        stv0299_writereg (fe, 0x21, (ratio      ) & 0xf0);
+        if (srate < 1500000) {
+                aclk = 0xb7; bclk = 0x47;
+        } else if (srate < 3000000) {
+                aclk = 0xb7; bclk = 0x4b;
+        } else if (srate < 7000000) {
+                aclk = 0xb7; bclk = 0x4f;
+        } else if (srate < 14000000) {
+                aclk = 0xb7; bclk = 0x53;
+        } else if (srate < 30000000) {
+                aclk = 0xb6; bclk = 0x53;
+        } else if (srate < 45000000) {
+                aclk = 0xb4; bclk = 0x51;
+        }
 
+        stv0299_writereg(fe, 0x13, aclk);
+        stv0299_writereg(fe, 0x14, bclk);
+        stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
+        stv0299_writereg(fe, 0x20, (ratio >>  8) & 0xff);
+        stv0299_writereg(fe, 0x21,  ratio        & 0xf0);
         return 0;
 }
 
-static int samsung_tbmu24112_tuner_set_params(struct dvb_frontend* fe, struct dvb_frontend_parameters *params)
+static int samsung_tbmu24112_tuner_set_params(struct dvb_frontend *fe,
+        struct dvb_frontend_parameters *params)
 {
         u8 buf[4];
         u32 div;
-        struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) };
+        struct i2c_msg msg = {
+        .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) };
         struct flexcop_device *fc = fe->dvb->priv;
-
         div = params->frequency / 125;
 
         buf[0] = (div >> 8) & 0x7f;
         buf[1] = div & 0xff;
-        buf[2] = 0x84;  /* 0xC4 */
+        buf[2] = 0x84; /* 0xC4 */
         buf[3] = 0x08;
 
         if (params->frequency < 1500000)
@@ -203,48 +251,48 @@ static int samsung_tbmu24112_tuner_set_params(struct dvb_frontend* fe, struct dv
 }
 
 static u8 samsung_tbmu24112_inittab[] = {
-             0x01, 0x15,
-             0x02, 0x30,
-             0x03, 0x00,
-             0x04, 0x7D,
-             0x05, 0x35,
-             0x06, 0x02,
-             0x07, 0x00,
-             0x08, 0xC3,
-             0x0C, 0x00,
-             0x0D, 0x81,
-             0x0E, 0x23,
-             0x0F, 0x12,
-             0x10, 0x7E,
-             0x11, 0x84,
-             0x12, 0xB9,
-             0x13, 0x88,
-             0x14, 0x89,
-             0x15, 0xC9,
-             0x16, 0x00,
-             0x17, 0x5C,
-             0x18, 0x00,
-             0x19, 0x00,
-             0x1A, 0x00,
-             0x1C, 0x00,
-             0x1D, 0x00,
-             0x1E, 0x00,
-             0x1F, 0x3A,
-             0x20, 0x2E,
-             0x21, 0x80,
-             0x22, 0xFF,
-             0x23, 0xC1,
-             0x28, 0x00,
-             0x29, 0x1E,
-             0x2A, 0x14,
-             0x2B, 0x0F,
-             0x2C, 0x09,
-             0x2D, 0x05,
-             0x31, 0x1F,
-             0x32, 0x19,
-             0x33, 0xFE,
-             0x34, 0x93,
-             0xff, 0xff,
+        0x01, 0x15,
+        0x02, 0x30,
+        0x03, 0x00,
+        0x04, 0x7D,
+        0x05, 0x35,
+        0x06, 0x02,
+        0x07, 0x00,
+        0x08, 0xC3,
+        0x0C, 0x00,
+        0x0D, 0x81,
+        0x0E, 0x23,
+        0x0F, 0x12,
+        0x10, 0x7E,
+        0x11, 0x84,
+        0x12, 0xB9,
+        0x13, 0x88,
+        0x14, 0x89,
+        0x15, 0xC9,
+        0x16, 0x00,
+        0x17, 0x5C,
+        0x18, 0x00,
+        0x19, 0x00,
+        0x1A, 0x00,
+        0x1C, 0x00,
+        0x1D, 0x00,
+        0x1E, 0x00,
+        0x1F, 0x3A,
+        0x20, 0x2E,
+        0x21, 0x80,
+        0x22, 0xFF,
+        0x23, 0xC1,
+        0x28, 0x00,
+        0x29, 0x1E,
+        0x2A, 0x14,
+        0x2B, 0x0F,
+        0x2C, 0x09,
+        0x2D, 0x05,
+        0x31, 0x1F,
+        0x32, 0x19,
+        0x33, 0xFE,
+        0x34, 0x93,
+        0xff, 0xff,
 };
 
 static struct stv0299_config samsung_tbmu24112_config = {
@@ -259,27 +307,155 @@ static struct stv0299_config samsung_tbmu24112_config = {
         .set_symbol_rate = samsung_tbmu24112_set_symbol_rate,
 };
 
-/* dvb-t mt352 */
-static int samsung_tdtc9251dh0_demod_init(struct dvb_frontend* fe)
+static int skystar2_rev26_attach(struct flexcop_device *fc,
+        struct i2c_adapter *i2c)
+{
+        fc->fe = dvb_attach(stv0299_attach, &samsung_tbmu24112_config, i2c);
+        if (fc->fe != NULL) {
+                struct dvb_frontend_ops *ops  = &fc->fe->ops;
+                ops->tuner_ops.set_params = samsung_tbmu24112_tuner_set_params;
+                ops->set_voltage = flexcop_set_voltage;
+                fc->fe_sleep = ops->sleep;
+                ops->sleep = flexcop_sleep;
+                return 1;
+        }
+        return 0;
+}
+#endif
+
+/* SkyStar2 DVB-S rev 2.7 */
+#if defined(CONFIG_DVB_S5H1420_MODULE)
+static struct s5h1420_config skystar2_rev2_7_s5h1420_config = {
+        .demod_address = 0x53,
+        .invert = 1,
+        .repeated_start_workaround = 1,
+        .serial_mpeg = 1,
+};
+
+static struct itd1000_config skystar2_rev2_7_itd1000_config = {
+        .i2c_address = 0x61,
+};
+
+static int skystar2_rev27_attach(struct flexcop_device *fc,
+        struct i2c_adapter *i2c)
+{
+        flexcop_ibi_value r108;
+        struct i2c_adapter *i2c_tuner;
+
+        /* enable no_base_addr - no repeated start when reading */
+        fc->fc_i2c_adap[0].no_base_addr = 1;
+        fc->fe = dvb_attach(s5h1420_attach, &skystar2_rev2_7_s5h1420_config,
+                            i2c);
+        if (!fc->fe)
+                goto fail;
+
+        i2c_tuner = s5h1420_get_tuner_i2c_adapter(fc->fe);
+        if (!i2c_tuner)
+                goto fail;
+
+        fc->fe_sleep = fc->fe->ops.sleep;
+        fc->fe->ops.sleep = flexcop_sleep;
+
+        /* enable no_base_addr - no repeated start when reading */
+        fc->fc_i2c_adap[2].no_base_addr = 1;
+        if (!dvb_attach(isl6421_attach, fc->fe, &fc->fc_i2c_adap[2].i2c_adap,
+                        0x08, 1, 1)) {
+                err("ISL6421 could NOT be attached");
+                goto fail_isl;
+        }
+        info("ISL6421 successfully attached");
+
+        /* the ITD1000 requires a lower i2c clock - is it a problem ? */
+        r108.raw = 0x00000506;
+        fc->write_ibi_reg(fc, tw_sm_c_108, r108);
+        if (!dvb_attach(itd1000_attach, fc->fe, i2c_tuner,
+                        &skystar2_rev2_7_itd1000_config)) {
+                err("ITD1000 could NOT be attached");
+                /* Should i2c clock be restored? */
+                goto fail_isl;
+        }
+        info("ITD1000 successfully attached");
+
+        return 1;
+
+fail_isl:
+        fc->fc_i2c_adap[2].no_base_addr = 0;
+fail:
+        /* for the next devices we need it again */
+        fc->fc_i2c_adap[0].no_base_addr = 0;
+        return 0;
+}
+#endif
+
+/* SkyStar2 rev 2.8 */
+#if defined(CONFIG_DVB_CX24123_MODULE)
+static struct cx24123_config skystar2_rev2_8_cx24123_config = {
+        .demod_address = 0x55,
+        .dont_use_pll = 1,
+        .agc_callback = cx24113_agc_callback,
+};
+
+static const struct cx24113_config skystar2_rev2_8_cx24113_config = {
+        .i2c_addr = 0x54,
+        .xtal_khz = 10111,
+};
+
+static int skystar2_rev28_attach(struct flexcop_device *fc,
+        struct i2c_adapter *i2c)
+{
+        struct i2c_adapter *i2c_tuner;
+
+        fc->fe = dvb_attach(cx24123_attach, &skystar2_rev2_8_cx24123_config,
+                            i2c);
+        if (!fc->fe)
+                return 0;
+
+        i2c_tuner = cx24123_get_tuner_i2c_adapter(fc->fe);;
+        if (!i2c_tuner)
+                return 0;
+
+        if (!dvb_attach(cx24113_attach, fc->fe, &skystar2_rev2_8_cx24113_config,
+                        i2c_tuner)) {
+                err("CX24113 could NOT be attached");
+                return 0;
+        }
+        info("CX24113 successfully attached");
+
+        fc->fc_i2c_adap[2].no_base_addr = 1;
+        if (!dvb_attach(isl6421_attach, fc->fe, &fc->fc_i2c_adap[2].i2c_adap,
+                        0x08, 0, 0)) {
+                err("ISL6421 could NOT be attached");
+                fc->fc_i2c_adap[2].no_base_addr = 0;
+                return 0;
+        }
+        info("ISL6421 successfully attached");
+        /* TODO on i2c_adap[1] addr 0x11 (EEPROM) there seems to be an
+         * IR-receiver (PIC16F818) - but the card has no input for that ??? */
+        return 1;
+}
+#endif
+
+/* AirStar DVB-T */
+#if defined(CONFIG_DVB_MT352_MODULE)
+static int samsung_tdtc9251dh0_demod_init(struct dvb_frontend *fe)
 {
-        static u8 mt352_clock_config [] = { 0x89, 0x18, 0x2d };
-        static u8 mt352_reset [] = { 0x50, 0x80 };
-        static u8 mt352_adc_ctl_1_cfg [] = { 0x8E, 0x40 };
-        static u8 mt352_agc_cfg [] = { 0x67, 0x28, 0xa1 };
+        static u8 mt352_clock_config[] = { 0x89, 0x18, 0x2d };
+        static u8 mt352_reset[] = { 0x50, 0x80 };
+        static u8 mt352_adc_ctl_1_cfg[] = { 0x8E, 0x40 };
+        static u8 mt352_agc_cfg[] = { 0x67, 0x28, 0xa1 };
         static u8 mt352_capt_range_cfg[] = { 0x75, 0x32 };
 
         mt352_write(fe, mt352_clock_config, sizeof(mt352_clock_config));
         udelay(2000);
         mt352_write(fe, mt352_reset, sizeof(mt352_reset));
         mt352_write(fe, mt352_adc_ctl_1_cfg, sizeof(mt352_adc_ctl_1_cfg));
-
         mt352_write(fe, mt352_agc_cfg, sizeof(mt352_agc_cfg));
         mt352_write(fe, mt352_capt_range_cfg, sizeof(mt352_capt_range_cfg));
-
         return 0;
 }
 
-static int samsung_tdtc9251dh0_calc_regs(struct dvb_frontend* fe, struct dvb_frontend_parameters *params, u8* pllbuf, int buf_len)
+static int samsung_tdtc9251dh0_calc_regs(struct dvb_frontend *fe,
+        struct dvb_frontend_parameters *params, u8* pllbuf, int buf_len)
 {
         u32 div;
         unsigned char bs = 0;
@@ -287,19 +463,20 @@ static int samsung_tdtc9251dh0_calc_regs(struct dvb_frontend* fe, struct dvb_fro
         if (buf_len < 5)
                 return -EINVAL;
 
-        #define IF_FREQUENCYx6 217    /* 6 * 36.16666666667MHz */
+#define IF_FREQUENCYx6 217    /* 6 * 36.16666666667MHz */
         div = (((params->frequency + 83333) * 3) / 500000) + IF_FREQUENCYx6;
-
-        if (params->frequency >= 48000000 && params->frequency <= 154000000) bs = 0x09;
-        if (params->frequency >= 161000000 && params->frequency <= 439000000) bs = 0x0a;
-        if (params->frequency >= 447000000 && params->frequency <= 863000000) bs = 0x08;
+        if (params->frequency >= 48000000 && params->frequency <= 154000000) \
+                bs = 0x09;
+        if (params->frequency >= 161000000 && params->frequency <= 439000000) \
+                bs = 0x0a;
+        if (params->frequency >= 447000000 && params->frequency <= 863000000) \
+                bs = 0x08;
 
         pllbuf[0] = 0x61;
         pllbuf[1] = div >> 8;
         pllbuf[2] = div & 0xff;
         pllbuf[3] = 0xcc;
         pllbuf[4] = bs;
-
         return 5;
 }
 
@@ -308,70 +485,95 @@ static struct mt352_config samsung_tdtc9251dh0_config = {
         .demod_init    = samsung_tdtc9251dh0_demod_init,
 };
 
-static int flexcop_fe_request_firmware(struct dvb_frontend* fe, const struct firmware **fw, char* name)
+static int airstar_dvbt_attach(struct flexcop_device *fc,
+        struct i2c_adapter *i2c)
+{
+        fc->fe = dvb_attach(mt352_attach, &samsung_tdtc9251dh0_config, i2c);
+        if (fc->fe != NULL) {
+                fc->fe->ops.tuner_ops.calc_regs = samsung_tdtc9251dh0_calc_regs;
+                return 1;
+        }
+        return 0;
+}
+#endif
+
+/* AirStar ATSC 1st generation */
+#if defined(CONFIG_DVB_BCM3510_MODULE)
+static int flexcop_fe_request_firmware(struct dvb_frontend *fe,
+        const struct firmware **fw, char* name)
 {
         struct flexcop_device *fc = fe->dvb->priv;
         return request_firmware(fw, name, fc->dev);
 }
 
-static struct lgdt330x_config air2pc_atsc_hd5000_config = {
-        .demod_address       = 0x59,
-        .demod_chip          = LGDT3303,
-        .serial_mpeg         = 0x04,
-        .clock_polarity_flip = 1,
-};
-
-static struct nxt200x_config samsung_tbmv_config = {
-        .demod_address    = 0x0a,
-};
-
 static struct bcm3510_config air2pc_atsc_first_gen_config = {
         .demod_address    = 0x0f,
         .request_firmware = flexcop_fe_request_firmware,
 };
 
-static int skystar23_samsung_tbdu18132_tuner_set_params(struct dvb_frontend* fe, struct dvb_frontend_parameters *params)
+static int airstar_atsc1_attach(struct flexcop_device *fc,
+        struct i2c_adapter *i2c)
 {
-        u8 buf[4];
-        u32 div;
-        struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) };
-        struct flexcop_device *fc = fe->dvb->priv;
-
-        div = (params->frequency + (125/2)) / 125;
+        fc->fe = dvb_attach(bcm3510_attach, &air2pc_atsc_first_gen_config, i2c);
+        return fc->fe != NULL;
+}
+#endif
 
-        buf[0] = (div >> 8) & 0x7f;
-        buf[1] = (div >> 0) & 0xff;
-        buf[2] = 0x84 | ((div >> 10) & 0x60);
-        buf[3] = 0x80;
+/* AirStar ATSC 2nd generation */
+#if defined(CONFIG_DVB_NXT200X_MODULE)
+static struct nxt200x_config samsung_tbmv_config = {
+        .demod_address = 0x0a,
+};
 
-        if (params->frequency < 1550000)
-                buf[3] |= 0x02;
+static int airstar_atsc2_attach(struct flexcop_device *fc,
+        struct i2c_adapter *i2c)
+{
+        fc->fe = dvb_attach(nxt200x_attach, &samsung_tbmv_config, i2c);
+        if (!fc->fe)
+                return 0;
 
-        if (fe->ops.i2c_gate_ctrl)
-                fe->ops.i2c_gate_ctrl(fe, 1);
-        if (i2c_transfer(&fc->fc_i2c_adap[0].i2c_adap, &msg, 1) != 1)
-                return -EIO;
-        return 0;
+        return !!dvb_attach(dvb_pll_attach, fc->fe, 0x61, NULL,
+                            DVB_PLL_SAMSUNG_TBMV);
 }
+#endif
 
-static struct mt312_config skystar23_samsung_tbdu18132_config = {
-
-        .demod_address = 0x0e,
+/* AirStar ATSC 3rd generation */
+#if defined(CONFIG_DVB_LGDT330X_MODULE)
+static struct lgdt330x_config air2pc_atsc_hd5000_config = {
+        .demod_address       = 0x59,
+        .demod_chip          = LGDT3303,
+        .serial_mpeg         = 0x04,
+        .clock_polarity_flip = 1,
 };
 
+static int airstar_atsc3_attach(struct flexcop_device *fc,
+        struct i2c_adapter *i2c)
+{
+        fc->fe = dvb_attach(lgdt330x_attach, &air2pc_atsc_hd5000_config, i2c);
+        if (!fc->fe)
+                return 0;
+
+        return !!dvb_attach(simple_tuner_attach, fc->fe, i2c, 0x61,
+                            TUNER_LG_TDVS_H06XF);
+}
+#endif
+
+/* CableStar2 DVB-C */
+#if defined(CONFIG_DVB_STV0297_MODULE)
 static int alps_tdee4_stv0297_tuner_set_params(struct dvb_frontend* fe,
-                                               struct dvb_frontend_parameters *fep)
+                struct dvb_frontend_parameters *fep)
 {
         struct flexcop_device *fc = fe->dvb->priv;
         u8 buf[4];
         u16 div;
         int ret;
 
-/*  62.5 kHz * 10 */
+/* 62.5 kHz * 10 */
 #define REF_FREQ    625
 #define FREQ_OFFSET 36125
 
-        div = ((fep->frequency/1000 + FREQ_OFFSET ) * 10)  / REF_FREQ; // 4 MHz = 4000 KHz
+        div = ((fep->frequency/1000 + FREQ_OFFSET) * 10) / REF_FREQ;
+/* 4 MHz = 4000 KHz */
 
         buf[0] = (u8)( div >> 8) & 0x7f;
         buf[1] = (u8)        div & 0xff;
@@ -384,11 +586,11 @@ static int alps_tdee4_stv0297_tuner_set_params(struct dvb_frontend* fe,
  * AGD = 1, R3 R2 R1 R0 = 0 1 0 1 => byte 4 = 1**10101 = 0x95 */
         buf[2] = 0x95;
 
-// Range(MHz)  C1 *  RE RTS BS4 BS3 BS2 BS1  Byte 5
-//  47 - 153   0  *  0   0   0   0   0   1   0x01
-// 153 - 430   0  *  0   0   0   0   1   0   0x02
-// 430 - 822   0  *  0   0   1   0   0   0   0x08
-// 822 - 862   1  *  0   0   1   0   0   0   0x88
+/* Range(MHz)  C1 *  RE RTS BS4 BS3 BS2 BS1  Byte 5
+ *  47 - 153   0  *  0   0   0   0   0   1   0x01
+ * 153 - 430   0  *  0   0   0   0   1   0   0x02
+ * 430 - 822   0  *  0   0   1   0   0   0   0x08
+ * 822 - 862   1  *  0   0   1   0   0   0   0x88 */
 
              if (fep->frequency <= 153000000) buf[3] = 0x01;
         else if (fep->frequency <= 430000000) buf[3] = 0x02;
@@ -397,11 +599,11 @@ static int alps_tdee4_stv0297_tuner_set_params(struct dvb_frontend* fe,
 
         if (fe->ops.i2c_gate_ctrl)
                 fe->ops.i2c_gate_ctrl(fe, 0);
-        deb_tuner("tuner buffer for %d Hz: %x %x %x %x\n",fep->frequency, buf[0],buf[1],buf[2],buf[3]);
+        deb_tuner("tuner buffer for %d Hz: %x %x %x %x\n", fep->frequency,
+        buf[0], buf[1], buf[2], buf[3]);
         ret = fc->i2c_request(&fc->fc_i2c_adap[2],
-                FC_WRITE, 0x61, buf[0], &buf[1], 3);
+                        FC_WRITE, 0x61, buf[0], &buf[1], 3);
         deb_tuner("tuner write returned: %d\n",ret);
-
         return ret;
 }
 
@@ -481,182 +683,73 @@ static u8 alps_tdee4_stv0297_inittab[] = {
 static struct stv0297_config alps_tdee4_stv0297_config = {
         .demod_address = 0x1c,
         .inittab = alps_tdee4_stv0297_inittab,
-//      .invert = 1,
-//      .pll_set = alps_tdee4_stv0297_pll_set,
-};
-
-
-/* SkyStar2 rev2.7 (a/u) */
-static struct s5h1420_config skystar2_rev2_7_s5h1420_config = {
-        .demod_address = 0x53,
-        .invert = 1,
-        .repeated_start_workaround = 1,
-        .serial_mpeg = 1,
-};
-
-static struct itd1000_config skystar2_rev2_7_itd1000_config = {
-        .i2c_address = 0x61,
 };
 
-/* SkyStar2 rev2.8 */
-static struct cx24123_config skystar2_rev2_8_cx24123_config = {
-        .demod_address = 0x55,
-        .dont_use_pll = 1,
-        .agc_callback = cx24113_agc_callback,
-};
-
-static const struct cx24113_config skystar2_rev2_8_cx24113_config = {
-        .i2c_addr = 0x54,
-        .xtal_khz = 10111,
-};
-
-/* try to figure out the frontend, each card/box can have on of the following list */
-int flexcop_frontend_init(struct flexcop_device *fc)
+static int cablestar2_attach(struct flexcop_device *fc,
+        struct i2c_adapter *i2c)
 {
-        struct dvb_frontend_ops *ops;
-        struct i2c_adapter *i2c = &fc->fc_i2c_adap[0].i2c_adap;
-        struct i2c_adapter *i2c_tuner;
-
-        /* enable no_base_addr - no repeated start when reading */
-        fc->fc_i2c_adap[0].no_base_addr = 1;
-        fc->fe = dvb_attach(s5h1420_attach, &skystar2_rev2_7_s5h1420_config, i2c);
-        if (fc->fe != NULL) {
-                flexcop_ibi_value r108;
-                i2c_tuner = s5h1420_get_tuner_i2c_adapter(fc->fe);
-                ops = &fc->fe->ops;
-
-                fc->fe_sleep = ops->sleep;
-                ops->sleep   = flexcop_sleep;
-
-                fc->dev_type = FC_SKY_REV27;
-
-                /* enable no_base_addr - no repeated start when reading */
-                fc->fc_i2c_adap[2].no_base_addr = 1;
-                if (dvb_attach(isl6421_attach, fc->fe, &fc->fc_i2c_adap[2].i2c_adap, 0x08, 1, 1) == NULL)
-                        err("ISL6421 could NOT be attached");
-                else
-                        info("ISL6421 successfully attached");
-
-                /* the ITD1000 requires a lower i2c clock - it slows down the stuff for everyone - but is it a problem ? */
-                r108.raw = 0x00000506;
-                fc->write_ibi_reg(fc, tw_sm_c_108, r108);
-                if (i2c_tuner) {
-                        if (dvb_attach(itd1000_attach, fc->fe, i2c_tuner, &skystar2_rev2_7_itd1000_config) == NULL)
-                                err("ITD1000 could NOT be attached");
-                        else
-                                info("ITD1000 successfully attached");
-                }
-                goto fe_found;
-        }
-        fc->fc_i2c_adap[0].no_base_addr = 0; /* for the next devices we need it again */
-
-        /* try the sky v2.8 (cx24123, isl6421) */
-        fc->fe = dvb_attach(cx24123_attach,
-                &skystar2_rev2_8_cx24123_config, i2c);
-        if (fc->fe != NULL) {
-                i2c_tuner = cx24123_get_tuner_i2c_adapter(fc->fe);
-                if (i2c_tuner != NULL) {
-                        if (dvb_attach(cx24113_attach, fc->fe,
-                                        &skystar2_rev2_8_cx24113_config,
-                                        i2c_tuner) == NULL)
-                                err("CX24113 could NOT be attached");
-                        else
-                                info("CX24113 successfully attached");
-                }
-
-                fc->dev_type = FC_SKY_REV28;
-
-                fc->fc_i2c_adap[2].no_base_addr = 1;
-                if (dvb_attach(isl6421_attach, fc->fe,
-                       &fc->fc_i2c_adap[2].i2c_adap, 0x08, 0, 0) == NULL)
-                        err("ISL6421 could NOT be attached");
-                else
-                        info("ISL6421 successfully attached");
-
-                /* TODO on i2c_adap[1] addr 0x11 (EEPROM) there seems to be an
-                 * IR-receiver (PIC16F818) - but the card has no input for
-                 * that ??? */
-
-                goto fe_found;
-    }
-
-        /* try the sky v2.6 (stv0299/Samsung tbmu24112(sl1935)) */
-        fc->fe = dvb_attach(stv0299_attach, &samsung_tbmu24112_config, i2c);
-        if (fc->fe != NULL) {
-                ops = &fc->fe->ops;
-
-                ops->tuner_ops.set_params = samsung_tbmu24112_tuner_set_params;
-
-                ops->set_voltage = flexcop_set_voltage;
-
-                fc->fe_sleep = ops->sleep;
-                ops->sleep = flexcop_sleep;
-
-                fc->dev_type = FC_SKY_REV26;
-                goto fe_found;
-        }
-
-        /* try the air dvb-t (mt352/Samsung tdtc9251dh0(??)) */
-        fc->fe = dvb_attach(mt352_attach, &samsung_tdtc9251dh0_config, i2c);
-        if (fc->fe != NULL) {
-                fc->dev_type = FC_AIR_DVBT;
-                fc->fe->ops.tuner_ops.calc_regs = samsung_tdtc9251dh0_calc_regs;
-                goto fe_found;
-        }
-
-        /* try the air atsc 2nd generation (nxt2002) */
-        fc->fe = dvb_attach(nxt200x_attach, &samsung_tbmv_config, i2c);
-        if (fc->fe != NULL) {
-                fc->dev_type = FC_AIR_ATSC2;
-                dvb_attach(dvb_pll_attach, fc->fe, 0x61, NULL, DVB_PLL_SAMSUNG_TBMV);
-                goto fe_found;
-        }
-
-        fc->fe = dvb_attach(lgdt330x_attach, &air2pc_atsc_hd5000_config, i2c);
-        if (fc->fe != NULL) {
-                fc->dev_type = FC_AIR_ATSC3;
-                dvb_attach(simple_tuner_attach, fc->fe, i2c, 0x61,
-                                TUNER_LG_TDVS_H06XF);
-                goto fe_found;
-        }
-
-        /* try the air atsc 1nd generation (bcm3510)/panasonic ct10s */
-        fc->fe = dvb_attach(bcm3510_attach, &air2pc_atsc_first_gen_config, i2c);
-        if (fc->fe != NULL) {
-                fc->dev_type = FC_AIR_ATSC1;
-                goto fe_found;
-        }
-
-        /* try the cable dvb (stv0297) */
         fc->fc_i2c_adap[0].no_base_addr = 1;
         fc->fe = dvb_attach(stv0297_attach, &alps_tdee4_stv0297_config, i2c);
-        if (fc->fe != NULL) {
-                fc->dev_type = FC_CABLE;
-                fc->fe->ops.tuner_ops.set_params = alps_tdee4_stv0297_tuner_set_params;
-                goto fe_found;
+        if (!fc->fe) {
+                /* Reset for next frontend to try */
+                fc->fc_i2c_adap[0].no_base_addr = 0;
+                return 0;
         }
-        fc->fc_i2c_adap[0].no_base_addr = 0;
-
-        /* try the sky v2.3 (vp310/Samsung tbdu18132(tsa5059)) */
-        fc->fe = dvb_attach(mt312_attach,
-                &skystar23_samsung_tbdu18132_config, i2c);
-        if (fc->fe != NULL) {
-                ops = &fc->fe->ops;
-
-                ops->tuner_ops.set_params = skystar23_samsung_tbdu18132_tuner_set_params;
-
-                ops->diseqc_send_master_cmd = flexcop_diseqc_send_master_cmd;
-                ops->diseqc_send_burst      = flexcop_diseqc_send_burst;
-                ops->set_tone               = flexcop_set_tone;
-                ops->set_voltage            = flexcop_set_voltage;
-
-                fc->fe_sleep                = ops->sleep;
-                ops->sleep                  = flexcop_sleep;
+        fc->fe->ops.tuner_ops.set_params = alps_tdee4_stv0297_tuner_set_params;
+        return 1;
+}
+#endif
+
+static struct {
+        flexcop_device_type_t type;
+        int (*attach)(struct flexcop_device *, struct i2c_adapter *);
+} flexcop_frontends[] = {
+#if defined(CONFIG_DVB_S5H1420_MODULE)
+        { FC_SKY_REV27, skystar2_rev27_attach },
+#endif
+#if defined(CONFIG_DVB_CX24123_MODULE)
+        { FC_SKY_REV28, skystar2_rev28_attach },
+#endif
+#if defined(CONFIG_DVB_STV0299_MODULE)
+        { FC_SKY_REV26, skystar2_rev26_attach },
+#endif
+#if defined(CONFIG_DVB_MT352_MODULE)
+        { FC_AIR_DVBT, airstar_dvbt_attach },
+#endif
+#if defined(CONFIG_DVB_NXT200X_MODULE)
+        { FC_AIR_ATSC2, airstar_atsc2_attach },
+#endif
+#if defined(CONFIG_DVB_LGDT330X_MODULE)
+        { FC_AIR_ATSC3, airstar_atsc3_attach },
+#endif
+#if defined(CONFIG_DVB_BCM3510_MODULE)
+        { FC_AIR_ATSC1, airstar_atsc1_attach },
+#endif
+#if defined(CONFIG_DVB_STV0297_MODULE)
+        { FC_CABLE, cablestar2_attach },
+#endif
+#if defined(CONFIG_DVB_MT312_MODULE)
+        { FC_SKY_REV23, skystar2_rev23_attach },
+#endif
+};
 
-                fc->dev_type                = FC_SKY_REV23;
-                goto fe_found;
+/* try to figure out the frontend */
+int flexcop_frontend_init(struct flexcop_device *fc)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(flexcop_frontends); i++) {
+                /* type needs to be set before, because of some workarounds
+                 * done based on the probed card type */
+                fc->dev_type = flexcop_frontends[i].type;
+                if (flexcop_frontends[i].attach(fc, &fc->fc_i2c_adap[0].i2c_adap))
+                        goto fe_found;
+                /* Clean up partially attached frontend */
+                if (fc->fe) {
+                        dvb_frontend_detach(fc->fe);
+                        fc->fe = NULL;
+                }
         }
-
+        fc->dev_type = FC_UNK;
         err("no frontend driver found for this B2C2/FlexCop adapter");
         return -ENODEV;
 
@@ -664,9 +757,7 @@ fe_found:
         info("found '%s' .", fc->fe->ops.info.name);
         if (dvb_register_frontend(&fc->dvb_adapter, fc->fe)) {
                 err("frontend registration failed!");
-                ops = &fc->fe->ops;
-                if (ops->release != NULL)
-                        ops->release(fc->fe);
+                dvb_frontend_detach(fc->fe);
                 fc->fe = NULL;
                 return -EINVAL;
         }
@@ -680,6 +771,5 @@ void flexcop_frontend_exit(struct flexcop_device *fc)
                 dvb_unregister_frontend(fc->fe);
                 dvb_frontend_detach(fc->fe);
         }
-
         fc->init_state &= ~FC_STATE_FE_INIT;
 }
diff --git a/drivers/media/dvb/b2c2/flexcop-i2c.c b/drivers/media/dvb/b2c2/flexcop-i2c.c
index e2bed5076485..fd1df2352764 100644
--- a/drivers/media/dvb/b2c2/flexcop-i2c.c
+++ b/drivers/media/dvb/b2c2/flexcop-i2c.c
@@ -200,7 +200,7 @@ static int flexcop_master_xfer(struct i2c_adapter *i2c_adap,
                                         msgs[i].buf[0], &msgs[i].buf[1],
                                         msgs[i].len - 1);
                 if (ret < 0) {
-                        err("i2c master_xfer failed");
+                        deb_i2c("i2c master_xfer failed");
                         break;
                 }
         }
diff --git a/drivers/media/dvb/b2c2/flexcop-misc.c b/drivers/media/dvb/b2c2/flexcop-misc.c
index e56627d2f0f4..f06f3a9070f5 100644
--- a/drivers/media/dvb/b2c2/flexcop-misc.c
+++ b/drivers/media/dvb/b2c2/flexcop-misc.c
@@ -46,16 +46,16 @@ static const char *flexcop_revision_names[] = {
 };
 
 static const char *flexcop_device_names[] = {
-        "Unknown device",
-        "Air2PC/AirStar 2 DVB-T",
-        "Air2PC/AirStar 2 ATSC 1st generation",
-        "Air2PC/AirStar 2 ATSC 2nd generation",
-        "Sky2PC/SkyStar 2 DVB-S",
-        "Sky2PC/SkyStar 2 DVB-S (old version)",
-        "Cable2PC/CableStar 2 DVB-C",
-        "Air2PC/AirStar 2 ATSC 3rd generation (HD5000)",
-        "Sky2PC/SkyStar 2 DVB-S rev 2.7a/u",
-        "Sky2PC/SkyStar 2 DVB-S rev 2.8",
+        [FC_UNK]        = "Unknown device",
+        [FC_CABLE]      = "Cable2PC/CableStar 2 DVB-C",
+        [FC_AIR_DVBT]   = "Air2PC/AirStar 2 DVB-T",
+        [FC_AIR_ATSC1]  = "Air2PC/AirStar 2 ATSC 1st generation",
+        [FC_AIR_ATSC2]  = "Air2PC/AirStar 2 ATSC 2nd generation",
+        [FC_AIR_ATSC3]  = "Air2PC/AirStar 2 ATSC 3rd generation (HD5000)",
+        [FC_SKY_REV23]  = "Sky2PC/SkyStar 2 DVB-S rev 2.3 (old version)",
+        [FC_SKY_REV26]  = "Sky2PC/SkyStar 2 DVB-S rev 2.6",
+        [FC_SKY_REV27]  = "Sky2PC/SkyStar 2 DVB-S rev 2.7a/u",
+        [FC_SKY_REV28]  = "Sky2PC/SkyStar 2 DVB-S rev 2.8",
 };
 
 static const char *flexcop_bus_names[] = {
diff --git a/drivers/media/dvb/bt8xx/bt878.c b/drivers/media/dvb/bt8xx/bt878.c
index 56d8fab688bb..a24c125331f0 100644
--- a/drivers/media/dvb/bt8xx/bt878.c
+++ b/drivers/media/dvb/bt8xx/bt878.c
@@ -508,12 +508,6 @@ static int __devinit bt878_probe(struct pci_dev *dev,
         pci_set_master(dev);
         pci_set_drvdata(dev, bt);
 
-/*        if(init_bt878(btv) < 0) {
-                bt878_remove(dev);
-                return -EIO;
-        }
-*/
-
         if ((result = bt878_mem_alloc(bt))) {
                 printk(KERN_ERR "bt878: failed to allocate memory!\n");
                 goto fail2;
@@ -579,7 +573,7 @@ static struct pci_driver bt878_pci_driver = {
       .name     = "bt878",
       .id_table = bt878_pci_tbl,
       .probe    = bt878_probe,
-      .remove   = bt878_remove,
+      .remove   = __devexit_p(bt878_remove),
 };
 
 static int bt878_pci_driver_registered;
diff --git a/drivers/media/dvb/dm1105/dm1105.c b/drivers/media/dvb/dm1105/dm1105.c
index 971a8b18f6dd..4dbd7d4185af 100644
--- a/drivers/media/dvb/dm1105/dm1105.c
+++ b/drivers/media/dvb/dm1105/dm1105.c
@@ -51,6 +51,9 @@
 #ifndef PCI_VENDOR_ID_TRIGEM
 #define PCI_VENDOR_ID_TRIGEM    0x109f
 #endif
+#ifndef PCI_VENDOR_ID_AXESS
+#define PCI_VENDOR_ID_AXESS     0x195d
+#endif
 #ifndef PCI_DEVICE_ID_DM1105
 #define PCI_DEVICE_ID_DM1105    0x036f
 #endif
@@ -60,6 +63,9 @@
 #ifndef PCI_DEVICE_ID_DW2004
 #define PCI_DEVICE_ID_DW2004    0x2004
 #endif
+#ifndef PCI_DEVICE_ID_DM05
+#define PCI_DEVICE_ID_DM05      0x1105
+#endif
 /* ----------------------------------------------- */
 /* sdmc dm1105 registers */
 
@@ -150,6 +156,11 @@
 #define DM1105_LNB_13V                          0x00010100
 #define DM1105_LNB_18V                          0x00000100
 
+/* GPIO's for LNB power control for Axess DM05 */
+#define DM05_LNB_MASK                           0x00000000
+#define DM05_LNB_13V                            0x00020000
+#define DM05_LNB_18V                            0x00030000
+
 static int ir_debug;
 module_param(ir_debug, int, 0644);
 MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding");
@@ -188,6 +199,8 @@ struct dm1105dvb {
 
         /* irq */
         struct work_struct work;
+        struct workqueue_struct *wq;
+        char wqn[16];
 
         /* dma */
         dma_addr_t dma_addr;
@@ -313,15 +326,25 @@ static inline struct dm1105dvb *frontend_to_dm1105dvb(struct dvb_frontend *fe)
 static int dm1105dvb_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
 {
         struct dm1105dvb *dm1105dvb = frontend_to_dm1105dvb(fe);
+        u32 lnb_mask, lnb_13v, lnb_18v;
 
-                if (voltage == SEC_VOLTAGE_18) {
-                        outl(DM1105_LNB_MASK, dm_io_mem(DM1105_GPIOCTR));
-                        outl(DM1105_LNB_18V, dm_io_mem(DM1105_GPIOVAL));
-                } else  {
-                /*LNB ON-13V by default!*/
-                        outl(DM1105_LNB_MASK, dm_io_mem(DM1105_GPIOCTR));
-                        outl(DM1105_LNB_13V, dm_io_mem(DM1105_GPIOVAL));
-                }
+        switch (dm1105dvb->pdev->subsystem_device) {
+        case PCI_DEVICE_ID_DM05:
+                lnb_mask = DM05_LNB_MASK;
+                lnb_13v = DM05_LNB_13V;
+                lnb_18v = DM05_LNB_18V;
+                break;
+        default:
+                lnb_mask = DM1105_LNB_MASK;
+                lnb_13v = DM1105_LNB_13V;
+                lnb_18v = DM1105_LNB_18V;
+        }
+
+        outl(lnb_mask, dm_io_mem(DM1105_GPIOCTR));
+        if (voltage == SEC_VOLTAGE_18)
+                outl(lnb_18v , dm_io_mem(DM1105_GPIOVAL));
+        else
+                outl(lnb_13v, dm_io_mem(DM1105_GPIOVAL));
 
         return 0;
 }
@@ -440,7 +463,7 @@ static irqreturn_t dm1105dvb_irq(int irq, void *dev_id)
         case (INTSTS_TSIRQ | INTSTS_IR):
                 dm1105dvb->nextwrp = inl(dm_io_mem(DM1105_WRP)) -
                                         inl(dm_io_mem(DM1105_STADR));
-                schedule_work(&dm1105dvb->work);
+                queue_work(dm1105dvb->wq, &dm1105dvb->work);
                 break;
         case INTSTS_IR:
                 dm1105dvb->ir.ir_command = inl(dm_io_mem(DM1105_IRCODE));
@@ -567,46 +590,44 @@ static int __devinit frontend_init(struct dm1105dvb *dm1105dvb)
         int ret;
 
         switch (dm1105dvb->pdev->subsystem_device) {
-        case PCI_DEVICE_ID_DW2002:
+        case PCI_DEVICE_ID_DW2004:
                 dm1105dvb->fe = dvb_attach(
-                        stv0299_attach, &sharp_z0194a_config,
+                        cx24116_attach, &serit_sp2633_config,
                         &dm1105dvb->i2c_adap);
+                if (dm1105dvb->fe)
+                        dm1105dvb->fe->ops.set_voltage = dm1105dvb_set_voltage;
 
+                break;
+        default:
+                dm1105dvb->fe = dvb_attach(
+                        stv0299_attach, &sharp_z0194a_config,
+                        &dm1105dvb->i2c_adap);
                 if (dm1105dvb->fe) {
                         dm1105dvb->fe->ops.set_voltage =
                                                         dm1105dvb_set_voltage;
                         dvb_attach(dvb_pll_attach, dm1105dvb->fe, 0x60,
                                         &dm1105dvb->i2c_adap, DVB_PLL_OPERA1);
+                        break;
                 }
 
-                if (!dm1105dvb->fe) {
-                        dm1105dvb->fe = dvb_attach(
-                                stv0288_attach, &earda_config,
-                                &dm1105dvb->i2c_adap);
-                        if (dm1105dvb->fe) {
-                                dm1105dvb->fe->ops.set_voltage =
-                                                        dm1105dvb_set_voltage;
-                                dvb_attach(stb6000_attach, dm1105dvb->fe, 0x61,
-                                                &dm1105dvb->i2c_adap);
-                        }
+                dm1105dvb->fe = dvb_attach(
+                        stv0288_attach, &earda_config,
+                        &dm1105dvb->i2c_adap);
+                if (dm1105dvb->fe) {
+                        dm1105dvb->fe->ops.set_voltage =
+                                                dm1105dvb_set_voltage;
+                        dvb_attach(stb6000_attach, dm1105dvb->fe, 0x61,
+                                        &dm1105dvb->i2c_adap);
+                        break;
                 }
 
-                if (!dm1105dvb->fe) {
-                        dm1105dvb->fe = dvb_attach(
-                                si21xx_attach, &serit_config,
-                                &dm1105dvb->i2c_adap);
-                        if (dm1105dvb->fe)
-                                dm1105dvb->fe->ops.set_voltage =
-                                                        dm1105dvb_set_voltage;
-                }
-                break;
-        case PCI_DEVICE_ID_DW2004:
                 dm1105dvb->fe = dvb_attach(
-                        cx24116_attach, &serit_sp2633_config,
+                        si21xx_attach, &serit_config,
                         &dm1105dvb->i2c_adap);
                 if (dm1105dvb->fe)
-                        dm1105dvb->fe->ops.set_voltage = dm1105dvb_set_voltage;
-                break;
+                        dm1105dvb->fe->ops.set_voltage =
+                                                dm1105dvb_set_voltage;
+
         }
 
         if (!dm1105dvb->fe) {
@@ -630,10 +651,17 @@ static void __devinit dm1105dvb_read_mac(struct dm1105dvb *dm1105dvb, u8 *mac)
         static u8 command[1] = { 0x28 };
 
         struct i2c_msg msg[] = {
-                { .addr = IIC_24C01_addr >> 1, .flags = 0,
-                                .buf = command, .len = 1 },
-                { .addr = IIC_24C01_addr >> 1, .flags = I2C_M_RD,
-                                .buf = mac, .len = 6 },
+                {
+                        .addr = IIC_24C01_addr >> 1,
+                        .flags = 0,
+                        .buf = command,
+                        .len = 1
+                }, {
+                        .addr = IIC_24C01_addr >> 1,
+                        .flags = I2C_M_RD,
+                        .buf = mac,
+                        .len = 6
+                },
         };
 
         dm1105_i2c_xfer(&dm1105dvb->i2c_adap, msg , 2);
@@ -752,14 +780,22 @@ static int __devinit dm1105_probe(struct pci_dev *pdev,
         dm1105_ir_init(dm1105dvb);
 
         INIT_WORK(&dm1105dvb->work, dm1105_dmx_buffer);
+        sprintf(dm1105dvb->wqn, "%s/%d", dvb_adapter->name, dvb_adapter->num);
+        dm1105dvb->wq = create_singlethread_workqueue(dm1105dvb->wqn);
+        if (!dm1105dvb->wq)
+                goto err_dvb_net;
 
         ret = request_irq(pdev->irq, dm1105dvb_irq, IRQF_SHARED,
                                                 DRIVER_NAME, dm1105dvb);
         if (ret < 0)
-                goto err_free_irq;
+                goto err_workqueue;
 
         return 0;
 
+err_workqueue:
+        destroy_workqueue(dm1105dvb->wq);
+err_dvb_net:
+        dvb_net_release(&dm1105dvb->dvbnet);
 err_disconnect_frontend:
         dmx->disconnect_frontend(dmx);
 err_remove_mem_frontend:
@@ -776,8 +812,6 @@ err_i2c_del_adapter:
         i2c_del_adapter(&dm1105dvb->i2c_adap);
 err_dm1105dvb_hw_exit:
         dm1105dvb_hw_exit(dm1105dvb);
-err_free_irq:
-        free_irq(pdev->irq, dm1105dvb);
 err_pci_iounmap:
         pci_iounmap(pdev, dm1105dvb->io_mem);
 err_pci_release_regions:
@@ -834,6 +868,11 @@ static struct pci_device_id dm1105_id_table[] __devinitdata = {
                 .subvendor = PCI_ANY_ID,
                 .subdevice = PCI_DEVICE_ID_DW2004,
         }, {
+                .vendor = PCI_VENDOR_ID_AXESS,
+                .device = PCI_DEVICE_ID_DM05,
+                .subvendor = PCI_VENDOR_ID_AXESS,
+                .subdevice = PCI_DEVICE_ID_DM05,
+        }, {
                 /* empty */
         },
 };
diff --git a/drivers/media/dvb/dvb-core/dmxdev.c b/drivers/media/dvb/dvb-core/dmxdev.c
index c35fbb8d8f4a..6d6121eb5d59 100644
--- a/drivers/media/dvb/dvb-core/dmxdev.c
+++ b/drivers/media/dvb/dvb-core/dmxdev.c
@@ -244,19 +244,13 @@ static ssize_t dvb_dvr_read(struct file *file, char __user *buf, size_t count,
 {
         struct dvb_device *dvbdev = file->private_data;
         struct dmxdev *dmxdev = dvbdev->priv;
-        int ret;
 
-        if (dmxdev->exit) {
-                mutex_unlock(&dmxdev->mutex);
+        if (dmxdev->exit)
                 return -ENODEV;
-        }
 
-        //mutex_lock(&dmxdev->mutex);
-        ret = dvb_dmxdev_buffer_read(&dmxdev->dvr_buffer,
-                                     file->f_flags & O_NONBLOCK,
-                                     buf, count, ppos);
-        //mutex_unlock(&dmxdev->mutex);
-        return ret;
+        return dvb_dmxdev_buffer_read(&dmxdev->dvr_buffer,
+                                      file->f_flags & O_NONBLOCK,
+                                      buf, count, ppos);
 }
 
 static int dvb_dvr_set_buffer_size(struct dmxdev *dmxdev,
diff --git a/drivers/media/dvb/dvb-core/dvb_demux.c b/drivers/media/dvb/dvb-core/dvb_demux.c
index e2eca0b1fe7c..cfe2768d24af 100644
--- a/drivers/media/dvb/dvb-core/dvb_demux.c
+++ b/drivers/media/dvb/dvb-core/dvb_demux.c
@@ -38,6 +38,16 @@
 */
 // #define DVB_DEMUX_SECTION_LOSS_LOG
 
+static int dvb_demux_tscheck;
+module_param(dvb_demux_tscheck, int, 0644);
+MODULE_PARM_DESC(dvb_demux_tscheck,
+                "enable transport stream continuity and TEI check");
+
+#define dprintk_tscheck(x...) do {                              \
+                if (dvb_demux_tscheck && printk_ratelimit())    \
+                        printk(x);                              \
+        } while (0)
+
 /******************************************************************************
  * static inlined helper functions
  ******************************************************************************/
@@ -376,6 +386,36 @@ static void dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf)
         u16 pid = ts_pid(buf);
         int dvr_done = 0;
 
+        if (dvb_demux_tscheck) {
+                if (!demux->cnt_storage)
+                        demux->cnt_storage = vmalloc(MAX_PID + 1);
+
+                if (!demux->cnt_storage) {
+                        printk(KERN_WARNING "Couldn't allocate memory for TS/TEI check. Disabling it\n");
+                        dvb_demux_tscheck = 0;
+                        goto no_dvb_demux_tscheck;
+                }
+
+                /* check pkt counter */
+                if (pid < MAX_PID) {
+                        if (buf[1] & 0x80)
+                                dprintk_tscheck("TEI detected. "
+                                                "PID=0x%x data1=0x%x\n",
+                                                pid, buf[1]);
+
+                        if ((buf[3] & 0xf) != demux->cnt_storage[pid])
+                                dprintk_tscheck("TS packet counter mismatch. "
+                                                "PID=0x%x expected 0x%x "
+                                                "got 0x%x\n",
+                                                pid, demux->cnt_storage[pid],
+                                                buf[3] & 0xf);
+
+                        demux->cnt_storage[pid] = ((buf[3] & 0xf) + 1)&0xf;
+                };
+                /* end check */
+        };
+no_dvb_demux_tscheck:
+
         list_for_each_entry(feed, &demux->feed_list, list_head) {
                 if ((feed->pid != pid) && (feed->pid != 0x2000))
                         continue;
@@ -1160,6 +1200,7 @@ int dvb_dmx_init(struct dvb_demux *dvbdemux)
         int i;
         struct dmx_demux *dmx = &dvbdemux->dmx;
 
+        dvbdemux->cnt_storage = NULL;
         dvbdemux->users = 0;
         dvbdemux->filter = vmalloc(dvbdemux->filternum * sizeof(struct dvb_demux_filter));
 
@@ -1226,6 +1267,7 @@ EXPORT_SYMBOL(dvb_dmx_init);
 
 void dvb_dmx_release(struct dvb_demux *dvbdemux)
 {
+        vfree(dvbdemux->cnt_storage);
         vfree(dvbdemux->filter);
         vfree(dvbdemux->feed);
 }
diff --git a/drivers/media/dvb/dvb-core/dvb_demux.h b/drivers/media/dvb/dvb-core/dvb_demux.h
index 2c5f915329ca..2fe05d03240d 100644
--- a/drivers/media/dvb/dvb-core/dvb_demux.h
+++ b/drivers/media/dvb/dvb-core/dvb_demux.h
@@ -42,6 +42,8 @@
 
 #define DVB_DEMUX_MASK_MAX 18
 
+#define MAX_PID 0x1fff
+
 struct dvb_demux_filter {
         struct dmx_section_filter filter;
         u8 maskandmode[DMX_MAX_FILTER_SIZE];
@@ -127,6 +129,8 @@ struct dvb_demux {
 
         struct mutex mutex;
         spinlock_t lock;
+
+        uint8_t *cnt_storage; /* for TS continuity check */
 };
 
 int dvb_dmx_init(struct dvb_demux *dvbdemux);
diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c
index ebc78157b9b8..f50ca7292a7d 100644
--- a/drivers/media/dvb/dvb-core/dvb_frontend.c
+++ b/drivers/media/dvb/dvb-core/dvb_frontend.c
@@ -543,6 +543,7 @@ restart:
 
                 if (kthread_should_stop() || dvb_frontend_is_exiting(fe)) {
                         /* got signal or quitting */
+                        fepriv->exit = 1;
                         break;
                 }
 
@@ -656,6 +657,7 @@ restart:
         }
 
         fepriv->thread = NULL;
+        fepriv->exit = 0;
         mb();
 
         dvb_frontend_wakeup(fe);
diff --git a/drivers/media/dvb/dvb-core/dvbdev.c b/drivers/media/dvb/dvb-core/dvbdev.c
index a454ee8f1e43..479dd05762a5 100644
--- a/drivers/media/dvb/dvb-core/dvbdev.c
+++ b/drivers/media/dvb/dvb-core/dvbdev.c
@@ -447,6 +447,15 @@ static int dvb_uevent(struct device *dev, struct kobj_uevent_env *env)
         return 0;
 }
 
+static char *dvb_nodename(struct device *dev)
+{
+        struct dvb_device *dvbdev = dev_get_drvdata(dev);
+
+        return kasprintf(GFP_KERNEL, "dvb/adapter%d/%s%d",
+                dvbdev->adapter->num, dnames[dvbdev->type], dvbdev->id);
+}
+
+
 static int __init init_dvbdev(void)
 {
         int retval;
@@ -469,6 +478,7 @@ static int __init init_dvbdev(void)
                 goto error;
         }
         dvb_class->dev_uevent = dvb_uevent;
+        dvb_class->nodename = dvb_nodename;
         return 0;
 
 error:
diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig
index 1bb66e1ed5a7..496c1a37034c 100644
--- a/drivers/media/dvb/dvb-usb/Kconfig
+++ b/drivers/media/dvb/dvb-usb/Kconfig
@@ -261,6 +261,7 @@ config DVB_USB_DW2102
         select DVB_STB6000 if !DVB_FE_CUSTOMISE
         select DVB_CX24116 if !DVB_FE_CUSTOMISE
         select DVB_SI21XX if !DVB_FE_CUSTOMISE
+        select DVB_TDA10021 if !DVB_FE_CUSTOMISE
         help
           Say Y here to support the DvbWorld DVB-S/S2 USB2.0 receivers
           and the TeVii S650.
diff --git a/drivers/media/dvb/dvb-usb/af9015.c b/drivers/media/dvb/dvb-usb/af9015.c
index 53bfc8e42fb9..4cb31e7c13c2 100644
--- a/drivers/media/dvb/dvb-usb/af9015.c
+++ b/drivers/media/dvb/dvb-usb/af9015.c
@@ -40,7 +40,7 @@ DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
 static DEFINE_MUTEX(af9015_usb_mutex);
 
 static struct af9015_config af9015_config;
-static struct dvb_usb_device_properties af9015_properties[2];
+static struct dvb_usb_device_properties af9015_properties[3];
 static int af9015_properties_count = ARRAY_SIZE(af9015_properties);
 
 static struct af9013_config af9015_af9013_config[] = {
@@ -538,7 +538,7 @@ exit:
 /* dump eeprom */
 static int af9015_eeprom_dump(struct dvb_usb_device *d)
 {
-        char buf[52], buf2[4];
+        char buf[4+3*16+1], buf2[4];
         u8 reg, val;
 
         for (reg = 0; ; reg++) {
@@ -1261,7 +1261,11 @@ static struct usb_device_id af9015_usb_table[] = {
         {USB_DEVICE(USB_VID_KWORLD_2,  USB_PID_KWORLD_395U_2)},
         {USB_DEVICE(USB_VID_KWORLD_2,  USB_PID_KWORLD_395U_3)},
         {USB_DEVICE(USB_VID_AFATECH,   USB_PID_TREKSTOR_DVBT)},
-        {USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A850)},
+/* 20 */{USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A850)},
+        {USB_DEVICE(USB_VID_AVERMEDIA, USB_PID_AVERMEDIA_A805)},
+        {USB_DEVICE(USB_VID_KWORLD_2,  USB_PID_CONCEPTRONIC_CTVDIGRCU)},
+        {USB_DEVICE(USB_VID_KWORLD_2,  USB_PID_KWORLD_MC810)},
+        {USB_DEVICE(USB_VID_KYE,       USB_PID_GENIUS_TVGO_DVB_T03)},
         {0},
 };
 MODULE_DEVICE_TABLE(usb, af9015_usb_table);
@@ -1321,7 +1325,7 @@ static struct dvb_usb_device_properties af9015_properties[] = {
 
                 .i2c_algo = &af9015_i2c_algo,
 
-                .num_device_descs = 9,
+                .num_device_descs = 9, /* max 9 */
                 .devices = {
                         {
                                 .name = "Afatech AF9015 DVB-T USB2.0 stick",
@@ -1426,7 +1430,7 @@ static struct dvb_usb_device_properties af9015_properties[] = {
 
                 .i2c_algo = &af9015_i2c_algo,
 
-                .num_device_descs = 9,
+                .num_device_descs = 9, /* max 9 */
                 .devices = {
                         {
                                 .name = "Xtensions XD-380",
@@ -1478,7 +1482,85 @@ static struct dvb_usb_device_properties af9015_properties[] = {
                                 .warm_ids = {NULL},
                         },
                 }
-        }
+        }, {
+                .caps = DVB_USB_IS_AN_I2C_ADAPTER,
+
+                .usb_ctrl = DEVICE_SPECIFIC,
+                .download_firmware = af9015_download_firmware,
+                .firmware = "dvb-usb-af9015.fw",
+                .no_reconnect = 1,
+
+                .size_of_priv = sizeof(struct af9015_state), \
+
+                .num_adapters = 2,
+                .adapter = {
+                        {
+                                .caps = DVB_USB_ADAP_HAS_PID_FILTER |
+                                DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
+
+                                .pid_filter_count = 32,
+                                .pid_filter       = af9015_pid_filter,
+                                .pid_filter_ctrl  = af9015_pid_filter_ctrl,
+
+                                .frontend_attach =
+                                        af9015_af9013_frontend_attach,
+                                .tuner_attach    = af9015_tuner_attach,
+                                .stream = {
+                                        .type = USB_BULK,
+                                        .count = 6,
+                                        .endpoint = 0x84,
+                                },
+                        },
+                        {
+                                .frontend_attach =
+                                        af9015_af9013_frontend_attach,
+                                .tuner_attach    = af9015_tuner_attach,
+                                .stream = {
+                                        .type = USB_BULK,
+                                        .count = 6,
+                                        .endpoint = 0x85,
+                                        .u = {
+                                                .bulk = {
+                                                        .buffersize =
+                                                TS_USB20_MAX_PACKET_SIZE,
+                                                }
+                                        }
+                                },
+                        }
+                },
+
+                .identify_state = af9015_identify_state,
+
+                .rc_query         = af9015_rc_query,
+                .rc_interval      = 150,
+
+                .i2c_algo = &af9015_i2c_algo,
+
+                .num_device_descs = 4, /* max 9 */
+                .devices = {
+                        {
+                                .name = "AverMedia AVerTV Volar GPS 805 (A805)",
+                                .cold_ids = {&af9015_usb_table[21], NULL},
+                                .warm_ids = {NULL},
+                        },
+                        {
+                                .name = "Conceptronic USB2.0 DVB-T CTVDIGRCU " \
+                                        "V3.0",
+                                .cold_ids = {&af9015_usb_table[22], NULL},
+                                .warm_ids = {NULL},
+                        },
+                        {
+                                .name = "KWorld Digial MC-810",
+                                .cold_ids = {&af9015_usb_table[23], NULL},
+                                .warm_ids = {NULL},
+                        },
+                        {
+                                .name = "Genius TVGo DVB-T03",
+                                .cold_ids = {&af9015_usb_table[24], NULL},
+                                .warm_ids = {NULL},
+                        },
+                }
+        },
 };
 
 static int af9015_usb_probe(struct usb_interface *intf,
diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c
index 8ddbadf62194..818b2ab584bf 100644
--- a/drivers/media/dvb/dvb-usb/dib0700_devices.c
+++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c
@@ -1346,9 +1346,9 @@ static int dib0700_xc5000_tuner_callback(void *priv, int component,
         if (command == XC5000_TUNER_RESET) {
                 /* Reset the tuner */
                 dib0700_set_gpio(adap->dev, GPIO1, GPIO_OUT, 0);
-                msleep(330); /* from Windows USB trace */
+                msleep(10);
                 dib0700_set_gpio(adap->dev, GPIO1, GPIO_OUT, 1);
-                msleep(330); /* from Windows USB trace */
+                msleep(10);
         } else {
                 err("xc5000: unknown tuner callback command: %d\n", command);
                 return -EINVAL;
@@ -1493,6 +1493,10 @@ struct usb_device_id dib0700_usb_id_table[] = {
         { USB_DEVICE(USB_VID_HAUPPAUGE, USB_PID_HAUPPAUGE_TIGER_ATSC_B210) },
         { USB_DEVICE(USB_VID_YUAN,      USB_PID_YUAN_MC770) },
         { USB_DEVICE(USB_VID_ELGATO,    USB_PID_ELGATO_EYETV_DTT) },
+/* 50 */{ USB_DEVICE(USB_VID_ELGATO,    USB_PID_ELGATO_EYETV_DTT_Dlx) },
+        { USB_DEVICE(USB_VID_LEADTEK,   USB_PID_WINFAST_DTV_DONGLE_H) },
+        { USB_DEVICE(USB_VID_TERRATEC,  USB_PID_TERRATEC_T3) },
+        { USB_DEVICE(USB_VID_TERRATEC,  USB_PID_TERRATEC_T5) },
         { 0 }           /* Terminating entry */
 };
 MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table);
@@ -1692,7 +1696,7 @@ struct dvb_usb_device_properties dib0700_devices[] = {
                         },
                 },
 
-                .num_device_descs = 11,
+                .num_device_descs = 12,
                 .devices = {
                         {   "DiBcom STK7070P reference design",
                                 { &dib0700_usb_id_table[15], NULL },
@@ -1726,8 +1730,9 @@ struct dvb_usb_device_properties dib0700_devices[] = {
                                 { &dib0700_usb_id_table[30], NULL },
                                 { NULL },
                         },
-                        {   "Terratec Cinergy T USB XXS",
-                                { &dib0700_usb_id_table[33], NULL },
+                        {   "Terratec Cinergy T USB XXS/ T3",
+                                { &dib0700_usb_id_table[33],
+                                        &dib0700_usb_id_table[52], NULL },
                                 { NULL },
                         },
                         {   "Elgato EyeTV DTT",
@@ -1738,6 +1743,10 @@ struct dvb_usb_device_properties dib0700_devices[] = {
                                 { &dib0700_usb_id_table[45], NULL },
                                 { NULL },
                         },
+                        {   "Elgato EyeTV Dtt Dlx PD378S",
+                                { &dib0700_usb_id_table[50], NULL },
+                                { NULL },
+                        },
                 },
 
                 .rc_interval      = DEFAULT_RC_INTERVAL,
@@ -1784,8 +1793,9 @@ struct dvb_usb_device_properties dib0700_devices[] = {
                                 { &dib0700_usb_id_table[36], NULL },
                                 { NULL },
                         },
-                        {  "Terratec Cinergy DT USB XS Diversity",
-                                { &dib0700_usb_id_table[43], NULL },
+                        {  "Terratec Cinergy DT USB XS Diversity/ T5",
+                                { &dib0700_usb_id_table[43],
+                                        &dib0700_usb_id_table[53], NULL},
                                 { NULL },
                         },
                         {  "Sony PlayTV",
@@ -1812,7 +1822,7 @@ struct dvb_usb_device_properties dib0700_devices[] = {
                         },
                 },
 
-                .num_device_descs = 7,
+                .num_device_descs = 8,
                 .devices = {
                         {   "Terratec Cinergy HT USB XE",
                                 { &dib0700_usb_id_table[27], NULL },
@@ -1842,6 +1852,11 @@ struct dvb_usb_device_properties dib0700_devices[] = {
                                 { &dib0700_usb_id_table[48], NULL },
                                 { NULL },
                         },
+                        {   "Leadtek WinFast DTV Dongle H",
+                                { &dib0700_usb_id_table[51], NULL },
+                                { NULL },
+                        },
+
                 },
                 .rc_interval      = DEFAULT_RC_INTERVAL,
                 .rc_key_map       = dib0700_rc_keys,
diff --git a/drivers/media/dvb/dvb-usb/dibusb-common.c b/drivers/media/dvb/dvb-usb/dibusb-common.c
index 8ee6cd4da9e7..8dbad1ec53c4 100644
--- a/drivers/media/dvb/dvb-usb/dibusb-common.c
+++ b/drivers/media/dvb/dvb-usb/dibusb-common.c
@@ -133,14 +133,17 @@ static int dibusb_i2c_xfer(struct i2c_adapter *adap,struct i2c_msg msg[],int num
 
         for (i = 0; i < num; i++) {
                 /* write/read request */
-                if (i+1 < num && (msg[i+1].flags & I2C_M_RD)) {
+                if (i+1 < num && (msg[i].flags & I2C_M_RD) == 0
+                                          && (msg[i+1].flags & I2C_M_RD)) {
                         if (dibusb_i2c_msg(d, msg[i].addr, msg[i].buf,msg[i].len,
                                                 msg[i+1].buf,msg[i+1].len) < 0)
                                 break;
                         i++;
-                } else
+                } else if ((msg[i].flags & I2C_M_RD) == 0) {
                         if (dibusb_i2c_msg(d, msg[i].addr, msg[i].buf,msg[i].len,NULL,0) < 0)
                                 break;
+                } else
+                        break;
         }
 
         mutex_unlock(&d->i2c_mutex);
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
index f506c74119f3..9593b7289994 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
@@ -80,6 +80,7 @@
 #define USB_PID_COMPRO_DVBU2000_UNK_WARM                0x010d
 #define USB_PID_COMPRO_VIDEOMATE_U500                   0x1e78
 #define USB_PID_COMPRO_VIDEOMATE_U500_PC                0x1e80
+#define USB_PID_CONCEPTRONIC_CTVDIGRCU                  0xe397
 #define USB_PID_CONEXANT_D680_DMB                       0x86d6
 #define USB_PID_DIBCOM_HOOK_DEFAULT                     0x0064
 #define USB_PID_DIBCOM_HOOK_DEFAULT_REENUM              0x0065
@@ -97,6 +98,7 @@
 #define USB_PID_DPOSH_M9206_COLD                        0x9206
 #define USB_PID_DPOSH_M9206_WARM                        0xa090
 #define USB_PID_UNIWILL_STK7700P                        0x6003
+#define USB_PID_GENIUS_TVGO_DVB_T03                     0x4012
 #define USB_PID_GRANDTEC_DVBT_USB_COLD                  0x0fa0
 #define USB_PID_GRANDTEC_DVBT_USB_WARM                  0x0fa1
 #define USB_PID_INTEL_CE9500                            0x9500
@@ -104,6 +106,7 @@
 #define USB_PID_KWORLD_395U                             0xe396
 #define USB_PID_KWORLD_395U_2                           0xe39b
 #define USB_PID_KWORLD_395U_3                           0xe395
+#define USB_PID_KWORLD_MC810                            0xc810
 #define USB_PID_KWORLD_PC160_2T                         0xc160
 #define USB_PID_KWORLD_VSTREAM_COLD                     0x17de
 #define USB_PID_KWORLD_VSTREAM_WARM                     0x17df
@@ -171,6 +174,7 @@
 #define USB_PID_AVERMEDIA_A309                          0xa309
 #define USB_PID_AVERMEDIA_A310                          0xa310
 #define USB_PID_AVERMEDIA_A850                          0x850a
+#define USB_PID_AVERMEDIA_A805                          0xa805
 #define USB_PID_TECHNOTREND_CONNECT_S2400               0x3006
 #define USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY        0x005a
 #define USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY_2      0x0081
@@ -178,6 +182,8 @@
 #define USB_PID_TERRATEC_CINERGY_HT_EXPRESS             0x0060
 #define USB_PID_TERRATEC_CINERGY_T_EXPRESS              0x0062
 #define USB_PID_TERRATEC_CINERGY_T_XXS                  0x0078
+#define USB_PID_TERRATEC_T3                             0x10a0
+#define USB_PID_TERRATEC_T5                             0x10a1
 #define USB_PID_PINNACLE_EXPRESSCARD_320CX              0x022e
 #define USB_PID_PINNACLE_PCTV2000E                      0x022c
 #define USB_PID_PINNACLE_PCTV_DVB_T_FLASH               0x0228
@@ -222,6 +228,7 @@
 #define USB_PID_WINFAST_DTV_DONGLE_COLD                 0x6025
 #define USB_PID_WINFAST_DTV_DONGLE_WARM                 0x6026
 #define USB_PID_WINFAST_DTV_DONGLE_STK7700P             0x6f00
+#define USB_PID_WINFAST_DTV_DONGLE_H                    0x60f6
 #define USB_PID_WINFAST_DTV_DONGLE_STK7700P_2           0x6f01
 #define USB_PID_WINFAST_DTV_DONGLE_GOLD                 0x6029
 #define USB_PID_GENPIX_8PSK_REV_1_COLD                  0x0200
@@ -251,5 +258,6 @@
 #define USB_PID_MSI_DIGI_VOX_MINI_III                   0x8807
 #define USB_PID_SONY_PLAYTV                             0x0003
 #define USB_PID_ELGATO_EYETV_DTT                        0x0021
+#define USB_PID_ELGATO_EYETV_DTT_Dlx                    0x0020
 
 #endif
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb.h b/drivers/media/dvb/dvb-usb/dvb-usb.h
index 2d5352e54dc0..e441d274e6c1 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb.h
@@ -196,7 +196,7 @@ struct dvb_usb_device_properties {
 #define CYPRESS_FX2     3
         int        usb_ctrl;
         int        (*download_firmware) (struct usb_device *, const struct firmware *);
-        const char firmware[FIRMWARE_NAME_MAX];
+        const char *firmware;
         int        no_reconnect;
 
         int size_of_priv;
@@ -223,7 +223,7 @@ struct dvb_usb_device_properties {
         int generic_bulk_ctrl_endpoint;
 
         int num_device_descs;
-        struct dvb_usb_device_description devices[11];
+        struct dvb_usb_device_description devices[12];
 };
 
 /**
diff --git a/drivers/media/dvb/dvb-usb/dw2102.c b/drivers/media/dvb/dvb-usb/dw2102.c
index c65f273ff313..75de49c0d943 100644
--- a/drivers/media/dvb/dvb-usb/dw2102.c
+++ b/drivers/media/dvb/dvb-usb/dw2102.c
@@ -1,7 +1,7 @@
 /* DVB USB framework compliant Linux driver for the
-*       DVBWorld DVB-S 2101, 2102, DVB-S2 2104 Card
-*
-* Copyright (C) 2008 Igor M. Liplianin (liplianin@me.by)
+*       DVBWorld DVB-S 2101, 2102, DVB-S2 2104, DVB-C 3101,
+*       TeVii S600, S650 Cards
+* Copyright (C) 2008,2009 Igor M. Liplianin (liplianin@me.by)
 *
 *       This program is free software; you can redistribute it and/or modify it
 *       under the terms of the GNU General Public License as published by the
@@ -17,6 +17,7 @@
 #include "stb6000.h"
 #include "eds1547.h"
 #include "cx24116.h"
+#include "tda1002x.h"
 
 #ifndef USB_PID_DW2102
 #define USB_PID_DW2102 0x2102
@@ -26,10 +27,18 @@
 #define USB_PID_DW2104 0x2104
 #endif
 
+#ifndef USB_PID_DW3101
+#define USB_PID_DW3101 0x3101
+#endif
+
 #ifndef USB_PID_CINERGY_S
 #define USB_PID_CINERGY_S 0x0064
 #endif
 
+#ifndef USB_PID_TEVII_S650
+#define USB_PID_TEVII_S650 0xd650
+#endif
+
 #define DW210X_READ_MSG 0
 #define DW210X_WRITE_MSG 1
 
@@ -40,18 +49,21 @@
 #define DW2102_VOLTAGE_CTRL (0x1800)
 #define DW2102_RC_QUERY (0x1a00)
 
-struct dw210x_state {
-        u32 last_key_pressed;
-};
-struct dw210x_rc_keys {
-        u32 keycode;
-        u32 event;
+struct dvb_usb_rc_keys_table {
+        struct dvb_usb_rc_key *rc_keys;
+        int rc_keys_size;
 };
 
 /* debug */
 static int dvb_usb_dw2102_debug;
 module_param_named(debug, dvb_usb_dw2102_debug, int, 0644);
-MODULE_PARM_DESC(debug, "set debugging level (1=info 2=xfer (or-able))." DVB_USB_DEBUG_STATUS);
+MODULE_PARM_DESC(debug, "set debugging level (1=info 2=xfer 4=rc(or-able))."
+                                                DVB_USB_DEBUG_STATUS);
+
+/* keymaps */
+static int ir_keymap;
+module_param_named(keymap, ir_keymap, int, 0644);
+MODULE_PARM_DESC(keymap, "set keymap 0=default 1=dvbworld 2=tevii 3=tbs  ...");
 
 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
 
@@ -79,7 +91,7 @@ static int dw210x_op_rw(struct usb_device *dev, u8 request, u16 value,
 static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[],
                 int num)
 {
-struct dvb_usb_device *d = i2c_get_adapdata(adap);
+        struct dvb_usb_device *d = i2c_get_adapdata(adap);
         int i = 0, ret = 0;
         u8 buf6[] = {0x2c, 0x05, 0xc0, 0, 0, 0, 0};
         u16 value;
@@ -205,6 +217,7 @@ static int dw2102_serit_i2c_transfer(struct i2c_adapter *adap,
         mutex_unlock(&d->i2c_mutex);
         return num;
 }
+
 static int dw2102_earda_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], int num)
 {
         struct dvb_usb_device *d = i2c_get_adapdata(adap);
@@ -219,7 +232,7 @@ static int dw2102_earda_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg ms
         case 2: {
                 /* read */
                 /* first write first register number */
-                u8 ibuf [msg[1].len + 2], obuf[3];
+                u8 ibuf[msg[1].len + 2], obuf[3];
                 obuf[0] = 0xd0;
                 obuf[1] = msg[0].len;
                 obuf[2] = msg[0].buf[0];
@@ -293,7 +306,7 @@ static int dw2104_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], i
         case 2: {
                 /* read */
                 /* first write first register number */
-                u8 ibuf [msg[1].len + 2], obuf[3];
+                u8 ibuf[msg[1].len + 2], obuf[3];
                 obuf[0] = 0xaa;
                 obuf[1] = msg[0].len;
                 obuf[2] = msg[0].buf[0];
@@ -360,6 +373,69 @@ static int dw2104_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], i
         return num;
 }
 
+static int dw3101_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[],
+                                                                int num)
+{
+        struct dvb_usb_device *d = i2c_get_adapdata(adap);
+        int ret = 0, i;
+
+        if (!d)
+                return -ENODEV;
+        if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
+                return -EAGAIN;
+
+        switch (num) {
+        case 2: {
+                /* read */
+                /* first write first register number */
+                u8 ibuf[msg[1].len + 2], obuf[3];
+                obuf[0] = msg[0].addr << 1;
+                obuf[1] = msg[0].len;
+                obuf[2] = msg[0].buf[0];
+                ret = dw210x_op_rw(d->udev, 0xc2, 0, 0,
+                                obuf, msg[0].len + 2, DW210X_WRITE_MSG);
+                /* second read registers */
+                ret = dw210x_op_rw(d->udev, 0xc3, 0x19 , 0,
+                                ibuf, msg[1].len + 2, DW210X_READ_MSG);
+                memcpy(msg[1].buf, ibuf + 2, msg[1].len);
+
+                break;
+        }
+        case 1:
+                switch (msg[0].addr) {
+                case 0x60:
+                case 0x0c: {
+                        /* write to register */
+                        u8 obuf[msg[0].len + 2];
+                        obuf[0] = msg[0].addr << 1;
+                        obuf[1] = msg[0].len;
+                        memcpy(obuf + 2, msg[0].buf, msg[0].len);
+                        ret = dw210x_op_rw(d->udev, 0xc2, 0, 0,
+                                        obuf, msg[0].len + 2, DW210X_WRITE_MSG);
+                        break;
+                }
+                case(DW2102_RC_QUERY): {
+                        u8 ibuf[2];
+                        ret  = dw210x_op_rw(d->udev, 0xb8, 0, 0,
+                                        ibuf, 2, DW210X_READ_MSG);
+                        memcpy(msg[0].buf, ibuf , 2);
+                        break;
+                }
+                }
+
+                break;
+        }
+
+        for (i = 0; i < num; i++) {
+                deb_xfer("%02x:%02x: %s ", i, msg[i].addr,
+                                msg[i].flags == 0 ? ">>>" : "<<<");
+                debug_dump(msg[i].buf, msg[i].len, deb_xfer);
+        }
+
+        mutex_unlock(&d->i2c_mutex);
+        return num;
+}
+
 static u32 dw210x_i2c_func(struct i2c_adapter *adapter)
 {
         return I2C_FUNC_I2C;
@@ -385,6 +461,11 @@ static struct i2c_algorithm dw2104_i2c_algo = {
         .functionality = dw210x_i2c_func,
 };
 
+static struct i2c_algorithm dw3101_i2c_algo = {
+        .master_xfer = dw3101_i2c_transfer,
+        .functionality = dw210x_i2c_func,
+};
+
 static int dw210x_read_mac_address(struct dvb_usb_device *d, u8 mac[6])
 {
         int i;
@@ -404,6 +485,7 @@ static int dw210x_read_mac_address(struct dvb_usb_device *d, u8 mac[6])
                         debug_dump(eepromline, 16, deb_xfer);
                 }
         }
+
         memcpy(mac, eeprom + 8, 6);
         return 0;
 };
@@ -448,6 +530,11 @@ static struct si21xx_config serit_sp1511lhb_config = {
 
 };
 
+static struct tda10023_config dw3101_tda10023_config = {
+        .demod_address = 0x0c,
+        .invert = 1,
+};
+
 static int dw2104_frontend_attach(struct dvb_usb_adapter *d)
 {
         if ((d->fe = dvb_attach(cx24116_attach, &dw2104_config,
@@ -460,6 +547,7 @@ static int dw2104_frontend_attach(struct dvb_usb_adapter *d)
 }
 
 static struct dvb_usb_device_properties dw2102_properties;
+static struct dvb_usb_device_properties dw2104_properties;
 
 static int dw2102_frontend_attach(struct dvb_usb_adapter *d)
 {
@@ -497,6 +585,17 @@ static int dw2102_frontend_attach(struct dvb_usb_adapter *d)
         return -EIO;
 }
 
+static int dw3101_frontend_attach(struct dvb_usb_adapter *d)
+{
+        d->fe = dvb_attach(tda10023_attach, &dw3101_tda10023_config,
+                                &d->dev->i2c_adap, 0x48);
+        if (d->fe != NULL) {
+                info("Attached tda10023!\n");
+                return 0;
+        }
+        return -EIO;
+}
+
 static int dw2102_tuner_attach(struct dvb_usb_adapter *adap)
 {
         dvb_attach(dvb_pll_attach, adap->fe, 0x60,
@@ -512,6 +611,14 @@ static int dw2102_earda_tuner_attach(struct dvb_usb_adapter *adap)
         return 0;
 }
 
+static int dw3101_tuner_attach(struct dvb_usb_adapter *adap)
+{
+        dvb_attach(dvb_pll_attach, adap->fe, 0x60,
+                &adap->dev->i2c_adap, DVB_PLL_TUA6034);
+
+        return 0;
+}
+
 static struct dvb_usb_rc_key dw210x_rc_keys[] = {
         { 0xf8, 0x0a, KEY_Q },          /*power*/
         { 0xf8, 0x0c, KEY_M },          /*mute*/
@@ -544,44 +651,147 @@ static struct dvb_usb_rc_key dw210x_rc_keys[] = {
         { 0xf8, 0x40, KEY_F },          /*full*/
         { 0xf8, 0x1e, KEY_W },          /*tvmode*/
         { 0xf8, 0x1b, KEY_B },          /*recall*/
+};
 
+static struct dvb_usb_rc_key tevii_rc_keys[] = {
+        { 0xf8, 0x0a, KEY_POWER },
+        { 0xf8, 0x0c, KEY_MUTE },
+        { 0xf8, 0x11, KEY_1 },
+        { 0xf8, 0x12, KEY_2 },
+        { 0xf8, 0x13, KEY_3 },
+        { 0xf8, 0x14, KEY_4 },
+        { 0xf8, 0x15, KEY_5 },
+        { 0xf8, 0x16, KEY_6 },
+        { 0xf8, 0x17, KEY_7 },
+        { 0xf8, 0x18, KEY_8 },
+        { 0xf8, 0x19, KEY_9 },
+        { 0xf8, 0x10, KEY_0 },
+        { 0xf8, 0x1c, KEY_MENU },
+        { 0xf8, 0x0f, KEY_VOLUMEDOWN },
+        { 0xf8, 0x1a, KEY_LAST },
+        { 0xf8, 0x0e, KEY_OPEN },
+        { 0xf8, 0x04, KEY_RECORD },
+        { 0xf8, 0x09, KEY_VOLUMEUP },
+        { 0xf8, 0x08, KEY_CHANNELUP },
+        { 0xf8, 0x07, KEY_PVR },
+        { 0xf8, 0x0b, KEY_TIME },
+        { 0xf8, 0x02, KEY_RIGHT },
+        { 0xf8, 0x03, KEY_LEFT },
+        { 0xf8, 0x00, KEY_UP },
+        { 0xf8, 0x1f, KEY_OK },
+        { 0xf8, 0x01, KEY_DOWN },
+        { 0xf8, 0x05, KEY_TUNER },
+        { 0xf8, 0x06, KEY_CHANNELDOWN },
+        { 0xf8, 0x40, KEY_PLAYPAUSE },
+        { 0xf8, 0x1e, KEY_REWIND },
+        { 0xf8, 0x1b, KEY_FAVORITES },
+        { 0xf8, 0x1d, KEY_BACK },
+        { 0xf8, 0x4d, KEY_FASTFORWARD },
+        { 0xf8, 0x44, KEY_EPG },
+        { 0xf8, 0x4c, KEY_INFO },
+        { 0xf8, 0x41, KEY_AB },
+        { 0xf8, 0x43, KEY_AUDIO },
+        { 0xf8, 0x45, KEY_SUBTITLE },
+        { 0xf8, 0x4a, KEY_LIST },
+        { 0xf8, 0x46, KEY_F1 },
+        { 0xf8, 0x47, KEY_F2 },
+        { 0xf8, 0x5e, KEY_F3 },
+        { 0xf8, 0x5c, KEY_F4 },
+        { 0xf8, 0x52, KEY_F5 },
+        { 0xf8, 0x5a, KEY_F6 },
+        { 0xf8, 0x56, KEY_MODE },
+        { 0xf8, 0x58, KEY_SWITCHVIDEOMODE },
 };
 
+static struct dvb_usb_rc_key tbs_rc_keys[] = {
+        { 0xf8, 0x84, KEY_POWER },
+        { 0xf8, 0x94, KEY_MUTE },
+        { 0xf8, 0x87, KEY_1 },
+        { 0xf8, 0x86, KEY_2 },
+        { 0xf8, 0x85, KEY_3 },
+        { 0xf8, 0x8b, KEY_4 },
+        { 0xf8, 0x8a, KEY_5 },
+        { 0xf8, 0x89, KEY_6 },
+        { 0xf8, 0x8f, KEY_7 },
+        { 0xf8, 0x8e, KEY_8 },
+        { 0xf8, 0x8d, KEY_9 },
+        { 0xf8, 0x92, KEY_0 },
+        { 0xf8, 0x96, KEY_CHANNELUP },
+        { 0xf8, 0x91, KEY_CHANNELDOWN },
+        { 0xf8, 0x93, KEY_VOLUMEUP },
+        { 0xf8, 0x8c, KEY_VOLUMEDOWN },
+        { 0xf8, 0x83, KEY_RECORD },
+        { 0xf8, 0x98, KEY_PAUSE  },
+        { 0xf8, 0x99, KEY_OK },
+        { 0xf8, 0x9a, KEY_SHUFFLE },
+        { 0xf8, 0x81, KEY_UP },
+        { 0xf8, 0x90, KEY_LEFT },
+        { 0xf8, 0x82, KEY_RIGHT },
+        { 0xf8, 0x88, KEY_DOWN },
+        { 0xf8, 0x95, KEY_FAVORITES },
+        { 0xf8, 0x97, KEY_SUBTITLE },
+        { 0xf8, 0x9d, KEY_ZOOM },
+        { 0xf8, 0x9f, KEY_EXIT },
+        { 0xf8, 0x9e, KEY_MENU },
+        { 0xf8, 0x9c, KEY_EPG },
+        { 0xf8, 0x80, KEY_PREVIOUS },
+        { 0xf8, 0x9b, KEY_MODE }
+};
 
+static struct dvb_usb_rc_keys_table keys_tables[] = {
+        { dw210x_rc_keys, ARRAY_SIZE(dw210x_rc_keys) },
+        { tevii_rc_keys, ARRAY_SIZE(tevii_rc_keys) },
+        { tbs_rc_keys, ARRAY_SIZE(tbs_rc_keys) },
+};
 
 static int dw2102_rc_query(struct dvb_usb_device *d, u32 *event, int *state)
 {
-        struct dw210x_state *st = d->priv;
+        struct dvb_usb_rc_key *keymap = d->props.rc_key_map;
+        int keymap_size = d->props.rc_key_map_size;
         u8 key[2];
-        struct i2c_msg msg[] = {
-                {.addr = DW2102_RC_QUERY, .flags = I2C_M_RD, .buf = key,
-                .len = 2},
+        struct i2c_msg msg = {
+                .addr = DW2102_RC_QUERY,
+                .flags = I2C_M_RD,
+                .buf = key,
+                .len = 2
         };
         int i;
+        /* override keymap */
+        if ((ir_keymap > 0) && (ir_keymap <= ARRAY_SIZE(keys_tables))) {
+                keymap = keys_tables[ir_keymap - 1].rc_keys ;
+                keymap_size = keys_tables[ir_keymap - 1].rc_keys_size;
+        }
 
         *state = REMOTE_NO_KEY_PRESSED;
-        if (dw2102_i2c_transfer(&d->i2c_adap, msg, 1) == 1) {
-                for (i = 0; i < ARRAY_SIZE(dw210x_rc_keys); i++) {
-                        if (dw210x_rc_keys[i].data == msg[0].buf[0]) {
+        if (dw2102_i2c_transfer(&d->i2c_adap, &msg, 1) == 1) {
+                for (i = 0; i < keymap_size ; i++) {
+                        if (keymap[i].data == msg.buf[0]) {
                                 *state = REMOTE_KEY_PRESSED;
-                                *event = dw210x_rc_keys[i].event;
-                                st->last_key_pressed =
-                                        dw210x_rc_keys[i].event;
+                                *event = keymap[i].event;
                                 break;
                         }
-                st->last_key_pressed = 0;
+
                 }
+
+                if ((*state) == REMOTE_KEY_PRESSED)
+                        deb_rc("%s: found rc key: %x, %x, event: %x\n",
+                                        __func__, key[0], key[1], (*event));
+                else if (key[0] != 0xff)
+                        deb_rc("%s: unknown rc key: %x, %x\n",
+                                        __func__, key[0], key[1]);
+
         }
-        /* info("key: %x %x\n",key[0],key[1]); */
+
         return 0;
 }
 
 static struct usb_device_id dw2102_table[] = {
         {USB_DEVICE(USB_VID_CYPRESS, USB_PID_DW2102)},
         {USB_DEVICE(USB_VID_CYPRESS, 0x2101)},
-        {USB_DEVICE(USB_VID_CYPRESS, 0x2104)},
-        {USB_DEVICE(0x9022, 0xd650)},
+        {USB_DEVICE(USB_VID_CYPRESS, USB_PID_DW2104)},
+        {USB_DEVICE(0x9022, USB_PID_TEVII_S650)},
         {USB_DEVICE(USB_VID_TERRATEC, USB_PID_CINERGY_S)},
+        {USB_DEVICE(USB_VID_CYPRESS, USB_PID_DW3101)},
         { }
 };
 
@@ -642,11 +852,16 @@ static int dw2102_load_firmware(struct usb_device *dev,
                 }
                 /* init registers */
                 switch (dev->descriptor.idProduct) {
+                case USB_PID_TEVII_S650:
+                        dw2104_properties.rc_key_map = tevii_rc_keys;
+                        dw2104_properties.rc_key_map_size =
+                                        ARRAY_SIZE(tevii_rc_keys);
                 case USB_PID_DW2104:
-                case 0xd650:
                         reset = 1;
                         dw210x_op_rw(dev, 0xc4, 0x0000, 0, &reset, 1,
                                         DW210X_WRITE_MSG);
+                        /* break omitted intentionally */
+                case USB_PID_DW3101:
                         reset = 0;
                         dw210x_op_rw(dev, 0xbf, 0x0040, 0, &reset, 0,
                                         DW210X_WRITE_MSG);
@@ -690,6 +905,7 @@ static int dw2102_load_firmware(struct usb_device *dev,
                                         DW210X_READ_MSG);
                         break;
                 }
+
                 msleep(100);
                 kfree(p);
         }
@@ -700,7 +916,6 @@ static struct dvb_usb_device_properties dw2102_properties = {
         .caps = DVB_USB_IS_AN_I2C_ADAPTER,
         .usb_ctrl = DEVICE_SPECIFIC,
         .firmware = "dvb-usb-dw2102.fw",
-        .size_of_priv = sizeof(struct dw210x_state),
         .no_reconnect = 1,
 
         .i2c_algo = &dw2102_serit_i2c_algo,
@@ -714,7 +929,7 @@ static struct dvb_usb_device_properties dw2102_properties = {
         .num_adapters = 1,
         .download_firmware = dw2102_load_firmware,
         .read_mac_address = dw210x_read_mac_address,
-                .adapter = {
+        .adapter = {
                 {
                         .frontend_attach = dw2102_frontend_attach,
                         .streaming_ctrl = NULL,
@@ -752,7 +967,6 @@ static struct dvb_usb_device_properties dw2104_properties = {
         .caps = DVB_USB_IS_AN_I2C_ADAPTER,
         .usb_ctrl = DEVICE_SPECIFIC,
         .firmware = "dvb-usb-dw2104.fw",
-        .size_of_priv = sizeof(struct dw210x_state),
         .no_reconnect = 1,
 
         .i2c_algo = &dw2104_i2c_algo,
@@ -796,12 +1010,57 @@ static struct dvb_usb_device_properties dw2104_properties = {
         }
 };
 
+static struct dvb_usb_device_properties dw3101_properties = {
+        .caps = DVB_USB_IS_AN_I2C_ADAPTER,
+        .usb_ctrl = DEVICE_SPECIFIC,
+        .firmware = "dvb-usb-dw3101.fw",
+        .no_reconnect = 1,
+
+        .i2c_algo = &dw3101_i2c_algo,
+        .rc_key_map = dw210x_rc_keys,
+        .rc_key_map_size = ARRAY_SIZE(dw210x_rc_keys),
+        .rc_interval = 150,
+        .rc_query = dw2102_rc_query,
+
+        .generic_bulk_ctrl_endpoint = 0x81,
+        /* parameter for the MPEG2-data transfer */
+        .num_adapters = 1,
+        .download_firmware = dw2102_load_firmware,
+        .read_mac_address = dw210x_read_mac_address,
+        .adapter = {
+                {
+                        .frontend_attach = dw3101_frontend_attach,
+                        .streaming_ctrl = NULL,
+                        .tuner_attach = dw3101_tuner_attach,
+                        .stream = {
+                                .type = USB_BULK,
+                                .count = 8,
+                                .endpoint = 0x82,
+                                .u = {
+                                        .bulk = {
+                                                .buffersize = 4096,
+                                        }
+                                }
+                        },
+                }
+        },
+        .num_device_descs = 1,
+        .devices = {
+                { "DVBWorld DVB-C 3101 USB2.0",
+                        {&dw2102_table[5], NULL},
+                        {NULL},
+                },
+        }
+};
+
 static int dw2102_probe(struct usb_interface *intf,
                 const struct usb_device_id *id)
 {
         if (0 == dvb_usb_device_init(intf, &dw2102_properties,
                         THIS_MODULE, NULL, adapter_nr) ||
             0 == dvb_usb_device_init(intf, &dw2104_properties,
+                        THIS_MODULE, NULL, adapter_nr) ||
+            0 == dvb_usb_device_init(intf, &dw3101_properties,
                         THIS_MODULE, NULL, adapter_nr)) {
                 return 0;
         }
@@ -833,6 +1092,8 @@ module_init(dw2102_module_init);
 module_exit(dw2102_module_exit);
 
 MODULE_AUTHOR("Igor M. Liplianin (c) liplianin@me.by");
-MODULE_DESCRIPTION("Driver for DVBWorld DVB-S 2101, 2102, DVB-S2 2104 USB2.0 device");
+MODULE_DESCRIPTION("Driver for DVBWorld DVB-S 2101, 2102, DVB-S2 2104,"
+                                " DVB-C 3101 USB2.0,"
+                                " TeVii S600, S650 USB2.0 devices");
 MODULE_VERSION("0.1");
 MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/dvb-usb/dw2102.h b/drivers/media/dvb/dvb-usb/dw2102.h
index e3370734e95a..5cd0b0eb6ce1 100644
--- a/drivers/media/dvb/dvb-usb/dw2102.h
+++ b/drivers/media/dvb/dvb-usb/dw2102.h
@@ -5,4 +5,5 @@
 #include "dvb-usb.h"
 
 #define deb_xfer(args...) dprintk(dvb_usb_dw2102_debug, 0x02, args)
+#define deb_rc(args...)   dprintk(dvb_usb_dw2102_debug, 0x04, args)
 #endif
diff --git a/drivers/media/dvb/dvb-usb/gp8psk.c b/drivers/media/dvb/dvb-usb/gp8psk.c
index 3dd6843864ed..afb444db43ad 100644
--- a/drivers/media/dvb/dvb-usb/gp8psk.c
+++ b/drivers/media/dvb/dvb-usb/gp8psk.c
@@ -223,7 +223,7 @@ static struct usb_device_id gp8psk_usb_table [] = {
             { USB_DEVICE(USB_VID_GENPIX, USB_PID_GENPIX_8PSK_REV_1_WARM) },
             { USB_DEVICE(USB_VID_GENPIX, USB_PID_GENPIX_8PSK_REV_2) },
             { USB_DEVICE(USB_VID_GENPIX, USB_PID_GENPIX_SKYWALKER_1) },
-            { USB_DEVICE(USB_VID_GENPIX, USB_PID_GENPIX_SKYWALKER_CW3K) },
+/*          { USB_DEVICE(USB_VID_GENPIX, USB_PID_GENPIX_SKYWALKER_CW3K) }, */
             { 0 },
 };
 MODULE_DEVICE_TABLE(usb, gp8psk_usb_table);
@@ -254,7 +254,7 @@ static struct dvb_usb_device_properties gp8psk_properties = {
 
         .generic_bulk_ctrl_endpoint = 0x01,
 
-        .num_device_descs = 4,
+        .num_device_descs = 3,
         .devices = {
                 { .name = "Genpix 8PSK-to-USB2 Rev.1 DVB-S receiver",
                   .cold_ids = { &gp8psk_usb_table[0], NULL },
@@ -268,10 +268,6 @@ static struct dvb_usb_device_properties gp8psk_properties = {
                   .cold_ids = { NULL },
                   .warm_ids = { &gp8psk_usb_table[3], NULL },
                 },
-                { .name = "Genpix SkyWalker-CW3K DVB-S receiver",
-                  .cold_ids = { NULL },
-                  .warm_ids = { &gp8psk_usb_table[4], NULL },
-                },
                 { NULL },
         }
 };
diff --git a/drivers/media/dvb/firewire/firedtv-1394.c b/drivers/media/dvb/firewire/firedtv-1394.c
index 4e207658c5d9..2b6eeeab5b25 100644
--- a/drivers/media/dvb/firewire/firedtv-1394.c
+++ b/drivers/media/dvb/firewire/firedtv-1394.c
@@ -225,7 +225,7 @@ fail_free:
 
 static int node_remove(struct device *dev)
 {
-        struct firedtv *fdtv = dev->driver_data;
+        struct firedtv *fdtv = dev_get_drvdata(dev);
 
         fdtv_dvb_unregister(fdtv);
 
@@ -242,7 +242,7 @@ static int node_remove(struct device *dev)
 
 static int node_update(struct unit_directory *ud)
 {
-        struct firedtv *fdtv = ud->device.driver_data;
+        struct firedtv *fdtv = dev_get_drvdata(&ud->device);
 
         if (fdtv->isochannel >= 0)
                 cmp_establish_pp_connection(fdtv, fdtv->subunit,
diff --git a/drivers/media/dvb/firewire/firedtv-dvb.c b/drivers/media/dvb/firewire/firedtv-dvb.c
index 9d308dd32a5c..5742fde79d99 100644
--- a/drivers/media/dvb/firewire/firedtv-dvb.c
+++ b/drivers/media/dvb/firewire/firedtv-dvb.c
@@ -268,7 +268,7 @@ struct firedtv *fdtv_alloc(struct device *dev,
         if (!fdtv)
                 return NULL;
 
-        dev->driver_data        = fdtv;
+        dev_set_drvdata(dev, fdtv);
         fdtv->device            = dev;
         fdtv->isochannel        = -1;
         fdtv->voltage           = 0xff;
diff --git a/drivers/media/dvb/firewire/firedtv-rc.c b/drivers/media/dvb/firewire/firedtv-rc.c
index 46a6324d7b73..27bca2e283df 100644
--- a/drivers/media/dvb/firewire/firedtv-rc.c
+++ b/drivers/media/dvb/firewire/firedtv-rc.c
@@ -18,7 +18,7 @@
 #include "firedtv.h"
 
 /* fixed table with older keycodes, geared towards MythTV */
-const static u16 oldtable[] = {
+static const u16 oldtable[] = {
 
         /* code from device: 0x4501...0x451f */
 
@@ -62,7 +62,7 @@ const static u16 oldtable[] = {
 };
 
 /* user-modifiable table for a remote as sold in 2008 */
-const static u16 keytable[] = {
+static const u16 keytable[] = {
 
         /* code from device: 0x0300...0x031f */
 
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index 23e4cffeba38..be967ac09a39 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -35,6 +35,21 @@ config DVB_STB6100
           A Silicon tuner from ST used in conjunction with the STB0899
           demodulator. Say Y when you want to support this tuner.
 
+config DVB_STV090x
+        tristate "STV0900/STV0903(A/B) based"
+        depends on DVB_CORE && I2C
+        default m if DVB_FE_CUSTOMISE
+        help
+          DVB-S/S2/DSS Multistandard Professional/Broadcast demodulators.
+          Say Y when you want to support these frontends.
+
+config DVB_STV6110x
+        tristate "STV6110/(A) based tuners"
+        depends on DVB_CORE && I2C
+        default m if DVB_FE_CUSTOMISE
+        help
+          A Silicon tuner that supports DVB-S and DVB-S2 modes
+
 comment "DVB-S (satellite) frontends"
         depends on DVB_CORE
 
@@ -506,6 +521,13 @@ config DVB_ISL6421
         help
           An SEC control chip.
 
+config DVB_ISL6423
+        tristate "ISL6423 SEC controller"
+        depends on DVB_CORE && I2C
+        default m if DVB_FE_CUSTOMISE
+        help
+          A SEC controller chip from Intersil
+
 config DVB_LGS8GL5
         tristate "Silicon Legend LGS-8GL5 demodulator (OFDM)"
         depends on DVB_CORE && I2C
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index bc2b00abd106..832473c1e512 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -71,4 +71,6 @@ obj-$(CONFIG_DVB_STB6000) += stb6000.o
 obj-$(CONFIG_DVB_S921) += s921.o
 obj-$(CONFIG_DVB_STV6110) += stv6110.o
 obj-$(CONFIG_DVB_STV0900) += stv0900.o
-
+obj-$(CONFIG_DVB_STV090x) += stv090x.o
+obj-$(CONFIG_DVB_STV6110x) += stv6110x.o
+obj-$(CONFIG_DVB_ISL6423) += isl6423.o
diff --git a/drivers/media/dvb/frontends/af9013.c b/drivers/media/dvb/frontends/af9013.c
index b2b50fb4cfd3..136c5863d81b 100644
--- a/drivers/media/dvb/frontends/af9013.c
+++ b/drivers/media/dvb/frontends/af9013.c
@@ -1455,7 +1455,7 @@ static int af9013_download_firmware(struct af9013_state *state)
                 af9013_ops.info.name);
 
         /* request the firmware, this will block and timeout */
-        ret = request_firmware(&fw, fw_file,  &state->i2c->dev);
+        ret = request_firmware(&fw, fw_file, state->i2c->dev.parent);
         if (ret) {
                 err("did not find the firmware file. (%s) "
                         "Please see linux/Documentation/dvb/ for more details" \
diff --git a/drivers/media/dvb/frontends/au8522_dig.c b/drivers/media/dvb/frontends/au8522_dig.c
index 35731258bb0a..956b80f4979c 100644
--- a/drivers/media/dvb/frontends/au8522_dig.c
+++ b/drivers/media/dvb/frontends/au8522_dig.c
@@ -367,11 +367,90 @@ static struct {
         { 0x8231, 0x13 },
 };
 
-/* QAM Modulation table */
+/* QAM64 Modulation table */
 static struct {
         u16 reg;
         u16 data;
-} QAM_mod_tab[] = {
+} QAM64_mod_tab[] = {
+        { 0x00a3, 0x09 },
+        { 0x00a4, 0x00 },
+        { 0x0081, 0xc4 },
+        { 0x00a5, 0x40 },
+        { 0x00aa, 0x77 },
+        { 0x00ad, 0x77 },
+        { 0x00a6, 0x67 },
+        { 0x0262, 0x20 },
+        { 0x021c, 0x30 },
+        { 0x00b8, 0x3e },
+        { 0x00b9, 0xf0 },
+        { 0x00ba, 0x01 },
+        { 0x00bb, 0x18 },
+        { 0x00bc, 0x50 },
+        { 0x00bd, 0x00 },
+        { 0x00be, 0xea },
+        { 0x00bf, 0xef },
+        { 0x00c0, 0xfc },
+        { 0x00c1, 0xbd },
+        { 0x00c2, 0x1f },
+        { 0x00c3, 0xfc },
+        { 0x00c4, 0xdd },
+        { 0x00c5, 0xaf },
+        { 0x00c6, 0x00 },
+        { 0x00c7, 0x38 },
+        { 0x00c8, 0x30 },
+        { 0x00c9, 0x05 },
+        { 0x00ca, 0x4a },
+        { 0x00cb, 0xd0 },
+        { 0x00cc, 0x01 },
+        { 0x00cd, 0xd9 },
+        { 0x00ce, 0x6f },
+        { 0x00cf, 0xf9 },
+        { 0x00d0, 0x70 },
+        { 0x00d1, 0xdf },
+        { 0x00d2, 0xf7 },
+        { 0x00d3, 0xc2 },
+        { 0x00d4, 0xdf },
+        { 0x00d5, 0x02 },
+        { 0x00d6, 0x9a },
+        { 0x00d7, 0xd0 },
+        { 0x0250, 0x0d },
+        { 0x0251, 0xcd },
+        { 0x0252, 0xe0 },
+        { 0x0253, 0x05 },
+        { 0x0254, 0xa7 },
+        { 0x0255, 0xff },
+        { 0x0256, 0xed },
+        { 0x0257, 0x5b },
+        { 0x0258, 0xae },
+        { 0x0259, 0xe6 },
+        { 0x025a, 0x3d },
+        { 0x025b, 0x0f },
+        { 0x025c, 0x0d },
+        { 0x025d, 0xea },
+        { 0x025e, 0xf2 },
+        { 0x025f, 0x51 },
+        { 0x0260, 0xf5 },
+        { 0x0261, 0x06 },
+        { 0x021a, 0x00 },
+        { 0x0546, 0x40 },
+        { 0x0210, 0xc7 },
+        { 0x0211, 0xaa },
+        { 0x0212, 0xab },
+        { 0x0213, 0x02 },
+        { 0x0502, 0x00 },
+        { 0x0121, 0x04 },
+        { 0x0122, 0x04 },
+        { 0x052e, 0x10 },
+        { 0x00a4, 0xca },
+        { 0x00a7, 0x40 },
+        { 0x0526, 0x01 },
+};
+
+/* QAM256 Modulation table */
+static struct {
+        u16 reg;
+        u16 data;
+} QAM256_mod_tab[] = {
         { 0x80a3, 0x09 },
         { 0x80a4, 0x00 },
         { 0x8081, 0xc4 },
@@ -464,12 +543,19 @@ static int au8522_enable_modulation(struct dvb_frontend *fe,
                 au8522_set_if(fe, state->config->vsb_if);
                 break;
         case QAM_64:
+                dprintk("%s() QAM 64\n", __func__);
+                for (i = 0; i < ARRAY_SIZE(QAM64_mod_tab); i++)
+                        au8522_writereg(state,
+                                QAM64_mod_tab[i].reg,
+                                QAM64_mod_tab[i].data);
+                au8522_set_if(fe, state->config->qam_if);
+                break;
         case QAM_256:
-                dprintk("%s() QAM 64/256\n", __func__);
-                for (i = 0; i < ARRAY_SIZE(QAM_mod_tab); i++)
+                dprintk("%s() QAM 256\n", __func__);
+                for (i = 0; i < ARRAY_SIZE(QAM256_mod_tab); i++)
                         au8522_writereg(state,
-                                QAM_mod_tab[i].reg,
-                                QAM_mod_tab[i].data);
+                                QAM256_mod_tab[i].reg,
+                                QAM256_mod_tab[i].data);
                 au8522_set_if(fe, state->config->qam_if);
                 break;
         default:
diff --git a/drivers/media/dvb/frontends/cx24116.c b/drivers/media/dvb/frontends/cx24116.c
index 9b9f57264cef..2410d8b59b6b 100644
--- a/drivers/media/dvb/frontends/cx24116.c
+++ b/drivers/media/dvb/frontends/cx24116.c
@@ -492,7 +492,7 @@ static int cx24116_firmware_ondemand(struct dvb_frontend *fe)
                 printk(KERN_INFO "%s: Waiting for firmware upload (%s)...\n",
                         __func__, CX24116_DEFAULT_FIRMWARE);
                 ret = request_firmware(&fw, CX24116_DEFAULT_FIRMWARE,
-                        &state->i2c->dev);
+                        state->i2c->dev.parent);
                 printk(KERN_INFO "%s: Waiting for firmware upload(2)...\n",
                         __func__);
                 if (ret) {
diff --git a/drivers/media/dvb/frontends/drx397xD.c b/drivers/media/dvb/frontends/drx397xD.c
index 172f1f928f02..010075535221 100644
--- a/drivers/media/dvb/frontends/drx397xD.c
+++ b/drivers/media/dvb/frontends/drx397xD.c
@@ -123,10 +123,10 @@ static int drx_load_fw(struct drx397xD_state *s, enum fw_ix ix)
         }
         memset(&fw[ix].data[0], 0, sizeof(fw[0].data));
 
-        if (request_firmware(&fw[ix].file, fw[ix].name, &s->i2c->dev) != 0) {
+        rc = request_firmware(&fw[ix].file, fw[ix].name, s->i2c->dev.parent);
+        if (rc != 0) {
                 printk(KERN_ERR "%s: Firmware \"%s\" not available\n",
                        mod_name, fw[ix].name);
-                rc = -ENOENT;
                 goto exit_err;
         }
 
diff --git a/drivers/media/dvb/frontends/isl6423.c b/drivers/media/dvb/frontends/isl6423.c
new file mode 100644
index 000000000000..dca5bebfeeb5
--- /dev/null
+++ b/drivers/media/dvb/frontends/isl6423.c
@@ -0,0 +1,308 @@
+/*
+        Intersil ISL6423 SEC and LNB Power supply controller
+
+        Copyright (C) Manu Abraham <abraham.manu@gmail.com>
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+
+#include "dvb_frontend.h"
+#include "isl6423.h"
+
+static unsigned int verbose;
+module_param(verbose, int, 0644);
+MODULE_PARM_DESC(verbose, "Set Verbosity level");
+
+#define FE_ERROR                                0
+#define FE_NOTICE                               1
+#define FE_INFO                                 2
+#define FE_DEBUG                                3
+#define FE_DEBUGREG                             4
+
+#define dprintk(__y, __z, format, arg...) do {                                          \
+        if (__z) {                                                                      \
+                if      ((verbose > FE_ERROR) && (verbose > __y))                       \
+                        printk(KERN_ERR "%s: " format "\n", __func__ , ##arg);          \
+                else if ((verbose > FE_NOTICE) && (verbose > __y))                      \
+                        printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg);       \
+                else if ((verbose > FE_INFO) && (verbose > __y))                        \
+                        printk(KERN_INFO "%s: " format "\n", __func__ , ##arg);         \
+                else if ((verbose > FE_DEBUG) && (verbose > __y))                       \
+                        printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg);        \
+        } else {                                                                        \
+                if (verbose > __y)                                                      \
+                        printk(format, ##arg);                                          \
+        }                                                                               \
+} while (0)
+
+struct isl6423_dev {
+        const struct isl6423_config     *config;
+        struct i2c_adapter              *i2c;
+
+        u8 reg_3;
+        u8 reg_4;
+
+        unsigned int verbose;
+};
+
+static int isl6423_write(struct isl6423_dev *isl6423, u8 reg)
+{
+        struct i2c_adapter *i2c = isl6423->i2c;
+        u8 addr                 = isl6423->config->addr;
+        int err = 0;
+
+        struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = &reg, .len = 1 };
+
+        dprintk(FE_DEBUG, 1, "write reg %02X", reg);
+        err = i2c_transfer(i2c, &msg, 1);
+        if (err < 0)
+                goto exit;
+        return 0;
+
+exit:
+        dprintk(FE_ERROR, 1, "I/O error <%d>", err);
+        return err;
+}
+
+static int isl6423_set_modulation(struct dvb_frontend *fe)
+{
+        struct isl6423_dev *isl6423             = (struct isl6423_dev *) fe->sec_priv;
+        const struct isl6423_config *config     = isl6423->config;
+        int err = 0;
+        u8 reg_2 = 0;
+
+        reg_2 = 0x01 << 5;
+
+        if (config->mod_extern)
+                reg_2 |= (1 << 3);
+        else
+                reg_2 |= (1 << 4);
+
+        err = isl6423_write(isl6423, reg_2);
+        if (err < 0)
+                goto exit;
+        return 0;
+
+exit:
+        dprintk(FE_ERROR, 1, "I/O error <%d>", err);
+        return err;
+}
+
+static int isl6423_voltage_boost(struct dvb_frontend *fe, long arg)
+{
+        struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
+        u8 reg_3 = isl6423->reg_3;
+        u8 reg_4 = isl6423->reg_4;
+        int err = 0;
+
+        if (arg) {
+                /* EN = 1, VSPEN = 1, VBOT = 1 */
+                reg_4 |= (1 << 4);
+                reg_4 |= 0x1;
+                reg_3 |= (1 << 3);
+        } else {
+                /* EN = 1, VSPEN = 1, VBOT = 0 */
+                reg_4 |= (1 << 4);
+                reg_4 &= ~0x1;
+                reg_3 |= (1 << 3);
+        }
+        err = isl6423_write(isl6423, reg_3);
+        if (err < 0)
+                goto exit;
+
+        err = isl6423_write(isl6423, reg_4);
+        if (err < 0)
+                goto exit;
+
+        isl6423->reg_3 = reg_3;
+        isl6423->reg_4 = reg_4;
+
+        return 0;
+exit:
+        dprintk(FE_ERROR, 1, "I/O error <%d>", err);
+        return err;
+}
+
+
+static int isl6423_set_voltage(struct dvb_frontend *fe,
+                               enum fe_sec_voltage voltage)
+{
+        struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
+        u8 reg_3 = isl6423->reg_3;
+        u8 reg_4 = isl6423->reg_4;
+        int err = 0;
+
+        switch (voltage) {
+        case SEC_VOLTAGE_OFF:
+                /* EN = 0 */
+                reg_4 &= ~(1 << 4);
+                break;
+
+        case SEC_VOLTAGE_13:
+                /* EN = 1, VSPEN = 1, VTOP = 0, VBOT = 0 */
+                reg_4 |= (1 << 4);
+                reg_4 &= ~0x3;
+                reg_3 |= (1 << 3);
+                break;
+
+        case SEC_VOLTAGE_18:
+                /* EN = 1, VSPEN = 1, VTOP = 1, VBOT = 0 */
+                reg_4 |= (1 << 4);
+                reg_4 |=  0x2;
+                reg_4 &= ~0x1;
+                reg_3 |= (1 << 3);
+                break;
+
+        default:
+                break;
+        }
+        err = isl6423_write(isl6423, reg_3);
+        if (err < 0)
+                goto exit;
+
+        err = isl6423_write(isl6423, reg_4);
+        if (err < 0)
+                goto exit;
+
+        isl6423->reg_3 = reg_3;
+        isl6423->reg_4 = reg_4;
+
+        return 0;
+exit:
+        dprintk(FE_ERROR, 1, "I/O error <%d>", err);
+        return err;
+}
+
+static int isl6423_set_current(struct dvb_frontend *fe)
+{
+        struct isl6423_dev *isl6423             = (struct isl6423_dev *) fe->sec_priv;
+        u8 reg_3 = isl6423->reg_3;
+        const struct isl6423_config *config     = isl6423->config;
+        int err = 0;
+
+        switch (config->current_max) {
+        case SEC_CURRENT_275m:
+                /* 275mA */
+                /* ISELH = 0, ISELL = 0 */
+                reg_3 &= ~0x3;
+                break;
+
+        case SEC_CURRENT_515m:
+                /* 515mA */
+                /* ISELH = 0, ISELL = 1 */
+                reg_3 &= ~0x2;
+                reg_3 |=  0x1;
+                break;
+
+        case SEC_CURRENT_635m:
+                /* 635mA */
+                /* ISELH = 1, ISELL = 0 */
+                reg_3 &= ~0x1;
+                reg_3 |=  0x2;
+                break;
+
+        case SEC_CURRENT_800m:
+                /* 800mA */
+                /* ISELH = 1, ISELL = 1 */
+                reg_3 |= 0x3;
+                break;
+        }
+
+        err = isl6423_write(isl6423, reg_3);
+        if (err < 0)
+                goto exit;
+
+        switch (config->curlim) {
+        case SEC_CURRENT_LIM_ON:
+                /* DCL = 0 */
+                reg_3 &= ~0x10;
+                break;
+
+        case SEC_CURRENT_LIM_OFF:
+                /* DCL = 1 */
+                reg_3 |= 0x10;
+                break;
+        }
+
+        err = isl6423_write(isl6423, reg_3);
+        if (err < 0)
+                goto exit;
+
+        isl6423->reg_3 = reg_3;
+
+        return 0;
+exit:
+        dprintk(FE_ERROR, 1, "I/O error <%d>", err);
+        return err;
+}
+
+static void isl6423_release(struct dvb_frontend *fe)
+{
+        isl6423_set_voltage(fe, SEC_VOLTAGE_OFF);
+
+        kfree(fe->sec_priv);
+        fe->sec_priv = NULL;
+}
+
+struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe,
+                                    struct i2c_adapter *i2c,
+                                    const struct isl6423_config *config)
+{
+        struct isl6423_dev *isl6423;
+
+        isl6423 = kzalloc(sizeof(struct isl6423_dev), GFP_KERNEL);
+        if (!isl6423)
+                return NULL;
+
+        isl6423->config = config;
+        isl6423->i2c    = i2c;
+        fe->sec_priv    = isl6423;
+
+        /* SR3H = 0, SR3M = 1, SR3L = 0 */
+        isl6423->reg_3 = 0x02 << 5;
+        /* SR4H = 0, SR4M = 1, SR4L = 1 */
+        isl6423->reg_4 = 0x03 << 5;
+
+        if (isl6423_set_current(fe))
+                goto exit;
+
+        if (isl6423_set_modulation(fe))
+                goto exit;
+
+        fe->ops.release_sec             = isl6423_release;
+        fe->ops.set_voltage             = isl6423_set_voltage;
+        fe->ops.enable_high_lnb_voltage = isl6423_voltage_boost;
+        isl6423->verbose                = verbose;
+
+        return fe;
+
+exit:
+        kfree(isl6423);
+        fe->sec_priv = NULL;
+        return NULL;
+}
+EXPORT_SYMBOL(isl6423_attach);
+
+MODULE_DESCRIPTION("ISL6423 SEC");
+MODULE_AUTHOR("Manu Abraham");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/isl6423.h b/drivers/media/dvb/frontends/isl6423.h
new file mode 100644
index 000000000000..e1a37fba01ca
--- /dev/null
+++ b/drivers/media/dvb/frontends/isl6423.h
@@ -0,0 +1,63 @@
+/*
+        Intersil ISL6423 SEC and LNB Power supply controller
+
+        Copyright (C) Manu Abraham <abraham.manu@gmail.com>
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __ISL_6423_H
+#define __ISL_6423_H
+
+#include <linux/dvb/frontend.h>
+
+enum isl6423_current {
+        SEC_CURRENT_275m = 0,
+        SEC_CURRENT_515m,
+        SEC_CURRENT_635m,
+        SEC_CURRENT_800m,
+};
+
+enum isl6423_curlim {
+        SEC_CURRENT_LIM_ON = 1,
+        SEC_CURRENT_LIM_OFF
+};
+
+struct isl6423_config {
+        enum isl6423_current current_max;
+        enum isl6423_curlim curlim;
+        u8 addr;
+        u8 mod_extern;
+};
+
+#if defined(CONFIG_DVB_ISL6423) || (defined(CONFIG_DVB_ISL6423_MODULE) && defined(MODULE))
+
+
+extern struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe,
+                                           struct i2c_adapter *i2c,
+                                           const struct isl6423_config *config);
+
+#else
+static inline struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe,
+                                                  struct i2c_adapter *i2c,
+                                                  const struct isl6423_config *config)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return NULL;
+}
+
+#endif /* CONFIG_DVB_ISL6423 */
+
+#endif /* __ISL_6423_H */
diff --git a/drivers/media/dvb/frontends/lgdt3305.c b/drivers/media/dvb/frontends/lgdt3305.c
index d92d0557a80b..fde8c59700fb 100644
--- a/drivers/media/dvb/frontends/lgdt3305.c
+++ b/drivers/media/dvb/frontends/lgdt3305.c
@@ -19,6 +19,7 @@
  *
  */
 
+#include <asm/div64.h>
 #include <linux/dvb/frontend.h>
 #include "dvb_math.h"
 #include "lgdt3305.h"
@@ -496,27 +497,15 @@ static int lgdt3305_set_if(struct lgdt3305_state *state,
 
         nco = if_freq_khz / 10;
 
-#define LGDT3305_64BIT_DIVISION_ENABLED 0
-        /* FIXME: 64bit division disabled to avoid linking error:
-         * WARNING: "__udivdi3" [lgdt3305.ko] undefined!
-         */
         switch (param->u.vsb.modulation) {
         case VSB_8:
-#if LGDT3305_64BIT_DIVISION_ENABLED
                 nco <<= 24;
-                nco /= 625;
-#else
-                nco *= ((1 << 24) / 625);
-#endif
+                do_div(nco, 625);
                 break;
         case QAM_64:
         case QAM_256:
-#if LGDT3305_64BIT_DIVISION_ENABLED
                 nco <<= 28;
-                nco /= 625;
-#else
-                nco *= ((1 << 28) / 625);
-#endif
+                do_div(nco, 625);
                 break;
         default:
                 return -EINVAL;
diff --git a/drivers/media/dvb/frontends/lgs8gxx.c b/drivers/media/dvb/frontends/lgs8gxx.c
index f9785dfe735b..fde27645bbed 100644
--- a/drivers/media/dvb/frontends/lgs8gxx.c
+++ b/drivers/media/dvb/frontends/lgs8gxx.c
@@ -37,14 +37,14 @@
         } while (0)
 
 static int debug;
-static int fake_signal_str;
+static int fake_signal_str = 1;
 
 module_param(debug, int, 0644);
 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 
 module_param(fake_signal_str, int, 0644);
 MODULE_PARM_DESC(fake_signal_str, "fake signal strength for LGS8913."
-"Signal strength calculation is slow.(default:off).");
+"Signal strength calculation is slow.(default:on).");
 
 /* LGS8GXX internal helper functions */
 
@@ -610,7 +610,7 @@ static int lgs8gxx_read_signal_agc(struct lgs8gxx_state *priv, u16 *signal)
         else
                 cat = 0;
 
-        *signal = cat;
+        *signal = cat * 65535 / 5;
 
         return 0;
 }
@@ -630,8 +630,8 @@ static int lgs8913_read_signal_strength(struct lgs8gxx_state *priv, u16 *signal)
 
         if (fake_signal_str) {
                 if ((t & 0xC0) == 0xC0) {
-                        dprintk("Fake signal strength as 50\n");
-                        *signal = 0x32;
+                        dprintk("Fake signal strength\n");
+                        *signal = 0x7FFF;
                 } else
                         *signal = 0;
                 return 0;
diff --git a/drivers/media/dvb/frontends/lnbp21.c b/drivers/media/dvb/frontends/lnbp21.c
index 1dcc56f32bff..71f607fe8fc7 100644
--- a/drivers/media/dvb/frontends/lnbp21.c
+++ b/drivers/media/dvb/frontends/lnbp21.c
@@ -133,7 +133,7 @@ static struct dvb_frontend *lnbx2x_attach(struct dvb_frontend *fe,
         /* override frontend ops */
         fe->ops.set_voltage = lnbp21_set_voltage;
         fe->ops.enable_high_lnb_voltage = lnbp21_enable_high_lnb_voltage;
-        printk(KERN_INFO "LNBx2x attached on addr=%x", lnbp21->i2c_addr);
+        printk(KERN_INFO "LNBx2x attached on addr=%x\n", lnbp21->i2c_addr);
 
         return fe;
 }
diff --git a/drivers/media/dvb/frontends/mt312.c b/drivers/media/dvb/frontends/mt312.c
index 5ac9b15920f8..a621f727935f 100644
--- a/drivers/media/dvb/frontends/mt312.c
+++ b/drivers/media/dvb/frontends/mt312.c
@@ -77,7 +77,7 @@ static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
         ret = i2c_transfer(state->i2c, msg, 2);
 
         if (ret != 2) {
-                printk(KERN_ERR "%s: ret == %d\n", __func__, ret);
+                printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret);
                 return -EREMOTEIO;
         }
 
diff --git a/drivers/media/dvb/frontends/nxt200x.c b/drivers/media/dvb/frontends/nxt200x.c
index a8429ebfa8a2..eac20650499f 100644
--- a/drivers/media/dvb/frontends/nxt200x.c
+++ b/drivers/media/dvb/frontends/nxt200x.c
@@ -879,7 +879,8 @@ static int nxt2002_init(struct dvb_frontend* fe)
 
         /* request the firmware, this will block until someone uploads it */
         printk("nxt2002: Waiting for firmware upload (%s)...\n", NXT2002_DEFAULT_FIRMWARE);
-        ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE, &state->i2c->dev);
+        ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE,
+                               state->i2c->dev.parent);
         printk("nxt2002: Waiting for firmware upload(2)...\n");
         if (ret) {
                 printk("nxt2002: No firmware uploaded (timeout or file not found?)\n");
@@ -943,7 +944,8 @@ static int nxt2004_init(struct dvb_frontend* fe)
 
         /* request the firmware, this will block until someone uploads it */
         printk("nxt2004: Waiting for firmware upload (%s)...\n", NXT2004_DEFAULT_FIRMWARE);
-        ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE, &state->i2c->dev);
+        ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE,
+                               state->i2c->dev.parent);
         printk("nxt2004: Waiting for firmware upload(2)...\n");
         if (ret) {
                 printk("nxt2004: No firmware uploaded (timeout or file not found?)\n");
diff --git a/drivers/media/dvb/frontends/or51132.c b/drivers/media/dvb/frontends/or51132.c
index 5ed32544de39..8133ea3cddd7 100644
--- a/drivers/media/dvb/frontends/or51132.c
+++ b/drivers/media/dvb/frontends/or51132.c
@@ -340,7 +340,7 @@ static int or51132_set_parameters(struct dvb_frontend* fe,
                 }
                 printk("or51132: Waiting for firmware upload(%s)...\n",
                        fwname);
-                ret = request_firmware(&fw, fwname, &state->i2c->dev);
+                ret = request_firmware(&fw, fwname, state->i2c->dev.parent);
                 if (ret) {
                         printk(KERN_WARNING "or51132: No firmware up"
                                "loaded(timeout or file not found?)\n");
diff --git a/drivers/media/dvb/frontends/stv0900_priv.h b/drivers/media/dvb/frontends/stv0900_priv.h
index 762d5af62d7a..67dc8ec634e2 100644
--- a/drivers/media/dvb/frontends/stv0900_priv.h
+++ b/drivers/media/dvb/frontends/stv0900_priv.h
@@ -60,8 +60,6 @@
                 } \
         } while (0)
 
-#define dmd_choose(a, b)        (demod = STV0900_DEMOD_2 ? b : a))
-
 static int stvdebug;
 
 #define dprintk(args...) \
diff --git a/drivers/media/dvb/frontends/stv090x.c b/drivers/media/dvb/frontends/stv090x.c
new file mode 100644
index 000000000000..96ef745a2e4e
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv090x.c
@@ -0,0 +1,4299 @@
+/*
+        STV0900/0903 Multistandard Broadcast Frontend driver
+        Copyright (C) Manu Abraham <abraham.manu@gmail.com>
+
+        Copyright (C) ST Microelectronics
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/mutex.h>
+
+#include <linux/dvb/frontend.h>
+#include "dvb_frontend.h"
+
+#include "stv6110x.h" /* for demodulator internal modes */
+
+#include "stv090x_reg.h"
+#include "stv090x.h"
+#include "stv090x_priv.h"
+
+static unsigned int verbose;
+module_param(verbose, int, 0644);
+
+struct mutex demod_lock;
+
+/* DVBS1 and DSS C/N Lookup table */
+static const struct stv090x_tab stv090x_s1cn_tab[] = {
+        {   0, 8917 }, /*  0.0dB */
+        {   5, 8801 }, /*  0.5dB */
+        {  10, 8667 }, /*  1.0dB */
+        {  15, 8522 }, /*  1.5dB */
+        {  20, 8355 }, /*  2.0dB */
+        {  25, 8175 }, /*  2.5dB */
+        {  30, 7979 }, /*  3.0dB */
+        {  35, 7763 }, /*  3.5dB */
+        {  40, 7530 }, /*  4.0dB */
+        {  45, 7282 }, /*  4.5dB */
+        {  50, 7026 }, /*  5.0dB */
+        {  55, 6781 }, /*  5.5dB */
+        {  60, 6514 }, /*  6.0dB */
+        {  65, 6241 }, /*  6.5dB */
+        {  70, 5965 }, /*  7.0dB */
+        {  75, 5690 }, /*  7.5dB */
+        {  80, 5424 }, /*  8.0dB */
+        {  85, 5161 }, /*  8.5dB */
+        {  90, 4902 }, /*  9.0dB */
+        {  95, 4654 }, /*  9.5dB */
+        { 100, 4417 }, /* 10.0dB */
+        { 105, 4186 }, /* 10.5dB */
+        { 110, 3968 }, /* 11.0dB */
+        { 115, 3757 }, /* 11.5dB */
+        { 120, 3558 }, /* 12.0dB */
+        { 125, 3366 }, /* 12.5dB */
+        { 130, 3185 }, /* 13.0dB */
+        { 135, 3012 }, /* 13.5dB */
+        { 140, 2850 }, /* 14.0dB */
+        { 145, 2698 }, /* 14.5dB */
+        { 150, 2550 }, /* 15.0dB */
+        { 160, 2283 }, /* 16.0dB */
+        { 170, 2042 }, /* 17.0dB */
+        { 180, 1827 }, /* 18.0dB */
+        { 190, 1636 }, /* 19.0dB */
+        { 200, 1466 }, /* 20.0dB */
+        { 210, 1315 }, /* 21.0dB */
+        { 220, 1181 }, /* 22.0dB */
+        { 230, 1064 }, /* 23.0dB */
+        { 240,  960 }, /* 24.0dB */
+        { 250,  869 }, /* 25.0dB */
+        { 260,  792 }, /* 26.0dB */
+        { 270,  724 }, /* 27.0dB */
+        { 280,  665 }, /* 28.0dB */
+        { 290,  616 }, /* 29.0dB */
+        { 300,  573 }, /* 30.0dB */
+        { 310,  537 }, /* 31.0dB */
+        { 320,  507 }, /* 32.0dB */
+        { 330,  483 }, /* 33.0dB */
+        { 400,  398 }, /* 40.0dB */
+        { 450,  381 }, /* 45.0dB */
+        { 500,  377 }  /* 50.0dB */
+};
+
+/* DVBS2 C/N Lookup table */
+static const struct stv090x_tab stv090x_s2cn_tab[] = {
+        { -30, 13348 }, /* -3.0dB */
+        { -20, 12640 }, /* -2d.0B */
+        { -10, 11883 }, /* -1.0dB */
+        {   0, 11101 }, /* -0.0dB */
+        {   5, 10718 }, /*  0.5dB */
+        {  10, 10339 }, /*  1.0dB */
+        {  15,  9947 }, /*  1.5dB */
+        {  20,  9552 }, /*  2.0dB */
+        {  25,  9183 }, /*  2.5dB */
+        {  30,  8799 }, /*  3.0dB */
+        {  35,  8422 }, /*  3.5dB */
+        {  40,  8062 }, /*  4.0dB */
+        {  45,  7707 }, /*  4.5dB */
+        {  50,  7353 }, /*  5.0dB */
+        {  55,  7025 }, /*  5.5dB */
+        {  60,  6684 }, /*  6.0dB */
+        {  65,  6331 }, /*  6.5dB */
+        {  70,  6036 }, /*  7.0dB */
+        {  75,  5727 }, /*  7.5dB */
+        {  80,  5437 }, /*  8.0dB */
+        {  85,  5164 }, /*  8.5dB */
+        {  90,  4902 }, /*  9.0dB */
+        {  95,  4653 }, /*  9.5dB */
+        { 100,  4408 }, /* 10.0dB */
+        { 105,  4187 }, /* 10.5dB */
+        { 110,  3961 }, /* 11.0dB */
+        { 115,  3751 }, /* 11.5dB */
+        { 120,  3558 }, /* 12.0dB */
+        { 125,  3368 }, /* 12.5dB */
+        { 130,  3191 }, /* 13.0dB */
+        { 135,  3017 }, /* 13.5dB */
+        { 140,  2862 }, /* 14.0dB */
+        { 145,  2710 }, /* 14.5dB */
+        { 150,  2565 }, /* 15.0dB */
+        { 160,  2300 }, /* 16.0dB */
+        { 170,  2058 }, /* 17.0dB */
+        { 180,  1849 }, /* 18.0dB */
+        { 190,  1663 }, /* 19.0dB */
+        { 200,  1495 }, /* 20.0dB */
+        { 210,  1349 }, /* 21.0dB */
+        { 220,  1222 }, /* 22.0dB */
+        { 230,  1110 }, /* 23.0dB */
+        { 240,  1011 }, /* 24.0dB */
+        { 250,   925 }, /* 25.0dB */
+        { 260,   853 }, /* 26.0dB */
+        { 270,   789 }, /* 27.0dB */
+        { 280,   734 }, /* 28.0dB */
+        { 290,   690 }, /* 29.0dB */
+        { 300,   650 }, /* 30.0dB */
+        { 310,   619 }, /* 31.0dB */
+        { 320,   593 }, /* 32.0dB */
+        { 330,   571 }, /* 33.0dB */
+        { 400,   498 }, /* 40.0dB */
+        { 450,   484 }, /* 45.0dB */
+        { 500,   481 }  /* 50.0dB */
+};
+
+/* RF level C/N lookup table */
+static const struct stv090x_tab stv090x_rf_tab[] = {
+        {  -5, 0xcaa1 }, /*  -5dBm */
+        { -10, 0xc229 }, /* -10dBm */
+        { -15, 0xbb08 }, /* -15dBm */
+        { -20, 0xb4bc }, /* -20dBm */
+        { -25, 0xad5a }, /* -25dBm */
+        { -30, 0xa298 }, /* -30dBm */
+        { -35, 0x98a8 }, /* -35dBm */
+        { -40, 0x8389 }, /* -40dBm */
+        { -45, 0x59be }, /* -45dBm */
+        { -50, 0x3a14 }, /* -50dBm */
+        { -55, 0x2d11 }, /* -55dBm */
+        { -60, 0x210d }, /* -60dBm */
+        { -65, 0xa14f }, /* -65dBm */
+        { -70, 0x07aa }  /* -70dBm */
+};
+
+
+static struct stv090x_reg stv0900_initval[] = {
+
+        { STV090x_OUTCFG,               0x00 },
+        { STV090x_MODECFG,              0xff },
+        { STV090x_AGCRF1CFG,            0x11 },
+        { STV090x_AGCRF2CFG,            0x13 },
+        { STV090x_TSGENERAL1X,          0x14 },
+        { STV090x_TSTTNR2,              0x21 },
+        { STV090x_TSTTNR4,              0x21 },
+        { STV090x_P2_DISTXCTL,          0x22 },
+        { STV090x_P2_F22TX,             0xc0 },
+        { STV090x_P2_F22RX,             0xc0 },
+        { STV090x_P2_DISRXCTL,          0x00 },
+        { STV090x_P2_DMDCFGMD,          0xF9 },
+        { STV090x_P2_DEMOD,             0x08 },
+        { STV090x_P2_DMDCFG3,           0xc4 },
+        { STV090x_P2_CARFREQ,           0xed },
+        { STV090x_P2_LDT,               0xd0 },
+        { STV090x_P2_LDT2,              0xb8 },
+        { STV090x_P2_TMGCFG,            0xd2 },
+        { STV090x_P2_TMGTHRISE,         0x20 },
+        { STV090x_P1_TMGCFG,            0xd2 },
+
+        { STV090x_P2_TMGTHFALL,         0x00 },
+        { STV090x_P2_FECSPY,            0x88 },
+        { STV090x_P2_FSPYDATA,          0x3a },
+        { STV090x_P2_FBERCPT4,          0x00 },
+        { STV090x_P2_FSPYBER,           0x10 },
+        { STV090x_P2_ERRCTRL1,          0x35 },
+        { STV090x_P2_ERRCTRL2,          0xc1 },
+        { STV090x_P2_CFRICFG,           0xf8 },
+        { STV090x_P2_NOSCFG,            0x1c },
+        { STV090x_P2_DMDTOM,            0x20 },
+        { STV090x_P2_CORRELMANT,        0x70 },
+        { STV090x_P2_CORRELABS,         0x88 },
+        { STV090x_P2_AGC2O,             0x5b },
+        { STV090x_P2_AGC2REF,           0x38 },
+        { STV090x_P2_CARCFG,            0xe4 },
+        { STV090x_P2_ACLC,              0x1A },
+        { STV090x_P2_BCLC,              0x09 },
+        { STV090x_P2_CARHDR,            0x08 },
+        { STV090x_P2_KREFTMG,           0xc1 },
+        { STV090x_P2_SFRUPRATIO,        0xf0 },
+        { STV090x_P2_SFRLOWRATIO,       0x70 },
+        { STV090x_P2_SFRSTEP,           0x58 },
+        { STV090x_P2_TMGCFG2,           0x01 },
+        { STV090x_P2_CAR2CFG,           0x26 },
+        { STV090x_P2_BCLC2S2Q,          0x86 },
+        { STV090x_P2_BCLC2S28,          0x86 },
+        { STV090x_P2_SMAPCOEF7,         0x77 },
+        { STV090x_P2_SMAPCOEF6,         0x85 },
+        { STV090x_P2_SMAPCOEF5,         0x77 },
+        { STV090x_P2_TSCFGL,            0x20 },
+        { STV090x_P2_DMDCFG2,           0x3b },
+        { STV090x_P2_MODCODLST0,        0xff },
+        { STV090x_P2_MODCODLST1,        0xff },
+        { STV090x_P2_MODCODLST2,        0xff },
+        { STV090x_P2_MODCODLST3,        0xff },
+        { STV090x_P2_MODCODLST4,        0xff },
+        { STV090x_P2_MODCODLST5,        0xff },
+        { STV090x_P2_MODCODLST6,        0xff },
+        { STV090x_P2_MODCODLST7,        0xcc },
+        { STV090x_P2_MODCODLST8,        0xcc },
+        { STV090x_P2_MODCODLST9,        0xcc },
+        { STV090x_P2_MODCODLSTA,        0xcc },
+        { STV090x_P2_MODCODLSTB,        0xcc },
+        { STV090x_P2_MODCODLSTC,        0xcc },
+        { STV090x_P2_MODCODLSTD,        0xcc },
+        { STV090x_P2_MODCODLSTE,        0xcc },
+        { STV090x_P2_MODCODLSTF,        0xcf },
+        { STV090x_P1_DISTXCTL,          0x22 },
+        { STV090x_P1_F22TX,             0xc0 },
+        { STV090x_P1_F22RX,             0xc0 },
+        { STV090x_P1_DISRXCTL,          0x00 },
+        { STV090x_P1_DMDCFGMD,          0xf9 },
+        { STV090x_P1_DEMOD,             0x08 },
+        { STV090x_P1_DMDCFG3,           0xc4 },
+        { STV090x_P1_DMDTOM,            0x20 },
+        { STV090x_P1_CARFREQ,           0xed },
+        { STV090x_P1_LDT,               0xd0 },
+        { STV090x_P1_LDT2,              0xb8 },
+        { STV090x_P1_TMGCFG,            0xd2 },
+        { STV090x_P1_TMGTHRISE,         0x20 },
+        { STV090x_P1_TMGTHFALL,         0x00 },
+        { STV090x_P1_SFRUPRATIO,        0xf0 },
+        { STV090x_P1_SFRLOWRATIO,       0x70 },
+        { STV090x_P1_TSCFGL,            0x20 },
+        { STV090x_P1_FECSPY,            0x88 },
+        { STV090x_P1_FSPYDATA,          0x3a },
+        { STV090x_P1_FBERCPT4,          0x00 },
+        { STV090x_P1_FSPYBER,           0x10 },
+        { STV090x_P1_ERRCTRL1,          0x35 },
+        { STV090x_P1_ERRCTRL2,          0xc1 },
+        { STV090x_P1_CFRICFG,           0xf8 },
+        { STV090x_P1_NOSCFG,            0x1c },
+        { STV090x_P1_CORRELMANT,        0x70 },
+        { STV090x_P1_CORRELABS,         0x88 },
+        { STV090x_P1_AGC2O,             0x5b },
+        { STV090x_P1_AGC2REF,           0x38 },
+        { STV090x_P1_CARCFG,            0xe4 },
+        { STV090x_P1_ACLC,              0x1A },
+        { STV090x_P1_BCLC,              0x09 },
+        { STV090x_P1_CARHDR,            0x08 },
+        { STV090x_P1_KREFTMG,           0xc1 },
+        { STV090x_P1_SFRSTEP,           0x58 },
+        { STV090x_P1_TMGCFG2,           0x01 },
+        { STV090x_P1_CAR2CFG,           0x26 },
+        { STV090x_P1_BCLC2S2Q,          0x86 },
+        { STV090x_P1_BCLC2S28,          0x86 },
+        { STV090x_P1_SMAPCOEF7,         0x77 },
+        { STV090x_P1_SMAPCOEF6,         0x85 },
+        { STV090x_P1_SMAPCOEF5,         0x77 },
+        { STV090x_P1_DMDCFG2,           0x3b },
+        { STV090x_P1_MODCODLST0,        0xff },
+        { STV090x_P1_MODCODLST1,        0xff },
+        { STV090x_P1_MODCODLST2,        0xff },
+        { STV090x_P1_MODCODLST3,        0xff },
+        { STV090x_P1_MODCODLST4,        0xff },
+        { STV090x_P1_MODCODLST5,        0xff },
+        { STV090x_P1_MODCODLST6,        0xff },
+        { STV090x_P1_MODCODLST7,        0xcc },
+        { STV090x_P1_MODCODLST8,        0xcc },
+        { STV090x_P1_MODCODLST9,        0xcc },
+        { STV090x_P1_MODCODLSTA,        0xcc },
+        { STV090x_P1_MODCODLSTB,        0xcc },
+        { STV090x_P1_MODCODLSTC,        0xcc },
+        { STV090x_P1_MODCODLSTD,        0xcc },
+        { STV090x_P1_MODCODLSTE,        0xcc },
+        { STV090x_P1_MODCODLSTF,        0xcf },
+        { STV090x_GENCFG,               0x1d },
+        { STV090x_NBITER_NF4,           0x37 },
+        { STV090x_NBITER_NF5,           0x29 },
+        { STV090x_NBITER_NF6,           0x37 },
+        { STV090x_NBITER_NF7,           0x33 },
+        { STV090x_NBITER_NF8,           0x31 },
+        { STV090x_NBITER_NF9,           0x2f },
+        { STV090x_NBITER_NF10,          0x39 },
+        { STV090x_NBITER_NF11,          0x3a },
+        { STV090x_NBITER_NF12,          0x29 },
+        { STV090x_NBITER_NF13,          0x37 },
+        { STV090x_NBITER_NF14,          0x33 },
+        { STV090x_NBITER_NF15,          0x2f },
+        { STV090x_NBITER_NF16,          0x39 },
+        { STV090x_NBITER_NF17,          0x3a },
+        { STV090x_NBITERNOERR,          0x04 },
+        { STV090x_GAINLLR_NF4,          0x0C },
+        { STV090x_GAINLLR_NF5,          0x0F },
+        { STV090x_GAINLLR_NF6,          0x11 },
+        { STV090x_GAINLLR_NF7,          0x14 },
+        { STV090x_GAINLLR_NF8,          0x17 },
+        { STV090x_GAINLLR_NF9,          0x19 },
+        { STV090x_GAINLLR_NF10,         0x20 },
+        { STV090x_GAINLLR_NF11,         0x21 },
+        { STV090x_GAINLLR_NF12,         0x0D },
+        { STV090x_GAINLLR_NF13,         0x0F },
+        { STV090x_GAINLLR_NF14,         0x13 },
+        { STV090x_GAINLLR_NF15,         0x1A },
+        { STV090x_GAINLLR_NF16,         0x1F },
+        { STV090x_GAINLLR_NF17,         0x21 },
+        { STV090x_RCCFGH,               0x20 },
+        { STV090x_P1_FECM,              0x01 }, /* disable DSS modes */
+        { STV090x_P2_FECM,              0x01 }, /* disable DSS modes */
+        { STV090x_P1_PRVIT,             0x2F }, /* disable PR 6/7 */
+        { STV090x_P2_PRVIT,             0x2F }, /* disable PR 6/7 */
+};
+
+static struct stv090x_reg stv0903_initval[] = {
+        { STV090x_OUTCFG,               0x00 },
+        { STV090x_AGCRF1CFG,            0x11 },
+        { STV090x_STOPCLK1,             0x48 },
+        { STV090x_STOPCLK2,             0x14 },
+        { STV090x_TSTTNR1,              0x27 },
+        { STV090x_TSTTNR2,              0x21 },
+        { STV090x_P1_DISTXCTL,          0x22 },
+        { STV090x_P1_F22TX,             0xc0 },
+        { STV090x_P1_F22RX,             0xc0 },
+        { STV090x_P1_DISRXCTL,          0x00 },
+        { STV090x_P1_DMDCFGMD,          0xF9 },
+        { STV090x_P1_DEMOD,             0x08 },
+        { STV090x_P1_DMDCFG3,           0xc4 },
+        { STV090x_P1_CARFREQ,           0xed },
+        { STV090x_P1_TNRCFG2,           0x82 },
+        { STV090x_P1_LDT,               0xd0 },
+        { STV090x_P1_LDT2,              0xb8 },
+        { STV090x_P1_TMGCFG,            0xd2 },
+        { STV090x_P1_TMGTHRISE,         0x20 },
+        { STV090x_P1_TMGTHFALL,         0x00 },
+        { STV090x_P1_SFRUPRATIO,        0xf0 },
+        { STV090x_P1_SFRLOWRATIO,       0x70 },
+        { STV090x_P1_TSCFGL,            0x20 },
+        { STV090x_P1_FECSPY,            0x88 },
+        { STV090x_P1_FSPYDATA,          0x3a },
+        { STV090x_P1_FBERCPT4,          0x00 },
+        { STV090x_P1_FSPYBER,           0x10 },
+        { STV090x_P1_ERRCTRL1,          0x35 },
+        { STV090x_P1_ERRCTRL2,          0xc1 },
+        { STV090x_P1_CFRICFG,           0xf8 },
+        { STV090x_P1_NOSCFG,            0x1c },
+        { STV090x_P1_DMDTOM,            0x20 },
+        { STV090x_P1_CORRELMANT,        0x70 },
+        { STV090x_P1_CORRELABS,         0x88 },
+        { STV090x_P1_AGC2O,             0x5b },
+        { STV090x_P1_AGC2REF,           0x38 },
+        { STV090x_P1_CARCFG,            0xe4 },
+        { STV090x_P1_ACLC,              0x1A },
+        { STV090x_P1_BCLC,              0x09 },
+        { STV090x_P1_CARHDR,            0x08 },
+        { STV090x_P1_KREFTMG,           0xc1 },
+        { STV090x_P1_SFRSTEP,           0x58 },
+        { STV090x_P1_TMGCFG2,           0x01 },
+        { STV090x_P1_CAR2CFG,           0x26 },
+        { STV090x_P1_BCLC2S2Q,          0x86 },
+        { STV090x_P1_BCLC2S28,          0x86 },
+        { STV090x_P1_SMAPCOEF7,         0x77 },
+        { STV090x_P1_SMAPCOEF6,         0x85 },
+        { STV090x_P1_SMAPCOEF5,         0x77 },
+        { STV090x_P1_DMDCFG2,           0x3b },
+        { STV090x_P1_MODCODLST0,        0xff },
+        { STV090x_P1_MODCODLST1,        0xff },
+        { STV090x_P1_MODCODLST2,        0xff },
+        { STV090x_P1_MODCODLST3,        0xff },
+        { STV090x_P1_MODCODLST4,        0xff },
+        { STV090x_P1_MODCODLST5,        0xff },
+        { STV090x_P1_MODCODLST6,        0xff },
+        { STV090x_P1_MODCODLST7,        0xcc },
+        { STV090x_P1_MODCODLST8,        0xcc },
+        { STV090x_P1_MODCODLST9,        0xcc },
+        { STV090x_P1_MODCODLSTA,        0xcc },
+        { STV090x_P1_MODCODLSTB,        0xcc },
+        { STV090x_P1_MODCODLSTC,        0xcc },
+        { STV090x_P1_MODCODLSTD,        0xcc },
+        { STV090x_P1_MODCODLSTE,        0xcc },
+        { STV090x_P1_MODCODLSTF,        0xcf },
+        { STV090x_GENCFG,               0x1c },
+        { STV090x_NBITER_NF4,           0x37 },
+        { STV090x_NBITER_NF5,           0x29 },
+        { STV090x_NBITER_NF6,           0x37 },
+        { STV090x_NBITER_NF7,           0x33 },
+        { STV090x_NBITER_NF8,           0x31 },
+        { STV090x_NBITER_NF9,           0x2f },
+        { STV090x_NBITER_NF10,          0x39 },
+        { STV090x_NBITER_NF11,          0x3a },
+        { STV090x_NBITER_NF12,          0x29 },
+        { STV090x_NBITER_NF13,          0x37 },
+        { STV090x_NBITER_NF14,          0x33 },
+        { STV090x_NBITER_NF15,          0x2f },
+        { STV090x_NBITER_NF16,          0x39 },
+        { STV090x_NBITER_NF17,          0x3a },
+        { STV090x_NBITERNOERR,          0x04 },
+        { STV090x_GAINLLR_NF4,          0x0C },
+        { STV090x_GAINLLR_NF5,          0x0F },
+        { STV090x_GAINLLR_NF6,          0x11 },
+        { STV090x_GAINLLR_NF7,          0x14 },
+        { STV090x_GAINLLR_NF8,          0x17 },
+        { STV090x_GAINLLR_NF9,          0x19 },
+        { STV090x_GAINLLR_NF10,         0x20 },
+        { STV090x_GAINLLR_NF11,         0x21 },
+        { STV090x_GAINLLR_NF12,         0x0D },
+        { STV090x_GAINLLR_NF13,         0x0F },
+        { STV090x_GAINLLR_NF14,         0x13 },
+        { STV090x_GAINLLR_NF15,         0x1A },
+        { STV090x_GAINLLR_NF16,         0x1F },
+        { STV090x_GAINLLR_NF17,         0x21 },
+        { STV090x_RCCFGH,               0x20 },
+        { STV090x_P1_FECM,              0x01 }, /*disable the DSS mode */
+        { STV090x_P1_PRVIT,             0x2f }  /*disable puncture rate 6/7*/
+};
+
+static struct stv090x_reg stv0900_cut20_val[] = {
+
+        { STV090x_P2_DMDCFG3,           0xe8 },
+        { STV090x_P2_DMDCFG4,           0x10 },
+        { STV090x_P2_CARFREQ,           0x38 },
+        { STV090x_P2_CARHDR,            0x20 },
+        { STV090x_P2_KREFTMG,           0x5a },
+        { STV090x_P2_SMAPCOEF7,         0x06 },
+        { STV090x_P2_SMAPCOEF6,         0x00 },
+        { STV090x_P2_SMAPCOEF5,         0x04 },
+        { STV090x_P2_NOSCFG,            0x0c },
+        { STV090x_P1_DMDCFG3,           0xe8 },
+        { STV090x_P1_DMDCFG4,           0x10 },
+        { STV090x_P1_CARFREQ,           0x38 },
+        { STV090x_P1_CARHDR,            0x20 },
+        { STV090x_P1_KREFTMG,           0x5a },
+        { STV090x_P1_SMAPCOEF7,         0x06 },
+        { STV090x_P1_SMAPCOEF6,         0x00 },
+        { STV090x_P1_SMAPCOEF5,         0x04 },
+        { STV090x_P1_NOSCFG,            0x0c },
+        { STV090x_GAINLLR_NF4,          0x21 },
+        { STV090x_GAINLLR_NF5,          0x21 },
+        { STV090x_GAINLLR_NF6,          0x20 },
+        { STV090x_GAINLLR_NF7,          0x1F },
+        { STV090x_GAINLLR_NF8,          0x1E },
+        { STV090x_GAINLLR_NF9,          0x1E },
+        { STV090x_GAINLLR_NF10,         0x1D },
+        { STV090x_GAINLLR_NF11,         0x1B },
+        { STV090x_GAINLLR_NF12,         0x20 },
+        { STV090x_GAINLLR_NF13,         0x20 },
+        { STV090x_GAINLLR_NF14,         0x20 },
+        { STV090x_GAINLLR_NF15,         0x20 },
+        { STV090x_GAINLLR_NF16,         0x20 },
+        { STV090x_GAINLLR_NF17,         0x21 },
+};
+
+static struct stv090x_reg stv0903_cut20_val[] = {
+        { STV090x_P1_DMDCFG3,           0xe8 },
+        { STV090x_P1_DMDCFG4,           0x10 },
+        { STV090x_P1_CARFREQ,           0x38 },
+        { STV090x_P1_CARHDR,            0x20 },
+        { STV090x_P1_KREFTMG,           0x5a },
+        { STV090x_P1_SMAPCOEF7,         0x06 },
+        { STV090x_P1_SMAPCOEF6,         0x00 },
+        { STV090x_P1_SMAPCOEF5,         0x04 },
+        { STV090x_P1_NOSCFG,            0x0c },
+        { STV090x_GAINLLR_NF4,          0x21 },
+        { STV090x_GAINLLR_NF5,          0x21 },
+        { STV090x_GAINLLR_NF6,          0x20 },
+        { STV090x_GAINLLR_NF7,          0x1F },
+        { STV090x_GAINLLR_NF8,          0x1E },
+        { STV090x_GAINLLR_NF9,          0x1E },
+        { STV090x_GAINLLR_NF10,         0x1D },
+        { STV090x_GAINLLR_NF11,         0x1B },
+        { STV090x_GAINLLR_NF12,         0x20 },
+        { STV090x_GAINLLR_NF13,         0x20 },
+        { STV090x_GAINLLR_NF14,         0x20 },
+        { STV090x_GAINLLR_NF15,         0x20 },
+        { STV090x_GAINLLR_NF16,         0x20 },
+        { STV090x_GAINLLR_NF17,         0x21 }
+};
+
+/* Cut 2.0 Long Frame Tracking CR loop */
+static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
+        /* MODCOD  2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+        { STV090x_QPSK_12,  0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
+        { STV090x_QPSK_35,  0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
+        { STV090x_QPSK_23,  0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
+        { STV090x_QPSK_34,  0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
+        { STV090x_QPSK_45,  0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
+        { STV090x_QPSK_56,  0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
+        { STV090x_QPSK_89,  0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
+        { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
+        { STV090x_8PSK_35,  0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
+        { STV090x_8PSK_23,  0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
+        { STV090x_8PSK_34,  0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
+        { STV090x_8PSK_56,  0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
+        { STV090x_8PSK_89,  0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
+        { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
+};
+
+/* Cut 3.0 Long Frame Tracking CR loop */
+static  struct stv090x_long_frame_crloop stv090x_s2_crl_cut30[] = {
+        /* MODCOD  2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+        { STV090x_QPSK_12,  0x3c, 0x2c, 0x0c, 0x2c, 0x1b, 0x2c, 0x1b, 0x1c, 0x0b, 0x3b },
+        { STV090x_QPSK_35,  0x0d, 0x0d, 0x0c, 0x0d, 0x1b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
+        { STV090x_QPSK_23,  0x1d, 0x0d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
+        { STV090x_QPSK_34,  0x1d, 0x1d, 0x0c, 0x1d, 0x2b, 0x3c, 0x1b, 0x1c, 0x0b, 0x3b },
+        { STV090x_QPSK_45,  0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
+        { STV090x_QPSK_56,  0x2d, 0x1d, 0x1c, 0x1d, 0x2b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
+        { STV090x_QPSK_89,  0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
+        { STV090x_QPSK_910, 0x3d, 0x2d, 0x1c, 0x1d, 0x3b, 0x3c, 0x2b, 0x0c, 0x1b, 0x3b },
+        { STV090x_8PSK_35,  0x39, 0x29, 0x39, 0x19, 0x19, 0x19, 0x19, 0x19, 0x09, 0x19 },
+        { STV090x_8PSK_23,  0x2a, 0x39, 0x1a, 0x0a, 0x39, 0x0a, 0x29, 0x39, 0x29, 0x0a },
+        { STV090x_8PSK_34,  0x2b, 0x3a, 0x1b, 0x1b, 0x3a, 0x1b, 0x1a, 0x0b, 0x1a, 0x3a },
+        { STV090x_8PSK_56,  0x0c, 0x1b, 0x3b, 0x3b, 0x1b, 0x3b, 0x3a, 0x3b, 0x3a, 0x1b },
+        { STV090x_8PSK_89,  0x0d, 0x3c, 0x2c, 0x2c, 0x2b, 0x0c, 0x0b, 0x3b, 0x0b, 0x1b },
+        { STV090x_8PSK_910, 0x0d, 0x0d, 0x2c, 0x3c, 0x3b, 0x1c, 0x0b, 0x3b, 0x0b, 0x1b }
+};
+
+/* Cut 2.0 Long Frame Tracking CR Loop */
+static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
+        /* MODCOD  2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+        { STV090x_16APSK_23,  0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
+        { STV090x_16APSK_34,  0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
+        { STV090x_16APSK_45,  0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
+        { STV090x_16APSK_56,  0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
+        { STV090x_16APSK_89,  0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
+        { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
+        { STV090x_32APSK_34,  0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
+        { STV090x_32APSK_45,  0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
+        { STV090x_32APSK_56,  0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
+        { STV090x_32APSK_89,  0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
+        { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
+};
+
+/* Cut 3.0 Long Frame Tracking CR Loop */
+static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut30[] = {
+        /* MODCOD  2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+        { STV090x_16APSK_23,  0x0a, 0x0a, 0x0a, 0x0a, 0x1a, 0x0a, 0x3a, 0x0a, 0x2a, 0x0a },
+        { STV090x_16APSK_34,  0x0a, 0x0a, 0x0a, 0x0a, 0x0b, 0x0a, 0x3b, 0x0a, 0x1b, 0x0a },
+        { STV090x_16APSK_45,  0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
+        { STV090x_16APSK_56,  0x0a, 0x0a, 0x0a, 0x0a, 0x1b, 0x0a, 0x3b, 0x0a, 0x2b, 0x0a },
+        { STV090x_16APSK_89,  0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
+        { STV090x_16APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x2b, 0x0a, 0x0c, 0x0a, 0x3b, 0x0a },
+        { STV090x_32APSK_34,  0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
+        { STV090x_32APSK_45,  0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
+        { STV090x_32APSK_56,  0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
+        { STV090x_32APSK_89,  0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a },
+        { STV090x_32APSK_910, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a, 0x0a }
+};
+
+static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
+        /* MODCOD  2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+        { STV090x_QPSK_14,  0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
+        { STV090x_QPSK_13,  0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
+        { STV090x_QPSK_25,  0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
+};
+
+static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut30[] = {
+        /* MODCOD  2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
+        { STV090x_QPSK_14,  0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x2a, 0x1c, 0x3a, 0x3b },
+        { STV090x_QPSK_13,  0x0c, 0x3c, 0x0b, 0x3c, 0x2a, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b },
+        { STV090x_QPSK_25,  0x1c, 0x3c, 0x1b, 0x3c, 0x3a, 0x1c, 0x3a, 0x3b, 0x3a, 0x2b }
+};
+
+/* Cut 2.0 Short Frame Tracking CR Loop */
+static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut20[] = {
+        /* MODCOD         2M    5M    10M   20M   30M */
+        { STV090x_QPSK,   0x2f, 0x2e, 0x0e, 0x0e, 0x3d },
+        { STV090x_8PSK,   0x3e, 0x0e, 0x2d, 0x0d, 0x3c },
+        { STV090x_16APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d },
+        { STV090x_32APSK, 0x1e, 0x1e, 0x1e, 0x3d, 0x2d }
+};
+
+/* Cut 3.0 Short Frame Tracking CR Loop */
+static struct stv090x_short_frame_crloop stv090x_s2_short_crl_cut30[] = {
+        /* MODCOD         2M    5M    10M   20M   30M */
+        { STV090x_QPSK,   0x2C, 0x2B, 0x0B, 0x0B, 0x3A },
+        { STV090x_8PSK,   0x3B, 0x0B, 0x2A, 0x0A, 0x39 },
+        { STV090x_16APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A },
+        { STV090x_32APSK, 0x1B, 0x1B, 0x1B, 0x3A, 0x2A }
+};
+
+static inline s32 comp2(s32 __x, s32 __width)
+{
+        if (__width == 32)
+                return __x;
+        else
+                return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
+}
+
+static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
+{
+        const struct stv090x_config *config = state->config;
+        int ret;
+
+        u8 b0[] = { reg >> 8, reg & 0xff };
+        u8 buf;
+
+        struct i2c_msg msg[] = {
+                { .addr = config->address, .flags       = 0,            .buf = b0,   .len = 2 },
+                { .addr = config->address, .flags       = I2C_M_RD,     .buf = &buf, .len = 1 }
+        };
+
+        ret = i2c_transfer(state->i2c, msg, 2);
+        if (ret != 2) {
+                if (ret != -ERESTARTSYS)
+                        dprintk(FE_ERROR, 1,
+                                "Read error, Reg=[0x%02x], Status=%d",
+                                reg, ret);
+
+                return ret < 0 ? ret : -EREMOTEIO;
+        }
+        if (unlikely(*state->verbose >= FE_DEBUGREG))
+                dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
+                        reg, buf);
+
+        return (unsigned int) buf;
+}
+
+static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
+{
+        const struct stv090x_config *config = state->config;
+        int ret;
+        u8 buf[2 + count];
+        struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
+
+        buf[0] = reg >> 8;
+        buf[1] = reg & 0xff;
+        memcpy(&buf[2], data, count);
+
+        if (unlikely(*state->verbose >= FE_DEBUGREG)) {
+                int i;
+
+                printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
+                for (i = 0; i < count; i++)
+                        printk(" %02x", data[i]);
+                printk("\n");
+        }
+
+        ret = i2c_transfer(state->i2c, &i2c_msg, 1);
+        if (ret != 1) {
+                if (ret != -ERESTARTSYS)
+                        dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
+                                reg, data[0], count, ret);
+                return ret < 0 ? ret : -EREMOTEIO;
+        }
+
+        return 0;
+}
+
+static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
+{
+        return stv090x_write_regs(state, reg, &data, 1);
+}
+
+static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        u32 reg;
+
+        reg = STV090x_READ_DEMOD(state, I2CRPT);
+        if (enable) {
+                dprintk(FE_DEBUG, 1, "Enable Gate");
+                STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
+                if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
+                        goto err;
+
+        } else {
+                dprintk(FE_DEBUG, 1, "Disable Gate");
+                STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
+                if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
+                        goto err;
+        }
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static void stv090x_get_lock_tmg(struct stv090x_state *state)
+{
+        switch (state->algo) {
+        case STV090x_BLIND_SEARCH:
+                dprintk(FE_DEBUG, 1, "Blind Search");
+                if (state->srate <= 1500000) {  /*10Msps< SR <=15Msps*/
+                        state->DemodTimeout = 1500;
+                        state->FecTimeout = 400;
+                } else if (state->srate <= 5000000) {  /*10Msps< SR <=15Msps*/
+                        state->DemodTimeout = 1000;
+                        state->FecTimeout = 300;
+                } else {  /*SR >20Msps*/
+                        state->DemodTimeout = 700;
+                        state->FecTimeout = 100;
+                }
+                break;
+
+        case STV090x_COLD_SEARCH:
+        case STV090x_WARM_SEARCH:
+        default:
+                dprintk(FE_DEBUG, 1, "Normal Search");
+                if (state->srate <= 1000000) {  /*SR <=1Msps*/
+                        state->DemodTimeout = 4500;
+                        state->FecTimeout = 1700;
+                } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
+                        state->DemodTimeout = 2500;
+                        state->FecTimeout = 1100;
+                } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
+                        state->DemodTimeout = 1000;
+                        state->FecTimeout = 550;
+                } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
+                        state->DemodTimeout = 700;
+                        state->FecTimeout = 250;
+                } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
+                        state->DemodTimeout = 400;
+                        state->FecTimeout = 130;
+                } else {   /*SR >20Msps*/
+                        state->DemodTimeout = 300;
+                        state->FecTimeout = 100;
+                }
+                break;
+        }
+
+        if (state->algo == STV090x_WARM_SEARCH)
+                state->DemodTimeout /= 2;
+}
+
+static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
+{
+        u32 sym;
+
+        if (srate > 60000000) {
+                sym  = (srate << 4); /* SR * 2^16 / master_clk */
+                sym /= (state->mclk >> 12);
+        } else if (srate > 6000000) {
+                sym  = (srate << 6);
+                sym /= (state->mclk >> 10);
+        } else {
+                sym  = (srate << 9);
+                sym /= (state->mclk >> 7);
+        }
+
+        if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
+                goto err;
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
+{
+        u32 sym;
+
+        srate = 105 * (srate / 100);
+        if (srate > 60000000) {
+                sym  = (srate << 4); /* SR * 2^16 / master_clk */
+                sym /= (state->mclk >> 12);
+        } else if (srate > 6000000) {
+                sym  = (srate << 6);
+                sym /= (state->mclk >> 10);
+        } else {
+                sym  = (srate << 9);
+                sym /= (state->mclk >> 7);
+        }
+
+        if (sym < 0x7fff) {
+                if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
+                        goto err;
+        } else {
+                if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
+                        goto err;
+        }
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
+{
+        u32 sym;
+
+        srate = 95 * (srate / 100);
+        if (srate > 60000000) {
+                sym  = (srate << 4); /* SR * 2^16 / master_clk */
+                sym /= (state->mclk >> 12);
+        } else if (srate > 6000000) {
+                sym  = (srate << 6);
+                sym /= (state->mclk >> 10);
+        } else {
+                sym  = (srate << 9);
+                sym /= (state->mclk >> 7);
+        }
+
+        if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
+                goto err;
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static u32 stv090x_car_width(u32 srate, enum stv090x_rolloff rolloff)
+{
+        u32 ro;
+
+        switch (rolloff) {
+        case STV090x_RO_20:
+                ro = 20;
+                break;
+        case STV090x_RO_25:
+                ro = 25;
+                break;
+        case STV090x_RO_35:
+        default:
+                ro = 35;
+                break;
+        }
+
+        return srate + (srate * ro) / 100;
+}
+
+static int stv090x_set_vit_thacq(struct stv090x_state *state)
+{
+        if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
+                goto err;
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_set_vit_thtracq(struct stv090x_state *state)
+{
+        if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
+                goto err;
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_set_viterbi(struct stv090x_state *state)
+{
+        switch (state->search_mode) {
+        case STV090x_SEARCH_AUTO:
+                if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
+                        goto err;
+                break;
+        case STV090x_SEARCH_DVBS1:
+                if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
+                        goto err;
+                switch (state->fec) {
+                case STV090x_PR12:
+                        if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
+                                goto err;
+                        break;
+
+                case STV090x_PR23:
+                        if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
+                                goto err;
+                        break;
+
+                case STV090x_PR34:
+                        if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
+                                goto err;
+                        break;
+
+                case STV090x_PR56:
+                        if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
+                                goto err;
+                        break;
+
+                case STV090x_PR78:
+                        if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
+                                goto err;
+                        break;
+
+                default:
+                        if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
+                                goto err;
+                        break;
+                }
+                break;
+        case STV090x_SEARCH_DSS:
+                if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
+                        goto err;
+                switch (state->fec) {
+                case STV090x_PR12:
+                        if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
+                                goto err;
+                        break;
+
+                case STV090x_PR23:
+                        if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
+                                goto err;
+                        break;
+
+                case STV090x_PR67:
+                        if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
+                                goto err;
+                        break;
+
+                default:
+                        if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
+                                goto err;
+                        break;
+                }
+                break;
+        default:
+                break;
+        }
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_stop_modcod(struct stv090x_state *state)
+{
+        if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
+                goto err;
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_activate_modcod(struct stv090x_state *state)
+{
+        if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_activate_modcod_single(struct stv090x_state *state)
+{
+
+        if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
+                goto err;
+
+        return 0;
+
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
+{
+        u32 reg;
+
+        switch (state->demod) {
+        case STV090x_DEMODULATOR_0:
+                mutex_lock(&demod_lock);
+                reg = stv090x_read_reg(state, STV090x_STOPCLK2);
+                STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
+                if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
+                        goto err;
+                mutex_unlock(&demod_lock);
+                break;
+
+        case STV090x_DEMODULATOR_1:
+                mutex_lock(&demod_lock);
+                reg = stv090x_read_reg(state, STV090x_STOPCLK2);
+                STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
+                if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
+                        goto err;
+                mutex_unlock(&demod_lock);
+                break;
+
+        default:
+                dprintk(FE_ERROR, 1, "Wrong demodulator!");
+                break;
+        }
+        return 0;
+err:
+        mutex_unlock(&demod_lock);
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_dvbs_track_crl(struct stv090x_state *state)
+{
+        if (state->dev_ver >= 0x30) {
+                /* Set ACLC BCLC optimised value vs SR */
+                if (state->srate >= 15000000) {
+                        if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
+                                goto err;
+                } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
+                        if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
+                                goto err;
+                } else if (state->srate < 7000000) {
+                        if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
+                                goto err;
+                }
+
+        } else {
+                /* Cut 2.0 */
+                if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
+                        goto err;
+        }
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_delivery_search(struct stv090x_state *state)
+{
+        u32 reg;
+
+        switch (state->search_mode) {
+        case STV090x_SEARCH_DVBS1:
+        case STV090x_SEARCH_DSS:
+                reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+                STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
+                STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                        goto err;
+
+                /* Activate Viterbi decoder in legacy search,
+                 * do not use FRESVIT1, might impact VITERBI2
+                 */
+                if (stv090x_vitclk_ctl(state, 0) < 0)
+                        goto err;
+
+                if (stv090x_dvbs_track_crl(state) < 0)
+                        goto err;
+
+                if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
+                        goto err;
+
+                if (stv090x_set_vit_thacq(state) < 0)
+                        goto err;
+                if (stv090x_set_viterbi(state) < 0)
+                        goto err;
+                break;
+
+        case STV090x_SEARCH_DVBS2:
+                reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+                STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
+                STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                        goto err;
+                STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
+                STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                        goto err;
+
+                if (stv090x_vitclk_ctl(state, 1) < 0)
+                        goto err;
+
+                if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
+                        goto err;
+
+                if (state->dev_ver <= 0x20) {
+                        /* enable S2 carrier loop */
+                        if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
+                                goto err;
+                } else {
+                        /* > Cut 3: Stop carrier 3 */
+                        if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
+                                goto err;
+                }
+
+                if (state->demod_mode != STV090x_SINGLE) {
+                        /* Cut 2: enable link during search */
+                        if (stv090x_activate_modcod(state) < 0)
+                                goto err;
+                } else {
+                        /* Single demodulator
+                         * Authorize SHORT and LONG frames,
+                         * QPSK, 8PSK, 16APSK and 32APSK
+                         */
+                        if (stv090x_activate_modcod_single(state) < 0)
+                                goto err;
+                }
+
+                break;
+
+        case STV090x_SEARCH_AUTO:
+        default:
+                /* enable DVB-S2 and DVB-S2 in Auto MODE */
+                reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+                STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
+                STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                        goto err;
+
+                if (stv090x_vitclk_ctl(state, 0) < 0)
+                        goto err;
+
+                if (stv090x_dvbs_track_crl(state) < 0)
+                        goto err;
+
+                if (state->dev_ver <= 0x20) {
+                        /* enable S2 carrier loop */
+                        if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
+                                goto err;
+                } else {
+                        /* > Cut 3: Stop carrier 3 */
+                        if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
+                                goto err;
+                }
+
+                if (state->demod_mode != STV090x_SINGLE) {
+                        /* Cut 2: enable link during search */
+                        if (stv090x_activate_modcod(state) < 0)
+                                goto err;
+                } else {
+                        /* Single demodulator
+                         * Authorize SHORT and LONG frames,
+                         * QPSK, 8PSK, 16APSK and 32APSK
+                         */
+                        if (stv090x_activate_modcod_single(state) < 0)
+                                goto err;
+                }
+
+                if (state->srate >= 2000000) {
+                        /* Srate >= 2MSPS, Viterbi threshold to acquire */
+                        if (stv090x_set_vit_thacq(state) < 0)
+                                goto err;
+                } else {
+                        /* Srate < 2MSPS, Reset Viterbi thresholdto track
+                         * and then re-acquire
+                         */
+                        if (stv090x_set_vit_thtracq(state) < 0)
+                                goto err;
+                }
+
+                if (stv090x_set_viterbi(state) < 0)
+                        goto err;
+                break;
+        }
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_start_search(struct stv090x_state *state)
+{
+        u32 reg, freq_abs;
+        s16 freq;
+
+        /* Reset demodulator */
+        reg = STV090x_READ_DEMOD(state, DMDISTATE);
+        STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
+        if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
+                goto err;
+
+        if (state->dev_ver <= 0x20) {
+                if (state->srate <= 5000000) {
+                        if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
+                                goto err;
+
+                        /*enlarge the timing bandwith for Low SR*/
+                        if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
+                                goto err;
+                } else {
+                        /* If the symbol rate is >5 Msps
+                        Set The carrier search up and low to auto mode */
+                        if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
+                                goto err;
+                        /*reduce the timing bandwith for high SR*/
+                        if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
+                                goto err;
+                }
+        } else {
+                /* >= Cut 3 */
+                if (state->srate <= 5000000) {
+                        /* enlarge the timing bandwith for Low SR */
+                        STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
+                } else {
+                        /* reduce timing bandwith for high SR */
+                        STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
+                }
+
+                /* Set CFR min and max to manual mode */
+                STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
+
+                if (state->algo == STV090x_WARM_SEARCH) {
+                        /* WARM Start
+                         * CFR min = -1MHz,
+                         * CFR max = +1MHz
+                         */
+                        freq_abs  = 1000 << 16;
+                        freq_abs /= (state->mclk / 1000);
+                        freq      = (s16) freq_abs;
+                } else {
+                        /* COLD Start
+                         * CFR min =- (SearchRange / 2 + 600KHz)
+                         * CFR max = +(SearchRange / 2 + 600KHz)
+                         * (600KHz for the tuner step size)
+                         */
+                        freq_abs  = (state->search_range / 2000) + 600;
+                        freq_abs  = freq_abs << 16;
+                        freq_abs /= (state->mclk / 1000);
+                        freq      = (s16) freq_abs;
+                }
+
+                if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, CFRUP1, LSB(freq)) < 0)
+                        goto err;
+
+                freq *= -1;
+
+                if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
+                        goto err;
+
+        }
+
+        if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
+                goto err;
+
+        if (state->dev_ver >= 0x20) {
+                if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
+                        goto err;
+
+                if ((state->search_mode == STV090x_DVBS1)       ||
+                        (state->search_mode == STV090x_DSS)     ||
+                        (state->search_mode == STV090x_SEARCH_AUTO)) {
+
+                        if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
+                                goto err;
+                }
+        }
+
+        if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
+                goto err;
+
+        reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+        STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
+        STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
+        if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                goto err;
+        reg = STV090x_READ_DEMOD(state, DMDCFG2);
+        STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
+        if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
+                goto err;
+
+        if (state->dev_ver >= 0x20) {
+                /*Frequency offset detector setting*/
+                if (state->srate < 2000000) {
+                        if (state->dev_ver <= 0x20) {
+                                /* Cut 2 */
+                                if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
+                                        goto err;
+                        } else {
+                                /* Cut 2 */
+                                if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
+                                        goto err;
+                        }
+                        if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
+                                goto err;
+                }
+
+                if (state->srate < 10000000) {
+                        if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
+                                goto err;
+                } else {
+                        if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
+                                goto err;
+                }
+        } else {
+                if (state->srate < 10000000) {
+                        if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
+                                goto err;
+                } else {
+                        if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
+                                goto err;
+                }
+        }
+
+        switch (state->algo) {
+        case STV090x_WARM_SEARCH:
+                /* The symbol rate and the exact
+                 * carrier Frequency are known
+                 */
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
+                        goto err;
+                break;
+
+        case STV090x_COLD_SEARCH:
+                /* The symbol rate is known */
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
+                        goto err;
+                break;
+
+        default:
+                break;
+        }
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_get_agc2_min_level(struct stv090x_state *state)
+{
+        u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg;
+        s32 i, j, steps, dir;
+
+        if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
+                goto err;
+        reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+        STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
+        STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
+        if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                goto err;
+
+        if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
+                goto err;
+        if (stv090x_set_srate(state, 1000000) < 0)
+                goto err;
+
+        steps  = -1 + state->search_range / 1000000;
+        steps /= 2;
+        steps  = (2 * steps) + 1;
+        if (steps < 0)
+                steps = 1;
+
+        dir = 1;
+        freq_step = (1000000 * 256) / (state->mclk / 256);
+        freq_init = 0;
+
+        for (i = 0; i < steps; i++) {
+                if (dir > 0)
+                        freq_init = freq_init + (freq_step * i);
+                else
+                        freq_init = freq_init - (freq_step * i);
+
+                dir = -1;
+
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
+                        goto err;
+                msleep(10);
+                for (j = 0; j < 10; j++) {
+                        agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
+                        agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
+                }
+                agc2 /= 10;
+                agc2_min = 0xffff;
+                if (agc2 < 0xffff)
+                        agc2_min = agc2;
+        }
+
+        return agc2_min;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
+{
+        u8 r3, r2, r1, r0;
+        s32 srate, int_1, int_2, tmp_1, tmp_2;
+
+        r3 = STV090x_READ_DEMOD(state, SFR3);
+        r2 = STV090x_READ_DEMOD(state, SFR2);
+        r1 = STV090x_READ_DEMOD(state, SFR1);
+        r0 = STV090x_READ_DEMOD(state, SFR0);
+
+        srate = ((r3 << 24) | (r2 << 16) | (r1 <<  8) | r0);
+
+        int_1 = clk >> 16;
+        int_2 = srate >> 16;
+
+        tmp_1 = clk % 0x10000;
+        tmp_2 = srate % 0x10000;
+
+        srate = (int_1 * int_2) +
+                ((int_1 * tmp_2) >> 16) +
+                ((int_2 * tmp_1) >> 16);
+
+        return srate;
+}
+
+static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
+{
+        struct dvb_frontend *fe = &state->frontend;
+
+        int tmg_lock = 0, i;
+        s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
+        u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
+
+        reg = STV090x_READ_DEMOD(state, DMDISTATE);
+        STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
+        if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
+                goto err;
+        reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+        STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
+        STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
+        if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                goto err;
+
+        if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0)
+                goto err;
+
+        if (state->dev_ver >= 0x30) {
+                if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
+                        goto err;
+
+        } else if (state->dev_ver >= 0x20) {
+                if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
+                        goto err;
+        }
+
+        if (state->srate <= 2000000)
+                car_step = 1000;
+        else if (state->srate <= 5000000)
+                car_step = 2000;
+        else if (state->srate <= 12000000)
+                car_step = 3000;
+        else
+                car_step = 5000;
+
+        steps  = -1 + ((state->search_range / 1000) / car_step);
+        steps /= 2;
+        steps  = (2 * steps) + 1;
+        if (steps < 0)
+                steps = 1;
+        else if (steps > 10) {
+                steps = 11;
+                car_step = (state->search_range / 1000) / 10;
+        }
+        cur_step = 0;
+        dir = 1;
+        freq = state->frequency;
+
+        while ((!tmg_lock) && (cur_step < steps)) {
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
+                        goto err;
+                reg = STV090x_READ_DEMOD(state, DMDISTATE);
+                STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
+                        goto err;
+                msleep(50);
+                for (i = 0; i < 10; i++) {
+                        reg = STV090x_READ_DEMOD(state, DSTATUS);
+                        if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
+                                tmg_cpt++;
+                        agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
+                        agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
+                }
+                agc2 /= 10;
+                srate_coarse = stv090x_get_srate(state, state->mclk);
+                cur_step++;
+                dir *= -1;
+                if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000))
+                        tmg_lock = 1;
+                else if (cur_step < steps) {
+                        if (dir > 0)
+                                freq += cur_step * car_step;
+                        else
+                                freq -= cur_step * car_step;
+
+                        /* Setup tuner */
+                        if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
+                                goto err;
+
+                        if (state->config->tuner_set_frequency) {
+                                if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
+                                        goto err;
+                        }
+
+                        if (state->config->tuner_set_bandwidth) {
+                                if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
+                                        goto err;
+                        }
+
+                        if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
+                                goto err;
+
+                        msleep(50);
+
+                        if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
+                                goto err;
+
+                        if (state->config->tuner_get_status) {
+                                if (state->config->tuner_get_status(fe, &reg) < 0)
+                                        goto err;
+                        }
+
+                        if (reg)
+                                dprintk(FE_DEBUG, 1, "Tuner phase locked");
+                        else
+                                dprintk(FE_DEBUG, 1, "Tuner unlocked");
+
+                        if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
+                                goto err;
+
+                }
+        }
+        if (!tmg_lock)
+                srate_coarse = 0;
+        else
+                srate_coarse = stv090x_get_srate(state, state->mclk);
+
+        return srate_coarse;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
+{
+        u32 srate_coarse, freq_coarse, sym, reg;
+
+        srate_coarse = stv090x_get_srate(state, state->mclk);
+        freq_coarse  = STV090x_READ_DEMOD(state, CFR2) << 8;
+        freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
+        sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
+
+        if (sym < state->srate)
+                srate_coarse = 0;
+        else {
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
+                        goto err;
+                reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+                STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                        goto err;
+
+                if (state->dev_ver >= 0x30) {
+                        if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
+                                goto err;
+                } else if (state->dev_ver >= 0x20) {
+                        if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
+                                goto err;
+                }
+
+                if (srate_coarse > 3000000) {
+                        sym  = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
+                        sym  = (sym / 1000) * 65536;
+                        sym /= (state->mclk / 1000);
+                        if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
+                                goto err;
+                        sym  = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
+                        sym  = (sym / 1000) * 65536;
+                        sym /= (state->mclk / 1000);
+                        if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
+                                goto err;
+                        sym  = (srate_coarse / 1000) * 65536;
+                        sym /= (state->mclk / 1000);
+                        if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
+                                goto err;
+                } else {
+                        sym  = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
+                        sym  = (sym / 100) * 65536;
+                        sym /= (state->mclk / 100);
+                        if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
+                                goto err;
+                        sym  = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
+                        sym  = (sym / 100) * 65536;
+                        sym /= (state->mclk / 100);
+                        if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
+                                goto err;
+                        sym  = (srate_coarse / 100) * 65536;
+                        sym /= (state->mclk / 100);
+                        if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
+                                goto err;
+                }
+                if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
+                        goto err;
+        }
+
+        return srate_coarse;
+
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
+{
+        s32 timer = 0, lock = 0;
+        u32 reg;
+        u8 stat;
+
+        while ((timer < timeout) && (!lock)) {
+                reg = STV090x_READ_DEMOD(state, DMDSTATE);
+                stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
+
+                switch (stat) {
+                case 0: /* searching */
+                case 1: /* first PLH detected */
+                default:
+                        dprintk(FE_DEBUG, 1, "Demodulator searching ..");
+                        lock = 0;
+                        break;
+                case 2: /* DVB-S2 mode */
+                case 3: /* DVB-S1/legacy mode */
+                        reg = STV090x_READ_DEMOD(state, DSTATUS);
+                        lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
+                        break;
+                }
+
+                if (!lock)
+                        msleep(10);
+                else
+                        dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
+
+                timer += 10;
+        }
+        return lock;
+}
+
+static int stv090x_blind_search(struct stv090x_state *state)
+{
+        u32 agc2, reg, srate_coarse;
+        s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
+        u8 k_ref, k_max, k_min;
+        int coarse_fail, lock;
+
+        k_max = 120;
+        k_min = 30;
+
+        agc2 = stv090x_get_agc2_min_level(state);
+
+        if (agc2 > STV090x_SEARCH_AGC2_TH(state->dev_ver)) {
+                lock = 0;
+        } else {
+
+                if (state->dev_ver <= 0x20) {
+                        if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
+                                goto err;
+                } else {
+                        /* > Cut 3 */
+                        if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
+                                goto err;
+                }
+
+                if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
+                        goto err;
+
+                if (state->dev_ver >= 0x20) {
+                        if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
+                                goto err;
+                }
+
+                k_ref = k_max;
+                do {
+                        if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
+                                goto err;
+                        if (stv090x_srate_srch_coarse(state) != 0) {
+                                srate_coarse = stv090x_srate_srch_fine(state);
+                                if (srate_coarse != 0) {
+                                        stv090x_get_lock_tmg(state);
+                                        lock = stv090x_get_dmdlock(state, timeout_dmd);
+                                } else {
+                                        lock = 0;
+                                }
+                        } else {
+                                cpt_fail = 0;
+                                agc2_ovflw = 0;
+                                for (i = 0; i < 10; i++) {
+                                        agc2  = STV090x_READ_DEMOD(state, AGC2I1) << 8;
+                                        agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
+                                        if (agc2 >= 0xff00)
+                                                agc2_ovflw++;
+                                        reg = STV090x_READ_DEMOD(state, DSTATUS2);
+                                        if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
+                                            (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
+
+                                                cpt_fail++;
+                                }
+                                if ((cpt_fail > 7) || (agc2_ovflw > 7))
+                                        coarse_fail = 1;
+
+                                lock = 0;
+                        }
+                        k_ref -= 30;
+                } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
+        }
+
+        return lock;
+
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_chk_tmg(struct stv090x_state *state)
+{
+        u32 reg;
+        s32 tmg_cpt = 0, i;
+        u8 freq, tmg_thh, tmg_thl;
+        int tmg_lock;
+
+        freq = STV090x_READ_DEMOD(state, CARFREQ);
+        tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
+        tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
+        if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
+                goto err;
+
+        reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+        STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
+        if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
+                goto err;
+
+        if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
+                goto err;
+
+        if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
+                goto err;
+
+        if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
+                goto err;
+        msleep(10);
+
+        for (i = 0; i < 10; i++) {
+                reg = STV090x_READ_DEMOD(state, DSTATUS);
+                if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
+                        tmg_cpt++;
+                msleep(1);
+        }
+        if (tmg_cpt >= 3)
+                tmg_lock = 1;
+
+        if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
+                goto err;
+
+        if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
+                goto err;
+
+        return  tmg_lock;
+
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
+{
+        struct dvb_frontend *fe = &state->frontend;
+
+        u32 reg;
+        s32 car_step, steps, cur_step, dir, freq, timeout_lock;
+        int lock = 0;
+
+        if (state->srate >= 10000000)
+                timeout_lock = timeout_dmd / 3;
+        else
+                timeout_lock = timeout_dmd / 2;
+
+        lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
+        if (!lock) {
+                if (state->srate >= 10000000) {
+                        if (stv090x_chk_tmg(state)) {
+                                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
+                                        goto err;
+                                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
+                                        goto err;
+                                lock = stv090x_get_dmdlock(state, timeout_dmd);
+                        } else {
+                                lock = 0;
+                        }
+                } else {
+                        if (state->srate <= 4000000)
+                                car_step = 1000;
+                        else if (state->srate <= 7000000)
+                                car_step = 2000;
+                        else if (state->srate <= 10000000)
+                                car_step = 3000;
+                        else
+                                car_step = 5000;
+
+                        steps  = (state->search_range / 1000) / car_step;
+                        steps /= 2;
+                        steps  = 2 * (steps + 1);
+                        if (steps < 0)
+                                steps = 2;
+                        else if (steps > 12)
+                                steps = 12;
+
+                        cur_step = 1;
+                        dir = 1;
+
+                        if (!lock) {
+                                freq = state->frequency;
+                                state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
+                                while ((cur_step <= steps) && (!lock)) {
+                                        if (dir > 0)
+                                                freq += cur_step * car_step;
+                                        else
+                                                freq -= cur_step * car_step;
+
+                                        /* Setup tuner */
+                                        if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
+                                                goto err;
+
+                                        if (state->config->tuner_set_frequency) {
+                                                if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
+                                                        goto err;
+                                        }
+
+                                        if (state->config->tuner_set_bandwidth) {
+                                                if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
+                                                        goto err;
+                                        }
+
+                                        if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
+                                                goto err;
+
+                                        msleep(50);
+
+                                        if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
+                                                goto err;
+
+                                        if (state->config->tuner_get_status) {
+                                                if (state->config->tuner_get_status(fe, &reg) < 0)
+                                                        goto err;
+                                        }
+
+                                        if (reg)
+                                                dprintk(FE_DEBUG, 1, "Tuner phase locked");
+                                        else
+                                                dprintk(FE_DEBUG, 1, "Tuner unlocked");
+
+                                        if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
+                                                goto err;
+
+                                        STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
+                                        if (state->delsys == STV090x_DVBS2) {
+                                                reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+                                                STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
+                                                STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
+                                                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                                                        goto err;
+                                                STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
+                                                STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
+                                                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                                                        goto err;
+                                        }
+                                        if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
+                                                goto err;
+                                        if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
+                                                goto err;
+                                        if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
+                                                goto err;
+                                        if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
+                                                goto err;
+                                        lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
+
+                                        dir *= -1;
+                                        cur_step++;
+                                }
+                        }
+                }
+        }
+
+        return lock;
+
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
+{
+        s32 timeout, inc, steps_max, srate, car_max;
+
+        srate = state->srate;
+        car_max = state->search_range / 1000;
+        car_max += car_max / 10;
+        car_max  = 65536 * (car_max / 2);
+        car_max /= (state->mclk / 1000);
+
+        if (car_max > 0x4000)
+                car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
+
+        inc  = srate;
+        inc /= state->mclk / 1000;
+        inc *= 256;
+        inc *= 256;
+        inc /= 1000;
+
+        switch (state->search_mode) {
+        case STV090x_SEARCH_DVBS1:
+        case STV090x_SEARCH_DSS:
+                inc *= 3; /* freq step = 3% of srate */
+                timeout = 20;
+                break;
+
+        case STV090x_SEARCH_DVBS2:
+                inc *= 4;
+                timeout = 25;
+                break;
+
+        case STV090x_SEARCH_AUTO:
+        default:
+                inc *= 3;
+                timeout = 25;
+                break;
+        }
+        inc /= 100;
+        if ((inc > car_max) || (inc < 0))
+                inc = car_max / 2; /* increment <= 1/8 Mclk */
+
+        timeout *= 27500; /* 27.5 Msps reference */
+        if (srate > 0)
+                timeout /= (srate / 1000);
+
+        if ((timeout > 100) || (timeout < 0))
+                timeout = 100;
+
+        steps_max = (car_max / inc) + 1; /* min steps = 3 */
+        if ((steps_max > 100) || (steps_max < 0)) {
+                steps_max = 100; /* max steps <= 100 */
+                inc = car_max / steps_max;
+        }
+        *freq_inc = inc;
+        *timeout_sw = timeout;
+        *steps = steps_max;
+
+        return 0;
+}
+
+static int stv090x_chk_signal(struct stv090x_state *state)
+{
+        s32 offst_car, agc2, car_max;
+        int no_signal;
+
+        offst_car  = STV090x_READ_DEMOD(state, CFR2) << 8;
+        offst_car |= STV090x_READ_DEMOD(state, CFR1);
+        offst_car = comp2(offst_car, 16);
+
+        agc2  = STV090x_READ_DEMOD(state, AGC2I1) << 8;
+        agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
+        car_max = state->search_range / 1000;
+
+        car_max += (car_max / 10); /* 10% margin */
+        car_max  = (65536 * car_max / 2);
+        car_max /= state->mclk / 1000;
+
+        if (car_max > 0x4000)
+                car_max = 0x4000;
+
+        if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
+                no_signal = 1;
+                dprintk(FE_DEBUG, 1, "No Signal");
+        } else {
+                no_signal = 0;
+                dprintk(FE_DEBUG, 1, "Found Signal");
+        }
+
+        return no_signal;
+}
+
+static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
+{
+        int no_signal, lock = 0;
+        s32 cpt_step = 0, offst_freq, car_max;
+        u32 reg;
+
+        car_max  = state->search_range / 1000;
+        car_max += (car_max / 10);
+        car_max  = (65536 * car_max / 2);
+        car_max /= (state->mclk / 1000);
+        if (car_max > 0x4000)
+                car_max = 0x4000;
+
+        if (zigzag)
+                offst_freq = 0;
+        else
+                offst_freq = -car_max + inc;
+
+        do {
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
+                        goto err;
+
+                reg = STV090x_READ_DEMOD(state, PDELCTRL1);
+                STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
+                if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
+                        goto err;
+
+                if (zigzag) {
+                        if (offst_freq >= 0)
+                                offst_freq = -offst_freq - 2 * inc;
+                        else
+                                offst_freq = -offst_freq;
+                } else {
+                        offst_freq += 2 * inc;
+                }
+
+                cpt_step++;
+
+                lock = stv090x_get_dmdlock(state, timeout);
+                no_signal = stv090x_chk_signal(state);
+
+        } while ((!lock) &&
+                 (!no_signal) &&
+                  ((offst_freq - inc) < car_max) &&
+                  ((offst_freq + inc) > -car_max) &&
+                  (cpt_step < steps_max));
+
+        reg = STV090x_READ_DEMOD(state, PDELCTRL1);
+        STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
+        if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
+                        goto err;
+
+        return lock;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_sw_algo(struct stv090x_state *state)
+{
+        int no_signal, zigzag, lock = 0;
+        u32 reg;
+
+        s32 dvbs2_fly_wheel;
+        s32 inc, timeout_step, trials, steps_max;
+
+        /* get params */
+        stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
+
+        switch (state->search_mode) {
+        case STV090x_SEARCH_DVBS1:
+        case STV090x_SEARCH_DSS:
+                /* accelerate the frequency detector */
+                if (state->dev_ver >= 0x20) {
+                        if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
+                                goto err;
+                }
+
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
+                        goto err;
+                zigzag = 0;
+                break;
+
+        case STV090x_SEARCH_DVBS2:
+                if (state->dev_ver >= 0x20) {
+                        if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
+                                goto err;
+                }
+
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
+                        goto err;
+                zigzag = 1;
+                break;
+
+        case STV090x_SEARCH_AUTO:
+        default:
+                /* accelerate the frequency detector */
+                if (state->dev_ver >= 0x20) {
+                        if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
+                                goto err;
+                }
+
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
+                        goto err;
+                zigzag = 0;
+                break;
+        }
+
+        trials = 0;
+        do {
+                lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
+                no_signal = stv090x_chk_signal(state);
+                trials++;
+
+                /*run the SW search 2 times maximum*/
+                if (lock || no_signal || (trials == 2)) {
+                        /*Check if the demod is not losing lock in DVBS2*/
+                        if (state->dev_ver >= 0x20) {
+                                if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
+                                        goto err;
+                                if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
+                                        goto err;
+                        }
+
+                        reg = STV090x_READ_DEMOD(state, DMDSTATE);
+                        if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
+                                /*Check if the demod is not losing lock in DVBS2*/
+                                msleep(timeout_step);
+                                reg = STV090x_READ_DEMOD(state, DMDFLYW);
+                                dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
+                                if (dvbs2_fly_wheel < 0xd) {     /*if correct frames is decrementing */
+                                        msleep(timeout_step);
+                                        reg = STV090x_READ_DEMOD(state, DMDFLYW);
+                                        dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
+                                }
+                                if (dvbs2_fly_wheel < 0xd) {
+                                        /*FALSE lock, The demod is loosing lock */
+                                        lock = 0;
+                                        if (trials < 2) {
+                                                if (state->dev_ver >= 0x20) {
+                                                        if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
+                                                                goto err;
+                                                }
+
+                                                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
+                                                        goto err;
+                                        }
+                                }
+                        }
+                }
+        } while ((!lock) && (trials < 2) && (!no_signal));
+
+        return lock;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
+{
+        u32 reg;
+        enum stv090x_delsys delsys;
+
+        reg = STV090x_READ_DEMOD(state, DMDSTATE);
+        if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
+                delsys = STV090x_DVBS2;
+        else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
+                reg = STV090x_READ_DEMOD(state, FECM);
+                if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
+                        delsys = STV090x_DSS;
+                else
+                        delsys = STV090x_DVBS1;
+        } else {
+                delsys = STV090x_ERROR;
+        }
+
+        return delsys;
+}
+
+/* in Hz */
+static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
+{
+        s32 derot, int_1, int_2, tmp_1, tmp_2;
+
+        derot  = STV090x_READ_DEMOD(state, CFR2) << 16;
+        derot |= STV090x_READ_DEMOD(state, CFR1) <<  8;
+        derot |= STV090x_READ_DEMOD(state, CFR0);
+
+        derot = comp2(derot, 24);
+        int_1 = state->mclk >> 12;
+        int_2 = derot >> 12;
+
+        /* carrier_frequency = MasterClock * Reg / 2^24 */
+        tmp_1 = state->mclk % 0x1000;
+        tmp_2 = derot % 0x1000;
+
+        derot = (int_1 * int_2) +
+                ((int_1 * tmp_2) >> 12) +
+                ((int_1 * tmp_1) >> 12);
+
+        return derot;
+}
+
+static int stv090x_get_viterbi(struct stv090x_state *state)
+{
+        u32 reg, rate;
+
+        reg = STV090x_READ_DEMOD(state, VITCURPUN);
+        rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
+
+        switch (rate) {
+        case 13:
+                state->fec = STV090x_PR12;
+                break;
+
+        case 18:
+                state->fec = STV090x_PR23;
+                break;
+
+        case 21:
+                state->fec = STV090x_PR34;
+                break;
+
+        case 24:
+                state->fec = STV090x_PR56;
+                break;
+
+        case 25:
+                state->fec = STV090x_PR67;
+                break;
+
+        case 26:
+                state->fec = STV090x_PR78;
+                break;
+
+        default:
+                state->fec = STV090x_PRERR;
+                break;
+        }
+
+        return 0;
+}
+
+static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
+{
+        struct dvb_frontend *fe = &state->frontend;
+
+        u8 tmg;
+        u32 reg;
+        s32 i = 0, offst_freq;
+
+        msleep(5);
+
+        if (state->algo == STV090x_BLIND_SEARCH) {
+                tmg = STV090x_READ_DEMOD(state, TMGREG2);
+                STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
+                while ((i <= 50) && (tmg != 0) && (tmg != 0xff)) {
+                        tmg = STV090x_READ_DEMOD(state, TMGREG2);
+                        msleep(5);
+                        i += 5;
+                }
+        }
+        state->delsys = stv090x_get_std(state);
+
+        if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
+                goto err;
+
+        if (state->config->tuner_get_frequency) {
+                if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
+                        goto err;
+        }
+
+        if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
+                goto err;
+
+        offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
+        state->frequency += offst_freq;
+
+        if (stv090x_get_viterbi(state) < 0)
+                goto err;
+
+        reg = STV090x_READ_DEMOD(state, DMDMODCOD);
+        state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
+        state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
+        state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
+        reg = STV090x_READ_DEMOD(state, TMGOBS);
+        state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
+        reg = STV090x_READ_DEMOD(state, FECM);
+        state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
+
+        if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
+
+                if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
+                        goto err;
+
+                if (state->config->tuner_get_frequency) {
+                        if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
+                                goto err;
+                }
+
+                if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
+                        goto err;
+
+                if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
+                        return STV090x_RANGEOK;
+                else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
+                        return STV090x_RANGEOK;
+                else
+                        return STV090x_OUTOFRANGE; /* Out of Range */
+        } else {
+                if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
+                        return STV090x_RANGEOK;
+                else
+                        return STV090x_OUTOFRANGE;
+        }
+
+        return STV090x_OUTOFRANGE;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
+{
+        s32 offst_tmg;
+
+        offst_tmg  = STV090x_READ_DEMOD(state, TMGREG2) << 16;
+        offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) <<  8;
+        offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
+
+        offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
+        if (!offst_tmg)
+                offst_tmg = 1;
+
+        offst_tmg  = ((s32) srate * 10) / ((s32) 0x1000000 / offst_tmg);
+        offst_tmg /= 320;
+
+        return offst_tmg;
+}
+
+static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
+{
+        u8 aclc = 0x29;
+        s32 i;
+        struct stv090x_long_frame_crloop *car_loop, *car_loop_qpsk_low, *car_loop_apsk_low;
+
+        if (state->dev_ver == 0x20) {
+                car_loop                = stv090x_s2_crl_cut20;
+                car_loop_qpsk_low       = stv090x_s2_lowqpsk_crl_cut20;
+                car_loop_apsk_low       = stv090x_s2_apsk_crl_cut20;
+        } else {
+                /* >= Cut 3 */
+                car_loop                = stv090x_s2_crl_cut30;
+                car_loop_qpsk_low       = stv090x_s2_lowqpsk_crl_cut30;
+                car_loop_apsk_low       = stv090x_s2_apsk_crl_cut30;
+        }
+
+        if (modcod < STV090x_QPSK_12) {
+                i = 0;
+                while ((i < 3) && (modcod != car_loop_qpsk_low[i].modcod))
+                        i++;
+
+                if (i >= 3)
+                        i = 2;
+
+        } else {
+                i = 0;
+                while ((i < 14) && (modcod != car_loop[i].modcod))
+                        i++;
+
+                if (i >= 14) {
+                        i = 0;
+                        while ((i < 11) && (modcod != car_loop_apsk_low[i].modcod))
+                                i++;
+
+                        if (i >= 11)
+                                i = 10;
+                }
+        }
+
+        if (modcod <= STV090x_QPSK_25) {
+                if (pilots) {
+                        if (state->srate <= 3000000)
+                                aclc = car_loop_qpsk_low[i].crl_pilots_on_2;
+                        else if (state->srate <= 7000000)
+                                aclc = car_loop_qpsk_low[i].crl_pilots_on_5;
+                        else if (state->srate <= 15000000)
+                                aclc = car_loop_qpsk_low[i].crl_pilots_on_10;
+                        else if (state->srate <= 25000000)
+                                aclc = car_loop_qpsk_low[i].crl_pilots_on_20;
+                        else
+                                aclc = car_loop_qpsk_low[i].crl_pilots_on_30;
+                } else {
+                        if (state->srate <= 3000000)
+                                aclc = car_loop_qpsk_low[i].crl_pilots_off_2;
+                        else if (state->srate <= 7000000)
+                                aclc = car_loop_qpsk_low[i].crl_pilots_off_5;
+                        else if (state->srate <= 15000000)
+                                aclc = car_loop_qpsk_low[i].crl_pilots_off_10;
+                        else if (state->srate <= 25000000)
+                                aclc = car_loop_qpsk_low[i].crl_pilots_off_20;
+                        else
+                                aclc = car_loop_qpsk_low[i].crl_pilots_off_30;
+                }
+
+        } else if (modcod <= STV090x_8PSK_910) {
+                if (pilots) {
+                        if (state->srate <= 3000000)
+                                aclc = car_loop[i].crl_pilots_on_2;
+                        else if (state->srate <= 7000000)
+                                aclc = car_loop[i].crl_pilots_on_5;
+                        else if (state->srate <= 15000000)
+                                aclc = car_loop[i].crl_pilots_on_10;
+                        else if (state->srate <= 25000000)
+                                aclc = car_loop[i].crl_pilots_on_20;
+                        else
+                                aclc = car_loop[i].crl_pilots_on_30;
+                } else {
+                        if (state->srate <= 3000000)
+                                aclc = car_loop[i].crl_pilots_off_2;
+                        else if (state->srate <= 7000000)
+                                aclc = car_loop[i].crl_pilots_off_5;
+                        else if (state->srate <= 15000000)
+                                aclc = car_loop[i].crl_pilots_off_10;
+                        else if (state->srate <= 25000000)
+                                aclc = car_loop[i].crl_pilots_off_20;
+                        else
+                                aclc = car_loop[i].crl_pilots_off_30;
+                }
+        } else { /* 16APSK and 32APSK */
+                if (state->srate <= 3000000)
+                        aclc = car_loop_apsk_low[i].crl_pilots_on_2;
+                else if (state->srate <= 7000000)
+                        aclc = car_loop_apsk_low[i].crl_pilots_on_5;
+                else if (state->srate <= 15000000)
+                        aclc = car_loop_apsk_low[i].crl_pilots_on_10;
+                else if (state->srate <= 25000000)
+                        aclc = car_loop_apsk_low[i].crl_pilots_on_20;
+                else
+                        aclc = car_loop_apsk_low[i].crl_pilots_on_30;
+        }
+
+        return aclc;
+}
+
+static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
+{
+        struct stv090x_short_frame_crloop *short_crl;
+        s32 index = 0;
+        u8 aclc = 0x0b;
+
+        switch (state->modulation) {
+        case STV090x_QPSK:
+        default:
+                index = 0;
+                break;
+        case STV090x_8PSK:
+                index = 1;
+                break;
+        case STV090x_16APSK:
+                index = 2;
+                break;
+        case STV090x_32APSK:
+                index = 3;
+                break;
+        }
+
+        if (state->dev_ver >= 0x30)
+                short_crl = stv090x_s2_short_crl_cut20;
+        else if (state->dev_ver >= 0x20)
+                short_crl = stv090x_s2_short_crl_cut30;
+
+        if (state->srate <= 3000000)
+                aclc = short_crl[index].crl_2;
+        else if (state->srate <= 7000000)
+                aclc = short_crl[index].crl_5;
+        else if (state->srate <= 15000000)
+                aclc = short_crl[index].crl_10;
+        else if (state->srate <= 25000000)
+                aclc = short_crl[index].crl_20;
+        else
+                aclc = short_crl[index].crl_30;
+
+        return aclc;
+}
+
+static int stv090x_optimize_track(struct stv090x_state *state)
+{
+        struct dvb_frontend *fe = &state->frontend;
+
+        enum stv090x_rolloff rolloff;
+        enum stv090x_modcod modcod;
+
+        s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
+        u32 reg;
+
+        srate  = stv090x_get_srate(state, state->mclk);
+        srate += stv090x_get_tmgoffst(state, srate);
+
+        switch (state->delsys) {
+        case STV090x_DVBS1:
+        case STV090x_DSS:
+                if (state->algo == STV090x_SEARCH_AUTO) {
+                        reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+                        STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
+                        STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
+                        if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                                goto err;
+                }
+                reg = STV090x_READ_DEMOD(state, DEMOD);
+                STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
+                STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
+                if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
+                        goto err;
+
+                if (state->dev_ver >= 0x30) {
+                        if (stv090x_get_viterbi(state) < 0)
+                                goto err;
+
+                        if (state->fec == STV090x_PR12) {
+                                if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
+                                        goto err;
+                                if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
+                                        goto err;
+                        } else {
+                                if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
+                                        goto err;
+                                if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
+                                        goto err;
+                        }
+                }
+
+                if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
+                        goto err;
+                break;
+
+        case STV090x_DVBS2:
+                reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+                STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
+                STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
+                        goto err;
+                if (state->frame_len == STV090x_LONG_FRAME) {
+                        reg = STV090x_READ_DEMOD(state, DMDMODCOD);
+                        modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
+                        pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
+                        aclc = stv090x_optimize_carloop(state, modcod, pilots);
+                        if (modcod <= STV090x_QPSK_910) {
+                                STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
+                        } else if (modcod <= STV090x_8PSK_910) {
+                                if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
+                                        goto err;
+                                if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
+                                        goto err;
+                        }
+                        if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
+                                if (modcod <= STV090x_16APSK_910) {
+                                        if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
+                                                goto err;
+                                        if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
+                                                goto err;
+                                } else {
+                                        if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
+                                                goto err;
+                                        if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
+                                                goto err;
+                                }
+                        }
+                } else {
+                        /*Carrier loop setting for short frame*/
+                        aclc = stv090x_optimize_carloop_short(state);
+                        if (state->modulation == STV090x_QPSK) {
+                                if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
+                                        goto err;
+                        } else if (state->modulation == STV090x_8PSK) {
+                                if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
+                                        goto err;
+                                if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
+                                        goto err;
+                        } else if (state->modulation == STV090x_16APSK) {
+                                if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
+                                        goto err;
+                                if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
+                                        goto err;
+                        } else if (state->modulation == STV090x_32APSK)  {
+                                if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
+                                        goto err;
+                                if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
+                                        goto err;
+                        }
+                }
+
+                STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
+                break;
+
+        case STV090x_UNKNOWN:
+        default:
+                reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+                STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
+                STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                        goto err;
+                break;
+        }
+
+        f_1 = STV090x_READ_DEMOD(state, CFR2);
+        f_0 = STV090x_READ_DEMOD(state, CFR1);
+        reg = STV090x_READ_DEMOD(state, TMGOBS);
+        rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
+
+        if (state->algo == STV090x_BLIND_SEARCH) {
+                STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
+                reg = STV090x_READ_DEMOD(state, DMDCFGMD);
+                STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
+                STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
+                if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
+                        goto err;
+
+                if (stv090x_set_srate(state, srate) < 0)
+                        goto err;
+                blind_tune = 1;
+        }
+
+        if (state->dev_ver >= 0x20) {
+                if ((state->search_mode == STV090x_SEARCH_DVBS1)        ||
+                    (state->search_mode == STV090x_SEARCH_DSS)          ||
+                    (state->search_mode == STV090x_SEARCH_AUTO)) {
+
+                        if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
+                                goto err;
+                }
+        }
+
+        if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
+                goto err;
+
+        /* AUTO tracking MODE */
+        if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
+                goto err;
+        /* AUTO tracking MODE */
+        if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
+                goto err;
+
+        if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
+                /* update initial carrier freq with the found freq offset */
+                if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
+                        goto err;
+                state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
+
+                if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
+
+                        if (state->algo != STV090x_WARM_SEARCH) {
+
+                                if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
+                                        goto err;
+
+                                if (state->config->tuner_set_bandwidth) {
+                                        if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
+                                                goto err;
+                                }
+
+                                if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
+                                        goto err;
+
+                        }
+                }
+                if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
+                        msleep(50); /* blind search: wait 50ms for SR stabilization */
+                else
+                        msleep(5);
+
+                stv090x_get_lock_tmg(state);
+
+                if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
+                        if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
+                                goto err;
+
+                        i = 0;
+
+                        while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
+
+                                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
+                                        goto err;
+                                if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
+                                        goto err;
+                                if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
+                                        goto err;
+                                if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
+                                        goto err;
+                                i++;
+                        }
+                }
+
+        }
+
+        if (state->dev_ver >= 0x20) {
+                if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
+                        goto err;
+        }
+
+        if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
+                stv090x_set_vit_thtracq(state);
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
+{
+        s32 timer = 0, lock = 0, stat;
+        u32 reg;
+
+        while ((timer < timeout) && (!lock)) {
+                reg = STV090x_READ_DEMOD(state, DMDSTATE);
+                stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
+
+                switch (stat) {
+                case 0: /* searching */
+                case 1: /* first PLH detected */
+                default:
+                        lock = 0;
+                        break;
+
+                case 2: /* DVB-S2 mode */
+                        reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
+                        lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
+                        break;
+
+                case 3: /* DVB-S1/legacy mode */
+                        reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
+                        lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
+                        break;
+                }
+                if (!lock) {
+                        msleep(10);
+                        timer += 10;
+                }
+        }
+        return lock;
+}
+
+static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
+{
+        u32 reg;
+        s32 timer = 0;
+        int lock;
+
+        lock = stv090x_get_dmdlock(state, timeout_dmd);
+        if (lock)
+                lock = stv090x_get_feclock(state, timeout_fec);
+
+        if (lock) {
+                lock = 0;
+
+                while ((timer < timeout_fec) && (!lock)) {
+                        reg = STV090x_READ_DEMOD(state, TSSTATUS);
+                        lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
+                        msleep(1);
+                        timer++;
+                }
+        }
+
+        return lock;
+}
+
+static int stv090x_set_s2rolloff(struct stv090x_state *state)
+{
+        u32 reg;
+
+        if (state->dev_ver <= 0x20) {
+                /* rolloff to auto mode if DVBS2 */
+                reg = STV090x_READ_DEMOD(state, DEMOD);
+                STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
+                if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
+                        goto err;
+        } else {
+                /* DVB-S2 rolloff to auto mode if DVBS2 */
+                reg = STV090x_READ_DEMOD(state, DEMOD);
+                STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
+                if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
+                        goto err;
+        }
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+
+static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
+{
+        struct dvb_frontend *fe = &state->frontend;
+        enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
+        u32 reg;
+        s32 timeout_dmd = 500, timeout_fec = 50, agc1_power, power_iq = 0, i;
+        int lock = 0, low_sr = 0, no_signal = 0;
+
+        reg = STV090x_READ_DEMOD(state, TSCFGH);
+        STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
+        if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
+                goto err;
+
+        if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
+                goto err;
+
+        if (state->dev_ver >= 0x20) {
+                if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
+                        goto err;
+        }
+
+        stv090x_get_lock_tmg(state);
+
+        if (state->algo == STV090x_BLIND_SEARCH) {
+                state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
+                if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
+                        goto err;
+                if (stv090x_set_srate(state, 1000000) < 0) /* inital srate = 1Msps */
+                        goto err;
+        } else {
+                /* known srate */
+                if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
+                        goto err;
+                if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
+                        goto err;
+
+                if (state->srate < 2000000) {
+                        /* SR < 2MSPS */
+                        if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
+                                goto err;
+                } else {
+                        /* SR >= 2Msps */
+                        if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
+                                goto err;
+                }
+
+                if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
+                        goto err;
+
+                if (state->dev_ver >= 0x20) {
+                        if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
+                                goto err;
+                        if (state->algo == STV090x_COLD_SEARCH)
+                                state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
+                        else if (state->algo == STV090x_WARM_SEARCH)
+                                state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
+                }
+
+                /* if cold start or warm  (Symbolrate is known)
+                 * use a Narrow symbol rate scan range
+                 */
+                if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
+                        goto err;
+
+                if (stv090x_set_srate(state, state->srate) < 0)
+                        goto err;
+
+                if (stv090x_set_max_srate(state, state->mclk, state->srate) < 0)
+                        goto err;
+                if (stv090x_set_min_srate(state, state->mclk, state->srate) < 0)
+                        goto err;
+
+                if (state->srate >= 10000000)
+                        low_sr = 0;
+                else
+                        low_sr = 1;
+        }
+
+        /* Setup tuner */
+        if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
+                goto err;
+
+        if (state->config->tuner_set_bbgain) {
+                if (state->config->tuner_set_bbgain(fe, 10) < 0) /* 10dB */
+                        goto err;
+        }
+
+        if (state->config->tuner_set_frequency) {
+                if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
+                        goto err;
+        }
+
+        if (state->config->tuner_set_bandwidth) {
+                if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
+                        goto err;
+        }
+
+        if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
+                goto err;
+
+        msleep(50);
+
+        if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
+                goto err;
+
+        if (state->config->tuner_get_status) {
+                if (state->config->tuner_get_status(fe, &reg) < 0)
+                        goto err;
+        }
+
+        if (reg)
+                dprintk(FE_DEBUG, 1, "Tuner phase locked");
+        else
+                dprintk(FE_DEBUG, 1, "Tuner unlocked");
+
+        if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
+                goto err;
+
+        msleep(10);
+        agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
+                                STV090x_READ_DEMOD(state, AGCIQIN0));
+
+        if (agc1_power == 0) {
+                /* If AGC1 integrator value is 0
+                 * then read POWERI, POWERQ
+                 */
+                for (i = 0; i < 5; i++) {
+                        power_iq += (STV090x_READ_DEMOD(state, POWERI) +
+                                     STV090x_READ_DEMOD(state, POWERQ)) >> 1;
+                }
+                power_iq /= 5;
+        }
+
+        if ((agc1_power == 0) && (power_iq < STV090x_IQPOWER_THRESHOLD)) {
+                dprintk(FE_ERROR, 1, "No Signal: POWER_IQ=0x%02x", power_iq);
+                lock = 0;
+
+        } else {
+                reg = STV090x_READ_DEMOD(state, DEMOD);
+                STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
+
+                if (state->dev_ver <= 0x20) {
+                        /* rolloff to auto mode if DVBS2 */
+                        STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
+                } else {
+                        /* DVB-S2 rolloff to auto mode if DVBS2 */
+                        STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
+                }
+                if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
+                        goto err;
+
+                if (stv090x_delivery_search(state) < 0)
+                        goto err;
+
+                if (state->algo != STV090x_BLIND_SEARCH) {
+                        if (stv090x_start_search(state) < 0)
+                                goto err;
+                }
+        }
+
+        /* need to check for AGC1 state */
+
+
+
+        if (state->algo == STV090x_BLIND_SEARCH)
+                lock = stv090x_blind_search(state);
+
+        else if (state->algo == STV090x_COLD_SEARCH)
+                lock = stv090x_get_coldlock(state, timeout_dmd);
+
+        else if (state->algo == STV090x_WARM_SEARCH)
+                lock = stv090x_get_dmdlock(state, timeout_dmd);
+
+        if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
+                if (!low_sr) {
+                        if (stv090x_chk_tmg(state))
+                                lock = stv090x_sw_algo(state);
+                }
+        }
+
+        if (lock)
+                signal_state = stv090x_get_sig_params(state);
+
+        if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
+                stv090x_optimize_track(state);
+
+                if (state->dev_ver >= 0x20) {
+                        /* >= Cut 2.0 :release TS reset after
+                         * demod lock and optimized Tracking
+                         */
+                        reg = STV090x_READ_DEMOD(state, TSCFGH);
+                        STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
+                        if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
+                                goto err;
+
+                        msleep(3);
+
+                        STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
+                        if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
+                                goto err;
+
+                        STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
+                        if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
+                                goto err;
+                }
+
+                if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
+                        lock = 1;
+                        if (state->delsys == STV090x_DVBS2) {
+                                stv090x_set_s2rolloff(state);
+
+                                reg = STV090x_READ_DEMOD(state, PDELCTRL2);
+                                STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
+                                if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
+                                        goto err;
+                                /* Reset DVBS2 packet delinator error counter */
+                                reg = STV090x_READ_DEMOD(state, PDELCTRL2);
+                                STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
+                                if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
+                                        goto err;
+
+                                if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
+                                        goto err;
+                        } else {
+                                if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
+                                        goto err;
+                        }
+                        /* Reset the Total packet counter */
+                        if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
+                                goto err;
+                        /* Reset the packet Error counter2 */
+                        if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
+                                goto err;
+                } else {
+                        lock = 0;
+                        signal_state = STV090x_NODATA;
+                        no_signal = stv090x_chk_signal(state);
+                }
+        }
+        return signal_state;
+
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        struct dtv_frontend_properties *props = &fe->dtv_property_cache;
+
+        state->delsys = props->delivery_system;
+        state->frequency = p->frequency;
+        state->srate = p->u.qpsk.symbol_rate;
+        state->search_mode = STV090x_SEARCH_AUTO;
+        state->algo = STV090x_COLD_SEARCH;
+        state->fec = STV090x_PRERR;
+        state->search_range = 2000000;
+
+        if (stv090x_algo(state) == STV090x_RANGEOK) {
+                dprintk(FE_DEBUG, 1, "Search success!");
+                return DVBFE_ALGO_SEARCH_SUCCESS;
+        } else {
+                dprintk(FE_DEBUG, 1, "Search failed!");
+                return DVBFE_ALGO_SEARCH_FAILED;
+        }
+
+        return DVBFE_ALGO_SEARCH_ERROR;
+}
+
+/* FIXME! */
+static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        u32 reg;
+        u8 search_state;
+
+        reg = STV090x_READ_DEMOD(state, DMDSTATE);
+        search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
+
+        switch (search_state) {
+        case 0: /* searching */
+        case 1: /* first PLH detected */
+        default:
+                dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
+                *status = 0;
+                break;
+
+        case 2: /* DVB-S2 mode */
+                dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
+                reg = STV090x_READ_DEMOD(state, DSTATUS);
+                if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
+                        reg = STV090x_READ_DEMOD(state, TSSTATUS);
+                        if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
+                                *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+                        }
+                }
+                break;
+
+        case 3: /* DVB-S1/legacy mode */
+                dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
+                reg = STV090x_READ_DEMOD(state, DSTATUS);
+                if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
+                        reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
+                        if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
+                                reg = STV090x_READ_DEMOD(state, TSSTATUS);
+                                if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
+                                        *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+                                }
+                        }
+                }
+                break;
+        }
+
+        return 0;
+}
+
+static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+
+        s32 count_4, count_3, count_2, count_1, count_0, count;
+        u32 reg, h, m, l;
+        enum fe_status status;
+
+        stv090x_read_status(fe, &status);
+        if (!(status & FE_HAS_LOCK)) {
+                *per = 1 << 23; /* Max PER */
+        } else {
+                /* Counter 2 */
+                reg = STV090x_READ_DEMOD(state, ERRCNT22);
+                h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
+
+                reg = STV090x_READ_DEMOD(state, ERRCNT21);
+                m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
+
+                reg = STV090x_READ_DEMOD(state, ERRCNT20);
+                l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
+
+                *per = ((h << 16) | (m << 8) | l);
+
+                count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
+                count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
+                count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
+                count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
+                count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
+
+                if ((!count_4) && (!count_3)) {
+                        count  = (count_2 & 0xff) << 16;
+                        count |= (count_1 & 0xff) <<  8;
+                        count |=  count_0 & 0xff;
+                } else {
+                        count = 1 << 24;
+                }
+                if (count == 0)
+                        *per = 1;
+        }
+        if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
+{
+        int res = 0;
+        int min = 0, med;
+
+        if (val < tab[min].read)
+                res = tab[min].real;
+        else if (val >= tab[max].read)
+                res = tab[max].real;
+        else {
+                while ((max - min) > 1) {
+                        med = (max + min) / 2;
+                        if (val >= tab[min].read && val < tab[med].read)
+                                max = med;
+                        else
+                                min = med;
+                }
+                res = ((val - tab[min].read) *
+                       (tab[max].real - tab[min].real) /
+                       (tab[max].read - tab[min].read)) +
+                        tab[min].real;
+        }
+
+        return res;
+}
+
+static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        u32 reg;
+        s32 agc;
+
+        reg = STV090x_READ_DEMOD(state, AGCIQIN1);
+        agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
+
+        *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
+        if (agc > stv090x_rf_tab[0].read)
+                *strength = 5;
+        else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
+                *strength = -100;
+
+        return 0;
+}
+
+static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        u32 reg_0, reg_1, reg, i;
+        s32 val_0, val_1, val = 0;
+        u8 lock_f;
+
+        switch (state->delsys) {
+        case STV090x_DVBS2:
+                reg = STV090x_READ_DEMOD(state, DSTATUS);
+                lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
+                if (lock_f) {
+                        msleep(5);
+                        for (i = 0; i < 16; i++) {
+                                reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
+                                val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
+                                reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
+                                val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
+                                val  += MAKEWORD16(val_1, val_0);
+                                msleep(1);
+                        }
+                        val /= 16;
+                        *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val);
+                        if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read)
+                                *cnr = 1000;
+                }
+                break;
+
+        case STV090x_DVBS1:
+        case STV090x_DSS:
+                reg = STV090x_READ_DEMOD(state, DSTATUS);
+                lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
+                if (lock_f) {
+                        msleep(5);
+                        for (i = 0; i < 16; i++) {
+                                reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
+                                val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
+                                reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
+                                val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
+                                val  += MAKEWORD16(val_1, val_0);
+                                msleep(1);
+                        }
+                        val /= 16;
+                        *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val);
+                        if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read)
+                                *cnr = 1000;
+                }
+                break;
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        u32 reg;
+
+        reg = STV090x_READ_DEMOD(state, DISTXCTL);
+        switch (tone) {
+        case SEC_TONE_ON:
+                STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
+                STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
+                if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
+                        goto err;
+                STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
+                if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
+                        goto err;
+                break;
+
+        case SEC_TONE_OFF:
+                STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
+                STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
+                if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
+                        goto err;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+
+static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
+{
+        return DVBFE_ALGO_CUSTOM;
+}
+
+static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        u32 reg, idle = 0, fifo_full = 1;
+        int i;
+
+        reg = STV090x_READ_DEMOD(state, DISTXCTL);
+
+        STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 2);
+        STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
+        if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
+                goto err;
+        STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
+        if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
+                goto err;
+
+        STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
+        if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
+                goto err;
+
+        for (i = 0; i < cmd->msg_len; i++) {
+
+                while (fifo_full) {
+                        reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
+                        fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
+                }
+
+                if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
+                        goto err;
+        }
+        reg = STV090x_READ_DEMOD(state, DISTXCTL);
+        STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
+        if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
+                goto err;
+
+        i = 0;
+
+        while ((!idle) && (i < 10)) {
+                reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
+                idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
+                msleep(10);
+                i++;
+        }
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        u32 reg, idle = 0, fifo_full = 1;
+        u8 mode, value;
+        int i;
+
+        reg = STV090x_READ_DEMOD(state, DISTXCTL);
+
+        if (burst == SEC_MINI_A) {
+                mode = 3;
+                value = 0x00;
+        } else {
+                mode = 2;
+                value = 0xFF;
+        }
+
+        STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
+        STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
+        if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
+                goto err;
+        STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
+        if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
+                goto err;
+
+        STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
+        if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
+                goto err;
+
+        while (fifo_full) {
+                reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
+                fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
+        }
+
+        if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
+                goto err;
+
+        reg = STV090x_READ_DEMOD(state, DISTXCTL);
+        STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
+        if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
+                goto err;
+
+        i = 0;
+
+        while ((!idle) && (i < 10)) {
+                reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
+                idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
+                msleep(10);
+                i++;
+        }
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        u32 reg = 0, i = 0, rx_end = 0;
+
+        while ((rx_end != 1) && (i < 10)) {
+                msleep(10);
+                i++;
+                reg = STV090x_READ_DEMOD(state, DISRX_ST0);
+                rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
+        }
+
+        if (rx_end) {
+                reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
+                for (i = 0; i < reply->msg_len; i++)
+                        reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
+        }
+
+        return 0;
+}
+
+static int stv090x_sleep(struct dvb_frontend *fe)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        u32 reg;
+
+        dprintk(FE_DEBUG, 1, "Set %s to sleep",
+                state->device == STV0900 ? "STV0900" : "STV0903");
+
+        reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
+        STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
+        if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
+                goto err;
+
+        reg = stv090x_read_reg(state, STV090x_TSTTNR1);
+        STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
+        if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_wakeup(struct dvb_frontend *fe)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        u32 reg;
+
+        dprintk(FE_DEBUG, 1, "Wake %s from standby",
+                state->device == STV0900 ? "STV0900" : "STV0903");
+
+        reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
+        STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
+        if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
+                goto err;
+
+        reg = stv090x_read_reg(state, STV090x_TSTTNR1);
+        STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
+        if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static void stv090x_release(struct dvb_frontend *fe)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+
+        kfree(state);
+}
+
+static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
+{
+        u32 reg = 0;
+
+        switch (ldpc_mode) {
+        case STV090x_DUAL:
+        default:
+                if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
+                        /* set LDPC to dual mode */
+                        if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
+                                goto err;
+
+                        state->demod_mode = STV090x_DUAL;
+
+                        reg = stv090x_read_reg(state, STV090x_TSTRES0);
+                        STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
+                        if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
+                                goto err;
+                        STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
+                        if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
+                                goto err;
+
+                        if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
+                                goto err;
+
+                        if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
+                                goto err;
+
+                        if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
+                                goto err;
+                        if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
+                                goto err;
+                }
+                break;
+
+        case STV090x_SINGLE:
+                if (stv090x_stop_modcod(state) < 0)
+                        goto err;
+                if (stv090x_activate_modcod_single(state) < 0)
+                        goto err;
+
+                if (state->demod == STV090x_DEMODULATOR_1) {
+                        if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
+                                goto err;
+                } else {
+                        if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
+                                goto err;
+                }
+
+                reg = stv090x_read_reg(state, STV090x_TSTRES0);
+                STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
+                if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
+                        goto err;
+                STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
+                if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
+                        goto err;
+
+                reg = STV090x_READ_DEMOD(state, PDELCTRL1);
+                STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
+                if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
+                        goto err;
+                STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
+                if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
+                        goto err;
+                break;
+        }
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+/* return (Hz), clk in Hz*/
+static u32 stv090x_get_mclk(struct stv090x_state *state)
+{
+        const struct stv090x_config *config = state->config;
+        u32 div, reg;
+        u8 ratio;
+
+        div = stv090x_read_reg(state, STV090x_NCOARSE);
+        reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
+        ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
+
+        return (div + 1) * config->xtal / ratio; /* kHz */
+}
+
+static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
+{
+        const struct stv090x_config *config = state->config;
+        u32 reg, div, clk_sel;
+
+        reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
+        clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
+
+        div = ((clk_sel * mclk) / config->xtal) - 1;
+
+        reg = stv090x_read_reg(state, STV090x_NCOARSE);
+        STV090x_SETFIELD(reg, M_DIV_FIELD, div);
+        if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
+                goto err;
+
+        state->mclk = stv090x_get_mclk(state);
+
+        /*Set the DiseqC frequency to 22KHz */
+        div = state->mclk / 704000;
+        if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
+                goto err;
+        if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_set_tspath(struct stv090x_state *state)
+{
+        u32 reg;
+
+        if (state->dev_ver >= 0x20) {
+                switch (state->config->ts1_mode) {
+                case STV090x_TSMODE_PARALLEL_PUNCTURED:
+                case STV090x_TSMODE_DVBCI:
+                        switch (state->config->ts2_mode) {
+                        case STV090x_TSMODE_SERIAL_PUNCTURED:
+                        case STV090x_TSMODE_SERIAL_CONTINUOUS:
+                        default:
+                                stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
+                                break;
+
+                        case STV090x_TSMODE_PARALLEL_PUNCTURED:
+                        case STV090x_TSMODE_DVBCI:
+                                if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
+                                        goto err;
+                                reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
+                                STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
+                                if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
+                                        goto err;
+                                reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
+                                STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
+                                if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
+                                        goto err;
+                                if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
+                                        goto err;
+                                if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
+                                        goto err;
+                                break;
+                        }
+                        break;
+
+                case STV090x_TSMODE_SERIAL_PUNCTURED:
+                case STV090x_TSMODE_SERIAL_CONTINUOUS:
+                default:
+                        switch (state->config->ts2_mode) {
+                        case STV090x_TSMODE_SERIAL_PUNCTURED:
+                        case STV090x_TSMODE_SERIAL_CONTINUOUS:
+                        default:
+                                if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
+                                        goto err;
+                                break;
+
+                        case STV090x_TSMODE_PARALLEL_PUNCTURED:
+                        case STV090x_TSMODE_DVBCI:
+                                if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
+                                        goto err;
+                                break;
+                        }
+                        break;
+                }
+        } else {
+                switch (state->config->ts1_mode) {
+                case STV090x_TSMODE_PARALLEL_PUNCTURED:
+                case STV090x_TSMODE_DVBCI:
+                        switch (state->config->ts2_mode) {
+                        case STV090x_TSMODE_SERIAL_PUNCTURED:
+                        case STV090x_TSMODE_SERIAL_CONTINUOUS:
+                        default:
+                                stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
+                                break;
+
+                        case STV090x_TSMODE_PARALLEL_PUNCTURED:
+                        case STV090x_TSMODE_DVBCI:
+                                stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
+                                reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
+                                STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
+                                if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
+                                        goto err;
+                                reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
+                                STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
+                                if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
+                                        goto err;
+                                if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
+                                        goto err;
+                                if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
+                                        goto err;
+                                break;
+                        }
+                        break;
+
+                case STV090x_TSMODE_SERIAL_PUNCTURED:
+                case STV090x_TSMODE_SERIAL_CONTINUOUS:
+                default:
+                        switch (state->config->ts2_mode) {
+                        case STV090x_TSMODE_SERIAL_PUNCTURED:
+                        case STV090x_TSMODE_SERIAL_CONTINUOUS:
+                        default:
+                                stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
+                                break;
+
+                        case STV090x_TSMODE_PARALLEL_PUNCTURED:
+                        case STV090x_TSMODE_DVBCI:
+                                stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
+                                break;
+                        }
+                        break;
+                }
+        }
+
+        switch (state->config->ts1_mode) {
+        case STV090x_TSMODE_PARALLEL_PUNCTURED:
+                reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
+                STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
+                STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
+                if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
+                        goto err;
+                break;
+
+        case STV090x_TSMODE_DVBCI:
+                reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
+                STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
+                STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
+                if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
+                        goto err;
+                break;
+
+        case STV090x_TSMODE_SERIAL_PUNCTURED:
+                reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
+                STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
+                STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
+                if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
+                        goto err;
+                break;
+
+        case STV090x_TSMODE_SERIAL_CONTINUOUS:
+                reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
+                STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
+                STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
+                if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
+                        goto err;
+                break;
+
+        default:
+                break;
+        }
+
+        switch (state->config->ts2_mode) {
+        case STV090x_TSMODE_PARALLEL_PUNCTURED:
+                reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
+                STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
+                STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
+                if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
+                        goto err;
+                break;
+
+        case STV090x_TSMODE_DVBCI:
+                reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
+                STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
+                STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
+                if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
+                        goto err;
+                break;
+
+        case STV090x_TSMODE_SERIAL_PUNCTURED:
+                reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
+                STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
+                STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
+                if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
+                        goto err;
+                break;
+
+        case STV090x_TSMODE_SERIAL_CONTINUOUS:
+                reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
+                STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
+                STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
+                if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
+                        goto err;
+                break;
+
+        default:
+                break;
+        }
+        reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
+        STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
+        if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
+                goto err;
+        STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
+        if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
+                goto err;
+
+        reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
+        STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
+        if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
+                goto err;
+        STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
+        if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_init(struct dvb_frontend *fe)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        const struct stv090x_config *config = state->config;
+        u32 reg;
+
+        if (stv090x_wakeup(fe) < 0) {
+                dprintk(FE_ERROR, 1, "Error waking device");
+                goto err;
+        }
+
+        if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
+                goto err;
+
+        reg = STV090x_READ_DEMOD(state, TNRCFG2);
+        STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
+        if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
+                goto err;
+        reg = STV090x_READ_DEMOD(state, DEMOD);
+        STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
+        if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
+                goto err;
+
+        if (stv090x_i2c_gate_ctrl(fe, 1) < 0)
+                goto err;
+
+        if (config->tuner_set_mode) {
+                if (config->tuner_set_mode(fe, TUNER_WAKE) < 0)
+                        goto err;
+        }
+
+        if (config->tuner_init) {
+                if (config->tuner_init(fe) < 0)
+                        goto err;
+        }
+
+        if (stv090x_i2c_gate_ctrl(fe, 0) < 0)
+                goto err;
+
+        if (stv090x_set_tspath(state) < 0)
+                goto err;
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static int stv090x_setup(struct dvb_frontend *fe)
+{
+        struct stv090x_state *state = fe->demodulator_priv;
+        const struct stv090x_config *config = state->config;
+        const struct stv090x_reg *stv090x_initval = NULL;
+        const struct stv090x_reg *stv090x_cut20_val = NULL;
+        unsigned long t1_size = 0, t2_size = 0;
+        u32 reg = 0;
+
+        int i;
+
+        if (state->device == STV0900) {
+                dprintk(FE_DEBUG, 1, "Initializing STV0900");
+                stv090x_initval = stv0900_initval;
+                t1_size = ARRAY_SIZE(stv0900_initval);
+                stv090x_cut20_val = stv0900_cut20_val;
+                t2_size = ARRAY_SIZE(stv0900_cut20_val);
+        } else if (state->device == STV0903) {
+                dprintk(FE_DEBUG, 1, "Initializing STV0903");
+                stv090x_initval = stv0903_initval;
+                t1_size = ARRAY_SIZE(stv0903_initval);
+                stv090x_cut20_val = stv0903_cut20_val;
+                t2_size = ARRAY_SIZE(stv0903_cut20_val);
+        }
+
+        /* STV090x init */
+        if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
+                goto err;
+
+        msleep(5);
+
+        if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
+                goto err;
+
+        STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
+        if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) /* repeater OFF */
+                goto err;
+
+        if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
+                goto err;
+        msleep(5);
+        if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
+                goto err;
+        if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
+                goto err;
+        msleep(5);
+
+        /* write initval */
+        dprintk(FE_DEBUG, 1, "Setting up initial values");
+        for (i = 0; i < t1_size; i++) {
+                if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
+                        goto err;
+        }
+
+        state->dev_ver = stv090x_read_reg(state, STV090x_MID);
+        if (state->dev_ver >= 0x20) {
+                if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
+                        goto err;
+
+                /* write cut20_val*/
+                dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
+                for (i = 0; i < t2_size; i++) {
+                        if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
+                                goto err;
+                }
+
+        } else if (state->dev_ver < 0x20) {
+                dprintk(FE_ERROR, 1, "ERROR: Unsupported Cut: 0x%02x!",
+                        state->dev_ver);
+
+                goto err;
+        } else if (state->dev_ver > 0x30) {
+                /* we shouldn't bail out from here */
+                dprintk(FE_ERROR, 1, "INFO: Cut: 0x%02x probably incomplete support!",
+                        state->dev_ver);
+        }
+
+        if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
+                goto err;
+        if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
+                goto err;
+
+        stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
+        msleep(5);
+        if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
+                goto err;
+        stv090x_get_mclk(state);
+
+        return 0;
+err:
+        dprintk(FE_ERROR, 1, "I/O error");
+        return -1;
+}
+
+static struct dvb_frontend_ops stv090x_ops = {
+
+        .info = {
+                .name                   = "STV090x Multistandard",
+                .type                   = FE_QPSK,
+                .frequency_min          = 950000,
+                .frequency_max          = 2150000,
+                .frequency_stepsize     = 0,
+                .frequency_tolerance    = 0,
+                .symbol_rate_min        = 1000000,
+                .symbol_rate_max        = 45000000,
+                .caps                   = FE_CAN_INVERSION_AUTO |
+                                          FE_CAN_FEC_AUTO       |
+                                          FE_CAN_QPSK           |
+                                          FE_CAN_2G_MODULATION
+        },
+
+        .release                        = stv090x_release,
+        .init                           = stv090x_init,
+
+        .sleep                          = stv090x_sleep,
+        .get_frontend_algo              = stv090x_frontend_algo,
+
+        .i2c_gate_ctrl                  = stv090x_i2c_gate_ctrl,
+
+        .diseqc_send_master_cmd         = stv090x_send_diseqc_msg,
+        .diseqc_send_burst              = stv090x_send_diseqc_burst,
+        .diseqc_recv_slave_reply        = stv090x_recv_slave_reply,
+        .set_tone                       = stv090x_set_tone,
+
+        .search                         = stv090x_search,
+        .read_status                    = stv090x_read_status,
+        .read_ber                       = stv090x_read_per,
+        .read_signal_strength           = stv090x_read_signal_strength,
+        .read_snr                       = stv090x_read_cnr
+};
+
+
+struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
+                                    struct i2c_adapter *i2c,
+                                    enum stv090x_demodulator demod)
+{
+        struct stv090x_state *state = NULL;
+
+        state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
+        if (state == NULL)
+                goto error;
+
+        state->verbose                          = &verbose;
+        state->config                           = config;
+        state->i2c                              = i2c;
+        state->frontend.ops                     = stv090x_ops;
+        state->frontend.demodulator_priv        = state;
+        state->demod                            = demod;
+        state->demod_mode                       = config->demod_mode; /* Single or Dual mode */
+        state->device                           = config->device;
+        state->rolloff                          = STV090x_RO_35; /* default */
+
+        if (state->demod == STV090x_DEMODULATOR_0)
+                mutex_init(&demod_lock);
+
+        if (stv090x_sleep(&state->frontend) < 0) {
+                dprintk(FE_ERROR, 1, "Error putting device to sleep");
+                goto error;
+        }
+
+        if (stv090x_setup(&state->frontend) < 0) {
+                dprintk(FE_ERROR, 1, "Error setting up device");
+                goto error;
+        }
+        if (stv090x_wakeup(&state->frontend) < 0) {
+                dprintk(FE_ERROR, 1, "Error waking device");
+                goto error;
+        }
+
+        dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
+               state->device == STV0900 ? "STV0900" : "STV0903",
+               demod,
+               state->dev_ver);
+
+        return &state->frontend;
+
+error:
+        kfree(state);
+        return NULL;
+}
+EXPORT_SYMBOL(stv090x_attach);
+MODULE_PARM_DESC(verbose, "Set Verbosity level");
+MODULE_AUTHOR("Manu Abraham");
+MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/stv090x.h b/drivers/media/dvb/frontends/stv090x.h
new file mode 100644
index 000000000000..e968c98bb70f
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv090x.h
@@ -0,0 +1,106 @@
+/*
+        STV0900/0903 Multistandard Broadcast Frontend driver
+        Copyright (C) Manu Abraham <abraham.manu@gmail.com>
+
+        Copyright (C) ST Microelectronics
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __STV090x_H
+#define __STV090x_H
+
+enum stv090x_demodulator {
+        STV090x_DEMODULATOR_0 = 1,
+        STV090x_DEMODULATOR_1
+};
+
+enum stv090x_device {
+        STV0903 =  0,
+        STV0900,
+};
+
+enum stv090x_mode {
+        STV090x_DUAL = 0,
+        STV090x_SINGLE
+};
+
+enum stv090x_tsmode {
+        STV090x_TSMODE_SERIAL_PUNCTURED = 1,
+        STV090x_TSMODE_SERIAL_CONTINUOUS,
+        STV090x_TSMODE_PARALLEL_PUNCTURED,
+        STV090x_TSMODE_DVBCI
+};
+
+enum stv090x_clkmode {
+        STV090x_CLK_INT = 0, /* Clk i/p = CLKI */
+        STV090x_CLK_EXT = 2 /* Clk i/p = XTALI */
+};
+
+enum stv090x_i2crpt {
+        STV090x_RPTLEVEL_256    = 0,
+        STV090x_RPTLEVEL_128    = 1,
+        STV090x_RPTLEVEL_64     = 2,
+        STV090x_RPTLEVEL_32     = 3,
+        STV090x_RPTLEVEL_16     = 4,
+        STV090x_RPTLEVEL_8      = 5,
+        STV090x_RPTLEVEL_4      = 6,
+        STV090x_RPTLEVEL_2      = 7,
+};
+
+struct stv090x_config {
+        enum stv090x_device     device;
+        enum stv090x_mode       demod_mode;
+        enum stv090x_clkmode    clk_mode;
+
+        u32 xtal; /* default: 8000000 */
+        u8 address; /* default: 0x68 */
+
+        u32 ref_clk; /* default: 16000000 FIXME to tuner config */
+
+        u8 ts1_mode;
+        u8 ts2_mode;
+
+        enum stv090x_i2crpt     repeater_level;
+
+        int (*tuner_init) (struct dvb_frontend *fe);
+        int (*tuner_set_mode) (struct dvb_frontend *fe, enum tuner_mode mode);
+        int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency);
+        int (*tuner_get_frequency) (struct dvb_frontend *fe, u32 *frequency);
+        int (*tuner_set_bandwidth) (struct dvb_frontend *fe, u32 bandwidth);
+        int (*tuner_get_bandwidth) (struct dvb_frontend *fe, u32 *bandwidth);
+        int (*tuner_set_bbgain) (struct dvb_frontend *fe, u32 gain);
+        int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain);
+        int (*tuner_set_refclk)  (struct dvb_frontend *fe, u32 refclk);
+        int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status);
+};
+
+#if defined(CONFIG_DVB_STV090x) || (defined(CONFIG_DVB_STV090x_MODULE) && defined(MODULE))
+
+extern struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
+                                           struct i2c_adapter *i2c,
+                                           enum stv090x_demodulator demod);
+#else
+
+static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
+                                                  struct i2c_adapter *i2c,
+                                                  enum stv090x_demodulator demod)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return NULL;
+}
+#endif /* CONFIG_DVB_STV090x */
+
+#endif /* __STV090x_H */
diff --git a/drivers/media/dvb/frontends/stv090x_priv.h b/drivers/media/dvb/frontends/stv090x_priv.h
new file mode 100644
index 000000000000..5a4a01740d88
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv090x_priv.h
@@ -0,0 +1,269 @@
+/*
+        STV0900/0903 Multistandard Broadcast Frontend driver
+        Copyright (C) Manu Abraham <abraham.manu@gmail.com>
+
+        Copyright (C) ST Microelectronics
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __STV090x_PRIV_H
+#define __STV090x_PRIV_H
+
+#include "dvb_frontend.h"
+
+#define FE_ERROR                                0
+#define FE_NOTICE                               1
+#define FE_INFO                                 2
+#define FE_DEBUG                                3
+#define FE_DEBUGREG                             4
+
+#define dprintk(__y, __z, format, arg...) do {                                          \
+        if (__z) {                                                                      \
+                if      ((verbose > FE_ERROR) && (verbose > __y))                       \
+                        printk(KERN_ERR "%s: " format "\n", __func__ , ##arg);          \
+                else if ((verbose > FE_NOTICE) && (verbose > __y))                      \
+                        printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg);       \
+                else if ((verbose > FE_INFO) && (verbose > __y))                        \
+                        printk(KERN_INFO "%s: " format "\n", __func__ , ##arg);         \
+                else if ((verbose > FE_DEBUG) && (verbose > __y))                       \
+                        printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg);        \
+        } else {                                                                        \
+                if (verbose > __y)                                                      \
+                        printk(format, ##arg);                                          \
+        }                                                                               \
+} while (0)
+
+#define STV090x_READ_DEMOD(__state, __reg) ((                   \
+        (__state)->demod == STV090x_DEMODULATOR_1)      ?       \
+        stv090x_read_reg(__state, STV090x_P2_##__reg) :         \
+        stv090x_read_reg(__state, STV090x_P1_##__reg))
+
+#define STV090x_WRITE_DEMOD(__state, __reg, __data) ((          \
+        (__state)->demod == STV090x_DEMODULATOR_1)      ?       \
+        stv090x_write_reg(__state, STV090x_P2_##__reg, __data) :\
+        stv090x_write_reg(__state, STV090x_P1_##__reg, __data))
+
+#define STV090x_ADDR_OFFST(__state, __x) ((                     \
+        (__state->demod) == STV090x_DEMODULATOR_1)      ?       \
+                STV090x_P1_##__x :                              \
+                STV090x_P2_##__x)
+
+
+#define STV090x_SETFIELD(mask, bitf, val)       (mask = (mask & (~(((1 << STV090x_WIDTH_##bitf) - 1) <<\
+                                                         STV090x_OFFST_##bitf))) | \
+                                                         (val << STV090x_OFFST_##bitf))
+
+#define STV090x_GETFIELD(val, bitf)             ((val >> STV090x_OFFST_##bitf) & ((1 << STV090x_WIDTH_##bitf) - 1))
+
+
+#define STV090x_SETFIELD_Px(mask, bitf, val)    (mask = (mask & (~(((1 << STV090x_WIDTH_Px_##bitf) - 1) <<\
+                                                         STV090x_OFFST_Px_##bitf))) | \
+                                                         (val << STV090x_OFFST_Px_##bitf))
+
+#define STV090x_GETFIELD_Px(val, bitf)          ((val >> STV090x_OFFST_Px_##bitf) & ((1 << STV090x_WIDTH_Px_##bitf) - 1))
+
+#define MAKEWORD16(__a, __b)                    (((__a) << 8) | (__b))
+
+#define MSB(__x)                                ((__x >> 8) & 0xff)
+#define LSB(__x)                                (__x & 0xff)
+
+
+#define STV090x_IQPOWER_THRESHOLD         30
+#define STV090x_SEARCH_AGC2_TH_CUT20     700
+#define STV090x_SEARCH_AGC2_TH_CUT30    1200
+
+#define STV090x_SEARCH_AGC2_TH(__ver)   \
+        ((__ver <= 0x20) ?              \
+        STV090x_SEARCH_AGC2_TH_CUT20 :  \
+        STV090x_SEARCH_AGC2_TH_CUT30)
+
+enum stv090x_signal_state {
+        STV090x_NOCARRIER,
+        STV090x_NODATA,
+        STV090x_DATAOK,
+        STV090x_RANGEOK,
+        STV090x_OUTOFRANGE
+};
+
+enum stv090x_fec {
+        STV090x_PR12 = 0,
+        STV090x_PR23,
+        STV090x_PR34,
+        STV090x_PR45,
+        STV090x_PR56,
+        STV090x_PR67,
+        STV090x_PR78,
+        STV090x_PR89,
+        STV090x_PR910,
+        STV090x_PRERR
+};
+
+enum stv090x_modulation {
+        STV090x_QPSK,
+        STV090x_8PSK,
+        STV090x_16APSK,
+        STV090x_32APSK,
+        STV090x_UNKNOWN
+};
+
+enum stv090x_frame {
+        STV090x_LONG_FRAME,
+        STV090x_SHORT_FRAME
+};
+
+enum stv090x_pilot {
+        STV090x_PILOTS_OFF,
+        STV090x_PILOTS_ON
+};
+
+enum stv090x_rolloff {
+        STV090x_RO_35,
+        STV090x_RO_25,
+        STV090x_RO_20
+};
+
+enum stv090x_inversion {
+        STV090x_IQ_AUTO,
+        STV090x_IQ_NORMAL,
+        STV090x_IQ_SWAP
+};
+
+enum stv090x_modcod {
+        STV090x_DUMMY_PLF = 0,
+        STV090x_QPSK_14,
+        STV090x_QPSK_13,
+        STV090x_QPSK_25,
+        STV090x_QPSK_12,
+        STV090x_QPSK_35,
+        STV090x_QPSK_23,
+        STV090x_QPSK_34,
+        STV090x_QPSK_45,
+        STV090x_QPSK_56,
+        STV090x_QPSK_89,
+        STV090x_QPSK_910,
+        STV090x_8PSK_35,
+        STV090x_8PSK_23,
+        STV090x_8PSK_34,
+        STV090x_8PSK_56,
+        STV090x_8PSK_89,
+        STV090x_8PSK_910,
+        STV090x_16APSK_23,
+        STV090x_16APSK_34,
+        STV090x_16APSK_45,
+        STV090x_16APSK_56,
+        STV090x_16APSK_89,
+        STV090x_16APSK_910,
+        STV090x_32APSK_34,
+        STV090x_32APSK_45,
+        STV090x_32APSK_56,
+        STV090x_32APSK_89,
+        STV090x_32APSK_910,
+        STV090x_MODCODE_UNKNOWN
+};
+
+enum stv090x_search {
+        STV090x_SEARCH_DSS = 0,
+        STV090x_SEARCH_DVBS1,
+        STV090x_SEARCH_DVBS2,
+        STV090x_SEARCH_AUTO
+};
+
+enum stv090x_algo {
+        STV090x_BLIND_SEARCH,
+        STV090x_COLD_SEARCH,
+        STV090x_WARM_SEARCH
+};
+
+enum stv090x_delsys {
+        STV090x_ERROR = 0,
+        STV090x_DVBS1 = 1,
+        STV090x_DVBS2,
+        STV090x_DSS
+};
+
+struct stv090x_long_frame_crloop {
+        enum stv090x_modcod     modcod;
+
+        u8 crl_pilots_on_2;
+        u8 crl_pilots_off_2;
+        u8 crl_pilots_on_5;
+        u8 crl_pilots_off_5;
+        u8 crl_pilots_on_10;
+        u8 crl_pilots_off_10;
+        u8 crl_pilots_on_20;
+        u8 crl_pilots_off_20;
+        u8 crl_pilots_on_30;
+        u8 crl_pilots_off_30;
+};
+
+struct stv090x_short_frame_crloop {
+        enum stv090x_modulation modulation;
+
+        u8 crl_2;  /*      SR <   3M */
+        u8 crl_5;  /*  3 < SR <=  7M */
+        u8 crl_10; /*  7 < SR <= 15M */
+        u8 crl_20; /* 10 < SR <= 25M */
+        u8 crl_30; /* 10 < SR <= 45M */
+};
+
+struct stv090x_reg {
+        u16 addr;
+        u8  data;
+};
+
+struct stv090x_tab {
+        s32 real;
+        s32 read;
+};
+
+struct stv090x_state {
+        enum stv090x_device             device;
+        enum stv090x_demodulator        demod;
+        enum stv090x_mode               demod_mode;
+        u32                             dev_ver;
+
+        struct i2c_adapter              *i2c;
+        const struct stv090x_config     *config;
+        struct dvb_frontend             frontend;
+
+        u32                             *verbose; /* Cached module verbosity */
+
+        enum stv090x_delsys             delsys;
+        enum stv090x_fec                fec;
+        enum stv090x_modulation         modulation;
+        enum stv090x_modcod             modcod;
+        enum stv090x_search             search_mode;
+        enum stv090x_frame              frame_len;
+        enum stv090x_pilot              pilots;
+        enum stv090x_rolloff            rolloff;
+        enum stv090x_inversion          inversion;
+        enum stv090x_algo               algo;
+
+        u32                             frequency;
+        u32                             srate;
+
+        s32                             mclk; /* Masterclock Divider factor */
+        s32                             tuner_bw;
+
+        u32                             tuner_refclk;
+
+        s32                             search_range;
+
+        s32                             DemodTimeout;
+        s32                             FecTimeout;
+};
+
+#endif /* __STV090x_PRIV_H */
diff --git a/drivers/media/dvb/frontends/stv090x_reg.h b/drivers/media/dvb/frontends/stv090x_reg.h
new file mode 100644
index 000000000000..57b6abbbd32d
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv090x_reg.h
@@ -0,0 +1,2373 @@
+/*
+        STV0900/0903 Multistandard Broadcast Frontend driver
+        Copyright (C) Manu Abraham <abraham.manu@gmail.com>
+
+        Copyright (C) ST Microelectronics
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __STV090x_REG_H
+#define __STV090x_REG_H
+
+#define STV090x_MID                             0xf100
+#define STV090x_OFFST_MCHIP_IDENT_FIELD         4
+#define STV090x_WIDTH_MCHIP_IDENT_FIELD         4
+#define STV090x_OFFST_MRELEASE_FIELD            0
+#define STV090x_WIDTH_MRELEASE_FIELD            4
+
+#define STV090x_DACR1                           0xf113
+#define STV090x_OFFST_DACR1_MODE_FIELD          5
+#define STV090x_WIDTH_DACR1_MODE_FIELD          3
+#define STV090x_OFFST_DACR1_VALUE_FIELD         0
+#define STV090x_WIDTH_DACR1_VALUE_FIELD         4
+
+#define STV090x_DACR2                           0xf114
+#define STV090x_OFFST_DACR2_VALUE_FIELD         0
+#define STV090x_WIDTH_DACR2_VALUE_FIELD         8
+
+#define STV090x_OUTCFG                          0xf11c
+#define STV090x_OFFST_OUTSERRS1_HZ_FIELD        6
+#define STV090x_WIDTH_OUTSERRS1_HZ_FIELD        1
+#define STV090x_OFFST_OUTSERRS2_HZ_FIELD        5
+#define STV090x_WIDTH_OUTSERRS2_HZ_FIELD        1
+#define STV090x_OFFST_OUTSERRS3_HZ_FIELD        4
+#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD        1
+#define STV090x_OFFST_OUTPARRS3_HZ_FIELD        3
+#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD        1
+
+#define STV090x_MODECFG                         0xf11d
+
+#define STV090x_IRQSTATUS3                      0xf120
+#define STV090x_OFFST_SPLL_LOCK_FIELD           5
+#define STV090x_WIDTH_SPLL_LOCK_FIELD           1
+#define STV090x_OFFST_SSTREAM_LCK_3_FIELD       4
+#define STV090x_WIDTH_SSTREAM_LCK_3_FIELD       1
+#define STV090x_OFFST_SSTREAM_LCK_2_FIELD       3
+#define STV090x_WIDTH_SSTREAM_LCK_2_FIELD       1
+#define STV090x_OFFST_SSTREAM_LCK_1_FIELD       2
+#define STV090x_WIDTH_SSTREAM_LCK_1_FIELD       1
+#define STV090x_OFFST_SDVBS1_PRF_2_FIELD        1
+#define STV090x_WIDTH_SDVBS1_PRF_2_FIELD        1
+#define STV090x_OFFST_SDVBS1_PRF_1_FIELD        0
+#define STV090x_WIDTH_SDVBS1_PRF_1_FIELD        1
+
+#define STV090x_IRQSTATUS2                      0xf121
+#define STV090x_OFFST_SSPY_ENDSIM_3_FIELD       7
+#define STV090x_WIDTH_SSPY_ENDSIM_3_FIELD       1
+#define STV090x_OFFST_SSPY_ENDSIM_2_FIELD       6
+#define STV090x_WIDTH_SSPY_ENDSIM_2_FIELD       1
+#define STV090x_OFFST_SSPY_ENDSIM_1_FIELD       5
+#define STV090x_WIDTH_SSPY_ENDSIM_1_FIELD       1
+#define STV090x_OFFST_SPKTDEL_ERROR_2_FIELD     4
+#define STV090x_WIDTH_SPKTDEL_ERROR_2_FIELD     1
+#define STV090x_OFFST_SPKTDEL_LOCKB_2_FIELD     3
+#define STV090x_WIDTH_SPKTDEL_LOCKB_2_FIELD     1
+#define STV090x_OFFST_SPKTDEL_LOCK_2_FIELD      2
+#define STV090x_WIDTH_SPKTDEL_LOCK_2_FIELD      1
+#define STV090x_OFFST_SPKTDEL_ERROR_1_FIELD     1
+#define STV090x_WIDTH_SPKTDEL_ERROR_1_FIELD     1
+#define STV090x_OFFST_SPKTDEL_LOCKB_1_FIELD     0
+#define STV090x_WIDTH_SPKTDEL_LOCKB_1_FIELD     1
+
+#define STV090x_IRQSTATUS1                      0xf122
+#define STV090x_OFFST_SPKTDEL_LOCK_1_FIELD      7
+#define STV090x_WIDTH_SPKTDEL_LOCK_1_FIELD      1
+#define STV090x_OFFST_SDEMOD_LOCKB_2_FIELD      2
+#define STV090x_WIDTH_SDEMOD_LOCKB_2_FIELD      1
+#define STV090x_OFFST_SDEMOD_LOCK_2_FIELD       1
+#define STV090x_WIDTH_SDEMOD_LOCK_2_FIELD       1
+#define STV090x_OFFST_SDEMOD_IRQ_2_FIELD        0
+#define STV090x_WIDTH_SDEMOD_IRQ_2_FIELD        1
+
+#define STV090x_IRQSTATUS0                      0xf123
+#define STV090x_OFFST_SDEMOD_LOCKB_1_FIELD      7
+#define STV090x_WIDTH_SDEMOD_LOCKB_1_FIELD      1
+#define STV090x_OFFST_SDEMOD_LOCK_1_FIELD       6
+#define STV090x_WIDTH_SDEMOD_LOCK_1_FIELD       1
+#define STV090x_OFFST_SDEMOD_IRQ_1_FIELD        5
+#define STV090x_WIDTH_SDEMOD_IRQ_1_FIELD        1
+#define STV090x_OFFST_SBCH_ERRFLAG_FIELD        4
+#define STV090x_WIDTH_SBCH_ERRFLAG_FIELD        1
+#define STV090x_OFFST_SDISEQC2RX_IRQ_FIELD      3
+#define STV090x_WIDTH_SDISEQC2RX_IRQ_FIELD      1
+#define STV090x_OFFST_SDISEQC2TX_IRQ_FIELD      2
+#define STV090x_WIDTH_SDISEQC2TX_IRQ_FIELD      1
+#define STV090x_OFFST_SDISEQC1RX_IRQ_FIELD      1
+#define STV090x_WIDTH_SDISEQC1RX_IRQ_FIELD      1
+#define STV090x_OFFST_SDISEQC1TX_IRQ_FIELD      0
+#define STV090x_WIDTH_SDISEQC1TX_IRQ_FIELD      1
+
+#define STV090x_IRQMASK3                        0xf124
+#define STV090x_OFFST_MPLL_LOCK_FIELD           5
+#define STV090x_WIDTH_MPLL_LOCK_FIELD           1
+#define STV090x_OFFST_MSTREAM_LCK_3_FIELD       2
+#define STV090x_WIDTH_MSTREAM_LCK_3_FIELD       3
+#define STV090x_OFFST_MSTREAM_LCK_2_FIELD       2
+#define STV090x_WIDTH_MSTREAM_LCK_2_FIELD       3
+#define STV090x_OFFST_MSTREAM_LCK_1_FIELD       2
+#define STV090x_WIDTH_MSTREAM_LCK_1_FIELD       3
+#define STV090x_OFFST_MDVBS1_PRF_2_FIELD        1
+#define STV090x_WIDTH_MDVBS1_PRF_2_FIELD        1
+#define STV090x_OFFST_MDVBS1_PRF_1_FIELD        0
+#define STV090x_WIDTH_MDVBS1_PRF_1_FIELD        1
+
+#define STV090x_IRQMASK2                        0xf125
+#define STV090x_OFFST_MSPY_ENDSIM_3_FIELD       5
+#define STV090x_WIDTH_MSPY_ENDSIM_3_FIELD       3
+#define STV090x_OFFST_MSPY_ENDSIM_2_FIELD       5
+#define STV090x_WIDTH_MSPY_ENDSIM_2_FIELD       3
+#define STV090x_OFFST_MSPY_ENDSIM_1_FIELD       5
+#define STV090x_WIDTH_MSPY_ENDSIM_1_FIELD       3
+#define STV090x_OFFST_MPKTDEL_ERROR_2_FIELD     4
+#define STV090x_WIDTH_MPKTDEL_ERROR_2_FIELD     1
+#define STV090x_OFFST_MPKTDEL_LOCKB_2_FIELD     3
+#define STV090x_WIDTH_MPKTDEL_LOCKB_2_FIELD     1
+#define STV090x_OFFST_MPKTDEL_LOCK_2_FIELD      2
+#define STV090x_WIDTH_MPKTDEL_LOCK_2_FIELD      1
+#define STV090x_OFFST_MPKTDEL_ERROR_1_FIELD     1
+#define STV090x_WIDTH_MPKTDEL_ERROR_1_FIELD     1
+#define STV090x_OFFST_MPKTDEL_LOCKB_1_FIELD     0
+#define STV090x_WIDTH_MPKTDEL_LOCKB_1_FIELD     1
+
+#define STV090x_IRQMASK1                        0xf126
+#define STV090x_OFFST_MPKTDEL_LOCK_1_FIELD      7
+#define STV090x_WIDTH_MPKTDEL_LOCK_1_FIELD      1
+#define STV090x_OFFST_MEXTPINB2_FIELD           6
+#define STV090x_WIDTH_MEXTPINB2_FIELD           1
+#define STV090x_OFFST_MEXTPIN2_FIELD            5
+#define STV090x_WIDTH_MEXTPIN2_FIELD            1
+#define STV090x_OFFST_MEXTPINB1_FIELD           4
+#define STV090x_WIDTH_MEXTPINB1_FIELD           1
+#define STV090x_OFFST_MEXTPIN1_FIELD            3
+#define STV090x_WIDTH_MEXTPIN1_FIELD            1
+#define STV090x_OFFST_MDEMOD_LOCKB_2_FIELD      2
+#define STV090x_WIDTH_MDEMOD_LOCKB_2_FIELD      1
+#define STV090x_OFFST_MDEMOD_LOCK_2_FIELD       1
+#define STV090x_WIDTH_MDEMOD_LOCK_2_FIELD       1
+#define STV090x_OFFST_MDEMOD_IRQ_2_FIELD        0
+#define STV090x_WIDTH_MDEMOD_IRQ_2_FIELD        1
+
+#define STV090x_IRQMASK0                        0xf127
+#define STV090x_OFFST_MDEMOD_LOCKB_1_FIELD      7
+#define STV090x_WIDTH_MDEMOD_LOCKB_1_FIELD      1
+#define STV090x_OFFST_MDEMOD_LOCK_1_FIELD       6
+#define STV090x_WIDTH_MDEMOD_LOCK_1_FIELD       1
+#define STV090x_OFFST_MDEMOD_IRQ_1_FIELD        5
+#define STV090x_WIDTH_MDEMOD_IRQ_1_FIELD        1
+#define STV090x_OFFST_MBCH_ERRFLAG_FIELD        4
+#define STV090x_WIDTH_MBCH_ERRFLAG_FIELD        1
+#define STV090x_OFFST_MDISEQC2RX_IRQ_FIELD      3
+#define STV090x_WIDTH_MDISEQC2RX_IRQ_FIELD      1
+#define STV090x_OFFST_MDISEQC2TX_IRQ_FIELD      2
+#define STV090x_WIDTH_MDISEQC2TX_IRQ_FIELD      1
+#define STV090x_OFFST_MDISEQC1RX_IRQ_FIELD      1
+#define STV090x_WIDTH_MDISEQC1RX_IRQ_FIELD      1
+#define STV090x_OFFST_MDISEQC1TX_IRQ_FIELD      0
+#define STV090x_WIDTH_MDISEQC1TX_IRQ_FIELD      1
+
+#define STV090x_I2CCFG                          0xf129
+#define STV090x_OFFST_12C_FASTMODE_FIELD        3
+#define STV090x_WIDTH_12C_FASTMODE_FIELD        1
+#define STV090x_OFFST_12CADDR_INC_FIELD         0
+#define STV090x_WIDTH_12CADDR_INC_FIELD         2
+
+#define STV090x_Px_I2CRPT(__x)                  (0xf12a + (__x - 1) * 0x1)
+#define STV090x_P1_I2CRPT                       STV090x_Px_I2CRPT(1)
+#define STV090x_P2_I2CRPT                       STV090x_Px_I2CRPT(2)
+#define STV090x_OFFST_Px_I2CT_ON_FIELD          7
+#define STV090x_WIDTH_Px_I2CT_ON_FIELD          1
+#define STV090x_OFFST_Px_ENARPT_LEVEL_FIELD     4
+#define STV090x_WIDTH_Px_ENARPT_LEVEL_FIELD     3
+#define STV090x_OFFST_Px_SCLT_DELAY_FIELD       3
+#define STV090x_WIDTH_Px_SCLT_DELAY_FIELD       1
+#define STV090x_OFFST_Px_STOP_ENABLE_FIELD      2
+#define STV090x_WIDTH_Px_STOP_ENABLE_FIELD      1
+#define STV090x_OFFST_Px_STOP_SDAT2SDA_FIELD    1
+#define STV090x_WIDTH_Px_STOP_SDAT2SDA_FIELD    1
+
+#define STV090x_CLKI2CFG                        0xf140
+#define STV090x_OFFST_CLKI2_OPD_FIELD           7
+#define STV090x_WIDTH_CLKI2_OPD_FIELD           1
+#define STV090x_OFFST_CLKI2_CONFIG_FIELD        1
+#define STV090x_WIDTH_CLKI2_CONFIG_FIELD        6
+#define STV090x_OFFST_CLKI2_XOR_FIELD           0
+#define STV090x_WIDTH_CLKI2_XOR_FIELD           1
+
+#define STV090x_GPIOxCFG(__x)                   (0xf141 + (__x - 1))
+#define STV090x_GPIO1CFG                        STV090x_GPIOxCFG(1)
+#define STV090x_GPIO2CFG                        STV090x_GPIOxCFG(2)
+#define STV090x_GPIO3CFG                        STV090x_GPIOxCFG(3)
+#define STV090x_GPIO4CFG                        STV090x_GPIOxCFG(4)
+#define STV090x_GPIO5CFG                        STV090x_GPIOxCFG(5)
+#define STV090x_GPIO6CFG                        STV090x_GPIOxCFG(6)
+#define STV090x_GPIO7CFG                        STV090x_GPIOxCFG(7)
+#define STV090x_GPIO8CFG                        STV090x_GPIOxCFG(8)
+#define STV090x_GPIO9CFG                        STV090x_GPIOxCFG(9)
+#define STV090x_GPIO10CFG                       STV090x_GPIOxCFG(10)
+#define STV090x_GPIO11CFG                       STV090x_GPIOxCFG(11)
+#define STV090x_GPIO12CFG                       STV090x_GPIOxCFG(12)
+#define STV090x_GPIO13CFG                       STV090x_GPIOxCFG(13)
+#define STV090x_OFFST_GPIOx_OPD_FIELD           7
+#define STV090x_WIDTH_GPIOx_OPD_FIELD           1
+#define STV090x_OFFST_GPIOx_CONFIG_FIELD        1
+#define STV090x_WIDTH_GPIOx_CONFIG_FIELD        6
+#define STV090x_OFFST_GPIOx_XOR_FIELD           0
+#define STV090x_WIDTH_GPIOx_XOR_FIELD           1
+
+#define STV090x_CSxCFG(__x)                     (0xf14e + __x * 0x1)
+#define STV090x_CS0CFG                          STV090x_CSxCFG(0)
+#define STV090x_CS1CFG                          STV090x_CSxCFG(1)
+#define STV090x_OFFST_CSX_OPD_FIELD             7
+#define STV090x_WIDTH_CSX_OPD_FIELD             1
+#define STV090x_OFFST_CSX_CONFIG_FIELD          1
+#define STV090x_WIDTH_CSX_CONFIG_FIELD          6
+#define STV090x_OFFST_CSX_XOR_FIELD             0
+#define STV090x_WIDTH_CSX_XOR_FIELD             1
+
+
+#define STV090x_STDBYCFG                        0xf150
+#define STV090x_OFFST_STDBY_OPD_FIELD           7
+#define STV090x_WIDTH_STDBY_OPD_FIELD           1
+#define STV090x_OFFST_STDBY_CONFIG_FIELD        1
+#define STV090x_WIDTH_STDBY_CONFIG_FIELD        6
+#define STV090x_OFFST_STDBY_XOR_FIELD           0
+#define STV090x_WIDTH_STDBY_XOR_FIELD           1
+
+#define STV090x_DIRCLKCFG                       0xf151
+#define STV090x_OFFST_DIRCLK_OPD_FIELD          7
+#define STV090x_WIDTH_DIRCLK_OPD_FIELD          1
+#define STV090x_OFFST_DIRCLK_CONFIG_FIELD       1
+#define STV090x_WIDTH_DIRCLK_CONFIG_FIELD       6
+#define STV090x_OFFST_DIRCLK_XOR_FIELD          0
+#define STV090x_WIDTH_DIRCLK_XOR_FIELD          1
+
+
+#define STV090x_AGCRFxCFG(__x)                  (0xf152 + (__x - 1) * 0x4)
+#define STV090x_AGCRF1CFG                       STV090x_AGCRFxCFG(1)
+#define STV090x_AGCRF2CFG                       STV090x_AGCRFxCFG(2)
+#define STV090x_OFFST_AGCRFx_OPD_FIELD          7
+#define STV090x_WIDTH_AGCRFx_OPD_FIELD          1
+#define STV090x_OFFST_AGCRFx_CONFIG_FIELD       1
+#define STV090x_WIDTH_AGCRFx_CONFIG_FIELD       6
+#define STV090x_OFFST_AGCRFx_XOR_FIELD          0
+#define STV090x_WIDTH_AGCRFx_XOR_FIELD          1
+
+#define STV090x_SDATxCFG(__x)                   (0xf153 + (__x - 1) * 0x4)
+#define STV090x_SDAT1CFG                        STV090x_SDATxCFG(1)
+#define STV090x_SDAT2CFG                        STV090x_SDATxCFG(2)
+#define STV090x_OFFST_SDATx_OPD_FIELD           7
+#define STV090x_WIDTH_SDATx_OPD_FIELD           1
+#define STV090x_OFFST_SDATx_CONFIG_FIELD        1
+#define STV090x_WIDTH_SDATx_CONFIG_FIELD        6
+#define STV090x_OFFST_SDATx_XOR_FIELD           0
+#define STV090x_WIDTH_SDATx_XOR_FIELD           1
+
+#define STV090x_SCLTxCFG(__x)                   (0xf154 + (__x - 1) * 0x4)
+#define STV090x_SCLT1CFG                        STV090x_SCLTxCFG(1)
+#define STV090x_SCLT2CFG                        STV090x_SCLTxCFG(2)
+#define STV090x_OFFST_SCLTx_OPD_FIELD           7
+#define STV090x_WIDTH_SCLTx_OPD_FIELD           1
+#define STV090x_OFFST_SCLTx_CONFIG_FIELD        1
+#define STV090x_WIDTH_SCLTx_CONFIG_FIELD        6
+#define STV090x_OFFST_SCLTx_XOR_FIELD           0
+#define STV090x_WIDTH_SCLTx_XOR_FIELD           1
+
+#define STV090x_DISEQCOxCFG(__x)                (0xf155 + (__x - 1) * 0x4)
+#define STV090x_DISEQCO1CFG                     STV090x_DISEQCOxCFG(1)
+#define STV090x_DISEQCO2CFG                     STV090x_DISEQCOxCFG(2)
+#define STV090x_OFFST_DISEQCOx_OPD_FIELD        7
+#define STV090x_WIDTH_DISEQCOx_OPD_FIELD        1
+#define STV090x_OFFST_DISEQCOx_CONFIG_FIELD     1
+#define STV090x_WIDTH_DISEQCOx_CONFIG_FIELD     6
+#define STV090x_OFFST_DISEQCOx_XOR_FIELD        0
+#define STV090x_WIDTH_DISEQCOx_XOR_FIELD        1
+
+#define STV090x_CLKOUT27CFG                     0xf15a
+#define STV090x_OFFST_CLKOUT27_OPD_FIELD        7
+#define STV090x_WIDTH_CLKOUT27_OPD_FIELD        1
+#define STV090x_OFFST_CLKOUT27_CONFIG_FIELD     1
+#define STV090x_WIDTH_CLKOUT27_CONFIG_FIELD     6
+#define STV090x_OFFST_CLKOUT27_XOR_FIELD        0
+#define STV090x_WIDTH_CLKOUT27_XOR_FIELD        1
+
+#define STV090x_ERRORxCFG(__x)                  (0xf15b + (__x - 1) * 0x5)
+#define STV090x_ERROR1CFG                       STV090x_ERRORxCFG(1)
+#define STV090x_ERROR2CFG                       STV090x_ERRORxCFG(2)
+#define STV090x_ERROR3CFG                       STV090x_ERRORxCFG(3)
+#define STV090x_OFFST_ERRORx_OPD_FIELD          7
+#define STV090x_WIDTH_ERRORx_OPD_FIELD          1
+#define STV090x_OFFST_ERRORx_CONFIG_FIELD       1
+#define STV090x_WIDTH_ERRORx_CONFIG_FIELD       6
+#define STV090x_OFFST_ERRORx_XOR_FIELD          0
+#define STV090x_WIDTH_ERRORx_XOR_FIELD          1
+
+#define STV090x_DPNxCFG(__x)                    (0xf15c + (__x - 1) * 0x5)
+#define STV090x_DPN1CFG                         STV090x_DPNxCFG(1)
+#define STV090x_DPN2CFG                         STV090x_DPNxCFG(2)
+#define STV090x_DPN3CFG                         STV090x_DPNxCFG(3)
+#define STV090x_OFFST_DPNx_OPD_FIELD            7
+#define STV090x_WIDTH_DPNx_OPD_FIELD            1
+#define STV090x_OFFST_DPNx_CONFIG_FIELD         1
+#define STV090x_WIDTH_DPNx_CONFIG_FIELD         6
+#define STV090x_OFFST_DPNx_XOR_FIELD            0
+#define STV090x_WIDTH_DPNx_XOR_FIELD            1
+
+#define STV090x_STROUTxCFG(__x)                 (0xf15d + (__x - 1) * 0x5)
+#define STV090x_STROUT1CFG                      STV090x_STROUTxCFG(1)
+#define STV090x_STROUT2CFG                      STV090x_STROUTxCFG(2)
+#define STV090x_STROUT3CFG                      STV090x_STROUTxCFG(3)
+#define STV090x_OFFST_STROUTx_OPD_FIELD         7
+#define STV090x_WIDTH_STROUTx_OPD_FIELD         1
+#define STV090x_OFFST_STROUTx_CONFIG_FIELD      1
+#define STV090x_WIDTH_STROUTx_CONFIG_FIELD      6
+#define STV090x_OFFST_STROUTx_XOR_FIELD         0
+#define STV090x_WIDTH_STROUTx_XOR_FIELD         1
+
+#define STV090x_CLKOUTxCFG(__x)                 (0xf15e + (__x - 1) * 0x5)
+#define STV090x_CLKOUT1CFG                      STV090x_CLKOUTxCFG(1)
+#define STV090x_CLKOUT2CFG                      STV090x_CLKOUTxCFG(2)
+#define STV090x_CLKOUT3CFG                      STV090x_CLKOUTxCFG(3)
+#define STV090x_OFFST_CLKOUTx_OPD_FIELD         7
+#define STV090x_WIDTH_CLKOUTx_OPD_FIELD         1
+#define STV090x_OFFST_CLKOUTx_CONFIG_FIELD      1
+#define STV090x_WIDTH_CLKOUTx_CONFIG_FIELD      6
+#define STV090x_OFFST_CLKOUTx_XOR_FIELD         0
+#define STV090x_WIDTH_CLKOUTx_XOR_FIELD         1
+
+#define STV090x_DATAxCFG(__x)                   (0xf15f + (__x - 71) * 0x5)
+#define STV090x_DATA71CFG                       STV090x_DATAxCFG(71)
+#define STV090x_DATA72CFG                       STV090x_DATAxCFG(72)
+#define STV090x_DATA73CFG                       STV090x_DATAxCFG(73)
+#define STV090x_OFFST_DATAx_OPD_FIELD           7
+#define STV090x_WIDTH_DATAx_OPD_FIELD           1
+#define STV090x_OFFST_DATAx_CONFIG_FIELD        1
+#define STV090x_WIDTH_DATAx_CONFIG_FIELD        6
+#define STV090x_OFFST_DATAx_XOR_FIELD           0
+#define STV090x_WIDTH_DATAx_XOR_FIELD           1
+
+#define STV090x_NCOARSE                         0xf1b3
+#define STV090x_OFFST_M_DIV_FIELD               0
+#define STV090x_WIDTH_M_DIV_FIELD               8
+
+#define STV090x_SYNTCTRL                        0xf1b6
+#define STV090x_OFFST_STANDBY_FIELD             7
+#define STV090x_WIDTH_STANDBY_FIELD             1
+#define STV090x_OFFST_BYPASSPLLCORE_FIELD       6
+#define STV090x_WIDTH_BYPASSPLLCORE_FIELD       1
+#define STV090x_OFFST_SELX1RATIO_FIELD          5
+#define STV090x_WIDTH_SELX1RATIO_FIELD          1
+#define STV090x_OFFST_STOP_PLL_FIELD            3
+#define STV090x_WIDTH_SELX1RATIO_FIELD          1
+#define STV090x_OFFST_BYPASSPLLFSK_FIELD        2
+#define STV090x_WIDTH_BYPASSPLLFSK_FIELD        1
+#define STV090x_OFFST_SELOSCI_FIELD             1
+#define STV090x_WIDTH_SELOSCI_FIELD             1
+#define STV090x_OFFST_BYPASSPLLADC_FIELD        0
+#define STV090x_WIDTH_BYPASSPLLADC_FIELD        1
+
+#define STV090x_FILTCTRL                        0xf1b7
+#define STV090x_OFFST_INV_CLK135_FIELD          7
+#define STV090x_WIDTH_INV_CLK135_FIELD          1
+#define STV090x_OFFST_SEL_FSKCKDIV_FIELD        2
+#define STV090x_WIDTH_SEL_FSKCKDIV_FIELD        1
+#define STV090x_OFFST_INV_CLKFSK_FIELD          1
+#define STV090x_WIDTH_INV_CLKFSK_FIELD          1
+#define STV090x_OFFST_BYPASS_APPLI_FIELD        0
+#define STV090x_WIDTH_BYPASS_APPLI_FIELD        1
+
+#define STV090x_PLLSTAT                         0xf1b8
+#define STV090x_OFFST_PLLLOCK_FIELD             0
+#define STV090x_WIDTH_PLLLOCK_FIELD             1
+
+#define STV090x_STOPCLK1                        0xf1c2
+#define STV090x_OFFST_STOP_CLKPKDT2_FIELD       6
+#define STV090x_WIDTH_STOP_CLKPKDT2_FIELD       1
+#define STV090x_OFFST_STOP_CLKPKDT1_FIELD       5
+#define STV090x_WIDTH_STOP_CLKPKDT1_FIELD       1
+#define STV090x_OFFST_STOP_CLKFEC_FIELD         4
+#define STV090x_WIDTH_STOP_CLKFEC_FIELD         1
+#define STV090x_OFFST_STOP_CLKADCI2_FIELD       3
+#define STV090x_WIDTH_STOP_CLKADCI2_FIELD       1
+#define STV090x_OFFST_INV_CLKADCI2_FIELD        2
+#define STV090x_WIDTH_INV_CLKADCI2_FIELD        1
+#define STV090x_OFFST_STOP_CLKADCI1_FIELD       1
+#define STV090x_WIDTH_STOP_CLKADCI1_FIELD       1
+#define STV090x_OFFST_INV_CLKADCI1_FIELD        0
+#define STV090x_WIDTH_INV_CLKADCI1_FIELD        1
+
+#define STV090x_STOPCLK2                        0xf1c3
+#define STV090x_OFFST_STOP_CLKSAMP2_FIELD       4
+#define STV090x_WIDTH_STOP_CLKSAMP2_FIELD       1
+#define STV090x_OFFST_STOP_CLKSAMP1_FIELD       3
+#define STV090x_WIDTH_STOP_CLKSAMP1_FIELD       1
+#define STV090x_OFFST_STOP_CLKVIT2_FIELD        2
+#define STV090x_WIDTH_STOP_CLKVIT2_FIELD        1
+#define STV090x_OFFST_STOP_CLKVIT1_FIELD        1
+#define STV090x_WIDTH_STOP_CLKVIT1_FIELD        1
+#define STV090x_OFFST_STOP_CLKTS_FIELD          0
+#define STV090x_WIDTH_STOP_CLKTS_FIELD          1
+
+#define STV090x_TSTTNR0                         0xf1df
+#define STV090x_OFFST_SEL_FSK_FIELD             7
+#define STV090x_WIDTH_SEL_FSK_FIELD             1
+#define STV090x_OFFST_FSK_PON_FIELD             2
+#define STV090x_WIDTH_FSK_PON_FIELD             1
+
+#define STV090x_TSTTNR1                         0xf1e0
+#define STV090x_OFFST_ADC1_PON_FIELD            1
+#define STV090x_WIDTH_ADC1_PON_FIELD            1
+#define STV090x_OFFST_ADC1_INMODE_FIELD         0
+#define STV090x_WIDTH_ADC1_INMODE_FIELD         1
+
+#define STV090x_TSTTNR2                         0xf1e1
+#define STV090x_OFFST_DISEQC1_PON_FIELD         5
+#define STV090x_WIDTH_DISEQC1_PON_FIELD         1
+
+#define STV090x_TSTTNR3                         0xf1e2
+#define STV090x_OFFST_ADC2_PON_FIELD            1
+#define STV090x_WIDTH_ADC2_PON_FIELD            1
+#define STV090x_OFFST_ADC2_INMODE_FIELD         0
+#define STV090x_WIDTH_ADC2_INMODE_FIELD         1
+
+#define STV090x_TSTTNR4                         0xf1e3
+#define STV090x_OFFST_DISEQC2_PON_FIELD         5
+#define STV090x_WIDTH_DISEQC2_PON_FIELD         1
+
+#define STV090x_FSKTFC2                         0xf170
+#define STV090x_OFFST_FSKT_KMOD_FIELD           2
+#define STV090x_WIDTH_FSKT_KMOD_FIELD           6
+#define STV090x_OFFST_FSKT_CAR_FIELD            0
+#define STV090x_WIDTH_FSKT_CAR_FIELD            2
+
+#define STV090x_FSKTFC1                         0xf171
+#define STV090x_OFFST_FSKTC1_CAR_FIELD          0
+#define STV090x_WIDTH_FSKTC1_CAR_FIELD          8
+
+#define STV090x_FSKTFC0                         0xf172
+#define STV090x_OFFST_FSKTC0_CAR_FIELD          0
+#define STV090x_WIDTH_FSKTC0_CAR_FIELD          8
+
+#define STV090x_FSKTDELTAF1                     0xf173
+#define STV090x_OFFST_FSKTF1_DELTAF_FIELD       0
+#define STV090x_WIDTH_FSKTF1_DELTAF_FIELD       4
+
+#define STV090x_FSKTDELTAF0                     0xf174
+#define STV090x_OFFST_FSKTF0_DELTAF_FIELD       0
+#define STV090x_WIDTH_FSKTF0_DELTAF_FIELD       8
+
+#define STV090x_FSKTCTRL                        0xf175
+#define STV090x_OFFST_FSKT_EN_SGN_FIELD         6
+#define STV090x_WIDTH_FSKT_EN_SGN_FIELD         1
+#define STV090x_OFFST_FSKT_MOD_SGN_FIELD        5
+#define STV090x_WIDTH_FSKT_MOD_SGN_FIELD        1
+#define STV090x_OFFST_FSKT_MOD_EN_FIELD         2
+#define STV090x_WIDTH_FSKT_MOD_EN_FIELD         3
+#define STV090x_OFFST_FSKT_DACMODE_FIELD        0
+#define STV090x_WIDTH_FSKT_DACMODE_FIELD        2
+
+#define STV090x_FSKRFC2                         0xf176
+#define STV090x_OFFST_FSKRC2_DETSGN_FIELD       6
+#define STV090x_WIDTH_FSKRC2_DETSGN_FIELD       1
+#define STV090x_OFFST_FSKRC2_OUTSGN_FIELD       5
+#define STV090x_WIDTH_FSKRC2_OUTSGN_FIELD       1
+#define STV090x_OFFST_FSKRC2_KAGC_FIELD         2
+#define STV090x_WIDTH_FSKRC2_KAGC_FIELD         3
+#define STV090x_OFFST_FSKRC2_CAR_FIELD          0
+#define STV090x_WIDTH_FSKRC2_CAR_FIELD          2
+
+#define STV090x_FSKRFC1                         0xf177
+#define STV090x_OFFST_FSKRC1_CAR_FIELD          0
+#define STV090x_WIDTH_FSKRC1_CAR_FIELD          8
+
+#define STV090x_FSKRFC0                         0xf178
+#define STV090x_OFFST_FSKRC0_CAR_FIELD          0
+#define STV090x_WIDTH_FSKRC0_CAR_FIELD          8
+
+#define STV090x_FSKRK1                          0xf179
+#define STV090x_OFFST_FSKR_K1_EXP_FIELD         5
+#define STV090x_WIDTH_FSKR_K1_EXP_FIELD         3
+#define STV090x_OFFST_FSKR_K1_MANT_FIELD        0
+#define STV090x_WIDTH_FSKR_K1_MANT_FIELD        5
+
+#define STV090x_FSKRK2                          0xf17a
+#define STV090x_OFFST_FSKR_K2_EXP_FIELD         5
+#define STV090x_WIDTH_FSKR_K2_EXP_FIELD         3
+#define STV090x_OFFST_FSKR_K2_MANT_FIELD        0
+#define STV090x_WIDTH_FSKR_K2_MANT_FIELD        5
+
+#define STV090x_FSKRAGCR                        0xf17b
+#define STV090x_OFFST_FSKR_OUTCTL_FIELD         6
+#define STV090x_WIDTH_FSKR_OUTCTL_FIELD         2
+#define STV090x_OFFST_FSKR_AGC_REF_FIELD        0
+#define STV090x_WIDTH_FSKR_AGC_REF_FIELD        6
+
+#define STV090x_FSKRAGC                         0xf17c
+#define STV090x_OFFST_FSKR_AGC_ACCU_FIELD       0
+#define STV090x_WIDTH_FSKR_AGC_ACCU_FIELD       8
+
+#define STV090x_FSKRALPHA                       0xf17d
+#define STV090x_OFFST_FSKR_ALPHA_EXP_FIELD      2
+#define STV090x_WIDTH_FSKR_ALPHA_EXP_FIELD      3
+#define STV090x_OFFST_FSKR_ALPHA_M_FIELD        0
+#define STV090x_WIDTH_FSKR_ALPHA_M_FIELD        2
+
+#define STV090x_FSKRPLTH1                       0xf17e
+#define STV090x_OFFST_FSKR_BETA_FIELD           4
+#define STV090x_WIDTH_FSKR_BETA_FIELD           4
+#define STV090x_OFFST_FSKR_PLL_TRESH1_FIELD     0
+#define STV090x_WIDTH_FSKR_PLL_TRESH1_FIELD     4
+
+#define STV090x_FSKRPLTH0                       0xf17f
+#define STV090x_OFFST_FSKR_PLL_TRESH0_FIELD     0
+#define STV090x_WIDTH_FSKR_PLL_TRESH0_FIELD     8
+
+#define STV090x_FSKRDF1                         0xf180
+#define STV090x_OFFST_FSKR_DELTAF1_FIELD        0
+#define STV090x_WIDTH_FSKR_DELTAF1_FIELD        5
+
+#define STV090x_FSKRDF0                         0xf181
+#define STV090x_OFFST_FSKR_DELTAF0_FIELD        0
+#define STV090x_WIDTH_FSKR_DELTAF0_FIELD        8
+
+#define STV090x_FSKRSTEPP                       0xf182
+#define STV090x_OFFST_FSKR_STEP_PLUS_FIELD      0
+#define STV090x_WIDTH_FSKR_STEP_PLUS_FIELD      8
+
+#define STV090x_FSKRSTEPM                       0xf183
+#define STV090x_OFFST_FSKR_STEP_MINUS_FIELD     0
+#define STV090x_WIDTH_FSKR_STEP_MINUS_FIELD     8
+
+#define STV090x_FSKRDET1                        0xf184
+#define STV090x_OFFST_FSKR_CARDET1_ACCU_FIELD   0
+#define STV090x_WIDTH_FSKR_CARDET1_ACCU_FIELD   4
+
+#define STV090x_FSKRDET0                        0xf185
+#define STV090x_OFFST_FSKR_CARDET0_ACCU_FIELD   0
+#define STV090x_WIDTH_FSKR_CARDET0_ACCU_FIELD   8
+
+#define STV090x_FSKRDTH1                                0xf186
+#define STV090x_OFFST_FSKR_CARLOSS_THRESH1_FIELD        4
+#define STV090x_WIDTH_FSKR_CARLOSS_THRESH1_FIELD        4
+#define STV090x_OFFST_FSKR_CARDET_THRESH1_FIELD         0
+#define STV090x_WIDTH_FSKR_CARDET_THRESH1_FIELD         4
+
+#define STV090x_FSKRDTH0                        0xf187
+#define STV090x_OFFST_FSKR_CARDET_THRESH0_FIELD 0
+#define STV090x_WIDTH_FSKR_CARDET_THRESH0_FIELD 8
+
+#define STV090x_FSKRLOSS                        0xf188
+#define STV090x_OFFST_FSKR_CARLOSS_THRESH_FIELD 0
+#define STV090x_WIDTH_FSKR_CARLOSS_THRESH_FIELD 8
+
+#define STV090x_Px_DISTXCTL(__x)                (0xF1A0 - (__x - 1) * 0x10)
+#define STV090x_P1_DISTXCTL                     STV090x_Px_DISTXCTL(1)
+#define STV090x_P2_DISTXCTL                     STV090x_Px_DISTXCTL(2)
+#define STV090x_OFFST_Px_TIM_OFF_FIELD          7
+#define STV090x_WIDTH_Px_TIM_OFF_FIELD          1
+#define STV090x_OFFST_Px_DISEQC_RESET_FIELD     6
+#define STV090x_WIDTH_Px_DISEQC_RESET_FIELD     1
+#define STV090x_OFFST_Px_TIM_CMD_FIELD          4
+#define STV090x_WIDTH_Px_TIM_CMD_FIELD          2
+#define STV090x_OFFST_Px_DIS_PRECHARGE_FIELD    3
+#define STV090x_WIDTH_Px_DIS_PRECHARGE_FIELD    1
+#define STV090x_OFFST_Px_DISTX_MODE_FIELD       0
+#define STV090x_WIDTH_Px_DISTX_MODE_FIELD       3
+
+#define STV090x_Px_DISRXCTL(__x)                (0xf1a1 - (__x - 1) * 0x10)
+#define STV090x_P1_DISRXCTL                     STV090x_Px_DISRXCTL(1)
+#define STV090x_P2_DISRXCTL                     STV090x_Px_DISRXCTL(2)
+#define STV090x_OFFST_Px_RECEIVER_ON_FIELD      7
+#define STV090x_WIDTH_Px_RECEIVER_ON_FIELD      1
+#define STV090x_OFFST_Px_IGNO_SHORT22K_FIELD    6
+#define STV090x_WIDTH_Px_IGNO_SHORT22K_FIELD    1
+#define STV090x_OFFST_Px_ONECHIP_TRX_FIELD      5
+#define STV090x_WIDTH_Px_ONECHIP_TRX_FIELD      1
+#define STV090x_OFFST_Px_EXT_ENVELOP_FIELD      4
+#define STV090x_WIDTH_Px_EXT_ENVELOP_FIELD      1
+#define STV090x_OFFST_Px_PIN_SELECT_FIELD       2
+#define STV090x_WIDTH_Px_PIN_SELECT_FIELD       2
+#define STV090x_OFFST_Px_IRQ_RXEND_FIELD        1
+#define STV090x_WIDTH_Px_IRQ_RXEND_FIELD        1
+#define STV090x_OFFST_Px_IRQ_4NBYTES_FIELD      0
+#define STV090x_WIDTH_Px_IRQ_4NBYTES_FIELD      1
+
+#define STV090x_Px_DISRX_ST0(__x)               (0xf1a4 - (__x - 1) * 0x10)
+#define STV090x_P1_DISRX_ST0                    STV090x_Px_DISRX_ST0(1)
+#define STV090x_P2_DISRX_ST0                    STV090x_Px_DISRX_ST0(2)
+#define STV090x_OFFST_Px_RX_END_FIELD           7
+#define STV090x_WIDTH_Px_RX_END_FIELD           1
+#define STV090x_OFFST_Px_RX_ACTIVE_FIELD        6
+#define STV090x_WIDTH_Px_RX_ACTIVE_FIELD        1
+#define STV090x_OFFST_Px_SHORT_22KHZ_FIELD      5
+#define STV090x_WIDTH_Px_SHORT_22KHZ_FIELD      1
+#define STV090x_OFFST_Px_CONT_TONE_FIELD        4
+#define STV090x_WIDTH_Px_CONT_TONE_FIELD        1
+#define STV090x_OFFST_Px_FIFO_4BREADY_FIELD     3
+#define STV090x_WIDTH_Px_FIFO_4BREADY_FIELD     2
+#define STV090x_OFFST_Px_FIFO_EMPTY_FIELD       2
+#define STV090x_WIDTH_Px_FIFO_EMPTY_FIELD       1
+#define STV090x_OFFST_Px_ABORT_DISRX_FIELD      0
+#define STV090x_WIDTH_Px_ABORT_DISRX_FIELD      1
+
+#define STV090x_Px_DISRX_ST1(__x)               (0xf1a5 - (__x - 1) * 0x10)
+#define STV090x_P1_DISRX_ST1                    STV090x_Px_DISRX_ST1(1)
+#define STV090x_P2_DISRX_ST1                    STV090x_Px_DISRX_ST1(2)
+#define STV090x_OFFST_Px_RX_FAIL_FIELD          7
+#define STV090x_WIDTH_Px_RX_FAIL_FIELD          1
+#define STV090x_OFFST_Px_FIFO_PARITYFAIL_FIELD  6
+#define STV090x_WIDTH_Px_FIFO_PARITYFAIL_FIELD  1
+#define STV090x_OFFST_Px_RX_NONBYTE_FIELD       5
+#define STV090x_WIDTH_Px_RX_NONBYTE_FIELD       1
+#define STV090x_OFFST_Px_FIFO_OVERFLOW_FIELD    4
+#define STV090x_WIDTH_Px_FIFO_OVERFLOW_FIELD    1
+#define STV090x_OFFST_Px_FIFO_BYTENBR_FIELD     0
+#define STV090x_WIDTH_Px_FIFO_BYTENBR_FIELD     4
+
+#define STV090x_Px_DISRXDATA(__x)               (0xf1a6 - (__x - 1) * 0x10)
+#define STV090x_P1_DISRXDATA                    STV090x_Px_DISRXDATA(1)
+#define STV090x_P2_DISRXDATA                    STV090x_Px_DISRXDATA(2)
+#define STV090x_OFFST_Px_DISRX_DATA_FIELD       0
+#define STV090x_WIDTH_Px_DISRX_DATA_FIELD       8
+
+#define STV090x_Px_DISTXDATA(__x)               (0xf1a7 - (__x - 1) * 0x10)
+#define STV090x_P1_DISTXDATA                    STV090x_Px_DISTXDATA(1)
+#define STV090x_P2_DISTXDATA                    STV090x_Px_DISTXDATA(2)
+#define STV090x_OFFST_Px_DISEQC_FIFO_FIELD      0
+#define STV090x_WIDTH_Px_DISEQC_FIFO_FIELD      8
+
+#define STV090x_Px_DISTXSTATUS(__x)             (0xf1a8 - (__x - 1) * 0x10)
+#define STV090x_P1_DISTXSTATUS                  STV090x_Px_DISTXSTATUS(1)
+#define STV090x_P2_DISTXSTATUS                  STV090x_Px_DISTXSTATUS(2)
+#define STV090x_OFFST_Px_TX_FAIL_FIELD          7
+#define STV090x_WIDTH_Px_TX_FAIL_FIELD          1
+#define STV090x_OFFST_Px_FIFO_FULL_FIELD        6
+#define STV090x_WIDTH_Px_FIFO_FULL_FIELD        1
+#define STV090x_OFFST_Px_TX_IDLE_FIELD          5
+#define STV090x_WIDTH_Px_TX_IDLE_FIELD          1
+#define STV090x_OFFST_Px_GAP_BURST_FIELD        4
+#define STV090x_WIDTH_Px_GAP_BURST_FIELD        1
+#define STV090x_OFFST_Px_TXFIFO_BYTES_FIELD     0
+#define STV090x_WIDTH_Px_TXFIFO_BYTES_FIELD     4
+
+#define STV090x_Px_F22TX(__x)                   (0xf1a9 - (__x - 1) * 0x10)
+#define STV090x_P1_F22TX                        STV090x_Px_F22TX(1)
+#define STV090x_P2_F22TX                        STV090x_Px_F22TX(2)
+#define STV090x_OFFST_Px_F22_REG_FIELD          0
+#define STV090x_WIDTH_Px_F22_REG_FIELD          8
+
+#define STV090x_Px_F22RX(__x)                   (0xf1aa - (__x - 1) * 0x10)
+#define STV090x_P1_F22RX                        STV090x_Px_F22RX(1)
+#define STV090x_P2_F22RX                        STV090x_Px_F22RX(2)
+#define STV090x_OFFST_Px_F22RX_REG_FIELD        0
+#define STV090x_WIDTH_Px_F22RX_REG_FIELD        8
+
+#define STV090x_Px_ACRPRESC(__x)                (0xf1ac - (__x - 1) * 0x10)
+#define STV090x_P1_ACRPRESC                     STV090x_Px_ACRPRESC(1)
+#define STV090x_P2_ACRPRESC                     STV090x_Px_ACRPRESC(2)
+#define STV090x_OFFST_Px_ACR_PRESC_FIELD        0
+#define STV090x_WIDTH_Px_ACR_PRESC_FIELD        3
+
+#define STV090x_Px_ACRDIV(__x)                  (0xf1ad - (__x - 1) * 0x10)
+#define STV090x_P1_ACRDIV                       STV090x_Px_ACRDIV(1)
+#define STV090x_P2_ACRDIV                       STV090x_Px_ACRDIV(2)
+#define STV090x_OFFST_Px_ACR_DIV_FIELD          0
+#define STV090x_WIDTH_Px_ACR_DIV_FIELD          8
+
+#define STV090x_Px_IQCONST(__x)                 (0xF400 - (__x - 1) * 0x200)
+#define STV090x_P1_IQCONST                      STV090x_Px_IQCONST(1)
+#define STV090x_P2_IQCONST                      STV090x_Px_IQCONST(2)
+#define STV090x_OFFST_Px_CONSTEL_SELECT_FIELD   5
+#define STV090x_WIDTH_Px_CONSTEL_SELECT_FIELD   2
+
+#define STV090x_Px_NOSCFG(__x)                  (0xF401 - (__x - 1) * 0x200)
+#define STV090x_P1_NOSCFG                       STV090x_Px_NOSCFG(1)
+#define STV090x_P2_NOSCFG                       STV090x_Px_NOSCFG(2)
+#define STV090x_OFFST_Px_NOSPLH_BETA_FIELD      3
+#define STV090x_WIDTH_Px_NOSPLH_BETA_FIELD      2
+#define STV090x_OFFST_Px_NOSDATA_BETA_FIELD     0
+#define STV090x_WIDTH_Px_NOSDATA_BETA_FIELD     3
+
+#define STV090x_Px_ISYMB(__x)                   (0xF402 - (__x - 1) * 0x200)
+#define STV090x_P1_ISYMB                        STV090x_Px_ISYMB(1)
+#define STV090x_P2_ISYMB                        STV090x_Px_ISYMB(2)
+#define STV090x_OFFST_Px_I_SYMBOL_FIELD         0
+#define STV090x_WIDTH_Px_I_SYMBOL_FIELD         8
+
+#define STV090x_Px_QSYMB(__x)                   (0xF403 - (__x - 1) * 0x200)
+#define STV090x_P1_QSYMB                        STV090x_Px_QSYMB(1)
+#define STV090x_P2_QSYMB                        STV090x_Px_QSYMB(2)
+#define STV090x_OFFST_Px_Q_SYMBOL_FIELD         0
+#define STV090x_WIDTH_Px_Q_SYMBOL_FIELD         8
+
+#define STV090x_Px_AGC1CFG(__x)                 (0xF404 - (__x - 1) * 0x200)
+#define STV090x_P1_AGC1CFG                      STV090x_Px_AGC1CFG(1)
+#define STV090x_P2_AGC1CFG                      STV090x_Px_AGC1CFG(2)
+#define STV090x_OFFST_Px_DC_FROZEN_FIELD        7
+#define STV090x_WIDTH_Px_DC_FROZEN_FIELD        1
+#define STV090x_OFFST_Px_DC_CORRECT_FIELD       6
+#define STV090x_WIDTH_Px_DC_CORRECT_FIELD       1
+#define STV090x_OFFST_Px_AMM_FROZEN_FIELD       5
+#define STV090x_WIDTH_Px_AMM_FROZEN_FIELD       1
+#define STV090x_OFFST_Px_AMM_CORRECT_FIELD      4
+#define STV090x_WIDTH_Px_AMM_CORRECT_FIELD      1
+#define STV090x_OFFST_Px_QUAD_FROZEN_FIELD      3
+#define STV090x_WIDTH_Px_QUAD_FROZEN_FIELD      1
+#define STV090x_OFFST_Px_QUAD_CORRECT_FIELD     2
+#define STV090x_WIDTH_Px_QUAD_CORRECT_FIELD     1
+
+#define STV090x_Px_AGC1CN(__x)                  (0xF406 - (__x - 1) * 0x200)
+#define STV090x_P1_AGC1CN                       STV090x_Px_AGC1CN(1)
+#define STV090x_P2_AGC1CN                       STV090x_Px_AGC1CN(2)
+#define STV090x_WIDTH_Px_AGC1_LOCKED_FIELD      7
+#define STV090x_OFFST_Px_AGC1_LOCKED_FIELD      1
+#define STV090x_OFFST_Px_AGC1_MINPOWER_FIELD    4
+#define STV090x_WIDTH_Px_AGC1_MINPOWER_FIELD    1
+#define STV090x_OFFST_Px_AGCOUT_FAST_FIELD      3
+#define STV090x_WIDTH_Px_AGCOUT_FAST_FIELD      1
+#define STV090x_OFFST_Px_AGCIQ_BETA_FIELD       0
+#define STV090x_WIDTH_Px_AGCIQ_BETA_FIELD       3
+
+#define STV090x_Px_AGC1REF(__x)                 (0xF407 - (__x - 1) * 0x200)
+#define STV090x_P1_AGC1REF                      STV090x_Px_AGC1REF(1)
+#define STV090x_P2_AGC1REF                      STV090x_Px_AGC1REF(2)
+#define STV090x_OFFST_Px_AGCIQ_REF_FIELD        0
+#define STV090x_WIDTH_Px_AGCIQ_REF_FIELD        8
+
+#define STV090x_Px_IDCCOMP(__x)                 (0xF408 - (__x - 1) * 0x200)
+#define STV090x_P1_IDCCOMP                      STV090x_Px_IDCCOMP(1)
+#define STV090x_P2_IDCCOMP                      STV090x_Px_IDCCOMP(2)
+#define STV090x_OFFST_Px_IAVERAGE_ADJ_FIELD     0
+#define STV090x_WIDTH_Px_IAVERAGE_ADJ_FIELD     8
+
+#define STV090x_Px_QDCCOMP(__x)                 (0xF409 - (__x - 1) * 0x200)
+#define STV090x_P1_QDCCOMP                      STV090x_Px_QDCCOMP(1)
+#define STV090x_P2_QDCCOMP                      STV090x_Px_QDCCOMP(2)
+#define STV090x_OFFST_Px_QAVERAGE_ADJ_FIELD     0
+#define STV090x_WIDTH_Px_QAVERAGE_ADJ_FIELD     8
+
+#define STV090x_Px_POWERI(__x)                  (0xF40A - (__x - 1) * 0x200)
+#define STV090x_P1_POWERI                       STV090x_Px_POWERI(1)
+#define STV090x_P2_POWERI                       STV090x_Px_POWERI(2)
+#define STV090x_OFFST_Px_POWER_I_FIELD          0
+#define STV090x_WIDTH_Px_POWER_I_FIELD          8
+
+#define STV090x_Px_POWERQ(__x)                  (0xF40B - (__x - 1) * 0x200)
+#define STV090x_P1_POWERQ                       STV090x_Px_POWERQ(1)
+#define STV090x_P2_POWERQ                       STV090x_Px_POWERQ(2)
+#define STV090x_OFFST_Px_POWER_Q_FIELD          0
+#define STV090x_WIDTH_Px_POWER_Q_FIELD          8
+
+#define STV090x_Px_AGC1AMM(__x)                 (0xF40C - (__x - 1) * 0x200)
+#define STV090x_P1_AGC1AMM                      STV090x_Px_AGC1AMM(1)
+#define STV090x_P2_AGC1AMM                      STV090x_Px_AGC1AMM(2)
+#define STV090x_OFFST_Px_AMM_VALUE_FIELD        0
+#define STV090x_WIDTH_Px_AMM_VALUE_FIELD        8
+
+#define STV090x_Px_AGC1QUAD(__x)                (0xF40D - (__x - 1) * 0x200)
+#define STV090x_P1_AGC1QUAD                     STV090x_Px_AGC1QUAD(1)
+#define STV090x_P2_AGC1QUAD                     STV090x_Px_AGC1QUAD(2)
+#define STV090x_OFFST_Px_QUAD_VALUE_FIELD       0
+#define STV090x_WIDTH_Px_QUAD_VALUE_FIELD       8
+
+#define STV090x_Px_AGCIQINy(__x, __y)           (0xF40F - (__x-1) * 0x200 - __y * 0x1)
+#define STV090x_P1_AGCIQIN0                     STV090x_Px_AGCIQINy(1, 0)
+#define STV090x_P1_AGCIQIN1                     STV090x_Px_AGCIQINy(1, 1)
+#define STV090x_P2_AGCIQIN0                     STV090x_Px_AGCIQINy(2, 0)
+#define STV090x_P2_AGCIQIN1                     STV090x_Px_AGCIQINy(2, 1)
+#define STV090x_OFFST_Px_AGCIQ_VALUE_FIELD      0
+#define STV090x_WIDTH_Px_AGCIQ_VALUE_FIELD      8
+
+#define STV090x_Px_DEMOD(__x)                   (0xF410 - (__x - 1) * 0x200)
+#define STV090x_P1_DEMOD                        STV090x_Px_DEMOD(1)
+#define STV090x_P2_DEMOD                        STV090x_Px_DEMOD(2)
+#define STV090x_OFFST_Px_MANUAL_S2ROLLOFF_FIELD 7
+#define STV090x_WIDTH_Px_MANUAL_S2ROLLOFF_FIELD 1
+#define STV090x_OFFST_Px_DEMOD_STOP_FIELD       6
+#define STV090x_WIDTH_Px_DEMOD_STOP_FIELD       1
+#define STV090x_OFFST_Px_SPECINV_CONTROL_FIELD  4
+#define STV090x_WIDTH_Px_SPECINV_CONTROL_FIELD  2
+#define STV090x_OFFST_Px_FORCE_ENASAMP_FIELD    3
+#define STV090x_WIDTH_Px_FORCE_ENASAMP_FIELD    1
+#define STV090x_OFFST_Px_MANUAL_SXROLLOFF_FIELD 2
+#define STV090x_WIDTH_Px_MANUAL_SXROLLOFF_FIELD 1
+#define STV090x_OFFST_Px_ROLLOFF_CONTROL_FIELD  0
+#define STV090x_WIDTH_Px_ROLLOFF_CONTROL_FIELD  2
+
+#define STV090x_Px_DMDMODCOD(__x)               (0xF411 - (__x - 1) * 0x200)
+#define STV090x_P1_DMDMODCOD                    STV090x_Px_DMDMODCOD(1)
+#define STV090x_P2_DMDMODCOD                    STV090x_Px_DMDMODCOD(2)
+#define STV090x_OFFST_Px_MANUAL_MODCOD_FIELD    7
+#define STV090x_WIDTH_Px_MANUAL_MODCOD_FIELD    1
+#define STV090x_OFFST_Px_DEMOD_MODCOD_FIELD     2
+#define STV090x_WIDTH_Px_DEMOD_MODCOD_FIELD     5
+#define STV090x_OFFST_Px_DEMOD_TYPE_FIELD       0
+#define STV090x_WIDTH_Px_DEMOD_TYPE_FIELD       2
+
+#define STV090x_Px_DSTATUS(__x)                 (0xF412 - (__x - 1) * 0x200)
+#define STV090x_P1_DSTATUS                      STV090x_Px_DSTATUS(1)
+#define STV090x_P2_DSTATUS                      STV090x_Px_DSTATUS(2)
+#define STV090x_OFFST_Px_CAR_LOCK_FIELD         7
+#define STV090x_WIDTH_Px_CAR_LOCK_FIELD         1
+#define STV090x_OFFST_Px_TMGLOCK_QUALITY_FIELD  5
+#define STV090x_WIDTH_Px_TMGLOCK_QUALITY_FIELD  2
+#define STV090x_OFFST_Px_LOCK_DEFINITIF_FIELD   3
+#define STV090x_WIDTH_Px_LOCK_DEFINITIF_FIELD   1
+
+#define STV090x_Px_DSTATUS2(__x)                (0xF413 - (__x - 1) * 0x200)
+#define STV090x_P1_DSTATUS2                     STV090x_Px_DSTATUS2(1)
+#define STV090x_P2_DSTATUS2                     STV090x_Px_DSTATUS2(2)
+#define STV090x_OFFST_Px_DEMOD_DELOCK_FIELD     7
+#define STV090x_WIDTH_Px_DEMOD_DELOCK_FIELD     1
+#define STV090x_OFFST_Px_AGC1_NOSIGNALACK_FIELD 3
+#define STV090x_WIDTH_Px_AGC1_NOSIGNALACK_FIELD 1
+#define STV090x_OFFST_Px_AGC2_OVERFLOW_FIELD    2
+#define STV090x_WIDTH_Px_AGC2_OVERFLOW_FIELD    1
+#define STV090x_OFFST_Px_CFR_OVERFLOW_FIELD     1
+#define STV090x_WIDTH_Px_CFR_OVERFLOW_FIELD     1
+#define STV090x_OFFST_Px_GAMMA_OVERUNDER_FIELD  0
+#define STV090x_WIDTH_Px_GAMMA_OVERUNDER_FIELD  1
+
+#define STV090x_Px_DMDCFGMD(__x)                (0xF414 - (__x - 1) * 0x200)
+#define STV090x_P1_DMDCFGMD                     STV090x_Px_DMDCFGMD(1)
+#define STV090x_P2_DMDCFGMD                     STV090x_Px_DMDCFGMD(2)
+#define STV090x_OFFST_Px_DVBS2_ENABLE_FIELD     7
+#define STV090x_WIDTH_Px_DVBS2_ENABLE_FIELD     1
+#define STV090x_OFFST_Px_DVBS1_ENABLE_FIELD     6
+#define STV090x_WIDTH_Px_DVBS1_ENABLE_FIELD     1
+#define STV090x_OFFST_Px_CFR_AUTOSCAN_FIELD     5 /* check */
+#define STV090x_WIDTH_Px_CFR_AUTOSCAN_FIELD     1
+#define STV090x_OFFST_Px_SCAN_ENABLE_FIELD      4 /* check */
+#define STV090x_WIDTH_Px_SCAN_ENABLE_FIELD      1
+#define STV090x_OFFST_Px_TUN_AUTOSCAN_FIELD     3
+#define STV090x_WIDTH_Px_TUN_AUTOSCAN_FIELD     1
+#define STV090x_OFFST_Px_NOFORCE_RELOCK_FIELD   2
+#define STV090x_WIDTH_Px_NOFORCE_RELOCK_FIELD   1
+#define STV090x_OFFST_Px_TUN_RNG_FIELD          0
+#define STV090x_WIDTH_Px_TUN_RNG_FIELD          2
+
+#define STV090x_Px_DMDCFG2(__x)                 (0xF415 - (__x - 1) * 0x200)
+#define STV090x_P1_DMDCFG2                      STV090x_Px_DMDCFG2(1)
+#define STV090x_P2_DMDCFG2                      STV090x_Px_DMDCFG2(2)
+#define STV090x_OFFST_Px_S1S2_SEQUENTIAL_FIELD  6
+#define STV090x_WIDTH_Px_S1S2_SEQUENTIAL_FIELD  1
+
+#define STV090x_Px_DMDISTATE(__x)               (0xF416 - (__x - 1) * 0x200)
+#define STV090x_P1_DMDISTATE                    STV090x_Px_DMDISTATE(1)
+#define STV090x_P2_DMDISTATE                    STV090x_Px_DMDISTATE(2)
+#define STV090x_OFFST_Px_I2C_DEMOD_MODE_FIELD   0
+#define STV090x_WIDTH_Px_I2C_DEMOD_MODE_FIELD   5
+
+#define STV090x_Px_DMDTOM(__x)                  (0xF417 - (__x - 1) * 0x200) /* check */
+#define STV090x_P1_DMDTOM                       STV090x_Px_DMDTOM(1)
+#define STV090x_P2_DMDTOM                       STV090x_Px_DMDTOM(2)
+
+#define STV090x_Px_DMDSTATE(__x)                (0xF41B - (__x - 1) * 0x200)
+#define STV090x_P1_DMDSTATE                     STV090x_Px_DMDSTATE(1)
+#define STV090x_P2_DMDSTATE                     STV090x_Px_DMDSTATE(2)
+#define STV090x_OFFST_Px_HEADER_MODE_FIELD      5
+#define STV090x_WIDTH_Px_HEADER_MODE_FIELD      2
+
+#define STV090x_Px_DMDFLYW(__x)                 (0xF41C - (__x - 1) * 0x200)
+#define STV090x_P1_DMDFLYW                      STV090x_Px_DMDFLYW(1)
+#define STV090x_P2_DMDFLYW                      STV090x_Px_DMDFLYW(2)
+#define STV090x_OFFST_Px_I2C_IRQVAL_FIELD       4
+#define STV090x_WIDTH_Px_I2C_IRQVAL_FIELD       4
+#define STV090x_OFFST_Px_FLYWHEEL_CPT_FIELD     0 /* check */
+#define STV090x_WIDTH_Px_FLYWHEEL_CPT_FIELD     4
+
+#define STV090x_Px_DSTATUS3(__x)                (0xF41D - (__x - 1) * 0x200)
+#define STV090x_P1_DSTATUS3                     STV090x_Px_DSTATUS3(1)
+#define STV090x_P2_DSTATUS3                     STV090x_Px_DSTATUS3(2)
+#define STV090x_OFFST_Px_DEMOD_CFGMODE_FIELD    5
+#define STV090x_WIDTH_Px_DEMOD_CFGMODE_FIELD    2
+
+#define STV090x_Px_DMDCFG3(__x)                 (0xF41E - (__x - 1) * 0x200)
+#define STV090x_P1_DMDCFG3                      STV090x_Px_DMDCFG3(1)
+#define STV090x_P2_DMDCFG3                      STV090x_Px_DMDCFG3(2)
+#define STV090x_OFFST_Px_NOSTOP_FIFOFULL_FIELD  3
+#define STV090x_WIDTH_Px_NOSTOP_FIFOFULL_FIELD  1
+
+#define STV090x_Px_DMDCFG4(__x)                 (0xf41f - (__x - 1) * 0x200)
+#define STV090x_P1_DMDCFG4                      STV090x_Px_DMDCFG4(1)
+#define STV090x_P2_DMDCFG4                      STV090x_Px_DMDCFG4(2)
+
+#define STV090x_Px_CORRELMANT(__x)              (0xF420 - (__x - 1) * 0x200)
+#define STV090x_P1_CORRELMANT                   STV090x_Px_CORRELMANT(1)
+#define STV090x_P2_CORRELMANT                   STV090x_Px_CORRELMANT(2)
+#define STV090x_OFFST_Px_CORREL_MANT_FIELD      0
+#define STV090x_WIDTH_Px_CORREL_MANT_FIELD      8
+
+#define STV090x_Px_CORRELABS(__x)               (0xF421 - (__x - 1) * 0x200)
+#define STV090x_P1_CORRELABS                    STV090x_Px_CORRELABS(1)
+#define STV090x_P2_CORRELABS                    STV090x_Px_CORRELABS(2)
+#define STV090x_OFFST_Px_CORREL_ABS_FIELD       0
+#define STV090x_WIDTH_Px_CORREL_ABS_FIELD       8
+
+#define STV090x_Px_CORRELEXP(__x)               (0xF422 - (__x - 1) * 0x200)
+#define STV090x_P1_CORRELEXP                    STV090x_Px_CORRELEXP(1)
+#define STV090x_P2_CORRELEXP                    STV090x_Px_CORRELEXP(2)
+#define STV090x_OFFST_Px_CORREL_ABSEXP_FIELD    4
+#define STV090x_WIDTH_Px_CORREL_ABSEXP_FIELD    4
+#define STV090x_OFFST_Px_CORREL_EXP_FIELD       0
+#define STV090x_WIDTH_Px_CORREL_EXP_FIELD       4
+
+#define STV090x_Px_PLHMODCOD(__x)               (0xF424 - (__x - 1) * 0x200)
+#define STV090x_P1_PLHMODCOD                    STV090x_Px_PLHMODCOD(1)
+#define STV090x_P2_PLHMODCOD                    STV090x_Px_PLHMODCOD(2)
+#define STV090x_OFFST_Px_SPECINV_DEMOD_FIELD    7
+#define STV090x_WIDTH_Px_SPECINV_DEMOD_FIELD    1
+#define STV090x_OFFST_Px_PLH_MODCOD_FIELD       2
+#define STV090x_WIDTH_Px_PLH_MODCOD_FIELD       5
+#define STV090x_OFFST_Px_PLH_TYPE_FIELD         0
+#define STV090x_WIDTH_Px_PLH_TYPE_FIELD         2
+
+#define STV090x_Px_AGCK32(__x)                  (0xf42b - (__x - 1) * 0x200)
+#define STV090x_P1_AGCK32                       STV090x_Px_AGCK32(1)
+#define STV090x_P2_AGCK32                       STV090x_Px_AGCK32(2)
+
+#define STV090x_Px_AGC2O(__x)                   (0xF42C - (__x - 1) * 0x200)
+#define STV090x_P1_AGC2O                        STV090x_Px_AGC2O(1)
+#define STV090x_P2_AGC2O                        STV090x_Px_AGC2O(2)
+
+#define STV090x_Px_AGC2REF(__x)                 (0xF42D - (__x - 1) * 0x200)
+#define STV090x_P1_AGC2REF                      STV090x_Px_AGC2REF(1)
+#define STV090x_P2_AGC2REF                      STV090x_Px_AGC2REF(2)
+#define STV090x_OFFST_Px_AGC2_REF_FIELD         0
+#define STV090x_WIDTH_Px_AGC2_REF_FIELD         8
+
+#define STV090x_Px_AGC1ADJ(__x)                 (0xF42E - (__x - 1) * 0x200)
+#define STV090x_P1_AGC1ADJ                      STV090x_Px_AGC1ADJ(1)
+#define STV090x_P2_AGC1ADJ                      STV090x_Px_AGC1ADJ(2)
+#define STV090x_OFFST_Px_AGC1_ADJUSTED_FIELD    0
+#define STV090x_WIDTH_Px_AGC1_ADJUSTED_FIELD    7
+
+#define STV090x_Px_AGC2Iy(__x, __y)             (0xF437 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_AGC2I0                       STV090x_Px_AGC2Iy(1, 0)
+#define STV090x_P1_AGC2I1                       STV090x_Px_AGC2Iy(1, 1)
+#define STV090x_P2_AGC2I0                       STV090x_Px_AGC2Iy(2, 0)
+#define STV090x_P2_AGC2I1                       STV090x_Px_AGC2Iy(2, 1)
+#define STV090x_OFFST_Px_AGC2_INTEGRATOR_FIELD  0
+#define STV090x_WIDTH_Px_AGC2_INTEGRATOR_FIELD  8
+
+#define STV090x_Px_CARCFG(__x)                  (0xF438 - (__x - 1) * 0x200)
+#define STV090x_P1_CARCFG                       STV090x_Px_CARCFG(1)
+#define STV090x_P2_CARCFG                       STV090x_Px_CARCFG(2)
+#define STV090x_OFFST_Px_EN_CAR2CENTER_FIELD    5
+#define STV090x_WIDTH_Px_EN_CAR2CENTER_FIELD    1
+#define STV090x_OFFST_Px_ROTATON_FIELD          2
+#define STV090x_WIDTH_Px_ROTATON_FIELD          1
+#define STV090x_OFFST_Px_PH_DET_ALGO_FIELD      0
+#define STV090x_WIDTH_Px_PH_DET_ALGO_FIELD      2
+
+#define STV090x_Px_ACLC(__x)                    (0xF439 - (__x - 1) * 0x200)
+#define STV090x_P1_ACLC                         STV090x_Px_ACLC(1)
+#define STV090x_P2_ACLC                         STV090x_Px_ACLC(2)
+#define STV090x_OFFST_Px_CAR_ALPHA_MANT_FIELD   4
+#define STV090x_WIDTH_Px_CAR_ALPHA_MANT_FIELD   2
+#define STV090x_OFFST_Px_CAR_ALPHA_EXP_FIELD    0
+#define STV090x_WIDTH_Px_CAR_ALPHA_EXP_FIELD    4
+
+#define STV090x_Px_BCLC(__x)                    (0xF43A - (__x - 1) * 0x200)
+#define STV090x_P1_BCLC                         STV090x_Px_BCLC(1)
+#define STV090x_P2_BCLC                         STV090x_Px_BCLC(2)
+#define STV090x_OFFST_Px_CAR_BETA_MANT_FIELD    4
+#define STV090x_WIDTH_Px_CAR_BETA_MANT_FIELD    2
+#define STV090x_OFFST_Px_CAR_BETA_EXP_FIELD     0
+#define STV090x_WIDTH_Px_CAR_BETA_EXP_FIELD     4
+
+#define STV090x_Px_CARFREQ(__x)                 (0xF43D - (__x - 1) * 0x200)
+#define STV090x_P1_CARFREQ                      STV090x_Px_CARFREQ(1)
+#define STV090x_P2_CARFREQ                      STV090x_Px_CARFREQ(2)
+#define STV090x_OFFST_Px_KC_COARSE_EXP_FIELD    4
+#define STV090x_WIDTH_Px_KC_COARSE_EXP_FIELD    4
+#define STV090x_OFFST_Px_BETA_FREQ_FIELD        0
+#define STV090x_WIDTH_Px_BETA_FREQ_FIELD        4
+
+#define STV090x_Px_CARHDR(__x)                  (0xF43E - (__x - 1) * 0x200)
+#define STV090x_P1_CARHDR                       STV090x_Px_CARHDR(1)
+#define STV090x_P2_CARHDR                       STV090x_Px_CARHDR(2)
+#define STV090x_OFFST_Px_FREQ_HDR_FIELD         0
+#define STV090x_WIDTH_Px_FREQ_HDR_FIELD         8
+
+#define STV090x_Px_LDT(__x)                     (0xF43F - (__x - 1) * 0x200)
+#define STV090x_P1_LDT                          STV090x_Px_LDT(1)
+#define STV090x_P2_LDT                          STV090x_Px_LDT(2)
+#define STV090x_OFFST_Px_CARLOCK_THRES_FIELD    0
+#define STV090x_WIDTH_Px_CARLOCK_THRES_FIELD    8
+
+#define STV090x_Px_LDT2(__x)                    (0xF440 - (__x - 1) * 0x200)
+#define STV090x_P1_LDT2                         STV090x_Px_LDT2(1)
+#define STV090x_P2_LDT2                         STV090x_Px_LDT2(2)
+#define STV090x_OFFST_Px_CARLOCK_THRES2_FIELD   0
+#define STV090x_WIDTH_Px_CARLOCK_THRES2_FIELD   8
+
+#define STV090x_Px_CFRICFG(__x)                 (0xF441 - (__x - 1) * 0x200)
+#define STV090x_P1_CFRICFG                      STV090x_Px_CFRICFG(1)
+#define STV090x_P2_CFRICFG                      STV090x_Px_CFRICFG(2)
+#define STV090x_OFFST_Px_NEG_CFRSTEP_FIELD      0
+#define STV090x_WIDTH_Px_NEG_CFRSTEP_FIELD      1
+
+#define STV090x_Pn_CFRUPy(__x, __y)             (0xF443 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_CFRUP0                       STV090x_Pn_CFRUPy(1, 0)
+#define STV090x_P1_CFRUP1                       STV090x_Pn_CFRUPy(1, 1)
+#define STV090x_P2_CFRUP0                       STV090x_Pn_CFRUPy(2, 0)
+#define STV090x_P2_CFRUP1                       STV090x_Pn_CFRUPy(2, 1)
+#define STV090x_OFFST_Px_CFR_UP_FIELD           0
+#define STV090x_WIDTH_Px_CFR_UP_FIELD           8
+
+#define STV090x_Pn_CFRLOWy(__x, __y)            (0xF447 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_CFRLOW0                      STV090x_Pn_CFRLOWy(1, 0)
+#define STV090x_P1_CFRLOW1                      STV090x_Pn_CFRLOWy(1, 1)
+#define STV090x_P2_CFRLOW0                      STV090x_Pn_CFRLOWy(2, 0)
+#define STV090x_P2_CFRLOW1                      STV090x_Pn_CFRLOWy(2, 1)
+#define STV090x_OFFST_Px_CFR_LOW_FIELD          0
+#define STV090x_WIDTH_Px_CFR_LOW_FIELD          8
+
+#define STV090x_Pn_CFRINITy(__x, __y)           (0xF449 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_CFRINIT0                     STV090x_Pn_CFRINITy(1, 0)
+#define STV090x_P1_CFRINIT1                     STV090x_Pn_CFRINITy(1, 1)
+#define STV090x_P2_CFRINIT0                     STV090x_Pn_CFRINITy(2, 0)
+#define STV090x_P2_CFRINIT1                     STV090x_Pn_CFRINITy(2, 1)
+#define STV090x_OFFST_Px_CFR_INIT_FIELD         0
+#define STV090x_WIDTH_Px_CFR_INIT_FIELD         8
+
+#define STV090x_Px_CFRINC1(__x)                 (0xF44A - (__x - 1) * 0x200)
+#define STV090x_P1_CFRINC1                      STV090x_Px_CFRINC1(1)
+#define STV090x_P2_CFRINC1                      STV090x_Px_CFRINC1(2)
+#define STV090x_OFFST_Px_CFR_INC1_FIELD         0
+#define STV090x_WIDTH_Px_CFR_INC1_FIELD         7
+
+#define STV090x_Px_CFRINC0(__x)                 (0xF44B - (__x - 1) * 0x200)
+#define STV090x_P1_CFRINC0                      STV090x_Px_CFRINC0(1)
+#define STV090x_P2_CFRINC0                      STV090x_Px_CFRINC0(2)
+#define STV090x_OFFST_Px_CFR_INC0_FIELD         4
+#define STV090x_WIDTH_Px_CFR_INC0_FIELD         4
+
+#define STV090x_Pn_CFRy(__x, __y)               (0xF44E - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_CFR0                         STV090x_Pn_CFRy(1, 0)
+#define STV090x_P1_CFR1                         STV090x_Pn_CFRy(1, 1)
+#define STV090x_P1_CFR2                         STV090x_Pn_CFRy(1, 2)
+#define STV090x_P2_CFR0                         STV090x_Pn_CFRy(2, 0)
+#define STV090x_P2_CFR1                         STV090x_Pn_CFRy(2, 1)
+#define STV090x_P2_CFR2                         STV090x_Pn_CFRy(2, 2)
+#define STV090x_OFFST_Px_CAR_FREQ_FIELD         0
+#define STV090x_WIDTH_Px_CAR_FREQ_FIELD         8
+
+#define STV090x_Px_LDI(__x)                     (0xF44F - (__x - 1) * 0x200)
+#define STV090x_P1_LDI                          STV090x_Px_LDI(1)
+#define STV090x_P2_LDI                          STV090x_Px_LDI(2)
+#define STV090x_OFFST_Px_LOCK_DET_INTEGR_FIELD  0
+#define STV090x_WIDTH_Px_LOCK_DET_INTEGR_FIELD  8
+
+#define STV090x_Px_TMGCFG(__x)                  (0xF450 - (__x - 1) * 0x200)
+#define STV090x_P1_TMGCFG                       STV090x_Px_TMGCFG(1)
+#define STV090x_P2_TMGCFG                       STV090x_Px_TMGCFG(2)
+#define STV090x_OFFST_Px_TMGLOCK_BETA_FIELD     6
+#define STV090x_WIDTH_Px_TMGLOCK_BETA_FIELD     2
+#define STV090x_OFFST_Px_DO_TIMING_FIELD        4
+#define STV090x_WIDTH_Px_DO_TIMING_FIELD        1
+#define STV090x_OFFST_Px_TMG_MINFREQ_FIELD      0
+#define STV090x_WIDTH_Px_TMG_MINFREQ_FIELD      2
+
+#define STV090x_Px_RTC(__x)                     (0xF451 - (__x - 1) * 0x200)
+#define STV090x_P1_RTC                          STV090x_Px_RTC(1)
+#define STV090x_P2_RTC                          STV090x_Px_RTC(2)
+#define STV090x_OFFST_Px_TMGALPHA_EXP_FIELD     4
+#define STV090x_WIDTH_Px_TMGALPHA_EXP_FIELD     4
+#define STV090x_OFFST_Px_TMGBETA_EXP_FIELD      0
+#define STV090x_WIDTH_Px_TMGBETA_EXP_FIELD      4
+
+#define STV090x_Px_RTCS2(__x)                   (0xF452 - (__x - 1) * 0x200)
+#define STV090x_P1_RTCS2                        STV090x_Px_RTCS2(1)
+#define STV090x_P2_RTCS2                        STV090x_Px_RTCS2(2)
+#define STV090x_OFFST_Px_TMGALPHAS2_EXP_FIELD   4
+#define STV090x_WIDTH_Px_TMGALPHAS2_EXP_FIELD   4
+#define STV090x_OFFST_Px_TMGBETAS2_EXP_FIELD    0
+#define STV090x_WIDTH_Px_TMGBETAS2_EXP_FIELD    4
+
+#define STV090x_Px_TMGTHRISE(__x)               (0xF453 - (__x - 1) * 0x200)
+#define STV090x_P1_TMGTHRISE                    STV090x_Px_TMGTHRISE(1)
+#define STV090x_P2_TMGTHRISE                    STV090x_Px_TMGTHRISE(2)
+#define STV090x_OFFST_Px_TMGLOCK_THRISE_FIELD   0
+#define STV090x_WIDTH_Px_TMGLOCK_THRISE_FIELD   8
+
+#define STV090x_Px_TMGTHFALL(__x)               (0xF454 - (__x - 1) * 0x200)
+#define STV090x_P1_TMGTHFALL                    STV090x_Px_TMGTHFALL(1)
+#define STV090x_P2_TMGTHFALL                    STV090x_Px_TMGTHFALL(2)
+#define STV090x_OFFST_Px_TMGLOCK_THFALL_FIELD   0
+#define STV090x_WIDTH_Px_TMGLOCK_THFALL_FIELD   8
+
+#define STV090x_Px_SFRUPRATIO(__x)              (0xF455 - (__x - 1) * 0x200)
+#define STV090x_P1_SFRUPRATIO                   STV090x_Px_SFRUPRATIO(1)
+#define STV090x_P2_SFRUPRATIO                   STV090x_Px_SFRUPRATIO(2)
+#define STV090x_OFFST_Px_SFR_UPRATIO_FIELD      0
+#define STV090x_WIDTH_Px_SFR_UPRATIO_FIELD      8
+
+#define STV090x_Px_SFRLOWRATIO(__x)             (0xF456 - (__x - 1) * 0x200)
+#define STV090x_P1_SFRLOWRATIO                  STV090x_Px_SFRLOWRATIO(1)
+#define STV090x_P2_SFRLOWRATIO                  STV090x_Px_SFRLOWRATIO(2)
+#define STV090x_OFFST_Px_SFR_LOWRATIO_FIELD     0
+#define STV090x_WIDTH_Px_SFR_LOWRATIO_FIELD     8
+
+#define STV090x_Px_KREFTMG(__x)                 (0xF458 - (__x - 1) * 0x200)
+#define STV090x_P1_KREFTMG                      STV090x_Px_KREFTMG(1)
+#define STV090x_P2_KREFTMG                      STV090x_Px_KREFTMG(2)
+#define STV090x_OFFST_Px_KREF_TMG_FIELD         0
+#define STV090x_WIDTH_Px_KREF_TMG_FIELD         8
+
+#define STV090x_Px_SFRSTEP(__x)                 (0xF459 - (__x - 1) * 0x200)
+#define STV090x_P1_SFRSTEP                      STV090x_Px_SFRSTEP(1)
+#define STV090x_P2_SFRSTEP                      STV090x_Px_SFRSTEP(2)
+#define STV090x_OFFST_Px_SFR_SCANSTEP_FIELD     4
+#define STV090x_WIDTH_Px_SFR_SCANSTEP_FIELD     4
+#define STV090x_OFFST_Px_SFR_CENTERSTEP_FIELD   0
+#define STV090x_WIDTH_Px_SFR_CENTERSTEP_FIELD   4
+
+#define STV090x_Px_TMGCFG2(__x)                 (0xF45A - (__x - 1) * 0x200)
+#define STV090x_P1_TMGCFG2                      STV090x_Px_TMGCFG2(1)
+#define STV090x_P2_TMGCFG2                      STV090x_Px_TMGCFG2(2)
+#define STV090x_OFFST_Px_SFRRATIO_FINE_FIELD    0
+#define STV090x_WIDTH_Px_SFRRATIO_FINE_FIELD    1
+
+#define STV090x_Px_SFRINIT1(__x)                (0xF45E - (__x - 1) * 0x200)
+#define STV090x_P1_SFRINIT1                     STV090x_Px_SFRINIT1(1)
+#define STV090x_P2_SFRINIT1                     STV090x_Px_SFRINIT1(2)
+#define STV090x_OFFST_Px_SFR_INIT_FIELD         0
+#define STV090x_WIDTH_Px_SFR_INIT_FIELD         8
+
+#define STV090x_Px_SFRINIT0(__x)                (0xF45F - (__x - 1) * 0x200)
+#define STV090x_P1_SFRINIT0                     STV090x_Px_SFRINIT0(1)
+#define STV090x_P2_SFRINIT0                     STV090x_Px_SFRINIT0(2)
+#define STV090x_OFFST_Px_SFR_INIT_FIELD         0
+#define STV090x_WIDTH_Px_SFR_INIT_FIELD         8
+
+#define STV090x_Px_SFRUP1(__x)                  (0xF460 - (__x - 1) * 0x200)
+#define STV090x_P1_SFRUP1                       STV090x_Px_SFRUP1(1)
+#define STV090x_P2_SFRUP1                       STV090x_Px_SFRUP1(2)
+#define STV090x_OFFST_Px_SYMB_FREQ_UP1_FIELD    0
+#define STV090x_WIDTH_Px_SYMB_FREQ_UP1_FIELD    7
+
+#define STV090x_Px_SFRUP0(__x)                  (0xF461 - (__x - 1) * 0x200)
+#define STV090x_P1_SFRUP0                       STV090x_Px_SFRUP0(1)
+#define STV090x_P2_SFRUP0                       STV090x_Px_SFRUP0(2)
+#define STV090x_OFFST_Px_SYMB_FREQ_UP0_FIELD    0
+#define STV090x_WIDTH_Px_SYMB_FREQ_UP0_FIELD    8
+
+#define STV090x_Px_SFRLOW1(__x)                 (0xF462 - (__x - 1) * 0x200)
+#define STV090x_P1_SFRLOW1                      STV090x_Px_SFRLOW1(1)
+#define STV090x_P2_SFRLOW1                      STV090x_Px_SFRLOW1(2)
+#define STV090x_OFFST_Px_SYMB_FREQ_LOW1_FIELD   0
+#define STV090x_WIDTH_Px_SYMB_FREQ_LOW1_FIELD   7
+
+#define STV090x_Px_SFRLOW0(__x)                 (0xF463 - (__x - 1) * 0x200)
+#define STV090x_P1_SFRLOW0                      STV090x_Px_SFRLOW0(1)
+#define STV090x_P2_SFRLOW0                      STV090x_Px_SFRLOW0(2)
+#define STV090x_OFFST_Px_SYMB_FREQ_LOW0_FIELD   0
+#define STV090x_WIDTH_Px_SYMB_FREQ_LOW0_FIELD   8
+
+#define STV090x_Px_SFRy(__x, __y)               (0xF464 - (__x-1) * 0x200 + (3 - __y))
+#define STV090x_P1_SFR0                         STV090x_Px_SFRy(1, 0)
+#define STV090x_P1_SFR1                         STV090x_Px_SFRy(1, 1)
+#define STV090x_P1_SFR2                         STV090x_Px_SFRy(1, 2)
+#define STV090x_P1_SFR3                         STV090x_Px_SFRy(1, 3)
+#define STV090x_P2_SFR0                         STV090x_Px_SFRy(2, 0)
+#define STV090x_P2_SFR1                         STV090x_Px_SFRy(2, 1)
+#define STV090x_P2_SFR2                         STV090x_Px_SFRy(2, 2)
+#define STV090x_P2_SFR3                         STV090x_Px_SFRy(2, 3)
+#define STV090x_OFFST_Px_SYMB_FREQ_FIELD        0
+#define STV090x_WIDTH_Px_SYMB_FREQ_FIELD        32
+
+#define STV090x_Px_TMGREG2(__x)                 (0xF468 - (__x - 1) * 0x200)
+#define STV090x_P1_TMGREG2                      STV090x_Px_TMGREG2(1)
+#define STV090x_P2_TMGREG2                      STV090x_Px_TMGREG2(2)
+#define STV090x_OFFST_Px_TMGREG_FIELD           0
+#define STV090x_WIDTH_Px_TMGREG_FIELD           8
+
+#define STV090x_Px_TMGREG1(__x)                 (0xF469 - (__x - 1) * 0x200)
+#define STV090x_P1_TMGREG1                      STV090x_Px_TMGREG1(1)
+#define STV090x_P2_TMGREG1                              STV090x_Px_TMGREG1(2)
+#define STV090x_OFFST_Px_TMGREG_FIELD           0
+#define STV090x_WIDTH_Px_TMGREG_FIELD           8
+
+#define STV090x_Px_TMGREG0(__x)                 (0xF46A - (__x - 1) * 0x200)
+#define STV090x_P1_TMGREG0                      STV090x_Px_TMGREG0(1)
+#define STV090x_P2_TMGREG0                      STV090x_Px_TMGREG0(2)
+#define STV090x_OFFST_Px_TMGREG_FIELD           0
+#define STV090x_WIDTH_Px_TMGREG_FIELD           8
+
+#define STV090x_Px_TMGLOCKy(__x, __y)           (0xF46C - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_TMGLOCK0                     STV090x_Px_TMGLOCKy(1, 0)
+#define STV090x_P1_TMGLOCK1                     STV090x_Px_TMGLOCKy(1, 1)
+#define STV090x_P2_TMGLOCK0                     STV090x_Px_TMGLOCKy(2, 0)
+#define STV090x_P2_TMGLOCK1                     STV090x_Px_TMGLOCKy(2, 1)
+#define STV090x_OFFST_Px_TMGLOCK_LEVEL_FIELD    0
+#define STV090x_WIDTH_Px_TMGLOCK_LEVEL_FIELD    8
+
+#define STV090x_Px_TMGOBS(__x)                  (0xF46D - (__x - 1) * 0x200)
+#define STV090x_P1_TMGOBS                       STV090x_Px_TMGOBS(1)
+#define STV090x_P2_TMGOBS                       STV090x_Px_TMGOBS(2)
+#define STV090x_OFFST_Px_ROLLOFF_STATUS_FIELD   6
+#define STV090x_WIDTH_Px_ROLLOFF_STATUS_FIELD   2
+
+#define STV090x_Px_EQUALCFG(__x)                (0xF46F - (__x - 1) * 0x200)
+#define STV090x_P1_EQUALCFG                     STV090x_Px_EQUALCFG(1)
+#define STV090x_P2_EQUALCFG                     STV090x_Px_EQUALCFG(2)
+#define STV090x_OFFST_Px_EQUAL_ON_FIELD         6
+#define STV090x_WIDTH_Px_EQUAL_ON_FIELD         1
+#define STV090x_OFFST_Px_MU_EQUALDFE_FIELD      0
+#define STV090x_WIDTH_Px_MU_EQUALDFE_FIELD      3
+
+#define STV090x_Px_EQUAIy(__x, __y)             (0xf470 - (__x - 1) * 0x200 + (__y - 1))
+#define STV090x_P1_EQUAI1                       STV090x_Px_EQUAIy(1, 1)
+#define STV090x_P1_EQUAI2                       STV090x_Px_EQUAIy(1, 2)
+#define STV090x_P1_EQUAI3                       STV090x_Px_EQUAIy(1, 3)
+#define STV090x_P1_EQUAI4                       STV090x_Px_EQUAIy(1, 4)
+#define STV090x_P1_EQUAI5                       STV090x_Px_EQUAIy(1, 5)
+#define STV090x_P1_EQUAI6                       STV090x_Px_EQUAIy(1, 6)
+#define STV090x_P1_EQUAI7                       STV090x_Px_EQUAIy(1, 7)
+#define STV090x_P1_EQUAI8                       STV090x_Px_EQUAIy(1, 8)
+
+#define STV090x_P2_EQUAI1                       STV090x_Px_EQUAIy(2, 1)
+#define STV090x_P2_EQUAI2                       STV090x_Px_EQUAIy(2, 2)
+#define STV090x_P2_EQUAI3                       STV090x_Px_EQUAIy(2, 3)
+#define STV090x_P2_EQUAI4                       STV090x_Px_EQUAIy(2, 4)
+#define STV090x_P2_EQUAI5                       STV090x_Px_EQUAIy(2, 5)
+#define STV090x_P2_EQUAI6                       STV090x_Px_EQUAIy(2, 6)
+#define STV090x_P2_EQUAI7                       STV090x_Px_EQUAIy(2, 7)
+#define STV090x_P2_EQUAI8                       STV090x_Px_EQUAIy(2, 8)
+#define STV090x_OFFST_Px_EQUA_ACCIy_FIELD       0
+#define STV090x_WIDTH_Px_EQUA_ACCIy_FIELD       8
+
+#define STV090x_Px_EQUAQy(__x, __y)             (0xf471 - (__x - 1) * 0x200 + (__y - 1))
+#define STV090x_P1_EQUAQ1                       STV090x_Px_EQUAQy(1, 1)
+#define STV090x_P1_EQUAQ2                       STV090x_Px_EQUAQy(1, 2)
+#define STV090x_P1_EQUAQ3                       STV090x_Px_EQUAQy(1, 3)
+#define STV090x_P1_EQUAQ4                       STV090x_Px_EQUAQy(1, 4)
+#define STV090x_P1_EQUAQ5                       STV090x_Px_EQUAQy(1, 5)
+#define STV090x_P1_EQUAQ6                       STV090x_Px_EQUAQy(1, 6)
+#define STV090x_P1_EQUAQ7                       STV090x_Px_EQUAQy(1, 7)
+#define STV090x_P1_EQUAQ8                       STV090x_Px_EQUAQy(1, 8)
+
+#define STV090x_P2_EQUAQ1                       STV090x_Px_EQUAQy(2, 1)
+#define STV090x_P2_EQUAQ2                       STV090x_Px_EQUAQy(2, 2)
+#define STV090x_P2_EQUAQ3                       STV090x_Px_EQUAQy(2, 3)
+#define STV090x_P2_EQUAQ4                       STV090x_Px_EQUAQy(2, 4)
+#define STV090x_P2_EQUAQ5                       STV090x_Px_EQUAQy(2, 5)
+#define STV090x_P2_EQUAQ6                       STV090x_Px_EQUAQy(2, 6)
+#define STV090x_P2_EQUAQ7                       STV090x_Px_EQUAQy(2, 7)
+#define STV090x_P2_EQUAQ8                       STV090x_Px_EQUAQy(2, 8)
+#define STV090x_OFFST_Px_EQUA_ACCQy_FIELD       0
+#define STV090x_WIDTH_Px_EQUA_ACCQy_FIELD       8
+
+#define STV090x_Px_NNOSDATATy(__x, __y)         (0xf481 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_NNOSDATAT0                   STV090x_Px_NNOSDATATy(1, 0)
+#define STV090x_P1_NNOSDATAT1                   STV090x_Px_NNOSDATATy(1, 1)
+#define STV090x_P2_NNOSDATAT0                   STV090x_Px_NNOSDATATy(2, 0)
+#define STV090x_P2_NNOSDATAT1                   STV090x_Px_NNOSDATATy(2, 1)
+#define STV090x_OFFST_Px_NOSDATAT_NORMED_FIELD  0
+#define STV090x_WIDTH_Px_NOSDATAT_NORMED_FIELD  8
+
+#define STV090x_Px_NNOSDATAy(__x, __y)          (0xf483 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_NNOSDATA0                    STV090x_Px_NNOSDATAy(1, 0)
+#define STV090x_P1_NNOSDATA1                    STV090x_Px_NNOSDATAy(1, 1)
+#define STV090x_P2_NNOSDATA0                    STV090x_Px_NNOSDATAy(2, 0)
+#define STV090x_P2_NNOSDATA1                    STV090x_Px_NNOSDATAy(2, 1)
+#define STV090x_OFFST_Px_NOSDATA_NORMED_FIELD   0
+#define STV090x_WIDTH_Px_NOSDATA_NORMED_FIELD   8
+
+#define STV090x_Px_NNOSPLHTy(__x, __y)          (0xf485 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_NNOSPLHT0                    STV090x_Px_NNOSPLHTy(1, 0)
+#define STV090x_P1_NNOSPLHT1                    STV090x_Px_NNOSPLHTy(1, 1)
+#define STV090x_P2_NNOSPLHT0                    STV090x_Px_NNOSPLHTy(2, 0)
+#define STV090x_P2_NNOSPLHT1                    STV090x_Px_NNOSPLHTy(2, 1)
+#define STV090x_OFFST_Px_NOSPLHT_NORMED_FIELD   0
+#define STV090x_WIDTH_Px_NOSPLHT_NORMED_FIELD   8
+
+#define STV090x_Px_NNOSPLHy(__x, __y)           (0xf487 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_NNOSPLH0                     STV090x_Px_NNOSPLHy(1, 0)
+#define STV090x_P1_NNOSPLH1                     STV090x_Px_NNOSPLHy(1, 1)
+#define STV090x_P2_NNOSPLH0                     STV090x_Px_NNOSPLHy(2, 0)
+#define STV090x_P2_NNOSPLH1                     STV090x_Px_NNOSPLHy(2, 1)
+#define STV090x_OFFST_Px_NOSPLH_NORMED_FIELD    0
+#define STV090x_WIDTH_Px_NOSPLH_NORMED_FIELD    8
+
+#define STV090x_Px_NOSDATATy(__x, __y)                  (0xf489 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_NOSDATAT0                            STV090x_Px_NOSDATATy(1, 0)
+#define STV090x_P1_NOSDATAT1                            STV090x_Px_NOSDATATy(1, 1)
+#define STV090x_P2_NOSDATAT0                            STV090x_Px_NOSDATATy(2, 0)
+#define STV090x_P2_NOSDATAT1                            STV090x_Px_NOSDATATy(2, 1)
+#define STV090x_OFFST_Px_NOSDATAT_UNNORMED_FIELD        0
+#define STV090x_WIDTH_Px_NOSDATAT_UNNORMED_FIELD        8
+
+#define STV090x_Px_NOSDATAy(__x, __y)           (0xf48b - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_NOSDATA0                     STV090x_Px_NOSDATAy(1, 0)
+#define STV090x_P1_NOSDATA1                     STV090x_Px_NOSDATAy(1, 1)
+#define STV090x_P2_NOSDATA0                     STV090x_Px_NOSDATAy(2, 0)
+#define STV090x_P2_NOSDATA1                     STV090x_Px_NOSDATAy(2, 1)
+#define STV090x_OFFST_Px_NOSDATA_UNNORMED_FIELD 0
+#define STV090x_WIDTH_Px_NOSDATA_UNNORMED_FIELD 8
+
+#define STV090x_Px_NOSPLHTy(__x, __y)           (0xf48d - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_NOSPLHT0                     STV090x_Px_NOSPLHTy(1, 0)
+#define STV090x_P1_NOSPLHT1                     STV090x_Px_NOSPLHTy(1, 1)
+#define STV090x_P2_NOSPLHT0                     STV090x_Px_NOSPLHTy(2, 0)
+#define STV090x_P2_NOSPLHT1                     STV090x_Px_NOSPLHTy(2, 1)
+#define STV090x_OFFST_Px_NOSPLHT_UNNORMED_FIELD 0
+#define STV090x_WIDTH_Px_NOSPLHT_UNNORMED_FIELD 8
+
+#define STV090x_Px_NOSPLHy(__x, __y)            (0xf48f - (__x - 1) * 0x200 - __y * 0x1)
+#define STv090x_P1_NOSPLH0                      STV090x_Px_NOSPLHy(1, 0)
+#define STv090x_P1_NOSPLH1                      STV090x_Px_NOSPLHy(1, 1)
+#define STv090x_P2_NOSPLH0                      STV090x_Px_NOSPLHy(2, 0)
+#define STv090x_P2_NOSPLH1                      STV090x_Px_NOSPLHy(2, 1)
+#define STV090x_OFFST_Px_NOSPLH_UNNORMED_FIELD  0
+#define STV090x_WIDTH_Px_NOSPLH_UNNORMED_FIELD  8
+
+#define STV090x_Px_CAR2CFG(__x)                 (0xf490 - (__x - 1) * 0x200)
+#define STV090x_P1_CAR2CFG                      STV090x_Px_CAR2CFG(1)
+#define STV090x_P2_CAR2CFG                      STV090x_Px_CAR2CFG(2)
+#define STV090x_OFFST_Px_PN4_SELECT_FIELD       6
+#define STV090x_WIDTH_Px_PN4_SELECT_FIELD       1
+#define STV090x_OFFST_Px_CFR2_STOPDVBS1_FIELD   5
+#define STV090x_WIDTH_Px_CFR2_STOPDVBS1_FIELD   1
+#define STV090x_OFFST_Px_ROTA2ON_FIELD          2
+#define STV090x_WIDTH_Px_ROTA2ON_FIELD          1
+#define STV090x_OFFST_Px_PH_DET_ALGO2_FIELD     0
+#define STV090x_WIDTH_Px_PH_DET_ALGO2_FIELD     2
+
+#define STV090x_Px_ACLC2(__x)                   (0xf491 - (__x - 1) * 0x200)
+#define STV090x_P1_ACLC2                        STV090x_Px_ACLC2(1)
+#define STV090x_P2_ACLC2                        STV090x_Px_ACLC2(2)
+#define STV090x_OFFST_Px_CAR2_ALPHA_MANT_FIELD  4
+#define STV090x_WIDTH_Px_CAR2_ALPHA_MANT_FIELD  2
+#define STV090x_OFFST_Px_CAR2_ALPHA_EXP_FIELD   0
+#define STV090x_WIDTH_Px_CAR2_ALPHA_EXP_FIELD   4
+
+#define STV090x_Px_BCLC2(__x)                   (0xf492 - (__x - 1) * 0x200)
+#define STV090x_P1_BCLC2                        STV090x_Px_BCLC2(1)
+#define STV090x_P2_BCLC2                        STV090x_Px_BCLC2(2)
+#define STV090x_OFFST_Px_CAR2_BETA_MANT_FIELD   4
+#define STV090x_WIDTH_Px_CAR2_BETA_MANT_FIELD   2
+#define STV090x_OFFST_Px_CAR2_BETA_EXP_FIELD    0
+#define STV090x_WIDTH_Px_CAR2_BETA_EXP_FIELD    4
+
+#define STV090x_Px_ACLC2S2Q(__x)                (0xf497 - (__x - 1) * 0x200)
+#define STV090x_P1_ACLC2S2Q                     STV090x_Px_ACLC2S2Q(1)
+#define STV090x_P2_ACLC2S2Q                     STV090x_Px_ACLC2S2Q(2)
+#define STV090x_OFFST_Px_ENAB_SPSKSYMB_FIELD    7
+#define STV090x_WIDTH_Px_ENAB_SPSKSYMB_FIELD    1
+#define STV090x_OFFST_Px_CAR2S2_Q_ALPH_M_FIELD  4
+#define STV090x_WIDTH_Px_CAR2S2_Q_ALPH_M_FIELD  2
+#define STV090x_OFFST_Px_CAR2S2_Q_ALPH_E_FIELD  0
+#define STV090x_WIDTH_Px_CAR2S2_Q_ALPH_E_FIELD  4
+
+#define STV090x_Px_ACLC2S28(__x)                (0xf498 - (__x - 1) * 0x200)
+#define STV090x_P1_ACLC2S28                     STV090x_Px_ACLC2S28(1)
+#define STV090x_P2_ACLC2S28                     STV090x_Px_ACLC2S28(2)
+#define STV090x_OFFST_Px_CAR2S2_8_ALPH_M_FIELD  4
+#define STV090x_WIDTH_Px_CAR2S2_8_ALPH_M_FIELD  2
+#define STV090x_OFFST_Px_CAR2S2_8_ALPH_E_FIELD  0
+#define STV090x_WIDTH_Px_CAR2S2_8_ALPH_E_FIELD  4
+
+#define STV090x_Px_ACLC2S216A(__x)              (0xf499 - (__x - 1) * 0x200)
+#define STV090x_P1_ACLC2S216A                   STV090x_Px_ACLC2S216A(1)
+#define STV090x_P2_ACLC2S216A                   STV090x_Px_ACLC2S216A(2)
+#define STV090x_OFFST_Px_CAR2S2_16A_ALPH_M_FIELD        4
+#define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_M_FIELD        2
+#define STV090x_OFFST_Px_CAR2S2_16A_ALPH_E_FIELD        0
+#define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_E_FIELD        4
+
+#define STV090x_Px_ACLC2S232A(__x)              (0xf499 - (__x - 1) * 0x200)
+#define STV090x_P1_ACLC2S232A                   STV090x_Px_ACLC2S232A(1)
+#define STV090x_P2_ACLC2S232A                   STV090x_Px_ACLC2S232A(2)
+#define STV090x_OFFST_Px_CAR2S2_32A_ALPH_M_FIELD        4
+#define STV090x_WIDTH_Px_CAR2S2_32A_ALPH_M_FIELD        2
+#define STV090x_OFFST_Px_CAR2S2_32A_ALPH_E_FIELD        0
+#define STV090x_WIDTH_Px_CAR2S2_32A_ALPH_E_FIELD        4
+
+#define STV090x_Px_BCLC2S2Q(__x)                (0xf49c - (__x - 1) * 0x200)
+#define STV090x_P1_BCLC2S2Q                     STV090x_Px_BCLC2S2Q(1)
+#define STV090x_P2_BCLC2S2Q                     STV090x_Px_BCLC2S2Q(2)
+#define STV090x_OFFST_Px_CAR2S2_Q_BETA_M_FIELD  4
+#define STV090x_WIDTH_Px_CAR2S2_Q_BETA_M_FIELD  2
+#define STV090x_OFFST_Px_CAR2S2_Q_BETA_E_FIELD  0
+#define STV090x_WIDTH_Px_CAR2S2_Q_BETA_E_FIELD  4
+
+#define STV090x_Px_BCLC2S28(__x)                (0xf49d - (__x - 1) * 0x200)
+#define STV090x_P1_BCLC2S28                     STV090x_Px_BCLC2S28(1)
+#define STV090x_P2_BCLC2S28                     STV090x_Px_BCLC2S28(1)
+#define STV090x_OFFST_Px_CAR2S2_8_BETA_M_FIELD  4
+#define STV090x_WIDTH_Px_CAR2S2_8_BETA_M_FIELD  2
+#define STV090x_OFFST_Px_CAR2S2_8_BETA_E_FIELD  0
+#define STV090x_WIDTH_Px_CAR2S2_8_BETA_E_FIELD  4
+
+#define STV090x_Px_BCLC2S216A(__x)              (0xf49d - (__x - 1) * 0x200)
+#define STV090x_P1_BCLC2S216A                   STV090x_Px_BCLC2S216A(1)
+#define STV090x_P2_BCLC2S216A                   STV090x_Px_BCLC2S216A(1)
+#define STV090x_OFFST_Px_CAR2S2_16A_BETA_M_FIELD        4
+#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_M_FIELD        2
+#define STV090x_OFFST_Px_CAR2S2_16A_BETA_E_FIELD        0
+#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_E_FIELD        4
+
+#define STV090x_Px_BCLC2S232A(__x)              (0xf49d - (__x - 1) * 0x200)
+#define STV090x_P1_BCLC2S232A                   STV090x_Px_BCLC2S232A(1)
+#define STV090x_P2_BCLC2S232A                   STV090x_Px_BCLC2S232A(1)
+#define STV090x_OFFST_Px_CAR2S2_32A_BETA_M_FIELD        4
+#define STV090x_WIDTH_Px_CAR2S2_32A_BETA_M_FIELD        2
+#define STV090x_OFFST_Px_CAR2S2_32A_BETA_E_FIELD        0
+#define STV090x_WIDTH_Px_CAR2S2_32A_BETA_E_FIELD        4
+
+#define STV090x_Px_PLROOT2(__x)                 (0xf4ac - (__x - 1) * 0x200)
+#define STV090x_P1_PLROOT2                      STV090x_Px_PLROOT2(1)
+#define STV090x_P2_PLROOT2                      STV090x_Px_PLROOT2(2)
+#define STV090x_OFFST_Px_PLSCRAMB_MODE_FIELD    2
+#define STV090x_WIDTH_Px_PLSCRAMB_MODE_FIELD    2
+#define STV090x_OFFST_Px_PLSCRAMB_ROOT_FIELD    0
+#define STV090x_WIDTH_Px_PLSCRAMB_ROOT_FIELD    2
+
+#define STV090x_Px_PLROOT1(__x)                 (0xf4ad - (__x - 1) * 0x200)
+#define STV090x_P1_PLROOT1                      STV090x_Px_PLROOT1(1)
+#define STV090x_P2_PLROOT1                      STV090x_Px_PLROOT1(2)
+#define STV090x_OFFST_Px_PLSCRAMB_ROOT1_FIELD   0
+#define STV090x_WIDTH_Px_PLSCRAMB_ROOT1_FIELD   8
+
+#define STV090x_Px_PLROOT0(__x)                 (0xf4ae - (__x - 1) * 0x200)
+#define STV090x_P1_PLROOT0                      STV090x_Px_PLROOT0(1)
+#define STV090x_P2_PLROOT0                      STV090x_Px_PLROOT0(2)
+#define STV090x_OFFST_Px_PLSCRAMB_ROOT0_FIELD   0
+#define STV090x_WIDTH_Px_PLSCRAMB_ROOT0_FIELD   8
+
+#define STV090x_Px_MODCODLST0(__x)              (0xf4b0 - (__x - 1) * 0x200) /* check */
+#define STV090x_P1_MODCODLST0                   STV090x_Px_MODCODLST0(1)
+#define STV090x_P2_MODCODLST0                   STV090x_Px_MODCODLST0(2)
+
+#define STV090x_Px_MODCODLST1(__x)              (0xf4b1 - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLST1                   STV090x_Px_MODCODLST1(1)
+#define STV090x_P2_MODCODLST1                   STV090x_Px_MODCODLST1(2)
+#define STV090x_OFFST_Px_DIS_MODCOD29_FIELD     4
+#define STV090x_WIDTH_Px_DIS_MODCOD29T_FIELD    4
+#define STV090x_OFFST_Px_DIS_32PSK_9_10_FIELD   0
+#define STV090x_WIDTH_Px_DIS_32PSK_9_10_FIELD   4
+
+#define STV090x_Px_MODCODLST2(__x)              (0xf4b2 - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLST2                   STV090x_Px_MODCODLST2(1)
+#define STV090x_P2_MODCODLST2                   STV090x_Px_MODCODLST2(2)
+#define STV090x_OFFST_Px_DIS_32PSK_8_9_FIELD    4
+#define STV090x_WIDTH_Px_DIS_32PSK_8_9_FIELD    4
+#define STV090x_OFFST_Px_DIS_32PSK_5_6_FIELD    0
+#define STV090x_WIDTH_Px_DIS_32PSK_5_6_FIELD    4
+
+#define STV090x_Px_MODCODLST3(__x)              (0xf4b3 - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLST3                   STV090x_Px_MODCODLST3(1)
+#define STV090x_P2_MODCODLST3                   STV090x_Px_MODCODLST3(2)
+#define STV090x_OFFST_Px_DIS_32PSK_4_5_FIELD    4
+#define STV090x_WIDTH_Px_DIS_32PSK_4_5_FIELD    4
+#define STV090x_OFFST_Px_DIS_32PSK_3_4_FIELD    0
+#define STV090x_WIDTH_Px_DIS_32PSK_3_4_FIELD    4
+
+#define STV090x_Px_MODCODLST4(__x)              (0xf4b4 - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLST4                   STV090x_Px_MODCODLST4(1)
+#define STV090x_P2_MODCODLST4                   STV090x_Px_MODCODLST4(2)
+#define STV090x_OFFST_Px_DIS_16PSK_9_10_FIELD   4
+#define STV090x_WIDTH_Px_DIS_16PSK_9_10_FIELD   4
+#define STV090x_OFFST_Px_DIS_16PSK_8_9_FIELD    0
+#define STV090x_WIDTH_Px_DIS_16PSK_8_9_FIELD    4
+
+#define STV090x_Px_MODCODLST5(__x)              (0xf4b5 - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLST5                   STV090x_Px_MODCODLST5(1)
+#define STV090x_P2_MODCODLST5                   STV090x_Px_MODCODLST5(2)
+#define STV090x_OFFST_Px_DIS_16PSK_5_6_FIELD    4
+#define STV090x_WIDTH_Px_DIS_16PSK_5_6_FIELD    4
+#define STV090x_OFFST_Px_DIS_16PSK_4_5_FIELD    0
+#define STV090x_WIDTH_Px_DIS_16PSK_4_5_FIELD    4
+
+#define STV090x_Px_MODCODLST6(__x)              (0xf4b6 - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLST6                   STV090x_Px_MODCODLST6(1)
+#define STV090x_P2_MODCODLST6                   STV090x_Px_MODCODLST6(2)
+#define STV090x_OFFST_Px_DIS_16PSK_3_4_FIELD    4
+#define STV090x_WIDTH_Px_DIS_16PSK_3_4_FIELD    4
+#define STV090x_OFFST_Px_DIS_16PSK_2_3_FIELD    0
+#define STV090x_WIDTH_Px_DIS_16PSK_2_3_FIELD    4
+
+#define STV090x_Px_MODCODLST7(__x)              (0xf4b7 - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLST7                   STV090x_Px_MODCODLST7(1)
+#define STV090x_P2_MODCODLST7                   STV090x_Px_MODCODLST7(2)
+#define STV090x_OFFST_Px_DIS_8P_9_10_FIELD      4
+#define STV090x_WIDTH_Px_DIS_8P_9_10_FIELD      4
+#define STV090x_OFFST_Px_DIS_8P_8_9_FIELD       0
+#define STV090x_WIDTH_Px_DIS_8P_8_9_FIELD       4
+
+#define STV090x_Px_MODCODLST8(__x)              (0xf4b8 - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLST8                   STV090x_Px_MODCODLST8(1)
+#define STV090x_P2_MODCODLST8                   STV090x_Px_MODCODLST8(2)
+#define STV090x_OFFST_Px_DIS_8P_5_6_FIELD       4
+#define STV090x_WIDTH_Px_DIS_8P_5_6_FIELD       4
+#define STV090x_OFFST_Px_DIS_8P_3_4_FIELD       0
+#define STV090x_WIDTH_Px_DIS_8P_3_4_FIELD       4
+
+#define STV090x_Px_MODCODLST9(__x)              (0xf4b9 - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLST9                   STV090x_Px_MODCODLST9(1)
+#define STV090x_P2_MODCODLST9                   STV090x_Px_MODCODLST9(2)
+#define STV090x_OFFST_Px_DIS_8P_2_3_FIELD       4
+#define STV090x_WIDTH_Px_DIS_8P_2_3_FIELD       4
+#define STV090x_OFFST_Px_DIS_8P_3_5_FIELD       0
+#define STV090x_WIDTH_Px_DIS_8P_3_5_FIELD       4
+
+#define STV090x_Px_MODCODLSTA(__x)              (0xf4ba - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLSTA                   STV090x_Px_MODCODLSTA(1)
+#define STV090x_P2_MODCODLSTA                   STV090x_Px_MODCODLSTA(2)
+#define STV090x_OFFST_Px_DIS_QP_9_10_FIELD      4
+#define STV090x_WIDTH_Px_DIS_QP_9_10_FIELD      4
+#define STV090x_OFFST_Px_DIS_QP_8_9_FIELD       0
+#define STV090x_WIDTH_Px_DIS_QP_8_9_FIELD       4
+
+#define STV090x_Px_MODCODLSTB(__x)              (0xf4bb - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLSTB                   STV090x_Px_MODCODLSTB(1)
+#define STV090x_P2_MODCODLSTB                   STV090x_Px_MODCODLSTB(2)
+#define STV090x_OFFST_Px_DIS_QP_5_6_FIELD       4
+#define STV090x_WIDTH_Px_DIS_QP_5_6_FIELD       4
+#define STV090x_OFFST_Px_DIS_QP_4_5_FIELD       0
+#define STV090x_WIDTH_Px_DIS_QP_4_5_FIELD       4
+
+#define STV090x_Px_MODCODLSTC(__x)              (0xf4bc - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLSTC                   STV090x_Px_MODCODLSTC(1)
+#define STV090x_P2_MODCODLSTC                   STV090x_Px_MODCODLSTC(2)
+#define STV090x_OFFST_Px_DIS_QP_3_4_FIELD       4
+#define STV090x_WIDTH_Px_DIS_QP_3_4_FIELD       4
+#define STV090x_OFFST_Px_DIS_QP_2_3_FIELD       0
+#define STV090x_WIDTH_Px_DIS_QP_2_3_FIELD       4
+
+#define STV090x_Px_MODCODLSTD(__x)              (0xf4bd - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLSTD                   STV090x_Px_MODCODLSTD(1)
+#define STV090x_P2_MODCODLSTD                   STV090x_Px_MODCODLSTD(2)
+#define STV090x_OFFST_Px_DIS_QP_3_5_FIELD       4
+#define STV090x_WIDTH_Px_DIS_QP_3_5_FIELD       4
+#define STV090x_OFFST_Px_DIS_QP_1_2_FIELD       0
+#define STV090x_WIDTH_Px_DIS_QP_1_2_FIELD       4
+
+#define STV090x_Px_MODCODLSTE(__x)              (0xf4be - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLSTE                   STV090x_Px_MODCODLSTE(1)
+#define STV090x_P2_MODCODLSTE                   STV090x_Px_MODCODLSTE(2)
+#define STV090x_OFFST_Px_DIS_QP_2_5_FIELD       4
+#define STV090x_WIDTH_Px_DIS_QP_2_5_FIELD       4
+#define STV090x_OFFST_Px_DIS_QP_1_3_FIELD       0
+#define STV090x_WIDTH_Px_DIS_QP_1_3_FIELD       4
+
+#define STV090x_Px_MODCODLSTF(__x)              (0xf4bf - (__x - 1) * 0x200)
+#define STV090x_P1_MODCODLSTF                   STV090x_Px_MODCODLSTF(1)
+#define STV090x_P2_MODCODLSTF                   STV090x_Px_MODCODLSTF(2)
+#define STV090x_OFFST_Px_DIS_QP_1_4_FIELD       4
+#define STV090x_WIDTH_Px_DIS_QP_1_4_FIELD       4
+
+#define STV090x_Px_GAUSSR0(__x)                 (0xf4c0 - (__x - 1) * 0x200)
+#define STV090x_P1_GAUSSR0                      STV090x_Px_GAUSSR0(1)
+#define STV090x_P2_GAUSSR0                      STV090x_Px_GAUSSR0(2)
+#define STV090x_OFFST_Px_EN_CCIMODE_FIELD       7
+#define STV090x_WIDTH_Px_EN_CCIMODE_FIELD       1
+#define STV090x_OFFST_Px_R0_GAUSSIEN_FIELD      0
+#define STV090x_WIDTH_Px_R0_GAUSSIEN_FIELD      7
+
+#define STV090x_Px_CCIR0(__x)                   (0xf4c1 - (__x - 1) * 0x200)
+#define STV090x_P1_CCIR0                        STV090x_Px_CCIR0(1)
+#define STV090x_P2_CCIR0                        STV090x_Px_CCIR0(2)
+#define STV090x_OFFST_Px_CCIDETECT_PLH_FIELD    7
+#define STV090x_WIDTH_Px_CCIDETECT_PLH_FIELD    1
+#define STV090x_OFFST_Px_R0_CCI_FIELD           0
+#define STV090x_WIDTH_Px_R0_CCI_FIELD           7
+
+#define STV090x_Px_CCIQUANT(__x)                (0xf4c2 - (__x - 1) * 0x200)
+#define STV090x_P1_CCIQUANT                     STV090x_Px_CCIQUANT(1)
+#define STV090x_P2_CCIQUANT                     STV090x_Px_CCIQUANT(2)
+#define STV090x_OFFST_Px_CCI_BETA_FIELD         5
+#define STV090x_WIDTH_Px_CCI_BETA_FIELD         3
+#define STV090x_OFFST_Px_CCI_QUANT_FIELD        0
+#define STV090x_WIDTH_Px_CCI_QUANT_FIELD        5
+
+#define STV090x_Px_CCITHRESH(__x)               (0xf4c3 - (__x - 1) * 0x200)
+#define STV090x_P1_CCITHRESH                    STV090x_Px_CCITHRESH(1)
+#define STV090x_P2_CCITHRESH                    STV090x_Px_CCITHRESH(2)
+#define STV090x_OFFST_Px_CCI_THRESHOLD_FIELD    0
+#define STV090x_WIDTH_Px_CCI_THRESHOLD_FIELD    8
+
+#define STV090x_Px_CCIACC(__x)                  (0xf4c4 - (__x - 1) * 0x200)
+#define STV090x_P1_CCIACC                       STV090x_Px_CCIACC(1)
+#define STV090x_P2_CCIACC                       STV090x_Px_CCIACC(1)
+#define STV090x_OFFST_Px_CCI_VALUE_FIELD        0
+#define STV090x_WIDTH_Px_CCI_VALUE_FIELD        8
+
+#define STV090x_Px_DMDRESCFG(__x)               (0xF4C6 - (__x - 1) * 0x200)
+#define STV090x_P1_DMDRESCFG                    STV090x_Px_DMDRESCFG(1)
+#define STV090x_P2_DMDRESCFG                    STV090x_Px_DMDRESCFG(2)
+#define STV090x_OFFST_Px_DMDRES_RESET_FIELD     7
+#define STV090x_WIDTH_Px_DMDRES_RESET_FIELD     1
+
+#define STV090x_Px_DMDRESADR(__x)               (0xF4C7 - (__x - 1) * 0x200)
+#define STV090x_P1_DMDRESADR                    STV090x_Px_DMDRESADR(1)
+#define STV090x_P2_DMDRESADR                    STV090x_Px_DMDRESADR(2)
+#define STV090x_OFFST_Px_DMDRES_RESNBR_FIELD    0
+#define STV090x_WIDTH_Px_DMDRES_RESNBR_FIELD    4
+
+#define STV090x_Px_DMDRESDATAy(__x, __y)        (0xF4C8 - (__x - 1) * 0x200 + (7 - __y))
+#define STV090x_P1_DMDRESDATA0                  STV090x_Px_DMDRESDATAy(1, 0)
+#define STV090x_P1_DMDRESDATA1                  STV090x_Px_DMDRESDATAy(1, 1)
+#define STV090x_P1_DMDRESDATA2                  STV090x_Px_DMDRESDATAy(1, 2)
+#define STV090x_P1_DMDRESDATA3                  STV090x_Px_DMDRESDATAy(1, 3)
+#define STV090x_P1_DMDRESDATA4                  STV090x_Px_DMDRESDATAy(1, 4)
+#define STV090x_P1_DMDRESDATA5                  STV090x_Px_DMDRESDATAy(1, 5)
+#define STV090x_P1_DMDRESDATA6                  STV090x_Px_DMDRESDATAy(1, 6)
+#define STV090x_P1_DMDRESDATA7                  STV090x_Px_DMDRESDATAy(1, 7)
+#define STV090x_P2_DMDRESDATA0                  STV090x_Px_DMDRESDATAy(2, 0)
+#define STV090x_P2_DMDRESDATA1                  STV090x_Px_DMDRESDATAy(2, 1)
+#define STV090x_P2_DMDRESDATA2                  STV090x_Px_DMDRESDATAy(2, 2)
+#define STV090x_P2_DMDRESDATA3                  STV090x_Px_DMDRESDATAy(2, 3)
+#define STV090x_P2_DMDRESDATA4                  STV090x_Px_DMDRESDATAy(2, 4)
+#define STV090x_P2_DMDRESDATA5                  STV090x_Px_DMDRESDATAy(2, 5)
+#define STV090x_P2_DMDRESDATA6                  STV090x_Px_DMDRESDATAy(2, 6)
+#define STV090x_P2_DMDRESDATA7                  STV090x_Px_DMDRESDATAy(2, 7)
+#define STV090x_OFFST_Px_DMDRES_DATA_FIELD      0
+#define STV090x_WIDTH_Px_DMDRES_DATA_FIELD      8
+
+#define STV090x_Px_FFEIy(__x, __y)              (0xf4d0 - (__x - 1) * 0x200 + 0x2 * (__y - 1))
+#define STV090x_P1_FFEI1                        STV090x_Px_FFEIy(1, 1)
+#define STV090x_P1_FFEI2                        STV090x_Px_FFEIy(1, 2)
+#define STV090x_P1_FFEI3                        STV090x_Px_FFEIy(1, 3)
+#define STV090x_P1_FFEI4                        STV090x_Px_FFEIy(1, 4)
+#define STV090x_P2_FFEI1                        STV090x_Px_FFEIy(2, 1)
+#define STV090x_P2_FFEI2                        STV090x_Px_FFEIy(2, 2)
+#define STV090x_P2_FFEI3                        STV090x_Px_FFEIy(2, 3)
+#define STV090x_P2_FFEI4                        STV090x_Px_FFEIy(2, 4)
+#define STV090x_OFFST_Px_FFE_ACCIy_FIELD        0
+#define STV090x_WIDTH_Px_FFE_ACCIy_FIELD        8
+
+#define STV090x_Px_FFEQy(__x, __y)              (0xf4d1 - (__x - 1) * 0x200 + 0x2 * (__y - 1))
+#define STV090x_P1_FFEQ1                        STV090x_Px_FFEQy(1, 1)
+#define STV090x_P1_FFEQ2                        STV090x_Px_FFEQy(1, 2)
+#define STV090x_P1_FFEQ3                        STV090x_Px_FFEQy(1, 3)
+#define STV090x_P1_FFEQ4                        STV090x_Px_FFEQy(1, 4)
+#define STV090x_P2_FFEQ1                        STV090x_Px_FFEQy(2, 1)
+#define STV090x_P2_FFEQ2                        STV090x_Px_FFEQy(2, 2)
+#define STV090x_P2_FFEQ3                        STV090x_Px_FFEQy(2, 3)
+#define STV090x_P2_FFEQ4                        STV090x_Px_FFEQy(2, 4)
+#define STV090x_OFFST_Px_FFE_ACCQy_FIELD        0
+#define STV090x_WIDTH_Px_FFE_ACCQy_FIELD        8
+
+#define STV090x_Px_FFECFG(__x)                  (0xf4d8 - (__x - 1) * 0x200)
+#define STV090x_P1_FFECFG                       STV090x_Px_FFECFG(1)
+#define STV090x_P2_FFECFG                       STV090x_Px_FFECFG(2)
+#define STV090x_OFFST_Px_EQUALFFE_ON_FIELD      6
+#define STV090x_WIDTH_Px_EQUALFFE_ON_FIELD      1
+
+#define STV090x_Px_SMAPCOEF7(__x)               (0xf500 - (__x - 1) * 0x200)
+#define STV090x_P1_SMAPCOEF7                    STV090x_Px_SMAPCOEF7(1)
+#define STV090x_P2_SMAPCOEF7                    STV090x_Px_SMAPCOEF7(2)
+#define STV090x_OFFST_Px_DIS_QSCALE_FIELD       7
+#define STV090x_WIDTH_Px_DIS_QSCALE_FIELD       1
+#define STV090x_OFFST_Px_SMAPCOEF_Q_LLR12_FIELD 0
+#define STV090x_WIDTH_Px_SMAPCOEF_Q_LLR12_FIELD 7
+
+#define STV090x_Px_SMAPCOEF6(__x)               (0xf501 - (__x - 1) * 0x200)
+#define STV090x_P1_SMAPCOEF6                    STV090x_Px_SMAPCOEF6(1)
+#define STV090x_P2_SMAPCOEF6                    STV090x_Px_SMAPCOEF6(2)
+#define STV090x_OFFST_Px_ADJ_8PSKLLR1_FIELD     2
+#define STV090x_WIDTH_Px_ADJ_8PSKLLR1_FIELD     1
+#define STV090x_OFFST_Px_OLD_8PSKLLR1_FIELD     1
+#define STV090x_WIDTH_Px_OLD_8PSKLLR1_FIELD     1
+#define STV090x_OFFST_Px_DIS_AB8PSK_FIELD       0
+#define STV090x_WIDTH_Px_DIS_AB8PSK_FIELD       1
+
+#define STV090x_Px_SMAPCOEF5(__x)                       (0xf502 - (__x - 1) * 0x200)
+#define STV090x_P1_SMAPCOEF5                            STV090x_Px_SMAPCOEF5(1)
+#define STV090x_P2_SMAPCOEF5                            STV090x_Px_SMAPCOEF5(2)
+#define STV090x_OFFST_Px_DIS_8SCALE_FIELD               7
+#define STV090x_WIDTH_Px_DIS_8SCALE_FIELD               1
+#define STV090x_OFFST_Px_SMAPCOEF_8P_LLR23_FIELD        0
+#define STV090x_WIDTH_Px_SMAPCOEF_8P_LLR23_FIELD        7
+
+#define STV090x_Px_DMDPLHSTAT(__x)              (0xF520 - (__x - 1) * 0x200)
+#define STV090x_P1_DMDPLHSTAT                   STV090x_Px_DMDPLHSTAT(1)
+#define STV090x_P2_DMDPLHSTAT                   STV090x_Px_DMDPLHSTAT(2)
+#define STV090x_OFFST_Px_PLH_STATISTIC_FIELD    0
+#define STV090x_WIDTH_Px_PLH_STATISTIC_FIELD    8
+
+#define STV090x_Px_LOCKTIMEy(__x, __y)          (0xF525 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_LOCKTIME0                    STV090x_Px_LOCKTIMEy(1, 0)
+#define STV090x_P1_LOCKTIME1                    STV090x_Px_LOCKTIMEy(1, 1)
+#define STV090x_P1_LOCKTIME2                    STV090x_Px_LOCKTIMEy(1, 2)
+#define STV090x_P1_LOCKTIME3                    STV090x_Px_LOCKTIMEy(1, 3)
+#define STV090x_P2_LOCKTIME0                    STV090x_Px_LOCKTIMEy(2, 0)
+#define STV090x_P2_LOCKTIME1                    STV090x_Px_LOCKTIMEy(2, 1)
+#define STV090x_P2_LOCKTIME2                    STV090x_Px_LOCKTIMEy(2, 2)
+#define STV090x_P2_LOCKTIME3                    STV090x_Px_LOCKTIMEy(2, 3)
+#define STV090x_OFFST_Px_DEMOD_LOCKTIME_FIELD   0
+#define STV090x_WIDTH_Px_DEMOD_LOCKTIME_FIELD   8
+
+#define STV090x_Px_TNRCFG(__x)                  (0xf4e0 - (__x - 1) * 0x200) /* check */
+#define STV090x_P1_TNRCFG                       STV090x_Px_TNRCFG(1)
+#define STV090x_P2_TNRCFG                       STV090x_Px_TNRCFG(2)
+
+#define STV090x_Px_TNRCFG2(__x)                 (0xf4e1 - (__x - 1) * 0x200)
+#define STV090x_P1_TNRCFG2                      STV090x_Px_TNRCFG2(1)
+#define STV090x_P2_TNRCFG2                      STV090x_Px_TNRCFG2(2)
+#define STV090x_OFFST_Px_TUN_IQSWAP_FIELD       7
+#define STV090x_WIDTH_Px_TUN_IQSWAP_FIELD       1
+
+#define STV090x_Px_VITSCALE(__x)                (0xf532 - (__x - 1) * 0x200)
+#define STV090x_P1_VITSCALE                     STV090x_Px_VITSCALE(1)
+#define STV090x_P2_VITSCALE                     STV090x_Px_VITSCALE(2)
+#define STV090x_OFFST_Px_NVTH_NOSRANGE_FIELD    7
+#define STV090x_WIDTH_Px_NVTH_NOSRANGE_FIELD    1
+#define STV090x_OFFST_Px_VERROR_MAXMODE_FIELD   6
+#define STV090x_WIDTH_Px_VERROR_MAXMODE_FIELD   1
+#define STV090x_OFFST_Px_NSLOWSN_LOCKED_FIELD   3
+#define STV090x_WIDTH_Px_NSLOWSN_LOCKED_FIELD   1
+#define STV090x_OFFST_Px_DIS_RSFLOCK_FIELD      1
+#define STV090x_WIDTH_Px_DIS_RSFLOCK_FIELD      1
+
+#define STV090x_Px_FECM(__x)                    (0xf533 - (__x - 1) * 0x200)
+#define STV090x_P1_FECM                         STV090x_Px_FECM(1)
+#define STV090x_P2_FECM                         STV090x_Px_FECM(2)
+#define STV090x_OFFST_Px_DSS_DVB_FIELD          7
+#define STV090x_WIDTH_Px_DSS_DVB_FIELD          1
+#define STV090x_OFFST_Px_DSS_SRCH_FIELD         4
+#define STV090x_WIDTH_Px_DSS_SRCH_FIELD         1
+#define STV090x_OFFST_Px_SYNCVIT_FIELD          1
+#define STV090x_WIDTH_Px_SYNCVIT_FIELD          1
+#define STV090x_OFFST_Px_IQINV_FIELD            0
+#define STV090x_WIDTH_Px_IQINV_FIELD            1
+
+#define STV090x_Px_VTH12(__x)                   (0xf534 - (__x - 1) * 0x200)
+#define STV090x_P1_VTH12                        STV090x_Px_VTH12(1)
+#define STV090x_P2_VTH12                        STV090x_Px_VTH12(2)
+#define STV090x_OFFST_Px_VTH12_FIELD            0
+#define STV090x_WIDTH_Px_VTH12_FIELD            8
+
+#define STV090x_Px_VTH23(__x)                   (0xf535 - (__x - 1) * 0x200)
+#define STV090x_P1_VTH23                        STV090x_Px_VTH23(1)
+#define STV090x_P2_VTH23                        STV090x_Px_VTH23(2)
+#define STV090x_OFFST_Px_VTH23_FIELD            0
+#define STV090x_WIDTH_Px_VTH23_FIELD            8
+
+#define STV090x_Px_VTH34(__x)                   (0xf536 - (__x - 1) * 0x200)
+#define STV090x_P1_VTH34                        STV090x_Px_VTH34(1)
+#define STV090x_P2_VTH34                        STV090x_Px_VTH34(2)
+#define STV090x_OFFST_Px_VTH34_FIELD            0
+#define STV090x_WIDTH_Px_VTH34_FIELD            8
+
+#define STV090x_Px_VTH56(__x)                   (0xf537 - (__x - 1) * 0x200)
+#define STV090x_P1_VTH56                        STV090x_Px_VTH56(1)
+#define STV090x_P2_VTH56                        STV090x_Px_VTH56(2)
+#define STV090x_OFFST_Px_VTH56_FIELD            0
+#define STV090x_WIDTH_Px_VTH56_FIELD            8
+
+#define STV090x_Px_VTH67(__x)                   (0xf538 - (__x - 1) * 0x200)
+#define STV090x_P1_VTH67                        STV090x_Px_VTH67(1)
+#define STV090x_P2_VTH67                        STV090x_Px_VTH67(2)
+#define STV090x_OFFST_Px_VTH67_FIELD            0
+#define STV090x_WIDTH_Px_VTH67_FIELD            8
+
+#define STV090x_Px_VTH78(__x)                   (0xf539 - (__x - 1) * 0x200)
+#define STV090x_P1_VTH78                        STV090x_Px_VTH78(1)
+#define STV090x_P2_VTH78                        STV090x_Px_VTH78(2)
+#define STV090x_OFFST_Px_VTH78_FIELD            0
+#define STV090x_WIDTH_Px_VTH78_FIELD            8
+
+#define STV090x_Px_VITCURPUN(__x)               (0xf53a - (__x - 1) * 0x200)
+#define STV090x_P1_VITCURPUN                    STV090x_Px_VITCURPUN(1)
+#define STV090x_P2_VITCURPUN                    STV090x_Px_VITCURPUN(2)
+#define STV090x_OFFST_Px_VIT_CURPUN_FIELD       0
+#define STV090x_WIDTH_Px_VIT_CURPUN_FIELD       5
+
+#define STV090x_Px_VERROR(__x)                  (0xf53b - (__x - 1) * 0x200)
+#define STV090x_P1_VERROR                       STV090x_Px_VERROR(1)
+#define STV090x_P2_VERROR                       STV090x_Px_VERROR(2)
+#define STV090x_OFFST_Px_REGERR_VIT_FIELD       0
+#define STV090x_WIDTH_Px_REGERR_VIT_FIELD       8
+
+#define STV090x_Px_PRVIT(__x)                   (0xf53c - (__x - 1) * 0x200)
+#define STV090x_P1_PRVIT                        STV090x_Px_PRVIT(1)
+#define STV090x_P2_PRVIT                        STV090x_Px_PRVIT(2)
+#define STV090x_OFFST_Px_DIS_VTHLOCK_FIELD      6
+#define STV090x_WIDTH_Px_DIS_VTHLOCK_FIELD      1
+#define STV090x_OFFST_Px_E7_8VIT_FIELD          5
+#define STV090x_WIDTH_Px_E7_8VIT_FIELD          1
+#define STV090x_OFFST_Px_E6_7VIT_FIELD          4
+#define STV090x_WIDTH_Px_E6_7VIT_FIELD          1
+#define STV090x_OFFST_Px_E5_6VIT_FIELD          3
+#define STV090x_WIDTH_Px_E5_6VIT_FIELD          1
+#define STV090x_OFFST_Px_E3_4VIT_FIELD          2
+#define STV090x_WIDTH_Px_E3_4VIT_FIELD          1
+#define STV090x_OFFST_Px_E2_3VIT_FIELD          1
+#define STV090x_WIDTH_Px_E2_3VIT_FIELD          1
+#define STV090x_OFFST_Px_E1_2VIT_FIELD          0
+#define STV090x_WIDTH_Px_E1_2VIT_FIELD          1
+
+#define STV090x_Px_VAVSRVIT(__x)                (0xf53d - (__x - 1) * 0x200)
+#define STV090x_P1_VAVSRVIT                     STV090x_Px_VAVSRVIT(1)
+#define STV090x_P2_VAVSRVIT                     STV090x_Px_VAVSRVIT(2)
+#define STV090x_OFFST_Px_SNVIT_FIELD            4
+#define STV090x_WIDTH_Px_SNVIT_FIELD            2
+#define STV090x_OFFST_Px_TOVVIT_FIELD           2
+#define STV090x_WIDTH_Px_TOVVIT_FIELD           2
+#define STV090x_OFFST_Px_HYPVIT_FIELD           0
+#define STV090x_WIDTH_Px_HYPVIT_FIELD           2
+
+#define STV090x_Px_VSTATUSVIT(__x)              (0xf53e - (__x - 1) * 0x200)
+#define STV090x_P1_VSTATUSVIT                   STV090x_Px_VSTATUSVIT(1)
+#define STV090x_P2_VSTATUSVIT                   STV090x_Px_VSTATUSVIT(2)
+#define STV090x_OFFST_Px_PRFVIT_FIELD           4
+#define STV090x_WIDTH_Px_PRFVIT_FIELD           1
+#define STV090x_OFFST_Px_LOCKEDVIT_FIELD        3
+#define STV090x_WIDTH_Px_LOCKEDVIT_FIELD        1
+
+#define STV090x_Px_VTHINUSE(__x)                (0xf53f - (__x - 1) * 0x200)
+#define STV090x_P1_VTHINUSE                     STV090x_Px_VTHINUSE(1)
+#define STV090x_P2_VTHINUSE                     STV090x_Px_VTHINUSE(2)
+#define STV090x_OFFST_Px_VIT_INUSE_FIELD        0
+#define STV090x_WIDTH_Px_VIT_INUSE_FIELD        8
+
+#define STV090x_Px_KDIV12(__x)                  (0xf540 - (__x - 1) * 0x200)
+#define STV090x_P1_KDIV12                       STV090x_Px_KDIV12(1)
+#define STV090x_P2_KDIV12                       STV090x_Px_KDIV12(2)
+#define STV090x_OFFST_Px_K_DIVIDER_12_FIELD     0
+#define STV090x_WIDTH_Px_K_DIVIDER_12_FIELD     7
+
+#define STV090x_Px_KDIV23(__x)                  (0xf541 - (__x - 1) * 0x200)
+#define STV090x_P1_KDIV23                       STV090x_Px_KDIV23(1)
+#define STV090x_P2_KDIV23                       STV090x_Px_KDIV23(2)
+#define STV090x_OFFST_Px_K_DIVIDER_23_FIELD     0
+#define STV090x_WIDTH_Px_K_DIVIDER_23_FIELD     7
+
+#define STV090x_Px_KDIV34(__x)                  (0xf542 - (__x - 1) * 0x200)
+#define STV090x_P1_KDIV34                       STV090x_Px_KDIV34(1)
+#define STV090x_P2_KDIV34                       STV090x_Px_KDIV34(2)
+#define STV090x_OFFST_Px_K_DIVIDER_34_FIELD     0
+#define STV090x_WIDTH_Px_K_DIVIDER_34_FIELD     7
+
+#define STV090x_Px_KDIV56(__x)                  (0xf543 - (__x - 1) * 0x200)
+#define STV090x_P1_KDIV56                       STV090x_Px_KDIV56(1)
+#define STV090x_P2_KDIV56                       STV090x_Px_KDIV56(2)
+#define STV090x_OFFST_Px_K_DIVIDER_56_FIELD     0
+#define STV090x_WIDTH_Px_K_DIVIDER_56_FIELD     7
+
+#define STV090x_Px_KDIV67(__x)                  (0xf544 - (__x - 1) * 0x200)
+#define STV090x_P1_KDIV67                       STV090x_Px_KDIV67(1)
+#define STV090x_P2_KDIV67                       STV090x_Px_KDIV67(2)
+#define STV090x_OFFST_Px_K_DIVIDER_67_FIELD     0
+#define STV090x_WIDTH_Px_K_DIVIDER_67_FIELD     7
+
+#define STV090x_Px_KDIV78(__x)                  (0xf545 - (__x - 1) * 0x200)
+#define STV090x_P1_KDIV78                       STV090x_Px_KDIV78(1)
+#define STV090x_P2_KDIV78                       STV090x_Px_KDIV78(2)
+#define STV090x_OFFST_Px_K_DIVIDER_78_FIELD     0
+#define STV090x_WIDTH_Px_K_DIVIDER_78_FIELD     7
+
+#define STV090x_Px_PDELCTRL1(__x)               (0xf550 - (__x - 1) * 0x200)
+#define STV090x_P1_PDELCTRL1                    STV090x_Px_PDELCTRL1(1)
+#define STV090x_P2_PDELCTRL1                    STV090x_Px_PDELCTRL1(2)
+#define STV090x_OFFST_Px_INV_MISMASK_FIELD      7
+#define STV090x_WIDTH_Px_INV_MISMASK_FIELD      1
+#define STV090x_OFFST_Px_FILTER_EN_FIELD        5
+#define STV090x_WIDTH_Px_FILTER_EN_FIELD        1
+#define STV090x_OFFST_Px_EN_MIS00_FIELD         1
+#define STV090x_WIDTH_Px_EN_MIS00_FIELD         1
+#define STV090x_OFFST_Px_ALGOSWRST_FIELD        0
+#define STV090x_WIDTH_Px_ALGOSWRST_FIELD        1
+
+#define STV090x_Px_PDELCTRL2(__x)               (0xf551 - (__x - 1) * 0x200)
+#define STV090x_P1_PDELCTRL2                    STV090x_Px_PDELCTRL2(1)
+#define STV090x_P2_PDELCTRL2                    STV090x_Px_PDELCTRL2(2)
+#define STV090x_OFFST_Px_FORCE_CONTINUOUS       7
+#define STV090x_WIDTH_Px_FORCE_CONTINUOUS       1
+#define STV090x_OFFST_Px_RESET_UPKO_COUNT       6
+#define STV090x_WIDTH_Px_RESET_UPKO_COUNT       1
+#define STV090x_OFFST_Px_USER_PKTDELIN_NB       5
+#define STV090x_WIDTH_Px_USER_PKTDELIN_NB       1
+#define STV090x_OFFST_Px_FORCE_LOCKED           4
+#define STV090x_WIDTH_Px_FORCE_LOCKED           1
+#define STV090x_OFFST_Px_DATA_UNBBSCRAM         3
+#define STV090x_WIDTH_Px_DATA_UNBBSCRAM         1
+#define STV090x_OFFST_Px_FORCE_LONGPACKET       2
+#define STV090x_WIDTH_Px_FORCE_LONGPACKET       1
+#define STV090x_OFFST_Px_FRAME_MODE_FIELD       1
+#define STV090x_WIDTH_Px_FRAME_MODE_FIELD       1
+
+#define STV090x_Px_HYSTTHRESH(__x)              (0xf554 - (__x - 1) * 0x200)
+#define STV090x_P1_HYSTTHRESH                   STV090x_Px_HYSTTHRESH(1)
+#define STV090x_P2_HYSTTHRESH                   STV090x_Px_HYSTTHRESH(2)
+#define STV090x_OFFST_Px_UNLCK_THRESH_FIELD     4
+#define STV090x_WIDTH_Px_UNLCK_THRESH_FIELD     4
+#define STV090x_OFFST_Px_DELIN_LCK_THRESH_FIELD 0
+#define STV090x_WIDTH_Px_DELIN_LCK_THRESH_FIELD 4
+
+#define STV090x_Px_ISIENTRY(__x)                (0xf55e - (__x - 1) * 0x200)
+#define STV090x_P1_ISIENTRY                     STV090x_Px_ISIENTRY(1)
+#define STV090x_P2_ISIENTRY                     STV090x_Px_ISIENTRY(2)
+#define STV090x_OFFST_Px_ISI_ENTRY_FIELD        0
+#define STV090x_WIDTH_Px_ISI_ENTRY_FIELD        8
+
+#define STV090x_Px_ISIBITENA(__x)               (0xf55f - (__x - 1) * 0x200)
+#define STV090x_P1_ISIBITENA                    STV090x_Px_ISIBITENA(1)
+#define STV090x_P2_ISIBITENA                    STV090x_Px_ISIBITENA(2)
+#define STV090x_OFFST_Px_ISI_BIT_EN_FIELD       0
+#define STV090x_WIDTH_Px_ISI_BIT_EN_FIELD       8
+
+#define STV090x_Px_MATSTRy(__x, __y)            (0xf561 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_MATSTR0                      STV090x_Px_MATSTRy(1, 0)
+#define STV090x_P1_MATSTR1                      STV090x_Px_MATSTRy(1, 1)
+#define STV090x_P2_MATSTR0                      STV090x_Px_MATSTRy(2, 0)
+#define STV090x_P2_MATSTR1                      STV090x_Px_MATSTRy(2, 1)
+#define STV090x_OFFST_Px_MATYPE_CURRENT_FIELD   0
+#define STV090x_WIDTH_Px_MATYPE_CURRENT_FIELD   8
+
+#define STV090x_Px_UPLSTRy(__x, __y)            (0xf563 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_UPLSTR0                      STV090x_Px_UPLSTRy(1, 0)
+#define STV090x_P1_UPLSTR1                      STV090x_Px_UPLSTRy(1, 1)
+#define STV090x_P2_UPLSTR0                      STV090x_Px_UPLSTRy(2, 0)
+#define STV090x_P2_UPLSTR1                      STV090x_Px_UPLSTRy(2, 1)
+#define STV090x_OFFST_Px_UPL_CURRENT_FIELD      0
+#define STV090x_WIDTH_Px_UPL_CURRENT_FIELD      8
+
+#define STV090x_Px_DFLSTRy(__x, __y)            (0xf565 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_DFLSTR0                      STV090x_Px_DFLSTRy(1, 0)
+#define STV090x_P1_DFLSTR1                      STV090x_Px_DFLSTRy(1, 1)
+#define STV090x_P2_DFLSTR0                      STV090x_Px_DFLSTRy(2, 0)
+#define STV090x_P2_DFLSTR1                      STV090x_Px_DFLSTRy(2, 1)
+#define STV090x_OFFST_Px_DFL_CURRENT_FIELD      0
+#define STV090x_WIDTH_Px_DFL_CURRENT_FIELD      8
+
+#define STV090x_Px_SYNCSTR(__x)                 (0xf566 - (__x - 1) * 0x200)
+#define STV090x_P1_SYNCSTR                      STV090x_Px_SYNCSTR(1)
+#define STV090x_P2_SYNCSTR                      STV090x_Px_SYNCSTR(2)
+#define STV090x_OFFST_Px_SYNC_CURRENT_FIELD     0
+#define STV090x_WIDTH_Px_SYNC_CURRENT_FIELD     8
+
+#define STV090x_Px_SYNCDSTRy(__x, __y)          (0xf568 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_SYNCDSTR0                    STV090x_Px_SYNCDSTRy(1, 0)
+#define STV090x_P1_SYNCDSTR1                    STV090x_Px_SYNCDSTRy(1, 1)
+#define STV090x_P2_SYNCDSTR0                    STV090x_Px_SYNCDSTRy(2, 0)
+#define STV090x_P2_SYNCDSTR1                    STV090x_Px_SYNCDSTRy(2, 1)
+#define STV090x_OFFST_Px_SYNCD_CURRENT_FIELD    0
+#define STV090x_WIDTH_Px_SYNCD_CURRENT_FIELD    8
+
+#define STV090x_Px_PDELSTATUS1(__x)             (0xf569 - (__x - 1) * 0x200)
+#define STV090x_P1_PDELSTATUS1                  STV090x_Px_PDELSTATUS1(1)
+#define STV090x_P2_PDELSTATUS1                  STV090x_Px_PDELSTATUS1(2)
+#define STV090x_OFFST_Px_PKTDELIN_LOCK_FIELD    1
+#define STV090x_WIDTH_Px_PKTDELIN_LOCK_FIELD    1
+#define STV090x_OFFST_Px_FIRST_LOCK_FIELD       0
+#define STV090x_WIDTH_Px_FIRST_LOCK_FIELD       1
+
+#define STV090x_Px_PDELSTATUS2(__x)             (0xf56a - (__x - 1) * 0x200)
+#define STV090x_P1_PDELSTATUS2                  STV090x_Px_PDELSTATUS2(1)
+#define STV090x_P2_PDELSTATUS2                  STV090x_Px_PDELSTATUS2(2)
+#define STV090x_OFFST_Px_FRAME_MODCOD_FIELD     2
+#define STV090x_WIDTH_Px_FRAME_MODCOD_FIELD     5
+#define STV090x_OFFST_Px_FRAME_TYPE_FIELD       0
+#define STV090x_WIDTH_Px_FRAME_TYPE_FIELD       2
+
+#define STV090x_Px_BBFCRCKO1(__x)               (0xf56b - (__x - 1) * 0x200)
+#define STV090x_P1_BBFCRCKO1                    STV090x_Px_BBFCRCKO1(1)
+#define STV090x_P2_BBFCRCKO1                    STV090x_Px_BBFCRCKO1(2)
+#define STV090x_OFFST_Px_BBHCRC_KOCNT_FIELD     0
+#define STV090x_WIDTH_Px_BBHCRC_KOCNT_FIELD     8
+
+#define STV090x_Px_BBFCRCKO0(__x)               (0xf56c - (__x - 1) * 0x200)
+#define STV090x_P1_BBFCRCKO0                    STV090x_Px_BBFCRCKO0(1)
+#define STV090x_P2_BBFCRCKO0                    STV090x_Px_BBFCRCKO0(2)
+#define STV090x_OFFST_Px_BBHCRC_KOCNT_FIELD     0
+#define STV090x_WIDTH_Px_BBHCRC_KOCNT_FIELD     8
+
+#define STV090x_Px_UPCRCKO1(__x)                (0xf56d - (__x - 1) * 0x200)
+#define STV090x_P1_UPCRCKO1                     STV090x_Px_UPCRCKO1(1)
+#define STV090x_P2_UPCRCKO1                     STV090x_Px_UPCRCKO1(2)
+#define STV090x_OFFST_Px_PKTCRC_KOCNT_FIELD     0
+#define STV090x_WIDTH_Px_PKTCRC_KOCNT_FIELD     8
+
+#define STV090x_Px_UPCRCKO0(__x)                (0xf56e - (__x - 1) * 0x200)
+#define STV090x_P1_UPCRCKO0                     STV090x_Px_UPCRCKO0(1)
+#define STV090x_P2_UPCRCKO0                     STV090x_Px_UPCRCKO0(2)
+#define STV090x_OFFST_Px_PKTCRC_KOCNT_FIELD     0
+#define STV090x_WIDTH_Px_PKTCRC_KOCNT_FIELD     8
+
+#define STV090x_NBITER_NFx(__x)                         (0xFA03 + (__x - 4) * 0x1)
+#define STV090x_NBITER_NF4                              STV090x_NBITER_NFx(4)
+#define STV090x_NBITER_NF5                              STV090x_NBITER_NFx(5)
+#define STV090x_NBITER_NF6                              STV090x_NBITER_NFx(6)
+#define STV090x_NBITER_NF7                              STV090x_NBITER_NFx(7)
+#define STV090x_NBITER_NF8                              STV090x_NBITER_NFx(8)
+#define STV090x_NBITER_NF9                              STV090x_NBITER_NFx(9)
+#define STV090x_NBITER_NF10                             STV090x_NBITER_NFx(10)
+#define STV090x_NBITER_NF11                             STV090x_NBITER_NFx(11)
+#define STV090x_NBITER_NF12                             STV090x_NBITER_NFx(12)
+#define STV090x_NBITER_NF13                             STV090x_NBITER_NFx(13)
+#define STV090x_NBITER_NF14                             STV090x_NBITER_NFx(14)
+#define STV090x_NBITER_NF15                             STV090x_NBITER_NFx(15)
+#define STV090x_NBITER_NF16                             STV090x_NBITER_NFx(16)
+#define STV090x_NBITER_NF17                             STV090x_NBITER_NFx(17)
+
+#define STV090x_NBITERNOERR                             0xFA3F
+#define STV090x_OFFST_NBITER_STOP_CRIT_FIELD            0
+#define STV090x_WIDTH_NBITER_STOP_CRIT_FIELD            4
+
+#define STV090x_GAINLLR_NFx(__x)                        (0xFA43 + (__x - 4) * 0x1)
+#define STV090x_GAINLLR_NF4                             STV090x_GAINLLR_NFx(4)
+#define STV090x_OFFST_GAINLLR_NF_QP_1_2_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_QP_1_2_FIELD           7
+
+#define STV090x_GAINLLR_NF5                             STV090x_GAINLLR_NFx(5)
+#define STV090x_OFFST_GAINLLR_NF_QP_3_5_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_QP_3_5_FIELD           7
+
+#define STV090x_GAINLLR_NF6                             STV090x_GAINLLR_NFx(6)
+#define STV090x_OFFST_GAINLLR_NF_QP_2_3_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_QP_2_3_FIELD           7
+
+#define STV090x_GAINLLR_NF7                             STV090x_GAINLLR_NFx(7)
+#define STV090x_OFFST_GAINLLR_NF_QP_3_4_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_QP_3_4_FIELD           7
+
+#define STV090x_GAINLLR_NF8                             STV090x_GAINLLR_NFx(8)
+#define STV090x_OFFST_GAINLLR_NF_QP_4_5_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_QP_4_5_FIELD           7
+
+#define STV090x_GAINLLR_NF9                             STV090x_GAINLLR_NFx(9)
+#define STV090x_OFFST_GAINLLR_NF_QP_5_6_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_QP_5_6_FIELD           7
+
+#define STV090x_GAINLLR_NF10                            STV090x_GAINLLR_NFx(10)
+#define STV090x_OFFST_GAINLLR_NF_QP_8_9_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_QP_8_9_FIELD           7
+
+#define STV090x_GAINLLR_NF11                            STV090x_GAINLLR_NFx(11)
+#define STV090x_OFFST_GAINLLR_NF_QP_9_10_FIELD          0
+#define STV090x_WIDTH_GAINLLR_NF_QP_9_10_FIELD          7
+
+#define STV090x_GAINLLR_NF12                            STV090x_GAINLLR_NFx(12)
+#define STV090x_OFFST_GAINLLR_NF_8P_3_5_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_8P_3_5_FIELD           7
+
+#define STV090x_GAINLLR_NF13                            STV090x_GAINLLR_NFx(13)
+#define STV090x_OFFST_GAINLLR_NF_8P_2_3_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_8P_2_3_FIELD           7
+
+#define STV090x_GAINLLR_NF14                            STV090x_GAINLLR_NFx(14)
+#define STV090x_OFFST_GAINLLR_NF_8P_3_4_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_8P_3_4_FIELD           7
+
+#define STV090x_GAINLLR_NF15                            STV090x_GAINLLR_NFx(15)
+#define STV090x_OFFST_GAINLLR_NF_8P_5_6_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_8P_5_6_FIELD           7
+
+#define STV090x_GAINLLR_NF16                            STV090x_GAINLLR_NFx(16)
+#define STV090x_OFFST_GAINLLR_NF_8P_8_9_FIELD           0
+#define STV090x_WIDTH_GAINLLR_NF_8P_8_9_FIELD           7
+
+#define STV090x_GAINLLR_NF17                            STV090x_GAINLLR_NFx(17)
+#define STV090x_OFFST_GAINLLR_NF_8P_9_10_FIELD          0
+#define STV090x_WIDTH_GAINLLR_NF_8P_9_10_FIELD          7
+
+#define STV090x_GENCFG                                  0xFA86
+#define STV090x_OFFST_BROADCAST_FIELD                   4
+#define STV090x_WIDTH_BROADCAST_FIELD                   1
+#define STV090x_OFFST_PRIORITY_FIELD                    1
+#define STV090x_WIDTH_PRIORITY_FIELD                    1
+#define STV090x_OFFST_DDEMOD_FIELD                      0
+#define STV090x_WIDTH_DDEMOD_FIELD                      1
+
+#define STV090x_LDPCERRx(__x)                           (0xFA97 - (__x  * 0x1))
+#define STV090x_LDPCERR0                                STV090x_LDPCERRx(0)
+#define STV090x_LDPCERR1                                STV090x_LDPCERRx(1)
+#define STV090x_OFFST_Px_LDPC_ERRORS_COUNTER_FIELD      0
+#define STV090x_WIDTH_Px_LDPC_ERRORS_COUNTER_FIELD      8
+
+#define STV090x_BCHERR                                  0xFA98
+#define STV090x_OFFST_Px_ERRORFLAG_FIELD                4
+#define STV090x_WIDTH_Px_ERRORFLAG_FIELD                1
+#define STV090x_OFFST_Px_BCH_ERRORS_COUNTER_FIELD       0
+#define STV090x_WIDTH_Px_BCH_ERRORS_COUNTER_FIELD       4
+
+#define STV090x_Px_TSSTATEM(__x)                        (0xF570 - (__x - 1) * 0x200)
+#define STV090x_P1_TSSTATEM                             STV090x_Px_TSSTATEM(1)
+#define STV090x_P2_TSSTATEM                             STV090x_Px_TSSTATEM(2)
+#define STV090x_OFFST_Px_TSDIL_ON_FIELD                 7
+#define STV090x_WIDTH_Px_TSDIL_ON_FIELD                 1
+#define STV090x_OFFST_Px_TSRS_ON_FIELD                  5
+#define STV090x_WIDTH_Px_TSRS_ON_FIELD                  1
+
+#define STV090x_Px_TSCFGH(__x)                          (0xF572 - (__x - 1) * 0x200)
+#define STV090x_P1_TSCFGH                               STV090x_Px_TSCFGH(1)
+#define STV090x_P2_TSCFGH                               STV090x_Px_TSCFGH(2)
+#define STV090x_OFFST_Px_TSFIFO_DVBCI_FIELD             7
+#define STV090x_WIDTH_Px_TSFIFO_DVBCI_FIELD             1
+#define STV090x_OFFST_Px_TSFIFO_SERIAL_FIELD            6
+#define STV090x_WIDTH_Px_TSFIFO_SERIAL_FIELD            1
+#define STV090x_OFFST_Px_TSFIFO_TEIUPDATE_FIELD         5
+#define STV090x_WIDTH_Px_TSFIFO_TEIUPDATE_FIELD         1
+#define STV090x_OFFST_Px_TSFIFO_DUTY50_FIELD            4
+#define STV090x_WIDTH_Px_TSFIFO_DUTY50_FIELD            1
+#define STV090x_OFFST_Px_TSFIFO_HSGNLOUT_FIELD          3
+#define STV090x_WIDTH_Px_TSFIFO_HSGNLOUT_FIELD          1
+#define STV090x_OFFST_Px_TSFIFO_ERRORMODE_FIELD         1
+#define STV090x_WIDTH_Px_TSFIFO_ERRORMODE_FIELD         2
+#define STV090x_OFFST_Px_RST_HWARE_FIELD                0
+#define STV090x_WIDTH_Px_RST_HWARE_FIELD                1
+
+#define STV090x_Px_TSCFGM(__x)                          (0xF573 - (__x - 1) * 0x200)
+#define STV090x_P1_TSCFGM                               STV090x_Px_TSCFGM(1)
+#define STV090x_P2_TSCFGM                               STV090x_Px_TSCFGM(2)
+#define STV090x_OFFST_Px_TSFIFO_MANSPEED_FIELD          6
+#define STV090x_WIDTH_Px_TSFIFO_MANSPEED_FIELD          2
+#define STV090x_OFFST_Px_TSFIFO_PERMDATA_FIELD          5
+#define STV090x_WIDTH_Px_TSFIFO_PERMDATA_FIELD          1
+#define STV090x_OFFST_Px_TSFIFO_INVDATA_FIELD           0
+#define STV090x_WIDTH_Px_TSFIFO_INVDATA_FIELD           1
+
+#define STV090x_Px_TSCFGL(__x)                          (0xF574 - (__x - 1) * 0x200)
+#define STV090x_P1_TSCFGL                               STV090x_Px_TSCFGL(1)
+#define STV090x_P2_TSCFGL                               STV090x_Px_TSCFGL(2)
+#define STV090x_OFFST_Px_TSFIFO_BCLKDEL1CK_FIELD        6
+#define STV090x_WIDTH_Px_TSFIFO_BCLKDEL1CK_FIELD        2
+#define STV090x_OFFST_Px_BCHERROR_MODE_FIELD            4
+#define STV090x_WIDTH_Px_BCHERROR_MODE_FIELD            2
+#define STV090x_OFFST_Px_TSFIFO_NSGNL2DATA_FIELD        3
+#define STV090x_WIDTH_Px_TSFIFO_NSGNL2DATA_FIELD        1
+#define STV090x_OFFST_Px_TSFIFO_EMBINDVB_FIELD          2
+#define STV090x_WIDTH_Px_TSFIFO_EMBINDVB_FIELD          1
+#define STV090x_OFFST_Px_TSFIFO_DPUNACT_FIELD           1
+#define STV090x_WIDTH_Px_TSFIFO_DPUNACT_FIELD           1
+
+#define STV090x_Px_TSINSDELH(__x)                       (0xF576 - (__x - 1) * 0x200)
+#define STV090x_P1_TSINSDELH                            STV090x_Px_TSINSDELH(1)
+#define STV090x_P2_TSINSDELH                            STV090x_Px_TSINSDELH(2)
+#define STV090x_OFFST_Px_TSDEL_SYNCBYTE_FIELD           7
+#define STV090x_WIDTH_Px_TSDEL_SYNCBYTE_FIELD           1
+#define STV090x_OFFST_Px_TSDEL_XXHEADER_FIELD           6
+#define STV090x_WIDTH_Px_TSDEL_XXHEADER_FIELD           1
+
+#define STV090x_Px_TSSPEED(__x)                         (0xF580 - (__x - 1) * 0x200)
+#define STV090x_P1_TSSPEED                              STV090x_Px_TSSPEED(1)
+#define STV090x_P2_TSSPEED                              STV090x_Px_TSSPEED(2)
+#define STV090x_OFFST_Px_TSFIFO_OUTSPEED_FIELD          0
+#define STV090x_WIDTH_Px_TSFIFO_OUTSPEED_FIELD          8
+
+#define STV090x_Px_TSSTATUS(__x)                        (0xF581 - (__x - 1) * 0x200)
+#define STV090x_P1_TSSTATUS                             STV090x_Px_TSSTATUS(1)
+#define STV090x_P2_TSSTATUS                             STV090x_Px_TSSTATUS(2)
+#define STV090x_OFFST_Px_TSFIFO_LINEOK_FIELD            7
+#define STV090x_WIDTH_Px_TSFIFO_LINEOK_FIELD            1
+#define STV090x_OFFST_Px_TSFIFO_ERROR_FIELD             6
+#define STV090x_WIDTH_Px_TSFIFO_ERROR_FIELD             1
+
+#define STV090x_Px_TSSTATUS2(__x)                       (0xF582 - (__x - 1) * 0x200)
+#define STV090x_P1_TSSTATUS2                            STV090x_Px_TSSTATUS2(1)
+#define STV090x_P2_TSSTATUS2                            STV090x_Px_TSSTATUS2(2)
+#define STV090x_OFFST_Px_TSFIFO_DEMODSEL_FIELD          7
+#define STV090x_WIDTH_Px_TSFIFO_DEMODSEL_FIELD          1
+#define STV090x_OFFST_Px_TSFIFOSPEED_STORE_FIELD        6
+#define STV090x_WIDTH_Px_TSFIFOSPEED_STORE_FIELD        1
+#define STV090x_OFFST_Px_DILXX_RESET_FIELD              5
+#define STV090x_WIDTH_Px_DILXX_RESET_FIELD              1
+#define STV090x_OFFST_Px_TSSERIAL_IMPOS_FIELD           5
+#define STV090x_WIDTH_Px_TSSERIAL_IMPOS_FIELD           1
+#define STV090x_OFFST_Px_SCRAMBDETECT_FIELD             1
+#define STV090x_WIDTH_Px_SCRAMBDETECT_FIELD             1
+
+#define STV090x_Px_TSBITRATEy(__x, __y)                 (0xF584 - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_TSBITRATE0                           STV090x_Px_TSBITRATEy(1, 0)
+#define STV090x_P1_TSBITRATE1                           STV090x_Px_TSBITRATEy(1, 1)
+#define STV090x_P2_TSBITRATE0                           STV090x_Px_TSBITRATEy(2, 0)
+#define STV090x_P2_TSBITRATE1                           STV090x_Px_TSBITRATEy(2, 1)
+#define STV090x_OFFST_Px_TSFIFO_BITRATE_FIELD           7
+#define STV090x_WIDTH_Px_TSFIFO_BITRATE_FIELD           8
+
+#define STV090x_Px_ERRCTRL1(__x)                        (0xF598 - (__x - 1) * 0x200)
+#define STV090x_P1_ERRCTRL1                             STV090x_Px_ERRCTRL1(1)
+#define STV090x_P2_ERRCTRL1                             STV090x_Px_ERRCTRL1(2)
+#define STV090x_OFFST_Px_ERR_SOURCE_FIELD               4
+#define STV090x_WIDTH_Px_ERR_SOURCE_FIELD               4
+#define STV090x_OFFST_Px_NUM_EVENT_FIELD                0
+#define STV090x_WIDTH_Px_NUM_EVENT_FIELD                3
+
+#define STV090x_Px_ERRCNT12(__x)                        (0xF599 - (__x - 1) * 0x200)
+#define STV090x_P1_ERRCNT12                             STV090x_Px_ERRCNT12(1)
+#define STV090x_P2_ERRCNT12                             STV090x_Px_ERRCNT12(2)
+#define STV090x_OFFST_Px_ERRCNT1_OLDVALUE_FIELD         7
+#define STV090x_WIDTH_Px_ERRCNT1_OLDVALUE_FIELD         1
+#define STV090x_OFFST_Px_ERR_CNT12_FIELD                0
+#define STV090x_WIDTH_Px_ERR_CNT12_FIELD                7
+
+#define STV090x_Px_ERRCNT11(__x)                        (0xF59A - (__x - 1) * 0x200)
+#define STV090x_P1_ERRCNT11                             STV090x_Px_ERRCNT11(1)
+#define STV090x_P2_ERRCNT11                             STV090x_Px_ERRCNT11(2)
+#define STV090x_OFFST_Px_ERR_CNT11_FIELD                0
+#define STV090x_WIDTH_Px_ERR_CNT11_FIELD                8
+
+#define STV090x_Px_ERRCNT10(__x)                        (0xF59B - (__x - 1) * 0x200)
+#define STV090x_P1_ERRCNT10                             STV090x_Px_ERRCNT10(1)
+#define STV090x_P2_ERRCNT10                             STV090x_Px_ERRCNT10(2)
+#define STV090x_OFFST_Px_ERR_CNT10_FIELD                0
+#define STV090x_WIDTH_Px_ERR_CNT10_FIELD                8
+
+#define STV090x_Px_ERRCTRL2(__x)                        (0xF59C - (__x - 1) * 0x200)
+#define STV090x_P1_ERRCTRL2                             STV090x_Px_ERRCTRL2(1)
+#define STV090x_P2_ERRCTRL2                             STV090x_Px_ERRCTRL2(2)
+#define STV090x_OFFST_Px_ERR_SOURCE2_FIELD              4
+#define STV090x_WIDTH_Px_ERR_SOURCE2_FIELD              4
+#define STV090x_OFFST_Px_NUM_EVENT2_FIELD               0
+#define STV090x_WIDTH_Px_NUM_EVENT2_FIELD               3
+
+#define STV090x_Px_ERRCNT22(__x)                        (0xF59D - (__x - 1) * 0x200)
+#define STV090x_P1_ERRCNT22                             STV090x_Px_ERRCNT22(1)
+#define STV090x_P2_ERRCNT22                             STV090x_Px_ERRCNT22(2)
+#define STV090x_OFFST_Px_ERRCNT2_OLDVALUE_FIELD         7
+#define STV090x_WIDTH_Px_ERRCNT2_OLDVALUE_FIELD         1
+#define STV090x_OFFST_Px_ERR_CNT2_FIELD                 0
+#define STV090x_WIDTH_Px_ERR_CNT2_FIELD                 7
+
+#define STV090x_Px_ERRCNT21(__x)                        (0xF59E - (__x - 1) * 0x200)
+#define STV090x_P1_ERRCNT21                             STV090x_Px_ERRCNT21(1)
+#define STV090x_P2_ERRCNT21                             STV090x_Px_ERRCNT21(2)
+#define STV090x_OFFST_Px_ERR_CNT21_FIELD                0
+#define STV090x_WIDTH_Px_ERR_CNT21_FIELD                8
+
+#define STV090x_Px_ERRCNT20(__x)                        (0xF59F - (__x - 1) * 0x200)
+#define STV090x_P1_ERRCNT20                             STV090x_Px_ERRCNT20(1)
+#define STV090x_P2_ERRCNT20                             STV090x_Px_ERRCNT20(2)
+#define STV090x_OFFST_Px_ERR_CNT20_FIELD                0
+#define STV090x_WIDTH_Px_ERR_CNT20_FIELD                8
+
+#define STV090x_Px_FECSPY(__x)                          (0xF5A0 - (__x - 1) * 0x200)
+#define STV090x_P1_FECSPY                               STV090x_Px_FECSPY(1)
+#define STV090x_P2_FECSPY                               STV090x_Px_FECSPY(2)
+#define STV090x_OFFST_Px_SPY_ENABLE_FIELD               7
+#define STV090x_WIDTH_Px_SPY_ENABLE_FIELD               1
+#define STV090x_OFFST_Px_BERMETER_DATAMAODE_FIELD       2
+#define STV090x_WIDTH_Px_BERMETER_DATAMAODE_FIELD       2
+
+#define STV090x_Px_FSPYCFG(__x)                         (0xF5A1 - (__x - 1) * 0x200)
+#define STV090x_P1_FSPYCFG                              STV090x_Px_FSPYCFG(1)
+#define STV090x_P2_FSPYCFG                              STV090x_Px_FSPYCFG(2)
+#define STV090x_OFFST_Px_RST_ON_ERROR_FIELD             5
+#define STV090x_WIDTH_Px_RST_ON_ERROR_FIELD             1
+#define STV090x_OFFST_Px_ONE_SHOT_FIELD                 4
+#define STV090x_WIDTH_Px_ONE_SHOT_FIELD                 1
+#define STV090x_OFFST_Px_I2C_MODE_FIELD                 2
+#define STV090x_WIDTH_Px_I2C_MODE_FIELD                 2
+
+#define STV090x_Px_FSPYDATA(__x)                        (0xF5A2 - (__x - 1) * 0x200)
+#define STV090x_P1_FSPYDATA                             STV090x_Px_FSPYDATA(1)
+#define STV090x_P2_FSPYDATA                             STV090x_Px_FSPYDATA(2)
+#define STV090x_OFFST_Px_SPY_STUFFING_FIELD             7
+#define STV090x_WIDTH_Px_SPY_STUFFING_FIELD             1
+#define STV090x_OFFST_Px_SPY_CNULLPKT_FIELD             5
+#define STV090x_WIDTH_Px_SPY_CNULLPKT_FIELD             1
+#define STV090x_OFFST_Px_SPY_OUTDATA_MODE_FIELD         0
+#define STV090x_WIDTH_Px_SPY_OUTDATA_MODE_FIELD         5
+
+#define STV090x_Px_FSPYOUT(__x)                         (0xF5A3 - (__x - 1) * 0x200)
+#define STV090x_P1_FSPYOUT                              STV090x_Px_FSPYOUT(1)
+#define STV090x_P2_FSPYOUT                              STV090x_Px_FSPYOUT(2)
+#define STV090x_OFFST_Px_FSPY_DIRECT_FIELD              7
+#define STV090x_WIDTH_Px_FSPY_DIRECT_FIELD              1
+#define STV090x_OFFST_Px_STUFF_MODE_FIELD               0
+#define STV090x_WIDTH_Px_STUFF_MODE_FIELD               3
+
+#define STV090x_Px_FSTATUS(__x)                         (0xF5A4 - (__x - 1) * 0x200)
+#define STV090x_P1_FSTATUS                              STV090x_Px_FSTATUS(1)
+#define STV090x_P2_FSTATUS                              STV090x_Px_FSTATUS(2)
+#define STV090x_OFFST_Px_SPY_ENDSIM_FIELD               7
+#define STV090x_WIDTH_Px_SPY_ENDSIM_FIELD               1
+#define STV090x_OFFST_Px_VALID_SIM_FIELD                6
+#define STV090x_WIDTH_Px_VALID_SIM_FIELD                1
+#define STV090x_OFFST_Px_FOUND_SIGNAL_FIELD             5
+#define STV090x_WIDTH_Px_FOUND_SIGNAL_FIELD             1
+#define STV090x_OFFST_Px_DSS_SYNCBYTE_FIELD             4
+#define STV090x_WIDTH_Px_DSS_SYNCBYTE_FIELD             1
+#define STV090x_OFFST_Px_RESULT_STATE_FIELD             0
+#define STV090x_WIDTH_Px_RESULT_STATE_FIELD             4
+
+#define STV090x_Px_FBERCPT4(__x)                        (0xF5A8 - (__x - 1) * 0x200)
+#define STV090x_P1_FBERCPT4                             STV090x_Px_FBERCPT4(1)
+#define STV090x_P2_FBERCPT4                             STV090x_Px_FBERCPT4(2)
+#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD            0
+#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD            8
+
+#define STV090x_Px_FBERCPT3(__x)                        (0xF5A9 - (__x - 1) * 0x200)
+#define STV090x_P1_FBERCPT3                             STV090x_Px_FBERCPT3(1)
+#define STV090x_P2_FBERCPT3                             STV090x_Px_FBERCPT3(2)
+#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD            0
+#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD            8
+
+#define STV090x_Px_FBERCPT2(__x)                        (0xF5AA - (__x - 1) * 0x200)
+#define STV090x_P1_FBERCPT2                             STV090x_Px_FBERCPT2(1)
+#define STV090x_P2_FBERCPT2                             STV090x_Px_FBERCPT2(2)
+#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD            0
+#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD            8
+
+#define STV090x_Px_FBERCPT1(__x)                        (0xF5AB - (__x - 1) * 0x200)
+#define STV090x_P1_FBERCPT1                             STV090x_Px_FBERCPT1(1)
+#define STV090x_P2_FBERCPT1                             STV090x_Px_FBERCPT1(2)
+#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD            0
+#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD            8
+
+#define STV090x_Px_FBERCPT0(__x)                        (0xF5AC - (__x - 1) * 0x200)
+#define STV090x_P1_FBERCPT0                             STV090x_Px_FBERCPT0(1)
+#define STV090x_P2_FBERCPT0                             STV090x_Px_FBERCPT0(2)
+#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD            0
+#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD            8
+
+#define STV090x_Px_FBERERRy(__x, __y)                   (0xF5AF - (__x - 1) * 0x200 - __y * 0x1)
+#define STV090x_P1_FBERERR0                             STV090x_Px_FBERERRy(1, 0)
+#define STV090x_P1_FBERERR1                             STV090x_Px_FBERERRy(1, 1)
+#define STV090x_P1_FBERERR2                             STV090x_Px_FBERERRy(1, 2)
+#define STV090x_P2_FBERERR0                             STV090x_Px_FBERERRy(2, 0)
+#define STV090x_P2_FBERERR1                             STV090x_Px_FBERERRy(2, 1)
+#define STV090x_P2_FBERERR2                             STV090x_Px_FBERERRy(2, 2)
+#define STV090x_OFFST_Px_FBERMETER_CPT_ERR_FIELD        0
+#define STV090x_WIDTH_Px_FBERMETER_CPT_ERR_FIELD        8
+
+#define STV090x_Px_FSPYBER(__x)                         (0xF5B2 - (__x - 1) * 0x200)
+#define STV090x_P1_FSPYBER                              STV090x_Px_FSPYBER(1)
+#define STV090x_P2_FSPYBER                              STV090x_Px_FSPYBER(2)
+#define STV090x_OFFST_Px_FSPYBER_SYNCBYTE_FIELD         4
+#define STV090x_WIDTH_Px_FSPYBER_SYNCBYTE_FIELD         1
+#define STV090x_OFFST_Px_FSPYBER_UNSYNC_FIELD           3
+#define STV090x_WIDTH_Px_FSPYBER_UNSYNC_FIELD           1
+#define STV090x_OFFST_Px_FSPYBER_CTIME_FIELD            0
+#define STV090x_WIDTH_Px_FSPYBER_CTIME_FIELD            3
+
+#define STV090x_RCCFGH                                  0xf600
+
+#define STV090x_TSGENERAL                               0xF630
+#define STV090x_OFFST_Px_MUXSTREAM_OUT_FIELD            3
+#define STV090x_WIDTH_Px_MUXSTREAM_OUT_FIELD            1
+#define STV090x_OFFST_Px_TSFIFO_PERMPARAL_FIELD         1
+#define STV090x_WIDTH_Px_TSFIFO_PERMPARAL_FIELD         2
+
+#define STV090x_TSGENERAL1X                             0xf670
+#define STV090x_CFGEXT                                  0xfa80
+
+#define STV090x_TSTRES0                                 0xFF11
+#define STV090x_OFFST_FRESFEC_FIELD                     7
+#define STV090x_WIDTH_FRESFEC_FIELD                     1
+
+#define STV090x_Px_TSTDISRX(__x)                        (0xFF67 - (__x - 1) * 0x2)
+#define STV090x_P1_TSTDISRX                             STV090x_Px_TSTDISRX(1)
+#define STV090x_P2_TSTDISRX                             STV090x_Px_TSTDISRX(2)
+#define STV090x_OFFST_Px_TSTDISRX_SELECT_FIELD          3
+#define STV090x_WIDTH_Px_TSTDISRX_SELECT_FIELD          1
+
+#endif /* __STV090x_REG_H */
diff --git a/drivers/media/dvb/frontends/stv6110x.c b/drivers/media/dvb/frontends/stv6110x.c
new file mode 100644
index 000000000000..3d8a2e01c9c4
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv6110x.c
@@ -0,0 +1,373 @@
+/*
+        STV6110(A) Silicon tuner driver
+
+        Copyright (C) Manu Abraham <abraham.manu@gmail.com>
+
+        Copyright (C) ST Microelectronics
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/string.h>
+
+#include "dvb_frontend.h"
+
+#include "stv6110x_reg.h"
+#include "stv6110x.h"
+#include "stv6110x_priv.h"
+
+static unsigned int verbose;
+module_param(verbose, int, 0644);
+MODULE_PARM_DESC(verbose, "Set Verbosity level");
+
+static u8 stv6110x_regs[] = {0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e};
+
+static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data)
+{
+        int ret;
+        const struct stv6110x_config *config = stv6110x->config;
+        u8 b0[] = { reg };
+        u8 b1[] = { 0 };
+        struct i2c_msg msg[] = {
+                { .addr = config->addr, .flags = 0,        .buf = b0, .len = 1 },
+                { .addr = config->addr, .flags = I2C_M_RD, .buf = b1, .len = 1 }
+        };
+
+        ret = i2c_transfer(stv6110x->i2c, msg, 2);
+        if (ret != 2) {
+                dprintk(FE_ERROR, 1, "I/O Error");
+                return -EREMOTEIO;
+        }
+        *data = b1[0];
+
+        return 0;
+}
+
+static int stv6110x_write_reg(struct stv6110x_state *stv6110x, u8 reg, u8 data)
+{
+        int ret;
+        const struct stv6110x_config *config = stv6110x->config;
+        u8 buf[] = { reg, data };
+        struct i2c_msg msg = { .addr = config->addr, .flags = 0, . buf = buf, .len = 2 };
+
+        ret = i2c_transfer(stv6110x->i2c, &msg, 1);
+        if (ret != 1) {
+                dprintk(FE_ERROR, 1, "I/O Error");
+                return -EREMOTEIO;
+        }
+
+        return 0;
+}
+
+static int stv6110x_init(struct dvb_frontend *fe)
+{
+        struct stv6110x_state *stv6110x = fe->tuner_priv;
+        int ret;
+        u8 i;
+
+        for (i = 0; i < ARRAY_SIZE(stv6110x_regs); i++) {
+                ret = stv6110x_write_reg(stv6110x, i, stv6110x_regs[i]);
+                if (ret < 0) {
+                        dprintk(FE_ERROR, 1, "Initialization failed");
+                        return -1;
+                }
+        }
+
+        return 0;
+}
+
+static int stv6110x_set_frequency(struct dvb_frontend *fe, u32 frequency)
+{
+        struct stv6110x_state *stv6110x = fe->tuner_priv;
+        u32 rDiv, divider;
+        s32 pVal, pCalc, rDivOpt = 0;
+        u8 i;
+
+        STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_K, (REFCLOCK_MHz - 16));
+
+        if (frequency <= 1023000) {
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
+                pVal = 40;
+        } else if (frequency <= 1300000) {
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
+                pVal = 40;
+        } else if (frequency <= 2046000) {
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
+                pVal = 20;
+        } else {
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
+                pVal = 20;
+        }
+
+        for (rDiv = 0; rDiv <= 3; rDiv++) {
+                pCalc = (REFCLOCK_kHz / 100) / R_DIV(rDiv);
+
+                if ((abs((s32)(pCalc - pVal))) < (abs((s32)(1000 - pVal))))
+                        rDivOpt = rDiv;
+        }
+
+        divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz;
+        divider = (divider + 5) / 10;
+
+        STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_R_DIV, rDivOpt);
+        STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider));
+        STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider));
+
+        /* VCO Auto calibration */
+        STV6110x_SETFIELD(stv6110x_regs[STV6110x_STAT1], STAT1_CALVCO_STRT, 1);
+
+        stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x_regs[STV6110x_CTRL1]);
+        stv6110x_write_reg(stv6110x, STV6110x_TNG1, stv6110x_regs[STV6110x_TNG1]);
+        stv6110x_write_reg(stv6110x, STV6110x_TNG0, stv6110x_regs[STV6110x_TNG0]);
+        stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x_regs[STV6110x_STAT1]);
+
+        for (i = 0; i < TRIALS; i++) {
+                stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x_regs[STV6110x_STAT1]);
+                if (!STV6110x_GETFIELD(STAT1_CALVCO_STRT, stv6110x_regs[STV6110x_STAT1]))
+                                break;
+                msleep(1);
+        }
+
+        return 0;
+}
+
+static int stv6110x_get_frequency(struct dvb_frontend *fe, u32 *frequency)
+{
+        struct stv6110x_state *stv6110x = fe->tuner_priv;
+
+        stv6110x_read_reg(stv6110x, STV6110x_TNG1, &stv6110x_regs[STV6110x_TNG1]);
+        stv6110x_read_reg(stv6110x, STV6110x_TNG0, &stv6110x_regs[STV6110x_TNG0]);
+
+        *frequency = (MAKEWORD16(STV6110x_GETFIELD(TNG1_N_DIV_11_8, stv6110x_regs[STV6110x_TNG1]),
+                                 STV6110x_GETFIELD(TNG0_N_DIV_7_0, stv6110x_regs[STV6110x_TNG0]))) * REFCLOCK_kHz;
+
+        *frequency /= (1 << (STV6110x_GETFIELD(TNG1_R_DIV, stv6110x_regs[STV6110x_TNG1]) +
+                             STV6110x_GETFIELD(TNG1_DIV4SEL, stv6110x_regs[STV6110x_TNG1])));
+
+        *frequency >>= 2;
+
+        return 0;
+}
+
+static int stv6110x_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
+{
+        struct stv6110x_state *stv6110x = fe->tuner_priv;
+        u32 halfbw;
+        u8 i;
+
+        halfbw = bandwidth >> 1;
+
+        if (halfbw > 36000000)
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_CF, 31); /* LPF */
+        else if (halfbw < 5000000)
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_CF, 0); /* LPF */
+        else
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_CF, ((halfbw / 1000000) - 5)); /* LPF */
+
+
+        STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x0); /* cal. clk activated */
+        STV6110x_SETFIELD(stv6110x_regs[STV6110x_STAT1], STAT1_CALRC_STRT, 0x1); /* LPF auto cal */
+
+        stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x_regs[STV6110x_CTRL3]);
+        stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x_regs[STV6110x_STAT1]);
+
+        for (i = 0; i < TRIALS; i++) {
+                stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x_regs[STV6110x_STAT1]);
+                if (!STV6110x_GETFIELD(STAT1_CALRC_STRT, stv6110x_regs[STV6110x_STAT1]))
+                        break;
+                msleep(1);
+        }
+        STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x1); /* cal. done */
+        stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x_regs[STV6110x_CTRL3]);
+
+        return 0;
+}
+
+static int stv6110x_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
+{
+        struct stv6110x_state *stv6110x = fe->tuner_priv;
+
+        stv6110x_read_reg(stv6110x, STV6110x_CTRL3, &stv6110x_regs[STV6110x_CTRL3]);
+        *bandwidth = (STV6110x_GETFIELD(CTRL3_CF, stv6110x_regs[STV6110x_CTRL3]) + 5) * 2000000;
+
+        return 0;
+}
+
+static int stv6110x_set_refclock(struct dvb_frontend *fe, u32 refclock)
+{
+        struct stv6110x_state *stv6110x = fe->tuner_priv;
+
+        /* setup divider */
+        switch (refclock) {
+        default:
+        case 1:
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0);
+                break;
+        case 2:
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1);
+                break;
+        case 4:
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2);
+                break;
+        case 8:
+        case 0:
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3);
+                break;
+        }
+        stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x_regs[STV6110x_CTRL2]);
+
+        return 0;
+}
+
+static int stv6110x_get_bbgain(struct dvb_frontend *fe, u32 *gain)
+{
+        struct stv6110x_state *stv6110x = fe->tuner_priv;
+
+        stv6110x_read_reg(stv6110x, STV6110x_CTRL2, &stv6110x_regs[STV6110x_CTRL2]);
+        *gain = 2 * STV6110x_GETFIELD(CTRL2_BBGAIN, stv6110x_regs[STV6110x_CTRL2]);
+
+        return 0;
+}
+
+static int stv6110x_set_bbgain(struct dvb_frontend *fe, u32 gain)
+{
+        struct stv6110x_state *stv6110x = fe->tuner_priv;
+
+        STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_BBGAIN, gain / 2);
+        stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x_regs[STV6110x_CTRL2]);
+
+        return 0;
+}
+
+static int stv6110x_set_mode(struct dvb_frontend *fe, enum tuner_mode mode)
+{
+        struct stv6110x_state *stv6110x = fe->tuner_priv;
+        int ret;
+
+        switch (mode) {
+        case TUNER_SLEEP:
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_SYN, 0);
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_RX, 0);
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_LPT, 0);
+                break;
+
+        case TUNER_WAKE:
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_SYN, 1);
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_RX, 1);
+                STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_LPT, 1);
+                break;
+        }
+
+        ret = stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x_regs[STV6110x_CTRL1]);
+        if (ret < 0) {
+                dprintk(FE_ERROR, 1, "I/O Error");
+                return -EIO;
+        }
+
+        return 0;
+}
+
+static int stv6110x_sleep(struct dvb_frontend *fe)
+{
+        return stv6110x_set_mode(fe, TUNER_SLEEP);
+}
+
+static int stv6110x_get_status(struct dvb_frontend *fe, u32 *status)
+{
+        struct stv6110x_state *stv6110x = fe->tuner_priv;
+
+        stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x_regs[STV6110x_STAT1]);
+
+        if (STV6110x_GETFIELD(STAT1_LOCK, stv6110x_regs[STV6110x_STAT1]))
+                *status = TUNER_PHASELOCKED;
+        else
+                *status = 0;
+
+        return 0;
+}
+
+
+static int stv6110x_release(struct dvb_frontend *fe)
+{
+        struct stv6110x_state *stv6110x = fe->tuner_priv;
+
+        fe->tuner_priv = NULL;
+        kfree(stv6110x);
+
+        return 0;
+}
+
+static struct dvb_tuner_ops stv6110x_ops = {
+        .info = {
+                .name           = "STV6110(A) Silicon Tuner",
+                .frequency_min  =  950000,
+                .frequency_max  = 2150000,
+                .frequency_step = 0,
+        },
+
+        .init                   = stv6110x_init,
+        .sleep                  = stv6110x_sleep,
+        .release                = stv6110x_release
+};
+
+static struct stv6110x_devctl stv6110x_ctl = {
+        .tuner_init             = stv6110x_init,
+        .tuner_set_mode         = stv6110x_set_mode,
+        .tuner_set_frequency    = stv6110x_set_frequency,
+        .tuner_get_frequency    = stv6110x_get_frequency,
+        .tuner_set_bandwidth    = stv6110x_set_bandwidth,
+        .tuner_get_bandwidth    = stv6110x_get_bandwidth,
+        .tuner_set_bbgain       = stv6110x_set_bbgain,
+        .tuner_get_bbgain       = stv6110x_get_bbgain,
+        .tuner_set_refclk       = stv6110x_set_refclock,
+        .tuner_get_status       = stv6110x_get_status,
+};
+
+struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
+                                        const struct stv6110x_config *config,
+                                        struct i2c_adapter *i2c)
+{
+        struct stv6110x_state *stv6110x;
+
+        stv6110x = kzalloc(sizeof (struct stv6110x_state), GFP_KERNEL);
+        if (stv6110x == NULL)
+                goto error;
+
+        stv6110x->i2c           = i2c;
+        stv6110x->config        = config;
+        stv6110x->devctl        = &stv6110x_ctl;
+
+        fe->tuner_priv          = stv6110x;
+        fe->ops.tuner_ops       = stv6110x_ops;
+
+        printk("%s: Attaching STV6110x \n", __func__);
+        return stv6110x->devctl;
+
+error:
+        kfree(stv6110x);
+        return NULL;
+}
+EXPORT_SYMBOL(stv6110x_attach);
+
+MODULE_AUTHOR("Manu Abraham");
+MODULE_DESCRIPTION("STV6110x Silicon tuner");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/stv6110x.h b/drivers/media/dvb/frontends/stv6110x.h
new file mode 100644
index 000000000000..a38257080e01
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv6110x.h
@@ -0,0 +1,71 @@
+/*
+        STV6110(A) Silicon tuner driver
+
+        Copyright (C) Manu Abraham <abraham.manu@gmail.com>
+
+        Copyright (C) ST Microelectronics
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __STV6110x_H
+#define __STV6110x_H
+
+struct stv6110x_config {
+        u8      addr;
+        u32     refclk;
+};
+
+enum tuner_mode {
+        TUNER_SLEEP = 1,
+        TUNER_WAKE,
+};
+
+enum tuner_status {
+        TUNER_PHASELOCKED = 1,
+};
+
+struct stv6110x_devctl {
+        int (*tuner_init) (struct dvb_frontend *fe);
+        int (*tuner_set_mode) (struct dvb_frontend *fe, enum tuner_mode mode);
+        int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency);
+        int (*tuner_get_frequency) (struct dvb_frontend *fe, u32 *frequency);
+        int (*tuner_set_bandwidth) (struct dvb_frontend *fe, u32 bandwidth);
+        int (*tuner_get_bandwidth) (struct dvb_frontend *fe, u32 *bandwidth);
+        int (*tuner_set_bbgain) (struct dvb_frontend *fe, u32 gain);
+        int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain);
+        int (*tuner_set_refclk)  (struct dvb_frontend *fe, u32 refclk);
+        int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status);
+};
+
+
+#if defined(CONFIG_DVB_STV6110x) || (defined(CONFIG_DVB_STV6110x_MODULE) && defined(MODULE))
+
+extern struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
+                                               const struct stv6110x_config *config,
+                                               struct i2c_adapter *i2c);
+
+#else
+static inline struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
+                                                      const struct stv6110x_config *config,
+                                                      struct i2c_adapter *i2c)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return NULL;
+}
+
+#endif /* CONFIG_DVB_STV6110x */
+
+#endif /* __STV6110x_H */
diff --git a/drivers/media/dvb/frontends/stv6110x_priv.h b/drivers/media/dvb/frontends/stv6110x_priv.h
new file mode 100644
index 000000000000..7260da633d49
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv6110x_priv.h
@@ -0,0 +1,75 @@
+/*
+        STV6110(A) Silicon tuner driver
+
+        Copyright (C) Manu Abraham <abraham.manu@gmail.com>
+
+        Copyright (C) ST Microelectronics
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __STV6110x_PRIV_H
+#define __STV6110x_PRIV_H
+
+#define FE_ERROR                                0
+#define FE_NOTICE                               1
+#define FE_INFO                                 2
+#define FE_DEBUG                                3
+#define FE_DEBUGREG                             4
+
+#define dprintk(__y, __z, format, arg...) do {                                          \
+        if (__z) {                                                                      \
+                if      ((verbose > FE_ERROR) && (verbose > __y))                       \
+                        printk(KERN_ERR "%s: " format "\n", __func__ , ##arg);          \
+                else if ((verbose > FE_NOTICE) && (verbose > __y))                      \
+                        printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg);       \
+                else if ((verbose > FE_INFO) && (verbose > __y))                        \
+                        printk(KERN_INFO "%s: " format "\n", __func__ , ##arg);         \
+                else if ((verbose > FE_DEBUG) && (verbose > __y))                       \
+                        printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg);        \
+        } else {                                                                        \
+                if (verbose > __y)                                                      \
+                        printk(format, ##arg);                                          \
+        }                                                                               \
+} while (0)
+
+
+#define STV6110x_SETFIELD(mask, bitf, val)                              \
+        (mask = (mask & (~(((1 << STV6110x_WIDTH_##bitf) - 1) <<        \
+                                  STV6110x_OFFST_##bitf))) |            \
+                          (val << STV6110x_OFFST_##bitf))
+
+#define STV6110x_GETFIELD(bitf, val)                                    \
+        ((val >> STV6110x_OFFST_##bitf) &                               \
+        ((1 << STV6110x_WIDTH_##bitf) - 1))
+
+#define MAKEWORD16(a, b)                        (((a) << 8) | (b))
+
+#define LSB(x)                                  ((x & 0xff))
+#define MSB(y)                                  ((y >> 8) & 0xff)
+
+#define TRIALS                                  10
+#define R_DIV(__div)                            (1 << (__div + 1))
+#define REFCLOCK_kHz                            (stv6110x->config->refclk /    1000)
+#define REFCLOCK_MHz                            (stv6110x->config->refclk / 1000000)
+
+struct stv6110x_state {
+        struct i2c_adapter              *i2c;
+        const struct stv6110x_config    *config;
+
+        struct stv6110x_devctl          *devctl;
+};
+
+#endif /* __STV6110x_PRIV_H */
diff --git a/drivers/media/dvb/frontends/stv6110x_reg.h b/drivers/media/dvb/frontends/stv6110x_reg.h
new file mode 100644
index 000000000000..93e5c70e5fd8
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv6110x_reg.h
@@ -0,0 +1,82 @@
+/*
+        STV6110(A) Silicon tuner driver
+
+        Copyright (C) Manu Abraham <abraham.manu@gmail.com>
+
+        Copyright (C) ST Microelectronics
+
+        This program is free software; you can redistribute it and/or modify
+        it under the terms of the GNU General Public License as published by
+        the Free Software Foundation; either version 2 of the License, or
+        (at your option) any later version.
+
+        This program is distributed in the hope that it will be useful,
+        but WITHOUT ANY WARRANTY; without even the implied warranty of
+        MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+        GNU General Public License for more details.
+
+        You should have received a copy of the GNU General Public License
+        along with this program; if not, write to the Free Software
+        Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#ifndef __STV6110x_REG_H
+#define __STV6110x_REG_H
+
+#define STV6110x_CTRL1                          0x00
+#define STV6110x_OFFST_CTRL1_K                  3
+#define STV6110x_WIDTH_CTRL1_K                  5
+#define STV6110x_OFFST_CTRL1_LPT                2
+#define STV6110x_WIDTH_CTRL1_LPT                1
+#define STV6110x_OFFST_CTRL1_RX                 1
+#define STV6110x_WIDTH_CTRL1_RX                 1
+#define STV6110x_OFFST_CTRL1_SYN                0
+#define STV6110x_WIDTH_CTRL1_SYN                1
+
+#define STV6110x_CTRL2                          0x01
+#define STV6110x_OFFST_CTRL2_CO_DIV             6
+#define STV6110x_WIDTH_CTRL2_CO_DIV             2
+#define STV6110x_OFFST_CTRL2_RSVD               5
+#define STV6110x_WIDTH_CTRL2_RSVD               1
+#define STV6110x_OFFST_CTRL2_REFOUT_SEL         4
+#define STV6110x_WIDTH_CTRL2_REFOUT_SEL         1
+#define STV6110x_OFFST_CTRL2_BBGAIN             0
+#define STV6110x_WIDTH_CTRL2_BBGAIN             4
+
+#define STV6110x_TNG0                           0x02
+#define STV6110x_OFFST_TNG0_N_DIV_7_0           0
+#define STV6110x_WIDTH_TNG0_N_DIV_7_0           8
+
+#define STV6110x_TNG1                           0x03
+#define STV6110x_OFFST_TNG1_R_DIV               6
+#define STV6110x_WIDTH_TNG1_R_DIV               2
+#define STV6110x_OFFST_TNG1_PRESC32_ON          5
+#define STV6110x_WIDTH_TNG1_PRESC32_ON          1
+#define STV6110x_OFFST_TNG1_DIV4SEL             4
+#define STV6110x_WIDTH_TNG1_DIV4SEL             1
+#define STV6110x_OFFST_TNG1_N_DIV_11_8          0
+#define STV6110x_WIDTH_TNG1_N_DIV_11_8          4
+
+
+#define STV6110x_CTRL3                          0x04
+#define STV6110x_OFFST_CTRL3_DCLOOP_OFF         7
+#define STV6110x_WIDTH_CTRL3_DCLOOP_OFF         1
+#define STV6110x_OFFST_CTRL3_RCCLK_OFF          6
+#define STV6110x_WIDTH_CTRL3_RCCLK_OFF          1
+#define STV6110x_OFFST_CTRL3_ICP                5
+#define STV6110x_WIDTH_CTRL3_ICP                1
+#define STV6110x_OFFST_CTRL3_CF                 0
+#define STV6110x_WIDTH_CTRL3_CF                 5
+
+#define STV6110x_STAT1                          0x05
+#define STV6110x_OFFST_STAT1_CALVCO_STRT        2
+#define STV6110x_WIDTH_STAT1_CALVCO_STRT        1
+#define STV6110x_OFFST_STAT1_CALRC_STRT         1
+#define STV6110x_WIDTH_STAT1_CALRC_STRT         1
+#define STV6110x_OFFST_STAT1_LOCK               0
+#define STV6110x_WIDTH_STAT1_LOCK               1
+
+#define STV6110x_STAT2                          0x06
+#define STV6110x_STAT3                          0x07
+
+#endif /* __STV6110x_REG_H */
diff --git a/drivers/media/dvb/frontends/tda10048.c b/drivers/media/dvb/frontends/tda10048.c
index 2a8bbcd44cd0..4302c563a6b8 100644
--- a/drivers/media/dvb/frontends/tda10048.c
+++ b/drivers/media/dvb/frontends/tda10048.c
@@ -1,7 +1,7 @@
 /*
     NXP TDA10048HN DVB OFDM demodulator driver
 
-    Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
+    Copyright (C) 2009 Steven Toth <stoth@kernellabs.com>
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -25,6 +25,7 @@
 #include <linux/string.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
+#include <asm/div64.h>
 #include "dvb_frontend.h"
 #include "dvb_math.h"
 #include "tda10048.h"
@@ -138,11 +139,20 @@ struct tda10048_state {
 
         struct i2c_adapter *i2c;
 
-        /* configuration settings */
-        const struct tda10048_config *config;
+        /* We'll cache and update the attach config settings */
+        struct tda10048_config config;
         struct dvb_frontend frontend;
 
         int fwloaded;
+
+        u32 freq_if_hz;
+        u32 xtal_hz;
+        u32 pll_mfactor;
+        u32 pll_nfactor;
+        u32 pll_pfactor;
+        u32 sample_freq;
+
+        enum fe_bandwidth bandwidth;
 };
 
 static struct init_tab {
@@ -192,12 +202,26 @@ static struct init_tab {
         { TDA10048_CONF_C4_2, 0x04 },
 };
 
+static struct pll_tab {
+        u32     clk_freq_khz;
+        u32     if_freq_khz;
+        u8      m, n, p;
+} pll_tab[] = {
+        { TDA10048_CLK_4000,  TDA10048_IF_36130, 10, 0, 0 },
+        { TDA10048_CLK_16000, TDA10048_IF_3300,  10, 3, 0 },
+        { TDA10048_CLK_16000, TDA10048_IF_3500,  10, 3, 0 },
+        { TDA10048_CLK_16000, TDA10048_IF_4000,  10, 3, 0 },
+        { TDA10048_CLK_16000, TDA10048_IF_4300,  10, 3, 0 },
+        { TDA10048_CLK_16000, TDA10048_IF_36130, 10, 3, 0 },
+};
+
 static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data)
 {
+        struct tda10048_config *config = &state->config;
         int ret;
         u8 buf[] = { reg, data };
         struct i2c_msg msg = {
-                .addr = state->config->demod_address,
+                .addr = config->demod_address,
                 .flags = 0, .buf = buf, .len = 2 };
 
         dprintk(2, "%s(reg = 0x%02x, data = 0x%02x)\n", __func__, reg, data);
@@ -212,13 +236,14 @@ static int tda10048_writereg(struct tda10048_state *state, u8 reg, u8 data)
 
 static u8 tda10048_readreg(struct tda10048_state *state, u8 reg)
 {
+        struct tda10048_config *config = &state->config;
         int ret;
         u8 b0[] = { reg };
         u8 b1[] = { 0 };
         struct i2c_msg msg[] = {
-                { .addr = state->config->demod_address,
+                { .addr = config->demod_address,
                         .flags = 0, .buf = b0, .len = 1 },
-                { .addr = state->config->demod_address,
+                { .addr = config->demod_address,
                         .flags = I2C_M_RD, .buf = b1, .len = 1 } };
 
         dprintk(2, "%s(reg = 0x%02x)\n", __func__, reg);
@@ -235,6 +260,7 @@ static u8 tda10048_readreg(struct tda10048_state *state, u8 reg)
 static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg,
                                  const u8 *data, u16 len)
 {
+        struct tda10048_config *config = &state->config;
         int ret = -EREMOTEIO;
         struct i2c_msg msg;
         u8 *buf;
@@ -250,7 +276,7 @@ static int tda10048_writeregbulk(struct tda10048_state *state, u8 reg,
         *buf = reg;
         memcpy(buf + 1, data, len);
 
-        msg.addr = state->config->demod_address;
+        msg.addr = config->demod_address;
         msg.flags = 0;
         msg.buf = buf;
         msg.len = len + 1;
@@ -271,14 +297,206 @@ error:
         return ret;
 }
 
+static int tda10048_set_phy2(struct dvb_frontend *fe, u32 sample_freq_hz,
+                             u32 if_hz)
+{
+        struct tda10048_state *state = fe->demodulator_priv;
+        u64 t;
+
+        dprintk(1, "%s()\n", __func__);
+
+        if (sample_freq_hz == 0)
+                return -EINVAL;
+
+        if (if_hz < (sample_freq_hz / 2)) {
+                /* PHY2 = (if2/fs) * 2^15 */
+                t = if_hz;
+                t *= 10;
+                t *= 32768;
+                do_div(t, sample_freq_hz);
+                t += 5;
+                do_div(t, 10);
+        } else {
+                /* PHY2 = ((IF1-fs)/fs) * 2^15 */
+                t = sample_freq_hz - if_hz;
+                t *= 10;
+                t *= 32768;
+                do_div(t, sample_freq_hz);
+                t += 5;
+                do_div(t, 10);
+                t = ~t + 1;
+        }
+
+        tda10048_writereg(state, TDA10048_FREQ_PHY2_LSB, (u8)t);
+        tda10048_writereg(state, TDA10048_FREQ_PHY2_MSB, (u8)(t >> 8));
+
+        return 0;
+}
+
+static int tda10048_set_wref(struct dvb_frontend *fe, u32 sample_freq_hz,
+                             u32 bw)
+{
+        struct tda10048_state *state = fe->demodulator_priv;
+        u64 t, z;
+        u32 b = 8000000;
+
+        dprintk(1, "%s()\n", __func__);
+
+        if (sample_freq_hz == 0)
+                return -EINVAL;
+
+        if (bw == BANDWIDTH_6_MHZ)
+                b = 6000000;
+        else
+        if (bw == BANDWIDTH_7_MHZ)
+                b = 7000000;
+
+        /* WREF = (B / (7 * fs)) * 2^31 */
+        t = b * 10;
+        /* avoid warning: this decimal constant is unsigned only in ISO C90 */
+        /* t *= 2147483648 on 32bit platforms */
+        t *= (2048 * 1024);
+        t *= 1024;
+        z = 7 * sample_freq_hz;
+        do_div(t, z);
+        t += 5;
+        do_div(t, 10);
+
+        tda10048_writereg(state, TDA10048_TIME_WREF_LSB, (u8)t);
+        tda10048_writereg(state, TDA10048_TIME_WREF_MID1, (u8)(t >> 8));
+        tda10048_writereg(state, TDA10048_TIME_WREF_MID2, (u8)(t >> 16));
+        tda10048_writereg(state, TDA10048_TIME_WREF_MSB, (u8)(t >> 24));
+
+        return 0;
+}
+
+static int tda10048_set_invwref(struct dvb_frontend *fe, u32 sample_freq_hz,
+                                u32 bw)
+{
+        struct tda10048_state *state = fe->demodulator_priv;
+        u64 t;
+        u32 b = 8000000;
+
+        dprintk(1, "%s()\n", __func__);
+
+        if (sample_freq_hz == 0)
+                return -EINVAL;
+
+        if (bw == BANDWIDTH_6_MHZ)
+                b = 6000000;
+        else
+        if (bw == BANDWIDTH_7_MHZ)
+                b = 7000000;
+
+        /* INVWREF = ((7 * fs) / B) * 2^5 */
+        t = sample_freq_hz;
+        t *= 7;
+        t *= 32;
+        t *= 10;
+        do_div(t, b);
+        t += 5;
+        do_div(t, 10);
+
+        tda10048_writereg(state, TDA10048_TIME_INVWREF_LSB, (u8)t);
+        tda10048_writereg(state, TDA10048_TIME_INVWREF_MSB, (u8)(t >> 8));
+
+        return 0;
+}
+
+static int tda10048_set_bandwidth(struct dvb_frontend *fe,
+        enum fe_bandwidth bw)
+{
+        struct tda10048_state *state = fe->demodulator_priv;
+        dprintk(1, "%s(bw=%d)\n", __func__, bw);
+
+        /* Bandwidth setting may need to be adjusted */
+        switch (bw) {
+        case BANDWIDTH_6_MHZ:
+        case BANDWIDTH_7_MHZ:
+        case BANDWIDTH_8_MHZ:
+                tda10048_set_wref(fe, state->sample_freq, bw);
+                tda10048_set_invwref(fe, state->sample_freq, bw);
+                break;
+        default:
+                printk(KERN_ERR "%s() invalid bandwidth\n", __func__);
+                return -EINVAL;
+        }
+
+        state->bandwidth = bw;
+
+        return 0;
+}
+
+static int tda10048_set_if(struct dvb_frontend *fe, enum fe_bandwidth bw)
+{
+        struct tda10048_state *state = fe->demodulator_priv;
+        struct tda10048_config *config = &state->config;
+        int i;
+        u32 if_freq_khz;
+
+        dprintk(1, "%s(bw = %d)\n", __func__, bw);
+
+        /* based on target bandwidth and clk we calculate pll factors */
+        switch (bw) {
+        case BANDWIDTH_6_MHZ:
+                if_freq_khz = config->dtv6_if_freq_khz;
+                break;
+        case BANDWIDTH_7_MHZ:
+                if_freq_khz = config->dtv7_if_freq_khz;
+                break;
+        case BANDWIDTH_8_MHZ:
+                if_freq_khz = config->dtv8_if_freq_khz;
+                break;
+        default:
+                printk(KERN_ERR "%s() no default\n", __func__);
+                return -EINVAL;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(pll_tab); i++) {
+                if ((pll_tab[i].clk_freq_khz == config->clk_freq_khz) &&
+                        (pll_tab[i].if_freq_khz == if_freq_khz)) {
+
+                        state->freq_if_hz = pll_tab[i].if_freq_khz * 1000;
+                        state->xtal_hz = pll_tab[i].clk_freq_khz * 1000;
+                        state->pll_mfactor = pll_tab[i].m;
+                        state->pll_nfactor = pll_tab[i].n;
+                        state->pll_pfactor = pll_tab[i].p;
+                        break;
+                }
+        }
+        if (i == ARRAY_SIZE(pll_tab)) {
+                printk(KERN_ERR "%s() Incorrect attach settings\n",
+                        __func__);
+                return -EINVAL;
+        }
+
+        dprintk(1, "- freq_if_hz = %d\n", state->freq_if_hz);
+        dprintk(1, "- xtal_hz = %d\n", state->xtal_hz);
+        dprintk(1, "- pll_mfactor = %d\n", state->pll_mfactor);
+        dprintk(1, "- pll_nfactor = %d\n", state->pll_nfactor);
+        dprintk(1, "- pll_pfactor = %d\n", state->pll_pfactor);
+
+        /* Calculate the sample frequency */
+        state->sample_freq = state->xtal_hz * (state->pll_mfactor + 45);
+        state->sample_freq /= (state->pll_nfactor + 1);
+        state->sample_freq /= (state->pll_pfactor + 4);
+        dprintk(1, "- sample_freq = %d\n", state->sample_freq);
+
+        /* Update the I/F */
+        tda10048_set_phy2(fe, state->sample_freq, state->freq_if_hz);
+
+        return 0;
+}
+
 static int tda10048_firmware_upload(struct dvb_frontend *fe)
 {
         struct tda10048_state *state = fe->demodulator_priv;
+        struct tda10048_config *config = &state->config;
         const struct firmware *fw;
         int ret;
         int pos = 0;
         int cnt;
-        u8 wlen = state->config->fwbulkwritelen;
+        u8 wlen = config->fwbulkwritelen;
 
         if ((wlen != TDA10048_BULKWRITE_200) && (wlen != TDA10048_BULKWRITE_50))
                 wlen = TDA10048_BULKWRITE_200;
@@ -289,7 +507,7 @@ static int tda10048_firmware_upload(struct dvb_frontend *fe)
                 TDA10048_DEFAULT_FIRMWARE);
 
         ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE,
-                &state->i2c->dev);
+                state->i2c->dev.parent);
         if (ret) {
                 printk(KERN_ERR "%s: Upload failed. (file not found?)\n",
                         __func__);
@@ -484,8 +702,12 @@ static int tda10048_get_tps(struct tda10048_state *state,
 static int tda10048_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 {
         struct tda10048_state *state = fe->demodulator_priv;
+        struct tda10048_config *config = &state->config;
         dprintk(1, "%s(%d)\n", __func__, enable);
 
+        if (config->disable_gate_access)
+                return 0;
+
         if (enable)
                 return tda10048_writereg(state, TDA10048_CONF_C4_1,
                         tda10048_readreg(state, TDA10048_CONF_C4_1) | 0x02);
@@ -523,6 +745,12 @@ static int tda10048_set_frontend(struct dvb_frontend *fe,
 
         dprintk(1, "%s(frequency=%d)\n", __func__, p->frequency);
 
+        /* Update the I/F pll's if the bandwidth changes */
+        if (p->u.ofdm.bandwidth != state->bandwidth) {
+                tda10048_set_if(fe, p->u.ofdm.bandwidth);
+                tda10048_set_bandwidth(fe, p->u.ofdm.bandwidth);
+        }
+
         if (fe->ops.tuner_ops.set_params) {
 
                 if (fe->ops.i2c_gate_ctrl)
@@ -544,6 +772,7 @@ static int tda10048_set_frontend(struct dvb_frontend *fe,
 static int tda10048_init(struct dvb_frontend *fe)
 {
         struct tda10048_state *state = fe->demodulator_priv;
+        struct tda10048_config *config = &state->config;
         int ret = 0, i;
 
         dprintk(1, "%s()\n", __func__);
@@ -556,10 +785,14 @@ static int tda10048_init(struct dvb_frontend *fe)
                 ret = tda10048_firmware_upload(fe);
 
         /* Set either serial or parallel */
-        tda10048_output_mode(fe, state->config->output_mode);
+        tda10048_output_mode(fe, config->output_mode);
+
+        /* Set inversion */
+        tda10048_set_inversion(fe, config->inversion);
 
-        /* set inversion */
-        tda10048_set_inversion(fe, state->config->inversion);
+        /* Establish default RF values */
+        tda10048_set_if(fe, BANDWIDTH_8_MHZ);
+        tda10048_set_bandwidth(fe, BANDWIDTH_8_MHZ);
 
         /* Ensure we leave the gate closed */
         tda10048_i2c_gate_ctrl(fe, 0);
@@ -812,6 +1045,45 @@ static void tda10048_release(struct dvb_frontend *fe)
         kfree(state);
 }
 
+static void tda10048_establish_defaults(struct dvb_frontend *fe)
+{
+        struct tda10048_state *state = fe->demodulator_priv;
+        struct tda10048_config *config = &state->config;
+
+        /* Validate/default the config */
+        if (config->dtv6_if_freq_khz == 0) {
+                config->dtv6_if_freq_khz = TDA10048_IF_4300;
+                printk(KERN_WARNING "%s() tda10048_config.dtv6_if_freq_khz "
+                        "is not set (defaulting to %d)\n",
+                        __func__,
+                        config->dtv6_if_freq_khz);
+        }
+
+        if (config->dtv7_if_freq_khz == 0) {
+                config->dtv7_if_freq_khz = TDA10048_IF_4300;
+                printk(KERN_WARNING "%s() tda10048_config.dtv7_if_freq_khz "
+                        "is not set (defaulting to %d)\n",
+                        __func__,
+                        config->dtv7_if_freq_khz);
+        }
+
+        if (config->dtv8_if_freq_khz == 0) {
+                config->dtv8_if_freq_khz = TDA10048_IF_4300;
+                printk(KERN_WARNING "%s() tda10048_config.dtv8_if_freq_khz "
+                        "is not set (defaulting to %d)\n",
+                        __func__,
+                        config->dtv8_if_freq_khz);
+        }
+
+        if (config->clk_freq_khz == 0) {
+                config->clk_freq_khz = TDA10048_CLK_16000;
+                printk(KERN_WARNING "%s() tda10048_config.clk_freq_khz "
+                        "is not set (defaulting to %d)\n",
+                        __func__,
+                        config->clk_freq_khz);
+        }
+}
+
 static struct dvb_frontend_ops tda10048_ops;
 
 struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
@@ -826,10 +1098,11 @@ struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
         if (state == NULL)
                 goto error;
 
-        /* setup the state */
-        state->config = config;
+        /* setup the state and clone the config */
+        memcpy(&state->config, config, sizeof(*config));
         state->i2c = i2c;
         state->fwloaded = 0;
+        state->bandwidth = BANDWIDTH_8_MHZ;
 
         /* check if the demod is present */
         if (tda10048_readreg(state, TDA10048_IDENTITY) != 0x048)
@@ -840,6 +1113,17 @@ struct dvb_frontend *tda10048_attach(const struct tda10048_config *config,
                 sizeof(struct dvb_frontend_ops));
         state->frontend.demodulator_priv = state;
 
+        /* Establish any defaults the the user didn't pass */
+        tda10048_establish_defaults(&state->frontend);
+
+        /* Set the xtal and freq defaults */
+        if (tda10048_set_if(&state->frontend, BANDWIDTH_8_MHZ) != 0)
+                goto error;
+
+        /* Default bandwidth */
+        if (tda10048_set_bandwidth(&state->frontend, BANDWIDTH_8_MHZ) != 0)
+                goto error;
+
         /* Leave the gate closed */
         tda10048_i2c_gate_ctrl(&state->frontend, 0);
 
diff --git a/drivers/media/dvb/frontends/tda10048.h b/drivers/media/dvb/frontends/tda10048.h
index 0457b24601fa..8828ceaf74bb 100644
--- a/drivers/media/dvb/frontends/tda10048.h
+++ b/drivers/media/dvb/frontends/tda10048.h
@@ -1,7 +1,7 @@
 /*
     NXP TDA10048HN DVB OFDM demodulator driver
 
-    Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>
+    Copyright (C) 2009 Steven Toth <stoth@kernellabs.com>
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -43,6 +43,25 @@ struct tda10048_config {
 #define TDA10048_INVERSION_OFF 0
 #define TDA10048_INVERSION_ON  1
         u8 inversion;
+
+#define TDA10048_IF_3300  3300
+#define TDA10048_IF_3500  3500
+#define TDA10048_IF_3800  3800
+#define TDA10048_IF_4000  4000
+#define TDA10048_IF_4300  4300
+#define TDA10048_IF_4500  4500
+#define TDA10048_IF_4750  4750
+#define TDA10048_IF_36130 36130
+        u16 dtv6_if_freq_khz;
+        u16 dtv7_if_freq_khz;
+        u16 dtv8_if_freq_khz;
+
+#define TDA10048_CLK_4000  4000
+#define TDA10048_CLK_16000 16000
+        u16 clk_freq_khz;
+
+        /* Disable I2C gate access */
+        u8 disable_gate_access;
 };
 
 #if defined(CONFIG_DVB_TDA10048) || \
diff --git a/drivers/media/dvb/siano/Makefile b/drivers/media/dvb/siano/Makefile
index bcf93f4828b2..c6644d909433 100644
--- a/drivers/media/dvb/siano/Makefile
+++ b/drivers/media/dvb/siano/Makefile
@@ -1,4 +1,4 @@
-sms1xxx-objs := smscoreapi.o sms-cards.o
+sms1xxx-objs := smscoreapi.o sms-cards.o smsendian.o smsir.o
 
 obj-$(CONFIG_DVB_SIANO_SMS1XXX) += sms1xxx.o
 obj-$(CONFIG_DVB_SIANO_SMS1XXX) += smsusb.o
diff --git a/drivers/media/dvb/siano/sms-cards.c b/drivers/media/dvb/siano/sms-cards.c
index 63e4d0ec6583..d8b15d583bde 100644
--- a/drivers/media/dvb/siano/sms-cards.c
+++ b/drivers/media/dvb/siano/sms-cards.c
@@ -18,6 +18,7 @@
  */
 
 #include "sms-cards.h"
+#include "smsir.h"
 
 static int sms_dbg;
 module_param_named(cards_dbg, sms_dbg, int, 0644);
@@ -30,17 +31,14 @@ static struct sms_board sms_boards[] = {
         [SMS1XXX_BOARD_SIANO_STELLAR] = {
                 .name   = "Siano Stellar Digital Receiver",
                 .type   = SMS_STELLAR,
-                .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-stellar-dvbt-01.fw",
         },
         [SMS1XXX_BOARD_SIANO_NOVA_A] = {
                 .name   = "Siano Nova A Digital Receiver",
                 .type   = SMS_NOVA_A0,
-                .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-nova-a-dvbt-01.fw",
         },
         [SMS1XXX_BOARD_SIANO_NOVA_B] = {
                 .name   = "Siano Nova B Digital Receiver",
                 .type   = SMS_NOVA_B0,
-                .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-nova-b-dvbt-01.fw",
         },
         [SMS1XXX_BOARD_SIANO_VEGA] = {
                 .name   = "Siano Vega Digital Receiver",
@@ -65,6 +63,9 @@ static struct sms_board sms_boards[] = {
                 .name   = "Hauppauge WinTV MiniStick",
                 .type   = SMS_NOVA_B0,
                 .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-hcw-55xxx-dvbt-02.fw",
+                .board_cfg.leds_power = 26,
+                .board_cfg.led0 = 27,
+                .board_cfg.led1 = 28,
                 .led_power = 26,
                 .led_lo    = 27,
                 .led_hi    = 28,
@@ -74,7 +75,9 @@ static struct sms_board sms_boards[] = {
                 .type   = SMS_NOVA_B0,
                 .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-hcw-55xxx-dvbt-02.fw",
                 .lna_ctrl  = 29,
+                .board_cfg.foreign_lna0_ctrl = 29,
                 .rf_switch = 17,
+                .board_cfg.rf_switch_uhf = 17,
         },
         [SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2] = {
                 .name   = "Hauppauge WinTV MiniCard",
@@ -82,6 +85,16 @@ static struct sms_board sms_boards[] = {
                 .fw[DEVICE_MODE_DVBT_BDA] = "sms1xxx-hcw-55xxx-dvbt-02.fw",
                 .lna_ctrl  = -1,
         },
+        [SMS1XXX_BOARD_SIANO_NICE] = {
+        /* 11 */
+                .name = "Siano Nice Digital Receiver",
+                .type = SMS_NOVA_B0,
+        },
+        [SMS1XXX_BOARD_SIANO_VENICE] = {
+        /* 12 */
+                .name = "Siano Venice Digital Receiver",
+                .type = SMS_VEGA,
+        },
 };
 
 struct sms_board *sms_get_board(int id)
@@ -91,12 +104,179 @@ struct sms_board *sms_get_board(int id)
         return &sms_boards[id];
 }
 EXPORT_SYMBOL_GPL(sms_get_board);
+static inline void sms_gpio_assign_11xx_default_led_config(
+                struct smscore_gpio_config *pGpioConfig) {
+        pGpioConfig->Direction = SMS_GPIO_DIRECTION_OUTPUT;
+        pGpioConfig->InputCharacteristics =
+                SMS_GPIO_INPUT_CHARACTERISTICS_NORMAL;
+        pGpioConfig->OutputDriving = SMS_GPIO_OUTPUT_DRIVING_4mA;
+        pGpioConfig->OutputSlewRate = SMS_GPIO_OUTPUT_SLEW_RATE_0_45_V_NS;
+        pGpioConfig->PullUpDown = SMS_GPIO_PULL_UP_DOWN_NONE;
+}
+
+int sms_board_event(struct smscore_device_t *coredev,
+                enum SMS_BOARD_EVENTS gevent) {
+        int board_id = smscore_get_board_id(coredev);
+        struct sms_board *board = sms_get_board(board_id);
+        struct smscore_gpio_config MyGpioConfig;
+
+        sms_gpio_assign_11xx_default_led_config(&MyGpioConfig);
+
+        switch (gevent) {
+        case BOARD_EVENT_POWER_INIT: /* including hotplug */
+                switch (board_id) {
+                case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
+                        /* set I/O and turn off all LEDs */
+                        smscore_gpio_configure(coredev,
+                                        board->board_cfg.leds_power,
+                                        &MyGpioConfig);
+                        smscore_gpio_set_level(coredev,
+                                        board->board_cfg.leds_power, 0);
+                        smscore_gpio_configure(coredev, board->board_cfg.led0,
+                                        &MyGpioConfig);
+                        smscore_gpio_set_level(coredev,
+                                        board->board_cfg.led0, 0);
+                        smscore_gpio_configure(coredev, board->board_cfg.led1,
+                                        &MyGpioConfig);
+                        smscore_gpio_set_level(coredev,
+                                        board->board_cfg.led1, 0);
+                        break;
+                case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2:
+                case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD:
+                        /* set I/O and turn off LNA */
+                        smscore_gpio_configure(coredev,
+                                        board->board_cfg.foreign_lna0_ctrl,
+                                        &MyGpioConfig);
+                        smscore_gpio_set_level(coredev,
+                                        board->board_cfg.foreign_lna0_ctrl,
+                                        0);
+                        break;
+                }
+                break; /* BOARD_EVENT_BIND */
+
+        case BOARD_EVENT_POWER_SUSPEND:
+                switch (board_id) {
+                case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
+                        smscore_gpio_set_level(coredev,
+                                                board->board_cfg.leds_power, 0);
+                        smscore_gpio_set_level(coredev,
+                                                board->board_cfg.led0, 0);
+                        smscore_gpio_set_level(coredev,
+                                                board->board_cfg.led1, 0);
+                        break;
+                case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2:
+                case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD:
+                        smscore_gpio_set_level(coredev,
+                                        board->board_cfg.foreign_lna0_ctrl,
+                                        0);
+                        break;
+                }
+                break; /* BOARD_EVENT_POWER_SUSPEND */
+
+        case BOARD_EVENT_POWER_RESUME:
+                switch (board_id) {
+                case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
+                        smscore_gpio_set_level(coredev,
+                                                board->board_cfg.leds_power, 1);
+                        smscore_gpio_set_level(coredev,
+                                                board->board_cfg.led0, 1);
+                        smscore_gpio_set_level(coredev,
+                                                board->board_cfg.led1, 0);
+                        break;
+                case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2:
+                case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD:
+                        smscore_gpio_set_level(coredev,
+                                        board->board_cfg.foreign_lna0_ctrl,
+                                        1);
+                        break;
+                }
+                break; /* BOARD_EVENT_POWER_RESUME */
+
+        case BOARD_EVENT_BIND:
+                switch (board_id) {
+                case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
+                        smscore_gpio_set_level(coredev,
+                                board->board_cfg.leds_power, 1);
+                        smscore_gpio_set_level(coredev,
+                                board->board_cfg.led0, 1);
+                        smscore_gpio_set_level(coredev,
+                                board->board_cfg.led1, 0);
+                        break;
+                case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2:
+                case SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD:
+                        smscore_gpio_set_level(coredev,
+                                        board->board_cfg.foreign_lna0_ctrl,
+                                        1);
+                        break;
+                }
+                break; /* BOARD_EVENT_BIND */
+
+        case BOARD_EVENT_SCAN_PROG:
+                break; /* BOARD_EVENT_SCAN_PROG */
+        case BOARD_EVENT_SCAN_COMP:
+                break; /* BOARD_EVENT_SCAN_COMP */
+        case BOARD_EVENT_EMERGENCY_WARNING_SIGNAL:
+                break; /* BOARD_EVENT_EMERGENCY_WARNING_SIGNAL */
+        case BOARD_EVENT_FE_LOCK:
+                switch (board_id) {
+                case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
+                        smscore_gpio_set_level(coredev,
+                        board->board_cfg.led1, 1);
+                        break;
+                }
+                break; /* BOARD_EVENT_FE_LOCK */
+        case BOARD_EVENT_FE_UNLOCK:
+                switch (board_id) {
+                case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
+                        smscore_gpio_set_level(coredev,
+                                                board->board_cfg.led1, 0);
+                        break;
+                }
+                break; /* BOARD_EVENT_FE_UNLOCK */
+        case BOARD_EVENT_DEMOD_LOCK:
+                break; /* BOARD_EVENT_DEMOD_LOCK */
+        case BOARD_EVENT_DEMOD_UNLOCK:
+                break; /* BOARD_EVENT_DEMOD_UNLOCK */
+        case BOARD_EVENT_RECEPTION_MAX_4:
+                break; /* BOARD_EVENT_RECEPTION_MAX_4 */
+        case BOARD_EVENT_RECEPTION_3:
+                break; /* BOARD_EVENT_RECEPTION_3 */
+        case BOARD_EVENT_RECEPTION_2:
+                break; /* BOARD_EVENT_RECEPTION_2 */
+        case BOARD_EVENT_RECEPTION_1:
+                break; /* BOARD_EVENT_RECEPTION_1 */
+        case BOARD_EVENT_RECEPTION_LOST_0:
+                break; /* BOARD_EVENT_RECEPTION_LOST_0 */
+        case BOARD_EVENT_MULTIPLEX_OK:
+                switch (board_id) {
+                case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
+                        smscore_gpio_set_level(coredev,
+                                                board->board_cfg.led1, 1);
+                        break;
+                }
+                break; /* BOARD_EVENT_MULTIPLEX_OK */
+        case BOARD_EVENT_MULTIPLEX_ERRORS:
+                switch (board_id) {
+                case SMS1XXX_BOARD_HAUPPAUGE_WINDHAM:
+                        smscore_gpio_set_level(coredev,
+                                                board->board_cfg.led1, 0);
+                        break;
+                }
+                break; /* BOARD_EVENT_MULTIPLEX_ERRORS */
+
+        default:
+                sms_err("Unknown SMS board event");
+                break;
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(sms_board_event);
 
 static int sms_set_gpio(struct smscore_device_t *coredev, int pin, int enable)
 {
         int lvl, ret;
         u32 gpio;
-        struct smscore_gpio_config gpioconfig = {
+        struct smscore_config_gpio gpioconfig = {
                 .direction            = SMS_GPIO_DIRECTION_OUTPUT,
                 .pullupdown           = SMS_GPIO_PULLUPDOWN_NONE,
                 .inputcharacteristics = SMS_GPIO_INPUTCHARACTERISTICS_NORMAL,
diff --git a/drivers/media/dvb/siano/sms-cards.h b/drivers/media/dvb/siano/sms-cards.h
index 64d74c59c33f..38f062f6ad68 100644
--- a/drivers/media/dvb/siano/sms-cards.h
+++ b/drivers/media/dvb/siano/sms-cards.h
@@ -22,6 +22,7 @@
 
 #include <linux/usb.h>
 #include "smscoreapi.h"
+#include "smsir.h"
 
 #define SMS_BOARD_UNKNOWN 0
 #define SMS1XXX_BOARD_SIANO_STELLAR 1
@@ -34,10 +35,47 @@
 #define SMS1XXX_BOARD_HAUPPAUGE_WINDHAM 8
 #define SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD 9
 #define SMS1XXX_BOARD_HAUPPAUGE_TIGER_MINICARD_R2 10
+#define SMS1XXX_BOARD_SIANO_NICE        11
+#define SMS1XXX_BOARD_SIANO_VENICE      12
+
+struct sms_board_gpio_cfg {
+        int lna_vhf_exist;
+        int lna_vhf_ctrl;
+        int lna_uhf_exist;
+        int lna_uhf_ctrl;
+        int lna_uhf_d_ctrl;
+        int lna_sband_exist;
+        int lna_sband_ctrl;
+        int lna_sband_d_ctrl;
+        int foreign_lna0_ctrl;
+        int foreign_lna1_ctrl;
+        int foreign_lna2_ctrl;
+        int rf_switch_vhf;
+        int rf_switch_uhf;
+        int rf_switch_sband;
+        int leds_power;
+        int led0;
+        int led1;
+        int led2;
+        int led3;
+        int led4;
+        int ir;
+        int eeprom_wp;
+        int mrc_sense;
+        int mrc_pdn_resetn;
+        int mrc_gp0; /* mrcs spi int */
+        int mrc_gp1;
+        int mrc_gp2;
+        int mrc_gp3;
+        int mrc_gp4;
+        int host_spi_gsp_ts_int;
+};
 
 struct sms_board {
         enum sms_device_type_st type;
         char *name, *fw[DEVICE_MODE_MAX];
+        struct sms_board_gpio_cfg board_cfg;
+        enum ir_kb_type ir_kb_type;
 
         /* gpios */
         int led_power, led_hi, led_lo, lna_ctrl, rf_switch;
@@ -45,6 +83,32 @@ struct sms_board {
 
 struct sms_board *sms_get_board(int id);
 
+extern struct smscore_device_t *coredev;
+
+enum SMS_BOARD_EVENTS {
+        BOARD_EVENT_POWER_INIT,
+        BOARD_EVENT_POWER_SUSPEND,
+        BOARD_EVENT_POWER_RESUME,
+        BOARD_EVENT_BIND,
+        BOARD_EVENT_SCAN_PROG,
+        BOARD_EVENT_SCAN_COMP,
+        BOARD_EVENT_EMERGENCY_WARNING_SIGNAL,
+        BOARD_EVENT_FE_LOCK,
+        BOARD_EVENT_FE_UNLOCK,
+        BOARD_EVENT_DEMOD_LOCK,
+        BOARD_EVENT_DEMOD_UNLOCK,
+        BOARD_EVENT_RECEPTION_MAX_4,
+        BOARD_EVENT_RECEPTION_3,
+        BOARD_EVENT_RECEPTION_2,
+        BOARD_EVENT_RECEPTION_1,
+        BOARD_EVENT_RECEPTION_LOST_0,
+        BOARD_EVENT_MULTIPLEX_OK,
+        BOARD_EVENT_MULTIPLEX_ERRORS
+};
+
+int sms_board_event(struct smscore_device_t *coredev,
+                enum SMS_BOARD_EVENTS gevent);
+
 int sms_board_setup(struct smscore_device_t *coredev);
 
 #define SMS_LED_OFF 0
diff --git a/drivers/media/dvb/siano/smscoreapi.c b/drivers/media/dvb/siano/smscoreapi.c
index 7bd4d1dee2b3..32be382f0e97 100644
--- a/drivers/media/dvb/siano/smscoreapi.c
+++ b/drivers/media/dvb/siano/smscoreapi.c
@@ -30,9 +30,13 @@
 #include <linux/io.h>
 
 #include <linux/firmware.h>
+#include <linux/wait.h>
+#include <asm/byteorder.h>
 
 #include "smscoreapi.h"
 #include "sms-cards.h"
+#include "smsir.h"
+#include "smsendian.h"
 
 static int sms_dbg;
 module_param_named(debug, sms_dbg, int, 0644);
@@ -58,42 +62,6 @@ struct smscore_client_t {
         onremove_t              onremove_handler;
 };
 
-struct smscore_device_t {
-        struct list_head entry;
-
-        struct list_head clients;
-        struct list_head subclients;
-        spinlock_t              clientslock;
-
-        struct list_head buffers;
-        spinlock_t              bufferslock;
-        int                             num_buffers;
-
-        void                    *common_buffer;
-        int                             common_buffer_size;
-        dma_addr_t              common_buffer_phys;
-
-        void                    *context;
-        struct device   *device;
-
-        char                    devpath[32];
-        unsigned long   device_flags;
-
-        setmode_t               setmode_handler;
-        detectmode_t    detectmode_handler;
-        sendrequest_t   sendrequest_handler;
-        preload_t               preload_handler;
-        postload_t              postload_handler;
-
-        int                             mode, modes_supported;
-
-        struct completion version_ex_done, data_download_done, trigger_done;
-        struct completion init_device_done, reload_start_done, resume_done;
-
-        int board_id;
-        int led_state;
-};
-
 void smscore_set_board_id(struct smscore_device_t *core, int id)
 {
         core->board_id = id;
@@ -384,6 +352,13 @@ int smscore_register_device(struct smsdevice_params_t *params,
         init_completion(&dev->init_device_done);
         init_completion(&dev->reload_start_done);
         init_completion(&dev->resume_done);
+        init_completion(&dev->gpio_configuration_done);
+        init_completion(&dev->gpio_set_level_done);
+        init_completion(&dev->gpio_get_level_done);
+        init_completion(&dev->ir_init_done);
+
+        /* Buffer management */
+        init_waitqueue_head(&dev->buffer_mng_waitq);
 
         /* alloc common buffer */
         dev->common_buffer_size = params->buffer_size * params->num_buffers;
@@ -439,6 +414,71 @@ int smscore_register_device(struct smsdevice_params_t *params,
 }
 EXPORT_SYMBOL_GPL(smscore_register_device);
 
+
+static int smscore_sendrequest_and_wait(struct smscore_device_t *coredev,
+                void *buffer, size_t size, struct completion *completion) {
+        int rc = coredev->sendrequest_handler(coredev->context, buffer, size);
+        if (rc < 0) {
+                sms_info("sendrequest returned error %d", rc);
+                return rc;
+        }
+
+        return wait_for_completion_timeout(completion,
+                        msecs_to_jiffies(SMS_PROTOCOL_MAX_RAOUNDTRIP_MS)) ?
+                        0 : -ETIME;
+}
+
+/**
+ * Starts & enables IR operations
+ *
+ * @return 0 on success, < 0 on error.
+ */
+static int smscore_init_ir(struct smscore_device_t *coredev)
+{
+        int ir_io;
+        int rc;
+        void *buffer;
+
+        coredev->ir.input_dev = NULL;
+        ir_io = sms_get_board(smscore_get_board_id(coredev))->board_cfg.ir;
+        if (ir_io) {/* only if IR port exist we use IR sub-module */
+                sms_info("IR loading");
+                rc = sms_ir_init(coredev);
+
+                if      (rc != 0)
+                        sms_err("Error initialization DTV IR sub-module");
+                else {
+                        buffer = kmalloc(sizeof(struct SmsMsgData_ST2) +
+                                                SMS_DMA_ALIGNMENT,
+                                                GFP_KERNEL | GFP_DMA);
+                        if (buffer) {
+                                struct SmsMsgData_ST2 *msg =
+                                (struct SmsMsgData_ST2 *)
+                                SMS_ALIGN_ADDRESS(buffer);
+
+                                SMS_INIT_MSG(&msg->xMsgHeader,
+                                                MSG_SMS_START_IR_REQ,
+                                                sizeof(struct SmsMsgData_ST2));
+                                msg->msgData[0] = coredev->ir.controller;
+                                msg->msgData[1] = coredev->ir.timeout;
+
+                                smsendian_handle_tx_message(
+                                        (struct SmsMsgHdr_ST2 *)msg);
+                                rc = smscore_sendrequest_and_wait(coredev, msg,
+                                                msg->xMsgHeader. msgLength,
+                                                &coredev->ir_init_done);
+
+                                kfree(buffer);
+                        } else
+                                sms_err
+                                ("Sending IR initialization message failed");
+                }
+        } else
+                sms_info("IR port has not been detected");
+
+        return 0;
+}
+
 /**
  * sets initial device mode and notifies client hotplugs that device is ready
  *
@@ -459,6 +499,7 @@ int smscore_start_device(struct smscore_device_t *coredev)
         kmutex_lock(&g_smscore_deviceslock);
 
         rc = smscore_notify_callbacks(coredev, coredev->device, 1);
+        smscore_init_ir(coredev);
 
         sms_info("device %p started, rc %d", coredev, rc);
 
@@ -468,29 +509,19 @@ int smscore_start_device(struct smscore_device_t *coredev)
 }
 EXPORT_SYMBOL_GPL(smscore_start_device);
 
-static int smscore_sendrequest_and_wait(struct smscore_device_t *coredev,
-                                        void *buffer, size_t size,
-                                        struct completion *completion)
-{
-        int rc = coredev->sendrequest_handler(coredev->context, buffer, size);
-        if (rc < 0) {
-                sms_info("sendrequest returned error %d", rc);
-                return rc;
-        }
-
-        return wait_for_completion_timeout(completion,
-                                           msecs_to_jiffies(10000)) ?
-                                                0 : -ETIME;
-}
 
 static int smscore_load_firmware_family2(struct smscore_device_t *coredev,
                                          void *buffer, size_t size)
 {
         struct SmsFirmware_ST *firmware = (struct SmsFirmware_ST *) buffer;
         struct SmsMsgHdr_ST *msg;
-        u32 mem_address = firmware->StartAddress;
+        u32 mem_address;
         u8 *payload = firmware->Payload;
         int rc = 0;
+        firmware->StartAddress = le32_to_cpu(firmware->StartAddress);
+        firmware->Length = le32_to_cpu(firmware->Length);
+
+        mem_address = firmware->StartAddress;
 
         sms_info("loading FW to addr 0x%x size %d",
                  mem_address, firmware->Length);
@@ -657,6 +688,9 @@ void smscore_unregister_device(struct smscore_device_t *coredev)
 
         kmutex_lock(&g_smscore_deviceslock);
 
+        /* Release input device (IR) resources */
+        sms_ir_exit(coredev);
+
         smscore_notify_clients(coredev);
         smscore_notify_callbacks(coredev, NULL, 0);
 
@@ -664,7 +698,9 @@ void smscore_unregister_device(struct smscore_device_t *coredev)
          * onresponse must no longer be called */
 
         while (1) {
-                while ((cb = smscore_getbuffer(coredev))) {
+                while (!list_empty(&coredev->buffers)) {
+                        cb = (struct smscore_buffer_t *) coredev->buffers.next;
+                        list_del(&cb->entry);
                         kfree(cb);
                         num_buffers++;
                 }
@@ -685,8 +721,10 @@ void smscore_unregister_device(struct smscore_device_t *coredev)
 
         if (coredev->common_buffer)
                 dma_free_coherent(NULL, coredev->common_buffer_size,
-                                  coredev->common_buffer,
-                                  coredev->common_buffer_phys);
+                        coredev->common_buffer, coredev->common_buffer_phys);
+
+        if (coredev->fw_buf != NULL)
+                kfree(coredev->fw_buf);
 
         list_del(&coredev->entry);
         kfree(coredev);
@@ -746,7 +784,7 @@ static char *smscore_fw_lkup[][SMS_NUM_OF_DEVICE_TYPES] = {
         /*BDA*/
         {"none", "dvb_nova_12mhz.inp", "dvb_nova_12mhz_b0.inp", "none"},
         /*ISDBT*/
-        {"none", "isdbt_nova_12mhz.inp", "dvb_nova_12mhz.inp", "none"},
+        {"none", "isdbt_nova_12mhz.inp", "isdbt_nova_12mhz_b0.inp", "none"},
         /*ISDBTBDA*/
         {"none", "isdbt_nova_12mhz.inp", "isdbt_nova_12mhz_b0.inp", "none"},
         /*CMMB*/
@@ -870,7 +908,7 @@ int smscore_set_device_mode(struct smscore_device_t *coredev, int mode)
                 coredev->device_flags &= ~SMS_DEVICE_NOT_READY;
         }
 
-        if (rc != 0)
+        if (rc < 0)
                 sms_err("return error code %d.", rc);
         return rc;
 }
@@ -940,14 +978,11 @@ smscore_client_t *smscore_find_client(struct smscore_device_t *coredev,
  *
  */
 void smscore_onresponse(struct smscore_device_t *coredev,
-                        struct smscore_buffer_t *cb)
-{
-        struct SmsMsgHdr_ST *phdr =
-                (struct SmsMsgHdr_ST *)((u8 *) cb->p + cb->offset);
-        struct smscore_client_t *client =
-                smscore_find_client(coredev, phdr->msgType, phdr->msgDstId);
+                struct smscore_buffer_t *cb) {
+        struct SmsMsgHdr_ST *phdr = (struct SmsMsgHdr_ST *) ((u8 *) cb->p
+                        + cb->offset);
+        struct smscore_client_t *client;
         int rc = -EBUSY;
-
         static unsigned long last_sample_time; /* = 0; */
         static int data_total; /* = 0; */
         unsigned long time_now = jiffies_to_msecs(jiffies);
@@ -965,6 +1000,16 @@ void smscore_onresponse(struct smscore_device_t *coredev,
         }
 
         data_total += cb->size;
+        /* Do we need to re-route? */
+        if ((phdr->msgType == MSG_SMS_HO_PER_SLICES_IND) ||
+                        (phdr->msgType == MSG_SMS_TRANSMISSION_IND)) {
+                if (coredev->mode == DEVICE_MODE_DVBT_BDA)
+                        phdr->msgDstId = DVBT_BDA_CONTROL_MSG_ID;
+        }
+
+
+        client = smscore_find_client(coredev, phdr->msgType, phdr->msgDstId);
+
         /* If no client registered for type & id,
          * check for control client where type is not registered */
         if (client)
@@ -1009,6 +1054,35 @@ void smscore_onresponse(struct smscore_device_t *coredev,
                 case MSG_SMS_SLEEP_RESUME_COMP_IND:
                         complete(&coredev->resume_done);
                         break;
+                case MSG_SMS_GPIO_CONFIG_EX_RES:
+                        sms_debug("MSG_SMS_GPIO_CONFIG_EX_RES");
+                        complete(&coredev->gpio_configuration_done);
+                        break;
+                case MSG_SMS_GPIO_SET_LEVEL_RES:
+                        sms_debug("MSG_SMS_GPIO_SET_LEVEL_RES");
+                        complete(&coredev->gpio_set_level_done);
+                        break;
+                case MSG_SMS_GPIO_GET_LEVEL_RES:
+                {
+                        u32 *msgdata = (u32 *) phdr;
+                        coredev->gpio_get_res = msgdata[1];
+                        sms_debug("MSG_SMS_GPIO_GET_LEVEL_RES gpio level %d",
+                                        coredev->gpio_get_res);
+                        complete(&coredev->gpio_get_level_done);
+                        break;
+                }
+                case MSG_SMS_START_IR_RES:
+                        complete(&coredev->ir_init_done);
+                        break;
+                case MSG_SMS_IR_SAMPLES_IND:
+                        sms_ir_event(coredev,
+                                (const char *)
+                                ((char *)phdr
+                                + sizeof(struct SmsMsgHdr_ST)),
+                                (int)phdr->msgLength
+                                - sizeof(struct SmsMsgHdr_ST));
+                        break;
+
                 default:
                         break;
                 }
@@ -1030,12 +1104,24 @@ struct smscore_buffer_t *smscore_getbuffer(struct smscore_device_t *coredev)
         struct smscore_buffer_t *cb = NULL;
         unsigned long flags;
 
+        DEFINE_WAIT(wait);
+
         spin_lock_irqsave(&coredev->bufferslock, flags);
 
-        if (!list_empty(&coredev->buffers)) {
-                cb = (struct smscore_buffer_t *) coredev->buffers.next;
-                list_del(&cb->entry);
-        }
+        /* This function must return a valid buffer, since the buffer list is
+         * finite, we check that there is an available buffer, if not, we wait
+         * until such buffer become available.
+         */
+
+        prepare_to_wait(&coredev->buffer_mng_waitq, &wait, TASK_INTERRUPTIBLE);
+
+        if (list_empty(&coredev->buffers))
+                schedule();
+
+        finish_wait(&coredev->buffer_mng_waitq, &wait);
+
+        cb = (struct smscore_buffer_t *) coredev->buffers.next;
+        list_del(&cb->entry);
 
         spin_unlock_irqrestore(&coredev->bufferslock, flags);
 
@@ -1052,8 +1138,8 @@ EXPORT_SYMBOL_GPL(smscore_getbuffer);
  *
  */
 void smscore_putbuffer(struct smscore_device_t *coredev,
-                       struct smscore_buffer_t *cb)
-{
+                struct smscore_buffer_t *cb) {
+        wake_up_interruptible(&coredev->buffer_mng_waitq);
         list_add_locked(&cb->entry, &coredev->buffers, &coredev->bufferslock);
 }
 EXPORT_SYMBOL_GPL(smscore_putbuffer);
@@ -1210,8 +1296,9 @@ int smsclient_sendrequest(struct smscore_client_t *client,
 EXPORT_SYMBOL_GPL(smsclient_sendrequest);
 
 
+/* old GPIO managments implementation */
 int smscore_configure_gpio(struct smscore_device_t *coredev, u32 pin,
-                           struct smscore_gpio_config *pinconfig)
+                           struct smscore_config_gpio *pinconfig)
 {
         struct {
                 struct SmsMsgHdr_ST hdr;
@@ -1280,35 +1367,254 @@ int smscore_set_gpio(struct smscore_device_t *coredev, u32 pin, int level)
                                             &msg, sizeof(msg));
 }
 
-static int __init smscore_module_init(void)
-{
-        int rc = 0;
+/* new GPIO managment implementation */
+static int GetGpioPinParams(u32 PinNum, u32 *pTranslatedPinNum,
+                u32 *pGroupNum, u32 *pGroupCfg) {
+
+        *pGroupCfg = 1;
+
+        if (PinNum >= 0 && PinNum <= 1) {
+                *pTranslatedPinNum = 0;
+                *pGroupNum = 9;
+                *pGroupCfg = 2;
+        } else if (PinNum >= 2 && PinNum <= 6) {
+                *pTranslatedPinNum = 2;
+                *pGroupNum = 0;
+                *pGroupCfg = 2;
+        } else if (PinNum >= 7 && PinNum <= 11) {
+                *pTranslatedPinNum = 7;
+                *pGroupNum = 1;
+        } else if (PinNum >= 12 && PinNum <= 15) {
+                *pTranslatedPinNum = 12;
+                *pGroupNum = 2;
+                *pGroupCfg = 3;
+        } else if (PinNum == 16) {
+                *pTranslatedPinNum = 16;
+                *pGroupNum = 23;
+        } else if (PinNum >= 17 && PinNum <= 24) {
+                *pTranslatedPinNum = 17;
+                *pGroupNum = 3;
+        } else if (PinNum == 25) {
+                *pTranslatedPinNum = 25;
+                *pGroupNum = 6;
+        } else if (PinNum >= 26 && PinNum <= 28) {
+                *pTranslatedPinNum = 26;
+                *pGroupNum = 4;
+        } else if (PinNum == 29) {
+                *pTranslatedPinNum = 29;
+                *pGroupNum = 5;
+                *pGroupCfg = 2;
+        } else if (PinNum == 30) {
+                *pTranslatedPinNum = 30;
+                *pGroupNum = 8;
+        } else if (PinNum == 31) {
+                *pTranslatedPinNum = 31;
+                *pGroupNum = 17;
+        } else
+                return -1;
 
-        INIT_LIST_HEAD(&g_smscore_notifyees);
-        INIT_LIST_HEAD(&g_smscore_devices);
-        kmutex_init(&g_smscore_deviceslock);
+        *pGroupCfg <<= 24;
 
-        INIT_LIST_HEAD(&g_smscore_registry);
-        kmutex_init(&g_smscore_registrylock);
+        return 0;
+}
+
+int smscore_gpio_configure(struct smscore_device_t *coredev, u8 PinNum,
+                struct smscore_gpio_config *pGpioConfig) {
+
+        u32 totalLen;
+        u32 TranslatedPinNum;
+        u32 GroupNum;
+        u32 ElectricChar;
+        u32 groupCfg;
+        void *buffer;
+        int rc;
+
+        struct SetGpioMsg {
+                struct SmsMsgHdr_ST xMsgHeader;
+                u32 msgData[6];
+        } *pMsg;
+
+
+        if (PinNum > MAX_GPIO_PIN_NUMBER)
+                return -EINVAL;
+
+        if (pGpioConfig == NULL)
+                return -EINVAL;
+
+        totalLen = sizeof(struct SmsMsgHdr_ST) + (sizeof(u32) * 6);
+
+        buffer = kmalloc(totalLen + SMS_DMA_ALIGNMENT,
+                        GFP_KERNEL | GFP_DMA);
+        if (!buffer)
+                return -ENOMEM;
+
+        pMsg = (struct SetGpioMsg *) SMS_ALIGN_ADDRESS(buffer);
+
+        pMsg->xMsgHeader.msgSrcId = DVBT_BDA_CONTROL_MSG_ID;
+        pMsg->xMsgHeader.msgDstId = HIF_TASK;
+        pMsg->xMsgHeader.msgFlags = 0;
+        pMsg->xMsgHeader.msgLength = (u16) totalLen;
+        pMsg->msgData[0] = PinNum;
+
+        if (!(coredev->device_flags & SMS_DEVICE_FAMILY2)) {
+                pMsg->xMsgHeader.msgType = MSG_SMS_GPIO_CONFIG_REQ;
+                if (GetGpioPinParams(PinNum, &TranslatedPinNum, &GroupNum,
+                                &groupCfg) != 0)
+                        return -EINVAL;
+
+                pMsg->msgData[1] = TranslatedPinNum;
+                pMsg->msgData[2] = GroupNum;
+                ElectricChar = (pGpioConfig->PullUpDown)
+                                | (pGpioConfig->InputCharacteristics << 2)
+                                | (pGpioConfig->OutputSlewRate << 3)
+                                | (pGpioConfig->OutputDriving << 4);
+                pMsg->msgData[3] = ElectricChar;
+                pMsg->msgData[4] = pGpioConfig->Direction;
+                pMsg->msgData[5] = groupCfg;
+        } else {
+                pMsg->xMsgHeader.msgType = MSG_SMS_GPIO_CONFIG_EX_REQ;
+                pMsg->msgData[1] = pGpioConfig->PullUpDown;
+                pMsg->msgData[2] = pGpioConfig->OutputSlewRate;
+                pMsg->msgData[3] = pGpioConfig->OutputDriving;
+                pMsg->msgData[4] = pGpioConfig->Direction;
+                pMsg->msgData[5] = 0;
+        }
+
+        smsendian_handle_tx_message((struct SmsMsgHdr_ST *)pMsg);
+        rc = smscore_sendrequest_and_wait(coredev, pMsg, totalLen,
+                        &coredev->gpio_configuration_done);
+
+        if (rc != 0) {
+                if (rc == -ETIME)
+                        sms_err("smscore_gpio_configure timeout");
+                else
+                        sms_err("smscore_gpio_configure error");
+        }
+        kfree(buffer);
+
+        return rc;
+}
+
+int smscore_gpio_set_level(struct smscore_device_t *coredev, u8 PinNum,
+                u8 NewLevel) {
+
+        u32 totalLen;
+        int rc;
+        void *buffer;
+
+        struct SetGpioMsg {
+                struct SmsMsgHdr_ST xMsgHeader;
+                u32 msgData[3]; /* keep it 3 ! */
+        } *pMsg;
+
+        if ((NewLevel > 1) || (PinNum > MAX_GPIO_PIN_NUMBER) ||
+                        (PinNum > MAX_GPIO_PIN_NUMBER))
+                return -EINVAL;
 
+        totalLen = sizeof(struct SmsMsgHdr_ST) +
+                        (3 * sizeof(u32)); /* keep it 3 ! */
 
+        buffer = kmalloc(totalLen + SMS_DMA_ALIGNMENT,
+                        GFP_KERNEL | GFP_DMA);
+        if (!buffer)
+                return -ENOMEM;
 
+        pMsg = (struct SetGpioMsg *) SMS_ALIGN_ADDRESS(buffer);
 
+        pMsg->xMsgHeader.msgSrcId = DVBT_BDA_CONTROL_MSG_ID;
+        pMsg->xMsgHeader.msgDstId = HIF_TASK;
+        pMsg->xMsgHeader.msgFlags = 0;
+        pMsg->xMsgHeader.msgType = MSG_SMS_GPIO_SET_LEVEL_REQ;
+        pMsg->xMsgHeader.msgLength = (u16) totalLen;
+        pMsg->msgData[0] = PinNum;
+        pMsg->msgData[1] = NewLevel;
 
+        /* Send message to SMS */
+        smsendian_handle_tx_message((struct SmsMsgHdr_ST *)pMsg);
+        rc = smscore_sendrequest_and_wait(coredev, pMsg, totalLen,
+                        &coredev->gpio_set_level_done);
+
+        if (rc != 0) {
+                if (rc == -ETIME)
+                        sms_err("smscore_gpio_set_level timeout");
+                else
+                        sms_err("smscore_gpio_set_level error");
+        }
+        kfree(buffer);
 
         return rc;
-        sms_debug("rc %d", rc);
+}
+
+int smscore_gpio_get_level(struct smscore_device_t *coredev, u8 PinNum,
+                u8 *level) {
+
+        u32 totalLen;
+        int rc;
+        void *buffer;
+
+        struct SetGpioMsg {
+                struct SmsMsgHdr_ST xMsgHeader;
+                u32 msgData[2];
+        } *pMsg;
+
+
+        if (PinNum > MAX_GPIO_PIN_NUMBER)
+                return -EINVAL;
+
+        totalLen = sizeof(struct SmsMsgHdr_ST) + (2 * sizeof(u32));
+
+        buffer = kmalloc(totalLen + SMS_DMA_ALIGNMENT,
+                        GFP_KERNEL | GFP_DMA);
+        if (!buffer)
+                return -ENOMEM;
+
+        pMsg = (struct SetGpioMsg *) SMS_ALIGN_ADDRESS(buffer);
+
+        pMsg->xMsgHeader.msgSrcId = DVBT_BDA_CONTROL_MSG_ID;
+        pMsg->xMsgHeader.msgDstId = HIF_TASK;
+        pMsg->xMsgHeader.msgFlags = 0;
+        pMsg->xMsgHeader.msgType = MSG_SMS_GPIO_GET_LEVEL_REQ;
+        pMsg->xMsgHeader.msgLength = (u16) totalLen;
+        pMsg->msgData[0] = PinNum;
+        pMsg->msgData[1] = 0;
+
+        /* Send message to SMS */
+        smsendian_handle_tx_message((struct SmsMsgHdr_ST *)pMsg);
+        rc = smscore_sendrequest_and_wait(coredev, pMsg, totalLen,
+                        &coredev->gpio_get_level_done);
+
+        if (rc != 0) {
+                if (rc == -ETIME)
+                        sms_err("smscore_gpio_get_level timeout");
+                else
+                        sms_err("smscore_gpio_get_level error");
+        }
+        kfree(buffer);
+
+        /* Its a race between other gpio_get_level() and the copy of the single
+         * global 'coredev->gpio_get_res' to  the function's variable 'level'
+         */
+        *level = coredev->gpio_get_res;
 
         return rc;
 }
 
-static void __exit smscore_module_exit(void)
+static int __init smscore_module_init(void)
 {
+        int rc = 0;
 
+        INIT_LIST_HEAD(&g_smscore_notifyees);
+        INIT_LIST_HEAD(&g_smscore_devices);
+        kmutex_init(&g_smscore_deviceslock);
 
+        INIT_LIST_HEAD(&g_smscore_registry);
+        kmutex_init(&g_smscore_registrylock);
 
+        return rc;
+}
 
-
+static void __exit smscore_module_exit(void)
+{
         kmutex_lock(&g_smscore_deviceslock);
         while (!list_empty(&g_smscore_notifyees)) {
                 struct smscore_device_notifyee_t *notifyee =
diff --git a/drivers/media/dvb/siano/smscoreapi.h b/drivers/media/dvb/siano/smscoreapi.h
index 548de9056e8b..f1108c64e895 100644
--- a/drivers/media/dvb/siano/smscoreapi.h
+++ b/drivers/media/dvb/siano/smscoreapi.h
@@ -1,26 +1,26 @@
-/*
- *  Driver for the Siano SMS1xxx USB dongle
- *
- *  author: Anatoly Greenblat
- *
- *  Copyright (c), 2005-2008 Siano Mobile Silicon, Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation;
- *
- *  Software distributed under the License is distributed on an "AS IS"
- *  basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
- *
- *  See the GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __smscoreapi_h__
-#define __smscoreapi_h__
+/****************************************************************
+
+Siano Mobile Silicon, Inc.
+MDTV receiver kernel modules.
+Copyright (C) 2006-2008, Uri Shkolnik, Anatoly Greenblat
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 2 of the License, or
+(at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+****************************************************************/
+
+#ifndef __SMS_CORE_API_H__
+#define __SMS_CORE_API_H__
 
 #include <linux/version.h>
 #include <linux/device.h>
@@ -28,14 +28,13 @@
 #include <linux/mm.h>
 #include <linux/scatterlist.h>
 #include <linux/types.h>
-#include <asm/page.h>
 #include <linux/mutex.h>
+#include <linux/wait.h>
+#include <linux/timer.h>
 
-#include "dmxdev.h"
-#include "dvbdev.h"
-#include "dvb_demux.h"
-#include "dvb_frontend.h"
+#include <asm/page.h>
 
+#include "smsir.h"
 
 #define kmutex_init(_p_) mutex_init(_p_)
 #define kmutex_lock(_p_) mutex_lock(_p_)
@@ -46,13 +45,14 @@
 #define min(a, b) (((a) < (b)) ? (a) : (b))
 #endif
 
-#define SMS_ALLOC_ALIGNMENT                                     128
-#define SMS_DMA_ALIGNMENT                                       16
+#define SMS_PROTOCOL_MAX_RAOUNDTRIP_MS                  (10000)
+#define SMS_ALLOC_ALIGNMENT                             128
+#define SMS_DMA_ALIGNMENT                               16
 #define SMS_ALIGN_ADDRESS(addr) \
         ((((uintptr_t)(addr)) + (SMS_DMA_ALIGNMENT-1)) & ~(SMS_DMA_ALIGNMENT-1))
 
-#define SMS_DEVICE_FAMILY2                                      1
-#define SMS_ROM_NO_RESPONSE                                     2
+#define SMS_DEVICE_FAMILY2                              1
+#define SMS_ROM_NO_RESPONSE                             2
 #define SMS_DEVICE_NOT_READY                            0x8000000
 
 enum sms_device_type_st {
@@ -83,13 +83,13 @@ typedef void (*onremove_t)(void *context);
 struct smscore_buffer_t {
         /* public members, once passed to clients can be changed freely */
         struct list_head entry;
-        int                             size;
-        int                             offset;
+        int size;
+        int offset;
 
         /* private members, read-only for clients */
-        void                    *p;
-        dma_addr_t              phys;
-        unsigned long   offset_in_common;
+        void *p;
+        dma_addr_t phys;
+        unsigned long offset_in_common;
 };
 
 struct smsdevice_params_t {
@@ -116,10 +116,63 @@ struct smsclient_params_t {
         int                             data_type;
         onresponse_t    onresponse_handler;
         onremove_t              onremove_handler;
-
         void                    *context;
 };
 
+struct smscore_device_t {
+        struct list_head entry;
+
+        struct list_head clients;
+        struct list_head subclients;
+        spinlock_t clientslock;
+
+        struct list_head buffers;
+        spinlock_t bufferslock;
+        int num_buffers;
+
+        void *common_buffer;
+        int common_buffer_size;
+        dma_addr_t common_buffer_phys;
+
+        void *context;
+        struct device *device;
+
+        char devpath[32];
+        unsigned long device_flags;
+
+        setmode_t setmode_handler;
+        detectmode_t detectmode_handler;
+        sendrequest_t sendrequest_handler;
+        preload_t preload_handler;
+        postload_t postload_handler;
+
+        int mode, modes_supported;
+
+        /* host <--> device messages */
+        struct completion version_ex_done, data_download_done, trigger_done;
+        struct completion init_device_done, reload_start_done, resume_done;
+        struct completion gpio_configuration_done, gpio_set_level_done;
+        struct completion gpio_get_level_done, ir_init_done;
+
+        /* Buffer management */
+        wait_queue_head_t buffer_mng_waitq;
+
+        /* GPIO */
+        int gpio_get_res;
+
+        /* Target hardware board */
+        int board_id;
+
+        /* Firmware */
+        u8 *fw_buf;
+        u32 fw_buf_size;
+
+        /* Infrared (IR) */
+        struct ir_t ir;
+
+        int led_state;
+};
+
 /* GPIO definitions for antenna frequency domain control (SMS8021) */
 #define SMS_ANTENNA_GPIO_0                                      1
 #define SMS_ANTENNA_GPIO_1                                      0
@@ -154,18 +207,15 @@ struct smsclient_params_t {
 #define MSG_SMS_INIT_DEVICE_RES                         579
 #define MSG_SMS_ADD_PID_FILTER_REQ                      601
 #define MSG_SMS_ADD_PID_FILTER_RES                      602
-#define MSG_SMS_REMOVE_PID_FILTER_REQ           603
-#define MSG_SMS_REMOVE_PID_FILTER_RES           604
-#define MSG_SMS_DAB_CHANNEL                                     607
-#define MSG_SMS_GET_PID_FILTER_LIST_REQ         608
-#define MSG_SMS_GET_PID_FILTER_LIST_RES         609
-#define MSG_SMS_GET_STATISTICS_REQ                      615
-#define MSG_SMS_GET_STATISTICS_RES                      616
-#define MSG_SMS_SET_ANTENNA_CONFIG_REQ          651
-#define MSG_SMS_SET_ANTENNA_CONFIG_RES          652
-#define MSG_SMS_GET_STATISTICS_EX_REQ           653
-#define MSG_SMS_GET_STATISTICS_EX_RES           654
-#define MSG_SMS_SLEEP_RESUME_COMP_IND           655
+#define MSG_SMS_REMOVE_PID_FILTER_REQ                   603
+#define MSG_SMS_REMOVE_PID_FILTER_RES                   604
+#define MSG_SMS_DAB_CHANNEL                             607
+#define MSG_SMS_GET_PID_FILTER_LIST_REQ                 608
+#define MSG_SMS_GET_PID_FILTER_LIST_RES                 609
+#define MSG_SMS_HO_PER_SLICES_IND                       630
+#define MSG_SMS_SET_ANTENNA_CONFIG_REQ                  651
+#define MSG_SMS_SET_ANTENNA_CONFIG_RES                  652
+#define MSG_SMS_SLEEP_RESUME_COMP_IND                   655
 #define MSG_SMS_DATA_DOWNLOAD_REQ                       660
 #define MSG_SMS_DATA_DOWNLOAD_RES                       661
 #define MSG_SMS_SWDOWNLOAD_TRIGGER_REQ          664
@@ -190,14 +240,31 @@ struct smsclient_params_t {
 #define MSG_SMS_GPIO_CONFIG_EX_RES                      713
 #define MSG_SMS_ISDBT_TUNE_REQ                          776
 #define MSG_SMS_ISDBT_TUNE_RES                          777
+#define MSG_SMS_TRANSMISSION_IND                        782
+#define MSG_SMS_START_IR_REQ                            800
+#define MSG_SMS_START_IR_RES                            801
+#define MSG_SMS_IR_SAMPLES_IND                          802
+#define MSG_SMS_SIGNAL_DETECTED_IND                     827
+#define MSG_SMS_NO_SIGNAL_IND                           828
 
 #define SMS_INIT_MSG_EX(ptr, type, src, dst, len) do { \
         (ptr)->msgType = type; (ptr)->msgSrcId = src; (ptr)->msgDstId = dst; \
         (ptr)->msgLength = len; (ptr)->msgFlags = 0; \
 } while (0)
+
 #define SMS_INIT_MSG(ptr, type, len) \
         SMS_INIT_MSG_EX(ptr, type, 0, HIF_TASK, len)
 
+enum SMS_DVB3_EVENTS {
+        DVB3_EVENT_INIT = 0,
+        DVB3_EVENT_SLEEP,
+        DVB3_EVENT_HOTPLUG,
+        DVB3_EVENT_FE_LOCK,
+        DVB3_EVENT_FE_UNLOCK,
+        DVB3_EVENT_UNC_OK,
+        DVB3_EVENT_UNC_ERR
+};
+
 enum SMS_DEVICE_MODE {
         DEVICE_MODE_NONE = -1,
         DEVICE_MODE_DVBT = 0,
@@ -221,8 +288,13 @@ struct SmsMsgHdr_ST {
 };
 
 struct SmsMsgData_ST {
-        struct SmsMsgHdr_ST     xMsgHeader;
-        u32                     msgData[1];
+        struct SmsMsgHdr_ST xMsgHeader;
+        u32 msgData[1];
+};
+
+struct SmsMsgData_ST2 {
+        struct SmsMsgHdr_ST xMsgHeader;
+        u32 msgData[2];
 };
 
 struct SmsDataDownload_ST {
@@ -238,11 +310,12 @@ struct SmsVersionRes_ST {
         u8              Step; /* 0 - Step A */
         u8              MetalFix; /* 0 - Metal 0 */
 
-        u8              FirmwareId; /* 0xFF � ROM, otherwise the
-                                     * value indicated by
-                                     * SMSHOSTLIB_DEVICE_MODES_E */
-        u8              SupportedProtocols; /* Bitwise OR combination of
+        /* FirmwareId 0xFF if ROM, otherwise the
+         * value indicated by SMSHOSTLIB_DEVICE_MODES_E */
+        u8 FirmwareId;
+        /* SupportedProtocols Bitwise OR combination of
                                              * supported protocols */
+        u8 SupportedProtocols;
 
         u8              VersionMajor;
         u8              VersionMinor;
@@ -264,86 +337,219 @@ struct SmsFirmware_ST {
         u8                      Payload[1];
 };
 
-struct SMSHOSTLIB_STATISTICS_ST {
-        u32 Reserved; /* Reserved */
+/* Statistics information returned as response for
+ * SmsHostApiGetStatistics_Req */
+struct SMSHOSTLIB_STATISTICS_S {
+        u32 Reserved;           /* Reserved */
 
         /* Common parameters */
-        u32 IsRfLocked; /* 0 - not locked, 1 - locked */
-        u32 IsDemodLocked; /* 0 - not locked, 1 - locked */
-        u32 IsExternalLNAOn; /* 0 - external LNA off, 1 - external LNA on */
+        u32 IsRfLocked;         /* 0 - not locked, 1 - locked */
+        u32 IsDemodLocked;      /* 0 - not locked, 1 - locked */
+        u32 IsExternalLNAOn;    /* 0 - external LNA off, 1 - external LNA on */
 
         /* Reception quality */
-        s32  SNR; /* dB */
-        u32 BER; /* Post Viterbi BER [1E-5] */
-        u32 FIB_CRC;    /* CRC errors percentage, valid only for DAB */
-        u32 TS_PER; /* Transport stream PER, 0xFFFFFFFF indicate N/A,
-                     * valid only for DVB-T/H */
-        u32 MFER; /* DVB-H frame error rate in percentage,
-                   * 0xFFFFFFFF indicate N/A, valid only for DVB-H */
-        s32  RSSI; /* dBm */
-        s32  InBandPwr; /* In band power in dBM */
-        s32  CarrierOffset; /* Carrier Offset in bin/1024 */
-
-        /* Transmission parameters, valid only for DVB-T/H */
-        u32 Frequency; /* Frequency in Hz */
-        u32 Bandwidth; /* Bandwidth in MHz */
-        u32 TransmissionMode; /* Transmission Mode, for DAB modes 1-4,
-                               * for DVB-T/H FFT mode carriers in Kilos */
-        u32 ModemState; /* from SMS_DvbModemState_ET */
-        u32 GuardInterval; /* Guard Interval, 1 divided by value */
-        u32 CodeRate; /* Code Rate from SMS_DvbModemState_ET */
-        u32 LPCodeRate; /* Low Priority Code Rate from SMS_DvbModemState_ET */
-        u32 Hierarchy; /* Hierarchy from SMS_Hierarchy_ET */
-        u32 Constellation; /* Constellation from SMS_Constellation_ET */
+        s32 SNR;                /* dB */
+        u32 BER;                /* Post Viterbi BER [1E-5] */
+        u32 FIB_CRC;            /* CRC errors percentage, valid only for DAB */
+        u32 TS_PER;             /* Transport stream PER,
+        0xFFFFFFFF indicate N/A, valid only for DVB-T/H */
+        u32 MFER;               /* DVB-H frame error rate in percentage,
+        0xFFFFFFFF indicate N/A, valid only for DVB-H */
+        s32 RSSI;               /* dBm */
+        s32 InBandPwr;          /* In band power in dBM */
+        s32 CarrierOffset;      /* Carrier Offset in bin/1024 */
+
+        /* Transmission parameters */
+        u32 Frequency;          /* Frequency in Hz */
+        u32 Bandwidth;          /* Bandwidth in MHz, valid only for DVB-T/H */
+        u32 TransmissionMode;   /* Transmission Mode, for DAB modes 1-4,
+        for DVB-T/H FFT mode carriers in Kilos */
+        u32 ModemState;         /* from SMSHOSTLIB_DVB_MODEM_STATE_ET,
+        valid only for DVB-T/H */
+        u32 GuardInterval;      /* Guard Interval from
+        SMSHOSTLIB_GUARD_INTERVALS_ET,  valid only for DVB-T/H */
+        u32 CodeRate;           /* Code Rate from SMSHOSTLIB_CODE_RATE_ET,
+        valid only for DVB-T/H */
+        u32 LPCodeRate;         /* Low Priority Code Rate from
+        SMSHOSTLIB_CODE_RATE_ET, valid only for DVB-T/H */
+        u32 Hierarchy;          /* Hierarchy from SMSHOSTLIB_HIERARCHY_ET,
+        valid only for DVB-T/H */
+        u32 Constellation;      /* Constellation from
+        SMSHOSTLIB_CONSTELLATION_ET, valid only for DVB-T/H */
 
         /* Burst parameters, valid only for DVB-H */
-        u32 BurstSize; /* Current burst size in bytes */
-        u32 BurstDuration; /* Current burst duration in mSec */
-        u32 BurstCycleTime; /* Current burst cycle time in mSec */
-        u32 CalculatedBurstCycleTime; /* Current burst cycle time in mSec,
-                                       * as calculated by demodulator */
-        u32 NumOfRows; /* Number of rows in MPE table */
-        u32 NumOfPaddCols; /* Number of padding columns in MPE table */
-        u32 NumOfPunctCols; /* Number of puncturing columns in MPE table */
-        /* Burst parameters */
-        u32 ErrorTSPackets; /* Number of erroneous transport-stream packets */
-        u32 TotalTSPackets; /* Total number of transport-stream packets */
-        u32 NumOfValidMpeTlbs; /* Number of MPE tables which do not include
-                                * errors after MPE RS decoding */
-        u32 NumOfInvalidMpeTlbs; /* Number of MPE tables which include errors
-                                  * after MPE RS decoding */
-        u32 NumOfCorrectedMpeTlbs; /* Number of MPE tables which were corrected
-                                    * by MPE RS decoding */
-
+        u32 BurstSize;          /* Current burst size in bytes,
+        valid only for DVB-H */
+        u32 BurstDuration;      /* Current burst duration in mSec,
+        valid only for DVB-H */
+        u32 BurstCycleTime;     /* Current burst cycle time in mSec,
+        valid only for DVB-H */
+        u32 CalculatedBurstCycleTime;/* Current burst cycle time in mSec,
+        as calculated by demodulator, valid only for DVB-H */
+        u32 NumOfRows;          /* Number of rows in MPE table,
+        valid only for DVB-H */
+        u32 NumOfPaddCols;      /* Number of padding columns in MPE table,
+        valid only for DVB-H */
+        u32 NumOfPunctCols;     /* Number of puncturing columns in MPE table,
+        valid only for DVB-H */
+        u32 ErrorTSPackets;     /* Number of erroneous
+        transport-stream packets */
+        u32 TotalTSPackets;     /* Total number of transport-stream packets */
+        u32 NumOfValidMpeTlbs;  /* Number of MPE tables which do not include
+        errors after MPE RS decoding */
+        u32 NumOfInvalidMpeTlbs;/* Number of MPE tables which include errors
+        after MPE RS decoding */
+        u32 NumOfCorrectedMpeTlbs;/* Number of MPE tables which were
+        corrected by MPE RS decoding */
         /* Common params */
-        u32 BERErrorCount; /* Number of errornous SYNC bits. */
-        u32 BERBitCount; /* Total number of SYNC bits. */
+        u32 BERErrorCount;      /* Number of errornous SYNC bits. */
+        u32 BERBitCount;        /* Total number of SYNC bits. */
 
         /* Interface information */
-        u32 SmsToHostTxErrors; /* Total number of transmission errors. */
+        u32 SmsToHostTxErrors;  /* Total number of transmission errors. */
 
         /* DAB/T-DMB */
-        u32 PreBER; /* DAB/T-DMB only: Pre Viterbi BER [1E-5] */
+        u32 PreBER;             /* DAB/T-DMB only: Pre Viterbi BER [1E-5] */
 
         /* DVB-H TPS parameters */
-        u32 CellId; /* TPS Cell ID in bits 15..0, bits 31..16 zero;
-                     * if set to 0xFFFFFFFF cell_id not yet recovered */
+        u32 CellId;             /* TPS Cell ID in bits 15..0, bits 31..16 zero;
+         if set to 0xFFFFFFFF cell_id not yet recovered */
+        u32 DvbhSrvIndHP;       /* DVB-H service indication info, bit 1 -
+        Time Slicing indicator, bit 0 - MPE-FEC indicator */
+        u32 DvbhSrvIndLP;       /* DVB-H service indication info, bit 1 -
+        Time Slicing indicator, bit 0 - MPE-FEC indicator */
 
+        u32 NumMPEReceived;     /* DVB-H, Num MPE section received */
+
+        u32 ReservedFields[10]; /* Reserved */
 };
 
-struct SmsMsgStatisticsInfo_ST {
-        u32 RequestResult;
+struct PID_STATISTICS_DATA_S {
+        struct PID_BURST_S {
+                u32 size;
+                u32 padding_cols;
+                u32 punct_cols;
+                u32 duration;
+                u32 cycle;
+                u32 calc_cycle;
+        } burst;
+
+        u32 tot_tbl_cnt;
+        u32 invalid_tbl_cnt;
+        u32 tot_cor_tbl;
+};
 
-        struct SMSHOSTLIB_STATISTICS_ST Stat;
+struct PID_DATA_S {
+        u32 pid;
+        u32 num_rows;
+        struct PID_STATISTICS_DATA_S pid_statistics;
+};
 
-        /* Split the calc of the SNR in DAB */
-        u32 Signal; /* dB */
-        u32 Noise; /* dB */
+#define CORRECT_STAT_RSSI(_stat) ((_stat).RSSI *= -1)
+#define CORRECT_STAT_BANDWIDTH(_stat) (_stat.Bandwidth = 8 - _stat.Bandwidth)
+#define CORRECT_STAT_TRANSMISSON_MODE(_stat) \
+        if (_stat.TransmissionMode == 0) \
+                _stat.TransmissionMode = 2; \
+        else if (_stat.TransmissionMode == 1) \
+                _stat.TransmissionMode = 8; \
+                else \
+                        _stat.TransmissionMode = 4;
+
+struct TRANSMISSION_STATISTICS_S {
+        u32 Frequency;          /* Frequency in Hz */
+        u32 Bandwidth;          /* Bandwidth in MHz */
+        u32 TransmissionMode;   /* FFT mode carriers in Kilos */
+        u32 GuardInterval;      /* Guard Interval from
+        SMSHOSTLIB_GUARD_INTERVALS_ET */
+        u32 CodeRate;           /* Code Rate from SMSHOSTLIB_CODE_RATE_ET */
+        u32 LPCodeRate;         /* Low Priority Code Rate from
+        SMSHOSTLIB_CODE_RATE_ET */
+        u32 Hierarchy;          /* Hierarchy from SMSHOSTLIB_HIERARCHY_ET */
+        u32 Constellation;      /* Constellation from
+        SMSHOSTLIB_CONSTELLATION_ET */
 
+        /* DVB-H TPS parameters */
+        u32 CellId;             /* TPS Cell ID in bits 15..0, bits 31..16 zero;
+         if set to 0xFFFFFFFF cell_id not yet recovered */
+        u32 DvbhSrvIndHP;       /* DVB-H service indication info, bit 1 -
+         Time Slicing indicator, bit 0 - MPE-FEC indicator */
+        u32 DvbhSrvIndLP;       /* DVB-H service indication info, bit 1 -
+         Time Slicing indicator, bit 0 - MPE-FEC indicator */
+        u32 IsDemodLocked;      /* 0 - not locked, 1 - locked */
 };
 
+struct RECEPTION_STATISTICS_S {
+        u32 IsRfLocked;         /* 0 - not locked, 1 - locked */
+        u32 IsDemodLocked;      /* 0 - not locked, 1 - locked */
+        u32 IsExternalLNAOn;    /* 0 - external LNA off, 1 - external LNA on */
+
+        u32 ModemState;         /* from SMSHOSTLIB_DVB_MODEM_STATE_ET */
+        s32 SNR;                /* dB */
+        u32 BER;                /* Post Viterbi BER [1E-5] */
+        u32 BERErrorCount;      /* Number of erronous SYNC bits. */
+        u32 BERBitCount;        /* Total number of SYNC bits. */
+        u32 TS_PER;             /* Transport stream PER,
+        0xFFFFFFFF indicate N/A */
+        u32 MFER;               /* DVB-H frame error rate in percentage,
+        0xFFFFFFFF indicate N/A, valid only for DVB-H */
+        s32 RSSI;               /* dBm */
+        s32 InBandPwr;          /* In band power in dBM */
+        s32 CarrierOffset;      /* Carrier Offset in bin/1024 */
+        u32 ErrorTSPackets;     /* Number of erroneous
+        transport-stream packets */
+        u32 TotalTSPackets;     /* Total number of transport-stream packets */
+
+        s32 MRC_SNR;            /* dB */
+        s32 MRC_RSSI;           /* dBm */
+        s32 MRC_InBandPwr;      /* In band power in dBM */
+};
 
-struct smscore_gpio_config {
+
+/* Statistics information returned as response for
+ * SmsHostApiGetStatisticsEx_Req for DVB applications, SMS1100 and up */
+struct SMSHOSTLIB_STATISTICS_DVB_S {
+        /* Reception */
+        struct RECEPTION_STATISTICS_S ReceptionData;
+
+        /* Transmission parameters */
+        struct TRANSMISSION_STATISTICS_S TransmissionData;
+
+        /* Burst parameters, valid only for DVB-H */
+#define SRVM_MAX_PID_FILTERS 8
+        struct PID_DATA_S PidData[SRVM_MAX_PID_FILTERS];
+};
+
+struct SRVM_SIGNAL_STATUS_S {
+        u32 result;
+        u32 snr;
+        u32 tsPackets;
+        u32 etsPackets;
+        u32 constellation;
+        u32 hpCode;
+        u32 tpsSrvIndLP;
+        u32 tpsSrvIndHP;
+        u32 cellId;
+        u32 reason;
+
+        s32 inBandPower;
+        u32 requestId;
+};
+
+struct SMSHOSTLIB_I2C_REQ_ST {
+        u32     DeviceAddress; /* I2c device address */
+        u32     WriteCount; /* number of bytes to write */
+        u32     ReadCount; /* number of bytes to read */
+        u8      Data[1];
+};
+
+struct SMSHOSTLIB_I2C_RES_ST {
+        u32     Status; /* non-zero value in case of failure */
+        u32     ReadCount; /* number of bytes read */
+        u8      Data[1];
+};
+
+
+struct smscore_config_gpio {
 #define SMS_GPIO_DIRECTION_INPUT  0
 #define SMS_GPIO_DIRECTION_OUTPUT 1
         u8 direction;
@@ -369,6 +575,47 @@ struct smscore_gpio_config {
         u8 outputdriving;
 };
 
+struct smscore_gpio_config {
+#define SMS_GPIO_DIRECTION_INPUT  0
+#define SMS_GPIO_DIRECTION_OUTPUT 1
+        u8 Direction;
+
+#define SMS_GPIO_PULL_UP_DOWN_NONE     0
+#define SMS_GPIO_PULL_UP_DOWN_PULLDOWN 1
+#define SMS_GPIO_PULL_UP_DOWN_PULLUP   2
+#define SMS_GPIO_PULL_UP_DOWN_KEEPER   3
+        u8 PullUpDown;
+
+#define SMS_GPIO_INPUT_CHARACTERISTICS_NORMAL  0
+#define SMS_GPIO_INPUT_CHARACTERISTICS_SCHMITT 1
+        u8 InputCharacteristics;
+
+#define SMS_GPIO_OUTPUT_SLEW_RATE_SLOW          1 /* 10xx */
+#define SMS_GPIO_OUTPUT_SLEW_RATE_FAST          0 /* 10xx */
+
+
+#define SMS_GPIO_OUTPUT_SLEW_RATE_0_45_V_NS     0 /* 11xx */
+#define SMS_GPIO_OUTPUT_SLEW_RATE_0_9_V_NS      1 /* 11xx */
+#define SMS_GPIO_OUTPUT_SLEW_RATE_1_7_V_NS      2 /* 11xx */
+#define SMS_GPIO_OUTPUT_SLEW_RATE_3_3_V_NS      3 /* 11xx */
+        u8 OutputSlewRate;
+
+#define SMS_GPIO_OUTPUT_DRIVING_S_4mA           0 /* 10xx */
+#define SMS_GPIO_OUTPUT_DRIVING_S_8mA           1 /* 10xx */
+#define SMS_GPIO_OUTPUT_DRIVING_S_12mA          2 /* 10xx */
+#define SMS_GPIO_OUTPUT_DRIVING_S_16mA          3 /* 10xx */
+
+#define SMS_GPIO_OUTPUT_DRIVING_1_5mA           0 /* 11xx */
+#define SMS_GPIO_OUTPUT_DRIVING_2_8mA           1 /* 11xx */
+#define SMS_GPIO_OUTPUT_DRIVING_4mA             2 /* 11xx */
+#define SMS_GPIO_OUTPUT_DRIVING_7mA             3 /* 11xx */
+#define SMS_GPIO_OUTPUT_DRIVING_10mA            4 /* 11xx */
+#define SMS_GPIO_OUTPUT_DRIVING_11mA            5 /* 11xx */
+#define SMS_GPIO_OUTPUT_DRIVING_14mA            6 /* 11xx */
+#define SMS_GPIO_OUTPUT_DRIVING_16mA            7 /* 11xx */
+        u8 OutputDriving;
+};
+
 extern void smscore_registry_setmode(char *devpath, int mode);
 extern int smscore_registry_getmode(char *devpath);
 
@@ -410,10 +657,19 @@ struct smscore_buffer_t *smscore_getbuffer(struct smscore_device_t *coredev);
 extern void smscore_putbuffer(struct smscore_device_t *coredev,
                               struct smscore_buffer_t *cb);
 
+/* old GPIO managment */
 int smscore_configure_gpio(struct smscore_device_t *coredev, u32 pin,
-                           struct smscore_gpio_config *pinconfig);
+                           struct smscore_config_gpio *pinconfig);
 int smscore_set_gpio(struct smscore_device_t *coredev, u32 pin, int level);
 
+/* new GPIO managment */
+extern int smscore_gpio_configure(struct smscore_device_t *coredev, u8 PinNum,
+                struct smscore_gpio_config *pGpioConfig);
+extern int smscore_gpio_set_level(struct smscore_device_t *coredev, u8 PinNum,
+                u8 NewLevel);
+extern int smscore_gpio_get_level(struct smscore_device_t *coredev, u8 PinNum,
+                u8 *level);
+
 void smscore_set_board_id(struct smscore_device_t *core, int id);
 int smscore_get_board_id(struct smscore_device_t *core);
 
@@ -442,4 +698,4 @@ int smscore_led_state(struct smscore_device_t *core, int led);
         dprintk(KERN_DEBUG, DBG_ADV, fmt, ##arg)
 
 
-#endif /* __smscoreapi_h__ */
+#endif /* __SMS_CORE_API_H__ */
diff --git a/drivers/media/dvb/siano/smsdvb.c b/drivers/media/dvb/siano/smsdvb.c
index ba080b95befb..3ee1c3902c56 100644
--- a/drivers/media/dvb/siano/smsdvb.c
+++ b/drivers/media/dvb/siano/smsdvb.c
@@ -1,28 +1,34 @@
-/*
- *  Driver for the Siano SMS1xxx USB dongle
- *
- *  Author: Uri Shkolni
- *
- *  Copyright (c), 2005-2008 Siano Mobile Silicon, Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation;
- *
- *  Software distributed under the License is distributed on an "AS IS"
- *  basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
- *
- *  See the GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
+/****************************************************************
+
+Siano Mobile Silicon, Inc.
+MDTV receiver kernel modules.
+Copyright (C) 2006-2008, Uri Shkolnik
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 2 of the License, or
+(at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+****************************************************************/
 
 #include <linux/module.h>
 #include <linux/init.h>
 
+#include "dmxdev.h"
+#include "dvbdev.h"
+#include "dvb_demux.h"
+#include "dvb_frontend.h"
+
 #include "smscoreapi.h"
+#include "smsendian.h"
 #include "sms-cards.h"
 
 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
@@ -39,12 +45,15 @@ struct smsdvb_client_t {
         struct dvb_frontend     frontend;
 
         fe_status_t             fe_status;
-        int                     fe_ber, fe_snr, fe_unc, fe_signal_strength;
 
-        struct completion       tune_done, stat_done;
+        struct completion       tune_done;
 
         /* todo: save freq/band instead whole struct */
         struct dvb_frontend_parameters fe_params;
+
+        struct SMSHOSTLIB_STATISTICS_DVB_S sms_stat_dvb;
+        int event_fe_state;
+        int event_unc_state;
 };
 
 static struct list_head g_smsdvb_clients;
@@ -54,11 +63,69 @@ static int sms_dbg;
 module_param_named(debug, sms_dbg, int, 0644);
 MODULE_PARM_DESC(debug, "set debug level (info=1, adv=2 (or-able))");
 
+/* Events that may come from DVB v3 adapter */
+static void sms_board_dvb3_event(struct smsdvb_client_t *client,
+                enum SMS_DVB3_EVENTS event) {
+
+        struct smscore_device_t *coredev = client->coredev;
+        switch (event) {
+        case DVB3_EVENT_INIT:
+                sms_debug("DVB3_EVENT_INIT");
+                sms_board_event(coredev, BOARD_EVENT_BIND);
+                break;
+        case DVB3_EVENT_SLEEP:
+                sms_debug("DVB3_EVENT_SLEEP");
+                sms_board_event(coredev, BOARD_EVENT_POWER_SUSPEND);
+                break;
+        case DVB3_EVENT_HOTPLUG:
+                sms_debug("DVB3_EVENT_HOTPLUG");
+                sms_board_event(coredev, BOARD_EVENT_POWER_INIT);
+                break;
+        case DVB3_EVENT_FE_LOCK:
+                if (client->event_fe_state != DVB3_EVENT_FE_LOCK) {
+                        client->event_fe_state = DVB3_EVENT_FE_LOCK;
+                        sms_debug("DVB3_EVENT_FE_LOCK");
+                        sms_board_event(coredev, BOARD_EVENT_FE_LOCK);
+                }
+                break;
+        case DVB3_EVENT_FE_UNLOCK:
+                if (client->event_fe_state != DVB3_EVENT_FE_UNLOCK) {
+                        client->event_fe_state = DVB3_EVENT_FE_UNLOCK;
+                        sms_debug("DVB3_EVENT_FE_UNLOCK");
+                        sms_board_event(coredev, BOARD_EVENT_FE_UNLOCK);
+                }
+                break;
+        case DVB3_EVENT_UNC_OK:
+                if (client->event_unc_state != DVB3_EVENT_UNC_OK) {
+                        client->event_unc_state = DVB3_EVENT_UNC_OK;
+                        sms_debug("DVB3_EVENT_UNC_OK");
+                        sms_board_event(coredev, BOARD_EVENT_MULTIPLEX_OK);
+                }
+                break;
+        case DVB3_EVENT_UNC_ERR:
+                if (client->event_unc_state != DVB3_EVENT_UNC_ERR) {
+                        client->event_unc_state = DVB3_EVENT_UNC_ERR;
+                        sms_debug("DVB3_EVENT_UNC_ERR");
+                        sms_board_event(coredev, BOARD_EVENT_MULTIPLEX_ERRORS);
+                }
+                break;
+
+        default:
+                sms_err("Unknown dvb3 api event");
+                break;
+        }
+}
+
 static int smsdvb_onresponse(void *context, struct smscore_buffer_t *cb)
 {
         struct smsdvb_client_t *client = (struct smsdvb_client_t *) context;
-        struct SmsMsgHdr_ST *phdr =
-                (struct SmsMsgHdr_ST *)(((u8 *) cb->p) + cb->offset);
+        struct SmsMsgHdr_ST *phdr = (struct SmsMsgHdr_ST *) (((u8 *) cb->p)
+                        + cb->offset);
+        u32 *pMsgData = (u32 *) phdr + 1;
+        /*u32 MsgDataLen = phdr->msgLength - sizeof(struct SmsMsgHdr_ST);*/
+        bool is_status_update = false;
+
+        smsendian_handle_rx_message((struct SmsMsgData_ST *) phdr);
 
         switch (phdr->msgType) {
         case MSG_SMS_DVBT_BDA_DATA:
@@ -70,43 +137,110 @@ static int smsdvb_onresponse(void *context, struct smscore_buffer_t *cb)
                 complete(&client->tune_done);
                 break;
 
-        case MSG_SMS_GET_STATISTICS_RES:
-        {
-                struct SmsMsgStatisticsInfo_ST *p =
-                        (struct SmsMsgStatisticsInfo_ST *)(phdr + 1);
-
-                if (p->Stat.IsDemodLocked) {
-                        client->fe_status = FE_HAS_SIGNAL |
-                                            FE_HAS_CARRIER |
-                                            FE_HAS_VITERBI |
-                                            FE_HAS_SYNC |
-                                            FE_HAS_LOCK;
-
-                        client->fe_snr = p->Stat.SNR;
-                        client->fe_ber = p->Stat.BER;
-                        client->fe_unc = p->Stat.BERErrorCount;
-
-                        if (p->Stat.InBandPwr < -95)
-                                client->fe_signal_strength = 0;
-                        else if (p->Stat.InBandPwr > -29)
-                                client->fe_signal_strength = 100;
-                        else
-                                client->fe_signal_strength =
-                                        (p->Stat.InBandPwr + 95) * 3 / 2;
+        case MSG_SMS_SIGNAL_DETECTED_IND:
+                sms_info("MSG_SMS_SIGNAL_DETECTED_IND");
+                client->sms_stat_dvb.TransmissionData.IsDemodLocked = true;
+                is_status_update = true;
+                break;
+
+        case MSG_SMS_NO_SIGNAL_IND:
+                sms_info("MSG_SMS_NO_SIGNAL_IND");
+                client->sms_stat_dvb.TransmissionData.IsDemodLocked = false;
+                is_status_update = true;
+                break;
+
+        case MSG_SMS_TRANSMISSION_IND: {
+                sms_info("MSG_SMS_TRANSMISSION_IND");
+
+                pMsgData++;
+                memcpy(&client->sms_stat_dvb.TransmissionData, pMsgData,
+                                sizeof(struct TRANSMISSION_STATISTICS_S));
+
+                /* Mo need to correct guard interval
+                 * (as opposed to old statistics message).
+                 */
+                CORRECT_STAT_BANDWIDTH(client->sms_stat_dvb.TransmissionData);
+                CORRECT_STAT_TRANSMISSON_MODE(
+                                client->sms_stat_dvb.TransmissionData);
+                is_status_update = true;
+                break;
+        }
+        case MSG_SMS_HO_PER_SLICES_IND: {
+                struct RECEPTION_STATISTICS_S *pReceptionData =
+                                &client->sms_stat_dvb.ReceptionData;
+                struct SRVM_SIGNAL_STATUS_S SignalStatusData;
+
+                /*sms_info("MSG_SMS_HO_PER_SLICES_IND");*/
+                pMsgData++;
+                SignalStatusData.result = pMsgData[0];
+                SignalStatusData.snr = pMsgData[1];
+                SignalStatusData.inBandPower = (s32) pMsgData[2];
+                SignalStatusData.tsPackets = pMsgData[3];
+                SignalStatusData.etsPackets = pMsgData[4];
+                SignalStatusData.constellation = pMsgData[5];
+                SignalStatusData.hpCode = pMsgData[6];
+                SignalStatusData.tpsSrvIndLP = pMsgData[7] & 0x03;
+                SignalStatusData.tpsSrvIndHP = pMsgData[8] & 0x03;
+                SignalStatusData.cellId = pMsgData[9] & 0xFFFF;
+                SignalStatusData.reason = pMsgData[10];
+                SignalStatusData.requestId = pMsgData[11];
+                pReceptionData->IsRfLocked = pMsgData[16];
+                pReceptionData->IsDemodLocked = pMsgData[17];
+                pReceptionData->ModemState = pMsgData[12];
+                pReceptionData->SNR = pMsgData[1];
+                pReceptionData->BER = pMsgData[13];
+                pReceptionData->RSSI = pMsgData[14];
+                CORRECT_STAT_RSSI(client->sms_stat_dvb.ReceptionData);
+
+                pReceptionData->InBandPwr = (s32) pMsgData[2];
+                pReceptionData->CarrierOffset = (s32) pMsgData[15];
+                pReceptionData->TotalTSPackets = pMsgData[3];
+                pReceptionData->ErrorTSPackets = pMsgData[4];
+
+                /* TS PER */
+                if ((SignalStatusData.tsPackets + SignalStatusData.etsPackets)
+                                > 0) {
+                        pReceptionData->TS_PER = (SignalStatusData.etsPackets
+                                        * 100) / (SignalStatusData.tsPackets
+                                        + SignalStatusData.etsPackets);
                 } else {
-                        client->fe_status = 0;
-                        client->fe_snr =
-                        client->fe_ber =
-                        client->fe_unc =
-                        client->fe_signal_strength = 0;
+                        pReceptionData->TS_PER = 0;
                 }
 
-                complete(&client->stat_done);
-                break;
-        } }
+                pReceptionData->BERBitCount = pMsgData[18];
+                pReceptionData->BERErrorCount = pMsgData[19];
 
+                pReceptionData->MRC_SNR = pMsgData[20];
+                pReceptionData->MRC_InBandPwr = pMsgData[21];
+                pReceptionData->MRC_RSSI = pMsgData[22];
+
+                is_status_update = true;
+                break;
+        }
+        }
         smscore_putbuffer(client->coredev, cb);
 
+        if (is_status_update) {
+                if (client->sms_stat_dvb.ReceptionData.IsDemodLocked) {
+                        client->fe_status = FE_HAS_SIGNAL | FE_HAS_CARRIER
+                                | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+                        sms_board_dvb3_event(client, DVB3_EVENT_FE_LOCK);
+                        if (client->sms_stat_dvb.ReceptionData.ErrorTSPackets
+                                        == 0)
+                                sms_board_dvb3_event(client, DVB3_EVENT_UNC_OK);
+                        else
+                                sms_board_dvb3_event(client,
+                                                DVB3_EVENT_UNC_ERR);
+
+                } else {
+                        /*client->fe_status =
+                                (phdr->msgType == MSG_SMS_NO_SIGNAL_IND) ?
+                                0 : FE_HAS_SIGNAL;*/
+                        client->fe_status = 0;
+                        sms_board_dvb3_event(client, DVB3_EVENT_FE_UNLOCK);
+                }
+        }
+
         return 0;
 }
 
@@ -149,6 +283,7 @@ static int smsdvb_start_feed(struct dvb_demux_feed *feed)
         PidMsg.xMsgHeader.msgLength = sizeof(PidMsg);
         PidMsg.msgData[0] = feed->pid;
 
+        smsendian_handle_tx_message((struct SmsMsgHdr_ST *)&PidMsg);
         return smsclient_sendrequest(client->smsclient,
                                      &PidMsg, sizeof(PidMsg));
 }
@@ -169,6 +304,7 @@ static int smsdvb_stop_feed(struct dvb_demux_feed *feed)
         PidMsg.xMsgHeader.msgLength = sizeof(PidMsg);
         PidMsg.msgData[0] = feed->pid;
 
+        smsendian_handle_tx_message((struct SmsMsgHdr_ST *)&PidMsg);
         return smsclient_sendrequest(client->smsclient,
                                      &PidMsg, sizeof(PidMsg));
 }
@@ -177,7 +313,10 @@ static int smsdvb_sendrequest_and_wait(struct smsdvb_client_t *client,
                                         void *buffer, size_t size,
                                         struct completion *completion)
 {
-        int rc = smsclient_sendrequest(client->smsclient, buffer, size);
+        int rc;
+
+        smsendian_handle_tx_message((struct SmsMsgHdr_ST *)buffer);
+        rc = smsclient_sendrequest(client->smsclient, buffer, size);
         if (rc < 0)
                 return rc;
 
@@ -186,83 +325,61 @@ static int smsdvb_sendrequest_and_wait(struct smsdvb_client_t *client,
                                                 0 : -ETIME;
 }
 
-static int smsdvb_send_statistics_request(struct smsdvb_client_t *client)
-{
-        struct SmsMsgHdr_ST Msg = { MSG_SMS_GET_STATISTICS_REQ,
-                             DVBT_BDA_CONTROL_MSG_ID,
-                             HIF_TASK, sizeof(struct SmsMsgHdr_ST), 0 };
-        int ret = smsdvb_sendrequest_and_wait(client, &Msg, sizeof(Msg),
-                                              &client->stat_done);
-        if (ret < 0)
-                return ret;
-
-        if (client->fe_status & FE_HAS_LOCK)
-                sms_board_led_feedback(client->coredev,
-                                       (client->fe_unc == 0) ?
-                                       SMS_LED_HI : SMS_LED_LO);
-        else
-                sms_board_led_feedback(client->coredev, SMS_LED_OFF);
-        return ret;
-}
-
 static int smsdvb_read_status(struct dvb_frontend *fe, fe_status_t *stat)
 {
-        struct smsdvb_client_t *client =
-                container_of(fe, struct smsdvb_client_t, frontend);
-        int rc = smsdvb_send_statistics_request(client);
+        struct smsdvb_client_t *client;
+        client = container_of(fe, struct smsdvb_client_t, frontend);
 
-        if (!rc)
-                *stat = client->fe_status;
+        *stat = client->fe_status;
 
-        return rc;
+        return 0;
 }
 
 static int smsdvb_read_ber(struct dvb_frontend *fe, u32 *ber)
 {
-        struct smsdvb_client_t *client =
-                container_of(fe, struct smsdvb_client_t, frontend);
-        int rc = smsdvb_send_statistics_request(client);
+        struct smsdvb_client_t *client;
+        client = container_of(fe, struct smsdvb_client_t, frontend);
 
-        if (!rc)
-                *ber = client->fe_ber;
+        *ber = client->sms_stat_dvb.ReceptionData.BER;
 
-        return rc;
+        return 0;
 }
 
 static int smsdvb_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
 {
-        struct smsdvb_client_t *client =
-                container_of(fe, struct smsdvb_client_t, frontend);
-        int rc = smsdvb_send_statistics_request(client);
+        struct smsdvb_client_t *client;
+        client = container_of(fe, struct smsdvb_client_t, frontend);
 
-        if (!rc)
-                *strength = client->fe_signal_strength;
+        if (client->sms_stat_dvb.ReceptionData.InBandPwr < -95)
+                *strength = 0;
+                else if (client->sms_stat_dvb.ReceptionData.InBandPwr > -29)
+                        *strength = 100;
+                else
+                        *strength =
+                                (client->sms_stat_dvb.ReceptionData.InBandPwr
+                                + 95) * 3 / 2;
 
-        return rc;
+        return 0;
 }
 
 static int smsdvb_read_snr(struct dvb_frontend *fe, u16 *snr)
 {
-        struct smsdvb_client_t *client =
-                container_of(fe, struct smsdvb_client_t, frontend);
-        int rc = smsdvb_send_statistics_request(client);
+        struct smsdvb_client_t *client;
+        client = container_of(fe, struct smsdvb_client_t, frontend);
 
-        if (!rc)
-                *snr = client->fe_snr;
+        *snr = client->sms_stat_dvb.ReceptionData.SNR;
 
-        return rc;
+        return 0;
 }
 
 static int smsdvb_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
 {
-        struct smsdvb_client_t *client =
-                container_of(fe, struct smsdvb_client_t, frontend);
-        int rc = smsdvb_send_statistics_request(client);
+        struct smsdvb_client_t *client;
+        client = container_of(fe, struct smsdvb_client_t, frontend);
 
-        if (!rc)
-                *ucblocks = client->fe_unc;
+        *ucblocks = client->sms_stat_dvb.ReceptionData.ErrorTSPackets;
 
-        return rc;
+        return 0;
 }
 
 static int smsdvb_get_tune_settings(struct dvb_frontend *fe,
@@ -286,12 +403,15 @@ static int smsdvb_set_frontend(struct dvb_frontend *fe,
                 struct SmsMsgHdr_ST     Msg;
                 u32             Data[3];
         } Msg;
-        int ret;
 
-        Msg.Msg.msgSrcId  = DVBT_BDA_CONTROL_MSG_ID;
-        Msg.Msg.msgDstId  = HIF_TASK;
-        Msg.Msg.msgFlags  = 0;
-        Msg.Msg.msgType   = MSG_SMS_RF_TUNE_REQ;
+        client->fe_status = FE_HAS_SIGNAL;
+        client->event_fe_state = -1;
+        client->event_unc_state = -1;
+
+        Msg.Msg.msgSrcId = DVBT_BDA_CONTROL_MSG_ID;
+        Msg.Msg.msgDstId = HIF_TASK;
+        Msg.Msg.msgFlags = 0;
+        Msg.Msg.msgType = MSG_SMS_RF_TUNE_REQ;
         Msg.Msg.msgLength = sizeof(Msg);
         Msg.Data[0] = fep->frequency;
         Msg.Data[2] = 12000000;
@@ -307,24 +427,6 @@ static int smsdvb_set_frontend(struct dvb_frontend *fe,
         default: return -EINVAL;
         }
 
-        /* Disable LNA, if any. An error is returned if no LNA is present */
-        ret = sms_board_lna_control(client->coredev, 0);
-        if (ret == 0) {
-                fe_status_t status;
-
-                /* tune with LNA off at first */
-                ret = smsdvb_sendrequest_and_wait(client, &Msg, sizeof(Msg),
-                                                  &client->tune_done);
-
-                smsdvb_read_status(fe, &status);
-
-                if (status & FE_HAS_LOCK)
-                        return ret;
-
-                /* previous tune didnt lock - enable LNA and tune again */
-                sms_board_lna_control(client->coredev, 1);
-        }
-
         return smsdvb_sendrequest_and_wait(client, &Msg, sizeof(Msg),
                                            &client->tune_done);
 }
@@ -349,8 +451,7 @@ static int smsdvb_init(struct dvb_frontend *fe)
         struct smsdvb_client_t *client =
                 container_of(fe, struct smsdvb_client_t, frontend);
 
-        sms_board_power(client->coredev, 1);
-
+        sms_board_dvb3_event(client, DVB3_EVENT_INIT);
         return 0;
 }
 
@@ -359,8 +460,7 @@ static int smsdvb_sleep(struct dvb_frontend *fe)
         struct smsdvb_client_t *client =
                 container_of(fe, struct smsdvb_client_t, frontend);
 
-        sms_board_led_feedback(client->coredev, SMS_LED_OFF);
-        sms_board_power(client->coredev, 0);
+        sms_board_dvb3_event(client, DVB3_EVENT_SLEEP);
 
         return 0;
 }
@@ -485,7 +585,6 @@ static int smsdvb_hotplug(struct smscore_device_t *coredev,
         client->coredev = coredev;
 
         init_completion(&client->tune_done);
-        init_completion(&client->stat_done);
 
         kmutex_lock(&g_smsdvb_clientslock);
 
@@ -493,8 +592,11 @@ static int smsdvb_hotplug(struct smscore_device_t *coredev,
 
         kmutex_unlock(&g_smsdvb_clientslock);
 
-        sms_info("success");
+        client->event_fe_state = -1;
+        client->event_unc_state = -1;
+        sms_board_dvb3_event(client, DVB3_EVENT_HOTPLUG);
 
+        sms_info("success");
         sms_board_setup(coredev);
 
         return 0;
@@ -547,5 +649,5 @@ module_init(smsdvb_module_init);
 module_exit(smsdvb_module_exit);
 
 MODULE_DESCRIPTION("SMS DVB subsystem adaptation module");
-MODULE_AUTHOR("Siano Mobile Silicon, INC. (uris@siano-ms.com)");
+MODULE_AUTHOR("Siano Mobile Silicon, Inc. (uris@siano-ms.com)");
 MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/siano/smsendian.c b/drivers/media/dvb/siano/smsendian.c
new file mode 100644
index 000000000000..457b6d02ef85
--- /dev/null
+++ b/drivers/media/dvb/siano/smsendian.c
@@ -0,0 +1,102 @@
+/****************************************************************
+
+ Siano Mobile Silicon, Inc.
+ MDTV receiver kernel modules.
+ Copyright (C) 2006-2009, Uri Shkolnik
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+ ****************************************************************/
+
+#include <asm/byteorder.h>
+
+#include "smsendian.h"
+#include "smscoreapi.h"
+
+void smsendian_handle_tx_message(void *buffer)
+{
+#ifdef __BIG_ENDIAN
+        struct SmsMsgData_ST *msg = (struct SmsMsgData_ST *)buffer;
+        int i;
+        int msgWords;
+
+        switch (msg->xMsgHeader.msgType) {
+        case MSG_SMS_DATA_DOWNLOAD_REQ:
+        {
+                msg->msgData[0] = le32_to_cpu(msg->msgData[0]);
+                break;
+        }
+
+        default:
+                msgWords = (msg->xMsgHeader.msgLength -
+                                sizeof(struct SmsMsgHdr_ST))/4;
+
+                for (i = 0; i < msgWords; i++)
+                        msg->msgData[i] = le32_to_cpu(msg->msgData[i]);
+
+                break;
+        }
+#endif /* __BIG_ENDIAN */
+}
+EXPORT_SYMBOL_GPL(smsendian_handle_tx_message);
+
+void smsendian_handle_rx_message(void *buffer)
+{
+#ifdef __BIG_ENDIAN
+        struct SmsMsgData_ST *msg = (struct SmsMsgData_ST *)buffer;
+        int i;
+        int msgWords;
+
+        switch (msg->xMsgHeader.msgType) {
+        case MSG_SMS_GET_VERSION_EX_RES:
+        {
+                struct SmsVersionRes_ST *ver =
+                        (struct SmsVersionRes_ST *) msg;
+                ver->ChipModel = le16_to_cpu(ver->ChipModel);
+                break;
+        }
+
+        case MSG_SMS_DVBT_BDA_DATA:
+        case MSG_SMS_DAB_CHANNEL:
+        case MSG_SMS_DATA_MSG:
+        {
+                break;
+        }
+
+        default:
+        {
+                msgWords = (msg->xMsgHeader.msgLength -
+                                sizeof(struct SmsMsgHdr_ST))/4;
+
+                for (i = 0; i < msgWords; i++)
+                        msg->msgData[i] = le32_to_cpu(msg->msgData[i]);
+
+                break;
+        }
+        }
+#endif /* __BIG_ENDIAN */
+}
+EXPORT_SYMBOL_GPL(smsendian_handle_rx_message);
+
+void smsendian_handle_message_header(void *msg)
+{
+#ifdef __BIG_ENDIAN
+        struct SmsMsgHdr_ST *phdr = (struct SmsMsgHdr_ST *)msg;
+
+        phdr->msgType = le16_to_cpu(phdr->msgType);
+        phdr->msgLength = le16_to_cpu(phdr->msgLength);
+        phdr->msgFlags = le16_to_cpu(phdr->msgFlags);
+#endif /* __BIG_ENDIAN */
+}
+EXPORT_SYMBOL_GPL(smsendian_handle_message_header);
diff --git a/drivers/media/dvb/siano/smsendian.h b/drivers/media/dvb/siano/smsendian.h
new file mode 100644
index 000000000000..1624d6fd367b
--- /dev/null
+++ b/drivers/media/dvb/siano/smsendian.h
@@ -0,0 +1,32 @@
+/****************************************************************
+
+Siano Mobile Silicon, Inc.
+MDTV receiver kernel modules.
+Copyright (C) 2006-2009, Uri Shkolnik
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 2 of the License, or
+(at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+****************************************************************/
+
+#ifndef __SMS_ENDIAN_H__
+#define __SMS_ENDIAN_H__
+
+#include <asm/byteorder.h>
+
+extern void smsendian_handle_tx_message(void *buffer);
+extern void smsendian_handle_rx_message(void *buffer);
+extern void smsendian_handle_message_header(void *msg);
+
+#endif /* __SMS_ENDIAN_H__ */
+
diff --git a/drivers/media/dvb/siano/smsir.c b/drivers/media/dvb/siano/smsir.c
new file mode 100644
index 000000000000..e3d776feeaca
--- /dev/null
+++ b/drivers/media/dvb/siano/smsir.c
@@ -0,0 +1,301 @@
+/****************************************************************
+
+ Siano Mobile Silicon, Inc.
+ MDTV receiver kernel modules.
+ Copyright (C) 2006-2009, Uri Shkolnik
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+ ****************************************************************/
+
+
+#include <linux/types.h>
+#include <linux/input.h>
+
+#include "smscoreapi.h"
+#include "smsir.h"
+#include "sms-cards.h"
+
+/* In order to add new IR remote control -
+ * 1) Add it to the <enum ir_kb_type> @ smsir,h,
+ * 2) Add its map to keyboard_layout_maps below
+ * 3) Set your board (sms-cards sub-module) to use it
+ */
+
+static struct keyboard_layout_map_t keyboard_layout_maps[] = {
+                [SMS_IR_KB_DEFAULT_TV] = {
+                        .ir_protocol = IR_RC5,
+                        .rc5_kbd_address = KEYBOARD_ADDRESS_TV1,
+                        .keyboard_layout_map = {
+                                        KEY_0, KEY_1, KEY_2,
+                                        KEY_3, KEY_4, KEY_5,
+                                        KEY_6, KEY_7, KEY_8,
+                                        KEY_9, 0, 0, KEY_POWER,
+                                        KEY_MUTE, 0, 0,
+                                        KEY_VOLUMEUP, KEY_VOLUMEDOWN,
+                                        KEY_BRIGHTNESSUP,
+                                        KEY_BRIGHTNESSDOWN, KEY_CHANNELUP,
+                                        KEY_CHANNELDOWN,
+                                        0, 0, 0, 0, 0, 0, 0, 0,
+                                        0, 0, 0, 0, 0, 0, 0, 0,
+                                        0, 0, 0, 0, 0, 0, 0, 0,
+                                        0, 0, 0, 0, 0, 0, 0, 0,
+                                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+                        }
+                },
+                [SMS_IR_KB_HCW_SILVER] = {
+                        .ir_protocol = IR_RC5,
+                        .rc5_kbd_address = KEYBOARD_ADDRESS_LIGHTING1,
+                        .keyboard_layout_map = {
+                                        KEY_0, KEY_1, KEY_2,
+                                        KEY_3, KEY_4, KEY_5,
+                                        KEY_6, KEY_7, KEY_8,
+                                        KEY_9, KEY_TEXT, KEY_RED,
+                                        KEY_RADIO, KEY_MENU,
+                                        KEY_SUBTITLE,
+                                        KEY_MUTE, KEY_VOLUMEUP,
+                                        KEY_VOLUMEDOWN, KEY_PREVIOUS, 0,
+                                        KEY_UP, KEY_DOWN, KEY_LEFT,
+                                        KEY_RIGHT, KEY_VIDEO, KEY_AUDIO,
+                                        KEY_MHP, KEY_EPG, KEY_TV,
+                                        0, KEY_NEXTSONG, KEY_EXIT,
+                                        KEY_CHANNELUP,  KEY_CHANNELDOWN,
+                                        KEY_CHANNEL, 0,
+                                        KEY_PREVIOUSSONG, KEY_ENTER,
+                                        KEY_SLEEP, 0, 0, KEY_BLUE,
+                                        0, 0, 0, 0, KEY_GREEN, 0,
+                                        KEY_PAUSE, 0, KEY_REWIND,
+                                        0, KEY_FASTFORWARD, KEY_PLAY,
+                                        KEY_STOP, KEY_RECORD,
+                                        KEY_YELLOW, 0, 0, KEY_SELECT,
+                                        KEY_ZOOM, KEY_POWER, 0, 0
+                        }
+                },
+                { } /* Terminating entry */
+};
+
+u32 ir_pos;
+u32     ir_word;
+u32 ir_toggle;
+
+#define RC5_PUSH_BIT(dst, bit, pos)     \
+        { dst <<= 1; dst |= bit; pos++; }
+
+
+static void sms_ir_rc5_event(struct smscore_device_t *coredev,
+                                u32 toggle, u32 addr, u32 cmd)
+{
+        bool toggle_changed;
+        u16 keycode;
+
+        sms_log("IR RC5 word: address %d, command %d, toggle %d",
+                                addr, cmd, toggle);
+
+        toggle_changed = ir_toggle != toggle;
+        /* keep toggle */
+        ir_toggle = toggle;
+
+        if (addr !=
+                keyboard_layout_maps[coredev->ir.ir_kb_type].rc5_kbd_address)
+                return; /* Check for valid address */
+
+        keycode =
+                keyboard_layout_maps
+                [coredev->ir.ir_kb_type].keyboard_layout_map[cmd];
+
+        if (!toggle_changed &&
+                        (keycode != KEY_VOLUMEUP && keycode != KEY_VOLUMEDOWN))
+                return; /* accept only repeated volume, reject other keys */
+
+        sms_log("kernel input keycode (from ir) %d", keycode);
+        input_report_key(coredev->ir.input_dev, keycode, 1);
+        input_sync(coredev->ir.input_dev);
+
+}
+
+/* decode raw bit pattern to RC5 code */
+/* taken from ir-functions.c */
+static u32 ir_rc5_decode(unsigned int code)
+{
+/*      unsigned int org_code = code;*/
+        unsigned int pair;
+        unsigned int rc5 = 0;
+        int i;
+
+        for (i = 0; i < 14; ++i) {
+                pair = code & 0x3;
+                code >>= 2;
+
+                rc5 <<= 1;
+                switch (pair) {
+                case 0:
+                case 2:
+                        break;
+                case 1:
+                        rc5 |= 1;
+                        break;
+                case 3:
+/*      dprintk(1, "ir-common: ir_rc5_decode(%x) bad code\n", org_code);*/
+                        sms_log("bad code");
+                        return 0;
+                }
+        }
+/*
+        dprintk(1, "ir-common: code=%x, rc5=%x, start=%x,
+                toggle=%x, address=%x, "
+                "instr=%x\n", rc5, org_code, RC5_START(rc5),
+                RC5_TOGGLE(rc5), RC5_ADDR(rc5), RC5_INSTR(rc5));
+*/
+        return rc5;
+}
+
+static void sms_rc5_parse_word(struct smscore_device_t *coredev)
+{
+        #define RC5_START(x)    (((x)>>12)&3)
+        #define RC5_TOGGLE(x)   (((x)>>11)&1)
+        #define RC5_ADDR(x)     (((x)>>6)&0x1F)
+        #define RC5_INSTR(x)    ((x)&0x3F)
+
+        int i, j;
+        u32 rc5_word = 0;
+
+        /* Reverse the IR word direction */
+        for (i = 0 ; i < 28 ; i++)
+                RC5_PUSH_BIT(rc5_word, (ir_word>>i)&1, j)
+
+        rc5_word = ir_rc5_decode(rc5_word);
+        /* sms_log("temp = 0x%x, rc5_code = 0x%x", ir_word, rc5_word); */
+
+        sms_ir_rc5_event(coredev,
+                                RC5_TOGGLE(rc5_word),
+                                RC5_ADDR(rc5_word),
+                                RC5_INSTR(rc5_word));
+}
+
+
+static void sms_rc5_accumulate_bits(struct smscore_device_t *coredev,
+                s32 ir_sample)
+{
+        #define RC5_TIME_GRANULARITY    200
+        #define RC5_DEF_BIT_TIME                889
+        #define RC5_MAX_SAME_BIT_CONT   4
+        #define RC5_WORD_LEN                    27 /* 28 bit */
+
+        u32 i, j;
+        s32 delta_time;
+        u32 time = (ir_sample > 0) ? ir_sample : (0-ir_sample);
+        u32 level = (ir_sample < 0) ? 0 : 1;
+
+        for (i = RC5_MAX_SAME_BIT_CONT; i > 0; i--) {
+                delta_time = time - (i*RC5_DEF_BIT_TIME) + RC5_TIME_GRANULARITY;
+                if (delta_time < 0)
+                        continue; /* not so many consecutive bits */
+                if (delta_time > (2 * RC5_TIME_GRANULARITY)) {
+                        /* timeout */
+                        if (ir_pos == (RC5_WORD_LEN-1))
+                                /* complete last bit */
+                                RC5_PUSH_BIT(ir_word, level, ir_pos)
+
+                        if (ir_pos == RC5_WORD_LEN)
+                                sms_rc5_parse_word(coredev);
+                        else if (ir_pos) /* timeout within a word */
+                                sms_log("IR error parsing a word");
+
+                        ir_pos = 0;
+                        ir_word = 0;
+                        /* sms_log("timeout %d", time); */
+                        break;
+                }
+                /* The time is within the range of this number of bits */
+                for (j = 0 ; j < i ; j++)
+                        RC5_PUSH_BIT(ir_word, level, ir_pos)
+
+                break;
+        }
+}
+
+void sms_ir_event(struct smscore_device_t *coredev, const char *buf, int len)
+{
+        #define IR_DATA_RECEIVE_MAX_LEN 520 /* 128*4 + 4 + 4 */
+        u32 i;
+        enum ir_protocol ir_protocol =
+                        keyboard_layout_maps[coredev->ir.ir_kb_type]
+                                             .ir_protocol;
+        s32 *samples;
+        int count = len>>2;
+
+        samples = (s32 *)buf;
+/*      sms_log("IR buffer received, length = %d", count);*/
+
+        for (i = 0; i < count; i++)
+                if (ir_protocol == IR_RC5)
+                        sms_rc5_accumulate_bits(coredev, samples[i]);
+        /*  IR_RCMM not implemented */
+}
+
+int sms_ir_init(struct smscore_device_t *coredev)
+{
+        struct input_dev *input_dev;
+
+        sms_log("Allocating input device");
+        input_dev = input_allocate_device();
+        if (!input_dev) {
+                sms_err("Not enough memory");
+                return -ENOMEM;
+        }
+
+        coredev->ir.input_dev = input_dev;
+        coredev->ir.ir_kb_type =
+                sms_get_board(smscore_get_board_id(coredev))->ir_kb_type;
+        coredev->ir.keyboard_layout_map =
+                keyboard_layout_maps[coredev->ir.ir_kb_type].
+                                keyboard_layout_map;
+        sms_log("IR remote keyboard type is %d", coredev->ir.ir_kb_type);
+
+        coredev->ir.controller = 0;     /* Todo: vega/nova SPI number */
+        coredev->ir.timeout = IR_DEFAULT_TIMEOUT;
+        sms_log("IR port %d, timeout %d ms",
+                        coredev->ir.controller, coredev->ir.timeout);
+
+        snprintf(coredev->ir.name,
+                                IR_DEV_NAME_MAX_LEN,
+                                "SMS IR w/kbd type %d",
+                                coredev->ir.ir_kb_type);
+        input_dev->name = coredev->ir.name;
+        input_dev->phys = coredev->ir.name;
+        input_dev->dev.parent = coredev->device;
+
+        /* Key press events only */
+        input_dev->evbit[0] = BIT_MASK(EV_KEY);
+        input_dev->keybit[BIT_WORD(BTN_0)] = BIT_MASK(BTN_0);
+
+        sms_log("Input device (IR) %s is set for key events", input_dev->name);
+
+        if (input_register_device(input_dev)) {
+                sms_err("Failed to register device");
+                input_free_device(input_dev);
+                return -EACCES;
+        }
+
+        return 0;
+}
+
+void sms_ir_exit(struct smscore_device_t *coredev)
+{
+        if (coredev->ir.input_dev)
+                input_unregister_device(coredev->ir.input_dev);
+
+        sms_log("");
+}
+
diff --git a/drivers/media/dvb/siano/smsir.h b/drivers/media/dvb/siano/smsir.h
new file mode 100644
index 000000000000..b7d703e2d338
--- /dev/null
+++ b/drivers/media/dvb/siano/smsir.h
@@ -0,0 +1,93 @@
+/****************************************************************
+
+Siano Mobile Silicon, Inc.
+MDTV receiver kernel modules.
+Copyright (C) 2006-2009, Uri Shkolnik
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 2 of the License, or
+(at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+****************************************************************/
+
+#ifndef __SMS_IR_H__
+#define __SMS_IR_H__
+
+#include <linux/input.h>
+
+#define IR_DEV_NAME_MAX_LEN             23 /* "SMS IR kbd type nn\0" */
+#define IR_KEYBOARD_LAYOUT_SIZE 64
+#define IR_DEFAULT_TIMEOUT              100
+
+enum ir_kb_type {
+        SMS_IR_KB_DEFAULT_TV,
+        SMS_IR_KB_HCW_SILVER
+};
+
+enum rc5_keyboard_address {
+        KEYBOARD_ADDRESS_TV1 = 0,
+        KEYBOARD_ADDRESS_TV2 = 1,
+        KEYBOARD_ADDRESS_TELETEXT = 2,
+        KEYBOARD_ADDRESS_VIDEO = 3,
+        KEYBOARD_ADDRESS_LV1 = 4,
+        KEYBOARD_ADDRESS_VCR1 = 5,
+        KEYBOARD_ADDRESS_VCR2 = 6,
+        KEYBOARD_ADDRESS_EXPERIMENTAL = 7,
+        KEYBOARD_ADDRESS_SAT1 = 8,
+        KEYBOARD_ADDRESS_CAMERA = 9,
+        KEYBOARD_ADDRESS_SAT2 = 10,
+        KEYBOARD_ADDRESS_CDV = 12,
+        KEYBOARD_ADDRESS_CAMCORDER = 13,
+        KEYBOARD_ADDRESS_PRE_AMP = 16,
+        KEYBOARD_ADDRESS_TUNER = 17,
+        KEYBOARD_ADDRESS_RECORDER1 = 18,
+        KEYBOARD_ADDRESS_PRE_AMP1 = 19,
+        KEYBOARD_ADDRESS_CD_PLAYER = 20,
+        KEYBOARD_ADDRESS_PHONO = 21,
+        KEYBOARD_ADDRESS_SATA = 22,
+        KEYBOARD_ADDRESS_RECORDER2 = 23,
+        KEYBOARD_ADDRESS_CDR = 26,
+        KEYBOARD_ADDRESS_LIGHTING = 29,
+        KEYBOARD_ADDRESS_LIGHTING1 = 30, /* KEYBOARD_ADDRESS_HCW_SILVER */
+        KEYBOARD_ADDRESS_PHONE = 31,
+        KEYBOARD_ADDRESS_NOT_RC5 = 0xFFFF
+};
+
+enum ir_protocol {
+        IR_RC5,
+        IR_RCMM
+};
+
+struct keyboard_layout_map_t {
+        enum ir_protocol ir_protocol;
+        enum rc5_keyboard_address rc5_kbd_address;
+        u16 keyboard_layout_map[IR_KEYBOARD_LAYOUT_SIZE];
+};
+
+struct smscore_device_t;
+
+struct ir_t {
+        struct input_dev *input_dev;
+        enum ir_kb_type ir_kb_type;
+        char name[IR_DEV_NAME_MAX_LEN+1];
+        u16 *keyboard_layout_map;
+        u32 timeout;
+        u32 controller;
+};
+
+int sms_ir_init(struct smscore_device_t *coredev);
+void sms_ir_exit(struct smscore_device_t *coredev);
+void sms_ir_event(struct smscore_device_t *coredev,
+                        const char *buf, int len);
+
+#endif /* __SMS_IR_H__ */
+
diff --git a/drivers/media/dvb/siano/smssdio.c b/drivers/media/dvb/siano/smssdio.c
new file mode 100644
index 000000000000..dfaa49a53f32
--- /dev/null
+++ b/drivers/media/dvb/siano/smssdio.c
@@ -0,0 +1,357 @@
+/*
+ *  smssdio.c - Siano 1xxx SDIO interface driver
+ *
+ *  Copyright 2008 Pierre Ossman
+ *
+ * Based on code by Siano Mobile Silicon, Inc.,
+ * Copyright (C) 2006-2008, Uri Shkolnik
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ *
+ * This hardware is a bit odd in that all transfers should be done
+ * to/from the SMSSDIO_DATA register, yet the "increase address" bit
+ * always needs to be set.
+ *
+ * Also, buffers from the card are always aligned to 128 byte
+ * boundaries.
+ */
+
+/*
+ * General cleanup notes:
+ *
+ * - only typedefs should be name *_t
+ *
+ * - use ERR_PTR and friends for smscore_register_device()
+ *
+ * - smscore_getbuffer should zero fields
+ *
+ * Fix stop command
+ */
+
+#include <linux/moduleparam.h>
+#include <linux/firmware.h>
+#include <linux/delay.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+
+#include "smscoreapi.h"
+#include "sms-cards.h"
+
+/* Registers */
+
+#define SMSSDIO_DATA            0x00
+#define SMSSDIO_INT             0x04
+
+static const struct sdio_device_id smssdio_ids[] = {
+        {SDIO_DEVICE(SDIO_VENDOR_ID_SIANO, SDIO_DEVICE_ID_SIANO_STELLAR),
+         .driver_data = SMS1XXX_BOARD_SIANO_STELLAR},
+        {SDIO_DEVICE(SDIO_VENDOR_ID_SIANO, SDIO_DEVICE_ID_SIANO_NOVA_A0),
+         .driver_data = SMS1XXX_BOARD_SIANO_NOVA_A},
+        {SDIO_DEVICE(SDIO_VENDOR_ID_SIANO, SDIO_DEVICE_ID_SIANO_NOVA_B0),
+         .driver_data = SMS1XXX_BOARD_SIANO_NOVA_B},
+        {SDIO_DEVICE(SDIO_VENDOR_ID_SIANO, SDIO_DEVICE_ID_SIANO_VEGA_A0),
+         .driver_data = SMS1XXX_BOARD_SIANO_VEGA},
+        {SDIO_DEVICE(SDIO_VENDOR_ID_SIANO, SDIO_DEVICE_ID_SIANO_VENICE),
+         .driver_data = SMS1XXX_BOARD_SIANO_VEGA},
+        { /* end: all zeroes */ },
+};
+
+MODULE_DEVICE_TABLE(sdio, smssdio_ids);
+
+struct smssdio_device {
+        struct sdio_func *func;
+
+        struct smscore_device_t *coredev;
+
+        struct smscore_buffer_t *split_cb;
+};
+
+/*******************************************************************/
+/* Siano core callbacks                                            */
+/*******************************************************************/
+
+static int smssdio_sendrequest(void *context, void *buffer, size_t size)
+{
+        int ret;
+        struct smssdio_device *smsdev;
+
+        smsdev = context;
+
+        sdio_claim_host(smsdev->func);
+
+        while (size >= smsdev->func->cur_blksize) {
+                ret = sdio_write_blocks(smsdev->func, SMSSDIO_DATA, buffer, 1);
+                if (ret)
+                        goto out;
+
+                buffer += smsdev->func->cur_blksize;
+                size -= smsdev->func->cur_blksize;
+        }
+
+        if (size) {
+                ret = sdio_write_bytes(smsdev->func, SMSSDIO_DATA,
+                                       buffer, size);
+        }
+
+out:
+        sdio_release_host(smsdev->func);
+
+        return ret;
+}
+
+/*******************************************************************/
+/* SDIO callbacks                                                  */
+/*******************************************************************/
+
+static void smssdio_interrupt(struct sdio_func *func)
+{
+        int ret, isr;
+
+        struct smssdio_device *smsdev;
+        struct smscore_buffer_t *cb;
+        struct SmsMsgHdr_ST *hdr;
+        size_t size;
+
+        smsdev = sdio_get_drvdata(func);
+
+        /*
+         * The interrupt register has no defined meaning. It is just
+         * a way of turning of the level triggered interrupt.
+         */
+        isr = sdio_readb(func, SMSSDIO_INT, &ret);
+        if (ret) {
+                dev_err(&smsdev->func->dev,
+                        "Unable to read interrupt register!\n");
+                return;
+        }
+
+        if (smsdev->split_cb == NULL) {
+                cb = smscore_getbuffer(smsdev->coredev);
+                if (!cb) {
+                        dev_err(&smsdev->func->dev,
+                                "Unable to allocate data buffer!\n");
+                        return;
+                }
+
+                ret = sdio_read_blocks(smsdev->func, cb->p, SMSSDIO_DATA, 1);
+                if (ret) {
+                        dev_err(&smsdev->func->dev,
+                                "Error %d reading initial block!\n", ret);
+                        return;
+                }
+
+                hdr = cb->p;
+
+                if (hdr->msgFlags & MSG_HDR_FLAG_SPLIT_MSG) {
+                        smsdev->split_cb = cb;
+                        return;
+                }
+
+                size = hdr->msgLength - smsdev->func->cur_blksize;
+        } else {
+                cb = smsdev->split_cb;
+                hdr = cb->p;
+
+                size = hdr->msgLength - sizeof(struct SmsMsgHdr_ST);
+
+                smsdev->split_cb = NULL;
+        }
+
+        if (hdr->msgLength > smsdev->func->cur_blksize) {
+                void *buffer;
+
+                size = ALIGN(size, 128);
+                buffer = cb->p + hdr->msgLength;
+
+                BUG_ON(smsdev->func->cur_blksize != 128);
+
+                /*
+                 * First attempt to transfer all of it in one go...
+                 */
+                ret = sdio_read_blocks(smsdev->func, buffer,
+                                       SMSSDIO_DATA, size / 128);
+                if (ret && ret != -EINVAL) {
+                        smscore_putbuffer(smsdev->coredev, cb);
+                        dev_err(&smsdev->func->dev,
+                                "Error %d reading data from card!\n", ret);
+                        return;
+                }
+
+                /*
+                 * ..then fall back to one block at a time if that is
+                 * not possible...
+                 *
+                 * (we have to do this manually because of the
+                 * problem with the "increase address" bit)
+                 */
+                if (ret == -EINVAL) {
+                        while (size) {
+                                ret = sdio_read_blocks(smsdev->func,
+                                                       buffer, SMSSDIO_DATA, 1);
+                                if (ret) {
+                                        smscore_putbuffer(smsdev->coredev, cb);
+                                        dev_err(&smsdev->func->dev,
+                                                "Error %d reading "
+                                                "data from card!\n", ret);
+                                        return;
+                                }
+
+                                buffer += smsdev->func->cur_blksize;
+                                if (size > smsdev->func->cur_blksize)
+                                        size -= smsdev->func->cur_blksize;
+                                else
+                                        size = 0;
+                        }
+                }
+        }
+
+        cb->size = hdr->msgLength;
+        cb->offset = 0;
+
+        smscore_onresponse(smsdev->coredev, cb);
+}
+
+static int smssdio_probe(struct sdio_func *func,
+                         const struct sdio_device_id *id)
+{
+        int ret;
+
+        int board_id;
+        struct smssdio_device *smsdev;
+        struct smsdevice_params_t params;
+
+        board_id = id->driver_data;
+
+        smsdev = kzalloc(sizeof(struct smssdio_device), GFP_KERNEL);
+        if (!smsdev)
+                return -ENOMEM;
+
+        smsdev->func = func;
+
+        memset(&params, 0, sizeof(struct smsdevice_params_t));
+
+        params.device = &func->dev;
+        params.buffer_size = 0x5000;    /* ?? */
+        params.num_buffers = 22;        /* ?? */
+        params.context = smsdev;
+
+        snprintf(params.devpath, sizeof(params.devpath),
+                 "sdio\\%s", sdio_func_id(func));
+
+        params.sendrequest_handler = smssdio_sendrequest;
+
+        params.device_type = sms_get_board(board_id)->type;
+
+        if (params.device_type != SMS_STELLAR)
+                params.flags |= SMS_DEVICE_FAMILY2;
+        else {
+                /*
+                 * FIXME: Stellar needs special handling...
+                 */
+                ret = -ENODEV;
+                goto free;
+        }
+
+        ret = smscore_register_device(&params, &smsdev->coredev);
+        if (ret < 0)
+                goto free;
+
+        smscore_set_board_id(smsdev->coredev, board_id);
+
+        sdio_claim_host(func);
+
+        ret = sdio_enable_func(func);
+        if (ret)
+                goto release;
+
+        ret = sdio_set_block_size(func, 128);
+        if (ret)
+                goto disable;
+
+        ret = sdio_claim_irq(func, smssdio_interrupt);
+        if (ret)
+                goto disable;
+
+        sdio_set_drvdata(func, smsdev);
+
+        sdio_release_host(func);
+
+        ret = smscore_start_device(smsdev->coredev);
+        if (ret < 0)
+                goto reclaim;
+
+        return 0;
+
+reclaim:
+        sdio_claim_host(func);
+        sdio_release_irq(func);
+disable:
+        sdio_disable_func(func);
+release:
+        sdio_release_host(func);
+        smscore_unregister_device(smsdev->coredev);
+free:
+        kfree(smsdev);
+
+        return ret;
+}
+
+static void smssdio_remove(struct sdio_func *func)
+{
+        struct smssdio_device *smsdev;
+
+        smsdev = sdio_get_drvdata(func);
+
+        /* FIXME: racy! */
+        if (smsdev->split_cb)
+                smscore_putbuffer(smsdev->coredev, smsdev->split_cb);
+
+        smscore_unregister_device(smsdev->coredev);
+
+        sdio_claim_host(func);
+        sdio_release_irq(func);
+        sdio_disable_func(func);
+        sdio_release_host(func);
+
+        kfree(smsdev);
+}
+
+static struct sdio_driver smssdio_driver = {
+        .name = "smssdio",
+        .id_table = smssdio_ids,
+        .probe = smssdio_probe,
+        .remove = smssdio_remove,
+};
+
+/*******************************************************************/
+/* Module functions                                                */
+/*******************************************************************/
+
+int smssdio_module_init(void)
+{
+        int ret = 0;
+
+        printk(KERN_INFO "smssdio: Siano SMS1xxx SDIO driver\n");
+        printk(KERN_INFO "smssdio: Copyright Pierre Ossman\n");
+
+        ret = sdio_register_driver(&smssdio_driver);
+
+        return ret;
+}
+
+void smssdio_module_exit(void)
+{
+        sdio_unregister_driver(&smssdio_driver);
+}
+
+module_init(smssdio_module_init);
+module_exit(smssdio_module_exit);
+
+MODULE_DESCRIPTION("Siano SMS1xxx SDIO driver");
+MODULE_AUTHOR("Pierre Ossman");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/siano/smsusb.c b/drivers/media/dvb/siano/smsusb.c
index 71c65f544c07..cb8a358b7310 100644
--- a/drivers/media/dvb/siano/smsusb.c
+++ b/drivers/media/dvb/siano/smsusb.c
@@ -1,23 +1,23 @@
-/*
- *  Driver for the Siano SMS1xxx USB dongle
- *
- *  author: Anatoly Greenblat
- *
- *  Copyright (c), 2005-2008 Siano Mobile Silicon, Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License version 2 as
- *  published by the Free Software Foundation;
- *
- *  Software distributed under the License is distributed on an "AS IS"
- *  basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
- *
- *  See the GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
+/****************************************************************
+
+Siano Mobile Silicon, Inc.
+MDTV receiver kernel modules.
+Copyright (C) 2005-2009, Uri Shkolnik, Anatoly Greenblat
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 2 of the License, or
+(at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+****************************************************************/
 
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -26,6 +26,7 @@
 
 #include "smscoreapi.h"
 #include "sms-cards.h"
+#include "smsendian.h"
 
 static int sms_dbg;
 module_param_named(debug, sms_dbg, int, 0644);
@@ -64,15 +65,16 @@ static void smsusb_onresponse(struct urb *urb)
         struct smsusb_urb_t *surb = (struct smsusb_urb_t *) urb->context;
         struct smsusb_device_t *dev = surb->dev;
 
-        if (urb->status < 0) {
-                sms_err("error, urb status %d, %d bytes",
+        if (urb->status == -ESHUTDOWN) {
+                sms_err("error, urb status %d (-ESHUTDOWN), %d bytes",
                         urb->status, urb->actual_length);
                 return;
         }
 
-        if (urb->actual_length > 0) {
-                struct SmsMsgHdr_ST *phdr = (struct SmsMsgHdr_ST *) surb->cb->p;
+        if ((urb->actual_length > 0) && (urb->status == 0)) {
+                struct SmsMsgHdr_ST *phdr = (struct SmsMsgHdr_ST *)surb->cb->p;
 
+                smsendian_handle_message_header(phdr);
                 if (urb->actual_length >= phdr->msgLength) {
                         surb->cb->size = phdr->msgLength;
 
@@ -109,7 +111,10 @@ static void smsusb_onresponse(struct urb *urb)
                                 "msglen %d actual %d",
                                 phdr->msgLength, urb->actual_length);
                 }
-        }
+        } else
+                sms_err("error, urb status %d, %d bytes",
+                        urb->status, urb->actual_length);
+
 
 exit_and_resubmit:
         smsusb_submit_urb(dev, surb);
@@ -176,6 +181,7 @@ static int smsusb_sendrequest(void *context, void *buffer, size_t size)
         struct smsusb_device_t *dev = (struct smsusb_device_t *) context;
         int dummy;
 
+        smsendian_handle_message_header((struct SmsMsgHdr_ST *)buffer);
         return usb_bulk_msg(dev->udev, usb_sndbulkpipe(dev->udev, 2),
                             buffer, size, &dummy, 1000);
 }
@@ -333,8 +339,8 @@ static int smsusb_init_device(struct usb_interface *intf, int board_id)
         case SMS_VEGA:
                 dev->buffer_size = USB2_BUFFER_SIZE;
                 dev->response_alignment =
-                        dev->udev->ep_in[1]->desc.wMaxPacketSize -
-                        sizeof(struct SmsMsgHdr_ST);
+                    le16_to_cpu(dev->udev->ep_in[1]->desc.wMaxPacketSize) -
+                    sizeof(struct SmsMsgHdr_ST);
 
                 params.flags |= SMS_DEVICE_FAMILY2;
                 break;
@@ -479,7 +485,6 @@ static int smsusb_resume(struct usb_interface *intf)
 }
 
 struct usb_device_id smsusb_id_table[] = {
-#ifdef CONFIG_DVB_SIANO_SMS1XXX_SMS_IDS
         { USB_DEVICE(0x187f, 0x0010),
                 .driver_info = SMS1XXX_BOARD_SIANO_STELLAR },
         { USB_DEVICE(0x187f, 0x0100),
@@ -490,7 +495,6 @@ struct usb_device_id smsusb_id_table[] = {
                 .driver_info = SMS1XXX_BOARD_SIANO_NOVA_B },
         { USB_DEVICE(0x187f, 0x0300),
                 .driver_info = SMS1XXX_BOARD_SIANO_VEGA },
-#endif
         { USB_DEVICE(0x2040, 0x1700),
                 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_CATAMOUNT },
         { USB_DEVICE(0x2040, 0x1800),
@@ -521,8 +525,13 @@ struct usb_device_id smsusb_id_table[] = {
                 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_WINDHAM },
         { USB_DEVICE(0x2040, 0x5590),
                 .driver_info = SMS1XXX_BOARD_HAUPPAUGE_WINDHAM },
-        { }             /* Terminating entry */
-};
+        { USB_DEVICE(0x187f, 0x0202),
+                .driver_info = SMS1XXX_BOARD_SIANO_NICE },
+        { USB_DEVICE(0x187f, 0x0301),
+                .driver_info = SMS1XXX_BOARD_SIANO_VENICE },
+        { } /* Terminating entry */
+        };
+
 MODULE_DEVICE_TABLE(usb, smsusb_id_table);
 
 static struct usb_driver smsusb_driver = {
@@ -548,14 +557,14 @@ int smsusb_module_init(void)
 
 void smsusb_module_exit(void)
 {
-        sms_debug("");
         /* Regular USB Cleanup */
         usb_deregister(&smsusb_driver);
+        sms_info("end");
 }
 
 module_init(smsusb_module_init);
 module_exit(smsusb_module_exit);
 
-MODULE_DESCRIPTION("Driver for the Siano SMS1XXX USB dongle");
+MODULE_DESCRIPTION("Driver for the Siano SMS1xxx USB dongle");
 MODULE_AUTHOR("Siano Mobile Silicon, INC. (uris@siano-ms.com)");
 MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/ttpci/av7110_av.c b/drivers/media/dvb/ttpci/av7110_av.c
index e4d0900d5121..53884814161c 100644
--- a/drivers/media/dvb/ttpci/av7110_av.c
+++ b/drivers/media/dvb/ttpci/av7110_av.c
@@ -89,6 +89,7 @@
 
 static void p_to_t(u8 const *buf, long int length, u16 pid,
                    u8 *counter, struct dvb_demux_feed *feed);
+static int write_ts_to_decoder(struct av7110 *av7110, int type, const u8 *buf, size_t len);
 
 
 int av7110_record_cb(struct dvb_filter_pes2ts *p2t, u8 *buf, size_t len)
@@ -192,8 +193,6 @@ int av7110_av_start_play(struct av7110 *av7110, int av)
                 ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Play, 2, AV_PES, 0);
                 break;
         }
-        if (!ret)
-                ret = av7110->playing;
         return ret;
 }
 
@@ -437,6 +436,45 @@ static void play_audio_cb(u8 *buf, int count, void *priv)
         aux_ring_buffer_write(&av7110->aout, buf, count);
 }
 
+
+#define FREE_COND_TS (dvb_ringbuffer_free(rb) >= 4096)
+
+static ssize_t ts_play(struct av7110 *av7110, const char __user *buf,
+                       unsigned long count, int nonblock, int type)
+{
+        struct dvb_ringbuffer *rb;
+        u8 *kb;
+        unsigned long todo = count;
+
+        dprintk(2, "%s: type %d cnt %lu\n", __func__, type, count);
+
+        rb = (type) ? &av7110->avout : &av7110->aout;
+        kb = av7110->kbuf[type];
+
+        if (!kb)
+                return -ENOBUFS;
+
+        if (nonblock && !FREE_COND_TS)
+                return -EWOULDBLOCK;
+
+        while (todo >= TS_SIZE) {
+                if (!FREE_COND_TS) {
+                        if (nonblock)
+                                return count - todo;
+                        if (wait_event_interruptible(rb->queue, FREE_COND_TS))
+                                return count - todo;
+                }
+                if (copy_from_user(kb, buf, TS_SIZE))
+                        return -EFAULT;
+                write_ts_to_decoder(av7110, type, kb, TS_SIZE);
+                todo -= TS_SIZE;
+                buf += TS_SIZE;
+        }
+
+        return count - todo;
+}
+
+
 #define FREE_COND (dvb_ringbuffer_free(&av7110->avout) >= 20 * 1024 && \
                    dvb_ringbuffer_free(&av7110->aout) >= 20 * 1024)
 
@@ -780,11 +818,37 @@ static void p_to_t(u8 const *buf, long int length, u16 pid, u8 *counter,
 }
 
 
+static int write_ts_to_decoder(struct av7110 *av7110, int type, const u8 *buf, size_t len)
+{
+        struct ipack *ipack = &av7110->ipack[type];
+
+        if (buf[1] & TRANS_ERROR) {
+                av7110_ipack_reset(ipack);
+                return -1;
+        }
+
+        if (!(buf[3] & PAYLOAD))
+                return -1;
+
+        if (buf[1] & PAY_START)
+                av7110_ipack_flush(ipack);
+
+        if (buf[3] & ADAPT_FIELD) {
+                len -= buf[4] + 1;
+                buf += buf[4] + 1;
+                if (!len)
+                        return 0;
+        }
+
+        av7110_ipack_instant_repack(buf + 4, len - 4, ipack);
+        return 0;
+}
+
+
 int av7110_write_to_decoder(struct dvb_demux_feed *feed, const u8 *buf, size_t len)
 {
         struct dvb_demux *demux = feed->demux;
         struct av7110 *av7110 = (struct av7110 *) demux->priv;
-        struct ipack *ipack = &av7110->ipack[feed->pes_type];
 
         dprintk(2, "av7110:%p, \n", av7110);
 
@@ -804,20 +868,7 @@ int av7110_write_to_decoder(struct dvb_demux_feed *feed, const u8 *buf, size_t l
                 return -1;
         }
 
-        if (!(buf[3] & 0x10)) /* no payload? */
-                return -1;
-        if (buf[1] & 0x40)
-                av7110_ipack_flush(ipack);
-
-        if (buf[3] & 0x20) {  /* adaptation field? */
-                len -= buf[4] + 1;
-                buf += buf[4] + 1;
-                if (!len)
-                        return 0;
-        }
-
-        av7110_ipack_instant_repack(buf + 4, len - 4, &av7110->ipack[feed->pes_type]);
-        return 0;
+        return write_ts_to_decoder(av7110, feed->pes_type, buf, len);
 }
 
 
@@ -916,6 +967,7 @@ static ssize_t dvb_video_write(struct file *file, const char __user *buf,
 {
         struct dvb_device *dvbdev = file->private_data;
         struct av7110 *av7110 = dvbdev->priv;
+        unsigned char c;
 
         dprintk(2, "av7110:%p, \n", av7110);
 
@@ -925,7 +977,12 @@ static ssize_t dvb_video_write(struct file *file, const char __user *buf,
         if (av7110->videostate.stream_source != VIDEO_SOURCE_MEMORY)
                 return -EPERM;
 
-        return dvb_play(av7110, buf, count, file->f_flags & O_NONBLOCK, 1);
+        if (get_user(c, buf))
+                return -EFAULT;
+        if (c == 0x47 && count % TS_SIZE == 0)
+                return ts_play(av7110, buf, count, file->f_flags & O_NONBLOCK, 1);
+        else
+                return dvb_play(av7110, buf, count, file->f_flags & O_NONBLOCK, 1);
 }
 
 static unsigned int dvb_audio_poll(struct file *file, poll_table *wait)
@@ -952,6 +1009,7 @@ static ssize_t dvb_audio_write(struct file *file, const char __user *buf,
 {
         struct dvb_device *dvbdev = file->private_data;
         struct av7110 *av7110 = dvbdev->priv;
+        unsigned char c;
 
         dprintk(2, "av7110:%p, \n", av7110);
 
@@ -959,7 +1017,13 @@ static ssize_t dvb_audio_write(struct file *file, const char __user *buf,
                 printk(KERN_ERR "not audio source memory\n");
                 return -EPERM;
         }
-        return dvb_aplay(av7110, buf, count, file->f_flags & O_NONBLOCK, 0);
+
+        if (get_user(c, buf))
+                return -EFAULT;
+        if (c == 0x47 && count % TS_SIZE == 0)
+                return ts_play(av7110, buf, count, file->f_flags & O_NONBLOCK, 0);
+        else
+                return dvb_aplay(av7110, buf, count, file->f_flags & O_NONBLOCK, 0);
 }
 
 static u8 iframe_header[] = { 0x00, 0x00, 0x01, 0xe0, 0x00, 0x00, 0x80, 0x00, 0x00 };
@@ -1062,7 +1126,6 @@ static int dvb_video_ioctl(struct inode *inode, struct file *file,
                         if (ret)
                                 break;
                 }
-
                 if (av7110->videostate.stream_source == VIDEO_SOURCE_MEMORY) {
                         if (av7110->playing == RP_AV) {
                                 ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Stop, 0);
@@ -1122,20 +1185,16 @@ static int dvb_video_ioctl(struct inode *inode, struct file *file,
         case VIDEO_SET_DISPLAY_FORMAT:
         {
                 video_displayformat_t format = (video_displayformat_t) arg;
-
                 switch (format) {
                 case VIDEO_PAN_SCAN:
                         av7110->display_panscan = VID_PAN_SCAN_PREF;
                         break;
-
                 case VIDEO_LETTER_BOX:
                         av7110->display_panscan = VID_VC_AND_PS_PREF;
                         break;
-
                 case VIDEO_CENTER_CUT_OUT:
                         av7110->display_panscan = VID_CENTRE_CUT_PREF;
                         break;
-
                 default:
                         ret = -EINVAL;
                 }
@@ -1183,7 +1242,8 @@ static int dvb_video_ioctl(struct inode *inode, struct file *file,
 
         case VIDEO_SLOWMOTION:
                 if (av7110->playing&RP_VIDEO) {
-                        ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Slow, 2, 0, 0);
+                        if (av7110->trickmode != TRICK_SLOW)
+                                ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY, __Slow, 2, 0, 0);
                         if (!ret)
                                 ret = vidcom(av7110, AV_VIDEO_CMD_SLOW, arg);
                 } else {
@@ -1207,7 +1267,6 @@ static int dvb_video_ioctl(struct inode *inode, struct file *file,
         case VIDEO_CLEAR_BUFFER:
                 dvb_ringbuffer_flush_spinlock_wakeup(&av7110->avout);
                 av7110_ipack_reset(&av7110->ipack[1]);
-
                 if (av7110->playing == RP_AV) {
                         ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY,
                                             __Play, 2, AV_PES, 0);
@@ -1228,13 +1287,13 @@ static int dvb_video_ioctl(struct inode *inode, struct file *file,
                 break;
 
         case VIDEO_SET_STREAMTYPE:
-
                 break;
 
         default:
                 ret = -ENOIOCTLCMD;
                 break;
         }
+
         return ret;
 }
 
@@ -1309,7 +1368,6 @@ static int dvb_audio_ioctl(struct inode *inode, struct file *file,
 
         case AUDIO_CHANNEL_SELECT:
                 av7110->audiostate.channel_select = (audio_channel_select_t) arg;
-
                 switch(av7110->audiostate.channel_select) {
                 case AUDIO_STEREO:
                         ret = audcom(av7110, AUDIO_CMD_STEREO);
@@ -1320,7 +1378,6 @@ static int dvb_audio_ioctl(struct inode *inode, struct file *file,
                                         msp_writereg(av7110, MSP_WR_DSP, 0x0008, 0x0220);
                         }
                         break;
-
                 case AUDIO_MONO_LEFT:
                         ret = audcom(av7110, AUDIO_CMD_MONO_L);
                         if (!ret) {
@@ -1330,7 +1387,6 @@ static int dvb_audio_ioctl(struct inode *inode, struct file *file,
                                         msp_writereg(av7110, MSP_WR_DSP, 0x0008, 0x0200);
                         }
                         break;
-
                 case AUDIO_MONO_RIGHT:
                         ret = audcom(av7110, AUDIO_CMD_MONO_R);
                         if (!ret) {
@@ -1340,7 +1396,6 @@ static int dvb_audio_ioctl(struct inode *inode, struct file *file,
                                         msp_writereg(av7110, MSP_WR_DSP, 0x0008, 0x0210);
                         }
                         break;
-
                 default:
                         ret = -EINVAL;
                         break;
@@ -1366,21 +1421,24 @@ static int dvb_audio_ioctl(struct inode *inode, struct file *file,
                         ret = av7110_fw_cmd(av7110, COMTYPE_REC_PLAY,
                                             __Play, 2, AV_PES, 0);
                 break;
-        case AUDIO_SET_ID:
 
+        case AUDIO_SET_ID:
                 break;
+
         case AUDIO_SET_MIXER:
         {
                 struct audio_mixer *amix = (struct audio_mixer *)parg;
-
                 ret = av7110_set_volume(av7110, amix->volume_left, amix->volume_right);
                 break;
         }
+
         case AUDIO_SET_STREAMTYPE:
                 break;
+
         default:
                 ret = -ENOIOCTLCMD;
         }
+
         return ret;
 }
 
diff --git a/drivers/media/dvb/ttpci/av7110_hw.c b/drivers/media/dvb/ttpci/av7110_hw.c
index 5e3f88911a1d..e162691b515d 100644
--- a/drivers/media/dvb/ttpci/av7110_hw.c
+++ b/drivers/media/dvb/ttpci/av7110_hw.c
@@ -1089,7 +1089,7 @@ int av7110_osd_cmd(struct av7110 *av7110, osd_cmd_t *dc)
                 else {
                         int i, len = dc->x0-dc->color+1;
                         u8 __user *colors = (u8 __user *)dc->data;
-                        u8 r, g, b, blend;
+                        u8 r, g = 0, b = 0, blend = 0;
                         ret = 0;
                         for (i = 0; i<len; i++) {
                                 if (get_user(r, colors + i * 4) ||
diff --git a/drivers/media/dvb/ttpci/av7110_v4l.c b/drivers/media/dvb/ttpci/av7110_v4l.c
index 2210cff738e6..ce64c6214cc4 100644
--- a/drivers/media/dvb/ttpci/av7110_v4l.c
+++ b/drivers/media/dvb/ttpci/av7110_v4l.c
@@ -458,7 +458,7 @@ static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i)
         dprintk(2, "VIDIOC_ENUMINPUT: %d\n", i->index);
 
         if (av7110->analog_tuner_flags) {
-                if (i->index < 0 || i->index >= 4)
+                if (i->index >= 4)
                         return -EINVAL;
         } else {
                 if (i->index != 0)
diff --git a/drivers/media/dvb/ttpci/budget-av.c b/drivers/media/dvb/ttpci/budget-av.c
index 855fe74b640b..8ea915227674 100644
--- a/drivers/media/dvb/ttpci/budget-av.c
+++ b/drivers/media/dvb/ttpci/budget-av.c
@@ -1413,7 +1413,7 @@ static struct v4l2_input knc1_inputs[KNC1_INPUTS] = {
 static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i)
 {
         dprintk(1, "VIDIOC_ENUMINPUT %d.\n", i->index);
-        if (i->index < 0 || i->index >= KNC1_INPUTS)
+        if (i->index >= KNC1_INPUTS)
                 return -EINVAL;
         memcpy(i, &knc1_inputs[i->index], sizeof(struct v4l2_input));
         return 0;
diff --git a/drivers/media/dvb/ttpci/budget.c b/drivers/media/dvb/ttpci/budget.c
index 83e9e7750c8c..e48380c48990 100644
--- a/drivers/media/dvb/ttpci/budget.c
+++ b/drivers/media/dvb/ttpci/budget.c
@@ -47,6 +47,9 @@
 #include "bsru6.h"
 #include "bsbe1.h"
 #include "tdhd1.h"
+#include "stv6110x.h"
+#include "stv090x.h"
+#include "isl6423.h"
 
 static int diseqc_method;
 module_param(diseqc_method, int, 0444);
@@ -425,6 +428,44 @@ static u8 read_pwm(struct budget* budget)
         return pwm;
 }
 
+static struct stv090x_config tt1600_stv090x_config = {
+        .device                 = STV0903,
+        .demod_mode             = STV090x_SINGLE,
+        .clk_mode               = STV090x_CLK_EXT,
+
+        .xtal                   = 27000000,
+        .address                = 0x68,
+        .ref_clk                = 27000000,
+
+        .ts1_mode               = STV090x_TSMODE_DVBCI,
+        .ts2_mode               = STV090x_TSMODE_SERIAL_CONTINUOUS,
+
+        .repeater_level         = STV090x_RPTLEVEL_16,
+
+        .tuner_init             = NULL,
+        .tuner_set_mode         = NULL,
+        .tuner_set_frequency    = NULL,
+        .tuner_get_frequency    = NULL,
+        .tuner_set_bandwidth    = NULL,
+        .tuner_get_bandwidth    = NULL,
+        .tuner_set_bbgain       = NULL,
+        .tuner_get_bbgain       = NULL,
+        .tuner_set_refclk       = NULL,
+        .tuner_get_status       = NULL,
+};
+
+static struct stv6110x_config tt1600_stv6110x_config = {
+        .addr                   = 0x60,
+        .refclk                 = 27000000,
+};
+
+static struct isl6423_config tt1600_isl6423_config = {
+        .current_max            = SEC_CURRENT_515m,
+        .curlim                 = SEC_CURRENT_LIM_ON,
+        .mod_extern             = 1,
+        .addr                   = 0x08,
+};
+
 static void frontend_init(struct budget *budget)
 {
         (void)alps_bsbe1_config; /* avoid warning */
@@ -566,6 +607,48 @@ static void frontend_init(struct budget *budget)
                         }
                         break;
                 }
+
+        case 0x101c: { /* TT S2-1600 */
+                        struct stv6110x_devctl *ctl;
+                        saa7146_setgpio(budget->dev, 2, SAA7146_GPIO_OUTLO);
+                        msleep(50);
+                        saa7146_setgpio(budget->dev, 2, SAA7146_GPIO_OUTHI);
+                        msleep(250);
+
+                        budget->dvb_frontend = dvb_attach(stv090x_attach,
+                                                          &tt1600_stv090x_config,
+                                                          &budget->i2c_adap,
+                                                          STV090x_DEMODULATOR_0);
+
+                        if (budget->dvb_frontend) {
+
+                                ctl = dvb_attach(stv6110x_attach,
+                                                 budget->dvb_frontend,
+                                                 &tt1600_stv6110x_config,
+                                                 &budget->i2c_adap);
+
+                                tt1600_stv090x_config.tuner_init          = ctl->tuner_init;
+                                tt1600_stv090x_config.tuner_set_mode      = ctl->tuner_set_mode;
+                                tt1600_stv090x_config.tuner_set_frequency = ctl->tuner_set_frequency;
+                                tt1600_stv090x_config.tuner_get_frequency = ctl->tuner_get_frequency;
+                                tt1600_stv090x_config.tuner_set_bandwidth = ctl->tuner_set_bandwidth;
+                                tt1600_stv090x_config.tuner_get_bandwidth = ctl->tuner_get_bandwidth;
+                                tt1600_stv090x_config.tuner_set_bbgain    = ctl->tuner_set_bbgain;
+                                tt1600_stv090x_config.tuner_get_bbgain    = ctl->tuner_get_bbgain;
+                                tt1600_stv090x_config.tuner_set_refclk    = ctl->tuner_set_refclk;
+                                tt1600_stv090x_config.tuner_get_status    = ctl->tuner_get_status;
+
+                                dvb_attach(isl6423_attach,
+                                        budget->dvb_frontend,
+                                        &budget->i2c_adap,
+                                        &tt1600_isl6423_config);
+
+                        } else {
+                                dvb_frontend_detach(budget->dvb_frontend);
+                                budget->dvb_frontend = NULL;
+                        }
+                }
+                break;
         }
 
         if (budget->dvb_frontend == NULL) {
@@ -641,6 +724,7 @@ MAKE_BUDGET_INFO(ttbc,	"TT-Budget/WinTV-NOVA-C  PCI",	BUDGET_TT);
 MAKE_BUDGET_INFO(ttbt,  "TT-Budget/WinTV-NOVA-T  PCI",  BUDGET_TT);
 MAKE_BUDGET_INFO(satel, "SATELCO Multimedia PCI",       BUDGET_TT_HW_DISEQC);
 MAKE_BUDGET_INFO(ttbs1401, "TT-Budget-S-1401 PCI", BUDGET_TT);
+MAKE_BUDGET_INFO(tt1600, "TT-Budget S2-1600 PCI", BUDGET_TT);
 MAKE_BUDGET_INFO(fsacs0, "Fujitsu Siemens Activy Budget-S PCI (rev GR/grundig frontend)", BUDGET_FS_ACTIVY);
 MAKE_BUDGET_INFO(fsacs1, "Fujitsu Siemens Activy Budget-S PCI (rev AL/alps frontend)", BUDGET_FS_ACTIVY);
 MAKE_BUDGET_INFO(fsact,  "Fujitsu Siemens Activy Budget-T PCI (rev GR/Grundig frontend)", BUDGET_FS_ACTIVY);
@@ -653,6 +737,7 @@ static struct pci_device_id pci_tbl[] = {
         MAKE_EXTENSION_PCI(satel, 0x13c2, 0x1013),
         MAKE_EXTENSION_PCI(ttbs,  0x13c2, 0x1016),
         MAKE_EXTENSION_PCI(ttbs1401, 0x13c2, 0x1018),
+        MAKE_EXTENSION_PCI(tt1600, 0x13c2, 0x101c),
         MAKE_EXTENSION_PCI(fsacs1,0x1131, 0x4f60),
         MAKE_EXTENSION_PCI(fsacs0,0x1131, 0x4f61),
         MAKE_EXTENSION_PCI(fsact1, 0x1131, 0x5f60),
diff --git a/drivers/media/radio/dsbr100.c b/drivers/media/radio/dsbr100.c
index 613576202294..ed9cd7ad0604 100644
--- a/drivers/media/radio/dsbr100.c
+++ b/drivers/media/radio/dsbr100.c
@@ -33,6 +33,10 @@
 
  History:
 
+ Version 0.46:
+        Removed usb_dsbr100_open/close calls and radio->users counter. Also,
+        radio->muted changed to radio->status and suspend/resume calls updated.
+
  Version 0.45:
         Converted to v4l2_device.
 
@@ -100,8 +104,8 @@
  */
 #include <linux/version.h>      /* for KERNEL_VERSION MACRO     */
 
-#define DRIVER_VERSION "v0.45"
-#define RADIO_VERSION KERNEL_VERSION(0, 4, 5)
+#define DRIVER_VERSION "v0.46"
+#define RADIO_VERSION KERNEL_VERSION(0, 4, 6)
 
 #define DRIVER_AUTHOR "Markus Demleitner <msdemlei@tucana.harvard.edu>"
 #define DRIVER_DESC "D-Link DSB-R100 USB FM radio driver"
@@ -121,13 +125,15 @@ devices, that would be 76 and 91.  */
 #define FREQ_MAX 108.0
 #define FREQ_MUL 16000
 
+/* defines for radio->status */
+#define STARTED 0
+#define STOPPED 1
+
 #define videodev_to_radio(d) container_of(d, struct dsbr100_device, videodev)
 
 static int usb_dsbr100_probe(struct usb_interface *intf,
                              const struct usb_device_id *id);
 static void usb_dsbr100_disconnect(struct usb_interface *intf);
-static int usb_dsbr100_open(struct file *file);
-static int usb_dsbr100_close(struct file *file);
 static int usb_dsbr100_suspend(struct usb_interface *intf,
                                                 pm_message_t message);
 static int usb_dsbr100_resume(struct usb_interface *intf);
@@ -145,9 +151,8 @@ struct dsbr100_device {
         struct mutex lock;      /* buffer locking */
         int curfreq;
         int stereo;
-        int users;
         int removed;
-        int muted;
+        int status;
 };
 
 static struct usb_device_id usb_dsbr100_device_table [] = {
@@ -201,7 +206,7 @@ static int dsbr100_start(struct dsbr100_device *radio)
                 goto usb_control_msg_failed;
         }
 
-        radio->muted = 0;
+        radio->status = STARTED;
         mutex_unlock(&radio->lock);
         return (radio->transfer_buffer)[0];
 
@@ -244,7 +249,7 @@ static int dsbr100_stop(struct dsbr100_device *radio)
                 goto usb_control_msg_failed;
         }
 
-        radio->muted = 1;
+        radio->status = STOPPED;
         mutex_unlock(&radio->lock);
         return (radio->transfer_buffer)[0];
 
@@ -258,12 +263,12 @@ usb_control_msg_failed:
 }
 
 /* set a frequency, freq is defined by v4l's TUNER_LOW, i.e. 1/16th kHz */
-static int dsbr100_setfreq(struct dsbr100_device *radio, int freq)
+static int dsbr100_setfreq(struct dsbr100_device *radio)
 {
         int retval;
         int request;
+        int freq = (radio->curfreq / 16 * 80) / 1000 + 856;
 
-        freq = (freq / 16 * 80) / 1000 + 856;
         mutex_lock(&radio->lock);
 
         retval = usb_control_msg(radio->usbdev,
@@ -431,7 +436,7 @@ static int vidioc_s_frequency(struct file *file, void *priv,
         radio->curfreq = f->frequency;
         mutex_unlock(&radio->lock);
 
-        retval = dsbr100_setfreq(radio, radio->curfreq);
+        retval = dsbr100_setfreq(radio);
         if (retval < 0)
                 dev_warn(&radio->usbdev->dev, "Set frequency failed\n");
         return 0;
@@ -473,7 +478,7 @@ static int vidioc_g_ctrl(struct file *file, void *priv,
 
         switch (ctrl->id) {
         case V4L2_CID_AUDIO_MUTE:
-                ctrl->value = radio->muted;
+                ctrl->value = radio->status;
                 return 0;
         }
         return -EINVAL;
@@ -543,65 +548,27 @@ static int vidioc_s_audio(struct file *file, void *priv,
         return 0;
 }
 
-static int usb_dsbr100_open(struct file *file)
-{
-        struct dsbr100_device *radio = video_drvdata(file);
-        int retval;
-
-        lock_kernel();
-        radio->users = 1;
-        radio->muted = 1;
-
-        retval = dsbr100_start(radio);
-        if (retval < 0) {
-                dev_warn(&radio->usbdev->dev,
-                         "Radio did not start up properly\n");
-                radio->users = 0;
-                unlock_kernel();
-                return -EIO;
-        }
-
-        retval = dsbr100_setfreq(radio, radio->curfreq);
-        if (retval < 0)
-                dev_warn(&radio->usbdev->dev,
-                        "set frequency failed\n");
-
-        unlock_kernel();
-        return 0;
-}
-
-static int usb_dsbr100_close(struct file *file)
-{
-        struct dsbr100_device *radio = video_drvdata(file);
-        int retval;
-
-        if (!radio)
-                return -ENODEV;
-
-        mutex_lock(&radio->lock);
-        radio->users = 0;
-        mutex_unlock(&radio->lock);
-
-        if (!radio->removed) {
-                retval = dsbr100_stop(radio);
-                if (retval < 0) {
-                        dev_warn(&radio->usbdev->dev,
-                                "dsbr100_stop failed\n");
-                }
-
-        }
-        return 0;
-}
-
 /* Suspend device - stop device. */
 static int usb_dsbr100_suspend(struct usb_interface *intf, pm_message_t message)
 {
         struct dsbr100_device *radio = usb_get_intfdata(intf);
         int retval;
 
-        retval = dsbr100_stop(radio);
-        if (retval < 0)
-                dev_warn(&intf->dev, "dsbr100_stop failed\n");
+        if (radio->status == STARTED) {
+                retval = dsbr100_stop(radio);
+                if (retval < 0)
+                        dev_warn(&intf->dev, "dsbr100_stop failed\n");
+
+                /* After dsbr100_stop() status set to STOPPED.
+                 * If we want driver to start radio on resume
+                 * we set status equal to STARTED.
+                 * On resume we will check status and run radio if needed.
+                 */
+
+                mutex_lock(&radio->lock);
+                radio->status = STARTED;
+                mutex_unlock(&radio->lock);
+        }
 
         dev_info(&intf->dev, "going into suspend..\n");
 
@@ -614,9 +581,11 @@ static int usb_dsbr100_resume(struct usb_interface *intf)
         struct dsbr100_device *radio = usb_get_intfdata(intf);
         int retval;
 
-        retval = dsbr100_start(radio);
-        if (retval < 0)
-                dev_warn(&intf->dev, "dsbr100_start failed\n");
+        if (radio->status == STARTED) {
+                retval = dsbr100_start(radio);
+                if (retval < 0)
+                        dev_warn(&intf->dev, "dsbr100_start failed\n");
+        }
 
         dev_info(&intf->dev, "coming out of suspend..\n");
 
@@ -636,8 +605,6 @@ static void usb_dsbr100_video_device_release(struct video_device *videodev)
 /* File system interface */
 static const struct v4l2_file_operations usb_dsbr100_fops = {
         .owner          = THIS_MODULE,
-        .open           = usb_dsbr100_open,
-        .release        = usb_dsbr100_close,
         .ioctl          = video_ioctl2,
 };
 
@@ -695,9 +662,9 @@ static int usb_dsbr100_probe(struct usb_interface *intf,
         mutex_init(&radio->lock);
 
         radio->removed = 0;
-        radio->users = 0;
         radio->usbdev = interface_to_usbdev(intf);
         radio->curfreq = FREQ_MIN * FREQ_MUL;
+        radio->status = STOPPED;
 
         video_set_drvdata(&radio->videodev, radio);
 
diff --git a/drivers/media/radio/radio-mr800.c b/drivers/media/radio/radio-mr800.c
index cab19d05e02f..837467f93805 100644
--- a/drivers/media/radio/radio-mr800.c
+++ b/drivers/media/radio/radio-mr800.c
@@ -64,6 +64,7 @@
 #include <media/v4l2-ioctl.h>
 #include <linux/usb.h>
 #include <linux/version.h>      /* for KERNEL_VERSION MACRO */
+#include <linux/mutex.h>
 
 /* driver and module definitions */
 #define DRIVER_AUTHOR "Alexey Klimov <klimov.linux@gmail.com>"
diff --git a/drivers/media/radio/radio-sf16fmi.c b/drivers/media/radio/radio-sf16fmi.c
index 5cf6c45b91fe..49c4aab95dab 100644
--- a/drivers/media/radio/radio-sf16fmi.c
+++ b/drivers/media/radio/radio-sf16fmi.c
@@ -49,7 +49,6 @@ struct fmi
         int io;
         int curvol; /* 1 or 0 */
         unsigned long curfreq; /* freq in kHz */
-        __u32 flags;
         struct mutex lock;
 };
 
@@ -57,7 +56,7 @@ static struct fmi fmi_card;
 static struct pnp_dev *dev;
 
 /* freq is in 1/16 kHz to internal number, hw precision is 50 kHz */
-/* It is only useful to give freq in intervall of 800 (=0.05Mhz),
+/* It is only useful to give freq in interval of 800 (=0.05Mhz),
  * other bits will be truncated, e.g 92.7400016 -> 92.7, but
  * 92.7400017 -> 92.75
  */
@@ -142,7 +141,6 @@ static int vidioc_querycap(struct file *file, void  *priv,
 static int vidioc_g_tuner(struct file *file, void *priv,
                                         struct v4l2_tuner *v)
 {
-        int mult;
         struct fmi *fmi = video_drvdata(file);
 
         if (v->index > 0)
@@ -150,11 +148,10 @@ static int vidioc_g_tuner(struct file *file, void *priv,
 
         strlcpy(v->name, "FM", sizeof(v->name));
         v->type = V4L2_TUNER_RADIO;
-        mult = (fmi->flags & V4L2_TUNER_CAP_LOW) ? 1 : 1000;
-        v->rangelow = RSF16_MINFREQ / mult;
-        v->rangehigh = RSF16_MAXFREQ / mult;
+        v->rangelow = RSF16_MINFREQ;
+        v->rangehigh = RSF16_MAXFREQ;
         v->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
-        v->capability = fmi->flags & V4L2_TUNER_CAP_LOW;
+        v->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LOW;
         v->audmode = V4L2_TUNER_MODE_STEREO;
         v->signal = fmi_getsigstr(fmi);
         return 0;
@@ -171,8 +168,6 @@ static int vidioc_s_frequency(struct file *file, void *priv,
 {
         struct fmi *fmi = video_drvdata(file);
 
-        if (!(fmi->flags & V4L2_TUNER_CAP_LOW))
-                f->frequency *= 1000;
         if (f->frequency < RSF16_MINFREQ ||
                         f->frequency > RSF16_MAXFREQ)
                 return -EINVAL;
@@ -189,8 +184,6 @@ static int vidioc_g_frequency(struct file *file, void *priv,
 
         f->type = V4L2_TUNER_RADIO;
         f->frequency = fmi->curfreq;
-        if (!(fmi->flags & V4L2_TUNER_CAP_LOW))
-                f->frequency /= 1000;
         return 0;
 }
 
@@ -347,7 +340,6 @@ static int __init fmi_init(void)
                 return res;
         }
 
-        fmi->flags = V4L2_TUNER_CAP_LOW;
         strlcpy(fmi->vdev.name, v4l2_dev->name, sizeof(fmi->vdev.name));
         fmi->vdev.v4l2_dev = v4l2_dev;
         fmi->vdev.fops = &fmi_fops;
diff --git a/drivers/media/radio/radio-sf16fmr2.c b/drivers/media/radio/radio-sf16fmr2.c
index 935ff9bcdfcc..a11414f648d4 100644
--- a/drivers/media/radio/radio-sf16fmr2.c
+++ b/drivers/media/radio/radio-sf16fmr2.c
@@ -61,13 +61,12 @@ struct fmr2
         int stereo; /* card is producing stereo audio */
         unsigned long curfreq; /* freq in kHz */
         int card_type;
-        u32 flags;
 };
 
 static struct fmr2 fmr2_card;
 
 /* hw precision is 12.5 kHz
- * It is only useful to give freq in intervall of 200 (=0.0125Mhz),
+ * It is only useful to give freq in interval of 200 (=0.0125Mhz),
  * other bits will be truncated
  */
 #define RSF16_ENCODE(x) ((x) / 200 + 856)
@@ -221,7 +220,6 @@ static int vidioc_querycap(struct file *file, void  *priv,
 static int vidioc_g_tuner(struct file *file, void *priv,
                                         struct v4l2_tuner *v)
 {
-        int mult;
         struct fmr2 *fmr2 = video_drvdata(file);
 
         if (v->index > 0)
@@ -230,13 +228,12 @@ static int vidioc_g_tuner(struct file *file, void *priv,
         strlcpy(v->name, "FM", sizeof(v->name));
         v->type = V4L2_TUNER_RADIO;
 
-        mult = (fmr2->flags & V4L2_TUNER_CAP_LOW) ? 1 : 1000;
-        v->rangelow = RSF16_MINFREQ / mult;
-        v->rangehigh = RSF16_MAXFREQ / mult;
-        v->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
-        v->capability = fmr2->flags&V4L2_TUNER_CAP_LOW;
-        v->audmode = fmr2->stereo ? V4L2_TUNER_MODE_STEREO:
-                                V4L2_TUNER_MODE_MONO;
+        v->rangelow = RSF16_MINFREQ;
+        v->rangehigh = RSF16_MAXFREQ;
+        v->rxsubchans = fmr2->stereo ? V4L2_TUNER_SUB_STEREO :
+                                        V4L2_TUNER_SUB_MONO;
+        v->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LOW;
+        v->audmode = V4L2_TUNER_MODE_STEREO;
         mutex_lock(&fmr2->lock);
         v->signal = fmr2_getsigstr(fmr2);
         mutex_unlock(&fmr2->lock);
@@ -254,8 +251,6 @@ static int vidioc_s_frequency(struct file *file, void *priv,
 {
         struct fmr2 *fmr2 = video_drvdata(file);
 
-        if (!(fmr2->flags & V4L2_TUNER_CAP_LOW))
-                f->frequency *= 1000;
         if (f->frequency < RSF16_MINFREQ ||
                         f->frequency > RSF16_MAXFREQ)
                 return -EINVAL;
@@ -279,8 +274,6 @@ static int vidioc_g_frequency(struct file *file, void *priv,
 
         f->type = V4L2_TUNER_RADIO;
         f->frequency = fmr2->curfreq;
-        if (!(fmr2->flags & V4L2_TUNER_CAP_LOW))
-                f->frequency /= 1000;
         return 0;
 }
 
@@ -406,7 +399,6 @@ static int __init fmr2_init(void)
         strlcpy(v4l2_dev->name, "sf16fmr2", sizeof(v4l2_dev->name));
         fmr2->io = io;
         fmr2->stereo = 1;
-        fmr2->flags = V4L2_TUNER_CAP_LOW;
         mutex_init(&fmr2->lock);
 
         if (!request_region(fmr2->io, 2, "sf16fmr2")) {
diff --git a/drivers/media/radio/radio-si470x.c b/drivers/media/radio/radio-si470x.c
index bd945d04dc90..640421ceb24a 100644
--- a/drivers/media/radio/radio-si470x.c
+++ b/drivers/media/radio/radio-si470x.c
@@ -1214,7 +1214,6 @@ static int si470x_fops_release(struct file *file)
                 usb_autopm_put_interface(radio->intf);
         }
 
-unlock:
         mutex_unlock(&radio->disconnect_lock);
 
 done:
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index 57835f5715fc..94f440535c64 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -440,6 +440,24 @@ config VIDEO_ADV7175
           To compile this driver as a module, choose M here: the
           module will be called adv7175.
 
+config VIDEO_THS7303
+        tristate "THS7303 Video Amplifier"
+        depends on I2C
+        help
+          Support for TI THS7303 video amplifier
+
+          To compile this driver as a module, choose M here: the
+          module will be called ths7303.
+
+config VIDEO_ADV7343
+        tristate "ADV7343 video encoder"
+        depends on I2C
+        help
+          Support for Analog Devices I2C bus based ADV7343 encoder.
+
+          To compile this driver as a module, choose M here: the
+          module will be called adv7343.
+
 comment "Video improvement chips"
 
 config VIDEO_UPD64031A
@@ -694,7 +712,7 @@ config VIDEO_CAFE_CCIC
 
 config SOC_CAMERA
         tristate "SoC camera support"
-        depends on VIDEO_V4L2 && HAS_DMA
+        depends on VIDEO_V4L2 && HAS_DMA && I2C
         select VIDEOBUF_GEN
         help
           SoC Camera is a common API to several cameras, not connecting
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index 3f1a0350a569..7fb3add1b387 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -12,6 +12,8 @@ omap2cam-objs	:=	omap24xxcam.o omap24xxcam-dma.o
 
 videodev-objs   :=      v4l2-dev.o v4l2-ioctl.o v4l2-device.o
 
+# V4L2 core modules
+
 obj-$(CONFIG_VIDEO_DEV) += videodev.o v4l2-int-device.o
 ifeq ($(CONFIG_COMPAT),y)
   obj-$(CONFIG_VIDEO_DEV) += v4l2-compat-ioctl32.o
@@ -23,21 +25,15 @@ ifeq ($(CONFIG_VIDEO_V4L1_COMPAT),y)
   obj-$(CONFIG_VIDEO_DEV) += v4l1-compat.o
 endif
 
-obj-$(CONFIG_VIDEO_TUNER) += tuner.o
+# All i2c modules must come first:
 
-obj-$(CONFIG_VIDEO_BT848) += bt8xx/
-obj-$(CONFIG_VIDEO_IR_I2C)  += ir-kbd-i2c.o
+obj-$(CONFIG_VIDEO_TUNER) += tuner.o
 obj-$(CONFIG_VIDEO_TVAUDIO) += tvaudio.o
 obj-$(CONFIG_VIDEO_TDA7432) += tda7432.o
 obj-$(CONFIG_VIDEO_TDA9875) += tda9875.o
-
 obj-$(CONFIG_VIDEO_SAA6588) += saa6588.o
 obj-$(CONFIG_VIDEO_SAA5246A) += saa5246a.o
 obj-$(CONFIG_VIDEO_SAA5249) += saa5249.o
-obj-$(CONFIG_VIDEO_CQCAM) += c-qcam.o
-obj-$(CONFIG_VIDEO_BWQCAM) += bw-qcam.o
-obj-$(CONFIG_VIDEO_W9966) += w9966.o
-
 obj-$(CONFIG_VIDEO_TDA9840) += tda9840.o
 obj-$(CONFIG_VIDEO_TEA6415C) += tea6415c.o
 obj-$(CONFIG_VIDEO_TEA6420) += tea6420.o
@@ -49,16 +45,47 @@ obj-$(CONFIG_VIDEO_SAA7185) += saa7185.o
 obj-$(CONFIG_VIDEO_SAA7191) += saa7191.o
 obj-$(CONFIG_VIDEO_ADV7170) += adv7170.o
 obj-$(CONFIG_VIDEO_ADV7175) += adv7175.o
+obj-$(CONFIG_VIDEO_ADV7343) += adv7343.o
 obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o
 obj-$(CONFIG_VIDEO_BT819) += bt819.o
 obj-$(CONFIG_VIDEO_BT856) += bt856.o
 obj-$(CONFIG_VIDEO_BT866) += bt866.o
 obj-$(CONFIG_VIDEO_KS0127) += ks0127.o
+obj-$(CONFIG_VIDEO_THS7303) += ths7303.o
+obj-$(CONFIG_VIDEO_VINO) += indycam.o
+obj-$(CONFIG_VIDEO_TVP5150) += tvp5150.o
+obj-$(CONFIG_VIDEO_TVP514X) += tvp514x.o
+obj-$(CONFIG_VIDEO_MSP3400) += msp3400.o
+obj-$(CONFIG_VIDEO_CS5345) += cs5345.o
+obj-$(CONFIG_VIDEO_CS53L32A) += cs53l32a.o
+obj-$(CONFIG_VIDEO_M52790) += m52790.o
+obj-$(CONFIG_VIDEO_TLV320AIC23B) += tlv320aic23b.o
+obj-$(CONFIG_VIDEO_WM8775) += wm8775.o
+obj-$(CONFIG_VIDEO_WM8739) += wm8739.o
+obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o
+obj-$(CONFIG_VIDEO_CX25840) += cx25840/
+obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o
+obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o
+obj-$(CONFIG_VIDEO_OV7670)      += ov7670.o
+obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o
+obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o
 
-obj-$(CONFIG_VIDEO_ZORAN) += zoran/
+obj-$(CONFIG_SOC_CAMERA_MT9M001)        += mt9m001.o
+obj-$(CONFIG_SOC_CAMERA_MT9M111)        += mt9m111.o
+obj-$(CONFIG_SOC_CAMERA_MT9T031)        += mt9t031.o
+obj-$(CONFIG_SOC_CAMERA_MT9V022)        += mt9v022.o
+obj-$(CONFIG_SOC_CAMERA_OV772X)         += ov772x.o
+obj-$(CONFIG_SOC_CAMERA_TW9910)         += tw9910.o
 
+# And now the v4l2 drivers:
+
+obj-$(CONFIG_VIDEO_BT848) += bt8xx/
+obj-$(CONFIG_VIDEO_ZORAN) += zoran/
+obj-$(CONFIG_VIDEO_CQCAM) += c-qcam.o
+obj-$(CONFIG_VIDEO_BWQCAM) += bw-qcam.o
+obj-$(CONFIG_VIDEO_W9966) += w9966.o
 obj-$(CONFIG_VIDEO_PMS) += pms.o
-obj-$(CONFIG_VIDEO_VINO) += vino.o indycam.o
+obj-$(CONFIG_VIDEO_VINO) += vino.o
 obj-$(CONFIG_VIDEO_STRADIS) += stradis.o
 obj-$(CONFIG_VIDEO_CPIA) += cpia.o
 obj-$(CONFIG_VIDEO_CPIA_PP) += cpia_pp.o
@@ -69,17 +96,7 @@ obj-$(CONFIG_VIDEO_CX88) += cx88/
 obj-$(CONFIG_VIDEO_EM28XX) += em28xx/
 obj-$(CONFIG_VIDEO_CX231XX) += cx231xx/
 obj-$(CONFIG_VIDEO_USBVISION) += usbvision/
-obj-$(CONFIG_VIDEO_TVP5150) += tvp5150.o
-obj-$(CONFIG_VIDEO_TVP514X) += tvp514x.o
 obj-$(CONFIG_VIDEO_PVRUSB2) += pvrusb2/
-obj-$(CONFIG_VIDEO_MSP3400) += msp3400.o
-obj-$(CONFIG_VIDEO_CS5345) += cs5345.o
-obj-$(CONFIG_VIDEO_CS53L32A) += cs53l32a.o
-obj-$(CONFIG_VIDEO_M52790) += m52790.o
-obj-$(CONFIG_VIDEO_TLV320AIC23B) += tlv320aic23b.o
-obj-$(CONFIG_VIDEO_WM8775) += wm8775.o
-obj-$(CONFIG_VIDEO_WM8739) += wm8739.o
-obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o
 obj-$(CONFIG_VIDEO_OVCAMCHIP) += ovcamchip/
 obj-$(CONFIG_VIDEO_CPIA2) += cpia2/
 obj-$(CONFIG_VIDEO_MXB) += mxb.o
@@ -92,19 +109,12 @@ obj-$(CONFIG_VIDEOBUF_DMA_CONTIG) += videobuf-dma-contig.o
 obj-$(CONFIG_VIDEOBUF_VMALLOC) += videobuf-vmalloc.o
 obj-$(CONFIG_VIDEOBUF_DVB) += videobuf-dvb.o
 obj-$(CONFIG_VIDEO_BTCX)  += btcx-risc.o
-obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o
 
 obj-$(CONFIG_VIDEO_M32R_AR_M64278) += arv.o
 
-obj-$(CONFIG_VIDEO_CX25840) += cx25840/
-obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o
-obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o
 obj-$(CONFIG_VIDEO_CX2341X) += cx2341x.o
 
 obj-$(CONFIG_VIDEO_CAFE_CCIC) += cafe_ccic.o
-obj-$(CONFIG_VIDEO_OV7670)      += ov7670.o
-
-obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o
 
 obj-$(CONFIG_USB_DABUSB)        += dabusb.o
 obj-$(CONFIG_USB_OV511)         += ov511.o
@@ -134,24 +144,21 @@ obj-$(CONFIG_VIDEO_CX18) += cx18/
 obj-$(CONFIG_VIDEO_VIVI) += vivi.o
 obj-$(CONFIG_VIDEO_CX23885) += cx23885/
 
+obj-$(CONFIG_VIDEO_OMAP2)               += omap2cam.o
+obj-$(CONFIG_SOC_CAMERA)                += soc_camera.o
+obj-$(CONFIG_SOC_CAMERA_PLATFORM)       += soc_camera_platform.o
+# soc-camera host drivers have to be linked after camera drivers
 obj-$(CONFIG_VIDEO_MX1)                 += mx1_camera.o
 obj-$(CONFIG_VIDEO_MX3)                 += mx3_camera.o
 obj-$(CONFIG_VIDEO_PXA27x)              += pxa_camera.o
 obj-$(CONFIG_VIDEO_SH_MOBILE_CEU)       += sh_mobile_ceu_camera.o
-obj-$(CONFIG_VIDEO_OMAP2)               += omap2cam.o
-obj-$(CONFIG_SOC_CAMERA)                += soc_camera.o
-obj-$(CONFIG_SOC_CAMERA_MT9M001)        += mt9m001.o
-obj-$(CONFIG_SOC_CAMERA_MT9M111)        += mt9m111.o
-obj-$(CONFIG_SOC_CAMERA_MT9T031)        += mt9t031.o
-obj-$(CONFIG_SOC_CAMERA_MT9V022)        += mt9v022.o
-obj-$(CONFIG_SOC_CAMERA_OV772X)         += ov772x.o
-obj-$(CONFIG_SOC_CAMERA_PLATFORM)       += soc_camera_platform.o
-obj-$(CONFIG_SOC_CAMERA_TW9910)         += tw9910.o
 
 obj-$(CONFIG_VIDEO_AU0828) += au0828/
 
 obj-$(CONFIG_USB_VIDEO_CLASS)   += uvc/
 
+obj-$(CONFIG_VIDEO_IR_I2C)  += ir-kbd-i2c.o
+
 EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core
 EXTRA_CFLAGS += -Idrivers/media/dvb/frontends
 EXTRA_CFLAGS += -Idrivers/media/common/tuners
diff --git a/drivers/media/video/adv7343.c b/drivers/media/video/adv7343.c
new file mode 100644
index 000000000000..30f5caf5dda5
--- /dev/null
+++ b/drivers/media/video/adv7343.c
@@ -0,0 +1,534 @@
+/*
+ * adv7343 - ADV7343 Video Encoder Driver
+ *
+ * The encoder hardware does not support SECAM.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed .as is. WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ctype.h>
+#include <linux/i2c.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/videodev2.h>
+#include <linux/uaccess.h>
+#include <linux/version.h>
+
+#include <media/adv7343.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-chip-ident.h>
+
+#include "adv7343_regs.h"
+
+MODULE_DESCRIPTION("ADV7343 video encoder driver");
+MODULE_LICENSE("GPL");
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Debug level 0-1");
+
+struct adv7343_state {
+        struct v4l2_subdev sd;
+        u8 reg00;
+        u8 reg01;
+        u8 reg02;
+        u8 reg35;
+        u8 reg80;
+        u8 reg82;
+        int bright;
+        int hue;
+        int gain;
+        u32 output;
+        v4l2_std_id std;
+};
+
+static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
+{
+        return container_of(sd, struct adv7343_state, sd);
+}
+
+static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
+{
+        struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+        return i2c_smbus_write_byte_data(client, reg, value);
+}
+
+static const u8 adv7343_init_reg_val[] = {
+        ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
+        ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
+
+        ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
+        ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
+        ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
+        ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
+        ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
+        ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
+        ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
+
+        ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
+        ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
+        ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
+        ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
+        ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
+        ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
+        ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
+        ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
+
+        ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
+        ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
+        ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
+};
+
+/*
+ *                          2^32
+ * FSC(reg) =  FSC (HZ) * --------
+ *                        27000000
+ */
+static const struct adv7343_std_info stdinfo[] = {
+        {
+                /* FSC(Hz) = 3,579,545.45 Hz */
+                SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
+        }, {
+                /* FSC(Hz) = 3,575,611.00 Hz */
+                SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
+        }, {
+                /* FSC(Hz) = 3,582,056.00 */
+                SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
+        }, {
+                /* FSC(Hz) = 4,433,618.75 Hz */
+                SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
+        }, {
+                /* FSC(Hz) = 4,433,618.75 Hz */
+                SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
+        }, {
+                /* FSC(Hz) = 4,433,618.75 Hz */
+                SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
+        }, {
+                /* FSC(Hz) = 4,433,618.75 Hz */
+                SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
+        },
+};
+
+static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
+{
+        struct adv7343_state *state = to_state(sd);
+        struct adv7343_std_info *std_info;
+        int output_idx, num_std;
+        char *fsc_ptr;
+        u8 reg, val;
+        int err = 0;
+        int i = 0;
+
+        output_idx = state->output;
+
+        std_info = (struct adv7343_std_info *)stdinfo;
+        num_std = ARRAY_SIZE(stdinfo);
+
+        for (i = 0; i < num_std; i++) {
+                if (std_info[i].stdid & std)
+                        break;
+        }
+
+        if (i == num_std) {
+                v4l2_dbg(1, debug, sd,
+                                "Invalid std or std is not supported: %llx\n",
+                                                (unsigned long long)std);
+                return -EINVAL;
+        }
+
+        /* Set the standard */
+        val = state->reg80 & (~(SD_STD_MASK));
+        val |= std_info[i].standard_val3;
+        err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
+        if (err < 0)
+                goto setstd_exit;
+
+        state->reg80 = val;
+
+        /* Configure the input mode register */
+        val = state->reg01 & (~((u8) INPUT_MODE_MASK));
+        val |= SD_INPUT_MODE;
+        err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
+        if (err < 0)
+                goto setstd_exit;
+
+        state->reg01 = val;
+
+        /* Program the sub carrier frequency registers */
+        fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
+        reg = ADV7343_FSC_REG0;
+        for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
+                err = adv7343_write(sd, reg, *fsc_ptr);
+                if (err < 0)
+                        goto setstd_exit;
+        }
+
+        val = state->reg80;
+
+        /* Filter settings */
+        if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
+                val &= 0x03;
+        else if (std & ~V4L2_STD_SECAM)
+                val |= 0x04;
+
+        err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
+        if (err < 0)
+                goto setstd_exit;
+
+        state->reg80 = val;
+
+setstd_exit:
+        if (err != 0)
+                v4l2_err(sd, "Error setting std, write failed\n");
+
+        return err;
+}
+
+static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
+{
+        struct adv7343_state *state = to_state(sd);
+        unsigned char val;
+        int err = 0;
+
+        if (output_type > ADV7343_SVIDEO_ID) {
+                v4l2_dbg(1, debug, sd,
+                        "Invalid output type or output type not supported:%d\n",
+                                                                output_type);
+                return -EINVAL;
+        }
+
+        /* Enable Appropriate DAC */
+        val = state->reg00 & 0x03;
+
+        if (output_type == ADV7343_COMPOSITE_ID)
+                val |= ADV7343_COMPOSITE_POWER_VALUE;
+        else if (output_type == ADV7343_COMPONENT_ID)
+                val |= ADV7343_COMPONENT_POWER_VALUE;
+        else
+                val |= ADV7343_SVIDEO_POWER_VALUE;
+
+        err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
+        if (err < 0)
+                goto setoutput_exit;
+
+        state->reg00 = val;
+
+        /* Enable YUV output */
+        val = state->reg02 | YUV_OUTPUT_SELECT;
+        err = adv7343_write(sd, ADV7343_MODE_REG0, val);
+        if (err < 0)
+                goto setoutput_exit;
+
+        state->reg02 = val;
+
+        /* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
+        val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
+        err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
+        if (err < 0)
+                goto setoutput_exit;
+
+        state->reg82 = val;
+
+        /* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
+         * zero */
+        val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
+        err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
+        if (err < 0)
+                goto setoutput_exit;
+
+        state->reg35 = val;
+
+setoutput_exit:
+        if (err != 0)
+                v4l2_err(sd, "Error setting output, write failed\n");
+
+        return err;
+}
+
+static int adv7343_log_status(struct v4l2_subdev *sd)
+{
+        struct adv7343_state *state = to_state(sd);
+
+        v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
+        v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
+                        ((state->output == 1) ? "Component" : "S-Video"));
+        return 0;
+}
+
+static int adv7343_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
+{
+        switch (qc->id) {
+        case V4L2_CID_BRIGHTNESS:
+                return v4l2_ctrl_query_fill(qc, ADV7343_BRIGHTNESS_MIN,
+                                                ADV7343_BRIGHTNESS_MAX, 1,
+                                                ADV7343_BRIGHTNESS_DEF);
+        case V4L2_CID_HUE:
+                return v4l2_ctrl_query_fill(qc, ADV7343_HUE_MIN,
+                                                ADV7343_HUE_MAX, 1 ,
+                                                ADV7343_HUE_DEF);
+        case V4L2_CID_GAIN:
+                return v4l2_ctrl_query_fill(qc, ADV7343_GAIN_MIN,
+                                                ADV7343_GAIN_MAX, 1,
+                                                ADV7343_GAIN_DEF);
+        default:
+                break;
+        }
+
+        return 0;
+}
+
+static int adv7343_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+        struct adv7343_state *state = to_state(sd);
+        int err = 0;
+
+        switch (ctrl->id) {
+        case V4L2_CID_BRIGHTNESS:
+                if (ctrl->value < ADV7343_BRIGHTNESS_MIN ||
+                                        ctrl->value > ADV7343_BRIGHTNESS_MAX) {
+                        v4l2_dbg(1, debug, sd,
+                                        "invalid brightness settings %d\n",
+                                                                ctrl->value);
+                        return -ERANGE;
+                }
+
+                state->bright = ctrl->value;
+                err = adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
+                                        state->bright);
+                break;
+
+        case V4L2_CID_HUE:
+                if (ctrl->value < ADV7343_HUE_MIN ||
+                                        ctrl->value > ADV7343_HUE_MAX) {
+                        v4l2_dbg(1, debug, sd, "invalid hue settings %d\n",
+                                                                ctrl->value);
+                        return -ERANGE;
+                }
+
+                state->hue = ctrl->value;
+                err = adv7343_write(sd, ADV7343_SD_HUE_REG, state->hue);
+                break;
+
+        case V4L2_CID_GAIN:
+                if (ctrl->value < ADV7343_GAIN_MIN ||
+                                        ctrl->value > ADV7343_GAIN_MAX) {
+                        v4l2_dbg(1, debug, sd, "invalid gain settings %d\n",
+                                                                ctrl->value);
+                        return -ERANGE;
+                }
+
+                if ((ctrl->value > POSITIVE_GAIN_MAX) &&
+                        (ctrl->value < NEGATIVE_GAIN_MIN)) {
+                        v4l2_dbg(1, debug, sd,
+                                "gain settings not within the specified range\n");
+                        return -ERANGE;
+                }
+
+                state->gain = ctrl->value;
+                err = adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, state->gain);
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        if (err < 0)
+                v4l2_err(sd, "Failed to set the encoder controls\n");
+
+        return err;
+}
+
+static int adv7343_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
+{
+        struct adv7343_state *state = to_state(sd);
+
+        switch (ctrl->id) {
+        case V4L2_CID_BRIGHTNESS:
+                ctrl->value = state->bright;
+                break;
+
+        case V4L2_CID_HUE:
+                ctrl->value = state->hue;
+                break;
+
+        case V4L2_CID_GAIN:
+                ctrl->value = state->gain;
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int adv7343_g_chip_ident(struct v4l2_subdev *sd,
+                                struct v4l2_dbg_chip_ident *chip)
+{
+        struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+        return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7343, 0);
+}
+
+static const struct v4l2_subdev_core_ops adv7343_core_ops = {
+        .log_status     = adv7343_log_status,
+        .g_chip_ident   = adv7343_g_chip_ident,
+        .g_ctrl         = adv7343_g_ctrl,
+        .s_ctrl         = adv7343_s_ctrl,
+        .queryctrl      = adv7343_queryctrl,
+};
+
+static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
+{
+        struct adv7343_state *state = to_state(sd);
+        int err = 0;
+
+        if (state->std == std)
+                return 0;
+
+        err = adv7343_setstd(sd, std);
+        if (!err)
+                state->std = std;
+
+        return err;
+}
+
+static int adv7343_s_routing(struct v4l2_subdev *sd,
+                u32 input, u32 output, u32 config)
+{
+        struct adv7343_state *state = to_state(sd);
+        int err = 0;
+
+        if (state->output == output)
+                return 0;
+
+        err = adv7343_setoutput(sd, output);
+        if (!err)
+                state->output = output;
+
+        return err;
+}
+
+static const struct v4l2_subdev_video_ops adv7343_video_ops = {
+        .s_std_output   = adv7343_s_std_output,
+        .s_routing      = adv7343_s_routing,
+};
+
+static const struct v4l2_subdev_ops adv7343_ops = {
+        .core   = &adv7343_core_ops,
+        .video  = &adv7343_video_ops,
+};
+
+static int adv7343_initialize(struct v4l2_subdev *sd)
+{
+        struct adv7343_state *state = to_state(sd);
+        int err = 0;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
+
+                err = adv7343_write(sd, adv7343_init_reg_val[i],
+                                        adv7343_init_reg_val[i+1]);
+                if (err) {
+                        v4l2_err(sd, "Error initializing\n");
+                        return err;
+                }
+        }
+
+        /* Configure for default video standard */
+        err = adv7343_setoutput(sd, state->output);
+        if (err < 0) {
+                v4l2_err(sd, "Error setting output during init\n");
+                return -EINVAL;
+        }
+
+        err = adv7343_setstd(sd, state->std);
+        if (err < 0) {
+                v4l2_err(sd, "Error setting std during init\n");
+                return -EINVAL;
+        }
+
+        return err;
+}
+
+static int adv7343_probe(struct i2c_client *client,
+                                const struct i2c_device_id *id)
+{
+        struct adv7343_state *state;
+
+        if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+                return -ENODEV;
+
+        v4l_info(client, "chip found @ 0x%x (%s)\n",
+                        client->addr << 1, client->adapter->name);
+
+        state = kzalloc(sizeof(struct adv7343_state), GFP_KERNEL);
+        if (state == NULL)
+                return -ENOMEM;
+
+        state->reg00    = 0x80;
+        state->reg01    = 0x00;
+        state->reg02    = 0x20;
+        state->reg35    = 0x00;
+        state->reg80    = ADV7343_SD_MODE_REG1_DEFAULT;
+        state->reg82    = ADV7343_SD_MODE_REG2_DEFAULT;
+
+        state->output = ADV7343_COMPOSITE_ID;
+        state->std = V4L2_STD_NTSC;
+
+        v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
+        return adv7343_initialize(&state->sd);
+}
+
+static int adv7343_remove(struct i2c_client *client)
+{
+        struct v4l2_subdev *sd = i2c_get_clientdata(client);
+
+        v4l2_device_unregister_subdev(sd);
+        kfree(to_state(sd));
+
+        return 0;
+}
+
+static const struct i2c_device_id adv7343_id[] = {
+        {"adv7343", 0},
+        {},
+};
+
+MODULE_DEVICE_TABLE(i2c, adv7343_id);
+
+static struct i2c_driver adv7343_driver = {
+        .driver = {
+                .owner  = THIS_MODULE,
+                .name   = "adv7343",
+        },
+        .probe          = adv7343_probe,
+        .remove         = adv7343_remove,
+        .id_table       = adv7343_id,
+};
+
+static __init int init_adv7343(void)
+{
+        return i2c_add_driver(&adv7343_driver);
+}
+
+static __exit void exit_adv7343(void)
+{
+        i2c_del_driver(&adv7343_driver);
+}
+
+module_init(init_adv7343);
+module_exit(exit_adv7343);
diff --git a/drivers/media/video/adv7343_regs.h b/drivers/media/video/adv7343_regs.h
new file mode 100644
index 000000000000..3431045b33da
--- /dev/null
+++ b/drivers/media/video/adv7343_regs.h
@@ -0,0 +1,185 @@
+/*
+ * ADV7343 encoder related structure and register definitions
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed .as is. WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ADV7343_REG_H
+#define ADV7343_REGS_H
+
+struct adv7343_std_info {
+        u32 standard_val3;
+        u32 fsc_val;
+        v4l2_std_id stdid;
+};
+
+/* Register offset macros */
+#define ADV7343_POWER_MODE_REG          (0x00)
+#define ADV7343_MODE_SELECT_REG         (0x01)
+#define ADV7343_MODE_REG0               (0x02)
+
+#define ADV7343_DAC2_OUTPUT_LEVEL       (0x0b)
+
+#define ADV7343_SOFT_RESET              (0x17)
+
+#define ADV7343_HD_MODE_REG1            (0x30)
+#define ADV7343_HD_MODE_REG2            (0x31)
+#define ADV7343_HD_MODE_REG3            (0x32)
+#define ADV7343_HD_MODE_REG4            (0x33)
+#define ADV7343_HD_MODE_REG5            (0x34)
+#define ADV7343_HD_MODE_REG6            (0x35)
+
+#define ADV7343_HD_MODE_REG7            (0x39)
+
+#define ADV7343_SD_MODE_REG1            (0x80)
+#define ADV7343_SD_MODE_REG2            (0x82)
+#define ADV7343_SD_MODE_REG3            (0x83)
+#define ADV7343_SD_MODE_REG4            (0x84)
+#define ADV7343_SD_MODE_REG5            (0x86)
+#define ADV7343_SD_MODE_REG6            (0x87)
+#define ADV7343_SD_MODE_REG7            (0x88)
+#define ADV7343_SD_MODE_REG8            (0x89)
+
+#define ADV7343_FSC_REG0                (0x8C)
+#define ADV7343_FSC_REG1                (0x8D)
+#define ADV7343_FSC_REG2                (0x8E)
+#define ADV7343_FSC_REG3                (0x8F)
+
+#define ADV7343_SD_CGMS_WSS0            (0x99)
+
+#define ADV7343_SD_HUE_REG              (0xA0)
+#define ADV7343_SD_BRIGHTNESS_WSS       (0xA1)
+
+/* Default values for the registers */
+#define ADV7343_POWER_MODE_REG_DEFAULT          (0x10)
+#define ADV7343_HD_MODE_REG1_DEFAULT            (0x3C)  /* Changed Default
+                                                           720p EAVSAV code*/
+#define ADV7343_HD_MODE_REG2_DEFAULT            (0x01)  /* Changed Pixel data
+                                                           valid */
+#define ADV7343_HD_MODE_REG3_DEFAULT            (0x00)  /* Color delay 0 clks */
+#define ADV7343_HD_MODE_REG4_DEFAULT            (0xE8)  /* Changed */
+#define ADV7343_HD_MODE_REG5_DEFAULT            (0x08)
+#define ADV7343_HD_MODE_REG6_DEFAULT            (0x00)
+#define ADV7343_HD_MODE_REG7_DEFAULT            (0x00)
+#define ADV7343_SD_MODE_REG8_DEFAULT            (0x00)
+#define ADV7343_SOFT_RESET_DEFAULT              (0x02)
+#define ADV7343_COMPOSITE_POWER_VALUE           (0x80)
+#define ADV7343_COMPONENT_POWER_VALUE           (0x1C)
+#define ADV7343_SVIDEO_POWER_VALUE              (0x60)
+#define ADV7343_SD_HUE_REG_DEFAULT              (127)
+#define ADV7343_SD_BRIGHTNESS_WSS_DEFAULT       (0x03)
+
+#define ADV7343_SD_CGMS_WSS0_DEFAULT            (0x10)
+
+#define ADV7343_SD_MODE_REG1_DEFAULT            (0x00)
+#define ADV7343_SD_MODE_REG2_DEFAULT            (0xC9)
+#define ADV7343_SD_MODE_REG3_DEFAULT            (0x10)
+#define ADV7343_SD_MODE_REG4_DEFAULT            (0x01)
+#define ADV7343_SD_MODE_REG5_DEFAULT            (0x02)
+#define ADV7343_SD_MODE_REG6_DEFAULT            (0x0C)
+#define ADV7343_SD_MODE_REG7_DEFAULT            (0x04)
+#define ADV7343_SD_MODE_REG8_DEFAULT            (0x00)
+
+/* Bit masks for Mode Select Register */
+#define INPUT_MODE_MASK                 (0x70)
+#define SD_INPUT_MODE                   (0x00)
+#define HD_720P_INPUT_MODE              (0x10)
+#define HD_1080I_INPUT_MODE             (0x10)
+
+/* Bit masks for Mode Register 0 */
+#define TEST_PATTERN_BLACK_BAR_EN       (0x04)
+#define YUV_OUTPUT_SELECT               (0x20)
+#define RGB_OUTPUT_SELECT               (0xDF)
+
+/* Bit masks for DAC output levels */
+#define DAC_OUTPUT_LEVEL_MASK           (0xFF)
+#define POSITIVE_GAIN_MAX               (0x40)
+#define POSITIVE_GAIN_MIN               (0x00)
+#define NEGATIVE_GAIN_MAX               (0xFF)
+#define NEGATIVE_GAIN_MIN               (0xC0)
+
+/* Bit masks for soft reset register */
+#define SOFT_RESET                      (0x02)
+
+/* Bit masks for HD Mode Register 1 */
+#define OUTPUT_STD_MASK         (0x03)
+#define OUTPUT_STD_SHIFT        (0)
+#define OUTPUT_STD_EIA0_2       (0x00)
+#define OUTPUT_STD_EIA0_1       (0x01)
+#define OUTPUT_STD_FULL         (0x02)
+#define EMBEDDED_SYNC           (0x04)
+#define EXTERNAL_SYNC           (0xFB)
+#define STD_MODE_SHIFT          (3)
+#define STD_MODE_MASK           (0x1F)
+#define STD_MODE_720P           (0x05)
+#define STD_MODE_720P_25        (0x08)
+#define STD_MODE_720P_30        (0x07)
+#define STD_MODE_720P_50        (0x06)
+#define STD_MODE_1080I          (0x0D)
+#define STD_MODE_1080I_25fps    (0x0E)
+#define STD_MODE_1080P_24       (0x12)
+#define STD_MODE_1080P_25       (0x10)
+#define STD_MODE_1080P_30       (0x0F)
+#define STD_MODE_525P           (0x00)
+#define STD_MODE_625P           (0x03)
+
+/* Bit masks for SD Mode Register 1 */
+#define SD_STD_MASK             (0x03)
+#define SD_STD_NTSC             (0x00)
+#define SD_STD_PAL_BDGHI        (0x01)
+#define SD_STD_PAL_M            (0x02)
+#define SD_STD_PAL_N            (0x03)
+#define SD_LUMA_FLTR_MASK       (0x7)
+#define SD_LUMA_FLTR_SHIFT      (0x2)
+#define SD_CHROMA_FLTR_MASK     (0x7)
+#define SD_CHROMA_FLTR_SHIFT    (0x5)
+
+/* Bit masks for SD Mode Register 2 */
+#define SD_PBPR_SSAF_EN         (0x01)
+#define SD_PBPR_SSAF_DI         (0xFE)
+#define SD_DAC_1_DI             (0xFD)
+#define SD_DAC_2_DI             (0xFB)
+#define SD_PEDESTAL_EN          (0x08)
+#define SD_PEDESTAL_DI          (0xF7)
+#define SD_SQUARE_PIXEL_EN      (0x10)
+#define SD_SQUARE_PIXEL_DI      (0xEF)
+#define SD_PIXEL_DATA_VALID     (0x40)
+#define SD_ACTIVE_EDGE_EN       (0x80)
+#define SD_ACTIVE_EDGE_DI       (0x7F)
+
+/* Bit masks for HD Mode Register 6 */
+#define HD_RGB_INPUT_EN         (0x02)
+#define HD_RGB_INPUT_DI         (0xFD)
+#define HD_PBPR_SYNC_EN         (0x04)
+#define HD_PBPR_SYNC_DI         (0xFB)
+#define HD_DAC_SWAP_EN          (0x08)
+#define HD_DAC_SWAP_DI          (0xF7)
+#define HD_GAMMA_CURVE_A        (0xEF)
+#define HD_GAMMA_CURVE_B        (0x10)
+#define HD_GAMMA_EN             (0x20)
+#define HD_GAMMA_DI             (0xDF)
+#define HD_ADPT_FLTR_MODEB      (0x40)
+#define HD_ADPT_FLTR_MODEA      (0xBF)
+#define HD_ADPT_FLTR_EN         (0x80)
+#define HD_ADPT_FLTR_DI         (0x7F)
+
+#define ADV7343_BRIGHTNESS_MAX  (127)
+#define ADV7343_BRIGHTNESS_MIN  (0)
+#define ADV7343_BRIGHTNESS_DEF  (3)
+#define ADV7343_HUE_MAX         (255)
+#define ADV7343_HUE_MIN         (0)
+#define ADV7343_HUE_DEF         (127)
+#define ADV7343_GAIN_MAX        (255)
+#define ADV7343_GAIN_MIN        (0)
+#define ADV7343_GAIN_DEF        (0)
+
+#endif
diff --git a/drivers/media/video/au0828/au0828-cards.c b/drivers/media/video/au0828/au0828-cards.c
index 053bbe8c8e3a..830c4a933f63 100644
--- a/drivers/media/video/au0828/au0828-cards.c
+++ b/drivers/media/video/au0828/au0828-cards.c
@@ -136,9 +136,9 @@ int au0828_tuner_callback(void *priv, int component, int command, int arg)
                         /* Tuner Reset Command from xc5000 */
                         /* Drive the tuner into reset and out */
                         au0828_clear(dev, REG_001, 2);
-                        mdelay(200);
+                        mdelay(10);
                         au0828_set(dev, REG_001, 2);
-                        mdelay(50);
+                        mdelay(10);
                         return 0;
                 } else {
                         printk(KERN_ERR
diff --git a/drivers/media/video/au0828/au0828-core.c b/drivers/media/video/au0828/au0828-core.c
index a1e4c0d769a6..3544a2f12f13 100644
--- a/drivers/media/video/au0828/au0828-core.c
+++ b/drivers/media/video/au0828/au0828-core.c
@@ -36,6 +36,11 @@ int au0828_debug;
 module_param_named(debug, au0828_debug, int, 0644);
 MODULE_PARM_DESC(debug, "enable debug messages");
 
+static unsigned int disable_usb_speed_check;
+module_param(disable_usb_speed_check, int, 0444);
+MODULE_PARM_DESC(disable_usb_speed_check,
+                 "override min bandwidth requirement of 480M bps");
+
 #define _AU0828_BULKPIPE 0x03
 #define _BULKPIPESIZE 0xffff
 
@@ -181,6 +186,18 @@ static int au0828_usb_probe(struct usb_interface *interface,
                 le16_to_cpu(usbdev->descriptor.idProduct),
                 ifnum);
 
+        /*
+         * Make sure we have 480 Mbps of bandwidth, otherwise things like
+         * video stream wouldn't likely work, since 12 Mbps is generally
+         * not enough even for most Digital TV streams.
+         */
+        if (usbdev->speed != USB_SPEED_HIGH && disable_usb_speed_check == 0) {
+                printk(KERN_ERR "au0828: Device initialization failed.\n");
+                printk(KERN_ERR "au0828: Device must be connected to a "
+                       "high-speed USB 2.0 port.\n");
+                return -ENODEV;
+        }
+
         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
         if (dev == NULL) {
                 printk(KERN_ERR "%s() Unable to allocate memory\n", __func__);
diff --git a/drivers/media/video/au0828/au0828-video.c b/drivers/media/video/au0828/au0828-video.c
index 27bedc6c7791..51527d7b55a7 100644
--- a/drivers/media/video/au0828/au0828-video.c
+++ b/drivers/media/video/au0828/au0828-video.c
@@ -829,6 +829,9 @@ static int au0828_v4l2_close(struct file *filp)
 
                 au0828_uninit_isoc(dev);
 
+                /* Save some power by putting tuner to sleep */
+                v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_standby);
+
                 /* When close the device, set the usb intf0 into alt0 to free
                    USB bandwidth */
                 ret = usb_set_interface(dev->usbdev, 0, 0);
@@ -910,11 +913,6 @@ static int au0828_v4l2_mmap(struct file *filp, struct vm_area_struct *vma)
 
         rc = videobuf_mmap_mapper(&fh->vb_vidq, vma);
 
-        dprintk(2, "vma start=0x%08lx, size=%ld, ret=%d\n",
-                (unsigned long)vma->vm_start,
-                (unsigned long)vma->vm_end-(unsigned long)vma->vm_start,
-                rc);
-
         return rc;
 }
 
diff --git a/drivers/media/video/bt8xx/bttv-driver.c b/drivers/media/video/bt8xx/bttv-driver.c
index 23b7499b3185..5eb1464af670 100644
--- a/drivers/media/video/bt8xx/bttv-driver.c
+++ b/drivers/media/video/bt8xx/bttv-driver.c
@@ -3152,6 +3152,7 @@ static unsigned int bttv_poll(struct file *file, poll_table *wait)
         struct bttv_fh *fh = file->private_data;
         struct bttv_buffer *buf;
         enum v4l2_field field;
+        unsigned int rc = POLLERR;
 
         if (V4L2_BUF_TYPE_VBI_CAPTURE == fh->type) {
                 if (!check_alloc_btres(fh->btv,fh,RESOURCE_VBI))
@@ -3160,9 +3161,10 @@ static unsigned int bttv_poll(struct file *file, poll_table *wait)
         }
 
         if (check_btres(fh,RESOURCE_VIDEO_STREAM)) {
+                mutex_lock(&fh->cap.vb_lock);
                 /* streaming capture */
                 if (list_empty(&fh->cap.stream))
-                        return POLLERR;
+                        goto err;
                 buf = list_entry(fh->cap.stream.next,struct bttv_buffer,vb.stream);
         } else {
                 /* read() capture */
@@ -3191,11 +3193,12 @@ static unsigned int bttv_poll(struct file *file, poll_table *wait)
         poll_wait(file, &buf->vb.done, wait);
         if (buf->vb.state == VIDEOBUF_DONE ||
             buf->vb.state == VIDEOBUF_ERROR)
-                return POLLIN|POLLRDNORM;
-        return 0;
+                rc =  POLLIN|POLLRDNORM;
+        else
+                rc = 0;
 err:
         mutex_unlock(&fh->cap.vb_lock);
-        return POLLERR;
+        return rc;
 }
 
 static int bttv_open(struct file *file)
@@ -4166,7 +4169,6 @@ static struct video_device *vdev_init(struct bttv *btv,
         if (NULL == vfd)
                 return NULL;
         *vfd = *template;
-        vfd->minor   = -1;
         vfd->v4l2_dev = &btv->c.v4l2_dev;
         vfd->release = video_device_release;
         vfd->debug   = bttv_debug;
@@ -4629,7 +4631,7 @@ static int __init bttv_init_module(void)
 #endif
         if (gbuffers < 2 || gbuffers > VIDEO_MAX_FRAME)
                 gbuffers = 2;
-        if (gbufsize < 0 || gbufsize > BTTV_MAX_FBUF)
+        if (gbufsize > BTTV_MAX_FBUF)
                 gbufsize = BTTV_MAX_FBUF;
         gbufsize = (gbufsize + PAGE_SIZE - 1) & PAGE_MASK;
         if (bttv_verbose)
diff --git a/drivers/media/video/bt8xx/bttv-i2c.c b/drivers/media/video/bt8xx/bttv-i2c.c
index a99d92fac3dc..ebd1ee9dc871 100644
--- a/drivers/media/video/bt8xx/bttv-i2c.c
+++ b/drivers/media/video/bt8xx/bttv-i2c.c
@@ -389,6 +389,27 @@ int __devinit init_bttv_i2c(struct bttv *btv)
         }
         if (0 == btv->i2c_rc && i2c_scan)
                 do_i2c_scan(btv->c.v4l2_dev.name, &btv->i2c_client);
+
+        /* Instantiate the IR receiver device, if present */
+        if (0 == btv->i2c_rc) {
+                struct i2c_board_info info;
+                /* The external IR receiver is at i2c address 0x34 (0x35 for
+                   reads).  Future Hauppauge cards will have an internal
+                   receiver at 0x30 (0x31 for reads).  In theory, both can be
+                   fitted, and Hauppauge suggest an external overrides an
+                   internal.
+
+                   That's why we probe 0x1a (~0x34) first. CB
+                */
+                const unsigned short addr_list[] = {
+                        0x1a, 0x18, 0x4b, 0x64, 0x30,
+                        I2C_CLIENT_END
+                };
+
+                memset(&info, 0, sizeof(struct i2c_board_info));
+                strlcpy(info.type, "ir_video", I2C_NAME_SIZE);
+                i2c_new_probed_device(&btv->c.i2c_adap, &info, addr_list);
+        }
         return btv->i2c_rc;
 }
 
diff --git a/drivers/media/video/cpia2/cpia2_v4l.c b/drivers/media/video/cpia2/cpia2_v4l.c
index d4099f5312ac..0b4a8f309cfa 100644
--- a/drivers/media/video/cpia2/cpia2_v4l.c
+++ b/drivers/media/video/cpia2/cpia2_v4l.c
@@ -1064,7 +1064,7 @@ static int ioctl_querymenu(void *arg,struct camera_data *cam)
 
         switch(m->id) {
         case CPIA2_CID_FLICKER_MODE:
-                if(m->index < 0 || m->index >= NUM_FLICKER_CONTROLS)
+                if (m->index >= NUM_FLICKER_CONTROLS)
                         return -EINVAL;
 
                 strcpy(m->name, flicker_controls[m->index].name);
@@ -1082,14 +1082,14 @@ static int ioctl_querymenu(void *arg,struct camera_data *cam)
                                         maximum = i;
                         }
                 }
-                if(m->index < 0 || m->index > maximum)
+                if (m->index > maximum)
                         return -EINVAL;
 
                 strcpy(m->name, framerate_controls[m->index].name);
                 break;
             }
         case CPIA2_CID_LIGHTS:
-                if(m->index < 0 || m->index >= NUM_LIGHTS_CONTROLS)
+                if (m->index >= NUM_LIGHTS_CONTROLS)
                         return -EINVAL;
 
                 strcpy(m->name, lights_controls[m->index].name);
diff --git a/drivers/media/video/cx18/cx18-audio.c b/drivers/media/video/cx18/cx18-audio.c
index 7a8ad5963de8..35268923911c 100644
--- a/drivers/media/video/cx18/cx18-audio.c
+++ b/drivers/media/video/cx18/cx18-audio.c
@@ -26,14 +26,18 @@
 #include "cx18-cards.h"
 #include "cx18-audio.h"
 
-#define CX18_AUDIO_ENABLE 0xc72014
+#define CX18_AUDIO_ENABLE    0xc72014
+#define CX18_AI1_MUX_MASK    0x30
+#define CX18_AI1_MUX_I2S1    0x00
+#define CX18_AI1_MUX_I2S2    0x10
+#define CX18_AI1_MUX_843_I2S 0x20
 
 /* Selects the audio input and output according to the current
    settings. */
 int cx18_audio_set_io(struct cx18 *cx)
 {
         const struct cx18_card_audio_input *in;
-        u32 val;
+        u32 u, v;
         int err;
 
         /* Determine which input to use */
@@ -52,9 +56,37 @@ int cx18_audio_set_io(struct cx18 *cx)
                 return err;
 
         /* FIXME - this internal mux should be abstracted to a subdev */
-        val = cx18_read_reg(cx, CX18_AUDIO_ENABLE) & ~0x30;
-        val |= (in->audio_input > CX18_AV_AUDIO_SERIAL2) ? 0x20 :
-                                        (in->audio_input << 4);
-        cx18_write_reg_expect(cx, val | 0xb00, CX18_AUDIO_ENABLE, val, 0x30);
+        u = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
+        v = u & ~CX18_AI1_MUX_MASK;
+        switch (in->audio_input) {
+        case CX18_AV_AUDIO_SERIAL1:
+                v |= CX18_AI1_MUX_I2S1;
+                break;
+        case CX18_AV_AUDIO_SERIAL2:
+                v |= CX18_AI1_MUX_I2S2;
+                break;
+        default:
+                v |= CX18_AI1_MUX_843_I2S;
+                break;
+        }
+        if (v == u) {
+                /* force a toggle of some AI1 MUX control bits */
+                u &= ~CX18_AI1_MUX_MASK;
+                switch (in->audio_input) {
+                case CX18_AV_AUDIO_SERIAL1:
+                        u |= CX18_AI1_MUX_843_I2S;
+                        break;
+                case CX18_AV_AUDIO_SERIAL2:
+                        u |= CX18_AI1_MUX_843_I2S;
+                        break;
+                default:
+                        u |= CX18_AI1_MUX_I2S1;
+                        break;
+                }
+                cx18_write_reg_expect(cx, u | 0xb00, CX18_AUDIO_ENABLE,
+                                      u, CX18_AI1_MUX_MASK);
+        }
+        cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
+                              v, CX18_AI1_MUX_MASK);
         return 0;
 }
diff --git a/drivers/media/video/cx18/cx18-av-core.c b/drivers/media/video/cx18/cx18-av-core.c
index cf2bd888a429..536dedb23ba3 100644
--- a/drivers/media/video/cx18/cx18-av-core.c
+++ b/drivers/media/video/cx18/cx18-av-core.c
@@ -99,9 +99,39 @@ int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask,
                              or_value);
 }
 
-static void cx18_av_initialize(struct cx18 *cx)
+static int cx18_av_init(struct v4l2_subdev *sd, u32 val)
 {
-        struct cx18_av_state *state = &cx->av_state;
+        struct cx18 *cx = v4l2_get_subdevdata(sd);
+
+        /*
+         * The crystal freq used in calculations in this driver will be
+         * 28.636360 MHz.
+         * Aim to run the PLLs' VCOs near 400 MHz to minimze errors.
+         */
+
+        /*
+         * VDCLK  Integer = 0x0f, Post Divider = 0x04
+         * AIMCLK Integer = 0x0e, Post Divider = 0x16
+         */
+        cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f);
+
+        /* VDCLK Fraction = 0x2be2fe */
+        /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */
+        cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe);
+
+        /* AIMCLK Fraction = 0x05227ad */
+        /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/
+        cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad);
+
+        /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
+        cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56);
+        return 0;
+}
+
+static void cx18_av_initialize(struct v4l2_subdev *sd)
+{
+        struct cx18_av_state *state = to_cx18_av_state(sd);
+        struct cx18 *cx = v4l2_get_subdevdata(sd);
         u32 v;
 
         cx18_av_loadfw(cx);
@@ -150,6 +180,26 @@ static void cx18_av_initialize(struct cx18 *cx)
         cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000);
         cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0);
 
+        /*
+         * Disable Video Auto-config of the Analog Front End and Video PLL.
+         *
+         * Since we only use BT.656 pixel mode, which works for both 525 and 625
+         * line systems, it's just easier for us to set registers
+         * 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL),
+         * 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC)
+         * ourselves, than to run around cleaning up after the auto-config.
+         *
+         * (Note: my CX23418 chip doesn't seem to let the ACFG_DIS bit
+         * get set to 1, but OTOH, it doesn't seem to do AFE and VID PLL
+         * autoconfig either.)
+         *
+         * As a default, also turn off Dual mode for ADC2 and set ADC2 to CH3.
+         */
+        cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000);
+
+        /* Setup the Video and and Aux/Audio PLLs */
+        cx18_av_init(sd, 0);
+
         /* set video to auto-detect */
         /* Clear bits 11-12 to enable slow locking mode.  Set autodetect mode */
         /* set the comb notch = 1 */
@@ -176,12 +226,23 @@ static void cx18_av_initialize(struct cx18 *cx)
         /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */
         /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */
 
-        v = cx18_av_read4(cx, CXADEC_AFE_CTRL);
-        v &= 0xFFFBFFFF;            /* turn OFF bit 18 for droop_comp_ch1 */
-        v &= 0xFFFF7FFF;            /* turn OFF bit 9 for clamp_sel_ch1 */
-        v &= 0xFFFFFFFE;            /* turn OFF bit 0 for 12db_ch1 */
-        /* v |= 0x00000001;*/            /* turn ON bit 0 for 12db_ch1 */
-        cx18_av_write4(cx, CXADEC_AFE_CTRL, v);
+        /*
+         * Analog Front End (AFE)
+         * Default to luma on ch1/ADC1, chroma on ch2/ADC2, SIF on ch3/ADC2
+         *  bypass_ch[1-3]     use filter
+         *  droop_comp_ch[1-3] disable
+         *  clamp_en_ch[1-3]   disable
+         *  aud_in_sel         ADC2
+         *  luma_in_sel        ADC1
+         *  chroma_in_sel      ADC2
+         *  clamp_sel_ch[2-3]  midcode
+         *  clamp_sel_ch1      video decoder
+         *  vga_sel_ch3        audio decoder
+         *  vga_sel_ch[1-2]    video decoder
+         *  half_bw_ch[1-3]    disable
+         *  +12db_ch[1-3]      disable
+         */
+        cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00);
 
 /*      if(dwEnable && dw3DCombAvailable) { */
 /*              CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */
@@ -195,50 +256,18 @@ static void cx18_av_initialize(struct cx18 *cx)
 
 static int cx18_av_reset(struct v4l2_subdev *sd, u32 val)
 {
-        struct cx18 *cx = v4l2_get_subdevdata(sd);
-
-        cx18_av_initialize(cx);
-        return 0;
-}
-
-static int cx18_av_init(struct v4l2_subdev *sd, u32 val)
-{
-        struct cx18 *cx = v4l2_get_subdevdata(sd);
-
-        /*
-         * The crystal freq used in calculations in this driver will be
-         * 28.636360 MHz.
-         * Aim to run the PLLs' VCOs near 400 MHz to minimze errors.
-         */
-
-        /*
-         * VDCLK  Integer = 0x0f, Post Divider = 0x04
-         * AIMCLK Integer = 0x0e, Post Divider = 0x16
-         */
-        cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f);
-
-        /* VDCLK Fraction = 0x2be2fe */
-        /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */
-        cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe);
-
-        /* AIMCLK Fraction = 0x05227ad */
-        /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/
-        cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad);
-
-        /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
-        cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56);
+        cx18_av_initialize(sd);
         return 0;
 }
 
 static int cx18_av_load_fw(struct v4l2_subdev *sd)
 {
         struct cx18_av_state *state = to_cx18_av_state(sd);
-        struct cx18 *cx = v4l2_get_subdevdata(sd);
 
         if (!state->is_initialized) {
                 /* initialize on first use */
                 state->is_initialized = 1;
-                cx18_av_initialize(cx);
+                cx18_av_initialize(sd);
         }
         return 0;
 }
@@ -248,8 +277,15 @@ void cx18_av_std_setup(struct cx18 *cx)
         struct cx18_av_state *state = &cx->av_state;
         struct v4l2_subdev *sd = &state->sd;
         v4l2_std_id std = state->std;
+
+        /*
+         * Video ADC crystal clock to pixel clock SRC decimation ratio
+         * 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b
+         */
+        const int src_decimation = 0x21f;
+
         int hblank, hactive, burst, vblank, vactive, sc;
-        int vblank656, src_decimation;
+        int vblank656;
         int luma_lpf, uv_lpf, comb;
         u32 pll_int, pll_frac, pll_post;
 
@@ -259,40 +295,96 @@ void cx18_av_std_setup(struct cx18 *cx)
         else
                 cx18_av_write(cx, 0x49f, 0x14);
 
+        /*
+         * Note: At the end of a field, there are 3 sets of half line duration
+         * (double horizontal rate) pulses:
+         *
+         * 5 (625) or 6 (525) half-lines to blank for the vertical retrace
+         * 5 (625) or 6 (525) vertical sync pulses of half line duration
+         * 5 (625) or 6 (525) half-lines of equalization pulses
+         */
         if (std & V4L2_STD_625_50) {
-                /* FIXME - revisit these for Sliced VBI */
+                /*
+                 * The following relationships of half line counts should hold:
+                 * 625 = vblank656 + vactive
+                 * 10 = vblank656 - vblank = vsync pulses + equalization pulses
+                 *
+                 * vblank656: half lines after line 625/mid-313 of blanked video
+                 * vblank:    half lines, after line 5/317, of blanked video
+                 * vactive:   half lines of active video +
+                 *              5 half lines after the end of active video
+                 *
+                 * As far as I can tell:
+                 * vblank656 starts counting from the falling edge of the first
+                 *      vsync pulse (start of line 1 or mid-313)
+                 * vblank starts counting from the after the 5 vsync pulses and
+                 *      5 or 4 equalization pulses (start of line 6 or 318)
+                 *
+                 * For 625 line systems the driver will extract VBI information
+                 * from lines 6-23 and lines 318-335 (but the slicer can only
+                 * handle 17 lines, not the 18 in the vblank region).
+                 * In addition, we need vblank656 and vblank to be one whole
+                 * line longer, to cover line 24 and 336, so the SAV/EAV RP
+                 * codes get generated such that the encoder can actually
+                 * extract line 23 & 335 (WSS).  We'll lose 1 line in each field
+                 * at the top of the screen.
+                 *
+                 * It appears the 5 half lines that happen after active
+                 * video must be included in vactive (579 instead of 574),
+                 * otherwise the colors get badly displayed in various regions
+                 * of the screen.  I guess the chroma comb filter gets confused
+                 * without them (at least when a PVR-350 is the PAL source).
+                 */
+                vblank656 = 48; /* lines  1 -  24  &  313 - 336 */
+                vblank = 38;    /* lines  6 -  24  &  318 - 336 */
+                vactive = 579;  /* lines 24 - 313  &  337 - 626 */
+
+                /*
+                 * For a 13.5 Mpps clock and 15,625 Hz line rate, a line is
+                 * is 864 pixels = 720 active + 144 blanking.  ITU-R BT.601
+                 * specifies 12 luma clock periods or ~ 0.9 * 13.5 Mpps after
+                 * the end of active video to start a horizontal line, so that
+                 * leaves 132 pixels of hblank to ignore.
+                 */
                 hblank = 132;
                 hactive = 720;
-                burst = 93;
-                vblank = 36;
-                vactive = 580;
-                vblank656 = 40;
-                src_decimation = 0x21f;
 
+                /*
+                 * Burst gate delay (for 625 line systems)
+                 * Hsync leading edge to color burst rise = 5.6 us
+                 * Color burst width = 2.25 us
+                 * Gate width = 4 pixel clocks
+                 * (5.6 us + 2.25/2 us) * 13.5 Mpps + 4/2 clocks = 92.79 clocks
+                 */
+                burst = 93;
                 luma_lpf = 2;
                 if (std & V4L2_STD_PAL) {
                         uv_lpf = 1;
                         comb = 0x20;
-                        sc = 688739;
+                        /* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
+                        sc = 688700;
                 } else if (std == V4L2_STD_PAL_Nc) {
                         uv_lpf = 1;
                         comb = 0x20;
-                        sc = 556453;
+                        /* sc = 3582056.25 * src_decimation/28636360 * 2^13 */
+                        sc = 556422;
                 } else { /* SECAM */
                         uv_lpf = 0;
                         comb = 0;
-                        sc = 672351;
+                        /* (fr + fb)/2 = (4406260 + 4250000)/2 = 4328130 */
+                        /* sc = 4328130 * src_decimation/28636360 * 2^13 */
+                        sc = 672314;
                 }
         } else {
                 /*
                  * The following relationships of half line counts should hold:
-                 * 525 = vsync + vactive + vblank656
-                 * 12 = vblank656 - vblank
+                 * 525 = prevsync + vblank656 + vactive
+                 * 12 = vblank656 - vblank = vsync pulses + equalization pulses
                  *
-                 * vsync:     always 6 half-lines of vsync pulses
-                 * vactive:   half lines of active video
+                 * prevsync:  6 half-lines before the vsync pulses
                  * vblank656: half lines, after line 3/mid-266, of blanked video
                  * vblank:    half lines, after line 9/272, of blanked video
+                 * vactive:   half lines of active video
                  *
                  * As far as I can tell:
                  * vblank656 starts counting from the falling edge of the first
@@ -319,20 +411,30 @@ void cx18_av_std_setup(struct cx18 *cx)
                 luma_lpf = 1;
                 uv_lpf = 1;
 
-                src_decimation = 0x21f;
+                /*
+                 * Burst gate delay (for 525 line systems)
+                 * Hsync leading edge to color burst rise = 5.3 us
+                 * Color burst width = 2.5 us
+                 * Gate width = 4 pixel clocks
+                 * (5.3 us + 2.5/2 us) * 13.5 Mpps + 4/2 clocks = 90.425 clocks
+                 */
                 if (std == V4L2_STD_PAL_60) {
-                        burst = 0x5b;
+                        burst = 90;
                         luma_lpf = 2;
                         comb = 0x20;
-                        sc = 688739;
+                        /* sc = 4433618.75 * src_decimation/28636360 * 2^13 */
+                        sc = 688700;
                 } else if (std == V4L2_STD_PAL_M) {
-                        burst = 0x61;
+                        /* The 97 needs to be verified against PAL-M timings */
+                        burst = 97;
                         comb = 0x20;
-                        sc = 555452;
+                        /* sc = 3575611.49 * src_decimation/28636360 * 2^13 */
+                        sc = 555421;
                 } else {
-                        burst = 0x5b;
+                        burst = 90;
                         comb = 0x66;
-                        sc = 556063;
+                        /* sc = 3579545.45.. * src_decimation/28636360 * 2^13 */
+                        sc = 556032;
                 }
         }
 
@@ -344,23 +446,26 @@ void cx18_av_std_setup(struct cx18 *cx)
                             pll_int, pll_frac, pll_post);
 
         if (pll_post) {
-                int fin, fsc, pll;
+                int fsc, pll;
+                u64 tmp;
 
                 pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
                 pll /= pll_post;
-                CX18_DEBUG_INFO_DEV(sd, "PLL = %d.%06d MHz\n",
+                CX18_DEBUG_INFO_DEV(sd, "Video PLL = %d.%06d MHz\n",
                                     pll / 1000000, pll % 1000000);
-                CX18_DEBUG_INFO_DEV(sd, "PLL/8 = %d.%06d MHz\n",
+                CX18_DEBUG_INFO_DEV(sd, "Pixel rate = %d.%06d Mpixel/sec\n",
                                     pll / 8000000, (pll / 8) % 1000000);
 
-                fin = ((u64)src_decimation * pll) >> 12;
-                CX18_DEBUG_INFO_DEV(sd, "ADC Sampling freq = %d.%06d MHz\n",
-                                    fin / 1000000, fin % 1000000);
+                CX18_DEBUG_INFO_DEV(sd, "ADC XTAL/pixel clock decimation ratio "
+                                    "= %d.%03d\n", src_decimation / 256,
+                                    ((src_decimation % 256) * 1000) / 256);
 
-                fsc = (((u64)sc) * pll) >> 24L;
+                tmp = 28636360 * (u64) sc;
+                do_div(tmp, src_decimation);
+                fsc = tmp >> 13;
                 CX18_DEBUG_INFO_DEV(sd,
-                                    "Chroma sub-carrier freq = %d.%06d MHz\n",
-                                    fsc / 1000000, fsc % 1000000);
+                                    "Chroma sub-carrier initial freq = %d.%06d "
+                                    "MHz\n", fsc / 1000000, fsc % 1000000);
 
                 CX18_DEBUG_INFO_DEV(sd, "hblank %i, hactive %i, vblank %i, "
                                     "vactive %i, vblank656 %i, src_dec %i, "
@@ -470,16 +575,23 @@ static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
 {
         struct cx18_av_state *state = &cx->av_state;
         struct v4l2_subdev *sd = &state->sd;
-        u8 is_composite = (vid_input >= CX18_AV_COMPOSITE1 &&
-                           vid_input <= CX18_AV_COMPOSITE8);
-        u8 reg;
-        u8 v;
+
+        enum analog_signal_type {
+                NONE, CVBS, Y, C, SIF, Pb, Pr
+        } ch[3] = {NONE, NONE, NONE};
+
+        u8 afe_mux_cfg;
+        u8 adc2_cfg;
+        u32 afe_cfg;
+        int i;
 
         CX18_DEBUG_INFO_DEV(sd, "decoder set video input %d, audio input %d\n",
                             vid_input, aud_input);
 
-        if (is_composite) {
-                reg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1);
+        if (vid_input >= CX18_AV_COMPOSITE1 &&
+            vid_input <= CX18_AV_COMPOSITE8) {
+                afe_mux_cfg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1);
+                ch[0] = CVBS;
         } else {
                 int luma = vid_input & 0xf0;
                 int chroma = vid_input & 0xf00;
@@ -493,26 +605,45 @@ static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
                                      vid_input);
                         return -EINVAL;
                 }
-                reg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4);
+                afe_mux_cfg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4);
+                ch[0] = Y;
                 if (chroma >= CX18_AV_SVIDEO_CHROMA7) {
-                        reg &= 0x3f;
-                        reg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2;
+                        afe_mux_cfg &= 0x3f;
+                        afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2;
+                        ch[2] = C;
                 } else {
-                        reg &= 0xcf;
-                        reg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4;
+                        afe_mux_cfg &= 0xcf;
+                        afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4;
+                        ch[1] = C;
                 }
         }
+        /* TODO: LeadTek WinFast DVR3100 H & WinFast PVR2100 can do Y/Pb/Pr */
 
         switch (aud_input) {
         case CX18_AV_AUDIO_SERIAL1:
         case CX18_AV_AUDIO_SERIAL2:
                 /* do nothing, use serial audio input */
                 break;
-        case CX18_AV_AUDIO4: reg &= ~0x30; break;
-        case CX18_AV_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
-        case CX18_AV_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
-        case CX18_AV_AUDIO7: reg &= ~0xc0; break;
-        case CX18_AV_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
+        case CX18_AV_AUDIO4:
+                afe_mux_cfg &= ~0x30;
+                ch[1] = SIF;
+                break;
+        case CX18_AV_AUDIO5:
+                afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x10;
+                ch[1] = SIF;
+                break;
+        case CX18_AV_AUDIO6:
+                afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x20;
+                ch[1] = SIF;
+                break;
+        case CX18_AV_AUDIO7:
+                afe_mux_cfg &= ~0xc0;
+                ch[2] = SIF;
+                break;
+        case CX18_AV_AUDIO8:
+                afe_mux_cfg = (afe_mux_cfg & ~0xc0) | 0x40;
+                ch[2] = SIF;
+                break;
 
         default:
                 CX18_ERR_DEV(sd, "0x%04x is not a valid audio input!\n",
@@ -520,24 +651,65 @@ static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input,
                 return -EINVAL;
         }
 
-        cx18_av_write_expect(cx, 0x103, reg, reg, 0xf7);
+        /* Set up analog front end multiplexers */
+        cx18_av_write_expect(cx, 0x103, afe_mux_cfg, afe_mux_cfg, 0xf7);
         /* Set INPUT_MODE to Composite (0) or S-Video (1) */
-        cx18_av_and_or(cx, 0x401, ~0x6, is_composite ? 0 : 0x02);
+        cx18_av_and_or(cx, 0x401, ~0x6, ch[0] == CVBS ? 0 : 0x02);
 
         /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
-        v = cx18_av_read(cx, 0x102);
-        if (reg & 0x80)
-                v &= ~0x2;
+        adc2_cfg = cx18_av_read(cx, 0x102);
+        if (ch[2] == NONE)
+                adc2_cfg &= ~0x2; /* No sig on CH3, set ADC2 to CH2 for input */
         else
-                v |= 0x2;
+                adc2_cfg |= 0x2;  /* Signal on CH3, set ADC2 to CH3 for input */
+
         /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */
-        if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
-                v |= 0x4;
+        if (ch[1] != NONE && ch[2] != NONE)
+                adc2_cfg |= 0x4; /* Set dual mode */
         else
-                v &= ~0x4;
-        cx18_av_write_expect(cx, 0x102, v, v, 0x17);
+                adc2_cfg &= ~0x4; /* Clear dual mode */
+        cx18_av_write_expect(cx, 0x102, adc2_cfg, adc2_cfg, 0x17);
+
+        /* Configure the analog front end */
+        afe_cfg = cx18_av_read4(cx, CXADEC_AFE_CTRL);
+        afe_cfg &= 0xff000000;
+        afe_cfg |= 0x00005000; /* CHROMA_IN, AUD_IN: ADC2; LUMA_IN: ADC1 */
+        if (ch[1] != NONE && ch[2] != NONE)
+                afe_cfg |= 0x00000030; /* half_bw_ch[2-3] since in dual mode */
+
+        for (i = 0; i < 3; i++) {
+                switch (ch[i]) {
+                default:
+                case NONE:
+                        /* CLAMP_SEL = Fixed to midcode clamp level */
+                        afe_cfg |= (0x00000200 << i);
+                        break;
+                case CVBS:
+                case Y:
+                        if (i > 0)
+                                afe_cfg |= 0x00002000; /* LUMA_IN_SEL: ADC2 */
+                        break;
+                case C:
+                case Pb:
+                case Pr:
+                        /* CLAMP_SEL = Fixed to midcode clamp level */
+                        afe_cfg |= (0x00000200 << i);
+                        if (i == 0 && ch[i] == C)
+                                afe_cfg &= ~0x00001000; /* CHROMA_IN_SEL ADC1 */
+                        break;
+                case SIF:
+                        /*
+                         * VGA_GAIN_SEL = Audio Decoder
+                         * CLAMP_SEL = Fixed to midcode clamp level
+                         */
+                        afe_cfg |= (0x00000240 << i);
+                        if (i == 0)
+                                afe_cfg &= ~0x00004000; /* AUD_IN_SEL ADC1 */
+                        break;
+                }
+        }
 
-        /*cx18_av_and_or4(cx, 0x104, ~0x001b4180, 0x00004180);*/
+        cx18_av_write4(cx, CXADEC_AFE_CTRL, afe_cfg);
 
         state->vid_input = vid_input;
         state->aud_input = aud_input;
@@ -858,9 +1030,9 @@ static int cx18_av_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
                  * cx18_av_std_setup(), above standard values:
                  *
                  * 480 + 1 for 60 Hz systems
-                 * 576 + 4 for 50 Hz systems
+                 * 576 + 3 for 50 Hz systems
                  */
-                Vlines = pix->height + (is_50Hz ? 4 : 1);
+                Vlines = pix->height + (is_50Hz ? 3 : 1);
 
                 /*
                  * Invalid height and width scaling requests are:
diff --git a/drivers/media/video/cx18/cx18-av-firmware.c b/drivers/media/video/cx18/cx18-av-firmware.c
index 49a55cc8d839..b9e8cc5d264a 100644
--- a/drivers/media/video/cx18/cx18-av-firmware.c
+++ b/drivers/media/video/cx18/cx18-av-firmware.c
@@ -24,15 +24,63 @@
 #include "cx18-io.h"
 #include <linux/firmware.h>
 
-#define CX18_AUDIO_ENABLE 0xc72014
+#define CX18_AUDIO_ENABLE    0xc72014
+#define CX18_AI1_MUX_MASK    0x30
+#define CX18_AI1_MUX_I2S1    0x00
+#define CX18_AI1_MUX_I2S2    0x10
+#define CX18_AI1_MUX_843_I2S 0x20
+#define CX18_AI1_MUX_INVALID 0x30
+
 #define FWFILE "v4l-cx23418-dig.fw"
 
+static int cx18_av_verifyfw(struct cx18 *cx, const struct firmware *fw)
+{
+        struct v4l2_subdev *sd = &cx->av_state.sd;
+        int ret = 0;
+        const u8 *data;
+        u32 size;
+        int addr;
+        u32 expected, dl_control;
+
+        /* Ensure we put the 8051 in reset and enable firmware upload mode */
+        dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
+        do {
+                dl_control &= 0x00ffffff;
+                dl_control |= 0x0f000000;
+                cx18_av_write4_noretry(cx, CXADEC_DL_CTL, dl_control);
+                dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
+        } while ((dl_control & 0xff000000) != 0x0f000000);
+
+        /* Read and auto increment until at address 0x0000 */
+        while (dl_control & 0x3fff)
+                dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
+
+        data = fw->data;
+        size = fw->size;
+        for (addr = 0; addr < size; addr++) {
+                dl_control &= 0xffff3fff; /* ignore top 2 bits of address */
+                expected = 0x0f000000 | ((u32)data[addr] << 16) | addr;
+                if (expected != dl_control) {
+                        CX18_ERR_DEV(sd, "verification of %s firmware load "
+                                     "failed: expected %#010x got %#010x\n",
+                                     FWFILE, expected, dl_control);
+                        ret = -EIO;
+                        break;
+                }
+                dl_control = cx18_av_read4(cx, CXADEC_DL_CTL);
+        }
+        if (ret == 0)
+                CX18_INFO_DEV(sd, "verified load of %s firmware (%d bytes)\n",
+                              FWFILE, size);
+        return ret;
+}
+
 int cx18_av_loadfw(struct cx18 *cx)
 {
         struct v4l2_subdev *sd = &cx->av_state.sd;
         const struct firmware *fw = NULL;
         u32 size;
-        u32 v;
+        u32 u, v;
         const u8 *ptr;
         int i;
         int retries1 = 0;
@@ -95,6 +143,12 @@ int cx18_av_loadfw(struct cx18 *cx)
         }
 
         cx18_av_write4_expect(cx, CXADEC_DL_CTL,
+                                0x03000000 | fw->size, 0x03000000, 0x13000000);
+
+        CX18_INFO_DEV(sd, "loaded %s firmware (%d bytes)\n", FWFILE, size);
+
+        if (cx18_av_verifyfw(cx, fw) == 0)
+                cx18_av_write4_expect(cx, CXADEC_DL_CTL,
                                 0x13000000 | fw->size, 0x13000000, 0x13000000);
 
         /* Output to the 416 */
@@ -135,6 +189,28 @@ int cx18_av_loadfw(struct cx18 *cx)
                 cx18_write_reg_expect(cx, v & 0xFFFFFBFF, CX18_AUDIO_ENABLE,
                                       0, 0x400);
 
+        /* Toggle the AI1 MUX */
+        v = cx18_read_reg(cx, CX18_AUDIO_ENABLE);
+        u = v & CX18_AI1_MUX_MASK;
+        v &= ~CX18_AI1_MUX_MASK;
+        if (u == CX18_AI1_MUX_843_I2S || u == CX18_AI1_MUX_INVALID) {
+                /* Switch to I2S1 */
+                v |= CX18_AI1_MUX_I2S1;
+                cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
+                                      v, CX18_AI1_MUX_MASK);
+                /* Switch back to the A/V decoder core I2S output */
+                v = (v & ~CX18_AI1_MUX_MASK) | CX18_AI1_MUX_843_I2S;
+        } else {
+                /* Switch to the A/V decoder core I2S output */
+                v |= CX18_AI1_MUX_843_I2S;
+                cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
+                                      v, CX18_AI1_MUX_MASK);
+                /* Switch back to I2S1 or I2S2 */
+                v = (v & ~CX18_AI1_MUX_MASK) | u;
+        }
+        cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE,
+                              v, CX18_AI1_MUX_MASK);
+
         /* Enable WW auto audio standard detection */
         v = cx18_av_read4(cx, CXADEC_STD_DET_CTL);
         v |= 0xFF;   /* Auto by default */
@@ -143,7 +219,5 @@ int cx18_av_loadfw(struct cx18 *cx)
         cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, v, v, 0x3F00FFFF);
 
         release_firmware(fw);
-
-        CX18_INFO_DEV(sd, "loaded %s firmware (%d bytes)\n", FWFILE, size);
         return 0;
 }
diff --git a/drivers/media/video/cx18/cx18-av-vbi.c b/drivers/media/video/cx18/cx18-av-vbi.c
index 23b31670bf1d..a51732bcca4b 100644
--- a/drivers/media/video/cx18/cx18-av-vbi.c
+++ b/drivers/media/video/cx18/cx18-av-vbi.c
@@ -255,8 +255,8 @@ int cx18_av_vbi_s_fmt(struct cx18 *cx, struct v4l2_format *fmt)
         }
 
         cx18_av_write(cx, 0x43c, 0x16);
-        /* FIXME - should match vblank set in cx18_av_std_setup() */
-        cx18_av_write(cx, 0x474, is_pal ? 0x2a : 26);
+        /* Should match vblank set in cx18_av_std_setup() */
+        cx18_av_write(cx, 0x474, is_pal ? 38 : 26);
         return 0;
 }
 
diff --git a/drivers/media/video/cx18/cx18-cards.c b/drivers/media/video/cx18/cx18-cards.c
index 9bc221837847..c92a25036f0e 100644
--- a/drivers/media/video/cx18/cx18-cards.c
+++ b/drivers/media/video/cx18/cx18-cards.c
@@ -340,13 +340,12 @@ static const struct cx18_card cx18_card_toshiba_qosmio_dvbt = {
 
 static const struct cx18_card_pci_info cx18_pci_leadtek_pvr2100[] = {
         { PCI_DEVICE_ID_CX23418, CX18_PCI_ID_LEADTEK, 0x6f27 }, /* PVR2100   */
-        { PCI_DEVICE_ID_CX23418, CX18_PCI_ID_LEADTEK, 0x6690 }, /* DVR3100 H */
         { 0, 0, 0 }
 };
 
 static const struct cx18_card cx18_card_leadtek_pvr2100 = {
         .type = CX18_CARD_LEADTEK_PVR2100,
-        .name = "Leadtek WinFast PVR2100/DVR3100 H",
+        .name = "Leadtek WinFast PVR2100",
         .comment = "Experimenters and photos needed for device to work well.\n"
                   "\tTo help, mail the ivtv-devel list (www.ivtvdriver.org).\n",
         .v4l2_capabilities = CX18_CAP_ENCODER,
@@ -365,15 +364,12 @@ static const struct cx18_card cx18_card_leadtek_pvr2100 = {
                 { CX18_CARD_INPUT_LINE_IN1,  CX18_AV_AUDIO_SERIAL1, 1 },
         },
         .tuners = {
-                /* XC3028 tuner */
+                /* XC2028 tuner */
                 { .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
         },
         .radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 2 },
         .ddr = {
-                /*
-                 * Pointer to proper DDR config values provided by
-                 * Terry Wu <terrywu at leadtek.com.tw>
-                 */
+                /* Pointer to proper DDR config values provided by Terry Wu */
                 .chip_config = 0x303,
                 .refresh = 0x3bb,
                 .timing1 = 0x24220e83,
@@ -392,6 +388,58 @@ static const struct cx18_card cx18_card_leadtek_pvr2100 = {
 
 /* ------------------------------------------------------------------------- */
 
+/* Leadtek WinFast DVR3100 H */
+
+static const struct cx18_card_pci_info cx18_pci_leadtek_dvr3100h[] = {
+        { PCI_DEVICE_ID_CX23418, CX18_PCI_ID_LEADTEK, 0x6690 }, /* DVR3100 H */
+        { 0, 0, 0 }
+};
+
+static const struct cx18_card cx18_card_leadtek_dvr3100h = {
+        .type = CX18_CARD_LEADTEK_DVR3100H,
+        .name = "Leadtek WinFast DVR3100 H",
+        .comment = "Simultaneous DVB-T and Analog capture supported,\n"
+                  "\texcept when capturing Analog from the antenna input.\n",
+        .v4l2_capabilities = CX18_CAP_ENCODER,
+        .hw_audio_ctrl = CX18_HW_418_AV,
+        .hw_muxer = CX18_HW_GPIO_MUX,
+        .hw_all = CX18_HW_418_AV | CX18_HW_TUNER | CX18_HW_GPIO_MUX |
+                  CX18_HW_DVB | CX18_HW_GPIO_RESET_CTRL,
+        .video_inputs = {
+                { CX18_CARD_INPUT_VID_TUNER,  0, CX18_AV_COMPOSITE2 },
+                { CX18_CARD_INPUT_SVIDEO1,    1,
+                        CX18_AV_SVIDEO_LUMA3 | CX18_AV_SVIDEO_CHROMA4 },
+                { CX18_CARD_INPUT_COMPOSITE1, 1, CX18_AV_COMPOSITE7 },
+        },
+        .audio_inputs = {
+                { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5,        0 },
+                { CX18_CARD_INPUT_LINE_IN1,  CX18_AV_AUDIO_SERIAL1, 1 },
+        },
+        .tuners = {
+                /* XC3028 tuner */
+                { .std = V4L2_STD_ALL, .tuner = TUNER_XC2028 },
+        },
+        .radio_input = { CX18_CARD_INPUT_AUD_TUNER, CX18_AV_AUDIO5, 2 },
+        .ddr = {
+                /* Pointer to proper DDR config values provided by Terry Wu */
+                .chip_config = 0x303,
+                .refresh = 0x3bb,
+                .timing1 = 0x24220e83,
+                .timing2 = 0x1f,
+                .tune_lane = 0,
+                .initial_emrs = 0x2,
+        },
+        .gpio_init.initial_value = 0x6,
+        .gpio_init.direction = 0x7,
+        .gpio_audio_input = { .mask   = 0x7,
+                              .tuner  = 0x6, .linein = 0x2, .radio  = 0x2 },
+        .xceive_pin = 1,
+        .pci_list = cx18_pci_leadtek_dvr3100h,
+        .i2c = &cx18_i2c_std,
+};
+
+/* ------------------------------------------------------------------------- */
+
 static const struct cx18_card *cx18_card_list[] = {
         &cx18_card_hvr1600_esmt,
         &cx18_card_hvr1600_samsung,
@@ -400,6 +448,7 @@ static const struct cx18_card *cx18_card_list[] = {
         &cx18_card_cnxt_raptor_pal,
         &cx18_card_toshiba_qosmio_dvbt,
         &cx18_card_leadtek_pvr2100,
+        &cx18_card_leadtek_dvr3100h,
 };
 
 const struct cx18_card *cx18_get_card(u16 index)
diff --git a/drivers/media/video/cx18/cx18-controls.c b/drivers/media/video/cx18/cx18-controls.c
index 82fc2f9d4021..8e35c3aed544 100644
--- a/drivers/media/video/cx18/cx18-controls.c
+++ b/drivers/media/video/cx18/cx18-controls.c
@@ -176,8 +176,10 @@ static int cx18_setup_vbi_fmt(struct cx18 *cx,
                 return -EBUSY;
 
         if (fmt != V4L2_MPEG_STREAM_VBI_FMT_IVTV ||
-            type != V4L2_MPEG_STREAM_TYPE_MPEG2_PS) {
-                /* We don't do VBI insertion aside from IVTV format in a PS */
+            !(type == V4L2_MPEG_STREAM_TYPE_MPEG2_PS ||
+              type == V4L2_MPEG_STREAM_TYPE_MPEG2_DVD ||
+              type == V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD)) {
+                /* Only IVTV fmt VBI insertion & only MPEG-2 PS type streams */
                 cx->vbi.insert_mpeg = V4L2_MPEG_STREAM_VBI_FMT_NONE;
                 CX18_DEBUG_INFO("disabled insertion of sliced VBI data into "
                                 "the MPEG stream\n");
diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c
index 49b1c3d7b1a8..92026e82e10e 100644
--- a/drivers/media/video/cx18/cx18-driver.c
+++ b/drivers/media/video/cx18/cx18-driver.c
@@ -30,6 +30,7 @@
 #include "cx18-irq.h"
 #include "cx18-gpio.h"
 #include "cx18-firmware.h"
+#include "cx18-queue.h"
 #include "cx18-streams.h"
 #include "cx18-av-core.h"
 #include "cx18-scb.h"
@@ -151,7 +152,8 @@ MODULE_PARM_DESC(cardtype,
                  "\t\t\t 4 = Yuan MPC718\n"
                  "\t\t\t 5 = Conexant Raptor PAL/SECAM\n"
                  "\t\t\t 6 = Toshiba Qosmio DVB-T/Analog\n"
-                 "\t\t\t 7 = Leadtek WinFast PVR2100/DVR3100 H\n"
+                 "\t\t\t 7 = Leadtek WinFast PVR2100\n"
+                 "\t\t\t 8 = Leadtek WinFast DVR3100 H\n"
                  "\t\t\t 0 = Autodetect (default)\n"
                  "\t\t\t-1 = Ignore this card\n\t\t");
 MODULE_PARM_DESC(pal, "Set PAL standard: B, G, H, D, K, I, M, N, Nc, 60");
@@ -312,7 +314,7 @@ static void cx18_process_eeprom(struct cx18 *cx)
         CX18_INFO("Autodetected %s\n", cx->card_name);
 
         if (tv.tuner_type == TUNER_ABSENT)
-                CX18_ERR("tveeprom cannot autodetect tuner!");
+                CX18_ERR("tveeprom cannot autodetect tuner!\n");
 
         if (cx->options.tuner == -1)
                 cx->options.tuner = tv.tuner_type;
@@ -546,6 +548,40 @@ done:
         cx->card_i2c = cx->card->i2c;
 }
 
+static int __devinit cx18_create_in_workq(struct cx18 *cx)
+{
+        snprintf(cx->in_workq_name, sizeof(cx->in_workq_name), "%s-in",
+                 cx->v4l2_dev.name);
+        cx->in_work_queue = create_singlethread_workqueue(cx->in_workq_name);
+        if (cx->in_work_queue == NULL) {
+                CX18_ERR("Unable to create incoming mailbox handler thread\n");
+                return -ENOMEM;
+        }
+        return 0;
+}
+
+static int __devinit cx18_create_out_workq(struct cx18 *cx)
+{
+        snprintf(cx->out_workq_name, sizeof(cx->out_workq_name), "%s-out",
+                 cx->v4l2_dev.name);
+        cx->out_work_queue = create_workqueue(cx->out_workq_name);
+        if (cx->out_work_queue == NULL) {
+                CX18_ERR("Unable to create outgoing mailbox handler threads\n");
+                return -ENOMEM;
+        }
+        return 0;
+}
+
+static void __devinit cx18_init_in_work_orders(struct cx18 *cx)
+{
+        int i;
+        for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) {
+                cx->in_work_order[i].cx = cx;
+                cx->in_work_order[i].str = cx->epu_debug_str;
+                INIT_WORK(&cx->in_work_order[i].work, cx18_in_work_handler);
+        }
+}
+
 /* Precondition: the cx18 structure has been memset to 0. Only
    the dev and instance fields have been filled in.
    No assumptions on the card type may be made here (see cx18_init_struct2
@@ -553,7 +589,7 @@ done:
  */
 static int __devinit cx18_init_struct1(struct cx18 *cx)
 {
-        int i;
+        int ret;
 
         cx->base_addr = pci_resource_start(cx->pci_dev, 0);
 
@@ -562,18 +598,18 @@ static int __devinit cx18_init_struct1(struct cx18 *cx)
         mutex_init(&cx->epu2apu_mb_lock);
         mutex_init(&cx->epu2cpu_mb_lock);
 
-        cx->work_queue = create_singlethread_workqueue(cx->v4l2_dev.name);
-        if (cx->work_queue == NULL) {
-                CX18_ERR("Unable to create work hander thread\n");
-                return -ENOMEM;
-        }
+        ret = cx18_create_out_workq(cx);
+        if (ret)
+                return ret;
 
-        for (i = 0; i < CX18_MAX_EPU_WORK_ORDERS; i++) {
-                cx->epu_work_order[i].cx = cx;
-                cx->epu_work_order[i].str = cx->epu_debug_str;
-                INIT_WORK(&cx->epu_work_order[i].work, cx18_epu_work_handler);
+        ret = cx18_create_in_workq(cx);
+        if (ret) {
+                destroy_workqueue(cx->out_work_queue);
+                return ret;
         }
 
+        cx18_init_in_work_orders(cx);
+
         /* start counting open_id at 1 */
         cx->open_id = 1;
 
@@ -759,17 +795,17 @@ static int __devinit cx18_probe(struct pci_dev *pci_dev,
                 retval = -ENODEV;
                 goto err;
         }
-        if (cx18_init_struct1(cx)) {
-                retval = -ENOMEM;
+
+        retval = cx18_init_struct1(cx);
+        if (retval)
                 goto err;
-        }
 
         CX18_DEBUG_INFO("base addr: 0x%08x\n", cx->base_addr);
 
         /* PCI Device Setup */
         retval = cx18_setup_pci(cx, pci_dev, pci_id);
         if (retval != 0)
-                goto free_workqueue;
+                goto free_workqueues;
 
         /* map io memory */
         CX18_DEBUG_INFO("attempting ioremap at 0x%08x len 0x%08x\n",
@@ -943,8 +979,9 @@ free_map:
         cx18_iounmap(cx);
 free_mem:
         release_mem_region(cx->base_addr, CX18_MEM_SIZE);
-free_workqueue:
-        destroy_workqueue(cx->work_queue);
+free_workqueues:
+        destroy_workqueue(cx->in_work_queue);
+        destroy_workqueue(cx->out_work_queue);
 err:
         if (retval == 0)
                 retval = -ENODEV;
@@ -1053,11 +1090,19 @@ int cx18_init_on_first_open(struct cx18 *cx)
         return 0;
 }
 
-static void cx18_cancel_epu_work_orders(struct cx18 *cx)
+static void cx18_cancel_in_work_orders(struct cx18 *cx)
 {
         int i;
-        for (i = 0; i < CX18_MAX_EPU_WORK_ORDERS; i++)
-                cancel_work_sync(&cx->epu_work_order[i].work);
+        for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++)
+                cancel_work_sync(&cx->in_work_order[i].work);
+}
+
+static void cx18_cancel_out_work_orders(struct cx18 *cx)
+{
+        int i;
+        for (i = 0; i < CX18_MAX_STREAMS; i++)
+                if (&cx->streams[i].video_dev != NULL)
+                        cancel_work_sync(&cx->streams[i].out_work_order);
 }
 
 static void cx18_remove(struct pci_dev *pci_dev)
@@ -1073,15 +1118,20 @@ static void cx18_remove(struct pci_dev *pci_dev)
         if (atomic_read(&cx->tot_capturing) > 0)
                 cx18_stop_all_captures(cx);
 
-        /* Interrupts */
+        /* Stop interrupts that cause incoming work to be queued */
         cx18_sw1_irq_disable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
+
+        /* Incoming work can cause outgoing work, so clean up incoming first */
+        cx18_cancel_in_work_orders(cx);
+        cx18_cancel_out_work_orders(cx);
+
+        /* Stop ack interrupts that may have been needed for work to finish */
         cx18_sw2_irq_disable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
 
         cx18_halt_firmware(cx);
 
-        cx18_cancel_epu_work_orders(cx);
-
-        destroy_workqueue(cx->work_queue);
+        destroy_workqueue(cx->in_work_queue);
+        destroy_workqueue(cx->out_work_queue);
 
         cx18_streams_cleanup(cx, 1);
 
diff --git a/drivers/media/video/cx18/cx18-driver.h b/drivers/media/video/cx18/cx18-driver.h
index ece4f281ef42..c6a1e907f63a 100644
--- a/drivers/media/video/cx18/cx18-driver.h
+++ b/drivers/media/video/cx18/cx18-driver.h
@@ -80,8 +80,9 @@
 #define CX18_CARD_YUAN_MPC718         3 /* Yuan MPC718 */
 #define CX18_CARD_CNXT_RAPTOR_PAL     4 /* Conexant Raptor PAL */
 #define CX18_CARD_TOSHIBA_QOSMIO_DVBT 5 /* Toshiba Qosmio Interal DVB-T/Analog*/
-#define CX18_CARD_LEADTEK_PVR2100     6 /* Leadtek WinFast PVR2100/DVR3100 H */
-#define CX18_CARD_LAST                6
+#define CX18_CARD_LEADTEK_PVR2100     6 /* Leadtek WinFast PVR2100 */
+#define CX18_CARD_LEADTEK_DVR3100H    7 /* Leadtek WinFast DVR3100 H */
+#define CX18_CARD_LAST                7
 
 #define CX18_ENC_STREAM_TYPE_MPG  0
 #define CX18_ENC_STREAM_TYPE_TS   1
@@ -254,6 +255,7 @@ struct cx18_options {
 #define CX18_F_S_INTERNAL_USE   5       /* this stream is used internally (sliced VBI processing) */
 #define CX18_F_S_STREAMOFF      7       /* signal end of stream EOS */
 #define CX18_F_S_APPL_IO        8       /* this stream is used read/written by an application */
+#define CX18_F_S_STOPPING       9       /* telling the fw to stop capturing */
 
 /* per-cx18, i_flags */
 #define CX18_F_I_LOADED_FW              0       /* Loaded firmware 1st time */
@@ -285,6 +287,7 @@ struct cx18_queue {
         struct list_head list;
         atomic_t buffers;
         u32 bytesused;
+        spinlock_t lock;
 };
 
 struct cx18_dvb {
@@ -305,7 +308,7 @@ struct cx18_scb; /* forward reference */
 
 
 #define CX18_MAX_MDL_ACKS 2
-#define CX18_MAX_EPU_WORK_ORDERS (CX18_MAX_FW_MDLS_PER_STREAM + 7)
+#define CX18_MAX_IN_WORK_ORDERS (CX18_MAX_FW_MDLS_PER_STREAM + 7)
 /* CPU_DE_RELEASE_MDL can burst CX18_MAX_FW_MDLS_PER_STREAM orders in a group */
 
 #define CX18_F_EWO_MB_STALE_UPON_RECEIPT 0x1
@@ -313,7 +316,7 @@ struct cx18_scb; /* forward reference */
 #define CX18_F_EWO_MB_STALE \
              (CX18_F_EWO_MB_STALE_UPON_RECEIPT | CX18_F_EWO_MB_STALE_WHILE_PROC)
 
-struct cx18_epu_work_order {
+struct cx18_in_work_order {
         struct work_struct work;
         atomic_t pending;
         struct cx18 *cx;
@@ -337,7 +340,6 @@ struct cx18_stream {
         unsigned mdl_offset;
 
         u32 id;
-        struct mutex qlock;     /* locks access to the queues */
         unsigned long s_flags;  /* status flags, see above */
         int dma;                /* can be PCI_DMA_TODEVICE,
                                    PCI_DMA_FROMDEVICE or
@@ -353,6 +355,8 @@ struct cx18_stream {
         struct cx18_queue q_busy;       /* busy buffers - in use by firmware */
         struct cx18_queue q_full;       /* full buffers - data for user apps */
 
+        struct work_struct out_work_order;
+
         /* DVB / Digital Transport */
         struct cx18_dvb dvb;
 };
@@ -568,10 +572,14 @@ struct cx18 {
         u32 sw2_irq_mask;
         u32 hw2_irq_mask;
 
-        struct workqueue_struct *work_queue;
-        struct cx18_epu_work_order epu_work_order[CX18_MAX_EPU_WORK_ORDERS];
+        struct workqueue_struct *in_work_queue;
+        char in_workq_name[11]; /* "cx18-NN-in" */
+        struct cx18_in_work_order in_work_order[CX18_MAX_IN_WORK_ORDERS];
         char epu_debug_str[256]; /* CX18_EPU_DEBUG is rare: use shared space */
 
+        struct workqueue_struct *out_work_queue;
+        char out_workq_name[12]; /* "cx18-NN-out" */
+
         /* i2c */
         struct i2c_adapter i2c_adap[2];
         struct i2c_algo_bit_data i2c_algo[2];
diff --git a/drivers/media/video/cx18/cx18-dvb.c b/drivers/media/video/cx18/cx18-dvb.c
index 3b86f57cd15a..6ea3fe623ef4 100644
--- a/drivers/media/video/cx18/cx18-dvb.c
+++ b/drivers/media/video/cx18/cx18-dvb.c
@@ -23,14 +23,20 @@
 #include "cx18-version.h"
 #include "cx18-dvb.h"
 #include "cx18-io.h"
+#include "cx18-queue.h"
 #include "cx18-streams.h"
 #include "cx18-cards.h"
+#include "cx18-gpio.h"
 #include "s5h1409.h"
 #include "mxl5005s.h"
+#include "zl10353.h"
+#include "tuner-xc2028.h"
 
 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
 
 #define CX18_REG_DMUX_NUM_PORT_0_CONTROL 0xd5a000
+#define CX18_CLOCK_ENABLE2               0xc71024
+#define CX18_DMUX_CLK_MASK               0x0080
 
 static struct mxl5005s_config hauppauge_hvr1600_tuner = {
         .i2c_address     = 0xC6 >> 1,
@@ -57,7 +63,15 @@ static struct s5h1409_config hauppauge_hvr1600_config = {
         .inversion     = S5H1409_INVERSION_OFF,
         .status_mode   = S5H1409_DEMODLOCKING,
         .mpeg_timing   = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK
+};
 
+/* Information/confirmation of proper config values provided by Terry Wu */
+static struct zl10353_config leadtek_dvr3100h_demod = {
+        .demod_address         = 0x1e >> 1, /* Datasheet suggested straps */
+        .if2                   = 45600,     /* 4.560 MHz IF from the XC3028 */
+        .parallel_ts           = 1,         /* Not a serial TS */
+        .no_tuner              = 1,         /* XC3028 is not behind the gate */
+        .disable_i2c_gate_ctrl = 1,         /* Disable the I2C gate */
 };
 
 static int dvb_register(struct cx18_stream *stream);
@@ -98,6 +112,7 @@ static int cx18_dvb_start_feed(struct dvb_demux_feed *feed)
                 cx18_write_reg(cx, v, CX18_REG_DMUX_NUM_PORT_0_CONTROL);
                 break;
 
+        case CX18_CARD_LEADTEK_DVR3100H:
         default:
                 /* Assumption - Parallel transport - Signalling
                  * undefined or default.
@@ -267,8 +282,7 @@ void cx18_dvb_unregister(struct cx18_stream *stream)
 }
 
 /* All the DVB attach calls go here, this function get's modified
- * for each new card. No other function in this file needs
- * to change.
+ * for each new card. cx18_dvb_start_feed() will also need changes.
  */
 static int dvb_register(struct cx18_stream *stream)
 {
@@ -289,6 +303,29 @@ static int dvb_register(struct cx18_stream *stream)
                         ret = 0;
                 }
                 break;
+        case CX18_CARD_LEADTEK_DVR3100H:
+                dvb->fe = dvb_attach(zl10353_attach,
+                                     &leadtek_dvr3100h_demod,
+                                     &cx->i2c_adap[1]);
+                if (dvb->fe != NULL) {
+                        struct dvb_frontend *fe;
+                        struct xc2028_config cfg = {
+                                .i2c_adap = &cx->i2c_adap[1],
+                                .i2c_addr = 0xc2 >> 1,
+                                .ctrl = NULL,
+                        };
+                        static struct xc2028_ctrl ctrl = {
+                                .fname   = XC2028_DEFAULT_FIRMWARE,
+                                .max_len = 64,
+                                .demod   = XC3028_FE_ZARLINK456,
+                                .type    = XC2028_AUTO,
+                        };
+
+                        fe = dvb_attach(xc2028_attach, dvb->fe, &cfg);
+                        if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
+                                fe->ops.tuner_ops.set_config(fe, &ctrl);
+                }
+                break;
         default:
                 /* No Digital Tv Support */
                 break;
@@ -299,6 +336,8 @@ static int dvb_register(struct cx18_stream *stream)
                 return -1;
         }
 
+        dvb->fe->callback = cx18_reset_tuner_gpio;
+
         ret = dvb_register_frontend(&dvb->dvb_adapter, dvb->fe);
         if (ret < 0) {
                 if (dvb->fe->ops.release)
@@ -306,5 +345,16 @@ static int dvb_register(struct cx18_stream *stream)
                 return ret;
         }
 
+        /*
+         * The firmware seems to enable the TS DMUX clock
+         * under various circumstances.  However, since we know we
+         * might use it, let's just turn it on ourselves here.
+         */
+        cx18_write_reg_expect(cx,
+                              (CX18_DMUX_CLK_MASK << 16) | CX18_DMUX_CLK_MASK,
+                              CX18_CLOCK_ENABLE2,
+                              CX18_DMUX_CLK_MASK,
+                              (CX18_DMUX_CLK_MASK << 16) | CX18_DMUX_CLK_MASK);
+
         return ret;
 }
diff --git a/drivers/media/video/cx18/cx18-fileops.c b/drivers/media/video/cx18/cx18-fileops.c
index b3889c0b2697..29969c18949c 100644
--- a/drivers/media/video/cx18/cx18-fileops.c
+++ b/drivers/media/video/cx18/cx18-fileops.c
@@ -265,8 +265,13 @@ static size_t cx18_copy_buf_to_user(struct cx18_stream *s,
                  * an MPEG-2 Program Pack start code, and provide only
                  * up to that point to the user, so it's easy to insert VBI data
                  * the next time around.
+                 *
+                 * This will not work for an MPEG-2 TS and has only been
+                 * verified by analysis to work for an MPEG-2 PS.  Helen Buus
+                 * pointed out this works for the CX23416 MPEG-2 DVD compatible
+                 * stream, and research indicates both the MPEG 2 SVCD and DVD
+                 * stream types use an MPEG-2 PS container.
                  */
-                /* FIXME - This only works for an MPEG-2 PS, not a TS */
                 /*
                  * An MPEG-2 Program Stream (PS) is a series of
                  * MPEG-2 Program Packs terminated by an
diff --git a/drivers/media/video/cx18/cx18-mailbox.c b/drivers/media/video/cx18/cx18-mailbox.c
index 2226e5791e99..afe46c3d4057 100644
--- a/drivers/media/video/cx18/cx18-mailbox.c
+++ b/drivers/media/video/cx18/cx18-mailbox.c
@@ -131,7 +131,7 @@ static void dump_mb(struct cx18 *cx, struct cx18_mailbox *mb, char *name)
  * Functions that run in a work_queue work handling context
  */
 
-static void epu_dma_done(struct cx18 *cx, struct cx18_epu_work_order *order)
+static void epu_dma_done(struct cx18 *cx, struct cx18_in_work_order *order)
 {
         u32 handle, mdl_ack_count, id;
         struct cx18_mailbox *mb;
@@ -191,29 +191,30 @@ static void epu_dma_done(struct cx18 *cx, struct cx18_epu_work_order *order)
                 if (buf == NULL) {
                         CX18_WARN("Could not find buf %d for stream %s\n",
                                   id, s->name);
-                        /* Put as many buffers as possible back into fw use */
-                        cx18_stream_load_fw_queue(s);
                         continue;
                 }
 
-                if (s->type == CX18_ENC_STREAM_TYPE_TS && s->dvb.enabled) {
-                        CX18_DEBUG_HI_DMA("TS recv bytesused = %d\n",
-                                          buf->bytesused);
-                        dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
-                                         buf->bytesused);
+                CX18_DEBUG_HI_DMA("%s recv bytesused = %d\n",
+                                  s->name, buf->bytesused);
+
+                if (s->type != CX18_ENC_STREAM_TYPE_TS)
+                        cx18_enqueue(s, buf, &s->q_full);
+                else {
+                        if (s->dvb.enabled)
+                                dvb_dmx_swfilter(&s->dvb.demux, buf->buf,
+                                                 buf->bytesused);
+                        cx18_enqueue(s, buf, &s->q_free);
                 }
-                /* Put as many buffers as possible back into fw use */
-                cx18_stream_load_fw_queue(s);
-                /* Put back TS buffer, since it was removed from all queues */
-                if (s->type == CX18_ENC_STREAM_TYPE_TS)
-                        cx18_stream_put_buf_fw(s, buf);
         }
+        /* Put as many buffers as possible back into fw use */
+        cx18_stream_load_fw_queue(s);
+
         wake_up(&cx->dma_waitq);
         if (s->id != -1)
                 wake_up(&s->waitq);
 }
 
-static void epu_debug(struct cx18 *cx, struct cx18_epu_work_order *order)
+static void epu_debug(struct cx18 *cx, struct cx18_in_work_order *order)
 {
         char *p;
         char *str = order->str;
@@ -224,7 +225,7 @@ static void epu_debug(struct cx18 *cx, struct cx18_epu_work_order *order)
                 CX18_INFO("FW version: %s\n", p - 1);
 }
 
-static void epu_cmd(struct cx18 *cx, struct cx18_epu_work_order *order)
+static void epu_cmd(struct cx18 *cx, struct cx18_in_work_order *order)
 {
         switch (order->rpu) {
         case CPU:
@@ -253,18 +254,18 @@ static void epu_cmd(struct cx18 *cx, struct cx18_epu_work_order *order)
 }
 
 static
-void free_epu_work_order(struct cx18 *cx, struct cx18_epu_work_order *order)
+void free_in_work_order(struct cx18 *cx, struct cx18_in_work_order *order)
 {
         atomic_set(&order->pending, 0);
 }
 
-void cx18_epu_work_handler(struct work_struct *work)
+void cx18_in_work_handler(struct work_struct *work)
 {
-        struct cx18_epu_work_order *order =
-                        container_of(work, struct cx18_epu_work_order, work);
+        struct cx18_in_work_order *order =
+                        container_of(work, struct cx18_in_work_order, work);
         struct cx18 *cx = order->cx;
         epu_cmd(cx, order);
-        free_epu_work_order(cx, order);
+        free_in_work_order(cx, order);
 }
 
 
@@ -272,7 +273,7 @@ void cx18_epu_work_handler(struct work_struct *work)
  * Functions that run in an interrupt handling context
  */
 
-static void mb_ack_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
+static void mb_ack_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 {
         struct cx18_mailbox __iomem *ack_mb;
         u32 ack_irq, req;
@@ -308,7 +309,7 @@ static void mb_ack_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
         return;
 }
 
-static int epu_dma_done_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
+static int epu_dma_done_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 {
         u32 handle, mdl_ack_offset, mdl_ack_count;
         struct cx18_mailbox *mb;
@@ -334,7 +335,7 @@ static int epu_dma_done_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
 }
 
 static
-int epu_debug_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
+int epu_debug_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 {
         u32 str_offset;
         char *str = order->str;
@@ -355,7 +356,7 @@ int epu_debug_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
 }
 
 static inline
-int epu_cmd_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
+int epu_cmd_irq(struct cx18 *cx, struct cx18_in_work_order *order)
 {
         int ret = -1;
 
@@ -387,12 +388,12 @@ int epu_cmd_irq(struct cx18 *cx, struct cx18_epu_work_order *order)
 }
 
 static inline
-struct cx18_epu_work_order *alloc_epu_work_order_irq(struct cx18 *cx)
+struct cx18_in_work_order *alloc_in_work_order_irq(struct cx18 *cx)
 {
         int i;
-        struct cx18_epu_work_order *order = NULL;
+        struct cx18_in_work_order *order = NULL;
 
-        for (i = 0; i < CX18_MAX_EPU_WORK_ORDERS; i++) {
+        for (i = 0; i < CX18_MAX_IN_WORK_ORDERS; i++) {
                 /*
                  * We only need "pending" atomic to inspect its contents,
                  * and need not do a check and set because:
@@ -401,8 +402,8 @@ struct cx18_epu_work_order *alloc_epu_work_order_irq(struct cx18 *cx)
                  * 2. "pending" is only set here, and we're serialized because
                  * we're called in an IRQ handler context.
                  */
-                if (atomic_read(&cx->epu_work_order[i].pending) == 0) {
-                        order = &cx->epu_work_order[i];
+                if (atomic_read(&cx->in_work_order[i].pending) == 0) {
+                        order = &cx->in_work_order[i];
                         atomic_set(&order->pending, 1);
                         break;
                 }
@@ -414,7 +415,7 @@ void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
 {
         struct cx18_mailbox __iomem *mb;
         struct cx18_mailbox *order_mb;
-        struct cx18_epu_work_order *order;
+        struct cx18_in_work_order *order;
         int submit;
 
         switch (rpu) {
@@ -428,7 +429,7 @@ void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
                 return;
         }
 
-        order = alloc_epu_work_order_irq(cx);
+        order = alloc_in_work_order_irq(cx);
         if (order == NULL) {
                 CX18_WARN("Unable to find blank work order form to schedule "
                           "incoming mailbox command processing\n");
@@ -461,7 +462,7 @@ void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu)
          */
         submit = epu_cmd_irq(cx, order);
         if (submit > 0) {
-                queue_work(cx->work_queue, &order->work);
+                queue_work(cx->in_work_queue, &order->work);
         }
 }
 
@@ -478,9 +479,10 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
         u32 __iomem *xpu_state;
         wait_queue_head_t *waitq;
         struct mutex *mb_lock;
-        long int timeout, ret;
+        unsigned long int t0, timeout, ret;
         int i;
         char argstr[MAX_MB_ARGUMENTS*11+1];
+        DEFINE_WAIT(w);
 
         if (info == NULL) {
                 CX18_WARN("unknown cmd %x\n", cmd);
@@ -562,25 +564,49 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[])
 
         CX18_DEBUG_HI_IRQ("sending interrupt SW1: %x to send %s\n",
                           irq, info->name);
+
+        /* So we don't miss the wakeup, prepare to wait before notifying fw */
+        prepare_to_wait(waitq, &w, TASK_UNINTERRUPTIBLE);
         cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq);
 
-        ret = wait_event_timeout(
-                       *waitq,
-                       cx18_readl(cx, &mb->ack) == cx18_readl(cx, &mb->request),
-                       timeout);
+        t0 = jiffies;
+        ack = cx18_readl(cx, &mb->ack);
+        if (ack != req) {
+                schedule_timeout(timeout);
+                ret = jiffies - t0;
+                ack = cx18_readl(cx, &mb->ack);
+        } else {
+                ret = jiffies - t0;
+        }
 
-        if (ret == 0) {
-                /* Timed out */
+        finish_wait(waitq, &w);
+
+        if (req != ack) {
                 mutex_unlock(mb_lock);
-                CX18_DEBUG_WARN("sending %s timed out waiting %d msecs for RPU "
-                                "acknowledgement\n",
-                                info->name, jiffies_to_msecs(timeout));
+                if (ret >= timeout) {
+                        /* Timed out */
+                        CX18_DEBUG_WARN("sending %s timed out waiting %d msecs "
+                                        "for RPU acknowledgement\n",
+                                        info->name, jiffies_to_msecs(ret));
+                } else {
+                        CX18_DEBUG_WARN("woken up before mailbox ack was ready "
+                                        "after submitting %s to RPU.  only "
+                                        "waited %d msecs on req %u but awakened"
+                                        " with unmatched ack %u\n",
+                                        info->name,
+                                        jiffies_to_msecs(ret),
+                                        req, ack);
+                }
                 return -EINVAL;
         }
 
-        if (ret != timeout)
+        if (ret >= timeout)
+                CX18_DEBUG_WARN("failed to be awakened upon RPU acknowledgment "
+                                "sending %s; timed out waiting %d msecs\n",
+                                info->name, jiffies_to_msecs(ret));
+        else
                 CX18_DEBUG_HI_API("waited %u msecs for %s to be acked\n",
-                                  jiffies_to_msecs(timeout-ret), info->name);
+                                  jiffies_to_msecs(ret), info->name);
 
         /* Collect data returned by the XPU */
         for (i = 0; i < MAX_MB_ARGUMENTS; i++)
diff --git a/drivers/media/video/cx18/cx18-mailbox.h b/drivers/media/video/cx18/cx18-mailbox.h
index ce2b6686aa00..e23aaac5b280 100644
--- a/drivers/media/video/cx18/cx18-mailbox.h
+++ b/drivers/media/video/cx18/cx18-mailbox.h
@@ -95,6 +95,6 @@ int cx18_api_func(void *priv, u32 cmd, int in, int out,
 
 void cx18_api_epu_cmd_irq(struct cx18 *cx, int rpu);
 
-void cx18_epu_work_handler(struct work_struct *work);
+void cx18_in_work_handler(struct work_struct *work);
 
 #endif
diff --git a/drivers/media/video/cx18/cx18-queue.c b/drivers/media/video/cx18/cx18-queue.c
index 3046b8e74345..fa1ed7897d97 100644
--- a/drivers/media/video/cx18/cx18-queue.c
+++ b/drivers/media/video/cx18/cx18-queue.c
@@ -23,8 +23,8 @@
  */
 
 #include "cx18-driver.h"
-#include "cx18-streams.h"
 #include "cx18-queue.h"
+#include "cx18-streams.h"
 #include "cx18-scb.h"
 
 void cx18_buf_swap(struct cx18_buffer *buf)
@@ -53,13 +53,13 @@ struct cx18_queue *_cx18_enqueue(struct cx18_stream *s, struct cx18_buffer *buf,
                 buf->skipped = 0;
         }
 
-        mutex_lock(&s->qlock);
-
         /* q_busy is restricted to a max buffer count imposed by firmware */
         if (q == &s->q_busy &&
             atomic_read(&q->buffers) >= CX18_MAX_FW_MDLS_PER_STREAM)
                 q = &s->q_free;
 
+        spin_lock(&q->lock);
+
         if (to_front)
                 list_add(&buf->list, &q->list); /* LIFO */
         else
@@ -67,7 +67,7 @@ struct cx18_queue *_cx18_enqueue(struct cx18_stream *s, struct cx18_buffer *buf,
         q->bytesused += buf->bytesused - buf->readpos;
         atomic_inc(&q->buffers);
 
-        mutex_unlock(&s->qlock);
+        spin_unlock(&q->lock);
         return q;
 }
 
@@ -75,7 +75,7 @@ struct cx18_buffer *cx18_dequeue(struct cx18_stream *s, struct cx18_queue *q)
 {
         struct cx18_buffer *buf = NULL;
 
-        mutex_lock(&s->qlock);
+        spin_lock(&q->lock);
         if (!list_empty(&q->list)) {
                 buf = list_first_entry(&q->list, struct cx18_buffer, list);
                 list_del_init(&buf->list);
@@ -83,7 +83,7 @@ struct cx18_buffer *cx18_dequeue(struct cx18_stream *s, struct cx18_queue *q)
                 buf->skipped = 0;
                 atomic_dec(&q->buffers);
         }
-        mutex_unlock(&s->qlock);
+        spin_unlock(&q->lock);
         return buf;
 }
 
@@ -94,9 +94,23 @@ struct cx18_buffer *cx18_queue_get_buf(struct cx18_stream *s, u32 id,
         struct cx18_buffer *buf;
         struct cx18_buffer *tmp;
         struct cx18_buffer *ret = NULL;
-
-        mutex_lock(&s->qlock);
+        LIST_HEAD(sweep_up);
+
+        /*
+         * We don't have to acquire multiple q locks here, because we are
+         * serialized by the single threaded work handler.
+         * Buffers from the firmware will thus remain in order as
+         * they are moved from q_busy to q_full or to the dvb ring buffer.
+         */
+        spin_lock(&s->q_busy.lock);
         list_for_each_entry_safe(buf, tmp, &s->q_busy.list, list) {
+                /*
+                 * We should find what the firmware told us is done,
+                 * right at the front of the queue.  If we don't, we likely have
+                 * missed a buffer done message from the firmware.
+                 * Once we skip a buffer repeatedly, relative to the size of
+                 * q_busy, we have high confidence we've missed it.
+                 */
                 if (buf->id != id) {
                         buf->skipped++;
                         if (buf->skipped >= atomic_read(&s->q_busy.buffers)-1) {
@@ -105,38 +119,41 @@ struct cx18_buffer *cx18_queue_get_buf(struct cx18_stream *s, u32 id,
                                           "times - it must have dropped out of "
                                           "rotation\n", s->name, buf->id,
                                           buf->skipped);
-                                /* move it to q_free */
-                                list_move_tail(&buf->list, &s->q_free.list);
-                                buf->bytesused = buf->readpos = buf->b_flags =
-                                        buf->skipped = 0;
+                                /* Sweep it up to put it back into rotation */
+                                list_move_tail(&buf->list, &sweep_up);
                                 atomic_dec(&s->q_busy.buffers);
-                                atomic_inc(&s->q_free.buffers);
                         }
                         continue;
                 }
-
-                buf->bytesused = bytesused;
-                /* Sync the buffer before we release the qlock */
-                cx18_buf_sync_for_cpu(s, buf);
-                if (s->type == CX18_ENC_STREAM_TYPE_TS) {
-                        /*
-                         * TS doesn't use q_full.  As we pull the buffer off of
-                         * the queue here, the caller will have to put it back.
-                         */
-                        list_del_init(&buf->list);
-                } else {
-                        /* Move buffer from q_busy to q_full */
-                        list_move_tail(&buf->list, &s->q_full.list);
-                        set_bit(CX18_F_B_NEED_BUF_SWAP, &buf->b_flags);
-                        s->q_full.bytesused += buf->bytesused;
-                        atomic_inc(&s->q_full.buffers);
-                }
+                /*
+                 * We pull the desired buffer off of the queue here.  Something
+                 * will have to put it back on a queue later.
+                 */
+                list_del_init(&buf->list);
                 atomic_dec(&s->q_busy.buffers);
-
                 ret = buf;
                 break;
         }
-        mutex_unlock(&s->qlock);
+        spin_unlock(&s->q_busy.lock);
+
+        /*
+         * We found the buffer for which we were looking.  Get it ready for
+         * the caller to put on q_full or in the dvb ring buffer.
+         */
+        if (ret != NULL) {
+                ret->bytesused = bytesused;
+                ret->skipped = 0;
+                /* readpos and b_flags were 0'ed when the buf went on q_busy */
+                cx18_buf_sync_for_cpu(s, ret);
+                if (s->type != CX18_ENC_STREAM_TYPE_TS)
+                        set_bit(CX18_F_B_NEED_BUF_SWAP, &ret->b_flags);
+        }
+
+        /* Put any buffers the firmware is ignoring back into normal rotation */
+        list_for_each_entry_safe(buf, tmp, &sweep_up, list) {
+                list_del_init(&buf->list);
+                cx18_enqueue(s, buf, &s->q_free);
+        }
         return ret;
 }
 
@@ -148,7 +165,7 @@ static void cx18_queue_flush(struct cx18_stream *s, struct cx18_queue *q)
         if (q == &s->q_free)
                 return;
 
-        mutex_lock(&s->qlock);
+        spin_lock(&q->lock);
         while (!list_empty(&q->list)) {
                 buf = list_first_entry(&q->list, struct cx18_buffer, list);
                 list_move_tail(&buf->list, &s->q_free.list);
@@ -156,7 +173,7 @@ static void cx18_queue_flush(struct cx18_stream *s, struct cx18_queue *q)
                 atomic_inc(&s->q_free.buffers);
         }
         cx18_queue_init(q);
-        mutex_unlock(&s->qlock);
+        spin_unlock(&q->lock);
 }
 
 void cx18_flush_queues(struct cx18_stream *s)
diff --git a/drivers/media/video/cx18/cx18-streams.c b/drivers/media/video/cx18/cx18-streams.c
index 0932b76b2373..54d248e16d85 100644
--- a/drivers/media/video/cx18/cx18-streams.c
+++ b/drivers/media/video/cx18/cx18-streams.c
@@ -116,12 +116,16 @@ static void cx18_stream_init(struct cx18 *cx, int type)
         s->buffers = cx->stream_buffers[type];
         s->buf_size = cx->stream_buf_size[type];
 
-        mutex_init(&s->qlock);
         init_waitqueue_head(&s->waitq);
         s->id = -1;
+        spin_lock_init(&s->q_free.lock);
         cx18_queue_init(&s->q_free);
+        spin_lock_init(&s->q_busy.lock);
         cx18_queue_init(&s->q_busy);
+        spin_lock_init(&s->q_full.lock);
         cx18_queue_init(&s->q_full);
+
+        INIT_WORK(&s->out_work_order, cx18_out_work_handler);
 }
 
 static int cx18_prep_dev(struct cx18 *cx, int type)
@@ -367,9 +371,14 @@ static void cx18_vbi_setup(struct cx18_stream *s)
                  * Tell the encoder to capture 21-4+1=18 lines per field,
                  * since we want lines 10 through 21.
                  *
-                 * FIXME - revisit for 625/50 systems
+                 * For 625/50 systems, according to the VIP 2 & BT.656 std:
+                 * The EAV RP code's Field bit toggles on line 1, a few lines
+                 * after the Vertcal Blank bit has already toggled.
+                 * (We've actually set the digitizer so that the Field bit
+                 * toggles on line 2.) Tell the encoder to capture 23-2+1=22
+                 * lines per field, since we want lines 6 through 23.
                  */
-                lines = cx->is_60hz ? (21 - 4 + 1) * 2 : 38;
+                lines = cx->is_60hz ? (21 - 4 + 1) * 2 : (23 - 2 + 1) * 2;
         }
 
         data[0] = s->handle;
@@ -431,14 +440,16 @@ static void cx18_vbi_setup(struct cx18_stream *s)
         cx18_api(cx, CX18_CPU_SET_RAW_VBI_PARAM, 6, data);
 }
 
-struct cx18_queue *cx18_stream_put_buf_fw(struct cx18_stream *s,
-                                          struct cx18_buffer *buf)
+static
+struct cx18_queue *_cx18_stream_put_buf_fw(struct cx18_stream *s,
+                                           struct cx18_buffer *buf)
 {
         struct cx18 *cx = s->cx;
         struct cx18_queue *q;
 
         /* Don't give it to the firmware, if we're not running a capture */
         if (s->handle == CX18_INVALID_TASK_HANDLE ||
+            test_bit(CX18_F_S_STOPPING, &s->s_flags) ||
             !test_bit(CX18_F_S_STREAMING, &s->s_flags))
                 return cx18_enqueue(s, buf, &s->q_free);
 
@@ -453,7 +464,8 @@ struct cx18_queue *cx18_stream_put_buf_fw(struct cx18_stream *s,
         return q;
 }
 
-void cx18_stream_load_fw_queue(struct cx18_stream *s)
+static
+void _cx18_stream_load_fw_queue(struct cx18_stream *s)
 {
         struct cx18_queue *q;
         struct cx18_buffer *buf;
@@ -467,11 +479,19 @@ void cx18_stream_load_fw_queue(struct cx18_stream *s)
                 buf = cx18_dequeue(s, &s->q_free);
                 if (buf == NULL)
                         break;
-                q = cx18_stream_put_buf_fw(s, buf);
+                q = _cx18_stream_put_buf_fw(s, buf);
         } while (atomic_read(&s->q_busy.buffers) < CX18_MAX_FW_MDLS_PER_STREAM
                  && q == &s->q_busy);
 }
 
+void cx18_out_work_handler(struct work_struct *work)
+{
+        struct cx18_stream *s =
+                         container_of(work, struct cx18_stream, out_work_order);
+
+        _cx18_stream_load_fw_queue(s);
+}
+
 int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
 {
         u32 data[MAX_MB_ARGUMENTS];
@@ -600,19 +620,20 @@ int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
 
         /* Init all the cpu_mdls for this stream */
         cx18_flush_queues(s);
-        mutex_lock(&s->qlock);
+        spin_lock(&s->q_free.lock);
         list_for_each_entry(buf, &s->q_free.list, list) {
                 cx18_writel(cx, buf->dma_handle,
                                         &cx->scb->cpu_mdl[buf->id].paddr);
                 cx18_writel(cx, s->buf_size, &cx->scb->cpu_mdl[buf->id].length);
         }
-        mutex_unlock(&s->qlock);
-        cx18_stream_load_fw_queue(s);
+        spin_unlock(&s->q_free.lock);
+        _cx18_stream_load_fw_queue(s);
 
         /* begin_capture */
         if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) {
                 CX18_DEBUG_WARN("Error starting capture!\n");
                 /* Ensure we're really not capturing before releasing MDLs */
+                set_bit(CX18_F_S_STOPPING, &s->s_flags);
                 if (s->type == CX18_ENC_STREAM_TYPE_MPG)
                         cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1);
                 else
@@ -622,6 +643,7 @@ int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
                 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
                 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
                 s->handle = CX18_INVALID_TASK_HANDLE;
+                clear_bit(CX18_F_S_STOPPING, &s->s_flags);
                 if (atomic_read(&cx->tot_capturing) == 0) {
                         set_bit(CX18_F_I_EOS, &cx->i_flags);
                         cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
@@ -666,6 +688,7 @@ int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end)
         if (atomic_read(&cx->tot_capturing) == 0)
                 return 0;
 
+        set_bit(CX18_F_S_STOPPING, &s->s_flags);
         if (s->type == CX18_ENC_STREAM_TYPE_MPG)
                 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end);
         else
@@ -689,6 +712,7 @@ int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end)
 
         cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
         s->handle = CX18_INVALID_TASK_HANDLE;
+        clear_bit(CX18_F_S_STOPPING, &s->s_flags);
 
         if (atomic_read(&cx->tot_capturing) > 0)
                 return 0;
diff --git a/drivers/media/video/cx18/cx18-streams.h b/drivers/media/video/cx18/cx18-streams.h
index 420e0a172945..1afc3fd9d822 100644
--- a/drivers/media/video/cx18/cx18-streams.h
+++ b/drivers/media/video/cx18/cx18-streams.h
@@ -28,10 +28,24 @@ int cx18_streams_setup(struct cx18 *cx);
 int cx18_streams_register(struct cx18 *cx);
 void cx18_streams_cleanup(struct cx18 *cx, int unregister);
 
+/* Related to submission of buffers to firmware */
+static inline void cx18_stream_load_fw_queue(struct cx18_stream *s)
+{
+        struct cx18 *cx = s->cx;
+        queue_work(cx->out_work_queue, &s->out_work_order);
+}
+
+static inline void cx18_stream_put_buf_fw(struct cx18_stream *s,
+                                          struct cx18_buffer *buf)
+{
+        /* Put buf on q_free; the out work handler will move buf(s) to q_busy */
+        cx18_enqueue(s, buf, &s->q_free);
+        cx18_stream_load_fw_queue(s);
+}
+
+void cx18_out_work_handler(struct work_struct *work);
+
 /* Capture related */
-void cx18_stream_load_fw_queue(struct cx18_stream *s);
-struct cx18_queue *cx18_stream_put_buf_fw(struct cx18_stream *s,
-                                          struct cx18_buffer *buf);
 int cx18_start_v4l2_encode_stream(struct cx18_stream *s);
 int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end);
 
diff --git a/drivers/media/video/cx18/cx18-version.h b/drivers/media/video/cx18/cx18-version.h
index bd9bd44da791..45494b094e7f 100644
--- a/drivers/media/video/cx18/cx18-version.h
+++ b/drivers/media/video/cx18/cx18-version.h
@@ -24,7 +24,7 @@
 
 #define CX18_DRIVER_NAME "cx18"
 #define CX18_DRIVER_VERSION_MAJOR 1
-#define CX18_DRIVER_VERSION_MINOR 1
+#define CX18_DRIVER_VERSION_MINOR 2
 #define CX18_DRIVER_VERSION_PATCHLEVEL 0
 
 #define CX18_VERSION __stringify(CX18_DRIVER_VERSION_MAJOR) "." __stringify(CX18_DRIVER_VERSION_MINOR) "." __stringify(CX18_DRIVER_VERSION_PATCHLEVEL)
diff --git a/drivers/media/video/cx231xx/cx231xx-avcore.c b/drivers/media/video/cx231xx/cx231xx-avcore.c
index 1be3881be991..6a9464079b4c 100644
--- a/drivers/media/video/cx231xx/cx231xx-avcore.c
+++ b/drivers/media/video/cx231xx/cx231xx-avcore.c
@@ -29,7 +29,6 @@
 #include <linux/bitmap.h>
 #include <linux/usb.h>
 #include <linux/i2c.h>
-#include <linux/version.h>
 #include <linux/mm.h>
 #include <linux/mutex.h>
 
diff --git a/drivers/media/video/cx231xx/cx231xx-cards.c b/drivers/media/video/cx231xx/cx231xx-cards.c
index c8a32b1b5381..63d2239fd324 100644
--- a/drivers/media/video/cx231xx/cx231xx-cards.c
+++ b/drivers/media/video/cx231xx/cx231xx-cards.c
@@ -281,12 +281,12 @@ static void cx231xx_config_tuner(struct cx231xx *dev)
 }
 
 /* ----------------------------------------------------------------------- */
-void cx231xx_set_ir(struct cx231xx *dev, struct IR_i2c *ir)
+void cx231xx_register_i2c_ir(struct cx231xx *dev)
 {
-        if (disable_ir) {
-                ir->get_key = NULL;
+        if (disable_ir)
                 return;
-        }
+
+        /* REVISIT: instantiate IR device */
 
         /* detect & configure */
         switch (dev->model) {
diff --git a/drivers/media/video/cx231xx/cx231xx-i2c.c b/drivers/media/video/cx231xx/cx231xx-i2c.c
index b4a03d813e00..33219dc4d649 100644
--- a/drivers/media/video/cx231xx/cx231xx-i2c.c
+++ b/drivers/media/video/cx231xx/cx231xx-i2c.c
@@ -424,34 +424,6 @@ static u32 functionality(struct i2c_adapter *adap)
         return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_I2C;
 }
 
-/*
- * attach_inform()
- * gets called when a device attaches to the i2c bus
- * does some basic configuration
- */
-static int attach_inform(struct i2c_client *client)
-{
-        struct cx231xx_i2c *bus = i2c_get_adapdata(client->adapter);
-        struct cx231xx *dev = bus->dev;
-
-        switch (client->addr << 1) {
-        case 0x8e:
-                {
-                        struct IR_i2c *ir = i2c_get_clientdata(client);
-                        dprintk1(1, "attach_inform: IR detected (%s).\n",
-                                 ir->phys);
-                        cx231xx_set_ir(dev, ir);
-                        break;
-                }
-                break;
-
-        default:
-                break;
-        }
-
-        return 0;
-}
-
 static struct i2c_algorithm cx231xx_algo = {
         .master_xfer = cx231xx_i2c_xfer,
         .functionality = functionality,
@@ -462,7 +434,6 @@ static struct i2c_adapter cx231xx_adap_template = {
         .name = "cx231xx",
         .id = I2C_HW_B_CX231XX,
         .algo = &cx231xx_algo,
-        .client_register = attach_inform,
 };
 
 static struct i2c_client cx231xx_client_template = {
@@ -537,6 +508,9 @@ int cx231xx_i2c_register(struct cx231xx_i2c *bus)
         if (0 == bus->i2c_rc) {
                 if (i2c_scan)
                         cx231xx_do_i2c_scan(dev, &bus->i2c_client);
+
+                /* Instantiate the IR receiver device, if present */
+                cx231xx_register_i2c_ir(dev);
         } else
                 cx231xx_warn("%s: i2c bus %d register FAILED\n",
                              dev->name, bus->nr);
diff --git a/drivers/media/video/cx231xx/cx231xx-input.c b/drivers/media/video/cx231xx/cx231xx-input.c
index 97e304c3c799..48f22fa38e6c 100644
--- a/drivers/media/video/cx231xx/cx231xx-input.c
+++ b/drivers/media/video/cx231xx/cx231xx-input.c
@@ -36,7 +36,7 @@ MODULE_PARM_DESC(ir_debug, "enable debug messages [IR]");
 
 #define i2cdprintk(fmt, arg...) \
         if (ir_debug) { \
-                printk(KERN_DEBUG "%s/ir: " fmt, ir->c.name , ## arg); \
+                printk(KERN_DEBUG "%s/ir: " fmt, ir->name , ## arg); \
         }
 
 #define dprintk(fmt, arg...) \
diff --git a/drivers/media/video/cx231xx/cx231xx-vbi.c b/drivers/media/video/cx231xx/cx231xx-vbi.c
index 94180526909c..e97b8023a655 100644
--- a/drivers/media/video/cx231xx/cx231xx-vbi.c
+++ b/drivers/media/video/cx231xx/cx231xx-vbi.c
@@ -26,7 +26,6 @@
 #include <linux/bitmap.h>
 #include <linux/usb.h>
 #include <linux/i2c.h>
-#include <linux/version.h>
 #include <linux/mm.h>
 #include <linux/mutex.h>
 
diff --git a/drivers/media/video/cx231xx/cx231xx.h b/drivers/media/video/cx231xx/cx231xx.h
index aa4a23ef491a..e38eb2d425f7 100644
--- a/drivers/media/video/cx231xx/cx231xx.h
+++ b/drivers/media/video/cx231xx/cx231xx.h
@@ -738,7 +738,7 @@ extern void cx231xx_card_setup(struct cx231xx *dev);
 extern struct cx231xx_board cx231xx_boards[];
 extern struct usb_device_id cx231xx_id_table[];
 extern const unsigned int cx231xx_bcount;
-void cx231xx_set_ir(struct cx231xx *dev, struct IR_i2c *ir);
+void cx231xx_register_i2c_ir(struct cx231xx *dev);
 int cx231xx_tuner_callback(void *ptr, int component, int command, int arg);
 
 /* Provided by cx231xx-input.c */
diff --git a/drivers/media/video/cx23885/cimax2.c b/drivers/media/video/cx23885/cimax2.c
index 9a6536998d90..08582e58bdbf 100644
--- a/drivers/media/video/cx23885/cimax2.c
+++ b/drivers/media/video/cx23885/cimax2.c
@@ -312,7 +312,7 @@ static void netup_read_ci_status(struct work_struct *work)
                 "TS config = %02x\n", __func__, state->ci_i2c_addr, 0, buf[0],
                 buf[32]);
 
-        if (buf[0] && 1)
+        if (buf[0] & 1)
                 state->status = DVB_CA_EN50221_POLL_CAM_PRESENT |
                         DVB_CA_EN50221_POLL_CAM_READY;
         else
diff --git a/drivers/media/video/cx23885/cx23885-417.c b/drivers/media/video/cx23885/cx23885-417.c
index 6f5df90af93e..2943bfd32a94 100644
--- a/drivers/media/video/cx23885/cx23885-417.c
+++ b/drivers/media/video/cx23885/cx23885-417.c
@@ -1742,7 +1742,6 @@ static struct video_device *cx23885_video_dev_alloc(
         if (NULL == vfd)
                 return NULL;
         *vfd = *template;
-        vfd->minor   = -1;
         snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
                 type, cx23885_boards[tsport->dev->board].name);
         vfd->parent  = &pci->dev;
diff --git a/drivers/media/video/cx23885/cx23885-cards.c b/drivers/media/video/cx23885/cx23885-cards.c
index 6d6293f7d428..ce29b5e34a11 100644
--- a/drivers/media/video/cx23885/cx23885-cards.c
+++ b/drivers/media/video/cx23885/cx23885-cards.c
@@ -181,6 +181,26 @@ struct cx23885_board cx23885_boards[] = {
                 .portb          = CX23885_MPEG_DVB,
                 .portc          = CX23885_MPEG_DVB,
         },
+        [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
+                .name           = "Hauppauge WinTV-HVR1270",
+                .portc          = CX23885_MPEG_DVB,
+        },
+        [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
+                .name           = "Hauppauge WinTV-HVR1275",
+                .portc          = CX23885_MPEG_DVB,
+        },
+        [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
+                .name           = "Hauppauge WinTV-HVR1255",
+                .portc          = CX23885_MPEG_DVB,
+        },
+        [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
+                .name           = "Hauppauge WinTV-HVR1210",
+                .portc          = CX23885_MPEG_DVB,
+        },
+        [CX23885_BOARD_MYGICA_X8506] = {
+                .name           = "Mygica X8506 DMB-TH",
+                .portb          = CX23885_MPEG_DVB,
+        },
 };
 const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
 
@@ -280,6 +300,30 @@ struct cx23885_subid cx23885_subids[] = {
                 .subvendor = 0x1b55,
                 .subdevice = 0x2a2c,
                 .card      = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
+        }, {
+                .subvendor = 0x0070,
+                .subdevice = 0x2211,
+                .card      = CX23885_BOARD_HAUPPAUGE_HVR1270,
+        }, {
+                .subvendor = 0x0070,
+                .subdevice = 0x2215,
+                .card      = CX23885_BOARD_HAUPPAUGE_HVR1275,
+        }, {
+                .subvendor = 0x0070,
+                .subdevice = 0x2251,
+                .card      = CX23885_BOARD_HAUPPAUGE_HVR1255,
+        }, {
+                .subvendor = 0x0070,
+                .subdevice = 0x2291,
+                .card      = CX23885_BOARD_HAUPPAUGE_HVR1210,
+        }, {
+                .subvendor = 0x0070,
+                .subdevice = 0x2295,
+                .card      = CX23885_BOARD_HAUPPAUGE_HVR1210,
+        }, {
+                .subvendor = 0x14f1,
+                .subdevice = 0x8651,
+                .card      = CX23885_BOARD_MYGICA_X8506,
         },
 };
 const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
@@ -321,6 +365,42 @@ static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
 
         /* Make sure we support the board model */
         switch (tv.model) {
+        case 22001:
+                /* WinTV-HVR1270 (PCIe, Retail, half height)
+                 * ATSC/QAM and basic analog, IR Blast */
+        case 22009:
+                /* WinTV-HVR1210 (PCIe, Retail, half height)
+                 * DVB-T and basic analog, IR Blast */
+        case 22011:
+                /* WinTV-HVR1270 (PCIe, Retail, half height)
+                 * ATSC/QAM and basic analog, IR Recv */
+        case 22019:
+                /* WinTV-HVR1210 (PCIe, Retail, half height)
+                 * DVB-T and basic analog, IR Recv */
+        case 22021:
+                /* WinTV-HVR1275 (PCIe, Retail, half height)
+                 * ATSC/QAM and basic analog, IR Recv */
+        case 22029:
+                /* WinTV-HVR1210 (PCIe, Retail, half height)
+                 * DVB-T and basic analog, IR Recv */
+        case 22101:
+                /* WinTV-HVR1270 (PCIe, Retail, full height)
+                 * ATSC/QAM and basic analog, IR Blast */
+        case 22109:
+                /* WinTV-HVR1210 (PCIe, Retail, full height)
+                 * DVB-T and basic analog, IR Blast */
+        case 22111:
+                /* WinTV-HVR1270 (PCIe, Retail, full height)
+                 * ATSC/QAM and basic analog, IR Recv */
+        case 22119:
+                /* WinTV-HVR1210 (PCIe, Retail, full height)
+                 * DVB-T and basic analog, IR Recv */
+        case 22121:
+                /* WinTV-HVR1275 (PCIe, Retail, full height)
+                 * ATSC/QAM and basic analog, IR Recv */
+        case 22129:
+                /* WinTV-HVR1210 (PCIe, Retail, full height)
+                 * DVB-T and basic analog, IR Recv */
         case 71009:
                 /* WinTV-HVR1200 (PCIe, Retail, full height)
                  * DVB-T and basic analog */
@@ -619,6 +699,30 @@ void cx23885_gpio_setup(struct cx23885_dev *dev)
                 /* enable irq */
                 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
                 break;
+        case CX23885_BOARD_HAUPPAUGE_HVR1270:
+        case CX23885_BOARD_HAUPPAUGE_HVR1275:
+        case CX23885_BOARD_HAUPPAUGE_HVR1255:
+        case CX23885_BOARD_HAUPPAUGE_HVR1210:
+                /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
+                /* GPIO-6 I2C Gate which can isolate the demod from the bus */
+                /* GPIO-9 Demod reset */
+
+                /* Put the parts into reset and back */
+                cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
+                cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
+                cx23885_gpio_clear(dev, GPIO_9);
+                mdelay(20);
+                cx23885_gpio_set(dev, GPIO_9);
+                break;
+        case CX23885_BOARD_MYGICA_X8506:
+                /* GPIO-1 reset XC5000 */
+                /* GPIO-2 reset LGS8GL5 */
+                cx_set(GP0_IO, 0x00060000);
+                cx_clear(GP0_IO, 0x00000006);
+                mdelay(100);
+                cx_set(GP0_IO, 0x00060006);
+                mdelay(100);
+                break;
         }
 }
 
@@ -631,6 +735,10 @@ int cx23885_ir_init(struct cx23885_dev *dev)
         case CX23885_BOARD_HAUPPAUGE_HVR1800:
         case CX23885_BOARD_HAUPPAUGE_HVR1200:
         case CX23885_BOARD_HAUPPAUGE_HVR1400:
+        case CX23885_BOARD_HAUPPAUGE_HVR1270:
+        case CX23885_BOARD_HAUPPAUGE_HVR1275:
+        case CX23885_BOARD_HAUPPAUGE_HVR1255:
+        case CX23885_BOARD_HAUPPAUGE_HVR1210:
                 /* FIXME: Implement me */
                 break;
         case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
@@ -666,6 +774,10 @@ void cx23885_card_setup(struct cx23885_dev *dev)
         case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
         case CX23885_BOARD_HAUPPAUGE_HVR1200:
         case CX23885_BOARD_HAUPPAUGE_HVR1700:
+        case CX23885_BOARD_HAUPPAUGE_HVR1270:
+        case CX23885_BOARD_HAUPPAUGE_HVR1275:
+        case CX23885_BOARD_HAUPPAUGE_HVR1255:
+        case CX23885_BOARD_HAUPPAUGE_HVR1210:
                 if (dev->i2c_bus[0].i2c_rc == 0)
                         hauppauge_eeprom(dev, eeprom+0xc0);
                 break;
@@ -714,6 +826,11 @@ void cx23885_card_setup(struct cx23885_dev *dev)
                 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
                 ts2->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
                 break;
+        case CX23885_BOARD_MYGICA_X8506:
+                ts1->gen_ctrl_val  = 0x5; /* Parallel */
+                ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
+                ts1->src_sel_val   = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
+                break;
         case CX23885_BOARD_HAUPPAUGE_HVR1250:
         case CX23885_BOARD_HAUPPAUGE_HVR1500:
         case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
@@ -723,6 +840,10 @@ void cx23885_card_setup(struct cx23885_dev *dev)
         case CX23885_BOARD_HAUPPAUGE_HVR1400:
         case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
         case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
+        case CX23885_BOARD_HAUPPAUGE_HVR1270:
+        case CX23885_BOARD_HAUPPAUGE_HVR1275:
+        case CX23885_BOARD_HAUPPAUGE_HVR1255:
+        case CX23885_BOARD_HAUPPAUGE_HVR1210:
         default:
                 ts2->gen_ctrl_val  = 0xc; /* Serial bus + punctured clock */
                 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
diff --git a/drivers/media/video/cx23885/cx23885-core.c b/drivers/media/video/cx23885/cx23885-core.c
index beda42925ce7..bf7bb1c412fb 100644
--- a/drivers/media/video/cx23885/cx23885-core.c
+++ b/drivers/media/video/cx23885/cx23885-core.c
@@ -1700,9 +1700,13 @@ static irqreturn_t cx23885_irq(int irq, void *dev_id)
         }
 
         if (cx23885_boards[dev->board].cimax > 0 &&
-                ((pci_status & PCI_MSK_GPIO0) || (pci_status & PCI_MSK_GPIO1)))
-                /* handled += cx23885_irq_gpio(dev, pci_status); */
-                handled += netup_ci_slot_status(dev, pci_status);
+                ((pci_status & PCI_MSK_GPIO0) ||
+                        (pci_status & PCI_MSK_GPIO1))) {
+
+                if (cx23885_boards[dev->board].cimax > 0)
+                        handled += netup_ci_slot_status(dev, pci_status);
+
+        }
 
         if (ts1_status) {
                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
@@ -1729,6 +1733,88 @@ out:
         return IRQ_RETVAL(handled);
 }
 
+static inline int encoder_on_portb(struct cx23885_dev *dev)
+{
+        return cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER;
+}
+
+static inline int encoder_on_portc(struct cx23885_dev *dev)
+{
+        return cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER;
+}
+
+/* Mask represents 32 different GPIOs, GPIO's are split into multiple
+ * registers depending on the board configuration (and whether the
+ * 417 encoder (wi it's own GPIO's) are present. Each GPIO bit will
+ * be pushed into the correct hardware register, regardless of the
+ * physical location. Certain registers are shared so we sanity check
+ * and report errors if we think we're tampering with a GPIo that might
+ * be assigned to the encoder (and used for the host bus).
+ *
+ * GPIO  2 thru  0 - On the cx23885 bridge
+ * GPIO 18 thru  3 - On the cx23417 host bus interface
+ * GPIO 23 thru 19 - On the cx25840 a/v core
+ */
+void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask)
+{
+        if (mask & 0x7)
+                cx_set(GP0_IO, mask & 0x7);
+
+        if (mask & 0x0007fff8) {
+                if (encoder_on_portb(dev) || encoder_on_portc(dev))
+                        printk(KERN_ERR
+                                "%s: Setting GPIO on encoder ports\n",
+                                dev->name);
+                cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
+        }
+
+        /* TODO: 23-19 */
+        if (mask & 0x00f80000)
+                printk(KERN_INFO "%s: Unsupported\n", dev->name);
+}
+
+void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask)
+{
+        if (mask & 0x00000007)
+                cx_clear(GP0_IO, mask & 0x7);
+
+        if (mask & 0x0007fff8) {
+                if (encoder_on_portb(dev) || encoder_on_portc(dev))
+                        printk(KERN_ERR
+                                "%s: Clearing GPIO moving on encoder ports\n",
+                                dev->name);
+                cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
+        }
+
+        /* TODO: 23-19 */
+        if (mask & 0x00f80000)
+                printk(KERN_INFO "%s: Unsupported\n", dev->name);
+}
+
+void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
+{
+        if ((mask & 0x00000007) && asoutput)
+                cx_set(GP0_IO, (mask & 0x7) << 16);
+        else if ((mask & 0x00000007) && !asoutput)
+                cx_clear(GP0_IO, (mask & 0x7) << 16);
+
+        if (mask & 0x0007fff8) {
+                if (encoder_on_portb(dev) || encoder_on_portc(dev))
+                        printk(KERN_ERR
+                                "%s: Enabling GPIO on encoder ports\n",
+                                dev->name);
+        }
+
+        /* MC417_OEN is active low for output, write 1 for an input */
+        if ((mask & 0x0007fff8) && asoutput)
+                cx_clear(MC417_OEN, (mask & 0x7fff8) >> 3);
+
+        else if ((mask & 0x0007fff8) && !asoutput)
+                cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
+
+        /* TODO: 23-19 */
+}
+
 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
                                      const struct pci_device_id *pci_id)
 {
diff --git a/drivers/media/video/cx23885/cx23885-dvb.c b/drivers/media/video/cx23885/cx23885-dvb.c
index 1dc070da8652..e236df23370e 100644
--- a/drivers/media/video/cx23885/cx23885-dvb.c
+++ b/drivers/media/video/cx23885/cx23885-dvb.c
@@ -49,8 +49,10 @@
 #include "lnbh24.h"
 #include "cx24116.h"
 #include "cimax2.h"
+#include "lgs8gxx.h"
 #include "netup-eeprom.h"
 #include "netup-init.h"
+#include "lgdt3305.h"
 
 static unsigned int debug;
 
@@ -122,7 +124,22 @@ static struct tda10048_config hauppauge_hvr1200_config = {
         .demod_address    = 0x10 >> 1,
         .output_mode      = TDA10048_SERIAL_OUTPUT,
         .fwbulkwritelen   = TDA10048_BULKWRITE_200,
-        .inversion        = TDA10048_INVERSION_ON
+        .inversion        = TDA10048_INVERSION_ON,
+        .dtv6_if_freq_khz = TDA10048_IF_3300,
+        .dtv7_if_freq_khz = TDA10048_IF_3800,
+        .dtv8_if_freq_khz = TDA10048_IF_4300,
+        .clk_freq_khz     = TDA10048_CLK_16000,
+};
+
+static struct tda10048_config hauppauge_hvr1210_config = {
+        .demod_address    = 0x10 >> 1,
+        .output_mode      = TDA10048_SERIAL_OUTPUT,
+        .fwbulkwritelen   = TDA10048_BULKWRITE_200,
+        .inversion        = TDA10048_INVERSION_ON,
+        .dtv6_if_freq_khz = TDA10048_IF_3300,
+        .dtv7_if_freq_khz = TDA10048_IF_3500,
+        .dtv8_if_freq_khz = TDA10048_IF_4000,
+        .clk_freq_khz     = TDA10048_CLK_16000,
 };
 
 static struct s5h1409_config hauppauge_ezqam_config = {
@@ -194,6 +211,16 @@ static struct s5h1411_config dvico_s5h1411_config = {
         .mpeg_timing   = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
 };
 
+static struct s5h1411_config hcw_s5h1411_config = {
+        .output_mode   = S5H1411_SERIAL_OUTPUT,
+        .gpio          = S5H1411_GPIO_OFF,
+        .vsb_if        = S5H1411_IF_44000,
+        .qam_if        = S5H1411_IF_4000,
+        .inversion     = S5H1411_INVERSION_ON,
+        .status_mode   = S5H1411_DEMODLOCKING,
+        .mpeg_timing   = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
+};
+
 static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
         .i2c_address      = 0x61,
         .if_khz           = 5380,
@@ -224,6 +251,32 @@ static struct tda18271_config hauppauge_hvr1200_tuner_config = {
         .gate    = TDA18271_GATE_ANALOG,
 };
 
+static struct tda18271_config hauppauge_hvr1210_tuner_config = {
+        .gate    = TDA18271_GATE_DIGITAL,
+};
+
+static struct tda18271_std_map hauppauge_hvr127x_std_map = {
+        .atsc_6   = { .if_freq = 3250, .agc_mode = 3, .std = 4,
+                      .if_lvl = 1, .rfagc_top = 0x58 },
+        .qam_6    = { .if_freq = 4000, .agc_mode = 3, .std = 5,
+                      .if_lvl = 1, .rfagc_top = 0x58 },
+};
+
+static struct tda18271_config hauppauge_hvr127x_config = {
+        .std_map = &hauppauge_hvr127x_std_map,
+};
+
+static struct lgdt3305_config hauppauge_lgdt3305_config = {
+        .i2c_addr           = 0x0e,
+        .mpeg_mode          = LGDT3305_MPEG_SERIAL,
+        .tpclk_edge         = LGDT3305_TPCLK_FALLING_EDGE,
+        .tpvalid_polarity   = LGDT3305_TP_VALID_HIGH,
+        .deny_i2c_rptr      = 1,
+        .spectral_inversion = 1,
+        .qam_if_khz         = 4000,
+        .vsb_if_khz         = 3250,
+};
+
 static struct dibx000_agc_config xc3028_agc_config = {
         BAND_VHF | BAND_UHF,    /* band_caps */
 
@@ -368,10 +421,29 @@ static struct cx24116_config dvbworld_cx24116_config = {
         .demod_address = 0x05,
 };
 
+static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
+        .prod = LGS8GXX_PROD_LGS8GL5,
+        .demod_address = 0x19,
+        .serial_ts = 0,
+        .ts_clk_pol = 1,
+        .ts_clk_gated = 1,
+        .if_clk_freq = 30400, /* 30.4 MHz */
+        .if_freq = 5380, /* 5.38 MHz */
+        .if_neg_center = 1,
+        .ext_adc = 0,
+        .adc_signed = 0,
+        .if_neg_edge = 0,
+};
+
+static struct xc5000_config mygica_x8506_xc5000_config = {
+        .i2c_address = 0x61,
+        .if_khz = 5380,
+};
+
 static int dvb_register(struct cx23885_tsport *port)
 {
         struct cx23885_dev *dev = port->dev;
-        struct cx23885_i2c *i2c_bus = NULL;
+        struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
         struct videobuf_dvb_frontend *fe0;
         int ret;
 
@@ -396,6 +468,29 @@ static int dvb_register(struct cx23885_tsport *port)
                                    &hauppauge_generic_tunerconfig, 0);
                 }
                 break;
+        case CX23885_BOARD_HAUPPAUGE_HVR1270:
+        case CX23885_BOARD_HAUPPAUGE_HVR1275:
+                i2c_bus = &dev->i2c_bus[0];
+                fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
+                                               &hauppauge_lgdt3305_config,
+                                               &i2c_bus->i2c_adap);
+                if (fe0->dvb.frontend != NULL) {
+                        dvb_attach(tda18271_attach, fe0->dvb.frontend,
+                                   0x60, &dev->i2c_bus[1].i2c_adap,
+                                   &hauppauge_hvr127x_config);
+                }
+                break;
+        case CX23885_BOARD_HAUPPAUGE_HVR1255:
+                i2c_bus = &dev->i2c_bus[0];
+                fe0->dvb.frontend = dvb_attach(s5h1411_attach,
+                                               &hcw_s5h1411_config,
+                                               &i2c_bus->i2c_adap);
+                if (fe0->dvb.frontend != NULL) {
+                        dvb_attach(tda18271_attach, fe0->dvb.frontend,
+                                   0x60, &dev->i2c_bus[1].i2c_adap,
+                                   &hauppauge_tda18271_config);
+                }
+                break;
         case CX23885_BOARD_HAUPPAUGE_HVR1800:
                 i2c_bus = &dev->i2c_bus[0];
                 switch (alt_tuner) {
@@ -496,6 +591,17 @@ static int dvb_register(struct cx23885_tsport *port)
                                 &hauppauge_hvr1200_tuner_config);
                 }
                 break;
+        case CX23885_BOARD_HAUPPAUGE_HVR1210:
+                i2c_bus = &dev->i2c_bus[0];
+                fe0->dvb.frontend = dvb_attach(tda10048_attach,
+                        &hauppauge_hvr1210_config,
+                        &i2c_bus->i2c_adap);
+                if (fe0->dvb.frontend != NULL) {
+                        dvb_attach(tda18271_attach, fe0->dvb.frontend,
+                                0x60, &dev->i2c_bus[1].i2c_adap,
+                                &hauppauge_hvr1210_tuner_config);
+                }
+                break;
         case CX23885_BOARD_HAUPPAUGE_HVR1400:
                 i2c_bus = &dev->i2c_bus[0];
                 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
@@ -659,6 +765,19 @@ static int dvb_register(struct cx23885_tsport *port)
                         break;
                 }
                 break;
+        case CX23885_BOARD_MYGICA_X8506:
+                i2c_bus = &dev->i2c_bus[0];
+                i2c_bus2 = &dev->i2c_bus[1];
+                fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
+                        &mygica_x8506_lgs8gl5_config,
+                        &i2c_bus->i2c_adap);
+                if (fe0->dvb.frontend != NULL) {
+                        dvb_attach(xc5000_attach,
+                                fe0->dvb.frontend,
+                                &i2c_bus2->i2c_adap,
+                                &mygica_x8506_xc5000_config);
+                }
+                break;
         default:
                 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
                         " isn't supported yet\n",
diff --git a/drivers/media/video/cx23885/cx23885-i2c.c b/drivers/media/video/cx23885/cx23885-i2c.c
index 3421bd12056a..384dec34134f 100644
--- a/drivers/media/video/cx23885/cx23885-i2c.c
+++ b/drivers/media/video/cx23885/cx23885-i2c.c
@@ -357,6 +357,18 @@ int cx23885_i2c_register(struct cx23885_i2c *bus)
                 printk(KERN_WARNING "%s: i2c bus %d register FAILED\n",
                         dev->name, bus->nr);
 
+        /* Instantiate the IR receiver device, if present */
+        if (0 == bus->i2c_rc) {
+                struct i2c_board_info info;
+                const unsigned short addr_list[] = {
+                        0x6b, I2C_CLIENT_END
+                };
+
+                memset(&info, 0, sizeof(struct i2c_board_info));
+                strlcpy(info.type, "ir_video", I2C_NAME_SIZE);
+                i2c_new_probed_device(&bus->i2c_adap, &info, addr_list);
+        }
+
         return bus->i2c_rc;
 }
 
diff --git a/drivers/media/video/cx23885/cx23885-video.c b/drivers/media/video/cx23885/cx23885-video.c
index 68068c6d0987..66bbd2e71105 100644
--- a/drivers/media/video/cx23885/cx23885-video.c
+++ b/drivers/media/video/cx23885/cx23885-video.c
@@ -796,6 +796,7 @@ static unsigned int video_poll(struct file *file,
 {
         struct cx23885_fh *fh = file->private_data;
         struct cx23885_buffer *buf;
+        unsigned int rc = POLLERR;
 
         if (V4L2_BUF_TYPE_VBI_CAPTURE == fh->type) {
                 if (!res_get(fh->dev, fh, RESOURCE_VBI))
@@ -803,23 +804,28 @@ static unsigned int video_poll(struct file *file,
                 return videobuf_poll_stream(file, &fh->vbiq, wait);
         }
 
+        mutex_lock(&fh->vidq.vb_lock);
         if (res_check(fh, RESOURCE_VIDEO)) {
                 /* streaming capture */
                 if (list_empty(&fh->vidq.stream))
-                        return POLLERR;
+                        goto done;
                 buf = list_entry(fh->vidq.stream.next,
                         struct cx23885_buffer, vb.stream);
         } else {
                 /* read() capture */
                 buf = (struct cx23885_buffer *)fh->vidq.read_buf;
                 if (NULL == buf)
-                        return POLLERR;
+                        goto done;
         }
         poll_wait(file, &buf->vb.done, wait);
         if (buf->vb.state == VIDEOBUF_DONE ||
             buf->vb.state == VIDEOBUF_ERROR)
-                return POLLIN|POLLRDNORM;
-        return 0;
+                rc =  POLLIN|POLLRDNORM;
+        else
+                rc = 0;
+done:
+        mutex_unlock(&fh->vidq.vb_lock);
+        return rc;
 }
 
 static int video_release(struct file *file)
diff --git a/drivers/media/video/cx23885/cx23885.h b/drivers/media/video/cx23885/cx23885.h
index 85642831ea8e..1a2ac518a3f1 100644
--- a/drivers/media/video/cx23885/cx23885.h
+++ b/drivers/media/video/cx23885/cx23885.h
@@ -71,6 +71,22 @@
 #define CX23885_BOARD_TEVII_S470               15
 #define CX23885_BOARD_DVBWORLD_2005            16
 #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI      17
+#define CX23885_BOARD_HAUPPAUGE_HVR1270        18
+#define CX23885_BOARD_HAUPPAUGE_HVR1275        19
+#define CX23885_BOARD_HAUPPAUGE_HVR1255        20
+#define CX23885_BOARD_HAUPPAUGE_HVR1210        21
+#define CX23885_BOARD_MYGICA_X8506             22
+
+#define GPIO_0 0x00000001
+#define GPIO_1 0x00000002
+#define GPIO_2 0x00000004
+#define GPIO_3 0x00000008
+#define GPIO_4 0x00000010
+#define GPIO_5 0x00000020
+#define GPIO_6 0x00000040
+#define GPIO_7 0x00000080
+#define GPIO_8 0x00000100
+#define GPIO_9 0x00000200
 
 /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
 #define CX23885_NORMS (\
@@ -422,6 +438,11 @@ extern int cx23885_restart_queue(struct cx23885_tsport *port,
 extern void cx23885_wakeup(struct cx23885_tsport *port,
                            struct cx23885_dmaqueue *q, u32 count);
 
+extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
+extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
+extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
+        int asoutput);
+
 
 /* ----------------------------------------------------------- */
 /* cx23885-cards.c                                             */
diff --git a/drivers/media/video/cx88/Makefile b/drivers/media/video/cx88/Makefile
index b06b1275a9ec..5b7e26761f0a 100644
--- a/drivers/media/video/cx88/Makefile
+++ b/drivers/media/video/cx88/Makefile
@@ -1,5 +1,5 @@
 cx88xx-objs     := cx88-cards.o cx88-core.o cx88-i2c.o cx88-tvaudio.o \
-                   cx88-input.o
+                   cx88-dsp.o cx88-input.o
 cx8800-objs     := cx88-video.o cx88-vbi.o
 cx8802-objs     := cx88-mpeg.o
 
diff --git a/drivers/media/video/cx88/cx88-alsa.c b/drivers/media/video/cx88/cx88-alsa.c
index 0ccdf36626e3..5a67445dd6ed 100644
--- a/drivers/media/video/cx88/cx88-alsa.c
+++ b/drivers/media/video/cx88/cx88-alsa.c
@@ -871,7 +871,7 @@ static struct pci_driver cx88_audio_pci_driver = {
         .name     = "cx88_audio",
         .id_table = cx88_audio_pci_tbl,
         .probe    = cx88_audio_initdev,
-        .remove   = cx88_audio_finidev,
+        .remove   = __devexit_p(cx88_audio_finidev),
 };
 
 /****************************************************************************
@@ -881,7 +881,7 @@ static struct pci_driver cx88_audio_pci_driver = {
 /*
  * module init
  */
-static int cx88_audio_init(void)
+static int __init cx88_audio_init(void)
 {
         printk(KERN_INFO "cx2388x alsa driver version %d.%d.%d loaded\n",
                (CX88_VERSION_CODE >> 16) & 0xff,
@@ -897,9 +897,8 @@ static int cx88_audio_init(void)
 /*
  * module remove
  */
-static void cx88_audio_fini(void)
+static void __exit cx88_audio_fini(void)
 {
-
         pci_unregister_driver(&cx88_audio_pci_driver);
 }
 
diff --git a/drivers/media/video/cx88/cx88-cards.c b/drivers/media/video/cx88/cx88-cards.c
index 6bbbfc66bb4b..94b7a52629d0 100644
--- a/drivers/media/video/cx88/cx88-cards.c
+++ b/drivers/media/video/cx88/cx88-cards.c
@@ -1969,6 +1969,54 @@ static const struct cx88_board cx88_boards[] = {
                 },
                 .mpeg           = CX88_MPEG_DVB,
         },
+        [CX88_BOARD_HAUPPAUGE_IRONLY] = {
+                .name           = "Hauppauge WinTV-IR Only",
+                .tuner_type     = UNSET,
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+        },
+        [CX88_BOARD_WINFAST_DTV1800H] = {
+                .name           = "Leadtek WinFast DTV1800 Hybrid",
+                .tuner_type     = TUNER_XC2028,
+                .radio_type     = TUNER_XC2028,
+                .tuner_addr     = 0x61,
+                .radio_addr     = 0x61,
+                /*
+                 * GPIO setting
+                 *
+                 *  2: mute (0=off,1=on)
+                 * 12: tuner reset pin
+                 * 13: audio source (0=tuner audio,1=line in)
+                 * 14: FM (0=on,1=off ???)
+                 */
+                .input          = {{
+                        .type   = CX88_VMUX_TELEVISION,
+                        .vmux   = 0,
+                        .gpio0  = 0x0400,       /* pin 2 = 0 */
+                        .gpio1  = 0x6040,       /* pin 13 = 0, pin 14 = 1 */
+                        .gpio2  = 0x0000,
+                }, {
+                        .type   = CX88_VMUX_COMPOSITE1,
+                        .vmux   = 1,
+                        .gpio0  = 0x0400,       /* pin 2 = 0 */
+                        .gpio1  = 0x6060,       /* pin 13 = 1, pin 14 = 1 */
+                        .gpio2  = 0x0000,
+                }, {
+                        .type   = CX88_VMUX_SVIDEO,
+                        .vmux   = 2,
+                        .gpio0  = 0x0400,       /* pin 2 = 0 */
+                        .gpio1  = 0x6060,       /* pin 13 = 1, pin 14 = 1 */
+                        .gpio2  = 0x0000,
+                } },
+                .radio = {
+                        .type   = CX88_RADIO,
+                        .gpio0  = 0x0400,       /* pin 2 = 0 */
+                        .gpio1  = 0x6000,       /* pin 13 = 0, pin 14 = 0 */
+                        .gpio2  = 0x0000,
+                },
+                .mpeg           = CX88_MPEG_DVB,
+        },
 };
 
 /* ------------------------------------------------------------------ */
@@ -2382,6 +2430,14 @@ static const struct cx88_subid cx88_subids[] = {
                 .subvendor = 0x153b,
                 .subdevice = 0x1177,
                 .card      = CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII,
+        }, {
+                .subvendor = 0x0070,
+                .subdevice = 0x9290,
+                .card      = CX88_BOARD_HAUPPAUGE_IRONLY,
+        }, {
+                .subvendor = 0x107d,
+                .subdevice = 0x6654,
+                .card      = CX88_BOARD_WINFAST_DTV1800H,
         },
 };
 
@@ -2448,6 +2504,7 @@ static void hauppauge_eeprom(struct cx88_core *core, u8 *eeprom_data)
         case 90500: /* Nova-T-PCI (oem) */
         case 90501: /* Nova-T-PCI (oem/IR) */
         case 92000: /* Nova-SE2 (OEM, No Video or IR) */
+        case 92900: /* WinTV-IROnly (No analog or digital Video inputs) */
         case 94009: /* WinTV-HVR1100 (Video and IR Retail) */
         case 94501: /* WinTV-HVR1100 (Video and IR OEM) */
         case 96009: /* WinTV-HVR1300 (PAL Video, MPEG Video and IR RX) */
@@ -2579,6 +2636,23 @@ static int cx88_xc3028_geniatech_tuner_callback(struct cx88_core *core,
         return -EINVAL;
 }
 
+static int cx88_xc3028_winfast1800h_callback(struct cx88_core *core,
+                                             int command, int arg)
+{
+        switch (command) {
+        case XC2028_TUNER_RESET:
+                /* GPIO 12 (xc3028 tuner reset) */
+                cx_set(MO_GP1_IO, 0x1010);
+                mdelay(50);
+                cx_clear(MO_GP1_IO, 0x10);
+                mdelay(50);
+                cx_set(MO_GP1_IO, 0x10);
+                mdelay(50);
+                return 0;
+        }
+        return -EINVAL;
+}
+
 /* ------------------------------------------------------------------- */
 /* some Divco specific stuff                                           */
 static int cx88_pv_8000gt_callback(struct cx88_core *core,
@@ -2651,6 +2725,8 @@ static int cx88_xc2028_tuner_callback(struct cx88_core *core,
         case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
         case CX88_BOARD_DVICO_FUSIONHDTV_5_PCI_NANO:
                 return cx88_dvico_xc2028_callback(core, command, arg);
+        case CX88_BOARD_WINFAST_DTV1800H:
+                return cx88_xc3028_winfast1800h_callback(core, command, arg);
         }
 
         switch (command) {
@@ -2690,10 +2766,22 @@ static int cx88_xc5000_tuner_callback(struct cx88_core *core,
         switch (core->boardnr) {
         case CX88_BOARD_PINNACLE_PCTV_HD_800i:
                 if (command == 0) { /* This is the reset command from xc5000 */
-                        /* Reset XC5000 tuner via SYS_RSTO_pin */
-                        cx_write(MO_SRST_IO, 0);
-                        msleep(10);
-                        cx_write(MO_SRST_IO, 1);
+
+                        /* djh - According to the engineer at PCTV Systems,
+                           the xc5000 reset pin is supposed to be on GPIO12.
+                           However, despite three nights of effort, pulling
+                           that GPIO low didn't reset the xc5000.  While
+                           pulling MO_SRST_IO low does reset the xc5000, this
+                           also resets in the s5h1409 being reset as well.
+                           This causes tuning to always fail since the internal
+                           state of the s5h1409 does not match the driver's
+                           state.  Given that the only two conditions in which
+                           the driver performs a reset is during firmware load
+                           and powering down the chip, I am taking out the
+                           reset.  We know that the chip is being reset
+                           when the cx88 comes online, and not being able to
+                           do power management for this board is worse than
+                           not having any tuning at all. */
                         return 0;
                 } else {
                         err_printk(core, "xc5000: unknown tuner "
@@ -2825,6 +2913,16 @@ static void cx88_card_setup_pre_i2c(struct cx88_core *core)
                 cx_set(MO_GP0_IO, 0x00000080); /* 702 out of reset */
                 udelay(1000);
                 break;
+
+        case CX88_BOARD_WINFAST_DTV1800H:
+                /* GPIO 12 (xc3028 tuner reset) */
+                cx_set(MO_GP1_IO, 0x1010);
+                mdelay(50);
+                cx_clear(MO_GP1_IO, 0x10);
+                mdelay(50);
+                cx_set(MO_GP1_IO, 0x10);
+                mdelay(50);
+                break;
         }
 }
 
@@ -2845,6 +2943,7 @@ void cx88_setup_xc3028(struct cx88_core *core, struct xc2028_ctrl *ctl)
                         core->i2c_algo.udelay = 16;
                 break;
         case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PRO:
+        case CX88_BOARD_WINFAST_DTV1800H:
                 ctl->demod = XC3028_FE_ZARLINK456;
                 break;
         case CX88_BOARD_KWORLD_ATSC_120:
@@ -2907,6 +3006,7 @@ static void cx88_card_setup(struct cx88_core *core)
         case CX88_BOARD_HAUPPAUGE_HVR1300:
         case CX88_BOARD_HAUPPAUGE_HVR4000:
         case CX88_BOARD_HAUPPAUGE_HVR4000LITE:
+        case CX88_BOARD_HAUPPAUGE_IRONLY:
                 if (0 == core->i2c_rc)
                         hauppauge_eeprom(core, eeprom);
                 break;
diff --git a/drivers/media/video/cx88/cx88-core.c b/drivers/media/video/cx88/cx88-core.c
index 0e149b22bd19..cf634606ba9a 100644
--- a/drivers/media/video/cx88/cx88-core.c
+++ b/drivers/media/video/cx88/cx88-core.c
@@ -231,7 +231,7 @@ cx88_free_buffer(struct videobuf_queue *q, struct cx88_buffer *buf)
  * can use the whole SDRAM for the DMA fifos.  To simplify things, we
  * use a static memory layout.  That surely will waste memory in case
  * we don't use all DMA channels at the same time (which will be the
- * case most of the time).  But that still gives us enougth FIFO space
+ * case most of the time).  But that still gives us enough FIFO space
  * to be able to deal with insane long pci latencies ...
  *
  * FIFO space allocations:
@@ -241,6 +241,7 @@ cx88_free_buffer(struct videobuf_queue *q, struct cx88_buffer *buf)
  *    channel  24    (vbi)      -  4.0k
  *    channels 25+26 (audio)    -  4.0k
  *    channel  28    (mpeg)     -  4.0k
+ *    channel  27    (audio rds)-  3.0k
  *    TOTAL                     = 29.0k
  *
  * Every channel has 160 bytes control data (64 bytes instruction
@@ -337,6 +338,18 @@ struct sram_channel cx88_sram_channels[] = {
                 .cnt1_reg   = MO_DMA28_CNT1,
                 .cnt2_reg   = MO_DMA28_CNT2,
         },
+        [SRAM_CH27] = {
+                .name       = "audio rds",
+                .cmds_start = 0x1801C0,
+                .ctrl_start = 0x180860,
+                .cdt        = 0x180860 + 64,
+                .fifo_start = 0x187400,
+                .fifo_size  = 0x000C00,
+                .ptr1_reg   = MO_DMA27_PTR1,
+                .ptr2_reg   = MO_DMA27_PTR2,
+                .cnt1_reg   = MO_DMA27_CNT1,
+                .cnt2_reg   = MO_DMA27_CNT2,
+        },
 };
 
 int cx88_sram_channel_setup(struct cx88_core *core,
@@ -598,6 +611,7 @@ int cx88_reset(struct cx88_core *core)
         cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], 128, 0);
         cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], 128, 0);
         cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28], 188*4, 0);
+        cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27], 128, 0);
 
         /* misc init ... */
         cx_write(MO_INPUT_FORMAT, ((1 << 13) |   // agc enable
@@ -796,6 +810,8 @@ int cx88_start_audio_dma(struct cx88_core *core)
         /* constant 128 made buzz in analog Nicam-stereo for bigger fifo_size */
         int bpl = cx88_sram_channels[SRAM_CH25].fifo_size/4;
 
+        int rds_bpl = cx88_sram_channels[SRAM_CH27].fifo_size/AUD_RDS_LINES;
+
         /* If downstream RISC is enabled, bail out; ALSA is managing DMA */
         if (cx_read(MO_AUD_DMACNTRL) & 0x10)
                 return 0;
@@ -803,12 +819,14 @@ int cx88_start_audio_dma(struct cx88_core *core)
         /* setup fifo + format */
         cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], bpl, 0);
         cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], bpl, 0);
+        cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27],
+                                rds_bpl, 0);
 
         cx_write(MO_AUDD_LNGTH, bpl); /* fifo bpl size */
-        cx_write(MO_AUDR_LNGTH, bpl); /* fifo bpl size */
+        cx_write(MO_AUDR_LNGTH, rds_bpl); /* fifo bpl size */
 
-        /* start dma */
-        cx_write(MO_AUD_DMACNTRL, 0x0003); /* Up and Down fifo enable */
+        /* enable Up, Down and Audio RDS fifo */
+        cx_write(MO_AUD_DMACNTRL, 0x0007);
 
         return 0;
 }
@@ -1010,7 +1028,6 @@ struct video_device *cx88_vdev_init(struct cx88_core *core,
         if (NULL == vfd)
                 return NULL;
         *vfd = *template;
-        vfd->minor   = -1;
         vfd->v4l2_dev = &core->v4l2_dev;
         vfd->parent = &pci->dev;
         vfd->release = video_device_release;
diff --git a/drivers/media/video/cx88/cx88-dsp.c b/drivers/media/video/cx88/cx88-dsp.c
new file mode 100644
index 000000000000..3e5eaf3fe2a6
--- /dev/null
+++ b/drivers/media/video/cx88/cx88-dsp.c
@@ -0,0 +1,312 @@
+/*
+ *
+ *  Stereo and SAP detection for cx88
+ *
+ *  Copyright (c) 2009 Marton Balint <cus@fazekas.hu>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/jiffies.h>
+#include <asm/div64.h>
+
+#include "cx88.h"
+#include "cx88-reg.h"
+
+#define INT_PI                  ((s32)(3.141592653589 * 32768.0))
+
+#define compat_remainder(a, b) \
+         ((float)(((s32)((a)*100))%((s32)((b)*100)))/100.0)
+
+#define baseband_freq(carrier, srate, tone) ((s32)( \
+         (compat_remainder(carrier + tone, srate)) / srate * 2 * INT_PI))
+
+/* We calculate the baseband frequencies of the carrier and the pilot tones
+ * based on the the sampling rate of the audio rds fifo. */
+
+#define FREQ_A2_CARRIER         baseband_freq(54687.5, 2689.36, 0.0)
+#define FREQ_A2_DUAL            baseband_freq(54687.5, 2689.36, 274.1)
+#define FREQ_A2_STEREO          baseband_freq(54687.5, 2689.36, 117.5)
+
+/* The frequencies below are from the reference driver. They probably need
+ * further adjustments, because they are not tested at all. You may even need
+ * to play a bit with the registers of the chip to select the proper signal
+ * for the input of the audio rds fifo, and measure it's sampling rate to
+ * calculate the proper baseband frequencies... */
+
+#define FREQ_A2M_CARRIER        ((s32)(2.114516 * 32768.0))
+#define FREQ_A2M_DUAL           ((s32)(2.754916 * 32768.0))
+#define FREQ_A2M_STEREO         ((s32)(2.462326 * 32768.0))
+
+#define FREQ_EIAJ_CARRIER       ((s32)(1.963495 * 32768.0)) /* 5pi/8  */
+#define FREQ_EIAJ_DUAL          ((s32)(2.562118 * 32768.0))
+#define FREQ_EIAJ_STEREO        ((s32)(2.601053 * 32768.0))
+
+#define FREQ_BTSC_DUAL          ((s32)(1.963495 * 32768.0)) /* 5pi/8  */
+#define FREQ_BTSC_DUAL_REF      ((s32)(1.374446 * 32768.0)) /* 7pi/16 */
+
+#define FREQ_BTSC_SAP           ((s32)(2.471532 * 32768.0))
+#define FREQ_BTSC_SAP_REF       ((s32)(1.730072 * 32768.0))
+
+/* The spectrum of the signal should be empty between these frequencies. */
+#define FREQ_NOISE_START        ((s32)(0.100000 * 32768.0))
+#define FREQ_NOISE_END          ((s32)(1.200000 * 32768.0))
+
+static unsigned int dsp_debug;
+module_param(dsp_debug, int, 0644);
+MODULE_PARM_DESC(dsp_debug, "enable audio dsp debug messages");
+
+#define dprintk(level, fmt, arg...)     if (dsp_debug >= level) \
+        printk(KERN_DEBUG "%s/0: " fmt, core->name , ## arg)
+
+static s32 int_cos(u32 x)
+{
+        u32 t2, t4, t6, t8;
+        s32 ret;
+        u16 period = x / INT_PI;
+        if (period % 2)
+                return -int_cos(x - INT_PI);
+        x = x % INT_PI;
+        if (x > INT_PI/2)
+                return -int_cos(INT_PI/2 - (x % (INT_PI/2)));
+        /* Now x is between 0 and INT_PI/2.
+         * To calculate cos(x) we use it's Taylor polinom. */
+        t2 = x*x/32768/2;
+        t4 = t2*x/32768*x/32768/3/4;
+        t6 = t4*x/32768*x/32768/5/6;
+        t8 = t6*x/32768*x/32768/7/8;
+        ret = 32768-t2+t4-t6+t8;
+        return ret;
+}
+
+static u32 int_goertzel(s16 x[], u32 N, u32 freq)
+{
+        /* We use the Goertzel algorithm to determine the power of the
+         * given frequency in the signal */
+        s32 s_prev = 0;
+        s32 s_prev2 = 0;
+        s32 coeff = 2*int_cos(freq);
+        u32 i;
+
+        u64 tmp;
+        u32 divisor;
+
+        for (i = 0; i < N; i++) {
+                s32 s = x[i] + ((s64)coeff*s_prev/32768) - s_prev2;
+                s_prev2 = s_prev;
+                s_prev = s;
+        }
+
+        tmp = (s64)s_prev2 * s_prev2 + (s64)s_prev * s_prev -
+                      (s64)coeff * s_prev2 * s_prev / 32768;
+
+        /* XXX: N must be low enough so that N*N fits in s32.
+         * Else we need two divisions. */
+        divisor = N * N;
+        do_div(tmp, divisor);
+
+        return (u32) tmp;
+}
+
+static u32 freq_magnitude(s16 x[], u32 N, u32 freq)
+{
+        u32 sum = int_goertzel(x, N, freq);
+        return (u32)int_sqrt(sum);
+}
+
+static u32 noise_magnitude(s16 x[], u32 N, u32 freq_start, u32 freq_end)
+{
+        int i;
+        u32 sum = 0;
+        u32 freq_step;
+        int samples = 5;
+
+        if (N > 192) {
+                /* The last 192 samples are enough for noise detection */
+                x += (N-192);
+                N = 192;
+        }
+
+        freq_step = (freq_end - freq_start) / (samples - 1);
+
+        for (i = 0; i < samples; i++) {
+                sum += int_goertzel(x, N, freq_start);
+                freq_start += freq_step;
+        }
+
+        return (u32)int_sqrt(sum / samples);
+}
+
+static s32 detect_a2_a2m_eiaj(struct cx88_core *core, s16 x[], u32 N)
+{
+        s32 carrier, stereo, dual, noise;
+        s32 carrier_freq, stereo_freq, dual_freq;
+        s32 ret;
+
+        switch (core->tvaudio) {
+        case WW_BG:
+        case WW_DK:
+                carrier_freq = FREQ_A2_CARRIER;
+                stereo_freq = FREQ_A2_STEREO;
+                dual_freq = FREQ_A2_DUAL;
+                break;
+        case WW_M:
+                carrier_freq = FREQ_A2M_CARRIER;
+                stereo_freq = FREQ_A2M_STEREO;
+                dual_freq = FREQ_A2M_DUAL;
+                break;
+        case WW_EIAJ:
+                carrier_freq = FREQ_EIAJ_CARRIER;
+                stereo_freq = FREQ_EIAJ_STEREO;
+                dual_freq = FREQ_EIAJ_DUAL;
+                break;
+        default:
+                printk(KERN_WARNING "%s/0: unsupported audio mode %d for %s\n",
+                       core->name, core->tvaudio, __func__);
+                return UNSET;
+        }
+
+        carrier = freq_magnitude(x, N, carrier_freq);
+        stereo  = freq_magnitude(x, N, stereo_freq);
+        dual    = freq_magnitude(x, N, dual_freq);
+        noise   = noise_magnitude(x, N, FREQ_NOISE_START, FREQ_NOISE_END);
+
+        dprintk(1, "detect a2/a2m/eiaj: carrier=%d, stereo=%d, dual=%d, "
+                   "noise=%d\n", carrier, stereo, dual, noise);
+
+        if (stereo > dual)
+                ret = V4L2_TUNER_SUB_STEREO;
+        else
+                ret = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
+
+        if (core->tvaudio == WW_EIAJ) {
+                /* EIAJ checks may need adjustments */
+                if ((carrier > max(stereo, dual)*2) &&
+                    (carrier < max(stereo, dual)*6) &&
+                    (carrier > 20 && carrier < 200) &&
+                    (max(stereo, dual) > min(stereo, dual))) {
+                        /* For EIAJ the carrier is always present,
+                           so we probably don't need noise detection */
+                        return ret;
+                }
+        } else {
+                if ((carrier > max(stereo, dual)*2) &&
+                    (carrier < max(stereo, dual)*8) &&
+                    (carrier > 20 && carrier < 200) &&
+                    (noise < 10) &&
+                    (max(stereo, dual) > min(stereo, dual)*2)) {
+                        return ret;
+                }
+        }
+        return V4L2_TUNER_SUB_MONO;
+}
+
+static s32 detect_btsc(struct cx88_core *core, s16 x[], u32 N)
+{
+        s32 sap_ref = freq_magnitude(x, N, FREQ_BTSC_SAP_REF);
+        s32 sap = freq_magnitude(x, N, FREQ_BTSC_SAP);
+        s32 dual_ref = freq_magnitude(x, N, FREQ_BTSC_DUAL_REF);
+        s32 dual = freq_magnitude(x, N, FREQ_BTSC_DUAL);
+        dprintk(1, "detect btsc: dual_ref=%d, dual=%d, sap_ref=%d, sap=%d"
+                   "\n", dual_ref, dual, sap_ref, sap);
+        /* FIXME: Currently not supported */
+        return UNSET;
+}
+
+static s16 *read_rds_samples(struct cx88_core *core, u32 *N)
+{
+        struct sram_channel *srch = &cx88_sram_channels[SRAM_CH27];
+        s16 *samples;
+
+        unsigned int i;
+        unsigned int bpl = srch->fifo_size/AUD_RDS_LINES;
+        unsigned int spl = bpl/4;
+        unsigned int sample_count = spl*(AUD_RDS_LINES-1);
+
+        u32 current_address = cx_read(srch->ptr1_reg);
+        u32 offset = (current_address - srch->fifo_start + bpl);
+
+        dprintk(1, "read RDS samples: current_address=%08x (offset=%08x), "
+                "sample_count=%d, aud_intstat=%08x\n", current_address,
+                current_address - srch->fifo_start, sample_count,
+                cx_read(MO_AUD_INTSTAT));
+
+        samples = kmalloc(sizeof(s16)*sample_count, GFP_KERNEL);
+        if (!samples)
+                return NULL;
+
+        *N = sample_count;
+
+        for (i = 0; i < sample_count; i++)  {
+                offset = offset % (AUD_RDS_LINES*bpl);
+                samples[i] = cx_read(srch->fifo_start + offset);
+                offset += 4;
+        }
+
+        if (dsp_debug >= 2) {
+                dprintk(2, "RDS samples dump: ");
+                for (i = 0; i < sample_count; i++)
+                        printk("%hd ", samples[i]);
+                printk(".\n");
+        }
+
+        return samples;
+}
+
+s32 cx88_dsp_detect_stereo_sap(struct cx88_core *core)
+{
+        s16 *samples;
+        u32 N = 0;
+        s32 ret = UNSET;
+
+        /* If audio RDS fifo is disabled, we can't read the samples */
+        if (!(cx_read(MO_AUD_DMACNTRL) & 0x04))
+                return ret;
+        if (!(cx_read(AUD_CTL) & EN_FMRADIO_EN_RDS))
+                return ret;
+
+        /* Wait at least 500 ms after an audio standard change */
+        if (time_before(jiffies, core->last_change + msecs_to_jiffies(500)))
+                return ret;
+
+        samples = read_rds_samples(core, &N);
+
+        if (!samples)
+                return ret;
+
+        switch (core->tvaudio) {
+        case WW_BG:
+        case WW_DK:
+                ret = detect_a2_a2m_eiaj(core, samples, N);
+                break;
+        case WW_BTSC:
+                ret = detect_btsc(core, samples, N);
+                break;
+        }
+
+        kfree(samples);
+
+        if (UNSET != ret)
+                dprintk(1, "stereo/sap detection result:%s%s%s\n",
+                           (ret & V4L2_TUNER_SUB_MONO) ? " mono" : "",
+                           (ret & V4L2_TUNER_SUB_STEREO) ? " stereo" : "",
+                           (ret & V4L2_TUNER_SUB_LANG2) ? " dual" : "");
+
+        return ret;
+}
+EXPORT_SYMBOL(cx88_dsp_detect_stereo_sap);
+
diff --git a/drivers/media/video/cx88/cx88-dvb.c b/drivers/media/video/cx88/cx88-dvb.c
index 9389cf290c1b..c44e87600219 100644
--- a/drivers/media/video/cx88/cx88-dvb.c
+++ b/drivers/media/video/cx88/cx88-dvb.c
@@ -1014,6 +1014,7 @@ static int dvb_register(struct cx8802_dev *dev)
                 }
                 break;
          case CX88_BOARD_PINNACLE_HYBRID_PCTV:
+        case CX88_BOARD_WINFAST_DTV1800H:
                 fe0->dvb.frontend = dvb_attach(zl10353_attach,
                                                &cx88_pinnacle_hybrid_pctv,
                                                &core->i2c_adap);
diff --git a/drivers/media/video/cx88/cx88-i2c.c b/drivers/media/video/cx88/cx88-i2c.c
index 996b4ed5a4fc..ee1ca39db06a 100644
--- a/drivers/media/video/cx88/cx88-i2c.c
+++ b/drivers/media/video/cx88/cx88-i2c.c
@@ -180,6 +180,19 @@ int cx88_i2c_init(struct cx88_core *core, struct pci_dev *pci)
                         do_i2c_scan(core->name,&core->i2c_client);
         } else
                 printk("%s: i2c register FAILED\n", core->name);
+
+        /* Instantiate the IR receiver device, if present */
+        if (0 == core->i2c_rc) {
+                struct i2c_board_info info;
+                const unsigned short addr_list[] = {
+                        0x18, 0x6b, 0x71,
+                        I2C_CLIENT_END
+                };
+
+                memset(&info, 0, sizeof(struct i2c_board_info));
+                strlcpy(info.type, "ir_video", I2C_NAME_SIZE);
+                i2c_new_probed_device(&core->i2c_adap, &info, addr_list);
+        }
         return core->i2c_rc;
 }
 
diff --git a/drivers/media/video/cx88/cx88-input.c b/drivers/media/video/cx88/cx88-input.c
index ec05312a9b62..d91f5c51206d 100644
--- a/drivers/media/video/cx88/cx88-input.c
+++ b/drivers/media/video/cx88/cx88-input.c
@@ -91,6 +91,8 @@ static void cx88_ir_handle_key(struct cx88_IR *ir)
                 gpio=(gpio & 0x7fd) + (auxgpio & 0xef);
                 break;
         case CX88_BOARD_WINFAST_DTV1000:
+        case CX88_BOARD_WINFAST_DTV1800H:
+        case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL:
                 gpio = (gpio & 0x6ff) | ((cx_read(MO_GP1_IO) << 8) & 0x900);
                 auxgpio = gpio;
                 break;
@@ -217,11 +219,13 @@ int cx88_ir_init(struct cx88_core *core, struct pci_dev *pci)
         case CX88_BOARD_HAUPPAUGE_HVR4000LITE:
         case CX88_BOARD_PCHDTV_HD3000:
         case CX88_BOARD_PCHDTV_HD5500:
+        case CX88_BOARD_HAUPPAUGE_IRONLY:
                 ir_codes = ir_codes_hauppauge_new;
                 ir_type = IR_TYPE_RC5;
                 ir->sampling = 1;
                 break;
         case CX88_BOARD_WINFAST_DTV2000H:
+        case CX88_BOARD_WINFAST_DTV1800H:
                 ir_codes = ir_codes_winfast;
                 ir->gpio_addr = MO_GP0_IO;
                 ir->mask_keycode = 0x8f8;
@@ -230,6 +234,7 @@ int cx88_ir_init(struct cx88_core *core, struct pci_dev *pci)
                 break;
         case CX88_BOARD_WINFAST2000XP_EXPERT:
         case CX88_BOARD_WINFAST_DTV1000:
+        case CX88_BOARD_WINFAST_TV2000_XP_GLOBAL:
                 ir_codes = ir_codes_winfast;
                 ir->gpio_addr = MO_GP0_IO;
                 ir->mask_keycode = 0x8f8;
@@ -459,6 +464,7 @@ void cx88_ir_irq(struct cx88_core *core)
         case CX88_BOARD_HAUPPAUGE_HVR4000LITE:
         case CX88_BOARD_PCHDTV_HD3000:
         case CX88_BOARD_PCHDTV_HD5500:
+        case CX88_BOARD_HAUPPAUGE_IRONLY:
                 ircode = ir_decode_biphase(ir->samples, ir->scount, 5, 7);
                 ir_dprintk("biphase decoded: %x\n", ircode);
                 /*
diff --git a/drivers/media/video/cx88/cx88-tvaudio.c b/drivers/media/video/cx88/cx88-tvaudio.c
index 7dd506b987fe..e8316cf7f32f 100644
--- a/drivers/media/video/cx88/cx88-tvaudio.c
+++ b/drivers/media/video/cx88/cx88-tvaudio.c
@@ -163,6 +163,8 @@ static void set_audio_finish(struct cx88_core *core, u32 ctl)
         /* unmute */
         volume = cx_sread(SHADOW_AUD_VOL_CTL);
         cx_swrite(SHADOW_AUD_VOL_CTL, AUD_VOL_CTL, volume);
+
+        core->last_change = jiffies;
 }
 
 /* ----------------------------------------------------------- */
@@ -745,6 +747,7 @@ void cx88_set_tvaudio(struct cx88_core *core)
                 break;
         case WW_BG:
         case WW_DK:
+        case WW_M:
         case WW_I:
         case WW_L:
                 /* prepare all dsp registers */
@@ -756,6 +759,7 @@ void cx88_set_tvaudio(struct cx88_core *core)
                 if (0 == cx88_detect_nicam(core)) {
                         /* fall back to fm / am mono */
                         set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
+                        core->audiomode_current = V4L2_TUNER_MODE_MONO;
                         core->use_nicam = 0;
                 } else {
                         core->use_nicam = 1;
@@ -787,6 +791,7 @@ void cx88_set_tvaudio(struct cx88_core *core)
 void cx88_newstation(struct cx88_core *core)
 {
         core->audiomode_manual = UNSET;
+        core->last_change = jiffies;
 }
 
 void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
@@ -805,12 +810,50 @@ void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
                         aud_ctl_names[cx_read(AUD_CTL) & 63]);
         core->astat = reg;
 
-/* TODO
-        Reading from AUD_STATUS is not enough
-        for auto-detecting sap/dual-fm/nicam.
-        Add some code here later.
-*/
+        t->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_SAP |
+            V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
+        t->rxsubchans = UNSET;
+        t->audmode = V4L2_TUNER_MODE_MONO;
+
+        switch (mode) {
+        case 0:
+                t->audmode = V4L2_TUNER_MODE_STEREO;
+                break;
+        case 1:
+                t->audmode = V4L2_TUNER_MODE_LANG2;
+                break;
+        case 2:
+                t->audmode = V4L2_TUNER_MODE_MONO;
+                break;
+        case 3:
+                t->audmode = V4L2_TUNER_MODE_SAP;
+                break;
+        }
 
+        switch (core->tvaudio) {
+        case WW_BTSC:
+        case WW_BG:
+        case WW_DK:
+        case WW_M:
+        case WW_EIAJ:
+                if (!core->use_nicam) {
+                        t->rxsubchans = cx88_dsp_detect_stereo_sap(core);
+                        break;
+                }
+                break;
+        default:
+                /* nothing */
+                break;
+        }
+
+        /* If software stereo detection is not supported... */
+        if (UNSET == t->rxsubchans) {
+                t->rxsubchans = V4L2_TUNER_SUB_MONO;
+                /* If the hardware itself detected stereo, also return
+                   stereo as an available subchannel */
+                if (V4L2_TUNER_MODE_STEREO == t->audmode)
+                        t->rxsubchans |= V4L2_TUNER_SUB_STEREO;
+        }
         return;
 }
 
@@ -847,6 +890,7 @@ void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual)
                 break;
         case WW_BG:
         case WW_DK:
+        case WW_M:
         case WW_I:
         case WW_L:
                 if (1 == core->use_nicam) {
@@ -872,20 +916,18 @@ void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual)
                                 set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
                         } else {
                                 /* TODO: Add A2 autodection */
+                                mask = 0x3f;
                                 switch (mode) {
                                 case V4L2_TUNER_MODE_MONO:
                                 case V4L2_TUNER_MODE_LANG1:
-                                        set_audio_standard_A2(core,
-                                                              EN_A2_FORCE_MONO1);
+                                        ctl = EN_A2_FORCE_MONO1;
                                         break;
                                 case V4L2_TUNER_MODE_LANG2:
-                                        set_audio_standard_A2(core,
-                                                              EN_A2_FORCE_MONO2);
+                                        ctl = EN_A2_FORCE_MONO2;
                                         break;
                                 case V4L2_TUNER_MODE_STEREO:
                                 case V4L2_TUNER_MODE_LANG1_LANG2:
-                                        set_audio_standard_A2(core,
-                                                              EN_A2_FORCE_STEREO);
+                                        ctl = EN_A2_FORCE_STEREO;
                                         break;
                                 }
                         }
@@ -932,24 +974,39 @@ int cx88_audio_thread(void *data)
                         break;
                 try_to_freeze();
 
-                /* just monitor the audio status for now ... */
-                memset(&t, 0, sizeof(t));
-                cx88_get_stereo(core, &t);
-
-                if (UNSET != core->audiomode_manual)
-                        /* manually set, don't do anything. */
-                        continue;
-
-                /* monitor signal */
-                if (t.rxsubchans & V4L2_TUNER_SUB_STEREO)
-                        mode = V4L2_TUNER_MODE_STEREO;
-                else
-                        mode = V4L2_TUNER_MODE_MONO;
-                if (mode == core->audiomode_current)
-                        continue;
-
-                /* automatically switch to best available mode */
-                cx88_set_stereo(core, mode, 0);
+                switch (core->tvaudio) {
+                case WW_BG:
+                case WW_DK:
+                case WW_M:
+                case WW_I:
+                case WW_L:
+                        if (core->use_nicam)
+                                goto hw_autodetect;
+
+                        /* just monitor the audio status for now ... */
+                        memset(&t, 0, sizeof(t));
+                        cx88_get_stereo(core, &t);
+
+                        if (UNSET != core->audiomode_manual)
+                                /* manually set, don't do anything. */
+                                continue;
+
+                        /* monitor signal and set stereo if available */
+                        if (t.rxsubchans & V4L2_TUNER_SUB_STEREO)
+                                mode = V4L2_TUNER_MODE_STEREO;
+                        else
+                                mode = V4L2_TUNER_MODE_MONO;
+                        if (mode == core->audiomode_current)
+                                continue;
+                        /* automatically switch to best available mode */
+                        cx88_set_stereo(core, mode, 0);
+                        break;
+                default:
+hw_autodetect:
+                        /* stereo autodetection is supported by hardware so
+                           we don't need to do it manually. Do nothing. */
+                        break;
+                }
         }
 
         dprintk("cx88: tvaudio thread exiting\n");
diff --git a/drivers/media/video/cx88/cx88-video.c b/drivers/media/video/cx88/cx88-video.c
index b993d42fe73c..0ccac702bea4 100644
--- a/drivers/media/video/cx88/cx88-video.c
+++ b/drivers/media/video/cx88/cx88-video.c
@@ -869,6 +869,7 @@ video_poll(struct file *file, struct poll_table_struct *wait)
 {
         struct cx8800_fh *fh = file->private_data;
         struct cx88_buffer *buf;
+        unsigned int rc = POLLERR;
 
         if (V4L2_BUF_TYPE_VBI_CAPTURE == fh->type) {
                 if (!res_get(fh->dev,fh,RESOURCE_VBI))
@@ -876,22 +877,27 @@ video_poll(struct file *file, struct poll_table_struct *wait)
                 return videobuf_poll_stream(file, &fh->vbiq, wait);
         }
 
+        mutex_lock(&fh->vidq.vb_lock);
         if (res_check(fh,RESOURCE_VIDEO)) {
                 /* streaming capture */
                 if (list_empty(&fh->vidq.stream))
-                        return POLLERR;
+                        goto done;
                 buf = list_entry(fh->vidq.stream.next,struct cx88_buffer,vb.stream);
         } else {
                 /* read() capture */
                 buf = (struct cx88_buffer*)fh->vidq.read_buf;
                 if (NULL == buf)
-                        return POLLERR;
+                        goto done;
         }
         poll_wait(file, &buf->vb.done, wait);
         if (buf->vb.state == VIDEOBUF_DONE ||
             buf->vb.state == VIDEOBUF_ERROR)
-                return POLLIN|POLLRDNORM;
-        return 0;
+                rc = POLLIN|POLLRDNORM;
+        else
+                rc = 0;
+done:
+        mutex_unlock(&fh->vidq.vb_lock);
+        return rc;
 }
 
 static int video_release(struct file *file)
@@ -926,8 +932,10 @@ static int video_release(struct file *file)
         file->private_data = NULL;
         kfree(fh);
 
+        mutex_lock(&dev->core->lock);
         if(atomic_dec_and_test(&dev->core->users))
                 call_all(dev->core, tuner, s_standby);
+        mutex_unlock(&dev->core->lock);
 
         return 0;
 }
diff --git a/drivers/media/video/cx88/cx88.h b/drivers/media/video/cx88/cx88.h
index 7724d168fc04..9d83762163f5 100644
--- a/drivers/media/video/cx88/cx88.h
+++ b/drivers/media/video/cx88/cx88.h
@@ -65,6 +65,8 @@
 #define VBI_LINE_COUNT              17
 #define VBI_LINE_LENGTH           2048
 
+#define AUD_RDS_LINES                4
+
 /* need "shadow" registers for some write-only ones ... */
 #define SHADOW_AUD_VOL_CTL           1
 #define SHADOW_AUD_BAL_CTL           2
@@ -132,6 +134,7 @@ struct cx88_ctrl {
 #define SRAM_CH25 4   /* audio */
 #define SRAM_CH26 5
 #define SRAM_CH28 6   /* mpeg */
+#define SRAM_CH27 7   /* audio rds */
 /* more */
 
 struct sram_channel {
@@ -232,6 +235,8 @@ extern struct sram_channel cx88_sram_channels[];
 #define CX88_BOARD_TBS_8910                77
 #define CX88_BOARD_PROF_6200               78
 #define CX88_BOARD_TERRATEC_CINERGY_HT_PCI_MKII 79
+#define CX88_BOARD_HAUPPAUGE_IRONLY        80
+#define CX88_BOARD_WINFAST_DTV1800H        81
 
 enum cx88_itype {
         CX88_VMUX_COMPOSITE1 = 1,
@@ -350,6 +355,7 @@ struct cx88_core {
         u32                        input;
         u32                        astat;
         u32                        use_nicam;
+        unsigned long              last_change;
 
         /* IR remote control state */
         struct cx88_IR             *ir;
@@ -652,6 +658,7 @@ extern void cx88_setup_xc3028(struct cx88_core *core, struct xc2028_ctrl *ctl);
 #define WW_I2SPT         8
 #define WW_FM            9
 #define WW_I2SADC        10
+#define WW_M             11
 
 void cx88_set_tvaudio(struct cx88_core *core);
 void cx88_newstation(struct cx88_core *core);
@@ -665,6 +672,11 @@ struct cx8802_dev *cx8802_get_device(int minor);
 struct cx8802_driver * cx8802_get_driver(struct cx8802_dev *dev, enum cx88_board_type btype);
 
 /* ----------------------------------------------------------- */
+/* cx88-dsp.c                                                  */
+
+s32 cx88_dsp_detect_stereo_sap(struct cx88_core *core);
+
+/* ----------------------------------------------------------- */
 /* cx88-input.c                                                */
 
 int cx88_ir_init(struct cx88_core *core, struct pci_dev *pci);
diff --git a/drivers/media/video/dabusb.c b/drivers/media/video/dabusb.c
index ba3709bec3f0..ec2f45dde164 100644
--- a/drivers/media/video/dabusb.c
+++ b/drivers/media/video/dabusb.c
@@ -747,8 +747,14 @@ static const struct file_operations dabusb_fops =
         .release =      dabusb_release,
 };
 
+static char *dabusb_nodename(struct device *dev)
+{
+        return kasprintf(GFP_KERNEL, "usb/%s", dev_name(dev));
+}
+
 static struct usb_class_driver dabusb_class = {
         .name =         "dabusb%d",
+        .nodename =     dabusb_nodename,
         .fops =         &dabusb_fops,
         .minor_base =   DABUSB_MINOR,
 };
diff --git a/drivers/media/video/em28xx/em28xx-audio.c b/drivers/media/video/em28xx/em28xx-audio.c
index 0131322475bf..7bd8a70f0a0b 100644
--- a/drivers/media/video/em28xx/em28xx-audio.c
+++ b/drivers/media/video/em28xx/em28xx-audio.c
@@ -339,6 +339,11 @@ static int snd_em28xx_pcm_close(struct snd_pcm_substream *substream)
         mutex_lock(&dev->lock);
         dev->adev.users--;
         em28xx_audio_analog_set(dev);
+        if (substream->runtime->dma_area) {
+                dprintk("freeing\n");
+                vfree(substream->runtime->dma_area);
+                substream->runtime->dma_area = NULL;
+        }
         mutex_unlock(&dev->lock);
 
         return 0;
diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c
index 7c70738479dd..00cc791a9e44 100644
--- a/drivers/media/video/em28xx/em28xx-cards.c
+++ b/drivers/media/video/em28xx/em28xx-cards.c
@@ -49,6 +49,11 @@ static unsigned int disable_ir;
 module_param(disable_ir, int, 0444);
 MODULE_PARM_DESC(disable_ir, "disable infrared remote support");
 
+static unsigned int disable_usb_speed_check;
+module_param(disable_usb_speed_check, int, 0444);
+MODULE_PARM_DESC(disable_usb_speed_check,
+                 "override min bandwidth requirement of 480M bps");
+
 static unsigned int card[]     = {[0 ... (EM28XX_MAXBOARDS - 1)] = UNSET };
 module_param_array(card,  int, NULL, 0444);
 MODULE_PARM_DESC(card,     "card type");
@@ -104,6 +109,24 @@ static struct em28xx_reg_seq em2880_msi_digivox_ad_analog[] = {
 /* Board  - EM2870 Kworld 355u
    Analog - No input analog */
 
+/* Board - EM2882 Kworld 315U digital */
+static struct em28xx_reg_seq em2882_kworld_315u_digital[] = {
+        {EM28XX_R08_GPIO,       0xff,   0xff,           10},
+        {EM28XX_R08_GPIO,       0xfe,   0xff,           10},
+        {EM2880_R04_GPO,        0x04,   0xff,           10},
+        {EM2880_R04_GPO,        0x0c,   0xff,           10},
+        {EM28XX_R08_GPIO,       0x7e,   0xff,           10},
+        {  -1,                  -1,     -1,             -1},
+};
+
+static struct em28xx_reg_seq em2882_kworld_315u_tuner_gpio[] = {
+        {EM2880_R04_GPO,        0x08,   0xff,           10},
+        {EM2880_R04_GPO,        0x0c,   0xff,           10},
+        {EM2880_R04_GPO,        0x08,   0xff,           10},
+        {EM2880_R04_GPO,        0x0c,   0xff,           10},
+        {  -1,                  -1,     -1,             -1},
+};
+
 static struct em28xx_reg_seq kworld_330u_analog[] = {
         {EM28XX_R08_GPIO,       0x6d,   ~EM_GPIO_4,     10},
         {EM2880_R04_GPO,        0x00,   0xff,           10},
@@ -140,6 +163,16 @@ static struct em28xx_reg_seq compro_mute_gpio[] = {
         {  -1,                  -1,             -1,             -1},
 };
 
+/* Terratec AV350 */
+static struct em28xx_reg_seq terratec_av350_mute_gpio[] = {
+        {EM28XX_R08_GPIO,       0xff,   0x7f,           10},
+        {       -1,             -1,     -1,             -1},
+};
+
+static struct em28xx_reg_seq terratec_av350_unmute_gpio[] = {
+        {EM28XX_R08_GPIO,       0xff,   0xff,           10},
+        {       -1,             -1,     -1,             -1},
+};
 /*
  *  Board definitions
  */
@@ -992,16 +1025,17 @@ struct em28xx_board em28xx_boards[] = {
                         .amux     = EM28XX_AMUX_LINE_IN,
                 } },
         },
-        [EM2860_BOARD_POINTNIX_INTRAORAL_CAMERA] = {
-                .name                = "PointNix Intra-Oral Camera",
+        [EM2860_BOARD_SAA711X_REFERENCE_DESIGN] = {
+                .name                = "EM2860/SAA711X Reference Design",
                 .has_snapshot_button = 1,
-                .tda9887_conf        = TDA9887_PRESENT,
                 .tuner_type          = TUNER_ABSENT,
                 .decoder             = EM28XX_SAA711X,
                 .input               = { {
                         .type     = EM28XX_VMUX_SVIDEO,
                         .vmux     = SAA7115_SVIDEO3,
-                        .amux     = EM28XX_AMUX_VIDEO,
+                }, {
+                        .type     = EM28XX_VMUX_COMPOSITE1,
+                        .vmux     = SAA7115_COMPOSITE0,
                 } },
         },
         [EM2880_BOARD_MSI_DIGIVOX_AD] = {
@@ -1095,6 +1129,63 @@ struct em28xx_board em28xx_boards[] = {
                         .gpio     = default_analog,
                 } },
         },
+        [EM2882_BOARD_KWORLD_ATSC_315U] = {
+                .name           = "KWorld ATSC 315U HDTV TV Box",
+                .valid          = EM28XX_BOARD_NOT_VALIDATED,
+                .tuner_type     = TUNER_THOMSON_DTT761X,
+                .tuner_gpio     = em2882_kworld_315u_tuner_gpio,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .decoder        = EM28XX_SAA711X,
+                .has_dvb        = 1,
+                .dvb_gpio       = em2882_kworld_315u_digital,
+                .xclk           = EM28XX_XCLK_FREQUENCY_12MHZ,
+                .i2c_speed      = EM28XX_I2C_CLK_WAIT_ENABLE,
+                /* Analog mode - still not ready */
+                /*.input        = { {
+                        .type = EM28XX_VMUX_TELEVISION,
+                        .vmux = SAA7115_COMPOSITE2,
+                        .amux = EM28XX_AMUX_VIDEO,
+                        .gpio = em2882_kworld_315u_analog,
+                        .aout = EM28XX_AOUT_PCM_IN | EM28XX_AOUT_PCM_STEREO,
+                }, {
+                        .type = EM28XX_VMUX_COMPOSITE1,
+                        .vmux = SAA7115_COMPOSITE0,
+                        .amux = EM28XX_AMUX_LINE_IN,
+                        .gpio = em2882_kworld_315u_analog1,
+                        .aout = EM28XX_AOUT_PCM_IN | EM28XX_AOUT_PCM_STEREO,
+                }, {
+                        .type = EM28XX_VMUX_SVIDEO,
+                        .vmux = SAA7115_SVIDEO3,
+                        .amux = EM28XX_AMUX_LINE_IN,
+                        .gpio = em2882_kworld_315u_analog1,
+                        .aout = EM28XX_AOUT_PCM_IN | EM28XX_AOUT_PCM_STEREO,
+                } }, */
+        },
+        [EM2880_BOARD_EMPIRE_DUAL_TV] = {
+                .name = "Empire dual TV",
+                .tuner_type = TUNER_XC2028,
+                .tuner_gpio = default_tuner_gpio,
+                .has_dvb = 1,
+                .dvb_gpio = default_digital,
+                .mts_firmware = 1,
+                .decoder = EM28XX_TVP5150,
+                .input = { {
+                        .type = EM28XX_VMUX_TELEVISION,
+                        .vmux = TVP5150_COMPOSITE0,
+                        .amux = EM28XX_AMUX_VIDEO,
+                        .gpio = default_analog,
+                }, {
+                        .type = EM28XX_VMUX_COMPOSITE1,
+                        .vmux = TVP5150_COMPOSITE1,
+                        .amux = EM28XX_AMUX_LINE_IN,
+                        .gpio = default_analog,
+                }, {
+                        .type = EM28XX_VMUX_SVIDEO,
+                        .vmux = TVP5150_SVIDEO,
+                        .amux = EM28XX_AMUX_LINE_IN,
+                        .gpio = default_analog,
+                } },
+        },
         [EM2881_BOARD_DNT_DA2_HYBRID] = {
                 .name         = "DNT DA2 Hybrid",
                 .valid        = EM28XX_BOARD_NOT_VALIDATED,
@@ -1322,6 +1413,42 @@ struct em28xx_board em28xx_boards[] = {
                         .amux     = EM28XX_AMUX_VIDEO,
                 } },
         },
+        [EM2860_BOARD_TERRATEC_GRABBY] = {
+                .name            = "Terratec Grabby",
+                .vchannels       = 2,
+                .tuner_type      = TUNER_ABSENT,
+                .decoder         = EM28XX_SAA711X,
+                .xclk            = EM28XX_XCLK_FREQUENCY_12MHZ,
+                .input           = { {
+                        .type     = EM28XX_VMUX_COMPOSITE1,
+                        .vmux     = SAA7115_COMPOSITE0,
+                        .amux     = EM28XX_AMUX_VIDEO2,
+                }, {
+                        .type     = EM28XX_VMUX_SVIDEO,
+                        .vmux     = SAA7115_SVIDEO3,
+                        .amux     = EM28XX_AMUX_VIDEO2,
+                } },
+        },
+        [EM2860_BOARD_TERRATEC_AV350] = {
+                .name            = "Terratec AV350",
+                .vchannels       = 2,
+                .tuner_type      = TUNER_ABSENT,
+                .decoder         = EM28XX_TVP5150,
+                .xclk            = EM28XX_XCLK_FREQUENCY_12MHZ,
+                .mute_gpio       = terratec_av350_mute_gpio,
+                .input           = { {
+                        .type     = EM28XX_VMUX_COMPOSITE1,
+                        .vmux     = TVP5150_COMPOSITE1,
+                        .amux     = EM28XX_AUDIO_SRC_LINE,
+                        .gpio     = terratec_av350_unmute_gpio,
+
+                }, {
+                        .type     = EM28XX_VMUX_SVIDEO,
+                        .vmux     = TVP5150_SVIDEO,
+                        .amux     = EM28XX_AUDIO_SRC_LINE,
+                        .gpio     = terratec_av350_unmute_gpio,
+                } },
+        },
 };
 const unsigned int em28xx_bcount = ARRAY_SIZE(em28xx_boards);
 
@@ -1355,6 +1482,8 @@ struct usb_device_id em28xx_id_table[] = {
                         .driver_info = EM2880_BOARD_KWORLD_DVB_305U },
         { USB_DEVICE(0xeb1a, 0xe310),
                         .driver_info = EM2880_BOARD_MSI_DIGIVOX_AD },
+        { USB_DEVICE(0xeb1a, 0xa313),
+                .driver_info = EM2882_BOARD_KWORLD_ATSC_315U },
         { USB_DEVICE(0xeb1a, 0xa316),
                         .driver_info = EM2883_BOARD_KWORLD_HYBRID_330U },
         { USB_DEVICE(0xeb1a, 0xe320),
@@ -1385,6 +1514,10 @@ struct usb_device_id em28xx_id_table[] = {
                         .driver_info = EM2870_BOARD_TERRATEC_XS },
         { USB_DEVICE(0x0ccd, 0x0047),
                         .driver_info = EM2880_BOARD_TERRATEC_PRODIGY_XS },
+        { USB_DEVICE(0x0ccd, 0x0084),
+                        .driver_info = EM2860_BOARD_TERRATEC_AV350 },
+        { USB_DEVICE(0x0ccd, 0x0096),
+                        .driver_info = EM2860_BOARD_TERRATEC_GRABBY },
         { USB_DEVICE(0x185b, 0x2870),
                         .driver_info = EM2870_BOARD_COMPRO_VIDEOMATE },
         { USB_DEVICE(0x185b, 0x2041),
@@ -1437,13 +1570,14 @@ static struct em28xx_hash_table em28xx_eeprom_hash[] = {
         {0x6ce05a8f, EM2820_BOARD_PROLINK_PLAYTV_USB2, TUNER_YMEC_TVF_5533MF},
         {0x72cc5a8b, EM2820_BOARD_PROLINK_PLAYTV_BOX4_USB2, TUNER_YMEC_TVF_5533MF},
         {0x966a0441, EM2880_BOARD_KWORLD_DVB_310U, TUNER_XC2028},
+        {0x9567eb1a, EM2880_BOARD_EMPIRE_DUAL_TV, TUNER_XC2028},
 };
 
 /* I2C devicelist hash table for devices with generic USB IDs */
 static struct em28xx_hash_table em28xx_i2c_hash[] = {
         {0xb06a32c3, EM2800_BOARD_TERRATEC_CINERGY_200, TUNER_LG_PAL_NEW_TAPC},
         {0xf51200e3, EM2800_BOARD_VGEAR_POCKETTV, TUNER_LG_PAL_NEW_TAPC},
-        {0x1ba50080, EM2860_BOARD_POINTNIX_INTRAORAL_CAMERA, TUNER_ABSENT},
+        {0x1ba50080, EM2860_BOARD_SAA711X_REFERENCE_DESIGN, TUNER_ABSENT},
         {0xc51200e3, EM2820_BOARD_GADMEI_TVR200, TUNER_LG_PAL_NEW_TAPC},
 };
 
@@ -1619,6 +1753,17 @@ void em28xx_pre_card_setup(struct em28xx *dev)
                 em28xx_write_reg(dev, EM28XX_R08_GPIO, 0xfd);
                 break;
 
+        case EM2882_BOARD_KWORLD_ATSC_315U:
+                em28xx_write_reg(dev, EM28XX_R08_GPIO, 0xff);
+                msleep(10);
+                em28xx_write_reg(dev, EM28XX_R08_GPIO, 0xfe);
+                msleep(10);
+                em28xx_write_reg(dev, EM2880_R04_GPO, 0x00);
+                msleep(10);
+                em28xx_write_reg(dev, EM2880_R04_GPO, 0x08);
+                msleep(10);
+                break;
+
         case EM2860_BOARD_KAIOMY_TVNPC_U2:
                 em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x07", 1);
                 em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
@@ -1664,6 +1809,7 @@ static void em28xx_setup_xc3028(struct em28xx *dev, struct xc2028_ctrl *ctl)
         ctl->mts = em28xx_boards[dev->model].mts_firmware;
 
         switch (dev->model) {
+        case EM2880_BOARD_EMPIRE_DUAL_TV:
         case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900:
                 ctl->demod = XC3028_FE_ZARLINK456;
                 break;
@@ -1835,12 +1981,20 @@ static int em28xx_hint_board(struct em28xx *dev)
 }
 
 /* ----------------------------------------------------------------------- */
-void em28xx_set_ir(struct em28xx *dev, struct IR_i2c *ir)
+void em28xx_register_i2c_ir(struct em28xx *dev)
 {
-        if (disable_ir) {
-                ir->get_key = NULL;
-                return ;
-        }
+        struct i2c_board_info info;
+        struct IR_i2c_init_data init_data;
+        const unsigned short addr_list[] = {
+                 0x30, 0x47, I2C_CLIENT_END
+        };
+
+        if (disable_ir)
+                return;
+
+        memset(&info, 0, sizeof(struct i2c_board_info));
+        memset(&init_data, 0, sizeof(struct IR_i2c_init_data));
+        strlcpy(info.type, "ir_video", I2C_NAME_SIZE);
 
         /* detect & configure */
         switch (dev->model) {
@@ -1850,22 +2004,19 @@ void em28xx_set_ir(struct em28xx *dev, struct IR_i2c *ir)
                 break;
         case (EM2800_BOARD_TERRATEC_CINERGY_200):
         case (EM2820_BOARD_TERRATEC_CINERGY_250):
-                ir->ir_codes = ir_codes_em_terratec;
-                ir->get_key = em28xx_get_key_terratec;
-                snprintf(ir->c.name, sizeof(ir->c.name),
-                         "i2c IR (EM28XX Terratec)");
+                init_data.ir_codes = ir_codes_em_terratec;
+                init_data.get_key = em28xx_get_key_terratec;
+                init_data.name = "i2c IR (EM28XX Terratec)";
                 break;
         case (EM2820_BOARD_PINNACLE_USB_2):
-                ir->ir_codes = ir_codes_pinnacle_grey;
-                ir->get_key = em28xx_get_key_pinnacle_usb_grey;
-                snprintf(ir->c.name, sizeof(ir->c.name),
-                         "i2c IR (EM28XX Pinnacle PCTV)");
+                init_data.ir_codes = ir_codes_pinnacle_grey;
+                init_data.get_key = em28xx_get_key_pinnacle_usb_grey;
+                init_data.name = "i2c IR (EM28XX Pinnacle PCTV)";
                 break;
         case (EM2820_BOARD_HAUPPAUGE_WINTV_USB_2):
-                ir->ir_codes = ir_codes_hauppauge_new;
-                ir->get_key = em28xx_get_key_em_haup;
-                snprintf(ir->c.name, sizeof(ir->c.name),
-                         "i2c IR (EM2840 Hauppauge)");
+                init_data.ir_codes = ir_codes_hauppauge_new;
+                init_data.get_key = em28xx_get_key_em_haup;
+                init_data.name = "i2c IR (EM2840 Hauppauge)";
                 break;
         case (EM2820_BOARD_MSI_VOX_USB_2):
                 break;
@@ -1876,6 +2027,10 @@ void em28xx_set_ir(struct em28xx *dev, struct IR_i2c *ir)
         case (EM2800_BOARD_GRABBEEX_USB2800):
                 break;
         }
+
+        if (init_data.name)
+                info.platform_data = &init_data;
+        i2c_new_probed_device(&dev->i2c_adap, &info, addr_list);
 }
 
 void em28xx_card_setup(struct em28xx *dev)
@@ -1886,6 +2041,9 @@ void em28xx_card_setup(struct em28xx *dev)
         if (em28xx_boards[dev->model].tuner_addr)
                 dev->tuner_addr = em28xx_boards[dev->model].tuner_addr;
 
+        if (em28xx_boards[dev->model].tda9887_conf)
+                dev->tda9887_conf = em28xx_boards[dev->model].tda9887_conf;
+
         /* request some modules */
         switch (dev->model) {
         case EM2820_BOARD_HAUPPAUGE_WINTV_USB_2:
@@ -1915,6 +2073,12 @@ void em28xx_card_setup(struct em28xx *dev)
 #endif
                 break;
         }
+        case EM2882_BOARD_KWORLD_ATSC_315U:
+                em28xx_write_reg(dev, 0x0d, 0x42);
+                msleep(10);
+                em28xx_write_reg(dev, EM28XX_R08_GPIO, 0xfd);
+                msleep(10);
+                break;
         case EM2820_BOARD_KWORLD_PVRTV2800RF:
                 /* GPIO enables sound on KWORLD PVR TV 2800RF */
                 em28xx_write_reg(dev, EM28XX_R08_GPIO, 0xf9);
@@ -2279,6 +2443,20 @@ static int em28xx_usb_probe(struct usb_interface *interface,
                 ifnum,
                 interface->altsetting->desc.bInterfaceNumber);
 
+        /*
+         * Make sure we have 480 Mbps of bandwidth, otherwise things like
+         * video stream wouldn't likely work, since 12 Mbps is generally
+         * not enough even for most Digital TV streams.
+         */
+        if (udev->speed != USB_SPEED_HIGH && disable_usb_speed_check == 0) {
+                printk(DRIVER_NAME ": Device initialization failed.\n");
+                printk(DRIVER_NAME ": Device must be connected to a high-speed"
+                       " USB 2.0 port.\n");
+                em28xx_devused &= ~(1<<nr);
+                retval = -ENODEV;
+                goto err;
+        }
+
         if (nr >= EM28XX_MAXBOARDS) {
                 printk(DRIVER_NAME ": Supports only %i em28xx boards.\n",
                                 EM28XX_MAXBOARDS);
diff --git a/drivers/media/video/em28xx/em28xx-core.c b/drivers/media/video/em28xx/em28xx-core.c
index 192b76cdd5d7..c8d7ce8fbd36 100644
--- a/drivers/media/video/em28xx/em28xx-core.c
+++ b/drivers/media/video/em28xx/em28xx-core.c
@@ -500,18 +500,21 @@ int em28xx_audio_setup(struct em28xx *dev)
 
         /* See how this device is configured */
         cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
-        if (cfg < 0)
+        em28xx_info("Config register raw data: 0x%02x\n", cfg);
+        if (cfg < 0) {
+                /* Register read error?  */
                 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
-        else
-                em28xx_info("Config register raw data: 0x%02x\n", cfg);
-
-        if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
-                    EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
+        } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
+                /* The device doesn't have vendor audio at all */
+                dev->has_alsa_audio = 0;
+                dev->audio_mode.has_audio = 0;
+                return 0;
+        } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
+                   EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
                 em28xx_info("I2S Audio (3 sample rates)\n");
                 dev->audio_mode.i2s_3rates = 1;
-        }
-        if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
-                    EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
+        } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
+                   EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
                 em28xx_info("I2S Audio (5 sample rates)\n");
                 dev->audio_mode.i2s_5rates = 1;
         }
@@ -938,7 +941,7 @@ int em28xx_init_isoc(struct em28xx *dev, int max_packets,
         dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
                                               GFP_KERNEL);
         if (!dev->isoc_ctl.transfer_buffer) {
-                em28xx_errdev("cannot allocate memory for usbtransfer\n");
+                em28xx_errdev("cannot allocate memory for usb transfer\n");
                 kfree(dev->isoc_ctl.urb);
                 return -ENOMEM;
         }
@@ -1012,6 +1015,41 @@ int em28xx_init_isoc(struct em28xx *dev, int max_packets,
 }
 EXPORT_SYMBOL_GPL(em28xx_init_isoc);
 
+/* Determine the packet size for the DVB stream for the given device
+   (underlying value programmed into the eeprom) */
+int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)
+{
+        unsigned int chip_cfg2;
+        unsigned int packet_size = 564;
+
+        if (dev->chip_id == CHIP_ID_EM2874) {
+                /* FIXME - for now assume 564 like it was before, but the
+                   em2874 code should be added to return the proper value... */
+                packet_size = 564;
+        } else {
+                /* TS max packet size stored in bits 1-0 of R01 */
+                chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
+                switch (chip_cfg2 & EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK) {
+                case EM28XX_CHIPCFG2_TS_PACKETSIZE_188:
+                        packet_size = 188;
+                        break;
+                case EM28XX_CHIPCFG2_TS_PACKETSIZE_376:
+                        packet_size = 376;
+                        break;
+                case EM28XX_CHIPCFG2_TS_PACKETSIZE_564:
+                        packet_size = 564;
+                        break;
+                case EM28XX_CHIPCFG2_TS_PACKETSIZE_752:
+                        packet_size = 752;
+                        break;
+                }
+        }
+
+        em28xx_coredbg("dvb max packet size=%d\n", packet_size);
+        return packet_size;
+}
+EXPORT_SYMBOL_GPL(em28xx_isoc_dvb_max_packetsize);
+
 /*
  * em28xx_wake_i2c()
  * configure i2c attached devices
diff --git a/drivers/media/video/em28xx/em28xx-dvb.c b/drivers/media/video/em28xx/em28xx-dvb.c
index fcd25511209b..563dd2b1c8e9 100644
--- a/drivers/media/video/em28xx/em28xx-dvb.c
+++ b/drivers/media/video/em28xx/em28xx-dvb.c
@@ -25,6 +25,8 @@
 #include "em28xx.h"
 #include <media/v4l2-common.h>
 #include <media/videobuf-vmalloc.h>
+#include <media/tuner.h>
+#include "tuner-simple.h"
 
 #include "lgdt330x.h"
 #include "zl10353.h"
@@ -46,7 +48,6 @@ if (debug >= level) 						\
 } while (0)
 
 #define EM28XX_DVB_NUM_BUFS 5
-#define EM28XX_DVB_MAX_PACKETSIZE 564
 #define EM28XX_DVB_MAX_PACKETS 64
 
 struct em28xx_dvb {
@@ -142,14 +143,17 @@ static int start_streaming(struct em28xx_dvb *dvb)
 {
         int rc;
         struct em28xx *dev = dvb->adapter.priv;
+        int max_dvb_packet_size;
 
         usb_set_interface(dev->udev, 0, 1);
         rc = em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
         if (rc < 0)
                 return rc;
 
+        max_dvb_packet_size = em28xx_isoc_dvb_max_packetsize(dev);
+
         return em28xx_init_isoc(dev, EM28XX_DVB_MAX_PACKETS,
-                                EM28XX_DVB_NUM_BUFS, EM28XX_DVB_MAX_PACKETSIZE,
+                                EM28XX_DVB_NUM_BUFS, max_dvb_packet_size,
                                 dvb_isoc_copy);
 }
 
@@ -431,6 +435,7 @@ static int dvb_init(struct em28xx *dev)
         case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900:
         case EM2880_BOARD_TERRATEC_HYBRID_XS:
         case EM2880_BOARD_KWORLD_DVB_310U:
+        case EM2880_BOARD_EMPIRE_DUAL_TV:
                 dvb->frontend = dvb_attach(zl10353_attach,
                                            &em28xx_zl10353_with_xc3028,
                                            &dev->i2c_adap);
@@ -448,6 +453,18 @@ static int dvb_init(struct em28xx *dev)
                         goto out_free;
                 }
                 break;
+        case EM2882_BOARD_KWORLD_ATSC_315U:
+                dvb->frontend = dvb_attach(lgdt330x_attach,
+                                           &em2880_lgdt3303_dev,
+                                           &dev->i2c_adap);
+                if (dvb->frontend != NULL) {
+                        if (!dvb_attach(simple_tuner_attach, dvb->frontend,
+                                &dev->i2c_adap, 0x61, TUNER_THOMSON_DTT761X)) {
+                                result = -EINVAL;
+                                goto out_free;
+                        }
+                }
+                break;
         case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2:
 #ifdef EM28XX_DRX397XD_SUPPORT
                 /* We don't have the config structure properly populated, so
diff --git a/drivers/media/video/em28xx/em28xx-i2c.c b/drivers/media/video/em28xx/em28xx-i2c.c
index f0bf1d960c75..2c86fcf089f5 100644
--- a/drivers/media/video/em28xx/em28xx-i2c.c
+++ b/drivers/media/video/em28xx/em28xx-i2c.c
@@ -451,27 +451,6 @@ static u32 functionality(struct i2c_adapter *adap)
         return I2C_FUNC_SMBUS_EMUL;
 }
 
-/*
- * attach_inform()
- * gets called when a device attaches to the i2c bus
- * does some basic configuration
- */
-static int attach_inform(struct i2c_client *client)
-{
-        struct em28xx *dev = client->adapter->algo_data;
-        struct IR_i2c *ir = i2c_get_clientdata(client);
-
-        switch (client->addr << 1) {
-        case 0x60:
-        case 0x8e:
-                dprintk1(1, "attach_inform: IR detected (%s).\n", ir->phys);
-                em28xx_set_ir(dev, ir);
-                break;
-        }
-
-        return 0;
-}
-
 static struct i2c_algorithm em28xx_algo = {
         .master_xfer   = em28xx_i2c_xfer,
         .functionality = functionality,
@@ -482,7 +461,6 @@ static struct i2c_adapter em28xx_adap_template = {
         .name = "em28xx",
         .id = I2C_HW_B_EM28XX,
         .algo = &em28xx_algo,
-        .client_register = attach_inform,
 };
 
 static struct i2c_client em28xx_client_template = {
@@ -575,6 +553,9 @@ int em28xx_i2c_register(struct em28xx *dev)
         if (i2c_scan)
                 em28xx_do_i2c_scan(dev);
 
+        /* Instantiate the IR receiver device, if present */
+        em28xx_register_i2c_ir(dev);
+
         return 0;
 }
 
diff --git a/drivers/media/video/em28xx/em28xx-input.c b/drivers/media/video/em28xx/em28xx-input.c
index a5abfd7a19f5..7a0fe3816e3d 100644
--- a/drivers/media/video/em28xx/em28xx-input.c
+++ b/drivers/media/video/em28xx/em28xx-input.c
@@ -40,7 +40,7 @@ MODULE_PARM_DESC(ir_debug, "enable debug messages [IR]");
 
 #define i2cdprintk(fmt, arg...) \
         if (ir_debug) { \
-                printk(KERN_DEBUG "%s/ir: " fmt, ir->c.name , ## arg); \
+                printk(KERN_DEBUG "%s/ir: " fmt, ir->name , ## arg); \
         }
 
 #define dprintk(fmt, arg...) \
@@ -85,7 +85,7 @@ int em28xx_get_key_terratec(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw)
         unsigned char b;
 
         /* poll IR chip */
-        if (1 != i2c_master_recv(&ir->c, &b, 1)) {
+        if (1 != i2c_master_recv(ir->c, &b, 1)) {
                 i2cdprintk("read error\n");
                 return -EIO;
         }
@@ -114,7 +114,7 @@ int em28xx_get_key_em_haup(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw)
         unsigned char code;
 
         /* poll IR chip */
-        if (2 != i2c_master_recv(&ir->c, buf, 2))
+        if (2 != i2c_master_recv(ir->c, buf, 2))
                 return -EIO;
 
         /* Does eliminate repeated parity code */
@@ -147,7 +147,7 @@ int em28xx_get_key_pinnacle_usb_grey(struct IR_i2c *ir, u32 *ir_key,
 
         /* poll IR chip */
 
-        if (3 != i2c_master_recv(&ir->c, buf, 3)) {
+        if (3 != i2c_master_recv(ir->c, buf, 3)) {
                 i2cdprintk("read error\n");
                 return -EIO;
         }
diff --git a/drivers/media/video/em28xx/em28xx-reg.h b/drivers/media/video/em28xx/em28xx-reg.h
index 24e39c56811e..a2676d63cfd0 100644
--- a/drivers/media/video/em28xx/em28xx-reg.h
+++ b/drivers/media/video/em28xx/em28xx-reg.h
@@ -27,6 +27,22 @@
 #define EM28XX_CHIPCFG_AC97                     0x10
 #define EM28XX_CHIPCFG_AUDIOMASK                0x30
 
+#define EM28XX_R01_CHIPCFG2     0x01
+
+/* em28xx Chip Configuration 2 0x01 */
+#define EM28XX_CHIPCFG2_TS_PRESENT              0x10
+#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_MASK    0x0c /* bits 3-2 */
+#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_1MF     0x00
+#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_2MF     0x04
+#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_4MF     0x08
+#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_8MF     0x0c
+#define EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK      0x03 /* bits 0-1 */
+#define EM28XX_CHIPCFG2_TS_PACKETSIZE_188       0x00
+#define EM28XX_CHIPCFG2_TS_PACKETSIZE_376       0x01
+#define EM28XX_CHIPCFG2_TS_PACKETSIZE_564       0x02
+#define EM28XX_CHIPCFG2_TS_PACKETSIZE_752       0x03
+
+
         /* GPIO/GPO registers */
 #define EM2880_R04_GPO  0x04    /* em2880-em2883 only */
 #define EM28XX_R08_GPIO 0x08    /* em2820 or upper */
diff --git a/drivers/media/video/em28xx/em28xx.h b/drivers/media/video/em28xx/em28xx.h
index 4c4e58004f54..8bf81be1da61 100644
--- a/drivers/media/video/em28xx/em28xx.h
+++ b/drivers/media/video/em28xx/em28xx.h
@@ -58,7 +58,7 @@
 #define EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950    16
 #define EM2880_BOARD_PINNACLE_PCTV_HD_PRO       17
 #define EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2 18
-#define EM2860_BOARD_POINTNIX_INTRAORAL_CAMERA  19
+#define EM2860_BOARD_SAA711X_REFERENCE_DESIGN   19
 #define EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600   20
 #define EM2800_BOARD_GRABBEEX_USB2800           21
 #define EM2750_BOARD_UNKNOWN                      22
@@ -102,6 +102,10 @@
 #define EM2860_BOARD_KAIOMY_TVNPC_U2              63
 #define EM2860_BOARD_EASYCAP                      64
 #define EM2820_BOARD_IODATA_GVMVP_SZ              65
+#define EM2880_BOARD_EMPIRE_DUAL_TV               66
+#define EM2860_BOARD_TERRATEC_GRABBY              67
+#define EM2860_BOARD_TERRATEC_AV350               68
+#define EM2882_BOARD_KWORLD_ATSC_315U             69
 
 /* Limits minimum and default number of buffers */
 #define EM28XX_MIN_BUF 4
@@ -615,6 +619,7 @@ int em28xx_init_isoc(struct em28xx *dev, int max_packets,
                      int num_bufs, int max_pkt_size,
                      int (*isoc_copy) (struct em28xx *dev, struct urb *urb));
 void em28xx_uninit_isoc(struct em28xx *dev);
+int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev);
 int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode);
 int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio);
 void em28xx_wake_i2c(struct em28xx *dev);
@@ -639,7 +644,7 @@ extern void em28xx_card_setup(struct em28xx *dev);
 extern struct em28xx_board em28xx_boards[];
 extern struct usb_device_id em28xx_id_table[];
 extern const unsigned int em28xx_bcount;
-void em28xx_set_ir(struct em28xx *dev, struct IR_i2c *ir);
+void em28xx_register_i2c_ir(struct em28xx *dev);
 int em28xx_tuner_callback(void *ptr, int component, int command, int arg);
 void em28xx_release_resources(struct em28xx *dev);
 
diff --git a/drivers/media/video/gspca/finepix.c b/drivers/media/video/gspca/finepix.c
index 00e6863ed666..480ec5c87d0e 100644
--- a/drivers/media/video/gspca/finepix.c
+++ b/drivers/media/video/gspca/finepix.c
@@ -168,6 +168,7 @@ static int sd_config(struct gspca_dev *gspca_dev,
 
         cam->cam_mode = fpix_mode;
         cam->nmodes = 1;
+        cam->bulk = 1;
         cam->bulk_size = FPIX_MAX_TRANSFER;
 
         INIT_WORK(&dev->work_struct, dostream);
diff --git a/drivers/media/video/gspca/gspca.c b/drivers/media/video/gspca/gspca.c
index a2741d7dccfe..f7e0355ad644 100644
--- a/drivers/media/video/gspca/gspca.c
+++ b/drivers/media/video/gspca/gspca.c
@@ -1,7 +1,7 @@
 /*
  * Main USB camera driver
  *
- * V4L2 by Jean-Francois Moine <http://moinejf.free.fr>
+ * Copyright (C) 2008-2009 Jean-Francois Moine (http://moinejf.free.fr)
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -47,7 +47,7 @@ MODULE_AUTHOR("Jean-Francois Moine <http://moinejf.free.fr>");
 MODULE_DESCRIPTION("GSPCA USB Camera Driver");
 MODULE_LICENSE("GPL");
 
-#define DRIVER_VERSION_NUMBER   KERNEL_VERSION(2, 5, 0)
+#define DRIVER_VERSION_NUMBER   KERNEL_VERSION(2, 6, 0)
 
 #ifdef GSPCA_DEBUG
 int gspca_debug = D_ERR | D_PROBE;
@@ -441,7 +441,7 @@ static void destroy_urbs(struct gspca_dev *gspca_dev)
  * look for an input transfer endpoint in an alternate setting
  */
 static struct usb_host_endpoint *alt_xfer(struct usb_host_interface *alt,
-                                          __u8 xfer)
+                                          int xfer)
 {
         struct usb_host_endpoint *ep;
         int i, attr;
@@ -449,7 +449,8 @@ static struct usb_host_endpoint *alt_xfer(struct usb_host_interface *alt,
         for (i = 0; i < alt->desc.bNumEndpoints; i++) {
                 ep = &alt->endpoint[i];
                 attr = ep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
-                if (attr == xfer)
+                if (attr == xfer
+                    && ep->desc.wMaxPacketSize != 0)
                         return ep;
         }
         return NULL;
@@ -467,37 +468,28 @@ static struct usb_host_endpoint *get_ep(struct gspca_dev *gspca_dev)
 {
         struct usb_interface *intf;
         struct usb_host_endpoint *ep;
-        int i, ret;
+        int xfer, i, ret;
 
         intf = usb_ifnum_to_if(gspca_dev->dev, gspca_dev->iface);
         ep = NULL;
+        xfer = gspca_dev->cam.bulk ? USB_ENDPOINT_XFER_BULK
+                                   : USB_ENDPOINT_XFER_ISOC;
         i = gspca_dev->alt;                     /* previous alt setting */
-
-        /* try isoc */
         while (--i >= 0) {
-                ep = alt_xfer(&intf->altsetting[i],
-                                USB_ENDPOINT_XFER_ISOC);
+                ep = alt_xfer(&intf->altsetting[i], xfer);
                 if (ep)
                         break;
         }
-
-        /* if no isoc, try bulk (alt 0 only) */
         if (ep == NULL) {
-                ep = alt_xfer(&intf->altsetting[0],
-                                USB_ENDPOINT_XFER_BULK);
-                if (ep == NULL) {
-                        err("no transfer endpoint found");
-                        return NULL;
-                }
-                i = 0;
-                gspca_dev->bulk = 1;
+                err("no transfer endpoint found");
+                return NULL;
         }
         PDEBUG(D_STREAM, "use alt %d ep 0x%02x",
                         i, ep->desc.bEndpointAddress);
-        if (i > 0) {
+        if (gspca_dev->nbalt > 1) {
                 ret = usb_set_interface(gspca_dev->dev, gspca_dev->iface, i);
                 if (ret < 0) {
-                        err("set interface err %d", ret);
+                        err("set alt %d err %d", i, ret);
                         return NULL;
                 }
         }
@@ -517,13 +509,13 @@ static int create_urbs(struct gspca_dev *gspca_dev,
         /* calculate the packet size and the number of packets */
         psize = le16_to_cpu(ep->desc.wMaxPacketSize);
 
-        if (!gspca_dev->bulk) {                 /* isoc */
+        if (!gspca_dev->cam.bulk) {             /* isoc */
 
                 /* See paragraph 5.9 / table 5-11 of the usb 2.0 spec. */
                 psize = (psize & 0x07ff) * (1 + ((psize >> 11) & 3));
-                npkt = ISO_MAX_SIZE / psize;
-                if (npkt > ISO_MAX_PKT)
-                        npkt = ISO_MAX_PKT;
+                npkt = gspca_dev->cam.npkt;
+                if (npkt == 0)
+                        npkt = 32;              /* default value */
                 bsize = psize * npkt;
                 PDEBUG(D_STREAM,
                         "isoc %d pkts size %d = bsize:%d",
@@ -617,7 +609,7 @@ static int gspca_init_transfer(struct gspca_dev *gspca_dev)
                         goto out;
 
                 /* clear the bulk endpoint */
-                if (gspca_dev->bulk)
+                if (gspca_dev->cam.bulk)
                         usb_clear_halt(gspca_dev->dev,
                                         gspca_dev->urb[0]->pipe);
 
@@ -630,7 +622,7 @@ static int gspca_init_transfer(struct gspca_dev *gspca_dev)
                 gspca_dev->streaming = 1;
 
                 /* some bulk transfers are started by the subdriver */
-                if (gspca_dev->bulk && gspca_dev->cam.bulk_nurbs == 0)
+                if (gspca_dev->cam.bulk && gspca_dev->cam.bulk_nurbs == 0)
                         break;
 
                 /* submit the URBs */
@@ -661,6 +653,8 @@ static int gspca_set_alt0(struct gspca_dev *gspca_dev)
 {
         int ret;
 
+        if (gspca_dev->alt == 0)
+                return 0;
         ret = usb_set_interface(gspca_dev->dev, gspca_dev->iface, 0);
         if (ret < 0)
                 PDEBUG(D_ERR|D_STREAM, "set alt 0 err %d", ret);
@@ -869,6 +863,32 @@ out:
         return ret;
 }
 
+static int vidioc_enum_framesizes(struct file *file, void *priv,
+                                  struct v4l2_frmsizeenum *fsize)
+{
+        struct gspca_dev *gspca_dev = priv;
+        int i;
+        __u32 index = 0;
+
+        for (i = 0; i < gspca_dev->cam.nmodes; i++) {
+                if (fsize->pixel_format !=
+                                gspca_dev->cam.cam_mode[i].pixelformat)
+                        continue;
+
+                if (fsize->index == index) {
+                        fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+                        fsize->discrete.width =
+                                gspca_dev->cam.cam_mode[i].width;
+                        fsize->discrete.height =
+                                gspca_dev->cam.cam_mode[i].height;
+                        return 0;
+                }
+                index++;
+        }
+
+        return -EINVAL;
+}
+
 static void gspca_release(struct video_device *vfd)
 {
         struct gspca_dev *gspca_dev = container_of(vfd, struct gspca_dev, vdev);
@@ -989,43 +1009,54 @@ out:
         return ret;
 }
 
+static const struct ctrl *get_ctrl(struct gspca_dev *gspca_dev,
+                                   int id)
+{
+        const struct ctrl *ctrls;
+        int i;
+
+        for (i = 0, ctrls = gspca_dev->sd_desc->ctrls;
+             i < gspca_dev->sd_desc->nctrls;
+             i++, ctrls++) {
+                if (gspca_dev->ctrl_dis & (1 << i))
+                        continue;
+                if (id == ctrls->qctrl.id)
+                        return ctrls;
+        }
+        return NULL;
+}
+
 static int vidioc_queryctrl(struct file *file, void *priv,
                            struct v4l2_queryctrl *q_ctrl)
 {
         struct gspca_dev *gspca_dev = priv;
-        int i, ix;
+        const struct ctrl *ctrls;
+        int i;
         u32 id;
 
-        ix = -1;
+        ctrls = NULL;
         id = q_ctrl->id;
         if (id & V4L2_CTRL_FLAG_NEXT_CTRL) {
                 id &= V4L2_CTRL_ID_MASK;
                 id++;
                 for (i = 0; i < gspca_dev->sd_desc->nctrls; i++) {
-                        if (gspca_dev->sd_desc->ctrls[i].qctrl.id < id)
+                        if (gspca_dev->ctrl_dis & (1 << i))
                                 continue;
-                        if (ix < 0) {
-                                ix = i;
+                        if (ctrls->qctrl.id < id)
                                 continue;
+                        if (ctrls != NULL) {
+                                if (gspca_dev->sd_desc->ctrls[i].qctrl.id
+                                            > ctrls->qctrl.id)
+                                        continue;
                         }
-                        if (gspca_dev->sd_desc->ctrls[i].qctrl.id
-                                    > gspca_dev->sd_desc->ctrls[ix].qctrl.id)
-                                continue;
-                        ix = i;
-                }
-        }
-        for (i = 0; i < gspca_dev->sd_desc->nctrls; i++) {
-                if (id == gspca_dev->sd_desc->ctrls[i].qctrl.id) {
-                        ix = i;
-                        break;
+                        ctrls = &gspca_dev->sd_desc->ctrls[i];
                 }
+        } else {
+                ctrls = get_ctrl(gspca_dev, id);
         }
-        if (ix < 0)
+        if (ctrls == NULL)
                 return -EINVAL;
-        memcpy(q_ctrl, &gspca_dev->sd_desc->ctrls[ix].qctrl,
-                sizeof *q_ctrl);
-        if (gspca_dev->ctrl_dis & (1 << ix))
-                q_ctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
+        memcpy(q_ctrl, ctrls, sizeof *q_ctrl);
         return 0;
 }
 
@@ -1034,56 +1065,45 @@ static int vidioc_s_ctrl(struct file *file, void *priv,
 {
         struct gspca_dev *gspca_dev = priv;
         const struct ctrl *ctrls;
-        int i, ret;
+        int ret;
 
-        for (i = 0, ctrls = gspca_dev->sd_desc->ctrls;
-             i < gspca_dev->sd_desc->nctrls;
-             i++, ctrls++) {
-                if (ctrl->id != ctrls->qctrl.id)
-                        continue;
-                if (gspca_dev->ctrl_dis & (1 << i))
-                        return -EINVAL;
-                if (ctrl->value < ctrls->qctrl.minimum
-                    || ctrl->value > ctrls->qctrl.maximum)
-                        return -ERANGE;
-                PDEBUG(D_CONF, "set ctrl [%08x] = %d", ctrl->id, ctrl->value);
-                if (mutex_lock_interruptible(&gspca_dev->usb_lock))
-                        return -ERESTARTSYS;
-                if (gspca_dev->present)
-                        ret = ctrls->set(gspca_dev, ctrl->value);
-                else
-                        ret = -ENODEV;
-                mutex_unlock(&gspca_dev->usb_lock);
-                return ret;
-        }
-        return -EINVAL;
+        ctrls = get_ctrl(gspca_dev, ctrl->id);
+        if (ctrls == NULL)
+                return -EINVAL;
+
+        if (ctrl->value < ctrls->qctrl.minimum
+            || ctrl->value > ctrls->qctrl.maximum)
+                return -ERANGE;
+        PDEBUG(D_CONF, "set ctrl [%08x] = %d", ctrl->id, ctrl->value);
+        if (mutex_lock_interruptible(&gspca_dev->usb_lock))
+                return -ERESTARTSYS;
+        if (gspca_dev->present)
+                ret = ctrls->set(gspca_dev, ctrl->value);
+        else
+                ret = -ENODEV;
+        mutex_unlock(&gspca_dev->usb_lock);
+        return ret;
 }
 
 static int vidioc_g_ctrl(struct file *file, void *priv,
                          struct v4l2_control *ctrl)
 {
         struct gspca_dev *gspca_dev = priv;
-
         const struct ctrl *ctrls;
-        int i, ret;
+        int ret;
 
-        for (i = 0, ctrls = gspca_dev->sd_desc->ctrls;
-             i < gspca_dev->sd_desc->nctrls;
-             i++, ctrls++) {
-                if (ctrl->id != ctrls->qctrl.id)
-                        continue;
-                if (gspca_dev->ctrl_dis & (1 << i))
-                        return -EINVAL;
-                if (mutex_lock_interruptible(&gspca_dev->usb_lock))
-                        return -ERESTARTSYS;
-                if (gspca_dev->present)
-                        ret = ctrls->get(gspca_dev, &ctrl->value);
-                else
-                        ret = -ENODEV;
-                mutex_unlock(&gspca_dev->usb_lock);
-                return ret;
-        }
-        return -EINVAL;
+        ctrls = get_ctrl(gspca_dev, ctrl->id);
+        if (ctrls == NULL)
+                return -EINVAL;
+
+        if (mutex_lock_interruptible(&gspca_dev->usb_lock))
+                return -ERESTARTSYS;
+        if (gspca_dev->present)
+                ret = ctrls->get(gspca_dev, &ctrl->value);
+        else
+                ret = -ENODEV;
+        mutex_unlock(&gspca_dev->usb_lock);
+        return ret;
 }
 
 /*fixme: have an audio flag in gspca_dev?*/
@@ -1864,6 +1884,7 @@ static const struct v4l2_ioctl_ops dev_ioctl_ops = {
         .vidioc_g_parm          = vidioc_g_parm,
         .vidioc_s_parm          = vidioc_s_parm,
         .vidioc_s_std           = vidioc_s_std,
+        .vidioc_enum_framesizes = vidioc_enum_framesizes,
 #ifdef CONFIG_VIDEO_V4L1_COMPAT
         .vidiocgmbuf          = vidiocgmbuf,
 #endif
@@ -1943,7 +1964,7 @@ int gspca_dev_probe(struct usb_interface *intf,
 
         /* init video stuff */
         memcpy(&gspca_dev->vdev, &gspca_template, sizeof gspca_template);
-        gspca_dev->vdev.parent = &dev->dev;
+        gspca_dev->vdev.parent = &intf->dev;
         gspca_dev->module = module;
         gspca_dev->present = 1;
         ret = video_register_device(&gspca_dev->vdev,
diff --git a/drivers/media/video/gspca/gspca.h b/drivers/media/video/gspca/gspca.h
index 58e8ff02136a..bd1faff88644 100644
--- a/drivers/media/video/gspca/gspca.h
+++ b/drivers/media/video/gspca/gspca.h
@@ -44,8 +44,6 @@ extern int gspca_debug;
 #define GSPCA_MAX_FRAMES 16     /* maximum number of video frame buffers */
 /* image transfers */
 #define MAX_NURBS 4             /* max number of URBs */
-#define ISO_MAX_PKT 32          /* max number of packets in an ISOC transfer */
-#define ISO_MAX_SIZE 0x8000     /* max size of one URB buffer (32 Kb) */
 
 /* device information - set at probe time */
 struct cam {
@@ -56,6 +54,9 @@ struct cam {
                                  * - cannot be > MAX_NURBS
                                  * - when 0 and bulk_size != 0 means
                                  *   1 URB and submit done by subdriver */
+        u8 bulk;                /* image transfer by 0:isoc / 1:bulk */
+        u8 npkt;                /* number of packets in an ISOC message
+                                 * 0 is the default value: 32 packets */
         u32 input_flags;        /* value for ENUM_INPUT status flags */
 };
 
@@ -168,7 +169,6 @@ struct gspca_dev {
         __u8 iface;                     /* USB interface number */
         __u8 alt;                       /* USB alternate setting */
         __u8 nbalt;                     /* number of USB alternate settings */
-        u8 bulk;                        /* image transfer by 0:isoc / 1:bulk */
 };
 
 int gspca_dev_probe(struct usb_interface *intf,
diff --git a/drivers/media/video/gspca/m5602/Makefile b/drivers/media/video/gspca/m5602/Makefile
index 9fa3644f4869..bf7a19a1e6d1 100644
--- a/drivers/media/video/gspca/m5602/Makefile
+++ b/drivers/media/video/gspca/m5602/Makefile
@@ -2,9 +2,10 @@ obj-$(CONFIG_USB_M5602) += gspca_m5602.o
 
 gspca_m5602-objs := m5602_core.o \
                     m5602_ov9650.o \
+                    m5602_ov7660.o \
                     m5602_mt9m111.o \
                     m5602_po1030.o \
                     m5602_s5k83a.o \
                     m5602_s5k4aa.o
 
-EXTRA_CFLAGS += -Idrivers/media/video/gspca
\ No newline at end of file
+EXTRA_CFLAGS += -Idrivers/media/video/gspca
diff --git a/drivers/media/video/gspca/m5602/m5602_bridge.h b/drivers/media/video/gspca/m5602/m5602_bridge.h
index 8f1cea6fd3bf..1127a405c9b2 100644
--- a/drivers/media/video/gspca/m5602/m5602_bridge.h
+++ b/drivers/media/video/gspca/m5602/m5602_bridge.h
@@ -45,6 +45,15 @@
 #define M5602_XB_SEN_CLK_DIV            0x15
 #define M5602_XB_AUD_CLK_CTRL           0x16
 #define M5602_XB_AUD_CLK_DIV            0x17
+#define M5602_OB_AC_LINK_STATE          0x22
+#define M5602_OB_PCM_SLOT_INDEX         0x24
+#define M5602_OB_GPIO_SLOT_INDEX        0x25
+#define M5602_OB_ACRX_STATUS_ADDRESS_H  0x28
+#define M5602_OB_ACRX_STATUS_DATA_L     0x29
+#define M5602_OB_ACRX_STATUS_DATA_H     0x2a
+#define M5602_OB_ACTX_COMMAND_ADDRESS   0x31
+#define M5602_OB_ACRX_COMMAND_DATA_L    0x32
+#define M5602_OB_ACTX_COMMAND_DATA_H    0X33
 #define M5602_XB_DEVCTR1                0x41
 #define M5602_XB_EPSETR0                0x42
 #define M5602_XB_EPAFCTR                0x47
@@ -77,7 +86,18 @@
 #define M5602_XB_GPIO_EN_L              0x75
 #define M5602_XB_GPIO_DAT               0x76
 #define M5602_XB_GPIO_DIR               0x77
-#define M5602_XB_MISC_CTL               0x70
+#define M5602_XB_SEN_CLK_CONTROL        0x80
+#define M5602_XB_SEN_CLK_DIVISION       0x81
+#define M5602_XB_CPR_CLK_CONTROL        0x82
+#define M5602_XB_CPR_CLK_DIVISION       0x83
+#define M5602_XB_MCU_CLK_CONTROL        0x84
+#define M5602_XB_MCU_CLK_DIVISION       0x85
+#define M5602_XB_DCT_CLK_CONTROL        0x86
+#define M5602_XB_DCT_CLK_DIVISION       0x87
+#define M5602_XB_EC_CLK_CONTROL         0x88
+#define M5602_XB_EC_CLK_DIVISION        0x89
+#define M5602_XB_LBUF_CLK_CONTROL       0x8a
+#define M5602_XB_LBUF_CLK_DIVISION      0x8b
 
 #define I2C_BUSY 0x80
 
@@ -128,10 +148,10 @@ struct sd {
 };
 
 int m5602_read_bridge(
-        struct sd *sd, u8 address, u8 *i2c_data);
+        struct sd *sd, const u8 address, u8 *i2c_data);
 
 int m5602_write_bridge(
-        struct sd *sd, u8 address, u8 i2c_data);
+        struct sd *sd, const u8 address, const u8 i2c_data);
 
 int m5602_write_sensor(struct sd *sd, const u8 address,
                        u8 *i2c_data, const u8 len);
diff --git a/drivers/media/video/gspca/m5602/m5602_core.c b/drivers/media/video/gspca/m5602/m5602_core.c
index 1aac2985fee6..8a5bba16ff32 100644
--- a/drivers/media/video/gspca/m5602/m5602_core.c
+++ b/drivers/media/video/gspca/m5602/m5602_core.c
@@ -17,6 +17,7 @@
  */
 
 #include "m5602_ov9650.h"
+#include "m5602_ov7660.h"
 #include "m5602_mt9m111.h"
 #include "m5602_po1030.h"
 #include "m5602_s5k83a.h"
@@ -35,7 +36,7 @@ static const __devinitdata struct usb_device_id m5602_table[] = {
 MODULE_DEVICE_TABLE(usb, m5602_table);
 
 /* Reads a byte from the m5602 */
-int m5602_read_bridge(struct sd *sd, u8 address, u8 *i2c_data)
+int m5602_read_bridge(struct sd *sd, const u8 address, u8 *i2c_data)
 {
         int err;
         struct usb_device *udev = sd->gspca_dev.dev;
@@ -56,7 +57,7 @@ int m5602_read_bridge(struct sd *sd, u8 address, u8 *i2c_data)
 }
 
 /* Writes a byte to to the m5602 */
-int m5602_write_bridge(struct sd *sd, u8 address, u8 i2c_data)
+int m5602_write_bridge(struct sd *sd, const u8 address, const u8 i2c_data)
 {
         int err;
         struct usb_device *udev = sd->gspca_dev.dev;
@@ -80,6 +81,17 @@ int m5602_write_bridge(struct sd *sd, u8 address, u8 i2c_data)
         return (err < 0) ? err : 0;
 }
 
+int m5602_wait_for_i2c(struct sd *sd)
+{
+        int err;
+        u8 data;
+
+        do {
+                err = m5602_read_bridge(sd, M5602_XB_I2C_STATUS, &data);
+        } while ((data & I2C_BUSY) && !err);
+        return err;
+}
+
 int m5602_read_sensor(struct sd *sd, const u8 address,
                        u8 *i2c_data, const u8 len)
 {
@@ -88,9 +100,7 @@ int m5602_read_sensor(struct sd *sd, const u8 address,
         if (!len || len > sd->sensor->i2c_regW)
                 return -EINVAL;
 
-        do {
-                err = m5602_read_bridge(sd, M5602_XB_I2C_STATUS, i2c_data);
-        } while ((*i2c_data & I2C_BUSY) && !err);
+        err = m5602_wait_for_i2c(sd);
         if (err < 0)
                 return err;
 
@@ -103,21 +113,25 @@ int m5602_read_sensor(struct sd *sd, const u8 address,
         if (err < 0)
                 return err;
 
+        /* Sensors with registers that are of only
+           one byte width are differently read */
+
+        /* FIXME: This works with the ov9650, but has issues with the po1030 */
         if (sd->sensor->i2c_regW == 1) {
-                err = m5602_write_bridge(sd, M5602_XB_I2C_CTRL, len);
+                err = m5602_write_bridge(sd, M5602_XB_I2C_CTRL, 1);
                 if (err < 0)
                         return err;
 
                 err = m5602_write_bridge(sd, M5602_XB_I2C_CTRL, 0x08);
-                if (err < 0)
-                        return err;
         } else {
                 err = m5602_write_bridge(sd, M5602_XB_I2C_CTRL, 0x18 + len);
-                if (err < 0)
-                        return err;
         }
 
         for (i = 0; (i < len) && !err; i++) {
+                err = m5602_wait_for_i2c(sd);
+                if (err < 0)
+                        return err;
+
                 err = m5602_read_bridge(sd, M5602_XB_I2C_DATA, &(i2c_data[i]));
 
                 PDEBUG(D_CONF, "Reading sensor register "
@@ -206,6 +220,11 @@ static int m5602_probe_sensor(struct sd *sd)
         if (!sd->sensor->probe(sd))
                 return 0;
 
+        /* Try the ov7660 */
+        sd->sensor = &ov7660;
+        if (!sd->sensor->probe(sd))
+                return 0;
+
         /* Try the s5k83a */
         sd->sensor = &s5k83a;
         if (!sd->sensor->probe(sd))
@@ -409,8 +428,9 @@ MODULE_DESCRIPTION(DRIVER_DESC);
 MODULE_LICENSE("GPL");
 module_param(force_sensor, int, S_IRUGO | S_IWUSR);
 MODULE_PARM_DESC(force_sensor,
-                "force detection of sensor, "
-                "1 = OV9650, 2 = S5K83A, 3 = S5K4AA, 4 = MT9M111, 5 = PO1030");
+                "forces detection of a sensor, "
+                "1 = OV9650, 2 = S5K83A, 3 = S5K4AA, "
+                "4 = MT9M111, 5 = PO1030, 6 = OV7660");
 
 module_param(dump_bridge, bool, S_IRUGO | S_IWUSR);
 MODULE_PARM_DESC(dump_bridge, "Dumps all usb bridge registers at startup");
diff --git a/drivers/media/video/gspca/m5602/m5602_mt9m111.c b/drivers/media/video/gspca/m5602/m5602_mt9m111.c
index 7d3f9e348ef4..8d071dff6944 100644
--- a/drivers/media/video/gspca/m5602/m5602_mt9m111.c
+++ b/drivers/media/video/gspca/m5602/m5602_mt9m111.c
@@ -18,6 +18,23 @@
 
 #include "m5602_mt9m111.h"
 
+static int mt9m111_set_vflip(struct gspca_dev *gspca_dev, __s32 val);
+static int mt9m111_get_vflip(struct gspca_dev *gspca_dev, __s32 *val);
+static int mt9m111_get_hflip(struct gspca_dev *gspca_dev, __s32 *val);
+static int mt9m111_set_hflip(struct gspca_dev *gspca_dev, __s32 val);
+static int mt9m111_get_gain(struct gspca_dev *gspca_dev, __s32 *val);
+static int mt9m111_set_gain(struct gspca_dev *gspca_dev, __s32 val);
+static int mt9m111_set_auto_white_balance(struct gspca_dev *gspca_dev,
+                                         __s32 val);
+static int mt9m111_get_auto_white_balance(struct gspca_dev *gspca_dev,
+                                          __s32 *val);
+static int mt9m111_get_green_balance(struct gspca_dev *gspca_dev, __s32 *val);
+static int mt9m111_set_green_balance(struct gspca_dev *gspca_dev, __s32 val);
+static int mt9m111_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val);
+static int mt9m111_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val);
+static int mt9m111_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val);
+static int mt9m111_set_red_balance(struct gspca_dev *gspca_dev, __s32 val);
+
 static struct v4l2_pix_format mt9m111_modes[] = {
         {
                 640,
@@ -32,6 +49,7 @@ static struct v4l2_pix_format mt9m111_modes[] = {
 };
 
 const static struct ctrl mt9m111_ctrls[] = {
+#define VFLIP_IDX 0
         {
                 {
                         .id             = V4L2_CID_VFLIP,
@@ -44,7 +62,9 @@ const static struct ctrl mt9m111_ctrls[] = {
                 },
                 .set = mt9m111_set_vflip,
                 .get = mt9m111_get_vflip
-        }, {
+        },
+#define HFLIP_IDX 1
+        {
                 {
                         .id             = V4L2_CID_HFLIP,
                         .type           = V4L2_CTRL_TYPE_BOOLEAN,
@@ -56,7 +76,9 @@ const static struct ctrl mt9m111_ctrls[] = {
                 },
                 .set = mt9m111_set_hflip,
                 .get = mt9m111_get_hflip
-        }, {
+        },
+#define GAIN_IDX 2
+        {
                 {
                         .id             = V4L2_CID_GAIN,
                         .type           = V4L2_CTRL_TYPE_INTEGER,
@@ -64,21 +86,80 @@ const static struct ctrl mt9m111_ctrls[] = {
                         .minimum        = 0,
                         .maximum        = (INITIAL_MAX_GAIN - 1) * 2 * 2 * 2,
                         .step           = 1,
-                        .default_value  = DEFAULT_GAIN,
+                        .default_value  = MT9M111_DEFAULT_GAIN,
                         .flags          = V4L2_CTRL_FLAG_SLIDER
                 },
                 .set = mt9m111_set_gain,
                 .get = mt9m111_get_gain
-        }
+        },
+#define AUTO_WHITE_BALANCE_IDX 3
+        {
+                {
+                        .id             = V4L2_CID_AUTO_WHITE_BALANCE,
+                        .type           = V4L2_CTRL_TYPE_BOOLEAN,
+                        .name           = "auto white balance",
+                        .minimum        = 0,
+                        .maximum        = 1,
+                        .step           = 1,
+                        .default_value  = 0,
+                },
+                .set = mt9m111_set_auto_white_balance,
+                .get = mt9m111_get_auto_white_balance
+        },
+#define GREEN_BALANCE_IDX 4
+        {
+                {
+                        .id             = M5602_V4L2_CID_GREEN_BALANCE,
+                        .type           = V4L2_CTRL_TYPE_INTEGER,
+                        .name           = "green balance",
+                        .minimum        = 0x00,
+                        .maximum        = 0x7ff,
+                        .step           = 0x1,
+                        .default_value  = MT9M111_GREEN_GAIN_DEFAULT,
+                        .flags          = V4L2_CTRL_FLAG_SLIDER
+                },
+                .set = mt9m111_set_green_balance,
+                .get = mt9m111_get_green_balance
+        },
+#define BLUE_BALANCE_IDX 5
+        {
+                {
+                        .id             = V4L2_CID_BLUE_BALANCE,
+                        .type           = V4L2_CTRL_TYPE_INTEGER,
+                        .name           = "blue balance",
+                        .minimum        = 0x00,
+                        .maximum        = 0x7ff,
+                        .step           = 0x1,
+                        .default_value  = MT9M111_BLUE_GAIN_DEFAULT,
+                        .flags          = V4L2_CTRL_FLAG_SLIDER
+                },
+                .set = mt9m111_set_blue_balance,
+                .get = mt9m111_get_blue_balance
+        },
+#define RED_BALANCE_IDX 5
+        {
+                {
+                        .id             = V4L2_CID_RED_BALANCE,
+                        .type           = V4L2_CTRL_TYPE_INTEGER,
+                        .name           = "red balance",
+                        .minimum        = 0x00,
+                        .maximum        = 0x7ff,
+                        .step           = 0x1,
+                        .default_value  = MT9M111_RED_GAIN_DEFAULT,
+                        .flags          = V4L2_CTRL_FLAG_SLIDER
+                },
+                .set = mt9m111_set_red_balance,
+                .get = mt9m111_get_red_balance
+        },
 };
 
-
 static void mt9m111_dump_registers(struct sd *sd);
 
 int mt9m111_probe(struct sd *sd)
 {
         u8 data[2] = {0x00, 0x00};
         int i;
+        s32 *sensor_settings;
 
         if (force_sensor) {
                 if (force_sensor == MT9M111_SENSOR) {
@@ -117,16 +198,27 @@ int mt9m111_probe(struct sd *sd)
         return -ENODEV;
 
 sensor_found:
+        sensor_settings = kmalloc(ARRAY_SIZE(mt9m111_ctrls) * sizeof(s32),
+                                  GFP_KERNEL);
+        if (!sensor_settings)
+                return -ENOMEM;
+
         sd->gspca_dev.cam.cam_mode = mt9m111_modes;
         sd->gspca_dev.cam.nmodes = ARRAY_SIZE(mt9m111_modes);
         sd->desc->ctrls = mt9m111_ctrls;
         sd->desc->nctrls = ARRAY_SIZE(mt9m111_ctrls);
+
+        for (i = 0; i < ARRAY_SIZE(mt9m111_ctrls); i++)
+                sensor_settings[i] = mt9m111_ctrls[i].qctrl.default_value;
+        sd->sensor_priv = sensor_settings;
+
         return 0;
 }
 
 int mt9m111_init(struct sd *sd)
 {
         int i, err = 0;
+        s32 *sensor_settings = sd->sensor_priv;
 
         /* Init the sensor */
         for (i = 0; i < ARRAY_SIZE(init_mt9m111) && !err; i++) {
@@ -147,36 +239,154 @@ int mt9m111_init(struct sd *sd)
         if (dump_sensor)
                 mt9m111_dump_registers(sd);
 
-        return (err < 0) ? err : 0;
+        err = mt9m111_set_vflip(&sd->gspca_dev, sensor_settings[VFLIP_IDX]);
+        if (err < 0)
+                return err;
+
+        err = mt9m111_set_hflip(&sd->gspca_dev, sensor_settings[HFLIP_IDX]);
+        if (err < 0)
+                return err;
+
+        err = mt9m111_set_green_balance(&sd->gspca_dev,
+                                         sensor_settings[GREEN_BALANCE_IDX]);
+        if (err < 0)
+                return err;
+
+        err = mt9m111_set_blue_balance(&sd->gspca_dev,
+                                         sensor_settings[BLUE_BALANCE_IDX]);
+        if (err < 0)
+                return err;
+
+        err = mt9m111_set_red_balance(&sd->gspca_dev,
+                                        sensor_settings[RED_BALANCE_IDX]);
+        if (err < 0)
+                return err;
+
+        return mt9m111_set_gain(&sd->gspca_dev, sensor_settings[GAIN_IDX]);
 }
 
-int mt9m111_power_down(struct sd *sd)
+int mt9m111_start(struct sd *sd)
 {
-        return 0;
+        int i, err = 0;
+        u8 data[2];
+        struct cam *cam = &sd->gspca_dev.cam;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        int width = cam->cam_mode[sd->gspca_dev.curr_mode].width - 1;
+        int height = cam->cam_mode[sd->gspca_dev.curr_mode].height;
+
+        for (i = 0; i < ARRAY_SIZE(start_mt9m111) && !err; i++) {
+                if (start_mt9m111[i][0] == BRIDGE) {
+                        err = m5602_write_bridge(sd,
+                                start_mt9m111[i][1],
+                                start_mt9m111[i][2]);
+                } else {
+                        data[0] = start_mt9m111[i][2];
+                        data[1] = start_mt9m111[i][3];
+                        err = m5602_write_sensor(sd,
+                                start_mt9m111[i][1], data, 2);
+                }
+        }
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, (height >> 8) & 0xff);
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, (height & 0xff));
+        if (err < 0)
+                return err;
+
+        for (i = 0; i < 2 && !err; i++)
+                err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, 0);
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 0);
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 2);
+        if (err < 0)
+                return err;
+
+        for (i = 0; i < 2 && !err; i++)
+                err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA, 0);
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA,
+                                 (width >> 8) & 0xff);
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA, width & 0xff);
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 0);
+        if (err < 0)
+                return err;
+
+        switch (width) {
+        case 640:
+                PDEBUG(D_V4L2, "Configuring camera for VGA mode");
+                data[0] = MT9M111_RMB_OVER_SIZED;
+                data[1] = MT9M111_RMB_ROW_SKIP_2X |
+                          MT9M111_RMB_COLUMN_SKIP_2X |
+                          (sensor_settings[VFLIP_IDX] << 0) |
+                          (sensor_settings[HFLIP_IDX] << 1);
+
+                err = m5602_write_sensor(sd,
+                                         MT9M111_SC_R_MODE_CONTEXT_B, data, 2);
+                break;
+
+        case 320:
+                PDEBUG(D_V4L2, "Configuring camera for QVGA mode");
+                data[0] = MT9M111_RMB_OVER_SIZED;
+                data[1] = MT9M111_RMB_ROW_SKIP_4X |
+                                MT9M111_RMB_COLUMN_SKIP_4X |
+                                (sensor_settings[VFLIP_IDX] << 0) |
+                                (sensor_settings[HFLIP_IDX] << 1);
+                err = m5602_write_sensor(sd,
+                                         MT9M111_SC_R_MODE_CONTEXT_B, data, 2);
+                break;
+        }
+        return err;
 }
 
-int mt9m111_get_vflip(struct gspca_dev *gspca_dev, __s32 *val)
+void mt9m111_disconnect(struct sd *sd)
+{
+        sd->sensor = NULL;
+        kfree(sd->sensor_priv);
+}
+
+static int mt9m111_get_vflip(struct gspca_dev *gspca_dev, __s32 *val)
 {
-        int err;
-        u8 data[2] = {0x00, 0x00};
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
 
-        err = m5602_read_sensor(sd, MT9M111_SC_R_MODE_CONTEXT_B,
-                                  data, 2);
-        *val = data[0] & MT9M111_RMB_MIRROR_ROWS;
+        *val = sensor_settings[VFLIP_IDX];
         PDEBUG(D_V4L2, "Read vertical flip %d", *val);
 
-        return err;
+        return 0;
 }
 
-int mt9m111_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
+static int mt9m111_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
         u8 data[2] = {0x00, 0x00};
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
 
         PDEBUG(D_V4L2, "Set vertical flip to %d", val);
 
+        sensor_settings[VFLIP_IDX] = val;
+
+        /* The mt9m111 is flipped by default */
+        val = !val;
+
         /* Set the correct page map */
         err = m5602_write_sensor(sd, MT9M111_PAGE_MAP, data, 2);
         if (err < 0)
@@ -186,34 +396,37 @@ int mt9m111_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
         if (err < 0)
                 return err;
 
-        data[0] = (data[0] & 0xfe) | val;
+        data[1] = (data[1] & 0xfe) | val;
         err = m5602_write_sensor(sd, MT9M111_SC_R_MODE_CONTEXT_B,
                                    data, 2);
         return err;
 }
 
-int mt9m111_get_hflip(struct gspca_dev *gspca_dev, __s32 *val)
+static int mt9m111_get_hflip(struct gspca_dev *gspca_dev, __s32 *val)
 {
-        int err;
-        u8 data[2] = {0x00, 0x00};
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
 
-        err = m5602_read_sensor(sd, MT9M111_SC_R_MODE_CONTEXT_B,
-                                  data, 2);
-        *val = data[0] & MT9M111_RMB_MIRROR_COLS;
+        *val = sensor_settings[HFLIP_IDX];
         PDEBUG(D_V4L2, "Read horizontal flip %d", *val);
 
-        return err;
+        return 0;
 }
 
-int mt9m111_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
+static int mt9m111_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
         u8 data[2] = {0x00, 0x00};
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
 
         PDEBUG(D_V4L2, "Set horizontal flip to %d", val);
 
+        sensor_settings[HFLIP_IDX] = val;
+
+        /* The mt9m111 is flipped by default */
+        val = !val;
+
         /* Set the correct page map */
         err = m5602_write_sensor(sd, MT9M111_PAGE_MAP, data, 2);
         if (err < 0)
@@ -223,36 +436,62 @@ int mt9m111_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
         if (err < 0)
                 return err;
 
-        data[0] = (data[0] & 0xfd) | ((val << 1) & 0x02);
+        data[1] = (data[1] & 0xfd) | ((val << 1) & 0x02);
         err = m5602_write_sensor(sd, MT9M111_SC_R_MODE_CONTEXT_B,
                                         data, 2);
         return err;
 }
 
-int mt9m111_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
+static int mt9m111_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
 {
-        int err, tmp;
-        u8 data[2] = {0x00, 0x00};
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
 
-        err = m5602_read_sensor(sd, MT9M111_SC_GLOBAL_GAIN, data, 2);
-        tmp = ((data[1] << 8) | data[0]);
+        *val = sensor_settings[GAIN_IDX];
+        PDEBUG(D_V4L2, "Read gain %d", *val);
 
-        *val = ((tmp & (1 << 10)) * 2) |
-              ((tmp & (1 <<  9)) * 2) |
-              ((tmp & (1 <<  8)) * 2) |
-               (tmp & 0x7f);
+        return 0;
+}
 
-        PDEBUG(D_V4L2, "Read gain %d", *val);
+static int mt9m111_set_auto_white_balance(struct gspca_dev *gspca_dev,
+                                          __s32 val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+        int err;
+        u8 data[2];
+
+        err = m5602_read_sensor(sd, MT9M111_CP_OPERATING_MODE_CTL, data, 2);
+        if (err < 0)
+                return err;
+
+        sensor_settings[AUTO_WHITE_BALANCE_IDX] = val & 0x01;
+        data[1] = ((data[1] & 0xfd) | ((val & 0x01) << 1));
 
+        err = m5602_write_sensor(sd, MT9M111_CP_OPERATING_MODE_CTL, data, 2);
+
+        PDEBUG(D_V4L2, "Set auto white balance %d", val);
         return err;
 }
 
-int mt9m111_set_gain(struct gspca_dev *gspca_dev, __s32 val)
+static int mt9m111_get_auto_white_balance(struct gspca_dev *gspca_dev,
+                                          __s32 *val) {
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[AUTO_WHITE_BALANCE_IDX];
+        PDEBUG(D_V4L2, "Read auto white balance %d", *val);
+        return 0;
+}
+
+static int mt9m111_set_gain(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err, tmp;
         u8 data[2] = {0x00, 0x00};
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        sensor_settings[GAIN_IDX] = val;
 
         /* Set the correct page map */
         err = m5602_write_sensor(sd, MT9M111_PAGE_MAP, data, 2);
@@ -275,8 +514,8 @@ int mt9m111_set_gain(struct gspca_dev *gspca_dev, __s32 val)
         else
                 tmp = val;
 
-        data[1] = (tmp & 0xff00) >> 8;
-        data[0] = (tmp & 0xff);
+        data[1] = (tmp & 0xff);
+        data[0] = (tmp & 0xff00) >> 8;
         PDEBUG(D_V4L2, "tmp=%d, data[1]=%d, data[0]=%d", tmp,
                data[1], data[0]);
 
@@ -286,6 +525,89 @@ int mt9m111_set_gain(struct gspca_dev *gspca_dev, __s32 val)
         return err;
 }
 
+static int mt9m111_set_green_balance(struct gspca_dev *gspca_dev, __s32 val)
+{
+        int err;
+        u8 data[2];
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        sensor_settings[GREEN_BALANCE_IDX] = val;
+        data[1] = (val & 0xff);
+        data[0] = (val & 0xff00) >> 8;
+
+        PDEBUG(D_V4L2, "Set green balance %d", val);
+        err = m5602_write_sensor(sd, MT9M111_SC_GREEN_1_GAIN,
+                                 data, 2);
+        if (err < 0)
+                return err;
+
+        return m5602_write_sensor(sd, MT9M111_SC_GREEN_2_GAIN,
+                                  data, 2);
+}
+
+static int mt9m111_get_green_balance(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[GREEN_BALANCE_IDX];
+        PDEBUG(D_V4L2, "Read green balance %d", *val);
+        return 0;
+}
+
+static int mt9m111_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val)
+{
+        u8 data[2];
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        sensor_settings[BLUE_BALANCE_IDX] = val;
+        data[1] = (val & 0xff);
+        data[0] = (val & 0xff00) >> 8;
+
+        PDEBUG(D_V4L2, "Set blue balance %d", val);
+
+        return m5602_write_sensor(sd, MT9M111_SC_BLUE_GAIN,
+                                  data, 2);
+}
+
+static int mt9m111_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[BLUE_BALANCE_IDX];
+        PDEBUG(D_V4L2, "Read blue balance %d", *val);
+        return 0;
+}
+
+static int mt9m111_set_red_balance(struct gspca_dev *gspca_dev, __s32 val)
+{
+        u8 data[2];
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        sensor_settings[RED_BALANCE_IDX] = val;
+        data[1] = (val & 0xff);
+        data[0] = (val & 0xff00) >> 8;
+
+        PDEBUG(D_V4L2, "Set red balance %d", val);
+
+        return m5602_write_sensor(sd, MT9M111_SC_RED_GAIN,
+                                  data, 2);
+}
+
+static int mt9m111_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[RED_BALANCE_IDX];
+        PDEBUG(D_V4L2, "Read red balance %d", *val);
+        return 0;
+}
+
 static void mt9m111_dump_registers(struct sd *sd)
 {
         u8 address, value[2] = {0x00, 0x00};
diff --git a/drivers/media/video/gspca/m5602/m5602_mt9m111.h b/drivers/media/video/gspca/m5602/m5602_mt9m111.h
index 00c6db02bdb7..b3de77823091 100644
--- a/drivers/media/video/gspca/m5602/m5602_mt9m111.h
+++ b/drivers/media/video/gspca/m5602/m5602_mt9m111.h
@@ -37,7 +37,6 @@
 #define MT9M111_SC_VBLANK_CONTEXT_A             0x08
 #define MT9M111_SC_SHUTTER_WIDTH                0x09
 #define MT9M111_SC_ROW_SPEED                    0x0a
-
 #define MT9M111_SC_EXTRA_DELAY                  0x0b
 #define MT9M111_SC_SHUTTER_DELAY                0x0c
 #define MT9M111_SC_RESET                        0x0d
@@ -50,9 +49,6 @@
 #define MT9M111_SC_GREEN_2_GAIN                 0x2e
 #define MT9M111_SC_GLOBAL_GAIN                  0x2f
 
-#define MT9M111_RMB_MIRROR_ROWS                 (1 << 0)
-#define MT9M111_RMB_MIRROR_COLS                 (1 << 1)
-
 #define MT9M111_CONTEXT_CONTROL                 0xc8
 #define MT9M111_PAGE_MAP                        0xf0
 #define MT9M111_BYTEWISE_ADDRESS                0xf1
@@ -74,8 +70,37 @@
 #define MT9M111_COLORPIPE                       0x01
 #define MT9M111_CAMERA_CONTROL                  0x02
 
+#define MT9M111_RESET                           (1 << 0)
+#define MT9M111_RESTART                         (1 << 1)
+#define MT9M111_ANALOG_STANDBY                  (1 << 2)
+#define MT9M111_CHIP_ENABLE                     (1 << 3)
+#define MT9M111_CHIP_DISABLE                    (0 << 3)
+#define MT9M111_OUTPUT_DISABLE                  (1 << 4)
+#define MT9M111_SHOW_BAD_FRAMES                 (1 << 0)
+#define MT9M111_RESTART_BAD_FRAMES              (1 << 1)
+#define MT9M111_SYNCHRONIZE_CHANGES             (1 << 7)
+
+#define MT9M111_RMB_OVER_SIZED                  (1 << 0)
+#define MT9M111_RMB_MIRROR_ROWS                 (1 << 0)
+#define MT9M111_RMB_MIRROR_COLS                 (1 << 1)
+#define MT9M111_RMB_ROW_SKIP_2X                 (1 << 2)
+#define MT9M111_RMB_COLUMN_SKIP_2X              (1 << 3)
+#define MT9M111_RMB_ROW_SKIP_4X                 (1 << 4)
+#define MT9M111_RMB_COLUMN_SKIP_4X              (1 << 5)
+
+#define MT9M111_COLOR_MATRIX_BYPASS             (1 << 4)
+#define MT9M111_SEL_CONTEXT_B                   (1 << 3)
+
+#define MT9M111_TRISTATE_PIN_IN_STANDBY         (1 << 1)
+#define MT9M111_SOC_SOFT_STANDBY                (1 << 0)
+
+#define MT9M111_2D_DEFECT_CORRECTION_ENABLE     (1 << 0)
+
 #define INITIAL_MAX_GAIN                        64
-#define DEFAULT_GAIN                            283
+#define MT9M111_DEFAULT_GAIN                    283
+#define MT9M111_GREEN_GAIN_DEFAULT              0x20
+#define MT9M111_BLUE_GAIN_DEFAULT               0x20
+#define MT9M111_RED_GAIN_DEFAULT                0x20
 
 /*****************************************************************************/
 
@@ -85,16 +110,10 @@ extern int dump_sensor;
 
 int mt9m111_probe(struct sd *sd);
 int mt9m111_init(struct sd *sd);
-int mt9m111_power_down(struct sd *sd);
+int mt9m111_start(struct sd *sd);
+void mt9m111_disconnect(struct sd *sd);
 
-int mt9m111_set_vflip(struct gspca_dev *gspca_dev, __s32 val);
-int mt9m111_get_vflip(struct gspca_dev *gspca_dev, __s32 *val);
-int mt9m111_get_hflip(struct gspca_dev *gspca_dev, __s32 *val);
-int mt9m111_set_hflip(struct gspca_dev *gspca_dev, __s32 val);
-int mt9m111_get_gain(struct gspca_dev *gspca_dev, __s32 *val);
-int mt9m111_set_gain(struct gspca_dev *gspca_dev, __s32 val);
-
-const static struct m5602_sensor mt9m111 = {
+static const struct m5602_sensor mt9m111 = {
         .name = "MT9M111",
 
         .i2c_slave_id = 0xba,
@@ -102,7 +121,8 @@ const static struct m5602_sensor mt9m111 = {
 
         .probe = mt9m111_probe,
         .init = mt9m111_init,
-        .power_down = mt9m111_power_down
+        .disconnect = mt9m111_disconnect,
+        .start = mt9m111_start,
 };
 
 static const unsigned char preinit_mt9m111[][4] =
@@ -117,7 +137,14 @@ static const unsigned char preinit_mt9m111[][4] =
         {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
 
         {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0xff, 0xf7},
+        {SENSOR, MT9M111_SC_RESET,
+                MT9M111_RESET |
+                MT9M111_RESTART |
+                MT9M111_ANALOG_STANDBY |
+                MT9M111_CHIP_DISABLE,
+                MT9M111_SHOW_BAD_FRAMES |
+                MT9M111_RESTART_BAD_FRAMES |
+                MT9M111_SYNCHRONIZE_CHANGES},
 
         {BRIDGE, M5602_XB_GPIO_DIR, 0x05, 0x00},
         {BRIDGE, M5602_XB_GPIO_DAT, 0x04, 0x00},
@@ -145,731 +172,42 @@ static const unsigned char init_mt9m111[][4] =
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
         {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_CTRL, 0x00, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
         {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0xff, 0xff},
-        {SENSOR, MT9M111_SC_RESET, 0xff, 0xff},
-        {SENSOR, MT9M111_SC_RESET, 0xff, 0xde},
-        {SENSOR, MT9M111_SC_RESET, 0xff, 0xff},
-        {SENSOR, MT9M111_SC_RESET, 0xff, 0xf7},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x01},
 
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xb3, 0x00},
-
-        {SENSOR, MT9M111_CP_GLOBAL_CLK_CONTROL, 0xff, 0xff},
-
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x05, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x04, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x3e, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x3e, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x02, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0xff, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR_L, 0xff, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT_L, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x04, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x07, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x0b, 0x00},
         {BRIDGE, M5602_XB_GPIO_EN_H, 0x06, 0x00},
         {BRIDGE, M5602_XB_GPIO_EN_L, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_CLK_DIV, 0x0a, 0x00},
-
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x05},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x29},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x08},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_OPERATING_MODE_CTL, 0x00, 0x10},
-        {SENSOR, MT9M111_CP_LENS_CORRECTION_1, 0x04, 0x2a},
-        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_A, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_B, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_LUMA_OFFSET, 0x00, 0x00},
-        {SENSOR, MT9M111_CP_LUMA_CLIP, 0xff, 0x00},
-        {SENSOR, MT9M111_CP_OUTPUT_FORMAT_CTL2_CONTEXT_A, 0x14, 0x00},
-        {SENSOR, MT9M111_CP_OUTPUT_FORMAT_CTL2_CONTEXT_B, 0x14, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xcd, 0x00},
-
-        {SENSOR, 0xcd, 0x00, 0x0e},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xd0, 0x00},
-        {SENSOR, 0xd0, 0x00, 0x40},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x02},
-        {SENSOR, MT9M111_CC_AUTO_EXPOSURE_PARAMETER_18, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x28, 0x00},
-        {SENSOR, MT9M111_CC_AWB_PARAMETER_7, 0xef, 0x07},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x28, 0x00},
-        {SENSOR, MT9M111_CC_AWB_PARAMETER_7, 0xef, 0x03},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x33, 0x00},
-        {SENSOR, 0x33, 0x03, 0x49},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x33, 0x00},
-
-        {SENSOR, 0x33, 0x03, 0x49},
-        {SENSOR, 0x34, 0xc0, 0x19},
-        {SENSOR, 0x3f, 0x20, 0x20},
-        {SENSOR, 0x40, 0x20, 0x20},
-        {SENSOR, 0x5a, 0xc0, 0x0a},
-        {SENSOR, 0x70, 0x7b, 0x0a},
-        {SENSOR, 0x71, 0xff, 0x00},
-        {SENSOR, 0x72, 0x19, 0x0e},
-        {SENSOR, 0x73, 0x18, 0x0f},
-        {SENSOR, 0x74, 0x57, 0x32},
-        {SENSOR, 0x75, 0x56, 0x34},
-        {SENSOR, 0x76, 0x73, 0x35},
-        {SENSOR, 0x77, 0x30, 0x12},
-        {SENSOR, 0x78, 0x79, 0x02},
-        {SENSOR, 0x79, 0x75, 0x06},
-        {SENSOR, 0x7a, 0x77, 0x0a},
-        {SENSOR, 0x7b, 0x78, 0x09},
-        {SENSOR, 0x7c, 0x7d, 0x06},
-        {SENSOR, 0x7d, 0x31, 0x10},
-        {SENSOR, 0x7e, 0x00, 0x7e},
-        {SENSOR, 0x80, 0x59, 0x04},
-        {SENSOR, 0x81, 0x59, 0x04},
-        {SENSOR, 0x82, 0x57, 0x0a},
-        {SENSOR, 0x83, 0x58, 0x0b},
-        {SENSOR, 0x84, 0x47, 0x0c},
-        {SENSOR, 0x85, 0x48, 0x0e},
-        {SENSOR, 0x86, 0x5b, 0x02},
-        {SENSOR, 0x87, 0x00, 0x5c},
-        {SENSOR, MT9M111_CONTEXT_CONTROL, 0x00, 0x08},
-        {SENSOR, 0x60, 0x00, 0x80},
-        {SENSOR, 0x61, 0x00, 0x00},
-        {SENSOR, 0x62, 0x00, 0x00},
-        {SENSOR, 0x63, 0x00, 0x00},
-        {SENSOR, 0x64, 0x00, 0x00},
-
-        {SENSOR, MT9M111_SC_ROWSTART, 0x00, 0x0d},
-        {SENSOR, MT9M111_SC_COLSTART, 0x00, 0x18},
-        {SENSOR, MT9M111_SC_WINDOW_HEIGHT, 0x04, 0x04},
-        {SENSOR, MT9M111_SC_WINDOW_WIDTH, 0x05, 0x08},
-        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_B, 0x01, 0x38},
-        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_B, 0x00, 0x11},
-        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_A, 0x01, 0x38},
-        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_A, 0x00, 0x11},
-        {SENSOR, MT9M111_SC_R_MODE_CONTEXT_B, 0x01, 0x03},
-        {SENSOR, MT9M111_SC_R_MODE_CONTEXT_A, 0x01, 0x03},
-        {SENSOR, 0x30, 0x04, 0x00},
-
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81, 0x00},
-        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x04, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x04, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x05, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x07, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xa0, 0x00},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_SHUTTER_WIDTH, 0x01, 0xf4},
-        {SENSOR, MT9M111_SC_GLOBAL_GAIN, 0x00, 0xea},
-
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81, 0x00},
-        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x04, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x04, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x05, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x07, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x09},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x29},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x08},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x0c},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x04},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x01},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xb3, 0x00},
-        {SENSOR, MT9M111_CP_GLOBAL_CLK_CONTROL, 0x00, 0x03},
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x05, 0x00},
         {BRIDGE, M5602_XB_GPIO_DAT, 0x04, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x3e, 0x00},
         {BRIDGE, M5602_XB_GPIO_DIR_H, 0x3e, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x02, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0xff, 0x00},
         {BRIDGE, M5602_XB_GPIO_DIR_L, 0xff, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT_L, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x04, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x07, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x0b, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_CLK_DIV, 0x0a, 0x00},
-
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x05},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x29},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x08},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_OPERATING_MODE_CTL, 0x00, 0x10},
-        {SENSOR, MT9M111_CP_LENS_CORRECTION_1, 0x04, 0x2a},
-        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_A, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_B, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_LUMA_OFFSET, 0x00, 0x00},
-        {SENSOR, MT9M111_CP_LUMA_CLIP, 0xff, 0x00},
-        {SENSOR, MT9M111_CP_OUTPUT_FORMAT_CTL2_CONTEXT_A, 0x14, 0x00},
-        {SENSOR, MT9M111_CP_OUTPUT_FORMAT_CTL2_CONTEXT_B, 0x14, 0x00},
-
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xcd, 0x00},
-        {SENSOR, 0xcd, 0x00, 0x0e},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xd0, 0x00},
-        {SENSOR, 0xd0, 0x00, 0x40},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x02},
-        {SENSOR, MT9M111_CC_AUTO_EXPOSURE_PARAMETER_18, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x28, 0x00},
-        {SENSOR, MT9M111_CC_AWB_PARAMETER_7, 0xef, 0x07},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x28, 0x00},
-        {SENSOR, MT9M111_CC_AWB_PARAMETER_7, 0xef, 0x03},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x33, 0x00},
-        {SENSOR, 0x33, 0x03, 0x49},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x33, 0x00},
-
-        {SENSOR, 0x33, 0x03, 0x49},
-        {SENSOR, 0x34, 0xc0, 0x19},
-        {SENSOR, 0x3f, 0x20, 0x20},
-        {SENSOR, 0x40, 0x20, 0x20},
-        {SENSOR, 0x5a, 0xc0, 0x0a},
-        {SENSOR, 0x70, 0x7b, 0x0a},
-        {SENSOR, 0x71, 0xff, 0x00},
-        {SENSOR, 0x72, 0x19, 0x0e},
-        {SENSOR, 0x73, 0x18, 0x0f},
-        {SENSOR, 0x74, 0x57, 0x32},
-        {SENSOR, 0x75, 0x56, 0x34},
-        {SENSOR, 0x76, 0x73, 0x35},
-        {SENSOR, 0x77, 0x30, 0x12},
-        {SENSOR, 0x78, 0x79, 0x02},
-        {SENSOR, 0x79, 0x75, 0x06},
-        {SENSOR, 0x7a, 0x77, 0x0a},
-        {SENSOR, 0x7b, 0x78, 0x09},
-        {SENSOR, 0x7c, 0x7d, 0x06},
-        {SENSOR, 0x7d, 0x31, 0x10},
-        {SENSOR, 0x7e, 0x00, 0x7e},
-        {SENSOR, 0x80, 0x59, 0x04},
-        {SENSOR, 0x81, 0x59, 0x04},
-        {SENSOR, 0x82, 0x57, 0x0a},
-        {SENSOR, 0x83, 0x58, 0x0b},
-        {SENSOR, 0x84, 0x47, 0x0c},
-        {SENSOR, 0x85, 0x48, 0x0e},
-        {SENSOR, 0x86, 0x5b, 0x02},
-        {SENSOR, 0x87, 0x00, 0x5c},
-        {SENSOR, MT9M111_CONTEXT_CONTROL, 0x00, 0x08},
-        {SENSOR, 0x60, 0x00, 0x80},
-        {SENSOR, 0x61, 0x00, 0x00},
-        {SENSOR, 0x62, 0x00, 0x00},
-        {SENSOR, 0x63, 0x00, 0x00},
-        {SENSOR, 0x64, 0x00, 0x00},
-
-        {SENSOR, MT9M111_SC_ROWSTART, 0x00, 0x0d},
-        {SENSOR, MT9M111_SC_COLSTART, 0x00, 0x18},
-        {SENSOR, MT9M111_SC_WINDOW_HEIGHT, 0x04, 0x04},
-        {SENSOR, MT9M111_SC_WINDOW_WIDTH, 0x05, 0x08},
-        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_B, 0x01, 0x38},
-        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_B, 0x00, 0x11},
-        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_A, 0x01, 0x38},
-        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_A, 0x00, 0x11},
-        {SENSOR, MT9M111_SC_R_MODE_CONTEXT_B, 0x01, 0x03},
-        {SENSOR, MT9M111_SC_R_MODE_CONTEXT_A, 0x01, 0x03},
-        {SENSOR, 0x30, 0x04, 0x00},
-
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81, 0x00},
-        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x04, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x04, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x05, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x07, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xa0, 0x00},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_SHUTTER_WIDTH, 0x01, 0xf4},
-        {SENSOR, MT9M111_SC_GLOBAL_GAIN, 0x00, 0xea},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x09},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x29},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x08},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x0c},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x04},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x01},
-
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xb3, 0x00},
-        {SENSOR, MT9M111_CP_GLOBAL_CLK_CONTROL, 0x00, 0x03},
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x05, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x04, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x3e, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x3e, 0x00},
         {BRIDGE, M5602_XB_GPIO_DAT_H, 0x02, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0xff, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR_L, 0xff, 0x00},
         {BRIDGE, M5602_XB_GPIO_DAT_L, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x04, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
         {BRIDGE, M5602_XB_GPIO_DIR, 0x07, 0x00},
         {BRIDGE, M5602_XB_GPIO_DAT, 0x0b, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0x00, 0x00},
         {BRIDGE, M5602_XB_I2C_CLK_DIV, 0x0a, 0x00},
 
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x05},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
         {SENSOR, MT9M111_SC_RESET, 0x00, 0x29},
         {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
         {SENSOR, MT9M111_SC_RESET, 0x00, 0x08},
         {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_OPERATING_MODE_CTL, 0x00, 0x10},
+        {SENSOR, MT9M111_CP_OPERATING_MODE_CTL, 0x00,
+                        MT9M111_CP_OPERATING_MODE_CTL},
         {SENSOR, MT9M111_CP_LENS_CORRECTION_1, 0x04, 0x2a},
-        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_A, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_B, 0x00, 0x01},
+        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_A, 0x00,
+                                MT9M111_2D_DEFECT_CORRECTION_ENABLE},
+        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_B, 0x00,
+                                MT9M111_2D_DEFECT_CORRECTION_ENABLE},
         {SENSOR, MT9M111_CP_LUMA_OFFSET, 0x00, 0x00},
         {SENSOR, MT9M111_CP_LUMA_CLIP, 0xff, 0x00},
         {SENSOR, MT9M111_CP_OUTPUT_FORMAT_CTL2_CONTEXT_A, 0x14, 0x00},
         {SENSOR, MT9M111_CP_OUTPUT_FORMAT_CTL2_CONTEXT_B, 0x14, 0x00},
-
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xcd, 0x00},
         {SENSOR, 0xcd, 0x00, 0x0e},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xd0, 0x00},
         {SENSOR, 0xd0, 0x00, 0x40},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x02},
-        {SENSOR, MT9M111_CC_AUTO_EXPOSURE_PARAMETER_18, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x28, 0x00},
-        {SENSOR, MT9M111_CC_AWB_PARAMETER_7, 0xef, 0x07},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x28, 0x00},
-        {SENSOR, MT9M111_CC_AWB_PARAMETER_7, 0xef, 0x03},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x33, 0x00},
-        {SENSOR, 0x33, 0x03, 0x49},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x33, 0x00},
-
-        {SENSOR, 0x33, 0x03, 0x49},
-        {SENSOR, 0x34, 0xc0, 0x19},
-        {SENSOR, 0x3f, 0x20, 0x20},
-        {SENSOR, 0x40, 0x20, 0x20},
-        {SENSOR, 0x5a, 0xc0, 0x0a},
-        {SENSOR, 0x70, 0x7b, 0x0a},
-        {SENSOR, 0x71, 0xff, 0x00},
-        {SENSOR, 0x72, 0x19, 0x0e},
-        {SENSOR, 0x73, 0x18, 0x0f},
-        {SENSOR, 0x74, 0x57, 0x32},
-        {SENSOR, 0x75, 0x56, 0x34},
-        {SENSOR, 0x76, 0x73, 0x35},
-        {SENSOR, 0x77, 0x30, 0x12},
-        {SENSOR, 0x78, 0x79, 0x02},
-        {SENSOR, 0x79, 0x75, 0x06},
-        {SENSOR, 0x7a, 0x77, 0x0a},
-        {SENSOR, 0x7b, 0x78, 0x09},
-        {SENSOR, 0x7c, 0x7d, 0x06},
-        {SENSOR, 0x7d, 0x31, 0x10},
-        {SENSOR, 0x7e, 0x00, 0x7e},
-        {SENSOR, 0x80, 0x59, 0x04},
-        {SENSOR, 0x81, 0x59, 0x04},
-        {SENSOR, 0x82, 0x57, 0x0a},
-        {SENSOR, 0x83, 0x58, 0x0b},
-        {SENSOR, 0x84, 0x47, 0x0c},
-        {SENSOR, 0x85, 0x48, 0x0e},
-        {SENSOR, 0x86, 0x5b, 0x02},
-        {SENSOR, 0x87, 0x00, 0x5c},
-        {SENSOR, MT9M111_CONTEXT_CONTROL, 0x00, 0x08},
-        {SENSOR, 0x60, 0x00, 0x80},
-        {SENSOR, 0x61, 0x00, 0x00},
-        {SENSOR, 0x62, 0x00, 0x00},
-        {SENSOR, 0x63, 0x00, 0x00},
-        {SENSOR, 0x64, 0x00, 0x00},
 
-        {SENSOR, MT9M111_SC_ROWSTART, 0x00, 0x0d},
-        {SENSOR, MT9M111_SC_COLSTART, 0x00, 0x18},
-        {SENSOR, MT9M111_SC_WINDOW_HEIGHT, 0x04, 0x04},
-        {SENSOR, MT9M111_SC_WINDOW_WIDTH, 0x05, 0x08},
-        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_B, 0x01, 0x38},
-        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_B, 0x00, 0x11},
-        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_A, 0x01, 0x38},
-        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_A, 0x00, 0x11},
-        {SENSOR, MT9M111_SC_R_MODE_CONTEXT_B, 0x01, 0x03},
-        {SENSOR, MT9M111_SC_R_MODE_CONTEXT_A, 0x01, 0x03},
-        {SENSOR, 0x30, 0x04, 0x00},
-
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81, 0x00},
-        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x04, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x04, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x05, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x07, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xa0, 0x00},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_SHUTTER_WIDTH, 0x01, 0xf4},
-        {SENSOR, MT9M111_SC_GLOBAL_GAIN, 0x00, 0xea},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x09},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x29},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x08},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x0c},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x04},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x01},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xb3, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_CP_GLOBAL_CLK_CONTROL, 0x00, 0x03},
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x05, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x04, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x3e, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x3e, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x02, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0xff, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR_L, 0xff, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT_L, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x04, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x07, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x0b, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_CLK_DIV, 0x0a, 0x00},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x05},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x29},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x08},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_OPERATING_MODE_CTL, 0x00, 0x10},
-        {SENSOR, MT9M111_CP_LENS_CORRECTION_1, 0x04, 0x2a},
-        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_A, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_B, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_LUMA_OFFSET, 0x00, 0x00},
-        {SENSOR, MT9M111_CP_LUMA_CLIP, 0xff, 0x00},
-        {SENSOR, MT9M111_CP_OUTPUT_FORMAT_CTL2_CONTEXT_A, 0x14, 0x00},
-        {SENSOR, MT9M111_CP_OUTPUT_FORMAT_CTL2_CONTEXT_B, 0x14, 0x00},
-
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xcd, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, 0xcd, 0x00, 0x0e},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xd0, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, 0xd0, 0x00, 0x40},
         {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x02},
         {SENSOR, MT9M111_CC_AUTO_EXPOSURE_PARAMETER_18, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x28, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_CC_AWB_PARAMETER_7, 0xef, 0x07},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x28, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
         {SENSOR, MT9M111_CC_AWB_PARAMETER_7, 0xef, 0x03},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x33, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, 0x33, 0x03, 0x49},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x33, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-
-        {SENSOR, 0x33, 0x03, 0x49},
-        {SENSOR, 0x34, 0xc0, 0x19},
-        {SENSOR, 0x3f, 0x20, 0x20},
-        {SENSOR, 0x40, 0x20, 0x20},
-        {SENSOR, 0x5a, 0xc0, 0x0a},
-        {SENSOR, 0x70, 0x7b, 0x0a},
-        {SENSOR, 0x71, 0xff, 0x00},
-        {SENSOR, 0x72, 0x19, 0x0e},
-        {SENSOR, 0x73, 0x18, 0x0f},
-        {SENSOR, 0x74, 0x57, 0x32},
-        {SENSOR, 0x75, 0x56, 0x34},
-        {SENSOR, 0x76, 0x73, 0x35},
-        {SENSOR, 0x77, 0x30, 0x12},
-        {SENSOR, 0x78, 0x79, 0x02},
-        {SENSOR, 0x79, 0x75, 0x06},
-        {SENSOR, 0x7a, 0x77, 0x0a},
-        {SENSOR, 0x7b, 0x78, 0x09},
-        {SENSOR, 0x7c, 0x7d, 0x06},
-        {SENSOR, 0x7d, 0x31, 0x10},
-        {SENSOR, 0x7e, 0x00, 0x7e},
-        {SENSOR, 0x80, 0x59, 0x04},
-        {SENSOR, 0x81, 0x59, 0x04},
-        {SENSOR, 0x82, 0x57, 0x0a},
-        {SENSOR, 0x83, 0x58, 0x0b},
-        {SENSOR, 0x84, 0x47, 0x0c},
-        {SENSOR, 0x85, 0x48, 0x0e},
-        {SENSOR, 0x86, 0x5b, 0x02},
-        {SENSOR, 0x87, 0x00, 0x5c},
-        {SENSOR, MT9M111_CONTEXT_CONTROL, 0x00, 0x08},
-        {SENSOR, 0x60, 0x00, 0x80},
-        {SENSOR, 0x61, 0x00, 0x00},
-        {SENSOR, 0x62, 0x00, 0x00},
-        {SENSOR, 0x63, 0x00, 0x00},
-        {SENSOR, 0x64, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_ROWSTART, 0x00, 0x0d},
-        {SENSOR, MT9M111_SC_COLSTART, 0x00, 0x12},
-        {SENSOR, MT9M111_SC_WINDOW_HEIGHT, 0x04, 0x00},
-        {SENSOR, MT9M111_SC_WINDOW_WIDTH, 0x05, 0x10},
-        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_B, 0x01, 0x60},
-        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_B, 0x00, 0x11},
-        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_A, 0x01, 0x60},
-        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_A, 0x00, 0x11},
-        {SENSOR, MT9M111_SC_R_MODE_CONTEXT_B, 0x01, 0x0f},
-        {SENSOR, MT9M111_SC_R_MODE_CONTEXT_A, 0x01, 0x0f},
-        {SENSOR, 0x30, 0x04, 0x00},
-
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81, 0x00},
-        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0xe3, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x87, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, MT9M111_SC_SHUTTER_WIDTH, 0x01, 0x90},
-        {SENSOR, MT9M111_SC_GLOBAL_GAIN, 0x00, 0xe6},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x09},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x29},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x08},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x0c},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x04},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x01},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xb3, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_CP_GLOBAL_CLK_CONTROL, 0x00, 0x03},
 
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x05, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x04, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x3e, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x3e, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x02, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0xff, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR_L, 0xff, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT_L, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x04, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x07, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x0b, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_CLK_DIV, 0x0a, 0x00},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x05},
         {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x29},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x0d, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_SC_RESET, 0x00, 0x08},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_OPERATING_MODE_CTL, 0x00, 0x10},
-        {SENSOR, MT9M111_CP_LENS_CORRECTION_1, 0x04, 0x2a},
-        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_A, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_DEFECT_CORR_CONTEXT_B, 0x00, 0x01},
-        {SENSOR, MT9M111_CP_LUMA_OFFSET, 0x00, 0x00},
-        {SENSOR, MT9M111_CP_LUMA_CLIP, 0xff, 0x00},
-        {SENSOR, MT9M111_CP_OUTPUT_FORMAT_CTL2_CONTEXT_A, 0x14, 0x00},
-        {SENSOR, MT9M111_CP_OUTPUT_FORMAT_CTL2_CONTEXT_B, 0x14, 0x00},
-
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xcd, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, 0xcd, 0x00, 0x0e},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0xd0, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, 0xd0, 0x00, 0x40},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x02},
-        {SENSOR, MT9M111_CC_AUTO_EXPOSURE_PARAMETER_18, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x28, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_CC_AWB_PARAMETER_7, 0xef, 0x07},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x28, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, MT9M111_CC_AWB_PARAMETER_7, 0xef, 0x03},
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x33, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-        {SENSOR, 0x33, 0x03, 0x49},
-        {BRIDGE, M5602_XB_I2C_DEV_ADDR, 0xba, 0x00},
-        {BRIDGE, M5602_XB_I2C_REG_ADDR, 0x33, 0x00},
-        {BRIDGE, M5602_XB_I2C_CTRL, 0x1a, 0x00},
-
         {SENSOR, 0x33, 0x03, 0x49},
         {SENSOR, 0x34, 0xc0, 0x19},
         {SENSOR, 0x3f, 0x20, 0x20},
@@ -898,25 +236,29 @@ static const unsigned char init_mt9m111[][4] =
         {SENSOR, 0x85, 0x48, 0x0e},
         {SENSOR, 0x86, 0x5b, 0x02},
         {SENSOR, 0x87, 0x00, 0x5c},
-        {SENSOR, MT9M111_CONTEXT_CONTROL, 0x00, 0x08},
+        {SENSOR, MT9M111_CONTEXT_CONTROL, 0x00, MT9M111_SEL_CONTEXT_B},
         {SENSOR, 0x60, 0x00, 0x80},
         {SENSOR, 0x61, 0x00, 0x00},
         {SENSOR, 0x62, 0x00, 0x00},
         {SENSOR, 0x63, 0x00, 0x00},
         {SENSOR, 0x64, 0x00, 0x00},
 
-        {SENSOR, MT9M111_SC_ROWSTART, 0x00, 0x0d},
-        {SENSOR, MT9M111_SC_COLSTART, 0x00, 0x12},
-        {SENSOR, MT9M111_SC_WINDOW_HEIGHT, 0x04, 0x00},
-        {SENSOR, MT9M111_SC_WINDOW_WIDTH, 0x05, 0x10},
-        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_B, 0x01, 0x60},
-        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_B, 0x00, 0x11},
-        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_A, 0x01, 0x60},
-        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_A, 0x00, 0x11},
-        {SENSOR, MT9M111_SC_R_MODE_CONTEXT_B, 0x01, 0x0f},
-        {SENSOR, MT9M111_SC_R_MODE_CONTEXT_A, 0x01, 0x0f},
+        {SENSOR, MT9M111_SC_ROWSTART, 0x00, 0x0d}, /* 13 */
+        {SENSOR, MT9M111_SC_COLSTART, 0x00, 0x12}, /* 18 */
+        {SENSOR, MT9M111_SC_WINDOW_HEIGHT, 0x04, 0x00}, /* 1024 */
+        {SENSOR, MT9M111_SC_WINDOW_WIDTH, 0x05, 0x10}, /* 1296 */
+        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_B, 0x01, 0x60}, /* 352 */
+        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_B, 0x00, 0x11}, /* 17 */
+        {SENSOR, MT9M111_SC_HBLANK_CONTEXT_A, 0x01, 0x60}, /* 352 */
+        {SENSOR, MT9M111_SC_VBLANK_CONTEXT_A, 0x00, 0x11}, /* 17 */
+        {SENSOR, MT9M111_SC_R_MODE_CONTEXT_A, 0x01, 0x0f}, /* 271 */
         {SENSOR, 0x30, 0x04, 0x00},
+        /* Set number of blank rows chosen to 400 */
+        {SENSOR, MT9M111_SC_SHUTTER_WIDTH, 0x01, 0x90},
+};
 
+static const unsigned char start_mt9m111[][4] =
+{
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
         {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
@@ -928,25 +270,6 @@ static const unsigned char init_mt9m111[][4] =
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0xe0, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x02, 0x00}, /* 639*/
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x7f, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-
-        {SENSOR, MT9M111_PAGE_MAP, 0x00, 0x00},
-        /* Set number of blank rows chosen to 400 */
-        {SENSOR, MT9M111_SC_SHUTTER_WIDTH, 0x01, 0x90},
-        /* Set the global gain to 283 (of 512) */
-        {SENSOR, MT9M111_SC_GLOBAL_GAIN, 0x03, 0x63}
 };
 
 #endif
diff --git a/drivers/media/video/gspca/m5602/m5602_ov7660.c b/drivers/media/video/gspca/m5602/m5602_ov7660.c
new file mode 100644
index 000000000000..7aafeb7cfa07
--- /dev/null
+++ b/drivers/media/video/gspca/m5602/m5602_ov7660.c
@@ -0,0 +1,227 @@
+/*
+ * Driver for the ov7660 sensor
+ *
+ * Copyright (C) 2009 Erik Andrén
+ * Copyright (C) 2007 Ilyes Gouta. Based on the m5603x Linux Driver Project.
+ * Copyright (C) 2005 m5603x Linux Driver Project <m5602@x3ng.com.br>
+ *
+ * Portions of code to USB interface and ALi driver software,
+ * Copyright (c) 2006 Willem Duinker
+ * v4l2 interface modeled after the V4L2 driver
+ * for SN9C10x PC Camera Controllers
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation, version 2.
+ *
+ */
+
+#include "m5602_ov7660.h"
+
+static int ov7660_get_gain(struct gspca_dev *gspca_dev, __s32 *val);
+static int ov7660_set_gain(struct gspca_dev *gspca_dev, __s32 val);
+
+const static struct ctrl ov7660_ctrls[] = {
+#define GAIN_IDX 1
+        {
+                {
+                        .id             = V4L2_CID_GAIN,
+                        .type           = V4L2_CTRL_TYPE_INTEGER,
+                        .name           = "gain",
+                        .minimum        = 0x00,
+                        .maximum        = 0xff,
+                        .step           = 0x1,
+                        .default_value  = OV7660_DEFAULT_GAIN,
+                        .flags          = V4L2_CTRL_FLAG_SLIDER
+                },
+                .set = ov7660_set_gain,
+                .get = ov7660_get_gain
+        },
+};
+
+static struct v4l2_pix_format ov7660_modes[] = {
+        {
+                640,
+                480,
+                V4L2_PIX_FMT_SBGGR8,
+                V4L2_FIELD_NONE,
+                .sizeimage =
+                        640 * 480,
+                .bytesperline = 640,
+                .colorspace = V4L2_COLORSPACE_SRGB,
+                .priv = 0
+        }
+};
+
+static void ov7660_dump_registers(struct sd *sd);
+
+int ov7660_probe(struct sd *sd)
+{
+        int err = 0, i;
+        u8 prod_id = 0, ver_id = 0;
+
+        s32 *sensor_settings;
+
+        if (force_sensor) {
+                if (force_sensor == OV7660_SENSOR) {
+                        info("Forcing an %s sensor", ov7660.name);
+                        goto sensor_found;
+                }
+                /* If we want to force another sensor,
+                don't try to probe this one */
+                return -ENODEV;
+        }
+
+        /* Do the preinit */
+        for (i = 0; i < ARRAY_SIZE(preinit_ov7660) && !err; i++) {
+                u8 data[2];
+
+                if (preinit_ov7660[i][0] == BRIDGE) {
+                        err = m5602_write_bridge(sd,
+                                preinit_ov7660[i][1],
+                                preinit_ov7660[i][2]);
+                } else {
+                        data[0] = preinit_ov7660[i][2];
+                        err = m5602_write_sensor(sd,
+                                preinit_ov7660[i][1], data, 1);
+                }
+        }
+        if (err < 0)
+                return err;
+
+        if (m5602_read_sensor(sd, OV7660_PID, &prod_id, 1))
+                return -ENODEV;
+
+        if (m5602_read_sensor(sd, OV7660_VER, &ver_id, 1))
+                return -ENODEV;
+
+        info("Sensor reported 0x%x%x", prod_id, ver_id);
+
+        if ((prod_id == 0x76) && (ver_id == 0x60)) {
+                info("Detected a ov7660 sensor");
+                goto sensor_found;
+        }
+        return -ENODEV;
+
+sensor_found:
+        sensor_settings = kmalloc(
+                ARRAY_SIZE(ov7660_ctrls) * sizeof(s32), GFP_KERNEL);
+        if (!sensor_settings)
+                return -ENOMEM;
+
+        sd->gspca_dev.cam.cam_mode = ov7660_modes;
+        sd->gspca_dev.cam.nmodes = ARRAY_SIZE(ov7660_modes);
+        sd->desc->ctrls = ov7660_ctrls;
+        sd->desc->nctrls = ARRAY_SIZE(ov7660_ctrls);
+
+        for (i = 0; i < ARRAY_SIZE(ov7660_ctrls); i++)
+                sensor_settings[i] = ov7660_ctrls[i].qctrl.default_value;
+        sd->sensor_priv = sensor_settings;
+
+        return 0;
+}
+
+int ov7660_init(struct sd *sd)
+{
+        int i, err = 0;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        /* Init the sensor */
+        for (i = 0; i < ARRAY_SIZE(init_ov7660); i++) {
+                u8 data[2];
+
+                if (init_ov7660[i][0] == BRIDGE) {
+                        err = m5602_write_bridge(sd,
+                                init_ov7660[i][1],
+                                init_ov7660[i][2]);
+                } else {
+                        data[0] = init_ov7660[i][2];
+                        err = m5602_write_sensor(sd,
+                                        init_ov7660[i][1], data, 1);
+                }
+        }
+
+        if (dump_sensor)
+                ov7660_dump_registers(sd);
+
+        err = ov7660_set_gain(&sd->gspca_dev, sensor_settings[GAIN_IDX]);
+        if (err < 0)
+                return err;
+
+        return err;
+}
+
+int ov7660_start(struct sd *sd)
+{
+        return 0;
+}
+
+int ov7660_stop(struct sd *sd)
+{
+        return 0;
+}
+
+void ov7660_disconnect(struct sd *sd)
+{
+        ov7660_stop(sd);
+
+        sd->sensor = NULL;
+        kfree(sd->sensor_priv);
+}
+
+static int ov7660_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[GAIN_IDX];
+        PDEBUG(D_V4L2, "Read gain %d", *val);
+        return 0;
+}
+
+static int ov7660_set_gain(struct gspca_dev *gspca_dev, __s32 val)
+{
+        int err;
+        u8 i2c_data;
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        PDEBUG(D_V4L2, "Setting gain to %d", val);
+
+        sensor_settings[GAIN_IDX] = val;
+
+        err = m5602_write_sensor(sd, OV7660_GAIN, &i2c_data, 1);
+        return err;
+}
+
+static void ov7660_dump_registers(struct sd *sd)
+{
+        int address;
+        info("Dumping the ov7660 register state");
+        for (address = 0; address < 0xa9; address++) {
+                u8 value;
+                m5602_read_sensor(sd, address, &value, 1);
+                info("register 0x%x contains 0x%x",
+                     address, value);
+        }
+
+        info("ov7660 register state dump complete");
+
+        info("Probing for which registers that are read/write");
+        for (address = 0; address < 0xff; address++) {
+                u8 old_value, ctrl_value;
+                u8 test_value[2] = {0xff, 0xff};
+
+                m5602_read_sensor(sd, address, &old_value, 1);
+                m5602_write_sensor(sd, address, test_value, 1);
+                m5602_read_sensor(sd, address, &ctrl_value, 1);
+
+                if (ctrl_value == test_value[0])
+                        info("register 0x%x is writeable", address);
+                else
+                        info("register 0x%x is read only", address);
+
+                /* Restore original value */
+                m5602_write_sensor(sd, address, &old_value, 1);
+        }
+}
diff --git a/drivers/media/video/gspca/m5602/m5602_ov7660.h b/drivers/media/video/gspca/m5602/m5602_ov7660.h
new file mode 100644
index 000000000000..3f2c169a93ea
--- /dev/null
+++ b/drivers/media/video/gspca/m5602/m5602_ov7660.h
@@ -0,0 +1,279 @@
+/*
+ * Driver for the ov7660 sensor
+ *
+ * Copyright (C) 2009 Erik Andrén
+ * Copyright (C) 2007 Ilyes Gouta. Based on the m5603x Linux Driver Project.
+ * Copyright (C) 2005 m5603x Linux Driver Project <m5602@x3ng.com.br>
+ *
+ * Portions of code to USB interface and ALi driver software,
+ * Copyright (c) 2006 Willem Duinker
+ * v4l2 interface modeled after the V4L2 driver
+ * for SN9C10x PC Camera Controllers
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation, version 2.
+ *
+ */
+
+#ifndef M5602_OV7660_H_
+#define M5602_OV7660_H_
+
+#include "m5602_sensor.h"
+
+#define OV7660_GAIN             0x00
+#define OV7660_BLUE_GAIN        0x01
+#define OV7660_RED_GAIN         0x02
+#define OV7660_VREF             0x03
+#define OV7660_COM1             0x04
+#define OV7660_BAVE             0x05
+#define OV7660_GEAVE            0x06
+#define OV7660_AECHH            0x07
+#define OV7660_RAVE             0x08
+#define OV7660_COM2             0x09
+#define OV7660_PID              0x0a
+#define OV7660_VER              0x0b
+#define OV7660_COM3             0x0c
+#define OV7660_COM4             0x0d
+#define OV7660_COM5             0x0e
+#define OV7660_COM6             0x0f
+#define OV7660_AECH             0x10
+#define OV7660_CLKRC            0x11
+#define OV7660_COM7             0x12
+#define OV7660_COM8             0x13
+#define OV7660_COM9             0x14
+#define OV7660_COM10            0x15
+#define OV7660_RSVD16           0x16
+#define OV7660_HSTART           0x17
+#define OV7660_HSTOP            0x18
+#define OV7660_VSTART           0x19
+#define OV7660_VSTOP            0x1a
+#define OV7660_PSHFT            0x1b
+#define OV7660_MIDH             0x1c
+#define OV7660_MIDL             0x1d
+#define OV7660_MVFP             0x1e
+#define OV7660_LAEC             0x1f
+#define OV7660_BOS              0x20
+#define OV7660_GBOS             0x21
+#define OV7660_GROS             0x22
+#define OV7660_ROS              0x23
+#define OV7660_AEW              0x24
+#define OV7660_AEB              0x25
+#define OV7660_VPT              0x26
+#define OV7660_BBIAS            0x27
+#define OV7660_GbBIAS           0x28
+#define OV7660_RSVD29           0x29
+#define OV7660_RBIAS            0x2c
+#define OV7660_HREF             0x32
+#define OV7660_ADC              0x37
+#define OV7660_OFON             0x39
+#define OV7660_TSLB             0x3a
+#define OV7660_COM12            0x3c
+#define OV7660_COM13            0x3d
+#define OV7660_LCC1             0x62
+#define OV7660_LCC2             0x63
+#define OV7660_LCC3             0x64
+#define OV7660_LCC4             0x65
+#define OV7660_LCC5             0x66
+#define OV7660_HV               0x69
+#define OV7660_RSVDA1           0xa1
+
+#define OV7660_DEFAULT_GAIN             0x0e
+#define OV7660_DEFAULT_RED_GAIN 0x80
+#define OV7660_DEFAULT_BLUE_GAIN        0x80
+#define OV7660_DEFAULT_SATURATION       0x00
+#define OV7660_DEFAULT_EXPOSURE 0x20
+
+/* Kernel module parameters */
+extern int force_sensor;
+extern int dump_sensor;
+
+int ov7660_probe(struct sd *sd);
+int ov7660_init(struct sd *sd);
+int ov7660_start(struct sd *sd);
+int ov7660_stop(struct sd *sd);
+void ov7660_disconnect(struct sd *sd);
+
+const static struct m5602_sensor ov7660 = {
+        .name = "ov7660",
+        .i2c_slave_id = 0x42,
+        .i2c_regW = 1,
+        .probe = ov7660_probe,
+        .init = ov7660_init,
+        .start = ov7660_start,
+        .stop = ov7660_stop,
+        .disconnect = ov7660_disconnect,
+};
+
+static const unsigned char preinit_ov7660[][4] =
+{
+        {BRIDGE, M5602_XB_MCU_CLK_DIV, 0x02},
+        {BRIDGE, M5602_XB_MCU_CLK_CTRL, 0xb0},
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
+        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
+        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0d},
+        {BRIDGE, M5602_XB_SENSOR_CTRL, 0x00},
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x03},
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x03},
+        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
+        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
+
+        {SENSOR, OV7660_OFON, 0x0c},
+        {SENSOR, OV7660_COM2, 0x11},
+        {SENSOR, OV7660_COM7, 0x05},
+
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x01},
+        {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
+        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00},
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x08},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
+        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
+        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
+        {BRIDGE, M5602_XB_GPIO_DAT, 0x00},
+        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_EN_L, 0x00}
+};
+
+static const unsigned char init_ov7660[][4] =
+{
+        {BRIDGE, M5602_XB_MCU_CLK_DIV, 0x02},
+        {BRIDGE, M5602_XB_MCU_CLK_CTRL, 0xb0},
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
+        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
+        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0d},
+        {BRIDGE, M5602_XB_SENSOR_CTRL, 0x00},
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x03},
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x03},
+        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
+        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
+
+        {SENSOR, OV7660_OFON, 0x0c},
+        {SENSOR, OV7660_COM2, 0x11},
+        {SENSOR, OV7660_COM7, 0x05},
+
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x01},
+        {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
+        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00},
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x08},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
+        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
+        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
+        {BRIDGE, M5602_XB_GPIO_DAT, 0x00},
+        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_EN_L, 0x00},
+
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x02},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
+
+        {SENSOR, OV7660_AECH, OV7660_DEFAULT_EXPOSURE},
+        {SENSOR, OV7660_COM1, 0x00},
+
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x01},
+        {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
+        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00},
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x08},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
+
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
+        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
+        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
+        {BRIDGE, M5602_XB_GPIO_DAT, 0x00},
+        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_EN_L, 0x00},
+
+        {SENSOR, OV7660_COM7, 0x80},
+        {SENSOR, OV7660_CLKRC, 0x80},
+        {SENSOR, OV7660_BLUE_GAIN, 0x80},
+        {SENSOR, OV7660_RED_GAIN, 0x80},
+        {SENSOR, OV7660_COM9, 0x4c},
+        {SENSOR, OV7660_OFON, 0x43},
+        {SENSOR, OV7660_COM12, 0x28},
+        {SENSOR, OV7660_COM8, 0x00},
+        {SENSOR, OV7660_COM10, 0x40},
+        {SENSOR, OV7660_HSTART, 0x0c},
+        {SENSOR, OV7660_HSTOP, 0x61},
+        {SENSOR, OV7660_HREF, 0xa4},
+        {SENSOR, OV7660_PSHFT, 0x0b},
+        {SENSOR, OV7660_VSTART, 0x01},
+        {SENSOR, OV7660_VSTOP, 0x7a},
+        {SENSOR, OV7660_VREF, 0x00},
+        {SENSOR, OV7660_COM7, 0x05},
+        {SENSOR, OV7660_COM6, 0x4b},
+        {SENSOR, OV7660_BBIAS, 0x98},
+        {SENSOR, OV7660_GbBIAS, 0x98},
+        {SENSOR, OV7660_RSVD29, 0x98},
+        {SENSOR, OV7660_RBIAS, 0x98},
+        {SENSOR, OV7660_COM1, 0x00},
+        {SENSOR, OV7660_AECH, 0x00},
+        {SENSOR, OV7660_AECHH, 0x00},
+        {SENSOR, OV7660_ADC, 0x04},
+        {SENSOR, OV7660_COM13, 0x00},
+        {SENSOR, OV7660_RSVDA1, 0x23},
+        {SENSOR, OV7660_TSLB, 0x0d},
+        {SENSOR, OV7660_HV, 0x80},
+        {SENSOR, OV7660_LCC1, 0x00},
+        {SENSOR, OV7660_LCC2, 0x00},
+        {SENSOR, OV7660_LCC3, 0x10},
+        {SENSOR, OV7660_LCC4, 0x40},
+        {SENSOR, OV7660_LCC5, 0x01},
+
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
+        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
+        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
+        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81},
+        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82},
+        {BRIDGE, M5602_XB_SIG_INI, 0x01},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x08},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x01},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0xe0}, /* 480 */
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
+        {BRIDGE, M5602_XB_SIG_INI, 0x00},
+        {BRIDGE, M5602_XB_SIG_INI, 0x02},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x27}, /* 39 */
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x02},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0xa7}, /* 679 */
+        {BRIDGE, M5602_XB_SIG_INI, 0x00},
+
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
+
+        {SENSOR, OV7660_AECH, 0x20},
+        {SENSOR, OV7660_COM1, 0x00},
+        {SENSOR, OV7660_OFON, 0x0c},
+        {SENSOR, OV7660_COM2, 0x11},
+        {SENSOR, OV7660_COM7, 0x05},
+        {SENSOR, OV7660_BLUE_GAIN, 0x80},
+        {SENSOR, OV7660_RED_GAIN, 0x80},
+
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x01},
+        {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
+        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00},
+        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x08},
+        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0}
+};
+
+#endif
diff --git a/drivers/media/video/gspca/m5602/m5602_ov9650.c b/drivers/media/video/gspca/m5602/m5602_ov9650.c
index fc4548fd441d..c2739d6605a1 100644
--- a/drivers/media/video/gspca/m5602/m5602_ov9650.c
+++ b/drivers/media/video/gspca/m5602/m5602_ov9650.c
@@ -18,44 +18,87 @@
 
 #include "m5602_ov9650.h"
 
+static int ov9650_set_exposure(struct gspca_dev *gspca_dev, __s32 val);
+static int ov9650_get_exposure(struct gspca_dev *gspca_dev, __s32 *val);
+static int ov9650_get_gain(struct gspca_dev *gspca_dev, __s32 *val);
+static int ov9650_set_gain(struct gspca_dev *gspca_dev, __s32 val);
+static int ov9650_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val);
+static int ov9650_set_red_balance(struct gspca_dev *gspca_dev, __s32 val);
+static int ov9650_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val);
+static int ov9650_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val);
+static int ov9650_get_hflip(struct gspca_dev *gspca_dev, __s32 *val);
+static int ov9650_set_hflip(struct gspca_dev *gspca_dev, __s32 val);
+static int ov9650_get_vflip(struct gspca_dev *gspca_dev, __s32 *val);
+static int ov9650_set_vflip(struct gspca_dev *gspca_dev, __s32 val);
+static int ov9650_get_auto_white_balance(struct gspca_dev *gspca_dev,
+                                         __s32 *val);
+static int ov9650_set_auto_white_balance(struct gspca_dev *gspca_dev,
+                                         __s32 val);
+static int ov9650_get_auto_gain(struct gspca_dev *gspca_dev, __s32 *val);
+static int ov9650_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val);
+static int ov9650_get_auto_exposure(struct gspca_dev *gspca_dev, __s32 *val);
+static int ov9650_set_auto_exposure(struct gspca_dev *gspca_dev, __s32 val);
+
 /* Vertically and horizontally flips the image if matched, needed for machines
    where the sensor is mounted upside down */
 static
     const
         struct dmi_system_id ov9650_flip_dmi_table[] = {
         {
-                .ident = "ASUS A6VC",
+                .ident = "ASUS A6Ja",
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "A6VC")
+                        DMI_MATCH(DMI_PRODUCT_NAME, "A6J")
                 }
         },
         {
-                .ident = "ASUS A6VM",
+                .ident = "ASUS A6JC",
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "A6VM")
+                        DMI_MATCH(DMI_PRODUCT_NAME, "A6JC")
                 }
         },
         {
-                .ident = "ASUS A6JC",
+                .ident = "ASUS A6K",
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "A6JC")
+                        DMI_MATCH(DMI_PRODUCT_NAME, "A6K")
                 }
         },
         {
-                .ident = "ASUS A6Ja",
+                .ident = "ASUS A6Kt",
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "A6J")
+                        DMI_MATCH(DMI_PRODUCT_NAME, "A6Kt")
                 }
         },
         {
-                .ident = "ASUS A6Kt",
+                .ident = "ASUS A6VA",
                 .matches = {
                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "A6Kt")
+                        DMI_MATCH(DMI_PRODUCT_NAME, "A6VA")
+                }
+        },
+        {
+
+                .ident = "ASUS A6VC",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "A6VC")
+                }
+        },
+        {
+                .ident = "ASUS A6VM",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "A6VM")
+                }
+        },
+        {
+                .ident = "ASUS A7V",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "A7V")
                 }
         },
         {
@@ -68,7 +111,7 @@ static
         {}
 };
 
-const static struct ctrl ov9650_ctrls[] = {
+static const struct ctrl ov9650_ctrls[] = {
 #define EXPOSURE_IDX 0
         {
                 {
@@ -102,6 +145,7 @@ const static struct ctrl ov9650_ctrls[] = {
 #define RED_BALANCE_IDX 2
         {
                 {
+                        .id             = V4L2_CID_RED_BALANCE,
                         .type           = V4L2_CTRL_TYPE_INTEGER,
                         .name           = "red balance",
                         .minimum        = 0x00,
@@ -116,6 +160,7 @@ const static struct ctrl ov9650_ctrls[] = {
 #define BLUE_BALANCE_IDX 3
         {
                 {
+                        .id             = V4L2_CID_BLUE_BALANCE,
                         .type           = V4L2_CTRL_TYPE_INTEGER,
                         .name           = "blue balance",
                         .minimum        = 0x00,
@@ -182,7 +227,22 @@ const static struct ctrl ov9650_ctrls[] = {
                 },
                 .set = ov9650_set_auto_gain,
                 .get = ov9650_get_auto_gain
+        },
+#define AUTO_EXPOSURE_IDX 8
+        {
+                {
+                        .id             = V4L2_CID_EXPOSURE_AUTO,
+                        .type           = V4L2_CTRL_TYPE_BOOLEAN,
+                        .name           = "auto exposure",
+                        .minimum        = 0,
+                        .maximum        = 1,
+                        .step           = 1,
+                        .default_value  = 1
+                },
+                .set = ov9650_set_auto_exposure,
+                .get = ov9650_get_auto_exposure
         }
+
 };
 
 static struct v4l2_pix_format ov9650_modes[] = {
@@ -289,12 +349,6 @@ sensor_found:
         for (i = 0; i < ARRAY_SIZE(ov9650_ctrls); i++)
                 sensor_settings[i] = ov9650_ctrls[i].qctrl.default_value;
         sd->sensor_priv = sensor_settings;
-
-        if (dmi_check_system(ov9650_flip_dmi_table) && !err) {
-                info("vflip quirk active");
-                sensor_settings[VFLIP_IDX] = 1;
-        }
-
         return 0;
 }
 
@@ -316,7 +370,8 @@ int ov9650_init(struct sd *sd)
                         err = m5602_write_bridge(sd, init_ov9650[i][1], data);
         }
 
-        err = ov9650_set_exposure(&sd->gspca_dev, sensor_settings[EXPOSURE_IDX]);
+        err = ov9650_set_exposure(&sd->gspca_dev,
+                                   sensor_settings[EXPOSURE_IDX]);
         if (err < 0)
                 return err;
 
@@ -324,11 +379,13 @@ int ov9650_init(struct sd *sd)
         if (err < 0)
                 return err;
 
-        err = ov9650_set_red_balance(&sd->gspca_dev, sensor_settings[RED_BALANCE_IDX]);
+        err = ov9650_set_red_balance(&sd->gspca_dev,
+                                      sensor_settings[RED_BALANCE_IDX]);
         if (err < 0)
                 return err;
 
-        err = ov9650_set_blue_balance(&sd->gspca_dev, sensor_settings[BLUE_BALANCE_IDX]);
+        err = ov9650_set_blue_balance(&sd->gspca_dev,
+                                       sensor_settings[BLUE_BALANCE_IDX]);
         if (err < 0)
                 return err;
 
@@ -340,11 +397,18 @@ int ov9650_init(struct sd *sd)
         if (err < 0)
                 return err;
 
-        err = ov9650_set_auto_white_balance(&sd->gspca_dev, sensor_settings[AUTO_WHITE_BALANCE_IDX]);
+        err = ov9650_set_auto_exposure(&sd->gspca_dev,
+                                sensor_settings[AUTO_EXPOSURE_IDX]);
+        if (err < 0)
+                return err;
+
+        err = ov9650_set_auto_white_balance(&sd->gspca_dev,
+                                sensor_settings[AUTO_WHITE_BALANCE_IDX]);
         if (err < 0)
                 return err;
 
-        err = ov9650_set_auto_gain(&sd->gspca_dev, sensor_settings[AUTO_GAIN_CTRL_IDX]);
+        err = ov9650_set_auto_gain(&sd->gspca_dev,
+                                sensor_settings[AUTO_GAIN_CTRL_IDX]);
         return err;
 }
 
@@ -360,7 +424,10 @@ int ov9650_start(struct sd *sd)
         int ver_offs = cam->cam_mode[sd->gspca_dev.curr_mode].priv;
         int hor_offs = OV9650_LEFT_OFFSET;
 
-        if (sensor_settings[VFLIP_IDX])
+        if ((!dmi_check_system(ov9650_flip_dmi_table) &&
+                sensor_settings[VFLIP_IDX]) ||
+                (dmi_check_system(ov9650_flip_dmi_table) &&
+                !sensor_settings[VFLIP_IDX]))
                 ver_offs--;
 
         if (width <= 320)
@@ -406,6 +473,14 @@ int ov9650_start(struct sd *sd)
         if (err < 0)
                 return err;
 
+        err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 0);
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 2);
+        if (err < 0)
+                return err;
+
         err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA,
                                  (hor_offs >> 8) & 0xff);
         if (err < 0)
@@ -425,6 +500,10 @@ int ov9650_start(struct sd *sd)
         if (err < 0)
                 return err;
 
+        err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 0);
+        if (err < 0)
+                return err;
+
         switch (width) {
         case 640:
                 PDEBUG(D_V4L2, "Configuring camera for VGA mode");
@@ -467,32 +546,15 @@ int ov9650_stop(struct sd *sd)
         return m5602_write_sensor(sd, OV9650_COM2, &data, 1);
 }
 
-int ov9650_power_down(struct sd *sd)
-{
-        int i, err = 0;
-        for (i = 0; i < ARRAY_SIZE(power_down_ov9650) && !err; i++) {
-                u8 data = power_down_ov9650[i][2];
-                if (power_down_ov9650[i][0] == SENSOR)
-                        err = m5602_write_sensor(sd,
-                                            power_down_ov9650[i][1], &data, 1);
-                else
-                        err = m5602_write_bridge(sd, power_down_ov9650[i][1],
-                                                 data);
-        }
-
-        return err;
-}
-
 void ov9650_disconnect(struct sd *sd)
 {
         ov9650_stop(sd);
-        ov9650_power_down(sd);
 
         sd->sensor = NULL;
         kfree(sd->sensor_priv);
 }
 
-int ov9650_get_exposure(struct gspca_dev *gspca_dev, __s32 *val)
+static int ov9650_get_exposure(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
         s32 *sensor_settings = sd->sensor_priv;
@@ -502,7 +564,7 @@ int ov9650_get_exposure(struct gspca_dev *gspca_dev, __s32 *val)
         return 0;
 }
 
-int ov9650_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
+static int ov9650_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
         s32 *sensor_settings = sd->sensor_priv;
@@ -532,7 +594,7 @@ int ov9650_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
         return err;
 }
 
-int ov9650_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
+static int ov9650_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
         s32 *sensor_settings = sd->sensor_priv;
@@ -542,7 +604,7 @@ int ov9650_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
         return 0;
 }
 
-int ov9650_set_gain(struct gspca_dev *gspca_dev, __s32 val)
+static int ov9650_set_gain(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
         u8 i2c_data;
@@ -573,7 +635,7 @@ int ov9650_set_gain(struct gspca_dev *gspca_dev, __s32 val)
         return err;
 }
 
-int ov9650_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val)
+static int ov9650_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
         s32 *sensor_settings = sd->sensor_priv;
@@ -583,7 +645,7 @@ int ov9650_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val)
         return 0;
 }
 
-int ov9650_set_red_balance(struct gspca_dev *gspca_dev, __s32 val)
+static int ov9650_set_red_balance(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
         u8 i2c_data;
@@ -599,7 +661,7 @@ int ov9650_set_red_balance(struct gspca_dev *gspca_dev, __s32 val)
         return err;
 }
 
-int ov9650_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val)
+static int ov9650_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
         s32 *sensor_settings = sd->sensor_priv;
@@ -610,7 +672,7 @@ int ov9650_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val)
         return 0;
 }
 
-int ov9650_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val)
+static int ov9650_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
         u8 i2c_data;
@@ -626,7 +688,7 @@ int ov9650_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val)
         return err;
 }
 
-int ov9650_get_hflip(struct gspca_dev *gspca_dev, __s32 *val)
+static int ov9650_get_hflip(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
         s32 *sensor_settings = sd->sensor_priv;
@@ -636,7 +698,7 @@ int ov9650_get_hflip(struct gspca_dev *gspca_dev, __s32 *val)
         return 0;
 }
 
-int ov9650_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
+static int ov9650_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
         u8 i2c_data;
@@ -646,13 +708,20 @@ int ov9650_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
         PDEBUG(D_V4L2, "Set horizontal flip to %d", val);
 
         sensor_settings[HFLIP_IDX] = val;
-        i2c_data = ((val & 0x01) << 5) | (sensor_settings[VFLIP_IDX] << 4);
+
+        if (!dmi_check_system(ov9650_flip_dmi_table))
+                i2c_data = ((val & 0x01) << 5) |
+                                (sensor_settings[VFLIP_IDX] << 4);
+        else
+                i2c_data = ((val & 0x01) << 5) |
+                                (!sensor_settings[VFLIP_IDX] << 4);
+
         err = m5602_write_sensor(sd, OV9650_MVFP, &i2c_data, 1);
 
         return err;
 }
 
-int ov9650_get_vflip(struct gspca_dev *gspca_dev, __s32 *val)
+static int ov9650_get_vflip(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
         s32 *sensor_settings = sd->sensor_priv;
@@ -663,7 +732,7 @@ int ov9650_get_vflip(struct gspca_dev *gspca_dev, __s32 *val)
         return 0;
 }
 
-int ov9650_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
+static int ov9650_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
         u8 i2c_data;
@@ -673,6 +742,9 @@ int ov9650_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
         PDEBUG(D_V4L2, "Set vertical flip to %d", val);
         sensor_settings[VFLIP_IDX] = val;
 
+        if (dmi_check_system(ov9650_flip_dmi_table))
+                val = !val;
+
         i2c_data = ((val & 0x01) << 4) | (sensor_settings[VFLIP_IDX] << 5);
         err = m5602_write_sensor(sd, OV9650_MVFP, &i2c_data, 1);
         if (err < 0)
@@ -685,48 +757,38 @@ int ov9650_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
         return err;
 }
 
-int ov9650_get_brightness(struct gspca_dev *gspca_dev, __s32 *val)
+static int ov9650_get_auto_exposure(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
         s32 *sensor_settings = sd->sensor_priv;
 
-        *val = sensor_settings[GAIN_IDX];
-        PDEBUG(D_V4L2, "Read gain %d", *val);
-
+        *val = sensor_settings[AUTO_EXPOSURE_IDX];
+        PDEBUG(D_V4L2, "Read auto exposure control %d", *val);
         return 0;
 }
 
-int ov9650_set_brightness(struct gspca_dev *gspca_dev, __s32 val)
+static int ov9650_set_auto_exposure(struct gspca_dev *gspca_dev,
+                                    __s32 val)
 {
         int err;
         u8 i2c_data;
         struct sd *sd = (struct sd *) gspca_dev;
         s32 *sensor_settings = sd->sensor_priv;
 
-        PDEBUG(D_V4L2, "Set gain to %d", val);
-
-        sensor_settings[GAIN_IDX] = val;
+        PDEBUG(D_V4L2, "Set auto exposure control to %d", val);
 
-        /* Read the OV9650_VREF register first to avoid
-                corrupting the VREF high and low bits */
-        err = m5602_read_sensor(sd, OV9650_VREF, &i2c_data, 1);
-        if (err < 0)
-                return err;
-
-        /* Mask away all uninteresting bits */
-        i2c_data = ((val & 0x0300) >> 2) | (i2c_data & 0x3F);
-        err = m5602_write_sensor(sd, OV9650_VREF, &i2c_data, 1);
+        sensor_settings[AUTO_EXPOSURE_IDX] = val;
+        err = m5602_read_sensor(sd, OV9650_COM8, &i2c_data, 1);
         if (err < 0)
                 return err;
 
-        /* The 8 LSBs */
-        i2c_data = val & 0xff;
-        err = m5602_write_sensor(sd, OV9650_GAIN, &i2c_data, 1);
+        i2c_data = ((i2c_data & 0xfe) | ((val & 0x01) << 0));
 
-        return err;
+        return m5602_write_sensor(sd, OV9650_COM8, &i2c_data, 1);
 }
 
-int ov9650_get_auto_white_balance(struct gspca_dev *gspca_dev, __s32 *val)
+static int ov9650_get_auto_white_balance(struct gspca_dev *gspca_dev,
+                                         __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
         s32 *sensor_settings = sd->sensor_priv;
@@ -735,7 +797,8 @@ int ov9650_get_auto_white_balance(struct gspca_dev *gspca_dev, __s32 *val)
         return 0;
 }
 
-int ov9650_set_auto_white_balance(struct gspca_dev *gspca_dev, __s32 val)
+static int ov9650_set_auto_white_balance(struct gspca_dev *gspca_dev,
+                                         __s32 val)
 {
         int err;
         u8 i2c_data;
@@ -755,7 +818,7 @@ int ov9650_set_auto_white_balance(struct gspca_dev *gspca_dev, __s32 val)
         return err;
 }
 
-int ov9650_get_auto_gain(struct gspca_dev *gspca_dev, __s32 *val)
+static int ov9650_get_auto_gain(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
         s32 *sensor_settings = sd->sensor_priv;
@@ -765,7 +828,7 @@ int ov9650_get_auto_gain(struct gspca_dev *gspca_dev, __s32 *val)
         return 0;
 }
 
-int ov9650_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val)
+static int ov9650_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
         u8 i2c_data;
@@ -780,9 +843,8 @@ int ov9650_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val)
                 return err;
 
         i2c_data = ((i2c_data & 0xfb) | ((val & 0x01) << 2));
-        err = m5602_write_sensor(sd, OV9650_COM8, &i2c_data, 1);
 
-        return err;
+        return m5602_write_sensor(sd, OV9650_COM8, &i2c_data, 1);
 }
 
 static void ov9650_dump_registers(struct sd *sd)
diff --git a/drivers/media/video/gspca/m5602/m5602_ov9650.h b/drivers/media/video/gspca/m5602/m5602_ov9650.h
index fcc54e4c0f4f..c98c40d69e05 100644
--- a/drivers/media/video/gspca/m5602/m5602_ov9650.h
+++ b/drivers/media/video/gspca/m5602/m5602_ov9650.h
@@ -120,6 +120,10 @@
 #define OV9650_SOFT_SLEEP               (1 << 4)
 #define OV9650_OUTPUT_DRIVE_2X          (1 << 0)
 
+#define OV9650_DENOISE_ENABLE           (1 << 5)
+#define OV9650_WHITE_PIXEL_ENABLE       (1 << 1)
+#define OV9650_WHITE_PIXEL_OPTION       (1 << 0)
+
 #define OV9650_LEFT_OFFSET              0x62
 
 #define GAIN_DEFAULT                    0x14
@@ -137,29 +141,9 @@ int ov9650_probe(struct sd *sd);
 int ov9650_init(struct sd *sd);
 int ov9650_start(struct sd *sd);
 int ov9650_stop(struct sd *sd);
-int ov9650_power_down(struct sd *sd);
 void ov9650_disconnect(struct sd *sd);
 
-int ov9650_set_exposure(struct gspca_dev *gspca_dev, __s32 val);
-int ov9650_get_exposure(struct gspca_dev *gspca_dev, __s32 *val);
-int ov9650_get_gain(struct gspca_dev *gspca_dev, __s32 *val);
-int ov9650_set_gain(struct gspca_dev *gspca_dev, __s32 val);
-int ov9650_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val);
-int ov9650_set_red_balance(struct gspca_dev *gspca_dev, __s32 val);
-int ov9650_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val);
-int ov9650_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val);
-int ov9650_get_hflip(struct gspca_dev *gspca_dev, __s32 *val);
-int ov9650_set_hflip(struct gspca_dev *gspca_dev, __s32 val);
-int ov9650_get_vflip(struct gspca_dev *gspca_dev, __s32 *val);
-int ov9650_set_vflip(struct gspca_dev *gspca_dev, __s32 val);
-int ov9650_get_brightness(struct gspca_dev *gspca_dev, __s32 *val);
-int ov9650_set_brightness(struct gspca_dev *gspca_dev, __s32 val);
-int ov9650_get_auto_white_balance(struct gspca_dev *gspca_dev, __s32 *val);
-int ov9650_set_auto_white_balance(struct gspca_dev *gspca_dev, __s32 val);
-int ov9650_get_auto_gain(struct gspca_dev *gspca_dev, __s32 *val);
-int ov9650_set_auto_gain(struct gspca_dev *gspca_dev, __s32 val);
-
-const static struct m5602_sensor ov9650 = {
+static const struct m5602_sensor ov9650 = {
         .name = "OV9650",
         .i2c_slave_id = 0x60,
         .i2c_regW = 1,
@@ -167,7 +151,6 @@ const static struct m5602_sensor ov9650 = {
         .init = ov9650_init,
         .start = ov9650_start,
         .stop = ov9650_stop,
-        .power_down = ov9650_power_down,
         .disconnect = ov9650_disconnect,
 };
 
@@ -219,7 +202,7 @@ static const unsigned char init_ov9650[][3] =
         /* Reset chip */
         {SENSOR, OV9650_COM7, OV9650_REGISTER_RESET},
         /* One extra reset is needed in order to make the sensor behave
-           properly when resuming from ram */
+           properly when resuming from ram, could be a timing issue */
         {SENSOR, OV9650_COM7, OV9650_REGISTER_RESET},
 
         /* Enable double clock */
@@ -229,8 +212,7 @@ static const unsigned char init_ov9650[][3] =
 
         /* Set fast AGC/AEC algorithm with unlimited step size */
         {SENSOR, OV9650_COM8, OV9650_FAST_AGC_AEC |
-                              OV9650_AEC_UNLIM_STEP_SIZE |
-                              OV9650_AWB_EN | OV9650_AGC_EN},
+                              OV9650_AEC_UNLIM_STEP_SIZE},
 
         {SENSOR, OV9650_CHLF, 0x10},
         {SENSOR, OV9650_ARBLM, 0xbf},
@@ -301,8 +283,11 @@ static const unsigned char init_ov9650[][3] =
         {SENSOR, OV9650_VREF, 0x10},
         {SENSOR, OV9650_ADC, 0x04},
         {SENSOR, OV9650_HV, 0x40},
+
         /* Enable denoise, and white-pixel erase */
-        {SENSOR, OV9650_COM22, 0x23},
+        {SENSOR, OV9650_COM22, OV9650_DENOISE_ENABLE |
+                 OV9650_WHITE_PIXEL_ENABLE |
+                 OV9650_WHITE_PIXEL_OPTION},
 
         /* Enable VARIOPIXEL */
         {SENSOR, OV9650_COM3, OV9650_VARIOPIXEL},
@@ -312,26 +297,6 @@ static const unsigned char init_ov9650[][3] =
         {SENSOR, OV9650_COM2, OV9650_SOFT_SLEEP | OV9650_OUTPUT_DRIVE_2X},
 };
 
-static const unsigned char power_down_ov9650[][3] =
-{
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x04},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
-        {SENSOR, OV9650_COM7, 0x80},
-        {SENSOR, OV9650_OFON, 0xf4},
-        {SENSOR, OV9650_MVFP, 0x80},
-        {SENSOR, OV9650_DBLV, 0x3f},
-        {SENSOR, OV9650_RSVD36, 0x49},
-        {SENSOR, OV9650_COM7, 0x05},
-
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0x06},
-        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x02},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x04},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
-};
-
 static const unsigned char res_init_ov9650[][3] =
 {
         {SENSOR, OV9650_COM2, OV9650_OUTPUT_DRIVE_2X},
diff --git a/drivers/media/video/gspca/m5602/m5602_po1030.c b/drivers/media/video/gspca/m5602/m5602_po1030.c
index eaddf488bad1..8d74d8065b79 100644
--- a/drivers/media/video/gspca/m5602/m5602_po1030.c
+++ b/drivers/media/video/gspca/m5602/m5602_po1030.c
@@ -18,6 +18,29 @@
 
 #include "m5602_po1030.h"
 
+static int po1030_get_exposure(struct gspca_dev *gspca_dev, __s32 *val);
+static int po1030_set_exposure(struct gspca_dev *gspca_dev, __s32 val);
+static int po1030_get_gain(struct gspca_dev *gspca_dev, __s32 *val);
+static int po1030_set_gain(struct gspca_dev *gspca_dev, __s32 val);
+static int po1030_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val);
+static int po1030_set_red_balance(struct gspca_dev *gspca_dev, __s32 val);
+static int po1030_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val);
+static int po1030_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val);
+static int po1030_get_green_balance(struct gspca_dev *gspca_dev, __s32 *val);
+static int po1030_set_green_balance(struct gspca_dev *gspca_dev, __s32 val);
+static int po1030_get_hflip(struct gspca_dev *gspca_dev, __s32 *val);
+static int po1030_set_hflip(struct gspca_dev *gspca_dev, __s32 val);
+static int po1030_get_vflip(struct gspca_dev *gspca_dev, __s32 *val);
+static int po1030_set_vflip(struct gspca_dev *gspca_dev, __s32 val);
+static int po1030_set_auto_white_balance(struct gspca_dev *gspca_dev,
+                                         __s32 val);
+static int po1030_get_auto_white_balance(struct gspca_dev *gspca_dev,
+                                         __s32 *val);
+static int po1030_set_auto_exposure(struct gspca_dev *gspca_dev,
+                                         __s32 val);
+static int po1030_get_auto_exposure(struct gspca_dev *gspca_dev,
+                                         __s32 *val);
+
 static struct v4l2_pix_format po1030_modes[] = {
         {
                 640,
@@ -27,11 +50,12 @@ static struct v4l2_pix_format po1030_modes[] = {
                 .sizeimage = 640 * 480,
                 .bytesperline = 640,
                 .colorspace = V4L2_COLORSPACE_SRGB,
-                .priv = 0
+                .priv = 2
         }
 };
 
-const static struct ctrl po1030_ctrls[] = {
+static const struct ctrl po1030_ctrls[] = {
+#define GAIN_IDX 0
         {
                 {
                         .id             = V4L2_CID_GAIN,
@@ -45,7 +69,9 @@ const static struct ctrl po1030_ctrls[] = {
                 },
                 .set = po1030_set_gain,
                 .get = po1030_get_gain
-        }, {
+        },
+#define EXPOSURE_IDX 1
+        {
                 {
                         .id             = V4L2_CID_EXPOSURE,
                         .type           = V4L2_CTRL_TYPE_INTEGER,
@@ -58,7 +84,9 @@ const static struct ctrl po1030_ctrls[] = {
                 },
                 .set = po1030_set_exposure,
                 .get = po1030_get_exposure
-        }, {
+        },
+#define RED_BALANCE_IDX 2
+        {
                 {
                         .id             = V4L2_CID_RED_BALANCE,
                         .type           = V4L2_CTRL_TYPE_INTEGER,
@@ -71,7 +99,9 @@ const static struct ctrl po1030_ctrls[] = {
                 },
                 .set = po1030_set_red_balance,
                 .get = po1030_get_red_balance
-        }, {
+        },
+#define BLUE_BALANCE_IDX 3
+        {
                 {
                         .id             = V4L2_CID_BLUE_BALANCE,
                         .type           = V4L2_CTRL_TYPE_INTEGER,
@@ -84,7 +114,9 @@ const static struct ctrl po1030_ctrls[] = {
                 },
                 .set = po1030_set_blue_balance,
                 .get = po1030_get_blue_balance
-        }, {
+        },
+#define HFLIP_IDX 4
+        {
                 {
                         .id             = V4L2_CID_HFLIP,
                         .type           = V4L2_CTRL_TYPE_BOOLEAN,
@@ -96,7 +128,9 @@ const static struct ctrl po1030_ctrls[] = {
                 },
                 .set = po1030_set_hflip,
                 .get = po1030_get_hflip
-        }, {
+        },
+#define VFLIP_IDX 5
+        {
                 {
                         .id             = V4L2_CID_VFLIP,
                         .type           = V4L2_CTRL_TYPE_BOOLEAN,
@@ -108,14 +142,58 @@ const static struct ctrl po1030_ctrls[] = {
                 },
                 .set = po1030_set_vflip,
                 .get = po1030_get_vflip
-        }
+        },
+#define AUTO_WHITE_BALANCE_IDX 6
+        {
+                {
+                        .id             = V4L2_CID_AUTO_WHITE_BALANCE,
+                        .type           = V4L2_CTRL_TYPE_BOOLEAN,
+                        .name           = "auto white balance",
+                        .minimum        = 0,
+                        .maximum        = 1,
+                        .step           = 1,
+                        .default_value  = 0,
+                },
+                .set = po1030_set_auto_white_balance,
+                .get = po1030_get_auto_white_balance
+        },
+#define AUTO_EXPOSURE_IDX 7
+        {
+                {
+                        .id             = V4L2_CID_EXPOSURE_AUTO,
+                        .type           = V4L2_CTRL_TYPE_BOOLEAN,
+                        .name           = "auto exposure",
+                        .minimum        = 0,
+                        .maximum        = 1,
+                        .step           = 1,
+                        .default_value  = 0,
+                },
+                .set = po1030_set_auto_exposure,
+                .get = po1030_get_auto_exposure
+        },
+#define GREEN_BALANCE_IDX 8
+        {
+                {
+                        .id             = M5602_V4L2_CID_GREEN_BALANCE,
+                        .type           = V4L2_CTRL_TYPE_INTEGER,
+                        .name           = "green balance",
+                        .minimum        = 0x00,
+                        .maximum        = 0xff,
+                        .step           = 0x1,
+                        .default_value  = PO1030_GREEN_GAIN_DEFAULT,
+                        .flags          = V4L2_CTRL_FLAG_SLIDER
+                },
+                .set = po1030_set_green_balance,
+                .get = po1030_get_green_balance
+        },
 };
 
 static void po1030_dump_registers(struct sd *sd);
 
 int po1030_probe(struct sd *sd)
 {
-        u8 prod_id = 0, ver_id = 0, i;
+        u8 dev_id_h = 0, i;
+        s32 *sensor_settings;
 
         if (force_sensor) {
                 if (force_sensor == PO1030_SENSOR) {
@@ -139,28 +217,36 @@ int po1030_probe(struct sd *sd)
                         m5602_write_bridge(sd, preinit_po1030[i][1], data);
         }
 
-        if (m5602_read_sensor(sd, 0x3, &prod_id, 1))
+        if (m5602_read_sensor(sd, PO1030_DEVID_H, &dev_id_h, 1))
                 return -ENODEV;
 
-        if (m5602_read_sensor(sd, 0x4, &ver_id, 1))
-                return -ENODEV;
-
-        if ((prod_id == 0x02) && (ver_id == 0xef)) {
+        if (dev_id_h == 0x30) {
                 info("Detected a po1030 sensor");
                 goto sensor_found;
         }
         return -ENODEV;
 
 sensor_found:
+        sensor_settings = kmalloc(
+                ARRAY_SIZE(po1030_ctrls) * sizeof(s32), GFP_KERNEL);
+        if (!sensor_settings)
+                return -ENOMEM;
+
         sd->gspca_dev.cam.cam_mode = po1030_modes;
         sd->gspca_dev.cam.nmodes = ARRAY_SIZE(po1030_modes);
         sd->desc->ctrls = po1030_ctrls;
         sd->desc->nctrls = ARRAY_SIZE(po1030_ctrls);
+
+        for (i = 0; i < ARRAY_SIZE(po1030_ctrls); i++)
+                sensor_settings[i] = po1030_ctrls[i].qctrl.default_value;
+        sd->sensor_priv = sensor_settings;
+
         return 0;
 }
 
 int po1030_init(struct sd *sd)
 {
+        s32 *sensor_settings = sd->sensor_priv;
         int i, err = 0;
 
         /* Init the sensor */
@@ -185,47 +271,206 @@ int po1030_init(struct sd *sd)
                         return -EINVAL;
                 }
         }
+        if (err < 0)
+                return err;
 
         if (dump_sensor)
                 po1030_dump_registers(sd);
 
+        err = po1030_set_exposure(&sd->gspca_dev,
+                                   sensor_settings[EXPOSURE_IDX]);
+        if (err < 0)
+                return err;
+
+        err = po1030_set_gain(&sd->gspca_dev, sensor_settings[GAIN_IDX]);
+        if (err < 0)
+                return err;
+
+        err = po1030_set_hflip(&sd->gspca_dev, sensor_settings[HFLIP_IDX]);
+        if (err < 0)
+                return err;
+
+        err = po1030_set_vflip(&sd->gspca_dev, sensor_settings[VFLIP_IDX]);
+        if (err < 0)
+                return err;
+
+        err = po1030_set_red_balance(&sd->gspca_dev,
+                                      sensor_settings[RED_BALANCE_IDX]);
+        if (err < 0)
+                return err;
+
+        err = po1030_set_blue_balance(&sd->gspca_dev,
+                                      sensor_settings[BLUE_BALANCE_IDX]);
+        if (err < 0)
+                return err;
+
+        err = po1030_set_green_balance(&sd->gspca_dev,
+                                       sensor_settings[GREEN_BALANCE_IDX]);
+        if (err < 0)
+                return err;
+
+        err = po1030_set_auto_white_balance(&sd->gspca_dev,
+                                sensor_settings[AUTO_WHITE_BALANCE_IDX]);
+        if (err < 0)
+                return err;
+
+        err = po1030_set_auto_exposure(&sd->gspca_dev,
+                                sensor_settings[AUTO_EXPOSURE_IDX]);
         return err;
 }
 
-int po1030_get_exposure(struct gspca_dev *gspca_dev, __s32 *val)
+int po1030_start(struct sd *sd)
 {
-        struct sd *sd = (struct sd *) gspca_dev;
-        u8 i2c_data;
-        int err;
+        struct cam *cam = &sd->gspca_dev.cam;
+        int i, err = 0;
+        int width = cam->cam_mode[sd->gspca_dev.curr_mode].width;
+        int height = cam->cam_mode[sd->gspca_dev.curr_mode].height;
+        int ver_offs = cam->cam_mode[sd->gspca_dev.curr_mode].priv;
+        u8 data;
+
+        switch (width) {
+        case 320:
+                data = PO1030_SUBSAMPLING;
+                err = m5602_write_sensor(sd, PO1030_CONTROL3, &data, 1);
+                if (err < 0)
+                        return err;
+
+                data = ((width + 3) >> 8) & 0xff;
+                err = m5602_write_sensor(sd, PO1030_WINDOWWIDTH_H, &data, 1);
+                if (err < 0)
+                        return err;
+
+                data = (width + 3) & 0xff;
+                err = m5602_write_sensor(sd, PO1030_WINDOWWIDTH_L, &data, 1);
+                if (err < 0)
+                        return err;
+
+                data = ((height + 1) >> 8) & 0xff;
+                err = m5602_write_sensor(sd, PO1030_WINDOWHEIGHT_H, &data, 1);
+                if (err < 0)
+                        return err;
+
+                data = (height + 1) & 0xff;
+                err = m5602_write_sensor(sd, PO1030_WINDOWHEIGHT_L, &data, 1);
+
+                height += 6;
+                width -= 1;
+                break;
+
+        case 640:
+                data = 0;
+                err = m5602_write_sensor(sd, PO1030_CONTROL3, &data, 1);
+                if (err < 0)
+                        return err;
+
+                data = ((width + 7) >> 8) & 0xff;
+                err = m5602_write_sensor(sd, PO1030_WINDOWWIDTH_H, &data, 1);
+                if (err < 0)
+                        return err;
+
+                data = (width + 7) & 0xff;
+                err = m5602_write_sensor(sd, PO1030_WINDOWWIDTH_L, &data, 1);
+                if (err < 0)
+                        return err;
+
+                data = ((height + 3) >> 8) & 0xff;
+                err = m5602_write_sensor(sd, PO1030_WINDOWHEIGHT_H, &data, 1);
+                if (err < 0)
+                        return err;
+
+                data = (height + 3) & 0xff;
+                err = m5602_write_sensor(sd, PO1030_WINDOWHEIGHT_L, &data, 1);
+
+                height += 12;
+                width -= 2;
+                break;
+        }
+        err = m5602_write_bridge(sd, M5602_XB_SENSOR_TYPE, 0x0c);
+        if (err < 0)
+                return err;
 
-        err = m5602_read_sensor(sd, PO1030_REG_INTEGLINES_H,
-                                 &i2c_data, 1);
+        err = m5602_write_bridge(sd, M5602_XB_LINE_OF_FRAME_H, 0x81);
         if (err < 0)
                 return err;
-        *val = (i2c_data << 8);
 
-        err = m5602_read_sensor(sd, PO1030_REG_INTEGLINES_M,
-                                 &i2c_data, 1);
-        *val |= i2c_data;
+        err = m5602_write_bridge(sd, M5602_XB_PIX_OF_LINE_H, 0x82);
+        if (err < 0)
+                return err;
 
-        PDEBUG(D_V4L2, "Exposure read as %d", *val);
+        err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 0x01);
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA,
+                                 ((ver_offs >> 8) & 0xff));
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, (ver_offs & 0xff));
+        if (err < 0)
+                return err;
+
+        for (i = 0; i < 2 && !err; i++)
+                err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, 0);
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, (height >> 8) & 0xff);
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, (height & 0xff));
+        if (err < 0)
+                return err;
+
+        for (i = 0; i < 2 && !err; i++)
+                err = m5602_write_bridge(sd, M5602_XB_VSYNC_PARA, 0);
+
+        for (i = 0; i < 2 && !err; i++)
+                err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 0);
+
+        for (i = 0; i < 2 && !err; i++)
+                err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA, 0);
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA, (width >> 8) & 0xff);
+        if (err < 0)
+                return err;
 
+        err = m5602_write_bridge(sd, M5602_XB_HSYNC_PARA, (width & 0xff));
+        if (err < 0)
+                return err;
+
+        err = m5602_write_bridge(sd, M5602_XB_SIG_INI, 0);
         return err;
 }
 
-int po1030_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
+static int po1030_get_exposure(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[EXPOSURE_IDX];
+        PDEBUG(D_V4L2, "Exposure read as %d", *val);
+        return 0;
+}
+
+static int po1030_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 i2c_data;
         int err;
 
+        sensor_settings[EXPOSURE_IDX] = val;
         PDEBUG(D_V4L2, "Set exposure to %d", val & 0xffff);
 
         i2c_data = ((val & 0xff00) >> 8);
         PDEBUG(D_V4L2, "Set exposure to high byte to 0x%x",
                i2c_data);
 
-        err = m5602_write_sensor(sd, PO1030_REG_INTEGLINES_H,
+        err = m5602_write_sensor(sd, PO1030_INTEGLINES_H,
                                   &i2c_data, 1);
         if (err < 0)
                 return err;
@@ -233,167 +478,256 @@ int po1030_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
         i2c_data = (val & 0xff);
         PDEBUG(D_V4L2, "Set exposure to low byte to 0x%x",
                i2c_data);
-        err = m5602_write_sensor(sd, PO1030_REG_INTEGLINES_M,
+        err = m5602_write_sensor(sd, PO1030_INTEGLINES_M,
                                   &i2c_data, 1);
 
         return err;
 }
 
-int po1030_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
+static int po1030_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
-        u8 i2c_data;
-        int err;
+        s32 *sensor_settings = sd->sensor_priv;
 
-        err = m5602_read_sensor(sd, PO1030_REG_GLOBALGAIN,
-                                 &i2c_data, 1);
-        *val = i2c_data;
+        *val = sensor_settings[GAIN_IDX];
         PDEBUG(D_V4L2, "Read global gain %d", *val);
-
-        return err;
+        return 0;
 }
 
-int po1030_get_hflip(struct gspca_dev *gspca_dev, __s32 *val)
+static int po1030_set_gain(struct gspca_dev *gspca_dev, __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 i2c_data;
         int err;
 
-        err = m5602_read_sensor(sd, PO1030_REG_CONTROL2,
+        sensor_settings[GAIN_IDX] = val;
+
+        i2c_data = val & 0xff;
+        PDEBUG(D_V4L2, "Set global gain to %d", i2c_data);
+        err = m5602_write_sensor(sd, PO1030_GLOBALGAIN,
                                  &i2c_data, 1);
+        return err;
+}
 
-        *val = (i2c_data >> 7) & 0x01 ;
+static int po1030_get_hflip(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
 
+        *val = sensor_settings[HFLIP_IDX];
         PDEBUG(D_V4L2, "Read hflip %d", *val);
 
-        return err;
+        return 0;
 }
 
-int po1030_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
+static int po1030_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 i2c_data;
         int err;
 
+        sensor_settings[HFLIP_IDX] = val;
+
         PDEBUG(D_V4L2, "Set hflip %d", val);
-        err = m5602_read_sensor(sd, PO1030_REG_CONTROL2, &i2c_data, 1);
+        err = m5602_read_sensor(sd, PO1030_CONTROL2, &i2c_data, 1);
         if (err < 0)
                 return err;
 
         i2c_data = (0x7f & i2c_data) | ((val & 0x01) << 7);
 
-        err = m5602_write_sensor(sd, PO1030_REG_CONTROL2,
+        err = m5602_write_sensor(sd, PO1030_CONTROL2,
                                  &i2c_data, 1);
 
         return err;
 }
 
-int po1030_get_vflip(struct gspca_dev *gspca_dev, __s32 *val)
+static int po1030_get_vflip(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
-        u8 i2c_data;
-        int err;
-
-        err = m5602_read_sensor(sd, PO1030_REG_GLOBALGAIN,
-                                 &i2c_data, 1);
-
-        *val = (i2c_data >> 6) & 0x01;
+        s32 *sensor_settings = sd->sensor_priv;
 
+        *val = sensor_settings[VFLIP_IDX];
         PDEBUG(D_V4L2, "Read vflip %d", *val);
 
-        return err;
+        return 0;
 }
 
-int po1030_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
+static int po1030_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 i2c_data;
         int err;
 
+        sensor_settings[VFLIP_IDX] = val;
+
         PDEBUG(D_V4L2, "Set vflip %d", val);
-        err = m5602_read_sensor(sd, PO1030_REG_CONTROL2, &i2c_data, 1);
+        err = m5602_read_sensor(sd, PO1030_CONTROL2, &i2c_data, 1);
         if (err < 0)
                 return err;
 
         i2c_data = (i2c_data & 0xbf) | ((val & 0x01) << 6);
 
-        err = m5602_write_sensor(sd, PO1030_REG_CONTROL2,
+        err = m5602_write_sensor(sd, PO1030_CONTROL2,
                                  &i2c_data, 1);
 
         return err;
 }
 
-int po1030_set_gain(struct gspca_dev *gspca_dev, __s32 val)
+static int po1030_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[RED_BALANCE_IDX];
+        PDEBUG(D_V4L2, "Read red gain %d", *val);
+        return 0;
+}
+
+static int po1030_set_red_balance(struct gspca_dev *gspca_dev, __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 i2c_data;
         int err;
 
+        sensor_settings[RED_BALANCE_IDX] = val;
+
         i2c_data = val & 0xff;
-        PDEBUG(D_V4L2, "Set global gain to %d", i2c_data);
-        err = m5602_write_sensor(sd, PO1030_REG_GLOBALGAIN,
+        PDEBUG(D_V4L2, "Set red gain to %d", i2c_data);
+        err = m5602_write_sensor(sd, PO1030_RED_GAIN,
                                   &i2c_data, 1);
         return err;
 }
 
-int po1030_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val)
+static int po1030_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
-        u8 i2c_data;
-        int err;
+        s32 *sensor_settings = sd->sensor_priv;
 
-        err = m5602_read_sensor(sd, PO1030_REG_RED_GAIN,
-                                 &i2c_data, 1);
-        *val = i2c_data;
-        PDEBUG(D_V4L2, "Read red gain %d", *val);
-        return err;
+        *val = sensor_settings[BLUE_BALANCE_IDX];
+        PDEBUG(D_V4L2, "Read blue gain %d", *val);
+
+        return 0;
 }
 
-int po1030_set_red_balance(struct gspca_dev *gspca_dev, __s32 val)
+static int po1030_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 i2c_data;
         int err;
 
+        sensor_settings[BLUE_BALANCE_IDX] = val;
+
         i2c_data = val & 0xff;
-        PDEBUG(D_V4L2, "Set red gain to %d", i2c_data);
-        err = m5602_write_sensor(sd, PO1030_REG_RED_GAIN,
+        PDEBUG(D_V4L2, "Set blue gain to %d", i2c_data);
+        err = m5602_write_sensor(sd, PO1030_BLUE_GAIN,
                                   &i2c_data, 1);
+
         return err;
 }
 
-int po1030_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val)
+static int po1030_get_green_balance(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[GREEN_BALANCE_IDX];
+        PDEBUG(D_V4L2, "Read green gain %d", *val);
+
+        return 0;
+}
+
+static int po1030_set_green_balance(struct gspca_dev *gspca_dev, __s32 val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 i2c_data;
         int err;
 
-        err = m5602_read_sensor(sd, PO1030_REG_BLUE_GAIN,
+        sensor_settings[GREEN_BALANCE_IDX] = val;
+        i2c_data = val & 0xff;
+        PDEBUG(D_V4L2, "Set green gain to %d", i2c_data);
+
+        err = m5602_write_sensor(sd, PO1030_GREEN_1_GAIN,
+                           &i2c_data, 1);
+        if (err < 0)
+                return err;
+
+        return m5602_write_sensor(sd, PO1030_GREEN_2_GAIN,
                                  &i2c_data, 1);
-        *val = i2c_data;
-        PDEBUG(D_V4L2, "Read blue gain %d", *val);
+}
 
-        return err;
+static int po1030_get_auto_white_balance(struct gspca_dev *gspca_dev,
+                                         __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[AUTO_WHITE_BALANCE_IDX];
+        PDEBUG(D_V4L2, "Auto white balancing is %d", *val);
+
+        return 0;
 }
 
-int po1030_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val)
+static int po1030_set_auto_white_balance(struct gspca_dev *gspca_dev,
+                                         __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 i2c_data;
         int err;
-        i2c_data = val & 0xff;
-        PDEBUG(D_V4L2, "Set blue gain to %d", i2c_data);
-        err = m5602_write_sensor(sd, PO1030_REG_BLUE_GAIN,
-                                  &i2c_data, 1);
 
+        sensor_settings[AUTO_WHITE_BALANCE_IDX] = val;
+
+        err = m5602_read_sensor(sd, PO1030_AUTOCTRL1, &i2c_data, 1);
+        if (err < 0)
+                return err;
+
+        PDEBUG(D_V4L2, "Set auto white balance to %d", val);
+        i2c_data = (i2c_data & 0xfe) | (val & 0x01);
+        err = m5602_write_sensor(sd, PO1030_AUTOCTRL1, &i2c_data, 1);
         return err;
 }
 
-int po1030_power_down(struct sd *sd)
+static int po1030_get_auto_exposure(struct gspca_dev *gspca_dev,
+                                    __s32 *val)
 {
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[AUTO_EXPOSURE_IDX];
+        PDEBUG(D_V4L2, "Auto exposure is %d", *val);
         return 0;
 }
 
+static int po1030_set_auto_exposure(struct gspca_dev *gspca_dev,
+                                    __s32 val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+        u8 i2c_data;
+        int err;
+
+        sensor_settings[AUTO_EXPOSURE_IDX] = val;
+        err = m5602_read_sensor(sd, PO1030_AUTOCTRL1, &i2c_data, 1);
+        if (err < 0)
+                return err;
+
+        PDEBUG(D_V4L2, "Set auto exposure to %d", val);
+        i2c_data = (i2c_data & 0xfd) | ((val & 0x01) << 1);
+        return m5602_write_sensor(sd, PO1030_AUTOCTRL1, &i2c_data, 1);
+}
+
+void po1030_disconnect(struct sd *sd)
+{
+        sd->sensor = NULL;
+        kfree(sd->sensor_priv);
+}
+
 static void po1030_dump_registers(struct sd *sd)
 {
         int address;
diff --git a/drivers/media/video/gspca/m5602/m5602_po1030.h b/drivers/media/video/gspca/m5602/m5602_po1030.h
index c10b12335818..1ea380b2bbe7 100644
--- a/drivers/media/video/gspca/m5602/m5602_po1030.h
+++ b/drivers/media/video/gspca/m5602/m5602_po1030.h
@@ -25,98 +25,123 @@
 
 /*****************************************************************************/
 
-#define PO1030_REG_DEVID_H              0x00
-#define PO1030_REG_DEVID_L              0x01
-#define PO1030_REG_FRAMEWIDTH_H         0x04
-#define PO1030_REG_FRAMEWIDTH_L         0x05
-#define PO1030_REG_FRAMEHEIGHT_H        0x06
-#define PO1030_REG_FRAMEHEIGHT_L        0x07
-#define PO1030_REG_WINDOWX_H            0x08
-#define PO1030_REG_WINDOWX_L            0x09
-#define PO1030_REG_WINDOWY_H            0x0a
-#define PO1030_REG_WINDOWY_L            0x0b
-#define PO1030_REG_WINDOWWIDTH_H        0x0c
-#define PO1030_REG_WINDOWWIDTH_L        0x0d
-#define PO1030_REG_WINDOWHEIGHT_H       0x0e
-#define PO1030_REG_WINDOWHEIGHT_L       0x0f
-
-#define PO1030_REG_GLOBALIBIAS          0x12
-#define PO1030_REG_PIXELIBIAS           0x13
-
-#define PO1030_REG_GLOBALGAIN           0x15
-#define PO1030_REG_RED_GAIN             0x16
-#define PO1030_REG_GREEN_1_GAIN         0x17
-#define PO1030_REG_BLUE_GAIN            0x18
-#define PO1030_REG_GREEN_2_GAIN         0x19
-
-#define PO1030_REG_INTEGLINES_H         0x1a
-#define PO1030_REG_INTEGLINES_M         0x1b
-#define PO1030_REG_INTEGLINES_L         0x1c
-
-#define PO1030_REG_CONTROL1             0x1d
-#define PO1030_REG_CONTROL2             0x1e
-#define PO1030_REG_CONTROL3             0x1f
-#define PO1030_REG_CONTROL4             0x20
-
-#define PO1030_REG_PERIOD50_H           0x23
-#define PO1030_REG_PERIOD50_L           0x24
-#define PO1030_REG_PERIOD60_H           0x25
-#define PO1030_REG_PERIOD60_L           0x26
-#define PO1030_REG_REGCLK167            0x27
-#define PO1030_REG_DELTA50              0x28
-#define PO1030_REG_DELTA60              0x29
-
-#define PO1030_REG_ADCOFFSET            0x2c
+#define PO1030_DEVID_H          0x00
+#define PO1030_DEVID_L          0x01
+#define PO1030_FRAMEWIDTH_H     0x04
+#define PO1030_FRAMEWIDTH_L     0x05
+#define PO1030_FRAMEHEIGHT_H    0x06
+#define PO1030_FRAMEHEIGHT_L    0x07
+#define PO1030_WINDOWX_H        0x08
+#define PO1030_WINDOWX_L        0x09
+#define PO1030_WINDOWY_H        0x0a
+#define PO1030_WINDOWY_L        0x0b
+#define PO1030_WINDOWWIDTH_H    0x0c
+#define PO1030_WINDOWWIDTH_L    0x0d
+#define PO1030_WINDOWHEIGHT_H   0x0e
+#define PO1030_WINDOWHEIGHT_L   0x0f
+
+#define PO1030_GLOBALIBIAS      0x12
+#define PO1030_PIXELIBIAS       0x13
+
+#define PO1030_GLOBALGAIN       0x15
+#define PO1030_RED_GAIN         0x16
+#define PO1030_GREEN_1_GAIN     0x17
+#define PO1030_BLUE_GAIN        0x18
+#define PO1030_GREEN_2_GAIN     0x19
+
+#define PO1030_INTEGLINES_H     0x1a
+#define PO1030_INTEGLINES_M     0x1b
+#define PO1030_INTEGLINES_L     0x1c
+
+#define PO1030_CONTROL1         0x1d
+#define PO1030_CONTROL2         0x1e
+#define PO1030_CONTROL3         0x1f
+#define PO1030_CONTROL4         0x20
+
+#define PO1030_PERIOD50_H       0x23
+#define PO1030_PERIOD50_L       0x24
+#define PO1030_PERIOD60_H       0x25
+#define PO1030_PERIOD60_L       0x26
+#define PO1030_REGCLK167        0x27
+#define PO1030_FLICKER_DELTA50  0x28
+#define PO1030_FLICKERDELTA60   0x29
+
+#define PO1030_ADCOFFSET        0x2c
 
 /* Gamma Correction Coeffs */
-#define PO1030_REG_GC0                  0x2d
-#define PO1030_REG_GC1                  0x2e
-#define PO1030_REG_GC2                  0x2f
-#define PO1030_REG_GC3                  0x30
-#define PO1030_REG_GC4                  0x31
-#define PO1030_REG_GC5                  0x32
-#define PO1030_REG_GC6                  0x33
-#define PO1030_REG_GC7                  0x34
+#define PO1030_GC0              0x2d
+#define PO1030_GC1              0x2e
+#define PO1030_GC2              0x2f
+#define PO1030_GC3              0x30
+#define PO1030_GC4              0x31
+#define PO1030_GC5              0x32
+#define PO1030_GC6              0x33
+#define PO1030_GC7              0x34
 
 /* Color Transform Matrix */
-#define PO1030_REG_CT0                  0x35
-#define PO1030_REG_CT1                  0x36
-#define PO1030_REG_CT2                  0x37
-#define PO1030_REG_CT3                  0x38
-#define PO1030_REG_CT4                  0x39
-#define PO1030_REG_CT5                  0x3a
-#define PO1030_REG_CT6                  0x3b
-#define PO1030_REG_CT7                  0x3c
-#define PO1030_REG_CT8                  0x3d
-
-#define PO1030_REG_AUTOCTRL1            0x3e
-#define PO1030_REG_AUTOCTRL2            0x3f
-
-#define PO1030_REG_YTARGET              0x40
-#define PO1030_REG_GLOBALGAINMIN        0x41
-#define PO1030_REG_GLOBALGAINMAX        0x42
+#define PO1030_CT0              0x35
+#define PO1030_CT1              0x36
+#define PO1030_CT2              0x37
+#define PO1030_CT3              0x38
+#define PO1030_CT4              0x39
+#define PO1030_CT5              0x3a
+#define PO1030_CT6              0x3b
+#define PO1030_CT7              0x3c
+#define PO1030_CT8              0x3d
+
+#define PO1030_AUTOCTRL1        0x3e
+#define PO1030_AUTOCTRL2        0x3f
+
+#define PO1030_YTARGET          0x40
+#define PO1030_GLOBALGAINMIN    0x41
+#define PO1030_GLOBALGAINMAX    0x42
+
+#define PO1030_AWB_RED_TUNING   0x47
+#define PO1030_AWB_BLUE_TUNING  0x48
 
 /* Output format control */
-#define PO1030_REG_OUTFORMCTRL1         0x5a
-#define PO1030_REG_OUTFORMCTRL2         0x5b
-#define PO1030_REG_OUTFORMCTRL3         0x5c
-#define PO1030_REG_OUTFORMCTRL4         0x5d
-#define PO1030_REG_OUTFORMCTRL5         0x5e
+#define PO1030_OUTFORMCTRL1     0x5a
+#define PO1030_OUTFORMCTRL2     0x5b
+#define PO1030_OUTFORMCTRL3     0x5c
+#define PO1030_OUTFORMCTRL4     0x5d
+#define PO1030_OUTFORMCTRL5     0x5e
 
-/* Imaging coefficients */
-#define PO1030_REG_YBRIGHT              0x73
-#define PO1030_REG_YCONTRAST            0x74
-#define PO1030_REG_YSATURATION          0x75
+#define PO1030_EDGE_ENH_OFF     0x5f
+#define PO1030_EGA              0x60
 
-#define PO1030_HFLIP                    (1 << 7)
-#define PO1030_VFLIP                    (1 << 6)
+#define PO1030_Cb_U_GAIN        0x63
+#define PO1030_Cr_V_GAIN        0x64
+
+#define PO1030_YCONTRAST        0x74
+#define PO1030_YSATURATION      0x75
+
+#define PO1030_HFLIP            (1 << 7)
+#define PO1030_VFLIP            (1 << 6)
+
+#define PO1030_HREF_ENABLE      (1 << 6)
+
+#define PO1030_RAW_RGB_BAYER    0x4
+
+#define PO1030_FRAME_EQUAL      (1 << 3)
+#define PO1030_AUTO_SUBSAMPLING (1 << 4)
+
+#define PO1030_WEIGHT_WIN_2X    (1 << 3)
+
+#define PO1030_SHUTTER_MODE     (1 << 6)
+#define PO1030_AUTO_SUBSAMPLING (1 << 4)
+#define PO1030_FRAME_EQUAL      (1 << 3)
+
+#define PO1030_SENSOR_RESET     (1 << 5)
+
+#define PO1030_SUBSAMPLING      (1 << 6)
 
 /*****************************************************************************/
 
 #define PO1030_GLOBAL_GAIN_DEFAULT      0x12
 #define PO1030_EXPOSURE_DEFAULT         0x0085
-#define PO1030_BLUE_GAIN_DEFAULT        0x40
-#define PO1030_RED_GAIN_DEFAULT         0x40
+#define PO1030_BLUE_GAIN_DEFAULT        0x36
+#define PO1030_RED_GAIN_DEFAULT         0x36
+#define PO1030_GREEN_GAIN_DEFAULT       0x40
 
 /*****************************************************************************/
 
@@ -126,20 +151,8 @@ extern int dump_sensor;
 
 int po1030_probe(struct sd *sd);
 int po1030_init(struct sd *sd);
-int po1030_power_down(struct sd *sd);
-
-int po1030_get_exposure(struct gspca_dev *gspca_dev, __s32 *val);
-int po1030_set_exposure(struct gspca_dev *gspca_dev, __s32 val);
-int po1030_get_gain(struct gspca_dev *gspca_dev, __s32 *val);
-int po1030_set_gain(struct gspca_dev *gspca_dev, __s32 val);
-int po1030_get_red_balance(struct gspca_dev *gspca_dev, __s32 *val);
-int po1030_set_red_balance(struct gspca_dev *gspca_dev, __s32 val);
-int po1030_get_blue_balance(struct gspca_dev *gspca_dev, __s32 *val);
-int po1030_set_blue_balance(struct gspca_dev *gspca_dev, __s32 val);
-int po1030_get_hflip(struct gspca_dev *gspca_dev, __s32 *val);
-int po1030_set_hflip(struct gspca_dev *gspca_dev, __s32 val);
-int po1030_get_vflip(struct gspca_dev *gspca_dev, __s32 *val);
-int po1030_set_vflip(struct gspca_dev *gspca_dev, __s32 val);
+int po1030_start(struct sd *sd);
+void po1030_disconnect(struct sd *sd);
 
 static const struct m5602_sensor po1030 = {
         .name = "PO1030",
@@ -149,7 +162,8 @@ static const struct m5602_sensor po1030 = {
 
         .probe = po1030_probe,
         .init = po1030_init,
-        .power_down = po1030_power_down,
+        .start = po1030_start,
+        .disconnect = po1030_disconnect,
 };
 
 static const unsigned char preinit_po1030[][3] =
@@ -159,248 +173,103 @@ static const unsigned char preinit_po1030[][3] =
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
         {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0d},
         {BRIDGE, M5602_XB_SENSOR_CTRL, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
         {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
-
-        {SENSOR, PO1030_REG_AUTOCTRL2, 0x24},
-
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
-        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06},
-        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x02},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x04},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
         {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
-        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81},
-        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82},
-        {BRIDGE, M5602_XB_SIG_INI, 0x01},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x02},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x01},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0xec},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x02},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x02},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x87},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00},
-
-        {SENSOR, PO1030_REG_AUTOCTRL2, 0x24},
-
         {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
         {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
         {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
         {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06},
         {BRIDGE, M5602_XB_GPIO_DAT_H, 0x02},
+
+        {SENSOR, PO1030_AUTOCTRL2, PO1030_SENSOR_RESET | (1 << 2)},
+
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x04},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
         {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
         {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
         {BRIDGE, M5602_XB_GPIO_DAT, 0x00}
 };
 
-static const unsigned char init_po1030[][4] =
+static const unsigned char init_po1030[][3] =
 {
         {BRIDGE, M5602_XB_MCU_CLK_DIV, 0x02},
         {BRIDGE, M5602_XB_MCU_CLK_CTRL, 0xb0},
-        /*sequence 1*/
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
         {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0d},
-
         {BRIDGE, M5602_XB_SENSOR_CTRL, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
         {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
-        /*end of sequence 1*/
-
-        /*sequence 2 (same as stop sequence)*/
-        {SENSOR, PO1030_REG_AUTOCTRL2, 0x24},
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
-        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06},
-        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x02},
-
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x04},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
-        /*end of sequence 2*/
 
-        /*sequence 5*/
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
-        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81},
-        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82},
-        {BRIDGE, M5602_XB_SIG_INI, 0x01},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x02},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x01},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0xec},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x02},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x02},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x87},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00},
-        /*end of sequence 5*/
-
-        /*sequence 2 stop */
-        {SENSOR, PO1030_REG_AUTOCTRL2, 0x24},
+        {SENSOR, PO1030_AUTOCTRL2, PO1030_SENSOR_RESET | (1 << 2)},
 
         {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
         {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
         {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_EN_L, 0x00},
         {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06},
         {BRIDGE, M5602_XB_GPIO_DAT_H, 0x02},
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x04},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
-        /*end of sequence 2 stop */
-
-/* ---------------------------------
- * end of init - begin of start
- * --------------------------------- */
-
-        /*sequence 3*/
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
-        /*end of sequence 3*/
-        /*sequence 4*/
         {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
         {BRIDGE, M5602_XB_GPIO_DAT, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0x00},
 
-        {SENSOR, PO1030_REG_AUTOCTRL2, 0x04},
+        {SENSOR, PO1030_AUTOCTRL2, 0x04},
+
+        {SENSOR, PO1030_OUTFORMCTRL2, PO1030_RAW_RGB_BAYER},
+        {SENSOR, PO1030_AUTOCTRL1, PO1030_WEIGHT_WIN_2X},
+
+        {SENSOR, PO1030_CONTROL2, 0x03},
+        {SENSOR, 0x21, 0x90},
+        {SENSOR, PO1030_YTARGET, 0x60},
+        {SENSOR, 0x59, 0x13},
+        {SENSOR, PO1030_OUTFORMCTRL1, PO1030_HREF_ENABLE},
+        {SENSOR, PO1030_EDGE_ENH_OFF, 0x00},
+        {SENSOR, PO1030_EGA, 0x80},
+        {SENSOR, 0x78, 0x14},
+        {SENSOR, 0x6f, 0x01},
+        {SENSOR, PO1030_GLOBALGAINMAX, 0x14},
+        {SENSOR, PO1030_Cb_U_GAIN, 0x38},
+        {SENSOR, PO1030_Cr_V_GAIN, 0x38},
+        {SENSOR, PO1030_CONTROL1, PO1030_SHUTTER_MODE |
+                                  PO1030_AUTO_SUBSAMPLING |
+                                  PO1030_FRAME_EQUAL},
+        {SENSOR, PO1030_GC0, 0x10},
+        {SENSOR, PO1030_GC1, 0x20},
+        {SENSOR, PO1030_GC2, 0x40},
+        {SENSOR, PO1030_GC3, 0x60},
+        {SENSOR, PO1030_GC4, 0x80},
+        {SENSOR, PO1030_GC5, 0xa0},
+        {SENSOR, PO1030_GC6, 0xc0},
+        {SENSOR, PO1030_GC7, 0xff},
 
         /* Set the width to 751 */
-        {SENSOR, PO1030_REG_FRAMEWIDTH_H, 0x02},
-        {SENSOR, PO1030_REG_FRAMEWIDTH_L, 0xef},
+        {SENSOR, PO1030_FRAMEWIDTH_H, 0x02},
+        {SENSOR, PO1030_FRAMEWIDTH_L, 0xef},
 
         /* Set the height to 540 */
-        {SENSOR, PO1030_REG_FRAMEHEIGHT_H, 0x02},
-        {SENSOR, PO1030_REG_FRAMEHEIGHT_L, 0x1c},
+        {SENSOR, PO1030_FRAMEHEIGHT_H, 0x02},
+        {SENSOR, PO1030_FRAMEHEIGHT_L, 0x1c},
 
         /* Set the x window to 1 */
-        {SENSOR, PO1030_REG_WINDOWX_H, 0x00},
-        {SENSOR, PO1030_REG_WINDOWX_L, 0x01},
+        {SENSOR, PO1030_WINDOWX_H, 0x00},
+        {SENSOR, PO1030_WINDOWX_L, 0x01},
 
         /* Set the y window to 1 */
-        {SENSOR, PO1030_REG_WINDOWY_H, 0x00},
-        {SENSOR, PO1030_REG_WINDOWY_L, 0x01},
-
-        {SENSOR, PO1030_REG_WINDOWWIDTH_H, 0x02},
-        {SENSOR, PO1030_REG_WINDOWWIDTH_L, 0x87},
-        {SENSOR, PO1030_REG_WINDOWHEIGHT_H, 0x01},
-        {SENSOR, PO1030_REG_WINDOWHEIGHT_L, 0xe3},
-
-        {SENSOR, PO1030_REG_OUTFORMCTRL2, 0x04},
-        {SENSOR, PO1030_REG_OUTFORMCTRL2, 0x04},
-        {SENSOR, PO1030_REG_AUTOCTRL1, 0x08},
-        {SENSOR, PO1030_REG_CONTROL2, 0x03},
-        {SENSOR, 0x21, 0x90},
-        {SENSOR, PO1030_REG_YTARGET, 0x60},
-        {SENSOR, 0x59, 0x13},
-        {SENSOR, PO1030_REG_OUTFORMCTRL1, 0x40},
-        {SENSOR, 0x5f, 0x00},
-        {SENSOR, 0x60, 0x80},
-        {SENSOR, 0x78, 0x14},
-        {SENSOR, 0x6f, 0x01},
-        {SENSOR, PO1030_REG_CONTROL1, 0x18},
-        {SENSOR, PO1030_REG_GLOBALGAINMAX, 0x14},
-        {SENSOR, 0x63, 0x38},
-        {SENSOR, 0x64, 0x38},
-        {SENSOR, PO1030_REG_CONTROL1, 0x58},
-        {SENSOR, PO1030_REG_RED_GAIN, 0x30},
-        {SENSOR, PO1030_REG_GREEN_1_GAIN, 0x30},
-        {SENSOR, PO1030_REG_BLUE_GAIN, 0x30},
-        {SENSOR, PO1030_REG_GREEN_2_GAIN, 0x30},
-        {SENSOR, PO1030_REG_GC0, 0x10},
-        {SENSOR, PO1030_REG_GC1, 0x20},
-        {SENSOR, PO1030_REG_GC2, 0x40},
-        {SENSOR, PO1030_REG_GC3, 0x60},
-        {SENSOR, PO1030_REG_GC4, 0x80},
-        {SENSOR, PO1030_REG_GC5, 0xa0},
-        {SENSOR, PO1030_REG_GC6, 0xc0},
-        {SENSOR, PO1030_REG_GC7, 0xff},
-        /*end of sequence 4*/
-        /*sequence 5*/
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x0c},
-        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81},
-        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82},
-        {BRIDGE, M5602_XB_SIG_INI, 0x01},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x02},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x01},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0xec},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x02},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x7e},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00},
-        /*end of sequence 5*/
-
-        /*sequence 6*/
-        /* Changing 40 in f0 the image becomes green in bayer mode and red in
-         * rgb mode */
-        {SENSOR, PO1030_REG_RED_GAIN, PO1030_RED_GAIN_DEFAULT},
-        /* in changing 40 in f0 the image becomes green in bayer mode and red in
-         * rgb mode */
-        {SENSOR, PO1030_REG_BLUE_GAIN, PO1030_BLUE_GAIN_DEFAULT},
+        {SENSOR, PO1030_WINDOWY_H, 0x00},
+        {SENSOR, PO1030_WINDOWY_L, 0x01},
 
         /* with a very low lighted environment increase the exposure but
          * decrease the FPS (Frame Per Second) */
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
 
-        /* Controls high exposure more than SENSOR_LOW_EXPOSURE, use only in
-         * low lighted environment (f0 is more than ff ?)*/
-        {SENSOR, PO1030_REG_INTEGLINES_H, ((PO1030_EXPOSURE_DEFAULT >> 2)
-                & 0xff)},
-
-        /* Controls middle exposure, use only in high lighted environment */
-        {SENSOR, PO1030_REG_INTEGLINES_M, PO1030_EXPOSURE_DEFAULT & 0xff},
-
-        /* Controls clarity (not sure) */
-        {SENSOR, PO1030_REG_INTEGLINES_L, 0x00},
-        /* Controls gain (the image is more lighted) */
-        {SENSOR, PO1030_REG_GLOBALGAIN, PO1030_GLOBAL_GAIN_DEFAULT},
-
-        /* Sets the width */
-        {SENSOR, PO1030_REG_FRAMEWIDTH_H, 0x02},
-        {SENSOR, PO1030_REG_FRAMEWIDTH_L, 0xef}
-        /*end of sequence 6*/
+        {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
+        {BRIDGE, M5602_XB_GPIO_DAT, 0x00},
+        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06},
+        {BRIDGE, M5602_XB_GPIO_EN_L, 0x00},
 };
 
 #endif
diff --git a/drivers/media/video/gspca/m5602/m5602_s5k4aa.c b/drivers/media/video/gspca/m5602/m5602_s5k4aa.c
index 4306d596056d..191bcd718979 100644
--- a/drivers/media/video/gspca/m5602/m5602_s5k4aa.c
+++ b/drivers/media/video/gspca/m5602/m5602_s5k4aa.c
@@ -18,6 +18,19 @@
 
 #include "m5602_s5k4aa.h"
 
+static int s5k4aa_get_exposure(struct gspca_dev *gspca_dev, __s32 *val);
+static int s5k4aa_set_exposure(struct gspca_dev *gspca_dev, __s32 val);
+static int s5k4aa_get_vflip(struct gspca_dev *gspca_dev, __s32 *val);
+static int s5k4aa_set_vflip(struct gspca_dev *gspca_dev, __s32 val);
+static int s5k4aa_get_hflip(struct gspca_dev *gspca_dev, __s32 *val);
+static int s5k4aa_set_hflip(struct gspca_dev *gspca_dev, __s32 val);
+static int s5k4aa_get_gain(struct gspca_dev *gspca_dev, __s32 *val);
+static int s5k4aa_set_gain(struct gspca_dev *gspca_dev, __s32 val);
+static int s5k4aa_get_noise(struct gspca_dev *gspca_dev, __s32 *val);
+static int s5k4aa_set_noise(struct gspca_dev *gspca_dev, __s32 val);
+static int s5k4aa_get_brightness(struct gspca_dev *gspca_dev, __s32 *val);
+static int s5k4aa_set_brightness(struct gspca_dev *gspca_dev, __s32 val);
+
 static
     const
         struct dmi_system_id s5k4aa_vflip_dmi_table[] = {
@@ -46,6 +59,18 @@ static
                         DMI_MATCH(DMI_SYS_VENDOR, "Micro-Star International"),
                         DMI_MATCH(DMI_PRODUCT_NAME, "GX700/GX705/EX700")
                 }
+        }, {
+                .ident = "MSI L735",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "Micro-Star International"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "MS-1717X")
+                }
+        }, {
+                .ident = "Lenovo Y300",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "L3000 Y300"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "Y300")
+                }
         },
         { }
 };
@@ -61,10 +86,22 @@ static struct v4l2_pix_format s5k4aa_modes[] = {
                 .bytesperline = 640,
                 .colorspace = V4L2_COLORSPACE_SRGB,
                 .priv = 0
+        },
+        {
+                1280,
+                1024,
+                V4L2_PIX_FMT_SBGGR8,
+                V4L2_FIELD_NONE,
+                .sizeimage =
+                        1280 * 1024,
+                .bytesperline = 1280,
+                .colorspace = V4L2_COLORSPACE_SRGB,
+                .priv = 0
         }
 };
 
-const static struct ctrl s5k4aa_ctrls[] = {
+static const struct ctrl s5k4aa_ctrls[] = {
+#define VFLIP_IDX 0
         {
                 {
                         .id             = V4L2_CID_VFLIP,
@@ -77,8 +114,9 @@ const static struct ctrl s5k4aa_ctrls[] = {
                 },
                 .set = s5k4aa_set_vflip,
                 .get = s5k4aa_get_vflip
-
-        }, {
+        },
+#define HFLIP_IDX 1
+        {
                 {
                         .id             = V4L2_CID_HFLIP,
                         .type           = V4L2_CTRL_TYPE_BOOLEAN,
@@ -90,8 +128,9 @@ const static struct ctrl s5k4aa_ctrls[] = {
                 },
                 .set = s5k4aa_set_hflip,
                 .get = s5k4aa_get_hflip
-
-        }, {
+        },
+#define GAIN_IDX 2
+        {
                 {
                         .id             = V4L2_CID_GAIN,
                         .type           = V4L2_CTRL_TYPE_INTEGER,
@@ -99,12 +138,14 @@ const static struct ctrl s5k4aa_ctrls[] = {
                         .minimum        = 0,
                         .maximum        = 127,
                         .step           = 1,
-                        .default_value  = 0xa0,
+                        .default_value  = S5K4AA_DEFAULT_GAIN,
                         .flags          = V4L2_CTRL_FLAG_SLIDER
                 },
                 .set = s5k4aa_set_gain,
                 .get = s5k4aa_get_gain
-        }, {
+        },
+#define EXPOSURE_IDX 3
+        {
                 {
                         .id             = V4L2_CID_EXPOSURE,
                         .type           = V4L2_CTRL_TYPE_INTEGER,
@@ -117,7 +158,36 @@ const static struct ctrl s5k4aa_ctrls[] = {
                 },
                 .set = s5k4aa_set_exposure,
                 .get = s5k4aa_get_exposure
-        }
+        },
+#define NOISE_SUPP_IDX 4
+        {
+                {
+                        .id             = V4L2_CID_PRIVATE_BASE,
+                        .type           = V4L2_CTRL_TYPE_BOOLEAN,
+                        .name           = "Noise suppression (smoothing)",
+                        .minimum        = 0,
+                        .maximum        = 1,
+                        .step           = 1,
+                        .default_value  = 1,
+                },
+                        .set = s5k4aa_set_noise,
+                        .get = s5k4aa_get_noise
+        },
+#define BRIGHTNESS_IDX 5
+        {
+                {
+                        .id             = V4L2_CID_BRIGHTNESS,
+                        .type           = V4L2_CTRL_TYPE_INTEGER,
+                        .name           = "Brightness",
+                        .minimum        = 0,
+                        .maximum        = 0x1f,
+                        .step           = 1,
+                        .default_value  = S5K4AA_DEFAULT_BRIGHTNESS,
+                },
+                        .set = s5k4aa_set_brightness,
+                        .get = s5k4aa_get_brightness
+        },
+
 };
 
 static void s5k4aa_dump_registers(struct sd *sd);
@@ -127,6 +197,7 @@ int s5k4aa_probe(struct sd *sd)
         u8 prod_id[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
         const u8 expected_prod_id[6] = {0x00, 0x10, 0x00, 0x4b, 0x33, 0x75};
         int i, err = 0;
+        s32 *sensor_settings;
 
         if (force_sensor) {
                 if (force_sensor == S5K4AA_SENSOR) {
@@ -185,10 +256,20 @@ int s5k4aa_probe(struct sd *sd)
                 info("Detected a s5k4aa sensor");
 
 sensor_found:
+        sensor_settings = kmalloc(
+                ARRAY_SIZE(s5k4aa_ctrls) * sizeof(s32), GFP_KERNEL);
+        if (!sensor_settings)
+                return -ENOMEM;
+
         sd->gspca_dev.cam.cam_mode = s5k4aa_modes;
         sd->gspca_dev.cam.nmodes = ARRAY_SIZE(s5k4aa_modes);
         sd->desc->ctrls = s5k4aa_ctrls;
         sd->desc->nctrls = ARRAY_SIZE(s5k4aa_ctrls);
+
+        for (i = 0; i < ARRAY_SIZE(s5k4aa_ctrls); i++)
+                sensor_settings[i] = s5k4aa_ctrls[i].qctrl.default_value;
+        sd->sensor_priv = sensor_settings;
+
         return 0;
 }
 
@@ -197,9 +278,45 @@ int s5k4aa_start(struct sd *sd)
         int i, err = 0;
         u8 data[2];
         struct cam *cam = &sd->gspca_dev.cam;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        switch (cam->cam_mode[sd->gspca_dev.curr_mode].width) {
+        case 1280:
+                PDEBUG(D_V4L2, "Configuring camera for SXGA mode");
+
+                for (i = 0; i < ARRAY_SIZE(SXGA_s5k4aa); i++) {
+                        switch (SXGA_s5k4aa[i][0]) {
+                        case BRIDGE:
+                                err = m5602_write_bridge(sd,
+                                                 SXGA_s5k4aa[i][1],
+                                                 SXGA_s5k4aa[i][2]);
+                        break;
+
+                        case SENSOR:
+                                data[0] = SXGA_s5k4aa[i][2];
+                                err = m5602_write_sensor(sd,
+                                                 SXGA_s5k4aa[i][1],
+                                                 data, 1);
+                        break;
+
+                        case SENSOR_LONG:
+                                data[0] = SXGA_s5k4aa[i][2];
+                                data[1] = SXGA_s5k4aa[i][3];
+                                err = m5602_write_sensor(sd,
+                                                  SXGA_s5k4aa[i][1],
+                                                  data, 2);
+                        break;
+
+                        default:
+                                err("Invalid stream command, exiting init");
+                                return -EINVAL;
+                        }
+                }
+                err = s5k4aa_set_noise(&sd->gspca_dev, 0);
+                if (err < 0)
+                        return err;
+                break;
 
-        switch (cam->cam_mode[sd->gspca_dev.curr_mode].width)
-        {
         case 640:
                 PDEBUG(D_V4L2, "Configuring camera for VGA mode");
 
@@ -231,8 +348,37 @@ int s5k4aa_start(struct sd *sd)
                                 return -EINVAL;
                         }
                 }
+                err = s5k4aa_set_noise(&sd->gspca_dev, 1);
+                if (err < 0)
+                        return err;
+                break;
         }
-        return err;
+        if (err < 0)
+                return err;
+
+        err = s5k4aa_set_exposure(&sd->gspca_dev,
+                                   sensor_settings[EXPOSURE_IDX]);
+        if (err < 0)
+                return err;
+
+        err = s5k4aa_set_gain(&sd->gspca_dev, sensor_settings[GAIN_IDX]);
+        if (err < 0)
+                return err;
+
+        err = s5k4aa_set_brightness(&sd->gspca_dev,
+                                     sensor_settings[BRIGHTNESS_IDX]);
+        if (err < 0)
+                return err;
+
+        err = s5k4aa_set_noise(&sd->gspca_dev, sensor_settings[NOISE_SUPP_IDX]);
+        if (err < 0)
+                return err;
+
+        err = s5k4aa_set_vflip(&sd->gspca_dev, sensor_settings[VFLIP_IDX]);
+        if (err < 0)
+                return err;
+
+        return s5k4aa_set_hflip(&sd->gspca_dev, sensor_settings[HFLIP_IDX]);
 }
 
 int s5k4aa_init(struct sd *sd)
@@ -270,62 +416,28 @@ int s5k4aa_init(struct sd *sd)
         if (dump_sensor)
                 s5k4aa_dump_registers(sd);
 
-        if (!err && dmi_check_system(s5k4aa_vflip_dmi_table)) {
-                u8 data = 0x02;
-                info("vertical flip quirk active");
-                m5602_write_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
-                m5602_read_sensor(sd, S5K4AA_READ_MODE, &data, 1);
-                data |= S5K4AA_RM_V_FLIP;
-                data &= ~S5K4AA_RM_H_FLIP;
-                m5602_write_sensor(sd, S5K4AA_READ_MODE, &data, 1);
-
-                /* Decrement COLSTART to preserve color order (BGGR) */
-                m5602_read_sensor(sd, S5K4AA_COLSTART_LO, &data, 1);
-                data--;
-                m5602_write_sensor(sd, S5K4AA_COLSTART_LO, &data, 1);
-
-                /* Increment ROWSTART to preserve color order (BGGR) */
-                m5602_read_sensor(sd, S5K4AA_ROWSTART_LO, &data, 1);
-                data++;
-                m5602_write_sensor(sd, S5K4AA_ROWSTART_LO, &data, 1);
-        }
-
-        return (err < 0) ? err : 0;
-}
-
-int s5k4aa_power_down(struct sd *sd)
-{
-        return 0;
+        return err;
 }
 
-int s5k4aa_get_exposure(struct gspca_dev *gspca_dev, __s32 *val)
+static int s5k4aa_get_exposure(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
-        u8 data = S5K4AA_PAGE_MAP_2;
-        int err;
-
-        err = m5602_write_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
-        if (err < 0)
-                return err;
+        s32 *sensor_settings = sd->sensor_priv;
 
-        err = m5602_read_sensor(sd, S5K4AA_EXPOSURE_HI, &data, 1);
-        if (err < 0)
-                return err;
-
-        *val = data << 8;
-        err = m5602_read_sensor(sd, S5K4AA_EXPOSURE_LO, &data, 1);
-        *val |= data;
+        *val = sensor_settings[EXPOSURE_IDX];
         PDEBUG(D_V4L2, "Read exposure %d", *val);
 
-        return err;
+        return 0;
 }
 
-int s5k4aa_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
+static int s5k4aa_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 data = S5K4AA_PAGE_MAP_2;
         int err;
 
+        sensor_settings[EXPOSURE_IDX] = val;
         PDEBUG(D_V4L2, "Set exposure to %d", val);
         err = m5602_write_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
         if (err < 0)
@@ -340,29 +452,26 @@ int s5k4aa_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
         return err;
 }
 
-int s5k4aa_get_vflip(struct gspca_dev *gspca_dev, __s32 *val)
+static int s5k4aa_get_vflip(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
-        u8 data = S5K4AA_PAGE_MAP_2;
-        int err;
-
-        err = m5602_write_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
-        if (err < 0)
-                return err;
+        s32 *sensor_settings = sd->sensor_priv;
 
-        err = m5602_read_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
-        *val = (data & S5K4AA_RM_V_FLIP) >> 7;
+        *val = sensor_settings[VFLIP_IDX];
         PDEBUG(D_V4L2, "Read vertical flip %d", *val);
 
-        return err;
+        return 0;
 }
 
-int s5k4aa_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
+static int s5k4aa_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 data = S5K4AA_PAGE_MAP_2;
         int err;
 
+        sensor_settings[VFLIP_IDX] = val;
+
         PDEBUG(D_V4L2, "Set vertical flip to %d", val);
         err = m5602_write_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
         if (err < 0)
@@ -370,56 +479,48 @@ int s5k4aa_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
         err = m5602_write_sensor(sd, S5K4AA_READ_MODE, &data, 1);
         if (err < 0)
                 return err;
-        data = ((data & ~S5K4AA_RM_V_FLIP)
-                        | ((val & 0x01) << 7));
-        err = m5602_write_sensor(sd, S5K4AA_READ_MODE, &data, 1);
+
+        err = m5602_read_sensor(sd, S5K4AA_READ_MODE, &data, 1);
         if (err < 0)
                 return err;
 
-        if (val) {
-                err = m5602_read_sensor(sd, S5K4AA_ROWSTART_LO, &data, 1);
-                if (err < 0)
-                        return err;
-
-                data++;
-                err = m5602_write_sensor(sd, S5K4AA_ROWSTART_LO, &data, 1);
-        } else {
-                err = m5602_read_sensor(sd, S5K4AA_ROWSTART_LO, &data, 1);
-                if (err < 0)
-                        return err;
+        if (dmi_check_system(s5k4aa_vflip_dmi_table))
+                val = !val;
 
-                data--;
-                err = m5602_write_sensor(sd, S5K4AA_ROWSTART_LO, &data, 1);
-        }
+        data = ((data & ~S5K4AA_RM_V_FLIP) | ((val & 0x01) << 7));
+        err = m5602_write_sensor(sd, S5K4AA_READ_MODE, &data, 1);
+        if (err < 0)
+                return err;
 
+        err = m5602_read_sensor(sd, S5K4AA_ROWSTART_LO, &data, 1);
+        if (err < 0)
+                return err;
+        data = (data & 0xfe) | !val;
+        err = m5602_write_sensor(sd, S5K4AA_ROWSTART_LO, &data, 1);
         return err;
 }
 
-int s5k4aa_get_hflip(struct gspca_dev *gspca_dev, __s32 *val)
+static int s5k4aa_get_hflip(struct gspca_dev *gspca_dev, __s32 *val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
-        u8 data = S5K4AA_PAGE_MAP_2;
-        int err;
-
-        err = m5602_write_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
-        if (err < 0)
-                return err;
+        s32 *sensor_settings = sd->sensor_priv;
 
-        err = m5602_read_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
-        *val = (data & S5K4AA_RM_H_FLIP) >> 6;
+        *val = sensor_settings[HFLIP_IDX];
         PDEBUG(D_V4L2, "Read horizontal flip %d", *val);
 
-        return err;
+        return 0;
 }
 
-int s5k4aa_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
+static int s5k4aa_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 data = S5K4AA_PAGE_MAP_2;
         int err;
 
-        PDEBUG(D_V4L2, "Set horizontal flip to %d",
-               val);
+        sensor_settings[HFLIP_IDX] = val;
+
+        PDEBUG(D_V4L2, "Set horizontal flip to %d", val);
         err = m5602_write_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
         if (err < 0)
                 return err;
@@ -427,62 +528,116 @@ int s5k4aa_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
         if (err < 0)
                 return err;
 
+        err = m5602_read_sensor(sd, S5K4AA_READ_MODE, &data, 1);
+        if (err < 0)
+                return err;
+
+        if (dmi_check_system(s5k4aa_vflip_dmi_table))
+                val = !val;
+
         data = ((data & ~S5K4AA_RM_H_FLIP) | ((val & 0x01) << 6));
         err = m5602_write_sensor(sd, S5K4AA_READ_MODE, &data, 1);
         if (err < 0)
                 return err;
 
-        if (val) {
-                err = m5602_read_sensor(sd, S5K4AA_COLSTART_LO, &data, 1);
-                if (err < 0)
-                        return err;
-                data++;
-                err = m5602_write_sensor(sd, S5K4AA_COLSTART_LO, &data, 1);
-                if (err < 0)
-                        return err;
-        } else {
-                err = m5602_read_sensor(sd, S5K4AA_COLSTART_LO, &data, 1);
-                if (err < 0)
-                        return err;
-                data--;
-                err = m5602_write_sensor(sd, S5K4AA_COLSTART_LO, &data, 1);
-        }
-
+        err = m5602_read_sensor(sd, S5K4AA_COLSTART_LO, &data, 1);
+        if (err < 0)
+                return err;
+        data = (data & 0xfe) | !val;
+        err = m5602_write_sensor(sd, S5K4AA_COLSTART_LO, &data, 1);
         return err;
 }
 
-int s5k4aa_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
+static int s5k4aa_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[GAIN_IDX];
+        PDEBUG(D_V4L2, "Read gain %d", *val);
+        return 0;
+}
+
+static int s5k4aa_set_gain(struct gspca_dev *gspca_dev, __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 data = S5K4AA_PAGE_MAP_2;
         int err;
 
+        sensor_settings[GAIN_IDX] = val;
+
+        PDEBUG(D_V4L2, "Set gain to %d", val);
         err = m5602_write_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
         if (err < 0)
                 return err;
 
-        err = m5602_read_sensor(sd, S5K4AA_GAIN_2, &data, 1);
-        *val = data;
-        PDEBUG(D_V4L2, "Read gain %d", *val);
+        data = val & 0xff;
+        err = m5602_write_sensor(sd, S5K4AA_GAIN, &data, 1);
 
         return err;
 }
 
-int s5k4aa_set_gain(struct gspca_dev *gspca_dev, __s32 val)
+static int s5k4aa_get_brightness(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[BRIGHTNESS_IDX];
+        PDEBUG(D_V4L2, "Read brightness %d", *val);
+        return 0;
+}
+
+static int s5k4aa_set_brightness(struct gspca_dev *gspca_dev, __s32 val)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
         u8 data = S5K4AA_PAGE_MAP_2;
         int err;
 
-        PDEBUG(D_V4L2, "Set gain to %d", val);
+        sensor_settings[BRIGHTNESS_IDX] = val;
+
+        PDEBUG(D_V4L2, "Set brightness to %d", val);
         err = m5602_write_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
         if (err < 0)
                 return err;
 
         data = val & 0xff;
-        err = m5602_write_sensor(sd, S5K4AA_GAIN_2, &data, 1);
+        return m5602_write_sensor(sd, S5K4AA_BRIGHTNESS, &data, 1);
+}
 
-        return err;
+static int s5k4aa_get_noise(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[NOISE_SUPP_IDX];
+        PDEBUG(D_V4L2, "Read noise %d", *val);
+        return 0;
+}
+
+static int s5k4aa_set_noise(struct gspca_dev *gspca_dev, __s32 val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+        u8 data = S5K4AA_PAGE_MAP_2;
+        int err;
+
+        sensor_settings[NOISE_SUPP_IDX] = val;
+
+        PDEBUG(D_V4L2, "Set noise to %d", val);
+        err = m5602_write_sensor(sd, S5K4AA_PAGE_MAP, &data, 1);
+        if (err < 0)
+                return err;
+
+        data = val & 0x01;
+        return m5602_write_sensor(sd, S5K4AA_NOISE_SUPP, &data, 1);
+}
+
+void s5k4aa_disconnect(struct sd *sd)
+{
+        sd->sensor = NULL;
+        kfree(sd->sensor_priv);
 }
 
 static void s5k4aa_dump_registers(struct sd *sd)
diff --git a/drivers/media/video/gspca/m5602/m5602_s5k4aa.h b/drivers/media/video/gspca/m5602/m5602_s5k4aa.h
index ca854d4f9475..4440da4e7f0f 100644
--- a/drivers/media/video/gspca/m5602/m5602_s5k4aa.h
+++ b/drivers/media/video/gspca/m5602/m5602_s5k4aa.h
@@ -47,8 +47,9 @@
 #define S5K4AA_H_BLANK_LO__             0x1e
 #define S5K4AA_EXPOSURE_HI              0x17
 #define S5K4AA_EXPOSURE_LO              0x18
-#define S5K4AA_GAIN_1                   0x1f /* (digital?) gain : 5 bits */
-#define S5K4AA_GAIN_2                   0x20 /* (analogue?) gain : 7 bits */
+#define S5K4AA_BRIGHTNESS               0x1f /* (digital?) gain : 5 bits */
+#define S5K4AA_GAIN                     0x20 /* (analogue?) gain : 7 bits */
+#define S5K4AA_NOISE_SUPP               0x37
 
 #define S5K4AA_RM_ROW_SKIP_4X           0x08
 #define S5K4AA_RM_ROW_SKIP_2X           0x04
@@ -57,6 +58,9 @@
 #define S5K4AA_RM_H_FLIP                0x40
 #define S5K4AA_RM_V_FLIP                0x80
 
+#define S5K4AA_DEFAULT_GAIN             0x5f
+#define S5K4AA_DEFAULT_BRIGHTNESS       0x10
+
 /*****************************************************************************/
 
 /* Kernel module parameters */
@@ -66,25 +70,17 @@ extern int dump_sensor;
 int s5k4aa_probe(struct sd *sd);
 int s5k4aa_init(struct sd *sd);
 int s5k4aa_start(struct sd *sd);
-int s5k4aa_power_down(struct sd *sd);
-
-int s5k4aa_get_exposure(struct gspca_dev *gspca_dev, __s32 *val);
-int s5k4aa_set_exposure(struct gspca_dev *gspca_dev, __s32 val);
-int s5k4aa_get_vflip(struct gspca_dev *gspca_dev, __s32 *val);
-int s5k4aa_set_vflip(struct gspca_dev *gspca_dev, __s32 val);
-int s5k4aa_get_hflip(struct gspca_dev *gspca_dev, __s32 *val);
-int s5k4aa_set_hflip(struct gspca_dev *gspca_dev, __s32 val);
-int s5k4aa_get_gain(struct gspca_dev *gspca_dev, __s32 *val);
-int s5k4aa_set_gain(struct gspca_dev *gspca_dev, __s32 val);
+void s5k4aa_disconnect(struct sd *sd);
 
 static const struct m5602_sensor s5k4aa = {
         .name = "S5K4AA",
+        .i2c_slave_id = 0x5a,
+        .i2c_regW = 2,
+
         .probe = s5k4aa_probe,
         .init = s5k4aa_init,
         .start = s5k4aa_start,
-        .power_down = s5k4aa_power_down,
-        .i2c_slave_id = 0x5a,
-        .i2c_regW = 2,
+        .disconnect = s5k4aa_disconnect,
 };
 
 static const unsigned char preinit_s5k4aa[][4] =
@@ -179,30 +175,12 @@ static const unsigned char init_s5k4aa[][4] =
         {SENSOR, S5K4AA_PAGE_MAP, 0x02, 0x00},
         {SENSOR, 0x0c, 0x05, 0x00},
         {SENSOR, 0x02, 0x0e, 0x00},
-        {SENSOR, S5K4AA_GAIN_1, 0x0f, 0x00},
-        {SENSOR, S5K4AA_GAIN_2, 0x00, 0x00},
-        {SENSOR, S5K4AA_GLOBAL_GAIN__, 0x01, 0x00},
-        {SENSOR, 0x11, 0x00, 0x00},
-        {SENSOR, 0x12, 0x00, 0x00},
-        {SENSOR, S5K4AA_PAGE_MAP, 0x02, 0x00},
         {SENSOR, S5K4AA_READ_MODE, 0xa0, 0x00},
         {SENSOR, 0x37, 0x00, 0x00},
-        {SENSOR, S5K4AA_ROWSTART_HI, 0x00, 0x00},
-        {SENSOR, S5K4AA_ROWSTART_LO, 0x2a, 0x00},
-        {SENSOR, S5K4AA_COLSTART_HI, 0x00, 0x00},
-        {SENSOR, S5K4AA_COLSTART_LO, 0x0b, 0x00},
-        {SENSOR, S5K4AA_WINDOW_HEIGHT_HI, 0x03, 0x00},
-        {SENSOR, S5K4AA_WINDOW_HEIGHT_LO, 0xc4, 0x00},
-        {SENSOR, S5K4AA_WINDOW_WIDTH_HI, 0x05, 0x00},
-        {SENSOR, S5K4AA_WINDOW_WIDTH_LO, 0x08, 0x00},
-        {SENSOR, S5K4AA_H_BLANK_HI__, 0x00, 0x00},
-        {SENSOR, S5K4AA_H_BLANK_LO__, 0x48, 0x00},
-        {SENSOR, S5K4AA_EXPOSURE_HI, 0x00, 0x00},
-        {SENSOR, S5K4AA_EXPOSURE_LO, 0x43, 0x00},
-        {SENSOR, 0x11, 0x04, 0x00},
-        {SENSOR, 0x12, 0xc3, 0x00},
-        {SENSOR, S5K4AA_PAGE_MAP, 0x02, 0x00},
+};
 
+static const unsigned char VGA_s5k4aa[][4] =
+{
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
         {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
@@ -238,7 +216,7 @@ static const unsigned char init_s5k4aa[][4] =
         {SENSOR, 0x37, 0x01, 0x00},
         /* ROWSTART_HI, ROWSTART_LO : 10 + (1024-960)/2 = 42 = 0x002a */
         {SENSOR, S5K4AA_ROWSTART_HI, 0x00, 0x00},
-        {SENSOR, S5K4AA_ROWSTART_LO, 0x2a, 0x00},
+        {SENSOR, S5K4AA_ROWSTART_LO, 0x29, 0x00},
         {SENSOR, S5K4AA_COLSTART_HI, 0x00, 0x00},
         {SENSOR, S5K4AA_COLSTART_LO, 0x0c, 0x00},
         /* window_height_hi, window_height_lo : 960 = 0x03c0 */
@@ -255,12 +233,9 @@ static const unsigned char init_s5k4aa[][4] =
         {SENSOR, 0x12, 0xc3, 0x00},
         {SENSOR, S5K4AA_PAGE_MAP, 0x02, 0x00},
         {SENSOR, 0x02, 0x0e, 0x00},
-        {SENSOR_LONG, S5K4AA_GLOBAL_GAIN__, 0x0f, 0x00},
-        {SENSOR, S5K4AA_GAIN_1, 0x0b, 0x00},
-        {SENSOR, S5K4AA_GAIN_2, 0xa0, 0x00}
 };
 
-static const unsigned char VGA_s5k4aa[][4] =
+static const unsigned char SXGA_s5k4aa[][4] =
 {
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
@@ -273,50 +248,42 @@ static const unsigned char VGA_s5k4aa[][4] =
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        /* VSYNC_PARA, VSYNC_PARA : img height 480 = 0x01e0 */
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0xe0, 0x00},
+        /* VSYNC_PARA, VSYNC_PARA : img height 1024 = 0x0400 */
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x04, 0x00},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
         {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00},
         {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        /* HSYNC_PARA, HSYNC_PARA : img width 640 = 0x0280 */
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x80, 0x00},
+        /* HSYNC_PARA, HSYNC_PARA : img width 1280 = 0x0500 */
+        {BRIDGE, M5602_XB_HSYNC_PARA, 0x05, 0x00},
+        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xa0, 0x00}, /* 48 MHz */
 
         {SENSOR, S5K4AA_PAGE_MAP, 0x02, 0x00},
-        {SENSOR, S5K4AA_READ_MODE, S5K4AA_RM_H_FLIP | S5K4AA_RM_ROW_SKIP_2X
-                | S5K4AA_RM_COL_SKIP_2X, 0x00},
-        /* 0x37 : Fix image stability when light is too bright and improves
-         * image quality in 640x480, but worsens it in 1280x1024 */
+        {SENSOR, S5K4AA_READ_MODE, S5K4AA_RM_H_FLIP, 0x00},
         {SENSOR, 0x37, 0x01, 0x00},
-        /* ROWSTART_HI, ROWSTART_LO : 10 + (1024-960)/2 = 42 = 0x002a */
         {SENSOR, S5K4AA_ROWSTART_HI, 0x00, 0x00},
-        {SENSOR, S5K4AA_ROWSTART_LO, 0x2a, 0x00},
+        {SENSOR, S5K4AA_ROWSTART_LO, 0x09, 0x00},
         {SENSOR, S5K4AA_COLSTART_HI, 0x00, 0x00},
-        {SENSOR, S5K4AA_COLSTART_LO, 0x0c, 0x00},
-        /* window_height_hi, window_height_lo : 960 = 0x03c0 */
-        {SENSOR, S5K4AA_WINDOW_HEIGHT_HI, 0x03, 0x00},
-        {SENSOR, S5K4AA_WINDOW_HEIGHT_LO, 0xc0, 0x00},
-        /* window_width_hi, window_width_lo : 1280 = 0x0500 */
+        {SENSOR, S5K4AA_COLSTART_LO, 0x0a, 0x00},
+        {SENSOR, S5K4AA_WINDOW_HEIGHT_HI, 0x04, 0x00},
+        {SENSOR, S5K4AA_WINDOW_HEIGHT_LO, 0x00, 0x00},
         {SENSOR, S5K4AA_WINDOW_WIDTH_HI, 0x05, 0x00},
         {SENSOR, S5K4AA_WINDOW_WIDTH_LO, 0x00, 0x00},
-        {SENSOR, S5K4AA_H_BLANK_HI__, 0x00, 0x00},
-        {SENSOR, S5K4AA_H_BLANK_LO__, 0xa8, 0x00}, /* helps to sync... */
+        {SENSOR, S5K4AA_H_BLANK_HI__, 0x01, 0x00},
+        {SENSOR, S5K4AA_H_BLANK_LO__, 0xa8, 0x00},
         {SENSOR, S5K4AA_EXPOSURE_HI, 0x01, 0x00},
         {SENSOR, S5K4AA_EXPOSURE_LO, 0x00, 0x00},
         {SENSOR, 0x11, 0x04, 0x00},
         {SENSOR, 0x12, 0xc3, 0x00},
         {SENSOR, S5K4AA_PAGE_MAP, 0x02, 0x00},
         {SENSOR, 0x02, 0x0e, 0x00},
-        {SENSOR_LONG, S5K4AA_GLOBAL_GAIN__, 0x0f, 0x00},
-        {SENSOR, S5K4AA_GAIN_1, 0x0b, 0x00},
-        {SENSOR, S5K4AA_GAIN_2, 0xa0, 0x00}
 };
 
+
 #endif
diff --git a/drivers/media/video/gspca/m5602/m5602_s5k83a.c b/drivers/media/video/gspca/m5602/m5602_s5k83a.c
index 42c86aa4dc8d..7127321ace8c 100644
--- a/drivers/media/video/gspca/m5602/m5602_s5k83a.c
+++ b/drivers/media/video/gspca/m5602/m5602_s5k83a.c
@@ -16,8 +16,20 @@
  *
  */
 
+#include <linux/kthread.h>
 #include "m5602_s5k83a.h"
 
+static int s5k83a_set_gain(struct gspca_dev *gspca_dev, __s32 val);
+static int s5k83a_get_gain(struct gspca_dev *gspca_dev, __s32 *val);
+static int s5k83a_set_brightness(struct gspca_dev *gspca_dev, __s32 val);
+static int s5k83a_get_brightness(struct gspca_dev *gspca_dev, __s32 *val);
+static int s5k83a_set_exposure(struct gspca_dev *gspca_dev, __s32 val);
+static int s5k83a_get_exposure(struct gspca_dev *gspca_dev, __s32 *val);
+static int s5k83a_get_vflip(struct gspca_dev *gspca_dev, __s32 *val);
+static int s5k83a_set_vflip(struct gspca_dev *gspca_dev, __s32 val);
+static int s5k83a_get_hflip(struct gspca_dev *gspca_dev, __s32 *val);
+static int s5k83a_set_hflip(struct gspca_dev *gspca_dev, __s32 val);
+
 static struct v4l2_pix_format s5k83a_modes[] = {
         {
                 640,
@@ -32,68 +44,77 @@ static struct v4l2_pix_format s5k83a_modes[] = {
         }
 };
 
-const static struct ctrl s5k83a_ctrls[] = {
+static const struct ctrl s5k83a_ctrls[] = {
+#define GAIN_IDX 0
         {
                 {
-                        .id = V4L2_CID_BRIGHTNESS,
+                        .id = V4L2_CID_GAIN,
                         .type = V4L2_CTRL_TYPE_INTEGER,
-                        .name = "brightness",
+                        .name = "gain",
                         .minimum = 0x00,
                         .maximum = 0xff,
                         .step = 0x01,
-                        .default_value = S5K83A_DEFAULT_BRIGHTNESS,
+                        .default_value = S5K83A_DEFAULT_GAIN,
                         .flags = V4L2_CTRL_FLAG_SLIDER
                 },
-                        .set = s5k83a_set_brightness,
-                        .get = s5k83a_get_brightness
+                        .set = s5k83a_set_gain,
+                        .get = s5k83a_get_gain
 
-        }, {
+        },
+#define BRIGHTNESS_IDX 1
+        {
                 {
-                        .id = V4L2_CID_WHITENESS,
+                        .id = V4L2_CID_BRIGHTNESS,
                         .type = V4L2_CTRL_TYPE_INTEGER,
-                        .name = "whiteness",
+                        .name = "brightness",
                         .minimum = 0x00,
                         .maximum = 0xff,
                         .step = 0x01,
-                        .default_value = S5K83A_DEFAULT_WHITENESS,
+                        .default_value = S5K83A_DEFAULT_BRIGHTNESS,
                         .flags = V4L2_CTRL_FLAG_SLIDER
                 },
-                        .set = s5k83a_set_whiteness,
-                        .get = s5k83a_get_whiteness,
-        }, {
+                        .set = s5k83a_set_brightness,
+                        .get = s5k83a_get_brightness,
+        },
+#define EXPOSURE_IDX 2
+        {
                 {
-                        .id = V4L2_CID_GAIN,
+                        .id = V4L2_CID_EXPOSURE,
                         .type = V4L2_CTRL_TYPE_INTEGER,
-                        .name = "gain",
+                        .name = "exposure",
                         .minimum = 0x00,
-                        .maximum = S5K83A_MAXIMUM_GAIN,
+                        .maximum = S5K83A_MAXIMUM_EXPOSURE,
                         .step = 0x01,
-                        .default_value = S5K83A_DEFAULT_GAIN,
+                        .default_value = S5K83A_DEFAULT_EXPOSURE,
                         .flags = V4L2_CTRL_FLAG_SLIDER
                 },
-                        .set = s5k83a_set_gain,
-                        .get = s5k83a_get_gain
-        }, {
+                        .set = s5k83a_set_exposure,
+                        .get = s5k83a_get_exposure
+        },
+#define HFLIP_IDX 3
+        {
                 {
-                        .id         = V4L2_CID_HFLIP,
-                        .type       = V4L2_CTRL_TYPE_BOOLEAN,
-                        .name       = "horizontal flip",
-                        .minimum    = 0,
-                        .maximum    = 1,
-                        .step       = 1,
-                        .default_value  = 0
+                        .id = V4L2_CID_HFLIP,
+                        .type = V4L2_CTRL_TYPE_BOOLEAN,
+                        .name = "horizontal flip",
+                        .minimum = 0,
+                        .maximum = 1,
+                        .step = 1,
+                        .default_value = 0
                 },
                         .set = s5k83a_set_hflip,
                         .get = s5k83a_get_hflip
-        }, {
+        },
+#define VFLIP_IDX 4
+        {
                 {
-                 .id         = V4L2_CID_VFLIP,
-                .type       = V4L2_CTRL_TYPE_BOOLEAN,
-                .name       = "vertical flip",
-                .minimum    = 0,
-                .maximum    = 1,
-                .step       = 1,
-                .default_value  = 0
+                        .id = V4L2_CID_VFLIP,
+                        .type = V4L2_CTRL_TYPE_BOOLEAN,
+                        .name = "vertical flip",
+                        .minimum = 0,
+                        .maximum = 1,
+                        .step = 1,
+                        .default_value = 0
                 },
                 .set = s5k83a_set_vflip,
                 .get = s5k83a_get_vflip
@@ -101,9 +122,14 @@ const static struct ctrl s5k83a_ctrls[] = {
 };
 
 static void s5k83a_dump_registers(struct sd *sd);
+static int s5k83a_get_rotation(struct sd *sd, u8 *reg_data);
+static int s5k83a_set_led_indication(struct sd *sd, u8 val);
+static int s5k83a_set_flip_real(struct gspca_dev *gspca_dev,
+                                __s32 vflip, __s32 hflip);
 
 int s5k83a_probe(struct sd *sd)
 {
+        struct s5k83a_priv *sens_priv;
         u8 prod_id = 0, ver_id = 0;
         int i, err = 0;
 
@@ -145,16 +171,36 @@ int s5k83a_probe(struct sd *sd)
                 info("Detected a s5k83a sensor");
 
 sensor_found:
+        sens_priv = kmalloc(
+                sizeof(struct s5k83a_priv), GFP_KERNEL);
+        if (!sens_priv)
+                return -ENOMEM;
+
+        sens_priv->settings =
+        kmalloc(sizeof(s32)*ARRAY_SIZE(s5k83a_ctrls), GFP_KERNEL);
+        if (!sens_priv->settings)
+                return -ENOMEM;
+
         sd->gspca_dev.cam.cam_mode = s5k83a_modes;
         sd->gspca_dev.cam.nmodes = ARRAY_SIZE(s5k83a_modes);
         sd->desc->ctrls = s5k83a_ctrls;
         sd->desc->nctrls = ARRAY_SIZE(s5k83a_ctrls);
+
+        /* null the pointer! thread is't running now */
+        sens_priv->rotation_thread = NULL;
+
+        for (i = 0; i < ARRAY_SIZE(s5k83a_ctrls); i++)
+                sens_priv->settings[i] = s5k83a_ctrls[i].qctrl.default_value;
+
+        sd->sensor_priv = sens_priv;
         return 0;
 }
 
 int s5k83a_init(struct sd *sd)
 {
         int i, err = 0;
+        s32 *sensor_settings =
+                        ((struct s5k83a_priv *) sd->sensor_priv)->settings;
 
         for (i = 0; i < ARRAY_SIZE(init_s5k83a) && !err; i++) {
                 u8 data[2] = {0x00, 0x00};
@@ -187,87 +233,138 @@ int s5k83a_init(struct sd *sd)
         if (dump_sensor)
                 s5k83a_dump_registers(sd);
 
-        return (err < 0) ? err : 0;
-}
+        err = s5k83a_set_gain(&sd->gspca_dev, sensor_settings[GAIN_IDX]);
+        if (err < 0)
+                return err;
 
-int s5k83a_start(struct sd *sd)
-{
-        return s5k83a_set_led_indication(sd, 1);
-}
+        err = s5k83a_set_brightness(&sd->gspca_dev,
+                                     sensor_settings[BRIGHTNESS_IDX]);
+        if (err < 0)
+                return err;
 
-int s5k83a_stop(struct sd *sd)
-{
-        return s5k83a_set_led_indication(sd, 0);
+        err = s5k83a_set_exposure(&sd->gspca_dev,
+                                   sensor_settings[EXPOSURE_IDX]);
+        if (err < 0)
+                return err;
+
+        err = s5k83a_set_hflip(&sd->gspca_dev, sensor_settings[HFLIP_IDX]);
+        if (err < 0)
+                return err;
+
+        err = s5k83a_set_vflip(&sd->gspca_dev, sensor_settings[VFLIP_IDX]);
+
+        return err;
 }
 
-int s5k83a_power_down(struct sd *sd)
+static int rotation_thread_function(void *data)
 {
+        struct sd *sd = (struct sd *) data;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
+        u8 reg, previous_rotation = 0;
+        __s32 vflip, hflip;
+
+        set_current_state(TASK_INTERRUPTIBLE);
+        while (!schedule_timeout(100)) {
+                if (mutex_lock_interruptible(&sd->gspca_dev.usb_lock))
+                        break;
+
+                s5k83a_get_rotation(sd, &reg);
+                if (previous_rotation != reg) {
+                        previous_rotation = reg;
+                        info("Camera was flipped");
+
+                        s5k83a_get_vflip((struct gspca_dev *) sd, &vflip);
+                        s5k83a_get_hflip((struct gspca_dev *) sd, &hflip);
+
+                        if (reg) {
+                                vflip = !vflip;
+                                hflip = !hflip;
+                        }
+                        s5k83a_set_flip_real((struct gspca_dev *) sd,
+                                              vflip, hflip);
+                }
+
+                mutex_unlock(&sd->gspca_dev.usb_lock);
+                set_current_state(TASK_INTERRUPTIBLE);
+        }
+
+        /* return to "front" flip */
+        if (previous_rotation) {
+                s5k83a_get_vflip((struct gspca_dev *) sd, &vflip);
+                s5k83a_get_hflip((struct gspca_dev *) sd, &hflip);
+                s5k83a_set_flip_real((struct gspca_dev *) sd, vflip, hflip);
+        }
+
+        sens_priv->rotation_thread = NULL;
         return 0;
 }
 
-static void s5k83a_dump_registers(struct sd *sd)
+int s5k83a_start(struct sd *sd)
 {
-        int address;
-        u8 page, old_page;
-        m5602_read_sensor(sd, S5K83A_PAGE_MAP, &old_page, 1);
+        int i, err = 0;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
 
-        for (page = 0; page < 16; page++) {
-                m5602_write_sensor(sd, S5K83A_PAGE_MAP, &page, 1);
-                info("Dumping the s5k83a register state for page 0x%x", page);
-                for (address = 0; address <= 0xff; address++) {
-                        u8 val = 0;
-                        m5602_read_sensor(sd, address, &val, 1);
-                        info("register 0x%x contains 0x%x",
-                             address, val);
-                }
+        /* Create another thread, polling the GPIO ports of the camera to check
+           if it got rotated. This is how the windows driver does it so we have
+           to assume that there is no better way of accomplishing this */
+        sens_priv->rotation_thread = kthread_create(rotation_thread_function,
+                                                    sd, "rotation thread");
+        wake_up_process(sens_priv->rotation_thread);
+
+        /* Preinit the sensor */
+        for (i = 0; i < ARRAY_SIZE(start_s5k83a) && !err; i++) {
+                u8 data[2] = {start_s5k83a[i][2], start_s5k83a[i][3]};
+                if (start_s5k83a[i][0] == SENSOR)
+                        err = m5602_write_sensor(sd, start_s5k83a[i][1],
+                                data, 2);
+                else
+                        err = m5602_write_bridge(sd, start_s5k83a[i][1],
+                                data[0]);
         }
-        info("s5k83a register state dump complete");
+        if (err < 0)
+                return err;
 
-        for (page = 0; page < 16; page++) {
-                m5602_write_sensor(sd, S5K83A_PAGE_MAP, &page, 1);
-                info("Probing for which registers that are read/write "
-                      "for page 0x%x", page);
-                for (address = 0; address <= 0xff; address++) {
-                        u8 old_val, ctrl_val, test_val = 0xff;
+        return s5k83a_set_led_indication(sd, 1);
+}
 
-                        m5602_read_sensor(sd, address, &old_val, 1);
-                        m5602_write_sensor(sd, address, &test_val, 1);
-                        m5602_read_sensor(sd, address, &ctrl_val, 1);
+int s5k83a_stop(struct sd *sd)
+{
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
 
-                        if (ctrl_val == test_val)
-                                info("register 0x%x is writeable", address);
-                        else
-                                info("register 0x%x is read only", address);
+        if (sens_priv->rotation_thread)
+                kthread_stop(sens_priv->rotation_thread);
 
-                        /* Restore original val */
-                        m5602_write_sensor(sd, address, &old_val, 1);
-                }
-        }
-        info("Read/write register probing complete");
-        m5602_write_sensor(sd, S5K83A_PAGE_MAP, &old_page, 1);
+        return s5k83a_set_led_indication(sd, 0);
 }
 
-int s5k83a_get_brightness(struct gspca_dev *gspca_dev, __s32 *val)
+void s5k83a_disconnect(struct sd *sd)
 {
-        int err;
-        u8 data[2];
-        struct sd *sd = (struct sd *) gspca_dev;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
 
-        err = m5602_read_sensor(sd, S5K83A_BRIGHTNESS, data, 2);
-        if (err < 0)
-                return err;
+        s5k83a_stop(sd);
+
+        sd->sensor = NULL;
+        kfree(sens_priv->settings);
+        kfree(sens_priv);
+}
 
-        data[1] = data[1] << 1;
-        *val = data[1];
+static int s5k83a_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
 
-        return err;
+        *val = sens_priv->settings[GAIN_IDX];
+        return 0;
 }
 
-int s5k83a_set_brightness(struct gspca_dev *gspca_dev, __s32 val)
+static int s5k83a_set_gain(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
         u8 data[2];
         struct sd *sd = (struct sd *) gspca_dev;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
+
+        sens_priv->settings[GAIN_IDX] = val;
 
         data[0] = 0x00;
         data[1] = 0x20;
@@ -283,89 +380,69 @@ int s5k83a_set_brightness(struct gspca_dev *gspca_dev, __s32 val)
 
         /* FIXME: This is not sane, we need to figure out the composition
                   of these registers */
-        data[0] = val >> 3; /* brightness, high 5 bits */
-        data[1] = val >> 1; /* brightness, high 7 bits */
-        err = m5602_write_sensor(sd, S5K83A_BRIGHTNESS, data, 2);
+        data[0] = val >> 3; /* gain, high 5 bits */
+        data[1] = val >> 1; /* gain, high 7 bits */
+        err = m5602_write_sensor(sd, S5K83A_GAIN, data, 2);
 
         return err;
 }
 
-int s5k83a_get_whiteness(struct gspca_dev *gspca_dev, __s32 *val)
+static int s5k83a_get_brightness(struct gspca_dev *gspca_dev, __s32 *val)
 {
-        int err;
-        u8 data;
         struct sd *sd = (struct sd *) gspca_dev;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
 
-        err = m5602_read_sensor(sd, S5K83A_WHITENESS, &data, 1);
-        if (err < 0)
-                return err;
-
-        *val = data;
-
-        return err;
+        *val = sens_priv->settings[BRIGHTNESS_IDX];
+        return 0;
 }
 
-int s5k83a_set_whiteness(struct gspca_dev *gspca_dev, __s32 val)
+static int s5k83a_set_brightness(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
         u8 data[1];
         struct sd *sd = (struct sd *) gspca_dev;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
 
+        sens_priv->settings[BRIGHTNESS_IDX] = val;
         data[0] = val;
-        err = m5602_write_sensor(sd, S5K83A_WHITENESS, data, 1);
-
+        err = m5602_write_sensor(sd, S5K83A_BRIGHTNESS, data, 1);
         return err;
 }
 
-int s5k83a_get_gain(struct gspca_dev *gspca_dev, __s32 *val)
+static int s5k83a_get_exposure(struct gspca_dev *gspca_dev, __s32 *val)
 {
-        int err;
-        u8 data[2];
         struct sd *sd = (struct sd *) gspca_dev;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
 
-        err = m5602_read_sensor(sd, S5K83A_GAIN, data, 2);
-        if (err < 0)
-                return err;
-
-        data[1] = data[1] & 0x3f;
-        if (data[1] > S5K83A_MAXIMUM_GAIN)
-                data[1] = S5K83A_MAXIMUM_GAIN;
-
-        *val = data[1];
-
-        return err;
+        *val = sens_priv->settings[EXPOSURE_IDX];
+        return 0;
 }
 
-int s5k83a_set_gain(struct gspca_dev *gspca_dev, __s32 val)
+static int s5k83a_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
         u8 data[2];
         struct sd *sd = (struct sd *) gspca_dev;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
 
+        sens_priv->settings[EXPOSURE_IDX] = val;
         data[0] = 0;
         data[1] = val;
-        err = m5602_write_sensor(sd, S5K83A_GAIN, data, 2);
+        err = m5602_write_sensor(sd, S5K83A_EXPOSURE, data, 2);
         return err;
 }
 
-int s5k83a_get_vflip(struct gspca_dev *gspca_dev, __s32 *val)
+static int s5k83a_get_vflip(struct gspca_dev *gspca_dev, __s32 *val)
 {
-        int err;
-        u8 data[1];
         struct sd *sd = (struct sd *) gspca_dev;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
 
-        data[0] = 0x05;
-        err = m5602_write_sensor(sd, S5K83A_PAGE_MAP, data, 1);
-        if (err < 0)
-                return err;
-
-        err = m5602_read_sensor(sd, S5K83A_FLIP, data, 1);
-        *val = (data[0] | 0x40) ? 1 : 0;
-
-        return err;
+        *val = sens_priv->settings[VFLIP_IDX];
+        return 0;
 }
 
-int s5k83a_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
+static int s5k83a_set_flip_real(struct gspca_dev *gspca_dev,
+                                __s32 vflip, __s32 hflip)
 {
         int err;
         u8 data[1];
@@ -376,69 +453,83 @@ int s5k83a_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
         if (err < 0)
                 return err;
 
-        err = m5602_read_sensor(sd, S5K83A_FLIP, data, 1);
-        if (err < 0)
-                return err;
+        /* six bit is vflip, seven is hflip */
+        data[0] = S5K83A_FLIP_MASK;
+        data[0] = (vflip) ? data[0] | 0x40 : data[0];
+        data[0] = (hflip) ? data[0] | 0x80 : data[0];
 
-        /* set or zero six bit, seven is hflip */
-        data[0] = (val) ? (data[0] & 0x80) | 0x40 | S5K83A_FLIP_MASK
-                        : (data[0] & 0x80) | S5K83A_FLIP_MASK;
         err = m5602_write_sensor(sd, S5K83A_FLIP, data, 1);
         if (err < 0)
                 return err;
 
-        data[0] = (val) ? 0x0b : 0x0a;
+        data[0] = (vflip) ? 0x0b : 0x0a;
         err = m5602_write_sensor(sd, S5K83A_VFLIP_TUNE, data, 1);
+        if (err < 0)
+                return err;
 
+        data[0] = (hflip) ? 0x0a : 0x0b;
+        err = m5602_write_sensor(sd, S5K83A_HFLIP_TUNE, data, 1);
         return err;
 }
 
-int s5k83a_get_hflip(struct gspca_dev *gspca_dev, __s32 *val)
+static int s5k83a_set_vflip(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
-        u8 data[1];
+        u8 reg;
+        __s32 hflip;
         struct sd *sd = (struct sd *) gspca_dev;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
 
-        data[0] = 0x05;
-        err = m5602_write_sensor(sd, S5K83A_PAGE_MAP, data, 1);
+        sens_priv->settings[VFLIP_IDX] = val;
+
+        s5k83a_get_hflip(gspca_dev, &hflip);
+
+        err = s5k83a_get_rotation(sd, &reg);
         if (err < 0)
                 return err;
+        if (reg) {
+                val = !val;
+                hflip = !hflip;
+        }
 
-        err = m5602_read_sensor(sd, S5K83A_FLIP, data, 1);
-        *val = (data[0] | 0x80) ? 1 : 0;
-
+        err = s5k83a_set_flip_real(gspca_dev, val, hflip);
         return err;
 }
 
-int s5k83a_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
+static int s5k83a_get_hflip(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
+
+        *val = sens_priv->settings[HFLIP_IDX];
+        return 0;
+}
+
+static int s5k83a_set_hflip(struct gspca_dev *gspca_dev, __s32 val)
 {
         int err;
-        u8 data[1];
+        u8 reg;
+        __s32 vflip;
         struct sd *sd = (struct sd *) gspca_dev;
+        struct s5k83a_priv *sens_priv = sd->sensor_priv;
 
-        data[0] = 0x05;
-        err = m5602_write_sensor(sd, S5K83A_PAGE_MAP, data, 1);
-        if (err < 0)
-                return err;
+        sens_priv->settings[HFLIP_IDX] = val;
 
-        err = m5602_read_sensor(sd, S5K83A_FLIP, data, 1);
-        if (err < 0)
-                return err;
+        s5k83a_get_vflip(gspca_dev, &vflip);
 
-        /* set or zero seven bit, six is vflip */
-        data[0] = (val) ? (data[0] & 0x40) | 0x80 | S5K83A_FLIP_MASK
-                        : (data[0] & 0x40) | S5K83A_FLIP_MASK;
-        err = m5602_write_sensor(sd, S5K83A_FLIP, data, 1);
+        err = s5k83a_get_rotation(sd, &reg);
         if (err < 0)
                 return err;
+        if (reg) {
+                val = !val;
+                vflip = !vflip;
+        }
 
-        data[0] = (val) ? 0x0a : 0x0b;
-        err = m5602_write_sensor(sd, S5K83A_HFLIP_TUNE, data, 1);
-
+        err = s5k83a_set_flip_real(gspca_dev, vflip, val);
         return err;
 }
 
-int s5k83a_set_led_indication(struct sd *sd, u8 val)
+static int s5k83a_set_led_indication(struct sd *sd, u8 val)
 {
         int err = 0;
         u8 data[1];
@@ -454,5 +545,55 @@ int s5k83a_set_led_indication(struct sd *sd, u8 val)
 
         err = m5602_write_bridge(sd, M5602_XB_GPIO_DAT, data[0]);
 
-        return (err < 0) ? err : 0;
+        return err;
+}
+
+/* Get camera rotation on Acer notebooks */
+static int s5k83a_get_rotation(struct sd *sd, u8 *reg_data)
+{
+        int err = m5602_read_bridge(sd, M5602_XB_GPIO_DAT, reg_data);
+        *reg_data = (*reg_data & S5K83A_GPIO_ROTATION_MASK) ? 0 : 1;
+        return err;
+}
+
+static void s5k83a_dump_registers(struct sd *sd)
+{
+        int address;
+        u8 page, old_page;
+        m5602_read_sensor(sd, S5K83A_PAGE_MAP, &old_page, 1);
+
+        for (page = 0; page < 16; page++) {
+                m5602_write_sensor(sd, S5K83A_PAGE_MAP, &page, 1);
+                info("Dumping the s5k83a register state for page 0x%x", page);
+                for (address = 0; address <= 0xff; address++) {
+                        u8 val = 0;
+                        m5602_read_sensor(sd, address, &val, 1);
+                        info("register 0x%x contains 0x%x",
+                             address, val);
+                }
+        }
+        info("s5k83a register state dump complete");
+
+        for (page = 0; page < 16; page++) {
+                m5602_write_sensor(sd, S5K83A_PAGE_MAP, &page, 1);
+                info("Probing for which registers that are read/write "
+                                "for page 0x%x", page);
+                for (address = 0; address <= 0xff; address++) {
+                        u8 old_val, ctrl_val, test_val = 0xff;
+
+                        m5602_read_sensor(sd, address, &old_val, 1);
+                        m5602_write_sensor(sd, address, &test_val, 1);
+                        m5602_read_sensor(sd, address, &ctrl_val, 1);
+
+                        if (ctrl_val == test_val)
+                                info("register 0x%x is writeable", address);
+                        else
+                                info("register 0x%x is read only", address);
+
+                        /* Restore original val */
+                        m5602_write_sensor(sd, address, &old_val, 1);
+                }
+        }
+        info("Read/write register probing complete");
+        m5602_write_sensor(sd, S5K83A_PAGE_MAP, &old_page, 1);
 }
diff --git a/drivers/media/video/gspca/m5602/m5602_s5k83a.h b/drivers/media/video/gspca/m5602/m5602_s5k83a.h
index 819ab25272be..7814b078acde 100644
--- a/drivers/media/video/gspca/m5602/m5602_s5k83a.h
+++ b/drivers/media/video/gspca/m5602/m5602_s5k83a.h
@@ -21,20 +21,21 @@
 
 #include "m5602_sensor.h"
 
-#define S5K83A_FLIP                             0x01
-#define S5K83A_HFLIP_TUNE                       0x03
-#define S5K83A_VFLIP_TUNE                       0x05
-#define S5K83A_WHITENESS                        0x0a
-#define S5K83A_GAIN                             0x18
-#define S5K83A_BRIGHTNESS                       0x1b
-#define S5K83A_PAGE_MAP                         0xec
-
-#define S5K83A_DEFAULT_BRIGHTNESS               0x71
-#define S5K83A_DEFAULT_WHITENESS                0x7e
-#define S5K83A_DEFAULT_GAIN                     0x00
-#define S5K83A_MAXIMUM_GAIN                     0x3c
-#define S5K83A_FLIP_MASK                        0x10
+#define S5K83A_FLIP                     0x01
+#define S5K83A_HFLIP_TUNE               0x03
+#define S5K83A_VFLIP_TUNE               0x05
+#define S5K83A_BRIGHTNESS               0x0a
+#define S5K83A_EXPOSURE                 0x18
+#define S5K83A_GAIN                     0x1b
+#define S5K83A_PAGE_MAP                 0xec
+
+#define S5K83A_DEFAULT_GAIN             0x71
+#define S5K83A_DEFAULT_BRIGHTNESS       0x7e
+#define S5K83A_DEFAULT_EXPOSURE         0x00
+#define S5K83A_MAXIMUM_EXPOSURE         0x3c
+#define S5K83A_FLIP_MASK                0x10
 #define S5K83A_GPIO_LED_MASK            0x10
+#define S5K83A_GPIO_ROTATION_MASK       0x40
 
 /*****************************************************************************/
 
@@ -46,20 +47,7 @@ int s5k83a_probe(struct sd *sd);
 int s5k83a_init(struct sd *sd);
 int s5k83a_start(struct sd *sd);
 int s5k83a_stop(struct sd *sd);
-int s5k83a_power_down(struct sd *sd);
-
-int s5k83a_set_led_indication(struct sd *sd, u8 val);
-
-int s5k83a_set_brightness(struct gspca_dev *gspca_dev, __s32 val);
-int s5k83a_get_brightness(struct gspca_dev *gspca_dev, __s32 *val);
-int s5k83a_set_whiteness(struct gspca_dev *gspca_dev, __s32 val);
-int s5k83a_get_whiteness(struct gspca_dev *gspca_dev, __s32 *val);
-int s5k83a_set_gain(struct gspca_dev *gspca_dev, __s32 val);
-int s5k83a_get_gain(struct gspca_dev *gspca_dev, __s32 *val);
-int s5k83a_get_vflip(struct gspca_dev *gspca_dev, __s32 *val);
-int s5k83a_set_vflip(struct gspca_dev *gspca_dev, __s32 val);
-int s5k83a_get_hflip(struct gspca_dev *gspca_dev, __s32 *val);
-int s5k83a_set_hflip(struct gspca_dev *gspca_dev, __s32 val);
+void s5k83a_disconnect(struct sd *sd);
 
 static const struct m5602_sensor s5k83a = {
         .name = "S5K83A",
@@ -67,11 +55,18 @@ static const struct m5602_sensor s5k83a = {
         .init = s5k83a_init,
         .start = s5k83a_start,
         .stop = s5k83a_stop,
-        .power_down = s5k83a_power_down,
+        .disconnect = s5k83a_disconnect,
         .i2c_slave_id = 0x5a,
         .i2c_regW = 2,
 };
 
+struct s5k83a_priv {
+        /* We use another thread periodically
+           probing the orientation of the camera */
+        struct task_struct *rotation_thread;
+        s32 *settings;
+};
+
 static const unsigned char preinit_s5k83a[][4] =
 {
         {BRIDGE, M5602_XB_MCU_CLK_DIV, 0x02, 0x00},
@@ -108,8 +103,6 @@ static const unsigned char preinit_s5k83a[][4] =
         {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00, 0x00},
         {BRIDGE, M5602_XB_GPIO_EN_L, 0x00, 0x00},
         {BRIDGE, M5602_XB_I2C_CLK_DIV, 0x20, 0x00},
-
-        {SENSOR, S5K83A_PAGE_MAP, 0x00, 0x00}
 };
 
 /* This could probably be considerably shortened.
@@ -117,86 +110,8 @@ static const unsigned char preinit_s5k83a[][4] =
 */
 static const unsigned char init_s5k83a[][4] =
 {
-        {SENSOR, S5K83A_PAGE_MAP, 0x04, 0x00},
-        {SENSOR, 0xaf, 0x01, 0x00},
-        {SENSOR, S5K83A_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, 0x7b, 0xff, 0x00},
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
-        {SENSOR, 0x01, 0x50, 0x00},
-        {SENSOR, 0x12, 0x20, 0x00},
-        {SENSOR, 0x17, 0x40, 0x00},
-        {SENSOR, S5K83A_BRIGHTNESS, 0x0f, 0x00},
-        {SENSOR, 0x1c, 0x00, 0x00},
-        {SENSOR, 0x02, 0x70, 0x00},
-        {SENSOR, 0x03, 0x0b, 0x00},
-        {SENSOR, 0x04, 0xf0, 0x00},
-        {SENSOR, 0x05, 0x0b, 0x00},
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
-
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81, 0x00},
-        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0xe4, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x87, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
-        {SENSOR, 0x06, 0x71, 0x00},
-        {SENSOR, 0x07, 0xe8, 0x00},
-        {SENSOR, 0x08, 0x02, 0x00},
-        {SENSOR, 0x09, 0x88, 0x00},
-        {SENSOR, 0x14, 0x00, 0x00},
-        {SENSOR, 0x15, 0x20, 0x00},
-        {SENSOR, 0x19, 0x00, 0x00},
-        {SENSOR, 0x1a, 0x98, 0x00},
-        {SENSOR, 0x0f, 0x02, 0x00},
-        {SENSOR, 0x10, 0xe5, 0x00},
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
-        {SENSOR_LONG, 0x14, 0x00, 0x20},
-        {SENSOR_LONG, 0x0d, 0x00, 0x7d},
-        {SENSOR_LONG, 0x1b, 0x0d, 0x05},
-
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81, 0x00},
-        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0xe4, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x87, 0x00},
-
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
+        /* The following sequence is useless after a clean boot
+           but is necessary after resume from suspend */
         {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00},
         {BRIDGE, M5602_XB_GPIO_DAT, 0x08, 0x00},
         {BRIDGE, M5602_XB_GPIO_EN_H, 0x3f, 0x00},
@@ -216,7 +131,7 @@ static const unsigned char init_s5k83a[][4] =
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xf0, 0x00},
         {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x1c, 0x00},
+        {BRIDGE, M5602_XB_GPIO_DAT, 0x08, 0x00},
         {BRIDGE, M5602_XB_GPIO_EN_H, 0x06, 0x00},
         {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06, 0x00},
         {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00, 0x00},
@@ -225,109 +140,34 @@ static const unsigned char init_s5k83a[][4] =
 
         {SENSOR, S5K83A_PAGE_MAP, 0x04, 0x00},
         {SENSOR, 0xaf, 0x01, 0x00},
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
-        /* ff ( init value )is very dark) || 71 and f0 better */
+        {SENSOR, S5K83A_PAGE_MAP, 0x00, 0x00},
         {SENSOR, 0x7b, 0xff, 0x00},
         {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
         {SENSOR, 0x01, 0x50, 0x00},
         {SENSOR, 0x12, 0x20, 0x00},
         {SENSOR, 0x17, 0x40, 0x00},
-        {SENSOR, S5K83A_BRIGHTNESS, 0x0f, 0x00},
         {SENSOR, 0x1c, 0x00, 0x00},
         {SENSOR, 0x02, 0x70, 0x00},
-        /* some values like 0x10 give a blue-purple image */
         {SENSOR, 0x03, 0x0b, 0x00},
         {SENSOR, 0x04, 0xf0, 0x00},
         {SENSOR, 0x05, 0x0b, 0x00},
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
-
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
-        /* under 80 don't work, highter depend on value */
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_LINE_OF_FRAME_H, 0x81, 0x00},
-        {BRIDGE, M5602_XB_PIX_OF_LINE_H, 0x82, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0xe4, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SIG_INI, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x7f, 0x00},
-
-        {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
         {SENSOR, 0x06, 0x71, 0x00},
-        {SENSOR, 0x07, 0xe8, 0x00},
+        {SENSOR, 0x07, 0xe8, 0x00}, /* 488 */
         {SENSOR, 0x08, 0x02, 0x00},
-        {SENSOR, 0x09, 0x88, 0x00},
+        {SENSOR, 0x09, 0x88, 0x00}, /* 648 */
         {SENSOR, 0x14, 0x00, 0x00},
-        {SENSOR, 0x15, 0x20, 0x00},
+        {SENSOR, 0x15, 0x20, 0x00}, /* 32 */
         {SENSOR, 0x19, 0x00, 0x00},
-        {SENSOR, 0x1a, 0x98, 0x00},
+        {SENSOR, 0x1a, 0x98, 0x00}, /* 152 */
         {SENSOR, 0x0f, 0x02, 0x00},
-        {SENSOR, 0x10, 0xe5, 0x00},
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
-        {SENSOR_LONG, 0x14, 0x00, 0x20},
-        {SENSOR_LONG, 0x0d, 0x00, 0x7d},
-        {SENSOR_LONG, 0x1b, 0x0d, 0x05},
-
-        /* The following sequence is useless after a clean boot
-           but is necessary after resume from suspend */
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x08, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x3f, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x3f, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0xff, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR_L, 0xff, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT_L, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0x80, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
-        {BRIDGE, M5602_XB_SENSOR_TYPE, 0x09, 0x00},
-        {BRIDGE, M5602_XB_MCU_CLK_DIV, 0x02, 0x00},
-        {BRIDGE, M5602_XB_MCU_CLK_CTRL, 0xb0, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
-        {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xf0, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR, 0x1d, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT, 0x08, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_H, 0x06, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DIR_H, 0x06, 0x00},
-        {BRIDGE, M5602_XB_GPIO_DAT_H, 0x00, 0x00},
-        {BRIDGE, M5602_XB_GPIO_EN_L, 0x00, 0x00},
-        {BRIDGE, M5602_XB_I2C_CLK_DIV, 0x20, 0x00},
-
-        {SENSOR, S5K83A_PAGE_MAP, 0x04, 0x00},
-        {SENSOR, 0xaf, 0x01, 0x00},
-        {SENSOR, S5K83A_PAGE_MAP, 0x00, 0x00},
-        {SENSOR, 0x7b, 0xff, 0x00},
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
-        {SENSOR, 0x01, 0x50, 0x00},
-        {SENSOR, 0x12, 0x20, 0x00},
-        {SENSOR, 0x17, 0x40, 0x00},
-        {SENSOR, S5K83A_BRIGHTNESS, 0x0f, 0x00},
-        {SENSOR, 0x1c, 0x00, 0x00},
-        {SENSOR, 0x02, 0x70, 0x00},
-        {SENSOR, 0x03, 0x0b, 0x00},
-        {SENSOR, 0x04, 0xf0, 0x00},
-        {SENSOR, 0x05, 0x0b, 0x00},
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
+        {SENSOR, 0x10, 0xe5, 0x00}, /* 741 */
+        /* normal colors
+        (this is value after boot, but after tries can be different) */
+        {SENSOR, 0x00, 0x06, 0x00},
+};
 
+static const unsigned char start_s5k83a[][4] =
+{
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x06, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
         {BRIDGE, M5602_XB_ADC_CTRL, 0xc0, 0x00},
@@ -340,7 +180,7 @@ static const unsigned char init_s5k83a[][4] =
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x01, 0x00},
-        {BRIDGE, M5602_XB_VSYNC_PARA, 0xe4, 0x00},
+        {BRIDGE, M5602_XB_VSYNC_PARA, 0xe4, 0x00}, /* 484 */
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_VSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
@@ -348,50 +188,10 @@ static const unsigned char init_s5k83a[][4] =
         {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_HSYNC_PARA, 0x00, 0x00},
         {BRIDGE, M5602_XB_HSYNC_PARA, 0x02, 0x00},
-        {BRIDGE, M5602_XB_HSYNC_PARA, 0x7f, 0x00},
+        {BRIDGE, M5602_XB_HSYNC_PARA, 0x7f, 0x00}, /* 639 */
         {BRIDGE, M5602_XB_SIG_INI, 0x00, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00, 0x00},
         {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0, 0x00},
-
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
-        {SENSOR, 0x06, 0x71, 0x00},
-        {SENSOR, 0x07, 0xe8, 0x00},
-        {SENSOR, 0x08, 0x02, 0x00},
-        {SENSOR, 0x09, 0x88, 0x00},
-        {SENSOR, 0x14, 0x00, 0x00},
-        {SENSOR, 0x15, 0x20, 0x00},
-        {SENSOR, 0x19, 0x00, 0x00},
-        {SENSOR, 0x1a, 0x98, 0x00},
-        {SENSOR, 0x0f, 0x02, 0x00},
-
-        {SENSOR, 0x10, 0xe5, 0x00},
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
-        {SENSOR_LONG, 0x14, 0x00, 0x20},
-        {SENSOR_LONG, 0x0d, 0x00, 0x7d},
-        {SENSOR_LONG, 0x1b, 0x0d, 0x05},
-
-        /* normal colors
-           (this is value after boot, but after tries can be different) */
-        {SENSOR, 0x00, 0x06, 0x00},
-
-        /* set default brightness */
-        {SENSOR_LONG, 0x14, 0x00, 0x20},
-        {SENSOR_LONG, 0x0d, 0x01, 0x00},
-        {SENSOR_LONG, 0x1b, S5K83A_DEFAULT_BRIGHTNESS >> 3,
-                            S5K83A_DEFAULT_BRIGHTNESS >> 1},
-
-        /* set default whiteness */
-        {SENSOR, S5K83A_WHITENESS, S5K83A_DEFAULT_WHITENESS, 0x00},
-
-        /* set default gain */
-        {SENSOR_LONG, 0x18, 0x00, S5K83A_DEFAULT_GAIN},
-
-        /* set default flip */
-        {SENSOR, S5K83A_PAGE_MAP, 0x05, 0x00},
-        {SENSOR, S5K83A_FLIP, 0x00 | S5K83A_FLIP_MASK, 0x00},
-        {SENSOR, S5K83A_HFLIP_TUNE, 0x0b, 0x00},
-        {SENSOR, S5K83A_VFLIP_TUNE, 0x0a, 0x00}
-
 };
 
 #endif
diff --git a/drivers/media/video/gspca/m5602/m5602_sensor.h b/drivers/media/video/gspca/m5602/m5602_sensor.h
index 0d3026936f2e..edff4f1f586f 100644
--- a/drivers/media/video/gspca/m5602/m5602_sensor.h
+++ b/drivers/media/video/gspca/m5602/m5602_sensor.h
@@ -21,13 +21,17 @@
 
 #include "m5602_bridge.h"
 
+#define M5602_V4L2_CID_GREEN_BALANCE    (V4L2_CID_PRIVATE_BASE + 0)
+#define M5602_V4L2_CID_NOISE_SUPPRESION (V4L2_CID_PRIVATE_BASE + 1)
+
 /* Enumerates all supported sensors */
 enum sensors {
         OV9650_SENSOR   = 1,
         S5K83A_SENSOR   = 2,
         S5K4AA_SENSOR   = 3,
         MT9M111_SENSOR  = 4,
-        PO1030_SENSOR   = 5
+        PO1030_SENSOR   = 5,
+        OV7660_SENSOR   = 6,
 };
 
 /* Enumerates all possible instruction types */
@@ -61,9 +65,6 @@ struct m5602_sensor {
 
         /* Executed when the device is disconnected */
         void (*disconnect)(struct sd *sd);
-
-        /* Performs a power down sequence */
-        int (*power_down)(struct sd *sd);
 };
 
 #endif
diff --git a/drivers/media/video/gspca/mr97310a.c b/drivers/media/video/gspca/mr97310a.c
index 2a901a4a6f00..30132513400c 100644
--- a/drivers/media/video/gspca/mr97310a.c
+++ b/drivers/media/video/gspca/mr97310a.c
@@ -321,6 +321,7 @@ static const struct sd_desc sd_desc = {
 /* -- module initialisation -- */
 static const __devinitdata struct usb_device_id device_table[] = {
         {USB_DEVICE(0x08ca, 0x0111)},
+        {USB_DEVICE(0x093a, 0x010f)},
         {}
 };
 MODULE_DEVICE_TABLE(usb, device_table);
@@ -347,8 +348,11 @@ static struct usb_driver sd_driver = {
 /* -- module insert / remove -- */
 static int __init sd_mod_init(void)
 {
-        if (usb_register(&sd_driver) < 0)
-                return -1;
+        int ret;
+
+        ret = usb_register(&sd_driver);
+        if (ret < 0)
+                return ret;
         PDEBUG(D_PROBE, "registered");
         return 0;
 }
diff --git a/drivers/media/video/gspca/ov519.c b/drivers/media/video/gspca/ov519.c
index 1fff37b79891..188866ac6cef 100644
--- a/drivers/media/video/gspca/ov519.c
+++ b/drivers/media/video/gspca/ov519.c
@@ -50,6 +50,13 @@ static int i2c_detect_tries = 10;
 struct sd {
         struct gspca_dev gspca_dev;             /* !! must be the first item */
 
+        char bridge;
+#define BRIDGE_OV511            0
+#define BRIDGE_OV511PLUS        1
+#define BRIDGE_OV518            2
+#define BRIDGE_OV518PLUS        3
+#define BRIDGE_OV519            4
+
         /* Determined by sensor type */
         __u8 sif;
 
@@ -87,6 +94,9 @@ static int sd_sethflip(struct gspca_dev *gspca_dev, __s32 val);
 static int sd_gethflip(struct gspca_dev *gspca_dev, __s32 *val);
 static int sd_setvflip(struct gspca_dev *gspca_dev, __s32 val);
 static int sd_getvflip(struct gspca_dev *gspca_dev, __s32 *val);
+static void setbrightness(struct gspca_dev *gspca_dev);
+static void setcontrast(struct gspca_dev *gspca_dev);
+static void setcolors(struct gspca_dev *gspca_dev);
 
 static struct ctrl sd_ctrls[] = {
         {
@@ -164,7 +174,7 @@ static struct ctrl sd_ctrls[] = {
         },
 };
 
-static const struct v4l2_pix_format vga_mode[] = {
+static const struct v4l2_pix_format ov519_vga_mode[] = {
         {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
                 .bytesperline = 320,
                 .sizeimage = 320 * 240 * 3 / 8 + 590,
@@ -176,7 +186,7 @@ static const struct v4l2_pix_format vga_mode[] = {
                 .colorspace = V4L2_COLORSPACE_JPEG,
                 .priv = 0},
 };
-static const struct v4l2_pix_format sif_mode[] = {
+static const struct v4l2_pix_format ov519_sif_mode[] = {
         {176, 144, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
                 .bytesperline = 176,
                 .sizeimage = 176 * 144 * 3 / 8 + 590,
@@ -189,6 +199,47 @@ static const struct v4l2_pix_format sif_mode[] = {
                 .priv = 0},
 };
 
+static const struct v4l2_pix_format ov518_vga_mode[] = {
+        {320, 240, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
+                .bytesperline = 320,
+                .sizeimage = 320 * 240 * 3 / 8 + 590,
+                .colorspace = V4L2_COLORSPACE_JPEG,
+                .priv = 1},
+        {640, 480, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
+                .bytesperline = 640,
+                .sizeimage = 640 * 480 * 3 / 8 + 590,
+                .colorspace = V4L2_COLORSPACE_JPEG,
+                .priv = 0},
+};
+static const struct v4l2_pix_format ov518_sif_mode[] = {
+        {176, 144, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
+                .bytesperline = 176,
+                .sizeimage = 40000,
+                .colorspace = V4L2_COLORSPACE_JPEG,
+                .priv = 1},
+        {352, 288, V4L2_PIX_FMT_OV518, V4L2_FIELD_NONE,
+                .bytesperline = 352,
+                .sizeimage = 352 * 288 * 3 / 8 + 590,
+                .colorspace = V4L2_COLORSPACE_JPEG,
+                .priv = 0},
+};
+
+
+/* Registers common to OV511 / OV518 */
+#define R51x_SYS_RESET                  0x50
+#define R51x_SYS_INIT                   0x53
+#define R51x_SYS_SNAP                   0x52
+#define R51x_SYS_CUST_ID                0x5F
+#define R51x_COMP_LUT_BEGIN             0x80
+
+/* OV511 Camera interface register numbers */
+#define R511_SYS_LED_CTL                0x55    /* OV511+ only */
+#define OV511_RESET_NOREGS              0x3F    /* All but OV511 & regs */
+
+/* OV518 Camera interface register numbers */
+#define R518_GPIO_OUT                   0x56    /* OV518(+) only */
+#define R518_GPIO_CTL                   0x57    /* OV518(+) only */
+
 /* OV519 Camera interface register numbers */
 #define OV519_R10_H_SIZE                0x10
 #define OV519_R11_V_SIZE                0x11
@@ -224,6 +275,8 @@ static const struct v4l2_pix_format sif_mode[] = {
 
 /* OV7610 registers */
 #define OV7610_REG_GAIN         0x00    /* gain setting (5:0) */
+#define OV7610_REG_BLUE         0x01    /* blue channel balance */
+#define OV7610_REG_RED          0x02    /* red channel balance */
 #define OV7610_REG_SAT          0x03    /* saturation */
 #define OV8610_REG_HUE          0x04    /* 04 reserved */
 #define OV7610_REG_CNT          0x05    /* Y contrast */
@@ -846,11 +899,12 @@ static unsigned char ov7670_abs_to_sm(unsigned char v)
 static int reg_w(struct sd *sd, __u16 index, __u8 value)
 {
         int ret;
+        int req = (sd->bridge <= BRIDGE_OV511PLUS) ? 2 : 1;
 
         sd->gspca_dev.usb_buf[0] = value;
         ret = usb_control_msg(sd->gspca_dev.dev,
                         usb_sndctrlpipe(sd->gspca_dev.dev, 0),
-                        1,                      /* REQ_IO (ov518/519) */
+                        req,
                         USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
                         0, index,
                         sd->gspca_dev.usb_buf, 1, 500);
@@ -864,10 +918,11 @@ static int reg_w(struct sd *sd, __u16 index, __u8 value)
 static int reg_r(struct sd *sd, __u16 index)
 {
         int ret;
+        int req = (sd->bridge <= BRIDGE_OV511PLUS) ? 3 : 1;
 
         ret = usb_control_msg(sd->gspca_dev.dev,
                         usb_rcvctrlpipe(sd->gspca_dev.dev, 0),
-                        1,                      /* REQ_IO */
+                        req,
                         USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
                         0, index, sd->gspca_dev.usb_buf, 1, 500);
 
@@ -924,6 +979,28 @@ static int reg_w_mask(struct sd *sd,
 }
 
 /*
+ * Writes multiple (n) byte value to a single register. Only valid with certain
+ * registers (0x30 and 0xc4 - 0xce).
+ */
+static int ov518_reg_w32(struct sd *sd, __u16 index, u32 value, int n)
+{
+        int ret;
+
+        *((u32 *)sd->gspca_dev.usb_buf) = __cpu_to_le32(value);
+
+        ret = usb_control_msg(sd->gspca_dev.dev,
+                        usb_sndctrlpipe(sd->gspca_dev.dev, 0),
+                        1 /* REG_IO */,
+                        USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+                        0, index,
+                        sd->gspca_dev.usb_buf, n, 500);
+        if (ret < 0)
+                PDEBUG(D_ERR, "Write reg32 [%02x] %08x failed", index, value);
+        return ret;
+}
+
+
+/*
  * The OV518 I2C I/O procedure is different, hence, this function.
  * This is normally only called from i2c_w(). Note that this function
  * always succeeds regardless of whether the sensor is present and working.
@@ -1014,20 +1091,47 @@ static inline int ov51x_stop(struct sd *sd)
 {
         PDEBUG(D_STREAM, "stopping");
         sd->stopped = 1;
-        return reg_w(sd, OV519_SYS_RESET1, 0x0f);
+        switch (sd->bridge) {
+        case BRIDGE_OV511:
+        case BRIDGE_OV511PLUS:
+                return reg_w(sd, R51x_SYS_RESET, 0x3d);
+        case BRIDGE_OV518:
+        case BRIDGE_OV518PLUS:
+                return reg_w_mask(sd, R51x_SYS_RESET, 0x3a, 0x3a);
+        case BRIDGE_OV519:
+                return reg_w(sd, OV519_SYS_RESET1, 0x0f);
+        }
+
+        return 0;
 }
 
 /* Restarts OV511 after ov511_stop() is called. Has no effect if it is not
  * actually stopped (for performance). */
 static inline int ov51x_restart(struct sd *sd)
 {
+        int rc;
+
         PDEBUG(D_STREAM, "restarting");
         if (!sd->stopped)
                 return 0;
         sd->stopped = 0;
 
         /* Reinitialize the stream */
-        return reg_w(sd, OV519_SYS_RESET1, 0x00);
+        switch (sd->bridge) {
+        case BRIDGE_OV511:
+        case BRIDGE_OV511PLUS:
+                return reg_w(sd, R51x_SYS_RESET, 0x00);
+        case BRIDGE_OV518:
+        case BRIDGE_OV518PLUS:
+                rc = reg_w(sd, 0x2f, 0x80);
+                if (rc < 0)
+                        return rc;
+                return reg_w(sd, R51x_SYS_RESET, 0x00);
+        case BRIDGE_OV519:
+                return reg_w(sd, OV519_SYS_RESET1, 0x00);
+        }
+
+        return 0;
 }
 
 /* This does an initial reset of an OmniVision sensor and ensures that I2C
@@ -1287,16 +1391,161 @@ static int ov6xx0_configure(struct sd *sd)
 /* Turns on or off the LED. Only has an effect with OV511+/OV518(+)/OV519 */
 static void ov51x_led_control(struct sd *sd, int on)
 {
-        reg_w_mask(sd, OV519_GPIO_DATA_OUT0, !on, 1);   /* 0 / 1 */
+        switch (sd->bridge) {
+        /* OV511 has no LED control */
+        case BRIDGE_OV511PLUS:
+                reg_w(sd, R511_SYS_LED_CTL, on ? 1 : 0);
+                break;
+        case BRIDGE_OV518:
+        case BRIDGE_OV518PLUS:
+                reg_w_mask(sd, R518_GPIO_OUT, on ? 0x02 : 0x00, 0x02);
+                break;
+        case BRIDGE_OV519:
+                reg_w_mask(sd, OV519_GPIO_DATA_OUT0, !on, 1);   /* 0 / 1 */
+                break;
+        }
 }
 
-/* this function is called at probe time */
-static int sd_config(struct gspca_dev *gspca_dev,
-                        const struct usb_device_id *id)
+/* OV518 quantization tables are 8x4 (instead of 8x8) */
+static int ov518_upload_quan_tables(struct sd *sd)
+{
+        const unsigned char yQuanTable518[] = {
+                5, 4, 5, 6, 6, 7, 7, 7,
+                5, 5, 5, 5, 6, 7, 7, 7,
+                6, 6, 6, 6, 7, 7, 7, 8,
+                7, 7, 6, 7, 7, 7, 8, 8
+        };
+
+        const unsigned char uvQuanTable518[] = {
+                6, 6, 6, 7, 7, 7, 7, 7,
+                6, 6, 6, 7, 7, 7, 7, 7,
+                6, 6, 6, 7, 7, 7, 7, 8,
+                7, 7, 7, 7, 7, 7, 8, 8
+        };
+
+        const unsigned char *pYTable = yQuanTable518;
+        const unsigned char *pUVTable = uvQuanTable518;
+        unsigned char val0, val1;
+        int i, rc, reg = R51x_COMP_LUT_BEGIN;
+
+        PDEBUG(D_PROBE, "Uploading quantization tables");
+
+        for (i = 0; i < 16; i++) {
+                val0 = *pYTable++;
+                val1 = *pYTable++;
+                val0 &= 0x0f;
+                val1 &= 0x0f;
+                val0 |= val1 << 4;
+                rc = reg_w(sd, reg, val0);
+                if (rc < 0)
+                        return rc;
+
+                val0 = *pUVTable++;
+                val1 = *pUVTable++;
+                val0 &= 0x0f;
+                val1 &= 0x0f;
+                val0 |= val1 << 4;
+                rc = reg_w(sd, reg + 16, val0);
+                if (rc < 0)
+                        return rc;
+
+                reg++;
+        }
+
+        return 0;
+}
+
+/* This initializes the OV518/OV518+ and the sensor */
+static int ov518_configure(struct gspca_dev *gspca_dev)
 {
         struct sd *sd = (struct sd *) gspca_dev;
-        struct cam *cam;
+        int rc;
+
+        /* For 518 and 518+ */
+        static struct ov_regvals init_518[] = {
+                { R51x_SYS_RESET,       0x40 },
+                { R51x_SYS_INIT,        0xe1 },
+                { R51x_SYS_RESET,       0x3e },
+                { R51x_SYS_INIT,        0xe1 },
+                { R51x_SYS_RESET,       0x00 },
+                { R51x_SYS_INIT,        0xe1 },
+                { 0x46,                 0x00 },
+                { 0x5d,                 0x03 },
+        };
+
+        static struct ov_regvals norm_518[] = {
+                { R51x_SYS_SNAP,        0x02 }, /* Reset */
+                { R51x_SYS_SNAP,        0x01 }, /* Enable */
+                { 0x31,                 0x0f },
+                { 0x5d,                 0x03 },
+                { 0x24,                 0x9f },
+                { 0x25,                 0x90 },
+                { 0x20,                 0x00 },
+                { 0x51,                 0x04 },
+                { 0x71,                 0x19 },
+                { 0x2f,                 0x80 },
+        };
+
+        static struct ov_regvals norm_518_p[] = {
+                { R51x_SYS_SNAP,        0x02 }, /* Reset */
+                { R51x_SYS_SNAP,        0x01 }, /* Enable */
+                { 0x31,                 0x0f },
+                { 0x5d,                 0x03 },
+                { 0x24,                 0x9f },
+                { 0x25,                 0x90 },
+                { 0x20,                 0x60 },
+                { 0x51,                 0x02 },
+                { 0x71,                 0x19 },
+                { 0x40,                 0xff },
+                { 0x41,                 0x42 },
+                { 0x46,                 0x00 },
+                { 0x33,                 0x04 },
+                { 0x21,                 0x19 },
+                { 0x3f,                 0x10 },
+                { 0x2f,                 0x80 },
+        };
+
+        /* First 5 bits of custom ID reg are a revision ID on OV518 */
+        PDEBUG(D_PROBE, "Device revision %d",
+               0x1F & reg_r(sd, R51x_SYS_CUST_ID));
+
+        rc = write_regvals(sd, init_518, ARRAY_SIZE(init_518));
+        if (rc < 0)
+                return rc;
+
+        /* Set LED GPIO pin to output mode */
+        rc = reg_w_mask(sd, R518_GPIO_CTL, 0x00, 0x02);
+        if (rc < 0)
+                return rc;
 
+        switch (sd->bridge) {
+        case BRIDGE_OV518:
+                rc = write_regvals(sd, norm_518, ARRAY_SIZE(norm_518));
+                if (rc < 0)
+                        return rc;
+                break;
+        case BRIDGE_OV518PLUS:
+                rc = write_regvals(sd, norm_518_p, ARRAY_SIZE(norm_518_p));
+                if (rc < 0)
+                        return rc;
+                break;
+        }
+
+        rc = ov518_upload_quan_tables(sd);
+        if (rc < 0) {
+                PDEBUG(D_ERR, "Error uploading quantization tables");
+                return rc;
+        }
+
+        rc = reg_w(sd, 0x2f, 0x80);
+        if (rc < 0)
+                return rc;
+
+        return 0;
+}
+
+static int ov519_configure(struct sd *sd)
+{
         static const struct ov_regvals init_519[] = {
                 { 0x5a,  0x6d }, /* EnableSystem */
                 { 0x53,  0x9b },
@@ -1313,8 +1562,32 @@ static int sd_config(struct gspca_dev *gspca_dev,
                 /* windows reads 0x55 at this point*/
         };
 
-        if (write_regvals(sd, init_519, ARRAY_SIZE(init_519)))
+        return write_regvals(sd, init_519, ARRAY_SIZE(init_519));
+}
+
+/* this function is called at probe time */
+static int sd_config(struct gspca_dev *gspca_dev,
+                        const struct usb_device_id *id)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        struct cam *cam;
+        int ret = 0;
+
+        sd->bridge = id->driver_info;
+
+        switch (sd->bridge) {
+        case BRIDGE_OV518:
+        case BRIDGE_OV518PLUS:
+                ret = ov518_configure(gspca_dev);
+                break;
+        case BRIDGE_OV519:
+                ret = ov519_configure(sd);
+                break;
+        }
+
+        if (ret)
                 goto error;
+
         ov51x_led_control(sd, 0);       /* turn LED off */
 
         /* Test for 76xx */
@@ -1360,12 +1633,26 @@ static int sd_config(struct gspca_dev *gspca_dev,
         }
 
         cam = &gspca_dev->cam;
-        if (!sd->sif) {
-                cam->cam_mode = vga_mode;
-                cam->nmodes = ARRAY_SIZE(vga_mode);
-        } else {
-                cam->cam_mode = sif_mode;
-                cam->nmodes = ARRAY_SIZE(sif_mode);
+        switch (sd->bridge) {
+        case BRIDGE_OV518:
+        case BRIDGE_OV518PLUS:
+                if (!sd->sif) {
+                        cam->cam_mode = ov518_vga_mode;
+                        cam->nmodes = ARRAY_SIZE(ov518_vga_mode);
+                } else {
+                        cam->cam_mode = ov518_sif_mode;
+                        cam->nmodes = ARRAY_SIZE(ov518_sif_mode);
+                }
+                break;
+        case BRIDGE_OV519:
+                if (!sd->sif) {
+                        cam->cam_mode = ov519_vga_mode;
+                        cam->nmodes = ARRAY_SIZE(ov519_vga_mode);
+                } else {
+                        cam->cam_mode = ov519_sif_mode;
+                        cam->nmodes = ARRAY_SIZE(ov519_sif_mode);
+                }
+                break;
         }
         sd->brightness = BRIGHTNESS_DEF;
         sd->contrast = CONTRAST_DEF;
@@ -1422,6 +1709,106 @@ static int sd_init(struct gspca_dev *gspca_dev)
         return 0;
 }
 
+/* Sets up the OV518/OV518+ with the given image parameters
+ *
+ * OV518 needs a completely different approach, until we can figure out what
+ * the individual registers do. Also, only 15 FPS is supported now.
+ *
+ * Do not put any sensor-specific code in here (including I2C I/O functions)
+ */
+static int ov518_mode_init_regs(struct sd *sd)
+{
+        int hsegs, vsegs;
+
+        /******** Set the mode ********/
+
+        reg_w(sd, 0x2b, 0);
+        reg_w(sd, 0x2c, 0);
+        reg_w(sd, 0x2d, 0);
+        reg_w(sd, 0x2e, 0);
+        reg_w(sd, 0x3b, 0);
+        reg_w(sd, 0x3c, 0);
+        reg_w(sd, 0x3d, 0);
+        reg_w(sd, 0x3e, 0);
+
+        if (sd->bridge == BRIDGE_OV518) {
+                /* Set 8-bit (YVYU) input format */
+                reg_w_mask(sd, 0x20, 0x08, 0x08);
+
+                /* Set 12-bit (4:2:0) output format */
+                reg_w_mask(sd, 0x28, 0x80, 0xf0);
+                reg_w_mask(sd, 0x38, 0x80, 0xf0);
+        } else {
+                reg_w(sd, 0x28, 0x80);
+                reg_w(sd, 0x38, 0x80);
+        }
+
+        hsegs = sd->gspca_dev.width / 16;
+        vsegs = sd->gspca_dev.height / 4;
+
+        reg_w(sd, 0x29, hsegs);
+        reg_w(sd, 0x2a, vsegs);
+
+        reg_w(sd, 0x39, hsegs);
+        reg_w(sd, 0x3a, vsegs);
+
+        /* Windows driver does this here; who knows why */
+        reg_w(sd, 0x2f, 0x80);
+
+        /******** Set the framerate (to 30 FPS) ********/
+        if (sd->bridge == BRIDGE_OV518PLUS)
+                sd->clockdiv = 1;
+        else
+                sd->clockdiv = 0;
+
+        /* Mode independent, but framerate dependent, regs */
+        reg_w(sd, 0x51, 0x04);  /* Clock divider; lower==faster */
+        reg_w(sd, 0x22, 0x18);
+        reg_w(sd, 0x23, 0xff);
+
+        if (sd->bridge == BRIDGE_OV518PLUS)
+                reg_w(sd, 0x21, 0x19);
+        else
+                reg_w(sd, 0x71, 0x17);  /* Compression-related? */
+
+        /* FIXME: Sensor-specific */
+        /* Bit 5 is what matters here. Of course, it is "reserved" */
+        i2c_w(sd, 0x54, 0x23);
+
+        reg_w(sd, 0x2f, 0x80);
+
+        if (sd->bridge == BRIDGE_OV518PLUS) {
+                reg_w(sd, 0x24, 0x94);
+                reg_w(sd, 0x25, 0x90);
+                ov518_reg_w32(sd, 0xc4,    400, 2);     /* 190h   */
+                ov518_reg_w32(sd, 0xc6,    540, 2);     /* 21ch   */
+                ov518_reg_w32(sd, 0xc7,    540, 2);     /* 21ch   */
+                ov518_reg_w32(sd, 0xc8,    108, 2);     /* 6ch    */
+                ov518_reg_w32(sd, 0xca, 131098, 3);     /* 2001ah */
+                ov518_reg_w32(sd, 0xcb,    532, 2);     /* 214h   */
+                ov518_reg_w32(sd, 0xcc,   2400, 2);     /* 960h   */
+                ov518_reg_w32(sd, 0xcd,     32, 2);     /* 20h    */
+                ov518_reg_w32(sd, 0xce,    608, 2);     /* 260h   */
+        } else {
+                reg_w(sd, 0x24, 0x9f);
+                reg_w(sd, 0x25, 0x90);
+                ov518_reg_w32(sd, 0xc4,    400, 2);     /* 190h   */
+                ov518_reg_w32(sd, 0xc6,    381, 2);     /* 17dh   */
+                ov518_reg_w32(sd, 0xc7,    381, 2);     /* 17dh   */
+                ov518_reg_w32(sd, 0xc8,    128, 2);     /* 80h    */
+                ov518_reg_w32(sd, 0xca, 183331, 3);     /* 2cc23h */
+                ov518_reg_w32(sd, 0xcb,    746, 2);     /* 2eah   */
+                ov518_reg_w32(sd, 0xcc,   1750, 2);     /* 6d6h   */
+                ov518_reg_w32(sd, 0xcd,     45, 2);     /* 2dh    */
+                ov518_reg_w32(sd, 0xce,    851, 2);     /* 353h   */
+        }
+
+        reg_w(sd, 0x2f, 0x80);
+
+        return 0;
+}
+
+
 /* Sets up the OV519 with the given image parameters
  *
  * OV519 needs a completely different approach, until we can figure out what
@@ -1740,6 +2127,11 @@ static int set_ov_sensor_window(struct sd *sd)
                 hwebase = 0x3a;
                 vwsbase = 0x05;
                 vwebase = 0x06;
+                if (qvga) {
+                        /* HDG: this fixes U and V getting swapped */
+                        hwsbase--;
+                        vwsbase--;
+                }
                 break;
         case SEN_OV7620:
                 hwsbase = 0x2f;         /* From 7620.SET (spec is wrong) */
@@ -1855,15 +2247,28 @@ static int set_ov_sensor_window(struct sd *sd)
 static int sd_start(struct gspca_dev *gspca_dev)
 {
         struct sd *sd = (struct sd *) gspca_dev;
-        int ret;
+        int ret = 0;
 
-        ret = ov519_mode_init_regs(sd);
+        switch (sd->bridge) {
+        case BRIDGE_OV518:
+        case BRIDGE_OV518PLUS:
+                ret = ov518_mode_init_regs(sd);
+                break;
+        case BRIDGE_OV519:
+                ret = ov519_mode_init_regs(sd);
+                break;
+        }
         if (ret < 0)
                 goto out;
+
         ret = set_ov_sensor_window(sd);
         if (ret < 0)
                 goto out;
 
+        setcontrast(gspca_dev);
+        setbrightness(gspca_dev);
+        setcolors(gspca_dev);
+
         ret = ov51x_restart(sd);
         if (ret < 0)
                 goto out;
@@ -1882,7 +2287,30 @@ static void sd_stopN(struct gspca_dev *gspca_dev)
         ov51x_led_control(sd, 0);
 }
 
-static void sd_pkt_scan(struct gspca_dev *gspca_dev,
+static void ov518_pkt_scan(struct gspca_dev *gspca_dev,
+                        struct gspca_frame *frame,      /* target */
+                        __u8 *data,                     /* isoc packet */
+                        int len)                        /* iso packet length */
+{
+        PDEBUG(D_STREAM, "ov518_pkt_scan: %d bytes", len);
+
+        if (len & 7) {
+                len--;
+                PDEBUG(D_STREAM, "packet number: %d\n", (int)data[len]);
+        }
+
+        /* A false positive here is likely, until OVT gives me
+         * the definitive SOF/EOF format */
+        if ((!(data[0] | data[1] | data[2] | data[3] | data[5])) && data[6]) {
+                gspca_frame_add(gspca_dev, LAST_PACKET, frame, data, 0);
+                gspca_frame_add(gspca_dev, FIRST_PACKET, frame, data, 0);
+        }
+
+        /* intermediate packet */
+        gspca_frame_add(gspca_dev, INTER_PACKET, frame, data, len);
+}
+
+static void ov519_pkt_scan(struct gspca_dev *gspca_dev,
                         struct gspca_frame *frame,      /* target */
                         __u8 *data,                     /* isoc packet */
                         int len)                        /* iso packet length */
@@ -1926,6 +2354,27 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev,
                         data, len);
 }
 
+static void sd_pkt_scan(struct gspca_dev *gspca_dev,
+                        struct gspca_frame *frame,      /* target */
+                        __u8 *data,                     /* isoc packet */
+                        int len)                        /* iso packet length */
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+
+        switch (sd->bridge) {
+        case BRIDGE_OV511:
+        case BRIDGE_OV511PLUS:
+                break;
+        case BRIDGE_OV518:
+        case BRIDGE_OV518PLUS:
+                ov518_pkt_scan(gspca_dev, frame, data, len);
+                break;
+        case BRIDGE_OV519:
+                ov519_pkt_scan(gspca_dev, frame, data, len);
+                break;
+        }
+}
+
 /* -- management routines -- */
 
 static void setbrightness(struct gspca_dev *gspca_dev)
@@ -1970,6 +2419,7 @@ static void setcontrast(struct gspca_dev *gspca_dev)
                 break;
         case SEN_OV6630:
                 i2c_w_mask(sd, OV7610_REG_CNT, val >> 4, 0x0f);
+                break;
         case SEN_OV8610: {
                 static const __u8 ctab[] = {
                         0x03, 0x09, 0x0b, 0x0f, 0x53, 0x6f, 0x35, 0x7f
@@ -2136,19 +2586,21 @@ static const struct sd_desc sd_desc = {
 
 /* -- module initialisation -- */
 static const __devinitdata struct usb_device_id device_table[] = {
-        {USB_DEVICE(0x041e, 0x4052)},
-        {USB_DEVICE(0x041e, 0x405f)},
-        {USB_DEVICE(0x041e, 0x4060)},
-        {USB_DEVICE(0x041e, 0x4061)},
-        {USB_DEVICE(0x041e, 0x4064)},
-        {USB_DEVICE(0x041e, 0x4068)},
-        {USB_DEVICE(0x045e, 0x028c)},
-        {USB_DEVICE(0x054c, 0x0154)},
-        {USB_DEVICE(0x054c, 0x0155)},
-        {USB_DEVICE(0x05a9, 0x0519)},
-        {USB_DEVICE(0x05a9, 0x0530)},
-        {USB_DEVICE(0x05a9, 0x4519)},
-        {USB_DEVICE(0x05a9, 0x8519)},
+        {USB_DEVICE(0x041e, 0x4052), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x041e, 0x405f), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x041e, 0x4060), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x041e, 0x4061), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x041e, 0x4064), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x041e, 0x4068), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x045e, 0x028c), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x054c, 0x0154), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x054c, 0x0155), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x05a9, 0x0518), .driver_info = BRIDGE_OV518 },
+        {USB_DEVICE(0x05a9, 0x0519), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x05a9, 0x0530), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x05a9, 0x4519), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x05a9, 0x8519), .driver_info = BRIDGE_OV519 },
+        {USB_DEVICE(0x05a9, 0xa518), .driver_info = BRIDGE_OV518PLUS },
         {}
 };
 
diff --git a/drivers/media/video/gspca/ov534.c b/drivers/media/video/gspca/ov534.c
index 19e0bc60de14..4b528b372911 100644
--- a/drivers/media/video/gspca/ov534.c
+++ b/drivers/media/video/gspca/ov534.c
@@ -60,10 +60,23 @@ struct sd {
 static struct ctrl sd_ctrls[] = {
 };
 
-static const struct v4l2_pix_format vga_mode[] = {
+static const struct v4l2_pix_format vga_yuyv_mode[] = {
         {640, 480, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
          .bytesperline = 640 * 2,
          .sizeimage = 640 * 480 * 2,
+         .colorspace = V4L2_COLORSPACE_SRGB,
+         .priv = 0},
+};
+
+static const struct v4l2_pix_format vga_jpeg_mode[] = {
+        {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
+         .bytesperline = 320,
+         .sizeimage = 320 * 240 * 3 / 8 + 590,
+         .colorspace = V4L2_COLORSPACE_JPEG,
+         .priv = 1},
+        {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
+         .bytesperline = 640,
+         .sizeimage = 640 * 480 * 3 / 8 + 590,
          .colorspace = V4L2_COLORSPACE_JPEG,
          .priv = 0},
 };
@@ -244,7 +257,7 @@ static const u8 bridge_init_ov965x[][2] = {
 };
 
 static const u8 sensor_init_ov965x[][2] = {
-        {0x12, 0x80},   /* com7 - reset */
+        {0x12, 0x80},   /* com7 - SSCB reset */
         {0x00, 0x00},   /* gain */
         {0x01, 0x80},   /* blue */
         {0x02, 0x80},   /* red */
@@ -254,10 +267,10 @@ static const u8 sensor_init_ov965x[][2] = {
         {0x0e, 0x61},   /* com5 */
         {0x0f, 0x42},   /* com6 */
         {0x11, 0x00},   /* clkrc */
-        {0x12, 0x02},   /* com7 */
+        {0x12, 0x02},   /* com7 - 15fps VGA YUYV */
         {0x13, 0xe7},   /* com8 - everything (AGC, AWB and AEC) */
         {0x14, 0x28},   /* com9 */
-        {0x16, 0x24},   /* rsvd16 */
+        {0x16, 0x24},   /* reg16 */
         {0x17, 0x1d},   /* hstart*/
         {0x18, 0xbd},   /* hstop */
         {0x19, 0x01},   /* vstrt */
@@ -269,24 +282,24 @@ static const u8 sensor_init_ov965x[][2] = {
         {0x27, 0x08},   /* bbias */
         {0x28, 0x08},   /* gbbias */
         {0x29, 0x15},   /* gr com */
-        {0x2a, 0x00},
-        {0x2b, 0x00},
+        {0x2a, 0x00},   /* exhch */
+        {0x2b, 0x00},   /* exhcl */
         {0x2c, 0x08},   /* rbias */
         {0x32, 0xff},   /* href */
         {0x33, 0x00},   /* chlf */
-        {0x34, 0x3f},   /* arblm */
-        {0x35, 0x00},   /* rsvd35 */
-        {0x36, 0xf8},   /* rsvd36 */
-        {0x38, 0x72},   /* acom38 */
-        {0x39, 0x57},   /* ofon */
-        {0x3a, 0x80},   /* tslb */
-        {0x3b, 0xc4},
+        {0x34, 0x3f},   /* aref1 */
+        {0x35, 0x00},   /* aref2 */
+        {0x36, 0xf8},   /* aref3 */
+        {0x38, 0x72},   /* adc2 */
+        {0x39, 0x57},   /* aref4 */
+        {0x3a, 0x80},   /* tslb - yuyv */
+        {0x3b, 0xc4},   /* com11 - night mode 1/4 frame rate */
         {0x3d, 0x99},   /* com13 */
-        {0x3f, 0xc1},
+        {0x3f, 0xc1},   /* edge */
         {0x40, 0xc0},   /* com15 */
         {0x41, 0x40},   /* com16 */
-        {0x42, 0xc0},
-        {0x43, 0x0a},
+        {0x42, 0xc0},   /* com17 */
+        {0x43, 0x0a},   /* rsvd */
         {0x44, 0xf0},
         {0x45, 0x46},
         {0x46, 0x62},
@@ -297,22 +310,22 @@ static const u8 sensor_init_ov965x[][2] = {
         {0x4c, 0x7f},
         {0x4d, 0x7f},
         {0x4e, 0x7f},
-        {0x4f, 0x98},
+        {0x4f, 0x98},   /* matrix */
         {0x50, 0x98},
         {0x51, 0x00},
         {0x52, 0x28},
         {0x53, 0x70},
         {0x54, 0x98},
-        {0x58, 0x1a},
-        {0x59, 0x85},
+        {0x58, 0x1a},   /* matrix coef sign */
+        {0x59, 0x85},   /* AWB control */
         {0x5a, 0xa9},
         {0x5b, 0x64},
         {0x5c, 0x84},
         {0x5d, 0x53},
         {0x5e, 0x0e},
-        {0x5f, 0xf0},
-        {0x60, 0xf0},
-        {0x61, 0xf0},
+        {0x5f, 0xf0},   /* AWB blue limit */
+        {0x60, 0xf0},   /* AWB red limit */
+        {0x61, 0xf0},   /* AWB green limit */
         {0x62, 0x00},   /* lcc1 */
         {0x63, 0x00},   /* lcc2 */
         {0x64, 0x02},   /* lcc3 */
@@ -324,15 +337,15 @@ static const u8 sensor_init_ov965x[][2] = {
         {0x6d, 0x55},
         {0x6e, 0x00},
         {0x6f, 0x9d},
-        {0x70, 0x21},
+        {0x70, 0x21},   /* dnsth */
         {0x71, 0x78},
-        {0x72, 0x00},
-        {0x73, 0x01},
-        {0x74, 0x3a},
-        {0x75, 0x35},
+        {0x72, 0x00},   /* poidx */
+        {0x73, 0x01},   /* pckdv */
+        {0x74, 0x3a},   /* xindx */
+        {0x75, 0x35},   /* yindx */
         {0x76, 0x01},
         {0x77, 0x02},
-        {0x7a, 0x12},
+        {0x7a, 0x12},   /* gamma curve */
         {0x7b, 0x08},
         {0x7c, 0x16},
         {0x7d, 0x30},
@@ -349,33 +362,33 @@ static const u8 sensor_init_ov965x[][2] = {
         {0x88, 0xe6},
         {0x89, 0xf2},
         {0x8a, 0x03},
-        {0x8c, 0x89},
+        {0x8c, 0x89},   /* com19 */
         {0x14, 0x28},   /* com9 */
         {0x90, 0x7d},
         {0x91, 0x7b},
-        {0x9d, 0x03},
-        {0x9e, 0x04},
+        {0x9d, 0x03},   /* lcc6 */
+        {0x9e, 0x04},   /* lcc7 */
         {0x9f, 0x7a},
         {0xa0, 0x79},
         {0xa1, 0x40},   /* aechm */
-        {0xa4, 0x50},
+        {0xa4, 0x50},   /* com21 */
         {0xa5, 0x68},   /* com26 */
-        {0xa6, 0x4a},
-        {0xa8, 0xc1},   /* acoma8 */
-        {0xa9, 0xef},   /* acoma9 */
+        {0xa6, 0x4a},   /* AWB green */
+        {0xa8, 0xc1},   /* refa8 */
+        {0xa9, 0xef},   /* refa9 */
         {0xaa, 0x92},
         {0xab, 0x04},
-        {0xac, 0x80},
+        {0xac, 0x80},   /* black level control */
         {0xad, 0x80},
         {0xae, 0x80},
         {0xaf, 0x80},
         {0xb2, 0xf2},
         {0xb3, 0x20},
-        {0xb4, 0x20},
+        {0xb4, 0x20},   /* ctrlb4 */
         {0xb5, 0x00},
         {0xb6, 0xaf},
         {0xbb, 0xae},
-        {0xbc, 0x7f},
+        {0xbc, 0x7f},   /* ADC channel offsets */
         {0xdb, 0x7f},
         {0xbe, 0x7f},
         {0xbf, 0x7f},
@@ -384,7 +397,7 @@ static const u8 sensor_init_ov965x[][2] = {
         {0xc2, 0x01},
         {0xc3, 0x4e},
         {0xc6, 0x85},
-        {0xc7, 0x80},
+        {0xc7, 0x80},   /* com24 */
         {0xc9, 0xe0},
         {0xca, 0xe8},
         {0xcb, 0xf0},
@@ -399,11 +412,11 @@ static const u8 sensor_init_ov965x[][2] = {
         {0x58, 0x1a},
         {0xff, 0x41},   /* read 41, write ff 00 */
         {0x41, 0x40},   /* com16 */
-        {0xc5, 0x03},
-        {0x6a, 0x02},
+        {0xc5, 0x03},   /* 60 Hz banding filter */
+        {0x6a, 0x02},   /* 50 Hz banding filter */
 
-        {0x12, 0x62},   /* com7 - VGA + CIF */
-        {0x36, 0xfa},   /* rsvd36 */
+        {0x12, 0x62},   /* com7 - 30fps VGA YUV */
+        {0x36, 0xfa},   /* aref3 */
         {0x69, 0x0a},   /* hv */
         {0x8c, 0x89},   /* com22 */
         {0x14, 0x28},   /* com9 */
@@ -442,8 +455,8 @@ static const u8 bridge_init_ov965x_2[][2] = {
         {0x52, 0x3c},
         {0x53, 0x00},
         {0x54, 0x00},
-        {0x55, 0x00},
-        {0x57, 0x00},
+        {0x55, 0x00},   /* brightness */
+        {0x57, 0x00},   /* contrast 2 */
         {0x5c, 0x00},
         {0x5a, 0xa0},
         {0x5b, 0x78},
@@ -489,9 +502,66 @@ static const u8 sensor_init_ov965x_2[][2] = {
         {0x13, 0xe7},   /* com8 - everything (AGC, AWB and AEC) */
 };
 
+static const u8 sensor_start_ov965x[][2] = {
+        {0x12, 0x62},   /* com7 - 30fps VGA YUV */
+        {0x36, 0xfa},   /* aref3 */
+        {0x69, 0x0a},   /* hv */
+        {0x8c, 0x89},   /* com22 */
+        {0x14, 0x28},   /* com9 */
+        {0x3e, 0x0c},   /* com14 */
+        {0x41, 0x40},   /* com16 */
+        {0x72, 0x00},
+        {0x73, 0x00},
+        {0x74, 0x3a},
+        {0x75, 0x35},
+        {0x76, 0x01},
+        {0xc7, 0x80},   /* com24 */
+        {0x03, 0x12},   /* vref */
+        {0x17, 0x16},   /* hstart */
+        {0x18, 0x02},   /* hstop */
+        {0x19, 0x01},   /* vstrt */
+        {0x1a, 0x3d},   /* vstop */
+        {0x32, 0xff},   /* href */
+        {0xc0, 0xaa},
+        {}
+};
+
 static const u8 bridge_start_ov965x[][2] = {
+        {0x94, 0xaa},
+        {0xf1, 0x60},
+        {0xe5, 0x04},
+        {0xc0, 0x50},
+        {0xc1, 0x3c},
+        {0x8c, 0x00},
+        {0x8d, 0x1c},
+        {0x34, 0x05},
+        {}
+};
+
+static const u8 bridge_start_ov965x_vga[][2] = {
+        {0xc2, 0x0c},
+        {0xc3, 0xf9},
+        {0xda, 0x01},
+        {0x50, 0x00},
+        {0x51, 0xa0},
+        {0x52, 0x3c},
+        {0x53, 0x00},
+        {0x54, 0x00},
+        {0x55, 0x00},
+        {0x57, 0x00},
+        {0x5c, 0x00},
+        {0x5a, 0xa0},
+        {0x5b, 0x78},
+        {0x35, 0x02},
+        {0xd9, 0x10},
+        {0x94, 0x11},
+        {}
+};
+
+static const u8 bridge_start_ov965x_cif[][2] = {
         {0xc2, 0x4c},
         {0xc3, 0xf9},
+        {0xda, 0x00},
         {0x50, 0x00},
         {0x51, 0xa0},
         {0x52, 0x78},
@@ -500,30 +570,54 @@ static const u8 bridge_start_ov965x[][2] = {
         {0x55, 0x00},
         {0x57, 0x00},
         {0x5c, 0x00},
-        {0x5a, 0x28},
-        {0x5b, 0x1e},
-        {0x35, 0x00},
-        {0xd9, 0x21},
+        {0x5a, 0x50},
+        {0x5b, 0x3c},
+        {0x35, 0x02},
+        {0xd9, 0x10},
         {0x94, 0x11},
+        {}
 };
 
-static const u8 sensor_start_ov965x[][2] = {
-        {0x3b, 0xe4},
+static const u8 sensor_start_ov965x_vga[][2] = {
+        {0x3b, 0xc4},   /* com11 - night mode 1/4 frame rate */
+        {0x1e, 0x04},   /* mvfp */
+        {0x13, 0xe0},   /* com8 */
+        {0x00, 0x00},
+        {0x13, 0xe7},   /* com8 - everything (AGC, AWB and AEC) */
+        {0x11, 0x03},   /* clkrc */
+        {0x6b, 0x5a},   /* dblv */
+        {0x6a, 0x05},   /* 50 Hz banding filter */
+        {0xc5, 0x07},   /* 60 Hz banding filter */
+        {0xa2, 0x4b},   /* bd50 */
+        {0xa3, 0x3e},   /* bd60 */
+
+        {0x2d, 0x00},   /* advfl */
+        {}
+};
+
+static const u8 sensor_start_ov965x_cif[][2] = {
+        {0x3b, 0xe4},   /* com11 - night mode 1/4 frame rate */
         {0x1e, 0x04},   /* mvfp */
         {0x13, 0xe0},   /* com8 */
         {0x00, 0x00},
         {0x13, 0xe7},   /* com8 - everything (AGC, AWB and AEC) */
         {0x11, 0x01},   /* clkrc */
         {0x6b, 0x5a},   /* dblv */
-        {0x6a, 0x02},
-        {0xc5, 0x03},
-        {0xa2, 0x96},
-        {0xa3, 0x7d},
+        {0x6a, 0x02},   /* 50 Hz banding filter */
+        {0xc5, 0x03},   /* 60 Hz banding filter */
+        {0xa2, 0x96},   /* bd50 */
+        {0xa3, 0x7d},   /* bd60 */
+
         {0xff, 0x13},   /* read 13, write ff 00 */
         {0x13, 0xe7},
-        {0x3a, 0x80},
+        {0x3a, 0x80},   /* tslb - yuyv */
+        {}
+};
+
+static const u8 sensor_start_ov965x_2[][2] = {
         {0xff, 0x42},   /* read 42, write ff 00 */
-        {0x42, 0xc1},
+        {0x42, 0xc1},   /* com17 - 50 Hz filter */
+        {}
 };
 
 
@@ -705,11 +799,17 @@ static int sd_config(struct gspca_dev *gspca_dev,
 
         cam = &gspca_dev->cam;
 
-        cam->cam_mode = vga_mode;
-        cam->nmodes = ARRAY_SIZE(vga_mode);
+        if (sd->sensor == SENSOR_OV772X) {
+                cam->cam_mode = vga_yuyv_mode;
+                cam->nmodes = ARRAY_SIZE(vga_yuyv_mode);
 
-        cam->bulk_size = 16384;
-        cam->bulk_nurbs = 2;
+                cam->bulk = 1;
+                cam->bulk_size = 16384;
+                cam->bulk_nurbs = 2;
+        } else {                /* ov965x */
+                cam->cam_mode = vga_jpeg_mode;
+                cam->nmodes = ARRAY_SIZE(vga_jpeg_mode);
+        }
 
         return 0;
 }
@@ -778,6 +878,7 @@ static int sd_init(struct gspca_dev *gspca_dev)
 static int sd_start(struct gspca_dev *gspca_dev)
 {
         struct sd *sd = (struct sd *) gspca_dev;
+        int mode;
 
         switch (sd->sensor) {
         case SENSOR_OV772X:
@@ -786,13 +887,28 @@ static int sd_start(struct gspca_dev *gspca_dev)
                 break;
         default:
 /*      case SENSOR_OV965X: */
-                reg_w_array(gspca_dev, bridge_start_ov965x,
-                                ARRAY_SIZE(bridge_start_ov965x));
+
                 sccb_w_array(gspca_dev, sensor_start_ov965x,
                                 ARRAY_SIZE(sensor_start_ov965x));
+                reg_w_array(gspca_dev, bridge_start_ov965x,
+                                ARRAY_SIZE(bridge_start_ov965x));
+                mode = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv;
+                if (mode != 0) {        /* 320x240 */
+                        reg_w_array(gspca_dev, bridge_start_ov965x_cif,
+                                        ARRAY_SIZE(bridge_start_ov965x_cif));
+                        sccb_w_array(gspca_dev, sensor_start_ov965x_cif,
+                                        ARRAY_SIZE(sensor_start_ov965x_cif));
+                } else {                /* 640x480 */
+                        reg_w_array(gspca_dev, bridge_start_ov965x_vga,
+                                        ARRAY_SIZE(bridge_start_ov965x_vga));
+                        sccb_w_array(gspca_dev, sensor_start_ov965x_vga,
+                                        ARRAY_SIZE(sensor_start_ov965x_vga));
+                }
+                sccb_w_array(gspca_dev, sensor_start_ov965x_2,
+                                ARRAY_SIZE(sensor_start_ov965x_2));
+                ov534_reg_write(gspca_dev, 0xe0, 0x00);
                 ov534_reg_write(gspca_dev, 0xe0, 0x00);
                 ov534_set_led(gspca_dev, 1);
-/*fixme: other sensor start omitted*/
         }
         return 0;
 }
@@ -832,9 +948,11 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, struct gspca_frame *frame,
         __u32 this_pts;
         u16 this_fid;
         int remaining_len = len;
+        int payload_len;
 
+        payload_len = gspca_dev->cam.bulk ? 2048 : 2040;
         do {
-                len = min(remaining_len, 2040);         /*fixme: was 2048*/
+                len = min(remaining_len, payload_len);
 
                 /* Payloads are prefixed with a UVC-style header.  We
                    consider a frame to start when the FID toggles, or the PTS
@@ -864,30 +982,27 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, struct gspca_frame *frame,
 
                 /* If PTS or FID has changed, start a new frame. */
                 if (this_pts != sd->last_pts || this_fid != sd->last_fid) {
-                        gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
-                                        NULL, 0);
+                        if (gspca_dev->last_packet_type == INTER_PACKET)
+                                frame = gspca_frame_add(gspca_dev,
+                                                        LAST_PACKET, frame,
+                                                        NULL, 0);
                         sd->last_pts = this_pts;
                         sd->last_fid = this_fid;
-                }
-
-                /* Add the data from this payload */
-                gspca_frame_add(gspca_dev, INTER_PACKET, frame,
+                        gspca_frame_add(gspca_dev, FIRST_PACKET, frame,
                                         data + 12, len - 12);
-
                 /* If this packet is marked as EOF, end the frame */
-                if (data[1] & UVC_STREAM_EOF) {
+                } else if (data[1] & UVC_STREAM_EOF) {
                         sd->last_pts = 0;
-
-                        if (frame->data_end - frame->data !=
-                            gspca_dev->width * gspca_dev->height * 2) {
-                                PDEBUG(D_PACK, "short frame");
-                                goto discard;
-                        }
-
                         frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame,
-                                                NULL, 0);
+                                                data + 12, len - 12);
+                } else {
+
+                        /* Add the data from this payload */
+                        gspca_frame_add(gspca_dev, INTER_PACKET, frame,
+                                                data + 12, len - 12);
                 }
 
+
                 /* Done this payload */
                 goto scan_next;
 
diff --git a/drivers/media/video/gspca/sonixb.c b/drivers/media/video/gspca/sonixb.c
index 153d0a91d4b5..cf3af8de6e97 100644
--- a/drivers/media/video/gspca/sonixb.c
+++ b/drivers/media/video/gspca/sonixb.c
@@ -877,6 +877,8 @@ static int sd_config(struct gspca_dev *gspca_dev,
                 cam->cam_mode = sif_mode;
                 cam->nmodes = ARRAY_SIZE(sif_mode);
         }
+        cam->npkt = 36;                 /* 36 packets per ISOC message */
+
         sd->brightness = BRIGHTNESS_DEF;
         sd->gain = GAIN_DEF;
         sd->exposure = EXPOSURE_DEF;
diff --git a/drivers/media/video/gspca/sonixj.c b/drivers/media/video/gspca/sonixj.c
index c72e19d3ac37..dc6a6f11354a 100644
--- a/drivers/media/video/gspca/sonixj.c
+++ b/drivers/media/video/gspca/sonixj.c
@@ -62,7 +62,6 @@ struct sd {
 #define BRIDGE_SN9C105 1
 #define BRIDGE_SN9C110 2
 #define BRIDGE_SN9C120 3
-#define BRIDGE_SN9C325 4
         u8 sensor;                      /* Type of image sensor chip */
 #define SENSOR_HV7131R 0
 #define SENSOR_MI0360 1
@@ -354,9 +353,9 @@ static const u8 sn_ov7648[0x1c] = {
 
 static const u8 sn_ov7660[0x1c] = {
 /*      reg0    reg1    reg2    reg3    reg4    reg5    reg6    reg7 */
-        0x00,   0x61,   0x40,   0x00,   0x1a,   0x20,   0x20,   0x20,
+        0x00,   0x61,   0x40,   0x00,   0x1a,   0x00,   0x00,   0x00,
 /*      reg8    reg9    rega    regb    regc    regd    rege    regf */
-        0x81,   0x21,   0x07,   0x00,   0x00,   0x00,   0x00,   0x10,
+        0x81,   0x21,   0x00,   0x00,   0x00,   0x00,   0x00,   0x00,
 /*      reg10   reg11   reg12   reg13   reg14   reg15   reg16   reg17 */
         0x03,   0x00,   0x01,   0x01,   0x08,   0x28,   0x1e,   0x20,
 /*      reg18   reg19   reg1a   reg1b */
@@ -757,6 +756,7 @@ static const u8 ov7660_sensor_init[][8] = {
         {0xc1, 0x21, 0x88, 0xaf, 0xc7, 0xdf, 0x00, 0x10}, /* gamma curve */
         {0xc1, 0x21, 0x8b, 0x99, 0x99, 0xcf, 0x00, 0x10}, /* reserved */
         {0xb1, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x10}, /* DM_LNL/H */
+        {0xb1, 0x21, 0xa1, 0x00, 0x00, 0x00, 0x00, 0x10},
 /****** (some exchanges in the win trace) ******/
         {0xa1, 0x21, 0x1e, 0x01, 0x00, 0x00, 0x00, 0x10}, /* MVFP */
                                                 /* bits[3..0]reserved */
@@ -1065,9 +1065,9 @@ static int configure_gpio(struct gspca_dev *gspca_dev,
         struct sd *sd = (struct sd *) gspca_dev;
         const u8 *reg9a;
         static const u8 reg9a_def[] =
-                {0x08, 0x40, 0x20, 0x10, 0x00, 0x04};
-        static const u8 reg9a_sn9c325[] =
-                {0x0a, 0x40, 0x38, 0x30, 0x00, 0x20};
+                {0x00, 0x40, 0x20, 0x00, 0x00, 0x00};
+        static const u8 reg9a_spec[] =
+                {0x00, 0x40, 0x38, 0x30, 0x00, 0x20};
         static const u8 regd4[] = {0x60, 0x00, 0x00};
 
         reg_w1(gspca_dev, 0xf1, 0x00);
@@ -1077,9 +1077,10 @@ static int configure_gpio(struct gspca_dev *gspca_dev,
         reg_w(gspca_dev, 0x01, &sn9c1xx[1], 2);
         reg_w(gspca_dev, 0x08, &sn9c1xx[8], 2);
         reg_w(gspca_dev, 0x17, &sn9c1xx[0x17], 5);      /* jfm len was 3 */
-        switch (sd->bridge) {
-        case BRIDGE_SN9C325:
-                reg9a = reg9a_sn9c325;
+        switch (sd->sensor) {
+        case SENSOR_OV7660:
+        case SENSOR_SP80708:
+                reg9a = reg9a_spec;
                 break;
         default:
                 reg9a = reg9a_def;
@@ -1104,7 +1105,6 @@ static int configure_gpio(struct gspca_dev *gspca_dev,
                 reg_w1(gspca_dev, 0x17, 0x64);
                 reg_w1(gspca_dev, 0x01, 0x42);
                 break;
-/*jfm: from win trace */
         case SENSOR_OV7630:
                 reg_w1(gspca_dev, 0x01, 0x61);
                 reg_w1(gspca_dev, 0x17, 0xe2);
@@ -1114,18 +1114,15 @@ static int configure_gpio(struct gspca_dev *gspca_dev,
         case SENSOR_OV7648:
                 reg_w1(gspca_dev, 0x01, 0x63);
                 reg_w1(gspca_dev, 0x17, 0x20);
+                reg_w1(gspca_dev, 0x01, 0x62);
                 reg_w1(gspca_dev, 0x01, 0x42);
                 break;
-/*jfm: from win trace */
         case SENSOR_OV7660:
-                if (sd->bridge == BRIDGE_SN9C120) {
-                        reg_w1(gspca_dev, 0x01, 0x61);
-                        reg_w1(gspca_dev, 0x17, 0x20);
-                        reg_w1(gspca_dev, 0x01, 0x60);
-                        reg_w1(gspca_dev, 0x01, 0x40);
-                        break;
-                }
-                /* fall thru */
+                reg_w1(gspca_dev, 0x01, 0x61);
+                reg_w1(gspca_dev, 0x17, 0x20);
+                reg_w1(gspca_dev, 0x01, 0x60);
+                reg_w1(gspca_dev, 0x01, 0x40);
+                break;
         case SENSOR_SP80708:
                 reg_w1(gspca_dev, 0x01, 0x63);
                 reg_w1(gspca_dev, 0x17, 0x20);
@@ -1134,6 +1131,9 @@ static int configure_gpio(struct gspca_dev *gspca_dev,
                 mdelay(100);
                 reg_w1(gspca_dev, 0x02, 0x62);
                 break;
+/*      case SENSOR_HV7131R: */
+/*      case SENSOR_MI0360: */
+/*      case SENSOR_MO4000: */
         default:
                 reg_w1(gspca_dev, 0x01, 0x43);
                 reg_w1(gspca_dev, 0x17, 0x61);
@@ -1280,6 +1280,7 @@ static int sd_config(struct gspca_dev *gspca_dev,
         cam = &gspca_dev->cam;
         cam->cam_mode = vga_mode;
         cam->nmodes = ARRAY_SIZE(vga_mode);
+        cam->npkt = 24;                 /* 24 packets per ISOC message */
 
         sd->bridge = id->driver_info >> 16;
         sd->sensor = id->driver_info >> 8;
@@ -1683,13 +1684,9 @@ static int sd_start(struct gspca_dev *gspca_dev)
         case SENSOR_OV7648:
                 reg17 = 0x20;
                 break;
-/*jfm: from win trace */
         case SENSOR_OV7660:
-                if (sd->bridge == BRIDGE_SN9C120) {
-                        reg17 = 0xa0;
-                        break;
-                }
-                /* fall thru */
+                reg17 = 0xa0;
+                break;
         default:
                 reg17 = 0x60;
                 break;
@@ -1714,16 +1711,17 @@ static int sd_start(struct gspca_dev *gspca_dev)
                 reg_w1(gspca_dev, 0x9a, 0x0a);
                 reg_w1(gspca_dev, 0x99, 0x60);
                 break;
+        case SENSOR_OV7660:
+                reg_w1(gspca_dev, 0x9a, 0x05);
+                if (sd->bridge == BRIDGE_SN9C105)
+                        reg_w1(gspca_dev, 0x99, 0xff);
+                else
+                        reg_w1(gspca_dev, 0x99, 0x5b);
+                break;
         case SENSOR_SP80708:
                 reg_w1(gspca_dev, 0x9a, 0x05);
                 reg_w1(gspca_dev, 0x99, 0x59);
                 break;
-        case SENSOR_OV7660:
-                if (sd->bridge == BRIDGE_SN9C120) {
-                        reg_w1(gspca_dev, 0x9a, 0x05);
-                        break;
-                }
-                /* fall thru */
         default:
                 reg_w1(gspca_dev, 0x9a, 0x08);
                 reg_w1(gspca_dev, 0x99, 0x59);
@@ -2193,6 +2191,7 @@ static const __devinitdata struct usb_device_id device_table[] = {
         {USB_DEVICE(0x0471, 0x0328), BSI(SN9C105, MI0360, 0x5d)},
         {USB_DEVICE(0x0471, 0x0330), BSI(SN9C105, MI0360, 0x5d)},
         {USB_DEVICE(0x06f8, 0x3004), BSI(SN9C105, OV7660, 0x21)},
+        {USB_DEVICE(0x06f8, 0x3008), BSI(SN9C105, OV7660, 0x21)},
         {USB_DEVICE(0x0c45, 0x6040), BSI(SN9C102P, HV7131R, 0x11)},
 /* bw600.inf:
         {USB_DEVICE(0x0c45, 0x6040), BSI(SN9C102P, MI0360, 0x5d)}, */
@@ -2211,7 +2210,12 @@ static const __devinitdata struct usb_device_id device_table[] = {
 #if !defined CONFIG_USB_SN9C102 && !defined CONFIG_USB_SN9C102_MODULE
         {USB_DEVICE(0x0c45, 0x60fe), BSI(SN9C105, OV7630, 0x21)},
 #endif
+        {USB_DEVICE(0x0c45, 0x6100), BSI(SN9C120, MI0360, 0x5d)}, /*sn9c128*/
 /*      {USB_DEVICE(0x0c45, 0x6108), BSI(SN9C120, OM6801, 0x??)}, */
+        {USB_DEVICE(0x0c45, 0x610a), BSI(SN9C120, OV7648, 0x21)}, /*sn9c128*/
+        {USB_DEVICE(0x0c45, 0x610b), BSI(SN9C120, OV7660, 0x21)}, /*sn9c128*/
+        {USB_DEVICE(0x0c45, 0x610c), BSI(SN9C120, HV7131R, 0x11)}, /*sn9c128*/
+        {USB_DEVICE(0x0c45, 0x610e), BSI(SN9C120, OV7630, 0x21)}, /*sn9c128*/
 /*      {USB_DEVICE(0x0c45, 0x6122), BSI(SN9C110, ICM105C, 0x??)}, */
 /*      {USB_DEVICE(0x0c45, 0x6123), BSI(SN9C110, SanyoCCD, 0x??)}, */
         {USB_DEVICE(0x0c45, 0x6128), BSI(SN9C110, OM6802, 0x21)}, /*sn9c325?*/
diff --git a/drivers/media/video/gspca/spca500.c b/drivers/media/video/gspca/spca500.c
index 6f38fa6d86b6..8806b2ff82be 100644
--- a/drivers/media/video/gspca/spca500.c
+++ b/drivers/media/video/gspca/spca500.c
@@ -32,9 +32,6 @@ MODULE_LICENSE("GPL");
 struct sd {
         struct gspca_dev gspca_dev;             /* !! must be the first item */
 
-        __u8 packet[ISO_MAX_SIZE + 128];
-                                 /* !! no more than 128 ff in an ISO packet */
-
         unsigned char brightness;
         unsigned char contrast;
         unsigned char colors;
@@ -906,7 +903,6 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev,
 {
         struct sd *sd = (struct sd *) gspca_dev;
         int i;
-        __u8 *s, *d;
         static __u8 ffd9[] = {0xff, 0xd9};
 
 /* frames are jpeg 4.1.1 without 0xff escape */
@@ -930,22 +926,19 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev,
         }
 
         /* add 0x00 after 0xff */
-        for (i = len; --i >= 0; )
-                if (data[i] == 0xff)
-                        break;
-        if (i < 0) {                    /* no 0xff */
-                gspca_frame_add(gspca_dev, INTER_PACKET, frame, data, len);
-                return;
-        }
-        s = data;
-        d = sd->packet;
-        for (i = 0; i < len; i++) {
-                *d++ = *s++;
-                if (s[-1] == 0xff)
-                        *d++ = 0x00;
-        }
-        gspca_frame_add(gspca_dev, INTER_PACKET, frame,
-                        sd->packet, d - sd->packet);
+        i = 0;
+        do {
+                if (data[i] == 0xff) {
+                        gspca_frame_add(gspca_dev, INTER_PACKET, frame,
+                                        data, i + 1);
+                        len -= i;
+                        data += i;
+                        *data = 0x00;
+                        i = 0;
+                }
+                i++;
+        } while (i < len);
+        gspca_frame_add(gspca_dev, INTER_PACKET, frame, data, len);
 }
 
 static void setbrightness(struct gspca_dev *gspca_dev)
diff --git a/drivers/media/video/gspca/spca505.c b/drivers/media/video/gspca/spca505.c
index 2acec58b1b97..ea8c9fe2e961 100644
--- a/drivers/media/video/gspca/spca505.c
+++ b/drivers/media/video/gspca/spca505.c
@@ -637,19 +637,19 @@ static int sd_config(struct gspca_dev *gspca_dev,
                 cam->nmodes = ARRAY_SIZE(vga_mode) - 1;
         sd->brightness = BRIGHTNESS_DEF;
 
-        if (sd->subtype == Nxultra) {
-                if (write_vector(gspca_dev, spca505b_init_data))
-                        return -EIO;
-        } else {
-                if (write_vector(gspca_dev, spca505_init_data))
-                        return -EIO;
-        }
         return 0;
 }
 
 /* this function is called at probe and resume time */
 static int sd_init(struct gspca_dev *gspca_dev)
 {
+        struct sd *sd = (struct sd *) gspca_dev;
+
+        if (write_vector(gspca_dev,
+                         sd->subtype == Nxultra
+                                ? spca505b_init_data
+                                : spca505_init_data))
+                return -EIO;
         return 0;
 }
 
diff --git a/drivers/media/video/gspca/spca508.c b/drivers/media/video/gspca/spca508.c
index adacf8437661..2ed2669bac3e 100644
--- a/drivers/media/video/gspca/spca508.c
+++ b/drivers/media/video/gspca/spca508.c
@@ -1,7 +1,7 @@
 /*
  * SPCA508 chip based cameras subdriver
  *
- * V4L2 by Jean-Francois Moine <http://moinejf.free.fr>
+ * Copyright (C) 2009 Jean-Francois Moine <http://moinejf.free.fr>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -30,9 +30,9 @@ MODULE_LICENSE("GPL");
 struct sd {
         struct gspca_dev gspca_dev;             /* !! must be the first item */
 
-        unsigned char brightness;
+        u8 brightness;
 
-        char subtype;
+        u8 subtype;
 #define CreativeVista 0
 #define HamaUSBSightcam 1
 #define HamaUSBSightcam2 2
@@ -86,58 +86,34 @@ static const struct v4l2_pix_format sif_mode[] = {
 };
 
 /* Frame packet header offsets for the spca508 */
-#define SPCA508_OFFSET_TYPE 1
-#define SPCA508_OFFSET_COMPRESS 2
-#define SPCA508_OFFSET_FRAMSEQ 8
-#define SPCA508_OFFSET_WIN1LUM 11
 #define SPCA508_OFFSET_DATA 37
 
-#define SPCA508_SNAPBIT 0x20
-#define SPCA508_SNAPCTRL 0x40
-/*************** I2c ****************/
-#define SPCA508_INDEX_I2C_BASE 0x8800
-
 /*
  * Initialization data: this is the first set-up data written to the
  * device (before the open data).
  */
 static const u16 spca508_init_data[][2] =
 {
-        /*  line   URB      value, index */
-        /* 44274  1804 */ {0x0000, 0x870b},
-
-        /* 44299  1805 */ {0x0020, 0x8112},
-        /* Video drop enable, ISO streaming disable */
-        /* 44324  1806 */ {0x0003, 0x8111},
-        /* Reset compression & memory */
-        /* 44349  1807 */ {0x0000, 0x8110},
-        /* Disable all outputs */
-        /* 44372  1808 */ /* READ {0x0000, 0x8114} -> 0000: 00  */
-        /* 44398  1809 */ {0x0000, 0x8114},
-        /* SW GPIO data */
-        /* 44423  1810 */ {0x0008, 0x8110},
-        /* Enable charge pump output */
-        /* 44527  1811 */ {0x0002, 0x8116},
-        /* 200 kHz pump clock */
-        /* 44555  1812 */
-                /* UNKNOWN DIRECTION (URB_FUNCTION_SELECT_INTERFACE:) */
-        /* 44590  1813 */ {0x0003, 0x8111},
-        /* Reset compression & memory */
-        /* 44615  1814 */ {0x0000, 0x8111},
-        /* Normal mode (not reset) */
-        /* 44640  1815 */ {0x0098, 0x8110},
-        /* Enable charge pump output, sync.serial,external 2x clock */
-        /* 44665  1816 */ {0x000d, 0x8114},
-        /* SW GPIO data */
-        /* 44690  1817 */ {0x0002, 0x8116},
-        /* 200 kHz pump clock */
-        /* 44715  1818 */ {0x0020, 0x8112},
-        /* Video drop enable, ISO streaming disable */
+        {0x0000, 0x870b},
+
+        {0x0020, 0x8112},       /* Video drop enable, ISO streaming disable */
+        {0x0003, 0x8111},       /* Reset compression & memory */
+        {0x0000, 0x8110},       /* Disable all outputs */
+        /* READ {0x0000, 0x8114} -> 0000: 00  */
+        {0x0000, 0x8114},       /* SW GPIO data */
+        {0x0008, 0x8110},       /* Enable charge pump output */
+        {0x0002, 0x8116},       /* 200 kHz pump clock */
+        /* UNKNOWN DIRECTION (URB_FUNCTION_SELECT_INTERFACE:) */
+        {0x0003, 0x8111},       /* Reset compression & memory */
+        {0x0000, 0x8111},       /* Normal mode (not reset) */
+        {0x0098, 0x8110},
+                /* Enable charge pump output, sync.serial,external 2x clock */
+        {0x000d, 0x8114},       /* SW GPIO data */
+        {0x0002, 0x8116},       /* 200 kHz pump clock */
+        {0x0020, 0x8112},       /* Video drop enable, ISO streaming disable */
 /* --------------------------------------- */
-        /* 44740  1819 */ {0x000f, 0x8402},
-        /* memory bank */
-        /* 44765  1820 */ {0x0000, 0x8403},
-        /* ... address */
+        {0x000f, 0x8402},       /* memory bank */
+        {0x0000, 0x8403},       /* ... address */
 /* --------------------------------------- */
 /* 0x88__ is Synchronous Serial Interface. */
 /* TBD: This table could be expressed more compactly */
@@ -145,446 +121,384 @@ static const u16 spca508_init_data[][2] =
 /* TBD: Should see if the values in spca50x_i2c_data */
 /* would work with the VQ110 instead of the values */
 /* below. */
-        /* 44790  1821 */ {0x00c0, 0x8804},
-        /* SSI slave addr */
-        /* 44815  1822 */ {0x0008, 0x8802},
-        /* 375 Khz SSI clock */
-        /* 44838  1823 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 44862  1824 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 44888  1825 */ {0x0008, 0x8802},
-        /* 375 Khz SSI clock */
-        /* 44913  1826 */ {0x0012, 0x8801},
-        /* SSI reg addr */
-        /* 44938  1827 */ {0x0080, 0x8800},
-        /* SSI data to write */
-        /* 44961  1828 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 44985  1829 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45009  1830 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 45035  1831 */ {0x0008, 0x8802},
-        /* 375 Khz SSI clock */
-        /* 45060  1832 */ {0x0012, 0x8801},
-        /* SSI reg addr */
-        /* 45085  1833 */ {0x0000, 0x8800},
-        /* SSI data to write */
-        /* 45108  1834 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45132  1835 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45156  1836 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 45182  1837 */ {0x0008, 0x8802},
-        /* 375 Khz SSI clock */
-        /* 45207  1838 */ {0x0011, 0x8801},
-        /* SSI reg addr */
-        /* 45232  1839 */ {0x0040, 0x8800},
-        /* SSI data to write */
-        /* 45255  1840 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45279  1841 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45303  1842 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 45329  1843 */ {0x0008, 0x8802},
-        /* 45354  1844 */ {0x0013, 0x8801},
-        /* 45379  1845 */ {0x0000, 0x8800},
-        /* 45402  1846 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45426  1847 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45450  1848 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 45476  1849 */ {0x0008, 0x8802},
-        /* 45501  1850 */ {0x0014, 0x8801},
-        /* 45526  1851 */ {0x0000, 0x8800},
-        /* 45549  1852 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45573  1853 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45597  1854 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 45623  1855 */ {0x0008, 0x8802},
-        /* 45648  1856 */ {0x0015, 0x8801},
-        /* 45673  1857 */ {0x0001, 0x8800},
-        /* 45696  1858 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45720  1859 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45744  1860 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 45770  1861 */ {0x0008, 0x8802},
-        /* 45795  1862 */ {0x0016, 0x8801},
-        /* 45820  1863 */ {0x0003, 0x8800},
-        /* 45843  1864 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45867  1865 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 45891  1866 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 45917  1867 */ {0x0008, 0x8802},
-        /* 45942  1868 */ {0x0017, 0x8801},
-        /* 45967  1869 */ {0x0036, 0x8800},
-        /* 45990  1870 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46014  1871 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46038  1872 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 46064  1873 */ {0x0008, 0x8802},
-        /* 46089  1874 */ {0x0018, 0x8801},
-        /* 46114  1875 */ {0x00ec, 0x8800},
-        /* 46137  1876 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46161  1877 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46185  1878 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 46211  1879 */ {0x0008, 0x8802},
-        /* 46236  1880 */ {0x001a, 0x8801},
-        /* 46261  1881 */ {0x0094, 0x8800},
-        /* 46284  1882 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46308  1883 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46332  1884 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 46358  1885 */ {0x0008, 0x8802},
-        /* 46383  1886 */ {0x001b, 0x8801},
-        /* 46408  1887 */ {0x0000, 0x8800},
-        /* 46431  1888 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46455  1889 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46479  1890 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 46505  1891 */ {0x0008, 0x8802},
-        /* 46530  1892 */ {0x0027, 0x8801},
-        /* 46555  1893 */ {0x00a2, 0x8800},
-        /* 46578  1894 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46602  1895 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46626  1896 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 46652  1897 */ {0x0008, 0x8802},
-        /* 46677  1898 */ {0x0028, 0x8801},
-        /* 46702  1899 */ {0x0040, 0x8800},
-        /* 46725  1900 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46749  1901 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46773  1902 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 46799  1903 */ {0x0008, 0x8802},
-        /* 46824  1904 */ {0x002a, 0x8801},
-        /* 46849  1905 */ {0x0084, 0x8800},
-        /* 46872  1906 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 46896  1907 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00 */
-        /* 46920  1908 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 46946  1909 */ {0x0008, 0x8802},
-        /* 46971  1910 */ {0x002b, 0x8801},
-        /* 46996  1911 */ {0x00a8, 0x8800},
-        /* 47019  1912 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47043  1913 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47067  1914 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 47093  1915 */ {0x0008, 0x8802},
-        /* 47118  1916 */ {0x002c, 0x8801},
-        /* 47143  1917 */ {0x00fe, 0x8800},
-        /* 47166  1918 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47190  1919 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47214  1920 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 47240  1921 */ {0x0008, 0x8802},
-        /* 47265  1922 */ {0x002d, 0x8801},
-        /* 47290  1923 */ {0x0003, 0x8800},
-        /* 47313  1924 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47337  1925 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47361  1926 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 47387  1927 */ {0x0008, 0x8802},
-        /* 47412  1928 */ {0x0038, 0x8801},
-        /* 47437  1929 */ {0x0083, 0x8800},
-        /* 47460  1930 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47484  1931 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47508  1932 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 47534  1933 */ {0x0008, 0x8802},
-        /* 47559  1934 */ {0x0033, 0x8801},
-        /* 47584  1935 */ {0x0081, 0x8800},
-        /* 47607  1936 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47631  1937 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47655  1938 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 47681  1939 */ {0x0008, 0x8802},
-        /* 47706  1940 */ {0x0034, 0x8801},
-        /* 47731  1941 */ {0x004a, 0x8800},
-        /* 47754  1942 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47778  1943 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47802  1944 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 47828  1945 */ {0x0008, 0x8802},
-        /* 47853  1946 */ {0x0039, 0x8801},
-        /* 47878  1947 */ {0x0000, 0x8800},
-        /* 47901  1948 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47925  1949 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 47949  1950 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 47975  1951 */ {0x0008, 0x8802},
-        /* 48000  1952 */ {0x0010, 0x8801},
-        /* 48025  1953 */ {0x00a8, 0x8800},
-        /* 48048  1954 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48072  1955 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48096  1956 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 48122  1957 */ {0x0008, 0x8802},
-        /* 48147  1958 */ {0x0006, 0x8801},
-        /* 48172  1959 */ {0x0058, 0x8800},
-        /* 48195  1960 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48219  1961 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00 */
-        /* 48243  1962 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 48269  1963 */ {0x0008, 0x8802},
-        /* 48294  1964 */ {0x0000, 0x8801},
-        /* 48319  1965 */ {0x0004, 0x8800},
-        /* 48342  1966 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48366  1967 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48390  1968 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 48416  1969 */ {0x0008, 0x8802},
-        /* 48441  1970 */ {0x0040, 0x8801},
-        /* 48466  1971 */ {0x0080, 0x8800},
-        /* 48489  1972 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48513  1973 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48537  1974 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 48563  1975 */ {0x0008, 0x8802},
-        /* 48588  1976 */ {0x0041, 0x8801},
-        /* 48613  1977 */ {0x000c, 0x8800},
-        /* 48636  1978 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48660  1979 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48684  1980 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 48710  1981 */ {0x0008, 0x8802},
-        /* 48735  1982 */ {0x0042, 0x8801},
-        /* 48760  1983 */ {0x000c, 0x8800},
-        /* 48783  1984 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48807  1985 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48831  1986 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 48857  1987 */ {0x0008, 0x8802},
-        /* 48882  1988 */ {0x0043, 0x8801},
-        /* 48907  1989 */ {0x0028, 0x8800},
-        /* 48930  1990 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48954  1991 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 48978  1992 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 49004  1993 */ {0x0008, 0x8802},
-        /* 49029  1994 */ {0x0044, 0x8801},
-        /* 49054  1995 */ {0x0080, 0x8800},
-        /* 49077  1996 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49101  1997 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49125  1998 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 49151  1999 */ {0x0008, 0x8802},
-        /* 49176  2000 */ {0x0045, 0x8801},
-        /* 49201  2001 */ {0x0020, 0x8800},
-        /* 49224  2002 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49248  2003 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49272  2004 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 49298  2005 */ {0x0008, 0x8802},
-        /* 49323  2006 */ {0x0046, 0x8801},
-        /* 49348  2007 */ {0x0020, 0x8800},
-        /* 49371  2008 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49395  2009 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49419  2010 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 49445  2011 */ {0x0008, 0x8802},
-        /* 49470  2012 */ {0x0047, 0x8801},
-        /* 49495  2013 */ {0x0080, 0x8800},
-        /* 49518  2014 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49542  2015 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49566  2016 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 49592  2017 */ {0x0008, 0x8802},
-        /* 49617  2018 */ {0x0048, 0x8801},
-        /* 49642  2019 */ {0x004c, 0x8800},
-        /* 49665  2020 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49689  2021 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49713  2022 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 49739  2023 */ {0x0008, 0x8802},
-        /* 49764  2024 */ {0x0049, 0x8801},
-        /* 49789  2025 */ {0x0084, 0x8800},
-        /* 49812  2026 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49836  2027 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49860  2028 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 49886  2029 */ {0x0008, 0x8802},
-        /* 49911  2030 */ {0x004a, 0x8801},
-        /* 49936  2031 */ {0x0084, 0x8800},
-        /* 49959  2032 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 49983  2033 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 50007  2034 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 50033  2035 */ {0x0008, 0x8802},
-        /* 50058  2036 */ {0x004b, 0x8801},
-        /* 50083  2037 */ {0x0084, 0x8800},
-        /* 50106  2038 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
+        {0x00c0, 0x8804},       /* SSI slave addr */
+        {0x0008, 0x8802},       /* 375 Khz SSI clock */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},       /* 375 Khz SSI clock */
+        {0x0012, 0x8801},       /* SSI reg addr */
+        {0x0080, 0x8800},       /* SSI data to write */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},       /* 375 Khz SSI clock */
+        {0x0012, 0x8801},       /* SSI reg addr */
+        {0x0000, 0x8800},       /* SSI data to write */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},       /* 375 Khz SSI clock */
+        {0x0011, 0x8801},       /* SSI reg addr */
+        {0x0040, 0x8800},       /* SSI data to write */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0013, 0x8801},
+        {0x0000, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0014, 0x8801},
+        {0x0000, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0015, 0x8801},
+        {0x0001, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0016, 0x8801},
+        {0x0003, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0017, 0x8801},
+        {0x0036, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0018, 0x8801},
+        {0x00ec, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x001a, 0x8801},
+        {0x0094, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x001b, 0x8801},
+        {0x0000, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0027, 0x8801},
+        {0x00a2, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0028, 0x8801},
+        {0x0040, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x002a, 0x8801},
+        {0x0084, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00 */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x002b, 0x8801},
+        {0x00a8, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x002c, 0x8801},
+        {0x00fe, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x002d, 0x8801},
+        {0x0003, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0038, 0x8801},
+        {0x0083, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0033, 0x8801},
+        {0x0081, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0034, 0x8801},
+        {0x004a, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0039, 0x8801},
+        {0x0000, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0010, 0x8801},
+        {0x00a8, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0006, 0x8801},
+        {0x0058, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00 */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0000, 0x8801},
+        {0x0004, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0040, 0x8801},
+        {0x0080, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0041, 0x8801},
+        {0x000c, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0042, 0x8801},
+        {0x000c, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0043, 0x8801},
+        {0x0028, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0044, 0x8801},
+        {0x0080, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0045, 0x8801},
+        {0x0020, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0046, 0x8801},
+        {0x0020, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0047, 0x8801},
+        {0x0080, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0048, 0x8801},
+        {0x004c, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x0049, 0x8801},
+        {0x0084, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x004a, 0x8801},
+        {0x0084, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x0008, 0x8802},
+        {0x004b, 0x8801},
+        {0x0084, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
         /* --------------------------------------- */
-        /* 50132  2039 */ {0x0012, 0x8700},
-        /* Clock speed 48Mhz/(2+2)/2= 6 Mhz */
-        /* 50157  2040 */ {0x0000, 0x8701},
-        /* CKx1 clock delay adj */
-        /* 50182  2041 */ {0x0000, 0x8701},
-        /* CKx1 clock delay adj */
-        /* 50207  2042 */ {0x0001, 0x870c},
-        /* CKOx2 output */
+        {0x0012, 0x8700},       /* Clock speed 48Mhz/(2+2)/2= 6 Mhz */
+        {0x0000, 0x8701},       /* CKx1 clock delay adj */
+        {0x0000, 0x8701},       /* CKx1 clock delay adj */
+        {0x0001, 0x870c},       /* CKOx2 output */
         /* --------------------------------------- */
-        /* 50232  2043 */ {0x0080, 0x8600},
-        /* Line memory read counter (L) */
-        /* 50257  2044 */ {0x0001, 0x8606},
-        /* reserved */
-        /* 50282  2045 */ {0x0064, 0x8607},
-        /* Line memory read counter (H) 0x6480=25,728 */
-        /* 50307  2046 */ {0x002a, 0x8601},
-        /* CDSP sharp interpolation mode,
+        {0x0080, 0x8600},       /* Line memory read counter (L) */
+        {0x0001, 0x8606},       /* reserved */
+        {0x0064, 0x8607},       /* Line memory read counter (H) 0x6480=25,728 */
+        {0x002a, 0x8601},       /* CDSP sharp interpolation mode,
          *                      line sel for color sep, edge enhance enab */
-        /* 50332  2047 */ {0x0000, 0x8602},
-        /* optical black level for user settng = 0 */
-        /* 50357  2048 */ {0x0080, 0x8600},
-        /* Line memory read counter (L) */
-        /* 50382  2049 */ {0x000a, 0x8603},
-        /* optical black level calc mode: auto; optical black offset = 10 */
-        /* 50407  2050 */ {0x00df, 0x865b},
-        /* Horiz offset for valid pixels (L)=0xdf */
-        /* 50432  2051 */ {0x0012, 0x865c},
-        /* Vert offset for valid lines (L)=0x12 */
+        {0x0000, 0x8602},       /* optical black level for user settng = 0 */
+        {0x0080, 0x8600},       /* Line memory read counter (L) */
+        {0x000a, 0x8603},       /* optical black level calc mode:
+                                 * auto; optical black offset = 10 */
+        {0x00df, 0x865b},       /* Horiz offset for valid pixels (L)=0xdf */
+        {0x0012, 0x865c},       /* Vert offset for valid lines (L)=0x12 */
 
 /* The following two lines seem to be the "wrong" resolution. */
 /* But perhaps these indicate the actual size of the sensor */
 /* rather than the size of the current video mode. */
-        /* 50457  2052 */ {0x0058, 0x865d},
-        /* Horiz valid pixels (*4) (L) = 352 */
-        /* 50482  2053 */ {0x0048, 0x865e},
-        /* Vert valid lines (*4) (L) = 288 */
-
-        /* 50507  2054 */ {0x0015, 0x8608},
-        /* A11 Coef ... */
-        /* 50532  2055 */ {0x0030, 0x8609},
-        /* 50557  2056 */ {0x00fb, 0x860a},
-        /* 50582  2057 */ {0x003e, 0x860b},
-        /* 50607  2058 */ {0x00ce, 0x860c},
-        /* 50632  2059 */ {0x00f4, 0x860d},
-        /* 50657  2060 */ {0x00eb, 0x860e},
-        /* 50682  2061 */ {0x00dc, 0x860f},
-        /* 50707  2062 */ {0x0039, 0x8610},
-        /* 50732  2063 */ {0x0001, 0x8611},
-        /* R offset for white balance ... */
-        /* 50757  2064 */ {0x0000, 0x8612},
-        /* 50782  2065 */ {0x0001, 0x8613},
-        /* 50807  2066 */ {0x0000, 0x8614},
-        /* 50832  2067 */ {0x005b, 0x8651},
-        /* R gain for white balance ... */
-        /* 50857  2068 */ {0x0040, 0x8652},
-        /* 50882  2069 */ {0x0060, 0x8653},
-        /* 50907  2070 */ {0x0040, 0x8654},
-        /* 50932  2071 */ {0x0000, 0x8655},
-        /* 50957  2072 */ {0x0001, 0x863f},
-        /* Fixed gamma correction enable, USB control,
-         *                       lum filter disable, lum noise clip disable */
-        /* 50982  2073 */ {0x00a1, 0x8656},
-        /* Window1 size 256x256, Windows2 size 64x64,
-         *               gamma look-up disable, new edge enhancement enable */
-        /* 51007  2074 */ {0x0018, 0x8657},
-        /* Edge gain high thresh */
-        /* 51032  2075 */ {0x0020, 0x8658},
-        /* Edge gain low thresh */
-        /* 51057  2076 */ {0x000a, 0x8659},
-        /* Edge bandwidth high threshold */
-        /* 51082  2077 */ {0x0005, 0x865a},
-        /* Edge bandwidth low threshold */
+        {0x0058, 0x865d},       /* Horiz valid pixels (*4) (L) = 352 */
+        {0x0048, 0x865e},       /* Vert valid lines (*4) (L) = 288 */
+
+        {0x0015, 0x8608},       /* A11 Coef ... */
+        {0x0030, 0x8609},
+        {0x00fb, 0x860a},
+        {0x003e, 0x860b},
+        {0x00ce, 0x860c},
+        {0x00f4, 0x860d},
+        {0x00eb, 0x860e},
+        {0x00dc, 0x860f},
+        {0x0039, 0x8610},
+        {0x0001, 0x8611},       /* R offset for white balance ... */
+        {0x0000, 0x8612},
+        {0x0001, 0x8613},
+        {0x0000, 0x8614},
+        {0x005b, 0x8651},       /* R gain for white balance ... */
+        {0x0040, 0x8652},
+        {0x0060, 0x8653},
+        {0x0040, 0x8654},
+        {0x0000, 0x8655},
+        {0x0001, 0x863f},       /* Fixed gamma correction enable, USB control,
+                                 * lum filter disable, lum noise clip disable */
+        {0x00a1, 0x8656},       /* Window1 size 256x256, Windows2 size 64x64,
+                                 * gamma look-up disable,
+                                 * new edge enhancement enable */
+        {0x0018, 0x8657},       /* Edge gain high thresh */
+        {0x0020, 0x8658},       /* Edge gain low thresh */
+        {0x000a, 0x8659},       /* Edge bandwidth high threshold */
+        {0x0005, 0x865a},       /* Edge bandwidth low threshold */
         /* -------------------------------- */
-        /* 51107  2078 */ {0x0030, 0x8112},
-        /* Video drop enable, ISO streaming enable */
-        /* 51130  2079 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 51154  2080 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 51180  2081 */ {0xa908, 0x8802},
-        /* 51205  2082 */ {0x0034, 0x8801},
-        /* SSI reg addr */
-        /* 51230  2083 */ {0x00ca, 0x8800},
+        {0x0030, 0x8112},       /* Video drop enable, ISO streaming enable */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0xa908, 0x8802},
+        {0x0034, 0x8801},       /* SSI reg addr */
+        {0x00ca, 0x8800},
         /* SSI data to write */
-        /* 51253  2084 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 51277  2085 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 51301  2086 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 51327  2087 */ {0x1f08, 0x8802},
-        /* 51352  2088 */ {0x0006, 0x8801},
-        /* 51377  2089 */ {0x0080, 0x8800},
-        /* 51400  2090 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0x1f08, 0x8802},
+        {0x0006, 0x8801},
+        {0x0080, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
 /* ----- Read back coefs we wrote earlier. */
-        /* 51424  2091 */ /* READ { 0, 0x0000, 0x8608 } -> 0000: 15  */
-        /* 51448  2092 */ /* READ { 0, 0x0000, 0x8609 } -> 0000: 30  */
-        /* 51472  2093 */ /* READ { 0, 0x0000, 0x860a } -> 0000: fb  */
-        /* 51496  2094 */ /* READ { 0, 0x0000, 0x860b } -> 0000: 3e  */
-        /* 51520  2095 */ /* READ { 0, 0x0000, 0x860c } -> 0000: ce  */
-        /* 51544  2096 */ /* READ { 0, 0x0000, 0x860d } -> 0000: f4  */
-        /* 51568  2097 */ /* READ { 0, 0x0000, 0x860e } -> 0000: eb  */
-        /* 51592  2098 */ /* READ { 0, 0x0000, 0x860f } -> 0000: dc  */
-        /* 51616  2099 */ /* READ { 0, 0x0000, 0x8610 } -> 0000: 39  */
-        /* 51640  2100 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 51664  2101 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 08  */
-        /* 51690  2102 */ {0xb008, 0x8802},
-        /* 51715  2103 */ {0x0006, 0x8801},
-        /* 51740  2104 */ {0x007d, 0x8800},
-        /* 51763  2105 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0000, 0x8608 } -> 0000: 15  */
+        /* READ { 0x0000, 0x8609 } -> 0000: 30  */
+        /* READ { 0x0000, 0x860a } -> 0000: fb  */
+        /* READ { 0x0000, 0x860b } -> 0000: 3e  */
+        /* READ { 0x0000, 0x860c } -> 0000: ce  */
+        /* READ { 0x0000, 0x860d } -> 0000: f4  */
+        /* READ { 0x0000, 0x860e } -> 0000: eb  */
+        /* READ { 0x0000, 0x860f } -> 0000: dc  */
+        /* READ { 0x0000, 0x8610 } -> 0000: 39  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 08  */
+        {0xb008, 0x8802},
+        {0x0006, 0x8801},
+        {0x007d, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
 
         /* This chunk is seemingly redundant with */
         /* earlier commands (A11 Coef...), but if I disable it, */
         /* the image appears too dark.  Maybe there was some kind of */
         /* reset since the earlier commands, so this is necessary again. */
-        /* 51789  2106 */ {0x0015, 0x8608},
-        /* 51814  2107 */ {0x0030, 0x8609},
-        /* 51839  2108 */ {0xfffb, 0x860a},
-        /* 51864  2109 */ {0x003e, 0x860b},
-        /* 51889  2110 */ {0xffce, 0x860c},
-        /* 51914  2111 */ {0xfff4, 0x860d},
-        /* 51939  2112 */ {0xffeb, 0x860e},
-        /* 51964  2113 */ {0xffdc, 0x860f},
-        /* 51989  2114 */ {0x0039, 0x8610},
-        /* 52014  2115 */ {0x0018, 0x8657},
-
-        /* 52039  2116 */ {0x0000, 0x8508},
-        /* Disable compression. */
+        {0x0015, 0x8608},
+        {0x0030, 0x8609},
+        {0xfffb, 0x860a},
+        {0x003e, 0x860b},
+        {0xffce, 0x860c},
+        {0xfff4, 0x860d},
+        {0xffeb, 0x860e},
+        {0xffdc, 0x860f},
+        {0x0039, 0x8610},
+        {0x0018, 0x8657},
+
+        {0x0000, 0x8508},       /* Disable compression. */
         /* Previous line was:
-         * 52039  2116 *  { 0, 0x0021, 0x8508 },  * Enable compression. */
-        /* 52064  2117 */ {0x0032, 0x850b},
-        /* compression stuff */
-        /* 52089  2118 */ {0x0003, 0x8509},
-        /* compression stuff */
-        /* 52114  2119 */ {0x0011, 0x850a},
-        /* compression stuff */
-        /* 52139  2120 */ {0x0021, 0x850d},
-        /* compression stuff */
-        /* 52164  2121 */ {0x0010, 0x850c},
-        /* compression stuff */
-        /* 52189  2122 */ {0x0003, 0x8500},
-        /* *** Video mode: 160x120 */
-        /* 52214  2123 */ {0x0001, 0x8501},
-        /* Hardware-dominated snap control */
-        /* 52239  2124 */ {0x0061, 0x8656},
-        /* Window1 size 128x128, Windows2 size 128x128,
-         *              gamma look-up disable, new edge enhancement enable */
-        /* 52264  2125 */ {0x0018, 0x8617},
-        /* Window1 start X (*2) */
-        /* 52289  2126 */ {0x0008, 0x8618},
-        /* Window1 start Y (*2) */
-        /* 52314  2127 */ {0x0061, 0x8656},
-        /* Window1 size 128x128, Windows2 size 128x128,
-         *              gamma look-up disable, new edge enhancement enable */
-        /* 52339  2128 */ {0x0058, 0x8619},
-        /* Window2 start X (*2) */
-        /* 52364  2129 */ {0x0008, 0x861a},
-        /* Window2 start Y (*2) */
-        /* 52389  2130 */ {0x00ff, 0x8615},
-        /* High lum thresh for white balance */
-        /* 52414  2131 */ {0x0000, 0x8616},
-        /* Low lum thresh for white balance */
-        /* 52439  2132 */ {0x0012, 0x8700},
-        /* Clock speed 48Mhz/(2+2)/2= 6 Mhz */
-        /* 52464  2133 */ {0x0012, 0x8700},
-        /* Clock speed 48Mhz/(2+2)/2= 6 Mhz */
-        /* 52487  2134 */ /* READ { 0, 0x0000, 0x8656 } -> 0000: 61  */
-        /* 52513  2135 */ {0x0028, 0x8802},
-        /* 375 Khz SSI clock, SSI r/w sync with VSYNC */
-        /* 52536  2136 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 52560  2137 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 28  */
-        /* 52586  2138 */ {0x1f28, 0x8802},
-        /* 375 Khz SSI clock, SSI r/w sync with VSYNC */
-        /* 52611  2139 */ {0x0010, 0x8801},
-        /* SSI reg addr */
-        /* 52636  2140 */ {0x003e, 0x8800},
-        /* SSI data to write */
-        /* 52659  2141 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 52685  2142 */ {0x0028, 0x8802},
-        /* 52708  2143 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 52732  2144 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 28  */
-        /* 52758  2145 */ {0x1f28, 0x8802},
-        /* 52783  2146 */ {0x0000, 0x8801},
-        /* 52808  2147 */ {0x001f, 0x8800},
-        /* 52831  2148 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 52857  2149 */ {0x0001, 0x8602},
-        /* optical black level for user settning = 1 */
+        {0x0021, 0x8508},        * Enable compression. */
+        {0x0032, 0x850b},       /* compression stuff */
+        {0x0003, 0x8509},       /* compression stuff */
+        {0x0011, 0x850a},       /* compression stuff */
+        {0x0021, 0x850d},       /* compression stuff */
+        {0x0010, 0x850c},       /* compression stuff */
+        {0x0003, 0x8500},       /* *** Video mode: 160x120 */
+        {0x0001, 0x8501},       /* Hardware-dominated snap control */
+        {0x0061, 0x8656},       /* Window1 size 128x128, Windows2 size 128x128,
+                                 * gamma look-up disable,
+                                 * new edge enhancement enable */
+        {0x0018, 0x8617},       /* Window1 start X (*2) */
+        {0x0008, 0x8618},       /* Window1 start Y (*2) */
+        {0x0061, 0x8656},       /* Window1 size 128x128, Windows2 size 128x128,
+                                 * gamma look-up disable,
+                                 * new edge enhancement enable */
+        {0x0058, 0x8619},       /* Window2 start X (*2) */
+        {0x0008, 0x861a},       /* Window2 start Y (*2) */
+        {0x00ff, 0x8615},       /* High lum thresh for white balance */
+        {0x0000, 0x8616},       /* Low lum thresh for white balance */
+        {0x0012, 0x8700},       /* Clock speed 48Mhz/(2+2)/2= 6 Mhz */
+        {0x0012, 0x8700},       /* Clock speed 48Mhz/(2+2)/2= 6 Mhz */
+        /* READ { 0x0000, 0x8656 } -> 0000: 61  */
+        {0x0028, 0x8802},    /* 375 Khz SSI clock, SSI r/w sync with VSYNC */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 28  */
+        {0x1f28, 0x8802},    /* 375 Khz SSI clock, SSI r/w sync with VSYNC */
+        {0x0010, 0x8801},       /* SSI reg addr */
+        {0x003e, 0x8800},       /* SSI data to write */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        {0x0028, 0x8802},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 28  */
+        {0x1f28, 0x8802},
+        {0x0000, 0x8801},
+        {0x001f, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        {0x0001, 0x8602},    /* optical black level for user settning = 1 */
 
         /* Original: */
-        /* 52882  2150 */ {0x0023, 0x8700},
-        /* Clock speed 48Mhz/(3+2)/4= 2.4 Mhz */
-        /* 52907  2151 */ {0x000f, 0x8602},
-        /* optical black level for user settning = 15 */
-
-        /* 52932  2152 */ {0x0028, 0x8802},
-        /* 52955  2153 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 52979  2154 */ /* READ { 0, 0x0001, 0x8802 } -> 0000: 28  */
-        /* 53005  2155 */ {0x1f28, 0x8802},
-        /* 53030  2156 */ {0x0010, 0x8801},
-        /* 53055  2157 */ {0x007b, 0x8800},
-        /* 53078  2158 */ /* READ { 0, 0x0001, 0x8803 } -> 0000: 00  */
-        /* 53104  2159 */ {0x002f, 0x8651},
-        /* R gain for white balance ... */
-        /* 53129  2160 */ {0x0080, 0x8653},
-        /* 53152  2161 */ /* READ { 0, 0x0000, 0x8655 } -> 0000: 00  */
-        /* 53178  2162 */ {0x0000, 0x8655},
-
-        /* 53203  2163 */ {0x0030, 0x8112},
-        /* Video drop enable, ISO streaming enable */
-        /* 53228  2164 */ {0x0020, 0x8112},
-        /* Video drop enable, ISO streaming disable */
-        /* 53252  2165 */
-             /* UNKNOWN DIRECTION (URB_FUNCTION_SELECT_INTERFACE: (ALT=0) ) */
+        {0x0023, 0x8700},       /* Clock speed 48Mhz/(3+2)/4= 2.4 Mhz */
+        {0x000f, 0x8602},    /* optical black level for user settning = 15 */
+
+        {0x0028, 0x8802},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 28  */
+        {0x1f28, 0x8802},
+        {0x0010, 0x8801},
+        {0x007b, 0x8800},
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        {0x002f, 0x8651},       /* R gain for white balance ... */
+        {0x0080, 0x8653},
+        /* READ { 0x0000, 0x8655 } -> 0000: 00  */
+        {0x0000, 0x8655},
+
+        {0x0030, 0x8112},       /* Video drop enable, ISO streaming enable */
+        {0x0020, 0x8112},       /* Video drop enable, ISO streaming disable */
+        /* UNKNOWN DIRECTION (URB_FUNCTION_SELECT_INTERFACE: (ALT=0) ) */
         {}
 };
 
@@ -592,27 +506,27 @@ static const u16 spca508_init_data[][2] =
  * Initialization data for Intel EasyPC Camera CS110
  */
 static const u16 spca508cs110_init_data[][2] = {
-        {0x0000, 0x870b}, /* Reset CTL3 */
-        {0x0003, 0x8111}, /* Soft Reset compression, memory, TG & CDSP */
-        {0x0000, 0x8111}, /* Normal operation on reset */
+        {0x0000, 0x870b},       /* Reset CTL3 */
+        {0x0003, 0x8111},       /* Soft Reset compression, memory, TG & CDSP */
+        {0x0000, 0x8111},       /* Normal operation on reset */
         {0x0090, 0x8110},
                  /* External Clock 2x & Synchronous Serial Interface Output */
-        {0x0020, 0x8112}, /* Video Drop packet enable */
-        {0x0000, 0x8114}, /* Software GPIO output data */
+        {0x0020, 0x8112},       /* Video Drop packet enable */
+        {0x0000, 0x8114},       /* Software GPIO output data */
         {0x0001, 0x8114},
         {0x0001, 0x8114},
         {0x0001, 0x8114},
         {0x0003, 0x8114},
 
         /* Initial sequence Synchronous Serial Interface */
-        {0x000f, 0x8402}, /* Memory bank Address */
-        {0x0000, 0x8403}, /* Memory bank Address */
-        {0x00ba, 0x8804}, /* SSI Slave address */
-        {0x0010, 0x8802}, /* 93.75kHz SSI Clock Two DataByte */
-        {0x0010, 0x8802}, /* 93.75kHz SSI Clock two DataByte */
+        {0x000f, 0x8402},       /* Memory bank Address */
+        {0x0000, 0x8403},       /* Memory bank Address */
+        {0x00ba, 0x8804},       /* SSI Slave address */
+        {0x0010, 0x8802},       /* 93.75kHz SSI Clock Two DataByte */
+        {0x0010, 0x8802},       /* 93.75kHz SSI Clock two DataByte */
 
         {0x0001, 0x8801},
-        {0x000a, 0x8805},/* a - NWG: Dunno what this is about */
+        {0x000a, 0x8805},       /* a - NWG: Dunno what this is about */
         {0x0000, 0x8800},
         {0x0010, 0x8802},
 
@@ -646,459 +560,459 @@ static const u16 spca508cs110_init_data[][2] = {
         {0x0000, 0x8800},
         {0x0010, 0x8802},
 
-        {0x0002, 0x8704}, /* External input CKIx1 */
-        {0x0001, 0x8606}, /* 1 Line memory Read Counter (H) Result: (d)410 */
-        {0x009a, 0x8600}, /* Line memory Read Counter (L) */
-        {0x0001, 0x865b}, /* 1 Horizontal Offset for Valid Pixel(L) */
-        {0x0003, 0x865c}, /* 3 Vertical Offset for Valid Lines(L) */
-        {0x0058, 0x865d}, /* 58 Horizontal Valid Pixel Window(L) */
+        {0x0002, 0x8704},       /* External input CKIx1 */
+        {0x0001, 0x8606},    /* 1 Line memory Read Counter (H) Result: (d)410 */
+        {0x009a, 0x8600},       /* Line memory Read Counter (L) */
+        {0x0001, 0x865b},       /* 1 Horizontal Offset for Valid Pixel(L) */
+        {0x0003, 0x865c},       /* 3 Vertical Offset for Valid Lines(L) */
+        {0x0058, 0x865d},       /* 58 Horizontal Valid Pixel Window(L) */
 
-        {0x0006, 0x8660}, /* Nibble data + input order */
+        {0x0006, 0x8660},       /* Nibble data + input order */
 
-        {0x000a, 0x8602}, /* Optical black level set to 0x0a */
-/* 1945 */ {0x0000, 0x8603}, /* Optical black level Offset */
+        {0x000a, 0x8602},       /* Optical black level set to 0x0a */
+        {0x0000, 0x8603},       /* Optical black level Offset */
 
-/* 1962 *  {0, 0x0000, 0x8611},  * 0 R  Offset for white Balance */
-/* 1963 *  {0, 0x0000, 0x8612},  * 1 Gr Offset for white Balance */
-/* 1964 *  {0, 0x0000, 0x8613},  * 1f B  Offset for white Balance */
-/* 1965 *  {0, 0x0000, 0x8614},  * f0 Gb Offset for white Balance */
+/*      {0x0000, 0x8611},        * 0 R  Offset for white Balance */
+/*      {0x0000, 0x8612},        * 1 Gr Offset for white Balance */
+/*      {0x0000, 0x8613},        * 1f B  Offset for white Balance */
+/*      {0x0000, 0x8614},        * f0 Gb Offset for white Balance */
 
-        {0x0040, 0x8651}, /* 2b BLUE gain for white balance  good at all 60 */
-        {0x0030, 0x8652}, /* 41 Gr Gain for white Balance (L) */
-        {0x0035, 0x8653}, /* 26 RED gain for white balance */
-        {0x0035, 0x8654}, /* 40Gb Gain for white Balance (L) */
+        {0x0040, 0x8651},   /* 2b BLUE gain for white balance  good at all 60 */
+        {0x0030, 0x8652},       /* 41 Gr Gain for white Balance (L) */
+        {0x0035, 0x8653},       /* 26 RED gain for white balance */
+        {0x0035, 0x8654},       /* 40Gb Gain for white Balance (L) */
         {0x0041, 0x863f},
               /* Fixed Gamma correction enabled (makes colours look better) */
 
-/* 2422 */ {0x0000, 0x8655},
-        /* High bits for white balance*****brightness control*** */
+        {0x0000, 0x8655},
+                /* High bits for white balance*****brightness control*** */
         {}
 };
 
 static const u16 spca508_sightcam_init_data[][2] = {
 /* This line seems to setup the frame/canvas */
-        /*368  */ {0x000f, 0x8402},
+        {0x000f, 0x8402},
 
 /* Theese 6 lines are needed to startup the webcam */
-        /*398  */ {0x0090, 0x8110},
-        /*399  */ {0x0001, 0x8114},
-        /*400  */ {0x0001, 0x8114},
-        /*401  */ {0x0001, 0x8114},
-        /*402  */ {0x0003, 0x8114},
-        /*403  */ {0x0080, 0x8804},
+        {0x0090, 0x8110},
+        {0x0001, 0x8114},
+        {0x0001, 0x8114},
+        {0x0001, 0x8114},
+        {0x0003, 0x8114},
+        {0x0080, 0x8804},
 
 /* This part seems to make the pictures darker? (autobrightness?) */
-        /*436  */ {0x0001, 0x8801},
-        /*437  */ {0x0004, 0x8800},
-        /*439  */ {0x0003, 0x8801},
-        /*440  */ {0x00e0, 0x8800},
-        /*442  */ {0x0004, 0x8801},
-        /*443  */ {0x00b4, 0x8800},
-        /*445  */ {0x0005, 0x8801},
-        /*446  */ {0x0000, 0x8800},
-
-        /*448  */ {0x0006, 0x8801},
-        /*449  */ {0x00e0, 0x8800},
-        /*451  */ {0x0007, 0x8801},
-        /*452  */ {0x000c, 0x8800},
+        {0x0001, 0x8801},
+        {0x0004, 0x8800},
+        {0x0003, 0x8801},
+        {0x00e0, 0x8800},
+        {0x0004, 0x8801},
+        {0x00b4, 0x8800},
+        {0x0005, 0x8801},
+        {0x0000, 0x8800},
+
+        {0x0006, 0x8801},
+        {0x00e0, 0x8800},
+        {0x0007, 0x8801},
+        {0x000c, 0x8800},
 
 /* This section is just needed, it probably
  * does something like the previous section,
  * but the cam won't start if it's not included.
  */
-        /*484  */ {0x0014, 0x8801},
-        /*485  */ {0x0008, 0x8800},
-        /*487  */ {0x0015, 0x8801},
-        /*488  */ {0x0067, 0x8800},
-        /*490  */ {0x0016, 0x8801},
-        /*491  */ {0x0000, 0x8800},
-        /*493  */ {0x0017, 0x8801},
-        /*494  */ {0x0020, 0x8800},
-        /*496  */ {0x0018, 0x8801},
-        /*497  */ {0x0044, 0x8800},
+        {0x0014, 0x8801},
+        {0x0008, 0x8800},
+        {0x0015, 0x8801},
+        {0x0067, 0x8800},
+        {0x0016, 0x8801},
+        {0x0000, 0x8800},
+        {0x0017, 0x8801},
+        {0x0020, 0x8800},
+        {0x0018, 0x8801},
+        {0x0044, 0x8800},
 
 /* Makes the picture darker - and the
  * cam won't start if not included
  */
-        /*505  */ {0x001e, 0x8801},
-        /*506  */ {0x00ea, 0x8800},
-        /*508  */ {0x001f, 0x8801},
-        /*509  */ {0x0001, 0x8800},
-        /*511  */ {0x0003, 0x8801},
-        /*512  */ {0x00e0, 0x8800},
+        {0x001e, 0x8801},
+        {0x00ea, 0x8800},
+        {0x001f, 0x8801},
+        {0x0001, 0x8800},
+        {0x0003, 0x8801},
+        {0x00e0, 0x8800},
 
 /* seems to place the colors ontop of each other #1 */
-        /*517  */ {0x0006, 0x8704},
-        /*518  */ {0x0001, 0x870c},
-        /*519  */ {0x0016, 0x8600},
-        /*520  */ {0x0002, 0x8606},
+        {0x0006, 0x8704},
+        {0x0001, 0x870c},
+        {0x0016, 0x8600},
+        {0x0002, 0x8606},
 
 /* if not included the pictures becomes _very_ dark */
-        /*521  */ {0x0064, 0x8607},
-        /*522  */ {0x003a, 0x8601},
-        /*523  */ {0x0000, 0x8602},
+        {0x0064, 0x8607},
+        {0x003a, 0x8601},
+        {0x0000, 0x8602},
 
 /* seems to place the colors ontop of each other #2 */
-        /*524  */ {0x0016, 0x8600},
-        /*525  */ {0x0018, 0x8617},
-        /*526  */ {0x0008, 0x8618},
-        /*527  */ {0x00a1, 0x8656},
+        {0x0016, 0x8600},
+        {0x0018, 0x8617},
+        {0x0008, 0x8618},
+        {0x00a1, 0x8656},
 
 /* webcam won't start if not included */
-        /*528  */ {0x0007, 0x865b},
-        /*529  */ {0x0001, 0x865c},
-        /*530  */ {0x0058, 0x865d},
-        /*531  */ {0x0048, 0x865e},
+        {0x0007, 0x865b},
+        {0x0001, 0x865c},
+        {0x0058, 0x865d},
+        {0x0048, 0x865e},
 
 /* adjusts the colors */
-        /*541  */ {0x0049, 0x8651},
-        /*542  */ {0x0040, 0x8652},
-        /*543  */ {0x004c, 0x8653},
-        /*544  */ {0x0040, 0x8654},
+        {0x0049, 0x8651},
+        {0x0040, 0x8652},
+        {0x004c, 0x8653},
+        {0x0040, 0x8654},
         {}
 };
 
 static const u16 spca508_sightcam2_init_data[][2] = {
-/* 35 */ {0x0020, 0x8112},
-
-/* 36 */ {0x000f, 0x8402},
-/* 37 */ {0x0000, 0x8403},
-
-/* 38 */ {0x0008, 0x8201},
-/* 39 */ {0x0008, 0x8200},
-/* 40 */ {0x0001, 0x8200},
-/* 43 */ {0x0009, 0x8201},
-/* 44 */ {0x0008, 0x8200},
-/* 45 */ {0x0001, 0x8200},
-/* 48 */ {0x000a, 0x8201},
-/* 49 */ {0x0008, 0x8200},
-/* 50 */ {0x0001, 0x8200},
-/* 53 */ {0x000b, 0x8201},
-/* 54 */ {0x0008, 0x8200},
-/* 55 */ {0x0001, 0x8200},
-/* 58 */ {0x000c, 0x8201},
-/* 59 */ {0x0008, 0x8200},
-/* 60 */ {0x0001, 0x8200},
-/* 63 */ {0x000d, 0x8201},
-/* 64 */ {0x0008, 0x8200},
-/* 65 */ {0x0001, 0x8200},
-/* 68 */ {0x000e, 0x8201},
-/* 69 */ {0x0008, 0x8200},
-/* 70 */ {0x0001, 0x8200},
-/* 73 */ {0x0007, 0x8201},
-/* 74 */ {0x0008, 0x8200},
-/* 75 */ {0x0001, 0x8200},
-/* 78 */ {0x000f, 0x8201},
-/* 79 */ {0x0008, 0x8200},
-/* 80 */ {0x0001, 0x8200},
-
-/* 84 */ {0x0018, 0x8660},
-/* 85 */ {0x0010, 0x8201},
-
-/* 86 */ {0x0008, 0x8200},
-/* 87 */ {0x0001, 0x8200},
-/* 90 */ {0x0011, 0x8201},
-/* 91 */ {0x0008, 0x8200},
-/* 92 */ {0x0001, 0x8200},
-
-/* 95 */ {0x0000, 0x86b0},
-/* 96 */ {0x0034, 0x86b1},
-/* 97 */ {0x0000, 0x86b2},
-/* 98 */ {0x0049, 0x86b3},
-/* 99 */ {0x0000, 0x86b4},
-/* 100 */ {0x0000, 0x86b4},
-
-/* 101 */ {0x0012, 0x8201},
-/* 102 */ {0x0008, 0x8200},
-/* 103 */ {0x0001, 0x8200},
-/* 106 */ {0x0013, 0x8201},
-/* 107 */ {0x0008, 0x8200},
-/* 108 */ {0x0001, 0x8200},
-
-/* 111 */ {0x0001, 0x86b0},
-/* 112 */ {0x00aa, 0x86b1},
-/* 113 */ {0x0000, 0x86b2},
-/* 114 */ {0x00e4, 0x86b3},
-/* 115 */ {0x0000, 0x86b4},
-/* 116 */ {0x0000, 0x86b4},
-
-/* 118 */ {0x0018, 0x8660},
-
-/* 119 */ {0x0090, 0x8110},
-/* 120 */ {0x0001, 0x8114},
-/* 121 */ {0x0001, 0x8114},
-/* 122 */ {0x0001, 0x8114},
-/* 123 */ {0x0003, 0x8114},
-
-/* 124 */ {0x0080, 0x8804},
-/* 157 */ {0x0003, 0x8801},
-/* 158 */ {0x0012, 0x8800},
-/* 160 */ {0x0004, 0x8801},
-/* 161 */ {0x0005, 0x8800},
-/* 163 */ {0x0005, 0x8801},
-/* 164 */ {0x0000, 0x8800},
-/* 166 */ {0x0006, 0x8801},
-/* 167 */ {0x0000, 0x8800},
-/* 169 */ {0x0007, 0x8801},
-/* 170 */ {0x0000, 0x8800},
-/* 172 */ {0x0008, 0x8801},
-/* 173 */ {0x0005, 0x8800},
-/* 175 */ {0x000a, 0x8700},
-/* 176 */ {0x000e, 0x8801},
-/* 177 */ {0x0004, 0x8800},
-/* 179 */ {0x0005, 0x8801},
-/* 180 */ {0x0047, 0x8800},
-/* 182 */ {0x0006, 0x8801},
-/* 183 */ {0x0000, 0x8800},
-/* 185 */ {0x0007, 0x8801},
-/* 186 */ {0x00c0, 0x8800},
-/* 188 */ {0x0008, 0x8801},
-/* 189 */ {0x0003, 0x8800},
-/* 191 */ {0x0013, 0x8801},
-/* 192 */ {0x0001, 0x8800},
-/* 194 */ {0x0009, 0x8801},
-/* 195 */ {0x0000, 0x8800},
-/* 197 */ {0x000a, 0x8801},
-/* 198 */ {0x0000, 0x8800},
-/* 200 */ {0x000b, 0x8801},
-/* 201 */ {0x0000, 0x8800},
-/* 203 */ {0x000c, 0x8801},
-/* 204 */ {0x0000, 0x8800},
-/* 206 */ {0x000e, 0x8801},
-/* 207 */ {0x0004, 0x8800},
-/* 209 */ {0x000f, 0x8801},
-/* 210 */ {0x0000, 0x8800},
-/* 212 */ {0x0010, 0x8801},
-/* 213 */ {0x0006, 0x8800},
-/* 215 */ {0x0011, 0x8801},
-/* 216 */ {0x0006, 0x8800},
-/* 218 */ {0x0012, 0x8801},
-/* 219 */ {0x0000, 0x8800},
-/* 221 */ {0x0013, 0x8801},
-/* 222 */ {0x0001, 0x8800},
-
-/* 224 */ {0x000a, 0x8700},
-/* 225 */ {0x0000, 0x8702},
-/* 226 */ {0x0000, 0x8703},
-/* 227 */ {0x00c2, 0x8704},
-/* 228 */ {0x0001, 0x870c},
-
-/* 229 */ {0x0044, 0x8600},
-/* 230 */ {0x0002, 0x8606},
-/* 231 */ {0x0064, 0x8607},
-/* 232 */ {0x003a, 0x8601},
-/* 233 */ {0x0008, 0x8602},
-/* 234 */ {0x0044, 0x8600},
-/* 235 */ {0x0018, 0x8617},
-/* 236 */ {0x0008, 0x8618},
-/* 237 */ {0x00a1, 0x8656},
-/* 238 */ {0x0004, 0x865b},
-/* 239 */ {0x0002, 0x865c},
-/* 240 */ {0x0058, 0x865d},
-/* 241 */ {0x0048, 0x865e},
-/* 242 */ {0x0012, 0x8608},
-/* 243 */ {0x002c, 0x8609},
-/* 244 */ {0x0002, 0x860a},
-/* 245 */ {0x002c, 0x860b},
-/* 246 */ {0x00db, 0x860c},
-/* 247 */ {0x00f9, 0x860d},
-/* 248 */ {0x00f1, 0x860e},
-/* 249 */ {0x00e3, 0x860f},
-/* 250 */ {0x002c, 0x8610},
-/* 251 */ {0x006c, 0x8651},
-/* 252 */ {0x0041, 0x8652},
-/* 253 */ {0x0059, 0x8653},
-/* 254 */ {0x0040, 0x8654},
-/* 255 */ {0x00fa, 0x8611},
-/* 256 */ {0x00ff, 0x8612},
-/* 257 */ {0x00f8, 0x8613},
-/* 258 */ {0x0000, 0x8614},
-/* 259 */ {0x0001, 0x863f},
-/* 260 */ {0x0000, 0x8640},
-/* 261 */ {0x0026, 0x8641},
-/* 262 */ {0x0045, 0x8642},
-/* 263 */ {0x0060, 0x8643},
-/* 264 */ {0x0075, 0x8644},
-/* 265 */ {0x0088, 0x8645},
-/* 266 */ {0x009b, 0x8646},
-/* 267 */ {0x00b0, 0x8647},
-/* 268 */ {0x00c5, 0x8648},
-/* 269 */ {0x00d2, 0x8649},
-/* 270 */ {0x00dc, 0x864a},
-/* 271 */ {0x00e5, 0x864b},
-/* 272 */ {0x00eb, 0x864c},
-/* 273 */ {0x00f0, 0x864d},
-/* 274 */ {0x00f6, 0x864e},
-/* 275 */ {0x00fa, 0x864f},
-/* 276 */ {0x00ff, 0x8650},
-/* 277 */ {0x0060, 0x8657},
-/* 278 */ {0x0010, 0x8658},
-/* 279 */ {0x0018, 0x8659},
-/* 280 */ {0x0005, 0x865a},
-/* 281 */ {0x0018, 0x8660},
-/* 282 */ {0x0003, 0x8509},
-/* 283 */ {0x0011, 0x850a},
-/* 284 */ {0x0032, 0x850b},
-/* 285 */ {0x0010, 0x850c},
-/* 286 */ {0x0021, 0x850d},
-/* 287 */ {0x0001, 0x8500},
-/* 288 */ {0x0000, 0x8508},
-/* 289 */ {0x0012, 0x8608},
-/* 290 */ {0x002c, 0x8609},
-/* 291 */ {0x0002, 0x860a},
-/* 292 */ {0x0039, 0x860b},
-/* 293 */ {0x00d0, 0x860c},
-/* 294 */ {0x00f7, 0x860d},
-/* 295 */ {0x00ed, 0x860e},
-/* 296 */ {0x00db, 0x860f},
-/* 297 */ {0x0039, 0x8610},
-/* 298 */ {0x0012, 0x8657},
-/* 299 */ {0x000c, 0x8619},
-/* 300 */ {0x0004, 0x861a},
-/* 301 */ {0x00a1, 0x8656},
-/* 302 */ {0x00c8, 0x8615},
-/* 303 */ {0x0032, 0x8616},
-
-/* 306 */ {0x0030, 0x8112},
-/* 313 */ {0x0020, 0x8112},
-/* 314 */ {0x0020, 0x8112},
-/* 315 */ {0x000f, 0x8402},
-/* 316 */ {0x0000, 0x8403},
-
-/* 317 */ {0x0090, 0x8110},
-/* 318 */ {0x0001, 0x8114},
-/* 319 */ {0x0001, 0x8114},
-/* 320 */ {0x0001, 0x8114},
-/* 321 */ {0x0003, 0x8114},
-/* 322 */ {0x0080, 0x8804},
-
-/* 355 */ {0x0003, 0x8801},
-/* 356 */ {0x0012, 0x8800},
-/* 358 */ {0x0004, 0x8801},
-/* 359 */ {0x0005, 0x8800},
-/* 361 */ {0x0005, 0x8801},
-/* 362 */ {0x0047, 0x8800},
-/* 364 */ {0x0006, 0x8801},
-/* 365 */ {0x0000, 0x8800},
-/* 367 */ {0x0007, 0x8801},
-/* 368 */ {0x00c0, 0x8800},
-/* 370 */ {0x0008, 0x8801},
-/* 371 */ {0x0003, 0x8800},
-/* 373 */ {0x000a, 0x8700},
-/* 374 */ {0x000e, 0x8801},
-/* 375 */ {0x0004, 0x8800},
-/* 377 */ {0x0005, 0x8801},
-/* 378 */ {0x0047, 0x8800},
-/* 380 */ {0x0006, 0x8801},
-/* 381 */ {0x0000, 0x8800},
-/* 383 */ {0x0007, 0x8801},
-/* 384 */ {0x00c0, 0x8800},
-/* 386 */ {0x0008, 0x8801},
-/* 387 */ {0x0003, 0x8800},
-/* 389 */ {0x0013, 0x8801},
-/* 390 */ {0x0001, 0x8800},
-/* 392 */ {0x0009, 0x8801},
-/* 393 */ {0x0000, 0x8800},
-/* 395 */ {0x000a, 0x8801},
-/* 396 */ {0x0000, 0x8800},
-/* 398 */ {0x000b, 0x8801},
-/* 399 */ {0x0000, 0x8800},
-/* 401 */ {0x000c, 0x8801},
-/* 402 */ {0x0000, 0x8800},
-/* 404 */ {0x000e, 0x8801},
-/* 405 */ {0x0004, 0x8800},
-/* 407 */ {0x000f, 0x8801},
-/* 408 */ {0x0000, 0x8800},
-/* 410 */ {0x0010, 0x8801},
-/* 411 */ {0x0006, 0x8800},
-/* 413 */ {0x0011, 0x8801},
-/* 414 */ {0x0006, 0x8800},
-/* 416 */ {0x0012, 0x8801},
-/* 417 */ {0x0000, 0x8800},
-/* 419 */ {0x0013, 0x8801},
-/* 420 */ {0x0001, 0x8800},
-/* 422 */ {0x000a, 0x8700},
-/* 423 */ {0x0000, 0x8702},
-/* 424 */ {0x0000, 0x8703},
-/* 425 */ {0x00c2, 0x8704},
-/* 426 */ {0x0001, 0x870c},
-/* 427 */ {0x0044, 0x8600},
-/* 428 */ {0x0002, 0x8606},
-/* 429 */ {0x0064, 0x8607},
-/* 430 */ {0x003a, 0x8601},
-/* 431 */ {0x0008, 0x8602},
-/* 432 */ {0x0044, 0x8600},
-/* 433 */ {0x0018, 0x8617},
-/* 434 */ {0x0008, 0x8618},
-/* 435 */ {0x00a1, 0x8656},
-/* 436 */ {0x0004, 0x865b},
-/* 437 */ {0x0002, 0x865c},
-/* 438 */ {0x0058, 0x865d},
-/* 439 */ {0x0048, 0x865e},
-/* 440 */ {0x0012, 0x8608},
-/* 441 */ {0x002c, 0x8609},
-/* 442 */ {0x0002, 0x860a},
-/* 443 */ {0x002c, 0x860b},
-/* 444 */ {0x00db, 0x860c},
-/* 445 */ {0x00f9, 0x860d},
-/* 446 */ {0x00f1, 0x860e},
-/* 447 */ {0x00e3, 0x860f},
-/* 448 */ {0x002c, 0x8610},
-/* 449 */ {0x006c, 0x8651},
-/* 450 */ {0x0041, 0x8652},
-/* 451 */ {0x0059, 0x8653},
-/* 452 */ {0x0040, 0x8654},
-/* 453 */ {0x00fa, 0x8611},
-/* 454 */ {0x00ff, 0x8612},
-/* 455 */ {0x00f8, 0x8613},
-/* 456 */ {0x0000, 0x8614},
-/* 457 */ {0x0001, 0x863f},
-/* 458 */ {0x0000, 0x8640},
-/* 459 */ {0x0026, 0x8641},
-/* 460 */ {0x0045, 0x8642},
-/* 461 */ {0x0060, 0x8643},
-/* 462 */ {0x0075, 0x8644},
-/* 463 */ {0x0088, 0x8645},
-/* 464 */ {0x009b, 0x8646},
-/* 465 */ {0x00b0, 0x8647},
-/* 466 */ {0x00c5, 0x8648},
-/* 467 */ {0x00d2, 0x8649},
-/* 468 */ {0x00dc, 0x864a},
-/* 469 */ {0x00e5, 0x864b},
-/* 470 */ {0x00eb, 0x864c},
-/* 471 */ {0x00f0, 0x864d},
-/* 472 */ {0x00f6, 0x864e},
-/* 473 */ {0x00fa, 0x864f},
-/* 474 */ {0x00ff, 0x8650},
-/* 475 */ {0x0060, 0x8657},
-/* 476 */ {0x0010, 0x8658},
-/* 477 */ {0x0018, 0x8659},
-/* 478 */ {0x0005, 0x865a},
-/* 479 */ {0x0018, 0x8660},
-/* 480 */ {0x0003, 0x8509},
-/* 481 */ {0x0011, 0x850a},
-/* 482 */ {0x0032, 0x850b},
-/* 483 */ {0x0010, 0x850c},
-/* 484 */ {0x0021, 0x850d},
-/* 485 */ {0x0001, 0x8500},
-/* 486 */ {0x0000, 0x8508},
-
-/* 487 */ {0x0012, 0x8608},
-/* 488 */ {0x002c, 0x8609},
-/* 489 */ {0x0002, 0x860a},
-/* 490 */ {0x0039, 0x860b},
-/* 491 */ {0x00d0, 0x860c},
-/* 492 */ {0x00f7, 0x860d},
-/* 493 */ {0x00ed, 0x860e},
-/* 494 */ {0x00db, 0x860f},
-/* 495 */ {0x0039, 0x8610},
-/* 496 */ {0x0012, 0x8657},
-/* 497 */ {0x0064, 0x8619},
+        {0x0020, 0x8112},
+
+        {0x000f, 0x8402},
+        {0x0000, 0x8403},
+
+        {0x0008, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+        {0x0009, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+        {0x000a, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+        {0x000b, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+        {0x000c, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+        {0x000d, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+        {0x000e, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+        {0x0007, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+        {0x000f, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+
+        {0x0018, 0x8660},
+        {0x0010, 0x8201},
+
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+        {0x0011, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+
+        {0x0000, 0x86b0},
+        {0x0034, 0x86b1},
+        {0x0000, 0x86b2},
+        {0x0049, 0x86b3},
+        {0x0000, 0x86b4},
+        {0x0000, 0x86b4},
+
+        {0x0012, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+        {0x0013, 0x8201},
+        {0x0008, 0x8200},
+        {0x0001, 0x8200},
+
+        {0x0001, 0x86b0},
+        {0x00aa, 0x86b1},
+        {0x0000, 0x86b2},
+        {0x00e4, 0x86b3},
+        {0x0000, 0x86b4},
+        {0x0000, 0x86b4},
+
+        {0x0018, 0x8660},
+
+        {0x0090, 0x8110},
+        {0x0001, 0x8114},
+        {0x0001, 0x8114},
+        {0x0001, 0x8114},
+        {0x0003, 0x8114},
+
+        {0x0080, 0x8804},
+        {0x0003, 0x8801},
+        {0x0012, 0x8800},
+        {0x0004, 0x8801},
+        {0x0005, 0x8800},
+        {0x0005, 0x8801},
+        {0x0000, 0x8800},
+        {0x0006, 0x8801},
+        {0x0000, 0x8800},
+        {0x0007, 0x8801},
+        {0x0000, 0x8800},
+        {0x0008, 0x8801},
+        {0x0005, 0x8800},
+        {0x000a, 0x8700},
+        {0x000e, 0x8801},
+        {0x0004, 0x8800},
+        {0x0005, 0x8801},
+        {0x0047, 0x8800},
+        {0x0006, 0x8801},
+        {0x0000, 0x8800},
+        {0x0007, 0x8801},
+        {0x00c0, 0x8800},
+        {0x0008, 0x8801},
+        {0x0003, 0x8800},
+        {0x0013, 0x8801},
+        {0x0001, 0x8800},
+        {0x0009, 0x8801},
+        {0x0000, 0x8800},
+        {0x000a, 0x8801},
+        {0x0000, 0x8800},
+        {0x000b, 0x8801},
+        {0x0000, 0x8800},
+        {0x000c, 0x8801},
+        {0x0000, 0x8800},
+        {0x000e, 0x8801},
+        {0x0004, 0x8800},
+        {0x000f, 0x8801},
+        {0x0000, 0x8800},
+        {0x0010, 0x8801},
+        {0x0006, 0x8800},
+        {0x0011, 0x8801},
+        {0x0006, 0x8800},
+        {0x0012, 0x8801},
+        {0x0000, 0x8800},
+        {0x0013, 0x8801},
+        {0x0001, 0x8800},
+
+        {0x000a, 0x8700},
+        {0x0000, 0x8702},
+        {0x0000, 0x8703},
+        {0x00c2, 0x8704},
+        {0x0001, 0x870c},
+
+        {0x0044, 0x8600},
+        {0x0002, 0x8606},
+        {0x0064, 0x8607},
+        {0x003a, 0x8601},
+        {0x0008, 0x8602},
+        {0x0044, 0x8600},
+        {0x0018, 0x8617},
+        {0x0008, 0x8618},
+        {0x00a1, 0x8656},
+        {0x0004, 0x865b},
+        {0x0002, 0x865c},
+        {0x0058, 0x865d},
+        {0x0048, 0x865e},
+        {0x0012, 0x8608},
+        {0x002c, 0x8609},
+        {0x0002, 0x860a},
+        {0x002c, 0x860b},
+        {0x00db, 0x860c},
+        {0x00f9, 0x860d},
+        {0x00f1, 0x860e},
+        {0x00e3, 0x860f},
+        {0x002c, 0x8610},
+        {0x006c, 0x8651},
+        {0x0041, 0x8652},
+        {0x0059, 0x8653},
+        {0x0040, 0x8654},
+        {0x00fa, 0x8611},
+        {0x00ff, 0x8612},
+        {0x00f8, 0x8613},
+        {0x0000, 0x8614},
+        {0x0001, 0x863f},
+        {0x0000, 0x8640},
+        {0x0026, 0x8641},
+        {0x0045, 0x8642},
+        {0x0060, 0x8643},
+        {0x0075, 0x8644},
+        {0x0088, 0x8645},
+        {0x009b, 0x8646},
+        {0x00b0, 0x8647},
+        {0x00c5, 0x8648},
+        {0x00d2, 0x8649},
+        {0x00dc, 0x864a},
+        {0x00e5, 0x864b},
+        {0x00eb, 0x864c},
+        {0x00f0, 0x864d},
+        {0x00f6, 0x864e},
+        {0x00fa, 0x864f},
+        {0x00ff, 0x8650},
+        {0x0060, 0x8657},
+        {0x0010, 0x8658},
+        {0x0018, 0x8659},
+        {0x0005, 0x865a},
+        {0x0018, 0x8660},
+        {0x0003, 0x8509},
+        {0x0011, 0x850a},
+        {0x0032, 0x850b},
+        {0x0010, 0x850c},
+        {0x0021, 0x850d},
+        {0x0001, 0x8500},
+        {0x0000, 0x8508},
+        {0x0012, 0x8608},
+        {0x002c, 0x8609},
+        {0x0002, 0x860a},
+        {0x0039, 0x860b},
+        {0x00d0, 0x860c},
+        {0x00f7, 0x860d},
+        {0x00ed, 0x860e},
+        {0x00db, 0x860f},
+        {0x0039, 0x8610},
+        {0x0012, 0x8657},
+        {0x000c, 0x8619},
+        {0x0004, 0x861a},
+        {0x00a1, 0x8656},
+        {0x00c8, 0x8615},
+        {0x0032, 0x8616},
+
+        {0x0030, 0x8112},
+        {0x0020, 0x8112},
+        {0x0020, 0x8112},
+        {0x000f, 0x8402},
+        {0x0000, 0x8403},
+
+        {0x0090, 0x8110},
+        {0x0001, 0x8114},
+        {0x0001, 0x8114},
+        {0x0001, 0x8114},
+        {0x0003, 0x8114},
+        {0x0080, 0x8804},
+
+        {0x0003, 0x8801},
+        {0x0012, 0x8800},
+        {0x0004, 0x8801},
+        {0x0005, 0x8800},
+        {0x0005, 0x8801},
+        {0x0047, 0x8800},
+        {0x0006, 0x8801},
+        {0x0000, 0x8800},
+        {0x0007, 0x8801},
+        {0x00c0, 0x8800},
+        {0x0008, 0x8801},
+        {0x0003, 0x8800},
+        {0x000a, 0x8700},
+        {0x000e, 0x8801},
+        {0x0004, 0x8800},
+        {0x0005, 0x8801},
+        {0x0047, 0x8800},
+        {0x0006, 0x8801},
+        {0x0000, 0x8800},
+        {0x0007, 0x8801},
+        {0x00c0, 0x8800},
+        {0x0008, 0x8801},
+        {0x0003, 0x8800},
+        {0x0013, 0x8801},
+        {0x0001, 0x8800},
+        {0x0009, 0x8801},
+        {0x0000, 0x8800},
+        {0x000a, 0x8801},
+        {0x0000, 0x8800},
+        {0x000b, 0x8801},
+        {0x0000, 0x8800},
+        {0x000c, 0x8801},
+        {0x0000, 0x8800},
+        {0x000e, 0x8801},
+        {0x0004, 0x8800},
+        {0x000f, 0x8801},
+        {0x0000, 0x8800},
+        {0x0010, 0x8801},
+        {0x0006, 0x8800},
+        {0x0011, 0x8801},
+        {0x0006, 0x8800},
+        {0x0012, 0x8801},
+        {0x0000, 0x8800},
+        {0x0013, 0x8801},
+        {0x0001, 0x8800},
+        {0x000a, 0x8700},
+        {0x0000, 0x8702},
+        {0x0000, 0x8703},
+        {0x00c2, 0x8704},
+        {0x0001, 0x870c},
+        {0x0044, 0x8600},
+        {0x0002, 0x8606},
+        {0x0064, 0x8607},
+        {0x003a, 0x8601},
+        {0x0008, 0x8602},
+        {0x0044, 0x8600},
+        {0x0018, 0x8617},
+        {0x0008, 0x8618},
+        {0x00a1, 0x8656},
+        {0x0004, 0x865b},
+        {0x0002, 0x865c},
+        {0x0058, 0x865d},
+        {0x0048, 0x865e},
+        {0x0012, 0x8608},
+        {0x002c, 0x8609},
+        {0x0002, 0x860a},
+        {0x002c, 0x860b},
+        {0x00db, 0x860c},
+        {0x00f9, 0x860d},
+        {0x00f1, 0x860e},
+        {0x00e3, 0x860f},
+        {0x002c, 0x8610},
+        {0x006c, 0x8651},
+        {0x0041, 0x8652},
+        {0x0059, 0x8653},
+        {0x0040, 0x8654},
+        {0x00fa, 0x8611},
+        {0x00ff, 0x8612},
+        {0x00f8, 0x8613},
+        {0x0000, 0x8614},
+        {0x0001, 0x863f},
+        {0x0000, 0x8640},
+        {0x0026, 0x8641},
+        {0x0045, 0x8642},
+        {0x0060, 0x8643},
+        {0x0075, 0x8644},
+        {0x0088, 0x8645},
+        {0x009b, 0x8646},
+        {0x00b0, 0x8647},
+        {0x00c5, 0x8648},
+        {0x00d2, 0x8649},
+        {0x00dc, 0x864a},
+        {0x00e5, 0x864b},
+        {0x00eb, 0x864c},
+        {0x00f0, 0x864d},
+        {0x00f6, 0x864e},
+        {0x00fa, 0x864f},
+        {0x00ff, 0x8650},
+        {0x0060, 0x8657},
+        {0x0010, 0x8658},
+        {0x0018, 0x8659},
+        {0x0005, 0x865a},
+        {0x0018, 0x8660},
+        {0x0003, 0x8509},
+        {0x0011, 0x850a},
+        {0x0032, 0x850b},
+        {0x0010, 0x850c},
+        {0x0021, 0x850d},
+        {0x0001, 0x8500},
+        {0x0000, 0x8508},
+
+        {0x0012, 0x8608},
+        {0x002c, 0x8609},
+        {0x0002, 0x860a},
+        {0x0039, 0x860b},
+        {0x00d0, 0x860c},
+        {0x00f7, 0x860d},
+        {0x00ed, 0x860e},
+        {0x00db, 0x860f},
+        {0x0039, 0x8610},
+        {0x0012, 0x8657},
+        {0x0064, 0x8619},
 
 /* This line starts it all, it is not needed here */
 /* since it has been build into the driver */
 /* jfm: don't start now */
-/* 590  *  {0x0030, 0x8112}, */
+/*      {0x0030, 0x8112}, */
         {}
 };
 
@@ -1109,14 +1023,14 @@ static const u16 spca508_vista_init_data[][2] = {
         {0x0008, 0x8200},       /* Clear register */
         {0x0000, 0x870b},       /* Reset CTL3 */
         {0x0020, 0x8112},       /* Video Drop packet enable */
-        {0x0003, 0x8111},  /* Soft Reset compression, memory, TG & CDSP */
+        {0x0003, 0x8111},       /* Soft Reset compression, memory, TG & CDSP */
         {0x0000, 0x8110},       /* Disable everything */
         {0x0000, 0x8114},       /* Software GPIO output data */
         {0x0000, 0x8114},
 
         {0x0003, 0x8111},
         {0x0000, 0x8111},
-        {0x0090, 0x8110},  /* Enable: SSI output, External 2X clock output */
+        {0x0090, 0x8110},    /* Enable: SSI output, External 2X clock output */
         {0x0020, 0x8112},
         {0x0000, 0x8114},
         {0x0001, 0x8114},
@@ -1129,191 +1043,143 @@ static const u16 spca508_vista_init_data[][2] = {
         {0x00ba, 0x8804},       /* SSI Slave address */
         {0x0010, 0x8802},       /* 93.75kHz SSI Clock Two DataByte */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},       /* Will write 2 bytes (DATA1+DATA2) */
         {0x0020, 0x8801},       /* Register address for SSI read/write */
         {0x0044, 0x8805},       /* DATA2 */
         {0x0004, 0x8800},       /* DATA1 -> write triggered */
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0009, 0x8801},
         {0x0042, 0x8805},
         {0x0001, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x003c, 0x8801},
         {0x0001, 0x8805},
         {0x0000, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0001, 0x8801},
         {0x000a, 0x8805},
         {0x0000, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0002, 0x8801},
         {0x0000, 0x8805},
         {0x0000, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0003, 0x8801},
         {0x0027, 0x8805},
         {0x0001, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0004, 0x8801},
         {0x0065, 0x8805},
         {0x0001, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0005, 0x8801},
         {0x0003, 0x8805},
         {0x0000, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0006, 0x8801},
         {0x001c, 0x8805},
         {0x0000, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0007, 0x8801},
         {0x002a, 0x8805},
         {0x0000, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x000e, 0x8801},
         {0x0000, 0x8805},
         {0x0000, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0028, 0x8801},
         {0x002e, 0x8805},
         {0x0000, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0039, 0x8801},
         {0x0013, 0x8805},
         {0x0000, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x003b, 0x8801},
         {0x000c, 0x8805},
         {0x0000, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0035, 0x8801},
         {0x0028, 0x8805},
         {0x0000, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
-        /* READ { 0, 0x0001, 0x8802 } ->
-                0000: 10  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
+        /* READ { 0x0001, 0x8802 } -> 0000: 10  */
         {0x0010, 0x8802},
         {0x0009, 0x8801},
         {0x0042, 0x8805},
         {0x0001, 0x8800},
-        /* READ { 0, 0x0001, 0x8803 } ->
-                0000: 00  */
+        /* READ { 0x0001, 0x8803 } -> 0000: 00  */
 
         {0x0050, 0x8703},
         {0x0002, 0x8704},       /* External input CKIx1 */
         {0x0001, 0x870c},       /* Select CKOx2 output */
         {0x009a, 0x8600},       /* Line memory Read Counter (L) */
-        {0x0001, 0x8606},  /* 1 Line memory Read Counter (H) Result: (d)410 */
+        {0x0001, 0x8606},    /* 1 Line memory Read Counter (H) Result: (d)410 */
         {0x0023, 0x8601},
         {0x0010, 0x8602},
         {0x000a, 0x8603},
-        {0x009A, 0x8600},
+        {0x009a, 0x8600},
         {0x0001, 0x865b},       /* 1 Horizontal Offset for Valid Pixel(L) */
         {0x0003, 0x865c},       /* Vertical offset for valid lines (L) */
         {0x0058, 0x865d},       /* Horizontal valid pixels window (L) */
@@ -1329,7 +1195,7 @@ static const u16 spca508_vista_init_data[][2] = {
         {0x0005, 0x860a},       /* ... */
         {0x0025, 0x860b},
         {0x00e1, 0x860c},
-        {0x00fa, 0x860D},
+        {0x00fa, 0x860d},
         {0x00f4, 0x860e},
         {0x00e8, 0x860f},
         {0x0025, 0x8610},       /* A33 Coef. */
@@ -1344,11 +1210,12 @@ static const u16 spca508_vista_init_data[][2] = {
         {0x0040, 0x8654},       /* Gb gain for white balance (L) */
         {0x0001, 0x863f},       /* Enable fixed gamma correction */
 
-        {0x00a1, 0x8656},       /* Size - Window1: 256x256, Window2: 128x128 */
-        /* UV division: UV no change, Enable New edge enhancement */
+        {0x00a1, 0x8656},       /* Size - Window1: 256x256, Window2: 128x128,
+                                 * UV division: UV no change,
+                                 * Enable New edge enhancement */
         {0x0018, 0x8657},       /* Edge gain high threshold */
         {0x0020, 0x8658},       /* Edge gain low threshold */
-        {0x000A, 0x8659},       /* Edge bandwidth high threshold */
+        {0x000a, 0x8659},       /* Edge bandwidth high threshold */
         {0x0005, 0x865a},       /* Edge bandwidth low threshold */
         {0x0064, 0x8607},       /* UV filter enable */
 
@@ -1384,29 +1251,20 @@ static const u16 spca508_vista_init_data[][2] = {
         {0x0000, 0x86b4},
         {0x001e, 0x8660},
 
-        /* READ { 0, 0x0000, 0x8608 } ->
-                0000: 13  */
-        /* READ { 0, 0x0000, 0x8609 } ->
-                0000: 28  */
-        /* READ { 0, 0x0000, 0x8610 } ->
-                0000: 05  */
-        /* READ { 0, 0x0000, 0x8611 } ->
-                0000: 25  */
-        /* READ { 0, 0x0000, 0x8612 } ->
-                0000: e1  */
-        /* READ { 0, 0x0000, 0x8613 } ->
-                0000: fa  */
-        /* READ { 0, 0x0000, 0x8614 } ->
-                0000: f4  */
-        /* READ { 0, 0x0000, 0x8615 } ->
-                0000: e8  */
-        /* READ { 0, 0x0000, 0x8616 } ->
-                0000: 25  */
+        /* READ { 0x0000, 0x8608 } -> 0000: 13  */
+        /* READ { 0x0000, 0x8609 } -> 0000: 28  */
+        /* READ { 0x0000, 0x8610 } -> 0000: 05  */
+        /* READ { 0x0000, 0x8611 } -> 0000: 25  */
+        /* READ { 0x0000, 0x8612 } -> 0000: e1  */
+        /* READ { 0x0000, 0x8613 } -> 0000: fa  */
+        /* READ { 0x0000, 0x8614 } -> 0000: f4  */
+        /* READ { 0x0000, 0x8615 } -> 0000: e8  */
+        /* READ { 0x0000, 0x8616 } -> 0000: 25  */
         {}
 };
 
 static int reg_write(struct usb_device *dev,
-                        __u16 index, __u16 value)
+                        u16 index, u16 value)
 {
         int ret;
 
@@ -1425,7 +1283,7 @@ static int reg_write(struct usb_device *dev,
 /* read 1 byte */
 /* returns: negative is error, pos or zero is data */
 static int reg_read(struct gspca_dev *gspca_dev,
-                        __u16 index)    /* wIndex */
+                        u16 index)      /* wIndex */
 {
         int ret;
 
@@ -1447,16 +1305,16 @@ static int reg_read(struct gspca_dev *gspca_dev,
 }
 
 static int write_vector(struct gspca_dev *gspca_dev,
-                        const u16 data[][2])
+                        const u16 (*data)[2])
 {
         struct usb_device *dev = gspca_dev->dev;
-        int ret, i = 0;
+        int ret;
 
-        while (data[i][1] != 0) {
-                ret = reg_write(dev, data[i][1], data[i][0]);
+        while ((*data)[1] != 0) {
+                ret = reg_write(dev, (*data)[1], (*data)[0]);
                 if (ret < 0)
                         return ret;
-                i++;
+                data++;
         }
         return 0;
 }
@@ -1468,6 +1326,15 @@ static int sd_config(struct gspca_dev *gspca_dev,
         struct sd *sd = (struct sd *) gspca_dev;
         struct cam *cam;
         int data1, data2;
+        const u16 (*init_data)[2];
+        static const u16 (*(init_data_tb[]))[2] = {
+                spca508_vista_init_data,        /* CreativeVista 0 */
+                spca508_sightcam_init_data,     /* HamaUSBSightcam 1 */
+                spca508_sightcam2_init_data,    /* HamaUSBSightcam2 2 */
+                spca508cs110_init_data,         /* IntelEasyPCCamera 3 */
+                spca508cs110_init_data,         /* MicroInnovationIC200 4 */
+                spca508_init_data,              /* ViewQuestVQ110 5 */
+        };
 
         /* Read from global register the USB product and vendor IDs, just to
          * prove that we can communicate with the device.  This works, which
@@ -1491,37 +1358,13 @@ static int sd_config(struct gspca_dev *gspca_dev,
         sd->subtype = id->driver_info;
         sd->brightness = BRIGHTNESS_DEF;
 
-        switch (sd->subtype) {
-        case ViewQuestVQ110:
-                if (write_vector(gspca_dev, spca508_init_data))
-                        return -1;
-                break;
-        default:
-/*      case MicroInnovationIC200: */
-/*      case IntelEasyPCCamera: */
-                if (write_vector(gspca_dev, spca508cs110_init_data))
-                        return -1;
-                break;
-        case HamaUSBSightcam:
-                if (write_vector(gspca_dev, spca508_sightcam_init_data))
-                        return -1;
-                break;
-        case HamaUSBSightcam2:
-                if (write_vector(gspca_dev, spca508_sightcam2_init_data))
-                        return -1;
-                break;
-        case CreativeVista:
-                if (write_vector(gspca_dev, spca508_vista_init_data))
-                        return -1;
-                break;
-        }
-        return 0;                       /* success */
+        init_data = init_data_tb[sd->subtype];
+        return write_vector(gspca_dev, init_data);
 }
 
 /* this function is called at probe and resume time */
 static int sd_init(struct gspca_dev *gspca_dev)
 {
-/*      write_vector(gspca_dev, spca508_open_data); */
         return 0;
 }
 
@@ -1529,7 +1372,7 @@ static int sd_start(struct gspca_dev *gspca_dev)
 {
         int mode;
 
-        mode = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv;
+        mode = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv;
         reg_write(gspca_dev->dev, 0x8500, mode);
         switch (mode) {
         case 0:
@@ -1554,7 +1397,7 @@ static void sd_stopN(struct gspca_dev *gspca_dev)
 
 static void sd_pkt_scan(struct gspca_dev *gspca_dev,
                         struct gspca_frame *frame,      /* target */
-                        __u8 *data,                     /* isoc packet */
+                        u8 *data,                       /* isoc packet */
                         int len)                        /* iso packet length */
 {
         switch (data[0]) {
@@ -1567,7 +1410,6 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev,
                                 data, len);
                 break;
         case 0xff:                      /* drop */
-/*              gspca_dev->last_packet_type = DISCARD_PACKET; */
                 break;
         default:
                 data += 1;
@@ -1581,7 +1423,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev,
 static void setbrightness(struct gspca_dev *gspca_dev)
 {
         struct sd *sd = (struct sd *) gspca_dev;
-        __u8 brightness = sd->brightness;
+        u8 brightness = sd->brightness;
 
         /* MX seem contrast */
         reg_write(gspca_dev->dev, 0x8651, brightness);
diff --git a/drivers/media/video/gspca/spca561.c b/drivers/media/video/gspca/spca561.c
index c99c5e34e211..27e82b35f3e7 100644
--- a/drivers/media/video/gspca/spca561.c
+++ b/drivers/media/video/gspca/spca561.c
@@ -34,8 +34,8 @@ struct sd {
 
         __u16 exposure;                 /* rev12a only */
 #define EXPOSURE_MIN 1
-#define EXPOSURE_DEF 200
-#define EXPOSURE_MAX (4095 - 900) /* see set_exposure */
+#define EXPOSURE_DEF 700                /* == 10 fps */
+#define EXPOSURE_MAX (2047 + 325)       /* see setexposure */
 
         __u8 contrast;                  /* rev72a only */
 #define CONTRAST_MIN 0x00
@@ -48,9 +48,9 @@ struct sd {
 #define BRIGHTNESS_MAX 0x3f
 
         __u8 white;
-#define WHITE_MIN 1
-#define WHITE_DEF 0x40
-#define WHITE_MAX 0x7f
+#define HUE_MIN 1
+#define HUE_DEF 0x40
+#define HUE_MAX 0x7f
 
         __u8 autogain;
 #define AUTOGAIN_MIN 0
@@ -58,9 +58,9 @@ struct sd {
 #define AUTOGAIN_MAX 1
 
         __u8 gain;                      /* rev12a only */
-#define GAIN_MIN 0x0
-#define GAIN_DEF 0x24
-#define GAIN_MAX 0x24
+#define GAIN_MIN 0
+#define GAIN_DEF 63
+#define GAIN_MAX 255
 
 #define EXPO12A_DEF 3
         __u8 expo12a;           /* expo/gain? for rev 12a */
@@ -461,7 +461,7 @@ static int sd_config(struct gspca_dev *gspca_dev,
         }
         sd->brightness = BRIGHTNESS_DEF;
         sd->contrast = CONTRAST_DEF;
-        sd->white = WHITE_DEF;
+        sd->white = HUE_DEF;
         sd->exposure = EXPOSURE_DEF;
         sd->autogain = AUTOGAIN_DEF;
         sd->gain = GAIN_DEF;
@@ -549,8 +549,7 @@ static void setcontrast(struct gspca_dev *gspca_dev)
 static void setexposure(struct gspca_dev *gspca_dev)
 {
         struct sd *sd = (struct sd *) gspca_dev;
-        int expo;
-        int clock_divider;
+        int i, expo = 0;
 
         /* Register 0x8309 controls exposure for the spca561,
            the basic exposure setting goes from 1-2047, where 1 is completely
@@ -564,16 +563,22 @@ static void setexposure(struct gspca_dev *gspca_dev)
            configure a divider for the base framerate which us used at the
            exposure setting of 1-300. These bits configure the base framerate
            according to the following formula: fps = 60 / (value + 2) */
-        if (sd->exposure < 2048) {
-                expo = sd->exposure;
-                clock_divider = 0;
-        } else {
-                /* Add 900 to make the 0 setting of the second part of the
-                   exposure equal to the 2047 setting of the first part. */
-                expo = (sd->exposure - 2048) + 900;
-                clock_divider = 3;
+
+        /* We choose to use the high bits setting the fixed framerate divisor
+           asap, as setting high basic exposure setting without the fixed
+           divider in combination with high gains makes the cam stop */
+        int table[] =  { 0, 450, 550, 625, EXPOSURE_MAX };
+
+        for (i = 0; i < ARRAY_SIZE(table) - 1; i++) {
+                if (sd->exposure <= table[i + 1]) {
+                        expo  = sd->exposure - table[i];
+                        if (i)
+                                expo += 300;
+                        expo |= i << 11;
+                        break;
+                }
         }
-        expo |= clock_divider << 11;
+
         gspca_dev->usb_buf[0] = expo;
         gspca_dev->usb_buf[1] = expo >> 8;
         reg_w_buf(gspca_dev, 0x8309, 2);
@@ -584,7 +589,16 @@ static void setgain(struct gspca_dev *gspca_dev)
 {
         struct sd *sd = (struct sd *) gspca_dev;
 
-        gspca_dev->usb_buf[0] = sd->gain;
+        /* gain reg low 6 bits  0-63 gain, bit 6 and 7, both double the
+           sensitivity when set, so 31 + one of them set == 63, and 15
+           with both of them set == 63 */
+        if (sd->gain < 64)
+                gspca_dev->usb_buf[0] = sd->gain;
+        else if (sd->gain < 128)
+                gspca_dev->usb_buf[0] = (sd->gain / 2) | 0x40;
+        else
+                gspca_dev->usb_buf[0] = (sd->gain / 4) | 0xC0;
+
         gspca_dev->usb_buf[1] = 0;
         reg_w_buf(gspca_dev, 0x8335, 2);
 }
@@ -629,8 +643,7 @@ static int sd_start_12a(struct gspca_dev *gspca_dev)
         reg_w_buf(gspca_dev, 0x8391, 8);
         reg_w_buf(gspca_dev, 0x8390, 8);
         setwhite(gspca_dev);
-        setautogain(gspca_dev);
-/*      setgain(gspca_dev);             */
+        setgain(gspca_dev);
         setexposure(gspca_dev);
         return 0;
 }
@@ -762,18 +775,6 @@ static void do_autogain(struct gspca_dev *gspca_dev)
                         i2c_write(gspca_dev, expotimes | pixelclk, 0x09);
                 }
                 break;
-        case Rev012A:
-                reg_r(gspca_dev, 0x8330, 2);
-                if (gspca_dev->usb_buf[1] > 0x08) {
-                        gspca_dev->usb_buf[0] = ++sd->expo12a;
-                        gspca_dev->usb_buf[1] = 0;
-                        reg_w_buf(gspca_dev, 0x8339, 2);
-                } else if (gspca_dev->usb_buf[1] < 0x02) {
-                        gspca_dev->usb_buf[0] = --sd->expo12a;
-                        gspca_dev->usb_buf[1] = 0;
-                        reg_w_buf(gspca_dev, 0x8339, 2);
-                }
-                break;
         }
 }
 
@@ -928,13 +929,13 @@ static int sd_getgain(struct gspca_dev *gspca_dev, __s32 *val)
 static struct ctrl sd_ctrls_12a[] = {
         {
             {
-                .id = V4L2_CID_DO_WHITE_BALANCE,
+                .id = V4L2_CID_HUE,
                 .type = V4L2_CTRL_TYPE_INTEGER,
-                .name = "White Balance",
-                .minimum = WHITE_MIN,
-                .maximum = WHITE_MAX,
+                .name = "Hue",
+                .minimum = HUE_MIN,
+                .maximum = HUE_MAX,
                 .step = 1,
-                .default_value = WHITE_DEF,
+                .default_value = HUE_DEF,
             },
             .set = sd_setwhite,
             .get = sd_getwhite,
@@ -954,19 +955,6 @@ static struct ctrl sd_ctrls_12a[] = {
         },
         {
             {
-                .id = V4L2_CID_AUTOGAIN,
-                .type = V4L2_CTRL_TYPE_BOOLEAN,
-                .name = "Auto Gain",
-                .minimum = AUTOGAIN_MIN,
-                .maximum = AUTOGAIN_MAX,
-                .step = 1,
-                .default_value = AUTOGAIN_DEF,
-            },
-            .set = sd_setautogain,
-            .get = sd_getautogain,
-        },
-        {
-            {
                 .id = V4L2_CID_GAIN,
                 .type = V4L2_CTRL_TYPE_INTEGER,
                 .name = "Gain",
@@ -983,13 +971,13 @@ static struct ctrl sd_ctrls_12a[] = {
 static struct ctrl sd_ctrls_72a[] = {
         {
             {
-                .id = V4L2_CID_DO_WHITE_BALANCE,
+                .id = V4L2_CID_HUE,
                 .type = V4L2_CTRL_TYPE_INTEGER,
-                .name = "White Balance",
-                .minimum = WHITE_MIN,
-                .maximum = WHITE_MAX,
+                .name = "Hue",
+                .minimum = HUE_MIN,
+                .maximum = HUE_MAX,
                 .step = 1,
-                .default_value = WHITE_DEF,
+                .default_value = HUE_DEF,
             },
             .set = sd_setwhite,
             .get = sd_getwhite,
@@ -1046,7 +1034,6 @@ static const struct sd_desc sd_desc_12a = {
         .stopN = sd_stopN,
         .stop0 = sd_stop0,
         .pkt_scan = sd_pkt_scan,
-/*      .dq_callback = do_autogain,      * fixme */
 };
 static const struct sd_desc sd_desc_72a = {
         .name = MODULE_NAME,
diff --git a/drivers/media/video/gspca/sq905.c b/drivers/media/video/gspca/sq905.c
index 2e1cdf068fda..715a68f0156e 100644
--- a/drivers/media/video/gspca/sq905.c
+++ b/drivers/media/video/gspca/sq905.c
@@ -309,6 +309,7 @@ static int sd_config(struct gspca_dev *gspca_dev,
         struct sd *dev = (struct sd *) gspca_dev;
 
         /* We don't use the buffer gspca allocates so make it small. */
+        cam->bulk = 1;
         cam->bulk_size = 64;
 
         INIT_WORK(&dev->work_struct, sq905_dostream);
diff --git a/drivers/media/video/gspca/sq905c.c b/drivers/media/video/gspca/sq905c.c
index 0bcb74a1b143..916892505432 100644
--- a/drivers/media/video/gspca/sq905c.c
+++ b/drivers/media/video/gspca/sq905c.c
@@ -206,6 +206,7 @@ static int sd_config(struct gspca_dev *gspca_dev,
                 cam->nmodes = 1;
         /* We don't use the buffer gspca allocates so make it small. */
         cam->bulk_size = 32;
+        cam->bulk = 1;
         INIT_WORK(&dev->work_struct, sq905c_dostream);
         return 0;
 }
diff --git a/drivers/media/video/gspca/stv06xx/stv06xx.c b/drivers/media/video/gspca/stv06xx/stv06xx.c
index 9dff2e65b116..e573c3406324 100644
--- a/drivers/media/video/gspca/stv06xx/stv06xx.c
+++ b/drivers/media/video/gspca/stv06xx/stv06xx.c
@@ -293,8 +293,6 @@ static void stv06xx_stopN(struct gspca_dev *gspca_dev)
                 goto out;
 
         err = sd->sensor->stop(sd);
-        if (err < 0)
-                goto out;
 
 out:
         if (err < 0)
diff --git a/drivers/media/video/gspca/stv06xx/stv06xx_vv6410.c b/drivers/media/video/gspca/stv06xx/stv06xx_vv6410.c
index 69c77c932fc0..11a0c002f5dc 100644
--- a/drivers/media/video/gspca/stv06xx/stv06xx_vv6410.c
+++ b/drivers/media/video/gspca/stv06xx/stv06xx_vv6410.c
@@ -80,12 +80,26 @@ static const struct ctrl vv6410_ctrl[] = {
                         .minimum        = 0,
                         .maximum        = 15,
                         .step           = 1,
-                        .default_value  = 0
+                        .default_value  = 10
                 },
                 .set = vv6410_set_analog_gain,
                 .get = vv6410_get_analog_gain
+        },
+#define EXPOSURE_IDX 3
+        {
+                {
+                        .id             = V4L2_CID_EXPOSURE,
+                        .type           = V4L2_CTRL_TYPE_INTEGER,
+                        .name           = "exposure",
+                        .minimum        = 0,
+                        .maximum        = 32768,
+                        .step           = 1,
+                        .default_value  = 20000
+                },
+                .set = vv6410_set_exposure,
+                .get = vv6410_get_exposure
         }
-};
+        };
 
 static int vv6410_probe(struct sd *sd)
 {
@@ -121,6 +135,7 @@ static int vv6410_probe(struct sd *sd)
 static int vv6410_init(struct sd *sd)
 {
         int err = 0, i;
+        s32 *sensor_settings = sd->sensor_priv;
 
         for (i = 0; i < ARRAY_SIZE(stv_bridge_init); i++) {
                 /* if NULL then len contains single value */
@@ -142,6 +157,16 @@ static int vv6410_init(struct sd *sd)
 
         err = stv06xx_write_sensor_bytes(sd, (u8 *) vv6410_sensor_init,
                                          ARRAY_SIZE(vv6410_sensor_init));
+        if (err < 0)
+                return err;
+
+        err = vv6410_set_exposure(&sd->gspca_dev,
+                                   sensor_settings[EXPOSURE_IDX]);
+        if (err < 0)
+                return err;
+
+        err = vv6410_set_analog_gain(&sd->gspca_dev,
+                                      sensor_settings[GAIN_IDX]);
 
         return (err < 0) ? err : 0;
 }
@@ -318,3 +343,50 @@ static int vv6410_set_analog_gain(struct gspca_dev *gspca_dev, __s32 val)
 
         return (err < 0) ? err : 0;
 }
+
+static int vv6410_get_exposure(struct gspca_dev *gspca_dev, __s32 *val)
+{
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+
+        *val = sensor_settings[EXPOSURE_IDX];
+
+        PDEBUG(D_V4L2, "Read exposure %d", *val);
+
+        return 0;
+}
+
+static int vv6410_set_exposure(struct gspca_dev *gspca_dev, __s32 val)
+{
+        int err;
+        struct sd *sd = (struct sd *) gspca_dev;
+        s32 *sensor_settings = sd->sensor_priv;
+        unsigned int fine, coarse;
+
+        sensor_settings[EXPOSURE_IDX] = val;
+
+        val = (val * val >> 14) + val / 4;
+
+        fine = val % VV6410_CIF_LINELENGTH;
+        coarse = min(512, val / VV6410_CIF_LINELENGTH);
+
+        PDEBUG(D_V4L2, "Set coarse exposure to %d, fine expsure to %d",
+               coarse, fine);
+
+        err = stv06xx_write_sensor(sd, VV6410_FINEH, fine >> 8);
+        if (err < 0)
+                goto out;
+
+        err = stv06xx_write_sensor(sd, VV6410_FINEL, fine & 0xff);
+        if (err < 0)
+                goto out;
+
+        err = stv06xx_write_sensor(sd, VV6410_COARSEH, coarse >> 8);
+        if (err < 0)
+                goto out;
+
+        err = stv06xx_write_sensor(sd, VV6410_COARSEL, coarse & 0xff);
+
+out:
+        return err;
+}
diff --git a/drivers/media/video/gspca/stv06xx/stv06xx_vv6410.h b/drivers/media/video/gspca/stv06xx/stv06xx_vv6410.h
index 95ac55891bd4..487d40555343 100644
--- a/drivers/media/video/gspca/stv06xx/stv06xx_vv6410.h
+++ b/drivers/media/video/gspca/stv06xx/stv06xx_vv6410.h
@@ -173,6 +173,8 @@
 #define VV6410_SUBSAMPLE                0x01
 #define VV6410_CROP_TO_QVGA             0x02
 
+#define VV6410_CIF_LINELENGTH           415
+
 static int vv6410_probe(struct sd *sd);
 static int vv6410_start(struct sd *sd);
 static int vv6410_init(struct sd *sd);
@@ -187,6 +189,8 @@ static int vv6410_get_vflip(struct gspca_dev *gspca_dev, __s32 *val);
 static int vv6410_set_vflip(struct gspca_dev *gspca_dev, __s32 val);
 static int vv6410_get_analog_gain(struct gspca_dev *gspca_dev, __s32 *val);
 static int vv6410_set_analog_gain(struct gspca_dev *gspca_dev, __s32 val);
+static int vv6410_get_exposure(struct gspca_dev *gspca_dev, __s32 *val);
+static int vv6410_set_exposure(struct gspca_dev *gspca_dev, __s32 val);
 
 const struct stv06xx_sensor stv06xx_sensor_vv6410 = {
         .name = "ST VV6410",
@@ -242,12 +246,6 @@ static const u8 vv6410_sensor_init[][2] = {
         /* Pre-clock generator divide off */
         {VV6410_DATAFORMAT,     BIT(7) | BIT(0)},
 
-        /* Exposure registers */
-        {VV6410_FINEH,          VV6410_FINE_EXPOSURE >> 8},
-        {VV6410_FINEL,          VV6410_FINE_EXPOSURE & 0xff},
-        {VV6410_COARSEH,        VV6410_COARSE_EXPOSURE >> 8},
-        {VV6410_COARSEL,        VV6410_COARSE_EXPOSURE & 0xff},
-        {VV6410_ANALOGGAIN,     0xf0 | VV6410_DEFAULT_GAIN},
         {VV6410_CLKDIV,         VV6410_CLK_DIV_2},
 
         /* System registers */
diff --git a/drivers/media/video/gspca/sunplus.c b/drivers/media/video/gspca/sunplus.c
index c2b8c10c075a..9623f294bdac 100644
--- a/drivers/media/video/gspca/sunplus.c
+++ b/drivers/media/video/gspca/sunplus.c
@@ -32,9 +32,6 @@ MODULE_LICENSE("GPL");
 struct sd {
         struct gspca_dev gspca_dev;     /* !! must be the first item */
 
-        __u8 packet[ISO_MAX_SIZE + 128];
-                                /* !! no more than 128 ff in an ISO packet */
-
         unsigned char brightness;
         unsigned char contrast;
         unsigned char colors;
@@ -1103,7 +1100,6 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev,
 {
         struct sd *sd = (struct sd *) gspca_dev;
         int i, sof = 0;
-        unsigned char *s, *d;
         static unsigned char ffd9[] = {0xff, 0xd9};
 
 /* frames are jpeg 4.1.1 without 0xff escape */
@@ -1177,22 +1173,19 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev,
         }
 
         /* add 0x00 after 0xff */
-        for (i = len; --i >= 0; )
-                if (data[i] == 0xff)
-                        break;
-        if (i < 0) {                    /* no 0xff */
-                gspca_frame_add(gspca_dev, INTER_PACKET, frame, data, len);
-                return;
-        }
-        s = data;
-        d = sd->packet;
-        for (i = 0; i < len; i++) {
-                *d++ = *s++;
-                if (s[-1] == 0xff)
-                        *d++ = 0x00;
-        }
-        gspca_frame_add(gspca_dev, INTER_PACKET, frame,
-                        sd->packet, d - sd->packet);
+        i = 0;
+        do {
+                if (data[i] == 0xff) {
+                        gspca_frame_add(gspca_dev, INTER_PACKET, frame,
+                                        data, i + 1);
+                        len -= i;
+                        data += i;
+                        *data = 0x00;
+                        i = 0;
+                }
+                i++;
+        } while (i < len);
+        gspca_frame_add(gspca_dev, INTER_PACKET, frame, data, len);
 }
 
 static void setbrightness(struct gspca_dev *gspca_dev)
diff --git a/drivers/media/video/gspca/t613.c b/drivers/media/video/gspca/t613.c
index f63e37e2e4fd..404214b8cd2b 100644
--- a/drivers/media/video/gspca/t613.c
+++ b/drivers/media/video/gspca/t613.c
@@ -697,7 +697,7 @@ static int sd_init(struct gspca_dev *gspca_dev)
                 return -EINVAL;
         }
 
-        if (sd->sensor != SENSOR_OTHER) {
+        if (sd->sensor == SENSOR_OM6802) {
                 reg_w_buf(gspca_dev, n1, sizeof n1);
                 i = 5;
                 while (--i >= 0) {
diff --git a/drivers/media/video/gspca/vc032x.c b/drivers/media/video/gspca/vc032x.c
index e4e933c400bc..26dd155efcc3 100644
--- a/drivers/media/video/gspca/vc032x.c
+++ b/drivers/media/video/gspca/vc032x.c
@@ -42,7 +42,7 @@ struct sd {
         char bridge;
 #define BRIDGE_VC0321 0
 #define BRIDGE_VC0323 1
-        char sensor;
+        u8 sensor;
 #define SENSOR_HV7131R 0
 #define SENSOR_MI0360 1
 #define SENSOR_MI1310_SOC 2
@@ -159,17 +159,17 @@ static const struct v4l2_pix_format vc0323_mode[] = {
                 .priv = 2},
 };
 static const struct v4l2_pix_format bi_mode[] = {
-        {320, 240, V4L2_PIX_FMT_YVYU, V4L2_FIELD_NONE,
+        {320, 240, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
                 .bytesperline = 320,
                 .sizeimage = 320 * 240 * 2,
                 .colorspace = V4L2_COLORSPACE_SRGB,
                 .priv = 2},
-        {640, 480, V4L2_PIX_FMT_YVYU, V4L2_FIELD_NONE,
+        {640, 480, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
                 .bytesperline = 640,
                 .sizeimage = 640 * 480 * 2,
                 .colorspace = V4L2_COLORSPACE_SRGB,
                 .priv = 1},
-        {1280, 1024, V4L2_PIX_FMT_YVYU, V4L2_FIELD_NONE,
+        {1280, 1024, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE,
                 .bytesperline = 1280,
                 .sizeimage = 1280 * 1024 * 2,
                 .colorspace = V4L2_COLORSPACE_SRGB,
@@ -2453,6 +2453,17 @@ static int sd_config(struct gspca_dev *gspca_dev,
         struct usb_device *dev = gspca_dev->dev;
         struct cam *cam;
         int sensor;
+        static u8 npkt[] = {    /* number of packets per ISOC message */
+                64,             /* HV7131R 0 */
+                32,             /* MI0360 1 */
+                32,             /* MI1310_SOC 2 */
+                64,             /* MI1320 3 */
+                128,            /* MI1320_SOC 4 */
+                32,             /* OV7660 5 */
+                64,             /* OV7670 6 */
+                128,            /* PO1200 7 */
+                128,            /* PO3130NC 8 */
+        };
 
         cam = &gspca_dev->cam;
         sd->bridge = id->driver_info;
@@ -2508,6 +2519,8 @@ static int sd_config(struct gspca_dev *gspca_dev,
                 case SENSOR_MI1320_SOC:
                         cam->cam_mode = bi_mode;
                         cam->nmodes = ARRAY_SIZE(bi_mode);
+                        cam->input_flags = V4L2_IN_ST_VFLIP |
+                                           V4L2_IN_ST_HFLIP;
                         break;
                 default:
                         cam->cam_mode = vc0323_mode;
@@ -2515,6 +2528,7 @@ static int sd_config(struct gspca_dev *gspca_dev,
                         break;
                 }
         }
+        cam->npkt = npkt[sd->sensor];
 
         sd->hflip = HFLIP_DEF;
         sd->vflip = VFLIP_DEF;
diff --git a/drivers/media/video/gspca/zc3xx.c b/drivers/media/video/gspca/zc3xx.c
index 4fe01d8b6c87..08422d315e68 100644
--- a/drivers/media/video/gspca/zc3xx.c
+++ b/drivers/media/video/gspca/zc3xx.c
@@ -6307,7 +6307,7 @@ static __u16 i2c_read(struct gspca_dev *gspca_dev,
         retbyte = reg_r_i(gspca_dev, 0x0091);           /* read status */
         retval = reg_r_i(gspca_dev, 0x0095);            /* read Lowbyte */
         retval |= reg_r_i(gspca_dev, 0x0096) << 8;      /* read Hightbyte */
-        PDEBUG(D_USBO, "i2c r [%02x] -> %04x (%02x)",
+        PDEBUG(D_USBI, "i2c r [%02x] -> %04x (%02x)",
                         reg, retval, retbyte);
         return retval;
 }
@@ -6868,7 +6868,6 @@ static const struct sensor_by_chipset_revision chipset_revision_sensor[] = {
         {0x8001, 0x13},
         {0x8000, 0x14},         /* CS2102K */
         {0x8400, 0x15},         /* TAS5130K */
-        {0x4001, 0x16},         /* ADCM2700 */
 };
 
 static int vga_3wr_probe(struct gspca_dev *gspca_dev)
@@ -6904,12 +6903,15 @@ static int vga_3wr_probe(struct gspca_dev *gspca_dev)
         retword |= reg_r(gspca_dev, 0x000a);
         PDEBUG(D_PROBE, "probe 3wr vga 1 0x%04x", retword);
         reg_r(gspca_dev, 0x0010);
-        /* this is tested only once anyway */
-        for (i = 0; i < ARRAY_SIZE(chipset_revision_sensor); i++) {
-                if (chipset_revision_sensor[i].revision == retword) {
-                        sd->chip_revision = retword;
-                        send_unknown(dev, SENSOR_PB0330);
-                        return chipset_revision_sensor[i].internal_sensor_id;
+        /* value 0x4001 is meaningless */
+        if (retword != 0x4001) {
+                for (i = 0; i < ARRAY_SIZE(chipset_revision_sensor); i++) {
+                        if (chipset_revision_sensor[i].revision == retword) {
+                                sd->chip_revision = retword;
+                                send_unknown(dev, SENSOR_PB0330);
+                                return chipset_revision_sensor[i]
+                                                        .internal_sensor_id;
+                        }
                 }
         }
 
@@ -6980,12 +6982,12 @@ static int vga_3wr_probe(struct gspca_dev *gspca_dev)
         reg_w(dev, 0x01, 0x0001);
         reg_w(dev, 0x03, 0x0012);
         reg_w(dev, 0x01, 0x0012);
-        reg_w(dev, 0x05, 0x0001);
+        reg_w(dev, 0x05, 0x0012);
         reg_w(dev, 0xd3, 0x008b);
         retword = i2c_read(gspca_dev, 0x01);
         if (retword != 0) {
                 PDEBUG(D_PROBE, "probe 3wr vga type 0a ? ret: %04x", retword);
-                return retword;
+                return 0x16;                    /* adcm2700 (6100/6200) */
         }
         return -1;
 }
diff --git a/drivers/media/video/hexium_gemini.c b/drivers/media/video/hexium_gemini.c
index 8e1463ee1b64..71c211402eb5 100644
--- a/drivers/media/video/hexium_gemini.c
+++ b/drivers/media/video/hexium_gemini.c
@@ -224,7 +224,7 @@ static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i)
 {
         DEB_EE(("VIDIOC_ENUMINPUT %d.\n", i->index));
 
-        if (i->index < 0 || i->index >= HEXIUM_INPUTS)
+        if (i->index >= HEXIUM_INPUTS)
                 return -EINVAL;
 
         memcpy(i, &hexium_inputs[i->index], sizeof(struct v4l2_input));
diff --git a/drivers/media/video/hexium_orion.c b/drivers/media/video/hexium_orion.c
index 2bc39f628455..39d65ca41c62 100644
--- a/drivers/media/video/hexium_orion.c
+++ b/drivers/media/video/hexium_orion.c
@@ -325,7 +325,7 @@ static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i)
 {
         DEB_EE(("VIDIOC_ENUMINPUT %d.\n", i->index));
 
-        if (i->index < 0 || i->index >= HEXIUM_INPUTS)
+        if (i->index >= HEXIUM_INPUTS)
                 return -EINVAL;
 
         memcpy(i, &hexium_inputs[i->index], sizeof(struct v4l2_input));
diff --git a/drivers/media/video/ir-kbd-i2c.c b/drivers/media/video/ir-kbd-i2c.c
index 092c7da0f37a..86f2fefe1edf 100644
--- a/drivers/media/video/ir-kbd-i2c.c
+++ b/drivers/media/video/ir-kbd-i2c.c
@@ -74,7 +74,7 @@ static int get_key_haup_common(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw,
         int start, range, toggle, dev, code, ircode;
 
         /* poll IR chip */
-        if (size != i2c_master_recv(&ir->c,buf,size))
+        if (size != i2c_master_recv(ir->c, buf, size))
                 return -EIO;
 
         /* split rc5 data block ... */
@@ -137,7 +137,7 @@ static int get_key_pixelview(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw)
         unsigned char b;
 
         /* poll IR chip */
-        if (1 != i2c_master_recv(&ir->c,&b,1)) {
+        if (1 != i2c_master_recv(ir->c, &b, 1)) {
                 dprintk(1,"read error\n");
                 return -EIO;
         }
@@ -151,7 +151,7 @@ static int get_key_pv951(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw)
         unsigned char b;
 
         /* poll IR chip */
-        if (1 != i2c_master_recv(&ir->c,&b,1)) {
+        if (1 != i2c_master_recv(ir->c, &b, 1)) {
                 dprintk(1,"read error\n");
                 return -EIO;
         }
@@ -171,7 +171,7 @@ static int get_key_fusionhdtv(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw)
         unsigned char buf[4];
 
         /* poll IR chip */
-        if (4 != i2c_master_recv(&ir->c,buf,4)) {
+        if (4 != i2c_master_recv(ir->c, buf, 4)) {
                 dprintk(1,"read error\n");
                 return -EIO;
         }
@@ -195,7 +195,7 @@ static int get_key_knc1(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw)
         unsigned char b;
 
         /* poll IR chip */
-        if (1 != i2c_master_recv(&ir->c,&b,1)) {
+        if (1 != i2c_master_recv(ir->c, &b, 1)) {
                 dprintk(1,"read error\n");
                 return -EIO;
         }
@@ -222,12 +222,12 @@ static int get_key_avermedia_cardbus(struct IR_i2c *ir,
                                      u32 *ir_key, u32 *ir_raw)
 {
         unsigned char subaddr, key, keygroup;
-        struct i2c_msg msg[] = { { .addr = ir->c.addr, .flags = 0,
+        struct i2c_msg msg[] = { { .addr = ir->c->addr, .flags = 0,
                                    .buf = &subaddr, .len = 1},
-                                 { .addr = ir->c.addr, .flags = I2C_M_RD,
+                                 { .addr = ir->c->addr, .flags = I2C_M_RD,
                                   .buf = &key, .len = 1} };
         subaddr = 0x0d;
-        if (2 != i2c_transfer(ir->c.adapter, msg, 2)) {
+        if (2 != i2c_transfer(ir->c->adapter, msg, 2)) {
                 dprintk(1, "read error\n");
                 return -EIO;
         }
@@ -237,7 +237,7 @@ static int get_key_avermedia_cardbus(struct IR_i2c *ir,
 
         subaddr = 0x0b;
         msg[1].buf = &keygroup;
-        if (2 != i2c_transfer(ir->c.adapter, msg, 2)) {
+        if (2 != i2c_transfer(ir->c->adapter, msg, 2)) {
                 dprintk(1, "read error\n");
                 return -EIO;
         }
@@ -286,7 +286,7 @@ static void ir_work(struct work_struct *work)
 
         /* MSI TV@nywhere Plus requires more frequent polling
            otherwise it will miss some keypresses */
-        if (ir->c.adapter->id == I2C_HW_SAA7134 && ir->c.addr == 0x30)
+        if (ir->c->adapter->id == I2C_HW_SAA7134 && ir->c->addr == 0x30)
                 polling_interval = 50;
 
         ir_key_poll(ir);
@@ -295,34 +295,15 @@ static void ir_work(struct work_struct *work)
 
 /* ----------------------------------------------------------------------- */
 
-static int ir_attach(struct i2c_adapter *adap, int addr,
-                      unsigned short flags, int kind);
-static int ir_detach(struct i2c_client *client);
-static int ir_probe(struct i2c_adapter *adap);
-
-static struct i2c_driver driver = {
-        .driver = {
-                .name   = "ir-kbd-i2c",
-        },
-        .id             = I2C_DRIVERID_INFRARED,
-        .attach_adapter = ir_probe,
-        .detach_client  = ir_detach,
-};
-
-static struct i2c_client client_template =
-{
-        .name = "unset",
-        .driver = &driver
-};
-
-static int ir_attach(struct i2c_adapter *adap, int addr,
-                     unsigned short flags, int kind)
+static int ir_probe(struct i2c_client *client, const struct i2c_device_id *id)
 {
         IR_KEYTAB_TYPE *ir_codes = NULL;
-        char *name;
+        const char *name = NULL;
         int ir_type;
         struct IR_i2c *ir;
         struct input_dev *input_dev;
+        struct i2c_adapter *adap = client->adapter;
+        unsigned short addr = client->addr;
         int err;
 
         ir = kzalloc(sizeof(struct IR_i2c),GFP_KERNEL);
@@ -332,13 +313,9 @@ static int ir_attach(struct i2c_adapter *adap, int addr,
                 goto err_out_free;
         }
 
-        ir->c = client_template;
+        ir->c = client;
         ir->input = input_dev;
-
-        ir->c.adapter = adap;
-        ir->c.addr    = addr;
-
-        i2c_set_clientdata(&ir->c, ir);
+        i2c_set_clientdata(client, ir);
 
         switch(addr) {
         case 0x64:
@@ -403,44 +380,46 @@ static int ir_attach(struct i2c_adapter *adap, int addr,
                 ir_codes    = ir_codes_avermedia_cardbus;
                 break;
         default:
-                /* shouldn't happen */
-                printk(DEVNAME ": Huh? unknown i2c address (0x%02x)?\n", addr);
+                dprintk(1, DEVNAME ": Unsupported i2c address 0x%02x\n", addr);
                 err = -ENODEV;
                 goto err_out_free;
         }
 
-        /* Sets name */
-        snprintf(ir->c.name, sizeof(ir->c.name), "i2c IR (%s)", name);
-        ir->ir_codes = ir_codes;
+        /* Let the caller override settings */
+        if (client->dev.platform_data) {
+                const struct IR_i2c_init_data *init_data =
+                                                client->dev.platform_data;
 
-        /* register i2c device
-         * At device register, IR codes may be changed to be
-         * board dependent.
-         */
-        err = i2c_attach_client(&ir->c);
-        if (err)
-                goto err_out_free;
+                ir_codes = init_data->ir_codes;
+                name = init_data->name;
+                ir->get_key = init_data->get_key;
+        }
 
-        /* If IR not supported or disabled, unregisters driver */
-        if (ir->get_key == NULL) {
+        /* Make sure we are all setup before going on */
+        if (!name || !ir->get_key || !ir_codes) {
+                dprintk(1, DEVNAME ": Unsupported device at address 0x%02x\n",
+                        addr);
                 err = -ENODEV;
-                goto err_out_detach;
+                goto err_out_free;
         }
 
-        /* Phys addr can only be set after attaching (for ir->c.dev) */
+        /* Sets name */
+        snprintf(ir->name, sizeof(ir->name), "i2c IR (%s)", name);
+        ir->ir_codes = ir_codes;
+
         snprintf(ir->phys, sizeof(ir->phys), "%s/%s/ir0",
-                 dev_name(&ir->c.adapter->dev),
-                 dev_name(&ir->c.dev));
+                 dev_name(&adap->dev),
+                 dev_name(&client->dev));
 
         /* init + register input device */
         ir_input_init(input_dev, &ir->ir, ir_type, ir->ir_codes);
         input_dev->id.bustype = BUS_I2C;
-        input_dev->name       = ir->c.name;
+        input_dev->name       = ir->name;
         input_dev->phys       = ir->phys;
 
         err = input_register_device(ir->input);
         if (err)
-                goto err_out_detach;
+                goto err_out_free;
 
         printk(DEVNAME ": %s detected at %s [%s]\n",
                ir->input->name, ir->input->phys, adap->name);
@@ -451,135 +430,42 @@ static int ir_attach(struct i2c_adapter *adap, int addr,
 
         return 0;
 
- err_out_detach:
-        i2c_detach_client(&ir->c);
  err_out_free:
         input_free_device(input_dev);
         kfree(ir);
         return err;
 }
 
-static int ir_detach(struct i2c_client *client)
+static int ir_remove(struct i2c_client *client)
 {
         struct IR_i2c *ir = i2c_get_clientdata(client);
 
         /* kill outstanding polls */
         cancel_delayed_work_sync(&ir->work);
 
-        /* unregister devices */
+        /* unregister device */
         input_unregister_device(ir->input);
-        i2c_detach_client(&ir->c);
 
         /* free memory */
         kfree(ir);
         return 0;
 }
 
-static int ir_probe(struct i2c_adapter *adap)
-{
-
-        /* The external IR receiver is at i2c address 0x34 (0x35 for
-           reads).  Future Hauppauge cards will have an internal
-           receiver at 0x30 (0x31 for reads).  In theory, both can be
-           fitted, and Hauppauge suggest an external overrides an
-           internal.
-
-           That's why we probe 0x1a (~0x34) first. CB
-        */
-
-        static const int probe_bttv[] = { 0x1a, 0x18, 0x4b, 0x64, 0x30, -1};
-        static const int probe_saa7134[] = { 0x7a, 0x47, 0x71, 0x2d, -1 };
-        static const int probe_em28XX[] = { 0x30, 0x47, -1 };
-        static const int probe_cx88[] = { 0x18, 0x6b, 0x71, -1 };
-        static const int probe_cx23885[] = { 0x6b, -1 };
-        const int *probe;
-        struct i2c_msg msg = {
-                .flags = I2C_M_RD,
-                .len = 0,
-                .buf = NULL,
-        };
-        int i, rc;
-
-        switch (adap->id) {
-        case I2C_HW_B_BT848:
-                probe = probe_bttv;
-                break;
-        case I2C_HW_B_CX2341X:
-                probe = probe_bttv;
-                break;
-        case I2C_HW_SAA7134:
-                probe = probe_saa7134;
-                break;
-        case I2C_HW_B_EM28XX:
-                probe = probe_em28XX;
-                break;
-        case I2C_HW_B_CX2388x:
-                probe = probe_cx88;
-                break;
-        case I2C_HW_B_CX23885:
-                probe = probe_cx23885;
-                break;
-        default:
-                return 0;
-        }
-
-        for (i = 0; -1 != probe[i]; i++) {
-                msg.addr = probe[i];
-                rc = i2c_transfer(adap, &msg, 1);
-                dprintk(1,"probe 0x%02x @ %s: %s\n",
-                        probe[i], adap->name,
-                        (1 == rc) ? "yes" : "no");
-                if (1 == rc) {
-                        ir_attach(adap, probe[i], 0, 0);
-                        return 0;
-                }
-        }
-
-        /* Special case for MSI TV@nywhere Plus remote */
-        if (adap->id == I2C_HW_SAA7134) {
-                u8 temp;
-
-                /* MSI TV@nywhere Plus controller doesn't seem to
-                   respond to probes unless we read something from
-                   an existing device. Weird... */
-
-                msg.addr = 0x50;
-                rc = i2c_transfer(adap, &msg, 1);
-                        dprintk(1, "probe 0x%02x @ %s: %s\n",
-                        msg.addr, adap->name,
-                        (1 == rc) ? "yes" : "no");
-
-                /* Now do the probe. The controller does not respond
-                   to 0-byte reads, so we use a 1-byte read instead. */
-                msg.addr = 0x30;
-                msg.len = 1;
-                msg.buf = &temp;
-                rc = i2c_transfer(adap, &msg, 1);
-                dprintk(1, "probe 0x%02x @ %s: %s\n",
-                        msg.addr, adap->name,
-                        (1 == rc) ? "yes" : "no");
-                if (1 == rc)
-                        ir_attach(adap, msg.addr, 0, 0);
-        }
-
-        /* Special case for AVerMedia Cardbus remote */
-        if (adap->id == I2C_HW_SAA7134) {
-                unsigned char subaddr, data;
-                struct i2c_msg msg[] = { { .addr = 0x40, .flags = 0,
-                                           .buf = &subaddr, .len = 1},
-                                         { .addr = 0x40, .flags = I2C_M_RD,
-                                           .buf = &data, .len = 1} };
-                subaddr = 0x0d;
-                rc = i2c_transfer(adap, msg, 2);
-                dprintk(1, "probe 0x%02x/0x%02x @ %s: %s\n",
-                        msg[0].addr, subaddr, adap->name,
-                        (2 == rc) ? "yes" : "no");
-                if (2 == rc)
-                        ir_attach(adap, msg[0].addr, 0, 0);
-        }
+static const struct i2c_device_id ir_kbd_id[] = {
+        /* Generic entry for any IR receiver */
+        { "ir_video", 0 },
+        /* IR device specific entries could be added here */
+        { }
+};
 
-        return 0;
-}
+static struct i2c_driver driver = {
+        .driver = {
+                .name   = "ir-kbd-i2c",
+        },
+        .probe          = ir_probe,
+        .remove         = ir_remove,
+        .id_table       = ir_kbd_id,
+};
 
 /* ----------------------------------------------------------------------- */
 
diff --git a/drivers/media/video/ivtv/ivtv-driver.c b/drivers/media/video/ivtv/ivtv-driver.c
index db2ac9a99acd..558f8a837ff4 100644
--- a/drivers/media/video/ivtv/ivtv-driver.c
+++ b/drivers/media/video/ivtv/ivtv-driver.c
@@ -455,7 +455,7 @@ static void ivtv_process_eeprom(struct ivtv *itv)
                         break;
         }
         if (tv.tuner_type == TUNER_ABSENT)
-                IVTV_ERR("tveeprom cannot autodetect tuner!");
+                IVTV_ERR("tveeprom cannot autodetect tuner!\n");
 
         if (itv->options.tuner == -1)
                 itv->options.tuner = tv.tuner_type;
@@ -946,17 +946,14 @@ static int __devinit ivtv_probe(struct pci_dev *pdev,
         if (itv == NULL)
                 return -ENOMEM;
         itv->pdev = pdev;
-        itv->instance = atomic_inc_return(&ivtv_instance) - 1;
+        itv->instance = v4l2_device_set_name(&itv->v4l2_dev, "ivtv",
+                                                &ivtv_instance);
 
         retval = v4l2_device_register(&pdev->dev, &itv->v4l2_dev);
         if (retval) {
                 kfree(itv);
                 return retval;
         }
-        /* "ivtv + PCI ID" is a bit of a mouthful, so use
-           "ivtv + instance" instead. */
-        snprintf(itv->v4l2_dev.name, sizeof(itv->v4l2_dev.name),
-                        "ivtv%d", itv->instance);
         IVTV_INFO("Initializing card %d\n", itv->instance);
 
         ivtv_process_options(itv);
diff --git a/drivers/media/video/ivtv/ivtv-i2c.c b/drivers/media/video/ivtv/ivtv-i2c.c
index 9e3d32b8004c..e52aa322b134 100644
--- a/drivers/media/video/ivtv/ivtv-i2c.c
+++ b/drivers/media/video/ivtv/ivtv-i2c.c
@@ -579,9 +579,11 @@ static struct i2c_client ivtv_i2c_client_template = {
         .name = "ivtv internal",
 };
 
-/* init + register i2c algo-bit adapter */
+/* init + register i2c adapter + instantiate IR receiver */
 int init_ivtv_i2c(struct ivtv *itv)
 {
+        int retval;
+
         IVTV_DEBUG_I2C("i2c init\n");
 
         /* Sanity checks for the I2C hardware arrays. They must be the
@@ -619,9 +621,37 @@ int init_ivtv_i2c(struct ivtv *itv)
         ivtv_setsda(itv, 1);
 
         if (itv->options.newi2c > 0)
-                return i2c_add_adapter(&itv->i2c_adap);
+                retval = i2c_add_adapter(&itv->i2c_adap);
         else
-                return i2c_bit_add_bus(&itv->i2c_adap);
+                retval = i2c_bit_add_bus(&itv->i2c_adap);
+
+        /* Instantiate the IR receiver device, if present */
+        if (retval == 0) {
+                struct i2c_board_info info;
+                /* The external IR receiver is at i2c address 0x34 (0x35 for
+                   reads).  Future Hauppauge cards will have an internal
+                   receiver at 0x30 (0x31 for reads).  In theory, both can be
+                   fitted, and Hauppauge suggest an external overrides an
+                   internal.
+
+                   That's why we probe 0x1a (~0x34) first. CB
+                */
+                const unsigned short addr_list[] = {
+                        0x1a,   /* Hauppauge IR external */
+                        0x18,   /* Hauppauge IR internal */
+                        0x71,   /* Hauppauge IR (PVR150) */
+                        0x64,   /* Pixelview IR */
+                        0x30,   /* KNC ONE IR */
+                        0x6b,   /* Adaptec IR */
+                        I2C_CLIENT_END
+                };
+
+                memset(&info, 0, sizeof(struct i2c_board_info));
+                strlcpy(info.type, "ir_video", I2C_NAME_SIZE);
+                i2c_new_probed_device(&itv->i2c_adap, &info, addr_list);
+        }
+
+        return retval;
 }
 
 void exit_ivtv_i2c(struct ivtv *itv)
diff --git a/drivers/media/video/ivtv/ivtv-ioctl.c b/drivers/media/video/ivtv/ivtv-ioctl.c
index c342a9fe983e..99f3c39a118b 100644
--- a/drivers/media/video/ivtv/ivtv-ioctl.c
+++ b/drivers/media/video/ivtv/ivtv-ioctl.c
@@ -709,7 +709,7 @@ static int ivtv_itvc(struct ivtv *itv, unsigned int cmd, void *arg)
         else if (itv->has_cx23415 && regs->reg >= IVTV_DECODER_OFFSET &&
                         regs->reg < IVTV_DECODER_OFFSET + IVTV_DECODER_SIZE)
                 reg_start = itv->dec_mem - IVTV_DECODER_OFFSET;
-        else if (regs->reg >= 0 && regs->reg < IVTV_ENCODER_SIZE)
+        else if (regs->reg < IVTV_ENCODER_SIZE)
                 reg_start = itv->enc_mem;
         else
                 return -EINVAL;
diff --git a/drivers/media/video/mt9m001.c b/drivers/media/video/mt9m001.c
index 684f62fa7897..459c04cbf69d 100644
--- a/drivers/media/video/mt9m001.c
+++ b/drivers/media/video/mt9m001.c
@@ -75,53 +75,50 @@ struct mt9m001 {
         unsigned char autoexposure;
 };
 
-static int reg_read(struct soc_camera_device *icd, const u8 reg)
+static int reg_read(struct i2c_client *client, const u8 reg)
 {
-        struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);
-        struct i2c_client *client = mt9m001->client;
         s32 data = i2c_smbus_read_word_data(client, reg);
         return data < 0 ? data : swab16(data);
 }
 
-static int reg_write(struct soc_camera_device *icd, const u8 reg,
+static int reg_write(struct i2c_client *client, const u8 reg,
                      const u16 data)
 {
-        struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);
-        return i2c_smbus_write_word_data(mt9m001->client, reg, swab16(data));
+        return i2c_smbus_write_word_data(client, reg, swab16(data));
 }
 
-static int reg_set(struct soc_camera_device *icd, const u8 reg,
+static int reg_set(struct i2c_client *client, const u8 reg,
                    const u16 data)
 {
         int ret;
 
-        ret = reg_read(icd, reg);
+        ret = reg_read(client, reg);
         if (ret < 0)
                 return ret;
-        return reg_write(icd, reg, ret | data);
+        return reg_write(client, reg, ret | data);
 }
 
-static int reg_clear(struct soc_camera_device *icd, const u8 reg,
+static int reg_clear(struct i2c_client *client, const u8 reg,
                      const u16 data)
 {
         int ret;
 
-        ret = reg_read(icd, reg);
+        ret = reg_read(client, reg);
         if (ret < 0)
                 return ret;
-        return reg_write(icd, reg, ret & ~data);
+        return reg_write(client, reg, ret & ~data);
 }
 
 static int mt9m001_init(struct soc_camera_device *icd)
 {
-        struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);
-        struct soc_camera_link *icl = mt9m001->client->dev.platform_data;
+        struct i2c_client *client = to_i2c_client(icd->control);
+        struct soc_camera_link *icl = client->dev.platform_data;
         int ret;
 
         dev_dbg(icd->vdev->parent, "%s\n", __func__);
 
         if (icl->power) {
-                ret = icl->power(&mt9m001->client->dev, 1);
+                ret = icl->power(&client->dev, 1);
                 if (ret < 0) {
                         dev_err(icd->vdev->parent,
                                 "Platform failed to power-on the camera.\n");
@@ -131,49 +128,53 @@ static int mt9m001_init(struct soc_camera_device *icd)
 
         /* The camera could have been already on, we reset it additionally */
         if (icl->reset)
-                ret = icl->reset(&mt9m001->client->dev);
+                ret = icl->reset(&client->dev);
         else
                 ret = -ENODEV;
 
         if (ret < 0) {
                 /* Either no platform reset, or platform reset failed */
-                ret = reg_write(icd, MT9M001_RESET, 1);
+                ret = reg_write(client, MT9M001_RESET, 1);
                 if (!ret)
-                        ret = reg_write(icd, MT9M001_RESET, 0);
+                        ret = reg_write(client, MT9M001_RESET, 0);
         }
         /* Disable chip, synchronous option update */
         if (!ret)
-                ret = reg_write(icd, MT9M001_OUTPUT_CONTROL, 0);
+                ret = reg_write(client, MT9M001_OUTPUT_CONTROL, 0);
 
         return ret;
 }
 
 static int mt9m001_release(struct soc_camera_device *icd)
 {
-        struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);
-        struct soc_camera_link *icl = mt9m001->client->dev.platform_data;
+        struct i2c_client *client = to_i2c_client(icd->control);
+        struct soc_camera_link *icl = client->dev.platform_data;
 
         /* Disable the chip */
-        reg_write(icd, MT9M001_OUTPUT_CONTROL, 0);
+        reg_write(client, MT9M001_OUTPUT_CONTROL, 0);
 
         if (icl->power)
-                icl->power(&mt9m001->client->dev, 0);
+                icl->power(&client->dev, 0);
 
         return 0;
 }
 
 static int mt9m001_start_capture(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
+
         /* Switch to master "normal" mode */
-        if (reg_write(icd, MT9M001_OUTPUT_CONTROL, 2) < 0)
+        if (reg_write(client, MT9M001_OUTPUT_CONTROL, 2) < 0)
                 return -EIO;
         return 0;
 }
 
 static int mt9m001_stop_capture(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
+
         /* Stop sensor readout */
-        if (reg_write(icd, MT9M001_OUTPUT_CONTROL, 0) < 0)
+        if (reg_write(client, MT9M001_OUTPUT_CONTROL, 0) < 0)
                 return -EIO;
         return 0;
 }
@@ -222,28 +223,29 @@ static unsigned long mt9m001_query_bus_param(struct soc_camera_device *icd)
 static int mt9m001_set_crop(struct soc_camera_device *icd,
                             struct v4l2_rect *rect)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);
         int ret;
         const u16 hblank = 9, vblank = 25;
 
         /* Blanking and start values - default... */
-        ret = reg_write(icd, MT9M001_HORIZONTAL_BLANKING, hblank);
+        ret = reg_write(client, MT9M001_HORIZONTAL_BLANKING, hblank);
         if (!ret)
-                ret = reg_write(icd, MT9M001_VERTICAL_BLANKING, vblank);
+                ret = reg_write(client, MT9M001_VERTICAL_BLANKING, vblank);
 
         /* The caller provides a supported format, as verified per
          * call to icd->try_fmt() */
         if (!ret)
-                ret = reg_write(icd, MT9M001_COLUMN_START, rect->left);
+                ret = reg_write(client, MT9M001_COLUMN_START, rect->left);
         if (!ret)
-                ret = reg_write(icd, MT9M001_ROW_START, rect->top);
+                ret = reg_write(client, MT9M001_ROW_START, rect->top);
         if (!ret)
-                ret = reg_write(icd, MT9M001_WINDOW_WIDTH, rect->width - 1);
+                ret = reg_write(client, MT9M001_WINDOW_WIDTH, rect->width - 1);
         if (!ret)
-                ret = reg_write(icd, MT9M001_WINDOW_HEIGHT,
+                ret = reg_write(client, MT9M001_WINDOW_HEIGHT,
                                 rect->height + icd->y_skip_top - 1);
         if (!ret && mt9m001->autoexposure) {
-                ret = reg_write(icd, MT9M001_SHUTTER_WIDTH,
+                ret = reg_write(client, MT9M001_SHUTTER_WIDTH,
                                 rect->height + icd->y_skip_top + vblank);
                 if (!ret) {
                         const struct v4l2_queryctrl *qctrl =
@@ -312,16 +314,16 @@ static int mt9m001_get_chip_id(struct soc_camera_device *icd,
 static int mt9m001_get_register(struct soc_camera_device *icd,
                                 struct v4l2_dbg_register *reg)
 {
-        struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);
+        struct i2c_client *client = to_i2c_client(icd->control);
 
         if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
                 return -EINVAL;
 
-        if (reg->match.addr != mt9m001->client->addr)
+        if (reg->match.addr != client->addr)
                 return -ENODEV;
 
         reg->size = 2;
-        reg->val = reg_read(icd, reg->reg);
+        reg->val = reg_read(client, reg->reg);
 
         if (reg->val > 0xffff)
                 return -EIO;
@@ -332,15 +334,15 @@ static int mt9m001_get_register(struct soc_camera_device *icd,
 static int mt9m001_set_register(struct soc_camera_device *icd,
                                 struct v4l2_dbg_register *reg)
 {
-        struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);
+        struct i2c_client *client = to_i2c_client(icd->control);
 
         if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
                 return -EINVAL;
 
-        if (reg->match.addr != mt9m001->client->addr)
+        if (reg->match.addr != client->addr)
                 return -ENODEV;
 
-        if (reg_write(icd, reg->reg, reg->val) < 0)
+        if (reg_write(client, reg->reg, reg->val) < 0)
                 return -EIO;
 
         return 0;
@@ -416,12 +418,13 @@ static struct soc_camera_ops mt9m001_ops = {
 
 static int mt9m001_get_control(struct soc_camera_device *icd, struct v4l2_control *ctrl)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);
         int data;
 
         switch (ctrl->id) {
         case V4L2_CID_VFLIP:
-                data = reg_read(icd, MT9M001_READ_OPTIONS2);
+                data = reg_read(client, MT9M001_READ_OPTIONS2);
                 if (data < 0)
                         return -EIO;
                 ctrl->value = !!(data & 0x8000);
@@ -435,6 +438,7 @@ static int mt9m001_get_control(struct soc_camera_device *icd, struct v4l2_contro
 
 static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_control *ctrl)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);
         const struct v4l2_queryctrl *qctrl;
         int data;
@@ -447,9 +451,9 @@ static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_contro
         switch (ctrl->id) {
         case V4L2_CID_VFLIP:
                 if (ctrl->value)
-                        data = reg_set(icd, MT9M001_READ_OPTIONS2, 0x8000);
+                        data = reg_set(client, MT9M001_READ_OPTIONS2, 0x8000);
                 else
-                        data = reg_clear(icd, MT9M001_READ_OPTIONS2, 0x8000);
+                        data = reg_clear(client, MT9M001_READ_OPTIONS2, 0x8000);
                 if (data < 0)
                         return -EIO;
                 break;
@@ -463,7 +467,7 @@ static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_contro
                         data = ((ctrl->value - qctrl->minimum) * 8 + range / 2) / range;
 
                         dev_dbg(&icd->dev, "Setting gain %d\n", data);
-                        data = reg_write(icd, MT9M001_GLOBAL_GAIN, data);
+                        data = reg_write(client, MT9M001_GLOBAL_GAIN, data);
                         if (data < 0)
                                 return -EIO;
                 } else {
@@ -481,8 +485,8 @@ static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_contro
                                 data = ((gain - 64) * 7 + 28) / 56 + 96;
 
                         dev_dbg(&icd->dev, "Setting gain from %d to %d\n",
-                                 reg_read(icd, MT9M001_GLOBAL_GAIN), data);
-                        data = reg_write(icd, MT9M001_GLOBAL_GAIN, data);
+                                 reg_read(client, MT9M001_GLOBAL_GAIN), data);
+                        data = reg_write(client, MT9M001_GLOBAL_GAIN, data);
                         if (data < 0)
                                 return -EIO;
                 }
@@ -500,8 +504,8 @@ static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_contro
                                                  range / 2) / range + 1;
 
                         dev_dbg(&icd->dev, "Setting shutter width from %d to %lu\n",
-                                 reg_read(icd, MT9M001_SHUTTER_WIDTH), shutter);
-                        if (reg_write(icd, MT9M001_SHUTTER_WIDTH, shutter) < 0)
+                                 reg_read(client, MT9M001_SHUTTER_WIDTH), shutter);
+                        if (reg_write(client, MT9M001_SHUTTER_WIDTH, shutter) < 0)
                                 return -EIO;
                         icd->exposure = ctrl->value;
                         mt9m001->autoexposure = 0;
@@ -510,7 +514,7 @@ static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_contro
         case V4L2_CID_EXPOSURE_AUTO:
                 if (ctrl->value) {
                         const u16 vblank = 25;
-                        if (reg_write(icd, MT9M001_SHUTTER_WIDTH, icd->height +
+                        if (reg_write(client, MT9M001_SHUTTER_WIDTH, icd->height +
                                       icd->y_skip_top + vblank) < 0)
                                 return -EIO;
                         qctrl = soc_camera_find_qctrl(icd->ops, V4L2_CID_EXPOSURE);
@@ -529,8 +533,9 @@ static int mt9m001_set_control(struct soc_camera_device *icd, struct v4l2_contro
  * this wasn't our capture interface, so, we wait for the right one */
 static int mt9m001_video_probe(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);
-        struct soc_camera_link *icl = mt9m001->client->dev.platform_data;
+        struct soc_camera_link *icl = client->dev.platform_data;
         s32 data;
         int ret;
         unsigned long flags;
@@ -542,11 +547,11 @@ static int mt9m001_video_probe(struct soc_camera_device *icd)
                 return -ENODEV;
 
         /* Enable the chip */
-        data = reg_write(icd, MT9M001_CHIP_ENABLE, 1);
+        data = reg_write(client, MT9M001_CHIP_ENABLE, 1);
         dev_dbg(&icd->dev, "write: %d\n", data);
 
         /* Read out the chip version register */
-        data = reg_read(icd, MT9M001_CHIP_VERSION);
+        data = reg_read(client, MT9M001_CHIP_VERSION);
 
         /* must be 0x8411 or 0x8421 for colour sensor and 8431 for bw */
         switch (data) {
@@ -604,10 +609,13 @@ ei2c:
 static void mt9m001_video_remove(struct soc_camera_device *icd)
 {
         struct mt9m001 *mt9m001 = container_of(icd, struct mt9m001, icd);
+        struct soc_camera_link *icl = mt9m001->client->dev.platform_data;
 
         dev_dbg(&icd->dev, "Video %x removed: %p, %p\n", mt9m001->client->addr,
                 icd->dev.parent, icd->vdev);
         soc_camera_video_stop(icd);
+        if (icl->free_bus)
+                icl->free_bus(icl);
 }
 
 static int mt9m001_probe(struct i2c_client *client,
diff --git a/drivers/media/video/mt9m111.c b/drivers/media/video/mt9m111.c
index cdd1ddb51388..fc5e2de03766 100644
--- a/drivers/media/video/mt9m111.c
+++ b/drivers/media/video/mt9m111.c
@@ -113,10 +113,10 @@
  * mt9m111: Camera control register addresses (0x200..0x2ff not implemented)
  */
 
-#define reg_read(reg) mt9m111_reg_read(icd, MT9M111_##reg)
-#define reg_write(reg, val) mt9m111_reg_write(icd, MT9M111_##reg, (val))
-#define reg_set(reg, val) mt9m111_reg_set(icd, MT9M111_##reg, (val))
-#define reg_clear(reg, val) mt9m111_reg_clear(icd, MT9M111_##reg, (val))
+#define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg)
+#define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val))
+#define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val))
+#define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val))
 
 #define MT9M111_MIN_DARK_ROWS   8
 #define MT9M111_MIN_DARK_COLS   24
@@ -184,58 +184,55 @@ static int reg_page_map_set(struct i2c_client *client, const u16 reg)
         return ret;
 }
 
-static int mt9m111_reg_read(struct soc_camera_device *icd, const u16 reg)
+static int mt9m111_reg_read(struct i2c_client *client, const u16 reg)
 {
-        struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
-        struct i2c_client *client = mt9m111->client;
         int ret;
 
         ret = reg_page_map_set(client, reg);
         if (!ret)
                 ret = swab16(i2c_smbus_read_word_data(client, (reg & 0xff)));
 
-        dev_dbg(&icd->dev, "read  reg.%03x -> %04x\n", reg, ret);
+        dev_dbg(&client->dev, "read  reg.%03x -> %04x\n", reg, ret);
         return ret;
 }
 
-static int mt9m111_reg_write(struct soc_camera_device *icd, const u16 reg,
+static int mt9m111_reg_write(struct i2c_client *client, const u16 reg,
                              const u16 data)
 {
-        struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
-        struct i2c_client *client = mt9m111->client;
         int ret;
 
         ret = reg_page_map_set(client, reg);
         if (!ret)
-                ret = i2c_smbus_write_word_data(mt9m111->client, (reg & 0xff),
+                ret = i2c_smbus_write_word_data(client, (reg & 0xff),
                                                 swab16(data));
-        dev_dbg(&icd->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret);
+        dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret);
         return ret;
 }
 
-static int mt9m111_reg_set(struct soc_camera_device *icd, const u16 reg,
+static int mt9m111_reg_set(struct i2c_client *client, const u16 reg,
                            const u16 data)
 {
         int ret;
 
-        ret = mt9m111_reg_read(icd, reg);
+        ret = mt9m111_reg_read(client, reg);
         if (ret >= 0)
-                ret = mt9m111_reg_write(icd, reg, ret | data);
+                ret = mt9m111_reg_write(client, reg, ret | data);
         return ret;
 }
 
-static int mt9m111_reg_clear(struct soc_camera_device *icd, const u16 reg,
+static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg,
                              const u16 data)
 {
         int ret;
 
-        ret = mt9m111_reg_read(icd, reg);
-        return mt9m111_reg_write(icd, reg, ret & ~data);
+        ret = mt9m111_reg_read(client, reg);
+        return mt9m111_reg_write(client, reg, ret & ~data);
 }
 
 static int mt9m111_set_context(struct soc_camera_device *icd,
                                enum mt9m111_context ctxt)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         int valB = MT9M111_CTXT_CTRL_RESTART | MT9M111_CTXT_CTRL_DEFECTCOR_B
                 | MT9M111_CTXT_CTRL_RESIZE_B | MT9M111_CTXT_CTRL_CTRL2_B
                 | MT9M111_CTXT_CTRL_GAMMA_B | MT9M111_CTXT_CTRL_READ_MODE_B
@@ -252,6 +249,7 @@ static int mt9m111_set_context(struct soc_camera_device *icd,
 static int mt9m111_setup_rect(struct soc_camera_device *icd,
                               struct v4l2_rect *rect)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
         int ret, is_raw_format;
         int width = rect->width;
@@ -296,6 +294,7 @@ static int mt9m111_setup_rect(struct soc_camera_device *icd,
 
 static int mt9m111_setup_pixfmt(struct soc_camera_device *icd, u16 outfmt)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         int ret;
 
         ret = reg_write(OUTPUT_FORMAT_CTRL2_A, outfmt);
@@ -357,12 +356,13 @@ static int mt9m111_setfmt_yuv(struct soc_camera_device *icd)
 
 static int mt9m111_enable(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
-        struct soc_camera_link *icl = mt9m111->client->dev.platform_data;
+        struct soc_camera_link *icl = client->dev.platform_data;
         int ret;
 
         if (icl->power) {
-                ret = icl->power(&mt9m111->client->dev, 1);
+                ret = icl->power(&client->dev, 1);
                 if (ret < 0) {
                         dev_err(icd->vdev->parent,
                                 "Platform failed to power-on the camera.\n");
@@ -378,8 +378,9 @@ static int mt9m111_enable(struct soc_camera_device *icd)
 
 static int mt9m111_disable(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
-        struct soc_camera_link *icl = mt9m111->client->dev.platform_data;
+        struct soc_camera_link *icl = client->dev.platform_data;
         int ret;
 
         ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
@@ -387,15 +388,15 @@ static int mt9m111_disable(struct soc_camera_device *icd)
                 mt9m111->powered = 0;
 
         if (icl->power)
-                icl->power(&mt9m111->client->dev, 0);
+                icl->power(&client->dev, 0);
 
         return ret;
 }
 
 static int mt9m111_reset(struct soc_camera_device *icd)
 {
-        struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
-        struct soc_camera_link *icl = mt9m111->client->dev.platform_data;
+        struct i2c_client *client = to_i2c_client(icd->control);
+        struct soc_camera_link *icl = client->dev.platform_data;
         int ret;
 
         ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
@@ -406,7 +407,7 @@ static int mt9m111_reset(struct soc_camera_device *icd)
                                 | MT9M111_RESET_RESET_SOC);
 
         if (icl->reset)
-                icl->reset(&mt9m111->client->dev);
+                icl->reset(&client->dev);
 
         return ret;
 }
@@ -562,15 +563,14 @@ static int mt9m111_get_register(struct soc_camera_device *icd,
                                 struct v4l2_dbg_register *reg)
 {
         int val;
-
-        struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
+        struct i2c_client *client = to_i2c_client(icd->control);
 
         if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff)
                 return -EINVAL;
-        if (reg->match.addr != mt9m111->client->addr)
+        if (reg->match.addr != client->addr)
                 return -ENODEV;
 
-        val = mt9m111_reg_read(icd, reg->reg);
+        val = mt9m111_reg_read(client, reg->reg);
         reg->size = 2;
         reg->val = (u64)val;
 
@@ -583,15 +583,15 @@ static int mt9m111_get_register(struct soc_camera_device *icd,
 static int mt9m111_set_register(struct soc_camera_device *icd,
                                 struct v4l2_dbg_register *reg)
 {
-        struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
+        struct i2c_client *client = to_i2c_client(icd->control);
 
         if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff)
                 return -EINVAL;
 
-        if (reg->match.addr != mt9m111->client->addr)
+        if (reg->match.addr != client->addr)
                 return -ENODEV;
 
-        if (mt9m111_reg_write(icd, reg->reg, reg->val) < 0)
+        if (mt9m111_reg_write(client, reg->reg, reg->val) < 0)
                 return -EIO;
 
         return 0;
@@ -672,6 +672,7 @@ static struct soc_camera_ops mt9m111_ops = {
 
 static int mt9m111_set_flip(struct soc_camera_device *icd, int flip, int mask)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
         int ret;
 
@@ -692,6 +693,7 @@ static int mt9m111_set_flip(struct soc_camera_device *icd, int flip, int mask)
 
 static int mt9m111_get_global_gain(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         int data;
 
         data = reg_read(GLOBAL_GAIN);
@@ -703,6 +705,7 @@ static int mt9m111_get_global_gain(struct soc_camera_device *icd)
 
 static int mt9m111_set_global_gain(struct soc_camera_device *icd, int gain)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         u16 val;
 
         if (gain > 63 * 2 * 2)
@@ -721,6 +724,7 @@ static int mt9m111_set_global_gain(struct soc_camera_device *icd, int gain)
 
 static int mt9m111_set_autoexposure(struct soc_camera_device *icd, int on)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
         int ret;
 
@@ -737,6 +741,7 @@ static int mt9m111_set_autoexposure(struct soc_camera_device *icd, int on)
 
 static int mt9m111_set_autowhitebalance(struct soc_camera_device *icd, int on)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
         int ret;
 
@@ -754,6 +759,7 @@ static int mt9m111_set_autowhitebalance(struct soc_camera_device *icd, int on)
 static int mt9m111_get_control(struct soc_camera_device *icd,
                                struct v4l2_control *ctrl)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
         int data;
 
@@ -898,6 +904,7 @@ static int mt9m111_release(struct soc_camera_device *icd)
  */
 static int mt9m111_video_probe(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9m111 *mt9m111 = container_of(icd, struct mt9m111, icd);
         s32 data;
         int ret;
diff --git a/drivers/media/video/mt9t031.c b/drivers/media/video/mt9t031.c
index 2b0927bfd217..f72aeb7c4deb 100644
--- a/drivers/media/video/mt9t031.c
+++ b/drivers/media/video/mt9t031.c
@@ -76,64 +76,61 @@ struct mt9t031 {
         u16 yskip;
 };
 
-static int reg_read(struct soc_camera_device *icd, const u8 reg)
+static int reg_read(struct i2c_client *client, const u8 reg)
 {
-        struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd);
-        struct i2c_client *client = mt9t031->client;
         s32 data = i2c_smbus_read_word_data(client, reg);
         return data < 0 ? data : swab16(data);
 }
 
-static int reg_write(struct soc_camera_device *icd, const u8 reg,
+static int reg_write(struct i2c_client *client, const u8 reg,
                      const u16 data)
 {
-        struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd);
-        return i2c_smbus_write_word_data(mt9t031->client, reg, swab16(data));
+        return i2c_smbus_write_word_data(client, reg, swab16(data));
 }
 
-static int reg_set(struct soc_camera_device *icd, const u8 reg,
+static int reg_set(struct i2c_client *client, const u8 reg,
                    const u16 data)
 {
         int ret;
 
-        ret = reg_read(icd, reg);
+        ret = reg_read(client, reg);
         if (ret < 0)
                 return ret;
-        return reg_write(icd, reg, ret | data);
+        return reg_write(client, reg, ret | data);
 }
 
-static int reg_clear(struct soc_camera_device *icd, const u8 reg,
+static int reg_clear(struct i2c_client *client, const u8 reg,
                      const u16 data)
 {
         int ret;
 
-        ret = reg_read(icd, reg);
+        ret = reg_read(client, reg);
         if (ret < 0)
                 return ret;
-        return reg_write(icd, reg, ret & ~data);
+        return reg_write(client, reg, ret & ~data);
 }
 
-static int set_shutter(struct soc_camera_device *icd, const u32 data)
+static int set_shutter(struct i2c_client *client, const u32 data)
 {
         int ret;
 
-        ret = reg_write(icd, MT9T031_SHUTTER_WIDTH_UPPER, data >> 16);
+        ret = reg_write(client, MT9T031_SHUTTER_WIDTH_UPPER, data >> 16);
 
         if (ret >= 0)
-                ret = reg_write(icd, MT9T031_SHUTTER_WIDTH, data & 0xffff);
+                ret = reg_write(client, MT9T031_SHUTTER_WIDTH, data & 0xffff);
 
         return ret;
 }
 
-static int get_shutter(struct soc_camera_device *icd, u32 *data)
+static int get_shutter(struct i2c_client *client, u32 *data)
 {
         int ret;
 
-        ret = reg_read(icd, MT9T031_SHUTTER_WIDTH_UPPER);
+        ret = reg_read(client, MT9T031_SHUTTER_WIDTH_UPPER);
         *data = ret << 16;
 
         if (ret >= 0)
-                ret = reg_read(icd, MT9T031_SHUTTER_WIDTH);
+                ret = reg_read(client, MT9T031_SHUTTER_WIDTH);
         *data |= ret & 0xffff;
 
         return ret < 0 ? ret : 0;
@@ -141,12 +138,12 @@ static int get_shutter(struct soc_camera_device *icd, u32 *data)
 
 static int mt9t031_init(struct soc_camera_device *icd)
 {
-        struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd);
-        struct soc_camera_link *icl = mt9t031->client->dev.platform_data;
+        struct i2c_client *client = to_i2c_client(icd->control);
+        struct soc_camera_link *icl = client->dev.platform_data;
         int ret;
 
         if (icl->power) {
-                ret = icl->power(&mt9t031->client->dev, 1);
+                ret = icl->power(&client->dev, 1);
                 if (ret < 0) {
                         dev_err(icd->vdev->parent,
                                 "Platform failed to power-on the camera.\n");
@@ -155,44 +152,48 @@ static int mt9t031_init(struct soc_camera_device *icd)
         }
 
         /* Disable chip output, synchronous option update */
-        ret = reg_write(icd, MT9T031_RESET, 1);
+        ret = reg_write(client, MT9T031_RESET, 1);
         if (ret >= 0)
-                ret = reg_write(icd, MT9T031_RESET, 0);
+                ret = reg_write(client, MT9T031_RESET, 0);
         if (ret >= 0)
-                ret = reg_clear(icd, MT9T031_OUTPUT_CONTROL, 2);
+                ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 2);
 
         if (ret < 0 && icl->power)
-                icl->power(&mt9t031->client->dev, 0);
+                icl->power(&client->dev, 0);
 
         return ret >= 0 ? 0 : -EIO;
 }
 
 static int mt9t031_release(struct soc_camera_device *icd)
 {
-        struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd);
-        struct soc_camera_link *icl = mt9t031->client->dev.platform_data;
+        struct i2c_client *client = to_i2c_client(icd->control);
+        struct soc_camera_link *icl = client->dev.platform_data;
 
         /* Disable the chip */
-        reg_clear(icd, MT9T031_OUTPUT_CONTROL, 2);
+        reg_clear(client, MT9T031_OUTPUT_CONTROL, 2);
 
         if (icl->power)
-                icl->power(&mt9t031->client->dev, 0);
+                icl->power(&client->dev, 0);
 
         return 0;
 }
 
 static int mt9t031_start_capture(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
+
         /* Switch to master "normal" mode */
-        if (reg_set(icd, MT9T031_OUTPUT_CONTROL, 2) < 0)
+        if (reg_set(client, MT9T031_OUTPUT_CONTROL, 2) < 0)
                 return -EIO;
         return 0;
 }
 
 static int mt9t031_stop_capture(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
+
         /* Stop sensor readout */
-        if (reg_clear(icd, MT9T031_OUTPUT_CONTROL, 2) < 0)
+        if (reg_clear(client, MT9T031_OUTPUT_CONTROL, 2) < 0)
                 return -EIO;
         return 0;
 }
@@ -200,14 +201,16 @@ static int mt9t031_stop_capture(struct soc_camera_device *icd)
 static int mt9t031_set_bus_param(struct soc_camera_device *icd,
                                  unsigned long flags)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
+
         /* The caller should have queried our parameters, check anyway */
         if (flags & ~MT9T031_BUS_PARAM)
                 return -EINVAL;
 
         if (flags & SOCAM_PCLK_SAMPLE_FALLING)
-                reg_clear(icd, MT9T031_PIXEL_CLOCK_CONTROL, 0x8000);
+                reg_clear(client, MT9T031_PIXEL_CLOCK_CONTROL, 0x8000);
         else
-                reg_set(icd, MT9T031_PIXEL_CLOCK_CONTROL, 0x8000);
+                reg_set(client, MT9T031_PIXEL_CLOCK_CONTROL, 0x8000);
 
         return 0;
 }
@@ -235,6 +238,7 @@ static void recalculate_limits(struct soc_camera_device *icd,
 static int mt9t031_set_params(struct soc_camera_device *icd,
                               struct v4l2_rect *rect, u16 xskip, u16 yskip)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd);
         int ret;
         u16 xbin, ybin, width, height, left, top;
@@ -277,22 +281,22 @@ static int mt9t031_set_params(struct soc_camera_device *icd,
         }
 
         /* Disable register update, reconfigure atomically */
-        ret = reg_set(icd, MT9T031_OUTPUT_CONTROL, 1);
+        ret = reg_set(client, MT9T031_OUTPUT_CONTROL, 1);
         if (ret < 0)
                 return ret;
 
         /* Blanking and start values - default... */
-        ret = reg_write(icd, MT9T031_HORIZONTAL_BLANKING, hblank);
+        ret = reg_write(client, MT9T031_HORIZONTAL_BLANKING, hblank);
         if (ret >= 0)
-                ret = reg_write(icd, MT9T031_VERTICAL_BLANKING, vblank);
+                ret = reg_write(client, MT9T031_VERTICAL_BLANKING, vblank);
 
         if (yskip != mt9t031->yskip || xskip != mt9t031->xskip) {
                 /* Binning, skipping */
                 if (ret >= 0)
-                        ret = reg_write(icd, MT9T031_COLUMN_ADDRESS_MODE,
+                        ret = reg_write(client, MT9T031_COLUMN_ADDRESS_MODE,
                                         ((xbin - 1) << 4) | (xskip - 1));
                 if (ret >= 0)
-                        ret = reg_write(icd, MT9T031_ROW_ADDRESS_MODE,
+                        ret = reg_write(client, MT9T031_ROW_ADDRESS_MODE,
                                         ((ybin - 1) << 4) | (yskip - 1));
         }
         dev_dbg(&icd->dev, "new physical left %u, top %u\n", left, top);
@@ -300,16 +304,16 @@ static int mt9t031_set_params(struct soc_camera_device *icd,
         /* The caller provides a supported format, as guaranteed by
          * icd->try_fmt_cap(), soc_camera_s_crop() and soc_camera_cropcap() */
         if (ret >= 0)
-                ret = reg_write(icd, MT9T031_COLUMN_START, left);
+                ret = reg_write(client, MT9T031_COLUMN_START, left);
         if (ret >= 0)
-                ret = reg_write(icd, MT9T031_ROW_START, top);
+                ret = reg_write(client, MT9T031_ROW_START, top);
         if (ret >= 0)
-                ret = reg_write(icd, MT9T031_WINDOW_WIDTH, width - 1);
+                ret = reg_write(client, MT9T031_WINDOW_WIDTH, width - 1);
         if (ret >= 0)
-                ret = reg_write(icd, MT9T031_WINDOW_HEIGHT,
+                ret = reg_write(client, MT9T031_WINDOW_HEIGHT,
                                 height + icd->y_skip_top - 1);
         if (ret >= 0 && mt9t031->autoexposure) {
-                ret = set_shutter(icd, height + icd->y_skip_top + vblank);
+                ret = set_shutter(client, height + icd->y_skip_top + vblank);
                 if (ret >= 0) {
                         const u32 shutter_max = MT9T031_MAX_HEIGHT + vblank;
                         const struct v4l2_queryctrl *qctrl =
@@ -324,7 +328,7 @@ static int mt9t031_set_params(struct soc_camera_device *icd,
 
         /* Re-enable register update, commit all changes */
         if (ret >= 0)
-                ret = reg_clear(icd, MT9T031_OUTPUT_CONTROL, 1);
+                ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 1);
 
         return ret < 0 ? ret : 0;
 }
@@ -417,15 +421,15 @@ static int mt9t031_get_chip_id(struct soc_camera_device *icd,
 static int mt9t031_get_register(struct soc_camera_device *icd,
                                 struct v4l2_dbg_register *reg)
 {
-        struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd);
+        struct i2c_client *client = to_i2c_client(icd->control);
 
         if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
                 return -EINVAL;
 
-        if (reg->match.addr != mt9t031->client->addr)
+        if (reg->match.addr != client->addr)
                 return -ENODEV;
 
-        reg->val = reg_read(icd, reg->reg);
+        reg->val = reg_read(client, reg->reg);
 
         if (reg->val > 0xffff)
                 return -EIO;
@@ -436,15 +440,15 @@ static int mt9t031_get_register(struct soc_camera_device *icd,
 static int mt9t031_set_register(struct soc_camera_device *icd,
                                 struct v4l2_dbg_register *reg)
 {
-        struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd);
+        struct i2c_client *client = to_i2c_client(icd->control);
 
         if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
                 return -EINVAL;
 
-        if (reg->match.addr != mt9t031->client->addr)
+        if (reg->match.addr != client->addr)
                 return -ENODEV;
 
-        if (reg_write(icd, reg->reg, reg->val) < 0)
+        if (reg_write(client, reg->reg, reg->val) < 0)
                 return -EIO;
 
         return 0;
@@ -528,18 +532,19 @@ static struct soc_camera_ops mt9t031_ops = {
 
 static int mt9t031_get_control(struct soc_camera_device *icd, struct v4l2_control *ctrl)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd);
         int data;
 
         switch (ctrl->id) {
         case V4L2_CID_VFLIP:
-                data = reg_read(icd, MT9T031_READ_MODE_2);
+                data = reg_read(client, MT9T031_READ_MODE_2);
                 if (data < 0)
                         return -EIO;
                 ctrl->value = !!(data & 0x8000);
                 break;
         case V4L2_CID_HFLIP:
-                data = reg_read(icd, MT9T031_READ_MODE_2);
+                data = reg_read(client, MT9T031_READ_MODE_2);
                 if (data < 0)
                         return -EIO;
                 ctrl->value = !!(data & 0x4000);
@@ -553,6 +558,7 @@ static int mt9t031_get_control(struct soc_camera_device *icd, struct v4l2_contro
 
 static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_control *ctrl)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd);
         const struct v4l2_queryctrl *qctrl;
         int data;
@@ -565,17 +571,17 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro
         switch (ctrl->id) {
         case V4L2_CID_VFLIP:
                 if (ctrl->value)
-                        data = reg_set(icd, MT9T031_READ_MODE_2, 0x8000);
+                        data = reg_set(client, MT9T031_READ_MODE_2, 0x8000);
                 else
-                        data = reg_clear(icd, MT9T031_READ_MODE_2, 0x8000);
+                        data = reg_clear(client, MT9T031_READ_MODE_2, 0x8000);
                 if (data < 0)
                         return -EIO;
                 break;
         case V4L2_CID_HFLIP:
                 if (ctrl->value)
-                        data = reg_set(icd, MT9T031_READ_MODE_2, 0x4000);
+                        data = reg_set(client, MT9T031_READ_MODE_2, 0x4000);
                 else
-                        data = reg_clear(icd, MT9T031_READ_MODE_2, 0x4000);
+                        data = reg_clear(client, MT9T031_READ_MODE_2, 0x4000);
                 if (data < 0)
                         return -EIO;
                 break;
@@ -589,7 +595,7 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro
                         data = ((ctrl->value - qctrl->minimum) * 8 + range / 2) / range;
 
                         dev_dbg(&icd->dev, "Setting gain %d\n", data);
-                        data = reg_write(icd, MT9T031_GLOBAL_GAIN, data);
+                        data = reg_write(client, MT9T031_GLOBAL_GAIN, data);
                         if (data < 0)
                                 return -EIO;
                 } else {
@@ -609,8 +615,8 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro
                                 data = (((gain - 64 + 7) * 32) & 0xff00) | 0x60;
 
                         dev_dbg(&icd->dev, "Setting gain from 0x%x to 0x%x\n",
-                                reg_read(icd, MT9T031_GLOBAL_GAIN), data);
-                        data = reg_write(icd, MT9T031_GLOBAL_GAIN, data);
+                                reg_read(client, MT9T031_GLOBAL_GAIN), data);
+                        data = reg_write(client, MT9T031_GLOBAL_GAIN, data);
                         if (data < 0)
                                 return -EIO;
                 }
@@ -628,10 +634,10 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro
                                              range / 2) / range + 1;
                         u32 old;
 
-                        get_shutter(icd, &old);
+                        get_shutter(client, &old);
                         dev_dbg(&icd->dev, "Setting shutter width from %u to %u\n",
                                 old, shutter);
-                        if (set_shutter(icd, shutter) < 0)
+                        if (set_shutter(client, shutter) < 0)
                                 return -EIO;
                         icd->exposure = ctrl->value;
                         mt9t031->autoexposure = 0;
@@ -641,7 +647,7 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro
                 if (ctrl->value) {
                         const u16 vblank = MT9T031_VERTICAL_BLANK;
                         const u32 shutter_max = MT9T031_MAX_HEIGHT + vblank;
-                        if (set_shutter(icd, icd->height +
+                        if (set_shutter(client, icd->height +
                                         icd->y_skip_top + vblank) < 0)
                                 return -EIO;
                         qctrl = soc_camera_find_qctrl(icd->ops, V4L2_CID_EXPOSURE);
@@ -661,6 +667,7 @@ static int mt9t031_set_control(struct soc_camera_device *icd, struct v4l2_contro
  * this wasn't our capture interface, so, we wait for the right one */
 static int mt9t031_video_probe(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9t031 *mt9t031 = container_of(icd, struct mt9t031, icd);
         s32 data;
         int ret;
@@ -672,11 +679,11 @@ static int mt9t031_video_probe(struct soc_camera_device *icd)
                 return -ENODEV;
 
         /* Enable the chip */
-        data = reg_write(icd, MT9T031_CHIP_ENABLE, 1);
+        data = reg_write(client, MT9T031_CHIP_ENABLE, 1);
         dev_dbg(&icd->dev, "write: %d\n", data);
 
         /* Read out the chip version register */
-        data = reg_read(icd, MT9T031_CHIP_VERSION);
+        data = reg_read(client, MT9T031_CHIP_VERSION);
 
         switch (data) {
         case 0x1621:
diff --git a/drivers/media/video/mt9v022.c b/drivers/media/video/mt9v022.c
index 4d3b4813c322..be20d312b1dc 100644
--- a/drivers/media/video/mt9v022.c
+++ b/drivers/media/video/mt9v022.c
@@ -91,51 +91,49 @@ struct mt9v022 {
         u16 chip_control;
 };
 
-static int reg_read(struct soc_camera_device *icd, const u8 reg)
+static int reg_read(struct i2c_client *client, const u8 reg)
 {
-        struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd);
-        struct i2c_client *client = mt9v022->client;
         s32 data = i2c_smbus_read_word_data(client, reg);
         return data < 0 ? data : swab16(data);
 }
 
-static int reg_write(struct soc_camera_device *icd, const u8 reg,
+static int reg_write(struct i2c_client *client, const u8 reg,
                      const u16 data)
 {
-        struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd);
-        return i2c_smbus_write_word_data(mt9v022->client, reg, swab16(data));
+        return i2c_smbus_write_word_data(client, reg, swab16(data));
 }
 
-static int reg_set(struct soc_camera_device *icd, const u8 reg,
+static int reg_set(struct i2c_client *client, const u8 reg,
                    const u16 data)
 {
         int ret;
 
-        ret = reg_read(icd, reg);
+        ret = reg_read(client, reg);
         if (ret < 0)
                 return ret;
-        return reg_write(icd, reg, ret | data);
+        return reg_write(client, reg, ret | data);
 }
 
-static int reg_clear(struct soc_camera_device *icd, const u8 reg,
+static int reg_clear(struct i2c_client *client, const u8 reg,
                      const u16 data)
 {
         int ret;
 
-        ret = reg_read(icd, reg);
+        ret = reg_read(client, reg);
         if (ret < 0)
                 return ret;
-        return reg_write(icd, reg, ret & ~data);
+        return reg_write(client, reg, ret & ~data);
 }
 
 static int mt9v022_init(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd);
-        struct soc_camera_link *icl = mt9v022->client->dev.platform_data;
+        struct soc_camera_link *icl = client->dev.platform_data;
         int ret;
 
         if (icl->power) {
-                ret = icl->power(&mt9v022->client->dev, 1);
+                ret = icl->power(&client->dev, 1);
                 if (ret < 0) {
                         dev_err(icd->vdev->parent,
                                 "Platform failed to power-on the camera.\n");
@@ -148,27 +146,27 @@ static int mt9v022_init(struct soc_camera_device *icd)
          * if available. Soft reset is done in video_probe().
          */
         if (icl->reset)
-                icl->reset(&mt9v022->client->dev);
+                icl->reset(&client->dev);
 
         /* Almost the default mode: master, parallel, simultaneous, and an
          * undocumented bit 0x200, which is present in table 7, but not in 8,
          * plus snapshot mode to disable scan for now */
         mt9v022->chip_control |= 0x10;
-        ret = reg_write(icd, MT9V022_CHIP_CONTROL, mt9v022->chip_control);
+        ret = reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control);
         if (!ret)
-                ret = reg_write(icd, MT9V022_READ_MODE, 0x300);
+                ret = reg_write(client, MT9V022_READ_MODE, 0x300);
 
         /* All defaults */
         if (!ret)
                 /* AEC, AGC on */
-                ret = reg_set(icd, MT9V022_AEC_AGC_ENABLE, 0x3);
+                ret = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x3);
         if (!ret)
-                ret = reg_write(icd, MT9V022_MAX_TOTAL_SHUTTER_WIDTH, 480);
+                ret = reg_write(client, MT9V022_MAX_TOTAL_SHUTTER_WIDTH, 480);
         if (!ret)
                 /* default - auto */
-                ret = reg_clear(icd, MT9V022_BLACK_LEVEL_CALIB_CTRL, 1);
+                ret = reg_clear(client, MT9V022_BLACK_LEVEL_CALIB_CTRL, 1);
         if (!ret)
-                ret = reg_write(icd, MT9V022_DIGITAL_TEST_PATTERN, 0);
+                ret = reg_write(client, MT9V022_DIGITAL_TEST_PATTERN, 0);
 
         return ret;
 }
@@ -186,10 +184,11 @@ static int mt9v022_release(struct soc_camera_device *icd)
 
 static int mt9v022_start_capture(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd);
         /* Switch to master "normal" mode */
         mt9v022->chip_control &= ~0x10;
-        if (reg_write(icd, MT9V022_CHIP_CONTROL,
+        if (reg_write(client, MT9V022_CHIP_CONTROL,
                       mt9v022->chip_control) < 0)
                 return -EIO;
         return 0;
@@ -197,10 +196,11 @@ static int mt9v022_start_capture(struct soc_camera_device *icd)
 
 static int mt9v022_stop_capture(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd);
         /* Switch to snapshot mode */
         mt9v022->chip_control |= 0x10;
-        if (reg_write(icd, MT9V022_CHIP_CONTROL,
+        if (reg_write(client, MT9V022_CHIP_CONTROL,
                       mt9v022->chip_control) < 0)
                 return -EIO;
         return 0;
@@ -209,8 +209,9 @@ static int mt9v022_stop_capture(struct soc_camera_device *icd)
 static int mt9v022_set_bus_param(struct soc_camera_device *icd,
                                  unsigned long flags)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd);
-        struct soc_camera_link *icl = mt9v022->client->dev.platform_data;
+        struct soc_camera_link *icl = client->dev.platform_data;
         unsigned int width_flag = flags & SOCAM_DATAWIDTH_MASK;
         int ret;
         u16 pixclk = 0;
@@ -243,14 +244,14 @@ static int mt9v022_set_bus_param(struct soc_camera_device *icd,
         if (!(flags & SOCAM_VSYNC_ACTIVE_HIGH))
                 pixclk |= 0x2;
 
-        ret = reg_write(icd, MT9V022_PIXCLK_FV_LV, pixclk);
+        ret = reg_write(client, MT9V022_PIXCLK_FV_LV, pixclk);
         if (ret < 0)
                 return ret;
 
         if (!(flags & SOCAM_MASTER))
                 mt9v022->chip_control &= ~0x8;
 
-        ret = reg_write(icd, MT9V022_CHIP_CONTROL, mt9v022->chip_control);
+        ret = reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control);
         if (ret < 0)
                 return ret;
 
@@ -282,35 +283,36 @@ static unsigned long mt9v022_query_bus_param(struct soc_camera_device *icd)
 static int mt9v022_set_crop(struct soc_camera_device *icd,
                             struct v4l2_rect *rect)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         int ret;
 
         /* Like in example app. Contradicts the datasheet though */
-        ret = reg_read(icd, MT9V022_AEC_AGC_ENABLE);
+        ret = reg_read(client, MT9V022_AEC_AGC_ENABLE);
         if (ret >= 0) {
                 if (ret & 1) /* Autoexposure */
-                        ret = reg_write(icd, MT9V022_MAX_TOTAL_SHUTTER_WIDTH,
+                        ret = reg_write(client, MT9V022_MAX_TOTAL_SHUTTER_WIDTH,
                                         rect->height + icd->y_skip_top + 43);
                 else
-                        ret = reg_write(icd, MT9V022_TOTAL_SHUTTER_WIDTH,
+                        ret = reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH,
                                         rect->height + icd->y_skip_top + 43);
         }
         /* Setup frame format: defaults apart from width and height */
         if (!ret)
-                ret = reg_write(icd, MT9V022_COLUMN_START, rect->left);
+                ret = reg_write(client, MT9V022_COLUMN_START, rect->left);
         if (!ret)
-                ret = reg_write(icd, MT9V022_ROW_START, rect->top);
+                ret = reg_write(client, MT9V022_ROW_START, rect->top);
         if (!ret)
                 /* Default 94, Phytec driver says:
                  * "width + horizontal blank >= 660" */
-                ret = reg_write(icd, MT9V022_HORIZONTAL_BLANKING,
+                ret = reg_write(client, MT9V022_HORIZONTAL_BLANKING,
                                 rect->width > 660 - 43 ? 43 :
                                 660 - rect->width);
         if (!ret)
-                ret = reg_write(icd, MT9V022_VERTICAL_BLANKING, 45);
+                ret = reg_write(client, MT9V022_VERTICAL_BLANKING, 45);
         if (!ret)
-                ret = reg_write(icd, MT9V022_WINDOW_WIDTH, rect->width);
+                ret = reg_write(client, MT9V022_WINDOW_WIDTH, rect->width);
         if (!ret)
-                ret = reg_write(icd, MT9V022_WINDOW_HEIGHT,
+                ret = reg_write(client, MT9V022_WINDOW_HEIGHT,
                                 rect->height + icd->y_skip_top);
 
         if (ret < 0)
@@ -396,16 +398,16 @@ static int mt9v022_get_chip_id(struct soc_camera_device *icd,
 static int mt9v022_get_register(struct soc_camera_device *icd,
                                 struct v4l2_dbg_register *reg)
 {
-        struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd);
+        struct i2c_client *client = to_i2c_client(icd->control);
 
         if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
                 return -EINVAL;
 
-        if (reg->match.addr != mt9v022->client->addr)
+        if (reg->match.addr != client->addr)
                 return -ENODEV;
 
         reg->size = 2;
-        reg->val = reg_read(icd, reg->reg);
+        reg->val = reg_read(client, reg->reg);
 
         if (reg->val > 0xffff)
                 return -EIO;
@@ -416,15 +418,15 @@ static int mt9v022_get_register(struct soc_camera_device *icd,
 static int mt9v022_set_register(struct soc_camera_device *icd,
                                 struct v4l2_dbg_register *reg)
 {
-        struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd);
+        struct i2c_client *client = to_i2c_client(icd->control);
 
         if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
                 return -EINVAL;
 
-        if (reg->match.addr != mt9v022->client->addr)
+        if (reg->match.addr != client->addr)
                 return -ENODEV;
 
-        if (reg_write(icd, reg->reg, reg->val) < 0)
+        if (reg_write(client, reg->reg, reg->val) < 0)
                 return -EIO;
 
         return 0;
@@ -517,29 +519,30 @@ static struct soc_camera_ops mt9v022_ops = {
 static int mt9v022_get_control(struct soc_camera_device *icd,
                                struct v4l2_control *ctrl)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         int data;
 
         switch (ctrl->id) {
         case V4L2_CID_VFLIP:
-                data = reg_read(icd, MT9V022_READ_MODE);
+                data = reg_read(client, MT9V022_READ_MODE);
                 if (data < 0)
                         return -EIO;
                 ctrl->value = !!(data & 0x10);
                 break;
         case V4L2_CID_HFLIP:
-                data = reg_read(icd, MT9V022_READ_MODE);
+                data = reg_read(client, MT9V022_READ_MODE);
                 if (data < 0)
                         return -EIO;
                 ctrl->value = !!(data & 0x20);
                 break;
         case V4L2_CID_EXPOSURE_AUTO:
-                data = reg_read(icd, MT9V022_AEC_AGC_ENABLE);
+                data = reg_read(client, MT9V022_AEC_AGC_ENABLE);
                 if (data < 0)
                         return -EIO;
                 ctrl->value = !!(data & 0x1);
                 break;
         case V4L2_CID_AUTOGAIN:
-                data = reg_read(icd, MT9V022_AEC_AGC_ENABLE);
+                data = reg_read(client, MT9V022_AEC_AGC_ENABLE);
                 if (data < 0)
                         return -EIO;
                 ctrl->value = !!(data & 0x2);
@@ -552,6 +555,7 @@ static int mt9v022_set_control(struct soc_camera_device *icd,
                                struct v4l2_control *ctrl)
 {
         int data;
+        struct i2c_client *client = to_i2c_client(icd->control);
         const struct v4l2_queryctrl *qctrl;
 
         qctrl = soc_camera_find_qctrl(&mt9v022_ops, ctrl->id);
@@ -562,17 +566,17 @@ static int mt9v022_set_control(struct soc_camera_device *icd,
         switch (ctrl->id) {
         case V4L2_CID_VFLIP:
                 if (ctrl->value)
-                        data = reg_set(icd, MT9V022_READ_MODE, 0x10);
+                        data = reg_set(client, MT9V022_READ_MODE, 0x10);
                 else
-                        data = reg_clear(icd, MT9V022_READ_MODE, 0x10);
+                        data = reg_clear(client, MT9V022_READ_MODE, 0x10);
                 if (data < 0)
                         return -EIO;
                 break;
         case V4L2_CID_HFLIP:
                 if (ctrl->value)
-                        data = reg_set(icd, MT9V022_READ_MODE, 0x20);
+                        data = reg_set(client, MT9V022_READ_MODE, 0x20);
                 else
-                        data = reg_clear(icd, MT9V022_READ_MODE, 0x20);
+                        data = reg_clear(client, MT9V022_READ_MODE, 0x20);
                 if (data < 0)
                         return -EIO;
                 break;
@@ -593,12 +597,12 @@ static int mt9v022_set_control(struct soc_camera_device *icd,
                         /* The user wants to set gain manually, hope, she
                          * knows, what she's doing... Switch AGC off. */
 
-                        if (reg_clear(icd, MT9V022_AEC_AGC_ENABLE, 0x2) < 0)
+                        if (reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0)
                                 return -EIO;
 
                         dev_info(&icd->dev, "Setting gain from %d to %lu\n",
-                                 reg_read(icd, MT9V022_ANALOG_GAIN), gain);
-                        if (reg_write(icd, MT9V022_ANALOG_GAIN, gain) < 0)
+                                 reg_read(client, MT9V022_ANALOG_GAIN), gain);
+                        if (reg_write(client, MT9V022_ANALOG_GAIN, gain) < 0)
                                 return -EIO;
                         icd->gain = ctrl->value;
                 }
@@ -614,13 +618,13 @@ static int mt9v022_set_control(struct soc_camera_device *icd,
                         /* The user wants to set shutter width manually, hope,
                          * she knows, what she's doing... Switch AEC off. */
 
-                        if (reg_clear(icd, MT9V022_AEC_AGC_ENABLE, 0x1) < 0)
+                        if (reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x1) < 0)
                                 return -EIO;
 
                         dev_dbg(&icd->dev, "Shutter width from %d to %lu\n",
-                                reg_read(icd, MT9V022_TOTAL_SHUTTER_WIDTH),
+                                reg_read(client, MT9V022_TOTAL_SHUTTER_WIDTH),
                                 shutter);
-                        if (reg_write(icd, MT9V022_TOTAL_SHUTTER_WIDTH,
+                        if (reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH,
                                       shutter) < 0)
                                 return -EIO;
                         icd->exposure = ctrl->value;
@@ -628,17 +632,17 @@ static int mt9v022_set_control(struct soc_camera_device *icd,
                 break;
         case V4L2_CID_AUTOGAIN:
                 if (ctrl->value)
-                        data = reg_set(icd, MT9V022_AEC_AGC_ENABLE, 0x2);
+                        data = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x2);
                 else
-                        data = reg_clear(icd, MT9V022_AEC_AGC_ENABLE, 0x2);
+                        data = reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x2);
                 if (data < 0)
                         return -EIO;
                 break;
         case V4L2_CID_EXPOSURE_AUTO:
                 if (ctrl->value)
-                        data = reg_set(icd, MT9V022_AEC_AGC_ENABLE, 0x1);
+                        data = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x1);
                 else
-                        data = reg_clear(icd, MT9V022_AEC_AGC_ENABLE, 0x1);
+                        data = reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x1);
                 if (data < 0)
                         return -EIO;
                 break;
@@ -650,8 +654,9 @@ static int mt9v022_set_control(struct soc_camera_device *icd,
  * this wasn't our capture interface, so, we wait for the right one */
 static int mt9v022_video_probe(struct soc_camera_device *icd)
 {
+        struct i2c_client *client = to_i2c_client(icd->control);
         struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd);
-        struct soc_camera_link *icl = mt9v022->client->dev.platform_data;
+        struct soc_camera_link *icl = client->dev.platform_data;
         s32 data;
         int ret;
         unsigned long flags;
@@ -661,7 +666,7 @@ static int mt9v022_video_probe(struct soc_camera_device *icd)
                 return -ENODEV;
 
         /* Read out the chip version register */
-        data = reg_read(icd, MT9V022_CHIP_VERSION);
+        data = reg_read(client, MT9V022_CHIP_VERSION);
 
         /* must be 0x1311 or 0x1313 */
         if (data != 0x1311 && data != 0x1313) {
@@ -672,12 +677,12 @@ static int mt9v022_video_probe(struct soc_camera_device *icd)
         }
 
         /* Soft reset */
-        ret = reg_write(icd, MT9V022_RESET, 1);
+        ret = reg_write(client, MT9V022_RESET, 1);
         if (ret < 0)
                 goto ei2c;
         /* 15 clock cycles */
         udelay(200);
-        if (reg_read(icd, MT9V022_RESET)) {
+        if (reg_read(client, MT9V022_RESET)) {
                 dev_err(&icd->dev, "Resetting MT9V022 failed!\n");
                 goto ei2c;
         }
@@ -685,11 +690,11 @@ static int mt9v022_video_probe(struct soc_camera_device *icd)
         /* Set monochrome or colour sensor type */
         if (sensor_type && (!strcmp("colour", sensor_type) ||
                             !strcmp("color", sensor_type))) {
-                ret = reg_write(icd, MT9V022_PIXEL_OPERATION_MODE, 4 | 0x11);
+                ret = reg_write(client, MT9V022_PIXEL_OPERATION_MODE, 4 | 0x11);
                 mt9v022->model = V4L2_IDENT_MT9V022IX7ATC;
                 icd->formats = mt9v022_colour_formats;
         } else {
-                ret = reg_write(icd, MT9V022_PIXEL_OPERATION_MODE, 0x11);
+                ret = reg_write(client, MT9V022_PIXEL_OPERATION_MODE, 0x11);
                 mt9v022->model = V4L2_IDENT_MT9V022IX7ATM;
                 icd->formats = mt9v022_monochrome_formats;
         }
@@ -735,10 +740,13 @@ ei2c:
 static void mt9v022_video_remove(struct soc_camera_device *icd)
 {
         struct mt9v022 *mt9v022 = container_of(icd, struct mt9v022, icd);
+        struct soc_camera_link *icl = mt9v022->client->dev.platform_data;
 
         dev_dbg(&icd->dev, "Video %x removed: %p, %p\n", mt9v022->client->addr,
                 icd->dev.parent, icd->vdev);
         soc_camera_video_stop(icd);
+        if (icl->free_bus)
+                icl->free_bus(icl);
 }
 
 static int mt9v022_probe(struct i2c_client *client,
diff --git a/drivers/media/video/mx1_camera.c b/drivers/media/video/mx1_camera.c
index 86fab56c5a20..2d075205bdfe 100644
--- a/drivers/media/video/mx1_camera.c
+++ b/drivers/media/video/mx1_camera.c
@@ -102,10 +102,10 @@ struct mx1_buffer {
  * Interface. If anyone ever builds hardware to enable more than
  * one camera, they will have to modify this driver too */
 struct mx1_camera_dev {
+        struct soc_camera_host          soc_host;
         struct soc_camera_device        *icd;
         struct mx1_camera_pdata         *pdata;
         struct mx1_buffer               *active;
-        struct device                   *dev;
         struct resource                 *res;
         struct clk                      *clk;
         struct list_head                capture;
@@ -219,7 +219,7 @@ static int mx1_camera_setup_dma(struct mx1_camera_dev *pcdev)
         int ret;
 
         if (unlikely(!pcdev->active)) {
-                dev_err(pcdev->dev, "DMA End IRQ with no active buffer\n");
+                dev_err(pcdev->soc_host.dev, "DMA End IRQ with no active buffer\n");
                 return -EFAULT;
         }
 
@@ -229,7 +229,7 @@ static int mx1_camera_setup_dma(struct mx1_camera_dev *pcdev)
                 vbuf->size, pcdev->res->start +
                 CSIRXR, DMA_MODE_READ);
         if (unlikely(ret))
-                dev_err(pcdev->dev, "Failed to setup DMA sg list\n");
+                dev_err(pcdev->soc_host.dev, "Failed to setup DMA sg list\n");
 
         return ret;
 }
@@ -338,14 +338,14 @@ static void mx1_camera_dma_irq(int channel, void *data)
         imx_dma_disable(channel);
 
         if (unlikely(!pcdev->active)) {
-                dev_err(pcdev->dev, "DMA End IRQ with no active buffer\n");
+                dev_err(pcdev->soc_host.dev, "DMA End IRQ with no active buffer\n");
                 goto out;
         }
 
         vb = &pcdev->active->vb;
         buf = container_of(vb, struct mx1_buffer, vb);
         WARN_ON(buf->inwork || list_empty(&vb->queue));
-        dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+        dev_dbg(pcdev->soc_host.dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
                 vb, vb->baddr, vb->bsize);
 
         mx1_camera_wakeup(pcdev, vb, buf);
@@ -366,7 +366,7 @@ static void mx1_camera_init_videobuf(struct videobuf_queue *q,
         struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
         struct mx1_camera_dev *pcdev = ici->priv;
 
-        videobuf_queue_dma_contig_init(q, &mx1_videobuf_ops, pcdev->dev,
+        videobuf_queue_dma_contig_init(q, &mx1_videobuf_ops, ici->dev,
                                         &pcdev->lock,
                                         V4L2_BUF_TYPE_VIDEO_CAPTURE,
                                         V4L2_FIELD_NONE,
@@ -385,7 +385,7 @@ static int mclk_get_divisor(struct mx1_camera_dev *pcdev)
          * they get a nice Oops */
         div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
 
-        dev_dbg(pcdev->dev, "System clock %lukHz, target freq %dkHz, "
+        dev_dbg(pcdev->soc_host.dev, "System clock %lukHz, target freq %dkHz, "
                 "divisor %lu\n", lcdclk / 1000, mclk / 1000, div);
 
         return div;
@@ -395,7 +395,7 @@ static void mx1_camera_activate(struct mx1_camera_dev *pcdev)
 {
         unsigned int csicr1 = CSICR1_EN;
 
-        dev_dbg(pcdev->dev, "Activate device\n");
+        dev_dbg(pcdev->soc_host.dev, "Activate device\n");
 
         clk_enable(pcdev->clk);
 
@@ -411,7 +411,7 @@ static void mx1_camera_activate(struct mx1_camera_dev *pcdev)
 
 static void mx1_camera_deactivate(struct mx1_camera_dev *pcdev)
 {
-        dev_dbg(pcdev->dev, "Deactivate device\n");
+        dev_dbg(pcdev->soc_host.dev, "Deactivate device\n");
 
         /* Disable all CSI interface */
         __raw_writel(0x00, pcdev->base + CSICR1);
@@ -550,7 +550,7 @@ static int mx1_camera_set_fmt(struct soc_camera_device *icd,
 
         xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
         if (!xlate) {
-                dev_warn(&ici->dev, "Format %x not found\n", pix->pixelformat);
+                dev_warn(ici->dev, "Format %x not found\n", pix->pixelformat);
                 return -EINVAL;
         }
 
@@ -633,12 +633,6 @@ static struct soc_camera_host_ops mx1_soc_camera_host_ops = {
         .querycap       = mx1_camera_querycap,
 };
 
-/* Should be allocated dynamically too, but we have only one. */
-static struct soc_camera_host mx1_soc_camera_host = {
-        .drv_name       = DRIVER_NAME,
-        .ops            = &mx1_soc_camera_host_ops,
-};
-
 static struct fiq_handler fh = {
         .name           = "csi_sof"
 };
@@ -673,7 +667,6 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
                 goto exit_put_clk;
         }
 
-        dev_set_drvdata(&pdev->dev, pcdev);
         pcdev->res = res;
         pcdev->clk = clk;
 
@@ -707,16 +700,15 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
         }
         pcdev->irq = irq;
         pcdev->base = base;
-        pcdev->dev = &pdev->dev;
 
         /* request dma */
         pcdev->dma_chan = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_HIGH);
         if (pcdev->dma_chan < 0) {
-                dev_err(pcdev->dev, "Can't request DMA for MX1 CSI\n");
+                dev_err(&pdev->dev, "Can't request DMA for MX1 CSI\n");
                 err = -EBUSY;
                 goto exit_iounmap;
         }
-        dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chan);
+        dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chan);
 
         imx_dma_setup_handlers(pcdev->dma_chan, mx1_camera_dma_irq, NULL,
                                pcdev);
@@ -729,7 +721,7 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
         /* request irq */
         err = claim_fiq(&fh);
         if (err) {
-                dev_err(pcdev->dev, "Camera interrupt register failed \n");
+                dev_err(&pdev->dev, "Camera interrupt register failed \n");
                 goto exit_free_dma;
         }
 
@@ -746,10 +738,12 @@ static int __init mx1_camera_probe(struct platform_device *pdev)
         mxc_set_irq_fiq(irq, 1);
         enable_fiq(irq);
 
-        mx1_soc_camera_host.priv        = pcdev;
-        mx1_soc_camera_host.dev.parent  = &pdev->dev;
-        mx1_soc_camera_host.nr          = pdev->id;
-        err = soc_camera_host_register(&mx1_soc_camera_host);
+        pcdev->soc_host.drv_name        = DRIVER_NAME;
+        pcdev->soc_host.ops             = &mx1_soc_camera_host_ops;
+        pcdev->soc_host.priv            = pcdev;
+        pcdev->soc_host.dev             = &pdev->dev;
+        pcdev->soc_host.nr              = pdev->id;
+        err = soc_camera_host_register(&pcdev->soc_host);
         if (err)
                 goto exit_free_irq;
 
@@ -777,7 +771,9 @@ exit:
 
 static int __exit mx1_camera_remove(struct platform_device *pdev)
 {
-        struct mx1_camera_dev *pcdev = platform_get_drvdata(pdev);
+        struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
+        struct mx1_camera_dev *pcdev = container_of(soc_host,
+                                        struct mx1_camera_dev, soc_host);
         struct resource *res;
 
         imx_dma_free(pcdev->dma_chan);
@@ -787,7 +783,7 @@ static int __exit mx1_camera_remove(struct platform_device *pdev)
 
         clk_put(pcdev->clk);
 
-        soc_camera_host_unregister(&mx1_soc_camera_host);
+        soc_camera_host_unregister(soc_host);
 
         iounmap(pcdev->base);
 
diff --git a/drivers/media/video/mx3_camera.c b/drivers/media/video/mx3_camera.c
index 2d0781118eb0..e605c076ed89 100644
--- a/drivers/media/video/mx3_camera.c
+++ b/drivers/media/video/mx3_camera.c
@@ -87,7 +87,6 @@ struct mx3_camera_buffer {
  * @soc_host:           embedded soc_host object
  */
 struct mx3_camera_dev {
-        struct device           *dev;
         /*
          * i.MX3x is only supposed to handle one camera on its Camera Sensor
          * Interface. If anyone ever builds hardware to enable more than one
@@ -431,7 +430,7 @@ static void mx3_camera_init_videobuf(struct videobuf_queue *q,
         struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
         struct mx3_camera_dev *mx3_cam = ici->priv;
 
-        videobuf_queue_dma_contig_init(q, &mx3_videobuf_ops, mx3_cam->dev,
+        videobuf_queue_dma_contig_init(q, &mx3_videobuf_ops, ici->dev,
                                        &mx3_cam->lock,
                                        V4L2_BUF_TYPE_VIDEO_CAPTURE,
                                        V4L2_FIELD_NONE,
@@ -599,7 +598,8 @@ static int test_platform_param(struct mx3_camera_dev *mx3_cam,
                 *flags |= SOCAM_DATAWIDTH_4;
                 break;
         default:
-                dev_info(mx3_cam->dev, "Unsupported bus width %d\n", buswidth);
+                dev_info(mx3_cam->soc_host.dev, "Unsupported bus width %d\n",
+                         buswidth);
                 return -EINVAL;
         }
 
@@ -614,7 +614,7 @@ static int mx3_camera_try_bus_param(struct soc_camera_device *icd,
         unsigned long bus_flags, camera_flags;
         int ret = test_platform_param(mx3_cam, depth, &bus_flags);
 
-        dev_dbg(&ici->dev, "requested bus width %d bit: %d\n", depth, ret);
+        dev_dbg(ici->dev, "requested bus width %d bit: %d\n", depth, ret);
 
         if (ret < 0)
                 return ret;
@@ -637,7 +637,7 @@ static bool chan_filter(struct dma_chan *chan, void *arg)
         if (!rq)
                 return false;
 
-        pdata = rq->mx3_cam->dev->platform_data;
+        pdata = rq->mx3_cam->soc_host.dev->platform_data;
 
         return rq->id == chan->chan_id &&
                 pdata->dma_dev == chan->device->dev;
@@ -697,7 +697,7 @@ static int mx3_camera_get_formats(struct soc_camera_device *icd, int idx,
                         xlate->cam_fmt = icd->formats + idx;
                         xlate->buswidth = buswidth;
                         xlate++;
-                        dev_dbg(&ici->dev, "Providing format %s using %s\n",
+                        dev_dbg(ici->dev, "Providing format %s using %s\n",
                                 mx3_camera_formats[0].name,
                                 icd->formats[idx].name);
                 }
@@ -709,7 +709,7 @@ static int mx3_camera_get_formats(struct soc_camera_device *icd, int idx,
                         xlate->cam_fmt = icd->formats + idx;
                         xlate->buswidth = buswidth;
                         xlate++;
-                        dev_dbg(&ici->dev, "Providing format %s using %s\n",
+                        dev_dbg(ici->dev, "Providing format %s using %s\n",
                                 mx3_camera_formats[0].name,
                                 icd->formats[idx].name);
                 }
@@ -722,7 +722,7 @@ passthrough:
                         xlate->cam_fmt = icd->formats + idx;
                         xlate->buswidth = buswidth;
                         xlate++;
-                        dev_dbg(&ici->dev,
+                        dev_dbg(ici->dev,
                                 "Providing format %s in pass-through mode\n",
                                 icd->formats[idx].name);
                 }
@@ -829,7 +829,7 @@ static int mx3_camera_set_fmt(struct soc_camera_device *icd,
 
         xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
         if (!xlate) {
-                dev_warn(&ici->dev, "Format %x not found\n", pix->pixelformat);
+                dev_warn(ici->dev, "Format %x not found\n", pix->pixelformat);
                 return -EINVAL;
         }
 
@@ -866,7 +866,7 @@ static int mx3_camera_try_fmt(struct soc_camera_device *icd,
 
         xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
         if (pixfmt && !xlate) {
-                dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
+                dev_warn(ici->dev, "Format %x not found\n", pixfmt);
                 return -EINVAL;
         }
 
@@ -933,11 +933,11 @@ static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
 
         xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
         if (!xlate) {
-                dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
+                dev_warn(ici->dev, "Format %x not found\n", pixfmt);
                 return -EINVAL;
         }
 
-        dev_dbg(&ici->dev, "requested bus width %d bit: %d\n",
+        dev_dbg(ici->dev, "requested bus width %d bit: %d\n",
                 icd->buswidth, ret);
 
         if (ret < 0)
@@ -947,7 +947,7 @@ static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
 
         common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
         if (!common_flags) {
-                dev_dbg(&ici->dev, "no common flags: camera %lx, host %lx\n",
+                dev_dbg(ici->dev, "no common flags: camera %lx, host %lx\n",
                         camera_flags, bus_flags);
                 return -EINVAL;
         }
@@ -1054,7 +1054,7 @@ static int mx3_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
 
         csi_reg_write(mx3_cam, sens_conf | dw, CSI_SENS_CONF);
 
-        dev_dbg(&ici->dev, "Set SENS_CONF to %x\n", sens_conf | dw);
+        dev_dbg(ici->dev, "Set SENS_CONF to %x\n", sens_conf | dw);
 
         return 0;
 }
@@ -1074,7 +1074,7 @@ static struct soc_camera_host_ops mx3_soc_camera_host_ops = {
         .set_bus_param  = mx3_camera_set_bus_param,
 };
 
-static int mx3_camera_probe(struct platform_device *pdev)
+static int __devinit mx3_camera_probe(struct platform_device *pdev)
 {
         struct mx3_camera_dev *mx3_cam;
         struct resource *res;
@@ -1102,8 +1102,6 @@ static int mx3_camera_probe(struct platform_device *pdev)
                 goto eclkget;
         }
 
-        dev_set_drvdata(&pdev->dev, mx3_cam);
-
         mx3_cam->pdata = pdev->dev.platform_data;
         mx3_cam->platform_flags = mx3_cam->pdata->flags;
         if (!(mx3_cam->platform_flags & (MX3_CAMERA_DATAWIDTH_4 |
@@ -1135,14 +1133,14 @@ static int mx3_camera_probe(struct platform_device *pdev)
         }
 
         mx3_cam->base   = base;
-        mx3_cam->dev    = &pdev->dev;
 
         soc_host                = &mx3_cam->soc_host;
         soc_host->drv_name      = MX3_CAM_DRV_NAME;
         soc_host->ops           = &mx3_soc_camera_host_ops;
         soc_host->priv          = mx3_cam;
-        soc_host->dev.parent    = &pdev->dev;
+        soc_host->dev           = &pdev->dev;
         soc_host->nr            = pdev->id;
+
         err = soc_camera_host_register(soc_host);
         if (err)
                 goto ecamhostreg;
@@ -1165,11 +1163,13 @@ egetres:
 
 static int __devexit mx3_camera_remove(struct platform_device *pdev)
 {
-        struct mx3_camera_dev *mx3_cam = platform_get_drvdata(pdev);
+        struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
+        struct mx3_camera_dev *mx3_cam = container_of(soc_host,
+                                        struct mx3_camera_dev, soc_host);
 
         clk_put(mx3_cam->clk);
 
-        soc_camera_host_unregister(&mx3_cam->soc_host);
+        soc_camera_host_unregister(soc_host);
 
         iounmap(mx3_cam->base);
 
@@ -1194,11 +1194,11 @@ static struct platform_driver mx3_camera_driver = {
                 .name   = MX3_CAM_DRV_NAME,
         },
         .probe          = mx3_camera_probe,
-        .remove         = __exit_p(mx3_camera_remove),
+        .remove         = __devexit_p(mx3_camera_remove),
 };
 
 
-static int __devinit mx3_camera_init(void)
+static int __init mx3_camera_init(void)
 {
         return platform_driver_register(&mx3_camera_driver);
 }
diff --git a/drivers/media/video/mxb.c b/drivers/media/video/mxb.c
index 3be5a71bdac2..35890e8b2431 100644
--- a/drivers/media/video/mxb.c
+++ b/drivers/media/video/mxb.c
@@ -453,7 +453,7 @@ static int vidioc_s_ctrl(struct file *file, void *fh, struct v4l2_control *vc)
 static int vidioc_enum_input(struct file *file, void *fh, struct v4l2_input *i)
 {
         DEB_EE(("VIDIOC_ENUMINPUT %d.\n", i->index));
-        if (i->index < 0 || i->index >= MXB_INPUTS)
+        if (i->index >= MXB_INPUTS)
                 return -EINVAL;
         memcpy(i, &mxb_inputs[i->index], sizeof(struct v4l2_input));
         return 0;
@@ -616,7 +616,7 @@ static int vidioc_g_audio(struct file *file, void *fh, struct v4l2_audio *a)
         struct saa7146_dev *dev = ((struct saa7146_fh *)fh)->dev;
         struct mxb *mxb = (struct mxb *)dev->ext_priv;
 
-        if (a->index < 0 || a->index > MXB_INPUTS) {
+        if (a->index > MXB_INPUTS) {
                 DEB_D(("VIDIOC_G_AUDIO %d out of range.\n", a->index));
                 return -EINVAL;
         }
diff --git a/drivers/media/video/ov511.c b/drivers/media/video/ov511.c
index 9af5532db142..08cfd3e4ae8a 100644
--- a/drivers/media/video/ov511.c
+++ b/drivers/media/video/ov511.c
@@ -112,6 +112,8 @@ static int framedrop		= -1;
 static int fastset;
 static int force_palette;
 static int backlight;
+/* Bitmask marking allocated devices from 0 to OV511_MAX_UNIT_VIDEO */
+static unsigned long ov511_devused;
 static int unit_video[OV511_MAX_UNIT_VIDEO];
 static int remove_zeros;
 static int mirror;
@@ -5720,7 +5722,7 @@ ov51x_probe(struct usb_interface *intf, const struct usb_device_id *id)
         struct usb_device *dev = interface_to_usbdev(intf);
         struct usb_interface_descriptor *idesc;
         struct usb_ov511 *ov;
-        int i;
+        int i, rc, nr;
 
         PDEBUG(1, "probing for device...");
 
@@ -5845,33 +5847,41 @@ ov51x_probe(struct usb_interface *intf, const struct usb_device_id *id)
         ov->vdev->parent = &intf->dev;
         video_set_drvdata(ov->vdev, ov);
 
-        for (i = 0; i < OV511_MAX_UNIT_VIDEO; i++) {
-                /* Minor 0 cannot be specified; assume user wants autodetect */
-                if (unit_video[i] == 0)
-                        break;
+        mutex_lock(&ov->lock);
 
-                if (video_register_device(ov->vdev, VFL_TYPE_GRABBER,
-                        unit_video[i]) >= 0) {
-                        break;
-                }
-        }
+        /* Check to see next free device and mark as used */
+        nr = find_first_zero_bit(&ov511_devused, OV511_MAX_UNIT_VIDEO);
+
+        /* Registers device */
+        if (unit_video[nr] != 0)
+                rc = video_register_device(ov->vdev, VFL_TYPE_GRABBER,
+                                           unit_video[nr]);
+        else
+                rc = video_register_device(ov->vdev, VFL_TYPE_GRABBER, -1);
 
-        /* Use the next available one */
-        if ((ov->vdev->minor == -1) &&
-            video_register_device(ov->vdev, VFL_TYPE_GRABBER, -1) < 0) {
+        if (rc < 0) {
                 err("video_register_device failed");
+                mutex_unlock(&ov->lock);
                 goto error;
         }
 
+        /* Mark device as used */
+        ov511_devused |= 1 << nr;
+        ov->nr = nr;
+
         dev_info(&intf->dev, "Device at %s registered to minor %d\n",
                  ov->usb_path, ov->vdev->minor);
 
         usb_set_intfdata(intf, ov);
         if (ov_create_sysfs(ov->vdev)) {
                 err("ov_create_sysfs failed");
+                ov511_devused &= ~(1 << nr);
+                mutex_unlock(&ov->lock);
                 goto error;
         }
 
+        mutex_lock(&ov->lock);
+
         return 0;
 
 error:
@@ -5906,10 +5916,16 @@ ov51x_disconnect(struct usb_interface *intf)
 
         PDEBUG(3, "");
 
+        mutex_lock(&ov->lock);
         usb_set_intfdata (intf, NULL);
 
-        if (!ov)
+        if (!ov) {
+                mutex_unlock(&ov->lock);
                 return;
+        }
+
+        /* Free device number */
+        ov511_devused &= ~(1 << ov->nr);
 
         if (ov->vdev)
                 video_unregister_device(ov->vdev);
@@ -5927,6 +5943,7 @@ ov51x_disconnect(struct usb_interface *intf)
 
         ov->streaming = 0;
         ov51x_unlink_isoc(ov);
+        mutex_unlock(&ov->lock);
 
         ov->dev = NULL;
 
diff --git a/drivers/media/video/ov511.h b/drivers/media/video/ov511.h
index 70d99e52329d..c450c92468da 100644
--- a/drivers/media/video/ov511.h
+++ b/drivers/media/video/ov511.h
@@ -494,6 +494,9 @@ struct usb_ov511 {
         int has_decoder;        /* Device has a video decoder */
         int pal;                /* Device is designed for PAL resolution */
 
+        /* ov511 device number ID */
+        int nr;                 /* Stores a device number */
+
         /* I2C interface */
         struct mutex i2c_lock;    /* Protect I2C controller regs */
         unsigned char primary_i2c_slave;  /* I2C write id of sensor */
diff --git a/drivers/media/video/pvrusb2/pvrusb2-devattr.c b/drivers/media/video/pvrusb2/pvrusb2-devattr.c
index 1cb6a260e8b0..336a20eded0f 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-devattr.c
+++ b/drivers/media/video/pvrusb2/pvrusb2-devattr.c
@@ -71,6 +71,7 @@ static const struct pvr2_device_desc pvr2_device_29xxx = {
                 .flag_has_svideo = !0,
                 .signal_routing_scheme = PVR2_ROUTING_SCHEME_HAUPPAUGE,
                 .led_scheme = PVR2_LED_SCHEME_HAUPPAUGE,
+                .ir_scheme = PVR2_IR_SCHEME_29XXX,
 };
 
 
@@ -284,6 +285,11 @@ static struct tda10048_config hauppauge_tda10048_config = {
         .output_mode    = TDA10048_PARALLEL_OUTPUT,
         .fwbulkwritelen = TDA10048_BULKWRITE_50,
         .inversion      = TDA10048_INVERSION_ON,
+        .dtv6_if_freq_khz = TDA10048_IF_3300,
+        .dtv7_if_freq_khz = TDA10048_IF_3800,
+        .dtv8_if_freq_khz = TDA10048_IF_4300,
+        .clk_freq_khz   = TDA10048_CLK_16000,
+        .disable_gate_access = 1,
 };
 
 static struct tda829x_config tda829x_no_probe = {
diff --git a/drivers/media/video/pvrusb2/pvrusb2-devattr.h b/drivers/media/video/pvrusb2/pvrusb2-devattr.h
index 3e553389cbc3..ea04ecf8aa39 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-devattr.h
+++ b/drivers/media/video/pvrusb2/pvrusb2-devattr.h
@@ -69,6 +69,7 @@ struct pvr2_string_table {
 #define PVR2_ROUTING_SCHEME_HAUPPAUGE 0
 #define PVR2_ROUTING_SCHEME_GOTVIEW 1
 #define PVR2_ROUTING_SCHEME_ONAIR 2
+#define PVR2_ROUTING_SCHEME_AV400 3
 
 #define PVR2_DIGITAL_SCHEME_NONE 0
 #define PVR2_DIGITAL_SCHEME_HAUPPAUGE 1
@@ -78,8 +79,10 @@ struct pvr2_string_table {
 #define PVR2_LED_SCHEME_HAUPPAUGE 1
 
 #define PVR2_IR_SCHEME_NONE 0
-#define PVR2_IR_SCHEME_24XXX 1
-#define PVR2_IR_SCHEME_ZILOG 2
+#define PVR2_IR_SCHEME_24XXX 1 /* FX2-controlled IR */
+#define PVR2_IR_SCHEME_ZILOG 2 /* HVR-1950 style (must be taken out of reset) */
+#define PVR2_IR_SCHEME_24XXX_MCE 3 /* 24xxx MCE device */
+#define PVR2_IR_SCHEME_29XXX 4 /* Original 29xxx device */
 
 /* This describes a particular hardware type (except for the USB device ID
    which must live in a separate structure due to environmental
@@ -162,19 +165,9 @@ struct pvr2_device_desc {
            ensure that it is found. */
         unsigned int flag_has_wm8775:1;
 
-        /* Indicate any specialized IR scheme that might need to be
-           supported by this driver.  If not set, then it is assumed that
-           IR can work without help from the driver (which is frequently
-           the case).  This is otherwise set to one of
-           PVR2_IR_SCHEME_xxxx.  For "xxxx", the value "24XXX" indicates a
-           Hauppauge 24xxx class device which has an FPGA-hosted IR
-           receiver that can only be reached via FX2 command codes.  In
-           that case the pvrusb2 driver will emulate the behavior of the
-           older 29xxx device's IR receiver (a "virtual" I2C chip) in terms
-           of those command codes.  For the value "ZILOG", we're dealing
-           with an IR chip that must be taken out of reset via another FX2
-           command code (which is the case for HVR-1950 devices). */
-        unsigned int ir_scheme:2;
+        /* Indicate IR scheme of hardware.  If not set, then it is assumed
+           that IR can work without any help from the driver. */
+        unsigned int ir_scheme:3;
 
         /* These bits define which kinds of sources the device can handle.
            Note: Digital tuner presence is inferred by the
diff --git a/drivers/media/video/pvrusb2/pvrusb2-hdw-internal.h b/drivers/media/video/pvrusb2/pvrusb2-hdw-internal.h
index 5d75eb5211b1..5b152ff20bd0 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-hdw-internal.h
+++ b/drivers/media/video/pvrusb2/pvrusb2-hdw-internal.h
@@ -200,6 +200,9 @@ struct pvr2_hdw {
         int i2c_cx25840_hack_state;
         int i2c_linked;
 
+        /* IR related */
+        unsigned int ir_scheme_active; /* IR scheme as seen from the outside */
+
         /* Frequency table */
         unsigned int freqTable[FREQTABLE_SIZE];
         unsigned int freqProgSlot;
diff --git a/drivers/media/video/pvrusb2/pvrusb2-hdw.c b/drivers/media/video/pvrusb2/pvrusb2-hdw.c
index add3395d3248..0c745b142fb7 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-hdw.c
+++ b/drivers/media/video/pvrusb2/pvrusb2-hdw.c
@@ -142,6 +142,15 @@ static const unsigned char *module_i2c_addresses[] = {
 };
 
 
+static const char *ir_scheme_names[] = {
+        [PVR2_IR_SCHEME_NONE] = "none",
+        [PVR2_IR_SCHEME_29XXX] = "29xxx",
+        [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
+        [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
+        [PVR2_IR_SCHEME_ZILOG] = "Zilog",
+};
+
+
 /* Define the list of additional controls we'll dynamically construct based
    on query of the cx2341x module. */
 struct pvr2_mpeg_ids {
@@ -2170,7 +2179,7 @@ static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
         }
 
         /* Take the IR chip out of reset, if appropriate */
-        if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
+        if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
                 pvr2_issue_simple_cmd(hdw,
                                       FX2CMD_HCW_ZILOG_RESET |
                                       (1 << 8) |
@@ -2451,6 +2460,7 @@ struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
                                 GFP_KERNEL);
         if (!hdw->controls) goto fail;
         hdw->hdw_desc = hdw_desc;
+        hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
         for (idx = 0; idx < hdw->control_cnt; idx++) {
                 cptr = hdw->controls + idx;
                 cptr->hdw = hdw;
@@ -4809,6 +4819,12 @@ static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
                         stats.buffers_processed,
                         stats.buffers_failed);
         }
+        case 6: {
+                unsigned int id = hdw->ir_scheme_active;
+                return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
+                                 (id >= ARRAY_SIZE(ir_scheme_names) ?
+                                  "?" : ir_scheme_names[id]));
+        }
         default: break;
         }
         return 0;
@@ -4825,65 +4841,35 @@ static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
         unsigned int tcnt = 0;
         unsigned int ccnt;
         struct i2c_client *client;
-        struct list_head *item;
-        void *cd;
         const char *p;
         unsigned int id;
 
-        ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers:");
+        ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
         tcnt += ccnt;
         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
                 id = sd->grp_id;
                 p = NULL;
                 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
                 if (p) {
-                        ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s", p);
+                        ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
                         tcnt += ccnt;
                 } else {
                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
-                                         " (unknown id=%u)", id);
+                                         "  (unknown id=%u):", id);
                         tcnt += ccnt;
                 }
-        }
-        ccnt = scnprintf(buf + tcnt, acnt - tcnt, "\n");
-        tcnt += ccnt;
-
-        ccnt = scnprintf(buf + tcnt, acnt - tcnt, "I2C clients:\n");
-        tcnt += ccnt;
-
-        mutex_lock(&hdw->i2c_adap.clist_lock);
-        list_for_each(item, &hdw->i2c_adap.clients) {
-                client = list_entry(item, struct i2c_client, list);
-                ccnt = scnprintf(buf + tcnt, acnt - tcnt,
-                                 "  %s: i2c=%02x", client->name, client->addr);
-                tcnt += ccnt;
-                cd = i2c_get_clientdata(client);
-                v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
-                        if (cd == sd) {
-                                id = sd->grp_id;
-                                p = NULL;
-                                if (id < ARRAY_SIZE(module_names)) {
-                                        p = module_names[id];
-                                }
-                                if (p) {
-                                        ccnt = scnprintf(buf + tcnt,
-                                                         acnt - tcnt,
-                                                         " subdev=%s", p);
-                                        tcnt += ccnt;
-                                } else {
-                                        ccnt = scnprintf(buf + tcnt,
-                                                         acnt - tcnt,
-                                                         " subdev= id %u)",
-                                                         id);
-                                        tcnt += ccnt;
-                                }
-                                break;
-                        }
+                client = v4l2_get_subdevdata(sd);
+                if (client) {
+                        ccnt = scnprintf(buf + tcnt, acnt - tcnt,
+                                         " %s @ %02x\n", client->name,
+                                         client->addr);
+                        tcnt += ccnt;
+                } else {
+                        ccnt = scnprintf(buf + tcnt, acnt - tcnt,
+                                         " no i2c client\n");
+                        tcnt += ccnt;
                 }
-                ccnt = scnprintf(buf + tcnt, acnt - tcnt, "\n");
-                tcnt += ccnt;
         }
-        mutex_unlock(&hdw->i2c_adap.clist_lock);
         return tcnt;
 }
 
diff --git a/drivers/media/video/pvrusb2/pvrusb2-i2c-core.c b/drivers/media/video/pvrusb2/pvrusb2-i2c-core.c
index 9af282f9e765..610bd848df24 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-i2c-core.c
+++ b/drivers/media/video/pvrusb2/pvrusb2-i2c-core.c
@@ -42,6 +42,18 @@ static int ir_mode[PVR_NUM] = { [0 ... PVR_NUM-1] = 1 };
 module_param_array(ir_mode, int, NULL, 0444);
 MODULE_PARM_DESC(ir_mode,"specify: 0=disable IR reception, 1=normal IR");
 
+static int pvr2_disable_ir_video;
+module_param_named(disable_autoload_ir_video, pvr2_disable_ir_video,
+                   int, S_IRUGO|S_IWUSR);
+MODULE_PARM_DESC(disable_autoload_ir_video,
+                 "1=do not try to autoload ir_video IR receiver");
+
+/* Mapping of IR schemes to known I2C addresses - if any */
+static const unsigned char ir_video_addresses[] = {
+        [PVR2_IR_SCHEME_29XXX] = 0x18,
+        [PVR2_IR_SCHEME_24XXX] = 0x18,
+};
+
 static int pvr2_i2c_write(struct pvr2_hdw *hdw, /* Context */
                           u8 i2c_addr,      /* I2C address we're talking to */
                           u8 *data,         /* Data to write */
@@ -559,6 +571,31 @@ static void do_i2c_scan(struct pvr2_hdw *hdw)
         printk(KERN_INFO "%s: i2c scan done.\n", hdw->name);
 }
 
+static void pvr2_i2c_register_ir(struct pvr2_hdw *hdw)
+{
+        struct i2c_board_info info;
+        unsigned char addr = 0;
+        if (pvr2_disable_ir_video) {
+                pvr2_trace(PVR2_TRACE_INFO,
+                           "Automatic binding of ir_video has been disabled.");
+                return;
+        }
+        if (hdw->ir_scheme_active < ARRAY_SIZE(ir_video_addresses)) {
+                addr = ir_video_addresses[hdw->ir_scheme_active];
+        }
+        if (!addr) {
+                /* The device either doesn't support I2C-based IR or we
+                   don't know (yet) how to operate IR on the device. */
+                return;
+        }
+        pvr2_trace(PVR2_TRACE_INFO,
+                   "Binding ir_video to i2c address 0x%02x.", addr);
+        memset(&info, 0, sizeof(struct i2c_board_info));
+        strlcpy(info.type, "ir_video", I2C_NAME_SIZE);
+        info.addr = addr;
+        i2c_new_device(&hdw->i2c_adap, &info);
+}
+
 void pvr2_i2c_core_init(struct pvr2_hdw *hdw)
 {
         unsigned int idx;
@@ -574,7 +611,9 @@ void pvr2_i2c_core_init(struct pvr2_hdw *hdw)
                 printk(KERN_INFO "%s: IR disabled\n",hdw->name);
                 hdw->i2c_func[0x18] = i2c_black_hole;
         } else if (ir_mode[hdw->unit_number] == 1) {
-                if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_24XXX) {
+                if (hdw->ir_scheme_active == PVR2_IR_SCHEME_24XXX) {
+                        /* Set up translation so that our IR looks like a
+                           29xxx device */
                         hdw->i2c_func[0x18] = i2c_24xxx_ir;
                 }
         }
@@ -597,15 +636,23 @@ void pvr2_i2c_core_init(struct pvr2_hdw *hdw)
         i2c_add_adapter(&hdw->i2c_adap);
         if (hdw->i2c_func[0x18] == i2c_24xxx_ir) {
                 /* Probe for a different type of IR receiver on this
-                   device.  If present, disable the emulated IR receiver. */
+                   device.  This is really the only way to differentiate
+                   older 24xxx devices from 24xxx variants that include an
+                   IR blaster.  If the IR blaster is present, the IR
+                   receiver is part of that chip and thus we must disable
+                   the emulated IR receiver. */
                 if (do_i2c_probe(hdw, 0x71)) {
                         pvr2_trace(PVR2_TRACE_INFO,
                                    "Device has newer IR hardware;"
                                    " disabling unneeded virtual IR device");
                         hdw->i2c_func[0x18] = NULL;
+                        /* Remember that this is a different device... */
+                        hdw->ir_scheme_active = PVR2_IR_SCHEME_24XXX_MCE;
                 }
         }
         if (i2c_scan) do_i2c_scan(hdw);
+
+        pvr2_i2c_register_ir(hdw);
 }
 
 void pvr2_i2c_core_done(struct pvr2_hdw *hdw)
diff --git a/drivers/media/video/pvrusb2/pvrusb2-sysfs.c b/drivers/media/video/pvrusb2/pvrusb2-sysfs.c
index 299c1cbc3832..6c23456e0bda 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-sysfs.c
+++ b/drivers/media/video/pvrusb2/pvrusb2-sysfs.c
@@ -539,7 +539,7 @@ static void class_dev_destroy(struct pvr2_sysfs *sfp)
                                          &sfp->attr_unit_number);
         }
         pvr2_sysfs_trace("Destroying class_dev id=%p",sfp->class_dev);
-        sfp->class_dev->driver_data = NULL;
+        dev_set_drvdata(sfp->class_dev, NULL);
         device_unregister(sfp->class_dev);
         sfp->class_dev = NULL;
 }
@@ -549,7 +549,7 @@ static ssize_t v4l_minor_number_show(struct device *class_dev,
                                      struct device_attribute *attr, char *buf)
 {
         struct pvr2_sysfs *sfp;
-        sfp = (struct pvr2_sysfs *)class_dev->driver_data;
+        sfp = dev_get_drvdata(class_dev);
         if (!sfp) return -EINVAL;
         return scnprintf(buf,PAGE_SIZE,"%d\n",
                          pvr2_hdw_v4l_get_minor_number(sfp->channel.hdw,
@@ -561,7 +561,7 @@ static ssize_t bus_info_show(struct device *class_dev,
                              struct device_attribute *attr, char *buf)
 {
         struct pvr2_sysfs *sfp;
-        sfp = (struct pvr2_sysfs *)class_dev->driver_data;
+        sfp = dev_get_drvdata(class_dev);
         if (!sfp) return -EINVAL;
         return scnprintf(buf,PAGE_SIZE,"%s\n",
                          pvr2_hdw_get_bus_info(sfp->channel.hdw));
@@ -572,7 +572,7 @@ static ssize_t hdw_name_show(struct device *class_dev,
                              struct device_attribute *attr, char *buf)
 {
         struct pvr2_sysfs *sfp;
-        sfp = (struct pvr2_sysfs *)class_dev->driver_data;
+        sfp = dev_get_drvdata(class_dev);
         if (!sfp) return -EINVAL;
         return scnprintf(buf,PAGE_SIZE,"%s\n",
                          pvr2_hdw_get_type(sfp->channel.hdw));
@@ -583,7 +583,7 @@ static ssize_t hdw_desc_show(struct device *class_dev,
                              struct device_attribute *attr, char *buf)
 {
         struct pvr2_sysfs *sfp;
-        sfp = (struct pvr2_sysfs *)class_dev->driver_data;
+        sfp = dev_get_drvdata(class_dev);
         if (!sfp) return -EINVAL;
         return scnprintf(buf,PAGE_SIZE,"%s\n",
                          pvr2_hdw_get_desc(sfp->channel.hdw));
@@ -595,7 +595,7 @@ static ssize_t v4l_radio_minor_number_show(struct device *class_dev,
                                            char *buf)
 {
         struct pvr2_sysfs *sfp;
-        sfp = (struct pvr2_sysfs *)class_dev->driver_data;
+        sfp = dev_get_drvdata(class_dev);
         if (!sfp) return -EINVAL;
         return scnprintf(buf,PAGE_SIZE,"%d\n",
                          pvr2_hdw_v4l_get_minor_number(sfp->channel.hdw,
@@ -607,7 +607,7 @@ static ssize_t unit_number_show(struct device *class_dev,
                                 struct device_attribute *attr, char *buf)
 {
         struct pvr2_sysfs *sfp;
-        sfp = (struct pvr2_sysfs *)class_dev->driver_data;
+        sfp = dev_get_drvdata(class_dev);
         if (!sfp) return -EINVAL;
         return scnprintf(buf,PAGE_SIZE,"%d\n",
                          pvr2_hdw_get_unit_number(sfp->channel.hdw));
@@ -635,7 +635,7 @@ static void class_dev_create(struct pvr2_sysfs *sfp,
         class_dev->parent = &usb_dev->dev;
 
         sfp->class_dev = class_dev;
-        class_dev->driver_data = sfp;
+        dev_set_drvdata(class_dev, sfp);
         ret = device_register(class_dev);
         if (ret) {
                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
@@ -792,7 +792,7 @@ static ssize_t debuginfo_show(struct device *class_dev,
                               struct device_attribute *attr, char *buf)
 {
         struct pvr2_sysfs *sfp;
-        sfp = (struct pvr2_sysfs *)class_dev->driver_data;
+        sfp = dev_get_drvdata(class_dev);
         if (!sfp) return -EINVAL;
         pvr2_hdw_trigger_module_log(sfp->channel.hdw);
         return pvr2_debugifc_print_info(sfp->channel.hdw,buf,PAGE_SIZE);
@@ -803,7 +803,7 @@ static ssize_t debugcmd_show(struct device *class_dev,
                              struct device_attribute *attr, char *buf)
 {
         struct pvr2_sysfs *sfp;
-        sfp = (struct pvr2_sysfs *)class_dev->driver_data;
+        sfp = dev_get_drvdata(class_dev);
         if (!sfp) return -EINVAL;
         return pvr2_debugifc_print_status(sfp->channel.hdw,buf,PAGE_SIZE);
 }
@@ -816,7 +816,7 @@ static ssize_t debugcmd_store(struct device *class_dev,
         struct pvr2_sysfs *sfp;
         int ret;
 
-        sfp = (struct pvr2_sysfs *)class_dev->driver_data;
+        sfp = dev_get_drvdata(class_dev);
         if (!sfp) return -EINVAL;
 
         ret = pvr2_debugifc_docmd(sfp->channel.hdw,buf,count);
diff --git a/drivers/media/video/pvrusb2/pvrusb2-v4l2.c b/drivers/media/video/pvrusb2/pvrusb2-v4l2.c
index 9e0f2b07b93b..2d8825e5b1be 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-v4l2.c
+++ b/drivers/media/video/pvrusb2/pvrusb2-v4l2.c
@@ -90,7 +90,7 @@ static struct v4l2_capability pvr_capability ={
         .driver         = "pvrusb2",
         .card           = "Hauppauge WinTV pvr-usb2",
         .bus_info       = "usb",
-        .version        = KERNEL_VERSION(0,8,0),
+        .version        = KERNEL_VERSION(0, 9, 0),
         .capabilities   = (V4L2_CAP_VIDEO_CAPTURE |
                            V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_RADIO |
                            V4L2_CAP_READWRITE),
@@ -267,7 +267,7 @@ static long pvr2_v4l2_do_ioctl(struct file *file, unsigned int cmd, void *arg)
                 memset(&tmp,0,sizeof(tmp));
                 tmp.index = vi->index;
                 ret = 0;
-                if ((vi->index < 0) || (vi->index >= fh->input_cnt)) {
+                if (vi->index >= fh->input_cnt) {
                         ret = -EINVAL;
                         break;
                 }
@@ -331,7 +331,7 @@ static long pvr2_v4l2_do_ioctl(struct file *file, unsigned int cmd, void *arg)
         case VIDIOC_S_INPUT:
         {
                 struct v4l2_input *vi = (struct v4l2_input *)arg;
-                if ((vi->index < 0) || (vi->index >= fh->input_cnt)) {
+                if (vi->index >= fh->input_cnt) {
                         ret = -ERANGE;
                         break;
                 }
diff --git a/drivers/media/video/pwc/pwc-if.c b/drivers/media/video/pwc/pwc-if.c
index 7c542caf248e..db25c3034c11 100644
--- a/drivers/media/video/pwc/pwc-if.c
+++ b/drivers/media/video/pwc/pwc-if.c
@@ -601,7 +601,7 @@ static void pwc_snapshot_button(struct pwc_device *pdev, int down)
 
 #ifdef CONFIG_USB_PWC_INPUT_EVDEV
         if (pdev->button_dev) {
-                input_report_key(pdev->button_dev, BTN_0, down);
+                input_report_key(pdev->button_dev, KEY_CAMERA, down);
                 input_sync(pdev->button_dev);
         }
 #endif
@@ -1783,7 +1783,7 @@ static int usb_pwc_probe(struct usb_interface *intf, const struct usb_device_id
                 return -ENOMEM;
         }
         memcpy(pdev->vdev, &pwc_template, sizeof(pwc_template));
-        pdev->vdev->parent = &(udev->dev);
+        pdev->vdev->parent = &intf->dev;
         strcpy(pdev->vdev->name, name);
         video_set_drvdata(pdev->vdev, pdev);
 
@@ -1847,7 +1847,7 @@ static int usb_pwc_probe(struct usb_interface *intf, const struct usb_device_id
         usb_to_input_id(pdev->udev, &pdev->button_dev->id);
         pdev->button_dev->dev.parent = &pdev->udev->dev;
         pdev->button_dev->evbit[0] = BIT_MASK(EV_KEY);
-        pdev->button_dev->keybit[BIT_WORD(BTN_0)] = BIT_MASK(BTN_0);
+        pdev->button_dev->keybit[BIT_WORD(KEY_CAMERA)] = BIT_MASK(KEY_CAMERA);
 
         rc = input_register_device(pdev->button_dev);
         if (rc) {
diff --git a/drivers/media/video/pwc/pwc-v4l.c b/drivers/media/video/pwc/pwc-v4l.c
index bc0a464295c5..2876ce084510 100644
--- a/drivers/media/video/pwc/pwc-v4l.c
+++ b/drivers/media/video/pwc/pwc-v4l.c
@@ -1107,7 +1107,7 @@ long pwc_video_do_ioctl(struct file *file, unsigned int cmd, void *arg)
                                 return -EINVAL;
                         if (buf->memory != V4L2_MEMORY_MMAP)
                                 return -EINVAL;
-                        if (buf->index < 0 || buf->index >= pwc_mbufs)
+                        if (buf->index >= pwc_mbufs)
                                 return -EINVAL;
 
                         buf->flags |= V4L2_BUF_FLAG_QUEUED;
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index c639845460ff..f60de40fd21f 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -202,7 +202,7 @@ struct pxa_buffer {
 };
 
 struct pxa_camera_dev {
-        struct device           *dev;
+        struct soc_camera_host  soc_host;
         /* PXA27x is only supposed to handle one camera on its Quick Capture
          * interface. If anyone ever builds hardware to enable more than
          * one camera, they will have to modify this driver too */
@@ -261,7 +261,6 @@ static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
 {
         struct soc_camera_device *icd = vq->priv_data;
         struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
-        struct pxa_camera_dev *pcdev = ici->priv;
         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
         int i;
 
@@ -278,7 +277,7 @@ static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
 
         for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
                 if (buf->dmas[i].sg_cpu)
-                        dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
+                        dma_free_coherent(ici->dev, buf->dmas[i].sg_size,
                                           buf->dmas[i].sg_cpu,
                                           buf->dmas[i].sg_dma);
                 buf->dmas[i].sg_cpu = NULL;
@@ -338,14 +337,14 @@ static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
         int dma_len = 0, xfer_len = 0;
 
         if (pxa_dma->sg_cpu)
-                dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
+                dma_free_coherent(pcdev->soc_host.dev, pxa_dma->sg_size,
                                   pxa_dma->sg_cpu, pxa_dma->sg_dma);
 
         sglen = calculate_dma_sglen(*sg_first, dma->sglen,
                                     *sg_first_ofs, size);
 
         pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
-        pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
+        pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->soc_host.dev, pxa_dma->sg_size,
                                              &pxa_dma->sg_dma, GFP_KERNEL);
         if (!pxa_dma->sg_cpu)
                 return -ENOMEM;
@@ -353,7 +352,7 @@ static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
         pxa_dma->sglen = sglen;
         offset = *sg_first_ofs;
 
-        dev_dbg(pcdev->dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
+        dev_dbg(pcdev->soc_host.dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
                 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
 
 
@@ -376,7 +375,7 @@ static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
                 pxa_dma->sg_cpu[i].ddadr =
                         pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
 
-                dev_vdbg(pcdev->dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
+                dev_vdbg(pcdev->soc_host.dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
                          pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
                          sg_dma_address(sg) + offset, xfer_len);
                 offset = 0;
@@ -488,7 +487,7 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq,
                 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
                                            &sg, &next_ofs);
                 if (ret) {
-                        dev_err(pcdev->dev,
+                        dev_err(pcdev->soc_host.dev,
                                 "DMA initialization for Y/RGB failed\n");
                         goto fail;
                 }
@@ -498,7 +497,7 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq,
                         ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
                                                    size_u, &sg, &next_ofs);
                 if (ret) {
-                        dev_err(pcdev->dev,
+                        dev_err(pcdev->soc_host.dev,
                                 "DMA initialization for U failed\n");
                         goto fail_u;
                 }
@@ -508,7 +507,7 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq,
                         ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
                                                    size_v, &sg, &next_ofs);
                 if (ret) {
-                        dev_err(pcdev->dev,
+                        dev_err(pcdev->soc_host.dev,
                                 "DMA initialization for V failed\n");
                         goto fail_v;
                 }
@@ -522,10 +521,10 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq,
         return 0;
 
 fail_v:
-        dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
+        dma_free_coherent(pcdev->soc_host.dev, buf->dmas[1].sg_size,
                           buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
 fail_u:
-        dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
+        dma_free_coherent(pcdev->soc_host.dev, buf->dmas[0].sg_size,
                           buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
 fail:
         free_buffer(vq, buf);
@@ -549,7 +548,7 @@ static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
         active = pcdev->active;
 
         for (i = 0; i < pcdev->channels; i++) {
-                dev_dbg(pcdev->dev, "%s (channel=%d) ddadr=%08x\n", __func__,
+                dev_dbg(pcdev->soc_host.dev, "%s (channel=%d) ddadr=%08x\n", __func__,
                         i, active->dmas[i].sg_dma);
                 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
                 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
@@ -561,7 +560,7 @@ static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
         int i;
 
         for (i = 0; i < pcdev->channels; i++) {
-                dev_dbg(pcdev->dev, "%s (channel=%d)\n", __func__, i);
+                dev_dbg(pcdev->soc_host.dev, "%s (channel=%d)\n", __func__, i);
                 DCSR(pcdev->dma_chans[i]) = 0;
         }
 }
@@ -597,7 +596,7 @@ static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
 {
         unsigned long cicr0, cifr;
 
-        dev_dbg(pcdev->dev, "%s\n", __func__);
+        dev_dbg(pcdev->soc_host.dev, "%s\n", __func__);
         /* Reset the FIFOs */
         cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
         __raw_writel(cifr, pcdev->base + CIFR);
@@ -617,7 +616,7 @@ static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
         __raw_writel(cicr0, pcdev->base + CICR0);
 
         pcdev->active = NULL;
-        dev_dbg(pcdev->dev, "%s\n", __func__);
+        dev_dbg(pcdev->soc_host.dev, "%s\n", __func__);
 }
 
 static void pxa_videobuf_queue(struct videobuf_queue *vq,
@@ -686,7 +685,7 @@ static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
         do_gettimeofday(&vb->ts);
         vb->field_count++;
         wake_up(&vb->done);
-        dev_dbg(pcdev->dev, "%s dequeud buffer (vb=0x%p)\n", __func__, vb);
+        dev_dbg(pcdev->soc_host.dev, "%s dequeud buffer (vb=0x%p)\n", __func__, vb);
 
         if (list_empty(&pcdev->capture)) {
                 pxa_camera_stop_capture(pcdev);
@@ -722,7 +721,7 @@ static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
         for (i = 0; i < pcdev->channels; i++)
                 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
                         is_dma_stopped = 0;
-        dev_dbg(pcdev->dev, "%s : top queued buffer=%p, dma_stopped=%d\n",
+        dev_dbg(pcdev->soc_host.dev, "%s : top queued buffer=%p, dma_stopped=%d\n",
                 __func__, pcdev->active, is_dma_stopped);
         if (pcdev->active && is_dma_stopped)
                 pxa_camera_start_capture(pcdev);
@@ -747,12 +746,12 @@ static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
                 overrun |= CISR_IFO_1 | CISR_IFO_2;
 
         if (status & DCSR_BUSERR) {
-                dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
+                dev_err(pcdev->soc_host.dev, "DMA Bus Error IRQ!\n");
                 goto out;
         }
 
         if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
-                dev_err(pcdev->dev, "Unknown DMA IRQ source, "
+                dev_err(pcdev->soc_host.dev, "Unknown DMA IRQ source, "
                         "status: 0x%08x\n", status);
                 goto out;
         }
@@ -776,7 +775,7 @@ static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
         buf = container_of(vb, struct pxa_buffer, vb);
         WARN_ON(buf->inwork || list_empty(&vb->queue));
 
-        dev_dbg(pcdev->dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
+        dev_dbg(pcdev->soc_host.dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
                 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
                 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
 
@@ -787,7 +786,7 @@ static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
                  */
                 if (camera_status & overrun &&
                     !list_is_last(pcdev->capture.next, &pcdev->capture)) {
-                        dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n",
+                        dev_dbg(pcdev->soc_host.dev, "FIFO overrun! CISR: %x\n",
                                 camera_status);
                         pxa_camera_stop_capture(pcdev);
                         pxa_camera_start_capture(pcdev);
@@ -854,7 +853,7 @@ static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
         /* mclk <= ciclk / 4 (27.4.2) */
         if (mclk > lcdclk / 4) {
                 mclk = lcdclk / 4;
-                dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk);
+                dev_warn(pcdev->soc_host.dev, "Limiting master clock to %lu\n", mclk);
         }
 
         /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
@@ -864,7 +863,7 @@ static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
         if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
                 pcdev->mclk = lcdclk / (2 * (div + 1));
 
-        dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, "
+        dev_dbg(pcdev->soc_host.dev, "LCD clock %luHz, target freq %luHz, "
                 "divisor %u\n", lcdclk, mclk, div);
 
         return div;
@@ -884,12 +883,12 @@ static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
         struct pxacamera_platform_data *pdata = pcdev->pdata;
         u32 cicr4 = 0;
 
-        dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
+        dev_dbg(pcdev->soc_host.dev, "Registered platform device at %p data %p\n",
                 pcdev, pdata);
 
         if (pdata && pdata->init) {
-                dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
-                pdata->init(pcdev->dev);
+                dev_dbg(pcdev->soc_host.dev, "%s: Init gpios\n", __func__);
+                pdata->init(pcdev->soc_host.dev);
         }
 
         /* disable all interrupts */
@@ -931,7 +930,7 @@ static irqreturn_t pxa_camera_irq(int irq, void *data)
         struct videobuf_buffer *vb;
 
         status = __raw_readl(pcdev->base + CISR);
-        dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status);
+        dev_dbg(pcdev->soc_host.dev, "Camera interrupt status 0x%lx\n", status);
 
         if (!status)
                 return IRQ_NONE;
@@ -1259,7 +1258,7 @@ static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
                         xlate->cam_fmt = icd->formats + idx;
                         xlate->buswidth = buswidth;
                         xlate++;
-                        dev_dbg(&ici->dev, "Providing format %s using %s\n",
+                        dev_dbg(ici->dev, "Providing format %s using %s\n",
                                 pxa_camera_formats[0].name,
                                 icd->formats[idx].name);
                 }
@@ -1274,7 +1273,7 @@ static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
                         xlate->cam_fmt = icd->formats + idx;
                         xlate->buswidth = buswidth;
                         xlate++;
-                        dev_dbg(&ici->dev, "Providing format %s packed\n",
+                        dev_dbg(ici->dev, "Providing format %s packed\n",
                                 icd->formats[idx].name);
                 }
                 break;
@@ -1286,7 +1285,7 @@ static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
                         xlate->cam_fmt = icd->formats + idx;
                         xlate->buswidth = icd->formats[idx].depth;
                         xlate++;
-                        dev_dbg(&ici->dev,
+                        dev_dbg(ici->dev,
                                 "Providing format %s in pass-through mode\n",
                                 icd->formats[idx].name);
                 }
@@ -1315,11 +1314,11 @@ static int pxa_camera_set_crop(struct soc_camera_device *icd,
         icd->sense = NULL;
 
         if (ret < 0) {
-                dev_warn(&ici->dev, "Failed to crop to %ux%u@%u:%u\n",
+                dev_warn(ici->dev, "Failed to crop to %ux%u@%u:%u\n",
                          rect->width, rect->height, rect->left, rect->top);
         } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
                 if (sense.pixel_clock > sense.pixel_clock_max) {
-                        dev_err(&ici->dev,
+                        dev_err(ici->dev,
                                 "pixel clock %lu set by the camera too high!",
                                 sense.pixel_clock);
                         return -EIO;
@@ -1347,7 +1346,7 @@ static int pxa_camera_set_fmt(struct soc_camera_device *icd,
 
         xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
         if (!xlate) {
-                dev_warn(&ici->dev, "Format %x not found\n", pix->pixelformat);
+                dev_warn(ici->dev, "Format %x not found\n", pix->pixelformat);
                 return -EINVAL;
         }
 
@@ -1363,11 +1362,11 @@ static int pxa_camera_set_fmt(struct soc_camera_device *icd,
         icd->sense = NULL;
 
         if (ret < 0) {
-                dev_warn(&ici->dev, "Failed to configure for format %x\n",
+                dev_warn(ici->dev, "Failed to configure for format %x\n",
                          pix->pixelformat);
         } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
                 if (sense.pixel_clock > sense.pixel_clock_max) {
-                        dev_err(&ici->dev,
+                        dev_err(ici->dev,
                                 "pixel clock %lu set by the camera too high!",
                                 sense.pixel_clock);
                         return -EIO;
@@ -1395,7 +1394,7 @@ static int pxa_camera_try_fmt(struct soc_camera_device *icd,
 
         xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
         if (!xlate) {
-                dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
+                dev_warn(ici->dev, "Format %x not found\n", pixfmt);
                 return -EINVAL;
         }
 
@@ -1552,13 +1551,7 @@ static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
         .set_bus_param  = pxa_camera_set_bus_param,
 };
 
-/* Should be allocated dynamically too, but we have only one. */
-static struct soc_camera_host pxa_soc_camera_host = {
-        .drv_name               = PXA_CAM_DRV_NAME,
-        .ops                    = &pxa_soc_camera_host_ops,
-};
-
-static int pxa_camera_probe(struct platform_device *pdev)
+static int __devinit pxa_camera_probe(struct platform_device *pdev)
 {
         struct pxa_camera_dev *pcdev;
         struct resource *res;
@@ -1586,7 +1579,6 @@ static int pxa_camera_probe(struct platform_device *pdev)
                 goto exit_kfree;
         }
 
-        dev_set_drvdata(&pdev->dev, pcdev);
         pcdev->res = res;
 
         pcdev->pdata = pdev->dev.platform_data;
@@ -1607,7 +1599,6 @@ static int pxa_camera_probe(struct platform_device *pdev)
                 pcdev->mclk = 20000000;
         }
 
-        pcdev->dev = &pdev->dev;
         pcdev->mclk_divisor = mclk_get_divisor(pcdev);
 
         INIT_LIST_HEAD(&pcdev->capture);
@@ -1616,13 +1607,13 @@ static int pxa_camera_probe(struct platform_device *pdev)
         /*
          * Request the regions.
          */
-        if (!request_mem_region(res->start, res->end - res->start + 1,
+        if (!request_mem_region(res->start, resource_size(res),
                                 PXA_CAM_DRV_NAME)) {
                 err = -EBUSY;
                 goto exit_clk;
         }
 
-        base = ioremap(res->start, res->end - res->start + 1);
+        base = ioremap(res->start, resource_size(res));
         if (!base) {
                 err = -ENOMEM;
                 goto exit_release;
@@ -1634,29 +1625,29 @@ static int pxa_camera_probe(struct platform_device *pdev)
         err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
                               pxa_camera_dma_irq_y, pcdev);
         if (err < 0) {
-                dev_err(pcdev->dev, "Can't request DMA for Y\n");
+                dev_err(&pdev->dev, "Can't request DMA for Y\n");
                 goto exit_iounmap;
         }
         pcdev->dma_chans[0] = err;
-        dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
+        dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
 
         err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
                               pxa_camera_dma_irq_u, pcdev);
         if (err < 0) {
-                dev_err(pcdev->dev, "Can't request DMA for U\n");
+                dev_err(&pdev->dev, "Can't request DMA for U\n");
                 goto exit_free_dma_y;
         }
         pcdev->dma_chans[1] = err;
-        dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
+        dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
 
         err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
                               pxa_camera_dma_irq_v, pcdev);
         if (err < 0) {
-                dev_err(pcdev->dev, "Can't request DMA for V\n");
+                dev_err(&pdev->dev, "Can't request DMA for V\n");
                 goto exit_free_dma_u;
         }
         pcdev->dma_chans[2] = err;
-        dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
+        dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
 
         DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
         DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
@@ -1666,14 +1657,17 @@ static int pxa_camera_probe(struct platform_device *pdev)
         err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
                           pcdev);
         if (err) {
-                dev_err(pcdev->dev, "Camera interrupt register failed \n");
+                dev_err(&pdev->dev, "Camera interrupt register failed \n");
                 goto exit_free_dma;
         }
 
-        pxa_soc_camera_host.priv        = pcdev;
-        pxa_soc_camera_host.dev.parent  = &pdev->dev;
-        pxa_soc_camera_host.nr          = pdev->id;
-        err = soc_camera_host_register(&pxa_soc_camera_host);
+        pcdev->soc_host.drv_name        = PXA_CAM_DRV_NAME;
+        pcdev->soc_host.ops             = &pxa_soc_camera_host_ops;
+        pcdev->soc_host.priv            = pcdev;
+        pcdev->soc_host.dev             = &pdev->dev;
+        pcdev->soc_host.nr              = pdev->id;
+
+        err = soc_camera_host_register(&pcdev->soc_host);
         if (err)
                 goto exit_free_irq;
 
@@ -1690,7 +1684,7 @@ exit_free_dma_y:
 exit_iounmap:
         iounmap(base);
 exit_release:
-        release_mem_region(res->start, res->end - res->start + 1);
+        release_mem_region(res->start, resource_size(res));
 exit_clk:
         clk_put(pcdev->clk);
 exit_kfree:
@@ -1701,7 +1695,9 @@ exit:
 
 static int __devexit pxa_camera_remove(struct platform_device *pdev)
 {
-        struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
+        struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
+        struct pxa_camera_dev *pcdev = container_of(soc_host,
+                                        struct pxa_camera_dev, soc_host);
         struct resource *res;
 
         clk_put(pcdev->clk);
@@ -1711,12 +1707,12 @@ static int __devexit pxa_camera_remove(struct platform_device *pdev)
         pxa_free_dma(pcdev->dma_chans[2]);
         free_irq(pcdev->irq, pcdev);
 
-        soc_camera_host_unregister(&pxa_soc_camera_host);
+        soc_camera_host_unregister(soc_host);
 
         iounmap(pcdev->base);
 
         res = pcdev->res;
-        release_mem_region(res->start, res->end - res->start + 1);
+        release_mem_region(res->start, resource_size(res));
 
         kfree(pcdev);
 
@@ -1730,11 +1726,11 @@ static struct platform_driver pxa_camera_driver = {
                 .name   = PXA_CAM_DRV_NAME,
         },
         .probe          = pxa_camera_probe,
-        .remove         = __exit_p(pxa_camera_remove),
+        .remove         = __devexit_p(pxa_camera_remove),
 };
 
 
-static int __devinit pxa_camera_init(void)
+static int __init pxa_camera_init(void)
 {
         return platform_driver_register(&pxa_camera_driver);
 }
diff --git a/drivers/media/video/s2255drv.c b/drivers/media/video/s2255drv.c
index 30f4698be90a..6be845ccc7d7 100644
--- a/drivers/media/video/s2255drv.c
+++ b/drivers/media/video/s2255drv.c
@@ -77,6 +77,8 @@
 #define MAX_CHANNELS            4
 #define S2255_MARKER_FRAME      0x2255DA4AL
 #define S2255_MARKER_RESPONSE   0x2255ACACL
+#define S2255_RESPONSE_SETMODE  0x01
+#define S2255_RESPONSE_FW       0x10
 #define S2255_USB_XFER_SIZE     (16 * 1024)
 #define MAX_CHANNELS            4
 #define MAX_PIPE_BUFFERS        1
@@ -107,6 +109,8 @@
 #define SCALE_4CIFS     1       /* 640x480(NTSC) or 704x576(PAL) */
 #define SCALE_2CIFS     2       /* 640x240(NTSC) or 704x288(PAL) */
 #define SCALE_1CIFS     3       /* 320x240(NTSC) or 352x288(PAL) */
+/* SCALE_4CIFSI is the 2 fields interpolated into one */
+#define SCALE_4CIFSI    4       /* 640x480(NTSC) or 704x576(PAL) high quality */
 
 #define COLOR_YUVPL     1       /* YUV planar */
 #define COLOR_YUVPK     2       /* YUV packed */
@@ -178,9 +182,6 @@ struct s2255_bufferi {
 
 struct s2255_dmaqueue {
         struct list_head        active;
-        /* thread for acquisition */
-        struct task_struct      *kthread;
-        int                     frame;
         struct s2255_dev        *dev;
         int                     channel;
 };
@@ -210,16 +211,11 @@ struct s2255_pipeinfo {
         u32 max_transfer_size;
         u32 cur_transfer_size;
         u8 *transfer_buffer;
-        u32 transfer_flags;;
         u32 state;
-        u32 prev_state;
-        u32 urb_size;
         void *stream_urb;
         void *dev;      /* back pointer to s2255_dev struct*/
         u32 err_count;
-        u32 buf_index;
         u32 idx;
-        u32 priority_set;
 };
 
 struct s2255_fmt; /*forward declaration */
@@ -239,13 +235,13 @@ struct s2255_dev {
         struct list_head        s2255_devlist;
         struct timer_list       timer;
         struct s2255_fw *fw_data;
-        int                     board_num;
-        int                     is_open;
         struct s2255_pipeinfo   pipes[MAX_PIPE_BUFFERS];
         struct s2255_bufferi            buffer[MAX_CHANNELS];
         struct s2255_mode       mode[MAX_CHANNELS];
         /* jpeg compression */
         struct v4l2_jpegcompression jc[MAX_CHANNELS];
+        /* capture parameters (for high quality mode full size) */
+        struct v4l2_captureparm cap_parm[MAX_CHANNELS];
         const struct s2255_fmt  *cur_fmt[MAX_CHANNELS];
         int                     cur_frame[MAX_CHANNELS];
         int                     last_frame[MAX_CHANNELS];
@@ -297,9 +293,10 @@ struct s2255_fh {
         int                     resources[MAX_CHANNELS];
 };
 
-#define CUR_USB_FWVER   774     /* current cypress EEPROM firmware version */
+/* current cypress EEPROM firmware version */
+#define S2255_CUR_USB_FWVER     ((3 << 8) | 6)
 #define S2255_MAJOR_VERSION     1
-#define S2255_MINOR_VERSION     13
+#define S2255_MINOR_VERSION     14
 #define S2255_RELEASE           0
 #define S2255_VERSION           KERNEL_VERSION(S2255_MAJOR_VERSION, \
                                                S2255_MINOR_VERSION, \
@@ -1027,9 +1024,16 @@ static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
         fh->type = f->type;
         norm = norm_minw(fh->dev->vdev[fh->channel]);
         if (fh->width > norm_minw(fh->dev->vdev[fh->channel])) {
-                if (fh->height > norm_minh(fh->dev->vdev[fh->channel]))
-                        fh->mode.scale = SCALE_4CIFS;
-                else
+                if (fh->height > norm_minh(fh->dev->vdev[fh->channel])) {
+                        if (fh->dev->cap_parm[fh->channel].capturemode &
+                            V4L2_MODE_HIGHQUALITY) {
+                                fh->mode.scale = SCALE_4CIFSI;
+                                dprintk(2, "scale 4CIFSI\n");
+                        } else {
+                                fh->mode.scale = SCALE_4CIFS;
+                                dprintk(2, "scale 4CIFS\n");
+                        }
+                } else
                         fh->mode.scale = SCALE_2CIFS;
 
         } else {
@@ -1130,6 +1134,7 @@ static u32 get_transfer_size(struct s2255_mode *mode)
         if (mode->format == FORMAT_NTSC) {
                 switch (mode->scale) {
                 case SCALE_4CIFS:
+                case SCALE_4CIFSI:
                         linesPerFrame = NUM_LINES_4CIFS_NTSC * 2;
                         pixelsPerLine = LINE_SZ_4CIFS_NTSC;
                         break;
@@ -1147,6 +1152,7 @@ static u32 get_transfer_size(struct s2255_mode *mode)
         } else if (mode->format == FORMAT_PAL) {
                 switch (mode->scale) {
                 case SCALE_4CIFS:
+                case SCALE_4CIFSI:
                         linesPerFrame = NUM_LINES_4CIFS_PAL * 2;
                         pixelsPerLine = LINE_SZ_4CIFS_PAL;
                         break;
@@ -1502,6 +1508,33 @@ static int vidioc_s_jpegcomp(struct file *file, void *priv,
         dprintk(2, "setting jpeg quality %d\n", jc->quality);
         return 0;
 }
+
+static int vidioc_g_parm(struct file *file, void *priv,
+                         struct v4l2_streamparm *sp)
+{
+        struct s2255_fh *fh = priv;
+        struct s2255_dev *dev = fh->dev;
+        if (sp->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+                return -EINVAL;
+        sp->parm.capture.capturemode = dev->cap_parm[fh->channel].capturemode;
+        dprintk(2, "getting parm %d\n", sp->parm.capture.capturemode);
+        return 0;
+}
+
+static int vidioc_s_parm(struct file *file, void *priv,
+                         struct v4l2_streamparm *sp)
+{
+        struct s2255_fh *fh = priv;
+        struct s2255_dev *dev = fh->dev;
+
+        if (sp->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+                return -EINVAL;
+
+        dev->cap_parm[fh->channel].capturemode = sp->parm.capture.capturemode;
+        dprintk(2, "setting param capture mode %d\n",
+                sp->parm.capture.capturemode);
+        return 0;
+}
 static int s2255_open(struct file *file)
 {
         int minor = video_devdata(file)->minor;
@@ -1793,6 +1826,8 @@ static const struct v4l2_ioctl_ops s2255_ioctl_ops = {
 #endif
         .vidioc_s_jpegcomp = vidioc_s_jpegcomp,
         .vidioc_g_jpegcomp = vidioc_g_jpegcomp,
+        .vidioc_s_parm = vidioc_s_parm,
+        .vidioc_g_parm = vidioc_g_parm,
 };
 
 static struct video_device template = {
@@ -1818,7 +1853,6 @@ static int s2255_probe_v4l(struct s2255_dev *dev)
                 INIT_LIST_HEAD(&dev->vidq[i].active);
                 dev->vidq[i].dev = dev;
                 dev->vidq[i].channel = i;
-                dev->vidq[i].kthread = NULL;
                 /* register 4 video devices */
                 dev->vdev[i] = video_device_alloc();
                 memcpy(dev->vdev[i], &template, sizeof(struct video_device));
@@ -1839,7 +1873,9 @@ static int s2255_probe_v4l(struct s2255_dev *dev)
                         return ret;
                 }
         }
-        printk(KERN_INFO "Sensoray 2255 V4L driver\n");
+        printk(KERN_INFO "Sensoray 2255 V4L driver Revision: %d.%d\n",
+               S2255_MAJOR_VERSION,
+               S2255_MINOR_VERSION);
         return ret;
 }
 
@@ -1929,14 +1965,14 @@ static int save_frame(struct s2255_dev *dev, struct s2255_pipeinfo *pipe_info)
                                 if (!(cc >= 0 && cc < MAX_CHANNELS))
                                         break;
                                 switch (pdword[2]) {
-                                case 0x01:
+                                case S2255_RESPONSE_SETMODE:
                                         /* check if channel valid */
                                         /* set mode ready */
                                         dev->setmode_ready[cc] = 1;
                                         wake_up(&dev->wait_setmode[cc]);
                                         dprintk(5, "setmode ready %d\n", cc);
                                         break;
-                                case 0x10:
+                                case S2255_RESPONSE_FW:
 
                                         dev->chn_ready |= (1 << cc);
                                         if ((dev->chn_ready & 0x0f) != 0x0f)
@@ -2172,10 +2208,15 @@ static int s2255_board_init(struct s2255_dev *dev)
         /* query the firmware */
         fw_ver = s2255_get_fx2fw(dev);
 
-        printk(KERN_INFO "2255 usb firmware version %d \n", fw_ver);
-        if (fw_ver < CUR_USB_FWVER)
+        printk(KERN_INFO "2255 usb firmware version %d.%d\n",
+               (fw_ver >> 8) & 0xff,
+               fw_ver & 0xff);
+
+        if (fw_ver < S2255_CUR_USB_FWVER)
                 dev_err(&dev->udev->dev,
-                        "usb firmware not up to date %d\n", fw_ver);
+                        "usb firmware not up to date %d.%d\n",
+                        (fw_ver >> 8) & 0xff,
+                        fw_ver & 0xff);
 
         for (j = 0; j < MAX_CHANNELS; j++) {
                 dev->b_acquire[j] = 0;
@@ -2240,8 +2281,10 @@ static void read_pipe_completion(struct urb *purb)
                 return;
         }
         status = purb->status;
-        if (status != 0) {
-                dprintk(2, "read_pipe_completion: err\n");
+        /* if shutting down, do not resubmit, exit immediately */
+        if (status == -ESHUTDOWN) {
+                dprintk(2, "read_pipe_completion: err shutdown\n");
+                pipe_info->err_count++;
                 return;
         }
 
@@ -2250,9 +2293,13 @@ static void read_pipe_completion(struct urb *purb)
                 return;
         }
 
-        s2255_read_video_callback(dev, pipe_info);
+        if (status == 0)
+                s2255_read_video_callback(dev, pipe_info);
+        else {
+                pipe_info->err_count++;
+                dprintk(1, "s2255drv: failed URB %d\n", status);
+        }
 
-        pipe_info->err_count = 0;
         pipe = usb_rcvbulkpipe(dev->udev, dev->read_endpoint);
         /* reuse urb */
         usb_fill_bulk_urb(pipe_info->stream_urb, dev->udev,
@@ -2264,7 +2311,6 @@ static void read_pipe_completion(struct urb *purb)
         if (pipe_info->state != 0) {
                 if (usb_submit_urb(pipe_info->stream_urb, GFP_KERNEL)) {
                         dev_err(&dev->udev->dev, "error submitting urb\n");
-                        usb_free_urb(pipe_info->stream_urb);
                 }
         } else {
                 dprintk(2, "read pipe complete state 0\n");
@@ -2283,8 +2329,7 @@ static int s2255_start_readpipe(struct s2255_dev *dev)
 
         for (i = 0; i < MAX_PIPE_BUFFERS; i++) {
                 pipe_info->state = 1;
-                pipe_info->buf_index = (u32) i;
-                pipe_info->priority_set = 0;
+                pipe_info->err_count = 0;
                 pipe_info->stream_urb = usb_alloc_urb(0, GFP_KERNEL);
                 if (!pipe_info->stream_urb) {
                         dev_err(&dev->udev->dev,
@@ -2298,7 +2343,6 @@ static int s2255_start_readpipe(struct s2255_dev *dev)
                                   pipe_info->cur_transfer_size,
                                   read_pipe_completion, pipe_info);
 
-                pipe_info->urb_size = sizeof(pipe_info->stream_urb);
                 dprintk(4, "submitting URB %p\n", pipe_info->stream_urb);
                 retval = usb_submit_urb(pipe_info->stream_urb, GFP_KERNEL);
                 if (retval) {
@@ -2403,8 +2447,6 @@ static void s2255_stop_readpipe(struct s2255_dev *dev)
                         if (pipe_info->state == 0)
                                 continue;
                         pipe_info->state = 0;
-                        pipe_info->prev_state = 1;
-
                 }
         }
 
@@ -2542,7 +2584,9 @@ static int s2255_probe(struct usb_interface *interface,
         s2255_probe_v4l(dev);
         usb_reset_device(dev->udev);
         /* load 2255 board specific */
-        s2255_board_init(dev);
+        retval = s2255_board_init(dev);
+        if (retval)
+                goto error;
 
         dprintk(4, "before probe done %p\n", dev);
         spin_lock_init(&dev->slock);
diff --git a/drivers/media/video/saa7134/Kconfig b/drivers/media/video/saa7134/Kconfig
index 0ba68987bfce..5bcce092e804 100644
--- a/drivers/media/video/saa7134/Kconfig
+++ b/drivers/media/video/saa7134/Kconfig
@@ -44,6 +44,7 @@ config VIDEO_SAA7134_DVB
         select DVB_LNBP21 if !DVB_FE_CUSTOMISE
         select DVB_ZL10353 if !DVB_FE_CUSTOMISE
         select DVB_LGDT3305 if !DVB_FE_CUSTOMISE
+        select DVB_TDA10048 if !DVB_FE_CUSTOMISE
         select MEDIA_TUNER_TDA18271 if !MEDIA_TUNER_CUSTOMISE
         select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMISE
         ---help---
diff --git a/drivers/media/video/saa7134/Makefile b/drivers/media/video/saa7134/Makefile
index 3dbaa19a6d00..604158a8c235 100644
--- a/drivers/media/video/saa7134/Makefile
+++ b/drivers/media/video/saa7134/Makefile
@@ -3,8 +3,7 @@ saa7134-objs :=	saa7134-cards.o saa7134-core.o saa7134-i2c.o	\
                 saa7134-ts.o saa7134-tvaudio.o saa7134-vbi.o    \
                 saa7134-video.o saa7134-input.o
 
-obj-$(CONFIG_VIDEO_SAA7134) +=  saa7134.o saa7134-empress.o \
-                                saa6752hs.o
+obj-$(CONFIG_VIDEO_SAA7134) +=  saa6752hs.o saa7134.o saa7134-empress.o
 
 obj-$(CONFIG_VIDEO_SAA7134_ALSA) += saa7134-alsa.o
 
diff --git a/drivers/media/video/saa7134/saa7134-cards.c b/drivers/media/video/saa7134/saa7134-cards.c
index fdb19449d269..06861b782b95 100644
--- a/drivers/media/video/saa7134/saa7134-cards.c
+++ b/drivers/media/video/saa7134/saa7134-cards.c
@@ -1669,6 +1669,39 @@ struct saa7134_board saa7134_boards[] = {
                         .amux = LINE1,
                 },
         },
+        [SAA7134_BOARD_AVERMEDIA_CARDBUS_501] = {
+                /* Oldrich Jedlicka <oldium.pro@seznam.cz> */
+                .name           = "AVerMedia Cardbus TV/Radio (E501R)",
+                .audio_clock    = 0x187de7,
+                .tuner_type     = TUNER_ALPS_TSBE5_PAL,
+                .radio_type     = TUNER_TEA5767,
+                .tuner_addr     = 0x61,
+                .radio_addr     = 0x60,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .gpiomask       = 0x08000000,
+                .inputs         = { {
+                        .name = name_tv,
+                        .vmux = 1,
+                        .amux = TV,
+                        .tv   = 1,
+                        .gpio = 0x08000000,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 3,
+                        .amux = LINE1,
+                        .gpio = 0x08000000,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                        .gpio = 0x08000000,
+                } },
+                .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                        .gpio = 0x00000000,
+                },
+        },
         [SAA7134_BOARD_CINERGY400_CARDBUS] = {
                 .name           = "Terratec Cinergy 400 mobile",
                 .audio_clock    = 0x187de7,
@@ -3331,13 +3364,15 @@ struct saa7134_board saa7134_boards[] = {
                 },
         },
         [SAA7134_BOARD_HAUPPAUGE_HVR1110R3] = {
-                .name           = "Hauppauge WinTV-HVR1110r3",
+                .name           = "Hauppauge WinTV-HVR1110r3 DVB-T/Hybrid",
                 .audio_clock    = 0x00187de7,
                 .tuner_type     = TUNER_PHILIPS_TDA8290,
                 .radio_type     = UNSET,
                 .tuner_addr     = ADDR_UNSET,
                 .radio_addr     = ADDR_UNSET,
                 .tuner_config   = 3,
+                .mpeg           = SAA7134_MPEG_DVB,
+                .ts_type        = SAA7134_MPEG_TS_SERIAL,
                 .gpiomask       = 0x0800100, /* GPIO 21 is an INPUT */
                 .inputs         = {{
                         .name = name_tv,
@@ -4006,7 +4041,7 @@ struct saa7134_board saa7134_boards[] = {
         [SAA7134_BOARD_BEHOLD_505FM] = {
                 /*       Beholder Intl. Ltd. 2008      */
                 /*Dmitry Belimov <d.belimov@gmail.com> */
-                .name           = "Beholder BeholdTV 505 FM/RDS",
+                .name           = "Beholder BeholdTV 505 FM",
                 .audio_clock    = 0x00200000,
                 .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
                 .radio_type     = UNSET,
@@ -4019,6 +4054,40 @@ struct saa7134_board saa7134_boards[] = {
                         .vmux = 3,
                         .amux = LINE2,
                         .tv   = 1,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 1,
+                        .amux = LINE1,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                } },
+                .mute = {
+                        .name = name_mute,
+                        .amux = LINE1,
+                },
+                .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                },
+        },
+        [SAA7134_BOARD_BEHOLD_505RDS] = {
+                /*       Beholder Intl. Ltd. 2008      */
+                /*Dmitry Belimov <d.belimov@gmail.com> */
+                .name           = "Beholder BeholdTV 505 RDS",
+                .audio_clock    = 0x00200000,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .gpiomask       = 0x00008000,
+                .inputs         = {{
+                        .name = name_tv,
+                        .vmux = 3,
+                        .amux = LINE2,
+                        .tv   = 1,
                 },{
                         .name = name_comp1,
                         .vmux = 1,
@@ -4040,7 +4109,7 @@ struct saa7134_board saa7134_boards[] = {
         [SAA7134_BOARD_BEHOLD_507_9FM] = {
                 /*       Beholder Intl. Ltd. 2008      */
                 /*Dmitry Belimov <d.belimov@gmail.com> */
-                .name           = "Beholder BeholdTV 507 FM/RDS / BeholdTV 509 FM",
+                .name           = "Beholder BeholdTV 507 FM / BeholdTV 509 FM",
                 .audio_clock    = 0x00187de7,
                 .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
                 .radio_type     = UNSET,
@@ -4067,6 +4136,66 @@ struct saa7134_board saa7134_boards[] = {
                         .amux = LINE2,
                 },
         },
+        [SAA7134_BOARD_BEHOLD_507RDS_MK5] = {
+                /*       Beholder Intl. Ltd. 2008      */
+                /*Dmitry Belimov <d.belimov@gmail.com> */
+                .name           = "Beholder BeholdTV 507 RDS",
+                .audio_clock    = 0x00187de7,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .gpiomask       = 0x00008000,
+                .inputs         = {{
+                        .name = name_tv,
+                        .vmux = 3,
+                        .amux = TV,
+                        .tv   = 1,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 1,
+                        .amux = LINE1,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                } },
+                        .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                },
+        },
+        [SAA7134_BOARD_BEHOLD_507RDS_MK3] = {
+                /*       Beholder Intl. Ltd. 2008      */
+                /*Dmitry Belimov <d.belimov@gmail.com> */
+                .name           = "Beholder BeholdTV 507 RDS",
+                .audio_clock    = 0x00187de7,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .gpiomask       = 0x00008000,
+                .inputs         = {{
+                        .name = name_tv,
+                        .vmux = 3,
+                        .amux = TV,
+                        .tv   = 1,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 1,
+                        .amux = LINE1,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                } },
+                        .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                },
+        },
         [SAA7134_BOARD_BEHOLD_COLUMBUS_TVFM] = {
                 /*       Beholder Intl. Ltd. 2008      */
                 /*Dmitry Belimov <d.belimov@gmail.com> */
@@ -4101,9 +4230,121 @@ struct saa7134_board saa7134_boards[] = {
                         .gpio = 0x000A8000,
                 },
         },
-        [SAA7134_BOARD_BEHOLD_607_9FM] = {
+        [SAA7134_BOARD_BEHOLD_607FM_MK3] = {
+                /* Andrey Melnikoff <temnota@kmv.ru> */
+                .name           = "Beholder BeholdTV 607 FM",
+                .audio_clock    = 0x00187de7,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .inputs         = {{
+                        .name = name_tv,
+                        .vmux = 3,
+                        .amux = TV,
+                        .tv   = 1,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 1,
+                        .amux = LINE1,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                } },
+                .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                },
+        },
+        [SAA7134_BOARD_BEHOLD_609FM_MK3] = {
+                /* Andrey Melnikoff <temnota@kmv.ru> */
+                .name           = "Beholder BeholdTV 609 FM",
+                .audio_clock    = 0x00187de7,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .inputs         = {{
+                        .name = name_tv,
+                        .vmux = 3,
+                        .amux = TV,
+                        .tv   = 1,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 1,
+                        .amux = LINE1,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                } },
+                .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                },
+        },
+        [SAA7134_BOARD_BEHOLD_607FM_MK5] = {
+                /* Andrey Melnikoff <temnota@kmv.ru> */
+                .name           = "Beholder BeholdTV 607 FM",
+                .audio_clock    = 0x00187de7,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .inputs         = {{
+                        .name = name_tv,
+                        .vmux = 3,
+                        .amux = TV,
+                        .tv   = 1,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 1,
+                        .amux = LINE1,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                } },
+                .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                },
+        },
+        [SAA7134_BOARD_BEHOLD_609FM_MK5] = {
                 /* Andrey Melnikoff <temnota@kmv.ru> */
-                .name           = "Beholder BeholdTV 607 / BeholdTV 609",
+                .name           = "Beholder BeholdTV 609 FM",
+                .audio_clock    = 0x00187de7,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .inputs         = {{
+                        .name = name_tv,
+                        .vmux = 3,
+                        .amux = TV,
+                        .tv   = 1,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 1,
+                        .amux = LINE1,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                } },
+                .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                },
+        },
+        [SAA7134_BOARD_BEHOLD_607RDS_MK3] = {
+                /* Andrey Melnikoff <temnota@kmv.ru> */
+                .name           = "Beholder BeholdTV 607 RDS",
                 .audio_clock    = 0x00187de7,
                 .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
                 .radio_type     = UNSET,
@@ -4115,6 +4356,90 @@ struct saa7134_board saa7134_boards[] = {
                         .vmux = 3,
                         .amux = TV,
                         .tv   = 1,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 1,
+                        .amux = LINE1,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                } },
+                .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                },
+        },
+        [SAA7134_BOARD_BEHOLD_609RDS_MK3] = {
+                /* Andrey Melnikoff <temnota@kmv.ru> */
+                .name           = "Beholder BeholdTV 609 RDS",
+                .audio_clock    = 0x00187de7,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .inputs         = {{
+                        .name = name_tv,
+                        .vmux = 3,
+                        .amux = TV,
+                        .tv   = 1,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 1,
+                        .amux = LINE1,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                } },
+                .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                },
+        },
+        [SAA7134_BOARD_BEHOLD_607RDS_MK5] = {
+                /* Andrey Melnikoff <temnota@kmv.ru> */
+                .name           = "Beholder BeholdTV 607 RDS",
+                .audio_clock    = 0x00187de7,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .inputs         = {{
+                        .name = name_tv,
+                        .vmux = 3,
+                        .amux = TV,
+                        .tv   = 1,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 1,
+                        .amux = LINE1,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                } },
+                .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                },
+        },
+        [SAA7134_BOARD_BEHOLD_609RDS_MK5] = {
+                /* Andrey Melnikoff <temnota@kmv.ru> */
+                .name           = "Beholder BeholdTV 609 RDS",
+                .audio_clock    = 0x00187de7,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .inputs         = {{
+                        .name = name_tv,
+                        .vmux = 3,
+                        .amux = TV,
+                        .tv   = 1,
                 },{
                         .name = name_comp1,
                         .vmux = 1,
@@ -4133,6 +4458,7 @@ struct saa7134_board saa7134_boards[] = {
                 /* Igor Kuznetsov <igk@igk.ru> */
                 /* Andrey Melnikoff <temnota@kmv.ru> */
                 /* Beholder Intl. Ltd. Dmitry Belimov <d.belimov@gmail.com> */
+                /* Alexey Osipov <lion-simba@pridelands.ru> */
                 .name           = "Beholder BeholdTV M6",
                 .audio_clock    = 0x00187de7,
                 .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
@@ -4207,10 +4533,10 @@ struct saa7134_board saa7134_boards[] = {
                 /* Igor Kuznetsov <igk@igk.ru> */
                 /* Andrey Melnikoff <temnota@kmv.ru> */
                 /* Beholder Intl. Ltd. Dmitry Belimov <d.belimov@gmail.com> */
+                /* Alexey Osipov <lion-simba@pridelands.ru> */
                 .name           = "Beholder BeholdTV M6 Extra",
                 .audio_clock    = 0x00187de7,
-                /* FIXME: Must be PHILIPS_FM1216ME_MK5*/
-                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3, /* FIXME to MK5 */
                 .radio_type     = UNSET,
                 .tuner_addr     = ADDR_UNSET,
                 .radio_addr     = ADDR_UNSET,
@@ -4465,7 +4791,6 @@ struct saa7134_board saa7134_boards[] = {
                 .radio_type     = UNSET,
                 .tuner_addr     = ADDR_UNSET,
                 .radio_addr     = ADDR_UNSET,
-                .mpeg           = SAA7134_MPEG_DVB,
                 .inputs = {{
                         .name   = name_tv,
                         .vmux   = 3,
@@ -4753,6 +5078,44 @@ struct saa7134_board saa7134_boards[] = {
                         .gpio = 0x01,
                 },
         },
+        [SAA7134_BOARD_AVERMEDIA_STUDIO_507UA] = {
+                /* Andy Shevchenko <andy@smile.org.ua> */
+                .name           = "Avermedia AVerTV Studio 507UA",
+                .audio_clock    = 0x00187de7,
+                .tuner_type     = TUNER_PHILIPS_FM1216ME_MK3, /* Should be MK5 */
+                .radio_type     = UNSET,
+                .tuner_addr     = ADDR_UNSET,
+                .radio_addr     = ADDR_UNSET,
+                .tda9887_conf   = TDA9887_PRESENT,
+                .gpiomask       = 0x03,
+                .inputs         = { {
+                        .name = name_tv,
+                        .vmux = 1,
+                        .amux = TV,
+                        .tv   = 1,
+                        .gpio = 0x00,
+                }, {
+                        .name = name_comp1,
+                        .vmux = 3,
+                        .amux = LINE1,
+                        .gpio = 0x00,
+                }, {
+                        .name = name_svideo,
+                        .vmux = 8,
+                        .amux = LINE1,
+                        .gpio = 0x00,
+                } },
+                .radio = {
+                        .name = name_radio,
+                        .amux = LINE2,
+                        .gpio = 0x01,
+                },
+                .mute  = {
+                        .name = name_mute,
+                        .amux = LINE1,
+                        .gpio = 0x00,
+                },
+        },
 };
 
 const unsigned int saa7134_bcount = ARRAY_SIZE(saa7134_boards);
@@ -5027,6 +5390,13 @@ struct pci_device_id saa7134_pci_tbl[] = {
                 .subdevice    = 0xd6ee,
                 .driver_data  = SAA7134_BOARD_AVERMEDIA_CARDBUS,
         },{
+                /* AVerMedia CardBus */
+                .vendor       = PCI_VENDOR_ID_PHILIPS,
+                .device       = PCI_DEVICE_ID_PHILIPS_SAA7134,
+                .subvendor    = 0x1461, /* Avermedia Technologies Inc */
+                .subdevice    = 0xb7e9,
+                .driver_data  = SAA7134_BOARD_AVERMEDIA_CARDBUS_501,
+        }, {
                 /* TransGear 3000TV */
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7130,
@@ -5441,6 +5811,12 @@ struct pci_device_id saa7134_pci_tbl[] = {
                 .driver_data  = SAA7134_BOARD_AVERMEDIA_STUDIO_507,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
+                .device       = PCI_DEVICE_ID_PHILIPS_SAA7134,
+                .subvendor    = 0x1461, /* Avermedia Technologies Inc */
+                .subdevice    = 0xa11b,
+                .driver_data  = SAA7134_BOARD_AVERMEDIA_STUDIO_507UA,
+        }, {
+                .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7133,
                 .subvendor    = 0x1043,
                 .subdevice    = 0x4876,
@@ -5647,14 +6023,8 @@ struct pci_device_id saa7134_pci_tbl[] = {
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7130,
                 .subvendor    = 0x0000,
-                .subdevice    = 0x5051,
-                .driver_data  = SAA7134_BOARD_BEHOLD_505FM,
-        },{
-                .vendor       = PCI_VENDOR_ID_PHILIPS,
-                .device       = PCI_DEVICE_ID_PHILIPS_SAA7130,
-                .subvendor    = 0x0000,
                 .subdevice    = 0x505B,
-                .driver_data  = SAA7134_BOARD_BEHOLD_505FM,
+                .driver_data  = SAA7134_BOARD_BEHOLD_505RDS,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7130,
@@ -5666,13 +6036,13 @@ struct pci_device_id saa7134_pci_tbl[] = {
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7133,
                 .subvendor    = 0x0000,
                 .subdevice    = 0x5071,
-                .driver_data  = SAA7134_BOARD_BEHOLD_507_9FM,
+                .driver_data  = SAA7134_BOARD_BEHOLD_507RDS_MK3,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7133,
                 .subvendor    = 0x0000,
                 .subdevice    = 0x507B,
-                .driver_data  = SAA7134_BOARD_BEHOLD_507_9FM,
+                .driver_data  = SAA7134_BOARD_BEHOLD_507RDS_MK5,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7134,
@@ -5696,49 +6066,49 @@ struct pci_device_id saa7134_pci_tbl[] = {
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7134,
                 .subvendor    = 0x5ace,
                 .subdevice    = 0x6070,
-                .driver_data  = SAA7134_BOARD_BEHOLD_607_9FM,
+                .driver_data  = SAA7134_BOARD_BEHOLD_607FM_MK3,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7134,
                 .subvendor    = 0x5ace,
                 .subdevice    = 0x6071,
-                .driver_data  = SAA7134_BOARD_BEHOLD_607_9FM,
+                .driver_data  = SAA7134_BOARD_BEHOLD_607FM_MK5,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7134,
                 .subvendor    = 0x5ace,
                 .subdevice    = 0x6072,
-                .driver_data  = SAA7134_BOARD_BEHOLD_607_9FM,
+                .driver_data  = SAA7134_BOARD_BEHOLD_607RDS_MK3,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7134,
                 .subvendor    = 0x5ace,
                 .subdevice    = 0x6073,
-                .driver_data  = SAA7134_BOARD_BEHOLD_607_9FM,
+                .driver_data  = SAA7134_BOARD_BEHOLD_607RDS_MK5,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7133,
                 .subvendor    = 0x5ace,
                 .subdevice    = 0x6090,
-                .driver_data  = SAA7134_BOARD_BEHOLD_607_9FM,
+                .driver_data  = SAA7134_BOARD_BEHOLD_609FM_MK3,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7133,
                 .subvendor    = 0x5ace,
                 .subdevice    = 0x6091,
-                .driver_data  = SAA7134_BOARD_BEHOLD_607_9FM,
+                .driver_data  = SAA7134_BOARD_BEHOLD_609FM_MK5,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7133,
                 .subvendor    = 0x5ace,
                 .subdevice    = 0x6092,
-                .driver_data  = SAA7134_BOARD_BEHOLD_607_9FM,
+                .driver_data  = SAA7134_BOARD_BEHOLD_609RDS_MK3,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7133,
                 .subvendor    = 0x5ace,
                 .subdevice    = 0x6093,
-                .driver_data  = SAA7134_BOARD_BEHOLD_607_9FM,
+                .driver_data  = SAA7134_BOARD_BEHOLD_609RDS_MK5,
         },{
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7133,
@@ -5832,6 +6202,12 @@ struct pci_device_id saa7134_pci_tbl[] = {
         }, {
                 .vendor       = PCI_VENDOR_ID_PHILIPS,
                 .device       = PCI_DEVICE_ID_PHILIPS_SAA7133,
+                .subvendor    = 0x1461, /* Avermedia Technologies Inc */
+                .subdevice    = 0xf736,
+                .driver_data  = SAA7134_BOARD_AVERMEDIA_M103,
+        }, {
+                .vendor       = PCI_VENDOR_ID_PHILIPS,
+                .device       = PCI_DEVICE_ID_PHILIPS_SAA7133,
                 .subvendor    = 0x1043,
                 .subdevice    = 0x4878, /* REV:1.02G */
                 .driver_data  = SAA7134_BOARD_ASUSTeK_TIGER_3IN1,
@@ -6114,7 +6490,6 @@ int saa7134_board_init1(struct saa7134_dev *dev)
         case SAA7134_BOARD_VIDEOMATE_DVBT_300:
         case SAA7134_BOARD_VIDEOMATE_DVBT_200:
         case SAA7134_BOARD_VIDEOMATE_DVBT_200A:
-        case SAA7134_BOARD_VIDEOMATE_T750:
         case SAA7134_BOARD_MANLI_MTV001:
         case SAA7134_BOARD_MANLI_MTV002:
         case SAA7134_BOARD_BEHOLD_409FM:
@@ -6142,7 +6517,10 @@ int saa7134_board_init1(struct saa7134_dev *dev)
         case SAA7134_BOARD_BEHOLD_407FM:
         case SAA7134_BOARD_BEHOLD_409:
         case SAA7134_BOARD_BEHOLD_505FM:
+        case SAA7134_BOARD_BEHOLD_505RDS:
         case SAA7134_BOARD_BEHOLD_507_9FM:
+        case SAA7134_BOARD_BEHOLD_507RDS_MK3:
+        case SAA7134_BOARD_BEHOLD_507RDS_MK5:
         case SAA7134_BOARD_GENIUS_TVGO_A11MCE:
         case SAA7134_BOARD_REAL_ANGEL_220:
         case SAA7134_BOARD_KWORLD_PLUS_TV_ANALOG:
@@ -6196,6 +6574,16 @@ int saa7134_board_init1(struct saa7134_dev *dev)
                 saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0xffffffff, 0xffffffff);
                 msleep(10);
                 break;
+        case SAA7134_BOARD_AVERMEDIA_CARDBUS_501:
+                /* power-down tuner chip */
+                saa_andorl(SAA7134_GPIO_GPMODE0 >> 2,   0x08400000, 0x08400000);
+                saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x08400000, 0);
+                msleep(10);
+                saa_andorl(SAA7134_GPIO_GPMODE0 >> 2,   0x08400000, 0x08400000);
+                saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x08400000, 0x08400000);
+                msleep(10);
+                dev->has_remote = SAA7134_REMOTE_I2C;
+                break;
         case SAA7134_BOARD_AVERMEDIA_CARDBUS_506:
                 saa7134_set_gpio(dev, 23, 0);
                 msleep(10);
@@ -6253,7 +6641,14 @@ int saa7134_board_init1(struct saa7134_dev *dev)
         case SAA7134_BOARD_UPMOST_PURPLE_TV:
         case SAA7134_BOARD_MSI_TVATANYWHERE_PLUS:
         case SAA7134_BOARD_HAUPPAUGE_HVR1110:
-        case SAA7134_BOARD_BEHOLD_607_9FM:
+        case SAA7134_BOARD_BEHOLD_607FM_MK3:
+        case SAA7134_BOARD_BEHOLD_607FM_MK5:
+        case SAA7134_BOARD_BEHOLD_609FM_MK3:
+        case SAA7134_BOARD_BEHOLD_609FM_MK5:
+        case SAA7134_BOARD_BEHOLD_607RDS_MK3:
+        case SAA7134_BOARD_BEHOLD_607RDS_MK5:
+        case SAA7134_BOARD_BEHOLD_609RDS_MK3:
+        case SAA7134_BOARD_BEHOLD_609RDS_MK5:
         case SAA7134_BOARD_BEHOLD_M6:
         case SAA7134_BOARD_BEHOLD_M63:
         case SAA7134_BOARD_BEHOLD_M6_EXTRA:
@@ -6635,6 +7030,7 @@ int saa7134_board_init2(struct saa7134_dev *dev)
 
         switch (dev->board) {
         case SAA7134_BOARD_BEHOLD_COLUMBUS_TVFM:
+        case SAA7134_BOARD_AVERMEDIA_CARDBUS_501:
         {
                 struct v4l2_priv_tun_config tea5767_cfg;
                 struct tea5767_ctrl ctl;
diff --git a/drivers/media/video/saa7134/saa7134-core.c b/drivers/media/video/saa7134/saa7134-core.c
index 2def6fec814b..94a023a14bbc 100644
--- a/drivers/media/video/saa7134/saa7134-core.c
+++ b/drivers/media/video/saa7134/saa7134-core.c
@@ -331,6 +331,10 @@ void saa7134_buffer_next(struct saa7134_dev *dev,
                 dprintk("buffer_next %p\n",NULL);
                 saa7134_set_dmabits(dev);
                 del_timer(&q->timeout);
+
+                if (card_has_mpeg(dev))
+                        if (dev->ts_started)
+                                saa7134_ts_stop(dev);
         }
 }
 
@@ -416,6 +420,19 @@ int saa7134_set_dmabits(struct saa7134_dev *dev)
                 ctrl |= SAA7134_MAIN_CTRL_TE5;
                 irq  |= SAA7134_IRQ1_INTE_RA2_1 |
                         SAA7134_IRQ1_INTE_RA2_0;
+
+                /* dma: setup channel 5 (= TS) */
+
+                saa_writeb(SAA7134_TS_DMA0, (dev->ts.nr_packets - 1) & 0xff);
+                saa_writeb(SAA7134_TS_DMA1,
+                        ((dev->ts.nr_packets - 1) >> 8) & 0xff);
+                /* TSNOPIT=0, TSCOLAP=0 */
+                saa_writeb(SAA7134_TS_DMA2,
+                        (((dev->ts.nr_packets - 1) >> 16) & 0x3f) | 0x00);
+                saa_writel(SAA7134_RS_PITCH(5), TS_PACKET_SIZE);
+                saa_writel(SAA7134_RS_CONTROL(5), SAA7134_RS_CONTROL_BURST_16 |
+                                                  SAA7134_RS_CONTROL_ME |
+                                                  (dev->ts.pt_ts.dma >> 12));
         }
 
         /* set task conditions + field handling */
@@ -775,7 +792,6 @@ static struct video_device *vdev_init(struct saa7134_dev *dev,
         if (NULL == vfd)
                 return NULL;
         *vfd = *template;
-        vfd->minor   = -1;
         vfd->v4l2_dev  = &dev->v4l2_dev;
         vfd->release = video_device_release;
         vfd->debug   = video_debug;
diff --git a/drivers/media/video/saa7134/saa7134-dvb.c b/drivers/media/video/saa7134/saa7134-dvb.c
index 4eff1ca8593c..31930f26ffc7 100644
--- a/drivers/media/video/saa7134/saa7134-dvb.c
+++ b/drivers/media/video/saa7134/saa7134-dvb.c
@@ -48,6 +48,7 @@
 #include "isl6405.h"
 #include "lnbp21.h"
 #include "tuner-simple.h"
+#include "tda10048.h"
 #include "tda18271.h"
 #include "lgdt3305.h"
 #include "tda8290.h"
@@ -978,6 +979,18 @@ static struct lgdt3305_config hcw_lgdt3305_config = {
         .vsb_if_khz         = 3250,
 };
 
+static struct tda10048_config hcw_tda10048_config = {
+        .demod_address    = 0x10 >> 1,
+        .output_mode      = TDA10048_SERIAL_OUTPUT,
+        .fwbulkwritelen   = TDA10048_BULKWRITE_200,
+        .inversion        = TDA10048_INVERSION_ON,
+        .dtv6_if_freq_khz = TDA10048_IF_3300,
+        .dtv7_if_freq_khz = TDA10048_IF_3500,
+        .dtv8_if_freq_khz = TDA10048_IF_4000,
+        .clk_freq_khz     = TDA10048_CLK_16000,
+        .disable_gate_access = 1,
+};
+
 static struct tda18271_std_map hauppauge_tda18271_std_map = {
         .atsc_6   = { .if_freq = 3250, .agc_mode = 3, .std = 4,
                       .if_lvl = 1, .rfagc_top = 0x58, },
@@ -1106,6 +1119,19 @@ static int dvb_init(struct saa7134_dev *dev)
                                          &tda827x_cfg_2) < 0)
                         goto dettach_frontend;
                 break;
+        case SAA7134_BOARD_HAUPPAUGE_HVR1110R3:
+                fe0->dvb.frontend = dvb_attach(tda10048_attach,
+                                               &hcw_tda10048_config,
+                                               &dev->i2c_adap);
+                if (fe0->dvb.frontend != NULL) {
+                        dvb_attach(tda829x_attach, fe0->dvb.frontend,
+                                   &dev->i2c_adap, 0x4b,
+                                   &tda829x_no_probe);
+                        dvb_attach(tda18271_attach, fe0->dvb.frontend,
+                                   0x60, &dev->i2c_adap,
+                                   &hcw_tda18271_config);
+                }
+                break;
         case SAA7134_BOARD_PHILIPS_TIGER:
                 if (configure_tda827x_fe(dev, &philips_tiger_config,
                                          &tda827x_cfg_0) < 0)
diff --git a/drivers/media/video/saa7134/saa7134-empress.c b/drivers/media/video/saa7134/saa7134-empress.c
index 9db3472667e5..add1757f8930 100644
--- a/drivers/media/video/saa7134/saa7134-empress.c
+++ b/drivers/media/video/saa7134/saa7134-empress.c
@@ -255,6 +255,16 @@ static int empress_s_fmt_vid_cap(struct file *file, void *priv,
         return 0;
 }
 
+static int empress_try_fmt_vid_cap(struct file *file, void *priv,
+                                struct v4l2_format *f)
+{
+        struct saa7134_dev *dev = file->private_data;
+
+        f->fmt.pix.pixelformat  = V4L2_PIX_FMT_MPEG;
+        f->fmt.pix.sizeimage    = TS_PACKET_SIZE * dev->ts.nr_packets;
+
+        return 0;
+}
 
 static int empress_reqbufs(struct file *file, void *priv,
                                         struct v4l2_requestbuffers *p)
@@ -450,6 +460,7 @@ static const struct v4l2_file_operations ts_fops =
 static const struct v4l2_ioctl_ops ts_ioctl_ops = {
         .vidioc_querycap                = empress_querycap,
         .vidioc_enum_fmt_vid_cap        = empress_enum_fmt_vid_cap,
+        .vidioc_try_fmt_vid_cap         = empress_try_fmt_vid_cap,
         .vidioc_s_fmt_vid_cap           = empress_s_fmt_vid_cap,
         .vidioc_g_fmt_vid_cap           = empress_g_fmt_vid_cap,
         .vidioc_reqbufs                 = empress_reqbufs,
@@ -491,11 +502,8 @@ static void empress_signal_update(struct work_struct *work)
 
         if (dev->nosignal) {
                 dprintk("no video signal\n");
-                ts_reset_encoder(dev);
         } else {
                 dprintk("video signal acquired\n");
-                if (atomic_read(&dev->empress_users))
-                        ts_init_encoder(dev);
         }
 }
 
diff --git a/drivers/media/video/saa7134/saa7134-i2c.c b/drivers/media/video/saa7134/saa7134-i2c.c
index f3e285aa2fb4..8096dace5f6c 100644
--- a/drivers/media/video/saa7134/saa7134-i2c.c
+++ b/drivers/media/video/saa7134/saa7134-i2c.c
@@ -259,7 +259,7 @@ static int saa7134_i2c_xfer(struct i2c_adapter *i2c_adap,
                                 /* workaround for a saa7134 i2c bug
                                  * needed to talk to the mt352 demux
                                  * thanks to pinnacle for the hint */
-                                int quirk = 0xfd;
+                                int quirk = 0xfe;
                                 d1printk(" [%02x quirk]",quirk);
                                 i2c_send_byte(dev,START,quirk);
                                 i2c_recv_byte(dev);
@@ -321,33 +321,6 @@ static u32 functionality(struct i2c_adapter *adap)
         return I2C_FUNC_SMBUS_EMUL;
 }
 
-static int attach_inform(struct i2c_client *client)
-{
-        struct saa7134_dev *dev = client->adapter->algo_data;
-
-        d1printk( "%s i2c attach [addr=0x%x,client=%s]\n",
-                client->driver->driver.name, client->addr, client->name);
-
-        /* Am I an i2c remote control? */
-
-        switch (client->addr) {
-                case 0x7a:
-                case 0x47:
-                case 0x71:
-                case 0x2d:
-                case 0x30:
-                {
-                        struct IR_i2c *ir = i2c_get_clientdata(client);
-                        d1printk("%s i2c IR detected (%s).\n",
-                                 client->driver->driver.name, ir->phys);
-                        saa7134_set_i2c_ir(dev,ir);
-                        break;
-                }
-        }
-
-        return 0;
-}
-
 static struct i2c_algorithm saa7134_algo = {
         .master_xfer   = saa7134_i2c_xfer,
         .functionality = functionality,
@@ -358,7 +331,6 @@ static struct i2c_adapter saa7134_adap_template = {
         .name          = "saa7134",
         .id            = I2C_HW_SAA7134,
         .algo          = &saa7134_algo,
-        .client_register = attach_inform,
 };
 
 static struct i2c_client saa7134_client_template = {
@@ -433,6 +405,9 @@ int saa7134_i2c_register(struct saa7134_dev *dev)
         saa7134_i2c_eeprom(dev,dev->eedata,sizeof(dev->eedata));
         if (i2c_scan)
                 do_i2c_scan(dev->name,&dev->i2c_client);
+
+        /* Instantiate the IR receiver device, if present */
+        saa7134_probe_i2c_ir(dev);
         return 0;
 }
 
diff --git a/drivers/media/video/saa7134/saa7134-input.c b/drivers/media/video/saa7134/saa7134-input.c
index 8a106d36e723..6e219c2db841 100644
--- a/drivers/media/video/saa7134/saa7134-input.c
+++ b/drivers/media/video/saa7134/saa7134-input.c
@@ -60,7 +60,7 @@ MODULE_PARM_DESC(disable_other_ir, "disable full codes of "
 #define dprintk(fmt, arg...)    if (ir_debug) \
         printk(KERN_DEBUG "%s/ir: " fmt, dev->name , ## arg)
 #define i2cdprintk(fmt, arg...)    if (ir_debug) \
-        printk(KERN_DEBUG "%s/ir: " fmt, ir->c.name , ## arg)
+        printk(KERN_DEBUG "%s/ir: " fmt, ir->name , ## arg)
 
 /* Helper functions for RC5 and NEC decoding at GPIO16 or GPIO18 */
 static int saa7134_rc5_irq(struct saa7134_dev *dev);
@@ -134,10 +134,10 @@ static int get_key_msi_tvanywhere_plus(struct IR_i2c *ir, u32 *ir_key,
         int gpio;
 
         /* <dev> is needed to access GPIO. Used by the saa_readl macro. */
-        struct saa7134_dev *dev = ir->c.adapter->algo_data;
+        struct saa7134_dev *dev = ir->c->adapter->algo_data;
         if (dev == NULL) {
                 dprintk("get_key_msi_tvanywhere_plus: "
-                        "gir->c.adapter->algo_data is NULL!\n");
+                        "gir->c->adapter->algo_data is NULL!\n");
                 return -EIO;
         }
 
@@ -156,7 +156,7 @@ static int get_key_msi_tvanywhere_plus(struct IR_i2c *ir, u32 *ir_key,
 
         /* GPIO says there is a button press. Get it. */
 
-        if (1 != i2c_master_recv(&ir->c, &b, 1)) {
+        if (1 != i2c_master_recv(ir->c, &b, 1)) {
                 i2cdprintk("read error\n");
                 return -EIO;
         }
@@ -179,7 +179,7 @@ static int get_key_purpletv(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw)
         unsigned char b;
 
         /* poll IR chip */
-        if (1 != i2c_master_recv(&ir->c,&b,1)) {
+        if (1 != i2c_master_recv(ir->c, &b, 1)) {
                 i2cdprintk("read error\n");
                 return -EIO;
         }
@@ -202,7 +202,7 @@ static int get_key_hvr1110(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw)
         unsigned char buf[5], cod4, code3, code4;
 
         /* poll IR chip */
-        if (5 != i2c_master_recv(&ir->c,buf,5))
+        if (5 != i2c_master_recv(ir->c, buf, 5))
                 return -EIO;
 
         cod4    = buf[4];
@@ -224,7 +224,7 @@ static int get_key_beholdm6xx(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw)
         unsigned char data[12];
         u32 gpio;
 
-        struct saa7134_dev *dev = ir->c.adapter->algo_data;
+        struct saa7134_dev *dev = ir->c->adapter->algo_data;
 
         /* rising SAA7134_GPIO_GPRESCAN reads the status */
         saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
@@ -235,9 +235,9 @@ static int get_key_beholdm6xx(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw)
         if (0x400000 & ~gpio)
                 return 0; /* No button press */
 
-        ir->c.addr = 0x5a >> 1;
+        ir->c->addr = 0x5a >> 1;
 
-        if (12 != i2c_master_recv(&ir->c, data, 12)) {
+        if (12 != i2c_master_recv(ir->c, data, 12)) {
                 i2cdprintk("read error\n");
                 return -EIO;
         }
@@ -267,7 +267,7 @@ static int get_key_pinnacle(struct IR_i2c *ir, u32 *ir_key, u32 *ir_raw,
         unsigned int start = 0,parity = 0,code = 0;
 
         /* poll IR chip */
-        if (4 != i2c_master_recv(&ir->c, b, 4)) {
+        if (4 != i2c_master_recv(ir->c, b, 4)) {
                 i2cdprintk("read error\n");
                 return -EIO;
         }
@@ -447,6 +447,7 @@ int saa7134_input_init1(struct saa7134_dev *dev)
         case SAA7134_BOARD_AVERMEDIA_STUDIO_305:
         case SAA7134_BOARD_AVERMEDIA_STUDIO_307:
         case SAA7134_BOARD_AVERMEDIA_STUDIO_507:
+        case SAA7134_BOARD_AVERMEDIA_STUDIO_507UA:
         case SAA7134_BOARD_AVERMEDIA_GO_007_FM:
         case SAA7134_BOARD_AVERMEDIA_M102:
         case SAA7134_BOARD_AVERMEDIA_GO_007_FM_PLUS:
@@ -506,7 +507,10 @@ int saa7134_input_init1(struct saa7134_dev *dev)
         case SAA7134_BOARD_BEHOLD_407FM:
         case SAA7134_BOARD_BEHOLD_409:
         case SAA7134_BOARD_BEHOLD_505FM:
+        case SAA7134_BOARD_BEHOLD_505RDS:
         case SAA7134_BOARD_BEHOLD_507_9FM:
+        case SAA7134_BOARD_BEHOLD_507RDS_MK3:
+        case SAA7134_BOARD_BEHOLD_507RDS_MK5:
                 ir_codes     = ir_codes_manli;
                 mask_keycode = 0x003f00;
                 mask_keyup   = 0x004000;
@@ -678,55 +682,101 @@ void saa7134_input_fini(struct saa7134_dev *dev)
         dev->remote = NULL;
 }
 
-void saa7134_set_i2c_ir(struct saa7134_dev *dev, struct IR_i2c *ir)
+void saa7134_probe_i2c_ir(struct saa7134_dev *dev)
 {
+        struct i2c_board_info info;
+        struct IR_i2c_init_data init_data;
+        const unsigned short addr_list[] = {
+                0x7a, 0x47, 0x71, 0x2d,
+                I2C_CLIENT_END
+        };
+
+        struct i2c_msg msg_msi = {
+                .addr = 0x50,
+                .flags = I2C_M_RD,
+                .len = 0,
+                .buf = NULL,
+        };
+
+        int rc;
+
         if (disable_ir) {
-                dprintk("Found supported i2c remote, but IR has been disabled\n");
-                ir->get_key=NULL;
+                dprintk("IR has been disabled, not probing for i2c remote\n");
                 return;
         }
 
+        memset(&info, 0, sizeof(struct i2c_board_info));
+        memset(&init_data, 0, sizeof(struct IR_i2c_init_data));
+        strlcpy(info.type, "ir_video", I2C_NAME_SIZE);
+
         switch (dev->board) {
         case SAA7134_BOARD_PINNACLE_PCTV_110i:
         case SAA7134_BOARD_PINNACLE_PCTV_310i:
-                snprintf(ir->c.name, sizeof(ir->c.name), "Pinnacle PCTV");
+                init_data.name = "Pinnacle PCTV";
                 if (pinnacle_remote == 0) {
-                        ir->get_key   = get_key_pinnacle_color;
-                        ir->ir_codes = ir_codes_pinnacle_color;
+                        init_data.get_key = get_key_pinnacle_color;
+                        init_data.ir_codes = ir_codes_pinnacle_color;
                 } else {
-                        ir->get_key   = get_key_pinnacle_grey;
-                        ir->ir_codes = ir_codes_pinnacle_grey;
+                        init_data.get_key = get_key_pinnacle_grey;
+                        init_data.ir_codes = ir_codes_pinnacle_grey;
                 }
                 break;
         case SAA7134_BOARD_UPMOST_PURPLE_TV:
-                snprintf(ir->c.name, sizeof(ir->c.name), "Purple TV");
-                ir->get_key   = get_key_purpletv;
-                ir->ir_codes  = ir_codes_purpletv;
+                init_data.name = "Purple TV";
+                init_data.get_key = get_key_purpletv;
+                init_data.ir_codes = ir_codes_purpletv;
                 break;
         case SAA7134_BOARD_MSI_TVATANYWHERE_PLUS:
-                snprintf(ir->c.name, sizeof(ir->c.name), "MSI TV@nywhere Plus");
-                ir->get_key  = get_key_msi_tvanywhere_plus;
-                ir->ir_codes = ir_codes_msi_tvanywhere_plus;
+                init_data.name = "MSI TV@nywhere Plus";
+                init_data.get_key = get_key_msi_tvanywhere_plus;
+                init_data.ir_codes = ir_codes_msi_tvanywhere_plus;
+                info.addr = 0x30;
+                /* MSI TV@nywhere Plus controller doesn't seem to
+                   respond to probes unless we read something from
+                   an existing device. Weird...
+                   REVISIT: might no longer be needed */
+                rc = i2c_transfer(&dev->i2c_adap, &msg_msi, 1);
+                dprintk(KERN_DEBUG "probe 0x%02x @ %s: %s\n",
+                        msg_msi.addr, dev->i2c_adap.name,
+                        (1 == rc) ? "yes" : "no");
                 break;
         case SAA7134_BOARD_HAUPPAUGE_HVR1110:
-                snprintf(ir->c.name, sizeof(ir->c.name), "HVR 1110");
-                ir->get_key   = get_key_hvr1110;
-                ir->ir_codes  = ir_codes_hauppauge_new;
-                break;
-        case SAA7134_BOARD_BEHOLD_607_9FM:
+                init_data.name = "HVR 1110";
+                init_data.get_key = get_key_hvr1110;
+                init_data.ir_codes = ir_codes_hauppauge_new;
+                break;
+        case SAA7134_BOARD_BEHOLD_607FM_MK3:
+        case SAA7134_BOARD_BEHOLD_607FM_MK5:
+        case SAA7134_BOARD_BEHOLD_609FM_MK3:
+        case SAA7134_BOARD_BEHOLD_609FM_MK5:
+        case SAA7134_BOARD_BEHOLD_607RDS_MK3:
+        case SAA7134_BOARD_BEHOLD_607RDS_MK5:
+        case SAA7134_BOARD_BEHOLD_609RDS_MK3:
+        case SAA7134_BOARD_BEHOLD_609RDS_MK5:
         case SAA7134_BOARD_BEHOLD_M6:
         case SAA7134_BOARD_BEHOLD_M63:
         case SAA7134_BOARD_BEHOLD_M6_EXTRA:
         case SAA7134_BOARD_BEHOLD_H6:
-                snprintf(ir->c.name, sizeof(ir->c.name), "BeholdTV");
-                ir->get_key   = get_key_beholdm6xx;
-                ir->ir_codes  = ir_codes_behold;
+                init_data.name = "BeholdTV";
+                init_data.get_key = get_key_beholdm6xx;
+                init_data.ir_codes = ir_codes_behold;
                 break;
-        default:
-                dprintk("Shouldn't get here: Unknown board %x for I2C IR?\n",dev->board);
+        case SAA7134_BOARD_AVERMEDIA_CARDBUS_501:
+        case SAA7134_BOARD_AVERMEDIA_CARDBUS_506:
+                info.addr = 0x40;
                 break;
         }
 
+        if (init_data.name)
+                info.platform_data = &init_data;
+        /* No need to probe if address is known */
+        if (info.addr) {
+                i2c_new_device(&dev->i2c_adap, &info);
+                return;
+        }
+
+        /* Address not known, fallback to probing */
+        i2c_new_probed_device(&dev->i2c_adap, &info, addr_list);
 }
 
 static int saa7134_rc5_irq(struct saa7134_dev *dev)
diff --git a/drivers/media/video/saa7134/saa7134-ts.c b/drivers/media/video/saa7134/saa7134-ts.c
index cc8b923afbc0..3fa652279ac0 100644
--- a/drivers/media/video/saa7134/saa7134-ts.c
+++ b/drivers/media/video/saa7134/saa7134-ts.c
@@ -65,35 +65,10 @@ static int buffer_activate(struct saa7134_dev *dev,
         /* start DMA */
         saa7134_set_dmabits(dev);
 
-        mod_timer(&dev->ts_q.timeout, jiffies+BUFFER_TIMEOUT);
-
-        if (dev->ts_state == SAA7134_TS_BUFF_DONE) {
-                /* Clear TS cache */
-                dev->buff_cnt = 0;
-                saa_writeb(SAA7134_TS_SERIAL1, 0x00);
-                saa_writeb(SAA7134_TS_SERIAL1, 0x03);
-                saa_writeb(SAA7134_TS_SERIAL1, 0x00);
-                saa_writeb(SAA7134_TS_SERIAL1, 0x01);
-
-                /* TS clock non-inverted */
-                saa_writeb(SAA7134_TS_SERIAL1, 0x00);
-
-                /* Start TS stream */
-                switch (saa7134_boards[dev->board].ts_type) {
-                case SAA7134_MPEG_TS_PARALLEL:
-                        saa_writeb(SAA7134_TS_SERIAL0, 0x40);
-                        saa_writeb(SAA7134_TS_PARALLEL, 0xec);
-                        break;
-                case SAA7134_MPEG_TS_SERIAL:
-                        saa_writeb(SAA7134_TS_SERIAL0, 0xd8);
-                        saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
-                        saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 0xbc);
-                        saa_writeb(SAA7134_TS_SERIAL1, 0x02);
-                        break;
-                }
+        mod_timer(&dev->ts_q.timeout, jiffies+TS_BUFFER_TIMEOUT);
 
-                dev->ts_state = SAA7134_TS_STARTED;
-        }
+        if (!dev->ts_started)
+                saa7134_ts_start(dev);
 
         return 0;
 }
@@ -104,7 +79,6 @@ static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,
         struct saa7134_dev *dev = q->priv_data;
         struct saa7134_buf *buf = container_of(vb,struct saa7134_buf,vb);
         unsigned int lines, llength, size;
-        u32 control;
         int err;
 
         dprintk("buffer_prepare [%p,%s]\n",buf,v4l2_field_names[field]);
@@ -121,8 +95,11 @@ static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,
         }
 
         if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
+
                 struct videobuf_dmabuf *dma=videobuf_to_dma(&buf->vb);
 
+                dprintk("buffer_prepare: needs_init\n");
+
                 buf->vb.width  = llength;
                 buf->vb.height = lines;
                 buf->vb.size   = size;
@@ -139,23 +116,6 @@ static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,
                         goto oops;
         }
 
-        dev->buff_cnt++;
-
-        if (dev->buff_cnt == dev->ts.nr_bufs) {
-                dev->ts_state = SAA7134_TS_BUFF_DONE;
-                /* dma: setup channel 5 (= TS) */
-                control = SAA7134_RS_CONTROL_BURST_16 |
-                        SAA7134_RS_CONTROL_ME |
-                        (buf->pt->dma >> 12);
-
-                saa_writeb(SAA7134_TS_DMA0, (lines - 1) & 0xff);
-                saa_writeb(SAA7134_TS_DMA1, ((lines - 1) >> 8) & 0xff);
-                /* TSNOPIT=0, TSCOLAP=0 */
-                saa_writeb(SAA7134_TS_DMA2, (((lines - 1) >> 16) & 0x3f) | 0x00);
-                saa_writel(SAA7134_RS_PITCH(5), TS_PACKET_SIZE);
-                saa_writel(SAA7134_RS_CONTROL(5), control);
-        }
-
         buf->vb.state = VIDEOBUF_PREPARED;
         buf->activate = buffer_activate;
         buf->vb.field = field;
@@ -175,8 +135,7 @@ buffer_setup(struct videobuf_queue *q, unsigned int *count, unsigned int *size)
         if (0 == *count)
                 *count = dev->ts.nr_bufs;
         *count = saa7134_buffer_count(*size,*count);
-        dev->buff_cnt = 0;
-        dev->ts_state = SAA7134_TS_STOPPED;
+
         return 0;
 }
 
@@ -193,11 +152,9 @@ static void buffer_release(struct videobuf_queue *q, struct videobuf_buffer *vb)
         struct saa7134_buf *buf = container_of(vb,struct saa7134_buf,vb);
         struct saa7134_dev *dev = q->priv_data;
 
-        if (dev->ts_state == SAA7134_TS_STARTED) {
-                /* Stop TS transport */
-                saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
-                dev->ts_state = SAA7134_TS_STOPPED;
-        }
+        if (dev->ts_started)
+                saa7134_ts_stop(dev);
+
         saa7134_dma_free(q,buf);
 }
 
@@ -214,7 +171,7 @@ EXPORT_SYMBOL_GPL(saa7134_ts_qops);
 
 static unsigned int tsbufs = 8;
 module_param(tsbufs, int, 0444);
-MODULE_PARM_DESC(tsbufs,"number of ts buffers, range 2-32");
+MODULE_PARM_DESC(tsbufs, "number of ts buffers for read/write IO, range 2-32");
 
 static unsigned int ts_nr_packets = 64;
 module_param(ts_nr_packets, int, 0444);
@@ -256,6 +213,7 @@ int saa7134_ts_init1(struct saa7134_dev *dev)
         dev->ts_q.timeout.data     = (unsigned long)(&dev->ts_q);
         dev->ts_q.dev              = dev;
         dev->ts_q.need_two         = 1;
+        dev->ts_started            = 0;
         saa7134_pgtable_alloc(dev->pci,&dev->ts.pt_ts);
 
         /* init TS hw */
@@ -264,13 +222,67 @@ int saa7134_ts_init1(struct saa7134_dev *dev)
         return 0;
 }
 
+/* Function for stop TS */
+int saa7134_ts_stop(struct saa7134_dev *dev)
+{
+        dprintk("TS stop\n");
+
+        BUG_ON(!dev->ts_started);
+
+        /* Stop TS stream */
+        switch (saa7134_boards[dev->board].ts_type) {
+        case SAA7134_MPEG_TS_PARALLEL:
+                saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
+                dev->ts_started = 0;
+                break;
+        case SAA7134_MPEG_TS_SERIAL:
+                saa_writeb(SAA7134_TS_SERIAL0, 0x40);
+                dev->ts_started = 0;
+                break;
+        }
+        return 0;
+}
+
+/* Function for start TS */
+int saa7134_ts_start(struct saa7134_dev *dev)
+{
+        dprintk("TS start\n");
+
+        BUG_ON(dev->ts_started);
+
+        saa_writeb(SAA7134_TS_SERIAL1, 0x00);
+        saa_writeb(SAA7134_TS_SERIAL1, 0x03);
+        saa_writeb(SAA7134_TS_SERIAL1, 0x00);
+        saa_writeb(SAA7134_TS_SERIAL1, 0x01);
+
+        /* TS clock non-inverted */
+        saa_writeb(SAA7134_TS_SERIAL1, 0x00);
+
+        /* Start TS stream */
+        switch (saa7134_boards[dev->board].ts_type) {
+        case SAA7134_MPEG_TS_PARALLEL:
+                saa_writeb(SAA7134_TS_SERIAL0, 0x40);
+                saa_writeb(SAA7134_TS_PARALLEL, 0xec);
+                break;
+        case SAA7134_MPEG_TS_SERIAL:
+                saa_writeb(SAA7134_TS_SERIAL0, 0xd8);
+                saa_writeb(SAA7134_TS_PARALLEL, 0x6c);
+                saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 0xbc);
+                saa_writeb(SAA7134_TS_SERIAL1, 0x02);
+                break;
+        }
+
+        dev->ts_started = 1;
+
+        return 0;
+}
+
 int saa7134_ts_fini(struct saa7134_dev *dev)
 {
         saa7134_pgtable_free(dev->pci,&dev->ts.pt_ts);
         return 0;
 }
 
-
 void saa7134_irq_ts_done(struct saa7134_dev *dev, unsigned long status)
 {
         enum v4l2_field field;
diff --git a/drivers/media/video/saa7134/saa7134-video.c b/drivers/media/video/saa7134/saa7134-video.c
index 493cad941460..e305c1674cee 100644
--- a/drivers/media/video/saa7134/saa7134-video.c
+++ b/drivers/media/video/saa7134/saa7134-video.c
@@ -1057,6 +1057,7 @@ static int buffer_prepare(struct videobuf_queue *q,
                 buf->vb.field  = field;
                 buf->fmt       = fh->fmt;
                 buf->pt        = &fh->pt_cap;
+                dev->video_q.curr = NULL;
 
                 err = videobuf_iolock(q,&buf->vb,&dev->ovbuf);
                 if (err)
@@ -1423,11 +1424,13 @@ video_poll(struct file *file, struct poll_table_struct *wait)
 {
         struct saa7134_fh *fh = file->private_data;
         struct videobuf_buffer *buf = NULL;
+        unsigned int rc = 0;
 
         if (V4L2_BUF_TYPE_VBI_CAPTURE == fh->type)
                 return videobuf_poll_stream(file, &fh->vbi, wait);
 
         if (res_check(fh,RESOURCE_VIDEO)) {
+                mutex_lock(&fh->cap.vb_lock);
                 if (!list_empty(&fh->cap.stream))
                         buf = list_entry(fh->cap.stream.next, struct videobuf_buffer, stream);
         } else {
@@ -1446,13 +1449,14 @@ video_poll(struct file *file, struct poll_table_struct *wait)
         }
 
         if (!buf)
-                return POLLERR;
+                goto err;
 
         poll_wait(file, &buf->done, wait);
         if (buf->state == VIDEOBUF_DONE ||
             buf->state == VIDEOBUF_ERROR)
-                return POLLIN|POLLRDNORM;
-        return 0;
+                rc = POLLIN|POLLRDNORM;
+        mutex_unlock(&fh->cap.vb_lock);
+        return rc;
 
 err:
         mutex_unlock(&fh->cap.vb_lock);
diff --git a/drivers/media/video/saa7134/saa7134.h b/drivers/media/video/saa7134/saa7134.h
index 0cbaf90d4874..82268848f26a 100644
--- a/drivers/media/video/saa7134/saa7134.h
+++ b/drivers/media/video/saa7134/saa7134.h
@@ -252,7 +252,7 @@ struct saa7134_format {
 #define SAA7134_BOARD_BEHOLD_505FM      126
 #define SAA7134_BOARD_BEHOLD_507_9FM    127
 #define SAA7134_BOARD_BEHOLD_COLUMBUS_TVFM 128
-#define SAA7134_BOARD_BEHOLD_607_9FM    129
+#define SAA7134_BOARD_BEHOLD_607FM_MK3  129
 #define SAA7134_BOARD_BEHOLD_M6         130
 #define SAA7134_BOARD_TWINHAN_DTV_DVB_3056 131
 #define SAA7134_BOARD_GENIUS_TVGO_A11MCE   132
@@ -280,6 +280,18 @@ struct saa7134_format {
 #define SAA7134_BOARD_AVERMEDIA_GO_007_FM_PLUS 154
 #define SAA7134_BOARD_HAUPPAUGE_HVR1120     155
 #define SAA7134_BOARD_HAUPPAUGE_HVR1110R3   156
+#define SAA7134_BOARD_AVERMEDIA_STUDIO_507UA 157
+#define SAA7134_BOARD_AVERMEDIA_CARDBUS_501 158
+#define SAA7134_BOARD_BEHOLD_505RDS         159
+#define SAA7134_BOARD_BEHOLD_507RDS_MK3     160
+#define SAA7134_BOARD_BEHOLD_507RDS_MK5     161
+#define SAA7134_BOARD_BEHOLD_607FM_MK5      162
+#define SAA7134_BOARD_BEHOLD_609FM_MK3      163
+#define SAA7134_BOARD_BEHOLD_609FM_MK5      164
+#define SAA7134_BOARD_BEHOLD_607RDS_MK3     165
+#define SAA7134_BOARD_BEHOLD_607RDS_MK5     166
+#define SAA7134_BOARD_BEHOLD_609RDS_MK3     167
+#define SAA7134_BOARD_BEHOLD_609RDS_MK5     168
 
 #define SAA7134_MAXBOARDS 32
 #define SAA7134_INPUT_MAX 8
@@ -364,6 +376,7 @@ struct saa7134_board {
 #define INTERLACE_OFF          2
 
 #define BUFFER_TIMEOUT     msecs_to_jiffies(500)  /* 0.5 seconds */
+#define TS_BUFFER_TIMEOUT  msecs_to_jiffies(1000)  /* 1 second */
 
 struct saa7134_dev;
 struct saa7134_dma;
@@ -480,12 +493,6 @@ struct saa7134_mpeg_ops {
         void                       (*signal_change)(struct saa7134_dev *dev);
 };
 
-enum saa7134_ts_status {
-        SAA7134_TS_STOPPED,
-        SAA7134_TS_BUFF_DONE,
-        SAA7134_TS_STARTED,
-};
-
 /* global device status */
 struct saa7134_dev {
         struct list_head           devlist;
@@ -580,8 +587,7 @@ struct saa7134_dev {
         /* SAA7134_MPEG_* */
         struct saa7134_ts          ts;
         struct saa7134_dmaqueue    ts_q;
-        enum saa7134_ts_status     ts_state;
-        unsigned int               buff_cnt;
+        int                        ts_started;
         struct saa7134_mpeg_ops    *mops;
 
         /* SAA7134_MPEG_EMPRESS only */
@@ -739,6 +745,9 @@ void saa7134_ts_unregister(struct saa7134_mpeg_ops *ops);
 
 int saa7134_ts_init_hw(struct saa7134_dev *dev);
 
+int saa7134_ts_start(struct saa7134_dev *dev);
+int saa7134_ts_stop(struct saa7134_dev *dev);
+
 /* ----------------------------------------------------------- */
 /* saa7134-vbi.c                                               */
 
@@ -786,7 +795,7 @@ void saa7134_irq_oss_done(struct saa7134_dev *dev, unsigned long status);
 int  saa7134_input_init1(struct saa7134_dev *dev);
 void saa7134_input_fini(struct saa7134_dev *dev);
 void saa7134_input_irq(struct saa7134_dev *dev);
-void saa7134_set_i2c_ir(struct saa7134_dev *dev, struct IR_i2c *ir);
+void saa7134_probe_i2c_ir(struct saa7134_dev *dev);
 void saa7134_ir_start(struct saa7134_dev *dev, struct card_ir *ir);
 void saa7134_ir_stop(struct saa7134_dev *dev);
 
diff --git a/drivers/media/video/se401.c b/drivers/media/video/se401.c
index 5990ab38a124..c8f05297d0f0 100644
--- a/drivers/media/video/se401.c
+++ b/drivers/media/video/se401.c
@@ -38,7 +38,7 @@ static const char version[] = "0.24";
 static int flickerless;
 static int video_nr = -1;
 
-static struct usb_device_id device_table [] = {
+static struct usb_device_id device_table[] = {
         { USB_DEVICE(0x03e8, 0x0004) },/* Endpoints/Aox SE401 */
         { USB_DEVICE(0x0471, 0x030b) },/* Philips PCVC665K */
         { USB_DEVICE(0x047d, 0x5001) },/* Kensington 67014 */
@@ -53,7 +53,8 @@ MODULE_AUTHOR("Jeroen Vreeken <pe1rxq@amsat.org>");
 MODULE_DESCRIPTION("SE401 USB Camera Driver");
 MODULE_LICENSE("GPL");
 module_param(flickerless, int, 0);
-MODULE_PARM_DESC(flickerless, "Net frequency to adjust exposure time to (0/50/60)");
+MODULE_PARM_DESC(flickerless,
+                "Net frequency to adjust exposure time to (0/50/60)");
 module_param(video_nr, int, 0);
 
 static struct usb_driver se401_driver;
@@ -78,8 +79,8 @@ static void *rvmalloc(unsigned long size)
         adr = (unsigned long) mem;
         while (size > 0) {
                 SetPageReserved(vmalloc_to_page((void *)adr));
-                adr += PAGE_SIZE;
-                size -= PAGE_SIZE;
+                adr +=  PAGE_SIZE;
+                size -=  PAGE_SIZE;
         }
 
         return mem;
@@ -95,8 +96,8 @@ static void rvfree(void *mem, unsigned long size)
         adr = (unsigned long) mem;
         while ((long) size > 0) {
                 ClearPageReserved(vmalloc_to_page((void *)adr));
-                adr += PAGE_SIZE;
-                size -= PAGE_SIZE;
+                adr +=  PAGE_SIZE;
+                size -=  PAGE_SIZE;
         }
         vfree(mem);
 }
@@ -112,7 +113,7 @@ static void rvfree(void *mem, unsigned long size)
 static int se401_sndctrl(int set, struct usb_se401 *se401, unsigned short req,
                          unsigned short value, unsigned char *cp, int size)
 {
-        return usb_control_msg (
+        return usb_control_msg(
                 se401->dev,
                 set ? usb_sndctrlpipe(se401->dev, 0) : usb_rcvctrlpipe(se401->dev, 0),
                 req,
@@ -132,7 +133,7 @@ static int se401_set_feature(struct usb_se401 *se401, unsigned short selector,
            and the param in index, but in the logs of the windows driver they do
            this the other way around...
          */
-        return usb_control_msg (
+        return usb_control_msg(
                 se401->dev,
                 usb_sndctrlpipe(se401->dev, 0),
                 SE401_REQ_SET_EXT_FEATURE,
@@ -152,7 +153,7 @@ static unsigned short se401_get_feature(struct usb_se401 *se401,
            wrong here to....
          */
         unsigned char cp[2];
-        usb_control_msg (
+        usb_control_msg(
                 se401->dev,
                 usb_rcvctrlpipe(se401->dev, 0),
                 SE401_REQ_GET_EXT_FEATURE,
@@ -175,46 +176,51 @@ static unsigned short se401_get_feature(struct usb_se401 *se401,
 
 static int se401_send_pict(struct usb_se401 *se401)
 {
-        se401_set_feature(se401, HV7131_REG_TITL, se401->expose_l);/* integration time low */
-        se401_set_feature(se401, HV7131_REG_TITM, se401->expose_m);/* integration time mid */
-        se401_set_feature(se401, HV7131_REG_TITU, se401->expose_h);/* integration time mid */
-        se401_set_feature(se401, HV7131_REG_ARLV, se401->resetlevel);/* reset level value */
-        se401_set_feature(se401, HV7131_REG_ARCG, se401->rgain);/* red color gain */
-        se401_set_feature(se401, HV7131_REG_AGCG, se401->ggain);/* green color gain */
-        se401_set_feature(se401, HV7131_REG_ABCG, se401->bgain);/* blue color gain */
+        /* integration time low */
+        se401_set_feature(se401, HV7131_REG_TITL, se401->expose_l);
+        /* integration time mid */
+        se401_set_feature(se401, HV7131_REG_TITM, se401->expose_m);
+        /* integration time mid */
+        se401_set_feature(se401, HV7131_REG_TITU, se401->expose_h);
+        /* reset level value */
+        se401_set_feature(se401, HV7131_REG_ARLV, se401->resetlevel);
+        /* red color gain */
+        se401_set_feature(se401, HV7131_REG_ARCG, se401->rgain);
+        /* green color gain */
+        se401_set_feature(se401, HV7131_REG_AGCG, se401->ggain);
+        /* blue color gain */
+        se401_set_feature(se401, HV7131_REG_ABCG, se401->bgain);
 
         return 0;
 }
 
 static void se401_set_exposure(struct usb_se401 *se401, int brightness)
 {
-        int integration=brightness<<5;
-
-        if (flickerless==50) {
-                integration=integration-integration%106667;
-        }
-        if (flickerless==60) {
-                integration=integration-integration%88889;
-        }
-        se401->brightness=integration>>5;
-        se401->expose_h=(integration>>16)&0xff;
-        se401->expose_m=(integration>>8)&0xff;
-        se401->expose_l=integration&0xff;
+        int integration = brightness << 5;
+
+        if (flickerless == 50)
+                integration = integration-integration % 106667;
+        if (flickerless == 60)
+                integration = integration-integration % 88889;
+        se401->brightness = integration >> 5;
+        se401->expose_h = (integration >> 16) & 0xff;
+        se401->expose_m = (integration >> 8) & 0xff;
+        se401->expose_l = integration & 0xff;
 }
 
 static int se401_get_pict(struct usb_se401 *se401, struct video_picture *p)
 {
-        p->brightness=se401->brightness;
-        if (se401->enhance) {
-                p->whiteness=32768;
-        } else {
-                p->whiteness=0;
-        }
-        p->colour=65535;
-        p->contrast=65535;
-        p->hue=se401->rgain<<10;
-        p->palette=se401->palette;
-        p->depth=3; /* rgb24 */
+        p->brightness = se401->brightness;
+        if (se401->enhance)
+                p->whiteness = 32768;
+        else
+                p->whiteness = 0;
+
+        p->colour = 65535;
+        p->contrast = 65535;
+        p->hue = se401->rgain << 10;
+        p->palette = se401->palette;
+        p->depth = 3; /* rgb24 */
         return 0;
 }
 
@@ -223,20 +229,19 @@ static int se401_set_pict(struct usb_se401 *se401, struct video_picture *p)
 {
         if (p->palette != VIDEO_PALETTE_RGB24)
                 return 1;
-        se401->palette=p->palette;
-        if (p->hue!=se401->hue) {
-                se401->rgain= p->hue>>10;
-                se401->bgain= 0x40-(p->hue>>10);
-                se401->hue=p->hue;
+        se401->palette = p->palette;
+        if (p->hue != se401->hue) {
+                se401->rgain =  p->hue >> 10;
+                se401->bgain =  0x40-(p->hue >> 10);
+                se401->hue = p->hue;
         }
-        if (p->brightness!=se401->brightness) {
+        if (p->brightness != se401->brightness)
                 se401_set_exposure(se401, p->brightness);
-        }
-        if (p->whiteness>=32768) {
-                se401->enhance=1;
-        } else {
-                se401->enhance=0;
-        }
+
+        if (p->whiteness >= 32768)
+                se401->enhance = 1;
+        else
+                se401->enhance = 0;
         se401_send_pict(se401);
         se401_send_pict(se401);
         return 0;
@@ -249,7 +254,7 @@ static int se401_set_pict(struct usb_se401 *se401, struct video_picture *p)
 static void se401_auto_resetlevel(struct usb_se401 *se401)
 {
         unsigned int ahrc, alrc;
-        int oldreset=se401->resetlevel;
+        int oldreset = se401->resetlevel;
 
         /* For some reason this normally read-only register doesn't get reset
            to zero after reading them just once...
@@ -258,24 +263,24 @@ static void se401_auto_resetlevel(struct usb_se401 *se401)
         se401_get_feature(se401, HV7131_REG_HIREFNOL);
         se401_get_feature(se401, HV7131_REG_LOREFNOH);
         se401_get_feature(se401, HV7131_REG_LOREFNOL);
-        ahrc=256*se401_get_feature(se401, HV7131_REG_HIREFNOH) +
+        ahrc = 256*se401_get_feature(se401, HV7131_REG_HIREFNOH) +
             se401_get_feature(se401, HV7131_REG_HIREFNOL);
-        alrc=256*se401_get_feature(se401, HV7131_REG_LOREFNOH) +
+        alrc = 256*se401_get_feature(se401, HV7131_REG_LOREFNOH) +
             se401_get_feature(se401, HV7131_REG_LOREFNOL);
 
         /* Not an exact science, but it seems to work pretty well... */
         if (alrc > 10) {
-                while (alrc>=10 && se401->resetlevel < 63) {
+                while (alrc >= 10 && se401->resetlevel < 63) {
                         se401->resetlevel++;
-                        alrc /=2;
+                        alrc /= 2;
                 }
         } else if (ahrc > 20) {
-                while (ahrc>=20 && se401->resetlevel > 0) {
+                while (ahrc >= 20 && se401->resetlevel > 0) {
                         se401->resetlevel--;
-                        ahrc /=2;
+                        ahrc /= 2;
                 }
         }
-        if (se401->resetlevel!=oldreset)
+        if (se401->resetlevel != oldreset)
                 se401_set_feature(se401, HV7131_REG_ARLV, se401->resetlevel);
 
         return;
@@ -300,21 +305,22 @@ static void se401_button_irq(struct urb *urb)
         case -ENOENT:
         case -ESHUTDOWN:
                 /* this urb is terminated, clean up */
-                dbg("%s - urb shutting down with status: %d", __func__, urb->status);
+                dbg("%s - urb shutting down with status: %d",
+                                                        __func__, urb->status);
                 return;
         default:
-                dbg("%s - nonzero urb status received: %d", __func__, urb->status);
+                dbg("%s - nonzero urb status received: %d",
+                                                        __func__, urb->status);
                 goto exit;
         }
 
-        if (urb->actual_length >=2) {
+        if (urb->actual_length  >= 2)
                 if (se401->button)
-                        se401->buttonpressed=1;
-        }
+                        se401->buttonpressed = 1;
 exit:
-        status = usb_submit_urb (urb, GFP_ATOMIC);
+        status = usb_submit_urb(urb, GFP_ATOMIC);
         if (status)
-                err ("%s - usb_submit_urb failed with result %d",
+                err("%s - usb_submit_urb failed with result %d",
                      __func__, status);
 }
 
@@ -336,55 +342,52 @@ static void se401_video_irq(struct urb *urb)
            keeps sending them forever...
          */
         if (length && !urb->status) {
-                se401->nullpackets=0;
-                switch(se401->scratch[se401->scratch_next].state) {
-                        case BUFFER_READY:
-                        case BUFFER_BUSY: {
-                                se401->dropped++;
-                                break;
-                        }
-                        case BUFFER_UNUSED: {
-                                memcpy(se401->scratch[se401->scratch_next].data, (unsigned char *)urb->transfer_buffer, length);
-                                se401->scratch[se401->scratch_next].state=BUFFER_READY;
-                                se401->scratch[se401->scratch_next].offset=se401->bayeroffset;
-                                se401->scratch[se401->scratch_next].length=length;
-                                if (waitqueue_active(&se401->wq)) {
-                                        wake_up_interruptible(&se401->wq);
-                                }
-                                se401->scratch_overflow=0;
-                                se401->scratch_next++;
-                                if (se401->scratch_next>=SE401_NUMSCRATCH)
-                                        se401->scratch_next=0;
-                                break;
-                        }
-                }
-                se401->bayeroffset+=length;
-                if (se401->bayeroffset>=se401->cheight*se401->cwidth) {
-                        se401->bayeroffset=0;
+                se401->nullpackets = 0;
+                switch (se401->scratch[se401->scratch_next].state) {
+                case BUFFER_READY:
+                case BUFFER_BUSY:
+                        se401->dropped++;
+                        break;
+                case BUFFER_UNUSED:
+                        memcpy(se401->scratch[se401->scratch_next].data,
+                                (unsigned char *)urb->transfer_buffer, length);
+                        se401->scratch[se401->scratch_next].state
+                                                        = BUFFER_READY;
+                        se401->scratch[se401->scratch_next].offset
+                                                        = se401->bayeroffset;
+                        se401->scratch[se401->scratch_next].length = length;
+                        if (waitqueue_active(&se401->wq))
+                                wake_up_interruptible(&se401->wq);
+                        se401->scratch_overflow = 0;
+                        se401->scratch_next++;
+                        if (se401->scratch_next >= SE401_NUMSCRATCH)
+                                se401->scratch_next = 0;
+                        break;
                 }
+                se401->bayeroffset += length;
+                if (se401->bayeroffset >= se401->cheight * se401->cwidth)
+                        se401->bayeroffset = 0;
         } else {
                 se401->nullpackets++;
-                if (se401->nullpackets > SE401_MAX_NULLPACKETS) {
-                        if (waitqueue_active(&se401->wq)) {
+                if (se401->nullpackets > SE401_MAX_NULLPACKETS)
+                        if (waitqueue_active(&se401->wq))
                                 wake_up_interruptible(&se401->wq);
-                        }
-                }
         }
 
         /* Resubmit urb for new data */
-        urb->status=0;
-        urb->dev=se401->dev;
-        if(usb_submit_urb(urb, GFP_KERNEL))
+        urb->status = 0;
+        urb->dev = se401->dev;
+        if (usb_submit_urb(urb, GFP_KERNEL))
                 dev_info(&urb->dev->dev, "urb burned down\n");
         return;
 }
 
 static void se401_send_size(struct usb_se401 *se401, int width, int height)
 {
-        int i=0;
-        int mode=0x03; /* No compression */
-        int sendheight=height;
-        int sendwidth=width;
+        int i = 0;
+        int mode = 0x03; /* No compression */
+        int sendheight = height;
+        int sendwidth = width;
 
         /* JangGu compression can only be used with the camera supported sizes,
            but bayer seems to work with any size that fits on the sensor.
@@ -392,18 +395,21 @@ static void se401_send_size(struct usb_se401 *se401, int width, int height)
            4 or 16 times subcapturing, if not we use uncompressed bayer data
            but this will result in cutouts of the maximum size....
          */
-        while (i<se401->sizes && !(se401->width[i]==width && se401->height[i]==height))
+        while (i < se401->sizes && !(se401->width[i] == width &&
+                                                se401->height[i] == height))
                 i++;
-        while (i<se401->sizes) {
-                if (se401->width[i]==width*2 && se401->height[i]==height*2) {
-                        sendheight=se401->height[i];
-                        sendwidth=se401->width[i];
-                        mode=0x40;
+        while (i < se401->sizes) {
+                if (se401->width[i] == width * 2 &&
+                                se401->height[i] == height * 2) {
+                        sendheight = se401->height[i];
+                        sendwidth = se401->width[i];
+                        mode = 0x40;
                 }
-                if (se401->width[i]==width*4 && se401->height[i]==height*4) {
-                        sendheight=se401->height[i];
-                        sendwidth=se401->width[i];
-                        mode=0x42;
+                if (se401->width[i] == width * 4 &&
+                                se401->height[i] == height * 4) {
+                        sendheight = se401->height[i];
+                        sendwidth = se401->width[i];
+                        mode = 0x42;
                 }
                 i++;
         }
@@ -412,13 +418,10 @@ static void se401_send_size(struct usb_se401 *se401, int width, int height)
         se401_sndctrl(1, se401, SE401_REQ_SET_HEIGHT, sendheight, NULL, 0);
         se401_set_feature(se401, SE401_OPERATINGMODE, mode);
 
-        if (mode==0x03) {
-                se401->format=FMT_BAYER;
-        } else {
-                se401->format=FMT_JANGGU;
-        }
-
-        return;
+        if (mode == 0x03)
+                se401->format = FMT_BAYER;
+        else
+                se401->format = FMT_JANGGU;
 }
 
 /*
@@ -429,29 +432,31 @@ static void se401_send_size(struct usb_se401 *se401, int width, int height)
 static int se401_start_stream(struct usb_se401 *se401)
 {
         struct urb *urb;
-        int err=0, i;
-        se401->streaming=1;
+        int err = 0, i;
+        se401->streaming = 1;
 
         se401_sndctrl(1, se401, SE401_REQ_CAMERA_POWER, 1, NULL, 0);
         se401_sndctrl(1, se401, SE401_REQ_LED_CONTROL, 1, NULL, 0);
 
         /* Set picture settings */
-        se401_set_feature(se401, HV7131_REG_MODE_B, 0x05);/*windowed + pix intg */
+        /* windowed + pix intg */
+        se401_set_feature(se401, HV7131_REG_MODE_B, 0x05);
         se401_send_pict(se401);
 
         se401_send_size(se401, se401->cwidth, se401->cheight);
 
-        se401_sndctrl(1, se401, SE401_REQ_START_CONTINUOUS_CAPTURE, 0, NULL, 0);
+        se401_sndctrl(1, se401, SE401_REQ_START_CONTINUOUS_CAPTURE,
+                                                                0, NULL, 0);
 
         /* Do some memory allocation */
-        for (i=0; i<SE401_NUMFRAMES; i++) {
-                se401->frame[i].data=se401->fbuf + i * se401->maxframesize;
-                se401->frame[i].curpix=0;
+        for (i = 0; i < SE401_NUMFRAMES; i++) {
+                se401->frame[i].data = se401->fbuf + i * se401->maxframesize;
+                se401->frame[i].curpix = 0;
         }
-        for (i=0; i<SE401_NUMSBUF; i++) {
-                se401->sbuf[i].data=kmalloc(SE401_PACKETSIZE, GFP_KERNEL);
+        for (i = 0; i < SE401_NUMSBUF; i++) {
+                se401->sbuf[i].data = kmalloc(SE401_PACKETSIZE, GFP_KERNEL);
                 if (!se401->sbuf[i].data) {
-                        for(i = i - 1; i >= 0; i--) {
+                        for (i = i - 1; i >= 0; i--) {
                                 kfree(se401->sbuf[i].data);
                                 se401->sbuf[i].data = NULL;
                         }
@@ -459,26 +464,26 @@ static int se401_start_stream(struct usb_se401 *se401)
                 }
         }
 
-        se401->bayeroffset=0;
-        se401->scratch_next=0;
-        se401->scratch_use=0;
-        se401->scratch_overflow=0;
-        for (i=0; i<SE401_NUMSCRATCH; i++) {
-                se401->scratch[i].data=kmalloc(SE401_PACKETSIZE, GFP_KERNEL);
+        se401->bayeroffset = 0;
+        se401->scratch_next = 0;
+        se401->scratch_use = 0;
+        se401->scratch_overflow = 0;
+        for (i = 0; i < SE401_NUMSCRATCH; i++) {
+                se401->scratch[i].data = kmalloc(SE401_PACKETSIZE, GFP_KERNEL);
                 if (!se401->scratch[i].data) {
-                        for(i = i - 1; i >= 0; i--) {
+                        for (i = i - 1; i >= 0; i--) {
                                 kfree(se401->scratch[i].data);
                                 se401->scratch[i].data = NULL;
                         }
                         goto nomem_sbuf;
                 }
-                se401->scratch[i].state=BUFFER_UNUSED;
+                se401->scratch[i].state = BUFFER_UNUSED;
         }
 
-        for (i=0; i<SE401_NUMSBUF; i++) {
-                urb=usb_alloc_urb(0, GFP_KERNEL);
-                if(!urb) {
-                        for(i = i - 1; i >= 0; i--) {
+        for (i = 0; i < SE401_NUMSBUF; i++) {
+                urb = usb_alloc_urb(0, GFP_KERNEL);
+                if (!urb) {
+                        for (i = i - 1; i >= 0; i--) {
                                 usb_kill_urb(se401->urb[i]);
                                 usb_free_urb(se401->urb[i]);
                                 se401->urb[i] = NULL;
@@ -492,24 +497,24 @@ static int se401_start_stream(struct usb_se401 *se401)
                         se401_video_irq,
                         se401);
 
-                se401->urb[i]=urb;
+                se401->urb[i] = urb;
 
-                err=usb_submit_urb(se401->urb[i], GFP_KERNEL);
-                if(err)
+                err = usb_submit_urb(se401->urb[i], GFP_KERNEL);
+                if (err)
                         err("urb burned down");
         }
 
-        se401->framecount=0;
+        se401->framecount = 0;
 
         return 0;
 
  nomem_scratch:
-        for (i=0; i<SE401_NUMSCRATCH; i++) {
+        for (i = 0; i < SE401_NUMSCRATCH; i++) {
                 kfree(se401->scratch[i].data);
                 se401->scratch[i].data = NULL;
         }
  nomem_sbuf:
-        for (i=0; i<SE401_NUMSBUF; i++) {
+        for (i = 0; i < SE401_NUMSBUF; i++) {
                 kfree(se401->sbuf[i].data);
                 se401->sbuf[i].data = NULL;
         }
@@ -523,22 +528,23 @@ static int se401_stop_stream(struct usb_se401 *se401)
         if (!se401->streaming || !se401->dev)
                 return 1;
 
-        se401->streaming=0;
+        se401->streaming = 0;
 
         se401_sndctrl(1, se401, SE401_REQ_STOP_CONTINUOUS_CAPTURE, 0, NULL, 0);
 
         se401_sndctrl(1, se401, SE401_REQ_LED_CONTROL, 0, NULL, 0);
         se401_sndctrl(1, se401, SE401_REQ_CAMERA_POWER, 0, NULL, 0);
 
-        for (i=0; i<SE401_NUMSBUF; i++) if (se401->urb[i]) {
-                usb_kill_urb(se401->urb[i]);
-                usb_free_urb(se401->urb[i]);
-                se401->urb[i]=NULL;
-                kfree(se401->sbuf[i].data);
-        }
-        for (i=0; i<SE401_NUMSCRATCH; i++) {
+        for (i = 0; i < SE401_NUMSBUF; i++)
+                if (se401->urb[i]) {
+                        usb_kill_urb(se401->urb[i]);
+                        usb_free_urb(se401->urb[i]);
+                        se401->urb[i] = NULL;
+                        kfree(se401->sbuf[i].data);
+                }
+        for (i = 0; i < SE401_NUMSCRATCH; i++) {
                 kfree(se401->scratch[i].data);
-                se401->scratch[i].data=NULL;
+                se401->scratch[i].data = NULL;
         }
 
         return 0;
@@ -546,9 +552,9 @@ static int se401_stop_stream(struct usb_se401 *se401)
 
 static int se401_set_size(struct usb_se401 *se401, int width, int height)
 {
-        int wasstreaming=se401->streaming;
+        int wasstreaming = se401->streaming;
         /* Check to see if we need to change */
-        if (se401->cwidth==width && se401->cheight==height)
+        if (se401->cwidth == width && se401->cheight == height)
                 return 0;
 
         /* Check for a valid mode */
@@ -556,16 +562,16 @@ static int se401_set_size(struct usb_se401 *se401, int width, int height)
                 return 1;
         if ((width & 1) || (height & 1))
                 return 1;
-        if (width>se401->width[se401->sizes-1])
+        if (width > se401->width[se401->sizes-1])
                 return 1;
-        if (height>se401->height[se401->sizes-1])
+        if (height > se401->height[se401->sizes-1])
                 return 1;
 
         /* Stop a current stream and start it again at the new size */
         if (wasstreaming)
                 se401_stop_stream(se401);
-        se401->cwidth=width;
-        se401->cheight=height;
+        se401->cwidth = width;
+        se401->cheight = height;
         if (wasstreaming)
                 se401_start_stream(se401);
         return 0;
@@ -586,68 +592,68 @@ static int se401_set_size(struct usb_se401 *se401, int width, int height)
 static inline void enhance_picture(unsigned char *frame, int len)
 {
         while (len--) {
-                *frame=(((*frame^255)*(*frame^255))/255)^255;
+                *frame = (((*frame^255)*(*frame^255))/255)^255;
                 frame++;
         }
 }
 
 static inline void decode_JangGu_integrate(struct usb_se401 *se401, int data)
 {
-        struct se401_frame *frame=&se401->frame[se401->curframe];
-        int linelength=se401->cwidth*3;
+        struct se401_frame *frame = &se401->frame[se401->curframe];
+        int linelength = se401->cwidth * 3;
 
         if (frame->curlinepix >= linelength) {
-                frame->curlinepix=0;
-                frame->curline+=linelength;
+                frame->curlinepix = 0;
+                frame->curline += linelength;
         }
 
         /* First three are absolute, all others relative.
          * Format is rgb from right to left (mirrorred image),
          * we flip it to get bgr from left to right. */
-        if (frame->curlinepix < 3) {
-                *(frame->curline-frame->curlinepix)=1+data*4;
-        } else {
-                *(frame->curline-frame->curlinepix)=
-                    *(frame->curline-frame->curlinepix+3)+data*4;
-        }
+        if (frame->curlinepix < 3)
+                *(frame->curline-frame->curlinepix) = 1 + data * 4;
+        else
+                *(frame->curline-frame->curlinepix) =
+                    *(frame->curline-frame->curlinepix + 3) + data * 4;
         frame->curlinepix++;
 }
 
-static inline void decode_JangGu_vlc (struct usb_se401 *se401, unsigned char *data, int bit_exp, int packetlength)
+static inline void decode_JangGu_vlc(struct usb_se401 *se401,
+                        unsigned char *data, int bit_exp, int packetlength)
 {
-        int pos=0;
-        int vlc_cod=0;
-        int vlc_size=0;
-        int vlc_data=0;
+        int pos = 0;
+        int vlc_cod = 0;
+        int vlc_size = 0;
+        int vlc_data = 0;
         int bit_cur;
         int bit;
-        data+=4;
+        data += 4;
         while (pos < packetlength) {
-                bit_cur=8;
+                bit_cur = 8;
                 while (bit_cur && bit_exp) {
-                        bit=((*data)>>(bit_cur-1))&1;
+                        bit = ((*data) >> (bit_cur-1))&1;
                         if (!vlc_cod) {
                                 if (bit) {
                                         vlc_size++;
                                 } else {
-                                        if (!vlc_size) {
+                                        if (!vlc_size)
                                                 decode_JangGu_integrate(se401, 0);
-                                        } else {
-                                                vlc_cod=2;
-                                                vlc_data=0;
+                                        else {
+                                                vlc_cod = 2;
+                                                vlc_data = 0;
                                         }
                                 }
                         } else {
-                                if (vlc_cod==2) {
+                                if (vlc_cod == 2) {
                                         if (!bit)
-                                                vlc_data =  -(1<<vlc_size) + 1;
+                                                vlc_data =  -(1 << vlc_size) + 1;
                                         vlc_cod--;
                                 }
                                 vlc_size--;
-                                vlc_data+=bit<<vlc_size;
+                                vlc_data += bit << vlc_size;
                                 if (!vlc_size) {
                                         decode_JangGu_integrate(se401, vlc_data);
-                                        vlc_cod=0;
+                                        vlc_cod = 0;
                                 }
                         }
                         bit_cur--;
@@ -658,186 +664,188 @@ static inline void decode_JangGu_vlc (struct usb_se401 *se401, unsigned char *da
         }
 }
 
-static inline void decode_JangGu (struct usb_se401 *se401, struct se401_scratch *buffer)
+static inline void decode_JangGu(struct usb_se401 *se401,
+                                                struct se401_scratch *buffer)
 {
-        unsigned char *data=buffer->data;
-        int len=buffer->length;
-        int bit_exp=0, pix_exp=0, frameinfo=0, packetlength=0, size;
-        int datapos=0;
+        unsigned char *data = buffer->data;
+        int len = buffer->length;
+        int bit_exp = 0, pix_exp = 0, frameinfo = 0, packetlength = 0, size;
+        int datapos = 0;
 
         /* New image? */
         if (!se401->frame[se401->curframe].curpix) {
-                se401->frame[se401->curframe].curlinepix=0;
-                se401->frame[se401->curframe].curline=
+                se401->frame[se401->curframe].curlinepix = 0;
+                se401->frame[se401->curframe].curline =
                     se401->frame[se401->curframe].data+
-                    se401->cwidth*3-1;
-                if (se401->frame[se401->curframe].grabstate==FRAME_READY)
-                        se401->frame[se401->curframe].grabstate=FRAME_GRABBING;
-                se401->vlcdatapos=0;
+                    se401->cwidth * 3 - 1;
+                if (se401->frame[se401->curframe].grabstate == FRAME_READY)
+                        se401->frame[se401->curframe].grabstate = FRAME_GRABBING;
+                se401->vlcdatapos = 0;
         }
         while (datapos < len) {
-                size=1024-se401->vlcdatapos;
+                size = 1024 - se401->vlcdatapos;
                 if (size+datapos > len)
-                        size=len-datapos;
+                        size = len-datapos;
                 memcpy(se401->vlcdata+se401->vlcdatapos, data+datapos, size);
-                se401->vlcdatapos+=size;
-                packetlength=0;
+                se401->vlcdatapos += size;
+                packetlength = 0;
                 if (se401->vlcdatapos >= 4) {
-                        bit_exp=se401->vlcdata[3]+(se401->vlcdata[2]<<8);
-                        pix_exp=se401->vlcdata[1]+((se401->vlcdata[0]&0x3f)<<8);
-                        frameinfo=se401->vlcdata[0]&0xc0;
-                        packetlength=((bit_exp+47)>>4)<<1;
+                        bit_exp = se401->vlcdata[3] + (se401->vlcdata[2] << 8);
+                        pix_exp = se401->vlcdata[1] +
+                                        ((se401->vlcdata[0] & 0x3f) << 8);
+                        frameinfo = se401->vlcdata[0] & 0xc0;
+                        packetlength = ((bit_exp + 47) >> 4) << 1;
                         if (packetlength > 1024) {
-                                se401->vlcdatapos=0;
-                                datapos=len;
-                                packetlength=0;
+                                se401->vlcdatapos = 0;
+                                datapos = len;
+                                packetlength = 0;
                                 se401->error++;
-                                se401->frame[se401->curframe].curpix=0;
+                                se401->frame[se401->curframe].curpix = 0;
                         }
                 }
                 if (packetlength && se401->vlcdatapos >= packetlength) {
-                        decode_JangGu_vlc(se401, se401->vlcdata, bit_exp, packetlength);
-                        se401->frame[se401->curframe].curpix+=pix_exp*3;
-                        datapos+=size-(se401->vlcdatapos-packetlength);
-                        se401->vlcdatapos=0;
-                        if (se401->frame[se401->curframe].curpix>=se401->cwidth*se401->cheight*3) {
-                                if (se401->frame[se401->curframe].curpix==se401->cwidth*se401->cheight*3) {
-                                        if (se401->frame[se401->curframe].grabstate==FRAME_GRABBING) {
-                                                se401->frame[se401->curframe].grabstate=FRAME_DONE;
+                        decode_JangGu_vlc(se401, se401->vlcdata, bit_exp,
+                                                                packetlength);
+                        se401->frame[se401->curframe].curpix += pix_exp * 3;
+                        datapos += size-(se401->vlcdatapos-packetlength);
+                        se401->vlcdatapos = 0;
+                        if (se401->frame[se401->curframe].curpix >= se401->cwidth * se401->cheight * 3) {
+                                if (se401->frame[se401->curframe].curpix == se401->cwidth * se401->cheight * 3) {
+                                        if (se401->frame[se401->curframe].grabstate == FRAME_GRABBING) {
+                                                se401->frame[se401->curframe].grabstate = FRAME_DONE;
                                                 se401->framecount++;
                                                 se401->readcount++;
                                         }
-                                        if (se401->frame[(se401->curframe+1)&(SE401_NUMFRAMES-1)].grabstate==FRAME_READY) {
-                                                se401->curframe=(se401->curframe+1) & (SE401_NUMFRAMES-1);
-                                        }
-                                } else {
+                                        if (se401->frame[(se401->curframe + 1) & (SE401_NUMFRAMES - 1)].grabstate == FRAME_READY)
+                                                se401->curframe = (se401->curframe + 1) & (SE401_NUMFRAMES - 1);
+                                } else
                                         se401->error++;
-                                }
-                                se401->frame[se401->curframe].curpix=0;
-                                datapos=len;
+                                se401->frame[se401->curframe].curpix = 0;
+                                datapos = len;
                         }
-                } else {
-                        datapos+=size;
-                }
+                } else
+                        datapos += size;
         }
 }
 
-static inline void decode_bayer (struct usb_se401 *se401, struct se401_scratch *buffer)
+static inline void decode_bayer(struct usb_se401 *se401,
+                                                struct se401_scratch *buffer)
 {
-        unsigned char *data=buffer->data;
-        int len=buffer->length;
-        int offset=buffer->offset;
-        int datasize=se401->cwidth*se401->cheight;
-        struct se401_frame *frame=&se401->frame[se401->curframe];
+        unsigned char *data = buffer->data;
+        int len = buffer->length;
+        int offset = buffer->offset;
+        int datasize = se401->cwidth * se401->cheight;
+        struct se401_frame *frame = &se401->frame[se401->curframe];
+        unsigned char *framedata = frame->data, *curline, *nextline;
+        int width = se401->cwidth;
+        int blineoffset = 0, bline;
+        int linelength = width * 3, i;
 
-        unsigned char *framedata=frame->data, *curline, *nextline;
-        int width=se401->cwidth;
-        int blineoffset=0, bline;
-        int linelength=width*3, i;
 
+        if (frame->curpix == 0) {
+                if (frame->grabstate == FRAME_READY)
+                        frame->grabstate = FRAME_GRABBING;
 
-        if (frame->curpix==0) {
-                if (frame->grabstate==FRAME_READY) {
-                        frame->grabstate=FRAME_GRABBING;
-                }
-                frame->curline=framedata+linelength;
-                frame->curlinepix=0;
+                frame->curline = framedata + linelength;
+                frame->curlinepix = 0;
         }
 
-        if (offset!=frame->curpix) {
+        if (offset != frame->curpix) {
                 /* Regard frame as lost :( */
-                frame->curpix=0;
+                frame->curpix = 0;
                 se401->error++;
                 return;
         }
 
         /* Check if we have to much data */
-        if (frame->curpix+len > datasize) {
-                len=datasize-frame->curpix;
-        }
-        if (se401->cheight%4)
-                blineoffset=1;
-        bline=frame->curpix/se401->cwidth+blineoffset;
-
-        curline=frame->curline;
-        nextline=curline+linelength;
-        if (nextline >= framedata+datasize*3)
-                nextline=curline;
+        if (frame->curpix + len > datasize)
+                len = datasize-frame->curpix;
+
+        if (se401->cheight % 4)
+                blineoffset = 1;
+        bline = frame->curpix / se401->cwidth+blineoffset;
+
+        curline = frame->curline;
+        nextline = curline + linelength;
+        if (nextline >= framedata+datasize * 3)
+                nextline = curline;
         while (len) {
-                if (frame->curlinepix>=width) {
-                        frame->curlinepix-=width;
-                        bline=frame->curpix/width+blineoffset;
-                        curline+=linelength*2;
-                        nextline+=linelength*2;
-                        if (curline >= framedata+datasize*3) {
+                if (frame->curlinepix >= width) {
+                        frame->curlinepix -= width;
+                        bline = frame->curpix / width + blineoffset;
+                        curline += linelength*2;
+                        nextline += linelength*2;
+                        if (curline >= framedata+datasize * 3) {
                                 frame->curlinepix++;
-                                curline-=3;
-                                nextline-=3;
+                                curline -= 3;
+                                nextline -= 3;
                                 len--;
                                 data++;
                                 frame->curpix++;
                         }
                         if (nextline >= framedata+datasize*3)
-                                nextline=curline;
+                                nextline = curline;
                 }
-                if ((bline&1)) {
-                        if ((frame->curlinepix&1)) {
-                                *(curline+2)=*data;
-                                *(curline-1)=*data;
-                                *(nextline+2)=*data;
-                                *(nextline-1)=*data;
+                if (bline & 1) {
+                        if (frame->curlinepix & 1) {
+                                *(curline + 2) = *data;
+                                *(curline - 1) = *data;
+                                *(nextline + 2) = *data;
+                                *(nextline - 1) = *data;
                         } else {
-                                *(curline+1)=
-                                        (*(curline+1)+*data)/2;
-                                *(curline-2)=
-                                        (*(curline-2)+*data)/2;
-                                *(nextline+1)=*data;
-                                *(nextline-2)=*data;
+                                *(curline + 1) =
+                                        (*(curline + 1) + *data) / 2;
+                                *(curline-2) =
+                                        (*(curline - 2) + *data) / 2;
+                                *(nextline + 1) = *data;
+                                *(nextline - 2) = *data;
                         }
                 } else {
-                        if ((frame->curlinepix&1)) {
-                                *(curline+1)=
-                                        (*(curline+1)+*data)/2;
-                                *(curline-2)=
-                                        (*(curline-2)+*data)/2;
-                                *(nextline+1)=*data;
-                                *(nextline-2)=*data;
+                        if (frame->curlinepix & 1) {
+                                *(curline + 1) =
+                                        (*(curline + 1) + *data) / 2;
+                                *(curline - 2) =
+                                        (*(curline - 2) + *data) / 2;
+                                *(nextline + 1) = *data;
+                                *(nextline - 2) = *data;
                         } else {
-                                *curline=*data;
-                                *(curline-3)=*data;
-                                *nextline=*data;
-                                *(nextline-3)=*data;
+                                *curline = *data;
+                                *(curline - 3) = *data;
+                                *nextline = *data;
+                                *(nextline - 3) = *data;
                         }
                 }
                 frame->curlinepix++;
-                curline-=3;
-                nextline-=3;
+                curline -= 3;
+                nextline -= 3;
                 len--;
                 data++;
                 frame->curpix++;
         }
-        frame->curline=curline;
+        frame->curline = curline;
 
-        if (frame->curpix>=datasize) {
+        if (frame->curpix >= datasize) {
                 /* Fix the top line */
-                framedata+=linelength;
-                for (i=0; i<linelength; i++) {
+                framedata += linelength;
+                for (i = 0; i < linelength; i++) {
                         framedata--;
-                        *framedata=*(framedata+linelength);
+                        *framedata = *(framedata + linelength);
                 }
                 /* Fix the left side (green is already present) */
-                for (i=0; i<se401->cheight; i++) {
-                        *framedata=*(framedata+3);
-                        *(framedata+1)=*(framedata+4);
-                        *(framedata+2)=*(framedata+5);
-                        framedata+=linelength;
+                for (i = 0; i < se401->cheight; i++) {
+                        *framedata = *(framedata + 3);
+                        *(framedata + 1) = *(framedata + 4);
+                        *(framedata + 2) = *(framedata + 5);
+                        framedata += linelength;
                 }
-                frame->curpix=0;
-                frame->grabstate=FRAME_DONE;
+                frame->curpix = 0;
+                frame->grabstate = FRAME_DONE;
                 se401->framecount++;
                 se401->readcount++;
-                if (se401->frame[(se401->curframe+1)&(SE401_NUMFRAMES-1)].grabstate==FRAME_READY) {
-                        se401->curframe=(se401->curframe+1) & (SE401_NUMFRAMES-1);
+                if (se401->frame[(se401->curframe + 1) &
+                    (SE401_NUMFRAMES - 1)].grabstate == FRAME_READY) {
+                        se401->curframe = (se401->curframe+1) &
+                                                        (SE401_NUMFRAMES-1);
                 }
         }
 }
@@ -845,72 +853,76 @@ static inline void decode_bayer (struct usb_se401 *se401, struct se401_scratch *
 static int se401_newframe(struct usb_se401 *se401, int framenr)
 {
         DECLARE_WAITQUEUE(wait, current);
-        int errors=0;
+        int errors = 0;
 
         while (se401->streaming &&
-            (se401->frame[framenr].grabstate==FRAME_READY ||
-             se401->frame[framenr].grabstate==FRAME_GRABBING) ) {
-                if(!se401->frame[framenr].curpix) {
+            (se401->frame[framenr].grabstate == FRAME_READY ||
+             se401->frame[framenr].grabstate == FRAME_GRABBING)) {
+                if (!se401->frame[framenr].curpix)
                         errors++;
-                }
+
                 wait_interruptible(
-                    se401->scratch[se401->scratch_use].state!=BUFFER_READY,
-                    &se401->wq,
-                    &wait
-                );
+                    se401->scratch[se401->scratch_use].state != BUFFER_READY,
+                                                    &se401->wq, &wait);
                 if (se401->nullpackets > SE401_MAX_NULLPACKETS) {
-                        se401->nullpackets=0;
+                        se401->nullpackets = 0;
                         dev_info(&se401->dev->dev,
-                                 "too many null length packets, restarting capture\n");
+                         "too many null length packets, restarting capture\n");
                         se401_stop_stream(se401);
                         se401_start_stream(se401);
                 } else {
-                        if (se401->scratch[se401->scratch_use].state!=BUFFER_READY) {
-                                se401->frame[framenr].grabstate=FRAME_ERROR;
+                        if (se401->scratch[se401->scratch_use].state !=
+                                                                BUFFER_READY) {
+                                se401->frame[framenr].grabstate = FRAME_ERROR;
                                 return -EIO;
                         }
-                        se401->scratch[se401->scratch_use].state=BUFFER_BUSY;
-                        if (se401->format==FMT_JANGGU) {
-                                decode_JangGu(se401, &se401->scratch[se401->scratch_use]);
-                        } else {
-                                decode_bayer(se401, &se401->scratch[se401->scratch_use]);
-                        }
-                        se401->scratch[se401->scratch_use].state=BUFFER_UNUSED;
+                        se401->scratch[se401->scratch_use].state = BUFFER_BUSY;
+                        if (se401->format == FMT_JANGGU)
+                                decode_JangGu(se401,
+                                        &se401->scratch[se401->scratch_use]);
+                        else
+                                decode_bayer(se401,
+                                        &se401->scratch[se401->scratch_use]);
+
+                        se401->scratch[se401->scratch_use].state =
+                                                        BUFFER_UNUSED;
                         se401->scratch_use++;
-                        if (se401->scratch_use>=SE401_NUMSCRATCH)
-                                se401->scratch_use=0;
+                        if (se401->scratch_use >= SE401_NUMSCRATCH)
+                                se401->scratch_use = 0;
                         if (errors > SE401_MAX_ERRORS) {
-                                errors=0;
+                                errors = 0;
                                 dev_info(&se401->dev->dev,
-                                         "too many errors, restarting capture\n");
+                                      "too many errors, restarting capture\n");
                                 se401_stop_stream(se401);
                                 se401_start_stream(se401);
                         }
                 }
         }
 
-        if (se401->frame[framenr].grabstate==FRAME_DONE)
+        if (se401->frame[framenr].grabstate == FRAME_DONE)
                 if (se401->enhance)
-                        enhance_picture(se401->frame[framenr].data, se401->cheight*se401->cwidth*3);
+                        enhance_picture(se401->frame[framenr].data,
+                                        se401->cheight * se401->cwidth * 3);
         return 0;
 }
 
-static void usb_se401_remove_disconnected (struct usb_se401 *se401)
+static void usb_se401_remove_disconnected(struct usb_se401 *se401)
 {
         int i;
 
         se401->dev = NULL;
 
-        for (i=0; i<SE401_NUMSBUF; i++)
+        for (i = 0; i < SE401_NUMSBUF; i++)
                 if (se401->urb[i]) {
                         usb_kill_urb(se401->urb[i]);
                         usb_free_urb(se401->urb[i]);
                         se401->urb[i] = NULL;
                         kfree(se401->sbuf[i].data);
                 }
-        for (i=0; i<SE401_NUMSCRATCH; i++) {
+
+        for (i = 0; i < SE401_NUMSCRATCH; i++)
                 kfree(se401->scratch[i].data);
-        }
+
         if (se401->inturb) {
                 usb_kill_urb(se401->inturb);
                 usb_free_urb(se401->inturb);
@@ -965,11 +977,11 @@ static int se401_close(struct file *file)
                 dev_info(&se401->dev->dev, "device unregistered\n");
                 usb_se401_remove_disconnected(se401);
         } else {
-                for (i=0; i<SE401_NUMFRAMES; i++)
-                        se401->frame[i].grabstate=FRAME_UNUSED;
+                for (i = 0; i < SE401_NUMFRAMES; i++)
+                        se401->frame[i].grabstate = FRAME_UNUSED;
                 if (se401->streaming)
                         se401_stop_stream(se401);
-                se401->user=0;
+                se401->user = 0;
         }
         file->private_data = NULL;
         return 0;
@@ -1065,7 +1077,7 @@ static long se401_do_ioctl(struct file *file, unsigned int cmd, void *arg)
                 memset(vm, 0, sizeof(*vm));
                 vm->size = SE401_NUMFRAMES * se401->maxframesize;
                 vm->frames = SE401_NUMFRAMES;
-                for (i=0; i<SE401_NUMFRAMES; i++)
+                for (i = 0; i < SE401_NUMFRAMES; i++)
                         vm->offsets[i] = se401->maxframesize * i;
                 return 0;
         }
@@ -1083,16 +1095,16 @@ static long se401_do_ioctl(struct file *file, unsigned int cmd, void *arg)
                 /* Is this according to the v4l spec??? */
                 if (se401_set_size(se401, vm->width, vm->height))
                         return -EINVAL;
-                se401->frame[vm->frame].grabstate=FRAME_READY;
+                se401->frame[vm->frame].grabstate = FRAME_READY;
 
                 if (!se401->streaming)
                         se401_start_stream(se401);
 
                 /* Set the picture properties */
-                if (se401->framecount==0)
+                if (se401->framecount == 0)
                         se401_send_pict(se401);
                 /* Calibrate the reset level after a few frames. */
-                if (se401->framecount%20==1)
+                if (se401->framecount % 20 == 1)
                         se401_auto_resetlevel(se401);
 
                 return 0;
@@ -1100,13 +1112,13 @@ static long se401_do_ioctl(struct file *file, unsigned int cmd, void *arg)
         case VIDIOCSYNC:
         {
                 int *frame = arg;
-                int ret=0;
+                int ret = 0;
 
-                if(*frame <0 || *frame >= SE401_NUMFRAMES)
+                if (*frame < 0 || *frame >= SE401_NUMFRAMES)
                         return -EINVAL;
 
-                ret=se401_newframe(se401, *frame);
-                se401->frame[*frame].grabstate=FRAME_UNUSED;
+                ret = se401_newframe(se401, *frame);
+                se401->frame[*frame].grabstate = FRAME_UNUSED;
                 return ret;
         }
         case VIDIOCGFBUF:
@@ -1147,36 +1159,36 @@ static long se401_ioctl(struct file *file,
 static ssize_t se401_read(struct file *file, char __user *buf,
                      size_t count, loff_t *ppos)
 {
-        int realcount=count, ret=0;
+        int realcount = count, ret = 0;
         struct video_device *dev = file->private_data;
         struct usb_se401 *se401 = (struct usb_se401 *)dev;
 
 
-        if (se401->dev == NULL)
+        if (se401->dev ==  NULL)
                 return -EIO;
         if (realcount > se401->cwidth*se401->cheight*3)
-                realcount=se401->cwidth*se401->cheight*3;
+                realcount = se401->cwidth*se401->cheight*3;
 
         /* Shouldn't happen: */
-        if (se401->frame[0].grabstate==FRAME_GRABBING)
+        if (se401->frame[0].grabstate == FRAME_GRABBING)
                 return -EBUSY;
-        se401->frame[0].grabstate=FRAME_READY;
-        se401->frame[1].grabstate=FRAME_UNUSED;
-        se401->curframe=0;
+        se401->frame[0].grabstate = FRAME_READY;
+        se401->frame[1].grabstate = FRAME_UNUSED;
+        se401->curframe = 0;
 
         if (!se401->streaming)
                 se401_start_stream(se401);
 
         /* Set the picture properties */
-        if (se401->framecount==0)
+        if (se401->framecount == 0)
                 se401_send_pict(se401);
         /* Calibrate the reset level after a few frames. */
-        if (se401->framecount%20==1)
+        if (se401->framecount%20 == 1)
                 se401_auto_resetlevel(se401);
 
-        ret=se401_newframe(se401, 0);
+        ret = se401_newframe(se401, 0);
 
-        se401->frame[0].grabstate=FRAME_UNUSED;
+        se401->frame[0].grabstate = FRAME_UNUSED;
         if (ret)
                 return ret;
         if (copy_to_user(buf, se401->frame[0].data, realcount))
@@ -1195,11 +1207,12 @@ static int se401_mmap(struct file *file, struct vm_area_struct *vma)
 
         mutex_lock(&se401->lock);
 
-        if (se401->dev == NULL) {
+        if (se401->dev ==  NULL) {
                 mutex_unlock(&se401->lock);
                 return -EIO;
         }
-        if (size > (((SE401_NUMFRAMES * se401->maxframesize) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1))) {
+        if (size > (((SE401_NUMFRAMES * se401->maxframesize) + PAGE_SIZE - 1)
+                                                        & ~(PAGE_SIZE - 1))) {
                 mutex_unlock(&se401->lock);
                 return -EINVAL;
         }
@@ -1210,10 +1223,10 @@ static int se401_mmap(struct file *file, struct vm_area_struct *vma)
                         mutex_unlock(&se401->lock);
                         return -EAGAIN;
                 }
-                start += PAGE_SIZE;
-                pos += PAGE_SIZE;
+                start +=  PAGE_SIZE;
+                pos +=  PAGE_SIZE;
                 if (size > PAGE_SIZE)
-                        size -= PAGE_SIZE;
+                        size -=  PAGE_SIZE;
                 else
                         size = 0;
         }
@@ -1223,7 +1236,7 @@ static int se401_mmap(struct file *file, struct vm_area_struct *vma)
 }
 
 static const struct v4l2_file_operations se401_fops = {
-        .owner =        THIS_MODULE,
+        .owner  =       THIS_MODULE,
         .open =         se401_open,
         .release =      se401_close,
         .read =         se401_read,
@@ -1241,71 +1254,76 @@ static struct video_device se401_template = {
 /***************************/
 static int se401_init(struct usb_se401 *se401, int button)
 {
-        int i=0, rc;
+        int i = 0, rc;
         unsigned char cp[0x40];
         char temp[200];
+        int slen;
 
         /* led on */
         se401_sndctrl(1, se401, SE401_REQ_LED_CONTROL, 1, NULL, 0);
 
         /* get camera descriptor */
-        rc=se401_sndctrl(0, se401, SE401_REQ_GET_CAMERA_DESCRIPTOR, 0, cp, sizeof(cp));
-        if (cp[1]!=0x41) {
+        rc = se401_sndctrl(0, se401, SE401_REQ_GET_CAMERA_DESCRIPTOR, 0,
+                                                        cp, sizeof(cp));
+        if (cp[1] != 0x41) {
                 err("Wrong descriptor type");
                 return 1;
         }
-        sprintf (temp, "ExtraFeatures: %d", cp[3]);
+        slen = snprintf(temp, 200, "ExtraFeatures: %d", cp[3]);
 
-        se401->sizes=cp[4]+cp[5]*256;
-        se401->width=kmalloc(se401->sizes*sizeof(int), GFP_KERNEL);
+        se401->sizes = cp[4] + cp[5] * 256;
+        se401->width = kmalloc(se401->sizes*sizeof(int), GFP_KERNEL);
         if (!se401->width)
                 return 1;
-        se401->height=kmalloc(se401->sizes*sizeof(int), GFP_KERNEL);
+        se401->height = kmalloc(se401->sizes*sizeof(int), GFP_KERNEL);
         if (!se401->height) {
                 kfree(se401->width);
                 return 1;
         }
-        for (i=0; i<se401->sizes; i++) {
-                    se401->width[i]=cp[6+i*4+0]+cp[6+i*4+1]*256;
-                    se401->height[i]=cp[6+i*4+2]+cp[6+i*4+3]*256;
+        for (i = 0; i < se401->sizes; i++) {
+                se401->width[i] = cp[6 + i * 4 + 0] + cp[6 + i*4 + 1] * 256;
+                se401->height[i] = cp[6 + i * 4 + 2] + cp[6 + i * 4 + 3] * 256;
         }
-        sprintf (temp, "%s Sizes:", temp);
-        for (i=0; i<se401->sizes; i++) {
-                sprintf(temp, "%s %dx%d", temp, se401->width[i], se401->height[i]);
+        slen += snprintf(temp + slen, 200 - slen, " Sizes:");
+        for (i = 0; i < se401->sizes; i++) {
+                slen +=  snprintf(temp + slen, 200 - slen,
+                        " %dx%d", se401->width[i], se401->height[i]);
         }
         dev_info(&se401->dev->dev, "%s\n", temp);
-        se401->maxframesize=se401->width[se401->sizes-1]*se401->height[se401->sizes-1]*3;
+        se401->maxframesize = se401->width[se401->sizes-1] *
+                                        se401->height[se401->sizes - 1] * 3;
 
-        rc=se401_sndctrl(0, se401, SE401_REQ_GET_WIDTH, 0, cp, sizeof(cp));
-        se401->cwidth=cp[0]+cp[1]*256;
-        rc=se401_sndctrl(0, se401, SE401_REQ_GET_HEIGHT, 0, cp, sizeof(cp));
-        se401->cheight=cp[0]+cp[1]*256;
+        rc = se401_sndctrl(0, se401, SE401_REQ_GET_WIDTH, 0, cp, sizeof(cp));
+        se401->cwidth = cp[0]+cp[1]*256;
+        rc = se401_sndctrl(0, se401, SE401_REQ_GET_HEIGHT, 0, cp, sizeof(cp));
+        se401->cheight = cp[0]+cp[1]*256;
 
         if (!(cp[2] & SE401_FORMAT_BAYER)) {
                 err("Bayer format not supported!");
                 return 1;
         }
         /* set output mode (BAYER) */
-        se401_sndctrl(1, se401, SE401_REQ_SET_OUTPUT_MODE, SE401_FORMAT_BAYER, NULL, 0);
+        se401_sndctrl(1, se401, SE401_REQ_SET_OUTPUT_MODE,
+                                                SE401_FORMAT_BAYER, NULL, 0);
 
-        rc=se401_sndctrl(0, se401, SE401_REQ_GET_BRT, 0, cp, sizeof(cp));
-        se401->brightness=cp[0]+cp[1]*256;
+        rc = se401_sndctrl(0, se401, SE401_REQ_GET_BRT, 0, cp, sizeof(cp));
+        se401->brightness = cp[0]+cp[1]*256;
         /* some default values */
-        se401->resetlevel=0x2d;
-        se401->rgain=0x20;
-        se401->ggain=0x20;
-        se401->bgain=0x20;
+        se401->resetlevel = 0x2d;
+        se401->rgain = 0x20;
+        se401->ggain = 0x20;
+        se401->bgain = 0x20;
         se401_set_exposure(se401, 20000);
-        se401->palette=VIDEO_PALETTE_RGB24;
-        se401->enhance=1;
-        se401->dropped=0;
-        se401->error=0;
-        se401->framecount=0;
-        se401->readcount=0;
+        se401->palette = VIDEO_PALETTE_RGB24;
+        se401->enhance = 1;
+        se401->dropped = 0;
+        se401->error = 0;
+        se401->framecount = 0;
+        se401->readcount = 0;
 
         /* Start interrupt transfers for snapshot button */
         if (button) {
-                se401->inturb=usb_alloc_urb(0, GFP_KERNEL);
+                se401->inturb = usb_alloc_urb(0, GFP_KERNEL);
                 if (!se401->inturb) {
                         dev_info(&se401->dev->dev,
                                  "Allocation of inturb failed\n");
@@ -1323,7 +1341,7 @@ static int se401_init(struct usb_se401 *se401, int button)
                         return 1;
                 }
         } else
-                se401->inturb=NULL;
+                se401->inturb = NULL;
 
         /* Flash the led */
         se401_sndctrl(1, se401, SE401_REQ_CAMERA_POWER, 1, NULL, 0);
@@ -1340,8 +1358,8 @@ static int se401_probe(struct usb_interface *intf,
         struct usb_device *dev = interface_to_usbdev(intf);
         struct usb_interface_descriptor *interface;
         struct usb_se401 *se401;
-        char *camera_name=NULL;
-        int button=1;
+        char *camera_name = NULL;
+        int button = 1;
 
         /* We don't handle multi-config cameras */
         if (dev->descriptor.bNumConfigurations != 1)
@@ -1350,22 +1368,22 @@ static int se401_probe(struct usb_interface *intf,
         interface = &intf->cur_altsetting->desc;
 
         /* Is it an se401? */
-        if (le16_to_cpu(dev->descriptor.idVendor) == 0x03e8 &&
-            le16_to_cpu(dev->descriptor.idProduct) == 0x0004) {
-                camera_name="Endpoints/Aox SE401";
-        } else if (le16_to_cpu(dev->descriptor.idVendor) == 0x0471 &&
-            le16_to_cpu(dev->descriptor.idProduct) == 0x030b) {
-                camera_name="Philips PCVC665K";
-        } else if (le16_to_cpu(dev->descriptor.idVendor) == 0x047d &&
-            le16_to_cpu(dev->descriptor.idProduct) == 0x5001) {
-                camera_name="Kensington VideoCAM 67014";
-        } else if (le16_to_cpu(dev->descriptor.idVendor) == 0x047d &&
-            le16_to_cpu(dev->descriptor.idProduct) == 0x5002) {
-                camera_name="Kensington VideoCAM 6701(5/7)";
-        } else if (le16_to_cpu(dev->descriptor.idVendor) == 0x047d &&
-            le16_to_cpu(dev->descriptor.idProduct) == 0x5003) {
-                camera_name="Kensington VideoCAM 67016";
-                button=0;
+        if (le16_to_cpu(dev->descriptor.idVendor) ==  0x03e8 &&
+            le16_to_cpu(dev->descriptor.idProduct) ==  0x0004) {
+                camera_name = "Endpoints/Aox SE401";
+        } else if (le16_to_cpu(dev->descriptor.idVendor) ==  0x0471 &&
+            le16_to_cpu(dev->descriptor.idProduct) ==  0x030b) {
+                camera_name = "Philips PCVC665K";
+        } else if (le16_to_cpu(dev->descriptor.idVendor) ==  0x047d &&
+            le16_to_cpu(dev->descriptor.idProduct) ==  0x5001) {
+                camera_name = "Kensington VideoCAM 67014";
+        } else if (le16_to_cpu(dev->descriptor.idVendor) ==  0x047d &&
+            le16_to_cpu(dev->descriptor.idProduct) ==  0x5002) {
+                camera_name = "Kensington VideoCAM 6701(5/7)";
+        } else if (le16_to_cpu(dev->descriptor.idVendor) ==  0x047d &&
+            le16_to_cpu(dev->descriptor.idProduct) ==  0x5003) {
+                camera_name = "Kensington VideoCAM 67016";
+                button = 0;
         } else
                 return -ENODEV;
 
@@ -1378,7 +1396,8 @@ static int se401_probe(struct usb_interface *intf,
         /* We found one */
         dev_info(&intf->dev, "SE401 camera found: %s\n", camera_name);
 
-        if ((se401 = kzalloc(sizeof(*se401), GFP_KERNEL)) == NULL) {
+        se401 = kzalloc(sizeof(*se401), GFP_KERNEL);
+        if (se401 ==  NULL) {
                 err("couldn't kmalloc se401 struct");
                 return -ENOMEM;
         }
@@ -1396,12 +1415,14 @@ static int se401_probe(struct usb_interface *intf,
         }
 
         memcpy(&se401->vdev, &se401_template, sizeof(se401_template));
-        memcpy(se401->vdev.name, se401->camera_name, strlen(se401->camera_name));
+        memcpy(se401->vdev.name, se401->camera_name,
+                                        strlen(se401->camera_name));
         init_waitqueue_head(&se401->wq);
         mutex_init(&se401->lock);
         wmb();
 
-        if (video_register_device(&se401->vdev, VFL_TYPE_GRABBER, video_nr) < 0) {
+        if (video_register_device(&se401->vdev,
+                                        VFL_TYPE_GRABBER, video_nr) < 0) {
                 kfree(se401);
                 err("video_register_device failed");
                 return -EIO;
@@ -1409,20 +1430,20 @@ static int se401_probe(struct usb_interface *intf,
         dev_info(&intf->dev, "registered new video device: video%d\n",
                  se401->vdev.num);
 
-        usb_set_intfdata (intf, se401);
+        usb_set_intfdata(intf, se401);
         return 0;
 }
 
 static void se401_disconnect(struct usb_interface *intf)
 {
-        struct usb_se401 *se401 = usb_get_intfdata (intf);
+        struct usb_se401 *se401 = usb_get_intfdata(intf);
 
-        usb_set_intfdata (intf, NULL);
+        usb_set_intfdata(intf, NULL);
         if (se401) {
                 video_unregister_device(&se401->vdev);
-                if (!se401->user){
+                if (!se401->user)
                         usb_se401_remove_disconnected(se401);
-                } else {
+                else {
                         se401->frame[0].grabstate = FRAME_ERROR;
                         se401->frame[0].grabstate = FRAME_ERROR;
 
@@ -1435,10 +1456,10 @@ static void se401_disconnect(struct usb_interface *intf)
 }
 
 static struct usb_driver se401_driver = {
-        .name           = "se401",
-        .id_table       = device_table,
-        .probe          = se401_probe,
-        .disconnect     = se401_disconnect,
+        .name            =  "se401",
+        .id_table        =  device_table,
+        .probe           =  se401_probe,
+        .disconnect      =  se401_disconnect,
 };
 
 
@@ -1451,9 +1472,10 @@ static struct usb_driver se401_driver = {
 
 static int __init usb_se401_init(void)
 {
-        printk(KERN_INFO "SE401 usb camera driver version %s registering\n", version);
+        printk(KERN_INFO "SE401 usb camera driver version %s registering\n",
+                                                                version);
         if (flickerless)
-                if (flickerless!=50 && flickerless!=60) {
+                if (flickerless != 50 && flickerless != 60) {
                         printk(KERN_ERR "Invallid flickerless value, use 0, 50 or 60.\n");
                         return -1;
         }
diff --git a/drivers/media/video/se401.h b/drivers/media/video/se401.h
index 2ce685db5d8b..bf7d2e9765b0 100644
--- a/drivers/media/video/se401.h
+++ b/drivers/media/video/se401.h
@@ -2,7 +2,7 @@
 #ifndef __LINUX_se401_H
 #define __LINUX_se401_H
 
-#include <asm/uaccess.h>
+#include <linux/uaccess.h>
 #include <linux/videodev.h>
 #include <media/v4l2-common.h>
 #include <media/v4l2-ioctl.h>
@@ -12,9 +12,10 @@
 
 #ifdef se401_DEBUG
 #  define PDEBUG(level, fmt, args...) \
-if (debug >= level) info("[" __PRETTY_FUNCTION__ ":%d] " fmt, __LINE__ , ## args)
+if (debug >= level) \
+        info("[" __PRETTY_FUNCTION__ ":%d] " fmt, __LINE__ , ## args)
 #else
-#  define PDEBUG(level, fmt, args...) do {} while(0)
+#  define PDEBUG(level, fmt, args...) do {} while (0)
 #endif
 
 /* An almost drop-in replacement for sleep_on_interruptible */
diff --git a/drivers/media/video/sh_mobile_ceu_camera.c b/drivers/media/video/sh_mobile_ceu_camera.c
index b5e37a530c62..d369e8409ab8 100644
--- a/drivers/media/video/sh_mobile_ceu_camera.c
+++ b/drivers/media/video/sh_mobile_ceu_camera.c
@@ -81,7 +81,6 @@ struct sh_mobile_ceu_buffer {
 };
 
 struct sh_mobile_ceu_dev {
-        struct device *dev;
         struct soc_camera_host ici;
         struct soc_camera_device *icd;
 
@@ -617,7 +616,7 @@ static int sh_mobile_ceu_get_formats(struct soc_camera_device *icd, int idx,
                         xlate->cam_fmt = icd->formats + idx;
                         xlate->buswidth = icd->formats[idx].depth;
                         xlate++;
-                        dev_dbg(&ici->dev, "Providing format %s using %s\n",
+                        dev_dbg(ici->dev, "Providing format %s using %s\n",
                                 sh_mobile_ceu_formats[k].name,
                                 icd->formats[idx].name);
                 }
@@ -630,7 +629,7 @@ add_single_format:
                         xlate->cam_fmt = icd->formats + idx;
                         xlate->buswidth = icd->formats[idx].depth;
                         xlate++;
-                        dev_dbg(&ici->dev,
+                        dev_dbg(ici->dev,
                                 "Providing format %s in pass-through mode\n",
                                 icd->formats[idx].name);
                 }
@@ -657,7 +656,7 @@ static int sh_mobile_ceu_set_fmt(struct soc_camera_device *icd,
 
         xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
         if (!xlate) {
-                dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
+                dev_warn(ici->dev, "Format %x not found\n", pixfmt);
                 return -EINVAL;
         }
 
@@ -684,7 +683,7 @@ static int sh_mobile_ceu_try_fmt(struct soc_camera_device *icd,
 
         xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
         if (!xlate) {
-                dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
+                dev_warn(ici->dev, "Format %x not found\n", pixfmt);
                 return -EINVAL;
         }
 
@@ -782,7 +781,7 @@ static void sh_mobile_ceu_init_videobuf(struct videobuf_queue *q,
 
         videobuf_queue_dma_contig_init(q,
                                        &sh_mobile_ceu_videobuf_ops,
-                                       &ici->dev, &pcdev->lock,
+                                       ici->dev, &pcdev->lock,
                                        V4L2_BUF_TYPE_VIDEO_CAPTURE,
                                        pcdev->is_interlaced ?
                                        V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE,
@@ -829,7 +828,6 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev)
                 goto exit;
         }
 
-        platform_set_drvdata(pdev, pcdev);
         INIT_LIST_HEAD(&pcdev->capture);
         spin_lock_init(&pcdev->lock);
 
@@ -840,7 +838,7 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev)
                 goto exit_kfree;
         }
 
-        base = ioremap_nocache(res->start, res->end - res->start + 1);
+        base = ioremap_nocache(res->start, resource_size(res));
         if (!base) {
                 err = -ENXIO;
                 dev_err(&pdev->dev, "Unable to ioremap CEU registers.\n");
@@ -850,13 +848,12 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev)
         pcdev->irq = irq;
         pcdev->base = base;
         pcdev->video_limit = 0; /* only enabled if second resource exists */
-        pcdev->dev = &pdev->dev;
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
         if (res) {
                 err = dma_declare_coherent_memory(&pdev->dev, res->start,
                                                   res->start,
-                                                  (res->end - res->start) + 1,
+                                                  resource_size(res),
                                                   DMA_MEMORY_MAP |
                                                   DMA_MEMORY_EXCLUSIVE);
                 if (!err) {
@@ -865,7 +862,7 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev)
                         goto exit_iounmap;
                 }
 
-                pcdev->video_limit = (res->end - res->start) + 1;
+                pcdev->video_limit = resource_size(res);
         }
 
         /* request irq */
@@ -885,7 +882,7 @@ static int sh_mobile_ceu_probe(struct platform_device *pdev)
         }
 
         pcdev->ici.priv = pcdev;
-        pcdev->ici.dev.parent = &pdev->dev;
+        pcdev->ici.dev = &pdev->dev;
         pcdev->ici.nr = pdev->id;
         pcdev->ici.drv_name = dev_name(&pdev->dev);
         pcdev->ici.ops = &sh_mobile_ceu_host_ops;
@@ -913,9 +910,11 @@ exit:
 
 static int sh_mobile_ceu_remove(struct platform_device *pdev)
 {
-        struct sh_mobile_ceu_dev *pcdev = platform_get_drvdata(pdev);
+        struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
+        struct sh_mobile_ceu_dev *pcdev = container_of(soc_host,
+                                        struct sh_mobile_ceu_dev, ici);
 
-        soc_camera_host_unregister(&pcdev->ici);
+        soc_camera_host_unregister(soc_host);
         clk_put(pcdev->clk);
         free_irq(pcdev->irq, pcdev);
         if (platform_get_resource(pdev, IORESOURCE_MEM, 1))
diff --git a/drivers/media/video/soc_camera.c b/drivers/media/video/soc_camera.c
index 0e890cc23377..16f595d4337a 100644
--- a/drivers/media/video/soc_camera.c
+++ b/drivers/media/video/soc_camera.c
@@ -16,19 +16,21 @@
  * published by the Free Software Foundation.
  */
 
-#include <linux/module.h>
-#include <linux/init.h>
 #include <linux/device.h>
-#include <linux/list.h>
 #include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/module.h>
 #include <linux/mutex.h>
+#include <linux/platform_device.h>
 #include <linux/vmalloc.h>
 
+#include <media/soc_camera.h>
 #include <media/v4l2-common.h>
-#include <media/v4l2-ioctl.h>
 #include <media/v4l2-dev.h>
+#include <media/v4l2-ioctl.h>
 #include <media/videobuf-core.h>
-#include <media/soc_camera.h>
 
 /* Default to VGA resolution */
 #define DEFAULT_WIDTH   640
@@ -279,7 +281,7 @@ static int soc_camera_set_fmt(struct soc_camera_file *icf,
                 return ret;
         } else if (!icd->current_fmt ||
                    icd->current_fmt->fourcc != pix->pixelformat) {
-                dev_err(&ici->dev,
+                dev_err(ici->dev,
                         "Host driver hasn't set up current format correctly!\n");
                 return -EINVAL;
         }
@@ -794,7 +796,7 @@ static void scan_add_host(struct soc_camera_host *ici)
 
         list_for_each_entry(icd, &devices, list) {
                 if (icd->iface == ici->nr) {
-                        icd->dev.parent = &ici->dev;
+                        icd->dev.parent = ici->dev;
                         device_register_link(icd);
                 }
         }
@@ -818,7 +820,7 @@ static int scan_add_device(struct soc_camera_device *icd)
         list_for_each_entry(ici, &hosts, list) {
                 if (icd->iface == ici->nr) {
                         ret = 1;
-                        icd->dev.parent = &ici->dev;
+                        icd->dev.parent = ici->dev;
                         break;
                 }
         }
@@ -952,7 +954,6 @@ static void dummy_release(struct device *dev)
 
 int soc_camera_host_register(struct soc_camera_host *ici)
 {
-        int ret;
         struct soc_camera_host *ix;
 
         if (!ici || !ici->ops ||
@@ -965,12 +966,10 @@ int soc_camera_host_register(struct soc_camera_host *ici)
             !ici->ops->reqbufs ||
             !ici->ops->add ||
             !ici->ops->remove ||
-            !ici->ops->poll)
+            !ici->ops->poll ||
+            !ici->dev)
                 return -EINVAL;
 
-        /* Number might be equal to the platform device ID */
-        dev_set_name(&ici->dev, "camera_host%d", ici->nr);
-
         mutex_lock(&list_lock);
         list_for_each_entry(ix, &hosts, list) {
                 if (ix->nr == ici->nr) {
@@ -979,26 +978,14 @@ int soc_camera_host_register(struct soc_camera_host *ici)
                 }
         }
 
+        dev_set_drvdata(ici->dev, ici);
+
         list_add_tail(&ici->list, &hosts);
         mutex_unlock(&list_lock);
 
-        ici->dev.release = dummy_release;
-
-        ret = device_register(&ici->dev);
-
-        if (ret)
-                goto edevr;
-
         scan_add_host(ici);
 
         return 0;
-
-edevr:
-        mutex_lock(&list_lock);
-        list_del(&ici->list);
-        mutex_unlock(&list_lock);
-
-        return ret;
 }
 EXPORT_SYMBOL(soc_camera_host_register);
 
@@ -1012,7 +999,7 @@ void soc_camera_host_unregister(struct soc_camera_host *ici)
         list_del(&ici->list);
 
         list_for_each_entry(icd, &devices, list) {
-                if (icd->dev.parent == &ici->dev) {
+                if (icd->dev.parent == ici->dev) {
                         device_unregister(&icd->dev);
                         /* Not before device_unregister(), .remove
                          * needs parent to call ici->ops->remove() */
@@ -1023,7 +1010,7 @@ void soc_camera_host_unregister(struct soc_camera_host *ici)
 
         mutex_unlock(&list_lock);
 
-        device_unregister(&ici->dev);
+        dev_set_drvdata(ici->dev, NULL);
 }
 EXPORT_SYMBOL(soc_camera_host_unregister);
 
@@ -1130,7 +1117,7 @@ int soc_camera_video_start(struct soc_camera_device *icd)
         vdev = video_device_alloc();
         if (!vdev)
                 goto evidallocd;
-        dev_dbg(&ici->dev, "Allocated video_device %p\n", vdev);
+        dev_dbg(ici->dev, "Allocated video_device %p\n", vdev);
 
         strlcpy(vdev->name, ici->drv_name, sizeof(vdev->name));
 
@@ -1174,6 +1161,57 @@ void soc_camera_video_stop(struct soc_camera_device *icd)
 }
 EXPORT_SYMBOL(soc_camera_video_stop);
 
+static int __devinit soc_camera_pdrv_probe(struct platform_device *pdev)
+{
+        struct soc_camera_link *icl = pdev->dev.platform_data;
+        struct i2c_adapter *adap;
+        struct i2c_client *client;
+
+        if (!icl)
+                return -EINVAL;
+
+        adap = i2c_get_adapter(icl->i2c_adapter_id);
+        if (!adap) {
+                dev_warn(&pdev->dev, "Cannot get adapter #%d. No driver?\n",
+                         icl->i2c_adapter_id);
+                /* -ENODEV and -ENXIO do not produce an error on probe()... */
+                return -ENOENT;
+        }
+
+        icl->board_info->platform_data = icl;
+        client = i2c_new_device(adap, icl->board_info);
+        if (!client) {
+                i2c_put_adapter(adap);
+                return -ENOMEM;
+        }
+
+        platform_set_drvdata(pdev, client);
+
+        return 0;
+}
+
+static int __devexit soc_camera_pdrv_remove(struct platform_device *pdev)
+{
+        struct i2c_client *client = platform_get_drvdata(pdev);
+
+        if (!client)
+                return -ENODEV;
+
+        i2c_unregister_device(client);
+        i2c_put_adapter(client->adapter);
+
+        return 0;
+}
+
+static struct platform_driver __refdata soc_camera_pdrv = {
+        .probe  = soc_camera_pdrv_probe,
+        .remove = __devexit_p(soc_camera_pdrv_remove),
+        .driver = {
+                .name = "soc-camera-pdrv",
+                .owner = THIS_MODULE,
+        },
+};
+
 static int __init soc_camera_init(void)
 {
         int ret = bus_register(&soc_camera_bus_type);
@@ -1183,8 +1221,14 @@ static int __init soc_camera_init(void)
         if (ret)
                 goto edrvr;
 
+        ret = platform_driver_register(&soc_camera_pdrv);
+        if (ret)
+                goto epdr;
+
         return 0;
 
+epdr:
+        driver_unregister(&ic_drv);
 edrvr:
         bus_unregister(&soc_camera_bus_type);
         return ret;
@@ -1192,6 +1236,7 @@ edrvr:
 
 static void __exit soc_camera_exit(void)
 {
+        platform_driver_unregister(&soc_camera_pdrv);
         driver_unregister(&ic_drv);
         bus_unregister(&soc_camera_bus_type);
 }
@@ -1202,3 +1247,4 @@ module_exit(soc_camera_exit);
 MODULE_DESCRIPTION("Image capture bus driver");
 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
 MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:soc-camera-pdrv");
diff --git a/drivers/media/video/stk-webcam.c b/drivers/media/video/stk-webcam.c
index 1a6d39cbd6f3..2e5937047278 100644
--- a/drivers/media/video/stk-webcam.c
+++ b/drivers/media/video/stk-webcam.c
@@ -1137,7 +1137,7 @@ static int stk_vidioc_querybuf(struct file *filp,
         struct stk_camera *dev = priv;
         struct stk_sio_buffer *sbuf;
 
-        if (buf->index < 0 || buf->index >= dev->n_sbufs)
+        if (buf->index >= dev->n_sbufs)
                 return -EINVAL;
         sbuf = dev->sio_bufs + buf->index;
         *buf = sbuf->v4lbuf;
@@ -1154,7 +1154,7 @@ static int stk_vidioc_qbuf(struct file *filp,
         if (buf->memory != V4L2_MEMORY_MMAP)
                 return -EINVAL;
 
-        if (buf->index < 0 || buf->index >= dev->n_sbufs)
+        if (buf->index >= dev->n_sbufs)
                 return -EINVAL;
         sbuf = dev->sio_bufs + buf->index;
         if (sbuf->v4lbuf.flags & V4L2_BUF_FLAG_QUEUED)
diff --git a/drivers/media/video/tda7432.c b/drivers/media/video/tda7432.c
index 005f8a468031..80f1cee23fa5 100644
--- a/drivers/media/video/tda7432.c
+++ b/drivers/media/video/tda7432.c
@@ -20,20 +20,6 @@
  * loudness - set between 0 and 15 for varying degrees of loudness effect
  *
  * maxvol   - set maximium volume to +20db (1), default is 0db(0)
- *
- *
- *  Revision: 0.7 - maxvol module parm to set maximium volume 0db or +20db
- *                              store if muted so we can return it
- *                              change balance only if flaged to
- *  Revision: 0.6 - added tone controls
- *  Revision: 0.5 - Fixed odd balance problem
- *  Revision: 0.4 - added muting
- *  Revision: 0.3 - Fixed silly reversed volume controls.  :)
- *  Revision: 0.2 - Cleaned up #defines
- *                      fixed volume control
- *          Added I2C_DRIVERID_TDA7432
- *                      added loudness insmod control
- *  Revision: 0.1 - initial version
  */
 
 #include <linux/module.h>
diff --git a/drivers/media/video/tea6415c.c b/drivers/media/video/tea6415c.c
index d4a9ed45764b..1585839bd0bd 100644
--- a/drivers/media/video/tea6415c.c
+++ b/drivers/media/video/tea6415c.c
@@ -141,7 +141,6 @@ static const struct v4l2_subdev_ops tea6415c_ops = {
         .video = &tea6415c_video_ops,
 };
 
-/* this function is called by i2c_probe */
 static int tea6415c_probe(struct i2c_client *client,
                           const struct i2c_device_id *id)
 {
diff --git a/drivers/media/video/tea6420.c b/drivers/media/video/tea6420.c
index ced6eadf347a..0446524d3543 100644
--- a/drivers/media/video/tea6420.c
+++ b/drivers/media/video/tea6420.c
@@ -112,7 +112,6 @@ static const struct v4l2_subdev_ops tea6420_ops = {
         .audio = &tea6420_audio_ops,
 };
 
-/* this function is called by i2c_probe */
 static int tea6420_probe(struct i2c_client *client,
                           const struct i2c_device_id *id)
 {
diff --git a/drivers/media/video/ths7303.c b/drivers/media/video/ths7303.c
new file mode 100644
index 000000000000..21781f8a0e8e
--- /dev/null
+++ b/drivers/media/video/ths7303.c
@@ -0,0 +1,151 @@
+/*
+ * ths7303- THS7303 Video Amplifier driver
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed .as is. WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ctype.h>
+#include <linux/i2c.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/uaccess.h>
+#include <linux/videodev2.h>
+
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-chip-ident.h>
+
+MODULE_DESCRIPTION("TI THS7303 video amplifier driver");
+MODULE_AUTHOR("Chaithrika U S");
+MODULE_LICENSE("GPL");
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Debug level 0-1");
+
+/* following function is used to set ths7303 */
+static int ths7303_setvalue(struct v4l2_subdev *sd, v4l2_std_id std)
+{
+        int err = 0;
+        u8 val;
+        struct i2c_client *client;
+
+        client = v4l2_get_subdevdata(sd);
+
+        if (std & (V4L2_STD_ALL & ~V4L2_STD_SECAM)) {
+                val = 0x02;
+                v4l2_dbg(1, debug, sd, "setting value for SDTV format\n");
+        } else {
+                val = 0x00;
+                v4l2_dbg(1, debug, sd, "disabling all channels\n");
+        }
+
+        err |= i2c_smbus_write_byte_data(client, 0x01, val);
+        err |= i2c_smbus_write_byte_data(client, 0x02, val);
+        err |= i2c_smbus_write_byte_data(client, 0x03, val);
+
+        if (err)
+                v4l2_err(sd, "write failed\n");
+
+        return err;
+}
+
+static int ths7303_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
+{
+        return ths7303_setvalue(sd, norm);
+}
+
+static int ths7303_g_chip_ident(struct v4l2_subdev *sd,
+                                struct v4l2_dbg_chip_ident *chip)
+{
+        struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+        return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_THS7303, 0);
+}
+
+static const struct v4l2_subdev_video_ops ths7303_video_ops = {
+        .s_std_output   = ths7303_s_std_output,
+};
+
+static const struct v4l2_subdev_core_ops ths7303_core_ops = {
+        .g_chip_ident = ths7303_g_chip_ident,
+};
+
+static const struct v4l2_subdev_ops ths7303_ops = {
+        .core   = &ths7303_core_ops,
+        .video  = &ths7303_video_ops,
+};
+
+static int ths7303_probe(struct i2c_client *client,
+                        const struct i2c_device_id *id)
+{
+        struct v4l2_subdev *sd;
+        v4l2_std_id std_id = V4L2_STD_NTSC;
+
+        if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+                return -ENODEV;
+
+        v4l_info(client, "chip found @ 0x%x (%s)\n",
+                        client->addr << 1, client->adapter->name);
+
+        sd = kzalloc(sizeof(struct v4l2_subdev), GFP_KERNEL);
+        if (sd == NULL)
+                return -ENOMEM;
+
+        v4l2_i2c_subdev_init(sd, client, &ths7303_ops);
+
+        return ths7303_setvalue(sd, std_id);
+}
+
+static int ths7303_remove(struct i2c_client *client)
+{
+        struct v4l2_subdev *sd = i2c_get_clientdata(client);
+
+        v4l2_device_unregister_subdev(sd);
+        kfree(sd);
+
+        return 0;
+}
+
+static const struct i2c_device_id ths7303_id[] = {
+        {"ths7303", 0},
+        {},
+};
+
+MODULE_DEVICE_TABLE(i2c, ths7303_id);
+
+static struct i2c_driver ths7303_driver = {
+        .driver = {
+                .owner  = THIS_MODULE,
+                .name   = "ths7303",
+        },
+        .probe          = ths7303_probe,
+        .remove         = ths7303_remove,
+        .id_table       = ths7303_id,
+};
+
+static int __init ths7303_init(void)
+{
+        return i2c_add_driver(&ths7303_driver);
+}
+
+static void __exit ths7303_exit(void)
+{
+        i2c_del_driver(&ths7303_driver);
+}
+
+module_init(ths7303_init);
+module_exit(ths7303_exit);
+
diff --git a/drivers/media/video/tuner-core.c b/drivers/media/video/tuner-core.c
index 78c377a399cb..537594211a90 100644
--- a/drivers/media/video/tuner-core.c
+++ b/drivers/media/video/tuner-core.c
@@ -309,32 +309,6 @@ static void set_freq(struct i2c_client *c, unsigned long freq)
         }
 }
 
-static void tuner_i2c_address_check(struct tuner *t)
-{
-        if ((t->type == UNSET || t->type == TUNER_ABSENT) ||
-            ((t->i2c->addr < 0x64) || (t->i2c->addr > 0x6f)))
-                return;
-
-        /* We already know that the XC5000 can only be located at
-         * i2c address 0x61, 0x62, 0x63 or 0x64 */
-        if ((t->type == TUNER_XC5000) &&
-            ((t->i2c->addr <= 0x64)) && (t->i2c->addr >= 0x61))
-                return;
-
-        tuner_warn("====================== WARNING! ======================\n");
-        tuner_warn("Support for tuners in i2c address range 0x64 thru 0x6f\n");
-        tuner_warn("will soon be dropped. This message indicates that your\n");
-        tuner_warn("hardware has a %s tuner at i2c address 0x%02x.\n",
-                   t->name, t->i2c->addr);
-        tuner_warn("To ensure continued support for your device, please\n");
-        tuner_warn("send a copy of this message, along with full dmesg\n");
-        tuner_warn("output to v4l-dvb-maintainer@linuxtv.org\n");
-        tuner_warn("Please use subject line: \"obsolete tuner i2c address.\"\n");
-        tuner_warn("driver: %s, addr: 0x%02x, type: %d (%s)\n",
-                   t->i2c->adapter->name, t->i2c->addr, t->type, t->name);
-        tuner_warn("====================== WARNING! ======================\n");
-}
-
 static struct xc5000_config xc5000_cfg;
 
 static void set_type(struct i2c_client *c, unsigned int type,
@@ -438,18 +412,12 @@ static void set_type(struct i2c_client *c, unsigned int type,
                 break;
         case TUNER_XC5000:
         {
-                struct dvb_tuner_ops *xc_tuner_ops;
-
                 xc5000_cfg.i2c_address    = t->i2c->addr;
                 /* if_khz will be set when the digital dvb_attach() occurs */
                 xc5000_cfg.if_khz         = 0;
                 if (!dvb_attach(xc5000_attach,
                                 &t->fe, t->i2c->adapter, &xc5000_cfg))
                         goto attach_failed;
-
-                xc_tuner_ops = &t->fe.ops.tuner_ops;
-                if (xc_tuner_ops->init)
-                        xc_tuner_ops->init(&t->fe);
                 break;
         }
         default:
@@ -490,7 +458,6 @@ static void set_type(struct i2c_client *c, unsigned int type,
         tuner_dbg("%s %s I2C addr 0x%02x with type %d used for 0x%02x\n",
                   c->adapter->name, c->driver->driver.name, c->addr << 1, type,
                   t->mode_mask);
-        tuner_i2c_address_check(t);
         return;
 
 attach_failed:
diff --git a/drivers/media/video/tveeprom.c b/drivers/media/video/tveeprom.c
index e24a38c7fa46..ac02808106c1 100644
--- a/drivers/media/video/tveeprom.c
+++ b/drivers/media/video/tveeprom.c
@@ -184,7 +184,7 @@ hauppauge_tuner[] =
         { TUNER_ABSENT,                 "Silicon TDA8275C1 8290 FM"},
         { TUNER_ABSENT,                 "Thompson DTT757"},
         /* 80-89 */
-        { TUNER_PHILIPS_FM1216ME_MK3,   "Philips FQ1216LME MK3"},
+        { TUNER_PHILIPS_FQ1216LME_MK3,  "Philips FQ1216LME MK3"},
         { TUNER_LG_PAL_NEW_TAPC,        "LG TAPC G701D"},
         { TUNER_LG_NTSC_NEW_TAPC,       "LG TAPC H791F"},
         { TUNER_LG_PAL_NEW_TAPC,        "TCL 2002MB 3"},
@@ -210,7 +210,7 @@ hauppauge_tuner[] =
         { TUNER_TEA5767,                "Philips TEA5768HL FM Radio"},
         { TUNER_ABSENT,                 "Panasonic ENV57H12D5"},
         { TUNER_PHILIPS_FM1236_MK3,     "TCL MFNM05-4"},
-        { TUNER_ABSENT,                 "TCL MNM05-4"},
+        { TUNER_PHILIPS_FM1236_MK3,     "TCL MNM05-4"},
         { TUNER_PHILIPS_FM1216ME_MK3,   "TCL MPE05-2"},
         { TUNER_ABSENT,                 "TCL MQNM05-4"},
         { TUNER_ABSENT,                 "LG TAPC-W701D"},
@@ -229,7 +229,7 @@ hauppauge_tuner[] =
         { TUNER_ABSENT,                 "Samsung THPD5222FG30A"},
         /* 120-129 */
         { TUNER_XC2028,                 "Xceive XC3028"},
-        { TUNER_ABSENT,                 "Philips FQ1216LME MK5"},
+        { TUNER_PHILIPS_FQ1216LME_MK3,  "Philips FQ1216LME MK5"},
         { TUNER_ABSENT,                 "Philips FQD1216LME"},
         { TUNER_ABSENT,                 "Conexant CX24118A"},
         { TUNER_ABSENT,                 "TCL DMF11WIP"},
diff --git a/drivers/media/video/tvp514x.c b/drivers/media/video/tvp514x.c
index 4262e60b8116..3750f7fadb12 100644
--- a/drivers/media/video/tvp514x.c
+++ b/drivers/media/video/tvp514x.c
@@ -692,7 +692,7 @@ static int ioctl_s_routing(struct v4l2_int_device *s,
                         break;  /* Input detected */
         }
 
-        if ((current_std == STD_INVALID) || (try_count <= 0))
+        if ((current_std == STD_INVALID) || (try_count < 0))
                 return -EINVAL;
 
         decoder->current_std = current_std;
diff --git a/drivers/media/video/usbvideo/konicawc.c b/drivers/media/video/usbvideo/konicawc.c
index 900ec2129ca1..31d57f2d09e1 100644
--- a/drivers/media/video/usbvideo/konicawc.c
+++ b/drivers/media/video/usbvideo/konicawc.c
@@ -240,7 +240,7 @@ static void konicawc_register_input(struct konicawc *cam, struct usb_device *dev
         input_dev->dev.parent = &dev->dev;
 
         input_dev->evbit[0] = BIT_MASK(EV_KEY);
-        input_dev->keybit[BIT_WORD(BTN_0)] = BIT_MASK(BTN_0);
+        input_dev->keybit[BIT_WORD(KEY_CAMERA)] = BIT_MASK(KEY_CAMERA);
 
         error = input_register_device(cam->input);
         if (error) {
@@ -263,7 +263,7 @@ static void konicawc_unregister_input(struct konicawc *cam)
 static void konicawc_report_buttonstat(struct konicawc *cam)
 {
         if (cam->input) {
-                input_report_key(cam->input, BTN_0, cam->buttonsts);
+                input_report_key(cam->input, KEY_CAMERA, cam->buttonsts);
                 input_sync(cam->input);
         }
 }
diff --git a/drivers/media/video/usbvideo/quickcam_messenger.c b/drivers/media/video/usbvideo/quickcam_messenger.c
index fd112f0b9d35..803d3e4e29a2 100644
--- a/drivers/media/video/usbvideo/quickcam_messenger.c
+++ b/drivers/media/video/usbvideo/quickcam_messenger.c
@@ -103,7 +103,7 @@ static void qcm_register_input(struct qcm *cam, struct usb_device *dev)
         input_dev->dev.parent = &dev->dev;
 
         input_dev->evbit[0] = BIT_MASK(EV_KEY);
-        input_dev->keybit[BIT_WORD(BTN_0)] = BIT_MASK(BTN_0);
+        input_dev->keybit[BIT_WORD(KEY_CAMERA)] = BIT_MASK(KEY_CAMERA);
 
         error = input_register_device(cam->input);
         if (error) {
@@ -126,7 +126,7 @@ static void qcm_unregister_input(struct qcm *cam)
 static void qcm_report_buttonstat(struct qcm *cam)
 {
         if (cam->input) {
-                input_report_key(cam->input, BTN_0, cam->button_sts);
+                input_report_key(cam->input, KEY_CAMERA, cam->button_sts);
                 input_sync(cam->input);
         }
 }
diff --git a/drivers/media/video/usbvision/usbvision-core.c b/drivers/media/video/usbvision/usbvision-core.c
index 8bc03b9e1315..6ba16abeebdd 100644
--- a/drivers/media/video/usbvision/usbvision-core.c
+++ b/drivers/media/video/usbvision/usbvision-core.c
@@ -390,10 +390,9 @@ int usbvision_scratch_alloc(struct usb_usbvision *usbvision)
 
 void usbvision_scratch_free(struct usb_usbvision *usbvision)
 {
-        if (usbvision->scratch != NULL) {
-                vfree(usbvision->scratch);
-                usbvision->scratch = NULL;
-        }
+        vfree(usbvision->scratch);
+        usbvision->scratch = NULL;
+
 }
 
 /*
@@ -506,10 +505,9 @@ int usbvision_decompress_alloc(struct usb_usbvision *usbvision)
  */
 void usbvision_decompress_free(struct usb_usbvision *usbvision)
 {
-        if (usbvision->IntraFrameBuffer != NULL) {
-                vfree(usbvision->IntraFrameBuffer);
-                usbvision->IntraFrameBuffer = NULL;
-        }
+        vfree(usbvision->IntraFrameBuffer);
+        usbvision->IntraFrameBuffer = NULL;
+
 }
 
 /************************************************************
diff --git a/drivers/media/video/usbvision/usbvision-video.c b/drivers/media/video/usbvision/usbvision-video.c
index d7056a5b7f9b..90b58914f984 100644
--- a/drivers/media/video/usbvision/usbvision-video.c
+++ b/drivers/media/video/usbvision/usbvision-video.c
@@ -541,7 +541,7 @@ static int vidioc_enum_input (struct file *file, void *priv,
         struct usb_usbvision *usbvision = video_drvdata(file);
         int chan;
 
-        if ((vi->index >= usbvision->video_inputs) || (vi->index < 0) )
+        if (vi->index >= usbvision->video_inputs)
                 return -EINVAL;
         if (usbvision->have_tuner) {
                 chan = vi->index;
@@ -1794,7 +1794,7 @@ static struct usb_driver usbvision_driver = {
         .name           = "usbvision",
         .id_table       = usbvision_table,
         .probe          = usbvision_probe,
-        .disconnect     = usbvision_disconnect
+        .disconnect     = __devexit_p(usbvision_disconnect),
 };
 
 /*
diff --git a/drivers/media/video/uvc/uvc_ctrl.c b/drivers/media/video/uvc/uvc_ctrl.c
index 0d7e38d6ff6a..36a6ba92df27 100644
--- a/drivers/media/video/uvc/uvc_ctrl.c
+++ b/drivers/media/video/uvc/uvc_ctrl.c
@@ -1372,21 +1372,19 @@ end:
 }
 
 /*
- * Prune an entity of its bogus controls. This currently includes processing
- * unit auto controls for which no corresponding manual control is available.
- * Such auto controls make little sense if any, and are known to crash at
- * least the SiGma Micro webcam.
+ * Prune an entity of its bogus controls using a blacklist. Bogus controls
+ * are currently the ones that crash the camera or unconditionally return an
+ * error when queried.
  */
 static void
-uvc_ctrl_prune_entity(struct uvc_entity *entity)
+uvc_ctrl_prune_entity(struct uvc_device *dev, struct uvc_entity *entity)
 {
         static const struct {
-                u8 idx_manual;
-                u8 idx_auto;
+                struct usb_device_id id;
+                u8 index;
         } blacklist[] = {
-                { 2, 11 }, /* Hue */
-                { 6, 12 }, /* White Balance Temperature */
-                { 7, 13 }, /* White Balance Component */
+                { { USB_DEVICE(0x1c4f, 0x3000) }, 6 }, /* WB Temperature */
+                { { USB_DEVICE(0x5986, 0x0241) }, 2 }, /* Hue */
         };
 
         u8 *controls;
@@ -1400,19 +1398,17 @@ uvc_ctrl_prune_entity(struct uvc_entity *entity)
         size = entity->processing.bControlSize;
 
         for (i = 0; i < ARRAY_SIZE(blacklist); ++i) {
-                if (blacklist[i].idx_auto >= 8 * size ||
-                    blacklist[i].idx_manual >= 8 * size)
+                if (!usb_match_id(dev->intf, &blacklist[i].id))
                         continue;
 
-                if (!uvc_test_bit(controls, blacklist[i].idx_auto) ||
-                     uvc_test_bit(controls, blacklist[i].idx_manual))
+                if (blacklist[i].index >= 8 * size ||
+                    !uvc_test_bit(controls, blacklist[i].index))
                         continue;
 
-                uvc_trace(UVC_TRACE_CONTROL, "Auto control %u/%u has no "
-                        "matching manual control, removing it.\n", entity->id,
-                        blacklist[i].idx_auto);
+                uvc_trace(UVC_TRACE_CONTROL, "%u/%u control is black listed, "
+                        "removing it.\n", entity->id, blacklist[i].index);
 
-                uvc_clear_bit(controls, blacklist[i].idx_auto);
+                uvc_clear_bit(controls, blacklist[i].index);
         }
 }
 
@@ -1442,8 +1438,7 @@ int uvc_ctrl_init_device(struct uvc_device *dev)
                         bControlSize = entity->camera.bControlSize;
                 }
 
-                if (dev->quirks & UVC_QUIRK_PRUNE_CONTROLS)
-                        uvc_ctrl_prune_entity(entity);
+                uvc_ctrl_prune_entity(dev, entity);
 
                 for (i = 0; i < bControlSize; ++i)
                         ncontrols += hweight8(bmControls[i]);
diff --git a/drivers/media/video/uvc/uvc_driver.c b/drivers/media/video/uvc/uvc_driver.c
index 507dc85646b2..89927b7aec28 100644
--- a/drivers/media/video/uvc/uvc_driver.c
+++ b/drivers/media/video/uvc/uvc_driver.c
@@ -289,10 +289,8 @@ static int uvc_parse_format(struct uvc_device *dev,
         struct uvc_format_desc *fmtdesc;
         struct uvc_frame *frame;
         const unsigned char *start = buffer;
-        unsigned char *_buffer;
         unsigned int interval;
         unsigned int i, n;
-        int _buflen;
         __u8 ftype;
 
         format->type = buffer[2];
@@ -303,7 +301,7 @@ static int uvc_parse_format(struct uvc_device *dev,
         case VS_FORMAT_FRAME_BASED:
                 n = buffer[2] == VS_FORMAT_UNCOMPRESSED ? 27 : 28;
                 if (buflen < n) {
-                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming"
+                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming "
                                "interface %d FORMAT error\n",
                                dev->udev->devnum,
                                alts->desc.bInterfaceNumber);
@@ -338,7 +336,7 @@ static int uvc_parse_format(struct uvc_device *dev,
 
         case VS_FORMAT_MJPEG:
                 if (buflen < 11) {
-                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming"
+                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming "
                                "interface %d FORMAT error\n",
                                dev->udev->devnum,
                                alts->desc.bInterfaceNumber);
@@ -354,7 +352,7 @@ static int uvc_parse_format(struct uvc_device *dev,
 
         case VS_FORMAT_DV:
                 if (buflen < 9) {
-                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming"
+                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming "
                                "interface %d FORMAT error\n",
                                dev->udev->devnum,
                                alts->desc.bInterfaceNumber);
@@ -372,7 +370,7 @@ static int uvc_parse_format(struct uvc_device *dev,
                         strlcpy(format->name, "HD-DV", sizeof format->name);
                         break;
                 default:
-                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming"
+                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming "
                                "interface %d: unknown DV format %u\n",
                                dev->udev->devnum,
                                alts->desc.bInterfaceNumber, buffer[8]);
@@ -401,7 +399,7 @@ static int uvc_parse_format(struct uvc_device *dev,
         case VS_FORMAT_STREAM_BASED:
                 /* Not supported yet. */
         default:
-                uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming"
+                uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming "
                        "interface %d unsupported format %u\n",
                        dev->udev->devnum, alts->desc.bInterfaceNumber,
                        buffer[2]);
@@ -413,20 +411,11 @@ static int uvc_parse_format(struct uvc_device *dev,
         buflen -= buffer[0];
         buffer += buffer[0];
 
-        /* Count the number of frame descriptors to test the bFrameIndex
-         * field when parsing the descriptors. We can't rely on the
-         * bNumFrameDescriptors field as some cameras don't initialize it
-         * properly.
-         */
-        for (_buflen = buflen, _buffer = buffer;
-             _buflen > 2 && _buffer[2] == ftype;
-             _buflen -= _buffer[0], _buffer += _buffer[0])
-                format->nframes++;
-
         /* Parse the frame descriptors. Only uncompressed, MJPEG and frame
          * based formats have frame descriptors.
          */
         while (buflen > 2 && buffer[2] == ftype) {
+                frame = &format->frame[format->nframes];
                 if (ftype != VS_FRAME_FRAME_BASED)
                         n = buflen > 25 ? buffer[25] : 0;
                 else
@@ -435,22 +424,12 @@ static int uvc_parse_format(struct uvc_device *dev,
                 n = n ? n : 3;
 
                 if (buflen < 26 + 4*n) {
-                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming"
+                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming "
                                "interface %d FRAME error\n", dev->udev->devnum,
                                alts->desc.bInterfaceNumber);
                         return -EINVAL;
                 }
 
-                if (buffer[3] - 1 >= format->nframes) {
-                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming"
-                               "interface %d frame index %u out of range\n",
-                               dev->udev->devnum, alts->desc.bInterfaceNumber,
-                               buffer[3]);
-                        return -EINVAL;
-                }
-
-                frame = &format->frame[buffer[3] - 1];
-
                 frame->bFrameIndex = buffer[3];
                 frame->bmCapabilities = buffer[4];
                 frame->wWidth = get_unaligned_le16(&buffer[5]);
@@ -507,6 +486,7 @@ static int uvc_parse_format(struct uvc_device *dev,
                         10000000/frame->dwDefaultFrameInterval,
                         (100000000/frame->dwDefaultFrameInterval)%10);
 
+                format->nframes++;
                 buflen -= buffer[0];
                 buffer += buffer[0];
         }
@@ -518,7 +498,7 @@ static int uvc_parse_format(struct uvc_device *dev,
 
         if (buflen > 2 && buffer[2] == VS_COLORFORMAT) {
                 if (buflen < 6) {
-                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming"
+                        uvc_trace(UVC_TRACE_DESCR, "device %d videostreaming "
                                "interface %d COLORFORMAT error\n",
                                dev->udev->devnum,
                                alts->desc.bInterfaceNumber);
@@ -664,7 +644,7 @@ static int uvc_parse_streaming(struct uvc_device *dev,
         _buflen = buflen;
 
         /* Count the format and frame descriptors. */
-        while (_buflen > 2) {
+        while (_buflen > 2 && _buffer[1] == CS_INTERFACE) {
                 switch (_buffer[2]) {
                 case VS_FORMAT_UNCOMPRESSED:
                 case VS_FORMAT_MJPEG:
@@ -729,7 +709,7 @@ static int uvc_parse_streaming(struct uvc_device *dev,
         streaming->nformats = nformats;
 
         /* Parse the format descriptors. */
-        while (buflen > 2) {
+        while (buflen > 2 && buffer[1] == CS_INTERFACE) {
                 switch (buffer[2]) {
                 case VS_FORMAT_UNCOMPRESSED:
                 case VS_FORMAT_MJPEG:
@@ -1316,7 +1296,7 @@ static int uvc_scan_chain_forward(struct uvc_video_device *video,
                         continue;
 
                 if (forward->extension.bNrInPins != 1) {
-                        uvc_trace(UVC_TRACE_DESCR, "Extension unit %d has"
+                        uvc_trace(UVC_TRACE_DESCR, "Extension unit %d has "
                                 "more than 1 input pin.\n", entity->id);
                         return -1;
                 }
@@ -1614,6 +1594,7 @@ static int uvc_probe(struct usb_interface *intf,
         INIT_LIST_HEAD(&dev->entities);
         INIT_LIST_HEAD(&dev->streaming);
         kref_init(&dev->kref);
+        atomic_set(&dev->users, 0);
 
         dev->udev = usb_get_dev(udev);
         dev->intf = usb_get_intf(intf);
@@ -1927,7 +1908,7 @@ static struct usb_device_id uvc_ids[] = {
           .bInterfaceSubClass   = 1,
           .bInterfaceProtocol   = 0,
           .driver_info          = UVC_QUIRK_STREAM_NO_FID },
-        /* Lenovo Thinkpad SL500 */
+        /* Lenovo Thinkpad SL400/SL500 */
         { .match_flags          = USB_DEVICE_ID_MATCH_DEVICE
                                 | USB_DEVICE_ID_MATCH_INT_INFO,
           .idVendor             = 0x17ef,
@@ -1936,6 +1917,15 @@ static struct usb_device_id uvc_ids[] = {
           .bInterfaceSubClass   = 1,
           .bInterfaceProtocol   = 0,
           .driver_info          = UVC_QUIRK_STREAM_NO_FID },
+        /* Aveo Technology USB 2.0 Camera */
+        { .match_flags          = USB_DEVICE_ID_MATCH_DEVICE
+                                | USB_DEVICE_ID_MATCH_INT_INFO,
+          .idVendor             = 0x1871,
+          .idProduct            = 0x0306,
+          .bInterfaceClass      = USB_CLASS_VIDEO,
+          .bInterfaceSubClass   = 1,
+          .bInterfaceProtocol   = 0,
+          .driver_info          = UVC_QUIRK_PROBE_EXTRAFIELDS },
         /* Ecamm Pico iMage */
         { .match_flags          = USB_DEVICE_ID_MATCH_DEVICE
                                 | USB_DEVICE_ID_MATCH_INT_INFO,
@@ -1945,6 +1935,15 @@ static struct usb_device_id uvc_ids[] = {
           .bInterfaceSubClass   = 1,
           .bInterfaceProtocol   = 0,
           .driver_info          = UVC_QUIRK_PROBE_EXTRAFIELDS },
+        /* FSC WebCam V30S */
+        { .match_flags          = USB_DEVICE_ID_MATCH_DEVICE
+                                | USB_DEVICE_ID_MATCH_INT_INFO,
+          .idVendor             = 0x18ec,
+          .idProduct            = 0x3288,
+          .bInterfaceClass      = USB_CLASS_VIDEO,
+          .bInterfaceSubClass   = 1,
+          .bInterfaceProtocol   = 0,
+          .driver_info          = UVC_QUIRK_PROBE_MINMAX },
         /* Bodelin ProScopeHR */
         { .match_flags          = USB_DEVICE_ID_MATCH_DEVICE
                                 | USB_DEVICE_ID_MATCH_DEV_HI
@@ -1965,8 +1964,7 @@ static struct usb_device_id uvc_ids[] = {
           .bInterfaceSubClass   = 1,
           .bInterfaceProtocol   = 0,
           .driver_info          = UVC_QUIRK_PROBE_MINMAX
-                                | UVC_QUIRK_IGNORE_SELECTOR_UNIT
-                                | UVC_QUIRK_PRUNE_CONTROLS },
+                                | UVC_QUIRK_IGNORE_SELECTOR_UNIT },
         /* Generic USB Video Class */
         { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, 0) },
         {}
diff --git a/drivers/media/video/uvc/uvc_queue.c b/drivers/media/video/uvc/uvc_queue.c
index 0155752e4a5a..f854698c4061 100644
--- a/drivers/media/video/uvc/uvc_queue.c
+++ b/drivers/media/video/uvc/uvc_queue.c
@@ -172,6 +172,20 @@ int uvc_free_buffers(struct uvc_video_queue *queue)
         return 0;
 }
 
+/*
+ * Check if buffers have been allocated.
+ */
+int uvc_queue_allocated(struct uvc_video_queue *queue)
+{
+        int allocated;
+
+        mutex_lock(&queue->mutex);
+        allocated = queue->count != 0;
+        mutex_unlock(&queue->mutex);
+
+        return allocated;
+}
+
 static void __uvc_query_buffer(struct uvc_buffer *buf,
                 struct v4l2_buffer *v4l2_buf)
 {
diff --git a/drivers/media/video/uvc/uvc_status.c b/drivers/media/video/uvc/uvc_status.c
index 21d87124986b..f152a9903862 100644
--- a/drivers/media/video/uvc/uvc_status.c
+++ b/drivers/media/video/uvc/uvc_status.c
@@ -194,7 +194,7 @@ int uvc_status_init(struct uvc_device *dev)
                 dev->status, UVC_MAX_STATUS_SIZE, uvc_status_complete,
                 dev, interval);
 
-        return usb_submit_urb(dev->int_urb, GFP_KERNEL);
+        return 0;
 }
 
 void uvc_status_cleanup(struct uvc_device *dev)
@@ -205,15 +205,30 @@ void uvc_status_cleanup(struct uvc_device *dev)
         uvc_input_cleanup(dev);
 }
 
-int uvc_status_suspend(struct uvc_device *dev)
+int uvc_status_start(struct uvc_device *dev)
+{
+        if (dev->int_urb == NULL)
+                return 0;
+
+        return usb_submit_urb(dev->int_urb, GFP_KERNEL);
+}
+
+void uvc_status_stop(struct uvc_device *dev)
 {
         usb_kill_urb(dev->int_urb);
+}
+
+int uvc_status_suspend(struct uvc_device *dev)
+{
+        if (atomic_read(&dev->users))
+                usb_kill_urb(dev->int_urb);
+
         return 0;
 }
 
 int uvc_status_resume(struct uvc_device *dev)
 {
-        if (dev->int_urb == NULL)
+        if (dev->int_urb == NULL || atomic_read(&dev->users) == 0)
                 return 0;
 
         return usb_submit_urb(dev->int_urb, GFP_NOIO);
diff --git a/drivers/media/video/uvc/uvc_v4l2.c b/drivers/media/video/uvc/uvc_v4l2.c
index 2a80caa54fb4..5e77cad29690 100644
--- a/drivers/media/video/uvc/uvc_v4l2.c
+++ b/drivers/media/video/uvc/uvc_v4l2.c
@@ -46,6 +46,8 @@ static int uvc_v4l2_query_menu(struct uvc_video_device *video,
         struct uvc_menu_info *menu_info;
         struct uvc_control_mapping *mapping;
         struct uvc_control *ctrl;
+        u32 index = query_menu->index;
+        u32 id = query_menu->id;
 
         ctrl = uvc_find_control(video, query_menu->id, &mapping);
         if (ctrl == NULL || mapping->v4l2_type != V4L2_CTRL_TYPE_MENU)
@@ -54,6 +56,10 @@ static int uvc_v4l2_query_menu(struct uvc_video_device *video,
         if (query_menu->index >= mapping->menu_count)
                 return -EINVAL;
 
+        memset(query_menu, 0, sizeof(*query_menu));
+        query_menu->id = id;
+        query_menu->index = index;
+
         menu_info = &mapping->menu_info[query_menu->index];
         strlcpy(query_menu->name, menu_info->name, sizeof query_menu->name);
         return 0;
@@ -245,7 +251,7 @@ static int uvc_v4l2_set_format(struct uvc_video_device *video,
         if (fmt->type != video->streaming->type)
                 return -EINVAL;
 
-        if (uvc_queue_streaming(&video->queue))
+        if (uvc_queue_allocated(&video->queue))
                 return -EBUSY;
 
         ret = uvc_v4l2_try_format(video, fmt, &probe, &format, &frame);
@@ -433,6 +439,15 @@ static int uvc_v4l2_open(struct file *file)
                 goto done;
         }
 
+        if (atomic_inc_return(&video->dev->users) == 1) {
+                if ((ret = uvc_status_start(video->dev)) < 0) {
+                        usb_autopm_put_interface(video->dev->intf);
+                        atomic_dec(&video->dev->users);
+                        kfree(handle);
+                        goto done;
+                }
+        }
+
         handle->device = video;
         handle->state = UVC_HANDLE_PASSIVE;
         file->private_data = handle;
@@ -467,6 +482,9 @@ static int uvc_v4l2_release(struct file *file)
         kfree(handle);
         file->private_data = NULL;
 
+        if (atomic_dec_return(&video->dev->users) == 0)
+                uvc_status_stop(video->dev);
+
         usb_autopm_put_interface(video->dev->intf);
         kref_put(&video->dev->kref, uvc_delete);
         return 0;
@@ -512,7 +530,10 @@ static long uvc_v4l2_do_ioctl(struct file *file, unsigned int cmd, void *arg)
                 memset(&xctrl, 0, sizeof xctrl);
                 xctrl.id = ctrl->id;
 
-                uvc_ctrl_begin(video);
+               ret = uvc_ctrl_begin(video);
+               if (ret < 0)
+                        return ret;
+
                 ret = uvc_ctrl_get(video, &xctrl);
                 uvc_ctrl_rollback(video);
                 if (ret >= 0)
@@ -529,7 +550,10 @@ static long uvc_v4l2_do_ioctl(struct file *file, unsigned int cmd, void *arg)
                 xctrl.id = ctrl->id;
                 xctrl.value = ctrl->value;
 
-                uvc_ctrl_begin(video);
+               ret = uvc_ctrl_begin(video);
+               if (ret < 0)
+                        return ret;
+
                 ret = uvc_ctrl_set(video, &xctrl);
                 if (ret < 0) {
                         uvc_ctrl_rollback(video);
@@ -548,7 +572,10 @@ static long uvc_v4l2_do_ioctl(struct file *file, unsigned int cmd, void *arg)
                 struct v4l2_ext_control *ctrl = ctrls->controls;
                 unsigned int i;
 
-                uvc_ctrl_begin(video);
+               ret = uvc_ctrl_begin(video);
+               if (ret < 0)
+                        return ret;
+
                 for (i = 0; i < ctrls->count; ++ctrl, ++i) {
                         ret = uvc_ctrl_get(video, ctrl);
                         if (ret < 0) {
@@ -648,7 +675,7 @@ static long uvc_v4l2_do_ioctl(struct file *file, unsigned int cmd, void *arg)
 
         case VIDIOC_S_INPUT:
         {
-                u8 input = *(u32 *)arg + 1;
+                u32 input = *(u32 *)arg + 1;
 
                 if ((ret = uvc_acquire_privileges(handle)) < 0)
                         return ret;
@@ -660,7 +687,7 @@ static long uvc_v4l2_do_ioctl(struct file *file, unsigned int cmd, void *arg)
                         break;
                 }
 
-                if (input > video->selector->selector.bNrInPins)
+                if (input == 0 || input > video->selector->selector.bNrInPins)
                         return -EINVAL;
 
                 return uvc_query_ctrl(video->dev, SET_CUR, video->selector->id,
diff --git a/drivers/media/video/uvc/uvc_video.c b/drivers/media/video/uvc/uvc_video.c
index 6ce974d7362f..01b633c73480 100644
--- a/drivers/media/video/uvc/uvc_video.c
+++ b/drivers/media/video/uvc/uvc_video.c
@@ -65,7 +65,8 @@ static void uvc_fixup_video_ctrl(struct uvc_video_device *video,
         struct uvc_streaming_control *ctrl)
 {
         struct uvc_format *format;
-        struct uvc_frame *frame;
+        struct uvc_frame *frame = NULL;
+        unsigned int i;
 
         if (ctrl->bFormatIndex <= 0 ||
             ctrl->bFormatIndex > video->streaming->nformats)
@@ -73,11 +74,15 @@ static void uvc_fixup_video_ctrl(struct uvc_video_device *video,
 
         format = &video->streaming->format[ctrl->bFormatIndex - 1];
 
-        if (ctrl->bFrameIndex <= 0 ||
-            ctrl->bFrameIndex > format->nframes)
-                return;
+        for (i = 0; i < format->nframes; ++i) {
+                if (format->frame[i].bFrameIndex == ctrl->bFrameIndex) {
+                        frame = &format->frame[i];
+                        break;
+                }
+        }
 
-        frame = &format->frame[ctrl->bFrameIndex - 1];
+        if (frame == NULL)
+                return;
 
         if (!(format->flags & UVC_FMT_FLAG_COMPRESSED) ||
              (ctrl->dwMaxVideoFrameSize == 0 &&
@@ -1089,7 +1094,7 @@ int uvc_video_init(struct uvc_video_device *video)
         /* Zero bFrameIndex might be correct. Stream-based formats (including
          * MPEG-2 TS and DV) do not support frames but have a dummy frame
          * descriptor with bFrameIndex set to zero. If the default frame
-         * descriptor is not found, use the first avalable frame.
+         * descriptor is not found, use the first available frame.
          */
         for (i = format->nframes; i > 0; --i) {
                 frame = &format->frame[i-1];
diff --git a/drivers/media/video/uvc/uvcvideo.h b/drivers/media/video/uvc/uvcvideo.h
index e5014e668f99..3c78d3c1e4c0 100644
--- a/drivers/media/video/uvc/uvcvideo.h
+++ b/drivers/media/video/uvc/uvcvideo.h
@@ -313,7 +313,6 @@ struct uvc_xu_control {
 #define UVC_QUIRK_BUILTIN_ISIGHT        0x00000008
 #define UVC_QUIRK_STREAM_NO_FID         0x00000010
 #define UVC_QUIRK_IGNORE_SELECTOR_UNIT  0x00000020
-#define UVC_QUIRK_PRUNE_CONTROLS        0x00000040
 #define UVC_QUIRK_FIX_BANDWIDTH         0x00000080
 
 /* Format flags */
@@ -634,6 +633,7 @@ struct uvc_device {
         enum uvc_device_state state;
         struct kref kref;
         struct list_head list;
+        atomic_t users;
 
         /* Video control interface */
         __u16 uvc_version;
@@ -747,6 +747,7 @@ extern struct uvc_buffer *uvc_queue_next_buffer(struct uvc_video_queue *queue,
                 struct uvc_buffer *buf);
 extern unsigned int uvc_queue_poll(struct uvc_video_queue *queue,
                 struct file *file, poll_table *wait);
+extern int uvc_queue_allocated(struct uvc_video_queue *queue);
 static inline int uvc_queue_streaming(struct uvc_video_queue *queue)
 {
         return queue->flags & UVC_QUEUE_STREAMING;
@@ -770,6 +771,8 @@ extern int uvc_query_ctrl(struct uvc_device *dev, __u8 query, __u8 unit,
 /* Status */
 extern int uvc_status_init(struct uvc_device *dev);
 extern void uvc_status_cleanup(struct uvc_device *dev);
+extern int uvc_status_start(struct uvc_device *dev);
+extern void uvc_status_stop(struct uvc_device *dev);
 extern int uvc_status_suspend(struct uvc_device *dev);
 extern int uvc_status_resume(struct uvc_device *dev);
 
diff --git a/drivers/media/video/v4l2-common.c b/drivers/media/video/v4l2-common.c
index f576ef66b807..f96475626da7 100644
--- a/drivers/media/video/v4l2-common.c
+++ b/drivers/media/video/v4l2-common.c
@@ -746,6 +746,7 @@ void v4l2_i2c_subdev_init(struct v4l2_subdev *sd, struct i2c_client *client,
                 const struct v4l2_subdev_ops *ops)
 {
         v4l2_subdev_init(sd, ops);
+        sd->flags |= V4L2_SUBDEV_FL_IS_I2C;
         /* the owner is the same as the i2c_client's driver owner */
         sd->owner = client->driver->driver.owner;
         /* i2c_client and v4l2_subdev point to one another */
@@ -897,8 +898,7 @@ const unsigned short *v4l2_i2c_tuner_addrs(enum v4l2_i2c_tuner_type type)
         };
         static const unsigned short tv_addrs[] = {
                 0x42, 0x43, 0x4a, 0x4b,         /* tda8290 */
-                0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
-                0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+                0x60, 0x61, 0x62, 0x63, 0x64,
                 I2C_CLIENT_END
         };
 
diff --git a/drivers/media/video/v4l2-device.c b/drivers/media/video/v4l2-device.c
index 94aa485ade52..0d06e7cbd5b3 100644
--- a/drivers/media/video/v4l2-device.c
+++ b/drivers/media/video/v4l2-device.c
@@ -49,6 +49,22 @@ int v4l2_device_register(struct device *dev, struct v4l2_device *v4l2_dev)
 }
 EXPORT_SYMBOL_GPL(v4l2_device_register);
 
+int v4l2_device_set_name(struct v4l2_device *v4l2_dev, const char *basename,
+                                                atomic_t *instance)
+{
+        int num = atomic_inc_return(instance) - 1;
+        int len = strlen(basename);
+
+        if (basename[len - 1] >= '0' && basename[len - 1] <= '9')
+                snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
+                                "%s-%d", basename, num);
+        else
+                snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
+                                "%s%d", basename, num);
+        return num;
+}
+EXPORT_SYMBOL_GPL(v4l2_device_set_name);
+
 void v4l2_device_disconnect(struct v4l2_device *v4l2_dev)
 {
         if (v4l2_dev->dev) {
@@ -67,8 +83,21 @@ void v4l2_device_unregister(struct v4l2_device *v4l2_dev)
         v4l2_device_disconnect(v4l2_dev);
 
         /* Unregister subdevs */
-        list_for_each_entry_safe(sd, next, &v4l2_dev->subdevs, list)
+        list_for_each_entry_safe(sd, next, &v4l2_dev->subdevs, list) {
                 v4l2_device_unregister_subdev(sd);
+#if defined(CONFIG_I2C) || (defined(CONFIG_I2C_MODULE) && defined(MODULE))
+                if (sd->flags & V4L2_SUBDEV_FL_IS_I2C) {
+                        struct i2c_client *client = v4l2_get_subdevdata(sd);
+
+                        /* We need to unregister the i2c client explicitly.
+                           We cannot rely on i2c_del_adapter to always
+                           unregister clients for us, since if the i2c bus
+                           is a platform bus, then it is never deleted. */
+                        if (client)
+                                i2c_unregister_device(client);
+                }
+#endif
+        }
 }
 EXPORT_SYMBOL_GPL(v4l2_device_unregister);
 
diff --git a/drivers/media/video/videobuf-core.c b/drivers/media/video/videobuf-core.c
index b7b05842cf28..f1ccf98c0a6f 100644
--- a/drivers/media/video/videobuf-core.c
+++ b/drivers/media/video/videobuf-core.c
@@ -118,6 +118,7 @@ void videobuf_queue_core_init(struct videobuf_queue *q,
                          void *priv,
                          struct videobuf_qtype_ops *int_ops)
 {
+        BUG_ON(!q);
         memset(q, 0, sizeof(*q));
         q->irqlock   = irqlock;
         q->dev       = dev;
@@ -439,6 +440,7 @@ int videobuf_reqbufs(struct videobuf_queue *q,
         }
 
         req->count = retval;
+        retval = 0;
 
  done:
         mutex_unlock(&q->vb_lock);
@@ -454,7 +456,7 @@ int videobuf_querybuf(struct videobuf_queue *q, struct v4l2_buffer *b)
                 dprintk(1, "querybuf: Wrong type.\n");
                 goto done;
         }
-        if (unlikely(b->index < 0 || b->index >= VIDEO_MAX_FRAME)) {
+        if (unlikely(b->index >= VIDEO_MAX_FRAME)) {
                 dprintk(1, "querybuf: index out of range.\n");
                 goto done;
         }
@@ -495,7 +497,7 @@ int videobuf_qbuf(struct videobuf_queue *q,
                 dprintk(1, "qbuf: Wrong type.\n");
                 goto done;
         }
-        if (b->index < 0 || b->index >= VIDEO_MAX_FRAME) {
+        if (b->index >= VIDEO_MAX_FRAME) {
                 dprintk(1, "qbuf: index out of range.\n");
                 goto done;
         }
diff --git a/drivers/media/video/videobuf-dma-contig.c b/drivers/media/video/videobuf-dma-contig.c
index 6109fb5f34e2..d09ce83a9429 100644
--- a/drivers/media/video/videobuf-dma-contig.c
+++ b/drivers/media/video/videobuf-dma-contig.c
@@ -17,6 +17,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/mm.h>
+#include <linux/pagemap.h>
 #include <linux/dma-mapping.h>
 #include <media/videobuf-dma-contig.h>
 
@@ -25,6 +26,7 @@ struct videobuf_dma_contig_memory {
         void *vaddr;
         dma_addr_t dma_handle;
         unsigned long size;
+        int is_userptr;
 };
 
 #define MAGIC_DC_MEM 0x0733ac61
@@ -108,6 +110,82 @@ static struct vm_operations_struct videobuf_vm_ops = {
         .close    = videobuf_vm_close,
 };
 
+/**
+ * videobuf_dma_contig_user_put() - reset pointer to user space buffer
+ * @mem: per-buffer private videobuf-dma-contig data
+ *
+ * This function resets the user space pointer
+ */
+static void videobuf_dma_contig_user_put(struct videobuf_dma_contig_memory *mem)
+{
+        mem->is_userptr = 0;
+        mem->dma_handle = 0;
+        mem->size = 0;
+}
+
+/**
+ * videobuf_dma_contig_user_get() - setup user space memory pointer
+ * @mem: per-buffer private videobuf-dma-contig data
+ * @vb: video buffer to map
+ *
+ * This function validates and sets up a pointer to user space memory.
+ * Only physically contiguous pfn-mapped memory is accepted.
+ *
+ * Returns 0 if successful.
+ */
+static int videobuf_dma_contig_user_get(struct videobuf_dma_contig_memory *mem,
+                                        struct videobuf_buffer *vb)
+{
+        struct mm_struct *mm = current->mm;
+        struct vm_area_struct *vma;
+        unsigned long prev_pfn, this_pfn;
+        unsigned long pages_done, user_address;
+        int ret;
+
+        mem->size = PAGE_ALIGN(vb->size);
+        mem->is_userptr = 0;
+        ret = -EINVAL;
+
+        down_read(&mm->mmap_sem);
+
+        vma = find_vma(mm, vb->baddr);
+        if (!vma)
+                goto out_up;
+
+        if ((vb->baddr + mem->size) > vma->vm_end)
+                goto out_up;
+
+        pages_done = 0;
+        prev_pfn = 0; /* kill warning */
+        user_address = vb->baddr;
+
+        while (pages_done < (mem->size >> PAGE_SHIFT)) {
+                ret = follow_pfn(vma, user_address, &this_pfn);
+                if (ret)
+                        break;
+
+                if (pages_done == 0)
+                        mem->dma_handle = this_pfn << PAGE_SHIFT;
+                else if (this_pfn != (prev_pfn + 1))
+                        ret = -EFAULT;
+
+                if (ret)
+                        break;
+
+                prev_pfn = this_pfn;
+                user_address += PAGE_SIZE;
+                pages_done++;
+        }
+
+        if (!ret)
+                mem->is_userptr = 1;
+
+ out_up:
+        up_read(&current->mm->mmap_sem);
+
+        return ret;
+}
+
 static void *__videobuf_alloc(size_t size)
 {
         struct videobuf_dma_contig_memory *mem;
@@ -154,12 +232,11 @@ static int __videobuf_iolock(struct videobuf_queue *q,
         case V4L2_MEMORY_USERPTR:
                 dev_dbg(q->dev, "%s memory method USERPTR\n", __func__);
 
-                /* The only USERPTR currently supported is the one needed for
-                   read() method.
-                 */
+                /* handle pointer from user space */
                 if (vb->baddr)
-                        return -EINVAL;
+                        return videobuf_dma_contig_user_get(mem, vb);
 
+                /* allocate memory for the read() method */
                 mem->size = PAGE_ALIGN(vb->size);
                 mem->vaddr = dma_alloc_coherent(q->dev, mem->size,
                                                 &mem->dma_handle, GFP_KERNEL);
@@ -182,19 +259,6 @@ static int __videobuf_iolock(struct videobuf_queue *q,
         return 0;
 }
 
-static int __videobuf_sync(struct videobuf_queue *q,
-                           struct videobuf_buffer *buf)
-{
-        struct videobuf_dma_contig_memory *mem = buf->priv;
-
-        BUG_ON(!mem);
-        MAGIC_CHECK(mem->magic, MAGIC_DC_MEM);
-
-        dma_sync_single_for_cpu(q->dev, mem->dma_handle, mem->size,
-                                DMA_FROM_DEVICE);
-        return 0;
-}
-
 static int __videobuf_mmap_free(struct videobuf_queue *q)
 {
         unsigned int i;
@@ -356,7 +420,6 @@ static struct videobuf_qtype_ops qops = {
 
         .alloc        = __videobuf_alloc,
         .iolock       = __videobuf_iolock,
-        .sync         = __videobuf_sync,
         .mmap_free    = __videobuf_mmap_free,
         .mmap_mapper  = __videobuf_mmap_mapper,
         .video_copy_to_user = __videobuf_copy_to_user,
@@ -400,7 +463,7 @@ void videobuf_dma_contig_free(struct videobuf_queue *q,
            So, it should free memory only if the memory were allocated for
            read() operation.
          */
-        if ((buf->memory != V4L2_MEMORY_USERPTR) || buf->baddr)
+        if (buf->memory != V4L2_MEMORY_USERPTR)
                 return;
 
         if (!mem)
@@ -408,6 +471,13 @@ void videobuf_dma_contig_free(struct videobuf_queue *q,
 
         MAGIC_CHECK(mem->magic, MAGIC_DC_MEM);
 
+        /* handle user space pointer case */
+        if (buf->baddr) {
+                videobuf_dma_contig_user_put(mem);
+                return;
+        }
+
+        /* read() method */
         dma_free_coherent(q->dev, mem->size, mem->vaddr, mem->dma_handle);
         mem->vaddr = NULL;
 }
diff --git a/drivers/media/video/videobuf-dma-sg.c b/drivers/media/video/videobuf-dma-sg.c
index da1790e57a86..a8dd22ace3fb 100644
--- a/drivers/media/video/videobuf-dma-sg.c
+++ b/drivers/media/video/videobuf-dma-sg.c
@@ -58,9 +58,10 @@ videobuf_vmalloc_to_sg(unsigned char *virt, int nr_pages)
         struct page *pg;
         int i;
 
-        sglist = kcalloc(nr_pages, sizeof(struct scatterlist), GFP_KERNEL);
+        sglist = vmalloc(nr_pages * sizeof(*sglist));
         if (NULL == sglist)
                 return NULL;
+        memset(sglist, 0, nr_pages * sizeof(*sglist));
         sg_init_table(sglist, nr_pages);
         for (i = 0; i < nr_pages; i++, virt += PAGE_SIZE) {
                 pg = vmalloc_to_page(virt);
@@ -72,7 +73,7 @@ videobuf_vmalloc_to_sg(unsigned char *virt, int nr_pages)
         return sglist;
 
  err:
-        kfree(sglist);
+        vfree(sglist);
         return NULL;
 }
 
@@ -84,7 +85,7 @@ videobuf_pages_to_sg(struct page **pages, int nr_pages, int offset)
 
         if (NULL == pages[0])
                 return NULL;
-        sglist = kmalloc(nr_pages * sizeof(*sglist), GFP_KERNEL);
+        sglist = vmalloc(nr_pages * sizeof(*sglist));
         if (NULL == sglist)
                 return NULL;
         sg_init_table(sglist, nr_pages);
@@ -104,12 +105,12 @@ videobuf_pages_to_sg(struct page **pages, int nr_pages, int offset)
 
  nopage:
         dprintk(2,"sgl: oops - no page\n");
-        kfree(sglist);
+        vfree(sglist);
         return NULL;
 
  highmem:
         dprintk(2,"sgl: oops - highmem page\n");
-        kfree(sglist);
+        vfree(sglist);
         return NULL;
 }
 
@@ -230,7 +231,7 @@ int videobuf_dma_map(struct videobuf_queue* q, struct videobuf_dmabuf *dma)
                                                 (dma->vmalloc,dma->nr_pages);
         }
         if (dma->bus_addr) {
-                dma->sglist = kmalloc(sizeof(struct scatterlist), GFP_KERNEL);
+                dma->sglist = vmalloc(sizeof(*dma->sglist));
                 if (NULL != dma->sglist) {
                         dma->sglen  = 1;
                         sg_dma_address(&dma->sglist[0]) = dma->bus_addr & PAGE_MASK;
@@ -248,10 +249,10 @@ int videobuf_dma_map(struct videobuf_queue* q, struct videobuf_dmabuf *dma)
                 if (0 == dma->sglen) {
                         printk(KERN_WARNING
                                "%s: videobuf_map_sg failed\n",__func__);
-                        kfree(dma->sglist);
+                        vfree(dma->sglist);
                         dma->sglist = NULL;
                         dma->sglen = 0;
-                        return -EIO;
+                        return -ENOMEM;
                 }
         }
         return 0;
@@ -274,7 +275,7 @@ int videobuf_dma_unmap(struct videobuf_queue* q,struct videobuf_dmabuf *dma)
 
         dma_unmap_sg(q->dev, dma->sglist, dma->nr_pages, dma->direction);
 
-        kfree(dma->sglist);
+        vfree(dma->sglist);
         dma->sglist = NULL;
         dma->sglen = 0;
         return 0;
diff --git a/drivers/media/video/vino.c b/drivers/media/video/vino.c
index 43e0998adb53..97b082fe4473 100644
--- a/drivers/media/video/vino.c
+++ b/drivers/media/video/vino.c
@@ -868,9 +868,9 @@ static void vino_sync_buffer(struct vino_framebuffer *fb)
         dprintk("vino_sync_buffer():\n");
 
         for (i = 0; i < fb->desc_table.page_count; i++)
-                dma_sync_single(NULL,
-                                fb->desc_table.dma_cpu[VINO_PAGE_RATIO * i],
-                                PAGE_SIZE, DMA_FROM_DEVICE);
+                dma_sync_single_for_cpu(NULL,
+                                        fb->desc_table.dma_cpu[VINO_PAGE_RATIO * i],
+                                        PAGE_SIZE, DMA_FROM_DEVICE);
 }
 
 /* Framebuffer fifo functions (need to be locked externally) */
diff --git a/drivers/media/video/zoran/zoran_card.c b/drivers/media/video/zoran/zoran_card.c
index ea6c577b0eb3..03dc2f3cf84a 100644
--- a/drivers/media/video/zoran/zoran_card.c
+++ b/drivers/media/video/zoran/zoran_card.c
@@ -1022,7 +1022,7 @@ zr36057_init (struct zoran *zr)
         zr->vbuf_bytesperline = 0;
 
         /* Avoid nonsense settings from user for default input/norm */
-        if (default_norm < 0 && default_norm > 2)
+        if (default_norm < 0 || default_norm > 2)
                 default_norm = 0;
         if (default_norm == 0) {
                 zr->norm = V4L2_STD_PAL;
@@ -1477,7 +1477,7 @@ static struct pci_driver zoran_driver = {
         .name = "zr36067",
         .id_table = zr36067_pci_tbl,
         .probe = zoran_probe,
-        .remove = zoran_remove,
+        .remove = __devexit_p(zoran_remove),
 };
 
 static int __init zoran_init(void)
diff --git a/drivers/media/video/zr364xx.c b/drivers/media/video/zr364xx.c
index ac169c9eb18d..fc976f42f432 100644
--- a/drivers/media/video/zr364xx.c
+++ b/drivers/media/video/zr364xx.c
@@ -882,9 +882,11 @@ static void zr364xx_disconnect(struct usb_interface *intf)
                 video_unregister_device(cam->vdev);
         cam->vdev = NULL;
         kfree(cam->buffer);
-        if (cam->framebuf)
-                vfree(cam->framebuf);
+        cam->buffer = NULL;
+        vfree(cam->framebuf);
+        cam->framebuf = NULL;
         kfree(cam);
+        cam = NULL;
 }
 
 
diff --git a/drivers/mfd/htc-pasic3.c b/drivers/mfd/htc-pasic3.c
index 386da1566fcc..cb73051e43db 100644
--- a/drivers/mfd/htc-pasic3.c
+++ b/drivers/mfd/htc-pasic3.c
@@ -35,7 +35,7 @@ struct pasic3_data {
  */
 void pasic3_write_register(struct device *dev, u32 reg, u8 val)
 {
-        struct pasic3_data *asic = dev->driver_data;
+        struct pasic3_data *asic = dev_get_drvdata(dev);
         int bus_shift = asic->bus_shift;
         void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift);
         void __iomem *data = asic->mapping + (REG_DATA << bus_shift);
@@ -50,7 +50,7 @@ EXPORT_SYMBOL(pasic3_write_register); /* for leds-pasic3 */
  */
 u8 pasic3_read_register(struct device *dev, u32 reg)
 {
-        struct pasic3_data *asic = dev->driver_data;
+        struct pasic3_data *asic = dev_get_drvdata(dev);
         int bus_shift = asic->bus_shift;
         void __iomem *addr = asic->mapping + (REG_ADDR << bus_shift);
         void __iomem *data = asic->mapping + (REG_DATA << bus_shift);
diff --git a/drivers/mfd/pcf50633-core.c b/drivers/mfd/pcf50633-core.c
index 11a6248cc1c1..082c197ab9b8 100644
--- a/drivers/mfd/pcf50633-core.c
+++ b/drivers/mfd/pcf50633-core.c
@@ -618,7 +618,7 @@ static int __devinit pcf50633_probe(struct i2c_client *client,
 
                 pdev->dev.parent = pcf->dev;
                 pdev->dev.platform_data = &pdata->reg_init_data[i];
-                pdev->dev.driver_data = pcf;
+                dev_set_drvdata(&pdev->dev, pcf);
                 pcf->regulator_pdev[i] = pdev;
 
                 platform_device_add(pdev);
diff --git a/drivers/mfd/wm8400-core.c b/drivers/mfd/wm8400-core.c
index cf30d06a0104..7c21bf791569 100644
--- a/drivers/mfd/wm8400-core.c
+++ b/drivers/mfd/wm8400-core.c
@@ -265,7 +265,7 @@ static int wm8400_init(struct wm8400 *wm8400,
 
         mutex_init(&wm8400->io_lock);
 
-        wm8400->dev->driver_data = wm8400;
+        dev_set_drvdata(wm8400->dev, wm8400);
 
         /* Check that this is actually a WM8400 */
         ret = wm8400->read_dev(wm8400->io_data, WM8400_RESET_ID, 1, &reg);
diff --git a/drivers/misc/c2port/core.c b/drivers/misc/c2port/core.c
index 0207dd59090d..b5346b4db91a 100644
--- a/drivers/misc/c2port/core.c
+++ b/drivers/misc/c2port/core.c
@@ -15,6 +15,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/kernel.h>
+#include <linux/kmemcheck.h>
 #include <linux/ctype.h>
 #include <linux/delay.h>
 #include <linux/idr.h>
@@ -891,6 +892,7 @@ struct c2port_device *c2port_device_register(char *name,
                 return ERR_PTR(-EINVAL);
 
         c2dev = kmalloc(sizeof(struct c2port_device), GFP_KERNEL);
+        kmemcheck_annotate_bitfield(c2dev, flags);
         if (unlikely(!c2dev))
                 return ERR_PTR(-ENOMEM);
 
diff --git a/drivers/misc/sgi-gru/grufile.c b/drivers/misc/sgi-gru/grufile.c
index bbefe77c67a9..3ce2920e2bf3 100644
--- a/drivers/misc/sgi-gru/grufile.c
+++ b/drivers/misc/sgi-gru/grufile.c
@@ -302,7 +302,7 @@ static int gru_init_tables(unsigned long gru_base_paddr, void *gru_base_vaddr)
                 pnode = uv_node_to_pnode(nid);
                 if (bid < 0 || gru_base[bid])
                         continue;
-                page = alloc_pages_node(nid, GFP_KERNEL, order);
+                page = alloc_pages_exact_node(nid, GFP_KERNEL, order);
                 if (!page)
                         goto fail;
                 gru_base[bid] = page_address(page);
diff --git a/drivers/misc/sgi-xp/xpc_uv.c b/drivers/misc/sgi-xp/xpc_uv.c
index 9172fcdee4e2..c76677afda1b 100644
--- a/drivers/misc/sgi-xp/xpc_uv.c
+++ b/drivers/misc/sgi-xp/xpc_uv.c
@@ -232,7 +232,7 @@ xpc_create_gru_mq_uv(unsigned int mq_size, int cpu, char *irq_name,
         mq->mmr_blade = uv_cpu_to_blade_id(cpu);
 
         nid = cpu_to_node(cpu);
-        page = alloc_pages_node(nid, GFP_KERNEL | __GFP_ZERO | GFP_THISNODE,
+        page = alloc_pages_exact_node(nid, GFP_KERNEL | __GFP_ZERO | GFP_THISNODE,
                                 pg_order);
         if (page == NULL) {
                 dev_err(xpc_part, "xpc_create_gru_mq_uv() failed to alloc %d "
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 3f063108e95f..b1cd7a1a2191 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -49,15 +49,16 @@ config MTD_UBI_BEB_RESERVE
           reserved. Leave the default value if unsure.
 
 config MTD_UBI_GLUEBI
-        bool "Emulate MTD devices"
+        tristate "MTD devices emulation driver (gluebi)"
         default n
         depends on MTD_UBI
         help
-           This option enables MTD devices emulation on top of UBI volumes: for
-           each UBI volumes an MTD device is created, and all I/O to this MTD
-           device is redirected to the UBI volume. This is handy to make
-           MTD-oriented software (like JFFS2) work on top of UBI. Do not enable
-           this if no legacy software will be used.
+           This option enables gluebi - an additional driver which emulates MTD
+           devices on top of UBI volumes: for each UBI volumes an MTD device is
+           created, and all I/O to this MTD device is redirected to the UBI
+           volume. This is handy to make MTD-oriented software (like JFFS2)
+           work on top of UBI. Do not enable this unless you use legacy
+           software.
 
 source "drivers/mtd/ubi/Kconfig.debug"
 endmenu
diff --git a/drivers/mtd/ubi/Makefile b/drivers/mtd/ubi/Makefile
index dd834e04151b..c9302a5452b0 100644
--- a/drivers/mtd/ubi/Makefile
+++ b/drivers/mtd/ubi/Makefile
@@ -4,4 +4,4 @@ ubi-y += vtbl.o vmt.o upd.o build.o cdev.o kapi.o eba.o io.o wl.o scan.o
 ubi-y += misc.o
 
 ubi-$(CONFIG_MTD_UBI_DEBUG) += debug.o
-ubi-$(CONFIG_MTD_UBI_GLUEBI) += gluebi.o
+obj-$(CONFIG_MTD_UBI_GLUEBI) += gluebi.o
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 4048db83aef6..286ed594e5a0 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -41,6 +41,7 @@
 #include <linux/miscdevice.h>
 #include <linux/log2.h>
 #include <linux/kthread.h>
+#include <linux/reboot.h>
 #include "ubi.h"
 
 /* Maximum length of the 'mtd=' parameter */
@@ -122,6 +123,94 @@ static struct device_attribute dev_mtd_num =
         __ATTR(mtd_num, S_IRUGO, dev_attribute_show, NULL);
 
 /**
+ * ubi_volume_notify - send a volume change notification.
+ * @ubi: UBI device description object
+ * @vol: volume description object of the changed volume
+ * @ntype: notification type to send (%UBI_VOLUME_ADDED, etc)
+ *
+ * This is a helper function which notifies all subscribers about a volume
+ * change event (creation, removal, re-sizing, re-naming, updating). Returns
+ * zero in case of success and a negative error code in case of failure.
+ */
+int ubi_volume_notify(struct ubi_device *ubi, struct ubi_volume *vol, int ntype)
+{
+        struct ubi_notification nt;
+
+        ubi_do_get_device_info(ubi, &nt.di);
+        ubi_do_get_volume_info(ubi, vol, &nt.vi);
+        return blocking_notifier_call_chain(&ubi_notifiers, ntype, &nt);
+}
+
+/**
+ * ubi_notify_all - send a notification to all volumes.
+ * @ubi: UBI device description object
+ * @ntype: notification type to send (%UBI_VOLUME_ADDED, etc)
+ * @nb: the notifier to call
+ *
+ * This function walks all volumes of UBI device @ubi and sends the @ntype
+ * notification for each volume. If @nb is %NULL, then all registered notifiers
+ * are called, otherwise only the @nb notifier is called. Returns the number of
+ * sent notifications.
+ */
+int ubi_notify_all(struct ubi_device *ubi, int ntype, struct notifier_block *nb)
+{
+        struct ubi_notification nt;
+        int i, count = 0;
+
+        ubi_do_get_device_info(ubi, &nt.di);
+
+        mutex_lock(&ubi->device_mutex);
+        for (i = 0; i < ubi->vtbl_slots; i++) {
+                /*
+                 * Since the @ubi->device is locked, and we are not going to
+                 * change @ubi->volumes, we do not have to lock
+                 * @ubi->volumes_lock.
+                 */
+                if (!ubi->volumes[i])
+                        continue;
+
+                ubi_do_get_volume_info(ubi, ubi->volumes[i], &nt.vi);
+                if (nb)
+                        nb->notifier_call(nb, ntype, &nt);
+                else
+                        blocking_notifier_call_chain(&ubi_notifiers, ntype,
+                                                     &nt);
+                count += 1;
+        }
+        mutex_unlock(&ubi->device_mutex);
+
+        return count;
+}
+
+/**
+ * ubi_enumerate_volumes - send "add" notification for all existing volumes.
+ * @nb: the notifier to call
+ *
+ * This function walks all UBI devices and volumes and sends the
+ * %UBI_VOLUME_ADDED notification for each volume. If @nb is %NULL, then all
+ * registered notifiers are called, otherwise only the @nb notifier is called.
+ * Returns the number of sent notifications.
+ */
+int ubi_enumerate_volumes(struct notifier_block *nb)
+{
+        int i, count = 0;
+
+        /*
+         * Since the @ubi_devices_mutex is locked, and we are not going to
+         * change @ubi_devices, we do not have to lock @ubi_devices_lock.
+         */
+        for (i = 0; i < UBI_MAX_DEVICES; i++) {
+                struct ubi_device *ubi = ubi_devices[i];
+
+                if (!ubi)
+                        continue;
+                count += ubi_notify_all(ubi, UBI_VOLUME_ADDED, nb);
+        }
+
+        return count;
+}
+
+/**
  * ubi_get_device - get UBI device.
  * @ubi_num: UBI device number
  *
@@ -380,7 +469,7 @@ static void free_user_volumes(struct ubi_device *ubi)
  * @ubi: UBI device description object
  *
  * This function returns zero in case of success and a negative error code in
- * case of failure. Note, this function destroys all volumes if it failes.
+ * case of failure. Note, this function destroys all volumes if it fails.
  */
 static int uif_init(struct ubi_device *ubi)
 {
@@ -633,6 +722,15 @@ static int io_init(struct ubi_device *ubi)
         }
 
         /*
+         * Set maximum amount of physical erroneous eraseblocks to be 10%.
+         * Erroneous PEB are those which have read errors.
+         */
+        ubi->max_erroneous = ubi->peb_count / 10;
+        if (ubi->max_erroneous < 16)
+                ubi->max_erroneous = 16;
+        dbg_msg("max_erroneous    %d", ubi->max_erroneous);
+
+        /*
          * It may happen that EC and VID headers are situated in one minimal
          * I/O unit. In this case we can only accept this UBI image in
          * read-only mode.
@@ -726,6 +824,34 @@ static int autoresize(struct ubi_device *ubi, int vol_id)
 }
 
 /**
+ * ubi_reboot_notifier - halt UBI transactions immediately prior to a reboot.
+ * @n: reboot notifier object
+ * @state: SYS_RESTART, SYS_HALT, or SYS_POWER_OFF
+ * @cmd: pointer to command string for RESTART2
+ *
+ * This function stops the UBI background thread so that the flash device
+ * remains quiescent when Linux restarts the system. Any queued work will be
+ * discarded, but this function will block until do_work() finishes if an
+ * operation is already in progress.
+ *
+ * This function solves a real-life problem observed on NOR flashes when an
+ * PEB erase operation starts, then the system is rebooted before the erase is
+ * finishes, and the boot loader gets confused and dies. So we prefer to finish
+ * the ongoing operation before rebooting.
+ */
+static int ubi_reboot_notifier(struct notifier_block *n, unsigned long state,
+                               void *cmd)
+{
+        struct ubi_device *ubi;
+
+        ubi = container_of(n, struct ubi_device, reboot_notifier);
+        if (ubi->bgt_thread)
+                kthread_stop(ubi->bgt_thread);
+        ubi_sync(ubi->ubi_num);
+        return NOTIFY_DONE;
+}
+
+/**
  * ubi_attach_mtd_dev - attach an MTD device.
  * @mtd: MTD device description object
  * @ubi_num: number to assign to the new UBI device
@@ -806,8 +932,7 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset)
 
         mutex_init(&ubi->buf_mutex);
         mutex_init(&ubi->ckvol_mutex);
-        mutex_init(&ubi->mult_mutex);
-        mutex_init(&ubi->volumes_mutex);
+        mutex_init(&ubi->device_mutex);
         spin_lock_init(&ubi->volumes_lock);
 
         ubi_msg("attaching mtd%d to ubi%d", mtd->index, ubi_num);
@@ -825,7 +950,7 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset)
         if (!ubi->peb_buf2)
                 goto out_free;
 
-#ifdef CONFIG_MTD_UBI_DEBUG
+#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID
         mutex_init(&ubi->dbg_buf_mutex);
         ubi->dbg_peb_buf = vmalloc(ubi->peb_size);
         if (!ubi->dbg_peb_buf)
@@ -872,11 +997,23 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, int vid_hdr_offset)
                 ubi->beb_rsvd_pebs);
         ubi_msg("max/mean erase counter: %d/%d", ubi->max_ec, ubi->mean_ec);
 
+        /*
+         * The below lock makes sure we do not race with 'ubi_thread()' which
+         * checks @ubi->thread_enabled. Otherwise we may fail to wake it up.
+         */
+        spin_lock(&ubi->wl_lock);
         if (!DBG_DISABLE_BGT)
                 ubi->thread_enabled = 1;
         wake_up_process(ubi->bgt_thread);
+        spin_unlock(&ubi->wl_lock);
+
+        /* Flash device priority is 0 - UBI needs to shut down first */
+        ubi->reboot_notifier.priority = 1;
+        ubi->reboot_notifier.notifier_call = ubi_reboot_notifier;
+        register_reboot_notifier(&ubi->reboot_notifier);
 
         ubi_devices[ubi_num] = ubi;
+        ubi_notify_all(ubi, UBI_VOLUME_ADDED, NULL);
         return ubi_num;
 
 out_uif:
@@ -892,7 +1029,7 @@ out_detach:
 out_free:
         vfree(ubi->peb_buf1);
         vfree(ubi->peb_buf2);
-#ifdef CONFIG_MTD_UBI_DEBUG
+#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID
         vfree(ubi->dbg_peb_buf);
 #endif
         kfree(ubi);
@@ -919,13 +1056,13 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway)
         if (ubi_num < 0 || ubi_num >= UBI_MAX_DEVICES)
                 return -EINVAL;
 
-        spin_lock(&ubi_devices_lock);
-        ubi = ubi_devices[ubi_num];
-        if (!ubi) {
-                spin_unlock(&ubi_devices_lock);
+        ubi = ubi_get_device(ubi_num);
+        if (!ubi)
                 return -EINVAL;
-        }
 
+        spin_lock(&ubi_devices_lock);
+        put_device(&ubi->dev);
+        ubi->ref_count -= 1;
         if (ubi->ref_count) {
                 if (!anyway) {
                         spin_unlock(&ubi_devices_lock);
@@ -939,12 +1076,14 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway)
         spin_unlock(&ubi_devices_lock);
 
         ubi_assert(ubi_num == ubi->ubi_num);
+        ubi_notify_all(ubi, UBI_VOLUME_REMOVED, NULL);
         dbg_msg("detaching mtd%d from ubi%d", ubi->mtd->index, ubi_num);
 
         /*
          * Before freeing anything, we have to stop the background thread to
          * prevent it from doing anything on this device while we are freeing.
          */
+        unregister_reboot_notifier(&ubi->reboot_notifier);
         if (ubi->bgt_thread)
                 kthread_stop(ubi->bgt_thread);
 
@@ -961,7 +1100,7 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway)
         put_mtd_device(ubi->mtd);
         vfree(ubi->peb_buf1);
         vfree(ubi->peb_buf2);
-#ifdef CONFIG_MTD_UBI_DEBUG
+#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID
         vfree(ubi->dbg_peb_buf);
 #endif
         ubi_msg("mtd%d is detached from ubi%d", ubi->mtd->index, ubi->ubi_num);
diff --git a/drivers/mtd/ubi/cdev.c b/drivers/mtd/ubi/cdev.c
index f8e0f68f2186..f237ddbb2713 100644
--- a/drivers/mtd/ubi/cdev.c
+++ b/drivers/mtd/ubi/cdev.c
@@ -113,7 +113,8 @@ static int vol_cdev_open(struct inode *inode, struct file *file)
         else
                 mode = UBI_READONLY;
 
-        dbg_gen("open volume %d, mode %d", vol_id, mode);
+        dbg_gen("open device %d, volume %d, mode %d",
+                ubi_num, vol_id, mode);
 
         desc = ubi_open_volume(ubi_num, vol_id, mode);
         if (IS_ERR(desc))
@@ -128,7 +129,8 @@ static int vol_cdev_release(struct inode *inode, struct file *file)
         struct ubi_volume_desc *desc = file->private_data;
         struct ubi_volume *vol = desc->vol;
 
-        dbg_gen("release volume %d, mode %d", vol->vol_id, desc->mode);
+        dbg_gen("release device %d, volume %d, mode %d",
+                vol->ubi->ubi_num, vol->vol_id, desc->mode);
 
         if (vol->updating) {
                 ubi_warn("update of volume %d not finished, volume is damaged",
@@ -393,7 +395,7 @@ static ssize_t vol_cdev_write(struct file *file, const char __user *buf,
                         vol->corrupted = 1;
                 }
                 vol->checked = 1;
-                ubi_gluebi_updated(vol);
+                ubi_volume_notify(ubi, vol, UBI_VOLUME_UPDATED);
                 revoke_exclusive(desc, UBI_READWRITE);
         }
 
@@ -558,7 +560,7 @@ static long vol_cdev_ioctl(struct file *file, unsigned int cmd,
                 break;
         }
 
-        /* Set volume property command*/
+        /* Set volume property command */
         case UBI_IOCSETPROP:
         {
                 struct ubi_set_prop_req req;
@@ -571,9 +573,9 @@ static long vol_cdev_ioctl(struct file *file, unsigned int cmd,
                 }
                 switch (req.property) {
                 case UBI_PROP_DIRECT_WRITE:
-                        mutex_lock(&ubi->volumes_mutex);
+                        mutex_lock(&ubi->device_mutex);
                         desc->vol->direct_writes = !!req.value;
-                        mutex_unlock(&ubi->volumes_mutex);
+                        mutex_unlock(&ubi->device_mutex);
                         break;
                 default:
                         err = -EINVAL;
@@ -810,9 +812,9 @@ static int rename_volumes(struct ubi_device *ubi,
                         re->desc->vol->vol_id, re->desc->vol->name);
         }
 
-        mutex_lock(&ubi->volumes_mutex);
+        mutex_lock(&ubi->device_mutex);
         err = ubi_rename_volumes(ubi, &rename_list);
-        mutex_unlock(&ubi->volumes_mutex);
+        mutex_unlock(&ubi->device_mutex);
 
 out_free:
         list_for_each_entry_safe(re, re1, &rename_list, list) {
@@ -856,9 +858,9 @@ static long ubi_cdev_ioctl(struct file *file, unsigned int cmd,
                 if (err)
                         break;
 
-                mutex_lock(&ubi->volumes_mutex);
+                mutex_lock(&ubi->device_mutex);
                 err = ubi_create_volume(ubi, &req);
-                mutex_unlock(&ubi->volumes_mutex);
+                mutex_unlock(&ubi->device_mutex);
                 if (err)
                         break;
 
@@ -887,9 +889,9 @@ static long ubi_cdev_ioctl(struct file *file, unsigned int cmd,
                         break;
                 }
 
-                mutex_lock(&ubi->volumes_mutex);
+                mutex_lock(&ubi->device_mutex);
                 err = ubi_remove_volume(desc, 0);
-                mutex_unlock(&ubi->volumes_mutex);
+                mutex_unlock(&ubi->device_mutex);
 
                 /*
                  * The volume is deleted (unless an error occurred), and the
@@ -926,9 +928,9 @@ static long ubi_cdev_ioctl(struct file *file, unsigned int cmd,
                 pebs = div_u64(req.bytes + desc->vol->usable_leb_size - 1,
                                desc->vol->usable_leb_size);
 
-                mutex_lock(&ubi->volumes_mutex);
+                mutex_lock(&ubi->device_mutex);
                 err = ubi_resize_volume(desc, pebs);
-                mutex_unlock(&ubi->volumes_mutex);
+                mutex_unlock(&ubi->device_mutex);
                 ubi_close_volume(desc);
                 break;
         }
@@ -952,9 +954,7 @@ static long ubi_cdev_ioctl(struct file *file, unsigned int cmd,
                         break;
                 }
 
-                mutex_lock(&ubi->mult_mutex);
                 err = rename_volumes(ubi, req);
-                mutex_unlock(&ubi->mult_mutex);
                 kfree(req);
                 break;
         }
diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index 25def348e5ba..0f2034c3ed2f 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -419,8 +419,9 @@ retry:
                                  * not implemented.
                                  */
                                 if (err == UBI_IO_BAD_VID_HDR) {
-                                        ubi_warn("bad VID header at PEB %d, LEB"
-                                                 "%d:%d", pnum, vol_id, lnum);
+                                        ubi_warn("corrupted VID header at PEB "
+                                                 "%d, LEB %d:%d", pnum, vol_id,
+                                                 lnum);
                                         err = -EBADMSG;
                                 } else
                                         ubi_ro_mode(ubi);
@@ -940,6 +941,33 @@ write_error:
 }
 
 /**
+ * is_error_sane - check whether a read error is sane.
+ * @err: code of the error happened during reading
+ *
+ * This is a helper function for 'ubi_eba_copy_leb()' which is called when we
+ * cannot read data from the target PEB (an error @err happened). If the error
+ * code is sane, then we treat this error as non-fatal. Otherwise the error is
+ * fatal and UBI will be switched to R/O mode later.
+ *
+ * The idea is that we try not to switch to R/O mode if the read error is
+ * something which suggests there was a real read problem. E.g., %-EIO. Or a
+ * memory allocation failed (-%ENOMEM). Otherwise, it is safer to switch to R/O
+ * mode, simply because we do not know what happened at the MTD level, and we
+ * cannot handle this. E.g., the underlying driver may have become crazy, and
+ * it is safer to switch to R/O mode to preserve the data.
+ *
+ * And bear in mind, this is about reading from the target PEB, i.e. the PEB
+ * which we have just written.
+ */
+static int is_error_sane(int err)
+{
+        if (err == -EIO || err == -ENOMEM || err == UBI_IO_BAD_VID_HDR ||
+            err == -ETIMEDOUT)
+                return 0;
+        return 1;
+}
+
+/**
  * ubi_eba_copy_leb - copy logical eraseblock.
  * @ubi: UBI device description object
  * @from: physical eraseblock number from where to copy
@@ -950,12 +978,7 @@ write_error:
  * physical eraseblock @to. The @vid_hdr buffer may be changed by this
  * function. Returns:
  *   o %0 in case of success;
- *   o %1 if the operation was canceled because the volume is being deleted
- *        or because the PEB was put meanwhile;
- *   o %2 if the operation was canceled because there was a write error to the
- *        target PEB;
- *   o %-EAGAIN if the operation was canceled because a bit-flip was detected
- *     in the target PEB;
+ *   o %MOVE_CANCEL_RACE, %MOVE_TARGET_WR_ERR, %MOVE_CANCEL_BITFLIPS, etc;
  *   o a negative error code in case of failure.
  */
 int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
@@ -968,7 +991,7 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
         vol_id = be32_to_cpu(vid_hdr->vol_id);
         lnum = be32_to_cpu(vid_hdr->lnum);
 
-        dbg_eba("copy LEB %d:%d, PEB %d to PEB %d", vol_id, lnum, from, to);
+        dbg_wl("copy LEB %d:%d, PEB %d to PEB %d", vol_id, lnum, from, to);
 
         if (vid_hdr->vol_type == UBI_VID_STATIC) {
                 data_size = be32_to_cpu(vid_hdr->data_size);
@@ -986,13 +1009,12 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
          * be locked in 'ubi_wl_put_peb()' and wait for the WL worker to finish.
          */
         vol = ubi->volumes[idx];
+        spin_unlock(&ubi->volumes_lock);
         if (!vol) {
                 /* No need to do further work, cancel */
-                dbg_eba("volume %d is being removed, cancel", vol_id);
-                spin_unlock(&ubi->volumes_lock);
-                return 1;
+                dbg_wl("volume %d is being removed, cancel", vol_id);
+                return MOVE_CANCEL_RACE;
         }
-        spin_unlock(&ubi->volumes_lock);
 
         /*
          * We do not want anybody to write to this logical eraseblock while we
@@ -1004,12 +1026,13 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
          * (@from). This task locks the LEB and goes sleep in the
          * 'ubi_wl_put_peb()' function on the @ubi->move_mutex. In turn, we are
          * holding @ubi->move_mutex and go sleep on the LEB lock. So, if the
-         * LEB is already locked, we just do not move it and return %1.
+         * LEB is already locked, we just do not move it and return
+         * %MOVE_CANCEL_RACE, which means that UBI will re-try, but later.
          */
         err = leb_write_trylock(ubi, vol_id, lnum);
         if (err) {
-                dbg_eba("contention on LEB %d:%d, cancel", vol_id, lnum);
-                return err;
+                dbg_wl("contention on LEB %d:%d, cancel", vol_id, lnum);
+                return MOVE_CANCEL_RACE;
         }
 
         /*
@@ -1018,25 +1041,26 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
          * cancel it.
          */
         if (vol->eba_tbl[lnum] != from) {
-                dbg_eba("LEB %d:%d is no longer mapped to PEB %d, mapped to "
-                        "PEB %d, cancel", vol_id, lnum, from,
-                        vol->eba_tbl[lnum]);
-                err = 1;
+                dbg_wl("LEB %d:%d is no longer mapped to PEB %d, mapped to "
+                       "PEB %d, cancel", vol_id, lnum, from,
+                       vol->eba_tbl[lnum]);
+                err = MOVE_CANCEL_RACE;
                 goto out_unlock_leb;
         }
 
         /*
          * OK, now the LEB is locked and we can safely start moving it. Since
-         * this function utilizes the @ubi->peb1_buf buffer which is shared
-         * with some other functions, so lock the buffer by taking the
+         * this function utilizes the @ubi->peb_buf1 buffer which is shared
+         * with some other functions - we lock the buffer by taking the
          * @ubi->buf_mutex.
          */
         mutex_lock(&ubi->buf_mutex);
-        dbg_eba("read %d bytes of data", aldata_size);
+        dbg_wl("read %d bytes of data", aldata_size);
         err = ubi_io_read_data(ubi, ubi->peb_buf1, from, 0, aldata_size);
         if (err && err != UBI_IO_BITFLIPS) {
                 ubi_warn("error %d while reading data from PEB %d",
                          err, from);
+                err = MOVE_SOURCE_RD_ERR;
                 goto out_unlock_buf;
         }
 
@@ -1059,7 +1083,7 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
         cond_resched();
 
         /*
-         * It may turn out to me that the whole @from physical eraseblock
+         * It may turn out to be that the whole @from physical eraseblock
          * contains only 0xFF bytes. Then we have to only write the VID header
          * and do not write any data. This also means we should not set
          * @vid_hdr->copy_flag, @vid_hdr->data_size, and @vid_hdr->data_crc.
@@ -1074,7 +1098,7 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
         err = ubi_io_write_vid_hdr(ubi, to, vid_hdr);
         if (err) {
                 if (err == -EIO)
-                        err = 2;
+                        err = MOVE_TARGET_WR_ERR;
                 goto out_unlock_buf;
         }
 
@@ -1083,10 +1107,13 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
         /* Read the VID header back and check if it was written correctly */
         err = ubi_io_read_vid_hdr(ubi, to, vid_hdr, 1);
         if (err) {
-                if (err != UBI_IO_BITFLIPS)
-                        ubi_warn("cannot read VID header back from PEB %d", to);
-                else
-                        err = -EAGAIN;
+                if (err != UBI_IO_BITFLIPS) {
+                        ubi_warn("error %d while reading VID header back from "
+                                  "PEB %d", err, to);
+                        if (is_error_sane(err))
+                                err = MOVE_TARGET_RD_ERR;
+                } else
+                        err = MOVE_CANCEL_BITFLIPS;
                 goto out_unlock_buf;
         }
 
@@ -1094,7 +1121,7 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
                 err = ubi_io_write_data(ubi, ubi->peb_buf1, to, 0, aldata_size);
                 if (err) {
                         if (err == -EIO)
-                                err = 2;
+                                err = MOVE_TARGET_WR_ERR;
                         goto out_unlock_buf;
                 }
 
@@ -1107,11 +1134,13 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
 
                 err = ubi_io_read_data(ubi, ubi->peb_buf2, to, 0, aldata_size);
                 if (err) {
-                        if (err != UBI_IO_BITFLIPS)
-                                ubi_warn("cannot read data back from PEB %d",
-                                         to);
-                        else
-                                err = -EAGAIN;
+                        if (err != UBI_IO_BITFLIPS) {
+                                ubi_warn("error %d while reading data back "
+                                         "from PEB %d", err, to);
+                                if (is_error_sane(err))
+                                        err = MOVE_TARGET_RD_ERR;
+                        } else
+                                err = MOVE_CANCEL_BITFLIPS;
                         goto out_unlock_buf;
                 }
 
diff --git a/drivers/mtd/ubi/gluebi.c b/drivers/mtd/ubi/gluebi.c
index 49cd55ade9c8..95aaac03f938 100644
--- a/drivers/mtd/ubi/gluebi.c
+++ b/drivers/mtd/ubi/gluebi.c
@@ -19,17 +19,71 @@
  */
 
 /*
- * This file includes implementation of fake MTD devices for each UBI volume.
- * This sounds strange, but it is in fact quite useful to make MTD-oriented
- * software (including all the legacy software) to work on top of UBI.
+ * This is a small driver which implements fake MTD devices on top of UBI
+ * volumes. This sounds strange, but it is in fact quite useful to make
+ * MTD-oriented software (including all the legacy software) work on top of
+ * UBI.
  *
  * Gluebi emulates MTD devices of "MTD_UBIVOLUME" type. Their minimal I/O unit
- * size (mtd->writesize) is equivalent to the UBI minimal I/O unit. The
+ * size (@mtd->writesize) is equivalent to the UBI minimal I/O unit. The
  * eraseblock size is equivalent to the logical eraseblock size of the volume.
  */
 
+#include <linux/err.h>
+#include <linux/list.h>
+#include <linux/sched.h>
 #include <linux/math64.h>
-#include "ubi.h"
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/mtd/ubi.h>
+#include <linux/mtd/mtd.h>
+#include "ubi-media.h"
+
+#define err_msg(fmt, ...)                                   \
+        printk(KERN_DEBUG "gluebi (pid %d): %s: " fmt "\n", \
+               current->pid, __func__, ##__VA_ARGS__)
+
+/**
+ * struct gluebi_device - a gluebi device description data structure.
+ * @mtd: emulated MTD device description object
+ * @refcnt: gluebi device reference count
+ * @desc: UBI volume descriptor
+ * @ubi_num: UBI device number this gluebi device works on
+ * @vol_id: ID of UBI volume this gluebi device works on
+ * @list: link in a list of gluebi devices
+ */
+struct gluebi_device {
+        struct mtd_info mtd;
+        int refcnt;
+        struct ubi_volume_desc *desc;
+        int ubi_num;
+        int vol_id;
+        struct list_head list;
+};
+
+/* List of all gluebi devices */
+static LIST_HEAD(gluebi_devices);
+static DEFINE_MUTEX(devices_mutex);
+
+/**
+ * find_gluebi_nolock - find a gluebi device.
+ * @ubi_num: UBI device number
+ * @vol_id: volume ID
+ *
+ * This function seraches for gluebi device corresponding to UBI device
+ * @ubi_num and UBI volume @vol_id. Returns the gluebi device description
+ * object in case of success and %NULL in case of failure. The caller has to
+ * have the &devices_mutex locked.
+ */
+static struct gluebi_device *find_gluebi_nolock(int ubi_num, int vol_id)
+{
+        struct gluebi_device *gluebi;
+
+        list_for_each_entry(gluebi, &gluebi_devices, list)
+                if (gluebi->ubi_num == ubi_num && gluebi->vol_id == vol_id)
+                        return gluebi;
+        return NULL;
+}
 
 /**
  * gluebi_get_device - get MTD device reference.
@@ -41,15 +95,18 @@
  */
 static int gluebi_get_device(struct mtd_info *mtd)
 {
-        struct ubi_volume *vol;
+        struct gluebi_device *gluebi;
+        int ubi_mode = UBI_READONLY;
 
-        vol = container_of(mtd, struct ubi_volume, gluebi_mtd);
+        if (!try_module_get(THIS_MODULE))
+                return -ENODEV;
 
-        /*
-         * We do not introduce locks for gluebi reference count because the
-         * get_device()/put_device() calls are already serialized at MTD.
-         */
-        if (vol->gluebi_refcount > 0) {
+        if (mtd->flags & MTD_WRITEABLE)
+                ubi_mode = UBI_READWRITE;
+
+        gluebi = container_of(mtd, struct gluebi_device, mtd);
+        mutex_lock(&devices_mutex);
+        if (gluebi->refcnt > 0) {
                 /*
                  * The MTD device is already referenced and this is just one
                  * more reference. MTD allows many users to open the same
@@ -58,7 +115,8 @@ static int gluebi_get_device(struct mtd_info *mtd)
                  * open the UBI volume again - just increase the reference
                  * counter and return.
                  */
-                vol->gluebi_refcount += 1;
+                gluebi->refcnt += 1;
+                mutex_unlock(&devices_mutex);
                 return 0;
         }
 
@@ -66,11 +124,15 @@ static int gluebi_get_device(struct mtd_info *mtd)
          * This is the first reference to this UBI volume via the MTD device
          * interface. Open the corresponding volume in read-write mode.
          */
-        vol->gluebi_desc = ubi_open_volume(vol->ubi->ubi_num, vol->vol_id,
-                                           UBI_READWRITE);
-        if (IS_ERR(vol->gluebi_desc))
-                return PTR_ERR(vol->gluebi_desc);
-        vol->gluebi_refcount += 1;
+        gluebi->desc = ubi_open_volume(gluebi->ubi_num, gluebi->vol_id,
+                                       ubi_mode);
+        if (IS_ERR(gluebi->desc)) {
+                mutex_unlock(&devices_mutex);
+                module_put(THIS_MODULE);
+                return PTR_ERR(gluebi->desc);
+        }
+        gluebi->refcnt += 1;
+        mutex_unlock(&devices_mutex);
         return 0;
 }
 
@@ -83,13 +145,15 @@ static int gluebi_get_device(struct mtd_info *mtd)
  */
 static void gluebi_put_device(struct mtd_info *mtd)
 {
-        struct ubi_volume *vol;
-
-        vol = container_of(mtd, struct ubi_volume, gluebi_mtd);
-        vol->gluebi_refcount -= 1;
-        ubi_assert(vol->gluebi_refcount >= 0);
-        if (vol->gluebi_refcount == 0)
-                ubi_close_volume(vol->gluebi_desc);
+        struct gluebi_device *gluebi;
+
+        gluebi = container_of(mtd, struct gluebi_device, mtd);
+        mutex_lock(&devices_mutex);
+        gluebi->refcnt -= 1;
+        if (gluebi->refcnt == 0)
+                ubi_close_volume(gluebi->desc);
+        module_put(THIS_MODULE);
+        mutex_unlock(&devices_mutex);
 }
 
 /**
@@ -107,16 +171,12 @@ static int gluebi_read(struct mtd_info *mtd, loff_t from, size_t len,
                        size_t *retlen, unsigned char *buf)
 {
         int err = 0, lnum, offs, total_read;
-        struct ubi_volume *vol;
-        struct ubi_device *ubi;
-
-        dbg_gen("read %zd bytes from offset %lld", len, from);
+        struct gluebi_device *gluebi;
 
         if (len < 0 || from < 0 || from + len > mtd->size)
                 return -EINVAL;
 
-        vol = container_of(mtd, struct ubi_volume, gluebi_mtd);
-        ubi = vol->ubi;
+        gluebi = container_of(mtd, struct gluebi_device, mtd);
 
         lnum = div_u64_rem(from, mtd->erasesize, &offs);
         total_read = len;
@@ -126,7 +186,7 @@ static int gluebi_read(struct mtd_info *mtd, loff_t from, size_t len,
                 if (to_read > total_read)
                         to_read = total_read;
 
-                err = ubi_eba_read_leb(ubi, vol, lnum, buf, offs, to_read, 0);
+                err = ubi_read(gluebi->desc, lnum, buf, offs, to_read);
                 if (err)
                         break;
 
@@ -152,21 +212,17 @@ static int gluebi_read(struct mtd_info *mtd, loff_t from, size_t len,
  * case of failure.
  */
 static int gluebi_write(struct mtd_info *mtd, loff_t to, size_t len,
-                       size_t *retlen, const u_char *buf)
+                        size_t *retlen, const u_char *buf)
 {
         int err = 0, lnum, offs, total_written;
-        struct ubi_volume *vol;
-        struct ubi_device *ubi;
-
-        dbg_gen("write %zd bytes to offset %lld", len, to);
+        struct gluebi_device *gluebi;
 
         if (len < 0 || to < 0 || len + to > mtd->size)
                 return -EINVAL;
 
-        vol = container_of(mtd, struct ubi_volume, gluebi_mtd);
-        ubi = vol->ubi;
+        gluebi = container_of(mtd, struct gluebi_device, mtd);
 
-        if (ubi->ro_mode)
+        if (!(mtd->flags & MTD_WRITEABLE))
                 return -EROFS;
 
         lnum = div_u64_rem(to, mtd->erasesize, &offs);
@@ -181,8 +237,7 @@ static int gluebi_write(struct mtd_info *mtd, loff_t to, size_t len,
                 if (to_write > total_written)
                         to_write = total_written;
 
-                err = ubi_eba_write_leb(ubi, vol, lnum, buf, offs, to_write,
-                                        UBI_UNKNOWN);
+                err = ubi_write(gluebi->desc, lnum, buf, offs, to_write);
                 if (err)
                         break;
 
@@ -207,41 +262,36 @@ static int gluebi_write(struct mtd_info *mtd, loff_t to, size_t len,
 static int gluebi_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
         int err, i, lnum, count;
-        struct ubi_volume *vol;
-        struct ubi_device *ubi;
-
-        dbg_gen("erase %llu bytes at offset %llu", (unsigned long long)instr->len,
-                 (unsigned long long)instr->addr);
+        struct gluebi_device *gluebi;
 
         if (instr->addr < 0 || instr->addr > mtd->size - mtd->erasesize)
                 return -EINVAL;
-
         if (instr->len < 0 || instr->addr + instr->len > mtd->size)
                 return -EINVAL;
-
         if (mtd_mod_by_ws(instr->addr, mtd) || mtd_mod_by_ws(instr->len, mtd))
                 return -EINVAL;
 
         lnum = mtd_div_by_eb(instr->addr, mtd);
         count = mtd_div_by_eb(instr->len, mtd);
 
-        vol = container_of(mtd, struct ubi_volume, gluebi_mtd);
-        ubi = vol->ubi;
+        gluebi = container_of(mtd, struct gluebi_device, mtd);
 
-        if (ubi->ro_mode)
+        if (!(mtd->flags & MTD_WRITEABLE))
                 return -EROFS;
 
-        for (i = 0; i < count; i++) {
-                err = ubi_eba_unmap_leb(ubi, vol, lnum + i);
+        for (i = 0; i < count - 1; i++) {
+                err = ubi_leb_unmap(gluebi->desc, lnum + i);
                 if (err)
                         goto out_err;
         }
-
         /*
          * MTD erase operations are synchronous, so we have to make sure the
          * physical eraseblock is wiped out.
+         *
+         * Thus, perform leb_erase instead of leb_unmap operation - leb_erase
+         * will wait for the end of operations
          */
-        err = ubi_wl_flush(ubi);
+        err = ubi_leb_erase(gluebi->desc, lnum + i);
         if (err)
                 goto out_err;
 
@@ -256,28 +306,38 @@ out_err:
 }
 
 /**
- * ubi_create_gluebi - initialize gluebi for an UBI volume.
- * @ubi: UBI device description object
- * @vol: volume description object
+ * gluebi_create - create a gluebi device for an UBI volume.
+ * @di: UBI device description object
+ * @vi: UBI volume description object
  *
- * This function is called when an UBI volume is created in order to create
+ * This function is called when a new UBI volume is created in order to create
  * corresponding fake MTD device. Returns zero in case of success and a
  * negative error code in case of failure.
  */
-int ubi_create_gluebi(struct ubi_device *ubi, struct ubi_volume *vol)
+static int gluebi_create(struct ubi_device_info *di,
+                         struct ubi_volume_info *vi)
 {
-        struct mtd_info *mtd = &vol->gluebi_mtd;
+        struct gluebi_device *gluebi, *g;
+        struct mtd_info *mtd;
 
-        mtd->name = kmemdup(vol->name, vol->name_len + 1, GFP_KERNEL);
-        if (!mtd->name)
+        gluebi = kzalloc(sizeof(struct gluebi_device), GFP_KERNEL);
+        if (!gluebi)
                 return -ENOMEM;
 
+        mtd = &gluebi->mtd;
+        mtd->name = kmemdup(vi->name, vi->name_len + 1, GFP_KERNEL);
+        if (!mtd->name) {
+                kfree(gluebi);
+                return -ENOMEM;
+        }
+
+        gluebi->vol_id = vi->vol_id;
         mtd->type = MTD_UBIVOLUME;
-        if (!ubi->ro_mode)
+        if (!di->ro_mode)
                 mtd->flags = MTD_WRITEABLE;
-        mtd->writesize  = ubi->min_io_size;
         mtd->owner      = THIS_MODULE;
-        mtd->erasesize  = vol->usable_leb_size;
+        mtd->writesize  = di->min_io_size;
+        mtd->erasesize  = vi->usable_leb_size;
         mtd->read       = gluebi_read;
         mtd->write      = gluebi_write;
         mtd->erase      = gluebi_erase;
@@ -285,60 +345,196 @@ int ubi_create_gluebi(struct ubi_device *ubi, struct ubi_volume *vol)
         mtd->put_device = gluebi_put_device;
 
         /*
-         * In case of dynamic volume, MTD device size is just volume size. In
+         * In case of dynamic a volume, MTD device size is just volume size. In
          * case of a static volume the size is equivalent to the amount of data
          * bytes.
          */
-        if (vol->vol_type == UBI_DYNAMIC_VOLUME)
-                mtd->size = (long long)vol->usable_leb_size * vol->reserved_pebs;
+        if (vi->vol_type == UBI_DYNAMIC_VOLUME)
+                mtd->size = (unsigned long long)vi->usable_leb_size * vi->size;
         else
-                mtd->size = vol->used_bytes;
+                mtd->size = vi->used_bytes;
+
+        /* Just a sanity check - make sure this gluebi device does not exist */
+        mutex_lock(&devices_mutex);
+        g = find_gluebi_nolock(vi->ubi_num, vi->vol_id);
+        if (g)
+                err_msg("gluebi MTD device %d form UBI device %d volume %d "
+                        "already exists", g->mtd.index, vi->ubi_num,
+                        vi->vol_id);
+        mutex_unlock(&devices_mutex);
 
         if (add_mtd_device(mtd)) {
-                ubi_err("cannot not add MTD device");
+                err_msg("cannot add MTD device");
                 kfree(mtd->name);
+                kfree(gluebi);
                 return -ENFILE;
         }
 
-        dbg_gen("added mtd%d (\"%s\"), size %llu, EB size %u",
-                mtd->index, mtd->name, (unsigned long long)mtd->size, mtd->erasesize);
+        mutex_lock(&devices_mutex);
+        list_add_tail(&gluebi->list, &gluebi_devices);
+        mutex_unlock(&devices_mutex);
         return 0;
 }
 
 /**
- * ubi_destroy_gluebi - close gluebi for an UBI volume.
- * @vol: volume description object
+ * gluebi_remove - remove a gluebi device.
+ * @vi: UBI volume description object
  *
- * This function is called when an UBI volume is removed in order to remove
+ * This function is called when an UBI volume is removed and it removes
  * corresponding fake MTD device. Returns zero in case of success and a
  * negative error code in case of failure.
  */
-int ubi_destroy_gluebi(struct ubi_volume *vol)
+static int gluebi_remove(struct ubi_volume_info *vi)
 {
-        int err;
-        struct mtd_info *mtd = &vol->gluebi_mtd;
+        int err = 0;
+        struct mtd_info *mtd;
+        struct gluebi_device *gluebi;
+
+        mutex_lock(&devices_mutex);
+        gluebi = find_gluebi_nolock(vi->ubi_num, vi->vol_id);
+        if (!gluebi) {
+                err_msg("got remove notification for unknown UBI device %d "
+                        "volume %d", vi->ubi_num, vi->vol_id);
+                err = -ENOENT;
+        } else if (gluebi->refcnt)
+                err = -EBUSY;
+        else
+                list_del(&gluebi->list);
+        mutex_unlock(&devices_mutex);
+        if (err)
+                return err;
 
-        dbg_gen("remove mtd%d", mtd->index);
+        mtd = &gluebi->mtd;
         err = del_mtd_device(mtd);
-        if (err)
+        if (err) {
+                err_msg("cannot remove fake MTD device %d, UBI device %d, "
+                        "volume %d, error %d", mtd->index, gluebi->ubi_num,
+                        gluebi->vol_id, err);
+                mutex_lock(&devices_mutex);
+                list_add_tail(&gluebi->list, &gluebi_devices);
+                mutex_unlock(&devices_mutex);
                 return err;
+        }
+
         kfree(mtd->name);
+        kfree(gluebi);
         return 0;
 }
 
 /**
- * ubi_gluebi_updated - UBI volume was updated notifier.
- * @vol: volume description object
+ * gluebi_updated - UBI volume was updated notifier.
+ * @vi: volume info structure
  *
- * This function is called every time an UBI volume is updated. This function
- * does nothing if volume @vol is dynamic, and changes MTD device size if the
+ * This function is called every time an UBI volume is updated. It does nothing
+ * if te volume @vol is dynamic, and changes MTD device size if the
  * volume is static. This is needed because static volumes cannot be read past
- * data they contain.
+ * data they contain. This function returns zero in case of success and a
+ * negative error code in case of error.
+ */
+static int gluebi_updated(struct ubi_volume_info *vi)
+{
+        struct gluebi_device *gluebi;
+
+        mutex_lock(&devices_mutex);
+        gluebi = find_gluebi_nolock(vi->ubi_num, vi->vol_id);
+        if (!gluebi) {
+                mutex_unlock(&devices_mutex);
+                err_msg("got update notification for unknown UBI device %d "
+                        "volume %d", vi->ubi_num, vi->vol_id);
+                return -ENOENT;
+        }
+
+        if (vi->vol_type == UBI_STATIC_VOLUME)
+                gluebi->mtd.size = vi->used_bytes;
+        mutex_unlock(&devices_mutex);
+        return 0;
+}
+
+/**
+ * gluebi_resized - UBI volume was re-sized notifier.
+ * @vi: volume info structure
+ *
+ * This function is called every time an UBI volume is re-size. It changes the
+ * corresponding fake MTD device size. This function returns zero in case of
+ * success and a negative error code in case of error.
+ */
+static int gluebi_resized(struct ubi_volume_info *vi)
+{
+        struct gluebi_device *gluebi;
+
+        mutex_lock(&devices_mutex);
+        gluebi = find_gluebi_nolock(vi->ubi_num, vi->vol_id);
+        if (!gluebi) {
+                mutex_unlock(&devices_mutex);
+                err_msg("got update notification for unknown UBI device %d "
+                        "volume %d", vi->ubi_num, vi->vol_id);
+                return -ENOENT;
+        }
+        gluebi->mtd.size = vi->used_bytes;
+        mutex_unlock(&devices_mutex);
+        return 0;
+}
+
+/**
+ * gluebi_notify - UBI notification handler.
+ * @nb: registered notifier block
+ * @l: notification type
+ * @ptr: pointer to the &struct ubi_notification object
  */
-void ubi_gluebi_updated(struct ubi_volume *vol)
+static int gluebi_notify(struct notifier_block *nb, unsigned long l,
+                         void *ns_ptr)
 {
-        struct mtd_info *mtd = &vol->gluebi_mtd;
+        struct ubi_notification *nt = ns_ptr;
+
+        switch (l) {
+        case UBI_VOLUME_ADDED:
+                gluebi_create(&nt->di, &nt->vi);
+                break;
+        case UBI_VOLUME_REMOVED:
+                gluebi_remove(&nt->vi);
+                break;
+        case UBI_VOLUME_RESIZED:
+                gluebi_resized(&nt->vi);
+                break;
+        case UBI_VOLUME_UPDATED:
+                gluebi_updated(&nt->vi);
+                break;
+        default:
+                break;
+        }
+        return NOTIFY_OK;
+}
 
-        if (vol->vol_type == UBI_STATIC_VOLUME)
-                mtd->size = vol->used_bytes;
+static struct notifier_block gluebi_notifier = {
+        .notifier_call  = gluebi_notify,
+};
+
+static int __init ubi_gluebi_init(void)
+{
+        return ubi_register_volume_notifier(&gluebi_notifier, 0);
 }
+
+static void __exit ubi_gluebi_exit(void)
+{
+        struct gluebi_device *gluebi, *g;
+
+        list_for_each_entry_safe(gluebi, g, &gluebi_devices, list) {
+                int err;
+                struct mtd_info *mtd = &gluebi->mtd;
+
+                err = del_mtd_device(mtd);
+                if (err)
+                        err_msg("error %d while removing gluebi MTD device %d, "
+                                "UBI device %d, volume %d - ignoring", err,
+                                mtd->index, gluebi->ubi_num, gluebi->vol_id);
+                kfree(mtd->name);
+                kfree(gluebi);
+        }
+        ubi_unregister_volume_notifier(&gluebi_notifier);
+}
+
+module_init(ubi_gluebi_init);
+module_exit(ubi_gluebi_exit);
+MODULE_DESCRIPTION("MTD emulation layer over UBI volumes");
+MODULE_AUTHOR("Artem Bityutskiy, Joern Engel");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
index fe81039f2a7c..effaff28bab1 100644
--- a/drivers/mtd/ubi/io.c
+++ b/drivers/mtd/ubi/io.c
@@ -100,6 +100,7 @@ static int paranoid_check_vid_hdr(const struct ubi_device *ubi, int pnum,
                                   const struct ubi_vid_hdr *vid_hdr);
 static int paranoid_check_all_ff(struct ubi_device *ubi, int pnum, int offset,
                                  int len);
+static int paranoid_check_empty(struct ubi_device *ubi, int pnum);
 #else
 #define paranoid_check_not_bad(ubi, pnum) 0
 #define paranoid_check_peb_ec_hdr(ubi, pnum)  0
@@ -107,6 +108,7 @@ static int paranoid_check_all_ff(struct ubi_device *ubi, int pnum, int offset,
 #define paranoid_check_peb_vid_hdr(ubi, pnum) 0
 #define paranoid_check_vid_hdr(ubi, pnum, vid_hdr) 0
 #define paranoid_check_all_ff(ubi, pnum, offset, len) 0
+#define paranoid_check_empty(ubi, pnum) 0
 #endif
 
 /**
@@ -670,11 +672,6 @@ int ubi_io_read_ec_hdr(struct ubi_device *ubi, int pnum,
                 if (read_err != -EBADMSG &&
                     check_pattern(ec_hdr, 0xFF, UBI_EC_HDR_SIZE)) {
                         /* The physical eraseblock is supposedly empty */
-
-                        /*
-                         * The below is just a paranoid check, it has to be
-                         * compiled out if paranoid checks are disabled.
-                         */
                         err = paranoid_check_all_ff(ubi, pnum, 0,
                                                     ubi->peb_size);
                         if (err)
@@ -902,7 +899,7 @@ bad:
  * o %UBI_IO_BITFLIPS if the CRC is correct, but bit-flips were detected
  *   and corrected by the flash driver; this is harmless but may indicate that
  *   this eraseblock may become bad soon;
- * o %UBI_IO_BAD_VID_HRD if the volume identifier header is corrupted (a CRC
+ * o %UBI_IO_BAD_VID_HDR if the volume identifier header is corrupted (a CRC
  *   error detected);
  * o %UBI_IO_PEB_FREE if the physical eraseblock is free (i.e., there is no VID
  *   header there);
@@ -955,8 +952,7 @@ int ubi_io_read_vid_hdr(struct ubi_device *ubi, int pnum,
                          * The below is just a paranoid check, it has to be
                          * compiled out if paranoid checks are disabled.
                          */
-                        err = paranoid_check_all_ff(ubi, pnum, ubi->leb_start,
-                                                    ubi->leb_size);
+                        err = paranoid_check_empty(ubi, pnum);
                         if (err)
                                 return err > 0 ? UBI_IO_BAD_VID_HDR : err;
 
@@ -1280,4 +1276,74 @@ error:
         return err;
 }
 
+/**
+ * paranoid_check_empty - whether a PEB is empty.
+ * @ubi: UBI device description object
+ * @pnum: the physical eraseblock number to check
+ *
+ * This function makes sure PEB @pnum is empty, which means it contains only
+ * %0xFF data bytes. Returns zero if the PEB is empty, %1 if not, and a
+ * negative error code in case of failure.
+ *
+ * Empty PEBs have the EC header, and do not have the VID header. The caller of
+ * this function should have already made sure the PEB does not have the VID
+ * header. However, this function re-checks that, because it is possible that
+ * the header and data has already been written to the PEB.
+ *
+ * Let's consider a possible scenario. Suppose there are 2 tasks - A and B.
+ * Task A is in 'wear_leveling_worker()'. It is reading VID header of PEB X to
+ * find which LEB it corresponds to. PEB X is currently unmapped, and has no
+ * VID header. Task B is trying to write to PEB X.
+ *
+ * Task A: in 'ubi_io_read_vid_hdr()': reads the VID header from PEB X. The
+ *         read data contain all 0xFF bytes;
+ * Task B: writes VID header and some data to PEB X;
+ * Task A: assumes PEB X is empty, calls 'paranoid_check_empty()'. And if we
+ *         do not re-read the VID header, and do not cancel the checking if it
+ *         is there, we fail.
+ */
+static int paranoid_check_empty(struct ubi_device *ubi, int pnum)
+{
+        int err, offs = ubi->vid_hdr_aloffset, len = ubi->vid_hdr_alsize;
+        size_t read;
+        uint32_t magic;
+        const struct ubi_vid_hdr *vid_hdr;
+
+        mutex_lock(&ubi->dbg_buf_mutex);
+        err = ubi->mtd->read(ubi->mtd, offs, len, &read, ubi->dbg_peb_buf);
+        if (err && err != -EUCLEAN) {
+                ubi_err("error %d while reading %d bytes from PEB %d:%d, "
+                        "read %zd bytes", err, len, pnum, offs, read);
+                goto error;
+        }
+
+        vid_hdr = ubi->dbg_peb_buf;
+        magic = be32_to_cpu(vid_hdr->magic);
+        if (magic == UBI_VID_HDR_MAGIC)
+                /* The PEB contains VID header, so it is not empty */
+                goto out;
+
+        err = check_pattern(ubi->dbg_peb_buf, 0xFF, len);
+        if (err == 0) {
+                ubi_err("flash region at PEB %d:%d, length %d does not "
+                        "contain all 0xFF bytes", pnum, offs, len);
+                goto fail;
+        }
+
+out:
+        mutex_unlock(&ubi->dbg_buf_mutex);
+        return 0;
+
+fail:
+        ubi_err("paranoid check failed for PEB %d", pnum);
+        ubi_msg("hex dump of the %d-%d region", offs, offs + len);
+        print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 32, 1,
+                       ubi->dbg_peb_buf, len, 1);
+        err = 1;
+error:
+        ubi_dbg_dump_stack();
+        mutex_unlock(&ubi->dbg_buf_mutex);
+        return err;
+}
+
 #endif /* CONFIG_MTD_UBI_DEBUG_PARANOID */
diff --git a/drivers/mtd/ubi/kapi.c b/drivers/mtd/ubi/kapi.c
index 4abbe573fa40..88a72e9c8beb 100644
--- a/drivers/mtd/ubi/kapi.c
+++ b/drivers/mtd/ubi/kapi.c
@@ -26,6 +26,24 @@
 #include "ubi.h"
 
 /**
+ * ubi_do_get_device_info - get information about UBI device.
+ * @ubi: UBI device description object
+ * @di: the information is stored here
+ *
+ * This function is the same as 'ubi_get_device_info()', but it assumes the UBI
+ * device is locked and cannot disappear.
+ */
+void ubi_do_get_device_info(struct ubi_device *ubi, struct ubi_device_info *di)
+{
+        di->ubi_num = ubi->ubi_num;
+        di->leb_size = ubi->leb_size;
+        di->min_io_size = ubi->min_io_size;
+        di->ro_mode = ubi->ro_mode;
+        di->cdev = ubi->cdev.dev;
+}
+EXPORT_SYMBOL_GPL(ubi_do_get_device_info);
+
+/**
  * ubi_get_device_info - get information about UBI device.
  * @ubi_num: UBI device number
  * @di: the information is stored here
@@ -39,33 +57,24 @@ int ubi_get_device_info(int ubi_num, struct ubi_device_info *di)
 
         if (ubi_num < 0 || ubi_num >= UBI_MAX_DEVICES)
                 return -EINVAL;
-
         ubi = ubi_get_device(ubi_num);
         if (!ubi)
                 return -ENODEV;
-
-        di->ubi_num = ubi->ubi_num;
-        di->leb_size = ubi->leb_size;
-        di->min_io_size = ubi->min_io_size;
-        di->ro_mode = ubi->ro_mode;
-        di->cdev = ubi->cdev.dev;
-
+        ubi_do_get_device_info(ubi, di);
         ubi_put_device(ubi);
         return 0;
 }
 EXPORT_SYMBOL_GPL(ubi_get_device_info);
 
 /**
- * ubi_get_volume_info - get information about UBI volume.
- * @desc: volume descriptor
+ * ubi_do_get_volume_info - get information about UBI volume.
+ * @ubi: UBI device description object
+ * @vol: volume description object
  * @vi: the information is stored here
  */
-void ubi_get_volume_info(struct ubi_volume_desc *desc,
-                         struct ubi_volume_info *vi)
+void ubi_do_get_volume_info(struct ubi_device *ubi, struct ubi_volume *vol,
+                            struct ubi_volume_info *vi)
 {
-        const struct ubi_volume *vol = desc->vol;
-        const struct ubi_device *ubi = vol->ubi;
-
         vi->vol_id = vol->vol_id;
         vi->ubi_num = ubi->ubi_num;
         vi->size = vol->reserved_pebs;
@@ -79,6 +88,17 @@ void ubi_get_volume_info(struct ubi_volume_desc *desc,
         vi->name = vol->name;
         vi->cdev = vol->cdev.dev;
 }
+
+/**
+ * ubi_get_volume_info - get information about UBI volume.
+ * @desc: volume descriptor
+ * @vi: the information is stored here
+ */
+void ubi_get_volume_info(struct ubi_volume_desc *desc,
+                         struct ubi_volume_info *vi)
+{
+        ubi_do_get_volume_info(desc->vol->ubi, desc->vol, vi);
+}
 EXPORT_SYMBOL_GPL(ubi_get_volume_info);
 
 /**
@@ -106,7 +126,7 @@ struct ubi_volume_desc *ubi_open_volume(int ubi_num, int vol_id, int mode)
         struct ubi_device *ubi;
         struct ubi_volume *vol;
 
-        dbg_gen("open device %d volume %d, mode %d", ubi_num, vol_id, mode);
+        dbg_gen("open device %d, volume %d, mode %d", ubi_num, vol_id, mode);
 
         if (ubi_num < 0 || ubi_num >= UBI_MAX_DEVICES)
                 return ERR_PTR(-EINVAL);
@@ -196,6 +216,8 @@ out_free:
         kfree(desc);
 out_put_ubi:
         ubi_put_device(ubi);
+        dbg_err("cannot open device %d, volume %d, error %d",
+                ubi_num, vol_id, err);
         return ERR_PTR(err);
 }
 EXPORT_SYMBOL_GPL(ubi_open_volume);
@@ -215,7 +237,7 @@ struct ubi_volume_desc *ubi_open_volume_nm(int ubi_num, const char *name,
         struct ubi_device *ubi;
         struct ubi_volume_desc *ret;
 
-        dbg_gen("open volume %s, mode %d", name, mode);
+        dbg_gen("open device %d, volume %s, mode %d", ubi_num, name, mode);
 
         if (!name)
                 return ERR_PTR(-EINVAL);
@@ -266,7 +288,8 @@ void ubi_close_volume(struct ubi_volume_desc *desc)
         struct ubi_volume *vol = desc->vol;
         struct ubi_device *ubi = vol->ubi;
 
-        dbg_gen("close volume %d, mode %d", vol->vol_id, desc->mode);
+        dbg_gen("close device %d, volume %d, mode %d",
+                ubi->ubi_num, vol->vol_id, desc->mode);
 
         spin_lock(&ubi->volumes_lock);
         switch (desc->mode) {
@@ -558,7 +581,7 @@ int ubi_leb_unmap(struct ubi_volume_desc *desc, int lnum)
 EXPORT_SYMBOL_GPL(ubi_leb_unmap);
 
 /**
- * ubi_leb_map - map logical erasblock to a physical eraseblock.
+ * ubi_leb_map - map logical eraseblock to a physical eraseblock.
  * @desc: volume descriptor
  * @lnum: logical eraseblock number
  * @dtype: expected data type
@@ -656,3 +679,59 @@ int ubi_sync(int ubi_num)
         return 0;
 }
 EXPORT_SYMBOL_GPL(ubi_sync);
+
+BLOCKING_NOTIFIER_HEAD(ubi_notifiers);
+
+/**
+ * ubi_register_volume_notifier - register a volume notifier.
+ * @nb: the notifier description object
+ * @ignore_existing: if non-zero, do not send "added" notification for all
+ *                   already existing volumes
+ *
+ * This function registers a volume notifier, which means that
+ * 'nb->notifier_call()' will be invoked when an UBI  volume is created,
+ * removed, re-sized, re-named, or updated. The first argument of the function
+ * is the notification type. The second argument is pointer to a
+ * &struct ubi_notification object which describes the notification event.
+ * Using UBI API from the volume notifier is prohibited.
+ *
+ * This function returns zero in case of success and a negative error code
+ * in case of failure.
+ */
+int ubi_register_volume_notifier(struct notifier_block *nb,
+                                 int ignore_existing)
+{
+        int err;
+
+        err = blocking_notifier_chain_register(&ubi_notifiers, nb);
+        if (err != 0)
+                return err;
+        if (ignore_existing)
+                return 0;
+
+        /*
+         * We are going to walk all UBI devices and all volumes, and
+         * notify the user about existing volumes by the %UBI_VOLUME_ADDED
+         * event. We have to lock the @ubi_devices_mutex to make sure UBI
+         * devices do not disappear.
+         */
+        mutex_lock(&ubi_devices_mutex);
+        ubi_enumerate_volumes(nb);
+        mutex_unlock(&ubi_devices_mutex);
+
+        return err;
+}
+EXPORT_SYMBOL_GPL(ubi_register_volume_notifier);
+
+/**
+ * ubi_unregister_volume_notifier - unregister the volume notifier.
+ * @nb: the notifier description object
+ *
+ * This function unregisters volume notifier @nm and returns zero in case of
+ * success and a negative error code in case of failure.
+ */
+int ubi_unregister_volume_notifier(struct notifier_block *nb)
+{
+        return blocking_notifier_chain_unregister(&ubi_notifiers, nb);
+}
+EXPORT_SYMBOL_GPL(ubi_unregister_volume_notifier);
diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h
index c055511bb1b2..28acd133c997 100644
--- a/drivers/mtd/ubi/ubi.h
+++ b/drivers/mtd/ubi/ubi.h
@@ -36,6 +36,7 @@
 #include <linux/device.h>
 #include <linux/string.h>
 #include <linux/vmalloc.h>
+#include <linux/notifier.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/ubi.h>
 
@@ -100,6 +101,28 @@ enum {
         UBI_IO_BITFLIPS
 };
 
+/*
+ * Return codes of the 'ubi_eba_copy_leb()' function.
+ *
+ * MOVE_CANCEL_RACE: canceled because the volume is being deleted, the source
+ *                   PEB was put meanwhile, or there is I/O on the source PEB
+ * MOVE_SOURCE_RD_ERR: canceled because there was a read error from the source
+ *                     PEB
+ * MOVE_TARGET_RD_ERR: canceled because there was a read error from the target
+ *                     PEB
+ * MOVE_TARGET_WR_ERR: canceled because there was a write error to the target
+ *                     PEB
+ * MOVE_CANCEL_BITFLIPS: canceled because a bit-flip was detected in the
+ *                       target PEB
+ */
+enum {
+        MOVE_CANCEL_RACE = 1,
+        MOVE_SOURCE_RD_ERR,
+        MOVE_TARGET_RD_ERR,
+        MOVE_TARGET_WR_ERR,
+        MOVE_CANCEL_BITFLIPS,
+};
+
 /**
  * struct ubi_wl_entry - wear-leveling entry.
  * @u.rb: link in the corresponding (free/used) RB-tree
@@ -208,10 +231,6 @@ struct ubi_volume_desc;
  * @changing_leb: %1 if the atomic LEB change ioctl command is in progress
  * @direct_writes: %1 if direct writes are enabled for this volume
  *
- * @gluebi_desc: gluebi UBI volume descriptor
- * @gluebi_refcount: reference count of the gluebi MTD device
- * @gluebi_mtd: MTD device description object of the gluebi MTD device
- *
  * The @corrupted field indicates that the volume's contents is corrupted.
  * Since UBI protects only static volumes, this field is not relevant to
  * dynamic volumes - it is user's responsibility to assure their data
@@ -255,17 +274,6 @@ struct ubi_volume {
         unsigned int updating:1;
         unsigned int changing_leb:1;
         unsigned int direct_writes:1;
-
-#ifdef CONFIG_MTD_UBI_GLUEBI
-        /*
-         * Gluebi-related stuff may be compiled out.
-         * Note: this should not be built into UBI but should be a separate
-         * ubimtd driver which works on top of UBI and emulates MTD devices.
-         */
-        struct ubi_volume_desc *gluebi_desc;
-        int gluebi_refcount;
-        struct mtd_info gluebi_mtd;
-#endif
 };
 
 /**
@@ -305,9 +313,9 @@ struct ubi_wl_entry;
  * @vtbl_slots: how many slots are available in the volume table
  * @vtbl_size: size of the volume table in bytes
  * @vtbl: in-RAM volume table copy
- * @volumes_mutex: protects on-flash volume table and serializes volume
- *                 changes, like creation, deletion, update, re-size,
- *                 re-name and set property
+ * @device_mutex: protects on-flash volume table and serializes volume
+ *                creation, deletion, update, re-size, re-name and set
+ *                property
  *
  * @max_ec: current highest erase counter value
  * @mean_ec: current mean erase counter value
@@ -318,14 +326,15 @@ struct ubi_wl_entry;
  * @alc_mutex: serializes "atomic LEB change" operations
  *
  * @used: RB-tree of used physical eraseblocks
+ * @erroneous: RB-tree of erroneous used physical eraseblocks
  * @free: RB-tree of free physical eraseblocks
  * @scrub: RB-tree of physical eraseblocks which need scrubbing
  * @pq: protection queue (contain physical eraseblocks which are temporarily
  *      protected from the wear-leveling worker)
  * @pq_head: protection queue head
  * @wl_lock: protects the @used, @free, @pq, @pq_head, @lookuptbl, @move_from,
- *           @move_to, @move_to_put @erase_pending, @wl_scheduled and @works
- *           fields
+ *           @move_to, @move_to_put @erase_pending, @wl_scheduled, @works,
+ *           @erroneous, and @erroneous_peb_count fields
  * @move_mutex: serializes eraseblock moves
  * @work_sem: synchronizes the WL worker with use tasks
  * @wl_scheduled: non-zero if the wear-leveling was scheduled
@@ -339,12 +348,15 @@ struct ubi_wl_entry;
  * @bgt_thread: background thread description object
  * @thread_enabled: if the background thread is enabled
  * @bgt_name: background thread name
+ * @reboot_notifier: notifier to terminate background thread before rebooting
  *
  * @flash_size: underlying MTD device size (in bytes)
  * @peb_count: count of physical eraseblocks on the MTD device
  * @peb_size: physical eraseblock size
  * @bad_peb_count: count of bad physical eraseblocks
  * @good_peb_count: count of good physical eraseblocks
+ * @erroneous_peb_count: count of erroneous physical eraseblocks in @erroneous
+ * @max_erroneous: maximum allowed amount of erroneous physical eraseblocks
  * @min_io_size: minimal input/output unit size of the underlying MTD device
  * @hdrs_min_io_size: minimal I/O unit size used for VID and EC headers
  * @ro_mode: if the UBI device is in read-only mode
@@ -366,7 +378,6 @@ struct ubi_wl_entry;
  * @peb_buf2: another buffer of PEB size used for different purposes
  * @buf_mutex: protects @peb_buf1 and @peb_buf2
  * @ckvol_mutex: serializes static volume checking when opening
- * @mult_mutex: serializes operations on multiple volumes, like re-naming
  * @dbg_peb_buf: buffer of PEB size used for debugging
  * @dbg_buf_mutex: protects @dbg_peb_buf
  */
@@ -389,7 +400,7 @@ struct ubi_device {
         int vtbl_slots;
         int vtbl_size;
         struct ubi_vtbl_record *vtbl;
-        struct mutex volumes_mutex;
+        struct mutex device_mutex;
 
         int max_ec;
         /* Note, mean_ec is not updated run-time - should be fixed */
@@ -403,6 +414,7 @@ struct ubi_device {
 
         /* Wear-leveling sub-system's stuff */
         struct rb_root used;
+        struct rb_root erroneous;
         struct rb_root free;
         struct rb_root scrub;
         struct list_head pq[UBI_PROT_QUEUE_LEN];
@@ -420,6 +432,7 @@ struct ubi_device {
         struct task_struct *bgt_thread;
         int thread_enabled;
         char bgt_name[sizeof(UBI_BGT_NAME_PATTERN)+2];
+        struct notifier_block reboot_notifier;
 
         /* I/O sub-system's stuff */
         long long flash_size;
@@ -427,6 +440,8 @@ struct ubi_device {
         int peb_size;
         int bad_peb_count;
         int good_peb_count;
+        int erroneous_peb_count;
+        int max_erroneous;
         int min_io_size;
         int hdrs_min_io_size;
         int ro_mode;
@@ -444,8 +459,7 @@ struct ubi_device {
         void *peb_buf2;
         struct mutex buf_mutex;
         struct mutex ckvol_mutex;
-        struct mutex mult_mutex;
-#ifdef CONFIG_MTD_UBI_DEBUG
+#ifdef CONFIG_MTD_UBI_DEBUG_PARANOID
         void *dbg_peb_buf;
         struct mutex dbg_buf_mutex;
 #endif
@@ -457,6 +471,7 @@ extern const struct file_operations ubi_cdev_operations;
 extern const struct file_operations ubi_vol_cdev_operations;
 extern struct class *ubi_class;
 extern struct mutex ubi_devices_mutex;
+extern struct blocking_notifier_head ubi_notifiers;
 
 /* vtbl.c */
 int ubi_change_vtbl_record(struct ubi_device *ubi, int idx,
@@ -489,17 +504,6 @@ int ubi_calc_data_len(const struct ubi_device *ubi, const void *buf,
 int ubi_check_volume(struct ubi_device *ubi, int vol_id);
 void ubi_calculate_reserved(struct ubi_device *ubi);
 
-/* gluebi.c */
-#ifdef CONFIG_MTD_UBI_GLUEBI
-int ubi_create_gluebi(struct ubi_device *ubi, struct ubi_volume *vol);
-int ubi_destroy_gluebi(struct ubi_volume *vol);
-void ubi_gluebi_updated(struct ubi_volume *vol);
-#else
-#define ubi_create_gluebi(ubi, vol) 0
-#define ubi_destroy_gluebi(vol) 0
-#define ubi_gluebi_updated(vol)
-#endif
-
 /* eba.c */
 int ubi_eba_unmap_leb(struct ubi_device *ubi, struct ubi_volume *vol,
                       int lnum);
@@ -549,6 +553,16 @@ struct ubi_device *ubi_get_device(int ubi_num);
 void ubi_put_device(struct ubi_device *ubi);
 struct ubi_device *ubi_get_by_major(int major);
 int ubi_major2num(int major);
+int ubi_volume_notify(struct ubi_device *ubi, struct ubi_volume *vol,
+                      int ntype);
+int ubi_notify_all(struct ubi_device *ubi, int ntype,
+                   struct notifier_block *nb);
+int ubi_enumerate_volumes(struct notifier_block *nb);
+
+/* kapi.c */
+void ubi_do_get_device_info(struct ubi_device *ubi, struct ubi_device_info *di);
+void ubi_do_get_volume_info(struct ubi_device *ubi, struct ubi_volume *vol,
+                            struct ubi_volume_info *vi);
 
 /*
  * ubi_rb_for_each_entry - walk an RB-tree.
diff --git a/drivers/mtd/ubi/upd.c b/drivers/mtd/ubi/upd.c
index 6b4d1ae891ae..74fdc40c8627 100644
--- a/drivers/mtd/ubi/upd.c
+++ b/drivers/mtd/ubi/upd.c
@@ -68,10 +68,10 @@ static int set_update_marker(struct ubi_device *ubi, struct ubi_volume *vol)
                sizeof(struct ubi_vtbl_record));
         vtbl_rec.upd_marker = 1;
 
-        mutex_lock(&ubi->volumes_mutex);
+        mutex_lock(&ubi->device_mutex);
         err = ubi_change_vtbl_record(ubi, vol->vol_id, &vtbl_rec);
-        mutex_unlock(&ubi->volumes_mutex);
         vol->upd_marker = 1;
+        mutex_unlock(&ubi->device_mutex);
         return err;
 }
 
@@ -109,10 +109,10 @@ static int clear_update_marker(struct ubi_device *ubi, struct ubi_volume *vol,
                         vol->last_eb_bytes = vol->usable_leb_size;
         }
 
-        mutex_lock(&ubi->volumes_mutex);
+        mutex_lock(&ubi->device_mutex);
         err = ubi_change_vtbl_record(ubi, vol->vol_id, &vtbl_rec);
-        mutex_unlock(&ubi->volumes_mutex);
         vol->upd_marker = 0;
+        mutex_unlock(&ubi->device_mutex);
         return err;
 }
 
diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c
index df5483562b7a..ab64cb56df6e 100644
--- a/drivers/mtd/ubi/vmt.c
+++ b/drivers/mtd/ubi/vmt.c
@@ -198,7 +198,7 @@ static void volume_sysfs_close(struct ubi_volume *vol)
  * %UBI_VOL_NUM_AUTO, this function automatically assign ID to the new volume
  * and saves it in @req->vol_id. Returns zero in case of success and a negative
  * error code in case of failure. Note, the caller has to have the
- * @ubi->volumes_mutex locked.
+ * @ubi->device_mutex locked.
  */
 int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req)
 {
@@ -232,8 +232,8 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req)
                 req->vol_id = vol_id;
         }
 
-        dbg_gen("volume ID %d, %llu bytes, type %d, name %s",
-                vol_id, (unsigned long long)req->bytes,
+        dbg_gen("create device %d, volume %d, %llu bytes, type %d, name %s",
+                ubi->ubi_num, vol_id, (unsigned long long)req->bytes,
                 (int)req->vol_type, req->name);
 
         /* Ensure that this volume does not exist */
@@ -317,10 +317,6 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req)
                 goto out_mapping;
         }
 
-        err = ubi_create_gluebi(ubi, vol);
-        if (err)
-                goto out_cdev;
-
         vol->dev.release = vol_release;
         vol->dev.parent = &ubi->dev;
         vol->dev.devt = dev;
@@ -330,7 +326,7 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req)
         err = device_register(&vol->dev);
         if (err) {
                 ubi_err("cannot register device");
-                goto out_gluebi;
+                goto out_cdev;
         }
 
         err = volume_sysfs_init(ubi, vol);
@@ -358,7 +354,9 @@ int ubi_create_volume(struct ubi_device *ubi, struct ubi_mkvol_req *req)
         ubi->vol_count += 1;
         spin_unlock(&ubi->volumes_lock);
 
-        err = paranoid_check_volumes(ubi);
+        ubi_volume_notify(ubi, vol, UBI_VOLUME_ADDED);
+        if (paranoid_check_volumes(ubi))
+                dbg_err("check failed while creating volume %d", vol_id);
         return err;
 
 out_sysfs:
@@ -373,10 +371,6 @@ out_sysfs:
         do_free = 0;
         get_device(&vol->dev);
         volume_sysfs_close(vol);
-out_gluebi:
-        if (ubi_destroy_gluebi(vol))
-                dbg_err("cannot destroy gluebi for volume %d:%d",
-                        ubi->ubi_num, vol_id);
 out_cdev:
         cdev_del(&vol->cdev);
 out_mapping:
@@ -403,7 +397,7 @@ out_unlock:
  *
  * This function removes volume described by @desc. The volume has to be opened
  * in "exclusive" mode. Returns zero in case of success and a negative error
- * code in case of failure. The caller has to have the @ubi->volumes_mutex
+ * code in case of failure. The caller has to have the @ubi->device_mutex
  * locked.
  */
 int ubi_remove_volume(struct ubi_volume_desc *desc, int no_vtbl)
@@ -412,7 +406,7 @@ int ubi_remove_volume(struct ubi_volume_desc *desc, int no_vtbl)
         struct ubi_device *ubi = vol->ubi;
         int i, err, vol_id = vol->vol_id, reserved_pebs = vol->reserved_pebs;
 
-        dbg_gen("remove UBI volume %d", vol_id);
+        dbg_gen("remove device %d, volume %d", ubi->ubi_num, vol_id);
         ubi_assert(desc->mode == UBI_EXCLUSIVE);
         ubi_assert(vol == ubi->volumes[vol_id]);
 
@@ -431,10 +425,6 @@ int ubi_remove_volume(struct ubi_volume_desc *desc, int no_vtbl)
         ubi->volumes[vol_id] = NULL;
         spin_unlock(&ubi->volumes_lock);
 
-        err = ubi_destroy_gluebi(vol);
-        if (err)
-                goto out_err;
-
         if (!no_vtbl) {
                 err = ubi_change_vtbl_record(ubi, vol_id, NULL);
                 if (err)
@@ -465,8 +455,10 @@ int ubi_remove_volume(struct ubi_volume_desc *desc, int no_vtbl)
         ubi->vol_count -= 1;
         spin_unlock(&ubi->volumes_lock);
 
-        if (!no_vtbl)
-                err = paranoid_check_volumes(ubi);
+        ubi_volume_notify(ubi, vol, UBI_VOLUME_REMOVED);
+        if (!no_vtbl && paranoid_check_volumes(ubi))
+                dbg_err("check failed while removing volume %d", vol_id);
+
         return err;
 
 out_err:
@@ -485,7 +477,7 @@ out_unlock:
  *
  * This function re-sizes the volume and returns zero in case of success, and a
  * negative error code in case of failure. The caller has to have the
- * @ubi->volumes_mutex locked.
+ * @ubi->device_mutex locked.
  */
 int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs)
 {
@@ -498,8 +490,8 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs)
         if (ubi->ro_mode)
                 return -EROFS;
 
-        dbg_gen("re-size volume %d to from %d to %d PEBs",
-                vol_id, vol->reserved_pebs, reserved_pebs);
+        dbg_gen("re-size device %d, volume %d to from %d to %d PEBs",
+                ubi->ubi_num, vol_id, vol->reserved_pebs, reserved_pebs);
 
         if (vol->vol_type == UBI_STATIC_VOLUME &&
             reserved_pebs < vol->used_ebs) {
@@ -587,7 +579,9 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs)
                         (long long)vol->used_ebs * vol->usable_leb_size;
         }
 
-        err = paranoid_check_volumes(ubi);
+        ubi_volume_notify(ubi, vol, UBI_VOLUME_RESIZED);
+        if (paranoid_check_volumes(ubi))
+                dbg_err("check failed while re-sizing volume %d", vol_id);
         return err;
 
 out_acc:
@@ -632,11 +626,12 @@ int ubi_rename_volumes(struct ubi_device *ubi, struct list_head *rename_list)
                         vol->name_len = re->new_name_len;
                         memcpy(vol->name, re->new_name, re->new_name_len + 1);
                         spin_unlock(&ubi->volumes_lock);
+                        ubi_volume_notify(ubi, vol, UBI_VOLUME_RENAMED);
                 }
         }
 
-        if (!err)
-                err = paranoid_check_volumes(ubi);
+        if (!err && paranoid_check_volumes(ubi))
+                ;
         return err;
 }
 
@@ -667,10 +662,6 @@ int ubi_add_volume(struct ubi_device *ubi, struct ubi_volume *vol)
                 return err;
         }
 
-        err = ubi_create_gluebi(ubi, vol);
-        if (err)
-                goto out_cdev;
-
         vol->dev.release = vol_release;
         vol->dev.parent = &ubi->dev;
         vol->dev.devt = dev;
@@ -678,21 +669,19 @@ int ubi_add_volume(struct ubi_device *ubi, struct ubi_volume *vol)
         dev_set_name(&vol->dev, "%s_%d", ubi->ubi_name, vol->vol_id);
         err = device_register(&vol->dev);
         if (err)
-                goto out_gluebi;
+                goto out_cdev;
 
         err = volume_sysfs_init(ubi, vol);
         if (err) {
                 cdev_del(&vol->cdev);
-                err = ubi_destroy_gluebi(vol);
                 volume_sysfs_close(vol);
                 return err;
         }
 
-        err = paranoid_check_volumes(ubi);
+        if (paranoid_check_volumes(ubi))
+                dbg_err("check failed while adding volume %d", vol_id);
         return err;
 
-out_gluebi:
-        err = ubi_destroy_gluebi(vol);
 out_cdev:
         cdev_del(&vol->cdev);
         return err;
@@ -708,12 +697,9 @@ out_cdev:
  */
 void ubi_free_volume(struct ubi_device *ubi, struct ubi_volume *vol)
 {
-        int err;
-
         dbg_gen("free volume %d", vol->vol_id);
 
         ubi->volumes[vol->vol_id] = NULL;
-        err = ubi_destroy_gluebi(vol);
         cdev_del(&vol->cdev);
         volume_sysfs_close(vol);
 }
@@ -868,6 +854,7 @@ fail:
         if (vol)
                 ubi_dbg_dump_vol_info(vol);
         ubi_dbg_dump_vtbl_record(&ubi->vtbl[vol_id], vol_id);
+        dump_stack();
         spin_unlock(&ubi->volumes_lock);
         return -EINVAL;
 }
diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c
index 891534f8210d..2b2472300610 100644
--- a/drivers/mtd/ubi/wl.c
+++ b/drivers/mtd/ubi/wl.c
@@ -55,8 +55,8 @@
  *
  * As it was said, for the UBI sub-system all physical eraseblocks are either
  * "free" or "used". Free eraseblock are kept in the @wl->free RB-tree, while
- * used eraseblocks are kept in @wl->used or @wl->scrub RB-trees, or
- * (temporarily) in the @wl->pq queue.
+ * used eraseblocks are kept in @wl->used, @wl->erroneous, or @wl->scrub
+ * RB-trees, as well as (temporarily) in the @wl->pq queue.
  *
  * When the WL sub-system returns a physical eraseblock, the physical
  * eraseblock is protected from being moved for some "time". For this reason,
@@ -83,6 +83,8 @@
  * used. The former state corresponds to the @wl->free tree. The latter state
  * is split up on several sub-states:
  * o the WL movement is allowed (@wl->used tree);
+ * o the WL movement is disallowed (@wl->erroneous) because the PEB is
+ *   erroneous - e.g., there was a read error;
  * o the WL movement is temporarily prohibited (@wl->pq queue);
  * o scrubbing is needed (@wl->scrub tree).
  *
@@ -653,7 +655,8 @@ static int schedule_erase(struct ubi_device *ubi, struct ubi_wl_entry *e,
 static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
                                 int cancel)
 {
-        int err, scrubbing = 0, torture = 0;
+        int err, scrubbing = 0, torture = 0, protect = 0, erroneous = 0;
+        int vol_id = -1, uninitialized_var(lnum);
         struct ubi_wl_entry *e1, *e2;
         struct ubi_vid_hdr *vid_hdr;
 
@@ -738,68 +741,78 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
                         /*
                          * We are trying to move PEB without a VID header. UBI
                          * always write VID headers shortly after the PEB was
-                         * given, so we have a situation when it did not have
-                         * chance to write it down because it was preempted.
-                         * Just re-schedule the work, so that next time it will
-                         * likely have the VID header in place.
+                         * given, so we have a situation when it has not yet
+                         * had a chance to write it, because it was preempted.
+                         * So add this PEB to the protection queue so far,
+                         * because presumably more data will be written there
+                         * (including the missing VID header), and then we'll
+                         * move it.
                          */
                         dbg_wl("PEB %d has no VID header", e1->pnum);
+                        protect = 1;
                         goto out_not_moved;
                 }
 
                 ubi_err("error %d while reading VID header from PEB %d",
                         err, e1->pnum);
-                if (err > 0)
-                        err = -EIO;
                 goto out_error;
         }
 
+        vol_id = be32_to_cpu(vid_hdr->vol_id);
+        lnum = be32_to_cpu(vid_hdr->lnum);
+
         err = ubi_eba_copy_leb(ubi, e1->pnum, e2->pnum, vid_hdr);
         if (err) {
-                if (err == -EAGAIN)
+                if (err == MOVE_CANCEL_RACE) {
+                        /*
+                         * The LEB has not been moved because the volume is
+                         * being deleted or the PEB has been put meanwhile. We
+                         * should prevent this PEB from being selected for
+                         * wear-leveling movement again, so put it to the
+                         * protection queue.
+                         */
+                        protect = 1;
                         goto out_not_moved;
-                if (err < 0)
-                        goto out_error;
-                if (err == 2) {
-                        /* Target PEB write error, torture it */
+                }
+
+                if (err == MOVE_CANCEL_BITFLIPS || err == MOVE_TARGET_WR_ERR ||
+                    err == MOVE_TARGET_RD_ERR) {
+                        /*
+                         * Target PEB had bit-flips or write error - torture it.
+                         */
                         torture = 1;
                         goto out_not_moved;
                 }
 
-                /*
-                 * The LEB has not been moved because the volume is being
-                 * deleted or the PEB has been put meanwhile. We should prevent
-                 * this PEB from being selected for wear-leveling movement
-                 * again, so put it to the protection queue.
-                 */
-
-                dbg_wl("canceled moving PEB %d", e1->pnum);
-                ubi_assert(err == 1);
-
-                ubi_free_vid_hdr(ubi, vid_hdr);
-                vid_hdr = NULL;
-
-                spin_lock(&ubi->wl_lock);
-                prot_queue_add(ubi, e1);
-                ubi_assert(!ubi->move_to_put);
-                ubi->move_from = ubi->move_to = NULL;
-                ubi->wl_scheduled = 0;
-                spin_unlock(&ubi->wl_lock);
+                if (err == MOVE_SOURCE_RD_ERR) {
+                        /*
+                         * An error happened while reading the source PEB. Do
+                         * not switch to R/O mode in this case, and give the
+                         * upper layers a possibility to recover from this,
+                         * e.g. by unmapping corresponding LEB. Instead, just
+                         * put this PEB to the @ubi->erroneous list to prevent
+                         * UBI from trying to move it over and over again.
+                         */
+                        if (ubi->erroneous_peb_count > ubi->max_erroneous) {
+                                ubi_err("too many erroneous eraseblocks (%d)",
+                                        ubi->erroneous_peb_count);
+                                goto out_error;
+                        }
+                        erroneous = 1;
+                        goto out_not_moved;
+                }
 
-                e1 = NULL;
-                err = schedule_erase(ubi, e2, 0);
-                if (err)
+                if (err < 0)
                         goto out_error;
-                mutex_unlock(&ubi->move_mutex);
-                return 0;
+
+                ubi_assert(0);
         }
 
         /* The PEB has been successfully moved */
-        ubi_free_vid_hdr(ubi, vid_hdr);
-        vid_hdr = NULL;
         if (scrubbing)
-                ubi_msg("scrubbed PEB %d, data moved to PEB %d",
-                        e1->pnum, e2->pnum);
+                ubi_msg("scrubbed PEB %d (LEB %d:%d), data moved to PEB %d",
+                        e1->pnum, vol_id, lnum, e2->pnum);
+        ubi_free_vid_hdr(ubi, vid_hdr);
 
         spin_lock(&ubi->wl_lock);
         if (!ubi->move_to_put) {
@@ -812,8 +825,10 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
 
         err = schedule_erase(ubi, e1, 0);
         if (err) {
-                e1 = NULL;
-                goto out_error;
+                kmem_cache_free(ubi_wl_entry_slab, e1);
+                if (e2)
+                        kmem_cache_free(ubi_wl_entry_slab, e2);
+                goto out_ro;
         }
 
         if (e2) {
@@ -821,10 +836,13 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
                  * Well, the target PEB was put meanwhile, schedule it for
                  * erasure.
                  */
-                dbg_wl("PEB %d was put meanwhile, erase", e2->pnum);
+                dbg_wl("PEB %d (LEB %d:%d) was put meanwhile, erase",
+                       e2->pnum, vol_id, lnum);
                 err = schedule_erase(ubi, e2, 0);
-                if (err)
-                        goto out_error;
+                if (err) {
+                        kmem_cache_free(ubi_wl_entry_slab, e2);
+                        goto out_ro;
+                }
         }
 
         dbg_wl("done");
@@ -837,11 +855,19 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
          * have been changed, schedule it for erasure.
          */
 out_not_moved:
-        dbg_wl("canceled moving PEB %d", e1->pnum);
-        ubi_free_vid_hdr(ubi, vid_hdr);
-        vid_hdr = NULL;
+        if (vol_id != -1)
+                dbg_wl("cancel moving PEB %d (LEB %d:%d) to PEB %d (%d)",
+                       e1->pnum, vol_id, lnum, e2->pnum, err);
+        else
+                dbg_wl("cancel moving PEB %d to PEB %d (%d)",
+                       e1->pnum, e2->pnum, err);
         spin_lock(&ubi->wl_lock);
-        if (scrubbing)
+        if (protect)
+                prot_queue_add(ubi, e1);
+        else if (erroneous) {
+                wl_tree_add(e1, &ubi->erroneous);
+                ubi->erroneous_peb_count += 1;
+        } else if (scrubbing)
                 wl_tree_add(e1, &ubi->scrub);
         else
                 wl_tree_add(e1, &ubi->used);
@@ -850,32 +876,36 @@ out_not_moved:
         ubi->wl_scheduled = 0;
         spin_unlock(&ubi->wl_lock);
 
-        e1 = NULL;
+        ubi_free_vid_hdr(ubi, vid_hdr);
         err = schedule_erase(ubi, e2, torture);
-        if (err)
-                goto out_error;
-
+        if (err) {
+                kmem_cache_free(ubi_wl_entry_slab, e2);
+                goto out_ro;
+        }
         mutex_unlock(&ubi->move_mutex);
         return 0;
 
 out_error:
-        ubi_err("error %d while moving PEB %d to PEB %d",
-                err, e1->pnum, e2->pnum);
-
-        ubi_free_vid_hdr(ubi, vid_hdr);
+        if (vol_id != -1)
+                ubi_err("error %d while moving PEB %d to PEB %d",
+                        err, e1->pnum, e2->pnum);
+        else
+                ubi_err("error %d while moving PEB %d (LEB %d:%d) to PEB %d",
+                        err, e1->pnum, vol_id, lnum, e2->pnum);
         spin_lock(&ubi->wl_lock);
         ubi->move_from = ubi->move_to = NULL;
         ubi->move_to_put = ubi->wl_scheduled = 0;
         spin_unlock(&ubi->wl_lock);
 
-        if (e1)
-                kmem_cache_free(ubi_wl_entry_slab, e1);
-        if (e2)
-                kmem_cache_free(ubi_wl_entry_slab, e2);
-        ubi_ro_mode(ubi);
+        ubi_free_vid_hdr(ubi, vid_hdr);
+        kmem_cache_free(ubi_wl_entry_slab, e1);
+        kmem_cache_free(ubi_wl_entry_slab, e2);
 
+out_ro:
+        ubi_ro_mode(ubi);
         mutex_unlock(&ubi->move_mutex);
-        return err;
+        ubi_assert(err != 0);
+        return err < 0 ? err : -EIO;
 
 out_cancel:
         ubi->wl_scheduled = 0;
@@ -1015,7 +1045,7 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk,
                 /*
                  * If this is not %-EIO, we have no idea what to do. Scheduling
                  * this physical eraseblock for erasure again would cause
-                 * errors again and again. Well, lets switch to RO mode.
+                 * errors again and again. Well, lets switch to R/O mode.
                  */
                 goto out_ro;
         }
@@ -1043,10 +1073,9 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk,
                 ubi_err("no reserved physical eraseblocks");
                 goto out_ro;
         }
-
         spin_unlock(&ubi->volumes_lock);
-        ubi_msg("mark PEB %d as bad", pnum);
 
+        ubi_msg("mark PEB %d as bad", pnum);
         err = ubi_io_mark_bad(ubi, pnum);
         if (err)
                 goto out_ro;
@@ -1056,7 +1085,9 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk,
         ubi->bad_peb_count += 1;
         ubi->good_peb_count -= 1;
         ubi_calculate_reserved(ubi);
-        if (ubi->beb_rsvd_pebs == 0)
+        if (ubi->beb_rsvd_pebs)
+                ubi_msg("%d PEBs left in the reserve", ubi->beb_rsvd_pebs);
+        else
                 ubi_warn("last PEB from the reserved pool was used");
         spin_unlock(&ubi->volumes_lock);
 
@@ -1125,6 +1156,13 @@ retry:
                 } else if (in_wl_tree(e, &ubi->scrub)) {
                         paranoid_check_in_wl_tree(e, &ubi->scrub);
                         rb_erase(&e->u.rb, &ubi->scrub);
+                } else if (in_wl_tree(e, &ubi->erroneous)) {
+                        paranoid_check_in_wl_tree(e, &ubi->erroneous);
+                        rb_erase(&e->u.rb, &ubi->erroneous);
+                        ubi->erroneous_peb_count -= 1;
+                        ubi_assert(ubi->erroneous_peb_count >= 0);
+                        /* Erroneous PEBs should be tortured */
+                        torture = 1;
                 } else {
                         err = prot_queue_del(ubi, e->pnum);
                         if (err) {
@@ -1373,7 +1411,7 @@ int ubi_wl_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si)
         struct ubi_scan_leb *seb, *tmp;
         struct ubi_wl_entry *e;
 
-        ubi->used = ubi->free = ubi->scrub = RB_ROOT;
+        ubi->used = ubi->erroneous = ubi->free = ubi->scrub = RB_ROOT;
         spin_lock_init(&ubi->wl_lock);
         mutex_init(&ubi->move_mutex);
         init_rwsem(&ubi->work_sem);
@@ -1511,6 +1549,7 @@ void ubi_wl_close(struct ubi_device *ubi)
         cancel_pending(ubi);
         protection_queue_destroy(ubi);
         tree_destroy(&ubi->used);
+        tree_destroy(&ubi->erroneous);
         tree_destroy(&ubi->free);
         tree_destroy(&ubi->scrub);
         kfree(ubi->lookuptbl);
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 01f282cd0989..892a9e4e275f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -2206,7 +2206,7 @@ config SKGE_DEBUG
        depends on SKGE && DEBUG_FS
        help
          This option adds the ability to dump driver state for debugging.
-         The file debugfs/skge/ethX displays the state of the internal
+         The file /sys/kernel/debug/skge/ethX displays the state of the internal
          transmit and receive rings.
 
          If unsure, say N.
@@ -2232,7 +2232,7 @@ config SKY2_DEBUG
        depends on SKY2 && DEBUG_FS
        help
          This option adds the ability to dump driver state for debugging.
-         The file debugfs/sky2/ethX displays the state of the internal
+         The file /sys/kernel/debug/sky2/ethX displays the state of the internal
          transmit and receive rings.
 
          If unsure, say N.
@@ -2272,8 +2272,9 @@ config BNX2
 
 config CNIC
         tristate "Broadcom CNIC support"
-        depends on BNX2
-        depends on UIO
+        depends on PCI
+        select BNX2
+        select UIO
         help
           This driver supports offload features of Broadcom NetXtremeII
           gigabit Ethernet cards.
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index 811d3517fce0..11a0ba47b677 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -1366,6 +1366,7 @@ static const struct file_operations tun_fops = {
 static struct miscdevice tun_miscdev = {
         .minor = TUN_MINOR,
         .name = "tun",
+        .devnode = "net/tun",
         .fops = &tun_fops,
 };
 
diff --git a/drivers/net/wimax/i2400m/i2400m.h b/drivers/net/wimax/i2400m/i2400m.h
index 1fe5da4cf0a0..60330f313f27 100644
--- a/drivers/net/wimax/i2400m/i2400m.h
+++ b/drivers/net/wimax/i2400m/i2400m.h
@@ -432,7 +432,7 @@ struct i2400m {
         unsigned ready:1;               /* all probing steps done */
         unsigned rx_reorder:1;          /* RX reorder is enabled */
         u8 trace_msg_from_user;         /* echo rx msgs to 'trace' pipe */
-                                        /* typed u8 so debugfs/u8 can tweak */
+                                        /* typed u8 so /sys/kernel/debug/u8 can tweak */
         enum i2400m_system_state state;
         wait_queue_head_t state_wq;     /* Woken up when on state updates */
 
diff --git a/drivers/net/wireless/ath/ath5k/Kconfig b/drivers/net/wireless/ath/ath5k/Kconfig
index 509b6f94f73b..daf0c83527d8 100644
--- a/drivers/net/wireless/ath/ath5k/Kconfig
+++ b/drivers/net/wireless/ath/ath5k/Kconfig
@@ -28,11 +28,10 @@ config ATH5K_DEBUG
           Say Y, if and you will get debug options for ath5k.
           To use this, you need to mount debugfs:
 
-          mkdir /debug/
-          mount -t debugfs debug /debug/
+          mount -t debugfs debug /sys/kernel/debug
 
           You will get access to files under:
-          /debug/ath5k/phy0/
+          /sys/kernel/debug/ath5k/phy0/
 
           To enable debug, pass the debug level to the debug module
           parameter. For example:
diff --git a/drivers/net/wireless/libertas/README b/drivers/net/wireless/libertas/README
index d860fc375752..ab6a2d518af0 100644
--- a/drivers/net/wireless/libertas/README
+++ b/drivers/net/wireless/libertas/README
@@ -72,7 +72,7 @@ rdrf
         location that is to be read.  This parameter must be specified in
         hexadecimal (its possible to preceed preceding the number with a "0x").
 
-        Path: /debugfs/libertas_wireless/ethX/registers/
+        Path: /sys/kernel/debug/libertas_wireless/ethX/registers/
 
         Usage:
                 echo "0xa123" > rdmac ; cat rdmac
@@ -95,7 +95,7 @@ wrrf
 sleepparams
         This command is used to set the sleepclock configurations
 
-        Path: /debugfs/libertas_wireless/ethX/
+        Path: /sys/kernel/debug/libertas_wireless/ethX/
 
         Usage:
                 cat sleepparams: reads the current sleepclock configuration
@@ -115,7 +115,7 @@ subscribed_events
         The subscribed_events directory contains the interface for the
         subscribed events API.
 
-        Path: /debugfs/libertas_wireless/ethX/subscribed_events/
+        Path: /sys/kernel/debug/libertas_wireless/ethX/subscribed_events/
 
         Each event is represented by a filename. Each filename consists of the
         following three fields:
@@ -165,7 +165,7 @@ subscribed_events
 extscan
         This command is used to do a specific scan.
 
-        Path: /debugfs/libertas_wireless/ethX/
+        Path: /sys/kernel/debug/libertas_wireless/ethX/
 
         Usage: echo "SSID" > extscan
 
@@ -179,7 +179,7 @@ getscantable
         Display the current contents of the driver scan table (ie. get the
         scan results).
 
-        Path: /debugfs/libertas_wireless/ethX/
+        Path: /sys/kernel/debug/libertas_wireless/ethX/
 
         Usage:
                 cat getscantable
@@ -188,7 +188,7 @@ setuserscan
         Initiate a customized scan and retrieve the results
 
 
-        Path: /debugfs/libertas_wireless/ethX/
+        Path: /sys/kernel/debug/libertas_wireless/ethX/
 
     Usage:
        echo "[ARGS]" > setuserscan
diff --git a/drivers/net/wireless/libertas/if_spi.c b/drivers/net/wireless/libertas/if_spi.c
index f8c2898d82b0..06a46d7b3d6c 100644
--- a/drivers/net/wireless/libertas/if_spi.c
+++ b/drivers/net/wireless/libertas/if_spi.c
@@ -43,8 +43,8 @@ struct if_spi_card {
         struct lbs_private              *priv;
         struct libertas_spi_platform_data *pdata;
 
-        char                            helper_fw_name[FIRMWARE_NAME_MAX];
-        char                            main_fw_name[FIRMWARE_NAME_MAX];
+        char                            helper_fw_name[IF_SPI_FW_NAME_MAX];
+        char                            main_fw_name[IF_SPI_FW_NAME_MAX];
 
         /* The card ID and card revision, as reported by the hardware. */
         u16                             card_id;
@@ -1019,9 +1019,9 @@ static int if_spi_calculate_fw_names(u16 card_id,
                 lbs_pr_err("Unsupported chip_id: 0x%02x\n", card_id);
                 return -EAFNOSUPPORT;
         }
-        snprintf(helper_fw, FIRMWARE_NAME_MAX, "libertas/gspi%d_hlp.bin",
+        snprintf(helper_fw, IF_SPI_FW_NAME_MAX, "libertas/gspi%d_hlp.bin",
                  chip_id_to_device_name[i].name);
-        snprintf(main_fw, FIRMWARE_NAME_MAX, "libertas/gspi%d.bin",
+        snprintf(main_fw, IF_SPI_FW_NAME_MAX, "libertas/gspi%d.bin",
                  chip_id_to_device_name[i].name);
         return 0;
 }
diff --git a/drivers/net/wireless/libertas/if_spi.h b/drivers/net/wireless/libertas/if_spi.h
index 2103869cc5b0..f87eec410848 100644
--- a/drivers/net/wireless/libertas/if_spi.h
+++ b/drivers/net/wireless/libertas/if_spi.h
@@ -22,6 +22,9 @@
 #define IF_SPI_CMD_BUF_SIZE 2400
 
 /***************** Firmware *****************/
+
+#define IF_SPI_FW_NAME_MAX 30
+
 struct chip_ident {
         u16 chip_id;
         u16 name;
diff --git a/drivers/net/wireless/libertas/if_usb.c b/drivers/net/wireless/libertas/if_usb.c
index d649caebf08a..1844c5adf6e9 100644
--- a/drivers/net/wireless/libertas/if_usb.c
+++ b/drivers/net/wireless/libertas/if_usb.c
@@ -61,11 +61,9 @@ static ssize_t if_usb_firmware_set(struct device *dev,
 {
         struct lbs_private *priv = to_net_dev(dev)->ml_priv;
         struct if_usb_card *cardp = priv->card;
-        char fwname[FIRMWARE_NAME_MAX];
         int ret;
 
-        sscanf(buf, "%29s", fwname); /* FIRMWARE_NAME_MAX - 1 = 29 */
-        ret = if_usb_prog_firmware(cardp, fwname, BOOT_CMD_UPDATE_FW);
+        ret = if_usb_prog_firmware(cardp, buf, BOOT_CMD_UPDATE_FW);
         if (ret == 0)
                 return count;
 
@@ -88,11 +86,9 @@ static ssize_t if_usb_boot2_set(struct device *dev,
 {
         struct lbs_private *priv = to_net_dev(dev)->ml_priv;
         struct if_usb_card *cardp = priv->card;
-        char fwname[FIRMWARE_NAME_MAX];
         int ret;
 
-        sscanf(buf, "%29s", fwname); /* FIRMWARE_NAME_MAX - 1 = 29 */
-        ret = if_usb_prog_firmware(cardp, fwname, BOOT_CMD_UPDATE_BOOT2);
+        ret = if_usb_prog_firmware(cardp, buf, BOOT_CMD_UPDATE_BOOT2);
         if (ret == 0)
                 return count;
 
diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c
index f67325387902..8d88daeed0c6 100644
--- a/drivers/net/xen-netfront.c
+++ b/drivers/net/xen-netfront.c
@@ -1212,7 +1212,7 @@ static int __devinit netfront_probe(struct xenbus_device *dev,
         }
 
         info = netdev_priv(netdev);
-        dev->dev.driver_data = info;
+        dev_set_drvdata(&dev->dev, info);
 
         err = register_netdev(info->netdev);
         if (err) {
@@ -1233,7 +1233,7 @@ static int __devinit netfront_probe(struct xenbus_device *dev,
 
  fail:
         free_netdev(netdev);
-        dev->dev.driver_data = NULL;
+        dev_set_drvdata(&dev->dev, NULL);
         return err;
 }
 
@@ -1275,7 +1275,7 @@ static void xennet_disconnect_backend(struct netfront_info *info)
  */
 static int netfront_resume(struct xenbus_device *dev)
 {
-        struct netfront_info *info = dev->dev.driver_data;
+        struct netfront_info *info = dev_get_drvdata(&dev->dev);
 
         dev_dbg(&dev->dev, "%s\n", dev->nodename);
 
@@ -1600,7 +1600,7 @@ static int xennet_connect(struct net_device *dev)
 static void backend_changed(struct xenbus_device *dev,
                             enum xenbus_state backend_state)
 {
-        struct netfront_info *np = dev->dev.driver_data;
+        struct netfront_info *np = dev_get_drvdata(&dev->dev);
         struct net_device *netdev = np->netdev;
 
         dev_dbg(&dev->dev, "%s\n", xenbus_strstate(backend_state));
@@ -1774,7 +1774,7 @@ static struct xenbus_device_id netfront_ids[] = {
 
 static int __devexit xennet_remove(struct xenbus_device *dev)
 {
-        struct netfront_info *info = dev->dev.driver_data;
+        struct netfront_info *info = dev_get_drvdata(&dev->dev);
 
         dev_dbg(&dev->dev, "%s\n", dev->nodename);
 
diff --git a/drivers/parisc/eisa.c b/drivers/parisc/eisa.c
index f415fdd9a885..5b89f404e668 100644
--- a/drivers/parisc/eisa.c
+++ b/drivers/parisc/eisa.c
@@ -373,7 +373,7 @@ static int __init eisa_probe(struct parisc_device *dev)
         if (result >= 0) {
                 /* FIXME : Don't enumerate the bus twice. */
                 eisa_dev.root.dev = &dev->dev;
-                dev->dev.driver_data = &eisa_dev.root;
+                dev_set_drvdata(&dev->dev, &eisa_dev.root);
                 eisa_dev.root.bus_base_addr = 0;
                 eisa_dev.root.res = &eisa_dev.hba.io_space;
                 eisa_dev.root.slots = result;
diff --git a/drivers/parisc/sba_iommu.c b/drivers/parisc/sba_iommu.c
index e5999c4cedc8..d46dd57450ac 100644
--- a/drivers/parisc/sba_iommu.c
+++ b/drivers/parisc/sba_iommu.c
@@ -2010,7 +2010,7 @@ void __init sba_init(void)
 void * sba_get_iommu(struct parisc_device *pci_hba)
 {
         struct parisc_device *sba_dev = parisc_parent(pci_hba);
-        struct sba_device *sba = sba_dev->dev.driver_data;
+        struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
         char t = sba_dev->id.hw_type;
         int iocnum = (pci_hba->hw_path >> 3);   /* rope # */
 
@@ -2031,7 +2031,7 @@ void * sba_get_iommu(struct parisc_device *pci_hba)
 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
 {
         struct parisc_device *sba_dev = parisc_parent(pci_hba);
-        struct sba_device *sba = sba_dev->dev.driver_data;
+        struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
         char t = sba_dev->id.hw_type;
         int i;
         int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1));  /* rope # */
@@ -2073,7 +2073,7 @@ void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
 {
         struct parisc_device *sba_dev = parisc_parent(pci_hba);
-        struct sba_device *sba = sba_dev->dev.driver_data;
+        struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
         char t = sba_dev->id.hw_type;
         int base, size;
         int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1));  /* rope # */
diff --git a/drivers/parport/parport_gsc.c b/drivers/parport/parport_gsc.c
index ea31a452b153..5d6de380e42b 100644
--- a/drivers/parport/parport_gsc.c
+++ b/drivers/parport/parport_gsc.c
@@ -376,14 +376,14 @@ static int __devinit parport_init_chip(struct parisc_device *dev)
                         /* PARPORT_IRQ_NONE */ PARPORT_DMA_NONE, NULL);
         if (p)
                 parport_count++;
-        dev->dev.driver_data = p;
+        dev_set_drvdata(&dev->dev, p);
 
         return 0;
 }
 
 static int __devexit parport_remove_chip(struct parisc_device *dev)
 {
-        struct parport *p = dev->dev.driver_data;
+        struct parport *p = dev_get_drvdata(&dev->dev);
         if (p) {
                 struct parport_gsc_private *priv = p->private_data;
                 struct parport_operations *ops = p->ops;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 1a91bf9687af..07bbb9b3b93f 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -24,6 +24,11 @@
 #include <asm/setup.h>
 #include "pci.h"
 
+const char *pci_power_names[] = {
+        "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
+};
+EXPORT_SYMBOL_GPL(pci_power_names);
+
 unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT;
 
 #ifdef CONFIG_PCI_DOMAINS
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index e39982503863..13ffdc35ea0e 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -275,7 +275,7 @@ static void pcie_device_init(struct pci_dev *parent, struct pcie_device *dev,
         memset(device, 0, sizeof(struct device));
         device->bus = &pcie_port_bus_type;
         device->driver = NULL;
-        device->driver_data = NULL;
+        dev_set_drvdata(device, NULL);
         device->release = release_pcie_device;  /* callback to free pcie dev */
         dev_set_name(device, "%s:pcie%02x",
                  pci_name(parent), get_descriptor_id(port_type, service_type));
diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c
index 47cab31ff6e4..304ff6d5cf3b 100644
--- a/drivers/pcmcia/ds.c
+++ b/drivers/pcmcia/ds.c
@@ -394,7 +394,7 @@ static int pcmcia_device_probe(struct device * dev)
         p_drv = to_pcmcia_drv(dev->driver);
         s = p_dev->socket;
 
-        /* The PCMCIA code passes the match data in via dev->driver_data
+        /* The PCMCIA code passes the match data in via dev_set_drvdata(dev)
          * which is an ugly hack. Once the driver probe is called it may
          * and often will overwrite the match data so we must save it first
          *
@@ -404,7 +404,7 @@ static int pcmcia_device_probe(struct device * dev)
          * call which will then check whether there are two
          * pseudo devices, and if not, add the second one.
          */
-        did = p_dev->dev.driver_data;
+        did = dev_get_drvdata(&p_dev->dev);
 
         ds_dev_dbg(1, dev, "trying to bind to %s\n", p_drv->drv.name);
 
@@ -499,7 +499,7 @@ static int pcmcia_device_remove(struct device * dev)
          * pseudo multi-function card, we need to unbind
          * all devices
          */
-        did = p_dev->dev.driver_data;
+        did = dev_get_drvdata(&p_dev->dev);
         if (did && (did->match_flags & PCMCIA_DEV_ID_MATCH_DEVICE_NO) &&
             (p_dev->socket->device_count != 0) &&
             (p_dev->device_no == 0))
@@ -828,7 +828,6 @@ static int pcmcia_load_firmware(struct pcmcia_device *dev, char * filename)
 {
         struct pcmcia_socket *s = dev->socket;
         const struct firmware *fw;
-        char path[FIRMWARE_NAME_MAX];
         int ret = -ENOMEM;
         int no_funcs;
         int old_funcs;
@@ -839,16 +838,7 @@ static int pcmcia_load_firmware(struct pcmcia_device *dev, char * filename)
 
         ds_dev_dbg(1, &dev->dev, "trying to load CIS file %s\n", filename);
 
-        if (strlen(filename) > (FIRMWARE_NAME_MAX - 1)) {
-                dev_printk(KERN_WARNING, &dev->dev,
-                           "pcmcia: CIS filename is too long [%s]\n",
-                           filename);
-                return -EINVAL;
-        }
-
-        snprintf(path, sizeof(path), "%s", filename);
-
-        if (request_firmware(&fw, path, &dev->dev) == 0) {
+        if (request_firmware(&fw, filename, &dev->dev) == 0) {
                 if (fw->size >= CISTPL_MAX_CIS_SIZE) {
                         ret = -EINVAL;
                         dev_printk(KERN_ERR, &dev->dev,
@@ -988,7 +978,7 @@ static inline int pcmcia_devmatch(struct pcmcia_device *dev,
                         return 0;
         }
 
-        dev->dev.driver_data = (void *) did;
+        dev_set_drvdata(&dev->dev, did);
 
         return 1;
 }
diff --git a/drivers/pcmcia/pcmcia_ioctl.c b/drivers/pcmcia/pcmcia_ioctl.c
index 1703b20cad5d..6095f8daecd7 100644
--- a/drivers/pcmcia/pcmcia_ioctl.c
+++ b/drivers/pcmcia/pcmcia_ioctl.c
@@ -915,12 +915,9 @@ static int ds_ioctl(struct inode * inode, struct file * file,
                 err = -EPERM;
                 goto free_out;
         } else {
-                static int printed = 0;
-                if (!printed) {
-                        printk(KERN_WARNING "2.6. kernels use pcmciamtd instead of memory_cs.c and do not require special\n");
-                        printk(KERN_WARNING "MTD handling any more.\n");
-                        printed++;
-                }
+                        printk_once(KERN_WARNING
+                                "2.6. kernels use pcmciamtd instead of memory_cs.c and do not require special\n");
+                        printk_once(KERN_WARNING "MTD handling any more.\n");
         }
         err = -EINVAL;
         goto free_out;
diff --git a/drivers/s390/char/con3215.c b/drivers/s390/char/con3215.c
index b79f31add39c..04dc734805c6 100644
--- a/drivers/s390/char/con3215.c
+++ b/drivers/s390/char/con3215.c
@@ -364,7 +364,7 @@ static void raw3215_irq(struct ccw_device *cdev, unsigned long intparm,
         int cstat, dstat;
         int count;
 
-        raw = cdev->dev.driver_data;
+        raw = dev_get_drvdata(&cdev->dev);
         req = (struct raw3215_req *) intparm;
         cstat = irb->scsw.cmd.cstat;
         dstat = irb->scsw.cmd.dstat;
@@ -652,7 +652,7 @@ static int raw3215_probe (struct ccw_device *cdev)
         int line;
 
         /* Console is special. */
-        if (raw3215[0] && (cdev->dev.driver_data == raw3215[0]))
+        if (raw3215[0] && (raw3215[0] == dev_get_drvdata(&cdev->dev)))
                 return 0;
         raw = kmalloc(sizeof(struct raw3215_info) +
                       RAW3215_INBUF_SIZE, GFP_KERNEL|GFP_DMA);
@@ -686,7 +686,7 @@ static int raw3215_probe (struct ccw_device *cdev)
         }
         init_waitqueue_head(&raw->empty_wait);
 
-        cdev->dev.driver_data = raw;
+        dev_set_drvdata(&cdev->dev, raw);
         cdev->handler = raw3215_irq;
 
         return 0;
@@ -697,9 +697,9 @@ static void raw3215_remove (struct ccw_device *cdev)
         struct raw3215_info *raw;
 
         ccw_device_set_offline(cdev);
-        raw = cdev->dev.driver_data;
+        raw = dev_get_drvdata(&cdev->dev);
         if (raw) {
-                cdev->dev.driver_data = NULL;
+                dev_set_drvdata(&cdev->dev, NULL);
                 kfree(raw->buffer);
                 kfree(raw);
         }
@@ -709,7 +709,7 @@ static int raw3215_set_online (struct ccw_device *cdev)
 {
         struct raw3215_info *raw;
 
-        raw = cdev->dev.driver_data;
+        raw = dev_get_drvdata(&cdev->dev);
         if (!raw)
                 return -ENODEV;
 
@@ -720,7 +720,7 @@ static int raw3215_set_offline (struct ccw_device *cdev)
 {
         struct raw3215_info *raw;
 
-        raw = cdev->dev.driver_data;
+        raw = dev_get_drvdata(&cdev->dev);
         if (!raw)
                 return -ENODEV;
 
@@ -898,7 +898,7 @@ static int __init con3215_init(void)
         raw->buffer = (char *) alloc_bootmem_low(RAW3215_BUFFER_SIZE);
         raw->inbuf = (char *) alloc_bootmem_low(RAW3215_INBUF_SIZE);
         raw->cdev = cdev;
-        cdev->dev.driver_data = raw;
+        dev_set_drvdata(&cdev->dev, raw);
         cdev->handler = raw3215_irq;
 
         raw->flags |= RAW3215_FIXED;
diff --git a/drivers/s390/char/raw3270.c b/drivers/s390/char/raw3270.c
index 81c151b5f0ac..acab7b2dfe8a 100644
--- a/drivers/s390/char/raw3270.c
+++ b/drivers/s390/char/raw3270.c
@@ -357,7 +357,7 @@ raw3270_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb)
         struct raw3270_request *rq;
         int rc;
 
-        rp = (struct raw3270 *) cdev->dev.driver_data;
+        rp = dev_get_drvdata(&cdev->dev);
         if (!rp)
                 return;
         rq = (struct raw3270_request *) intparm;
@@ -831,7 +831,7 @@ raw3270_setup_device(struct ccw_device *cdev, struct raw3270 *rp, char *ascebc)
         if (rp->minor == -1)
                 return -EUSERS;
         rp->cdev = cdev;
-        cdev->dev.driver_data = rp;
+        dev_set_drvdata(&cdev->dev, rp);
         cdev->handler = raw3270_irq;
         return 0;
 }
@@ -1112,7 +1112,7 @@ raw3270_delete_device(struct raw3270 *rp)
         /* Disconnect from ccw_device. */
         cdev = rp->cdev;
         rp->cdev = NULL;
-        cdev->dev.driver_data = NULL;
+        dev_set_drvdata(&cdev->dev, NULL);
         cdev->handler = NULL;
 
         /* Put ccw_device structure. */
@@ -1136,7 +1136,7 @@ static ssize_t
 raw3270_model_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
         return snprintf(buf, PAGE_SIZE, "%i\n",
-                        ((struct raw3270 *) dev->driver_data)->model);
+                        ((struct raw3270 *) dev_get_drvdata(dev))->model);
 }
 static DEVICE_ATTR(model, 0444, raw3270_model_show, NULL);
 
@@ -1144,7 +1144,7 @@ static ssize_t
 raw3270_rows_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
         return snprintf(buf, PAGE_SIZE, "%i\n",
-                        ((struct raw3270 *) dev->driver_data)->rows);
+                        ((struct raw3270 *) dev_get_drvdata(dev))->rows);
 }
 static DEVICE_ATTR(rows, 0444, raw3270_rows_show, NULL);
 
@@ -1152,7 +1152,7 @@ static ssize_t
 raw3270_columns_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
         return snprintf(buf, PAGE_SIZE, "%i\n",
-                        ((struct raw3270 *) dev->driver_data)->cols);
+                        ((struct raw3270 *) dev_get_drvdata(dev))->cols);
 }
 static DEVICE_ATTR(columns, 0444, raw3270_columns_show, NULL);
 
@@ -1289,7 +1289,7 @@ raw3270_remove (struct ccw_device *cdev)
         struct raw3270_view *v;
         struct raw3270_notifier *np;
 
-        rp = cdev->dev.driver_data;
+        rp = dev_get_drvdata(&cdev->dev);
         /*
          * _remove is the opposite of _probe; it's probe that
          * should set up rp.  raw3270_remove gets entered for
@@ -1337,7 +1337,7 @@ raw3270_set_offline (struct ccw_device *cdev)
 {
         struct raw3270 *rp;
 
-        rp = cdev->dev.driver_data;
+        rp = dev_get_drvdata(&cdev->dev);
         if (test_bit(RAW3270_FLAGS_CONSOLE, &rp->flags))
                 return -EBUSY;
         raw3270_remove(cdev);
diff --git a/drivers/s390/char/tape_34xx.c b/drivers/s390/char/tape_34xx.c
index 144d2a5e1a92..5a519fac37b7 100644
--- a/drivers/s390/char/tape_34xx.c
+++ b/drivers/s390/char/tape_34xx.c
@@ -1289,7 +1289,7 @@ static int
 tape_34xx_online(struct ccw_device *cdev)
 {
         return tape_generic_online(
-                cdev->dev.driver_data,
+                dev_get_drvdata(&cdev->dev),
                 &tape_discipline_34xx
         );
 }
diff --git a/drivers/s390/char/tape_3590.c b/drivers/s390/char/tape_3590.c
index 23e6598bc4b5..418f72dd39b4 100644
--- a/drivers/s390/char/tape_3590.c
+++ b/drivers/s390/char/tape_3590.c
@@ -1703,7 +1703,7 @@ static struct ccw_device_id tape_3590_ids[] = {
 static int
 tape_3590_online(struct ccw_device *cdev)
 {
-        return tape_generic_online(cdev->dev.driver_data,
+        return tape_generic_online(dev_get_drvdata(&cdev->dev),
                                    &tape_discipline_3590);
 }
 
diff --git a/drivers/s390/char/tape_core.c b/drivers/s390/char/tape_core.c
index 3ebaa8eb5c86..595aa04cfd01 100644
--- a/drivers/s390/char/tape_core.c
+++ b/drivers/s390/char/tape_core.c
@@ -92,7 +92,7 @@ tape_medium_state_show(struct device *dev, struct device_attribute *attr, char *
 {
         struct tape_device *tdev;
 
-        tdev = (struct tape_device *) dev->driver_data;
+        tdev = dev_get_drvdata(dev);
         return scnprintf(buf, PAGE_SIZE, "%i\n", tdev->medium_state);
 }
 
@@ -104,7 +104,7 @@ tape_first_minor_show(struct device *dev, struct device_attribute *attr, char *b
 {
         struct tape_device *tdev;
 
-        tdev = (struct tape_device *) dev->driver_data;
+        tdev = dev_get_drvdata(dev);
         return scnprintf(buf, PAGE_SIZE, "%i\n", tdev->first_minor);
 }
 
@@ -116,7 +116,7 @@ tape_state_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
         struct tape_device *tdev;
 
-        tdev = (struct tape_device *) dev->driver_data;
+        tdev = dev_get_drvdata(dev);
         return scnprintf(buf, PAGE_SIZE, "%s\n", (tdev->first_minor < 0) ?
                 "OFFLINE" : tape_state_verbose[tdev->tape_state]);
 }
@@ -130,7 +130,7 @@ tape_operation_show(struct device *dev, struct device_attribute *attr, char *buf
         struct tape_device *tdev;
         ssize_t rc;
 
-        tdev = (struct tape_device *) dev->driver_data;
+        tdev = dev_get_drvdata(dev);
         if (tdev->first_minor < 0)
                 return scnprintf(buf, PAGE_SIZE, "N/A\n");
 
@@ -156,7 +156,7 @@ tape_blocksize_show(struct device *dev, struct device_attribute *attr, char *buf
 {
         struct tape_device *tdev;
 
-        tdev = (struct tape_device *) dev->driver_data;
+        tdev = dev_get_drvdata(dev);
 
         return scnprintf(buf, PAGE_SIZE, "%i\n", tdev->char_data.block_size);
 }
@@ -440,7 +440,7 @@ tape_generic_offline(struct ccw_device *cdev)
 {
         struct tape_device *device;
 
-        device = cdev->dev.driver_data;
+        device = dev_get_drvdata(&cdev->dev);
         if (!device) {
                 return -ENODEV;
         }
@@ -583,7 +583,7 @@ tape_generic_probe(struct ccw_device *cdev)
                 tape_put_device(device);
                 return ret;
         }
-        cdev->dev.driver_data = device;
+        dev_set_drvdata(&cdev->dev, device);
         cdev->handler = __tape_do_irq;
         device->cdev = cdev;
         ccw_device_get_id(cdev, &dev_id);
@@ -622,7 +622,7 @@ tape_generic_remove(struct ccw_device *cdev)
 {
         struct tape_device *    device;
 
-        device = cdev->dev.driver_data;
+        device = dev_get_drvdata(&cdev->dev);
         if (!device) {
                 return;
         }
@@ -662,9 +662,9 @@ tape_generic_remove(struct ccw_device *cdev)
                         tape_cleanup_device(device);
         }
 
-        if (cdev->dev.driver_data != NULL) {
+        if (!dev_get_drvdata(&cdev->dev)) {
                 sysfs_remove_group(&cdev->dev.kobj, &tape_attr_group);
-                cdev->dev.driver_data = tape_put_device(cdev->dev.driver_data);
+                dev_set_drvdata(&cdev->dev, tape_put_device(dev_get_drvdata(&cdev->dev)));
         }
 }
 
@@ -1060,7 +1060,7 @@ __tape_do_irq (struct ccw_device *cdev, unsigned long intparm, struct irb *irb)
         struct tape_request *request;
         int rc;
 
-        device = (struct tape_device *) cdev->dev.driver_data;
+        device = dev_get_drvdata(&cdev->dev);
         if (device == NULL) {
                 return;
         }
diff --git a/drivers/s390/char/vmlogrdr.c b/drivers/s390/char/vmlogrdr.c
index e925808c2149..411cfa3c7719 100644
--- a/drivers/s390/char/vmlogrdr.c
+++ b/drivers/s390/char/vmlogrdr.c
@@ -504,7 +504,7 @@ static ssize_t vmlogrdr_autopurge_store(struct device * dev,
                                         struct device_attribute *attr,
                                         const char * buf, size_t count)
 {
-        struct vmlogrdr_priv_t *priv = dev->driver_data;
+        struct vmlogrdr_priv_t *priv = dev_get_drvdata(dev);
         ssize_t ret = count;
 
         switch (buf[0]) {
@@ -525,7 +525,7 @@ static ssize_t vmlogrdr_autopurge_show(struct device *dev,
                                        struct device_attribute *attr,
                                        char *buf)
 {
-        struct vmlogrdr_priv_t *priv = dev->driver_data;
+        struct vmlogrdr_priv_t *priv = dev_get_drvdata(dev);
         return sprintf(buf, "%u\n", priv->autopurge);
 }
 
@@ -541,7 +541,7 @@ static ssize_t vmlogrdr_purge_store(struct device * dev,
 
         char cp_command[80];
         char cp_response[80];
-        struct vmlogrdr_priv_t *priv = dev->driver_data;
+        struct vmlogrdr_priv_t *priv = dev_get_drvdata(dev);
 
         if (buf[0] != '1')
                 return -EINVAL;
@@ -578,7 +578,7 @@ static ssize_t vmlogrdr_autorecording_store(struct device *dev,
                                             struct device_attribute *attr,
                                             const char *buf, size_t count)
 {
-        struct vmlogrdr_priv_t *priv = dev->driver_data;
+        struct vmlogrdr_priv_t *priv = dev_get_drvdata(dev);
         ssize_t ret = count;
 
         switch (buf[0]) {
@@ -599,7 +599,7 @@ static ssize_t vmlogrdr_autorecording_show(struct device *dev,
                                            struct device_attribute *attr,
                                            char *buf)
 {
-        struct vmlogrdr_priv_t *priv = dev->driver_data;
+        struct vmlogrdr_priv_t *priv = dev_get_drvdata(dev);
         return sprintf(buf, "%u\n", priv->autorecording);
 }
 
@@ -612,7 +612,7 @@ static ssize_t vmlogrdr_recording_store(struct device * dev,
                                         struct device_attribute *attr,
                                         const char * buf, size_t count)
 {
-        struct vmlogrdr_priv_t *priv = dev->driver_data;
+        struct vmlogrdr_priv_t *priv = dev_get_drvdata(dev);
         ssize_t ret;
 
         switch (buf[0]) {
diff --git a/drivers/s390/char/vmur.c b/drivers/s390/char/vmur.c
index 92458219a9e9..7d9e67cb6471 100644
--- a/drivers/s390/char/vmur.c
+++ b/drivers/s390/char/vmur.c
@@ -80,11 +80,11 @@ static DEFINE_MUTEX(vmur_mutex);
  *
  * Each ur device (urd) contains a reference to its corresponding ccw device
  * (cdev) using the urd->cdev pointer. Each ccw device has a reference to the
- * ur device using the cdev->dev.driver_data pointer.
+ * ur device using dev_get_drvdata(&cdev->dev) pointer.
  *
  * urd references:
  * - ur_probe gets a urd reference, ur_remove drops the reference
- *   (cdev->dev.driver_data)
+ *   dev_get_drvdata(&cdev->dev)
  * - ur_open gets a urd reference, ur_relase drops the reference
  *   (urf->urd)
  *
@@ -92,7 +92,7 @@ static DEFINE_MUTEX(vmur_mutex);
  * - urdev_alloc get a cdev reference (urd->cdev)
  * - urdev_free drops the cdev reference (urd->cdev)
  *
- * Setting and clearing of cdev->dev.driver_data is protected by the ccwdev lock
+ * Setting and clearing of dev_get_drvdata(&cdev->dev) is protected by the ccwdev lock
  */
 static struct urdev *urdev_alloc(struct ccw_device *cdev)
 {
@@ -131,7 +131,7 @@ static struct urdev *urdev_get_from_cdev(struct ccw_device *cdev)
         unsigned long flags;
 
         spin_lock_irqsave(get_ccwdev_lock(cdev), flags);
-        urd = cdev->dev.driver_data;
+        urd = dev_get_drvdata(&cdev->dev);
         if (urd)
                 urdev_get(urd);
         spin_unlock_irqrestore(get_ccwdev_lock(cdev), flags);
@@ -310,7 +310,7 @@ static void ur_int_handler(struct ccw_device *cdev, unsigned long intparm,
                 TRACE("ur_int_handler: unsolicited interrupt\n");
                 return;
         }
-        urd = cdev->dev.driver_data;
+        urd = dev_get_drvdata(&cdev->dev);
         BUG_ON(!urd);
         /* On special conditions irb is an error pointer */
         if (IS_ERR(irb))
@@ -856,7 +856,7 @@ static int ur_probe(struct ccw_device *cdev)
                 goto fail_remove_attr;
         }
         spin_lock_irq(get_ccwdev_lock(cdev));
-        cdev->dev.driver_data = urd;
+        dev_set_drvdata(&cdev->dev, urd);
         spin_unlock_irq(get_ccwdev_lock(cdev));
 
         mutex_unlock(&vmur_mutex);
@@ -996,8 +996,8 @@ static void ur_remove(struct ccw_device *cdev)
         ur_remove_attributes(&cdev->dev);
 
         spin_lock_irqsave(get_ccwdev_lock(cdev), flags);
-        urdev_put(cdev->dev.driver_data);
-        cdev->dev.driver_data = NULL;
+        urdev_put(dev_get_drvdata(&cdev->dev));
+        dev_set_drvdata(&cdev->dev, NULL);
         spin_unlock_irqrestore(get_ccwdev_lock(cdev), flags);
 
         mutex_unlock(&vmur_mutex);
diff --git a/drivers/s390/net/claw.c b/drivers/s390/net/claw.c
index d40f7a934f94..f370f8d460a7 100644
--- a/drivers/s390/net/claw.c
+++ b/drivers/s390/net/claw.c
@@ -290,7 +290,7 @@ claw_probe(struct ccwgroup_device *cgdev)
         if (!get_device(&cgdev->dev))
                 return -ENODEV;
         privptr = kzalloc(sizeof(struct claw_privbk), GFP_KERNEL);
-        cgdev->dev.driver_data = privptr;
+        dev_set_drvdata(&cgdev->dev, privptr);
         if (privptr == NULL) {
                 probe_error(cgdev);
                 put_device(&cgdev->dev);
@@ -597,14 +597,14 @@ claw_irq_handler(struct ccw_device *cdev,
 
         CLAW_DBF_TEXT(4, trace, "clawirq");
         /* Bypass all 'unsolicited interrupts' */
-        if (!cdev->dev.driver_data) {
+        privptr = dev_get_drvdata(&cdev->dev);
+        if (!privptr) {
                 dev_warn(&cdev->dev, "An uninitialized CLAW device received an"
                         " IRQ, c-%02x d-%02x\n",
                         irb->scsw.cmd.cstat, irb->scsw.cmd.dstat);
                 CLAW_DBF_TEXT(2, trace, "badirq");
                 return;
         }
-        privptr = (struct claw_privbk *)cdev->dev.driver_data;
 
         /* Try to extract channel from driver data. */
         if (privptr->channel[READ].cdev == cdev)
@@ -1986,9 +1986,9 @@ probe_error( struct ccwgroup_device *cgdev)
         struct claw_privbk *privptr;
 
         CLAW_DBF_TEXT(4, trace, "proberr");
-        privptr = (struct claw_privbk *) cgdev->dev.driver_data;
+        privptr = dev_get_drvdata(&cgdev->dev);
         if (privptr != NULL) {
-                cgdev->dev.driver_data = NULL;
+                dev_set_drvdata(&cgdev->dev, NULL);
                 kfree(privptr->p_env);
                 kfree(privptr->p_mtc_envelope);
                 kfree(privptr);
@@ -2917,9 +2917,9 @@ claw_new_device(struct ccwgroup_device *cgdev)
         dev_info(&cgdev->dev, "add for %s\n",
                  dev_name(&cgdev->cdev[READ]->dev));
         CLAW_DBF_TEXT(2, setup, "new_dev");
-        privptr = cgdev->dev.driver_data;
-        cgdev->cdev[READ]->dev.driver_data = privptr;
-        cgdev->cdev[WRITE]->dev.driver_data = privptr;
+        privptr = dev_get_drvdata(&cgdev->dev);
+        dev_set_drvdata(&cgdev->cdev[READ]->dev, privptr);
+        dev_set_drvdata(&cgdev->cdev[WRITE]->dev, privptr);
         if (!privptr)
                 return -ENODEV;
         p_env = privptr->p_env;
@@ -2956,9 +2956,9 @@ claw_new_device(struct ccwgroup_device *cgdev)
                 goto out;
         }
         dev->ml_priv = privptr;
-        cgdev->dev.driver_data = privptr;
-        cgdev->cdev[READ]->dev.driver_data = privptr;
-        cgdev->cdev[WRITE]->dev.driver_data = privptr;
+        dev_set_drvdata(&cgdev->dev, privptr);
+        dev_set_drvdata(&cgdev->cdev[READ]->dev, privptr);
+        dev_set_drvdata(&cgdev->cdev[WRITE]->dev, privptr);
         /* sysfs magic */
         SET_NETDEV_DEV(dev, &cgdev->dev);
         if (register_netdev(dev) != 0) {
@@ -3024,7 +3024,7 @@ claw_shutdown_device(struct ccwgroup_device *cgdev)
         int     ret;
 
         CLAW_DBF_TEXT_(2, setup, "%s", dev_name(&cgdev->dev));
-        priv = cgdev->dev.driver_data;
+        priv = dev_get_drvdata(&cgdev->dev);
         if (!priv)
                 return -ENODEV;
         ndev = priv->channel[READ].ndev;
@@ -3054,7 +3054,7 @@ claw_remove_device(struct ccwgroup_device *cgdev)
 
         BUG_ON(!cgdev);
         CLAW_DBF_TEXT_(2, setup, "%s", dev_name(&cgdev->dev));
-        priv = cgdev->dev.driver_data;
+        priv = dev_get_drvdata(&cgdev->dev);
         BUG_ON(!priv);
         dev_info(&cgdev->dev, " will be removed.\n");
         if (cgdev->state == CCWGROUP_ONLINE)
@@ -3069,9 +3069,9 @@ claw_remove_device(struct ccwgroup_device *cgdev)
         kfree(priv->channel[1].irb);
         priv->channel[1].irb=NULL;
         kfree(priv);
-        cgdev->dev.driver_data=NULL;
-        cgdev->cdev[READ]->dev.driver_data = NULL;
-        cgdev->cdev[WRITE]->dev.driver_data = NULL;
+        dev_set_drvdata(&cgdev->dev, NULL);
+        dev_set_drvdata(&cgdev->cdev[READ]->dev, NULL);
+        dev_set_drvdata(&cgdev->cdev[WRITE]->dev, NULL);
         put_device(&cgdev->dev);
 
         return;
@@ -3087,7 +3087,7 @@ claw_hname_show(struct device *dev, struct device_attribute *attr, char *buf)
         struct claw_privbk *priv;
         struct claw_env *  p_env;
 
-        priv = dev->driver_data;
+        priv = dev_get_drvdata(dev);
         if (!priv)
                 return -ENODEV;
         p_env = priv->p_env;
@@ -3101,7 +3101,7 @@ claw_hname_write(struct device *dev, struct device_attribute *attr,
         struct claw_privbk *priv;
         struct claw_env *  p_env;
 
-        priv = dev->driver_data;
+        priv = dev_get_drvdata(dev);
         if (!priv)
                 return -ENODEV;
         p_env = priv->p_env;
@@ -3125,7 +3125,7 @@ claw_adname_show(struct device *dev, struct device_attribute *attr, char *buf)
         struct claw_privbk *priv;
         struct claw_env *  p_env;
 
-        priv = dev->driver_data;
+        priv = dev_get_drvdata(dev);
         if (!priv)
                 return -ENODEV;
         p_env = priv->p_env;
@@ -3139,7 +3139,7 @@ claw_adname_write(struct device *dev, struct device_attribute *attr,
         struct claw_privbk *priv;
         struct claw_env *  p_env;
 
-        priv = dev->driver_data;
+        priv = dev_get_drvdata(dev);
         if (!priv)
                 return -ENODEV;
         p_env = priv->p_env;
@@ -3163,7 +3163,7 @@ claw_apname_show(struct device *dev, struct device_attribute *attr, char *buf)
         struct claw_privbk *priv;
         struct claw_env *  p_env;
 
-        priv = dev->driver_data;
+        priv = dev_get_drvdata(dev);
         if (!priv)
                 return -ENODEV;
         p_env = priv->p_env;
@@ -3178,7 +3178,7 @@ claw_apname_write(struct device *dev, struct device_attribute *attr,
         struct claw_privbk *priv;
         struct claw_env *  p_env;
 
-        priv = dev->driver_data;
+        priv = dev_get_drvdata(dev);
         if (!priv)
                 return -ENODEV;
         p_env = priv->p_env;
@@ -3212,7 +3212,7 @@ claw_wbuff_show(struct device *dev, struct device_attribute *attr, char *buf)
         struct claw_privbk *priv;
         struct claw_env * p_env;
 
-        priv = dev->driver_data;
+        priv = dev_get_drvdata(dev);
         if (!priv)
                 return -ENODEV;
         p_env = priv->p_env;
@@ -3227,7 +3227,7 @@ claw_wbuff_write(struct device *dev, struct device_attribute *attr,
         struct claw_env *  p_env;
         int nnn,max;
 
-        priv = dev->driver_data;
+        priv = dev_get_drvdata(dev);
         if (!priv)
                 return -ENODEV;
         p_env = priv->p_env;
@@ -3254,7 +3254,7 @@ claw_rbuff_show(struct device *dev, struct device_attribute *attr, char *buf)
         struct claw_privbk *priv;
         struct claw_env *  p_env;
 
-        priv = dev->driver_data;
+        priv = dev_get_drvdata(dev);
         if (!priv)
                 return -ENODEV;
         p_env = priv->p_env;
@@ -3269,7 +3269,7 @@ claw_rbuff_write(struct device *dev, struct device_attribute *attr,
         struct claw_env *p_env;
         int nnn,max;
 
-        priv = dev->driver_data;
+        priv = dev_get_drvdata(dev);
         if (!priv)
                 return -ENODEV;
         p_env = priv->p_env;
diff --git a/drivers/s390/net/lcs.c b/drivers/s390/net/lcs.c
index 07a25c3f94b6..8c675905448b 100644
--- a/drivers/s390/net/lcs.c
+++ b/drivers/s390/net/lcs.c
@@ -1936,7 +1936,7 @@ lcs_portno_show (struct device *dev, struct device_attribute *attr, char *buf)
 {
         struct lcs_card *card;
 
-        card = (struct lcs_card *)dev->driver_data;
+        card = dev_get_drvdata(dev);
 
         if (!card)
                 return 0;
@@ -1953,7 +1953,7 @@ lcs_portno_store (struct device *dev, struct device_attribute *attr, const char
         struct lcs_card *card;
         int value;
 
-        card = (struct lcs_card *)dev->driver_data;
+        card = dev_get_drvdata(dev);
 
         if (!card)
                 return 0;
@@ -1987,7 +1987,7 @@ lcs_timeout_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
         struct lcs_card *card;
 
-        card = (struct lcs_card *)dev->driver_data;
+        card = dev_get_drvdata(dev);
 
         return card ? sprintf(buf, "%u\n", card->lancmd_timeout) : 0;
 }
@@ -1998,7 +1998,7 @@ lcs_timeout_store (struct device *dev, struct device_attribute *attr, const char
         struct lcs_card *card;
         int value;
 
-        card = (struct lcs_card *)dev->driver_data;
+        card = dev_get_drvdata(dev);
 
         if (!card)
                 return 0;
@@ -2017,7 +2017,7 @@ static ssize_t
 lcs_dev_recover_store(struct device *dev, struct device_attribute *attr,
                       const char *buf, size_t count)
 {
-        struct lcs_card *card = dev->driver_data;
+        struct lcs_card *card = dev_get_drvdata(dev);
         char *tmp;
         int i;
 
@@ -2070,7 +2070,7 @@ lcs_probe_device(struct ccwgroup_device *ccwgdev)
                 put_device(&ccwgdev->dev);
                 return ret;
         }
-        ccwgdev->dev.driver_data = card;
+        dev_set_drvdata(&ccwgdev->dev, card);
         ccwgdev->cdev[0]->handler = lcs_irq;
         ccwgdev->cdev[1]->handler = lcs_irq;
         card->gdev = ccwgdev;
@@ -2087,7 +2087,7 @@ lcs_register_netdev(struct ccwgroup_device *ccwgdev)
         struct lcs_card *card;
 
         LCS_DBF_TEXT(2, setup, "regnetdv");
-        card = (struct lcs_card *)ccwgdev->dev.driver_data;
+        card = dev_get_drvdata(&ccwgdev->dev);
         if (card->dev->reg_state != NETREG_UNINITIALIZED)
                 return 0;
         SET_NETDEV_DEV(card->dev, &ccwgdev->dev);
@@ -2120,7 +2120,7 @@ lcs_new_device(struct ccwgroup_device *ccwgdev)
         enum lcs_dev_states recover_state;
         int rc;
 
-        card = (struct lcs_card *)ccwgdev->dev.driver_data;
+        card = dev_get_drvdata(&ccwgdev->dev);
         if (!card)
                 return -ENODEV;
 
@@ -2226,7 +2226,7 @@ __lcs_shutdown_device(struct ccwgroup_device *ccwgdev, int recovery_mode)
         int ret;
 
         LCS_DBF_TEXT(3, setup, "shtdndev");
-        card = (struct lcs_card *)ccwgdev->dev.driver_data;
+        card = dev_get_drvdata(&ccwgdev->dev);
         if (!card)
                 return -ENODEV;
         if (recovery_mode == 0) {
@@ -2293,7 +2293,7 @@ lcs_remove_device(struct ccwgroup_device *ccwgdev)
 {
         struct lcs_card *card;
 
-        card = (struct lcs_card *)ccwgdev->dev.driver_data;
+        card = dev_get_drvdata(&ccwgdev->dev);
         if (!card)
                 return;
 
diff --git a/drivers/s390/net/lcs.h b/drivers/s390/net/lcs.h
index d58fea52557d..6d668642af27 100644
--- a/drivers/s390/net/lcs.h
+++ b/drivers/s390/net/lcs.h
@@ -34,8 +34,8 @@ static inline int lcs_dbf_passes(debug_info_t *dbf_grp, int level)
  *      sysfs related stuff
  */
 #define CARD_FROM_DEV(cdev) \
-        (struct lcs_card *) \
-        ((struct ccwgroup_device *)cdev->dev.driver_data)->dev.driver_data;
+        (struct lcs_card *) dev_get_drvdata( \
+                &((struct ccwgroup_device *)dev_get_drvdata(&cdev->dev))->dev);
 /**
  * CCW commands used in this driver
  */
diff --git a/drivers/s390/net/netiucv.c b/drivers/s390/net/netiucv.c
index fdb02d043d3e..52574ce797b2 100644
--- a/drivers/s390/net/netiucv.c
+++ b/drivers/s390/net/netiucv.c
@@ -1452,7 +1452,7 @@ static int netiucv_change_mtu(struct net_device * dev, int new_mtu)
 static ssize_t user_show(struct device *dev, struct device_attribute *attr,
                          char *buf)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%s\n", netiucv_printname(priv->conn->userid));
@@ -1461,7 +1461,7 @@ static ssize_t user_show(struct device *dev, struct device_attribute *attr,
 static ssize_t user_write(struct device *dev, struct device_attribute *attr,
                           const char *buf, size_t count)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
         struct net_device *ndev = priv->conn->netdev;
         char    *p;
         char    *tmp;
@@ -1518,7 +1518,8 @@ static DEVICE_ATTR(user, 0644, user_show, user_write);
 
 static ssize_t buffer_show (struct device *dev, struct device_attribute *attr,
                             char *buf)
-{       struct netiucv_priv *priv = dev->driver_data;
+{
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%d\n", priv->conn->max_buffsize);
@@ -1527,7 +1528,7 @@ static ssize_t buffer_show (struct device *dev, struct device_attribute *attr,
 static ssize_t buffer_write (struct device *dev, struct device_attribute *attr,
                              const char *buf, size_t count)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
         struct net_device *ndev = priv->conn->netdev;
         char         *e;
         int          bs1;
@@ -1575,7 +1576,7 @@ static DEVICE_ATTR(buffer, 0644, buffer_show, buffer_write);
 static ssize_t dev_fsm_show (struct device *dev, struct device_attribute *attr,
                              char *buf)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%s\n", fsm_getstate_str(priv->fsm));
@@ -1586,7 +1587,7 @@ static DEVICE_ATTR(device_fsm_state, 0444, dev_fsm_show, NULL);
 static ssize_t conn_fsm_show (struct device *dev,
                               struct device_attribute *attr, char *buf)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%s\n", fsm_getstate_str(priv->conn->fsm));
@@ -1597,7 +1598,7 @@ static DEVICE_ATTR(connection_fsm_state, 0444, conn_fsm_show, NULL);
 static ssize_t maxmulti_show (struct device *dev,
                               struct device_attribute *attr, char *buf)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%ld\n", priv->conn->prof.maxmulti);
@@ -1607,7 +1608,7 @@ static ssize_t maxmulti_write (struct device *dev,
                                struct device_attribute *attr,
                                const char *buf, size_t count)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 4, __func__);
         priv->conn->prof.maxmulti = 0;
@@ -1619,7 +1620,7 @@ static DEVICE_ATTR(max_tx_buffer_used, 0644, maxmulti_show, maxmulti_write);
 static ssize_t maxcq_show (struct device *dev, struct device_attribute *attr,
                            char *buf)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%ld\n", priv->conn->prof.maxcqueue);
@@ -1628,7 +1629,7 @@ static ssize_t maxcq_show (struct device *dev, struct device_attribute *attr,
 static ssize_t maxcq_write (struct device *dev, struct device_attribute *attr,
                             const char *buf, size_t count)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 4, __func__);
         priv->conn->prof.maxcqueue = 0;
@@ -1640,7 +1641,7 @@ static DEVICE_ATTR(max_chained_skbs, 0644, maxcq_show, maxcq_write);
 static ssize_t sdoio_show (struct device *dev, struct device_attribute *attr,
                            char *buf)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%ld\n", priv->conn->prof.doios_single);
@@ -1649,7 +1650,7 @@ static ssize_t sdoio_show (struct device *dev, struct device_attribute *attr,
 static ssize_t sdoio_write (struct device *dev, struct device_attribute *attr,
                             const char *buf, size_t count)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 4, __func__);
         priv->conn->prof.doios_single = 0;
@@ -1661,7 +1662,7 @@ static DEVICE_ATTR(tx_single_write_ops, 0644, sdoio_show, sdoio_write);
 static ssize_t mdoio_show (struct device *dev, struct device_attribute *attr,
                            char *buf)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%ld\n", priv->conn->prof.doios_multi);
@@ -1670,7 +1671,7 @@ static ssize_t mdoio_show (struct device *dev, struct device_attribute *attr,
 static ssize_t mdoio_write (struct device *dev, struct device_attribute *attr,
                             const char *buf, size_t count)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         priv->conn->prof.doios_multi = 0;
@@ -1682,7 +1683,7 @@ static DEVICE_ATTR(tx_multi_write_ops, 0644, mdoio_show, mdoio_write);
 static ssize_t txlen_show (struct device *dev, struct device_attribute *attr,
                            char *buf)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%ld\n", priv->conn->prof.txlen);
@@ -1691,7 +1692,7 @@ static ssize_t txlen_show (struct device *dev, struct device_attribute *attr,
 static ssize_t txlen_write (struct device *dev, struct device_attribute *attr,
                             const char *buf, size_t count)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 4, __func__);
         priv->conn->prof.txlen = 0;
@@ -1703,7 +1704,7 @@ static DEVICE_ATTR(netto_bytes, 0644, txlen_show, txlen_write);
 static ssize_t txtime_show (struct device *dev, struct device_attribute *attr,
                             char *buf)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%ld\n", priv->conn->prof.tx_time);
@@ -1712,7 +1713,7 @@ static ssize_t txtime_show (struct device *dev, struct device_attribute *attr,
 static ssize_t txtime_write (struct device *dev, struct device_attribute *attr,
                              const char *buf, size_t count)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 4, __func__);
         priv->conn->prof.tx_time = 0;
@@ -1724,7 +1725,7 @@ static DEVICE_ATTR(max_tx_io_time, 0644, txtime_show, txtime_write);
 static ssize_t txpend_show (struct device *dev, struct device_attribute *attr,
                             char *buf)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%ld\n", priv->conn->prof.tx_pending);
@@ -1733,7 +1734,7 @@ static ssize_t txpend_show (struct device *dev, struct device_attribute *attr,
 static ssize_t txpend_write (struct device *dev, struct device_attribute *attr,
                              const char *buf, size_t count)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 4, __func__);
         priv->conn->prof.tx_pending = 0;
@@ -1745,7 +1746,7 @@ static DEVICE_ATTR(tx_pending, 0644, txpend_show, txpend_write);
 static ssize_t txmpnd_show (struct device *dev, struct device_attribute *attr,
                             char *buf)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 5, __func__);
         return sprintf(buf, "%ld\n", priv->conn->prof.tx_max_pending);
@@ -1754,7 +1755,7 @@ static ssize_t txmpnd_show (struct device *dev, struct device_attribute *attr,
 static ssize_t txmpnd_write (struct device *dev, struct device_attribute *attr,
                              const char *buf, size_t count)
 {
-        struct netiucv_priv *priv = dev->driver_data;
+        struct netiucv_priv *priv = dev_get_drvdata(dev);
 
         IUCV_DBF_TEXT(trace, 4, __func__);
         priv->conn->prof.tx_max_pending = 0;
@@ -1845,7 +1846,7 @@ static int netiucv_register_device(struct net_device *ndev)
         if (ret)
                 goto out_unreg;
         priv->dev = dev;
-        dev->driver_data = priv;
+        dev_set_drvdata(dev, priv);
         return 0;
 
 out_unreg:
diff --git a/drivers/s390/scsi/zfcp_aux.c b/drivers/s390/scsi/zfcp_aux.c
index 3ac27ee47396..2ccbd185a5fb 100644
--- a/drivers/s390/scsi/zfcp_aux.c
+++ b/drivers/s390/scsi/zfcp_aux.c
@@ -470,6 +470,12 @@ int zfcp_adapter_enqueue(struct ccw_device *ccw_device)
         if (!adapter)
                 return -ENOMEM;
 
+        adapter->gs = kzalloc(sizeof(struct zfcp_wka_ports), GFP_KERNEL);
+        if (!adapter->gs) {
+                kfree(adapter);
+                return -ENOMEM;
+        }
+
         ccw_device->handler = NULL;
         adapter->ccw_device = ccw_device;
         atomic_set(&adapter->refcount, 0);
@@ -523,8 +529,7 @@ int zfcp_adapter_enqueue(struct ccw_device *ccw_device)
                 goto sysfs_failed;
 
         atomic_clear_mask(ZFCP_STATUS_COMMON_REMOVE, &adapter->status);
-
-        zfcp_fc_nameserver_init(adapter);
+        zfcp_fc_wka_ports_init(adapter);
 
         if (!zfcp_adapter_scsi_register(adapter))
                 return 0;
@@ -571,6 +576,7 @@ void zfcp_adapter_dequeue(struct zfcp_adapter *adapter)
         kfree(adapter->req_list);
         kfree(adapter->fc_stats);
         kfree(adapter->stats_reset_data);
+        kfree(adapter->gs);
         kfree(adapter);
 }
 
diff --git a/drivers/s390/scsi/zfcp_def.h b/drivers/s390/scsi/zfcp_def.h
index 2074d45dbf6c..49d0532bca1c 100644
--- a/drivers/s390/scsi/zfcp_def.h
+++ b/drivers/s390/scsi/zfcp_def.h
@@ -22,6 +22,8 @@
 #include <linux/syscalls.h>
 #include <linux/scatterlist.h>
 #include <linux/ioctl.h>
+#include <scsi/fc/fc_fs.h>
+#include <scsi/fc/fc_gs.h>
 #include <scsi/scsi.h>
 #include <scsi/scsi_tcq.h>
 #include <scsi/scsi_cmnd.h>
@@ -29,6 +31,7 @@
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_transport.h>
 #include <scsi/scsi_transport_fc.h>
+#include <scsi/scsi_bsg_fc.h>
 #include <asm/ccwdev.h>
 #include <asm/qdio.h>
 #include <asm/debug.h>
@@ -228,11 +231,6 @@ struct zfcp_ls_adisc {
 
 /* FC-PH/FC-GS well-known address identifiers for generic services */
 #define ZFCP_DID_WKA                            0xFFFFF0
-#define ZFCP_DID_MANAGEMENT_SERVICE             0xFFFFFA
-#define ZFCP_DID_TIME_SERVICE                   0xFFFFFB
-#define ZFCP_DID_DIRECTORY_SERVICE              0xFFFFFC
-#define ZFCP_DID_ALIAS_SERVICE                  0xFFFFF8
-#define ZFCP_DID_KEY_DISTRIBUTION_SERVICE       0xFFFFF7
 
 /* remote port status */
 #define ZFCP_STATUS_PORT_PHYS_OPEN              0x00000001
@@ -376,6 +374,14 @@ struct zfcp_wka_port {
         struct delayed_work     work;
 };
 
+struct zfcp_wka_ports {
+        struct zfcp_wka_port ms;        /* management service */
+        struct zfcp_wka_port ts;        /* time service */
+        struct zfcp_wka_port ds;        /* directory service */
+        struct zfcp_wka_port as;        /* alias service */
+        struct zfcp_wka_port ks;        /* key distribution service */
+};
+
 struct zfcp_qdio_queue {
         struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q];
         u8                 first;       /* index of next free bfr in queue */
@@ -461,7 +467,7 @@ struct zfcp_adapter {
                                                       actions */
         u32                     erp_low_mem_count; /* nr of erp actions waiting
                                                       for memory */
-        struct zfcp_wka_port    nsp;               /* adapter's nameserver */
+        struct zfcp_wka_ports   *gs;               /* generic services */
         debug_info_t            *rec_dbf;
         debug_info_t            *hba_dbf;
         debug_info_t            *san_dbf;          /* debug feature areas */
diff --git a/drivers/s390/scsi/zfcp_erp.c b/drivers/s390/scsi/zfcp_erp.c
index e50ea465bc2b..8030e25152fb 100644
--- a/drivers/s390/scsi/zfcp_erp.c
+++ b/drivers/s390/scsi/zfcp_erp.c
@@ -719,7 +719,7 @@ static void zfcp_erp_adapter_strategy_close(struct zfcp_erp_action *act)
         zfcp_qdio_close(adapter);
         zfcp_fsf_req_dismiss_all(adapter);
         adapter->fsf_req_seq_no = 0;
-        zfcp_fc_wka_port_force_offline(&adapter->nsp);
+        zfcp_fc_wka_port_force_offline(&adapter->gs->ds);
         /* all ports and units are closed */
         zfcp_erp_modify_adapter_status(adapter, "erascl1", NULL,
                                        ZFCP_STATUS_COMMON_OPEN, ZFCP_CLEAR);
diff --git a/drivers/s390/scsi/zfcp_ext.h b/drivers/s390/scsi/zfcp_ext.h
index 120a9a1c81f7..3044c6010306 100644
--- a/drivers/s390/scsi/zfcp_ext.h
+++ b/drivers/s390/scsi/zfcp_ext.h
@@ -106,8 +106,12 @@ extern int zfcp_fc_ns_gid_pn(struct zfcp_erp_action *);
 extern void zfcp_fc_plogi_evaluate(struct zfcp_port *, struct fsf_plogi *);
 extern void zfcp_test_link(struct zfcp_port *);
 extern void zfcp_fc_link_test_work(struct work_struct *);
-extern void zfcp_fc_nameserver_init(struct zfcp_adapter *);
 extern void zfcp_fc_wka_port_force_offline(struct zfcp_wka_port *);
+extern void zfcp_fc_wka_ports_init(struct zfcp_adapter *);
+extern int zfcp_fc_execute_els_fc_job(struct fc_bsg_job *);
+extern int zfcp_fc_execute_ct_fc_job(struct fc_bsg_job *);
+extern void zfcp_fc_wka_port_force_offline(struct zfcp_wka_port *);
+
 
 /* zfcp_fsf.c */
 extern int zfcp_fsf_open_port(struct zfcp_erp_action *);
diff --git a/drivers/s390/scsi/zfcp_fc.c b/drivers/s390/scsi/zfcp_fc.c
index 35493a82d2a8..2f0705d76b72 100644
--- a/drivers/s390/scsi/zfcp_fc.c
+++ b/drivers/s390/scsi/zfcp_fc.c
@@ -120,14 +120,13 @@ static void zfcp_wka_port_put(struct zfcp_wka_port *wka_port)
         schedule_delayed_work(&wka_port->work, HZ / 100);
 }
 
-void zfcp_fc_nameserver_init(struct zfcp_adapter *adapter)
+static void zfcp_fc_wka_port_init(struct zfcp_wka_port *wka_port, u32 d_id,
+                                  struct zfcp_adapter *adapter)
 {
-        struct zfcp_wka_port *wka_port = &adapter->nsp;
-
         init_waitqueue_head(&wka_port->completion_wq);
 
         wka_port->adapter = adapter;
-        wka_port->d_id = ZFCP_DID_DIRECTORY_SERVICE;
+        wka_port->d_id = d_id;
 
         wka_port->status = ZFCP_WKA_PORT_OFFLINE;
         atomic_set(&wka_port->refcount, 0);
@@ -143,6 +142,17 @@ void zfcp_fc_wka_port_force_offline(struct zfcp_wka_port *wka)
         mutex_unlock(&wka->mutex);
 }
 
+void zfcp_fc_wka_ports_init(struct zfcp_adapter *adapter)
+{
+        struct zfcp_wka_ports *gs = adapter->gs;
+
+        zfcp_fc_wka_port_init(&gs->ms, FC_FID_MGMT_SERV, adapter);
+        zfcp_fc_wka_port_init(&gs->ts, FC_FID_TIME_SERV, adapter);
+        zfcp_fc_wka_port_init(&gs->ds, FC_FID_DIR_SERV, adapter);
+        zfcp_fc_wka_port_init(&gs->as, FC_FID_ALIASES, adapter);
+        zfcp_fc_wka_port_init(&gs->ks, FC_FID_SEC_KEY, adapter);
+}
+
 static void _zfcp_fc_incoming_rscn(struct zfcp_fsf_req *fsf_req, u32 range,
                                    struct fcp_rscn_element *elem)
 {
@@ -282,7 +292,7 @@ int static zfcp_fc_ns_gid_pn_request(struct zfcp_erp_action *erp_action,
 
         /* setup parameters for send generic command */
         gid_pn->port = erp_action->port;
-        gid_pn->ct.wka_port = &adapter->nsp;
+        gid_pn->ct.wka_port = &adapter->gs->ds;
         gid_pn->ct.handler = zfcp_fc_ns_handler;
         gid_pn->ct.handler_data = (unsigned long) &compl_rec;
         gid_pn->ct.timeout = ZFCP_NS_GID_PN_TIMEOUT;
@@ -329,13 +339,13 @@ int zfcp_fc_ns_gid_pn(struct zfcp_erp_action *erp_action)
 
         memset(gid_pn, 0, sizeof(*gid_pn));
 
-        ret = zfcp_wka_port_get(&adapter->nsp);
+        ret = zfcp_wka_port_get(&adapter->gs->ds);
         if (ret)
                 goto out;
 
         ret = zfcp_fc_ns_gid_pn_request(erp_action, gid_pn);
 
-        zfcp_wka_port_put(&adapter->nsp);
+        zfcp_wka_port_put(&adapter->gs->ds);
 out:
         mempool_free(gid_pn, adapter->pool.data_gid_pn);
         return ret;
@@ -525,7 +535,7 @@ static int zfcp_scan_issue_gpn_ft(struct zfcp_gpn_ft *gpn_ft,
         req->fc4_type = ZFCP_CT_SCSI_FCP;
 
         /* prepare zfcp_send_ct */
-        ct->wka_port = &adapter->nsp;
+        ct->wka_port = &adapter->gs->ds;
         ct->handler = zfcp_fc_ns_handler;
         ct->handler_data = (unsigned long)&compl_rec;
         ct->timeout = 10;
@@ -644,7 +654,7 @@ int zfcp_scan_ports(struct zfcp_adapter *adapter)
             fc_host_port_type(adapter->scsi_host) != FC_PORTTYPE_NPIV)
                 return 0;
 
-        ret = zfcp_wka_port_get(&adapter->nsp);
+        ret = zfcp_wka_port_get(&adapter->gs->ds);
         if (ret)
                 return ret;
 
@@ -666,7 +676,7 @@ int zfcp_scan_ports(struct zfcp_adapter *adapter)
         }
         zfcp_free_sg_env(gpn_ft, buf_num);
 out:
-        zfcp_wka_port_put(&adapter->nsp);
+        zfcp_wka_port_put(&adapter->gs->ds);
         return ret;
 }
 
@@ -675,3 +685,158 @@ void _zfcp_scan_ports_later(struct work_struct *work)
 {
         zfcp_scan_ports(container_of(work, struct zfcp_adapter, scan_work));
 }
+
+struct zfcp_els_fc_job {
+        struct zfcp_send_els els;
+        struct fc_bsg_job *job;
+};
+
+static void zfcp_fc_generic_els_handler(unsigned long data)
+{
+        struct zfcp_els_fc_job *els_fc_job = (struct zfcp_els_fc_job *) data;
+        struct fc_bsg_job *job = els_fc_job->job;
+        struct fc_bsg_reply *reply = job->reply;
+
+        if (els_fc_job->els.status) {
+                /* request rejected or timed out */
+                reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_REJECT;
+                goto out;
+        }
+
+        reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
+        reply->reply_payload_rcv_len = job->reply_payload.payload_len;
+
+out:
+        job->state_flags = FC_RQST_STATE_DONE;
+        job->job_done(job);
+        kfree(els_fc_job);
+}
+
+int zfcp_fc_execute_els_fc_job(struct fc_bsg_job *job)
+{
+        struct zfcp_els_fc_job *els_fc_job;
+        struct fc_rport *rport = job->rport;
+        struct Scsi_Host *shost;
+        struct zfcp_adapter *adapter;
+        struct zfcp_port *port;
+        u8 *port_did;
+
+        shost = rport ? rport_to_shost(rport) : job->shost;
+        adapter = (struct zfcp_adapter *)shost->hostdata[0];
+
+        if (!(atomic_read(&adapter->status) & ZFCP_STATUS_COMMON_OPEN))
+                return -EINVAL;
+
+        els_fc_job = kzalloc(sizeof(struct zfcp_els_fc_job), GFP_KERNEL);
+        if (!els_fc_job)
+                return -ENOMEM;
+
+        els_fc_job->els.adapter = adapter;
+        if (rport) {
+                read_lock_irq(&zfcp_data.config_lock);
+                port = rport->dd_data;
+                if (port)
+                        els_fc_job->els.d_id = port->d_id;
+                read_unlock_irq(&zfcp_data.config_lock);
+                if (!port) {
+                        kfree(els_fc_job);
+                        return -EINVAL;
+                }
+        } else {
+                port_did = job->request->rqst_data.h_els.port_id;
+                els_fc_job->els.d_id = (port_did[0] << 16) +
+                                        (port_did[1] << 8) + port_did[2];
+        }
+
+        els_fc_job->els.req = job->request_payload.sg_list;
+        els_fc_job->els.resp = job->reply_payload.sg_list;
+        els_fc_job->els.handler = zfcp_fc_generic_els_handler;
+        els_fc_job->els.handler_data = (unsigned long) els_fc_job;
+        els_fc_job->job = job;
+
+        return zfcp_fsf_send_els(&els_fc_job->els);
+}
+
+struct zfcp_ct_fc_job {
+        struct zfcp_send_ct ct;
+        struct fc_bsg_job *job;
+};
+
+static void zfcp_fc_generic_ct_handler(unsigned long data)
+{
+        struct zfcp_ct_fc_job *ct_fc_job = (struct zfcp_ct_fc_job *) data;
+        struct fc_bsg_job *job = ct_fc_job->job;
+
+        job->reply->reply_data.ctels_reply.status = ct_fc_job->ct.status ?
+                                FC_CTELS_STATUS_REJECT : FC_CTELS_STATUS_OK;
+        job->reply->reply_payload_rcv_len = job->reply_payload.payload_len;
+        job->state_flags = FC_RQST_STATE_DONE;
+        job->job_done(job);
+
+        zfcp_wka_port_put(ct_fc_job->ct.wka_port);
+
+        kfree(ct_fc_job);
+}
+
+int zfcp_fc_execute_ct_fc_job(struct fc_bsg_job *job)
+{
+        int ret;
+        u8 gs_type;
+        struct fc_rport *rport = job->rport;
+        struct Scsi_Host *shost;
+        struct zfcp_adapter *adapter;
+        struct zfcp_ct_fc_job *ct_fc_job;
+        u32 preamble_word1;
+
+        shost = rport ? rport_to_shost(rport) : job->shost;
+
+        adapter = (struct zfcp_adapter *)shost->hostdata[0];
+        if (!(atomic_read(&adapter->status) & ZFCP_STATUS_COMMON_OPEN))
+                return -EINVAL;
+
+        ct_fc_job = kzalloc(sizeof(struct zfcp_ct_fc_job), GFP_KERNEL);
+        if (!ct_fc_job)
+                return -ENOMEM;
+
+        preamble_word1 = job->request->rqst_data.r_ct.preamble_word1;
+        gs_type = (preamble_word1 & 0xff000000) >> 24;
+
+        switch (gs_type) {
+        case FC_FST_ALIAS:
+                ct_fc_job->ct.wka_port = &adapter->gs->as;
+                break;
+        case FC_FST_MGMT:
+                ct_fc_job->ct.wka_port = &adapter->gs->ms;
+                break;
+        case FC_FST_TIME:
+                ct_fc_job->ct.wka_port = &adapter->gs->ts;
+                break;
+        case FC_FST_DIR:
+                ct_fc_job->ct.wka_port = &adapter->gs->ds;
+                break;
+        default:
+                kfree(ct_fc_job);
+                return -EINVAL; /* no such service */
+        }
+
+        ret = zfcp_wka_port_get(ct_fc_job->ct.wka_port);
+        if (ret) {
+                kfree(ct_fc_job);
+                return ret;
+        }
+
+        ct_fc_job->ct.req = job->request_payload.sg_list;
+        ct_fc_job->ct.resp = job->reply_payload.sg_list;
+        ct_fc_job->ct.timeout = ZFCP_FSF_REQUEST_TIMEOUT;
+        ct_fc_job->ct.handler = zfcp_fc_generic_ct_handler;
+        ct_fc_job->ct.handler_data = (unsigned long) ct_fc_job;
+        ct_fc_job->ct.completion = NULL;
+        ct_fc_job->job = job;
+
+        ret = zfcp_fsf_send_ct(&ct_fc_job->ct, NULL, NULL);
+        if (ret) {
+                kfree(ct_fc_job);
+                zfcp_wka_port_put(ct_fc_job->ct.wka_port);
+        }
+        return ret;
+}
diff --git a/drivers/s390/scsi/zfcp_fsf.c b/drivers/s390/scsi/zfcp_fsf.c
index e6dae3744e79..c57658f3d34f 100644
--- a/drivers/s390/scsi/zfcp_fsf.c
+++ b/drivers/s390/scsi/zfcp_fsf.c
@@ -1146,7 +1146,8 @@ static void zfcp_fsf_send_els_handler(struct zfcp_fsf_req *req)
         case FSF_RESPONSE_SIZE_TOO_LARGE:
                 break;
         case FSF_ACCESS_DENIED:
-                zfcp_fsf_access_denied_port(req, port);
+                if (port)
+                        zfcp_fsf_access_denied_port(req, port);
                 break;
         case FSF_SBAL_MISMATCH:
                 /* should never occure, avoided in zfcp_fsf_send_els */
diff --git a/drivers/s390/scsi/zfcp_scsi.c b/drivers/s390/scsi/zfcp_scsi.c
index 7d0da230eb63..967ede73f4c5 100644
--- a/drivers/s390/scsi/zfcp_scsi.c
+++ b/drivers/s390/scsi/zfcp_scsi.c
@@ -623,6 +623,20 @@ void zfcp_scsi_scan(struct work_struct *work)
         zfcp_unit_put(unit);
 }
 
+static int zfcp_execute_fc_job(struct fc_bsg_job *job)
+{
+        switch (job->request->msgcode) {
+        case FC_BSG_RPT_ELS:
+        case FC_BSG_HST_ELS_NOLOGIN:
+                return zfcp_fc_execute_els_fc_job(job);
+        case FC_BSG_RPT_CT:
+        case FC_BSG_HST_CT:
+                return zfcp_fc_execute_ct_fc_job(job);
+        default:
+                return -EINVAL;
+        }
+}
+
 struct fc_function_template zfcp_transport_functions = {
         .show_starget_port_id = 1,
         .show_starget_port_name = 1,
@@ -644,6 +658,7 @@ struct fc_function_template zfcp_transport_functions = {
         .dev_loss_tmo_callbk = zfcp_scsi_dev_loss_tmo_callbk,
         .terminate_rport_io = zfcp_scsi_terminate_rport_io,
         .show_host_port_state = 1,
+        .bsg_request = zfcp_execute_fc_job,
         /* no functions registered for following dynamic attributes but
            directly set by LLDD */
         .show_host_port_type = 1,
diff --git a/drivers/scsi/aha1740.c b/drivers/scsi/aha1740.c
index ed0e3e55652a..538135783aab 100644
--- a/drivers/scsi/aha1740.c
+++ b/drivers/scsi/aha1740.c
@@ -646,7 +646,7 @@ static int aha1740_probe (struct device *dev)
 
 static __devexit int aha1740_remove (struct device *dev)
 {
-        struct Scsi_Host *shpnt = dev->driver_data;
+        struct Scsi_Host *shpnt = dev_get_drvdata(dev);
         struct aha1740_hostdata *host = HOSTDATA (shpnt);
 
         scsi_remove_host(shpnt);
diff --git a/drivers/scsi/aic7xxx/aic79xx_osm.c b/drivers/scsi/aic7xxx/aic79xx_osm.c
index 0f829b3b8ab7..75b23317bd26 100644
--- a/drivers/scsi/aic7xxx/aic79xx_osm.c
+++ b/drivers/scsi/aic7xxx/aic79xx_osm.c
@@ -627,19 +627,15 @@ ahd_linux_target_alloc(struct scsi_target *starget)
                                             starget->id, &tstate);
 
                 if ((flags  & CFPACKETIZED) == 0) {
-                        /* Do not negotiate packetized transfers */
-                        spi_rd_strm(starget) = 0;
-                        spi_pcomp_en(starget) = 0;
-                        spi_rti(starget) = 0;
-                        spi_wr_flow(starget) = 0;
-                        spi_hold_mcs(starget) = 0;
+                        /* don't negotiate packetized (IU) transfers */
+                        spi_max_iu(starget) = 0;
                 } else {
                         if ((ahd->features & AHD_RTI) == 0)
                                 spi_rti(starget) = 0;
                 }
 
                 if ((flags & CFQAS) == 0)
-                        spi_qas(starget) = 0;
+                        spi_max_qas(starget) = 0;
 
                 /* Transinfo values have been set to BIOS settings */
                 spi_max_width(starget) = (flags & CFWIDEB) ? 1 : 0;
diff --git a/drivers/scsi/bnx2i/Kconfig b/drivers/scsi/bnx2i/Kconfig
index 820d428ae839..b62b482e55e7 100644
--- a/drivers/scsi/bnx2i/Kconfig
+++ b/drivers/scsi/bnx2i/Kconfig
@@ -2,6 +2,7 @@ config SCSI_BNX2_ISCSI
         tristate "Broadcom NetXtreme II iSCSI support"
         select SCSI_ISCSI_ATTRS
         select CNIC
+        depends on PCI
         ---help---
         This driver supports iSCSI offload for the Broadcom NetXtreme II
         devices.
diff --git a/drivers/scsi/ibmvscsi/ibmvscsi.c b/drivers/scsi/ibmvscsi/ibmvscsi.c
index 11d2602ae88e..869a11bdccbd 100644
--- a/drivers/scsi/ibmvscsi/ibmvscsi.c
+++ b/drivers/scsi/ibmvscsi/ibmvscsi.c
@@ -1877,7 +1877,7 @@ static int ibmvscsi_probe(struct vio_dev *vdev, const struct vio_device_id *id)
         unsigned long wait_switch = 0;
         int rc;
 
-        vdev->dev.driver_data = NULL;
+        dev_set_drvdata(&vdev->dev, NULL);
 
         host = scsi_host_alloc(&driver_template, sizeof(*hostdata));
         if (!host) {
@@ -1949,7 +1949,7 @@ static int ibmvscsi_probe(struct vio_dev *vdev, const struct vio_device_id *id)
                         scsi_scan_host(host);
         }
 
-        vdev->dev.driver_data = hostdata;
+        dev_set_drvdata(&vdev->dev, hostdata);
         return 0;
 
       add_srp_port_failed:
@@ -1968,7 +1968,7 @@ static int ibmvscsi_probe(struct vio_dev *vdev, const struct vio_device_id *id)
 
 static int ibmvscsi_remove(struct vio_dev *vdev)
 {
-        struct ibmvscsi_host_data *hostdata = vdev->dev.driver_data;
+        struct ibmvscsi_host_data *hostdata = dev_get_drvdata(&vdev->dev);
         unmap_persist_bufs(hostdata);
         release_event_pool(&hostdata->pool, hostdata);
         ibmvscsi_ops->release_crq_queue(&hostdata->queue, hostdata,
diff --git a/drivers/scsi/ibmvscsi/ibmvstgt.c b/drivers/scsi/ibmvscsi/ibmvstgt.c
index e2dd6a45924a..d5eaf9727109 100644
--- a/drivers/scsi/ibmvscsi/ibmvstgt.c
+++ b/drivers/scsi/ibmvscsi/ibmvstgt.c
@@ -892,7 +892,7 @@ free_vport:
 
 static int ibmvstgt_remove(struct vio_dev *dev)
 {
-        struct srp_target *target = (struct srp_target *) dev->dev.driver_data;
+        struct srp_target *target = dev_get_drvdata(&dev->dev);
         struct Scsi_Host *shost = target->shost;
         struct vio_port *vport = target->ldata;
 
diff --git a/drivers/scsi/libsrp.c b/drivers/scsi/libsrp.c
index 15e2d132e8b9..2742ae8a3d09 100644
--- a/drivers/scsi/libsrp.c
+++ b/drivers/scsi/libsrp.c
@@ -135,7 +135,7 @@ int srp_target_alloc(struct srp_target *target, struct device *dev,
         INIT_LIST_HEAD(&target->cmd_queue);
 
         target->dev = dev;
-        target->dev->driver_data = target;
+        dev_set_drvdata(target->dev, target);
 
         target->srp_iu_size = iu_size;
         target->rx_ring_size = nr;
diff --git a/drivers/scsi/lpfc/lpfc.h b/drivers/scsi/lpfc/lpfc.h
index 540569849099..1877d9811831 100644
--- a/drivers/scsi/lpfc/lpfc.h
+++ b/drivers/scsi/lpfc/lpfc.h
@@ -457,10 +457,6 @@ struct lpfc_hba {
         void (*lpfc_scsi_prep_cmnd)
                 (struct lpfc_vport *, struct lpfc_scsi_buf *,
                  struct lpfc_nodelist *);
-        int (*lpfc_scsi_prep_task_mgmt_cmd)
-                (struct lpfc_vport *, struct lpfc_scsi_buf *,
-                 unsigned int, uint8_t);
-
         /* IOCB interface function jump table entries */
         int (*__lpfc_sli_issue_iocb)
                 (struct lpfc_hba *, uint32_t,
diff --git a/drivers/scsi/lpfc/lpfc_attr.c b/drivers/scsi/lpfc/lpfc_attr.c
index d73e677201f8..fc07be5fbce9 100644
--- a/drivers/scsi/lpfc/lpfc_attr.c
+++ b/drivers/scsi/lpfc/lpfc_attr.c
@@ -3113,6 +3113,9 @@ sysfs_ctlreg_write(struct kobject *kobj, struct bin_attribute *bin_attr,
         struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
         struct lpfc_hba   *phba = vport->phba;
 
+        if (phba->sli_rev >= LPFC_SLI_REV4)
+                return -EPERM;
+
         if ((off + count) > FF_REG_AREA_SIZE)
                 return -ERANGE;
 
@@ -3163,6 +3166,9 @@ sysfs_ctlreg_read(struct kobject *kobj, struct bin_attribute *bin_attr,
         struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
         struct lpfc_hba   *phba = vport->phba;
 
+        if (phba->sli_rev >= LPFC_SLI_REV4)
+                return -EPERM;
+
         if (off > FF_REG_AREA_SIZE)
                 return -ERANGE;
 
diff --git a/drivers/scsi/lpfc/lpfc_ct.c b/drivers/scsi/lpfc/lpfc_ct.c
index 1dbccfd3d022..0e532f072eb3 100644
--- a/drivers/scsi/lpfc/lpfc_ct.c
+++ b/drivers/scsi/lpfc/lpfc_ct.c
@@ -1732,7 +1732,9 @@ lpfc_decode_firmware_rev(struct lpfc_hba *phba, char *fwrevision, int flag)
         uint32_t *ptr, str[4];
         uint8_t *fwname;
 
-        if (vp->rev.rBit) {
+        if (phba->sli_rev == LPFC_SLI_REV4)
+                sprintf(fwrevision, "%s", vp->rev.opFwName);
+        else if (vp->rev.rBit) {
                 if (psli->sli_flag & LPFC_SLI_ACTIVE)
                         rev = vp->rev.sli2FwRev;
                 else
diff --git a/drivers/scsi/lpfc/lpfc_debugfs.c b/drivers/scsi/lpfc/lpfc_debugfs.c
index 2b02b1fb39a0..8d0f0de76b63 100644
--- a/drivers/scsi/lpfc/lpfc_debugfs.c
+++ b/drivers/scsi/lpfc/lpfc_debugfs.c
@@ -53,8 +53,7 @@
  * debugfs interface
  *
  * To access this interface the user should:
- * # mkdir /debug
- * # mount -t debugfs none /debug
+ * # mount -t debugfs none /sys/kernel/debug
  *
  * The lpfc debugfs directory hierarchy is:
  * lpfc/lpfcX/vportY
diff --git a/drivers/scsi/lpfc/lpfc_els.c b/drivers/scsi/lpfc/lpfc_els.c
index 6bdeb14878a2..f72fdf23bf1b 100644
--- a/drivers/scsi/lpfc/lpfc_els.c
+++ b/drivers/scsi/lpfc/lpfc_els.c
@@ -168,6 +168,19 @@ lpfc_prep_els_iocb(struct lpfc_vport *vport, uint8_t expectRsp,
         if (elsiocb == NULL)
                 return NULL;
 
+        /*
+         * If this command is for fabric controller and HBA running
+         * in FIP mode send FLOGI, FDISC and LOGO as FIP frames.
+         */
+        if ((did == Fabric_DID) &&
+                bf_get(lpfc_fip_flag, &phba->sli4_hba.sli4_flags) &&
+                ((elscmd == ELS_CMD_FLOGI) ||
+                 (elscmd == ELS_CMD_FDISC) ||
+                 (elscmd == ELS_CMD_LOGO)))
+                elsiocb->iocb_flag |= LPFC_FIP_ELS;
+        else
+                elsiocb->iocb_flag &= ~LPFC_FIP_ELS;
+
         icmd = &elsiocb->iocb;
 
         /* fill in BDEs for command */
@@ -6108,9 +6121,17 @@ lpfc_issue_els_fdisc(struct lpfc_vport *vport, struct lpfc_nodelist *ndlp,
         icmd->un.elsreq64.myID = 0;
         icmd->un.elsreq64.fl = 1;
 
-        /* For FDISC, Let FDISC rsp set the NPortID for this VPI */
-        icmd->ulpCt_h = 1;
-        icmd->ulpCt_l = 0;
+        if  (phba->sli_rev == LPFC_SLI_REV4) {
+                /* FDISC needs to be 1 for WQE VPI */
+                elsiocb->iocb.ulpCt_h = (SLI4_CT_VPI >> 1) & 1;
+                elsiocb->iocb.ulpCt_l = SLI4_CT_VPI & 1 ;
+                /* Set the ulpContext to the vpi */
+                elsiocb->iocb.ulpContext = vport->vpi + phba->vpi_base;
+        } else {
+                /* For FDISC, Let FDISC rsp set the NPortID for this VPI */
+                icmd->ulpCt_h = 1;
+                icmd->ulpCt_l = 0;
+        }
 
         pcmd = (uint8_t *) (((struct lpfc_dmabuf *) elsiocb->context2)->virt);
         *((uint32_t *) (pcmd)) = ELS_CMD_FDISC;
diff --git a/drivers/scsi/lpfc/lpfc_hbadisc.c b/drivers/scsi/lpfc/lpfc_hbadisc.c
index 35c41ae75be2..ed46b24a3380 100644
--- a/drivers/scsi/lpfc/lpfc_hbadisc.c
+++ b/drivers/scsi/lpfc/lpfc_hbadisc.c
@@ -1197,6 +1197,11 @@ lpfc_match_fcf_conn_list(struct lpfc_hba *phba,
 {
         struct lpfc_fcf_conn_entry *conn_entry;
 
+        /* If FCF not available return 0 */
+        if (!bf_get(lpfc_fcf_record_fcf_avail, new_fcf_record) ||
+                !bf_get(lpfc_fcf_record_fcf_valid, new_fcf_record))
+                return 0;
+
         if (!phba->cfg_enable_fip) {
                 *boot_flag = 0;
                 *addr_mode = bf_get(lpfc_fcf_record_mac_addr_prov,
@@ -1216,6 +1221,14 @@ lpfc_match_fcf_conn_list(struct lpfc_hba *phba,
                 *boot_flag = 0;
                 *addr_mode = bf_get(lpfc_fcf_record_mac_addr_prov,
                         new_fcf_record);
+
+                /*
+                 * When there are no FCF connect entries, use driver's default
+                 * addressing mode - FPMA.
+                 */
+                if (*addr_mode & LPFC_FCF_FPMA)
+                        *addr_mode = LPFC_FCF_FPMA;
+
                 *vlan_id = 0xFFFF;
                 return 1;
         }
@@ -1241,6 +1254,14 @@ lpfc_match_fcf_conn_list(struct lpfc_hba *phba,
                 }
 
                 /*
+                 * If connection record does not support any addressing mode,
+                 * skip the FCF record.
+                 */
+                if (!(bf_get(lpfc_fcf_record_mac_addr_prov, new_fcf_record)
+                        & (LPFC_FCF_FPMA | LPFC_FCF_SPMA)))
+                        continue;
+
+                /*
                  * Check if the connection record specifies a required
                  * addressing mode.
                  */
@@ -1272,6 +1293,11 @@ lpfc_match_fcf_conn_list(struct lpfc_hba *phba,
                 else
                         *boot_flag = 0;
 
+                /*
+                 * If user did not specify any addressing mode, or if the
+                 * prefered addressing mode specified by user is not supported
+                 * by FCF, allow fabric to pick the addressing mode.
+                 */
                 *addr_mode = bf_get(lpfc_fcf_record_mac_addr_prov,
                                 new_fcf_record);
                 /*
@@ -1297,12 +1323,6 @@ lpfc_match_fcf_conn_list(struct lpfc_hba *phba,
                         !(conn_entry->conn_rec.flags & FCFCNCT_AM_SPMA) &&
                         (*addr_mode & LPFC_FCF_FPMA))
                                 *addr_mode = LPFC_FCF_FPMA;
-                /*
-                 * If user did not specify any addressing mode, use FPMA if
-                 * possible else use SPMA.
-                 */
-                else if (*addr_mode & LPFC_FCF_FPMA)
-                        *addr_mode = LPFC_FCF_FPMA;
 
                 if (conn_entry->conn_rec.flags & FCFCNCT_VLAN_VALID)
                         *vlan_id = conn_entry->conn_rec.vlan_tag;
@@ -1864,7 +1884,7 @@ lpfc_mbx_cmpl_read_la(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmb)
                 vport->fc_flag &= ~FC_BYPASSED_MODE;
         spin_unlock_irq(shost->host_lock);
 
-        if (((phba->fc_eventTag + 1) < la->eventTag) ||
+        if ((phba->fc_eventTag  < la->eventTag) ||
             (phba->fc_eventTag == la->eventTag)) {
                 phba->fc_stat.LinkMultiEvent++;
                 if (la->attType == AT_LINK_UP)
@@ -2925,6 +2945,7 @@ lpfc_unreg_rpi(struct lpfc_vport *vport, struct lpfc_nodelist *ndlp)
                 lpfc_no_rpi(phba, ndlp);
                 ndlp->nlp_rpi = 0;
                 ndlp->nlp_flag &= ~NLP_RPI_VALID;
+                ndlp->nlp_flag &= ~NLP_NPR_ADISC;
                 return 1;
         }
         return 0;
diff --git a/drivers/scsi/lpfc/lpfc_hw.h b/drivers/scsi/lpfc/lpfc_hw.h
index 02aa016b93e9..8a3a026667e4 100644
--- a/drivers/scsi/lpfc/lpfc_hw.h
+++ b/drivers/scsi/lpfc/lpfc_hw.h
@@ -1183,7 +1183,6 @@ typedef struct {
 #define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
 #define PCI_VENDOR_ID_SERVERENGINE  0x19a2
 #define PCI_DEVICE_ID_TIGERSHARK    0x0704
-#define PCI_DEVICE_ID_TIGERSHARK_S  0x0705
 
 #define JEDEC_ID_ADDRESS            0x0080001c
 #define FIREFLY_JEDEC_ID            0x1ACC
diff --git a/drivers/scsi/lpfc/lpfc_hw4.h b/drivers/scsi/lpfc/lpfc_hw4.h
index 39c34b3ad29d..2995d128f07f 100644
--- a/drivers/scsi/lpfc/lpfc_hw4.h
+++ b/drivers/scsi/lpfc/lpfc_hw4.h
@@ -422,9 +422,9 @@ struct lpfc_wqe_generic{
 #define lpfc_wqe_gen_pri_WORD           word10
         uint32_t word11;
 #define lpfc_wqe_gen_cq_id_SHIFT        16
-#define lpfc_wqe_gen_cq_id_MASK         0x000003FF
+#define lpfc_wqe_gen_cq_id_MASK         0x0000FFFF
 #define lpfc_wqe_gen_cq_id_WORD         word11
-#define LPFC_WQE_CQ_ID_DEFAULT  0x3ff
+#define LPFC_WQE_CQ_ID_DEFAULT  0xffff
 #define lpfc_wqe_gen_wqec_SHIFT         7
 #define lpfc_wqe_gen_wqec_MASK          0x00000001
 #define lpfc_wqe_gen_wqec_WORD          word11
@@ -1128,7 +1128,7 @@ struct fcf_record {
 #define lpfc_fcf_record_mac_5_WORD              word4
 #define lpfc_fcf_record_fcf_avail_SHIFT         16
 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
-#define lpfc_fcf_record_fc_avail_WORD           word4
+#define lpfc_fcf_record_fcf_avail_WORD          word4
 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
diff --git a/drivers/scsi/lpfc/lpfc_init.c b/drivers/scsi/lpfc/lpfc_init.c
index 2f5907f92eea..fc67cc65c63b 100644
--- a/drivers/scsi/lpfc/lpfc_init.c
+++ b/drivers/scsi/lpfc/lpfc_init.c
@@ -428,7 +428,8 @@ lpfc_config_port_post(struct lpfc_hba *phba)
         /* Reset the DFT_HBA_Q_DEPTH to the max xri  */
         if (phba->cfg_hba_queue_depth > (mb->un.varRdConfig.max_xri+1))
                 phba->cfg_hba_queue_depth =
-                        mb->un.varRdConfig.max_xri + 1;
+                        (mb->un.varRdConfig.max_xri + 1) -
+                                        lpfc_sli4_get_els_iocb_cnt(phba);
 
         phba->lmt = mb->un.varRdConfig.lmt;
 
@@ -1646,10 +1647,6 @@ lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
                 oneConnect = 1;
                 m = (typeof(m)) {"OCe10100-F", max_speed, "PCIe"};
                 break;
-        case PCI_DEVICE_ID_TIGERSHARK_S:
-                oneConnect = 1;
-                m = (typeof(m)) {"OCe10100-F-S", max_speed, "PCIe"};
-                break;
         default:
                 m = (typeof(m)){ NULL };
                 break;
@@ -3543,6 +3540,7 @@ lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
 
         /* Free the allocated rpi headers. */
         lpfc_sli4_remove_rpi_hdrs(phba);
+        lpfc_sli4_remove_rpis(phba);
 
         /* Free the ELS sgl list */
         lpfc_free_active_sgl(phba);
@@ -7184,16 +7182,19 @@ lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
 {
         int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
 
-        if (max_xri <= 100)
-                return 4;
-        else if (max_xri <= 256)
-                return 8;
-        else if (max_xri <= 512)
-                return 16;
-        else if (max_xri <= 1024)
-                return 32;
-        else
-                return 48;
+        if (phba->sli_rev == LPFC_SLI_REV4) {
+                if (max_xri <= 100)
+                        return 4;
+                else if (max_xri <= 256)
+                        return 8;
+                else if (max_xri <= 512)
+                        return 16;
+                else if (max_xri <= 1024)
+                        return 32;
+                else
+                        return 48;
+        } else
+                return 0;
 }
 
 /**
@@ -7642,7 +7643,6 @@ lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
 
         switch (dev_id) {
         case PCI_DEVICE_ID_TIGERSHARK:
-        case PCI_DEVICE_ID_TIGERSHARK_S:
                 rc = lpfc_pci_probe_one_s4(pdev, pid);
                 break;
         default:
@@ -7941,8 +7941,6 @@ static struct pci_device_id lpfc_id_table[] = {
                 PCI_ANY_ID, PCI_ANY_ID, },
         {PCI_VENDOR_ID_SERVERENGINE, PCI_DEVICE_ID_TIGERSHARK,
                 PCI_ANY_ID, PCI_ANY_ID, },
-        {PCI_VENDOR_ID_SERVERENGINE, PCI_DEVICE_ID_TIGERSHARK_S,
-                PCI_ANY_ID, PCI_ANY_ID, },
         { 0 }
 };
 
diff --git a/drivers/scsi/lpfc/lpfc_mbox.c b/drivers/scsi/lpfc/lpfc_mbox.c
index b9b451c09010..3423571dd1b3 100644
--- a/drivers/scsi/lpfc/lpfc_mbox.c
+++ b/drivers/scsi/lpfc/lpfc_mbox.c
@@ -1631,6 +1631,7 @@ lpfc_sli4_config(struct lpfc_hba *phba, struct lpfcMboxq *mbox,
                 /* In case of malloc fails, proceed with whatever we have */
                 if (!viraddr)
                         break;
+                memset(viraddr, 0, PAGE_SIZE);
                 mbox->sge_array->addr[pagen] = viraddr;
                 /* Keep the first page for later sub-header construction */
                 if (pagen == 0)
@@ -1715,8 +1716,10 @@ lpfc_request_features(struct lpfc_hba *phba, struct lpfcMboxq *mboxq)
         /* Set up host requested features. */
         bf_set(lpfc_mbx_rq_ftr_rq_fcpi, &mboxq->u.mqe.un.req_ftrs, 1);
 
-        /* Virtual fabrics and FIPs are not supported yet. */
-        bf_set(lpfc_mbx_rq_ftr_rq_ifip, &mboxq->u.mqe.un.req_ftrs, 0);
+        if (phba->cfg_enable_fip)
+                bf_set(lpfc_mbx_rq_ftr_rq_ifip, &mboxq->u.mqe.un.req_ftrs, 0);
+        else
+                bf_set(lpfc_mbx_rq_ftr_rq_ifip, &mboxq->u.mqe.un.req_ftrs, 1);
 
         /* Enable DIF (block guard) only if configured to do so. */
         if (phba->cfg_enable_bg)
diff --git a/drivers/scsi/lpfc/lpfc_nportdisc.c b/drivers/scsi/lpfc/lpfc_nportdisc.c
index 09f659f77bb3..3e74136f1ede 100644
--- a/drivers/scsi/lpfc/lpfc_nportdisc.c
+++ b/drivers/scsi/lpfc/lpfc_nportdisc.c
@@ -497,7 +497,7 @@ lpfc_rcv_logo(struct lpfc_vport *vport, struct lpfc_nodelist *ndlp,
                 lpfc_els_rsp_acc(vport, ELS_CMD_PRLO, cmdiocb, ndlp, NULL);
         else
                 lpfc_els_rsp_acc(vport, ELS_CMD_ACC, cmdiocb, ndlp, NULL);
-        if ((ndlp->nlp_type & NLP_FABRIC) &&
+        if ((ndlp->nlp_DID == Fabric_DID) &&
                 vport->port_type == LPFC_NPIV_PORT) {
                 lpfc_linkdown_port(vport);
                 mod_timer(&ndlp->nlp_delayfunc, jiffies + HZ * 1);
diff --git a/drivers/scsi/lpfc/lpfc_scsi.c b/drivers/scsi/lpfc/lpfc_scsi.c
index 7991ba1980ae..da59c4f0168f 100644
--- a/drivers/scsi/lpfc/lpfc_scsi.c
+++ b/drivers/scsi/lpfc/lpfc_scsi.c
@@ -116,6 +116,27 @@ lpfc_debug_save_dif(struct scsi_cmnd *cmnd)
 }
 
 /**
+ * lpfc_sli4_set_rsp_sgl_last - Set the last bit in the response sge.
+ * @phba: Pointer to HBA object.
+ * @lpfc_cmd: lpfc scsi command object pointer.
+ *
+ * This function is called from the lpfc_prep_task_mgmt_cmd function to
+ * set the last bit in the response sge entry.
+ **/
+static void
+lpfc_sli4_set_rsp_sgl_last(struct lpfc_hba *phba,
+                                struct lpfc_scsi_buf *lpfc_cmd)
+{
+        struct sli4_sge *sgl = (struct sli4_sge *)lpfc_cmd->fcp_bpl;
+        if (sgl) {
+                sgl += 1;
+                sgl->word2 = le32_to_cpu(sgl->word2);
+                bf_set(lpfc_sli4_sge_last, sgl, 1);
+                sgl->word2 = cpu_to_le32(sgl->word2);
+        }
+}
+
+/**
  * lpfc_update_stats - Update statistical data for the command completion
  * @phba: Pointer to HBA object.
  * @lpfc_cmd: lpfc scsi command object pointer.
@@ -1978,7 +1999,7 @@ lpfc_send_scsi_error_event(struct lpfc_hba *phba, struct lpfc_vport *vport,
 }
 
 /**
- * lpfc_scsi_unprep_dma_buf_s3 - Un-map DMA mapping of SG-list for SLI3 dev
+ * lpfc_scsi_unprep_dma_buf - Un-map DMA mapping of SG-list for dev
  * @phba: The HBA for which this call is being executed.
  * @psb: The scsi buffer which is going to be un-mapped.
  *
@@ -1986,7 +2007,7 @@ lpfc_send_scsi_error_event(struct lpfc_hba *phba, struct lpfc_vport *vport,
  * field of @lpfc_cmd for device with SLI-3 interface spec.
  **/
 static void
-lpfc_scsi_unprep_dma_buf_s3(struct lpfc_hba *phba, struct lpfc_scsi_buf *psb)
+lpfc_scsi_unprep_dma_buf(struct lpfc_hba *phba, struct lpfc_scsi_buf *psb)
 {
         /*
          * There are only two special cases to consider.  (1) the scsi command
@@ -2003,36 +2024,6 @@ lpfc_scsi_unprep_dma_buf_s3(struct lpfc_hba *phba, struct lpfc_scsi_buf *psb)
 }
 
 /**
- * lpfc_scsi_unprep_dma_buf_s4 - Un-map DMA mapping of SG-list for SLI4 dev
- * @phba: The Hba for which this call is being executed.
- * @psb: The scsi buffer which is going to be un-mapped.
- *
- * This routine does DMA un-mapping of scatter gather list of scsi command
- * field of @lpfc_cmd for device with SLI-4 interface spec. If we have to
- * remove the sgl for this scsi buffer then we will do it here. For now
- * we should be able to just call the sli3 unprep routine.
- **/
-static void
-lpfc_scsi_unprep_dma_buf_s4(struct lpfc_hba *phba, struct lpfc_scsi_buf *psb)
-{
-        lpfc_scsi_unprep_dma_buf_s3(phba, psb);
-}
-
-/**
- * lpfc_scsi_unprep_dma_buf - Wrapper function for unmap DMA mapping of SG-list
- * @phba: The Hba for which this call is being executed.
- * @psb: The scsi buffer which is going to be un-mapped.
- *
- * This routine does DMA un-mapping of scatter gather list of scsi command
- * field of @lpfc_cmd for device with SLI-4 interface spec.
- **/
-static void
-lpfc_scsi_unprep_dma_buf(struct lpfc_hba *phba, struct lpfc_scsi_buf *psb)
-{
-        phba->lpfc_scsi_unprep_dma_buf(phba, psb);
-}
-
-/**
  * lpfc_handler_fcp_err - FCP response handler
  * @vport: The virtual port for which this call is being executed.
  * @lpfc_cmd: Pointer to lpfc_scsi_buf data structure.
@@ -2461,7 +2452,7 @@ lpfc_fcpcmd_to_iocb(uint8_t *data, struct fcp_cmnd *fcp_cmnd)
 }
 
 /**
- * lpfc_scsi_prep_cmnd_s3 - Convert scsi cmnd to FCP infor unit for SLI3 dev
+ * lpfc_scsi_prep_cmnd - Wrapper func for convert scsi cmnd to FCP info unit
  * @vport: The virtual port for which this call is being executed.
  * @lpfc_cmd: The scsi command which needs to send.
  * @pnode: Pointer to lpfc_nodelist.
@@ -2470,7 +2461,7 @@ lpfc_fcpcmd_to_iocb(uint8_t *data, struct fcp_cmnd *fcp_cmnd)
  * to transfer for device with SLI3 interface spec.
  **/
 static void
-lpfc_scsi_prep_cmnd_s3(struct lpfc_vport *vport, struct lpfc_scsi_buf *lpfc_cmd,
+lpfc_scsi_prep_cmnd(struct lpfc_vport *vport, struct lpfc_scsi_buf *lpfc_cmd,
                     struct lpfc_nodelist *pnode)
 {
         struct lpfc_hba *phba = vport->phba;
@@ -2558,46 +2549,7 @@ lpfc_scsi_prep_cmnd_s3(struct lpfc_vport *vport, struct lpfc_scsi_buf *lpfc_cmd,
 }
 
 /**
- * lpfc_scsi_prep_cmnd_s4 - Convert scsi cmnd to FCP infor unit for SLI4 dev
- * @vport: The virtual port for which this call is being executed.
- * @lpfc_cmd: The scsi command which needs to send.
- * @pnode: Pointer to lpfc_nodelist.
- *
- * This routine initializes fcp_cmnd and iocb data structure from scsi command
- * to transfer for device with SLI4 interface spec.
- **/
-static void
-lpfc_scsi_prep_cmnd_s4(struct lpfc_vport *vport, struct lpfc_scsi_buf *lpfc_cmd,
-                       struct lpfc_nodelist *pnode)
-{
-        /*
-         * The prep cmnd routines do not touch the sgl or its
-         * entries. We may not have to do anything different.
-         * I will leave this function in place until we can
-         * run some IO through the driver and determine if changes
-         * are needed.
-         */
-        return lpfc_scsi_prep_cmnd_s3(vport, lpfc_cmd, pnode);
-}
-
-/**
- * lpfc_scsi_prep_cmnd - Wrapper func for convert scsi cmnd to FCP info unit
- * @vport: The virtual port for which this call is being executed.
- * @lpfc_cmd: The scsi command which needs to send.
- * @pnode: Pointer to lpfc_nodelist.
- *
- * This routine wraps the actual convert SCSI cmnd function pointer from
- * the lpfc_hba struct.
- **/
-static inline void
-lpfc_scsi_prep_cmnd(struct lpfc_vport *vport, struct lpfc_scsi_buf *lpfc_cmd,
-                    struct lpfc_nodelist *pnode)
-{
-        vport->phba->lpfc_scsi_prep_cmnd(vport, lpfc_cmd, pnode);
-}
-
-/**
- * lpfc_scsi_prep_task_mgmt_cmnd_s3 - Convert SLI3 scsi TM cmd to FCP info unit
+ * lpfc_scsi_prep_task_mgmt_cmnd - Convert SLI3 scsi TM cmd to FCP info unit
  * @vport: The virtual port for which this call is being executed.
  * @lpfc_cmd: Pointer to lpfc_scsi_buf data structure.
  * @lun: Logical unit number.
@@ -2611,7 +2563,7 @@ lpfc_scsi_prep_cmnd(struct lpfc_vport *vport, struct lpfc_scsi_buf *lpfc_cmd,
  *   1 - Success
  **/
 static int
-lpfc_scsi_prep_task_mgmt_cmd_s3(struct lpfc_vport *vport,
+lpfc_scsi_prep_task_mgmt_cmd(struct lpfc_vport *vport,
                              struct lpfc_scsi_buf *lpfc_cmd,
                              unsigned int lun,
                              uint8_t task_mgmt_cmd)
@@ -2653,68 +2605,13 @@ lpfc_scsi_prep_task_mgmt_cmd_s3(struct lpfc_vport *vport,
                  * The driver will provide the timeout mechanism.
                  */
                 piocb->ulpTimeout = 0;
-        } else {
+        } else
                 piocb->ulpTimeout = lpfc_cmd->timeout;
-        }
-
-        return 1;
-}
-
-/**
- * lpfc_scsi_prep_task_mgmt_cmnd_s4 - Convert SLI4 scsi TM cmd to FCP info unit
- * @vport: The virtual port for which this call is being executed.
- * @lpfc_cmd: Pointer to lpfc_scsi_buf data structure.
- * @lun: Logical unit number.
- * @task_mgmt_cmd: SCSI task management command.
- *
- * This routine creates FCP information unit corresponding to @task_mgmt_cmd
- * for device with SLI-4 interface spec.
- *
- * Return codes:
- *      0 - Error
- *      1 - Success
- **/
-static int
-lpfc_scsi_prep_task_mgmt_cmd_s4(struct lpfc_vport *vport,
-                                struct lpfc_scsi_buf *lpfc_cmd,
-                                unsigned int lun,
-                                uint8_t task_mgmt_cmd)
-{
-        /*
-         * The prep cmnd routines do not touch the sgl or its
-         * entries. We may not have to do anything different.
-         * I will leave this function in place until we can
-         * run some IO through the driver and determine if changes
-         * are needed.
-         */
-        return lpfc_scsi_prep_task_mgmt_cmd_s3(vport, lpfc_cmd, lun,
-                                                task_mgmt_cmd);
-}
 
-/**
- * lpfc_scsi_prep_task_mgmt_cmnd - Wrapper func convert scsi TM cmd to FCP info
- * @vport: The virtual port for which this call is being executed.
- * @lpfc_cmd: Pointer to lpfc_scsi_buf data structure.
- * @lun: Logical unit number.
- * @task_mgmt_cmd: SCSI task management command.
- *
- * This routine wraps the actual convert SCSI TM to FCP information unit
- * function pointer from the lpfc_hba struct.
- *
- * Return codes:
- *      0 - Error
- *      1 - Success
- **/
-static inline int
-lpfc_scsi_prep_task_mgmt_cmd(struct lpfc_vport *vport,
-                             struct lpfc_scsi_buf *lpfc_cmd,
-                             unsigned int lun,
-                             uint8_t task_mgmt_cmd)
-{
-        struct lpfc_hba *phba = vport->phba;
+        if (vport->phba->sli_rev == LPFC_SLI_REV4)
+                lpfc_sli4_set_rsp_sgl_last(vport->phba, lpfc_cmd);
 
-        return phba->lpfc_scsi_prep_task_mgmt_cmd(vport, lpfc_cmd, lun,
-                                                  task_mgmt_cmd);
+        return 1;
 }
 
 /**
@@ -2730,23 +2627,19 @@ int
 lpfc_scsi_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
 {
 
+        phba->lpfc_scsi_unprep_dma_buf = lpfc_scsi_unprep_dma_buf;
+        phba->lpfc_scsi_prep_cmnd = lpfc_scsi_prep_cmnd;
+        phba->lpfc_get_scsi_buf = lpfc_get_scsi_buf;
+
         switch (dev_grp) {
         case LPFC_PCI_DEV_LP:
                 phba->lpfc_new_scsi_buf = lpfc_new_scsi_buf_s3;
                 phba->lpfc_scsi_prep_dma_buf = lpfc_scsi_prep_dma_buf_s3;
-                phba->lpfc_scsi_prep_cmnd = lpfc_scsi_prep_cmnd_s3;
-                phba->lpfc_scsi_unprep_dma_buf = lpfc_scsi_unprep_dma_buf_s3;
-                phba->lpfc_scsi_prep_task_mgmt_cmd =
-                                        lpfc_scsi_prep_task_mgmt_cmd_s3;
                 phba->lpfc_release_scsi_buf = lpfc_release_scsi_buf_s3;
                 break;
         case LPFC_PCI_DEV_OC:
                 phba->lpfc_new_scsi_buf = lpfc_new_scsi_buf_s4;
                 phba->lpfc_scsi_prep_dma_buf = lpfc_scsi_prep_dma_buf_s4;
-                phba->lpfc_scsi_prep_cmnd = lpfc_scsi_prep_cmnd_s4;
-                phba->lpfc_scsi_unprep_dma_buf = lpfc_scsi_unprep_dma_buf_s4;
-                phba->lpfc_scsi_prep_task_mgmt_cmd =
-                                        lpfc_scsi_prep_task_mgmt_cmd_s4;
                 phba->lpfc_release_scsi_buf = lpfc_release_scsi_buf_s4;
                 break;
         default:
@@ -2783,72 +2676,6 @@ lpfc_tskmgmt_def_cmpl(struct lpfc_hba *phba,
 }
 
 /**
- * lpfc_scsi_tgt_reset - Target reset handler
- * @lpfc_cmd: Pointer to lpfc_scsi_buf data structure
- * @vport: The virtual port for which this call is being executed.
- * @tgt_id: Target ID.
- * @lun: Lun number.
- * @rdata: Pointer to lpfc_rport_data.
- *
- * This routine issues a TARGET RESET iocb to reset a target with @tgt_id ID.
- *
- * Return Code:
- *   0x2003 - Error
- *   0x2002 - Success.
- **/
-static int
-lpfc_scsi_tgt_reset(struct lpfc_scsi_buf *lpfc_cmd, struct lpfc_vport *vport,
-                    unsigned  tgt_id, unsigned int lun,
-                    struct lpfc_rport_data *rdata)
-{
-        struct lpfc_hba   *phba = vport->phba;
-        struct lpfc_iocbq *iocbq;
-        struct lpfc_iocbq *iocbqrsp;
-        int ret;
-        int status;
-
-        if (!rdata->pnode || !NLP_CHK_NODE_ACT(rdata->pnode))
-                return FAILED;
-
-        lpfc_cmd->rdata = rdata;
-        status = lpfc_scsi_prep_task_mgmt_cmd(vport, lpfc_cmd, lun,
-                                           FCP_TARGET_RESET);
-        if (!status)
-                return FAILED;
-
-        iocbq = &lpfc_cmd->cur_iocbq;
-        iocbqrsp = lpfc_sli_get_iocbq(phba);
-
-        if (!iocbqrsp)
-                return FAILED;
-
-        /* Issue Target Reset to TGT <num> */
-        lpfc_printf_vlog(vport, KERN_INFO, LOG_FCP,
-                         "0702 Issue Target Reset to TGT %d Data: x%x x%x\n",
-                         tgt_id, rdata->pnode->nlp_rpi, rdata->pnode->nlp_flag);
-        status = lpfc_sli_issue_iocb_wait(phba, LPFC_FCP_RING,
-                                          iocbq, iocbqrsp, lpfc_cmd->timeout);
-        if (status != IOCB_SUCCESS) {
-                if (status == IOCB_TIMEDOUT) {
-                        iocbq->iocb_cmpl = lpfc_tskmgmt_def_cmpl;
-                        ret = TIMEOUT_ERROR;
-                } else
-                        ret = FAILED;
-                lpfc_cmd->status = IOSTAT_DRIVER_REJECT;
-        } else {
-                ret = SUCCESS;
-                lpfc_cmd->result = iocbqrsp->iocb.un.ulpWord[4];
-                lpfc_cmd->status = iocbqrsp->iocb.ulpStatus;
-                if (lpfc_cmd->status == IOSTAT_LOCAL_REJECT &&
-                        (lpfc_cmd->result & IOERR_DRVR_MASK))
-                                lpfc_cmd->status = IOSTAT_DRIVER_REJECT;
-        }
-
-        lpfc_sli_release_iocbq(phba, iocbqrsp);
-        return ret;
-}
-
-/**
  * lpfc_info - Info entry point of scsi_host_template data structure
  * @host: The scsi host for which this call is being executed.
  *
@@ -3228,156 +3055,334 @@ lpfc_abort_handler(struct scsi_cmnd *cmnd)
         return ret;
 }
 
+static char *
+lpfc_taskmgmt_name(uint8_t task_mgmt_cmd)
+{
+        switch (task_mgmt_cmd) {
+        case FCP_ABORT_TASK_SET:
+                return "ABORT_TASK_SET";
+        case FCP_CLEAR_TASK_SET:
+                return "FCP_CLEAR_TASK_SET";
+        case FCP_BUS_RESET:
+                return "FCP_BUS_RESET";
+        case FCP_LUN_RESET:
+                return "FCP_LUN_RESET";
+        case FCP_TARGET_RESET:
+                return "FCP_TARGET_RESET";
+        case FCP_CLEAR_ACA:
+                return "FCP_CLEAR_ACA";
+        case FCP_TERMINATE_TASK:
+                return "FCP_TERMINATE_TASK";
+        default:
+                return "unknown";
+        }
+}
+
 /**
- * lpfc_device_reset_handler - scsi_host_template eh_device_reset entry point
- * @cmnd: Pointer to scsi_cmnd data structure.
+ * lpfc_send_taskmgmt - Generic SCSI Task Mgmt Handler
+ * @vport: The virtual port for which this call is being executed.
+ * @rdata: Pointer to remote port local data
+ * @tgt_id: Target ID of remote device.
+ * @lun_id: Lun number for the TMF
+ * @task_mgmt_cmd: type of TMF to send
  *
- * This routine does a device reset by sending a TARGET_RESET task management
- * command.
+ * This routine builds and sends a TMF (SCSI Task Mgmt Function) to
+ * a remote port.
  *
- * Return code :
- *  0x2003 - Error
- *  0x2002 - Success
+ * Return Code:
+ *   0x2003 - Error
+ *   0x2002 - Success.
  **/
 static int
-lpfc_device_reset_handler(struct scsi_cmnd *cmnd)
+lpfc_send_taskmgmt(struct lpfc_vport *vport, struct lpfc_rport_data *rdata,
+                    unsigned  tgt_id, unsigned int lun_id,
+                    uint8_t task_mgmt_cmd)
 {
-        struct Scsi_Host  *shost = cmnd->device->host;
-        struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
         struct lpfc_hba   *phba = vport->phba;
         struct lpfc_scsi_buf *lpfc_cmd;
-        struct lpfc_iocbq *iocbq, *iocbqrsp;
-        struct lpfc_rport_data *rdata = cmnd->device->hostdata;
-        struct lpfc_nodelist *pnode = rdata->pnode;
-        unsigned long later;
-        int ret = SUCCESS;
+        struct lpfc_iocbq *iocbq;
+        struct lpfc_iocbq *iocbqrsp;
+        int ret;
         int status;
-        int cnt;
-        struct lpfc_scsi_event_header scsi_event;
 
-        lpfc_block_error_handler(cmnd);
-        /*
-         * If target is not in a MAPPED state, delay the reset until
-         * target is rediscovered or devloss timeout expires.
-         */
-        later = msecs_to_jiffies(2 * vport->cfg_devloss_tmo * 1000) + jiffies;
-        while (time_after(later, jiffies)) {
-                if (!pnode || !NLP_CHK_NODE_ACT(pnode))
-                        return FAILED;
-                if (pnode->nlp_state == NLP_STE_MAPPED_NODE)
-                        break;
-                schedule_timeout_uninterruptible(msecs_to_jiffies(500));
-                rdata = cmnd->device->hostdata;
-                if (!rdata)
-                        break;
-                pnode = rdata->pnode;
-        }
-
-        scsi_event.event_type = FC_REG_SCSI_EVENT;
-        scsi_event.subcategory = LPFC_EVENT_TGTRESET;
-        scsi_event.lun = 0;
-        memcpy(scsi_event.wwpn, &pnode->nlp_portname, sizeof(struct lpfc_name));
-        memcpy(scsi_event.wwnn, &pnode->nlp_nodename, sizeof(struct lpfc_name));
-
-        fc_host_post_vendor_event(shost,
-                fc_get_event_number(),
-                sizeof(scsi_event),
-                (char *)&scsi_event,
-                LPFC_NL_VENDOR_ID);
-
-        if (!rdata || pnode->nlp_state != NLP_STE_MAPPED_NODE) {
-                lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
-                                 "0721 LUN Reset rport "
-                                 "failure: msec x%x rdata x%p\n",
-                                 jiffies_to_msecs(jiffies - later), rdata);
+        if (!rdata->pnode || !NLP_CHK_NODE_ACT(rdata->pnode))
                 return FAILED;
-        }
+
         lpfc_cmd = lpfc_get_scsi_buf(phba);
         if (lpfc_cmd == NULL)
                 return FAILED;
         lpfc_cmd->timeout = 60;
         lpfc_cmd->rdata = rdata;
 
-        status = lpfc_scsi_prep_task_mgmt_cmd(vport, lpfc_cmd,
-                                              cmnd->device->lun,
-                                              FCP_TARGET_RESET);
+        status = lpfc_scsi_prep_task_mgmt_cmd(vport, lpfc_cmd, lun_id,
+                                           task_mgmt_cmd);
         if (!status) {
                 lpfc_release_scsi_buf(phba, lpfc_cmd);
                 return FAILED;
         }
-        iocbq = &lpfc_cmd->cur_iocbq;
 
-        /* get a buffer for this IOCB command response */
+        iocbq = &lpfc_cmd->cur_iocbq;
         iocbqrsp = lpfc_sli_get_iocbq(phba);
         if (iocbqrsp == NULL) {
                 lpfc_release_scsi_buf(phba, lpfc_cmd);
                 return FAILED;
         }
+
         lpfc_printf_vlog(vport, KERN_INFO, LOG_FCP,
-                         "0703 Issue target reset to TGT %d LUN %d "
-                         "rpi x%x nlp_flag x%x\n", cmnd->device->id,
-                         cmnd->device->lun, pnode->nlp_rpi, pnode->nlp_flag);
+                         "0702 Issue %s to TGT %d LUN %d "
+                         "rpi x%x nlp_flag x%x\n",
+                         lpfc_taskmgmt_name(task_mgmt_cmd), tgt_id, lun_id,
+                         rdata->pnode->nlp_rpi, rdata->pnode->nlp_flag);
+
         status = lpfc_sli_issue_iocb_wait(phba, LPFC_FCP_RING,
                                           iocbq, iocbqrsp, lpfc_cmd->timeout);
-        if (status == IOCB_TIMEDOUT) {
-                iocbq->iocb_cmpl = lpfc_tskmgmt_def_cmpl;
-                ret = TIMEOUT_ERROR;
-        } else {
-                if (status != IOCB_SUCCESS)
+        if (status != IOCB_SUCCESS) {
+                if (status == IOCB_TIMEDOUT) {
+                        iocbq->iocb_cmpl = lpfc_tskmgmt_def_cmpl;
+                        ret = TIMEOUT_ERROR;
+                } else
                         ret = FAILED;
-                lpfc_release_scsi_buf(phba, lpfc_cmd);
-        }
-        lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
-                         "0713 SCSI layer issued device reset (%d, %d) "
-                         "return x%x status x%x result x%x\n",
-                         cmnd->device->id, cmnd->device->lun, ret,
-                         iocbqrsp->iocb.ulpStatus,
+                lpfc_cmd->status = IOSTAT_DRIVER_REJECT;
+                lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
+                         "0727 TMF %s to TGT %d LUN %d failed (%d, %d)\n",
+                         lpfc_taskmgmt_name(task_mgmt_cmd),
+                         tgt_id, lun_id, iocbqrsp->iocb.ulpStatus,
                          iocbqrsp->iocb.un.ulpWord[4]);
+        } else
+                ret = SUCCESS;
+
         lpfc_sli_release_iocbq(phba, iocbqrsp);
-        cnt = lpfc_sli_sum_iocb(vport, cmnd->device->id, cmnd->device->lun,
-                                LPFC_CTX_TGT);
+
+        if (ret != TIMEOUT_ERROR)
+                lpfc_release_scsi_buf(phba, lpfc_cmd);
+
+        return ret;
+}
+
+/**
+ * lpfc_chk_tgt_mapped -
+ * @vport: The virtual port to check on
+ * @cmnd: Pointer to scsi_cmnd data structure.
+ *
+ * This routine delays until the scsi target (aka rport) for the
+ * command exists (is present and logged in) or we declare it non-existent.
+ *
+ * Return code :
+ *  0x2003 - Error
+ *  0x2002 - Success
+ **/
+static int
+lpfc_chk_tgt_mapped(struct lpfc_vport *vport, struct scsi_cmnd *cmnd)
+{
+        struct lpfc_rport_data *rdata = cmnd->device->hostdata;
+        struct lpfc_nodelist *pnode = rdata->pnode;
+        unsigned long later;
+
+        /*
+         * If target is not in a MAPPED state, delay until
+         * target is rediscovered or devloss timeout expires.
+         */
+        later = msecs_to_jiffies(2 * vport->cfg_devloss_tmo * 1000) + jiffies;
+        while (time_after(later, jiffies)) {
+                if (!pnode || !NLP_CHK_NODE_ACT(pnode))
+                        return FAILED;
+                if (pnode->nlp_state == NLP_STE_MAPPED_NODE)
+                        return SUCCESS;
+                schedule_timeout_uninterruptible(msecs_to_jiffies(500));
+                rdata = cmnd->device->hostdata;
+                if (!rdata)
+                        return FAILED;
+                pnode = rdata->pnode;
+        }
+        if (!pnode || !NLP_CHK_NODE_ACT(pnode) ||
+            (pnode->nlp_state != NLP_STE_MAPPED_NODE))
+                return FAILED;
+        return SUCCESS;
+}
+
+/**
+ * lpfc_reset_flush_io_context -
+ * @vport: The virtual port (scsi_host) for the flush context
+ * @tgt_id: If aborting by Target contect - specifies the target id
+ * @lun_id: If aborting by Lun context - specifies the lun id
+ * @context: specifies the context level to flush at.
+ *
+ * After a reset condition via TMF, we need to flush orphaned i/o
+ * contexts from the adapter. This routine aborts any contexts
+ * outstanding, then waits for their completions. The wait is
+ * bounded by devloss_tmo though.
+ *
+ * Return code :
+ *  0x2003 - Error
+ *  0x2002 - Success
+ **/
+static int
+lpfc_reset_flush_io_context(struct lpfc_vport *vport, uint16_t tgt_id,
+                        uint64_t lun_id, lpfc_ctx_cmd context)
+{
+        struct lpfc_hba   *phba = vport->phba;
+        unsigned long later;
+        int cnt;
+
+        cnt = lpfc_sli_sum_iocb(vport, tgt_id, lun_id, context);
         if (cnt)
                 lpfc_sli_abort_iocb(vport, &phba->sli.ring[phba->sli.fcp_ring],
-                                    cmnd->device->id, cmnd->device->lun,
-                                    LPFC_CTX_TGT);
+                                    tgt_id, lun_id, context);
         later = msecs_to_jiffies(2 * vport->cfg_devloss_tmo * 1000) + jiffies;
         while (time_after(later, jiffies) && cnt) {
                 schedule_timeout_uninterruptible(msecs_to_jiffies(20));
-                cnt = lpfc_sli_sum_iocb(vport, cmnd->device->id,
-                                        cmnd->device->lun, LPFC_CTX_TGT);
+                cnt = lpfc_sli_sum_iocb(vport, tgt_id, lun_id, context);
         }
         if (cnt) {
                 lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
-                                 "0719 device reset I/O flush failure: "
-                                 "cnt x%x\n", cnt);
-                ret = FAILED;
+                        "0724 I/O flush failure for context %s : cnt x%x\n",
+                        ((context == LPFC_CTX_LUN) ? "LUN" :
+                         ((context == LPFC_CTX_TGT) ? "TGT" :
+                          ((context == LPFC_CTX_HOST) ? "HOST" : "Unknown"))),
+                        cnt);
+                return FAILED;
         }
-        return ret;
+        return SUCCESS;
+}
+
+/**
+ * lpfc_device_reset_handler - scsi_host_template eh_device_reset entry point
+ * @cmnd: Pointer to scsi_cmnd data structure.
+ *
+ * This routine does a device reset by sending a LUN_RESET task management
+ * command.
+ *
+ * Return code :
+ *  0x2003 - Error
+ *  0x2002 - Success
+ **/
+static int
+lpfc_device_reset_handler(struct scsi_cmnd *cmnd)
+{
+        struct Scsi_Host  *shost = cmnd->device->host;
+        struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
+        struct lpfc_rport_data *rdata = cmnd->device->hostdata;
+        struct lpfc_nodelist *pnode = rdata->pnode;
+        unsigned tgt_id = cmnd->device->id;
+        unsigned int lun_id = cmnd->device->lun;
+        struct lpfc_scsi_event_header scsi_event;
+        int status;
+
+        lpfc_block_error_handler(cmnd);
+
+        status = lpfc_chk_tgt_mapped(vport, cmnd);
+        if (status == FAILED) {
+                lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
+                        "0721 Device Reset rport failure: rdata x%p\n", rdata);
+                return FAILED;
+        }
+
+        scsi_event.event_type = FC_REG_SCSI_EVENT;
+        scsi_event.subcategory = LPFC_EVENT_LUNRESET;
+        scsi_event.lun = lun_id;
+        memcpy(scsi_event.wwpn, &pnode->nlp_portname, sizeof(struct lpfc_name));
+        memcpy(scsi_event.wwnn, &pnode->nlp_nodename, sizeof(struct lpfc_name));
+
+        fc_host_post_vendor_event(shost, fc_get_event_number(),
+                sizeof(scsi_event), (char *)&scsi_event, LPFC_NL_VENDOR_ID);
+
+        status = lpfc_send_taskmgmt(vport, rdata, tgt_id, lun_id,
+                                                FCP_LUN_RESET);
+
+        lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
+                         "0713 SCSI layer issued Device Reset (%d, %d) "
+                         "return x%x\n", tgt_id, lun_id, status);
+
+        /*
+         * We have to clean up i/o as : they may be orphaned by the TMF;
+         * or if the TMF failed, they may be in an indeterminate state.
+         * So, continue on.
+         * We will report success if all the i/o aborts successfully.
+         */
+        status = lpfc_reset_flush_io_context(vport, tgt_id, lun_id,
+                                                LPFC_CTX_LUN);
+        return status;
+}
+
+/**
+ * lpfc_target_reset_handler - scsi_host_template eh_target_reset entry point
+ * @cmnd: Pointer to scsi_cmnd data structure.
+ *
+ * This routine does a target reset by sending a TARGET_RESET task management
+ * command.
+ *
+ * Return code :
+ *  0x2003 - Error
+ *  0x2002 - Success
+ **/
+static int
+lpfc_target_reset_handler(struct scsi_cmnd *cmnd)
+{
+        struct Scsi_Host  *shost = cmnd->device->host;
+        struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
+        struct lpfc_rport_data *rdata = cmnd->device->hostdata;
+        struct lpfc_nodelist *pnode = rdata->pnode;
+        unsigned tgt_id = cmnd->device->id;
+        unsigned int lun_id = cmnd->device->lun;
+        struct lpfc_scsi_event_header scsi_event;
+        int status;
+
+        lpfc_block_error_handler(cmnd);
+
+        status = lpfc_chk_tgt_mapped(vport, cmnd);
+        if (status == FAILED) {
+                lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
+                        "0722 Target Reset rport failure: rdata x%p\n", rdata);
+                return FAILED;
+        }
+
+        scsi_event.event_type = FC_REG_SCSI_EVENT;
+        scsi_event.subcategory = LPFC_EVENT_TGTRESET;
+        scsi_event.lun = 0;
+        memcpy(scsi_event.wwpn, &pnode->nlp_portname, sizeof(struct lpfc_name));
+        memcpy(scsi_event.wwnn, &pnode->nlp_nodename, sizeof(struct lpfc_name));
+
+        fc_host_post_vendor_event(shost, fc_get_event_number(),
+                sizeof(scsi_event), (char *)&scsi_event, LPFC_NL_VENDOR_ID);
+
+        status = lpfc_send_taskmgmt(vport, rdata, tgt_id, lun_id,
+                                        FCP_TARGET_RESET);
+
+        lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
+                         "0723 SCSI layer issued Target Reset (%d, %d) "
+                         "return x%x\n", tgt_id, lun_id, status);
+
+        /*
+         * We have to clean up i/o as : they may be orphaned by the TMF;
+         * or if the TMF failed, they may be in an indeterminate state.
+         * So, continue on.
+         * We will report success if all the i/o aborts successfully.
+         */
+        status = lpfc_reset_flush_io_context(vport, tgt_id, lun_id,
+                                        LPFC_CTX_TGT);
+        return status;
 }
 
 /**
  * lpfc_bus_reset_handler - scsi_host_template eh_bus_reset_handler entry point
  * @cmnd: Pointer to scsi_cmnd data structure.
  *
- * This routine does target reset to all target on @cmnd->device->host.
+ * This routine does target reset to all targets on @cmnd->device->host.
+ * This emulates Parallel SCSI Bus Reset Semantics.
  *
- * Return Code:
- *   0x2003 - Error
- *   0x2002 - Success
+ * Return code :
+ *  0x2003 - Error
+ *  0x2002 - Success
  **/
 static int
 lpfc_bus_reset_handler(struct scsi_cmnd *cmnd)
 {
         struct Scsi_Host  *shost = cmnd->device->host;
         struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
-        struct lpfc_hba   *phba = vport->phba;
         struct lpfc_nodelist *ndlp = NULL;
-        int match;
-        int ret = SUCCESS, status = SUCCESS, i;
-        int cnt;
-        struct lpfc_scsi_buf * lpfc_cmd;
-        unsigned long later;
         struct lpfc_scsi_event_header scsi_event;
+        int match;
+        int ret = SUCCESS, status, i;
 
         scsi_event.event_type = FC_REG_SCSI_EVENT;
         scsi_event.subcategory = LPFC_EVENT_BUSRESET;
@@ -3385,13 +3390,11 @@ lpfc_bus_reset_handler(struct scsi_cmnd *cmnd)
         memcpy(scsi_event.wwpn, &vport->fc_portname, sizeof(struct lpfc_name));
         memcpy(scsi_event.wwnn, &vport->fc_nodename, sizeof(struct lpfc_name));
 
-        fc_host_post_vendor_event(shost,
-                fc_get_event_number(),
-                sizeof(scsi_event),
-                (char *)&scsi_event,
-                LPFC_NL_VENDOR_ID);
+        fc_host_post_vendor_event(shost, fc_get_event_number(),
+                sizeof(scsi_event), (char *)&scsi_event, LPFC_NL_VENDOR_ID);
 
         lpfc_block_error_handler(cmnd);
+
         /*
          * Since the driver manages a single bus device, reset all
          * targets known to the driver.  Should any target reset
@@ -3414,16 +3417,11 @@ lpfc_bus_reset_handler(struct scsi_cmnd *cmnd)
                 spin_unlock_irq(shost->host_lock);
                 if (!match)
                         continue;
-                lpfc_cmd = lpfc_get_scsi_buf(phba);
-                if (lpfc_cmd) {
-                        lpfc_cmd->timeout = 60;
-                        status = lpfc_scsi_tgt_reset(lpfc_cmd, vport, i,
-                                                     cmnd->device->lun,
-                                                     ndlp->rport->dd_data);
-                        if (status != TIMEOUT_ERROR)
-                                lpfc_release_scsi_buf(phba, lpfc_cmd);
-                }
-                if (!lpfc_cmd || status != SUCCESS) {
+
+                status = lpfc_send_taskmgmt(vport, ndlp->rport->dd_data,
+                                        i, 0, FCP_TARGET_RESET);
+
+                if (status != SUCCESS) {
                         lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
                                          "0700 Bus Reset on target %d failed\n",
                                          i);
@@ -3431,25 +3429,16 @@ lpfc_bus_reset_handler(struct scsi_cmnd *cmnd)
                 }
         }
         /*
-         * All outstanding txcmplq I/Os should have been aborted by
-         * the targets.  Unfortunately, some targets do not abide by
-         * this forcing the driver to double check.
+         * We have to clean up i/o as : they may be orphaned by the TMFs
+         * above; or if any of the TMFs failed, they may be in an
+         * indeterminate state.
+         * We will report success if all the i/o aborts successfully.
          */
-        cnt = lpfc_sli_sum_iocb(vport, 0, 0, LPFC_CTX_HOST);
-        if (cnt)
-                lpfc_sli_abort_iocb(vport, &phba->sli.ring[phba->sli.fcp_ring],
-                                    0, 0, LPFC_CTX_HOST);
-        later = msecs_to_jiffies(2 * vport->cfg_devloss_tmo * 1000) + jiffies;
-        while (time_after(later, jiffies) && cnt) {
-                schedule_timeout_uninterruptible(msecs_to_jiffies(20));
-                cnt = lpfc_sli_sum_iocb(vport, 0, 0, LPFC_CTX_HOST);
-        }
-        if (cnt) {
-                lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
-                                 "0715 Bus Reset I/O flush failure: "
-                                 "cnt x%x left x%x\n", cnt, i);
+
+        status = lpfc_reset_flush_io_context(vport, 0, 0, LPFC_CTX_HOST);
+        if (status != SUCCESS)
                 ret = FAILED;
-        }
+
         lpfc_printf_vlog(vport, KERN_ERR, LOG_FCP,
                          "0714 SCSI layer issued Bus Reset Data: x%x\n", ret);
         return ret;
@@ -3582,7 +3571,8 @@ struct scsi_host_template lpfc_template = {
         .info                   = lpfc_info,
         .queuecommand           = lpfc_queuecommand,
         .eh_abort_handler       = lpfc_abort_handler,
-        .eh_device_reset_handler= lpfc_device_reset_handler,
+        .eh_device_reset_handler = lpfc_device_reset_handler,
+        .eh_target_reset_handler = lpfc_target_reset_handler,
         .eh_bus_reset_handler   = lpfc_bus_reset_handler,
         .slave_alloc            = lpfc_slave_alloc,
         .slave_configure        = lpfc_slave_configure,
@@ -3602,7 +3592,8 @@ struct scsi_host_template lpfc_vport_template = {
         .info                   = lpfc_info,
         .queuecommand           = lpfc_queuecommand,
         .eh_abort_handler       = lpfc_abort_handler,
-        .eh_device_reset_handler= lpfc_device_reset_handler,
+        .eh_device_reset_handler = lpfc_device_reset_handler,
+        .eh_target_reset_handler = lpfc_target_reset_handler,
         .eh_bus_reset_handler   = lpfc_bus_reset_handler,
         .slave_alloc            = lpfc_slave_alloc,
         .slave_configure        = lpfc_slave_configure,
diff --git a/drivers/scsi/lpfc/lpfc_sli.c b/drivers/scsi/lpfc/lpfc_sli.c
index ff04daf18f48..acc43b061ba1 100644
--- a/drivers/scsi/lpfc/lpfc_sli.c
+++ b/drivers/scsi/lpfc/lpfc_sli.c
@@ -4139,8 +4139,11 @@ lpfc_sli4_read_fcoe_params(struct lpfc_hba *phba,
                 return -EIO;
         }
         data_length = mqe->un.mb_words[5];
-        if (data_length > DMP_FCOEPARAM_RGN_SIZE)
+        if (data_length > DMP_FCOEPARAM_RGN_SIZE) {
+                lpfc_mbuf_free(phba, mp->virt, mp->phys);
+                kfree(mp);
                 return -EIO;
+        }
 
         lpfc_parse_fcoe_conf(phba, mp->virt, data_length);
         lpfc_mbuf_free(phba, mp->virt, mp->phys);
@@ -4211,27 +4214,6 @@ lpfc_sli4_read_rev(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq,
                 return -EIO;
         }
 
-        lpfc_printf_log(phba, KERN_INFO, LOG_MBOX | LOG_SLI,
-                        "(%d):0380 Mailbox cmd x%x Status x%x "
-                        "Data: x%x x%x x%x x%x x%x x%x x%x x%x x%x "
-                        "x%x x%x x%x x%x x%x x%x x%x x%x x%x "
-                        "CQ: x%x x%x x%x x%x\n",
-                        mboxq->vport ? mboxq->vport->vpi : 0,
-                        bf_get(lpfc_mqe_command, mqe),
-                        bf_get(lpfc_mqe_status, mqe),
-                        mqe->un.mb_words[0], mqe->un.mb_words[1],
-                        mqe->un.mb_words[2], mqe->un.mb_words[3],
-                        mqe->un.mb_words[4], mqe->un.mb_words[5],
-                        mqe->un.mb_words[6], mqe->un.mb_words[7],
-                        mqe->un.mb_words[8], mqe->un.mb_words[9],
-                        mqe->un.mb_words[10], mqe->un.mb_words[11],
-                        mqe->un.mb_words[12], mqe->un.mb_words[13],
-                        mqe->un.mb_words[14], mqe->un.mb_words[15],
-                        mqe->un.mb_words[16], mqe->un.mb_words[50],
-                        mboxq->mcqe.word0,
-                        mboxq->mcqe.mcqe_tag0,  mboxq->mcqe.mcqe_tag1,
-                        mboxq->mcqe.trailer);
-
         /*
          * The available vpd length cannot be bigger than the
          * DMA buffer passed to the port.  Catch the less than
@@ -4337,21 +4319,18 @@ lpfc_sli4_hba_setup(struct lpfc_hba *phba)
                 goto out_free_vpd;
 
         mqe = &mboxq->u.mqe;
-        if ((bf_get(lpfc_mbx_rd_rev_sli_lvl,
-                    &mqe->un.read_rev) != LPFC_SLI_REV4) ||
-            (bf_get(lpfc_mbx_rd_rev_fcoe, &mqe->un.read_rev) == 0)) {
+        phba->sli_rev = bf_get(lpfc_mbx_rd_rev_sli_lvl, &mqe->un.read_rev);
+        if (bf_get(lpfc_mbx_rd_rev_fcoe, &mqe->un.read_rev))
+                phba->hba_flag |= HBA_FCOE_SUPPORT;
+        if (phba->sli_rev != LPFC_SLI_REV4 ||
+            !(phba->hba_flag & HBA_FCOE_SUPPORT)) {
                 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
                         "0376 READ_REV Error. SLI Level %d "
                         "FCoE enabled %d\n",
-                        bf_get(lpfc_mbx_rd_rev_sli_lvl, &mqe->un.read_rev),
-                        bf_get(lpfc_mbx_rd_rev_fcoe, &mqe->un.read_rev));
+                        phba->sli_rev, phba->hba_flag & HBA_FCOE_SUPPORT);
                 rc = -EIO;
                 goto out_free_vpd;
         }
-        /* Single threaded at this point, no need for lock */
-        spin_lock_irq(&phba->hbalock);
-        phba->hba_flag |= HBA_FCOE_SUPPORT;
-        spin_unlock_irq(&phba->hbalock);
         /*
          * Evaluate the read rev and vpd data. Populate the driver
          * state with the results. If this routine fails, the failure
@@ -4365,8 +4344,32 @@ lpfc_sli4_hba_setup(struct lpfc_hba *phba)
                 rc = 0;
         }
 
-        /* By now, we should determine the SLI revision, hard code for now */
-        phba->sli_rev = LPFC_SLI_REV4;
+        /* Save information as VPD data */
+        phba->vpd.rev.biuRev = mqe->un.read_rev.first_hw_rev;
+        phba->vpd.rev.smRev = mqe->un.read_rev.second_hw_rev;
+        phba->vpd.rev.endecRev = mqe->un.read_rev.third_hw_rev;
+        phba->vpd.rev.fcphHigh = bf_get(lpfc_mbx_rd_rev_fcph_high,
+                                         &mqe->un.read_rev);
+        phba->vpd.rev.fcphLow = bf_get(lpfc_mbx_rd_rev_fcph_low,
+                                       &mqe->un.read_rev);
+        phba->vpd.rev.feaLevelHigh = bf_get(lpfc_mbx_rd_rev_ftr_lvl_high,
+                                            &mqe->un.read_rev);
+        phba->vpd.rev.feaLevelLow = bf_get(lpfc_mbx_rd_rev_ftr_lvl_low,
+                                           &mqe->un.read_rev);
+        phba->vpd.rev.sli1FwRev = mqe->un.read_rev.fw_id_rev;
+        memcpy(phba->vpd.rev.sli1FwName, mqe->un.read_rev.fw_name, 16);
+        phba->vpd.rev.sli2FwRev = mqe->un.read_rev.ulp_fw_id_rev;
+        memcpy(phba->vpd.rev.sli2FwName, mqe->un.read_rev.ulp_fw_name, 16);
+        phba->vpd.rev.opFwRev = mqe->un.read_rev.fw_id_rev;
+        memcpy(phba->vpd.rev.opFwName, mqe->un.read_rev.fw_name, 16);
+        lpfc_printf_log(phba, KERN_INFO, LOG_MBOX | LOG_SLI,
+                        "(%d):0380 READ_REV Status x%x "
+                        "fw_rev:%s fcphHi:%x fcphLo:%x flHi:%x flLo:%x\n",
+                        mboxq->vport ? mboxq->vport->vpi : 0,
+                        bf_get(lpfc_mqe_status, mqe),
+                        phba->vpd.rev.opFwName,
+                        phba->vpd.rev.fcphHigh, phba->vpd.rev.fcphLow,
+                        phba->vpd.rev.feaLevelHigh, phba->vpd.rev.feaLevelLow);
 
         /*
          * Discover the port's supported feature set and match it against the
@@ -4491,8 +4494,10 @@ lpfc_sli4_hba_setup(struct lpfc_hba *phba)
                 rc = -ENODEV;
                 goto out_free_vpd;
         }
-        /* Temporary initialization of lpfc_fip_flag to non-fip */
-        bf_set(lpfc_fip_flag, &phba->sli4_hba.sli4_flags, 0);
+        if (phba->cfg_enable_fip)
+                bf_set(lpfc_fip_flag, &phba->sli4_hba.sli4_flags, 1);
+        else
+                bf_set(lpfc_fip_flag, &phba->sli4_hba.sli4_flags, 0);
 
         /* Set up all the queues to the device */
         rc = lpfc_sli4_queue_setup(phba);
@@ -5030,6 +5035,92 @@ out_not_finished:
 }
 
 /**
+ * lpfc_sli4_async_mbox_block - Block posting SLI4 asynchronous mailbox command
+ * @phba: Pointer to HBA context object.
+ *
+ * The function blocks the posting of SLI4 asynchronous mailbox commands from
+ * the driver internal pending mailbox queue. It will then try to wait out the
+ * possible outstanding mailbox command before return.
+ *
+ * Returns:
+ *      0 - the outstanding mailbox command completed; otherwise, the wait for
+ *      the outstanding mailbox command timed out.
+ **/
+static int
+lpfc_sli4_async_mbox_block(struct lpfc_hba *phba)
+{
+        struct lpfc_sli *psli = &phba->sli;
+        uint8_t actcmd = MBX_HEARTBEAT;
+        int rc = 0;
+        unsigned long timeout;
+
+        /* Mark the asynchronous mailbox command posting as blocked */
+        spin_lock_irq(&phba->hbalock);
+        psli->sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
+        if (phba->sli.mbox_active)
+                actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
+        spin_unlock_irq(&phba->hbalock);
+        /* Determine how long we might wait for the active mailbox
+         * command to be gracefully completed by firmware.
+         */
+        timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba, actcmd) * 1000) +
+                                   jiffies;
+        /* Wait for the outstnading mailbox command to complete */
+        while (phba->sli.mbox_active) {
+                /* Check active mailbox complete status every 2ms */
+                msleep(2);
+                if (time_after(jiffies, timeout)) {
+                        /* Timeout, marked the outstanding cmd not complete */
+                        rc = 1;
+                        break;
+                }
+        }
+
+        /* Can not cleanly block async mailbox command, fails it */
+        if (rc) {
+                spin_lock_irq(&phba->hbalock);
+                psli->sli_flag &= ~LPFC_SLI_ASYNC_MBX_BLK;
+                spin_unlock_irq(&phba->hbalock);
+        }
+        return rc;
+}
+
+/**
+ * lpfc_sli4_async_mbox_unblock - Block posting SLI4 async mailbox command
+ * @phba: Pointer to HBA context object.
+ *
+ * The function unblocks and resume posting of SLI4 asynchronous mailbox
+ * commands from the driver internal pending mailbox queue. It makes sure
+ * that there is no outstanding mailbox command before resuming posting
+ * asynchronous mailbox commands. If, for any reason, there is outstanding
+ * mailbox command, it will try to wait it out before resuming asynchronous
+ * mailbox command posting.
+ **/
+static void
+lpfc_sli4_async_mbox_unblock(struct lpfc_hba *phba)
+{
+        struct lpfc_sli *psli = &phba->sli;
+
+        spin_lock_irq(&phba->hbalock);
+        if (!(psli->sli_flag & LPFC_SLI_ASYNC_MBX_BLK)) {
+                /* Asynchronous mailbox posting is not blocked, do nothing */
+                spin_unlock_irq(&phba->hbalock);
+                return;
+        }
+
+        /* Outstanding synchronous mailbox command is guaranteed to be done,
+         * successful or timeout, after timing-out the outstanding mailbox
+         * command shall always be removed, so just unblock posting async
+         * mailbox command and resume
+         */
+        psli->sli_flag &= ~LPFC_SLI_ASYNC_MBX_BLK;
+        spin_unlock_irq(&phba->hbalock);
+
+        /* wake up worker thread to post asynchronlous mailbox command */
+        lpfc_worker_wake_up(phba);
+}
+
+/**
  * lpfc_sli4_post_sync_mbox - Post an SLI4 mailbox to the bootstrap mailbox
  * @phba: Pointer to HBA context object.
  * @mboxq: Pointer to mailbox object.
@@ -5204,14 +5295,35 @@ lpfc_sli_issue_mbox_s4(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq,
                                         psli->sli_flag, flag);
                 return rc;
         } else if (flag == MBX_POLL) {
-                lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
-                                "(%d):2542 Mailbox command x%x (x%x) "
-                                "cannot issue Data: x%x x%x\n",
+                lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX | LOG_SLI,
+                                "(%d):2542 Try to issue mailbox command "
+                                "x%x (x%x) synchronously ahead of async"
+                                "mailbox command queue: x%x x%x\n",
                                 mboxq->vport ? mboxq->vport->vpi : 0,
                                 mboxq->u.mb.mbxCommand,
                                 lpfc_sli4_mbox_opcode_get(phba, mboxq),
                                 psli->sli_flag, flag);
-                return -EIO;
+                /* Try to block the asynchronous mailbox posting */
+                rc = lpfc_sli4_async_mbox_block(phba);
+                if (!rc) {
+                        /* Successfully blocked, now issue sync mbox cmd */
+                        rc = lpfc_sli4_post_sync_mbox(phba, mboxq);
+                        if (rc != MBX_SUCCESS)
+                                lpfc_printf_log(phba, KERN_ERR,
+                                                LOG_MBOX | LOG_SLI,
+                                                "(%d):2597 Mailbox command "
+                                                "x%x (x%x) cannot issue "
+                                                "Data: x%x x%x\n",
+                                                mboxq->vport ?
+                                                mboxq->vport->vpi : 0,
+                                                mboxq->u.mb.mbxCommand,
+                                                lpfc_sli4_mbox_opcode_get(phba,
+                                                                mboxq),
+                                                psli->sli_flag, flag);
+                        /* Unblock the async mailbox posting afterward */
+                        lpfc_sli4_async_mbox_unblock(phba);
+                }
+                return rc;
         }
 
         /* Now, interrupt mode asynchrous mailbox command */
@@ -5749,18 +5861,13 @@ lpfc_sli4_iocb2wqe(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq,
 
         fip = bf_get(lpfc_fip_flag, &phba->sli4_hba.sli4_flags);
         /* The fcp commands will set command type */
-        if ((!(iocbq->iocb_flag &  LPFC_IO_FCP)) && (!fip))
-                command_type = ELS_COMMAND_NON_FIP;
-        else if (!(iocbq->iocb_flag &  LPFC_IO_FCP))
-                command_type = ELS_COMMAND_FIP;
-        else if (iocbq->iocb_flag &  LPFC_IO_FCP)
+        if (iocbq->iocb_flag &  LPFC_IO_FCP)
                 command_type = FCP_COMMAND;
-        else {
-                lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
-                        "2019 Invalid cmd 0x%x\n",
-                        iocbq->iocb.ulpCommand);
-                return IOCB_ERROR;
-        }
+        else if (fip && (iocbq->iocb_flag & LPFC_FIP_ELS))
+                command_type = ELS_COMMAND_FIP;
+        else
+                command_type = ELS_COMMAND_NON_FIP;
+
         /* Some of the fields are in the right position already */
         memcpy(wqe, &iocbq->iocb, sizeof(union lpfc_wqe));
         abort_tag = (uint32_t) iocbq->iotag;
@@ -5814,11 +5921,6 @@ lpfc_sli4_iocb2wqe(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq,
                 bf_set(lpfc_wqe_gen_context, &wqe->generic,
                                 iocbq->iocb.ulpContext);
 
-                if (iocbq->vport->fc_myDID != 0) {
-                        bf_set(els_req64_sid, &wqe->els_req,
-                                 iocbq->vport->fc_myDID);
-                        bf_set(els_req64_sp, &wqe->els_req, 1);
-                }
                 bf_set(lpfc_wqe_gen_ct, &wqe->generic, ct);
                 bf_set(lpfc_wqe_gen_pu, &wqe->generic, 0);
                 /* CCP CCPE PV PRI in word10 were set in the memcpy */
@@ -5877,14 +5979,19 @@ lpfc_sli4_iocb2wqe(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq,
                  * is set and we are sending our 2nd or greater command on
                  * this exchange.
                  */
+                /* Always open the exchange */
+                bf_set(wqe_xc, &wqe->fcp_iread.wqe_com, 0);
 
-        /* ALLOW read & write to fall through to ICMD64 */
+                wqe->words[10] &= 0xffff0000; /* zero out ebde count */
+                bf_set(lpfc_wqe_gen_pu, &wqe->generic, iocbq->iocb.ulpPU);
+                break;
         case CMD_FCP_ICMND64_CR:
                 /* Always open the exchange */
                 bf_set(wqe_xc, &wqe->fcp_iread.wqe_com, 0);
 
+                wqe->words[4] = 0;
                 wqe->words[10] &= 0xffff0000; /* zero out ebde count */
-                bf_set(lpfc_wqe_gen_pu, &wqe->generic, iocbq->iocb.ulpPU);
+                bf_set(lpfc_wqe_gen_pu, &wqe->generic, 0);
         break;
         case CMD_GEN_REQUEST64_CR:
                 /* word3 command length is described as byte offset to the
@@ -7247,6 +7354,32 @@ lpfc_sli_wake_iocb_wait(struct lpfc_hba *phba,
 }
 
 /**
+ * lpfc_chk_iocb_flg - Test IOCB flag with lock held.
+ * @phba: Pointer to HBA context object..
+ * @piocbq: Pointer to command iocb.
+ * @flag: Flag to test.
+ *
+ * This routine grabs the hbalock and then test the iocb_flag to
+ * see if the passed in flag is set.
+ * Returns:
+ * 1 if flag is set.
+ * 0 if flag is not set.
+ **/
+static int
+lpfc_chk_iocb_flg(struct lpfc_hba *phba,
+                 struct lpfc_iocbq *piocbq, uint32_t flag)
+{
+        unsigned long iflags;
+        int ret;
+
+        spin_lock_irqsave(&phba->hbalock, iflags);
+        ret = piocbq->iocb_flag & flag;
+        spin_unlock_irqrestore(&phba->hbalock, iflags);
+        return ret;
+
+}
+
+/**
  * lpfc_sli_issue_iocb_wait - Synchronous function to issue iocb commands
  * @phba: Pointer to HBA context object..
  * @pring: Pointer to sli ring.
@@ -7313,7 +7446,7 @@ lpfc_sli_issue_iocb_wait(struct lpfc_hba *phba,
         if (retval == IOCB_SUCCESS) {
                 timeout_req = timeout * HZ;
                 timeleft = wait_event_timeout(done_q,
-                                piocb->iocb_flag & LPFC_IO_WAKE,
+                                lpfc_chk_iocb_flg(phba, piocb, LPFC_IO_WAKE),
                                 timeout_req);
 
                 if (piocb->iocb_flag & LPFC_IO_WAKE) {
@@ -7498,20 +7631,16 @@ lpfc_sli_eratt_read(struct lpfc_hba *phba)
                 if ((HS_FFER1 & phba->work_hs) &&
                     ((HS_FFER2 | HS_FFER3 | HS_FFER4 | HS_FFER5 |
                      HS_FFER6 | HS_FFER7) & phba->work_hs)) {
-                        spin_lock_irq(&phba->hbalock);
                         phba->hba_flag |= DEFER_ERATT;
-                        spin_unlock_irq(&phba->hbalock);
                         /* Clear all interrupt enable conditions */
                         writel(0, phba->HCregaddr);
                         readl(phba->HCregaddr);
                 }
 
                 /* Set the driver HA work bitmap */
-                spin_lock_irq(&phba->hbalock);
                 phba->work_ha |= HA_ERATT;
                 /* Indicate polling handles this ERATT */
                 phba->hba_flag |= HBA_ERATT_HANDLED;
-                spin_unlock_irq(&phba->hbalock);
                 return 1;
         }
         return 0;
@@ -7557,12 +7686,10 @@ lpfc_sli4_eratt_read(struct lpfc_hba *phba)
                         return 0;
                         phba->work_status[0] = uerr_sta_lo;
                         phba->work_status[1] = uerr_sta_hi;
-                        spin_lock_irq(&phba->hbalock);
                         /* Set the driver HA work bitmap */
                         phba->work_ha |= HA_ERATT;
                         /* Indicate polling handles this ERATT */
                         phba->hba_flag |= HBA_ERATT_HANDLED;
-                        spin_unlock_irq(&phba->hbalock);
                         return 1;
                 }
         }
@@ -9245,6 +9372,7 @@ lpfc_sli4_queue_alloc(struct lpfc_hba *phba, uint32_t entry_size,
                         kfree(dmabuf);
                         goto out_fail;
                 }
+                memset(dmabuf->virt, 0, PAGE_SIZE);
                 dmabuf->buffer_tag = x;
                 list_add_tail(&dmabuf->list, &queue->page_list);
                 /* initialize queue's entry array */
@@ -9667,7 +9795,7 @@ lpfc_wq_create(struct lpfc_hba *phba, struct lpfc_queue *wq,
         /* link the wq onto the parent cq child list */
         list_add_tail(&wq->list, &cq->child_list);
 out:
-        if (rc == MBX_TIMEOUT)
+        if (rc != MBX_TIMEOUT)
                 mempool_free(mbox, phba->mbox_mem_pool);
         return status;
 }
@@ -11020,10 +11148,7 @@ lpfc_sli4_post_rpi_hdr(struct lpfc_hba *phba, struct lpfc_rpi_hdr *rpi_page)
                rpi_page->start_rpi);
         hdr_tmpl->rpi_paddr_lo = putPaddrLow(rpi_page->dmabuf->phys);
         hdr_tmpl->rpi_paddr_hi = putPaddrHigh(rpi_page->dmabuf->phys);
-        if (!phba->sli4_hba.intr_enable)
-                rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
-        else
-                rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
+        rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
         shdr = (union lpfc_sli4_cfg_shdr *) &hdr_tmpl->header.cfg_shdr;
         shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
         shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
@@ -11363,6 +11488,7 @@ lpfc_sli4_build_dflt_fcf_record(struct lpfc_hba *phba,
         bf_set(lpfc_fcf_record_fc_map_1, fcf_record, phba->fc_map[1]);
         bf_set(lpfc_fcf_record_fc_map_2, fcf_record, phba->fc_map[2]);
         bf_set(lpfc_fcf_record_fcf_valid, fcf_record, 1);
+        bf_set(lpfc_fcf_record_fcf_avail, fcf_record, 1);
         bf_set(lpfc_fcf_record_fcf_index, fcf_record, fcf_index);
         bf_set(lpfc_fcf_record_mac_addr_prov, fcf_record,
                 LPFC_FCF_FPMA | LPFC_FCF_SPMA);
diff --git a/drivers/scsi/lpfc/lpfc_sli.h b/drivers/scsi/lpfc/lpfc_sli.h
index 7d37eb7459bf..3c53316cf6d0 100644
--- a/drivers/scsi/lpfc/lpfc_sli.h
+++ b/drivers/scsi/lpfc/lpfc_sli.h
@@ -56,6 +56,7 @@ struct lpfc_iocbq {
 #define LPFC_DRIVER_ABORTED     8       /* driver aborted this request */
 #define LPFC_IO_FABRIC          0x10    /* Iocb send using fabric scheduler */
 #define LPFC_DELAY_MEM_FREE     0x20    /* Defer free'ing of FC data */
+#define LPFC_FIP_ELS            0x40
 
         uint8_t abort_count;
         uint8_t rsvd2;
diff --git a/drivers/scsi/lpfc/lpfc_sli4.h b/drivers/scsi/lpfc/lpfc_sli4.h
index 5196b46608d7..3b276b47d18f 100644
--- a/drivers/scsi/lpfc/lpfc_sli4.h
+++ b/drivers/scsi/lpfc/lpfc_sli4.h
@@ -229,7 +229,7 @@ struct lpfc_bmbx {
 
 #define LPFC_EQE_DEF_COUNT      1024
 #define LPFC_CQE_DEF_COUNT      256
-#define LPFC_WQE_DEF_COUNT      64
+#define LPFC_WQE_DEF_COUNT      256
 #define LPFC_MQE_DEF_COUNT      16
 #define LPFC_RQE_DEF_COUNT      512
 
diff --git a/drivers/scsi/lpfc/lpfc_version.h b/drivers/scsi/lpfc/lpfc_version.h
index 6b8a148f0a55..41094e02304b 100644
--- a/drivers/scsi/lpfc/lpfc_version.h
+++ b/drivers/scsi/lpfc/lpfc_version.h
@@ -18,7 +18,7 @@
  * included with this package.                                     *
  *******************************************************************/
 
-#define LPFC_DRIVER_VERSION "8.3.2"
+#define LPFC_DRIVER_VERSION "8.3.3"
 
 #define LPFC_DRIVER_NAME                "lpfc"
 #define LPFC_SP_DRIVER_HANDLER_NAME     "lpfc:sp"
diff --git a/drivers/scsi/lpfc/lpfc_vport.c b/drivers/scsi/lpfc/lpfc_vport.c
index a6313ee84ac5..e0b49922193e 100644
--- a/drivers/scsi/lpfc/lpfc_vport.c
+++ b/drivers/scsi/lpfc/lpfc_vport.c
@@ -695,8 +695,6 @@ lpfc_vport_delete(struct fc_vport *fc_vport)
                 }
                 vport->unreg_vpi_cmpl = VPORT_INVAL;
                 timeout = msecs_to_jiffies(phba->fc_ratov * 2000);
-                if (ndlp->nlp_state == NLP_STE_UNUSED_NODE)
-                        goto skip_logo;
                 if (!lpfc_issue_els_npiv_logo(vport, ndlp))
                         while (vport->unreg_vpi_cmpl == VPORT_INVAL && timeout)
                                 timeout = schedule_timeout(timeout);
diff --git a/drivers/scsi/ncr53c8xx.c b/drivers/scsi/ncr53c8xx.c
index 3b7240e40819..e3c482aa87b5 100644
--- a/drivers/scsi/ncr53c8xx.c
+++ b/drivers/scsi/ncr53c8xx.c
@@ -5444,7 +5444,7 @@ static void ncr_getsync(struct ncb *np, u_char sfac, u_char *fakp, u_char *scntl
         **      input speed faster than the period.
         */
         kpc = per * clk;
-        while (--div >= 0)
+        while (--div > 0)
                 if (kpc >= (div_10M[div] << 2)) break;
 
         /*
diff --git a/drivers/scsi/pcmcia/nsp_cs.c b/drivers/scsi/pcmcia/nsp_cs.c
index 11a61ea8d5d9..70b60ade049e 100644
--- a/drivers/scsi/pcmcia/nsp_cs.c
+++ b/drivers/scsi/pcmcia/nsp_cs.c
@@ -530,7 +530,7 @@ static int nsp_negate_signal(struct scsi_cmnd *SCpnt, unsigned char mask,
                 if (reg == 0xff) {
                         break;
                 }
-        } while ((time_out-- != 0) && (reg & mask) != 0);
+        } while ((--time_out != 0) && (reg & mask) != 0);
 
         if (time_out == 0) {
                 nsp_msg(KERN_DEBUG, " %s signal off timeut", str);
@@ -801,7 +801,7 @@ static void nsp_pio_read(struct scsi_cmnd *SCpnt)
 
         data->FifoCount = ocount;
 
-        if (time_out == 0) {
+        if (time_out < 0) {
                 nsp_msg(KERN_DEBUG, "pio read timeout resid=%d this_residual=%d buffers_residual=%d",
                         scsi_get_resid(SCpnt), SCpnt->SCp.this_residual,
                         SCpnt->SCp.buffers_residual);
@@ -897,7 +897,7 @@ static void nsp_pio_write(struct scsi_cmnd *SCpnt)
 
         data->FifoCount = ocount;
 
-        if (time_out == 0) {
+        if (time_out < 0) {
                 nsp_msg(KERN_DEBUG, "pio write timeout resid=0x%x",
                                                         scsi_get_resid(SCpnt));
         }
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c
index c8d0a176fea4..245e7afb4c4d 100644
--- a/drivers/scsi/qla2xxx/qla_isr.c
+++ b/drivers/scsi/qla2xxx/qla_isr.c
@@ -37,6 +37,7 @@ qla2100_intr_handler(int irq, void *dev_id)
         uint16_t        hccr;
         uint16_t        mb[4];
         struct rsp_que *rsp;
+        unsigned long   flags;
 
         rsp = (struct rsp_que *) dev_id;
         if (!rsp) {
@@ -49,7 +50,7 @@ qla2100_intr_handler(int irq, void *dev_id)
         reg = &ha->iobase->isp;
         status = 0;
 
-        spin_lock(&ha->hardware_lock);
+        spin_lock_irqsave(&ha->hardware_lock, flags);
         vha = pci_get_drvdata(ha->pdev);
         for (iter = 50; iter--; ) {
                 hccr = RD_REG_WORD(&reg->hccr);
@@ -101,7 +102,7 @@ qla2100_intr_handler(int irq, void *dev_id)
                         RD_REG_WORD(&reg->hccr);
                 }
         }
-        spin_unlock(&ha->hardware_lock);
+        spin_unlock_irqrestore(&ha->hardware_lock, flags);
 
         if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
             (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
@@ -133,6 +134,7 @@ qla2300_intr_handler(int irq, void *dev_id)
         uint16_t        mb[4];
         struct rsp_que *rsp;
         struct qla_hw_data *ha;
+        unsigned long   flags;
 
         rsp = (struct rsp_que *) dev_id;
         if (!rsp) {
@@ -145,7 +147,7 @@ qla2300_intr_handler(int irq, void *dev_id)
         reg = &ha->iobase->isp;
         status = 0;
 
-        spin_lock(&ha->hardware_lock);
+        spin_lock_irqsave(&ha->hardware_lock, flags);
         vha = pci_get_drvdata(ha->pdev);
         for (iter = 50; iter--; ) {
                 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
@@ -216,7 +218,7 @@ qla2300_intr_handler(int irq, void *dev_id)
                 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
                 RD_REG_WORD_RELAXED(&reg->hccr);
         }
-        spin_unlock(&ha->hardware_lock);
+        spin_unlock_irqrestore(&ha->hardware_lock, flags);
 
         if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
             (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
@@ -1626,6 +1628,7 @@ qla24xx_intr_handler(int irq, void *dev_id)
         uint32_t        hccr;
         uint16_t        mb[4];
         struct rsp_que *rsp;
+        unsigned long   flags;
 
         rsp = (struct rsp_que *) dev_id;
         if (!rsp) {
@@ -1638,7 +1641,7 @@ qla24xx_intr_handler(int irq, void *dev_id)
         reg = &ha->iobase->isp24;
         status = 0;
 
-        spin_lock(&ha->hardware_lock);
+        spin_lock_irqsave(&ha->hardware_lock, flags);
         vha = pci_get_drvdata(ha->pdev);
         for (iter = 50; iter--; ) {
                 stat = RD_REG_DWORD(&reg->host_status);
@@ -1688,7 +1691,7 @@ qla24xx_intr_handler(int irq, void *dev_id)
                 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
                 RD_REG_DWORD_RELAXED(&reg->hccr);
         }
-        spin_unlock(&ha->hardware_lock);
+        spin_unlock_irqrestore(&ha->hardware_lock, flags);
 
         if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
             (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c
index 6260505dceb5..010e69b29afe 100644
--- a/drivers/scsi/qla2xxx/qla_sup.c
+++ b/drivers/scsi/qla2xxx/qla_sup.c
@@ -945,7 +945,9 @@ qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
 
                 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV[%02x]: wwpn=%llx "
                         "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
-                        vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
+                        (unsigned long long)vid.port_name,
+                        (unsigned long long)vid.node_name,
+                        le16_to_cpu(entry->vf_id),
                         entry->q_qos, entry->f_qos));
 
                 if (i < QLA_PRECONFIG_VPORTS) {
@@ -954,7 +956,8 @@ qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
                                 qla_printk(KERN_INFO, ha,
                                 "NPIV-Config: Failed to create vport [%02x]: "
                                 "wwpn=%llx wwnn=%llx.\n", cnt,
-                                vid.port_name, vid.node_name);
+                                (unsigned long long)vid.port_name,
+                                (unsigned long long)vid.node_name);
                 }
         }
 done:
diff --git a/drivers/scsi/scsi_devinfo.c b/drivers/scsi/scsi_devinfo.c
index b13481369642..8821df9a277b 100644
--- a/drivers/scsi/scsi_devinfo.c
+++ b/drivers/scsi/scsi_devinfo.c
@@ -225,6 +225,7 @@ static struct {
         {"SGI", "Universal Xport", "*", BLIST_NO_ULD_ATTACH},
         {"IBM", "Universal Xport", "*", BLIST_NO_ULD_ATTACH},
         {"SUN", "Universal Xport", "*", BLIST_NO_ULD_ATTACH},
+        {"DELL", "Universal Xport", "*", BLIST_NO_ULD_ATTACH},
         {"SMSC", "USB 2 HS-CF", NULL, BLIST_SPARSELUN | BLIST_INQUIRY_36},
         {"SONY", "CD-ROM CDU-8001", NULL, BLIST_BORKEN},
         {"SONY", "TSL", NULL, BLIST_FORCELUN},          /* DDS3 & DDS4 autoloaders */
diff --git a/drivers/scsi/scsi_transport_fc.c b/drivers/scsi/scsi_transport_fc.c
index a152f89ae51c..3f64d93b6c8b 100644
--- a/drivers/scsi/scsi_transport_fc.c
+++ b/drivers/scsi/scsi_transport_fc.c
@@ -35,6 +35,7 @@
 #include <linux/netlink.h>
 #include <net/netlink.h>
 #include <scsi/scsi_netlink_fc.h>
+#include <scsi/scsi_bsg_fc.h>
 #include "scsi_priv.h"
 #include "scsi_transport_fc_internal.h"
 
@@ -43,6 +44,10 @@ static void fc_vport_sched_delete(struct work_struct *work);
 static int fc_vport_setup(struct Scsi_Host *shost, int channel,
         struct device *pdev, struct fc_vport_identifiers  *ids,
         struct fc_vport **vport);
+static int fc_bsg_hostadd(struct Scsi_Host *, struct fc_host_attrs *);
+static int fc_bsg_rportadd(struct Scsi_Host *, struct fc_rport *);
+static void fc_bsg_remove(struct request_queue *);
+static void fc_bsg_goose_queue(struct fc_rport *);
 
 /*
  * Redefine so that we can have same named attributes in the
@@ -411,13 +416,26 @@ static int fc_host_setup(struct transport_container *tc, struct device *dev,
                 return -ENOMEM;
         }
 
+        fc_bsg_hostadd(shost, fc_host);
+        /* ignore any bsg add error - we just can't do sgio */
+
+        return 0;
+}
+
+static int fc_host_remove(struct transport_container *tc, struct device *dev,
+                         struct device *cdev)
+{
+        struct Scsi_Host *shost = dev_to_shost(dev);
+        struct fc_host_attrs *fc_host = shost_to_fc_host(shost);
+
+        fc_bsg_remove(fc_host->rqst_q);
         return 0;
 }
 
 static DECLARE_TRANSPORT_CLASS(fc_host_class,
                                "fc_host",
                                fc_host_setup,
-                               NULL,
+                               fc_host_remove,
                                NULL);
 
 /*
@@ -2375,6 +2393,7 @@ fc_rport_final_delete(struct work_struct *work)
                 scsi_flush_work(shost);
 
         fc_terminate_rport_io(rport);
+
         /*
          * Cancel any outstanding timers. These should really exist
          * only when rmmod'ing the LLDD and we're asking for
@@ -2407,6 +2426,8 @@ fc_rport_final_delete(struct work_struct *work)
             (i->f->dev_loss_tmo_callbk))
                 i->f->dev_loss_tmo_callbk(rport);
 
+        fc_bsg_remove(rport->rqst_q);
+
         transport_remove_device(dev);
         device_del(dev);
         transport_destroy_device(dev);
@@ -2494,6 +2515,9 @@ fc_rport_create(struct Scsi_Host *shost, int channel,
         transport_add_device(dev);
         transport_configure_device(dev);
 
+        fc_bsg_rportadd(shost, rport);
+        /* ignore any bsg add error - we just can't do sgio */
+
         if (rport->roles & FC_PORT_ROLE_FCP_TARGET) {
                 /* initiate a scan of the target */
                 rport->flags |= FC_RPORT_SCAN_PENDING;
@@ -2658,6 +2682,8 @@ fc_remote_port_add(struct Scsi_Host *shost, int channel,
                                         spin_unlock_irqrestore(shost->host_lock,
                                                         flags);
 
+                                fc_bsg_goose_queue(rport);
+
                                 return rport;
                         }
                 }
@@ -3343,6 +3369,592 @@ fc_vport_sched_delete(struct work_struct *work)
 }
 
 
+/*
+ * BSG support
+ */
+
+
+/**
+ * fc_destroy_bsgjob - routine to teardown/delete a fc bsg job
+ * @job:        fc_bsg_job that is to be torn down
+ */
+static void
+fc_destroy_bsgjob(struct fc_bsg_job *job)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&job->job_lock, flags);
+        if (job->ref_cnt) {
+                spin_unlock_irqrestore(&job->job_lock, flags);
+                return;
+        }
+        spin_unlock_irqrestore(&job->job_lock, flags);
+
+        put_device(job->dev);   /* release reference for the request */
+
+        kfree(job->request_payload.sg_list);
+        kfree(job->reply_payload.sg_list);
+        kfree(job);
+}
+
+
+/**
+ * fc_bsg_jobdone - completion routine for bsg requests that the LLD has
+ *                  completed
+ * @job:        fc_bsg_job that is complete
+ */
+static void
+fc_bsg_jobdone(struct fc_bsg_job *job)
+{
+        struct request *req = job->req;
+        struct request *rsp = req->next_rq;
+        unsigned long flags;
+        int err;
+
+        spin_lock_irqsave(&job->job_lock, flags);
+        job->state_flags |= FC_RQST_STATE_DONE;
+        job->ref_cnt--;
+        spin_unlock_irqrestore(&job->job_lock, flags);
+
+        err = job->req->errors = job->reply->result;
+        if (err < 0)
+                /* we're only returning the result field in the reply */
+                job->req->sense_len = sizeof(uint32_t);
+        else
+                job->req->sense_len = job->reply_len;
+
+        /* we assume all request payload was transferred, residual == 0 */
+        req->resid_len = 0;
+
+        if (rsp) {
+                WARN_ON(job->reply->reply_payload_rcv_len > rsp->resid_len);
+
+                /* set reply (bidi) residual */
+                rsp->resid_len -= min(job->reply->reply_payload_rcv_len,
+                                      rsp->resid_len);
+        }
+
+        blk_end_request_all(req, err);
+
+        fc_destroy_bsgjob(job);
+}
+
+
+/**
+ * fc_bsg_job_timeout - handler for when a bsg request timesout
+ * @req:        request that timed out
+ */
+static enum blk_eh_timer_return
+fc_bsg_job_timeout(struct request *req)
+{
+        struct fc_bsg_job *job = (void *) req->special;
+        struct Scsi_Host *shost = job->shost;
+        struct fc_internal *i = to_fc_internal(shost->transportt);
+        unsigned long flags;
+        int err = 0, done = 0;
+
+        if (job->rport && job->rport->port_state == FC_PORTSTATE_BLOCKED)
+                return BLK_EH_RESET_TIMER;
+
+        spin_lock_irqsave(&job->job_lock, flags);
+        if (job->state_flags & FC_RQST_STATE_DONE)
+                done = 1;
+        else
+                job->ref_cnt++;
+        spin_unlock_irqrestore(&job->job_lock, flags);
+
+        if (!done && i->f->bsg_timeout) {
+                /* call LLDD to abort the i/o as it has timed out */
+                err = i->f->bsg_timeout(job);
+                if (err)
+                        printk(KERN_ERR "ERROR: FC BSG request timeout - LLD "
+                                "abort failed with status %d\n", err);
+        }
+
+        if (!done) {
+                spin_lock_irqsave(&job->job_lock, flags);
+                job->ref_cnt--;
+                spin_unlock_irqrestore(&job->job_lock, flags);
+                fc_destroy_bsgjob(job);
+        }
+
+        /* the blk_end_sync_io() doesn't check the error */
+        return BLK_EH_HANDLED;
+}
+
+
+
+static int
+fc_bsg_map_buffer(struct fc_bsg_buffer *buf, struct request *req)
+{
+        size_t sz = (sizeof(struct scatterlist) * req->nr_phys_segments);
+
+        BUG_ON(!req->nr_phys_segments);
+
+        buf->sg_list = kzalloc(sz, GFP_KERNEL);
+        if (!buf->sg_list)
+                return -ENOMEM;
+        sg_init_table(buf->sg_list, req->nr_phys_segments);
+        buf->sg_cnt = blk_rq_map_sg(req->q, req, buf->sg_list);
+        buf->payload_len = blk_rq_bytes(req);
+        return 0;
+}
+
+
+/**
+ * fc_req_to_bsgjob - Allocate/create the fc_bsg_job structure for the
+ *                   bsg request
+ * @shost:      SCSI Host corresponding to the bsg object
+ * @rport:      (optional) FC Remote Port corresponding to the bsg object
+ * @req:        BSG request that needs a job structure
+ */
+static int
+fc_req_to_bsgjob(struct Scsi_Host *shost, struct fc_rport *rport,
+        struct request *req)
+{
+        struct fc_internal *i = to_fc_internal(shost->transportt);
+        struct request *rsp = req->next_rq;
+        struct fc_bsg_job *job;
+        int ret;
+
+        BUG_ON(req->special);
+
+        job = kzalloc(sizeof(struct fc_bsg_job) + i->f->dd_bsg_size,
+                        GFP_KERNEL);
+        if (!job)
+                return -ENOMEM;
+
+        /*
+         * Note: this is a bit silly.
+         * The request gets formatted as a SGIO v4 ioctl request, which
+         * then gets reformatted as a blk request, which then gets
+         * reformatted as a fc bsg request. And on completion, we have
+         * to wrap return results such that SGIO v4 thinks it was a scsi
+         * status.  I hope this was all worth it.
+         */
+
+        req->special = job;
+        job->shost = shost;
+        job->rport = rport;
+        job->req = req;
+        if (i->f->dd_bsg_size)
+                job->dd_data = (void *)&job[1];
+        spin_lock_init(&job->job_lock);
+        job->request = (struct fc_bsg_request *)req->cmd;
+        job->request_len = req->cmd_len;
+        job->reply = req->sense;
+        job->reply_len = SCSI_SENSE_BUFFERSIZE; /* Size of sense buffer
+                                                 * allocated */
+        if (req->bio) {
+                ret = fc_bsg_map_buffer(&job->request_payload, req);
+                if (ret)
+                        goto failjob_rls_job;
+        }
+        if (rsp && rsp->bio) {
+                ret = fc_bsg_map_buffer(&job->reply_payload, rsp);
+                if (ret)
+                        goto failjob_rls_rqst_payload;
+        }
+        job->job_done = fc_bsg_jobdone;
+        if (rport)
+                job->dev = &rport->dev;
+        else
+                job->dev = &shost->shost_gendev;
+        get_device(job->dev);           /* take a reference for the request */
+
+        job->ref_cnt = 1;
+
+        return 0;
+
+
+failjob_rls_rqst_payload:
+        kfree(job->request_payload.sg_list);
+failjob_rls_job:
+        kfree(job);
+        return -ENOMEM;
+}
+
+
+enum fc_dispatch_result {
+        FC_DISPATCH_BREAK,      /* on return, q is locked, break from q loop */
+        FC_DISPATCH_LOCKED,     /* on return, q is locked, continue on */
+        FC_DISPATCH_UNLOCKED,   /* on return, q is unlocked, continue on */
+};
+
+
+/**
+ * fc_bsg_host_dispatch - process fc host bsg requests and dispatch to LLDD
+ * @shost:      scsi host rport attached to
+ * @job:        bsg job to be processed
+ */
+static enum fc_dispatch_result
+fc_bsg_host_dispatch(struct request_queue *q, struct Scsi_Host *shost,
+                         struct fc_bsg_job *job)
+{
+        struct fc_internal *i = to_fc_internal(shost->transportt);
+        int cmdlen = sizeof(uint32_t);  /* start with length of msgcode */
+        int ret;
+
+        /* Validate the host command */
+        switch (job->request->msgcode) {
+        case FC_BSG_HST_ADD_RPORT:
+                cmdlen += sizeof(struct fc_bsg_host_add_rport);
+                break;
+
+        case FC_BSG_HST_DEL_RPORT:
+                cmdlen += sizeof(struct fc_bsg_host_del_rport);
+                break;
+
+        case FC_BSG_HST_ELS_NOLOGIN:
+                cmdlen += sizeof(struct fc_bsg_host_els);
+                /* there better be a xmt and rcv payloads */
+                if ((!job->request_payload.payload_len) ||
+                    (!job->reply_payload.payload_len)) {
+                        ret = -EINVAL;
+                        goto fail_host_msg;
+                }
+                break;
+
+        case FC_BSG_HST_CT:
+                cmdlen += sizeof(struct fc_bsg_host_ct);
+                /* there better be xmt and rcv payloads */
+                if ((!job->request_payload.payload_len) ||
+                    (!job->reply_payload.payload_len)) {
+                        ret = -EINVAL;
+                        goto fail_host_msg;
+                }
+                break;
+
+        case FC_BSG_HST_VENDOR:
+                cmdlen += sizeof(struct fc_bsg_host_vendor);
+                if ((shost->hostt->vendor_id == 0L) ||
+                    (job->request->rqst_data.h_vendor.vendor_id !=
+                        shost->hostt->vendor_id)) {
+                        ret = -ESRCH;
+                        goto fail_host_msg;
+                }
+                break;
+
+        default:
+                ret = -EBADR;
+                goto fail_host_msg;
+        }
+
+        /* check if we really have all the request data needed */
+        if (job->request_len < cmdlen) {
+                ret = -ENOMSG;
+                goto fail_host_msg;
+        }
+
+        ret = i->f->bsg_request(job);
+        if (!ret)
+                return FC_DISPATCH_UNLOCKED;
+
+fail_host_msg:
+        /* return the errno failure code as the only status */
+        BUG_ON(job->reply_len < sizeof(uint32_t));
+        job->reply->result = ret;
+        job->reply_len = sizeof(uint32_t);
+        fc_bsg_jobdone(job);
+        return FC_DISPATCH_UNLOCKED;
+}
+
+
+/*
+ * fc_bsg_goose_queue - restart rport queue in case it was stopped
+ * @rport:      rport to be restarted
+ */
+static void
+fc_bsg_goose_queue(struct fc_rport *rport)
+{
+        int flagset;
+
+        if (!rport->rqst_q)
+                return;
+
+        get_device(&rport->dev);
+
+        spin_lock(rport->rqst_q->queue_lock);
+        flagset = test_bit(QUEUE_FLAG_REENTER, &rport->rqst_q->queue_flags) &&
+                  !test_bit(QUEUE_FLAG_REENTER, &rport->rqst_q->queue_flags);
+        if (flagset)
+                queue_flag_set(QUEUE_FLAG_REENTER, rport->rqst_q);
+        __blk_run_queue(rport->rqst_q);
+        if (flagset)
+                queue_flag_clear(QUEUE_FLAG_REENTER, rport->rqst_q);
+        spin_unlock(rport->rqst_q->queue_lock);
+
+        put_device(&rport->dev);
+}
+
+
+/**
+ * fc_bsg_rport_dispatch - process rport bsg requests and dispatch to LLDD
+ * @shost:      scsi host rport attached to
+ * @rport:      rport request destined to
+ * @job:        bsg job to be processed
+ */
+static enum fc_dispatch_result
+fc_bsg_rport_dispatch(struct request_queue *q, struct Scsi_Host *shost,
+                         struct fc_rport *rport, struct fc_bsg_job *job)
+{
+        struct fc_internal *i = to_fc_internal(shost->transportt);
+        int cmdlen = sizeof(uint32_t);  /* start with length of msgcode */
+        int ret;
+
+        /* Validate the rport command */
+        switch (job->request->msgcode) {
+        case FC_BSG_RPT_ELS:
+                cmdlen += sizeof(struct fc_bsg_rport_els);
+                goto check_bidi;
+
+        case FC_BSG_RPT_CT:
+                cmdlen += sizeof(struct fc_bsg_rport_ct);
+check_bidi:
+                /* there better be xmt and rcv payloads */
+                if ((!job->request_payload.payload_len) ||
+                    (!job->reply_payload.payload_len)) {
+                        ret = -EINVAL;
+                        goto fail_rport_msg;
+                }
+                break;
+        default:
+                ret = -EBADR;
+                goto fail_rport_msg;
+        }
+
+        /* check if we really have all the request data needed */
+        if (job->request_len < cmdlen) {
+                ret = -ENOMSG;
+                goto fail_rport_msg;
+        }
+
+        ret = i->f->bsg_request(job);
+        if (!ret)
+                return FC_DISPATCH_UNLOCKED;
+
+fail_rport_msg:
+        /* return the errno failure code as the only status */
+        BUG_ON(job->reply_len < sizeof(uint32_t));
+        job->reply->result = ret;
+        job->reply_len = sizeof(uint32_t);
+        fc_bsg_jobdone(job);
+        return FC_DISPATCH_UNLOCKED;
+}
+
+
+/**
+ * fc_bsg_request_handler - generic handler for bsg requests
+ * @q:          request queue to manage
+ * @shost:      Scsi_Host related to the bsg object
+ * @rport:      FC remote port related to the bsg object (optional)
+ * @dev:        device structure for bsg object
+ */
+static void
+fc_bsg_request_handler(struct request_queue *q, struct Scsi_Host *shost,
+                       struct fc_rport *rport, struct device *dev)
+{
+        struct request *req;
+        struct fc_bsg_job *job;
+        enum fc_dispatch_result ret;
+
+        if (!get_device(dev))
+                return;
+
+        while (!blk_queue_plugged(q)) {
+                if (rport && (rport->port_state == FC_PORTSTATE_BLOCKED))
+                                break;
+
+                req = blk_fetch_request(q);
+                if (!req)
+                        break;
+
+                if (rport && (rport->port_state != FC_PORTSTATE_ONLINE)) {
+                        req->errors = -ENXIO;
+                        spin_unlock_irq(q->queue_lock);
+                        blk_end_request(req, -ENXIO, blk_rq_bytes(req));
+                        spin_lock_irq(q->queue_lock);
+                        continue;
+                }
+
+                spin_unlock_irq(q->queue_lock);
+
+                ret = fc_req_to_bsgjob(shost, rport, req);
+                if (ret) {
+                        req->errors = ret;
+                        blk_end_request(req, ret, blk_rq_bytes(req));
+                        spin_lock_irq(q->queue_lock);
+                        continue;
+                }
+
+                job = req->special;
+
+                /* check if we have the msgcode value at least */
+                if (job->request_len < sizeof(uint32_t)) {
+                        BUG_ON(job->reply_len < sizeof(uint32_t));
+                        job->reply->result = -ENOMSG;
+                        job->reply_len = sizeof(uint32_t);
+                        fc_bsg_jobdone(job);
+                        spin_lock_irq(q->queue_lock);
+                        continue;
+                }
+
+                /* the dispatch routines will unlock the queue_lock */
+                if (rport)
+                        ret = fc_bsg_rport_dispatch(q, shost, rport, job);
+                else
+                        ret = fc_bsg_host_dispatch(q, shost, job);
+
+                /* did dispatcher hit state that can't process any more */
+                if (ret == FC_DISPATCH_BREAK)
+                        break;
+
+                /* did dispatcher had released the lock */
+                if (ret == FC_DISPATCH_UNLOCKED)
+                        spin_lock_irq(q->queue_lock);
+        }
+
+        spin_unlock_irq(q->queue_lock);
+        put_device(dev);
+        spin_lock_irq(q->queue_lock);
+}
+
+
+/**
+ * fc_bsg_host_handler - handler for bsg requests for a fc host
+ * @q:          fc host request queue
+ */
+static void
+fc_bsg_host_handler(struct request_queue *q)
+{
+        struct Scsi_Host *shost = q->queuedata;
+
+        fc_bsg_request_handler(q, shost, NULL, &shost->shost_gendev);
+}
+
+
+/**
+ * fc_bsg_rport_handler - handler for bsg requests for a fc rport
+ * @q:          rport request queue
+ */
+static void
+fc_bsg_rport_handler(struct request_queue *q)
+{
+        struct fc_rport *rport = q->queuedata;
+        struct Scsi_Host *shost = rport_to_shost(rport);
+
+        fc_bsg_request_handler(q, shost, rport, &rport->dev);
+}
+
+
+/**
+ * fc_bsg_hostadd - Create and add the bsg hooks so we can receive requests
+ * @shost:      shost for fc_host
+ * @fc_host:    fc_host adding the structures to
+ */
+static int
+fc_bsg_hostadd(struct Scsi_Host *shost, struct fc_host_attrs *fc_host)
+{
+        struct device *dev = &shost->shost_gendev;
+        struct fc_internal *i = to_fc_internal(shost->transportt);
+        struct request_queue *q;
+        int err;
+        char bsg_name[BUS_ID_SIZE]; /*20*/
+
+        fc_host->rqst_q = NULL;
+
+        if (!i->f->bsg_request)
+                return -ENOTSUPP;
+
+        snprintf(bsg_name, sizeof(bsg_name),
+                 "fc_host%d", shost->host_no);
+
+        q = __scsi_alloc_queue(shost, fc_bsg_host_handler);
+        if (!q) {
+                printk(KERN_ERR "fc_host%d: bsg interface failed to "
+                                "initialize - no request queue\n",
+                                 shost->host_no);
+                return -ENOMEM;
+        }
+
+        q->queuedata = shost;
+        queue_flag_set_unlocked(QUEUE_FLAG_BIDI, q);
+        blk_queue_rq_timed_out(q, fc_bsg_job_timeout);
+        blk_queue_rq_timeout(q, FC_DEFAULT_BSG_TIMEOUT);
+
+        err = bsg_register_queue(q, dev, bsg_name, NULL);
+        if (err) {
+                printk(KERN_ERR "fc_host%d: bsg interface failed to "
+                                "initialize - register queue\n",
+                                shost->host_no);
+                blk_cleanup_queue(q);
+                return err;
+        }
+
+        fc_host->rqst_q = q;
+        return 0;
+}
+
+
+/**
+ * fc_bsg_rportadd - Create and add the bsg hooks so we can receive requests
+ * @shost:      shost that rport is attached to
+ * @rport:      rport that the bsg hooks are being attached to
+ */
+static int
+fc_bsg_rportadd(struct Scsi_Host *shost, struct fc_rport *rport)
+{
+        struct device *dev = &rport->dev;
+        struct fc_internal *i = to_fc_internal(shost->transportt);
+        struct request_queue *q;
+        int err;
+
+        rport->rqst_q = NULL;
+
+        if (!i->f->bsg_request)
+                return -ENOTSUPP;
+
+        q = __scsi_alloc_queue(shost, fc_bsg_rport_handler);
+        if (!q) {
+                printk(KERN_ERR "%s: bsg interface failed to "
+                                "initialize - no request queue\n",
+                                 dev->kobj.name);
+                return -ENOMEM;
+        }
+
+        q->queuedata = rport;
+        queue_flag_set_unlocked(QUEUE_FLAG_BIDI, q);
+        blk_queue_rq_timed_out(q, fc_bsg_job_timeout);
+        blk_queue_rq_timeout(q, BLK_DEFAULT_SG_TIMEOUT);
+
+        err = bsg_register_queue(q, dev, NULL, NULL);
+        if (err) {
+                printk(KERN_ERR "%s: bsg interface failed to "
+                                "initialize - register queue\n",
+                                 dev->kobj.name);
+                blk_cleanup_queue(q);
+                return err;
+        }
+
+        rport->rqst_q = q;
+        return 0;
+}
+
+
+/**
+ * fc_bsg_remove - Deletes the bsg hooks on fchosts/rports
+ * @q:  the request_queue that is to be torn down.
+ */
+static void
+fc_bsg_remove(struct request_queue *q)
+{
+        if (q) {
+                bsg_unregister_queue(q);
+                blk_cleanup_queue(q);
+        }
+}
+
+
 /* Original Author:  Martin Hicks */
 MODULE_AUTHOR("James Smart");
 MODULE_DESCRIPTION("FC Transport Attributes");
diff --git a/drivers/scsi/scsi_transport_spi.c b/drivers/scsi/scsi_transport_spi.c
index f49f55c6bfc8..654a34fb04cb 100644
--- a/drivers/scsi/scsi_transport_spi.c
+++ b/drivers/scsi/scsi_transport_spi.c
@@ -234,8 +234,10 @@ static int spi_setup_transport_attrs(struct transport_container *tc,
         spi_width(starget) = 0; /* narrow */
         spi_max_width(starget) = 1;
         spi_iu(starget) = 0;    /* no IU */
+        spi_max_iu(starget) = 1;
         spi_dt(starget) = 0;    /* ST */
         spi_qas(starget) = 0;
+        spi_max_qas(starget) = 1;
         spi_wr_flow(starget) = 0;
         spi_rd_strm(starget) = 0;
         spi_rti(starget) = 0;
@@ -360,9 +362,9 @@ static DEVICE_ATTR(field, S_IRUGO,				\
 /* The Parallel SCSI Tranport Attributes: */
 spi_transport_max_attr(offset, "%d\n");
 spi_transport_max_attr(width, "%d\n");
-spi_transport_rd_attr(iu, "%d\n");
+spi_transport_max_attr(iu, "%d\n");
 spi_transport_rd_attr(dt, "%d\n");
-spi_transport_rd_attr(qas, "%d\n");
+spi_transport_max_attr(qas, "%d\n");
 spi_transport_rd_attr(wr_flow, "%d\n");
 spi_transport_rd_attr(rd_strm, "%d\n");
 spi_transport_rd_attr(rti, "%d\n");
@@ -874,13 +876,13 @@ spi_dv_device_internal(struct scsi_device *sdev, u8 *buffer)
 
         /* try QAS requests; this should be harmless to set if the
          * target supports it */
-        if (scsi_device_qas(sdev)) {
+        if (scsi_device_qas(sdev) && spi_max_qas(starget)) {
                 DV_SET(qas, 1);
         } else {
                 DV_SET(qas, 0);
         }
 
-        if (scsi_device_ius(sdev) && min_period < 9) {
+        if (scsi_device_ius(sdev) && spi_max_iu(starget) && min_period < 9) {
                 /* This u320 (or u640). Set IU transfers */
                 DV_SET(iu, 1);
                 /* Then set the optional parameters */
@@ -1412,12 +1414,18 @@ static mode_t target_attribute_is_visible(struct kobject *kobj,
         else if (attr == &dev_attr_iu.attr &&
                  spi_support_ius(starget))
                 return TARGET_ATTRIBUTE_HELPER(iu);
+        else if (attr == &dev_attr_max_iu.attr &&
+                 spi_support_ius(starget))
+                return TARGET_ATTRIBUTE_HELPER(iu);
         else if (attr == &dev_attr_dt.attr &&
                  spi_support_dt(starget))
                 return TARGET_ATTRIBUTE_HELPER(dt);
         else if (attr == &dev_attr_qas.attr &&
                  spi_support_qas(starget))
                 return TARGET_ATTRIBUTE_HELPER(qas);
+        else if (attr == &dev_attr_max_qas.attr &&
+                 spi_support_qas(starget))
+                return TARGET_ATTRIBUTE_HELPER(qas);
         else if (attr == &dev_attr_wr_flow.attr &&
                  spi_support_ius(starget))
                 return TARGET_ATTRIBUTE_HELPER(wr_flow);
@@ -1447,8 +1455,10 @@ static struct attribute *target_attributes[] = {
         &dev_attr_width.attr,
         &dev_attr_max_width.attr,
         &dev_attr_iu.attr,
+        &dev_attr_max_iu.attr,
         &dev_attr_dt.attr,
         &dev_attr_qas.attr,
+        &dev_attr_max_qas.attr,
         &dev_attr_wr_flow.attr,
         &dev_attr_rd_strm.attr,
         &dev_attr_rti.attr,
diff --git a/drivers/serial/of_serial.c b/drivers/serial/of_serial.c
index 3f2027c70e46..02406ba6da1c 100644
--- a/drivers/serial/of_serial.c
+++ b/drivers/serial/of_serial.c
@@ -122,7 +122,7 @@ static int __devinit of_platform_serial_probe(struct of_device *ofdev,
 
         info->type = port_type;
         info->line = ret;
-        ofdev->dev.driver_data = info;
+        dev_set_drvdata(&ofdev->dev, info);
         return 0;
 out:
         kfree(info);
@@ -135,7 +135,7 @@ out:
  */
 static int of_platform_serial_remove(struct of_device *ofdev)
 {
-        struct of_serial_info *info = ofdev->dev.driver_data;
+        struct of_serial_info *info = dev_get_drvdata(&ofdev->dev);
         switch (info->type) {
 #ifdef CONFIG_SERIAL_8250
         case PORT_8250 ... PORT_MAX_8250:
diff --git a/drivers/spi/spi_mpc83xx.c b/drivers/spi/spi_mpc83xx.c
index f4573a96af24..a32ccb44065e 100644
--- a/drivers/spi/spi_mpc83xx.c
+++ b/drivers/spi/spi_mpc83xx.c
@@ -711,12 +711,12 @@ static int of_mpc83xx_spi_get_chipselects(struct device *dev)
                 return 0;
         }
 
-        pinfo->gpios = kmalloc(ngpios * sizeof(pinfo->gpios), GFP_KERNEL);
+        pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
         if (!pinfo->gpios)
                 return -ENOMEM;
-        memset(pinfo->gpios, -1, ngpios * sizeof(pinfo->gpios));
+        memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
 
-        pinfo->alow_flags = kzalloc(ngpios * sizeof(pinfo->alow_flags),
+        pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
                                     GFP_KERNEL);
         if (!pinfo->alow_flags) {
                 ret = -ENOMEM;
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 0dcf9ca0b0ac..925657889f0f 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -115,5 +115,9 @@ source "drivers/staging/line6/Kconfig"
 
 source "drivers/staging/serqt_usb/Kconfig"
 
+source "drivers/gpu/drm/radeon/Kconfig"
+
+source "drivers/staging/octeon/Kconfig"
+
 endif # !STAGING_EXCLUDE_BUILD
 endif # STAGING
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index 47dfd5b4288b..6da9c74c1840 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -40,3 +40,4 @@ obj-$(CONFIG_PLAN9AUTH)		+= p9auth/
 obj-$(CONFIG_HECI)              += heci/
 obj-$(CONFIG_LINE6_USB)         += line6/
 obj-$(CONFIG_USB_SERIAL_QUATECH_ESU100) += serqt_usb/
+obj-$(CONFIG_OCTEON_ETHERNET)   += octeon/
diff --git a/drivers/staging/octeon/Kconfig b/drivers/staging/octeon/Kconfig
new file mode 100644
index 000000000000..536e2382de54
--- /dev/null
+++ b/drivers/staging/octeon/Kconfig
@@ -0,0 +1,12 @@
+config OCTEON_ETHERNET
+        tristate "Cavium Networks Octeon Ethernet support"
+        depends on CPU_CAVIUM_OCTEON
+        select MII
+        help
+          This driver supports the builtin ethernet ports on Cavium
+          Networks' products in the Octeon family. This driver supports the
+          CN3XXX and CN5XXX Octeon processors.
+
+          To compile this driver as a module, choose M here.  The module
+          will be called octeon-ethernet.
+
diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile
new file mode 100644
index 000000000000..3c839e37d37f
--- /dev/null
+++ b/drivers/staging/octeon/Makefile
@@ -0,0 +1,30 @@
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 2005-2009 Cavium Networks
+#
+
+#
+# Makefile for Cavium OCTEON on-board ethernet driver
+#
+
+obj-${CONFIG_OCTEON_ETHERNET} :=  octeon-ethernet.o
+
+octeon-ethernet-objs := ethernet.o
+octeon-ethernet-objs += ethernet-common.o
+octeon-ethernet-objs += ethernet-mdio.o
+octeon-ethernet-objs += ethernet-mem.o
+octeon-ethernet-objs += ethernet-proc.o
+octeon-ethernet-objs += ethernet-rgmii.o
+octeon-ethernet-objs += ethernet-rx.o
+octeon-ethernet-objs += ethernet-sgmii.o
+octeon-ethernet-objs += ethernet-spi.o
+octeon-ethernet-objs += ethernet-tx.o
+octeon-ethernet-objs += ethernet-xaui.o
+octeon-ethernet-objs += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
+        cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \
+        cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \
+        cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
+        cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
+
diff --git a/drivers/staging/octeon/cvmx-address.h b/drivers/staging/octeon/cvmx-address.h
new file mode 100644
index 000000000000..3c74d826e2e6
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-address.h
@@ -0,0 +1,274 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2009 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * Typedefs and defines for working with Octeon physical addresses.
+ *
+ */
+#ifndef __CVMX_ADDRESS_H__
+#define __CVMX_ADDRESS_H__
+
+#if 0
+typedef enum {
+        CVMX_MIPS_SPACE_XKSEG = 3LL,
+        CVMX_MIPS_SPACE_XKPHYS = 2LL,
+        CVMX_MIPS_SPACE_XSSEG = 1LL,
+        CVMX_MIPS_SPACE_XUSEG = 0LL
+} cvmx_mips_space_t;
+#endif
+
+typedef enum {
+        CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
+        CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
+        CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
+        CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
+} cvmx_mips_xkseg_space_t;
+
+/* decodes <14:13> of a kseg3 window address */
+typedef enum {
+        CVMX_ADD_WIN_SCR = 0L,
+        /* see cvmx_add_win_dma_dec_t for further decode */
+        CVMX_ADD_WIN_DMA = 1L,
+        CVMX_ADD_WIN_UNUSED = 2L,
+        CVMX_ADD_WIN_UNUSED2 = 3L
+} cvmx_add_win_dec_t;
+
+/* decode within DMA space */
+typedef enum {
+        /*
+         * Add store data to the write buffer entry, allocating it if
+         * necessary.
+         */
+        CVMX_ADD_WIN_DMA_ADD = 0L,
+        /* send out the write buffer entry to DRAM */
+        CVMX_ADD_WIN_DMA_SENDMEM = 1L,
+        /* store data must be normal DRAM memory space address in this case */
+        /* send out the write buffer entry as an IOBDMA command */
+        CVMX_ADD_WIN_DMA_SENDDMA = 2L,
+        /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */
+        /* send out the write buffer entry as an IO write */
+        CVMX_ADD_WIN_DMA_SENDIO = 3L,
+        /* store data must be normal IO space address in this case */
+        /* send out a single-tick command on the NCB bus */
+        CVMX_ADD_WIN_DMA_SENDSINGLE = 4L,
+        /* no write buffer data needed/used */
+} cvmx_add_win_dma_dec_t;
+
+/*
+ *   Physical Address Decode
+ *
+ * Octeon-I HW never interprets this X (<39:36> reserved
+ * for future expansion), software should set to 0.
+ *
+ *  - 0x0 XXX0 0000 0000 to      DRAM         Cached
+ *  - 0x0 XXX0 0FFF FFFF
+ *
+ *  - 0x0 XXX0 1000 0000 to      Boot Bus     Uncached  (Converted to 0x1 00X0 1000 0000
+ *  - 0x0 XXX0 1FFF FFFF         + EJTAG                           to 0x1 00X0 1FFF FFFF)
+ *
+ *  - 0x0 XXX0 2000 0000 to      DRAM         Cached
+ *  - 0x0 XXXF FFFF FFFF
+ *
+ *  - 0x1 00X0 0000 0000 to      Boot Bus     Uncached
+ *  - 0x1 00XF FFFF FFFF
+ *
+ *  - 0x1 01X0 0000 0000 to      Other NCB    Uncached
+ *  - 0x1 FFXF FFFF FFFF         devices
+ *
+ * Decode of all Octeon addresses
+ */
+typedef union {
+
+        uint64_t u64;
+        /* mapped or unmapped virtual address */
+        struct {
+                uint64_t R:2;
+                uint64_t offset:62;
+        } sva;
+
+        /* mapped USEG virtual addresses (typically) */
+        struct {
+                uint64_t zeroes:33;
+                uint64_t offset:31;
+        } suseg;
+
+        /* mapped or unmapped virtual address */
+        struct {
+                uint64_t ones:33;
+                uint64_t sp:2;
+                uint64_t offset:29;
+        } sxkseg;
+
+        /*
+         * physical address accessed through xkphys unmapped virtual
+         * address.
+         */
+        struct {
+                uint64_t R:2;   /* CVMX_MIPS_SPACE_XKPHYS in this case */
+                uint64_t cca:3; /* ignored by octeon */
+                uint64_t mbz:10;
+                uint64_t pa:49; /* physical address */
+        } sxkphys;
+
+        /* physical address */
+        struct {
+                uint64_t mbz:15;
+                /* if set, the address is uncached and resides on MCB bus */
+                uint64_t is_io:1;
+                /*
+                 * the hardware ignores this field when is_io==0, else
+                 * device ID.
+                 */
+                uint64_t did:8;
+                /* the hardware ignores <39:36> in Octeon I */
+                uint64_t unaddr:4;
+                uint64_t offset:36;
+        } sphys;
+
+        /* physical mem address */
+        struct {
+                /* techically, <47:40> are dont-cares */
+                uint64_t zeroes:24;
+                /* the hardware ignores <39:36> in Octeon I */
+                uint64_t unaddr:4;
+                uint64_t offset:36;
+        } smem;
+
+        /* physical IO address */
+        struct {
+                uint64_t mem_region:2;
+                uint64_t mbz:13;
+                /* 1 in this case */
+                uint64_t is_io:1;
+                /*
+                 * The hardware ignores this field when is_io==0, else
+                 * device ID.
+                 */
+                uint64_t did:8;
+                /* the hardware ignores <39:36> in Octeon I */
+                uint64_t unaddr:4;
+                uint64_t offset:36;
+        } sio;
+
+        /*
+         * Scratchpad virtual address - accessed through a window at
+         * the end of kseg3
+         */
+        struct {
+                uint64_t ones:49;
+                /* CVMX_ADD_WIN_SCR (0) in this case */
+                cvmx_add_win_dec_t csrdec:2;
+                uint64_t addr:13;
+        } sscr;
+
+        /* there should only be stores to IOBDMA space, no loads */
+        /*
+         * IOBDMA virtual address - accessed through a window at the
+         * end of kseg3
+         */
+        struct {
+                uint64_t ones:49;
+                uint64_t csrdec:2;      /* CVMX_ADD_WIN_DMA (1) in this case */
+                uint64_t unused2:3;
+                uint64_t type:3;
+                uint64_t addr:7;
+        } sdma;
+
+        struct {
+                uint64_t didspace:24;
+                uint64_t unused:40;
+        } sfilldidspace;
+
+} cvmx_addr_t;
+
+/* These macros for used by 32 bit applications */
+
+#define CVMX_MIPS32_SPACE_KSEG0 1l
+#define CVMX_ADD_SEG32(segment, add) \
+        (((int32_t)segment << 31) | (int32_t)(add))
+
+/*
+ * Currently all IOs are performed using XKPHYS addressing. Linux uses
+ * the CvmMemCtl register to enable XKPHYS addressing to IO space from
+ * user mode.  Future OSes may need to change the upper bits of IO
+ * addresses. The following define controls the upper two bits for all
+ * IO addresses generated by the simple executive library.
+ */
+#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
+
+/* These macros simplify the process of creating common IO addresses */
+#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add))
+#ifndef CVMX_ADD_IO_SEG
+#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
+#endif
+#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
+#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40)
+#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid))
+
+  /* from include/ncb_rsl_id.v */
+#define CVMX_OCT_DID_MIS 0ULL   /* misc stuff */
+#define CVMX_OCT_DID_GMX0 1ULL
+#define CVMX_OCT_DID_GMX1 2ULL
+#define CVMX_OCT_DID_PCI 3ULL
+#define CVMX_OCT_DID_KEY 4ULL
+#define CVMX_OCT_DID_FPA 5ULL
+#define CVMX_OCT_DID_DFA 6ULL
+#define CVMX_OCT_DID_ZIP 7ULL
+#define CVMX_OCT_DID_RNG 8ULL
+#define CVMX_OCT_DID_IPD 9ULL
+#define CVMX_OCT_DID_PKT 10ULL
+#define CVMX_OCT_DID_TIM 11ULL
+#define CVMX_OCT_DID_TAG 12ULL
+  /* the rest are not on the IO bus */
+#define CVMX_OCT_DID_L2C 16ULL
+#define CVMX_OCT_DID_LMC 17ULL
+#define CVMX_OCT_DID_SPX0 18ULL
+#define CVMX_OCT_DID_SPX1 19ULL
+#define CVMX_OCT_DID_PIP 20ULL
+#define CVMX_OCT_DID_ASX0 22ULL
+#define CVMX_OCT_DID_ASX1 23ULL
+#define CVMX_OCT_DID_IOB 30ULL
+
+#define CVMX_OCT_DID_PKT_SEND       CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
+#define CVMX_OCT_DID_TAG_SWTAG      CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
+#define CVMX_OCT_DID_TAG_TAG1       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
+#define CVMX_OCT_DID_TAG_TAG2       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
+#define CVMX_OCT_DID_TAG_TAG3       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
+#define CVMX_OCT_DID_TAG_NULL_RD    CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
+#define CVMX_OCT_DID_TAG_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
+#define CVMX_OCT_DID_FAU_FAI        CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
+#define CVMX_OCT_DID_TIM_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
+#define CVMX_OCT_DID_KEY_RW         CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
+#define CVMX_OCT_DID_PCI_6          CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
+#define CVMX_OCT_DID_MIS_BOO        CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
+#define CVMX_OCT_DID_PCI_RML        CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
+#define CVMX_OCT_DID_IPD_CSR        CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
+#define CVMX_OCT_DID_DFA_CSR        CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
+#define CVMX_OCT_DID_MIS_CSR        CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
+#define CVMX_OCT_DID_ZIP_CSR        CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
+
+#endif /* __CVMX_ADDRESS_H__ */
diff --git a/drivers/staging/octeon/cvmx-asxx-defs.h b/drivers/staging/octeon/cvmx-asxx-defs.h
new file mode 100644
index 000000000000..91415a85e8d2
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-asxx-defs.h
@@ -0,0 +1,475 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_ASXX_DEFS_H__
+#define __CVMX_ASXX_DEFS_H__
+
+#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull))
+#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull))
+#define CVMX_ASXX_INT_EN(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_INT_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull))
+#define CVMX_ASXX_PRT_LOOP(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RLD_BYPASS(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RLD_COMP(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RLD_DATA_DRV(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RLD_SETTING(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RX_PRT_EN(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RX_WOL(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RX_WOL_MSK(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RX_WOL_POWOK(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_RX_WOL_SIG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_TX_COMP_BYP(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_ASXX_TX_PRT_EN(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull))
+
+union cvmx_asxx_gmii_rx_clk_set {
+        uint64_t u64;
+        struct cvmx_asxx_gmii_rx_clk_set_s {
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+        } s;
+        struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
+        struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
+        struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
+};
+
+union cvmx_asxx_gmii_rx_dat_set {
+        uint64_t u64;
+        struct cvmx_asxx_gmii_rx_dat_set_s {
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+        } s;
+        struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
+        struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
+        struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
+};
+
+union cvmx_asxx_int_en {
+        uint64_t u64;
+        struct cvmx_asxx_int_en_s {
+                uint64_t reserved_12_63:52;
+                uint64_t txpsh:4;
+                uint64_t txpop:4;
+                uint64_t ovrflw:4;
+        } s;
+        struct cvmx_asxx_int_en_cn30xx {
+                uint64_t reserved_11_63:53;
+                uint64_t txpsh:3;
+                uint64_t reserved_7_7:1;
+                uint64_t txpop:3;
+                uint64_t reserved_3_3:1;
+                uint64_t ovrflw:3;
+        } cn30xx;
+        struct cvmx_asxx_int_en_cn30xx cn31xx;
+        struct cvmx_asxx_int_en_s cn38xx;
+        struct cvmx_asxx_int_en_s cn38xxp2;
+        struct cvmx_asxx_int_en_cn30xx cn50xx;
+        struct cvmx_asxx_int_en_s cn58xx;
+        struct cvmx_asxx_int_en_s cn58xxp1;
+};
+
+union cvmx_asxx_int_reg {
+        uint64_t u64;
+        struct cvmx_asxx_int_reg_s {
+                uint64_t reserved_12_63:52;
+                uint64_t txpsh:4;
+                uint64_t txpop:4;
+                uint64_t ovrflw:4;
+        } s;
+        struct cvmx_asxx_int_reg_cn30xx {
+                uint64_t reserved_11_63:53;
+                uint64_t txpsh:3;
+                uint64_t reserved_7_7:1;
+                uint64_t txpop:3;
+                uint64_t reserved_3_3:1;
+                uint64_t ovrflw:3;
+        } cn30xx;
+        struct cvmx_asxx_int_reg_cn30xx cn31xx;
+        struct cvmx_asxx_int_reg_s cn38xx;
+        struct cvmx_asxx_int_reg_s cn38xxp2;
+        struct cvmx_asxx_int_reg_cn30xx cn50xx;
+        struct cvmx_asxx_int_reg_s cn58xx;
+        struct cvmx_asxx_int_reg_s cn58xxp1;
+};
+
+union cvmx_asxx_mii_rx_dat_set {
+        uint64_t u64;
+        struct cvmx_asxx_mii_rx_dat_set_s {
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+        } s;
+        struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
+        struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
+};
+
+union cvmx_asxx_prt_loop {
+        uint64_t u64;
+        struct cvmx_asxx_prt_loop_s {
+                uint64_t reserved_8_63:56;
+                uint64_t ext_loop:4;
+                uint64_t int_loop:4;
+        } s;
+        struct cvmx_asxx_prt_loop_cn30xx {
+                uint64_t reserved_7_63:57;
+                uint64_t ext_loop:3;
+                uint64_t reserved_3_3:1;
+                uint64_t int_loop:3;
+        } cn30xx;
+        struct cvmx_asxx_prt_loop_cn30xx cn31xx;
+        struct cvmx_asxx_prt_loop_s cn38xx;
+        struct cvmx_asxx_prt_loop_s cn38xxp2;
+        struct cvmx_asxx_prt_loop_cn30xx cn50xx;
+        struct cvmx_asxx_prt_loop_s cn58xx;
+        struct cvmx_asxx_prt_loop_s cn58xxp1;
+};
+
+union cvmx_asxx_rld_bypass {
+        uint64_t u64;
+        struct cvmx_asxx_rld_bypass_s {
+                uint64_t reserved_1_63:63;
+                uint64_t bypass:1;
+        } s;
+        struct cvmx_asxx_rld_bypass_s cn38xx;
+        struct cvmx_asxx_rld_bypass_s cn38xxp2;
+        struct cvmx_asxx_rld_bypass_s cn58xx;
+        struct cvmx_asxx_rld_bypass_s cn58xxp1;
+};
+
+union cvmx_asxx_rld_bypass_setting {
+        uint64_t u64;
+        struct cvmx_asxx_rld_bypass_setting_s {
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+        } s;
+        struct cvmx_asxx_rld_bypass_setting_s cn38xx;
+        struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
+        struct cvmx_asxx_rld_bypass_setting_s cn58xx;
+        struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
+};
+
+union cvmx_asxx_rld_comp {
+        uint64_t u64;
+        struct cvmx_asxx_rld_comp_s {
+                uint64_t reserved_9_63:55;
+                uint64_t pctl:5;
+                uint64_t nctl:4;
+        } s;
+        struct cvmx_asxx_rld_comp_cn38xx {
+                uint64_t reserved_8_63:56;
+                uint64_t pctl:4;
+                uint64_t nctl:4;
+        } cn38xx;
+        struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
+        struct cvmx_asxx_rld_comp_s cn58xx;
+        struct cvmx_asxx_rld_comp_s cn58xxp1;
+};
+
+union cvmx_asxx_rld_data_drv {
+        uint64_t u64;
+        struct cvmx_asxx_rld_data_drv_s {
+                uint64_t reserved_8_63:56;
+                uint64_t pctl:4;
+                uint64_t nctl:4;
+        } s;
+        struct cvmx_asxx_rld_data_drv_s cn38xx;
+        struct cvmx_asxx_rld_data_drv_s cn38xxp2;
+        struct cvmx_asxx_rld_data_drv_s cn58xx;
+        struct cvmx_asxx_rld_data_drv_s cn58xxp1;
+};
+
+union cvmx_asxx_rld_fcram_mode {
+        uint64_t u64;
+        struct cvmx_asxx_rld_fcram_mode_s {
+                uint64_t reserved_1_63:63;
+                uint64_t mode:1;
+        } s;
+        struct cvmx_asxx_rld_fcram_mode_s cn38xx;
+        struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
+};
+
+union cvmx_asxx_rld_nctl_strong {
+        uint64_t u64;
+        struct cvmx_asxx_rld_nctl_strong_s {
+                uint64_t reserved_5_63:59;
+                uint64_t nctl:5;
+        } s;
+        struct cvmx_asxx_rld_nctl_strong_s cn38xx;
+        struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
+        struct cvmx_asxx_rld_nctl_strong_s cn58xx;
+        struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
+};
+
+union cvmx_asxx_rld_nctl_weak {
+        uint64_t u64;
+        struct cvmx_asxx_rld_nctl_weak_s {
+                uint64_t reserved_5_63:59;
+                uint64_t nctl:5;
+        } s;
+        struct cvmx_asxx_rld_nctl_weak_s cn38xx;
+        struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
+        struct cvmx_asxx_rld_nctl_weak_s cn58xx;
+        struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
+};
+
+union cvmx_asxx_rld_pctl_strong {
+        uint64_t u64;
+        struct cvmx_asxx_rld_pctl_strong_s {
+                uint64_t reserved_5_63:59;
+                uint64_t pctl:5;
+        } s;
+        struct cvmx_asxx_rld_pctl_strong_s cn38xx;
+        struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
+        struct cvmx_asxx_rld_pctl_strong_s cn58xx;
+        struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
+};
+
+union cvmx_asxx_rld_pctl_weak {
+        uint64_t u64;
+        struct cvmx_asxx_rld_pctl_weak_s {
+                uint64_t reserved_5_63:59;
+                uint64_t pctl:5;
+        } s;
+        struct cvmx_asxx_rld_pctl_weak_s cn38xx;
+        struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
+        struct cvmx_asxx_rld_pctl_weak_s cn58xx;
+        struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
+};
+
+union cvmx_asxx_rld_setting {
+        uint64_t u64;
+        struct cvmx_asxx_rld_setting_s {
+                uint64_t reserved_13_63:51;
+                uint64_t dfaset:5;
+                uint64_t dfalag:1;
+                uint64_t dfalead:1;
+                uint64_t dfalock:1;
+                uint64_t setting:5;
+        } s;
+        struct cvmx_asxx_rld_setting_cn38xx {
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+        } cn38xx;
+        struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
+        struct cvmx_asxx_rld_setting_s cn58xx;
+        struct cvmx_asxx_rld_setting_s cn58xxp1;
+};
+
+union cvmx_asxx_rx_clk_setx {
+        uint64_t u64;
+        struct cvmx_asxx_rx_clk_setx_s {
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+        } s;
+        struct cvmx_asxx_rx_clk_setx_s cn30xx;
+        struct cvmx_asxx_rx_clk_setx_s cn31xx;
+        struct cvmx_asxx_rx_clk_setx_s cn38xx;
+        struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
+        struct cvmx_asxx_rx_clk_setx_s cn50xx;
+        struct cvmx_asxx_rx_clk_setx_s cn58xx;
+        struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
+};
+
+union cvmx_asxx_rx_prt_en {
+        uint64_t u64;
+        struct cvmx_asxx_rx_prt_en_s {
+                uint64_t reserved_4_63:60;
+                uint64_t prt_en:4;
+        } s;
+        struct cvmx_asxx_rx_prt_en_cn30xx {
+                uint64_t reserved_3_63:61;
+                uint64_t prt_en:3;
+        } cn30xx;
+        struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
+        struct cvmx_asxx_rx_prt_en_s cn38xx;
+        struct cvmx_asxx_rx_prt_en_s cn38xxp2;
+        struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
+        struct cvmx_asxx_rx_prt_en_s cn58xx;
+        struct cvmx_asxx_rx_prt_en_s cn58xxp1;
+};
+
+union cvmx_asxx_rx_wol {
+        uint64_t u64;
+        struct cvmx_asxx_rx_wol_s {
+                uint64_t reserved_2_63:62;
+                uint64_t status:1;
+                uint64_t enable:1;
+        } s;
+        struct cvmx_asxx_rx_wol_s cn38xx;
+        struct cvmx_asxx_rx_wol_s cn38xxp2;
+};
+
+union cvmx_asxx_rx_wol_msk {
+        uint64_t u64;
+        struct cvmx_asxx_rx_wol_msk_s {
+                uint64_t msk:64;
+        } s;
+        struct cvmx_asxx_rx_wol_msk_s cn38xx;
+        struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
+};
+
+union cvmx_asxx_rx_wol_powok {
+        uint64_t u64;
+        struct cvmx_asxx_rx_wol_powok_s {
+                uint64_t reserved_1_63:63;
+                uint64_t powerok:1;
+        } s;
+        struct cvmx_asxx_rx_wol_powok_s cn38xx;
+        struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
+};
+
+union cvmx_asxx_rx_wol_sig {
+        uint64_t u64;
+        struct cvmx_asxx_rx_wol_sig_s {
+                uint64_t reserved_32_63:32;
+                uint64_t sig:32;
+        } s;
+        struct cvmx_asxx_rx_wol_sig_s cn38xx;
+        struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
+};
+
+union cvmx_asxx_tx_clk_setx {
+        uint64_t u64;
+        struct cvmx_asxx_tx_clk_setx_s {
+                uint64_t reserved_5_63:59;
+                uint64_t setting:5;
+        } s;
+        struct cvmx_asxx_tx_clk_setx_s cn30xx;
+        struct cvmx_asxx_tx_clk_setx_s cn31xx;
+        struct cvmx_asxx_tx_clk_setx_s cn38xx;
+        struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
+        struct cvmx_asxx_tx_clk_setx_s cn50xx;
+        struct cvmx_asxx_tx_clk_setx_s cn58xx;
+        struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
+};
+
+union cvmx_asxx_tx_comp_byp {
+        uint64_t u64;
+        struct cvmx_asxx_tx_comp_byp_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_asxx_tx_comp_byp_cn30xx {
+                uint64_t reserved_9_63:55;
+                uint64_t bypass:1;
+                uint64_t pctl:4;
+                uint64_t nctl:4;
+        } cn30xx;
+        struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
+        struct cvmx_asxx_tx_comp_byp_cn38xx {
+                uint64_t reserved_8_63:56;
+                uint64_t pctl:4;
+                uint64_t nctl:4;
+        } cn38xx;
+        struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
+        struct cvmx_asxx_tx_comp_byp_cn50xx {
+                uint64_t reserved_17_63:47;
+                uint64_t bypass:1;
+                uint64_t reserved_13_15:3;
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:5;
+        } cn50xx;
+        struct cvmx_asxx_tx_comp_byp_cn58xx {
+                uint64_t reserved_13_63:51;
+                uint64_t pctl:5;
+                uint64_t reserved_5_7:3;
+                uint64_t nctl:5;
+        } cn58xx;
+        struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
+};
+
+union cvmx_asxx_tx_hi_waterx {
+        uint64_t u64;
+        struct cvmx_asxx_tx_hi_waterx_s {
+                uint64_t reserved_4_63:60;
+                uint64_t mark:4;
+        } s;
+        struct cvmx_asxx_tx_hi_waterx_cn30xx {
+                uint64_t reserved_3_63:61;
+                uint64_t mark:3;
+        } cn30xx;
+        struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
+        struct cvmx_asxx_tx_hi_waterx_s cn38xx;
+        struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
+        struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
+        struct cvmx_asxx_tx_hi_waterx_s cn58xx;
+        struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
+};
+
+union cvmx_asxx_tx_prt_en {
+        uint64_t u64;
+        struct cvmx_asxx_tx_prt_en_s {
+                uint64_t reserved_4_63:60;
+                uint64_t prt_en:4;
+        } s;
+        struct cvmx_asxx_tx_prt_en_cn30xx {
+                uint64_t reserved_3_63:61;
+                uint64_t prt_en:3;
+        } cn30xx;
+        struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
+        struct cvmx_asxx_tx_prt_en_s cn38xx;
+        struct cvmx_asxx_tx_prt_en_s cn38xxp2;
+        struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
+        struct cvmx_asxx_tx_prt_en_s cn58xx;
+        struct cvmx_asxx_tx_prt_en_s cn58xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-cmd-queue.c b/drivers/staging/octeon/cvmx-cmd-queue.c
new file mode 100644
index 000000000000..976227b01273
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-cmd-queue.c
@@ -0,0 +1,306 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Support functions for managing command queues used for
+ * various hardware blocks.
+ */
+
+#include <linux/kernel.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-config.h"
+#include "cvmx-fpa.h"
+#include "cvmx-cmd-queue.h"
+
+#include <asm/octeon/cvmx-npei-defs.h>
+#include <asm/octeon/cvmx-pexp-defs.h>
+#include "cvmx-pko-defs.h"
+
+/**
+ * This application uses this pointer to access the global queue
+ * state. It points to a bootmem named block.
+ */
+__cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr;
+
+/**
+ * Initialize the Global queue state pointer.
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void)
+{
+        char *alloc_name = "cvmx_cmd_queues";
+#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32
+        extern uint64_t octeon_reserve32_memory;
+#endif
+
+        if (likely(__cvmx_cmd_queue_state_ptr))
+                return CVMX_CMD_QUEUE_SUCCESS;
+
+#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32
+        if (octeon_reserve32_memory)
+                __cvmx_cmd_queue_state_ptr =
+                    cvmx_bootmem_alloc_named_range(sizeof(*__cvmx_cmd_queue_state_ptr),
+                                                   octeon_reserve32_memory,
+                                                   octeon_reserve32_memory +
+                                                   (CONFIG_CAVIUM_RESERVE32 <<
+                                                    20) - 1, 128, alloc_name);
+        else
+#endif
+                __cvmx_cmd_queue_state_ptr =
+                    cvmx_bootmem_alloc_named(sizeof(*__cvmx_cmd_queue_state_ptr),
+                                            128,
+                                            alloc_name);
+        if (__cvmx_cmd_queue_state_ptr)
+                memset(__cvmx_cmd_queue_state_ptr, 0,
+                       sizeof(*__cvmx_cmd_queue_state_ptr));
+        else {
+                struct cvmx_bootmem_named_block_desc *block_desc =
+                    cvmx_bootmem_find_named_block(alloc_name);
+                if (block_desc)
+                        __cvmx_cmd_queue_state_ptr =
+                            cvmx_phys_to_ptr(block_desc->base_addr);
+                else {
+                        cvmx_dprintf
+                            ("ERROR: cvmx_cmd_queue_initialize: Unable to get named block %s.\n",
+                             alloc_name);
+                        return CVMX_CMD_QUEUE_NO_MEMORY;
+                }
+        }
+        return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+/**
+ * Initialize a command queue for use. The initial FPA buffer is
+ * allocated and the hardware unit is configured to point to the
+ * new command queue.
+ *
+ * @queue_id:  Hardware command queue to initialize.
+ * @max_depth: Maximum outstanding commands that can be queued.
+ * @fpa_pool:  FPA pool the command queues should come from.
+ * @pool_size: Size of each buffer in the FPA pool (bytes)
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
+                                                  int max_depth, int fpa_pool,
+                                                  int pool_size)
+{
+        __cvmx_cmd_queue_state_t *qstate;
+        cvmx_cmd_queue_result_t result = __cvmx_cmd_queue_init_state_ptr();
+        if (result != CVMX_CMD_QUEUE_SUCCESS)
+                return result;
+
+        qstate = __cvmx_cmd_queue_get_state(queue_id);
+        if (qstate == NULL)
+                return CVMX_CMD_QUEUE_INVALID_PARAM;
+
+        /*
+         * We artificially limit max_depth to 1<<20 words. It is an
+         * arbitrary limit.
+         */
+        if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH) {
+                if ((max_depth < 0) || (max_depth > 1 << 20))
+                        return CVMX_CMD_QUEUE_INVALID_PARAM;
+        } else if (max_depth != 0)
+                return CVMX_CMD_QUEUE_INVALID_PARAM;
+
+        if ((fpa_pool < 0) || (fpa_pool > 7))
+                return CVMX_CMD_QUEUE_INVALID_PARAM;
+        if ((pool_size < 128) || (pool_size > 65536))
+                return CVMX_CMD_QUEUE_INVALID_PARAM;
+
+        /* See if someone else has already initialized the queue */
+        if (qstate->base_ptr_div128) {
+                if (max_depth != (int)qstate->max_depth) {
+                        cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
+                                "Queue already initalized with different "
+                                "max_depth (%d).\n",
+                             (int)qstate->max_depth);
+                        return CVMX_CMD_QUEUE_INVALID_PARAM;
+                }
+                if (fpa_pool != qstate->fpa_pool) {
+                        cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
+                                "Queue already initalized with different "
+                                "FPA pool (%u).\n",
+                             qstate->fpa_pool);
+                        return CVMX_CMD_QUEUE_INVALID_PARAM;
+                }
+                if ((pool_size >> 3) - 1 != qstate->pool_size_m1) {
+                        cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
+                                "Queue already initalized with different "
+                                "FPA pool size (%u).\n",
+                             (qstate->pool_size_m1 + 1) << 3);
+                        return CVMX_CMD_QUEUE_INVALID_PARAM;
+                }
+                CVMX_SYNCWS;
+                return CVMX_CMD_QUEUE_ALREADY_SETUP;
+        } else {
+                union cvmx_fpa_ctl_status status;
+                void *buffer;
+
+                status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
+                if (!status.s.enb) {
+                        cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
+                                     "FPA is not enabled.\n");
+                        return CVMX_CMD_QUEUE_NO_MEMORY;
+                }
+                buffer = cvmx_fpa_alloc(fpa_pool);
+                if (buffer == NULL) {
+                        cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: "
+                                     "Unable to allocate initial buffer.\n");
+                        return CVMX_CMD_QUEUE_NO_MEMORY;
+                }
+
+                memset(qstate, 0, sizeof(*qstate));
+                qstate->max_depth = max_depth;
+                qstate->fpa_pool = fpa_pool;
+                qstate->pool_size_m1 = (pool_size >> 3) - 1;
+                qstate->base_ptr_div128 = cvmx_ptr_to_phys(buffer) / 128;
+                /*
+                 * We zeroed the now serving field so we need to also
+                 * zero the ticket.
+                 */
+                __cvmx_cmd_queue_state_ptr->
+                    ticket[__cvmx_cmd_queue_get_index(queue_id)] = 0;
+                CVMX_SYNCWS;
+                return CVMX_CMD_QUEUE_SUCCESS;
+        }
+}
+
+/**
+ * Shutdown a queue a free it's command buffers to the FPA. The
+ * hardware connected to the queue must be stopped before this
+ * function is called.
+ *
+ * @queue_id: Queue to shutdown
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id)
+{
+        __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+        if (qptr == NULL) {
+                cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Unable to "
+                             "get queue information.\n");
+                return CVMX_CMD_QUEUE_INVALID_PARAM;
+        }
+
+        if (cvmx_cmd_queue_length(queue_id) > 0) {
+                cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Queue still "
+                             "has data in it.\n");
+                return CVMX_CMD_QUEUE_FULL;
+        }
+
+        __cvmx_cmd_queue_lock(queue_id, qptr);
+        if (qptr->base_ptr_div128) {
+                cvmx_fpa_free(cvmx_phys_to_ptr
+                              ((uint64_t) qptr->base_ptr_div128 << 7),
+                              qptr->fpa_pool, 0);
+                qptr->base_ptr_div128 = 0;
+        }
+        __cvmx_cmd_queue_unlock(qptr);
+
+        return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+/**
+ * Return the number of command words pending in the queue. This
+ * function may be relatively slow for some hardware units.
+ *
+ * @queue_id: Hardware command queue to query
+ *
+ * Returns Number of outstanding commands
+ */
+int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id)
+{
+        if (CVMX_ENABLE_PARAMETER_CHECKING) {
+                if (__cvmx_cmd_queue_get_state(queue_id) == NULL)
+                        return CVMX_CMD_QUEUE_INVALID_PARAM;
+        }
+
+        /*
+         * The cast is here so gcc with check that all values in the
+         * cvmx_cmd_queue_id_t enumeration are here.
+         */
+        switch ((cvmx_cmd_queue_id_t) (queue_id & 0xff0000)) {
+        case CVMX_CMD_QUEUE_PKO_BASE:
+                /*
+                 * FIXME: Need atomic lock on
+                 * CVMX_PKO_REG_READ_IDX. Right now we are normally
+                 * called with the queue lock, so that is a SLIGHT
+                 * amount of protection.
+                 */
+                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue_id & 0xffff);
+                if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+                        union cvmx_pko_mem_debug9 debug9;
+                        debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
+                        return debug9.cn38xx.doorbell;
+                } else {
+                        union cvmx_pko_mem_debug8 debug8;
+                        debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
+                        return debug8.cn58xx.doorbell;
+                }
+        case CVMX_CMD_QUEUE_ZIP:
+        case CVMX_CMD_QUEUE_DFA:
+        case CVMX_CMD_QUEUE_RAID:
+                /* FIXME: Implement other lengths */
+                return 0;
+        case CVMX_CMD_QUEUE_DMA_BASE:
+                {
+                        union cvmx_npei_dmax_counts dmax_counts;
+                        dmax_counts.u64 =
+                            cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS
+                                          (queue_id & 0x7));
+                        return dmax_counts.s.dbell;
+                }
+        case CVMX_CMD_QUEUE_END:
+                return CVMX_CMD_QUEUE_INVALID_PARAM;
+        }
+        return CVMX_CMD_QUEUE_INVALID_PARAM;
+}
+
+/**
+ * Return the command buffer to be written to. The purpose of this
+ * function is to allow CVMX routine access t othe low level buffer
+ * for initial hardware setup. User applications should not call this
+ * function directly.
+ *
+ * @queue_id: Command queue to query
+ *
+ * Returns Command buffer or NULL on failure
+ */
+void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id)
+{
+        __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+        if (qptr && qptr->base_ptr_div128)
+                return cvmx_phys_to_ptr((uint64_t) qptr->base_ptr_div128 << 7);
+        else
+                return NULL;
+}
diff --git a/drivers/staging/octeon/cvmx-cmd-queue.h b/drivers/staging/octeon/cvmx-cmd-queue.h
new file mode 100644
index 000000000000..f0cb20ffa39a
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-cmd-queue.h
@@ -0,0 +1,617 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * Support functions for managing command queues used for
+ * various hardware blocks.
+ *
+ * The common command queue infrastructure abstracts out the
+ * software necessary for adding to Octeon's chained queue
+ * structures. These structures are used for commands to the
+ * PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each
+ * hardware unit takes commands and CSRs of different types,
+ * they all use basic linked command buffers to store the
+ * pending request. In general, users of the CVMX API don't
+ * call cvmx-cmd-queue functions directly. Instead the hardware
+ * unit specific wrapper should be used. The wrappers perform
+ * unit specific validation and CSR writes to submit the
+ * commands.
+ *
+ * Even though most software will never directly interact with
+ * cvmx-cmd-queue, knowledge of its internal working can help
+ * in diagnosing performance problems and help with debugging.
+ *
+ * Command queue pointers are stored in a global named block
+ * called "cvmx_cmd_queues". Except for the PKO queues, each
+ * hardware queue is stored in its own cache line to reduce SMP
+ * contention on spin locks. The PKO queues are stored such that
+ * every 16th queue is next to each other in memory. This scheme
+ * allows for queues being in separate cache lines when there
+ * are low number of queues per port. With 16 queues per port,
+ * the first queue for each port is in the same cache area. The
+ * second queues for each port are in another area, etc. This
+ * allows software to implement very efficient lockless PKO with
+ * 16 queues per port using a minimum of cache lines per core.
+ * All queues for a given core will be isolated in the same
+ * cache area.
+ *
+ * In addition to the memory pointer layout, cvmx-cmd-queue
+ * provides an optimized fair ll/sc locking mechanism for the
+ * queues. The lock uses a "ticket / now serving" model to
+ * maintain fair order on contended locks. In addition, it uses
+ * predicted locking time to limit cache contention. When a core
+ * know it must wait in line for a lock, it spins on the
+ * internal cycle counter to completely eliminate any causes of
+ * bus traffic.
+ *
+ */
+
+#ifndef __CVMX_CMD_QUEUE_H__
+#define __CVMX_CMD_QUEUE_H__
+
+#include <linux/prefetch.h>
+
+#include "cvmx-fpa.h"
+/**
+ * By default we disable the max depth support. Most programs
+ * don't use it and it slows down the command queue processing
+ * significantly.
+ */
+#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH
+#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0
+#endif
+
+/**
+ * Enumeration representing all hardware blocks that use command
+ * queues. Each hardware block has up to 65536 sub identifiers for
+ * multiple command queues. Not all chips support all hardware
+ * units.
+ */
+typedef enum {
+        CVMX_CMD_QUEUE_PKO_BASE = 0x00000,
+
+#define CVMX_CMD_QUEUE_PKO(queue) \
+        ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue))))
+
+        CVMX_CMD_QUEUE_ZIP = 0x10000,
+        CVMX_CMD_QUEUE_DFA = 0x20000,
+        CVMX_CMD_QUEUE_RAID = 0x30000,
+        CVMX_CMD_QUEUE_DMA_BASE = 0x40000,
+
+#define CVMX_CMD_QUEUE_DMA(queue) \
+        ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff&(queue))))
+
+        CVMX_CMD_QUEUE_END = 0x50000,
+} cvmx_cmd_queue_id_t;
+
+/**
+ * Command write operations can fail if the comamnd queue needs
+ * a new buffer and the associated FPA pool is empty. It can also
+ * fail if the number of queued command words reaches the maximum
+ * set at initialization.
+ */
+typedef enum {
+        CVMX_CMD_QUEUE_SUCCESS = 0,
+        CVMX_CMD_QUEUE_NO_MEMORY = -1,
+        CVMX_CMD_QUEUE_FULL = -2,
+        CVMX_CMD_QUEUE_INVALID_PARAM = -3,
+        CVMX_CMD_QUEUE_ALREADY_SETUP = -4,
+} cvmx_cmd_queue_result_t;
+
+typedef struct {
+        /* You have lock when this is your ticket */
+        uint8_t now_serving;
+        uint64_t unused1:24;
+        /* Maximum outstanding command words */
+        uint32_t max_depth;
+        /* FPA pool buffers come from */
+        uint64_t fpa_pool:3;
+        /* Top of command buffer pointer shifted 7 */
+        uint64_t base_ptr_div128:29;
+        uint64_t unused2:6;
+        /* FPA buffer size in 64bit words minus 1 */
+        uint64_t pool_size_m1:13;
+        /* Number of comamnds already used in buffer */
+        uint64_t index:13;
+} __cvmx_cmd_queue_state_t;
+
+/**
+ * This structure contains the global state of all comamnd queues.
+ * It is stored in a bootmem named block and shared by all
+ * applications running on Octeon. Tickets are stored in a differnet
+ * cahce line that queue information to reduce the contention on the
+ * ll/sc used to get a ticket. If this is not the case, the update
+ * of queue state causes the ll/sc to fail quite often.
+ */
+typedef struct {
+        uint64_t ticket[(CVMX_CMD_QUEUE_END >> 16) * 256];
+        __cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END >> 16) * 256];
+} __cvmx_cmd_queue_all_state_t;
+
+/**
+ * Initialize a command queue for use. The initial FPA buffer is
+ * allocated and the hardware unit is configured to point to the
+ * new command queue.
+ *
+ * @queue_id:  Hardware command queue to initialize.
+ * @max_depth: Maximum outstanding commands that can be queued.
+ * @fpa_pool:  FPA pool the command queues should come from.
+ * @pool_size: Size of each buffer in the FPA pool (bytes)
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id,
+                                                  int max_depth, int fpa_pool,
+                                                  int pool_size);
+
+/**
+ * Shutdown a queue a free it's command buffers to the FPA. The
+ * hardware connected to the queue must be stopped before this
+ * function is called.
+ *
+ * @queue_id: Queue to shutdown
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id);
+
+/**
+ * Return the number of command words pending in the queue. This
+ * function may be relatively slow for some hardware units.
+ *
+ * @queue_id: Hardware command queue to query
+ *
+ * Returns Number of outstanding commands
+ */
+int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id);
+
+/**
+ * Return the command buffer to be written to. The purpose of this
+ * function is to allow CVMX routine access t othe low level buffer
+ * for initial hardware setup. User applications should not call this
+ * function directly.
+ *
+ * @queue_id: Command queue to query
+ *
+ * Returns Command buffer or NULL on failure
+ */
+void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id);
+
+/**
+ * Get the index into the state arrays for the supplied queue id.
+ *
+ * @queue_id: Queue ID to get an index for
+ *
+ * Returns Index into the state arrays
+ */
+static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id)
+{
+        /*
+         * Warning: This code currently only works with devices that
+         * have 256 queues or less. Devices with more than 16 queues
+         * are layed out in memory to allow cores quick access to
+         * every 16th queue. This reduces cache thrashing when you are
+         * running 16 queues per port to support lockless operation.
+         */
+        int unit = queue_id >> 16;
+        int q = (queue_id >> 4) & 0xf;
+        int core = queue_id & 0xf;
+        return unit * 256 + core * 16 + q;
+}
+
+/**
+ * Lock the supplied queue so nobody else is updating it at the same
+ * time as us.
+ *
+ * @queue_id: Queue ID to lock
+ * @qptr:     Pointer to the queue's global state
+ */
+static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id,
+                                         __cvmx_cmd_queue_state_t *qptr)
+{
+        extern __cvmx_cmd_queue_all_state_t
+            *__cvmx_cmd_queue_state_ptr;
+        int tmp;
+        int my_ticket;
+        prefetch(qptr);
+        asm volatile (
+                ".set push\n"
+                ".set noreorder\n"
+                "1:\n"
+                /* Atomic add one to ticket_ptr */
+                "ll     %[my_ticket], %[ticket_ptr]\n"
+                /* and store the original value */
+                "li     %[ticket], 1\n"
+                /* in my_ticket */
+                "baddu  %[ticket], %[my_ticket]\n"
+                "sc     %[ticket], %[ticket_ptr]\n"
+                "beqz   %[ticket], 1b\n"
+                " nop\n"
+                /* Load the current now_serving ticket */
+                "lbu    %[ticket], %[now_serving]\n"
+                "2:\n"
+                /* Jump out if now_serving == my_ticket */
+                "beq    %[ticket], %[my_ticket], 4f\n"
+                /* Find out how many tickets are in front of me */
+                " subu   %[ticket], %[my_ticket], %[ticket]\n"
+                /* Use tickets in front of me minus one to delay */
+                "subu  %[ticket], 1\n"
+                /* Delay will be ((tickets in front)-1)*32 loops */
+                "cins   %[ticket], %[ticket], 5, 7\n"
+                "3:\n"
+                /* Loop here until our ticket might be up */
+                "bnez   %[ticket], 3b\n"
+                " subu  %[ticket], 1\n"
+                /* Jump back up to check out ticket again */
+                "b      2b\n"
+                /* Load the current now_serving ticket */
+                " lbu   %[ticket], %[now_serving]\n"
+                "4:\n"
+                ".set pop\n" :
+                [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
+                [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp),
+                [my_ticket] "=r"(my_ticket)
+            );
+}
+
+/**
+ * Unlock the queue, flushing all writes.
+ *
+ * @qptr:   Queue to unlock
+ */
+static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr)
+{
+        qptr->now_serving++;
+        CVMX_SYNCWS;
+}
+
+/**
+ * Get the queue state structure for the given queue id
+ *
+ * @queue_id: Queue id to get
+ *
+ * Returns Queue structure or NULL on failure
+ */
+static inline __cvmx_cmd_queue_state_t
+    *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id)
+{
+        extern __cvmx_cmd_queue_all_state_t
+            *__cvmx_cmd_queue_state_ptr;
+        return &__cvmx_cmd_queue_state_ptr->
+            state[__cvmx_cmd_queue_get_index(queue_id)];
+}
+
+/**
+ * Write an arbitrary number of command words to a command queue.
+ * This is a generic function; the fixed number of comamnd word
+ * functions yield higher performance.
+ *
+ * @queue_id:  Hardware command queue to write to
+ * @use_locking:
+ *                  Use internal locking to ensure exclusive access for queue
+ *                  updates. If you don't use this locking you must ensure
+ *                  exclusivity some other way. Locking is strongly recommended.
+ * @cmd_count: Number of command words to write
+ * @cmds:      Array of comamnds to write
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t
+                                                           queue_id,
+                                                           int use_locking,
+                                                           int cmd_count,
+                                                           uint64_t *cmds)
+{
+        __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+
+        /* Make sure nobody else is updating the same queue */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_lock(queue_id, qptr);
+
+        /*
+         * If a max queue length was specified then make sure we don't
+         * exceed it. If any part of the command would be below the
+         * limit we allow it.
+         */
+        if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
+                if (unlikely
+                    (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_FULL;
+                }
+        }
+
+        /*
+         * Normally there is plenty of room in the current buffer for
+         * the command.
+         */
+        if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) {
+                uint64_t *ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                ptr += qptr->index;
+                qptr->index += cmd_count;
+                while (cmd_count--)
+                        *ptr++ = *cmds++;
+        } else {
+                uint64_t *ptr;
+                int count;
+                /*
+                 * We need a new comamnd buffer. Fail if there isn't
+                 * one available.
+                 */
+                uint64_t *new_buffer =
+                    (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
+                if (unlikely(new_buffer == NULL)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_NO_MEMORY;
+                }
+                ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                /*
+                 * Figure out how many command words will fit in this
+                 * buffer. One location will be needed for the next
+                 * buffer pointer.
+                 */
+                count = qptr->pool_size_m1 - qptr->index;
+                ptr += qptr->index;
+                cmd_count -= count;
+                while (count--)
+                        *ptr++ = *cmds++;
+                *ptr = cvmx_ptr_to_phys(new_buffer);
+                /*
+                 * The current buffer is full and has a link to the
+                 * next buffer. Time to write the rest of the commands
+                 * into the new buffer.
+                 */
+                qptr->base_ptr_div128 = *ptr >> 7;
+                qptr->index = cmd_count;
+                ptr = new_buffer;
+                while (cmd_count--)
+                        *ptr++ = *cmds++;
+        }
+
+        /* All updates are complete. Release the lock and return */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+        return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+/**
+ * Simple function to write two command words to a command
+ * queue.
+ *
+ * @queue_id: Hardware command queue to write to
+ * @use_locking:
+ *                 Use internal locking to ensure exclusive access for queue
+ *                 updates. If you don't use this locking you must ensure
+ *                 exclusivity some other way. Locking is strongly recommended.
+ * @cmd1:     Command
+ * @cmd2:     Command
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t
+                                                            queue_id,
+                                                            int use_locking,
+                                                            uint64_t cmd1,
+                                                            uint64_t cmd2)
+{
+        __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+
+        /* Make sure nobody else is updating the same queue */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_lock(queue_id, qptr);
+
+        /*
+         * If a max queue length was specified then make sure we don't
+         * exceed it. If any part of the command would be below the
+         * limit we allow it.
+         */
+        if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
+                if (unlikely
+                    (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_FULL;
+                }
+        }
+
+        /*
+         * Normally there is plenty of room in the current buffer for
+         * the command.
+         */
+        if (likely(qptr->index + 2 < qptr->pool_size_m1)) {
+                uint64_t *ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                ptr += qptr->index;
+                qptr->index += 2;
+                ptr[0] = cmd1;
+                ptr[1] = cmd2;
+        } else {
+                uint64_t *ptr;
+                /*
+                 * Figure out how many command words will fit in this
+                 * buffer. One location will be needed for the next
+                 * buffer pointer.
+                 */
+                int count = qptr->pool_size_m1 - qptr->index;
+                /*
+                 * We need a new comamnd buffer. Fail if there isn't
+                 * one available.
+                 */
+                uint64_t *new_buffer =
+                    (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
+                if (unlikely(new_buffer == NULL)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_NO_MEMORY;
+                }
+                count--;
+                ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                ptr += qptr->index;
+                *ptr++ = cmd1;
+                if (likely(count))
+                        *ptr++ = cmd2;
+                *ptr = cvmx_ptr_to_phys(new_buffer);
+                /*
+                 * The current buffer is full and has a link to the
+                 * next buffer. Time to write the rest of the commands
+                 * into the new buffer.
+                 */
+                qptr->base_ptr_div128 = *ptr >> 7;
+                qptr->index = 0;
+                if (unlikely(count == 0)) {
+                        qptr->index = 1;
+                        new_buffer[0] = cmd2;
+                }
+        }
+
+        /* All updates are complete. Release the lock and return */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+        return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+/**
+ * Simple function to write three command words to a command
+ * queue.
+ *
+ * @queue_id: Hardware command queue to write to
+ * @use_locking:
+ *                 Use internal locking to ensure exclusive access for queue
+ *                 updates. If you don't use this locking you must ensure
+ *                 exclusivity some other way. Locking is strongly recommended.
+ * @cmd1:     Command
+ * @cmd2:     Command
+ * @cmd3:     Command
+ *
+ * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code
+ */
+static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t
+                                                            queue_id,
+                                                            int use_locking,
+                                                            uint64_t cmd1,
+                                                            uint64_t cmd2,
+                                                            uint64_t cmd3)
+{
+        __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id);
+
+        /* Make sure nobody else is updating the same queue */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_lock(queue_id, qptr);
+
+        /*
+         * If a max queue length was specified then make sure we don't
+         * exceed it. If any part of the command would be below the
+         * limit we allow it.
+         */
+        if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) {
+                if (unlikely
+                    (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_FULL;
+                }
+        }
+
+        /*
+         * Normally there is plenty of room in the current buffer for
+         * the command.
+         */
+        if (likely(qptr->index + 3 < qptr->pool_size_m1)) {
+                uint64_t *ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                ptr += qptr->index;
+                qptr->index += 3;
+                ptr[0] = cmd1;
+                ptr[1] = cmd2;
+                ptr[2] = cmd3;
+        } else {
+                uint64_t *ptr;
+                /*
+                 * Figure out how many command words will fit in this
+                 * buffer. One location will be needed for the next
+                 * buffer pointer
+                 */
+                int count = qptr->pool_size_m1 - qptr->index;
+                /*
+                 * We need a new comamnd buffer. Fail if there isn't
+                 * one available
+                 */
+                uint64_t *new_buffer =
+                    (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool);
+                if (unlikely(new_buffer == NULL)) {
+                        if (likely(use_locking))
+                                __cvmx_cmd_queue_unlock(qptr);
+                        return CVMX_CMD_QUEUE_NO_MEMORY;
+                }
+                count--;
+                ptr =
+                    (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr->
+                                                  base_ptr_div128 << 7);
+                ptr += qptr->index;
+                *ptr++ = cmd1;
+                if (count) {
+                        *ptr++ = cmd2;
+                        if (count > 1)
+                                *ptr++ = cmd3;
+                }
+                *ptr = cvmx_ptr_to_phys(new_buffer);
+                /*
+                 * The current buffer is full and has a link to the
+                 * next buffer. Time to write the rest of the commands
+                 * into the new buffer.
+                 */
+                qptr->base_ptr_div128 = *ptr >> 7;
+                qptr->index = 0;
+                ptr = new_buffer;
+                if (count == 0) {
+                        *ptr++ = cmd2;
+                        qptr->index++;
+                }
+                if (count < 2) {
+                        *ptr++ = cmd3;
+                        qptr->index++;
+                }
+        }
+
+        /* All updates are complete. Release the lock and return */
+        if (likely(use_locking))
+                __cvmx_cmd_queue_unlock(qptr);
+        return CVMX_CMD_QUEUE_SUCCESS;
+}
+
+#endif /* __CVMX_CMD_QUEUE_H__ */
diff --git a/drivers/staging/octeon/cvmx-config.h b/drivers/staging/octeon/cvmx-config.h
new file mode 100644
index 000000000000..078a520481cf
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-config.h
@@ -0,0 +1,169 @@
+#ifndef __CVMX_CONFIG_H__
+#define __CVMX_CONFIG_H__
+
+/************************* Config Specific Defines ************************/
+#define CVMX_LLM_NUM_PORTS 1
+#define CVMX_NULL_POINTER_PROTECT 1
+#define CVMX_ENABLE_DEBUG_PRINTS 1
+/* PKO queues per port for interface 0 (ports 0-15) */
+#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
+/* PKO queues per port for interface 1 (ports 16-31) */
+#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
+/* Limit on the number of PKO ports enabled for interface 0 */
+#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
+/* Limit on the number of PKO ports enabled for interface 1 */
+#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
+/* PKO queues per port for PCI (ports 32-35) */
+#define CVMX_PKO_QUEUES_PER_PORT_PCI 1
+/* PKO queues per port for Loop devices (ports 36-39) */
+#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1
+
+/************************* FPA allocation *********************************/
+/* Pool sizes in bytes, must be multiple of a cache line */
+#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)
+
+/* Pools in use */
+/* Packet buffers */
+#define CVMX_FPA_PACKET_POOL                (0)
+#define CVMX_FPA_PACKET_POOL_SIZE           CVMX_FPA_POOL_0_SIZE
+/* Work queue entrys */
+#define CVMX_FPA_WQE_POOL                   (1)
+#define CVMX_FPA_WQE_POOL_SIZE              CVMX_FPA_POOL_1_SIZE
+/* PKO queue command buffers */
+#define CVMX_FPA_OUTPUT_BUFFER_POOL         (2)
+#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE    CVMX_FPA_POOL_2_SIZE
+
+/*************************  FAU allocation ********************************/
+/* The fetch and add registers are allocated here.  They are arranged
+ * in order of descending size so that all alignment constraints are
+ * automatically met.  The enums are linked so that the following enum
+ * continues allocating where the previous one left off, so the
+ * numbering within each enum always starts with zero.  The macros
+ * take care of the address increment size, so the values entered
+ * always increase by 1.  FAU registers are accessed with byte
+ * addresses.
+ */
+
+#define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START)
+typedef enum {
+        CVMX_FAU_REG_64_START   = 0,
+        CVMX_FAU_REG_64_END     = CVMX_FAU_REG_64_ADDR(0),
+} cvmx_fau_reg_64_t;
+
+#define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START)
+typedef enum {
+        CVMX_FAU_REG_32_START   = CVMX_FAU_REG_64_END,
+        CVMX_FAU_REG_32_END     = CVMX_FAU_REG_32_ADDR(0),
+} cvmx_fau_reg_32_t;
+
+#define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START)
+typedef enum {
+        CVMX_FAU_REG_16_START   = CVMX_FAU_REG_32_END,
+        CVMX_FAU_REG_16_END     = CVMX_FAU_REG_16_ADDR(0),
+} cvmx_fau_reg_16_t;
+
+#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START)
+typedef enum {
+        CVMX_FAU_REG_8_START    = CVMX_FAU_REG_16_END,
+        CVMX_FAU_REG_8_END      = CVMX_FAU_REG_8_ADDR(0),
+} cvmx_fau_reg_8_t;
+
+/*
+ * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first
+ * available FAU address that is not allocated in cvmx-config.h. This
+ * is 64 bit aligned.
+ */
+#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL))
+#define CVMX_FAU_REG_END (2048)
+
+/********************** scratch memory allocation *************************/
+/* Scratchpad memory allocation.  Note that these are byte memory
+ * addresses.  Some uses of scratchpad (IOBDMA for example) require
+ * the use of 8-byte aligned addresses, so proper alignment needs to
+ * be taken into account.
+ */
+/* Generic scratch iobdma area */
+#define CVMX_SCR_SCRATCH               (0)
+/* First location available after cvmx-config.h allocated region. */
+#define CVMX_SCR_REG_AVAIL_BASE        (8)
+
+/*
+ * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve
+ * before the beginning of the packet. If necessary, override the
+ * default here.  See the IPD section of the hardware manual for MBUFF
+ * SKIP details.
+ */
+#define CVMX_HELPER_FIRST_MBUFF_SKIP 184
+
+/*
+ * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve
+ * in each chained packet element. If necessary, override the default
+ * here.
+ */
+#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0
+
+/*
+ * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is
+ * enabled for all input ports. This controls if IPD sends
+ * backpressure to all ports if Octeon's FPA pools don't have enough
+ * packet or work queue entries. Even when this is off, it is still
+ * possible to get backpressure from individual hardware ports. When
+ * configuring backpressure, also check
+ * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override
+ * the default here.
+ */
+#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1
+
+/*
+ * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
+ * function. Once it is enabled the hardware starts accepting
+ * packets. You might want to skip the IPD enable if configuration
+ * changes are need from the default helper setup. If necessary,
+ * override the default here.
+ */
+#define CVMX_HELPER_ENABLE_IPD 0
+
+/*
+ * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
+ * to incoming packets.
+ */
+#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED
+
+#define CVMX_ENABLE_PARAMETER_CHECKING 0
+
+/*
+ * The following select which fields are used by the PIP to generate
+ * the tag on INPUT
+ * 0: don't include
+ * 1: include
+ */
+#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP       0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP       0
+#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT     0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT     0
+#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER  0
+#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP       0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP       0
+#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT     0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT     0
+#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL     0
+#define CVMX_HELPER_INPUT_TAG_INPUT_PORT        1
+
+/* Select skip mode for input ports */
+#define CVMX_HELPER_INPUT_PORT_SKIP_MODE        CVMX_PIP_PORT_CFG_MODE_SKIPL2
+
+/*
+ * Force backpressure to be disabled.  This overrides all other
+ * backpressure configuration.
+ */
+#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0
+
+#endif /* __CVMX_CONFIG_H__ */
+
diff --git a/drivers/staging/octeon/cvmx-dbg-defs.h b/drivers/staging/octeon/cvmx-dbg-defs.h
new file mode 100644
index 000000000000..abbf42d05e5a
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-dbg-defs.h
@@ -0,0 +1,72 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_DBG_DEFS_H__
+#define __CVMX_DBG_DEFS_H__
+
+#define CVMX_DBG_DATA \
+         CVMX_ADD_IO_SEG(0x00011F00000001E8ull)
+
+union cvmx_dbg_data {
+        uint64_t u64;
+        struct cvmx_dbg_data_s {
+                uint64_t reserved_23_63:41;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+        } s;
+        struct cvmx_dbg_data_cn30xx {
+                uint64_t reserved_31_63:33;
+                uint64_t pll_mul:3;
+                uint64_t reserved_23_27:5;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+        } cn30xx;
+        struct cvmx_dbg_data_cn30xx cn31xx;
+        struct cvmx_dbg_data_cn38xx {
+                uint64_t reserved_29_63:35;
+                uint64_t d_mul:4;
+                uint64_t dclk_mul2:1;
+                uint64_t cclk_div2:1;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+        } cn38xx;
+        struct cvmx_dbg_data_cn38xx cn38xxp2;
+        struct cvmx_dbg_data_cn30xx cn50xx;
+        struct cvmx_dbg_data_cn58xx {
+                uint64_t reserved_29_63:35;
+                uint64_t rem:6;
+                uint64_t c_mul:5;
+                uint64_t dsel_ext:1;
+                uint64_t data:17;
+        } cn58xx;
+        struct cvmx_dbg_data_cn58xx cn58xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-fau.h b/drivers/staging/octeon/cvmx-fau.h
new file mode 100644
index 000000000000..29bdce66cdf8
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-fau.h
@@ -0,0 +1,597 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Interface to the hardware Fetch and Add Unit.
+ */
+
+#ifndef __CVMX_FAU_H__
+#define __CVMX_FAU_H__
+
+/*
+ * Octeon Fetch and Add Unit (FAU)
+ */
+
+#define CVMX_FAU_LOAD_IO_ADDRESS    cvmx_build_io_address(0x1e, 0)
+#define CVMX_FAU_BITS_SCRADDR       63, 56
+#define CVMX_FAU_BITS_LEN           55, 48
+#define CVMX_FAU_BITS_INEVAL        35, 14
+#define CVMX_FAU_BITS_TAGWAIT       13, 13
+#define CVMX_FAU_BITS_NOADD         13, 13
+#define CVMX_FAU_BITS_SIZE          12, 11
+#define CVMX_FAU_BITS_REGISTER      10, 0
+
+typedef enum {
+        CVMX_FAU_OP_SIZE_8 = 0,
+        CVMX_FAU_OP_SIZE_16 = 1,
+        CVMX_FAU_OP_SIZE_32 = 2,
+        CVMX_FAU_OP_SIZE_64 = 3
+} cvmx_fau_op_size_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct {
+        uint64_t error:1;
+        int64_t value:63;
+} cvmx_fau_tagwait64_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct {
+        uint64_t error:1;
+        int32_t value:31;
+} cvmx_fau_tagwait32_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct {
+        uint64_t error:1;
+        int16_t value:15;
+} cvmx_fau_tagwait16_t;
+
+/**
+ * Tagwait return definition. If a timeout occurs, the error
+ * bit will be set. Otherwise the value of the register before
+ * the update will be returned.
+ */
+typedef struct {
+        uint64_t error:1;
+        int8_t value:7;
+} cvmx_fau_tagwait8_t;
+
+/**
+ * Asynchronous tagwait return definition. If a timeout occurs,
+ * the error bit will be set. Otherwise the value of the
+ * register before the update will be returned.
+ */
+typedef union {
+        uint64_t u64;
+        struct {
+                uint64_t invalid:1;
+                uint64_t data:63;       /* unpredictable if invalid is set */
+        } s;
+} cvmx_fau_async_tagwait_result_t;
+
+/**
+ * Builds a store I/O address for writing to the FAU
+ *
+ * @noadd:  0 = Store value is atomically added to the current value
+ *               1 = Store value is atomically written over the current value
+ * @reg:    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 2 for 16 bit access.
+ *               - Step by 4 for 32 bit access.
+ *               - Step by 8 for 64 bit access.
+ * Returns Address to store for atomic update
+ */
+static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
+{
+        return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
+               cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) |
+               cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
+}
+
+/**
+ * Builds a I/O address for accessing the FAU
+ *
+ * @tagwait: Should the atomic add wait for the current tag switch
+ *                operation to complete.
+ *                - 0 = Don't wait
+ *                - 1 = Wait for tag switch to complete
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ *                - Step by 4 for 32 bit access.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to add.
+ *                Note: When performing 32 and 64 bit access, only the low
+ *                22 bits are available.
+ * Returns Address to read from for atomic update
+ */
+static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg,
+                                                 int64_t value)
+{
+        return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) |
+               cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
+               cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
+               cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
+}
+
+/**
+ * Perform an atomic 64 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Value of the register before the update
+ */
+static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
+                                               int64_t value)
+{
+        return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+/**
+ * Perform an atomic 32 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Value of the register before the update
+ */
+static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
+                                               int32_t value)
+{
+        return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+/**
+ * Perform an atomic 16 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @value:   Signed value to add.
+ * Returns Value of the register before the update
+ */
+static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg,
+                                               int16_t value)
+{
+        return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+/**
+ * Perform an atomic 8 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ * @value:   Signed value to add.
+ * Returns Value of the register before the update
+ */
+static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+        return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value));
+}
+
+/**
+ * Perform an atomic 64 bit add after the current tag switch
+ * completes
+ *
+ * @reg:    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 8 for 64 bit access.
+ * @value:  Signed value to add.
+ *               Note: Only the low 22 bits are available.
+ * Returns If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait64_t
+cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
+{
+        union {
+                uint64_t i64;
+                cvmx_fau_tagwait64_t t;
+        } result;
+        result.i64 =
+            cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value));
+        return result.t;
+}
+
+/**
+ * Perform an atomic 32 bit add after the current tag switch
+ * completes
+ *
+ * @reg:    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 4 for 32 bit access.
+ * @value:  Signed value to add.
+ *               Note: Only the low 22 bits are available.
+ * Returns If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait32_t
+cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
+{
+        union {
+                uint64_t i32;
+                cvmx_fau_tagwait32_t t;
+        } result;
+        result.i32 =
+            cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value));
+        return result.t;
+}
+
+/**
+ * Perform an atomic 16 bit add after the current tag switch
+ * completes
+ *
+ * @reg:    FAU atomic register to access. 0 <= reg < 2048.
+ *               - Step by 2 for 16 bit access.
+ * @value:  Signed value to add.
+ * Returns If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait16_t
+cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
+{
+        union {
+                uint64_t i16;
+                cvmx_fau_tagwait16_t t;
+        } result;
+        result.i16 =
+            cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value));
+        return result.t;
+}
+
+/**
+ * Perform an atomic 8 bit add after the current tag switch
+ * completes
+ *
+ * @reg:    FAU atomic register to access. 0 <= reg < 2048.
+ * @value:  Signed value to add.
+ * Returns If a timeout occurs, the error bit will be set. Otherwise
+ *         the value of the register before the update will be
+ *         returned
+ */
+static inline cvmx_fau_tagwait8_t
+cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+        union {
+                uint64_t i8;
+                cvmx_fau_tagwait8_t t;
+        } result;
+        result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value));
+        return result.t;
+}
+
+/**
+ * Builds I/O data for async operations
+ *
+ * @scraddr: Scratch pad byte addres to write to.  Must be 8 byte aligned
+ * @value:   Signed value to add.
+ *                Note: When performing 32 and 64 bit access, only the low
+ *                22 bits are available.
+ * @tagwait: Should the atomic add wait for the current tag switch
+ *                operation to complete.
+ *                - 0 = Don't wait
+ *                - 1 = Wait for tag switch to complete
+ * @size:    The size of the operation:
+ *                - CVMX_FAU_OP_SIZE_8  (0) = 8 bits
+ *                - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
+ *                - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
+ *                - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ *                - Step by 4 for 32 bit access.
+ *                - Step by 8 for 64 bit access.
+ * Returns Data to write using cvmx_send_single
+ */
+static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value,
+                                              uint64_t tagwait,
+                                              cvmx_fau_op_size_t size,
+                                              uint64_t reg)
+{
+        return CVMX_FAU_LOAD_IO_ADDRESS |
+               cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) |
+               cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) |
+               cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) |
+               cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) |
+               cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) |
+               cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg);
+}
+
+/**
+ * Perform an async atomic 64 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @scraddr: Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr,
+                                                  cvmx_fau_reg_64_t reg,
+                                                  int64_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg));
+}
+
+/**
+ * Perform an async atomic 32 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @scraddr: Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
+                                                  cvmx_fau_reg_32_t reg,
+                                                  int32_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg));
+}
+
+/**
+ * Perform an async atomic 16 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @scraddr: Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @value:   Signed value to add.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr,
+                                                  cvmx_fau_reg_16_t reg,
+                                                  int16_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg));
+}
+
+/**
+ * Perform an async atomic 8 bit add. The old value is
+ * placed in the scratch memory at byte address scraddr.
+ *
+ * @scraddr: Scratch memory byte address to put response in.
+ *                Must be 8 byte aligned.
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ * @value:   Signed value to add.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr,
+                                                 cvmx_fau_reg_8_t reg,
+                                                 int8_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg));
+}
+
+/**
+ * Perform an async atomic 64 bit add after the current tag
+ * switch completes.
+ *
+ * @scraddr: Scratch memory byte address to put response in.  Must be
+ *           8 byte aligned.  If a timeout occurs, the error bit (63)
+ *           will be set. Otherwise the value of the register before
+ *           the update will be returned
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr,
+                                                          cvmx_fau_reg_64_t reg,
+                                                          int64_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg));
+}
+
+/**
+ * Perform an async atomic 32 bit add after the current tag
+ * switch completes.
+ *
+ * @scraddr: Scratch memory byte address to put response in.  Must be
+ *           8 byte aligned.  If a timeout occurs, the error bit (63)
+ *           will be set. Otherwise the value of the register before
+ *           the update will be returned
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @value:   Signed value to add.
+ *                Note: Only the low 22 bits are available.
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr,
+                                                          cvmx_fau_reg_32_t reg,
+                                                          int32_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg));
+}
+
+/**
+ * Perform an async atomic 16 bit add after the current tag
+ * switch completes.
+ *
+ * @scraddr: Scratch memory byte address to put response in.  Must be
+ *           8 byte aligned.  If a timeout occurs, the error bit (63)
+ *           will be set. Otherwise the value of the register before
+ *           the update will be returned
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @value:   Signed value to add.
+ *
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr,
+                                                          cvmx_fau_reg_16_t reg,
+                                                          int16_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg));
+}
+
+/**
+ * Perform an async atomic 8 bit add after the current tag
+ * switch completes.
+ *
+ * @scraddr: Scratch memory byte address to put response in.  Must be
+ *           8 byte aligned.  If a timeout occurs, the error bit (63)
+ *           will be set. Otherwise the value of the register before
+ *           the update will be returned
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ * @value:   Signed value to add.
+ *
+ * Returns Placed in the scratch pad register
+ */
+static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr,
+                                                         cvmx_fau_reg_8_t reg,
+                                                         int8_t value)
+{
+        cvmx_send_single(__cvmx_fau_iobdma_data
+                         (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg));
+}
+
+/**
+ * Perform an atomic 64 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
+{
+        cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value);
+}
+
+/**
+ * Perform an atomic 32 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @value:   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
+{
+        cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value);
+}
+
+/**
+ * Perform an atomic 16 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @value:   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
+{
+        cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value);
+}
+
+/**
+ * Perform an atomic 8 bit add
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ * @value:   Signed value to add.
+ */
+static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+        cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value);
+}
+
+/**
+ * Perform an atomic 64 bit write
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 8 for 64 bit access.
+ * @value:   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
+{
+        cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value);
+}
+
+/**
+ * Perform an atomic 32 bit write
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 4 for 32 bit access.
+ * @value:   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
+{
+        cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value);
+}
+
+/**
+ * Perform an atomic 16 bit write
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ *                - Step by 2 for 16 bit access.
+ * @value:   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
+{
+        cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value);
+}
+
+/**
+ * Perform an atomic 8 bit write
+ *
+ * @reg:     FAU atomic register to access. 0 <= reg < 2048.
+ * @value:   Signed value to write.
+ */
+static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value)
+{
+        cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value);
+}
+
+#endif /* __CVMX_FAU_H__ */
diff --git a/drivers/staging/octeon/cvmx-fpa-defs.h b/drivers/staging/octeon/cvmx-fpa-defs.h
new file mode 100644
index 000000000000..bf5546b90110
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-fpa-defs.h
@@ -0,0 +1,403 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_FPA_DEFS_H__
+#define __CVMX_FPA_DEFS_H__
+
+#define CVMX_FPA_BIST_STATUS \
+         CVMX_ADD_IO_SEG(0x00011800280000E8ull)
+#define CVMX_FPA_CTL_STATUS \
+         CVMX_ADD_IO_SEG(0x0001180028000050ull)
+#define CVMX_FPA_FPF0_MARKS \
+         CVMX_ADD_IO_SEG(0x0001180028000000ull)
+#define CVMX_FPA_FPF0_SIZE \
+         CVMX_ADD_IO_SEG(0x0001180028000058ull)
+#define CVMX_FPA_FPF1_MARKS \
+         CVMX_ADD_IO_SEG(0x0001180028000008ull)
+#define CVMX_FPA_FPF2_MARKS \
+         CVMX_ADD_IO_SEG(0x0001180028000010ull)
+#define CVMX_FPA_FPF3_MARKS \
+         CVMX_ADD_IO_SEG(0x0001180028000018ull)
+#define CVMX_FPA_FPF4_MARKS \
+         CVMX_ADD_IO_SEG(0x0001180028000020ull)
+#define CVMX_FPA_FPF5_MARKS \
+         CVMX_ADD_IO_SEG(0x0001180028000028ull)
+#define CVMX_FPA_FPF6_MARKS \
+         CVMX_ADD_IO_SEG(0x0001180028000030ull)
+#define CVMX_FPA_FPF7_MARKS \
+         CVMX_ADD_IO_SEG(0x0001180028000038ull)
+#define CVMX_FPA_FPFX_MARKS(offset) \
+         CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1)
+#define CVMX_FPA_FPFX_SIZE(offset) \
+         CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1)
+#define CVMX_FPA_INT_ENB \
+         CVMX_ADD_IO_SEG(0x0001180028000048ull)
+#define CVMX_FPA_INT_SUM \
+         CVMX_ADD_IO_SEG(0x0001180028000040ull)
+#define CVMX_FPA_QUE0_PAGE_INDEX \
+         CVMX_ADD_IO_SEG(0x00011800280000F0ull)
+#define CVMX_FPA_QUE1_PAGE_INDEX \
+         CVMX_ADD_IO_SEG(0x00011800280000F8ull)
+#define CVMX_FPA_QUE2_PAGE_INDEX \
+         CVMX_ADD_IO_SEG(0x0001180028000100ull)
+#define CVMX_FPA_QUE3_PAGE_INDEX \
+         CVMX_ADD_IO_SEG(0x0001180028000108ull)
+#define CVMX_FPA_QUE4_PAGE_INDEX \
+         CVMX_ADD_IO_SEG(0x0001180028000110ull)
+#define CVMX_FPA_QUE5_PAGE_INDEX \
+         CVMX_ADD_IO_SEG(0x0001180028000118ull)
+#define CVMX_FPA_QUE6_PAGE_INDEX \
+         CVMX_ADD_IO_SEG(0x0001180028000120ull)
+#define CVMX_FPA_QUE7_PAGE_INDEX \
+         CVMX_ADD_IO_SEG(0x0001180028000128ull)
+#define CVMX_FPA_QUEX_AVAILABLE(offset) \
+         CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8))
+#define CVMX_FPA_QUEX_PAGE_INDEX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8))
+#define CVMX_FPA_QUE_ACT \
+         CVMX_ADD_IO_SEG(0x0001180028000138ull)
+#define CVMX_FPA_QUE_EXP \
+         CVMX_ADD_IO_SEG(0x0001180028000130ull)
+#define CVMX_FPA_WART_CTL \
+         CVMX_ADD_IO_SEG(0x00011800280000D8ull)
+#define CVMX_FPA_WART_STATUS \
+         CVMX_ADD_IO_SEG(0x00011800280000E0ull)
+
+union cvmx_fpa_bist_status {
+        uint64_t u64;
+        struct cvmx_fpa_bist_status_s {
+                uint64_t reserved_5_63:59;
+                uint64_t frd:1;
+                uint64_t fpf0:1;
+                uint64_t fpf1:1;
+                uint64_t ffr:1;
+                uint64_t fdr:1;
+        } s;
+        struct cvmx_fpa_bist_status_s cn30xx;
+        struct cvmx_fpa_bist_status_s cn31xx;
+        struct cvmx_fpa_bist_status_s cn38xx;
+        struct cvmx_fpa_bist_status_s cn38xxp2;
+        struct cvmx_fpa_bist_status_s cn50xx;
+        struct cvmx_fpa_bist_status_s cn52xx;
+        struct cvmx_fpa_bist_status_s cn52xxp1;
+        struct cvmx_fpa_bist_status_s cn56xx;
+        struct cvmx_fpa_bist_status_s cn56xxp1;
+        struct cvmx_fpa_bist_status_s cn58xx;
+        struct cvmx_fpa_bist_status_s cn58xxp1;
+};
+
+union cvmx_fpa_ctl_status {
+        uint64_t u64;
+        struct cvmx_fpa_ctl_status_s {
+                uint64_t reserved_18_63:46;
+                uint64_t reset:1;
+                uint64_t use_ldt:1;
+                uint64_t use_stt:1;
+                uint64_t enb:1;
+                uint64_t mem1_err:7;
+                uint64_t mem0_err:7;
+        } s;
+        struct cvmx_fpa_ctl_status_s cn30xx;
+        struct cvmx_fpa_ctl_status_s cn31xx;
+        struct cvmx_fpa_ctl_status_s cn38xx;
+        struct cvmx_fpa_ctl_status_s cn38xxp2;
+        struct cvmx_fpa_ctl_status_s cn50xx;
+        struct cvmx_fpa_ctl_status_s cn52xx;
+        struct cvmx_fpa_ctl_status_s cn52xxp1;
+        struct cvmx_fpa_ctl_status_s cn56xx;
+        struct cvmx_fpa_ctl_status_s cn56xxp1;
+        struct cvmx_fpa_ctl_status_s cn58xx;
+        struct cvmx_fpa_ctl_status_s cn58xxp1;
+};
+
+union cvmx_fpa_fpfx_marks {
+        uint64_t u64;
+        struct cvmx_fpa_fpfx_marks_s {
+                uint64_t reserved_22_63:42;
+                uint64_t fpf_wr:11;
+                uint64_t fpf_rd:11;
+        } s;
+        struct cvmx_fpa_fpfx_marks_s cn38xx;
+        struct cvmx_fpa_fpfx_marks_s cn38xxp2;
+        struct cvmx_fpa_fpfx_marks_s cn56xx;
+        struct cvmx_fpa_fpfx_marks_s cn56xxp1;
+        struct cvmx_fpa_fpfx_marks_s cn58xx;
+        struct cvmx_fpa_fpfx_marks_s cn58xxp1;
+};
+
+union cvmx_fpa_fpfx_size {
+        uint64_t u64;
+        struct cvmx_fpa_fpfx_size_s {
+                uint64_t reserved_11_63:53;
+                uint64_t fpf_siz:11;
+        } s;
+        struct cvmx_fpa_fpfx_size_s cn38xx;
+        struct cvmx_fpa_fpfx_size_s cn38xxp2;
+        struct cvmx_fpa_fpfx_size_s cn56xx;
+        struct cvmx_fpa_fpfx_size_s cn56xxp1;
+        struct cvmx_fpa_fpfx_size_s cn58xx;
+        struct cvmx_fpa_fpfx_size_s cn58xxp1;
+};
+
+union cvmx_fpa_fpf0_marks {
+        uint64_t u64;
+        struct cvmx_fpa_fpf0_marks_s {
+                uint64_t reserved_24_63:40;
+                uint64_t fpf_wr:12;
+                uint64_t fpf_rd:12;
+        } s;
+        struct cvmx_fpa_fpf0_marks_s cn38xx;
+        struct cvmx_fpa_fpf0_marks_s cn38xxp2;
+        struct cvmx_fpa_fpf0_marks_s cn56xx;
+        struct cvmx_fpa_fpf0_marks_s cn56xxp1;
+        struct cvmx_fpa_fpf0_marks_s cn58xx;
+        struct cvmx_fpa_fpf0_marks_s cn58xxp1;
+};
+
+union cvmx_fpa_fpf0_size {
+        uint64_t u64;
+        struct cvmx_fpa_fpf0_size_s {
+                uint64_t reserved_12_63:52;
+                uint64_t fpf_siz:12;
+        } s;
+        struct cvmx_fpa_fpf0_size_s cn38xx;
+        struct cvmx_fpa_fpf0_size_s cn38xxp2;
+        struct cvmx_fpa_fpf0_size_s cn56xx;
+        struct cvmx_fpa_fpf0_size_s cn56xxp1;
+        struct cvmx_fpa_fpf0_size_s cn58xx;
+        struct cvmx_fpa_fpf0_size_s cn58xxp1;
+};
+
+union cvmx_fpa_int_enb {
+        uint64_t u64;
+        struct cvmx_fpa_int_enb_s {
+                uint64_t reserved_28_63:36;
+                uint64_t q7_perr:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_und:1;
+                uint64_t q6_perr:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_und:1;
+                uint64_t q5_perr:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_und:1;
+                uint64_t q4_perr:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_und:1;
+                uint64_t q3_perr:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_und:1;
+                uint64_t q2_perr:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_und:1;
+                uint64_t q1_perr:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_und:1;
+                uint64_t q0_perr:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_und:1;
+                uint64_t fed1_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed0_sbe:1;
+        } s;
+        struct cvmx_fpa_int_enb_s cn30xx;
+        struct cvmx_fpa_int_enb_s cn31xx;
+        struct cvmx_fpa_int_enb_s cn38xx;
+        struct cvmx_fpa_int_enb_s cn38xxp2;
+        struct cvmx_fpa_int_enb_s cn50xx;
+        struct cvmx_fpa_int_enb_s cn52xx;
+        struct cvmx_fpa_int_enb_s cn52xxp1;
+        struct cvmx_fpa_int_enb_s cn56xx;
+        struct cvmx_fpa_int_enb_s cn56xxp1;
+        struct cvmx_fpa_int_enb_s cn58xx;
+        struct cvmx_fpa_int_enb_s cn58xxp1;
+};
+
+union cvmx_fpa_int_sum {
+        uint64_t u64;
+        struct cvmx_fpa_int_sum_s {
+                uint64_t reserved_28_63:36;
+                uint64_t q7_perr:1;
+                uint64_t q7_coff:1;
+                uint64_t q7_und:1;
+                uint64_t q6_perr:1;
+                uint64_t q6_coff:1;
+                uint64_t q6_und:1;
+                uint64_t q5_perr:1;
+                uint64_t q5_coff:1;
+                uint64_t q5_und:1;
+                uint64_t q4_perr:1;
+                uint64_t q4_coff:1;
+                uint64_t q4_und:1;
+                uint64_t q3_perr:1;
+                uint64_t q3_coff:1;
+                uint64_t q3_und:1;
+                uint64_t q2_perr:1;
+                uint64_t q2_coff:1;
+                uint64_t q2_und:1;
+                uint64_t q1_perr:1;
+                uint64_t q1_coff:1;
+                uint64_t q1_und:1;
+                uint64_t q0_perr:1;
+                uint64_t q0_coff:1;
+                uint64_t q0_und:1;
+                uint64_t fed1_dbe:1;
+                uint64_t fed1_sbe:1;
+                uint64_t fed0_dbe:1;
+                uint64_t fed0_sbe:1;
+        } s;
+        struct cvmx_fpa_int_sum_s cn30xx;
+        struct cvmx_fpa_int_sum_s cn31xx;
+        struct cvmx_fpa_int_sum_s cn38xx;
+        struct cvmx_fpa_int_sum_s cn38xxp2;
+        struct cvmx_fpa_int_sum_s cn50xx;
+        struct cvmx_fpa_int_sum_s cn52xx;
+        struct cvmx_fpa_int_sum_s cn52xxp1;
+        struct cvmx_fpa_int_sum_s cn56xx;
+        struct cvmx_fpa_int_sum_s cn56xxp1;
+        struct cvmx_fpa_int_sum_s cn58xx;
+        struct cvmx_fpa_int_sum_s cn58xxp1;
+};
+
+union cvmx_fpa_quex_available {
+        uint64_t u64;
+        struct cvmx_fpa_quex_available_s {
+                uint64_t reserved_29_63:35;
+                uint64_t que_siz:29;
+        } s;
+        struct cvmx_fpa_quex_available_s cn30xx;
+        struct cvmx_fpa_quex_available_s cn31xx;
+        struct cvmx_fpa_quex_available_s cn38xx;
+        struct cvmx_fpa_quex_available_s cn38xxp2;
+        struct cvmx_fpa_quex_available_s cn50xx;
+        struct cvmx_fpa_quex_available_s cn52xx;
+        struct cvmx_fpa_quex_available_s cn52xxp1;
+        struct cvmx_fpa_quex_available_s cn56xx;
+        struct cvmx_fpa_quex_available_s cn56xxp1;
+        struct cvmx_fpa_quex_available_s cn58xx;
+        struct cvmx_fpa_quex_available_s cn58xxp1;
+};
+
+union cvmx_fpa_quex_page_index {
+        uint64_t u64;
+        struct cvmx_fpa_quex_page_index_s {
+                uint64_t reserved_25_63:39;
+                uint64_t pg_num:25;
+        } s;
+        struct cvmx_fpa_quex_page_index_s cn30xx;
+        struct cvmx_fpa_quex_page_index_s cn31xx;
+        struct cvmx_fpa_quex_page_index_s cn38xx;
+        struct cvmx_fpa_quex_page_index_s cn38xxp2;
+        struct cvmx_fpa_quex_page_index_s cn50xx;
+        struct cvmx_fpa_quex_page_index_s cn52xx;
+        struct cvmx_fpa_quex_page_index_s cn52xxp1;
+        struct cvmx_fpa_quex_page_index_s cn56xx;
+        struct cvmx_fpa_quex_page_index_s cn56xxp1;
+        struct cvmx_fpa_quex_page_index_s cn58xx;
+        struct cvmx_fpa_quex_page_index_s cn58xxp1;
+};
+
+union cvmx_fpa_que_act {
+        uint64_t u64;
+        struct cvmx_fpa_que_act_s {
+                uint64_t reserved_29_63:35;
+                uint64_t act_que:3;
+                uint64_t act_indx:26;
+        } s;
+        struct cvmx_fpa_que_act_s cn30xx;
+        struct cvmx_fpa_que_act_s cn31xx;
+        struct cvmx_fpa_que_act_s cn38xx;
+        struct cvmx_fpa_que_act_s cn38xxp2;
+        struct cvmx_fpa_que_act_s cn50xx;
+        struct cvmx_fpa_que_act_s cn52xx;
+        struct cvmx_fpa_que_act_s cn52xxp1;
+        struct cvmx_fpa_que_act_s cn56xx;
+        struct cvmx_fpa_que_act_s cn56xxp1;
+        struct cvmx_fpa_que_act_s cn58xx;
+        struct cvmx_fpa_que_act_s cn58xxp1;
+};
+
+union cvmx_fpa_que_exp {
+        uint64_t u64;
+        struct cvmx_fpa_que_exp_s {
+                uint64_t reserved_29_63:35;
+                uint64_t exp_que:3;
+                uint64_t exp_indx:26;
+        } s;
+        struct cvmx_fpa_que_exp_s cn30xx;
+        struct cvmx_fpa_que_exp_s cn31xx;
+        struct cvmx_fpa_que_exp_s cn38xx;
+        struct cvmx_fpa_que_exp_s cn38xxp2;
+        struct cvmx_fpa_que_exp_s cn50xx;
+        struct cvmx_fpa_que_exp_s cn52xx;
+        struct cvmx_fpa_que_exp_s cn52xxp1;
+        struct cvmx_fpa_que_exp_s cn56xx;
+        struct cvmx_fpa_que_exp_s cn56xxp1;
+        struct cvmx_fpa_que_exp_s cn58xx;
+        struct cvmx_fpa_que_exp_s cn58xxp1;
+};
+
+union cvmx_fpa_wart_ctl {
+        uint64_t u64;
+        struct cvmx_fpa_wart_ctl_s {
+                uint64_t reserved_16_63:48;
+                uint64_t ctl:16;
+        } s;
+        struct cvmx_fpa_wart_ctl_s cn30xx;
+        struct cvmx_fpa_wart_ctl_s cn31xx;
+        struct cvmx_fpa_wart_ctl_s cn38xx;
+        struct cvmx_fpa_wart_ctl_s cn38xxp2;
+        struct cvmx_fpa_wart_ctl_s cn50xx;
+        struct cvmx_fpa_wart_ctl_s cn52xx;
+        struct cvmx_fpa_wart_ctl_s cn52xxp1;
+        struct cvmx_fpa_wart_ctl_s cn56xx;
+        struct cvmx_fpa_wart_ctl_s cn56xxp1;
+        struct cvmx_fpa_wart_ctl_s cn58xx;
+        struct cvmx_fpa_wart_ctl_s cn58xxp1;
+};
+
+union cvmx_fpa_wart_status {
+        uint64_t u64;
+        struct cvmx_fpa_wart_status_s {
+                uint64_t reserved_32_63:32;
+                uint64_t status:32;
+        } s;
+        struct cvmx_fpa_wart_status_s cn30xx;
+        struct cvmx_fpa_wart_status_s cn31xx;
+        struct cvmx_fpa_wart_status_s cn38xx;
+        struct cvmx_fpa_wart_status_s cn38xxp2;
+        struct cvmx_fpa_wart_status_s cn50xx;
+        struct cvmx_fpa_wart_status_s cn52xx;
+        struct cvmx_fpa_wart_status_s cn52xxp1;
+        struct cvmx_fpa_wart_status_s cn56xx;
+        struct cvmx_fpa_wart_status_s cn56xxp1;
+        struct cvmx_fpa_wart_status_s cn58xx;
+        struct cvmx_fpa_wart_status_s cn58xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-fpa.c b/drivers/staging/octeon/cvmx-fpa.c
new file mode 100644
index 000000000000..55d9147acc85
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-fpa.c
@@ -0,0 +1,183 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Support library for the hardware Free Pool Allocator.
+ *
+ *
+ */
+
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-fpa.h"
+#include "cvmx-ipd.h"
+
+/**
+ * Current state of all the pools. Use access functions
+ * instead of using it directly.
+ */
+CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
+
+/**
+ * Setup a FPA pool to control a new block of memory. The
+ * buffer pointer must be a physical address.
+ *
+ * @pool:       Pool to initialize
+ *                   0 <= pool < 8
+ * @name:       Constant character string to name this pool.
+ *                   String is not copied.
+ * @buffer:     Pointer to the block of memory to use. This must be
+ *                   accessable by all processors and external hardware.
+ * @block_size: Size for each block controlled by the FPA
+ * @num_blocks: Number of blocks
+ *
+ * Returns 0 on Success,
+ *         -1 on failure
+ */
+int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
+                        uint64_t block_size, uint64_t num_blocks)
+{
+        char *ptr;
+        if (!buffer) {
+                cvmx_dprintf
+                    ("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n");
+                return -1;
+        }
+        if (pool >= CVMX_FPA_NUM_POOLS) {
+                cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n");
+                return -1;
+        }
+
+        if (block_size < CVMX_FPA_MIN_BLOCK_SIZE) {
+                cvmx_dprintf
+                    ("ERROR: cvmx_fpa_setup_pool: Block size too small.\n");
+                return -1;
+        }
+
+        if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT - 1)) != 0) {
+                cvmx_dprintf
+                    ("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n");
+                return -1;
+        }
+
+        cvmx_fpa_pool_info[pool].name = name;
+        cvmx_fpa_pool_info[pool].size = block_size;
+        cvmx_fpa_pool_info[pool].starting_element_count = num_blocks;
+        cvmx_fpa_pool_info[pool].base = buffer;
+
+        ptr = (char *)buffer;
+        while (num_blocks--) {
+                cvmx_fpa_free(ptr, pool, 0);
+                ptr += block_size;
+        }
+        return 0;
+}
+
+/**
+ * Shutdown a Memory pool and validate that it had all of
+ * the buffers originally placed in it.
+ *
+ * @pool:   Pool to shutdown
+ * Returns Zero on success
+ *         - Positive is count of missing buffers
+ *         - Negative is too many buffers or corrupted pointers
+ */
+uint64_t cvmx_fpa_shutdown_pool(uint64_t pool)
+{
+        uint64_t errors = 0;
+        uint64_t count = 0;
+        uint64_t base = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base);
+        uint64_t finish =
+            base +
+            cvmx_fpa_pool_info[pool].size *
+            cvmx_fpa_pool_info[pool].starting_element_count;
+        void *ptr;
+        uint64_t address;
+
+        count = 0;
+        do {
+                ptr = cvmx_fpa_alloc(pool);
+                if (ptr)
+                        address = cvmx_ptr_to_phys(ptr);
+                else
+                        address = 0;
+                if (address) {
+                        if ((address >= base) && (address < finish) &&
+                            (((address -
+                               base) % cvmx_fpa_pool_info[pool].size) == 0)) {
+                                count++;
+                        } else {
+                                cvmx_dprintf
+                                    ("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n",
+                                     (unsigned long long)address,
+                                     cvmx_fpa_pool_info[pool].name, (int)pool);
+                                errors++;
+                        }
+                }
+        } while (address);
+
+#ifdef CVMX_ENABLE_PKO_FUNCTIONS
+        if (pool == 0)
+                cvmx_ipd_free_ptr();
+#endif
+
+        if (errors) {
+                cvmx_dprintf
+                    ("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n",
+                     cvmx_fpa_pool_info[pool].name, (int)pool,
+                     (unsigned long long)base, (unsigned long long)finish,
+                     (unsigned long long)cvmx_fpa_pool_info[pool].size);
+                return -errors;
+        } else
+                return 0;
+}
+
+uint64_t cvmx_fpa_get_block_size(uint64_t pool)
+{
+        switch (pool) {
+        case 0:
+                return CVMX_FPA_POOL_0_SIZE;
+        case 1:
+                return CVMX_FPA_POOL_1_SIZE;
+        case 2:
+                return CVMX_FPA_POOL_2_SIZE;
+        case 3:
+                return CVMX_FPA_POOL_3_SIZE;
+        case 4:
+                return CVMX_FPA_POOL_4_SIZE;
+        case 5:
+                return CVMX_FPA_POOL_5_SIZE;
+        case 6:
+                return CVMX_FPA_POOL_6_SIZE;
+        case 7:
+                return CVMX_FPA_POOL_7_SIZE;
+        default:
+                return 0;
+        }
+}
diff --git a/drivers/staging/octeon/cvmx-fpa.h b/drivers/staging/octeon/cvmx-fpa.h
new file mode 100644
index 000000000000..1d7788fe09f2
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-fpa.h
@@ -0,0 +1,299 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Interface to the hardware Free Pool Allocator.
+ *
+ *
+ */
+
+#ifndef __CVMX_FPA_H__
+#define __CVMX_FPA_H__
+
+#include "cvmx-address.h"
+#include "cvmx-fpa-defs.h"
+
+#define CVMX_FPA_NUM_POOLS      8
+#define CVMX_FPA_MIN_BLOCK_SIZE 128
+#define CVMX_FPA_ALIGNMENT      128
+
+/**
+ * Structure describing the data format used for stores to the FPA.
+ */
+typedef union {
+        uint64_t u64;
+        struct {
+                /*
+                 * the (64-bit word) location in scratchpad to write
+                 * to (if len != 0)
+                 */
+                uint64_t scraddr:8;
+                /* the number of words in the response (0 => no response) */
+                uint64_t len:8;
+                /* the ID of the device on the non-coherent bus */
+                uint64_t did:8;
+                /*
+                 * the address that will appear in the first tick on
+                 * the NCB bus.
+                 */
+                uint64_t addr:40;
+        } s;
+} cvmx_fpa_iobdma_data_t;
+
+/**
+ * Structure describing the current state of a FPA pool.
+ */
+typedef struct {
+        /* Name it was created under */
+        const char *name;
+        /* Size of each block */
+        uint64_t size;
+        /* The base memory address of whole block */
+        void *base;
+        /* The number of elements in the pool at creation */
+        uint64_t starting_element_count;
+} cvmx_fpa_pool_info_t;
+
+/**
+ * Current state of all the pools. Use access functions
+ * instead of using it directly.
+ */
+extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Return the name of the pool
+ *
+ * @pool:   Pool to get the name of
+ * Returns The name
+ */
+static inline const char *cvmx_fpa_get_name(uint64_t pool)
+{
+        return cvmx_fpa_pool_info[pool].name;
+}
+
+/**
+ * Return the base of the pool
+ *
+ * @pool:   Pool to get the base of
+ * Returns The base
+ */
+static inline void *cvmx_fpa_get_base(uint64_t pool)
+{
+        return cvmx_fpa_pool_info[pool].base;
+}
+
+/**
+ * Check if a pointer belongs to an FPA pool. Return non-zero
+ * if the supplied pointer is inside the memory controlled by
+ * an FPA pool.
+ *
+ * @pool:   Pool to check
+ * @ptr:    Pointer to check
+ * Returns Non-zero if pointer is in the pool. Zero if not
+ */
+static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr)
+{
+        return ((ptr >= cvmx_fpa_pool_info[pool].base) &&
+                ((char *)ptr <
+                 ((char *)(cvmx_fpa_pool_info[pool].base)) +
+                 cvmx_fpa_pool_info[pool].size *
+                 cvmx_fpa_pool_info[pool].starting_element_count));
+}
+
+/**
+ * Enable the FPA for use. Must be performed after any CSR
+ * configuration but before any other FPA functions.
+ */
+static inline void cvmx_fpa_enable(void)
+{
+        union cvmx_fpa_ctl_status status;
+
+        status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS);
+        if (status.s.enb) {
+                cvmx_dprintf
+                    ("Warning: Enabling FPA when FPA already enabled.\n");
+        }
+
+        /*
+         * Do runtime check as we allow pass1 compiled code to run on
+         * pass2 chips.
+         */
+        if (cvmx_octeon_is_pass1()) {
+                union cvmx_fpa_fpfx_marks marks;
+                int i;
+                for (i = 1; i < 8; i++) {
+                        marks.u64 =
+                            cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull);
+                        marks.s.fpf_wr = 0xe0;
+                        cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull,
+                                       marks.u64);
+                }
+
+                /* Enforce a 10 cycle delay between config and enable */
+                cvmx_wait(10);
+        }
+
+        /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */
+        status.u64 = 0;
+        status.s.enb = 1;
+        cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64);
+}
+
+/**
+ * Get a new block from the FPA
+ *
+ * @pool:   Pool to get the block from
+ * Returns Pointer to the block or NULL on failure
+ */
+static inline void *cvmx_fpa_alloc(uint64_t pool)
+{
+        uint64_t address =
+            cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)));
+        if (address)
+                return cvmx_phys_to_ptr(address);
+        else
+                return NULL;
+}
+
+/**
+ * Asynchronously get a new block from the FPA
+ *
+ * @scr_addr: Local scratch address to put response in.  This is a byte address,
+ *                  but must be 8 byte aligned.
+ * @pool:      Pool to get the block from
+ */
+static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
+{
+        cvmx_fpa_iobdma_data_t data;
+
+        /*
+         * Hardware only uses 64 bit alligned locations, so convert
+         * from byte address to 64-bit index
+         */
+        data.s.scraddr = scr_addr >> 3;
+        data.s.len = 1;
+        data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool);
+        data.s.addr = 0;
+        cvmx_send_single(data.u64);
+}
+
+/**
+ * Free a block allocated with a FPA pool.  Does NOT provide memory
+ * ordering in cases where the memory block was modified by the core.
+ *
+ * @ptr:    Block to free
+ * @pool:   Pool to put it in
+ * @num_cache_lines:
+ *               Cache lines to invalidate
+ */
+static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool,
+                                        uint64_t num_cache_lines)
+{
+        cvmx_addr_t newptr;
+        newptr.u64 = cvmx_ptr_to_phys(ptr);
+        newptr.sfilldidspace.didspace =
+            CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
+        /* Prevent GCC from reordering around free */
+        barrier();
+        /* value written is number of cache lines not written back */
+        cvmx_write_io(newptr.u64, num_cache_lines);
+}
+
+/**
+ * Free a block allocated with a FPA pool.  Provides required memory
+ * ordering in cases where memory block was modified by core.
+ *
+ * @ptr:    Block to free
+ * @pool:   Pool to put it in
+ * @num_cache_lines:
+ *               Cache lines to invalidate
+ */
+static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
+                                 uint64_t num_cache_lines)
+{
+        cvmx_addr_t newptr;
+        newptr.u64 = cvmx_ptr_to_phys(ptr);
+        newptr.sfilldidspace.didspace =
+            CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
+        /*
+         * Make sure that any previous writes to memory go out before
+         * we free this buffer.  This also serves as a barrier to
+         * prevent GCC from reordering operations to after the
+         * free.
+         */
+        CVMX_SYNCWS;
+        /* value written is number of cache lines not written back */
+        cvmx_write_io(newptr.u64, num_cache_lines);
+}
+
+/**
+ * Setup a FPA pool to control a new block of memory.
+ * This can only be called once per pool. Make sure proper
+ * locking enforces this.
+ *
+ * @pool:       Pool to initialize
+ *                   0 <= pool < 8
+ * @name:       Constant character string to name this pool.
+ *                   String is not copied.
+ * @buffer:     Pointer to the block of memory to use. This must be
+ *                   accessable by all processors and external hardware.
+ * @block_size: Size for each block controlled by the FPA
+ * @num_blocks: Number of blocks
+ *
+ * Returns 0 on Success,
+ *         -1 on failure
+ */
+extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
+                               uint64_t block_size, uint64_t num_blocks);
+
+/**
+ * Shutdown a Memory pool and validate that it had all of
+ * the buffers originally placed in it. This should only be
+ * called by one processor after all hardware has finished
+ * using the pool.
+ *
+ * @pool:   Pool to shutdown
+ * Returns Zero on success
+ *         - Positive is count of missing buffers
+ *         - Negative is too many buffers or corrupted pointers
+ */
+extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
+
+/**
+ * Get the size of blocks controlled by the pool
+ * This is resolved to a constant at compile time.
+ *
+ * @pool:   Pool to access
+ * Returns Size of the block in bytes
+ */
+uint64_t cvmx_fpa_get_block_size(uint64_t pool);
+
+#endif /*  __CVM_FPA_H__ */
diff --git a/drivers/staging/octeon/cvmx-gmxx-defs.h b/drivers/staging/octeon/cvmx-gmxx-defs.h
new file mode 100644
index 000000000000..946a43a73fd7
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-gmxx-defs.h
@@ -0,0 +1,2529 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_GMXX_DEFS_H__
+#define __CVMX_GMXX_DEFS_H__
+
+#define CVMX_GMXX_BAD_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_BIST(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_CLK_EN(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_HG2_CONTROL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_INF_MODE(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_NXA_ADR(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_PRTX_CFG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_DECISION(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_IFG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_JABBER(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RX_HG2_STATUS(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RX_PASS_EN(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RX_PRTS(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RX_PRT_INFO(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RX_TX_STATUS(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull))
+#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_RX_XAUI_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_SMACX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_STAT_BP(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_APPEND(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_BURST(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_CLK(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_CTL(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_SLOT(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_STAT0(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_STAT1(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_STAT2(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_STAT3(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_STAT4(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_STAT5(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_STAT6(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_STAT7(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_STAT8(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_STAT9(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TXX_THRESH(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_BP(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull))
+#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_CORRUPT(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_HG2_REG1(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_HG2_REG2(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_IFG(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_INT_EN(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_INT_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_JAM(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_LFSR(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_OVR_BP(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_PRTS(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_SPI_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_SPI_MAX(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_SPI_THRESH(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_TX_XAUI_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull))
+
+union cvmx_gmxx_bad_reg {
+        uint64_t u64;
+        struct cvmx_gmxx_bad_reg_s {
+                uint64_t reserved_31_63:33;
+                uint64_t inb_nxa:4;
+                uint64_t statovr:1;
+                uint64_t loststat:4;
+                uint64_t reserved_18_21:4;
+                uint64_t out_ovr:16;
+                uint64_t ncb_ovr:1;
+                uint64_t out_col:1;
+        } s;
+        struct cvmx_gmxx_bad_reg_cn30xx {
+                uint64_t reserved_31_63:33;
+                uint64_t inb_nxa:4;
+                uint64_t statovr:1;
+                uint64_t reserved_25_25:1;
+                uint64_t loststat:3;
+                uint64_t reserved_5_21:17;
+                uint64_t out_ovr:3;
+                uint64_t reserved_0_1:2;
+        } cn30xx;
+        struct cvmx_gmxx_bad_reg_cn30xx cn31xx;
+        struct cvmx_gmxx_bad_reg_s cn38xx;
+        struct cvmx_gmxx_bad_reg_s cn38xxp2;
+        struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
+        struct cvmx_gmxx_bad_reg_cn52xx {
+                uint64_t reserved_31_63:33;
+                uint64_t inb_nxa:4;
+                uint64_t statovr:1;
+                uint64_t loststat:4;
+                uint64_t reserved_6_21:16;
+                uint64_t out_ovr:4;
+                uint64_t reserved_0_1:2;
+        } cn52xx;
+        struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;
+        struct cvmx_gmxx_bad_reg_cn52xx cn56xx;
+        struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
+        struct cvmx_gmxx_bad_reg_s cn58xx;
+        struct cvmx_gmxx_bad_reg_s cn58xxp1;
+};
+
+union cvmx_gmxx_bist {
+        uint64_t u64;
+        struct cvmx_gmxx_bist_s {
+                uint64_t reserved_17_63:47;
+                uint64_t status:17;
+        } s;
+        struct cvmx_gmxx_bist_cn30xx {
+                uint64_t reserved_10_63:54;
+                uint64_t status:10;
+        } cn30xx;
+        struct cvmx_gmxx_bist_cn30xx cn31xx;
+        struct cvmx_gmxx_bist_cn30xx cn38xx;
+        struct cvmx_gmxx_bist_cn30xx cn38xxp2;
+        struct cvmx_gmxx_bist_cn50xx {
+                uint64_t reserved_12_63:52;
+                uint64_t status:12;
+        } cn50xx;
+        struct cvmx_gmxx_bist_cn52xx {
+                uint64_t reserved_16_63:48;
+                uint64_t status:16;
+        } cn52xx;
+        struct cvmx_gmxx_bist_cn52xx cn52xxp1;
+        struct cvmx_gmxx_bist_cn52xx cn56xx;
+        struct cvmx_gmxx_bist_cn52xx cn56xxp1;
+        struct cvmx_gmxx_bist_s cn58xx;
+        struct cvmx_gmxx_bist_s cn58xxp1;
+};
+
+union cvmx_gmxx_clk_en {
+        uint64_t u64;
+        struct cvmx_gmxx_clk_en_s {
+                uint64_t reserved_1_63:63;
+                uint64_t clk_en:1;
+        } s;
+        struct cvmx_gmxx_clk_en_s cn52xx;
+        struct cvmx_gmxx_clk_en_s cn52xxp1;
+        struct cvmx_gmxx_clk_en_s cn56xx;
+        struct cvmx_gmxx_clk_en_s cn56xxp1;
+};
+
+union cvmx_gmxx_hg2_control {
+        uint64_t u64;
+        struct cvmx_gmxx_hg2_control_s {
+                uint64_t reserved_19_63:45;
+                uint64_t hg2tx_en:1;
+                uint64_t hg2rx_en:1;
+                uint64_t phys_en:1;
+                uint64_t logl_en:16;
+        } s;
+        struct cvmx_gmxx_hg2_control_s cn52xx;
+        struct cvmx_gmxx_hg2_control_s cn52xxp1;
+        struct cvmx_gmxx_hg2_control_s cn56xx;
+};
+
+union cvmx_gmxx_inf_mode {
+        uint64_t u64;
+        struct cvmx_gmxx_inf_mode_s {
+                uint64_t reserved_10_63:54;
+                uint64_t speed:2;
+                uint64_t reserved_6_7:2;
+                uint64_t mode:2;
+                uint64_t reserved_3_3:1;
+                uint64_t p0mii:1;
+                uint64_t en:1;
+                uint64_t type:1;
+        } s;
+        struct cvmx_gmxx_inf_mode_cn30xx {
+                uint64_t reserved_3_63:61;
+                uint64_t p0mii:1;
+                uint64_t en:1;
+                uint64_t type:1;
+        } cn30xx;
+        struct cvmx_gmxx_inf_mode_cn31xx {
+                uint64_t reserved_2_63:62;
+                uint64_t en:1;
+                uint64_t type:1;
+        } cn31xx;
+        struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
+        struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
+        struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
+        struct cvmx_gmxx_inf_mode_cn52xx {
+                uint64_t reserved_10_63:54;
+                uint64_t speed:2;
+                uint64_t reserved_6_7:2;
+                uint64_t mode:2;
+                uint64_t reserved_2_3:2;
+                uint64_t en:1;
+                uint64_t type:1;
+        } cn52xx;
+        struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;
+        struct cvmx_gmxx_inf_mode_cn52xx cn56xx;
+        struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
+        struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
+        struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
+};
+
+union cvmx_gmxx_nxa_adr {
+        uint64_t u64;
+        struct cvmx_gmxx_nxa_adr_s {
+                uint64_t reserved_6_63:58;
+                uint64_t prt:6;
+        } s;
+        struct cvmx_gmxx_nxa_adr_s cn30xx;
+        struct cvmx_gmxx_nxa_adr_s cn31xx;
+        struct cvmx_gmxx_nxa_adr_s cn38xx;
+        struct cvmx_gmxx_nxa_adr_s cn38xxp2;
+        struct cvmx_gmxx_nxa_adr_s cn50xx;
+        struct cvmx_gmxx_nxa_adr_s cn52xx;
+        struct cvmx_gmxx_nxa_adr_s cn52xxp1;
+        struct cvmx_gmxx_nxa_adr_s cn56xx;
+        struct cvmx_gmxx_nxa_adr_s cn56xxp1;
+        struct cvmx_gmxx_nxa_adr_s cn58xx;
+        struct cvmx_gmxx_nxa_adr_s cn58xxp1;
+};
+
+union cvmx_gmxx_prtx_cbfc_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_prtx_cbfc_ctl_s {
+                uint64_t phys_en:16;
+                uint64_t logl_en:16;
+                uint64_t phys_bp:16;
+                uint64_t reserved_4_15:12;
+                uint64_t bck_en:1;
+                uint64_t drp_en:1;
+                uint64_t tx_en:1;
+                uint64_t rx_en:1;
+        } s;
+        struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
+        struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
+};
+
+union cvmx_gmxx_prtx_cfg {
+        uint64_t u64;
+        struct cvmx_gmxx_prtx_cfg_s {
+                uint64_t reserved_14_63:50;
+                uint64_t tx_idle:1;
+                uint64_t rx_idle:1;
+                uint64_t reserved_9_11:3;
+                uint64_t speed_msb:1;
+                uint64_t reserved_4_7:4;
+                uint64_t slottime:1;
+                uint64_t duplex:1;
+                uint64_t speed:1;
+                uint64_t en:1;
+        } s;
+        struct cvmx_gmxx_prtx_cfg_cn30xx {
+                uint64_t reserved_4_63:60;
+                uint64_t slottime:1;
+                uint64_t duplex:1;
+                uint64_t speed:1;
+                uint64_t en:1;
+        } cn30xx;
+        struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;
+        struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
+        struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
+        struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
+        struct cvmx_gmxx_prtx_cfg_s cn52xx;
+        struct cvmx_gmxx_prtx_cfg_s cn52xxp1;
+        struct cvmx_gmxx_prtx_cfg_s cn56xx;
+        struct cvmx_gmxx_prtx_cfg_s cn56xxp1;
+        struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
+        struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_adr_cam0 {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_adr_cam0_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_gmxx_rxx_adr_cam0_s cn30xx;
+        struct cvmx_gmxx_rxx_adr_cam0_s cn31xx;
+        struct cvmx_gmxx_rxx_adr_cam0_s cn38xx;
+        struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2;
+        struct cvmx_gmxx_rxx_adr_cam0_s cn50xx;
+        struct cvmx_gmxx_rxx_adr_cam0_s cn52xx;
+        struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1;
+        struct cvmx_gmxx_rxx_adr_cam0_s cn56xx;
+        struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
+        struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
+        struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_adr_cam1 {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_adr_cam1_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_gmxx_rxx_adr_cam1_s cn30xx;
+        struct cvmx_gmxx_rxx_adr_cam1_s cn31xx;
+        struct cvmx_gmxx_rxx_adr_cam1_s cn38xx;
+        struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2;
+        struct cvmx_gmxx_rxx_adr_cam1_s cn50xx;
+        struct cvmx_gmxx_rxx_adr_cam1_s cn52xx;
+        struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1;
+        struct cvmx_gmxx_rxx_adr_cam1_s cn56xx;
+        struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
+        struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
+        struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_adr_cam2 {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_adr_cam2_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_gmxx_rxx_adr_cam2_s cn30xx;
+        struct cvmx_gmxx_rxx_adr_cam2_s cn31xx;
+        struct cvmx_gmxx_rxx_adr_cam2_s cn38xx;
+        struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2;
+        struct cvmx_gmxx_rxx_adr_cam2_s cn50xx;
+        struct cvmx_gmxx_rxx_adr_cam2_s cn52xx;
+        struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1;
+        struct cvmx_gmxx_rxx_adr_cam2_s cn56xx;
+        struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
+        struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
+        struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_adr_cam3 {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_adr_cam3_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_gmxx_rxx_adr_cam3_s cn30xx;
+        struct cvmx_gmxx_rxx_adr_cam3_s cn31xx;
+        struct cvmx_gmxx_rxx_adr_cam3_s cn38xx;
+        struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2;
+        struct cvmx_gmxx_rxx_adr_cam3_s cn50xx;
+        struct cvmx_gmxx_rxx_adr_cam3_s cn52xx;
+        struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1;
+        struct cvmx_gmxx_rxx_adr_cam3_s cn56xx;
+        struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
+        struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
+        struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_adr_cam4 {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_adr_cam4_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_gmxx_rxx_adr_cam4_s cn30xx;
+        struct cvmx_gmxx_rxx_adr_cam4_s cn31xx;
+        struct cvmx_gmxx_rxx_adr_cam4_s cn38xx;
+        struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2;
+        struct cvmx_gmxx_rxx_adr_cam4_s cn50xx;
+        struct cvmx_gmxx_rxx_adr_cam4_s cn52xx;
+        struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1;
+        struct cvmx_gmxx_rxx_adr_cam4_s cn56xx;
+        struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
+        struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
+        struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_adr_cam5 {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_adr_cam5_s {
+                uint64_t adr:64;
+        } s;
+        struct cvmx_gmxx_rxx_adr_cam5_s cn30xx;
+        struct cvmx_gmxx_rxx_adr_cam5_s cn31xx;
+        struct cvmx_gmxx_rxx_adr_cam5_s cn38xx;
+        struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2;
+        struct cvmx_gmxx_rxx_adr_cam5_s cn50xx;
+        struct cvmx_gmxx_rxx_adr_cam5_s cn52xx;
+        struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1;
+        struct cvmx_gmxx_rxx_adr_cam5_s cn56xx;
+        struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
+        struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
+        struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_adr_cam_en {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_adr_cam_en_s {
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+        } s;
+        struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;
+        struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;
+        struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx;
+        struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2;
+        struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx;
+        struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx;
+        struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1;
+        struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx;
+        struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
+        struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
+        struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_adr_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_adr_ctl_s {
+                uint64_t reserved_4_63:60;
+                uint64_t cam_mode:1;
+                uint64_t mcst:2;
+                uint64_t bcst:1;
+        } s;
+        struct cvmx_gmxx_rxx_adr_ctl_s cn30xx;
+        struct cvmx_gmxx_rxx_adr_ctl_s cn31xx;
+        struct cvmx_gmxx_rxx_adr_ctl_s cn38xx;
+        struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2;
+        struct cvmx_gmxx_rxx_adr_ctl_s cn50xx;
+        struct cvmx_gmxx_rxx_adr_ctl_s cn52xx;
+        struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1;
+        struct cvmx_gmxx_rxx_adr_ctl_s cn56xx;
+        struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
+        struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
+        struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_decision {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_decision_s {
+                uint64_t reserved_5_63:59;
+                uint64_t cnt:5;
+        } s;
+        struct cvmx_gmxx_rxx_decision_s cn30xx;
+        struct cvmx_gmxx_rxx_decision_s cn31xx;
+        struct cvmx_gmxx_rxx_decision_s cn38xx;
+        struct cvmx_gmxx_rxx_decision_s cn38xxp2;
+        struct cvmx_gmxx_rxx_decision_s cn50xx;
+        struct cvmx_gmxx_rxx_decision_s cn52xx;
+        struct cvmx_gmxx_rxx_decision_s cn52xxp1;
+        struct cvmx_gmxx_rxx_decision_s cn56xx;
+        struct cvmx_gmxx_rxx_decision_s cn56xxp1;
+        struct cvmx_gmxx_rxx_decision_s cn58xx;
+        struct cvmx_gmxx_rxx_decision_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_frm_chk {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_frm_chk_s {
+                uint64_t reserved_10_63:54;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_gmxx_rxx_frm_chk_s cn30xx;
+        struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
+        struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
+        struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
+        struct cvmx_gmxx_rxx_frm_chk_cn50xx {
+                uint64_t reserved_10_63:54;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_6_6:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+        } cn50xx;
+        struct cvmx_gmxx_rxx_frm_chk_cn52xx {
+                uint64_t reserved_9_63:55;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+        } cn52xx;
+        struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;
+        struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;
+        struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
+        struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
+        struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_frm_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_frm_ctl_s {
+                uint64_t reserved_11_63:53;
+                uint64_t null_dis:1;
+                uint64_t pre_align:1;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+        } s;
+        struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
+                uint64_t reserved_9_63:55;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+        } cn30xx;
+        struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
+                uint64_t reserved_8_63:56;
+                uint64_t vlan_len:1;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+        } cn31xx;
+        struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
+        struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
+        struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
+                uint64_t reserved_11_63:53;
+                uint64_t null_dis:1;
+                uint64_t pre_align:1;
+                uint64_t reserved_7_8:2;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+        } cn50xx;
+        struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
+        struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
+        struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
+        struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
+                uint64_t reserved_10_63:54;
+                uint64_t pre_align:1;
+                uint64_t reserved_7_8:2;
+                uint64_t pre_free:1;
+                uint64_t ctl_smac:1;
+                uint64_t ctl_mcst:1;
+                uint64_t ctl_bck:1;
+                uint64_t ctl_drp:1;
+                uint64_t pre_strp:1;
+                uint64_t pre_chk:1;
+        } cn56xxp1;
+        struct cvmx_gmxx_rxx_frm_ctl_s cn58xx;
+        struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_frm_max {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_frm_max_s {
+                uint64_t reserved_16_63:48;
+                uint64_t len:16;
+        } s;
+        struct cvmx_gmxx_rxx_frm_max_s cn30xx;
+        struct cvmx_gmxx_rxx_frm_max_s cn31xx;
+        struct cvmx_gmxx_rxx_frm_max_s cn38xx;
+        struct cvmx_gmxx_rxx_frm_max_s cn38xxp2;
+        struct cvmx_gmxx_rxx_frm_max_s cn58xx;
+        struct cvmx_gmxx_rxx_frm_max_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_frm_min {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_frm_min_s {
+                uint64_t reserved_16_63:48;
+                uint64_t len:16;
+        } s;
+        struct cvmx_gmxx_rxx_frm_min_s cn30xx;
+        struct cvmx_gmxx_rxx_frm_min_s cn31xx;
+        struct cvmx_gmxx_rxx_frm_min_s cn38xx;
+        struct cvmx_gmxx_rxx_frm_min_s cn38xxp2;
+        struct cvmx_gmxx_rxx_frm_min_s cn58xx;
+        struct cvmx_gmxx_rxx_frm_min_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_ifg {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_ifg_s {
+                uint64_t reserved_4_63:60;
+                uint64_t ifg:4;
+        } s;
+        struct cvmx_gmxx_rxx_ifg_s cn30xx;
+        struct cvmx_gmxx_rxx_ifg_s cn31xx;
+        struct cvmx_gmxx_rxx_ifg_s cn38xx;
+        struct cvmx_gmxx_rxx_ifg_s cn38xxp2;
+        struct cvmx_gmxx_rxx_ifg_s cn50xx;
+        struct cvmx_gmxx_rxx_ifg_s cn52xx;
+        struct cvmx_gmxx_rxx_ifg_s cn52xxp1;
+        struct cvmx_gmxx_rxx_ifg_s cn56xx;
+        struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
+        struct cvmx_gmxx_rxx_ifg_s cn58xx;
+        struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_int_en {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_int_en_s {
+                uint64_t reserved_29_63:35;
+                uint64_t hg2cc:1;
+                uint64_t hg2fld:1;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_gmxx_rxx_int_en_cn30xx {
+                uint64_t reserved_19_63:45;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } cn30xx;
+        struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
+        struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
+        struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
+        struct cvmx_gmxx_rxx_int_en_cn50xx {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_6_6:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+        } cn50xx;
+        struct cvmx_gmxx_rxx_int_en_cn52xx {
+                uint64_t reserved_29_63:35;
+                uint64_t hg2cc:1;
+                uint64_t hg2fld:1;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+        } cn52xx;
+        struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
+        struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
+        struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
+                uint64_t reserved_27_63:37;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+        } cn56xxp1;
+        struct cvmx_gmxx_rxx_int_en_cn58xx {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } cn58xx;
+        struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_int_reg {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_int_reg_s {
+                uint64_t reserved_29_63:35;
+                uint64_t hg2cc:1;
+                uint64_t hg2fld:1;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } s;
+        struct cvmx_gmxx_rxx_int_reg_cn30xx {
+                uint64_t reserved_19_63:45;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } cn30xx;
+        struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
+        struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
+        struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
+        struct cvmx_gmxx_rxx_int_reg_cn50xx {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_6_6:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+        } cn50xx;
+        struct cvmx_gmxx_rxx_int_reg_cn52xx {
+                uint64_t reserved_29_63:35;
+                uint64_t hg2cc:1;
+                uint64_t hg2fld:1;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+        } cn52xx;
+        struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1;
+        struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx;
+        struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
+                uint64_t reserved_27_63:37;
+                uint64_t undat:1;
+                uint64_t uneop:1;
+                uint64_t unsop:1;
+                uint64_t bad_term:1;
+                uint64_t bad_seq:1;
+                uint64_t rem_fault:1;
+                uint64_t loc_fault:1;
+                uint64_t pause_drp:1;
+                uint64_t reserved_16_18:3;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t reserved_9_9:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t reserved_5_6:2;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t reserved_2_2:1;
+                uint64_t carext:1;
+                uint64_t reserved_0_0:1;
+        } cn56xxp1;
+        struct cvmx_gmxx_rxx_int_reg_cn58xx {
+                uint64_t reserved_20_63:44;
+                uint64_t pause_drp:1;
+                uint64_t phy_dupx:1;
+                uint64_t phy_spd:1;
+                uint64_t phy_link:1;
+                uint64_t ifgerr:1;
+                uint64_t coldet:1;
+                uint64_t falerr:1;
+                uint64_t rsverr:1;
+                uint64_t pcterr:1;
+                uint64_t ovrerr:1;
+                uint64_t niberr:1;
+                uint64_t skperr:1;
+                uint64_t rcverr:1;
+                uint64_t lenerr:1;
+                uint64_t alnerr:1;
+                uint64_t fcserr:1;
+                uint64_t jabber:1;
+                uint64_t maxerr:1;
+                uint64_t carext:1;
+                uint64_t minerr:1;
+        } cn58xx;
+        struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_jabber {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_jabber_s {
+                uint64_t reserved_16_63:48;
+                uint64_t cnt:16;
+        } s;
+        struct cvmx_gmxx_rxx_jabber_s cn30xx;
+        struct cvmx_gmxx_rxx_jabber_s cn31xx;
+        struct cvmx_gmxx_rxx_jabber_s cn38xx;
+        struct cvmx_gmxx_rxx_jabber_s cn38xxp2;
+        struct cvmx_gmxx_rxx_jabber_s cn50xx;
+        struct cvmx_gmxx_rxx_jabber_s cn52xx;
+        struct cvmx_gmxx_rxx_jabber_s cn52xxp1;
+        struct cvmx_gmxx_rxx_jabber_s cn56xx;
+        struct cvmx_gmxx_rxx_jabber_s cn56xxp1;
+        struct cvmx_gmxx_rxx_jabber_s cn58xx;
+        struct cvmx_gmxx_rxx_jabber_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_pause_drop_time {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_pause_drop_time_s {
+                uint64_t reserved_16_63:48;
+                uint64_t status:16;
+        } s;
+        struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
+        struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
+        struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
+        struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
+        struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
+        struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
+        struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_rx_inbnd {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_rx_inbnd_s {
+                uint64_t reserved_4_63:60;
+                uint64_t duplex:1;
+                uint64_t speed:2;
+                uint64_t status:1;
+        } s;
+        struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx;
+        struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx;
+        struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx;
+        struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2;
+        struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx;
+        struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx;
+        struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_stats_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_stats_ctl_s {
+                uint64_t reserved_1_63:63;
+                uint64_t rd_clr:1;
+        } s;
+        struct cvmx_gmxx_rxx_stats_ctl_s cn30xx;
+        struct cvmx_gmxx_rxx_stats_ctl_s cn31xx;
+        struct cvmx_gmxx_rxx_stats_ctl_s cn38xx;
+        struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2;
+        struct cvmx_gmxx_rxx_stats_ctl_s cn50xx;
+        struct cvmx_gmxx_rxx_stats_ctl_s cn52xx;
+        struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1;
+        struct cvmx_gmxx_rxx_stats_ctl_s cn56xx;
+        struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1;
+        struct cvmx_gmxx_rxx_stats_ctl_s cn58xx;
+        struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_stats_octs {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_stats_octs_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_gmxx_rxx_stats_octs_s cn30xx;
+        struct cvmx_gmxx_rxx_stats_octs_s cn31xx;
+        struct cvmx_gmxx_rxx_stats_octs_s cn38xx;
+        struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2;
+        struct cvmx_gmxx_rxx_stats_octs_s cn50xx;
+        struct cvmx_gmxx_rxx_stats_octs_s cn52xx;
+        struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1;
+        struct cvmx_gmxx_rxx_stats_octs_s cn56xx;
+        struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1;
+        struct cvmx_gmxx_rxx_stats_octs_s cn58xx;
+        struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_stats_octs_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
+        struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_stats_octs_dmac {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
+        struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_stats_octs_drp {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s {
+                uint64_t reserved_48_63:16;
+                uint64_t cnt:48;
+        } s;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
+        struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_stats_pkts {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_stats_pkts_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_gmxx_rxx_stats_pkts_s cn30xx;
+        struct cvmx_gmxx_rxx_stats_pkts_s cn31xx;
+        struct cvmx_gmxx_rxx_stats_pkts_s cn38xx;
+        struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2;
+        struct cvmx_gmxx_rxx_stats_pkts_s cn50xx;
+        struct cvmx_gmxx_rxx_stats_pkts_s cn52xx;
+        struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1;
+        struct cvmx_gmxx_rxx_stats_pkts_s cn56xx;
+        struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1;
+        struct cvmx_gmxx_rxx_stats_pkts_s cn58xx;
+        struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_stats_pkts_bad {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
+        struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_stats_pkts_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
+        struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_stats_pkts_dmac {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
+        struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_stats_pkts_drp {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
+        struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
+};
+
+union cvmx_gmxx_rxx_udd_skp {
+        uint64_t u64;
+        struct cvmx_gmxx_rxx_udd_skp_s {
+                uint64_t reserved_9_63:55;
+                uint64_t fcssel:1;
+                uint64_t reserved_7_7:1;
+                uint64_t len:7;
+        } s;
+        struct cvmx_gmxx_rxx_udd_skp_s cn30xx;
+        struct cvmx_gmxx_rxx_udd_skp_s cn31xx;
+        struct cvmx_gmxx_rxx_udd_skp_s cn38xx;
+        struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2;
+        struct cvmx_gmxx_rxx_udd_skp_s cn50xx;
+        struct cvmx_gmxx_rxx_udd_skp_s cn52xx;
+        struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1;
+        struct cvmx_gmxx_rxx_udd_skp_s cn56xx;
+        struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1;
+        struct cvmx_gmxx_rxx_udd_skp_s cn58xx;
+        struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1;
+};
+
+union cvmx_gmxx_rx_bp_dropx {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_bp_dropx_s {
+                uint64_t reserved_6_63:58;
+                uint64_t mark:6;
+        } s;
+        struct cvmx_gmxx_rx_bp_dropx_s cn30xx;
+        struct cvmx_gmxx_rx_bp_dropx_s cn31xx;
+        struct cvmx_gmxx_rx_bp_dropx_s cn38xx;
+        struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2;
+        struct cvmx_gmxx_rx_bp_dropx_s cn50xx;
+        struct cvmx_gmxx_rx_bp_dropx_s cn52xx;
+        struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1;
+        struct cvmx_gmxx_rx_bp_dropx_s cn56xx;
+        struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1;
+        struct cvmx_gmxx_rx_bp_dropx_s cn58xx;
+        struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1;
+};
+
+union cvmx_gmxx_rx_bp_offx {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_bp_offx_s {
+                uint64_t reserved_6_63:58;
+                uint64_t mark:6;
+        } s;
+        struct cvmx_gmxx_rx_bp_offx_s cn30xx;
+        struct cvmx_gmxx_rx_bp_offx_s cn31xx;
+        struct cvmx_gmxx_rx_bp_offx_s cn38xx;
+        struct cvmx_gmxx_rx_bp_offx_s cn38xxp2;
+        struct cvmx_gmxx_rx_bp_offx_s cn50xx;
+        struct cvmx_gmxx_rx_bp_offx_s cn52xx;
+        struct cvmx_gmxx_rx_bp_offx_s cn52xxp1;
+        struct cvmx_gmxx_rx_bp_offx_s cn56xx;
+        struct cvmx_gmxx_rx_bp_offx_s cn56xxp1;
+        struct cvmx_gmxx_rx_bp_offx_s cn58xx;
+        struct cvmx_gmxx_rx_bp_offx_s cn58xxp1;
+};
+
+union cvmx_gmxx_rx_bp_onx {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_bp_onx_s {
+                uint64_t reserved_9_63:55;
+                uint64_t mark:9;
+        } s;
+        struct cvmx_gmxx_rx_bp_onx_s cn30xx;
+        struct cvmx_gmxx_rx_bp_onx_s cn31xx;
+        struct cvmx_gmxx_rx_bp_onx_s cn38xx;
+        struct cvmx_gmxx_rx_bp_onx_s cn38xxp2;
+        struct cvmx_gmxx_rx_bp_onx_s cn50xx;
+        struct cvmx_gmxx_rx_bp_onx_s cn52xx;
+        struct cvmx_gmxx_rx_bp_onx_s cn52xxp1;
+        struct cvmx_gmxx_rx_bp_onx_s cn56xx;
+        struct cvmx_gmxx_rx_bp_onx_s cn56xxp1;
+        struct cvmx_gmxx_rx_bp_onx_s cn58xx;
+        struct cvmx_gmxx_rx_bp_onx_s cn58xxp1;
+};
+
+union cvmx_gmxx_rx_hg2_status {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_hg2_status_s {
+                uint64_t reserved_48_63:16;
+                uint64_t phtim2go:16;
+                uint64_t xof:16;
+                uint64_t lgtim2go:16;
+        } s;
+        struct cvmx_gmxx_rx_hg2_status_s cn52xx;
+        struct cvmx_gmxx_rx_hg2_status_s cn52xxp1;
+        struct cvmx_gmxx_rx_hg2_status_s cn56xx;
+};
+
+union cvmx_gmxx_rx_pass_en {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_pass_en_s {
+                uint64_t reserved_16_63:48;
+                uint64_t en:16;
+        } s;
+        struct cvmx_gmxx_rx_pass_en_s cn38xx;
+        struct cvmx_gmxx_rx_pass_en_s cn38xxp2;
+        struct cvmx_gmxx_rx_pass_en_s cn58xx;
+        struct cvmx_gmxx_rx_pass_en_s cn58xxp1;
+};
+
+union cvmx_gmxx_rx_pass_mapx {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_pass_mapx_s {
+                uint64_t reserved_4_63:60;
+                uint64_t dprt:4;
+        } s;
+        struct cvmx_gmxx_rx_pass_mapx_s cn38xx;
+        struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2;
+        struct cvmx_gmxx_rx_pass_mapx_s cn58xx;
+        struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1;
+};
+
+union cvmx_gmxx_rx_prt_info {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_prt_info_s {
+                uint64_t reserved_32_63:32;
+                uint64_t drop:16;
+                uint64_t commit:16;
+        } s;
+        struct cvmx_gmxx_rx_prt_info_cn30xx {
+                uint64_t reserved_19_63:45;
+                uint64_t drop:3;
+                uint64_t reserved_3_15:13;
+                uint64_t commit:3;
+        } cn30xx;
+        struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx;
+        struct cvmx_gmxx_rx_prt_info_s cn38xx;
+        struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx;
+        struct cvmx_gmxx_rx_prt_info_cn52xx {
+                uint64_t reserved_20_63:44;
+                uint64_t drop:4;
+                uint64_t reserved_4_15:12;
+                uint64_t commit:4;
+        } cn52xx;
+        struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1;
+        struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx;
+        struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1;
+        struct cvmx_gmxx_rx_prt_info_s cn58xx;
+        struct cvmx_gmxx_rx_prt_info_s cn58xxp1;
+};
+
+union cvmx_gmxx_rx_prts {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_prts_s {
+                uint64_t reserved_3_63:61;
+                uint64_t prts:3;
+        } s;
+        struct cvmx_gmxx_rx_prts_s cn30xx;
+        struct cvmx_gmxx_rx_prts_s cn31xx;
+        struct cvmx_gmxx_rx_prts_s cn38xx;
+        struct cvmx_gmxx_rx_prts_s cn38xxp2;
+        struct cvmx_gmxx_rx_prts_s cn50xx;
+        struct cvmx_gmxx_rx_prts_s cn52xx;
+        struct cvmx_gmxx_rx_prts_s cn52xxp1;
+        struct cvmx_gmxx_rx_prts_s cn56xx;
+        struct cvmx_gmxx_rx_prts_s cn56xxp1;
+        struct cvmx_gmxx_rx_prts_s cn58xx;
+        struct cvmx_gmxx_rx_prts_s cn58xxp1;
+};
+
+union cvmx_gmxx_rx_tx_status {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_tx_status_s {
+                uint64_t reserved_7_63:57;
+                uint64_t tx:3;
+                uint64_t reserved_3_3:1;
+                uint64_t rx:3;
+        } s;
+        struct cvmx_gmxx_rx_tx_status_s cn30xx;
+        struct cvmx_gmxx_rx_tx_status_s cn31xx;
+        struct cvmx_gmxx_rx_tx_status_s cn50xx;
+};
+
+union cvmx_gmxx_rx_xaui_bad_col {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_xaui_bad_col_s {
+                uint64_t reserved_40_63:24;
+                uint64_t val:1;
+                uint64_t state:3;
+                uint64_t lane_rxc:4;
+                uint64_t lane_rxd:32;
+        } s;
+        struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx;
+        struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1;
+        struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx;
+        struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1;
+};
+
+union cvmx_gmxx_rx_xaui_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_rx_xaui_ctl_s {
+                uint64_t reserved_2_63:62;
+                uint64_t status:2;
+        } s;
+        struct cvmx_gmxx_rx_xaui_ctl_s cn52xx;
+        struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1;
+        struct cvmx_gmxx_rx_xaui_ctl_s cn56xx;
+        struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1;
+};
+
+union cvmx_gmxx_smacx {
+        uint64_t u64;
+        struct cvmx_gmxx_smacx_s {
+                uint64_t reserved_48_63:16;
+                uint64_t smac:48;
+        } s;
+        struct cvmx_gmxx_smacx_s cn30xx;
+        struct cvmx_gmxx_smacx_s cn31xx;
+        struct cvmx_gmxx_smacx_s cn38xx;
+        struct cvmx_gmxx_smacx_s cn38xxp2;
+        struct cvmx_gmxx_smacx_s cn50xx;
+        struct cvmx_gmxx_smacx_s cn52xx;
+        struct cvmx_gmxx_smacx_s cn52xxp1;
+        struct cvmx_gmxx_smacx_s cn56xx;
+        struct cvmx_gmxx_smacx_s cn56xxp1;
+        struct cvmx_gmxx_smacx_s cn58xx;
+        struct cvmx_gmxx_smacx_s cn58xxp1;
+};
+
+union cvmx_gmxx_stat_bp {
+        uint64_t u64;
+        struct cvmx_gmxx_stat_bp_s {
+                uint64_t reserved_17_63:47;
+                uint64_t bp:1;
+                uint64_t cnt:16;
+        } s;
+        struct cvmx_gmxx_stat_bp_s cn30xx;
+        struct cvmx_gmxx_stat_bp_s cn31xx;
+        struct cvmx_gmxx_stat_bp_s cn38xx;
+        struct cvmx_gmxx_stat_bp_s cn38xxp2;
+        struct cvmx_gmxx_stat_bp_s cn50xx;
+        struct cvmx_gmxx_stat_bp_s cn52xx;
+        struct cvmx_gmxx_stat_bp_s cn52xxp1;
+        struct cvmx_gmxx_stat_bp_s cn56xx;
+        struct cvmx_gmxx_stat_bp_s cn56xxp1;
+        struct cvmx_gmxx_stat_bp_s cn58xx;
+        struct cvmx_gmxx_stat_bp_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_append {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_append_s {
+                uint64_t reserved_4_63:60;
+                uint64_t force_fcs:1;
+                uint64_t fcs:1;
+                uint64_t pad:1;
+                uint64_t preamble:1;
+        } s;
+        struct cvmx_gmxx_txx_append_s cn30xx;
+        struct cvmx_gmxx_txx_append_s cn31xx;
+        struct cvmx_gmxx_txx_append_s cn38xx;
+        struct cvmx_gmxx_txx_append_s cn38xxp2;
+        struct cvmx_gmxx_txx_append_s cn50xx;
+        struct cvmx_gmxx_txx_append_s cn52xx;
+        struct cvmx_gmxx_txx_append_s cn52xxp1;
+        struct cvmx_gmxx_txx_append_s cn56xx;
+        struct cvmx_gmxx_txx_append_s cn56xxp1;
+        struct cvmx_gmxx_txx_append_s cn58xx;
+        struct cvmx_gmxx_txx_append_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_burst {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_burst_s {
+                uint64_t reserved_16_63:48;
+                uint64_t burst:16;
+        } s;
+        struct cvmx_gmxx_txx_burst_s cn30xx;
+        struct cvmx_gmxx_txx_burst_s cn31xx;
+        struct cvmx_gmxx_txx_burst_s cn38xx;
+        struct cvmx_gmxx_txx_burst_s cn38xxp2;
+        struct cvmx_gmxx_txx_burst_s cn50xx;
+        struct cvmx_gmxx_txx_burst_s cn52xx;
+        struct cvmx_gmxx_txx_burst_s cn52xxp1;
+        struct cvmx_gmxx_txx_burst_s cn56xx;
+        struct cvmx_gmxx_txx_burst_s cn56xxp1;
+        struct cvmx_gmxx_txx_burst_s cn58xx;
+        struct cvmx_gmxx_txx_burst_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_cbfc_xoff {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_cbfc_xoff_s {
+                uint64_t reserved_16_63:48;
+                uint64_t xoff:16;
+        } s;
+        struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx;
+        struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx;
+};
+
+union cvmx_gmxx_txx_cbfc_xon {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_cbfc_xon_s {
+                uint64_t reserved_16_63:48;
+                uint64_t xon:16;
+        } s;
+        struct cvmx_gmxx_txx_cbfc_xon_s cn52xx;
+        struct cvmx_gmxx_txx_cbfc_xon_s cn56xx;
+};
+
+union cvmx_gmxx_txx_clk {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_clk_s {
+                uint64_t reserved_6_63:58;
+                uint64_t clk_cnt:6;
+        } s;
+        struct cvmx_gmxx_txx_clk_s cn30xx;
+        struct cvmx_gmxx_txx_clk_s cn31xx;
+        struct cvmx_gmxx_txx_clk_s cn38xx;
+        struct cvmx_gmxx_txx_clk_s cn38xxp2;
+        struct cvmx_gmxx_txx_clk_s cn50xx;
+        struct cvmx_gmxx_txx_clk_s cn58xx;
+        struct cvmx_gmxx_txx_clk_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_ctl_s {
+                uint64_t reserved_2_63:62;
+                uint64_t xsdef_en:1;
+                uint64_t xscol_en:1;
+        } s;
+        struct cvmx_gmxx_txx_ctl_s cn30xx;
+        struct cvmx_gmxx_txx_ctl_s cn31xx;
+        struct cvmx_gmxx_txx_ctl_s cn38xx;
+        struct cvmx_gmxx_txx_ctl_s cn38xxp2;
+        struct cvmx_gmxx_txx_ctl_s cn50xx;
+        struct cvmx_gmxx_txx_ctl_s cn52xx;
+        struct cvmx_gmxx_txx_ctl_s cn52xxp1;
+        struct cvmx_gmxx_txx_ctl_s cn56xx;
+        struct cvmx_gmxx_txx_ctl_s cn56xxp1;
+        struct cvmx_gmxx_txx_ctl_s cn58xx;
+        struct cvmx_gmxx_txx_ctl_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_min_pkt {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_min_pkt_s {
+                uint64_t reserved_8_63:56;
+                uint64_t min_size:8;
+        } s;
+        struct cvmx_gmxx_txx_min_pkt_s cn30xx;
+        struct cvmx_gmxx_txx_min_pkt_s cn31xx;
+        struct cvmx_gmxx_txx_min_pkt_s cn38xx;
+        struct cvmx_gmxx_txx_min_pkt_s cn38xxp2;
+        struct cvmx_gmxx_txx_min_pkt_s cn50xx;
+        struct cvmx_gmxx_txx_min_pkt_s cn52xx;
+        struct cvmx_gmxx_txx_min_pkt_s cn52xxp1;
+        struct cvmx_gmxx_txx_min_pkt_s cn56xx;
+        struct cvmx_gmxx_txx_min_pkt_s cn56xxp1;
+        struct cvmx_gmxx_txx_min_pkt_s cn58xx;
+        struct cvmx_gmxx_txx_min_pkt_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_pause_pkt_interval {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s {
+                uint64_t reserved_16_63:48;
+                uint64_t interval:16;
+        } s;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
+        struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_pause_pkt_time {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_pause_pkt_time_s {
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+        } s;
+        struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
+        struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
+        struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
+        struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
+        struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
+        struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
+        struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
+        struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
+        struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
+        struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
+        struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_pause_togo {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_pause_togo_s {
+                uint64_t reserved_32_63:32;
+                uint64_t msg_time:16;
+                uint64_t time:16;
+        } s;
+        struct cvmx_gmxx_txx_pause_togo_cn30xx {
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+        } cn30xx;
+        struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
+        struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
+        struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
+        struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
+        struct cvmx_gmxx_txx_pause_togo_s cn52xx;
+        struct cvmx_gmxx_txx_pause_togo_s cn52xxp1;
+        struct cvmx_gmxx_txx_pause_togo_s cn56xx;
+        struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
+        struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
+        struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
+};
+
+union cvmx_gmxx_txx_pause_zero {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_pause_zero_s {
+                uint64_t reserved_1_63:63;
+                uint64_t send:1;
+        } s;
+        struct cvmx_gmxx_txx_pause_zero_s cn30xx;
+        struct cvmx_gmxx_txx_pause_zero_s cn31xx;
+        struct cvmx_gmxx_txx_pause_zero_s cn38xx;
+        struct cvmx_gmxx_txx_pause_zero_s cn38xxp2;
+        struct cvmx_gmxx_txx_pause_zero_s cn50xx;
+        struct cvmx_gmxx_txx_pause_zero_s cn52xx;
+        struct cvmx_gmxx_txx_pause_zero_s cn52xxp1;
+        struct cvmx_gmxx_txx_pause_zero_s cn56xx;
+        struct cvmx_gmxx_txx_pause_zero_s cn56xxp1;
+        struct cvmx_gmxx_txx_pause_zero_s cn58xx;
+        struct cvmx_gmxx_txx_pause_zero_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_sgmii_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_sgmii_ctl_s {
+                uint64_t reserved_1_63:63;
+                uint64_t align:1;
+        } s;
+        struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx;
+        struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1;
+        struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx;
+        struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1;
+};
+
+union cvmx_gmxx_txx_slot {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_slot_s {
+                uint64_t reserved_10_63:54;
+                uint64_t slot:10;
+        } s;
+        struct cvmx_gmxx_txx_slot_s cn30xx;
+        struct cvmx_gmxx_txx_slot_s cn31xx;
+        struct cvmx_gmxx_txx_slot_s cn38xx;
+        struct cvmx_gmxx_txx_slot_s cn38xxp2;
+        struct cvmx_gmxx_txx_slot_s cn50xx;
+        struct cvmx_gmxx_txx_slot_s cn52xx;
+        struct cvmx_gmxx_txx_slot_s cn52xxp1;
+        struct cvmx_gmxx_txx_slot_s cn56xx;
+        struct cvmx_gmxx_txx_slot_s cn56xxp1;
+        struct cvmx_gmxx_txx_slot_s cn58xx;
+        struct cvmx_gmxx_txx_slot_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_soft_pause {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_soft_pause_s {
+                uint64_t reserved_16_63:48;
+                uint64_t time:16;
+        } s;
+        struct cvmx_gmxx_txx_soft_pause_s cn30xx;
+        struct cvmx_gmxx_txx_soft_pause_s cn31xx;
+        struct cvmx_gmxx_txx_soft_pause_s cn38xx;
+        struct cvmx_gmxx_txx_soft_pause_s cn38xxp2;
+        struct cvmx_gmxx_txx_soft_pause_s cn50xx;
+        struct cvmx_gmxx_txx_soft_pause_s cn52xx;
+        struct cvmx_gmxx_txx_soft_pause_s cn52xxp1;
+        struct cvmx_gmxx_txx_soft_pause_s cn56xx;
+        struct cvmx_gmxx_txx_soft_pause_s cn56xxp1;
+        struct cvmx_gmxx_txx_soft_pause_s cn58xx;
+        struct cvmx_gmxx_txx_soft_pause_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_stat0 {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_stat0_s {
+                uint64_t xsdef:32;
+                uint64_t xscol:32;
+        } s;
+        struct cvmx_gmxx_txx_stat0_s cn30xx;
+        struct cvmx_gmxx_txx_stat0_s cn31xx;
+        struct cvmx_gmxx_txx_stat0_s cn38xx;
+        struct cvmx_gmxx_txx_stat0_s cn38xxp2;
+        struct cvmx_gmxx_txx_stat0_s cn50xx;
+        struct cvmx_gmxx_txx_stat0_s cn52xx;
+        struct cvmx_gmxx_txx_stat0_s cn52xxp1;
+        struct cvmx_gmxx_txx_stat0_s cn56xx;
+        struct cvmx_gmxx_txx_stat0_s cn56xxp1;
+        struct cvmx_gmxx_txx_stat0_s cn58xx;
+        struct cvmx_gmxx_txx_stat0_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_stat1 {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_stat1_s {
+                uint64_t scol:32;
+                uint64_t mcol:32;
+        } s;
+        struct cvmx_gmxx_txx_stat1_s cn30xx;
+        struct cvmx_gmxx_txx_stat1_s cn31xx;
+        struct cvmx_gmxx_txx_stat1_s cn38xx;
+        struct cvmx_gmxx_txx_stat1_s cn38xxp2;
+        struct cvmx_gmxx_txx_stat1_s cn50xx;
+        struct cvmx_gmxx_txx_stat1_s cn52xx;
+        struct cvmx_gmxx_txx_stat1_s cn52xxp1;
+        struct cvmx_gmxx_txx_stat1_s cn56xx;
+        struct cvmx_gmxx_txx_stat1_s cn56xxp1;
+        struct cvmx_gmxx_txx_stat1_s cn58xx;
+        struct cvmx_gmxx_txx_stat1_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_stat2 {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_stat2_s {
+                uint64_t reserved_48_63:16;
+                uint64_t octs:48;
+        } s;
+        struct cvmx_gmxx_txx_stat2_s cn30xx;
+        struct cvmx_gmxx_txx_stat2_s cn31xx;
+        struct cvmx_gmxx_txx_stat2_s cn38xx;
+        struct cvmx_gmxx_txx_stat2_s cn38xxp2;
+        struct cvmx_gmxx_txx_stat2_s cn50xx;
+        struct cvmx_gmxx_txx_stat2_s cn52xx;
+        struct cvmx_gmxx_txx_stat2_s cn52xxp1;
+        struct cvmx_gmxx_txx_stat2_s cn56xx;
+        struct cvmx_gmxx_txx_stat2_s cn56xxp1;
+        struct cvmx_gmxx_txx_stat2_s cn58xx;
+        struct cvmx_gmxx_txx_stat2_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_stat3 {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_stat3_s {
+                uint64_t reserved_32_63:32;
+                uint64_t pkts:32;
+        } s;
+        struct cvmx_gmxx_txx_stat3_s cn30xx;
+        struct cvmx_gmxx_txx_stat3_s cn31xx;
+        struct cvmx_gmxx_txx_stat3_s cn38xx;
+        struct cvmx_gmxx_txx_stat3_s cn38xxp2;
+        struct cvmx_gmxx_txx_stat3_s cn50xx;
+        struct cvmx_gmxx_txx_stat3_s cn52xx;
+        struct cvmx_gmxx_txx_stat3_s cn52xxp1;
+        struct cvmx_gmxx_txx_stat3_s cn56xx;
+        struct cvmx_gmxx_txx_stat3_s cn56xxp1;
+        struct cvmx_gmxx_txx_stat3_s cn58xx;
+        struct cvmx_gmxx_txx_stat3_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_stat4 {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_stat4_s {
+                uint64_t hist1:32;
+                uint64_t hist0:32;
+        } s;
+        struct cvmx_gmxx_txx_stat4_s cn30xx;
+        struct cvmx_gmxx_txx_stat4_s cn31xx;
+        struct cvmx_gmxx_txx_stat4_s cn38xx;
+        struct cvmx_gmxx_txx_stat4_s cn38xxp2;
+        struct cvmx_gmxx_txx_stat4_s cn50xx;
+        struct cvmx_gmxx_txx_stat4_s cn52xx;
+        struct cvmx_gmxx_txx_stat4_s cn52xxp1;
+        struct cvmx_gmxx_txx_stat4_s cn56xx;
+        struct cvmx_gmxx_txx_stat4_s cn56xxp1;
+        struct cvmx_gmxx_txx_stat4_s cn58xx;
+        struct cvmx_gmxx_txx_stat4_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_stat5 {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_stat5_s {
+                uint64_t hist3:32;
+                uint64_t hist2:32;
+        } s;
+        struct cvmx_gmxx_txx_stat5_s cn30xx;
+        struct cvmx_gmxx_txx_stat5_s cn31xx;
+        struct cvmx_gmxx_txx_stat5_s cn38xx;
+        struct cvmx_gmxx_txx_stat5_s cn38xxp2;
+        struct cvmx_gmxx_txx_stat5_s cn50xx;
+        struct cvmx_gmxx_txx_stat5_s cn52xx;
+        struct cvmx_gmxx_txx_stat5_s cn52xxp1;
+        struct cvmx_gmxx_txx_stat5_s cn56xx;
+        struct cvmx_gmxx_txx_stat5_s cn56xxp1;
+        struct cvmx_gmxx_txx_stat5_s cn58xx;
+        struct cvmx_gmxx_txx_stat5_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_stat6 {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_stat6_s {
+                uint64_t hist5:32;
+                uint64_t hist4:32;
+        } s;
+        struct cvmx_gmxx_txx_stat6_s cn30xx;
+        struct cvmx_gmxx_txx_stat6_s cn31xx;
+        struct cvmx_gmxx_txx_stat6_s cn38xx;
+        struct cvmx_gmxx_txx_stat6_s cn38xxp2;
+        struct cvmx_gmxx_txx_stat6_s cn50xx;
+        struct cvmx_gmxx_txx_stat6_s cn52xx;
+        struct cvmx_gmxx_txx_stat6_s cn52xxp1;
+        struct cvmx_gmxx_txx_stat6_s cn56xx;
+        struct cvmx_gmxx_txx_stat6_s cn56xxp1;
+        struct cvmx_gmxx_txx_stat6_s cn58xx;
+        struct cvmx_gmxx_txx_stat6_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_stat7 {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_stat7_s {
+                uint64_t hist7:32;
+                uint64_t hist6:32;
+        } s;
+        struct cvmx_gmxx_txx_stat7_s cn30xx;
+        struct cvmx_gmxx_txx_stat7_s cn31xx;
+        struct cvmx_gmxx_txx_stat7_s cn38xx;
+        struct cvmx_gmxx_txx_stat7_s cn38xxp2;
+        struct cvmx_gmxx_txx_stat7_s cn50xx;
+        struct cvmx_gmxx_txx_stat7_s cn52xx;
+        struct cvmx_gmxx_txx_stat7_s cn52xxp1;
+        struct cvmx_gmxx_txx_stat7_s cn56xx;
+        struct cvmx_gmxx_txx_stat7_s cn56xxp1;
+        struct cvmx_gmxx_txx_stat7_s cn58xx;
+        struct cvmx_gmxx_txx_stat7_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_stat8 {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_stat8_s {
+                uint64_t mcst:32;
+                uint64_t bcst:32;
+        } s;
+        struct cvmx_gmxx_txx_stat8_s cn30xx;
+        struct cvmx_gmxx_txx_stat8_s cn31xx;
+        struct cvmx_gmxx_txx_stat8_s cn38xx;
+        struct cvmx_gmxx_txx_stat8_s cn38xxp2;
+        struct cvmx_gmxx_txx_stat8_s cn50xx;
+        struct cvmx_gmxx_txx_stat8_s cn52xx;
+        struct cvmx_gmxx_txx_stat8_s cn52xxp1;
+        struct cvmx_gmxx_txx_stat8_s cn56xx;
+        struct cvmx_gmxx_txx_stat8_s cn56xxp1;
+        struct cvmx_gmxx_txx_stat8_s cn58xx;
+        struct cvmx_gmxx_txx_stat8_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_stat9 {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_stat9_s {
+                uint64_t undflw:32;
+                uint64_t ctl:32;
+        } s;
+        struct cvmx_gmxx_txx_stat9_s cn30xx;
+        struct cvmx_gmxx_txx_stat9_s cn31xx;
+        struct cvmx_gmxx_txx_stat9_s cn38xx;
+        struct cvmx_gmxx_txx_stat9_s cn38xxp2;
+        struct cvmx_gmxx_txx_stat9_s cn50xx;
+        struct cvmx_gmxx_txx_stat9_s cn52xx;
+        struct cvmx_gmxx_txx_stat9_s cn52xxp1;
+        struct cvmx_gmxx_txx_stat9_s cn56xx;
+        struct cvmx_gmxx_txx_stat9_s cn56xxp1;
+        struct cvmx_gmxx_txx_stat9_s cn58xx;
+        struct cvmx_gmxx_txx_stat9_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_stats_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_stats_ctl_s {
+                uint64_t reserved_1_63:63;
+                uint64_t rd_clr:1;
+        } s;
+        struct cvmx_gmxx_txx_stats_ctl_s cn30xx;
+        struct cvmx_gmxx_txx_stats_ctl_s cn31xx;
+        struct cvmx_gmxx_txx_stats_ctl_s cn38xx;
+        struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2;
+        struct cvmx_gmxx_txx_stats_ctl_s cn50xx;
+        struct cvmx_gmxx_txx_stats_ctl_s cn52xx;
+        struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1;
+        struct cvmx_gmxx_txx_stats_ctl_s cn56xx;
+        struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1;
+        struct cvmx_gmxx_txx_stats_ctl_s cn58xx;
+        struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1;
+};
+
+union cvmx_gmxx_txx_thresh {
+        uint64_t u64;
+        struct cvmx_gmxx_txx_thresh_s {
+                uint64_t reserved_9_63:55;
+                uint64_t cnt:9;
+        } s;
+        struct cvmx_gmxx_txx_thresh_cn30xx {
+                uint64_t reserved_7_63:57;
+                uint64_t cnt:7;
+        } cn30xx;
+        struct cvmx_gmxx_txx_thresh_cn30xx cn31xx;
+        struct cvmx_gmxx_txx_thresh_s cn38xx;
+        struct cvmx_gmxx_txx_thresh_s cn38xxp2;
+        struct cvmx_gmxx_txx_thresh_cn30xx cn50xx;
+        struct cvmx_gmxx_txx_thresh_s cn52xx;
+        struct cvmx_gmxx_txx_thresh_s cn52xxp1;
+        struct cvmx_gmxx_txx_thresh_s cn56xx;
+        struct cvmx_gmxx_txx_thresh_s cn56xxp1;
+        struct cvmx_gmxx_txx_thresh_s cn58xx;
+        struct cvmx_gmxx_txx_thresh_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_bp {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_bp_s {
+                uint64_t reserved_4_63:60;
+                uint64_t bp:4;
+        } s;
+        struct cvmx_gmxx_tx_bp_cn30xx {
+                uint64_t reserved_3_63:61;
+                uint64_t bp:3;
+        } cn30xx;
+        struct cvmx_gmxx_tx_bp_cn30xx cn31xx;
+        struct cvmx_gmxx_tx_bp_s cn38xx;
+        struct cvmx_gmxx_tx_bp_s cn38xxp2;
+        struct cvmx_gmxx_tx_bp_cn30xx cn50xx;
+        struct cvmx_gmxx_tx_bp_s cn52xx;
+        struct cvmx_gmxx_tx_bp_s cn52xxp1;
+        struct cvmx_gmxx_tx_bp_s cn56xx;
+        struct cvmx_gmxx_tx_bp_s cn56xxp1;
+        struct cvmx_gmxx_tx_bp_s cn58xx;
+        struct cvmx_gmxx_tx_bp_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_clk_mskx {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_clk_mskx_s {
+                uint64_t reserved_1_63:63;
+                uint64_t msk:1;
+        } s;
+        struct cvmx_gmxx_tx_clk_mskx_s cn30xx;
+        struct cvmx_gmxx_tx_clk_mskx_s cn50xx;
+};
+
+union cvmx_gmxx_tx_col_attempt {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_col_attempt_s {
+                uint64_t reserved_5_63:59;
+                uint64_t limit:5;
+        } s;
+        struct cvmx_gmxx_tx_col_attempt_s cn30xx;
+        struct cvmx_gmxx_tx_col_attempt_s cn31xx;
+        struct cvmx_gmxx_tx_col_attempt_s cn38xx;
+        struct cvmx_gmxx_tx_col_attempt_s cn38xxp2;
+        struct cvmx_gmxx_tx_col_attempt_s cn50xx;
+        struct cvmx_gmxx_tx_col_attempt_s cn52xx;
+        struct cvmx_gmxx_tx_col_attempt_s cn52xxp1;
+        struct cvmx_gmxx_tx_col_attempt_s cn56xx;
+        struct cvmx_gmxx_tx_col_attempt_s cn56xxp1;
+        struct cvmx_gmxx_tx_col_attempt_s cn58xx;
+        struct cvmx_gmxx_tx_col_attempt_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_corrupt {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_corrupt_s {
+                uint64_t reserved_4_63:60;
+                uint64_t corrupt:4;
+        } s;
+        struct cvmx_gmxx_tx_corrupt_cn30xx {
+                uint64_t reserved_3_63:61;
+                uint64_t corrupt:3;
+        } cn30xx;
+        struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx;
+        struct cvmx_gmxx_tx_corrupt_s cn38xx;
+        struct cvmx_gmxx_tx_corrupt_s cn38xxp2;
+        struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx;
+        struct cvmx_gmxx_tx_corrupt_s cn52xx;
+        struct cvmx_gmxx_tx_corrupt_s cn52xxp1;
+        struct cvmx_gmxx_tx_corrupt_s cn56xx;
+        struct cvmx_gmxx_tx_corrupt_s cn56xxp1;
+        struct cvmx_gmxx_tx_corrupt_s cn58xx;
+        struct cvmx_gmxx_tx_corrupt_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_hg2_reg1 {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_hg2_reg1_s {
+                uint64_t reserved_16_63:48;
+                uint64_t tx_xof:16;
+        } s;
+        struct cvmx_gmxx_tx_hg2_reg1_s cn52xx;
+        struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1;
+        struct cvmx_gmxx_tx_hg2_reg1_s cn56xx;
+};
+
+union cvmx_gmxx_tx_hg2_reg2 {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_hg2_reg2_s {
+                uint64_t reserved_16_63:48;
+                uint64_t tx_xon:16;
+        } s;
+        struct cvmx_gmxx_tx_hg2_reg2_s cn52xx;
+        struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1;
+        struct cvmx_gmxx_tx_hg2_reg2_s cn56xx;
+};
+
+union cvmx_gmxx_tx_ifg {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_ifg_s {
+                uint64_t reserved_8_63:56;
+                uint64_t ifg2:4;
+                uint64_t ifg1:4;
+        } s;
+        struct cvmx_gmxx_tx_ifg_s cn30xx;
+        struct cvmx_gmxx_tx_ifg_s cn31xx;
+        struct cvmx_gmxx_tx_ifg_s cn38xx;
+        struct cvmx_gmxx_tx_ifg_s cn38xxp2;
+        struct cvmx_gmxx_tx_ifg_s cn50xx;
+        struct cvmx_gmxx_tx_ifg_s cn52xx;
+        struct cvmx_gmxx_tx_ifg_s cn52xxp1;
+        struct cvmx_gmxx_tx_ifg_s cn56xx;
+        struct cvmx_gmxx_tx_ifg_s cn56xxp1;
+        struct cvmx_gmxx_tx_ifg_s cn58xx;
+        struct cvmx_gmxx_tx_ifg_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_int_en {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_int_en_s {
+                uint64_t reserved_20_63:44;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t ncb_nxa:1;
+                uint64_t pko_nxa:1;
+        } s;
+        struct cvmx_gmxx_tx_int_en_cn30xx {
+                uint64_t reserved_19_63:45;
+                uint64_t late_col:3;
+                uint64_t reserved_15_15:1;
+                uint64_t xsdef:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xscol:3;
+                uint64_t reserved_5_7:3;
+                uint64_t undflw:3;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn30xx;
+        struct cvmx_gmxx_tx_int_en_cn31xx {
+                uint64_t reserved_15_63:49;
+                uint64_t xsdef:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xscol:3;
+                uint64_t reserved_5_7:3;
+                uint64_t undflw:3;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn31xx;
+        struct cvmx_gmxx_tx_int_en_s cn38xx;
+        struct cvmx_gmxx_tx_int_en_cn38xxp2 {
+                uint64_t reserved_16_63:48;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t ncb_nxa:1;
+                uint64_t pko_nxa:1;
+        } cn38xxp2;
+        struct cvmx_gmxx_tx_int_en_cn30xx cn50xx;
+        struct cvmx_gmxx_tx_int_en_cn52xx {
+                uint64_t reserved_20_63:44;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn52xx;
+        struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1;
+        struct cvmx_gmxx_tx_int_en_cn52xx cn56xx;
+        struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1;
+        struct cvmx_gmxx_tx_int_en_s cn58xx;
+        struct cvmx_gmxx_tx_int_en_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_int_reg {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_int_reg_s {
+                uint64_t reserved_20_63:44;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t ncb_nxa:1;
+                uint64_t pko_nxa:1;
+        } s;
+        struct cvmx_gmxx_tx_int_reg_cn30xx {
+                uint64_t reserved_19_63:45;
+                uint64_t late_col:3;
+                uint64_t reserved_15_15:1;
+                uint64_t xsdef:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xscol:3;
+                uint64_t reserved_5_7:3;
+                uint64_t undflw:3;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn30xx;
+        struct cvmx_gmxx_tx_int_reg_cn31xx {
+                uint64_t reserved_15_63:49;
+                uint64_t xsdef:3;
+                uint64_t reserved_11_11:1;
+                uint64_t xscol:3;
+                uint64_t reserved_5_7:3;
+                uint64_t undflw:3;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn31xx;
+        struct cvmx_gmxx_tx_int_reg_s cn38xx;
+        struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
+                uint64_t reserved_16_63:48;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t ncb_nxa:1;
+                uint64_t pko_nxa:1;
+        } cn38xxp2;
+        struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx;
+        struct cvmx_gmxx_tx_int_reg_cn52xx {
+                uint64_t reserved_20_63:44;
+                uint64_t late_col:4;
+                uint64_t xsdef:4;
+                uint64_t xscol:4;
+                uint64_t reserved_6_7:2;
+                uint64_t undflw:4;
+                uint64_t reserved_1_1:1;
+                uint64_t pko_nxa:1;
+        } cn52xx;
+        struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1;
+        struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx;
+        struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1;
+        struct cvmx_gmxx_tx_int_reg_s cn58xx;
+        struct cvmx_gmxx_tx_int_reg_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_jam {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_jam_s {
+                uint64_t reserved_8_63:56;
+                uint64_t jam:8;
+        } s;
+        struct cvmx_gmxx_tx_jam_s cn30xx;
+        struct cvmx_gmxx_tx_jam_s cn31xx;
+        struct cvmx_gmxx_tx_jam_s cn38xx;
+        struct cvmx_gmxx_tx_jam_s cn38xxp2;
+        struct cvmx_gmxx_tx_jam_s cn50xx;
+        struct cvmx_gmxx_tx_jam_s cn52xx;
+        struct cvmx_gmxx_tx_jam_s cn52xxp1;
+        struct cvmx_gmxx_tx_jam_s cn56xx;
+        struct cvmx_gmxx_tx_jam_s cn56xxp1;
+        struct cvmx_gmxx_tx_jam_s cn58xx;
+        struct cvmx_gmxx_tx_jam_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_lfsr {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_lfsr_s {
+                uint64_t reserved_16_63:48;
+                uint64_t lfsr:16;
+        } s;
+        struct cvmx_gmxx_tx_lfsr_s cn30xx;
+        struct cvmx_gmxx_tx_lfsr_s cn31xx;
+        struct cvmx_gmxx_tx_lfsr_s cn38xx;
+        struct cvmx_gmxx_tx_lfsr_s cn38xxp2;
+        struct cvmx_gmxx_tx_lfsr_s cn50xx;
+        struct cvmx_gmxx_tx_lfsr_s cn52xx;
+        struct cvmx_gmxx_tx_lfsr_s cn52xxp1;
+        struct cvmx_gmxx_tx_lfsr_s cn56xx;
+        struct cvmx_gmxx_tx_lfsr_s cn56xxp1;
+        struct cvmx_gmxx_tx_lfsr_s cn58xx;
+        struct cvmx_gmxx_tx_lfsr_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_ovr_bp {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_ovr_bp_s {
+                uint64_t reserved_48_63:16;
+                uint64_t tx_prt_bp:16;
+                uint64_t reserved_12_31:20;
+                uint64_t en:4;
+                uint64_t bp:4;
+                uint64_t ign_full:4;
+        } s;
+        struct cvmx_gmxx_tx_ovr_bp_cn30xx {
+                uint64_t reserved_11_63:53;
+                uint64_t en:3;
+                uint64_t reserved_7_7:1;
+                uint64_t bp:3;
+                uint64_t reserved_3_3:1;
+                uint64_t ign_full:3;
+        } cn30xx;
+        struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx;
+        struct cvmx_gmxx_tx_ovr_bp_cn38xx {
+                uint64_t reserved_12_63:52;
+                uint64_t en:4;
+                uint64_t bp:4;
+                uint64_t ign_full:4;
+        } cn38xx;
+        struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2;
+        struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx;
+        struct cvmx_gmxx_tx_ovr_bp_s cn52xx;
+        struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1;
+        struct cvmx_gmxx_tx_ovr_bp_s cn56xx;
+        struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1;
+        struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx;
+        struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1;
+};
+
+union cvmx_gmxx_tx_pause_pkt_dmac {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s {
+                uint64_t reserved_48_63:16;
+                uint64_t dmac:48;
+        } s;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
+        struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_pause_pkt_type {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_pause_pkt_type_s {
+                uint64_t reserved_16_63:48;
+                uint64_t type:16;
+        } s;
+        struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;
+        struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;
+        struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;
+        struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;
+        struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;
+        struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;
+        struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;
+        struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;
+        struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
+        struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
+        struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_prts {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_prts_s {
+                uint64_t reserved_5_63:59;
+                uint64_t prts:5;
+        } s;
+        struct cvmx_gmxx_tx_prts_s cn30xx;
+        struct cvmx_gmxx_tx_prts_s cn31xx;
+        struct cvmx_gmxx_tx_prts_s cn38xx;
+        struct cvmx_gmxx_tx_prts_s cn38xxp2;
+        struct cvmx_gmxx_tx_prts_s cn50xx;
+        struct cvmx_gmxx_tx_prts_s cn52xx;
+        struct cvmx_gmxx_tx_prts_s cn52xxp1;
+        struct cvmx_gmxx_tx_prts_s cn56xx;
+        struct cvmx_gmxx_tx_prts_s cn56xxp1;
+        struct cvmx_gmxx_tx_prts_s cn58xx;
+        struct cvmx_gmxx_tx_prts_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_spi_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_spi_ctl_s {
+                uint64_t reserved_2_63:62;
+                uint64_t tpa_clr:1;
+                uint64_t cont_pkt:1;
+        } s;
+        struct cvmx_gmxx_tx_spi_ctl_s cn38xx;
+        struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2;
+        struct cvmx_gmxx_tx_spi_ctl_s cn58xx;
+        struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_spi_drain {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_spi_drain_s {
+                uint64_t reserved_16_63:48;
+                uint64_t drain:16;
+        } s;
+        struct cvmx_gmxx_tx_spi_drain_s cn38xx;
+        struct cvmx_gmxx_tx_spi_drain_s cn58xx;
+        struct cvmx_gmxx_tx_spi_drain_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_spi_max {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_spi_max_s {
+                uint64_t reserved_23_63:41;
+                uint64_t slice:7;
+                uint64_t max2:8;
+                uint64_t max1:8;
+        } s;
+        struct cvmx_gmxx_tx_spi_max_cn38xx {
+                uint64_t reserved_16_63:48;
+                uint64_t max2:8;
+                uint64_t max1:8;
+        } cn38xx;
+        struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2;
+        struct cvmx_gmxx_tx_spi_max_s cn58xx;
+        struct cvmx_gmxx_tx_spi_max_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_spi_roundx {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_spi_roundx_s {
+                uint64_t reserved_16_63:48;
+                uint64_t round:16;
+        } s;
+        struct cvmx_gmxx_tx_spi_roundx_s cn58xx;
+        struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_spi_thresh {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_spi_thresh_s {
+                uint64_t reserved_6_63:58;
+                uint64_t thresh:6;
+        } s;
+        struct cvmx_gmxx_tx_spi_thresh_s cn38xx;
+        struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2;
+        struct cvmx_gmxx_tx_spi_thresh_s cn58xx;
+        struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1;
+};
+
+union cvmx_gmxx_tx_xaui_ctl {
+        uint64_t u64;
+        struct cvmx_gmxx_tx_xaui_ctl_s {
+                uint64_t reserved_11_63:53;
+                uint64_t hg_pause_hgi:2;
+                uint64_t hg_en:1;
+                uint64_t reserved_7_7:1;
+                uint64_t ls_byp:1;
+                uint64_t ls:2;
+                uint64_t reserved_2_3:2;
+                uint64_t uni_en:1;
+                uint64_t dic_en:1;
+        } s;
+        struct cvmx_gmxx_tx_xaui_ctl_s cn52xx;
+        struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1;
+        struct cvmx_gmxx_tx_xaui_ctl_s cn56xx;
+        struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1;
+};
+
+union cvmx_gmxx_xaui_ext_loopback {
+        uint64_t u64;
+        struct cvmx_gmxx_xaui_ext_loopback_s {
+                uint64_t reserved_5_63:59;
+                uint64_t en:1;
+                uint64_t thresh:4;
+        } s;
+        struct cvmx_gmxx_xaui_ext_loopback_s cn52xx;
+        struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
+        struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
+        struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-helper-board.c b/drivers/staging/octeon/cvmx-helper-board.c
new file mode 100644
index 000000000000..3085e38a6f99
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-board.c
@@ -0,0 +1,706 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * Helper functions to abstract board specific data about
+ * network ports from the rest of the cvmx-helper files.
+ */
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-bootinfo.h>
+
+#include "cvmx-config.h"
+
+#include "cvmx-mdio.h"
+
+#include "cvmx-helper.h"
+#include "cvmx-helper-util.h"
+#include "cvmx-helper-board.h"
+
+#include "cvmx-gmxx-defs.h"
+#include "cvmx-asxx-defs.h"
+
+/**
+ * cvmx_override_board_link_get(int ipd_port) is a function
+ * pointer. It is meant to allow customization of the process of
+ * talking to a PHY to determine link speed. It is called every
+ * time a PHY must be polled for link status. Users should set
+ * this pointer to a function before calling any cvmx-helper
+ * operations.
+ */
+cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) =
+    NULL;
+
+/**
+ * Return the MII PHY address associated with the given IPD
+ * port. A result of -1 means there isn't a MII capable PHY
+ * connected to this port. On chips supporting multiple MII
+ * busses the bus number is encoded in bits <15:8>.
+ *
+ * This function must be modified for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It replies on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @ipd_port: Octeon IPD port to get the MII address for.
+ *
+ * Returns MII PHY address and bus number or -1.
+ */
+int cvmx_helper_board_get_mii_address(int ipd_port)
+{
+        switch (cvmx_sysinfo_get()->board_type) {
+        case CVMX_BOARD_TYPE_SIM:
+                /* Simulator doesn't have MII */
+                return -1;
+        case CVMX_BOARD_TYPE_EBT3000:
+        case CVMX_BOARD_TYPE_EBT5800:
+        case CVMX_BOARD_TYPE_THUNDER:
+        case CVMX_BOARD_TYPE_NICPRO2:
+                /* Interface 0 is SPI4, interface 1 is RGMII */
+                if ((ipd_port >= 16) && (ipd_port < 20))
+                        return ipd_port - 16;
+                else
+                        return -1;
+        case CVMX_BOARD_TYPE_KODAMA:
+        case CVMX_BOARD_TYPE_EBH3100:
+        case CVMX_BOARD_TYPE_HIKARI:
+        case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+        case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+        case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
+                /*
+                 * Port 0 is WAN connected to a PHY, Port 1 is GMII
+                 * connected to a switch
+                 */
+                if (ipd_port == 0)
+                        return 4;
+                else if (ipd_port == 1)
+                        return 9;
+                else
+                        return -1;
+        case CVMX_BOARD_TYPE_NAC38:
+                /* Board has 8 RGMII ports PHYs are 0-7 */
+                if ((ipd_port >= 0) && (ipd_port < 4))
+                        return ipd_port;
+                else if ((ipd_port >= 16) && (ipd_port < 20))
+                        return ipd_port - 16 + 4;
+                else
+                        return -1;
+        case CVMX_BOARD_TYPE_EBH3000:
+                /* Board has dual SPI4 and no PHYs */
+                return -1;
+        case CVMX_BOARD_TYPE_EBH5200:
+        case CVMX_BOARD_TYPE_EBH5201:
+        case CVMX_BOARD_TYPE_EBT5200:
+                /*
+                 * Board has 4 SGMII ports. The PHYs start right after the MII
+                 * ports MII0 = 0, MII1 = 1, SGMII = 2-5.
+                 */
+                if ((ipd_port >= 0) && (ipd_port < 4))
+                        return ipd_port + 2;
+                else
+                        return -1;
+        case CVMX_BOARD_TYPE_EBH5600:
+        case CVMX_BOARD_TYPE_EBH5601:
+        case CVMX_BOARD_TYPE_EBH5610:
+                /*
+                 * Board has 8 SGMII ports. 4 connect out, two connect
+                 * to a switch, and 2 loop to each other
+                 */
+                if ((ipd_port >= 0) && (ipd_port < 4))
+                        return ipd_port + 1;
+                else
+                        return -1;
+        case CVMX_BOARD_TYPE_CUST_NB5:
+                if (ipd_port == 2)
+                        return 4;
+                else
+                        return -1;
+        case CVMX_BOARD_TYPE_NIC_XLE_4G:
+                /* Board has 4 SGMII ports. connected QLM3(interface 1) */
+                if ((ipd_port >= 16) && (ipd_port < 20))
+                        return ipd_port - 16 + 1;
+                else
+                        return -1;
+        case CVMX_BOARD_TYPE_BBGW_REF:
+                /*
+                 * No PHYs are connected to Octeon, everything is
+                 * through switch.
+                 */
+                return -1;
+        }
+
+        /* Some unknown board. Somebody forgot to update this function... */
+        cvmx_dprintf
+            ("cvmx_helper_board_get_mii_address: Unknown board type %d\n",
+             cvmx_sysinfo_get()->board_type);
+        return -1;
+}
+
+/**
+ * This function is the board specific method of determining an
+ * ethernet ports link speed. Most Octeon boards have Marvell PHYs
+ * and are handled by the fall through case. This function must be
+ * updated for boards that don't have the normal Marvell PHYs.
+ *
+ * This function must be modified for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relies on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @ipd_port: IPD input port associated with the port we want to get link
+ *                 status for.
+ *
+ * Returns The ports link status. If the link isn't fully resolved, this must
+ *         return zero.
+ */
+cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
+{
+        cvmx_helper_link_info_t result;
+        int phy_addr;
+        int is_broadcom_phy = 0;
+
+        /* Give the user a chance to override the processing of this function */
+        if (cvmx_override_board_link_get)
+                return cvmx_override_board_link_get(ipd_port);
+
+        /* Unless we fix it later, all links are defaulted to down */
+        result.u64 = 0;
+
+        /*
+         * This switch statement should handle all ports that either don't use
+         * Marvell PHYS, or don't support in-band status.
+         */
+        switch (cvmx_sysinfo_get()->board_type) {
+        case CVMX_BOARD_TYPE_SIM:
+                /* The simulator gives you a simulated 1Gbps full duplex link */
+                result.s.link_up = 1;
+                result.s.full_duplex = 1;
+                result.s.speed = 1000;
+                return result;
+        case CVMX_BOARD_TYPE_EBH3100:
+        case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
+        case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+        case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
+                /* Port 1 on these boards is always Gigabit */
+                if (ipd_port == 1) {
+                        result.s.link_up = 1;
+                        result.s.full_duplex = 1;
+                        result.s.speed = 1000;
+                        return result;
+                }
+                /* Fall through to the generic code below */
+                break;
+        case CVMX_BOARD_TYPE_CUST_NB5:
+                /* Port 1 on these boards is always Gigabit */
+                if (ipd_port == 1) {
+                        result.s.link_up = 1;
+                        result.s.full_duplex = 1;
+                        result.s.speed = 1000;
+                        return result;
+                } else          /* The other port uses a broadcom PHY */
+                        is_broadcom_phy = 1;
+                break;
+        case CVMX_BOARD_TYPE_BBGW_REF:
+                /* Port 1 on these boards is always Gigabit */
+                if (ipd_port == 2) {
+                        /* Port 2 is not hooked up */
+                        result.u64 = 0;
+                        return result;
+                } else {
+                        /* Ports 0 and 1 connect to the switch */
+                        result.s.link_up = 1;
+                        result.s.full_duplex = 1;
+                        result.s.speed = 1000;
+                        return result;
+                }
+                break;
+        }
+
+        phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
+        if (phy_addr != -1) {
+                if (is_broadcom_phy) {
+                        /*
+                         * Below we are going to read SMI/MDIO
+                         * register 0x19 which works on Broadcom
+                         * parts
+                         */
+                        int phy_status =
+                            cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                           0x19);
+                        switch ((phy_status >> 8) & 0x7) {
+                        case 0:
+                                result.u64 = 0;
+                                break;
+                        case 1:
+                                result.s.link_up = 1;
+                                result.s.full_duplex = 0;
+                                result.s.speed = 10;
+                                break;
+                        case 2:
+                                result.s.link_up = 1;
+                                result.s.full_duplex = 1;
+                                result.s.speed = 10;
+                                break;
+                        case 3:
+                                result.s.link_up = 1;
+                                result.s.full_duplex = 0;
+                                result.s.speed = 100;
+                                break;
+                        case 4:
+                                result.s.link_up = 1;
+                                result.s.full_duplex = 1;
+                                result.s.speed = 100;
+                                break;
+                        case 5:
+                                result.s.link_up = 1;
+                                result.s.full_duplex = 1;
+                                result.s.speed = 100;
+                                break;
+                        case 6:
+                                result.s.link_up = 1;
+                                result.s.full_duplex = 0;
+                                result.s.speed = 1000;
+                                break;
+                        case 7:
+                                result.s.link_up = 1;
+                                result.s.full_duplex = 1;
+                                result.s.speed = 1000;
+                                break;
+                        }
+                } else {
+                        /*
+                         * This code assumes we are using a Marvell
+                         * Gigabit PHY. All the speed information can
+                         * be read from register 17 in one
+                         * go. Somebody using a different PHY will
+                         * need to handle it above in the board
+                         * specific area.
+                         */
+                        int phy_status =
+                            cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
+
+                        /*
+                         * If the resolve bit 11 isn't set, see if
+                         * autoneg is turned off (bit 12, reg 0). The
+                         * resolve bit doesn't get set properly when
+                         * autoneg is off, so force it.
+                         */
+                        if ((phy_status & (1 << 11)) == 0) {
+                                int auto_status =
+                                    cvmx_mdio_read(phy_addr >> 8,
+                                                   phy_addr & 0xff, 0);
+                                if ((auto_status & (1 << 12)) == 0)
+                                        phy_status |= 1 << 11;
+                        }
+
+                        /*
+                         * Only return a link if the PHY has finished
+                         * auto negotiation and set the resolved bit
+                         * (bit 11)
+                         */
+                        if (phy_status & (1 << 11)) {
+                                result.s.link_up = 1;
+                                result.s.full_duplex = ((phy_status >> 13) & 1);
+                                switch ((phy_status >> 14) & 3) {
+                                case 0: /* 10 Mbps */
+                                        result.s.speed = 10;
+                                        break;
+                                case 1: /* 100 Mbps */
+                                        result.s.speed = 100;
+                                        break;
+                                case 2: /* 1 Gbps */
+                                        result.s.speed = 1000;
+                                        break;
+                                case 3: /* Illegal */
+                                        result.u64 = 0;
+                                        break;
+                                }
+                        }
+                }
+        } else if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
+                   || OCTEON_IS_MODEL(OCTEON_CN58XX)
+                   || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                /*
+                 * We don't have a PHY address, so attempt to use
+                 * in-band status. It is really important that boards
+                 * not supporting in-band status never get
+                 * here. Reading broken in-band status tends to do bad
+                 * things
+                 */
+                union cvmx_gmxx_rxx_rx_inbnd inband_status;
+                int interface = cvmx_helper_get_interface_num(ipd_port);
+                int index = cvmx_helper_get_interface_index_num(ipd_port);
+                inband_status.u64 =
+                    cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface));
+
+                result.s.link_up = inband_status.s.status;
+                result.s.full_duplex = inband_status.s.duplex;
+                switch (inband_status.s.speed) {
+                case 0: /* 10 Mbps */
+                        result.s.speed = 10;
+                        break;
+                case 1: /* 100 Mbps */
+                        result.s.speed = 100;
+                        break;
+                case 2: /* 1 Gbps */
+                        result.s.speed = 1000;
+                        break;
+                case 3: /* Illegal */
+                        result.u64 = 0;
+                        break;
+                }
+        } else {
+                /*
+                 * We don't have a PHY address and we don't have
+                 * in-band status. There is no way to determine the
+                 * link speed. Return down assuming this port isn't
+                 * wired
+                 */
+                result.u64 = 0;
+        }
+
+        /* If link is down, return all fields as zero. */
+        if (!result.s.link_up)
+                result.u64 = 0;
+
+        return result;
+}
+
+/**
+ * This function as a board specific method of changing the PHY
+ * speed, duplex, and auto-negotiation. This programs the PHY and
+ * not Octeon. This can be used to force Octeon's links to
+ * specific settings.
+ *
+ * @phy_addr:  The address of the PHY to program
+ * @enable_autoneg:
+ *                  Non zero if you want to enable auto-negotiation.
+ * @link_info: Link speed to program. If the speed is zero and auto-negotiation
+ *                  is enabled, all possible negotiation speeds are advertised.
+ *
+ * Returns Zero on success, negative on failure
+ */
+int cvmx_helper_board_link_set_phy(int phy_addr,
+                                   cvmx_helper_board_set_phy_link_flags_types_t
+                                   link_flags,
+                                   cvmx_helper_link_info_t link_info)
+{
+
+        /* Set the flow control settings based on link_flags */
+        if ((link_flags & set_phy_link_flags_flow_control_mask) !=
+            set_phy_link_flags_flow_control_dont_touch) {
+                cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
+                reg_autoneg_adver.u16 =
+                    cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                   CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
+                reg_autoneg_adver.s.asymmetric_pause =
+                    (link_flags & set_phy_link_flags_flow_control_mask) ==
+                    set_phy_link_flags_flow_control_enable;
+                reg_autoneg_adver.s.pause =
+                    (link_flags & set_phy_link_flags_flow_control_mask) ==
+                    set_phy_link_flags_flow_control_enable;
+                cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
+                                CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
+                                reg_autoneg_adver.u16);
+        }
+
+        /* If speed isn't set and autoneg is on advertise all supported modes */
+        if ((link_flags & set_phy_link_flags_autoneg)
+            && (link_info.s.speed == 0)) {
+                cvmx_mdio_phy_reg_control_t reg_control;
+                cvmx_mdio_phy_reg_status_t reg_status;
+                cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
+                cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
+                cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
+
+                reg_status.u16 =
+                    cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                   CVMX_MDIO_PHY_REG_STATUS);
+                reg_autoneg_adver.u16 =
+                    cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                   CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
+                reg_autoneg_adver.s.advert_100base_t4 =
+                    reg_status.s.capable_100base_t4;
+                reg_autoneg_adver.s.advert_10base_tx_full =
+                    reg_status.s.capable_10_full;
+                reg_autoneg_adver.s.advert_10base_tx_half =
+                    reg_status.s.capable_10_half;
+                reg_autoneg_adver.s.advert_100base_tx_full =
+                    reg_status.s.capable_100base_x_full;
+                reg_autoneg_adver.s.advert_100base_tx_half =
+                    reg_status.s.capable_100base_x_half;
+                cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
+                                CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
+                                reg_autoneg_adver.u16);
+                if (reg_status.s.capable_extended_status) {
+                        reg_extended_status.u16 =
+                            cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                           CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
+                        reg_control_1000.u16 =
+                            cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                           CVMX_MDIO_PHY_REG_CONTROL_1000);
+                        reg_control_1000.s.advert_1000base_t_full =
+                            reg_extended_status.s.capable_1000base_t_full;
+                        reg_control_1000.s.advert_1000base_t_half =
+                            reg_extended_status.s.capable_1000base_t_half;
+                        cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
+                                        CVMX_MDIO_PHY_REG_CONTROL_1000,
+                                        reg_control_1000.u16);
+                }
+                reg_control.u16 =
+                    cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                   CVMX_MDIO_PHY_REG_CONTROL);
+                reg_control.s.autoneg_enable = 1;
+                reg_control.s.restart_autoneg = 1;
+                cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
+                                CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
+        } else if ((link_flags & set_phy_link_flags_autoneg)) {
+                cvmx_mdio_phy_reg_control_t reg_control;
+                cvmx_mdio_phy_reg_status_t reg_status;
+                cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
+                cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
+                cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
+
+                reg_status.u16 =
+                    cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                   CVMX_MDIO_PHY_REG_STATUS);
+                reg_autoneg_adver.u16 =
+                    cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                   CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
+                reg_autoneg_adver.s.advert_100base_t4 = 0;
+                reg_autoneg_adver.s.advert_10base_tx_full = 0;
+                reg_autoneg_adver.s.advert_10base_tx_half = 0;
+                reg_autoneg_adver.s.advert_100base_tx_full = 0;
+                reg_autoneg_adver.s.advert_100base_tx_half = 0;
+                if (reg_status.s.capable_extended_status) {
+                        reg_extended_status.u16 =
+                            cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                           CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
+                        reg_control_1000.u16 =
+                            cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                           CVMX_MDIO_PHY_REG_CONTROL_1000);
+                        reg_control_1000.s.advert_1000base_t_full = 0;
+                        reg_control_1000.s.advert_1000base_t_half = 0;
+                }
+                switch (link_info.s.speed) {
+                case 10:
+                        reg_autoneg_adver.s.advert_10base_tx_full =
+                            link_info.s.full_duplex;
+                        reg_autoneg_adver.s.advert_10base_tx_half =
+                            !link_info.s.full_duplex;
+                        break;
+                case 100:
+                        reg_autoneg_adver.s.advert_100base_tx_full =
+                            link_info.s.full_duplex;
+                        reg_autoneg_adver.s.advert_100base_tx_half =
+                            !link_info.s.full_duplex;
+                        break;
+                case 1000:
+                        reg_control_1000.s.advert_1000base_t_full =
+                            link_info.s.full_duplex;
+                        reg_control_1000.s.advert_1000base_t_half =
+                            !link_info.s.full_duplex;
+                        break;
+                }
+                cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
+                                CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
+                                reg_autoneg_adver.u16);
+                if (reg_status.s.capable_extended_status)
+                        cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
+                                        CVMX_MDIO_PHY_REG_CONTROL_1000,
+                                        reg_control_1000.u16);
+                reg_control.u16 =
+                    cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                   CVMX_MDIO_PHY_REG_CONTROL);
+                reg_control.s.autoneg_enable = 1;
+                reg_control.s.restart_autoneg = 1;
+                cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
+                                CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
+        } else {
+                cvmx_mdio_phy_reg_control_t reg_control;
+                reg_control.u16 =
+                    cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
+                                   CVMX_MDIO_PHY_REG_CONTROL);
+                reg_control.s.autoneg_enable = 0;
+                reg_control.s.restart_autoneg = 1;
+                reg_control.s.duplex = link_info.s.full_duplex;
+                if (link_info.s.speed == 1000) {
+                        reg_control.s.speed_msb = 1;
+                        reg_control.s.speed_lsb = 0;
+                } else if (link_info.s.speed == 100) {
+                        reg_control.s.speed_msb = 0;
+                        reg_control.s.speed_lsb = 1;
+                } else if (link_info.s.speed == 10) {
+                        reg_control.s.speed_msb = 0;
+                        reg_control.s.speed_lsb = 0;
+                }
+                cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
+                                CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
+        }
+        return 0;
+}
+
+/**
+ * This function is called by cvmx_helper_interface_probe() after it
+ * determines the number of ports Octeon can support on a specific
+ * interface. This function is the per board location to override
+ * this value. It is called with the number of ports Octeon might
+ * support and should return the number of actual ports on the
+ * board.
+ *
+ * This function must be modifed for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relys on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @interface: Interface to probe
+ * @supported_ports:
+ *                  Number of ports Octeon supports.
+ *
+ * Returns Number of ports the actual board supports. Many times this will
+ *         simple be "support_ports".
+ */
+int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
+{
+        switch (cvmx_sysinfo_get()->board_type) {
+        case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
+                if (interface == 0)
+                        return 2;
+                break;
+        case CVMX_BOARD_TYPE_BBGW_REF:
+                if (interface == 0)
+                        return 2;
+                break;
+        case CVMX_BOARD_TYPE_NIC_XLE_4G:
+                if (interface == 0)
+                        return 0;
+                break;
+                /* The 2nd interface on the EBH5600 is connected to the Marvel switch,
+                   which we don't support. Disable ports connected to it */
+        case CVMX_BOARD_TYPE_EBH5600:
+                if (interface == 1)
+                        return 0;
+                break;
+        }
+        return supported_ports;
+}
+
+/**
+ * Enable packet input/output from the hardware. This function is
+ * called after by cvmx_helper_packet_hardware_enable() to
+ * perform board specific initialization. For most boards
+ * nothing is needed.
+ *
+ * @interface: Interface to enable
+ *
+ * Returns Zero on success, negative on failure
+ */
+int __cvmx_helper_board_hardware_enable(int interface)
+{
+        if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) {
+                if (interface == 0) {
+                        /* Different config for switch port */
+                        cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0);
+                        cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0);
+                        /*
+                         * Boards with gigabit WAN ports need a
+                         * different setting that is compatible with
+                         * 100 Mbit settings
+                         */
+                        cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface),
+                                       0xc);
+                        cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface),
+                                       0xc);
+                }
+        } else if (cvmx_sysinfo_get()->board_type ==
+                   CVMX_BOARD_TYPE_CN3010_EVB_HS5) {
+                /*
+                 * Broadcom PHYs require differnet ASX
+                 * clocks. Unfortunately many boards don't define a
+                 * new board Id and simply mangle the
+                 * CN3010_EVB_HS5
+                 */
+                if (interface == 0) {
+                        /*
+                         * Some boards use a hacked up bootloader that
+                         * identifies them as CN3010_EVB_HS5
+                         * evaluation boards.  This leads to all kinds
+                         * of configuration problems.  Detect one
+                         * case, and print warning, while trying to do
+                         * the right thing.
+                         */
+                        int phy_addr = cvmx_helper_board_get_mii_address(0);
+                        if (phy_addr != -1) {
+                                int phy_identifier =
+                                    cvmx_mdio_read(phy_addr >> 8,
+                                                   phy_addr & 0xff, 0x2);
+                                /* Is it a Broadcom PHY? */
+                                if (phy_identifier == 0x0143) {
+                                        cvmx_dprintf("\n");
+                                        cvmx_dprintf("ERROR:\n");
+                                        cvmx_dprintf
+                                            ("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n");
+                                        cvmx_dprintf
+                                            ("ERROR: The board type is mis-configured, and software malfunctions are likely.\n");
+                                        cvmx_dprintf
+                                            ("ERROR: All boards require a unique board type to identify them.\n");
+                                        cvmx_dprintf("ERROR:\n");
+                                        cvmx_dprintf("\n");
+                                        cvmx_wait(1000000000);
+                                        cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX
+                                                       (0, interface), 5);
+                                        cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX
+                                                       (0, interface), 5);
+                                }
+                        }
+                }
+        }
+        return 0;
+}
+
+cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void)
+{
+        switch (cvmx_sysinfo_get()->board_type) {
+        case CVMX_BOARD_TYPE_BBGW_REF:
+                return USB_CLOCK_TYPE_CRYSTAL_12;
+        }
+        return USB_CLOCK_TYPE_REF_48;
+}
+
+int __cvmx_helper_board_usb_get_num_ports(int supported_ports)
+{
+        switch (cvmx_sysinfo_get()->board_type) {
+        case CVMX_BOARD_TYPE_NIC_XLE_4G:
+                return 0;
+        }
+
+        return supported_ports;
+}
diff --git a/drivers/staging/octeon/cvmx-helper-board.h b/drivers/staging/octeon/cvmx-helper-board.h
new file mode 100644
index 000000000000..dc20b01247c4
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-board.h
@@ -0,0 +1,180 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * Helper functions to abstract board specific data about
+ * network ports from the rest of the cvmx-helper files.
+ *
+ */
+#ifndef __CVMX_HELPER_BOARD_H__
+#define __CVMX_HELPER_BOARD_H__
+
+#include "cvmx-helper.h"
+
+typedef enum {
+        USB_CLOCK_TYPE_REF_12,
+        USB_CLOCK_TYPE_REF_24,
+        USB_CLOCK_TYPE_REF_48,
+        USB_CLOCK_TYPE_CRYSTAL_12,
+} cvmx_helper_board_usb_clock_types_t;
+
+typedef enum {
+        set_phy_link_flags_autoneg = 0x1,
+        set_phy_link_flags_flow_control_dont_touch = 0x0 << 1,
+        set_phy_link_flags_flow_control_enable = 0x1 << 1,
+        set_phy_link_flags_flow_control_disable = 0x2 << 1,
+        set_phy_link_flags_flow_control_mask = 0x3 << 1,        /* Mask for 2 bit wide flow control field */
+} cvmx_helper_board_set_phy_link_flags_types_t;
+
+/**
+ * cvmx_override_board_link_get(int ipd_port) is a function
+ * pointer. It is meant to allow customization of the process of
+ * talking to a PHY to determine link speed. It is called every
+ * time a PHY must be polled for link status. Users should set
+ * this pointer to a function before calling any cvmx-helper
+ * operations.
+ */
+extern cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port);
+
+/**
+ * Return the MII PHY address associated with the given IPD
+ * port. A result of -1 means there isn't a MII capable PHY
+ * connected to this port. On chips supporting multiple MII
+ * busses the bus number is encoded in bits <15:8>.
+ *
+ * This function must be modifed for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relys on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @ipd_port: Octeon IPD port to get the MII address for.
+ *
+ * Returns MII PHY address and bus number or -1.
+ */
+extern int cvmx_helper_board_get_mii_address(int ipd_port);
+
+/**
+ * This function as a board specific method of changing the PHY
+ * speed, duplex, and autonegotiation. This programs the PHY and
+ * not Octeon. This can be used to force Octeon's links to
+ * specific settings.
+ *
+ * @phy_addr:  The address of the PHY to program
+ * @link_flags:
+ *                  Flags to control autonegotiation.  Bit 0 is autonegotiation
+ *                  enable/disable to maintain backware compatability.
+ * @link_info: Link speed to program. If the speed is zero and autonegotiation
+ *                  is enabled, all possible negotiation speeds are advertised.
+ *
+ * Returns Zero on success, negative on failure
+ */
+int cvmx_helper_board_link_set_phy(int phy_addr,
+                                   cvmx_helper_board_set_phy_link_flags_types_t
+                                   link_flags,
+                                   cvmx_helper_link_info_t link_info);
+
+/**
+ * This function is the board specific method of determining an
+ * ethernet ports link speed. Most Octeon boards have Marvell PHYs
+ * and are handled by the fall through case. This function must be
+ * updated for boards that don't have the normal Marvell PHYs.
+ *
+ * This function must be modifed for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relys on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @ipd_port: IPD input port associated with the port we want to get link
+ *                 status for.
+ *
+ * Returns The ports link status. If the link isn't fully resolved, this must
+ *         return zero.
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port);
+
+/**
+ * This function is called by cvmx_helper_interface_probe() after it
+ * determines the number of ports Octeon can support on a specific
+ * interface. This function is the per board location to override
+ * this value. It is called with the number of ports Octeon might
+ * support and should return the number of actual ports on the
+ * board.
+ *
+ * This function must be modifed for every new Octeon board.
+ * Internally it uses switch statements based on the cvmx_sysinfo
+ * data to determine board types and revisions. It relys on the
+ * fact that every Octeon board receives a unique board type
+ * enumeration from the bootloader.
+ *
+ * @interface: Interface to probe
+ * @supported_ports:
+ *                  Number of ports Octeon supports.
+ *
+ * Returns Number of ports the actual board supports. Many times this will
+ *         simple be "support_ports".
+ */
+extern int __cvmx_helper_board_interface_probe(int interface,
+                                               int supported_ports);
+
+/**
+ * Enable packet input/output from the hardware. This function is
+ * called after by cvmx_helper_packet_hardware_enable() to
+ * perform board specific initialization. For most boards
+ * nothing is needed.
+ *
+ * @interface: Interface to enable
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_board_hardware_enable(int interface);
+
+/**
+ * Gets the clock type used for the USB block based on board type.
+ * Used by the USB code for auto configuration of clock type.
+ *
+ * Returns USB clock type enumeration
+ */
+cvmx_helper_board_usb_clock_types_t
+__cvmx_helper_board_usb_get_clock_type(void);
+
+/**
+ * Adjusts the number of available USB ports on Octeon based on board
+ * specifics.
+ *
+ * @supported_ports: expected number of ports based on chip type;
+ *
+ *
+ * Returns number of available usb ports, based on board specifics.
+ *         Return value is supported_ports if function does not
+ *         override.
+ */
+int __cvmx_helper_board_usb_get_num_ports(int supported_ports);
+
+#endif /* __CVMX_HELPER_BOARD_H__ */
diff --git a/drivers/staging/octeon/cvmx-helper-fpa.c b/drivers/staging/octeon/cvmx-helper-fpa.c
new file mode 100644
index 000000000000..c239e5f4ab9a
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-fpa.c
@@ -0,0 +1,243 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Helper functions for FPA setup.
+ *
+ */
+#include "executive-config.h"
+#include "cvmx-config.h"
+#include "cvmx.h"
+#include "cvmx-bootmem.h"
+#include "cvmx-fpa.h"
+#include "cvmx-helper-fpa.h"
+
+/**
+ * Allocate memory for and initialize a single FPA pool.
+ *
+ * @pool:    Pool to initialize
+ * @buffer_size:  Size of buffers to allocate in bytes
+ * @buffers: Number of buffers to put in the pool. Zero is allowed
+ * @name:    String name of the pool for debugging purposes
+ * Returns Zero on success, non-zero on failure
+ */
+static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size,
+                                             uint64_t buffers, const char *name)
+{
+        uint64_t current_num;
+        void *memory;
+        uint64_t align = CVMX_CACHE_LINE_SIZE;
+
+        /*
+         * Align the allocation so that power of 2 size buffers are
+         * naturally aligned.
+         */
+        while (align < buffer_size)
+                align = align << 1;
+
+        if (buffers == 0)
+                return 0;
+
+        current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool));
+        if (current_num) {
+                cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. "
+                             "Skipping setup.\n",
+                     pool, name, (unsigned long long)current_num);
+                return 0;
+        }
+
+        memory = cvmx_bootmem_alloc(buffer_size * buffers, align);
+        if (memory == NULL) {
+                cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n",
+                             pool, name);
+                return -1;
+        }
+        cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers);
+        return 0;
+}
+
+/**
+ * Allocate memory and initialize the FPA pools using memory
+ * from cvmx-bootmem. Specifying zero for the number of
+ * buffers will cause that FPA pool to not be setup. This is
+ * useful if you aren't using some of the hardware and want
+ * to save memory. Use cvmx_helper_initialize_fpa instead of
+ * this function directly.
+ *
+ * @pip_pool: Should always be CVMX_FPA_PACKET_POOL
+ * @pip_size: Should always be CVMX_FPA_PACKET_POOL_SIZE
+ * @pip_buffers:
+ *                 Number of packet buffers.
+ * @wqe_pool: Should always be CVMX_FPA_WQE_POOL
+ * @wqe_size: Should always be CVMX_FPA_WQE_POOL_SIZE
+ * @wqe_entries:
+ *                 Number of work queue entries
+ * @pko_pool: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL
+ * @pko_size: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE
+ * @pko_buffers:
+ *                 PKO Command buffers. You should at minimum have two per
+ *                 each PKO queue.
+ * @tim_pool: Should always be CVMX_FPA_TIMER_POOL
+ * @tim_size: Should always be CVMX_FPA_TIMER_POOL_SIZE
+ * @tim_buffers:
+ *                 TIM ring buffer command queues. At least two per timer bucket
+ *                 is recommened.
+ * @dfa_pool: Should always be CVMX_FPA_DFA_POOL
+ * @dfa_size: Should always be CVMX_FPA_DFA_POOL_SIZE
+ * @dfa_buffers:
+ *                 DFA command buffer. A relatively small (32 for example)
+ *                 number should work.
+ * Returns Zero on success, non-zero if out of memory
+ */
+static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size,
+                                        int pip_buffers, int wqe_pool,
+                                        int wqe_size, int wqe_entries,
+                                        int pko_pool, int pko_size,
+                                        int pko_buffers, int tim_pool,
+                                        int tim_size, int tim_buffers,
+                                        int dfa_pool, int dfa_size,
+                                        int dfa_buffers)
+{
+        int status;
+
+        cvmx_fpa_enable();
+
+        if ((pip_buffers > 0) && (pip_buffers <= 64))
+                cvmx_dprintf
+                    ("Warning: %d packet buffers may not be enough for hardware"
+                     " prefetch. 65 or more is recommended.\n", pip_buffers);
+
+        if (pip_pool >= 0) {
+                status =
+                    __cvmx_helper_initialize_fpa_pool(pip_pool, pip_size,
+                                                      pip_buffers,
+                                                      "Packet Buffers");
+                if (status)
+                        return status;
+        }
+
+        if (wqe_pool >= 0) {
+                status =
+                    __cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size,
+                                                      wqe_entries,
+                                                      "Work Queue Entries");
+                if (status)
+                        return status;
+        }
+
+        if (pko_pool >= 0) {
+                status =
+                    __cvmx_helper_initialize_fpa_pool(pko_pool, pko_size,
+                                                      pko_buffers,
+                                                      "PKO Command Buffers");
+                if (status)
+                        return status;
+        }
+
+        if (tim_pool >= 0) {
+                status =
+                    __cvmx_helper_initialize_fpa_pool(tim_pool, tim_size,
+                                                      tim_buffers,
+                                                      "TIM Command Buffers");
+                if (status)
+                        return status;
+        }
+
+        if (dfa_pool >= 0) {
+                status =
+                    __cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size,
+                                                      dfa_buffers,
+                                                      "DFA Command Buffers");
+                if (status)
+                        return status;
+        }
+
+        return 0;
+}
+
+/**
+ * Allocate memory and initialize the FPA pools using memory
+ * from cvmx-bootmem. Sizes of each element in the pools is
+ * controlled by the cvmx-config.h header file. Specifying
+ * zero for any parameter will cause that FPA pool to not be
+ * setup. This is useful if you aren't using some of the
+ * hardware and want to save memory.
+ *
+ * @packet_buffers:
+ *               Number of packet buffers to allocate
+ * @work_queue_entries:
+ *               Number of work queue entries
+ * @pko_buffers:
+ *               PKO Command buffers. You should at minimum have two per
+ *               each PKO queue.
+ * @tim_buffers:
+ *               TIM ring buffer command queues. At least two per timer bucket
+ *               is recommened.
+ * @dfa_buffers:
+ *               DFA command buffer. A relatively small (32 for example)
+ *               number should work.
+ * Returns Zero on success, non-zero if out of memory
+ */
+int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries,
+                               int pko_buffers, int tim_buffers,
+                               int dfa_buffers)
+{
+#ifndef CVMX_FPA_PACKET_POOL
+#define CVMX_FPA_PACKET_POOL -1
+#define CVMX_FPA_PACKET_POOL_SIZE 0
+#endif
+#ifndef CVMX_FPA_WQE_POOL
+#define CVMX_FPA_WQE_POOL -1
+#define CVMX_FPA_WQE_POOL_SIZE 0
+#endif
+#ifndef CVMX_FPA_OUTPUT_BUFFER_POOL
+#define CVMX_FPA_OUTPUT_BUFFER_POOL -1
+#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0
+#endif
+#ifndef CVMX_FPA_TIMER_POOL
+#define CVMX_FPA_TIMER_POOL -1
+#define CVMX_FPA_TIMER_POOL_SIZE 0
+#endif
+#ifndef CVMX_FPA_DFA_POOL
+#define CVMX_FPA_DFA_POOL -1
+#define CVMX_FPA_DFA_POOL_SIZE 0
+#endif
+        return __cvmx_helper_initialize_fpa(CVMX_FPA_PACKET_POOL,
+                                            CVMX_FPA_PACKET_POOL_SIZE,
+                                            packet_buffers, CVMX_FPA_WQE_POOL,
+                                            CVMX_FPA_WQE_POOL_SIZE,
+                                            work_queue_entries,
+                                            CVMX_FPA_OUTPUT_BUFFER_POOL,
+                                            CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE,
+                                            pko_buffers, CVMX_FPA_TIMER_POOL,
+                                            CVMX_FPA_TIMER_POOL_SIZE,
+                                            tim_buffers, CVMX_FPA_DFA_POOL,
+                                            CVMX_FPA_DFA_POOL_SIZE,
+                                            dfa_buffers);
+}
diff --git a/drivers/staging/octeon/cvmx-helper-fpa.h b/drivers/staging/octeon/cvmx-helper-fpa.h
new file mode 100644
index 000000000000..5ff8c93198de
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-fpa.h
@@ -0,0 +1,64 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Helper functions for FPA setup.
+ *
+ */
+#ifndef __CVMX_HELPER_H_FPA__
+#define __CVMX_HELPER_H_FPA__
+
+/**
+ * Allocate memory and initialize the FPA pools using memory
+ * from cvmx-bootmem. Sizes of each element in the pools is
+ * controlled by the cvmx-config.h header file. Specifying
+ * zero for any parameter will cause that FPA pool to not be
+ * setup. This is useful if you aren't using some of the
+ * hardware and want to save memory.
+ *
+ * @packet_buffers:
+ *               Number of packet buffers to allocate
+ * @work_queue_entries:
+ *               Number of work queue entries
+ * @pko_buffers:
+ *               PKO Command buffers. You should at minimum have two per
+ *               each PKO queue.
+ * @tim_buffers:
+ *               TIM ring buffer command queues. At least two per timer bucket
+ *               is recommened.
+ * @dfa_buffers:
+ *               DFA command buffer. A relatively small (32 for example)
+ *               number should work.
+ * Returns Zero on success, non-zero if out of memory
+ */
+extern int cvmx_helper_initialize_fpa(int packet_buffers,
+                                      int work_queue_entries, int pko_buffers,
+                                      int tim_buffers, int dfa_buffers);
+
+#endif /* __CVMX_HELPER_H__ */
diff --git a/drivers/staging/octeon/cvmx-helper-loop.c b/drivers/staging/octeon/cvmx-helper-loop.c
new file mode 100644
index 000000000000..55a571a69529
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-loop.c
@@ -0,0 +1,85 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Functions for LOOP initialization, configuration,
+ * and monitoring.
+ */
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-config.h"
+
+#include "cvmx-helper.h"
+#include "cvmx-pip-defs.h"
+
+/**
+ * Probe a LOOP interface and determine the number of ports
+ * connected to it. The LOOP interface should still be down
+ * after this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_loop_probe(int interface)
+{
+        union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
+        int num_ports = 4;
+        int port;
+
+        /* We need to disable length checking so packet < 64 bytes and jumbo
+           frames don't get errors */
+        for (port = 0; port < num_ports; port++) {
+                union cvmx_pip_prt_cfgx port_cfg;
+                int ipd_port = cvmx_helper_get_ipd_port(interface, port);
+                port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+                port_cfg.s.maxerr_en = 0;
+                port_cfg.s.minerr_en = 0;
+                cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64);
+        }
+
+        /* Disable FCS stripping for loopback ports */
+        ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
+        ipd_sub_port_fcs.s.port_bit2 = 0;
+        cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
+        return num_ports;
+}
+
+/**
+ * Bringup and enable a LOOP interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+int __cvmx_helper_loop_enable(int interface)
+{
+        /* Do nothing. */
+        return 0;
+}
diff --git a/drivers/staging/octeon/cvmx-helper-loop.h b/drivers/staging/octeon/cvmx-helper-loop.h
new file mode 100644
index 000000000000..e646a6ccce75
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-loop.h
@@ -0,0 +1,59 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as published by
+ * the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for LOOP initialization, configuration,
+ * and monitoring.
+ *
+ */
+#ifndef __CVMX_HELPER_LOOP_H__
+#define __CVMX_HELPER_LOOP_H__
+
+/**
+ * Probe a LOOP interface and determine the number of ports
+ * connected to it. The LOOP interface should still be down after
+ * this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_loop_probe(int interface);
+
+/**
+ * Bringup and enable a LOOP interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_loop_enable(int interface);
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-helper-npi.c b/drivers/staging/octeon/cvmx-helper-npi.c
new file mode 100644
index 000000000000..7388a1e72b38
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-npi.c
@@ -0,0 +1,113 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Functions for NPI initialization, configuration,
+ * and monitoring.
+ */
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-config.h"
+
+#include "cvmx-helper.h"
+
+#include "cvmx-pip-defs.h"
+
+/**
+ * Probe a NPI interface and determine the number of ports
+ * connected to it. The NPI interface should still be down
+ * after this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_npi_probe(int interface)
+{
+#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0
+        if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+                return 4;
+        else if (OCTEON_IS_MODEL(OCTEON_CN56XX)
+                 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
+                /* The packet engines didn't exist before pass 2 */
+                return 4;
+        else if (OCTEON_IS_MODEL(OCTEON_CN52XX)
+                 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X))
+                /* The packet engines didn't exist before pass 2 */
+                return 4;
+#if 0
+        /*
+         * Technically CN30XX, CN31XX, and CN50XX contain packet
+         * engines, but nobody ever uses them. Since this is the case,
+         * we disable them here.
+         */
+        else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
+                 || OCTEON_IS_MODEL(OCTEON_CN50XX))
+                return 2;
+        else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
+                return 1;
+#endif
+#endif
+        return 0;
+}
+
+/**
+ * Bringup and enable a NPI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+int __cvmx_helper_npi_enable(int interface)
+{
+        /*
+         * On CN50XX, CN52XX, and CN56XX we need to disable length
+         * checking so packet < 64 bytes and jumbo frames don't get
+         * errors.
+         */
+        if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) &&
+            !OCTEON_IS_MODEL(OCTEON_CN58XX)) {
+                int num_ports = cvmx_helper_ports_on_interface(interface);
+                int port;
+                for (port = 0; port < num_ports; port++) {
+                        union cvmx_pip_prt_cfgx port_cfg;
+                        int ipd_port =
+                            cvmx_helper_get_ipd_port(interface, port);
+                        port_cfg.u64 =
+                            cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+                        port_cfg.s.maxerr_en = 0;
+                        port_cfg.s.minerr_en = 0;
+                        cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port),
+                                       port_cfg.u64);
+                }
+        }
+
+        /* Enables are controlled by the remote host, so nothing to do here */
+        return 0;
+}
diff --git a/drivers/staging/octeon/cvmx-helper-npi.h b/drivers/staging/octeon/cvmx-helper-npi.h
new file mode 100644
index 000000000000..908e7b08c214
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-npi.h
@@ -0,0 +1,60 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for NPI initialization, configuration,
+ * and monitoring.
+ *
+ */
+#ifndef __CVMX_HELPER_NPI_H__
+#define __CVMX_HELPER_NPI_H__
+
+/**
+ * Probe a NPI interface and determine the number of ports
+ * connected to it. The NPI interface should still be down after
+ * this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_npi_probe(int interface);
+
+/**
+ * Bringup and enable a NPI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_npi_enable(int interface);
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.c b/drivers/staging/octeon/cvmx-helper-rgmii.c
new file mode 100644
index 000000000000..aa2d5d7fee2b
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-rgmii.c
@@ -0,0 +1,525 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Functions for RGMII/GMII/MII initialization, configuration,
+ * and monitoring.
+ */
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-config.h"
+
+
+#include "cvmx-mdio.h"
+#include "cvmx-pko.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-board.h"
+
+#include <asm/octeon/cvmx-npi-defs.h>
+#include "cvmx-gmxx-defs.h"
+#include "cvmx-asxx-defs.h"
+#include "cvmx-dbg-defs.h"
+
+void __cvmx_interrupt_gmxx_enable(int interface);
+void __cvmx_interrupt_asxx_enable(int block);
+
+/**
+ * Probe RGMII ports and determine the number present
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of RGMII/GMII/MII ports (0-4).
+ */
+int __cvmx_helper_rgmii_probe(int interface)
+{
+        int num_ports = 0;
+        union cvmx_gmxx_inf_mode mode;
+        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+
+        if (mode.s.type) {
+                if (OCTEON_IS_MODEL(OCTEON_CN38XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
+                        cvmx_dprintf("ERROR: RGMII initialize called in "
+                                     "SPI interface\n");
+                } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
+                           || OCTEON_IS_MODEL(OCTEON_CN30XX)
+                           || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                        /*
+                         * On these chips "type" says we're in
+                         * GMII/MII mode. This limits us to 2 ports
+                         */
+                        num_ports = 2;
+                } else {
+                        cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
+                                     __func__);
+                }
+        } else {
+                if (OCTEON_IS_MODEL(OCTEON_CN38XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
+                        num_ports = 4;
+                } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
+                           || OCTEON_IS_MODEL(OCTEON_CN30XX)
+                           || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                        num_ports = 3;
+                } else {
+                        cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
+                                     __func__);
+                }
+        }
+        return num_ports;
+}
+
+/**
+ * Put an RGMII interface in loopback mode. Internal packets sent
+ * out will be received back again on the same port. Externally
+ * received packets will echo back out.
+ *
+ * @port:   IPD port number to loop.
+ */
+void cvmx_helper_rgmii_internal_loopback(int port)
+{
+        int interface = (port >> 4) & 1;
+        int index = port & 0xf;
+        uint64_t tmp;
+
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        gmx_cfg.u64 = 0;
+        gmx_cfg.s.duplex = 1;
+        gmx_cfg.s.slottime = 1;
+        gmx_cfg.s.speed = 1;
+        cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
+        cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
+        cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+        tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
+        cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp);
+        tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
+        cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp);
+        tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
+        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp);
+        gmx_cfg.s.en = 1;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+}
+
+/**
+ * Workaround ASX setup errata with CN38XX pass1
+ *
+ * @interface: Interface to setup
+ * @port:      Port to setup (0..3)
+ * @cpu_clock_hz:
+ *                  Chip frequency in Hertz
+ *
+ * Returns Zero on success, negative on failure
+ */
+static int __cvmx_helper_errata_asx_pass1(int interface, int port,
+                                          int cpu_clock_hz)
+{
+        /* Set hi water mark as per errata GMX-4 */
+        if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000)
+                cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);
+        else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000)
+                cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);
+        else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000)
+                cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);
+        else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000)
+                cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);
+        else
+                cvmx_dprintf("Illegal clock frequency (%d). "
+                        "CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz);
+        return 0;
+}
+
+/**
+ * Configure all of the ASX, GMX, and PKO regsiters required
+ * to get RGMII to function on the supplied interface.
+ *
+ * @interface: PKO Interface to configure (0 or 1)
+ *
+ * Returns Zero on success
+ */
+int __cvmx_helper_rgmii_enable(int interface)
+{
+        int num_ports = cvmx_helper_ports_on_interface(interface);
+        int port;
+        struct cvmx_sysinfo *sys_info_ptr = cvmx_sysinfo_get();
+        union cvmx_gmxx_inf_mode mode;
+        union cvmx_asxx_tx_prt_en asx_tx;
+        union cvmx_asxx_rx_prt_en asx_rx;
+
+        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+
+        if (mode.s.en == 0)
+                return -1;
+        if ((OCTEON_IS_MODEL(OCTEON_CN38XX) ||
+             OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1)
+                /* Ignore SPI interfaces */
+                return -1;
+
+        /* Configure the ASX registers needed to use the RGMII ports */
+        asx_tx.u64 = 0;
+        asx_tx.s.prt_en = cvmx_build_mask(num_ports);
+        cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64);
+
+        asx_rx.u64 = 0;
+        asx_rx.s.prt_en = cvmx_build_mask(num_ports);
+        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64);
+
+        /* Configure the GMX registers needed to use the RGMII ports */
+        for (port = 0; port < num_ports; port++) {
+                /* Setting of CVMX_GMXX_TXX_THRESH has been moved to
+                   __cvmx_helper_setup_gmx() */
+
+                if (cvmx_octeon_is_pass1())
+                        __cvmx_helper_errata_asx_pass1(interface, port,
+                                                       sys_info_ptr->
+                                                       cpu_clock_hz);
+                else {
+                        /*
+                         * Configure more flexible RGMII preamble
+                         * checking. Pass 1 doesn't support this
+                         * feature.
+                         */
+                        union cvmx_gmxx_rxx_frm_ctl frm_ctl;
+                        frm_ctl.u64 =
+                            cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL
+                                          (port, interface));
+                        /* New field, so must be compile time */
+                        frm_ctl.s.pre_free = 1;
+                        cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface),
+                                       frm_ctl.u64);
+                }
+
+                /*
+                 * Each pause frame transmitted will ask for about 10M
+                 * bit times before resume.  If buffer space comes
+                 * available before that time has expired, an XON
+                 * pause frame (0 time) will be transmitted to restart
+                 * the flow.
+                 */
+                cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface),
+                               20000);
+                cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL
+                               (port, interface), 19000);
+
+                if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                        cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
+                                       16);
+                        cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
+                                       16);
+                } else {
+                        cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
+                                       24);
+                        cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
+                                       24);
+                }
+        }
+
+        __cvmx_helper_setup_gmx(interface, num_ports);
+
+        /* enable the ports now */
+        for (port = 0; port < num_ports; port++) {
+                union cvmx_gmxx_prtx_cfg gmx_cfg;
+                cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port
+                                          (interface, port));
+                gmx_cfg.u64 =
+                    cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface));
+                gmx_cfg.s.en = 1;
+                cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface),
+                               gmx_cfg.u64);
+        }
+        __cvmx_interrupt_asxx_enable(interface);
+        __cvmx_interrupt_gmxx_enable(interface);
+
+        return 0;
+}
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port)
+{
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+        union cvmx_asxx_prt_loop asxx_prt_loop;
+
+        asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
+        if (asxx_prt_loop.s.int_loop & (1 << index)) {
+                /* Force 1Gbps full duplex on internal loopback */
+                cvmx_helper_link_info_t result;
+                result.u64 = 0;
+                result.s.full_duplex = 1;
+                result.s.link_up = 1;
+                result.s.speed = 1000;
+                return result;
+        } else
+                return __cvmx_helper_board_link_get(ipd_port);
+}
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+int __cvmx_helper_rgmii_link_set(int ipd_port,
+                                 cvmx_helper_link_info_t link_info)
+{
+        int result = 0;
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+        union cvmx_gmxx_prtx_cfg original_gmx_cfg;
+        union cvmx_gmxx_prtx_cfg new_gmx_cfg;
+        union cvmx_pko_mem_queue_qos pko_mem_queue_qos;
+        union cvmx_pko_mem_queue_qos pko_mem_queue_qos_save[16];
+        union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp;
+        union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp_save;
+        int i;
+
+        /* Ignore speed sets in the simulator */
+        if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
+                return 0;
+
+        /* Read the current settings so we know the current enable state */
+        original_gmx_cfg.u64 =
+            cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+        new_gmx_cfg = original_gmx_cfg;
+
+        /* Disable the lowest level RX */
+        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
+                       cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) &
+                                     ~(1 << index));
+
+        /* Disable all queues so that TX should become idle */
+        for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
+                int queue = cvmx_pko_get_base_queue(ipd_port) + i;
+                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
+                pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS);
+                pko_mem_queue_qos.s.pid = ipd_port;
+                pko_mem_queue_qos.s.qid = queue;
+                pko_mem_queue_qos_save[i] = pko_mem_queue_qos;
+                pko_mem_queue_qos.s.qos_mask = 0;
+                cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64);
+        }
+
+        /* Disable backpressure */
+        gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
+        gmx_tx_ovr_bp_save = gmx_tx_ovr_bp;
+        gmx_tx_ovr_bp.s.bp &= ~(1 << index);
+        gmx_tx_ovr_bp.s.en |= 1 << index;
+        cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);
+        cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
+
+        /*
+         * Poll the GMX state machine waiting for it to become
+         * idle. Preferably we should only change speed when it is
+         * idle. If it doesn't become idle we will still do the speed
+         * change, but there is a slight chance that GMX will
+         * lockup.
+         */
+        cvmx_write_csr(CVMX_NPI_DBG_SELECT,
+                       interface * 0x800 + index * 0x100 + 0x880);
+        CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7,
+                        ==, 0, 10000);
+        CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 0xf,
+                        ==, 0, 10000);
+
+        /* Disable the port before we make any changes */
+        new_gmx_cfg.s.en = 0;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
+        cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+
+        /* Set full/half duplex */
+        if (cvmx_octeon_is_pass1())
+                /* Half duplex is broken for 38XX Pass 1 */
+                new_gmx_cfg.s.duplex = 1;
+        else if (!link_info.s.link_up)
+                /* Force full duplex on down links */
+                new_gmx_cfg.s.duplex = 1;
+        else
+                new_gmx_cfg.s.duplex = link_info.s.full_duplex;
+
+        /* Set the link speed. Anything unknown is set to 1Gbps */
+        if (link_info.s.speed == 10) {
+                new_gmx_cfg.s.slottime = 0;
+                new_gmx_cfg.s.speed = 0;
+        } else if (link_info.s.speed == 100) {
+                new_gmx_cfg.s.slottime = 0;
+                new_gmx_cfg.s.speed = 0;
+        } else {
+                new_gmx_cfg.s.slottime = 1;
+                new_gmx_cfg.s.speed = 1;
+        }
+
+        /* Adjust the clocks */
+        if (link_info.s.speed == 10) {
+                cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50);
+                cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
+                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
+        } else if (link_info.s.speed == 100) {
+                cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5);
+                cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
+                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
+        } else {
+                cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
+                cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
+                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
+        }
+
+        if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                if ((link_info.s.speed == 10) || (link_info.s.speed == 100)) {
+                        union cvmx_gmxx_inf_mode mode;
+                        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+
+        /*
+         * Port  .en  .type  .p0mii  Configuration
+         * ----  ---  -----  ------  -----------------------------------------
+         *  X      0     X      X    All links are disabled.
+         *  0      1     X      0    Port 0 is RGMII
+         *  0      1     X      1    Port 0 is MII
+         *  1      1     0      X    Ports 1 and 2 are configured as RGMII ports.
+         *  1      1     1      X    Port 1: GMII/MII; Port 2: disabled. GMII or
+         *                           MII port is selected by GMX_PRT1_CFG[SPEED].
+         */
+
+                        /* In MII mode, CLK_CNT = 1. */
+                        if (((index == 0) && (mode.s.p0mii == 1))
+                            || ((index != 0) && (mode.s.type == 1))) {
+                                cvmx_write_csr(CVMX_GMXX_TXX_CLK
+                                               (index, interface), 1);
+                        }
+                }
+        }
+
+        /* Do a read to make sure all setup stuff is complete */
+        cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+
+        /* Save the new GMX setting without enabling the port */
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
+
+        /* Enable the lowest level RX */
+        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
+                       cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1 <<
+                                                                        index));
+
+        /* Re-enable the TX path */
+        for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
+                int queue = cvmx_pko_get_base_queue(ipd_port) + i;
+                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
+                cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS,
+                               pko_mem_queue_qos_save[i].u64);
+        }
+
+        /* Restore backpressure */
+        cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64);
+
+        /* Restore the GMX enable state. Port config is complete */
+        new_gmx_cfg.s.en = original_gmx_cfg.s.en;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
+
+        return result;
+}
+
+/**
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @ipd_port: IPD/PKO port to loopback.
+ * @enable_internal:
+ *                 Non zero if you want internal loopback
+ * @enable_external:
+ *                 Non zero if you want external loopback
+ *
+ * Returns Zero on success, negative on failure.
+ */
+int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal,
+                                           int enable_external)
+{
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+        int original_enable;
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        union cvmx_asxx_prt_loop asxx_prt_loop;
+
+        /* Read the current enable state and save it */
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+        original_enable = gmx_cfg.s.en;
+        /* Force port to be disabled */
+        gmx_cfg.s.en = 0;
+        if (enable_internal) {
+                /* Force speed if we're doing internal loopback */
+                gmx_cfg.s.duplex = 1;
+                gmx_cfg.s.slottime = 1;
+                gmx_cfg.s.speed = 1;
+                cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
+                cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
+                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
+        }
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+
+        /* Set the loopback bits */
+        asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
+        if (enable_internal)
+                asxx_prt_loop.s.int_loop |= 1 << index;
+        else
+                asxx_prt_loop.s.int_loop &= ~(1 << index);
+        if (enable_external)
+                asxx_prt_loop.s.ext_loop |= 1 << index;
+        else
+                asxx_prt_loop.s.ext_loop &= ~(1 << index);
+        cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), asxx_prt_loop.u64);
+
+        /* Force enables in internal loopback */
+        if (enable_internal) {
+                uint64_t tmp;
+                tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
+                cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface),
+                               (1 << index) | tmp);
+                tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
+                cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
+                               (1 << index) | tmp);
+                original_enable = 1;
+        }
+
+        /* Restore the enable state */
+        gmx_cfg.s.en = original_enable;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+        return 0;
+}
diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.h b/drivers/staging/octeon/cvmx-helper-rgmii.h
new file mode 100644
index 000000000000..ea2652604a57
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-rgmii.h
@@ -0,0 +1,110 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for RGMII/GMII/MII initialization, configuration,
+ * and monitoring.
+ *
+ */
+#ifndef __CVMX_HELPER_RGMII_H__
+#define __CVMX_HELPER_RGMII_H__
+
+/**
+ * Probe RGMII ports and determine the number present
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of RGMII/GMII/MII ports (0-4).
+ */
+extern int __cvmx_helper_rgmii_probe(int interface);
+
+/**
+ * Put an RGMII interface in loopback mode. Internal packets sent
+ * out will be received back again on the same port. Externally
+ * received packets will echo back out.
+ *
+ * @port:   IPD port number to loop.
+ */
+extern void cvmx_helper_rgmii_internal_loopback(int port);
+
+/**
+ * Configure all of the ASX, GMX, and PKO regsiters required
+ * to get RGMII to function on the supplied interface.
+ *
+ * @interface: PKO Interface to configure (0 or 1)
+ *
+ * Returns Zero on success
+ */
+extern int __cvmx_helper_rgmii_enable(int interface);
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port);
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_rgmii_link_set(int ipd_port,
+                                        cvmx_helper_link_info_t link_info);
+
+/**
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @ipd_port: IPD/PKO port to loopback.
+ * @enable_internal:
+ *                 Non zero if you want internal loopback
+ * @enable_external:
+ *                 Non zero if you want external loopback
+ *
+ * Returns Zero on success, negative on failure.
+ */
+extern int __cvmx_helper_rgmii_configure_loopback(int ipd_port,
+                                                  int enable_internal,
+                                                  int enable_external);
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.c b/drivers/staging/octeon/cvmx-helper-sgmii.c
new file mode 100644
index 000000000000..6214e3b6d975
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-sgmii.c
@@ -0,0 +1,550 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Functions for SGMII initialization, configuration,
+ * and monitoring.
+ */
+
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-config.h"
+
+#include "cvmx-mdio.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-board.h"
+
+#include "cvmx-gmxx-defs.h"
+#include "cvmx-pcsx-defs.h"
+
+void __cvmx_interrupt_gmxx_enable(int interface);
+void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
+void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
+
+/**
+ * Perform initialization required only once for an SGMII port.
+ *
+ * @interface: Interface to init
+ * @index:     Index of prot on the interface
+ *
+ * Returns Zero on success, negative on failure
+ */
+static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index)
+{
+        const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000;
+        union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg;
+        union cvmx_pcsx_linkx_timer_count_reg pcsx_linkx_timer_count_reg;
+        union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
+
+        /* Disable GMX */
+        gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+        gmxx_prtx_cfg.s.en = 0;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
+
+        /*
+         * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the
+         * appropriate value. 1000BASE-X specifies a 10ms
+         * interval. SGMII specifies a 1.6ms interval.
+         */
+        pcs_misc_ctl_reg.u64 =
+            cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+        pcsx_linkx_timer_count_reg.u64 =
+            cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface));
+        if (pcs_misc_ctl_reg.s.mode) {
+                /* 1000BASE-X */
+                pcsx_linkx_timer_count_reg.s.count =
+                    (10000ull * clock_mhz) >> 10;
+        } else {
+                /* SGMII */
+                pcsx_linkx_timer_count_reg.s.count =
+                    (1600ull * clock_mhz) >> 10;
+        }
+        cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface),
+                       pcsx_linkx_timer_count_reg.u64);
+
+        /*
+         * Write the advertisement register to be used as the
+         * tx_Config_Reg<D15:D0> of the autonegotiation.  In
+         * 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG.
+         * In SGMII PHY mode, tx_Config_Reg<D15:D0> is
+         * PCS*_SGM*_AN_ADV_REG.  In SGMII MAC mode,
+         * tx_Config_Reg<D15:D0> is the fixed value 0x4001, so this
+         * step can be skipped.
+         */
+        if (pcs_misc_ctl_reg.s.mode) {
+                /* 1000BASE-X */
+                union cvmx_pcsx_anx_adv_reg pcsx_anx_adv_reg;
+                pcsx_anx_adv_reg.u64 =
+                    cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface));
+                pcsx_anx_adv_reg.s.rem_flt = 0;
+                pcsx_anx_adv_reg.s.pause = 3;
+                pcsx_anx_adv_reg.s.hfd = 1;
+                pcsx_anx_adv_reg.s.fd = 1;
+                cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface),
+                               pcsx_anx_adv_reg.u64);
+        } else {
+                union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
+                pcsx_miscx_ctl_reg.u64 =
+                    cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+                if (pcsx_miscx_ctl_reg.s.mac_phy) {
+                        /* PHY Mode */
+                        union cvmx_pcsx_sgmx_an_adv_reg pcsx_sgmx_an_adv_reg;
+                        pcsx_sgmx_an_adv_reg.u64 =
+                            cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG
+                                          (index, interface));
+                        pcsx_sgmx_an_adv_reg.s.link = 1;
+                        pcsx_sgmx_an_adv_reg.s.dup = 1;
+                        pcsx_sgmx_an_adv_reg.s.speed = 2;
+                        cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG
+                                       (index, interface),
+                                       pcsx_sgmx_an_adv_reg.u64);
+                } else {
+                        /* MAC Mode - Nothing to do */
+                }
+        }
+        return 0;
+}
+
+/**
+ * Initialize the SERTES link for the first time or after a loss
+ * of link.
+ *
+ * @interface: Interface to init
+ * @index:     Index of prot on the interface
+ *
+ * Returns Zero on success, negative on failure
+ */
+static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index)
+{
+        union cvmx_pcsx_mrx_control_reg control_reg;
+
+        /*
+         * Take PCS through a reset sequence.
+         * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero.
+         * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the
+         * value of the other PCS*_MR*_CONTROL_REG bits).  Read
+         * PCS*_MR*_CONTROL_REG[RESET] until it changes value to
+         * zero.
+         */
+        control_reg.u64 =
+            cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
+        if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
+                control_reg.s.reset = 1;
+                cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
+                               control_reg.u64);
+                if (CVMX_WAIT_FOR_FIELD64
+                    (CVMX_PCSX_MRX_CONTROL_REG(index, interface),
+                     union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) {
+                        cvmx_dprintf("SGMII%d: Timeout waiting for port %d "
+                                     "to finish reset\n",
+                             interface, index);
+                        return -1;
+                }
+        }
+
+        /*
+         * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh
+         * sgmii negotiation starts.
+         */
+        control_reg.s.rst_an = 1;
+        control_reg.s.an_en = 1;
+        control_reg.s.pwr_dn = 0;
+        cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
+                       control_reg.u64);
+
+        /*
+         * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating
+         * that sgmii autonegotiation is complete. In MAC mode this
+         * isn't an ethernet link, but a link between Octeon and the
+         * PHY.
+         */
+        if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
+            CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface),
+                                  union cvmx_pcsx_mrx_status_reg, an_cpt, ==, 1,
+                                  10000)) {
+                /* cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); */
+                return -1;
+        }
+        return 0;
+}
+
+/**
+ * Configure an SGMII link to the specified speed after the SERTES
+ * link is up.
+ *
+ * @interface: Interface to init
+ * @index:     Index of prot on the interface
+ * @link_info: Link state to configure
+ *
+ * Returns Zero on success, negative on failure
+ */
+static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface,
+                                                        int index,
+                                                        cvmx_helper_link_info_t
+                                                        link_info)
+{
+        int is_enabled;
+        union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
+        union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
+
+        /* Disable GMX before we make any changes. Remember the enable state */
+        gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+        is_enabled = gmxx_prtx_cfg.s.en;
+        gmxx_prtx_cfg.s.en = 0;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
+
+        /* Wait for GMX to be idle */
+        if (CVMX_WAIT_FOR_FIELD64
+            (CVMX_GMXX_PRTX_CFG(index, interface), union cvmx_gmxx_prtx_cfg,
+             rx_idle, ==, 1, 10000)
+            || CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface),
+                                     union cvmx_gmxx_prtx_cfg, tx_idle, ==, 1,
+                                     10000)) {
+                cvmx_dprintf
+                    ("SGMII%d: Timeout waiting for port %d to be idle\n",
+                     interface, index);
+                return -1;
+        }
+
+        /* Read GMX CFG again to make sure the disable completed */
+        gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+
+        /*
+         * Get the misc control for PCS. We will need to set the
+         * duplication amount.
+         */
+        pcsx_miscx_ctl_reg.u64 =
+            cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+
+        /*
+         * Use GMXENO to force the link down if the status we get says
+         * it should be down.
+         */
+        pcsx_miscx_ctl_reg.s.gmxeno = !link_info.s.link_up;
+
+        /* Only change the duplex setting if the link is up */
+        if (link_info.s.link_up)
+                gmxx_prtx_cfg.s.duplex = link_info.s.full_duplex;
+
+        /* Do speed based setting for GMX */
+        switch (link_info.s.speed) {
+        case 10:
+                gmxx_prtx_cfg.s.speed = 0;
+                gmxx_prtx_cfg.s.speed_msb = 1;
+                gmxx_prtx_cfg.s.slottime = 0;
+                /* Setting from GMX-603 */
+                pcsx_miscx_ctl_reg.s.samp_pt = 25;
+                cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
+                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
+                break;
+        case 100:
+                gmxx_prtx_cfg.s.speed = 0;
+                gmxx_prtx_cfg.s.speed_msb = 0;
+                gmxx_prtx_cfg.s.slottime = 0;
+                pcsx_miscx_ctl_reg.s.samp_pt = 0x5;
+                cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64);
+                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
+                break;
+        case 1000:
+                gmxx_prtx_cfg.s.speed = 1;
+                gmxx_prtx_cfg.s.speed_msb = 0;
+                gmxx_prtx_cfg.s.slottime = 1;
+                pcsx_miscx_ctl_reg.s.samp_pt = 1;
+                cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512);
+                cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192);
+                break;
+        default:
+                break;
+        }
+
+        /* Write the new misc control for PCS */
+        cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
+                       pcsx_miscx_ctl_reg.u64);
+
+        /* Write the new GMX settings with the port still disabled */
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
+
+        /* Read GMX CFG again to make sure the config completed */
+        gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+
+        /* Restore the enabled / disabled state */
+        gmxx_prtx_cfg.s.en = is_enabled;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64);
+
+        return 0;
+}
+
+/**
+ * Bring up the SGMII interface to be ready for packet I/O but
+ * leave I/O disabled using the GMX override. This function
+ * follows the bringup documented in 10.6.3 of the manual.
+ *
+ * @interface: Interface to bringup
+ * @num_ports: Number of ports on the interface
+ *
+ * Returns Zero on success, negative on failure
+ */
+static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports)
+{
+        int index;
+
+        __cvmx_helper_setup_gmx(interface, num_ports);
+
+        for (index = 0; index < num_ports; index++) {
+                int ipd_port = cvmx_helper_get_ipd_port(interface, index);
+                __cvmx_helper_sgmii_hardware_init_one_time(interface, index);
+                __cvmx_helper_sgmii_link_set(ipd_port,
+                                             __cvmx_helper_sgmii_link_get
+                                             (ipd_port));
+
+        }
+
+        return 0;
+}
+
+/**
+ * Probe a SGMII interface and determine the number of ports
+ * connected to it. The SGMII interface should still be down after
+ * this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_sgmii_probe(int interface)
+{
+        union cvmx_gmxx_inf_mode mode;
+
+        /*
+         * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
+         * interface needs to be enabled before IPD otherwise per port
+         * backpressure may not work properly
+         */
+        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+        mode.s.en = 1;
+        cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
+        return 4;
+}
+
+/**
+ * Bringup and enable a SGMII interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+int __cvmx_helper_sgmii_enable(int interface)
+{
+        int num_ports = cvmx_helper_ports_on_interface(interface);
+        int index;
+
+        __cvmx_helper_sgmii_hardware_init(interface, num_ports);
+
+        for (index = 0; index < num_ports; index++) {
+                union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg;
+                gmxx_prtx_cfg.u64 =
+                    cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+                gmxx_prtx_cfg.s.en = 1;
+                cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
+                               gmxx_prtx_cfg.u64);
+                __cvmx_interrupt_pcsx_intx_en_reg_enable(index, interface);
+        }
+        __cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
+        __cvmx_interrupt_gmxx_enable(interface);
+        return 0;
+}
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port)
+{
+        cvmx_helper_link_info_t result;
+        union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg;
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+        union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg;
+
+        result.u64 = 0;
+
+        if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) {
+                /* The simulator gives you a simulated 1Gbps full duplex link */
+                result.s.link_up = 1;
+                result.s.full_duplex = 1;
+                result.s.speed = 1000;
+                return result;
+        }
+
+        pcsx_mrx_control_reg.u64 =
+            cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
+        if (pcsx_mrx_control_reg.s.loopbck1) {
+                /* Force 1Gbps full duplex link for internal loopback */
+                result.s.link_up = 1;
+                result.s.full_duplex = 1;
+                result.s.speed = 1000;
+                return result;
+        }
+
+        pcs_misc_ctl_reg.u64 =
+            cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+        if (pcs_misc_ctl_reg.s.mode) {
+                /* 1000BASE-X */
+                /* FIXME */
+        } else {
+                union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
+                pcsx_miscx_ctl_reg.u64 =
+                    cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+                if (pcsx_miscx_ctl_reg.s.mac_phy) {
+                        /* PHY Mode */
+                        union cvmx_pcsx_mrx_status_reg pcsx_mrx_status_reg;
+                        union cvmx_pcsx_anx_results_reg pcsx_anx_results_reg;
+
+                        /*
+                         * Don't bother continuing if the SERTES low
+                         * level link is down
+                         */
+                        pcsx_mrx_status_reg.u64 =
+                            cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG
+                                          (index, interface));
+                        if (pcsx_mrx_status_reg.s.lnk_st == 0) {
+                                if (__cvmx_helper_sgmii_hardware_init_link
+                                    (interface, index) != 0)
+                                        return result;
+                        }
+
+                        /* Read the autoneg results */
+                        pcsx_anx_results_reg.u64 =
+                            cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG
+                                          (index, interface));
+                        if (pcsx_anx_results_reg.s.an_cpt) {
+                                /*
+                                 * Auto negotiation is complete. Set
+                                 * status accordingly.
+                                 */
+                                result.s.full_duplex =
+                                    pcsx_anx_results_reg.s.dup;
+                                result.s.link_up =
+                                    pcsx_anx_results_reg.s.link_ok;
+                                switch (pcsx_anx_results_reg.s.spd) {
+                                case 0:
+                                        result.s.speed = 10;
+                                        break;
+                                case 1:
+                                        result.s.speed = 100;
+                                        break;
+                                case 2:
+                                        result.s.speed = 1000;
+                                        break;
+                                default:
+                                        result.s.speed = 0;
+                                        result.s.link_up = 0;
+                                        break;
+                                }
+                        } else {
+                                /*
+                                 * Auto negotiation isn't
+                                 * complete. Return link down.
+                                 */
+                                result.s.speed = 0;
+                                result.s.link_up = 0;
+                        }
+                } else {        /* MAC Mode */
+
+                        result = __cvmx_helper_board_link_get(ipd_port);
+                }
+        }
+        return result;
+}
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+int __cvmx_helper_sgmii_link_set(int ipd_port,
+                                 cvmx_helper_link_info_t link_info)
+{
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+        __cvmx_helper_sgmii_hardware_init_link(interface, index);
+        return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index,
+                                                            link_info);
+}
+
+/**
+ * Configure a port for internal and/or external loopback. Internal
+ * loopback causes packets sent by the port to be received by
+ * Octeon. External loopback causes packets received from the wire to
+ * sent out again.
+ *
+ * @ipd_port: IPD/PKO port to loopback.
+ * @enable_internal:
+ *                 Non zero if you want internal loopback
+ * @enable_external:
+ *                 Non zero if you want external loopback
+ *
+ * Returns Zero on success, negative on failure.
+ */
+int __cvmx_helper_sgmii_configure_loopback(int ipd_port, int enable_internal,
+                                           int enable_external)
+{
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+        union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg;
+        union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
+
+        pcsx_mrx_control_reg.u64 =
+            cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
+        pcsx_mrx_control_reg.s.loopbck1 = enable_internal;
+        cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
+                       pcsx_mrx_control_reg.u64);
+
+        pcsx_miscx_ctl_reg.u64 =
+            cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
+        pcsx_miscx_ctl_reg.s.loopbck2 = enable_external;
+        cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
+                       pcsx_miscx_ctl_reg.u64);
+
+        __cvmx_helper_sgmii_hardware_init_link(interface, index);
+        return 0;
+}
diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.h b/drivers/staging/octeon/cvmx-helper-sgmii.h
new file mode 100644
index 000000000000..19b48d60857f
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-sgmii.h
@@ -0,0 +1,104 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for SGMII initialization, configuration,
+ * and monitoring.
+ *
+ */
+#ifndef __CVMX_HELPER_SGMII_H__
+#define __CVMX_HELPER_SGMII_H__
+
+/**
+ * Probe a SGMII interface and determine the number of ports
+ * connected to it. The SGMII interface should still be down after
+ * this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_sgmii_probe(int interface);
+
+/**
+ * Bringup and enable a SGMII interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_sgmii_enable(int interface);
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port);
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_sgmii_link_set(int ipd_port,
+                                        cvmx_helper_link_info_t link_info);
+
+/**
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @ipd_port: IPD/PKO port to loopback.
+ * @enable_internal:
+ *                 Non zero if you want internal loopback
+ * @enable_external:
+ *                 Non zero if you want external loopback
+ *
+ * Returns Zero on success, negative on failure.
+ */
+extern int __cvmx_helper_sgmii_configure_loopback(int ipd_port,
+                                                  int enable_internal,
+                                                  int enable_external);
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-helper-spi.c b/drivers/staging/octeon/cvmx-helper-spi.c
new file mode 100644
index 000000000000..8ba6c832471e
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-spi.c
@@ -0,0 +1,195 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+void __cvmx_interrupt_gmxx_enable(int interface);
+void __cvmx_interrupt_spxx_int_msk_enable(int index);
+void __cvmx_interrupt_stxx_int_msk_enable(int index);
+
+/*
+ * Functions for SPI initialization, configuration,
+ * and monitoring.
+ */
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-config.h"
+#include "cvmx-spi.h"
+#include "cvmx-helper.h"
+
+#include "cvmx-pip-defs.h"
+#include "cvmx-pko-defs.h"
+
+/*
+ * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI
+ * initialization routines wait for SPI training. You can override the
+ * value using executive-config.h if necessary.
+ */
+#ifndef CVMX_HELPER_SPI_TIMEOUT
+#define CVMX_HELPER_SPI_TIMEOUT 10
+#endif
+
+/**
+ * Probe a SPI interface and determine the number of ports
+ * connected to it. The SPI interface should still be down after
+ * this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_spi_probe(int interface)
+{
+        int num_ports = 0;
+
+        if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) &&
+            cvmx_spi4000_is_present(interface)) {
+                num_ports = 10;
+        } else {
+                union cvmx_pko_reg_crc_enable enable;
+                num_ports = 16;
+                /*
+                 * Unlike the SPI4000, most SPI devices don't
+                 * automatically put on the L2 CRC. For everything
+                 * except for the SPI4000 have PKO append the L2 CRC
+                 * to the packet.
+                 */
+                enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE);
+                enable.s.enable |= 0xffff << (interface * 16);
+                cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64);
+        }
+        __cvmx_helper_setup_gmx(interface, num_ports);
+        return num_ports;
+}
+
+/**
+ * Bringup and enable a SPI interface. After this call packet I/O
+ * should be fully functional. This is called with IPD enabled but
+ * PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+int __cvmx_helper_spi_enable(int interface)
+{
+        /*
+         * Normally the ethernet L2 CRC is checked and stripped in the
+         * GMX block.  When you are using SPI, this isn' the case and
+         * IPD needs to check the L2 CRC.
+         */
+        int num_ports = cvmx_helper_ports_on_interface(interface);
+        int ipd_port;
+        for (ipd_port = interface * 16; ipd_port < interface * 16 + num_ports;
+             ipd_port++) {
+                union cvmx_pip_prt_cfgx port_config;
+                port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+                port_config.s.crc_en = 1;
+                cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64);
+        }
+
+        if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) {
+                cvmx_spi_start_interface(interface, CVMX_SPI_MODE_DUPLEX,
+                                         CVMX_HELPER_SPI_TIMEOUT, num_ports);
+                if (cvmx_spi4000_is_present(interface))
+                        cvmx_spi4000_initialize(interface);
+        }
+        __cvmx_interrupt_spxx_int_msk_enable(interface);
+        __cvmx_interrupt_stxx_int_msk_enable(interface);
+        __cvmx_interrupt_gmxx_enable(interface);
+        return 0;
+}
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port)
+{
+        cvmx_helper_link_info_t result;
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+        result.u64 = 0;
+
+        if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) {
+                /* The simulator gives you a simulated full duplex link */
+                result.s.link_up = 1;
+                result.s.full_duplex = 1;
+                result.s.speed = 10000;
+        } else if (cvmx_spi4000_is_present(interface)) {
+                union cvmx_gmxx_rxx_rx_inbnd inband =
+                    cvmx_spi4000_check_speed(interface, index);
+                result.s.link_up = inband.s.status;
+                result.s.full_duplex = inband.s.duplex;
+                switch (inband.s.speed) {
+                case 0: /* 10 Mbps */
+                        result.s.speed = 10;
+                        break;
+                case 1: /* 100 Mbps */
+                        result.s.speed = 100;
+                        break;
+                case 2: /* 1 Gbps */
+                        result.s.speed = 1000;
+                        break;
+                case 3: /* Illegal */
+                        result.s.speed = 0;
+                        result.s.link_up = 0;
+                        break;
+                }
+        } else {
+                /* For generic SPI we can't determine the link, just return some
+                   sane results */
+                result.s.link_up = 1;
+                result.s.full_duplex = 1;
+                result.s.speed = 10000;
+        }
+        return result;
+}
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+int __cvmx_helper_spi_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
+{
+        /* Nothing to do. If we have a SPI4000 then the setup was already performed
+           by cvmx_spi4000_check_speed(). If not then there isn't any link
+           info */
+        return 0;
+}
diff --git a/drivers/staging/octeon/cvmx-helper-spi.h b/drivers/staging/octeon/cvmx-helper-spi.h
new file mode 100644
index 000000000000..69bac036d10e
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-spi.h
@@ -0,0 +1,84 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Functions for SPI initialization, configuration,
+ * and monitoring.
+ */
+#ifndef __CVMX_HELPER_SPI_H__
+#define __CVMX_HELPER_SPI_H__
+
+/**
+ * Probe a SPI interface and determine the number of ports
+ * connected to it. The SPI interface should still be down after
+ * this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_spi_probe(int interface);
+
+/**
+ * Bringup and enable a SPI interface. After this call packet I/O
+ * should be fully functional. This is called with IPD enabled but
+ * PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_spi_enable(int interface);
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port);
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_spi_link_set(int ipd_port,
+                                      cvmx_helper_link_info_t link_info);
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-helper-util.c b/drivers/staging/octeon/cvmx-helper-util.c
new file mode 100644
index 000000000000..41ef8a40bb03
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-util.c
@@ -0,0 +1,433 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Small helper utilities.
+ */
+#include <linux/kernel.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-config.h"
+
+#include "cvmx-fpa.h"
+#include "cvmx-pip.h"
+#include "cvmx-pko.h"
+#include "cvmx-ipd.h"
+#include "cvmx-spi.h"
+
+#include "cvmx-helper.h"
+#include "cvmx-helper-util.h"
+
+#include <asm/octeon/cvmx-ipd-defs.h>
+
+/**
+ * Convert a interface mode into a human readable string
+ *
+ * @mode:   Mode to convert
+ *
+ * Returns String
+ */
+const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t
+                                                 mode)
+{
+        switch (mode) {
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+                return "DISABLED";
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+                return "RGMII";
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+                return "GMII";
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+                return "SPI";
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+                return "PCIE";
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+                return "XAUI";
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+                return "SGMII";
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                return "PICMG";
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+                return "NPI";
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                return "LOOP";
+        }
+        return "UNKNOWN";
+}
+
+/**
+ * Debug routine to dump the packet structure to the console
+ *
+ * @work:   Work queue entry containing the packet to dump
+ * Returns
+ */
+int cvmx_helper_dump_packet(cvmx_wqe_t *work)
+{
+        uint64_t count;
+        uint64_t remaining_bytes;
+        union cvmx_buf_ptr buffer_ptr;
+        uint64_t start_of_buffer;
+        uint8_t *data_address;
+        uint8_t *end_of_data;
+
+        cvmx_dprintf("Packet Length:   %u\n", work->len);
+        cvmx_dprintf("    Input Port:  %u\n", work->ipprt);
+        cvmx_dprintf("    QoS:         %u\n", work->qos);
+        cvmx_dprintf("    Buffers:     %u\n", work->word2.s.bufs);
+
+        if (work->word2.s.bufs == 0) {
+                union cvmx_ipd_wqe_fpa_queue wqe_pool;
+                wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE);
+                buffer_ptr.u64 = 0;
+                buffer_ptr.s.pool = wqe_pool.s.wqe_pool;
+                buffer_ptr.s.size = 128;
+                buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data);
+                if (likely(!work->word2.s.not_IP)) {
+                        union cvmx_pip_ip_offset pip_ip_offset;
+                        pip_ip_offset.u64 = cvmx_read_csr(CVMX_PIP_IP_OFFSET);
+                        buffer_ptr.s.addr +=
+                            (pip_ip_offset.s.offset << 3) -
+                            work->word2.s.ip_offset;
+                        buffer_ptr.s.addr += (work->word2.s.is_v6 ^ 1) << 2;
+                } else {
+                        /*
+                         * WARNING: This code assumes that the packet
+                         * is not RAW. If it was, we would use
+                         * PIP_GBL_CFG[RAW_SHF] instead of
+                         * PIP_GBL_CFG[NIP_SHF].
+                         */
+                        union cvmx_pip_gbl_cfg pip_gbl_cfg;
+                        pip_gbl_cfg.u64 = cvmx_read_csr(CVMX_PIP_GBL_CFG);
+                        buffer_ptr.s.addr += pip_gbl_cfg.s.nip_shf;
+                }
+        } else
+                buffer_ptr = work->packet_ptr;
+        remaining_bytes = work->len;
+
+        while (remaining_bytes) {
+                start_of_buffer =
+                    ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
+                cvmx_dprintf("    Buffer Start:%llx\n",
+                             (unsigned long long)start_of_buffer);
+                cvmx_dprintf("    Buffer I   : %u\n", buffer_ptr.s.i);
+                cvmx_dprintf("    Buffer Back: %u\n", buffer_ptr.s.back);
+                cvmx_dprintf("    Buffer Pool: %u\n", buffer_ptr.s.pool);
+                cvmx_dprintf("    Buffer Data: %llx\n",
+                             (unsigned long long)buffer_ptr.s.addr);
+                cvmx_dprintf("    Buffer Size: %u\n", buffer_ptr.s.size);
+
+                cvmx_dprintf("\t\t");
+                data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr);
+                end_of_data = data_address + buffer_ptr.s.size;
+                count = 0;
+                while (data_address < end_of_data) {
+                        if (remaining_bytes == 0)
+                                break;
+                        else
+                                remaining_bytes--;
+                        cvmx_dprintf("%02x", (unsigned int)*data_address);
+                        data_address++;
+                        if (remaining_bytes && (count == 7)) {
+                                cvmx_dprintf("\n\t\t");
+                                count = 0;
+                        } else
+                                count++;
+                }
+                cvmx_dprintf("\n");
+
+                if (remaining_bytes)
+                        buffer_ptr = *(union cvmx_buf_ptr *)
+                                cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
+        }
+        return 0;
+}
+
+/**
+ * Setup Random Early Drop on a specific input queue
+ *
+ * @queue:  Input queue to setup RED on (0-7)
+ * @pass_thresh:
+ *               Packets will begin slowly dropping when there are less than
+ *               this many packet buffers free in FPA 0.
+ * @drop_thresh:
+ *               All incomming packets will be dropped when there are less
+ *               than this many free packet buffers in FPA 0.
+ * Returns Zero on success. Negative on failure
+ */
+int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
+{
+        union cvmx_ipd_qosx_red_marks red_marks;
+        union cvmx_ipd_red_quex_param red_param;
+
+        /* Set RED to begin dropping packets when there are pass_thresh buffers
+           left. It will linearly drop more packets until reaching drop_thresh
+           buffers */
+        red_marks.u64 = 0;
+        red_marks.s.drop = drop_thresh;
+        red_marks.s.pass = pass_thresh;
+        cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64);
+
+        /* Use the actual queue 0 counter, not the average */
+        red_param.u64 = 0;
+        red_param.s.prb_con =
+            (255ul << 24) / (red_marks.s.pass - red_marks.s.drop);
+        red_param.s.avg_con = 1;
+        red_param.s.new_con = 255;
+        red_param.s.use_pcnt = 1;
+        cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64);
+        return 0;
+}
+
+/**
+ * Setup Random Early Drop to automatically begin dropping packets.
+ *
+ * @pass_thresh:
+ *               Packets will begin slowly dropping when there are less than
+ *               this many packet buffers free in FPA 0.
+ * @drop_thresh:
+ *               All incomming packets will be dropped when there are less
+ *               than this many free packet buffers in FPA 0.
+ * Returns Zero on success. Negative on failure
+ */
+int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
+{
+        union cvmx_ipd_portx_bp_page_cnt page_cnt;
+        union cvmx_ipd_bp_prt_red_end ipd_bp_prt_red_end;
+        union cvmx_ipd_red_port_enable red_port_enable;
+        int queue;
+        int interface;
+        int port;
+
+        /* Disable backpressure based on queued buffers. It needs SW support */
+        page_cnt.u64 = 0;
+        page_cnt.s.bp_enb = 0;
+        page_cnt.s.page_cnt = 100;
+        for (interface = 0; interface < 2; interface++) {
+                for (port = cvmx_helper_get_first_ipd_port(interface);
+                     port < cvmx_helper_get_last_ipd_port(interface); port++)
+                        cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port),
+                                       page_cnt.u64);
+        }
+
+        for (queue = 0; queue < 8; queue++)
+                cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh);
+
+        /* Shutoff the dropping based on the per port page count. SW isn't
+           decrementing it right now */
+        ipd_bp_prt_red_end.u64 = 0;
+        ipd_bp_prt_red_end.s.prt_enb = 0;
+        cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64);
+
+        red_port_enable.u64 = 0;
+        red_port_enable.s.prt_enb = 0xfffffffffull;
+        red_port_enable.s.avg_dly = 10000;
+        red_port_enable.s.prb_dly = 10000;
+        cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);
+
+        return 0;
+}
+
+/**
+ * Setup the common GMX settings that determine the number of
+ * ports. These setting apply to almost all configurations of all
+ * chips.
+ *
+ * @interface: Interface to configure
+ * @num_ports: Number of ports on the interface
+ *
+ * Returns Zero on success, negative on failure
+ */
+int __cvmx_helper_setup_gmx(int interface, int num_ports)
+{
+        union cvmx_gmxx_tx_prts gmx_tx_prts;
+        union cvmx_gmxx_rx_prts gmx_rx_prts;
+        union cvmx_pko_reg_gmx_port_mode pko_mode;
+        union cvmx_gmxx_txx_thresh gmx_tx_thresh;
+        int index;
+
+        /* Tell GMX the number of TX ports on this interface */
+        gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface));
+        gmx_tx_prts.s.prts = num_ports;
+        cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64);
+
+        /* Tell GMX the number of RX ports on this interface.  This only
+         ** applies to *GMII and XAUI ports */
+        if (cvmx_helper_interface_get_mode(interface) ==
+            CVMX_HELPER_INTERFACE_MODE_RGMII
+            || cvmx_helper_interface_get_mode(interface) ==
+            CVMX_HELPER_INTERFACE_MODE_SGMII
+            || cvmx_helper_interface_get_mode(interface) ==
+            CVMX_HELPER_INTERFACE_MODE_GMII
+            || cvmx_helper_interface_get_mode(interface) ==
+            CVMX_HELPER_INTERFACE_MODE_XAUI) {
+                if (num_ports > 4) {
+                        cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal "
+                                     "num_ports\n");
+                        return -1;
+                }
+
+                gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface));
+                gmx_rx_prts.s.prts = num_ports;
+                cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64);
+        }
+
+        /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */
+        if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX)
+            && !OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                /* Tell PKO the number of ports on this interface */
+                pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE);
+                if (interface == 0) {
+                        if (num_ports == 1)
+                                pko_mode.s.mode0 = 4;
+                        else if (num_ports == 2)
+                                pko_mode.s.mode0 = 3;
+                        else if (num_ports <= 4)
+                                pko_mode.s.mode0 = 2;
+                        else if (num_ports <= 8)
+                                pko_mode.s.mode0 = 1;
+                        else
+                                pko_mode.s.mode0 = 0;
+                } else {
+                        if (num_ports == 1)
+                                pko_mode.s.mode1 = 4;
+                        else if (num_ports == 2)
+                                pko_mode.s.mode1 = 3;
+                        else if (num_ports <= 4)
+                                pko_mode.s.mode1 = 2;
+                        else if (num_ports <= 8)
+                                pko_mode.s.mode1 = 1;
+                        else
+                                pko_mode.s.mode1 = 0;
+                }
+                cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64);
+        }
+
+        /*
+         * Set GMX to buffer as much data as possible before starting
+         * transmit.  This reduces the chances that we have a TX under
+         * run due to memory contention. Any packet that fits entirely
+         * in the GMX FIFO can never have an under run regardless of
+         * memory load.
+         */
+        gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface));
+        if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)
+            || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                /* These chips have a fixed max threshold of 0x40 */
+                gmx_tx_thresh.s.cnt = 0x40;
+        } else {
+                /* Choose the max value for the number of ports */
+                if (num_ports <= 1)
+                        gmx_tx_thresh.s.cnt = 0x100 / 1;
+                else if (num_ports == 2)
+                        gmx_tx_thresh.s.cnt = 0x100 / 2;
+                else
+                        gmx_tx_thresh.s.cnt = 0x100 / 4;
+        }
+        /*
+         * SPI and XAUI can have lots of ports but the GMX hardware
+         * only ever has a max of 4.
+         */
+        if (num_ports > 4)
+                num_ports = 4;
+        for (index = 0; index < num_ports; index++)
+                cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface),
+                               gmx_tx_thresh.u64);
+
+        return 0;
+}
+
+/**
+ * Returns the IPD/PKO port number for a port on teh given
+ * interface.
+ *
+ * @interface: Interface to use
+ * @port:      Port on the interface
+ *
+ * Returns IPD/PKO port number
+ */
+int cvmx_helper_get_ipd_port(int interface, int port)
+{
+        switch (interface) {
+        case 0:
+                return port;
+        case 1:
+                return port + 16;
+        case 2:
+                return port + 32;
+        case 3:
+                return port + 36;
+        }
+        return -1;
+}
+
+/**
+ * Returns the interface number for an IPD/PKO port number.
+ *
+ * @ipd_port: IPD/PKO port number
+ *
+ * Returns Interface number
+ */
+int cvmx_helper_get_interface_num(int ipd_port)
+{
+        if (ipd_port < 16)
+                return 0;
+        else if (ipd_port < 32)
+                return 1;
+        else if (ipd_port < 36)
+                return 2;
+        else if (ipd_port < 40)
+                return 3;
+        else
+                cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD "
+                             "port number\n");
+
+        return -1;
+}
+
+/**
+ * Returns the interface index number for an IPD/PKO port
+ * number.
+ *
+ * @ipd_port: IPD/PKO port number
+ *
+ * Returns Interface index number
+ */
+int cvmx_helper_get_interface_index_num(int ipd_port)
+{
+        if (ipd_port < 32)
+                return ipd_port & 15;
+        else if (ipd_port < 36)
+                return ipd_port & 3;
+        else if (ipd_port < 40)
+                return ipd_port & 3;
+        else
+                cvmx_dprintf("cvmx_helper_get_interface_index_num: "
+                             "Illegal IPD port number\n");
+
+        return -1;
+}
diff --git a/drivers/staging/octeon/cvmx-helper-util.h b/drivers/staging/octeon/cvmx-helper-util.h
new file mode 100644
index 000000000000..6a6e52fc22c1
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-util.h
@@ -0,0 +1,215 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * Small helper utilities.
+ *
+ */
+
+#ifndef __CVMX_HELPER_UTIL_H__
+#define __CVMX_HELPER_UTIL_H__
+
+/**
+ * Convert a interface mode into a human readable string
+ *
+ * @mode:   Mode to convert
+ *
+ * Returns String
+ */
+extern const char
+    *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode);
+
+/**
+ * Debug routine to dump the packet structure to the console
+ *
+ * @work:   Work queue entry containing the packet to dump
+ * Returns
+ */
+extern int cvmx_helper_dump_packet(cvmx_wqe_t *work);
+
+/**
+ * Setup Random Early Drop on a specific input queue
+ *
+ * @queue:  Input queue to setup RED on (0-7)
+ * @pass_thresh:
+ *               Packets will begin slowly dropping when there are less than
+ *               this many packet buffers free in FPA 0.
+ * @drop_thresh:
+ *               All incomming packets will be dropped when there are less
+ *               than this many free packet buffers in FPA 0.
+ * Returns Zero on success. Negative on failure
+ */
+extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh,
+                                       int drop_thresh);
+
+/**
+ * Setup Random Early Drop to automatically begin dropping packets.
+ *
+ * @pass_thresh:
+ *               Packets will begin slowly dropping when there are less than
+ *               this many packet buffers free in FPA 0.
+ * @drop_thresh:
+ *               All incomming packets will be dropped when there are less
+ *               than this many free packet buffers in FPA 0.
+ * Returns Zero on success. Negative on failure
+ */
+extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);
+
+/**
+ * Get the version of the CVMX libraries.
+ *
+ * Returns Version string. Note this buffer is allocated statically
+ *         and will be shared by all callers.
+ */
+extern const char *cvmx_helper_get_version(void);
+
+/**
+ * Setup the common GMX settings that determine the number of
+ * ports. These setting apply to almost all configurations of all
+ * chips.
+ *
+ * @interface: Interface to configure
+ * @num_ports: Number of ports on the interface
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_setup_gmx(int interface, int num_ports);
+
+/**
+ * Returns the IPD/PKO port number for a port on the given
+ * interface.
+ *
+ * @interface: Interface to use
+ * @port:      Port on the interface
+ *
+ * Returns IPD/PKO port number
+ */
+extern int cvmx_helper_get_ipd_port(int interface, int port);
+
+/**
+ * Returns the IPD/PKO port number for the first port on the given
+ * interface.
+ *
+ * @interface: Interface to use
+ *
+ * Returns IPD/PKO port number
+ */
+static inline int cvmx_helper_get_first_ipd_port(int interface)
+{
+        return cvmx_helper_get_ipd_port(interface, 0);
+}
+
+/**
+ * Returns the IPD/PKO port number for the last port on the given
+ * interface.
+ *
+ * @interface: Interface to use
+ *
+ * Returns IPD/PKO port number
+ */
+static inline int cvmx_helper_get_last_ipd_port(int interface)
+{
+        extern int cvmx_helper_ports_on_interface(int interface);
+
+        return cvmx_helper_get_first_ipd_port(interface) +
+               cvmx_helper_ports_on_interface(interface) - 1;
+}
+
+/**
+ * Free the packet buffers contained in a work queue entry.
+ * The work queue entry is not freed.
+ *
+ * @work:   Work queue entry with packet to free
+ */
+static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work)
+{
+        uint64_t number_buffers;
+        union cvmx_buf_ptr buffer_ptr;
+        union cvmx_buf_ptr next_buffer_ptr;
+        uint64_t start_of_buffer;
+
+        number_buffers = work->word2.s.bufs;
+        if (number_buffers == 0)
+                return;
+        buffer_ptr = work->packet_ptr;
+
+        /*
+         * Since the number of buffers is not zero, we know this is
+         * not a dynamic short packet. We need to check if it is a
+         * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is
+         * true, we need to free all buffers except for the first
+         * one. The caller doesn't expect their WQE pointer to be
+         * freed
+         */
+        start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
+        if (cvmx_ptr_to_phys(work) == start_of_buffer) {
+                next_buffer_ptr =
+                    *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
+                buffer_ptr = next_buffer_ptr;
+                number_buffers--;
+        }
+
+        while (number_buffers--) {
+                /*
+                 * Remember the back pointer is in cache lines, not
+                 * 64bit words
+                 */
+                start_of_buffer =
+                    ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
+                /*
+                 * Read pointer to next buffer before we free the
+                 * current buffer.
+                 */
+                next_buffer_ptr =
+                    *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
+                cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer),
+                              buffer_ptr.s.pool, 0);
+                buffer_ptr = next_buffer_ptr;
+        }
+}
+
+/**
+ * Returns the interface number for an IPD/PKO port number.
+ *
+ * @ipd_port: IPD/PKO port number
+ *
+ * Returns Interface number
+ */
+extern int cvmx_helper_get_interface_num(int ipd_port);
+
+/**
+ * Returns the interface index number for an IPD/PKO port
+ * number.
+ *
+ * @ipd_port: IPD/PKO port number
+ *
+ * Returns Interface index number
+ */
+extern int cvmx_helper_get_interface_index_num(int ipd_port);
+
+#endif /* __CVMX_HELPER_H__ */
diff --git a/drivers/staging/octeon/cvmx-helper-xaui.c b/drivers/staging/octeon/cvmx-helper-xaui.c
new file mode 100644
index 000000000000..a11e6769e234
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-xaui.c
@@ -0,0 +1,348 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Functions for XAUI initialization, configuration,
+ * and monitoring.
+ *
+ */
+
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-config.h"
+
+#include "cvmx-helper.h"
+
+#include "cvmx-pko-defs.h"
+#include "cvmx-gmxx-defs.h"
+#include "cvmx-pcsxx-defs.h"
+
+void __cvmx_interrupt_gmxx_enable(int interface);
+void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block);
+void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);
+/**
+ * Probe a XAUI interface and determine the number of ports
+ * connected to it. The XAUI interface should still be down
+ * after this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+int __cvmx_helper_xaui_probe(int interface)
+{
+        int i;
+        union cvmx_gmxx_hg2_control gmx_hg2_control;
+        union cvmx_gmxx_inf_mode mode;
+
+        /*
+         * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the
+         * interface needs to be enabled before IPD otherwise per port
+         * backpressure may not work properly.
+         */
+        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+        mode.s.en = 1;
+        cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64);
+
+        __cvmx_helper_setup_gmx(interface, 1);
+
+        /*
+         * Setup PKO to support 16 ports for HiGig2 virtual
+         * ports. We're pointing all of the PKO packet ports for this
+         * interface to the XAUI. This allows us to use HiGig2
+         * backpressure per port.
+         */
+        for (i = 0; i < 16; i++) {
+                union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs;
+                pko_mem_port_ptrs.u64 = 0;
+                /*
+                 * We set each PKO port to have equal priority in a
+                 * round robin fashion.
+                 */
+                pko_mem_port_ptrs.s.static_p = 0;
+                pko_mem_port_ptrs.s.qos_mask = 0xff;
+                /* All PKO ports map to the same XAUI hardware port */
+                pko_mem_port_ptrs.s.eid = interface * 4;
+                pko_mem_port_ptrs.s.pid = interface * 16 + i;
+                cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64);
+        }
+
+        /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */
+        gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface));
+        if (gmx_hg2_control.s.hg2tx_en)
+                return 16;
+        else
+                return 1;
+}
+
+/**
+ * Bringup and enable a XAUI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+int __cvmx_helper_xaui_enable(int interface)
+{
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        union cvmx_pcsxx_control1_reg xauiCtl;
+        union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl;
+        union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl;
+        union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
+        union cvmx_gmxx_tx_int_en gmx_tx_int_en;
+        union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
+
+        /* (1) Interface has already been enabled. */
+
+        /* (2) Disable GMX. */
+        xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface));
+        xauiMiscCtl.s.gmxeno = 1;
+        cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
+
+        /* (3) Disable GMX and PCSX interrupts. */
+        gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface));
+        cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
+        gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface));
+        cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
+        pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface));
+        cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
+
+        /* (4) Bring up the PCSX and GMX reconciliation layer. */
+        /* (4)a Set polarity and lane swapping. */
+        /* (4)b */
+        gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
+        /* Enable better IFG packing and improves performance */
+        gmxXauiTxCtl.s.dic_en = 1;
+        gmxXauiTxCtl.s.uni_en = 0;
+        cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64);
+
+        /* (4)c Aply reset sequence */
+        xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
+        xauiCtl.s.lo_pwr = 0;
+        xauiCtl.s.reset = 1;
+        cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64);
+
+        /* Wait for PCS to come out of reset */
+        if (CVMX_WAIT_FOR_FIELD64
+            (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg,
+             reset, ==, 0, 10000))
+                return -1;
+        /* Wait for PCS to be aligned */
+        if (CVMX_WAIT_FOR_FIELD64
+            (CVMX_PCSXX_10GBX_STATUS_REG(interface),
+             union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000))
+                return -1;
+        /* Wait for RX to be ready */
+        if (CVMX_WAIT_FOR_FIELD64
+            (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl,
+                    status, ==, 0, 10000))
+                return -1;
+
+        /* (6) Configure GMX */
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
+        gmx_cfg.s.en = 0;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+
+        /* Wait for GMX RX to be idle */
+        if (CVMX_WAIT_FOR_FIELD64
+            (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
+                    rx_idle, ==, 1, 10000))
+                return -1;
+        /* Wait for GMX TX to be idle */
+        if (CVMX_WAIT_FOR_FIELD64
+            (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg,
+                    tx_idle, ==, 1, 10000))
+                return -1;
+
+        /* GMX configure */
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
+        gmx_cfg.s.speed = 1;
+        gmx_cfg.s.speed_msb = 0;
+        gmx_cfg.s.slottime = 1;
+        cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1);
+        cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512);
+        cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192);
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+
+        /* (7) Clear out any error state */
+        cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface),
+                       cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface)));
+        cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface),
+                       cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface)));
+        cvmx_write_csr(CVMX_PCSXX_INT_REG(interface),
+                       cvmx_read_csr(CVMX_PCSXX_INT_REG(interface)));
+
+        /* Wait for receive link */
+        if (CVMX_WAIT_FOR_FIELD64
+            (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg,
+             rcv_lnk, ==, 1, 10000))
+                return -1;
+        if (CVMX_WAIT_FOR_FIELD64
+            (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
+             xmtflt, ==, 0, 10000))
+                return -1;
+        if (CVMX_WAIT_FOR_FIELD64
+            (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg,
+             rcvflt, ==, 0, 10000))
+                return -1;
+
+        cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64);
+        cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
+        cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
+
+        cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0));
+
+        /* (8) Enable packet reception */
+        xauiMiscCtl.s.gmxeno = 0;
+        cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
+
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface));
+        gmx_cfg.s.en = 1;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64);
+
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface);
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface);
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface);
+        __cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface);
+        __cvmx_interrupt_pcsxx_int_en_reg_enable(interface);
+        __cvmx_interrupt_gmxx_enable(interface);
+
+        return 0;
+}
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port)
+{
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
+        union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
+        union cvmx_pcsxx_status1_reg pcsxx_status1_reg;
+        cvmx_helper_link_info_t result;
+
+        gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
+        gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
+        pcsxx_status1_reg.u64 =
+            cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface));
+        result.u64 = 0;
+
+        /* Only return a link if both RX and TX are happy */
+        if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) &&
+            (pcsxx_status1_reg.s.rcv_lnk == 1)) {
+                result.s.link_up = 1;
+                result.s.full_duplex = 1;
+                result.s.speed = 10000;
+        } else {
+                /* Disable GMX and PCSX interrupts. */
+                cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0);
+                cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0);
+                cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0);
+        }
+        return result;
+}
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
+{
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl;
+        union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl;
+
+        gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface));
+        gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface));
+
+        /* If the link shouldn't be up, then just return */
+        if (!link_info.s.link_up)
+                return 0;
+
+        /* Do nothing if both RX and TX are happy */
+        if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0))
+                return 0;
+
+        /* Bring the link up */
+        return __cvmx_helper_xaui_enable(interface);
+}
+
+/**
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @ipd_port: IPD/PKO port to loopback.
+ * @enable_internal:
+ *                 Non zero if you want internal loopback
+ * @enable_external:
+ *                 Non zero if you want external loopback
+ *
+ * Returns Zero on success, negative on failure.
+ */
+extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
+                                                 int enable_internal,
+                                                 int enable_external)
+{
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        union cvmx_pcsxx_control1_reg pcsxx_control1_reg;
+        union cvmx_gmxx_xaui_ext_loopback gmxx_xaui_ext_loopback;
+
+        /* Set the internal loop */
+        pcsxx_control1_reg.u64 =
+            cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface));
+        pcsxx_control1_reg.s.loopbck1 = enable_internal;
+        cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface),
+                       pcsxx_control1_reg.u64);
+
+        /* Set the external loop */
+        gmxx_xaui_ext_loopback.u64 =
+            cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface));
+        gmxx_xaui_ext_loopback.s.en = enable_external;
+        cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface),
+                       gmxx_xaui_ext_loopback.u64);
+
+        /* Take the link through a reset */
+        return __cvmx_helper_xaui_enable(interface);
+}
diff --git a/drivers/staging/octeon/cvmx-helper-xaui.h b/drivers/staging/octeon/cvmx-helper-xaui.h
new file mode 100644
index 000000000000..4b4db2f93cd4
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper-xaui.h
@@ -0,0 +1,103 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * @file
+ *
+ * Functions for XAUI initialization, configuration,
+ * and monitoring.
+ *
+ */
+#ifndef __CVMX_HELPER_XAUI_H__
+#define __CVMX_HELPER_XAUI_H__
+
+/**
+ * Probe a XAUI interface and determine the number of ports
+ * connected to it. The XAUI interface should still be down
+ * after this call.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Number of ports on the interface. Zero to disable.
+ */
+extern int __cvmx_helper_xaui_probe(int interface);
+
+/**
+ * Bringup and enable a XAUI interface. After this call packet
+ * I/O should be fully functional. This is called with IPD
+ * enabled but PKO disabled.
+ *
+ * @interface: Interface to bring up
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_xaui_enable(int interface);
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+extern cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port);
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int __cvmx_helper_xaui_link_set(int ipd_port,
+                                       cvmx_helper_link_info_t link_info);
+
+/**
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @ipd_port: IPD/PKO port to loopback.
+ * @enable_internal:
+ *                 Non zero if you want internal loopback
+ * @enable_external:
+ *                 Non zero if you want external loopback
+ *
+ * Returns Zero on success, negative on failure.
+ */
+extern int __cvmx_helper_xaui_configure_loopback(int ipd_port,
+                                                 int enable_internal,
+                                                 int enable_external);
+#endif
diff --git a/drivers/staging/octeon/cvmx-helper.c b/drivers/staging/octeon/cvmx-helper.c
new file mode 100644
index 000000000000..591506643d02
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper.c
@@ -0,0 +1,1058 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * Helper functions for common, but complicated tasks.
+ *
+ */
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-config.h"
+
+#include "cvmx-fpa.h"
+#include "cvmx-pip.h"
+#include "cvmx-pko.h"
+#include "cvmx-ipd.h"
+#include "cvmx-spi.h"
+#include "cvmx-helper.h"
+#include "cvmx-helper-board.h"
+
+#include "cvmx-pip-defs.h"
+#include "cvmx-smix-defs.h"
+#include "cvmx-asxx-defs.h"
+
+/**
+ * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
+ * priorities[16]) is a function pointer. It is meant to allow
+ * customization of the PKO queue priorities based on the port
+ * number. Users should set this pointer to a function before
+ * calling any cvmx-helper operations.
+ */
+void (*cvmx_override_pko_queue_priority) (int pko_port,
+                                          uint64_t priorities[16]);
+
+/**
+ * cvmx_override_ipd_port_setup(int ipd_port) is a function
+ * pointer. It is meant to allow customization of the IPD port
+ * setup before packet input/output comes online. It is called
+ * after cvmx-helper does the default IPD configuration, but
+ * before IPD is enabled. Users should set this pointer to a
+ * function before calling any cvmx-helper operations.
+ */
+void (*cvmx_override_ipd_port_setup) (int ipd_port);
+
+/* Port count per interface */
+static int interface_port_count[4] = { 0, 0, 0, 0 };
+
+/* Port last configured link info index by IPD/PKO port */
+static cvmx_helper_link_info_t
+    port_link_info[CVMX_PIP_NUM_INPUT_PORTS];
+
+/**
+ * Return the number of interfaces the chip has. Each interface
+ * may have multiple ports. Most chips support two interfaces,
+ * but the CNX0XX and CNX1XX are exceptions. These only support
+ * one interface.
+ *
+ * Returns Number of interfaces on chip
+ */
+int cvmx_helper_get_number_of_interfaces(void)
+{
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+                return 4;
+        else
+                return 3;
+}
+
+/**
+ * Return the number of ports on an interface. Depending on the
+ * chip and configuration, this can be 1-16. A value of 0
+ * specifies that the interface doesn't exist or isn't usable.
+ *
+ * @interface: Interface to get the port count for
+ *
+ * Returns Number of ports on interface. Can be Zero.
+ */
+int cvmx_helper_ports_on_interface(int interface)
+{
+        return interface_port_count[interface];
+}
+
+/**
+ * Get the operating mode of an interface. Depending on the Octeon
+ * chip and configuration, this function returns an enumeration
+ * of the type of packet I/O supported by an interface.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Mode of the interface. Unknown or unsupported interfaces return
+ *         DISABLED.
+ */
+cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
+{
+        union cvmx_gmxx_inf_mode mode;
+        if (interface == 2)
+                return CVMX_HELPER_INTERFACE_MODE_NPI;
+
+        if (interface == 3) {
+                if (OCTEON_IS_MODEL(OCTEON_CN56XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN52XX))
+                        return CVMX_HELPER_INTERFACE_MODE_LOOP;
+                else
+                        return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+        }
+
+        if (interface == 0
+            && cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5
+            && cvmx_sysinfo_get()->board_rev_major == 1) {
+                /*
+                 * Lie about interface type of CN3005 board.  This
+                 * board has a switch on port 1 like the other
+                 * evaluation boards, but it is connected over RGMII
+                 * instead of GMII.  Report GMII mode so that the
+                 * speed is forced to 1 Gbit full duplex.  Other than
+                 * some initial configuration (which does not use the
+                 * output of this function) there is no difference in
+                 * setup between GMII and RGMII modes.
+                 */
+                return CVMX_HELPER_INTERFACE_MODE_GMII;
+        }
+
+        /* Interface 1 is always disabled on CN31XX and CN30XX */
+        if ((interface == 1)
+            && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX)
+                || OCTEON_IS_MODEL(OCTEON_CN50XX)
+                || OCTEON_IS_MODEL(OCTEON_CN52XX)))
+                return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                switch (mode.cn56xx.mode) {
+                case 0:
+                        return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+                case 1:
+                        return CVMX_HELPER_INTERFACE_MODE_XAUI;
+                case 2:
+                        return CVMX_HELPER_INTERFACE_MODE_SGMII;
+                case 3:
+                        return CVMX_HELPER_INTERFACE_MODE_PICMG;
+                default:
+                        return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+                }
+        } else {
+                if (!mode.s.en)
+                        return CVMX_HELPER_INTERFACE_MODE_DISABLED;
+
+                if (mode.s.type) {
+                        if (OCTEON_IS_MODEL(OCTEON_CN38XX)
+                            || OCTEON_IS_MODEL(OCTEON_CN58XX))
+                                return CVMX_HELPER_INTERFACE_MODE_SPI;
+                        else
+                                return CVMX_HELPER_INTERFACE_MODE_GMII;
+                } else
+                        return CVMX_HELPER_INTERFACE_MODE_RGMII;
+        }
+}
+
+/**
+ * Configure the IPD/PIP tagging and QoS options for a specific
+ * port. This function determines the POW work queue entry
+ * contents for a port. The setup performed here is controlled by
+ * the defines in executive-config.h.
+ *
+ * @ipd_port: Port to configure. This follows the IPD numbering, not the
+ *                 per interface numbering
+ *
+ * Returns Zero on success, negative on failure
+ */
+static int __cvmx_helper_port_setup_ipd(int ipd_port)
+{
+        union cvmx_pip_prt_cfgx port_config;
+        union cvmx_pip_prt_tagx tag_config;
+
+        port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
+        tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port));
+
+        /* Have each port go to a different POW queue */
+        port_config.s.qos = ipd_port & 0x7;
+
+        /* Process the headers and place the IP header in the work queue */
+        port_config.s.mode = CVMX_HELPER_INPUT_PORT_SKIP_MODE;
+
+        tag_config.s.ip6_src_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP;
+        tag_config.s.ip6_dst_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_IP;
+        tag_config.s.ip6_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT;
+        tag_config.s.ip6_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT;
+        tag_config.s.ip6_nxth_flag = CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER;
+        tag_config.s.ip4_src_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP;
+        tag_config.s.ip4_dst_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_IP;
+        tag_config.s.ip4_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT;
+        tag_config.s.ip4_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT;
+        tag_config.s.ip4_pctl_flag = CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL;
+        tag_config.s.inc_prt_flag = CVMX_HELPER_INPUT_TAG_INPUT_PORT;
+        tag_config.s.tcp6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+        tag_config.s.tcp4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+        tag_config.s.ip6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+        tag_config.s.ip4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+        tag_config.s.non_tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+        /* Put all packets in group 0. Other groups can be used by the app */
+        tag_config.s.grp = 0;
+
+        cvmx_pip_config_port(ipd_port, port_config, tag_config);
+
+        /* Give the user a chance to override our setting for each port */
+        if (cvmx_override_ipd_port_setup)
+                cvmx_override_ipd_port_setup(ipd_port);
+
+        return 0;
+}
+
+/**
+ * This function probes an interface to determine the actual
+ * number of hardware ports connected to it. It doesn't setup the
+ * ports or enable them. The main goal here is to set the global
+ * interface_port_count[interface] correctly. Hardware setup of the
+ * ports will be performed later.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Zero on success, negative on failure
+ */
+int cvmx_helper_interface_probe(int interface)
+{
+        /* At this stage in the game we don't want packets to be moving yet.
+           The following probe calls should perform hardware setup
+           needed to determine port counts. Receive must still be disabled */
+        switch (cvmx_helper_interface_get_mode(interface)) {
+                /* These types don't support ports to IPD/PKO */
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+                interface_port_count[interface] = 0;
+                break;
+                /* XAUI is a single high speed port */
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+                interface_port_count[interface] =
+                    __cvmx_helper_xaui_probe(interface);
+                break;
+                /*
+                 * RGMII/GMII/MII are all treated about the same. Most
+                 * functions refer to these ports as RGMII.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+                interface_port_count[interface] =
+                    __cvmx_helper_rgmii_probe(interface);
+                break;
+                /*
+                 * SPI4 can have 1-16 ports depending on the device at
+                 * the other end.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+                interface_port_count[interface] =
+                    __cvmx_helper_spi_probe(interface);
+                break;
+                /*
+                 * SGMII can have 1-4 ports depending on how many are
+                 * hooked up.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                interface_port_count[interface] =
+                    __cvmx_helper_sgmii_probe(interface);
+                break;
+                /* PCI target Network Packet Interface */
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+                interface_port_count[interface] =
+                    __cvmx_helper_npi_probe(interface);
+                break;
+                /*
+                 * Special loopback only ports. These are not the same
+                 * as other ports in loopback mode.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                interface_port_count[interface] =
+                    __cvmx_helper_loop_probe(interface);
+                break;
+        }
+
+        interface_port_count[interface] =
+            __cvmx_helper_board_interface_probe(interface,
+                                                interface_port_count
+                                                [interface]);
+
+        /* Make sure all global variables propagate to other cores */
+        CVMX_SYNCWS;
+
+        return 0;
+}
+
+/**
+ * Setup the IPD/PIP for the ports on an interface. Packet
+ * classification and tagging are set for every port on the
+ * interface. The number of ports on the interface must already
+ * have been probed.
+ *
+ * @interface: Interface to setup IPD/PIP for
+ *
+ * Returns Zero on success, negative on failure
+ */
+static int __cvmx_helper_interface_setup_ipd(int interface)
+{
+        int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
+        int num_ports = interface_port_count[interface];
+
+        while (num_ports--) {
+                __cvmx_helper_port_setup_ipd(ipd_port);
+                ipd_port++;
+        }
+        return 0;
+}
+
+/**
+ * Setup global setting for IPD/PIP not related to a specific
+ * interface or port. This must be called before IPD is enabled.
+ *
+ * Returns Zero on success, negative on failure.
+ */
+static int __cvmx_helper_global_setup_ipd(void)
+{
+        /* Setup the global packet input options */
+        cvmx_ipd_config(CVMX_FPA_PACKET_POOL_SIZE / 8,
+                        CVMX_HELPER_FIRST_MBUFF_SKIP / 8,
+                        CVMX_HELPER_NOT_FIRST_MBUFF_SKIP / 8,
+                        /* The +8 is to account for the next ptr */
+                        (CVMX_HELPER_FIRST_MBUFF_SKIP + 8) / 128,
+                        /* The +8 is to account for the next ptr */
+                        (CVMX_HELPER_NOT_FIRST_MBUFF_SKIP + 8) / 128,
+                        CVMX_FPA_WQE_POOL,
+                        CVMX_IPD_OPC_MODE_STT,
+                        CVMX_HELPER_ENABLE_BACK_PRESSURE);
+        return 0;
+}
+
+/**
+ * Setup the PKO for the ports on an interface. The number of
+ * queues per port and the priority of each PKO output queue
+ * is set here. PKO must be disabled when this function is called.
+ *
+ * @interface: Interface to setup PKO for
+ *
+ * Returns Zero on success, negative on failure
+ */
+static int __cvmx_helper_interface_setup_pko(int interface)
+{
+        /*
+         * Each packet output queue has an associated priority. The
+         * higher the priority, the more often it can send a packet. A
+         * priority of 8 means it can send in all 8 rounds of
+         * contention. We're going to make each queue one less than
+         * the last.  The vector of priorities has been extended to
+         * support CN5xxx CPUs, where up to 16 queues can be
+         * associated to a port.  To keep backward compatibility we
+         * don't change the initial 8 priorities and replicate them in
+         * the second half.  With per-core PKO queues (PKO lockless
+         * operation) all queues have the same priority.
+         */
+        uint64_t priorities[16] =
+            { 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1 };
+
+        /*
+         * Setup the IPD/PIP and PKO for the ports discovered
+         * above. Here packet classification, tagging and output
+         * priorities are set.
+         */
+        int ipd_port = cvmx_helper_get_ipd_port(interface, 0);
+        int num_ports = interface_port_count[interface];
+        while (num_ports--) {
+                /*
+                 * Give the user a chance to override the per queue
+                 * priorities.
+                 */
+                if (cvmx_override_pko_queue_priority)
+                        cvmx_override_pko_queue_priority(ipd_port, priorities);
+
+                cvmx_pko_config_port(ipd_port,
+                                     cvmx_pko_get_base_queue_per_core(ipd_port,
+                                                                      0),
+                                     cvmx_pko_get_num_queues(ipd_port),
+                                     priorities);
+                ipd_port++;
+        }
+        return 0;
+}
+
+/**
+ * Setup global setting for PKO not related to a specific
+ * interface or port. This must be called before PKO is enabled.
+ *
+ * Returns Zero on success, negative on failure.
+ */
+static int __cvmx_helper_global_setup_pko(void)
+{
+        /*
+         * Disable tagwait FAU timeout. This needs to be done before
+         * anyone might start packet output using tags.
+         */
+        union cvmx_iob_fau_timeout fau_to;
+        fau_to.u64 = 0;
+        fau_to.s.tout_val = 0xfff;
+        fau_to.s.tout_enb = 0;
+        cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64);
+        return 0;
+}
+
+/**
+ * Setup global backpressure setting.
+ *
+ * Returns Zero on success, negative on failure
+ */
+static int __cvmx_helper_global_setup_backpressure(void)
+{
+#if CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE
+        /* Disable backpressure if configured to do so */
+        /* Disable backpressure (pause frame) generation */
+        int num_interfaces = cvmx_helper_get_number_of_interfaces();
+        int interface;
+        for (interface = 0; interface < num_interfaces; interface++) {
+                switch (cvmx_helper_interface_get_mode(interface)) {
+                case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+                case CVMX_HELPER_INTERFACE_MODE_PCIE:
+                case CVMX_HELPER_INTERFACE_MODE_NPI:
+                case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                case CVMX_HELPER_INTERFACE_MODE_XAUI:
+                        break;
+                case CVMX_HELPER_INTERFACE_MODE_RGMII:
+                case CVMX_HELPER_INTERFACE_MODE_GMII:
+                case CVMX_HELPER_INTERFACE_MODE_SPI:
+                case CVMX_HELPER_INTERFACE_MODE_SGMII:
+                case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                        cvmx_gmx_set_backpressure_override(interface, 0xf);
+                        break;
+                }
+        }
+#endif
+
+        return 0;
+}
+
+/**
+ * Enable packet input/output from the hardware. This function is
+ * called after all internal setup is complete and IPD is enabled.
+ * After this function completes, packets will be accepted from the
+ * hardware ports. PKO should still be disabled to make sure packets
+ * aren't sent out partially setup hardware.
+ *
+ * @interface: Interface to enable
+ *
+ * Returns Zero on success, negative on failure
+ */
+static int __cvmx_helper_packet_hardware_enable(int interface)
+{
+        int result = 0;
+        switch (cvmx_helper_interface_get_mode(interface)) {
+                /* These types don't support ports to IPD/PKO */
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+                /* Nothing to do */
+                break;
+                /* XAUI is a single high speed port */
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+                result = __cvmx_helper_xaui_enable(interface);
+                break;
+                /*
+                 * RGMII/GMII/MII are all treated about the same. Most
+                 * functions refer to these ports as RGMII
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+                result = __cvmx_helper_rgmii_enable(interface);
+                break;
+                /*
+                 * SPI4 can have 1-16 ports depending on the device at
+                 * the other end
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+                result = __cvmx_helper_spi_enable(interface);
+                break;
+                /*
+                 * SGMII can have 1-4 ports depending on how many are
+                 * hooked up
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                result = __cvmx_helper_sgmii_enable(interface);
+                break;
+                /* PCI target Network Packet Interface */
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+                result = __cvmx_helper_npi_enable(interface);
+                break;
+                /*
+                 * Special loopback only ports. These are not the same
+                 * as other ports in loopback mode
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                result = __cvmx_helper_loop_enable(interface);
+                break;
+        }
+        result |= __cvmx_helper_board_hardware_enable(interface);
+        return result;
+}
+
+/**
+ * Function to adjust internal IPD pointer alignments
+ *
+ * Returns 0 on success
+ *         !0 on failure
+ */
+int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
+{
+#define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES \
+     (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_FIRST_MBUFF_SKIP)
+#define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES \
+        (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_NOT_FIRST_MBUFF_SKIP)
+#define FIX_IPD_OUTPORT 0
+        /* Ports 0-15 are interface 0, 16-31 are interface 1 */
+#define INTERFACE(port) (port >> 4)
+#define INDEX(port) (port & 0xf)
+        uint64_t *p64;
+        cvmx_pko_command_word0_t pko_command;
+        union cvmx_buf_ptr g_buffer, pkt_buffer;
+        cvmx_wqe_t *work;
+        int size, num_segs = 0, wqe_pcnt, pkt_pcnt;
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        int retry_cnt;
+        int retry_loop_cnt;
+        int mtu;
+        int i;
+        cvmx_helper_link_info_t link_info;
+
+        /* Save values for restore at end */
+        uint64_t prtx_cfg =
+            cvmx_read_csr(CVMX_GMXX_PRTX_CFG
+                          (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
+        uint64_t tx_ptr_en =
+            cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
+        uint64_t rx_ptr_en =
+            cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
+        uint64_t rxx_jabber =
+            cvmx_read_csr(CVMX_GMXX_RXX_JABBER
+                          (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
+        uint64_t frame_max =
+            cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX
+                          (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)));
+
+        /* Configure port to gig FDX as required for loopback mode */
+        cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT);
+
+        /*
+         * Disable reception on all ports so if traffic is present it
+         * will not interfere.
+         */
+        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
+
+        cvmx_wait(100000000ull);
+
+        for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) {
+                retry_cnt = 100000;
+                wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
+                pkt_pcnt = (wqe_pcnt >> 7) & 0x7f;
+                wqe_pcnt &= 0x7f;
+
+                num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3;
+
+                if (num_segs == 0)
+                        goto fix_ipd_exit;
+
+                num_segs += 1;
+
+                size =
+                    FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES +
+                    ((num_segs - 1) * FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) -
+                    (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2);
+
+                cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)),
+                               1 << INDEX(FIX_IPD_OUTPORT));
+                CVMX_SYNC;
+
+                g_buffer.u64 = 0;
+                g_buffer.s.addr =
+                    cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL));
+                if (g_buffer.s.addr == 0) {
+                        cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT "
+                                     "buffer allocation failure.\n");
+                        goto fix_ipd_exit;
+                }
+
+                g_buffer.s.pool = CVMX_FPA_WQE_POOL;
+                g_buffer.s.size = num_segs;
+
+                pkt_buffer.u64 = 0;
+                pkt_buffer.s.addr =
+                    cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL));
+                if (pkt_buffer.s.addr == 0) {
+                        cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT "
+                                     "buffer allocation failure.\n");
+                        goto fix_ipd_exit;
+                }
+                pkt_buffer.s.i = 1;
+                pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL;
+                pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES;
+
+                p64 = (uint64_t *) cvmx_phys_to_ptr(pkt_buffer.s.addr);
+                p64[0] = 0xffffffffffff0000ull;
+                p64[1] = 0x08004510ull;
+                p64[2] = ((uint64_t) (size - 14) << 48) | 0x5ae740004000ull;
+                p64[3] = 0x3a5fc0a81073c0a8ull;
+
+                for (i = 0; i < num_segs; i++) {
+                        if (i > 0)
+                                pkt_buffer.s.size =
+                                    FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES;
+
+                        if (i == (num_segs - 1))
+                                pkt_buffer.s.i = 0;
+
+                        *(uint64_t *) cvmx_phys_to_ptr(g_buffer.s.addr +
+                                                       8 * i) = pkt_buffer.u64;
+                }
+
+                /* Build the PKO command */
+                pko_command.u64 = 0;
+                pko_command.s.segs = num_segs;
+                pko_command.s.total_bytes = size;
+                pko_command.s.dontfree = 0;
+                pko_command.s.gather = 1;
+
+                gmx_cfg.u64 =
+                    cvmx_read_csr(CVMX_GMXX_PRTX_CFG
+                                  (INDEX(FIX_IPD_OUTPORT),
+                                   INTERFACE(FIX_IPD_OUTPORT)));
+                gmx_cfg.s.en = 1;
+                cvmx_write_csr(CVMX_GMXX_PRTX_CFG
+                               (INDEX(FIX_IPD_OUTPORT),
+                                INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64);
+                cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
+                               1 << INDEX(FIX_IPD_OUTPORT));
+                cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
+                               1 << INDEX(FIX_IPD_OUTPORT));
+
+                mtu =
+                    cvmx_read_csr(CVMX_GMXX_RXX_JABBER
+                                  (INDEX(FIX_IPD_OUTPORT),
+                                   INTERFACE(FIX_IPD_OUTPORT)));
+                cvmx_write_csr(CVMX_GMXX_RXX_JABBER
+                               (INDEX(FIX_IPD_OUTPORT),
+                                INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
+                cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX
+                               (INDEX(FIX_IPD_OUTPORT),
+                                INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
+
+                cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT,
+                                             cvmx_pko_get_base_queue
+                                             (FIX_IPD_OUTPORT),
+                                             CVMX_PKO_LOCK_CMD_QUEUE);
+                cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT,
+                                            cvmx_pko_get_base_queue
+                                            (FIX_IPD_OUTPORT), pko_command,
+                                            g_buffer, CVMX_PKO_LOCK_CMD_QUEUE);
+
+                CVMX_SYNC;
+
+                do {
+                        work = cvmx_pow_work_request_sync(CVMX_POW_WAIT);
+                        retry_cnt--;
+                } while ((work == NULL) && (retry_cnt > 0));
+
+                if (!retry_cnt)
+                        cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT "
+                                     "get_work() timeout occured.\n");
+
+                /* Free packet */
+                if (work)
+                        cvmx_helper_free_packet_data(work);
+        }
+
+fix_ipd_exit:
+
+        /* Return CSR configs to saved values */
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG
+                       (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
+                       prtx_cfg);
+        cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
+                       tx_ptr_en);
+        cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
+                       rx_ptr_en);
+        cvmx_write_csr(CVMX_GMXX_RXX_JABBER
+                       (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
+                       rxx_jabber);
+        cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX
+                       (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
+                       frame_max);
+        cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0);
+        /* Set link to down so autonegotiation will set it up again */
+        link_info.u64 = 0;
+        cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info);
+
+        /*
+         * Bring the link back up as autonegotiation is not done in
+         * user applications.
+         */
+        cvmx_helper_link_autoconf(FIX_IPD_OUTPORT);
+
+        CVMX_SYNC;
+        if (num_segs)
+                cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n");
+
+        return !!num_segs;
+
+}
+
+/**
+ * Called after all internal packet IO paths are setup. This
+ * function enables IPD/PIP and begins packet input and output.
+ *
+ * Returns Zero on success, negative on failure
+ */
+int cvmx_helper_ipd_and_packet_input_enable(void)
+{
+        int num_interfaces;
+        int interface;
+
+        /* Enable IPD */
+        cvmx_ipd_enable();
+
+        /*
+         * Time to enable hardware ports packet input and output. Note
+         * that at this point IPD/PIP must be fully functional and PKO
+         * must be disabled
+         */
+        num_interfaces = cvmx_helper_get_number_of_interfaces();
+        for (interface = 0; interface < num_interfaces; interface++) {
+                if (cvmx_helper_ports_on_interface(interface) > 0)
+                        __cvmx_helper_packet_hardware_enable(interface);
+        }
+
+        /* Finally enable PKO now that the entire path is up and running */
+        cvmx_pko_enable();
+
+        if ((OCTEON_IS_MODEL(OCTEON_CN31XX_PASS1)
+             || OCTEON_IS_MODEL(OCTEON_CN30XX_PASS1))
+            && (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM))
+                __cvmx_helper_errata_fix_ipd_ptr_alignment();
+        return 0;
+}
+
+/**
+ * Initialize the PIP, IPD, and PKO hardware to support
+ * simple priority based queues for the ethernet ports. Each
+ * port is configured with a number of priority queues based
+ * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower
+ * priority than the previous.
+ *
+ * Returns Zero on success, non-zero on failure
+ */
+int cvmx_helper_initialize_packet_io_global(void)
+{
+        int result = 0;
+        int interface;
+        union cvmx_l2c_cfg l2c_cfg;
+        union cvmx_smix_en smix_en;
+        const int num_interfaces = cvmx_helper_get_number_of_interfaces();
+
+        /*
+         * CN52XX pass 1: Due to a bug in 2nd order CDR, it needs to
+         * be disabled.
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
+                __cvmx_helper_errata_qlm_disable_2nd_order_cdr(1);
+
+        /*
+         * Tell L2 to give the IOB statically higher priority compared
+         * to the cores. This avoids conditions where IO blocks might
+         * be starved under very high L2 loads.
+         */
+        l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
+        l2c_cfg.s.lrf_arb_mode = 0;
+        l2c_cfg.s.rfb_arb_mode = 0;
+        cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64);
+
+        /* Make sure SMI/MDIO is enabled so we can query PHYs */
+        smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0));
+        if (!smix_en.s.en) {
+                smix_en.s.en = 1;
+                cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64);
+        }
+
+        /* Newer chips actually have two SMI/MDIO interfaces */
+        if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) &&
+            !OCTEON_IS_MODEL(OCTEON_CN58XX) &&
+            !OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1));
+                if (!smix_en.s.en) {
+                        smix_en.s.en = 1;
+                        cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64);
+                }
+        }
+
+        cvmx_pko_initialize_global();
+        for (interface = 0; interface < num_interfaces; interface++) {
+                result |= cvmx_helper_interface_probe(interface);
+                if (cvmx_helper_ports_on_interface(interface) > 0)
+                        cvmx_dprintf("Interface %d has %d ports (%s)\n",
+                                     interface,
+                                     cvmx_helper_ports_on_interface(interface),
+                                     cvmx_helper_interface_mode_to_string
+                                     (cvmx_helper_interface_get_mode
+                                      (interface)));
+                result |= __cvmx_helper_interface_setup_ipd(interface);
+                result |= __cvmx_helper_interface_setup_pko(interface);
+        }
+
+        result |= __cvmx_helper_global_setup_ipd();
+        result |= __cvmx_helper_global_setup_pko();
+
+        /* Enable any flow control and backpressure */
+        result |= __cvmx_helper_global_setup_backpressure();
+
+#if CVMX_HELPER_ENABLE_IPD
+        result |= cvmx_helper_ipd_and_packet_input_enable();
+#endif
+        return result;
+}
+
+/**
+ * Does core local initialization for packet io
+ *
+ * Returns Zero on success, non-zero on failure
+ */
+int cvmx_helper_initialize_packet_io_local(void)
+{
+        return cvmx_pko_initialize_local();
+}
+
+/**
+ * Auto configure an IPD/PKO port link state and speed. This
+ * function basically does the equivalent of:
+ * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
+ *
+ * @ipd_port: IPD/PKO port to auto configure
+ *
+ * Returns Link state after configure
+ */
+cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port)
+{
+        cvmx_helper_link_info_t link_info;
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+
+        if (index >= cvmx_helper_ports_on_interface(interface)) {
+                link_info.u64 = 0;
+                return link_info;
+        }
+
+        link_info = cvmx_helper_link_get(ipd_port);
+        if (link_info.u64 == port_link_info[ipd_port].u64)
+                return link_info;
+
+        /* If we fail to set the link speed, port_link_info will not change */
+        cvmx_helper_link_set(ipd_port, link_info);
+
+        /*
+         * port_link_info should be the current value, which will be
+         * different than expect if cvmx_helper_link_set() failed.
+         */
+        return port_link_info[ipd_port];
+}
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port)
+{
+        cvmx_helper_link_info_t result;
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+
+        /* The default result will be a down link unless the code below
+           changes it */
+        result.u64 = 0;
+
+        if (index >= cvmx_helper_ports_on_interface(interface))
+                return result;
+
+        switch (cvmx_helper_interface_get_mode(interface)) {
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+                /* Network links are not supported */
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+                result = __cvmx_helper_xaui_link_get(ipd_port);
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+                if (index == 0)
+                        result = __cvmx_helper_rgmii_link_get(ipd_port);
+                else {
+                        result.s.full_duplex = 1;
+                        result.s.link_up = 1;
+                        result.s.speed = 1000;
+                }
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+                result = __cvmx_helper_rgmii_link_get(ipd_port);
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+                result = __cvmx_helper_spi_link_get(ipd_port);
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                result = __cvmx_helper_sgmii_link_get(ipd_port);
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                /* Network links are not supported */
+                break;
+        }
+        return result;
+}
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
+{
+        int result = -1;
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+
+        if (index >= cvmx_helper_ports_on_interface(interface))
+                return -1;
+
+        switch (cvmx_helper_interface_get_mode(interface)) {
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+                result = __cvmx_helper_xaui_link_set(ipd_port, link_info);
+                break;
+                /*
+                 * RGMII/GMII/MII are all treated about the same. Most
+                 * functions refer to these ports as RGMII.
+                 */
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+                result = __cvmx_helper_rgmii_link_set(ipd_port, link_info);
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+                result = __cvmx_helper_spi_link_set(ipd_port, link_info);
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                result = __cvmx_helper_sgmii_link_set(ipd_port, link_info);
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                break;
+        }
+        /* Set the port_link_info here so that the link status is updated
+           no matter how cvmx_helper_link_set is called. We don't change
+           the value if link_set failed */
+        if (result == 0)
+                port_link_info[ipd_port].u64 = link_info.u64;
+        return result;
+}
+
+/**
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @ipd_port: IPD/PKO port to loopback.
+ * @enable_internal:
+ *                 Non zero if you want internal loopback
+ * @enable_external:
+ *                 Non zero if you want external loopback
+ *
+ * Returns Zero on success, negative on failure.
+ */
+int cvmx_helper_configure_loopback(int ipd_port, int enable_internal,
+                                   int enable_external)
+{
+        int result = -1;
+        int interface = cvmx_helper_get_interface_num(ipd_port);
+        int index = cvmx_helper_get_interface_index_num(ipd_port);
+
+        if (index >= cvmx_helper_ports_on_interface(interface))
+                return -1;
+
+        switch (cvmx_helper_interface_get_mode(interface)) {
+        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+        case CVMX_HELPER_INTERFACE_MODE_SPI:
+        case CVMX_HELPER_INTERFACE_MODE_NPI:
+        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+                result =
+                    __cvmx_helper_xaui_configure_loopback(ipd_port,
+                                                          enable_internal,
+                                                          enable_external);
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+        case CVMX_HELPER_INTERFACE_MODE_GMII:
+                result =
+                    __cvmx_helper_rgmii_configure_loopback(ipd_port,
+                                                           enable_internal,
+                                                           enable_external);
+                break;
+        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                result =
+                    __cvmx_helper_sgmii_configure_loopback(ipd_port,
+                                                           enable_internal,
+                                                           enable_external);
+                break;
+        }
+        return result;
+}
diff --git a/drivers/staging/octeon/cvmx-helper.h b/drivers/staging/octeon/cvmx-helper.h
new file mode 100644
index 000000000000..51916f3cc40c
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-helper.h
@@ -0,0 +1,227 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * Helper functions for common, but complicated tasks.
+ *
+ */
+
+#ifndef __CVMX_HELPER_H__
+#define __CVMX_HELPER_H__
+
+#include "cvmx-config.h"
+#include "cvmx-fpa.h"
+#include "cvmx-wqe.h"
+
+typedef enum {
+        CVMX_HELPER_INTERFACE_MODE_DISABLED,
+        CVMX_HELPER_INTERFACE_MODE_RGMII,
+        CVMX_HELPER_INTERFACE_MODE_GMII,
+        CVMX_HELPER_INTERFACE_MODE_SPI,
+        CVMX_HELPER_INTERFACE_MODE_PCIE,
+        CVMX_HELPER_INTERFACE_MODE_XAUI,
+        CVMX_HELPER_INTERFACE_MODE_SGMII,
+        CVMX_HELPER_INTERFACE_MODE_PICMG,
+        CVMX_HELPER_INTERFACE_MODE_NPI,
+        CVMX_HELPER_INTERFACE_MODE_LOOP,
+} cvmx_helper_interface_mode_t;
+
+typedef union {
+        uint64_t u64;
+        struct {
+                uint64_t reserved_20_63:44;
+                uint64_t link_up:1;         /**< Is the physical link up? */
+                uint64_t full_duplex:1;     /**< 1 if the link is full duplex */
+                uint64_t speed:18;          /**< Speed of the link in Mbps */
+        } s;
+} cvmx_helper_link_info_t;
+
+#include "cvmx-helper-fpa.h"
+
+#include <asm/octeon/cvmx-helper-errata.h>
+#include "cvmx-helper-loop.h"
+#include "cvmx-helper-npi.h"
+#include "cvmx-helper-rgmii.h"
+#include "cvmx-helper-sgmii.h"
+#include "cvmx-helper-spi.h"
+#include "cvmx-helper-util.h"
+#include "cvmx-helper-xaui.h"
+
+/**
+ * cvmx_override_pko_queue_priority(int ipd_port, uint64_t
+ * priorities[16]) is a function pointer. It is meant to allow
+ * customization of the PKO queue priorities based on the port
+ * number. Users should set this pointer to a function before
+ * calling any cvmx-helper operations.
+ */
+extern void (*cvmx_override_pko_queue_priority) (int pko_port,
+                                                 uint64_t priorities[16]);
+
+/**
+ * cvmx_override_ipd_port_setup(int ipd_port) is a function
+ * pointer. It is meant to allow customization of the IPD port
+ * setup before packet input/output comes online. It is called
+ * after cvmx-helper does the default IPD configuration, but
+ * before IPD is enabled. Users should set this pointer to a
+ * function before calling any cvmx-helper operations.
+ */
+extern void (*cvmx_override_ipd_port_setup) (int ipd_port);
+
+/**
+ * This function enables the IPD and also enables the packet interfaces.
+ * The packet interfaces (RGMII and SPI) must be enabled after the
+ * IPD.  This should be called by the user program after any additional
+ * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD
+ * is not set in the executive-config.h file.
+ *
+ * Returns 0 on success
+ *         -1 on failure
+ */
+extern int cvmx_helper_ipd_and_packet_input_enable(void);
+
+/**
+ * Initialize the PIP, IPD, and PKO hardware to support
+ * simple priority based queues for the ethernet ports. Each
+ * port is configured with a number of priority queues based
+ * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower
+ * priority than the previous.
+ *
+ * Returns Zero on success, non-zero on failure
+ */
+extern int cvmx_helper_initialize_packet_io_global(void);
+
+/**
+ * Does core local initialization for packet io
+ *
+ * Returns Zero on success, non-zero on failure
+ */
+extern int cvmx_helper_initialize_packet_io_local(void);
+
+/**
+ * Returns the number of ports on the given interface.
+ * The interface must be initialized before the port count
+ * can be returned.
+ *
+ * @interface: Which interface to return port count for.
+ *
+ * Returns Port count for interface
+ *         -1 for uninitialized interface
+ */
+extern int cvmx_helper_ports_on_interface(int interface);
+
+/**
+ * Return the number of interfaces the chip has. Each interface
+ * may have multiple ports. Most chips support two interfaces,
+ * but the CNX0XX and CNX1XX are exceptions. These only support
+ * one interface.
+ *
+ * Returns Number of interfaces on chip
+ */
+extern int cvmx_helper_get_number_of_interfaces(void);
+
+/**
+ * Get the operating mode of an interface. Depending on the Octeon
+ * chip and configuration, this function returns an enumeration
+ * of the type of packet I/O supported by an interface.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Mode of the interface. Unknown or unsupported interfaces return
+ *         DISABLED.
+ */
+extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
+                                                                   interface);
+
+/**
+ * Auto configure an IPD/PKO port link state and speed. This
+ * function basically does the equivalent of:
+ * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port));
+ *
+ * @ipd_port: IPD/PKO port to auto configure
+ *
+ * Returns Link state after configure
+ */
+extern cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port);
+
+/**
+ * Return the link state of an IPD/PKO port as returned by
+ * auto negotiation. The result of this function may not match
+ * Octeon's link config if auto negotiation has changed since
+ * the last call to cvmx_helper_link_set().
+ *
+ * @ipd_port: IPD/PKO port to query
+ *
+ * Returns Link state
+ */
+extern cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port);
+
+/**
+ * Configure an IPD/PKO port for the specified link state. This
+ * function does not influence auto negotiation at the PHY level.
+ * The passed link state must always match the link state returned
+ * by cvmx_helper_link_get(). It is normally best to use
+ * cvmx_helper_link_autoconf() instead.
+ *
+ * @ipd_port:  IPD/PKO port to configure
+ * @link_info: The new link state
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int cvmx_helper_link_set(int ipd_port,
+                                cvmx_helper_link_info_t link_info);
+
+/**
+ * This function probes an interface to determine the actual
+ * number of hardware ports connected to it. It doesn't setup the
+ * ports or enable them. The main goal here is to set the global
+ * interface_port_count[interface] correctly. Hardware setup of the
+ * ports will be performed later.
+ *
+ * @interface: Interface to probe
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int cvmx_helper_interface_probe(int interface);
+
+/**
+ * Configure a port for internal and/or external loopback. Internal loopback
+ * causes packets sent by the port to be received by Octeon. External loopback
+ * causes packets received from the wire to sent out again.
+ *
+ * @ipd_port: IPD/PKO port to loopback.
+ * @enable_internal:
+ *                 Non zero if you want internal loopback
+ * @enable_external:
+ *                 Non zero if you want external loopback
+ *
+ * Returns Zero on success, negative on failure.
+ */
+extern int cvmx_helper_configure_loopback(int ipd_port, int enable_internal,
+                                          int enable_external);
+
+#endif /* __CVMX_HELPER_H__ */
diff --git a/drivers/staging/octeon/cvmx-interrupt-decodes.c b/drivers/staging/octeon/cvmx-interrupt-decodes.c
new file mode 100644
index 000000000000..a3337e382ee9
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-interrupt-decodes.c
@@ -0,0 +1,371 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2009 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * Automatically generated functions useful for enabling
+ * and decoding RSL_INT_BLOCKS interrupts.
+ *
+ */
+
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-gmxx-defs.h"
+#include "cvmx-pcsx-defs.h"
+#include "cvmx-pcsxx-defs.h"
+#include "cvmx-spxx-defs.h"
+#include "cvmx-stxx-defs.h"
+
+#ifndef PRINT_ERROR
+#define PRINT_ERROR(format, ...)
+#endif
+
+
+/**
+ * __cvmx_interrupt_gmxx_rxx_int_en_enable enables all interrupt bits in cvmx_gmxx_rxx_int_en_t
+ */
+void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
+{
+        union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
+        cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block),
+                       cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block)));
+        gmx_rx_int_en.u64 = 0;
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
+                /* Skipping gmx_rx_int_en.s.reserved_29_63 */
+                gmx_rx_int_en.s.hg2cc = 1;
+                gmx_rx_int_en.s.hg2fld = 1;
+                gmx_rx_int_en.s.undat = 1;
+                gmx_rx_int_en.s.uneop = 1;
+                gmx_rx_int_en.s.unsop = 1;
+                gmx_rx_int_en.s.bad_term = 1;
+                gmx_rx_int_en.s.bad_seq = 1;
+                gmx_rx_int_en.s.rem_fault = 1;
+                gmx_rx_int_en.s.loc_fault = 1;
+                gmx_rx_int_en.s.pause_drp = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_16_18 */
+                /*gmx_rx_int_en.s.ifgerr = 1; */
+                /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
+                /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
+                /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
+                /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
+                gmx_rx_int_en.s.ovrerr = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_9_9 */
+                gmx_rx_int_en.s.skperr = 1;
+                gmx_rx_int_en.s.rcverr = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_5_6 */
+                /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
+                gmx_rx_int_en.s.jabber = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_2_2 */
+                gmx_rx_int_en.s.carext = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_0_0 */
+        }
+        if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
+                /* Skipping gmx_rx_int_en.s.reserved_19_63 */
+                /*gmx_rx_int_en.s.phy_dupx = 1; */
+                /*gmx_rx_int_en.s.phy_spd = 1; */
+                /*gmx_rx_int_en.s.phy_link = 1; */
+                /*gmx_rx_int_en.s.ifgerr = 1; */
+                /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
+                /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
+                /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
+                /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
+                gmx_rx_int_en.s.ovrerr = 1;
+                gmx_rx_int_en.s.niberr = 1;
+                gmx_rx_int_en.s.skperr = 1;
+                gmx_rx_int_en.s.rcverr = 1;
+                /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
+                gmx_rx_int_en.s.alnerr = 1;
+                /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
+                gmx_rx_int_en.s.jabber = 1;
+                gmx_rx_int_en.s.maxerr = 1;
+                gmx_rx_int_en.s.carext = 1;
+                gmx_rx_int_en.s.minerr = 1;
+        }
+        if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
+                /* Skipping gmx_rx_int_en.s.reserved_20_63 */
+                gmx_rx_int_en.s.pause_drp = 1;
+                /*gmx_rx_int_en.s.phy_dupx = 1; */
+                /*gmx_rx_int_en.s.phy_spd = 1; */
+                /*gmx_rx_int_en.s.phy_link = 1; */
+                /*gmx_rx_int_en.s.ifgerr = 1; */
+                /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
+                /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
+                /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
+                /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
+                gmx_rx_int_en.s.ovrerr = 1;
+                gmx_rx_int_en.s.niberr = 1;
+                gmx_rx_int_en.s.skperr = 1;
+                gmx_rx_int_en.s.rcverr = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_6_6 */
+                gmx_rx_int_en.s.alnerr = 1;
+                /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
+                gmx_rx_int_en.s.jabber = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_2_2 */
+                gmx_rx_int_en.s.carext = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_0_0 */
+        }
+        if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
+                /* Skipping gmx_rx_int_en.s.reserved_19_63 */
+                /*gmx_rx_int_en.s.phy_dupx = 1; */
+                /*gmx_rx_int_en.s.phy_spd = 1; */
+                /*gmx_rx_int_en.s.phy_link = 1; */
+                /*gmx_rx_int_en.s.ifgerr = 1; */
+                /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
+                /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
+                /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
+                /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
+                gmx_rx_int_en.s.ovrerr = 1;
+                gmx_rx_int_en.s.niberr = 1;
+                gmx_rx_int_en.s.skperr = 1;
+                gmx_rx_int_en.s.rcverr = 1;
+                /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
+                gmx_rx_int_en.s.alnerr = 1;
+                /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
+                gmx_rx_int_en.s.jabber = 1;
+                gmx_rx_int_en.s.maxerr = 1;
+                gmx_rx_int_en.s.carext = 1;
+                gmx_rx_int_en.s.minerr = 1;
+        }
+        if (OCTEON_IS_MODEL(OCTEON_CN31XX)) {
+                /* Skipping gmx_rx_int_en.s.reserved_19_63 */
+                /*gmx_rx_int_en.s.phy_dupx = 1; */
+                /*gmx_rx_int_en.s.phy_spd = 1; */
+                /*gmx_rx_int_en.s.phy_link = 1; */
+                /*gmx_rx_int_en.s.ifgerr = 1; */
+                /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
+                /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
+                /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
+                /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
+                gmx_rx_int_en.s.ovrerr = 1;
+                gmx_rx_int_en.s.niberr = 1;
+                gmx_rx_int_en.s.skperr = 1;
+                gmx_rx_int_en.s.rcverr = 1;
+                /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
+                gmx_rx_int_en.s.alnerr = 1;
+                /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
+                gmx_rx_int_en.s.jabber = 1;
+                gmx_rx_int_en.s.maxerr = 1;
+                gmx_rx_int_en.s.carext = 1;
+                gmx_rx_int_en.s.minerr = 1;
+        }
+        if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
+                /* Skipping gmx_rx_int_en.s.reserved_20_63 */
+                gmx_rx_int_en.s.pause_drp = 1;
+                /*gmx_rx_int_en.s.phy_dupx = 1; */
+                /*gmx_rx_int_en.s.phy_spd = 1; */
+                /*gmx_rx_int_en.s.phy_link = 1; */
+                /*gmx_rx_int_en.s.ifgerr = 1; */
+                /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
+                /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
+                /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
+                /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
+                gmx_rx_int_en.s.ovrerr = 1;
+                gmx_rx_int_en.s.niberr = 1;
+                gmx_rx_int_en.s.skperr = 1;
+                gmx_rx_int_en.s.rcverr = 1;
+                /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
+                gmx_rx_int_en.s.alnerr = 1;
+                /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
+                gmx_rx_int_en.s.jabber = 1;
+                gmx_rx_int_en.s.maxerr = 1;
+                gmx_rx_int_en.s.carext = 1;
+                gmx_rx_int_en.s.minerr = 1;
+        }
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                /* Skipping gmx_rx_int_en.s.reserved_29_63 */
+                gmx_rx_int_en.s.hg2cc = 1;
+                gmx_rx_int_en.s.hg2fld = 1;
+                gmx_rx_int_en.s.undat = 1;
+                gmx_rx_int_en.s.uneop = 1;
+                gmx_rx_int_en.s.unsop = 1;
+                gmx_rx_int_en.s.bad_term = 1;
+                gmx_rx_int_en.s.bad_seq = 0;
+                gmx_rx_int_en.s.rem_fault = 1;
+                gmx_rx_int_en.s.loc_fault = 0;
+                gmx_rx_int_en.s.pause_drp = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_16_18 */
+                /*gmx_rx_int_en.s.ifgerr = 1; */
+                /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
+                /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
+                /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
+                /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
+                gmx_rx_int_en.s.ovrerr = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_9_9 */
+                gmx_rx_int_en.s.skperr = 1;
+                gmx_rx_int_en.s.rcverr = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_5_6 */
+                /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
+                gmx_rx_int_en.s.jabber = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_2_2 */
+                gmx_rx_int_en.s.carext = 1;
+                /* Skipping gmx_rx_int_en.s.reserved_0_0 */
+        }
+        cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64);
+}
+/**
+ * __cvmx_interrupt_pcsx_intx_en_reg_enable enables all interrupt bits in cvmx_pcsx_intx_en_reg_t
+ */
+void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block)
+{
+        union cvmx_pcsx_intx_en_reg pcs_int_en_reg;
+        cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block),
+                       cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block)));
+        pcs_int_en_reg.u64 = 0;
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
+                /* Skipping pcs_int_en_reg.s.reserved_12_63 */
+                /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */
+                pcs_int_en_reg.s.sync_bad_en = 1;
+                pcs_int_en_reg.s.an_bad_en = 1;
+                pcs_int_en_reg.s.rxlock_en = 1;
+                pcs_int_en_reg.s.rxbad_en = 1;
+                /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */
+                pcs_int_en_reg.s.txbad_en = 1;
+                pcs_int_en_reg.s.txfifo_en = 1;
+                pcs_int_en_reg.s.txfifu_en = 1;
+                pcs_int_en_reg.s.an_err_en = 1;
+                /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */
+                /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */
+        }
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                /* Skipping pcs_int_en_reg.s.reserved_12_63 */
+                /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */
+                pcs_int_en_reg.s.sync_bad_en = 1;
+                pcs_int_en_reg.s.an_bad_en = 1;
+                pcs_int_en_reg.s.rxlock_en = 1;
+                pcs_int_en_reg.s.rxbad_en = 1;
+                /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */
+                pcs_int_en_reg.s.txbad_en = 1;
+                pcs_int_en_reg.s.txfifo_en = 1;
+                pcs_int_en_reg.s.txfifu_en = 1;
+                pcs_int_en_reg.s.an_err_en = 1;
+                /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */
+                /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */
+        }
+        cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64);
+}
+/**
+ * __cvmx_interrupt_pcsxx_int_en_reg_enable enables all interrupt bits in cvmx_pcsxx_int_en_reg_t
+ */
+void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index)
+{
+        union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
+        cvmx_write_csr(CVMX_PCSXX_INT_REG(index),
+                       cvmx_read_csr(CVMX_PCSXX_INT_REG(index)));
+        pcsx_int_en_reg.u64 = 0;
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
+                /* Skipping pcsx_int_en_reg.s.reserved_6_63 */
+                pcsx_int_en_reg.s.algnlos_en = 1;
+                pcsx_int_en_reg.s.synlos_en = 1;
+                pcsx_int_en_reg.s.bitlckls_en = 1;
+                pcsx_int_en_reg.s.rxsynbad_en = 1;
+                pcsx_int_en_reg.s.rxbad_en = 1;
+                pcsx_int_en_reg.s.txflt_en = 1;
+        }
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                /* Skipping pcsx_int_en_reg.s.reserved_6_63 */
+                pcsx_int_en_reg.s.algnlos_en = 1;
+                pcsx_int_en_reg.s.synlos_en = 1;
+                pcsx_int_en_reg.s.bitlckls_en = 0;      /* Happens if XAUI module is not installed */
+                pcsx_int_en_reg.s.rxsynbad_en = 1;
+                pcsx_int_en_reg.s.rxbad_en = 1;
+                pcsx_int_en_reg.s.txflt_en = 1;
+        }
+        cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64);
+}
+
+/**
+ * __cvmx_interrupt_spxx_int_msk_enable enables all interrupt bits in cvmx_spxx_int_msk_t
+ */
+void __cvmx_interrupt_spxx_int_msk_enable(int index)
+{
+        union cvmx_spxx_int_msk spx_int_msk;
+        cvmx_write_csr(CVMX_SPXX_INT_REG(index),
+                       cvmx_read_csr(CVMX_SPXX_INT_REG(index)));
+        spx_int_msk.u64 = 0;
+        if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
+                /* Skipping spx_int_msk.s.reserved_12_63 */
+                spx_int_msk.s.calerr = 1;
+                spx_int_msk.s.syncerr = 1;
+                spx_int_msk.s.diperr = 1;
+                spx_int_msk.s.tpaovr = 1;
+                spx_int_msk.s.rsverr = 1;
+                spx_int_msk.s.drwnng = 1;
+                spx_int_msk.s.clserr = 1;
+                spx_int_msk.s.spiovr = 1;
+                /* Skipping spx_int_msk.s.reserved_2_3 */
+                spx_int_msk.s.abnorm = 1;
+                spx_int_msk.s.prtnxa = 1;
+        }
+        if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
+                /* Skipping spx_int_msk.s.reserved_12_63 */
+                spx_int_msk.s.calerr = 1;
+                spx_int_msk.s.syncerr = 1;
+                spx_int_msk.s.diperr = 1;
+                spx_int_msk.s.tpaovr = 1;
+                spx_int_msk.s.rsverr = 1;
+                spx_int_msk.s.drwnng = 1;
+                spx_int_msk.s.clserr = 1;
+                spx_int_msk.s.spiovr = 1;
+                /* Skipping spx_int_msk.s.reserved_2_3 */
+                spx_int_msk.s.abnorm = 1;
+                spx_int_msk.s.prtnxa = 1;
+        }
+        cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64);
+}
+/**
+ * __cvmx_interrupt_stxx_int_msk_enable enables all interrupt bits in cvmx_stxx_int_msk_t
+ */
+void __cvmx_interrupt_stxx_int_msk_enable(int index)
+{
+        union cvmx_stxx_int_msk stx_int_msk;
+        cvmx_write_csr(CVMX_STXX_INT_REG(index),
+                       cvmx_read_csr(CVMX_STXX_INT_REG(index)));
+        stx_int_msk.u64 = 0;
+        if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
+                /* Skipping stx_int_msk.s.reserved_8_63 */
+                stx_int_msk.s.frmerr = 1;
+                stx_int_msk.s.unxfrm = 1;
+                stx_int_msk.s.nosync = 1;
+                stx_int_msk.s.diperr = 1;
+                stx_int_msk.s.datovr = 1;
+                stx_int_msk.s.ovrbst = 1;
+                stx_int_msk.s.calpar1 = 1;
+                stx_int_msk.s.calpar0 = 1;
+        }
+        if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
+                /* Skipping stx_int_msk.s.reserved_8_63 */
+                stx_int_msk.s.frmerr = 1;
+                stx_int_msk.s.unxfrm = 1;
+                stx_int_msk.s.nosync = 1;
+                stx_int_msk.s.diperr = 1;
+                stx_int_msk.s.datovr = 1;
+                stx_int_msk.s.ovrbst = 1;
+                stx_int_msk.s.calpar1 = 1;
+                stx_int_msk.s.calpar0 = 1;
+        }
+        cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64);
+}
diff --git a/drivers/staging/octeon/cvmx-interrupt-rsl.c b/drivers/staging/octeon/cvmx-interrupt-rsl.c
new file mode 100644
index 000000000000..df50048cfbc0
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-interrupt-rsl.c
@@ -0,0 +1,140 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Utility functions to decode Octeon's RSL_INT_BLOCKS
+ * interrupts into error messages.
+ */
+
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-asxx-defs.h"
+#include "cvmx-gmxx-defs.h"
+
+#ifndef PRINT_ERROR
+#define PRINT_ERROR(format, ...)
+#endif
+
+void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block);
+
+/**
+ * Enable ASX error interrupts that exist on CN3XXX, CN50XX, and
+ * CN58XX.
+ *
+ * @block:  Interface to enable 0-1
+ */
+void __cvmx_interrupt_asxx_enable(int block)
+{
+        int mask;
+        union cvmx_asxx_int_en csr;
+        /*
+         * CN38XX and CN58XX have two interfaces with 4 ports per
+         * interface. All other chips have a max of 3 ports on
+         * interface 0
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
+                mask = 0xf;     /* Set enables for 4 ports */
+        else
+                mask = 0x7;     /* Set enables for 3 ports */
+
+        /* Enable interface interrupts */
+        csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block));
+        csr.s.txpsh = mask;
+        csr.s.txpop = mask;
+        csr.s.ovrflw = mask;
+        cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64);
+}
+/**
+ * Enable GMX error reporting for the supplied interface
+ *
+ * @interface: Interface to enable
+ */
+void __cvmx_interrupt_gmxx_enable(int interface)
+{
+        union cvmx_gmxx_inf_mode mode;
+        union cvmx_gmxx_tx_int_en gmx_tx_int_en;
+        int num_ports;
+        int index;
+
+        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                if (mode.s.en) {
+                        switch (mode.cn56xx.mode) {
+                        case 1: /* XAUI */
+                                num_ports = 1;
+                                break;
+                        case 2: /* SGMII */
+                        case 3: /* PICMG */
+                                num_ports = 4;
+                                break;
+                        default:        /* Disabled */
+                                num_ports = 0;
+                                break;
+                        }
+                } else
+                        num_ports = 0;
+        } else {
+                if (mode.s.en) {
+                        if (OCTEON_IS_MODEL(OCTEON_CN38XX)
+                            || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
+                                /*
+                                 * SPI on CN38XX and CN58XX report all
+                                 * errors through port 0.  RGMII needs
+                                 * to check all 4 ports
+                                 */
+                                if (mode.s.type)
+                                        num_ports = 1;
+                                else
+                                        num_ports = 4;
+                        } else {
+                                /*
+                                 * CN30XX, CN31XX, and CN50XX have two
+                                 * or three ports. GMII and MII has 2,
+                                 * RGMII has three
+                                 */
+                                if (mode.s.type)
+                                        num_ports = 2;
+                                else
+                                        num_ports = 3;
+                        }
+                } else
+                        num_ports = 0;
+        }
+
+        gmx_tx_int_en.u64 = 0;
+        if (num_ports) {
+                if (OCTEON_IS_MODEL(OCTEON_CN38XX)
+                    || OCTEON_IS_MODEL(OCTEON_CN58XX))
+                        gmx_tx_int_en.s.ncb_nxa = 1;
+                gmx_tx_int_en.s.pko_nxa = 1;
+        }
+        gmx_tx_int_en.s.undflw = (1 << num_ports) - 1;
+        cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
+        for (index = 0; index < num_ports; index++)
+                __cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface);
+}
diff --git a/drivers/staging/octeon/cvmx-ipd.h b/drivers/staging/octeon/cvmx-ipd.h
new file mode 100644
index 000000000000..115a552c5c7f
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-ipd.h
@@ -0,0 +1,338 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * Interface to the hardware Input Packet Data unit.
+ */
+
+#ifndef __CVMX_IPD_H__
+#define __CVMX_IPD_H__
+
+#include <asm/octeon/octeon-feature.h>
+
+#include <asm/octeon/cvmx-ipd-defs.h>
+
+enum cvmx_ipd_mode {
+   CVMX_IPD_OPC_MODE_STT = 0LL,   /* All blocks DRAM, not cached in L2 */
+   CVMX_IPD_OPC_MODE_STF = 1LL,   /* All bloccks into  L2 */
+   CVMX_IPD_OPC_MODE_STF1_STT = 2LL,   /* 1st block L2, rest DRAM */
+   CVMX_IPD_OPC_MODE_STF2_STT = 3LL    /* 1st, 2nd blocks L2, rest DRAM */
+};
+
+#ifndef CVMX_ENABLE_LEN_M8_FIX
+#define CVMX_ENABLE_LEN_M8_FIX 0
+#endif
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_mbuff_first_skip_t;
+typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_first_next_ptr_back_t;
+
+typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t;
+typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
+
+/**
+ * Configure IPD
+ *
+ * @mbuff_size: Packets buffer size in 8 byte words
+ * @first_mbuff_skip:
+ *                   Number of 8 byte words to skip in the first buffer
+ * @not_first_mbuff_skip:
+ *                   Number of 8 byte words to skip in each following buffer
+ * @first_back: Must be same as first_mbuff_skip / 128
+ * @second_back:
+ *                   Must be same as not_first_mbuff_skip / 128
+ * @wqe_fpa_pool:
+ *                   FPA pool to get work entries from
+ * @cache_mode:
+ * @back_pres_enable_flag:
+ *                   Enable or disable port back pressure
+ */
+static inline void cvmx_ipd_config(uint64_t mbuff_size,
+                                   uint64_t first_mbuff_skip,
+                                   uint64_t not_first_mbuff_skip,
+                                   uint64_t first_back,
+                                   uint64_t second_back,
+                                   uint64_t wqe_fpa_pool,
+                                   enum cvmx_ipd_mode cache_mode,
+                                   uint64_t back_pres_enable_flag)
+{
+        cvmx_ipd_mbuff_first_skip_t first_skip;
+        cvmx_ipd_mbuff_not_first_skip_t not_first_skip;
+        union cvmx_ipd_packet_mbuff_size size;
+        cvmx_ipd_first_next_ptr_back_t first_back_struct;
+        cvmx_ipd_second_next_ptr_back_t second_back_struct;
+        union cvmx_ipd_wqe_fpa_queue wqe_pool;
+        union cvmx_ipd_ctl_status ipd_ctl_reg;
+
+        first_skip.u64 = 0;
+        first_skip.s.skip_sz = first_mbuff_skip;
+        cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64);
+
+        not_first_skip.u64 = 0;
+        not_first_skip.s.skip_sz = not_first_mbuff_skip;
+        cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64);
+
+        size.u64 = 0;
+        size.s.mb_size = mbuff_size;
+        cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64);
+
+        first_back_struct.u64 = 0;
+        first_back_struct.s.back = first_back;
+        cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64);
+
+        second_back_struct.u64 = 0;
+        second_back_struct.s.back = second_back;
+        cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64);
+
+        wqe_pool.u64 = 0;
+        wqe_pool.s.wqe_pool = wqe_fpa_pool;
+        cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64);
+
+        ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+        ipd_ctl_reg.s.opc_mode = cache_mode;
+        ipd_ctl_reg.s.pbp_en = back_pres_enable_flag;
+        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64);
+
+        /* Note: the example RED code that used to be here has been moved to
+           cvmx_helper_setup_red */
+}
+
+/**
+ * Enable IPD
+ */
+static inline void cvmx_ipd_enable(void)
+{
+        union cvmx_ipd_ctl_status ipd_reg;
+        ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+        if (ipd_reg.s.ipd_en) {
+                cvmx_dprintf
+                    ("Warning: Enabling IPD when IPD already enabled.\n");
+        }
+        ipd_reg.s.ipd_en = 1;
+#if  CVMX_ENABLE_LEN_M8_FIX
+        if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
+                ipd_reg.s.len_m8 = TRUE;
+#endif
+        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
+}
+
+/**
+ * Disable IPD
+ */
+static inline void cvmx_ipd_disable(void)
+{
+        union cvmx_ipd_ctl_status ipd_reg;
+        ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+        ipd_reg.s.ipd_en = 0;
+        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
+}
+
+/**
+ * Supportive function for cvmx_fpa_shutdown_pool.
+ */
+static inline void cvmx_ipd_free_ptr(void)
+{
+        /* Only CN38XXp{1,2} cannot read pointer out of the IPD */
+        if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)
+            && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
+                int no_wptr = 0;
+                union cvmx_ipd_ptr_count ipd_ptr_count;
+                ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
+
+                /* Handle Work Queue Entry in cn56xx and cn52xx */
+                if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) {
+                        union cvmx_ipd_ctl_status ipd_ctl_status;
+                        ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+                        if (ipd_ctl_status.s.no_wptr)
+                                no_wptr = 1;
+                }
+
+                /* Free the prefetched WQE */
+                if (ipd_ptr_count.s.wqev_cnt) {
+                        union cvmx_ipd_wqe_ptr_valid ipd_wqe_ptr_valid;
+                        ipd_wqe_ptr_valid.u64 =
+                            cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID);
+                        if (no_wptr)
+                                cvmx_fpa_free(cvmx_phys_to_ptr
+                                              ((uint64_t) ipd_wqe_ptr_valid.s.
+                                               ptr << 7), CVMX_FPA_PACKET_POOL,
+                                              0);
+                        else
+                                cvmx_fpa_free(cvmx_phys_to_ptr
+                                              ((uint64_t) ipd_wqe_ptr_valid.s.
+                                               ptr << 7), CVMX_FPA_WQE_POOL, 0);
+                }
+
+                /* Free all WQE in the fifo */
+                if (ipd_ptr_count.s.wqe_pcnt) {
+                        int i;
+                        union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
+                        ipd_pwp_ptr_fifo_ctl.u64 =
+                            cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+                        for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) {
+                                ipd_pwp_ptr_fifo_ctl.s.cena = 0;
+                                ipd_pwp_ptr_fifo_ctl.s.raddr =
+                                    ipd_pwp_ptr_fifo_ctl.s.max_cnts +
+                                    (ipd_pwp_ptr_fifo_ctl.s.wraddr +
+                                     i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
+                                cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
+                                               ipd_pwp_ptr_fifo_ctl.u64);
+                                ipd_pwp_ptr_fifo_ctl.u64 =
+                                    cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+                                if (no_wptr)
+                                        cvmx_fpa_free(cvmx_phys_to_ptr
+                                                      ((uint64_t)
+                                                       ipd_pwp_ptr_fifo_ctl.s.
+                                                       ptr << 7),
+                                                      CVMX_FPA_PACKET_POOL, 0);
+                                else
+                                        cvmx_fpa_free(cvmx_phys_to_ptr
+                                                      ((uint64_t)
+                                                       ipd_pwp_ptr_fifo_ctl.s.
+                                                       ptr << 7),
+                                                      CVMX_FPA_WQE_POOL, 0);
+                        }
+                        ipd_pwp_ptr_fifo_ctl.s.cena = 1;
+                        cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
+                                       ipd_pwp_ptr_fifo_ctl.u64);
+                }
+
+                /* Free the prefetched packet */
+                if (ipd_ptr_count.s.pktv_cnt) {
+                        union cvmx_ipd_pkt_ptr_valid ipd_pkt_ptr_valid;
+                        ipd_pkt_ptr_valid.u64 =
+                            cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID);
+                        cvmx_fpa_free(cvmx_phys_to_ptr
+                                      (ipd_pkt_ptr_valid.s.ptr << 7),
+                                      CVMX_FPA_PACKET_POOL, 0);
+                }
+
+                /* Free the per port prefetched packets */
+                if (1) {
+                        int i;
+                        union cvmx_ipd_prc_port_ptr_fifo_ctl
+                            ipd_prc_port_ptr_fifo_ctl;
+                        ipd_prc_port_ptr_fifo_ctl.u64 =
+                            cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
+
+                        for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
+                             i++) {
+                                ipd_prc_port_ptr_fifo_ctl.s.cena = 0;
+                                ipd_prc_port_ptr_fifo_ctl.s.raddr =
+                                    i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt;
+                                cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
+                                               ipd_prc_port_ptr_fifo_ctl.u64);
+                                ipd_prc_port_ptr_fifo_ctl.u64 =
+                                    cvmx_read_csr
+                                    (CVMX_IPD_PRC_PORT_PTR_FIFO_CTL);
+                                cvmx_fpa_free(cvmx_phys_to_ptr
+                                              ((uint64_t)
+                                               ipd_prc_port_ptr_fifo_ctl.s.
+                                               ptr << 7), CVMX_FPA_PACKET_POOL,
+                                              0);
+                        }
+                        ipd_prc_port_ptr_fifo_ctl.s.cena = 1;
+                        cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL,
+                                       ipd_prc_port_ptr_fifo_ctl.u64);
+                }
+
+                /* Free all packets in the holding fifo */
+                if (ipd_ptr_count.s.pfif_cnt) {
+                        int i;
+                        union cvmx_ipd_prc_hold_ptr_fifo_ctl
+                            ipd_prc_hold_ptr_fifo_ctl;
+
+                        ipd_prc_hold_ptr_fifo_ctl.u64 =
+                            cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
+
+                        for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) {
+                                ipd_prc_hold_ptr_fifo_ctl.s.cena = 0;
+                                ipd_prc_hold_ptr_fifo_ctl.s.raddr =
+                                    (ipd_prc_hold_ptr_fifo_ctl.s.praddr +
+                                     i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt;
+                                cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
+                                               ipd_prc_hold_ptr_fifo_ctl.u64);
+                                ipd_prc_hold_ptr_fifo_ctl.u64 =
+                                    cvmx_read_csr
+                                    (CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL);
+                                cvmx_fpa_free(cvmx_phys_to_ptr
+                                              ((uint64_t)
+                                               ipd_prc_hold_ptr_fifo_ctl.s.
+                                               ptr << 7), CVMX_FPA_PACKET_POOL,
+                                              0);
+                        }
+                        ipd_prc_hold_ptr_fifo_ctl.s.cena = 1;
+                        cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL,
+                                       ipd_prc_hold_ptr_fifo_ctl.u64);
+                }
+
+                /* Free all packets in the fifo */
+                if (ipd_ptr_count.s.pkt_pcnt) {
+                        int i;
+                        union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl;
+                        ipd_pwp_ptr_fifo_ctl.u64 =
+                            cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+
+                        for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) {
+                                ipd_pwp_ptr_fifo_ctl.s.cena = 0;
+                                ipd_pwp_ptr_fifo_ctl.s.raddr =
+                                    (ipd_pwp_ptr_fifo_ctl.s.praddr +
+                                     i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts;
+                                cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
+                                               ipd_pwp_ptr_fifo_ctl.u64);
+                                ipd_pwp_ptr_fifo_ctl.u64 =
+                                    cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL);
+                                cvmx_fpa_free(cvmx_phys_to_ptr
+                                              ((uint64_t) ipd_pwp_ptr_fifo_ctl.
+                                               s.ptr << 7),
+                                              CVMX_FPA_PACKET_POOL, 0);
+                        }
+                        ipd_pwp_ptr_fifo_ctl.s.cena = 1;
+                        cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL,
+                                       ipd_pwp_ptr_fifo_ctl.u64);
+                }
+
+                /* Reset the IPD to get all buffers out of it */
+                {
+                        union cvmx_ipd_ctl_status ipd_ctl_status;
+                        ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
+                        ipd_ctl_status.s.reset = 1;
+                        cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
+                }
+
+                /* Reset the PIP */
+                {
+                        union cvmx_pip_sft_rst pip_sft_rst;
+                        pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST);
+                        pip_sft_rst.s.rst = 1;
+                        cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64);
+                }
+        }
+}
+
+#endif /*  __CVMX_IPD_H__ */
diff --git a/drivers/staging/octeon/cvmx-mdio.h b/drivers/staging/octeon/cvmx-mdio.h
new file mode 100644
index 000000000000..c987a75a20cf
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-mdio.h
@@ -0,0 +1,506 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3
+ * clause 22 and clause 45 operations.
+ *
+ */
+
+#ifndef __CVMX_MIO_H__
+#define __CVMX_MIO_H__
+
+#include "cvmx-smix-defs.h"
+
+/**
+ * PHY register 0 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_CONTROL 0
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t reset:1;
+                uint16_t loopback:1;
+                uint16_t speed_lsb:1;
+                uint16_t autoneg_enable:1;
+                uint16_t power_down:1;
+                uint16_t isolate:1;
+                uint16_t restart_autoneg:1;
+                uint16_t duplex:1;
+                uint16_t collision_test:1;
+                uint16_t speed_msb:1;
+                uint16_t unidirectional_enable:1;
+                uint16_t reserved_0_4:5;
+        } s;
+} cvmx_mdio_phy_reg_control_t;
+
+/**
+ * PHY register 1 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_STATUS 1
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t capable_100base_t4:1;
+                uint16_t capable_100base_x_full:1;
+                uint16_t capable_100base_x_half:1;
+                uint16_t capable_10_full:1;
+                uint16_t capable_10_half:1;
+                uint16_t capable_100base_t2_full:1;
+                uint16_t capable_100base_t2_half:1;
+                uint16_t capable_extended_status:1;
+                uint16_t capable_unidirectional:1;
+                uint16_t capable_mf_preamble_suppression:1;
+                uint16_t autoneg_complete:1;
+                uint16_t remote_fault:1;
+                uint16_t capable_autoneg:1;
+                uint16_t link_status:1;
+                uint16_t jabber_detect:1;
+                uint16_t capable_extended_registers:1;
+
+        } s;
+} cvmx_mdio_phy_reg_status_t;
+
+/**
+ * PHY register 2 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_ID1 2
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t oui_bits_3_18;
+        } s;
+} cvmx_mdio_phy_reg_id1_t;
+
+/**
+ * PHY register 3 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_ID2 3
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t oui_bits_19_24:6;
+                uint16_t model:6;
+                uint16_t revision:4;
+        } s;
+} cvmx_mdio_phy_reg_id2_t;
+
+/**
+ * PHY register 4 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t next_page:1;
+                uint16_t reserved_14:1;
+                uint16_t remote_fault:1;
+                uint16_t reserved_12:1;
+                uint16_t asymmetric_pause:1;
+                uint16_t pause:1;
+                uint16_t advert_100base_t4:1;
+                uint16_t advert_100base_tx_full:1;
+                uint16_t advert_100base_tx_half:1;
+                uint16_t advert_10base_tx_full:1;
+                uint16_t advert_10base_tx_half:1;
+                uint16_t selector:5;
+        } s;
+} cvmx_mdio_phy_reg_autoneg_adver_t;
+
+/**
+ * PHY register 5 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t next_page:1;
+                uint16_t ack:1;
+                uint16_t remote_fault:1;
+                uint16_t reserved_12:1;
+                uint16_t asymmetric_pause:1;
+                uint16_t pause:1;
+                uint16_t advert_100base_t4:1;
+                uint16_t advert_100base_tx_full:1;
+                uint16_t advert_100base_tx_half:1;
+                uint16_t advert_10base_tx_full:1;
+                uint16_t advert_10base_tx_half:1;
+                uint16_t selector:5;
+        } s;
+} cvmx_mdio_phy_reg_link_partner_ability_t;
+
+/**
+ * PHY register 6 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t reserved_5_15:11;
+                uint16_t parallel_detection_fault:1;
+                uint16_t link_partner_next_page_capable:1;
+                uint16_t local_next_page_capable:1;
+                uint16_t page_received:1;
+                uint16_t link_partner_autoneg_capable:1;
+
+        } s;
+} cvmx_mdio_phy_reg_autoneg_expansion_t;
+
+/**
+ * PHY register 9 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_CONTROL_1000 9
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t test_mode:3;
+                uint16_t manual_master_slave:1;
+                uint16_t master:1;
+                uint16_t port_type:1;
+                uint16_t advert_1000base_t_full:1;
+                uint16_t advert_1000base_t_half:1;
+                uint16_t reserved_0_7:8;
+        } s;
+} cvmx_mdio_phy_reg_control_1000_t;
+
+/**
+ * PHY register 10 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_STATUS_1000 10
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t master_slave_fault:1;
+                uint16_t is_master:1;
+                uint16_t local_receiver_ok:1;
+                uint16_t remote_receiver_ok:1;
+                uint16_t remote_capable_1000base_t_full:1;
+                uint16_t remote_capable_1000base_t_half:1;
+                uint16_t reserved_8_9:2;
+                uint16_t idle_error_count:8;
+        } s;
+} cvmx_mdio_phy_reg_status_1000_t;
+
+/**
+ * PHY register 15 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t capable_1000base_x_full:1;
+                uint16_t capable_1000base_x_half:1;
+                uint16_t capable_1000base_t_full:1;
+                uint16_t capable_1000base_t_half:1;
+                uint16_t reserved_0_11:12;
+        } s;
+} cvmx_mdio_phy_reg_extended_status_t;
+
+/**
+ * PHY register 13 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t function:2;
+                uint16_t reserved_5_13:9;
+                uint16_t devad:5;
+        } s;
+} cvmx_mdio_phy_reg_mmd_control_t;
+
+/**
+ * PHY register 14 from the 802.3 spec
+ */
+#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14
+typedef union {
+        uint16_t u16;
+        struct {
+                uint16_t address_data:16;
+        } s;
+} cvmx_mdio_phy_reg_mmd_address_data_t;
+
+/* Operating request encodings. */
+#define MDIO_CLAUSE_22_WRITE    0
+#define MDIO_CLAUSE_22_READ     1
+
+#define MDIO_CLAUSE_45_ADDRESS  0
+#define MDIO_CLAUSE_45_WRITE    1
+#define MDIO_CLAUSE_45_READ_INC 2
+#define MDIO_CLAUSE_45_READ     3
+
+/* MMD identifiers, mostly for accessing devices withing XENPAK modules. */
+#define CVMX_MMD_DEVICE_PMA_PMD      1
+#define CVMX_MMD_DEVICE_WIS          2
+#define CVMX_MMD_DEVICE_PCS          3
+#define CVMX_MMD_DEVICE_PHY_XS       4
+#define CVMX_MMD_DEVICE_DTS_XS       5
+#define CVMX_MMD_DEVICE_TC           6
+#define CVMX_MMD_DEVICE_CL22_EXT     29
+#define CVMX_MMD_DEVICE_VENDOR_1     30
+#define CVMX_MMD_DEVICE_VENDOR_2     31
+
+/* Helper function to put MDIO interface into clause 45 mode */
+static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
+{
+        union cvmx_smix_clk smi_clk;
+        /* Put bus into clause 45 mode */
+        smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
+        smi_clk.s.mode = 1;
+        smi_clk.s.preamble = 1;
+        cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
+}
+
+/* Helper function to put MDIO interface into clause 22 mode */
+static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
+{
+        union cvmx_smix_clk smi_clk;
+        /* Put bus into clause 22 mode */
+        smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
+        smi_clk.s.mode = 0;
+        cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
+}
+
+/**
+ * Perform an MII read. This function is used to read PHY
+ * registers controlling auto negotiation.
+ *
+ * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
+ *                 support multiple busses.
+ * @phy_id:   The MII phy id
+ * @location: Register location to read
+ *
+ * Returns Result from the read or -1 on failure
+ */
+static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
+{
+        union cvmx_smix_cmd smi_cmd;
+        union cvmx_smix_rd_dat smi_rd;
+        int timeout = 1000;
+
+        if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
+                __cvmx_mdio_set_clause22_mode(bus_id);
+
+        smi_cmd.u64 = 0;
+        smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ;
+        smi_cmd.s.phy_adr = phy_id;
+        smi_cmd.s.reg_adr = location;
+        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+        do {
+                cvmx_wait(1000);
+                smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
+        } while (smi_rd.s.pending && timeout--);
+
+        if (smi_rd.s.val)
+                return smi_rd.s.dat;
+        else
+                return -1;
+}
+
+/**
+ * Perform an MII write. This function is used to write PHY
+ * registers controlling auto negotiation.
+ *
+ * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
+ *                 support multiple busses.
+ * @phy_id:   The MII phy id
+ * @location: Register location to write
+ * @val:      Value to write
+ *
+ * Returns -1 on error
+ *         0 on success
+ */
+static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
+{
+        union cvmx_smix_cmd smi_cmd;
+        union cvmx_smix_wr_dat smi_wr;
+        int timeout = 1000;
+
+        if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
+                __cvmx_mdio_set_clause22_mode(bus_id);
+
+        smi_wr.u64 = 0;
+        smi_wr.s.dat = val;
+        cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
+
+        smi_cmd.u64 = 0;
+        smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE;
+        smi_cmd.s.phy_adr = phy_id;
+        smi_cmd.s.reg_adr = location;
+        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+        do {
+                cvmx_wait(1000);
+                smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
+        } while (smi_wr.s.pending && --timeout);
+        if (timeout <= 0)
+                return -1;
+
+        return 0;
+}
+
+/**
+ * Perform an IEEE 802.3 clause 45 MII read. This function is used to
+ * read PHY registers controlling auto negotiation.
+ *
+ * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
+ *                 support multiple busses.
+ * @phy_id:   The MII phy id
+ * @device:   MDIO Managable Device (MMD) id
+ * @location: Register location to read
+ *
+ * Returns Result from the read or -1 on failure
+ */
+
+static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
+                                    int location)
+{
+        union cvmx_smix_cmd smi_cmd;
+        union cvmx_smix_rd_dat smi_rd;
+        union cvmx_smix_wr_dat smi_wr;
+        int timeout = 1000;
+
+        if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
+                return -1;
+
+        __cvmx_mdio_set_clause45_mode(bus_id);
+
+        smi_wr.u64 = 0;
+        smi_wr.s.dat = location;
+        cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
+
+        smi_cmd.u64 = 0;
+        smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
+        smi_cmd.s.phy_adr = phy_id;
+        smi_cmd.s.reg_adr = device;
+        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+        do {
+                cvmx_wait(1000);
+                smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
+        } while (smi_wr.s.pending && --timeout);
+        if (timeout <= 0) {
+                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
+                             "device %2d register %2d   TIME OUT(address)\n",
+                     bus_id, phy_id, device, location);
+                return -1;
+        }
+
+        smi_cmd.u64 = 0;
+        smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ;
+        smi_cmd.s.phy_adr = phy_id;
+        smi_cmd.s.reg_adr = device;
+        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+        do {
+                cvmx_wait(1000);
+                smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
+        } while (smi_rd.s.pending && timeout--);
+
+        if (timeout <= 0) {
+                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
+                             "device %2d register %2d   TIME OUT(data)\n",
+                     bus_id, phy_id, device, location);
+                return -1;
+        }
+
+        if (smi_rd.s.val)
+                return smi_rd.s.dat;
+        else {
+                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
+                             "device %2d register %2d   INVALID READ\n",
+                     bus_id, phy_id, device, location);
+                return -1;
+        }
+}
+
+/**
+ * Perform an IEEE 802.3 clause 45 MII write. This function is used to
+ * write PHY registers controlling auto negotiation.
+ *
+ * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
+ *                 support multiple busses.
+ * @phy_id:   The MII phy id
+ * @device:   MDIO Managable Device (MMD) id
+ * @location: Register location to write
+ * @val:      Value to write
+ *
+ * Returns -1 on error
+ *         0 on success
+ */
+static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device,
+                                     int location, int val)
+{
+        union cvmx_smix_cmd smi_cmd;
+        union cvmx_smix_wr_dat smi_wr;
+        int timeout = 1000;
+
+        if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45))
+                return -1;
+
+        __cvmx_mdio_set_clause45_mode(bus_id);
+
+        smi_wr.u64 = 0;
+        smi_wr.s.dat = location;
+        cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
+
+        smi_cmd.u64 = 0;
+        smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS;
+        smi_cmd.s.phy_adr = phy_id;
+        smi_cmd.s.reg_adr = device;
+        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+        do {
+                cvmx_wait(1000);
+                smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
+        } while (smi_wr.s.pending && --timeout);
+        if (timeout <= 0)
+                return -1;
+
+        smi_wr.u64 = 0;
+        smi_wr.s.dat = val;
+        cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
+
+        smi_cmd.u64 = 0;
+        smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE;
+        smi_cmd.s.phy_adr = phy_id;
+        smi_cmd.s.reg_adr = device;
+        cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
+
+        do {
+                cvmx_wait(1000);
+                smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id));
+        } while (smi_wr.s.pending && --timeout);
+        if (timeout <= 0)
+                return -1;
+
+        return 0;
+}
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-packet.h b/drivers/staging/octeon/cvmx-packet.h
new file mode 100644
index 000000000000..62ffe78a8c81
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-packet.h
@@ -0,0 +1,65 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * Packet buffer defines.
+ */
+
+#ifndef __CVMX_PACKET_H__
+#define __CVMX_PACKET_H__
+
+/**
+ * This structure defines a buffer pointer on Octeon
+ */
+union cvmx_buf_ptr {
+        void *ptr;
+        uint64_t u64;
+        struct {
+                /*
+                 * if set, invert the "free" pick of the overall
+                 * packet. HW always sets this bit to 0 on inbound
+                 * packet
+                 */
+                uint64_t i:1;
+                /*
+                 * Indicates the amount to back up to get to the
+                 * buffer start in cache lines. In most cases this is
+                 * less than one complete cache line, so the value is
+                 * zero.
+                 */
+                uint64_t back:4;
+                /* The pool that the buffer came from / goes to */
+                uint64_t pool:3;
+                /* The size of the segment pointed to by addr (in bytes) */
+                uint64_t size:16;
+                /* Pointer to the first byte of the data, NOT buffer */
+                uint64_t addr:40;
+        } s;
+};
+
+#endif /*  __CVMX_PACKET_H__ */
diff --git a/drivers/staging/octeon/cvmx-pcsx-defs.h b/drivers/staging/octeon/cvmx-pcsx-defs.h
new file mode 100644
index 000000000000..d45952df5f5b
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-pcsx-defs.h
@@ -0,0 +1,370 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PCSX_DEFS_H__
+#define __CVMX_PCSX_DEFS_H__
+
+#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_INTX_EN_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_INTX_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull))
+
+union cvmx_pcsx_anx_adv_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_anx_adv_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t np:1;
+                uint64_t reserved_14_14:1;
+                uint64_t rem_flt:2;
+                uint64_t reserved_9_11:3;
+                uint64_t pause:2;
+                uint64_t hfd:1;
+                uint64_t fd:1;
+                uint64_t reserved_0_4:5;
+        } s;
+        struct cvmx_pcsx_anx_adv_reg_s cn52xx;
+        struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
+        struct cvmx_pcsx_anx_adv_reg_s cn56xx;
+        struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_anx_ext_st_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_anx_ext_st_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t thou_xfd:1;
+                uint64_t thou_xhd:1;
+                uint64_t thou_tfd:1;
+                uint64_t thou_thd:1;
+                uint64_t reserved_0_11:12;
+        } s;
+        struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
+        struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
+        struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
+        struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_anx_lp_abil_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_anx_lp_abil_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t np:1;
+                uint64_t ack:1;
+                uint64_t rem_flt:2;
+                uint64_t reserved_9_11:3;
+                uint64_t pause:2;
+                uint64_t hfd:1;
+                uint64_t fd:1;
+                uint64_t reserved_0_4:5;
+        } s;
+        struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
+        struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
+        struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
+        struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_anx_results_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_anx_results_reg_s {
+                uint64_t reserved_7_63:57;
+                uint64_t pause:2;
+                uint64_t spd:2;
+                uint64_t an_cpt:1;
+                uint64_t dup:1;
+                uint64_t link_ok:1;
+        } s;
+        struct cvmx_pcsx_anx_results_reg_s cn52xx;
+        struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
+        struct cvmx_pcsx_anx_results_reg_s cn56xx;
+        struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_intx_en_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_intx_en_reg_s {
+                uint64_t reserved_12_63:52;
+                uint64_t dup:1;
+                uint64_t sync_bad_en:1;
+                uint64_t an_bad_en:1;
+                uint64_t rxlock_en:1;
+                uint64_t rxbad_en:1;
+                uint64_t rxerr_en:1;
+                uint64_t txbad_en:1;
+                uint64_t txfifo_en:1;
+                uint64_t txfifu_en:1;
+                uint64_t an_err_en:1;
+                uint64_t xmit_en:1;
+                uint64_t lnkspd_en:1;
+        } s;
+        struct cvmx_pcsx_intx_en_reg_s cn52xx;
+        struct cvmx_pcsx_intx_en_reg_s cn52xxp1;
+        struct cvmx_pcsx_intx_en_reg_s cn56xx;
+        struct cvmx_pcsx_intx_en_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_intx_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_intx_reg_s {
+                uint64_t reserved_12_63:52;
+                uint64_t dup:1;
+                uint64_t sync_bad:1;
+                uint64_t an_bad:1;
+                uint64_t rxlock:1;
+                uint64_t rxbad:1;
+                uint64_t rxerr:1;
+                uint64_t txbad:1;
+                uint64_t txfifo:1;
+                uint64_t txfifu:1;
+                uint64_t an_err:1;
+                uint64_t xmit:1;
+                uint64_t lnkspd:1;
+        } s;
+        struct cvmx_pcsx_intx_reg_s cn52xx;
+        struct cvmx_pcsx_intx_reg_s cn52xxp1;
+        struct cvmx_pcsx_intx_reg_s cn56xx;
+        struct cvmx_pcsx_intx_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_linkx_timer_count_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_linkx_timer_count_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t count:16;
+        } s;
+        struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
+        struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
+        struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
+        struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_log_anlx_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_log_anlx_reg_s {
+                uint64_t reserved_4_63:60;
+                uint64_t lafifovfl:1;
+                uint64_t la_en:1;
+                uint64_t pkt_sz:2;
+        } s;
+        struct cvmx_pcsx_log_anlx_reg_s cn52xx;
+        struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
+        struct cvmx_pcsx_log_anlx_reg_s cn56xx;
+        struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_miscx_ctl_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_miscx_ctl_reg_s {
+                uint64_t reserved_13_63:51;
+                uint64_t sgmii:1;
+                uint64_t gmxeno:1;
+                uint64_t loopbck2:1;
+                uint64_t mac_phy:1;
+                uint64_t mode:1;
+                uint64_t an_ovrd:1;
+                uint64_t samp_pt:7;
+        } s;
+        struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
+        struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
+        struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
+        struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_mrx_control_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_mrx_control_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t reset:1;
+                uint64_t loopbck1:1;
+                uint64_t spdlsb:1;
+                uint64_t an_en:1;
+                uint64_t pwr_dn:1;
+                uint64_t reserved_10_10:1;
+                uint64_t rst_an:1;
+                uint64_t dup:1;
+                uint64_t coltst:1;
+                uint64_t spdmsb:1;
+                uint64_t uni:1;
+                uint64_t reserved_0_4:5;
+        } s;
+        struct cvmx_pcsx_mrx_control_reg_s cn52xx;
+        struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
+        struct cvmx_pcsx_mrx_control_reg_s cn56xx;
+        struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_mrx_status_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_mrx_status_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t hun_t4:1;
+                uint64_t hun_xfd:1;
+                uint64_t hun_xhd:1;
+                uint64_t ten_fd:1;
+                uint64_t ten_hd:1;
+                uint64_t hun_t2fd:1;
+                uint64_t hun_t2hd:1;
+                uint64_t ext_st:1;
+                uint64_t reserved_7_7:1;
+                uint64_t prb_sup:1;
+                uint64_t an_cpt:1;
+                uint64_t rm_flt:1;
+                uint64_t an_abil:1;
+                uint64_t lnk_st:1;
+                uint64_t reserved_1_1:1;
+                uint64_t extnd:1;
+        } s;
+        struct cvmx_pcsx_mrx_status_reg_s cn52xx;
+        struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
+        struct cvmx_pcsx_mrx_status_reg_s cn56xx;
+        struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_rxx_states_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_rxx_states_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t rx_bad:1;
+                uint64_t rx_st:5;
+                uint64_t sync_bad:1;
+                uint64_t sync:4;
+                uint64_t an_bad:1;
+                uint64_t an_st:4;
+        } s;
+        struct cvmx_pcsx_rxx_states_reg_s cn52xx;
+        struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
+        struct cvmx_pcsx_rxx_states_reg_s cn56xx;
+        struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_rxx_sync_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_rxx_sync_reg_s {
+                uint64_t reserved_2_63:62;
+                uint64_t sync:1;
+                uint64_t bit_lock:1;
+        } s;
+        struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
+        struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
+        struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
+        struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_sgmx_an_adv_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_sgmx_an_adv_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t link:1;
+                uint64_t ack:1;
+                uint64_t reserved_13_13:1;
+                uint64_t dup:1;
+                uint64_t speed:2;
+                uint64_t reserved_1_9:9;
+                uint64_t one:1;
+        } s;
+        struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
+        struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
+        struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
+        struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_sgmx_lp_adv_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_sgmx_lp_adv_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t link:1;
+                uint64_t reserved_13_14:2;
+                uint64_t dup:1;
+                uint64_t speed:2;
+                uint64_t reserved_1_9:9;
+                uint64_t one:1;
+        } s;
+        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
+        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
+        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
+        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_txx_states_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_txx_states_reg_s {
+                uint64_t reserved_7_63:57;
+                uint64_t xmit:2;
+                uint64_t tx_bad:1;
+                uint64_t ord_st:4;
+        } s;
+        struct cvmx_pcsx_txx_states_reg_s cn52xx;
+        struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
+        struct cvmx_pcsx_txx_states_reg_s cn56xx;
+        struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
+};
+
+union cvmx_pcsx_tx_rxx_polarity_reg {
+        uint64_t u64;
+        struct cvmx_pcsx_tx_rxx_polarity_reg_s {
+                uint64_t reserved_4_63:60;
+                uint64_t rxovrd:1;
+                uint64_t autorxpl:1;
+                uint64_t rxplrt:1;
+                uint64_t txplrt:1;
+        } s;
+        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
+        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
+        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
+        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-pcsxx-defs.h b/drivers/staging/octeon/cvmx-pcsxx-defs.h
new file mode 100644
index 000000000000..55d120fe8aed
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-pcsxx-defs.h
@@ -0,0 +1,316 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PCSXX_DEFS_H__
+#define __CVMX_PCSXX_DEFS_H__
+
+#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_BIST_STATUS_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_CONTROL1_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_CONTROL2_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_INT_EN_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_INT_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_LOG_ANL_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_MISC_CTL_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_SPD_ABIL_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_STATUS1_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_STATUS2_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull))
+
+union cvmx_pcsxx_10gbx_status_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_10gbx_status_reg_s {
+                uint64_t reserved_13_63:51;
+                uint64_t alignd:1;
+                uint64_t pattst:1;
+                uint64_t reserved_4_10:7;
+                uint64_t l3sync:1;
+                uint64_t l2sync:1;
+                uint64_t l1sync:1;
+                uint64_t l0sync:1;
+        } s;
+        struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
+        struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
+        struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
+        struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_bist_status_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_bist_status_reg_s {
+                uint64_t reserved_1_63:63;
+                uint64_t bist_status:1;
+        } s;
+        struct cvmx_pcsxx_bist_status_reg_s cn52xx;
+        struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
+        struct cvmx_pcsxx_bist_status_reg_s cn56xx;
+        struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_bit_lock_status_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_bit_lock_status_reg_s {
+                uint64_t reserved_4_63:60;
+                uint64_t bitlck3:1;
+                uint64_t bitlck2:1;
+                uint64_t bitlck1:1;
+                uint64_t bitlck0:1;
+        } s;
+        struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
+        struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
+        struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
+        struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_control1_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_control1_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t reset:1;
+                uint64_t loopbck1:1;
+                uint64_t spdsel1:1;
+                uint64_t reserved_12_12:1;
+                uint64_t lo_pwr:1;
+                uint64_t reserved_7_10:4;
+                uint64_t spdsel0:1;
+                uint64_t spd:4;
+                uint64_t reserved_0_1:2;
+        } s;
+        struct cvmx_pcsxx_control1_reg_s cn52xx;
+        struct cvmx_pcsxx_control1_reg_s cn52xxp1;
+        struct cvmx_pcsxx_control1_reg_s cn56xx;
+        struct cvmx_pcsxx_control1_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_control2_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_control2_reg_s {
+                uint64_t reserved_2_63:62;
+                uint64_t type:2;
+        } s;
+        struct cvmx_pcsxx_control2_reg_s cn52xx;
+        struct cvmx_pcsxx_control2_reg_s cn52xxp1;
+        struct cvmx_pcsxx_control2_reg_s cn56xx;
+        struct cvmx_pcsxx_control2_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_int_en_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_int_en_reg_s {
+                uint64_t reserved_6_63:58;
+                uint64_t algnlos_en:1;
+                uint64_t synlos_en:1;
+                uint64_t bitlckls_en:1;
+                uint64_t rxsynbad_en:1;
+                uint64_t rxbad_en:1;
+                uint64_t txflt_en:1;
+        } s;
+        struct cvmx_pcsxx_int_en_reg_s cn52xx;
+        struct cvmx_pcsxx_int_en_reg_s cn52xxp1;
+        struct cvmx_pcsxx_int_en_reg_s cn56xx;
+        struct cvmx_pcsxx_int_en_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_int_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_int_reg_s {
+                uint64_t reserved_6_63:58;
+                uint64_t algnlos:1;
+                uint64_t synlos:1;
+                uint64_t bitlckls:1;
+                uint64_t rxsynbad:1;
+                uint64_t rxbad:1;
+                uint64_t txflt:1;
+        } s;
+        struct cvmx_pcsxx_int_reg_s cn52xx;
+        struct cvmx_pcsxx_int_reg_s cn52xxp1;
+        struct cvmx_pcsxx_int_reg_s cn56xx;
+        struct cvmx_pcsxx_int_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_log_anl_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_log_anl_reg_s {
+                uint64_t reserved_7_63:57;
+                uint64_t enc_mode:1;
+                uint64_t drop_ln:2;
+                uint64_t lafifovfl:1;
+                uint64_t la_en:1;
+                uint64_t pkt_sz:2;
+        } s;
+        struct cvmx_pcsxx_log_anl_reg_s cn52xx;
+        struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
+        struct cvmx_pcsxx_log_anl_reg_s cn56xx;
+        struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_misc_ctl_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_misc_ctl_reg_s {
+                uint64_t reserved_4_63:60;
+                uint64_t tx_swap:1;
+                uint64_t rx_swap:1;
+                uint64_t xaui:1;
+                uint64_t gmxeno:1;
+        } s;
+        struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
+        struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
+        struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
+        struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_rx_sync_states_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_rx_sync_states_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t sync3st:4;
+                uint64_t sync2st:4;
+                uint64_t sync1st:4;
+                uint64_t sync0st:4;
+        } s;
+        struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
+        struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
+        struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
+        struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_spd_abil_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_spd_abil_reg_s {
+                uint64_t reserved_2_63:62;
+                uint64_t tenpasst:1;
+                uint64_t tengb:1;
+        } s;
+        struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
+        struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
+        struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
+        struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_status1_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_status1_reg_s {
+                uint64_t reserved_8_63:56;
+                uint64_t flt:1;
+                uint64_t reserved_3_6:4;
+                uint64_t rcv_lnk:1;
+                uint64_t lpable:1;
+                uint64_t reserved_0_0:1;
+        } s;
+        struct cvmx_pcsxx_status1_reg_s cn52xx;
+        struct cvmx_pcsxx_status1_reg_s cn52xxp1;
+        struct cvmx_pcsxx_status1_reg_s cn56xx;
+        struct cvmx_pcsxx_status1_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_status2_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_status2_reg_s {
+                uint64_t reserved_16_63:48;
+                uint64_t dev:2;
+                uint64_t reserved_12_13:2;
+                uint64_t xmtflt:1;
+                uint64_t rcvflt:1;
+                uint64_t reserved_3_9:7;
+                uint64_t tengb_w:1;
+                uint64_t tengb_x:1;
+                uint64_t tengb_r:1;
+        } s;
+        struct cvmx_pcsxx_status2_reg_s cn52xx;
+        struct cvmx_pcsxx_status2_reg_s cn52xxp1;
+        struct cvmx_pcsxx_status2_reg_s cn56xx;
+        struct cvmx_pcsxx_status2_reg_s cn56xxp1;
+};
+
+union cvmx_pcsxx_tx_rx_polarity_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_tx_rx_polarity_reg_s {
+                uint64_t reserved_10_63:54;
+                uint64_t xor_rxplrt:4;
+                uint64_t xor_txplrt:4;
+                uint64_t rxplrt:1;
+                uint64_t txplrt:1;
+        } s;
+        struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
+        struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
+                uint64_t reserved_2_63:62;
+                uint64_t rxplrt:1;
+                uint64_t txplrt:1;
+        } cn52xxp1;
+        struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
+        struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
+};
+
+union cvmx_pcsxx_tx_rx_states_reg {
+        uint64_t u64;
+        struct cvmx_pcsxx_tx_rx_states_reg_s {
+                uint64_t reserved_14_63:50;
+                uint64_t term_err:1;
+                uint64_t syn3bad:1;
+                uint64_t syn2bad:1;
+                uint64_t syn1bad:1;
+                uint64_t syn0bad:1;
+                uint64_t rxbad:1;
+                uint64_t algn_st:3;
+                uint64_t rx_st:2;
+                uint64_t tx_st:3;
+        } s;
+        struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
+        struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
+                uint64_t reserved_13_63:51;
+                uint64_t syn3bad:1;
+                uint64_t syn2bad:1;
+                uint64_t syn1bad:1;
+                uint64_t syn0bad:1;
+                uint64_t rxbad:1;
+                uint64_t algn_st:3;
+                uint64_t rx_st:2;
+                uint64_t tx_st:3;
+        } cn52xxp1;
+        struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
+        struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-pip-defs.h b/drivers/staging/octeon/cvmx-pip-defs.h
new file mode 100644
index 000000000000..5a369100ca68
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-pip-defs.h
@@ -0,0 +1,1267 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PIP_DEFS_H__
+#define __CVMX_PIP_DEFS_H__
+
+/*
+ * Enumeration representing the amount of packet processing
+ * and validation performed by the input hardware.
+ */
+enum cvmx_pip_port_parse_mode {
+        /*
+         * Packet input doesn't perform any processing of the input
+         * packet.
+         */
+        CVMX_PIP_PORT_CFG_MODE_NONE = 0ull,
+        /*
+         * Full packet processing is performed with pointer starting
+         * at the L2 (ethernet MAC) header.
+         */
+        CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,
+        /*
+         * Input packets are assumed to be IP.  Results from non IP
+         * packets is undefined. Pointers reference the beginning of
+         * the IP header.
+         */
+        CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull
+};
+
+#define CVMX_PIP_BCK_PRS \
+         CVMX_ADD_IO_SEG(0x00011800A0000038ull)
+#define CVMX_PIP_BIST_STATUS \
+         CVMX_ADD_IO_SEG(0x00011800A0000000ull)
+#define CVMX_PIP_CRC_CTLX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000040ull + (((offset) & 1) * 8))
+#define CVMX_PIP_CRC_IVX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000050ull + (((offset) & 1) * 8))
+#define CVMX_PIP_DEC_IPSECX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000080ull + (((offset) & 3) * 8))
+#define CVMX_PIP_DSA_SRC_GRP \
+         CVMX_ADD_IO_SEG(0x00011800A0000190ull)
+#define CVMX_PIP_DSA_VID_GRP \
+         CVMX_ADD_IO_SEG(0x00011800A0000198ull)
+#define CVMX_PIP_FRM_LEN_CHKX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000180ull + (((offset) & 1) * 8))
+#define CVMX_PIP_GBL_CFG \
+         CVMX_ADD_IO_SEG(0x00011800A0000028ull)
+#define CVMX_PIP_GBL_CTL \
+         CVMX_ADD_IO_SEG(0x00011800A0000020ull)
+#define CVMX_PIP_HG_PRI_QOS \
+         CVMX_ADD_IO_SEG(0x00011800A00001A0ull)
+#define CVMX_PIP_INT_EN \
+         CVMX_ADD_IO_SEG(0x00011800A0000010ull)
+#define CVMX_PIP_INT_REG \
+         CVMX_ADD_IO_SEG(0x00011800A0000008ull)
+#define CVMX_PIP_IP_OFFSET \
+         CVMX_ADD_IO_SEG(0x00011800A0000060ull)
+#define CVMX_PIP_PRT_CFGX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000200ull + (((offset) & 63) * 8))
+#define CVMX_PIP_PRT_TAGX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000400ull + (((offset) & 63) * 8))
+#define CVMX_PIP_QOS_DIFFX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000600ull + (((offset) & 63) * 8))
+#define CVMX_PIP_QOS_VLANX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A00000C0ull + (((offset) & 7) * 8))
+#define CVMX_PIP_QOS_WATCHX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000100ull + (((offset) & 7) * 8))
+#define CVMX_PIP_RAW_WORD \
+         CVMX_ADD_IO_SEG(0x00011800A00000B0ull)
+#define CVMX_PIP_SFT_RST \
+         CVMX_ADD_IO_SEG(0x00011800A0000030ull)
+#define CVMX_PIP_STAT0_PRTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000800ull + (((offset) & 63) * 80))
+#define CVMX_PIP_STAT1_PRTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000808ull + (((offset) & 63) * 80))
+#define CVMX_PIP_STAT2_PRTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000810ull + (((offset) & 63) * 80))
+#define CVMX_PIP_STAT3_PRTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000818ull + (((offset) & 63) * 80))
+#define CVMX_PIP_STAT4_PRTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000820ull + (((offset) & 63) * 80))
+#define CVMX_PIP_STAT5_PRTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000828ull + (((offset) & 63) * 80))
+#define CVMX_PIP_STAT6_PRTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000830ull + (((offset) & 63) * 80))
+#define CVMX_PIP_STAT7_PRTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000838ull + (((offset) & 63) * 80))
+#define CVMX_PIP_STAT8_PRTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000840ull + (((offset) & 63) * 80))
+#define CVMX_PIP_STAT9_PRTX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0000848ull + (((offset) & 63) * 80))
+#define CVMX_PIP_STAT_CTL \
+         CVMX_ADD_IO_SEG(0x00011800A0000018ull)
+#define CVMX_PIP_STAT_INB_ERRSX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0001A10ull + (((offset) & 63) * 32))
+#define CVMX_PIP_STAT_INB_OCTSX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0001A08ull + (((offset) & 63) * 32))
+#define CVMX_PIP_STAT_INB_PKTSX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0001A00ull + (((offset) & 63) * 32))
+#define CVMX_PIP_TAG_INCX(offset) \
+         CVMX_ADD_IO_SEG(0x00011800A0001800ull + (((offset) & 63) * 8))
+#define CVMX_PIP_TAG_MASK \
+         CVMX_ADD_IO_SEG(0x00011800A0000070ull)
+#define CVMX_PIP_TAG_SECRET \
+         CVMX_ADD_IO_SEG(0x00011800A0000068ull)
+#define CVMX_PIP_TODO_ENTRY \
+         CVMX_ADD_IO_SEG(0x00011800A0000078ull)
+
+union cvmx_pip_bck_prs {
+        uint64_t u64;
+        struct cvmx_pip_bck_prs_s {
+                uint64_t bckprs:1;
+                uint64_t reserved_13_62:50;
+                uint64_t hiwater:5;
+                uint64_t reserved_5_7:3;
+                uint64_t lowater:5;
+        } s;
+        struct cvmx_pip_bck_prs_s cn38xx;
+        struct cvmx_pip_bck_prs_s cn38xxp2;
+        struct cvmx_pip_bck_prs_s cn56xx;
+        struct cvmx_pip_bck_prs_s cn56xxp1;
+        struct cvmx_pip_bck_prs_s cn58xx;
+        struct cvmx_pip_bck_prs_s cn58xxp1;
+};
+
+union cvmx_pip_bist_status {
+        uint64_t u64;
+        struct cvmx_pip_bist_status_s {
+                uint64_t reserved_18_63:46;
+                uint64_t bist:18;
+        } s;
+        struct cvmx_pip_bist_status_s cn30xx;
+        struct cvmx_pip_bist_status_s cn31xx;
+        struct cvmx_pip_bist_status_s cn38xx;
+        struct cvmx_pip_bist_status_s cn38xxp2;
+        struct cvmx_pip_bist_status_cn50xx {
+                uint64_t reserved_17_63:47;
+                uint64_t bist:17;
+        } cn50xx;
+        struct cvmx_pip_bist_status_s cn52xx;
+        struct cvmx_pip_bist_status_s cn52xxp1;
+        struct cvmx_pip_bist_status_s cn56xx;
+        struct cvmx_pip_bist_status_s cn56xxp1;
+        struct cvmx_pip_bist_status_s cn58xx;
+        struct cvmx_pip_bist_status_s cn58xxp1;
+};
+
+union cvmx_pip_crc_ctlx {
+        uint64_t u64;
+        struct cvmx_pip_crc_ctlx_s {
+                uint64_t reserved_2_63:62;
+                uint64_t invres:1;
+                uint64_t reflect:1;
+        } s;
+        struct cvmx_pip_crc_ctlx_s cn38xx;
+        struct cvmx_pip_crc_ctlx_s cn38xxp2;
+        struct cvmx_pip_crc_ctlx_s cn58xx;
+        struct cvmx_pip_crc_ctlx_s cn58xxp1;
+};
+
+union cvmx_pip_crc_ivx {
+        uint64_t u64;
+        struct cvmx_pip_crc_ivx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t iv:32;
+        } s;
+        struct cvmx_pip_crc_ivx_s cn38xx;
+        struct cvmx_pip_crc_ivx_s cn38xxp2;
+        struct cvmx_pip_crc_ivx_s cn58xx;
+        struct cvmx_pip_crc_ivx_s cn58xxp1;
+};
+
+union cvmx_pip_dec_ipsecx {
+        uint64_t u64;
+        struct cvmx_pip_dec_ipsecx_s {
+                uint64_t reserved_18_63:46;
+                uint64_t tcp:1;
+                uint64_t udp:1;
+                uint64_t dprt:16;
+        } s;
+        struct cvmx_pip_dec_ipsecx_s cn30xx;
+        struct cvmx_pip_dec_ipsecx_s cn31xx;
+        struct cvmx_pip_dec_ipsecx_s cn38xx;
+        struct cvmx_pip_dec_ipsecx_s cn38xxp2;
+        struct cvmx_pip_dec_ipsecx_s cn50xx;
+        struct cvmx_pip_dec_ipsecx_s cn52xx;
+        struct cvmx_pip_dec_ipsecx_s cn52xxp1;
+        struct cvmx_pip_dec_ipsecx_s cn56xx;
+        struct cvmx_pip_dec_ipsecx_s cn56xxp1;
+        struct cvmx_pip_dec_ipsecx_s cn58xx;
+        struct cvmx_pip_dec_ipsecx_s cn58xxp1;
+};
+
+union cvmx_pip_dsa_src_grp {
+        uint64_t u64;
+        struct cvmx_pip_dsa_src_grp_s {
+                uint64_t map15:4;
+                uint64_t map14:4;
+                uint64_t map13:4;
+                uint64_t map12:4;
+                uint64_t map11:4;
+                uint64_t map10:4;
+                uint64_t map9:4;
+                uint64_t map8:4;
+                uint64_t map7:4;
+                uint64_t map6:4;
+                uint64_t map5:4;
+                uint64_t map4:4;
+                uint64_t map3:4;
+                uint64_t map2:4;
+                uint64_t map1:4;
+                uint64_t map0:4;
+        } s;
+        struct cvmx_pip_dsa_src_grp_s cn52xx;
+        struct cvmx_pip_dsa_src_grp_s cn52xxp1;
+        struct cvmx_pip_dsa_src_grp_s cn56xx;
+};
+
+union cvmx_pip_dsa_vid_grp {
+        uint64_t u64;
+        struct cvmx_pip_dsa_vid_grp_s {
+                uint64_t map15:4;
+                uint64_t map14:4;
+                uint64_t map13:4;
+                uint64_t map12:4;
+                uint64_t map11:4;
+                uint64_t map10:4;
+                uint64_t map9:4;
+                uint64_t map8:4;
+                uint64_t map7:4;
+                uint64_t map6:4;
+                uint64_t map5:4;
+                uint64_t map4:4;
+                uint64_t map3:4;
+                uint64_t map2:4;
+                uint64_t map1:4;
+                uint64_t map0:4;
+        } s;
+        struct cvmx_pip_dsa_vid_grp_s cn52xx;
+        struct cvmx_pip_dsa_vid_grp_s cn52xxp1;
+        struct cvmx_pip_dsa_vid_grp_s cn56xx;
+};
+
+union cvmx_pip_frm_len_chkx {
+        uint64_t u64;
+        struct cvmx_pip_frm_len_chkx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t maxlen:16;
+                uint64_t minlen:16;
+        } s;
+        struct cvmx_pip_frm_len_chkx_s cn50xx;
+        struct cvmx_pip_frm_len_chkx_s cn52xx;
+        struct cvmx_pip_frm_len_chkx_s cn52xxp1;
+        struct cvmx_pip_frm_len_chkx_s cn56xx;
+        struct cvmx_pip_frm_len_chkx_s cn56xxp1;
+};
+
+union cvmx_pip_gbl_cfg {
+        uint64_t u64;
+        struct cvmx_pip_gbl_cfg_s {
+                uint64_t reserved_19_63:45;
+                uint64_t tag_syn:1;
+                uint64_t ip6_udp:1;
+                uint64_t max_l2:1;
+                uint64_t reserved_11_15:5;
+                uint64_t raw_shf:3;
+                uint64_t reserved_3_7:5;
+                uint64_t nip_shf:3;
+        } s;
+        struct cvmx_pip_gbl_cfg_s cn30xx;
+        struct cvmx_pip_gbl_cfg_s cn31xx;
+        struct cvmx_pip_gbl_cfg_s cn38xx;
+        struct cvmx_pip_gbl_cfg_s cn38xxp2;
+        struct cvmx_pip_gbl_cfg_s cn50xx;
+        struct cvmx_pip_gbl_cfg_s cn52xx;
+        struct cvmx_pip_gbl_cfg_s cn52xxp1;
+        struct cvmx_pip_gbl_cfg_s cn56xx;
+        struct cvmx_pip_gbl_cfg_s cn56xxp1;
+        struct cvmx_pip_gbl_cfg_s cn58xx;
+        struct cvmx_pip_gbl_cfg_s cn58xxp1;
+};
+
+union cvmx_pip_gbl_ctl {
+        uint64_t u64;
+        struct cvmx_pip_gbl_ctl_s {
+                uint64_t reserved_27_63:37;
+                uint64_t dsa_grp_tvid:1;
+                uint64_t dsa_grp_scmd:1;
+                uint64_t dsa_grp_sid:1;
+                uint64_t reserved_21_23:3;
+                uint64_t ring_en:1;
+                uint64_t reserved_17_19:3;
+                uint64_t ignrs:1;
+                uint64_t vs_wqe:1;
+                uint64_t vs_qos:1;
+                uint64_t l2_mal:1;
+                uint64_t tcp_flag:1;
+                uint64_t l4_len:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_mal:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ip6_eext:2;
+                uint64_t ip4_opts:1;
+                uint64_t ip_hop:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_chk:1;
+        } s;
+        struct cvmx_pip_gbl_ctl_cn30xx {
+                uint64_t reserved_17_63:47;
+                uint64_t ignrs:1;
+                uint64_t vs_wqe:1;
+                uint64_t vs_qos:1;
+                uint64_t l2_mal:1;
+                uint64_t tcp_flag:1;
+                uint64_t l4_len:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_mal:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ip6_eext:2;
+                uint64_t ip4_opts:1;
+                uint64_t ip_hop:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_chk:1;
+        } cn30xx;
+        struct cvmx_pip_gbl_ctl_cn30xx cn31xx;
+        struct cvmx_pip_gbl_ctl_cn30xx cn38xx;
+        struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2;
+        struct cvmx_pip_gbl_ctl_cn30xx cn50xx;
+        struct cvmx_pip_gbl_ctl_s cn52xx;
+        struct cvmx_pip_gbl_ctl_s cn52xxp1;
+        struct cvmx_pip_gbl_ctl_s cn56xx;
+        struct cvmx_pip_gbl_ctl_cn56xxp1 {
+                uint64_t reserved_21_63:43;
+                uint64_t ring_en:1;
+                uint64_t reserved_17_19:3;
+                uint64_t ignrs:1;
+                uint64_t vs_wqe:1;
+                uint64_t vs_qos:1;
+                uint64_t l2_mal:1;
+                uint64_t tcp_flag:1;
+                uint64_t l4_len:1;
+                uint64_t l4_chk:1;
+                uint64_t l4_prt:1;
+                uint64_t l4_mal:1;
+                uint64_t reserved_6_7:2;
+                uint64_t ip6_eext:2;
+                uint64_t ip4_opts:1;
+                uint64_t ip_hop:1;
+                uint64_t ip_mal:1;
+                uint64_t ip_chk:1;
+        } cn56xxp1;
+        struct cvmx_pip_gbl_ctl_cn30xx cn58xx;
+        struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1;
+};
+
+union cvmx_pip_hg_pri_qos {
+        uint64_t u64;
+        struct cvmx_pip_hg_pri_qos_s {
+                uint64_t reserved_11_63:53;
+                uint64_t qos:3;
+                uint64_t reserved_6_7:2;
+                uint64_t pri:6;
+        } s;
+        struct cvmx_pip_hg_pri_qos_s cn52xx;
+        struct cvmx_pip_hg_pri_qos_s cn52xxp1;
+        struct cvmx_pip_hg_pri_qos_s cn56xx;
+};
+
+union cvmx_pip_int_en {
+        uint64_t u64;
+        struct cvmx_pip_int_en_s {
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+        } s;
+        struct cvmx_pip_int_en_cn30xx {
+                uint64_t reserved_9_63:55;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+        } cn30xx;
+        struct cvmx_pip_int_en_cn30xx cn31xx;
+        struct cvmx_pip_int_en_cn30xx cn38xx;
+        struct cvmx_pip_int_en_cn30xx cn38xxp2;
+        struct cvmx_pip_int_en_cn50xx {
+                uint64_t reserved_12_63:52;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pktdrp:1;
+        } cn50xx;
+        struct cvmx_pip_int_en_cn52xx {
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pktdrp:1;
+        } cn52xx;
+        struct cvmx_pip_int_en_cn52xx cn52xxp1;
+        struct cvmx_pip_int_en_s cn56xx;
+        struct cvmx_pip_int_en_cn56xxp1 {
+                uint64_t reserved_12_63:52;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+        } cn56xxp1;
+        struct cvmx_pip_int_en_cn58xx {
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t reserved_9_11:3;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+        } cn58xx;
+        struct cvmx_pip_int_en_cn30xx cn58xxp1;
+};
+
+union cvmx_pip_int_reg {
+        uint64_t u64;
+        struct cvmx_pip_int_reg_s {
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+        } s;
+        struct cvmx_pip_int_reg_cn30xx {
+                uint64_t reserved_9_63:55;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+        } cn30xx;
+        struct cvmx_pip_int_reg_cn30xx cn31xx;
+        struct cvmx_pip_int_reg_cn30xx cn38xx;
+        struct cvmx_pip_int_reg_cn30xx cn38xxp2;
+        struct cvmx_pip_int_reg_cn50xx {
+                uint64_t reserved_12_63:52;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pktdrp:1;
+        } cn50xx;
+        struct cvmx_pip_int_reg_cn52xx {
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t reserved_1_1:1;
+                uint64_t pktdrp:1;
+        } cn52xx;
+        struct cvmx_pip_int_reg_cn52xx cn52xxp1;
+        struct cvmx_pip_int_reg_s cn56xx;
+        struct cvmx_pip_int_reg_cn56xxp1 {
+                uint64_t reserved_12_63:52;
+                uint64_t lenerr:1;
+                uint64_t maxerr:1;
+                uint64_t minerr:1;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+        } cn56xxp1;
+        struct cvmx_pip_int_reg_cn58xx {
+                uint64_t reserved_13_63:51;
+                uint64_t punyerr:1;
+                uint64_t reserved_9_11:3;
+                uint64_t beperr:1;
+                uint64_t feperr:1;
+                uint64_t todoovr:1;
+                uint64_t skprunt:1;
+                uint64_t badtag:1;
+                uint64_t prtnxa:1;
+                uint64_t bckprs:1;
+                uint64_t crcerr:1;
+                uint64_t pktdrp:1;
+        } cn58xx;
+        struct cvmx_pip_int_reg_cn30xx cn58xxp1;
+};
+
+union cvmx_pip_ip_offset {
+        uint64_t u64;
+        struct cvmx_pip_ip_offset_s {
+                uint64_t reserved_3_63:61;
+                uint64_t offset:3;
+        } s;
+        struct cvmx_pip_ip_offset_s cn30xx;
+        struct cvmx_pip_ip_offset_s cn31xx;
+        struct cvmx_pip_ip_offset_s cn38xx;
+        struct cvmx_pip_ip_offset_s cn38xxp2;
+        struct cvmx_pip_ip_offset_s cn50xx;
+        struct cvmx_pip_ip_offset_s cn52xx;
+        struct cvmx_pip_ip_offset_s cn52xxp1;
+        struct cvmx_pip_ip_offset_s cn56xx;
+        struct cvmx_pip_ip_offset_s cn56xxp1;
+        struct cvmx_pip_ip_offset_s cn58xx;
+        struct cvmx_pip_ip_offset_s cn58xxp1;
+};
+
+union cvmx_pip_prt_cfgx {
+        uint64_t u64;
+        struct cvmx_pip_prt_cfgx_s {
+                uint64_t reserved_53_63:11;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t lenerr_en:1;
+                uint64_t maxerr_en:1;
+                uint64_t minerr_en:1;
+                uint64_t grp_wat_47:4;
+                uint64_t qos_wat_47:4;
+                uint64_t reserved_37_39:3;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t hg_qos:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t qos_vsel:1;
+                uint64_t qos_vod:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_13_15:3;
+                uint64_t crc_en:1;
+                uint64_t higig_en:1;
+                uint64_t dsa_en:1;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+        } s;
+        struct cvmx_pip_prt_cfgx_cn30xx {
+                uint64_t reserved_37_63:27;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t reserved_27_27:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t reserved_18_19:2;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_10_15:6;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+        } cn30xx;
+        struct cvmx_pip_prt_cfgx_cn30xx cn31xx;
+        struct cvmx_pip_prt_cfgx_cn38xx {
+                uint64_t reserved_37_63:27;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t reserved_27_27:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t reserved_18_19:2;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_13_15:3;
+                uint64_t crc_en:1;
+                uint64_t reserved_10_11:2;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+        } cn38xx;
+        struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2;
+        struct cvmx_pip_prt_cfgx_cn50xx {
+                uint64_t reserved_53_63:11;
+                uint64_t pad_len:1;
+                uint64_t vlan_len:1;
+                uint64_t lenerr_en:1;
+                uint64_t maxerr_en:1;
+                uint64_t minerr_en:1;
+                uint64_t grp_wat_47:4;
+                uint64_t qos_wat_47:4;
+                uint64_t reserved_37_39:3;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t reserved_27_27:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t reserved_19_19:1;
+                uint64_t qos_vod:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_13_15:3;
+                uint64_t crc_en:1;
+                uint64_t reserved_10_11:2;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+        } cn50xx;
+        struct cvmx_pip_prt_cfgx_s cn52xx;
+        struct cvmx_pip_prt_cfgx_s cn52xxp1;
+        struct cvmx_pip_prt_cfgx_s cn56xx;
+        struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1;
+        struct cvmx_pip_prt_cfgx_cn58xx {
+                uint64_t reserved_37_63:27;
+                uint64_t rawdrp:1;
+                uint64_t tag_inc:2;
+                uint64_t dyn_rs:1;
+                uint64_t inst_hdr:1;
+                uint64_t grp_wat:4;
+                uint64_t reserved_27_27:1;
+                uint64_t qos:3;
+                uint64_t qos_wat:4;
+                uint64_t reserved_19_19:1;
+                uint64_t qos_vod:1;
+                uint64_t qos_diff:1;
+                uint64_t qos_vlan:1;
+                uint64_t reserved_13_15:3;
+                uint64_t crc_en:1;
+                uint64_t reserved_10_11:2;
+                uint64_t mode:2;
+                uint64_t reserved_7_7:1;
+                uint64_t skip:7;
+        } cn58xx;
+        struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1;
+};
+
+union cvmx_pip_prt_tagx {
+        uint64_t u64;
+        struct cvmx_pip_prt_tagx_s {
+                uint64_t reserved_40_63:24;
+                uint64_t grptagbase:4;
+                uint64_t grptagmask:4;
+                uint64_t grptag:1;
+                uint64_t grptag_mskip:1;
+                uint64_t tag_mode:2;
+                uint64_t inc_vs:2;
+                uint64_t inc_vlan:1;
+                uint64_t inc_prt_flag:1;
+                uint64_t ip6_dprt_flag:1;
+                uint64_t ip4_dprt_flag:1;
+                uint64_t ip6_sprt_flag:1;
+                uint64_t ip4_sprt_flag:1;
+                uint64_t ip6_nxth_flag:1;
+                uint64_t ip4_pctl_flag:1;
+                uint64_t ip6_dst_flag:1;
+                uint64_t ip4_dst_flag:1;
+                uint64_t ip6_src_flag:1;
+                uint64_t ip4_src_flag:1;
+                uint64_t tcp6_tag_type:2;
+                uint64_t tcp4_tag_type:2;
+                uint64_t ip6_tag_type:2;
+                uint64_t ip4_tag_type:2;
+                uint64_t non_tag_type:2;
+                uint64_t grp:4;
+        } s;
+        struct cvmx_pip_prt_tagx_cn30xx {
+                uint64_t reserved_40_63:24;
+                uint64_t grptagbase:4;
+                uint64_t grptagmask:4;
+                uint64_t grptag:1;
+                uint64_t reserved_30_30:1;
+                uint64_t tag_mode:2;
+                uint64_t inc_vs:2;
+                uint64_t inc_vlan:1;
+                uint64_t inc_prt_flag:1;
+                uint64_t ip6_dprt_flag:1;
+                uint64_t ip4_dprt_flag:1;
+                uint64_t ip6_sprt_flag:1;
+                uint64_t ip4_sprt_flag:1;
+                uint64_t ip6_nxth_flag:1;
+                uint64_t ip4_pctl_flag:1;
+                uint64_t ip6_dst_flag:1;
+                uint64_t ip4_dst_flag:1;
+                uint64_t ip6_src_flag:1;
+                uint64_t ip4_src_flag:1;
+                uint64_t tcp6_tag_type:2;
+                uint64_t tcp4_tag_type:2;
+                uint64_t ip6_tag_type:2;
+                uint64_t ip4_tag_type:2;
+                uint64_t non_tag_type:2;
+                uint64_t grp:4;
+        } cn30xx;
+        struct cvmx_pip_prt_tagx_cn30xx cn31xx;
+        struct cvmx_pip_prt_tagx_cn30xx cn38xx;
+        struct cvmx_pip_prt_tagx_cn30xx cn38xxp2;
+        struct cvmx_pip_prt_tagx_s cn50xx;
+        struct cvmx_pip_prt_tagx_s cn52xx;
+        struct cvmx_pip_prt_tagx_s cn52xxp1;
+        struct cvmx_pip_prt_tagx_s cn56xx;
+        struct cvmx_pip_prt_tagx_s cn56xxp1;
+        struct cvmx_pip_prt_tagx_cn30xx cn58xx;
+        struct cvmx_pip_prt_tagx_cn30xx cn58xxp1;
+};
+
+union cvmx_pip_qos_diffx {
+        uint64_t u64;
+        struct cvmx_pip_qos_diffx_s {
+                uint64_t reserved_3_63:61;
+                uint64_t qos:3;
+        } s;
+        struct cvmx_pip_qos_diffx_s cn30xx;
+        struct cvmx_pip_qos_diffx_s cn31xx;
+        struct cvmx_pip_qos_diffx_s cn38xx;
+        struct cvmx_pip_qos_diffx_s cn38xxp2;
+        struct cvmx_pip_qos_diffx_s cn50xx;
+        struct cvmx_pip_qos_diffx_s cn52xx;
+        struct cvmx_pip_qos_diffx_s cn52xxp1;
+        struct cvmx_pip_qos_diffx_s cn56xx;
+        struct cvmx_pip_qos_diffx_s cn56xxp1;
+        struct cvmx_pip_qos_diffx_s cn58xx;
+        struct cvmx_pip_qos_diffx_s cn58xxp1;
+};
+
+union cvmx_pip_qos_vlanx {
+        uint64_t u64;
+        struct cvmx_pip_qos_vlanx_s {
+                uint64_t reserved_7_63:57;
+                uint64_t qos1:3;
+                uint64_t reserved_3_3:1;
+                uint64_t qos:3;
+        } s;
+        struct cvmx_pip_qos_vlanx_cn30xx {
+                uint64_t reserved_3_63:61;
+                uint64_t qos:3;
+        } cn30xx;
+        struct cvmx_pip_qos_vlanx_cn30xx cn31xx;
+        struct cvmx_pip_qos_vlanx_cn30xx cn38xx;
+        struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2;
+        struct cvmx_pip_qos_vlanx_cn30xx cn50xx;
+        struct cvmx_pip_qos_vlanx_s cn52xx;
+        struct cvmx_pip_qos_vlanx_s cn52xxp1;
+        struct cvmx_pip_qos_vlanx_s cn56xx;
+        struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1;
+        struct cvmx_pip_qos_vlanx_cn30xx cn58xx;
+        struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1;
+};
+
+union cvmx_pip_qos_watchx {
+        uint64_t u64;
+        struct cvmx_pip_qos_watchx_s {
+                uint64_t reserved_48_63:16;
+                uint64_t mask:16;
+                uint64_t reserved_28_31:4;
+                uint64_t grp:4;
+                uint64_t reserved_23_23:1;
+                uint64_t qos:3;
+                uint64_t reserved_19_19:1;
+                uint64_t match_type:3;
+                uint64_t match_value:16;
+        } s;
+        struct cvmx_pip_qos_watchx_cn30xx {
+                uint64_t reserved_48_63:16;
+                uint64_t mask:16;
+                uint64_t reserved_28_31:4;
+                uint64_t grp:4;
+                uint64_t reserved_23_23:1;
+                uint64_t qos:3;
+                uint64_t reserved_18_19:2;
+                uint64_t match_type:2;
+                uint64_t match_value:16;
+        } cn30xx;
+        struct cvmx_pip_qos_watchx_cn30xx cn31xx;
+        struct cvmx_pip_qos_watchx_cn30xx cn38xx;
+        struct cvmx_pip_qos_watchx_cn30xx cn38xxp2;
+        struct cvmx_pip_qos_watchx_s cn50xx;
+        struct cvmx_pip_qos_watchx_s cn52xx;
+        struct cvmx_pip_qos_watchx_s cn52xxp1;
+        struct cvmx_pip_qos_watchx_s cn56xx;
+        struct cvmx_pip_qos_watchx_s cn56xxp1;
+        struct cvmx_pip_qos_watchx_cn30xx cn58xx;
+        struct cvmx_pip_qos_watchx_cn30xx cn58xxp1;
+};
+
+union cvmx_pip_raw_word {
+        uint64_t u64;
+        struct cvmx_pip_raw_word_s {
+                uint64_t reserved_56_63:8;
+                uint64_t word:56;
+        } s;
+        struct cvmx_pip_raw_word_s cn30xx;
+        struct cvmx_pip_raw_word_s cn31xx;
+        struct cvmx_pip_raw_word_s cn38xx;
+        struct cvmx_pip_raw_word_s cn38xxp2;
+        struct cvmx_pip_raw_word_s cn50xx;
+        struct cvmx_pip_raw_word_s cn52xx;
+        struct cvmx_pip_raw_word_s cn52xxp1;
+        struct cvmx_pip_raw_word_s cn56xx;
+        struct cvmx_pip_raw_word_s cn56xxp1;
+        struct cvmx_pip_raw_word_s cn58xx;
+        struct cvmx_pip_raw_word_s cn58xxp1;
+};
+
+union cvmx_pip_sft_rst {
+        uint64_t u64;
+        struct cvmx_pip_sft_rst_s {
+                uint64_t reserved_1_63:63;
+                uint64_t rst:1;
+        } s;
+        struct cvmx_pip_sft_rst_s cn30xx;
+        struct cvmx_pip_sft_rst_s cn31xx;
+        struct cvmx_pip_sft_rst_s cn38xx;
+        struct cvmx_pip_sft_rst_s cn50xx;
+        struct cvmx_pip_sft_rst_s cn52xx;
+        struct cvmx_pip_sft_rst_s cn52xxp1;
+        struct cvmx_pip_sft_rst_s cn56xx;
+        struct cvmx_pip_sft_rst_s cn56xxp1;
+        struct cvmx_pip_sft_rst_s cn58xx;
+        struct cvmx_pip_sft_rst_s cn58xxp1;
+};
+
+union cvmx_pip_stat0_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat0_prtx_s {
+                uint64_t drp_pkts:32;
+                uint64_t drp_octs:32;
+        } s;
+        struct cvmx_pip_stat0_prtx_s cn30xx;
+        struct cvmx_pip_stat0_prtx_s cn31xx;
+        struct cvmx_pip_stat0_prtx_s cn38xx;
+        struct cvmx_pip_stat0_prtx_s cn38xxp2;
+        struct cvmx_pip_stat0_prtx_s cn50xx;
+        struct cvmx_pip_stat0_prtx_s cn52xx;
+        struct cvmx_pip_stat0_prtx_s cn52xxp1;
+        struct cvmx_pip_stat0_prtx_s cn56xx;
+        struct cvmx_pip_stat0_prtx_s cn56xxp1;
+        struct cvmx_pip_stat0_prtx_s cn58xx;
+        struct cvmx_pip_stat0_prtx_s cn58xxp1;
+};
+
+union cvmx_pip_stat1_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat1_prtx_s {
+                uint64_t reserved_48_63:16;
+                uint64_t octs:48;
+        } s;
+        struct cvmx_pip_stat1_prtx_s cn30xx;
+        struct cvmx_pip_stat1_prtx_s cn31xx;
+        struct cvmx_pip_stat1_prtx_s cn38xx;
+        struct cvmx_pip_stat1_prtx_s cn38xxp2;
+        struct cvmx_pip_stat1_prtx_s cn50xx;
+        struct cvmx_pip_stat1_prtx_s cn52xx;
+        struct cvmx_pip_stat1_prtx_s cn52xxp1;
+        struct cvmx_pip_stat1_prtx_s cn56xx;
+        struct cvmx_pip_stat1_prtx_s cn56xxp1;
+        struct cvmx_pip_stat1_prtx_s cn58xx;
+        struct cvmx_pip_stat1_prtx_s cn58xxp1;
+};
+
+union cvmx_pip_stat2_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat2_prtx_s {
+                uint64_t pkts:32;
+                uint64_t raw:32;
+        } s;
+        struct cvmx_pip_stat2_prtx_s cn30xx;
+        struct cvmx_pip_stat2_prtx_s cn31xx;
+        struct cvmx_pip_stat2_prtx_s cn38xx;
+        struct cvmx_pip_stat2_prtx_s cn38xxp2;
+        struct cvmx_pip_stat2_prtx_s cn50xx;
+        struct cvmx_pip_stat2_prtx_s cn52xx;
+        struct cvmx_pip_stat2_prtx_s cn52xxp1;
+        struct cvmx_pip_stat2_prtx_s cn56xx;
+        struct cvmx_pip_stat2_prtx_s cn56xxp1;
+        struct cvmx_pip_stat2_prtx_s cn58xx;
+        struct cvmx_pip_stat2_prtx_s cn58xxp1;
+};
+
+union cvmx_pip_stat3_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat3_prtx_s {
+                uint64_t bcst:32;
+                uint64_t mcst:32;
+        } s;
+        struct cvmx_pip_stat3_prtx_s cn30xx;
+        struct cvmx_pip_stat3_prtx_s cn31xx;
+        struct cvmx_pip_stat3_prtx_s cn38xx;
+        struct cvmx_pip_stat3_prtx_s cn38xxp2;
+        struct cvmx_pip_stat3_prtx_s cn50xx;
+        struct cvmx_pip_stat3_prtx_s cn52xx;
+        struct cvmx_pip_stat3_prtx_s cn52xxp1;
+        struct cvmx_pip_stat3_prtx_s cn56xx;
+        struct cvmx_pip_stat3_prtx_s cn56xxp1;
+        struct cvmx_pip_stat3_prtx_s cn58xx;
+        struct cvmx_pip_stat3_prtx_s cn58xxp1;
+};
+
+union cvmx_pip_stat4_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat4_prtx_s {
+                uint64_t h65to127:32;
+                uint64_t h64:32;
+        } s;
+        struct cvmx_pip_stat4_prtx_s cn30xx;
+        struct cvmx_pip_stat4_prtx_s cn31xx;
+        struct cvmx_pip_stat4_prtx_s cn38xx;
+        struct cvmx_pip_stat4_prtx_s cn38xxp2;
+        struct cvmx_pip_stat4_prtx_s cn50xx;
+        struct cvmx_pip_stat4_prtx_s cn52xx;
+        struct cvmx_pip_stat4_prtx_s cn52xxp1;
+        struct cvmx_pip_stat4_prtx_s cn56xx;
+        struct cvmx_pip_stat4_prtx_s cn56xxp1;
+        struct cvmx_pip_stat4_prtx_s cn58xx;
+        struct cvmx_pip_stat4_prtx_s cn58xxp1;
+};
+
+union cvmx_pip_stat5_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat5_prtx_s {
+                uint64_t h256to511:32;
+                uint64_t h128to255:32;
+        } s;
+        struct cvmx_pip_stat5_prtx_s cn30xx;
+        struct cvmx_pip_stat5_prtx_s cn31xx;
+        struct cvmx_pip_stat5_prtx_s cn38xx;
+        struct cvmx_pip_stat5_prtx_s cn38xxp2;
+        struct cvmx_pip_stat5_prtx_s cn50xx;
+        struct cvmx_pip_stat5_prtx_s cn52xx;
+        struct cvmx_pip_stat5_prtx_s cn52xxp1;
+        struct cvmx_pip_stat5_prtx_s cn56xx;
+        struct cvmx_pip_stat5_prtx_s cn56xxp1;
+        struct cvmx_pip_stat5_prtx_s cn58xx;
+        struct cvmx_pip_stat5_prtx_s cn58xxp1;
+};
+
+union cvmx_pip_stat6_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat6_prtx_s {
+                uint64_t h1024to1518:32;
+                uint64_t h512to1023:32;
+        } s;
+        struct cvmx_pip_stat6_prtx_s cn30xx;
+        struct cvmx_pip_stat6_prtx_s cn31xx;
+        struct cvmx_pip_stat6_prtx_s cn38xx;
+        struct cvmx_pip_stat6_prtx_s cn38xxp2;
+        struct cvmx_pip_stat6_prtx_s cn50xx;
+        struct cvmx_pip_stat6_prtx_s cn52xx;
+        struct cvmx_pip_stat6_prtx_s cn52xxp1;
+        struct cvmx_pip_stat6_prtx_s cn56xx;
+        struct cvmx_pip_stat6_prtx_s cn56xxp1;
+        struct cvmx_pip_stat6_prtx_s cn58xx;
+        struct cvmx_pip_stat6_prtx_s cn58xxp1;
+};
+
+union cvmx_pip_stat7_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat7_prtx_s {
+                uint64_t fcs:32;
+                uint64_t h1519:32;
+        } s;
+        struct cvmx_pip_stat7_prtx_s cn30xx;
+        struct cvmx_pip_stat7_prtx_s cn31xx;
+        struct cvmx_pip_stat7_prtx_s cn38xx;
+        struct cvmx_pip_stat7_prtx_s cn38xxp2;
+        struct cvmx_pip_stat7_prtx_s cn50xx;
+        struct cvmx_pip_stat7_prtx_s cn52xx;
+        struct cvmx_pip_stat7_prtx_s cn52xxp1;
+        struct cvmx_pip_stat7_prtx_s cn56xx;
+        struct cvmx_pip_stat7_prtx_s cn56xxp1;
+        struct cvmx_pip_stat7_prtx_s cn58xx;
+        struct cvmx_pip_stat7_prtx_s cn58xxp1;
+};
+
+union cvmx_pip_stat8_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat8_prtx_s {
+                uint64_t frag:32;
+                uint64_t undersz:32;
+        } s;
+        struct cvmx_pip_stat8_prtx_s cn30xx;
+        struct cvmx_pip_stat8_prtx_s cn31xx;
+        struct cvmx_pip_stat8_prtx_s cn38xx;
+        struct cvmx_pip_stat8_prtx_s cn38xxp2;
+        struct cvmx_pip_stat8_prtx_s cn50xx;
+        struct cvmx_pip_stat8_prtx_s cn52xx;
+        struct cvmx_pip_stat8_prtx_s cn52xxp1;
+        struct cvmx_pip_stat8_prtx_s cn56xx;
+        struct cvmx_pip_stat8_prtx_s cn56xxp1;
+        struct cvmx_pip_stat8_prtx_s cn58xx;
+        struct cvmx_pip_stat8_prtx_s cn58xxp1;
+};
+
+union cvmx_pip_stat9_prtx {
+        uint64_t u64;
+        struct cvmx_pip_stat9_prtx_s {
+                uint64_t jabber:32;
+                uint64_t oversz:32;
+        } s;
+        struct cvmx_pip_stat9_prtx_s cn30xx;
+        struct cvmx_pip_stat9_prtx_s cn31xx;
+        struct cvmx_pip_stat9_prtx_s cn38xx;
+        struct cvmx_pip_stat9_prtx_s cn38xxp2;
+        struct cvmx_pip_stat9_prtx_s cn50xx;
+        struct cvmx_pip_stat9_prtx_s cn52xx;
+        struct cvmx_pip_stat9_prtx_s cn52xxp1;
+        struct cvmx_pip_stat9_prtx_s cn56xx;
+        struct cvmx_pip_stat9_prtx_s cn56xxp1;
+        struct cvmx_pip_stat9_prtx_s cn58xx;
+        struct cvmx_pip_stat9_prtx_s cn58xxp1;
+};
+
+union cvmx_pip_stat_ctl {
+        uint64_t u64;
+        struct cvmx_pip_stat_ctl_s {
+                uint64_t reserved_1_63:63;
+                uint64_t rdclr:1;
+        } s;
+        struct cvmx_pip_stat_ctl_s cn30xx;
+        struct cvmx_pip_stat_ctl_s cn31xx;
+        struct cvmx_pip_stat_ctl_s cn38xx;
+        struct cvmx_pip_stat_ctl_s cn38xxp2;
+        struct cvmx_pip_stat_ctl_s cn50xx;
+        struct cvmx_pip_stat_ctl_s cn52xx;
+        struct cvmx_pip_stat_ctl_s cn52xxp1;
+        struct cvmx_pip_stat_ctl_s cn56xx;
+        struct cvmx_pip_stat_ctl_s cn56xxp1;
+        struct cvmx_pip_stat_ctl_s cn58xx;
+        struct cvmx_pip_stat_ctl_s cn58xxp1;
+};
+
+union cvmx_pip_stat_inb_errsx {
+        uint64_t u64;
+        struct cvmx_pip_stat_inb_errsx_s {
+                uint64_t reserved_16_63:48;
+                uint64_t errs:16;
+        } s;
+        struct cvmx_pip_stat_inb_errsx_s cn30xx;
+        struct cvmx_pip_stat_inb_errsx_s cn31xx;
+        struct cvmx_pip_stat_inb_errsx_s cn38xx;
+        struct cvmx_pip_stat_inb_errsx_s cn38xxp2;
+        struct cvmx_pip_stat_inb_errsx_s cn50xx;
+        struct cvmx_pip_stat_inb_errsx_s cn52xx;
+        struct cvmx_pip_stat_inb_errsx_s cn52xxp1;
+        struct cvmx_pip_stat_inb_errsx_s cn56xx;
+        struct cvmx_pip_stat_inb_errsx_s cn56xxp1;
+        struct cvmx_pip_stat_inb_errsx_s cn58xx;
+        struct cvmx_pip_stat_inb_errsx_s cn58xxp1;
+};
+
+union cvmx_pip_stat_inb_octsx {
+        uint64_t u64;
+        struct cvmx_pip_stat_inb_octsx_s {
+                uint64_t reserved_48_63:16;
+                uint64_t octs:48;
+        } s;
+        struct cvmx_pip_stat_inb_octsx_s cn30xx;
+        struct cvmx_pip_stat_inb_octsx_s cn31xx;
+        struct cvmx_pip_stat_inb_octsx_s cn38xx;
+        struct cvmx_pip_stat_inb_octsx_s cn38xxp2;
+        struct cvmx_pip_stat_inb_octsx_s cn50xx;
+        struct cvmx_pip_stat_inb_octsx_s cn52xx;
+        struct cvmx_pip_stat_inb_octsx_s cn52xxp1;
+        struct cvmx_pip_stat_inb_octsx_s cn56xx;
+        struct cvmx_pip_stat_inb_octsx_s cn56xxp1;
+        struct cvmx_pip_stat_inb_octsx_s cn58xx;
+        struct cvmx_pip_stat_inb_octsx_s cn58xxp1;
+};
+
+union cvmx_pip_stat_inb_pktsx {
+        uint64_t u64;
+        struct cvmx_pip_stat_inb_pktsx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t pkts:32;
+        } s;
+        struct cvmx_pip_stat_inb_pktsx_s cn30xx;
+        struct cvmx_pip_stat_inb_pktsx_s cn31xx;
+        struct cvmx_pip_stat_inb_pktsx_s cn38xx;
+        struct cvmx_pip_stat_inb_pktsx_s cn38xxp2;
+        struct cvmx_pip_stat_inb_pktsx_s cn50xx;
+        struct cvmx_pip_stat_inb_pktsx_s cn52xx;
+        struct cvmx_pip_stat_inb_pktsx_s cn52xxp1;
+        struct cvmx_pip_stat_inb_pktsx_s cn56xx;
+        struct cvmx_pip_stat_inb_pktsx_s cn56xxp1;
+        struct cvmx_pip_stat_inb_pktsx_s cn58xx;
+        struct cvmx_pip_stat_inb_pktsx_s cn58xxp1;
+};
+
+union cvmx_pip_tag_incx {
+        uint64_t u64;
+        struct cvmx_pip_tag_incx_s {
+                uint64_t reserved_8_63:56;
+                uint64_t en:8;
+        } s;
+        struct cvmx_pip_tag_incx_s cn30xx;
+        struct cvmx_pip_tag_incx_s cn31xx;
+        struct cvmx_pip_tag_incx_s cn38xx;
+        struct cvmx_pip_tag_incx_s cn38xxp2;
+        struct cvmx_pip_tag_incx_s cn50xx;
+        struct cvmx_pip_tag_incx_s cn52xx;
+        struct cvmx_pip_tag_incx_s cn52xxp1;
+        struct cvmx_pip_tag_incx_s cn56xx;
+        struct cvmx_pip_tag_incx_s cn56xxp1;
+        struct cvmx_pip_tag_incx_s cn58xx;
+        struct cvmx_pip_tag_incx_s cn58xxp1;
+};
+
+union cvmx_pip_tag_mask {
+        uint64_t u64;
+        struct cvmx_pip_tag_mask_s {
+                uint64_t reserved_16_63:48;
+                uint64_t mask:16;
+        } s;
+        struct cvmx_pip_tag_mask_s cn30xx;
+        struct cvmx_pip_tag_mask_s cn31xx;
+        struct cvmx_pip_tag_mask_s cn38xx;
+        struct cvmx_pip_tag_mask_s cn38xxp2;
+        struct cvmx_pip_tag_mask_s cn50xx;
+        struct cvmx_pip_tag_mask_s cn52xx;
+        struct cvmx_pip_tag_mask_s cn52xxp1;
+        struct cvmx_pip_tag_mask_s cn56xx;
+        struct cvmx_pip_tag_mask_s cn56xxp1;
+        struct cvmx_pip_tag_mask_s cn58xx;
+        struct cvmx_pip_tag_mask_s cn58xxp1;
+};
+
+union cvmx_pip_tag_secret {
+        uint64_t u64;
+        struct cvmx_pip_tag_secret_s {
+                uint64_t reserved_32_63:32;
+                uint64_t dst:16;
+                uint64_t src:16;
+        } s;
+        struct cvmx_pip_tag_secret_s cn30xx;
+        struct cvmx_pip_tag_secret_s cn31xx;
+        struct cvmx_pip_tag_secret_s cn38xx;
+        struct cvmx_pip_tag_secret_s cn38xxp2;
+        struct cvmx_pip_tag_secret_s cn50xx;
+        struct cvmx_pip_tag_secret_s cn52xx;
+        struct cvmx_pip_tag_secret_s cn52xxp1;
+        struct cvmx_pip_tag_secret_s cn56xx;
+        struct cvmx_pip_tag_secret_s cn56xxp1;
+        struct cvmx_pip_tag_secret_s cn58xx;
+        struct cvmx_pip_tag_secret_s cn58xxp1;
+};
+
+union cvmx_pip_todo_entry {
+        uint64_t u64;
+        struct cvmx_pip_todo_entry_s {
+                uint64_t val:1;
+                uint64_t reserved_62_62:1;
+                uint64_t entry:62;
+        } s;
+        struct cvmx_pip_todo_entry_s cn30xx;
+        struct cvmx_pip_todo_entry_s cn31xx;
+        struct cvmx_pip_todo_entry_s cn38xx;
+        struct cvmx_pip_todo_entry_s cn38xxp2;
+        struct cvmx_pip_todo_entry_s cn50xx;
+        struct cvmx_pip_todo_entry_s cn52xx;
+        struct cvmx_pip_todo_entry_s cn52xxp1;
+        struct cvmx_pip_todo_entry_s cn56xx;
+        struct cvmx_pip_todo_entry_s cn56xxp1;
+        struct cvmx_pip_todo_entry_s cn58xx;
+        struct cvmx_pip_todo_entry_s cn58xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-pip.h b/drivers/staging/octeon/cvmx-pip.h
new file mode 100644
index 000000000000..78dbce8f2c5e
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-pip.h
@@ -0,0 +1,524 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Interface to the hardware Packet Input Processing unit.
+ *
+ */
+
+#ifndef __CVMX_PIP_H__
+#define __CVMX_PIP_H__
+
+#include "cvmx-wqe.h"
+#include "cvmx-fpa.h"
+#include "cvmx-pip-defs.h"
+
+#define CVMX_PIP_NUM_INPUT_PORTS                40
+#define CVMX_PIP_NUM_WATCHERS                   4
+
+/*
+ * Encodes the different error and exception codes
+ */
+typedef enum {
+        CVMX_PIP_L4_NO_ERR = 0ull,
+        /*
+         * 1 = TCP (UDP) packet not long enough to cover TCP (UDP)
+         * header
+         */
+        CVMX_PIP_L4_MAL_ERR = 1ull,
+        /* 2  = TCP/UDP checksum failure */
+        CVMX_PIP_CHK_ERR = 2ull,
+        /*
+         * 3 = TCP/UDP length check (TCP/UDP length does not match IP
+         * length).
+         */
+        CVMX_PIP_L4_LENGTH_ERR = 3ull,
+        /* 4  = illegal TCP/UDP port (either source or dest port is zero) */
+        CVMX_PIP_BAD_PRT_ERR = 4ull,
+        /* 8  = TCP flags = FIN only */
+        CVMX_PIP_TCP_FLG8_ERR = 8ull,
+        /* 9  = TCP flags = 0 */
+        CVMX_PIP_TCP_FLG9_ERR = 9ull,
+        /* 10 = TCP flags = FIN+RST+* */
+        CVMX_PIP_TCP_FLG10_ERR = 10ull,
+        /* 11 = TCP flags = SYN+URG+* */
+        CVMX_PIP_TCP_FLG11_ERR = 11ull,
+        /* 12 = TCP flags = SYN+RST+* */
+        CVMX_PIP_TCP_FLG12_ERR = 12ull,
+        /* 13 = TCP flags = SYN+FIN+* */
+        CVMX_PIP_TCP_FLG13_ERR = 13ull
+} cvmx_pip_l4_err_t;
+
+typedef enum {
+
+        CVMX_PIP_IP_NO_ERR = 0ull,
+        /* 1 = not IPv4 or IPv6 */
+        CVMX_PIP_NOT_IP = 1ull,
+        /* 2 = IPv4 header checksum violation */
+        CVMX_PIP_IPV4_HDR_CHK = 2ull,
+        /* 3 = malformed (packet not long enough to cover IP hdr) */
+        CVMX_PIP_IP_MAL_HDR = 3ull,
+        /* 4 = malformed (packet not long enough to cover len in IP hdr) */
+        CVMX_PIP_IP_MAL_PKT = 4ull,
+        /* 5 = TTL / hop count equal zero */
+        CVMX_PIP_TTL_HOP = 5ull,
+        /* 6 = IPv4 options / IPv6 early extension headers */
+        CVMX_PIP_OPTS = 6ull
+} cvmx_pip_ip_exc_t;
+
+/**
+ * NOTES
+ *       late collision (data received before collision)
+ *            late collisions cannot be detected by the receiver
+ *            they would appear as JAM bits which would appear as bad FCS
+ *            or carrier extend error which is CVMX_PIP_EXTEND_ERR
+ */
+typedef enum {
+        /* No error */
+        CVMX_PIP_RX_NO_ERR = 0ull,
+        /* RGM+SPI 1 = partially received packet (buffering/bandwidth
+         * not adequate) */
+        CVMX_PIP_PARTIAL_ERR = 1ull,
+        /* RGM+SPI 2 = receive packet too large and truncated */
+        CVMX_PIP_JABBER_ERR = 2ull,
+        /*
+         * RGM 3 = max frame error (pkt len > max frame len) (with FCS
+         * error)
+         */
+        CVMX_PIP_OVER_FCS_ERR = 3ull,
+        /* RGM+SPI 4 = max frame error (pkt len > max frame len) */
+        CVMX_PIP_OVER_ERR = 4ull,
+        /*
+         * RGM 5 = nibble error (data not byte multiple - 100M and 10M
+         * only)
+         */
+        CVMX_PIP_ALIGN_ERR = 5ull,
+        /*
+         * RGM 6 = min frame error (pkt len < min frame len) (with FCS
+         * error)
+         */
+        CVMX_PIP_UNDER_FCS_ERR = 6ull,
+        /* RGM     7 = FCS error */
+        CVMX_PIP_GMX_FCS_ERR = 7ull,
+        /* RGM+SPI 8 = min frame error (pkt len < min frame len) */
+        CVMX_PIP_UNDER_ERR = 8ull,
+        /* RGM     9 = Frame carrier extend error */
+        CVMX_PIP_EXTEND_ERR = 9ull,
+        /*
+         * RGM 10 = length mismatch (len did not match len in L2
+         * length/type)
+         */
+        CVMX_PIP_LENGTH_ERR = 10ull,
+        /* RGM 11 = Frame error (some or all data bits marked err) */
+        CVMX_PIP_DAT_ERR = 11ull,
+        /*     SPI 11 = DIP4 error */
+        CVMX_PIP_DIP_ERR = 11ull,
+        /*
+         * RGM 12 = packet was not large enough to pass the skipper -
+         * no inspection could occur.
+         */
+        CVMX_PIP_SKIP_ERR = 12ull,
+        /*
+         * RGM 13 = studder error (data not repeated - 100M and 10M
+         * only)
+         */
+        CVMX_PIP_NIBBLE_ERR = 13ull,
+        /* RGM+SPI 16 = FCS error */
+        CVMX_PIP_PIP_FCS = 16L,
+        /*
+         * RGM+SPI+PCI 17 = packet was not large enough to pass the
+         * skipper - no inspection could occur.
+         */
+        CVMX_PIP_PIP_SKIP_ERR = 17L,
+        /*
+         * RGM+SPI+PCI 18 = malformed l2 (packet not long enough to
+         * cover L2 hdr).
+         */
+        CVMX_PIP_PIP_L2_MAL_HDR = 18L
+        /*
+         * NOTES: xx = late collision (data received before collision)
+         *       late collisions cannot be detected by the receiver
+         *       they would appear as JAM bits which would appear as
+         *       bad FCS or carrier extend error which is
+         *       CVMX_PIP_EXTEND_ERR
+         */
+} cvmx_pip_rcv_err_t;
+
+/**
+ * This defines the err_code field errors in the work Q entry
+ */
+typedef union {
+        cvmx_pip_l4_err_t l4_err;
+        cvmx_pip_ip_exc_t ip_exc;
+        cvmx_pip_rcv_err_t rcv_err;
+} cvmx_pip_err_t;
+
+/**
+ * Status statistics for a port
+ */
+typedef struct {
+        /* Inbound octets marked to be dropped by the IPD */
+        uint32_t dropped_octets;
+        /* Inbound packets marked to be dropped by the IPD */
+        uint32_t dropped_packets;
+        /* RAW PCI Packets received by PIP per port */
+        uint32_t pci_raw_packets;
+        /* Number of octets processed by PIP */
+        uint32_t octets;
+        /* Number of packets processed by PIP */
+        uint32_t packets;
+        /*
+         * Number of indentified L2 multicast packets.  Does not
+         * include broadcast packets.  Only includes packets whose
+         * parse mode is SKIP_TO_L2
+         */
+        uint32_t multicast_packets;
+        /*
+         * Number of indentified L2 broadcast packets.  Does not
+         * include multicast packets.  Only includes packets whose
+         * parse mode is SKIP_TO_L2
+         */
+        uint32_t broadcast_packets;
+        /* Number of 64B packets */
+        uint32_t len_64_packets;
+        /* Number of 65-127B packets */
+        uint32_t len_65_127_packets;
+        /* Number of 128-255B packets */
+        uint32_t len_128_255_packets;
+        /* Number of 256-511B packets */
+        uint32_t len_256_511_packets;
+        /* Number of 512-1023B packets */
+        uint32_t len_512_1023_packets;
+        /* Number of 1024-1518B packets */
+        uint32_t len_1024_1518_packets;
+        /* Number of 1519-max packets */
+        uint32_t len_1519_max_packets;
+        /* Number of packets with FCS or Align opcode errors */
+        uint32_t fcs_align_err_packets;
+        /* Number of packets with length < min */
+        uint32_t runt_packets;
+        /* Number of packets with length < min and FCS error */
+        uint32_t runt_crc_packets;
+        /* Number of packets with length > max */
+        uint32_t oversize_packets;
+        /* Number of packets with length > max and FCS error */
+        uint32_t oversize_crc_packets;
+        /* Number of packets without GMX/SPX/PCI errors received by PIP */
+        uint32_t inb_packets;
+        /*
+         * Total number of octets from all packets received by PIP,
+         * including CRC
+         */
+        uint64_t inb_octets;
+        /* Number of packets with GMX/SPX/PCI errors received by PIP */
+        uint16_t inb_errors;
+} cvmx_pip_port_status_t;
+
+/**
+ * Definition of the PIP custom header that can be prepended
+ * to a packet by external hardware.
+ */
+typedef union {
+        uint64_t u64;
+        struct {
+                /*
+                 * Documented as R - Set if the Packet is RAWFULL. If
+                 * set, this header must be the full 8 bytes.
+                 */
+                uint64_t rawfull:1;
+                /* Must be zero */
+                uint64_t reserved0:5;
+                /* PIP parse mode for this packet */
+                uint64_t parse_mode:2;
+                /* Must be zero */
+                uint64_t reserved1:1;
+                /*
+                 * Skip amount, including this header, to the
+                 * beginning of the packet
+                 */
+                uint64_t skip_len:7;
+                /* Must be zero */
+                uint64_t reserved2:6;
+                /* POW input queue for this packet */
+                uint64_t qos:3;
+                /* POW input group for this packet */
+                uint64_t grp:4;
+                /*
+                 * Flag to store this packet in the work queue entry,
+                 * if possible
+                 */
+                uint64_t rs:1;
+                /* POW input tag type */
+                uint64_t tag_type:2;
+                /* POW input tag */
+                uint64_t tag:32;
+        } s;
+} cvmx_pip_pkt_inst_hdr_t;
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Configure an ethernet input port
+ *
+ * @port_num: Port number to configure
+ * @port_cfg: Port hardware configuration
+ * @port_tag_cfg:
+ *                 Port POW tagging configuration
+ */
+static inline void cvmx_pip_config_port(uint64_t port_num,
+                                        union cvmx_pip_prt_cfgx port_cfg,
+                                        union cvmx_pip_prt_tagx port_tag_cfg)
+{
+        cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
+        cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
+}
+#if 0
+/**
+ * @deprecated      This function is a thin wrapper around the Pass1 version
+ *                  of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
+ *                  setting the group that is incompatible with this function,
+ *                  the preferred upgrade path is to use the CSR directly.
+ *
+ * Configure the global QoS packet watchers. Each watcher is
+ * capable of matching a field in a packet to determine the
+ * QoS queue for scheduling.
+ *
+ * @watcher:    Watcher number to configure (0 - 3).
+ * @match_type: Watcher match type
+ * @match_value:
+ *                   Value the watcher will match against
+ * @qos:        QoS queue for packets matching this watcher
+ */
+static inline void cvmx_pip_config_watcher(uint64_t watcher,
+                                           cvmx_pip_qos_watch_types match_type,
+                                           uint64_t match_value, uint64_t qos)
+{
+        cvmx_pip_port_watcher_cfg_t watcher_config;
+
+        watcher_config.u64 = 0;
+        watcher_config.s.match_type = match_type;
+        watcher_config.s.match_value = match_value;
+        watcher_config.s.qos = qos;
+
+        cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
+}
+#endif
+/**
+ * Configure the VLAN priority to QoS queue mapping.
+ *
+ * @vlan_priority:
+ *               VLAN priority (0-7)
+ * @qos:    QoS queue for packets matching this watcher
+ */
+static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority,
+                                            uint64_t qos)
+{
+        union cvmx_pip_qos_vlanx pip_qos_vlanx;
+        pip_qos_vlanx.u64 = 0;
+        pip_qos_vlanx.s.qos = qos;
+        cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
+}
+
+/**
+ * Configure the Diffserv to QoS queue mapping.
+ *
+ * @diffserv: Diffserv field value (0-63)
+ * @qos:      QoS queue for packets matching this watcher
+ */
+static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
+{
+        union cvmx_pip_qos_diffx pip_qos_diffx;
+        pip_qos_diffx.u64 = 0;
+        pip_qos_diffx.s.qos = qos;
+        cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
+}
+
+/**
+ * Get the status counters for a port.
+ *
+ * @port_num: Port number to get statistics for.
+ * @clear:    Set to 1 to clear the counters after they are read
+ * @status:   Where to put the results.
+ */
+static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
+                                            cvmx_pip_port_status_t *status)
+{
+        union cvmx_pip_stat_ctl pip_stat_ctl;
+        union cvmx_pip_stat0_prtx stat0;
+        union cvmx_pip_stat1_prtx stat1;
+        union cvmx_pip_stat2_prtx stat2;
+        union cvmx_pip_stat3_prtx stat3;
+        union cvmx_pip_stat4_prtx stat4;
+        union cvmx_pip_stat5_prtx stat5;
+        union cvmx_pip_stat6_prtx stat6;
+        union cvmx_pip_stat7_prtx stat7;
+        union cvmx_pip_stat8_prtx stat8;
+        union cvmx_pip_stat9_prtx stat9;
+        union cvmx_pip_stat_inb_pktsx pip_stat_inb_pktsx;
+        union cvmx_pip_stat_inb_octsx pip_stat_inb_octsx;
+        union cvmx_pip_stat_inb_errsx pip_stat_inb_errsx;
+
+        pip_stat_ctl.u64 = 0;
+        pip_stat_ctl.s.rdclr = clear;
+        cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
+
+        stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
+        stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
+        stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
+        stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
+        stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
+        stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
+        stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
+        stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
+        stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
+        stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
+        pip_stat_inb_pktsx.u64 =
+            cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
+        pip_stat_inb_octsx.u64 =
+            cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
+        pip_stat_inb_errsx.u64 =
+            cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
+
+        status->dropped_octets = stat0.s.drp_octs;
+        status->dropped_packets = stat0.s.drp_pkts;
+        status->octets = stat1.s.octs;
+        status->pci_raw_packets = stat2.s.raw;
+        status->packets = stat2.s.pkts;
+        status->multicast_packets = stat3.s.mcst;
+        status->broadcast_packets = stat3.s.bcst;
+        status->len_64_packets = stat4.s.h64;
+        status->len_65_127_packets = stat4.s.h65to127;
+        status->len_128_255_packets = stat5.s.h128to255;
+        status->len_256_511_packets = stat5.s.h256to511;
+        status->len_512_1023_packets = stat6.s.h512to1023;
+        status->len_1024_1518_packets = stat6.s.h1024to1518;
+        status->len_1519_max_packets = stat7.s.h1519;
+        status->fcs_align_err_packets = stat7.s.fcs;
+        status->runt_packets = stat8.s.undersz;
+        status->runt_crc_packets = stat8.s.frag;
+        status->oversize_packets = stat9.s.oversz;
+        status->oversize_crc_packets = stat9.s.jabber;
+        status->inb_packets = pip_stat_inb_pktsx.s.pkts;
+        status->inb_octets = pip_stat_inb_octsx.s.octs;
+        status->inb_errors = pip_stat_inb_errsx.s.errs;
+
+        if (cvmx_octeon_is_pass1()) {
+                /*
+                 * Kludge to fix Octeon Pass 1 errata - Drop counts
+                 * don't work.
+                 */
+                if (status->inb_packets > status->packets)
+                        status->dropped_packets =
+                            status->inb_packets - status->packets;
+                else
+                        status->dropped_packets = 0;
+                if (status->inb_octets - status->inb_packets * 4 >
+                    status->octets)
+                        status->dropped_octets =
+                            status->inb_octets - status->inb_packets * 4 -
+                            status->octets;
+                else
+                        status->dropped_octets = 0;
+        }
+}
+
+/**
+ * Configure the hardware CRC engine
+ *
+ * @interface: Interface to configure (0 or 1)
+ * @invert_result:
+ *                 Invert the result of the CRC
+ * @reflect:  Reflect
+ * @initialization_vector:
+ *                 CRC initialization vector
+ */
+static inline void cvmx_pip_config_crc(uint64_t interface,
+                                       uint64_t invert_result, uint64_t reflect,
+                                       uint32_t initialization_vector)
+{
+        if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
+                union cvmx_pip_crc_ctlx config;
+                union cvmx_pip_crc_ivx pip_crc_ivx;
+
+                config.u64 = 0;
+                config.s.invres = invert_result;
+                config.s.reflect = reflect;
+                cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);
+
+                pip_crc_ivx.u64 = 0;
+                pip_crc_ivx.s.iv = initialization_vector;
+                cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);
+        }
+}
+
+/**
+ * Clear all bits in a tag mask. This should be called on
+ * startup before any calls to cvmx_pip_tag_mask_set. Each bit
+ * set in the final mask represent a byte used in the packet for
+ * tag generation.
+ *
+ * @mask_index: Which tag mask to clear (0..3)
+ */
+static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
+{
+        uint64_t index;
+        union cvmx_pip_tag_incx pip_tag_incx;
+        pip_tag_incx.u64 = 0;
+        pip_tag_incx.s.en = 0;
+        for (index = mask_index * 16; index < (mask_index + 1) * 16; index++)
+                cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
+}
+
+/**
+ * Sets a range of bits in the tag mask. The tag mask is used
+ * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
+ * There are four separate masks that can be configured.
+ *
+ * @mask_index: Which tag mask to modify (0..3)
+ * @offset: Offset into the bitmask to set bits at. Use the GCC macro
+ *          offsetof() to determine the offsets into packet headers.
+ *          For example, offsetof(ethhdr, protocol) returns the offset
+ *          of the ethernet protocol field.  The bitmask selects which
+ *          bytes to include the the tag, with bit offset X selecting
+ *          byte at offset X from the beginning of the packet data.
+ * @len:    Number of bytes to include. Usually this is the sizeof()
+ *          the field.
+ */
+static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset,
+                                         uint64_t len)
+{
+        while (len--) {
+                union cvmx_pip_tag_incx pip_tag_incx;
+                uint64_t index = mask_index * 16 + offset / 8;
+                pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));
+                pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
+                cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
+                offset++;
+        }
+}
+
+#endif /*  __CVMX_PIP_H__ */
diff --git a/drivers/staging/octeon/cvmx-pko-defs.h b/drivers/staging/octeon/cvmx-pko-defs.h
new file mode 100644
index 000000000000..50e779cf1ad8
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-pko-defs.h
@@ -0,0 +1,1133 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PKO_DEFS_H__
+#define __CVMX_PKO_DEFS_H__
+
+#define CVMX_PKO_MEM_COUNT0 \
+         CVMX_ADD_IO_SEG(0x0001180050001080ull)
+#define CVMX_PKO_MEM_COUNT1 \
+         CVMX_ADD_IO_SEG(0x0001180050001088ull)
+#define CVMX_PKO_MEM_DEBUG0 \
+         CVMX_ADD_IO_SEG(0x0001180050001100ull)
+#define CVMX_PKO_MEM_DEBUG1 \
+         CVMX_ADD_IO_SEG(0x0001180050001108ull)
+#define CVMX_PKO_MEM_DEBUG10 \
+         CVMX_ADD_IO_SEG(0x0001180050001150ull)
+#define CVMX_PKO_MEM_DEBUG11 \
+         CVMX_ADD_IO_SEG(0x0001180050001158ull)
+#define CVMX_PKO_MEM_DEBUG12 \
+         CVMX_ADD_IO_SEG(0x0001180050001160ull)
+#define CVMX_PKO_MEM_DEBUG13 \
+         CVMX_ADD_IO_SEG(0x0001180050001168ull)
+#define CVMX_PKO_MEM_DEBUG14 \
+         CVMX_ADD_IO_SEG(0x0001180050001170ull)
+#define CVMX_PKO_MEM_DEBUG2 \
+         CVMX_ADD_IO_SEG(0x0001180050001110ull)
+#define CVMX_PKO_MEM_DEBUG3 \
+         CVMX_ADD_IO_SEG(0x0001180050001118ull)
+#define CVMX_PKO_MEM_DEBUG4 \
+         CVMX_ADD_IO_SEG(0x0001180050001120ull)
+#define CVMX_PKO_MEM_DEBUG5 \
+         CVMX_ADD_IO_SEG(0x0001180050001128ull)
+#define CVMX_PKO_MEM_DEBUG6 \
+         CVMX_ADD_IO_SEG(0x0001180050001130ull)
+#define CVMX_PKO_MEM_DEBUG7 \
+         CVMX_ADD_IO_SEG(0x0001180050001138ull)
+#define CVMX_PKO_MEM_DEBUG8 \
+         CVMX_ADD_IO_SEG(0x0001180050001140ull)
+#define CVMX_PKO_MEM_DEBUG9 \
+         CVMX_ADD_IO_SEG(0x0001180050001148ull)
+#define CVMX_PKO_MEM_PORT_PTRS \
+         CVMX_ADD_IO_SEG(0x0001180050001010ull)
+#define CVMX_PKO_MEM_PORT_QOS \
+         CVMX_ADD_IO_SEG(0x0001180050001018ull)
+#define CVMX_PKO_MEM_PORT_RATE0 \
+         CVMX_ADD_IO_SEG(0x0001180050001020ull)
+#define CVMX_PKO_MEM_PORT_RATE1 \
+         CVMX_ADD_IO_SEG(0x0001180050001028ull)
+#define CVMX_PKO_MEM_QUEUE_PTRS \
+         CVMX_ADD_IO_SEG(0x0001180050001000ull)
+#define CVMX_PKO_MEM_QUEUE_QOS \
+         CVMX_ADD_IO_SEG(0x0001180050001008ull)
+#define CVMX_PKO_REG_BIST_RESULT \
+         CVMX_ADD_IO_SEG(0x0001180050000080ull)
+#define CVMX_PKO_REG_CMD_BUF \
+         CVMX_ADD_IO_SEG(0x0001180050000010ull)
+#define CVMX_PKO_REG_CRC_CTLX(offset) \
+         CVMX_ADD_IO_SEG(0x0001180050000028ull + (((offset) & 1) * 8))
+#define CVMX_PKO_REG_CRC_ENABLE \
+         CVMX_ADD_IO_SEG(0x0001180050000020ull)
+#define CVMX_PKO_REG_CRC_IVX(offset) \
+         CVMX_ADD_IO_SEG(0x0001180050000038ull + (((offset) & 1) * 8))
+#define CVMX_PKO_REG_DEBUG0 \
+         CVMX_ADD_IO_SEG(0x0001180050000098ull)
+#define CVMX_PKO_REG_DEBUG1 \
+         CVMX_ADD_IO_SEG(0x00011800500000A0ull)
+#define CVMX_PKO_REG_DEBUG2 \
+         CVMX_ADD_IO_SEG(0x00011800500000A8ull)
+#define CVMX_PKO_REG_DEBUG3 \
+         CVMX_ADD_IO_SEG(0x00011800500000B0ull)
+#define CVMX_PKO_REG_ENGINE_INFLIGHT \
+         CVMX_ADD_IO_SEG(0x0001180050000050ull)
+#define CVMX_PKO_REG_ENGINE_THRESH \
+         CVMX_ADD_IO_SEG(0x0001180050000058ull)
+#define CVMX_PKO_REG_ERROR \
+         CVMX_ADD_IO_SEG(0x0001180050000088ull)
+#define CVMX_PKO_REG_FLAGS \
+         CVMX_ADD_IO_SEG(0x0001180050000000ull)
+#define CVMX_PKO_REG_GMX_PORT_MODE \
+         CVMX_ADD_IO_SEG(0x0001180050000018ull)
+#define CVMX_PKO_REG_INT_MASK \
+         CVMX_ADD_IO_SEG(0x0001180050000090ull)
+#define CVMX_PKO_REG_QUEUE_MODE \
+         CVMX_ADD_IO_SEG(0x0001180050000048ull)
+#define CVMX_PKO_REG_QUEUE_PTRS1 \
+         CVMX_ADD_IO_SEG(0x0001180050000100ull)
+#define CVMX_PKO_REG_READ_IDX \
+         CVMX_ADD_IO_SEG(0x0001180050000008ull)
+
+union cvmx_pko_mem_count0 {
+        uint64_t u64;
+        struct cvmx_pko_mem_count0_s {
+                uint64_t reserved_32_63:32;
+                uint64_t count:32;
+        } s;
+        struct cvmx_pko_mem_count0_s cn30xx;
+        struct cvmx_pko_mem_count0_s cn31xx;
+        struct cvmx_pko_mem_count0_s cn38xx;
+        struct cvmx_pko_mem_count0_s cn38xxp2;
+        struct cvmx_pko_mem_count0_s cn50xx;
+        struct cvmx_pko_mem_count0_s cn52xx;
+        struct cvmx_pko_mem_count0_s cn52xxp1;
+        struct cvmx_pko_mem_count0_s cn56xx;
+        struct cvmx_pko_mem_count0_s cn56xxp1;
+        struct cvmx_pko_mem_count0_s cn58xx;
+        struct cvmx_pko_mem_count0_s cn58xxp1;
+};
+
+union cvmx_pko_mem_count1 {
+        uint64_t u64;
+        struct cvmx_pko_mem_count1_s {
+                uint64_t reserved_48_63:16;
+                uint64_t count:48;
+        } s;
+        struct cvmx_pko_mem_count1_s cn30xx;
+        struct cvmx_pko_mem_count1_s cn31xx;
+        struct cvmx_pko_mem_count1_s cn38xx;
+        struct cvmx_pko_mem_count1_s cn38xxp2;
+        struct cvmx_pko_mem_count1_s cn50xx;
+        struct cvmx_pko_mem_count1_s cn52xx;
+        struct cvmx_pko_mem_count1_s cn52xxp1;
+        struct cvmx_pko_mem_count1_s cn56xx;
+        struct cvmx_pko_mem_count1_s cn56xxp1;
+        struct cvmx_pko_mem_count1_s cn58xx;
+        struct cvmx_pko_mem_count1_s cn58xxp1;
+};
+
+union cvmx_pko_mem_debug0 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug0_s {
+                uint64_t fau:28;
+                uint64_t cmd:14;
+                uint64_t segs:6;
+                uint64_t size:16;
+        } s;
+        struct cvmx_pko_mem_debug0_s cn30xx;
+        struct cvmx_pko_mem_debug0_s cn31xx;
+        struct cvmx_pko_mem_debug0_s cn38xx;
+        struct cvmx_pko_mem_debug0_s cn38xxp2;
+        struct cvmx_pko_mem_debug0_s cn50xx;
+        struct cvmx_pko_mem_debug0_s cn52xx;
+        struct cvmx_pko_mem_debug0_s cn52xxp1;
+        struct cvmx_pko_mem_debug0_s cn56xx;
+        struct cvmx_pko_mem_debug0_s cn56xxp1;
+        struct cvmx_pko_mem_debug0_s cn58xx;
+        struct cvmx_pko_mem_debug0_s cn58xxp1;
+};
+
+union cvmx_pko_mem_debug1 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug1_s {
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t ptr:40;
+        } s;
+        struct cvmx_pko_mem_debug1_s cn30xx;
+        struct cvmx_pko_mem_debug1_s cn31xx;
+        struct cvmx_pko_mem_debug1_s cn38xx;
+        struct cvmx_pko_mem_debug1_s cn38xxp2;
+        struct cvmx_pko_mem_debug1_s cn50xx;
+        struct cvmx_pko_mem_debug1_s cn52xx;
+        struct cvmx_pko_mem_debug1_s cn52xxp1;
+        struct cvmx_pko_mem_debug1_s cn56xx;
+        struct cvmx_pko_mem_debug1_s cn56xxp1;
+        struct cvmx_pko_mem_debug1_s cn58xx;
+        struct cvmx_pko_mem_debug1_s cn58xxp1;
+};
+
+union cvmx_pko_mem_debug10 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug10_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_pko_mem_debug10_cn30xx {
+                uint64_t fau:28;
+                uint64_t cmd:14;
+                uint64_t segs:6;
+                uint64_t size:16;
+        } cn30xx;
+        struct cvmx_pko_mem_debug10_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug10_cn30xx cn38xx;
+        struct cvmx_pko_mem_debug10_cn30xx cn38xxp2;
+        struct cvmx_pko_mem_debug10_cn50xx {
+                uint64_t reserved_49_63:15;
+                uint64_t ptrs1:17;
+                uint64_t reserved_17_31:15;
+                uint64_t ptrs2:17;
+        } cn50xx;
+        struct cvmx_pko_mem_debug10_cn50xx cn52xx;
+        struct cvmx_pko_mem_debug10_cn50xx cn52xxp1;
+        struct cvmx_pko_mem_debug10_cn50xx cn56xx;
+        struct cvmx_pko_mem_debug10_cn50xx cn56xxp1;
+        struct cvmx_pko_mem_debug10_cn50xx cn58xx;
+        struct cvmx_pko_mem_debug10_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_mem_debug11 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug11_s {
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t reserved_0_39:40;
+        } s;
+        struct cvmx_pko_mem_debug11_cn30xx {
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t ptr:40;
+        } cn30xx;
+        struct cvmx_pko_mem_debug11_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug11_cn30xx cn38xx;
+        struct cvmx_pko_mem_debug11_cn30xx cn38xxp2;
+        struct cvmx_pko_mem_debug11_cn50xx {
+                uint64_t reserved_23_63:41;
+                uint64_t maj:1;
+                uint64_t uid:3;
+                uint64_t sop:1;
+                uint64_t len:1;
+                uint64_t chk:1;
+                uint64_t cnt:13;
+                uint64_t mod:3;
+        } cn50xx;
+        struct cvmx_pko_mem_debug11_cn50xx cn52xx;
+        struct cvmx_pko_mem_debug11_cn50xx cn52xxp1;
+        struct cvmx_pko_mem_debug11_cn50xx cn56xx;
+        struct cvmx_pko_mem_debug11_cn50xx cn56xxp1;
+        struct cvmx_pko_mem_debug11_cn50xx cn58xx;
+        struct cvmx_pko_mem_debug11_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_mem_debug12 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug12_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_pko_mem_debug12_cn30xx {
+                uint64_t data:64;
+        } cn30xx;
+        struct cvmx_pko_mem_debug12_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug12_cn30xx cn38xx;
+        struct cvmx_pko_mem_debug12_cn30xx cn38xxp2;
+        struct cvmx_pko_mem_debug12_cn50xx {
+                uint64_t fau:28;
+                uint64_t cmd:14;
+                uint64_t segs:6;
+                uint64_t size:16;
+        } cn50xx;
+        struct cvmx_pko_mem_debug12_cn50xx cn52xx;
+        struct cvmx_pko_mem_debug12_cn50xx cn52xxp1;
+        struct cvmx_pko_mem_debug12_cn50xx cn56xx;
+        struct cvmx_pko_mem_debug12_cn50xx cn56xxp1;
+        struct cvmx_pko_mem_debug12_cn50xx cn58xx;
+        struct cvmx_pko_mem_debug12_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_mem_debug13 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug13_s {
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t reserved_0_55:56;
+        } s;
+        struct cvmx_pko_mem_debug13_cn30xx {
+                uint64_t reserved_51_63:13;
+                uint64_t widx:17;
+                uint64_t ridx2:17;
+                uint64_t widx2:17;
+        } cn30xx;
+        struct cvmx_pko_mem_debug13_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug13_cn30xx cn38xx;
+        struct cvmx_pko_mem_debug13_cn30xx cn38xxp2;
+        struct cvmx_pko_mem_debug13_cn50xx {
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t ptr:40;
+        } cn50xx;
+        struct cvmx_pko_mem_debug13_cn50xx cn52xx;
+        struct cvmx_pko_mem_debug13_cn50xx cn52xxp1;
+        struct cvmx_pko_mem_debug13_cn50xx cn56xx;
+        struct cvmx_pko_mem_debug13_cn50xx cn56xxp1;
+        struct cvmx_pko_mem_debug13_cn50xx cn58xx;
+        struct cvmx_pko_mem_debug13_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_mem_debug14 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug14_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_pko_mem_debug14_cn30xx {
+                uint64_t reserved_17_63:47;
+                uint64_t ridx:17;
+        } cn30xx;
+        struct cvmx_pko_mem_debug14_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug14_cn30xx cn38xx;
+        struct cvmx_pko_mem_debug14_cn30xx cn38xxp2;
+        struct cvmx_pko_mem_debug14_cn52xx {
+                uint64_t data:64;
+        } cn52xx;
+        struct cvmx_pko_mem_debug14_cn52xx cn52xxp1;
+        struct cvmx_pko_mem_debug14_cn52xx cn56xx;
+        struct cvmx_pko_mem_debug14_cn52xx cn56xxp1;
+};
+
+union cvmx_pko_mem_debug2 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug2_s {
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t ptr:40;
+        } s;
+        struct cvmx_pko_mem_debug2_s cn30xx;
+        struct cvmx_pko_mem_debug2_s cn31xx;
+        struct cvmx_pko_mem_debug2_s cn38xx;
+        struct cvmx_pko_mem_debug2_s cn38xxp2;
+        struct cvmx_pko_mem_debug2_s cn50xx;
+        struct cvmx_pko_mem_debug2_s cn52xx;
+        struct cvmx_pko_mem_debug2_s cn52xxp1;
+        struct cvmx_pko_mem_debug2_s cn56xx;
+        struct cvmx_pko_mem_debug2_s cn56xxp1;
+        struct cvmx_pko_mem_debug2_s cn58xx;
+        struct cvmx_pko_mem_debug2_s cn58xxp1;
+};
+
+union cvmx_pko_mem_debug3 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug3_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_pko_mem_debug3_cn30xx {
+                uint64_t i:1;
+                uint64_t back:4;
+                uint64_t pool:3;
+                uint64_t size:16;
+                uint64_t ptr:40;
+        } cn30xx;
+        struct cvmx_pko_mem_debug3_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug3_cn30xx cn38xx;
+        struct cvmx_pko_mem_debug3_cn30xx cn38xxp2;
+        struct cvmx_pko_mem_debug3_cn50xx {
+                uint64_t data:64;
+        } cn50xx;
+        struct cvmx_pko_mem_debug3_cn50xx cn52xx;
+        struct cvmx_pko_mem_debug3_cn50xx cn52xxp1;
+        struct cvmx_pko_mem_debug3_cn50xx cn56xx;
+        struct cvmx_pko_mem_debug3_cn50xx cn56xxp1;
+        struct cvmx_pko_mem_debug3_cn50xx cn58xx;
+        struct cvmx_pko_mem_debug3_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_mem_debug4 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug4_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_pko_mem_debug4_cn30xx {
+                uint64_t data:64;
+        } cn30xx;
+        struct cvmx_pko_mem_debug4_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug4_cn30xx cn38xx;
+        struct cvmx_pko_mem_debug4_cn30xx cn38xxp2;
+        struct cvmx_pko_mem_debug4_cn50xx {
+                uint64_t cmnd_segs:3;
+                uint64_t cmnd_siz:16;
+                uint64_t cmnd_off:6;
+                uint64_t uid:3;
+                uint64_t dread_sop:1;
+                uint64_t init_dwrite:1;
+                uint64_t chk_once:1;
+                uint64_t chk_mode:1;
+                uint64_t active:1;
+                uint64_t static_p:1;
+                uint64_t qos:3;
+                uint64_t qcb_ridx:5;
+                uint64_t qid_off_max:4;
+                uint64_t qid_off:4;
+                uint64_t qid_base:8;
+                uint64_t wait:1;
+                uint64_t minor:2;
+                uint64_t major:3;
+        } cn50xx;
+        struct cvmx_pko_mem_debug4_cn52xx {
+                uint64_t curr_siz:8;
+                uint64_t curr_off:16;
+                uint64_t cmnd_segs:6;
+                uint64_t cmnd_siz:16;
+                uint64_t cmnd_off:6;
+                uint64_t uid:2;
+                uint64_t dread_sop:1;
+                uint64_t init_dwrite:1;
+                uint64_t chk_once:1;
+                uint64_t chk_mode:1;
+                uint64_t wait:1;
+                uint64_t minor:2;
+                uint64_t major:3;
+        } cn52xx;
+        struct cvmx_pko_mem_debug4_cn52xx cn52xxp1;
+        struct cvmx_pko_mem_debug4_cn52xx cn56xx;
+        struct cvmx_pko_mem_debug4_cn52xx cn56xxp1;
+        struct cvmx_pko_mem_debug4_cn50xx cn58xx;
+        struct cvmx_pko_mem_debug4_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_mem_debug5 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug5_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_pko_mem_debug5_cn30xx {
+                uint64_t dwri_mod:1;
+                uint64_t dwri_sop:1;
+                uint64_t dwri_len:1;
+                uint64_t dwri_cnt:13;
+                uint64_t cmnd_siz:16;
+                uint64_t uid:1;
+                uint64_t xfer_wor:1;
+                uint64_t xfer_dwr:1;
+                uint64_t cbuf_fre:1;
+                uint64_t reserved_27_27:1;
+                uint64_t chk_mode:1;
+                uint64_t active:1;
+                uint64_t qos:3;
+                uint64_t qcb_ridx:5;
+                uint64_t qid_off:3;
+                uint64_t qid_base:7;
+                uint64_t wait:1;
+                uint64_t minor:2;
+                uint64_t major:4;
+        } cn30xx;
+        struct cvmx_pko_mem_debug5_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug5_cn30xx cn38xx;
+        struct cvmx_pko_mem_debug5_cn30xx cn38xxp2;
+        struct cvmx_pko_mem_debug5_cn50xx {
+                uint64_t curr_ptr:29;
+                uint64_t curr_siz:16;
+                uint64_t curr_off:16;
+                uint64_t cmnd_segs:3;
+        } cn50xx;
+        struct cvmx_pko_mem_debug5_cn52xx {
+                uint64_t reserved_54_63:10;
+                uint64_t nxt_inflt:6;
+                uint64_t curr_ptr:40;
+                uint64_t curr_siz:8;
+        } cn52xx;
+        struct cvmx_pko_mem_debug5_cn52xx cn52xxp1;
+        struct cvmx_pko_mem_debug5_cn52xx cn56xx;
+        struct cvmx_pko_mem_debug5_cn52xx cn56xxp1;
+        struct cvmx_pko_mem_debug5_cn50xx cn58xx;
+        struct cvmx_pko_mem_debug5_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_mem_debug6 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug6_s {
+                uint64_t reserved_37_63:27;
+                uint64_t qid_offres:4;
+                uint64_t qid_offths:4;
+                uint64_t preempter:1;
+                uint64_t preemptee:1;
+                uint64_t preempted:1;
+                uint64_t active:1;
+                uint64_t statc:1;
+                uint64_t qos:3;
+                uint64_t qcb_ridx:5;
+                uint64_t qid_offmax:4;
+                uint64_t reserved_0_11:12;
+        } s;
+        struct cvmx_pko_mem_debug6_cn30xx {
+                uint64_t reserved_11_63:53;
+                uint64_t qid_offm:3;
+                uint64_t static_p:1;
+                uint64_t work_min:3;
+                uint64_t dwri_chk:1;
+                uint64_t dwri_uid:1;
+                uint64_t dwri_mod:2;
+        } cn30xx;
+        struct cvmx_pko_mem_debug6_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug6_cn30xx cn38xx;
+        struct cvmx_pko_mem_debug6_cn30xx cn38xxp2;
+        struct cvmx_pko_mem_debug6_cn50xx {
+                uint64_t reserved_11_63:53;
+                uint64_t curr_ptr:11;
+        } cn50xx;
+        struct cvmx_pko_mem_debug6_cn52xx {
+                uint64_t reserved_37_63:27;
+                uint64_t qid_offres:4;
+                uint64_t qid_offths:4;
+                uint64_t preempter:1;
+                uint64_t preemptee:1;
+                uint64_t preempted:1;
+                uint64_t active:1;
+                uint64_t statc:1;
+                uint64_t qos:3;
+                uint64_t qcb_ridx:5;
+                uint64_t qid_offmax:4;
+                uint64_t qid_off:4;
+                uint64_t qid_base:8;
+        } cn52xx;
+        struct cvmx_pko_mem_debug6_cn52xx cn52xxp1;
+        struct cvmx_pko_mem_debug6_cn52xx cn56xx;
+        struct cvmx_pko_mem_debug6_cn52xx cn56xxp1;
+        struct cvmx_pko_mem_debug6_cn50xx cn58xx;
+        struct cvmx_pko_mem_debug6_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_mem_debug7 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug7_s {
+                uint64_t qos:5;
+                uint64_t tail:1;
+                uint64_t reserved_0_57:58;
+        } s;
+        struct cvmx_pko_mem_debug7_cn30xx {
+                uint64_t reserved_58_63:6;
+                uint64_t dwb:9;
+                uint64_t start:33;
+                uint64_t size:16;
+        } cn30xx;
+        struct cvmx_pko_mem_debug7_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug7_cn30xx cn38xx;
+        struct cvmx_pko_mem_debug7_cn30xx cn38xxp2;
+        struct cvmx_pko_mem_debug7_cn50xx {
+                uint64_t qos:5;
+                uint64_t tail:1;
+                uint64_t buf_siz:13;
+                uint64_t buf_ptr:33;
+                uint64_t qcb_widx:6;
+                uint64_t qcb_ridx:6;
+        } cn50xx;
+        struct cvmx_pko_mem_debug7_cn50xx cn52xx;
+        struct cvmx_pko_mem_debug7_cn50xx cn52xxp1;
+        struct cvmx_pko_mem_debug7_cn50xx cn56xx;
+        struct cvmx_pko_mem_debug7_cn50xx cn56xxp1;
+        struct cvmx_pko_mem_debug7_cn50xx cn58xx;
+        struct cvmx_pko_mem_debug7_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_mem_debug8 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug8_s {
+                uint64_t reserved_59_63:5;
+                uint64_t tail:1;
+                uint64_t buf_siz:13;
+                uint64_t reserved_0_44:45;
+        } s;
+        struct cvmx_pko_mem_debug8_cn30xx {
+                uint64_t qos:5;
+                uint64_t tail:1;
+                uint64_t buf_siz:13;
+                uint64_t buf_ptr:33;
+                uint64_t qcb_widx:6;
+                uint64_t qcb_ridx:6;
+        } cn30xx;
+        struct cvmx_pko_mem_debug8_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug8_cn30xx cn38xx;
+        struct cvmx_pko_mem_debug8_cn30xx cn38xxp2;
+        struct cvmx_pko_mem_debug8_cn50xx {
+                uint64_t reserved_28_63:36;
+                uint64_t doorbell:20;
+                uint64_t reserved_6_7:2;
+                uint64_t static_p:1;
+                uint64_t s_tail:1;
+                uint64_t static_q:1;
+                uint64_t qos:3;
+        } cn50xx;
+        struct cvmx_pko_mem_debug8_cn52xx {
+                uint64_t reserved_29_63:35;
+                uint64_t preempter:1;
+                uint64_t doorbell:20;
+                uint64_t reserved_7_7:1;
+                uint64_t preemptee:1;
+                uint64_t static_p:1;
+                uint64_t s_tail:1;
+                uint64_t static_q:1;
+                uint64_t qos:3;
+        } cn52xx;
+        struct cvmx_pko_mem_debug8_cn52xx cn52xxp1;
+        struct cvmx_pko_mem_debug8_cn52xx cn56xx;
+        struct cvmx_pko_mem_debug8_cn52xx cn56xxp1;
+        struct cvmx_pko_mem_debug8_cn50xx cn58xx;
+        struct cvmx_pko_mem_debug8_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_mem_debug9 {
+        uint64_t u64;
+        struct cvmx_pko_mem_debug9_s {
+                uint64_t reserved_49_63:15;
+                uint64_t ptrs0:17;
+                uint64_t reserved_0_31:32;
+        } s;
+        struct cvmx_pko_mem_debug9_cn30xx {
+                uint64_t reserved_28_63:36;
+                uint64_t doorbell:20;
+                uint64_t reserved_5_7:3;
+                uint64_t s_tail:1;
+                uint64_t static_q:1;
+                uint64_t qos:3;
+        } cn30xx;
+        struct cvmx_pko_mem_debug9_cn30xx cn31xx;
+        struct cvmx_pko_mem_debug9_cn38xx {
+                uint64_t reserved_28_63:36;
+                uint64_t doorbell:20;
+                uint64_t reserved_6_7:2;
+                uint64_t static_p:1;
+                uint64_t s_tail:1;
+                uint64_t static_q:1;
+                uint64_t qos:3;
+        } cn38xx;
+        struct cvmx_pko_mem_debug9_cn38xx cn38xxp2;
+        struct cvmx_pko_mem_debug9_cn50xx {
+                uint64_t reserved_49_63:15;
+                uint64_t ptrs0:17;
+                uint64_t reserved_17_31:15;
+                uint64_t ptrs3:17;
+        } cn50xx;
+        struct cvmx_pko_mem_debug9_cn50xx cn52xx;
+        struct cvmx_pko_mem_debug9_cn50xx cn52xxp1;
+        struct cvmx_pko_mem_debug9_cn50xx cn56xx;
+        struct cvmx_pko_mem_debug9_cn50xx cn56xxp1;
+        struct cvmx_pko_mem_debug9_cn50xx cn58xx;
+        struct cvmx_pko_mem_debug9_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_mem_port_ptrs {
+        uint64_t u64;
+        struct cvmx_pko_mem_port_ptrs_s {
+                uint64_t reserved_62_63:2;
+                uint64_t static_p:1;
+                uint64_t qos_mask:8;
+                uint64_t reserved_16_52:37;
+                uint64_t bp_port:6;
+                uint64_t eid:4;
+                uint64_t pid:6;
+        } s;
+        struct cvmx_pko_mem_port_ptrs_s cn52xx;
+        struct cvmx_pko_mem_port_ptrs_s cn52xxp1;
+        struct cvmx_pko_mem_port_ptrs_s cn56xx;
+        struct cvmx_pko_mem_port_ptrs_s cn56xxp1;
+};
+
+union cvmx_pko_mem_port_qos {
+        uint64_t u64;
+        struct cvmx_pko_mem_port_qos_s {
+                uint64_t reserved_61_63:3;
+                uint64_t qos_mask:8;
+                uint64_t reserved_10_52:43;
+                uint64_t eid:4;
+                uint64_t pid:6;
+        } s;
+        struct cvmx_pko_mem_port_qos_s cn52xx;
+        struct cvmx_pko_mem_port_qos_s cn52xxp1;
+        struct cvmx_pko_mem_port_qos_s cn56xx;
+        struct cvmx_pko_mem_port_qos_s cn56xxp1;
+};
+
+union cvmx_pko_mem_port_rate0 {
+        uint64_t u64;
+        struct cvmx_pko_mem_port_rate0_s {
+                uint64_t reserved_51_63:13;
+                uint64_t rate_word:19;
+                uint64_t rate_pkt:24;
+                uint64_t reserved_6_7:2;
+                uint64_t pid:6;
+        } s;
+        struct cvmx_pko_mem_port_rate0_s cn52xx;
+        struct cvmx_pko_mem_port_rate0_s cn52xxp1;
+        struct cvmx_pko_mem_port_rate0_s cn56xx;
+        struct cvmx_pko_mem_port_rate0_s cn56xxp1;
+};
+
+union cvmx_pko_mem_port_rate1 {
+        uint64_t u64;
+        struct cvmx_pko_mem_port_rate1_s {
+                uint64_t reserved_32_63:32;
+                uint64_t rate_lim:24;
+                uint64_t reserved_6_7:2;
+                uint64_t pid:6;
+        } s;
+        struct cvmx_pko_mem_port_rate1_s cn52xx;
+        struct cvmx_pko_mem_port_rate1_s cn52xxp1;
+        struct cvmx_pko_mem_port_rate1_s cn56xx;
+        struct cvmx_pko_mem_port_rate1_s cn56xxp1;
+};
+
+union cvmx_pko_mem_queue_ptrs {
+        uint64_t u64;
+        struct cvmx_pko_mem_queue_ptrs_s {
+                uint64_t s_tail:1;
+                uint64_t static_p:1;
+                uint64_t static_q:1;
+                uint64_t qos_mask:8;
+                uint64_t buf_ptr:36;
+                uint64_t tail:1;
+                uint64_t index:3;
+                uint64_t port:6;
+                uint64_t queue:7;
+        } s;
+        struct cvmx_pko_mem_queue_ptrs_s cn30xx;
+        struct cvmx_pko_mem_queue_ptrs_s cn31xx;
+        struct cvmx_pko_mem_queue_ptrs_s cn38xx;
+        struct cvmx_pko_mem_queue_ptrs_s cn38xxp2;
+        struct cvmx_pko_mem_queue_ptrs_s cn50xx;
+        struct cvmx_pko_mem_queue_ptrs_s cn52xx;
+        struct cvmx_pko_mem_queue_ptrs_s cn52xxp1;
+        struct cvmx_pko_mem_queue_ptrs_s cn56xx;
+        struct cvmx_pko_mem_queue_ptrs_s cn56xxp1;
+        struct cvmx_pko_mem_queue_ptrs_s cn58xx;
+        struct cvmx_pko_mem_queue_ptrs_s cn58xxp1;
+};
+
+union cvmx_pko_mem_queue_qos {
+        uint64_t u64;
+        struct cvmx_pko_mem_queue_qos_s {
+                uint64_t reserved_61_63:3;
+                uint64_t qos_mask:8;
+                uint64_t reserved_13_52:40;
+                uint64_t pid:6;
+                uint64_t qid:7;
+        } s;
+        struct cvmx_pko_mem_queue_qos_s cn30xx;
+        struct cvmx_pko_mem_queue_qos_s cn31xx;
+        struct cvmx_pko_mem_queue_qos_s cn38xx;
+        struct cvmx_pko_mem_queue_qos_s cn38xxp2;
+        struct cvmx_pko_mem_queue_qos_s cn50xx;
+        struct cvmx_pko_mem_queue_qos_s cn52xx;
+        struct cvmx_pko_mem_queue_qos_s cn52xxp1;
+        struct cvmx_pko_mem_queue_qos_s cn56xx;
+        struct cvmx_pko_mem_queue_qos_s cn56xxp1;
+        struct cvmx_pko_mem_queue_qos_s cn58xx;
+        struct cvmx_pko_mem_queue_qos_s cn58xxp1;
+};
+
+union cvmx_pko_reg_bist_result {
+        uint64_t u64;
+        struct cvmx_pko_reg_bist_result_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_pko_reg_bist_result_cn30xx {
+                uint64_t reserved_27_63:37;
+                uint64_t psb2:5;
+                uint64_t count:1;
+                uint64_t rif:1;
+                uint64_t wif:1;
+                uint64_t ncb:1;
+                uint64_t out:1;
+                uint64_t crc:1;
+                uint64_t chk:1;
+                uint64_t qsb:2;
+                uint64_t qcb:2;
+                uint64_t pdb:4;
+                uint64_t psb:7;
+        } cn30xx;
+        struct cvmx_pko_reg_bist_result_cn30xx cn31xx;
+        struct cvmx_pko_reg_bist_result_cn30xx cn38xx;
+        struct cvmx_pko_reg_bist_result_cn30xx cn38xxp2;
+        struct cvmx_pko_reg_bist_result_cn50xx {
+                uint64_t reserved_33_63:31;
+                uint64_t csr:1;
+                uint64_t iob:1;
+                uint64_t out_crc:1;
+                uint64_t out_ctl:3;
+                uint64_t out_sta:1;
+                uint64_t out_wif:1;
+                uint64_t prt_chk:3;
+                uint64_t prt_nxt:1;
+                uint64_t prt_psb:6;
+                uint64_t ncb_inb:2;
+                uint64_t prt_qcb:2;
+                uint64_t prt_qsb:3;
+                uint64_t dat_dat:4;
+                uint64_t dat_ptr:4;
+        } cn50xx;
+        struct cvmx_pko_reg_bist_result_cn52xx {
+                uint64_t reserved_35_63:29;
+                uint64_t csr:1;
+                uint64_t iob:1;
+                uint64_t out_dat:1;
+                uint64_t out_ctl:3;
+                uint64_t out_sta:1;
+                uint64_t out_wif:1;
+                uint64_t prt_chk:3;
+                uint64_t prt_nxt:1;
+                uint64_t prt_psb:8;
+                uint64_t ncb_inb:2;
+                uint64_t prt_qcb:2;
+                uint64_t prt_qsb:3;
+                uint64_t prt_ctl:2;
+                uint64_t dat_dat:2;
+                uint64_t dat_ptr:4;
+        } cn52xx;
+        struct cvmx_pko_reg_bist_result_cn52xx cn52xxp1;
+        struct cvmx_pko_reg_bist_result_cn52xx cn56xx;
+        struct cvmx_pko_reg_bist_result_cn52xx cn56xxp1;
+        struct cvmx_pko_reg_bist_result_cn50xx cn58xx;
+        struct cvmx_pko_reg_bist_result_cn50xx cn58xxp1;
+};
+
+union cvmx_pko_reg_cmd_buf {
+        uint64_t u64;
+        struct cvmx_pko_reg_cmd_buf_s {
+                uint64_t reserved_23_63:41;
+                uint64_t pool:3;
+                uint64_t reserved_13_19:7;
+                uint64_t size:13;
+        } s;
+        struct cvmx_pko_reg_cmd_buf_s cn30xx;
+        struct cvmx_pko_reg_cmd_buf_s cn31xx;
+        struct cvmx_pko_reg_cmd_buf_s cn38xx;
+        struct cvmx_pko_reg_cmd_buf_s cn38xxp2;
+        struct cvmx_pko_reg_cmd_buf_s cn50xx;
+        struct cvmx_pko_reg_cmd_buf_s cn52xx;
+        struct cvmx_pko_reg_cmd_buf_s cn52xxp1;
+        struct cvmx_pko_reg_cmd_buf_s cn56xx;
+        struct cvmx_pko_reg_cmd_buf_s cn56xxp1;
+        struct cvmx_pko_reg_cmd_buf_s cn58xx;
+        struct cvmx_pko_reg_cmd_buf_s cn58xxp1;
+};
+
+union cvmx_pko_reg_crc_ctlx {
+        uint64_t u64;
+        struct cvmx_pko_reg_crc_ctlx_s {
+                uint64_t reserved_2_63:62;
+                uint64_t invres:1;
+                uint64_t refin:1;
+        } s;
+        struct cvmx_pko_reg_crc_ctlx_s cn38xx;
+        struct cvmx_pko_reg_crc_ctlx_s cn38xxp2;
+        struct cvmx_pko_reg_crc_ctlx_s cn58xx;
+        struct cvmx_pko_reg_crc_ctlx_s cn58xxp1;
+};
+
+union cvmx_pko_reg_crc_enable {
+        uint64_t u64;
+        struct cvmx_pko_reg_crc_enable_s {
+                uint64_t reserved_32_63:32;
+                uint64_t enable:32;
+        } s;
+        struct cvmx_pko_reg_crc_enable_s cn38xx;
+        struct cvmx_pko_reg_crc_enable_s cn38xxp2;
+        struct cvmx_pko_reg_crc_enable_s cn58xx;
+        struct cvmx_pko_reg_crc_enable_s cn58xxp1;
+};
+
+union cvmx_pko_reg_crc_ivx {
+        uint64_t u64;
+        struct cvmx_pko_reg_crc_ivx_s {
+                uint64_t reserved_32_63:32;
+                uint64_t iv:32;
+        } s;
+        struct cvmx_pko_reg_crc_ivx_s cn38xx;
+        struct cvmx_pko_reg_crc_ivx_s cn38xxp2;
+        struct cvmx_pko_reg_crc_ivx_s cn58xx;
+        struct cvmx_pko_reg_crc_ivx_s cn58xxp1;
+};
+
+union cvmx_pko_reg_debug0 {
+        uint64_t u64;
+        struct cvmx_pko_reg_debug0_s {
+                uint64_t asserts:64;
+        } s;
+        struct cvmx_pko_reg_debug0_cn30xx {
+                uint64_t reserved_17_63:47;
+                uint64_t asserts:17;
+        } cn30xx;
+        struct cvmx_pko_reg_debug0_cn30xx cn31xx;
+        struct cvmx_pko_reg_debug0_cn30xx cn38xx;
+        struct cvmx_pko_reg_debug0_cn30xx cn38xxp2;
+        struct cvmx_pko_reg_debug0_s cn50xx;
+        struct cvmx_pko_reg_debug0_s cn52xx;
+        struct cvmx_pko_reg_debug0_s cn52xxp1;
+        struct cvmx_pko_reg_debug0_s cn56xx;
+        struct cvmx_pko_reg_debug0_s cn56xxp1;
+        struct cvmx_pko_reg_debug0_s cn58xx;
+        struct cvmx_pko_reg_debug0_s cn58xxp1;
+};
+
+union cvmx_pko_reg_debug1 {
+        uint64_t u64;
+        struct cvmx_pko_reg_debug1_s {
+                uint64_t asserts:64;
+        } s;
+        struct cvmx_pko_reg_debug1_s cn50xx;
+        struct cvmx_pko_reg_debug1_s cn52xx;
+        struct cvmx_pko_reg_debug1_s cn52xxp1;
+        struct cvmx_pko_reg_debug1_s cn56xx;
+        struct cvmx_pko_reg_debug1_s cn56xxp1;
+        struct cvmx_pko_reg_debug1_s cn58xx;
+        struct cvmx_pko_reg_debug1_s cn58xxp1;
+};
+
+union cvmx_pko_reg_debug2 {
+        uint64_t u64;
+        struct cvmx_pko_reg_debug2_s {
+                uint64_t asserts:64;
+        } s;
+        struct cvmx_pko_reg_debug2_s cn50xx;
+        struct cvmx_pko_reg_debug2_s cn52xx;
+        struct cvmx_pko_reg_debug2_s cn52xxp1;
+        struct cvmx_pko_reg_debug2_s cn56xx;
+        struct cvmx_pko_reg_debug2_s cn56xxp1;
+        struct cvmx_pko_reg_debug2_s cn58xx;
+        struct cvmx_pko_reg_debug2_s cn58xxp1;
+};
+
+union cvmx_pko_reg_debug3 {
+        uint64_t u64;
+        struct cvmx_pko_reg_debug3_s {
+                uint64_t asserts:64;
+        } s;
+        struct cvmx_pko_reg_debug3_s cn50xx;
+        struct cvmx_pko_reg_debug3_s cn52xx;
+        struct cvmx_pko_reg_debug3_s cn52xxp1;
+        struct cvmx_pko_reg_debug3_s cn56xx;
+        struct cvmx_pko_reg_debug3_s cn56xxp1;
+        struct cvmx_pko_reg_debug3_s cn58xx;
+        struct cvmx_pko_reg_debug3_s cn58xxp1;
+};
+
+union cvmx_pko_reg_engine_inflight {
+        uint64_t u64;
+        struct cvmx_pko_reg_engine_inflight_s {
+                uint64_t reserved_40_63:24;
+                uint64_t engine9:4;
+                uint64_t engine8:4;
+                uint64_t engine7:4;
+                uint64_t engine6:4;
+                uint64_t engine5:4;
+                uint64_t engine4:4;
+                uint64_t engine3:4;
+                uint64_t engine2:4;
+                uint64_t engine1:4;
+                uint64_t engine0:4;
+        } s;
+        struct cvmx_pko_reg_engine_inflight_s cn52xx;
+        struct cvmx_pko_reg_engine_inflight_s cn52xxp1;
+        struct cvmx_pko_reg_engine_inflight_s cn56xx;
+        struct cvmx_pko_reg_engine_inflight_s cn56xxp1;
+};
+
+union cvmx_pko_reg_engine_thresh {
+        uint64_t u64;
+        struct cvmx_pko_reg_engine_thresh_s {
+                uint64_t reserved_10_63:54;
+                uint64_t mask:10;
+        } s;
+        struct cvmx_pko_reg_engine_thresh_s cn52xx;
+        struct cvmx_pko_reg_engine_thresh_s cn52xxp1;
+        struct cvmx_pko_reg_engine_thresh_s cn56xx;
+        struct cvmx_pko_reg_engine_thresh_s cn56xxp1;
+};
+
+union cvmx_pko_reg_error {
+        uint64_t u64;
+        struct cvmx_pko_reg_error_s {
+                uint64_t reserved_3_63:61;
+                uint64_t currzero:1;
+                uint64_t doorbell:1;
+                uint64_t parity:1;
+        } s;
+        struct cvmx_pko_reg_error_cn30xx {
+                uint64_t reserved_2_63:62;
+                uint64_t doorbell:1;
+                uint64_t parity:1;
+        } cn30xx;
+        struct cvmx_pko_reg_error_cn30xx cn31xx;
+        struct cvmx_pko_reg_error_cn30xx cn38xx;
+        struct cvmx_pko_reg_error_cn30xx cn38xxp2;
+        struct cvmx_pko_reg_error_s cn50xx;
+        struct cvmx_pko_reg_error_s cn52xx;
+        struct cvmx_pko_reg_error_s cn52xxp1;
+        struct cvmx_pko_reg_error_s cn56xx;
+        struct cvmx_pko_reg_error_s cn56xxp1;
+        struct cvmx_pko_reg_error_s cn58xx;
+        struct cvmx_pko_reg_error_s cn58xxp1;
+};
+
+union cvmx_pko_reg_flags {
+        uint64_t u64;
+        struct cvmx_pko_reg_flags_s {
+                uint64_t reserved_4_63:60;
+                uint64_t reset:1;
+                uint64_t store_be:1;
+                uint64_t ena_dwb:1;
+                uint64_t ena_pko:1;
+        } s;
+        struct cvmx_pko_reg_flags_s cn30xx;
+        struct cvmx_pko_reg_flags_s cn31xx;
+        struct cvmx_pko_reg_flags_s cn38xx;
+        struct cvmx_pko_reg_flags_s cn38xxp2;
+        struct cvmx_pko_reg_flags_s cn50xx;
+        struct cvmx_pko_reg_flags_s cn52xx;
+        struct cvmx_pko_reg_flags_s cn52xxp1;
+        struct cvmx_pko_reg_flags_s cn56xx;
+        struct cvmx_pko_reg_flags_s cn56xxp1;
+        struct cvmx_pko_reg_flags_s cn58xx;
+        struct cvmx_pko_reg_flags_s cn58xxp1;
+};
+
+union cvmx_pko_reg_gmx_port_mode {
+        uint64_t u64;
+        struct cvmx_pko_reg_gmx_port_mode_s {
+                uint64_t reserved_6_63:58;
+                uint64_t mode1:3;
+                uint64_t mode0:3;
+        } s;
+        struct cvmx_pko_reg_gmx_port_mode_s cn30xx;
+        struct cvmx_pko_reg_gmx_port_mode_s cn31xx;
+        struct cvmx_pko_reg_gmx_port_mode_s cn38xx;
+        struct cvmx_pko_reg_gmx_port_mode_s cn38xxp2;
+        struct cvmx_pko_reg_gmx_port_mode_s cn50xx;
+        struct cvmx_pko_reg_gmx_port_mode_s cn52xx;
+        struct cvmx_pko_reg_gmx_port_mode_s cn52xxp1;
+        struct cvmx_pko_reg_gmx_port_mode_s cn56xx;
+        struct cvmx_pko_reg_gmx_port_mode_s cn56xxp1;
+        struct cvmx_pko_reg_gmx_port_mode_s cn58xx;
+        struct cvmx_pko_reg_gmx_port_mode_s cn58xxp1;
+};
+
+union cvmx_pko_reg_int_mask {
+        uint64_t u64;
+        struct cvmx_pko_reg_int_mask_s {
+                uint64_t reserved_3_63:61;
+                uint64_t currzero:1;
+                uint64_t doorbell:1;
+                uint64_t parity:1;
+        } s;
+        struct cvmx_pko_reg_int_mask_cn30xx {
+                uint64_t reserved_2_63:62;
+                uint64_t doorbell:1;
+                uint64_t parity:1;
+        } cn30xx;
+        struct cvmx_pko_reg_int_mask_cn30xx cn31xx;
+        struct cvmx_pko_reg_int_mask_cn30xx cn38xx;
+        struct cvmx_pko_reg_int_mask_cn30xx cn38xxp2;
+        struct cvmx_pko_reg_int_mask_s cn50xx;
+        struct cvmx_pko_reg_int_mask_s cn52xx;
+        struct cvmx_pko_reg_int_mask_s cn52xxp1;
+        struct cvmx_pko_reg_int_mask_s cn56xx;
+        struct cvmx_pko_reg_int_mask_s cn56xxp1;
+        struct cvmx_pko_reg_int_mask_s cn58xx;
+        struct cvmx_pko_reg_int_mask_s cn58xxp1;
+};
+
+union cvmx_pko_reg_queue_mode {
+        uint64_t u64;
+        struct cvmx_pko_reg_queue_mode_s {
+                uint64_t reserved_2_63:62;
+                uint64_t mode:2;
+        } s;
+        struct cvmx_pko_reg_queue_mode_s cn30xx;
+        struct cvmx_pko_reg_queue_mode_s cn31xx;
+        struct cvmx_pko_reg_queue_mode_s cn38xx;
+        struct cvmx_pko_reg_queue_mode_s cn38xxp2;
+        struct cvmx_pko_reg_queue_mode_s cn50xx;
+        struct cvmx_pko_reg_queue_mode_s cn52xx;
+        struct cvmx_pko_reg_queue_mode_s cn52xxp1;
+        struct cvmx_pko_reg_queue_mode_s cn56xx;
+        struct cvmx_pko_reg_queue_mode_s cn56xxp1;
+        struct cvmx_pko_reg_queue_mode_s cn58xx;
+        struct cvmx_pko_reg_queue_mode_s cn58xxp1;
+};
+
+union cvmx_pko_reg_queue_ptrs1 {
+        uint64_t u64;
+        struct cvmx_pko_reg_queue_ptrs1_s {
+                uint64_t reserved_2_63:62;
+                uint64_t idx3:1;
+                uint64_t qid7:1;
+        } s;
+        struct cvmx_pko_reg_queue_ptrs1_s cn50xx;
+        struct cvmx_pko_reg_queue_ptrs1_s cn52xx;
+        struct cvmx_pko_reg_queue_ptrs1_s cn52xxp1;
+        struct cvmx_pko_reg_queue_ptrs1_s cn56xx;
+        struct cvmx_pko_reg_queue_ptrs1_s cn56xxp1;
+        struct cvmx_pko_reg_queue_ptrs1_s cn58xx;
+        struct cvmx_pko_reg_queue_ptrs1_s cn58xxp1;
+};
+
+union cvmx_pko_reg_read_idx {
+        uint64_t u64;
+        struct cvmx_pko_reg_read_idx_s {
+                uint64_t reserved_16_63:48;
+                uint64_t inc:8;
+                uint64_t index:8;
+        } s;
+        struct cvmx_pko_reg_read_idx_s cn30xx;
+        struct cvmx_pko_reg_read_idx_s cn31xx;
+        struct cvmx_pko_reg_read_idx_s cn38xx;
+        struct cvmx_pko_reg_read_idx_s cn38xxp2;
+        struct cvmx_pko_reg_read_idx_s cn50xx;
+        struct cvmx_pko_reg_read_idx_s cn52xx;
+        struct cvmx_pko_reg_read_idx_s cn52xxp1;
+        struct cvmx_pko_reg_read_idx_s cn56xx;
+        struct cvmx_pko_reg_read_idx_s cn56xxp1;
+        struct cvmx_pko_reg_read_idx_s cn58xx;
+        struct cvmx_pko_reg_read_idx_s cn58xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-pko.c b/drivers/staging/octeon/cvmx-pko.c
new file mode 100644
index 000000000000..00db91529b19
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-pko.c
@@ -0,0 +1,506 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ * Support library for the hardware Packet Output unit.
+ */
+
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-config.h"
+#include "cvmx-pko.h"
+#include "cvmx-helper.h"
+
+/**
+ * Internal state of packet output
+ */
+
+/**
+ * Call before any other calls to initialize the packet
+ * output system.  This does chip global config, and should only be
+ * done by one core.
+ */
+
+void cvmx_pko_initialize_global(void)
+{
+        int i;
+        uint64_t priority = 8;
+        union cvmx_pko_reg_cmd_buf config;
+
+        /*
+         * Set the size of the PKO command buffers to an odd number of
+         * 64bit words. This allows the normal two word send to stay
+         * aligned and never span a comamnd word buffer.
+         */
+        config.u64 = 0;
+        config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
+        config.s.size = CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE / 8 - 1;
+
+        cvmx_write_csr(CVMX_PKO_REG_CMD_BUF, config.u64);
+
+        for (i = 0; i < CVMX_PKO_MAX_OUTPUT_QUEUES; i++)
+                cvmx_pko_config_port(CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID, i, 1,
+                                     &priority);
+
+        /*
+         * If we aren't using all of the queues optimize PKO's
+         * internal memory.
+         */
+        if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)
+            || OCTEON_IS_MODEL(OCTEON_CN56XX)
+            || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
+                int num_interfaces = cvmx_helper_get_number_of_interfaces();
+                int last_port =
+                    cvmx_helper_get_last_ipd_port(num_interfaces - 1);
+                int max_queues =
+                    cvmx_pko_get_base_queue(last_port) +
+                    cvmx_pko_get_num_queues(last_port);
+                if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
+                        if (max_queues <= 32)
+                                cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
+                        else if (max_queues <= 64)
+                                cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
+                } else {
+                        if (max_queues <= 64)
+                                cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 2);
+                        else if (max_queues <= 128)
+                                cvmx_write_csr(CVMX_PKO_REG_QUEUE_MODE, 1);
+                }
+        }
+}
+
+/**
+ * This function does per-core initialization required by the PKO routines.
+ * This must be called on all cores that will do packet output, and must
+ * be called after the FPA has been initialized and filled with pages.
+ *
+ * Returns 0 on success
+ *         !0 on failure
+ */
+int cvmx_pko_initialize_local(void)
+{
+        /* Nothing to do */
+        return 0;
+}
+
+/**
+ * Enables the packet output hardware. It must already be
+ * configured.
+ */
+void cvmx_pko_enable(void)
+{
+        union cvmx_pko_reg_flags flags;
+
+        flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
+        if (flags.s.ena_pko)
+                cvmx_dprintf
+                    ("Warning: Enabling PKO when PKO already enabled.\n");
+
+        flags.s.ena_dwb = 1;
+        flags.s.ena_pko = 1;
+        /*
+         * always enable big endian for 3-word command. Does nothing
+         * for 2-word.
+         */
+        flags.s.store_be = 1;
+        cvmx_write_csr(CVMX_PKO_REG_FLAGS, flags.u64);
+}
+
+/**
+ * Disables the packet output. Does not affect any configuration.
+ */
+void cvmx_pko_disable(void)
+{
+        union cvmx_pko_reg_flags pko_reg_flags;
+        pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
+        pko_reg_flags.s.ena_pko = 0;
+        cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
+}
+
+
+/**
+ * Reset the packet output.
+ */
+static void __cvmx_pko_reset(void)
+{
+        union cvmx_pko_reg_flags pko_reg_flags;
+        pko_reg_flags.u64 = cvmx_read_csr(CVMX_PKO_REG_FLAGS);
+        pko_reg_flags.s.reset = 1;
+        cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64);
+}
+
+/**
+ * Shutdown and free resources required by packet output.
+ */
+void cvmx_pko_shutdown(void)
+{
+        union cvmx_pko_mem_queue_ptrs config;
+        int queue;
+
+        cvmx_pko_disable();
+
+        for (queue = 0; queue < CVMX_PKO_MAX_OUTPUT_QUEUES; queue++) {
+                config.u64 = 0;
+                config.s.tail = 1;
+                config.s.index = 0;
+                config.s.port = CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID;
+                config.s.queue = queue & 0x7f;
+                config.s.qos_mask = 0;
+                config.s.buf_ptr = 0;
+                if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+                        union cvmx_pko_reg_queue_ptrs1 config1;
+                        config1.u64 = 0;
+                        config1.s.qid7 = queue >> 7;
+                        cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
+                }
+                cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
+                cvmx_cmd_queue_shutdown(CVMX_CMD_QUEUE_PKO(queue));
+        }
+        __cvmx_pko_reset();
+}
+
+/**
+ * Configure a output port and the associated queues for use.
+ *
+ * @port:       Port to configure.
+ * @base_queue: First queue number to associate with this port.
+ * @num_queues: Number of queues to associate with this port
+ * @priority:   Array of priority levels for each queue. Values are
+ *                   allowed to be 0-8. A value of 8 get 8 times the traffic
+ *                   of a value of 1.  A value of 0 indicates that no rounds
+ *                   will be participated in. These priorities can be changed
+ *                   on the fly while the pko is enabled. A priority of 9
+ *                   indicates that static priority should be used.  If static
+ *                   priority is used all queues with static priority must be
+ *                   contiguous starting at the base_queue, and lower numbered
+ *                   queues have higher priority than higher numbered queues.
+ *                   There must be num_queues elements in the array.
+ */
+cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
+                                       uint64_t num_queues,
+                                       const uint64_t priority[])
+{
+        cvmx_pko_status_t result_code;
+        uint64_t queue;
+        union cvmx_pko_mem_queue_ptrs config;
+        union cvmx_pko_reg_queue_ptrs1 config1;
+        int static_priority_base = -1;
+        int static_priority_end = -1;
+
+        if ((port >= CVMX_PKO_NUM_OUTPUT_PORTS)
+            && (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID)) {
+                cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid port %llu\n",
+                             (unsigned long long)port);
+                return CVMX_PKO_INVALID_PORT;
+        }
+
+        if (base_queue + num_queues > CVMX_PKO_MAX_OUTPUT_QUEUES) {
+                cvmx_dprintf
+                    ("ERROR: cvmx_pko_config_port: Invalid queue range %llu\n",
+                     (unsigned long long)(base_queue + num_queues));
+                return CVMX_PKO_INVALID_QUEUE;
+        }
+
+        if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) {
+                /*
+                 * Validate the static queue priority setup and set
+                 * static_priority_base and static_priority_end
+                 * accordingly.
+                 */
+                for (queue = 0; queue < num_queues; queue++) {
+                        /* Find first queue of static priority */
+                        if (static_priority_base == -1
+                            && priority[queue] ==
+                            CVMX_PKO_QUEUE_STATIC_PRIORITY)
+                                static_priority_base = queue;
+                        /* Find last queue of static priority */
+                        if (static_priority_base != -1
+                            && static_priority_end == -1
+                            && priority[queue] != CVMX_PKO_QUEUE_STATIC_PRIORITY
+                            && queue)
+                                static_priority_end = queue - 1;
+                        else if (static_priority_base != -1
+                                 && static_priority_end == -1
+                                 && queue == num_queues - 1)
+                                /* all queues are static priority */
+                                static_priority_end = queue;
+                        /*
+                         * Check to make sure all static priority
+                         * queues are contiguous.  Also catches some
+                         * cases of static priorites not starting at
+                         * queue 0.
+                         */
+                        if (static_priority_end != -1
+                            && (int)queue > static_priority_end
+                            && priority[queue] ==
+                            CVMX_PKO_QUEUE_STATIC_PRIORITY) {
+                                cvmx_dprintf("ERROR: cvmx_pko_config_port: "
+                                             "Static priority queues aren't "
+                                             "contiguous or don't start at "
+                                             "base queue. q: %d, eq: %d\n",
+                                        (int)queue, static_priority_end);
+                                return CVMX_PKO_INVALID_PRIORITY;
+                        }
+                }
+                if (static_priority_base > 0) {
+                        cvmx_dprintf("ERROR: cvmx_pko_config_port: Static "
+                                     "priority queues don't start at base "
+                                     "queue. sq: %d\n",
+                                static_priority_base);
+                        return CVMX_PKO_INVALID_PRIORITY;
+                }
+#if 0
+                cvmx_dprintf("Port %d: Static priority queue base: %d, "
+                             "end: %d\n", port,
+                        static_priority_base, static_priority_end);
+#endif
+        }
+        /*
+         * At this point, static_priority_base and static_priority_end
+         * are either both -1, or are valid start/end queue
+         * numbers.
+         */
+
+        result_code = CVMX_PKO_SUCCESS;
+
+#ifdef PKO_DEBUG
+        cvmx_dprintf("num queues: %d (%lld,%lld)\n", num_queues,
+                     CVMX_PKO_QUEUES_PER_PORT_INTERFACE0,
+                     CVMX_PKO_QUEUES_PER_PORT_INTERFACE1);
+#endif
+
+        for (queue = 0; queue < num_queues; queue++) {
+                uint64_t *buf_ptr = NULL;
+
+                config1.u64 = 0;
+                config1.s.idx3 = queue >> 3;
+                config1.s.qid7 = (base_queue + queue) >> 7;
+
+                config.u64 = 0;
+                config.s.tail = queue == (num_queues - 1);
+                config.s.index = queue;
+                config.s.port = port;
+                config.s.queue = base_queue + queue;
+
+                if (!cvmx_octeon_is_pass1()) {
+                        config.s.static_p = static_priority_base >= 0;
+                        config.s.static_q = (int)queue <= static_priority_end;
+                        config.s.s_tail = (int)queue == static_priority_end;
+                }
+                /*
+                 * Convert the priority into an enable bit field. Try
+                 * to space the bits out evenly so the packet don't
+                 * get grouped up
+                 */
+                switch ((int)priority[queue]) {
+                case 0:
+                        config.s.qos_mask = 0x00;
+                        break;
+                case 1:
+                        config.s.qos_mask = 0x01;
+                        break;
+                case 2:
+                        config.s.qos_mask = 0x11;
+                        break;
+                case 3:
+                        config.s.qos_mask = 0x49;
+                        break;
+                case 4:
+                        config.s.qos_mask = 0x55;
+                        break;
+                case 5:
+                        config.s.qos_mask = 0x57;
+                        break;
+                case 6:
+                        config.s.qos_mask = 0x77;
+                        break;
+                case 7:
+                        config.s.qos_mask = 0x7f;
+                        break;
+                case 8:
+                        config.s.qos_mask = 0xff;
+                        break;
+                case CVMX_PKO_QUEUE_STATIC_PRIORITY:
+                        /* Pass 1 will fall through to the error case */
+                        if (!cvmx_octeon_is_pass1()) {
+                                config.s.qos_mask = 0xff;
+                                break;
+                        }
+                default:
+                        cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid "
+                                     "priority %llu\n",
+                                (unsigned long long)priority[queue]);
+                        config.s.qos_mask = 0xff;
+                        result_code = CVMX_PKO_INVALID_PRIORITY;
+                        break;
+                }
+
+                if (port != CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID) {
+                        cvmx_cmd_queue_result_t cmd_res =
+                            cvmx_cmd_queue_initialize(CVMX_CMD_QUEUE_PKO
+                                                      (base_queue + queue),
+                                                      CVMX_PKO_MAX_QUEUE_DEPTH,
+                                                      CVMX_FPA_OUTPUT_BUFFER_POOL,
+                                                      CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE
+                                                      -
+                                                      CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST
+                                                      * 8);
+                        if (cmd_res != CVMX_CMD_QUEUE_SUCCESS) {
+                                switch (cmd_res) {
+                                case CVMX_CMD_QUEUE_NO_MEMORY:
+                                        cvmx_dprintf("ERROR: "
+                                                     "cvmx_pko_config_port: "
+                                                     "Unable to allocate "
+                                                     "output buffer.\n");
+                                        return CVMX_PKO_NO_MEMORY;
+                                case CVMX_CMD_QUEUE_ALREADY_SETUP:
+                                        cvmx_dprintf
+                                            ("ERROR: cvmx_pko_config_port: Port already setup.\n");
+                                        return CVMX_PKO_PORT_ALREADY_SETUP;
+                                case CVMX_CMD_QUEUE_INVALID_PARAM:
+                                default:
+                                        cvmx_dprintf
+                                            ("ERROR: cvmx_pko_config_port: Command queue initialization failed.\n");
+                                        return CVMX_PKO_CMD_QUEUE_INIT_ERROR;
+                                }
+                        }
+
+                        buf_ptr =
+                            (uint64_t *)
+                            cvmx_cmd_queue_buffer(CVMX_CMD_QUEUE_PKO
+                                                  (base_queue + queue));
+                        config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr);
+                } else
+                        config.s.buf_ptr = 0;
+
+                CVMX_SYNCWS;
+
+                if (!OCTEON_IS_MODEL(OCTEON_CN3XXX))
+                        cvmx_write_csr(CVMX_PKO_REG_QUEUE_PTRS1, config1.u64);
+                cvmx_write_csr(CVMX_PKO_MEM_QUEUE_PTRS, config.u64);
+        }
+
+        return result_code;
+}
+
+#ifdef PKO_DEBUG
+/**
+ * Show map of ports -> queues for different cores.
+ */
+void cvmx_pko_show_queue_map()
+{
+        int core, port;
+        int pko_output_ports = 36;
+
+        cvmx_dprintf("port");
+        for (port = 0; port < pko_output_ports; port++)
+                cvmx_dprintf("%3d ", port);
+        cvmx_dprintf("\n");
+
+        for (core = 0; core < CVMX_MAX_CORES; core++) {
+                cvmx_dprintf("\n%2d: ", core);
+                for (port = 0; port < pko_output_ports; port++) {
+                        cvmx_dprintf("%3d ",
+                                     cvmx_pko_get_base_queue_per_core(port,
+                                                                      core));
+                }
+        }
+        cvmx_dprintf("\n");
+}
+#endif
+
+/**
+ * Rate limit a PKO port to a max packets/sec. This function is only
+ * supported on CN51XX and higher, excluding CN58XX.
+ *
+ * @port:      Port to rate limit
+ * @packets_s: Maximum packet/sec
+ * @burst:     Maximum number of packets to burst in a row before rate
+ *                  limiting cuts in.
+ *
+ * Returns Zero on success, negative on failure
+ */
+int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst)
+{
+        union cvmx_pko_mem_port_rate0 pko_mem_port_rate0;
+        union cvmx_pko_mem_port_rate1 pko_mem_port_rate1;
+
+        pko_mem_port_rate0.u64 = 0;
+        pko_mem_port_rate0.s.pid = port;
+        pko_mem_port_rate0.s.rate_pkt =
+            cvmx_sysinfo_get()->cpu_clock_hz / packets_s / 16;
+        /* No cost per word since we are limited by packets/sec, not bits/sec */
+        pko_mem_port_rate0.s.rate_word = 0;
+
+        pko_mem_port_rate1.u64 = 0;
+        pko_mem_port_rate1.s.pid = port;
+        pko_mem_port_rate1.s.rate_lim =
+            ((uint64_t) pko_mem_port_rate0.s.rate_pkt * burst) >> 8;
+
+        cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
+        cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
+        return 0;
+}
+
+/**
+ * Rate limit a PKO port to a max bits/sec. This function is only
+ * supported on CN51XX and higher, excluding CN58XX.
+ *
+ * @port:   Port to rate limit
+ * @bits_s: PKO rate limit in bits/sec
+ * @burst:  Maximum number of bits to burst before rate
+ *               limiting cuts in.
+ *
+ * Returns Zero on success, negative on failure
+ */
+int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst)
+{
+        union cvmx_pko_mem_port_rate0 pko_mem_port_rate0;
+        union cvmx_pko_mem_port_rate1 pko_mem_port_rate1;
+        uint64_t clock_rate = cvmx_sysinfo_get()->cpu_clock_hz;
+        uint64_t tokens_per_bit = clock_rate * 16 / bits_s;
+
+        pko_mem_port_rate0.u64 = 0;
+        pko_mem_port_rate0.s.pid = port;
+        /*
+         * Each packet has a 12 bytes of interframe gap, an 8 byte
+         * preamble, and a 4 byte CRC. These are not included in the
+         * per word count. Multiply by 8 to covert to bits and divide
+         * by 256 for limit granularity.
+         */
+        pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256;
+        /* Each 8 byte word has 64bits */
+        pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit;
+
+        pko_mem_port_rate1.u64 = 0;
+        pko_mem_port_rate1.s.pid = port;
+        pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256;
+
+        cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
+        cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
+        return 0;
+}
diff --git a/drivers/staging/octeon/cvmx-pko.h b/drivers/staging/octeon/cvmx-pko.h
new file mode 100644
index 000000000000..f068c1982497
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-pko.h
@@ -0,0 +1,610 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * Interface to the hardware Packet Output unit.
+ *
+ * Starting with SDK 1.7.0, the PKO output functions now support
+ * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to
+ * function similarly to previous SDKs by using POW atomic tags
+ * to preserve ordering and exclusivity. As a new option, you
+ * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc
+ * memory based locking instead. This locking has the advantage
+ * of not affecting the tag state but doesn't preserve packet
+ * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most
+ * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
+ * with hand tuned fast path code.
+ *
+ * Some of other SDK differences visible to the command command
+ * queuing:
+ * - PKO indexes are no longer stored in the FAU. A large
+ *   percentage of the FAU register block used to be tied up
+ *   maintaining PKO queue pointers. These are now stored in a
+ *   global named block.
+ * - The PKO <b>use_locking</b> parameter can now have a global
+ *   effect. Since all application use the same named block,
+ *   queue locking correctly applies across all operating
+ *   systems when using CVMX_PKO_LOCK_CMD_QUEUE.
+ * - PKO 3 word commands are now supported. Use
+ *   cvmx_pko_send_packet_finish3().
+ *
+ */
+
+#ifndef __CVMX_PKO_H__
+#define __CVMX_PKO_H__
+
+#include "cvmx-fpa.h"
+#include "cvmx-pow.h"
+#include "cvmx-cmd-queue.h"
+#include "cvmx-pko-defs.h"
+
+/* Adjust the command buffer size by 1 word so that in the case of using only
+ * two word PKO commands no command words stradle buffers.  The useful values
+ * for this are 0 and 1. */
+#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
+
+#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
+#define CVMX_PKO_MAX_OUTPUT_QUEUES      ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \
+        OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \
+        OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \
+                (OCTEON_IS_MODEL(OCTEON_CN58XX) || \
+                OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
+#define CVMX_PKO_NUM_OUTPUT_PORTS       40
+/* use this for queues that are not used */
+#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63
+#define CVMX_PKO_QUEUE_STATIC_PRIORITY  9
+#define CVMX_PKO_ILLEGAL_QUEUE  0xFFFF
+#define CVMX_PKO_MAX_QUEUE_DEPTH 0
+
+typedef enum {
+        CVMX_PKO_SUCCESS,
+        CVMX_PKO_INVALID_PORT,
+        CVMX_PKO_INVALID_QUEUE,
+        CVMX_PKO_INVALID_PRIORITY,
+        CVMX_PKO_NO_MEMORY,
+        CVMX_PKO_PORT_ALREADY_SETUP,
+        CVMX_PKO_CMD_QUEUE_INIT_ERROR
+} cvmx_pko_status_t;
+
+/**
+ * This enumeration represents the differnet locking modes supported by PKO.
+ */
+typedef enum {
+        /*
+         * PKO doesn't do any locking. It is the responsibility of the
+         * application to make sure that no other core is accessing
+         * the same queue at the smae time
+         */
+        CVMX_PKO_LOCK_NONE = 0,
+        /*
+         * PKO performs an atomic tagswitch to insure exclusive access
+         * to the output queue. This will maintain packet ordering on
+         * output.
+         */
+        CVMX_PKO_LOCK_ATOMIC_TAG = 1,
+        /*
+         * PKO uses the common command queue locks to insure exclusive
+         * access to the output queue. This is a memory based
+         * ll/sc. This is the most portable locking mechanism.
+         */
+        CVMX_PKO_LOCK_CMD_QUEUE = 2,
+} cvmx_pko_lock_t;
+
+typedef struct {
+        uint32_t packets;
+        uint64_t octets;
+        uint64_t doorbell;
+} cvmx_pko_port_status_t;
+
+/**
+ * This structure defines the address to use on a packet enqueue
+ */
+typedef union {
+        uint64_t u64;
+        struct {
+                /* Must CVMX_IO_SEG */
+                uint64_t mem_space:2;
+                /* Must be zero */
+                uint64_t reserved:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* The ID of the device on the non-coherent bus */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved2:4;
+                /* Must be zero */
+                uint64_t reserved3:18;
+                /*
+                 * The hardware likes to have the output port in
+                 * addition to the output queue,
+                 */
+                uint64_t port:6;
+                /*
+                 * The output queue to send the packet to (0-127 are
+                 * legal)
+                 */
+                uint64_t queue:9;
+                /* Must be zero */
+                uint64_t reserved4:3;
+        } s;
+} cvmx_pko_doorbell_address_t;
+
+/**
+ * Structure of the first packet output command word.
+ */
+typedef union {
+        uint64_t u64;
+        struct {
+                /*
+                 * The size of the reg1 operation - could be 8, 16,
+                 * 32, or 64 bits.
+                 */
+                uint64_t size1:2;
+                /*
+                 * The size of the reg0 operation - could be 8, 16,
+                 * 32, or 64 bits.
+                 */
+                uint64_t size0:2;
+                /*
+                 * If set, subtract 1, if clear, subtract packet
+                 * size.
+                 */
+                uint64_t subone1:1;
+                /*
+                 * The register, subtract will be done if reg1 is
+                 * non-zero.
+                 */
+                uint64_t reg1:11;
+                /* If set, subtract 1, if clear, subtract packet size */
+                uint64_t subone0:1;
+                /* The register, subtract will be done if reg0 is non-zero */
+                uint64_t reg0:11;
+                /*
+                 * When set, interpret segment pointer and segment
+                 * bytes in little endian order.
+                 */
+                uint64_t le:1;
+                /*
+                 * When set, packet data not allocated in L2 cache by
+                 * PKO.
+                 */
+                uint64_t n2:1;
+                /*
+                 * If set and rsp is set, word3 contains a pointer to
+                 * a work queue entry.
+                 */
+                uint64_t wqp:1;
+                /* If set, the hardware will send a response when done */
+                uint64_t rsp:1;
+                /*
+                 * If set, the supplied pkt_ptr is really a pointer to
+                 * a list of pkt_ptr's.
+                 */
+                uint64_t gather:1;
+                /*
+                 * If ipoffp1 is non zero, (ipoffp1-1) is the number
+                 * of bytes to IP header, and the hardware will
+                 * calculate and insert the UDP/TCP checksum.
+                 */
+                uint64_t ipoffp1:7;
+                /*
+                 * If set, ignore the I bit (force to zero) from all
+                 * pointer structures.
+                 */
+                uint64_t ignore_i:1;
+                /*
+                 * If clear, the hardware will attempt to free the
+                 * buffers containing the packet.
+                 */
+                uint64_t dontfree:1;
+                /*
+                 * The total number of segs in the packet, if gather
+                 * set, also gather list length.
+                 */
+                uint64_t segs:6;
+                /* Including L2, but no trailing CRC */
+                uint64_t total_bytes:16;
+        } s;
+} cvmx_pko_command_word0_t;
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Definition of internal state for Packet output processing
+ */
+typedef struct {
+        /* ptr to start of buffer, offset kept in FAU reg */
+        uint64_t *start_ptr;
+} cvmx_pko_state_elem_t;
+
+/**
+ * Call before any other calls to initialize the packet
+ * output system.
+ */
+extern void cvmx_pko_initialize_global(void);
+extern int cvmx_pko_initialize_local(void);
+
+/**
+ * Enables the packet output hardware. It must already be
+ * configured.
+ */
+extern void cvmx_pko_enable(void);
+
+/**
+ * Disables the packet output. Does not affect any configuration.
+ */
+extern void cvmx_pko_disable(void);
+
+/**
+ * Shutdown and free resources required by packet output.
+ */
+
+extern void cvmx_pko_shutdown(void);
+
+/**
+ * Configure a output port and the associated queues for use.
+ *
+ * @port:       Port to configure.
+ * @base_queue: First queue number to associate with this port.
+ * @num_queues: Number of queues t oassociate with this port
+ * @priority:   Array of priority levels for each queue. Values are
+ *                   allowed to be 1-8. A value of 8 get 8 times the traffic
+ *                   of a value of 1. There must be num_queues elements in the
+ *                   array.
+ */
+extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
+                                              uint64_t base_queue,
+                                              uint64_t num_queues,
+                                              const uint64_t priority[]);
+
+/**
+ * Ring the packet output doorbell. This tells the packet
+ * output hardware that "len" command words have been added
+ * to its pending list.  This command includes the required
+ * CVMX_SYNCWS before the doorbell ring.
+ *
+ * @port:   Port the packet is for
+ * @queue:  Queue the packet is for
+ * @len:    Length of the command in 64 bit words
+ */
+static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue,
+                                     uint64_t len)
+{
+        cvmx_pko_doorbell_address_t ptr;
+
+        ptr.u64 = 0;
+        ptr.s.mem_space = CVMX_IO_SEG;
+        ptr.s.did = CVMX_OCT_DID_PKT_SEND;
+        ptr.s.is_io = 1;
+        ptr.s.port = port;
+        ptr.s.queue = queue;
+        /*
+         * Need to make sure output queue data is in DRAM before
+         * doorbell write.
+         */
+        CVMX_SYNCWS;
+        cvmx_write_io(ptr.u64, len);
+}
+
+/**
+ * Prepare to send a packet.  This may initiate a tag switch to
+ * get exclusive access to the output queue structure, and
+ * performs other prep work for the packet send operation.
+ *
+ * cvmx_pko_send_packet_finish() MUST be called after this function is called,
+ * and must be called with the same port/queue/use_locking arguments.
+ *
+ * The use_locking parameter allows the caller to use three
+ * possible locking modes.
+ * - CVMX_PKO_LOCK_NONE
+ *      - PKO doesn't do any locking. It is the responsibility
+ *          of the application to make sure that no other core
+ *          is accessing the same queue at the smae time.
+ * - CVMX_PKO_LOCK_ATOMIC_TAG
+ *      - PKO performs an atomic tagswitch to insure exclusive
+ *          access to the output queue. This will maintain
+ *          packet ordering on output.
+ * - CVMX_PKO_LOCK_CMD_QUEUE
+ *      - PKO uses the common command queue locks to insure
+ *          exclusive access to the output queue. This is a
+ *          memory based ll/sc. This is the most portable
+ *          locking mechanism.
+ *
+ * NOTE: If atomic locking is used, the POW entry CANNOT be
+ * descheduled, as it does not contain a valid WQE pointer.
+ *
+ * @port:   Port to send it on
+ * @queue:  Queue to use
+ * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
+ *               CVMX_PKO_LOCK_CMD_QUEUE
+ */
+
+static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
+                                                cvmx_pko_lock_t use_locking)
+{
+        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) {
+                /*
+                 * Must do a full switch here to handle all cases.  We
+                 * use a fake WQE pointer, as the POW does not access
+                 * this memory.  The WQE pointer and group are only
+                 * used if this work is descheduled, which is not
+                 * supported by the
+                 * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish
+                 * combination.  Note that this is a special case in
+                 * which these fake values can be used - this is not a
+                 * general technique.
+                 */
+                uint32_t tag =
+                    CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT |
+                    CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT |
+                    (CVMX_TAG_SUBGROUP_MASK & queue);
+                cvmx_pow_tag_sw_full((cvmx_wqe_t *) cvmx_phys_to_ptr(0x80), tag,
+                                     CVMX_POW_TAG_TYPE_ATOMIC, 0);
+        }
+}
+
+/**
+ * Complete packet output. cvmx_pko_send_packet_prepare() must be
+ * called exactly once before this, and the same parameters must be
+ * passed to both cvmx_pko_send_packet_prepare() and
+ * cvmx_pko_send_packet_finish().
+ *
+ * @port:   Port to send it on
+ * @queue:  Queue to use
+ * @pko_command:
+ *               PKO HW command word
+ * @packet: Packet to send
+ * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
+ *               CVMX_PKO_LOCK_CMD_QUEUE
+ *
+ * Returns returns CVMX_PKO_SUCCESS on success, or error code on
+ * failure of output
+ */
+static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
+        uint64_t port,
+        uint64_t queue,
+        cvmx_pko_command_word0_t pko_command,
+        union cvmx_buf_ptr packet,
+        cvmx_pko_lock_t use_locking)
+{
+        cvmx_cmd_queue_result_t result;
+        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
+                cvmx_pow_tag_sw_wait();
+        result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
+                                       (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
+                                       pko_command.u64, packet.u64);
+        if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
+                cvmx_pko_doorbell(port, queue, 2);
+                return CVMX_PKO_SUCCESS;
+        } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
+                   || (result == CVMX_CMD_QUEUE_FULL)) {
+                return CVMX_PKO_NO_MEMORY;
+        } else {
+                return CVMX_PKO_INVALID_QUEUE;
+        }
+}
+
+/**
+ * Complete packet output. cvmx_pko_send_packet_prepare() must be
+ * called exactly once before this, and the same parameters must be
+ * passed to both cvmx_pko_send_packet_prepare() and
+ * cvmx_pko_send_packet_finish().
+ *
+ * @port:   Port to send it on
+ * @queue:  Queue to use
+ * @pko_command:
+ *               PKO HW command word
+ * @packet: Packet to send
+ * @addr: Plysical address of a work queue entry or physical address
+ *        to zero on complete.
+ * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
+ *               CVMX_PKO_LOCK_CMD_QUEUE
+ *
+ * Returns returns CVMX_PKO_SUCCESS on success, or error code on
+ * failure of output
+ */
+static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(
+        uint64_t port,
+        uint64_t queue,
+        cvmx_pko_command_word0_t pko_command,
+        union cvmx_buf_ptr packet,
+        uint64_t addr,
+        cvmx_pko_lock_t use_locking)
+{
+        cvmx_cmd_queue_result_t result;
+        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
+                cvmx_pow_tag_sw_wait();
+        result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
+                                       (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
+                                       pko_command.u64, packet.u64, addr);
+        if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
+                cvmx_pko_doorbell(port, queue, 3);
+                return CVMX_PKO_SUCCESS;
+        } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
+                   || (result == CVMX_CMD_QUEUE_FULL)) {
+                return CVMX_PKO_NO_MEMORY;
+        } else {
+                return CVMX_PKO_INVALID_QUEUE;
+        }
+}
+
+/**
+ * Return the pko output queue associated with a port and a specific core.
+ * In normal mode (PKO lockless operation is disabled), the value returned
+ * is the base queue.
+ *
+ * @port:   Port number
+ * @core:   Core to get queue for
+ *
+ * Returns Core-specific output queue
+ */
+static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
+{
+#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
+#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
+#endif
+#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
+#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
+#endif
+
+        if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
+                return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
+        else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
+                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port -
+                                                           16) *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core;
+        else if ((port >= 32) && (port < 36))
+                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
+                    CVMX_PKO_MAX_PORTS_INTERFACE1 *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port -
+                                                           32) *
+                    CVMX_PKO_QUEUES_PER_PORT_PCI;
+        else if ((port >= 36) && (port < 40))
+                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
+                    CVMX_PKO_MAX_PORTS_INTERFACE1 *
+                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
+                    4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port -
+                                                        36) *
+                    CVMX_PKO_QUEUES_PER_PORT_LOOP;
+        else
+                /* Given the limit on the number of ports we can map to
+                 * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
+                 * divided among all cores), the remaining unmapped ports
+                 * are assigned an illegal queue number */
+                return CVMX_PKO_ILLEGAL_QUEUE;
+}
+
+/**
+ * For a given port number, return the base pko output queue
+ * for the port.
+ *
+ * @port:   Port number
+ * Returns Base output queue
+ */
+static inline int cvmx_pko_get_base_queue(int port)
+{
+        return cvmx_pko_get_base_queue_per_core(port, 0);
+}
+
+/**
+ * For a given port number, return the number of pko output queues.
+ *
+ * @port:   Port number
+ * Returns Number of output queues
+ */
+static inline int cvmx_pko_get_num_queues(int port)
+{
+        if (port < 16)
+                return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
+        else if (port < 32)
+                return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
+        else if (port < 36)
+                return CVMX_PKO_QUEUES_PER_PORT_PCI;
+        else if (port < 40)
+                return CVMX_PKO_QUEUES_PER_PORT_LOOP;
+        else
+                return 0;
+}
+
+/**
+ * Get the status counters for a port.
+ *
+ * @port_num: Port number to get statistics for.
+ * @clear:    Set to 1 to clear the counters after they are read
+ * @status:   Where to put the results.
+ */
+static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
+                                            cvmx_pko_port_status_t *status)
+{
+        union cvmx_pko_reg_read_idx pko_reg_read_idx;
+        union cvmx_pko_mem_count0 pko_mem_count0;
+        union cvmx_pko_mem_count1 pko_mem_count1;
+
+        pko_reg_read_idx.u64 = 0;
+        pko_reg_read_idx.s.index = port_num;
+        cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
+
+        pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
+        status->packets = pko_mem_count0.s.count;
+        if (clear) {
+                pko_mem_count0.s.count = port_num;
+                cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
+        }
+
+        pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
+        status->octets = pko_mem_count1.s.count;
+        if (clear) {
+                pko_mem_count1.s.count = port_num;
+                cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
+        }
+
+        if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+                union cvmx_pko_mem_debug9 debug9;
+                pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
+                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
+                debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
+                status->doorbell = debug9.cn38xx.doorbell;
+        } else {
+                union cvmx_pko_mem_debug8 debug8;
+                pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
+                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
+                debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
+                status->doorbell = debug8.cn58xx.doorbell;
+        }
+}
+
+/**
+ * Rate limit a PKO port to a max packets/sec. This function is only
+ * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
+ *
+ * @port:      Port to rate limit
+ * @packets_s: Maximum packet/sec
+ * @burst:     Maximum number of packets to burst in a row before rate
+ *                  limiting cuts in.
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
+
+/**
+ * Rate limit a PKO port to a max bits/sec. This function is only
+ * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
+ *
+ * @port:   Port to rate limit
+ * @bits_s: PKO rate limit in bits/sec
+ * @burst:  Maximum number of bits to burst before rate
+ *               limiting cuts in.
+ *
+ * Returns Zero on success, negative on failure
+ */
+extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
+
+#endif /* __CVMX_PKO_H__ */
diff --git a/drivers/staging/octeon/cvmx-pow.h b/drivers/staging/octeon/cvmx-pow.h
new file mode 100644
index 000000000000..c5d66f272b0d
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-pow.h
@@ -0,0 +1,1982 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ * Interface to the hardware Packet Order / Work unit.
+ *
+ * New, starting with SDK 1.7.0, cvmx-pow supports a number of
+ * extended consistency checks. The define
+ * CVMX_ENABLE_POW_CHECKS controls the runtime insertion of POW
+ * internal state checks to find common programming errors. If
+ * CVMX_ENABLE_POW_CHECKS is not defined, checks are by default
+ * enabled. For example, cvmx-pow will check for the following
+ * program errors or POW state inconsistency.
+ * - Requesting a POW operation with an active tag switch in
+ *   progress.
+ * - Waiting for a tag switch to complete for an excessively
+ *   long period. This is normally a sign of an error in locking
+ *   causing deadlock.
+ * - Illegal tag switches from NULL_NULL.
+ * - Illegal tag switches from NULL.
+ * - Illegal deschedule request.
+ * - WQE pointer not matching the one attached to the core by
+ *   the POW.
+ *
+ */
+
+#ifndef __CVMX_POW_H__
+#define __CVMX_POW_H__
+
+#include <asm/octeon/cvmx-pow-defs.h>
+
+#include "cvmx-scratch.h"
+#include "cvmx-wqe.h"
+
+/* Default to having all POW constancy checks turned on */
+#ifndef CVMX_ENABLE_POW_CHECKS
+#define CVMX_ENABLE_POW_CHECKS 1
+#endif
+
+enum cvmx_pow_tag_type {
+        /* Tag ordering is maintained */
+        CVMX_POW_TAG_TYPE_ORDERED   = 0L,
+        /* Tag ordering is maintained, and at most one PP has the tag */
+        CVMX_POW_TAG_TYPE_ATOMIC    = 1L,
+        /*
+         * The work queue entry from the order - NEVER tag switch from
+         * NULL to NULL
+         */
+        CVMX_POW_TAG_TYPE_NULL      = 2L,
+        /* A tag switch to NULL, and there is no space reserved in POW
+         * - NEVER tag switch to NULL_NULL
+         * - NEVER tag switch from NULL_NULL
+         * - NULL_NULL is entered at the beginning of time and on a deschedule.
+         * - NULL_NULL can be exited by a new work request. A NULL_SWITCH
+         * load can also switch the state to NULL
+         */
+        CVMX_POW_TAG_TYPE_NULL_NULL = 3L
+};
+
+/**
+ * Wait flag values for pow functions.
+ */
+typedef enum {
+        CVMX_POW_WAIT = 1,
+        CVMX_POW_NO_WAIT = 0,
+} cvmx_pow_wait_t;
+
+/**
+ *  POW tag operations.  These are used in the data stored to the POW.
+ */
+typedef enum {
+        /*
+         * switch the tag (only) for this PP
+         * - the previous tag should be non-NULL in this case
+         * - tag switch response required
+         * - fields used: op, type, tag
+         */
+        CVMX_POW_TAG_OP_SWTAG = 0L,
+        /*
+         * switch the tag for this PP, with full information
+         * - this should be used when the previous tag is NULL
+         * - tag switch response required
+         * - fields used: address, op, grp, type, tag
+         */
+        CVMX_POW_TAG_OP_SWTAG_FULL = 1L,
+        /*
+         * switch the tag (and/or group) for this PP and de-schedule
+         * - OK to keep the tag the same and only change the group
+         * - fields used: op, no_sched, grp, type, tag
+         */
+        CVMX_POW_TAG_OP_SWTAG_DESCH = 2L,
+        /*
+         * just de-schedule
+         * - fields used: op, no_sched
+         */
+        CVMX_POW_TAG_OP_DESCH = 3L,
+        /*
+         * create an entirely new work queue entry
+         * - fields used: address, op, qos, grp, type, tag
+         */
+        CVMX_POW_TAG_OP_ADDWQ = 4L,
+        /*
+         * just update the work queue pointer and grp for this PP
+         * - fields used: address, op, grp
+         */
+        CVMX_POW_TAG_OP_UPDATE_WQP_GRP = 5L,
+        /*
+         * set the no_sched bit on the de-schedule list
+         *
+         * - does nothing if the selected entry is not on the
+         *   de-schedule list
+         *
+         * - does nothing if the stored work queue pointer does not
+         *   match the address field
+         *
+         * - fields used: address, index, op
+         *
+         *  Before issuing a *_NSCHED operation, SW must guarantee
+         *  that all prior deschedules and set/clr NSCHED operations
+         *  are complete and all prior switches are complete. The
+         *  hardware provides the opsdone bit and swdone bit for SW
+         *  polling. After issuing a *_NSCHED operation, SW must
+         *  guarantee that the set/clr NSCHED is complete before any
+         *  subsequent operations.
+         */
+        CVMX_POW_TAG_OP_SET_NSCHED = 6L,
+        /*
+         * clears the no_sched bit on the de-schedule list
+         *
+         * - does nothing if the selected entry is not on the
+         *   de-schedule list
+         *
+         * - does nothing if the stored work queue pointer does not
+         *   match the address field
+         *
+         * - fields used: address, index, op
+         *
+         * Before issuing a *_NSCHED operation, SW must guarantee that
+         * all prior deschedules and set/clr NSCHED operations are
+         * complete and all prior switches are complete. The hardware
+         * provides the opsdone bit and swdone bit for SW
+         * polling. After issuing a *_NSCHED operation, SW must
+         * guarantee that the set/clr NSCHED is complete before any
+         * subsequent operations.
+         */
+        CVMX_POW_TAG_OP_CLR_NSCHED = 7L,
+        /* do nothing */
+        CVMX_POW_TAG_OP_NOP = 15L
+} cvmx_pow_tag_op_t;
+
+/**
+ * This structure defines the store data on a store to POW
+ */
+typedef union {
+        uint64_t u64;
+        struct {
+                /*
+                 * Don't reschedule this entry. no_sched is used for
+                 * CVMX_POW_TAG_OP_SWTAG_DESCH and
+                 * CVMX_POW_TAG_OP_DESCH
+                 */
+                uint64_t no_sched:1;
+                uint64_t unused:2;
+                /* Tontains index of entry for a CVMX_POW_TAG_OP_*_NSCHED */
+                uint64_t index:13;
+                /* The operation to perform */
+                cvmx_pow_tag_op_t op:4;
+                uint64_t unused2:2;
+                /*
+                 * The QOS level for the packet. qos is only used for
+                 * CVMX_POW_TAG_OP_ADDWQ
+                 */
+                uint64_t qos:3;
+                /*
+                 * The group that the work queue entry will be
+                 * scheduled to grp is used for CVMX_POW_TAG_OP_ADDWQ,
+                 * CVMX_POW_TAG_OP_SWTAG_FULL,
+                 * CVMX_POW_TAG_OP_SWTAG_DESCH, and
+                 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP
+                 */
+                uint64_t grp:4;
+                /*
+                 * The type of the tag. type is used for everything
+                 * except CVMX_POW_TAG_OP_DESCH,
+                 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
+                 * CVMX_POW_TAG_OP_*_NSCHED
+                 */
+                uint64_t type:3;
+                /*
+                 * The actual tag. tag is used for everything except
+                 * CVMX_POW_TAG_OP_DESCH,
+                 * CVMX_POW_TAG_OP_UPDATE_WQP_GRP, and
+                 * CVMX_POW_TAG_OP_*_NSCHED
+                 */
+                uint64_t tag:32;
+        } s;
+} cvmx_pow_tag_req_t;
+
+/**
+ * This structure describes the address to load stuff from POW
+ */
+typedef union {
+        uint64_t u64;
+
+    /**
+     * Address for new work request loads (did<2:0> == 0)
+     */
+        struct {
+                /* Mips64 address region. Should be CVMX_IO_SEG */
+                uint64_t mem_region:2;
+                /* Must be zero */
+                uint64_t reserved_49_61:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* the ID of POW -- did<2:0> == 0 in this case */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved_4_39:36;
+                /*
+                 * If set, don't return load response until work is
+                 * available.
+                 */
+                uint64_t wait:1;
+                /* Must be zero */
+                uint64_t reserved_0_2:3;
+        } swork;
+
+    /**
+     * Address for loads to get POW internal status
+     */
+        struct {
+                /* Mips64 address region. Should be CVMX_IO_SEG */
+                uint64_t mem_region:2;
+                /* Must be zero */
+                uint64_t reserved_49_61:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* the ID of POW -- did<2:0> == 1 in this case */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved_10_39:30;
+                /* The core id to get status for */
+                uint64_t coreid:4;
+                /*
+                 * If set and get_cur is set, return reverse tag-list
+                 * pointer rather than forward tag-list pointer.
+                 */
+                uint64_t get_rev:1;
+                /*
+                 * If set, return current status rather than pending
+                 * status.
+                 */
+                uint64_t get_cur:1;
+                /*
+                 * If set, get the work-queue pointer rather than
+                 * tag/type.
+                 */
+                uint64_t get_wqp:1;
+                /* Must be zero */
+                uint64_t reserved_0_2:3;
+        } sstatus;
+
+    /**
+     * Address for memory loads to get POW internal state
+     */
+        struct {
+                /* Mips64 address region. Should be CVMX_IO_SEG */
+                uint64_t mem_region:2;
+                /* Must be zero */
+                uint64_t reserved_49_61:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* the ID of POW -- did<2:0> == 2 in this case */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved_16_39:24;
+                /* POW memory index */
+                uint64_t index:11;
+                /*
+                 * If set, return deschedule information rather than
+                 * the standard response for work-queue index (invalid
+                 * if the work-queue entry is not on the deschedule
+                 * list).
+                 */
+                uint64_t get_des:1;
+                /*
+                 * If set, get the work-queue pointer rather than
+                 * tag/type (no effect when get_des set).
+                 */
+                uint64_t get_wqp:1;
+                /* Must be zero */
+                uint64_t reserved_0_2:3;
+        } smemload;
+
+    /**
+     * Address for index/pointer loads
+     */
+        struct {
+                /* Mips64 address region. Should be CVMX_IO_SEG */
+                uint64_t mem_region:2;
+                /* Must be zero */
+                uint64_t reserved_49_61:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* the ID of POW -- did<2:0> == 3 in this case */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved_9_39:31;
+                /*
+                 * when {get_rmt ==0 AND get_des_get_tail == 0}, this
+                 * field selects one of eight POW internal-input
+                 * queues (0-7), one per QOS level; values 8-15 are
+                 * illegal in this case; when {get_rmt ==0 AND
+                 * get_des_get_tail == 1}, this field selects one of
+                 * 16 deschedule lists (per group); when get_rmt ==1,
+                 * this field selects one of 16 memory-input queue
+                 * lists.  The two memory-input queue lists associated
+                 * with each QOS level are:
+                 *
+                 * - qosgrp = 0, qosgrp = 8:      QOS0
+                 * - qosgrp = 1, qosgrp = 9:      QOS1
+                 * - qosgrp = 2, qosgrp = 10:     QOS2
+                 * - qosgrp = 3, qosgrp = 11:     QOS3
+                 * - qosgrp = 4, qosgrp = 12:     QOS4
+                 * - qosgrp = 5, qosgrp = 13:     QOS5
+                 * - qosgrp = 6, qosgrp = 14:     QOS6
+                 * - qosgrp = 7, qosgrp = 15:     QOS7
+                 */
+                uint64_t qosgrp:4;
+                /*
+                 * If set and get_rmt is clear, return deschedule list
+                 * indexes rather than indexes for the specified qos
+                 * level; if set and get_rmt is set, return the tail
+                 * pointer rather than the head pointer for the
+                 * specified qos level.
+                 */
+                uint64_t get_des_get_tail:1;
+                /*
+                 * If set, return remote pointers rather than the
+                 * local indexes for the specified qos level.
+                 */
+                uint64_t get_rmt:1;
+                /* Must be zero */
+                uint64_t reserved_0_2:3;
+        } sindexload;
+
+    /**
+     * address for NULL_RD request (did<2:0> == 4) when this is read,
+     * HW attempts to change the state to NULL if it is NULL_NULL (the
+     * hardware cannot switch from NULL_NULL to NULL if a POW entry is
+     * not available - software may need to recover by finishing
+     * another piece of work before a POW entry can ever become
+     * available.)
+     */
+        struct {
+                /* Mips64 address region. Should be CVMX_IO_SEG */
+                uint64_t mem_region:2;
+                /* Must be zero */
+                uint64_t reserved_49_61:13;
+                /* Must be one */
+                uint64_t is_io:1;
+                /* the ID of POW -- did<2:0> == 4 in this case */
+                uint64_t did:8;
+                /* Must be zero */
+                uint64_t reserved_0_39:40;
+        } snull_rd;
+} cvmx_pow_load_addr_t;
+
+/**
+ * This structure defines the response to a load/SENDSINGLE to POW
+ * (except CSR reads)
+ */
+typedef union {
+        uint64_t u64;
+
+    /**
+     * Response to new work request loads
+     */
+        struct {
+                /*
+                 * Set when no new work queue entry was returned.  *
+                 * If there was de-scheduled work, the HW will
+                 * definitely return it. When this bit is set, it
+                 * could mean either mean:
+                 *
+                 * - There was no work, or
+                 *
+                 * - There was no work that the HW could find. This
+                 *   case can happen, regardless of the wait bit value
+                 *   in the original request, when there is work in
+                 *   the IQ's that is too deep down the list.
+                 */
+                uint64_t no_work:1;
+                /* Must be zero */
+                uint64_t reserved_40_62:23;
+                /* 36 in O1 -- the work queue pointer */
+                uint64_t addr:40;
+        } s_work;
+
+    /**
+     * Result for a POW Status Load (when get_cur==0 and get_wqp==0)
+     */
+        struct {
+                uint64_t reserved_62_63:2;
+                /* Set when there is a pending non-NULL SWTAG or
+                 * SWTAG_FULL, and the POW entry has not left the list
+                 * for the original tag. */
+                uint64_t pend_switch:1;
+                /* Set when SWTAG_FULL and pend_switch is set. */
+                uint64_t pend_switch_full:1;
+                /*
+                 * Set when there is a pending NULL SWTAG, or an
+                 * implicit switch to NULL.
+                 */
+                uint64_t pend_switch_null:1;
+                /* Set when there is a pending DESCHED or SWTAG_DESCHED. */
+                uint64_t pend_desched:1;
+                /*
+                 * Set when there is a pending SWTAG_DESCHED and
+                 * pend_desched is set.
+                 */
+                uint64_t pend_desched_switch:1;
+                /* Set when nosched is desired and pend_desched is set. */
+                uint64_t pend_nosched:1;
+                /* Set when there is a pending GET_WORK. */
+                uint64_t pend_new_work:1;
+                /*
+                 * When pend_new_work is set, this bit indicates that
+                 * the wait bit was set.
+                 */
+                uint64_t pend_new_work_wait:1;
+                /* Set when there is a pending NULL_RD. */
+                uint64_t pend_null_rd:1;
+                /* Set when there is a pending CLR_NSCHED. */
+                uint64_t pend_nosched_clr:1;
+                uint64_t reserved_51:1;
+                /* This is the index when pend_nosched_clr is set. */
+                uint64_t pend_index:11;
+                /*
+                 * This is the new_grp when (pend_desched AND
+                 * pend_desched_switch) is set.
+                 */
+                uint64_t pend_grp:4;
+                uint64_t reserved_34_35:2;
+                /*
+                 * This is the tag type when pend_switch or
+                 * (pend_desched AND pend_desched_switch) are set.
+                 */
+                uint64_t pend_type:2;
+                /*
+                 * - this is the tag when pend_switch or (pend_desched
+                 *    AND pend_desched_switch) are set.
+                 */
+                uint64_t pend_tag:32;
+        } s_sstatus0;
+
+    /**
+     * Result for a POW Status Load (when get_cur==0 and get_wqp==1)
+     */
+        struct {
+                uint64_t reserved_62_63:2;
+                /*
+                 * Set when there is a pending non-NULL SWTAG or
+                 * SWTAG_FULL, and the POW entry has not left the list
+                 * for the original tag.
+                 */
+                uint64_t pend_switch:1;
+                /* Set when SWTAG_FULL and pend_switch is set. */
+                uint64_t pend_switch_full:1;
+                /*
+                 * Set when there is a pending NULL SWTAG, or an
+                 * implicit switch to NULL.
+                 */
+                uint64_t pend_switch_null:1;
+                /*
+                 * Set when there is a pending DESCHED or
+                 * SWTAG_DESCHED.
+                 */
+                uint64_t pend_desched:1;
+                /*
+                 * Set when there is a pending SWTAG_DESCHED and
+                 * pend_desched is set.
+                 */
+                uint64_t pend_desched_switch:1;
+                /* Set when nosched is desired and pend_desched is set. */
+                uint64_t pend_nosched:1;
+                /* Set when there is a pending GET_WORK. */
+                uint64_t pend_new_work:1;
+                /*
+                 * When pend_new_work is set, this bit indicates that
+                 * the wait bit was set.
+                 */
+                uint64_t pend_new_work_wait:1;
+                /* Set when there is a pending NULL_RD. */
+                uint64_t pend_null_rd:1;
+                /* Set when there is a pending CLR_NSCHED. */
+                uint64_t pend_nosched_clr:1;
+                uint64_t reserved_51:1;
+                /* This is the index when pend_nosched_clr is set. */
+                uint64_t pend_index:11;
+                /*
+                 * This is the new_grp when (pend_desched AND
+                 * pend_desched_switch) is set.
+                 */
+                uint64_t pend_grp:4;
+                /* This is the wqp when pend_nosched_clr is set. */
+                uint64_t pend_wqp:36;
+        } s_sstatus1;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==0, and
+     * get_rev==0)
+     */
+        struct {
+                uint64_t reserved_62_63:2;
+                /*
+                 * Points to the next POW entry in the tag list when
+                 * tail == 0 (and tag_type is not NULL or NULL_NULL).
+                 */
+                uint64_t link_index:11;
+                /* The POW entry attached to the core. */
+                uint64_t index:11;
+                /*
+                 * The group attached to the core (updated when new
+                 * tag list entered on SWTAG_FULL).
+                 */
+                uint64_t grp:4;
+                /*
+                 * Set when this POW entry is at the head of its tag
+                 * list (also set when in the NULL or NULL_NULL
+                 * state).
+                 */
+                uint64_t head:1;
+                /*
+                 * Set when this POW entry is at the tail of its tag
+                 * list (also set when in the NULL or NULL_NULL
+                 * state).
+                 */
+                uint64_t tail:1;
+                /*
+                 * The tag type attached to the core (updated when new
+                 * tag list entered on SWTAG, SWTAG_FULL, or
+                 * SWTAG_DESCHED).
+                 */
+                uint64_t tag_type:2;
+                /*
+                 * The tag attached to the core (updated when new tag
+                 * list entered on SWTAG, SWTAG_FULL, or
+                 * SWTAG_DESCHED).
+                 */
+                uint64_t tag:32;
+        } s_sstatus2;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==0, and get_rev==1)
+     */
+        struct {
+                uint64_t reserved_62_63:2;
+                /*
+                 * Points to the prior POW entry in the tag list when
+                 * head == 0 (and tag_type is not NULL or
+                 * NULL_NULL). This field is unpredictable when the
+                 * core's state is NULL or NULL_NULL.
+                 */
+                uint64_t revlink_index:11;
+                /* The POW entry attached to the core. */
+                uint64_t index:11;
+                /*
+                 * The group attached to the core (updated when new
+                 * tag list entered on SWTAG_FULL).
+                 */
+                uint64_t grp:4;
+                /* Set when this POW entry is at the head of its tag
+                 * list (also set when in the NULL or NULL_NULL
+                 * state).
+                 */
+                uint64_t head:1;
+                /*
+                 * Set when this POW entry is at the tail of its tag
+                 * list (also set when in the NULL or NULL_NULL
+                 * state).
+                 */
+                uint64_t tail:1;
+                /*
+                 * The tag type attached to the core (updated when new
+                 * tag list entered on SWTAG, SWTAG_FULL, or
+                 * SWTAG_DESCHED).
+                 */
+                uint64_t tag_type:2;
+                /*
+                 * The tag attached to the core (updated when new tag
+                 * list entered on SWTAG, SWTAG_FULL, or
+                 * SWTAG_DESCHED).
+                 */
+                uint64_t tag:32;
+        } s_sstatus3;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==1, and
+     * get_rev==0)
+     */
+        struct {
+                uint64_t reserved_62_63:2;
+                /*
+                 * Points to the next POW entry in the tag list when
+                 * tail == 0 (and tag_type is not NULL or NULL_NULL).
+                 */
+                uint64_t link_index:11;
+                /* The POW entry attached to the core. */
+                uint64_t index:11;
+                /*
+                 * The group attached to the core (updated when new
+                 * tag list entered on SWTAG_FULL).
+                 */
+                uint64_t grp:4;
+                /*
+                 * The wqp attached to the core (updated when new tag
+                 * list entered on SWTAG_FULL).
+                 */
+                uint64_t wqp:36;
+        } s_sstatus4;
+
+    /**
+     * Result for a POW Status Load (when get_cur==1, get_wqp==1, and
+     * get_rev==1)
+     */
+        struct {
+                uint64_t reserved_62_63:2;
+                /*
+                 * Points to the prior POW entry in the tag list when
+                 * head == 0 (and tag_type is not NULL or
+                 * NULL_NULL). This field is unpredictable when the
+                 * core's state is NULL or NULL_NULL.
+                 */
+                uint64_t revlink_index:11;
+                /* The POW entry attached to the core. */
+                uint64_t index:11;
+                /*
+                 * The group attached to the core (updated when new
+                 * tag list entered on SWTAG_FULL).
+                 */
+                uint64_t grp:4;
+                /*
+                 * The wqp attached to the core (updated when new tag
+                 * list entered on SWTAG_FULL).
+                 */
+                uint64_t wqp:36;
+        } s_sstatus5;
+
+    /**
+     * Result For POW Memory Load (get_des == 0 and get_wqp == 0)
+     */
+        struct {
+                uint64_t reserved_51_63:13;
+                /*
+                 * The next entry in the input, free, descheduled_head
+                 * list (unpredictable if entry is the tail of the
+                 * list).
+                 */
+                uint64_t next_index:11;
+                /* The group of the POW entry. */
+                uint64_t grp:4;
+                uint64_t reserved_35:1;
+                /*
+                 * Set when this POW entry is at the tail of its tag
+                 * list (also set when in the NULL or NULL_NULL
+                 * state).
+                 */
+                uint64_t tail:1;
+                /* The tag type of the POW entry. */
+                uint64_t tag_type:2;
+                /* The tag of the POW entry. */
+                uint64_t tag:32;
+        } s_smemload0;
+
+    /**
+     * Result For POW Memory Load (get_des == 0 and get_wqp == 1)
+     */
+        struct {
+                uint64_t reserved_51_63:13;
+                /*
+                 * The next entry in the input, free, descheduled_head
+                 * list (unpredictable if entry is the tail of the
+                 * list).
+                 */
+                uint64_t next_index:11;
+                /* The group of the POW entry. */
+                uint64_t grp:4;
+                /* The WQP held in the POW entry. */
+                uint64_t wqp:36;
+        } s_smemload1;
+
+    /**
+     * Result For POW Memory Load (get_des == 1)
+     */
+        struct {
+                uint64_t reserved_51_63:13;
+                /*
+                 * The next entry in the tag list connected to the
+                 * descheduled head.
+                 */
+                uint64_t fwd_index:11;
+                /* The group of the POW entry. */
+                uint64_t grp:4;
+                /* The nosched bit for the POW entry. */
+                uint64_t nosched:1;
+                /* There is a pending tag switch */
+                uint64_t pend_switch:1;
+                /*
+                 * The next tag type for the new tag list when
+                 * pend_switch is set.
+                 */
+                uint64_t pend_type:2;
+                /*
+                 * The next tag for the new tag list when pend_switch
+                 * is set.
+                 */
+                uint64_t pend_tag:32;
+        } s_smemload2;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 0)
+     */
+        struct {
+                uint64_t reserved_52_63:12;
+                /*
+                 * set when there is one or more POW entries on the
+                 * free list.
+                 */
+                uint64_t free_val:1;
+                /*
+                 * set when there is exactly one POW entry on the free
+                 * list.
+                 */
+                uint64_t free_one:1;
+                uint64_t reserved_49:1;
+                /*
+                 * when free_val is set, indicates the first entry on
+                 * the free list.
+                 */
+                uint64_t free_head:11;
+                uint64_t reserved_37:1;
+                /*
+                 * when free_val is set, indicates the last entry on
+                 * the free list.
+                 */
+                uint64_t free_tail:11;
+                /*
+                 * set when there is one or more POW entries on the
+                 * input Q list selected by qosgrp.
+                 */
+                uint64_t loc_val:1;
+                /*
+                 * set when there is exactly one POW entry on the
+                 * input Q list selected by qosgrp.
+                 */
+                uint64_t loc_one:1;
+                uint64_t reserved_23:1;
+                /*
+                 * when loc_val is set, indicates the first entry on
+                 * the input Q list selected by qosgrp.
+                 */
+                uint64_t loc_head:11;
+                uint64_t reserved_11:1;
+                /*
+                 * when loc_val is set, indicates the last entry on
+                 * the input Q list selected by qosgrp.
+                 */
+                uint64_t loc_tail:11;
+        } sindexload0;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt == 0/get_des_get_tail == 1)
+     */
+        struct {
+                uint64_t reserved_52_63:12;
+                /*
+                 * set when there is one or more POW entries on the
+                 * nosched list.
+                 */
+                uint64_t nosched_val:1;
+                /*
+                 * set when there is exactly one POW entry on the
+                 * nosched list.
+                 */
+                uint64_t nosched_one:1;
+                uint64_t reserved_49:1;
+                /*
+                 * when nosched_val is set, indicates the first entry
+                 * on the nosched list.
+                 */
+                uint64_t nosched_head:11;
+                uint64_t reserved_37:1;
+                /*
+                 * when nosched_val is set, indicates the last entry
+                 * on the nosched list.
+                 */
+                uint64_t nosched_tail:11;
+                /*
+                 * set when there is one or more descheduled heads on
+                 * the descheduled list selected by qosgrp.
+                 */
+                uint64_t des_val:1;
+                /*
+                 * set when there is exactly one descheduled head on
+                 * the descheduled list selected by qosgrp.
+                 */
+                uint64_t des_one:1;
+                uint64_t reserved_23:1;
+                /*
+                 * when des_val is set, indicates the first
+                 * descheduled head on the descheduled list selected
+                 * by qosgrp.
+                 */
+                uint64_t des_head:11;
+                uint64_t reserved_11:1;
+                /*
+                 * when des_val is set, indicates the last descheduled
+                 * head on the descheduled list selected by qosgrp.
+                 */
+                uint64_t des_tail:11;
+        } sindexload1;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt == 1/get_des_get_tail == 0)
+     */
+        struct {
+                uint64_t reserved_39_63:25;
+                /*
+                 * Set when this DRAM list is the current head
+                 * (i.e. is the next to be reloaded when the POW
+                 * hardware reloads a POW entry from DRAM). The POW
+                 * hardware alternates between the two DRAM lists
+                 * associated with a QOS level when it reloads work
+                 * from DRAM into the POW unit.
+                 */
+                uint64_t rmt_is_head:1;
+                /*
+                 * Set when the DRAM portion of the input Q list
+                 * selected by qosgrp contains one or more pieces of
+                 * work.
+                 */
+                uint64_t rmt_val:1;
+                /*
+                 * Set when the DRAM portion of the input Q list
+                 * selected by qosgrp contains exactly one piece of
+                 * work.
+                 */
+                uint64_t rmt_one:1;
+                /*
+                 * When rmt_val is set, indicates the first piece of
+                 * work on the DRAM input Q list selected by
+                 * qosgrp.
+                 */
+                uint64_t rmt_head:36;
+        } sindexload2;
+
+    /**
+     * Result For POW Index/Pointer Load (get_rmt ==
+     * 1/get_des_get_tail == 1)
+     */
+        struct {
+                uint64_t reserved_39_63:25;
+                /*
+                 * set when this DRAM list is the current head
+                 * (i.e. is the next to be reloaded when the POW
+                 * hardware reloads a POW entry from DRAM). The POW
+                 * hardware alternates between the two DRAM lists
+                 * associated with a QOS level when it reloads work
+                 * from DRAM into the POW unit.
+                 */
+                uint64_t rmt_is_head:1;
+                /*
+                 * set when the DRAM portion of the input Q list
+                 * selected by qosgrp contains one or more pieces of
+                 * work.
+                 */
+                uint64_t rmt_val:1;
+                /*
+                 * set when the DRAM portion of the input Q list
+                 * selected by qosgrp contains exactly one piece of
+                 * work.
+                 */
+                uint64_t rmt_one:1;
+                /*
+                 * when rmt_val is set, indicates the last piece of
+                 * work on the DRAM input Q list selected by
+                 * qosgrp.
+                 */
+                uint64_t rmt_tail:36;
+        } sindexload3;
+
+    /**
+     * Response to NULL_RD request loads
+     */
+        struct {
+                uint64_t unused:62;
+                /* of type cvmx_pow_tag_type_t. state is one of the
+                 * following:
+                 *
+                 * - CVMX_POW_TAG_TYPE_ORDERED
+                 * - CVMX_POW_TAG_TYPE_ATOMIC
+                 * - CVMX_POW_TAG_TYPE_NULL
+                 * - CVMX_POW_TAG_TYPE_NULL_NULL
+                 */
+                uint64_t state:2;
+        } s_null_rd;
+
+} cvmx_pow_tag_load_resp_t;
+
+/**
+ * This structure describes the address used for stores to the POW.
+ *  The store address is meaningful on stores to the POW.  The
+ *  hardware assumes that an aligned 64-bit store was used for all
+ *  these stores.  Note the assumption that the work queue entry is
+ *  aligned on an 8-byte boundary (since the low-order 3 address bits
+ *  must be zero).  Note that not all fields are used by all
+ *  operations.
+ *
+ *  NOTE: The following is the behavior of the pending switch bit at the PP
+ *       for POW stores (i.e. when did<7:3> == 0xc)
+ *     - did<2:0> == 0      => pending switch bit is set
+ *     - did<2:0> == 1      => no affect on the pending switch bit
+ *     - did<2:0> == 3      => pending switch bit is cleared
+ *     - did<2:0> == 7      => no affect on the pending switch bit
+ *     - did<2:0> == others => must not be used
+ *     - No other loads/stores have an affect on the pending switch bit
+ *     - The switch bus from POW can clear the pending switch bit
+ *
+ *  NOTE: did<2:0> == 2 is used by the HW for a special single-cycle
+ *  ADDWQ command that only contains the pointer). SW must never use
+ *  did<2:0> == 2.
+ */
+typedef union {
+    /**
+     * Unsigned 64 bit integer representation of store address
+     */
+        uint64_t u64;
+
+        struct {
+                /* Memory region.  Should be CVMX_IO_SEG in most cases */
+                uint64_t mem_reg:2;
+                uint64_t reserved_49_61:13;     /* Must be zero */
+                uint64_t is_io:1;       /* Must be one */
+                /* Device ID of POW.  Note that different sub-dids are used. */
+                uint64_t did:8;
+                uint64_t reserved_36_39:4;      /* Must be zero */
+                /* Address field. addr<2:0> must be zero */
+                uint64_t addr:36;
+        } stag;
+} cvmx_pow_tag_store_addr_t;
+
+/**
+ * decode of the store data when an IOBDMA SENDSINGLE is sent to POW
+ */
+typedef union {
+        uint64_t u64;
+
+        struct {
+                /*
+                 * the (64-bit word) location in scratchpad to write
+                 * to (if len != 0)
+                 */
+                uint64_t scraddr:8;
+                /* the number of words in the response (0 => no response) */
+                uint64_t len:8;
+                /* the ID of the device on the non-coherent bus */
+                uint64_t did:8;
+                uint64_t unused:36;
+                /* if set, don't return load response until work is available */
+                uint64_t wait:1;
+                uint64_t unused2:3;
+        } s;
+
+} cvmx_pow_iobdma_store_t;
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+/**
+ * Get the POW tag for this core. This returns the current
+ * tag type, tag, group, and POW entry index associated with
+ * this core. Index is only valid if the tag type isn't NULL_NULL.
+ * If a tag switch is pending this routine returns the tag before
+ * the tag switch, not after.
+ *
+ * Returns Current tag
+ */
+static inline cvmx_pow_tag_req_t cvmx_pow_get_current_tag(void)
+{
+        cvmx_pow_load_addr_t load_addr;
+        cvmx_pow_tag_load_resp_t load_resp;
+        cvmx_pow_tag_req_t result;
+
+        load_addr.u64 = 0;
+        load_addr.sstatus.mem_region = CVMX_IO_SEG;
+        load_addr.sstatus.is_io = 1;
+        load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
+        load_addr.sstatus.coreid = cvmx_get_core_num();
+        load_addr.sstatus.get_cur = 1;
+        load_resp.u64 = cvmx_read_csr(load_addr.u64);
+        result.u64 = 0;
+        result.s.grp = load_resp.s_sstatus2.grp;
+        result.s.index = load_resp.s_sstatus2.index;
+        result.s.type = load_resp.s_sstatus2.tag_type;
+        result.s.tag = load_resp.s_sstatus2.tag;
+        return result;
+}
+
+/**
+ * Get the POW WQE for this core. This returns the work queue
+ * entry currently associated with this core.
+ *
+ * Returns WQE pointer
+ */
+static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void)
+{
+        cvmx_pow_load_addr_t load_addr;
+        cvmx_pow_tag_load_resp_t load_resp;
+
+        load_addr.u64 = 0;
+        load_addr.sstatus.mem_region = CVMX_IO_SEG;
+        load_addr.sstatus.is_io = 1;
+        load_addr.sstatus.did = CVMX_OCT_DID_TAG_TAG1;
+        load_addr.sstatus.coreid = cvmx_get_core_num();
+        load_addr.sstatus.get_cur = 1;
+        load_addr.sstatus.get_wqp = 1;
+        load_resp.u64 = cvmx_read_csr(load_addr.u64);
+        return (cvmx_wqe_t *) cvmx_phys_to_ptr(load_resp.s_sstatus4.wqp);
+}
+
+#ifndef CVMX_MF_CHORD
+#define CVMX_MF_CHORD(dest)         CVMX_RDHWR(dest, 30)
+#endif
+
+/**
+ * Print a warning if a tag switch is pending for this core
+ *
+ * @function: Function name checking for a pending tag switch
+ */
+static inline void __cvmx_pow_warn_if_pending_switch(const char *function)
+{
+        uint64_t switch_complete;
+        CVMX_MF_CHORD(switch_complete);
+        if (!switch_complete)
+                pr_warning("%s called with tag switch in progress\n", function);
+}
+
+/**
+ * Waits for a tag switch to complete by polling the completion bit.
+ * Note that switches to NULL complete immediately and do not need
+ * to be waited for.
+ */
+static inline void cvmx_pow_tag_sw_wait(void)
+{
+        const uint64_t MAX_CYCLES = 1ull << 31;
+        uint64_t switch_complete;
+        uint64_t start_cycle = cvmx_get_cycle();
+        while (1) {
+                CVMX_MF_CHORD(switch_complete);
+                if (unlikely(switch_complete))
+                        break;
+                if (unlikely(cvmx_get_cycle() > start_cycle + MAX_CYCLES)) {
+                        pr_warning("Tag switch is taking a long time, "
+                                   "possible deadlock\n");
+                        start_cycle = -MAX_CYCLES - 1;
+                }
+        }
+}
+
+/**
+ * Synchronous work request.  Requests work from the POW.
+ * This function does NOT wait for previous tag switches to complete,
+ * so the caller must ensure that there is not a pending tag switch.
+ *
+ * @wait:   When set, call stalls until work becomes avaiable, or times out.
+ *               If not set, returns immediately.
+ *
+ * Returns Returns the WQE pointer from POW. Returns NULL if no work
+ * was available.
+ */
+static inline cvmx_wqe_t *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t
+                                                             wait)
+{
+        cvmx_pow_load_addr_t ptr;
+        cvmx_pow_tag_load_resp_t result;
+
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        ptr.u64 = 0;
+        ptr.swork.mem_region = CVMX_IO_SEG;
+        ptr.swork.is_io = 1;
+        ptr.swork.did = CVMX_OCT_DID_TAG_SWTAG;
+        ptr.swork.wait = wait;
+
+        result.u64 = cvmx_read_csr(ptr.u64);
+
+        if (result.s_work.no_work)
+                return NULL;
+        else
+                return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr);
+}
+
+/**
+ * Synchronous work request.  Requests work from the POW.
+ * This function waits for any previous tag switch to complete before
+ * requesting the new work.
+ *
+ * @wait:   When set, call stalls until work becomes avaiable, or times out.
+ *               If not set, returns immediately.
+ *
+ * Returns Returns the WQE pointer from POW. Returns NULL if no work
+ * was available.
+ */
+static inline cvmx_wqe_t *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /* Must not have a switch pending when requesting work */
+        cvmx_pow_tag_sw_wait();
+        return cvmx_pow_work_request_sync_nocheck(wait);
+
+}
+
+/**
+ * Synchronous null_rd request.  Requests a switch out of NULL_NULL POW state.
+ * This function waits for any previous tag switch to complete before
+ * requesting the null_rd.
+ *
+ * Returns Returns the POW state of type cvmx_pow_tag_type_t.
+ */
+static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void)
+{
+        cvmx_pow_load_addr_t ptr;
+        cvmx_pow_tag_load_resp_t result;
+
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /* Must not have a switch pending when requesting work */
+        cvmx_pow_tag_sw_wait();
+
+        ptr.u64 = 0;
+        ptr.snull_rd.mem_region = CVMX_IO_SEG;
+        ptr.snull_rd.is_io = 1;
+        ptr.snull_rd.did = CVMX_OCT_DID_TAG_NULL_RD;
+
+        result.u64 = cvmx_read_csr(ptr.u64);
+
+        return (enum cvmx_pow_tag_type) result.s_null_rd.state;
+}
+
+/**
+ * Asynchronous work request.  Work is requested from the POW unit,
+ * and should later be checked with function
+ * cvmx_pow_work_response_async.  This function does NOT wait for
+ * previous tag switches to complete, so the caller must ensure that
+ * there is not a pending tag switch.
+ *
+ * @scr_addr: Scratch memory address that response will be returned
+ *            to, which is either a valid WQE, or a response with the
+ *            invalid bit set.  Byte address, must be 8 byte aligned.
+ *
+ * @wait: 1 to cause response to wait for work to become available (or
+ *        timeout), 0 to cause response to return immediately
+ */
+static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
+                                                       cvmx_pow_wait_t wait)
+{
+        cvmx_pow_iobdma_store_t data;
+
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /* scr_addr must be 8 byte aligned */
+        data.s.scraddr = scr_addr >> 3;
+        data.s.len = 1;
+        data.s.did = CVMX_OCT_DID_TAG_SWTAG;
+        data.s.wait = wait;
+        cvmx_send_single(data.u64);
+}
+
+/**
+ * Asynchronous work request.  Work is requested from the POW unit,
+ * and should later be checked with function
+ * cvmx_pow_work_response_async.  This function waits for any previous
+ * tag switch to complete before requesting the new work.
+ *
+ * @scr_addr: Scratch memory address that response will be returned
+ *            to, which is either a valid WQE, or a response with the
+ *            invalid bit set.  Byte address, must be 8 byte aligned.
+ *
+ * @wait: 1 to cause response to wait for work to become available (or
+ *                  timeout), 0 to cause response to return immediately
+ */
+static inline void cvmx_pow_work_request_async(int scr_addr,
+                                               cvmx_pow_wait_t wait)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /* Must not have a switch pending when requesting work */
+        cvmx_pow_tag_sw_wait();
+        cvmx_pow_work_request_async_nocheck(scr_addr, wait);
+}
+
+/**
+ * Gets result of asynchronous work request.  Performs a IOBDMA sync
+ * to wait for the response.
+ *
+ * @scr_addr: Scratch memory address to get result from Byte address,
+ *            must be 8 byte aligned.
+ *
+ * Returns Returns the WQE from the scratch register, or NULL if no
+ * work was available.
+ */
+static inline cvmx_wqe_t *cvmx_pow_work_response_async(int scr_addr)
+{
+        cvmx_pow_tag_load_resp_t result;
+
+        CVMX_SYNCIOBDMA;
+        result.u64 = cvmx_scratch_read64(scr_addr);
+
+        if (result.s_work.no_work)
+                return NULL;
+        else
+                return (cvmx_wqe_t *) cvmx_phys_to_ptr(result.s_work.addr);
+}
+
+/**
+ * Checks if a work queue entry pointer returned by a work
+ * request is valid.  It may be invalid due to no work
+ * being available or due to a timeout.
+ *
+ * @wqe_ptr: pointer to a work queue entry returned by the POW
+ *
+ * Returns 0 if pointer is valid
+ *         1 if invalid (no work was returned)
+ */
+static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr)
+{
+        return wqe_ptr == NULL;
+}
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.
+ * Completion for the tag switch must be checked for separately.  This
+ * function does NOT update the work queue entry in dram to match tag
+ * value and type, so the application must keep track of these if they
+ * are important to the application.  This tag switch command must not
+ * be used for switches to NULL, as the tag switch pending bit will be
+ * set by the switch request, but never cleared by the hardware.
+ *
+ * NOTE: This should not be used when switching from a NULL tag.  Use
+ * cvmx_pow_tag_sw_full() instead.
+ *
+ * This function does no checks, so the caller must ensure that any
+ * previous tag switch has completed.
+ *
+ * @tag:      new tag value
+ * @tag_type: new tag type (ordered or atomic)
+ */
+static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag,
+                                           enum cvmx_pow_tag_type tag_type)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        if (CVMX_ENABLE_POW_CHECKS) {
+                cvmx_pow_tag_req_t current_tag;
+                __cvmx_pow_warn_if_pending_switch(__func__);
+                current_tag = cvmx_pow_get_current_tag();
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
+                        pr_warning("%s called with NULL_NULL tag\n",
+                                   __func__);
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warning("%s called with NULL tag\n", __func__);
+                if ((current_tag.s.type == tag_type)
+                   && (current_tag.s.tag == tag))
+                        pr_warning("%s called to perform a tag switch to the "
+                                   "same tag\n",
+                             __func__);
+                if (tag_type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warning("%s called to perform a tag switch to "
+                                   "NULL. Use cvmx_pow_tag_sw_null() instead\n",
+                             __func__);
+        }
+
+        /*
+         * Note that WQE in DRAM is not updated here, as the POW does
+         * not read from DRAM once the WQE is in flight.  See hardware
+         * manual for complete details.  It is the application's
+         * responsibility to keep track of the current tag value if
+         * that is important.
+         */
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
+        tag_req.s.tag = tag;
+        tag_req.s.type = tag_type;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
+
+        /* once this store arrives at POW, it will attempt the switch
+           software must wait for the switch to complete separately */
+        cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.
+ * Completion for the tag switch must be checked for separately.  This
+ * function does NOT update the work queue entry in dram to match tag
+ * value and type, so the application must keep track of these if they
+ * are important to the application.  This tag switch command must not
+ * be used for switches to NULL, as the tag switch pending bit will be
+ * set by the switch request, but never cleared by the hardware.
+ *
+ * NOTE: This should not be used when switching from a NULL tag.  Use
+ * cvmx_pow_tag_sw_full() instead.
+ *
+ * This function waits for any previous tag switch to complete, and also
+ * displays an error on tag switches to NULL.
+ *
+ * @tag:      new tag value
+ * @tag_type: new tag type (ordered or atomic)
+ */
+static inline void cvmx_pow_tag_sw(uint32_t tag,
+                                   enum cvmx_pow_tag_type tag_type)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /*
+         * Note that WQE in DRAM is not updated here, as the POW does
+         * not read from DRAM once the WQE is in flight.  See hardware
+         * manual for complete details.  It is the application's
+         * responsibility to keep track of the current tag value if
+         * that is important.
+         */
+
+        /*
+         * Ensure that there is not a pending tag switch, as a tag
+         * switch cannot be started if a previous switch is still
+         * pending.
+         */
+        cvmx_pow_tag_sw_wait();
+        cvmx_pow_tag_sw_nocheck(tag, tag_type);
+}
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.
+ * Completion for the tag switch must be checked for separately.  This
+ * function does NOT update the work queue entry in dram to match tag
+ * value and type, so the application must keep track of these if they
+ * are important to the application.  This tag switch command must not
+ * be used for switches to NULL, as the tag switch pending bit will be
+ * set by the switch request, but never cleared by the hardware.
+ *
+ * This function must be used for tag switches from NULL.
+ *
+ * This function does no checks, so the caller must ensure that any
+ * previous tag switch has completed.
+ *
+ * @wqp:      pointer to work queue entry to submit.  This entry is
+ *            updated to match the other parameters
+ * @tag:      tag value to be assigned to work queue entry
+ * @tag_type: type of tag
+ * @group:    group value for the work queue entry.
+ */
+static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag,
+                                                enum cvmx_pow_tag_type tag_type,
+                                                uint64_t group)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        if (CVMX_ENABLE_POW_CHECKS) {
+                cvmx_pow_tag_req_t current_tag;
+                __cvmx_pow_warn_if_pending_switch(__func__);
+                current_tag = cvmx_pow_get_current_tag();
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
+                        pr_warning("%s called with NULL_NULL tag\n",
+                                   __func__);
+                if ((current_tag.s.type == tag_type)
+                   && (current_tag.s.tag == tag))
+                        pr_warning("%s called to perform a tag switch to "
+                                   "the same tag\n",
+                             __func__);
+                if (tag_type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warning("%s called to perform a tag switch to "
+                                   "NULL. Use cvmx_pow_tag_sw_null() instead\n",
+                             __func__);
+                if (wqp != cvmx_phys_to_ptr(0x80))
+                        if (wqp != cvmx_pow_get_current_wqp())
+                                pr_warning("%s passed WQE(%p) doesn't match "
+                                           "the address in the POW(%p)\n",
+                                     __func__, wqp,
+                                     cvmx_pow_get_current_wqp());
+        }
+
+        /*
+         * Note that WQE in DRAM is not updated here, as the POW does
+         * not read from DRAM once the WQE is in flight.  See hardware
+         * manual for complete details.  It is the application's
+         * responsibility to keep track of the current tag value if
+         * that is important.
+         */
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_FULL;
+        tag_req.s.tag = tag;
+        tag_req.s.type = tag_type;
+        tag_req.s.grp = group;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_SWTAG;
+        ptr.sio.offset = CAST64(wqp);
+
+        /*
+         * once this store arrives at POW, it will attempt the switch
+         * software must wait for the switch to complete separately.
+         */
+        cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+/**
+ * Starts a tag switch to the provided tag value and tag type.
+ * Completion for the tag switch must be checked for separately.  This
+ * function does NOT update the work queue entry in dram to match tag
+ * value and type, so the application must keep track of these if they
+ * are important to the application.  This tag switch command must not
+ * be used for switches to NULL, as the tag switch pending bit will be
+ * set by the switch request, but never cleared by the hardware.
+ *
+ * This function must be used for tag switches from NULL.
+ *
+ * This function waits for any pending tag switches to complete
+ * before requesting the tag switch.
+ *
+ * @wqp:      pointer to work queue entry to submit.  This entry is updated
+ *            to match the other parameters
+ * @tag:      tag value to be assigned to work queue entry
+ * @tag_type: type of tag
+ * @group:      group value for the work queue entry.
+ */
+static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag,
+                                        enum cvmx_pow_tag_type tag_type,
+                                        uint64_t group)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /*
+         * Ensure that there is not a pending tag switch, as a tag
+         * switch cannot be started if a previous switch is still
+         * pending.
+         */
+        cvmx_pow_tag_sw_wait();
+        cvmx_pow_tag_sw_full_nocheck(wqp, tag, tag_type, group);
+}
+
+/**
+ * Switch to a NULL tag, which ends any ordering or
+ * synchronization provided by the POW for the current
+ * work queue entry.  This operation completes immediatly,
+ * so completetion should not be waited for.
+ * This function does NOT wait for previous tag switches to complete,
+ * so the caller must ensure that any previous tag switches have completed.
+ */
+static inline void cvmx_pow_tag_sw_null_nocheck(void)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        if (CVMX_ENABLE_POW_CHECKS) {
+                cvmx_pow_tag_req_t current_tag;
+                __cvmx_pow_warn_if_pending_switch(__func__);
+                current_tag = cvmx_pow_get_current_tag();
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
+                        pr_warning("%s called with NULL_NULL tag\n",
+                                   __func__);
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warning("%s called when we already have a "
+                                   "NULL tag\n",
+                             __func__);
+        }
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG;
+        tag_req.s.type = CVMX_POW_TAG_TYPE_NULL;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
+
+        cvmx_write_io(ptr.u64, tag_req.u64);
+
+        /* switch to NULL completes immediately */
+}
+
+/**
+ * Switch to a NULL tag, which ends any ordering or
+ * synchronization provided by the POW for the current
+ * work queue entry.  This operation completes immediatly,
+ * so completetion should not be waited for.
+ * This function waits for any pending tag switches to complete
+ * before requesting the switch to NULL.
+ */
+static inline void cvmx_pow_tag_sw_null(void)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /*
+         * Ensure that there is not a pending tag switch, as a tag
+         * switch cannot be started if a previous switch is still
+         * pending.
+         */
+        cvmx_pow_tag_sw_wait();
+        cvmx_pow_tag_sw_null_nocheck();
+
+        /* switch to NULL completes immediately */
+}
+
+/**
+ * Submits work to an input queue.  This function updates the work
+ * queue entry in DRAM to match the arguments given.  Note that the
+ * tag provided is for the work queue entry submitted, and is
+ * unrelated to the tag that the core currently holds.
+ *
+ * @wqp:      pointer to work queue entry to submit.  This entry is
+ *            updated to match the other parameters
+ * @tag:      tag value to be assigned to work queue entry
+ * @tag_type: type of tag
+ * @qos:      Input queue to add to.
+ * @grp:      group value for the work queue entry.
+ */
+static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag,
+                                        enum cvmx_pow_tag_type tag_type,
+                                        uint64_t qos, uint64_t grp)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        wqp->qos = qos;
+        wqp->tag = tag;
+        wqp->tag_type = tag_type;
+        wqp->grp = grp;
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_ADDWQ;
+        tag_req.s.type = tag_type;
+        tag_req.s.tag = tag;
+        tag_req.s.qos = qos;
+        tag_req.s.grp = grp;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_TAG1;
+        ptr.sio.offset = cvmx_ptr_to_phys(wqp);
+
+        /*
+         * SYNC write to memory before the work submit.  This is
+         * necessary as POW may read values from DRAM at this time.
+         */
+        CVMX_SYNCWS;
+        cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+/**
+ * This function sets the group mask for a core.  The group mask
+ * indicates which groups each core will accept work from. There are
+ * 16 groups.
+ *
+ * @core_num:   core to apply mask to
+ * @mask:   Group mask. There are 16 groups, so only bits 0-15 are valid,
+ *               representing groups 0-15.
+ *               Each 1 bit in the mask enables the core to accept work from
+ *               the corresponding group.
+ */
+static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask)
+{
+        union cvmx_pow_pp_grp_mskx grp_msk;
+
+        grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
+        grp_msk.s.grp_msk = mask;
+        cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
+}
+
+/**
+ * This function sets POW static priorities for a core. Each input queue has
+ * an associated priority value.
+ *
+ * @core_num:   core to apply priorities to
+ * @priority:   Vector of 8 priorities, one per POW Input Queue (0-7).
+ *                   Highest priority is 0 and lowest is 7. A priority value
+ *                   of 0xF instructs POW to skip the Input Queue when
+ *                   scheduling to this specific core.
+ *                   NOTE: priorities should not have gaps in values, meaning
+ *                         {0,1,1,1,1,1,1,1} is a valid configuration while
+ *                         {0,2,2,2,2,2,2,2} is not.
+ */
+static inline void cvmx_pow_set_priority(uint64_t core_num,
+                                         const uint8_t priority[])
+{
+        /* POW priorities are supported on CN5xxx and later */
+        if (!OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+                union cvmx_pow_pp_grp_mskx grp_msk;
+
+                grp_msk.u64 = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(core_num));
+                grp_msk.s.qos0_pri = priority[0];
+                grp_msk.s.qos1_pri = priority[1];
+                grp_msk.s.qos2_pri = priority[2];
+                grp_msk.s.qos3_pri = priority[3];
+                grp_msk.s.qos4_pri = priority[4];
+                grp_msk.s.qos5_pri = priority[5];
+                grp_msk.s.qos6_pri = priority[6];
+                grp_msk.s.qos7_pri = priority[7];
+
+                /* Detect gaps between priorities and flag error */
+                {
+                        int i;
+                        uint32_t prio_mask = 0;
+
+                        for (i = 0; i < 8; i++)
+                                if (priority[i] != 0xF)
+                                        prio_mask |= 1 << priority[i];
+
+                        if (prio_mask ^ ((1 << cvmx_pop(prio_mask)) - 1)) {
+                                pr_err("POW static priorities should be "
+                                       "contiguous (0x%llx)\n",
+                                     (unsigned long long)prio_mask);
+                                return;
+                        }
+                }
+
+                cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(core_num), grp_msk.u64);
+        }
+}
+
+/**
+ * Performs a tag switch and then an immediate deschedule. This completes
+ * immediatly, so completion must not be waited for.  This function does NOT
+ * update the wqe in DRAM to match arguments.
+ *
+ * This function does NOT wait for any prior tag switches to complete, so the
+ * calling code must do this.
+ *
+ * Note the following CAVEAT of the Octeon HW behavior when
+ * re-scheduling DE-SCHEDULEd items whose (next) state is
+ * ORDERED:
+ *   - If there are no switches pending at the time that the
+ *     HW executes the de-schedule, the HW will only re-schedule
+ *     the head of the FIFO associated with the given tag. This
+ *     means that in many respects, the HW treats this ORDERED
+ *     tag as an ATOMIC tag. Note that in the SWTAG_DESCH
+ *     case (to an ORDERED tag), the HW will do the switch
+ *     before the deschedule whenever it is possible to do
+ *     the switch immediately, so it may often look like
+ *     this case.
+ *   - If there is a pending switch to ORDERED at the time
+ *     the HW executes the de-schedule, the HW will perform
+ *     the switch at the time it re-schedules, and will be
+ *     able to reschedule any/all of the entries with the
+ *     same tag.
+ * Due to this behavior, the RECOMMENDATION to software is
+ * that they have a (next) state of ATOMIC when they
+ * DE-SCHEDULE. If an ORDERED tag is what was really desired,
+ * SW can choose to immediately switch to an ORDERED tag
+ * after the work (that has an ATOMIC tag) is re-scheduled.
+ * Note that since there are never any tag switches pending
+ * when the HW re-schedules, this switch can be IMMEDIATE upon
+ * the reception of the pointer during the re-schedule.
+ *
+ * @tag:      New tag value
+ * @tag_type: New tag type
+ * @group:    New group value
+ * @no_sched: Control whether this work queue entry will be rescheduled.
+ *                 - 1 : don't schedule this work
+ *                 - 0 : allow this work to be scheduled.
+ */
+static inline void cvmx_pow_tag_sw_desched_nocheck(
+        uint32_t tag,
+        enum cvmx_pow_tag_type tag_type,
+        uint64_t group,
+        uint64_t no_sched)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        if (CVMX_ENABLE_POW_CHECKS) {
+                cvmx_pow_tag_req_t current_tag;
+                __cvmx_pow_warn_if_pending_switch(__func__);
+                current_tag = cvmx_pow_get_current_tag();
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
+                        pr_warning("%s called with NULL_NULL tag\n",
+                                   __func__);
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warning("%s called with NULL tag. Deschedule not "
+                                   "allowed from NULL state\n",
+                             __func__);
+                if ((current_tag.s.type != CVMX_POW_TAG_TYPE_ATOMIC)
+                        && (tag_type != CVMX_POW_TAG_TYPE_ATOMIC))
+                        pr_warning("%s called where neither the before or "
+                                   "after tag is ATOMIC\n",
+                             __func__);
+        }
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_SWTAG_DESCH;
+        tag_req.s.tag = tag;
+        tag_req.s.type = tag_type;
+        tag_req.s.grp = group;
+        tag_req.s.no_sched = no_sched;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
+        /*
+         * since TAG3 is used, this store will clear the local pending
+         * switch bit.
+         */
+        cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+/**
+ * Performs a tag switch and then an immediate deschedule. This completes
+ * immediatly, so completion must not be waited for.  This function does NOT
+ * update the wqe in DRAM to match arguments.
+ *
+ * This function waits for any prior tag switches to complete, so the
+ * calling code may call this function with a pending tag switch.
+ *
+ * Note the following CAVEAT of the Octeon HW behavior when
+ * re-scheduling DE-SCHEDULEd items whose (next) state is
+ * ORDERED:
+ *   - If there are no switches pending at the time that the
+ *     HW executes the de-schedule, the HW will only re-schedule
+ *     the head of the FIFO associated with the given tag. This
+ *     means that in many respects, the HW treats this ORDERED
+ *     tag as an ATOMIC tag. Note that in the SWTAG_DESCH
+ *     case (to an ORDERED tag), the HW will do the switch
+ *     before the deschedule whenever it is possible to do
+ *     the switch immediately, so it may often look like
+ *     this case.
+ *   - If there is a pending switch to ORDERED at the time
+ *     the HW executes the de-schedule, the HW will perform
+ *     the switch at the time it re-schedules, and will be
+ *     able to reschedule any/all of the entries with the
+ *     same tag.
+ * Due to this behavior, the RECOMMENDATION to software is
+ * that they have a (next) state of ATOMIC when they
+ * DE-SCHEDULE. If an ORDERED tag is what was really desired,
+ * SW can choose to immediately switch to an ORDERED tag
+ * after the work (that has an ATOMIC tag) is re-scheduled.
+ * Note that since there are never any tag switches pending
+ * when the HW re-schedules, this switch can be IMMEDIATE upon
+ * the reception of the pointer during the re-schedule.
+ *
+ * @tag:      New tag value
+ * @tag_type: New tag type
+ * @group:    New group value
+ * @no_sched: Control whether this work queue entry will be rescheduled.
+ *                 - 1 : don't schedule this work
+ *                 - 0 : allow this work to be scheduled.
+ */
+static inline void cvmx_pow_tag_sw_desched(uint32_t tag,
+                                           enum cvmx_pow_tag_type tag_type,
+                                           uint64_t group, uint64_t no_sched)
+{
+        if (CVMX_ENABLE_POW_CHECKS)
+                __cvmx_pow_warn_if_pending_switch(__func__);
+
+        /* Need to make sure any writes to the work queue entry are complete */
+        CVMX_SYNCWS;
+        /*
+         * Ensure that there is not a pending tag switch, as a tag
+         * switch cannot be started if a previous switch is still
+         * pending.
+         */
+        cvmx_pow_tag_sw_wait();
+        cvmx_pow_tag_sw_desched_nocheck(tag, tag_type, group, no_sched);
+}
+
+/**
+ * Descchedules the current work queue entry.
+ *
+ * @no_sched: no schedule flag value to be set on the work queue
+ *            entry.  If this is set the entry will not be
+ *            rescheduled.
+ */
+static inline void cvmx_pow_desched(uint64_t no_sched)
+{
+        cvmx_addr_t ptr;
+        cvmx_pow_tag_req_t tag_req;
+
+        if (CVMX_ENABLE_POW_CHECKS) {
+                cvmx_pow_tag_req_t current_tag;
+                __cvmx_pow_warn_if_pending_switch(__func__);
+                current_tag = cvmx_pow_get_current_tag();
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL_NULL)
+                        pr_warning("%s called with NULL_NULL tag\n",
+                                   __func__);
+                if (current_tag.s.type == CVMX_POW_TAG_TYPE_NULL)
+                        pr_warning("%s called with NULL tag. Deschedule not "
+                                   "expected from NULL state\n",
+                             __func__);
+        }
+
+        /* Need to make sure any writes to the work queue entry are complete */
+        CVMX_SYNCWS;
+
+        tag_req.u64 = 0;
+        tag_req.s.op = CVMX_POW_TAG_OP_DESCH;
+        tag_req.s.no_sched = no_sched;
+
+        ptr.u64 = 0;
+        ptr.sio.mem_region = CVMX_IO_SEG;
+        ptr.sio.is_io = 1;
+        ptr.sio.did = CVMX_OCT_DID_TAG_TAG3;
+        /*
+         * since TAG3 is used, this store will clear the local pending
+         * switch bit.
+         */
+        cvmx_write_io(ptr.u64, tag_req.u64);
+}
+
+/****************************************************
+* Define usage of bits within the 32 bit tag values.
+*****************************************************/
+
+/*
+ * Number of bits of the tag used by software.  The SW bits are always
+ * a contiguous block of the high starting at bit 31.  The hardware
+ * bits are always the low bits.  By default, the top 8 bits of the
+ * tag are reserved for software, and the low 24 are set by the IPD
+ * unit.
+ */
+#define CVMX_TAG_SW_BITS    (8)
+#define CVMX_TAG_SW_SHIFT   (32 - CVMX_TAG_SW_BITS)
+
+/* Below is the list of values for the top 8 bits of the tag. */
+/*
+ * Tag values with top byte of this value are reserved for internal
+ * executive uses.
+ */
+#define CVMX_TAG_SW_BITS_INTERNAL  0x1
+/* The executive divides the remaining 24 bits as follows:
+ *  - the upper 8 bits (bits 23 - 16 of the tag) define a subgroup
+ *
+ *  - the lower 16 bits (bits 15 - 0 of the tag) define are the value
+ *    with the subgroup
+ *
+ * Note that this section describes the format of tags generated by
+ * software - refer to the hardware documentation for a description of
+ * the tags values generated by the packet input hardware.  Subgroups
+ * are defined here.
+ */
+/* Mask for the value portion of the tag */
+#define CVMX_TAG_SUBGROUP_MASK  0xFFFF
+#define CVMX_TAG_SUBGROUP_SHIFT 16
+#define CVMX_TAG_SUBGROUP_PKO  0x1
+
+/* End of executive tag subgroup definitions */
+
+/*
+ * The remaining values software bit values 0x2 - 0xff are available
+ * for application use.
+ */
+
+/**
+ * This function creates a 32 bit tag value from the two values provided.
+ *
+ * @sw_bits: The upper bits (number depends on configuration) are set
+ *           to this value.  The remainder of bits are set by the
+ *           hw_bits parameter.
+ *
+ * @hw_bits: The lower bits (number depends on configuration) are set
+ *           to this value.  The remainder of bits are set by the
+ *           sw_bits parameter.
+ *
+ * Returns 32 bit value of the combined hw and sw bits.
+ */
+static inline uint32_t cvmx_pow_tag_compose(uint64_t sw_bits, uint64_t hw_bits)
+{
+        return ((sw_bits & cvmx_build_mask(CVMX_TAG_SW_BITS)) <<
+                        CVMX_TAG_SW_SHIFT) |
+                (hw_bits & cvmx_build_mask(32 - CVMX_TAG_SW_BITS));
+}
+
+/**
+ * Extracts the bits allocated for software use from the tag
+ *
+ * @tag:    32 bit tag value
+ *
+ * Returns N bit software tag value, where N is configurable with the
+ * CVMX_TAG_SW_BITS define
+ */
+static inline uint32_t cvmx_pow_tag_get_sw_bits(uint64_t tag)
+{
+        return (tag >> (32 - CVMX_TAG_SW_BITS)) &
+                cvmx_build_mask(CVMX_TAG_SW_BITS);
+}
+
+/**
+ *
+ * Extracts the bits allocated for hardware use from the tag
+ *
+ * @tag:    32 bit tag value
+ *
+ * Returns (32 - N) bit software tag value, where N is configurable
+ * with the CVMX_TAG_SW_BITS define
+ */
+static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag)
+{
+        return tag & cvmx_build_mask(32 - CVMX_TAG_SW_BITS);
+}
+
+/**
+ * Store the current POW internal state into the supplied
+ * buffer. It is recommended that you pass a buffer of at least
+ * 128KB. The format of the capture may change based on SDK
+ * version and Octeon chip.
+ *
+ * @buffer: Buffer to store capture into
+ * @buffer_size:
+ *               The size of the supplied buffer
+ *
+ * Returns Zero on sucess, negative on failure
+ */
+extern int cvmx_pow_capture(void *buffer, int buffer_size);
+
+/**
+ * Dump a POW capture to the console in a human readable format.
+ *
+ * @buffer: POW capture from cvmx_pow_capture()
+ * @buffer_size:
+ *               Size of the buffer
+ */
+extern void cvmx_pow_display(void *buffer, int buffer_size);
+
+/**
+ * Return the number of POW entries supported by this chip
+ *
+ * Returns Number of POW entries
+ */
+extern int cvmx_pow_get_num_entries(void);
+
+#endif /* __CVMX_POW_H__ */
diff --git a/drivers/staging/octeon/cvmx-scratch.h b/drivers/staging/octeon/cvmx-scratch.h
new file mode 100644
index 000000000000..96b70cfd6245
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-scratch.h
@@ -0,0 +1,139 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * This file provides support for the processor local scratch memory.
+ * Scratch memory is byte addressable - all addresses are byte addresses.
+ *
+ */
+
+#ifndef __CVMX_SCRATCH_H__
+#define __CVMX_SCRATCH_H__
+
+/*
+ * Note: This define must be a long, not a long long in order to
+ * compile without warnings for both 32bit and 64bit.
+ */
+#define CVMX_SCRATCH_BASE       (-32768l)       /* 0xffffffffffff8000 */
+
+/**
+ * Reads an 8 bit value from the processor local scratchpad memory.
+ *
+ * @address: byte address to read from
+ *
+ * Returns value read
+ */
+static inline uint8_t cvmx_scratch_read8(uint64_t address)
+{
+        return *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address);
+}
+
+/**
+ * Reads a 16 bit value from the processor local scratchpad memory.
+ *
+ * @address: byte address to read from
+ *
+ * Returns value read
+ */
+static inline uint16_t cvmx_scratch_read16(uint64_t address)
+{
+        return *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address);
+}
+
+/**
+ * Reads a 32 bit value from the processor local scratchpad memory.
+ *
+ * @address: byte address to read from
+ *
+ * Returns value read
+ */
+static inline uint32_t cvmx_scratch_read32(uint64_t address)
+{
+        return *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address);
+}
+
+/**
+ * Reads a 64 bit value from the processor local scratchpad memory.
+ *
+ * @address: byte address to read from
+ *
+ * Returns value read
+ */
+static inline uint64_t cvmx_scratch_read64(uint64_t address)
+{
+        return *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address);
+}
+
+/**
+ * Writes an 8 bit value to the processor local scratchpad memory.
+ *
+ * @address: byte address to write to
+ * @value:   value to write
+ */
+static inline void cvmx_scratch_write8(uint64_t address, uint64_t value)
+{
+        *CASTPTR(volatile uint8_t, CVMX_SCRATCH_BASE + address) =
+            (uint8_t) value;
+}
+
+/**
+ * Writes a 32 bit value to the processor local scratchpad memory.
+ *
+ * @address: byte address to write to
+ * @value:   value to write
+ */
+static inline void cvmx_scratch_write16(uint64_t address, uint64_t value)
+{
+        *CASTPTR(volatile uint16_t, CVMX_SCRATCH_BASE + address) =
+            (uint16_t) value;
+}
+
+/**
+ * Writes a 16 bit value to the processor local scratchpad memory.
+ *
+ * @address: byte address to write to
+ * @value:   value to write
+ */
+static inline void cvmx_scratch_write32(uint64_t address, uint64_t value)
+{
+        *CASTPTR(volatile uint32_t, CVMX_SCRATCH_BASE + address) =
+            (uint32_t) value;
+}
+
+/**
+ * Writes a 64 bit value to the processor local scratchpad memory.
+ *
+ * @address: byte address to write to
+ * @value:   value to write
+ */
+static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
+{
+        *CASTPTR(volatile uint64_t, CVMX_SCRATCH_BASE + address) = value;
+}
+
+#endif /* __CVMX_SCRATCH_H__ */
diff --git a/drivers/staging/octeon/cvmx-smix-defs.h b/drivers/staging/octeon/cvmx-smix-defs.h
new file mode 100644
index 000000000000..9ae45fcbe3e3
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-smix-defs.h
@@ -0,0 +1,178 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SMIX_DEFS_H__
+#define __CVMX_SMIX_DEFS_H__
+
+#define CVMX_SMIX_CLK(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001818ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_CMD(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001800ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_EN(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001820ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_RD_DAT(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001810ull + (((offset) & 1) * 256))
+#define CVMX_SMIX_WR_DAT(offset) \
+         CVMX_ADD_IO_SEG(0x0001180000001808ull + (((offset) & 1) * 256))
+
+union cvmx_smix_clk {
+        uint64_t u64;
+        struct cvmx_smix_clk_s {
+                uint64_t reserved_25_63:39;
+                uint64_t mode:1;
+                uint64_t reserved_21_23:3;
+                uint64_t sample_hi:5;
+                uint64_t sample_mode:1;
+                uint64_t reserved_14_14:1;
+                uint64_t clk_idle:1;
+                uint64_t preamble:1;
+                uint64_t sample:4;
+                uint64_t phase:8;
+        } s;
+        struct cvmx_smix_clk_cn30xx {
+                uint64_t reserved_21_63:43;
+                uint64_t sample_hi:5;
+                uint64_t reserved_14_15:2;
+                uint64_t clk_idle:1;
+                uint64_t preamble:1;
+                uint64_t sample:4;
+                uint64_t phase:8;
+        } cn30xx;
+        struct cvmx_smix_clk_cn30xx cn31xx;
+        struct cvmx_smix_clk_cn30xx cn38xx;
+        struct cvmx_smix_clk_cn30xx cn38xxp2;
+        struct cvmx_smix_clk_cn50xx {
+                uint64_t reserved_25_63:39;
+                uint64_t mode:1;
+                uint64_t reserved_21_23:3;
+                uint64_t sample_hi:5;
+                uint64_t reserved_14_15:2;
+                uint64_t clk_idle:1;
+                uint64_t preamble:1;
+                uint64_t sample:4;
+                uint64_t phase:8;
+        } cn50xx;
+        struct cvmx_smix_clk_s cn52xx;
+        struct cvmx_smix_clk_cn50xx cn52xxp1;
+        struct cvmx_smix_clk_s cn56xx;
+        struct cvmx_smix_clk_cn50xx cn56xxp1;
+        struct cvmx_smix_clk_cn30xx cn58xx;
+        struct cvmx_smix_clk_cn30xx cn58xxp1;
+};
+
+union cvmx_smix_cmd {
+        uint64_t u64;
+        struct cvmx_smix_cmd_s {
+                uint64_t reserved_18_63:46;
+                uint64_t phy_op:2;
+                uint64_t reserved_13_15:3;
+                uint64_t phy_adr:5;
+                uint64_t reserved_5_7:3;
+                uint64_t reg_adr:5;
+        } s;
+        struct cvmx_smix_cmd_cn30xx {
+                uint64_t reserved_17_63:47;
+                uint64_t phy_op:1;
+                uint64_t reserved_13_15:3;
+                uint64_t phy_adr:5;
+                uint64_t reserved_5_7:3;
+                uint64_t reg_adr:5;
+        } cn30xx;
+        struct cvmx_smix_cmd_cn30xx cn31xx;
+        struct cvmx_smix_cmd_cn30xx cn38xx;
+        struct cvmx_smix_cmd_cn30xx cn38xxp2;
+        struct cvmx_smix_cmd_s cn50xx;
+        struct cvmx_smix_cmd_s cn52xx;
+        struct cvmx_smix_cmd_s cn52xxp1;
+        struct cvmx_smix_cmd_s cn56xx;
+        struct cvmx_smix_cmd_s cn56xxp1;
+        struct cvmx_smix_cmd_cn30xx cn58xx;
+        struct cvmx_smix_cmd_cn30xx cn58xxp1;
+};
+
+union cvmx_smix_en {
+        uint64_t u64;
+        struct cvmx_smix_en_s {
+                uint64_t reserved_1_63:63;
+                uint64_t en:1;
+        } s;
+        struct cvmx_smix_en_s cn30xx;
+        struct cvmx_smix_en_s cn31xx;
+        struct cvmx_smix_en_s cn38xx;
+        struct cvmx_smix_en_s cn38xxp2;
+        struct cvmx_smix_en_s cn50xx;
+        struct cvmx_smix_en_s cn52xx;
+        struct cvmx_smix_en_s cn52xxp1;
+        struct cvmx_smix_en_s cn56xx;
+        struct cvmx_smix_en_s cn56xxp1;
+        struct cvmx_smix_en_s cn58xx;
+        struct cvmx_smix_en_s cn58xxp1;
+};
+
+union cvmx_smix_rd_dat {
+        uint64_t u64;
+        struct cvmx_smix_rd_dat_s {
+                uint64_t reserved_18_63:46;
+                uint64_t pending:1;
+                uint64_t val:1;
+                uint64_t dat:16;
+        } s;
+        struct cvmx_smix_rd_dat_s cn30xx;
+        struct cvmx_smix_rd_dat_s cn31xx;
+        struct cvmx_smix_rd_dat_s cn38xx;
+        struct cvmx_smix_rd_dat_s cn38xxp2;
+        struct cvmx_smix_rd_dat_s cn50xx;
+        struct cvmx_smix_rd_dat_s cn52xx;
+        struct cvmx_smix_rd_dat_s cn52xxp1;
+        struct cvmx_smix_rd_dat_s cn56xx;
+        struct cvmx_smix_rd_dat_s cn56xxp1;
+        struct cvmx_smix_rd_dat_s cn58xx;
+        struct cvmx_smix_rd_dat_s cn58xxp1;
+};
+
+union cvmx_smix_wr_dat {
+        uint64_t u64;
+        struct cvmx_smix_wr_dat_s {
+                uint64_t reserved_18_63:46;
+                uint64_t pending:1;
+                uint64_t val:1;
+                uint64_t dat:16;
+        } s;
+        struct cvmx_smix_wr_dat_s cn30xx;
+        struct cvmx_smix_wr_dat_s cn31xx;
+        struct cvmx_smix_wr_dat_s cn38xx;
+        struct cvmx_smix_wr_dat_s cn38xxp2;
+        struct cvmx_smix_wr_dat_s cn50xx;
+        struct cvmx_smix_wr_dat_s cn52xx;
+        struct cvmx_smix_wr_dat_s cn52xxp1;
+        struct cvmx_smix_wr_dat_s cn56xx;
+        struct cvmx_smix_wr_dat_s cn56xxp1;
+        struct cvmx_smix_wr_dat_s cn58xx;
+        struct cvmx_smix_wr_dat_s cn58xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-spi.c b/drivers/staging/octeon/cvmx-spi.c
new file mode 100644
index 000000000000..82794d920cec
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-spi.c
@@ -0,0 +1,667 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * Support library for the SPI
+ */
+#include <asm/octeon/octeon.h>
+
+#include "cvmx-config.h"
+
+#include "cvmx-pko.h"
+#include "cvmx-spi.h"
+
+#include "cvmx-spxx-defs.h"
+#include "cvmx-stxx-defs.h"
+#include "cvmx-srxx-defs.h"
+
+#define INVOKE_CB(function_p, args...)          \
+        do {                                    \
+                if (function_p) {               \
+                        res = function_p(args); \
+                        if (res)                \
+                                return res;     \
+                }                               \
+        } while (0)
+
+#if CVMX_ENABLE_DEBUG_PRINTS
+static const char *modes[] =
+    { "UNKNOWN", "TX Halfplex", "Rx Halfplex", "Duplex" };
+#endif
+
+/* Default callbacks, can be overridden
+ *  using cvmx_spi_get_callbacks/cvmx_spi_set_callbacks
+ */
+static cvmx_spi_callbacks_t cvmx_spi_callbacks = {
+        .reset_cb = cvmx_spi_reset_cb,
+        .calendar_setup_cb = cvmx_spi_calendar_setup_cb,
+        .clock_detect_cb = cvmx_spi_clock_detect_cb,
+        .training_cb = cvmx_spi_training_cb,
+        .calendar_sync_cb = cvmx_spi_calendar_sync_cb,
+        .interface_up_cb = cvmx_spi_interface_up_cb
+};
+
+/**
+ * Get current SPI4 initialization callbacks
+ *
+ * @callbacks:  Pointer to the callbacks structure.to fill
+ *
+ * Returns Pointer to cvmx_spi_callbacks_t structure.
+ */
+void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks)
+{
+        memcpy(callbacks, &cvmx_spi_callbacks, sizeof(cvmx_spi_callbacks));
+}
+
+/**
+ * Set new SPI4 initialization callbacks
+ *
+ * @new_callbacks:  Pointer to an updated callbacks structure.
+ */
+void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks)
+{
+        memcpy(&cvmx_spi_callbacks, new_callbacks, sizeof(cvmx_spi_callbacks));
+}
+
+/**
+ * Initialize and start the SPI interface.
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for clock synchronization in seconds
+ * @num_ports: Number of SPI ports to configure
+ *
+ * Returns Zero on success, negative of failure.
+ */
+int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout,
+                             int num_ports)
+{
+        int res = -1;
+
+        if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+                return res;
+
+        /* Callback to perform SPI4 reset */
+        INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode);
+
+        /* Callback to perform calendar setup */
+        INVOKE_CB(cvmx_spi_callbacks.calendar_setup_cb, interface, mode,
+                  num_ports);
+
+        /* Callback to perform clock detection */
+        INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
+
+        /* Callback to perform SPI4 link training */
+        INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout);
+
+        /* Callback to perform calendar sync */
+        INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode,
+                  timeout);
+
+        /* Callback to handle interface coming up */
+        INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode);
+
+        return res;
+}
+
+/**
+ * This routine restarts the SPI interface after it has lost synchronization
+ * with its correspondent system.
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for clock synchronization in seconds
+ *
+ * Returns Zero on success, negative of failure.
+ */
+int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
+{
+        int res = -1;
+
+        if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
+                return res;
+
+        cvmx_dprintf("SPI%d: Restart %s\n", interface, modes[mode]);
+
+        /* Callback to perform SPI4 reset */
+        INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode);
+
+        /* NOTE: Calendar setup is not performed during restart */
+        /*       Refer to cvmx_spi_start_interface() for the full sequence */
+
+        /* Callback to perform clock detection */
+        INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
+
+        /* Callback to perform SPI4 link training */
+        INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout);
+
+        /* Callback to perform calendar sync */
+        INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode,
+                  timeout);
+
+        /* Callback to handle interface coming up */
+        INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode);
+
+        return res;
+}
+
+/**
+ * Callback to perform SPI4 reset
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
+{
+        union cvmx_spxx_dbg_deskew_ctl spxx_dbg_deskew_ctl;
+        union cvmx_spxx_clk_ctl spxx_clk_ctl;
+        union cvmx_spxx_bist_stat spxx_bist_stat;
+        union cvmx_spxx_int_msk spxx_int_msk;
+        union cvmx_stxx_int_msk stxx_int_msk;
+        union cvmx_spxx_trn4_ctl spxx_trn4_ctl;
+        int index;
+        uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+
+        /* Disable SPI error events while we run BIST */
+        spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));
+        cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0);
+        stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));
+        cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0);
+
+        /* Run BIST in the SPI interface */
+        cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0);
+        cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0);
+        spxx_clk_ctl.u64 = 0;
+        spxx_clk_ctl.s.runbist = 1;
+        cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
+        cvmx_wait(10 * MS);
+        spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface));
+        if (spxx_bist_stat.s.stat0)
+                cvmx_dprintf
+                    ("ERROR SPI%d: BIST failed on receive datapath FIFO\n",
+                     interface);
+        if (spxx_bist_stat.s.stat1)
+                cvmx_dprintf("ERROR SPI%d: BIST failed on RX calendar table\n",
+                             interface);
+        if (spxx_bist_stat.s.stat2)
+                cvmx_dprintf("ERROR SPI%d: BIST failed on TX calendar table\n",
+                             interface);
+
+        /* Clear the calendar table after BIST to fix parity errors */
+        for (index = 0; index < 32; index++) {
+                union cvmx_srxx_spi4_calx srxx_spi4_calx;
+                union cvmx_stxx_spi4_calx stxx_spi4_calx;
+
+                srxx_spi4_calx.u64 = 0;
+                srxx_spi4_calx.s.oddpar = 1;
+                cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface),
+                               srxx_spi4_calx.u64);
+
+                stxx_spi4_calx.u64 = 0;
+                stxx_spi4_calx.s.oddpar = 1;
+                cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface),
+                               stxx_spi4_calx.u64);
+        }
+
+        /* Re enable reporting of error interrupts */
+        cvmx_write_csr(CVMX_SPXX_INT_REG(interface),
+                       cvmx_read_csr(CVMX_SPXX_INT_REG(interface)));
+        cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);
+        cvmx_write_csr(CVMX_STXX_INT_REG(interface),
+                       cvmx_read_csr(CVMX_STXX_INT_REG(interface)));
+        cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);
+
+        /* Setup the CLKDLY right in the middle */
+        spxx_clk_ctl.u64 = 0;
+        spxx_clk_ctl.s.seetrn = 0;
+        spxx_clk_ctl.s.clkdly = 0x10;
+        spxx_clk_ctl.s.runbist = 0;
+        spxx_clk_ctl.s.statdrv = 0;
+        /* This should always be on the opposite edge as statdrv */
+        spxx_clk_ctl.s.statrcv = 1;
+        spxx_clk_ctl.s.sndtrn = 0;
+        spxx_clk_ctl.s.drptrn = 0;
+        spxx_clk_ctl.s.rcvtrn = 0;
+        spxx_clk_ctl.s.srxdlck = 0;
+        cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
+        cvmx_wait(100 * MS);
+
+        /* Reset SRX0 DLL */
+        spxx_clk_ctl.s.srxdlck = 1;
+        cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
+
+        /* Waiting for Inf0 Spi4 RX DLL to lock */
+        cvmx_wait(100 * MS);
+
+        /* Enable dynamic alignment */
+        spxx_trn4_ctl.s.trntest = 0;
+        spxx_trn4_ctl.s.jitter = 1;
+        spxx_trn4_ctl.s.clr_boot = 1;
+        spxx_trn4_ctl.s.set_boot = 0;
+        if (OCTEON_IS_MODEL(OCTEON_CN58XX))
+                spxx_trn4_ctl.s.maxdist = 3;
+        else
+                spxx_trn4_ctl.s.maxdist = 8;
+        spxx_trn4_ctl.s.macro_en = 1;
+        spxx_trn4_ctl.s.mux_en = 1;
+        cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);
+
+        spxx_dbg_deskew_ctl.u64 = 0;
+        cvmx_write_csr(CVMX_SPXX_DBG_DESKEW_CTL(interface),
+                       spxx_dbg_deskew_ctl.u64);
+
+        return 0;
+}
+
+/**
+ * Callback to setup calendar and miscellaneous settings before clock detection
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @num_ports: Number of ports to configure on SPI
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
+                               int num_ports)
+{
+        int port;
+        int index;
+        if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
+                union cvmx_srxx_com_ctl srxx_com_ctl;
+                union cvmx_srxx_spi4_stat srxx_spi4_stat;
+
+                /* SRX0 number of Ports */
+                srxx_com_ctl.u64 = 0;
+                srxx_com_ctl.s.prts = num_ports - 1;
+                srxx_com_ctl.s.st_en = 0;
+                srxx_com_ctl.s.inf_en = 0;
+                cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
+
+                /* SRX0 Calendar Table. This round robbins through all ports */
+                port = 0;
+                index = 0;
+                while (port < num_ports) {
+                        union cvmx_srxx_spi4_calx srxx_spi4_calx;
+                        srxx_spi4_calx.u64 = 0;
+                        srxx_spi4_calx.s.prt0 = port++;
+                        srxx_spi4_calx.s.prt1 = port++;
+                        srxx_spi4_calx.s.prt2 = port++;
+                        srxx_spi4_calx.s.prt3 = port++;
+                        srxx_spi4_calx.s.oddpar =
+                            ~(cvmx_dpop(srxx_spi4_calx.u64) & 1);
+                        cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface),
+                                       srxx_spi4_calx.u64);
+                        index++;
+                }
+                srxx_spi4_stat.u64 = 0;
+                srxx_spi4_stat.s.len = num_ports;
+                srxx_spi4_stat.s.m = 1;
+                cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface),
+                               srxx_spi4_stat.u64);
+        }
+
+        if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
+                union cvmx_stxx_arb_ctl stxx_arb_ctl;
+                union cvmx_gmxx_tx_spi_max gmxx_tx_spi_max;
+                union cvmx_gmxx_tx_spi_thresh gmxx_tx_spi_thresh;
+                union cvmx_gmxx_tx_spi_ctl gmxx_tx_spi_ctl;
+                union cvmx_stxx_spi4_stat stxx_spi4_stat;
+                union cvmx_stxx_spi4_dat stxx_spi4_dat;
+
+                /* STX0 Config */
+                stxx_arb_ctl.u64 = 0;
+                stxx_arb_ctl.s.igntpa = 0;
+                stxx_arb_ctl.s.mintrn = 0;
+                cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64);
+
+                gmxx_tx_spi_max.u64 = 0;
+                gmxx_tx_spi_max.s.max1 = 8;
+                gmxx_tx_spi_max.s.max2 = 4;
+                gmxx_tx_spi_max.s.slice = 0;
+                cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface),
+                               gmxx_tx_spi_max.u64);
+
+                gmxx_tx_spi_thresh.u64 = 0;
+                gmxx_tx_spi_thresh.s.thresh = 4;
+                cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface),
+                               gmxx_tx_spi_thresh.u64);
+
+                gmxx_tx_spi_ctl.u64 = 0;
+                gmxx_tx_spi_ctl.s.tpa_clr = 0;
+                gmxx_tx_spi_ctl.s.cont_pkt = 0;
+                cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface),
+                               gmxx_tx_spi_ctl.u64);
+
+                /* STX0 Training Control */
+                stxx_spi4_dat.u64 = 0;
+                /*Minimum needed by dynamic alignment */
+                stxx_spi4_dat.s.alpha = 32;
+                stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */
+                cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface),
+                               stxx_spi4_dat.u64);
+
+                /* STX0 Calendar Table. This round robbins through all ports */
+                port = 0;
+                index = 0;
+                while (port < num_ports) {
+                        union cvmx_stxx_spi4_calx stxx_spi4_calx;
+                        stxx_spi4_calx.u64 = 0;
+                        stxx_spi4_calx.s.prt0 = port++;
+                        stxx_spi4_calx.s.prt1 = port++;
+                        stxx_spi4_calx.s.prt2 = port++;
+                        stxx_spi4_calx.s.prt3 = port++;
+                        stxx_spi4_calx.s.oddpar =
+                            ~(cvmx_dpop(stxx_spi4_calx.u64) & 1);
+                        cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface),
+                                       stxx_spi4_calx.u64);
+                        index++;
+                }
+                stxx_spi4_stat.u64 = 0;
+                stxx_spi4_stat.s.len = num_ports;
+                stxx_spi4_stat.s.m = 1;
+                cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface),
+                               stxx_spi4_stat.u64);
+        }
+
+        return 0;
+}
+
+/**
+ * Callback to perform clock detection
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for clock synchronization in seconds
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout)
+{
+        int clock_transitions;
+        union cvmx_spxx_clk_stat stat;
+        uint64_t timeout_time;
+        uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+
+        /*
+         * Regardless of operating mode, both Tx and Rx clocks must be
+         * present for the SPI interface to operate.
+         */
+        cvmx_dprintf("SPI%d: Waiting to see TsClk...\n", interface);
+        timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
+        /*
+         * Require 100 clock transitions in order to avoid any noise
+         * in the beginning.
+         */
+        clock_transitions = 100;
+        do {
+                stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
+                if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) {
+                        /*
+                         * We've seen a clock transition, so decrement
+                         * the number we still need.
+                         */
+                        clock_transitions--;
+                        cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
+                        stat.s.s4clk0 = 0;
+                        stat.s.s4clk1 = 0;
+                }
+                if (cvmx_get_cycle() > timeout_time) {
+                        cvmx_dprintf("SPI%d: Timeout\n", interface);
+                        return -1;
+                }
+        } while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0);
+
+        cvmx_dprintf("SPI%d: Waiting to see RsClk...\n", interface);
+        timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
+        /*
+         * Require 100 clock transitions in order to avoid any noise in the
+         * beginning.
+         */
+        clock_transitions = 100;
+        do {
+                stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
+                if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) {
+                        /*
+                         * We've seen a clock transition, so decrement
+                         * the number we still need
+                         */
+                        clock_transitions--;
+                        cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
+                        stat.s.d4clk0 = 0;
+                        stat.s.d4clk1 = 0;
+                }
+                if (cvmx_get_cycle() > timeout_time) {
+                        cvmx_dprintf("SPI%d: Timeout\n", interface);
+                        return -1;
+                }
+        } while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0);
+
+        return 0;
+}
+
+/**
+ * Callback to perform link training
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for link to be trained (in seconds)
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
+{
+        union cvmx_spxx_trn4_ctl spxx_trn4_ctl;
+        union cvmx_spxx_clk_stat stat;
+        uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+        uint64_t timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
+        int rx_training_needed;
+
+        /* SRX0 & STX0 Inf0 Links are configured - begin training */
+        union cvmx_spxx_clk_ctl spxx_clk_ctl;
+        spxx_clk_ctl.u64 = 0;
+        spxx_clk_ctl.s.seetrn = 0;
+        spxx_clk_ctl.s.clkdly = 0x10;
+        spxx_clk_ctl.s.runbist = 0;
+        spxx_clk_ctl.s.statdrv = 0;
+        /* This should always be on the opposite edge as statdrv */
+        spxx_clk_ctl.s.statrcv = 1;
+        spxx_clk_ctl.s.sndtrn = 1;
+        spxx_clk_ctl.s.drptrn = 1;
+        spxx_clk_ctl.s.rcvtrn = 1;
+        spxx_clk_ctl.s.srxdlck = 1;
+        cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64);
+        cvmx_wait(1000 * MS);
+
+        /* SRX0 clear the boot bit */
+        spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface));
+        spxx_trn4_ctl.s.clr_boot = 1;
+        cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64);
+
+        /* Wait for the training sequence to complete */
+        cvmx_dprintf("SPI%d: Waiting for training\n", interface);
+        cvmx_wait(1000 * MS);
+        /* Wait a really long time here */
+        timeout_time = cvmx_get_cycle() + 1000ull * MS * 600;
+        /*
+         * The HRM says we must wait for 34 + 16 * MAXDIST training sequences.
+         * We'll be pessimistic and wait for a lot more.
+         */
+        rx_training_needed = 500;
+        do {
+                stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
+                if (stat.s.srxtrn && rx_training_needed) {
+                        rx_training_needed--;
+                        cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64);
+                        stat.s.srxtrn = 0;
+                }
+                if (cvmx_get_cycle() > timeout_time) {
+                        cvmx_dprintf("SPI%d: Timeout\n", interface);
+                        return -1;
+                }
+        } while (stat.s.srxtrn == 0);
+
+        return 0;
+}
+
+/**
+ * Callback to perform calendar data synchronization
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for calendar data in seconds
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout)
+{
+        uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000;
+        if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
+                /* SRX0 interface should be good, send calendar data */
+                union cvmx_srxx_com_ctl srxx_com_ctl;
+                cvmx_dprintf
+                    ("SPI%d: Rx is synchronized, start sending calendar data\n",
+                     interface);
+                srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
+                srxx_com_ctl.s.inf_en = 1;
+                srxx_com_ctl.s.st_en = 1;
+                cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
+        }
+
+        if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
+                /* STX0 has achieved sync */
+                /* The corespondant board should be sending calendar data */
+                /* Enable the STX0 STAT receiver. */
+                union cvmx_spxx_clk_stat stat;
+                uint64_t timeout_time;
+                union cvmx_stxx_com_ctl stxx_com_ctl;
+                stxx_com_ctl.u64 = 0;
+                stxx_com_ctl.s.st_en = 1;
+                cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);
+
+                /* Waiting for calendar sync on STX0 STAT */
+                cvmx_dprintf("SPI%d: Waiting to sync on STX[%d] STAT\n",
+                             interface, interface);
+                timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout;
+                /* SPX0_CLK_STAT - SPX0_CLK_STAT[STXCAL] should be 1 (bit10) */
+                do {
+                        stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface));
+                        if (cvmx_get_cycle() > timeout_time) {
+                                cvmx_dprintf("SPI%d: Timeout\n", interface);
+                                return -1;
+                        }
+                } while (stat.s.stxcal == 0);
+        }
+
+        return 0;
+}
+
+/**
+ * Callback to handle interface up
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode)
+{
+        union cvmx_gmxx_rxx_frm_min gmxx_rxx_frm_min;
+        union cvmx_gmxx_rxx_frm_max gmxx_rxx_frm_max;
+        union cvmx_gmxx_rxx_jabber gmxx_rxx_jabber;
+
+        if (mode & CVMX_SPI_MODE_RX_HALFPLEX) {
+                union cvmx_srxx_com_ctl srxx_com_ctl;
+                srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface));
+                srxx_com_ctl.s.inf_en = 1;
+                cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64);
+                cvmx_dprintf("SPI%d: Rx is now up\n", interface);
+        }
+
+        if (mode & CVMX_SPI_MODE_TX_HALFPLEX) {
+                union cvmx_stxx_com_ctl stxx_com_ctl;
+                stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface));
+                stxx_com_ctl.s.inf_en = 1;
+                cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64);
+                cvmx_dprintf("SPI%d: Tx is now up\n", interface);
+        }
+
+        gmxx_rxx_frm_min.u64 = 0;
+        gmxx_rxx_frm_min.s.len = 64;
+        cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0, interface),
+                       gmxx_rxx_frm_min.u64);
+        gmxx_rxx_frm_max.u64 = 0;
+        gmxx_rxx_frm_max.s.len = 64 * 1024 - 4;
+        cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0, interface),
+                       gmxx_rxx_frm_max.u64);
+        gmxx_rxx_jabber.u64 = 0;
+        gmxx_rxx_jabber.s.cnt = 64 * 1024 - 4;
+        cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0, interface), gmxx_rxx_jabber.u64);
+
+        return 0;
+}
diff --git a/drivers/staging/octeon/cvmx-spi.h b/drivers/staging/octeon/cvmx-spi.h
new file mode 100644
index 000000000000..e814648953a5
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-spi.h
@@ -0,0 +1,269 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/*
+ *
+ * This file contains defines for the SPI interface
+ */
+#ifndef __CVMX_SPI_H__
+#define __CVMX_SPI_H__
+
+#include "cvmx-gmxx-defs.h"
+
+/* CSR typedefs have been moved to cvmx-csr-*.h */
+
+typedef enum {
+        CVMX_SPI_MODE_UNKNOWN = 0,
+        CVMX_SPI_MODE_TX_HALFPLEX = 1,
+        CVMX_SPI_MODE_RX_HALFPLEX = 2,
+        CVMX_SPI_MODE_DUPLEX = 3
+} cvmx_spi_mode_t;
+
+/** Callbacks structure to customize SPI4 initialization sequence */
+typedef struct {
+    /** Called to reset SPI4 DLL */
+        int (*reset_cb) (int interface, cvmx_spi_mode_t mode);
+
+    /** Called to setup calendar */
+        int (*calendar_setup_cb) (int interface, cvmx_spi_mode_t mode,
+                                  int num_ports);
+
+    /** Called for Tx and Rx clock detection */
+        int (*clock_detect_cb) (int interface, cvmx_spi_mode_t mode,
+                                int timeout);
+
+    /** Called to perform link training */
+        int (*training_cb) (int interface, cvmx_spi_mode_t mode, int timeout);
+
+    /** Called for calendar data synchronization */
+        int (*calendar_sync_cb) (int interface, cvmx_spi_mode_t mode,
+                                 int timeout);
+
+    /** Called when interface is up */
+        int (*interface_up_cb) (int interface, cvmx_spi_mode_t mode);
+
+} cvmx_spi_callbacks_t;
+
+/**
+ * Return true if the supplied interface is configured for SPI
+ *
+ * @interface: Interface to check
+ * Returns True if interface is SPI
+ */
+static inline int cvmx_spi_is_spi_interface(int interface)
+{
+        uint64_t gmxState = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
+        return (gmxState & 0x2) && (gmxState & 0x1);
+}
+
+/**
+ * Initialize and start the SPI interface.
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for clock synchronization in seconds
+ * @num_ports: Number of SPI ports to configure
+ *
+ * Returns Zero on success, negative of failure.
+ */
+extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode,
+                                    int timeout, int num_ports);
+
+/**
+ * This routine restarts the SPI interface after it has lost synchronization
+ * with its corespondant system.
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for clock synchronization in seconds
+ * Returns Zero on success, negative of failure.
+ */
+extern int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode,
+                                      int timeout);
+
+/**
+ * Return non-zero if the SPI interface has a SPI4000 attached
+ *
+ * @interface: SPI interface the SPI4000 is connected to
+ *
+ * Returns
+ */
+static inline int cvmx_spi4000_is_present(int interface)
+{
+        return 0;
+}
+
+/**
+ * Initialize the SPI4000 for use
+ *
+ * @interface: SPI interface the SPI4000 is connected to
+ */
+static inline int cvmx_spi4000_initialize(int interface)
+{
+        return 0;
+}
+
+/**
+ * Poll all the SPI4000 port and check its speed
+ *
+ * @interface: Interface the SPI4000 is on
+ * @port:      Port to poll (0-9)
+ * Returns Status of the port. 0=down. All other values the port is up.
+ */
+static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
+        int interface,
+        int port)
+{
+        union cvmx_gmxx_rxx_rx_inbnd r;
+        r.u64 = 0;
+        return r;
+}
+
+/**
+ * Get current SPI4 initialization callbacks
+ *
+ * @callbacks:  Pointer to the callbacks structure.to fill
+ *
+ * Returns Pointer to cvmx_spi_callbacks_t structure.
+ */
+extern void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks);
+
+/**
+ * Set new SPI4 initialization callbacks
+ *
+ * @new_callbacks:  Pointer to an updated callbacks structure.
+ */
+extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks);
+
+/**
+ * Callback to perform SPI4 reset
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode);
+
+/**
+ * Callback to setup calendar and miscellaneous settings before clock
+ * detection
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @num_ports: Number of ports to configure on SPI
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
+                                      int num_ports);
+
+/**
+ * Callback to perform clock detection
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for clock synchronization in seconds
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode,
+                                    int timeout);
+
+/**
+ * Callback to perform link training
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for link to be trained (in seconds)
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode,
+                                int timeout);
+
+/**
+ * Callback to perform calendar data synchronization
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ * @timeout:   Timeout to wait for calendar data in seconds
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode,
+                                     int timeout);
+
+/**
+ * Callback to handle interface up
+ *
+ * @interface: The identifier of the packet interface to configure and
+ *                  use as a SPI interface.
+ * @mode:      The operating mode for the SPI interface. The interface
+ *                  can operate as a full duplex (both Tx and Rx data paths
+ *                  active) or as a halfplex (either the Tx data path is
+ *                  active or the Rx data path is active, but not both).
+ *
+ * Returns Zero on success, non-zero error code on failure (will cause
+ * SPI initialization to abort)
+ */
+extern int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode);
+
+#endif /* __CVMX_SPI_H__ */
diff --git a/drivers/staging/octeon/cvmx-spxx-defs.h b/drivers/staging/octeon/cvmx-spxx-defs.h
new file mode 100644
index 000000000000..b16940e32c83
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-spxx-defs.h
@@ -0,0 +1,347 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SPXX_DEFS_H__
+#define __CVMX_SPXX_DEFS_H__
+
+#define CVMX_SPXX_BCKPRS_CNT(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000340ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_BIST_STAT(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800900007F8ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_CLK_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000348ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_CLK_STAT(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000350ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_DBG_DESKEW_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000368ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_DBG_DESKEW_STATE(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000370ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_DRV_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000358ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_ERR_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000320ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_INT_DAT(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000318ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_INT_MSK(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000308ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_INT_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000300ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_INT_SYNC(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000310ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_TPA_ACC(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000338ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_TPA_MAX(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000330ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_TPA_SEL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000328ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SPXX_TRN4_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000360ull + (((block_id) & 1) * 0x8000000ull))
+
+union cvmx_spxx_bckprs_cnt {
+        uint64_t u64;
+        struct cvmx_spxx_bckprs_cnt_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_spxx_bckprs_cnt_s cn38xx;
+        struct cvmx_spxx_bckprs_cnt_s cn38xxp2;
+        struct cvmx_spxx_bckprs_cnt_s cn58xx;
+        struct cvmx_spxx_bckprs_cnt_s cn58xxp1;
+};
+
+union cvmx_spxx_bist_stat {
+        uint64_t u64;
+        struct cvmx_spxx_bist_stat_s {
+                uint64_t reserved_3_63:61;
+                uint64_t stat2:1;
+                uint64_t stat1:1;
+                uint64_t stat0:1;
+        } s;
+        struct cvmx_spxx_bist_stat_s cn38xx;
+        struct cvmx_spxx_bist_stat_s cn38xxp2;
+        struct cvmx_spxx_bist_stat_s cn58xx;
+        struct cvmx_spxx_bist_stat_s cn58xxp1;
+};
+
+union cvmx_spxx_clk_ctl {
+        uint64_t u64;
+        struct cvmx_spxx_clk_ctl_s {
+                uint64_t reserved_17_63:47;
+                uint64_t seetrn:1;
+                uint64_t reserved_12_15:4;
+                uint64_t clkdly:5;
+                uint64_t runbist:1;
+                uint64_t statdrv:1;
+                uint64_t statrcv:1;
+                uint64_t sndtrn:1;
+                uint64_t drptrn:1;
+                uint64_t rcvtrn:1;
+                uint64_t srxdlck:1;
+        } s;
+        struct cvmx_spxx_clk_ctl_s cn38xx;
+        struct cvmx_spxx_clk_ctl_s cn38xxp2;
+        struct cvmx_spxx_clk_ctl_s cn58xx;
+        struct cvmx_spxx_clk_ctl_s cn58xxp1;
+};
+
+union cvmx_spxx_clk_stat {
+        uint64_t u64;
+        struct cvmx_spxx_clk_stat_s {
+                uint64_t reserved_11_63:53;
+                uint64_t stxcal:1;
+                uint64_t reserved_9_9:1;
+                uint64_t srxtrn:1;
+                uint64_t s4clk1:1;
+                uint64_t s4clk0:1;
+                uint64_t d4clk1:1;
+                uint64_t d4clk0:1;
+                uint64_t reserved_0_3:4;
+        } s;
+        struct cvmx_spxx_clk_stat_s cn38xx;
+        struct cvmx_spxx_clk_stat_s cn38xxp2;
+        struct cvmx_spxx_clk_stat_s cn58xx;
+        struct cvmx_spxx_clk_stat_s cn58xxp1;
+};
+
+union cvmx_spxx_dbg_deskew_ctl {
+        uint64_t u64;
+        struct cvmx_spxx_dbg_deskew_ctl_s {
+                uint64_t reserved_30_63:34;
+                uint64_t fallnop:1;
+                uint64_t fall8:1;
+                uint64_t reserved_26_27:2;
+                uint64_t sstep_go:1;
+                uint64_t sstep:1;
+                uint64_t reserved_22_23:2;
+                uint64_t clrdly:1;
+                uint64_t dec:1;
+                uint64_t inc:1;
+                uint64_t mux:1;
+                uint64_t offset:5;
+                uint64_t bitsel:5;
+                uint64_t offdly:6;
+                uint64_t dllfrc:1;
+                uint64_t dlldis:1;
+        } s;
+        struct cvmx_spxx_dbg_deskew_ctl_s cn38xx;
+        struct cvmx_spxx_dbg_deskew_ctl_s cn38xxp2;
+        struct cvmx_spxx_dbg_deskew_ctl_s cn58xx;
+        struct cvmx_spxx_dbg_deskew_ctl_s cn58xxp1;
+};
+
+union cvmx_spxx_dbg_deskew_state {
+        uint64_t u64;
+        struct cvmx_spxx_dbg_deskew_state_s {
+                uint64_t reserved_9_63:55;
+                uint64_t testres:1;
+                uint64_t unxterm:1;
+                uint64_t muxsel:2;
+                uint64_t offset:5;
+        } s;
+        struct cvmx_spxx_dbg_deskew_state_s cn38xx;
+        struct cvmx_spxx_dbg_deskew_state_s cn38xxp2;
+        struct cvmx_spxx_dbg_deskew_state_s cn58xx;
+        struct cvmx_spxx_dbg_deskew_state_s cn58xxp1;
+};
+
+union cvmx_spxx_drv_ctl {
+        uint64_t u64;
+        struct cvmx_spxx_drv_ctl_s {
+                uint64_t reserved_0_63:64;
+        } s;
+        struct cvmx_spxx_drv_ctl_cn38xx {
+                uint64_t reserved_16_63:48;
+                uint64_t stx4ncmp:4;
+                uint64_t stx4pcmp:4;
+                uint64_t srx4cmp:8;
+        } cn38xx;
+        struct cvmx_spxx_drv_ctl_cn38xx cn38xxp2;
+        struct cvmx_spxx_drv_ctl_cn58xx {
+                uint64_t reserved_24_63:40;
+                uint64_t stx4ncmp:4;
+                uint64_t stx4pcmp:4;
+                uint64_t reserved_10_15:6;
+                uint64_t srx4cmp:10;
+        } cn58xx;
+        struct cvmx_spxx_drv_ctl_cn58xx cn58xxp1;
+};
+
+union cvmx_spxx_err_ctl {
+        uint64_t u64;
+        struct cvmx_spxx_err_ctl_s {
+                uint64_t reserved_9_63:55;
+                uint64_t prtnxa:1;
+                uint64_t dipcls:1;
+                uint64_t dippay:1;
+                uint64_t reserved_4_5:2;
+                uint64_t errcnt:4;
+        } s;
+        struct cvmx_spxx_err_ctl_s cn38xx;
+        struct cvmx_spxx_err_ctl_s cn38xxp2;
+        struct cvmx_spxx_err_ctl_s cn58xx;
+        struct cvmx_spxx_err_ctl_s cn58xxp1;
+};
+
+union cvmx_spxx_int_dat {
+        uint64_t u64;
+        struct cvmx_spxx_int_dat_s {
+                uint64_t reserved_32_63:32;
+                uint64_t mul:1;
+                uint64_t reserved_14_30:17;
+                uint64_t calbnk:2;
+                uint64_t rsvop:4;
+                uint64_t prt:8;
+        } s;
+        struct cvmx_spxx_int_dat_s cn38xx;
+        struct cvmx_spxx_int_dat_s cn38xxp2;
+        struct cvmx_spxx_int_dat_s cn58xx;
+        struct cvmx_spxx_int_dat_s cn58xxp1;
+};
+
+union cvmx_spxx_int_msk {
+        uint64_t u64;
+        struct cvmx_spxx_int_msk_s {
+                uint64_t reserved_12_63:52;
+                uint64_t calerr:1;
+                uint64_t syncerr:1;
+                uint64_t diperr:1;
+                uint64_t tpaovr:1;
+                uint64_t rsverr:1;
+                uint64_t drwnng:1;
+                uint64_t clserr:1;
+                uint64_t spiovr:1;
+                uint64_t reserved_2_3:2;
+                uint64_t abnorm:1;
+                uint64_t prtnxa:1;
+        } s;
+        struct cvmx_spxx_int_msk_s cn38xx;
+        struct cvmx_spxx_int_msk_s cn38xxp2;
+        struct cvmx_spxx_int_msk_s cn58xx;
+        struct cvmx_spxx_int_msk_s cn58xxp1;
+};
+
+union cvmx_spxx_int_reg {
+        uint64_t u64;
+        struct cvmx_spxx_int_reg_s {
+                uint64_t reserved_32_63:32;
+                uint64_t spf:1;
+                uint64_t reserved_12_30:19;
+                uint64_t calerr:1;
+                uint64_t syncerr:1;
+                uint64_t diperr:1;
+                uint64_t tpaovr:1;
+                uint64_t rsverr:1;
+                uint64_t drwnng:1;
+                uint64_t clserr:1;
+                uint64_t spiovr:1;
+                uint64_t reserved_2_3:2;
+                uint64_t abnorm:1;
+                uint64_t prtnxa:1;
+        } s;
+        struct cvmx_spxx_int_reg_s cn38xx;
+        struct cvmx_spxx_int_reg_s cn38xxp2;
+        struct cvmx_spxx_int_reg_s cn58xx;
+        struct cvmx_spxx_int_reg_s cn58xxp1;
+};
+
+union cvmx_spxx_int_sync {
+        uint64_t u64;
+        struct cvmx_spxx_int_sync_s {
+                uint64_t reserved_12_63:52;
+                uint64_t calerr:1;
+                uint64_t syncerr:1;
+                uint64_t diperr:1;
+                uint64_t tpaovr:1;
+                uint64_t rsverr:1;
+                uint64_t drwnng:1;
+                uint64_t clserr:1;
+                uint64_t spiovr:1;
+                uint64_t reserved_2_3:2;
+                uint64_t abnorm:1;
+                uint64_t prtnxa:1;
+        } s;
+        struct cvmx_spxx_int_sync_s cn38xx;
+        struct cvmx_spxx_int_sync_s cn38xxp2;
+        struct cvmx_spxx_int_sync_s cn58xx;
+        struct cvmx_spxx_int_sync_s cn58xxp1;
+};
+
+union cvmx_spxx_tpa_acc {
+        uint64_t u64;
+        struct cvmx_spxx_tpa_acc_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_spxx_tpa_acc_s cn38xx;
+        struct cvmx_spxx_tpa_acc_s cn38xxp2;
+        struct cvmx_spxx_tpa_acc_s cn58xx;
+        struct cvmx_spxx_tpa_acc_s cn58xxp1;
+};
+
+union cvmx_spxx_tpa_max {
+        uint64_t u64;
+        struct cvmx_spxx_tpa_max_s {
+                uint64_t reserved_32_63:32;
+                uint64_t max:32;
+        } s;
+        struct cvmx_spxx_tpa_max_s cn38xx;
+        struct cvmx_spxx_tpa_max_s cn38xxp2;
+        struct cvmx_spxx_tpa_max_s cn58xx;
+        struct cvmx_spxx_tpa_max_s cn58xxp1;
+};
+
+union cvmx_spxx_tpa_sel {
+        uint64_t u64;
+        struct cvmx_spxx_tpa_sel_s {
+                uint64_t reserved_4_63:60;
+                uint64_t prtsel:4;
+        } s;
+        struct cvmx_spxx_tpa_sel_s cn38xx;
+        struct cvmx_spxx_tpa_sel_s cn38xxp2;
+        struct cvmx_spxx_tpa_sel_s cn58xx;
+        struct cvmx_spxx_tpa_sel_s cn58xxp1;
+};
+
+union cvmx_spxx_trn4_ctl {
+        uint64_t u64;
+        struct cvmx_spxx_trn4_ctl_s {
+                uint64_t reserved_13_63:51;
+                uint64_t trntest:1;
+                uint64_t jitter:3;
+                uint64_t clr_boot:1;
+                uint64_t set_boot:1;
+                uint64_t maxdist:5;
+                uint64_t macro_en:1;
+                uint64_t mux_en:1;
+        } s;
+        struct cvmx_spxx_trn4_ctl_s cn38xx;
+        struct cvmx_spxx_trn4_ctl_s cn38xxp2;
+        struct cvmx_spxx_trn4_ctl_s cn58xx;
+        struct cvmx_spxx_trn4_ctl_s cn58xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-srxx-defs.h b/drivers/staging/octeon/cvmx-srxx-defs.h
new file mode 100644
index 000000000000..d82b366c279f
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-srxx-defs.h
@@ -0,0 +1,126 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_SRXX_DEFS_H__
+#define __CVMX_SRXX_DEFS_H__
+
+#define CVMX_SRXX_COM_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000200ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SRXX_IGN_RX_FULL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000218ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SRXX_SPI4_CALX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000000ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SRXX_SPI4_STAT(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000208ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SRXX_SW_TICK_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000220ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_SRXX_SW_TICK_DAT(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000228ull + (((block_id) & 1) * 0x8000000ull))
+
+union cvmx_srxx_com_ctl {
+        uint64_t u64;
+        struct cvmx_srxx_com_ctl_s {
+                uint64_t reserved_8_63:56;
+                uint64_t prts:4;
+                uint64_t st_en:1;
+                uint64_t reserved_1_2:2;
+                uint64_t inf_en:1;
+        } s;
+        struct cvmx_srxx_com_ctl_s cn38xx;
+        struct cvmx_srxx_com_ctl_s cn38xxp2;
+        struct cvmx_srxx_com_ctl_s cn58xx;
+        struct cvmx_srxx_com_ctl_s cn58xxp1;
+};
+
+union cvmx_srxx_ign_rx_full {
+        uint64_t u64;
+        struct cvmx_srxx_ign_rx_full_s {
+                uint64_t reserved_16_63:48;
+                uint64_t ignore:16;
+        } s;
+        struct cvmx_srxx_ign_rx_full_s cn38xx;
+        struct cvmx_srxx_ign_rx_full_s cn38xxp2;
+        struct cvmx_srxx_ign_rx_full_s cn58xx;
+        struct cvmx_srxx_ign_rx_full_s cn58xxp1;
+};
+
+union cvmx_srxx_spi4_calx {
+        uint64_t u64;
+        struct cvmx_srxx_spi4_calx_s {
+                uint64_t reserved_17_63:47;
+                uint64_t oddpar:1;
+                uint64_t prt3:4;
+                uint64_t prt2:4;
+                uint64_t prt1:4;
+                uint64_t prt0:4;
+        } s;
+        struct cvmx_srxx_spi4_calx_s cn38xx;
+        struct cvmx_srxx_spi4_calx_s cn38xxp2;
+        struct cvmx_srxx_spi4_calx_s cn58xx;
+        struct cvmx_srxx_spi4_calx_s cn58xxp1;
+};
+
+union cvmx_srxx_spi4_stat {
+        uint64_t u64;
+        struct cvmx_srxx_spi4_stat_s {
+                uint64_t reserved_16_63:48;
+                uint64_t m:8;
+                uint64_t reserved_7_7:1;
+                uint64_t len:7;
+        } s;
+        struct cvmx_srxx_spi4_stat_s cn38xx;
+        struct cvmx_srxx_spi4_stat_s cn38xxp2;
+        struct cvmx_srxx_spi4_stat_s cn58xx;
+        struct cvmx_srxx_spi4_stat_s cn58xxp1;
+};
+
+union cvmx_srxx_sw_tick_ctl {
+        uint64_t u64;
+        struct cvmx_srxx_sw_tick_ctl_s {
+                uint64_t reserved_14_63:50;
+                uint64_t eop:1;
+                uint64_t sop:1;
+                uint64_t mod:4;
+                uint64_t opc:4;
+                uint64_t adr:4;
+        } s;
+        struct cvmx_srxx_sw_tick_ctl_s cn38xx;
+        struct cvmx_srxx_sw_tick_ctl_s cn58xx;
+        struct cvmx_srxx_sw_tick_ctl_s cn58xxp1;
+};
+
+union cvmx_srxx_sw_tick_dat {
+        uint64_t u64;
+        struct cvmx_srxx_sw_tick_dat_s {
+                uint64_t dat:64;
+        } s;
+        struct cvmx_srxx_sw_tick_dat_s cn38xx;
+        struct cvmx_srxx_sw_tick_dat_s cn58xx;
+        struct cvmx_srxx_sw_tick_dat_s cn58xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-stxx-defs.h b/drivers/staging/octeon/cvmx-stxx-defs.h
new file mode 100644
index 000000000000..4f209b62cae1
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-stxx-defs.h
@@ -0,0 +1,292 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_STXX_DEFS_H__
+#define __CVMX_STXX_DEFS_H__
+
+#define CVMX_STXX_ARB_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000608ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_BCKPRS_CNT(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000688ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_COM_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000600ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_DIP_CNT(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000690ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_IGN_CAL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000610ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_INT_MSK(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800900006A0ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_INT_REG(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000698ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_INT_SYNC(block_id) \
+         CVMX_ADD_IO_SEG(0x00011800900006A8ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_MIN_BST(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000618ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_SPI4_CALX(offset, block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000400ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_SPI4_DAT(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000628ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_SPI4_STAT(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000630ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_STAT_BYTES_HI(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000648ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_STAT_BYTES_LO(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000680ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_STAT_CTL(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000638ull + (((block_id) & 1) * 0x8000000ull))
+#define CVMX_STXX_STAT_PKT_XMT(block_id) \
+         CVMX_ADD_IO_SEG(0x0001180090000640ull + (((block_id) & 1) * 0x8000000ull))
+
+union cvmx_stxx_arb_ctl {
+        uint64_t u64;
+        struct cvmx_stxx_arb_ctl_s {
+                uint64_t reserved_6_63:58;
+                uint64_t mintrn:1;
+                uint64_t reserved_4_4:1;
+                uint64_t igntpa:1;
+                uint64_t reserved_0_2:3;
+        } s;
+        struct cvmx_stxx_arb_ctl_s cn38xx;
+        struct cvmx_stxx_arb_ctl_s cn38xxp2;
+        struct cvmx_stxx_arb_ctl_s cn58xx;
+        struct cvmx_stxx_arb_ctl_s cn58xxp1;
+};
+
+union cvmx_stxx_bckprs_cnt {
+        uint64_t u64;
+        struct cvmx_stxx_bckprs_cnt_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_stxx_bckprs_cnt_s cn38xx;
+        struct cvmx_stxx_bckprs_cnt_s cn38xxp2;
+        struct cvmx_stxx_bckprs_cnt_s cn58xx;
+        struct cvmx_stxx_bckprs_cnt_s cn58xxp1;
+};
+
+union cvmx_stxx_com_ctl {
+        uint64_t u64;
+        struct cvmx_stxx_com_ctl_s {
+                uint64_t reserved_4_63:60;
+                uint64_t st_en:1;
+                uint64_t reserved_1_2:2;
+                uint64_t inf_en:1;
+        } s;
+        struct cvmx_stxx_com_ctl_s cn38xx;
+        struct cvmx_stxx_com_ctl_s cn38xxp2;
+        struct cvmx_stxx_com_ctl_s cn58xx;
+        struct cvmx_stxx_com_ctl_s cn58xxp1;
+};
+
+union cvmx_stxx_dip_cnt {
+        uint64_t u64;
+        struct cvmx_stxx_dip_cnt_s {
+                uint64_t reserved_8_63:56;
+                uint64_t frmmax:4;
+                uint64_t dipmax:4;
+        } s;
+        struct cvmx_stxx_dip_cnt_s cn38xx;
+        struct cvmx_stxx_dip_cnt_s cn38xxp2;
+        struct cvmx_stxx_dip_cnt_s cn58xx;
+        struct cvmx_stxx_dip_cnt_s cn58xxp1;
+};
+
+union cvmx_stxx_ign_cal {
+        uint64_t u64;
+        struct cvmx_stxx_ign_cal_s {
+                uint64_t reserved_16_63:48;
+                uint64_t igntpa:16;
+        } s;
+        struct cvmx_stxx_ign_cal_s cn38xx;
+        struct cvmx_stxx_ign_cal_s cn38xxp2;
+        struct cvmx_stxx_ign_cal_s cn58xx;
+        struct cvmx_stxx_ign_cal_s cn58xxp1;
+};
+
+union cvmx_stxx_int_msk {
+        uint64_t u64;
+        struct cvmx_stxx_int_msk_s {
+                uint64_t reserved_8_63:56;
+                uint64_t frmerr:1;
+                uint64_t unxfrm:1;
+                uint64_t nosync:1;
+                uint64_t diperr:1;
+                uint64_t datovr:1;
+                uint64_t ovrbst:1;
+                uint64_t calpar1:1;
+                uint64_t calpar0:1;
+        } s;
+        struct cvmx_stxx_int_msk_s cn38xx;
+        struct cvmx_stxx_int_msk_s cn38xxp2;
+        struct cvmx_stxx_int_msk_s cn58xx;
+        struct cvmx_stxx_int_msk_s cn58xxp1;
+};
+
+union cvmx_stxx_int_reg {
+        uint64_t u64;
+        struct cvmx_stxx_int_reg_s {
+                uint64_t reserved_9_63:55;
+                uint64_t syncerr:1;
+                uint64_t frmerr:1;
+                uint64_t unxfrm:1;
+                uint64_t nosync:1;
+                uint64_t diperr:1;
+                uint64_t datovr:1;
+                uint64_t ovrbst:1;
+                uint64_t calpar1:1;
+                uint64_t calpar0:1;
+        } s;
+        struct cvmx_stxx_int_reg_s cn38xx;
+        struct cvmx_stxx_int_reg_s cn38xxp2;
+        struct cvmx_stxx_int_reg_s cn58xx;
+        struct cvmx_stxx_int_reg_s cn58xxp1;
+};
+
+union cvmx_stxx_int_sync {
+        uint64_t u64;
+        struct cvmx_stxx_int_sync_s {
+                uint64_t reserved_8_63:56;
+                uint64_t frmerr:1;
+                uint64_t unxfrm:1;
+                uint64_t nosync:1;
+                uint64_t diperr:1;
+                uint64_t datovr:1;
+                uint64_t ovrbst:1;
+                uint64_t calpar1:1;
+                uint64_t calpar0:1;
+        } s;
+        struct cvmx_stxx_int_sync_s cn38xx;
+        struct cvmx_stxx_int_sync_s cn38xxp2;
+        struct cvmx_stxx_int_sync_s cn58xx;
+        struct cvmx_stxx_int_sync_s cn58xxp1;
+};
+
+union cvmx_stxx_min_bst {
+        uint64_t u64;
+        struct cvmx_stxx_min_bst_s {
+                uint64_t reserved_9_63:55;
+                uint64_t minb:9;
+        } s;
+        struct cvmx_stxx_min_bst_s cn38xx;
+        struct cvmx_stxx_min_bst_s cn38xxp2;
+        struct cvmx_stxx_min_bst_s cn58xx;
+        struct cvmx_stxx_min_bst_s cn58xxp1;
+};
+
+union cvmx_stxx_spi4_calx {
+        uint64_t u64;
+        struct cvmx_stxx_spi4_calx_s {
+                uint64_t reserved_17_63:47;
+                uint64_t oddpar:1;
+                uint64_t prt3:4;
+                uint64_t prt2:4;
+                uint64_t prt1:4;
+                uint64_t prt0:4;
+        } s;
+        struct cvmx_stxx_spi4_calx_s cn38xx;
+        struct cvmx_stxx_spi4_calx_s cn38xxp2;
+        struct cvmx_stxx_spi4_calx_s cn58xx;
+        struct cvmx_stxx_spi4_calx_s cn58xxp1;
+};
+
+union cvmx_stxx_spi4_dat {
+        uint64_t u64;
+        struct cvmx_stxx_spi4_dat_s {
+                uint64_t reserved_32_63:32;
+                uint64_t alpha:16;
+                uint64_t max_t:16;
+        } s;
+        struct cvmx_stxx_spi4_dat_s cn38xx;
+        struct cvmx_stxx_spi4_dat_s cn38xxp2;
+        struct cvmx_stxx_spi4_dat_s cn58xx;
+        struct cvmx_stxx_spi4_dat_s cn58xxp1;
+};
+
+union cvmx_stxx_spi4_stat {
+        uint64_t u64;
+        struct cvmx_stxx_spi4_stat_s {
+                uint64_t reserved_16_63:48;
+                uint64_t m:8;
+                uint64_t reserved_7_7:1;
+                uint64_t len:7;
+        } s;
+        struct cvmx_stxx_spi4_stat_s cn38xx;
+        struct cvmx_stxx_spi4_stat_s cn38xxp2;
+        struct cvmx_stxx_spi4_stat_s cn58xx;
+        struct cvmx_stxx_spi4_stat_s cn58xxp1;
+};
+
+union cvmx_stxx_stat_bytes_hi {
+        uint64_t u64;
+        struct cvmx_stxx_stat_bytes_hi_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_stxx_stat_bytes_hi_s cn38xx;
+        struct cvmx_stxx_stat_bytes_hi_s cn38xxp2;
+        struct cvmx_stxx_stat_bytes_hi_s cn58xx;
+        struct cvmx_stxx_stat_bytes_hi_s cn58xxp1;
+};
+
+union cvmx_stxx_stat_bytes_lo {
+        uint64_t u64;
+        struct cvmx_stxx_stat_bytes_lo_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_stxx_stat_bytes_lo_s cn38xx;
+        struct cvmx_stxx_stat_bytes_lo_s cn38xxp2;
+        struct cvmx_stxx_stat_bytes_lo_s cn58xx;
+        struct cvmx_stxx_stat_bytes_lo_s cn58xxp1;
+};
+
+union cvmx_stxx_stat_ctl {
+        uint64_t u64;
+        struct cvmx_stxx_stat_ctl_s {
+                uint64_t reserved_5_63:59;
+                uint64_t clr:1;
+                uint64_t bckprs:4;
+        } s;
+        struct cvmx_stxx_stat_ctl_s cn38xx;
+        struct cvmx_stxx_stat_ctl_s cn38xxp2;
+        struct cvmx_stxx_stat_ctl_s cn58xx;
+        struct cvmx_stxx_stat_ctl_s cn58xxp1;
+};
+
+union cvmx_stxx_stat_pkt_xmt {
+        uint64_t u64;
+        struct cvmx_stxx_stat_pkt_xmt_s {
+                uint64_t reserved_32_63:32;
+                uint64_t cnt:32;
+        } s;
+        struct cvmx_stxx_stat_pkt_xmt_s cn38xx;
+        struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2;
+        struct cvmx_stxx_stat_pkt_xmt_s cn58xx;
+        struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1;
+};
+
+#endif
diff --git a/drivers/staging/octeon/cvmx-wqe.h b/drivers/staging/octeon/cvmx-wqe.h
new file mode 100644
index 000000000000..653610953d28
--- /dev/null
+++ b/drivers/staging/octeon/cvmx-wqe.h
@@ -0,0 +1,397 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+/**
+ *
+ * This header file defines the work queue entry (wqe) data structure.
+ * Since this is a commonly used structure that depends on structures
+ * from several hardware blocks, those definitions have been placed
+ * in this file to create a single point of definition of the wqe
+ * format.
+ * Data structures are still named according to the block that they
+ * relate to.
+ *
+ */
+
+#ifndef __CVMX_WQE_H__
+#define __CVMX_WQE_H__
+
+#include "cvmx-packet.h"
+
+
+#define OCT_TAG_TYPE_STRING(x)                                          \
+        (((x) == CVMX_POW_TAG_TYPE_ORDERED) ?  "ORDERED" :              \
+                (((x) == CVMX_POW_TAG_TYPE_ATOMIC) ?  "ATOMIC" :        \
+                        (((x) == CVMX_POW_TAG_TYPE_NULL) ?  "NULL" :    \
+                                "NULL_NULL")))
+
+/**
+ * HW decode / err_code in work queue entry
+ */
+typedef union {
+        uint64_t u64;
+
+        /* Use this struct if the hardware determines that the packet is IP */
+        struct {
+                /* HW sets this to the number of buffers used by this packet */
+                uint64_t bufs:8;
+                /* HW sets to the number of L2 bytes prior to the IP */
+                uint64_t ip_offset:8;
+                /* set to 1 if we found DSA/VLAN in the L2 */
+                uint64_t vlan_valid:1;
+                /* Set to 1 if the DSA/VLAN tag is stacked */
+                uint64_t vlan_stacked:1;
+                uint64_t unassigned:1;
+                /* HW sets to the DSA/VLAN CFI flag (valid when vlan_valid) */
+                uint64_t vlan_cfi:1;
+                /* HW sets to the DSA/VLAN_ID field (valid when vlan_valid) */
+                uint64_t vlan_id:12;
+                /* Ring Identifier (if PCIe). Requires PIP_GBL_CTL[RING_EN]=1 */
+                uint64_t pr:4;
+                uint64_t unassigned2:8;
+                /* the packet needs to be decompressed */
+                uint64_t dec_ipcomp:1;
+                /* the packet is either TCP or UDP */
+                uint64_t tcp_or_udp:1;
+                /* the packet needs to be decrypted (ESP or AH) */
+                uint64_t dec_ipsec:1;
+                /* the packet is IPv6 */
+                uint64_t is_v6:1;
+
+                /*
+                 * (rcv_error, not_IP, IP_exc, is_frag, L4_error,
+                 * software, etc.).
+                 */
+
+                /*
+                 * reserved for software use, hardware will clear on
+                 * packet creation.
+                 */
+                uint64_t software:1;
+                /* exceptional conditions below */
+                /* the receive interface hardware detected an L4 error
+                 * (only applies if !is_frag) (only applies if
+                 * !rcv_error && !not_IP && !IP_exc && !is_frag)
+                 * failure indicated in err_code below, decode:
+                 *
+                 * - 1 = Malformed L4
+                 * - 2 = L4 Checksum Error: the L4 checksum value is
+                 * - 3 = UDP Length Error: The UDP length field would
+                 *       make the UDP data longer than what remains in
+                 *       the IP packet (as defined by the IP header
+                 *       length field).
+                 * - 4 = Bad L4 Port: either the source or destination
+                 *       TCP/UDP port is 0.
+                 * - 8 = TCP FIN Only: the packet is TCP and only the
+                 *       FIN flag set.
+                 * - 9 = TCP No Flags: the packet is TCP and no flags
+                 *       are set.
+                 * - 10 = TCP FIN RST: the packet is TCP and both FIN
+                 *        and RST are set.
+                 * - 11 = TCP SYN URG: the packet is TCP and both SYN
+                 *        and URG are set.
+                 * - 12 = TCP SYN RST: the packet is TCP and both SYN
+                 *        and RST are set.
+                 * - 13 = TCP SYN FIN: the packet is TCP and both SYN
+                 *        and FIN are set.
+                 */
+                uint64_t L4_error:1;
+                /* set if the packet is a fragment */
+                uint64_t is_frag:1;
+                /* the receive interface hardware detected an IP error
+                 * / exception (only applies if !rcv_error && !not_IP)
+                 * failure indicated in err_code below, decode:
+                 *
+                 * - 1 = Not IP: the IP version field is neither 4 nor
+                 *       6.
+                 * - 2 = IPv4 Header Checksum Error: the IPv4 header
+                 *       has a checksum violation.
+                 * - 3 = IP Malformed Header: the packet is not long
+                 *       enough to contain the IP header.
+                 * - 4 = IP Malformed: the packet is not long enough
+                 *       to contain the bytes indicated by the IP
+                 *       header. Pad is allowed.
+                 * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
+                 *       Hop Count field are zero.
+                 * - 6 = IP Options
+                 */
+                uint64_t IP_exc:1;
+                /*
+                 * Set if the hardware determined that the packet is a
+                 * broadcast.
+                 */
+                uint64_t is_bcast:1;
+                /*
+                 * St if the hardware determined that the packet is a
+                 * multi-cast.
+                 */
+                uint64_t is_mcast:1;
+                /*
+                 * Set if the packet may not be IP (must be zero in
+                 * this case).
+                 */
+                uint64_t not_IP:1;
+                /*
+                 * The receive interface hardware detected a receive
+                 * error (must be zero in this case).
+                 */
+                uint64_t rcv_error:1;
+                /* lower err_code = first-level descriptor of the
+                 * work */
+                /* zero for packet submitted by hardware that isn't on
+                 * the slow path */
+                /* type is cvmx_pip_err_t */
+                uint64_t err_code:8;
+        } s;
+
+        /* use this to get at the 16 vlan bits */
+        struct {
+                uint64_t unused1:16;
+                uint64_t vlan:16;
+                uint64_t unused2:32;
+        } svlan;
+
+        /*
+         * use this struct if the hardware could not determine that
+         * the packet is ip.
+         */
+        struct {
+                /*
+                 * HW sets this to the number of buffers used by this
+                 * packet.
+                 */
+                uint64_t bufs:8;
+                uint64_t unused:8;
+                /* set to 1 if we found DSA/VLAN in the L2 */
+                uint64_t vlan_valid:1;
+                /* Set to 1 if the DSA/VLAN tag is stacked */
+                uint64_t vlan_stacked:1;
+                uint64_t unassigned:1;
+                /*
+                 * HW sets to the DSA/VLAN CFI flag (valid when
+                 * vlan_valid)
+                 */
+                uint64_t vlan_cfi:1;
+                /*
+                 * HW sets to the DSA/VLAN_ID field (valid when
+                 * vlan_valid).
+                 */
+                uint64_t vlan_id:12;
+                /*
+                 * Ring Identifier (if PCIe). Requires
+                 * PIP_GBL_CTL[RING_EN]=1
+                 */
+                uint64_t pr:4;
+                uint64_t unassigned2:12;
+                /*
+                 * reserved for software use, hardware will clear on
+                 * packet creation.
+                 */
+                uint64_t software:1;
+                uint64_t unassigned3:1;
+                /*
+                 * set if the hardware determined that the packet is
+                 * rarp.
+                 */
+                uint64_t is_rarp:1;
+                /*
+                 * set if the hardware determined that the packet is
+                 * arp
+                 */
+                uint64_t is_arp:1;
+                /*
+                 * set if the hardware determined that the packet is a
+                 * broadcast.
+                 */
+                uint64_t is_bcast:1;
+                /*
+                 * set if the hardware determined that the packet is a
+                 * multi-cast
+                 */
+                uint64_t is_mcast:1;
+                /*
+                 * set if the packet may not be IP (must be one in
+                 * this case)
+                 */
+                uint64_t not_IP:1;
+                /* The receive interface hardware detected a receive
+                 * error.  Failure indicated in err_code below,
+                 * decode:
+                 *
+                 * - 1 = partial error: a packet was partially
+                 *       received, but internal buffering / bandwidth
+                 *       was not adequate to receive the entire
+                 *       packet.
+                 * - 2 = jabber error: the RGMII packet was too large
+                 *       and is truncated.
+                 * - 3 = overrun error: the RGMII packet is longer
+                 *       than allowed and had an FCS error.
+                 * - 4 = oversize error: the RGMII packet is longer
+                 *       than allowed.
+                 * - 5 = alignment error: the RGMII packet is not an
+                 *       integer number of bytes
+                 *       and had an FCS error (100M and 10M only).
+                 * - 6 = fragment error: the RGMII packet is shorter
+                 *       than allowed and had an FCS error.
+                 * - 7 = GMX FCS error: the RGMII packet had an FCS
+                 *       error.
+                 * - 8 = undersize error: the RGMII packet is shorter
+                 *       than allowed.
+                 * - 9 = extend error: the RGMII packet had an extend
+                 *       error.
+                 * - 10 = length mismatch error: the RGMII packet had
+                 *        a length that did not match the length field
+                 *        in the L2 HDR.
+                 * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
+                 *        packet had one or more data reception errors
+                 *        (RXERR) or the SPI4 packet had one or more
+                 *        DIP4 errors.
+                 * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
+                 *        packet was not large enough to cover the
+                 *        skipped bytes or the SPI4 packet was
+                 *        terminated with an About EOPS.
+                 * - 13 = RGMII nibble error/SPI4 Port NXA Error: the
+                 *        RGMII packet had a studder error (data not
+                 *        repeated - 10/100M only) or the SPI4 packet
+                 *        was sent to an NXA.
+                 * - 16 = FCS error: a SPI4.2 packet had an FCS error.
+                 * - 17 = Skip error: a packet was not large enough to
+                 *        cover the skipped bytes.
+                 * - 18 = L2 header malformed: the packet is not long
+                 *        enough to contain the L2.
+                 */
+
+                uint64_t rcv_error:1;
+                /*
+                 * lower err_code = first-level descriptor of the
+                 * work
+                 */
+                /*
+                 * zero for packet submitted by hardware that isn't on
+                 * the slow path
+                 */
+                /* type is cvmx_pip_err_t (union, so can't use directly */
+                uint64_t err_code:8;
+        } snoip;
+
+} cvmx_pip_wqe_word2;
+
+/**
+ * Work queue entry format
+ *
+ * must be 8-byte aligned
+ */
+typedef struct {
+
+    /*****************************************************************
+     * WORD 0
+     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
+     */
+
+    /**
+     * raw chksum result generated by the HW
+     */
+        uint16_t hw_chksum;
+    /**
+     * Field unused by hardware - available for software
+     */
+        uint8_t unused;
+    /**
+     * Next pointer used by hardware for list maintenance.
+     * May be written/read by HW before the work queue
+     *           entry is scheduled to a PP
+     * (Only 36 bits used in Octeon 1)
+     */
+        uint64_t next_ptr:40;
+
+    /*****************************************************************
+     * WORD 1
+     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
+     */
+
+    /**
+     * HW sets to the total number of bytes in the packet
+     */
+        uint64_t len:16;
+    /**
+     * HW sets this to input physical port
+     */
+        uint64_t ipprt:6;
+
+    /**
+     * HW sets this to what it thought the priority of the input packet was
+     */
+        uint64_t qos:3;
+
+    /**
+     * the group that the work queue entry will be scheduled to
+     */
+        uint64_t grp:4;
+    /**
+     * the type of the tag (ORDERED, ATOMIC, NULL)
+     */
+        uint64_t tag_type:3;
+    /**
+     * the synchronization/ordering tag
+     */
+        uint64_t tag:32;
+
+    /**
+     * WORD 2 HW WRITE: the following 64-bits are filled in by
+     *   hardware when a packet arrives This indicates a variety of
+     *   status and error conditions.
+     */
+        cvmx_pip_wqe_word2 word2;
+
+    /**
+     * Pointer to the first segment of the packet.
+     */
+        union cvmx_buf_ptr packet_ptr;
+
+    /**
+     *   HW WRITE: octeon will fill in a programmable amount from the
+     *             packet, up to (at most, but perhaps less) the amount
+     *             needed to fill the work queue entry to 128 bytes
+     *
+     *   If the packet is recognized to be IP, the hardware starts
+     *   (except that the IPv4 header is padded for appropriate
+     *   alignment) writing here where the IP header starts.  If the
+     *   packet is not recognized to be IP, the hardware starts
+     *   writing the beginning of the packet here.
+     */
+        uint8_t packet_data[96];
+
+    /**
+     * If desired, SW can make the work Q entry any length. For the
+     * purposes of discussion here, Assume 128B always, as this is all that
+     * the hardware deals with.
+     *
+     */
+
+} CVMX_CACHE_LINE_ALIGNED cvmx_wqe_t;
+
+#endif /* __CVMX_WQE_H__ */
diff --git a/drivers/staging/octeon/ethernet-common.c b/drivers/staging/octeon/ethernet-common.c
new file mode 100644
index 000000000000..3e6f5b8cc63d
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-common.c
@@ -0,0 +1,328 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+#include <linux/kernel.h>
+#include <linux/mii.h>
+#include <net/dst.h>
+
+#include <asm/atomic.h>
+#include <asm/octeon/octeon.h>
+
+#include "ethernet-defines.h"
+#include "ethernet-tx.h"
+#include "ethernet-mdio.h"
+#include "ethernet-util.h"
+#include "octeon-ethernet.h"
+#include "ethernet-common.h"
+
+#include "cvmx-pip.h"
+#include "cvmx-pko.h"
+#include "cvmx-fau.h"
+#include "cvmx-helper.h"
+
+#include "cvmx-gmxx-defs.h"
+
+/**
+ * Get the low level ethernet statistics
+ *
+ * @dev:    Device to get the statistics from
+ * Returns Pointer to the statistics
+ */
+static struct net_device_stats *cvm_oct_common_get_stats(struct net_device *dev)
+{
+        cvmx_pip_port_status_t rx_status;
+        cvmx_pko_port_status_t tx_status;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+
+        if (priv->port < CVMX_PIP_NUM_INPUT_PORTS) {
+                if (octeon_is_simulation()) {
+                        /* The simulator doesn't support statistics */
+                        memset(&rx_status, 0, sizeof(rx_status));
+                        memset(&tx_status, 0, sizeof(tx_status));
+                } else {
+                        cvmx_pip_get_port_status(priv->port, 1, &rx_status);
+                        cvmx_pko_get_port_status(priv->port, 1, &tx_status);
+                }
+
+                priv->stats.rx_packets += rx_status.inb_packets;
+                priv->stats.tx_packets += tx_status.packets;
+                priv->stats.rx_bytes += rx_status.inb_octets;
+                priv->stats.tx_bytes += tx_status.octets;
+                priv->stats.multicast += rx_status.multicast_packets;
+                priv->stats.rx_crc_errors += rx_status.inb_errors;
+                priv->stats.rx_frame_errors += rx_status.fcs_align_err_packets;
+
+                /*
+                 * The drop counter must be incremented atomically
+                 * since the RX tasklet also increments it.
+                 */
+#ifdef CONFIG_64BIT
+                atomic64_add(rx_status.dropped_packets,
+                             (atomic64_t *)&priv->stats.rx_dropped);
+#else
+                atomic_add(rx_status.dropped_packets,
+                             (atomic_t *)&priv->stats.rx_dropped);
+#endif
+        }
+
+        return &priv->stats;
+}
+
+/**
+ * Set the multicast list. Currently unimplemented.
+ *
+ * @dev:    Device to work on
+ */
+static void cvm_oct_common_set_multicast_list(struct net_device *dev)
+{
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int interface = INTERFACE(priv->port);
+        int index = INDEX(priv->port);
+
+        if ((interface < 2)
+            && (cvmx_helper_interface_get_mode(interface) !=
+                CVMX_HELPER_INTERFACE_MODE_SPI)) {
+                union cvmx_gmxx_rxx_adr_ctl control;
+                control.u64 = 0;
+                control.s.bcst = 1;     /* Allow broadcast MAC addresses */
+
+                if (dev->mc_list || (dev->flags & IFF_ALLMULTI) ||
+                    (dev->flags & IFF_PROMISC))
+                        /* Force accept multicast packets */
+                        control.s.mcst = 2;
+                else
+                        /* Force reject multicat packets */
+                        control.s.mcst = 1;
+
+                if (dev->flags & IFF_PROMISC)
+                        /*
+                         * Reject matches if promisc. Since CAM is
+                         * shut off, should accept everything.
+                         */
+                        control.s.cam_mode = 0;
+                else
+                        /* Filter packets based on the CAM */
+                        control.s.cam_mode = 1;
+
+                gmx_cfg.u64 =
+                    cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+                cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
+                               gmx_cfg.u64 & ~1ull);
+
+                cvmx_write_csr(CVMX_GMXX_RXX_ADR_CTL(index, interface),
+                               control.u64);
+                if (dev->flags & IFF_PROMISC)
+                        cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN
+                                       (index, interface), 0);
+                else
+                        cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN
+                                       (index, interface), 1);
+
+                cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
+                               gmx_cfg.u64);
+        }
+}
+
+/**
+ * Set the hardware MAC address for a device
+ *
+ * @dev:    Device to change the MAC address for
+ * @addr:   Address structure to change it too. MAC address is addr + 2.
+ * Returns Zero on success
+ */
+static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        int interface = INTERFACE(priv->port);
+        int index = INDEX(priv->port);
+
+        memcpy(dev->dev_addr, addr + 2, 6);
+
+        if ((interface < 2)
+            && (cvmx_helper_interface_get_mode(interface) !=
+                CVMX_HELPER_INTERFACE_MODE_SPI)) {
+                int i;
+                uint8_t *ptr = addr;
+                uint64_t mac = 0;
+                for (i = 0; i < 6; i++)
+                        mac = (mac << 8) | (uint64_t) (ptr[i + 2]);
+
+                gmx_cfg.u64 =
+                    cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+                cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
+                               gmx_cfg.u64 & ~1ull);
+
+                cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac);
+                cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface),
+                               ptr[2]);
+                cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface),
+                               ptr[3]);
+                cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface),
+                               ptr[4]);
+                cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface),
+                               ptr[5]);
+                cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface),
+                               ptr[6]);
+                cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface),
+                               ptr[7]);
+                cvm_oct_common_set_multicast_list(dev);
+                cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
+                               gmx_cfg.u64);
+        }
+        return 0;
+}
+
+/**
+ * Change the link MTU. Unimplemented
+ *
+ * @dev:     Device to change
+ * @new_mtu: The new MTU
+ *
+ * Returns Zero on success
+ */
+static int cvm_oct_common_change_mtu(struct net_device *dev, int new_mtu)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int interface = INTERFACE(priv->port);
+        int index = INDEX(priv->port);
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+        int vlan_bytes = 4;
+#else
+        int vlan_bytes = 0;
+#endif
+
+        /*
+         * Limit the MTU to make sure the ethernet packets are between
+         * 64 bytes and 65535 bytes.
+         */
+        if ((new_mtu + 14 + 4 + vlan_bytes < 64)
+            || (new_mtu + 14 + 4 + vlan_bytes > 65392)) {
+                pr_err("MTU must be between %d and %d.\n",
+                       64 - 14 - 4 - vlan_bytes, 65392 - 14 - 4 - vlan_bytes);
+                return -EINVAL;
+        }
+        dev->mtu = new_mtu;
+
+        if ((interface < 2)
+            && (cvmx_helper_interface_get_mode(interface) !=
+                CVMX_HELPER_INTERFACE_MODE_SPI)) {
+                /* Add ethernet header and FCS, and VLAN if configured. */
+                int max_packet = new_mtu + 14 + 4 + vlan_bytes;
+
+                if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
+                    || OCTEON_IS_MODEL(OCTEON_CN58XX)) {
+                        /* Signal errors on packets larger than the MTU */
+                        cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(index, interface),
+                                       max_packet);
+                } else {
+                        /*
+                         * Set the hardware to truncate packets larger
+                         * than the MTU and smaller the 64 bytes.
+                         */
+                        union cvmx_pip_frm_len_chkx frm_len_chk;
+                        frm_len_chk.u64 = 0;
+                        frm_len_chk.s.minlen = 64;
+                        frm_len_chk.s.maxlen = max_packet;
+                        cvmx_write_csr(CVMX_PIP_FRM_LEN_CHKX(interface),
+                                       frm_len_chk.u64);
+                }
+                /*
+                 * Set the hardware to truncate packets larger than
+                 * the MTU. The jabber register must be set to a
+                 * multiple of 8 bytes, so round up.
+                 */
+                cvmx_write_csr(CVMX_GMXX_RXX_JABBER(index, interface),
+                               (max_packet + 7) & ~7u);
+        }
+        return 0;
+}
+
+/**
+ * Per network device initialization
+ *
+ * @dev:    Device to initialize
+ * Returns Zero on success
+ */
+int cvm_oct_common_init(struct net_device *dev)
+{
+        static int count;
+        char mac[8] = { 0x00, 0x00,
+                octeon_bootinfo->mac_addr_base[0],
+                octeon_bootinfo->mac_addr_base[1],
+                octeon_bootinfo->mac_addr_base[2],
+                octeon_bootinfo->mac_addr_base[3],
+                octeon_bootinfo->mac_addr_base[4],
+                octeon_bootinfo->mac_addr_base[5] + count
+        };
+        struct octeon_ethernet *priv = netdev_priv(dev);
+
+        /*
+         * Force the interface to use the POW send if always_use_pow
+         * was specified or it is in the pow send list.
+         */
+        if ((pow_send_group != -1)
+            && (always_use_pow || strstr(pow_send_list, dev->name)))
+                priv->queue = -1;
+
+        if (priv->queue != -1) {
+                dev->hard_start_xmit = cvm_oct_xmit;
+                if (USE_HW_TCPUDP_CHECKSUM)
+                        dev->features |= NETIF_F_IP_CSUM;
+        } else
+                dev->hard_start_xmit = cvm_oct_xmit_pow;
+        count++;
+
+        dev->get_stats = cvm_oct_common_get_stats;
+        dev->set_mac_address = cvm_oct_common_set_mac_address;
+        dev->set_multicast_list = cvm_oct_common_set_multicast_list;
+        dev->change_mtu = cvm_oct_common_change_mtu;
+        dev->do_ioctl = cvm_oct_ioctl;
+        /* We do our own locking, Linux doesn't need to */
+        dev->features |= NETIF_F_LLTX;
+        SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops);
+#ifdef CONFIG_NET_POLL_CONTROLLER
+        dev->poll_controller = cvm_oct_poll_controller;
+#endif
+
+        cvm_oct_mdio_setup_device(dev);
+        dev->set_mac_address(dev, mac);
+        dev->change_mtu(dev, dev->mtu);
+
+        /*
+         * Zero out stats for port so we won't mistakenly show
+         * counters from the bootloader.
+         */
+        memset(dev->get_stats(dev), 0, sizeof(struct net_device_stats));
+
+        return 0;
+}
+
+void cvm_oct_common_uninit(struct net_device *dev)
+{
+        /* Currently nothing to do */
+}
diff --git a/drivers/staging/octeon/ethernet-common.h b/drivers/staging/octeon/ethernet-common.h
new file mode 100644
index 000000000000..2bd9cd76a398
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-common.h
@@ -0,0 +1,29 @@
+/*********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+*********************************************************************/
+
+int cvm_oct_common_init(struct net_device *dev);
+void cvm_oct_common_uninit(struct net_device *dev);
diff --git a/drivers/staging/octeon/ethernet-defines.h b/drivers/staging/octeon/ethernet-defines.h
new file mode 100644
index 000000000000..8f7374e7664c
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-defines.h
@@ -0,0 +1,134 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+
+/*
+ * A few defines are used to control the operation of this driver:
+ *  CONFIG_CAVIUM_RESERVE32
+ *      This kernel config options controls the amount of memory configured
+ *      in a wired TLB entry for all processes to share. If this is set, the
+ *      driver will use this memory instead of kernel memory for pools. This
+ *      allows 32bit userspace application to access the buffers, but also
+ *      requires all received packets to be copied.
+ *  CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS
+ *      This kernel config option allows the user to control the number of
+ *      packet and work queue buffers allocated by the driver. If this is zero,
+ *      the driver uses the default from below.
+ *  USE_SKBUFFS_IN_HW
+ *      Tells the driver to populate the packet buffers with kernel skbuffs.
+ *      This allows the driver to receive packets without copying them. It also
+ *      means that 32bit userspace can't access the packet buffers.
+ *  USE_32BIT_SHARED
+ *      This define tells the driver to allocate memory for buffers from the
+ *      32bit sahred region instead of the kernel memory space.
+ *  USE_HW_TCPUDP_CHECKSUM
+ *      Controls if the Octeon TCP/UDP checksum engine is used for packet
+ *      output. If this is zero, the kernel will perform the checksum in
+ *      software.
+ *  USE_MULTICORE_RECEIVE
+ *      Process receive interrupts on multiple cores. This spreads the network
+ *      load across the first 8 processors. If ths is zero, only one core
+ *      processes incomming packets.
+ *  USE_ASYNC_IOBDMA
+ *      Use asynchronous IO access to hardware. This uses Octeon's asynchronous
+ *      IOBDMAs to issue IO accesses without stalling. Set this to zero
+ *      to disable this. Note that IOBDMAs require CVMSEG.
+ *  REUSE_SKBUFFS_WITHOUT_FREE
+ *      Allows the TX path to free an skbuff into the FPA hardware pool. This
+ *      can significantly improve performance for forwarding and bridging, but
+ *      may be somewhat dangerous. Checks are made, but if any buffer is reused
+ *      without the proper Linux cleanup, the networking stack may have very
+ *      bizarre bugs.
+ */
+#ifndef __ETHERNET_DEFINES_H__
+#define __ETHERNET_DEFINES_H__
+
+#include "cvmx-config.h"
+
+
+#define OCTEON_ETHERNET_VERSION "1.9"
+
+#ifndef CONFIG_CAVIUM_RESERVE32
+#define CONFIG_CAVIUM_RESERVE32 0
+#endif
+
+#if CONFIG_CAVIUM_RESERVE32
+#define USE_32BIT_SHARED            1
+#define USE_SKBUFFS_IN_HW           0
+#define REUSE_SKBUFFS_WITHOUT_FREE  0
+#else
+#define USE_32BIT_SHARED            0
+#define USE_SKBUFFS_IN_HW           1
+#ifdef CONFIG_NETFILTER
+#define REUSE_SKBUFFS_WITHOUT_FREE  0
+#else
+#define REUSE_SKBUFFS_WITHOUT_FREE  1
+#endif
+#endif
+
+/* Max interrupts per second per core */
+#define INTERRUPT_LIMIT             10000
+
+/* Don't limit the number of interrupts */
+/*#define INTERRUPT_LIMIT             0     */
+#define USE_HW_TCPUDP_CHECKSUM      1
+
+#define USE_MULTICORE_RECEIVE       1
+
+/* Enable Random Early Dropping under load */
+#define USE_RED                     1
+#define USE_ASYNC_IOBDMA            (CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0)
+
+/*
+ * Allow SW based preamble removal at 10Mbps to workaround PHYs giving
+ * us bad preambles.
+ */
+#define USE_10MBPS_PREAMBLE_WORKAROUND 1
+/*
+ * Use this to have all FPA frees also tell the L2 not to write data
+ * to memory.
+ */
+#define DONT_WRITEBACK(x)           (x)
+/* Use this to not have FPA frees control L2 */
+/*#define DONT_WRITEBACK(x)         0   */
+
+/* Maximum number of packets to process per interrupt. */
+#define MAX_RX_PACKETS 120
+#define MAX_OUT_QUEUE_DEPTH 1000
+
+#ifndef CONFIG_SMP
+#undef USE_MULTICORE_RECEIVE
+#define USE_MULTICORE_RECEIVE 0
+#endif
+
+#define IP_PROTOCOL_TCP             6
+#define IP_PROTOCOL_UDP             0x11
+
+#define FAU_NUM_PACKET_BUFFERS_TO_FREE (CVMX_FAU_REG_END - sizeof(uint32_t))
+#define TOTAL_NUMBER_OF_PORTS       (CVMX_PIP_NUM_INPUT_PORTS+1)
+
+
+#endif /* __ETHERNET_DEFINES_H__ */
diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c
new file mode 100644
index 000000000000..93cab0a48925
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-mdio.c
@@ -0,0 +1,231 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+#include <linux/kernel.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <net/dst.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "ethernet-defines.h"
+#include "octeon-ethernet.h"
+#include "ethernet-mdio.h"
+
+#include "cvmx-helper-board.h"
+
+#include "cvmx-smix-defs.h"
+
+DECLARE_MUTEX(mdio_sem);
+
+/**
+ * Perform an MII read. Called by the generic MII routines
+ *
+ * @dev:      Device to perform read for
+ * @phy_id:   The MII phy id
+ * @location: Register location to read
+ * Returns Result from the read or zero on failure
+ */
+static int cvm_oct_mdio_read(struct net_device *dev, int phy_id, int location)
+{
+        union cvmx_smix_cmd smi_cmd;
+        union cvmx_smix_rd_dat smi_rd;
+
+        smi_cmd.u64 = 0;
+        smi_cmd.s.phy_op = 1;
+        smi_cmd.s.phy_adr = phy_id;
+        smi_cmd.s.reg_adr = location;
+        cvmx_write_csr(CVMX_SMIX_CMD(0), smi_cmd.u64);
+
+        do {
+                if (!in_interrupt())
+                        yield();
+                smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(0));
+        } while (smi_rd.s.pending);
+
+        if (smi_rd.s.val)
+                return smi_rd.s.dat;
+        else
+                return 0;
+}
+
+static int cvm_oct_mdio_dummy_read(struct net_device *dev, int phy_id,
+                                   int location)
+{
+        return 0xffff;
+}
+
+/**
+ * Perform an MII write. Called by the generic MII routines
+ *
+ * @dev:      Device to perform write for
+ * @phy_id:   The MII phy id
+ * @location: Register location to write
+ * @val:      Value to write
+ */
+static void cvm_oct_mdio_write(struct net_device *dev, int phy_id, int location,
+                               int val)
+{
+        union cvmx_smix_cmd smi_cmd;
+        union cvmx_smix_wr_dat smi_wr;
+
+        smi_wr.u64 = 0;
+        smi_wr.s.dat = val;
+        cvmx_write_csr(CVMX_SMIX_WR_DAT(0), smi_wr.u64);
+
+        smi_cmd.u64 = 0;
+        smi_cmd.s.phy_op = 0;
+        smi_cmd.s.phy_adr = phy_id;
+        smi_cmd.s.reg_adr = location;
+        cvmx_write_csr(CVMX_SMIX_CMD(0), smi_cmd.u64);
+
+        do {
+                if (!in_interrupt())
+                        yield();
+                smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(0));
+        } while (smi_wr.s.pending);
+}
+
+static void cvm_oct_mdio_dummy_write(struct net_device *dev, int phy_id,
+                                     int location, int val)
+{
+}
+
+static void cvm_oct_get_drvinfo(struct net_device *dev,
+                                struct ethtool_drvinfo *info)
+{
+        strcpy(info->driver, "cavium-ethernet");
+        strcpy(info->version, OCTEON_ETHERNET_VERSION);
+        strcpy(info->bus_info, "Builtin");
+}
+
+static int cvm_oct_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int ret;
+
+        down(&mdio_sem);
+        ret = mii_ethtool_gset(&priv->mii_info, cmd);
+        up(&mdio_sem);
+
+        return ret;
+}
+
+static int cvm_oct_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int ret;
+
+        down(&mdio_sem);
+        ret = mii_ethtool_sset(&priv->mii_info, cmd);
+        up(&mdio_sem);
+
+        return ret;
+}
+
+static int cvm_oct_nway_reset(struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int ret;
+
+        down(&mdio_sem);
+        ret = mii_nway_restart(&priv->mii_info);
+        up(&mdio_sem);
+
+        return ret;
+}
+
+static u32 cvm_oct_get_link(struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        u32 ret;
+
+        down(&mdio_sem);
+        ret = mii_link_ok(&priv->mii_info);
+        up(&mdio_sem);
+
+        return ret;
+}
+
+struct ethtool_ops cvm_oct_ethtool_ops = {
+        .get_drvinfo = cvm_oct_get_drvinfo,
+        .get_settings = cvm_oct_get_settings,
+        .set_settings = cvm_oct_set_settings,
+        .nway_reset = cvm_oct_nway_reset,
+        .get_link = cvm_oct_get_link,
+        .get_sg = ethtool_op_get_sg,
+        .get_tx_csum = ethtool_op_get_tx_csum,
+};
+
+/**
+ * IOCTL support for PHY control
+ *
+ * @dev:    Device to change
+ * @rq:     the request
+ * @cmd:    the command
+ * Returns Zero on success
+ */
+int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        struct mii_ioctl_data *data = if_mii(rq);
+        unsigned int duplex_chg;
+        int ret;
+
+        down(&mdio_sem);
+        ret = generic_mii_ioctl(&priv->mii_info, data, cmd, &duplex_chg);
+        up(&mdio_sem);
+
+        return ret;
+}
+
+/**
+ * Setup the MDIO device structures
+ *
+ * @dev:    Device to setup
+ *
+ * Returns Zero on success, negative on failure
+ */
+int cvm_oct_mdio_setup_device(struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int phy_id = cvmx_helper_board_get_mii_address(priv->port);
+        if (phy_id != -1) {
+                priv->mii_info.dev = dev;
+                priv->mii_info.phy_id = phy_id;
+                priv->mii_info.phy_id_mask = 0xff;
+                priv->mii_info.supports_gmii = 1;
+                priv->mii_info.reg_num_mask = 0x1f;
+                priv->mii_info.mdio_read = cvm_oct_mdio_read;
+                priv->mii_info.mdio_write = cvm_oct_mdio_write;
+        } else {
+                /* Supply dummy MDIO routines so the kernel won't crash
+                   if the user tries to read them */
+                priv->mii_info.mdio_read = cvm_oct_mdio_dummy_read;
+                priv->mii_info.mdio_write = cvm_oct_mdio_dummy_write;
+        }
+        return 0;
+}
diff --git a/drivers/staging/octeon/ethernet-mdio.h b/drivers/staging/octeon/ethernet-mdio.h
new file mode 100644
index 000000000000..6314141e5ef2
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-mdio.h
@@ -0,0 +1,46 @@
+/*********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+*********************************************************************/
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/init.h>
+#include <linux/etherdevice.h>
+#include <linux/ip.h>
+#include <linux/string.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/seq_file.h>
+#include <linux/proc_fs.h>
+#include <net/dst.h>
+#ifdef CONFIG_XFRM
+#include <linux/xfrm.h>
+#include <net/xfrm.h>
+#endif /* CONFIG_XFRM */
+
+extern struct ethtool_ops cvm_oct_ethtool_ops;
+int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
+int cvm_oct_mdio_setup_device(struct net_device *dev);
diff --git a/drivers/staging/octeon/ethernet-mem.c b/drivers/staging/octeon/ethernet-mem.c
new file mode 100644
index 000000000000..b595903e2af1
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-mem.c
@@ -0,0 +1,198 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/mii.h>
+#include <net/dst.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "ethernet-defines.h"
+
+#include "cvmx-fpa.h"
+
+/**
+ * Fill the supplied hardware pool with skbuffs
+ *
+ * @pool:     Pool to allocate an skbuff for
+ * @size:     Size of the buffer needed for the pool
+ * @elements: Number of buffers to allocate
+ */
+static int cvm_oct_fill_hw_skbuff(int pool, int size, int elements)
+{
+        int freed = elements;
+        while (freed) {
+
+                struct sk_buff *skb = dev_alloc_skb(size + 128);
+                if (unlikely(skb == NULL)) {
+                        pr_warning
+                            ("Failed to allocate skb for hardware pool %d\n",
+                             pool);
+                        break;
+                }
+
+                skb_reserve(skb, 128 - (((unsigned long)skb->data) & 0x7f));
+                *(struct sk_buff **)(skb->data - sizeof(void *)) = skb;
+                cvmx_fpa_free(skb->data, pool, DONT_WRITEBACK(size / 128));
+                freed--;
+        }
+        return elements - freed;
+}
+
+/**
+ * Free the supplied hardware pool of skbuffs
+ *
+ * @pool:     Pool to allocate an skbuff for
+ * @size:     Size of the buffer needed for the pool
+ * @elements: Number of buffers to allocate
+ */
+static void cvm_oct_free_hw_skbuff(int pool, int size, int elements)
+{
+        char *memory;
+
+        do {
+                memory = cvmx_fpa_alloc(pool);
+                if (memory) {
+                        struct sk_buff *skb =
+                            *(struct sk_buff **)(memory - sizeof(void *));
+                        elements--;
+                        dev_kfree_skb(skb);
+                }
+        } while (memory);
+
+        if (elements < 0)
+                pr_warning("Freeing of pool %u had too many skbuffs (%d)\n",
+                     pool, elements);
+        else if (elements > 0)
+                pr_warning("Freeing of pool %u is missing %d skbuffs\n",
+                       pool, elements);
+}
+
+/**
+ * This function fills a hardware pool with memory. Depending
+ * on the config defines, this memory might come from the
+ * kernel or global 32bit memory allocated with
+ * cvmx_bootmem_alloc.
+ *
+ * @pool:     Pool to populate
+ * @size:     Size of each buffer in the pool
+ * @elements: Number of buffers to allocate
+ */
+static int cvm_oct_fill_hw_memory(int pool, int size, int elements)
+{
+        char *memory;
+        int freed = elements;
+
+        if (USE_32BIT_SHARED) {
+                extern uint64_t octeon_reserve32_memory;
+
+                memory =
+                    cvmx_bootmem_alloc_range(elements * size, 128,
+                                             octeon_reserve32_memory,
+                                             octeon_reserve32_memory +
+                                             (CONFIG_CAVIUM_RESERVE32 << 20) -
+                                             1);
+                if (memory == NULL)
+                        panic("Unable to allocate %u bytes for FPA pool %d\n",
+                              elements * size, pool);
+
+                pr_notice("Memory range %p - %p reserved for "
+                          "hardware\n", memory,
+                          memory + elements * size - 1);
+
+                while (freed) {
+                        cvmx_fpa_free(memory, pool, 0);
+                        memory += size;
+                        freed--;
+                }
+        } else {
+                while (freed) {
+                        /* We need to force alignment to 128 bytes here */
+                        memory = kmalloc(size + 127, GFP_ATOMIC);
+                        if (unlikely(memory == NULL)) {
+                                pr_warning("Unable to allocate %u bytes for "
+                                           "FPA pool %d\n",
+                                     elements * size, pool);
+                                break;
+                        }
+                        memory = (char *)(((unsigned long)memory + 127) & -128);
+                        cvmx_fpa_free(memory, pool, 0);
+                        freed--;
+                }
+        }
+        return elements - freed;
+}
+
+/**
+ * Free memory previously allocated with cvm_oct_fill_hw_memory
+ *
+ * @pool:     FPA pool to free
+ * @size:     Size of each buffer in the pool
+ * @elements: Number of buffers that should be in the pool
+ */
+static void cvm_oct_free_hw_memory(int pool, int size, int elements)
+{
+        if (USE_32BIT_SHARED) {
+                pr_warning("Warning: 32 shared memory is not freeable\n");
+        } else {
+                char *memory;
+                do {
+                        memory = cvmx_fpa_alloc(pool);
+                        if (memory) {
+                                elements--;
+                                kfree(phys_to_virt(cvmx_ptr_to_phys(memory)));
+                        }
+                } while (memory);
+
+                if (elements < 0)
+                        pr_warning("Freeing of pool %u had too many "
+                                   "buffers (%d)\n",
+                               pool, elements);
+                else if (elements > 0)
+                        pr_warning("Warning: Freeing of pool %u is "
+                                "missing %d buffers\n",
+                             pool, elements);
+        }
+}
+
+int cvm_oct_mem_fill_fpa(int pool, int size, int elements)
+{
+        int freed;
+        if (USE_SKBUFFS_IN_HW)
+                freed = cvm_oct_fill_hw_skbuff(pool, size, elements);
+        else
+                freed = cvm_oct_fill_hw_memory(pool, size, elements);
+        return freed;
+}
+
+void cvm_oct_mem_empty_fpa(int pool, int size, int elements)
+{
+        if (USE_SKBUFFS_IN_HW)
+                cvm_oct_free_hw_skbuff(pool, size, elements);
+        else
+                cvm_oct_free_hw_memory(pool, size, elements);
+}
diff --git a/drivers/staging/octeon/ethernet-mem.h b/drivers/staging/octeon/ethernet-mem.h
new file mode 100644
index 000000000000..713f2edc8b4f
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-mem.h
@@ -0,0 +1,29 @@
+/*********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+********************************************************************/
+
+int cvm_oct_mem_fill_fpa(int pool, int size, int elements);
+void cvm_oct_mem_empty_fpa(int pool, int size, int elements);
diff --git a/drivers/staging/octeon/ethernet-proc.c b/drivers/staging/octeon/ethernet-proc.c
new file mode 100644
index 000000000000..8fa88fc419b7
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-proc.c
@@ -0,0 +1,256 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+#include <linux/kernel.h>
+#include <linux/mii.h>
+#include <linux/seq_file.h>
+#include <linux/proc_fs.h>
+#include <net/dst.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "octeon-ethernet.h"
+#include "ethernet-defines.h"
+
+#include "cvmx-helper.h"
+#include "cvmx-pip.h"
+
+static unsigned long long cvm_oct_stats_read_switch(struct net_device *dev,
+                                                    int phy_id, int offset)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+
+        priv->mii_info.mdio_write(dev, phy_id, 0x1d, 0xcc00 | offset);
+        return ((uint64_t) priv->mii_info.
+                mdio_read(dev, phy_id,
+                          0x1e) << 16) | (uint64_t) priv->mii_info.
+            mdio_read(dev, phy_id, 0x1f);
+}
+
+static int cvm_oct_stats_switch_show(struct seq_file *m, void *v)
+{
+        static const int ports[] = { 0, 1, 2, 3, 9, -1 };
+        struct net_device *dev = cvm_oct_device[0];
+        int index = 0;
+
+        while (ports[index] != -1) {
+
+                /* Latch port */
+                struct octeon_ethernet *priv = netdev_priv(dev);
+
+                priv->mii_info.mdio_write(dev, 0x1b, 0x1d,
+                                          0xdc00 | ports[index]);
+                seq_printf(m, "\nSwitch Port %d\n", ports[index]);
+                seq_printf(m, "InGoodOctets:   %12llu\t"
+                           "OutOctets:      %12llu\t"
+                           "64 Octets:      %12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b,
+                                                     0x00) |
+                           (cvm_oct_stats_read_switch(dev, 0x1b, 0x01) << 32),
+                           cvm_oct_stats_read_switch(dev, 0x1b,
+                                                     0x0E) |
+                           (cvm_oct_stats_read_switch(dev, 0x1b, 0x0F) << 32),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x08));
+
+                seq_printf(m, "InBadOctets:    %12llu\t"
+                           "OutUnicast:     %12llu\t"
+                           "65-127 Octets:  %12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x02),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x10),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x09));
+
+                seq_printf(m, "InUnicast:      %12llu\t"
+                           "OutBroadcasts:  %12llu\t"
+                           "128-255 Octets: %12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x04),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x13),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x0A));
+
+                seq_printf(m, "InBroadcasts:   %12llu\t"
+                           "OutMulticasts:  %12llu\t"
+                           "256-511 Octets: %12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x06),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x12),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x0B));
+
+                seq_printf(m, "InMulticasts:   %12llu\t"
+                           "OutPause:       %12llu\t"
+                           "512-1023 Octets:%12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x07),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x15),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x0C));
+
+                seq_printf(m, "InPause:        %12llu\t"
+                           "Excessive:      %12llu\t"
+                           "1024-Max Octets:%12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x16),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x11),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x0D));
+
+                seq_printf(m, "InUndersize:    %12llu\t"
+                           "Collisions:     %12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x18),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x1E));
+
+                seq_printf(m, "InFragments:    %12llu\t"
+                           "Deferred:       %12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x19),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x05));
+
+                seq_printf(m, "InOversize:     %12llu\t"
+                           "Single:         %12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x1A),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x14));
+
+                seq_printf(m, "InJabber:       %12llu\t"
+                           "Multiple:       %12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x1B),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x17));
+
+                seq_printf(m, "In RxErr:       %12llu\t"
+                           "OutFCSErr:      %12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x1C),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x03));
+
+                seq_printf(m, "InFCSErr:       %12llu\t"
+                           "Late:           %12llu\n",
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x1D),
+                           cvm_oct_stats_read_switch(dev, 0x1b, 0x1F));
+                index++;
+        }
+        return 0;
+}
+
+/**
+ * User is reading /proc/octeon_ethernet_stats
+ *
+ * @m:
+ * @v:
+ * Returns
+ */
+static int cvm_oct_stats_show(struct seq_file *m, void *v)
+{
+        struct octeon_ethernet *priv;
+        int port;
+
+        for (port = 0; port < TOTAL_NUMBER_OF_PORTS; port++) {
+
+                if (cvm_oct_device[port]) {
+                        priv = netdev_priv(cvm_oct_device[port]);
+
+                        seq_printf(m, "\nOcteon Port %d (%s)\n", port,
+                                   cvm_oct_device[port]->name);
+                        seq_printf(m,
+                                   "rx_packets:             %12lu\t"
+                                   "tx_packets:             %12lu\n",
+                                   priv->stats.rx_packets,
+                                   priv->stats.tx_packets);
+                        seq_printf(m,
+                                   "rx_bytes:               %12lu\t"
+                                   "tx_bytes:               %12lu\n",
+                                   priv->stats.rx_bytes, priv->stats.tx_bytes);
+                        seq_printf(m,
+                                   "rx_errors:              %12lu\t"
+                                   "tx_errors:              %12lu\n",
+                                   priv->stats.rx_errors,
+                                   priv->stats.tx_errors);
+                        seq_printf(m,
+                                   "rx_dropped:             %12lu\t"
+                                   "tx_dropped:             %12lu\n",
+                                   priv->stats.rx_dropped,
+                                   priv->stats.tx_dropped);
+                        seq_printf(m,
+                                   "rx_length_errors:       %12lu\t"
+                                   "tx_aborted_errors:      %12lu\n",
+                                   priv->stats.rx_length_errors,
+                                   priv->stats.tx_aborted_errors);
+                        seq_printf(m,
+                                   "rx_over_errors:         %12lu\t"
+                                   "tx_carrier_errors:      %12lu\n",
+                                   priv->stats.rx_over_errors,
+                                   priv->stats.tx_carrier_errors);
+                        seq_printf(m,
+                                   "rx_crc_errors:          %12lu\t"
+                                   "tx_fifo_errors:         %12lu\n",
+                                   priv->stats.rx_crc_errors,
+                                   priv->stats.tx_fifo_errors);
+                        seq_printf(m,
+                                   "rx_frame_errors:        %12lu\t"
+                                   "tx_heartbeat_errors:    %12lu\n",
+                                   priv->stats.rx_frame_errors,
+                                   priv->stats.tx_heartbeat_errors);
+                        seq_printf(m,
+                                   "rx_fifo_errors:         %12lu\t"
+                                   "tx_window_errors:       %12lu\n",
+                                   priv->stats.rx_fifo_errors,
+                                   priv->stats.tx_window_errors);
+                        seq_printf(m,
+                                   "rx_missed_errors:       %12lu\t"
+                                   "multicast:              %12lu\n",
+                                   priv->stats.rx_missed_errors,
+                                   priv->stats.multicast);
+                }
+        }
+
+        if (cvm_oct_device[0]) {
+                priv = netdev_priv(cvm_oct_device[0]);
+                if (priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII)
+                        cvm_oct_stats_switch_show(m, v);
+        }
+        return 0;
+}
+
+/**
+ * /proc/octeon_ethernet_stats was openned. Use the single_open iterator
+ *
+ * @inode:
+ * @file:
+ * Returns
+ */
+static int cvm_oct_stats_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, cvm_oct_stats_show, NULL);
+}
+
+static const struct file_operations cvm_oct_stats_operations = {
+        .open = cvm_oct_stats_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+};
+
+void cvm_oct_proc_initialize(void)
+{
+        struct proc_dir_entry *entry =
+            create_proc_entry("octeon_ethernet_stats", 0, NULL);
+        if (entry)
+                entry->proc_fops = &cvm_oct_stats_operations;
+}
+
+void cvm_oct_proc_shutdown(void)
+{
+        remove_proc_entry("octeon_ethernet_stats", NULL);
+}
diff --git a/drivers/staging/octeon/ethernet-proc.h b/drivers/staging/octeon/ethernet-proc.h
new file mode 100644
index 000000000000..82c7d9f78bc4
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-proc.h
@@ -0,0 +1,29 @@
+/*********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+*********************************************************************/
+
+void cvm_oct_proc_initialize(void);
+void cvm_oct_proc_shutdown(void);
diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c
new file mode 100644
index 000000000000..8579f1670d1e
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-rgmii.c
@@ -0,0 +1,397 @@
+/*********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/mii.h>
+#include <net/dst.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "ethernet-defines.h"
+#include "octeon-ethernet.h"
+#include "ethernet-common.h"
+#include "ethernet-util.h"
+
+#include "cvmx-helper.h"
+
+#include <asm/octeon/cvmx-ipd-defs.h>
+#include <asm/octeon/cvmx-npi-defs.h>
+#include "cvmx-gmxx-defs.h"
+
+DEFINE_SPINLOCK(global_register_lock);
+
+static int number_rgmii_ports;
+
+static void cvm_oct_rgmii_poll(struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        unsigned long flags;
+        cvmx_helper_link_info_t link_info;
+
+        /*
+         * Take the global register lock since we are going to touch
+         * registers that affect more than one port.
+         */
+        spin_lock_irqsave(&global_register_lock, flags);
+
+        link_info = cvmx_helper_link_get(priv->port);
+        if (link_info.u64 == priv->link_info) {
+
+                /*
+                 * If the 10Mbps preamble workaround is supported and we're
+                 * at 10Mbps we may need to do some special checking.
+                 */
+                if (USE_10MBPS_PREAMBLE_WORKAROUND && (link_info.s.speed == 10)) {
+
+                        /*
+                         * Read the GMXX_RXX_INT_REG[PCTERR] bit and
+                         * see if we are getting preamble errors.
+                         */
+                        int interface = INTERFACE(priv->port);
+                        int index = INDEX(priv->port);
+                        union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
+                        gmxx_rxx_int_reg.u64 =
+                            cvmx_read_csr(CVMX_GMXX_RXX_INT_REG
+                                          (index, interface));
+                        if (gmxx_rxx_int_reg.s.pcterr) {
+
+                                /*
+                                 * We are getting preamble errors at
+                                 * 10Mbps.  Most likely the PHY is
+                                 * giving us packets with mis aligned
+                                 * preambles. In order to get these
+                                 * packets we need to disable preamble
+                                 * checking and do it in software.
+                                 */
+                                union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
+                                union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
+
+                                /* Disable preamble checking */
+                                gmxx_rxx_frm_ctl.u64 =
+                                    cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL
+                                                  (index, interface));
+                                gmxx_rxx_frm_ctl.s.pre_chk = 0;
+                                cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL
+                                               (index, interface),
+                                               gmxx_rxx_frm_ctl.u64);
+
+                                /* Disable FCS stripping */
+                                ipd_sub_port_fcs.u64 =
+                                    cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
+                                ipd_sub_port_fcs.s.port_bit &=
+                                    0xffffffffull ^ (1ull << priv->port);
+                                cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS,
+                                               ipd_sub_port_fcs.u64);
+
+                                /* Clear any error bits */
+                                cvmx_write_csr(CVMX_GMXX_RXX_INT_REG
+                                               (index, interface),
+                                               gmxx_rxx_int_reg.u64);
+                                DEBUGPRINT("%s: Using 10Mbps with software "
+                                           "preamble removal\n",
+                                     dev->name);
+                        }
+                }
+                spin_unlock_irqrestore(&global_register_lock, flags);
+                return;
+        }
+
+        /* If the 10Mbps preamble workaround is allowed we need to on
+           preamble checking, FCS stripping, and clear error bits on
+           every speed change. If errors occur during 10Mbps operation
+           the above code will change this stuff */
+        if (USE_10MBPS_PREAMBLE_WORKAROUND) {
+
+                union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
+                union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
+                union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
+                int interface = INTERFACE(priv->port);
+                int index = INDEX(priv->port);
+
+                /* Enable preamble checking */
+                gmxx_rxx_frm_ctl.u64 =
+                    cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
+                gmxx_rxx_frm_ctl.s.pre_chk = 1;
+                cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface),
+                               gmxx_rxx_frm_ctl.u64);
+                /* Enable FCS stripping */
+                ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
+                ipd_sub_port_fcs.s.port_bit |= 1ull << priv->port;
+                cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
+                /* Clear any error bits */
+                gmxx_rxx_int_reg.u64 =
+                    cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, interface));
+                cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface),
+                               gmxx_rxx_int_reg.u64);
+        }
+
+        link_info = cvmx_helper_link_autoconf(priv->port);
+        priv->link_info = link_info.u64;
+        spin_unlock_irqrestore(&global_register_lock, flags);
+
+        /* Tell Linux */
+        if (link_info.s.link_up) {
+
+                if (!netif_carrier_ok(dev))
+                        netif_carrier_on(dev);
+                if (priv->queue != -1)
+                        DEBUGPRINT
+                            ("%s: %u Mbps %s duplex, port %2d, queue %2d\n",
+                             dev->name, link_info.s.speed,
+                             (link_info.s.full_duplex) ? "Full" : "Half",
+                             priv->port, priv->queue);
+                else
+                        DEBUGPRINT("%s: %u Mbps %s duplex, port %2d, POW\n",
+                                   dev->name, link_info.s.speed,
+                                   (link_info.s.full_duplex) ? "Full" : "Half",
+                                   priv->port);
+        } else {
+
+                if (netif_carrier_ok(dev))
+                        netif_carrier_off(dev);
+                DEBUGPRINT("%s: Link down\n", dev->name);
+        }
+}
+
+static irqreturn_t cvm_oct_rgmii_rml_interrupt(int cpl, void *dev_id)
+{
+        union cvmx_npi_rsl_int_blocks rsl_int_blocks;
+        int index;
+        irqreturn_t return_status = IRQ_NONE;
+
+        rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS);
+
+        /* Check and see if this interrupt was caused by the GMX0 block */
+        if (rsl_int_blocks.s.gmx0) {
+
+                int interface = 0;
+                /* Loop through every port of this interface */
+                for (index = 0;
+                     index < cvmx_helper_ports_on_interface(interface);
+                     index++) {
+
+                        /* Read the GMX interrupt status bits */
+                        union cvmx_gmxx_rxx_int_reg gmx_rx_int_reg;
+                        gmx_rx_int_reg.u64 =
+                            cvmx_read_csr(CVMX_GMXX_RXX_INT_REG
+                                          (index, interface));
+                        gmx_rx_int_reg.u64 &=
+                            cvmx_read_csr(CVMX_GMXX_RXX_INT_EN
+                                          (index, interface));
+                        /* Poll the port if inband status changed */
+                        if (gmx_rx_int_reg.s.phy_dupx
+                            || gmx_rx_int_reg.s.phy_link
+                            || gmx_rx_int_reg.s.phy_spd) {
+
+                                struct net_device *dev =
+                                    cvm_oct_device[cvmx_helper_get_ipd_port
+                                                   (interface, index)];
+                                if (dev)
+                                        cvm_oct_rgmii_poll(dev);
+                                gmx_rx_int_reg.u64 = 0;
+                                gmx_rx_int_reg.s.phy_dupx = 1;
+                                gmx_rx_int_reg.s.phy_link = 1;
+                                gmx_rx_int_reg.s.phy_spd = 1;
+                                cvmx_write_csr(CVMX_GMXX_RXX_INT_REG
+                                               (index, interface),
+                                               gmx_rx_int_reg.u64);
+                                return_status = IRQ_HANDLED;
+                        }
+                }
+        }
+
+        /* Check and see if this interrupt was caused by the GMX1 block */
+        if (rsl_int_blocks.s.gmx1) {
+
+                int interface = 1;
+                /* Loop through every port of this interface */
+                for (index = 0;
+                     index < cvmx_helper_ports_on_interface(interface);
+                     index++) {
+
+                        /* Read the GMX interrupt status bits */
+                        union cvmx_gmxx_rxx_int_reg gmx_rx_int_reg;
+                        gmx_rx_int_reg.u64 =
+                            cvmx_read_csr(CVMX_GMXX_RXX_INT_REG
+                                          (index, interface));
+                        gmx_rx_int_reg.u64 &=
+                            cvmx_read_csr(CVMX_GMXX_RXX_INT_EN
+                                          (index, interface));
+                        /* Poll the port if inband status changed */
+                        if (gmx_rx_int_reg.s.phy_dupx
+                            || gmx_rx_int_reg.s.phy_link
+                            || gmx_rx_int_reg.s.phy_spd) {
+
+                                struct net_device *dev =
+                                    cvm_oct_device[cvmx_helper_get_ipd_port
+                                                   (interface, index)];
+                                if (dev)
+                                        cvm_oct_rgmii_poll(dev);
+                                gmx_rx_int_reg.u64 = 0;
+                                gmx_rx_int_reg.s.phy_dupx = 1;
+                                gmx_rx_int_reg.s.phy_link = 1;
+                                gmx_rx_int_reg.s.phy_spd = 1;
+                                cvmx_write_csr(CVMX_GMXX_RXX_INT_REG
+                                               (index, interface),
+                                               gmx_rx_int_reg.u64);
+                                return_status = IRQ_HANDLED;
+                        }
+                }
+        }
+        return return_status;
+}
+
+static int cvm_oct_rgmii_open(struct net_device *dev)
+{
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int interface = INTERFACE(priv->port);
+        int index = INDEX(priv->port);
+        cvmx_helper_link_info_t link_info;
+
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+        gmx_cfg.s.en = 1;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+
+        if (!octeon_is_simulation()) {
+                link_info = cvmx_helper_link_get(priv->port);
+                if (!link_info.s.link_up)
+                        netif_carrier_off(dev);
+        }
+
+        return 0;
+}
+
+static int cvm_oct_rgmii_stop(struct net_device *dev)
+{
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int interface = INTERFACE(priv->port);
+        int index = INDEX(priv->port);
+
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+        gmx_cfg.s.en = 0;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+        return 0;
+}
+
+int cvm_oct_rgmii_init(struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int r;
+
+        cvm_oct_common_init(dev);
+        dev->open = cvm_oct_rgmii_open;
+        dev->stop = cvm_oct_rgmii_stop;
+        dev->stop(dev);
+
+        /*
+         * Due to GMX errata in CN3XXX series chips, it is necessary
+         * to take the link down immediately whne the PHY changes
+         * state. In order to do this we call the poll function every
+         * time the RGMII inband status changes.  This may cause
+         * problems if the PHY doesn't implement inband status
+         * properly.
+         */
+        if (number_rgmii_ports == 0) {
+                r = request_irq(OCTEON_IRQ_RML, cvm_oct_rgmii_rml_interrupt,
+                                IRQF_SHARED, "RGMII", &number_rgmii_ports);
+        }
+        number_rgmii_ports++;
+
+        /*
+         * Only true RGMII ports need to be polled. In GMII mode, port
+         * 0 is really a RGMII port.
+         */
+        if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII)
+             && (priv->port == 0))
+            || (priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
+
+                if (!octeon_is_simulation()) {
+
+                        union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
+                        int interface = INTERFACE(priv->port);
+                        int index = INDEX(priv->port);
+
+                        /*
+                         * Enable interrupts on inband status changes
+                         * for this port.
+                         */
+                        gmx_rx_int_en.u64 =
+                            cvmx_read_csr(CVMX_GMXX_RXX_INT_EN
+                                          (index, interface));
+                        gmx_rx_int_en.s.phy_dupx = 1;
+                        gmx_rx_int_en.s.phy_link = 1;
+                        gmx_rx_int_en.s.phy_spd = 1;
+                        cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface),
+                                       gmx_rx_int_en.u64);
+                        priv->poll = cvm_oct_rgmii_poll;
+                }
+        }
+
+        return 0;
+}
+
+void cvm_oct_rgmii_uninit(struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        cvm_oct_common_uninit(dev);
+
+        /*
+         * Only true RGMII ports need to be polled. In GMII mode, port
+         * 0 is really a RGMII port.
+         */
+        if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII)
+             && (priv->port == 0))
+            || (priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
+
+                if (!octeon_is_simulation()) {
+
+                        union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
+                        int interface = INTERFACE(priv->port);
+                        int index = INDEX(priv->port);
+
+                        /*
+                         * Disable interrupts on inband status changes
+                         * for this port.
+                         */
+                        gmx_rx_int_en.u64 =
+                            cvmx_read_csr(CVMX_GMXX_RXX_INT_EN
+                                          (index, interface));
+                        gmx_rx_int_en.s.phy_dupx = 0;
+                        gmx_rx_int_en.s.phy_link = 0;
+                        gmx_rx_int_en.s.phy_spd = 0;
+                        cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface),
+                                       gmx_rx_int_en.u64);
+                }
+        }
+
+        /* Remove the interrupt handler when the last port is removed. */
+        number_rgmii_ports--;
+        if (number_rgmii_ports == 0)
+                free_irq(OCTEON_IRQ_RML, &number_rgmii_ports);
+}
diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c
new file mode 100644
index 000000000000..1b237b7e689d
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-rx.c
@@ -0,0 +1,505 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/cache.h>
+#include <linux/netdevice.h>
+#include <linux/init.h>
+#include <linux/etherdevice.h>
+#include <linux/ip.h>
+#include <linux/string.h>
+#include <linux/prefetch.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/seq_file.h>
+#include <linux/proc_fs.h>
+#include <net/dst.h>
+#ifdef CONFIG_XFRM
+#include <linux/xfrm.h>
+#include <net/xfrm.h>
+#endif /* CONFIG_XFRM */
+
+#include <asm/atomic.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "ethernet-defines.h"
+#include "octeon-ethernet.h"
+#include "ethernet-mem.h"
+#include "ethernet-util.h"
+
+#include "cvmx-helper.h"
+#include "cvmx-wqe.h"
+#include "cvmx-fau.h"
+#include "cvmx-pow.h"
+#include "cvmx-pip.h"
+#include "cvmx-scratch.h"
+
+#include "cvmx-gmxx-defs.h"
+
+struct cvm_tasklet_wrapper {
+        struct tasklet_struct t;
+};
+
+/*
+ * Aligning the tasklet_struct on cachline boundries seems to decrease
+ * throughput even though in theory it would reduce contantion on the
+ * cache lines containing the locks.
+ */
+
+static struct cvm_tasklet_wrapper cvm_oct_tasklet[NR_CPUS];
+
+/**
+ * Interrupt handler. The interrupt occurs whenever the POW
+ * transitions from 0->1 packets in our group.
+ *
+ * @cpl:
+ * @dev_id:
+ * @regs:
+ * Returns
+ */
+irqreturn_t cvm_oct_do_interrupt(int cpl, void *dev_id)
+{
+        /* Acknowledge the interrupt */
+        if (INTERRUPT_LIMIT)
+                cvmx_write_csr(CVMX_POW_WQ_INT, 1 << pow_receive_group);
+        else
+                cvmx_write_csr(CVMX_POW_WQ_INT, 0x10001 << pow_receive_group);
+        preempt_disable();
+        tasklet_schedule(&cvm_oct_tasklet[smp_processor_id()].t);
+        preempt_enable();
+        return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_NET_POLL_CONTROLLER
+/**
+ * This is called when the kernel needs to manually poll the
+ * device. For Octeon, this is simply calling the interrupt
+ * handler. We actually poll all the devices, not just the
+ * one supplied.
+ *
+ * @dev:    Device to poll. Unused
+ */
+void cvm_oct_poll_controller(struct net_device *dev)
+{
+        preempt_disable();
+        tasklet_schedule(&cvm_oct_tasklet[smp_processor_id()].t);
+        preempt_enable();
+}
+#endif
+
+/**
+ * This is called on receive errors, and determines if the packet
+ * can be dropped early-on in cvm_oct_tasklet_rx().
+ *
+ * @work: Work queue entry pointing to the packet.
+ * Returns Non-zero if the packet can be dropped, zero otherwise.
+ */
+static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work)
+{
+        if ((work->word2.snoip.err_code == 10) && (work->len <= 64)) {
+                /*
+                 * Ignore length errors on min size packets. Some
+                 * equipment incorrectly pads packets to 64+4FCS
+                 * instead of 60+4FCS.  Note these packets still get
+                 * counted as frame errors.
+                 */
+        } else
+            if (USE_10MBPS_PREAMBLE_WORKAROUND
+                && ((work->word2.snoip.err_code == 5)
+                    || (work->word2.snoip.err_code == 7))) {
+
+                /*
+                 * We received a packet with either an alignment error
+                 * or a FCS error. This may be signalling that we are
+                 * running 10Mbps with GMXX_RXX_FRM_CTL[PRE_CHK}
+                 * off. If this is the case we need to parse the
+                 * packet to determine if we can remove a non spec
+                 * preamble and generate a correct packet.
+                 */
+                int interface = cvmx_helper_get_interface_num(work->ipprt);
+                int index = cvmx_helper_get_interface_index_num(work->ipprt);
+                union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
+                gmxx_rxx_frm_ctl.u64 =
+                    cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface));
+                if (gmxx_rxx_frm_ctl.s.pre_chk == 0) {
+
+                        uint8_t *ptr =
+                            cvmx_phys_to_ptr(work->packet_ptr.s.addr);
+                        int i = 0;
+
+                        while (i < work->len - 1) {
+                                if (*ptr != 0x55)
+                                        break;
+                                ptr++;
+                                i++;
+                        }
+
+                        if (*ptr == 0xd5) {
+                                /*
+                                   DEBUGPRINT("Port %d received 0xd5 preamble\n", work->ipprt);
+                                 */
+                                work->packet_ptr.s.addr += i + 1;
+                                work->len -= i + 5;
+                        } else if ((*ptr & 0xf) == 0xd) {
+                                /*
+                                   DEBUGPRINT("Port %d received 0x?d preamble\n", work->ipprt);
+                                 */
+                                work->packet_ptr.s.addr += i;
+                                work->len -= i + 4;
+                                for (i = 0; i < work->len; i++) {
+                                        *ptr =
+                                            ((*ptr & 0xf0) >> 4) |
+                                            ((*(ptr + 1) & 0xf) << 4);
+                                        ptr++;
+                                }
+                        } else {
+                                DEBUGPRINT("Port %d unknown preamble, packet "
+                                           "dropped\n",
+                                     work->ipprt);
+                                /*
+                                   cvmx_helper_dump_packet(work);
+                                 */
+                                cvm_oct_free_work(work);
+                                return 1;
+                        }
+                }
+        } else {
+                DEBUGPRINT("Port %d receive error code %d, packet dropped\n",
+                           work->ipprt, work->word2.snoip.err_code);
+                cvm_oct_free_work(work);
+                return 1;
+        }
+
+        return 0;
+}
+
+/**
+ * Tasklet function that is scheduled on a core when an interrupt occurs.
+ *
+ * @unused:
+ */
+void cvm_oct_tasklet_rx(unsigned long unused)
+{
+        const int coreid = cvmx_get_core_num();
+        uint64_t old_group_mask;
+        uint64_t old_scratch;
+        int rx_count = 0;
+        int number_to_free;
+        int num_freed;
+        int packet_not_copied;
+
+        /* Prefetch cvm_oct_device since we know we need it soon */
+        prefetch(cvm_oct_device);
+
+        if (USE_ASYNC_IOBDMA) {
+                /* Save scratch in case userspace is using it */
+                CVMX_SYNCIOBDMA;
+                old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
+        }
+
+        /* Only allow work for our group (and preserve priorities) */
+        old_group_mask = cvmx_read_csr(CVMX_POW_PP_GRP_MSKX(coreid));
+        cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid),
+                       (old_group_mask & ~0xFFFFull) | 1 << pow_receive_group);
+
+        if (USE_ASYNC_IOBDMA)
+                cvmx_pow_work_request_async(CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
+
+        while (1) {
+                struct sk_buff *skb = NULL;
+                int skb_in_hw;
+                cvmx_wqe_t *work;
+
+                if (USE_ASYNC_IOBDMA) {
+                        work = cvmx_pow_work_response_async(CVMX_SCR_SCRATCH);
+                } else {
+                        if ((INTERRUPT_LIMIT == 0)
+                            || likely(rx_count < MAX_RX_PACKETS))
+                                work =
+                                    cvmx_pow_work_request_sync
+                                    (CVMX_POW_NO_WAIT);
+                        else
+                                work = NULL;
+                }
+                prefetch(work);
+                if (work == NULL)
+                        break;
+
+                /*
+                 * Limit each core to processing MAX_RX_PACKETS
+                 * packets without a break.  This way the RX can't
+                 * starve the TX task.
+                 */
+                if (USE_ASYNC_IOBDMA) {
+
+                        if ((INTERRUPT_LIMIT == 0)
+                            || likely(rx_count < MAX_RX_PACKETS))
+                                cvmx_pow_work_request_async_nocheck
+                                    (CVMX_SCR_SCRATCH, CVMX_POW_NO_WAIT);
+                        else {
+                                cvmx_scratch_write64(CVMX_SCR_SCRATCH,
+                                                     0x8000000000000000ull);
+                                cvmx_pow_tag_sw_null_nocheck();
+                        }
+                }
+
+                skb_in_hw = USE_SKBUFFS_IN_HW && work->word2.s.bufs == 1;
+                if (likely(skb_in_hw)) {
+                        skb =
+                            *(struct sk_buff
+                              **)(cvm_oct_get_buffer_ptr(work->packet_ptr) -
+                                  sizeof(void *));
+                        prefetch(&skb->head);
+                        prefetch(&skb->len);
+                }
+                prefetch(cvm_oct_device[work->ipprt]);
+
+                rx_count++;
+                /* Immediately throw away all packets with receive errors */
+                if (unlikely(work->word2.snoip.rcv_error)) {
+                        if (cvm_oct_check_rcv_error(work))
+                                continue;
+                }
+
+                /*
+                 * We can only use the zero copy path if skbuffs are
+                 * in the FPA pool and the packet fits in a single
+                 * buffer.
+                 */
+                if (likely(skb_in_hw)) {
+                        /*
+                         * This calculation was changed in case the
+                         * skb header is using a different address
+                         * aliasing type than the buffer. It doesn't
+                         * make any differnece now, but the new one is
+                         * more correct.
+                         */
+                        skb->data =
+                            skb->head + work->packet_ptr.s.addr -
+                            cvmx_ptr_to_phys(skb->head);
+                        prefetch(skb->data);
+                        skb->len = work->len;
+                        skb_set_tail_pointer(skb, skb->len);
+                        packet_not_copied = 1;
+                } else {
+
+                        /*
+                         * We have to copy the packet. First allocate
+                         * an skbuff for it.
+                         */
+                        skb = dev_alloc_skb(work->len);
+                        if (!skb) {
+                                DEBUGPRINT("Port %d failed to allocate "
+                                           "skbuff, packet dropped\n",
+                                     work->ipprt);
+                                cvm_oct_free_work(work);
+                                continue;
+                        }
+
+                        /*
+                         * Check if we've received a packet that was
+                         * entirely stored in the work entry. This is
+                         * untested.
+                         */
+                        if (unlikely(work->word2.s.bufs == 0)) {
+                                uint8_t *ptr = work->packet_data;
+
+                                if (likely(!work->word2.s.not_IP)) {
+                                        /*
+                                         * The beginning of the packet
+                                         * moves for IP packets.
+                                         */
+                                        if (work->word2.s.is_v6)
+                                                ptr += 2;
+                                        else
+                                                ptr += 6;
+                                }
+                                memcpy(skb_put(skb, work->len), ptr, work->len);
+                                /* No packet buffers to free */
+                        } else {
+                                int segments = work->word2.s.bufs;
+                                union cvmx_buf_ptr segment_ptr =
+                                        work->packet_ptr;
+                                int len = work->len;
+
+                                while (segments--) {
+                                        union cvmx_buf_ptr next_ptr =
+                                            *(union cvmx_buf_ptr *)
+                                            cvmx_phys_to_ptr(segment_ptr.s.
+                                                             addr - 8);
+                        /*
+                         * Octeon Errata PKI-100: The segment size is
+                         * wrong. Until it is fixed, calculate the
+                         * segment size based on the packet pool
+                         * buffer size. When it is fixed, the
+                         * following line should be replaced with this
+                         * one: int segment_size =
+                         * segment_ptr.s.size;
+                         */
+                                        int segment_size =
+                                            CVMX_FPA_PACKET_POOL_SIZE -
+                                            (segment_ptr.s.addr -
+                                             (((segment_ptr.s.addr >> 7) -
+                                               segment_ptr.s.back) << 7));
+                                        /* Don't copy more than what is left
+                                           in the packet */
+                                        if (segment_size > len)
+                                                segment_size = len;
+                                        /* Copy the data into the packet */
+                                        memcpy(skb_put(skb, segment_size),
+                                               cvmx_phys_to_ptr(segment_ptr.s.
+                                                                addr),
+                                               segment_size);
+                                        /* Reduce the amount of bytes left
+                                           to copy */
+                                        len -= segment_size;
+                                        segment_ptr = next_ptr;
+                                }
+                        }
+                        packet_not_copied = 0;
+                }
+
+                if (likely((work->ipprt < TOTAL_NUMBER_OF_PORTS) &&
+                           cvm_oct_device[work->ipprt])) {
+                        struct net_device *dev = cvm_oct_device[work->ipprt];
+                        struct octeon_ethernet *priv = netdev_priv(dev);
+
+                        /* Only accept packets for devices
+                           that are currently up */
+                        if (likely(dev->flags & IFF_UP)) {
+                                skb->protocol = eth_type_trans(skb, dev);
+                                skb->dev = dev;
+
+                                if (unlikely
+                                    (work->word2.s.not_IP
+                                     || work->word2.s.IP_exc
+                                     || work->word2.s.L4_error))
+                                        skb->ip_summed = CHECKSUM_NONE;
+                                else
+                                        skb->ip_summed = CHECKSUM_UNNECESSARY;
+
+                                /* Increment RX stats for virtual ports */
+                                if (work->ipprt >= CVMX_PIP_NUM_INPUT_PORTS) {
+#ifdef CONFIG_64BIT
+                                        atomic64_add(1, (atomic64_t *)&priv->stats.rx_packets);
+                                        atomic64_add(skb->len, (atomic64_t *)&priv->stats.rx_bytes);
+#else
+                                        atomic_add(1, (atomic_t *)&priv->stats.rx_packets);
+                                        atomic_add(skb->len, (atomic_t *)&priv->stats.rx_bytes);
+#endif
+                                }
+                                netif_receive_skb(skb);
+                        } else {
+                                /*
+                                 * Drop any packet received for a
+                                 * device that isn't up.
+                                 */
+                                /*
+                                   DEBUGPRINT("%s: Device not up, packet dropped\n",
+                                   dev->name);
+                                 */
+#ifdef CONFIG_64BIT
+                                atomic64_add(1, (atomic64_t *)&priv->stats.rx_dropped);
+#else
+                                atomic_add(1, (atomic_t *)&priv->stats.rx_dropped);
+#endif
+                                dev_kfree_skb_irq(skb);
+                        }
+                } else {
+                        /*
+                         * Drop any packet received for a device that
+                         * doesn't exist.
+                         */
+                        DEBUGPRINT("Port %d not controlled by Linux, packet "
+                                   "dropped\n",
+                             work->ipprt);
+                        dev_kfree_skb_irq(skb);
+                }
+                /*
+                 * Check to see if the skbuff and work share the same
+                 * packet buffer.
+                 */
+                if (USE_SKBUFFS_IN_HW && likely(packet_not_copied)) {
+                        /*
+                         * This buffer needs to be replaced, increment
+                         * the number of buffers we need to free by
+                         * one.
+                         */
+                        cvmx_fau_atomic_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE,
+                                              1);
+
+                        cvmx_fpa_free(work, CVMX_FPA_WQE_POOL,
+                                      DONT_WRITEBACK(1));
+                } else {
+                        cvm_oct_free_work(work);
+                }
+        }
+
+        /* Restore the original POW group mask */
+        cvmx_write_csr(CVMX_POW_PP_GRP_MSKX(coreid), old_group_mask);
+        if (USE_ASYNC_IOBDMA) {
+                /* Restore the scratch area */
+                cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
+        }
+
+        if (USE_SKBUFFS_IN_HW) {
+                /* Refill the packet buffer pool */
+                number_to_free =
+                    cvmx_fau_fetch_and_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0);
+
+                if (number_to_free > 0) {
+                        cvmx_fau_atomic_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE,
+                                              -number_to_free);
+                        num_freed =
+                            cvm_oct_mem_fill_fpa(CVMX_FPA_PACKET_POOL,
+                                                 CVMX_FPA_PACKET_POOL_SIZE,
+                                                 number_to_free);
+                        if (num_freed != number_to_free) {
+                                cvmx_fau_atomic_add32
+                                    (FAU_NUM_PACKET_BUFFERS_TO_FREE,
+                                     number_to_free - num_freed);
+                        }
+                }
+        }
+}
+
+void cvm_oct_rx_initialize(void)
+{
+        int i;
+        /* Initialize all of the tasklets */
+        for (i = 0; i < NR_CPUS; i++)
+                tasklet_init(&cvm_oct_tasklet[i].t, cvm_oct_tasklet_rx, 0);
+}
+
+void cvm_oct_rx_shutdown(void)
+{
+        int i;
+        /* Shutdown all of the tasklets */
+        for (i = 0; i < NR_CPUS; i++)
+                tasklet_kill(&cvm_oct_tasklet[i].t);
+}
diff --git a/drivers/staging/octeon/ethernet-rx.h b/drivers/staging/octeon/ethernet-rx.h
new file mode 100644
index 000000000000..a9b72b87a7a6
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-rx.h
@@ -0,0 +1,33 @@
+/*********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+*********************************************************************/
+
+irqreturn_t cvm_oct_do_interrupt(int cpl, void *dev_id);
+void cvm_oct_poll_controller(struct net_device *dev);
+void cvm_oct_tasklet_rx(unsigned long unused);
+
+void cvm_oct_rx_initialize(void);
+void cvm_oct_rx_shutdown(void);
diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c
new file mode 100644
index 000000000000..58fa39c1d675
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-sgmii.c
@@ -0,0 +1,129 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/mii.h>
+#include <net/dst.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "ethernet-defines.h"
+#include "octeon-ethernet.h"
+#include "ethernet-util.h"
+#include "ethernet-common.h"
+
+#include "cvmx-helper.h"
+
+#include "cvmx-gmxx-defs.h"
+
+static int cvm_oct_sgmii_open(struct net_device *dev)
+{
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int interface = INTERFACE(priv->port);
+        int index = INDEX(priv->port);
+        cvmx_helper_link_info_t link_info;
+
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+        gmx_cfg.s.en = 1;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+
+        if (!octeon_is_simulation()) {
+                link_info = cvmx_helper_link_get(priv->port);
+                if (!link_info.s.link_up)
+                        netif_carrier_off(dev);
+        }
+
+        return 0;
+}
+
+static int cvm_oct_sgmii_stop(struct net_device *dev)
+{
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int interface = INTERFACE(priv->port);
+        int index = INDEX(priv->port);
+
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+        gmx_cfg.s.en = 0;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+        return 0;
+}
+
+static void cvm_oct_sgmii_poll(struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        cvmx_helper_link_info_t link_info;
+
+        link_info = cvmx_helper_link_get(priv->port);
+        if (link_info.u64 == priv->link_info)
+                return;
+
+        link_info = cvmx_helper_link_autoconf(priv->port);
+        priv->link_info = link_info.u64;
+
+        /* Tell Linux */
+        if (link_info.s.link_up) {
+
+                if (!netif_carrier_ok(dev))
+                        netif_carrier_on(dev);
+                if (priv->queue != -1)
+                        DEBUGPRINT
+                            ("%s: %u Mbps %s duplex, port %2d, queue %2d\n",
+                             dev->name, link_info.s.speed,
+                             (link_info.s.full_duplex) ? "Full" : "Half",
+                             priv->port, priv->queue);
+                else
+                        DEBUGPRINT("%s: %u Mbps %s duplex, port %2d, POW\n",
+                                   dev->name, link_info.s.speed,
+                                   (link_info.s.full_duplex) ? "Full" : "Half",
+                                   priv->port);
+        } else {
+                if (netif_carrier_ok(dev))
+                        netif_carrier_off(dev);
+                DEBUGPRINT("%s: Link down\n", dev->name);
+        }
+}
+
+int cvm_oct_sgmii_init(struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        cvm_oct_common_init(dev);
+        dev->open = cvm_oct_sgmii_open;
+        dev->stop = cvm_oct_sgmii_stop;
+        dev->stop(dev);
+        if (!octeon_is_simulation())
+                priv->poll = cvm_oct_sgmii_poll;
+
+        /* FIXME: Need autoneg logic */
+        return 0;
+}
+
+void cvm_oct_sgmii_uninit(struct net_device *dev)
+{
+        cvm_oct_common_uninit(dev);
+}
diff --git a/drivers/staging/octeon/ethernet-spi.c b/drivers/staging/octeon/ethernet-spi.c
new file mode 100644
index 000000000000..e0971bbe4ddc
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-spi.c
@@ -0,0 +1,323 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/mii.h>
+#include <net/dst.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "ethernet-defines.h"
+#include "octeon-ethernet.h"
+#include "ethernet-common.h"
+#include "ethernet-util.h"
+
+#include "cvmx-spi.h"
+
+#include <asm/octeon/cvmx-npi-defs.h>
+#include "cvmx-spxx-defs.h"
+#include "cvmx-stxx-defs.h"
+
+static int number_spi_ports;
+static int need_retrain[2] = { 0, 0 };
+
+static irqreturn_t cvm_oct_spi_rml_interrupt(int cpl, void *dev_id)
+{
+        irqreturn_t return_status = IRQ_NONE;
+        union cvmx_npi_rsl_int_blocks rsl_int_blocks;
+
+        /* Check and see if this interrupt was caused by the GMX block */
+        rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS);
+        if (rsl_int_blocks.s.spx1) {    /* 19 - SPX1_INT_REG & STX1_INT_REG */
+
+                union cvmx_spxx_int_reg spx_int_reg;
+                union cvmx_stxx_int_reg stx_int_reg;
+
+                spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(1));
+                cvmx_write_csr(CVMX_SPXX_INT_REG(1), spx_int_reg.u64);
+                if (!need_retrain[1]) {
+
+                        spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(1));
+                        if (spx_int_reg.s.spf)
+                                pr_err("SPI1: SRX Spi4 interface down\n");
+                        if (spx_int_reg.s.calerr)
+                                pr_err("SPI1: SRX Spi4 Calendar table "
+                                       "parity error\n");
+                        if (spx_int_reg.s.syncerr)
+                                pr_err("SPI1: SRX Consecutive Spi4 DIP4 "
+                                       "errors have exceeded "
+                                       "SPX_ERR_CTL[ERRCNT]\n");
+                        if (spx_int_reg.s.diperr)
+                                pr_err("SPI1: SRX Spi4 DIP4 error\n");
+                        if (spx_int_reg.s.tpaovr)
+                                pr_err("SPI1: SRX Selected port has hit "
+                                       "TPA overflow\n");
+                        if (spx_int_reg.s.rsverr)
+                                pr_err("SPI1: SRX Spi4 reserved control "
+                                       "word detected\n");
+                        if (spx_int_reg.s.drwnng)
+                                pr_err("SPI1: SRX Spi4 receive FIFO "
+                                       "drowning/overflow\n");
+                        if (spx_int_reg.s.clserr)
+                                pr_err("SPI1: SRX Spi4 packet closed on "
+                                       "non-16B alignment without EOP\n");
+                        if (spx_int_reg.s.spiovr)
+                                pr_err("SPI1: SRX Spi4 async FIFO overflow\n");
+                        if (spx_int_reg.s.abnorm)
+                                pr_err("SPI1: SRX Abnormal packet "
+                                       "termination (ERR bit)\n");
+                        if (spx_int_reg.s.prtnxa)
+                                pr_err("SPI1: SRX Port out of range\n");
+                }
+
+                stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(1));
+                cvmx_write_csr(CVMX_STXX_INT_REG(1), stx_int_reg.u64);
+                if (!need_retrain[1]) {
+
+                        stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(1));
+                        if (stx_int_reg.s.syncerr)
+                                pr_err("SPI1: STX Interface encountered a "
+                                       "fatal error\n");
+                        if (stx_int_reg.s.frmerr)
+                                pr_err("SPI1: STX FRMCNT has exceeded "
+                                       "STX_DIP_CNT[MAXFRM]\n");
+                        if (stx_int_reg.s.unxfrm)
+                                pr_err("SPI1: STX Unexpected framing "
+                                       "sequence\n");
+                        if (stx_int_reg.s.nosync)
+                                pr_err("SPI1: STX ERRCNT has exceeded "
+                                       "STX_DIP_CNT[MAXDIP]\n");
+                        if (stx_int_reg.s.diperr)
+                                pr_err("SPI1: STX DIP2 error on the Spi4 "
+                                       "Status channel\n");
+                        if (stx_int_reg.s.datovr)
+                                pr_err("SPI1: STX Spi4 FIFO overflow error\n");
+                        if (stx_int_reg.s.ovrbst)
+                                pr_err("SPI1: STX Transmit packet burst "
+                                       "too big\n");
+                        if (stx_int_reg.s.calpar1)
+                                pr_err("SPI1: STX Calendar Table Parity "
+                                       "Error Bank1\n");
+                        if (stx_int_reg.s.calpar0)
+                                pr_err("SPI1: STX Calendar Table Parity "
+                                       "Error Bank0\n");
+                }
+
+                cvmx_write_csr(CVMX_SPXX_INT_MSK(1), 0);
+                cvmx_write_csr(CVMX_STXX_INT_MSK(1), 0);
+                need_retrain[1] = 1;
+                return_status = IRQ_HANDLED;
+        }
+
+        if (rsl_int_blocks.s.spx0) {    /* 18 - SPX0_INT_REG & STX0_INT_REG */
+                union cvmx_spxx_int_reg spx_int_reg;
+                union cvmx_stxx_int_reg stx_int_reg;
+
+                spx_int_reg.u64 = cvmx_read_csr(CVMX_SPXX_INT_REG(0));
+                cvmx_write_csr(CVMX_SPXX_INT_REG(0), spx_int_reg.u64);
+                if (!need_retrain[0]) {
+
+                        spx_int_reg.u64 &= cvmx_read_csr(CVMX_SPXX_INT_MSK(0));
+                        if (spx_int_reg.s.spf)
+                                pr_err("SPI0: SRX Spi4 interface down\n");
+                        if (spx_int_reg.s.calerr)
+                                pr_err("SPI0: SRX Spi4 Calendar table "
+                                       "parity error\n");
+                        if (spx_int_reg.s.syncerr)
+                                pr_err("SPI0: SRX Consecutive Spi4 DIP4 "
+                                       "errors have exceeded "
+                                       "SPX_ERR_CTL[ERRCNT]\n");
+                        if (spx_int_reg.s.diperr)
+                                pr_err("SPI0: SRX Spi4 DIP4 error\n");
+                        if (spx_int_reg.s.tpaovr)
+                                pr_err("SPI0: SRX Selected port has hit "
+                                       "TPA overflow\n");
+                        if (spx_int_reg.s.rsverr)
+                                pr_err("SPI0: SRX Spi4 reserved control "
+                                       "word detected\n");
+                        if (spx_int_reg.s.drwnng)
+                                pr_err("SPI0: SRX Spi4 receive FIFO "
+                                       "drowning/overflow\n");
+                        if (spx_int_reg.s.clserr)
+                                pr_err("SPI0: SRX Spi4 packet closed on "
+                                       "non-16B alignment without EOP\n");
+                        if (spx_int_reg.s.spiovr)
+                                pr_err("SPI0: SRX Spi4 async FIFO overflow\n");
+                        if (spx_int_reg.s.abnorm)
+                                pr_err("SPI0: SRX Abnormal packet "
+                                       "termination (ERR bit)\n");
+                        if (spx_int_reg.s.prtnxa)
+                                pr_err("SPI0: SRX Port out of range\n");
+                }
+
+                stx_int_reg.u64 = cvmx_read_csr(CVMX_STXX_INT_REG(0));
+                cvmx_write_csr(CVMX_STXX_INT_REG(0), stx_int_reg.u64);
+                if (!need_retrain[0]) {
+
+                        stx_int_reg.u64 &= cvmx_read_csr(CVMX_STXX_INT_MSK(0));
+                        if (stx_int_reg.s.syncerr)
+                                pr_err("SPI0: STX Interface encountered a "
+                                       "fatal error\n");
+                        if (stx_int_reg.s.frmerr)
+                                pr_err("SPI0: STX FRMCNT has exceeded "
+                                       "STX_DIP_CNT[MAXFRM]\n");
+                        if (stx_int_reg.s.unxfrm)
+                                pr_err("SPI0: STX Unexpected framing "
+                                       "sequence\n");
+                        if (stx_int_reg.s.nosync)
+                                pr_err("SPI0: STX ERRCNT has exceeded "
+                                       "STX_DIP_CNT[MAXDIP]\n");
+                        if (stx_int_reg.s.diperr)
+                                pr_err("SPI0: STX DIP2 error on the Spi4 "
+                                       "Status channel\n");
+                        if (stx_int_reg.s.datovr)
+                                pr_err("SPI0: STX Spi4 FIFO overflow error\n");
+                        if (stx_int_reg.s.ovrbst)
+                                pr_err("SPI0: STX Transmit packet burst "
+                                       "too big\n");
+                        if (stx_int_reg.s.calpar1)
+                                pr_err("SPI0: STX Calendar Table Parity "
+                                       "Error Bank1\n");
+                        if (stx_int_reg.s.calpar0)
+                                pr_err("SPI0: STX Calendar Table Parity "
+                                       "Error Bank0\n");
+                }
+
+                cvmx_write_csr(CVMX_SPXX_INT_MSK(0), 0);
+                cvmx_write_csr(CVMX_STXX_INT_MSK(0), 0);
+                need_retrain[0] = 1;
+                return_status = IRQ_HANDLED;
+        }
+
+        return return_status;
+}
+
+static void cvm_oct_spi_enable_error_reporting(int interface)
+{
+        union cvmx_spxx_int_msk spxx_int_msk;
+        union cvmx_stxx_int_msk stxx_int_msk;
+
+        spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface));
+        spxx_int_msk.s.calerr = 1;
+        spxx_int_msk.s.syncerr = 1;
+        spxx_int_msk.s.diperr = 1;
+        spxx_int_msk.s.tpaovr = 1;
+        spxx_int_msk.s.rsverr = 1;
+        spxx_int_msk.s.drwnng = 1;
+        spxx_int_msk.s.clserr = 1;
+        spxx_int_msk.s.spiovr = 1;
+        spxx_int_msk.s.abnorm = 1;
+        spxx_int_msk.s.prtnxa = 1;
+        cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64);
+
+        stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface));
+        stxx_int_msk.s.frmerr = 1;
+        stxx_int_msk.s.unxfrm = 1;
+        stxx_int_msk.s.nosync = 1;
+        stxx_int_msk.s.diperr = 1;
+        stxx_int_msk.s.datovr = 1;
+        stxx_int_msk.s.ovrbst = 1;
+        stxx_int_msk.s.calpar1 = 1;
+        stxx_int_msk.s.calpar0 = 1;
+        cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64);
+}
+
+static void cvm_oct_spi_poll(struct net_device *dev)
+{
+        static int spi4000_port;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int interface;
+
+        for (interface = 0; interface < 2; interface++) {
+
+                if ((priv->port == interface * 16) && need_retrain[interface]) {
+
+                        if (cvmx_spi_restart_interface
+                            (interface, CVMX_SPI_MODE_DUPLEX, 10) == 0) {
+                                need_retrain[interface] = 0;
+                                cvm_oct_spi_enable_error_reporting(interface);
+                        }
+                }
+
+                /*
+                 * The SPI4000 TWSI interface is very slow. In order
+                 * not to bring the system to a crawl, we only poll a
+                 * single port every second. This means negotiation
+                 * speed changes take up to 10 seconds, but at least
+                 * we don't waste absurd amounts of time waiting for
+                 * TWSI.
+                 */
+                if (priv->port == spi4000_port) {
+                        /*
+                         * This function does nothing if it is called on an
+                         * interface without a SPI4000.
+                         */
+                        cvmx_spi4000_check_speed(interface, priv->port);
+                        /*
+                         * Normal ordering increments. By decrementing
+                         * we only match once per iteration.
+                         */
+                        spi4000_port--;
+                        if (spi4000_port < 0)
+                                spi4000_port = 10;
+                }
+        }
+}
+
+int cvm_oct_spi_init(struct net_device *dev)
+{
+        int r;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+
+        if (number_spi_ports == 0) {
+                r = request_irq(OCTEON_IRQ_RML, cvm_oct_spi_rml_interrupt,
+                                IRQF_SHARED, "SPI", &number_spi_ports);
+        }
+        number_spi_ports++;
+
+        if ((priv->port == 0) || (priv->port == 16)) {
+                cvm_oct_spi_enable_error_reporting(INTERFACE(priv->port));
+                priv->poll = cvm_oct_spi_poll;
+        }
+        cvm_oct_common_init(dev);
+        return 0;
+}
+
+void cvm_oct_spi_uninit(struct net_device *dev)
+{
+        int interface;
+
+        cvm_oct_common_uninit(dev);
+        number_spi_ports--;
+        if (number_spi_ports == 0) {
+                for (interface = 0; interface < 2; interface++) {
+                        cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0);
+                        cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0);
+                }
+                free_irq(8 + 46, &number_spi_ports);
+        }
+}
diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c
new file mode 100644
index 000000000000..77b7122c8fdb
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-tx.c
@@ -0,0 +1,634 @@
+/*********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+*********************************************************************/
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/init.h>
+#include <linux/etherdevice.h>
+#include <linux/ip.h>
+#include <linux/string.h>
+#include <linux/ethtool.h>
+#include <linux/mii.h>
+#include <linux/seq_file.h>
+#include <linux/proc_fs.h>
+#include <net/dst.h>
+#ifdef CONFIG_XFRM
+#include <linux/xfrm.h>
+#include <net/xfrm.h>
+#endif /* CONFIG_XFRM */
+
+#include <asm/atomic.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "ethernet-defines.h"
+#include "octeon-ethernet.h"
+#include "ethernet-util.h"
+
+#include "cvmx-wqe.h"
+#include "cvmx-fau.h"
+#include "cvmx-pko.h"
+#include "cvmx-helper.h"
+
+#include "cvmx-gmxx-defs.h"
+
+/*
+ * You can define GET_SKBUFF_QOS() to override how the skbuff output
+ * function determines which output queue is used. The default
+ * implementation always uses the base queue for the port. If, for
+ * example, you wanted to use the skb->priority fieid, define
+ * GET_SKBUFF_QOS as: #define GET_SKBUFF_QOS(skb) ((skb)->priority)
+ */
+#ifndef GET_SKBUFF_QOS
+#define GET_SKBUFF_QOS(skb) 0
+#endif
+
+/**
+ * Packet transmit
+ *
+ * @skb:    Packet to send
+ * @dev:    Device info structure
+ * Returns Always returns zero
+ */
+int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+        cvmx_pko_command_word0_t pko_command;
+        union cvmx_buf_ptr hw_buffer;
+        uint64_t old_scratch;
+        uint64_t old_scratch2;
+        int dropped;
+        int qos;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int32_t in_use;
+        int32_t buffers_to_free;
+#if REUSE_SKBUFFS_WITHOUT_FREE
+        unsigned char *fpa_head;
+#endif
+
+        /*
+         * Prefetch the private data structure.  It is larger that one
+         * cache line.
+         */
+        prefetch(priv);
+
+        /* Start off assuming no drop */
+        dropped = 0;
+
+        /*
+         * The check on CVMX_PKO_QUEUES_PER_PORT_* is designed to
+         * completely remove "qos" in the event neither interface
+         * supports multiple queues per port.
+         */
+        if ((CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 > 1) ||
+            (CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 > 1)) {
+                qos = GET_SKBUFF_QOS(skb);
+                if (qos <= 0)
+                        qos = 0;
+                else if (qos >= cvmx_pko_get_num_queues(priv->port))
+                        qos = 0;
+        } else
+                qos = 0;
+
+        if (USE_ASYNC_IOBDMA) {
+                /* Save scratch in case userspace is using it */
+                CVMX_SYNCIOBDMA;
+                old_scratch = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
+                old_scratch2 = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8);
+
+                /*
+                 * Assume we're going to be able t osend this
+                 * packet. Fetch and increment the number of pending
+                 * packets for output.
+                 */
+                cvmx_fau_async_fetch_and_add32(CVMX_SCR_SCRATCH + 8,
+                                               FAU_NUM_PACKET_BUFFERS_TO_FREE,
+                                               0);
+                cvmx_fau_async_fetch_and_add32(CVMX_SCR_SCRATCH,
+                                               priv->fau + qos * 4, 1);
+        }
+
+        /*
+         * The CN3XXX series of parts has an errata (GMX-401) which
+         * causes the GMX block to hang if a collision occurs towards
+         * the end of a <68 byte packet. As a workaround for this, we
+         * pad packets to be 68 bytes whenever we are in half duplex
+         * mode. We don't handle the case of having a small packet but
+         * no room to add the padding.  The kernel should always give
+         * us at least a cache line
+         */
+        if ((skb->len < 64) && OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
+                union cvmx_gmxx_prtx_cfg gmx_prt_cfg;
+                int interface = INTERFACE(priv->port);
+                int index = INDEX(priv->port);
+
+                if (interface < 2) {
+                        /* We only need to pad packet in half duplex mode */
+                        gmx_prt_cfg.u64 =
+                            cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+                        if (gmx_prt_cfg.s.duplex == 0) {
+                                int add_bytes = 64 - skb->len;
+                                if ((skb_tail_pointer(skb) + add_bytes) <=
+                                    skb_end_pointer(skb))
+                                        memset(__skb_put(skb, add_bytes), 0,
+                                               add_bytes);
+                        }
+                }
+        }
+
+        /* Build the PKO buffer pointer */
+        hw_buffer.u64 = 0;
+        hw_buffer.s.addr = cvmx_ptr_to_phys(skb->data);
+        hw_buffer.s.pool = 0;
+        hw_buffer.s.size =
+            (unsigned long)skb_end_pointer(skb) - (unsigned long)skb->head;
+
+        /* Build the PKO command */
+        pko_command.u64 = 0;
+        pko_command.s.n2 = 1;   /* Don't pollute L2 with the outgoing packet */
+        pko_command.s.segs = 1;
+        pko_command.s.total_bytes = skb->len;
+        pko_command.s.size0 = CVMX_FAU_OP_SIZE_32;
+        pko_command.s.subone0 = 1;
+
+        pko_command.s.dontfree = 1;
+        pko_command.s.reg0 = priv->fau + qos * 4;
+        /*
+         * See if we can put this skb in the FPA pool. Any strange
+         * behavior from the Linux networking stack will most likely
+         * be caused by a bug in the following code. If some field is
+         * in use by the network stack and get carried over when a
+         * buffer is reused, bad thing may happen.  If in doubt and
+         * you dont need the absolute best performance, disable the
+         * define REUSE_SKBUFFS_WITHOUT_FREE. The reuse of buffers has
+         * shown a 25% increase in performance under some loads.
+         */
+#if REUSE_SKBUFFS_WITHOUT_FREE
+        fpa_head = skb->head + 128 - ((unsigned long)skb->head & 0x7f);
+        if (unlikely(skb->data < fpa_head)) {
+                /*
+                 * printk("TX buffer beginning can't meet FPA
+                 * alignment constraints\n");
+                 */
+                goto dont_put_skbuff_in_hw;
+        }
+        if (unlikely
+            ((skb_end_pointer(skb) - fpa_head) < CVMX_FPA_PACKET_POOL_SIZE)) {
+                /*
+                   printk("TX buffer isn't large enough for the FPA\n");
+                 */
+                goto dont_put_skbuff_in_hw;
+        }
+        if (unlikely(skb_shared(skb))) {
+                /*
+                   printk("TX buffer sharing data with someone else\n");
+                 */
+                goto dont_put_skbuff_in_hw;
+        }
+        if (unlikely(skb_cloned(skb))) {
+                /*
+                   printk("TX buffer has been cloned\n");
+                 */
+                goto dont_put_skbuff_in_hw;
+        }
+        if (unlikely(skb_header_cloned(skb))) {
+                /*
+                   printk("TX buffer header has been cloned\n");
+                 */
+                goto dont_put_skbuff_in_hw;
+        }
+        if (unlikely(skb->destructor)) {
+                /*
+                   printk("TX buffer has a destructor\n");
+                 */
+                goto dont_put_skbuff_in_hw;
+        }
+        if (unlikely(skb_shinfo(skb)->nr_frags)) {
+                /*
+                   printk("TX buffer has fragments\n");
+                 */
+                goto dont_put_skbuff_in_hw;
+        }
+        if (unlikely
+            (skb->truesize !=
+             sizeof(*skb) + skb_end_pointer(skb) - skb->head)) {
+                /*
+                   printk("TX buffer truesize has been changed\n");
+                 */
+                goto dont_put_skbuff_in_hw;
+        }
+
+        /*
+         * We can use this buffer in the FPA.  We don't need the FAU
+         * update anymore
+         */
+        pko_command.s.reg0 = 0;
+        pko_command.s.dontfree = 0;
+
+        hw_buffer.s.back = (skb->data - fpa_head) >> 7;
+        *(struct sk_buff **)(fpa_head - sizeof(void *)) = skb;
+
+        /*
+         * The skbuff will be reused without ever being freed. We must
+         * cleanup a bunch of Linux stuff.
+         */
+        dst_release(skb->dst);
+        skb->dst = NULL;
+#ifdef CONFIG_XFRM
+        secpath_put(skb->sp);
+        skb->sp = NULL;
+#endif
+        nf_reset(skb);
+
+#ifdef CONFIG_NET_SCHED
+        skb->tc_index = 0;
+#ifdef CONFIG_NET_CLS_ACT
+        skb->tc_verd = 0;
+#endif /* CONFIG_NET_CLS_ACT */
+#endif /* CONFIG_NET_SCHED */
+
+dont_put_skbuff_in_hw:
+#endif /* REUSE_SKBUFFS_WITHOUT_FREE */
+
+        /* Check if we can use the hardware checksumming */
+        if (USE_HW_TCPUDP_CHECKSUM && (skb->protocol == htons(ETH_P_IP)) &&
+            (ip_hdr(skb)->version == 4) && (ip_hdr(skb)->ihl == 5) &&
+            ((ip_hdr(skb)->frag_off == 0) || (ip_hdr(skb)->frag_off == 1 << 14))
+            && ((ip_hdr(skb)->protocol == IP_PROTOCOL_TCP)
+                || (ip_hdr(skb)->protocol == IP_PROTOCOL_UDP))) {
+                /* Use hardware checksum calc */
+                pko_command.s.ipoffp1 = sizeof(struct ethhdr) + 1;
+        }
+
+        if (USE_ASYNC_IOBDMA) {
+                /* Get the number of skbuffs in use by the hardware */
+                CVMX_SYNCIOBDMA;
+                in_use = cvmx_scratch_read64(CVMX_SCR_SCRATCH);
+                buffers_to_free = cvmx_scratch_read64(CVMX_SCR_SCRATCH + 8);
+        } else {
+                /* Get the number of skbuffs in use by the hardware */
+                in_use = cvmx_fau_fetch_and_add32(priv->fau + qos * 4, 1);
+                buffers_to_free =
+                    cvmx_fau_fetch_and_add32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0);
+        }
+
+        /*
+         * If we're sending faster than the receive can free them then
+         * don't do the HW free.
+         */
+        if ((buffers_to_free < -100) && !pko_command.s.dontfree) {
+                pko_command.s.dontfree = 1;
+                pko_command.s.reg0 = priv->fau + qos * 4;
+        }
+
+        cvmx_pko_send_packet_prepare(priv->port, priv->queue + qos,
+                                     CVMX_PKO_LOCK_CMD_QUEUE);
+
+        /* Drop this packet if we have too many already queued to the HW */
+        if (unlikely
+            (skb_queue_len(&priv->tx_free_list[qos]) >= MAX_OUT_QUEUE_DEPTH)) {
+                /*
+                   DEBUGPRINT("%s: Tx dropped. Too many queued\n", dev->name);
+                 */
+                dropped = 1;
+        }
+        /* Send the packet to the output queue */
+        else if (unlikely
+                 (cvmx_pko_send_packet_finish
+                  (priv->port, priv->queue + qos, pko_command, hw_buffer,
+                   CVMX_PKO_LOCK_CMD_QUEUE))) {
+                DEBUGPRINT("%s: Failed to send the packet\n", dev->name);
+                dropped = 1;
+        }
+
+        if (USE_ASYNC_IOBDMA) {
+                /* Restore the scratch area */
+                cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch);
+                cvmx_scratch_write64(CVMX_SCR_SCRATCH + 8, old_scratch2);
+        }
+
+        if (unlikely(dropped)) {
+                dev_kfree_skb_any(skb);
+                cvmx_fau_atomic_add32(priv->fau + qos * 4, -1);
+                priv->stats.tx_dropped++;
+        } else {
+                if (USE_SKBUFFS_IN_HW) {
+                        /* Put this packet on the queue to be freed later */
+                        if (pko_command.s.dontfree)
+                                skb_queue_tail(&priv->tx_free_list[qos], skb);
+                        else {
+                                cvmx_fau_atomic_add32
+                                    (FAU_NUM_PACKET_BUFFERS_TO_FREE, -1);
+                                cvmx_fau_atomic_add32(priv->fau + qos * 4, -1);
+                        }
+                } else {
+                        /* Put this packet on the queue to be freed later */
+                        skb_queue_tail(&priv->tx_free_list[qos], skb);
+                }
+        }
+
+        /* Free skbuffs not in use by the hardware, possibly two at a time */
+        if (skb_queue_len(&priv->tx_free_list[qos]) > in_use) {
+                spin_lock(&priv->tx_free_list[qos].lock);
+                /*
+                 * Check again now that we have the lock. It might
+                 * have changed.
+                 */
+                if (skb_queue_len(&priv->tx_free_list[qos]) > in_use)
+                        dev_kfree_skb(__skb_dequeue(&priv->tx_free_list[qos]));
+                if (skb_queue_len(&priv->tx_free_list[qos]) > in_use)
+                        dev_kfree_skb(__skb_dequeue(&priv->tx_free_list[qos]));
+                spin_unlock(&priv->tx_free_list[qos].lock);
+        }
+
+        return 0;
+}
+
+/**
+ * Packet transmit to the POW
+ *
+ * @skb:    Packet to send
+ * @dev:    Device info structure
+ * Returns Always returns zero
+ */
+int cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        void *packet_buffer;
+        void *copy_location;
+
+        /* Get a work queue entry */
+        cvmx_wqe_t *work = cvmx_fpa_alloc(CVMX_FPA_WQE_POOL);
+        if (unlikely(work == NULL)) {
+                DEBUGPRINT("%s: Failed to allocate a work queue entry\n",
+                           dev->name);
+                priv->stats.tx_dropped++;
+                dev_kfree_skb(skb);
+                return 0;
+        }
+
+        /* Get a packet buffer */
+        packet_buffer = cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL);
+        if (unlikely(packet_buffer == NULL)) {
+                DEBUGPRINT("%s: Failed to allocate a packet buffer\n",
+                           dev->name);
+                cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, DONT_WRITEBACK(1));
+                priv->stats.tx_dropped++;
+                dev_kfree_skb(skb);
+                return 0;
+        }
+
+        /*
+         * Calculate where we need to copy the data to. We need to
+         * leave 8 bytes for a next pointer (unused). We also need to
+         * include any configure skip. Then we need to align the IP
+         * packet src and dest into the same 64bit word. The below
+         * calculation may add a little extra, but that doesn't
+         * hurt.
+         */
+        copy_location = packet_buffer + sizeof(uint64_t);
+        copy_location += ((CVMX_HELPER_FIRST_MBUFF_SKIP + 7) & 0xfff8) + 6;
+
+        /*
+         * We have to copy the packet since whoever processes this
+         * packet will free it to a hardware pool. We can't use the
+         * trick of counting outstanding packets like in
+         * cvm_oct_xmit.
+         */
+        memcpy(copy_location, skb->data, skb->len);
+
+        /*
+         * Fill in some of the work queue fields. We may need to add
+         * more if the software at the other end needs them.
+         */
+        work->hw_chksum = skb->csum;
+        work->len = skb->len;
+        work->ipprt = priv->port;
+        work->qos = priv->port & 0x7;
+        work->grp = pow_send_group;
+        work->tag_type = CVMX_HELPER_INPUT_TAG_TYPE;
+        work->tag = pow_send_group;     /* FIXME */
+        /* Default to zero. Sets of zero later are commented out */
+        work->word2.u64 = 0;
+        work->word2.s.bufs = 1;
+        work->packet_ptr.u64 = 0;
+        work->packet_ptr.s.addr = cvmx_ptr_to_phys(copy_location);
+        work->packet_ptr.s.pool = CVMX_FPA_PACKET_POOL;
+        work->packet_ptr.s.size = CVMX_FPA_PACKET_POOL_SIZE;
+        work->packet_ptr.s.back = (copy_location - packet_buffer) >> 7;
+
+        if (skb->protocol == htons(ETH_P_IP)) {
+                work->word2.s.ip_offset = 14;
+#if 0
+                work->word2.s.vlan_valid = 0;   /* FIXME */
+                work->word2.s.vlan_cfi = 0;     /* FIXME */
+                work->word2.s.vlan_id = 0;      /* FIXME */
+                work->word2.s.dec_ipcomp = 0;   /* FIXME */
+#endif
+                work->word2.s.tcp_or_udp =
+                    (ip_hdr(skb)->protocol == IP_PROTOCOL_TCP)
+                    || (ip_hdr(skb)->protocol == IP_PROTOCOL_UDP);
+#if 0
+                /* FIXME */
+                work->word2.s.dec_ipsec = 0;
+                /* We only support IPv4 right now */
+                work->word2.s.is_v6 = 0;
+                /* Hardware would set to zero */
+                work->word2.s.software = 0;
+                /* No error, packet is internal */
+                work->word2.s.L4_error = 0;
+#endif
+                work->word2.s.is_frag = !((ip_hdr(skb)->frag_off == 0)
+                                          || (ip_hdr(skb)->frag_off ==
+                                              1 << 14));
+#if 0
+                /* Assume Linux is sending a good packet */
+                work->word2.s.IP_exc = 0;
+#endif
+                work->word2.s.is_bcast = (skb->pkt_type == PACKET_BROADCAST);
+                work->word2.s.is_mcast = (skb->pkt_type == PACKET_MULTICAST);
+#if 0
+                /* This is an IP packet */
+                work->word2.s.not_IP = 0;
+                /* No error, packet is internal */
+                work->word2.s.rcv_error = 0;
+                /* No error, packet is internal */
+                work->word2.s.err_code = 0;
+#endif
+
+                /*
+                 * When copying the data, include 4 bytes of the
+                 * ethernet header to align the same way hardware
+                 * does.
+                 */
+                memcpy(work->packet_data, skb->data + 10,
+                       sizeof(work->packet_data));
+        } else {
+#if 0
+                work->word2.snoip.vlan_valid = 0;       /* FIXME */
+                work->word2.snoip.vlan_cfi = 0; /* FIXME */
+                work->word2.snoip.vlan_id = 0;  /* FIXME */
+                work->word2.snoip.software = 0; /* Hardware would set to zero */
+#endif
+                work->word2.snoip.is_rarp = skb->protocol == htons(ETH_P_RARP);
+                work->word2.snoip.is_arp = skb->protocol == htons(ETH_P_ARP);
+                work->word2.snoip.is_bcast =
+                    (skb->pkt_type == PACKET_BROADCAST);
+                work->word2.snoip.is_mcast =
+                    (skb->pkt_type == PACKET_MULTICAST);
+                work->word2.snoip.not_IP = 1;   /* IP was done up above */
+#if 0
+                /* No error, packet is internal */
+                work->word2.snoip.rcv_error = 0;
+                /* No error, packet is internal */
+                work->word2.snoip.err_code = 0;
+#endif
+                memcpy(work->packet_data, skb->data, sizeof(work->packet_data));
+        }
+
+        /* Submit the packet to the POW */
+        cvmx_pow_work_submit(work, work->tag, work->tag_type, work->qos,
+                             work->grp);
+        priv->stats.tx_packets++;
+        priv->stats.tx_bytes += skb->len;
+        dev_kfree_skb(skb);
+        return 0;
+}
+
+/**
+ * Transmit a work queue entry out of the ethernet port. Both
+ * the work queue entry and the packet data can optionally be
+ * freed. The work will be freed on error as well.
+ *
+ * @dev:     Device to transmit out.
+ * @work_queue_entry:
+ *                Work queue entry to send
+ * @do_free: True if the work queue entry and packet data should be
+ *                freed. If false, neither will be freed.
+ * @qos:     Index into the queues for this port to transmit on. This
+ *                is used to implement QoS if their are multiple queues per
+ *                port. This parameter must be between 0 and the number of
+ *                queues per port minus 1. Values outside of this range will
+ *                be change to zero.
+ *
+ * Returns Zero on success, negative on failure.
+ */
+int cvm_oct_transmit_qos(struct net_device *dev, void *work_queue_entry,
+                         int do_free, int qos)
+{
+        unsigned long flags;
+        union cvmx_buf_ptr hw_buffer;
+        cvmx_pko_command_word0_t pko_command;
+        int dropped;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        cvmx_wqe_t *work = work_queue_entry;
+
+        if (!(dev->flags & IFF_UP)) {
+                DEBUGPRINT("%s: Device not up\n", dev->name);
+                if (do_free)
+                        cvm_oct_free_work(work);
+                return -1;
+        }
+
+        /* The check on CVMX_PKO_QUEUES_PER_PORT_* is designed to completely
+           remove "qos" in the event neither interface supports
+           multiple queues per port */
+        if ((CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 > 1) ||
+            (CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 > 1)) {
+                if (qos <= 0)
+                        qos = 0;
+                else if (qos >= cvmx_pko_get_num_queues(priv->port))
+                        qos = 0;
+        } else
+                qos = 0;
+
+        /* Start off assuming no drop */
+        dropped = 0;
+
+        local_irq_save(flags);
+        cvmx_pko_send_packet_prepare(priv->port, priv->queue + qos,
+                                     CVMX_PKO_LOCK_CMD_QUEUE);
+
+        /* Build the PKO buffer pointer */
+        hw_buffer.u64 = 0;
+        hw_buffer.s.addr = work->packet_ptr.s.addr;
+        hw_buffer.s.pool = CVMX_FPA_PACKET_POOL;
+        hw_buffer.s.size = CVMX_FPA_PACKET_POOL_SIZE;
+        hw_buffer.s.back = work->packet_ptr.s.back;
+
+        /* Build the PKO command */
+        pko_command.u64 = 0;
+        pko_command.s.n2 = 1;   /* Don't pollute L2 with the outgoing packet */
+        pko_command.s.dontfree = !do_free;
+        pko_command.s.segs = work->word2.s.bufs;
+        pko_command.s.total_bytes = work->len;
+
+        /* Check if we can use the hardware checksumming */
+        if (unlikely(work->word2.s.not_IP || work->word2.s.IP_exc))
+                pko_command.s.ipoffp1 = 0;
+        else
+                pko_command.s.ipoffp1 = sizeof(struct ethhdr) + 1;
+
+        /* Send the packet to the output queue */
+        if (unlikely
+            (cvmx_pko_send_packet_finish
+             (priv->port, priv->queue + qos, pko_command, hw_buffer,
+              CVMX_PKO_LOCK_CMD_QUEUE))) {
+                DEBUGPRINT("%s: Failed to send the packet\n", dev->name);
+                dropped = -1;
+        }
+        local_irq_restore(flags);
+
+        if (unlikely(dropped)) {
+                if (do_free)
+                        cvm_oct_free_work(work);
+                priv->stats.tx_dropped++;
+        } else if (do_free)
+                cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, DONT_WRITEBACK(1));
+
+        return dropped;
+}
+EXPORT_SYMBOL(cvm_oct_transmit_qos);
+
+/**
+ * This function frees all skb that are currenty queued for TX.
+ *
+ * @dev:    Device being shutdown
+ */
+void cvm_oct_tx_shutdown(struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        unsigned long flags;
+        int qos;
+
+        for (qos = 0; qos < 16; qos++) {
+                spin_lock_irqsave(&priv->tx_free_list[qos].lock, flags);
+                while (skb_queue_len(&priv->tx_free_list[qos]))
+                        dev_kfree_skb_any(__skb_dequeue
+                                          (&priv->tx_free_list[qos]));
+                spin_unlock_irqrestore(&priv->tx_free_list[qos].lock, flags);
+        }
+}
diff --git a/drivers/staging/octeon/ethernet-tx.h b/drivers/staging/octeon/ethernet-tx.h
new file mode 100644
index 000000000000..5106236fe981
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-tx.h
@@ -0,0 +1,32 @@
+/*********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+*********************************************************************/
+
+int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev);
+int cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev);
+int cvm_oct_transmit_qos(struct net_device *dev, void *work_queue_entry,
+                         int do_free, int qos);
+void cvm_oct_tx_shutdown(struct net_device *dev);
diff --git a/drivers/staging/octeon/ethernet-util.h b/drivers/staging/octeon/ethernet-util.h
new file mode 100644
index 000000000000..37b665918000
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-util.h
@@ -0,0 +1,81 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+*********************************************************************/
+
+#define DEBUGPRINT(format, ...) do { if (printk_ratelimit())            \
+                                        printk(format, ##__VA_ARGS__);  \
+                                } while (0)
+
+/**
+ * Given a packet data address, return a pointer to the
+ * beginning of the packet buffer.
+ *
+ * @packet_ptr: Packet data hardware address
+ * Returns Packet buffer pointer
+ */
+static inline void *cvm_oct_get_buffer_ptr(union cvmx_buf_ptr packet_ptr)
+{
+        return cvmx_phys_to_ptr(((packet_ptr.s.addr >> 7) - packet_ptr.s.back)
+                                << 7);
+}
+
+/**
+ * Given an IPD/PKO port number, return the logical interface it is
+ * on.
+ *
+ * @ipd_port: Port to check
+ *
+ * Returns Logical interface
+ */
+static inline int INTERFACE(int ipd_port)
+{
+        if (ipd_port < 32)      /* Interface 0 or 1 for RGMII,GMII,SPI, etc */
+                return ipd_port >> 4;
+        else if (ipd_port < 36) /* Interface 2 for NPI */
+                return 2;
+        else if (ipd_port < 40) /* Interface 3 for loopback */
+                return 3;
+        else if (ipd_port == 40)        /* Non existant interface for POW0 */
+                return 4;
+        else
+                panic("Illegal ipd_port %d passed to INTERFACE\n", ipd_port);
+}
+
+/**
+ * Given an IPD/PKO port number, return the port's index on a
+ * logical interface.
+ *
+ * @ipd_port: Port to check
+ *
+ * Returns Index into interface port list
+ */
+static inline int INDEX(int ipd_port)
+{
+        if (ipd_port < 32)
+                return ipd_port & 15;
+        else
+                return ipd_port & 3;
+}
diff --git a/drivers/staging/octeon/ethernet-xaui.c b/drivers/staging/octeon/ethernet-xaui.c
new file mode 100644
index 000000000000..f08eb32e04fc
--- /dev/null
+++ b/drivers/staging/octeon/ethernet-xaui.c
@@ -0,0 +1,127 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+#include <linux/kernel.h>
+#include <linux/netdevice.h>
+#include <linux/mii.h>
+#include <net/dst.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "ethernet-defines.h"
+#include "octeon-ethernet.h"
+#include "ethernet-common.h"
+#include "ethernet-util.h"
+
+#include "cvmx-helper.h"
+
+#include "cvmx-gmxx-defs.h"
+
+static int cvm_oct_xaui_open(struct net_device *dev)
+{
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int interface = INTERFACE(priv->port);
+        int index = INDEX(priv->port);
+        cvmx_helper_link_info_t link_info;
+
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+        gmx_cfg.s.en = 1;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+
+        if (!octeon_is_simulation()) {
+                link_info = cvmx_helper_link_get(priv->port);
+                if (!link_info.s.link_up)
+                        netif_carrier_off(dev);
+        }
+        return 0;
+}
+
+static int cvm_oct_xaui_stop(struct net_device *dev)
+{
+        union cvmx_gmxx_prtx_cfg gmx_cfg;
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        int interface = INTERFACE(priv->port);
+        int index = INDEX(priv->port);
+
+        gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
+        gmx_cfg.s.en = 0;
+        cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
+        return 0;
+}
+
+static void cvm_oct_xaui_poll(struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        cvmx_helper_link_info_t link_info;
+
+        link_info = cvmx_helper_link_get(priv->port);
+        if (link_info.u64 == priv->link_info)
+                return;
+
+        link_info = cvmx_helper_link_autoconf(priv->port);
+        priv->link_info = link_info.u64;
+
+        /* Tell Linux */
+        if (link_info.s.link_up) {
+
+                if (!netif_carrier_ok(dev))
+                        netif_carrier_on(dev);
+                if (priv->queue != -1)
+                        DEBUGPRINT
+                            ("%s: %u Mbps %s duplex, port %2d, queue %2d\n",
+                             dev->name, link_info.s.speed,
+                             (link_info.s.full_duplex) ? "Full" : "Half",
+                             priv->port, priv->queue);
+                else
+                        DEBUGPRINT("%s: %u Mbps %s duplex, port %2d, POW\n",
+                                   dev->name, link_info.s.speed,
+                                   (link_info.s.full_duplex) ? "Full" : "Half",
+                                   priv->port);
+        } else {
+                if (netif_carrier_ok(dev))
+                        netif_carrier_off(dev);
+                DEBUGPRINT("%s: Link down\n", dev->name);
+        }
+}
+
+int cvm_oct_xaui_init(struct net_device *dev)
+{
+        struct octeon_ethernet *priv = netdev_priv(dev);
+        cvm_oct_common_init(dev);
+        dev->open = cvm_oct_xaui_open;
+        dev->stop = cvm_oct_xaui_stop;
+        dev->stop(dev);
+        if (!octeon_is_simulation())
+                priv->poll = cvm_oct_xaui_poll;
+
+        return 0;
+}
+
+void cvm_oct_xaui_uninit(struct net_device *dev)
+{
+        cvm_oct_common_uninit(dev);
+}
diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c
new file mode 100644
index 000000000000..e8ef9e0b791f
--- /dev/null
+++ b/drivers/staging/octeon/ethernet.c
@@ -0,0 +1,507 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/delay.h>
+#include <linux/mii.h>
+
+#include <net/dst.h>
+
+#include <asm/octeon/octeon.h>
+
+#include "ethernet-defines.h"
+#include "ethernet-mem.h"
+#include "ethernet-rx.h"
+#include "ethernet-tx.h"
+#include "ethernet-util.h"
+#include "ethernet-proc.h"
+#include "ethernet-common.h"
+#include "octeon-ethernet.h"
+
+#include "cvmx-pip.h"
+#include "cvmx-pko.h"
+#include "cvmx-fau.h"
+#include "cvmx-ipd.h"
+#include "cvmx-helper.h"
+
+#include "cvmx-smix-defs.h"
+
+#if defined(CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS) \
+        && CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS
+int num_packet_buffers = CONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS;
+#else
+int num_packet_buffers = 1024;
+#endif
+module_param(num_packet_buffers, int, 0444);
+MODULE_PARM_DESC(num_packet_buffers, "\n"
+        "\tNumber of packet buffers to allocate and store in the\n"
+        "\tFPA. By default, 1024 packet buffers are used unless\n"
+        "\tCONFIG_CAVIUM_OCTEON_NUM_PACKET_BUFFERS is defined.");
+
+int pow_receive_group = 15;
+module_param(pow_receive_group, int, 0444);
+MODULE_PARM_DESC(pow_receive_group, "\n"
+        "\tPOW group to receive packets from. All ethernet hardware\n"
+        "\twill be configured to send incomming packets to this POW\n"
+        "\tgroup. Also any other software can submit packets to this\n"
+        "\tgroup for the kernel to process.");
+
+int pow_send_group = -1;
+module_param(pow_send_group, int, 0644);
+MODULE_PARM_DESC(pow_send_group, "\n"
+        "\tPOW group to send packets to other software on. This\n"
+        "\tcontrols the creation of the virtual device pow0.\n"
+        "\talways_use_pow also depends on this value.");
+
+int always_use_pow;
+module_param(always_use_pow, int, 0444);
+MODULE_PARM_DESC(always_use_pow, "\n"
+        "\tWhen set, always send to the pow group. This will cause\n"
+        "\tpackets sent to real ethernet devices to be sent to the\n"
+        "\tPOW group instead of the hardware. Unless some other\n"
+        "\tapplication changes the config, packets will still be\n"
+        "\treceived from the low level hardware. Use this option\n"
+        "\tto allow a CVMX app to intercept all packets from the\n"
+        "\tlinux kernel. You must specify pow_send_group along with\n"
+        "\tthis option.");
+
+char pow_send_list[128] = "";
+module_param_string(pow_send_list, pow_send_list, sizeof(pow_send_list), 0444);
+MODULE_PARM_DESC(pow_send_list, "\n"
+        "\tComma separated list of ethernet devices that should use the\n"
+        "\tPOW for transmit instead of the actual ethernet hardware. This\n"
+        "\tis a per port version of always_use_pow. always_use_pow takes\n"
+        "\tprecedence over this list. For example, setting this to\n"
+        "\t\"eth2,spi3,spi7\" would cause these three devices to transmit\n"
+        "\tusing the pow_send_group.");
+
+static int disable_core_queueing = 1;
+module_param(disable_core_queueing, int, 0444);
+MODULE_PARM_DESC(disable_core_queueing, "\n"
+        "\tWhen set the networking core's tx_queue_len is set to zero.  This\n"
+        "\tallows packets to be sent without lock contention in the packet\n"
+        "\tscheduler resulting in some cases in improved throughput.\n");
+
+/**
+ * Periodic timer to check auto negotiation
+ */
+static struct timer_list cvm_oct_poll_timer;
+
+/**
+ * Array of every ethernet device owned by this driver indexed by
+ * the ipd input port number.
+ */
+struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS];
+
+extern struct semaphore mdio_sem;
+
+/**
+ * Periodic timer tick for slow management operations
+ *
+ * @arg:    Device to check
+ */
+static void cvm_do_timer(unsigned long arg)
+{
+        static int port;
+        if (port < CVMX_PIP_NUM_INPUT_PORTS) {
+                if (cvm_oct_device[port]) {
+                        int queues_per_port;
+                        int qos;
+                        struct octeon_ethernet *priv =
+                                netdev_priv(cvm_oct_device[port]);
+                        if (priv->poll) {
+                                /* skip polling if we don't get the lock */
+                                if (!down_trylock(&mdio_sem)) {
+                                        priv->poll(cvm_oct_device[port]);
+                                        up(&mdio_sem);
+                                }
+                        }
+
+                        queues_per_port = cvmx_pko_get_num_queues(port);
+                        /* Drain any pending packets in the free list */
+                        for (qos = 0; qos < queues_per_port; qos++) {
+                                if (skb_queue_len(&priv->tx_free_list[qos])) {
+                                        spin_lock(&priv->tx_free_list[qos].
+                                                  lock);
+                                        while (skb_queue_len
+                                               (&priv->tx_free_list[qos]) >
+                                               cvmx_fau_fetch_and_add32(priv->
+                                                                        fau +
+                                                                        qos * 4,
+                                                                        0))
+                                                dev_kfree_skb(__skb_dequeue
+                                                              (&priv->
+                                                               tx_free_list
+                                                               [qos]));
+                                        spin_unlock(&priv->tx_free_list[qos].
+                                                    lock);
+                                }
+                        }
+                        cvm_oct_device[port]->get_stats(cvm_oct_device[port]);
+                }
+                port++;
+                /* Poll the next port in a 50th of a second.
+                   This spreads the polling of ports out a little bit */
+                mod_timer(&cvm_oct_poll_timer, jiffies + HZ / 50);
+        } else {
+                port = 0;
+                /* All ports have been polled. Start the next iteration through
+                   the ports in one second */
+                mod_timer(&cvm_oct_poll_timer, jiffies + HZ);
+        }
+}
+
+/**
+ * Configure common hardware for all interfaces
+ */
+static __init void cvm_oct_configure_common_hw(void)
+{
+        int r;
+        /* Setup the FPA */
+        cvmx_fpa_enable();
+        cvm_oct_mem_fill_fpa(CVMX_FPA_PACKET_POOL, CVMX_FPA_PACKET_POOL_SIZE,
+                             num_packet_buffers);
+        cvm_oct_mem_fill_fpa(CVMX_FPA_WQE_POOL, CVMX_FPA_WQE_POOL_SIZE,
+                             num_packet_buffers);
+        if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL)
+                cvm_oct_mem_fill_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL,
+                                     CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128);
+
+        if (USE_RED)
+                cvmx_helper_setup_red(num_packet_buffers / 4,
+                                      num_packet_buffers / 8);
+
+        /* Enable the MII interface */
+        if (!octeon_is_simulation())
+                cvmx_write_csr(CVMX_SMIX_EN(0), 1);
+
+        /* Register an IRQ hander for to receive POW interrupts */
+        r = request_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group,
+                        cvm_oct_do_interrupt, IRQF_SHARED, "Ethernet",
+                        cvm_oct_device);
+
+#if defined(CONFIG_SMP) && 0
+        if (USE_MULTICORE_RECEIVE) {
+                irq_set_affinity(OCTEON_IRQ_WORKQ0 + pow_receive_group,
+                                 cpu_online_mask);
+        }
+#endif
+}
+
+/**
+ * Free a work queue entry received in a intercept callback.
+ *
+ * @work_queue_entry:
+ *               Work queue entry to free
+ * Returns Zero on success, Negative on failure.
+ */
+int cvm_oct_free_work(void *work_queue_entry)
+{
+        cvmx_wqe_t *work = work_queue_entry;
+
+        int segments = work->word2.s.bufs;
+        union cvmx_buf_ptr segment_ptr = work->packet_ptr;
+
+        while (segments--) {
+                union cvmx_buf_ptr next_ptr = *(union cvmx_buf_ptr *)
+                        cvmx_phys_to_ptr(segment_ptr.s.addr - 8);
+                if (unlikely(!segment_ptr.s.i))
+                        cvmx_fpa_free(cvm_oct_get_buffer_ptr(segment_ptr),
+                                      segment_ptr.s.pool,
+                                      DONT_WRITEBACK(CVMX_FPA_PACKET_POOL_SIZE /
+                                                     128));
+                segment_ptr = next_ptr;
+        }
+        cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, DONT_WRITEBACK(1));
+
+        return 0;
+}
+EXPORT_SYMBOL(cvm_oct_free_work);
+
+/**
+ * Module/ driver initialization. Creates the linux network
+ * devices.
+ *
+ * Returns Zero on success
+ */
+static int __init cvm_oct_init_module(void)
+{
+        int num_interfaces;
+        int interface;
+        int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;
+        int qos;
+
+        pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION);
+
+        cvm_oct_proc_initialize();
+        cvm_oct_rx_initialize();
+        cvm_oct_configure_common_hw();
+
+        cvmx_helper_initialize_packet_io_global();
+
+        /* Change the input group for all ports before input is enabled */
+        num_interfaces = cvmx_helper_get_number_of_interfaces();
+        for (interface = 0; interface < num_interfaces; interface++) {
+                int num_ports = cvmx_helper_ports_on_interface(interface);
+                int port;
+
+                for (port = cvmx_helper_get_ipd_port(interface, 0);
+                     port < cvmx_helper_get_ipd_port(interface, num_ports);
+                     port++) {
+                        union cvmx_pip_prt_tagx pip_prt_tagx;
+                        pip_prt_tagx.u64 =
+                            cvmx_read_csr(CVMX_PIP_PRT_TAGX(port));
+                        pip_prt_tagx.s.grp = pow_receive_group;
+                        cvmx_write_csr(CVMX_PIP_PRT_TAGX(port),
+                                       pip_prt_tagx.u64);
+                }
+        }
+
+        cvmx_helper_ipd_and_packet_input_enable();
+
+        memset(cvm_oct_device, 0, sizeof(cvm_oct_device));
+
+        /*
+         * Initialize the FAU used for counting packet buffers that
+         * need to be freed.
+         */
+        cvmx_fau_atomic_write32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0);
+
+        if ((pow_send_group != -1)) {
+                struct net_device *dev;
+                pr_info("\tConfiguring device for POW only access\n");
+                dev = alloc_etherdev(sizeof(struct octeon_ethernet));
+                if (dev) {
+                        /* Initialize the device private structure. */
+                        struct octeon_ethernet *priv = netdev_priv(dev);
+                        memset(priv, 0, sizeof(struct octeon_ethernet));
+
+                        dev->init = cvm_oct_common_init;
+                        priv->imode = CVMX_HELPER_INTERFACE_MODE_DISABLED;
+                        priv->port = CVMX_PIP_NUM_INPUT_PORTS;
+                        priv->queue = -1;
+                        strcpy(dev->name, "pow%d");
+                        for (qos = 0; qos < 16; qos++)
+                                skb_queue_head_init(&priv->tx_free_list[qos]);
+
+                        if (register_netdev(dev) < 0) {
+                                pr_err("Failed to register ethernet "
+                                         "device for POW\n");
+                                kfree(dev);
+                        } else {
+                                cvm_oct_device[CVMX_PIP_NUM_INPUT_PORTS] = dev;
+                                pr_info("%s: POW send group %d, receive "
+                                        "group %d\n",
+                                     dev->name, pow_send_group,
+                                     pow_receive_group);
+                        }
+                } else {
+                        pr_err("Failed to allocate ethernet device "
+                                 "for POW\n");
+                }
+        }
+
+        num_interfaces = cvmx_helper_get_number_of_interfaces();
+        for (interface = 0; interface < num_interfaces; interface++) {
+                cvmx_helper_interface_mode_t imode =
+                    cvmx_helper_interface_get_mode(interface);
+                int num_ports = cvmx_helper_ports_on_interface(interface);
+                int port;
+
+                for (port = cvmx_helper_get_ipd_port(interface, 0);
+                     port < cvmx_helper_get_ipd_port(interface, num_ports);
+                     port++) {
+                        struct octeon_ethernet *priv;
+                        struct net_device *dev =
+                            alloc_etherdev(sizeof(struct octeon_ethernet));
+                        if (!dev) {
+                                pr_err("Failed to allocate ethernet device "
+                                         "for port %d\n", port);
+                                continue;
+                        }
+                        if (disable_core_queueing)
+                                dev->tx_queue_len = 0;
+
+                        /* Initialize the device private structure. */
+                        priv = netdev_priv(dev);
+                        memset(priv, 0, sizeof(struct octeon_ethernet));
+
+                        priv->imode = imode;
+                        priv->port = port;
+                        priv->queue = cvmx_pko_get_base_queue(priv->port);
+                        priv->fau = fau - cvmx_pko_get_num_queues(port) * 4;
+                        for (qos = 0; qos < 16; qos++)
+                                skb_queue_head_init(&priv->tx_free_list[qos]);
+                        for (qos = 0; qos < cvmx_pko_get_num_queues(port);
+                             qos++)
+                                cvmx_fau_atomic_write32(priv->fau + qos * 4, 0);
+
+                        switch (priv->imode) {
+
+                        /* These types don't support ports to IPD/PKO */
+                        case CVMX_HELPER_INTERFACE_MODE_DISABLED:
+                        case CVMX_HELPER_INTERFACE_MODE_PCIE:
+                        case CVMX_HELPER_INTERFACE_MODE_PICMG:
+                                break;
+
+                        case CVMX_HELPER_INTERFACE_MODE_NPI:
+                                dev->init = cvm_oct_common_init;
+                                dev->uninit = cvm_oct_common_uninit;
+                                strcpy(dev->name, "npi%d");
+                                break;
+
+                        case CVMX_HELPER_INTERFACE_MODE_XAUI:
+                                dev->init = cvm_oct_xaui_init;
+                                dev->uninit = cvm_oct_xaui_uninit;
+                                strcpy(dev->name, "xaui%d");
+                                break;
+
+                        case CVMX_HELPER_INTERFACE_MODE_LOOP:
+                                dev->init = cvm_oct_common_init;
+                                dev->uninit = cvm_oct_common_uninit;
+                                strcpy(dev->name, "loop%d");
+                                break;
+
+                        case CVMX_HELPER_INTERFACE_MODE_SGMII:
+                                dev->init = cvm_oct_sgmii_init;
+                                dev->uninit = cvm_oct_sgmii_uninit;
+                                strcpy(dev->name, "eth%d");
+                                break;
+
+                        case CVMX_HELPER_INTERFACE_MODE_SPI:
+                                dev->init = cvm_oct_spi_init;
+                                dev->uninit = cvm_oct_spi_uninit;
+                                strcpy(dev->name, "spi%d");
+                                break;
+
+                        case CVMX_HELPER_INTERFACE_MODE_RGMII:
+                        case CVMX_HELPER_INTERFACE_MODE_GMII:
+                                dev->init = cvm_oct_rgmii_init;
+                                dev->uninit = cvm_oct_rgmii_uninit;
+                                strcpy(dev->name, "eth%d");
+                                break;
+                        }
+
+                        if (!dev->init) {
+                                kfree(dev);
+                        } else if (register_netdev(dev) < 0) {
+                                pr_err("Failed to register ethernet device "
+                                         "for interface %d, port %d\n",
+                                         interface, priv->port);
+                                kfree(dev);
+                        } else {
+                                cvm_oct_device[priv->port] = dev;
+                                fau -=
+                                    cvmx_pko_get_num_queues(priv->port) *
+                                    sizeof(uint32_t);
+                        }
+                }
+        }
+
+        if (INTERRUPT_LIMIT) {
+                /*
+                 * Set the POW timer rate to give an interrupt at most
+                 * INTERRUPT_LIMIT times per second.
+                 */
+                cvmx_write_csr(CVMX_POW_WQ_INT_PC,
+                               octeon_bootinfo->eclock_hz / (INTERRUPT_LIMIT *
+                                                             16 * 256) << 8);
+
+                /*
+                 * Enable POW timer interrupt. It will count when
+                 * there are packets available.
+                 */
+                cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group),
+                               0x1ful << 24);
+        } else {
+                /* Enable POW interrupt when our port has at least one packet */
+                cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0x1001);
+        }
+
+        /* Enable the poll timer for checking RGMII status */
+        init_timer(&cvm_oct_poll_timer);
+        cvm_oct_poll_timer.data = 0;
+        cvm_oct_poll_timer.function = cvm_do_timer;
+        mod_timer(&cvm_oct_poll_timer, jiffies + HZ);
+
+        return 0;
+}
+
+/**
+ * Module / driver shutdown
+ *
+ * Returns Zero on success
+ */
+static void __exit cvm_oct_cleanup_module(void)
+{
+        int port;
+
+        /* Disable POW interrupt */
+        cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0);
+
+        cvmx_ipd_disable();
+
+        /* Free the interrupt handler */
+        free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device);
+
+        del_timer(&cvm_oct_poll_timer);
+        cvm_oct_rx_shutdown();
+        cvmx_pko_disable();
+
+        /* Free the ethernet devices */
+        for (port = 0; port < TOTAL_NUMBER_OF_PORTS; port++) {
+                if (cvm_oct_device[port]) {
+                        cvm_oct_tx_shutdown(cvm_oct_device[port]);
+                        unregister_netdev(cvm_oct_device[port]);
+                        kfree(cvm_oct_device[port]);
+                        cvm_oct_device[port] = NULL;
+                }
+        }
+
+        cvmx_pko_shutdown();
+        cvm_oct_proc_shutdown();
+
+        cvmx_ipd_free_ptr();
+
+        /* Free the HW pools */
+        cvm_oct_mem_empty_fpa(CVMX_FPA_PACKET_POOL, CVMX_FPA_PACKET_POOL_SIZE,
+                              num_packet_buffers);
+        cvm_oct_mem_empty_fpa(CVMX_FPA_WQE_POOL, CVMX_FPA_WQE_POOL_SIZE,
+                              num_packet_buffers);
+        if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL)
+                cvm_oct_mem_empty_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL,
+                                      CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128);
+}
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
+MODULE_DESCRIPTION("Cavium Networks Octeon ethernet driver.");
+module_init(cvm_oct_init_module);
+module_exit(cvm_oct_cleanup_module);
diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h
new file mode 100644
index 000000000000..b3199076ef5e
--- /dev/null
+++ b/drivers/staging/octeon/octeon-ethernet.h
@@ -0,0 +1,127 @@
+/**********************************************************************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2007 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+**********************************************************************/
+
+/*
+ * External interface for the Cavium Octeon ethernet driver.
+ */
+#ifndef OCTEON_ETHERNET_H
+#define OCTEON_ETHERNET_H
+
+/**
+ * This is the definition of the Ethernet driver's private
+ * driver state stored in netdev_priv(dev).
+ */
+struct octeon_ethernet {
+        /* PKO hardware output port */
+        int port;
+        /* PKO hardware queue for the port */
+        int queue;
+        /* Hardware fetch and add to count outstanding tx buffers */
+        int fau;
+        /*
+         * Type of port. This is one of the enums in
+         * cvmx_helper_interface_mode_t
+         */
+        int imode;
+        /* List of outstanding tx buffers per queue */
+        struct sk_buff_head tx_free_list[16];
+        /* Device statistics */
+        struct net_device_stats stats
+;       /* Generic MII info structure */
+        struct mii_if_info mii_info;
+        /* Last negotiated link state */
+        uint64_t link_info;
+        /* Called periodically to check link status */
+        void (*poll) (struct net_device *dev);
+};
+
+/**
+ * Free a work queue entry received in a intercept callback.
+ *
+ * @work_queue_entry:
+ *               Work queue entry to free
+ * Returns Zero on success, Negative on failure.
+ */
+int cvm_oct_free_work(void *work_queue_entry);
+
+/**
+ * Transmit a work queue entry out of the ethernet port. Both
+ * the work queue entry and the packet data can optionally be
+ * freed. The work will be freed on error as well.
+ *
+ * @dev:     Device to transmit out.
+ * @work_queue_entry:
+ *                Work queue entry to send
+ * @do_free: True if the work queue entry and packet data should be
+ *                freed. If false, neither will be freed.
+ * @qos:     Index into the queues for this port to transmit on. This
+ *                is used to implement QoS if their are multiple queues per
+ *                port. This parameter must be between 0 and the number of
+ *                queues per port minus 1. Values outside of this range will
+ *                be change to zero.
+ *
+ * Returns Zero on success, negative on failure.
+ */
+int cvm_oct_transmit_qos(struct net_device *dev, void *work_queue_entry,
+                         int do_free, int qos);
+
+/**
+ * Transmit a work queue entry out of the ethernet port. Both
+ * the work queue entry and the packet data can optionally be
+ * freed. The work will be freed on error as well. This simply
+ * wraps cvmx_oct_transmit_qos() for backwards compatability.
+ *
+ * @dev:     Device to transmit out.
+ * @work_queue_entry:
+ *                Work queue entry to send
+ * @do_free: True if the work queue entry and packet data should be
+ *                freed. If false, neither will be freed.
+ *
+ * Returns Zero on success, negative on failure.
+ */
+static inline int cvm_oct_transmit(struct net_device *dev,
+                                   void *work_queue_entry, int do_free)
+{
+        return cvm_oct_transmit_qos(dev, work_queue_entry, do_free, 0);
+}
+
+extern int cvm_oct_rgmii_init(struct net_device *dev);
+extern void cvm_oct_rgmii_uninit(struct net_device *dev);
+extern int cvm_oct_sgmii_init(struct net_device *dev);
+extern void cvm_oct_sgmii_uninit(struct net_device *dev);
+extern int cvm_oct_spi_init(struct net_device *dev);
+extern void cvm_oct_spi_uninit(struct net_device *dev);
+extern int cvm_oct_xaui_init(struct net_device *dev);
+extern void cvm_oct_xaui_uninit(struct net_device *dev);
+
+extern int always_use_pow;
+extern int pow_send_group;
+extern int pow_receive_group;
+extern char pow_send_list[];
+extern struct net_device *cvm_oct_device[];
+
+#endif
diff --git a/drivers/staging/uc2322/aten2011.c b/drivers/staging/uc2322/aten2011.c
index 9c62f787cc9c..39d0926d1a90 100644
--- a/drivers/staging/uc2322/aten2011.c
+++ b/drivers/staging/uc2322/aten2011.c
@@ -2336,7 +2336,7 @@ static int ATEN2011_startup(struct usb_serial *serial)
         return 0;
 }
 
-static void ATEN2011_shutdown(struct usb_serial *serial)
+static void ATEN2011_release(struct usb_serial *serial)
 {
         int i;
         struct ATENINTL_port *ATEN2011_port;
@@ -2382,7 +2382,7 @@ static struct usb_serial_driver aten_serial_driver = {
         .tiocmget =             ATEN2011_tiocmget,
         .tiocmset =             ATEN2011_tiocmset,
         .attach =               ATEN2011_startup,
-        .shutdown =             ATEN2011_shutdown,
+        .release =              ATEN2011_release,
         .read_bulk_callback =   ATEN2011_bulk_in_callback,
         .read_int_callback =    ATEN2011_interrupt_callback,
 };
diff --git a/drivers/thermal/thermal_sys.c b/drivers/thermal/thermal_sys.c
index 5e38ba10a3a9..0a69672097a8 100644
--- a/drivers/thermal/thermal_sys.c
+++ b/drivers/thermal/thermal_sys.c
@@ -417,7 +417,7 @@ static LIST_HEAD(thermal_hwmon_list);
 static ssize_t
 name_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
-        struct thermal_hwmon_device *hwmon = dev->driver_data;
+        struct thermal_hwmon_device *hwmon = dev_get_drvdata(dev);
         return sprintf(buf, "%s\n", hwmon->type);
 }
 static DEVICE_ATTR(name, 0444, name_show, NULL);
@@ -488,7 +488,7 @@ thermal_add_hwmon_sysfs(struct thermal_zone_device *tz)
                 result = PTR_ERR(hwmon->device);
                 goto free_mem;
         }
-        hwmon->device->driver_data = hwmon;
+        dev_set_drvdata(hwmon->device, hwmon);
         result = device_create_file(hwmon->device, &dev_attr_name);
         if (result)
                 goto unregister_hwmon_device;
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 5eee3f82be5d..dcd49f1e96d0 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -64,6 +64,7 @@ config USB_ARCH_HAS_EHCI
 config USB
         tristate "Support for Host-side USB"
         depends on USB_ARCH_HAS_HCD
+        select NLS  # for UTF-8 strings
         ---help---
           Universal Serial Bus (USB) is a specification for a serial bus
           subsystem which offers higher speeds and more features than the
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 0a3dc5ece634..19cb7d5480d7 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_USB_ISP116X_HCD)	+= host/
 obj-$(CONFIG_USB_OHCI_HCD)      += host/
 obj-$(CONFIG_USB_UHCI_HCD)      += host/
 obj-$(CONFIG_USB_FHCI_HCD)      += host/
+obj-$(CONFIG_USB_XHCI_HCD)      += host/
 obj-$(CONFIG_USB_SL811_HCD)     += host/
 obj-$(CONFIG_USB_U132_HCD)      += host/
 obj-$(CONFIG_USB_R8A66597_HCD)  += host/
diff --git a/drivers/usb/atm/ueagle-atm.c b/drivers/usb/atm/ueagle-atm.c
index 9cf9ff69e3e3..d171b563e94c 100644
--- a/drivers/usb/atm/ueagle-atm.c
+++ b/drivers/usb/atm/ueagle-atm.c
@@ -306,6 +306,7 @@ enum {
 #define FW_GET_BYTE(p)  *((__u8 *) (p))
 
 #define FW_DIR "ueagle-atm/"
+#define UEA_FW_NAME_MAX 30
 #define NB_MODEM 4
 
 #define BULK_TIMEOUT 300
@@ -1564,9 +1565,9 @@ static void cmvs_file_name(struct uea_softc *sc, char *const cmv_name, int ver)
                 file = cmv_file[sc->modem_index];
 
         strcpy(cmv_name, FW_DIR);
-        strlcat(cmv_name, file, FIRMWARE_NAME_MAX);
+        strlcat(cmv_name, file, UEA_FW_NAME_MAX);
         if (ver == 2)
-                strlcat(cmv_name, ".v2", FIRMWARE_NAME_MAX);
+                strlcat(cmv_name, ".v2", UEA_FW_NAME_MAX);
 }
 
 static int request_cmvs_old(struct uea_softc *sc,
@@ -1574,7 +1575,7 @@ static int request_cmvs_old(struct uea_softc *sc,
 {
         int ret, size;
         u8 *data;
-        char cmv_name[FIRMWARE_NAME_MAX]; /* 30 bytes stack variable */
+        char cmv_name[UEA_FW_NAME_MAX]; /* 30 bytes stack variable */
 
         cmvs_file_name(sc, cmv_name, 1);
         ret = request_firmware(fw, cmv_name, &sc->usb_dev->dev);
@@ -1608,7 +1609,7 @@ static int request_cmvs(struct uea_softc *sc,
         int ret, size;
         u32 crc;
         u8 *data;
-        char cmv_name[FIRMWARE_NAME_MAX]; /* 30 bytes stack variable */
+        char cmv_name[UEA_FW_NAME_MAX]; /* 30 bytes stack variable */
 
         cmvs_file_name(sc, cmv_name, 2);
         ret = request_firmware(fw, cmv_name, &sc->usb_dev->dev);
diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index ddeb69192537..38bfdb0f6660 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -937,9 +937,9 @@ static int acm_probe(struct usb_interface *intf,
         int buflen = intf->altsetting->extralen;
         struct usb_interface *control_interface;
         struct usb_interface *data_interface;
-        struct usb_endpoint_descriptor *epctrl;
-        struct usb_endpoint_descriptor *epread;
-        struct usb_endpoint_descriptor *epwrite;
+        struct usb_endpoint_descriptor *epctrl = NULL;
+        struct usb_endpoint_descriptor *epread = NULL;
+        struct usb_endpoint_descriptor *epwrite = NULL;
         struct usb_device *usb_dev = interface_to_usbdev(intf);
         struct acm *acm;
         int minor;
@@ -952,6 +952,7 @@ static int acm_probe(struct usb_interface *intf,
         unsigned long quirks;
         int num_rx_buf;
         int i;
+        int combined_interfaces = 0;
 
         /* normal quirks */
         quirks = (unsigned long)id->driver_info;
@@ -1033,9 +1034,15 @@ next_desc:
                         data_interface = usb_ifnum_to_if(usb_dev, (data_interface_num = call_interface_num));
                         control_interface = intf;
                 } else {
-                        dev_dbg(&intf->dev,
-                                        "No union descriptor, giving up\n");
-                        return -ENODEV;
+                        if (intf->cur_altsetting->desc.bNumEndpoints != 3) {
+                                dev_dbg(&intf->dev,"No union descriptor, giving up\n");
+                                return -ENODEV;
+                        } else {
+                                dev_warn(&intf->dev,"No union descriptor, testing for castrated device\n");
+                                combined_interfaces = 1;
+                                control_interface = data_interface = intf;
+                                goto look_for_collapsed_interface;
+                        }
                 }
         } else {
                 control_interface = usb_ifnum_to_if(usb_dev, union_header->bMasterInterface0);
@@ -1049,6 +1056,36 @@ next_desc:
         if (data_interface_num != call_interface_num)
                 dev_dbg(&intf->dev, "Separate call control interface. That is not fully supported.\n");
 
+        if (control_interface == data_interface) {
+                /* some broken devices designed for windows work this way */
+                dev_warn(&intf->dev,"Control and data interfaces are not separated!\n");
+                combined_interfaces = 1;
+                /* a popular other OS doesn't use it */
+                quirks |= NO_CAP_LINE;
+                if (data_interface->cur_altsetting->desc.bNumEndpoints != 3) {
+                        dev_err(&intf->dev, "This needs exactly 3 endpoints\n");
+                        return -EINVAL;
+                }
+look_for_collapsed_interface:
+                for (i = 0; i < 3; i++) {
+                        struct usb_endpoint_descriptor *ep;
+                        ep = &data_interface->cur_altsetting->endpoint[i].desc;
+
+                        if (usb_endpoint_is_int_in(ep))
+                                epctrl = ep;
+                        else if (usb_endpoint_is_bulk_out(ep))
+                                epwrite = ep;
+                        else if (usb_endpoint_is_bulk_in(ep))
+                                epread = ep;
+                        else
+                                return -EINVAL;
+                }
+                if (!epctrl || !epread || !epwrite)
+                        return -ENODEV;
+                else
+                        goto made_compressed_probe;
+        }
+
 skip_normal_probe:
 
         /*workaround for switched interfaces */
@@ -1068,10 +1105,11 @@ skip_normal_probe:
         }
 
         /* Accept probe requests only for the control interface */
-        if (intf != control_interface)
+        if (!combined_interfaces && intf != control_interface)
                 return -ENODEV;
 
-        if (usb_interface_claimed(data_interface)) { /* valid in this context */
+        if (!combined_interfaces && usb_interface_claimed(data_interface)) {
+                /* valid in this context */
                 dev_dbg(&intf->dev, "The data interface isn't available\n");
                 return -EBUSY;
         }
@@ -1095,6 +1133,7 @@ skip_normal_probe:
                 epread = epwrite;
                 epwrite = t;
         }
+made_compressed_probe:
         dbg("interfaces are valid");
         for (minor = 0; minor < ACM_TTY_MINORS && acm_table[minor]; minor++);
 
@@ -1112,12 +1151,15 @@ skip_normal_probe:
         ctrlsize = le16_to_cpu(epctrl->wMaxPacketSize);
         readsize = le16_to_cpu(epread->wMaxPacketSize) *
                                 (quirks == SINGLE_RX_URB ? 1 : 2);
+        acm->combined_interfaces = combined_interfaces;
         acm->writesize = le16_to_cpu(epwrite->wMaxPacketSize) * 20;
         acm->control = control_interface;
         acm->data = data_interface;
         acm->minor = minor;
         acm->dev = usb_dev;
         acm->ctrl_caps = ac_management_function;
+        if (quirks & NO_CAP_LINE)
+                acm->ctrl_caps &= ~USB_CDC_CAP_LINE;
         acm->ctrlsize = ctrlsize;
         acm->readsize = readsize;
         acm->rx_buflimit = num_rx_buf;
@@ -1223,9 +1265,10 @@ skip_normal_probe:
 
 skip_countries:
         usb_fill_int_urb(acm->ctrlurb, usb_dev,
-                        usb_rcvintpipe(usb_dev, epctrl->bEndpointAddress),
-                        acm->ctrl_buffer, ctrlsize, acm_ctrl_irq, acm,
-                        epctrl->bInterval);
+                         usb_rcvintpipe(usb_dev, epctrl->bEndpointAddress),
+                         acm->ctrl_buffer, ctrlsize, acm_ctrl_irq, acm,
+                         /* works around buggy devices */
+                         epctrl->bInterval ? epctrl->bInterval : 0xff);
         acm->ctrlurb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
         acm->ctrlurb->transfer_dma = acm->ctrl_dma;
 
@@ -1312,7 +1355,8 @@ static void acm_disconnect(struct usb_interface *intf)
                                                                 acm->ctrl_dma);
         acm_read_buffers_free(acm);
 
-        usb_driver_release_interface(&acm_driver, intf == acm->control ?
+        if (!acm->combined_interfaces)
+                usb_driver_release_interface(&acm_driver, intf == acm->control ?
                                         acm->data : acm->control);
 
         if (acm->port.count == 0) {
@@ -1451,6 +1495,9 @@ static struct usb_device_id acm_ids[] = {
                                            Maybe we should define a new
                                            quirk for this. */
         },
+        { USB_DEVICE(0x1bbb, 0x0003), /* Alcatel OT-I650 */
+        .driver_info = NO_UNION_NORMAL, /* reports zero length descriptor */
+        },
 
         /* control interfaces with various AT-command sets */
         { USB_INTERFACE_INFO(USB_CLASS_COMM, USB_CDC_SUBCLASS_ACM,
diff --git a/drivers/usb/class/cdc-acm.h b/drivers/usb/class/cdc-acm.h
index 4c3856420add..1602324808ba 100644
--- a/drivers/usb/class/cdc-acm.h
+++ b/drivers/usb/class/cdc-acm.h
@@ -125,6 +125,7 @@ struct acm {
         unsigned char clocal;                           /* termios CLOCAL */
         unsigned int ctrl_caps;                         /* control capabilities from the class specific header */
         unsigned int susp_count;                        /* number of suspended interfaces */
+        int combined_interfaces:1;                      /* control and data collapsed */
         struct acm_wb *delayed_wb;                      /* write queued for a device about to be woken */
 };
 
@@ -133,3 +134,4 @@ struct acm {
 /* constants describing various quirks and errors */
 #define NO_UNION_NORMAL                 1
 #define SINGLE_RX_URB                   2
+#define NO_CAP_LINE                     4
diff --git a/drivers/usb/class/usblp.c b/drivers/usb/class/usblp.c
index d2747a49b974..26c09f0257db 100644
--- a/drivers/usb/class/usblp.c
+++ b/drivers/usb/class/usblp.c
@@ -1057,8 +1057,14 @@ static const struct file_operations usblp_fops = {
         .release =      usblp_release,
 };
 
+static char *usblp_nodename(struct device *dev)
+{
+        return kasprintf(GFP_KERNEL, "usb/%s", dev_name(dev));
+}
+
 static struct usb_class_driver usblp_class = {
         .name =         "lp%d",
+        .nodename =     usblp_nodename,
         .fops =         &usblp_fops,
         .minor_base =   USBLP_MINOR_BASE,
 };
diff --git a/drivers/usb/class/usbtmc.c b/drivers/usb/class/usbtmc.c
index c40a9b284cc9..3703789d0d2a 100644
--- a/drivers/usb/class/usbtmc.c
+++ b/drivers/usb/class/usbtmc.c
@@ -927,21 +927,27 @@ static long usbtmc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
         switch (cmd) {
         case USBTMC_IOCTL_CLEAR_OUT_HALT:
                 retval = usbtmc_ioctl_clear_out_halt(data);
+                break;
 
         case USBTMC_IOCTL_CLEAR_IN_HALT:
                 retval = usbtmc_ioctl_clear_in_halt(data);
+                break;
 
         case USBTMC_IOCTL_INDICATOR_PULSE:
                 retval = usbtmc_ioctl_indicator_pulse(data);
+                break;
 
         case USBTMC_IOCTL_CLEAR:
                 retval = usbtmc_ioctl_clear(data);
+                break;
 
         case USBTMC_IOCTL_ABORT_BULK_OUT:
                 retval = usbtmc_ioctl_abort_bulk_out(data);
+                break;
 
         case USBTMC_IOCTL_ABORT_BULK_IN:
                 retval = usbtmc_ioctl_abort_bulk_in(data);
+                break;
         }
 
         mutex_unlock(&data->io_mutex);
diff --git a/drivers/usb/core/Kconfig b/drivers/usb/core/Kconfig
index e1759d17ac5d..69280c35b5cb 100644
--- a/drivers/usb/core/Kconfig
+++ b/drivers/usb/core/Kconfig
@@ -28,7 +28,7 @@ comment "Miscellaneous USB options"
         depends on USB
 
 config USB_DEVICEFS
-        bool "USB device filesystem"
+        bool "USB device filesystem (DEPRECATED)" if EMBEDDED
         depends on USB
         ---help---
           If you say Y here (and to "/proc file system support" in the "File
@@ -46,11 +46,15 @@ config USB_DEVICEFS
           For the format of the various /proc/bus/usb/ files, please read
           <file:Documentation/usb/proc_usb_info.txt>.
 
-          Usbfs files can't handle Access Control Lists (ACL), which are the
-          default way to grant access to USB devices for untrusted users of a
-          desktop system. The usbfs functionality is replaced by real
-          device-nodes managed by udev. These nodes live in /dev/bus/usb and
-          are used by libusb.
+          Modern Linux systems do not use this.
+
+          Usbfs entries are files and not character devices; usbfs can't
+          handle Access Control Lists (ACL) which are the default way to
+          grant access to USB devices for untrusted users of a desktop
+          system.
+
+          The usbfs functionality is replaced by real device-nodes managed by
+          udev.  These nodes lived in /dev/bus/usb and are used by libusb.
 
 config USB_DEVICE_CLASS
         bool "USB device class-devices (DEPRECATED)"
diff --git a/drivers/usb/core/Makefile b/drivers/usb/core/Makefile
index b6078706fb93..ec16e6029905 100644
--- a/drivers/usb/core/Makefile
+++ b/drivers/usb/core/Makefile
@@ -4,14 +4,14 @@
 
 usbcore-objs    := usb.o hub.o hcd.o urb.o message.o driver.o \
                         config.o file.o buffer.o sysfs.o endpoint.o \
-                        devio.o notify.o generic.o quirks.o
+                        devio.o notify.o generic.o quirks.o devices.o
 
 ifeq ($(CONFIG_PCI),y)
         usbcore-objs    += hcd-pci.o
 endif
 
 ifeq ($(CONFIG_USB_DEVICEFS),y)
-        usbcore-objs    += inode.o devices.o
+        usbcore-objs    += inode.o
 endif
 
 obj-$(CONFIG_USB)       += usbcore.o
diff --git a/drivers/usb/core/config.c b/drivers/usb/core/config.c
index 568244c99bdc..24dfb33f90cb 100644
--- a/drivers/usb/core/config.c
+++ b/drivers/usb/core/config.c
@@ -19,6 +19,32 @@ static inline const char *plural(int n)
         return (n == 1 ? "" : "s");
 }
 
+/* FIXME: this is a kludge */
+static int find_next_descriptor_more(unsigned char *buffer, int size,
+    int dt1, int dt2, int dt3, int *num_skipped)
+{
+        struct usb_descriptor_header *h;
+        int n = 0;
+        unsigned char *buffer0 = buffer;
+
+        /* Find the next descriptor of type dt1 or dt2 or dt3 */
+        while (size > 0) {
+                h = (struct usb_descriptor_header *) buffer;
+                if (h->bDescriptorType == dt1 || h->bDescriptorType == dt2 ||
+                                h->bDescriptorType == dt3)
+                        break;
+                buffer += h->bLength;
+                size -= h->bLength;
+                ++n;
+        }
+
+        /* Store the number of descriptors skipped and return the
+         * number of bytes skipped */
+        if (num_skipped)
+                *num_skipped = n;
+        return buffer - buffer0;
+}
+
 static int find_next_descriptor(unsigned char *buffer, int size,
     int dt1, int dt2, int *num_skipped)
 {
@@ -43,6 +69,129 @@ static int find_next_descriptor(unsigned char *buffer, int size,
         return buffer - buffer0;
 }
 
+static int usb_parse_ss_endpoint_companion(struct device *ddev, int cfgno,
+                int inum, int asnum, struct usb_host_endpoint *ep,
+                int num_ep, unsigned char *buffer, int size)
+{
+        unsigned char *buffer_start = buffer;
+        struct usb_ss_ep_comp_descriptor        *desc;
+        int retval;
+        int num_skipped;
+        int max_tx;
+        int i;
+
+        /* Allocate space for the SS endpoint companion descriptor */
+        ep->ss_ep_comp = kzalloc(sizeof(struct usb_host_ss_ep_comp),
+                        GFP_KERNEL);
+        if (!ep->ss_ep_comp)
+                return -ENOMEM;
+        desc = (struct usb_ss_ep_comp_descriptor *) buffer;
+        if (desc->bDescriptorType != USB_DT_SS_ENDPOINT_COMP) {
+                dev_warn(ddev, "No SuperSpeed endpoint companion for config %d "
+                                " interface %d altsetting %d ep %d: "
+                                "using minimum values\n",
+                                cfgno, inum, asnum, ep->desc.bEndpointAddress);
+                ep->ss_ep_comp->desc.bLength = USB_DT_SS_EP_COMP_SIZE;
+                ep->ss_ep_comp->desc.bDescriptorType = USB_DT_SS_ENDPOINT_COMP;
+                ep->ss_ep_comp->desc.bMaxBurst = 0;
+                /*
+                 * Leave bmAttributes as zero, which will mean no streams for
+                 * bulk, and isoc won't support multiple bursts of packets.
+                 * With bursts of only one packet, and a Mult of 1, the max
+                 * amount of data moved per endpoint service interval is one
+                 * packet.
+                 */
+                if (usb_endpoint_xfer_isoc(&ep->desc) ||
+                                usb_endpoint_xfer_int(&ep->desc))
+                        ep->ss_ep_comp->desc.wBytesPerInterval =
+                                ep->desc.wMaxPacketSize;
+                /*
+                 * The next descriptor is for an Endpoint or Interface,
+                 * no extra descriptors to copy into the companion structure,
+                 * and we didn't eat up any of the buffer.
+                 */
+                retval = 0;
+                goto valid;
+        }
+        memcpy(&ep->ss_ep_comp->desc, desc, USB_DT_SS_EP_COMP_SIZE);
+        desc = &ep->ss_ep_comp->desc;
+        buffer += desc->bLength;
+        size -= desc->bLength;
+
+        /* Eat up the other descriptors we don't care about */
+        ep->ss_ep_comp->extra = buffer;
+        i = find_next_descriptor(buffer, size, USB_DT_ENDPOINT,
+                        USB_DT_INTERFACE, &num_skipped);
+        ep->ss_ep_comp->extralen = i;
+        buffer += i;
+        size -= i;
+        retval = buffer - buffer_start + i;
+        if (num_skipped > 0)
+                dev_dbg(ddev, "skipped %d descriptor%s after %s\n",
+                                num_skipped, plural(num_skipped),
+                                "SuperSpeed endpoint companion");
+
+        /* Check the various values */
+        if (usb_endpoint_xfer_control(&ep->desc) && desc->bMaxBurst != 0) {
+                dev_warn(ddev, "Control endpoint with bMaxBurst = %d in "
+                                "config %d interface %d altsetting %d ep %d: "
+                                "setting to zero\n", desc->bMaxBurst,
+                                cfgno, inum, asnum, ep->desc.bEndpointAddress);
+                desc->bMaxBurst = 0;
+        }
+        if (desc->bMaxBurst > 15) {
+                dev_warn(ddev, "Endpoint with bMaxBurst = %d in "
+                                "config %d interface %d altsetting %d ep %d: "
+                                "setting to 15\n", desc->bMaxBurst,
+                                cfgno, inum, asnum, ep->desc.bEndpointAddress);
+                desc->bMaxBurst = 15;
+        }
+        if ((usb_endpoint_xfer_control(&ep->desc) || usb_endpoint_xfer_int(&ep->desc))
+                        && desc->bmAttributes != 0) {
+                dev_warn(ddev, "%s endpoint with bmAttributes = %d in "
+                                "config %d interface %d altsetting %d ep %d: "
+                                "setting to zero\n",
+                                usb_endpoint_xfer_control(&ep->desc) ? "Control" : "Bulk",
+                                desc->bmAttributes,
+                                cfgno, inum, asnum, ep->desc.bEndpointAddress);
+                desc->bmAttributes = 0;
+        }
+        if (usb_endpoint_xfer_bulk(&ep->desc) && desc->bmAttributes > 16) {
+                dev_warn(ddev, "Bulk endpoint with more than 65536 streams in "
+                                "config %d interface %d altsetting %d ep %d: "
+                                "setting to max\n",
+                                cfgno, inum, asnum, ep->desc.bEndpointAddress);
+                desc->bmAttributes = 16;
+        }
+        if (usb_endpoint_xfer_isoc(&ep->desc) && desc->bmAttributes > 2) {
+                dev_warn(ddev, "Isoc endpoint has Mult of %d in "
+                                "config %d interface %d altsetting %d ep %d: "
+                                "setting to 3\n", desc->bmAttributes + 1,
+                                cfgno, inum, asnum, ep->desc.bEndpointAddress);
+                desc->bmAttributes = 2;
+        }
+        if (usb_endpoint_xfer_isoc(&ep->desc)) {
+                max_tx = ep->desc.wMaxPacketSize * (desc->bMaxBurst + 1) *
+                        (desc->bmAttributes + 1);
+        } else if (usb_endpoint_xfer_int(&ep->desc)) {
+                max_tx = ep->desc.wMaxPacketSize * (desc->bMaxBurst + 1);
+        } else {
+                goto valid;
+        }
+        if (desc->wBytesPerInterval > max_tx) {
+                dev_warn(ddev, "%s endpoint with wBytesPerInterval of %d in "
+                                "config %d interface %d altsetting %d ep %d: "
+                                "setting to %d\n",
+                                usb_endpoint_xfer_isoc(&ep->desc) ? "Isoc" : "Int",
+                                desc->wBytesPerInterval,
+                                cfgno, inum, asnum, ep->desc.bEndpointAddress,
+                                max_tx);
+                desc->wBytesPerInterval = max_tx;
+        }
+valid:
+        return retval;
+}
+
 static int usb_parse_endpoint(struct device *ddev, int cfgno, int inum,
     int asnum, struct usb_host_interface *ifp, int num_ep,
     unsigned char *buffer, int size)
@@ -50,7 +199,7 @@ static int usb_parse_endpoint(struct device *ddev, int cfgno, int inum,
         unsigned char *buffer0 = buffer;
         struct usb_endpoint_descriptor *d;
         struct usb_host_endpoint *endpoint;
-        int n, i, j;
+        int n, i, j, retval;
 
         d = (struct usb_endpoint_descriptor *) buffer;
         buffer += d->bLength;
@@ -92,6 +241,7 @@ static int usb_parse_endpoint(struct device *ddev, int cfgno, int inum,
         if (usb_endpoint_xfer_int(d)) {
                 i = 1;
                 switch (to_usb_device(ddev)->speed) {
+                case USB_SPEED_SUPER:
                 case USB_SPEED_HIGH:
                         /* Many device manufacturers are using full-speed
                          * bInterval values in high-speed interrupt endpoint
@@ -161,17 +311,39 @@ static int usb_parse_endpoint(struct device *ddev, int cfgno, int inum,
                                 cfgno, inum, asnum, d->bEndpointAddress,
                                 maxp);
         }
-
-        /* Skip over any Class Specific or Vendor Specific descriptors;
-         * find the next endpoint or interface descriptor */
-        endpoint->extra = buffer;
-        i = find_next_descriptor(buffer, size, USB_DT_ENDPOINT,
-            USB_DT_INTERFACE, &n);
-        endpoint->extralen = i;
+        /* Allocate room for and parse any SS endpoint companion descriptors */
+        if (to_usb_device(ddev)->speed == USB_SPEED_SUPER) {
+                endpoint->extra = buffer;
+                i = find_next_descriptor_more(buffer, size, USB_DT_SS_ENDPOINT_COMP,
+                                USB_DT_ENDPOINT, USB_DT_INTERFACE, &n);
+                endpoint->extralen = i;
+                buffer += i;
+                size -= i;
+
+                if (size > 0) {
+                        retval = usb_parse_ss_endpoint_companion(ddev, cfgno,
+                                        inum, asnum, endpoint, num_ep, buffer,
+                                        size);
+                        if (retval >= 0) {
+                                buffer += retval;
+                                retval = buffer - buffer0;
+                        }
+                } else {
+                        retval = buffer - buffer0;
+                }
+        } else {
+                /* Skip over any Class Specific or Vendor Specific descriptors;
+                 * find the next endpoint or interface descriptor */
+                endpoint->extra = buffer;
+                i = find_next_descriptor(buffer, size, USB_DT_ENDPOINT,
+                                USB_DT_INTERFACE, &n);
+                endpoint->extralen = i;
+                retval = buffer - buffer0 + i;
+        }
         if (n > 0)
                 dev_dbg(ddev, "skipped %d descriptor%s after %s\n",
                     n, plural(n), "endpoint");
-        return buffer - buffer0 + i;
+        return retval;
 
 skip_to_next_endpoint_or_interface_descriptor:
         i = find_next_descriptor(buffer, size, USB_DT_ENDPOINT,
@@ -452,6 +624,8 @@ static int usb_parse_configuration(struct device *ddev, int cfgidx,
                 kref_init(&intfc->ref);
         }
 
+        /* FIXME: parse the BOS descriptor */
+
         /* Skip over any Class Specific or Vendor Specific descriptors;
          * find the first interface descriptor */
         config->extra = buffer;
diff --git a/drivers/usb/core/driver.c b/drivers/usb/core/driver.c
index d0a21a5f8201..69e5773abfce 100644
--- a/drivers/usb/core/driver.c
+++ b/drivers/usb/core/driver.c
@@ -154,16 +154,11 @@ static const struct usb_device_id *usb_match_dynamic_id(struct usb_interface *in
 static int usb_probe_device(struct device *dev)
 {
         struct usb_device_driver *udriver = to_usb_device_driver(dev->driver);
-        struct usb_device *udev;
+        struct usb_device *udev = to_usb_device(dev);
         int error = -ENODEV;
 
         dev_dbg(dev, "%s\n", __func__);
 
-        if (!is_usb_device(dev))        /* Sanity check */
-                return error;
-
-        udev = to_usb_device(dev);
-
         /* TODO: Add real matching code */
 
         /* The device should always appear to be in use
@@ -203,18 +198,13 @@ static void usb_cancel_queued_reset(struct usb_interface *iface)
 static int usb_probe_interface(struct device *dev)
 {
         struct usb_driver *driver = to_usb_driver(dev->driver);
-        struct usb_interface *intf;
-        struct usb_device *udev;
+        struct usb_interface *intf = to_usb_interface(dev);
+        struct usb_device *udev = interface_to_usbdev(intf);
         const struct usb_device_id *id;
         int error = -ENODEV;
 
         dev_dbg(dev, "%s\n", __func__);
 
-        if (is_usb_device(dev))         /* Sanity check */
-                return error;
-
-        intf = to_usb_interface(dev);
-        udev = interface_to_usbdev(intf);
         intf->needs_binding = 0;
 
         if (udev->authorized == 0) {
@@ -385,7 +375,6 @@ void usb_driver_release_interface(struct usb_driver *driver,
                                         struct usb_interface *iface)
 {
         struct device *dev = &iface->dev;
-        struct usb_device *udev = interface_to_usbdev(iface);
 
         /* this should never happen, don't release something that's not ours */
         if (!dev->driver || dev->driver != &driver->drvwrap.driver)
@@ -394,23 +383,19 @@ void usb_driver_release_interface(struct usb_driver *driver,
         /* don't release from within disconnect() */
         if (iface->condition != USB_INTERFACE_BOUND)
                 return;
+        iface->condition = USB_INTERFACE_UNBINDING;
 
-        /* don't release if the interface hasn't been added yet */
+        /* Release via the driver core only if the interface
+         * has already been registered
+         */
         if (device_is_registered(dev)) {
-                iface->condition = USB_INTERFACE_UNBINDING;
                 device_release_driver(dev);
         } else {
-                iface->condition = USB_INTERFACE_UNBOUND;
-                usb_cancel_queued_reset(iface);
+                down(&dev->sem);
+                usb_unbind_interface(dev);
+                dev->driver = NULL;
+                up(&dev->sem);
         }
-        dev->driver = NULL;
-        usb_set_intfdata(iface, NULL);
-
-        usb_pm_lock(udev);
-        iface->condition = USB_INTERFACE_UNBOUND;
-        mark_quiesced(iface);
-        iface->needs_remote_wakeup = 0;
-        usb_pm_unlock(udev);
 }
 EXPORT_SYMBOL_GPL(usb_driver_release_interface);
 
@@ -598,7 +583,7 @@ static int usb_device_match(struct device *dev, struct device_driver *drv)
                 /* TODO: Add real matching code */
                 return 1;
 
-        } else {
+        } else if (is_usb_interface(dev)) {
                 struct usb_interface *intf;
                 struct usb_driver *usb_drv;
                 const struct usb_device_id *id;
@@ -630,11 +615,14 @@ static int usb_uevent(struct device *dev, struct kobj_uevent_env *env)
         /* driver is often null here; dev_dbg() would oops */
         pr_debug("usb %s: uevent\n", dev_name(dev));
 
-        if (is_usb_device(dev))
+        if (is_usb_device(dev)) {
                 usb_dev = to_usb_device(dev);
-        else {
+        } else if (is_usb_interface(dev)) {
                 struct usb_interface *intf = to_usb_interface(dev);
+
                 usb_dev = interface_to_usbdev(intf);
+        } else {
+                return 0;
         }
 
         if (usb_dev->devnum < 0) {
@@ -1762,6 +1750,7 @@ int usb_suspend(struct device *dev, pm_message_t msg)
 int usb_resume(struct device *dev, pm_message_t msg)
 {
         struct usb_device       *udev;
+        int                     status;
 
         udev = to_usb_device(dev);
 
@@ -1771,7 +1760,14 @@ int usb_resume(struct device *dev, pm_message_t msg)
          */
         if (udev->skip_sys_resume)
                 return 0;
-        return usb_external_resume_device(udev, msg);
+        status = usb_external_resume_device(udev, msg);
+
+        /* Avoid PM error messages for devices disconnected while suspended
+         * as we'll display regular disconnect messages just a bit later.
+         */
+        if (status == -ENODEV)
+                return 0;
+        return status;
 }
 
 #endif /* CONFIG_PM */
diff --git a/drivers/usb/core/endpoint.c b/drivers/usb/core/endpoint.c
index 40dee2ac0133..bc39fc40bbde 100644
--- a/drivers/usb/core/endpoint.c
+++ b/drivers/usb/core/endpoint.c
@@ -15,19 +15,18 @@
 #include <linux/usb.h>
 #include "usb.h"
 
-#define MAX_ENDPOINT_MINORS (64*128*32)
-static int usb_endpoint_major;
-static DEFINE_IDR(endpoint_idr);
-
 struct ep_device {
         struct usb_endpoint_descriptor *desc;
         struct usb_device *udev;
         struct device dev;
-        int minor;
 };
 #define to_ep_device(_dev) \
         container_of(_dev, struct ep_device, dev)
 
+struct device_type usb_ep_device_type = {
+        .name =         "usb_endpoint",
+};
+
 struct ep_attribute {
         struct attribute attr;
         ssize_t (*show)(struct usb_device *,
@@ -160,118 +159,10 @@ static struct attribute_group *ep_dev_groups[] = {
         NULL
 };
 
-static int usb_endpoint_major_init(void)
-{
-        dev_t dev;
-        int error;
-
-        error = alloc_chrdev_region(&dev, 0, MAX_ENDPOINT_MINORS,
-                                    "usb_endpoint");
-        if (error) {
-                printk(KERN_ERR "Unable to get a dynamic major for "
-                       "usb endpoints.\n");
-                return error;
-        }
-        usb_endpoint_major = MAJOR(dev);
-
-        return error;
-}
-
-static void usb_endpoint_major_cleanup(void)
-{
-        unregister_chrdev_region(MKDEV(usb_endpoint_major, 0),
-                                 MAX_ENDPOINT_MINORS);
-}
-
-static int endpoint_get_minor(struct ep_device *ep_dev)
-{
-        static DEFINE_MUTEX(minor_lock);
-        int retval = -ENOMEM;
-        int id;
-
-        mutex_lock(&minor_lock);
-        if (idr_pre_get(&endpoint_idr, GFP_KERNEL) == 0)
-                goto exit;
-
-        retval = idr_get_new(&endpoint_idr, ep_dev, &id);
-        if (retval < 0) {
-                if (retval == -EAGAIN)
-                        retval = -ENOMEM;
-                goto exit;
-        }
-        ep_dev->minor = id & MAX_ID_MASK;
-exit:
-        mutex_unlock(&minor_lock);
-        return retval;
-}
-
-static void endpoint_free_minor(struct ep_device *ep_dev)
-{
-        idr_remove(&endpoint_idr, ep_dev->minor);
-}
-
-static struct endpoint_class {
-        struct kref kref;
-        struct class *class;
-} *ep_class;
-
-static int init_endpoint_class(void)
-{
-        int result = 0;
-
-        if (ep_class != NULL) {
-                kref_get(&ep_class->kref);
-                goto exit;
-        }
-
-        ep_class = kmalloc(sizeof(*ep_class), GFP_KERNEL);
-        if (!ep_class) {
-                result = -ENOMEM;
-                goto exit;
-        }
-
-        kref_init(&ep_class->kref);
-        ep_class->class = class_create(THIS_MODULE, "usb_endpoint");
-        if (IS_ERR(ep_class->class)) {
-                result = PTR_ERR(ep_class->class);
-                goto class_create_error;
-        }
-
-        result = usb_endpoint_major_init();
-        if (result)
-                goto endpoint_major_error;
-
-        goto exit;
-
-endpoint_major_error:
-        class_destroy(ep_class->class);
-class_create_error:
-        kfree(ep_class);
-        ep_class = NULL;
-exit:
-        return result;
-}
-
-static void release_endpoint_class(struct kref *kref)
-{
-        /* Ok, we cheat as we know we only have one ep_class */
-        class_destroy(ep_class->class);
-        kfree(ep_class);
-        ep_class = NULL;
-        usb_endpoint_major_cleanup();
-}
-
-static void destroy_endpoint_class(void)
-{
-        if (ep_class)
-                kref_put(&ep_class->kref, release_endpoint_class);
-}
-
 static void ep_device_release(struct device *dev)
 {
         struct ep_device *ep_dev = to_ep_device(dev);
 
-        endpoint_free_minor(ep_dev);
         kfree(ep_dev);
 }
 
@@ -279,62 +170,32 @@ int usb_create_ep_devs(struct device *parent,
                         struct usb_host_endpoint *endpoint,
                         struct usb_device *udev)
 {
-        char name[8];
         struct ep_device *ep_dev;
         int retval;
 
-        retval = init_endpoint_class();
-        if (retval)
-                goto exit;
-
         ep_dev = kzalloc(sizeof(*ep_dev), GFP_KERNEL);
         if (!ep_dev) {
                 retval = -ENOMEM;
-                goto error_alloc;
-        }
-
-        retval = endpoint_get_minor(ep_dev);
-        if (retval) {
-                dev_err(parent, "can not allocate minor number for %s\n",
-                        dev_name(&ep_dev->dev));
-                goto error_register;
+                goto exit;
         }
 
         ep_dev->desc = &endpoint->desc;
         ep_dev->udev = udev;
         ep_dev->dev.groups = ep_dev_groups;
-        ep_dev->dev.devt = MKDEV(usb_endpoint_major, ep_dev->minor);
-        ep_dev->dev.class = ep_class->class;
+        ep_dev->dev.type = &usb_ep_device_type;
         ep_dev->dev.parent = parent;
         ep_dev->dev.release = ep_device_release;
-        dev_set_name(&ep_dev->dev, "usbdev%d.%d_ep%02x",
-                 udev->bus->busnum, udev->devnum,
-                 endpoint->desc.bEndpointAddress);
+        dev_set_name(&ep_dev->dev, "ep_%02x", endpoint->desc.bEndpointAddress);
 
         retval = device_register(&ep_dev->dev);
         if (retval)
-                goto error_chrdev;
+                goto error_register;
 
-        /* create the symlink to the old-style "ep_XX" directory */
-        sprintf(name, "ep_%02x", endpoint->desc.bEndpointAddress);
-        retval = sysfs_create_link(&parent->kobj, &ep_dev->dev.kobj, name);
-        if (retval)
-                goto error_link;
         endpoint->ep_dev = ep_dev;
         return retval;
 
-error_link:
-        device_unregister(&ep_dev->dev);
-        destroy_endpoint_class();
-        return retval;
-
-error_chrdev:
-        endpoint_free_minor(ep_dev);
-
 error_register:
         kfree(ep_dev);
-error_alloc:
-        destroy_endpoint_class();
 exit:
         return retval;
 }
@@ -344,12 +205,7 @@ void usb_remove_ep_devs(struct usb_host_endpoint *endpoint)
         struct ep_device *ep_dev = endpoint->ep_dev;
 
         if (ep_dev) {
-                char name[8];
-
-                sprintf(name, "ep_%02x", endpoint->desc.bEndpointAddress);
-                sysfs_remove_link(&ep_dev->dev.parent->kobj, name);
                 device_unregister(&ep_dev->dev);
                 endpoint->ep_dev = NULL;
-                destroy_endpoint_class();
         }
 }
diff --git a/drivers/usb/core/file.c b/drivers/usb/core/file.c
index 997e659ff693..5cef88929b3e 100644
--- a/drivers/usb/core/file.c
+++ b/drivers/usb/core/file.c
@@ -67,6 +67,16 @@ static struct usb_class {
         struct class *class;
 } *usb_class;
 
+static char *usb_nodename(struct device *dev)
+{
+        struct usb_class_driver *drv;
+
+        drv = dev_get_drvdata(dev);
+        if (!drv || !drv->nodename)
+                return NULL;
+        return drv->nodename(dev);
+}
+
 static int init_usb_class(void)
 {
         int result = 0;
@@ -90,6 +100,7 @@ static int init_usb_class(void)
                 kfree(usb_class);
                 usb_class = NULL;
         }
+        usb_class->class->nodename = usb_nodename;
 
 exit:
         return result;
@@ -198,7 +209,7 @@ int usb_register_dev(struct usb_interface *intf,
         else
                 temp = name;
         intf->usb_dev = device_create(usb_class->class, &intf->dev,
-                                      MKDEV(USB_MAJOR, minor), NULL,
+                                      MKDEV(USB_MAJOR, minor), class_driver,
                                       "%s", temp);
         if (IS_ERR(intf->usb_dev)) {
                 down_write(&minor_rwsem);
diff --git a/drivers/usb/core/hcd-pci.c b/drivers/usb/core/hcd-pci.c
index a4301dc02d27..91f2885b6ee1 100644
--- a/drivers/usb/core/hcd-pci.c
+++ b/drivers/usb/core/hcd-pci.c
@@ -185,194 +185,198 @@ void usb_hcd_pci_remove(struct pci_dev *dev)
 }
 EXPORT_SYMBOL_GPL(usb_hcd_pci_remove);
 
-
-#ifdef  CONFIG_PM
-
 /**
- * usb_hcd_pci_suspend - power management suspend of a PCI-based HCD
- * @dev: USB Host Controller being suspended
- * @message: Power Management message describing this state transition
- *
- * Store this function in the HCD's struct pci_driver as .suspend.
+ * usb_hcd_pci_shutdown - shutdown host controller
+ * @dev: USB Host Controller being shutdown
  */
-int usb_hcd_pci_suspend(struct pci_dev *dev, pm_message_t message)
+void usb_hcd_pci_shutdown(struct pci_dev *dev)
+{
+        struct usb_hcd          *hcd;
+
+        hcd = pci_get_drvdata(dev);
+        if (!hcd)
+                return;
+
+        if (hcd->driver->shutdown)
+                hcd->driver->shutdown(hcd);
+}
+EXPORT_SYMBOL_GPL(usb_hcd_pci_shutdown);
+
+#ifdef  CONFIG_PM_SLEEP
+
+static int check_root_hub_suspended(struct device *dev)
+{
+        struct pci_dev          *pci_dev = to_pci_dev(dev);
+        struct usb_hcd          *hcd = pci_get_drvdata(pci_dev);
+
+        if (!(hcd->state == HC_STATE_SUSPENDED ||
+                        hcd->state == HC_STATE_HALT)) {
+                dev_warn(dev, "Root hub is not suspended\n");
+                return -EBUSY;
+        }
+        return 0;
+}
+
+static int hcd_pci_suspend(struct device *dev)
 {
-        struct usb_hcd          *hcd = pci_get_drvdata(dev);
-        int                     retval = 0;
-        int                     wake, w;
-        int                     has_pci_pm;
+        struct pci_dev          *pci_dev = to_pci_dev(dev);
+        struct usb_hcd          *hcd = pci_get_drvdata(pci_dev);
+        int                     retval;
 
         /* Root hub suspend should have stopped all downstream traffic,
          * and all bus master traffic.  And done so for both the interface
          * and the stub usb_device (which we check here).  But maybe it
          * didn't; writing sysfs power/state files ignores such rules...
-         *
-         * We must ignore the FREEZE vs SUSPEND distinction here, because
-         * otherwise the swsusp will save (and restore) garbage state.
          */
-        if (!(hcd->state == HC_STATE_SUSPENDED ||
-                        hcd->state == HC_STATE_HALT)) {
-                dev_warn(&dev->dev, "Root hub is not suspended\n");
-                retval = -EBUSY;
-                goto done;
-        }
+        retval = check_root_hub_suspended(dev);
+        if (retval)
+                return retval;
 
         /* We might already be suspended (runtime PM -- not yet written) */
-        if (dev->current_state != PCI_D0)
-                goto done;
+        if (pci_dev->current_state != PCI_D0)
+                return retval;
 
         if (hcd->driver->pci_suspend) {
-                retval = hcd->driver->pci_suspend(hcd, message);
+                retval = hcd->driver->pci_suspend(hcd);
                 suspend_report_result(hcd->driver->pci_suspend, retval);
                 if (retval)
-                        goto done;
+                        return retval;
         }
 
-        synchronize_irq(dev->irq);
+        synchronize_irq(pci_dev->irq);
 
         /* Downstream ports from this root hub should already be quiesced, so
          * there will be no DMA activity.  Now we can shut down the upstream
-         * link (except maybe for PME# resume signaling) and enter some PCI
-         * low power state, if the hardware allows.
+         * link (except maybe for PME# resume signaling).  We'll enter a
+         * low power state during suspend_noirq, if the hardware allows.
          */
-        pci_disable_device(dev);
+        pci_disable_device(pci_dev);
+        return retval;
+}
+
+static int hcd_pci_suspend_noirq(struct device *dev)
+{
+        struct pci_dev          *pci_dev = to_pci_dev(dev);
+        struct usb_hcd          *hcd = pci_get_drvdata(pci_dev);
+        int                     retval;
+
+        retval = check_root_hub_suspended(dev);
+        if (retval)
+                return retval;
 
-        pci_save_state(dev);
+        pci_save_state(pci_dev);
 
-        /* Don't fail on error to enable wakeup.  We rely on pci code
-         * to reject requests the hardware can't implement, rather
-         * than coding the same thing.
+        /* If the root hub is HALTed rather than SUSPENDed,
+         * disallow remote wakeup.
          */
-        wake = (hcd->state == HC_STATE_SUSPENDED &&
-                        device_may_wakeup(&dev->dev));
-        w = pci_wake_from_d3(dev, wake);
-        if (w < 0)
-                wake = w;
-        dev_dbg(&dev->dev, "wakeup: %d\n", wake);
-
-        /* Don't change state if we don't need to */
-        if (message.event == PM_EVENT_FREEZE ||
-                        message.event == PM_EVENT_PRETHAW) {
-                dev_dbg(&dev->dev, "--> no state change\n");
-                goto done;
-        }
+        if (hcd->state == HC_STATE_HALT)
+                device_set_wakeup_enable(dev, 0);
+        dev_dbg(dev, "wakeup: %d\n", device_may_wakeup(dev));
 
-        has_pci_pm = pci_find_capability(dev, PCI_CAP_ID_PM);
-        if (!has_pci_pm) {
-                dev_dbg(&dev->dev, "--> PCI D0 legacy\n");
+        /* Possibly enable remote wakeup,
+         * choose the appropriate low-power state, and go to that state.
+         */
+        retval = pci_prepare_to_sleep(pci_dev);
+        if (retval == -EIO) {           /* Low-power not supported */
+                dev_dbg(dev, "--> PCI D0 legacy\n");
+                retval = 0;
+        } else if (retval == 0) {
+                dev_dbg(dev, "--> PCI %s\n",
+                                pci_power_name(pci_dev->current_state));
         } else {
-
-                /* NOTE:  dev->current_state becomes nonzero only here, and
-                 * only for devices that support PCI PM.  Also, exiting
-                 * PCI_D3 (but not PCI_D1 or PCI_D2) is allowed to reset
-                 * some device state (e.g. as part of clock reinit).
-                 */
-                retval = pci_set_power_state(dev, PCI_D3hot);
-                suspend_report_result(pci_set_power_state, retval);
-                if (retval == 0) {
-                        dev_dbg(&dev->dev, "--> PCI D3\n");
-                } else {
-                        dev_dbg(&dev->dev, "PCI D3 suspend fail, %d\n",
-                                        retval);
-                        pci_restore_state(dev);
-                }
+                suspend_report_result(pci_prepare_to_sleep, retval);
+                return retval;
         }
 
 #ifdef CONFIG_PPC_PMAC
-        if (retval == 0) {
-                /* Disable ASIC clocks for USB */
-                if (machine_is(powermac)) {
-                        struct device_node      *of_node;
-
-                        of_node = pci_device_to_OF_node(dev);
-                        if (of_node)
-                                pmac_call_feature(PMAC_FTR_USB_ENABLE,
-                                                        of_node, 0, 0);
-                }
+        /* Disable ASIC clocks for USB */
+        if (machine_is(powermac)) {
+                struct device_node      *of_node;
+
+                of_node = pci_device_to_OF_node(pci_dev);
+                if (of_node)
+                        pmac_call_feature(PMAC_FTR_USB_ENABLE, of_node, 0, 0);
         }
 #endif
-
- done:
         return retval;
 }
-EXPORT_SYMBOL_GPL(usb_hcd_pci_suspend);
 
-/**
- * usb_hcd_pci_resume - power management resume of a PCI-based HCD
- * @dev: USB Host Controller being resumed
- *
- * Store this function in the HCD's struct pci_driver as .resume.
- */
-int usb_hcd_pci_resume(struct pci_dev *dev)
+static int hcd_pci_resume_noirq(struct device *dev)
 {
-        struct usb_hcd          *hcd;
-        int                     retval;
+        struct pci_dev          *pci_dev = to_pci_dev(dev);
 
 #ifdef CONFIG_PPC_PMAC
         /* Reenable ASIC clocks for USB */
         if (machine_is(powermac)) {
                 struct device_node *of_node;
 
-                of_node = pci_device_to_OF_node(dev);
+                of_node = pci_device_to_OF_node(pci_dev);
                 if (of_node)
                         pmac_call_feature(PMAC_FTR_USB_ENABLE,
                                                 of_node, 0, 1);
         }
 #endif
 
-        pci_restore_state(dev);
+        /* Go back to D0 and disable remote wakeup */
+        pci_back_from_sleep(pci_dev);
+        return 0;
+}
+
+static int resume_common(struct device *dev, bool hibernated)
+{
+        struct pci_dev          *pci_dev = to_pci_dev(dev);
+        struct usb_hcd          *hcd = pci_get_drvdata(pci_dev);
+        int                     retval;
 
-        hcd = pci_get_drvdata(dev);
         if (hcd->state != HC_STATE_SUSPENDED) {
-                dev_dbg(hcd->self.controller,
-                                "can't resume, not suspended!\n");
+                dev_dbg(dev, "can't resume, not suspended!\n");
                 return 0;
         }
 
-        pci_enable_wake(dev, PCI_D0, false);
-
-        retval = pci_enable_device(dev);
+        retval = pci_enable_device(pci_dev);
         if (retval < 0) {
-                dev_err(&dev->dev, "can't re-enable after resume, %d!\n",
-                                retval);
+                dev_err(dev, "can't re-enable after resume, %d!\n", retval);
                 return retval;
         }
 
-        pci_set_master(dev);
-
-        /* yes, ignore this result too... */
-        (void) pci_wake_from_d3(dev, 0);
+        pci_set_master(pci_dev);
 
         clear_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
 
         if (hcd->driver->pci_resume) {
-                retval = hcd->driver->pci_resume(hcd);
+                retval = hcd->driver->pci_resume(hcd, hibernated);
                 if (retval) {
-                        dev_err(hcd->self.controller,
-                                "PCI post-resume error %d!\n", retval);
+                        dev_err(dev, "PCI post-resume error %d!\n", retval);
                         usb_hc_died(hcd);
                 }
         }
         return retval;
 }
-EXPORT_SYMBOL_GPL(usb_hcd_pci_resume);
 
-#endif  /* CONFIG_PM */
-
-/**
- * usb_hcd_pci_shutdown - shutdown host controller
- * @dev: USB Host Controller being shutdown
- */
-void usb_hcd_pci_shutdown(struct pci_dev *dev)
+static int hcd_pci_resume(struct device *dev)
 {
-        struct usb_hcd          *hcd;
-
-        hcd = pci_get_drvdata(dev);
-        if (!hcd)
-                return;
+        return resume_common(dev, false);
+}
 
-        if (hcd->driver->shutdown)
-                hcd->driver->shutdown(hcd);
+static int hcd_pci_restore(struct device *dev)
+{
+        return resume_common(dev, true);
 }
-EXPORT_SYMBOL_GPL(usb_hcd_pci_shutdown);
 
+struct dev_pm_ops usb_hcd_pci_pm_ops = {
+        .suspend        = hcd_pci_suspend,
+        .suspend_noirq  = hcd_pci_suspend_noirq,
+        .resume_noirq   = hcd_pci_resume_noirq,
+        .resume         = hcd_pci_resume,
+        .freeze         = check_root_hub_suspended,
+        .freeze_noirq   = check_root_hub_suspended,
+        .thaw_noirq     = NULL,
+        .thaw           = NULL,
+        .poweroff       = hcd_pci_suspend,
+        .poweroff_noirq = hcd_pci_suspend_noirq,
+        .restore_noirq  = hcd_pci_resume_noirq,
+        .restore        = hcd_pci_restore,
+};
+EXPORT_SYMBOL_GPL(usb_hcd_pci_pm_ops);
+
+#endif  /* CONFIG_PM_SLEEP */
diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 42b93da1085d..ce3f453f02ef 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -128,6 +128,27 @@ static inline int is_root_hub(struct usb_device *udev)
 #define KERNEL_REL      ((LINUX_VERSION_CODE >> 16) & 0x0ff)
 #define KERNEL_VER      ((LINUX_VERSION_CODE >> 8) & 0x0ff)
 
+/* usb 3.0 root hub device descriptor */
+static const u8 usb3_rh_dev_descriptor[18] = {
+        0x12,       /*  __u8  bLength; */
+        0x01,       /*  __u8  bDescriptorType; Device */
+        0x00, 0x03, /*  __le16 bcdUSB; v3.0 */
+
+        0x09,       /*  __u8  bDeviceClass; HUB_CLASSCODE */
+        0x00,       /*  __u8  bDeviceSubClass; */
+        0x03,       /*  __u8  bDeviceProtocol; USB 3.0 hub */
+        0x09,       /*  __u8  bMaxPacketSize0; 2^9 = 512 Bytes */
+
+        0x6b, 0x1d, /*  __le16 idVendor; Linux Foundation */
+        0x02, 0x00, /*  __le16 idProduct; device 0x0002 */
+        KERNEL_VER, KERNEL_REL, /*  __le16 bcdDevice */
+
+        0x03,       /*  __u8  iManufacturer; */
+        0x02,       /*  __u8  iProduct; */
+        0x01,       /*  __u8  iSerialNumber; */
+        0x01        /*  __u8  bNumConfigurations; */
+};
+
 /* usb 2.0 root hub device descriptor */
 static const u8 usb2_rh_dev_descriptor [18] = {
         0x12,       /*  __u8  bLength; */
@@ -273,6 +294,47 @@ static const u8 hs_rh_config_descriptor [] = {
         0x0c        /*  __u8  ep_bInterval; (256ms -- usb 2.0 spec) */
 };
 
+static const u8 ss_rh_config_descriptor[] = {
+        /* one configuration */
+        0x09,       /*  __u8  bLength; */
+        0x02,       /*  __u8  bDescriptorType; Configuration */
+        0x19, 0x00, /*  __le16 wTotalLength; FIXME */
+        0x01,       /*  __u8  bNumInterfaces; (1) */
+        0x01,       /*  __u8  bConfigurationValue; */
+        0x00,       /*  __u8  iConfiguration; */
+        0xc0,       /*  __u8  bmAttributes;
+                                 Bit 7: must be set,
+                                     6: Self-powered,
+                                     5: Remote wakeup,
+                                     4..0: resvd */
+        0x00,       /*  __u8  MaxPower; */
+
+        /* one interface */
+        0x09,       /*  __u8  if_bLength; */
+        0x04,       /*  __u8  if_bDescriptorType; Interface */
+        0x00,       /*  __u8  if_bInterfaceNumber; */
+        0x00,       /*  __u8  if_bAlternateSetting; */
+        0x01,       /*  __u8  if_bNumEndpoints; */
+        0x09,       /*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
+        0x00,       /*  __u8  if_bInterfaceSubClass; */
+        0x00,       /*  __u8  if_bInterfaceProtocol; */
+        0x00,       /*  __u8  if_iInterface; */
+
+        /* one endpoint (status change endpoint) */
+        0x07,       /*  __u8  ep_bLength; */
+        0x05,       /*  __u8  ep_bDescriptorType; Endpoint */
+        0x81,       /*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
+        0x03,       /*  __u8  ep_bmAttributes; Interrupt */
+                    /* __le16 ep_wMaxPacketSize; 1 + (MAX_ROOT_PORTS / 8)
+                     * see hub.c:hub_configure() for details. */
+        (USB_MAXCHILDREN + 1 + 7) / 8, 0x00,
+        0x0c        /*  __u8  ep_bInterval; (256ms -- usb 2.0 spec) */
+        /*
+         * All 3.0 hubs should have an endpoint companion descriptor,
+         * but we're ignoring that for now.  FIXME?
+         */
+};
+
 /*-------------------------------------------------------------------------*/
 
 /*
@@ -426,23 +488,39 @@ static int rh_call_control (struct usb_hcd *hcd, struct urb *urb)
         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
                 switch (wValue & 0xff00) {
                 case USB_DT_DEVICE << 8:
-                        if (hcd->driver->flags & HCD_USB2)
+                        switch (hcd->driver->flags & HCD_MASK) {
+                        case HCD_USB3:
+                                bufp = usb3_rh_dev_descriptor;
+                                break;
+                        case HCD_USB2:
                                 bufp = usb2_rh_dev_descriptor;
-                        else if (hcd->driver->flags & HCD_USB11)
+                                break;
+                        case HCD_USB11:
                                 bufp = usb11_rh_dev_descriptor;
-                        else
+                                break;
+                        default:
                                 goto error;
+                        }
                         len = 18;
                         if (hcd->has_tt)
                                 patch_protocol = 1;
                         break;
                 case USB_DT_CONFIG << 8:
-                        if (hcd->driver->flags & HCD_USB2) {
+                        switch (hcd->driver->flags & HCD_MASK) {
+                        case HCD_USB3:
+                                bufp = ss_rh_config_descriptor;
+                                len = sizeof ss_rh_config_descriptor;
+                                break;
+                        case HCD_USB2:
                                 bufp = hs_rh_config_descriptor;
                                 len = sizeof hs_rh_config_descriptor;
-                        } else {
+                                break;
+                        case HCD_USB11:
                                 bufp = fs_rh_config_descriptor;
                                 len = sizeof fs_rh_config_descriptor;
+                                break;
+                        default:
+                                goto error;
                         }
                         if (device_can_wakeup(&hcd->self.root_hub->dev))
                                 patch_wakeup = 1;
@@ -755,23 +833,6 @@ static struct attribute_group usb_bus_attr_group = {
 
 /*-------------------------------------------------------------------------*/
 
-static struct class *usb_host_class;
-
-int usb_host_init(void)
-{
-        int retval = 0;
-
-        usb_host_class = class_create(THIS_MODULE, "usb_host");
-        if (IS_ERR(usb_host_class))
-                retval = PTR_ERR(usb_host_class);
-        return retval;
-}
-
-void usb_host_cleanup(void)
-{
-        class_destroy(usb_host_class);
-}
-
 /**
  * usb_bus_init - shared initialization code
  * @bus: the bus structure being initialized
@@ -818,12 +879,6 @@ static int usb_register_bus(struct usb_bus *bus)
         set_bit (busnum, busmap.busmap);
         bus->busnum = busnum;
 
-        bus->dev = device_create(usb_host_class, bus->controller, MKDEV(0, 0),
-                                 bus, "usb_host%d", busnum);
-        result = PTR_ERR(bus->dev);
-        if (IS_ERR(bus->dev))
-                goto error_create_class_dev;
-
         /* Add it to the local list of buses */
         list_add (&bus->bus_list, &usb_bus_list);
         mutex_unlock(&usb_bus_list_lock);
@@ -834,8 +889,6 @@ static int usb_register_bus(struct usb_bus *bus)
                   "number %d\n", bus->busnum);
         return 0;
 
-error_create_class_dev:
-        clear_bit(busnum, busmap.busmap);
 error_find_busnum:
         mutex_unlock(&usb_bus_list_lock);
         return result;
@@ -865,8 +918,6 @@ static void usb_deregister_bus (struct usb_bus *bus)
         usb_notify_remove_bus(bus);
 
         clear_bit (bus->busnum, busmap.busmap);
-
-        device_unregister(bus->dev);
 }
 
 /**
@@ -1199,7 +1250,8 @@ static int map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
 
         /* Map the URB's buffers for DMA access.
          * Lower level HCD code should use *_dma exclusively,
-         * unless it uses pio or talks to another transport.
+         * unless it uses pio or talks to another transport,
+         * or uses the provided scatter gather list for bulk.
          */
         if (is_root_hub(urb->dev))
                 return 0;
@@ -1520,6 +1572,92 @@ rescan:
         }
 }
 
+/* Check whether a new configuration or alt setting for an interface
+ * will exceed the bandwidth for the bus (or the host controller resources).
+ * Only pass in a non-NULL config or interface, not both!
+ * Passing NULL for both new_config and new_intf means the device will be
+ * de-configured by issuing a set configuration 0 command.
+ */
+int usb_hcd_check_bandwidth(struct usb_device *udev,
+                struct usb_host_config *new_config,
+                struct usb_interface *new_intf)
+{
+        int num_intfs, i, j;
+        struct usb_interface_cache *intf_cache;
+        struct usb_host_interface *alt = 0;
+        int ret = 0;
+        struct usb_hcd *hcd;
+        struct usb_host_endpoint *ep;
+
+        hcd = bus_to_hcd(udev->bus);
+        if (!hcd->driver->check_bandwidth)
+                return 0;
+
+        /* Configuration is being removed - set configuration 0 */
+        if (!new_config && !new_intf) {
+                for (i = 1; i < 16; ++i) {
+                        ep = udev->ep_out[i];
+                        if (ep)
+                                hcd->driver->drop_endpoint(hcd, udev, ep);
+                        ep = udev->ep_in[i];
+                        if (ep)
+                                hcd->driver->drop_endpoint(hcd, udev, ep);
+                }
+                hcd->driver->check_bandwidth(hcd, udev);
+                return 0;
+        }
+        /* Check if the HCD says there's enough bandwidth.  Enable all endpoints
+         * each interface's alt setting 0 and ask the HCD to check the bandwidth
+         * of the bus.  There will always be bandwidth for endpoint 0, so it's
+         * ok to exclude it.
+         */
+        if (new_config) {
+                num_intfs = new_config->desc.bNumInterfaces;
+                /* Remove endpoints (except endpoint 0, which is always on the
+                 * schedule) from the old config from the schedule
+                 */
+                for (i = 1; i < 16; ++i) {
+                        ep = udev->ep_out[i];
+                        if (ep) {
+                                ret = hcd->driver->drop_endpoint(hcd, udev, ep);
+                                if (ret < 0)
+                                        goto reset;
+                        }
+                        ep = udev->ep_in[i];
+                        if (ep) {
+                                ret = hcd->driver->drop_endpoint(hcd, udev, ep);
+                                if (ret < 0)
+                                        goto reset;
+                        }
+                }
+                for (i = 0; i < num_intfs; ++i) {
+
+                        /* Dig the endpoints for alt setting 0 out of the
+                         * interface cache for this interface
+                         */
+                        intf_cache = new_config->intf_cache[i];
+                        for (j = 0; j < intf_cache->num_altsetting; j++) {
+                                if (intf_cache->altsetting[j].desc.bAlternateSetting == 0)
+                                        alt = &intf_cache->altsetting[j];
+                        }
+                        if (!alt) {
+                                printk(KERN_DEBUG "Did not find alt setting 0 for intf %d\n", i);
+                                continue;
+                        }
+                        for (j = 0; j < alt->desc.bNumEndpoints; j++) {
+                                ret = hcd->driver->add_endpoint(hcd, udev, &alt->endpoint[j]);
+                                if (ret < 0)
+                                        goto reset;
+                        }
+                }
+        }
+        ret = hcd->driver->check_bandwidth(hcd, udev);
+reset:
+        if (ret < 0)
+                hcd->driver->reset_bandwidth(hcd, udev);
+        return ret;
+}
+
 /* Disables the endpoint: synchronizes with the hcd to make sure all
  * endpoint state is gone from hardware.  usb_hcd_flush_endpoint() must
  * have been called previously.  Use for set_configuration, set_interface,
@@ -1897,8 +2035,20 @@ int usb_add_hcd(struct usb_hcd *hcd,
                 retval = -ENOMEM;
                 goto err_allocate_root_hub;
         }
-        rhdev->speed = (hcd->driver->flags & HCD_USB2) ? USB_SPEED_HIGH :
-                        USB_SPEED_FULL;
+
+        switch (hcd->driver->flags & HCD_MASK) {
+        case HCD_USB11:
+                rhdev->speed = USB_SPEED_FULL;
+                break;
+        case HCD_USB2:
+                rhdev->speed = USB_SPEED_HIGH;
+                break;
+        case HCD_USB3:
+                rhdev->speed = USB_SPEED_SUPER;
+                break;
+        default:
+                goto err_allocate_root_hub;
+        }
         hcd->self.root_hub = rhdev;
 
         /* wakeup flag init defaults to "everything works" for root hubs,
diff --git a/drivers/usb/core/hcd.h b/drivers/usb/core/hcd.h
index e7d4479de41c..d397ecfd5b17 100644
--- a/drivers/usb/core/hcd.h
+++ b/drivers/usb/core/hcd.h
@@ -173,6 +173,8 @@ struct hc_driver {
 #define HCD_LOCAL_MEM   0x0002          /* HC needs local memory */
 #define HCD_USB11       0x0010          /* USB 1.1 */
 #define HCD_USB2        0x0020          /* USB 2.0 */
+#define HCD_USB3        0x0040          /* USB 3.0 */
+#define HCD_MASK        0x0070
 
         /* called to init HCD and root hub */
         int     (*reset) (struct usb_hcd *hcd);
@@ -182,10 +184,10 @@ struct hc_driver {
          * a whole, not just the root hub; they're for PCI bus glue.
          */
         /* called after suspending the hub, before entering D3 etc */
-        int     (*pci_suspend) (struct usb_hcd *hcd, pm_message_t message);
+        int     (*pci_suspend)(struct usb_hcd *hcd);
 
         /* called after entering D0 (etc), before resuming the hub */
-        int     (*pci_resume) (struct usb_hcd *hcd);
+        int     (*pci_resume)(struct usb_hcd *hcd, bool hibernated);
 
         /* cleanly make HCD stop writing memory and doing I/O */
         void    (*stop) (struct usb_hcd *hcd);
@@ -224,6 +226,43 @@ struct hc_driver {
         void    (*relinquish_port)(struct usb_hcd *, int);
                 /* has a port been handed over to a companion? */
         int     (*port_handed_over)(struct usb_hcd *, int);
+
+        /* xHCI specific functions */
+                /* Called by usb_alloc_dev to alloc HC device structures */
+        int     (*alloc_dev)(struct usb_hcd *, struct usb_device *);
+                /* Called by usb_release_dev to free HC device structures */
+        void    (*free_dev)(struct usb_hcd *, struct usb_device *);
+
+        /* Bandwidth computation functions */
+        /* Note that add_endpoint() can only be called once per endpoint before
+         * check_bandwidth() or reset_bandwidth() must be called.
+         * drop_endpoint() can only be called once per endpoint also.
+         * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
+         * add the endpoint to the schedule with possibly new parameters denoted by a
+         * different endpoint descriptor in usb_host_endpoint.
+         * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
+         * not allowed.
+         */
+                /* Allocate endpoint resources and add them to a new schedule */
+        int     (*add_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);
+                /* Drop an endpoint from a new schedule */
+        int     (*drop_endpoint)(struct usb_hcd *, struct usb_device *, struct usb_host_endpoint *);
+                /* Check that a new hardware configuration, set using
+                 * endpoint_enable and endpoint_disable, does not exceed bus
+                 * bandwidth.  This must be called before any set configuration
+                 * or set interface requests are sent to the device.
+                 */
+        int     (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
+                /* Reset the device schedule to the last known good schedule,
+                 * which was set from a previous successful call to
+                 * check_bandwidth().  This reverts any add_endpoint() and
+                 * drop_endpoint() calls since that last successful call.
+                 * Used for when a check_bandwidth() call fails due to resource
+                 * or bandwidth constraints.
+                 */
+        void    (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
+                /* Returns the hardware-chosen device address */
+        int     (*address_device)(struct usb_hcd *, struct usb_device *udev);
 };
 
 extern int usb_hcd_link_urb_to_ep(struct usb_hcd *hcd, struct urb *urb);
@@ -242,6 +281,9 @@ extern void usb_hcd_disable_endpoint(struct usb_device *udev,
 extern void usb_hcd_reset_endpoint(struct usb_device *udev,
                 struct usb_host_endpoint *ep);
 extern void usb_hcd_synchronize_unlinks(struct usb_device *udev);
+extern int usb_hcd_check_bandwidth(struct usb_device *udev,
+                struct usb_host_config *new_config,
+                struct usb_interface *new_intf);
 extern int usb_hcd_get_frame_number(struct usb_device *udev);
 
 extern struct usb_hcd *usb_create_hcd(const struct hc_driver *driver,
@@ -261,14 +303,11 @@ struct pci_device_id;
 extern int usb_hcd_pci_probe(struct pci_dev *dev,
                                 const struct pci_device_id *id);
 extern void usb_hcd_pci_remove(struct pci_dev *dev);
-
-#ifdef CONFIG_PM
-extern int usb_hcd_pci_suspend(struct pci_dev *dev, pm_message_t msg);
-extern int usb_hcd_pci_resume(struct pci_dev *dev);
-#endif /* CONFIG_PM */
-
 extern void usb_hcd_pci_shutdown(struct pci_dev *dev);
 
+#ifdef CONFIG_PM_SLEEP
+extern struct dev_pm_ops        usb_hcd_pci_pm_ops;
+#endif
 #endif /* CONFIG_PCI */
 
 /* pci-ish (pdev null is ok) buffer alloc/mapping support */
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index be86ae3f4088..2af3b4f06054 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -155,6 +155,8 @@ static inline char *portspeed(int portstatus)
                 return "480 Mb/s";
         else if (portstatus & (1 << USB_PORT_FEAT_LOWSPEED))
                 return "1.5 Mb/s";
+        else if (portstatus & (1 << USB_PORT_FEAT_SUPERSPEED))
+                return "5.0 Gb/s";
         else
                 return "12 Mb/s";
 }
@@ -457,13 +459,13 @@ static void hub_tt_kevent (struct work_struct *work)
 
         spin_lock_irqsave (&hub->tt.lock, flags);
         while (--limit && !list_empty (&hub->tt.clear_list)) {
-                struct list_head        *temp;
+                struct list_head        *next;
                 struct usb_tt_clear     *clear;
                 struct usb_device       *hdev = hub->hdev;
                 int                     status;
 
-                temp = hub->tt.clear_list.next;
-                clear = list_entry (temp, struct usb_tt_clear, clear_list);
+                next = hub->tt.clear_list.next;
+                clear = list_entry (next, struct usb_tt_clear, clear_list);
                 list_del (&clear->clear_list);
 
                 /* drop lock so HCD can concurrently report other TT errors */
@@ -951,6 +953,9 @@ static int hub_configure(struct usb_hub *hub,
                                         ret);
                         hub->tt.hub = hdev;
                         break;
+                case 3:
+                        /* USB 3.0 hubs don't have a TT */
+                        break;
                 default:
                         dev_dbg(hub_dev, "Unrecognized hub protocol %d\n",
                                 hdev->descriptor.bDeviceProtocol);
@@ -1323,6 +1328,11 @@ EXPORT_SYMBOL_GPL(usb_set_device_state);
  * 0 is reserved by USB for default address; (b) Linux's USB stack
  * uses always #1 for the root hub of the controller. So USB stack's
  * port #1, which is wusb virtual-port #0 has address #2.
+ *
+ * Devices connected under xHCI are not as simple.  The host controller
+ * supports virtualization, so the hardware assigns device addresses and
+ * the HCD must setup data structures before issuing a set address
+ * command to the hardware.
  */
 static void choose_address(struct usb_device *udev)
 {
@@ -1642,6 +1652,9 @@ int usb_new_device(struct usb_device *udev)
         err = usb_configure_device(udev);       /* detect & probe dev/intfs */
         if (err < 0)
                 goto fail;
+        dev_dbg(&udev->dev, "udev %d, busnum %d, minor = %d\n",
+                        udev->devnum, udev->bus->busnum,
+                        (((udev->bus->busnum-1) * 128) + (udev->devnum-1)));
         /* export the usbdev device-node for libusb */
         udev->dev.devt = MKDEV(USB_DEVICE_MAJOR,
                         (((udev->bus->busnum-1) * 128) + (udev->devnum-1)));
@@ -2395,19 +2408,29 @@ EXPORT_SYMBOL_GPL(usb_ep0_reinit);
 static int hub_set_address(struct usb_device *udev, int devnum)
 {
         int retval;
+        struct usb_hcd *hcd = bus_to_hcd(udev->bus);
 
-        if (devnum <= 1)
+        /*
+         * The host controller will choose the device address,
+         * instead of the core having chosen it earlier
+         */
+        if (!hcd->driver->address_device && devnum <= 1)
                 return -EINVAL;
         if (udev->state == USB_STATE_ADDRESS)
                 return 0;
         if (udev->state != USB_STATE_DEFAULT)
                 return -EINVAL;
-        retval = usb_control_msg(udev, usb_sndaddr0pipe(),
-                USB_REQ_SET_ADDRESS, 0, devnum, 0,
-                NULL, 0, USB_CTRL_SET_TIMEOUT);
+        if (hcd->driver->address_device) {
+                retval = hcd->driver->address_device(hcd, udev);
+        } else {
+                retval = usb_control_msg(udev, usb_sndaddr0pipe(),
+                                USB_REQ_SET_ADDRESS, 0, devnum, 0,
+                                NULL, 0, USB_CTRL_SET_TIMEOUT);
+                if (retval == 0)
+                        update_address(udev, devnum);
+        }
         if (retval == 0) {
                 /* Device now using proper address. */
-                update_address(udev, devnum);
                 usb_set_device_state(udev, USB_STATE_ADDRESS);
                 usb_ep0_reinit(udev);
         }
@@ -2430,6 +2453,7 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
         static DEFINE_MUTEX(usb_address0_mutex);
 
         struct usb_device       *hdev = hub->hdev;
+        struct usb_hcd          *hcd = bus_to_hcd(hdev->bus);
         int                     i, j, retval;
         unsigned                delay = HUB_SHORT_RESET_TIME;
         enum usb_device_speed   oldspeed = udev->speed;
@@ -2452,11 +2476,24 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
 
         mutex_lock(&usb_address0_mutex);
 
-        /* Reset the device; full speed may morph to high speed */
-        retval = hub_port_reset(hub, port1, udev, delay);
-        if (retval < 0)         /* error or disconnect */
+        if ((hcd->driver->flags & HCD_USB3) && udev->config) {
+                /* FIXME this will need special handling by the xHCI driver. */
+                dev_dbg(&udev->dev,
+                                "xHCI reset of configured device "
+                                "not supported yet.\n");
+                retval = -EINVAL;
                 goto fail;
-                                /* success, speed is known */
+        } else if (!udev->config && oldspeed == USB_SPEED_SUPER) {
+                /* Don't reset USB 3.0 devices during an initial setup */
+                usb_set_device_state(udev, USB_STATE_DEFAULT);
+        } else {
+                /* Reset the device; full speed may morph to high speed */
+                /* FIXME a USB 2.0 device may morph into SuperSpeed on reset. */
+                retval = hub_port_reset(hub, port1, udev, delay);
+                if (retval < 0)         /* error or disconnect */
+                        goto fail;
+                /* success, speed is known */
+        }
         retval = -ENODEV;
 
         if (oldspeed != USB_SPEED_UNKNOWN && oldspeed != udev->speed) {
@@ -2471,6 +2508,7 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
          * reported as 0xff in the device descriptor). WUSB1.0[4.8.1].
          */
         switch (udev->speed) {
+        case USB_SPEED_SUPER:
         case USB_SPEED_VARIABLE:        /* fixed at 512 */
                 udev->ep0.desc.wMaxPacketSize = cpu_to_le16(512);
                 break;
@@ -2496,16 +2534,20 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
         case USB_SPEED_LOW:     speed = "low";  break;
         case USB_SPEED_FULL:    speed = "full"; break;
         case USB_SPEED_HIGH:    speed = "high"; break;
+        case USB_SPEED_SUPER:
+                                speed = "super";
+                                break;
         case USB_SPEED_VARIABLE:
                                 speed = "variable";
                                 type = "Wireless ";
                                 break;
         default:                speed = "?";    break;
         }
-        dev_info (&udev->dev,
-                  "%s %s speed %sUSB device using %s and address %d\n",
-                  (udev->config) ? "reset" : "new", speed, type,
-                  udev->bus->controller->driver->name, devnum);
+        if (udev->speed != USB_SPEED_SUPER)
+                dev_info(&udev->dev,
+                                "%s %s speed %sUSB device using %s and address %d\n",
+                                (udev->config) ? "reset" : "new", speed, type,
+                                udev->bus->controller->driver->name, devnum);
 
         /* Set up TT records, if needed  */
         if (hdev->tt) {
@@ -2530,7 +2572,11 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
          * value.
          */
         for (i = 0; i < GET_DESCRIPTOR_TRIES; (++i, msleep(100))) {
-                if (USE_NEW_SCHEME(retry_counter)) {
+                /*
+                 * An xHCI controller cannot send any packets to a device until
+                 * a set address command successfully completes.
+                 */
+                if (USE_NEW_SCHEME(retry_counter) && !(hcd->driver->flags & HCD_USB3)) {
                         struct usb_device_descriptor *buf;
                         int r = 0;
 
@@ -2596,7 +2642,7 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
                  * unauthorized address in the Connect Ack sequence;
                  * authorization will assign the final address.
                  */
-                if (udev->wusb == 0) {
+                if (udev->wusb == 0) {
                         for (j = 0; j < SET_ADDRESS_TRIES; ++j) {
                                 retval = hub_set_address(udev, devnum);
                                 if (retval >= 0)
@@ -2609,13 +2655,20 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
                                         devnum, retval);
                                 goto fail;
                         }
+                        if (udev->speed == USB_SPEED_SUPER) {
+                                devnum = udev->devnum;
+                                dev_info(&udev->dev,
+                                                "%s SuperSpeed USB device using %s and address %d\n",
+                                                (udev->config) ? "reset" : "new",
+                                                udev->bus->controller->driver->name, devnum);
+                        }
 
                         /* cope with hardware quirkiness:
                          *  - let SET_ADDRESS settle, some device hardware wants it
                          *  - read ep0 maxpacket even for high and low speed,
                          */
                         msleep(10);
-                        if (USE_NEW_SCHEME(retry_counter))
+                        if (USE_NEW_SCHEME(retry_counter) && !(hcd->driver->flags & HCD_USB3))
                                 break;
                 }
 
@@ -2634,8 +2687,11 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
         if (retval)
                 goto fail;
 
-        i = udev->descriptor.bMaxPacketSize0 == 0xff?   /* wusb device? */
-            512 : udev->descriptor.bMaxPacketSize0;
+        if (udev->descriptor.bMaxPacketSize0 == 0xff ||
+                        udev->speed == USB_SPEED_SUPER)
+                i = 512;
+        else
+                i = udev->descriptor.bMaxPacketSize0;
         if (le16_to_cpu(udev->ep0.desc.wMaxPacketSize) != i) {
                 if (udev->speed != USB_SPEED_FULL ||
                                 !(i == 8 || i == 16 || i == 32 || i == 64)) {
@@ -2847,19 +2903,41 @@ static void hub_port_connect_change(struct usb_hub *hub, int port1,
                 }
 
                 usb_set_device_state(udev, USB_STATE_POWERED);
-                udev->speed = USB_SPEED_UNKNOWN;
                 udev->bus_mA = hub->mA_per_port;
                 udev->level = hdev->level + 1;
                 udev->wusb = hub_is_wusb(hub);
 
-                /* set the address */
-                choose_address(udev);
-                if (udev->devnum <= 0) {
-                        status = -ENOTCONN;     /* Don't retry */
-                        goto loop;
+                /*
+                 * USB 3.0 devices are reset automatically before the connect
+                 * port status change appears, and the root hub port status
+                 * shows the correct speed.  We also get port change
+                 * notifications for USB 3.0 devices from the USB 3.0 portion of
+                 * an external USB 3.0 hub, but this isn't handled correctly yet
+                 * FIXME.
+                 */
+
+                if (!(hcd->driver->flags & HCD_USB3))
+                        udev->speed = USB_SPEED_UNKNOWN;
+                else if ((hdev->parent == NULL) &&
+                                (portstatus & (1 << USB_PORT_FEAT_SUPERSPEED)))
+                        udev->speed = USB_SPEED_SUPER;
+                else
+                        udev->speed = USB_SPEED_UNKNOWN;
+
+                /*
+                 * xHCI needs to issue an address device command later
+                 * in the hub_port_init sequence for SS/HS/FS/LS devices.
+                 */
+                if (!(hcd->driver->flags & HCD_USB3)) {
+                        /* set the address */
+                        choose_address(udev);
+                        if (udev->devnum <= 0) {
+                                status = -ENOTCONN;     /* Don't retry */
+                                goto loop;
+                        }
                 }
 
-                /* reset and get descriptor */
+                /* reset (non-USB 3.0 devices) and get descriptor */
                 status = hub_port_init(hub, udev, port1, i);
                 if (status < 0)
                         goto loop;
diff --git a/drivers/usb/core/hub.h b/drivers/usb/core/hub.h
index 2a116ce53c9b..889c0f32a40b 100644
--- a/drivers/usb/core/hub.h
+++ b/drivers/usb/core/hub.h
@@ -47,7 +47,10 @@
 #define USB_PORT_FEAT_L1                5       /* L1 suspend */
 #define USB_PORT_FEAT_POWER             8
 #define USB_PORT_FEAT_LOWSPEED          9
+/* This value was never in Table 11-17 */
 #define USB_PORT_FEAT_HIGHSPEED         10
+/* This value is also fake */
+#define USB_PORT_FEAT_SUPERSPEED        11
 #define USB_PORT_FEAT_C_CONNECTION      16
 #define USB_PORT_FEAT_C_ENABLE          17
 #define USB_PORT_FEAT_C_SUSPEND         18
diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c
index b62628377654..2bed83caacb1 100644
--- a/drivers/usb/core/message.c
+++ b/drivers/usb/core/message.c
@@ -10,6 +10,7 @@
 #include <linux/mm.h>
 #include <linux/timer.h>
 #include <linux/ctype.h>
+#include <linux/nls.h>
 #include <linux/device.h>
 #include <linux/scatterlist.h>
 #include <linux/usb/quirks.h>
@@ -364,6 +365,7 @@ int usb_sg_init(struct usb_sg_request *io, struct usb_device *dev,
         int i;
         int urb_flags;
         int dma;
+        int use_sg;
 
         if (!io || !dev || !sg
                         || usb_pipecontrol(pipe)
@@ -391,7 +393,19 @@ int usb_sg_init(struct usb_sg_request *io, struct usb_device *dev,
         if (io->entries <= 0)
                 return io->entries;
 
-        io->urbs = kmalloc(io->entries * sizeof *io->urbs, mem_flags);
+        /* If we're running on an xHCI host controller, queue the whole scatter
+         * gather list with one call to urb_enqueue().  This is only for bulk,
+         * as that endpoint type does not care how the data gets broken up
+         * across frames.
+         */
+        if (usb_pipebulk(pipe) &&
+                        bus_to_hcd(dev->bus)->driver->flags & HCD_USB3) {
+                io->urbs = kmalloc(sizeof *io->urbs, mem_flags);
+                use_sg = true;
+        } else {
+                io->urbs = kmalloc(io->entries * sizeof *io->urbs, mem_flags);
+                use_sg = false;
+        }
         if (!io->urbs)
                 goto nomem;
 
@@ -401,62 +415,92 @@ int usb_sg_init(struct usb_sg_request *io, struct usb_device *dev,
         if (usb_pipein(pipe))
                 urb_flags |= URB_SHORT_NOT_OK;
 
-        for_each_sg(sg, sg, io->entries, i) {
-                unsigned len;
-
-                io->urbs[i] = usb_alloc_urb(0, mem_flags);
-                if (!io->urbs[i]) {
-                        io->entries = i;
+        if (use_sg) {
+                io->urbs[0] = usb_alloc_urb(0, mem_flags);
+                if (!io->urbs[0]) {
+                        io->entries = 0;
                         goto nomem;
                 }
 
-                io->urbs[i]->dev = NULL;
-                io->urbs[i]->pipe = pipe;
-                io->urbs[i]->interval = period;
-                io->urbs[i]->transfer_flags = urb_flags;
-
-                io->urbs[i]->complete = sg_complete;
-                io->urbs[i]->context = io;
-
-                /*
-                 * Some systems need to revert to PIO when DMA is temporarily
-                 * unavailable.  For their sakes, both transfer_buffer and
-                 * transfer_dma are set when possible.  However this can only
-                 * work on systems without:
-                 *
-                 *  - HIGHMEM, since DMA buffers located in high memory are
-                 *    not directly addressable by the CPU for PIO;
-                 *
-                 *  - IOMMU, since dma_map_sg() is allowed to use an IOMMU to
-                 *    make virtually discontiguous buffers be "dma-contiguous"
-                 *    so that PIO and DMA need diferent numbers of URBs.
-                 *
-                 * So when HIGHMEM or IOMMU are in use, transfer_buffer is NULL
-                 * to prevent stale pointers and to help spot bugs.
-                 */
-                if (dma) {
-                        io->urbs[i]->transfer_dma = sg_dma_address(sg);
-                        len = sg_dma_len(sg);
+                io->urbs[0]->dev = NULL;
+                io->urbs[0]->pipe = pipe;
+                io->urbs[0]->interval = period;
+                io->urbs[0]->transfer_flags = urb_flags;
+
+                io->urbs[0]->complete = sg_complete;
+                io->urbs[0]->context = io;
+                /* A length of zero means transfer the whole sg list */
+                io->urbs[0]->transfer_buffer_length = length;
+                if (length == 0) {
+                        for_each_sg(sg, sg, io->entries, i) {
+                                io->urbs[0]->transfer_buffer_length +=
+                                        sg_dma_len(sg);
+                        }
+                }
+                io->urbs[0]->sg = io;
+                io->urbs[0]->num_sgs = io->entries;
+                io->entries = 1;
+        } else {
+                for_each_sg(sg, sg, io->entries, i) {
+                        unsigned len;
+
+                        io->urbs[i] = usb_alloc_urb(0, mem_flags);
+                        if (!io->urbs[i]) {
+                                io->entries = i;
+                                goto nomem;
+                        }
+
+                        io->urbs[i]->dev = NULL;
+                        io->urbs[i]->pipe = pipe;
+                        io->urbs[i]->interval = period;
+                        io->urbs[i]->transfer_flags = urb_flags;
+
+                        io->urbs[i]->complete = sg_complete;
+                        io->urbs[i]->context = io;
+
+                        /*
+                         * Some systems need to revert to PIO when DMA is
+                         * temporarily unavailable.  For their sakes, both
+                         * transfer_buffer and transfer_dma are set when
+                         * possible.  However this can only work on systems
+                         * without:
+                         *
+                         *  - HIGHMEM, since DMA buffers located in high memory
+                         *    are not directly addressable by the CPU for PIO;
+                         *
+                         *  - IOMMU, since dma_map_sg() is allowed to use an
+                         *    IOMMU to make virtually discontiguous buffers be
+                         *    "dma-contiguous" so that PIO and DMA need diferent
+                         *    numbers of URBs.
+                         *
+                         * So when HIGHMEM or IOMMU are in use, transfer_buffer
+                         * is NULL to prevent stale pointers and to help spot
+                         * bugs.
+                         */
+                        if (dma) {
+                                io->urbs[i]->transfer_dma = sg_dma_address(sg);
+                                len = sg_dma_len(sg);
 #if defined(CONFIG_HIGHMEM) || defined(CONFIG_GART_IOMMU)
-                        io->urbs[i]->transfer_buffer = NULL;
+                                io->urbs[i]->transfer_buffer = NULL;
 #else
-                        io->urbs[i]->transfer_buffer = sg_virt(sg);
+                                io->urbs[i]->transfer_buffer = sg_virt(sg);
 #endif
-                } else {
-                        /* hc may use _only_ transfer_buffer */
-                        io->urbs[i]->transfer_buffer = sg_virt(sg);
-                        len = sg->length;
-                }
+                        } else {
+                                /* hc may use _only_ transfer_buffer */
+                                io->urbs[i]->transfer_buffer = sg_virt(sg);
+                                len = sg->length;
+                        }
 
-                if (length) {
-                        len = min_t(unsigned, len, length);
-                        length -= len;
-                        if (length == 0)
-                                io->entries = i + 1;
+                        if (length) {
+                                len = min_t(unsigned, len, length);
+                                length -= len;
+                                if (length == 0)
+                                        io->entries = i + 1;
+                        }
+                        io->urbs[i]->transfer_buffer_length = len;
                 }
-                io->urbs[i]->transfer_buffer_length = len;
+                io->urbs[--i]->transfer_flags &= ~URB_NO_INTERRUPT;
         }
-        io->urbs[--i]->transfer_flags &= ~URB_NO_INTERRUPT;
 
         /* transaction state */
         io->count = io->entries;
@@ -509,6 +553,10 @@ EXPORT_SYMBOL_GPL(usb_sg_init);
  * could be transferred.  That capability is less useful for low or full
  * speed interrupt endpoints, which allow at most one packet per millisecond,
  * of at most 8 or 64 bytes (respectively).
+ *
+ * It is not necessary to call this function to reserve bandwidth for devices
+ * under an xHCI host controller, as the bandwidth is reserved when the
+ * configuration or interface alt setting is selected.
  */
 void usb_sg_wait(struct usb_sg_request *io)
 {
@@ -759,7 +807,7 @@ static int usb_string_sub(struct usb_device *dev, unsigned int langid,
 }
 
 /**
- * usb_string - returns ISO 8859-1 version of a string descriptor
+ * usb_string - returns UTF-8 version of a string descriptor
  * @dev: the device whose string descriptor is being retrieved
  * @index: the number of the descriptor
  * @buf: where to put the string
@@ -767,17 +815,10 @@ static int usb_string_sub(struct usb_device *dev, unsigned int langid,
  * Context: !in_interrupt ()
  *
  * This converts the UTF-16LE encoded strings returned by devices, from
- * usb_get_string_descriptor(), to null-terminated ISO-8859-1 encoded ones
- * that are more usable in most kernel contexts.  Note that all characters
- * in the chosen descriptor that can't be encoded using ISO-8859-1
- * are converted to the question mark ("?") character, and this function
+ * usb_get_string_descriptor(), to null-terminated UTF-8 encoded ones
+ * that are more usable in most kernel contexts.  Note that this function
  * chooses strings in the first language supported by the device.
  *
- * The ASCII (or, redundantly, "US-ASCII") character set is the seven-bit
- * subset of ISO 8859-1. ISO-8859-1 is the eight-bit subset of Unicode,
- * and is appropriate for use many uses of English and several other
- * Western European languages.  (But it doesn't include the "Euro" symbol.)
- *
  * This call is synchronous, and may not be used in an interrupt context.
  *
  * Returns length of the string (>= 0) or usb_control_msg status (< 0).
@@ -786,7 +827,6 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size)
 {
         unsigned char *tbuf;
         int err;
-        unsigned int u, idx;
 
         if (dev->state == USB_STATE_SUSPENDED)
                 return -EHOSTUNREACH;
@@ -821,16 +861,9 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size)
                 goto errout;
 
         size--;         /* leave room for trailing NULL char in output buffer */
-        for (idx = 0, u = 2; u < err; u += 2) {
-                if (idx >= size)
-                        break;
-                if (tbuf[u+1])                  /* high byte */
-                        buf[idx++] = '?';  /* non ISO-8859-1 character */
-                else
-                        buf[idx++] = tbuf[u];
-        }
-        buf[idx] = 0;
-        err = idx;
+        err = utf16s_to_utf8s((wchar_t *) &tbuf[2], (err - 2) / 2,
+                        UTF16_LITTLE_ENDIAN, buf, size);
+        buf[err] = 0;
 
         if (tbuf[1] != USB_DT_STRING)
                 dev_dbg(&dev->dev,
@@ -843,6 +876,9 @@ int usb_string(struct usb_device *dev, int index, char *buf, size_t size)
 }
 EXPORT_SYMBOL_GPL(usb_string);
 
+/* one UTF-8-encoded 16-bit character has at most three bytes */
+#define MAX_USB_STRING_SIZE (127 * 3 + 1)
+
 /**
  * usb_cache_string - read a string descriptor and cache it for later use
  * @udev: the device whose string descriptor is being read
@@ -860,9 +896,9 @@ char *usb_cache_string(struct usb_device *udev, int index)
         if (index <= 0)
                 return NULL;
 
-        buf = kmalloc(256, GFP_KERNEL);
+        buf = kmalloc(MAX_USB_STRING_SIZE, GFP_KERNEL);
         if (buf) {
-                len = usb_string(udev, index, buf, 256);
+                len = usb_string(udev, index, buf, MAX_USB_STRING_SIZE);
                 if (len > 0) {
                         smallbuf = kmalloc(++len, GFP_KERNEL);
                         if (!smallbuf)
@@ -1664,6 +1700,21 @@ free_interfaces:
         if (ret)
                 goto free_interfaces;
 
+        /* Make sure we have bandwidth (and available HCD resources) for this
+         * configuration.  Remove endpoints from the schedule if we're dropping
+         * this configuration to set configuration 0.  After this point, the
+         * host controller will not allow submissions to dropped endpoints.  If
+         * this call fails, the device state is unchanged.
+         */
+        if (cp)
+                ret = usb_hcd_check_bandwidth(dev, cp, NULL);
+        else
+                ret = usb_hcd_check_bandwidth(dev, NULL, NULL);
+        if (ret < 0) {
+                usb_autosuspend_device(dev);
+                goto free_interfaces;
+        }
+
         /* if it's already configured, clear out old state first.
          * getting rid of old interfaces means unbinding their drivers.
          */
@@ -1686,6 +1737,7 @@ free_interfaces:
         dev->actconfig = cp;
         if (!cp) {
                 usb_set_device_state(dev, USB_STATE_ADDRESS);
+                usb_hcd_check_bandwidth(dev, NULL, NULL);
                 usb_autosuspend_device(dev);
                 goto free_interfaces;
         }
diff --git a/drivers/usb/core/sysfs.c b/drivers/usb/core/sysfs.c
index c66789197927..b5c72e458943 100644
--- a/drivers/usb/core/sysfs.c
+++ b/drivers/usb/core/sysfs.c
@@ -552,8 +552,8 @@ static struct attribute *dev_string_attrs[] = {
 static mode_t dev_string_attrs_are_visible(struct kobject *kobj,
                 struct attribute *a, int n)
 {
-        struct usb_device *udev = to_usb_device(
-                        container_of(kobj, struct device, kobj));
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct usb_device *udev = to_usb_device(dev);
 
         if (a == &dev_attr_manufacturer.attr) {
                 if (udev->manufacturer == NULL)
@@ -585,8 +585,8 @@ static ssize_t
 read_descriptors(struct kobject *kobj, struct bin_attribute *attr,
                 char *buf, loff_t off, size_t count)
 {
-        struct usb_device *udev = to_usb_device(
-                        container_of(kobj, struct device, kobj));
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct usb_device *udev = to_usb_device(dev);
         size_t nleft = count;
         size_t srclen, n;
         int cfgno;
@@ -786,8 +786,8 @@ static struct attribute *intf_assoc_attrs[] = {
 static mode_t intf_assoc_attrs_are_visible(struct kobject *kobj,
                 struct attribute *a, int n)
 {
-        struct usb_interface *intf = to_usb_interface(
-                        container_of(kobj, struct device, kobj));
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct usb_interface *intf = to_usb_interface(dev);
 
         if (intf->intf_assoc == NULL)
                 return 0;
diff --git a/drivers/usb/core/urb.c b/drivers/usb/core/urb.c
index 3376055f36e7..0885d4abdc62 100644
--- a/drivers/usb/core/urb.c
+++ b/drivers/usb/core/urb.c
@@ -241,6 +241,12 @@ EXPORT_SYMBOL_GPL(usb_unanchor_urb);
  * If the USB subsystem can't allocate sufficient bandwidth to perform
  * the periodic request, submitting such a periodic request should fail.
  *
+ * For devices under xHCI, the bandwidth is reserved at configuration time, or
+ * when the alt setting is selected.  If there is not enough bus bandwidth, the
+ * configuration/alt setting request will fail.  Therefore, submissions to
+ * periodic endpoints on devices under xHCI should never fail due to bandwidth
+ * constraints.
+ *
  * Device drivers must explicitly request that repetition, by ensuring that
  * some URB is always on the endpoint's queue (except possibly for short
  * periods during completion callacks).  When there is no longer an urb
@@ -351,6 +357,7 @@ int usb_submit_urb(struct urb *urb, gfp_t mem_flags)
         if (xfertype == USB_ENDPOINT_XFER_ISOC) {
                 int     n, len;
 
+                /* FIXME SuperSpeed isoc endpoints have up to 16 bursts */
                 /* "high bandwidth" mode, 1-3 packets/uframe? */
                 if (dev->speed == USB_SPEED_HIGH) {
                         int     mult = 1 + ((max >> 11) & 0x03);
@@ -426,6 +433,11 @@ int usb_submit_urb(struct urb *urb, gfp_t mem_flags)
                         return -EINVAL;
                 /* too big? */
                 switch (dev->speed) {
+                case USB_SPEED_SUPER:   /* units are 125us */
+                        /* Handle up to 2^(16-1) microframes */
+                        if (urb->interval > (1 << 15))
+                                return -EINVAL;
+                        max = 1 << 15;
                 case USB_SPEED_HIGH:    /* units are microframes */
                         /* NOTE usb handles 2^15 */
                         if (urb->interval > (1024 * 8))
diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c
index 7eee400d3e32..a26f73880c32 100644
--- a/drivers/usb/core/usb.c
+++ b/drivers/usb/core/usb.c
@@ -34,6 +34,7 @@
 #include <linux/usb.h>
 #include <linux/mutex.h>
 #include <linux/workqueue.h>
+#include <linux/debugfs.h>
 
 #include <asm/io.h>
 #include <linux/scatterlist.h>
@@ -139,8 +140,7 @@ static int __find_interface(struct device *dev, void *data)
         struct find_interface_arg *arg = data;
         struct usb_interface *intf;
 
-        /* can't look at usb devices, only interfaces */
-        if (is_usb_device(dev))
+        if (!is_usb_interface(dev))
                 return 0;
 
         intf = to_usb_interface(dev);
@@ -184,11 +184,16 @@ EXPORT_SYMBOL_GPL(usb_find_interface);
 static void usb_release_dev(struct device *dev)
 {
         struct usb_device *udev;
+        struct usb_hcd *hcd;
 
         udev = to_usb_device(dev);
+        hcd = bus_to_hcd(udev->bus);
 
         usb_destroy_configuration(udev);
-        usb_put_hcd(bus_to_hcd(udev->bus));
+        /* Root hubs aren't real devices, so don't free HCD resources */
+        if (hcd->driver->free_dev && udev->parent)
+                hcd->driver->free_dev(hcd, udev);
+        usb_put_hcd(hcd);
         kfree(udev->product);
         kfree(udev->manufacturer);
         kfree(udev->serial);
@@ -305,10 +310,21 @@ static struct dev_pm_ops usb_device_pm_ops = {
 
 #endif  /* CONFIG_PM */
 
+
+static char *usb_nodename(struct device *dev)
+{
+        struct usb_device *usb_dev;
+
+        usb_dev = to_usb_device(dev);
+        return kasprintf(GFP_KERNEL, "bus/usb/%03d/%03d",
+                         usb_dev->bus->busnum, usb_dev->devnum);
+}
+
 struct device_type usb_device_type = {
         .name =         "usb_device",
         .release =      usb_release_dev,
         .uevent =       usb_dev_uevent,
+        .nodename =     usb_nodename,
         .pm =           &usb_device_pm_ops,
 };
 
@@ -348,6 +364,13 @@ struct usb_device *usb_alloc_dev(struct usb_device *parent,
                 kfree(dev);
                 return NULL;
         }
+        /* Root hubs aren't true devices, so don't allocate HCD resources */
+        if (usb_hcd->driver->alloc_dev && parent &&
+                !usb_hcd->driver->alloc_dev(usb_hcd, dev)) {
+                usb_put_hcd(bus_to_hcd(bus));
+                kfree(dev);
+                return NULL;
+        }
 
         device_initialize(&dev->dev);
         dev->dev.bus = &usb_bus_type;
@@ -375,18 +398,24 @@ struct usb_device *usb_alloc_dev(struct usb_device *parent,
          */
         if (unlikely(!parent)) {
                 dev->devpath[0] = '0';
+                dev->route = 0;
 
                 dev->dev.parent = bus->controller;
                 dev_set_name(&dev->dev, "usb%d", bus->busnum);
                 root_hub = 1;
         } else {
                 /* match any labeling on the hubs; it's one-based */
-                if (parent->devpath[0] == '0')
+                if (parent->devpath[0] == '0') {
                         snprintf(dev->devpath, sizeof dev->devpath,
                                 "%d", port1);
-                else
+                        /* Root ports are not counted in route string */
+                        dev->route = 0;
+                } else {
                         snprintf(dev->devpath, sizeof dev->devpath,
                                 "%s.%d", parent->devpath, port1);
+                        dev->route = parent->route +
+                                (port1 << ((parent->level - 1)*4));
+                }
 
                 dev->dev.parent = &parent->dev;
                 dev_set_name(&dev->dev, "%d-%s", bus->busnum, dev->devpath);
@@ -799,12 +828,12 @@ void usb_buffer_dmasync(struct urb *urb)
                 return;
 
         if (controller->dma_mask) {
-                dma_sync_single(controller,
+                dma_sync_single_for_cpu(controller,
                         urb->transfer_dma, urb->transfer_buffer_length,
                         usb_pipein(urb->pipe)
                                 ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
                 if (usb_pipecontrol(urb->pipe))
-                        dma_sync_single(controller,
+                        dma_sync_single_for_cpu(controller,
                                         urb->setup_dma,
                                         sizeof(struct usb_ctrlrequest),
                                         DMA_TO_DEVICE);
@@ -922,8 +951,8 @@ void usb_buffer_dmasync_sg(const struct usb_device *dev, int is_in,
                         || !controller->dma_mask)
                 return;
 
-        dma_sync_sg(controller, sg, n_hw_ents,
-                        is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
+        dma_sync_sg_for_cpu(controller, sg, n_hw_ents,
+                            is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
 }
 EXPORT_SYMBOL_GPL(usb_buffer_dmasync_sg);
 #endif
@@ -1001,6 +1030,35 @@ static struct notifier_block usb_bus_nb = {
         .notifier_call = usb_bus_notify,
 };
 
+struct dentry *usb_debug_root;
+EXPORT_SYMBOL_GPL(usb_debug_root);
+
+struct dentry *usb_debug_devices;
+
+static int usb_debugfs_init(void)
+{
+        usb_debug_root = debugfs_create_dir("usb", NULL);
+        if (!usb_debug_root)
+                return -ENOENT;
+
+        usb_debug_devices = debugfs_create_file("devices", 0444,
+                                                usb_debug_root, NULL,
+                                                &usbfs_devices_fops);
+        if (!usb_debug_devices) {
+                debugfs_remove(usb_debug_root);
+                usb_debug_root = NULL;
+                return -ENOENT;
+        }
+
+        return 0;
+}
+
+static void usb_debugfs_cleanup(void)
+{
+        debugfs_remove(usb_debug_devices);
+        debugfs_remove(usb_debug_root);
+}
+
 /*
  * Init
  */
@@ -1012,6 +1070,10 @@ static int __init usb_init(void)
                 return 0;
         }
 
+        retval = usb_debugfs_init();
+        if (retval)
+                goto out;
+
         retval = ksuspend_usb_init();
         if (retval)
                 goto out;
@@ -1021,9 +1083,6 @@ static int __init usb_init(void)
         retval = bus_register_notifier(&usb_bus_type, &usb_bus_nb);
         if (retval)
                 goto bus_notifier_failed;
-        retval = usb_host_init();
-        if (retval)
-                goto host_init_failed;
         retval = usb_major_init();
         if (retval)
                 goto major_init_failed;
@@ -1053,8 +1112,6 @@ usb_devio_init_failed:
 driver_register_failed:
         usb_major_cleanup();
 major_init_failed:
-        usb_host_cleanup();
-host_init_failed:
         bus_unregister_notifier(&usb_bus_type, &usb_bus_nb);
 bus_notifier_failed:
         bus_unregister(&usb_bus_type);
@@ -1079,10 +1136,10 @@ static void __exit usb_exit(void)
         usb_deregister(&usbfs_driver);
         usb_devio_cleanup();
         usb_hub_cleanup();
-        usb_host_cleanup();
         bus_unregister_notifier(&usb_bus_type, &usb_bus_nb);
         bus_unregister(&usb_bus_type);
         ksuspend_usb_cleanup();
+        usb_debugfs_cleanup();
 }
 
 subsys_initcall(usb_init);
diff --git a/drivers/usb/core/usb.h b/drivers/usb/core/usb.h
index 79d8a9ea559b..e2a8cfaade1d 100644
--- a/drivers/usb/core/usb.h
+++ b/drivers/usb/core/usb.h
@@ -41,8 +41,6 @@ extern int  usb_hub_init(void);
 extern void usb_hub_cleanup(void);
 extern int usb_major_init(void);
 extern void usb_major_cleanup(void);
-extern int usb_host_init(void);
-extern void usb_host_cleanup(void);
 
 #ifdef  CONFIG_PM
 
@@ -106,6 +104,7 @@ extern struct workqueue_struct *ksuspend_usb_wq;
 extern struct bus_type usb_bus_type;
 extern struct device_type usb_device_type;
 extern struct device_type usb_if_device_type;
+extern struct device_type usb_ep_device_type;
 extern struct usb_device_driver usb_generic_driver;
 
 static inline int is_usb_device(const struct device *dev)
@@ -113,6 +112,16 @@ static inline int is_usb_device(const struct device *dev)
         return dev->type == &usb_device_type;
 }
 
+static inline int is_usb_interface(const struct device *dev)
+{
+        return dev->type == &usb_if_device_type;
+}
+
+static inline int is_usb_endpoint(const struct device *dev)
+{
+        return dev->type == &usb_ep_device_type;
+}
+
 /* Do the same for device drivers and interface drivers. */
 
 static inline int is_usb_device_driver(struct device_driver *drv)
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 080bb1e4b847..5d1ddf485d1e 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -156,7 +156,7 @@ config USB_ATMEL_USBA
 
 config USB_GADGET_FSL_USB2
         boolean "Freescale Highspeed USB DR Peripheral Controller"
-        depends on FSL_SOC
+        depends on FSL_SOC || ARCH_MXC
         select USB_GADGET_DUALSPEED
         help
            Some of Freescale PowerPC processors have a High Speed
@@ -253,7 +253,7 @@ config USB_PXA25X_SMALL
 
 config USB_GADGET_PXA27X
         boolean "PXA 27x"
-        depends on ARCH_PXA && PXA27x
+        depends on ARCH_PXA && (PXA27x || PXA3xx)
         select USB_OTG_UTILS
         help
            Intel's PXA 27x series XScale ARM v5TE processors include
@@ -272,6 +272,20 @@ config USB_PXA27X
         default USB_GADGET
         select USB_GADGET_SELECTED
 
+config USB_GADGET_S3C_HSOTG
+        boolean "S3C HS/OtG USB Device controller"
+        depends on S3C_DEV_USB_HSOTG
+        select USB_GADGET_S3C_HSOTG_PIO
+        help
+          The Samsung S3C64XX USB2.0 high-speed gadget controller
+          integrated into the S3C64XX series SoC.
+
+config USB_S3C_HSOTG
+        tristate
+        depends on USB_GADGET_S3C_HSOTG
+        default USB_GADGET
+        select USB_GADGET_SELECTED
+
 config USB_GADGET_S3C2410
         boolean "S3C2410 USB Device Controller"
         depends on ARCH_S3C2410
@@ -460,6 +474,27 @@ config USB_GOKU
         default USB_GADGET
         select USB_GADGET_SELECTED
 
+config USB_GADGET_LANGWELL
+        boolean "Intel Langwell USB Device Controller"
+        depends on PCI
+        select USB_GADGET_DUALSPEED
+        help
+           Intel Langwell USB Device Controller is a High-Speed USB
+           On-The-Go device controller.
+
+           The number of programmable endpoints is different through
+           controller revision.
+
+           Say "y" to link the driver statically, or "m" to build a
+           dynamically linked module called "langwell_udc" and force all
+           gadget drivers to also be dynamically linked.
+
+config USB_LANGWELL
+        tristate
+        depends on USB_GADGET_LANGWELL
+        default USB_GADGET
+        select USB_GADGET_SELECTED
+
 
 #
 # LAST -- dummy/emulated controller
@@ -566,6 +601,20 @@ config USB_ZERO_HNPTEST
           the "B-Peripheral" role, that device will use HNP to let this
           one serve as the USB host instead (in the "B-Host" role).
 
+config USB_AUDIO
+        tristate "Audio Gadget (EXPERIMENTAL)"
+        depends on SND
+        help
+          Gadget Audio is compatible with USB Audio Class specification 1.0.
+          It will include at least one AudioControl interface, zero or more
+          AudioStream interface and zero or more MIDIStream interface.
+
+          Gadget Audio will use on-board ALSA (CONFIG_SND) audio card to
+          playback or capture audio stream.
+
+          Say "y" to link the driver statically, or "m" to build a
+          dynamically linked module called "g_audio".
+
 config USB_ETH
         tristate "Ethernet Gadget (with CDC Ethernet support)"
         depends on NET
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 39a51d746cb7..e6017e6bf6da 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -18,14 +18,21 @@ obj-$(CONFIG_USB_S3C2410)	+= s3c2410_udc.o
 obj-$(CONFIG_USB_AT91)          += at91_udc.o
 obj-$(CONFIG_USB_ATMEL_USBA)    += atmel_usba_udc.o
 obj-$(CONFIG_USB_FSL_USB2)      += fsl_usb2_udc.o
+fsl_usb2_udc-objs               := fsl_udc_core.o
+ifeq ($(CONFIG_ARCH_MXC),y)
+fsl_usb2_udc-objs               += fsl_mx3_udc.o
+endif
 obj-$(CONFIG_USB_M66592)        += m66592-udc.o
 obj-$(CONFIG_USB_FSL_QE)        += fsl_qe_udc.o
 obj-$(CONFIG_USB_CI13XXX)       += ci13xxx_udc.o
+obj-$(CONFIG_USB_S3C_HSOTG)     += s3c-hsotg.o
+obj-$(CONFIG_USB_LANGWELL)      += langwell_udc.o
 
 #
 # USB gadget drivers
 #
 g_zero-objs                     := zero.o
+g_audio-objs                    := audio.o
 g_ether-objs                    := ether.o
 g_serial-objs                   := serial.o
 g_midi-objs                     := gmidi.o
@@ -35,6 +42,7 @@ g_printer-objs			:= printer.o
 g_cdc-objs                      := cdc2.o
 
 obj-$(CONFIG_USB_ZERO)          += g_zero.o
+obj-$(CONFIG_USB_AUDIO)         += g_audio.o
 obj-$(CONFIG_USB_ETH)           += g_ether.o
 obj-$(CONFIG_USB_GADGETFS)      += gadgetfs.o
 obj-$(CONFIG_USB_FILE_STORAGE)  += g_file_storage.o
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 0b2bb8f0706d..72bae8f39d81 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -485,7 +485,7 @@ static int at91_ep_enable(struct usb_ep *_ep,
                 return -ESHUTDOWN;
         }
 
-        tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+        tmp = usb_endpoint_type(desc);
         switch (tmp) {
         case USB_ENDPOINT_XFER_CONTROL:
                 DBG("only one control endpoint\n");
@@ -517,7 +517,7 @@ ok:
         local_irq_save(flags);
 
         /* initialize endpoint to match this descriptor */
-        ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
+        ep->is_in = usb_endpoint_dir_in(desc);
         ep->is_iso = (tmp == USB_ENDPOINT_XFER_ISOC);
         ep->stopped = 0;
         if (ep->is_in)
@@ -1574,7 +1574,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver)
 
         udc->driver = driver;
         udc->gadget.dev.driver = &driver->driver;
-        udc->gadget.dev.driver_data = &driver->driver;
+        dev_set_drvdata(&udc->gadget.dev, &driver->driver);
         udc->enabled = 1;
         udc->selfpowered = 1;
 
@@ -1583,7 +1583,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver)
                 DBG("driver->bind() returned %d\n", retval);
                 udc->driver = NULL;
                 udc->gadget.dev.driver = NULL;
-                udc->gadget.dev.driver_data = NULL;
+                dev_set_drvdata(&udc->gadget.dev, NULL);
                 udc->enabled = 0;
                 udc->selfpowered = 0;
                 return retval;
@@ -1613,7 +1613,7 @@ int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
 
         driver->unbind(&udc->gadget);
         udc->gadget.dev.driver = NULL;
-        udc->gadget.dev.driver_data = NULL;
+        dev_set_drvdata(&udc->gadget.dev, NULL);
         udc->driver = NULL;
 
         DBG("unbound from %s\n", driver->driver.name);
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index 05c913cc3658..4e970cf0e29a 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -326,13 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
         return 1;
 }
 
-#if defined(CONFIG_AVR32)
-
-static void toggle_bias(int is_on)
-{
-}
-
-#elif defined(CONFIG_ARCH_AT91)
+#if defined(CONFIG_ARCH_AT91SAM9RL)
 
 #include <mach/at91_pmc.h>
 
@@ -346,7 +340,13 @@ static void toggle_bias(int is_on)
                 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(AT91_PMC_BIASEN));
 }
 
-#endif /* CONFIG_ARCH_AT91 */
+#else
+
+static void toggle_bias(int is_on)
+{
+}
+
+#endif /* CONFIG_ARCH_AT91SAM9RL */
 
 static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
 {
@@ -550,12 +550,12 @@ usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
         DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
                         ep->ep.name, ept_cfg, maxpacket);
 
-        if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
+        if (usb_endpoint_dir_in(desc)) {
                 ep->is_in = 1;
                 ept_cfg |= USBA_EPT_DIR_IN;
         }
 
-        switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
+        switch (usb_endpoint_type(desc)) {
         case USB_ENDPOINT_XFER_CONTROL:
                 ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
                 ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
diff --git a/drivers/usb/gadget/audio.c b/drivers/usb/gadget/audio.c
new file mode 100644
index 000000000000..94de7e864614
--- /dev/null
+++ b/drivers/usb/gadget/audio.c
@@ -0,0 +1,302 @@
+/*
+ * audio.c -- Audio gadget driver
+ *
+ * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
+ * Copyright (C) 2008 Analog Devices, Inc
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+/* #define VERBOSE_DEBUG */
+
+#include <linux/kernel.h>
+#include <linux/utsname.h>
+
+#include "u_audio.h"
+
+#define DRIVER_DESC             "Linux USB Audio Gadget"
+#define DRIVER_VERSION          "Dec 18, 2008"
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * Kbuild is not very cooperative with respect to linking separately
+ * compiled library objects into one module.  So for now we won't use
+ * separate compilation ... ensuring init/exit sections work to shrink
+ * the runtime footprint, and giving us at least some parts of what
+ * a "gcc --combine ... part1.c part2.c part3.c ... " build would.
+ */
+#include "composite.c"
+#include "usbstring.c"
+#include "config.c"
+#include "epautoconf.c"
+
+#include "u_audio.c"
+#include "f_audio.c"
+
+/*-------------------------------------------------------------------------*/
+
+/* DO NOT REUSE THESE IDs with a protocol-incompatible driver!!  Ever!!
+ * Instead:  allocate your own, using normal USB-IF procedures.
+ */
+
+/* Thanks to NetChip Technologies for donating this product ID. */
+#define AUDIO_VENDOR_NUM                0x0525  /* NetChip */
+#define AUDIO_PRODUCT_NUM               0xa4a1  /* Linux-USB Audio Gadget */
+
+/*-------------------------------------------------------------------------*/
+
+static struct usb_device_descriptor device_desc = {
+        .bLength =              sizeof device_desc,
+        .bDescriptorType =      USB_DT_DEVICE,
+
+        .bcdUSB =               __constant_cpu_to_le16(0x200),
+
+        .bDeviceClass =         USB_CLASS_PER_INTERFACE,
+        .bDeviceSubClass =      0,
+        .bDeviceProtocol =      0,
+        /* .bMaxPacketSize0 = f(hardware) */
+
+        /* Vendor and product id defaults change according to what configs
+         * we support.  (As does bNumConfigurations.)  These values can
+         * also be overridden by module parameters.
+         */
+        .idVendor =             __constant_cpu_to_le16(AUDIO_VENDOR_NUM),
+        .idProduct =            __constant_cpu_to_le16(AUDIO_PRODUCT_NUM),
+        /* .bcdDevice = f(hardware) */
+        /* .iManufacturer = DYNAMIC */
+        /* .iProduct = DYNAMIC */
+        /* NO SERIAL NUMBER */
+        .bNumConfigurations =   1,
+};
+
+static struct usb_otg_descriptor otg_descriptor = {
+        .bLength =              sizeof otg_descriptor,
+        .bDescriptorType =      USB_DT_OTG,
+
+        /* REVISIT SRP-only hardware is possible, although
+         * it would not be called "OTG" ...
+         */
+        .bmAttributes =         USB_OTG_SRP | USB_OTG_HNP,
+};
+
+static const struct usb_descriptor_header *otg_desc[] = {
+        (struct usb_descriptor_header *) &otg_descriptor,
+        NULL,
+};
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * Handle USB audio endpoint set/get command in setup class request
+ */
+
+static int audio_set_endpoint_req(struct usb_configuration *c,
+                const struct usb_ctrlrequest *ctrl)
+{
+        struct usb_composite_dev *cdev = c->cdev;
+        int                     value = -EOPNOTSUPP;
+        u16                     ep = le16_to_cpu(ctrl->wIndex);
+        u16                     len = le16_to_cpu(ctrl->wLength);
+        u16                     w_value = le16_to_cpu(ctrl->wValue);
+
+        DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, endpoint %d\n",
+                        ctrl->bRequest, w_value, len, ep);
+
+        switch (ctrl->bRequest) {
+        case SET_CUR:
+                value = 0;
+                break;
+
+        case SET_MIN:
+                break;
+
+        case SET_MAX:
+                break;
+
+        case SET_RES:
+                break;
+
+        case SET_MEM:
+                break;
+
+        default:
+                break;
+        }
+
+        return value;
+}
+
+static int audio_get_endpoint_req(struct usb_configuration *c,
+                const struct usb_ctrlrequest *ctrl)
+{
+        struct usb_composite_dev *cdev = c->cdev;
+        int value = -EOPNOTSUPP;
+        u8 ep = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF);
+        u16 len = le16_to_cpu(ctrl->wLength);
+        u16 w_value = le16_to_cpu(ctrl->wValue);
+
+        DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, endpoint %d\n",
+                        ctrl->bRequest, w_value, len, ep);
+
+        switch (ctrl->bRequest) {
+        case GET_CUR:
+        case GET_MIN:
+        case GET_MAX:
+        case GET_RES:
+                value = 3;
+                break;
+        case GET_MEM:
+                break;
+        default:
+                break;
+        }
+
+        return value;
+}
+
+static int
+audio_setup(struct usb_configuration *c, const struct usb_ctrlrequest *ctrl)
+{
+        struct usb_composite_dev *cdev = c->cdev;
+        struct usb_request *req = cdev->req;
+        int value = -EOPNOTSUPP;
+        u16 w_index = le16_to_cpu(ctrl->wIndex);
+        u16 w_value = le16_to_cpu(ctrl->wValue);
+        u16 w_length = le16_to_cpu(ctrl->wLength);
+
+        /* composite driver infrastructure handles everything except
+         * Audio class messages; interface activation uses set_alt().
+         */
+        switch (ctrl->bRequestType) {
+        case USB_AUDIO_SET_ENDPOINT:
+                value = audio_set_endpoint_req(c, ctrl);
+                break;
+
+        case USB_AUDIO_GET_ENDPOINT:
+                value = audio_get_endpoint_req(c, ctrl);
+                break;
+
+        default:
+                ERROR(cdev, "Invalid control req%02x.%02x v%04x i%04x l%d\n",
+                        ctrl->bRequestType, ctrl->bRequest,
+                        w_value, w_index, w_length);
+        }
+
+        /* respond with data transfer or status phase? */
+        if (value >= 0) {
+                DBG(cdev, "Audio req%02x.%02x v%04x i%04x l%d\n",
+                        ctrl->bRequestType, ctrl->bRequest,
+                        w_value, w_index, w_length);
+                req->zero = 0;
+                req->length = value;
+                value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC);
+                if (value < 0)
+                        ERROR(cdev, "Audio response on err %d\n", value);
+        }
+
+        /* device either stalls (value < 0) or reports success */
+        return value;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int __init audio_do_config(struct usb_configuration *c)
+{
+        /* FIXME alloc iConfiguration string, set it in c->strings */
+
+        if (gadget_is_otg(c->cdev->gadget)) {
+                c->descriptors = otg_desc;
+                c->bmAttributes |= USB_CONFIG_ATT_WAKEUP;
+        }
+
+        audio_bind_config(c);
+
+        return 0;
+}
+
+static struct usb_configuration audio_config_driver = {
+        .label                  = DRIVER_DESC,
+        .bind                   = audio_do_config,
+        .setup                  = audio_setup,
+        .bConfigurationValue    = 1,
+        /* .iConfiguration = DYNAMIC */
+        .bmAttributes           = USB_CONFIG_ATT_SELFPOWER,
+};
+
+/*-------------------------------------------------------------------------*/
+
+static int __init audio_bind(struct usb_composite_dev *cdev)
+{
+        int                     gcnum;
+        int                     status;
+
+        gcnum = usb_gadget_controller_number(cdev->gadget);
+        if (gcnum >= 0)
+                device_desc.bcdDevice = cpu_to_le16(0x0300 | gcnum);
+        else {
+                ERROR(cdev, "controller '%s' not recognized; trying %s\n",
+                        cdev->gadget->name,
+                        audio_config_driver.label);
+                device_desc.bcdDevice =
+                        __constant_cpu_to_le16(0x0300 | 0x0099);
+        }
+
+        /* device descriptor strings: manufacturer, product */
+        snprintf(manufacturer, sizeof manufacturer, "%s %s with %s",
+                init_utsname()->sysname, init_utsname()->release,
+                cdev->gadget->name);
+        status = usb_string_id(cdev);
+        if (status < 0)
+                goto fail;
+        strings_dev[STRING_MANUFACTURER_IDX].id = status;
+        device_desc.iManufacturer = status;
+
+        status = usb_string_id(cdev);
+        if (status < 0)
+                goto fail;
+        strings_dev[STRING_PRODUCT_IDX].id = status;
+        device_desc.iProduct = status;
+
+        status = usb_add_config(cdev, &audio_config_driver);
+        if (status < 0)
+                goto fail;
+
+        INFO(cdev, "%s, version: %s\n", DRIVER_DESC, DRIVER_VERSION);
+        return 0;
+
+fail:
+        return status;
+}
+
+static int __exit audio_unbind(struct usb_composite_dev *cdev)
+{
+        return 0;
+}
+
+static struct usb_composite_driver audio_driver = {
+        .name           = "g_audio",
+        .dev            = &device_desc,
+        .strings        = audio_strings,
+        .bind           = audio_bind,
+        .unbind         = __exit_p(audio_unbind),
+};
+
+static int __init init(void)
+{
+        return usb_composite_register(&audio_driver);
+}
+module_init(init);
+
+static void __exit cleanup(void)
+{
+        usb_composite_unregister(&audio_driver);
+}
+module_exit(cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR("Bryan Wu <cooloney@kernel.org>");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index 38e531ecae4d..c7cb87a6fee2 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -1977,9 +1977,9 @@ static int ep_enable(struct usb_ep *ep,
         if (!list_empty(&mEp->qh[mEp->dir].queue))
                 warn("enabling a non-empty endpoint!");
 
-        mEp->dir  = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? TX : RX;
-        mEp->num  =  desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
-        mEp->type =  desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+        mEp->dir  = usb_endpoint_dir_in(desc) ? TX : RX;
+        mEp->num  = usb_endpoint_num(desc);
+        mEp->type = usb_endpoint_type(desc);
 
         mEp->ep.maxpacket = __constant_le16_to_cpu(desc->wMaxPacketSize);
 
diff --git a/drivers/usb/gadget/f_audio.c b/drivers/usb/gadget/f_audio.c
new file mode 100644
index 000000000000..66527ba2d2ea
--- /dev/null
+++ b/drivers/usb/gadget/f_audio.c
@@ -0,0 +1,707 @@
+/*
+ * f_audio.c -- USB Audio class function driver
+  *
+ * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
+ * Copyright (C) 2008 Analog Devices, Inc
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <asm/atomic.h>
+
+#include "u_audio.h"
+
+#define OUT_EP_MAX_PACKET_SIZE  200
+static int req_buf_size = OUT_EP_MAX_PACKET_SIZE;
+module_param(req_buf_size, int, S_IRUGO);
+MODULE_PARM_DESC(req_buf_size, "ISO OUT endpoint request buffer size");
+
+static int req_count = 256;
+module_param(req_count, int, S_IRUGO);
+MODULE_PARM_DESC(req_count, "ISO OUT endpoint request count");
+
+static int audio_buf_size = 48000;
+module_param(audio_buf_size, int, S_IRUGO);
+MODULE_PARM_DESC(audio_buf_size, "Audio buffer size");
+
+/*
+ * DESCRIPTORS ... most are static, but strings and full
+ * configuration descriptors are built on demand.
+ */
+
+/*
+ * We have two interfaces- AudioControl and AudioStreaming
+ * TODO: only supcard playback currently
+ */
+#define F_AUDIO_AC_INTERFACE    0
+#define F_AUDIO_AS_INTERFACE    1
+#define F_AUDIO_NUM_INTERFACES  2
+
+/* B.3.1  Standard AC Interface Descriptor */
+static struct usb_interface_descriptor ac_interface_desc __initdata = {
+        .bLength =              USB_DT_INTERFACE_SIZE,
+        .bDescriptorType =      USB_DT_INTERFACE,
+        .bNumEndpoints =        0,
+        .bInterfaceClass =      USB_CLASS_AUDIO,
+        .bInterfaceSubClass =   USB_SUBCLASS_AUDIOCONTROL,
+};
+
+DECLARE_USB_AC_HEADER_DESCRIPTOR(2);
+
+#define USB_DT_AC_HEADER_LENGH  USB_DT_AC_HEADER_SIZE(F_AUDIO_NUM_INTERFACES)
+/* B.3.2  Class-Specific AC Interface Descriptor */
+static struct usb_ac_header_descriptor_2 ac_header_desc = {
+        .bLength =              USB_DT_AC_HEADER_LENGH,
+        .bDescriptorType =      USB_DT_CS_INTERFACE,
+        .bDescriptorSubtype =   HEADER,
+        .bcdADC =               __constant_cpu_to_le16(0x0100),
+        .wTotalLength =         __constant_cpu_to_le16(USB_DT_AC_HEADER_LENGH),
+        .bInCollection =        F_AUDIO_NUM_INTERFACES,
+        .baInterfaceNr = {
+                [0] =           F_AUDIO_AC_INTERFACE,
+                [1] =           F_AUDIO_AS_INTERFACE,
+        }
+};
+
+#define INPUT_TERMINAL_ID       1
+static struct usb_input_terminal_descriptor input_terminal_desc = {
+        .bLength =              USB_DT_AC_INPUT_TERMINAL_SIZE,
+        .bDescriptorType =      USB_DT_CS_INTERFACE,
+        .bDescriptorSubtype =   INPUT_TERMINAL,
+        .bTerminalID =          INPUT_TERMINAL_ID,
+        .wTerminalType =        USB_AC_TERMINAL_STREAMING,
+        .bAssocTerminal =       0,
+        .wChannelConfig =       0x3,
+};
+
+DECLARE_USB_AC_FEATURE_UNIT_DESCRIPTOR(0);
+
+#define FEATURE_UNIT_ID         2
+static struct usb_ac_feature_unit_descriptor_0 feature_unit_desc = {
+        .bLength                = USB_DT_AC_FEATURE_UNIT_SIZE(0),
+        .bDescriptorType        = USB_DT_CS_INTERFACE,
+        .bDescriptorSubtype     = FEATURE_UNIT,
+        .bUnitID                = FEATURE_UNIT_ID,
+        .bSourceID              = INPUT_TERMINAL_ID,
+        .bControlSize           = 2,
+        .bmaControls[0]         = (FU_MUTE | FU_VOLUME),
+};
+
+static struct usb_audio_control mute_control = {
+        .list = LIST_HEAD_INIT(mute_control.list),
+        .name = "Mute Control",
+        .type = MUTE_CONTROL,
+        /* Todo: add real Mute control code */
+        .set = generic_set_cmd,
+        .get = generic_get_cmd,
+};
+
+static struct usb_audio_control volume_control = {
+        .list = LIST_HEAD_INIT(volume_control.list),
+        .name = "Volume Control",
+        .type = VOLUME_CONTROL,
+        /* Todo: add real Volume control code */
+        .set = generic_set_cmd,
+        .get = generic_get_cmd,
+};
+
+static struct usb_audio_control_selector feature_unit = {
+        .list = LIST_HEAD_INIT(feature_unit.list),
+        .id = FEATURE_UNIT_ID,
+        .name = "Mute & Volume Control",
+        .type = FEATURE_UNIT,
+        .desc = (struct usb_descriptor_header *)&feature_unit_desc,
+};
+
+#define OUTPUT_TERMINAL_ID      3
+static struct usb_output_terminal_descriptor output_terminal_desc = {
+        .bLength                = USB_DT_AC_OUTPUT_TERMINAL_SIZE,
+        .bDescriptorType        = USB_DT_CS_INTERFACE,
+        .bDescriptorSubtype     = OUTPUT_TERMINAL,
+        .bTerminalID            = OUTPUT_TERMINAL_ID,
+        .wTerminalType          = USB_AC_OUTPUT_TERMINAL_SPEAKER,
+        .bAssocTerminal         = FEATURE_UNIT_ID,
+        .bSourceID              = FEATURE_UNIT_ID,
+};
+
+/* B.4.1  Standard AS Interface Descriptor */
+static struct usb_interface_descriptor as_interface_alt_0_desc = {
+        .bLength =              USB_DT_INTERFACE_SIZE,
+        .bDescriptorType =      USB_DT_INTERFACE,
+        .bAlternateSetting =    0,
+        .bNumEndpoints =        0,
+        .bInterfaceClass =      USB_CLASS_AUDIO,
+        .bInterfaceSubClass =   USB_SUBCLASS_AUDIOSTREAMING,
+};
+
+static struct usb_interface_descriptor as_interface_alt_1_desc = {
+        .bLength =              USB_DT_INTERFACE_SIZE,
+        .bDescriptorType =      USB_DT_INTERFACE,
+        .bAlternateSetting =    1,
+        .bNumEndpoints =        1,
+        .bInterfaceClass =      USB_CLASS_AUDIO,
+        .bInterfaceSubClass =   USB_SUBCLASS_AUDIOSTREAMING,
+};
+
+/* B.4.2  Class-Specific AS Interface Descriptor */
+static struct usb_as_header_descriptor as_header_desc = {
+        .bLength =              USB_DT_AS_HEADER_SIZE,
+        .bDescriptorType =      USB_DT_CS_INTERFACE,
+        .bDescriptorSubtype =   AS_GENERAL,
+        .bTerminalLink =        INPUT_TERMINAL_ID,
+        .bDelay =               1,
+        .wFormatTag =           USB_AS_AUDIO_FORMAT_TYPE_I_PCM,
+};
+
+DECLARE_USB_AS_FORMAT_TYPE_I_DISCRETE_DESC(1);
+
+static struct usb_as_formate_type_i_discrete_descriptor_1 as_type_i_desc = {
+        .bLength =              USB_AS_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(1),
+        .bDescriptorType =      USB_DT_CS_INTERFACE,
+        .bDescriptorSubtype =   FORMAT_TYPE,
+        .bFormatType =          USB_AS_FORMAT_TYPE_I,
+        .bSubframeSize =        2,
+        .bBitResolution =       16,
+        .bSamFreqType =         1,
+};
+
+/* Standard ISO OUT Endpoint Descriptor */
+static struct usb_endpoint_descriptor as_out_ep_desc __initdata = {
+        .bLength =              USB_DT_ENDPOINT_AUDIO_SIZE,
+        .bDescriptorType =      USB_DT_ENDPOINT,
+        .bEndpointAddress =     USB_DIR_OUT,
+        .bmAttributes =         USB_AS_ENDPOINT_ADAPTIVE
+                                | USB_ENDPOINT_XFER_ISOC,
+        .wMaxPacketSize =       __constant_cpu_to_le16(OUT_EP_MAX_PACKET_SIZE),
+        .bInterval =            4,
+};
+
+/* Class-specific AS ISO OUT Endpoint Descriptor */
+static struct usb_as_iso_endpoint_descriptor as_iso_out_desc __initdata = {
+        .bLength =              USB_AS_ISO_ENDPOINT_DESC_SIZE,
+        .bDescriptorType =      USB_DT_CS_ENDPOINT,
+        .bDescriptorSubtype =   EP_GENERAL,
+        .bmAttributes =         1,
+        .bLockDelayUnits =      1,
+        .wLockDelay =           __constant_cpu_to_le16(1),
+};
+
+static struct usb_descriptor_header *f_audio_desc[] __initdata = {
+        (struct usb_descriptor_header *)&ac_interface_desc,
+        (struct usb_descriptor_header *)&ac_header_desc,
+
+        (struct usb_descriptor_header *)&input_terminal_desc,
+        (struct usb_descriptor_header *)&output_terminal_desc,
+        (struct usb_descriptor_header *)&feature_unit_desc,
+
+        (struct usb_descriptor_header *)&as_interface_alt_0_desc,
+        (struct usb_descriptor_header *)&as_interface_alt_1_desc,
+        (struct usb_descriptor_header *)&as_header_desc,
+
+        (struct usb_descriptor_header *)&as_type_i_desc,
+
+        (struct usb_descriptor_header *)&as_out_ep_desc,
+        (struct usb_descriptor_header *)&as_iso_out_desc,
+        NULL,
+};
+
+/* string IDs are assigned dynamically */
+
+#define STRING_MANUFACTURER_IDX         0
+#define STRING_PRODUCT_IDX              1
+
+static char manufacturer[50];
+
+static struct usb_string strings_dev[] = {
+        [STRING_MANUFACTURER_IDX].s = manufacturer,
+        [STRING_PRODUCT_IDX].s = DRIVER_DESC,
+        {  } /* end of list */
+};
+
+static struct usb_gadget_strings stringtab_dev = {
+        .language       = 0x0409,       /* en-us */
+        .strings        = strings_dev,
+};
+
+static struct usb_gadget_strings *audio_strings[] = {
+        &stringtab_dev,
+        NULL,
+};
+
+/*
+ * This function is an ALSA sound card following USB Audio Class Spec 1.0.
+ */
+
+/*-------------------------------------------------------------------------*/
+struct f_audio_buf {
+        u8 *buf;
+        int actual;
+        struct list_head list;
+};
+
+static struct f_audio_buf *f_audio_buffer_alloc(int buf_size)
+{
+        struct f_audio_buf *copy_buf;
+
+        copy_buf = kzalloc(sizeof *copy_buf, GFP_ATOMIC);
+        if (!copy_buf)
+                return (struct f_audio_buf *)-ENOMEM;
+
+        copy_buf->buf = kzalloc(buf_size, GFP_ATOMIC);
+        if (!copy_buf->buf) {
+                kfree(copy_buf);
+                return (struct f_audio_buf *)-ENOMEM;
+        }
+
+        return copy_buf;
+}
+
+static void f_audio_buffer_free(struct f_audio_buf *audio_buf)
+{
+        kfree(audio_buf->buf);
+        kfree(audio_buf);
+}
+/*-------------------------------------------------------------------------*/
+
+struct f_audio {
+        struct gaudio                   card;
+
+        /* endpoints handle full and/or high speeds */
+        struct usb_ep                   *out_ep;
+        struct usb_endpoint_descriptor  *out_desc;
+
+        spinlock_t                      lock;
+        struct f_audio_buf *copy_buf;
+        struct work_struct playback_work;
+        struct list_head play_queue;
+
+        /* Control Set command */
+        struct list_head cs;
+        u8 set_cmd;
+        struct usb_audio_control *set_con;
+};
+
+static inline struct f_audio *func_to_audio(struct usb_function *f)
+{
+        return container_of(f, struct f_audio, card.func);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void f_audio_playback_work(struct work_struct *data)
+{
+        struct f_audio *audio = container_of(data, struct f_audio,
+                                        playback_work);
+        struct f_audio_buf *play_buf;
+
+        spin_lock_irq(&audio->lock);
+        if (list_empty(&audio->play_queue)) {
+                spin_unlock_irq(&audio->lock);
+                return;
+        }
+        play_buf = list_first_entry(&audio->play_queue,
+                        struct f_audio_buf, list);
+        list_del(&play_buf->list);
+        spin_unlock_irq(&audio->lock);
+
+        u_audio_playback(&audio->card, play_buf->buf, play_buf->actual);
+        f_audio_buffer_free(play_buf);
+
+        return;
+}
+
+static int f_audio_out_ep_complete(struct usb_ep *ep, struct usb_request *req)
+{
+        struct f_audio *audio = req->context;
+        struct usb_composite_dev *cdev = audio->card.func.config->cdev;
+        struct f_audio_buf *copy_buf = audio->copy_buf;
+        int err;
+
+        if (!copy_buf)
+                return -EINVAL;
+
+        /* Copy buffer is full, add it to the play_queue */
+        if (audio_buf_size - copy_buf->actual < req->actual) {
+                list_add_tail(&copy_buf->list, &audio->play_queue);
+                schedule_work(&audio->playback_work);
+                copy_buf = f_audio_buffer_alloc(audio_buf_size);
+                if (copy_buf < 0)
+                        return -ENOMEM;
+        }
+
+        memcpy(copy_buf->buf + copy_buf->actual, req->buf, req->actual);
+        copy_buf->actual += req->actual;
+        audio->copy_buf = copy_buf;
+
+        err = usb_ep_queue(ep, req, GFP_ATOMIC);
+        if (err)
+                ERROR(cdev, "%s queue req: %d\n", ep->name, err);
+
+        return 0;
+
+}
+
+static void f_audio_complete(struct usb_ep *ep, struct usb_request *req)
+{
+        struct f_audio *audio = req->context;
+        int status = req->status;
+        u32 data = 0;
+        struct usb_ep *out_ep = audio->out_ep;
+
+        switch (status) {
+
+        case 0:                         /* normal completion? */
+                if (ep == out_ep)
+                        f_audio_out_ep_complete(ep, req);
+                else if (audio->set_con) {
+                        memcpy(&data, req->buf, req->length);
+                        audio->set_con->set(audio->set_con, audio->set_cmd,
+                                        le16_to_cpu(data));
+                        audio->set_con = NULL;
+                }
+                break;
+        default:
+                break;
+        }
+}
+
+static int audio_set_intf_req(struct usb_function *f,
+                const struct usb_ctrlrequest *ctrl)
+{
+        struct f_audio          *audio = func_to_audio(f);
+        struct usb_composite_dev *cdev = f->config->cdev;
+        struct usb_request      *req = cdev->req;
+        u8                      id = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF);
+        u16                     len = le16_to_cpu(ctrl->wLength);
+        u16                     w_value = le16_to_cpu(ctrl->wValue);
+        u8                      con_sel = (w_value >> 8) & 0xFF;
+        u8                      cmd = (ctrl->bRequest & 0x0F);
+        struct usb_audio_control_selector *cs;
+        struct usb_audio_control *con;
+
+        DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, entity %d\n",
+                        ctrl->bRequest, w_value, len, id);
+
+        list_for_each_entry(cs, &audio->cs, list) {
+                if (cs->id == id) {
+                        list_for_each_entry(con, &cs->control, list) {
+                                if (con->type == con_sel) {
+                                        audio->set_con = con;
+                                        break;
+                                }
+                        }
+                        break;
+                }
+        }
+
+        audio->set_cmd = cmd;
+        req->context = audio;
+        req->complete = f_audio_complete;
+
+        return len;
+}
+
+static int audio_get_intf_req(struct usb_function *f,
+                const struct usb_ctrlrequest *ctrl)
+{
+        struct f_audio          *audio = func_to_audio(f);
+        struct usb_composite_dev *cdev = f->config->cdev;
+        struct usb_request      *req = cdev->req;
+        int                     value = -EOPNOTSUPP;
+        u8                      id = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF);
+        u16                     len = le16_to_cpu(ctrl->wLength);
+        u16                     w_value = le16_to_cpu(ctrl->wValue);
+        u8                      con_sel = (w_value >> 8) & 0xFF;
+        u8                      cmd = (ctrl->bRequest & 0x0F);
+        struct usb_audio_control_selector *cs;
+        struct usb_audio_control *con;
+
+        DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, entity %d\n",
+                        ctrl->bRequest, w_value, len, id);
+
+        list_for_each_entry(cs, &audio->cs, list) {
+                if (cs->id == id) {
+                        list_for_each_entry(con, &cs->control, list) {
+                                if (con->type == con_sel && con->get) {
+                                        value = con->get(con, cmd);
+                                        break;
+                                }
+                        }
+                        break;
+                }
+        }
+
+        req->context = audio;
+        req->complete = f_audio_complete;
+        memcpy(req->buf, &value, len);
+
+        return len;
+}
+
+static int
+f_audio_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl)
+{
+        struct usb_composite_dev *cdev = f->config->cdev;
+        struct usb_request      *req = cdev->req;
+        int                     value = -EOPNOTSUPP;
+        u16                     w_index = le16_to_cpu(ctrl->wIndex);
+        u16                     w_value = le16_to_cpu(ctrl->wValue);
+        u16                     w_length = le16_to_cpu(ctrl->wLength);
+
+        /* composite driver infrastructure handles everything except
+         * Audio class messages; interface activation uses set_alt().
+         */
+        switch (ctrl->bRequestType) {
+        case USB_AUDIO_SET_INTF:
+                value = audio_set_intf_req(f, ctrl);
+                break;
+
+        case USB_AUDIO_GET_INTF:
+                value = audio_get_intf_req(f, ctrl);
+                break;
+
+        default:
+                ERROR(cdev, "invalid control req%02x.%02x v%04x i%04x l%d\n",
+                        ctrl->bRequestType, ctrl->bRequest,
+                        w_value, w_index, w_length);
+        }
+
+        /* respond with data transfer or status phase? */
+        if (value >= 0) {
+                DBG(cdev, "audio req%02x.%02x v%04x i%04x l%d\n",
+                        ctrl->bRequestType, ctrl->bRequest,
+                        w_value, w_index, w_length);
+                req->zero = 0;
+                req->length = value;
+                value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC);
+                if (value < 0)
+                        ERROR(cdev, "audio response on err %d\n", value);
+        }
+
+        /* device either stalls (value < 0) or reports success */
+        return value;
+}
+
+static int f_audio_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
+{
+        struct f_audio          *audio = func_to_audio(f);
+        struct usb_composite_dev *cdev = f->config->cdev;
+        struct usb_ep *out_ep = audio->out_ep;
+        struct usb_request *req;
+        int i = 0, err = 0;
+
+        DBG(cdev, "intf %d, alt %d\n", intf, alt);
+
+        if (intf == 1) {
+                if (alt == 1) {
+                        usb_ep_enable(out_ep, audio->out_desc);
+                        out_ep->driver_data = audio;
+                        audio->copy_buf = f_audio_buffer_alloc(audio_buf_size);
+
+                        /*
+                         * allocate a bunch of read buffers
+                         * and queue them all at once.
+                         */
+                        for (i = 0; i < req_count && err == 0; i++) {
+                                req = usb_ep_alloc_request(out_ep, GFP_ATOMIC);
+                                if (req) {
+                                        req->buf = kzalloc(req_buf_size,
+                                                        GFP_ATOMIC);
+                                        if (req->buf) {
+                                                req->length = req_buf_size;
+                                                req->context = audio;
+                                                req->complete =
+                                                        f_audio_complete;
+                                                err = usb_ep_queue(out_ep,
+                                                        req, GFP_ATOMIC);
+                                                if (err)
+                                                        ERROR(cdev,
+                                                        "%s queue req: %d\n",
+                                                        out_ep->name, err);
+                                        } else
+                                                err = -ENOMEM;
+                                } else
+                                        err = -ENOMEM;
+                        }
+
+                } else {
+                        struct f_audio_buf *copy_buf = audio->copy_buf;
+                        if (copy_buf) {
+                                list_add_tail(&copy_buf->list,
+                                                &audio->play_queue);
+                                schedule_work(&audio->playback_work);
+                        }
+                }
+        }
+
+        return err;
+}
+
+static void f_audio_disable(struct usb_function *f)
+{
+        return;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static void f_audio_build_desc(struct f_audio *audio)
+{
+        struct gaudio *card = &audio->card;
+        u8 *sam_freq;
+        int rate;
+
+        /* Set channel numbers */
+        input_terminal_desc.bNrChannels = u_audio_get_playback_channels(card);
+        as_type_i_desc.bNrChannels = u_audio_get_playback_channels(card);
+
+        /* Set sample rates */
+        rate = u_audio_get_playback_rate(card);
+        sam_freq = as_type_i_desc.tSamFreq[0];
+        memcpy(sam_freq, &rate, 3);
+
+        /* Todo: Set Sample bits and other parameters */
+
+        return;
+}
+
+/* audio function driver setup/binding */
+static int __init
+f_audio_bind(struct usb_configuration *c, struct usb_function *f)
+{
+        struct usb_composite_dev *cdev = c->cdev;
+        struct f_audio          *audio = func_to_audio(f);
+        int                     status;
+        struct usb_ep           *ep;
+
+        f_audio_build_desc(audio);
+
+        /* allocate instance-specific interface IDs, and patch descriptors */
+        status = usb_interface_id(c, f);
+        if (status < 0)
+                goto fail;
+        ac_interface_desc.bInterfaceNumber = status;
+
+        status = usb_interface_id(c, f);
+        if (status < 0)
+                goto fail;
+        as_interface_alt_0_desc.bInterfaceNumber = status;
+        as_interface_alt_1_desc.bInterfaceNumber = status;
+
+        status = -ENODEV;
+
+        /* allocate instance-specific endpoints */
+        ep = usb_ep_autoconfig(cdev->gadget, &as_out_ep_desc);
+        if (!ep)
+                goto fail;
+        audio->out_ep = ep;
+        ep->driver_data = cdev; /* claim */
+
+        status = -ENOMEM;
+
+        /* supcard all relevant hardware speeds... we expect that when
+         * hardware is dual speed, all bulk-capable endpoints work at
+         * both speeds
+         */
+
+        /* copy descriptors, and track endpoint copies */
+        if (gadget_is_dualspeed(c->cdev->gadget)) {
+                c->highspeed = true;
+                f->hs_descriptors = usb_copy_descriptors(f_audio_desc);
+        } else
+                f->descriptors = usb_copy_descriptors(f_audio_desc);
+
+        return 0;
+
+fail:
+
+        return status;
+}
+
+static void
+f_audio_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+        struct f_audio          *audio = func_to_audio(f);
+
+        usb_free_descriptors(f->descriptors);
+        kfree(audio);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Todo: add more control selecotor dynamically */
+int __init control_selector_init(struct f_audio *audio)
+{
+        INIT_LIST_HEAD(&audio->cs);
+        list_add(&feature_unit.list, &audio->cs);
+
+        INIT_LIST_HEAD(&feature_unit.control);
+        list_add(&mute_control.list, &feature_unit.control);
+        list_add(&volume_control.list, &feature_unit.control);
+
+        volume_control.data[_CUR] = 0xffc0;
+        volume_control.data[_MIN] = 0xe3a0;
+        volume_control.data[_MAX] = 0xfff0;
+        volume_control.data[_RES] = 0x0030;
+
+        return 0;
+}
+
+/**
+ * audio_bind_config - add USB audio fucntion to a configuration
+ * @c: the configuration to supcard the USB audio function
+ * Context: single threaded during gadget setup
+ *
+ * Returns zero on success, else negative errno.
+ */
+int __init audio_bind_config(struct usb_configuration *c)
+{
+        struct f_audio *audio;
+        int status;
+
+        /* allocate and initialize one new instance */
+        audio = kzalloc(sizeof *audio, GFP_KERNEL);
+        if (!audio)
+                return -ENOMEM;
+
+        audio->card.func.name = "g_audio";
+        audio->card.gadget = c->cdev->gadget;
+
+        INIT_LIST_HEAD(&audio->play_queue);
+        spin_lock_init(&audio->lock);
+
+        /* set up ASLA audio devices */
+        status = gaudio_setup(&audio->card);
+        if (status < 0)
+                goto setup_fail;
+
+        audio->card.func.strings = audio_strings;
+        audio->card.func.bind = f_audio_bind;
+        audio->card.func.unbind = f_audio_unbind;
+        audio->card.func.set_alt = f_audio_set_alt;
+        audio->card.func.setup = f_audio_setup;
+        audio->card.func.disable = f_audio_disable;
+        audio->out_desc = &as_out_ep_desc;
+
+        control_selector_init(audio);
+
+        INIT_WORK(&audio->playback_work, f_audio_playback_work);
+
+        status = usb_add_function(c, &audio->card.func);
+        if (status)
+                goto add_fail;
+
+        INFO(c->cdev, "audio_buf_size %d, req_buf_size %d, req_count %d\n",
+                audio_buf_size, req_buf_size, req_count);
+
+        return status;
+
+add_fail:
+        gaudio_cleanup(&audio->card);
+setup_fail:
+        kfree(audio);
+        return status;
+}
diff --git a/drivers/usb/gadget/f_rndis.c b/drivers/usb/gadget/f_rndis.c
index 3279a4726042..424a37c5773f 100644
--- a/drivers/usb/gadget/f_rndis.c
+++ b/drivers/usb/gadget/f_rndis.c
@@ -475,7 +475,9 @@ static int rndis_set_alt(struct usb_function *f, unsigned intf, unsigned alt)
                 if (rndis->port.in_ep->driver_data) {
                         DBG(cdev, "reset rndis\n");
                         gether_disconnect(&rndis->port);
-                } else {
+                }
+
+                if (!rndis->port.in) {
                         DBG(cdev, "init rndis\n");
                         rndis->port.in = ep_choose(cdev->gadget,
                                         rndis->hs.in, rndis->fs.in);
diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
index 381a53b3e11c..1e6aa504d58a 100644
--- a/drivers/usb/gadget/file_storage.c
+++ b/drivers/usb/gadget/file_storage.c
@@ -248,6 +248,8 @@
 #include <linux/freezer.h>
 #include <linux/utsname.h>
 
+#include <asm/unaligned.h>
+
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 
@@ -799,29 +801,9 @@ static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep)
 
 /* Routines for unaligned data access */
 
-static u16 get_be16(u8 *buf)
-{
-        return ((u16) buf[0] << 8) | ((u16) buf[1]);
-}
-
-static u32 get_be32(u8 *buf)
-{
-        return ((u32) buf[0] << 24) | ((u32) buf[1] << 16) |
-                        ((u32) buf[2] << 8) | ((u32) buf[3]);
-}
-
-static void put_be16(u8 *buf, u16 val)
-{
-        buf[0] = val >> 8;
-        buf[1] = val;
-}
-
-static void put_be32(u8 *buf, u32 val)
+static u32 get_unaligned_be24(u8 *buf)
 {
-        buf[0] = val >> 24;
-        buf[1] = val >> 16;
-        buf[2] = val >> 8;
-        buf[3] = val & 0xff;
+        return 0xffffff & (u32) get_unaligned_be32(buf - 1);
 }
 
 
@@ -1582,9 +1564,9 @@ static int do_read(struct fsg_dev *fsg)
         /* Get the starting Logical Block Address and check that it's
          * not too big */
         if (fsg->cmnd[0] == SC_READ_6)
-                lba = (fsg->cmnd[1] << 16) | get_be16(&fsg->cmnd[2]);
+                lba = get_unaligned_be24(&fsg->cmnd[1]);
         else {
-                lba = get_be32(&fsg->cmnd[2]);
+                lba = get_unaligned_be32(&fsg->cmnd[2]);
 
                 /* We allow DPO (Disable Page Out = don't save data in the
                  * cache) and FUA (Force Unit Access = don't read from the
@@ -1717,9 +1699,9 @@ static int do_write(struct fsg_dev *fsg)
         /* Get the starting Logical Block Address and check that it's
          * not too big */
         if (fsg->cmnd[0] == SC_WRITE_6)
-                lba = (fsg->cmnd[1] << 16) | get_be16(&fsg->cmnd[2]);
+                lba = get_unaligned_be24(&fsg->cmnd[1]);
         else {
-                lba = get_be32(&fsg->cmnd[2]);
+                lba = get_unaligned_be32(&fsg->cmnd[2]);
 
                 /* We allow DPO (Disable Page Out = don't save data in the
                  * cache) and FUA (Force Unit Access = write directly to the
@@ -1940,7 +1922,7 @@ static int do_verify(struct fsg_dev *fsg)
 
         /* Get the starting Logical Block Address and check that it's
          * not too big */
-        lba = get_be32(&fsg->cmnd[2]);
+        lba = get_unaligned_be32(&fsg->cmnd[2]);
         if (lba >= curlun->num_sectors) {
                 curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
                 return -EINVAL;
@@ -1953,7 +1935,7 @@ static int do_verify(struct fsg_dev *fsg)
                 return -EINVAL;
         }
 
-        verification_length = get_be16(&fsg->cmnd[7]);
+        verification_length = get_unaligned_be16(&fsg->cmnd[7]);
         if (unlikely(verification_length == 0))
                 return -EIO;            // No default reply
 
@@ -2103,7 +2085,7 @@ static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
         memset(buf, 0, 18);
         buf[0] = valid | 0x70;                  // Valid, current error
         buf[2] = SK(sd);
-        put_be32(&buf[3], sdinfo);              // Sense information
+        put_unaligned_be32(sdinfo, &buf[3]);    /* Sense information */
         buf[7] = 18 - 8;                        // Additional sense length
         buf[12] = ASC(sd);
         buf[13] = ASCQ(sd);
@@ -2114,7 +2096,7 @@ static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
 static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
 {
         struct lun      *curlun = fsg->curlun;
-        u32             lba = get_be32(&fsg->cmnd[2]);
+        u32             lba = get_unaligned_be32(&fsg->cmnd[2]);
         int             pmi = fsg->cmnd[8];
         u8              *buf = (u8 *) bh->buf;
 
@@ -2124,8 +2106,9 @@ static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh)
                 return -EINVAL;
         }
 
-        put_be32(&buf[0], curlun->num_sectors - 1);     // Max logical block
-        put_be32(&buf[4], 512);                         // Block length
+        put_unaligned_be32(curlun->num_sectors - 1, &buf[0]);
+                                                /* Max logical block */
+        put_unaligned_be32(512, &buf[4]);       /* Block length */
         return 8;
 }
 
@@ -2144,7 +2127,7 @@ static void store_cdrom_address(u8 *dest, int msf, u32 addr)
                 dest[0] = 0;            /* Reserved */
         } else {
                 /* Absolute sector */
-                put_be32(dest, addr);
+                put_unaligned_be32(addr, dest);
         }
 }
 
@@ -2152,7 +2135,7 @@ static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh)
 {
         struct lun      *curlun = fsg->curlun;
         int             msf = fsg->cmnd[1] & 0x02;
-        u32             lba = get_be32(&fsg->cmnd[2]);
+        u32             lba = get_unaligned_be32(&fsg->cmnd[2]);
         u8              *buf = (u8 *) bh->buf;
 
         if ((fsg->cmnd[1] & ~0x02) != 0) {              /* Mask away MSF */
@@ -2252,10 +2235,13 @@ static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
                         buf[2] = 0x04;  // Write cache enable,
                                         // Read cache not disabled
                                         // No cache retention priorities
-                        put_be16(&buf[4], 0xffff);  // Don't disable prefetch
-                                        // Minimum prefetch = 0
-                        put_be16(&buf[8], 0xffff);  // Maximum prefetch
-                        put_be16(&buf[10], 0xffff); // Maximum prefetch ceiling
+                        put_unaligned_be16(0xffff, &buf[4]);
+                                        /* Don't disable prefetch */
+                                        /* Minimum prefetch = 0 */
+                        put_unaligned_be16(0xffff, &buf[8]);
+                                        /* Maximum prefetch */
+                        put_unaligned_be16(0xffff, &buf[10]);
+                                        /* Maximum prefetch ceiling */
                 }
                 buf += 12;
         }
@@ -2272,7 +2258,7 @@ static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh)
         if (mscmnd == SC_MODE_SENSE_6)
                 buf0[0] = len - 1;
         else
-                put_be16(buf0, len - 2);
+                put_unaligned_be16(len - 2, buf0);
         return len;
 }
 
@@ -2360,9 +2346,10 @@ static int do_read_format_capacities(struct fsg_dev *fsg,
         buf[3] = 8;             // Only the Current/Maximum Capacity Descriptor
         buf += 4;
 
-        put_be32(&buf[0], curlun->num_sectors);         // Number of blocks
-        put_be32(&buf[4], 512);                         // Block length
-        buf[4] = 0x02;                                  // Current capacity
+        put_unaligned_be32(curlun->num_sectors, &buf[0]);
+                                                /* Number of blocks */
+        put_unaligned_be32(512, &buf[4]);       /* Block length */
+        buf[4] = 0x02;                          /* Current capacity */
         return 12;
 }
 
@@ -2882,7 +2869,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
                 break;
 
         case SC_MODE_SELECT_10:
-                fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+                fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
                 if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
                                 (1<<1) | (3<<7), 0,
                                 "MODE SELECT(10)")) == 0)
@@ -2898,7 +2885,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
                 break;
 
         case SC_MODE_SENSE_10:
-                fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+                fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
                 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
                                 (1<<1) | (1<<2) | (3<<7), 0,
                                 "MODE SENSE(10)")) == 0)
@@ -2923,7 +2910,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
                 break;
 
         case SC_READ_10:
-                fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]) << 9;
+                fsg->data_size_from_cmnd =
+                                get_unaligned_be16(&fsg->cmnd[7]) << 9;
                 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
                                 (1<<1) | (0xf<<2) | (3<<7), 1,
                                 "READ(10)")) == 0)
@@ -2931,7 +2919,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
                 break;
 
         case SC_READ_12:
-                fsg->data_size_from_cmnd = get_be32(&fsg->cmnd[6]) << 9;
+                fsg->data_size_from_cmnd =
+                                get_unaligned_be32(&fsg->cmnd[6]) << 9;
                 if ((reply = check_command(fsg, 12, DATA_DIR_TO_HOST,
                                 (1<<1) | (0xf<<2) | (0xf<<6), 1,
                                 "READ(12)")) == 0)
@@ -2949,7 +2938,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
         case SC_READ_HEADER:
                 if (!mod_data.cdrom)
                         goto unknown_cmnd;
-                fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+                fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
                 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
                                 (3<<7) | (0x1f<<1), 1,
                                 "READ HEADER")) == 0)
@@ -2959,7 +2948,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
         case SC_READ_TOC:
                 if (!mod_data.cdrom)
                         goto unknown_cmnd;
-                fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+                fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
                 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
                                 (7<<6) | (1<<1), 1,
                                 "READ TOC")) == 0)
@@ -2967,7 +2956,7 @@ static int do_scsi_command(struct fsg_dev *fsg)
                 break;
 
         case SC_READ_FORMAT_CAPACITIES:
-                fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]);
+                fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]);
                 if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST,
                                 (3<<7), 1,
                                 "READ FORMAT CAPACITIES")) == 0)
@@ -3025,7 +3014,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
                 break;
 
         case SC_WRITE_10:
-                fsg->data_size_from_cmnd = get_be16(&fsg->cmnd[7]) << 9;
+                fsg->data_size_from_cmnd =
+                                get_unaligned_be16(&fsg->cmnd[7]) << 9;
                 if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST,
                                 (1<<1) | (0xf<<2) | (3<<7), 1,
                                 "WRITE(10)")) == 0)
@@ -3033,7 +3023,8 @@ static int do_scsi_command(struct fsg_dev *fsg)
                 break;
 
         case SC_WRITE_12:
-                fsg->data_size_from_cmnd = get_be32(&fsg->cmnd[6]) << 9;
+                fsg->data_size_from_cmnd =
+                                get_unaligned_be32(&fsg->cmnd[6]) << 9;
                 if ((reply = check_command(fsg, 12, DATA_DIR_FROM_HOST,
                                 (1<<1) | (0xf<<2) | (0xf<<6), 1,
                                 "WRITE(12)")) == 0)
diff --git a/drivers/usb/gadget/fsl_mx3_udc.c b/drivers/usb/gadget/fsl_mx3_udc.c
new file mode 100644
index 000000000000..4bc2bf3d602e
--- /dev/null
+++ b/drivers/usb/gadget/fsl_mx3_udc.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * Description:
+ * Helper routines for i.MX3x SoCs from Freescale, needed by the fsl_usb2_udc.c
+ * driver to function correctly on these systems.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/fsl_devices.h>
+#include <linux/platform_device.h>
+
+static struct clk *mxc_ahb_clk;
+static struct clk *mxc_usb_clk;
+
+int fsl_udc_clk_init(struct platform_device *pdev)
+{
+        struct fsl_usb2_platform_data *pdata;
+        unsigned long freq;
+        int ret;
+
+        pdata = pdev->dev.platform_data;
+
+        mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb");
+        if (IS_ERR(mxc_ahb_clk))
+                return PTR_ERR(mxc_ahb_clk);
+
+        ret = clk_enable(mxc_ahb_clk);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n");
+                goto eenahb;
+        }
+
+        /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */
+        mxc_usb_clk = clk_get(&pdev->dev, "usb");
+        if (IS_ERR(mxc_usb_clk)) {
+                dev_err(&pdev->dev, "clk_get(\"usb\") failed\n");
+                ret = PTR_ERR(mxc_usb_clk);
+                goto egusb;
+        }
+
+        freq = clk_get_rate(mxc_usb_clk);
+        if (pdata->phy_mode != FSL_USB2_PHY_ULPI &&
+            (freq < 59999000 || freq > 60001000)) {
+                dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq);
+                goto eclkrate;
+        }
+
+        ret = clk_enable(mxc_usb_clk);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "clk_enable(\"usb_clk\") failed\n");
+                goto eenusb;
+        }
+
+        return 0;
+
+eenusb:
+eclkrate:
+        clk_put(mxc_usb_clk);
+        mxc_usb_clk = NULL;
+egusb:
+        clk_disable(mxc_ahb_clk);
+eenahb:
+        clk_put(mxc_ahb_clk);
+        return ret;
+}
+
+void fsl_udc_clk_finalize(struct platform_device *pdev)
+{
+        struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+        /* ULPI transceivers don't need usbpll */
+        if (pdata->phy_mode == FSL_USB2_PHY_ULPI) {
+                clk_disable(mxc_usb_clk);
+                clk_put(mxc_usb_clk);
+                mxc_usb_clk = NULL;
+        }
+}
+
+void fsl_udc_clk_release(void)
+{
+        if (mxc_usb_clk) {
+                clk_disable(mxc_usb_clk);
+                clk_put(mxc_usb_clk);
+        }
+        clk_disable(mxc_ahb_clk);
+        clk_put(mxc_ahb_clk);
+}
diff --git a/drivers/usb/gadget/fsl_usb2_udc.c b/drivers/usb/gadget/fsl_udc_core.c
index 9d7b95d4e3d2..42a74b8a0bb8 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -38,6 +38,7 @@
 #include <linux/platform_device.h>
 #include <linux/fsl_devices.h>
 #include <linux/dmapool.h>
+#include <linux/delay.h>
 
 #include <asm/byteorder.h>
 #include <asm/io.h>
@@ -57,7 +58,9 @@ static const char driver_name[] = "fsl-usb2-udc";
 static const char driver_desc[] = DRIVER_DESC;
 
 static struct usb_dr_device *dr_regs;
+#ifndef CONFIG_ARCH_MXC
 static struct usb_sys_interface *usb_sys_regs;
+#endif
 
 /* it is initialized in probe()  */
 static struct fsl_udc *udc_controller = NULL;
@@ -174,10 +177,34 @@ static void nuke(struct fsl_ep *ep, int status)
 
 static int dr_controller_setup(struct fsl_udc *udc)
 {
-        unsigned int tmp = 0, portctrl = 0, ctrl = 0;
+        unsigned int tmp, portctrl;
+#ifndef CONFIG_ARCH_MXC
+        unsigned int ctrl;
+#endif
         unsigned long timeout;
 #define FSL_UDC_RESET_TIMEOUT 1000
 
+        /* Config PHY interface */
+        portctrl = fsl_readl(&dr_regs->portsc1);
+        portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
+        switch (udc->phy_mode) {
+        case FSL_USB2_PHY_ULPI:
+                portctrl |= PORTSCX_PTS_ULPI;
+                break;
+        case FSL_USB2_PHY_UTMI_WIDE:
+                portctrl |= PORTSCX_PTW_16BIT;
+                /* fall through */
+        case FSL_USB2_PHY_UTMI:
+                portctrl |= PORTSCX_PTS_UTMI;
+                break;
+        case FSL_USB2_PHY_SERIAL:
+                portctrl |= PORTSCX_PTS_FSLS;
+                break;
+        default:
+                return -EINVAL;
+        }
+        fsl_writel(portctrl, &dr_regs->portsc1);
+
         /* Stop and reset the usb controller */
         tmp = fsl_readl(&dr_regs->usbcmd);
         tmp &= ~USB_CMD_RUN_STOP;
@@ -215,31 +242,12 @@ static int dr_controller_setup(struct fsl_udc *udc)
                 udc->ep_qh, (int)tmp,
                 fsl_readl(&dr_regs->endpointlistaddr));
 
-        /* Config PHY interface */
-        portctrl = fsl_readl(&dr_regs->portsc1);
-        portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
-        switch (udc->phy_mode) {
-        case FSL_USB2_PHY_ULPI:
-                portctrl |= PORTSCX_PTS_ULPI;
-                break;
-        case FSL_USB2_PHY_UTMI_WIDE:
-                portctrl |= PORTSCX_PTW_16BIT;
-                /* fall through */
-        case FSL_USB2_PHY_UTMI:
-                portctrl |= PORTSCX_PTS_UTMI;
-                break;
-        case FSL_USB2_PHY_SERIAL:
-                portctrl |= PORTSCX_PTS_FSLS;
-                break;
-        default:
-                return -EINVAL;
-        }
-        fsl_writel(portctrl, &dr_regs->portsc1);
-
         /* Config control enable i/o output, cpu endian register */
+#ifndef CONFIG_ARCH_MXC
         ctrl = __raw_readl(&usb_sys_regs->control);
         ctrl |= USB_CTRL_IOENB;
         __raw_writel(ctrl, &usb_sys_regs->control);
+#endif
 
 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
         /* Turn on cache snooping hardware, since some PowerPC platforms
@@ -2043,6 +2051,7 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
         size -= t;
         next += t;
 
+#ifndef CONFIG_ARCH_MXC
         tmp_reg = usb_sys_regs->snoop1;
         t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
         size -= t;
@@ -2053,6 +2062,7 @@ static int fsl_proc_read(char *page, char **start, off_t off, int count,
                         tmp_reg);
         size -= t;
         next += t;
+#endif
 
         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
         ep = &udc->eps[0];
@@ -2263,14 +2273,21 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
                 goto err_kfree;
         }
 
-        dr_regs = ioremap(res->start, res->end - res->start + 1);
+        dr_regs = ioremap(res->start, resource_size(res));
         if (!dr_regs) {
                 ret = -ENOMEM;
                 goto err_release_mem_region;
         }
 
+#ifndef CONFIG_ARCH_MXC
         usb_sys_regs = (struct usb_sys_interface *)
                         ((u32)dr_regs + USB_DR_SYS_OFFSET);
+#endif
+
+        /* Initialize USB clocks */
+        ret = fsl_udc_clk_init(pdev);
+        if (ret < 0)
+                goto err_iounmap_noclk;
 
         /* Read Device Controller Capability Parameters register */
         dccparams = fsl_readl(&dr_regs->dccparams);
@@ -2308,6 +2325,8 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
          * leave usbintr reg untouched */
         dr_controller_setup(udc_controller);
 
+        fsl_udc_clk_finalize(pdev);
+
         /* Setup gadget structure */
         udc_controller->gadget.ops = &fsl_gadget_ops;
         udc_controller->gadget.is_dualspeed = 1;
@@ -2362,6 +2381,8 @@ err_unregister:
 err_free_irq:
         free_irq(udc_controller->irq, udc_controller);
 err_iounmap:
+        fsl_udc_clk_release();
+err_iounmap_noclk:
         iounmap(dr_regs);
 err_release_mem_region:
         release_mem_region(res->start, res->end - res->start + 1);
@@ -2384,6 +2405,8 @@ static int __exit fsl_udc_remove(struct platform_device *pdev)
                 return -ENODEV;
         udc_controller->done = &done;
 
+        fsl_udc_clk_release();
+
         /* DR has been stopped in usb_gadget_unregister_driver() */
         remove_proc_file();
 
diff --git a/drivers/usb/gadget/fsl_usb2_udc.h b/drivers/usb/gadget/fsl_usb2_udc.h
index e63ef12645f5..20aeceed48c7 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.h
+++ b/drivers/usb/gadget/fsl_usb2_udc.h
@@ -563,4 +563,22 @@ static void dump_msg(const char *label, const u8 * buf, unsigned int length)
                                         * 2 + ((windex & USB_DIR_IN) ? 1 : 0))
 #define get_pipe_by_ep(EP)      (ep_index(EP) * 2 + ep_is_in(EP))
 
+struct platform_device;
+#ifdef CONFIG_ARCH_MXC
+int fsl_udc_clk_init(struct platform_device *pdev);
+void fsl_udc_clk_finalize(struct platform_device *pdev);
+void fsl_udc_clk_release(void);
+#else
+static inline int fsl_udc_clk_init(struct platform_device *pdev)
+{
+        return 0;
+}
+static inline void fsl_udc_clk_finalize(struct platform_device *pdev)
+{
+}
+static inline void fsl_udc_clk_release(void)
+{
+}
+#endif
+
 #endif
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index ec6d439a2aa5..8e0e9a0b7364 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -137,6 +137,12 @@
 #define gadget_is_musbhdrc(g)   0
 #endif
 
+#ifdef CONFIG_USB_GADGET_LANGWELL
+#define gadget_is_langwell(g)   (!strcmp("langwell_udc", (g)->name))
+#else
+#define gadget_is_langwell(g)   0
+#endif
+
 /* from Montavista kernel (?) */
 #ifdef CONFIG_USB_GADGET_MPC8272
 #define gadget_is_mpc8272(g)    !strcmp("mpc8272_udc", (g)->name)
@@ -231,6 +237,8 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
                 return 0x22;
         else if (gadget_is_ci13xxx(gadget))
                 return 0x23;
+        else if (gadget_is_langwell(gadget))
+                return 0x24;
         return -ENOENT;
 }
 
diff --git a/drivers/usb/gadget/goku_udc.c b/drivers/usb/gadget/goku_udc.c
index de010c939dbb..112bb40a427c 100644
--- a/drivers/usb/gadget/goku_udc.c
+++ b/drivers/usb/gadget/goku_udc.c
@@ -110,10 +110,10 @@ goku_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
                 return -EINVAL;
         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
                 return -ESHUTDOWN;
-        if (ep->num != (desc->bEndpointAddress & 0x0f))
+        if (ep->num != usb_endpoint_num(desc))
                 return -EINVAL;
 
-        switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
+        switch (usb_endpoint_type(desc)) {
         case USB_ENDPOINT_XFER_BULK:
         case USB_ENDPOINT_XFER_INT:
                 break;
@@ -142,7 +142,7 @@ goku_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
         /* ep1/ep2 dma direction is chosen early; it works in the other
          * direction, with pio.  be cautious with out-dma.
          */
-        ep->is_in = (USB_DIR_IN & desc->bEndpointAddress) != 0;
+        ep->is_in = usb_endpoint_dir_in(desc);
         if (ep->is_in) {
                 mode |= 1;
                 ep->dma = (use_dma != 0) && (ep->num == UDC_MSTRD_ENDPOINT);
diff --git a/drivers/usb/gadget/imx_udc.c b/drivers/usb/gadget/imx_udc.c
index 168658b4b4e2..c52a681f376c 100644
--- a/drivers/usb/gadget/imx_udc.c
+++ b/drivers/usb/gadget/imx_udc.c
@@ -415,6 +415,13 @@ static int write_packet(struct imx_ep_struct *imx_ep, struct imx_request *req)
         u8      *buf;
         int     length, count, temp;
 
+        if (unlikely(__raw_readl(imx_ep->imx_usb->base +
+                                 USB_EP_STAT(EP_NO(imx_ep))) & EPSTAT_ZLPS)) {
+                D_TRX(imx_ep->imx_usb->dev, "<%s> zlp still queued in EP %s\n",
+                        __func__, imx_ep->ep.name);
+                return -1;
+        }
+
         buf = req->req.buf + req->req.actual;
         prefetch(buf);
 
@@ -734,9 +741,12 @@ static struct usb_request *imx_ep_alloc_request
 {
         struct imx_request *req;
 
+        if (!usb_ep)
+                return NULL;
+
         req = kzalloc(sizeof *req, gfp_flags);
-        if (!req || !usb_ep)
-                return 0;
+        if (!req)
+                return NULL;
 
         INIT_LIST_HEAD(&req->queue);
         req->in_use = 0;
diff --git a/drivers/usb/gadget/inode.c b/drivers/usb/gadget/inode.c
index d20937f28a19..7d33f50b5874 100644
--- a/drivers/usb/gadget/inode.c
+++ b/drivers/usb/gadget/inode.c
@@ -384,9 +384,8 @@ ep_read (struct file *fd, char __user *buf, size_t len, loff_t *ptr)
                 return value;
 
         /* halt any endpoint by doing a "wrong direction" i/o call */
-        if (data->desc.bEndpointAddress & USB_DIR_IN) {
-                if ((data->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
-                                == USB_ENDPOINT_XFER_ISOC)
+        if (usb_endpoint_dir_in(&data->desc)) {
+                if (usb_endpoint_xfer_isoc(&data->desc))
                         return -EINVAL;
                 DBG (data->dev, "%s halt\n", data->name);
                 spin_lock_irq (&data->dev->lock);
@@ -428,9 +427,8 @@ ep_write (struct file *fd, const char __user *buf, size_t len, loff_t *ptr)
                 return value;
 
         /* halt any endpoint by doing a "wrong direction" i/o call */
-        if (!(data->desc.bEndpointAddress & USB_DIR_IN)) {
-                if ((data->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
-                                == USB_ENDPOINT_XFER_ISOC)
+        if (!usb_endpoint_dir_in(&data->desc)) {
+                if (usb_endpoint_xfer_isoc(&data->desc))
                         return -EINVAL;
                 DBG (data->dev, "%s halt\n", data->name);
                 spin_lock_irq (&data->dev->lock);
@@ -691,7 +689,7 @@ ep_aio_read(struct kiocb *iocb, const struct iovec *iov,
         struct ep_data          *epdata = iocb->ki_filp->private_data;
         char                    *buf;
 
-        if (unlikely(epdata->desc.bEndpointAddress & USB_DIR_IN))
+        if (unlikely(usb_endpoint_dir_in(&epdata->desc)))
                 return -EINVAL;
 
         buf = kmalloc(iocb->ki_left, GFP_KERNEL);
@@ -711,7 +709,7 @@ ep_aio_write(struct kiocb *iocb, const struct iovec *iov,
         size_t                  len = 0;
         int                     i = 0;
 
-        if (unlikely(!(epdata->desc.bEndpointAddress & USB_DIR_IN)))
+        if (unlikely(!usb_endpoint_dir_in(&epdata->desc)))
                 return -EINVAL;
 
         buf = kmalloc(iocb->ki_left, GFP_KERNEL);
diff --git a/drivers/usb/gadget/langwell_udc.c b/drivers/usb/gadget/langwell_udc.c
new file mode 100644
index 000000000000..6829d5961359
--- /dev/null
+++ b/drivers/usb/gadget/langwell_udc.c
@@ -0,0 +1,3373 @@
+/*
+ * Intel Langwell USB Device Controller driver
+ * Copyright (C) 2008-2009, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+
+/* #undef       DEBUG */
+/* #undef       VERBOSE */
+
+#if defined(CONFIG_USB_LANGWELL_OTG)
+#define OTG_TRANSCEIVER
+#endif
+
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/smp_lock.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+#include <linux/pm.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+
+#include "langwell_udc.h"
+
+
+#define DRIVER_DESC             "Intel Langwell USB Device Controller driver"
+#define DRIVER_VERSION          "16 May 2009"
+
+static const char driver_name[] = "langwell_udc";
+static const char driver_desc[] = DRIVER_DESC;
+
+
+/* controller device global variable */
+static struct langwell_udc      *the_controller;
+
+/* for endpoint 0 operations */
+static const struct usb_endpoint_descriptor
+langwell_ep0_desc = {
+        .bLength =              USB_DT_ENDPOINT_SIZE,
+        .bDescriptorType =      USB_DT_ENDPOINT,
+        .bEndpointAddress =     0,
+        .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
+        .wMaxPacketSize =       EP0_MAX_PKT_SIZE,
+};
+
+
+/*-------------------------------------------------------------------------*/
+/* debugging */
+
+#ifdef  DEBUG
+#define DBG(dev, fmt, args...) \
+        pr_debug("%s %s: " fmt , driver_name, \
+                        pci_name(dev->pdev), ## args)
+#else
+#define DBG(dev, fmt, args...) \
+        do { } while (0)
+#endif /* DEBUG */
+
+
+#ifdef  VERBOSE
+#define VDBG DBG
+#else
+#define VDBG(dev, fmt, args...) \
+        do { } while (0)
+#endif  /* VERBOSE */
+
+
+#define ERROR(dev, fmt, args...) \
+        pr_err("%s %s: " fmt , driver_name, \
+                        pci_name(dev->pdev), ## args)
+
+#define WARNING(dev, fmt, args...) \
+        pr_warning("%s %s: " fmt , driver_name, \
+                        pci_name(dev->pdev), ## args)
+
+#define INFO(dev, fmt, args...) \
+        pr_info("%s %s: " fmt , driver_name, \
+                        pci_name(dev->pdev), ## args)
+
+
+#ifdef  VERBOSE
+static inline void print_all_registers(struct langwell_udc *dev)
+{
+        int     i;
+
+        /* Capability Registers */
+        printk(KERN_DEBUG "Capability Registers (offset: "
+                        "0x%04x, length: 0x%08x)\n",
+                        CAP_REG_OFFSET,
+                        (u32)sizeof(struct langwell_cap_regs));
+        printk(KERN_DEBUG "caplength=0x%02x\n",
+                        readb(&dev->cap_regs->caplength));
+        printk(KERN_DEBUG "hciversion=0x%04x\n",
+                        readw(&dev->cap_regs->hciversion));
+        printk(KERN_DEBUG "hcsparams=0x%08x\n",
+                        readl(&dev->cap_regs->hcsparams));
+        printk(KERN_DEBUG "hccparams=0x%08x\n",
+                        readl(&dev->cap_regs->hccparams));
+        printk(KERN_DEBUG "dciversion=0x%04x\n",
+                        readw(&dev->cap_regs->dciversion));
+        printk(KERN_DEBUG "dccparams=0x%08x\n",
+                        readl(&dev->cap_regs->dccparams));
+
+        /* Operational Registers */
+        printk(KERN_DEBUG "Operational Registers (offset: "
+                        "0x%04x, length: 0x%08x)\n",
+                        OP_REG_OFFSET,
+                        (u32)sizeof(struct langwell_op_regs));
+        printk(KERN_DEBUG "extsts=0x%08x\n",
+                        readl(&dev->op_regs->extsts));
+        printk(KERN_DEBUG "extintr=0x%08x\n",
+                        readl(&dev->op_regs->extintr));
+        printk(KERN_DEBUG "usbcmd=0x%08x\n",
+                        readl(&dev->op_regs->usbcmd));
+        printk(KERN_DEBUG "usbsts=0x%08x\n",
+                        readl(&dev->op_regs->usbsts));
+        printk(KERN_DEBUG "usbintr=0x%08x\n",
+                        readl(&dev->op_regs->usbintr));
+        printk(KERN_DEBUG "frindex=0x%08x\n",
+                        readl(&dev->op_regs->frindex));
+        printk(KERN_DEBUG "ctrldssegment=0x%08x\n",
+                        readl(&dev->op_regs->ctrldssegment));
+        printk(KERN_DEBUG "deviceaddr=0x%08x\n",
+                        readl(&dev->op_regs->deviceaddr));
+        printk(KERN_DEBUG "endpointlistaddr=0x%08x\n",
+                        readl(&dev->op_regs->endpointlistaddr));
+        printk(KERN_DEBUG "ttctrl=0x%08x\n",
+                        readl(&dev->op_regs->ttctrl));
+        printk(KERN_DEBUG "burstsize=0x%08x\n",
+                        readl(&dev->op_regs->burstsize));
+        printk(KERN_DEBUG "txfilltuning=0x%08x\n",
+                        readl(&dev->op_regs->txfilltuning));
+        printk(KERN_DEBUG "txttfilltuning=0x%08x\n",
+                        readl(&dev->op_regs->txttfilltuning));
+        printk(KERN_DEBUG "ic_usb=0x%08x\n",
+                        readl(&dev->op_regs->ic_usb));
+        printk(KERN_DEBUG "ulpi_viewport=0x%08x\n",
+                        readl(&dev->op_regs->ulpi_viewport));
+        printk(KERN_DEBUG "configflag=0x%08x\n",
+                        readl(&dev->op_regs->configflag));
+        printk(KERN_DEBUG "portsc1=0x%08x\n",
+                        readl(&dev->op_regs->portsc1));
+        printk(KERN_DEBUG "devlc=0x%08x\n",
+                        readl(&dev->op_regs->devlc));
+        printk(KERN_DEBUG "otgsc=0x%08x\n",
+                        readl(&dev->op_regs->otgsc));
+        printk(KERN_DEBUG "usbmode=0x%08x\n",
+                        readl(&dev->op_regs->usbmode));
+        printk(KERN_DEBUG "endptnak=0x%08x\n",
+                        readl(&dev->op_regs->endptnak));
+        printk(KERN_DEBUG "endptnaken=0x%08x\n",
+                        readl(&dev->op_regs->endptnaken));
+        printk(KERN_DEBUG "endptsetupstat=0x%08x\n",
+                        readl(&dev->op_regs->endptsetupstat));
+        printk(KERN_DEBUG "endptprime=0x%08x\n",
+                        readl(&dev->op_regs->endptprime));
+        printk(KERN_DEBUG "endptflush=0x%08x\n",
+                        readl(&dev->op_regs->endptflush));
+        printk(KERN_DEBUG "endptstat=0x%08x\n",
+                        readl(&dev->op_regs->endptstat));
+        printk(KERN_DEBUG "endptcomplete=0x%08x\n",
+                        readl(&dev->op_regs->endptcomplete));
+
+        for (i = 0; i < dev->ep_max / 2; i++) {
+                printk(KERN_DEBUG "endptctrl[%d]=0x%08x\n",
+                                i, readl(&dev->op_regs->endptctrl[i]));
+        }
+}
+#endif /* VERBOSE */
+
+
+/*-------------------------------------------------------------------------*/
+
+#define DIR_STRING(bAddress)    (((bAddress) & USB_DIR_IN) ? "in" : "out")
+
+#define is_in(ep)       (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
+                        USB_DIR_IN) : ((ep)->desc->bEndpointAddress \
+                        & USB_DIR_IN) == USB_DIR_IN)
+
+
+#ifdef  DEBUG
+static char *type_string(u8 bmAttributes)
+{
+        switch ((bmAttributes) & USB_ENDPOINT_XFERTYPE_MASK) {
+        case USB_ENDPOINT_XFER_BULK:
+                return "bulk";
+        case USB_ENDPOINT_XFER_ISOC:
+                return "iso";
+        case USB_ENDPOINT_XFER_INT:
+                return "int";
+        };
+
+        return "control";
+}
+#endif
+
+
+/* configure endpoint control registers */
+static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
+                unsigned char is_in, unsigned char ep_type)
+{
+        struct langwell_udc     *dev;
+        u32                     endptctrl;
+
+        dev = ep->dev;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
+        if (is_in) {    /* TX */
+                if (ep_num)
+                        endptctrl |= EPCTRL_TXR;
+                endptctrl |= EPCTRL_TXE;
+                endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
+        } else {        /* RX */
+                if (ep_num)
+                        endptctrl |= EPCTRL_RXR;
+                endptctrl |= EPCTRL_RXE;
+                endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
+        }
+
+        writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
+
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* reset ep0 dQH and endptctrl */
+static void ep0_reset(struct langwell_udc *dev)
+{
+        struct langwell_ep      *ep;
+        int                     i;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        /* ep0 in and out */
+        for (i = 0; i < 2; i++) {
+                ep = &dev->ep[i];
+                ep->dev = dev;
+
+                /* ep0 dQH */
+                ep->dqh = &dev->ep_dqh[i];
+
+                /* configure ep0 endpoint capabilities in dQH */
+                ep->dqh->dqh_ios = 1;
+                ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
+
+                /* FIXME: enable ep0-in HW zero length termination select */
+                if (is_in(ep))
+                        ep->dqh->dqh_zlt = 0;
+                ep->dqh->dqh_mult = 0;
+
+                /* configure ep0 control registers */
+                ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
+        }
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* endpoints operations */
+
+/* configure endpoint, making it usable */
+static int langwell_ep_enable(struct usb_ep *_ep,
+                const struct usb_endpoint_descriptor *desc)
+{
+        struct langwell_udc     *dev;
+        struct langwell_ep      *ep;
+        u16                     max = 0;
+        unsigned long           flags;
+        int                     retval = 0;
+        unsigned char           zlt, ios = 0, mult = 0;
+
+        ep = container_of(_ep, struct langwell_ep, ep);
+        dev = ep->dev;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (!_ep || !desc || ep->desc
+                        || desc->bDescriptorType != USB_DT_ENDPOINT)
+                return -EINVAL;
+
+        if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
+                return -ESHUTDOWN;
+
+        max = le16_to_cpu(desc->wMaxPacketSize);
+
+        /*
+         * disable HW zero length termination select
+         * driver handles zero length packet through req->req.zero
+         */
+        zlt = 1;
+
+        /*
+         * sanity check type, direction, address, and then
+         * initialize the endpoint capabilities fields in dQH
+         */
+        switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
+        case USB_ENDPOINT_XFER_CONTROL:
+                ios = 1;
+                break;
+        case USB_ENDPOINT_XFER_BULK:
+                if ((dev->gadget.speed == USB_SPEED_HIGH
+                                        && max != 512)
+                                || (dev->gadget.speed == USB_SPEED_FULL
+                                        && max > 64)) {
+                        goto done;
+                }
+                break;
+        case USB_ENDPOINT_XFER_INT:
+                if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
+                        goto done;
+
+                switch (dev->gadget.speed) {
+                case USB_SPEED_HIGH:
+                        if (max <= 1024)
+                                break;
+                case USB_SPEED_FULL:
+                        if (max <= 64)
+                                break;
+                default:
+                        if (max <= 8)
+                                break;
+                        goto done;
+                }
+                break;
+        case USB_ENDPOINT_XFER_ISOC:
+                if (strstr(ep->ep.name, "-bulk")
+                                || strstr(ep->ep.name, "-int"))
+                        goto done;
+
+                switch (dev->gadget.speed) {
+                case USB_SPEED_HIGH:
+                        if (max <= 1024)
+                                break;
+                case USB_SPEED_FULL:
+                        if (max <= 1023)
+                                break;
+                default:
+                        goto done;
+                }
+                /*
+                 * FIXME:
+                 * calculate transactions needed for high bandwidth iso
+                 */
+                mult = (unsigned char)(1 + ((max >> 11) & 0x03));
+                max = max & 0x8ff;      /* bit 0~10 */
+                /* 3 transactions at most */
+                if (mult > 3)
+                        goto done;
+                break;
+        default:
+                goto done;
+        }
+
+        spin_lock_irqsave(&dev->lock, flags);
+
+        /* configure endpoint capabilities in dQH */
+        ep->dqh->dqh_ios = ios;
+        ep->dqh->dqh_mpl = cpu_to_le16(max);
+        ep->dqh->dqh_zlt = zlt;
+        ep->dqh->dqh_mult = mult;
+
+        ep->ep.maxpacket = max;
+        ep->desc = desc;
+        ep->stopped = 0;
+        ep->ep_num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+
+        /* ep_type */
+        ep->ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+
+        /* configure endpoint control registers */
+        ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
+
+        DBG(dev, "enabled %s (ep%d%s-%s), max %04x\n",
+                        _ep->name,
+                        ep->ep_num,
+                        DIR_STRING(desc->bEndpointAddress),
+                        type_string(desc->bmAttributes),
+                        max);
+
+        spin_unlock_irqrestore(&dev->lock, flags);
+done:
+        VDBG(dev, "<--- %s()\n", __func__);
+        return retval;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* retire a request */
+static void done(struct langwell_ep *ep, struct langwell_request *req,
+                int status)
+{
+        struct langwell_udc     *dev = ep->dev;
+        unsigned                stopped = ep->stopped;
+        struct langwell_dtd     *curr_dtd, *next_dtd;
+        int                     i;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        /* remove the req from ep->queue */
+        list_del_init(&req->queue);
+
+        if (req->req.status == -EINPROGRESS)
+                req->req.status = status;
+        else
+                status = req->req.status;
+
+        /* free dTD for the request */
+        next_dtd = req->head;
+        for (i = 0; i < req->dtd_count; i++) {
+                curr_dtd = next_dtd;
+                if (i != req->dtd_count - 1)
+                        next_dtd = curr_dtd->next_dtd_virt;
+                dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
+        }
+
+        if (req->mapped) {
+                dma_unmap_single(&dev->pdev->dev, req->req.dma, req->req.length,
+                        is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
+                req->req.dma = DMA_ADDR_INVALID;
+                req->mapped = 0;
+        } else
+                dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma,
+                                req->req.length,
+                                is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+
+        if (status != -ESHUTDOWN)
+                DBG(dev, "complete %s, req %p, stat %d, len %u/%u\n",
+                        ep->ep.name, &req->req, status,
+                        req->req.actual, req->req.length);
+
+        /* don't modify queue heads during completion callback */
+        ep->stopped = 1;
+
+        spin_unlock(&dev->lock);
+        /* complete routine from gadget driver */
+        if (req->req.complete)
+                req->req.complete(&ep->ep, &req->req);
+
+        spin_lock(&dev->lock);
+        ep->stopped = stopped;
+
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+static void langwell_ep_fifo_flush(struct usb_ep *_ep);
+
+/* delete all endpoint requests, called with spinlock held */
+static void nuke(struct langwell_ep *ep, int status)
+{
+        /* called with spinlock held */
+        ep->stopped = 1;
+
+        /* endpoint fifo flush */
+        if (&ep->ep && ep->desc)
+                langwell_ep_fifo_flush(&ep->ep);
+
+        while (!list_empty(&ep->queue)) {
+                struct langwell_request *req = NULL;
+                req = list_entry(ep->queue.next, struct langwell_request,
+                                queue);
+                done(ep, req, status);
+        }
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* endpoint is no longer usable */
+static int langwell_ep_disable(struct usb_ep *_ep)
+{
+        struct langwell_ep      *ep;
+        unsigned long           flags;
+        struct langwell_udc     *dev;
+        int                     ep_num;
+        u32                     endptctrl;
+
+        ep = container_of(_ep, struct langwell_ep, ep);
+        dev = ep->dev;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (!_ep || !ep->desc)
+                return -EINVAL;
+
+        spin_lock_irqsave(&dev->lock, flags);
+
+        /* disable endpoint control register */
+        ep_num = ep->ep_num;
+        endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
+        if (is_in(ep))
+                endptctrl &= ~EPCTRL_TXE;
+        else
+                endptctrl &= ~EPCTRL_RXE;
+        writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
+
+        /* nuke all pending requests (does flush) */
+        nuke(ep, -ESHUTDOWN);
+
+        ep->desc = NULL;
+        ep->stopped = 1;
+
+        spin_unlock_irqrestore(&dev->lock, flags);
+
+        DBG(dev, "disabled %s\n", _ep->name);
+        VDBG(dev, "<--- %s()\n", __func__);
+
+        return 0;
+}
+
+
+/* allocate a request object to use with this endpoint */
+static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
+                gfp_t gfp_flags)
+{
+        struct langwell_ep      *ep;
+        struct langwell_udc     *dev;
+        struct langwell_request *req = NULL;
+
+        if (!_ep)
+                return NULL;
+
+        ep = container_of(_ep, struct langwell_ep, ep);
+        dev = ep->dev;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        req = kzalloc(sizeof(*req), gfp_flags);
+        if (!req)
+                return NULL;
+
+        req->req.dma = DMA_ADDR_INVALID;
+        INIT_LIST_HEAD(&req->queue);
+
+        VDBG(dev, "alloc request for %s\n", _ep->name);
+        VDBG(dev, "<--- %s()\n", __func__);
+        return &req->req;
+}
+
+
+/* free a request object */
+static void langwell_free_request(struct usb_ep *_ep,
+                struct usb_request *_req)
+{
+        struct langwell_ep      *ep;
+        struct langwell_udc     *dev;
+        struct langwell_request *req = NULL;
+
+        ep = container_of(_ep, struct langwell_ep, ep);
+        dev = ep->dev;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (!_ep || !_req)
+                return;
+
+        req = container_of(_req, struct langwell_request, req);
+        WARN_ON(!list_empty(&req->queue));
+
+        if (_req)
+                kfree(req);
+
+        VDBG(dev, "free request for %s\n", _ep->name);
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* queue dTD and PRIME endpoint */
+static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
+{
+        u32                     bit_mask, usbcmd, endptstat, dtd_dma;
+        u8                      dtd_status;
+        int                     i;
+        struct langwell_dqh     *dqh;
+        struct langwell_udc     *dev;
+
+        dev = ep->dev;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        i = ep->ep_num * 2 + is_in(ep);
+        dqh = &dev->ep_dqh[i];
+
+        if (ep->ep_num)
+                VDBG(dev, "%s\n", ep->name);
+        else
+                /* ep0 */
+                VDBG(dev, "%s-%s\n", ep->name, is_in(ep) ? "in" : "out");
+
+        VDBG(dev, "ep_dqh[%d] addr: 0x%08x\n", i, (u32)&(dev->ep_dqh[i]));
+
+        bit_mask = is_in(ep) ?
+                (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
+
+        VDBG(dev, "bit_mask = 0x%08x\n", bit_mask);
+
+        /* check if the pipe is empty */
+        if (!(list_empty(&ep->queue))) {
+                /* add dTD to the end of linked list */
+                struct langwell_request *lastreq;
+                lastreq = list_entry(ep->queue.prev,
+                                struct langwell_request, queue);
+
+                lastreq->tail->dtd_next =
+                        cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
+
+                /* read prime bit, if 1 goto out */
+                if (readl(&dev->op_regs->endptprime) & bit_mask)
+                        goto out;
+
+                do {
+                        /* set ATDTW bit in USBCMD */
+                        usbcmd = readl(&dev->op_regs->usbcmd);
+                        writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
+
+                        /* read correct status bit */
+                        endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
+
+                } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
+
+                /* write ATDTW bit to 0 */
+                usbcmd = readl(&dev->op_regs->usbcmd);
+                writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
+
+                if (endptstat)
+                        goto out;
+        }
+
+        /* write dQH next pointer and terminate bit to 0 */
+        dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
+        dqh->dtd_next = cpu_to_le32(dtd_dma);
+
+        /* clear active and halt bit */
+        dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
+        dqh->dtd_status &= dtd_status;
+        VDBG(dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
+
+        /* write 1 to endptprime register to PRIME endpoint */
+        bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
+        VDBG(dev, "endprime bit_mask = 0x%08x\n", bit_mask);
+        writel(bit_mask, &dev->op_regs->endptprime);
+out:
+        VDBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+
+
+/* fill in the dTD structure to build a transfer descriptor */
+static struct langwell_dtd *build_dtd(struct langwell_request *req,
+                unsigned *length, dma_addr_t *dma, int *is_last)
+{
+        u32                      buf_ptr;
+        struct langwell_dtd     *dtd;
+        struct langwell_udc     *dev;
+        int                     i;
+
+        dev = req->ep->dev;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        /* the maximum transfer length, up to 16k bytes */
+        *length = min(req->req.length - req->req.actual,
+                        (unsigned)DTD_MAX_TRANSFER_LENGTH);
+
+        /* create dTD dma_pool resource */
+        dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
+        if (dtd == NULL)
+                return dtd;
+        dtd->dtd_dma = *dma;
+
+        /* initialize buffer page pointers */
+        buf_ptr = (u32)(req->req.dma + req->req.actual);
+        for (i = 0; i < 5; i++)
+                dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
+
+        req->req.actual += *length;
+
+        /* fill in total bytes with transfer size */
+        dtd->dtd_total = cpu_to_le16(*length);
+        VDBG(dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
+
+        /* set is_last flag if req->req.zero is set or not */
+        if (req->req.zero) {
+                if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
+                        *is_last = 1;
+                else
+                        *is_last = 0;
+        } else if (req->req.length == req->req.actual) {
+                *is_last = 1;
+        } else
+                *is_last = 0;
+
+        if (*is_last == 0)
+                VDBG(dev, "multi-dtd request!\n");
+
+        /* set interrupt on complete bit for the last dTD */
+        if (*is_last && !req->req.no_interrupt)
+                dtd->dtd_ioc = 1;
+
+        /* set multiplier override 0 for non-ISO and non-TX endpoint */
+        dtd->dtd_multo = 0;
+
+        /* set the active bit of status field to 1 */
+        dtd->dtd_status = DTD_STS_ACTIVE;
+        VDBG(dev, "dtd->dtd_status = 0x%02x\n", dtd->dtd_status);
+
+        VDBG(dev, "length = %d, dma addr= 0x%08x\n", *length, (int)*dma);
+        VDBG(dev, "<--- %s()\n", __func__);
+        return dtd;
+}
+
+
+/* generate dTD linked list for a request */
+static int req_to_dtd(struct langwell_request *req)
+{
+        unsigned                count;
+        int                     is_last, is_first = 1;
+        struct langwell_dtd     *dtd, *last_dtd = NULL;
+        struct langwell_udc     *dev;
+        dma_addr_t              dma;
+
+        dev = req->ep->dev;
+        VDBG(dev, "---> %s()\n", __func__);
+        do {
+                dtd = build_dtd(req, &count, &dma, &is_last);
+                if (dtd == NULL)
+                        return -ENOMEM;
+
+                if (is_first) {
+                        is_first = 0;
+                        req->head = dtd;
+                } else {
+                        last_dtd->dtd_next = cpu_to_le32(dma);
+                        last_dtd->next_dtd_virt = dtd;
+                }
+                last_dtd = dtd;
+                req->dtd_count++;
+        } while (!is_last);
+
+        /* set terminate bit to 1 for the last dTD */
+        dtd->dtd_next = DTD_TERM;
+
+        req->tail = dtd;
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* queue (submits) an I/O requests to an endpoint */
+static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
+                gfp_t gfp_flags)
+{
+        struct langwell_request *req;
+        struct langwell_ep      *ep;
+        struct langwell_udc     *dev;
+        unsigned long           flags;
+        int                     is_iso = 0, zlflag = 0;
+
+        /* always require a cpu-view buffer */
+        req = container_of(_req, struct langwell_request, req);
+        ep = container_of(_ep, struct langwell_ep, ep);
+
+        if (!_req || !_req->complete || !_req->buf
+                        || !list_empty(&req->queue)) {
+                return -EINVAL;
+        }
+
+        if (unlikely(!_ep || !ep->desc))
+                return -EINVAL;
+
+        dev = ep->dev;
+        req->ep = ep;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+                if (req->req.length > ep->ep.maxpacket)
+                        return -EMSGSIZE;
+                is_iso = 1;
+        }
+
+        if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
+                return -ESHUTDOWN;
+
+        /* set up dma mapping in case the caller didn't */
+        if (_req->dma == DMA_ADDR_INVALID) {
+                /* WORKAROUND: WARN_ON(size == 0) */
+                if (_req->length == 0) {
+                        VDBG(dev, "req->length: 0->1\n");
+                        zlflag = 1;
+                        _req->length++;
+                }
+
+                _req->dma = dma_map_single(&dev->pdev->dev,
+                                _req->buf, _req->length,
+                                is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+                if (zlflag && (_req->length == 1)) {
+                        VDBG(dev, "req->length: 1->0\n");
+                        zlflag = 0;
+                        _req->length = 0;
+                }
+
+                req->mapped = 1;
+                VDBG(dev, "req->mapped = 1\n");
+        } else {
+                dma_sync_single_for_device(&dev->pdev->dev,
+                                _req->dma, _req->length,
+                                is_in(ep) ?  DMA_TO_DEVICE : DMA_FROM_DEVICE);
+                req->mapped = 0;
+                VDBG(dev, "req->mapped = 0\n");
+        }
+
+        DBG(dev, "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
+                        _ep->name,
+                        _req, _req->length, _req->buf, _req->dma);
+
+        _req->status = -EINPROGRESS;
+        _req->actual = 0;
+        req->dtd_count = 0;
+
+        spin_lock_irqsave(&dev->lock, flags);
+
+        /* build and put dTDs to endpoint queue */
+        if (!req_to_dtd(req)) {
+                queue_dtd(ep, req);
+        } else {
+                spin_unlock_irqrestore(&dev->lock, flags);
+                return -ENOMEM;
+        }
+
+        /* update ep0 state */
+        if (ep->ep_num == 0)
+                dev->ep0_state = DATA_STATE_XMIT;
+
+        if (likely(req != NULL)) {
+                list_add_tail(&req->queue, &ep->queue);
+                VDBG(dev, "list_add_tail() \n");
+        }
+
+        spin_unlock_irqrestore(&dev->lock, flags);
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+
+
+/* dequeue (cancels, unlinks) an I/O request from an endpoint */
+static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+        struct langwell_ep      *ep;
+        struct langwell_udc     *dev;
+        struct langwell_request *req;
+        unsigned long           flags;
+        int                     stopped, ep_num, retval = 0;
+        u32                     endptctrl;
+
+        ep = container_of(_ep, struct langwell_ep, ep);
+        dev = ep->dev;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (!_ep || !ep->desc || !_req)
+                return -EINVAL;
+
+        if (!dev->driver)
+                return -ESHUTDOWN;
+
+        spin_lock_irqsave(&dev->lock, flags);
+        stopped = ep->stopped;
+
+        /* quiesce dma while we patch the queue */
+        ep->stopped = 1;
+        ep_num = ep->ep_num;
+
+        /* disable endpoint control register */
+        endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
+        if (is_in(ep))
+                endptctrl &= ~EPCTRL_TXE;
+        else
+                endptctrl &= ~EPCTRL_RXE;
+        writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
+
+        /* make sure it's still queued on this endpoint */
+        list_for_each_entry(req, &ep->queue, queue) {
+                if (&req->req == _req)
+                        break;
+        }
+
+        if (&req->req != _req) {
+                retval = -EINVAL;
+                goto done;
+        }
+
+        /* queue head may be partially complete. */
+        if (ep->queue.next == &req->queue) {
+                DBG(dev, "unlink (%s) dma\n", _ep->name);
+                _req->status = -ECONNRESET;
+                langwell_ep_fifo_flush(&ep->ep);
+
+                /* not the last request in endpoint queue */
+                if (likely(ep->queue.next == &req->queue)) {
+                        struct langwell_dqh     *dqh;
+                        struct langwell_request *next_req;
+
+                        dqh = ep->dqh;
+                        next_req = list_entry(req->queue.next,
+                                        struct langwell_request, queue);
+
+                        /* point the dQH to the first dTD of next request */
+                        writel((u32) next_req->head, &dqh->dqh_current);
+                }
+        } else {
+                struct langwell_request *prev_req;
+
+                prev_req = list_entry(req->queue.prev,
+                                struct langwell_request, queue);
+                writel(readl(&req->tail->dtd_next),
+                                &prev_req->tail->dtd_next);
+        }
+
+        done(ep, req, -ECONNRESET);
+
+done:
+        /* enable endpoint again */
+        endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
+        if (is_in(ep))
+                endptctrl |= EPCTRL_TXE;
+        else
+                endptctrl |= EPCTRL_RXE;
+        writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
+
+        ep->stopped = stopped;
+        spin_unlock_irqrestore(&dev->lock, flags);
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return retval;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* endpoint set/clear halt */
+static void ep_set_halt(struct langwell_ep *ep, int value)
+{
+        u32                     endptctrl = 0;
+        int                     ep_num;
+        struct langwell_udc     *dev = ep->dev;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        ep_num = ep->ep_num;
+        endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
+
+        /* value: 1 - set halt, 0 - clear halt */
+        if (value) {
+                /* set the stall bit */
+                if (is_in(ep))
+                        endptctrl |= EPCTRL_TXS;
+                else
+                        endptctrl |= EPCTRL_RXS;
+        } else {
+                /* clear the stall bit and reset data toggle */
+                if (is_in(ep)) {
+                        endptctrl &= ~EPCTRL_TXS;
+                        endptctrl |= EPCTRL_TXR;
+                } else {
+                        endptctrl &= ~EPCTRL_RXS;
+                        endptctrl |= EPCTRL_RXR;
+                }
+        }
+
+        writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
+
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* set the endpoint halt feature */
+static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
+{
+        struct langwell_ep      *ep;
+        struct langwell_udc     *dev;
+        unsigned long           flags;
+        int                     retval = 0;
+
+        ep = container_of(_ep, struct langwell_ep, ep);
+        dev = ep->dev;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (!_ep || !ep->desc)
+                return -EINVAL;
+
+        if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
+                return -ESHUTDOWN;
+
+        if (ep->desc && (ep->desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
+                        == USB_ENDPOINT_XFER_ISOC)
+                return  -EOPNOTSUPP;
+
+        spin_lock_irqsave(&dev->lock, flags);
+
+        /*
+         * attempt to halt IN ep will fail if any transfer requests
+         * are still queue
+         */
+        if (!list_empty(&ep->queue) && is_in(ep) && value) {
+                /* IN endpoint FIFO holds bytes */
+                DBG(dev, "%s FIFO holds bytes\n", _ep->name);
+                retval = -EAGAIN;
+                goto done;
+        }
+
+        /* endpoint set/clear halt */
+        if (ep->ep_num) {
+                ep_set_halt(ep, value);
+        } else { /* endpoint 0 */
+                dev->ep0_state = WAIT_FOR_SETUP;
+                dev->ep0_dir = USB_DIR_OUT;
+        }
+done:
+        spin_unlock_irqrestore(&dev->lock, flags);
+        DBG(dev, "%s %s halt\n", _ep->name, value ? "set" : "clear");
+        VDBG(dev, "<--- %s()\n", __func__);
+        return retval;
+}
+
+
+/* set the halt feature and ignores clear requests */
+static int langwell_ep_set_wedge(struct usb_ep *_ep)
+{
+        struct langwell_ep      *ep;
+        struct langwell_udc     *dev;
+
+        ep = container_of(_ep, struct langwell_ep, ep);
+        dev = ep->dev;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (!_ep || !ep->desc)
+                return -EINVAL;
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return usb_ep_set_halt(_ep);
+}
+
+
+/* flush contents of a fifo */
+static void langwell_ep_fifo_flush(struct usb_ep *_ep)
+{
+        struct langwell_ep      *ep;
+        struct langwell_udc     *dev;
+        u32                     flush_bit;
+        unsigned long           timeout;
+
+        ep = container_of(_ep, struct langwell_ep, ep);
+        dev = ep->dev;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (!_ep || !ep->desc) {
+                VDBG(dev, "ep or ep->desc is NULL\n");
+                VDBG(dev, "<--- %s()\n", __func__);
+                return;
+        }
+
+        VDBG(dev, "%s-%s fifo flush\n", _ep->name, is_in(ep) ? "in" : "out");
+
+        /* flush endpoint buffer */
+        if (ep->ep_num == 0)
+                flush_bit = (1 << 16) | 1;
+        else if (is_in(ep))
+                flush_bit = 1 << (ep->ep_num + 16);     /* TX */
+        else
+                flush_bit = 1 << ep->ep_num;            /* RX */
+
+        /* wait until flush complete */
+        timeout = jiffies + FLUSH_TIMEOUT;
+        do {
+                writel(flush_bit, &dev->op_regs->endptflush);
+                while (readl(&dev->op_regs->endptflush)) {
+                        if (time_after(jiffies, timeout)) {
+                                ERROR(dev, "ep flush timeout\n");
+                                goto done;
+                        }
+                        cpu_relax();
+                }
+        } while (readl(&dev->op_regs->endptstat) & flush_bit);
+done:
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* endpoints operations structure */
+static const struct usb_ep_ops langwell_ep_ops = {
+
+        /* configure endpoint, making it usable */
+        .enable         = langwell_ep_enable,
+
+        /* endpoint is no longer usable */
+        .disable        = langwell_ep_disable,
+
+        /* allocate a request object to use with this endpoint */
+        .alloc_request  = langwell_alloc_request,
+
+        /* free a request object */
+        .free_request   = langwell_free_request,
+
+        /* queue (submits) an I/O requests to an endpoint */
+        .queue          = langwell_ep_queue,
+
+        /* dequeue (cancels, unlinks) an I/O request from an endpoint */
+        .dequeue        = langwell_ep_dequeue,
+
+        /* set the endpoint halt feature */
+        .set_halt       = langwell_ep_set_halt,
+
+        /* set the halt feature and ignores clear requests */
+        .set_wedge      = langwell_ep_set_wedge,
+
+        /* flush contents of a fifo */
+        .fifo_flush     = langwell_ep_fifo_flush,
+};
+
+
+/*-------------------------------------------------------------------------*/
+
+/* device controller usb_gadget_ops structure */
+
+/* returns the current frame number */
+static int langwell_get_frame(struct usb_gadget *_gadget)
+{
+        struct langwell_udc     *dev;
+        u16                     retval;
+
+        if (!_gadget)
+                return -ENODEV;
+
+        dev = container_of(_gadget, struct langwell_udc, gadget);
+        VDBG(dev, "---> %s()\n", __func__);
+
+        retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return retval;
+}
+
+
+/* tries to wake up the host connected to this gadget */
+static int langwell_wakeup(struct usb_gadget *_gadget)
+{
+        struct langwell_udc     *dev;
+        u32                     portsc1, devlc;
+        unsigned long           flags;
+
+        if (!_gadget)
+                return 0;
+
+        dev = container_of(_gadget, struct langwell_udc, gadget);
+        VDBG(dev, "---> %s()\n", __func__);
+
+        /* Remote Wakeup feature not enabled by host */
+        if (!dev->remote_wakeup)
+                return -ENOTSUPP;
+
+        spin_lock_irqsave(&dev->lock, flags);
+
+        portsc1 = readl(&dev->op_regs->portsc1);
+        if (!(portsc1 & PORTS_SUSP)) {
+                spin_unlock_irqrestore(&dev->lock, flags);
+                return 0;
+        }
+
+        /* LPM L1 to L0, remote wakeup */
+        if (dev->lpm && dev->lpm_state == LPM_L1) {
+                portsc1 |= PORTS_SLP;
+                writel(portsc1, &dev->op_regs->portsc1);
+        }
+
+        /* force port resume */
+        if (dev->usb_state == USB_STATE_SUSPENDED) {
+                portsc1 |= PORTS_FPR;
+                writel(portsc1, &dev->op_regs->portsc1);
+        }
+
+        /* exit PHY low power suspend */
+        devlc = readl(&dev->op_regs->devlc);
+        VDBG(dev, "devlc = 0x%08x\n", devlc);
+        devlc &= ~LPM_PHCD;
+        writel(devlc, &dev->op_regs->devlc);
+
+        spin_unlock_irqrestore(&dev->lock, flags);
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+
+
+/* notify controller that VBUS is powered or not */
+static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
+{
+        struct langwell_udc     *dev;
+        unsigned long           flags;
+        u32                     usbcmd;
+
+        if (!_gadget)
+                return -ENODEV;
+
+        dev = container_of(_gadget, struct langwell_udc, gadget);
+        VDBG(dev, "---> %s()\n", __func__);
+
+        spin_lock_irqsave(&dev->lock, flags);
+        VDBG(dev, "VBUS status: %s\n", is_active ? "on" : "off");
+
+        dev->vbus_active = (is_active != 0);
+        if (dev->driver && dev->softconnected && dev->vbus_active) {
+                usbcmd = readl(&dev->op_regs->usbcmd);
+                usbcmd |= CMD_RUNSTOP;
+                writel(usbcmd, &dev->op_regs->usbcmd);
+        } else {
+                usbcmd = readl(&dev->op_regs->usbcmd);
+                usbcmd &= ~CMD_RUNSTOP;
+                writel(usbcmd, &dev->op_regs->usbcmd);
+        }
+
+        spin_unlock_irqrestore(&dev->lock, flags);
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+
+
+/* constrain controller's VBUS power usage */
+static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
+{
+        struct langwell_udc     *dev;
+
+        if (!_gadget)
+                return -ENODEV;
+
+        dev = container_of(_gadget, struct langwell_udc, gadget);
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (dev->transceiver) {
+                VDBG(dev, "otg_set_power\n");
+                VDBG(dev, "<--- %s()\n", __func__);
+                return otg_set_power(dev->transceiver, mA);
+        }
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return -ENOTSUPP;
+}
+
+
+/* D+ pullup, software-controlled connect/disconnect to USB host */
+static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
+{
+        struct langwell_udc     *dev;
+        u32                     usbcmd;
+        unsigned long           flags;
+
+        if (!_gadget)
+                return -ENODEV;
+
+        dev = container_of(_gadget, struct langwell_udc, gadget);
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        spin_lock_irqsave(&dev->lock, flags);
+        dev->softconnected = (is_on != 0);
+
+        if (dev->driver && dev->softconnected && dev->vbus_active) {
+                usbcmd = readl(&dev->op_regs->usbcmd);
+                usbcmd |= CMD_RUNSTOP;
+                writel(usbcmd, &dev->op_regs->usbcmd);
+        } else {
+                usbcmd = readl(&dev->op_regs->usbcmd);
+                usbcmd &= ~CMD_RUNSTOP;
+                writel(usbcmd, &dev->op_regs->usbcmd);
+        }
+        spin_unlock_irqrestore(&dev->lock, flags);
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+
+
+/* device controller usb_gadget_ops structure */
+static const struct usb_gadget_ops langwell_ops = {
+
+        /* returns the current frame number */
+        .get_frame      = langwell_get_frame,
+
+        /* tries to wake up the host connected to this gadget */
+        .wakeup         = langwell_wakeup,
+
+        /* set the device selfpowered feature, always selfpowered */
+        /* .set_selfpowered = langwell_set_selfpowered, */
+
+        /* notify controller that VBUS is powered or not */
+        .vbus_session   = langwell_vbus_session,
+
+        /* constrain controller's VBUS power usage */
+        .vbus_draw      = langwell_vbus_draw,
+
+        /* D+ pullup, software-controlled connect/disconnect to USB host */
+        .pullup         = langwell_pullup,
+};
+
+
+/*-------------------------------------------------------------------------*/
+
+/* device controller operations */
+
+/* reset device controller */
+static int langwell_udc_reset(struct langwell_udc *dev)
+{
+        u32             usbcmd, usbmode, devlc, endpointlistaddr;
+        unsigned long   timeout;
+
+        if (!dev)
+                return -EINVAL;
+
+        DBG(dev, "---> %s()\n", __func__);
+
+        /* set controller to stop state */
+        usbcmd = readl(&dev->op_regs->usbcmd);
+        usbcmd &= ~CMD_RUNSTOP;
+        writel(usbcmd, &dev->op_regs->usbcmd);
+
+        /* reset device controller */
+        usbcmd = readl(&dev->op_regs->usbcmd);
+        usbcmd |= CMD_RST;
+        writel(usbcmd, &dev->op_regs->usbcmd);
+
+        /* wait for reset to complete */
+        timeout = jiffies + RESET_TIMEOUT;
+        while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
+                if (time_after(jiffies, timeout)) {
+                        ERROR(dev, "device reset timeout\n");
+                        return -ETIMEDOUT;
+                }
+                cpu_relax();
+        }
+
+        /* set controller to device mode */
+        usbmode = readl(&dev->op_regs->usbmode);
+        usbmode |= MODE_DEVICE;
+
+        /* turn setup lockout off, require setup tripwire in usbcmd */
+        usbmode |= MODE_SLOM;
+
+        writel(usbmode, &dev->op_regs->usbmode);
+        usbmode = readl(&dev->op_regs->usbmode);
+        VDBG(dev, "usbmode=0x%08x\n", usbmode);
+
+        /* Write-Clear setup status */
+        writel(0, &dev->op_regs->usbsts);
+
+        /* if support USB LPM, ACK all LPM token */
+        if (dev->lpm) {
+                devlc = readl(&dev->op_regs->devlc);
+                devlc &= ~LPM_STL;      /* don't STALL LPM token */
+                devlc &= ~LPM_NYT_ACK;  /* ACK LPM token */
+                writel(devlc, &dev->op_regs->devlc);
+        }
+
+        /* fill endpointlistaddr register */
+        endpointlistaddr = dev->ep_dqh_dma;
+        endpointlistaddr &= ENDPOINTLISTADDR_MASK;
+        writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
+
+        VDBG(dev, "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
+                        dev->ep_dqh, endpointlistaddr,
+                        readl(&dev->op_regs->endpointlistaddr));
+        DBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+
+
+/* reinitialize device controller endpoints */
+static int eps_reinit(struct langwell_udc *dev)
+{
+        struct langwell_ep      *ep;
+        char                    name[14];
+        int                     i;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        /* initialize ep0 */
+        ep = &dev->ep[0];
+        ep->dev = dev;
+        strncpy(ep->name, "ep0", sizeof(ep->name));
+        ep->ep.name = ep->name;
+        ep->ep.ops = &langwell_ep_ops;
+        ep->stopped = 0;
+        ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
+        ep->ep_num = 0;
+        ep->desc = &langwell_ep0_desc;
+        INIT_LIST_HEAD(&ep->queue);
+
+        ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
+
+        /* initialize other endpoints */
+        for (i = 2; i < dev->ep_max; i++) {
+                ep = &dev->ep[i];
+                if (i % 2)
+                        snprintf(name, sizeof(name), "ep%din", i / 2);
+                else
+                        snprintf(name, sizeof(name), "ep%dout", i / 2);
+                ep->dev = dev;
+                strncpy(ep->name, name, sizeof(ep->name));
+                ep->ep.name = ep->name;
+
+                ep->ep.ops = &langwell_ep_ops;
+                ep->stopped = 0;
+                ep->ep.maxpacket = (unsigned short) ~0;
+                ep->ep_num = i / 2;
+
+                INIT_LIST_HEAD(&ep->queue);
+                list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
+
+                ep->dqh = &dev->ep_dqh[i];
+        }
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+
+
+/* enable interrupt and set controller to run state */
+static void langwell_udc_start(struct langwell_udc *dev)
+{
+        u32     usbintr, usbcmd;
+        DBG(dev, "---> %s()\n", __func__);
+
+        /* enable interrupts */
+        usbintr = INTR_ULPIE    /* ULPI */
+                | INTR_SLE      /* suspend */
+                /* | INTR_SRE   SOF received */
+                | INTR_URE      /* USB reset */
+                | INTR_AAE      /* async advance */
+                | INTR_SEE      /* system error */
+                | INTR_FRE      /* frame list rollover */
+                | INTR_PCE      /* port change detect */
+                | INTR_UEE      /* USB error interrupt */
+                | INTR_UE;      /* USB interrupt */
+        writel(usbintr, &dev->op_regs->usbintr);
+
+        /* clear stopped bit */
+        dev->stopped = 0;
+
+        /* set controller to run */
+        usbcmd = readl(&dev->op_regs->usbcmd);
+        usbcmd |= CMD_RUNSTOP;
+        writel(usbcmd, &dev->op_regs->usbcmd);
+
+        DBG(dev, "<--- %s()\n", __func__);
+        return;
+}
+
+
+/* disable interrupt and set controller to stop state */
+static void langwell_udc_stop(struct langwell_udc *dev)
+{
+        u32     usbcmd;
+
+        DBG(dev, "---> %s()\n", __func__);
+
+        /* disable all interrupts */
+        writel(0, &dev->op_regs->usbintr);
+
+        /* set stopped bit */
+        dev->stopped = 1;
+
+        /* set controller to stop state */
+        usbcmd = readl(&dev->op_regs->usbcmd);
+        usbcmd &= ~CMD_RUNSTOP;
+        writel(usbcmd, &dev->op_regs->usbcmd);
+
+        DBG(dev, "<--- %s()\n", __func__);
+        return;
+}
+
+
+/* stop all USB activities */
+static void stop_activity(struct langwell_udc *dev,
+                struct usb_gadget_driver *driver)
+{
+        struct langwell_ep      *ep;
+        DBG(dev, "---> %s()\n", __func__);
+
+        nuke(&dev->ep[0], -ESHUTDOWN);
+
+        list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
+                nuke(ep, -ESHUTDOWN);
+        }
+
+        /* report disconnect; the driver is already quiesced */
+        if (driver) {
+                spin_unlock(&dev->lock);
+                driver->disconnect(&dev->gadget);
+                spin_lock(&dev->lock);
+        }
+
+        DBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* device "function" sysfs attribute file */
+static ssize_t show_function(struct device *_dev,
+                struct device_attribute *attr, char *buf)
+{
+        struct langwell_udc     *dev = the_controller;
+
+        if (!dev->driver || !dev->driver->function
+                        || strlen(dev->driver->function) > PAGE_SIZE)
+                return 0;
+
+        return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
+}
+static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
+
+
+/* device "langwell_udc" sysfs attribute file */
+static ssize_t show_langwell_udc(struct device *_dev,
+                struct device_attribute *attr, char *buf)
+{
+        struct langwell_udc     *dev = the_controller;
+        struct langwell_request *req;
+        struct langwell_ep      *ep = NULL;
+        char                    *next;
+        unsigned                size;
+        unsigned                t;
+        unsigned                i;
+        unsigned long           flags;
+        u32                     tmp_reg;
+
+        next = buf;
+        size = PAGE_SIZE;
+        spin_lock_irqsave(&dev->lock, flags);
+
+        /* driver basic information */
+        t = scnprintf(next, size,
+                        DRIVER_DESC "\n"
+                        "%s version: %s\n"
+                        "Gadget driver: %s\n\n",
+                        driver_name, DRIVER_VERSION,
+                        dev->driver ? dev->driver->driver.name : "(none)");
+        size -= t;
+        next += t;
+
+        /* device registers */
+        tmp_reg = readl(&dev->op_regs->usbcmd);
+        t = scnprintf(next, size,
+                        "USBCMD reg:\n"
+                        "SetupTW: %d\n"
+                        "Run/Stop: %s\n\n",
+                        (tmp_reg & CMD_SUTW) ? 1 : 0,
+                        (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
+        size -= t;
+        next += t;
+
+        tmp_reg = readl(&dev->op_regs->usbsts);
+        t = scnprintf(next, size,
+                        "USB Status Reg:\n"
+                        "Device Suspend: %d\n"
+                        "Reset Received: %d\n"
+                        "System Error: %s\n"
+                        "USB Error Interrupt: %s\n\n",
+                        (tmp_reg & STS_SLI) ? 1 : 0,
+                        (tmp_reg & STS_URI) ? 1 : 0,
+                        (tmp_reg & STS_SEI) ? "Error" : "No error",
+                        (tmp_reg & STS_UEI) ? "Error detected" : "No error");
+        size -= t;
+        next += t;
+
+        tmp_reg = readl(&dev->op_regs->usbintr);
+        t = scnprintf(next, size,
+                        "USB Intrrupt Enable Reg:\n"
+                        "Sleep Enable: %d\n"
+                        "SOF Received Enable: %d\n"
+                        "Reset Enable: %d\n"
+                        "System Error Enable: %d\n"
+                        "Port Change Dectected Enable: %d\n"
+                        "USB Error Intr Enable: %d\n"
+                        "USB Intr Enable: %d\n\n",
+                        (tmp_reg & INTR_SLE) ? 1 : 0,
+                        (tmp_reg & INTR_SRE) ? 1 : 0,
+                        (tmp_reg & INTR_URE) ? 1 : 0,
+                        (tmp_reg & INTR_SEE) ? 1 : 0,
+                        (tmp_reg & INTR_PCE) ? 1 : 0,
+                        (tmp_reg & INTR_UEE) ? 1 : 0,
+                        (tmp_reg & INTR_UE) ? 1 : 0);
+        size -= t;
+        next += t;
+
+        tmp_reg = readl(&dev->op_regs->frindex);
+        t = scnprintf(next, size,
+                        "USB Frame Index Reg:\n"
+                        "Frame Number is 0x%08x\n\n",
+                        (tmp_reg & FRINDEX_MASK));
+        size -= t;
+        next += t;
+
+        tmp_reg = readl(&dev->op_regs->deviceaddr);
+        t = scnprintf(next, size,
+                        "USB Device Address Reg:\n"
+                        "Device Addr is 0x%x\n\n",
+                        USBADR(tmp_reg));
+        size -= t;
+        next += t;
+
+        tmp_reg = readl(&dev->op_regs->endpointlistaddr);
+        t = scnprintf(next, size,
+                        "USB Endpoint List Address Reg:\n"
+                        "Endpoint List Pointer is 0x%x\n\n",
+                        EPBASE(tmp_reg));
+        size -= t;
+        next += t;
+
+        tmp_reg = readl(&dev->op_regs->portsc1);
+        t = scnprintf(next, size,
+                "USB Port Status & Control Reg:\n"
+                "Port Reset: %s\n"
+                "Port Suspend Mode: %s\n"
+                "Over-current Change: %s\n"
+                "Port Enable/Disable Change: %s\n"
+                "Port Enabled/Disabled: %s\n"
+                "Current Connect Status: %s\n\n",
+                (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
+                (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
+                (tmp_reg & PORTS_OCC) ? "Detected" : "No",
+                (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
+                (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
+                (tmp_reg & PORTS_CCS) ?  "Attached" : "Not Attached");
+        size -= t;
+        next += t;
+
+        tmp_reg = readl(&dev->op_regs->devlc);
+        t = scnprintf(next, size,
+                "Device LPM Control Reg:\n"
+                "Parallel Transceiver : %d\n"
+                "Serial Transceiver : %d\n"
+                "Port Speed: %s\n"
+                "Port Force Full Speed Connenct: %s\n"
+                "PHY Low Power Suspend Clock Disable: %s\n"
+                "BmAttributes: %d\n\n",
+                LPM_PTS(tmp_reg),
+                (tmp_reg & LPM_STS) ? 1 : 0,
+                ({
+                        char    *s;
+                        switch (LPM_PSPD(tmp_reg)) {
+                        case LPM_SPEED_FULL:
+                                s = "Full Speed"; break;
+                        case LPM_SPEED_LOW:
+                                s = "Low Speed"; break;
+                        case LPM_SPEED_HIGH:
+                                s = "High Speed"; break;
+                        default:
+                                s = "Unknown Speed"; break;
+                        }
+                        s;
+                }),
+                (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
+                (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
+                LPM_BA(tmp_reg));
+        size -= t;
+        next += t;
+
+        tmp_reg = readl(&dev->op_regs->usbmode);
+        t = scnprintf(next, size,
+                        "USB Mode Reg:\n"
+                        "Controller Mode is : %s\n\n", ({
+                                char *s;
+                                switch (MODE_CM(tmp_reg)) {
+                                case MODE_IDLE:
+                                        s = "Idle"; break;
+                                case MODE_DEVICE:
+                                        s = "Device Controller"; break;
+                                case MODE_HOST:
+                                        s = "Host Controller"; break;
+                                default:
+                                        s = "None"; break;
+                                }
+                                s;
+                        }));
+        size -= t;
+        next += t;
+
+        tmp_reg = readl(&dev->op_regs->endptsetupstat);
+        t = scnprintf(next, size,
+                        "Endpoint Setup Status Reg:\n"
+                        "SETUP on ep 0x%04x\n\n",
+                        tmp_reg & SETUPSTAT_MASK);
+        size -= t;
+        next += t;
+
+        for (i = 0; i < dev->ep_max / 2; i++) {
+                tmp_reg = readl(&dev->op_regs->endptctrl[i]);
+                t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
+                                i, tmp_reg);
+                size -= t;
+                next += t;
+        }
+        tmp_reg = readl(&dev->op_regs->endptprime);
+        t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
+        size -= t;
+        next += t;
+
+        /* langwell_udc, langwell_ep, langwell_request structure information */
+        ep = &dev->ep[0];
+        t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
+                        ep->ep.name, ep->ep.maxpacket, ep->ep_num);
+        size -= t;
+        next += t;
+
+        if (list_empty(&ep->queue)) {
+                t = scnprintf(next, size, "its req queue is empty\n\n");
+                size -= t;
+                next += t;
+        } else {
+                list_for_each_entry(req, &ep->queue, queue) {
+                        t = scnprintf(next, size,
+                                "req %p actual 0x%x length 0x%x  buf %p\n",
+                                &req->req, req->req.actual,
+                                req->req.length, req->req.buf);
+                        size -= t;
+                        next += t;
+                }
+        }
+        /* other gadget->eplist ep */
+        list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
+                if (ep->desc) {
+                        t = scnprintf(next, size,
+                                        "\n%s MaxPacketSize: 0x%x, "
+                                        "ep_num: %d\n",
+                                        ep->ep.name, ep->ep.maxpacket,
+                                        ep->ep_num);
+                        size -= t;
+                        next += t;
+
+                        if (list_empty(&ep->queue)) {
+                                t = scnprintf(next, size,
+                                                "its req queue is empty\n\n");
+                                size -= t;
+                                next += t;
+                        } else {
+                                list_for_each_entry(req, &ep->queue, queue) {
+                                        t = scnprintf(next, size,
+                                                "req %p actual 0x%x length "
+                                                "0x%x  buf %p\n",
+                                                &req->req, req->req.actual,
+                                                req->req.length, req->req.buf);
+                                        size -= t;
+                                        next += t;
+                                }
+                        }
+                }
+        }
+
+        spin_unlock_irqrestore(&dev->lock, flags);
+        return PAGE_SIZE - size;
+}
+static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
+
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * when a driver is successfully registered, it will receive
+ * control requests including set_configuration(), which enables
+ * non-control requests.  then usb traffic follows until a
+ * disconnect is reported.  then a host may connect again, or
+ * the driver might get unbound.
+ */
+
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+        struct langwell_udc     *dev = the_controller;
+        unsigned long           flags;
+        int                     retval;
+
+        if (!dev)
+                return -ENODEV;
+
+        DBG(dev, "---> %s()\n", __func__);
+
+        if (dev->driver)
+                return -EBUSY;
+
+        spin_lock_irqsave(&dev->lock, flags);
+
+        /* hook up the driver ... */
+        driver->driver.bus = NULL;
+        dev->driver = driver;
+        dev->gadget.dev.driver = &driver->driver;
+
+        spin_unlock_irqrestore(&dev->lock, flags);
+
+        retval = driver->bind(&dev->gadget);
+        if (retval) {
+                DBG(dev, "bind to driver %s --> %d\n",
+                                driver->driver.name, retval);
+                dev->driver = NULL;
+                dev->gadget.dev.driver = NULL;
+                return retval;
+        }
+
+        retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
+        if (retval)
+                goto err_unbind;
+
+        dev->usb_state = USB_STATE_ATTACHED;
+        dev->ep0_state = WAIT_FOR_SETUP;
+        dev->ep0_dir = USB_DIR_OUT;
+
+        /* enable interrupt and set controller to run state */
+        if (dev->got_irq)
+                langwell_udc_start(dev);
+
+        VDBG(dev, "After langwell_udc_start(), print all registers:\n");
+#ifdef  VERBOSE
+        print_all_registers(dev);
+#endif
+
+        INFO(dev, "register driver: %s\n", driver->driver.name);
+        VDBG(dev, "<--- %s()\n", __func__);
+        return 0;
+
+err_unbind:
+        driver->unbind(&dev->gadget);
+        dev->gadget.dev.driver = NULL;
+        dev->driver = NULL;
+
+        DBG(dev, "<--- %s()\n", __func__);
+        return retval;
+}
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+
+/* unregister gadget driver */
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+        struct langwell_udc     *dev = the_controller;
+        unsigned long           flags;
+
+        if (!dev)
+                return -ENODEV;
+
+        DBG(dev, "---> %s()\n", __func__);
+
+        if (unlikely(!driver || !driver->bind || !driver->unbind))
+                return -EINVAL;
+
+        /* unbind OTG transceiver */
+        if (dev->transceiver)
+                (void)otg_set_peripheral(dev->transceiver, 0);
+
+        /* disable interrupt and set controller to stop state */
+        langwell_udc_stop(dev);
+
+        dev->usb_state = USB_STATE_ATTACHED;
+        dev->ep0_state = WAIT_FOR_SETUP;
+        dev->ep0_dir = USB_DIR_OUT;
+
+        spin_lock_irqsave(&dev->lock, flags);
+
+        /* stop all usb activities */
+        dev->gadget.speed = USB_SPEED_UNKNOWN;
+        stop_activity(dev, driver);
+        spin_unlock_irqrestore(&dev->lock, flags);
+
+        /* unbind gadget driver */
+        driver->unbind(&dev->gadget);
+        dev->gadget.dev.driver = NULL;
+        dev->driver = NULL;
+
+        device_remove_file(&dev->pdev->dev, &dev_attr_function);
+
+        INFO(dev, "unregistered driver '%s'\n", driver->driver.name);
+        DBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * setup tripwire is used as a semaphore to ensure that the setup data
+ * payload is extracted from a dQH without being corrupted
+ */
+static void setup_tripwire(struct langwell_udc *dev)
+{
+        u32                     usbcmd,
+                                endptsetupstat;
+        unsigned long           timeout;
+        struct langwell_dqh     *dqh;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        /* ep0 OUT dQH */
+        dqh = &dev->ep_dqh[EP_DIR_OUT];
+
+        /* Write-Clear endptsetupstat */
+        endptsetupstat = readl(&dev->op_regs->endptsetupstat);
+        writel(endptsetupstat, &dev->op_regs->endptsetupstat);
+
+        /* wait until endptsetupstat is cleared */
+        timeout = jiffies + SETUPSTAT_TIMEOUT;
+        while (readl(&dev->op_regs->endptsetupstat)) {
+                if (time_after(jiffies, timeout)) {
+                        ERROR(dev, "setup_tripwire timeout\n");
+                        break;
+                }
+                cpu_relax();
+        }
+
+        /* while a hazard exists when setup packet arrives */
+        do {
+                /* set setup tripwire bit */
+                usbcmd = readl(&dev->op_regs->usbcmd);
+                writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
+
+                /* copy the setup packet to local buffer */
+                memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
+        } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
+
+        /* Write-Clear setup tripwire bit */
+        usbcmd = readl(&dev->op_regs->usbcmd);
+        writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
+
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* protocol ep0 stall, will automatically be cleared on new transaction */
+static void ep0_stall(struct langwell_udc *dev)
+{
+        u32     endptctrl;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        /* set TX and RX to stall */
+        endptctrl = readl(&dev->op_regs->endptctrl[0]);
+        endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
+        writel(endptctrl, &dev->op_regs->endptctrl[0]);
+
+        /* update ep0 state */
+        dev->ep0_state = WAIT_FOR_SETUP;
+        dev->ep0_dir = USB_DIR_OUT;
+
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* PRIME a status phase for ep0 */
+static int prime_status_phase(struct langwell_udc *dev, int dir)
+{
+        struct langwell_request *req;
+        struct langwell_ep      *ep;
+        int                     status = 0;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (dir == EP_DIR_IN)
+                dev->ep0_dir = USB_DIR_IN;
+        else
+                dev->ep0_dir = USB_DIR_OUT;
+
+        ep = &dev->ep[0];
+        dev->ep0_state = WAIT_FOR_OUT_STATUS;
+
+        req = dev->status_req;
+
+        req->ep = ep;
+        req->req.length = 0;
+        req->req.status = -EINPROGRESS;
+        req->req.actual = 0;
+        req->req.complete = NULL;
+        req->dtd_count = 0;
+
+        if (!req_to_dtd(req))
+                status = queue_dtd(ep, req);
+        else
+                return -ENOMEM;
+
+        if (status)
+                ERROR(dev, "can't queue ep0 status request\n");
+
+        list_add_tail(&req->queue, &ep->queue);
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return status;
+}
+
+
+/* SET_ADDRESS request routine */
+static void set_address(struct langwell_udc *dev, u16 value,
+                u16 index, u16 length)
+{
+        VDBG(dev, "---> %s()\n", __func__);
+
+        /* save the new address to device struct */
+        dev->dev_addr = (u8) value;
+        VDBG(dev, "dev->dev_addr = %d\n", dev->dev_addr);
+
+        /* update usb state */
+        dev->usb_state = USB_STATE_ADDRESS;
+
+        /* STATUS phase */
+        if (prime_status_phase(dev, EP_DIR_IN))
+                ep0_stall(dev);
+
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* return endpoint by windex */
+static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
+                u16 wIndex)
+{
+        struct langwell_ep              *ep;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
+                return &dev->ep[0];
+
+        list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
+                u8      bEndpointAddress;
+                if (!ep->desc)
+                        continue;
+
+                bEndpointAddress = ep->desc->bEndpointAddress;
+                if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
+                        continue;
+
+                if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
+                        == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
+                        return ep;
+        }
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return NULL;
+}
+
+
+/* return whether endpoint is stalled, 0: not stalled; 1: stalled */
+static int ep_is_stall(struct langwell_ep *ep)
+{
+        struct langwell_udc     *dev = ep->dev;
+        u32                     endptctrl;
+        int                     retval;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
+        if (is_in(ep))
+                retval = endptctrl & EPCTRL_TXS ? 1 : 0;
+        else
+                retval = endptctrl & EPCTRL_RXS ? 1 : 0;
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return retval;
+}
+
+
+/* GET_STATUS request routine */
+static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
+                u16 index, u16 length)
+{
+        struct langwell_request *req;
+        struct langwell_ep      *ep;
+        u16     status_data = 0;        /* 16 bits cpu view status data */
+        int     status = 0;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        ep = &dev->ep[0];
+
+        if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
+                /* get device status */
+                status_data = 1 << USB_DEVICE_SELF_POWERED;
+                status_data |= dev->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
+        } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
+                /* get interface status */
+                status_data = 0;
+        } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
+                /* get endpoint status */
+                struct langwell_ep      *epn;
+                epn = get_ep_by_windex(dev, index);
+                /* stall if endpoint doesn't exist */
+                if (!epn)
+                        goto stall;
+
+                status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
+        }
+
+        dev->ep0_dir = USB_DIR_IN;
+
+        /* borrow the per device status_req */
+        req = dev->status_req;
+
+        /* fill in the reqest structure */
+        *((u16 *) req->req.buf) = cpu_to_le16(status_data);
+        req->ep = ep;
+        req->req.length = 2;
+        req->req.status = -EINPROGRESS;
+        req->req.actual = 0;
+        req->req.complete = NULL;
+        req->dtd_count = 0;
+
+        /* prime the data phase */
+        if (!req_to_dtd(req))
+                status = queue_dtd(ep, req);
+        else                    /* no mem */
+                goto stall;
+
+        if (status) {
+                ERROR(dev, "response error on GET_STATUS request\n");
+                goto stall;
+        }
+
+        list_add_tail(&req->queue, &ep->queue);
+        dev->ep0_state = DATA_STATE_XMIT;
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return;
+stall:
+        ep0_stall(dev);
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* setup packet interrupt handler */
+static void handle_setup_packet(struct langwell_udc *dev,
+                struct usb_ctrlrequest *setup)
+{
+        u16     wValue = le16_to_cpu(setup->wValue);
+        u16     wIndex = le16_to_cpu(setup->wIndex);
+        u16     wLength = le16_to_cpu(setup->wLength);
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        /* ep0 fifo flush */
+        nuke(&dev->ep[0], -ESHUTDOWN);
+
+        DBG(dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
+                        setup->bRequestType, setup->bRequest,
+                        wValue, wIndex, wLength);
+
+        /* RNDIS gadget delegate */
+        if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
+                /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
+                goto delegate;
+        }
+
+        /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
+        if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
+                /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
+                goto delegate;
+        }
+
+        /* We process some stardard setup requests here */
+        switch (setup->bRequest) {
+        case USB_REQ_GET_STATUS:
+                DBG(dev, "SETUP: USB_REQ_GET_STATUS\n");
+                /* get status, DATA and STATUS phase */
+                if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
+                                        != (USB_DIR_IN | USB_TYPE_STANDARD))
+                        break;
+                get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
+                goto end;
+
+        case USB_REQ_SET_ADDRESS:
+                DBG(dev, "SETUP: USB_REQ_SET_ADDRESS\n");
+                /* STATUS phase */
+                if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
+                                                | USB_RECIP_DEVICE))
+                        break;
+                set_address(dev, wValue, wIndex, wLength);
+                goto end;
+
+        case USB_REQ_CLEAR_FEATURE:
+        case USB_REQ_SET_FEATURE:
+                /* STATUS phase */
+        {
+                int rc = -EOPNOTSUPP;
+                if (setup->bRequest == USB_REQ_SET_FEATURE)
+                        DBG(dev, "SETUP: USB_REQ_SET_FEATURE\n");
+                else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
+                        DBG(dev, "SETUP: USB_REQ_CLEAR_FEATURE\n");
+
+                if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
+                                == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
+                        struct langwell_ep      *epn;
+                        epn = get_ep_by_windex(dev, wIndex);
+                        /* stall if endpoint doesn't exist */
+                        if (!epn) {
+                                ep0_stall(dev);
+                                goto end;
+                        }
+
+                        if (wValue != 0 || wLength != 0
+                                        || epn->ep_num > dev->ep_max)
+                                break;
+
+                        spin_unlock(&dev->lock);
+                        rc = langwell_ep_set_halt(&epn->ep,
+                                        (setup->bRequest == USB_REQ_SET_FEATURE)
+                                                ? 1 : 0);
+                        spin_lock(&dev->lock);
+
+                } else if ((setup->bRequestType & (USB_RECIP_MASK
+                                | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
+                                | USB_TYPE_STANDARD)) {
+                        if (!gadget_is_otg(&dev->gadget))
+                                break;
+                        else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) {
+                                dev->gadget.b_hnp_enable = 1;
+#ifdef  OTG_TRANSCEIVER
+                                if (!dev->lotg->otg.default_a)
+                                        dev->lotg->hsm.b_hnp_enable = 1;
+#endif
+                        } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
+                                dev->gadget.a_hnp_support = 1;
+                        else if (setup->bRequest ==
+                                        USB_DEVICE_A_ALT_HNP_SUPPORT)
+                                dev->gadget.a_alt_hnp_support = 1;
+                        else
+                                break;
+                        rc = 0;
+                } else
+                        break;
+
+                if (rc == 0) {
+                        if (prime_status_phase(dev, EP_DIR_IN))
+                                ep0_stall(dev);
+                }
+                goto end;
+        }
+
+        case USB_REQ_GET_DESCRIPTOR:
+                DBG(dev, "SETUP: USB_REQ_GET_DESCRIPTOR\n");
+                goto delegate;
+
+        case USB_REQ_SET_DESCRIPTOR:
+                DBG(dev, "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
+                goto delegate;
+
+        case USB_REQ_GET_CONFIGURATION:
+                DBG(dev, "SETUP: USB_REQ_GET_CONFIGURATION\n");
+                goto delegate;
+
+        case USB_REQ_SET_CONFIGURATION:
+                DBG(dev, "SETUP: USB_REQ_SET_CONFIGURATION\n");
+                goto delegate;
+
+        case USB_REQ_GET_INTERFACE:
+                DBG(dev, "SETUP: USB_REQ_GET_INTERFACE\n");
+                goto delegate;
+
+        case USB_REQ_SET_INTERFACE:
+                DBG(dev, "SETUP: USB_REQ_SET_INTERFACE\n");
+                goto delegate;
+
+        case USB_REQ_SYNCH_FRAME:
+                DBG(dev, "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
+                goto delegate;
+
+        default:
+                /* delegate USB standard requests to the gadget driver */
+                goto delegate;
+delegate:
+                /* USB requests handled by gadget */
+                if (wLength) {
+                        /* DATA phase from gadget, STATUS phase from udc */
+                        dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
+                                        ?  USB_DIR_IN : USB_DIR_OUT;
+                        VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n",
+                                        dev->ep0_dir, wLength);
+                        spin_unlock(&dev->lock);
+                        if (dev->driver->setup(&dev->gadget,
+                                        &dev->local_setup_buff) < 0)
+                                ep0_stall(dev);
+                        spin_lock(&dev->lock);
+                        dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
+                                        ?  DATA_STATE_XMIT : DATA_STATE_RECV;
+                } else {
+                        /* no DATA phase, IN STATUS phase from gadget */
+                        dev->ep0_dir = USB_DIR_IN;
+                        VDBG(dev, "dev->ep0_dir = 0x%x, wLength = %d\n",
+                                        dev->ep0_dir, wLength);
+                        spin_unlock(&dev->lock);
+                        if (dev->driver->setup(&dev->gadget,
+                                        &dev->local_setup_buff) < 0)
+                                ep0_stall(dev);
+                        spin_lock(&dev->lock);
+                        dev->ep0_state = WAIT_FOR_OUT_STATUS;
+                }
+                break;
+        }
+end:
+        VDBG(dev, "<--- %s()\n", __func__);
+        return;
+}
+
+
+/* transfer completion, process endpoint request and free the completed dTDs
+ * for this request
+ */
+static int process_ep_req(struct langwell_udc *dev, int index,
+                struct langwell_request *curr_req)
+{
+        struct langwell_dtd     *curr_dtd;
+        struct langwell_dqh     *curr_dqh;
+        int                     td_complete, actual, remaining_length;
+        int                     i, dir;
+        u8                      dtd_status = 0;
+        int                     retval = 0;
+
+        curr_dqh = &dev->ep_dqh[index];
+        dir = index % 2;
+
+        curr_dtd = curr_req->head;
+        td_complete = 0;
+        actual = curr_req->req.length;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        for (i = 0; i < curr_req->dtd_count; i++) {
+                remaining_length = le16_to_cpu(curr_dtd->dtd_total);
+                actual -= remaining_length;
+
+                /* command execution states by dTD */
+                dtd_status = curr_dtd->dtd_status;
+
+                if (!dtd_status) {
+                        /* transfers completed successfully */
+                        if (!remaining_length) {
+                                td_complete++;
+                                VDBG(dev, "dTD transmitted successfully\n");
+                        } else {
+                                if (dir) {
+                                        VDBG(dev, "TX dTD remains data\n");
+                                        retval = -EPROTO;
+                                        break;
+
+                                } else {
+                                        td_complete++;
+                                        break;
+                                }
+                        }
+                } else {
+                        /* transfers completed with errors */
+                        if (dtd_status & DTD_STS_ACTIVE) {
+                                DBG(dev, "request not completed\n");
+                                retval = 1;
+                                return retval;
+                        } else if (dtd_status & DTD_STS_HALTED) {
+                                ERROR(dev, "dTD error %08x dQH[%d]\n",
+                                                dtd_status, index);
+                                /* clear the errors and halt condition */
+                                curr_dqh->dtd_status = 0;
+                                retval = -EPIPE;
+                                break;
+                        } else if (dtd_status & DTD_STS_DBE) {
+                                DBG(dev, "data buffer (overflow) error\n");
+                                retval = -EPROTO;
+                                break;
+                        } else if (dtd_status & DTD_STS_TRE) {
+                                DBG(dev, "transaction(ISO) error\n");
+                                retval = -EILSEQ;
+                                break;
+                        } else
+                                ERROR(dev, "unknown error (0x%x)!\n",
+                                                dtd_status);
+                }
+
+                if (i != curr_req->dtd_count - 1)
+                        curr_dtd = (struct langwell_dtd *)
+                                curr_dtd->next_dtd_virt;
+        }
+
+        if (retval)
+                return retval;
+
+        curr_req->req.actual = actual;
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+
+
+/* complete DATA or STATUS phase of ep0 prime status phase if needed */
+static void ep0_req_complete(struct langwell_udc *dev,
+                struct langwell_ep *ep0, struct langwell_request *req)
+{
+        u32     new_addr;
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (dev->usb_state == USB_STATE_ADDRESS) {
+                /* set the new address */
+                new_addr = (u32)dev->dev_addr;
+                writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
+
+                new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
+                VDBG(dev, "new_addr = %d\n", new_addr);
+        }
+
+        done(ep0, req, 0);
+
+        switch (dev->ep0_state) {
+        case DATA_STATE_XMIT:
+                /* receive status phase */
+                if (prime_status_phase(dev, EP_DIR_OUT))
+                        ep0_stall(dev);
+                break;
+        case DATA_STATE_RECV:
+                /* send status phase */
+                if (prime_status_phase(dev, EP_DIR_IN))
+                        ep0_stall(dev);
+                break;
+        case WAIT_FOR_OUT_STATUS:
+                dev->ep0_state = WAIT_FOR_SETUP;
+                break;
+        case WAIT_FOR_SETUP:
+                ERROR(dev, "unexpect ep0 packets\n");
+                break;
+        default:
+                ep0_stall(dev);
+                break;
+        }
+
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* USB transfer completion interrupt */
+static void handle_trans_complete(struct langwell_udc *dev)
+{
+        u32                     complete_bits;
+        int                     i, ep_num, dir, bit_mask, status;
+        struct langwell_ep      *epn;
+        struct langwell_request *curr_req, *temp_req;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        complete_bits = readl(&dev->op_regs->endptcomplete);
+        VDBG(dev, "endptcomplete register: 0x%08x\n", complete_bits);
+
+        /* Write-Clear the bits in endptcomplete register */
+        writel(complete_bits, &dev->op_regs->endptcomplete);
+
+        if (!complete_bits) {
+                DBG(dev, "complete_bits = 0\n");
+                goto done;
+        }
+
+        for (i = 0; i < dev->ep_max; i++) {
+                ep_num = i / 2;
+                dir = i % 2;
+
+                bit_mask = 1 << (ep_num + 16 * dir);
+
+                if (!(complete_bits & bit_mask))
+                        continue;
+
+                /* ep0 */
+                if (i == 1)
+                        epn = &dev->ep[0];
+                else
+                        epn = &dev->ep[i];
+
+                if (epn->name == NULL) {
+                        WARNING(dev, "invalid endpoint\n");
+                        continue;
+                }
+
+                if (i < 2)
+                        /* ep0 in and out */
+                        DBG(dev, "%s-%s transfer completed\n",
+                                        epn->name,
+                                        is_in(epn) ? "in" : "out");
+                else
+                        DBG(dev, "%s transfer completed\n", epn->name);
+
+                /* process the req queue until an uncomplete request */
+                list_for_each_entry_safe(curr_req, temp_req,
+                                &epn->queue, queue) {
+                        status = process_ep_req(dev, i, curr_req);
+                        VDBG(dev, "%s req status: %d\n", epn->name, status);
+
+                        if (status)
+                                break;
+
+                        /* write back status to req */
+                        curr_req->req.status = status;
+
+                        /* ep0 request completion */
+                        if (ep_num == 0) {
+                                ep0_req_complete(dev, epn, curr_req);
+                                break;
+                        } else {
+                                done(epn, curr_req, status);
+                        }
+                }
+        }
+done:
+        VDBG(dev, "<--- %s()\n", __func__);
+        return;
+}
+
+
+/* port change detect interrupt handler */
+static void handle_port_change(struct langwell_udc *dev)
+{
+        u32     portsc1, devlc;
+        u32     speed;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (dev->bus_reset)
+                dev->bus_reset = 0;
+
+        portsc1 = readl(&dev->op_regs->portsc1);
+        devlc = readl(&dev->op_regs->devlc);
+        VDBG(dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
+                        portsc1, devlc);
+
+        /* bus reset is finished */
+        if (!(portsc1 & PORTS_PR)) {
+                /* get the speed */
+                speed = LPM_PSPD(devlc);
+                switch (speed) {
+                case LPM_SPEED_HIGH:
+                        dev->gadget.speed = USB_SPEED_HIGH;
+                        break;
+                case LPM_SPEED_FULL:
+                        dev->gadget.speed = USB_SPEED_FULL;
+                        break;
+                case LPM_SPEED_LOW:
+                        dev->gadget.speed = USB_SPEED_LOW;
+                        break;
+                default:
+                        dev->gadget.speed = USB_SPEED_UNKNOWN;
+                        break;
+                }
+                VDBG(dev, "speed = %d, dev->gadget.speed = %d\n",
+                                speed, dev->gadget.speed);
+        }
+
+        /* LPM L0 to L1 */
+        if (dev->lpm && dev->lpm_state == LPM_L0)
+                if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
+                                INFO(dev, "LPM L0 to L1\n");
+                                dev->lpm_state = LPM_L1;
+                }
+
+        /* LPM L1 to L0, force resume or remote wakeup finished */
+        if (dev->lpm && dev->lpm_state == LPM_L1)
+                if (!(portsc1 & PORTS_SUSP)) {
+                        if (portsc1 & PORTS_SLP)
+                                INFO(dev, "LPM L1 to L0, force resume\n");
+                        else
+                                INFO(dev, "LPM L1 to L0, remote wakeup\n");
+
+                        dev->lpm_state = LPM_L0;
+                }
+
+        /* update USB state */
+        if (!dev->resume_state)
+                dev->usb_state = USB_STATE_DEFAULT;
+
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* USB reset interrupt handler */
+static void handle_usb_reset(struct langwell_udc *dev)
+{
+        u32             deviceaddr,
+                        endptsetupstat,
+                        endptcomplete;
+        unsigned long   timeout;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        /* Write-Clear the device address */
+        deviceaddr = readl(&dev->op_regs->deviceaddr);
+        writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
+
+        dev->dev_addr = 0;
+
+        /* clear usb state */
+        dev->resume_state = 0;
+
+        /* LPM L1 to L0, reset */
+        if (dev->lpm)
+                dev->lpm_state = LPM_L0;
+
+        dev->ep0_dir = USB_DIR_OUT;
+        dev->ep0_state = WAIT_FOR_SETUP;
+        dev->remote_wakeup = 0;         /* default to 0 on reset */
+        dev->gadget.b_hnp_enable = 0;
+        dev->gadget.a_hnp_support = 0;
+        dev->gadget.a_alt_hnp_support = 0;
+
+        /* Write-Clear all the setup token semaphores */
+        endptsetupstat = readl(&dev->op_regs->endptsetupstat);
+        writel(endptsetupstat, &dev->op_regs->endptsetupstat);
+
+        /* Write-Clear all the endpoint complete status bits */
+        endptcomplete = readl(&dev->op_regs->endptcomplete);
+        writel(endptcomplete, &dev->op_regs->endptcomplete);
+
+        /* wait until all endptprime bits cleared */
+        timeout = jiffies + PRIME_TIMEOUT;
+        while (readl(&dev->op_regs->endptprime)) {
+                if (time_after(jiffies, timeout)) {
+                        ERROR(dev, "USB reset timeout\n");
+                        break;
+                }
+                cpu_relax();
+        }
+
+        /* write 1s to endptflush register to clear any primed buffers */
+        writel((u32) ~0, &dev->op_regs->endptflush);
+
+        if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
+                VDBG(dev, "USB bus reset\n");
+                /* bus is reseting */
+                dev->bus_reset = 1;
+
+                /* reset all the queues, stop all USB activities */
+                stop_activity(dev, dev->driver);
+                dev->usb_state = USB_STATE_DEFAULT;
+        } else {
+                VDBG(dev, "device controller reset\n");
+                /* controller reset */
+                langwell_udc_reset(dev);
+
+                /* reset all the queues, stop all USB activities */
+                stop_activity(dev, dev->driver);
+
+                /* reset ep0 dQH and endptctrl */
+                ep0_reset(dev);
+
+                /* enable interrupt and set controller to run state */
+                langwell_udc_start(dev);
+
+                dev->usb_state = USB_STATE_ATTACHED;
+        }
+
+#ifdef  OTG_TRANSCEIVER
+        /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */
+        if (!dev->lotg->otg.default_a)
+                dev->lotg->hsm.b_hnp_enable = 0;
+#endif
+
+        VDBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* USB bus suspend/resume interrupt */
+static void handle_bus_suspend(struct langwell_udc *dev)
+{
+        u32             devlc;
+        DBG(dev, "---> %s()\n", __func__);
+
+        dev->resume_state = dev->usb_state;
+        dev->usb_state = USB_STATE_SUSPENDED;
+
+#ifdef  OTG_TRANSCEIVER
+        if (dev->lotg->otg.default_a) {
+                if (dev->lotg->hsm.b_bus_suspend_vld == 1) {
+                        dev->lotg->hsm.b_bus_suspend = 1;
+                        /* notify transceiver the state changes */
+                        if (spin_trylock(&dev->lotg->wq_lock)) {
+                                langwell_update_transceiver();
+                                spin_unlock(&dev->lotg->wq_lock);
+                        }
+                }
+                dev->lotg->hsm.b_bus_suspend_vld++;
+        } else {
+                if (!dev->lotg->hsm.a_bus_suspend) {
+                        dev->lotg->hsm.a_bus_suspend = 1;
+                        /* notify transceiver the state changes */
+                        if (spin_trylock(&dev->lotg->wq_lock)) {
+                                langwell_update_transceiver();
+                                spin_unlock(&dev->lotg->wq_lock);
+                        }
+                }
+        }
+#endif
+
+        /* report suspend to the driver */
+        if (dev->driver) {
+                if (dev->driver->suspend) {
+                        spin_unlock(&dev->lock);
+                        dev->driver->suspend(&dev->gadget);
+                        spin_lock(&dev->lock);
+                        DBG(dev, "suspend %s\n", dev->driver->driver.name);
+                }
+        }
+
+        /* enter PHY low power suspend */
+        devlc = readl(&dev->op_regs->devlc);
+        VDBG(dev, "devlc = 0x%08x\n", devlc);
+        devlc |= LPM_PHCD;
+        writel(devlc, &dev->op_regs->devlc);
+
+        DBG(dev, "<--- %s()\n", __func__);
+}
+
+
+static void handle_bus_resume(struct langwell_udc *dev)
+{
+        u32             devlc;
+        DBG(dev, "---> %s()\n", __func__);
+
+        dev->usb_state = dev->resume_state;
+        dev->resume_state = 0;
+
+        /* exit PHY low power suspend */
+        devlc = readl(&dev->op_regs->devlc);
+        VDBG(dev, "devlc = 0x%08x\n", devlc);
+        devlc &= ~LPM_PHCD;
+        writel(devlc, &dev->op_regs->devlc);
+
+#ifdef  OTG_TRANSCEIVER
+        if (dev->lotg->otg.default_a == 0)
+                dev->lotg->hsm.a_bus_suspend = 0;
+#endif
+
+        /* report resume to the driver */
+        if (dev->driver) {
+                if (dev->driver->resume) {
+                        spin_unlock(&dev->lock);
+                        dev->driver->resume(&dev->gadget);
+                        spin_lock(&dev->lock);
+                        DBG(dev, "resume %s\n", dev->driver->driver.name);
+                }
+        }
+
+        DBG(dev, "<--- %s()\n", __func__);
+}
+
+
+/* USB device controller interrupt handler */
+static irqreturn_t langwell_irq(int irq, void *_dev)
+{
+        struct langwell_udc     *dev = _dev;
+        u32                     usbsts,
+                                usbintr,
+                                irq_sts,
+                                portsc1;
+
+        VDBG(dev, "---> %s()\n", __func__);
+
+        if (dev->stopped) {
+                VDBG(dev, "handle IRQ_NONE\n");
+                VDBG(dev, "<--- %s()\n", __func__);
+                return IRQ_NONE;
+        }
+
+        spin_lock(&dev->lock);
+
+        /* USB status */
+        usbsts = readl(&dev->op_regs->usbsts);
+
+        /* USB interrupt enable */
+        usbintr = readl(&dev->op_regs->usbintr);
+
+        irq_sts = usbsts & usbintr;
+        VDBG(dev, "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
+                        usbsts, usbintr, irq_sts);
+
+        if (!irq_sts) {
+                VDBG(dev, "handle IRQ_NONE\n");
+                VDBG(dev, "<--- %s()\n", __func__);
+                spin_unlock(&dev->lock);
+                return IRQ_NONE;
+        }
+
+        /* Write-Clear interrupt status bits */
+        writel(irq_sts, &dev->op_regs->usbsts);
+
+        /* resume from suspend */
+        portsc1 = readl(&dev->op_regs->portsc1);
+        if (dev->usb_state == USB_STATE_SUSPENDED)
+                if (!(portsc1 & PORTS_SUSP))
+                        handle_bus_resume(dev);
+
+        /* USB interrupt */
+        if (irq_sts & STS_UI) {
+                VDBG(dev, "USB interrupt\n");
+
+                /* setup packet received from ep0 */
+                if (readl(&dev->op_regs->endptsetupstat)
+                                & EP0SETUPSTAT_MASK) {
+                        VDBG(dev, "USB SETUP packet received interrupt\n");
+                        /* setup tripwire semaphone */
+                        setup_tripwire(dev);
+                        handle_setup_packet(dev, &dev->local_setup_buff);
+                }
+
+                /* USB transfer completion */
+                if (readl(&dev->op_regs->endptcomplete)) {
+                        VDBG(dev, "USB transfer completion interrupt\n");
+                        handle_trans_complete(dev);
+                }
+        }
+
+        /* SOF received interrupt (for ISO transfer) */
+        if (irq_sts & STS_SRI) {
+                /* FIXME */
+                /* VDBG(dev, "SOF received interrupt\n"); */
+        }
+
+        /* port change detect interrupt */
+        if (irq_sts & STS_PCI) {
+                VDBG(dev, "port change detect interrupt\n");
+                handle_port_change(dev);
+        }
+
+        /* suspend interrrupt */
+        if (irq_sts & STS_SLI) {
+                VDBG(dev, "suspend interrupt\n");
+                handle_bus_suspend(dev);
+        }
+
+        /* USB reset interrupt */
+        if (irq_sts & STS_URI) {
+                VDBG(dev, "USB reset interrupt\n");
+                handle_usb_reset(dev);
+        }
+
+        /* USB error or system error interrupt */
+        if (irq_sts & (STS_UEI | STS_SEI)) {
+                /* FIXME */
+                WARNING(dev, "error IRQ, irq_sts: %x\n", irq_sts);
+        }
+
+        spin_unlock(&dev->lock);
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return IRQ_HANDLED;
+}
+
+
+/*-------------------------------------------------------------------------*/
+
+/* release device structure */
+static void gadget_release(struct device *_dev)
+{
+        struct langwell_udc     *dev = the_controller;
+
+        DBG(dev, "---> %s()\n", __func__);
+
+        complete(dev->done);
+
+        DBG(dev, "<--- %s()\n", __func__);
+        kfree(dev);
+}
+
+
+/* tear down the binding between this driver and the pci device */
+static void langwell_udc_remove(struct pci_dev *pdev)
+{
+        struct langwell_udc     *dev = the_controller;
+
+        DECLARE_COMPLETION(done);
+
+        BUG_ON(dev->driver);
+        DBG(dev, "---> %s()\n", __func__);
+
+        dev->done = &done;
+
+        /* free memory allocated in probe */
+        if (dev->dtd_pool)
+                dma_pool_destroy(dev->dtd_pool);
+
+        if (dev->status_req) {
+                kfree(dev->status_req->req.buf);
+                kfree(dev->status_req);
+        }
+
+        if (dev->ep_dqh)
+                dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
+                        dev->ep_dqh, dev->ep_dqh_dma);
+
+        kfree(dev->ep);
+
+        /* diable IRQ handler */
+        if (dev->got_irq)
+                free_irq(pdev->irq, dev);
+
+#ifndef OTG_TRANSCEIVER
+        if (dev->cap_regs)
+                iounmap(dev->cap_regs);
+
+        if (dev->region)
+                release_mem_region(pci_resource_start(pdev, 0),
+                                pci_resource_len(pdev, 0));
+
+        if (dev->enabled)
+                pci_disable_device(pdev);
+#else
+        if (dev->transceiver) {
+                otg_put_transceiver(dev->transceiver);
+                dev->transceiver = NULL;
+                dev->lotg = NULL;
+        }
+#endif
+
+        dev->cap_regs = NULL;
+
+        INFO(dev, "unbind\n");
+        DBG(dev, "<--- %s()\n", __func__);
+
+        device_unregister(&dev->gadget.dev);
+        device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
+
+#ifndef OTG_TRANSCEIVER
+        pci_set_drvdata(pdev, NULL);
+#endif
+
+        /* free dev, wait for the release() finished */
+        wait_for_completion(&done);
+
+        the_controller = NULL;
+}
+
+
+/*
+ * wrap this driver around the specified device, but
+ * don't respond over USB until a gadget driver binds to us.
+ */
+static int langwell_udc_probe(struct pci_dev *pdev,
+                const struct pci_device_id *id)
+{
+        struct langwell_udc     *dev;
+#ifndef OTG_TRANSCEIVER
+        unsigned long           resource, len;
+#endif
+        void                    __iomem *base = NULL;
+        size_t                  size;
+        int                     retval;
+
+        if (the_controller) {
+                dev_warn(&pdev->dev, "ignoring\n");
+                return -EBUSY;
+        }
+
+        /* alloc, and start init */
+        dev = kzalloc(sizeof *dev, GFP_KERNEL);
+        if (dev == NULL) {
+                retval = -ENOMEM;
+                goto error;
+        }
+
+        /* initialize device spinlock */
+        spin_lock_init(&dev->lock);
+
+        dev->pdev = pdev;
+        DBG(dev, "---> %s()\n", __func__);
+
+#ifdef  OTG_TRANSCEIVER
+        /* PCI device is already enabled by otg_transceiver driver */
+        dev->enabled = 1;
+
+        /* mem region and register base */
+        dev->region = 1;
+        dev->transceiver = otg_get_transceiver();
+        dev->lotg = otg_to_langwell(dev->transceiver);
+        base = dev->lotg->regs;
+#else
+        pci_set_drvdata(pdev, dev);
+
+        /* now all the pci goodies ... */
+        if (pci_enable_device(pdev) < 0) {
+                retval = -ENODEV;
+                goto error;
+        }
+        dev->enabled = 1;
+
+        /* control register: BAR 0 */
+        resource = pci_resource_start(pdev, 0);
+        len = pci_resource_len(pdev, 0);
+        if (!request_mem_region(resource, len, driver_name)) {
+                ERROR(dev, "controller already in use\n");
+                retval = -EBUSY;
+                goto error;
+        }
+        dev->region = 1;
+
+        base = ioremap_nocache(resource, len);
+#endif
+        if (base == NULL) {
+                ERROR(dev, "can't map memory\n");
+                retval = -EFAULT;
+                goto error;
+        }
+
+        dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
+        VDBG(dev, "dev->cap_regs: %p\n", dev->cap_regs);
+        dev->op_regs = (struct langwell_op_regs __iomem *)
+                (base + OP_REG_OFFSET);
+        VDBG(dev, "dev->op_regs: %p\n", dev->op_regs);
+
+        /* irq setup after old hardware is cleaned up */
+        if (!pdev->irq) {
+                ERROR(dev, "No IRQ. Check PCI setup!\n");
+                retval = -ENODEV;
+                goto error;
+        }
+
+#ifndef OTG_TRANSCEIVER
+        INFO(dev, "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
+                        pdev->irq, resource, len, base);
+        /* enables bus-mastering for device dev */
+        pci_set_master(pdev);
+
+        if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
+                                driver_name, dev) != 0) {
+                ERROR(dev, "request interrupt %d failed\n", pdev->irq);
+                retval = -EBUSY;
+                goto error;
+        }
+        dev->got_irq = 1;
+#endif
+
+        /* set stopped bit */
+        dev->stopped = 1;
+
+        /* capabilities and endpoint number */
+        dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
+        dev->dciversion = readw(&dev->cap_regs->dciversion);
+        dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
+        VDBG(dev, "dev->lpm: %d\n", dev->lpm);
+        VDBG(dev, "dev->dciversion: 0x%04x\n", dev->dciversion);
+        VDBG(dev, "dccparams: 0x%08x\n", readl(&dev->cap_regs->dccparams));
+        VDBG(dev, "dev->devcap: %d\n", dev->devcap);
+        if (!dev->devcap) {
+                ERROR(dev, "can't support device mode\n");
+                retval = -ENODEV;
+                goto error;
+        }
+
+        /* a pair of endpoints (out/in) for each address */
+        dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
+        VDBG(dev, "dev->ep_max: %d\n", dev->ep_max);
+
+        /* allocate endpoints memory */
+        dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
+                        GFP_KERNEL);
+        if (!dev->ep) {
+                ERROR(dev, "allocate endpoints memory failed\n");
+                retval = -ENOMEM;
+                goto error;
+        }
+
+        /* allocate device dQH memory */
+        size = dev->ep_max * sizeof(struct langwell_dqh);
+        VDBG(dev, "orig size = %d\n", size);
+        if (size < DQH_ALIGNMENT)
+                size = DQH_ALIGNMENT;
+        else if ((size % DQH_ALIGNMENT) != 0) {
+                size += DQH_ALIGNMENT + 1;
+                size &= ~(DQH_ALIGNMENT - 1);
+        }
+        dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
+                                        &dev->ep_dqh_dma, GFP_KERNEL);
+        if (!dev->ep_dqh) {
+                ERROR(dev, "allocate dQH memory failed\n");
+                retval = -ENOMEM;
+                goto error;
+        }
+        dev->ep_dqh_size = size;
+        VDBG(dev, "ep_dqh_size = %d\n", dev->ep_dqh_size);
+
+        /* initialize ep0 status request structure */
+        dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
+        if (!dev->status_req) {
+                ERROR(dev, "allocate status_req memory failed\n");
+                retval = -ENOMEM;
+                goto error;
+        }
+        INIT_LIST_HEAD(&dev->status_req->queue);
+
+        /* allocate a small amount of memory to get valid address */
+        dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
+        dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
+
+        dev->resume_state = USB_STATE_NOTATTACHED;
+        dev->usb_state = USB_STATE_POWERED;
+        dev->ep0_dir = USB_DIR_OUT;
+        dev->remote_wakeup = 0; /* default to 0 on reset */
+
+#ifndef OTG_TRANSCEIVER
+        /* reset device controller */
+        langwell_udc_reset(dev);
+#endif
+
+        /* initialize gadget structure */
+        dev->gadget.ops = &langwell_ops;        /* usb_gadget_ops */
+        dev->gadget.ep0 = &dev->ep[0].ep;       /* gadget ep0 */
+        INIT_LIST_HEAD(&dev->gadget.ep_list);   /* ep_list */
+        dev->gadget.speed = USB_SPEED_UNKNOWN;  /* speed */
+        dev->gadget.is_dualspeed = 1;           /* support dual speed */
+#ifdef  OTG_TRANSCEIVER
+        dev->gadget.is_otg = 1;                 /* support otg mode */
+#endif
+
+        /* the "gadget" abstracts/virtualizes the controller */
+        dev_set_name(&dev->gadget.dev, "gadget");
+        dev->gadget.dev.parent = &pdev->dev;
+        dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
+        dev->gadget.dev.release = gadget_release;
+        dev->gadget.name = driver_name;         /* gadget name */
+
+        /* controller endpoints reinit */
+        eps_reinit(dev);
+
+#ifndef OTG_TRANSCEIVER
+        /* reset ep0 dQH and endptctrl */
+        ep0_reset(dev);
+#endif
+
+        /* create dTD dma_pool resource */
+        dev->dtd_pool = dma_pool_create("langwell_dtd",
+                        &dev->pdev->dev,
+                        sizeof(struct langwell_dtd),
+                        DTD_ALIGNMENT,
+                        DMA_BOUNDARY);
+
+        if (!dev->dtd_pool) {
+                retval = -ENOMEM;
+                goto error;
+        }
+
+        /* done */
+        INFO(dev, "%s\n", driver_desc);
+        INFO(dev, "irq %d, pci mem %p\n", pdev->irq, base);
+        INFO(dev, "Driver version: " DRIVER_VERSION "\n");
+        INFO(dev, "Support (max) %d endpoints\n", dev->ep_max);
+        INFO(dev, "Device interface version: 0x%04x\n", dev->dciversion);
+        INFO(dev, "Controller mode: %s\n", dev->devcap ? "Device" : "Host");
+        INFO(dev, "Support USB LPM: %s\n", dev->lpm ? "Yes" : "No");
+
+        VDBG(dev, "After langwell_udc_probe(), print all registers:\n");
+#ifdef  VERBOSE
+        print_all_registers(dev);
+#endif
+
+        the_controller = dev;
+
+        retval = device_register(&dev->gadget.dev);
+        if (retval)
+                goto error;
+
+        retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
+        if (retval)
+                goto error;
+
+        VDBG(dev, "<--- %s()\n", __func__);
+        return 0;
+
+error:
+        if (dev) {
+                DBG(dev, "<--- %s()\n", __func__);
+                langwell_udc_remove(pdev);
+        }
+
+        return retval;
+}
+
+
+/* device controller suspend */
+static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+        struct langwell_udc     *dev = the_controller;
+        u32                     devlc;
+
+        DBG(dev, "---> %s()\n", __func__);
+
+        /* disable interrupt and set controller to stop state */
+        langwell_udc_stop(dev);
+
+        /* diable IRQ handler */
+        if (dev->got_irq)
+                free_irq(pdev->irq, dev);
+        dev->got_irq = 0;
+
+
+        /* save PCI state */
+        pci_save_state(pdev);
+
+        /* set device power state */
+        pci_set_power_state(pdev, PCI_D3hot);
+
+        /* enter PHY low power suspend */
+        devlc = readl(&dev->op_regs->devlc);
+        VDBG(dev, "devlc = 0x%08x\n", devlc);
+        devlc |= LPM_PHCD;
+        writel(devlc, &dev->op_regs->devlc);
+
+        DBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+
+
+/* device controller resume */
+static int langwell_udc_resume(struct pci_dev *pdev)
+{
+        struct langwell_udc     *dev = the_controller;
+        u32                     devlc;
+
+        DBG(dev, "---> %s()\n", __func__);
+
+        /* exit PHY low power suspend */
+        devlc = readl(&dev->op_regs->devlc);
+        VDBG(dev, "devlc = 0x%08x\n", devlc);
+        devlc &= ~LPM_PHCD;
+        writel(devlc, &dev->op_regs->devlc);
+
+        /* set device D0 power state */
+        pci_set_power_state(pdev, PCI_D0);
+
+        /* restore PCI state */
+        pci_restore_state(pdev);
+
+        /* enable IRQ handler */
+        if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED, driver_name, dev)
+                        != 0) {
+                ERROR(dev, "request interrupt %d failed\n", pdev->irq);
+                return -1;
+        }
+        dev->got_irq = 1;
+
+        /* reset and start controller to run state */
+        if (dev->stopped) {
+                /* reset device controller */
+                langwell_udc_reset(dev);
+
+                /* reset ep0 dQH and endptctrl */
+                ep0_reset(dev);
+
+                /* start device if gadget is loaded */
+                if (dev->driver)
+                        langwell_udc_start(dev);
+        }
+
+        /* reset USB status */
+        dev->usb_state = USB_STATE_ATTACHED;
+        dev->ep0_state = WAIT_FOR_SETUP;
+        dev->ep0_dir = USB_DIR_OUT;
+
+        DBG(dev, "<--- %s()\n", __func__);
+        return 0;
+}
+
+
+/* pci driver shutdown */
+static void langwell_udc_shutdown(struct pci_dev *pdev)
+{
+        struct langwell_udc     *dev = the_controller;
+        u32                     usbmode;
+
+        DBG(dev, "---> %s()\n", __func__);
+
+        /* reset controller mode to IDLE */
+        usbmode = readl(&dev->op_regs->usbmode);
+        DBG(dev, "usbmode = 0x%08x\n", usbmode);
+        usbmode &= (~3 | MODE_IDLE);
+        writel(usbmode, &dev->op_regs->usbmode);
+
+        DBG(dev, "<--- %s()\n", __func__);
+}
+
+/*-------------------------------------------------------------------------*/
+
+static const struct pci_device_id pci_ids[] = { {
+        .class =        ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
+        .class_mask =   ~0,
+        .vendor =       0x8086,
+        .device =       0x0811,
+        .subvendor =    PCI_ANY_ID,
+        .subdevice =    PCI_ANY_ID,
+}, { /* end: all zeroes */ }
+};
+
+
+MODULE_DEVICE_TABLE(pci, pci_ids);
+
+
+static struct pci_driver langwell_pci_driver = {
+        .name =         (char *) driver_name,
+        .id_table =     pci_ids,
+
+        .probe =        langwell_udc_probe,
+        .remove =       langwell_udc_remove,
+
+        /* device controller suspend/resume */
+        .suspend =      langwell_udc_suspend,
+        .resume =       langwell_udc_resume,
+
+        .shutdown =     langwell_udc_shutdown,
+};
+
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
+MODULE_VERSION(DRIVER_VERSION);
+MODULE_LICENSE("GPL");
+
+
+static int __init init(void)
+{
+#ifdef  OTG_TRANSCEIVER
+        return langwell_register_peripheral(&langwell_pci_driver);
+#else
+        return pci_register_driver(&langwell_pci_driver);
+#endif
+}
+module_init(init);
+
+
+static void __exit cleanup(void)
+{
+#ifdef  OTG_TRANSCEIVER
+        return langwell_unregister_peripheral(&langwell_pci_driver);
+#else
+        pci_unregister_driver(&langwell_pci_driver);
+#endif
+}
+module_exit(cleanup);
+
diff --git a/drivers/usb/gadget/langwell_udc.h b/drivers/usb/gadget/langwell_udc.h
new file mode 100644
index 000000000000..9719934e1c08
--- /dev/null
+++ b/drivers/usb/gadget/langwell_udc.h
@@ -0,0 +1,228 @@
+/*
+ * Intel Langwell USB Device Controller driver
+ * Copyright (C) 2008-2009, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/usb/langwell_udc.h>
+
+#if defined(CONFIG_USB_LANGWELL_OTG)
+#include <linux/usb/langwell_otg.h>
+#endif
+
+
+/*-------------------------------------------------------------------------*/
+
+/* driver data structures and utilities */
+
+/*
+ * dTD: Device Endpoint Transfer Descriptor
+ * describe to the device controller the location and quantity of
+ * data to be send/received for given transfer
+ */
+struct langwell_dtd {
+        u32     dtd_next;
+/* bits 31:5, next transfer element pointer */
+#define DTD_NEXT(d)     (((d)>>5)&0x7ffffff)
+#define DTD_NEXT_MASK   (0x7ffffff << 5)
+/* terminate */
+#define DTD_TERM        BIT(0)
+        /* bits 7:0, execution back states */
+        u32     dtd_status:8;
+#define DTD_STATUS(d)   (((d)>>0)&0xff)
+#define DTD_STS_ACTIVE  BIT(7)  /* active */
+#define DTD_STS_HALTED  BIT(6)  /* halted */
+#define DTD_STS_DBE     BIT(5)  /* data buffer error */
+#define DTD_STS_TRE     BIT(3)  /* transaction error  */
+        /* bits 9:8 */
+        u32     dtd_res0:2;
+        /* bits 11:10, multipier override */
+        u32     dtd_multo:2;
+#define DTD_MULTO       (BIT(11) | BIT(10))
+        /* bits 14:12 */
+        u32     dtd_res1:3;
+        /* bit 15, interrupt on complete */
+        u32     dtd_ioc:1;
+#define DTD_IOC         BIT(15)
+        /* bits 30:16, total bytes */
+        u32     dtd_total:15;
+#define DTD_TOTAL(d)    (((d)>>16)&0x7fff)
+#define DTD_MAX_TRANSFER_LENGTH 0x4000
+        /* bit 31 */
+        u32     dtd_res2:1;
+        /* dTD buffer pointer page 0 to 4 */
+        u32     dtd_buf[5];
+#define DTD_OFFSET_MASK 0xfff
+/* bits 31:12, buffer pointer */
+#define DTD_BUFFER(d)   (((d)>>12)&0x3ff)
+/* bits 11:0, current offset */
+#define DTD_C_OFFSET(d) (((d)>>0)&0xfff)
+/* bits 10:0, frame number */
+#define DTD_FRAME(d)    (((d)>>0)&0x7ff)
+
+        /* driver-private parts */
+
+        /* dtd dma address */
+        dma_addr_t              dtd_dma;
+        /* next dtd virtual address */
+        struct langwell_dtd     *next_dtd_virt;
+};
+
+
+/*
+ * dQH: Device Endpoint Queue Head
+ * describe where all transfers are managed
+ * 48-byte data structure, aligned on 64-byte boundary
+ *
+ * These are associated with dTD structure
+ */
+struct langwell_dqh {
+        /* endpoint capabilities and characteristics */
+        u32     dqh_res0:15;    /* bits 14:0 */
+        u32     dqh_ios:1;      /* bit 15, interrupt on setup */
+#define DQH_IOS         BIT(15)
+        u32     dqh_mpl:11;     /* bits 26:16, maximum packet length */
+#define DQH_MPL         (0x7ff << 16)
+        u32     dqh_res1:2;     /* bits 28:27 */
+        u32     dqh_zlt:1;      /* bit 29, zero length termination */
+#define DQH_ZLT         BIT(29)
+        u32     dqh_mult:2;     /* bits 31:30 */
+#define DQH_MULT        (BIT(30) | BIT(31))
+
+        /* current dTD pointer */
+        u32     dqh_current;    /* locate the transfer in progress */
+#define DQH_C_DTD(e)    \
+        (((e)>>5)&0x7ffffff)    /* bits 31:5, current dTD pointer */
+
+        /* transfer overlay, hardware parts of a struct langwell_dtd */
+        u32     dtd_next;
+        u32     dtd_status:8;   /* bits 7:0, execution back states */
+        u32     dtd_res0:2;     /* bits 9:8 */
+        u32     dtd_multo:2;    /* bits 11:10, multipier override */
+        u32     dtd_res1:3;     /* bits 14:12 */
+        u32     dtd_ioc:1;      /* bit 15, interrupt on complete */
+        u32     dtd_total:15;   /* bits 30:16, total bytes */
+        u32     dtd_res2:1;     /* bit 31 */
+        u32     dtd_buf[5];     /* dTD buffer pointer page 0 to 4 */
+
+        u32     dqh_res2;
+        struct usb_ctrlrequest  dqh_setup;      /* setup packet buffer */
+} __attribute__ ((aligned(64)));
+
+
+/* endpoint data structure */
+struct langwell_ep {
+        struct usb_ep           ep;
+        dma_addr_t              dma;
+        struct langwell_udc     *dev;
+        unsigned long           irqs;
+        struct list_head        queue;
+        struct langwell_dqh     *dqh;
+        const struct usb_endpoint_descriptor    *desc;
+        char                    name[14];
+        unsigned                stopped:1,
+                                ep_type:2,
+                                ep_num:8;
+};
+
+
+/* request data structure */
+struct langwell_request {
+        struct usb_request      req;
+        struct langwell_dtd     *dtd, *head, *tail;
+        struct langwell_ep      *ep;
+        dma_addr_t              dtd_dma;
+        struct list_head        queue;
+        unsigned                dtd_count;
+        unsigned                mapped:1;
+};
+
+
+/* ep0 transfer state */
+enum ep0_state {
+        WAIT_FOR_SETUP,
+        DATA_STATE_XMIT,
+        DATA_STATE_NEED_ZLP,
+        WAIT_FOR_OUT_STATUS,
+        DATA_STATE_RECV,
+};
+
+
+/* device suspend state */
+enum lpm_state {
+        LPM_L0, /* on */
+        LPM_L1, /* LPM L1 sleep */
+        LPM_L2, /* suspend */
+        LPM_L3, /* off */
+};
+
+
+/* device data structure */
+struct langwell_udc {
+        /* each pci device provides one gadget, several endpoints */
+        struct usb_gadget       gadget;
+        spinlock_t              lock;   /* device lock */
+        struct langwell_ep      *ep;
+        struct usb_gadget_driver        *driver;
+        struct otg_transceiver  *transceiver;
+        u8                      dev_addr;
+        u32                     usb_state;
+        u32                     resume_state;
+        u32                     bus_reset;
+        enum lpm_state          lpm_state;
+        enum ep0_state          ep0_state;
+        u32                     ep0_dir;
+        u16                     dciversion;
+        unsigned                ep_max;
+        unsigned                devcap:1,
+                                enabled:1,
+                                region:1,
+                                got_irq:1,
+                                powered:1,
+                                remote_wakeup:1,
+                                rate:1,
+                                is_reset:1,
+                                softconnected:1,
+                                vbus_active:1,
+                                suspended:1,
+                                stopped:1,
+                                lpm:1;  /* LPM capability */
+
+        /* pci state used to access those endpoints */
+        struct pci_dev          *pdev;
+
+        /* Langwell otg transceiver */
+        struct langwell_otg     *lotg;
+
+        /* control registers */
+        struct langwell_cap_regs        __iomem *cap_regs;
+        struct langwell_op_regs         __iomem *op_regs;
+
+        struct usb_ctrlrequest  local_setup_buff;
+        struct langwell_dqh     *ep_dqh;
+        size_t                  ep_dqh_size;
+        dma_addr_t              ep_dqh_dma;
+
+        /* ep0 status request */
+        struct langwell_request *status_req;
+
+        /* dma pool */
+        struct dma_pool         *dtd_pool;
+
+        /* make sure release() is done */
+        struct completion       *done;
+};
+
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c
index 8cc676ecbb23..1937d8c7b433 100644
--- a/drivers/usb/gadget/pxa27x_udc.c
+++ b/drivers/usb/gadget/pxa27x_udc.c
@@ -38,7 +38,6 @@
 #include <linux/usb.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
-#include <mach/pxa2xx-regs.h> /* FIXME: for PSSR */
 #include <mach/udc.h>
 
 #include "pxa27x_udc.h"
@@ -474,6 +473,23 @@ static inline void udc_clear_mask_UDCCR(struct pxa_udc *udc, int mask)
 }
 
 /**
+ * ep_write_UDCCSR - set bits in UDCCSR
+ * @udc: udc device
+ * @mask: bits to set in UDCCR
+ *
+ * Sets bits in UDCCSR (UDCCSR0 and UDCCSR*).
+ *
+ * A specific case is applied to ep0 : the ACM bit is always set to 1, for
+ * SET_INTERFACE and SET_CONFIGURATION.
+ */
+static inline void ep_write_UDCCSR(struct pxa_ep *ep, int mask)
+{
+        if (is_ep0(ep))
+                mask |= UDCCSR0_ACM;
+        udc_ep_writel(ep, UDCCSR, mask);
+}
+
+/**
  * ep_count_bytes_remain - get how many bytes in udc endpoint
  * @ep: udc endpoint
  *
@@ -861,7 +877,7 @@ static int read_packet(struct pxa_ep *ep, struct pxa27x_request *req)
                 *buf++ = udc_ep_readl(ep, UDCDR);
         req->req.actual += count;
 
-        udc_ep_writel(ep, UDCCSR, UDCCSR_PC);
+        ep_write_UDCCSR(ep, UDCCSR_PC);
 
         return count;
 }
@@ -969,12 +985,12 @@ static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
                 if (udccsr & UDCCSR_PC) {
                         ep_vdbg(ep, "Clearing Transmit Complete, udccsr=%x\n",
                                 udccsr);
-                        udc_ep_writel(ep, UDCCSR, UDCCSR_PC);
+                        ep_write_UDCCSR(ep, UDCCSR_PC);
                 }
                 if (udccsr & UDCCSR_TRN) {
                         ep_vdbg(ep, "Clearing Underrun on, udccsr=%x\n",
                                 udccsr);
-                        udc_ep_writel(ep, UDCCSR, UDCCSR_TRN);
+                        ep_write_UDCCSR(ep, UDCCSR_TRN);
                 }
 
                 count = write_packet(ep, req, max);
@@ -996,7 +1012,7 @@ static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
                 }
 
                 if (is_short)
-                        udc_ep_writel(ep, UDCCSR, UDCCSR_SP);
+                        ep_write_UDCCSR(ep, UDCCSR_SP);
 
                 /* requests complete when all IN data is in the FIFO */
                 if (is_last) {
@@ -1029,7 +1045,7 @@ static int read_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
 
         while (epout_has_pkt(ep)) {
                 count = read_packet(ep, req);
-                udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC);
+                ep_write_UDCCSR(ep, UDCCSR0_OPC);
                 inc_ep_stats_bytes(ep, count, !USB_DIR_IN);
 
                 is_short = (count < ep->fifo_size);
@@ -1074,7 +1090,7 @@ static int write_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
 
         /* Sends either a short packet or a 0 length packet */
         if (unlikely(is_short))
-                udc_ep_writel(ep, UDCCSR, UDCCSR0_IPR);
+                ep_write_UDCCSR(ep, UDCCSR0_IPR);
 
         ep_dbg(ep, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n",
                 count, is_short ? "/S" : "", is_last ? "/L" : "",
@@ -1277,7 +1293,7 @@ static int pxa_ep_set_halt(struct usb_ep *_ep, int value)
 
         /* FST, FEF bits are the same for control and non control endpoints */
         rc = 0;
-        udc_ep_writel(ep, UDCCSR, UDCCSR_FST | UDCCSR_FEF);
+        ep_write_UDCCSR(ep, UDCCSR_FST | UDCCSR_FEF);
         if (is_ep0(ep))
                 set_ep0state(ep->dev, STALL);
 
@@ -1343,7 +1359,7 @@ static void pxa_ep_fifo_flush(struct usb_ep *_ep)
                         udc_ep_readl(ep, UDCDR);
         } else {
                 /* most IN status is the same, but ISO can't stall */
-                udc_ep_writel(ep, UDCCSR,
+                ep_write_UDCCSR(ep,
                                 UDCCSR_PC | UDCCSR_FEF | UDCCSR_TRN
                                 | (EPXFERTYPE_is_ISO(ep) ? 0 : UDCCSR_SST));
         }
@@ -1728,6 +1744,7 @@ static void udc_enable(struct pxa_udc *udc)
         memset(&udc->stats, 0, sizeof(udc->stats));
 
         udc_set_mask_UDCCR(udc, UDCCR_UDE);
+        ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_ACM);
         udelay(2);
         if (udc_readl(udc, UDCCR) & UDCCR_EMCE)
                 dev_err(udc->dev, "Configuration errors, udc disabled\n");
@@ -1893,6 +1910,15 @@ static void handle_ep0_ctrl_req(struct pxa_udc *udc,
 
         nuke(ep, -EPROTO);
 
+        /*
+         * In the PXA320 manual, in the section about Back-to-Back setup
+         * packets, it describes this situation.  The solution is to set OPC to
+         * get rid of the status packet, and then continue with the setup
+         * packet. Generalize to pxa27x CPUs.
+         */
+        if (epout_has_pkt(ep) && (ep_count_bytes_remain(ep) == 0))
+                ep_write_UDCCSR(ep, UDCCSR0_OPC);
+
         /* read SETUP packet */
         for (i = 0; i < 2; i++) {
                 if (unlikely(ep_is_empty(ep)))
@@ -1919,7 +1945,7 @@ static void handle_ep0_ctrl_req(struct pxa_udc *udc,
                 set_ep0state(udc, OUT_DATA_STAGE);
 
         /* Tell UDC to enter Data Stage */
-        udc_ep_writel(ep, UDCCSR, UDCCSR0_SA | UDCCSR0_OPC);
+        ep_write_UDCCSR(ep, UDCCSR0_SA | UDCCSR0_OPC);
 
         i = udc->driver->setup(&udc->gadget, &u.r);
         if (i < 0)
@@ -1929,7 +1955,7 @@ out:
 stall:
         ep_dbg(ep, "protocol STALL, udccsr0=%03x err %d\n",
                 udc_ep_readl(ep, UDCCSR), i);
-        udc_ep_writel(ep, UDCCSR, UDCCSR0_FST | UDCCSR0_FTF);
+        ep_write_UDCCSR(ep, UDCCSR0_FST | UDCCSR0_FTF);
         set_ep0state(udc, STALL);
         goto out;
 }
@@ -1966,6 +1992,8 @@ stall:
  *     cleared by software.
  *   - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it
  *     before reading ep0.
+ *     This is true only for PXA27x. This is not true anymore for PXA3xx family
+ *     (check Back-to-Back setup packet in developers guide).
  *   - irq can be called on a "packet complete" event (opc_irq=1), while
  *     UDCCSR0_OPC is not yet raised (delta can be as big as 100ms
  *     from experimentation).
@@ -1998,7 +2026,7 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
         if (udccsr0 & UDCCSR0_SST) {
                 ep_dbg(ep, "clearing stall status\n");
                 nuke(ep, -EPIPE);
-                udc_ep_writel(ep, UDCCSR, UDCCSR0_SST);
+                ep_write_UDCCSR(ep, UDCCSR0_SST);
                 ep0_idle(udc);
         }
 
@@ -2023,7 +2051,7 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
                 break;
         case IN_DATA_STAGE:                     /* GET_DESCRIPTOR */
                 if (epout_has_pkt(ep))
-                        udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC);
+                        ep_write_UDCCSR(ep, UDCCSR0_OPC);
                 if (req && !ep_is_full(ep))
                         completed = write_ep0_fifo(ep, req);
                 if (completed)
@@ -2036,7 +2064,7 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
                         ep0_end_out_req(ep, req);
                 break;
         case STALL:
-                udc_ep_writel(ep, UDCCSR, UDCCSR0_FST);
+                ep_write_UDCCSR(ep, UDCCSR0_FST);
                 break;
         case IN_STATUS_STAGE:
                 /*
@@ -2131,6 +2159,7 @@ static void pxa27x_change_configuration(struct pxa_udc *udc, int config)
 
         set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
         udc->driver->setup(&udc->gadget, &req);
+        ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN);
 }
 
 /**
@@ -2159,6 +2188,7 @@ static void pxa27x_change_interface(struct pxa_udc *udc, int iface, int alt)
 
         set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
         udc->driver->setup(&udc->gadget, &req);
+        ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN);
 }
 
 /*
@@ -2280,7 +2310,7 @@ static void irq_udc_reset(struct pxa_udc *udc)
         memset(&udc->stats, 0, sizeof udc->stats);
 
         nuke(ep, -EPROTO);
-        udc_ep_writel(ep, UDCCSR, UDCCSR0_FTF | UDCCSR0_OPC);
+        ep_write_UDCCSR(ep, UDCCSR0_FTF | UDCCSR0_OPC);
         ep0_idle(udc);
 }
 
@@ -2479,6 +2509,12 @@ static void pxa_udc_shutdown(struct platform_device *_dev)
                 udc_disable(udc);
 }
 
+#ifdef CONFIG_CPU_PXA27x
+extern void pxa27x_clear_otgph(void);
+#else
+#define pxa27x_clear_otgph()   do {} while (0)
+#endif
+
 #ifdef CONFIG_PM
 /**
  * pxa_udc_suspend - Suspend udc device
@@ -2546,8 +2582,7 @@ static int pxa_udc_resume(struct platform_device *_dev)
          * Software must configure the USB OTG pad, UDC, and UHC
          * to the state they were in before entering sleep mode.
          */
-        if (cpu_is_pxa27x())
-                PSSR |= PSSR_OTGPH;
+        pxa27x_clear_otgph();
 
         return 0;
 }
@@ -2571,7 +2606,7 @@ static struct platform_driver udc_driver = {
 
 static int __init udc_init(void)
 {
-        if (!cpu_is_pxa27x())
+        if (!cpu_is_pxa27x() && !cpu_is_pxa3xx())
                 return -ENODEV;
 
         printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION);
diff --git a/drivers/usb/gadget/pxa27x_udc.h b/drivers/usb/gadget/pxa27x_udc.h
index db58125331da..e25225e26586 100644
--- a/drivers/usb/gadget/pxa27x_udc.h
+++ b/drivers/usb/gadget/pxa27x_udc.h
@@ -130,6 +130,8 @@
 #define UP2OCR_HXOE     (1 << 17)       /* Transceiver Output Enable */
 #define UP2OCR_SEOS     (1 << 24)       /* Single-Ended Output Select */
 
+#define UDCCSR0_ACM     (1 << 9)        /* Ack Control Mode */
+#define UDCCSR0_AREN    (1 << 8)        /* Ack Response Enable */
 #define UDCCSR0_SA      (1 << 7)        /* Setup Active */
 #define UDCCSR0_RNE     (1 << 6)        /* Receive FIFO Not Empty */
 #define UDCCSR0_FST     (1 << 5)        /* Force Stall */
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
new file mode 100644
index 000000000000..50c71aae2cc2
--- /dev/null
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -0,0 +1,3269 @@
+/* linux/drivers/usb/gadget/s3c-hsotg.c
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C USB2.0 High-speed / OtG driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+#include <mach/map.h>
+
+#include <plat/regs-usb-hsotg-phy.h>
+#include <plat/regs-usb-hsotg.h>
+#include <plat/regs-sys.h>
+#include <plat/udc-hs.h>
+
+#define DMA_ADDR_INVALID (~((dma_addr_t)0))
+
+/* EP0_MPS_LIMIT
+ *
+ * Unfortunately there seems to be a limit of the amount of data that can
+ * be transfered by IN transactions on EP0. This is either 127 bytes or 3
+ * packets (which practially means 1 packet and 63 bytes of data) when the
+ * MPS is set to 64.
+ *
+ * This means if we are wanting to move >127 bytes of data, we need to
+ * split the transactions up, but just doing one packet at a time does
+ * not work (this may be an implicit DATA0 PID on first packet of the
+ * transaction) and doing 2 packets is outside the controller's limits.
+ *
+ * If we try to lower the MPS size for EP0, then no transfers work properly
+ * for EP0, and the system will fail basic enumeration. As no cause for this
+ * has currently been found, we cannot support any large IN transfers for
+ * EP0.
+ */
+#define EP0_MPS_LIMIT   64
+
+struct s3c_hsotg;
+struct s3c_hsotg_req;
+
+/**
+ * struct s3c_hsotg_ep - driver endpoint definition.
+ * @ep: The gadget layer representation of the endpoint.
+ * @name: The driver generated name for the endpoint.
+ * @queue: Queue of requests for this endpoint.
+ * @parent: Reference back to the parent device structure.
+ * @req: The current request that the endpoint is processing. This is
+ *       used to indicate an request has been loaded onto the endpoint
+ *       and has yet to be completed (maybe due to data move, or simply
+ *       awaiting an ack from the core all the data has been completed).
+ * @debugfs: File entry for debugfs file for this endpoint.
+ * @lock: State lock to protect contents of endpoint.
+ * @dir_in: Set to true if this endpoint is of the IN direction, which
+ *          means that it is sending data to the Host.
+ * @index: The index for the endpoint registers.
+ * @name: The name array passed to the USB core.
+ * @halted: Set if the endpoint has been halted.
+ * @periodic: Set if this is a periodic ep, such as Interrupt
+ * @sent_zlp: Set if we've sent a zero-length packet.
+ * @total_data: The total number of data bytes done.
+ * @fifo_size: The size of the FIFO (for periodic IN endpoints)
+ * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
+ * @last_load: The offset of data for the last start of request.
+ * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
+ *
+ * This is the driver's state for each registered enpoint, allowing it
+ * to keep track of transactions that need doing. Each endpoint has a
+ * lock to protect the state, to try and avoid using an overall lock
+ * for the host controller as much as possible.
+ *
+ * For periodic IN endpoints, we have fifo_size and fifo_load to try
+ * and keep track of the amount of data in the periodic FIFO for each
+ * of these as we don't have a status register that tells us how much
+ * is in each of them.
+ */
+struct s3c_hsotg_ep {
+        struct usb_ep           ep;
+        struct list_head        queue;
+        struct s3c_hsotg        *parent;
+        struct s3c_hsotg_req    *req;
+        struct dentry           *debugfs;
+
+        spinlock_t              lock;
+
+        unsigned long           total_data;
+        unsigned int            size_loaded;
+        unsigned int            last_load;
+        unsigned int            fifo_load;
+        unsigned short          fifo_size;
+
+        unsigned char           dir_in;
+        unsigned char           index;
+
+        unsigned int            halted:1;
+        unsigned int            periodic:1;
+        unsigned int            sent_zlp:1;
+
+        char                    name[10];
+};
+
+#define S3C_HSOTG_EPS   (8+1)   /* limit to 9 for the moment */
+
+/**
+ * struct s3c_hsotg - driver state.
+ * @dev: The parent device supplied to the probe function
+ * @driver: USB gadget driver
+ * @plat: The platform specific configuration data.
+ * @regs: The memory area mapped for accessing registers.
+ * @regs_res: The resource that was allocated when claiming register space.
+ * @irq: The IRQ number we are using
+ * @debug_root: root directrory for debugfs.
+ * @debug_file: main status file for debugfs.
+ * @debug_fifo: FIFO status file for debugfs.
+ * @ep0_reply: Request used for ep0 reply.
+ * @ep0_buff: Buffer for EP0 reply data, if needed.
+ * @ctrl_buff: Buffer for EP0 control requests.
+ * @ctrl_req: Request for EP0 control packets.
+ * @eps: The endpoints being supplied to the gadget framework
+ */
+struct s3c_hsotg {
+        struct device            *dev;
+        struct usb_gadget_driver *driver;
+        struct s3c_hsotg_plat    *plat;
+
+        void __iomem            *regs;
+        struct resource         *regs_res;
+        int                     irq;
+
+        struct dentry           *debug_root;
+        struct dentry           *debug_file;
+        struct dentry           *debug_fifo;
+
+        struct usb_request      *ep0_reply;
+        struct usb_request      *ctrl_req;
+        u8                      ep0_buff[8];
+        u8                      ctrl_buff[8];
+
+        struct usb_gadget       gadget;
+        struct s3c_hsotg_ep     eps[];
+};
+
+/**
+ * struct s3c_hsotg_req - data transfer request
+ * @req: The USB gadget request
+ * @queue: The list of requests for the endpoint this is queued for.
+ * @in_progress: Has already had size/packets written to core
+ * @mapped: DMA buffer for this request has been mapped via dma_map_single().
+ */
+struct s3c_hsotg_req {
+        struct usb_request      req;
+        struct list_head        queue;
+        unsigned char           in_progress;
+        unsigned char           mapped;
+};
+
+/* conversion functions */
+static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
+{
+        return container_of(req, struct s3c_hsotg_req, req);
+}
+
+static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
+{
+        return container_of(ep, struct s3c_hsotg_ep, ep);
+}
+
+static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
+{
+        return container_of(gadget, struct s3c_hsotg, gadget);
+}
+
+static inline void __orr32(void __iomem *ptr, u32 val)
+{
+        writel(readl(ptr) | val, ptr);
+}
+
+static inline void __bic32(void __iomem *ptr, u32 val)
+{
+        writel(readl(ptr) & ~val, ptr);
+}
+
+/* forward decleration of functions */
+static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
+
+/**
+ * using_dma - return the DMA status of the driver.
+ * @hsotg: The driver state.
+ *
+ * Return true if we're using DMA.
+ *
+ * Currently, we have the DMA support code worked into everywhere
+ * that needs it, but the AMBA DMA implementation in the hardware can
+ * only DMA from 32bit aligned addresses. This means that gadgets such
+ * as the CDC Ethernet cannot work as they often pass packets which are
+ * not 32bit aligned.
+ *
+ * Unfortunately the choice to use DMA or not is global to the controller
+ * and seems to be only settable when the controller is being put through
+ * a core reset. This means we either need to fix the gadgets to take
+ * account of DMA alignment, or add bounce buffers (yuerk).
+ *
+ * Until this issue is sorted out, we always return 'false'.
+ */
+static inline bool using_dma(struct s3c_hsotg *hsotg)
+{
+        return false;   /* support is not complete */
+}
+
+/**
+ * s3c_hsotg_en_gsint - enable one or more of the general interrupt
+ * @hsotg: The device state
+ * @ints: A bitmask of the interrupts to enable
+ */
+static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
+{
+        u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
+        u32 new_gsintmsk;
+
+        new_gsintmsk = gsintmsk | ints;
+
+        if (new_gsintmsk != gsintmsk) {
+                dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
+                writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
+        }
+}
+
+/**
+ * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
+ * @hsotg: The device state
+ * @ints: A bitmask of the interrupts to enable
+ */
+static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
+{
+        u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
+        u32 new_gsintmsk;
+
+        new_gsintmsk = gsintmsk & ~ints;
+
+        if (new_gsintmsk != gsintmsk)
+                writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
+}
+
+/**
+ * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
+ * @hsotg: The device state
+ * @ep: The endpoint index
+ * @dir_in: True if direction is in.
+ * @en: The enable value, true to enable
+ *
+ * Set or clear the mask for an individual endpoint's interrupt
+ * request.
+ */
+static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
+                                 unsigned int ep, unsigned int dir_in,
+                                 unsigned int en)
+{
+        unsigned long flags;
+        u32 bit = 1 << ep;
+        u32 daint;
+
+        if (!dir_in)
+                bit <<= 16;
+
+        local_irq_save(flags);
+        daint = readl(hsotg->regs + S3C_DAINTMSK);
+        if (en)
+                daint |= bit;
+        else
+                daint &= ~bit;
+        writel(daint, hsotg->regs + S3C_DAINTMSK);
+        local_irq_restore(flags);
+}
+
+/**
+ * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
+ * @hsotg: The device instance.
+ */
+static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
+{
+        /* the ryu 2.6.24 release ahs
+           writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
+           writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
+                S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
+                hsotg->regs + S3C_GNPTXFSIZ);
+        */
+
+        /* set FIFO sizes to 2048/0x1C0 */
+
+        writel(2048, hsotg->regs + S3C_GRXFSIZ);
+        writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
+               S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
+               hsotg->regs + S3C_GNPTXFSIZ);
+}
+
+/**
+ * @ep: USB endpoint to allocate request for.
+ * @flags: Allocation flags
+ *
+ * Allocate a new USB request structure appropriate for the specified endpoint
+ */
+struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep, gfp_t flags)
+{
+        struct s3c_hsotg_req *req;
+
+        req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
+        if (!req)
+                return NULL;
+
+        INIT_LIST_HEAD(&req->queue);
+
+        req->req.dma = DMA_ADDR_INVALID;
+        return &req->req;
+}
+
+/**
+ * is_ep_periodic - return true if the endpoint is in periodic mode.
+ * @hs_ep: The endpoint to query.
+ *
+ * Returns true if the endpoint is in periodic mode, meaning it is being
+ * used for an Interrupt or ISO transfer.
+ */
+static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
+{
+        return hs_ep->periodic;
+}
+
+/**
+ * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint for the request
+ * @hs_req: The request being processed.
+ *
+ * This is the reverse of s3c_hsotg_map_dma(), called for the completion
+ * of a request to ensure the buffer is ready for access by the caller.
+*/
+static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
+                                struct s3c_hsotg_ep *hs_ep,
+                                struct s3c_hsotg_req *hs_req)
+{
+        struct usb_request *req = &hs_req->req;
+        enum dma_data_direction dir;
+
+        dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+
+        /* ignore this if we're not moving any data */
+        if (hs_req->req.length == 0)
+                return;
+
+        if (hs_req->mapped) {
+                /* we mapped this, so unmap and remove the dma */
+
+                dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
+
+                req->dma = DMA_ADDR_INVALID;
+                hs_req->mapped = 0;
+        } else {
+                dma_sync_single(hsotg->dev, req->dma, req->length, dir);
+        }
+}
+
+/**
+ * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
+ * @hsotg: The controller state.
+ * @hs_ep: The endpoint we're going to write for.
+ * @hs_req: The request to write data for.
+ *
+ * This is called when the TxFIFO has some space in it to hold a new
+ * transmission and we have something to give it. The actual setup of
+ * the data size is done elsewhere, so all we have to do is to actually
+ * write the data.
+ *
+ * The return value is zero if there is more space (or nothing was done)
+ * otherwise -ENOSPC is returned if the FIFO space was used up.
+ *
+ * This routine is only needed for PIO
+*/
+static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
+                                struct s3c_hsotg_ep *hs_ep,
+                                struct s3c_hsotg_req *hs_req)
+{
+        bool periodic = is_ep_periodic(hs_ep);
+        u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
+        int buf_pos = hs_req->req.actual;
+        int to_write = hs_ep->size_loaded;
+        void *data;
+        int can_write;
+        int pkt_round;
+
+        to_write -= (buf_pos - hs_ep->last_load);
+
+        /* if there's nothing to write, get out early */
+        if (to_write == 0)
+                return 0;
+
+        if (periodic) {
+                u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
+                int size_left;
+                int size_done;
+
+                /* work out how much data was loaded so we can calculate
+                 * how much data is left in the fifo. */
+
+                size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
+
+                dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
+                        __func__, size_left,
+                        hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
+
+                /* how much of the data has moved */
+                size_done = hs_ep->size_loaded - size_left;
+
+                /* how much data is left in the fifo */
+                can_write = hs_ep->fifo_load - size_done;
+                dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
+                        __func__, can_write);
+
+                can_write = hs_ep->fifo_size - can_write;
+                dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
+                        __func__, can_write);
+
+                if (can_write <= 0) {
+                        s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
+                        return -ENOSPC;
+                }
+        } else {
+                if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
+                        dev_dbg(hsotg->dev,
+                                "%s: no queue slots available (0x%08x)\n",
+                                __func__, gnptxsts);
+
+                        s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
+                        return -ENOSPC;
+                }
+
+                can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
+        }
+
+        dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
+                 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
+
+        /* limit to 512 bytes of data, it seems at least on the non-periodic
+         * FIFO, requests of >512 cause the endpoint to get stuck with a
+         * fragment of the end of the transfer in it.
+         */
+        if (can_write > 512)
+                can_write = 512;
+
+        /* see if we can write data */
+
+        if (to_write > can_write) {
+                to_write = can_write;
+                pkt_round = to_write % hs_ep->ep.maxpacket;
+
+                /* Not sure, but we probably shouldn't be writing partial
+                 * packets into the FIFO, so round the write down to an
+                 * exact number of packets.
+                 *
+                 * Note, we do not currently check to see if we can ever
+                 * write a full packet or not to the FIFO.
+                 */
+
+                if (pkt_round)
+                        to_write -= pkt_round;
+
+                /* enable correct FIFO interrupt to alert us when there
+                 * is more room left. */
+
+                s3c_hsotg_en_gsint(hsotg,
+                                   periodic ? S3C_GINTSTS_PTxFEmp :
+                                   S3C_GINTSTS_NPTxFEmp);
+        }
+
+        dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
+                 to_write, hs_req->req.length, can_write, buf_pos);
+
+        if (to_write <= 0)
+                return -ENOSPC;
+
+        hs_req->req.actual = buf_pos + to_write;
+        hs_ep->total_data += to_write;
+
+        if (periodic)
+                hs_ep->fifo_load += to_write;
+
+        to_write = DIV_ROUND_UP(to_write, 4);
+        data = hs_req->req.buf + buf_pos;
+
+        writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
+
+        return (to_write >= can_write) ? -ENOSPC : 0;
+}
+
+/**
+ * get_ep_limit - get the maximum data legnth for this endpoint
+ * @hs_ep: The endpoint
+ *
+ * Return the maximum data that can be queued in one go on a given endpoint
+ * so that transfers that are too long can be split.
+ */
+static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
+{
+        int index = hs_ep->index;
+        unsigned maxsize;
+        unsigned maxpkt;
+
+        if (index != 0) {
+                maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
+                maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
+        } else {
+                if (hs_ep->dir_in) {
+                        /* maxsize = S3C_DIEPTSIZ0_XferSize_LIMIT + 1; */
+                        maxsize = 64+64+1;
+                        maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
+                } else {
+                        maxsize = 0x3f;
+                        maxpkt = 2;
+                }
+        }
+
+        /* we made the constant loading easier above by using +1 */
+        maxpkt--;
+        maxsize--;
+
+        /* constrain by packet count if maxpkts*pktsize is greater
+         * than the length register size. */
+
+        if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
+                maxsize = maxpkt * hs_ep->ep.maxpacket;
+
+        return maxsize;
+}
+
+/**
+ * s3c_hsotg_start_req - start a USB request from an endpoint's queue
+ * @hsotg: The controller state.
+ * @hs_ep: The endpoint to process a request for
+ * @hs_req: The request to start.
+ * @continuing: True if we are doing more for the current request.
+ *
+ * Start the given request running by setting the endpoint registers
+ * appropriately, and writing any data to the FIFOs.
+ */
+static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
+                                struct s3c_hsotg_ep *hs_ep,
+                                struct s3c_hsotg_req *hs_req,
+                                bool continuing)
+{
+        struct usb_request *ureq = &hs_req->req;
+        int index = hs_ep->index;
+        int dir_in = hs_ep->dir_in;
+        u32 epctrl_reg;
+        u32 epsize_reg;
+        u32 epsize;
+        u32 ctrl;
+        unsigned length;
+        unsigned packets;
+        unsigned maxreq;
+
+        if (index != 0) {
+                if (hs_ep->req && !continuing) {
+                        dev_err(hsotg->dev, "%s: active request\n", __func__);
+                        WARN_ON(1);
+                        return;
+                } else if (hs_ep->req != hs_req && continuing) {
+                        dev_err(hsotg->dev,
+                                "%s: continue different req\n", __func__);
+                        WARN_ON(1);
+                        return;
+                }
+        }
+
+        epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
+        epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
+
+        dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
+                __func__, readl(hsotg->regs + epctrl_reg), index,
+                hs_ep->dir_in ? "in" : "out");
+
+        length = ureq->length - ureq->actual;
+
+        if (0)
+                dev_dbg(hsotg->dev,
+                        "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
+                        ureq->buf, length, ureq->dma,
+                        ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
+
+        maxreq = get_ep_limit(hs_ep);
+        if (length > maxreq) {
+                int round = maxreq % hs_ep->ep.maxpacket;
+
+                dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
+                        __func__, length, maxreq, round);
+
+                /* round down to multiple of packets */
+                if (round)
+                        maxreq -= round;
+
+                length = maxreq;
+        }
+
+        if (length)
+                packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
+        else
+                packets = 1;    /* send one packet if length is zero. */
+
+        if (dir_in && index != 0)
+                epsize = S3C_DxEPTSIZ_MC(1);
+        else
+                epsize = 0;
+
+        if (index != 0 && ureq->zero) {
+                /* test for the packets being exactly right for the
+                 * transfer */
+
+                if (length == (packets * hs_ep->ep.maxpacket))
+                        packets++;
+        }
+
+        epsize |= S3C_DxEPTSIZ_PktCnt(packets);
+        epsize |= S3C_DxEPTSIZ_XferSize(length);
+
+        dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
+                __func__, packets, length, ureq->length, epsize, epsize_reg);
+
+        /* store the request as the current one we're doing */
+        hs_ep->req = hs_req;
+
+        /* write size / packets */
+        writel(epsize, hsotg->regs + epsize_reg);
+
+        ctrl = readl(hsotg->regs + epctrl_reg);
+
+        if (ctrl & S3C_DxEPCTL_Stall) {
+                dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
+
+                /* not sure what we can do here, if it is EP0 then we should
+                 * get this cleared once the endpoint has transmitted the
+                 * STALL packet, otherwise it needs to be cleared by the
+                 * host.
+                 */
+        }
+
+        if (using_dma(hsotg)) {
+                unsigned int dma_reg;
+
+                /* write DMA address to control register, buffer already
+                 * synced by s3c_hsotg_ep_queue().  */
+
+                dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
+                writel(ureq->dma, hsotg->regs + dma_reg);
+
+                dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
+                        __func__, ureq->dma, dma_reg);
+        }
+
+        ctrl |= S3C_DxEPCTL_EPEna;      /* ensure ep enabled */
+        ctrl |= S3C_DxEPCTL_USBActEp;
+        ctrl |= S3C_DxEPCTL_CNAK;       /* clear NAK set by core */
+
+        dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
+        writel(ctrl, hsotg->regs + epctrl_reg);
+
+        /* set these, it seems that DMA support increments past the end
+         * of the packet buffer so we need to calculate the length from
+         * this information. */
+        hs_ep->size_loaded = length;
+        hs_ep->last_load = ureq->actual;
+
+        if (dir_in && !using_dma(hsotg)) {
+                /* set these anyway, we may need them for non-periodic in */
+                hs_ep->fifo_load = 0;
+
+                s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
+        }
+
+        /* clear the INTknTXFEmpMsk when we start request, more as a aide
+         * to debugging to see what is going on. */
+        if (dir_in)
+                writel(S3C_DIEPMSK_INTknTXFEmpMsk,
+                       hsotg->regs + S3C_DIEPINT(index));
+
+        /* Note, trying to clear the NAK here causes problems with transmit
+         * on the S3C6400 ending up with the TXFIFO becomming full. */
+
+        /* check ep is enabled */
+        if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
+                dev_warn(hsotg->dev,
+                         "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
+                         index, readl(hsotg->regs + epctrl_reg));
+
+        dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
+                __func__, readl(hsotg->regs + epctrl_reg));
+}
+
+/**
+ * s3c_hsotg_map_dma - map the DMA memory being used for the request
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint the request is on.
+ * @req: The request being processed.
+ *
+ * We've been asked to queue a request, so ensure that the memory buffer
+ * is correctly setup for DMA. If we've been passed an extant DMA address
+ * then ensure the buffer has been synced to memory. If our buffer has no
+ * DMA memory, then we map the memory and mark our request to allow us to
+ * cleanup on completion.
+*/
+static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
+                             struct s3c_hsotg_ep *hs_ep,
+                             struct usb_request *req)
+{
+        enum dma_data_direction dir;
+        struct s3c_hsotg_req *hs_req = our_req(req);
+
+        dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+
+        /* if the length is zero, ignore the DMA data */
+        if (hs_req->req.length == 0)
+                return 0;
+
+        if (req->dma == DMA_ADDR_INVALID) {
+                dma_addr_t dma;
+
+                dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
+
+                if (unlikely(dma_mapping_error(hsotg->dev, dma)))
+                        goto dma_error;
+
+                if (dma & 3) {
+                        dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
+                                __func__);
+
+                        dma_unmap_single(hsotg->dev, dma, req->length, dir);
+                        return -EINVAL;
+                }
+
+                hs_req->mapped = 1;
+                req->dma = dma;
+        } else {
+                dma_sync_single(hsotg->dev, req->dma, req->length, dir);
+                hs_req->mapped = 0;
+        }
+
+        return 0;
+
+dma_error:
+        dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
+                __func__, req->buf, req->length);
+
+        return -EIO;
+}
+
+static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
+                              gfp_t gfp_flags)
+{
+        struct s3c_hsotg_req *hs_req = our_req(req);
+        struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+        struct s3c_hsotg *hs = hs_ep->parent;
+        unsigned long irqflags;
+        bool first;
+
+        dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
+                ep->name, req, req->length, req->buf, req->no_interrupt,
+                req->zero, req->short_not_ok);
+
+        /* initialise status of the request */
+        INIT_LIST_HEAD(&hs_req->queue);
+        req->actual = 0;
+        req->status = -EINPROGRESS;
+
+        /* if we're using DMA, sync the buffers as necessary */
+        if (using_dma(hs)) {
+                int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
+                if (ret)
+                        return ret;
+        }
+
+        spin_lock_irqsave(&hs_ep->lock, irqflags);
+
+        first = list_empty(&hs_ep->queue);
+        list_add_tail(&hs_req->queue, &hs_ep->queue);
+
+        if (first)
+                s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
+
+        spin_unlock_irqrestore(&hs_ep->lock, irqflags);
+
+        return 0;
+}
+
+static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
+                                      struct usb_request *req)
+{
+        struct s3c_hsotg_req *hs_req = our_req(req);
+
+        kfree(hs_req);
+}
+
+/**
+ * s3c_hsotg_complete_oursetup - setup completion callback
+ * @ep: The endpoint the request was on.
+ * @req: The request completed.
+ *
+ * Called on completion of any requests the driver itself
+ * submitted that need cleaning up.
+ */
+static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
+                                        struct usb_request *req)
+{
+        struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+        struct s3c_hsotg *hsotg = hs_ep->parent;
+
+        dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
+
+        s3c_hsotg_ep_free_request(ep, req);
+}
+
+/**
+ * ep_from_windex - convert control wIndex value to endpoint
+ * @hsotg: The driver state.
+ * @windex: The control request wIndex field (in host order).
+ *
+ * Convert the given wIndex into a pointer to an driver endpoint
+ * structure, or return NULL if it is not a valid endpoint.
+*/
+static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
+                                           u32 windex)
+{
+        struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
+        int dir = (windex & USB_DIR_IN) ? 1 : 0;
+        int idx = windex & 0x7F;
+
+        if (windex >= 0x100)
+                return NULL;
+
+        if (idx > S3C_HSOTG_EPS)
+                return NULL;
+
+        if (idx && ep->dir_in != dir)
+                return NULL;
+
+        return ep;
+}
+
+/**
+ * s3c_hsotg_send_reply - send reply to control request
+ * @hsotg: The device state
+ * @ep: Endpoint 0
+ * @buff: Buffer for request
+ * @length: Length of reply.
+ *
+ * Create a request and queue it on the given endpoint. This is useful as
+ * an internal method of sending replies to certain control requests, etc.
+ */
+static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
+                                struct s3c_hsotg_ep *ep,
+                                void *buff,
+                                int length)
+{
+        struct usb_request *req;
+        int ret;
+
+        dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
+
+        req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
+        hsotg->ep0_reply = req;
+        if (!req) {
+                dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
+                return -ENOMEM;
+        }
+
+        req->buf = hsotg->ep0_buff;
+        req->length = length;
+        req->zero = 1; /* always do zero-length final transfer */
+        req->complete = s3c_hsotg_complete_oursetup;
+
+        if (length)
+                memcpy(req->buf, buff, length);
+        else
+                ep->sent_zlp = 1;
+
+        ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
+        if (ret) {
+                dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
+                return ret;
+        }
+
+        return 0;
+}
+
+/**
+ * s3c_hsotg_process_req_status - process request GET_STATUS
+ * @hsotg: The device state
+ * @ctrl: USB control request
+ */
+static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
+                                        struct usb_ctrlrequest *ctrl)
+{
+        struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
+        struct s3c_hsotg_ep *ep;
+        __le16 reply;
+        int ret;
+
+        dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
+
+        if (!ep0->dir_in) {
+                dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
+                return -EINVAL;
+        }
+
+        switch (ctrl->bRequestType & USB_RECIP_MASK) {
+        case USB_RECIP_DEVICE:
+                reply = cpu_to_le16(0); /* bit 0 => self powered,
+                                         * bit 1 => remote wakeup */
+                break;
+
+        case USB_RECIP_INTERFACE:
+                /* currently, the data result should be zero */
+                reply = cpu_to_le16(0);
+                break;
+
+        case USB_RECIP_ENDPOINT:
+                ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
+                if (!ep)
+                        return -ENOENT;
+
+                reply = cpu_to_le16(ep->halted ? 1 : 0);
+                break;
+
+        default:
+                return 0;
+        }
+
+        if (le16_to_cpu(ctrl->wLength) != 2)
+                return -EINVAL;
+
+        ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
+        if (ret) {
+                dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
+                return ret;
+        }
+
+        return 1;
+}
+
+static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
+
+/**
+ * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
+ * @hsotg: The device state
+ * @ctrl: USB control request
+ */
+static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
+                                         struct usb_ctrlrequest *ctrl)
+{
+        bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
+        struct s3c_hsotg_ep *ep;
+
+        dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
+                __func__, set ? "SET" : "CLEAR");
+
+        if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
+                ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
+                if (!ep) {
+                        dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
+                                __func__, le16_to_cpu(ctrl->wIndex));
+                        return -ENOENT;
+                }
+
+                switch (le16_to_cpu(ctrl->wValue)) {
+                case USB_ENDPOINT_HALT:
+                        s3c_hsotg_ep_sethalt(&ep->ep, set);
+                        break;
+
+                default:
+                        return -ENOENT;
+                }
+        } else
+                return -ENOENT;  /* currently only deal with endpoint */
+
+        return 1;
+}
+
+/**
+ * s3c_hsotg_process_control - process a control request
+ * @hsotg: The device state
+ * @ctrl: The control request received
+ *
+ * The controller has received the SETUP phase of a control request, and
+ * needs to work out what to do next (and whether to pass it on to the
+ * gadget driver).
+ */
+static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
+                                      struct usb_ctrlrequest *ctrl)
+{
+        struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
+        int ret = 0;
+        u32 dcfg;
+
+        ep0->sent_zlp = 0;
+
+        dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
+                 ctrl->bRequest, ctrl->bRequestType,
+                 ctrl->wValue, ctrl->wLength);
+
+        /* record the direction of the request, for later use when enquing
+         * packets onto EP0. */
+
+        ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
+        dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
+
+        /* if we've no data with this request, then the last part of the
+         * transaction is going to implicitly be IN. */
+        if (ctrl->wLength == 0)
+                ep0->dir_in = 1;
+
+        if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
+                switch (ctrl->bRequest) {
+                case USB_REQ_SET_ADDRESS:
+                        dcfg = readl(hsotg->regs + S3C_DCFG);
+                        dcfg &= ~S3C_DCFG_DevAddr_MASK;
+                        dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
+                        writel(dcfg, hsotg->regs + S3C_DCFG);
+
+                        dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
+
+                        ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
+                        return;
+
+                case USB_REQ_GET_STATUS:
+                        ret = s3c_hsotg_process_req_status(hsotg, ctrl);
+                        break;
+
+                case USB_REQ_CLEAR_FEATURE:
+                case USB_REQ_SET_FEATURE:
+                        ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
+                        break;
+                }
+        }
+
+        /* as a fallback, try delivering it to the driver to deal with */
+
+        if (ret == 0 && hsotg->driver) {
+                ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
+                if (ret < 0)
+                        dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
+        }
+
+        if (ret > 0) {
+                if (!ep0->dir_in) {
+                        /* need to generate zlp in reply or take data */
+                        /* todo - deal with any data we might be sent? */
+                        ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
+                }
+        }
+
+        /* the request is either unhandlable, or is not formatted correctly
+         * so respond with a STALL for the status stage to indicate failure.
+         */
+
+        if (ret < 0) {
+                u32 reg;
+                u32 ctrl;
+
+                dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
+                reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
+
+                /* S3C_DxEPCTL_Stall will be cleared by EP once it has
+                 * taken effect, so no need to clear later. */
+
+                ctrl = readl(hsotg->regs + reg);
+                ctrl |= S3C_DxEPCTL_Stall;
+                ctrl |= S3C_DxEPCTL_CNAK;
+                writel(ctrl, hsotg->regs + reg);
+
+                dev_dbg(hsotg->dev,
+                        "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
+                        ctrl, reg, readl(hsotg->regs + reg));
+
+                /* don't belive we need to anything more to get the EP
+                 * to reply with a STALL packet */
+        }
+}
+
+static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
+
+/**
+ * s3c_hsotg_complete_setup - completion of a setup transfer
+ * @ep: The endpoint the request was on.
+ * @req: The request completed.
+ *
+ * Called on completion of any requests the driver itself submitted for
+ * EP0 setup packets
+ */
+static void s3c_hsotg_complete_setup(struct usb_ep *ep,
+                                     struct usb_request *req)
+{
+        struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+        struct s3c_hsotg *hsotg = hs_ep->parent;
+
+        if (req->status < 0) {
+                dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
+                return;
+        }
+
+        if (req->actual == 0)
+                s3c_hsotg_enqueue_setup(hsotg);
+        else
+                s3c_hsotg_process_control(hsotg, req->buf);
+}
+
+/**
+ * s3c_hsotg_enqueue_setup - start a request for EP0 packets
+ * @hsotg: The device state.
+ *
+ * Enqueue a request on EP0 if necessary to received any SETUP packets
+ * received from the host.
+ */
+static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
+{
+        struct usb_request *req = hsotg->ctrl_req;
+        struct s3c_hsotg_req *hs_req = our_req(req);
+        int ret;
+
+        dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
+
+        req->zero = 0;
+        req->length = 8;
+        req->buf = hsotg->ctrl_buff;
+        req->complete = s3c_hsotg_complete_setup;
+
+        if (!list_empty(&hs_req->queue)) {
+                dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
+                return;
+        }
+
+        hsotg->eps[0].dir_in = 0;
+
+        ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
+        if (ret < 0) {
+                dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
+                /* Don't think there's much we can do other than watch the
+                 * driver fail. */
+        }
+}
+
+/**
+ * get_ep_head - return the first request on the endpoint
+ * @hs_ep: The controller endpoint to get
+ *
+ * Get the first request on the endpoint.
+*/
+static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
+{
+        if (list_empty(&hs_ep->queue))
+                return NULL;
+
+        return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
+}
+
+/**
+ * s3c_hsotg_complete_request - complete a request given to us
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint the request was on.
+ * @hs_req: The request to complete.
+ * @result: The result code (0 => Ok, otherwise errno)
+ *
+ * The given request has finished, so call the necessary completion
+ * if it has one and then look to see if we can start a new request
+ * on the endpoint.
+ *
+ * Note, expects the ep to already be locked as appropriate.
+*/
+static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
+                                       struct s3c_hsotg_ep *hs_ep,
+                                       struct s3c_hsotg_req *hs_req,
+                                       int result)
+{
+        bool restart;
+
+        if (!hs_req) {
+                dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
+                return;
+        }
+
+        dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
+                hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
+
+        /* only replace the status if we've not already set an error
+         * from a previous transaction */
+
+        if (hs_req->req.status == -EINPROGRESS)
+                hs_req->req.status = result;
+
+        hs_ep->req = NULL;
+        list_del_init(&hs_req->queue);
+
+        if (using_dma(hsotg))
+                s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
+
+        /* call the complete request with the locks off, just in case the
+         * request tries to queue more work for this endpoint. */
+
+        if (hs_req->req.complete) {
+                spin_unlock(&hs_ep->lock);
+                hs_req->req.complete(&hs_ep->ep, &hs_req->req);
+                spin_lock(&hs_ep->lock);
+        }
+
+        /* Look to see if there is anything else to do. Note, the completion
+         * of the previous request may have caused a new request to be started
+         * so be careful when doing this. */
+
+        if (!hs_ep->req && result >= 0) {
+                restart = !list_empty(&hs_ep->queue);
+                if (restart) {
+                        hs_req = get_ep_head(hs_ep);
+                        s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
+                }
+        }
+}
+
+/**
+ * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint the request was on.
+ * @hs_req: The request to complete.
+ * @result: The result code (0 => Ok, otherwise errno)
+ *
+ * See s3c_hsotg_complete_request(), but called with the endpoint's
+ * lock held.
+*/
+static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
+                                            struct s3c_hsotg_ep *hs_ep,
+                                            struct s3c_hsotg_req *hs_req,
+                                            int result)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&hs_ep->lock, flags);
+        s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
+        spin_unlock_irqrestore(&hs_ep->lock, flags);
+}
+
+/**
+ * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
+ * @hsotg: The device state.
+ * @ep_idx: The endpoint index for the data
+ * @size: The size of data in the fifo, in bytes
+ *
+ * The FIFO status shows there is data to read from the FIFO for a given
+ * endpoint, so sort out whether we need to read the data into a request
+ * that has been made for that endpoint.
+ */
+static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
+{
+        struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
+        struct s3c_hsotg_req *hs_req = hs_ep->req;
+        void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
+        int to_read;
+        int max_req;
+        int read_ptr;
+
+        if (!hs_req) {
+                u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
+                int ptr;
+
+                dev_warn(hsotg->dev,
+                         "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
+                         __func__, size, ep_idx, epctl);
+
+                /* dump the data from the FIFO, we've nothing we can do */
+                for (ptr = 0; ptr < size; ptr += 4)
+                        (void)readl(fifo);
+
+                return;
+        }
+
+        spin_lock(&hs_ep->lock);
+
+        to_read = size;
+        read_ptr = hs_req->req.actual;
+        max_req = hs_req->req.length - read_ptr;
+
+        if (to_read > max_req) {
+                /* more data appeared than we where willing
+                 * to deal with in this request.
+                 */
+
+                /* currently we don't deal this */
+                WARN_ON_ONCE(1);
+        }
+
+        dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
+                __func__, to_read, max_req, read_ptr, hs_req->req.length);
+
+        hs_ep->total_data += to_read;
+        hs_req->req.actual += to_read;
+        to_read = DIV_ROUND_UP(to_read, 4);
+
+        /* note, we might over-write the buffer end by 3 bytes depending on
+         * alignment of the data. */
+        readsl(fifo, hs_req->req.buf + read_ptr, to_read);
+
+        spin_unlock(&hs_ep->lock);
+}
+
+/**
+ * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
+ * @hsotg: The device instance
+ * @req: The request currently on this endpoint
+ *
+ * Generate a zero-length IN packet request for terminating a SETUP
+ * transaction.
+ *
+ * Note, since we don't write any data to the TxFIFO, then it is
+ * currently belived that we do not need to wait for any space in
+ * the TxFIFO.
+ */
+static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
+                               struct s3c_hsotg_req *req)
+{
+        u32 ctrl;
+
+        if (!req) {
+                dev_warn(hsotg->dev, "%s: no request?\n", __func__);
+                return;
+        }
+
+        if (req->req.length == 0) {
+                hsotg->eps[0].sent_zlp = 1;
+                s3c_hsotg_enqueue_setup(hsotg);
+                return;
+        }
+
+        hsotg->eps[0].dir_in = 1;
+        hsotg->eps[0].sent_zlp = 1;
+
+        dev_dbg(hsotg->dev, "sending zero-length packet\n");
+
+        /* issue a zero-sized packet to terminate this */
+        writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
+               S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
+
+        ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
+        ctrl |= S3C_DxEPCTL_CNAK;  /* clear NAK set by core */
+        ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
+        ctrl |= S3C_DxEPCTL_USBActEp;
+        writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
+}
+
+/**
+ * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
+ * @hsotg: The device instance
+ * @epnum: The endpoint received from
+ * @was_setup: Set if processing a SetupDone event.
+ *
+ * The RXFIFO has delivered an OutDone event, which means that the data
+ * transfer for an OUT endpoint has been completed, either by a short
+ * packet or by the finish of a transfer.
+*/
+static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
+                                     int epnum, bool was_setup)
+{
+        struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
+        struct s3c_hsotg_req *hs_req = hs_ep->req;
+        struct usb_request *req = &hs_req->req;
+        int result = 0;
+
+        if (!hs_req) {
+                dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
+                return;
+        }
+
+        if (using_dma(hsotg)) {
+                u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
+                unsigned size_done;
+                unsigned size_left;
+
+                /* Calculate the size of the transfer by checking how much
+                 * is left in the endpoint size register and then working it
+                 * out from the amount we loaded for the transfer.
+                 *
+                 * We need to do this as DMA pointers are always 32bit aligned
+                 * so may overshoot/undershoot the transfer.
+                 */
+
+                size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
+
+                size_done = hs_ep->size_loaded - size_left;
+                size_done += hs_ep->last_load;
+
+                req->actual = size_done;
+        }
+
+        if (req->actual < req->length && req->short_not_ok) {
+                dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
+                        __func__, req->actual, req->length);
+
+                /* todo - what should we return here? there's no one else
+                 * even bothering to check the status. */
+        }
+
+        if (epnum == 0) {
+                if (!was_setup && req->complete != s3c_hsotg_complete_setup)
+                        s3c_hsotg_send_zlp(hsotg, hs_req);
+        }
+
+        s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
+}
+
+/**
+ * s3c_hsotg_read_frameno - read current frame number
+ * @hsotg: The device instance
+ *
+ * Return the current frame number
+*/
+static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
+{
+        u32 dsts;
+
+        dsts = readl(hsotg->regs + S3C_DSTS);
+        dsts &= S3C_DSTS_SOFFN_MASK;
+        dsts >>= S3C_DSTS_SOFFN_SHIFT;
+
+        return dsts;
+}
+
+/**
+ * s3c_hsotg_handle_rx - RX FIFO has data
+ * @hsotg: The device instance
+ *
+ * The IRQ handler has detected that the RX FIFO has some data in it
+ * that requires processing, so find out what is in there and do the
+ * appropriate read.
+ *
+ * The RXFIFO is a true FIFO, the packets comming out are still in packet
+ * chunks, so if you have x packets received on an endpoint you'll get x
+ * FIFO events delivered, each with a packet's worth of data in it.
+ *
+ * When using DMA, we should not be processing events from the RXFIFO
+ * as the actual data should be sent to the memory directly and we turn
+ * on the completion interrupts to get notifications of transfer completion.
+ */
+void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
+{
+        u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
+        u32 epnum, status, size;
+
+        WARN_ON(using_dma(hsotg));
+
+        epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
+        status = grxstsr & S3C_GRXSTS_PktSts_MASK;
+
+        size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
+        size >>= S3C_GRXSTS_ByteCnt_SHIFT;
+
+        if (1)
+                dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
+                        __func__, grxstsr, size, epnum);
+
+#define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
+
+        switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
+        case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
+                dev_dbg(hsotg->dev, "GlobalOutNAK\n");
+                break;
+
+        case __status(S3C_GRXSTS_PktSts_OutDone):
+                dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
+                        s3c_hsotg_read_frameno(hsotg));
+
+                if (!using_dma(hsotg))
+                        s3c_hsotg_handle_outdone(hsotg, epnum, false);
+                break;
+
+        case __status(S3C_GRXSTS_PktSts_SetupDone):
+                dev_dbg(hsotg->dev,
+                        "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
+                        s3c_hsotg_read_frameno(hsotg),
+                        readl(hsotg->regs + S3C_DOEPCTL(0)));
+
+                s3c_hsotg_handle_outdone(hsotg, epnum, true);
+                break;
+
+        case __status(S3C_GRXSTS_PktSts_OutRX):
+                s3c_hsotg_rx_data(hsotg, epnum, size);
+                break;
+
+        case __status(S3C_GRXSTS_PktSts_SetupRX):
+                dev_dbg(hsotg->dev,
+                        "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
+                        s3c_hsotg_read_frameno(hsotg),
+                        readl(hsotg->regs + S3C_DOEPCTL(0)));
+
+                s3c_hsotg_rx_data(hsotg, epnum, size);
+                break;
+
+        default:
+                dev_warn(hsotg->dev, "%s: unknown status %08x\n",
+                         __func__, grxstsr);
+
+                s3c_hsotg_dump(hsotg);
+                break;
+        }
+}
+
+/**
+ * s3c_hsotg_ep0_mps - turn max packet size into register setting
+ * @mps: The maximum packet size in bytes.
+*/
+static u32 s3c_hsotg_ep0_mps(unsigned int mps)
+{
+        switch (mps) {
+        case 64:
+                return S3C_D0EPCTL_MPS_64;
+        case 32:
+                return S3C_D0EPCTL_MPS_32;
+        case 16:
+                return S3C_D0EPCTL_MPS_16;
+        case 8:
+                return S3C_D0EPCTL_MPS_8;
+        }
+
+        /* bad max packet size, warn and return invalid result */
+        WARN_ON(1);
+        return (u32)-1;
+}
+
+/**
+ * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
+ * @hsotg: The driver state.
+ * @ep: The index number of the endpoint
+ * @mps: The maximum packet size in bytes
+ *
+ * Configure the maximum packet size for the given endpoint, updating
+ * the hardware control registers to reflect this.
+ */
+static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
+                                       unsigned int ep, unsigned int mps)
+{
+        struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
+        void __iomem *regs = hsotg->regs;
+        u32 mpsval;
+        u32 reg;
+
+        if (ep == 0) {
+                /* EP0 is a special case */
+                mpsval = s3c_hsotg_ep0_mps(mps);
+                if (mpsval > 3)
+                        goto bad_mps;
+        } else {
+                if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
+                        goto bad_mps;
+
+                mpsval = mps;
+        }
+
+        hs_ep->ep.maxpacket = mps;
+
+        /* update both the in and out endpoint controldir_ registers, even
+         * if one of the directions may not be in use. */
+
+        reg = readl(regs + S3C_DIEPCTL(ep));
+        reg &= ~S3C_DxEPCTL_MPS_MASK;
+        reg |= mpsval;
+        writel(reg, regs + S3C_DIEPCTL(ep));
+
+        reg = readl(regs + S3C_DOEPCTL(ep));
+        reg &= ~S3C_DxEPCTL_MPS_MASK;
+        reg |= mpsval;
+        writel(reg, regs + S3C_DOEPCTL(ep));
+
+        return;
+
+bad_mps:
+        dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
+}
+
+
+/**
+ * s3c_hsotg_trytx - check to see if anything needs transmitting
+ * @hsotg: The driver state
+ * @hs_ep: The driver endpoint to check.
+ *
+ * Check to see if there is a request that has data to send, and if so
+ * make an attempt to write data into the FIFO.
+ */
+static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
+                           struct s3c_hsotg_ep *hs_ep)
+{
+        struct s3c_hsotg_req *hs_req = hs_ep->req;
+
+        if (!hs_ep->dir_in || !hs_req)
+                return 0;
+
+        if (hs_req->req.actual < hs_req->req.length) {
+                dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
+                        hs_ep->index);
+                return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
+        }
+
+        return 0;
+}
+
+/**
+ * s3c_hsotg_complete_in - complete IN transfer
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint that has just completed.
+ *
+ * An IN transfer has been completed, update the transfer's state and then
+ * call the relevant completion routines.
+ */
+static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
+                                  struct s3c_hsotg_ep *hs_ep)
+{
+        struct s3c_hsotg_req *hs_req = hs_ep->req;
+        u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
+        int size_left, size_done;
+
+        if (!hs_req) {
+                dev_dbg(hsotg->dev, "XferCompl but no req\n");
+                return;
+        }
+
+        /* Calculate the size of the transfer by checking how much is left
+         * in the endpoint size register and then working it out from
+         * the amount we loaded for the transfer.
+         *
+         * We do this even for DMA, as the transfer may have incremented
+         * past the end of the buffer (DMA transfers are always 32bit
+         * aligned).
+         */
+
+        size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
+
+        size_done = hs_ep->size_loaded - size_left;
+        size_done += hs_ep->last_load;
+
+        if (hs_req->req.actual != size_done)
+                dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
+                        __func__, hs_req->req.actual, size_done);
+
+        hs_req->req.actual = size_done;
+
+        /* if we did all of the transfer, and there is more data left
+         * around, then try restarting the rest of the request */
+
+        if (!size_left && hs_req->req.actual < hs_req->req.length) {
+                dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
+                s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
+        } else
+                s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
+}
+
+/**
+ * s3c_hsotg_epint - handle an in/out endpoint interrupt
+ * @hsotg: The driver state
+ * @idx: The index for the endpoint (0..15)
+ * @dir_in: Set if this is an IN endpoint
+ *
+ * Process and clear any interrupt pending for an individual endpoint
+*/
+static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
+                            int dir_in)
+{
+        struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
+        u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
+        u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
+        u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
+        u32 ints;
+        u32 clear = 0;
+
+        ints = readl(hsotg->regs + epint_reg);
+
+        dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
+                __func__, idx, dir_in ? "in" : "out", ints);
+
+        if (ints & S3C_DxEPINT_XferCompl) {
+                dev_dbg(hsotg->dev,
+                        "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
+                        __func__, readl(hsotg->regs + epctl_reg),
+                        readl(hsotg->regs + epsiz_reg));
+
+                /* we get OutDone from the FIFO, so we only need to look
+                 * at completing IN requests here */
+                if (dir_in) {
+                        s3c_hsotg_complete_in(hsotg, hs_ep);
+
+                        if (idx == 0)
+                                s3c_hsotg_enqueue_setup(hsotg);
+                } else if (using_dma(hsotg)) {
+                        /* We're using DMA, we need to fire an OutDone here
+                         * as we ignore the RXFIFO. */
+
+                        s3c_hsotg_handle_outdone(hsotg, idx, false);
+                }
+
+                clear |= S3C_DxEPINT_XferCompl;
+        }
+
+        if (ints & S3C_DxEPINT_EPDisbld) {
+                dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
+                clear |= S3C_DxEPINT_EPDisbld;
+        }
+
+        if (ints & S3C_DxEPINT_AHBErr) {
+                dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
+                clear |= S3C_DxEPINT_AHBErr;
+        }
+
+        if (ints & S3C_DxEPINT_Setup) {  /* Setup or Timeout */
+                dev_dbg(hsotg->dev, "%s: Setup/Timeout\n",  __func__);
+
+                if (using_dma(hsotg) && idx == 0) {
+                        /* this is the notification we've received a
+                         * setup packet. In non-DMA mode we'd get this
+                         * from the RXFIFO, instead we need to process
+                         * the setup here. */
+
+                        if (dir_in)
+                                WARN_ON_ONCE(1);
+                        else
+                                s3c_hsotg_handle_outdone(hsotg, 0, true);
+                }
+
+                clear |= S3C_DxEPINT_Setup;
+        }
+
+        if (ints & S3C_DxEPINT_Back2BackSetup) {
+                dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
+                clear |= S3C_DxEPINT_Back2BackSetup;
+        }
+
+        if (dir_in) {
+                /* not sure if this is important, but we'll clear it anyway
+                 */
+                if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
+                        dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
+                                __func__, idx);
+                        clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
+                }
+
+                /* this probably means something bad is happening */
+                if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
+                        dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
+                                 __func__, idx);
+                        clear |= S3C_DIEPMSK_INTknEPMisMsk;
+                }
+        }
+
+        writel(clear, hsotg->regs + epint_reg);
+}
+
+/**
+ * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
+ * @hsotg: The device state.
+ *
+ * Handle updating the device settings after the enumeration phase has
+ * been completed.
+*/
+static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
+{
+        u32 dsts = readl(hsotg->regs + S3C_DSTS);
+        int ep0_mps = 0, ep_mps;
+
+        /* This should signal the finish of the enumeration phase
+         * of the USB handshaking, so we should now know what rate
+         * we connected at. */
+
+        dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
+
+        /* note, since we're limited by the size of transfer on EP0, and
+         * it seems IN transfers must be a even number of packets we do
+         * not advertise a 64byte MPS on EP0. */
+
+        /* catch both EnumSpd_FS and EnumSpd_FS48 */
+        switch (dsts & S3C_DSTS_EnumSpd_MASK) {
+        case S3C_DSTS_EnumSpd_FS:
+        case S3C_DSTS_EnumSpd_FS48:
+                hsotg->gadget.speed = USB_SPEED_FULL;
+                dev_info(hsotg->dev, "new device is full-speed\n");
+
+                ep0_mps = EP0_MPS_LIMIT;
+                ep_mps = 64;
+                break;
+
+        case S3C_DSTS_EnumSpd_HS:
+                dev_info(hsotg->dev, "new device is high-speed\n");
+                hsotg->gadget.speed = USB_SPEED_HIGH;
+
+                ep0_mps = EP0_MPS_LIMIT;
+                ep_mps = 512;
+                break;
+
+        case S3C_DSTS_EnumSpd_LS:
+                hsotg->gadget.speed = USB_SPEED_LOW;
+                dev_info(hsotg->dev, "new device is low-speed\n");
+
+                /* note, we don't actually support LS in this driver at the
+                 * moment, and the documentation seems to imply that it isn't
+                 * supported by the PHYs on some of the devices.
+                 */
+                break;
+        }
+
+        /* we should now know the maximum packet size for an
+         * endpoint, so set the endpoints to a default value. */
+
+        if (ep0_mps) {
+                int i;
+                s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
+                for (i = 1; i < S3C_HSOTG_EPS; i++)
+                        s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
+        }
+
+        /* ensure after enumeration our EP0 is active */
+
+        s3c_hsotg_enqueue_setup(hsotg);
+
+        dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
+                readl(hsotg->regs + S3C_DIEPCTL0),
+                readl(hsotg->regs + S3C_DOEPCTL0));
+}
+
+/**
+ * kill_all_requests - remove all requests from the endpoint's queue
+ * @hsotg: The device state.
+ * @ep: The endpoint the requests may be on.
+ * @result: The result code to use.
+ * @force: Force removal of any current requests
+ *
+ * Go through the requests on the given endpoint and mark them
+ * completed with the given result code.
+ */
+static void kill_all_requests(struct s3c_hsotg *hsotg,
+                              struct s3c_hsotg_ep *ep,
+                              int result, bool force)
+{
+        struct s3c_hsotg_req *req, *treq;
+        unsigned long flags;
+
+        spin_lock_irqsave(&ep->lock, flags);
+
+        list_for_each_entry_safe(req, treq, &ep->queue, queue) {
+                /* currently, we can't do much about an already
+                 * running request on an in endpoint */
+
+                if (ep->req == req && ep->dir_in && !force)
+                        continue;
+
+                s3c_hsotg_complete_request(hsotg, ep, req,
+                                           result);
+        }
+
+        spin_unlock_irqrestore(&ep->lock, flags);
+}
+
+#define call_gadget(_hs, _entry) \
+        if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
+            (_hs)->driver && (_hs)->driver->_entry)     \
+                (_hs)->driver->_entry(&(_hs)->gadget);
+
+/**
+ * s3c_hsotg_disconnect_irq - disconnect irq service
+ * @hsotg: The device state.
+ *
+ * A disconnect IRQ has been received, meaning that the host has
+ * lost contact with the bus. Remove all current transactions
+ * and signal the gadget driver that this has happened.
+*/
+static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
+{
+        unsigned ep;
+
+        for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
+                kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
+
+        call_gadget(hsotg, disconnect);
+}
+
+/**
+ * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
+ * @hsotg: The device state:
+ * @periodic: True if this is a periodic FIFO interrupt
+ */
+static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
+{
+        struct s3c_hsotg_ep *ep;
+        int epno, ret;
+
+        /* look through for any more data to transmit */
+
+        for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
+                ep = &hsotg->eps[epno];
+
+                if (!ep->dir_in)
+                        continue;
+
+                if ((periodic && !ep->periodic) ||
+                    (!periodic && ep->periodic))
+                        continue;
+
+                ret = s3c_hsotg_trytx(hsotg, ep);
+                if (ret < 0)
+                        break;
+        }
+}
+
+static struct s3c_hsotg *our_hsotg;
+
+/* IRQ flags which will trigger a retry around the IRQ loop */
+#define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
+                        S3C_GINTSTS_PTxFEmp |  \
+                        S3C_GINTSTS_RxFLvl)
+
+/**
+ * s3c_hsotg_irq - handle device interrupt
+ * @irq: The IRQ number triggered
+ * @pw: The pw value when registered the handler.
+ */
+static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
+{
+        struct s3c_hsotg *hsotg = pw;
+        int retry_count = 8;
+        u32 gintsts;
+        u32 gintmsk;
+
+irq_retry:
+        gintsts = readl(hsotg->regs + S3C_GINTSTS);
+        gintmsk = readl(hsotg->regs + S3C_GINTMSK);
+
+        dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
+                __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
+
+        gintsts &= gintmsk;
+
+        if (gintsts & S3C_GINTSTS_OTGInt) {
+                u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
+
+                dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
+
+                writel(otgint, hsotg->regs + S3C_GOTGINT);
+                writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
+        }
+
+        if (gintsts & S3C_GINTSTS_DisconnInt) {
+                dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
+                writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
+
+                s3c_hsotg_disconnect_irq(hsotg);
+        }
+
+        if (gintsts & S3C_GINTSTS_SessReqInt) {
+                dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
+                writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
+        }
+
+        if (gintsts & S3C_GINTSTS_EnumDone) {
+                s3c_hsotg_irq_enumdone(hsotg);
+                writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
+        }
+
+        if (gintsts & S3C_GINTSTS_ConIDStsChng) {
+                dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
+                        readl(hsotg->regs + S3C_DSTS),
+                        readl(hsotg->regs + S3C_GOTGCTL));
+
+                writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
+        }
+
+        if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
+                u32 daint = readl(hsotg->regs + S3C_DAINT);
+                u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
+                u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
+                int ep;
+
+                dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
+
+                for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
+                        if (daint_out & 1)
+                                s3c_hsotg_epint(hsotg, ep, 0);
+                }
+
+                for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
+                        if (daint_in & 1)
+                                s3c_hsotg_epint(hsotg, ep, 1);
+                }
+
+                writel(daint, hsotg->regs + S3C_DAINT);
+                writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
+                       hsotg->regs + S3C_GINTSTS);
+        }
+
+        if (gintsts & S3C_GINTSTS_USBRst) {
+                dev_info(hsotg->dev, "%s: USBRst\n", __func__);
+                dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
+                        readl(hsotg->regs + S3C_GNPTXSTS));
+
+                kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
+
+                /* it seems after a reset we can end up with a situation
+                 * where the TXFIFO still has data in it... try flushing
+                 * it to remove anything that may still be in it.
+                 */
+
+                if (1) {
+                        writel(S3C_GRSTCTL_TxFNum(0) | S3C_GRSTCTL_TxFFlsh,
+                               hsotg->regs + S3C_GRSTCTL);
+
+                        dev_info(hsotg->dev, "GNPTXSTS=%08x\n",
+                                 readl(hsotg->regs + S3C_GNPTXSTS));
+                }
+
+                s3c_hsotg_enqueue_setup(hsotg);
+
+                writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
+        }
+
+        /* check both FIFOs */
+
+        if (gintsts & S3C_GINTSTS_NPTxFEmp) {
+                dev_dbg(hsotg->dev, "NPTxFEmp\n");
+
+                /* Disable the interrupt to stop it happening again
+                 * unless one of these endpoint routines decides that
+                 * it needs re-enabling */
+
+                s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
+                s3c_hsotg_irq_fifoempty(hsotg, false);
+
+                writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
+        }
+
+        if (gintsts & S3C_GINTSTS_PTxFEmp) {
+                dev_dbg(hsotg->dev, "PTxFEmp\n");
+
+                /* See note in S3C_GINTSTS_NPTxFEmp */
+
+                s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
+                s3c_hsotg_irq_fifoempty(hsotg, true);
+
+                writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
+        }
+
+        if (gintsts & S3C_GINTSTS_RxFLvl) {
+                /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
+                 * we need to retry s3c_hsotg_handle_rx if this is still
+                 * set. */
+
+                s3c_hsotg_handle_rx(hsotg);
+                writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
+        }
+
+        if (gintsts & S3C_GINTSTS_ModeMis) {
+                dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
+                writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
+        }
+
+        if (gintsts & S3C_GINTSTS_USBSusp) {
+                dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
+                writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
+
+                call_gadget(hsotg, suspend);
+        }
+
+        if (gintsts & S3C_GINTSTS_WkUpInt) {
+                dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
+                writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
+
+                call_gadget(hsotg, resume);
+        }
+
+        if (gintsts & S3C_GINTSTS_ErlySusp) {
+                dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
+                writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
+        }
+
+        /* these next two seem to crop-up occasionally causing the core
+         * to shutdown the USB transfer, so try clearing them and logging
+         * the occurence. */
+
+        if (gintsts & S3C_GINTSTS_GOUTNakEff) {
+                dev_info(hsotg->dev, "GOUTNakEff triggered\n");
+
+                s3c_hsotg_dump(hsotg);
+
+                writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
+                writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
+        }
+
+        if (gintsts & S3C_GINTSTS_GINNakEff) {
+                dev_info(hsotg->dev, "GINNakEff triggered\n");
+
+                s3c_hsotg_dump(hsotg);
+
+                writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
+                writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
+        }
+
+        /* if we've had fifo events, we should try and go around the
+         * loop again to see if there's any point in returning yet. */
+
+        if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
+                        goto irq_retry;
+
+        return IRQ_HANDLED;
+}
+
+/**
+ * s3c_hsotg_ep_enable - enable the given endpoint
+ * @ep: The USB endpint to configure
+ * @desc: The USB endpoint descriptor to configure with.
+ *
+ * This is called from the USB gadget code's usb_ep_enable().
+*/
+static int s3c_hsotg_ep_enable(struct usb_ep *ep,
+                               const struct usb_endpoint_descriptor *desc)
+{
+        struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+        struct s3c_hsotg *hsotg = hs_ep->parent;
+        unsigned long flags;
+        int index = hs_ep->index;
+        u32 epctrl_reg;
+        u32 epctrl;
+        u32 mps;
+        int dir_in;
+
+        dev_dbg(hsotg->dev,
+                "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
+                __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
+                desc->wMaxPacketSize, desc->bInterval);
+
+        /* not to be called for EP0 */
+        WARN_ON(index == 0);
+
+        dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
+        if (dir_in != hs_ep->dir_in) {
+                dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
+                return -EINVAL;
+        }
+
+        mps = le16_to_cpu(desc->wMaxPacketSize);
+
+        /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
+
+        epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
+        epctrl = readl(hsotg->regs + epctrl_reg);
+
+        dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
+                __func__, epctrl, epctrl_reg);
+
+        spin_lock_irqsave(&hs_ep->lock, flags);
+
+        epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
+        epctrl |= S3C_DxEPCTL_MPS(mps);
+
+        /* mark the endpoint as active, otherwise the core may ignore
+         * transactions entirely for this endpoint */
+        epctrl |= S3C_DxEPCTL_USBActEp;
+
+        /* set the NAK status on the endpoint, otherwise we might try and
+         * do something with data that we've yet got a request to process
+         * since the RXFIFO will take data for an endpoint even if the
+         * size register hasn't been set.
+         */
+
+        epctrl |= S3C_DxEPCTL_SNAK;
+
+        /* update the endpoint state */
+        hs_ep->ep.maxpacket = mps;
+
+        /* default, set to non-periodic */
+        hs_ep->periodic = 0;
+
+        switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
+        case USB_ENDPOINT_XFER_ISOC:
+                dev_err(hsotg->dev, "no current ISOC support\n");
+                return -EINVAL;
+
+        case USB_ENDPOINT_XFER_BULK:
+                epctrl |= S3C_DxEPCTL_EPType_Bulk;
+                break;
+
+        case USB_ENDPOINT_XFER_INT:
+                if (dir_in) {
+                        /* Allocate our TxFNum by simply using the index
+                         * of the endpoint for the moment. We could do
+                         * something better if the host indicates how
+                         * many FIFOs we are expecting to use. */
+
+                        hs_ep->periodic = 1;
+                        epctrl |= S3C_DxEPCTL_TxFNum(index);
+                }
+
+                epctrl |= S3C_DxEPCTL_EPType_Intterupt;
+                break;
+
+        case USB_ENDPOINT_XFER_CONTROL:
+                epctrl |= S3C_DxEPCTL_EPType_Control;
+                break;
+        }
+
+        /* for non control endpoints, set PID to D0 */
+        if (index)
+                epctrl |= S3C_DxEPCTL_SetD0PID;
+
+        dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
+                __func__, epctrl);
+
+        writel(epctrl, hsotg->regs + epctrl_reg);
+        dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
+                __func__, readl(hsotg->regs + epctrl_reg));
+
+        /* enable the endpoint interrupt */
+        s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
+
+        spin_unlock_irqrestore(&hs_ep->lock, flags);
+        return 0;
+}
+
+static int s3c_hsotg_ep_disable(struct usb_ep *ep)
+{
+        struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+        struct s3c_hsotg *hsotg = hs_ep->parent;
+        int dir_in = hs_ep->dir_in;
+        int index = hs_ep->index;
+        unsigned long flags;
+        u32 epctrl_reg;
+        u32 ctrl;
+
+        dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
+
+        if (ep == &hsotg->eps[0].ep) {
+                dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
+                return -EINVAL;
+        }
+
+        epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
+
+        /* terminate all requests with shutdown */
+        kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
+
+        spin_lock_irqsave(&hs_ep->lock, flags);
+
+        ctrl = readl(hsotg->regs + epctrl_reg);
+        ctrl &= ~S3C_DxEPCTL_EPEna;
+        ctrl &= ~S3C_DxEPCTL_USBActEp;
+        ctrl |= S3C_DxEPCTL_SNAK;
+
+        dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
+        writel(ctrl, hsotg->regs + epctrl_reg);
+
+        /* disable endpoint interrupts */
+        s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
+
+        spin_unlock_irqrestore(&hs_ep->lock, flags);
+        return 0;
+}
+
+/**
+ * on_list - check request is on the given endpoint
+ * @ep: The endpoint to check.
+ * @test: The request to test if it is on the endpoint.
+*/
+static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
+{
+        struct s3c_hsotg_req *req, *treq;
+
+        list_for_each_entry_safe(req, treq, &ep->queue, queue) {
+                if (req == test)
+                        return true;
+        }
+
+        return false;
+}
+
+static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
+{
+        struct s3c_hsotg_req *hs_req = our_req(req);
+        struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+        struct s3c_hsotg *hs = hs_ep->parent;
+        unsigned long flags;
+
+        dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
+
+        if (hs_req == hs_ep->req) {
+                dev_dbg(hs->dev, "%s: already in progress\n", __func__);
+                return -EINPROGRESS;
+        }
+
+        spin_lock_irqsave(&hs_ep->lock, flags);
+
+        if (!on_list(hs_ep, hs_req)) {
+                spin_unlock_irqrestore(&hs_ep->lock, flags);
+                return -EINVAL;
+        }
+
+        s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
+        spin_unlock_irqrestore(&hs_ep->lock, flags);
+
+        return 0;
+}
+
+static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
+{
+        struct s3c_hsotg_ep *hs_ep = our_ep(ep);
+        struct s3c_hsotg *hs = hs_ep->parent;
+        int index = hs_ep->index;
+        unsigned long irqflags;
+        u32 epreg;
+        u32 epctl;
+
+        dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
+
+        spin_lock_irqsave(&hs_ep->lock, irqflags);
+
+        /* write both IN and OUT control registers */
+
+        epreg = S3C_DIEPCTL(index);
+        epctl = readl(hs->regs + epreg);
+
+        if (value)
+                epctl |= S3C_DxEPCTL_Stall;
+        else
+                epctl &= ~S3C_DxEPCTL_Stall;
+
+        writel(epctl, hs->regs + epreg);
+
+        epreg = S3C_DOEPCTL(index);
+        epctl = readl(hs->regs + epreg);
+
+        if (value)
+                epctl |= S3C_DxEPCTL_Stall;
+        else
+                epctl &= ~S3C_DxEPCTL_Stall;
+
+        writel(epctl, hs->regs + epreg);
+
+        spin_unlock_irqrestore(&hs_ep->lock, irqflags);
+
+        return 0;
+}
+
+static struct usb_ep_ops s3c_hsotg_ep_ops = {
+        .enable         = s3c_hsotg_ep_enable,
+        .disable        = s3c_hsotg_ep_disable,
+        .alloc_request  = s3c_hsotg_ep_alloc_request,
+        .free_request   = s3c_hsotg_ep_free_request,
+        .queue          = s3c_hsotg_ep_queue,
+        .dequeue        = s3c_hsotg_ep_dequeue,
+        .set_halt       = s3c_hsotg_ep_sethalt,
+        /* note, don't belive we have any call for the fifo routines */
+};
+
+/**
+ * s3c_hsotg_corereset - issue softreset to the core
+ * @hsotg: The device state
+ *
+ * Issue a soft reset to the core, and await the core finishing it.
+*/
+static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
+{
+        int timeout;
+        u32 grstctl;
+
+        dev_dbg(hsotg->dev, "resetting core\n");
+
+        /* issue soft reset */
+        writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
+
+        timeout = 1000;
+        do {
+                grstctl = readl(hsotg->regs + S3C_GRSTCTL);
+        } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
+
+        if (!grstctl & S3C_GRSTCTL_CSftRst) {
+                dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
+                return -EINVAL;
+        }
+
+        timeout = 1000;
+
+        while (1) {
+                u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
+
+                if (timeout-- < 0) {
+                        dev_info(hsotg->dev,
+                                 "%s: reset failed, GRSTCTL=%08x\n",
+                                 __func__, grstctl);
+                        return -ETIMEDOUT;
+                }
+
+                if (grstctl & S3C_GRSTCTL_CSftRst)
+                        continue;
+
+                if (!(grstctl & S3C_GRSTCTL_AHBIdle))
+                        continue;
+
+                break;          /* reset done */
+        }
+
+        dev_dbg(hsotg->dev, "reset successful\n");
+        return 0;
+}
+
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+        struct s3c_hsotg *hsotg = our_hsotg;
+        int ret;
+
+        if (!hsotg) {
+                printk(KERN_ERR "%s: called with no device\n", __func__);
+                return -ENODEV;
+        }
+
+        if (!driver) {
+                dev_err(hsotg->dev, "%s: no driver\n", __func__);
+                return -EINVAL;
+        }
+
+        if (driver->speed != USB_SPEED_HIGH &&
+            driver->speed != USB_SPEED_FULL) {
+                dev_err(hsotg->dev, "%s: bad speed\n", __func__);
+        }
+
+        if (!driver->bind || !driver->setup) {
+                dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
+                return -EINVAL;
+        }
+
+        WARN_ON(hsotg->driver);
+
+        driver->driver.bus = NULL;
+        hsotg->driver = driver;
+        hsotg->gadget.dev.driver = &driver->driver;
+        hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
+        hsotg->gadget.speed = USB_SPEED_UNKNOWN;
+
+        ret = device_add(&hsotg->gadget.dev);
+        if (ret) {
+                dev_err(hsotg->dev, "failed to register gadget device\n");
+                goto err;
+        }
+
+        ret = driver->bind(&hsotg->gadget);
+        if (ret) {
+                dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
+
+                hsotg->gadget.dev.driver = NULL;
+                hsotg->driver = NULL;
+                goto err;
+        }
+
+        /* we must now enable ep0 ready for host detection and then
+         * set configuration. */
+
+        s3c_hsotg_corereset(hsotg);
+
+        /* set the PLL on, remove the HNP/SRP and set the PHY */
+        writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
+               (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
+
+        /* looks like soft-reset changes state of FIFOs */
+        s3c_hsotg_init_fifo(hsotg);
+
+        __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
+
+        writel(1 << 18 | S3C_DCFG_DevSpd_HS,  hsotg->regs + S3C_DCFG);
+
+        writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
+               S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
+               S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
+               S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
+               S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
+               S3C_GINTSTS_ErlySusp,
+               hsotg->regs + S3C_GINTMSK);
+
+        if (using_dma(hsotg))
+                writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
+                       S3C_GAHBCFG_HBstLen_Incr4,
+                       hsotg->regs + S3C_GAHBCFG);
+        else
+                writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
+
+        /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
+         * up being flooded with interrupts if the host is polling the
+         * endpoint to try and read data. */
+
+        writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
+               S3C_DIEPMSK_INTknEPMisMsk |
+               S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
+               hsotg->regs + S3C_DIEPMSK);
+
+        /* don't need XferCompl, we get that from RXFIFO in slave mode. In
+         * DMA mode we may need this. */
+        writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
+               S3C_DOEPMSK_EPDisbldMsk |
+               using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
+                                   S3C_DIEPMSK_TimeOUTMsk) : 0,
+               hsotg->regs + S3C_DOEPMSK);
+
+        writel(0, hsotg->regs + S3C_DAINTMSK);
+
+        dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
+                 readl(hsotg->regs + S3C_DIEPCTL0),
+                 readl(hsotg->regs + S3C_DOEPCTL0));
+
+        /* enable in and out endpoint interrupts */
+        s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
+
+        /* Enable the RXFIFO when in slave mode, as this is how we collect
+         * the data. In DMA mode, we get events from the FIFO but also
+         * things we cannot process, so do not use it. */
+        if (!using_dma(hsotg))
+                s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
+
+        /* Enable interrupts for EP0 in and out */
+        s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
+        s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
+
+        __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
+        udelay(10);  /* see openiboot */
+        __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
+
+        dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
+
+        /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
+           writing to the EPCTL register.. */
+
+        /* set to read 1 8byte packet */
+        writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
+               S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
+
+        writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
+               S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
+               S3C_DxEPCTL_USBActEp,
+               hsotg->regs + S3C_DOEPCTL0);
+
+        /* enable, but don't activate EP0in */
+        writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
+               S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
+
+        s3c_hsotg_enqueue_setup(hsotg);
+
+        dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
+                 readl(hsotg->regs + S3C_DIEPCTL0),
+                 readl(hsotg->regs + S3C_DOEPCTL0));
+
+        /* clear global NAKs */
+        writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
+               hsotg->regs + S3C_DCTL);
+
+        /* remove the soft-disconnect and let's go */
+        __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
+
+        /* report to the user, and return */
+
+        dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
+        return 0;
+
+err:
+        hsotg->driver = NULL;
+        hsotg->gadget.dev.driver = NULL;
+        return ret;
+}
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+        struct s3c_hsotg *hsotg = our_hsotg;
+        int ep;
+
+        if (!hsotg)
+                return -ENODEV;
+
+        if (!driver || driver != hsotg->driver || !driver->unbind)
+                return -EINVAL;
+
+        /* all endpoints should be shutdown */
+        for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
+                s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
+
+        call_gadget(hsotg, disconnect);
+
+        driver->unbind(&hsotg->gadget);
+        hsotg->driver = NULL;
+        hsotg->gadget.speed = USB_SPEED_UNKNOWN;
+
+        device_del(&hsotg->gadget.dev);
+
+        dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
+                 driver->driver.name);
+
+        return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
+{
+        return s3c_hsotg_read_frameno(to_hsotg(gadget));
+}
+
+static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
+        .get_frame      = s3c_hsotg_gadget_getframe,
+};
+
+/**
+ * s3c_hsotg_initep - initialise a single endpoint
+ * @hsotg: The device state.
+ * @hs_ep: The endpoint to be initialised.
+ * @epnum: The endpoint number
+ *
+ * Initialise the given endpoint (as part of the probe and device state
+ * creation) to give to the gadget driver. Setup the endpoint name, any
+ * direction information and other state that may be required.
+ */
+static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
+                                       struct s3c_hsotg_ep *hs_ep,
+                                       int epnum)
+{
+        u32 ptxfifo;
+        char *dir;
+
+        if (epnum == 0)
+                dir = "";
+        else if ((epnum % 2) == 0) {
+                dir = "out";
+        } else {
+                dir = "in";
+                hs_ep->dir_in = 1;
+        }
+
+        hs_ep->index = epnum;
+
+        snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
+
+        INIT_LIST_HEAD(&hs_ep->queue);
+        INIT_LIST_HEAD(&hs_ep->ep.ep_list);
+
+        spin_lock_init(&hs_ep->lock);
+
+        /* add to the list of endpoints known by the gadget driver */
+        if (epnum)
+                list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
+
+        hs_ep->parent = hsotg;
+        hs_ep->ep.name = hs_ep->name;
+        hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
+        hs_ep->ep.ops = &s3c_hsotg_ep_ops;
+
+        /* Read the FIFO size for the Periodic TX FIFO, even if we're
+         * an OUT endpoint, we may as well do this if in future the
+         * code is changed to make each endpoint's direction changeable.
+         */
+
+        ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
+        hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo);
+
+        /* if we're using dma, we need to set the next-endpoint pointer
+         * to be something valid.
+         */
+
+        if (using_dma(hsotg)) {
+                u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
+                writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
+                writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
+        }
+}
+
+/**
+ * s3c_hsotg_otgreset - reset the OtG phy block
+ * @hsotg: The host state.
+ *
+ * Power up the phy, set the basic configuration and start the PHY.
+ */
+static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
+{
+        u32 osc;
+
+        writel(0, S3C_PHYPWR);
+        mdelay(1);
+
+        osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
+
+        writel(osc | 0x10, S3C_PHYCLK);
+
+        /* issue a full set of resets to the otg and core */
+
+        writel(S3C_RSTCON_PHY, S3C_RSTCON);
+        udelay(20);     /* at-least 10uS */
+        writel(0, S3C_RSTCON);
+}
+
+
+static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
+{
+        /* unmask subset of endpoint interrupts */
+
+        writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
+               S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
+               hsotg->regs + S3C_DIEPMSK);
+
+        writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
+               S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
+               hsotg->regs + S3C_DOEPMSK);
+
+        writel(0, hsotg->regs + S3C_DAINTMSK);
+
+        if (0) {
+                /* post global nak until we're ready */
+                writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
+                       hsotg->regs + S3C_DCTL);
+        }
+
+        /* setup fifos */
+
+        dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
+                 readl(hsotg->regs + S3C_GRXFSIZ),
+                 readl(hsotg->regs + S3C_GNPTXFSIZ));
+
+        s3c_hsotg_init_fifo(hsotg);
+
+        /* set the PLL on, remove the HNP/SRP and set the PHY */
+        writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
+               hsotg->regs + S3C_GUSBCFG);
+
+        writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
+               hsotg->regs + S3C_GAHBCFG);
+}
+
+static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
+{
+        struct device *dev = hsotg->dev;
+        void __iomem *regs = hsotg->regs;
+        u32 val;
+        int idx;
+
+        dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
+                 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
+                 readl(regs + S3C_DIEPMSK));
+
+        dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
+                 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
+
+        dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
+                 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
+
+        /* show periodic fifo settings */
+
+        for (idx = 1; idx <= 15; idx++) {
+                val = readl(regs + S3C_DPTXFSIZn(idx));
+                dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
+                         val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
+                         val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
+        }
+
+        for (idx = 0; idx < 15; idx++) {
+                dev_info(dev,
+                         "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
+                         readl(regs + S3C_DIEPCTL(idx)),
+                         readl(regs + S3C_DIEPTSIZ(idx)),
+                         readl(regs + S3C_DIEPDMA(idx)));
+
+                val = readl(regs + S3C_DOEPCTL(idx));
+                dev_info(dev,
+                         "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
+                         idx, readl(regs + S3C_DOEPCTL(idx)),
+                         readl(regs + S3C_DOEPTSIZ(idx)),
+                         readl(regs + S3C_DOEPDMA(idx)));
+
+        }
+
+        dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
+                 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
+}
+
+
+/**
+ * state_show - debugfs: show overall driver and device state.
+ * @seq: The seq file to write to.
+ * @v: Unused parameter.
+ *
+ * This debugfs entry shows the overall state of the hardware and
+ * some general information about each of the endpoints available
+ * to the system.
+ */
+static int state_show(struct seq_file *seq, void *v)
+{
+        struct s3c_hsotg *hsotg = seq->private;
+        void __iomem *regs = hsotg->regs;
+        int idx;
+
+        seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
+                 readl(regs + S3C_DCFG),
+                 readl(regs + S3C_DCTL),
+                 readl(regs + S3C_DSTS));
+
+        seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
+                   readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
+
+        seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
+                   readl(regs + S3C_GINTMSK),
+                   readl(regs + S3C_GINTSTS));
+
+        seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
+                   readl(regs + S3C_DAINTMSK),
+                   readl(regs + S3C_DAINT));
+
+        seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
+                   readl(regs + S3C_GNPTXSTS),
+                   readl(regs + S3C_GRXSTSR));
+
+        seq_printf(seq, "\nEndpoint status:\n");
+
+        for (idx = 0; idx < 15; idx++) {
+                u32 in, out;
+
+                in = readl(regs + S3C_DIEPCTL(idx));
+                out = readl(regs + S3C_DOEPCTL(idx));
+
+                seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
+                           idx, in, out);
+
+                in = readl(regs + S3C_DIEPTSIZ(idx));
+                out = readl(regs + S3C_DOEPTSIZ(idx));
+
+                seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
+                           in, out);
+
+                seq_printf(seq, "\n");
+        }
+
+        return 0;
+}
+
+static int state_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, state_show, inode->i_private);
+}
+
+static const struct file_operations state_fops = {
+        .owner          = THIS_MODULE,
+        .open           = state_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+/**
+ * fifo_show - debugfs: show the fifo information
+ * @seq: The seq_file to write data to.
+ * @v: Unused parameter.
+ *
+ * Show the FIFO information for the overall fifo and all the
+ * periodic transmission FIFOs.
+*/
+static int fifo_show(struct seq_file *seq, void *v)
+{
+        struct s3c_hsotg *hsotg = seq->private;
+        void __iomem *regs = hsotg->regs;
+        u32 val;
+        int idx;
+
+        seq_printf(seq, "Non-periodic FIFOs:\n");
+        seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
+
+        val = readl(regs + S3C_GNPTXFSIZ);
+        seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
+                   val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
+                   val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
+
+        seq_printf(seq, "\nPeriodic TXFIFOs:\n");
+
+        for (idx = 1; idx <= 15; idx++) {
+                val = readl(regs + S3C_DPTXFSIZn(idx));
+
+                seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
+                           val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
+                           val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
+        }
+
+        return 0;
+}
+
+static int fifo_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, fifo_show, inode->i_private);
+}
+
+static const struct file_operations fifo_fops = {
+        .owner          = THIS_MODULE,
+        .open           = fifo_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+
+static const char *decode_direction(int is_in)
+{
+        return is_in ? "in" : "out";
+}
+
+/**
+ * ep_show - debugfs: show the state of an endpoint.
+ * @seq: The seq_file to write data to.
+ * @v: Unused parameter.
+ *
+ * This debugfs entry shows the state of the given endpoint (one is
+ * registered for each available).
+*/
+static int ep_show(struct seq_file *seq, void *v)
+{
+        struct s3c_hsotg_ep *ep = seq->private;
+        struct s3c_hsotg *hsotg = ep->parent;
+        struct s3c_hsotg_req *req;
+        void __iomem *regs = hsotg->regs;
+        int index = ep->index;
+        int show_limit = 15;
+        unsigned long flags;
+
+        seq_printf(seq, "Endpoint index %d, named %s,  dir %s:\n",
+                   ep->index, ep->ep.name, decode_direction(ep->dir_in));
+
+        /* first show the register state */
+
+        seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
+                   readl(regs + S3C_DIEPCTL(index)),
+                   readl(regs + S3C_DOEPCTL(index)));
+
+        seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
+                   readl(regs + S3C_DIEPDMA(index)),
+                   readl(regs + S3C_DOEPDMA(index)));
+
+        seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
+                   readl(regs + S3C_DIEPINT(index)),
+                   readl(regs + S3C_DOEPINT(index)));
+
+        seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
+                   readl(regs + S3C_DIEPTSIZ(index)),
+                   readl(regs + S3C_DOEPTSIZ(index)));
+
+        seq_printf(seq, "\n");
+        seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
+        seq_printf(seq, "total_data=%ld\n", ep->total_data);
+
+        seq_printf(seq, "request list (%p,%p):\n",
+                   ep->queue.next, ep->queue.prev);
+
+        spin_lock_irqsave(&ep->lock, flags);
+
+        list_for_each_entry(req, &ep->queue, queue) {
+                if (--show_limit < 0) {
+                        seq_printf(seq, "not showing more requests...\n");
+                        break;
+                }
+
+                seq_printf(seq, "%c req %p: %d bytes @%p, ",
+                           req == ep->req ? '*' : ' ',
+                           req, req->req.length, req->req.buf);
+                seq_printf(seq, "%d done, res %d\n",
+                           req->req.actual, req->req.status);
+        }
+
+        spin_unlock_irqrestore(&ep->lock, flags);
+
+        return 0;
+}
+
+static int ep_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, ep_show, inode->i_private);
+}
+
+static const struct file_operations ep_fops = {
+        .owner          = THIS_MODULE,
+        .open           = ep_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+/**
+ * s3c_hsotg_create_debug - create debugfs directory and files
+ * @hsotg: The driver state
+ *
+ * Create the debugfs files to allow the user to get information
+ * about the state of the system. The directory name is created
+ * with the same name as the device itself, in case we end up
+ * with multiple blocks in future systems.
+*/
+static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
+{
+        struct dentry *root;
+        unsigned epidx;
+
+        root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
+        hsotg->debug_root = root;
+        if (IS_ERR(root)) {
+                dev_err(hsotg->dev, "cannot create debug root\n");
+                return;
+        }
+
+        /* create general state file */
+
+        hsotg->debug_file = debugfs_create_file("state", 0444, root,
+                                                hsotg, &state_fops);
+
+        if (IS_ERR(hsotg->debug_file))
+                dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
+
+        hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
+                                                hsotg, &fifo_fops);
+
+        if (IS_ERR(hsotg->debug_fifo))
+                dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
+
+        /* create one file for each endpoint */
+
+        for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
+                struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
+
+                ep->debugfs = debugfs_create_file(ep->name, 0444,
+                                                  root, ep, &ep_fops);
+
+                if (IS_ERR(ep->debugfs))
+                        dev_err(hsotg->dev, "failed to create %s debug file\n",
+                                ep->name);
+        }
+}
+
+/**
+ * s3c_hsotg_delete_debug - cleanup debugfs entries
+ * @hsotg: The driver state
+ *
+ * Cleanup (remove) the debugfs files for use on module exit.
+*/
+static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
+{
+        unsigned epidx;
+
+        for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
+                struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
+                debugfs_remove(ep->debugfs);
+        }
+
+        debugfs_remove(hsotg->debug_file);
+        debugfs_remove(hsotg->debug_fifo);
+        debugfs_remove(hsotg->debug_root);
+}
+
+/**
+ * s3c_hsotg_gate - set the hardware gate for the block
+ * @pdev: The device we bound to
+ * @on: On or off.
+ *
+ * Set the hardware gate setting into the block. If we end up on
+ * something other than an S3C64XX, then we might need to change this
+ * to using a platform data callback, or some other mechanism.
+ */
+static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
+{
+        unsigned long flags;
+        u32 others;
+
+        local_irq_save(flags);
+
+        others = __raw_readl(S3C64XX_OTHERS);
+        if (on)
+                others |= S3C64XX_OTHERS_USBMASK;
+        else
+                others &= ~S3C64XX_OTHERS_USBMASK;
+        __raw_writel(others, S3C64XX_OTHERS);
+
+        local_irq_restore(flags);
+}
+
+struct s3c_hsotg_plat s3c_hsotg_default_pdata;
+
+static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
+{
+        struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
+        struct device *dev = &pdev->dev;
+        struct s3c_hsotg *hsotg;
+        struct resource *res;
+        int epnum;
+        int ret;
+
+        if (!plat)
+                plat = &s3c_hsotg_default_pdata;
+
+        hsotg = kzalloc(sizeof(struct s3c_hsotg) +
+                        sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
+                        GFP_KERNEL);
+        if (!hsotg) {
+                dev_err(dev, "cannot get memory\n");
+                return -ENOMEM;
+        }
+
+        hsotg->dev = dev;
+        hsotg->plat = plat;
+
+        platform_set_drvdata(pdev, hsotg);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(dev, "cannot find register resource 0\n");
+                ret = -EINVAL;
+                goto err_mem;
+        }
+
+        hsotg->regs_res = request_mem_region(res->start, resource_size(res),
+                                             dev_name(dev));
+        if (!hsotg->regs_res) {
+                dev_err(dev, "cannot reserve registers\n");
+                ret = -ENOENT;
+                goto err_mem;
+        }
+
+        hsotg->regs = ioremap(res->start, resource_size(res));
+        if (!hsotg->regs) {
+                dev_err(dev, "cannot map registers\n");
+                ret = -ENXIO;
+                goto err_regs_res;
+        }
+
+        ret = platform_get_irq(pdev, 0);
+        if (ret < 0) {
+                dev_err(dev, "cannot find IRQ\n");
+                goto err_regs;
+        }
+
+        hsotg->irq = ret;
+
+        ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
+        if (ret < 0) {
+                dev_err(dev, "cannot claim IRQ\n");
+                goto err_regs;
+        }
+
+        dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
+
+        device_initialize(&hsotg->gadget.dev);
+
+        dev_set_name(&hsotg->gadget.dev, "gadget");
+
+        hsotg->gadget.is_dualspeed = 1;
+        hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
+        hsotg->gadget.name = dev_name(dev);
+
+        hsotg->gadget.dev.parent = dev;
+        hsotg->gadget.dev.dma_mask = dev->dma_mask;
+
+        /* setup endpoint information */
+
+        INIT_LIST_HEAD(&hsotg->gadget.ep_list);
+        hsotg->gadget.ep0 = &hsotg->eps[0].ep;
+
+        /* allocate EP0 request */
+
+        hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
+                                                     GFP_KERNEL);
+        if (!hsotg->ctrl_req) {
+                dev_err(dev, "failed to allocate ctrl req\n");
+                goto err_regs;
+        }
+
+        /* reset the system */
+
+        s3c_hsotg_gate(pdev, true);
+
+        s3c_hsotg_otgreset(hsotg);
+        s3c_hsotg_corereset(hsotg);
+        s3c_hsotg_init(hsotg);
+
+        /* initialise the endpoints now the core has been initialised */
+        for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
+                s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
+
+        s3c_hsotg_create_debug(hsotg);
+
+        s3c_hsotg_dump(hsotg);
+
+        our_hsotg = hsotg;
+        return 0;
+
+err_regs:
+        iounmap(hsotg->regs);
+
+err_regs_res:
+        release_resource(hsotg->regs_res);
+        kfree(hsotg->regs_res);
+
+err_mem:
+        kfree(hsotg);
+        return ret;
+}
+
+static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
+{
+        struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
+
+        s3c_hsotg_delete_debug(hsotg);
+
+        usb_gadget_unregister_driver(hsotg->driver);
+
+        free_irq(hsotg->irq, hsotg);
+        iounmap(hsotg->regs);
+
+        release_resource(hsotg->regs_res);
+        kfree(hsotg->regs_res);
+
+        s3c_hsotg_gate(pdev, false);
+
+        kfree(hsotg);
+        return 0;
+}
+
+#if 1
+#define s3c_hsotg_suspend NULL
+#define s3c_hsotg_resume NULL
+#endif
+
+static struct platform_driver s3c_hsotg_driver = {
+        .driver         = {
+                .name   = "s3c-hsotg",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = s3c_hsotg_probe,
+        .remove         = __devexit_p(s3c_hsotg_remove),
+        .suspend        = s3c_hsotg_suspend,
+        .resume         = s3c_hsotg_resume,
+};
+
+static int __init s3c_hsotg_modinit(void)
+{
+        return platform_driver_register(&s3c_hsotg_driver);
+}
+
+static void __exit s3c_hsotg_modexit(void)
+{
+        platform_driver_unregister(&s3c_hsotg_driver);
+}
+
+module_init(s3c_hsotg_modinit);
+module_exit(s3c_hsotg_modexit);
+
+MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:s3c-hsotg");
diff --git a/drivers/usb/gadget/u_audio.c b/drivers/usb/gadget/u_audio.c
new file mode 100644
index 000000000000..0f3d22fc030e
--- /dev/null
+++ b/drivers/usb/gadget/u_audio.c
@@ -0,0 +1,319 @@
+/*
+ * u_audio.c -- ALSA audio utilities for Gadget stack
+ *
+ * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
+ * Copyright (C) 2008 Analog Devices, Inc
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/utsname.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/ctype.h>
+#include <linux/random.h>
+#include <linux/syscalls.h>
+
+#include "u_audio.h"
+
+/*
+ * This component encapsulates the ALSA devices for USB audio gadget
+ */
+
+#define FILE_PCM_PLAYBACK       "/dev/snd/pcmC0D0p"
+#define FILE_PCM_CAPTURE        "/dev/snd/pcmC0D0c"
+#define FILE_CONTROL            "/dev/snd/controlC0"
+
+static char *fn_play = FILE_PCM_PLAYBACK;
+module_param(fn_play, charp, S_IRUGO);
+MODULE_PARM_DESC(fn_play, "Playback PCM device file name");
+
+static char *fn_cap = FILE_PCM_CAPTURE;
+module_param(fn_cap, charp, S_IRUGO);
+MODULE_PARM_DESC(fn_cap, "Capture PCM device file name");
+
+static char *fn_cntl = FILE_CONTROL;
+module_param(fn_cntl, charp, S_IRUGO);
+MODULE_PARM_DESC(fn_cntl, "Control device file name");
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * Some ALSA internal helper functions
+ */
+static int snd_interval_refine_set(struct snd_interval *i, unsigned int val)
+{
+        struct snd_interval t;
+        t.empty = 0;
+        t.min = t.max = val;
+        t.openmin = t.openmax = 0;
+        t.integer = 1;
+        return snd_interval_refine(i, &t);
+}
+
+static int _snd_pcm_hw_param_set(struct snd_pcm_hw_params *params,
+                                 snd_pcm_hw_param_t var, unsigned int val,
+                                 int dir)
+{
+        int changed;
+        if (hw_is_mask(var)) {
+                struct snd_mask *m = hw_param_mask(params, var);
+                if (val == 0 && dir < 0) {
+                        changed = -EINVAL;
+                        snd_mask_none(m);
+                } else {
+                        if (dir > 0)
+                                val++;
+                        else if (dir < 0)
+                                val--;
+                        changed = snd_mask_refine_set(
+                                        hw_param_mask(params, var), val);
+                }
+        } else if (hw_is_interval(var)) {
+                struct snd_interval *i = hw_param_interval(params, var);
+                if (val == 0 && dir < 0) {
+                        changed = -EINVAL;
+                        snd_interval_none(i);
+                } else if (dir == 0)
+                        changed = snd_interval_refine_set(i, val);
+                else {
+                        struct snd_interval t;
+                        t.openmin = 1;
+                        t.openmax = 1;
+                        t.empty = 0;
+                        t.integer = 0;
+                        if (dir < 0) {
+                                t.min = val - 1;
+                                t.max = val;
+                        } else {
+                                t.min = val;
+                                t.max = val+1;
+                        }
+                        changed = snd_interval_refine(i, &t);
+                }
+        } else
+                return -EINVAL;
+        if (changed) {
+                params->cmask |= 1 << var;
+                params->rmask |= 1 << var;
+        }
+        return changed;
+}
+/*-------------------------------------------------------------------------*/
+
+/**
+ * Set default hardware params
+ */
+static int playback_default_hw_params(struct gaudio_snd_dev *snd)
+{
+        struct snd_pcm_substream *substream = snd->substream;
+        struct snd_pcm_hw_params *params;
+        snd_pcm_sframes_t result;
+
+       /*
+        * SNDRV_PCM_ACCESS_RW_INTERLEAVED,
+        * SNDRV_PCM_FORMAT_S16_LE
+        * CHANNELS: 2
+        * RATE: 48000
+        */
+        snd->access = SNDRV_PCM_ACCESS_RW_INTERLEAVED;
+        snd->format = SNDRV_PCM_FORMAT_S16_LE;
+        snd->channels = 2;
+        snd->rate = 48000;
+
+        params = kzalloc(sizeof(*params), GFP_KERNEL);
+        if (!params)
+                return -ENOMEM;
+
+        _snd_pcm_hw_params_any(params);
+        _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_ACCESS,
+                        snd->access, 0);
+        _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_FORMAT,
+                        snd->format, 0);
+        _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_CHANNELS,
+                        snd->channels, 0);
+        _snd_pcm_hw_param_set(params, SNDRV_PCM_HW_PARAM_RATE,
+                        snd->rate, 0);
+
+        snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_DROP, NULL);
+        snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_HW_PARAMS, params);
+
+        result = snd_pcm_kernel_ioctl(substream, SNDRV_PCM_IOCTL_PREPARE, NULL);
+        if (result < 0) {
+                ERROR(snd->card,
+                        "Preparing sound card failed: %d\n", (int)result);
+                kfree(params);
+                return result;
+        }
+
+        /* Store the hardware parameters */
+        snd->access = params_access(params);
+        snd->format = params_format(params);
+        snd->channels = params_channels(params);
+        snd->rate = params_rate(params);
+
+        kfree(params);
+
+        INFO(snd->card,
+                "Hardware params: access %x, format %x, channels %d, rate %d\n",
+                snd->access, snd->format, snd->channels, snd->rate);
+
+        return 0;
+}
+
+/**
+ * Playback audio buffer data by ALSA PCM device
+ */
+static size_t u_audio_playback(struct gaudio *card, void *buf, size_t count)
+{
+        struct gaudio_snd_dev   *snd = &card->playback;
+        struct snd_pcm_substream *substream = snd->substream;
+        struct snd_pcm_runtime *runtime = substream->runtime;
+        mm_segment_t old_fs;
+        ssize_t result;
+        snd_pcm_sframes_t frames;
+
+try_again:
+        if (runtime->status->state == SNDRV_PCM_STATE_XRUN ||
+                runtime->status->state == SNDRV_PCM_STATE_SUSPENDED) {
+                result = snd_pcm_kernel_ioctl(substream,
+                                SNDRV_PCM_IOCTL_PREPARE, NULL);
+                if (result < 0) {
+                        ERROR(card, "Preparing sound card failed: %d\n",
+                                        (int)result);
+                        return result;
+                }
+        }
+
+        frames = bytes_to_frames(runtime, count);
+        old_fs = get_fs();
+        set_fs(KERNEL_DS);
+        result = snd_pcm_lib_write(snd->substream, buf, frames);
+        if (result != frames) {
+                ERROR(card, "Playback error: %d\n", (int)result);
+                set_fs(old_fs);
+                goto try_again;
+        }
+        set_fs(old_fs);
+
+        return 0;
+}
+
+static int u_audio_get_playback_channels(struct gaudio *card)
+{
+        return card->playback.channels;
+}
+
+static int u_audio_get_playback_rate(struct gaudio *card)
+{
+        return card->playback.rate;
+}
+
+/**
+ * Open ALSA PCM and control device files
+ * Initial the PCM or control device
+ */
+static int gaudio_open_snd_dev(struct gaudio *card)
+{
+        struct snd_pcm_file *pcm_file;
+        struct gaudio_snd_dev *snd;
+
+        if (!card)
+                return -ENODEV;
+
+        /* Open control device */
+        snd = &card->control;
+        snd->filp = filp_open(fn_cntl, O_RDWR, 0);
+        if (IS_ERR(snd->filp)) {
+                int ret = PTR_ERR(snd->filp);
+                ERROR(card, "unable to open sound control device file: %s\n",
+                                fn_cntl);
+                snd->filp = NULL;
+                return ret;
+        }
+        snd->card = card;
+
+        /* Open PCM playback device and setup substream */
+        snd = &card->playback;
+        snd->filp = filp_open(fn_play, O_WRONLY, 0);
+        if (IS_ERR(snd->filp)) {
+                ERROR(card, "No such PCM playback device: %s\n", fn_play);
+                snd->filp = NULL;
+        }
+        pcm_file = snd->filp->private_data;
+        snd->substream = pcm_file->substream;
+        snd->card = card;
+        playback_default_hw_params(snd);
+
+        /* Open PCM capture device and setup substream */
+        snd = &card->capture;
+        snd->filp = filp_open(fn_cap, O_RDONLY, 0);
+        if (IS_ERR(snd->filp)) {
+                ERROR(card, "No such PCM capture device: %s\n", fn_cap);
+                snd->filp = NULL;
+        }
+        pcm_file = snd->filp->private_data;
+        snd->substream = pcm_file->substream;
+        snd->card = card;
+
+        return 0;
+}
+
+/**
+ * Close ALSA PCM and control device files
+ */
+static int gaudio_close_snd_dev(struct gaudio *gau)
+{
+        struct gaudio_snd_dev   *snd;
+
+        /* Close control device */
+        snd = &gau->control;
+        if (!IS_ERR(snd->filp))
+                filp_close(snd->filp, current->files);
+
+        /* Close PCM playback device and setup substream */
+        snd = &gau->playback;
+        if (!IS_ERR(snd->filp))
+                filp_close(snd->filp, current->files);
+
+        /* Close PCM capture device and setup substream */
+        snd = &gau->capture;
+        if (!IS_ERR(snd->filp))
+                filp_close(snd->filp, current->files);
+
+        return 0;
+}
+
+/**
+ * gaudio_setup - setup ALSA interface and preparing for USB transfer
+ *
+ * This sets up PCM, mixer or MIDI ALSA devices fore USB gadget using.
+ *
+ * Returns negative errno, or zero on success
+ */
+int __init gaudio_setup(struct gaudio *card)
+{
+        int     ret;
+
+        ret = gaudio_open_snd_dev(card);
+        if (ret)
+                ERROR(card, "we need at least one control device\n");
+
+        return ret;
+
+}
+
+/**
+ * gaudio_cleanup - remove ALSA device interface
+ *
+ * This is called to free all resources allocated by @gaudio_setup().
+ */
+void gaudio_cleanup(struct gaudio *card)
+{
+        if (card)
+                gaudio_close_snd_dev(card);
+}
+
diff --git a/drivers/usb/gadget/u_audio.h b/drivers/usb/gadget/u_audio.h
new file mode 100644
index 000000000000..cc8d159c648a
--- /dev/null
+++ b/drivers/usb/gadget/u_audio.h
@@ -0,0 +1,56 @@
+/*
+ * u_audio.h -- interface to USB gadget "ALSA AUDIO" utilities
+ *
+ * Copyright (C) 2008 Bryan Wu <cooloney@kernel.org>
+ * Copyright (C) 2008 Analog Devices, Inc
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __U_AUDIO_H
+#define __U_AUDIO_H
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/usb/audio.h>
+#include <linux/usb/composite.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+
+#include "gadget_chips.h"
+
+/*
+ * This represents the USB side of an audio card device, managed by a USB
+ * function which provides control and stream interfaces.
+ */
+
+struct gaudio_snd_dev {
+        struct gaudio                   *card;
+        struct file                     *filp;
+        struct snd_pcm_substream        *substream;
+        int                             access;
+        int                             format;
+        int                             channels;
+        int                             rate;
+};
+
+struct gaudio {
+        struct usb_function             func;
+        struct usb_gadget               *gadget;
+
+        /* ALSA sound device interfaces */
+        struct gaudio_snd_dev           control;
+        struct gaudio_snd_dev           playback;
+        struct gaudio_snd_dev           capture;
+
+        /* TODO */
+};
+
+int gaudio_setup(struct gaudio *card);
+void gaudio_cleanup(struct gaudio *card);
+
+#endif /* __U_AUDIO_H */
diff --git a/drivers/usb/gadget/u_serial.c b/drivers/usb/gadget/u_serial.c
index 0a4d99ab40d8..fc6e709f45b1 100644
--- a/drivers/usb/gadget/u_serial.c
+++ b/drivers/usb/gadget/u_serial.c
@@ -371,6 +371,7 @@ __acquires(&port->port_lock)
 
                 req->length = len;
                 list_del(&req->list);
+                req->zero = (gs_buf_data_avail(&port->port_write_buf) == 0);
 
                 pr_vdebug(PREFIX "%d: tx len=%d, 0x%02x 0x%02x 0x%02x ...\n",
                                 port->port_num, len, *((u8 *)req->buf),
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 845479f7c707..1576a0520adf 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -17,6 +17,26 @@ config USB_C67X00_HCD
           To compile this driver as a module, choose M here: the
           module will be called c67x00.
 
+config USB_XHCI_HCD
+        tristate "xHCI HCD (USB 3.0) support (EXPERIMENTAL)"
+        depends on USB && PCI && EXPERIMENTAL
+        ---help---
+          The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
+          "SuperSpeed" host controller hardware.
+
+          To compile this driver as a module, choose M here: the
+          module will be called xhci-hcd.
+
+config USB_XHCI_HCD_DEBUGGING
+        bool "Debugging for the xHCI host controller"
+        depends on USB_XHCI_HCD
+        ---help---
+          Say 'Y' to turn on debugging for the xHCI host controller driver.
+          This will spew debugging output, even in interrupt context.
+          This should only be used for debugging xHCI driver bugs.
+
+          If unsure, say N.
+
 config USB_EHCI_HCD
         tristate "EHCI HCD (USB 2.0) support"
         depends on USB && USB_ARCH_HAS_EHCI
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index f163571e33d8..289d748bb414 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -12,6 +12,7 @@ fhci-objs := fhci-hcd.o fhci-hub.o fhci-q.o fhci-mem.o \
 ifeq ($(CONFIG_FHCI_DEBUG),y)
 fhci-objs += fhci-dbg.o
 endif
+xhci-objs := xhci-hcd.o xhci-mem.o xhci-pci.o xhci-ring.o xhci-hub.o xhci-dbg.o
 
 obj-$(CONFIG_USB_WHCI_HCD)      += whci/
 
@@ -23,6 +24,7 @@ obj-$(CONFIG_USB_ISP116X_HCD)	+= isp116x-hcd.o
 obj-$(CONFIG_USB_OHCI_HCD)      += ohci-hcd.o
 obj-$(CONFIG_USB_UHCI_HCD)      += uhci-hcd.o
 obj-$(CONFIG_USB_FHCI_HCD)      += fhci.o
+obj-$(CONFIG_USB_XHCI_HCD)      += xhci.o
 obj-$(CONFIG_USB_SL811_HCD)     += sl811-hcd.o
 obj-$(CONFIG_USB_SL811_CS)      += sl811_cs.o
 obj-$(CONFIG_USB_U132_HCD)      += u132-hcd.o
diff --git a/drivers/usb/host/ehci-au1xxx.c b/drivers/usb/host/ehci-au1xxx.c
index bf69f4739107..c3a778bd359c 100644
--- a/drivers/usb/host/ehci-au1xxx.c
+++ b/drivers/usb/host/ehci-au1xxx.c
@@ -97,6 +97,7 @@ static const struct hc_driver ehci_au1xxx_hc_driver = {
         .urb_enqueue            = ehci_urb_enqueue,
         .urb_dequeue            = ehci_urb_dequeue,
         .endpoint_disable       = ehci_endpoint_disable,
+        .endpoint_reset         = ehci_endpoint_reset,
 
         /*
          * scheduling support
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 01c3da34f678..bf86809c5120 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -309,6 +309,7 @@ static const struct hc_driver ehci_fsl_hc_driver = {
         .urb_enqueue = ehci_urb_enqueue,
         .urb_dequeue = ehci_urb_dequeue,
         .endpoint_disable = ehci_endpoint_disable,
+        .endpoint_reset = ehci_endpoint_reset,
 
         /*
          * scheduling support
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index c637207a1c80..2b72473544d3 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -1024,6 +1024,51 @@ done:
         return;
 }
 
+static void
+ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
+{
+        struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
+        struct ehci_qh          *qh;
+        int                     eptype = usb_endpoint_type(&ep->desc);
+
+        if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
+                return;
+
+ rescan:
+        spin_lock_irq(&ehci->lock);
+        qh = ep->hcpriv;
+
+        /* For Bulk and Interrupt endpoints we maintain the toggle state
+         * in the hardware; the toggle bits in udev aren't used at all.
+         * When an endpoint is reset by usb_clear_halt() we must reset
+         * the toggle bit in the QH.
+         */
+        if (qh) {
+                if (!list_empty(&qh->qtd_list)) {
+                        WARN_ONCE(1, "clear_halt for a busy endpoint\n");
+                } else if (qh->qh_state == QH_STATE_IDLE) {
+                        qh->hw_token &= ~cpu_to_hc32(ehci, QTD_TOGGLE);
+                } else {
+                        /* It's not safe to write into the overlay area
+                         * while the QH is active.  Unlink it first and
+                         * wait for the unlink to complete.
+                         */
+                        if (qh->qh_state == QH_STATE_LINKED) {
+                                if (eptype == USB_ENDPOINT_XFER_BULK) {
+                                        unlink_async(ehci, qh);
+                                } else {
+                                        intr_deschedule(ehci, qh);
+                                        (void) qh_schedule(ehci, qh);
+                                }
+                        }
+                        spin_unlock_irq(&ehci->lock);
+                        schedule_timeout_uninterruptible(1);
+                        goto rescan;
+                }
+        }
+        spin_unlock_irq(&ehci->lock);
+}
+
 static int ehci_get_frame (struct usb_hcd *hcd)
 {
         struct ehci_hcd         *ehci = hcd_to_ehci (hcd);
@@ -1097,7 +1142,7 @@ static int __init ehci_hcd_init(void)
                  sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
 
 #ifdef DEBUG
-        ehci_debug_root = debugfs_create_dir("ehci", NULL);
+        ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
         if (!ehci_debug_root) {
                 retval = -ENOENT;
                 goto err_debug;
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index 97a53a48a3d8..f46ad27c9a90 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -391,7 +391,7 @@ static inline void create_companion_file(struct ehci_hcd *ehci)
 
         /* with integrated TT there is no companion! */
         if (!ehci_is_TDI(ehci))
-                i = device_create_file(ehci_to_hcd(ehci)->self.dev,
+                i = device_create_file(ehci_to_hcd(ehci)->self.controller,
                                        &dev_attr_companion);
 }
 
@@ -399,7 +399,7 @@ static inline void remove_companion_file(struct ehci_hcd *ehci)
 {
         /* with integrated TT there is no companion! */
         if (!ehci_is_TDI(ehci))
-                device_remove_file(ehci_to_hcd(ehci)->self.dev,
+                device_remove_file(ehci_to_hcd(ehci)->self.controller,
                                    &dev_attr_companion);
 }
 
diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c
index 9c32063a0c2f..a44bb4a94954 100644
--- a/drivers/usb/host/ehci-ixp4xx.c
+++ b/drivers/usb/host/ehci-ixp4xx.c
@@ -51,6 +51,7 @@ static const struct hc_driver ixp4xx_ehci_hc_driver = {
         .urb_enqueue            = ehci_urb_enqueue,
         .urb_dequeue            = ehci_urb_dequeue,
         .endpoint_disable       = ehci_endpoint_disable,
+        .endpoint_reset         = ehci_endpoint_reset,
         .get_frame_number       = ehci_get_frame,
         .hub_status_data        = ehci_hub_status_data,
         .hub_control            = ehci_hub_control,
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
index 9d487908012e..770dd9aba62a 100644
--- a/drivers/usb/host/ehci-orion.c
+++ b/drivers/usb/host/ehci-orion.c
@@ -149,6 +149,7 @@ static const struct hc_driver ehci_orion_hc_driver = {
         .urb_enqueue = ehci_urb_enqueue,
         .urb_dequeue = ehci_urb_dequeue,
         .endpoint_disable = ehci_endpoint_disable,
+        .endpoint_reset = ehci_endpoint_reset,
 
         /*
          * scheduling support
@@ -187,7 +188,7 @@ ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
         }
 }
 
-static int __init ehci_orion_drv_probe(struct platform_device *pdev)
+static int __devinit ehci_orion_drv_probe(struct platform_device *pdev)
 {
         struct orion_ehci_data *pd = pdev->dev.platform_data;
         struct resource *res;
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 5aa8bce90e1f..f3683e1da161 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -268,7 +268,7 @@ done:
  * Also they depend on separate root hub suspend/resume.
  */
 
-static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
+static int ehci_pci_suspend(struct usb_hcd *hcd)
 {
         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
         unsigned long           flags;
@@ -293,12 +293,6 @@ static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
         (void)ehci_readl(ehci, &ehci->regs->intr_enable);
 
-        /* make sure snapshot being resumed re-enumerates everything */
-        if (message.event == PM_EVENT_PRETHAW) {
-                ehci_halt(ehci);
-                ehci_reset(ehci);
-        }
-
         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  bail:
         spin_unlock_irqrestore (&ehci->lock, flags);
@@ -309,7 +303,7 @@ static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
         return rc;
 }
 
-static int ehci_pci_resume(struct usb_hcd *hcd)
+static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 {
         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
@@ -322,10 +316,12 @@ static int ehci_pci_resume(struct usb_hcd *hcd)
         /* Mark hardware accessible again as we are out of D3 state by now */
         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 
-        /* If CF is still set, we maintained PCI Vaux power.
+        /* If CF is still set and we aren't resuming from hibernation
+         * then we maintained PCI Vaux power.
          * Just undo the effect of ehci_pci_suspend().
          */
-        if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) {
+        if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
+                                !hibernated) {
                 int     mask = INTR_MASK;
 
                 if (!hcd->self.root_hub->do_remote_wakeup)
@@ -335,7 +331,6 @@ static int ehci_pci_resume(struct usb_hcd *hcd)
                 return 0;
         }
 
-        ehci_dbg(ehci, "lost power, restarting\n");
         usb_root_hub_lost_power(hcd->self.root_hub);
 
         /* Else reset, to cope with power loss or flush-to-storage
@@ -393,6 +388,7 @@ static const struct hc_driver ehci_pci_hc_driver = {
         .urb_enqueue =          ehci_urb_enqueue,
         .urb_dequeue =          ehci_urb_dequeue,
         .endpoint_disable =     ehci_endpoint_disable,
+        .endpoint_reset =       ehci_endpoint_reset,
 
         /*
          * scheduling support
@@ -429,10 +425,11 @@ static struct pci_driver ehci_pci_driver = {
 
         .probe =        usb_hcd_pci_probe,
         .remove =       usb_hcd_pci_remove,
+        .shutdown =     usb_hcd_pci_shutdown,
 
-#ifdef  CONFIG_PM
-        .suspend =      usb_hcd_pci_suspend,
-        .resume =       usb_hcd_pci_resume,
+#ifdef CONFIG_PM_SLEEP
+        .driver =       {
+                .pm =   &usb_hcd_pci_pm_ops
+        },
 #endif
-        .shutdown =     usb_hcd_pci_shutdown,
 };
diff --git a/drivers/usb/host/ehci-ppc-of.c b/drivers/usb/host/ehci-ppc-of.c
index ef732b704f53..fbd272288fc2 100644
--- a/drivers/usb/host/ehci-ppc-of.c
+++ b/drivers/usb/host/ehci-ppc-of.c
@@ -61,6 +61,7 @@ static const struct hc_driver ehci_ppc_of_hc_driver = {
         .urb_enqueue            = ehci_urb_enqueue,
         .urb_dequeue            = ehci_urb_dequeue,
         .endpoint_disable       = ehci_endpoint_disable,
+        .endpoint_reset         = ehci_endpoint_reset,
 
         /*
          * scheduling support
diff --git a/drivers/usb/host/ehci-ps3.c b/drivers/usb/host/ehci-ps3.c
index 3e8844e56ca9..93f7035d00a1 100644
--- a/drivers/usb/host/ehci-ps3.c
+++ b/drivers/usb/host/ehci-ps3.c
@@ -65,6 +65,7 @@ static const struct hc_driver ps3_ehci_hc_driver = {
         .urb_enqueue            = ehci_urb_enqueue,
         .urb_dequeue            = ehci_urb_dequeue,
         .endpoint_disable       = ehci_endpoint_disable,
+        .endpoint_reset         = ehci_endpoint_reset,
         .get_frame_number       = ehci_get_frame,
         .hub_status_data        = ehci_hub_status_data,
         .hub_control            = ehci_hub_control,
diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c
index 1976b1b3778c..3192f683f807 100644
--- a/drivers/usb/host/ehci-q.c
+++ b/drivers/usb/host/ehci-q.c
@@ -93,22 +93,6 @@ qh_update (struct ehci_hcd *ehci, struct ehci_qh *qh, struct ehci_qtd *qtd)
         qh->hw_qtd_next = QTD_NEXT(ehci, qtd->qtd_dma);
         qh->hw_alt_next = EHCI_LIST_END(ehci);
 
-        /* Except for control endpoints, we make hardware maintain data
-         * toggle (like OHCI) ... here (re)initialize the toggle in the QH,
-         * and set the pseudo-toggle in udev. Only usb_clear_halt() will
-         * ever clear it.
-         */
-        if (!(qh->hw_info1 & cpu_to_hc32(ehci, 1 << 14))) {
-                unsigned        is_out, epnum;
-
-                is_out = !(qtd->hw_token & cpu_to_hc32(ehci, 1 << 8));
-                epnum = (hc32_to_cpup(ehci, &qh->hw_info1) >> 8) & 0x0f;
-                if (unlikely (!usb_gettoggle (qh->dev, epnum, is_out))) {
-                        qh->hw_token &= ~cpu_to_hc32(ehci, QTD_TOGGLE);
-                        usb_settoggle (qh->dev, epnum, is_out, 1);
-                }
-        }
-
         /* HC must see latest qtd and qh data before we clear ACTIVE+HALT */
         wmb ();
         qh->hw_token &= cpu_to_hc32(ehci, QTD_TOGGLE | QTD_STS_PING);
@@ -850,7 +834,6 @@ done:
         qh->qh_state = QH_STATE_IDLE;
         qh->hw_info1 = cpu_to_hc32(ehci, info1);
         qh->hw_info2 = cpu_to_hc32(ehci, info2);
-        usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), !is_input, 1);
         qh_refresh (ehci, qh);
         return qh;
 }
@@ -881,7 +864,7 @@ static void qh_link_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
                 }
         }
 
-        /* clear halt and/or toggle; and maybe recover from silicon quirk */
+        /* clear halt and maybe recover from silicon quirk */
         if (qh->qh_state == QH_STATE_IDLE)
                 qh_refresh (ehci, qh);
 
diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c
index 556d0ec0c1f8..9d1babc7ff65 100644
--- a/drivers/usb/host/ehci-sched.c
+++ b/drivers/usb/host/ehci-sched.c
@@ -760,8 +760,10 @@ static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
         if (status) {
                 /* "normal" case, uframing flexible except with splits */
                 if (qh->period) {
-                        frame = qh->period - 1;
-                        do {
+                        int             i;
+
+                        for (i = qh->period; status && i > 0; --i) {
+                                frame = ++ehci->random_frame % qh->period;
                                 for (uframe = 0; uframe < 8; uframe++) {
                                         status = check_intr_schedule (ehci,
                                                         frame, uframe, qh,
@@ -769,7 +771,7 @@ static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
                                         if (status == 0)
                                                 break;
                                 }
-                        } while (status && frame--);
+                        }
 
                 /* qh->period == 0 means every uframe */
                 } else {
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 6cff195e1a36..90ad3395bb21 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -116,6 +116,7 @@ struct ehci_hcd {			/* one per controller */
         struct timer_list       watchdog;
         unsigned long           actions;
         unsigned                stamp;
+        unsigned                random_frame;
         unsigned long           next_statechange;
         u32                     command;
 
diff --git a/drivers/usb/host/fhci-dbg.c b/drivers/usb/host/fhci-dbg.c
index ea8a4255c5da..e799f86dab11 100644
--- a/drivers/usb/host/fhci-dbg.c
+++ b/drivers/usb/host/fhci-dbg.c
@@ -108,7 +108,7 @@ void fhci_dfs_create(struct fhci_hcd *fhci)
 {
         struct device *dev = fhci_to_hcd(fhci)->self.controller;
 
-        fhci->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
+        fhci->dfs_root = debugfs_create_dir(dev_name(dev), usb_debug_root);
         if (!fhci->dfs_root) {
                 WARN_ON(1);
                 return;
diff --git a/drivers/usb/host/hwa-hc.c b/drivers/usb/host/hwa-hc.c
index cbf30e515f29..88b03214622b 100644
--- a/drivers/usb/host/hwa-hc.c
+++ b/drivers/usb/host/hwa-hc.c
@@ -172,25 +172,6 @@ error_cluster_id_get:
 
 }
 
-static int hwahc_op_suspend(struct usb_hcd *usb_hcd, pm_message_t msg)
-{
-        struct wusbhc *wusbhc = usb_hcd_to_wusbhc(usb_hcd);
-        struct hwahc *hwahc = container_of(wusbhc, struct hwahc, wusbhc);
-        dev_err(wusbhc->dev, "%s (%p [%p], 0x%lx) UNIMPLEMENTED\n", __func__,
-                usb_hcd, hwahc, *(unsigned long *) &msg);
-        return -ENOSYS;
-}
-
-static int hwahc_op_resume(struct usb_hcd *usb_hcd)
-{
-        struct wusbhc *wusbhc = usb_hcd_to_wusbhc(usb_hcd);
-        struct hwahc *hwahc = container_of(wusbhc, struct hwahc, wusbhc);
-
-        dev_err(wusbhc->dev, "%s (%p [%p]) UNIMPLEMENTED\n", __func__,
-                usb_hcd, hwahc);
-        return -ENOSYS;
-}
-
 /*
  * No need to abort pipes, as when this is called, all the children
  * has been disconnected and that has done it [through
@@ -598,8 +579,6 @@ static struct hc_driver hwahc_hc_driver = {
         .flags = HCD_USB2,              /* FIXME */
         .reset = hwahc_op_reset,
         .start = hwahc_op_start,
-        .pci_suspend = hwahc_op_suspend,
-        .pci_resume = hwahc_op_resume,
         .stop = hwahc_op_stop,
         .get_frame_number = hwahc_op_get_frame_number,
         .urb_enqueue = hwahc_op_urb_enqueue,
diff --git a/drivers/usb/host/ohci-dbg.c b/drivers/usb/host/ohci-dbg.c
index d3269656aa4d..811f5dfdc582 100644
--- a/drivers/usb/host/ohci-dbg.c
+++ b/drivers/usb/host/ohci-dbg.c
@@ -431,7 +431,7 @@ static struct dentry *ohci_debug_root;
 
 struct debug_buffer {
         ssize_t (*fill_func)(struct debug_buffer *);    /* fill method */
-        struct device *dev;
+        struct ohci_hcd *ohci;
         struct mutex mutex;     /* protect filling of buffer */
         size_t count;           /* number of characters filled into buffer */
         char *page;
@@ -505,15 +505,11 @@ show_list (struct ohci_hcd *ohci, char *buf, size_t count, struct ed *ed)
 
 static ssize_t fill_async_buffer(struct debug_buffer *buf)
 {
-        struct usb_bus          *bus;
-        struct usb_hcd          *hcd;
         struct ohci_hcd         *ohci;
         size_t                  temp;
         unsigned long           flags;
 
-        bus = dev_get_drvdata(buf->dev);
-        hcd = bus_to_hcd(bus);
-        ohci = hcd_to_ohci(hcd);
+        ohci = buf->ohci;
 
         /* display control and bulk lists together, for simplicity */
         spin_lock_irqsave (&ohci->lock, flags);
@@ -529,8 +525,6 @@ static ssize_t fill_async_buffer(struct debug_buffer *buf)
 
 static ssize_t fill_periodic_buffer(struct debug_buffer *buf)
 {
-        struct usb_bus          *bus;
-        struct usb_hcd          *hcd;
         struct ohci_hcd         *ohci;
         struct ed               **seen, *ed;
         unsigned long           flags;
@@ -542,9 +536,7 @@ static ssize_t fill_periodic_buffer(struct debug_buffer *buf)
                 return 0;
         seen_count = 0;
 
-        bus = (struct usb_bus *)dev_get_drvdata(buf->dev);
-        hcd = bus_to_hcd(bus);
-        ohci = hcd_to_ohci(hcd);
+        ohci = buf->ohci;
         next = buf->page;
         size = PAGE_SIZE;
 
@@ -626,7 +618,6 @@ static ssize_t fill_periodic_buffer(struct debug_buffer *buf)
 
 static ssize_t fill_registers_buffer(struct debug_buffer *buf)
 {
-        struct usb_bus          *bus;
         struct usb_hcd          *hcd;
         struct ohci_hcd         *ohci;
         struct ohci_regs __iomem *regs;
@@ -635,9 +626,8 @@ static ssize_t fill_registers_buffer(struct debug_buffer *buf)
         char                    *next;
         u32                     rdata;
 
-        bus = (struct usb_bus *)dev_get_drvdata(buf->dev);
-        hcd = bus_to_hcd(bus);
-        ohci = hcd_to_ohci(hcd);
+        ohci = buf->ohci;
+        hcd = ohci_to_hcd(ohci);
         regs = ohci->regs;
         next = buf->page;
         size = PAGE_SIZE;
@@ -710,7 +700,7 @@ done:
         return PAGE_SIZE - size;
 }
 
-static struct debug_buffer *alloc_buffer(struct device *dev,
+static struct debug_buffer *alloc_buffer(struct ohci_hcd *ohci,
                                 ssize_t (*fill_func)(struct debug_buffer *))
 {
         struct debug_buffer *buf;
@@ -718,7 +708,7 @@ static struct debug_buffer *alloc_buffer(struct device *dev,
         buf = kzalloc(sizeof(struct debug_buffer), GFP_KERNEL);
 
         if (buf) {
-                buf->dev = dev;
+                buf->ohci = ohci;
                 buf->fill_func = fill_func;
                 mutex_init(&buf->mutex);
         }
@@ -810,26 +800,25 @@ static int debug_registers_open(struct inode *inode, struct file *file)
 static inline void create_debug_files (struct ohci_hcd *ohci)
 {
         struct usb_bus *bus = &ohci_to_hcd(ohci)->self;
-        struct device *dev = bus->dev;
 
         ohci->debug_dir = debugfs_create_dir(bus->bus_name, ohci_debug_root);
         if (!ohci->debug_dir)
                 goto dir_error;
 
         ohci->debug_async = debugfs_create_file("async", S_IRUGO,
-                                                ohci->debug_dir, dev,
+                                                ohci->debug_dir, ohci,
                                                 &debug_async_fops);
         if (!ohci->debug_async)
                 goto async_error;
 
         ohci->debug_periodic = debugfs_create_file("periodic", S_IRUGO,
-                                                   ohci->debug_dir, dev,
+                                                   ohci->debug_dir, ohci,
                                                    &debug_periodic_fops);
         if (!ohci->debug_periodic)
                 goto periodic_error;
 
         ohci->debug_registers = debugfs_create_file("registers", S_IRUGO,
-                                                    ohci->debug_dir, dev,
+                                                    ohci->debug_dir, ohci,
                                                     &debug_registers_fops);
         if (!ohci->debug_registers)
                 goto registers_error;
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 25db704f3a2a..58151687d351 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -571,7 +571,7 @@ static int ohci_init (struct ohci_hcd *ohci)
  */
 static int ohci_run (struct ohci_hcd *ohci)
 {
-        u32                     mask, temp;
+        u32                     mask, val;
         int                     first = ohci->fminterval == 0;
         struct usb_hcd          *hcd = ohci_to_hcd(ohci);
 
@@ -580,8 +580,8 @@ static int ohci_run (struct ohci_hcd *ohci)
         /* boot firmware should have set this up (5.1.1.3.1) */
         if (first) {
 
-                temp = ohci_readl (ohci, &ohci->regs->fminterval);
-                ohci->fminterval = temp & 0x3fff;
+                val = ohci_readl (ohci, &ohci->regs->fminterval);
+                ohci->fminterval = val & 0x3fff;
                 if (ohci->fminterval != FI)
                         ohci_dbg (ohci, "fminterval delta %d\n",
                                 ohci->fminterval - FI);
@@ -600,25 +600,25 @@ static int ohci_run (struct ohci_hcd *ohci)
 
         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
         case OHCI_USB_OPER:
-                temp = 0;
+                val = 0;
                 break;
         case OHCI_USB_SUSPEND:
         case OHCI_USB_RESUME:
                 ohci->hc_control &= OHCI_CTRL_RWC;
                 ohci->hc_control |= OHCI_USB_RESUME;
-                temp = 10 /* msec wait */;
+                val = 10 /* msec wait */;
                 break;
         // case OHCI_USB_RESET:
         default:
                 ohci->hc_control &= OHCI_CTRL_RWC;
                 ohci->hc_control |= OHCI_USB_RESET;
-                temp = 50 /* msec wait */;
+                val = 50 /* msec wait */;
                 break;
         }
         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
         // flush the writes
         (void) ohci_readl (ohci, &ohci->regs->control);
-        msleep(temp);
+        msleep(val);
 
         memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
 
@@ -628,9 +628,9 @@ static int ohci_run (struct ohci_hcd *ohci)
 retry:
         /* HC Reset requires max 10 us delay */
         ohci_writel (ohci, OHCI_HCR,  &ohci->regs->cmdstatus);
-        temp = 30;      /* ... allow extra time */
+        val = 30;       /* ... allow extra time */
         while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
-                if (--temp == 0) {
+                if (--val == 0) {
                         spin_unlock_irq (&ohci->lock);
                         ohci_err (ohci, "USB HC reset timed out!\n");
                         return -1;
@@ -699,23 +699,23 @@ retry:
         ohci_writel (ohci, mask, &ohci->regs->intrenable);
 
         /* handle root hub init quirks ... */
-        temp = roothub_a (ohci);
-        temp &= ~(RH_A_PSM | RH_A_OCPM);
+        val = roothub_a (ohci);
+        val &= ~(RH_A_PSM | RH_A_OCPM);
         if (ohci->flags & OHCI_QUIRK_SUPERIO) {
                 /* NSC 87560 and maybe others */
-                temp |= RH_A_NOCP;
-                temp &= ~(RH_A_POTPGT | RH_A_NPS);
-                ohci_writel (ohci, temp, &ohci->regs->roothub.a);
+                val |= RH_A_NOCP;
+                val &= ~(RH_A_POTPGT | RH_A_NPS);
+                ohci_writel (ohci, val, &ohci->regs->roothub.a);
         } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
                         (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
                 /* hub power always on; required for AMD-756 and some
                  * Mac platforms.  ganged overcurrent reporting, if any.
                  */
-                temp |= RH_A_NPS;
-                ohci_writel (ohci, temp, &ohci->regs->roothub.a);
+                val |= RH_A_NPS;
+                ohci_writel (ohci, val, &ohci->regs->roothub.a);
         }
         ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
-        ohci_writel (ohci, (temp & RH_A_NPS) ? 0 : RH_B_PPCM,
+        ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
                                                 &ohci->regs->roothub.b);
         // flush those writes
         (void) ohci_readl (ohci, &ohci->regs->control);
@@ -724,7 +724,7 @@ retry:
         spin_unlock_irq (&ohci->lock);
 
         // POTPGT delay is bits 24-31, in 2 ms units.
-        mdelay ((temp >> 23) & 0x1fe);
+        mdelay ((val >> 23) & 0x1fe);
         hcd->state = HC_STATE_RUNNING;
 
         if (quirk_zfmicro(ohci)) {
@@ -1105,7 +1105,7 @@ static int __init ohci_hcd_mod_init(void)
         set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
 
 #ifdef DEBUG
-        ohci_debug_root = debugfs_create_dir("ohci", NULL);
+        ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
         if (!ohci_debug_root) {
                 retval = -ENOENT;
                 goto error_debug;
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index f9961b4c0da3..d2ba04dd785e 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -372,7 +372,7 @@ static int __devinit ohci_pci_start (struct usb_hcd *hcd)
 
 #ifdef  CONFIG_PM
 
-static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
+static int ohci_pci_suspend(struct usb_hcd *hcd)
 {
         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
         unsigned long   flags;
@@ -394,10 +394,6 @@ static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
         ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
         (void)ohci_readl(ohci, &ohci->regs->intrdisable);
 
-        /* make sure snapshot being resumed re-enumerates everything */
-        if (message.event == PM_EVENT_PRETHAW)
-                ohci_usb_reset(ohci);
-
         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  bail:
         spin_unlock_irqrestore (&ohci->lock, flags);
@@ -406,9 +402,14 @@ static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
 }
 
 
-static int ohci_pci_resume (struct usb_hcd *hcd)
+static int ohci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 {
         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+
+        /* Make sure resume from hibernation re-enumerates everything */
+        if (hibernated)
+                ohci_usb_reset(hcd_to_ohci(hcd));
+
         ohci_finish_controller_resume(hcd);
         return 0;
 }
@@ -484,12 +485,11 @@ static struct pci_driver ohci_pci_driver = {
 
         .probe =        usb_hcd_pci_probe,
         .remove =       usb_hcd_pci_remove,
+        .shutdown =     usb_hcd_pci_shutdown,
 
-#ifdef  CONFIG_PM
-        .suspend =      usb_hcd_pci_suspend,
-        .resume =       usb_hcd_pci_resume,
+#ifdef CONFIG_PM_SLEEP
+        .driver =       {
+                .pm =   &usb_hcd_pci_pm_ops
+        },
 #endif
-
-        .shutdown =     usb_hcd_pci_shutdown,
 };
-
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 033c2846ce59..83b5f9cea85a 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -15,6 +15,7 @@
 #include <linux/delay.h>
 #include <linux/acpi.h>
 #include "pci-quirks.h"
+#include "xhci-ext-caps.h"
 
 
 #define UHCI_USBLEGSUP          0xc0            /* legacy support */
@@ -341,7 +342,127 @@ static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
         return;
 }
 
+/*
+ * handshake - spin reading a register until handshake completes
+ * @ptr: address of hc register to be read
+ * @mask: bits to look at in result of read
+ * @done: value of those bits when handshake succeeds
+ * @wait_usec: timeout in microseconds
+ * @delay_usec: delay in microseconds to wait between polling
+ *
+ * Polls a register every delay_usec microseconds.
+ * Returns 0 when the mask bits have the value done.
+ * Returns -ETIMEDOUT if this condition is not true after
+ * wait_usec microseconds have passed.
+ */
+static int handshake(void __iomem *ptr, u32 mask, u32 done,
+                int wait_usec, int delay_usec)
+{
+        u32     result;
+
+        do {
+                result = readl(ptr);
+                result &= mask;
+                if (result == done)
+                        return 0;
+                udelay(delay_usec);
+                wait_usec -= delay_usec;
+        } while (wait_usec > 0);
+        return -ETIMEDOUT;
+}
+
+/**
+ * PCI Quirks for xHCI.
+ *
+ * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
+ * It signals to the BIOS that the OS wants control of the host controller,
+ * and then waits 5 seconds for the BIOS to hand over control.
+ * If we timeout, assume the BIOS is broken and take control anyway.
+ */
+static void __devinit quirk_usb_handoff_xhci(struct pci_dev *pdev)
+{
+        void __iomem *base;
+        int ext_cap_offset;
+        void __iomem *op_reg_base;
+        u32 val;
+        int timeout;
+
+        if (!mmio_resource_enabled(pdev, 0))
+                return;
+
+        base = ioremap_nocache(pci_resource_start(pdev, 0),
+                                pci_resource_len(pdev, 0));
+        if (base == NULL)
+                return;
 
+        /*
+         * Find the Legacy Support Capability register -
+         * this is optional for xHCI host controllers.
+         */
+        ext_cap_offset = xhci_find_next_cap_offset(base, XHCI_HCC_PARAMS_OFFSET);
+        do {
+                if (!ext_cap_offset)
+                        /* We've reached the end of the extended capabilities */
+                        goto hc_init;
+                val = readl(base + ext_cap_offset);
+                if (XHCI_EXT_CAPS_ID(val) == XHCI_EXT_CAPS_LEGACY)
+                        break;
+                ext_cap_offset = xhci_find_next_cap_offset(base, ext_cap_offset);
+        } while (1);
+
+        /* If the BIOS owns the HC, signal that the OS wants it, and wait */
+        if (val & XHCI_HC_BIOS_OWNED) {
+                writel(val & XHCI_HC_OS_OWNED, base + ext_cap_offset);
+
+                /* Wait for 5 seconds with 10 microsecond polling interval */
+                timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
+                                0, 5000, 10);
+
+                /* Assume a buggy BIOS and take HC ownership anyway */
+                if (timeout) {
+                        dev_warn(&pdev->dev, "xHCI BIOS handoff failed"
+                                        " (BIOS bug ?) %08x\n", val);
+                        writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
+                }
+        }
+
+        /* Disable any BIOS SMIs */
+        writel(XHCI_LEGACY_DISABLE_SMI,
+                        base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
+
+hc_init:
+        op_reg_base = base + XHCI_HC_LENGTH(readl(base));
+
+        /* Wait for the host controller to be ready before writing any
+         * operational or runtime registers.  Wait 5 seconds and no more.
+         */
+        timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
+                        5000, 10);
+        /* Assume a buggy HC and start HC initialization anyway */
+        if (timeout) {
+                val = readl(op_reg_base + XHCI_STS_OFFSET);
+                dev_warn(&pdev->dev,
+                                "xHCI HW not ready after 5 sec (HC bug?) "
+                                "status = 0x%x\n", val);
+        }
+
+        /* Send the halt and disable interrupts command */
+        val = readl(op_reg_base + XHCI_CMD_OFFSET);
+        val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
+        writel(val, op_reg_base + XHCI_CMD_OFFSET);
+
+        /* Wait for the HC to halt - poll every 125 usec (one microframe). */
+        timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
+                        XHCI_MAX_HALT_USEC, 125);
+        if (timeout) {
+                val = readl(op_reg_base + XHCI_STS_OFFSET);
+                dev_warn(&pdev->dev,
+                                "xHCI HW did not halt within %d usec "
+                                "status = 0x%x\n", XHCI_MAX_HALT_USEC, val);
+        }
+
+        iounmap(base);
+}
 
 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
 {
@@ -351,5 +472,7 @@ static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
                 quirk_usb_handoff_ohci(pdev);
         else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
                 quirk_usb_disable_ehci(pdev);
+        else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
+                quirk_usb_handoff_xhci(pdev);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c
index f1626e58c141..56976cc0352a 100644
--- a/drivers/usb/host/r8a66597-hcd.c
+++ b/drivers/usb/host/r8a66597-hcd.c
@@ -46,31 +46,10 @@ MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Yoshihiro Shimoda");
 MODULE_ALIAS("platform:r8a66597_hcd");
 
-#define DRIVER_VERSION  "10 Apr 2008"
+#define DRIVER_VERSION  "2009-05-26"
 
 static const char hcd_name[] = "r8a66597_hcd";
 
-/* module parameters */
-#if !defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
-static unsigned short clock = XTAL12;
-module_param(clock, ushort, 0644);
-MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 "
-                "(default=0)");
-#endif
-
-static unsigned short vif = LDRV;
-module_param(vif, ushort, 0644);
-MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0(default=32768)");
-
-static unsigned short endian;
-module_param(endian, ushort, 0644);
-MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)");
-
-static unsigned short irq_sense = 0xff;
-module_param(irq_sense, ushort, 0644);
-MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=32, falling edge=0 "
-                "(default=32)");
-
 static void packet_write(struct r8a66597 *r8a66597, u16 pipenum);
 static int r8a66597_get_frame(struct usb_hcd *hcd);
 
@@ -136,7 +115,8 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597)
                 }
         } while ((tmp & USBE) != USBE);
         r8a66597_bclr(r8a66597, USBE, SYSCFG0);
-        r8a66597_mdfy(r8a66597, clock, XTAL, SYSCFG0);
+        r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata), XTAL,
+                        SYSCFG0);
 
         i = 0;
         r8a66597_bset(r8a66597, XCKE, SYSCFG0);
@@ -203,6 +183,9 @@ static void r8a66597_disable_port(struct r8a66597 *r8a66597, int port)
 static int enable_controller(struct r8a66597 *r8a66597)
 {
         int ret, port;
+        u16 vif = r8a66597->pdata->vif ? LDRV : 0;
+        u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
+        u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
 
         ret = r8a66597_clock_enable(r8a66597);
         if (ret < 0)
@@ -2373,7 +2356,7 @@ static int __init_or_module r8a66597_remove(struct platform_device *pdev)
         return 0;
 }
 
-static int __init r8a66597_probe(struct platform_device *pdev)
+static int __devinit r8a66597_probe(struct platform_device *pdev)
 {
 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK)
         char clk_name[8];
@@ -2418,6 +2401,12 @@ static int __init r8a66597_probe(struct platform_device *pdev)
                 goto clean_up;
         }
 
+        if (pdev->dev.platform_data == NULL) {
+                dev_err(&pdev->dev, "no platform data\n");
+                ret = -ENODEV;
+                goto clean_up;
+        }
+
         /* initialize hcd */
         hcd = usb_create_hcd(&r8a66597_hc_driver, &pdev->dev, (char *)hcd_name);
         if (!hcd) {
@@ -2428,6 +2417,8 @@ static int __init r8a66597_probe(struct platform_device *pdev)
         r8a66597 = hcd_to_r8a66597(hcd);
         memset(r8a66597, 0, sizeof(struct r8a66597));
         dev_set_drvdata(&pdev->dev, r8a66597);
+        r8a66597->pdata = pdev->dev.platform_data;
+        r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
 
 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK)
         snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
@@ -2458,29 +2449,6 @@ static int __init r8a66597_probe(struct platform_device *pdev)
 
         hcd->rsrc_start = res->start;
 
-        /* irq_sense setting on cmdline takes precedence over resource
-         * settings, so the introduction of irqflags in IRQ resourse
-         * won't disturb existing setups */
-        switch (irq_sense) {
-                case INTL:
-                        irq_trigger = IRQF_TRIGGER_LOW;
-                        break;
-                case 0:
-                        irq_trigger = IRQF_TRIGGER_FALLING;
-                        break;
-                case 0xff:
-                        if (irq_trigger)
-                                irq_sense = (irq_trigger & IRQF_TRIGGER_LOW) ?
-                                            INTL : 0;
-                        else {
-                                irq_sense = INTL;
-                                irq_trigger = IRQF_TRIGGER_LOW;
-                        }
-                        break;
-                default:
-                        dev_err(&pdev->dev, "Unknown irq_sense value.\n");
-        }
-
         ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | irq_trigger);
         if (ret != 0) {
                 dev_err(&pdev->dev, "Failed to add hcd\n");
diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h
index f49208f1bb74..d72680b433f9 100644
--- a/drivers/usb/host/r8a66597.h
+++ b/drivers/usb/host/r8a66597.h
@@ -30,6 +30,8 @@
 #include <linux/clk.h>
 #endif
 
+#include <linux/usb/r8a66597.h>
+
 #define SYSCFG0         0x00
 #define SYSCFG1         0x02
 #define SYSSTS0         0x04
@@ -488,6 +490,7 @@ struct r8a66597 {
 #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) && defined(CONFIG_HAVE_CLK)
         struct clk *clk;
 #endif
+        struct r8a66597_platdata        *pdata;
         struct r8a66597_device          device0;
         struct r8a66597_root_hub        root_hub[R8A66597_MAX_ROOT_HUB];
         struct list_head                pipe_queue[R8A66597_MAX_NUM_PIPE];
@@ -506,6 +509,7 @@ struct r8a66597 {
         unsigned long child_connect_map[4];
 
         unsigned bus_suspended:1;
+        unsigned irq_sense_low:1;
 };
 
 static inline struct r8a66597 *hcd_to_r8a66597(struct usb_hcd *hcd)
@@ -660,10 +664,36 @@ static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
 {
         unsigned long dvstctr_reg = get_dvstctr_reg(port);
 
-        if (power)
-                r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
-        else
-                r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
+        if (r8a66597->pdata->port_power) {
+                r8a66597->pdata->port_power(port, power);
+        } else {
+                if (power)
+                        r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
+                else
+                        r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
+        }
+}
+
+static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
+{
+        u16 clock = 0;
+
+        switch (pdata->xtal) {
+        case R8A66597_PLATDATA_XTAL_12MHZ:
+                clock = XTAL12;
+                break;
+        case R8A66597_PLATDATA_XTAL_24MHZ:
+                clock = XTAL24;
+                break;
+        case R8A66597_PLATDATA_XTAL_48MHZ:
+                clock = XTAL48;
+                break;
+        default:
+                printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
+                break;
+        }
+
+        return clock;
 }
 
 #define get_pipectr_addr(pipenum)       (PIPE1CTR + (pipenum - 1) * 2)
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index cf5e4cf7ea42..274751b4409c 100644
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -769,7 +769,7 @@ static int uhci_rh_resume(struct usb_hcd *hcd)
         return rc;
 }
 
-static int uhci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
+static int uhci_pci_suspend(struct usb_hcd *hcd)
 {
         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
         int rc = 0;
@@ -795,10 +795,6 @@ static int uhci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
 
         /* FIXME: Enable non-PME# remote wakeup? */
 
-        /* make sure snapshot being resumed re-enumerates everything */
-        if (message.event == PM_EVENT_PRETHAW)
-                uhci_hc_died(uhci);
-
 done_okay:
         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 done:
@@ -806,7 +802,7 @@ done:
         return rc;
 }
 
-static int uhci_pci_resume(struct usb_hcd *hcd)
+static int uhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 {
         struct uhci_hcd *uhci = hcd_to_uhci(hcd);
 
@@ -820,6 +816,10 @@ static int uhci_pci_resume(struct usb_hcd *hcd)
 
         spin_lock_irq(&uhci->lock);
 
+        /* Make sure resume from hibernation re-enumerates everything */
+        if (hibernated)
+                uhci_hc_died(uhci);
+
         /* FIXME: Disable non-PME# remote wakeup? */
 
         /* The firmware or a boot kernel may have changed the controller
@@ -940,10 +940,11 @@ static struct pci_driver uhci_pci_driver = {
         .remove =       usb_hcd_pci_remove,
         .shutdown =     uhci_shutdown,
 
-#ifdef  CONFIG_PM
-        .suspend =      usb_hcd_pci_suspend,
-        .resume =       usb_hcd_pci_resume,
-#endif  /* PM */
+#ifdef CONFIG_PM_SLEEP
+        .driver =       {
+                .pm =   &usb_hcd_pci_pm_ops
+        },
+#endif
 };
  
 static int __init uhci_hcd_init(void)
@@ -961,7 +962,7 @@ static int __init uhci_hcd_init(void)
                 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL);
                 if (!errbuf)
                         goto errbuf_failed;
-                uhci_debugfs_root = debugfs_create_dir("uhci", NULL);
+                uhci_debugfs_root = debugfs_create_dir("uhci", usb_debug_root);
                 if (!uhci_debugfs_root)
                         goto debug_failed;
         }
diff --git a/drivers/usb/host/uhci-q.c b/drivers/usb/host/uhci-q.c
index 3e5807d14ffb..64e57bfe236b 100644
--- a/drivers/usb/host/uhci-q.c
+++ b/drivers/usb/host/uhci-q.c
@@ -260,7 +260,7 @@ static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci,
         INIT_LIST_HEAD(&qh->node);
 
         if (udev) {             /* Normal QH */
-                qh->type = hep->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
+                qh->type = usb_endpoint_type(&hep->desc);
                 if (qh->type != USB_ENDPOINT_XFER_ISOC) {
                         qh->dummy_td = uhci_alloc_td(uhci);
                         if (!qh->dummy_td) {
diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c
new file mode 100644
index 000000000000..2501c571f855
--- /dev/null
+++ b/drivers/usb/host/xhci-dbg.c
@@ -0,0 +1,485 @@
+/*
+ * xHCI host controller driver
+ *
+ * Copyright (C) 2008 Intel Corp.
+ *
+ * Author: Sarah Sharp
+ * Some code borrowed from the Linux EHCI driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "xhci.h"
+
+#define XHCI_INIT_VALUE 0x0
+
+/* Add verbose debugging later, just print everything for now */
+
+void xhci_dbg_regs(struct xhci_hcd *xhci)
+{
+        u32 temp;
+
+        xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
+                        xhci->cap_regs);
+        temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
+        xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
+                        &xhci->cap_regs->hc_capbase, temp);
+        xhci_dbg(xhci, "//   CAPLENGTH: 0x%x\n",
+                        (unsigned int) HC_LENGTH(temp));
+#if 0
+        xhci_dbg(xhci, "//   HCIVERSION: 0x%x\n",
+                        (unsigned int) HC_VERSION(temp));
+#endif
+
+        xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
+
+        temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
+        xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
+                        &xhci->cap_regs->run_regs_off,
+                        (unsigned int) temp & RTSOFF_MASK);
+        xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
+
+        temp = xhci_readl(xhci, &xhci->cap_regs->db_off);
+        xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
+        xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
+}
+
+static void xhci_print_cap_regs(struct xhci_hcd *xhci)
+{
+        u32 temp;
+
+        xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
+
+        temp = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
+        xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
+                        (unsigned int) temp);
+        xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
+                        (unsigned int) HC_LENGTH(temp));
+        xhci_dbg(xhci, "HCIVERSION: 0x%x\n",
+                        (unsigned int) HC_VERSION(temp));
+
+        temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
+        xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
+                        (unsigned int) temp);
+        xhci_dbg(xhci, "  Max device slots: %u\n",
+                        (unsigned int) HCS_MAX_SLOTS(temp));
+        xhci_dbg(xhci, "  Max interrupters: %u\n",
+                        (unsigned int) HCS_MAX_INTRS(temp));
+        xhci_dbg(xhci, "  Max ports: %u\n",
+                        (unsigned int) HCS_MAX_PORTS(temp));
+
+        temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
+        xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
+                        (unsigned int) temp);
+        xhci_dbg(xhci, "  Isoc scheduling threshold: %u\n",
+                        (unsigned int) HCS_IST(temp));
+        xhci_dbg(xhci, "  Maximum allowed segments in event ring: %u\n",
+                        (unsigned int) HCS_ERST_MAX(temp));
+
+        temp = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
+        xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
+                        (unsigned int) temp);
+        xhci_dbg(xhci, "  Worst case U1 device exit latency: %u\n",
+                        (unsigned int) HCS_U1_LATENCY(temp));
+        xhci_dbg(xhci, "  Worst case U2 device exit latency: %u\n",
+                        (unsigned int) HCS_U2_LATENCY(temp));
+
+        temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
+        xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
+        xhci_dbg(xhci, "  HC generates %s bit addresses\n",
+                        HCC_64BIT_ADDR(temp) ? "64" : "32");
+        /* FIXME */
+        xhci_dbg(xhci, "  FIXME: more HCCPARAMS debugging\n");
+
+        temp = xhci_readl(xhci, &xhci->cap_regs->run_regs_off);
+        xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
+}
+
+static void xhci_print_command_reg(struct xhci_hcd *xhci)
+{
+        u32 temp;
+
+        temp = xhci_readl(xhci, &xhci->op_regs->command);
+        xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
+        xhci_dbg(xhci, "  HC is %s\n",
+                        (temp & CMD_RUN) ? "running" : "being stopped");
+        xhci_dbg(xhci, "  HC has %sfinished hard reset\n",
+                        (temp & CMD_RESET) ? "not " : "");
+        xhci_dbg(xhci, "  Event Interrupts %s\n",
+                        (temp & CMD_EIE) ? "enabled " : "disabled");
+        xhci_dbg(xhci, "  Host System Error Interrupts %s\n",
+                        (temp & CMD_EIE) ? "enabled " : "disabled");
+        xhci_dbg(xhci, "  HC has %sfinished light reset\n",
+                        (temp & CMD_LRESET) ? "not " : "");
+}
+
+static void xhci_print_status(struct xhci_hcd *xhci)
+{
+        u32 temp;
+
+        temp = xhci_readl(xhci, &xhci->op_regs->status);
+        xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
+        xhci_dbg(xhci, "  Event ring is %sempty\n",
+                        (temp & STS_EINT) ? "not " : "");
+        xhci_dbg(xhci, "  %sHost System Error\n",
+                        (temp & STS_FATAL) ? "WARNING: " : "No ");
+        xhci_dbg(xhci, "  HC is %s\n",
+                        (temp & STS_HALT) ? "halted" : "running");
+}
+
+static void xhci_print_op_regs(struct xhci_hcd *xhci)
+{
+        xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
+        xhci_print_command_reg(xhci);
+        xhci_print_status(xhci);
+}
+
+static void xhci_print_ports(struct xhci_hcd *xhci)
+{
+        u32 __iomem *addr;
+        int i, j;
+        int ports;
+        char *names[NUM_PORT_REGS] = {
+                "status",
+                "power",
+                "link",
+                "reserved",
+        };
+
+        ports = HCS_MAX_PORTS(xhci->hcs_params1);
+        addr = &xhci->op_regs->port_status_base;
+        for (i = 0; i < ports; i++) {
+                for (j = 0; j < NUM_PORT_REGS; ++j) {
+                        xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
+                                        addr, names[j],
+                                        (unsigned int) xhci_readl(xhci, addr));
+                        addr++;
+                }
+        }
+}
+
+void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num)
+{
+        void *addr;
+        u32 temp;
+
+        addr = &ir_set->irq_pending;
+        temp = xhci_readl(xhci, addr);
+        if (temp == XHCI_INIT_VALUE)
+                return;
+
+        xhci_dbg(xhci, "  %p: ir_set[%i]\n", ir_set, set_num);
+
+        xhci_dbg(xhci, "  %p: ir_set.pending = 0x%x\n", addr,
+                        (unsigned int)temp);
+
+        addr = &ir_set->irq_control;
+        temp = xhci_readl(xhci, addr);
+        xhci_dbg(xhci, "  %p: ir_set.control = 0x%x\n", addr,
+                        (unsigned int)temp);
+
+        addr = &ir_set->erst_size;
+        temp = xhci_readl(xhci, addr);
+        xhci_dbg(xhci, "  %p: ir_set.erst_size = 0x%x\n", addr,
+                        (unsigned int)temp);
+
+        addr = &ir_set->rsvd;
+        temp = xhci_readl(xhci, addr);
+        if (temp != XHCI_INIT_VALUE)
+                xhci_dbg(xhci, "  WARN: %p: ir_set.rsvd = 0x%x\n",
+                                addr, (unsigned int)temp);
+
+        addr = &ir_set->erst_base[0];
+        temp = xhci_readl(xhci, addr);
+        xhci_dbg(xhci, "  %p: ir_set.erst_base[0] = 0x%x\n",
+                        addr, (unsigned int) temp);
+
+        addr = &ir_set->erst_base[1];
+        temp = xhci_readl(xhci, addr);
+        xhci_dbg(xhci, "  %p: ir_set.erst_base[1] = 0x%x\n",
+                        addr, (unsigned int) temp);
+
+        addr = &ir_set->erst_dequeue[0];
+        temp = xhci_readl(xhci, addr);
+        xhci_dbg(xhci, "  %p: ir_set.erst_dequeue[0] = 0x%x\n",
+                        addr, (unsigned int) temp);
+
+        addr = &ir_set->erst_dequeue[1];
+        temp = xhci_readl(xhci, addr);
+        xhci_dbg(xhci, "  %p: ir_set.erst_dequeue[1] = 0x%x\n",
+                        addr, (unsigned int) temp);
+}
+
+void xhci_print_run_regs(struct xhci_hcd *xhci)
+{
+        u32 temp;
+        int i;
+
+        xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
+        temp = xhci_readl(xhci, &xhci->run_regs->microframe_index);
+        xhci_dbg(xhci, "  %p: Microframe index = 0x%x\n",
+                        &xhci->run_regs->microframe_index,
+                        (unsigned int) temp);
+        for (i = 0; i < 7; ++i) {
+                temp = xhci_readl(xhci, &xhci->run_regs->rsvd[i]);
+                if (temp != XHCI_INIT_VALUE)
+                        xhci_dbg(xhci, "  WARN: %p: Rsvd[%i] = 0x%x\n",
+                                        &xhci->run_regs->rsvd[i],
+                                        i, (unsigned int) temp);
+        }
+}
+
+void xhci_print_registers(struct xhci_hcd *xhci)
+{
+        xhci_print_cap_regs(xhci);
+        xhci_print_op_regs(xhci);
+        xhci_print_ports(xhci);
+}
+
+void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb)
+{
+        int i;
+        for (i = 0; i < 4; ++i)
+                xhci_dbg(xhci, "Offset 0x%x = 0x%x\n",
+                                i*4, trb->generic.field[i]);
+}
+
+/**
+ * Debug a transfer request block (TRB).
+ */
+void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
+{
+        u64     address;
+        u32     type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK;
+
+        switch (type) {
+        case TRB_TYPE(TRB_LINK):
+                xhci_dbg(xhci, "Link TRB:\n");
+                xhci_print_trb_offsets(xhci, trb);
+
+                address = trb->link.segment_ptr[0] +
+                        (((u64) trb->link.segment_ptr[1]) << 32);
+                xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
+
+                xhci_dbg(xhci, "Interrupter target = 0x%x\n",
+                                GET_INTR_TARGET(trb->link.intr_target));
+                xhci_dbg(xhci, "Cycle bit = %u\n",
+                                (unsigned int) (trb->link.control & TRB_CYCLE));
+                xhci_dbg(xhci, "Toggle cycle bit = %u\n",
+                                (unsigned int) (trb->link.control & LINK_TOGGLE));
+                xhci_dbg(xhci, "No Snoop bit = %u\n",
+                                (unsigned int) (trb->link.control & TRB_NO_SNOOP));
+                break;
+        case TRB_TYPE(TRB_TRANSFER):
+                address = trb->trans_event.buffer[0] +
+                        (((u64) trb->trans_event.buffer[1]) << 32);
+                /*
+                 * FIXME: look at flags to figure out if it's an address or if
+                 * the data is directly in the buffer field.
+                 */
+                xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
+                break;
+        case TRB_TYPE(TRB_COMPLETION):
+                address = trb->event_cmd.cmd_trb[0] +
+                        (((u64) trb->event_cmd.cmd_trb[1]) << 32);
+                xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
+                xhci_dbg(xhci, "Completion status = %u\n",
+                                (unsigned int) GET_COMP_CODE(trb->event_cmd.status));
+                xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags);
+                break;
+        default:
+                xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
+                                (unsigned int) type>>10);
+                xhci_print_trb_offsets(xhci, trb);
+                break;
+        }
+}
+
+/**
+ * Debug a segment with an xHCI ring.
+ *
+ * @return The Link TRB of the segment, or NULL if there is no Link TRB
+ * (which is a bug, since all segments must have a Link TRB).
+ *
+ * Prints out all TRBs in the segment, even those after the Link TRB.
+ *
+ * XXX: should we print out TRBs that the HC owns?  As long as we don't
+ * write, that should be fine...  We shouldn't expect that the memory pointed to
+ * by the TRB is valid at all.  Do we care about ones the HC owns?  Probably,
+ * for HC debugging.
+ */
+void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
+{
+        int i;
+        u32 addr = (u32) seg->dma;
+        union xhci_trb *trb = seg->trbs;
+
+        for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
+                trb = &seg->trbs[i];
+                xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr,
+                                (unsigned int) trb->link.segment_ptr[0],
+                                (unsigned int) trb->link.segment_ptr[1],
+                                (unsigned int) trb->link.intr_target,
+                                (unsigned int) trb->link.control);
+                addr += sizeof(*trb);
+        }
+}
+
+void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring)
+{
+        xhci_dbg(xhci, "Ring deq = %p (virt), 0x%llx (dma)\n",
+                        ring->dequeue,
+                        (unsigned long long)xhci_trb_virt_to_dma(ring->deq_seg,
+                                                            ring->dequeue));
+        xhci_dbg(xhci, "Ring deq updated %u times\n",
+                        ring->deq_updates);
+        xhci_dbg(xhci, "Ring enq = %p (virt), 0x%llx (dma)\n",
+                        ring->enqueue,
+                        (unsigned long long)xhci_trb_virt_to_dma(ring->enq_seg,
+                                                            ring->enqueue));
+        xhci_dbg(xhci, "Ring enq updated %u times\n",
+                        ring->enq_updates);
+}
+
+/**
+ * Debugging for an xHCI ring, which is a queue broken into multiple segments.
+ *
+ * Print out each segment in the ring.  Check that the DMA address in
+ * each link segment actually matches the segment's stored DMA address.
+ * Check that the link end bit is only set at the end of the ring.
+ * Check that the dequeue and enqueue pointers point to real data in this ring
+ * (not some other ring).
+ */
+void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring)
+{
+        /* FIXME: Throw an error if any segment doesn't have a Link TRB */
+        struct xhci_segment *seg;
+        struct xhci_segment *first_seg = ring->first_seg;
+        xhci_debug_segment(xhci, first_seg);
+
+        if (!ring->enq_updates && !ring->deq_updates) {
+                xhci_dbg(xhci, "  Ring has not been updated\n");
+                return;
+        }
+        for (seg = first_seg->next; seg != first_seg; seg = seg->next)
+                xhci_debug_segment(xhci, seg);
+}
+
+void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
+{
+        u32 addr = (u32) erst->erst_dma_addr;
+        int i;
+        struct xhci_erst_entry *entry;
+
+        for (i = 0; i < erst->num_entries; ++i) {
+                entry = &erst->entries[i];
+                xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n",
+                                (unsigned int) addr,
+                                (unsigned int) entry->seg_addr[0],
+                                (unsigned int) entry->seg_addr[1],
+                                (unsigned int) entry->seg_size,
+                                (unsigned int) entry->rsvd);
+                addr += sizeof(*entry);
+        }
+}
+
+void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
+{
+        u32 val;
+
+        val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[0]);
+        xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = 0x%x\n", val);
+        val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[1]);
+        xhci_dbg(xhci, "// xHC command ring deq ptr high bits = 0x%x\n", val);
+}
+
+void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_device_control *ctx, dma_addr_t dma, unsigned int last_ep)
+{
+        int i, j;
+        int last_ep_ctx = 31;
+        /* Fields are 32 bits wide, DMA addresses are in bytes */
+        int field_size = 32 / 8;
+
+        xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - drop flags\n",
+                        &ctx->drop_flags, (unsigned long long)dma,
+                        ctx->drop_flags);
+        dma += field_size;
+        xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - add flags\n",
+                        &ctx->add_flags, (unsigned long long)dma,
+                        ctx->add_flags);
+        dma += field_size;
+        for (i = 0; i > 6; ++i) {
+                xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
+                                &ctx->rsvd[i], (unsigned long long)dma,
+                                ctx->rsvd[i], i);
+                dma += field_size;
+        }
+
+        xhci_dbg(xhci, "Slot Context:\n");
+        xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info\n",
+                        &ctx->slot.dev_info,
+                        (unsigned long long)dma, ctx->slot.dev_info);
+        dma += field_size;
+        xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_info2\n",
+                        &ctx->slot.dev_info2,
+                        (unsigned long long)dma, ctx->slot.dev_info2);
+        dma += field_size;
+        xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tt_info\n",
+                        &ctx->slot.tt_info,
+                        (unsigned long long)dma, ctx->slot.tt_info);
+        dma += field_size;
+        xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - dev_state\n",
+                        &ctx->slot.dev_state,
+                        (unsigned long long)dma, ctx->slot.dev_state);
+        dma += field_size;
+        for (i = 0; i > 4; ++i) {
+                xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
+                                &ctx->slot.reserved[i], (unsigned long long)dma,
+                                ctx->slot.reserved[i], i);
+                dma += field_size;
+        }
+
+        if (last_ep < 31)
+                last_ep_ctx = last_ep + 1;
+        for (i = 0; i < last_ep_ctx; ++i) {
+                xhci_dbg(xhci, "Endpoint %02d Context:\n", i);
+                xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info\n",
+                                &ctx->ep[i].ep_info,
+                                (unsigned long long)dma, ctx->ep[i].ep_info);
+                dma += field_size;
+                xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - ep_info2\n",
+                                &ctx->ep[i].ep_info2,
+                                (unsigned long long)dma, ctx->ep[i].ep_info2);
+                dma += field_size;
+                xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - deq[0]\n",
+                                &ctx->ep[i].deq[0],
+                                (unsigned long long)dma, ctx->ep[i].deq[0]);
+                dma += field_size;
+                xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - deq[1]\n",
+                                &ctx->ep[i].deq[1],
+                                (unsigned long long)dma, ctx->ep[i].deq[1]);
+                dma += field_size;
+                xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - tx_info\n",
+                                &ctx->ep[i].tx_info,
+                                (unsigned long long)dma, ctx->ep[i].tx_info);
+                dma += field_size;
+                for (j = 0; j < 3; ++j) {
+                        xhci_dbg(xhci, "@%p (virt) @%08llx (dma) %#08x - rsvd[%d]\n",
+                                        &ctx->ep[i].reserved[j],
+                                        (unsigned long long)dma,
+                                        ctx->ep[i].reserved[j], j);
+                        dma += field_size;
+                }
+        }
+}
diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
new file mode 100644
index 000000000000..ecc131c3fe33
--- /dev/null
+++ b/drivers/usb/host/xhci-ext-caps.h
@@ -0,0 +1,145 @@
+/*
+ * xHCI host controller driver
+ *
+ * Copyright (C) 2008 Intel Corp.
+ *
+ * Author: Sarah Sharp
+ * Some code borrowed from the Linux EHCI driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+/* Up to 16 microframes to halt an HC - one microframe is 125 microsectonds */
+#define XHCI_MAX_HALT_USEC      (16*125)
+/* HC not running - set to 1 when run/stop bit is cleared. */
+#define XHCI_STS_HALT           (1<<0)
+
+/* HCCPARAMS offset from PCI base address */
+#define XHCI_HCC_PARAMS_OFFSET  0x10
+/* HCCPARAMS contains the first extended capability pointer */
+#define XHCI_HCC_EXT_CAPS(p)    (((p)>>16)&0xffff)
+
+/* Command and Status registers offset from the Operational Registers address */
+#define XHCI_CMD_OFFSET         0x00
+#define XHCI_STS_OFFSET         0x04
+
+#define XHCI_MAX_EXT_CAPS               50
+
+/* Capability Register */
+/* bits 7:0 - how long is the Capabilities register */
+#define XHCI_HC_LENGTH(p)       (((p)>>00)&0x00ff)
+
+/* Extended capability register fields */
+#define XHCI_EXT_CAPS_ID(p)     (((p)>>0)&0xff)
+#define XHCI_EXT_CAPS_NEXT(p)   (((p)>>8)&0xff)
+#define XHCI_EXT_CAPS_VAL(p)    ((p)>>16)
+/* Extended capability IDs - ID 0 reserved */
+#define XHCI_EXT_CAPS_LEGACY    1
+#define XHCI_EXT_CAPS_PROTOCOL  2
+#define XHCI_EXT_CAPS_PM        3
+#define XHCI_EXT_CAPS_VIRT      4
+#define XHCI_EXT_CAPS_ROUTE     5
+/* IDs 6-9 reserved */
+#define XHCI_EXT_CAPS_DEBUG     10
+/* USB Legacy Support Capability - section 7.1.1 */
+#define XHCI_HC_BIOS_OWNED      (1 << 16)
+#define XHCI_HC_OS_OWNED        (1 << 24)
+
+/* USB Legacy Support Capability - section 7.1.1 */
+/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
+#define XHCI_LEGACY_SUPPORT_OFFSET      (0x00)
+
+/* USB Legacy Support Control and Status Register  - section 7.1.2 */
+/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
+#define XHCI_LEGACY_CONTROL_OFFSET      (0x04)
+/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
+#define XHCI_LEGACY_DISABLE_SMI         ((0x3 << 1) + (0xff << 5) + (0x7 << 17))
+
+/* command register values to disable interrupts and halt the HC */
+/* start/stop HC execution - do not write unless HC is halted*/
+#define XHCI_CMD_RUN            (1 << 0)
+/* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
+#define XHCI_CMD_EIE            (1 << 2)
+/* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
+#define XHCI_CMD_HSEIE          (1 << 3)
+/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
+#define XHCI_CMD_EWE            (1 << 10)
+
+#define XHCI_IRQS               (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
+
+/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
+#define XHCI_STS_CNR            (1 << 11)
+
+#include <linux/io.h>
+
+/**
+ * Return the next extended capability pointer register.
+ *
+ * @base        PCI register base address.
+ *
+ * @ext_offset  Offset of the 32-bit register that contains the extended
+ * capabilites pointer.  If searching for the first extended capability, pass
+ * in XHCI_HCC_PARAMS_OFFSET.  If searching for the next extended capability,
+ * pass in the offset of the current extended capability register.
+ *
+ * Returns 0 if there is no next extended capability register or returns the register offset
+ * from the PCI registers base address.
+ */
+static inline int xhci_find_next_cap_offset(void __iomem *base, int ext_offset)
+{
+        u32 next;
+
+        next = readl(base + ext_offset);
+
+        if (ext_offset == XHCI_HCC_PARAMS_OFFSET)
+                /* Find the first extended capability */
+                next = XHCI_HCC_EXT_CAPS(next);
+        else
+                /* Find the next extended capability */
+                next = XHCI_EXT_CAPS_NEXT(next);
+        if (!next)
+                return 0;
+        /*
+         * Address calculation from offset of extended capabilities
+         * (or HCCPARAMS) register - see section 5.3.6 and section 7.
+         */
+        return ext_offset + (next << 2);
+}
+
+/**
+ * Find the offset of the extended capabilities with capability ID id.
+ *
+ * @base PCI MMIO registers base address.
+ * @ext_offset Offset from base of the first extended capability to look at,
+ *              or the address of HCCPARAMS.
+ * @id Extended capability ID to search for.
+ *
+ * This uses an arbitrary limit of XHCI_MAX_EXT_CAPS extended capabilities
+ * to make sure that the list doesn't contain a loop.
+ */
+static inline int xhci_find_ext_cap_by_id(void __iomem *base, int ext_offset, int id)
+{
+        u32 val;
+        int limit = XHCI_MAX_EXT_CAPS;
+
+        while (ext_offset && limit > 0) {
+                val = readl(base + ext_offset);
+                if (XHCI_EXT_CAPS_ID(val) == id)
+                        break;
+                ext_offset = xhci_find_next_cap_offset(base, ext_offset);
+                limit--;
+        }
+        if (limit > 0)
+                return ext_offset;
+        return 0;
+}
diff --git a/drivers/usb/host/xhci-hcd.c b/drivers/usb/host/xhci-hcd.c
new file mode 100644
index 000000000000..dba3e07ccd09
--- /dev/null
+++ b/drivers/usb/host/xhci-hcd.c
@@ -0,0 +1,1274 @@
+/*
+ * xHCI host controller driver
+ *
+ * Copyright (C) 2008 Intel Corp.
+ *
+ * Author: Sarah Sharp
+ * Some code borrowed from the Linux EHCI driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/irq.h>
+#include <linux/module.h>
+
+#include "xhci.h"
+
+#define DRIVER_AUTHOR "Sarah Sharp"
+#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
+
+/* TODO: copied from ehci-hcd.c - can this be refactored? */
+/*
+ * handshake - spin reading hc until handshake completes or fails
+ * @ptr: address of hc register to be read
+ * @mask: bits to look at in result of read
+ * @done: value of those bits when handshake succeeds
+ * @usec: timeout in microseconds
+ *
+ * Returns negative errno, or zero on success
+ *
+ * Success happens when the "mask" bits have the specified value (hardware
+ * handshake done).  There are two failure modes:  "usec" have passed (major
+ * hardware flakeout), or the register reads as all-ones (hardware removed).
+ */
+static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
+                      u32 mask, u32 done, int usec)
+{
+        u32     result;
+
+        do {
+                result = xhci_readl(xhci, ptr);
+                if (result == ~(u32)0)          /* card removed */
+                        return -ENODEV;
+                result &= mask;
+                if (result == done)
+                        return 0;
+                udelay(1);
+                usec--;
+        } while (usec > 0);
+        return -ETIMEDOUT;
+}
+
+/*
+ * Force HC into halt state.
+ *
+ * Disable any IRQs and clear the run/stop bit.
+ * HC will complete any current and actively pipelined transactions, and
+ * should halt within 16 microframes of the run/stop bit being cleared.
+ * Read HC Halted bit in the status register to see when the HC is finished.
+ * XXX: shouldn't we set HC_STATE_HALT here somewhere?
+ */
+int xhci_halt(struct xhci_hcd *xhci)
+{
+        u32 halted;
+        u32 cmd;
+        u32 mask;
+
+        xhci_dbg(xhci, "// Halt the HC\n");
+        /* Disable all interrupts from the host controller */
+        mask = ~(XHCI_IRQS);
+        halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
+        if (!halted)
+                mask &= ~CMD_RUN;
+
+        cmd = xhci_readl(xhci, &xhci->op_regs->command);
+        cmd &= mask;
+        xhci_writel(xhci, cmd, &xhci->op_regs->command);
+
+        return handshake(xhci, &xhci->op_regs->status,
+                        STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
+}
+
+/*
+ * Reset a halted HC, and set the internal HC state to HC_STATE_HALT.
+ *
+ * This resets pipelines, timers, counters, state machines, etc.
+ * Transactions will be terminated immediately, and operational registers
+ * will be set to their defaults.
+ */
+int xhci_reset(struct xhci_hcd *xhci)
+{
+        u32 command;
+        u32 state;
+
+        state = xhci_readl(xhci, &xhci->op_regs->status);
+        BUG_ON((state & STS_HALT) == 0);
+
+        xhci_dbg(xhci, "// Reset the HC\n");
+        command = xhci_readl(xhci, &xhci->op_regs->command);
+        command |= CMD_RESET;
+        xhci_writel(xhci, command, &xhci->op_regs->command);
+        /* XXX: Why does EHCI set this here?  Shouldn't other code do this? */
+        xhci_to_hcd(xhci)->state = HC_STATE_HALT;
+
+        return handshake(xhci, &xhci->op_regs->command, CMD_RESET, 0, 250 * 1000);
+}
+
+/*
+ * Stop the HC from processing the endpoint queues.
+ */
+static void xhci_quiesce(struct xhci_hcd *xhci)
+{
+        /*
+         * Queues are per endpoint, so we need to disable an endpoint or slot.
+         *
+         * To disable a slot, we need to insert a disable slot command on the
+         * command ring and ring the doorbell.  This will also free any internal
+         * resources associated with the slot (which might not be what we want).
+         *
+         * A Release Endpoint command sounds better - doesn't free internal HC
+         * memory, but removes the endpoints from the schedule and releases the
+         * bandwidth, disables the doorbells, and clears the endpoint enable
+         * flag.  Usually used prior to a set interface command.
+         *
+         * TODO: Implement after command ring code is done.
+         */
+        BUG_ON(!HC_IS_RUNNING(xhci_to_hcd(xhci)->state));
+        xhci_dbg(xhci, "Finished quiescing -- code not written yet\n");
+}
+
+#if 0
+/* Set up MSI-X table for entry 0 (may claim other entries later) */
+static int xhci_setup_msix(struct xhci_hcd *xhci)
+{
+        int ret;
+        struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
+
+        xhci->msix_count = 0;
+        /* XXX: did I do this right?  ixgbe does kcalloc for more than one */
+        xhci->msix_entries = kmalloc(sizeof(struct msix_entry), GFP_KERNEL);
+        if (!xhci->msix_entries) {
+                xhci_err(xhci, "Failed to allocate MSI-X entries\n");
+                return -ENOMEM;
+        }
+        xhci->msix_entries[0].entry = 0;
+
+        ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
+        if (ret) {
+                xhci_err(xhci, "Failed to enable MSI-X\n");
+                goto free_entries;
+        }
+
+        /*
+         * Pass the xhci pointer value as the request_irq "cookie".
+         * If more irqs are added, this will need to be unique for each one.
+         */
+        ret = request_irq(xhci->msix_entries[0].vector, &xhci_irq, 0,
+                        "xHCI", xhci_to_hcd(xhci));
+        if (ret) {
+                xhci_err(xhci, "Failed to allocate MSI-X interrupt\n");
+                goto disable_msix;
+        }
+        xhci_dbg(xhci, "Finished setting up MSI-X\n");
+        return 0;
+
+disable_msix:
+        pci_disable_msix(pdev);
+free_entries:
+        kfree(xhci->msix_entries);
+        xhci->msix_entries = NULL;
+        return ret;
+}
+
+/* XXX: code duplication; can xhci_setup_msix call this? */
+/* Free any IRQs and disable MSI-X */
+static void xhci_cleanup_msix(struct xhci_hcd *xhci)
+{
+        struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
+        if (!xhci->msix_entries)
+                return;
+
+        free_irq(xhci->msix_entries[0].vector, xhci);
+        pci_disable_msix(pdev);
+        kfree(xhci->msix_entries);
+        xhci->msix_entries = NULL;
+        xhci_dbg(xhci, "Finished cleaning up MSI-X\n");
+}
+#endif
+
+/*
+ * Initialize memory for HCD and xHC (one-time init).
+ *
+ * Program the PAGESIZE register, initialize the device context array, create
+ * device contexts (?), set up a command ring segment (or two?), create event
+ * ring (one for now).
+ */
+int xhci_init(struct usb_hcd *hcd)
+{
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        int retval = 0;
+
+        xhci_dbg(xhci, "xhci_init\n");
+        spin_lock_init(&xhci->lock);
+        retval = xhci_mem_init(xhci, GFP_KERNEL);
+        xhci_dbg(xhci, "Finished xhci_init\n");
+
+        return retval;
+}
+
+/*
+ * Called in interrupt context when there might be work
+ * queued on the event ring
+ *
+ * xhci->lock must be held by caller.
+ */
+static void xhci_work(struct xhci_hcd *xhci)
+{
+        u32 temp;
+
+        /*
+         * Clear the op reg interrupt status first,
+         * so we can receive interrupts from other MSI-X interrupters.
+         * Write 1 to clear the interrupt status.
+         */
+        temp = xhci_readl(xhci, &xhci->op_regs->status);
+        temp |= STS_EINT;
+        xhci_writel(xhci, temp, &xhci->op_regs->status);
+        /* FIXME when MSI-X is supported and there are multiple vectors */
+        /* Clear the MSI-X event interrupt status */
+
+        /* Acknowledge the interrupt */
+        temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
+        temp |= 0x3;
+        xhci_writel(xhci, temp, &xhci->ir_set->irq_pending);
+        /* Flush posted writes */
+        xhci_readl(xhci, &xhci->ir_set->irq_pending);
+
+        /* FIXME this should be a delayed service routine that clears the EHB */
+        xhci_handle_event(xhci);
+
+        /* Clear the event handler busy flag; the event ring should be empty. */
+        temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
+        xhci_writel(xhci, temp & ~ERST_EHB, &xhci->ir_set->erst_dequeue[0]);
+        /* Flush posted writes -- FIXME is this necessary? */
+        xhci_readl(xhci, &xhci->ir_set->irq_pending);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * xHCI spec says we can get an interrupt, and if the HC has an error condition,
+ * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
+ * indicators of an event TRB error, but we check the status *first* to be safe.
+ */
+irqreturn_t xhci_irq(struct usb_hcd *hcd)
+{
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        u32 temp, temp2;
+
+        spin_lock(&xhci->lock);
+        /* Check if the xHC generated the interrupt, or the irq is shared */
+        temp = xhci_readl(xhci, &xhci->op_regs->status);
+        temp2 = xhci_readl(xhci, &xhci->ir_set->irq_pending);
+        if (!(temp & STS_EINT) && !ER_IRQ_PENDING(temp2)) {
+                spin_unlock(&xhci->lock);
+                return IRQ_NONE;
+        }
+
+        if (temp & STS_FATAL) {
+                xhci_warn(xhci, "WARNING: Host System Error\n");
+                xhci_halt(xhci);
+                xhci_to_hcd(xhci)->state = HC_STATE_HALT;
+                spin_unlock(&xhci->lock);
+                return -ESHUTDOWN;
+        }
+
+        xhci_work(xhci);
+        spin_unlock(&xhci->lock);
+
+        return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
+void xhci_event_ring_work(unsigned long arg)
+{
+        unsigned long flags;
+        int temp;
+        struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
+        int i, j;
+
+        xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
+
+        spin_lock_irqsave(&xhci->lock, flags);
+        temp = xhci_readl(xhci, &xhci->op_regs->status);
+        xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
+        temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
+        xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
+        xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled);
+        xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
+        xhci->error_bitmask = 0;
+        xhci_dbg(xhci, "Event ring:\n");
+        xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
+        xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
+        temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
+        temp &= ERST_PTR_MASK;
+        xhci_dbg(xhci, "ERST deq = 0x%x\n", temp);
+        xhci_dbg(xhci, "Command ring:\n");
+        xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
+        xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
+        xhci_dbg_cmd_ptrs(xhci);
+        for (i = 0; i < MAX_HC_SLOTS; ++i) {
+                if (xhci->devs[i]) {
+                        for (j = 0; j < 31; ++j) {
+                                if (xhci->devs[i]->ep_rings[j]) {
+                                        xhci_dbg(xhci, "Dev %d endpoint ring %d:\n", i, j);
+                                        xhci_debug_segment(xhci, xhci->devs[i]->ep_rings[j]->deq_seg);
+                                }
+                        }
+                }
+        }
+
+        if (xhci->noops_submitted != NUM_TEST_NOOPS)
+                if (xhci_setup_one_noop(xhci))
+                        xhci_ring_cmd_db(xhci);
+        spin_unlock_irqrestore(&xhci->lock, flags);
+
+        if (!xhci->zombie)
+                mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
+        else
+                xhci_dbg(xhci, "Quit polling the event ring.\n");
+}
+#endif
+
+/*
+ * Start the HC after it was halted.
+ *
+ * This function is called by the USB core when the HC driver is added.
+ * Its opposite is xhci_stop().
+ *
+ * xhci_init() must be called once before this function can be called.
+ * Reset the HC, enable device slot contexts, program DCBAAP, and
+ * set command ring pointer and event ring pointer.
+ *
+ * Setup MSI-X vectors and enable interrupts.
+ */
+int xhci_run(struct usb_hcd *hcd)
+{
+        u32 temp;
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        void (*doorbell)(struct xhci_hcd *) = NULL;
+
+        hcd->uses_new_polling = 1;
+        hcd->poll_rh = 0;
+
+        xhci_dbg(xhci, "xhci_run\n");
+#if 0   /* FIXME: MSI not setup yet */
+        /* Do this at the very last minute */
+        ret = xhci_setup_msix(xhci);
+        if (!ret)
+                return ret;
+
+        return -ENOSYS;
+#endif
+#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
+        init_timer(&xhci->event_ring_timer);
+        xhci->event_ring_timer.data = (unsigned long) xhci;
+        xhci->event_ring_timer.function = xhci_event_ring_work;
+        /* Poll the event ring */
+        xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
+        xhci->zombie = 0;
+        xhci_dbg(xhci, "Setting event ring polling timer\n");
+        add_timer(&xhci->event_ring_timer);
+#endif
+
+        xhci_dbg(xhci, "// Set the interrupt modulation register\n");
+        temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
+        temp &= ~ER_IRQ_INTERVAL_MASK;
+        temp |= (u32) 160;
+        xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
+
+        /* Set the HCD state before we enable the irqs */
+        hcd->state = HC_STATE_RUNNING;
+        temp = xhci_readl(xhci, &xhci->op_regs->command);
+        temp |= (CMD_EIE);
+        xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
+                        temp);
+        xhci_writel(xhci, temp, &xhci->op_regs->command);
+
+        temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
+        xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
+                        xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
+        xhci_writel(xhci, ER_IRQ_ENABLE(temp),
+                        &xhci->ir_set->irq_pending);
+        xhci_print_ir_set(xhci, xhci->ir_set, 0);
+
+        if (NUM_TEST_NOOPS > 0)
+                doorbell = xhci_setup_one_noop(xhci);
+
+        xhci_dbg(xhci, "Command ring memory map follows:\n");
+        xhci_debug_ring(xhci, xhci->cmd_ring);
+        xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
+        xhci_dbg_cmd_ptrs(xhci);
+
+        xhci_dbg(xhci, "ERST memory map follows:\n");
+        xhci_dbg_erst(xhci, &xhci->erst);
+        xhci_dbg(xhci, "Event ring:\n");
+        xhci_debug_ring(xhci, xhci->event_ring);
+        xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
+        temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
+        temp &= ERST_PTR_MASK;
+        xhci_dbg(xhci, "ERST deq = 0x%x\n", temp);
+        temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[1]);
+        xhci_dbg(xhci, "ERST deq upper = 0x%x\n", temp);
+
+        temp = xhci_readl(xhci, &xhci->op_regs->command);
+        temp |= (CMD_RUN);
+        xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
+                        temp);
+        xhci_writel(xhci, temp, &xhci->op_regs->command);
+        /* Flush PCI posted writes */
+        temp = xhci_readl(xhci, &xhci->op_regs->command);
+        xhci_dbg(xhci, "// @%p = 0x%x\n", &xhci->op_regs->command, temp);
+        if (doorbell)
+                (*doorbell)(xhci);
+
+        xhci_dbg(xhci, "Finished xhci_run\n");
+        return 0;
+}
+
+/*
+ * Stop xHCI driver.
+ *
+ * This function is called by the USB core when the HC driver is removed.
+ * Its opposite is xhci_run().
+ *
+ * Disable device contexts, disable IRQs, and quiesce the HC.
+ * Reset the HC, finish any completed transactions, and cleanup memory.
+ */
+void xhci_stop(struct usb_hcd *hcd)
+{
+        u32 temp;
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+
+        spin_lock_irq(&xhci->lock);
+        if (HC_IS_RUNNING(hcd->state))
+                xhci_quiesce(xhci);
+        xhci_halt(xhci);
+        xhci_reset(xhci);
+        spin_unlock_irq(&xhci->lock);
+
+#if 0   /* No MSI yet */
+        xhci_cleanup_msix(xhci);
+#endif
+#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
+        /* Tell the event ring poll function not to reschedule */
+        xhci->zombie = 1;
+        del_timer_sync(&xhci->event_ring_timer);
+#endif
+
+        xhci_dbg(xhci, "// Disabling event ring interrupts\n");
+        temp = xhci_readl(xhci, &xhci->op_regs->status);
+        xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
+        temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
+        xhci_writel(xhci, ER_IRQ_DISABLE(temp),
+                        &xhci->ir_set->irq_pending);
+        xhci_print_ir_set(xhci, xhci->ir_set, 0);
+
+        xhci_dbg(xhci, "cleaning up memory\n");
+        xhci_mem_cleanup(xhci);
+        xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
+                    xhci_readl(xhci, &xhci->op_regs->status));
+}
+
+/*
+ * Shutdown HC (not bus-specific)
+ *
+ * This is called when the machine is rebooting or halting.  We assume that the
+ * machine will be powered off, and the HC's internal state will be reset.
+ * Don't bother to free memory.
+ */
+void xhci_shutdown(struct usb_hcd *hcd)
+{
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+
+        spin_lock_irq(&xhci->lock);
+        xhci_halt(xhci);
+        spin_unlock_irq(&xhci->lock);
+
+#if 0
+        xhci_cleanup_msix(xhci);
+#endif
+
+        xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
+                    xhci_readl(xhci, &xhci->op_regs->status));
+}
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
+ * HCDs.  Find the index for an endpoint given its descriptor.  Use the return
+ * value to right shift 1 for the bitmask.
+ *
+ * Index  = (epnum * 2) + direction - 1,
+ * where direction = 0 for OUT, 1 for IN.
+ * For control endpoints, the IN index is used (OUT index is unused), so
+ * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
+ */
+unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
+{
+        unsigned int index;
+        if (usb_endpoint_xfer_control(desc))
+                index = (unsigned int) (usb_endpoint_num(desc)*2);
+        else
+                index = (unsigned int) (usb_endpoint_num(desc)*2) +
+                        (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
+        return index;
+}
+
+/* Find the flag for this endpoint (for use in the control context).  Use the
+ * endpoint index to create a bitmask.  The slot context is bit 0, endpoint 0 is
+ * bit 1, etc.
+ */
+unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
+{
+        return 1 << (xhci_get_endpoint_index(desc) + 1);
+}
+
+/* Compute the last valid endpoint context index.  Basically, this is the
+ * endpoint index plus one.  For slot contexts with more than valid endpoint,
+ * we find the most significant bit set in the added contexts flags.
+ * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
+ * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
+ */
+static inline unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
+{
+        return fls(added_ctxs) - 1;
+}
+
+/* Returns 1 if the arguments are OK;
+ * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
+ */
+int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
+                struct usb_host_endpoint *ep, int check_ep, const char *func) {
+        if (!hcd || (check_ep && !ep) || !udev) {
+                printk(KERN_DEBUG "xHCI %s called with invalid args\n",
+                                func);
+                return -EINVAL;
+        }
+        if (!udev->parent) {
+                printk(KERN_DEBUG "xHCI %s called for root hub\n",
+                                func);
+                return 0;
+        }
+        if (!udev->slot_id) {
+                printk(KERN_DEBUG "xHCI %s called with unaddressed device\n",
+                                func);
+                return -EINVAL;
+        }
+        return 1;
+}
+
+/*
+ * non-error returns are a promise to giveback() the urb later
+ * we drop ownership so next owner (or urb unlink) can get it
+ */
+int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
+{
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        unsigned long flags;
+        int ret = 0;
+        unsigned int slot_id, ep_index;
+
+        if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, true, __func__) <= 0)
+                return -EINVAL;
+
+        slot_id = urb->dev->slot_id;
+        ep_index = xhci_get_endpoint_index(&urb->ep->desc);
+
+        spin_lock_irqsave(&xhci->lock, flags);
+        if (!xhci->devs || !xhci->devs[slot_id]) {
+                if (!in_interrupt())
+                        dev_warn(&urb->dev->dev, "WARN: urb submitted for dev with no Slot ID\n");
+                ret = -EINVAL;
+                goto exit;
+        }
+        if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+                if (!in_interrupt())
+                        xhci_dbg(xhci, "urb submitted during PCI suspend\n");
+                ret = -ESHUTDOWN;
+                goto exit;
+        }
+        if (usb_endpoint_xfer_control(&urb->ep->desc))
+                ret = xhci_queue_ctrl_tx(xhci, mem_flags, urb,
+                                slot_id, ep_index);
+        else if (usb_endpoint_xfer_bulk(&urb->ep->desc))
+                ret = xhci_queue_bulk_tx(xhci, mem_flags, urb,
+                                slot_id, ep_index);
+        else
+                ret = -EINVAL;
+exit:
+        spin_unlock_irqrestore(&xhci->lock, flags);
+        return ret;
+}
+
+/*
+ * Remove the URB's TD from the endpoint ring.  This may cause the HC to stop
+ * USB transfers, potentially stopping in the middle of a TRB buffer.  The HC
+ * should pick up where it left off in the TD, unless a Set Transfer Ring
+ * Dequeue Pointer is issued.
+ *
+ * The TRBs that make up the buffers for the canceled URB will be "removed" from
+ * the ring.  Since the ring is a contiguous structure, they can't be physically
+ * removed.  Instead, there are two options:
+ *
+ *  1) If the HC is in the middle of processing the URB to be canceled, we
+ *     simply move the ring's dequeue pointer past those TRBs using the Set
+ *     Transfer Ring Dequeue Pointer command.  This will be the common case,
+ *     when drivers timeout on the last submitted URB and attempt to cancel.
+ *
+ *  2) If the HC is in the middle of a different TD, we turn the TRBs into a
+ *     series of 1-TRB transfer no-op TDs.  (No-ops shouldn't be chained.)  The
+ *     HC will need to invalidate the any TRBs it has cached after the stop
+ *     endpoint command, as noted in the xHCI 0.95 errata.
+ *
+ *  3) The TD may have completed by the time the Stop Endpoint Command
+ *     completes, so software needs to handle that case too.
+ *
+ * This function should protect against the TD enqueueing code ringing the
+ * doorbell while this code is waiting for a Stop Endpoint command to complete.
+ * It also needs to account for multiple cancellations on happening at the same
+ * time for the same endpoint.
+ *
+ * Note that this function can be called in any context, or so says
+ * usb_hcd_unlink_urb()
+ */
+int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+{
+        unsigned long flags;
+        int ret;
+        struct xhci_hcd *xhci;
+        struct xhci_td *td;
+        unsigned int ep_index;
+        struct xhci_ring *ep_ring;
+
+        xhci = hcd_to_xhci(hcd);
+        spin_lock_irqsave(&xhci->lock, flags);
+        /* Make sure the URB hasn't completed or been unlinked already */
+        ret = usb_hcd_check_unlink_urb(hcd, urb, status);
+        if (ret || !urb->hcpriv)
+                goto done;
+
+        xhci_dbg(xhci, "Cancel URB %p\n", urb);
+        ep_index = xhci_get_endpoint_index(&urb->ep->desc);
+        ep_ring = xhci->devs[urb->dev->slot_id]->ep_rings[ep_index];
+        td = (struct xhci_td *) urb->hcpriv;
+
+        ep_ring->cancels_pending++;
+        list_add_tail(&td->cancelled_td_list, &ep_ring->cancelled_td_list);
+        /* Queue a stop endpoint command, but only if this is
+         * the first cancellation to be handled.
+         */
+        if (ep_ring->cancels_pending == 1) {
+                xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index);
+                xhci_ring_cmd_db(xhci);
+        }
+done:
+        spin_unlock_irqrestore(&xhci->lock, flags);
+        return ret;
+}
+
+/* Drop an endpoint from a new bandwidth configuration for this device.
+ * Only one call to this function is allowed per endpoint before
+ * check_bandwidth() or reset_bandwidth() must be called.
+ * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
+ * add the endpoint to the schedule with possibly new parameters denoted by a
+ * different endpoint descriptor in usb_host_endpoint.
+ * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
+ * not allowed.
+ *
+ * The USB core will not allow URBs to be queued to an endpoint that is being
+ * disabled, so there's no need for mutual exclusion to protect
+ * the xhci->devs[slot_id] structure.
+ */
+int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
+                struct usb_host_endpoint *ep)
+{
+        struct xhci_hcd *xhci;
+        struct xhci_device_control *in_ctx;
+        unsigned int last_ctx;
+        unsigned int ep_index;
+        struct xhci_ep_ctx *ep_ctx;
+        u32 drop_flag;
+        u32 new_add_flags, new_drop_flags, new_slot_info;
+        int ret;
+
+        ret = xhci_check_args(hcd, udev, ep, 1, __func__);
+        if (ret <= 0)
+                return ret;
+        xhci = hcd_to_xhci(hcd);
+        xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
+
+        drop_flag = xhci_get_endpoint_flag(&ep->desc);
+        if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
+                xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
+                                __func__, drop_flag);
+                return 0;
+        }
+
+        if (!xhci->devs || !xhci->devs[udev->slot_id]) {
+                xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
+                                __func__);
+                return -EINVAL;
+        }
+
+        in_ctx = xhci->devs[udev->slot_id]->in_ctx;
+        ep_index = xhci_get_endpoint_index(&ep->desc);
+        ep_ctx = &xhci->devs[udev->slot_id]->out_ctx->ep[ep_index];
+        /* If the HC already knows the endpoint is disabled,
+         * or the HCD has noted it is disabled, ignore this request
+         */
+        if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED ||
+                        in_ctx->drop_flags & xhci_get_endpoint_flag(&ep->desc)) {
+                xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
+                                __func__, ep);
+                return 0;
+        }
+
+        in_ctx->drop_flags |= drop_flag;
+        new_drop_flags = in_ctx->drop_flags;
+
+        in_ctx->add_flags = ~drop_flag;
+        new_add_flags = in_ctx->add_flags;
+
+        last_ctx = xhci_last_valid_endpoint(in_ctx->add_flags);
+        /* Update the last valid endpoint context, if we deleted the last one */
+        if ((in_ctx->slot.dev_info & LAST_CTX_MASK) > LAST_CTX(last_ctx)) {
+                in_ctx->slot.dev_info &= ~LAST_CTX_MASK;
+                in_ctx->slot.dev_info |= LAST_CTX(last_ctx);
+        }
+        new_slot_info = in_ctx->slot.dev_info;
+
+        xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
+
+        xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
+                        (unsigned int) ep->desc.bEndpointAddress,
+                        udev->slot_id,
+                        (unsigned int) new_drop_flags,
+                        (unsigned int) new_add_flags,
+                        (unsigned int) new_slot_info);
+        return 0;
+}
+
+/* Add an endpoint to a new possible bandwidth configuration for this device.
+ * Only one call to this function is allowed per endpoint before
+ * check_bandwidth() or reset_bandwidth() must be called.
+ * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
+ * add the endpoint to the schedule with possibly new parameters denoted by a
+ * different endpoint descriptor in usb_host_endpoint.
+ * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
+ * not allowed.
+ *
+ * The USB core will not allow URBs to be queued to an endpoint until the
+ * configuration or alt setting is installed in the device, so there's no need
+ * for mutual exclusion to protect the xhci->devs[slot_id] structure.
+ */
+int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
+                struct usb_host_endpoint *ep)
+{
+        struct xhci_hcd *xhci;
+        struct xhci_device_control *in_ctx;
+        unsigned int ep_index;
+        struct xhci_ep_ctx *ep_ctx;
+        u32 added_ctxs;
+        unsigned int last_ctx;
+        u32 new_add_flags, new_drop_flags, new_slot_info;
+        int ret = 0;
+
+        ret = xhci_check_args(hcd, udev, ep, 1, __func__);
+        if (ret <= 0)
+                return ret;
+        xhci = hcd_to_xhci(hcd);
+
+        added_ctxs = xhci_get_endpoint_flag(&ep->desc);
+        last_ctx = xhci_last_valid_endpoint(added_ctxs);
+        if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
+                /* FIXME when we have to issue an evaluate endpoint command to
+                 * deal with ep0 max packet size changing once we get the
+                 * descriptors
+                 */
+                xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
+                                __func__, added_ctxs);
+                return 0;
+        }
+
+        if (!xhci->devs || !xhci->devs[udev->slot_id]) {
+                xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
+                                __func__);
+                return -EINVAL;
+        }
+
+        in_ctx = xhci->devs[udev->slot_id]->in_ctx;
+        ep_index = xhci_get_endpoint_index(&ep->desc);
+        ep_ctx = &xhci->devs[udev->slot_id]->out_ctx->ep[ep_index];
+        /* If the HCD has already noted the endpoint is enabled,
+         * ignore this request.
+         */
+        if (in_ctx->add_flags & xhci_get_endpoint_flag(&ep->desc)) {
+                xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
+                                __func__, ep);
+                return 0;
+        }
+
+        /*
+         * Configuration and alternate setting changes must be done in
+         * process context, not interrupt context (or so documenation
+         * for usb_set_interface() and usb_set_configuration() claim).
+         */
+        if (xhci_endpoint_init(xhci, xhci->devs[udev->slot_id],
+                                udev, ep, GFP_KERNEL) < 0) {
+                dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
+                                __func__, ep->desc.bEndpointAddress);
+                return -ENOMEM;
+        }
+
+        in_ctx->add_flags |= added_ctxs;
+        new_add_flags = in_ctx->add_flags;
+
+        /* If xhci_endpoint_disable() was called for this endpoint, but the
+         * xHC hasn't been notified yet through the check_bandwidth() call,
+         * this re-adds a new state for the endpoint from the new endpoint
+         * descriptors.  We must drop and re-add this endpoint, so we leave the
+         * drop flags alone.
+         */
+        new_drop_flags = in_ctx->drop_flags;
+
+        /* Update the last valid endpoint context, if we just added one past */
+        if ((in_ctx->slot.dev_info & LAST_CTX_MASK) < LAST_CTX(last_ctx)) {
+                in_ctx->slot.dev_info &= ~LAST_CTX_MASK;
+                in_ctx->slot.dev_info |= LAST_CTX(last_ctx);
+        }
+        new_slot_info = in_ctx->slot.dev_info;
+
+        xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
+                        (unsigned int) ep->desc.bEndpointAddress,
+                        udev->slot_id,
+                        (unsigned int) new_drop_flags,
+                        (unsigned int) new_add_flags,
+                        (unsigned int) new_slot_info);
+        return 0;
+}
+
+static void xhci_zero_in_ctx(struct xhci_virt_device *virt_dev)
+{
+        struct xhci_ep_ctx *ep_ctx;
+        int i;
+
+        /* When a device's add flag and drop flag are zero, any subsequent
+         * configure endpoint command will leave that endpoint's state
+         * untouched.  Make sure we don't leave any old state in the input
+         * endpoint contexts.
+         */
+        virt_dev->in_ctx->drop_flags = 0;
+        virt_dev->in_ctx->add_flags = 0;
+        virt_dev->in_ctx->slot.dev_info &= ~LAST_CTX_MASK;
+        /* Endpoint 0 is always valid */
+        virt_dev->in_ctx->slot.dev_info |= LAST_CTX(1);
+        for (i = 1; i < 31; ++i) {
+                ep_ctx = &virt_dev->in_ctx->ep[i];
+                ep_ctx->ep_info = 0;
+                ep_ctx->ep_info2 = 0;
+                ep_ctx->deq[0] = 0;
+                ep_ctx->deq[1] = 0;
+                ep_ctx->tx_info = 0;
+        }
+}
+
+/* Called after one or more calls to xhci_add_endpoint() or
+ * xhci_drop_endpoint().  If this call fails, the USB core is expected
+ * to call xhci_reset_bandwidth().
+ *
+ * Since we are in the middle of changing either configuration or
+ * installing a new alt setting, the USB core won't allow URBs to be
+ * enqueued for any endpoint on the old config or interface.  Nothing
+ * else should be touching the xhci->devs[slot_id] structure, so we
+ * don't need to take the xhci->lock for manipulating that.
+ */
+int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
+{
+        int i;
+        int ret = 0;
+        int timeleft;
+        unsigned long flags;
+        struct xhci_hcd *xhci;
+        struct xhci_virt_device *virt_dev;
+
+        ret = xhci_check_args(hcd, udev, NULL, 0, __func__);
+        if (ret <= 0)
+                return ret;
+        xhci = hcd_to_xhci(hcd);
+
+        if (!udev->slot_id || !xhci->devs || !xhci->devs[udev->slot_id]) {
+                xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
+                                __func__);
+                return -EINVAL;
+        }
+        xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
+        virt_dev = xhci->devs[udev->slot_id];
+
+        /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
+        virt_dev->in_ctx->add_flags |= SLOT_FLAG;
+        virt_dev->in_ctx->add_flags &= ~EP0_FLAG;
+        virt_dev->in_ctx->drop_flags &= ~SLOT_FLAG;
+        virt_dev->in_ctx->drop_flags &= ~EP0_FLAG;
+        xhci_dbg(xhci, "New Input Control Context:\n");
+        xhci_dbg_ctx(xhci, virt_dev->in_ctx, virt_dev->in_ctx_dma,
+                        LAST_CTX_TO_EP_NUM(virt_dev->in_ctx->slot.dev_info));
+
+        spin_lock_irqsave(&xhci->lock, flags);
+        ret = xhci_queue_configure_endpoint(xhci, virt_dev->in_ctx_dma,
+                        udev->slot_id);
+        if (ret < 0) {
+                spin_unlock_irqrestore(&xhci->lock, flags);
+                xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
+                return -ENOMEM;
+        }
+        xhci_ring_cmd_db(xhci);
+        spin_unlock_irqrestore(&xhci->lock, flags);
+
+        /* Wait for the configure endpoint command to complete */
+        timeleft = wait_for_completion_interruptible_timeout(
+                        &virt_dev->cmd_completion,
+                        USB_CTRL_SET_TIMEOUT);
+        if (timeleft <= 0) {
+                xhci_warn(xhci, "%s while waiting for configure endpoint command\n",
+                                timeleft == 0 ? "Timeout" : "Signal");
+                /* FIXME cancel the configure endpoint command */
+                return -ETIME;
+        }
+
+        switch (virt_dev->cmd_status) {
+        case COMP_ENOMEM:
+                dev_warn(&udev->dev, "Not enough host controller resources "
+                                "for new device state.\n");
+                ret = -ENOMEM;
+                /* FIXME: can we allocate more resources for the HC? */
+                break;
+        case COMP_BW_ERR:
+                dev_warn(&udev->dev, "Not enough bandwidth "
+                                "for new device state.\n");
+                ret = -ENOSPC;
+                /* FIXME: can we go back to the old state? */
+                break;
+        case COMP_TRB_ERR:
+                /* the HCD set up something wrong */
+                dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, add flag = 1, "
+                                "and endpoint is not disabled.\n");
+                ret = -EINVAL;
+                break;
+        case COMP_SUCCESS:
+                dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
+                break;
+        default:
+                xhci_err(xhci, "ERROR: unexpected command completion "
+                                "code 0x%x.\n", virt_dev->cmd_status);
+                ret = -EINVAL;
+                break;
+        }
+        if (ret) {
+                /* Callee should call reset_bandwidth() */
+                return ret;
+        }
+
+        xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
+        xhci_dbg_ctx(xhci, virt_dev->out_ctx, virt_dev->out_ctx_dma,
+                        LAST_CTX_TO_EP_NUM(virt_dev->in_ctx->slot.dev_info));
+
+        xhci_zero_in_ctx(virt_dev);
+        /* Free any old rings */
+        for (i = 1; i < 31; ++i) {
+                if (virt_dev->new_ep_rings[i]) {
+                        xhci_ring_free(xhci, virt_dev->ep_rings[i]);
+                        virt_dev->ep_rings[i] = virt_dev->new_ep_rings[i];
+                        virt_dev->new_ep_rings[i] = NULL;
+                }
+        }
+
+        return ret;
+}
+
+void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
+{
+        struct xhci_hcd *xhci;
+        struct xhci_virt_device *virt_dev;
+        int i, ret;
+
+        ret = xhci_check_args(hcd, udev, NULL, 0, __func__);
+        if (ret <= 0)
+                return;
+        xhci = hcd_to_xhci(hcd);
+
+        if (!xhci->devs || !xhci->devs[udev->slot_id]) {
+                xhci_warn(xhci, "xHCI %s called with unaddressed device\n",
+                                __func__);
+                return;
+        }
+        xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
+        virt_dev = xhci->devs[udev->slot_id];
+        /* Free any rings allocated for added endpoints */
+        for (i = 0; i < 31; ++i) {
+                if (virt_dev->new_ep_rings[i]) {
+                        xhci_ring_free(xhci, virt_dev->new_ep_rings[i]);
+                        virt_dev->new_ep_rings[i] = NULL;
+                }
+        }
+        xhci_zero_in_ctx(virt_dev);
+}
+
+/*
+ * At this point, the struct usb_device is about to go away, the device has
+ * disconnected, and all traffic has been stopped and the endpoints have been
+ * disabled.  Free any HC data structures associated with that device.
+ */
+void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
+{
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        unsigned long flags;
+
+        if (udev->slot_id == 0)
+                return;
+
+        spin_lock_irqsave(&xhci->lock, flags);
+        if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
+                spin_unlock_irqrestore(&xhci->lock, flags);
+                xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
+                return;
+        }
+        xhci_ring_cmd_db(xhci);
+        spin_unlock_irqrestore(&xhci->lock, flags);
+        /*
+         * Event command completion handler will free any data structures
+         * associated with the slot.  XXX Can free sleep?
+         */
+}
+
+/*
+ * Returns 0 if the xHC ran out of device slots, the Enable Slot command
+ * timed out, or allocating memory failed.  Returns 1 on success.
+ */
+int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
+{
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        unsigned long flags;
+        int timeleft;
+        int ret;
+
+        spin_lock_irqsave(&xhci->lock, flags);
+        ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
+        if (ret) {
+                spin_unlock_irqrestore(&xhci->lock, flags);
+                xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
+                return 0;
+        }
+        xhci_ring_cmd_db(xhci);
+        spin_unlock_irqrestore(&xhci->lock, flags);
+
+        /* XXX: how much time for xHC slot assignment? */
+        timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
+                        USB_CTRL_SET_TIMEOUT);
+        if (timeleft <= 0) {
+                xhci_warn(xhci, "%s while waiting for a slot\n",
+                                timeleft == 0 ? "Timeout" : "Signal");
+                /* FIXME cancel the enable slot request */
+                return 0;
+        }
+
+        if (!xhci->slot_id) {
+                xhci_err(xhci, "Error while assigning device slot ID\n");
+                return 0;
+        }
+        /* xhci_alloc_virt_device() does not touch rings; no need to lock */
+        if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_KERNEL)) {
+                /* Disable slot, if we can do it without mem alloc */
+                xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
+                spin_lock_irqsave(&xhci->lock, flags);
+                if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
+                        xhci_ring_cmd_db(xhci);
+                spin_unlock_irqrestore(&xhci->lock, flags);
+                return 0;
+        }
+        udev->slot_id = xhci->slot_id;
+        /* Is this a LS or FS device under a HS hub? */
+        /* Hub or peripherial? */
+        return 1;
+}
+
+/*
+ * Issue an Address Device command (which will issue a SetAddress request to
+ * the device).
+ * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
+ * we should only issue and wait on one address command at the same time.
+ *
+ * We add one to the device address issued by the hardware because the USB core
+ * uses address 1 for the root hubs (even though they're not really devices).
+ */
+int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
+{
+        unsigned long flags;
+        int timeleft;
+        struct xhci_virt_device *virt_dev;
+        int ret = 0;
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        u32 temp;
+
+        if (!udev->slot_id) {
+                xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
+                return -EINVAL;
+        }
+
+        virt_dev = xhci->devs[udev->slot_id];
+
+        /* If this is a Set Address to an unconfigured device, setup ep 0 */
+        if (!udev->config)
+                xhci_setup_addressable_virt_dev(xhci, udev);
+        /* Otherwise, assume the core has the device configured how it wants */
+
+        spin_lock_irqsave(&xhci->lock, flags);
+        ret = xhci_queue_address_device(xhci, virt_dev->in_ctx_dma,
+                        udev->slot_id);
+        if (ret) {
+                spin_unlock_irqrestore(&xhci->lock, flags);
+                xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
+                return ret;
+        }
+        xhci_ring_cmd_db(xhci);
+        spin_unlock_irqrestore(&xhci->lock, flags);
+
+        /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
+        timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
+                        USB_CTRL_SET_TIMEOUT);
+        /* FIXME: From section 4.3.4: "Software shall be responsible for timing
+         * the SetAddress() "recovery interval" required by USB and aborting the
+         * command on a timeout.
+         */
+        if (timeleft <= 0) {
+                xhci_warn(xhci, "%s while waiting for a slot\n",
+                                timeleft == 0 ? "Timeout" : "Signal");
+                /* FIXME cancel the address device command */
+                return -ETIME;
+        }
+
+        switch (virt_dev->cmd_status) {
+        case COMP_CTX_STATE:
+        case COMP_EBADSLT:
+                xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
+                                udev->slot_id);
+                ret = -EINVAL;
+                break;
+        case COMP_TX_ERR:
+                dev_warn(&udev->dev, "Device not responding to set address.\n");
+                ret = -EPROTO;
+                break;
+        case COMP_SUCCESS:
+                xhci_dbg(xhci, "Successful Address Device command\n");
+                break;
+        default:
+                xhci_err(xhci, "ERROR: unexpected command completion "
+                                "code 0x%x.\n", virt_dev->cmd_status);
+                ret = -EINVAL;
+                break;
+        }
+        if (ret) {
+                return ret;
+        }
+        temp = xhci_readl(xhci, &xhci->op_regs->dcbaa_ptr[0]);
+        xhci_dbg(xhci, "Op regs DCBAA ptr[0] = %#08x\n", temp);
+        temp = xhci_readl(xhci, &xhci->op_regs->dcbaa_ptr[1]);
+        xhci_dbg(xhci, "Op regs DCBAA ptr[1] = %#08x\n", temp);
+        xhci_dbg(xhci, "Slot ID %d dcbaa entry[0] @%p = %#08x\n",
+                        udev->slot_id,
+                        &xhci->dcbaa->dev_context_ptrs[2*udev->slot_id],
+                        xhci->dcbaa->dev_context_ptrs[2*udev->slot_id]);
+        xhci_dbg(xhci, "Slot ID %d dcbaa entry[1] @%p = %#08x\n",
+                        udev->slot_id,
+                        &xhci->dcbaa->dev_context_ptrs[2*udev->slot_id+1],
+                        xhci->dcbaa->dev_context_ptrs[2*udev->slot_id+1]);
+        xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
+                        (unsigned long long)virt_dev->out_ctx_dma);
+        xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
+        xhci_dbg_ctx(xhci, virt_dev->in_ctx, virt_dev->in_ctx_dma, 2);
+        xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
+        xhci_dbg_ctx(xhci, virt_dev->out_ctx, virt_dev->out_ctx_dma, 2);
+        /*
+         * USB core uses address 1 for the roothubs, so we add one to the
+         * address given back to us by the HC.
+         */
+        udev->devnum = (virt_dev->out_ctx->slot.dev_state & DEV_ADDR_MASK) + 1;
+        /* Zero the input context control for later use */
+        virt_dev->in_ctx->add_flags = 0;
+        virt_dev->in_ctx->drop_flags = 0;
+        /* Mirror flags in the output context for future ep enable/disable */
+        virt_dev->out_ctx->add_flags = SLOT_FLAG | EP0_FLAG;
+        virt_dev->out_ctx->drop_flags = 0;
+
+        xhci_dbg(xhci, "Device address = %d\n", udev->devnum);
+        /* XXX Meh, not sure if anyone else but choose_address uses this. */
+        set_bit(udev->devnum, udev->bus->devmap.devicemap);
+
+        return 0;
+}
+
+int xhci_get_frame(struct usb_hcd *hcd)
+{
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        /* EHCI mods by the periodic size.  Why? */
+        return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
+}
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_LICENSE("GPL");
+
+static int __init xhci_hcd_init(void)
+{
+#ifdef CONFIG_PCI
+        int retval = 0;
+
+        retval = xhci_register_pci();
+
+        if (retval < 0) {
+                printk(KERN_DEBUG "Problem registering PCI driver.");
+                return retval;
+        }
+#endif
+        /*
+         * Check the compiler generated sizes of structures that must be laid
+         * out in specific ways for hardware access.
+         */
+        BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
+        BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
+        BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
+        /* xhci_device_control has eight fields, and also
+         * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
+         */
+        BUILD_BUG_ON(sizeof(struct xhci_device_control) != (8+8+8*31)*32/8);
+        BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
+        BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
+        BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
+        BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
+        BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
+        /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
+        BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
+        BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
+        return 0;
+}
+module_init(xhci_hcd_init);
+
+static void __exit xhci_hcd_cleanup(void)
+{
+#ifdef CONFIG_PCI
+        xhci_unregister_pci();
+#endif
+}
+module_exit(xhci_hcd_cleanup);
diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
new file mode 100644
index 000000000000..eac5b53aa9e7
--- /dev/null
+++ b/drivers/usb/host/xhci-hub.c
@@ -0,0 +1,308 @@
+/*
+ * xHCI host controller driver
+ *
+ * Copyright (C) 2008 Intel Corp.
+ *
+ * Author: Sarah Sharp
+ * Some code borrowed from the Linux EHCI driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <asm/unaligned.h>
+
+#include "xhci.h"
+
+static void xhci_hub_descriptor(struct xhci_hcd *xhci,
+                struct usb_hub_descriptor *desc)
+{
+        int ports;
+        u16 temp;
+
+        ports = HCS_MAX_PORTS(xhci->hcs_params1);
+
+        /* USB 3.0 hubs have a different descriptor, but we fake this for now */
+        desc->bDescriptorType = 0x29;
+        desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
+        desc->bHubContrCurrent = 0;
+
+        desc->bNbrPorts = ports;
+        temp = 1 + (ports / 8);
+        desc->bDescLength = 7 + 2 * temp;
+
+        /* Why does core/hcd.h define bitmap?  It's just confusing. */
+        memset(&desc->DeviceRemovable[0], 0, temp);
+        memset(&desc->DeviceRemovable[temp], 0xff, temp);
+
+        /* Ugh, these should be #defines, FIXME */
+        /* Using table 11-13 in USB 2.0 spec. */
+        temp = 0;
+        /* Bits 1:0 - support port power switching, or power always on */
+        if (HCC_PPC(xhci->hcc_params))
+                temp |= 0x0001;
+        else
+                temp |= 0x0002;
+        /* Bit  2 - root hubs are not part of a compound device */
+        /* Bits 4:3 - individual port over current protection */
+        temp |= 0x0008;
+        /* Bits 6:5 - no TTs in root ports */
+        /* Bit  7 - no port indicators */
+        desc->wHubCharacteristics = (__force __u16) cpu_to_le16(temp);
+}
+
+static unsigned int xhci_port_speed(unsigned int port_status)
+{
+        if (DEV_LOWSPEED(port_status))
+                return 1 << USB_PORT_FEAT_LOWSPEED;
+        if (DEV_HIGHSPEED(port_status))
+                return 1 << USB_PORT_FEAT_HIGHSPEED;
+        if (DEV_SUPERSPEED(port_status))
+                return 1 << USB_PORT_FEAT_SUPERSPEED;
+        /*
+         * FIXME: Yes, we should check for full speed, but the core uses that as
+         * a default in portspeed() in usb/core/hub.c (which is the only place
+         * USB_PORT_FEAT_*SPEED is used).
+         */
+        return 0;
+}
+
+/*
+ * These bits are Read Only (RO) and should be saved and written to the
+ * registers: 0, 3, 10:13, 30
+ * connect status, over-current status, port speed, and device removable.
+ * connect status and port speed are also sticky - meaning they're in
+ * the AUX well and they aren't changed by a hot, warm, or cold reset.
+ */
+#define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
+/*
+ * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
+ * bits 5:8, 9, 14:15, 25:27
+ * link state, port power, port indicator state, "wake on" enable state
+ */
+#define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
+/*
+ * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
+ * bit 4 (port reset)
+ */
+#define XHCI_PORT_RW1S  ((1<<4))
+/*
+ * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
+ * bits 1, 17, 18, 19, 20, 21, 22, 23
+ * port enable/disable, and
+ * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
+ * over-current, reset, link state, and L1 change
+ */
+#define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
+/*
+ * Bit 16 is RW, and writing a '1' to it causes the link state control to be
+ * latched in
+ */
+#define XHCI_PORT_RW    ((1<<16))
+/*
+ * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
+ * bits 2, 24, 28:31
+ */
+#define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
+
+/*
+ * Given a port state, this function returns a value that would result in the
+ * port being in the same state, if the value was written to the port status
+ * control register.
+ * Save Read Only (RO) bits and save read/write bits where
+ * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
+ * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
+ */
+static u32 xhci_port_state_to_neutral(u32 state)
+{
+        /* Save read-only status and port state */
+        return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
+}
+
+int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
+                u16 wIndex, char *buf, u16 wLength)
+{
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        int ports;
+        unsigned long flags;
+        u32 temp, status;
+        int retval = 0;
+        u32 __iomem *addr;
+        char *port_change_bit;
+
+        ports = HCS_MAX_PORTS(xhci->hcs_params1);
+
+        spin_lock_irqsave(&xhci->lock, flags);
+        switch (typeReq) {
+        case GetHubStatus:
+                /* No power source, over-current reported per port */
+                memset(buf, 0, 4);
+                break;
+        case GetHubDescriptor:
+                xhci_hub_descriptor(xhci, (struct usb_hub_descriptor *) buf);
+                break;
+        case GetPortStatus:
+                if (!wIndex || wIndex > ports)
+                        goto error;
+                wIndex--;
+                status = 0;
+                addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff);
+                temp = xhci_readl(xhci, addr);
+                xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n", wIndex, temp);
+
+                /* wPortChange bits */
+                if (temp & PORT_CSC)
+                        status |= 1 << USB_PORT_FEAT_C_CONNECTION;
+                if (temp & PORT_PEC)
+                        status |= 1 << USB_PORT_FEAT_C_ENABLE;
+                if ((temp & PORT_OCC))
+                        status |= 1 << USB_PORT_FEAT_C_OVER_CURRENT;
+                /*
+                 * FIXME ignoring suspend, reset, and USB 2.1/3.0 specific
+                 * changes
+                 */
+                if (temp & PORT_CONNECT) {
+                        status |= 1 << USB_PORT_FEAT_CONNECTION;
+                        status |= xhci_port_speed(temp);
+                }
+                if (temp & PORT_PE)
+                        status |= 1 << USB_PORT_FEAT_ENABLE;
+                if (temp & PORT_OC)
+                        status |= 1 << USB_PORT_FEAT_OVER_CURRENT;
+                if (temp & PORT_RESET)
+                        status |= 1 << USB_PORT_FEAT_RESET;
+                if (temp & PORT_POWER)
+                        status |= 1 << USB_PORT_FEAT_POWER;
+                xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
+                put_unaligned(cpu_to_le32(status), (__le32 *) buf);
+                break;
+        case SetPortFeature:
+                wIndex &= 0xff;
+                if (!wIndex || wIndex > ports)
+                        goto error;
+                wIndex--;
+                addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(wIndex & 0xff);
+                temp = xhci_readl(xhci, addr);
+                temp = xhci_port_state_to_neutral(temp);
+                switch (wValue) {
+                case USB_PORT_FEAT_POWER:
+                        /*
+                         * Turn on ports, even if there isn't per-port switching.
+                         * HC will report connect events even before this is set.
+                         * However, khubd will ignore the roothub events until
+                         * the roothub is registered.
+                         */
+                        xhci_writel(xhci, temp | PORT_POWER, addr);
+
+                        temp = xhci_readl(xhci, addr);
+                        xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
+                        break;
+                case USB_PORT_FEAT_RESET:
+                        temp = (temp | PORT_RESET);
+                        xhci_writel(xhci, temp, addr);
+
+                        temp = xhci_readl(xhci, addr);
+                        xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
+                        break;
+                default:
+                        goto error;
+                }
+                temp = xhci_readl(xhci, addr); /* unblock any posted writes */
+                break;
+        case ClearPortFeature:
+                if (!wIndex || wIndex > ports)
+                        goto error;
+                wIndex--;
+                addr = &xhci->op_regs->port_status_base +
+                        NUM_PORT_REGS*(wIndex & 0xff);
+                temp = xhci_readl(xhci, addr);
+                temp = xhci_port_state_to_neutral(temp);
+                switch (wValue) {
+                case USB_PORT_FEAT_C_RESET:
+                        status = PORT_RC;
+                        port_change_bit = "reset";
+                        break;
+                case USB_PORT_FEAT_C_CONNECTION:
+                        status = PORT_CSC;
+                        port_change_bit = "connect";
+                        break;
+                case USB_PORT_FEAT_C_OVER_CURRENT:
+                        status = PORT_OCC;
+                        port_change_bit = "over-current";
+                        break;
+                default:
+                        goto error;
+                }
+                /* Change bits are all write 1 to clear */
+                xhci_writel(xhci, temp | status, addr);
+                temp = xhci_readl(xhci, addr);
+                xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
+                                port_change_bit, wIndex, temp);
+                temp = xhci_readl(xhci, addr); /* unblock any posted writes */
+                break;
+        default:
+error:
+                /* "stall" on error */
+                retval = -EPIPE;
+        }
+        spin_unlock_irqrestore(&xhci->lock, flags);
+        return retval;
+}
+
+/*
+ * Returns 0 if the status hasn't changed, or the number of bytes in buf.
+ * Ports are 0-indexed from the HCD point of view,
+ * and 1-indexed from the USB core pointer of view.
+ * xHCI instances can have up to 127 ports, so FIXME if you see more than 15.
+ *
+ * Note that the status change bits will be cleared as soon as a port status
+ * change event is generated, so we use the saved status from that event.
+ */
+int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
+{
+        unsigned long flags;
+        u32 temp, status;
+        int i, retval;
+        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        int ports;
+        u32 __iomem *addr;
+
+        ports = HCS_MAX_PORTS(xhci->hcs_params1);
+
+        /* Initial status is no changes */
+        buf[0] = 0;
+        status = 0;
+        if (ports > 7) {
+                buf[1] = 0;
+                retval = 2;
+        } else {
+                retval = 1;
+        }
+
+        spin_lock_irqsave(&xhci->lock, flags);
+        /* For each port, did anything change?  If so, set that bit in buf. */
+        for (i = 0; i < ports; i++) {
+                addr = &xhci->op_regs->port_status_base +
+                        NUM_PORT_REGS*i;
+                temp = xhci_readl(xhci, addr);
+                if (temp & (PORT_CSC | PORT_PEC | PORT_OCC)) {
+                        if (i < 7)
+                                buf[0] |= 1 << (i + 1);
+                        else
+                                buf[1] |= 1 << (i - 7);
+                        status = 1;
+                }
+        }
+        spin_unlock_irqrestore(&xhci->lock, flags);
+        return status ? retval : 0;
+}
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
new file mode 100644
index 000000000000..c8a72de1c508
--- /dev/null
+++ b/drivers/usb/host/xhci-mem.c
@@ -0,0 +1,769 @@
+/*
+ * xHCI host controller driver
+ *
+ * Copyright (C) 2008 Intel Corp.
+ *
+ * Author: Sarah Sharp
+ * Some code borrowed from the Linux EHCI driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/usb.h>
+#include <linux/pci.h>
+#include <linux/dmapool.h>
+
+#include "xhci.h"
+
+/*
+ * Allocates a generic ring segment from the ring pool, sets the dma address,
+ * initializes the segment to zero, and sets the private next pointer to NULL.
+ *
+ * Section 4.11.1.1:
+ * "All components of all Command and Transfer TRBs shall be initialized to '0'"
+ */
+static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
+{
+        struct xhci_segment *seg;
+        dma_addr_t      dma;
+
+        seg = kzalloc(sizeof *seg, flags);
+        if (!seg)
+                return 0;
+        xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
+
+        seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
+        if (!seg->trbs) {
+                kfree(seg);
+                return 0;
+        }
+        xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
+                        seg->trbs, (unsigned long long)dma);
+
+        memset(seg->trbs, 0, SEGMENT_SIZE);
+        seg->dma = dma;
+        seg->next = NULL;
+
+        return seg;
+}
+
+static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
+{
+        if (!seg)
+                return;
+        if (seg->trbs) {
+                xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
+                                seg->trbs, (unsigned long long)seg->dma);
+                dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
+                seg->trbs = NULL;
+        }
+        xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
+        kfree(seg);
+}
+
+/*
+ * Make the prev segment point to the next segment.
+ *
+ * Change the last TRB in the prev segment to be a Link TRB which points to the
+ * DMA address of the next segment.  The caller needs to set any Link TRB
+ * related flags, such as End TRB, Toggle Cycle, and no snoop.
+ */
+static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
+                struct xhci_segment *next, bool link_trbs)
+{
+        u32 val;
+
+        if (!prev || !next)
+                return;
+        prev->next = next;
+        if (link_trbs) {
+                prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr[0] = next->dma;
+
+                /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
+                val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
+                val &= ~TRB_TYPE_BITMASK;
+                val |= TRB_TYPE(TRB_LINK);
+                prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
+        }
+        xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
+                        (unsigned long long)prev->dma,
+                        (unsigned long long)next->dma);
+}
+
+/* XXX: Do we need the hcd structure in all these functions? */
+void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
+{
+        struct xhci_segment *seg;
+        struct xhci_segment *first_seg;
+
+        if (!ring || !ring->first_seg)
+                return;
+        first_seg = ring->first_seg;
+        seg = first_seg->next;
+        xhci_dbg(xhci, "Freeing ring at %p\n", ring);
+        while (seg != first_seg) {
+                struct xhci_segment *next = seg->next;
+                xhci_segment_free(xhci, seg);
+                seg = next;
+        }
+        xhci_segment_free(xhci, first_seg);
+        ring->first_seg = NULL;
+        kfree(ring);
+}
+
+/**
+ * Create a new ring with zero or more segments.
+ *
+ * Link each segment together into a ring.
+ * Set the end flag and the cycle toggle bit on the last segment.
+ * See section 4.9.1 and figures 15 and 16.
+ */
+static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
+                unsigned int num_segs, bool link_trbs, gfp_t flags)
+{
+        struct xhci_ring        *ring;
+        struct xhci_segment     *prev;
+
+        ring = kzalloc(sizeof *(ring), flags);
+        xhci_dbg(xhci, "Allocating ring at %p\n", ring);
+        if (!ring)
+                return 0;
+
+        INIT_LIST_HEAD(&ring->td_list);
+        INIT_LIST_HEAD(&ring->cancelled_td_list);
+        if (num_segs == 0)
+                return ring;
+
+        ring->first_seg = xhci_segment_alloc(xhci, flags);
+        if (!ring->first_seg)
+                goto fail;
+        num_segs--;
+
+        prev = ring->first_seg;
+        while (num_segs > 0) {
+                struct xhci_segment     *next;
+
+                next = xhci_segment_alloc(xhci, flags);
+                if (!next)
+                        goto fail;
+                xhci_link_segments(xhci, prev, next, link_trbs);
+
+                prev = next;
+                num_segs--;
+        }
+        xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
+
+        if (link_trbs) {
+                /* See section 4.9.2.1 and 6.4.4.1 */
+                prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE);
+                xhci_dbg(xhci, "Wrote link toggle flag to"
+                                " segment %p (virtual), 0x%llx (DMA)\n",
+                                prev, (unsigned long long)prev->dma);
+        }
+        /* The ring is empty, so the enqueue pointer == dequeue pointer */
+        ring->enqueue = ring->first_seg->trbs;
+        ring->enq_seg = ring->first_seg;
+        ring->dequeue = ring->enqueue;
+        ring->deq_seg = ring->first_seg;
+        /* The ring is initialized to 0. The producer must write 1 to the cycle
+         * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
+         * compare CCS to the cycle bit to check ownership, so CCS = 1.
+         */
+        ring->cycle_state = 1;
+
+        return ring;
+
+fail:
+        xhci_ring_free(xhci, ring);
+        return 0;
+}
+
+/* All the xhci_tds in the ring's TD list should be freed at this point */
+void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
+{
+        struct xhci_virt_device *dev;
+        int i;
+
+        /* Slot ID 0 is reserved */
+        if (slot_id == 0 || !xhci->devs[slot_id])
+                return;
+
+        dev = xhci->devs[slot_id];
+        xhci->dcbaa->dev_context_ptrs[2*slot_id] = 0;
+        xhci->dcbaa->dev_context_ptrs[2*slot_id + 1] = 0;
+        if (!dev)
+                return;
+
+        for (i = 0; i < 31; ++i)
+                if (dev->ep_rings[i])
+                        xhci_ring_free(xhci, dev->ep_rings[i]);
+
+        if (dev->in_ctx)
+                dma_pool_free(xhci->device_pool,
+                                dev->in_ctx, dev->in_ctx_dma);
+        if (dev->out_ctx)
+                dma_pool_free(xhci->device_pool,
+                                dev->out_ctx, dev->out_ctx_dma);
+        kfree(xhci->devs[slot_id]);
+        xhci->devs[slot_id] = 0;
+}
+
+int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
+                struct usb_device *udev, gfp_t flags)
+{
+        dma_addr_t      dma;
+        struct xhci_virt_device *dev;
+
+        /* Slot ID 0 is reserved */
+        if (slot_id == 0 || xhci->devs[slot_id]) {
+                xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
+                return 0;
+        }
+
+        xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
+        if (!xhci->devs[slot_id])
+                return 0;
+        dev = xhci->devs[slot_id];
+
+        /* Allocate the (output) device context that will be used in the HC */
+        dev->out_ctx = dma_pool_alloc(xhci->device_pool, flags, &dma);
+        if (!dev->out_ctx)
+                goto fail;
+        dev->out_ctx_dma = dma;
+        xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
+                        (unsigned long long)dma);
+        memset(dev->out_ctx, 0, sizeof(*dev->out_ctx));
+
+        /* Allocate the (input) device context for address device command */
+        dev->in_ctx = dma_pool_alloc(xhci->device_pool, flags, &dma);
+        if (!dev->in_ctx)
+                goto fail;
+        dev->in_ctx_dma = dma;
+        xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
+                        (unsigned long long)dma);
+        memset(dev->in_ctx, 0, sizeof(*dev->in_ctx));
+
+        /* Allocate endpoint 0 ring */
+        dev->ep_rings[0] = xhci_ring_alloc(xhci, 1, true, flags);
+        if (!dev->ep_rings[0])
+                goto fail;
+
+        init_completion(&dev->cmd_completion);
+
+        /*
+         * Point to output device context in dcbaa; skip the output control
+         * context, which is eight 32 bit fields (or 32 bytes long)
+         */
+        xhci->dcbaa->dev_context_ptrs[2*slot_id] =
+                (u32) dev->out_ctx_dma + (32);
+        xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
+                        slot_id,
+                        &xhci->dcbaa->dev_context_ptrs[2*slot_id],
+                        (unsigned long long)dev->out_ctx_dma);
+        xhci->dcbaa->dev_context_ptrs[2*slot_id + 1] = 0;
+
+        return 1;
+fail:
+        xhci_free_virt_device(xhci, slot_id);
+        return 0;
+}
+
+/* Setup an xHCI virtual device for a Set Address command */
+int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
+{
+        struct xhci_virt_device *dev;
+        struct xhci_ep_ctx      *ep0_ctx;
+        struct usb_device       *top_dev;
+
+        dev = xhci->devs[udev->slot_id];
+        /* Slot ID 0 is reserved */
+        if (udev->slot_id == 0 || !dev) {
+                xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
+                                udev->slot_id);
+                return -EINVAL;
+        }
+        ep0_ctx = &dev->in_ctx->ep[0];
+
+        /* 2) New slot context and endpoint 0 context are valid*/
+        dev->in_ctx->add_flags = SLOT_FLAG | EP0_FLAG;
+
+        /* 3) Only the control endpoint is valid - one endpoint context */
+        dev->in_ctx->slot.dev_info |= LAST_CTX(1);
+
+        switch (udev->speed) {
+        case USB_SPEED_SUPER:
+                dev->in_ctx->slot.dev_info |= (u32) udev->route;
+                dev->in_ctx->slot.dev_info |= (u32) SLOT_SPEED_SS;
+                break;
+        case USB_SPEED_HIGH:
+                dev->in_ctx->slot.dev_info |= (u32) SLOT_SPEED_HS;
+                break;
+        case USB_SPEED_FULL:
+                dev->in_ctx->slot.dev_info |= (u32) SLOT_SPEED_FS;
+                break;
+        case USB_SPEED_LOW:
+                dev->in_ctx->slot.dev_info |= (u32) SLOT_SPEED_LS;
+                break;
+        case USB_SPEED_VARIABLE:
+                xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
+                return -EINVAL;
+                break;
+        default:
+                /* Speed was set earlier, this shouldn't happen. */
+                BUG();
+        }
+        /* Find the root hub port this device is under */
+        for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
+                        top_dev = top_dev->parent)
+                /* Found device below root hub */;
+        dev->in_ctx->slot.dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum);
+        xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum);
+
+        /* Is this a LS/FS device under a HS hub? */
+        /*
+         * FIXME: I don't think this is right, where does the TT info for the
+         * roothub or parent hub come from?
+         */
+        if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) &&
+                        udev->tt) {
+                dev->in_ctx->slot.tt_info = udev->tt->hub->slot_id;
+                dev->in_ctx->slot.tt_info |= udev->ttport << 8;
+        }
+        xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
+        xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
+
+        /* Step 4 - ring already allocated */
+        /* Step 5 */
+        ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP);
+        /*
+         * See section 4.3 bullet 6:
+         * The default Max Packet size for ep0 is "8 bytes for a USB2
+         * LS/FS/HS device or 512 bytes for a USB3 SS device"
+         * XXX: Not sure about wireless USB devices.
+         */
+        if (udev->speed == USB_SPEED_SUPER)
+                ep0_ctx->ep_info2 |= MAX_PACKET(512);
+        else
+                ep0_ctx->ep_info2 |= MAX_PACKET(8);
+        /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
+        ep0_ctx->ep_info2 |= MAX_BURST(0);
+        ep0_ctx->ep_info2 |= ERROR_COUNT(3);
+
+        ep0_ctx->deq[0] =
+                dev->ep_rings[0]->first_seg->dma;
+        ep0_ctx->deq[0] |= dev->ep_rings[0]->cycle_state;
+        ep0_ctx->deq[1] = 0;
+
+        /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
+
+        return 0;
+}
+
+/* Return the polling or NAK interval.
+ *
+ * The polling interval is expressed in "microframes".  If xHCI's Interval field
+ * is set to N, it will service the endpoint every 2^(Interval)*125us.
+ *
+ * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
+ * is set to 0.
+ */
+static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
+                struct usb_host_endpoint *ep)
+{
+        unsigned int interval = 0;
+
+        switch (udev->speed) {
+        case USB_SPEED_HIGH:
+                /* Max NAK rate */
+                if (usb_endpoint_xfer_control(&ep->desc) ||
+                                usb_endpoint_xfer_bulk(&ep->desc))
+                        interval = ep->desc.bInterval;
+                /* Fall through - SS and HS isoc/int have same decoding */
+        case USB_SPEED_SUPER:
+                if (usb_endpoint_xfer_int(&ep->desc) ||
+                                usb_endpoint_xfer_isoc(&ep->desc)) {
+                        if (ep->desc.bInterval == 0)
+                                interval = 0;
+                        else
+                                interval = ep->desc.bInterval - 1;
+                        if (interval > 15)
+                                interval = 15;
+                        if (interval != ep->desc.bInterval + 1)
+                                dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n",
+                                                ep->desc.bEndpointAddress, 1 << interval);
+                }
+                break;
+        /* Convert bInterval (in 1-255 frames) to microframes and round down to
+         * nearest power of 2.
+         */
+        case USB_SPEED_FULL:
+        case USB_SPEED_LOW:
+                if (usb_endpoint_xfer_int(&ep->desc) ||
+                                usb_endpoint_xfer_isoc(&ep->desc)) {
+                        interval = fls(8*ep->desc.bInterval) - 1;
+                        if (interval > 10)
+                                interval = 10;
+                        if (interval < 3)
+                                interval = 3;
+                        if ((1 << interval) != 8*ep->desc.bInterval)
+                                dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n",
+                                                ep->desc.bEndpointAddress, 1 << interval);
+                }
+                break;
+        default:
+                BUG();
+        }
+        return EP_INTERVAL(interval);
+}
+
+static inline u32 xhci_get_endpoint_type(struct usb_device *udev,
+                struct usb_host_endpoint *ep)
+{
+        int in;
+        u32 type;
+
+        in = usb_endpoint_dir_in(&ep->desc);
+        if (usb_endpoint_xfer_control(&ep->desc)) {
+                type = EP_TYPE(CTRL_EP);
+        } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
+                if (in)
+                        type = EP_TYPE(BULK_IN_EP);
+                else
+                        type = EP_TYPE(BULK_OUT_EP);
+        } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
+                if (in)
+                        type = EP_TYPE(ISOC_IN_EP);
+                else
+                        type = EP_TYPE(ISOC_OUT_EP);
+        } else if (usb_endpoint_xfer_int(&ep->desc)) {
+                if (in)
+                        type = EP_TYPE(INT_IN_EP);
+                else
+                        type = EP_TYPE(INT_OUT_EP);
+        } else {
+                BUG();
+        }
+        return type;
+}
+
+int xhci_endpoint_init(struct xhci_hcd *xhci,
+                struct xhci_virt_device *virt_dev,
+                struct usb_device *udev,
+                struct usb_host_endpoint *ep,
+                gfp_t mem_flags)
+{
+        unsigned int ep_index;
+        struct xhci_ep_ctx *ep_ctx;
+        struct xhci_ring *ep_ring;
+        unsigned int max_packet;
+        unsigned int max_burst;
+
+        ep_index = xhci_get_endpoint_index(&ep->desc);
+        ep_ctx = &virt_dev->in_ctx->ep[ep_index];
+
+        /* Set up the endpoint ring */
+        virt_dev->new_ep_rings[ep_index] = xhci_ring_alloc(xhci, 1, true, mem_flags);
+        if (!virt_dev->new_ep_rings[ep_index])
+                return -ENOMEM;
+        ep_ring = virt_dev->new_ep_rings[ep_index];
+        ep_ctx->deq[0] = ep_ring->first_seg->dma | ep_ring->cycle_state;
+        ep_ctx->deq[1] = 0;
+
+        ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep);
+
+        /* FIXME dig Mult and streams info out of ep companion desc */
+
+        /* Allow 3 retries for everything but isoc */
+        if (!usb_endpoint_xfer_isoc(&ep->desc))
+                ep_ctx->ep_info2 = ERROR_COUNT(3);
+        else
+                ep_ctx->ep_info2 = ERROR_COUNT(0);
+
+        ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep);
+
+        /* Set the max packet size and max burst */
+        switch (udev->speed) {
+        case USB_SPEED_SUPER:
+                max_packet = ep->desc.wMaxPacketSize;
+                ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
+                /* dig out max burst from ep companion desc */
+                max_packet = ep->ss_ep_comp->desc.bMaxBurst;
+                ep_ctx->ep_info2 |= MAX_BURST(max_packet);
+                break;
+        case USB_SPEED_HIGH:
+                /* bits 11:12 specify the number of additional transaction
+                 * opportunities per microframe (USB 2.0, section 9.6.6)
+                 */
+                if (usb_endpoint_xfer_isoc(&ep->desc) ||
+                                usb_endpoint_xfer_int(&ep->desc)) {
+                        max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;
+                        ep_ctx->ep_info2 |= MAX_BURST(max_burst);
+                }
+                /* Fall through */
+        case USB_SPEED_FULL:
+        case USB_SPEED_LOW:
+                max_packet = ep->desc.wMaxPacketSize & 0x3ff;
+                ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
+                break;
+        default:
+                BUG();
+        }
+        /* FIXME Debug endpoint context */
+        return 0;
+}
+
+void xhci_endpoint_zero(struct xhci_hcd *xhci,
+                struct xhci_virt_device *virt_dev,
+                struct usb_host_endpoint *ep)
+{
+        unsigned int ep_index;
+        struct xhci_ep_ctx *ep_ctx;
+
+        ep_index = xhci_get_endpoint_index(&ep->desc);
+        ep_ctx = &virt_dev->in_ctx->ep[ep_index];
+
+        ep_ctx->ep_info = 0;
+        ep_ctx->ep_info2 = 0;
+        ep_ctx->deq[0] = 0;
+        ep_ctx->deq[1] = 0;
+        ep_ctx->tx_info = 0;
+        /* Don't free the endpoint ring until the set interface or configuration
+         * request succeeds.
+         */
+}
+
+void xhci_mem_cleanup(struct xhci_hcd *xhci)
+{
+        struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
+        int size;
+        int i;
+
+        /* Free the Event Ring Segment Table and the actual Event Ring */
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_base[0]);
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_base[1]);
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_dequeue[0]);
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_dequeue[1]);
+        size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
+        if (xhci->erst.entries)
+                pci_free_consistent(pdev, size,
+                                xhci->erst.entries, xhci->erst.erst_dma_addr);
+        xhci->erst.entries = NULL;
+        xhci_dbg(xhci, "Freed ERST\n");
+        if (xhci->event_ring)
+                xhci_ring_free(xhci, xhci->event_ring);
+        xhci->event_ring = NULL;
+        xhci_dbg(xhci, "Freed event ring\n");
+
+        xhci_writel(xhci, 0, &xhci->op_regs->cmd_ring[0]);
+        xhci_writel(xhci, 0, &xhci->op_regs->cmd_ring[1]);
+        if (xhci->cmd_ring)
+                xhci_ring_free(xhci, xhci->cmd_ring);
+        xhci->cmd_ring = NULL;
+        xhci_dbg(xhci, "Freed command ring\n");
+
+        for (i = 1; i < MAX_HC_SLOTS; ++i)
+                xhci_free_virt_device(xhci, i);
+
+        if (xhci->segment_pool)
+                dma_pool_destroy(xhci->segment_pool);
+        xhci->segment_pool = NULL;
+        xhci_dbg(xhci, "Freed segment pool\n");
+
+        if (xhci->device_pool)
+                dma_pool_destroy(xhci->device_pool);
+        xhci->device_pool = NULL;
+        xhci_dbg(xhci, "Freed device context pool\n");
+
+        xhci_writel(xhci, 0, &xhci->op_regs->dcbaa_ptr[0]);
+        xhci_writel(xhci, 0, &xhci->op_regs->dcbaa_ptr[1]);
+        if (xhci->dcbaa)
+                pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
+                                xhci->dcbaa, xhci->dcbaa->dma);
+        xhci->dcbaa = NULL;
+
+        xhci->page_size = 0;
+        xhci->page_shift = 0;
+}
+
+int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
+{
+        dma_addr_t      dma;
+        struct device   *dev = xhci_to_hcd(xhci)->self.controller;
+        unsigned int    val, val2;
+        struct xhci_segment     *seg;
+        u32 page_size;
+        int i;
+
+        page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
+        xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
+        for (i = 0; i < 16; i++) {
+                if ((0x1 & page_size) != 0)
+                        break;
+                page_size = page_size >> 1;
+        }
+        if (i < 16)
+                xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
+        else
+                xhci_warn(xhci, "WARN: no supported page size\n");
+        /* Use 4K pages, since that's common and the minimum the HC supports */
+        xhci->page_shift = 12;
+        xhci->page_size = 1 << xhci->page_shift;
+        xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
+
+        /*
+         * Program the Number of Device Slots Enabled field in the CONFIG
+         * register with the max value of slots the HC can handle.
+         */
+        val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
+        xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
+                        (unsigned int) val);
+        val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
+        val |= (val2 & ~HCS_SLOTS_MASK);
+        xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
+                        (unsigned int) val);
+        xhci_writel(xhci, val, &xhci->op_regs->config_reg);
+
+        /*
+         * Section 5.4.8 - doorbell array must be
+         * "physically contiguous and 64-byte (cache line) aligned".
+         */
+        xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
+                        sizeof(*xhci->dcbaa), &dma);
+        if (!xhci->dcbaa)
+                goto fail;
+        memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
+        xhci->dcbaa->dma = dma;
+        xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
+                        (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
+        xhci_writel(xhci, dma, &xhci->op_regs->dcbaa_ptr[0]);
+        xhci_writel(xhci, (u32) 0, &xhci->op_regs->dcbaa_ptr[1]);
+
+        /*
+         * Initialize the ring segment pool.  The ring must be a contiguous
+         * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
+         * however, the command ring segment needs 64-byte aligned segments,
+         * so we pick the greater alignment need.
+         */
+        xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
+                        SEGMENT_SIZE, 64, xhci->page_size);
+        /* See Table 46 and Note on Figure 55 */
+        /* FIXME support 64-byte contexts */
+        xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
+                        sizeof(struct xhci_device_control),
+                        64, xhci->page_size);
+        if (!xhci->segment_pool || !xhci->device_pool)
+                goto fail;
+
+        /* Set up the command ring to have one segments for now. */
+        xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
+        if (!xhci->cmd_ring)
+                goto fail;
+        xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
+        xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
+                        (unsigned long long)xhci->cmd_ring->first_seg->dma);
+
+        /* Set the address in the Command Ring Control register */
+        val = xhci_readl(xhci, &xhci->op_regs->cmd_ring[0]);
+        val = (val & ~CMD_RING_ADDR_MASK) |
+                (xhci->cmd_ring->first_seg->dma & CMD_RING_ADDR_MASK) |
+                xhci->cmd_ring->cycle_state;
+        xhci_dbg(xhci, "// Setting command ring address low bits to 0x%x\n", val);
+        xhci_writel(xhci, val, &xhci->op_regs->cmd_ring[0]);
+        xhci_dbg(xhci, "// Setting command ring address high bits to 0x0\n");
+        xhci_writel(xhci, (u32) 0, &xhci->op_regs->cmd_ring[1]);
+        xhci_dbg_cmd_ptrs(xhci);
+
+        val = xhci_readl(xhci, &xhci->cap_regs->db_off);
+        val &= DBOFF_MASK;
+        xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
+                        " from cap regs base addr\n", val);
+        xhci->dba = (void *) xhci->cap_regs + val;
+        xhci_dbg_regs(xhci);
+        xhci_print_run_regs(xhci);
+        /* Set ir_set to interrupt register set 0 */
+        xhci->ir_set = (void *) xhci->run_regs->ir_set;
+
+        /*
+         * Event ring setup: Allocate a normal ring, but also setup
+         * the event ring segment table (ERST).  Section 4.9.3.
+         */
+        xhci_dbg(xhci, "// Allocating event ring\n");
+        xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
+        if (!xhci->event_ring)
+                goto fail;
+
+        xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
+                        sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
+        if (!xhci->erst.entries)
+                goto fail;
+        xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
+                        (unsigned long long)dma);
+
+        memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
+        xhci->erst.num_entries = ERST_NUM_SEGS;
+        xhci->erst.erst_dma_addr = dma;
+        xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
+                        xhci->erst.num_entries,
+                        xhci->erst.entries,
+                        (unsigned long long)xhci->erst.erst_dma_addr);
+
+        /* set ring base address and size for each segment table entry */
+        for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
+                struct xhci_erst_entry *entry = &xhci->erst.entries[val];
+                entry->seg_addr[0] = seg->dma;
+                entry->seg_addr[1] = 0;
+                entry->seg_size = TRBS_PER_SEGMENT;
+                entry->rsvd = 0;
+                seg = seg->next;
+        }
+
+        /* set ERST count with the number of entries in the segment table */
+        val = xhci_readl(xhci, &xhci->ir_set->erst_size);
+        val &= ERST_SIZE_MASK;
+        val |= ERST_NUM_SEGS;
+        xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
+                        val);
+        xhci_writel(xhci, val, &xhci->ir_set->erst_size);
+
+        xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
+        /* set the segment table base address */
+        xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
+                        (unsigned long long)xhci->erst.erst_dma_addr);
+        val = xhci_readl(xhci, &xhci->ir_set->erst_base[0]);
+        val &= ERST_PTR_MASK;
+        val |= (xhci->erst.erst_dma_addr & ~ERST_PTR_MASK);
+        xhci_writel(xhci, val, &xhci->ir_set->erst_base[0]);
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_base[1]);
+
+        /* Set the event ring dequeue address */
+        xhci_set_hc_event_deq(xhci);
+        xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
+        xhci_print_ir_set(xhci, xhci->ir_set, 0);
+
+        /*
+         * XXX: Might need to set the Interrupter Moderation Register to
+         * something other than the default (~1ms minimum between interrupts).
+         * See section 5.5.1.2.
+         */
+        init_completion(&xhci->addr_dev);
+        for (i = 0; i < MAX_HC_SLOTS; ++i)
+                xhci->devs[i] = 0;
+
+        return 0;
+fail:
+        xhci_warn(xhci, "Couldn't initialize memory\n");
+        xhci_mem_cleanup(xhci);
+        return -ENOMEM;
+}
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
new file mode 100644
index 000000000000..1462709e26c0
--- /dev/null
+++ b/drivers/usb/host/xhci-pci.c
@@ -0,0 +1,166 @@
+/*
+ * xHCI host controller driver PCI Bus Glue.
+ *
+ * Copyright (C) 2008 Intel Corp.
+ *
+ * Author: Sarah Sharp
+ * Some code borrowed from the Linux EHCI driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/pci.h>
+
+#include "xhci.h"
+
+static const char hcd_name[] = "xhci_hcd";
+
+/* called after powerup, by probe or system-pm "wakeup" */
+static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
+{
+        /*
+         * TODO: Implement finding debug ports later.
+         * TODO: see if there are any quirks that need to be added to handle
+         * new extended capabilities.
+         */
+
+        /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
+        if (!pci_set_mwi(pdev))
+                xhci_dbg(xhci, "MWI active\n");
+
+        xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
+        return 0;
+}
+
+/* called during probe() after chip reset completes */
+static int xhci_pci_setup(struct usb_hcd *hcd)
+{
+        struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
+        struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
+        int                     retval;
+
+        xhci->cap_regs = hcd->regs;
+        xhci->op_regs = hcd->regs +
+                HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
+        xhci->run_regs = hcd->regs +
+                (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
+        /* Cache read-only capability registers */
+        xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
+        xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
+        xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
+        xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
+        xhci_print_registers(xhci);
+
+        /* Make sure the HC is halted. */
+        retval = xhci_halt(xhci);
+        if (retval)
+                return retval;
+
+        xhci_dbg(xhci, "Resetting HCD\n");
+        /* Reset the internal HC memory state and registers. */
+        retval = xhci_reset(xhci);
+        if (retval)
+                return retval;
+        xhci_dbg(xhci, "Reset complete\n");
+
+        xhci_dbg(xhci, "Calling HCD init\n");
+        /* Initialize HCD and host controller data structures. */
+        retval = xhci_init(hcd);
+        if (retval)
+                return retval;
+        xhci_dbg(xhci, "Called HCD init\n");
+
+        pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
+        xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
+
+        /* Find any debug ports */
+        return xhci_pci_reinit(xhci, pdev);
+}
+
+static const struct hc_driver xhci_pci_hc_driver = {
+        .description =          hcd_name,
+        .product_desc =         "xHCI Host Controller",
+        .hcd_priv_size =        sizeof(struct xhci_hcd),
+
+        /*
+         * generic hardware linkage
+         */
+        .irq =                  xhci_irq,
+        .flags =                HCD_MEMORY | HCD_USB3,
+
+        /*
+         * basic lifecycle operations
+         */
+        .reset =                xhci_pci_setup,
+        .start =                xhci_run,
+        /* suspend and resume implemented later */
+        .stop =                 xhci_stop,
+        .shutdown =             xhci_shutdown,
+
+        /*
+         * managing i/o requests and associated device resources
+         */
+        .urb_enqueue =          xhci_urb_enqueue,
+        .urb_dequeue =          xhci_urb_dequeue,
+        .alloc_dev =            xhci_alloc_dev,
+        .free_dev =             xhci_free_dev,
+        .add_endpoint =         xhci_add_endpoint,
+        .drop_endpoint =        xhci_drop_endpoint,
+        .check_bandwidth =      xhci_check_bandwidth,
+        .reset_bandwidth =      xhci_reset_bandwidth,
+        .address_device =       xhci_address_device,
+
+        /*
+         * scheduling support
+         */
+        .get_frame_number =     xhci_get_frame,
+
+        /* Root hub support */
+        .hub_control =          xhci_hub_control,
+        .hub_status_data =      xhci_hub_status_data,
+};
+
+/*-------------------------------------------------------------------------*/
+
+/* PCI driver selection metadata; PCI hotplugging uses this */
+static const struct pci_device_id pci_ids[] = { {
+        /* handle any USB 3.0 xHCI controller */
+        PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
+        .driver_data =  (unsigned long) &xhci_pci_hc_driver,
+        },
+        { /* end: all zeroes */ }
+};
+MODULE_DEVICE_TABLE(pci, pci_ids);
+
+/* pci driver glue; this is a "new style" PCI driver module */
+static struct pci_driver xhci_pci_driver = {
+        .name =         (char *) hcd_name,
+        .id_table =     pci_ids,
+
+        .probe =        usb_hcd_pci_probe,
+        .remove =       usb_hcd_pci_remove,
+        /* suspend and resume implemented later */
+
+        .shutdown =     usb_hcd_pci_shutdown,
+};
+
+int xhci_register_pci()
+{
+        return pci_register_driver(&xhci_pci_driver);
+}
+
+void xhci_unregister_pci()
+{
+        pci_unregister_driver(&xhci_pci_driver);
+}
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
new file mode 100644
index 000000000000..02d81985c454
--- /dev/null
+++ b/drivers/usb/host/xhci-ring.c
@@ -0,0 +1,1648 @@
+/*
+ * xHCI host controller driver
+ *
+ * Copyright (C) 2008 Intel Corp.
+ *
+ * Author: Sarah Sharp
+ * Some code borrowed from the Linux EHCI driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Ring initialization rules:
+ * 1. Each segment is initialized to zero, except for link TRBs.
+ * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
+ *    Consumer Cycle State (CCS), depending on ring function.
+ * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
+ *
+ * Ring behavior rules:
+ * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
+ *    least one free TRB in the ring.  This is useful if you want to turn that
+ *    into a link TRB and expand the ring.
+ * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
+ *    link TRB, then load the pointer with the address in the link TRB.  If the
+ *    link TRB had its toggle bit set, you may need to update the ring cycle
+ *    state (see cycle bit rules).  You may have to do this multiple times
+ *    until you reach a non-link TRB.
+ * 3. A ring is full if enqueue++ (for the definition of increment above)
+ *    equals the dequeue pointer.
+ *
+ * Cycle bit rules:
+ * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
+ *    in a link TRB, it must toggle the ring cycle state.
+ * 2. When a producer increments an enqueue pointer and encounters a toggle bit
+ *    in a link TRB, it must toggle the ring cycle state.
+ *
+ * Producer rules:
+ * 1. Check if ring is full before you enqueue.
+ * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
+ *    Update enqueue pointer between each write (which may update the ring
+ *    cycle state).
+ * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
+ *    and endpoint rings.  If HC is the producer for the event ring,
+ *    and it generates an interrupt according to interrupt modulation rules.
+ *
+ * Consumer rules:
+ * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
+ *    the TRB is owned by the consumer.
+ * 2. Update dequeue pointer (which may update the ring cycle state) and
+ *    continue processing TRBs until you reach a TRB which is not owned by you.
+ * 3. Notify the producer.  SW is the consumer for the event ring, and it
+ *   updates event ring dequeue pointer.  HC is the consumer for the command and
+ *   endpoint rings; it generates events on the event ring for these.
+ */
+
+#include <linux/scatterlist.h>
+#include "xhci.h"
+
+/*
+ * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
+ * address of the TRB.
+ */
+dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
+                union xhci_trb *trb)
+{
+        unsigned long segment_offset;
+
+        if (!seg || !trb || trb < seg->trbs)
+                return 0;
+        /* offset in TRBs */
+        segment_offset = trb - seg->trbs;
+        if (segment_offset > TRBS_PER_SEGMENT)
+                return 0;
+        return seg->dma + (segment_offset * sizeof(*trb));
+}
+
+/* Does this link TRB point to the first segment in a ring,
+ * or was the previous TRB the last TRB on the last segment in the ERST?
+ */
+static inline bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
+                struct xhci_segment *seg, union xhci_trb *trb)
+{
+        if (ring == xhci->event_ring)
+                return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
+                        (seg->next == xhci->event_ring->first_seg);
+        else
+                return trb->link.control & LINK_TOGGLE;
+}
+
+/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
+ * segment?  I.e. would the updated event TRB pointer step off the end of the
+ * event seg?
+ */
+static inline int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
+                struct xhci_segment *seg, union xhci_trb *trb)
+{
+        if (ring == xhci->event_ring)
+                return trb == &seg->trbs[TRBS_PER_SEGMENT];
+        else
+                return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
+}
+
+/* Updates trb to point to the next TRB in the ring, and updates seg if the next
+ * TRB is in a new segment.  This does not skip over link TRBs, and it does not
+ * effect the ring dequeue or enqueue pointers.
+ */
+static void next_trb(struct xhci_hcd *xhci,
+                struct xhci_ring *ring,
+                struct xhci_segment **seg,
+                union xhci_trb **trb)
+{
+        if (last_trb(xhci, ring, *seg, *trb)) {
+                *seg = (*seg)->next;
+                *trb = ((*seg)->trbs);
+        } else {
+                *trb = (*trb)++;
+        }
+}
+
+/*
+ * See Cycle bit rules. SW is the consumer for the event ring only.
+ * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
+ */
+static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
+{
+        union xhci_trb *next = ++(ring->dequeue);
+
+        ring->deq_updates++;
+        /* Update the dequeue pointer further if that was a link TRB or we're at
+         * the end of an event ring segment (which doesn't have link TRBS)
+         */
+        while (last_trb(xhci, ring, ring->deq_seg, next)) {
+                if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
+                        ring->cycle_state = (ring->cycle_state ? 0 : 1);
+                        if (!in_interrupt())
+                                xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
+                                                ring,
+                                                (unsigned int) ring->cycle_state);
+                }
+                ring->deq_seg = ring->deq_seg->next;
+                ring->dequeue = ring->deq_seg->trbs;
+                next = ring->dequeue;
+        }
+}
+
+/*
+ * See Cycle bit rules. SW is the consumer for the event ring only.
+ * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
+ *
+ * If we've just enqueued a TRB that is in the middle of a TD (meaning the
+ * chain bit is set), then set the chain bit in all the following link TRBs.
+ * If we've enqueued the last TRB in a TD, make sure the following link TRBs
+ * have their chain bit cleared (so that each Link TRB is a separate TD).
+ *
+ * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
+ * set, but other sections talk about dealing with the chain bit set.
+ * Assume section 6.4.4.1 is wrong, and the chain bit can be set in a Link TRB.
+ */
+static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
+{
+        u32 chain;
+        union xhci_trb *next;
+
+        chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
+        next = ++(ring->enqueue);
+
+        ring->enq_updates++;
+        /* Update the dequeue pointer further if that was a link TRB or we're at
+         * the end of an event ring segment (which doesn't have link TRBS)
+         */
+        while (last_trb(xhci, ring, ring->enq_seg, next)) {
+                if (!consumer) {
+                        if (ring != xhci->event_ring) {
+                                next->link.control &= ~TRB_CHAIN;
+                                next->link.control |= chain;
+                                /* Give this link TRB to the hardware */
+                                wmb();
+                                if (next->link.control & TRB_CYCLE)
+                                        next->link.control &= (u32) ~TRB_CYCLE;
+                                else
+                                        next->link.control |= (u32) TRB_CYCLE;
+                        }
+                        /* Toggle the cycle bit after the last ring segment. */
+                        if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
+                                ring->cycle_state = (ring->cycle_state ? 0 : 1);
+                                if (!in_interrupt())
+                                        xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
+                                                        ring,
+                                                        (unsigned int) ring->cycle_state);
+                        }
+                }
+                ring->enq_seg = ring->enq_seg->next;
+                ring->enqueue = ring->enq_seg->trbs;
+                next = ring->enqueue;
+        }
+}
+
+/*
+ * Check to see if there's room to enqueue num_trbs on the ring.  See rules
+ * above.
+ * FIXME: this would be simpler and faster if we just kept track of the number
+ * of free TRBs in a ring.
+ */
+static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
+                unsigned int num_trbs)
+{
+        int i;
+        union xhci_trb *enq = ring->enqueue;
+        struct xhci_segment *enq_seg = ring->enq_seg;
+
+        /* Check if ring is empty */
+        if (enq == ring->dequeue)
+                return 1;
+        /* Make sure there's an extra empty TRB available */
+        for (i = 0; i <= num_trbs; ++i) {
+                if (enq == ring->dequeue)
+                        return 0;
+                enq++;
+                while (last_trb(xhci, ring, enq_seg, enq)) {
+                        enq_seg = enq_seg->next;
+                        enq = enq_seg->trbs;
+                }
+        }
+        return 1;
+}
+
+void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
+{
+        u32 temp;
+        dma_addr_t deq;
+
+        deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
+                        xhci->event_ring->dequeue);
+        if (deq == 0 && !in_interrupt())
+                xhci_warn(xhci, "WARN something wrong with SW event ring "
+                                "dequeue ptr.\n");
+        /* Update HC event ring dequeue pointer */
+        temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
+        temp &= ERST_PTR_MASK;
+        if (!in_interrupt())
+                xhci_dbg(xhci, "// Write event ring dequeue pointer\n");
+        xhci_writel(xhci, 0, &xhci->ir_set->erst_dequeue[1]);
+        xhci_writel(xhci, (deq & ~ERST_PTR_MASK) | temp,
+                        &xhci->ir_set->erst_dequeue[0]);
+}
+
+/* Ring the host controller doorbell after placing a command on the ring */
+void xhci_ring_cmd_db(struct xhci_hcd *xhci)
+{
+        u32 temp;
+
+        xhci_dbg(xhci, "// Ding dong!\n");
+        temp = xhci_readl(xhci, &xhci->dba->doorbell[0]) & DB_MASK;
+        xhci_writel(xhci, temp | DB_TARGET_HOST, &xhci->dba->doorbell[0]);
+        /* Flush PCI posted writes */
+        xhci_readl(xhci, &xhci->dba->doorbell[0]);
+}
+
+static void ring_ep_doorbell(struct xhci_hcd *xhci,
+                unsigned int slot_id,
+                unsigned int ep_index)
+{
+        struct xhci_ring *ep_ring;
+        u32 field;
+        __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
+
+        ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
+        /* Don't ring the doorbell for this endpoint if there are pending
+         * cancellations because the we don't want to interrupt processing.
+         */
+        if (!ep_ring->cancels_pending && !(ep_ring->state & SET_DEQ_PENDING)) {
+                field = xhci_readl(xhci, db_addr) & DB_MASK;
+                xhci_writel(xhci, field | EPI_TO_DB(ep_index), db_addr);
+                /* Flush PCI posted writes - FIXME Matthew Wilcox says this
+                 * isn't time-critical and we shouldn't make the CPU wait for
+                 * the flush.
+                 */
+                xhci_readl(xhci, db_addr);
+        }
+}
+
+/*
+ * Find the segment that trb is in.  Start searching in start_seg.
+ * If we must move past a segment that has a link TRB with a toggle cycle state
+ * bit set, then we will toggle the value pointed at by cycle_state.
+ */
+static struct xhci_segment *find_trb_seg(
+                struct xhci_segment *start_seg,
+                union xhci_trb  *trb, int *cycle_state)
+{
+        struct xhci_segment *cur_seg = start_seg;
+        struct xhci_generic_trb *generic_trb;
+
+        while (cur_seg->trbs > trb ||
+                        &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
+                generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
+                if (TRB_TYPE(generic_trb->field[3]) == TRB_LINK &&
+                                (generic_trb->field[3] & LINK_TOGGLE))
+                        *cycle_state = ~(*cycle_state) & 0x1;
+                cur_seg = cur_seg->next;
+                if (cur_seg == start_seg)
+                        /* Looped over the entire list.  Oops! */
+                        return 0;
+        }
+        return cur_seg;
+}
+
+struct dequeue_state {
+        struct xhci_segment *new_deq_seg;
+        union xhci_trb *new_deq_ptr;
+        int new_cycle_state;
+};
+
+/*
+ * Move the xHC's endpoint ring dequeue pointer past cur_td.
+ * Record the new state of the xHC's endpoint ring dequeue segment,
+ * dequeue pointer, and new consumer cycle state in state.
+ * Update our internal representation of the ring's dequeue pointer.
+ *
+ * We do this in three jumps:
+ *  - First we update our new ring state to be the same as when the xHC stopped.
+ *  - Then we traverse the ring to find the segment that contains
+ *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
+ *    any link TRBs with the toggle cycle bit set.
+ *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
+ *    if we've moved it past a link TRB with the toggle cycle bit set.
+ */
+static void find_new_dequeue_state(struct xhci_hcd *xhci,
+                unsigned int slot_id, unsigned int ep_index,
+                struct xhci_td *cur_td, struct dequeue_state *state)
+{
+        struct xhci_virt_device *dev = xhci->devs[slot_id];
+        struct xhci_ring *ep_ring = dev->ep_rings[ep_index];
+        struct xhci_generic_trb *trb;
+
+        state->new_cycle_state = 0;
+        state->new_deq_seg = find_trb_seg(cur_td->start_seg,
+                        ep_ring->stopped_trb,
+                        &state->new_cycle_state);
+        if (!state->new_deq_seg)
+                BUG();
+        /* Dig out the cycle state saved by the xHC during the stop ep cmd */
+        state->new_cycle_state = 0x1 & dev->out_ctx->ep[ep_index].deq[0];
+
+        state->new_deq_ptr = cur_td->last_trb;
+        state->new_deq_seg = find_trb_seg(state->new_deq_seg,
+                        state->new_deq_ptr,
+                        &state->new_cycle_state);
+        if (!state->new_deq_seg)
+                BUG();
+
+        trb = &state->new_deq_ptr->generic;
+        if (TRB_TYPE(trb->field[3]) == TRB_LINK &&
+                                (trb->field[3] & LINK_TOGGLE))
+                state->new_cycle_state = ~(state->new_cycle_state) & 0x1;
+        next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
+
+        /* Don't update the ring cycle state for the producer (us). */
+        ep_ring->dequeue = state->new_deq_ptr;
+        ep_ring->deq_seg = state->new_deq_seg;
+}
+
+static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
+                struct xhci_td *cur_td)
+{
+        struct xhci_segment *cur_seg;
+        union xhci_trb *cur_trb;
+
+        for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
+                        true;
+                        next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
+                if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
+                                TRB_TYPE(TRB_LINK)) {
+                        /* Unchain any chained Link TRBs, but
+                         * leave the pointers intact.
+                         */
+                        cur_trb->generic.field[3] &= ~TRB_CHAIN;
+                        xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
+                        xhci_dbg(xhci, "Address = %p (0x%llx dma); "
+                                        "in seg %p (0x%llx dma)\n",
+                                        cur_trb,
+                                        (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
+                                        cur_seg,
+                                        (unsigned long long)cur_seg->dma);
+                } else {
+                        cur_trb->generic.field[0] = 0;
+                        cur_trb->generic.field[1] = 0;
+                        cur_trb->generic.field[2] = 0;
+                        /* Preserve only the cycle bit of this TRB */
+                        cur_trb->generic.field[3] &= TRB_CYCLE;
+                        cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
+                        xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
+                                        "in seg %p (0x%llx dma)\n",
+                                        cur_trb,
+                                        (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
+                                        cur_seg,
+                                        (unsigned long long)cur_seg->dma);
+                }
+                if (cur_trb == cur_td->last_trb)
+                        break;
+        }
+}
+
+static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
+                unsigned int ep_index, struct xhci_segment *deq_seg,
+                union xhci_trb *deq_ptr, u32 cycle_state);
+
+/*
+ * When we get a command completion for a Stop Endpoint Command, we need to
+ * unlink any cancelled TDs from the ring.  There are two ways to do that:
+ *
+ *  1. If the HW was in the middle of processing the TD that needs to be
+ *     cancelled, then we must move the ring's dequeue pointer past the last TRB
+ *     in the TD with a Set Dequeue Pointer Command.
+ *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
+ *     bit cleared) so that the HW will skip over them.
+ */
+static void handle_stopped_endpoint(struct xhci_hcd *xhci,
+                union xhci_trb *trb)
+{
+        unsigned int slot_id;
+        unsigned int ep_index;
+        struct xhci_ring *ep_ring;
+        struct list_head *entry;
+        struct xhci_td *cur_td = 0;
+        struct xhci_td *last_unlinked_td;
+
+        struct dequeue_state deq_state;
+#ifdef CONFIG_USB_HCD_STAT
+        ktime_t stop_time = ktime_get();
+#endif
+
+        memset(&deq_state, 0, sizeof(deq_state));
+        slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
+        ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
+        ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
+
+        if (list_empty(&ep_ring->cancelled_td_list))
+                return;
+
+        /* Fix up the ep ring first, so HW stops executing cancelled TDs.
+         * We have the xHCI lock, so nothing can modify this list until we drop
+         * it.  We're also in the event handler, so we can't get re-interrupted
+         * if another Stop Endpoint command completes
+         */
+        list_for_each(entry, &ep_ring->cancelled_td_list) {
+                cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
+                xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
+                                cur_td->first_trb,
+                                (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
+                /*
+                 * If we stopped on the TD we need to cancel, then we have to
+                 * move the xHC endpoint ring dequeue pointer past this TD.
+                 */
+                if (cur_td == ep_ring->stopped_td)
+                        find_new_dequeue_state(xhci, slot_id, ep_index, cur_td,
+                                        &deq_state);
+                else
+                        td_to_noop(xhci, ep_ring, cur_td);
+                /*
+                 * The event handler won't see a completion for this TD anymore,
+                 * so remove it from the endpoint ring's TD list.  Keep it in
+                 * the cancelled TD list for URB completion later.
+                 */
+                list_del(&cur_td->td_list);
+                ep_ring->cancels_pending--;
+        }
+        last_unlinked_td = cur_td;
+
+        /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
+        if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
+                xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
+                                "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
+                                deq_state.new_deq_seg,
+                                (unsigned long long)deq_state.new_deq_seg->dma,
+                                deq_state.new_deq_ptr,
+                                (unsigned long long)xhci_trb_virt_to_dma(deq_state.new_deq_seg, deq_state.new_deq_ptr),
+                                deq_state.new_cycle_state);
+                queue_set_tr_deq(xhci, slot_id, ep_index,
+                                deq_state.new_deq_seg,
+                                deq_state.new_deq_ptr,
+                                (u32) deq_state.new_cycle_state);
+                /* Stop the TD queueing code from ringing the doorbell until
+                 * this command completes.  The HC won't set the dequeue pointer
+                 * if the ring is running, and ringing the doorbell starts the
+                 * ring running.
+                 */
+                ep_ring->state |= SET_DEQ_PENDING;
+                xhci_ring_cmd_db(xhci);
+        } else {
+                /* Otherwise just ring the doorbell to restart the ring */
+                ring_ep_doorbell(xhci, slot_id, ep_index);
+        }
+
+        /*
+         * Drop the lock and complete the URBs in the cancelled TD list.
+         * New TDs to be cancelled might be added to the end of the list before
+         * we can complete all the URBs for the TDs we already unlinked.
+         * So stop when we've completed the URB for the last TD we unlinked.
+         */
+        do {
+                cur_td = list_entry(ep_ring->cancelled_td_list.next,
+                                struct xhci_td, cancelled_td_list);
+                list_del(&cur_td->cancelled_td_list);
+
+                /* Clean up the cancelled URB */
+#ifdef CONFIG_USB_HCD_STAT
+                hcd_stat_update(xhci->tp_stat, cur_td->urb->actual_length,
+                                ktime_sub(stop_time, cur_td->start_time));
+#endif
+                cur_td->urb->hcpriv = NULL;
+                usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), cur_td->urb);
+
+                xhci_dbg(xhci, "Giveback cancelled URB %p\n", cur_td->urb);
+                spin_unlock(&xhci->lock);
+                /* Doesn't matter what we pass for status, since the core will
+                 * just overwrite it (because the URB has been unlinked).
+                 */
+                usb_hcd_giveback_urb(xhci_to_hcd(xhci), cur_td->urb, 0);
+                kfree(cur_td);
+
+                spin_lock(&xhci->lock);
+        } while (cur_td != last_unlinked_td);
+
+        /* Return to the event handler with xhci->lock re-acquired */
+}
+
+/*
+ * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
+ * we need to clear the set deq pending flag in the endpoint ring state, so that
+ * the TD queueing code can ring the doorbell again.  We also need to ring the
+ * endpoint doorbell to restart the ring, but only if there aren't more
+ * cancellations pending.
+ */
+static void handle_set_deq_completion(struct xhci_hcd *xhci,
+                struct xhci_event_cmd *event,
+                union xhci_trb *trb)
+{
+        unsigned int slot_id;
+        unsigned int ep_index;
+        struct xhci_ring *ep_ring;
+        struct xhci_virt_device *dev;
+
+        slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
+        ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
+        dev = xhci->devs[slot_id];
+        ep_ring = dev->ep_rings[ep_index];
+
+        if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
+                unsigned int ep_state;
+                unsigned int slot_state;
+
+                switch (GET_COMP_CODE(event->status)) {
+                case COMP_TRB_ERR:
+                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
+                                        "of stream ID configuration\n");
+                        break;
+                case COMP_CTX_STATE:
+                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
+                                        "to incorrect slot or ep state.\n");
+                        ep_state = dev->out_ctx->ep[ep_index].ep_info;
+                        ep_state &= EP_STATE_MASK;
+                        slot_state = dev->out_ctx->slot.dev_state;
+                        slot_state = GET_SLOT_STATE(slot_state);
+                        xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
+                                        slot_state, ep_state);
+                        break;
+                case COMP_EBADSLT:
+                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
+                                        "slot %u was not enabled.\n", slot_id);
+                        break;
+                default:
+                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
+                                        "completion code of %u.\n",
+                                        GET_COMP_CODE(event->status));
+                        break;
+                }
+                /* OK what do we do now?  The endpoint state is hosed, and we
+                 * should never get to this point if the synchronization between
+                 * queueing, and endpoint state are correct.  This might happen
+                 * if the device gets disconnected after we've finished
+                 * cancelling URBs, which might not be an error...
+                 */
+        } else {
+                xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq[0] = 0x%x, "
+                                "deq[1] = 0x%x.\n",
+                                dev->out_ctx->ep[ep_index].deq[0],
+                                dev->out_ctx->ep[ep_index].deq[1]);
+        }
+
+        ep_ring->state &= ~SET_DEQ_PENDING;
+        ring_ep_doorbell(xhci, slot_id, ep_index);
+}
+
+
+static void handle_cmd_completion(struct xhci_hcd *xhci,
+                struct xhci_event_cmd *event)
+{
+        int slot_id = TRB_TO_SLOT_ID(event->flags);
+        u64 cmd_dma;
+        dma_addr_t cmd_dequeue_dma;
+
+        cmd_dma = (((u64) event->cmd_trb[1]) << 32) + event->cmd_trb[0];
+        cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
+                        xhci->cmd_ring->dequeue);
+        /* Is the command ring deq ptr out of sync with the deq seg ptr? */
+        if (cmd_dequeue_dma == 0) {
+                xhci->error_bitmask |= 1 << 4;
+                return;
+        }
+        /* Does the DMA address match our internal dequeue pointer address? */
+        if (cmd_dma != (u64) cmd_dequeue_dma) {
+                xhci->error_bitmask |= 1 << 5;
+                return;
+        }
+        switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
+        case TRB_TYPE(TRB_ENABLE_SLOT):
+                if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
+                        xhci->slot_id = slot_id;
+                else
+                        xhci->slot_id = 0;
+                complete(&xhci->addr_dev);
+                break;
+        case TRB_TYPE(TRB_DISABLE_SLOT):
+                if (xhci->devs[slot_id])
+                        xhci_free_virt_device(xhci, slot_id);
+                break;
+        case TRB_TYPE(TRB_CONFIG_EP):
+                xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
+                complete(&xhci->devs[slot_id]->cmd_completion);
+                break;
+        case TRB_TYPE(TRB_ADDR_DEV):
+                xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
+                complete(&xhci->addr_dev);
+                break;
+        case TRB_TYPE(TRB_STOP_RING):
+                handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue);
+                break;
+        case TRB_TYPE(TRB_SET_DEQ):
+                handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
+                break;
+        case TRB_TYPE(TRB_CMD_NOOP):
+                ++xhci->noops_handled;
+                break;
+        default:
+                /* Skip over unknown commands on the event ring */
+                xhci->error_bitmask |= 1 << 6;
+                break;
+        }
+        inc_deq(xhci, xhci->cmd_ring, false);
+}
+
+static void handle_port_status(struct xhci_hcd *xhci,
+                union xhci_trb *event)
+{
+        u32 port_id;
+
+        /* Port status change events always have a successful completion code */
+        if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
+                xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
+                xhci->error_bitmask |= 1 << 8;
+        }
+        /* FIXME: core doesn't care about all port link state changes yet */
+        port_id = GET_PORT_ID(event->generic.field[0]);
+        xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
+
+        /* Update event ring dequeue pointer before dropping the lock */
+        inc_deq(xhci, xhci->event_ring, true);
+        xhci_set_hc_event_deq(xhci);
+
+        spin_unlock(&xhci->lock);
+        /* Pass this up to the core */
+        usb_hcd_poll_rh_status(xhci_to_hcd(xhci));
+        spin_lock(&xhci->lock);
+}
+
+/*
+ * This TD is defined by the TRBs starting at start_trb in start_seg and ending
+ * at end_trb, which may be in another segment.  If the suspect DMA address is a
+ * TRB in this TD, this function returns that TRB's segment.  Otherwise it
+ * returns 0.
+ */
+static struct xhci_segment *trb_in_td(
+                struct xhci_segment *start_seg,
+                union xhci_trb  *start_trb,
+                union xhci_trb  *end_trb,
+                dma_addr_t      suspect_dma)
+{
+        dma_addr_t start_dma;
+        dma_addr_t end_seg_dma;
+        dma_addr_t end_trb_dma;
+        struct xhci_segment *cur_seg;
+
+        start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
+        cur_seg = start_seg;
+
+        do {
+                /* We may get an event for a Link TRB in the middle of a TD */
+                end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
+                                &start_seg->trbs[TRBS_PER_SEGMENT - 1]);
+                /* If the end TRB isn't in this segment, this is set to 0 */
+                end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
+
+                if (end_trb_dma > 0) {
+                        /* The end TRB is in this segment, so suspect should be here */
+                        if (start_dma <= end_trb_dma) {
+                                if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
+                                        return cur_seg;
+                        } else {
+                                /* Case for one segment with
+                                 * a TD wrapped around to the top
+                                 */
+                                if ((suspect_dma >= start_dma &&
+                                                        suspect_dma <= end_seg_dma) ||
+                                                (suspect_dma >= cur_seg->dma &&
+                                                 suspect_dma <= end_trb_dma))
+                                        return cur_seg;
+                        }
+                        return 0;
+                } else {
+                        /* Might still be somewhere in this segment */
+                        if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
+                                return cur_seg;
+                }
+                cur_seg = cur_seg->next;
+                start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
+        } while (1);
+
+}
+
+/*
+ * If this function returns an error condition, it means it got a Transfer
+ * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
+ * At this point, the host controller is probably hosed and should be reset.
+ */
+static int handle_tx_event(struct xhci_hcd *xhci,
+                struct xhci_transfer_event *event)
+{
+        struct xhci_virt_device *xdev;
+        struct xhci_ring *ep_ring;
+        int ep_index;
+        struct xhci_td *td = 0;
+        dma_addr_t event_dma;
+        struct xhci_segment *event_seg;
+        union xhci_trb *event_trb;
+        struct urb *urb = 0;
+        int status = -EINPROGRESS;
+
+        xdev = xhci->devs[TRB_TO_SLOT_ID(event->flags)];
+        if (!xdev) {
+                xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
+                return -ENODEV;
+        }
+
+        /* Endpoint ID is 1 based, our index is zero based */
+        ep_index = TRB_TO_EP_ID(event->flags) - 1;
+        ep_ring = xdev->ep_rings[ep_index];
+        if (!ep_ring || (xdev->out_ctx->ep[ep_index].ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
+                xhci_err(xhci, "ERROR Transfer event pointed to disabled endpoint\n");
+                return -ENODEV;
+        }
+
+        event_dma = event->buffer[0];
+        if (event->buffer[1] != 0)
+                xhci_warn(xhci, "WARN ignoring upper 32-bits of 64-bit TRB dma address\n");
+
+        /* This TRB should be in the TD at the head of this ring's TD list */
+        if (list_empty(&ep_ring->td_list)) {
+                xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
+                                TRB_TO_SLOT_ID(event->flags), ep_index);
+                xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
+                                (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
+                xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
+                urb = NULL;
+                goto cleanup;
+        }
+        td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
+
+        /* Is this a TRB in the currently executing TD? */
+        event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
+                        td->last_trb, event_dma);
+        if (!event_seg) {
+                /* HC is busted, give up! */
+                xhci_err(xhci, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
+                return -ESHUTDOWN;
+        }
+        event_trb = &event_seg->trbs[(event_dma - event_seg->dma) / sizeof(*event_trb)];
+        xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
+                        (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
+        xhci_dbg(xhci, "Offset 0x00 (buffer[0]) = 0x%x\n",
+                        (unsigned int) event->buffer[0]);
+        xhci_dbg(xhci, "Offset 0x04 (buffer[0]) = 0x%x\n",
+                        (unsigned int) event->buffer[1]);
+        xhci_dbg(xhci, "Offset 0x08 (transfer length) = 0x%x\n",
+                        (unsigned int) event->transfer_len);
+        xhci_dbg(xhci, "Offset 0x0C (flags) = 0x%x\n",
+                        (unsigned int) event->flags);
+
+        /* Look for common error cases */
+        switch (GET_COMP_CODE(event->transfer_len)) {
+        /* Skip codes that require special handling depending on
+         * transfer type
+         */
+        case COMP_SUCCESS:
+        case COMP_SHORT_TX:
+                break;
+        case COMP_STOP:
+                xhci_dbg(xhci, "Stopped on Transfer TRB\n");
+                break;
+        case COMP_STOP_INVAL:
+                xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
+                break;
+        case COMP_STALL:
+                xhci_warn(xhci, "WARN: Stalled endpoint\n");
+                status = -EPIPE;
+                break;
+        case COMP_TRB_ERR:
+                xhci_warn(xhci, "WARN: TRB error on endpoint\n");
+                status = -EILSEQ;
+                break;
+        case COMP_TX_ERR:
+                xhci_warn(xhci, "WARN: transfer error on endpoint\n");
+                status = -EPROTO;
+                break;
+        case COMP_DB_ERR:
+                xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
+                status = -ENOSR;
+                break;
+        default:
+                xhci_warn(xhci, "ERROR Unknown event condition, HC probably busted\n");
+                urb = NULL;
+                goto cleanup;
+        }
+        /* Now update the urb's actual_length and give back to the core */
+        /* Was this a control transfer? */
+        if (usb_endpoint_xfer_control(&td->urb->ep->desc)) {
+                xhci_debug_trb(xhci, xhci->event_ring->dequeue);
+                switch (GET_COMP_CODE(event->transfer_len)) {
+                case COMP_SUCCESS:
+                        if (event_trb == ep_ring->dequeue) {
+                                xhci_warn(xhci, "WARN: Success on ctrl setup TRB without IOC set??\n");
+                                status = -ESHUTDOWN;
+                        } else if (event_trb != td->last_trb) {
+                                xhci_warn(xhci, "WARN: Success on ctrl data TRB without IOC set??\n");
+                                status = -ESHUTDOWN;
+                        } else {
+                                xhci_dbg(xhci, "Successful control transfer!\n");
+                                status = 0;
+                        }
+                        break;
+                case COMP_SHORT_TX:
+                        xhci_warn(xhci, "WARN: short transfer on control ep\n");
+                        status = -EREMOTEIO;
+                        break;
+                default:
+                        /* Others already handled above */
+                        break;
+                }
+                /*
+                 * Did we transfer any data, despite the errors that might have
+                 * happened?  I.e. did we get past the setup stage?
+                 */
+                if (event_trb != ep_ring->dequeue) {
+                        /* The event was for the status stage */
+                        if (event_trb == td->last_trb) {
+                                td->urb->actual_length =
+                                        td->urb->transfer_buffer_length;
+                        } else {
+                        /* Maybe the event was for the data stage? */
+                                if (GET_COMP_CODE(event->transfer_len) != COMP_STOP_INVAL)
+                                        /* We didn't stop on a link TRB in the middle */
+                                        td->urb->actual_length =
+                                                td->urb->transfer_buffer_length -
+                                                TRB_LEN(event->transfer_len);
+                        }
+                }
+        } else {
+                switch (GET_COMP_CODE(event->transfer_len)) {
+                case COMP_SUCCESS:
+                        /* Double check that the HW transferred everything. */
+                        if (event_trb != td->last_trb) {
+                                xhci_warn(xhci, "WARN Successful completion "
+                                                "on short TX\n");
+                                if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
+                                        status = -EREMOTEIO;
+                                else
+                                        status = 0;
+                        } else {
+                                xhci_dbg(xhci, "Successful bulk transfer!\n");
+                                status = 0;
+                        }
+                        break;
+                case COMP_SHORT_TX:
+                        if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
+                                status = -EREMOTEIO;
+                        else
+                                status = 0;
+                        break;
+                default:
+                        /* Others already handled above */
+                        break;
+                }
+                dev_dbg(&td->urb->dev->dev,
+                                "ep %#x - asked for %d bytes, "
+                                "%d bytes untransferred\n",
+                                td->urb->ep->desc.bEndpointAddress,
+                                td->urb->transfer_buffer_length,
+                                TRB_LEN(event->transfer_len));
+                /* Fast path - was this the last TRB in the TD for this URB? */
+                if (event_trb == td->last_trb) {
+                        if (TRB_LEN(event->transfer_len) != 0) {
+                                td->urb->actual_length =
+                                        td->urb->transfer_buffer_length -
+                                        TRB_LEN(event->transfer_len);
+                                if (td->urb->actual_length < 0) {
+                                        xhci_warn(xhci, "HC gave bad length "
+                                                        "of %d bytes left\n",
+                                                        TRB_LEN(event->transfer_len));
+                                        td->urb->actual_length = 0;
+                                }
+                                if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
+                                        status = -EREMOTEIO;
+                                else
+                                        status = 0;
+                        } else {
+                                td->urb->actual_length = td->urb->transfer_buffer_length;
+                                /* Ignore a short packet completion if the
+                                 * untransferred length was zero.
+                                 */
+                                status = 0;
+                        }
+                } else {
+                        /* Slow path - walk the list, starting from the dequeue
+                         * pointer, to get the actual length transferred.
+                         */
+                        union xhci_trb *cur_trb;
+                        struct xhci_segment *cur_seg;
+
+                        td->urb->actual_length = 0;
+                        for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
+                                        cur_trb != event_trb;
+                                        next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
+                                if (TRB_TYPE(cur_trb->generic.field[3]) != TRB_TR_NOOP &&
+                                                TRB_TYPE(cur_trb->generic.field[3]) != TRB_LINK)
+                                        td->urb->actual_length +=
+                                                TRB_LEN(cur_trb->generic.field[2]);
+                        }
+                        /* If the ring didn't stop on a Link or No-op TRB, add
+                         * in the actual bytes transferred from the Normal TRB
+                         */
+                        if (GET_COMP_CODE(event->transfer_len) != COMP_STOP_INVAL)
+                                td->urb->actual_length +=
+                                        TRB_LEN(cur_trb->generic.field[2]) -
+                                        TRB_LEN(event->transfer_len);
+                }
+        }
+        /* The Endpoint Stop Command completion will take care of
+         * any stopped TDs.  A stopped TD may be restarted, so don't update the
+         * ring dequeue pointer or take this TD off any lists yet.
+         */
+        if (GET_COMP_CODE(event->transfer_len) == COMP_STOP_INVAL ||
+                        GET_COMP_CODE(event->transfer_len) == COMP_STOP) {
+                ep_ring->stopped_td = td;
+                ep_ring->stopped_trb = event_trb;
+        } else {
+                /* Update ring dequeue pointer */
+                while (ep_ring->dequeue != td->last_trb)
+                        inc_deq(xhci, ep_ring, false);
+                inc_deq(xhci, ep_ring, false);
+
+                /* Clean up the endpoint's TD list */
+                urb = td->urb;
+                list_del(&td->td_list);
+                /* Was this TD slated to be cancelled but completed anyway? */
+                if (!list_empty(&td->cancelled_td_list)) {
+                        list_del(&td->cancelled_td_list);
+                        ep_ring->cancels_pending--;
+                }
+                kfree(td);
+                urb->hcpriv = NULL;
+        }
+cleanup:
+        inc_deq(xhci, xhci->event_ring, true);
+        xhci_set_hc_event_deq(xhci);
+
+        /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
+        if (urb) {
+                usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci), urb);
+                spin_unlock(&xhci->lock);
+                usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, status);
+                spin_lock(&xhci->lock);
+        }
+        return 0;
+}
+
+/*
+ * This function handles all OS-owned events on the event ring.  It may drop
+ * xhci->lock between event processing (e.g. to pass up port status changes).
+ */
+void xhci_handle_event(struct xhci_hcd *xhci)
+{
+        union xhci_trb *event;
+        int update_ptrs = 1;
+        int ret;
+
+        if (!xhci->event_ring || !xhci->event_ring->dequeue) {
+                xhci->error_bitmask |= 1 << 1;
+                return;
+        }
+
+        event = xhci->event_ring->dequeue;
+        /* Does the HC or OS own the TRB? */
+        if ((event->event_cmd.flags & TRB_CYCLE) !=
+                        xhci->event_ring->cycle_state) {
+                xhci->error_bitmask |= 1 << 2;
+                return;
+        }
+
+        /* FIXME: Handle more event types. */
+        switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
+        case TRB_TYPE(TRB_COMPLETION):
+                handle_cmd_completion(xhci, &event->event_cmd);
+                break;
+        case TRB_TYPE(TRB_PORT_STATUS):
+                handle_port_status(xhci, event);
+                update_ptrs = 0;
+                break;
+        case TRB_TYPE(TRB_TRANSFER):
+                ret = handle_tx_event(xhci, &event->trans_event);
+                if (ret < 0)
+                        xhci->error_bitmask |= 1 << 9;
+                else
+                        update_ptrs = 0;
+                break;
+        default:
+                xhci->error_bitmask |= 1 << 3;
+        }
+
+        if (update_ptrs) {
+                /* Update SW and HC event ring dequeue pointer */
+                inc_deq(xhci, xhci->event_ring, true);
+                xhci_set_hc_event_deq(xhci);
+        }
+        /* Are there more items on the event ring? */
+        xhci_handle_event(xhci);
+}
+
+/****           Endpoint Ring Operations        ****/
+
+/*
+ * Generic function for queueing a TRB on a ring.
+ * The caller must have checked to make sure there's room on the ring.
+ */
+static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
+                bool consumer,
+                u32 field1, u32 field2, u32 field3, u32 field4)
+{
+        struct xhci_generic_trb *trb;
+
+        trb = &ring->enqueue->generic;
+        trb->field[0] = field1;
+        trb->field[1] = field2;
+        trb->field[2] = field3;
+        trb->field[3] = field4;
+        inc_enq(xhci, ring, consumer);
+}
+
+/*
+ * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
+ * FIXME allocate segments if the ring is full.
+ */
+static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
+                u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
+{
+        /* Make sure the endpoint has been added to xHC schedule */
+        xhci_dbg(xhci, "Endpoint state = 0x%x\n", ep_state);
+        switch (ep_state) {
+        case EP_STATE_DISABLED:
+                /*
+                 * USB core changed config/interfaces without notifying us,
+                 * or hardware is reporting the wrong state.
+                 */
+                xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
+                return -ENOENT;
+        case EP_STATE_HALTED:
+        case EP_STATE_ERROR:
+                xhci_warn(xhci, "WARN waiting for halt or error on ep "
+                                "to be cleared\n");
+                /* FIXME event handling code for error needs to clear it */
+                /* XXX not sure if this should be -ENOENT or not */
+                return -EINVAL;
+        case EP_STATE_STOPPED:
+        case EP_STATE_RUNNING:
+                break;
+        default:
+                xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
+                /*
+                 * FIXME issue Configure Endpoint command to try to get the HC
+                 * back into a known state.
+                 */
+                return -EINVAL;
+        }
+        if (!room_on_ring(xhci, ep_ring, num_trbs)) {
+                /* FIXME allocate more room */
+                xhci_err(xhci, "ERROR no room on ep ring\n");
+                return -ENOMEM;
+        }
+        return 0;
+}
+
+static int prepare_transfer(struct xhci_hcd *xhci,
+                struct xhci_virt_device *xdev,
+                unsigned int ep_index,
+                unsigned int num_trbs,
+                struct urb *urb,
+                struct xhci_td **td,
+                gfp_t mem_flags)
+{
+        int ret;
+
+        ret = prepare_ring(xhci, xdev->ep_rings[ep_index],
+                        xdev->out_ctx->ep[ep_index].ep_info & EP_STATE_MASK,
+                        num_trbs, mem_flags);
+        if (ret)
+                return ret;
+        *td = kzalloc(sizeof(struct xhci_td), mem_flags);
+        if (!*td)
+                return -ENOMEM;
+        INIT_LIST_HEAD(&(*td)->td_list);
+        INIT_LIST_HEAD(&(*td)->cancelled_td_list);
+
+        ret = usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci), urb);
+        if (unlikely(ret)) {
+                kfree(*td);
+                return ret;
+        }
+
+        (*td)->urb = urb;
+        urb->hcpriv = (void *) (*td);
+        /* Add this TD to the tail of the endpoint ring's TD list */
+        list_add_tail(&(*td)->td_list, &xdev->ep_rings[ep_index]->td_list);
+        (*td)->start_seg = xdev->ep_rings[ep_index]->enq_seg;
+        (*td)->first_trb = xdev->ep_rings[ep_index]->enqueue;
+
+        return 0;
+}
+
+static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
+{
+        int num_sgs, num_trbs, running_total, temp, i;
+        struct scatterlist *sg;
+
+        sg = NULL;
+        num_sgs = urb->num_sgs;
+        temp = urb->transfer_buffer_length;
+
+        xhci_dbg(xhci, "count sg list trbs: \n");
+        num_trbs = 0;
+        for_each_sg(urb->sg->sg, sg, num_sgs, i) {
+                unsigned int previous_total_trbs = num_trbs;
+                unsigned int len = sg_dma_len(sg);
+
+                /* Scatter gather list entries may cross 64KB boundaries */
+                running_total = TRB_MAX_BUFF_SIZE -
+                        (sg_dma_address(sg) & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
+                if (running_total != 0)
+                        num_trbs++;
+
+                /* How many more 64KB chunks to transfer, how many more TRBs? */
+                while (running_total < sg_dma_len(sg)) {
+                        num_trbs++;
+                        running_total += TRB_MAX_BUFF_SIZE;
+                }
+                xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
+                                i, (unsigned long long)sg_dma_address(sg),
+                                len, len, num_trbs - previous_total_trbs);
+
+                len = min_t(int, len, temp);
+                temp -= len;
+                if (temp == 0)
+                        break;
+        }
+        xhci_dbg(xhci, "\n");
+        if (!in_interrupt())
+                dev_dbg(&urb->dev->dev, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
+                                urb->ep->desc.bEndpointAddress,
+                                urb->transfer_buffer_length,
+                                num_trbs);
+        return num_trbs;
+}
+
+static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
+{
+        if (num_trbs != 0)
+                dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
+                                "TRBs, %d left\n", __func__,
+                                urb->ep->desc.bEndpointAddress, num_trbs);
+        if (running_total != urb->transfer_buffer_length)
+                dev_dbg(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
+                                "queued %#x (%d), asked for %#x (%d)\n",
+                                __func__,
+                                urb->ep->desc.bEndpointAddress,
+                                running_total, running_total,
+                                urb->transfer_buffer_length,
+                                urb->transfer_buffer_length);
+}
+
+static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
+                unsigned int ep_index, int start_cycle,
+                struct xhci_generic_trb *start_trb, struct xhci_td *td)
+{
+        /*
+         * Pass all the TRBs to the hardware at once and make sure this write
+         * isn't reordered.
+         */
+        wmb();
+        start_trb->field[3] |= start_cycle;
+        ring_ep_doorbell(xhci, slot_id, ep_index);
+}
+
+static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
+                struct urb *urb, int slot_id, unsigned int ep_index)
+{
+        struct xhci_ring *ep_ring;
+        unsigned int num_trbs;
+        struct xhci_td *td;
+        struct scatterlist *sg;
+        int num_sgs;
+        int trb_buff_len, this_sg_len, running_total;
+        bool first_trb;
+        u64 addr;
+
+        struct xhci_generic_trb *start_trb;
+        int start_cycle;
+
+        ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
+        num_trbs = count_sg_trbs_needed(xhci, urb);
+        num_sgs = urb->num_sgs;
+
+        trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
+                        ep_index, num_trbs, urb, &td, mem_flags);
+        if (trb_buff_len < 0)
+                return trb_buff_len;
+        /*
+         * Don't give the first TRB to the hardware (by toggling the cycle bit)
+         * until we've finished creating all the other TRBs.  The ring's cycle
+         * state may change as we enqueue the other TRBs, so save it too.
+         */
+        start_trb = &ep_ring->enqueue->generic;
+        start_cycle = ep_ring->cycle_state;
+
+        running_total = 0;
+        /*
+         * How much data is in the first TRB?
+         *
+         * There are three forces at work for TRB buffer pointers and lengths:
+         * 1. We don't want to walk off the end of this sg-list entry buffer.
+         * 2. The transfer length that the driver requested may be smaller than
+         *    the amount of memory allocated for this scatter-gather list.
+         * 3. TRBs buffers can't cross 64KB boundaries.
+         */
+        sg = urb->sg->sg;
+        addr = (u64) sg_dma_address(sg);
+        this_sg_len = sg_dma_len(sg);
+        trb_buff_len = TRB_MAX_BUFF_SIZE -
+                (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
+        trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
+        if (trb_buff_len > urb->transfer_buffer_length)
+                trb_buff_len = urb->transfer_buffer_length;
+        xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
+                        trb_buff_len);
+
+        first_trb = true;
+        /* Queue the first TRB, even if it's zero-length */
+        do {
+                u32 field = 0;
+
+                /* Don't change the cycle bit of the first TRB until later */
+                if (first_trb)
+                        first_trb = false;
+                else
+                        field |= ep_ring->cycle_state;
+
+                /* Chain all the TRBs together; clear the chain bit in the last
+                 * TRB to indicate it's the last TRB in the chain.
+                 */
+                if (num_trbs > 1) {
+                        field |= TRB_CHAIN;
+                } else {
+                        /* FIXME - add check for ZERO_PACKET flag before this */
+                        td->last_trb = ep_ring->enqueue;
+                        field |= TRB_IOC;
+                }
+                xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
+                                "64KB boundary at %#x, end dma = %#x\n",
+                                (unsigned int) addr, trb_buff_len, trb_buff_len,
+                                (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
+                                (unsigned int) addr + trb_buff_len);
+                if (TRB_MAX_BUFF_SIZE -
+                                (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1)) < trb_buff_len) {
+                        xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
+                        xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
+                                        (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
+                                        (unsigned int) addr + trb_buff_len);
+                }
+                queue_trb(xhci, ep_ring, false,
+                                (u32) addr,
+                                (u32) ((u64) addr >> 32),
+                                TRB_LEN(trb_buff_len) | TRB_INTR_TARGET(0),
+                                /* We always want to know if the TRB was short,
+                                 * or we won't get an event when it completes.
+                                 * (Unless we use event data TRBs, which are a
+                                 * waste of space and HC resources.)
+                                 */
+                                field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
+                --num_trbs;
+                running_total += trb_buff_len;
+
+                /* Calculate length for next transfer --
+                 * Are we done queueing all the TRBs for this sg entry?
+                 */
+                this_sg_len -= trb_buff_len;
+                if (this_sg_len == 0) {
+                        --num_sgs;
+                        if (num_sgs == 0)
+                                break;
+                        sg = sg_next(sg);
+                        addr = (u64) sg_dma_address(sg);
+                        this_sg_len = sg_dma_len(sg);
+                } else {
+                        addr += trb_buff_len;
+                }
+
+                trb_buff_len = TRB_MAX_BUFF_SIZE -
+                        (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
+                trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
+                if (running_total + trb_buff_len > urb->transfer_buffer_length)
+                        trb_buff_len =
+                                urb->transfer_buffer_length - running_total;
+        } while (running_total < urb->transfer_buffer_length);
+
+        check_trb_math(urb, num_trbs, running_total);
+        giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
+        return 0;
+}
+
+/* This is very similar to what ehci-q.c qtd_fill() does */
+int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
+                struct urb *urb, int slot_id, unsigned int ep_index)
+{
+        struct xhci_ring *ep_ring;
+        struct xhci_td *td;
+        int num_trbs;
+        struct xhci_generic_trb *start_trb;
+        bool first_trb;
+        int start_cycle;
+        u32 field;
+
+        int running_total, trb_buff_len, ret;
+        u64 addr;
+
+        if (urb->sg)
+                return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
+
+        ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
+
+        num_trbs = 0;
+        /* How much data is (potentially) left before the 64KB boundary? */
+        running_total = TRB_MAX_BUFF_SIZE -
+                (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
+
+        /* If there's some data on this 64KB chunk, or we have to send a
+         * zero-length transfer, we need at least one TRB
+         */
+        if (running_total != 0 || urb->transfer_buffer_length == 0)
+                num_trbs++;
+        /* How many more 64KB chunks to transfer, how many more TRBs? */
+        while (running_total < urb->transfer_buffer_length) {
+                num_trbs++;
+                running_total += TRB_MAX_BUFF_SIZE;
+        }
+        /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
+
+        if (!in_interrupt())
+                dev_dbg(&urb->dev->dev, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
+                                urb->ep->desc.bEndpointAddress,
+                                urb->transfer_buffer_length,
+                                urb->transfer_buffer_length,
+                                (unsigned long long)urb->transfer_dma,
+                                num_trbs);
+
+        ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
+                        num_trbs, urb, &td, mem_flags);
+        if (ret < 0)
+                return ret;
+
+        /*
+         * Don't give the first TRB to the hardware (by toggling the cycle bit)
+         * until we've finished creating all the other TRBs.  The ring's cycle
+         * state may change as we enqueue the other TRBs, so save it too.
+         */
+        start_trb = &ep_ring->enqueue->generic;
+        start_cycle = ep_ring->cycle_state;
+
+        running_total = 0;
+        /* How much data is in the first TRB? */
+        addr = (u64) urb->transfer_dma;
+        trb_buff_len = TRB_MAX_BUFF_SIZE -
+                (urb->transfer_dma & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
+        if (urb->transfer_buffer_length < trb_buff_len)
+                trb_buff_len = urb->transfer_buffer_length;
+
+        first_trb = true;
+
+        /* Queue the first TRB, even if it's zero-length */
+        do {
+                field = 0;
+
+                /* Don't change the cycle bit of the first TRB until later */
+                if (first_trb)
+                        first_trb = false;
+                else
+                        field |= ep_ring->cycle_state;
+
+                /* Chain all the TRBs together; clear the chain bit in the last
+                 * TRB to indicate it's the last TRB in the chain.
+                 */
+                if (num_trbs > 1) {
+                        field |= TRB_CHAIN;
+                } else {
+                        /* FIXME - add check for ZERO_PACKET flag before this */
+                        td->last_trb = ep_ring->enqueue;
+                        field |= TRB_IOC;
+                }
+                queue_trb(xhci, ep_ring, false,
+                                (u32) addr,
+                                (u32) ((u64) addr >> 32),
+                                TRB_LEN(trb_buff_len) | TRB_INTR_TARGET(0),
+                                /* We always want to know if the TRB was short,
+                                 * or we won't get an event when it completes.
+                                 * (Unless we use event data TRBs, which are a
+                                 * waste of space and HC resources.)
+                                 */
+                                field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
+                --num_trbs;
+                running_total += trb_buff_len;
+
+                /* Calculate length for next transfer */
+                addr += trb_buff_len;
+                trb_buff_len = urb->transfer_buffer_length - running_total;
+                if (trb_buff_len > TRB_MAX_BUFF_SIZE)
+                        trb_buff_len = TRB_MAX_BUFF_SIZE;
+        } while (running_total < urb->transfer_buffer_length);
+
+        check_trb_math(urb, num_trbs, running_total);
+        giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
+        return 0;
+}
+
+/* Caller must have locked xhci->lock */
+int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
+                struct urb *urb, int slot_id, unsigned int ep_index)
+{
+        struct xhci_ring *ep_ring;
+        int num_trbs;
+        int ret;
+        struct usb_ctrlrequest *setup;
+        struct xhci_generic_trb *start_trb;
+        int start_cycle;
+        u32 field;
+        struct xhci_td *td;
+
+        ep_ring = xhci->devs[slot_id]->ep_rings[ep_index];
+
+        /*
+         * Need to copy setup packet into setup TRB, so we can't use the setup
+         * DMA address.
+         */
+        if (!urb->setup_packet)
+                return -EINVAL;
+
+        if (!in_interrupt())
+                xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
+                                slot_id, ep_index);
+        /* 1 TRB for setup, 1 for status */
+        num_trbs = 2;
+        /*
+         * Don't need to check if we need additional event data and normal TRBs,
+         * since data in control transfers will never get bigger than 16MB
+         * XXX: can we get a buffer that crosses 64KB boundaries?
+         */
+        if (urb->transfer_buffer_length > 0)
+                num_trbs++;
+        ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index, num_trbs,
+                        urb, &td, mem_flags);
+        if (ret < 0)
+                return ret;
+
+        /*
+         * Don't give the first TRB to the hardware (by toggling the cycle bit)
+         * until we've finished creating all the other TRBs.  The ring's cycle
+         * state may change as we enqueue the other TRBs, so save it too.
+         */
+        start_trb = &ep_ring->enqueue->generic;
+        start_cycle = ep_ring->cycle_state;
+
+        /* Queue setup TRB - see section 6.4.1.2.1 */
+        /* FIXME better way to translate setup_packet into two u32 fields? */
+        setup = (struct usb_ctrlrequest *) urb->setup_packet;
+        queue_trb(xhci, ep_ring, false,
+                        /* FIXME endianness is probably going to bite my ass here. */
+                        setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
+                        setup->wIndex | setup->wLength << 16,
+                        TRB_LEN(8) | TRB_INTR_TARGET(0),
+                        /* Immediate data in pointer */
+                        TRB_IDT | TRB_TYPE(TRB_SETUP));
+
+        /* If there's data, queue data TRBs */
+        field = 0;
+        if (urb->transfer_buffer_length > 0) {
+                if (setup->bRequestType & USB_DIR_IN)
+                        field |= TRB_DIR_IN;
+                queue_trb(xhci, ep_ring, false,
+                                lower_32_bits(urb->transfer_dma),
+                                upper_32_bits(urb->transfer_dma),
+                                TRB_LEN(urb->transfer_buffer_length) | TRB_INTR_TARGET(0),
+                                /* Event on short tx */
+                                field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
+        }
+
+        /* Save the DMA address of the last TRB in the TD */
+        td->last_trb = ep_ring->enqueue;
+
+        /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
+        /* If the device sent data, the status stage is an OUT transfer */
+        if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
+                field = 0;
+        else
+                field = TRB_DIR_IN;
+        queue_trb(xhci, ep_ring, false,
+                        0,
+                        0,
+                        TRB_INTR_TARGET(0),
+                        /* Event on completion */
+                        field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
+
+        giveback_first_trb(xhci, slot_id, ep_index, start_cycle, start_trb, td);
+        return 0;
+}
+
+/****           Command Ring Operations         ****/
+
+/* Generic function for queueing a command TRB on the command ring */
+static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2, u32 field3, u32 field4)
+{
+        if (!room_on_ring(xhci, xhci->cmd_ring, 1)) {
+                if (!in_interrupt())
+                        xhci_err(xhci, "ERR: No room for command on command ring\n");
+                return -ENOMEM;
+        }
+        queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
+                        field4 | xhci->cmd_ring->cycle_state);
+        return 0;
+}
+
+/* Queue a no-op command on the command ring */
+static int queue_cmd_noop(struct xhci_hcd *xhci)
+{
+        return queue_command(xhci, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP));
+}
+
+/*
+ * Place a no-op command on the command ring to test the command and
+ * event ring.
+ */
+void *xhci_setup_one_noop(struct xhci_hcd *xhci)
+{
+        if (queue_cmd_noop(xhci) < 0)
+                return NULL;
+        xhci->noops_submitted++;
+        return xhci_ring_cmd_db;
+}
+
+/* Queue a slot enable or disable request on the command ring */
+int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
+{
+        return queue_command(xhci, 0, 0, 0,
+                        TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id));
+}
+
+/* Queue an address device command TRB */
+int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
+                u32 slot_id)
+{
+        return queue_command(xhci, in_ctx_ptr, 0, 0,
+                        TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id));
+}
+
+/* Queue a configure endpoint command TRB */
+int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
+                u32 slot_id)
+{
+        return queue_command(xhci, in_ctx_ptr, 0, 0,
+                        TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id));
+}
+
+int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
+                unsigned int ep_index)
+{
+        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
+        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
+        u32 type = TRB_TYPE(TRB_STOP_RING);
+
+        return queue_command(xhci, 0, 0, 0,
+                        trb_slot_id | trb_ep_index | type);
+}
+
+/* Set Transfer Ring Dequeue Pointer command.
+ * This should not be used for endpoints that have streams enabled.
+ */
+static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
+                unsigned int ep_index, struct xhci_segment *deq_seg,
+                union xhci_trb *deq_ptr, u32 cycle_state)
+{
+        dma_addr_t addr;
+        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
+        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
+        u32 type = TRB_TYPE(TRB_SET_DEQ);
+
+        addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
+        if (addr == 0)
+                xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
+                xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
+                                deq_seg, deq_ptr);
+        return queue_command(xhci, (u32) addr | cycle_state, 0, 0,
+                        trb_slot_id | trb_ep_index | type);
+}
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
new file mode 100644
index 000000000000..8936eeb5588b
--- /dev/null
+++ b/drivers/usb/host/xhci.h
@@ -0,0 +1,1157 @@
+/*
+ * xHCI host controller driver
+ *
+ * Copyright (C) 2008 Intel Corp.
+ *
+ * Author: Sarah Sharp
+ * Some code borrowed from the Linux EHCI driver.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __LINUX_XHCI_HCD_H
+#define __LINUX_XHCI_HCD_H
+
+#include <linux/usb.h>
+#include <linux/timer.h>
+
+#include "../core/hcd.h"
+/* Code sharing between pci-quirks and xhci hcd */
+#include        "xhci-ext-caps.h"
+
+/* xHCI PCI Configuration Registers */
+#define XHCI_SBRN_OFFSET        (0x60)
+
+/* Max number of USB devices for any host controller - limit in section 6.1 */
+#define MAX_HC_SLOTS            256
+/* Section 5.3.3 - MaxPorts */
+#define MAX_HC_PORTS            127
+
+/*
+ * xHCI register interface.
+ * This corresponds to the eXtensible Host Controller Interface (xHCI)
+ * Revision 0.95 specification
+ *
+ * Registers should always be accessed with double word or quad word accesses.
+ *
+ * Some xHCI implementations may support 64-bit address pointers.  Registers
+ * with 64-bit address pointers should be written to with dword accesses by
+ * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
+ * xHCI implementations that do not support 64-bit address pointers will ignore
+ * the high dword, and write order is irrelevant.
+ */
+
+/**
+ * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
+ * @hc_capbase:         length of the capabilities register and HC version number
+ * @hcs_params1:        HCSPARAMS1 - Structural Parameters 1
+ * @hcs_params2:        HCSPARAMS2 - Structural Parameters 2
+ * @hcs_params3:        HCSPARAMS3 - Structural Parameters 3
+ * @hcc_params:         HCCPARAMS - Capability Parameters
+ * @db_off:             DBOFF - Doorbell array offset
+ * @run_regs_off:       RTSOFF - Runtime register space offset
+ */
+struct xhci_cap_regs {
+        u32     hc_capbase;
+        u32     hcs_params1;
+        u32     hcs_params2;
+        u32     hcs_params3;
+        u32     hcc_params;
+        u32     db_off;
+        u32     run_regs_off;
+        /* Reserved up to (CAPLENGTH - 0x1C) */
+};
+
+/* hc_capbase bitmasks */
+/* bits 7:0 - how long is the Capabilities register */
+#define HC_LENGTH(p)            XHCI_HC_LENGTH(p)
+/* bits 31:16   */
+#define HC_VERSION(p)           (((p) >> 16) & 0xffff)
+
+/* HCSPARAMS1 - hcs_params1 - bitmasks */
+/* bits 0:7, Max Device Slots */
+#define HCS_MAX_SLOTS(p)        (((p) >> 0) & 0xff)
+#define HCS_SLOTS_MASK          0xff
+/* bits 8:18, Max Interrupters */
+#define HCS_MAX_INTRS(p)        (((p) >> 8) & 0x7ff)
+/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
+#define HCS_MAX_PORTS(p)        (((p) >> 24) & 0x7f)
+
+/* HCSPARAMS2 - hcs_params2 - bitmasks */
+/* bits 0:3, frames or uframes that SW needs to queue transactions
+ * ahead of the HW to meet periodic deadlines */
+#define HCS_IST(p)              (((p) >> 0) & 0xf)
+/* bits 4:7, max number of Event Ring segments */
+#define HCS_ERST_MAX(p)         (((p) >> 4) & 0xf)
+/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
+/* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
+
+/* HCSPARAMS3 - hcs_params3 - bitmasks */
+/* bits 0:7, Max U1 to U0 latency for the roothub ports */
+#define HCS_U1_LATENCY(p)       (((p) >> 0) & 0xff)
+/* bits 16:31, Max U2 to U0 latency for the roothub ports */
+#define HCS_U2_LATENCY(p)       (((p) >> 16) & 0xffff)
+
+/* HCCPARAMS - hcc_params - bitmasks */
+/* true: HC can use 64-bit address pointers */
+#define HCC_64BIT_ADDR(p)       ((p) & (1 << 0))
+/* true: HC can do bandwidth negotiation */
+#define HCC_BANDWIDTH_NEG(p)    ((p) & (1 << 1))
+/* true: HC uses 64-byte Device Context structures
+ * FIXME 64-byte context structures aren't supported yet.
+ */
+#define HCC_64BYTE_CONTEXT(p)   ((p) & (1 << 2))
+/* true: HC has port power switches */
+#define HCC_PPC(p)              ((p) & (1 << 3))
+/* true: HC has port indicators */
+#define HCS_INDICATOR(p)        ((p) & (1 << 4))
+/* true: HC has Light HC Reset Capability */
+#define HCC_LIGHT_RESET(p)      ((p) & (1 << 5))
+/* true: HC supports latency tolerance messaging */
+#define HCC_LTC(p)              ((p) & (1 << 6))
+/* true: no secondary Stream ID Support */
+#define HCC_NSS(p)              ((p) & (1 << 7))
+/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
+#define HCC_MAX_PSA             (1 << ((((p) >> 12) & 0xf) + 1))
+/* Extended Capabilities pointer from PCI base - section 5.3.6 */
+#define HCC_EXT_CAPS(p)         XHCI_HCC_EXT_CAPS(p)
+
+/* db_off bitmask - bits 0:1 reserved */
+#define DBOFF_MASK      (~0x3)
+
+/* run_regs_off bitmask - bits 0:4 reserved */
+#define RTSOFF_MASK     (~0x1f)
+
+
+/* Number of registers per port */
+#define NUM_PORT_REGS   4
+
+/**
+ * struct xhci_op_regs - xHCI Host Controller Operational Registers.
+ * @command:            USBCMD - xHC command register
+ * @status:             USBSTS - xHC status register
+ * @page_size:          This indicates the page size that the host controller
+ *                      supports.  If bit n is set, the HC supports a page size
+ *                      of 2^(n+12), up to a 128MB page size.
+ *                      4K is the minimum page size.
+ * @cmd_ring:           CRP - 64-bit Command Ring Pointer
+ * @dcbaa_ptr:          DCBAAP - 64-bit Device Context Base Address Array Pointer
+ * @config_reg:         CONFIG - Configure Register
+ * @port_status_base:   PORTSCn - base address for Port Status and Control
+ *                      Each port has a Port Status and Control register,
+ *                      followed by a Port Power Management Status and Control
+ *                      register, a Port Link Info register, and a reserved
+ *                      register.
+ * @port_power_base:    PORTPMSCn - base address for
+ *                      Port Power Management Status and Control
+ * @port_link_base:     PORTLIn - base address for Port Link Info (current
+ *                      Link PM state and control) for USB 2.1 and USB 3.0
+ *                      devices.
+ */
+struct xhci_op_regs {
+        u32     command;
+        u32     status;
+        u32     page_size;
+        u32     reserved1;
+        u32     reserved2;
+        u32     dev_notification;
+        u32     cmd_ring[2];
+        /* rsvd: offset 0x20-2F */
+        u32     reserved3[4];
+        u32     dcbaa_ptr[2];
+        u32     config_reg;
+        /* rsvd: offset 0x3C-3FF */
+        u32     reserved4[241];
+        /* port 1 registers, which serve as a base address for other ports */
+        u32     port_status_base;
+        u32     port_power_base;
+        u32     port_link_base;
+        u32     reserved5;
+        /* registers for ports 2-255 */
+        u32     reserved6[NUM_PORT_REGS*254];
+};
+
+/* USBCMD - USB command - command bitmasks */
+/* start/stop HC execution - do not write unless HC is halted*/
+#define CMD_RUN         XHCI_CMD_RUN
+/* Reset HC - resets internal HC state machine and all registers (except
+ * PCI config regs).  HC does NOT drive a USB reset on the downstream ports.
+ * The xHCI driver must reinitialize the xHC after setting this bit.
+ */
+#define CMD_RESET       (1 << 1)
+/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
+#define CMD_EIE         XHCI_CMD_EIE
+/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
+#define CMD_HSEIE       XHCI_CMD_HSEIE
+/* bits 4:6 are reserved (and should be preserved on writes). */
+/* light reset (port status stays unchanged) - reset completed when this is 0 */
+#define CMD_LRESET      (1 << 7)
+/* FIXME: ignoring host controller save/restore state for now. */
+#define CMD_CSS         (1 << 8)
+#define CMD_CRS         (1 << 9)
+/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
+#define CMD_EWE         XHCI_CMD_EWE
+/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
+ * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
+ * '0' means the xHC can power it off if all ports are in the disconnect,
+ * disabled, or powered-off state.
+ */
+#define CMD_PM_INDEX    (1 << 11)
+/* bits 12:31 are reserved (and should be preserved on writes). */
+
+/* USBSTS - USB status - status bitmasks */
+/* HC not running - set to 1 when run/stop bit is cleared. */
+#define STS_HALT        XHCI_STS_HALT
+/* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
+#define STS_FATAL       (1 << 2)
+/* event interrupt - clear this prior to clearing any IP flags in IR set*/
+#define STS_EINT        (1 << 3)
+/* port change detect */
+#define STS_PORT        (1 << 4)
+/* bits 5:7 reserved and zeroed */
+/* save state status - '1' means xHC is saving state */
+#define STS_SAVE        (1 << 8)
+/* restore state status - '1' means xHC is restoring state */
+#define STS_RESTORE     (1 << 9)
+/* true: save or restore error */
+#define STS_SRE         (1 << 10)
+/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
+#define STS_CNR         XHCI_STS_CNR
+/* true: internal Host Controller Error - SW needs to reset and reinitialize */
+#define STS_HCE         (1 << 12)
+/* bits 13:31 reserved and should be preserved */
+
+/*
+ * DNCTRL - Device Notification Control Register - dev_notification bitmasks
+ * Generate a device notification event when the HC sees a transaction with a
+ * notification type that matches a bit set in this bit field.
+ */
+#define DEV_NOTE_MASK           (0xffff)
+#define ENABLE_DEV_NOTE(x)      (1 << x)
+/* Most of the device notification types should only be used for debug.
+ * SW does need to pay attention to function wake notifications.
+ */
+#define DEV_NOTE_FWAKE          ENABLE_DEV_NOTE(1)
+
+/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
+/* bit 0 is the command ring cycle state */
+/* stop ring operation after completion of the currently executing command */
+#define CMD_RING_PAUSE          (1 << 1)
+/* stop ring immediately - abort the currently executing command */
+#define CMD_RING_ABORT          (1 << 2)
+/* true: command ring is running */
+#define CMD_RING_RUNNING        (1 << 3)
+/* bits 4:5 reserved and should be preserved */
+/* Command Ring pointer - bit mask for the lower 32 bits. */
+#define CMD_RING_ADDR_MASK      (0xffffffc0)
+
+/* CONFIG - Configure Register - config_reg bitmasks */
+/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
+#define MAX_DEVS(p)     ((p) & 0xff)
+/* bits 8:31 - reserved and should be preserved */
+
+/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
+/* true: device connected */
+#define PORT_CONNECT    (1 << 0)
+/* true: port enabled */
+#define PORT_PE         (1 << 1)
+/* bit 2 reserved and zeroed */
+/* true: port has an over-current condition */
+#define PORT_OC         (1 << 3)
+/* true: port reset signaling asserted */
+#define PORT_RESET      (1 << 4)
+/* Port Link State - bits 5:8
+ * A read gives the current link PM state of the port,
+ * a write with Link State Write Strobe set sets the link state.
+ */
+/* true: port has power (see HCC_PPC) */
+#define PORT_POWER      (1 << 9)
+/* bits 10:13 indicate device speed:
+ * 0 - undefined speed - port hasn't be initialized by a reset yet
+ * 1 - full speed
+ * 2 - low speed
+ * 3 - high speed
+ * 4 - super speed
+ * 5-15 reserved
+ */
+#define DEV_SPEED_MASK          (0xf << 10)
+#define XDEV_FS                 (0x1 << 10)
+#define XDEV_LS                 (0x2 << 10)
+#define XDEV_HS                 (0x3 << 10)
+#define XDEV_SS                 (0x4 << 10)
+#define DEV_UNDEFSPEED(p)       (((p) & DEV_SPEED_MASK) == (0x0<<10))
+#define DEV_FULLSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_FS)
+#define DEV_LOWSPEED(p)         (((p) & DEV_SPEED_MASK) == XDEV_LS)
+#define DEV_HIGHSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_HS)
+#define DEV_SUPERSPEED(p)       (((p) & DEV_SPEED_MASK) == XDEV_SS)
+/* Bits 20:23 in the Slot Context are the speed for the device */
+#define SLOT_SPEED_FS           (XDEV_FS << 10)
+#define SLOT_SPEED_LS           (XDEV_LS << 10)
+#define SLOT_SPEED_HS           (XDEV_HS << 10)
+#define SLOT_SPEED_SS           (XDEV_SS << 10)
+/* Port Indicator Control */
+#define PORT_LED_OFF    (0 << 14)
+#define PORT_LED_AMBER  (1 << 14)
+#define PORT_LED_GREEN  (2 << 14)
+#define PORT_LED_MASK   (3 << 14)
+/* Port Link State Write Strobe - set this when changing link state */
+#define PORT_LINK_STROBE        (1 << 16)
+/* true: connect status change */
+#define PORT_CSC        (1 << 17)
+/* true: port enable change */
+#define PORT_PEC        (1 << 18)
+/* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
+ * into an enabled state, and the device into the default state.  A "warm" reset
+ * also resets the link, forcing the device through the link training sequence.
+ * SW can also look at the Port Reset register to see when warm reset is done.
+ */
+#define PORT_WRC        (1 << 19)
+/* true: over-current change */
+#define PORT_OCC        (1 << 20)
+/* true: reset change - 1 to 0 transition of PORT_RESET */
+#define PORT_RC         (1 << 21)
+/* port link status change - set on some port link state transitions:
+ *  Transition                          Reason
+ *  ------------------------------------------------------------------------------
+ *  - U3 to Resume                      Wakeup signaling from a device
+ *  - Resume to Recovery to U0          USB 3.0 device resume
+ *  - Resume to U0                      USB 2.0 device resume
+ *  - U3 to Recovery to U0              Software resume of USB 3.0 device complete
+ *  - U3 to U0                          Software resume of USB 2.0 device complete
+ *  - U2 to U0                          L1 resume of USB 2.1 device complete
+ *  - U0 to U0 (???)                    L1 entry rejection by USB 2.1 device
+ *  - U0 to disabled                    L1 entry error with USB 2.1 device
+ *  - Any state to inactive             Error on USB 3.0 port
+ */
+#define PORT_PLC        (1 << 22)
+/* port configure error change - port failed to configure its link partner */
+#define PORT_CEC        (1 << 23)
+/* bit 24 reserved */
+/* wake on connect (enable) */
+#define PORT_WKCONN_E   (1 << 25)
+/* wake on disconnect (enable) */
+#define PORT_WKDISC_E   (1 << 26)
+/* wake on over-current (enable) */
+#define PORT_WKOC_E     (1 << 27)
+/* bits 28:29 reserved */
+/* true: device is removable - for USB 3.0 roothub emulation */
+#define PORT_DEV_REMOVE (1 << 30)
+/* Initiate a warm port reset - complete when PORT_WRC is '1' */
+#define PORT_WR         (1 << 31)
+
+/* Port Power Management Status and Control - port_power_base bitmasks */
+/* Inactivity timer value for transitions into U1, in microseconds.
+ * Timeout can be up to 127us.  0xFF means an infinite timeout.
+ */
+#define PORT_U1_TIMEOUT(p)      ((p) & 0xff)
+/* Inactivity timer value for transitions into U2 */
+#define PORT_U2_TIMEOUT(p)      (((p) & 0xff) << 8)
+/* Bits 24:31 for port testing */
+
+
+/**
+ * struct xhci_intr_reg - Interrupt Register Set
+ * @irq_pending:        IMAN - Interrupt Management Register.  Used to enable
+ *                      interrupts and check for pending interrupts.
+ * @irq_control:        IMOD - Interrupt Moderation Register.
+ *                      Used to throttle interrupts.
+ * @erst_size:          Number of segments in the Event Ring Segment Table (ERST).
+ * @erst_base:          ERST base address.
+ * @erst_dequeue:       Event ring dequeue pointer.
+ *
+ * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
+ * Ring Segment Table (ERST) associated with it.  The event ring is comprised of
+ * multiple segments of the same size.  The HC places events on the ring and
+ * "updates the Cycle bit in the TRBs to indicate to software the current
+ * position of the Enqueue Pointer." The HCD (Linux) processes those events and
+ * updates the dequeue pointer.
+ */
+struct xhci_intr_reg {
+        u32     irq_pending;
+        u32     irq_control;
+        u32     erst_size;
+        u32     rsvd;
+        u32     erst_base[2];
+        u32     erst_dequeue[2];
+};
+
+/* irq_pending bitmasks */
+#define ER_IRQ_PENDING(p)       ((p) & 0x1)
+/* bits 2:31 need to be preserved */
+/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
+#define ER_IRQ_CLEAR(p)         ((p) & 0xfffffffe)
+#define ER_IRQ_ENABLE(p)        ((ER_IRQ_CLEAR(p)) | 0x2)
+#define ER_IRQ_DISABLE(p)       ((ER_IRQ_CLEAR(p)) & ~(0x2))
+
+/* irq_control bitmasks */
+/* Minimum interval between interrupts (in 250ns intervals).  The interval
+ * between interrupts will be longer if there are no events on the event ring.
+ * Default is 4000 (1 ms).
+ */
+#define ER_IRQ_INTERVAL_MASK    (0xffff)
+/* Counter used to count down the time to the next interrupt - HW use only */
+#define ER_IRQ_COUNTER_MASK     (0xffff << 16)
+
+/* erst_size bitmasks */
+/* Preserve bits 16:31 of erst_size */
+#define ERST_SIZE_MASK          (0xffff << 16)
+
+/* erst_dequeue bitmasks */
+/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
+ * where the current dequeue pointer lies.  This is an optional HW hint.
+ */
+#define ERST_DESI_MASK          (0x7)
+/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
+ * a work queue (or delayed service routine)?
+ */
+#define ERST_EHB                (1 << 3)
+#define ERST_PTR_MASK           (0xf)
+
+/**
+ * struct xhci_run_regs
+ * @microframe_index:
+ *              MFINDEX - current microframe number
+ *
+ * Section 5.5 Host Controller Runtime Registers:
+ * "Software should read and write these registers using only Dword (32 bit)
+ * or larger accesses"
+ */
+struct xhci_run_regs {
+        u32                     microframe_index;
+        u32                     rsvd[7];
+        struct xhci_intr_reg    ir_set[128];
+};
+
+/**
+ * struct doorbell_array
+ *
+ * Section 5.6
+ */
+struct xhci_doorbell_array {
+        u32     doorbell[256];
+};
+
+#define DB_TARGET_MASK          0xFFFFFF00
+#define DB_STREAM_ID_MASK       0x0000FFFF
+#define DB_TARGET_HOST          0x0
+#define DB_STREAM_ID_HOST       0x0
+#define DB_MASK                 (0xff << 8)
+
+/* Endpoint Target - bits 0:7 */
+#define EPI_TO_DB(p)            (((p) + 1) & 0xff)
+
+
+/**
+ * struct xhci_slot_ctx
+ * @dev_info:   Route string, device speed, hub info, and last valid endpoint
+ * @dev_info2:  Max exit latency for device number, root hub port number
+ * @tt_info:    tt_info is used to construct split transaction tokens
+ * @dev_state:  slot state and device address
+ *
+ * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
+ * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
+ * reserved at the end of the slot context for HC internal use.
+ */
+struct xhci_slot_ctx {
+        u32     dev_info;
+        u32     dev_info2;
+        u32     tt_info;
+        u32     dev_state;
+        /* offset 0x10 to 0x1f reserved for HC internal use */
+        u32     reserved[4];
+};
+
+/* dev_info bitmasks */
+/* Route String - 0:19 */
+#define ROUTE_STRING_MASK       (0xfffff)
+/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
+#define DEV_SPEED       (0xf << 20)
+/* bit 24 reserved */
+/* Is this LS/FS device connected through a HS hub? - bit 25 */
+#define DEV_MTT         (0x1 << 25)
+/* Set if the device is a hub - bit 26 */
+#define DEV_HUB         (0x1 << 26)
+/* Index of the last valid endpoint context in this device context - 27:31 */
+#define LAST_CTX_MASK   (0x1f << 27)
+#define LAST_CTX(p)     ((p) << 27)
+#define LAST_CTX_TO_EP_NUM(p)   (((p) >> 27) - 1)
+#define SLOT_FLAG       (1 << 0)
+#define EP0_FLAG        (1 << 1)
+
+/* dev_info2 bitmasks */
+/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
+#define MAX_EXIT        (0xffff)
+/* Root hub port number that is needed to access the USB device */
+#define ROOT_HUB_PORT(p)        (((p) & 0xff) << 16)
+
+/* tt_info bitmasks */
+/*
+ * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
+ * The Slot ID of the hub that isolates the high speed signaling from
+ * this low or full-speed device.  '0' if attached to root hub port.
+ */
+#define TT_SLOT         (0xff)
+/*
+ * The number of the downstream facing port of the high-speed hub
+ * '0' if the device is not low or full speed.
+ */
+#define TT_PORT         (0xff << 8)
+
+/* dev_state bitmasks */
+/* USB device address - assigned by the HC */
+#define DEV_ADDR_MASK   (0xff)
+/* bits 8:26 reserved */
+/* Slot state */
+#define SLOT_STATE      (0x1f << 27)
+#define GET_SLOT_STATE(p)       (((p) & (0x1f << 27)) >> 27)
+
+
+/**
+ * struct xhci_ep_ctx
+ * @ep_info:    endpoint state, streams, mult, and interval information.
+ * @ep_info2:   information on endpoint type, max packet size, max burst size,
+ *              error count, and whether the HC will force an event for all
+ *              transactions.
+ * @deq:        64-bit ring dequeue pointer address.  If the endpoint only
+ *              defines one stream, this points to the endpoint transfer ring.
+ *              Otherwise, it points to a stream context array, which has a
+ *              ring pointer for each flow.
+ * @tx_info:
+ *              Average TRB lengths for the endpoint ring and
+ *              max payload within an Endpoint Service Interval Time (ESIT).
+ *
+ * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
+ * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
+ * reserved at the end of the endpoint context for HC internal use.
+ */
+struct xhci_ep_ctx {
+        u32     ep_info;
+        u32     ep_info2;
+        u32     deq[2];
+        u32     tx_info;
+        /* offset 0x14 - 0x1f reserved for HC internal use */
+        u32     reserved[3];
+};
+
+/* ep_info bitmasks */
+/*
+ * Endpoint State - bits 0:2
+ * 0 - disabled
+ * 1 - running
+ * 2 - halted due to halt condition - ok to manipulate endpoint ring
+ * 3 - stopped
+ * 4 - TRB error
+ * 5-7 - reserved
+ */
+#define EP_STATE_MASK           (0xf)
+#define EP_STATE_DISABLED       0
+#define EP_STATE_RUNNING        1
+#define EP_STATE_HALTED         2
+#define EP_STATE_STOPPED        3
+#define EP_STATE_ERROR          4
+/* Mult - Max number of burtst within an interval, in EP companion desc. */
+#define EP_MULT(p)              ((p & 0x3) << 8)
+/* bits 10:14 are Max Primary Streams */
+/* bit 15 is Linear Stream Array */
+/* Interval - period between requests to an endpoint - 125u increments. */
+#define EP_INTERVAL(p)          ((p & 0xff) << 16)
+
+/* ep_info2 bitmasks */
+/*
+ * Force Event - generate transfer events for all TRBs for this endpoint
+ * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
+ */
+#define FORCE_EVENT     (0x1)
+#define ERROR_COUNT(p)  (((p) & 0x3) << 1)
+#define EP_TYPE(p)      ((p) << 3)
+#define ISOC_OUT_EP     1
+#define BULK_OUT_EP     2
+#define INT_OUT_EP      3
+#define CTRL_EP         4
+#define ISOC_IN_EP      5
+#define BULK_IN_EP      6
+#define INT_IN_EP       7
+/* bit 6 reserved */
+/* bit 7 is Host Initiate Disable - for disabling stream selection */
+#define MAX_BURST(p)    (((p)&0xff) << 8)
+#define MAX_PACKET(p)   (((p)&0xffff) << 16)
+
+
+/**
+ * struct xhci_device_control
+ * Input/Output context; see section 6.2.5.
+ *
+ * @drop_context:       set the bit of the endpoint context you want to disable
+ * @add_context:        set the bit of the endpoint context you want to enable
+ */
+struct xhci_device_control {
+        u32     drop_flags;
+        u32     add_flags;
+        u32     rsvd[6];
+        struct xhci_slot_ctx    slot;
+        struct xhci_ep_ctx      ep[31];
+};
+
+/* drop context bitmasks */
+#define DROP_EP(x)      (0x1 << x)
+/* add context bitmasks */
+#define ADD_EP(x)       (0x1 << x)
+
+
+struct xhci_virt_device {
+        /*
+         * Commands to the hardware are passed an "input context" that
+         * tells the hardware what to change in its data structures.
+         * The hardware will return changes in an "output context" that
+         * software must allocate for the hardware.  We need to keep
+         * track of input and output contexts separately because
+         * these commands might fail and we don't trust the hardware.
+         */
+        struct xhci_device_control      *out_ctx;
+        dma_addr_t                      out_ctx_dma;
+        /* Used for addressing devices and configuration changes */
+        struct xhci_device_control      *in_ctx;
+        dma_addr_t                      in_ctx_dma;
+        /* FIXME when stream support is added */
+        struct xhci_ring                *ep_rings[31];
+        /* Temporary storage in case the configure endpoint command fails and we
+         * have to restore the device state to the previous state
+         */
+        struct xhci_ring                *new_ep_rings[31];
+        struct completion               cmd_completion;
+        /* Status of the last command issued for this device */
+        u32                             cmd_status;
+};
+
+
+/**
+ * struct xhci_device_context_array
+ * @dev_context_ptr     array of 64-bit DMA addresses for device contexts
+ */
+struct xhci_device_context_array {
+        /* 64-bit device addresses; we only write 32-bit addresses */
+        u32                     dev_context_ptrs[2*MAX_HC_SLOTS];
+        /* private xHCD pointers */
+        dma_addr_t      dma;
+};
+/* TODO: write function to set the 64-bit device DMA address */
+/*
+ * TODO: change this to be dynamically sized at HC mem init time since the HC
+ * might not be able to handle the maximum number of devices possible.
+ */
+
+
+struct xhci_stream_ctx {
+        /* 64-bit stream ring address, cycle state, and stream type */
+        u32     stream_ring[2];
+        /* offset 0x14 - 0x1f reserved for HC internal use */
+        u32     reserved[2];
+};
+
+
+struct xhci_transfer_event {
+        /* 64-bit buffer address, or immediate data */
+        u32     buffer[2];
+        u32     transfer_len;
+        /* This field is interpreted differently based on the type of TRB */
+        u32     flags;
+};
+
+/** Transfer Event bit fields **/
+#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
+
+/* Completion Code - only applicable for some types of TRBs */
+#define COMP_CODE_MASK          (0xff << 24)
+#define GET_COMP_CODE(p)        (((p) & COMP_CODE_MASK) >> 24)
+#define COMP_SUCCESS    1
+/* Data Buffer Error */
+#define COMP_DB_ERR     2
+/* Babble Detected Error */
+#define COMP_BABBLE     3
+/* USB Transaction Error */
+#define COMP_TX_ERR     4
+/* TRB Error - some TRB field is invalid */
+#define COMP_TRB_ERR    5
+/* Stall Error - USB device is stalled */
+#define COMP_STALL      6
+/* Resource Error - HC doesn't have memory for that device configuration */
+#define COMP_ENOMEM     7
+/* Bandwidth Error - not enough room in schedule for this dev config */
+#define COMP_BW_ERR     8
+/* No Slots Available Error - HC ran out of device slots */
+#define COMP_ENOSLOTS   9
+/* Invalid Stream Type Error */
+#define COMP_STREAM_ERR 10
+/* Slot Not Enabled Error - doorbell rung for disabled device slot */
+#define COMP_EBADSLT    11
+/* Endpoint Not Enabled Error */
+#define COMP_EBADEP     12
+/* Short Packet */
+#define COMP_SHORT_TX   13
+/* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
+#define COMP_UNDERRUN   14
+/* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
+#define COMP_OVERRUN    15
+/* Virtual Function Event Ring Full Error */
+#define COMP_VF_FULL    16
+/* Parameter Error - Context parameter is invalid */
+#define COMP_EINVAL     17
+/* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
+#define COMP_BW_OVER    18
+/* Context State Error - illegal context state transition requested */
+#define COMP_CTX_STATE  19
+/* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
+#define COMP_PING_ERR   20
+/* Event Ring is full */
+#define COMP_ER_FULL    21
+/* Missed Service Error - HC couldn't service an isoc ep within interval */
+#define COMP_MISSED_INT 23
+/* Successfully stopped command ring */
+#define COMP_CMD_STOP   24
+/* Successfully aborted current command and stopped command ring */
+#define COMP_CMD_ABORT  25
+/* Stopped - transfer was terminated by a stop endpoint command */
+#define COMP_STOP       26
+/* Same as COMP_EP_STOPPED, but the transfered length in the event is invalid */
+#define COMP_STOP_INVAL 27
+/* Control Abort Error - Debug Capability - control pipe aborted */
+#define COMP_DBG_ABORT  28
+/* TRB type 29 and 30 reserved */
+/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
+#define COMP_BUFF_OVER  31
+/* Event Lost Error - xHC has an "internal event overrun condition" */
+#define COMP_ISSUES     32
+/* Undefined Error - reported when other error codes don't apply */
+#define COMP_UNKNOWN    33
+/* Invalid Stream ID Error */
+#define COMP_STRID_ERR  34
+/* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
+/* FIXME - check for this */
+#define COMP_2ND_BW_ERR 35
+/* Split Transaction Error */
+#define COMP_SPLIT_ERR  36
+
+struct xhci_link_trb {
+        /* 64-bit segment pointer*/
+        u32 segment_ptr[2];
+        u32 intr_target;
+        u32 control;
+};
+
+/* control bitfields */
+#define LINK_TOGGLE     (0x1<<1)
+
+/* Command completion event TRB */
+struct xhci_event_cmd {
+        /* Pointer to command TRB, or the value passed by the event data trb */
+        u32 cmd_trb[2];
+        u32 status;
+        u32 flags;
+};
+
+/* flags bitmasks */
+/* bits 16:23 are the virtual function ID */
+/* bits 24:31 are the slot ID */
+#define TRB_TO_SLOT_ID(p)       (((p) & (0xff<<24)) >> 24)
+#define SLOT_ID_FOR_TRB(p)      (((p) & 0xff) << 24)
+
+/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
+#define TRB_TO_EP_INDEX(p)              ((((p) & (0x1f << 16)) >> 16) - 1)
+#define EP_ID_FOR_TRB(p)                ((((p) + 1) & 0x1f) << 16)
+
+
+/* Port Status Change Event TRB fields */
+/* Port ID - bits 31:24 */
+#define GET_PORT_ID(p)          (((p) & (0xff << 24)) >> 24)
+
+/* Normal TRB fields */
+/* transfer_len bitmasks - bits 0:16 */
+#define TRB_LEN(p)              ((p) & 0x1ffff)
+/* TD size - number of bytes remaining in the TD (including this TRB):
+ * bits 17 - 21.  Shift the number of bytes by 10. */
+#define TD_REMAINDER(p)         ((((p) >> 10) & 0x1f) << 17)
+/* Interrupter Target - which MSI-X vector to target the completion event at */
+#define TRB_INTR_TARGET(p)      (((p) & 0x3ff) << 22)
+#define GET_INTR_TARGET(p)      (((p) >> 22) & 0x3ff)
+
+/* Cycle bit - indicates TRB ownership by HC or HCD */
+#define TRB_CYCLE               (1<<0)
+/*
+ * Force next event data TRB to be evaluated before task switch.
+ * Used to pass OS data back after a TD completes.
+ */
+#define TRB_ENT                 (1<<1)
+/* Interrupt on short packet */
+#define TRB_ISP                 (1<<2)
+/* Set PCIe no snoop attribute */
+#define TRB_NO_SNOOP            (1<<3)
+/* Chain multiple TRBs into a TD */
+#define TRB_CHAIN               (1<<4)
+/* Interrupt on completion */
+#define TRB_IOC                 (1<<5)
+/* The buffer pointer contains immediate data */
+#define TRB_IDT                 (1<<6)
+
+
+/* Control transfer TRB specific fields */
+#define TRB_DIR_IN              (1<<16)
+
+struct xhci_generic_trb {
+        u32 field[4];
+};
+
+union xhci_trb {
+        struct xhci_link_trb            link;
+        struct xhci_transfer_event      trans_event;
+        struct xhci_event_cmd           event_cmd;
+        struct xhci_generic_trb         generic;
+};
+
+/* TRB bit mask */
+#define TRB_TYPE_BITMASK        (0xfc00)
+#define TRB_TYPE(p)             ((p) << 10)
+/* TRB type IDs */
+/* bulk, interrupt, isoc scatter/gather, and control data stage */
+#define TRB_NORMAL              1
+/* setup stage for control transfers */
+#define TRB_SETUP               2
+/* data stage for control transfers */
+#define TRB_DATA                3
+/* status stage for control transfers */
+#define TRB_STATUS              4
+/* isoc transfers */
+#define TRB_ISOC                5
+/* TRB for linking ring segments */
+#define TRB_LINK                6
+#define TRB_EVENT_DATA          7
+/* Transfer Ring No-op (not for the command ring) */
+#define TRB_TR_NOOP             8
+/* Command TRBs */
+/* Enable Slot Command */
+#define TRB_ENABLE_SLOT         9
+/* Disable Slot Command */
+#define TRB_DISABLE_SLOT        10
+/* Address Device Command */
+#define TRB_ADDR_DEV            11
+/* Configure Endpoint Command */
+#define TRB_CONFIG_EP           12
+/* Evaluate Context Command */
+#define TRB_EVAL_CONTEXT        13
+/* Reset Transfer Ring Command */
+#define TRB_RESET_RING          14
+/* Stop Transfer Ring Command */
+#define TRB_STOP_RING           15
+/* Set Transfer Ring Dequeue Pointer Command */
+#define TRB_SET_DEQ             16
+/* Reset Device Command */
+#define TRB_RESET_DEV           17
+/* Force Event Command (opt) */
+#define TRB_FORCE_EVENT         18
+/* Negotiate Bandwidth Command (opt) */
+#define TRB_NEG_BANDWIDTH       19
+/* Set Latency Tolerance Value Command (opt) */
+#define TRB_SET_LT              20
+/* Get port bandwidth Command */
+#define TRB_GET_BW              21
+/* Force Header Command - generate a transaction or link management packet */
+#define TRB_FORCE_HEADER        22
+/* No-op Command - not for transfer rings */
+#define TRB_CMD_NOOP            23
+/* TRB IDs 24-31 reserved */
+/* Event TRBS */
+/* Transfer Event */
+#define TRB_TRANSFER            32
+/* Command Completion Event */
+#define TRB_COMPLETION          33
+/* Port Status Change Event */
+#define TRB_PORT_STATUS         34
+/* Bandwidth Request Event (opt) */
+#define TRB_BANDWIDTH_EVENT     35
+/* Doorbell Event (opt) */
+#define TRB_DOORBELL            36
+/* Host Controller Event */
+#define TRB_HC_EVENT            37
+/* Device Notification Event - device sent function wake notification */
+#define TRB_DEV_NOTE            38
+/* MFINDEX Wrap Event - microframe counter wrapped */
+#define TRB_MFINDEX_WRAP        39
+/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
+
+/*
+ * TRBS_PER_SEGMENT must be a multiple of 4,
+ * since the command ring is 64-byte aligned.
+ * It must also be greater than 16.
+ */
+#define TRBS_PER_SEGMENT        64
+#define SEGMENT_SIZE            (TRBS_PER_SEGMENT*16)
+/* TRB buffer pointers can't cross 64KB boundaries */
+#define TRB_MAX_BUFF_SHIFT              16
+#define TRB_MAX_BUFF_SIZE       (1 << TRB_MAX_BUFF_SHIFT)
+
+struct xhci_segment {
+        union xhci_trb          *trbs;
+        /* private to HCD */
+        struct xhci_segment     *next;
+        dma_addr_t              dma;
+};
+
+struct xhci_td {
+        struct list_head        td_list;
+        struct list_head        cancelled_td_list;
+        struct urb              *urb;
+        struct xhci_segment     *start_seg;
+        union xhci_trb          *first_trb;
+        union xhci_trb          *last_trb;
+};
+
+struct xhci_ring {
+        struct xhci_segment     *first_seg;
+        union  xhci_trb         *enqueue;
+        struct xhci_segment     *enq_seg;
+        unsigned int            enq_updates;
+        union  xhci_trb         *dequeue;
+        struct xhci_segment     *deq_seg;
+        unsigned int            deq_updates;
+        struct list_head        td_list;
+        /* ----  Related to URB cancellation ---- */
+        struct list_head        cancelled_td_list;
+        unsigned int            cancels_pending;
+        unsigned int            state;
+#define SET_DEQ_PENDING         (1 << 0)
+        /* The TRB that was last reported in a stopped endpoint ring */
+        union xhci_trb          *stopped_trb;
+        struct xhci_td          *stopped_td;
+        /*
+         * Write the cycle state into the TRB cycle field to give ownership of
+         * the TRB to the host controller (if we are the producer), or to check
+         * if we own the TRB (if we are the consumer).  See section 4.9.1.
+         */
+        u32                     cycle_state;
+};
+
+struct xhci_erst_entry {
+        /* 64-bit event ring segment address */
+        u32     seg_addr[2];
+        u32     seg_size;
+        /* Set to zero */
+        u32     rsvd;
+};
+
+struct xhci_erst {
+        struct xhci_erst_entry  *entries;
+        unsigned int            num_entries;
+        /* xhci->event_ring keeps track of segment dma addresses */
+        dma_addr_t              erst_dma_addr;
+        /* Num entries the ERST can contain */
+        unsigned int            erst_size;
+};
+
+/*
+ * Each segment table entry is 4*32bits long.  1K seems like an ok size:
+ * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
+ * meaning 64 ring segments.
+ * Initial allocated size of the ERST, in number of entries */
+#define ERST_NUM_SEGS   1
+/* Initial allocated size of the ERST, in number of entries */
+#define ERST_SIZE       64
+/* Initial number of event segment rings allocated */
+#define ERST_ENTRIES    1
+/* Poll every 60 seconds */
+#define POLL_TIMEOUT    60
+/* XXX: Make these module parameters */
+
+
+/* There is one ehci_hci structure per controller */
+struct xhci_hcd {
+        /* glue to PCI and HCD framework */
+        struct xhci_cap_regs __iomem *cap_regs;
+        struct xhci_op_regs __iomem *op_regs;
+        struct xhci_run_regs __iomem *run_regs;
+        struct xhci_doorbell_array __iomem *dba;
+        /* Our HCD's current interrupter register set */
+        struct  xhci_intr_reg __iomem *ir_set;
+
+        /* Cached register copies of read-only HC data */
+        __u32           hcs_params1;
+        __u32           hcs_params2;
+        __u32           hcs_params3;
+        __u32           hcc_params;
+
+        spinlock_t      lock;
+
+        /* packed release number */
+        u8              sbrn;
+        u16             hci_version;
+        u8              max_slots;
+        u8              max_interrupters;
+        u8              max_ports;
+        u8              isoc_threshold;
+        int             event_ring_max;
+        int             addr_64;
+        /* 4KB min, 128MB max */
+        int             page_size;
+        /* Valid values are 12 to 20, inclusive */
+        int             page_shift;
+        /* only one MSI vector for now, but might need more later */
+        int             msix_count;
+        struct msix_entry       *msix_entries;
+        /* data structures */
+        struct xhci_device_context_array *dcbaa;
+        struct xhci_ring        *cmd_ring;
+        struct xhci_ring        *event_ring;
+        struct xhci_erst        erst;
+        /* slot enabling and address device helpers */
+        struct completion       addr_dev;
+        int slot_id;
+        /* Internal mirror of the HW's dcbaa */
+        struct xhci_virt_device *devs[MAX_HC_SLOTS];
+
+        /* DMA pools */
+        struct dma_pool *device_pool;
+        struct dma_pool *segment_pool;
+
+#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
+        /* Poll the rings - for debugging */
+        struct timer_list       event_ring_timer;
+        int                     zombie;
+#endif
+        /* Statistics */
+        int                     noops_submitted;
+        int                     noops_handled;
+        int                     error_bitmask;
+};
+
+/* For testing purposes */
+#define NUM_TEST_NOOPS  0
+
+/* convert between an HCD pointer and the corresponding EHCI_HCD */
+static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
+{
+        return (struct xhci_hcd *) (hcd->hcd_priv);
+}
+
+static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
+{
+        return container_of((void *) xhci, struct usb_hcd, hcd_priv);
+}
+
+#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
+#define XHCI_DEBUG      1
+#else
+#define XHCI_DEBUG      0
+#endif
+
+#define xhci_dbg(xhci, fmt, args...) \
+        do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
+#define xhci_info(xhci, fmt, args...) \
+        do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
+#define xhci_err(xhci, fmt, args...) \
+        dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
+#define xhci_warn(xhci, fmt, args...) \
+        dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
+
+/* TODO: copied from ehci.h - can be refactored? */
+/* xHCI spec says all registers are little endian */
+static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
+                __u32 __iomem *regs)
+{
+        return readl(regs);
+}
+static inline void xhci_writel(struct xhci_hcd *xhci,
+                const unsigned int val, __u32 __iomem *regs)
+{
+        if (!in_interrupt())
+                xhci_dbg(xhci,
+                         "`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
+                         regs, val);
+        writel(val, regs);
+}
+
+/* xHCI debugging */
+void xhci_print_ir_set(struct xhci_hcd *xhci, struct xhci_intr_reg *ir_set, int set_num);
+void xhci_print_registers(struct xhci_hcd *xhci);
+void xhci_dbg_regs(struct xhci_hcd *xhci);
+void xhci_print_run_regs(struct xhci_hcd *xhci);
+void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
+void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
+void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
+void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
+void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
+void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
+void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
+void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_device_control *ctx, dma_addr_t dma, unsigned int last_ep);
+
+/* xHCI memory managment */
+void xhci_mem_cleanup(struct xhci_hcd *xhci);
+int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
+void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
+int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
+int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
+unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
+unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
+void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
+int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
+                struct usb_device *udev, struct usb_host_endpoint *ep,
+                gfp_t mem_flags);
+void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
+
+#ifdef CONFIG_PCI
+/* xHCI PCI glue */
+int xhci_register_pci(void);
+void xhci_unregister_pci(void);
+#endif
+
+/* xHCI host controller glue */
+int xhci_halt(struct xhci_hcd *xhci);
+int xhci_reset(struct xhci_hcd *xhci);
+int xhci_init(struct usb_hcd *hcd);
+int xhci_run(struct usb_hcd *hcd);
+void xhci_stop(struct usb_hcd *hcd);
+void xhci_shutdown(struct usb_hcd *hcd);
+int xhci_get_frame(struct usb_hcd *hcd);
+irqreturn_t xhci_irq(struct usb_hcd *hcd);
+int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
+void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
+int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
+int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
+int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
+int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
+int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
+int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
+void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
+
+/* xHCI ring, segment, TRB, and TD functions */
+dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
+void xhci_ring_cmd_db(struct xhci_hcd *xhci);
+void *xhci_setup_one_noop(struct xhci_hcd *xhci);
+void xhci_handle_event(struct xhci_hcd *xhci);
+void xhci_set_hc_event_deq(struct xhci_hcd *xhci);
+int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
+int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
+                u32 slot_id);
+int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
+                unsigned int ep_index);
+int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
+                int slot_id, unsigned int ep_index);
+int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
+                int slot_id, unsigned int ep_index);
+int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
+                u32 slot_id);
+
+/* xHCI roothub code */
+int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
+                char *buf, u16 wLength);
+int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
+
+#endif /* __LINUX_XHCI_HCD_H */
diff --git a/drivers/usb/misc/iowarrior.c b/drivers/usb/misc/iowarrior.c
index a4ef77ef917d..3c5fe5cee05a 100644
--- a/drivers/usb/misc/iowarrior.c
+++ b/drivers/usb/misc/iowarrior.c
@@ -726,12 +726,18 @@ static const struct file_operations iowarrior_fops = {
         .poll = iowarrior_poll,
 };
 
+static char *iowarrior_nodename(struct device *dev)
+{
+        return kasprintf(GFP_KERNEL, "usb/%s", dev_name(dev));
+}
+
 /*
  * usb class driver info in order to get a minor number from the usb core,
  * and to have the device registered with devfs and the driver core
  */
 static struct usb_class_driver iowarrior_class = {
         .name = "iowarrior%d",
+        .nodename = iowarrior_nodename,
         .fops = &iowarrior_fops,
         .minor_base = IOWARRIOR_MINOR_BASE,
 };
diff --git a/drivers/usb/misc/legousbtower.c b/drivers/usb/misc/legousbtower.c
index ab0f3226158b..c1e2433f640d 100644
--- a/drivers/usb/misc/legousbtower.c
+++ b/drivers/usb/misc/legousbtower.c
@@ -266,12 +266,18 @@ static const struct file_operations tower_fops = {
         .llseek =       tower_llseek,
 };
 
+static char *legousbtower_nodename(struct device *dev)
+{
+        return kasprintf(GFP_KERNEL, "usb/%s", dev_name(dev));
+}
+
 /*
  * usb class driver info in order to get a minor number from the usb core,
  * and to have the device registered with the driver core
  */
 static struct usb_class_driver tower_class = {
         .name =         "legousbtower%d",
+        .nodename =     legousbtower_nodename,
         .fops =         &tower_fops,
         .minor_base =   LEGO_USB_TOWER_MINOR_BASE,
 };
diff --git a/drivers/usb/misc/sisusbvga/Kconfig b/drivers/usb/misc/sisusbvga/Kconfig
index 7603cbe0865d..30ea7ca6846e 100644
--- a/drivers/usb/misc/sisusbvga/Kconfig
+++ b/drivers/usb/misc/sisusbvga/Kconfig
@@ -1,7 +1,7 @@
 
 config USB_SISUSBVGA
         tristate "USB 2.0 SVGA dongle support (Net2280/SiS315)"
-        depends on USB && USB_EHCI_HCD
+        depends on USB && (USB_MUSB_HDRC || USB_EHCI_HCD)
         ---help---
           Say Y here if you intend to attach a USB2VGA dongle based on a
           Net2280 and a SiS315 chip.
diff --git a/drivers/usb/misc/usbtest.c b/drivers/usb/misc/usbtest.c
index 5f1a19d1497d..a9f06d76960f 100644
--- a/drivers/usb/misc/usbtest.c
+++ b/drivers/usb/misc/usbtest.c
@@ -1072,23 +1072,34 @@ static int unlink1 (struct usbtest_dev *dev, int pipe, int size, int async)
          */
         msleep (jiffies % (2 * INTERRUPT_RATE));
         if (async) {
-retry:
-                retval = usb_unlink_urb (urb);
-                if (retval == -EBUSY || retval == -EIDRM) {
-                        /* we can't unlink urbs while they're completing.
-                         * or if they've completed, and we haven't resubmitted.
-                         * "normal" drivers would prevent resubmission, but
-                         * since we're testing unlink paths, we can't.
-                         */
-                        ERROR(dev,  "unlink retry\n");
-                        goto retry;
+                while (!completion_done(&completion)) {
+                        retval = usb_unlink_urb(urb);
+
+                        switch (retval) {
+                        case -EBUSY:
+                        case -EIDRM:
+                                /* we can't unlink urbs while they're completing
+                                 * or if they've completed, and we haven't
+                                 * resubmitted. "normal" drivers would prevent
+                                 * resubmission, but since we're testing unlink
+                                 * paths, we can't.
+                                 */
+                                ERROR(dev, "unlink retry\n");
+                                continue;
+                        case 0:
+                        case -EINPROGRESS:
+                                break;
+
+                        default:
+                                dev_err(&dev->intf->dev,
+                                        "unlink fail %d\n", retval);
+                                return retval;
+                        }
+
+                        break;
                 }
         } else
                 usb_kill_urb (urb);
-        if (!(retval == 0 || retval == -EINPROGRESS)) {
-                dev_err(&dev->intf->dev, "unlink fail %d\n", retval);
-                return retval;
-        }
 
         wait_for_completion (&completion);
         retval = urb->status;
diff --git a/drivers/usb/mon/mon_text.c b/drivers/usb/mon/mon_text.c
index 1f715436d6d3..a7eb4c99342c 100644
--- a/drivers/usb/mon/mon_text.c
+++ b/drivers/usb/mon/mon_text.c
@@ -733,7 +733,7 @@ int __init mon_text_init(void)
 {
         struct dentry *mondir;
 
-        mondir = debugfs_create_dir("usbmon", NULL);
+        mondir = debugfs_create_dir("usbmon", usb_debug_root);
         if (IS_ERR(mondir)) {
                 printk(KERN_NOTICE TAG ": debugfs is not available\n");
                 return -ENODEV;
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index b66e8544d8b9..70073b157f0a 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -10,6 +10,7 @@ comment "Enable Host or Gadget support to see Inventra options"
 config USB_MUSB_HDRC
         depends on (USB || USB_GADGET) && HAVE_CLK
         depends on !SUPERH
+        select NOP_USB_XCEIV if ARCH_DAVINCI
         select TWL4030_USB if MACH_OMAP_3430SDP
         select USB_OTG_UTILS
         tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
@@ -55,6 +56,7 @@ comment "Blackfin high speed USB Support"
 config USB_TUSB6010
         boolean "TUSB 6010 support"
         depends on USB_MUSB_HDRC && !USB_MUSB_SOC
+        select NOP_USB_XCEIV
         default y
         help
           The TUSB 6010 chip, from Texas Instruments, connects a discrete
diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
index 786134852092..f2f66ebc7362 100644
--- a/drivers/usb/musb/blackfin.c
+++ b/drivers/usb/musb/blackfin.c
@@ -143,7 +143,7 @@ static void musb_conn_timer_handler(unsigned long _musb)
         u16 val;
 
         spin_lock_irqsave(&musb->lock, flags);
-        switch (musb->xceiv.state) {
+        switch (musb->xceiv->state) {
         case OTG_STATE_A_IDLE:
         case OTG_STATE_A_WAIT_BCON:
                 /* Start a new session */
@@ -154,7 +154,7 @@ static void musb_conn_timer_handler(unsigned long _musb)
                 val = musb_readw(musb->mregs, MUSB_DEVCTL);
                 if (!(val & MUSB_DEVCTL_BDEVICE)) {
                         gpio_set_value(musb->config->gpio_vrsel, 1);
-                        musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
+                        musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
                 } else {
                         gpio_set_value(musb->config->gpio_vrsel, 0);
 
@@ -247,6 +247,11 @@ int __init musb_platform_init(struct musb *musb)
         }
         gpio_direction_output(musb->config->gpio_vrsel, 0);
 
+        usb_nop_xceiv_register();
+        musb->xceiv = otg_get_transceiver();
+        if (!musb->xceiv)
+                return -ENODEV;
+
         if (ANOMALY_05000346) {
                 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
                 SSYNC();
@@ -291,7 +296,7 @@ int __init musb_platform_init(struct musb *musb)
                         musb_conn_timer_handler, (unsigned long) musb);
         }
         if (is_peripheral_enabled(musb))
-                musb->xceiv.set_power = bfin_set_power;
+                musb->xceiv->set_power = bfin_set_power;
 
         musb->isr = blackfin_interrupt;
 
diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
index 1976e9b41800..c3577bbbae6c 100644
--- a/drivers/usb/musb/cppi_dma.c
+++ b/drivers/usb/musb/cppi_dma.c
@@ -6,6 +6,7 @@
  * The TUSB6020, using VLYNQ, has CPPI that looks much like DaVinci.
  */
 
+#include <linux/platform_device.h>
 #include <linux/usb.h>
 
 #include "musb_core.h"
@@ -1145,17 +1146,27 @@ static bool cppi_rx_scan(struct cppi *cppi, unsigned ch)
         return completed;
 }
 
-void cppi_completion(struct musb *musb, u32 rx, u32 tx)
+irqreturn_t cppi_interrupt(int irq, void *dev_id)
 {
-        void __iomem            *tibase;
-        int                     i, index;
+        struct musb             *musb = dev_id;
         struct cppi             *cppi;
+        void __iomem            *tibase;
         struct musb_hw_ep       *hw_ep = NULL;
+        u32                     rx, tx;
+        int                     i, index;
 
         cppi = container_of(musb->dma_controller, struct cppi, controller);
 
         tibase = musb->ctrl_base;
 
+        tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
+        rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
+
+        if (!tx && !rx)
+                return IRQ_NONE;
+
+        DBG(4, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
+
         /* process TX channels */
         for (index = 0; tx; tx = tx >> 1, index++) {
                 struct cppi_channel             *tx_ch;
@@ -1273,6 +1284,8 @@ void cppi_completion(struct musb *musb, u32 rx, u32 tx)
 
         /* write to CPPI EOI register to re-enable interrupts */
         musb_writel(tibase, DAVINCI_CPPI_EOI_REG, 0);
+
+        return IRQ_HANDLED;
 }
 
 /* Instantiate a software object representing a DMA controller. */
@@ -1280,6 +1293,9 @@ struct dma_controller *__init
 dma_controller_create(struct musb *musb, void __iomem *mregs)
 {
         struct cppi             *controller;
+        struct device           *dev = musb->controller;
+        struct platform_device  *pdev = to_platform_device(dev);
+        int                     irq = platform_get_irq(pdev, 1);
 
         controller = kzalloc(sizeof *controller, GFP_KERNEL);
         if (!controller)
@@ -1310,6 +1326,15 @@ dma_controller_create(struct musb *musb, void __iomem *mregs)
                 return NULL;
         }
 
+        if (irq > 0) {
+                if (request_irq(irq, cppi_interrupt, 0, "cppi-dma", musb)) {
+                        dev_err(dev, "request_irq %d failed!\n", irq);
+                        dma_controller_destroy(&controller->controller);
+                        return NULL;
+                }
+                controller->irq = irq;
+        }
+
         return &controller->controller;
 }
 
@@ -1322,6 +1347,9 @@ void dma_controller_destroy(struct dma_controller *c)
 
         cppi = container_of(c, struct cppi, controller);
 
+        if (cppi->irq)
+                free_irq(cppi->irq, cppi->musb);
+
         /* assert:  caller stopped the controller first */
         dma_pool_destroy(cppi->pool);
 
diff --git a/drivers/usb/musb/cppi_dma.h b/drivers/usb/musb/cppi_dma.h
index 729b4071787b..8a39de3e6e47 100644
--- a/drivers/usb/musb/cppi_dma.h
+++ b/drivers/usb/musb/cppi_dma.h
@@ -119,6 +119,8 @@ struct cppi {
         void __iomem                    *mregs;         /* Mentor regs */
         void __iomem                    *tibase;        /* TI/CPPI regs */
 
+        int                             irq;
+
         struct cppi_channel             tx[4];
         struct cppi_channel             rx[4];
 
@@ -127,7 +129,7 @@ struct cppi {
         struct list_head                tx_complete;
 };
 
-/* irq handling hook */
-extern void cppi_completion(struct musb *, u32 rx, u32 tx);
+/* CPPI IRQ handler */
+extern irqreturn_t cppi_interrupt(int, void *);
 
 #endif                          /* end of ifndef _CPPI_DMA_H_ */
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index 10d11ab113ab..180d7daa4099 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -215,7 +215,7 @@ static void otg_timer(unsigned long _musb)
         DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
 
         spin_lock_irqsave(&musb->lock, flags);
-        switch (musb->xceiv.state) {
+        switch (musb->xceiv->state) {
         case OTG_STATE_A_WAIT_VFALL:
                 /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
                  * seems to mis-handle session "start" otherwise (or in our
@@ -226,7 +226,7 @@ static void otg_timer(unsigned long _musb)
                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
                         break;
                 }
-                musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
+                musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
                 musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
                         MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
                 break;
@@ -251,7 +251,7 @@ static void otg_timer(unsigned long _musb)
                 if (devctl & MUSB_DEVCTL_BDEVICE)
                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
                 else
-                        musb->xceiv.state = OTG_STATE_A_IDLE;
+                        musb->xceiv->state = OTG_STATE_A_IDLE;
                 break;
         default:
                 break;
@@ -265,6 +265,7 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
         irqreturn_t     retval = IRQ_NONE;
         struct musb     *musb = __hci;
         void __iomem    *tibase = musb->ctrl_base;
+        struct cppi     *cppi;
         u32             tmp;
 
         spin_lock_irqsave(&musb->lock, flags);
@@ -281,16 +282,9 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
         /* CPPI interrupts share the same IRQ line, but have their own
          * mask, state, "vector", and EOI registers.
          */
-        if (is_cppi_enabled()) {
-                u32 cppi_tx = musb_readl(tibase, DAVINCI_TXCPPI_MASKED_REG);
-                u32 cppi_rx = musb_readl(tibase, DAVINCI_RXCPPI_MASKED_REG);
-
-                if (cppi_tx || cppi_rx) {
-                        DBG(4, "CPPI IRQ t%x r%x\n", cppi_tx, cppi_rx);
-                        cppi_completion(musb, cppi_rx, cppi_tx);
-                        retval = IRQ_HANDLED;
-                }
-        }
+        cppi = container_of(musb->dma_controller, struct cppi, controller);
+        if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
+                retval = cppi_interrupt(irq, __hci);
 
         /* ack and handle non-CPPI interrupts */
         tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
@@ -331,21 +325,21 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
                          * to stop registering in devctl.
                          */
                         musb->int_usb &= ~MUSB_INTR_VBUSERROR;
-                        musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
+                        musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
                         WARNING("VBUS error workaround (delay coming)\n");
                 } else if (is_host_enabled(musb) && drvvbus) {
                         musb->is_active = 1;
                         MUSB_HST_MODE(musb);
-                        musb->xceiv.default_a = 1;
-                        musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
+                        musb->xceiv->default_a = 1;
+                        musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
                         portstate(musb->port1_status |= USB_PORT_STAT_POWER);
                         del_timer(&otg_workaround);
                 } else {
                         musb->is_active = 0;
                         MUSB_DEV_MODE(musb);
-                        musb->xceiv.default_a = 0;
-                        musb->xceiv.state = OTG_STATE_B_IDLE;
+                        musb->xceiv->default_a = 0;
+                        musb->xceiv->state = OTG_STATE_B_IDLE;
                         portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
                 }
 
@@ -367,17 +361,12 @@ static irqreturn_t davinci_interrupt(int irq, void *__hci)
 
         /* poll for ID change */
         if (is_otg_enabled(musb)
-                        && musb->xceiv.state == OTG_STATE_B_IDLE)
+                        && musb->xceiv->state == OTG_STATE_B_IDLE)
                 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 
         spin_unlock_irqrestore(&musb->lock, flags);
 
-        /* REVISIT we sometimes get unhandled IRQs
-         * (e.g. ep0).  not clear why...
-         */
-        if (retval != IRQ_HANDLED)
-                DBG(5, "unhandled? %08x\n", tmp);
-        return IRQ_HANDLED;
+        return retval;
 }
 
 int musb_platform_set_mode(struct musb *musb, u8 mode)
@@ -391,6 +380,11 @@ int __init musb_platform_init(struct musb *musb)
         void __iomem    *tibase = musb->ctrl_base;
         u32             revision;
 
+        usb_nop_xceiv_register();
+        musb->xceiv = otg_get_transceiver();
+        if (!musb->xceiv)
+                return -ENODEV;
+
         musb->mregs += DAVINCI_BASE_OFFSET;
 
         clk_enable(musb->clock);
@@ -398,7 +392,7 @@ int __init musb_platform_init(struct musb *musb)
         /* returns zero if e.g. not clocked */
         revision = musb_readl(tibase, DAVINCI_USB_VERSION_REG);
         if (revision == 0)
-                return -ENODEV;
+                goto fail;
 
         if (is_host_enabled(musb))
                 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
@@ -432,6 +426,10 @@ int __init musb_platform_init(struct musb *musb)
 
         musb->isr = davinci_interrupt;
         return 0;
+
+fail:
+        usb_nop_xceiv_unregister();
+        return -ENODEV;
 }
 
 int musb_platform_exit(struct musb *musb)
@@ -442,7 +440,7 @@ int musb_platform_exit(struct musb *musb)
         davinci_source_power(musb, 0 /*off*/, 1);
 
         /* delay, to avoid problems with module reload */
-        if (is_host_enabled(musb) && musb->xceiv.default_a) {
+        if (is_host_enabled(musb) && musb->xceiv->default_a) {
                 int     maxdelay = 30;
                 u8      devctl, warn = 0;
 
@@ -471,5 +469,7 @@ int musb_platform_exit(struct musb *musb)
 
         clk_disable(musb->clock);
 
+        usb_nop_xceiv_unregister();
+
         return 0;
 }
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 4000cf6d1e81..554a414f65d1 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -112,6 +112,7 @@
 #include "davinci.h"
 #endif
 
+#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
 
 
 unsigned musb_debug;
@@ -267,7 +268,7 @@ void musb_load_testpacket(struct musb *musb)
 
 const char *otg_state_string(struct musb *musb)
 {
-        switch (musb->xceiv.state) {
+        switch (musb->xceiv->state) {
         case OTG_STATE_A_IDLE:          return "a_idle";
         case OTG_STATE_A_WAIT_VRISE:    return "a_wait_vrise";
         case OTG_STATE_A_WAIT_BCON:     return "a_wait_bcon";
@@ -288,12 +289,6 @@ const char *otg_state_string(struct musb *musb)
 #ifdef  CONFIG_USB_MUSB_OTG
 
 /*
- * See also USB_OTG_1-3.pdf 6.6.5 Timers
- * REVISIT: Are the other timers done in the hardware?
- */
-#define TB_ASE0_BRST            100     /* Min 3.125 ms */
-
-/*
  * Handles OTG hnp timeouts, such as b_ase0_brst
  */
 void musb_otg_timer_func(unsigned long data)
@@ -302,16 +297,18 @@ void musb_otg_timer_func(unsigned long data)
         unsigned long   flags;
 
         spin_lock_irqsave(&musb->lock, flags);
-        switch (musb->xceiv.state) {
+        switch (musb->xceiv->state) {
         case OTG_STATE_B_WAIT_ACON:
                 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
                 musb_g_disconnect(musb);
-                musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
+                musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
                 musb->is_active = 0;
                 break;
+        case OTG_STATE_A_SUSPEND:
         case OTG_STATE_A_WAIT_BCON:
-                DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
-                musb_hnp_stop(musb);
+                DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
+                musb_set_vbus(musb, 0);
+                musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
                 break;
         default:
                 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
@@ -320,10 +317,8 @@ void musb_otg_timer_func(unsigned long data)
         spin_unlock_irqrestore(&musb->lock, flags);
 }
 
-static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
-
 /*
- * Stops the B-device HNP state. Caller must take care of locking.
+ * Stops the HNP transition. Caller must take care of locking.
  */
 void musb_hnp_stop(struct musb *musb)
 {
@@ -331,20 +326,17 @@ void musb_hnp_stop(struct musb *musb)
         void __iomem    *mbase = musb->mregs;
         u8      reg;
 
-        switch (musb->xceiv.state) {
+        DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
+
+        switch (musb->xceiv->state) {
         case OTG_STATE_A_PERIPHERAL:
-        case OTG_STATE_A_WAIT_VFALL:
-        case OTG_STATE_A_WAIT_BCON:
-                DBG(1, "HNP: Switching back to A-host\n");
                 musb_g_disconnect(musb);
-                musb->xceiv.state = OTG_STATE_A_IDLE;
-                MUSB_HST_MODE(musb);
-                musb->is_active = 0;
+                DBG(1, "HNP: back to %s\n", otg_state_string(musb));
                 break;
         case OTG_STATE_B_HOST:
                 DBG(1, "HNP: Disabling HR\n");
                 hcd->self.is_b_host = 0;
-                musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
+                musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
                 MUSB_DEV_MODE(musb);
                 reg = musb_readb(mbase, MUSB_POWER);
                 reg |= MUSB_POWER_SUSPENDM;
@@ -402,7 +394,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
 
                 if (devctl & MUSB_DEVCTL_HM) {
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
-                        switch (musb->xceiv.state) {
+                        switch (musb->xceiv->state) {
                         case OTG_STATE_A_SUSPEND:
                                 /* remote wakeup?  later, GetPortStatus
                                  * will stop RESUME signaling
@@ -425,12 +417,12 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
                                 musb->rh_timer = jiffies
                                                 + msecs_to_jiffies(20);
 
-                                musb->xceiv.state = OTG_STATE_A_HOST;
+                                musb->xceiv->state = OTG_STATE_A_HOST;
                                 musb->is_active = 1;
                                 usb_hcd_resume_root_hub(musb_to_hcd(musb));
                                 break;
                         case OTG_STATE_B_WAIT_ACON:
-                                musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
+                                musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
                                 musb->is_active = 1;
                                 MUSB_DEV_MODE(musb);
                                 break;
@@ -441,11 +433,11 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
                         }
 #endif
                 } else {
-                        switch (musb->xceiv.state) {
+                        switch (musb->xceiv->state) {
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
                         case OTG_STATE_A_SUSPEND:
                                 /* possibly DISCONNECT is upcoming */
-                                musb->xceiv.state = OTG_STATE_A_HOST;
+                                musb->xceiv->state = OTG_STATE_A_HOST;
                                 usb_hcd_resume_root_hub(musb_to_hcd(musb));
                                 break;
 #endif
@@ -490,7 +482,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
                  */
                 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
                 musb->ep0_stage = MUSB_EP0_START;
-                musb->xceiv.state = OTG_STATE_A_IDLE;
+                musb->xceiv->state = OTG_STATE_A_IDLE;
                 MUSB_HST_MODE(musb);
                 musb_set_vbus(musb, 1);
 
@@ -516,7 +508,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
                  * REVISIT:  do delays from lots of DEBUG_KERNEL checks
                  * make trouble here, keeping VBUS < 4.4V ?
                  */
-                switch (musb->xceiv.state) {
+                switch (musb->xceiv->state) {
                 case OTG_STATE_A_HOST:
                         /* recovery is dicey once we've gotten past the
                          * initial stages of enumeration, but if VBUS
@@ -594,37 +586,40 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
                 if (devctl & MUSB_DEVCTL_LSDEV)
                         musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
 
-                if (hcd->status_urb)
-                        usb_hcd_poll_rh_status(hcd);
-                else
-                        usb_hcd_resume_root_hub(hcd);
-
-                MUSB_HST_MODE(musb);
-
                 /* indicate new connection to OTG machine */
-                switch (musb->xceiv.state) {
+                switch (musb->xceiv->state) {
                 case OTG_STATE_B_PERIPHERAL:
                         if (int_usb & MUSB_INTR_SUSPEND) {
                                 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
-                                musb->xceiv.state = OTG_STATE_B_HOST;
-                                hcd->self.is_b_host = 1;
                                 int_usb &= ~MUSB_INTR_SUSPEND;
+                                goto b_host;
                         } else
                                 DBG(1, "CONNECT as b_peripheral???\n");
                         break;
                 case OTG_STATE_B_WAIT_ACON:
-                        DBG(1, "HNP: Waiting to switch to b_host state\n");
-                        musb->xceiv.state = OTG_STATE_B_HOST;
+                        DBG(1, "HNP: CONNECT, now b_host\n");
+b_host:
+                        musb->xceiv->state = OTG_STATE_B_HOST;
                         hcd->self.is_b_host = 1;
+                        musb->ignore_disconnect = 0;
+                        del_timer(&musb->otg_timer);
                         break;
                 default:
                         if ((devctl & MUSB_DEVCTL_VBUS)
                                         == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
-                                musb->xceiv.state = OTG_STATE_A_HOST;
+                                musb->xceiv->state = OTG_STATE_A_HOST;
                                 hcd->self.is_b_host = 0;
                         }
                         break;
                 }
+
+                /* poke the root hub */
+                MUSB_HST_MODE(musb);
+                if (hcd->status_urb)
+                        usb_hcd_poll_rh_status(hcd);
+                else
+                        usb_hcd_resume_root_hub(hcd);
+
                 DBG(1, "CONNECT (%s) devctl %02x\n",
                                 otg_state_string(musb), devctl);
         }
@@ -650,7 +645,7 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
                         }
                 } else if (is_peripheral_capable()) {
                         DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
-                        switch (musb->xceiv.state) {
+                        switch (musb->xceiv->state) {
 #ifdef CONFIG_USB_OTG
                         case OTG_STATE_A_SUSPEND:
                                 /* We need to ignore disconnect on suspend
@@ -661,24 +656,27 @@ static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
                                 musb_g_reset(musb);
                                 /* FALLTHROUGH */
                         case OTG_STATE_A_WAIT_BCON:     /* OPT TD.4.7-900ms */
-                                DBG(1, "HNP: Setting timer as %s\n",
-                                                otg_state_string(musb));
-                                musb_otg_timer.data = (unsigned long)musb;
-                                mod_timer(&musb_otg_timer, jiffies
-                                        + msecs_to_jiffies(100));
+                                /* never use invalid T(a_wait_bcon) */
+                                DBG(1, "HNP: in %s, %d msec timeout\n",
+                                                otg_state_string(musb),
+                                                TA_WAIT_BCON(musb));
+                                mod_timer(&musb->otg_timer, jiffies
+                                        + msecs_to_jiffies(TA_WAIT_BCON(musb)));
                                 break;
                         case OTG_STATE_A_PERIPHERAL:
-                                musb_hnp_stop(musb);
+                                musb->ignore_disconnect = 0;
+                                del_timer(&musb->otg_timer);
+                                musb_g_reset(musb);
                                 break;
                         case OTG_STATE_B_WAIT_ACON:
                                 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
                                         otg_state_string(musb));
-                                musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
+                                musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
                                 musb_g_reset(musb);
                                 break;
 #endif
                         case OTG_STATE_B_IDLE:
-                                musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
+                                musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
                                 /* FALLTHROUGH */
                         case OTG_STATE_B_PERIPHERAL:
                                 musb_g_reset(musb);
@@ -763,7 +761,7 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
                                 MUSB_MODE(musb), devctl);
                 handled = IRQ_HANDLED;
 
-                switch (musb->xceiv.state) {
+                switch (musb->xceiv->state) {
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
                 case OTG_STATE_A_HOST:
                 case OTG_STATE_A_SUSPEND:
@@ -776,7 +774,16 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
 #endif  /* HOST */
 #ifdef CONFIG_USB_MUSB_OTG
                 case OTG_STATE_B_HOST:
-                        musb_hnp_stop(musb);
+                        /* REVISIT this behaves for "real disconnect"
+                         * cases; make sure the other transitions from
+                         * from B_HOST act right too.  The B_HOST code
+                         * in hnp_stop() is currently not used...
+                         */
+                        musb_root_disconnect(musb);
+                        musb_to_hcd(musb)->self.is_b_host = 0;
+                        musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
+                        MUSB_DEV_MODE(musb);
+                        musb_g_disconnect(musb);
                         break;
                 case OTG_STATE_A_PERIPHERAL:
                         musb_hnp_stop(musb);
@@ -805,26 +812,35 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
                                 otg_state_string(musb), devctl, power);
                 handled = IRQ_HANDLED;
 
-                switch (musb->xceiv.state) {
+                switch (musb->xceiv->state) {
 #ifdef  CONFIG_USB_MUSB_OTG
                 case OTG_STATE_A_PERIPHERAL:
-                        /*
-                         * We cannot stop HNP here, devctl BDEVICE might be
-                         * still set.
+                        /* We also come here if the cable is removed, since
+                         * this silicon doesn't report ID-no-longer-grounded.
+                         *
+                         * We depend on T(a_wait_bcon) to shut us down, and
+                         * hope users don't do anything dicey during this
+                         * undesired detour through A_WAIT_BCON.
                          */
+                        musb_hnp_stop(musb);
+                        usb_hcd_resume_root_hub(musb_to_hcd(musb));
+                        musb_root_disconnect(musb);
+                        musb_platform_try_idle(musb, jiffies
+                                        + msecs_to_jiffies(musb->a_wait_bcon
+                                                ? : OTG_TIME_A_WAIT_BCON));
                         break;
 #endif
                 case OTG_STATE_B_PERIPHERAL:
                         musb_g_suspend(musb);
                         musb->is_active = is_otg_enabled(musb)
-                                        && musb->xceiv.gadget->b_hnp_enable;
+                                        && musb->xceiv->gadget->b_hnp_enable;
                         if (musb->is_active) {
 #ifdef  CONFIG_USB_MUSB_OTG
-                                musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
+                                musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
                                 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
-                                musb_otg_timer.data = (unsigned long)musb;
-                                mod_timer(&musb_otg_timer, jiffies
-                                        + msecs_to_jiffies(TB_ASE0_BRST));
+                                mod_timer(&musb->otg_timer, jiffies
+                                        + msecs_to_jiffies(
+                                                        OTG_TIME_B_ASE0_BRST));
 #endif
                         }
                         break;
@@ -834,9 +850,9 @@ static irqreturn_t musb_stage2_irq(struct musb *musb, u8 int_usb,
                                         + msecs_to_jiffies(musb->a_wait_bcon));
                         break;
                 case OTG_STATE_A_HOST:
-                        musb->xceiv.state = OTG_STATE_A_SUSPEND;
+                        musb->xceiv->state = OTG_STATE_A_SUSPEND;
                         musb->is_active = is_otg_enabled(musb)
-                                        && musb->xceiv.host->b_hnp_enable;
+                                        && musb->xceiv->host->b_hnp_enable;
                         break;
                 case OTG_STATE_B_HOST:
                         /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
@@ -1068,14 +1084,13 @@ static struct fifo_cfg __initdata mode_4_cfg[] = {
 { .hw_ep_num =  8, .style = FIFO_RX,   .maxpacket = 512, },
 { .hw_ep_num =  9, .style = FIFO_TX,   .maxpacket = 512, },
 { .hw_ep_num =  9, .style = FIFO_RX,   .maxpacket = 512, },
-{ .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 512, },
-{ .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 512, },
-{ .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 512, },
-{ .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 512, },
-{ .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 512, },
-{ .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 512, },
-{ .hw_ep_num = 13, .style = FIFO_TX,   .maxpacket = 512, },
-{ .hw_ep_num = 13, .style = FIFO_RX,   .maxpacket = 512, },
+{ .hw_ep_num = 10, .style = FIFO_TX,   .maxpacket = 256, },
+{ .hw_ep_num = 10, .style = FIFO_RX,   .maxpacket = 64, },
+{ .hw_ep_num = 11, .style = FIFO_TX,   .maxpacket = 256, },
+{ .hw_ep_num = 11, .style = FIFO_RX,   .maxpacket = 64, },
+{ .hw_ep_num = 12, .style = FIFO_TX,   .maxpacket = 256, },
+{ .hw_ep_num = 12, .style = FIFO_RX,   .maxpacket = 64, },
+{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
 };
@@ -1335,11 +1350,11 @@ static int __init musb_core_init(u16 musb_type, struct musb *musb)
         }
         if (reg & MUSB_CONFIGDATA_HBRXE) {
                 strcat(aInfo, ", HB-ISO Rx");
-                strcat(aInfo, " (X)");          /* no driver support */
+                musb->hb_iso_rx = true;
         }
         if (reg & MUSB_CONFIGDATA_HBTXE) {
                 strcat(aInfo, ", HB-ISO Tx");
-                strcat(aInfo, " (X)");          /* no driver support */
+                musb->hb_iso_tx = true;
         }
         if (reg & MUSB_CONFIGDATA_SOFTCONE)
                 strcat(aInfo, ", SoftConn");
@@ -1481,13 +1496,7 @@ static irqreturn_t generic_interrupt(int irq, void *__hci)
 
         spin_unlock_irqrestore(&musb->lock, flags);
 
-        /* REVISIT we sometimes get spurious IRQs on g_ep0
-         * not clear why...
-         */
-        if (retval != IRQ_HANDLED)
-                DBG(5, "spurious?\n");
-
-        return IRQ_HANDLED;
+        return retval;
 }
 
 #else
@@ -1687,8 +1696,9 @@ musb_vbus_store(struct device *dev, struct device_attribute *attr,
         }
 
         spin_lock_irqsave(&musb->lock, flags);
-        musb->a_wait_bcon = val;
-        if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
+        /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
+        musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
+        if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
                 musb->is_active = 0;
         musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
         spin_unlock_irqrestore(&musb->lock, flags);
@@ -1706,10 +1716,13 @@ musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
 
         spin_lock_irqsave(&musb->lock, flags);
         val = musb->a_wait_bcon;
+        /* FIXME get_vbus_status() is normally #defined as false...
+         * and is effectively TUSB-specific.
+         */
         vbus = musb_platform_get_vbus_status(musb);
         spin_unlock_irqrestore(&musb->lock, flags);
 
-        return sprintf(buf, "Vbus %s, timeout %lu\n",
+        return sprintf(buf, "Vbus %s, timeout %lu msec\n",
                         vbus ? "on" : "off", val);
 }
 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
@@ -1749,8 +1762,8 @@ static void musb_irq_work(struct work_struct *data)
         struct musb *musb = container_of(data, struct musb, irq_work);
         static int old_state;
 
-        if (musb->xceiv.state != old_state) {
-                old_state = musb->xceiv.state;
+        if (musb->xceiv->state != old_state) {
+                old_state = musb->xceiv->state;
                 sysfs_notify(&musb->controller->kobj, NULL, "mode");
         }
 }
@@ -1782,6 +1795,7 @@ allocate_instance(struct device *dev,
         hcd->uses_new_polling = 1;
 
         musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
+        musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
 #else
         musb = kzalloc(sizeof *musb, GFP_KERNEL);
         if (!musb)
@@ -1847,7 +1861,7 @@ static void musb_free(struct musb *musb)
         }
 
 #ifdef CONFIG_USB_MUSB_OTG
-        put_device(musb->xceiv.dev);
+        put_device(musb->xceiv->dev);
 #endif
 
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
@@ -1928,10 +1942,18 @@ bad_config:
                 }
         }
 
-        /* assume vbus is off */
-
-        /* platform adjusts musb->mregs and musb->isr if needed,
-         * and activates clocks
+        /* The musb_platform_init() call:
+         *   - adjusts musb->mregs and musb->isr if needed,
+         *   - may initialize an integrated tranceiver
+         *   - initializes musb->xceiv, usually by otg_get_transceiver()
+         *   - activates clocks.
+         *   - stops powering VBUS
+         *   - assigns musb->board_set_vbus if host mode is enabled
+         *
+         * There are various transciever configurations.  Blackfin,
+         * DaVinci, TUSB60x0, and others integrate them.  OMAP3 uses
+         * external/discrete ones in various flavors (twl4030 family,
+         * isp1504, non-OTG, etc) mostly hooking up through ULPI.
          */
         musb->isr = generic_interrupt;
         status = musb_platform_init(musb);
@@ -1968,6 +1990,10 @@ bad_config:
         if (status < 0)
                 goto fail2;
 
+#ifdef CONFIG_USB_OTG
+        setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
+#endif
+
         /* Init IRQ workqueue before request_irq */
         INIT_WORK(&musb->irq_work, musb_irq_work);
 
@@ -1999,17 +2025,17 @@ bad_config:
                                 ? "DMA" : "PIO",
                         musb->nIrq);
 
-#ifdef CONFIG_USB_MUSB_HDRC_HCD
-        /* host side needs more setup, except for no-host modes */
-        if (musb->board_mode != MUSB_PERIPHERAL) {
+        /* host side needs more setup */
+        if (is_host_enabled(musb)) {
                 struct usb_hcd  *hcd = musb_to_hcd(musb);
 
-                if (musb->board_mode == MUSB_OTG)
+                otg_set_host(musb->xceiv, &hcd->self);
+
+                if (is_otg_enabled(musb))
                         hcd->self.otg_port = 1;
-                musb->xceiv.host = &hcd->self;
+                musb->xceiv->host = &hcd->self;
                 hcd->power_budget = 2 * (plat->power ? : 250);
         }
-#endif                          /* CONFIG_USB_MUSB_HDRC_HCD */
 
         /* For the host-only role, we can activate right away.
          * (We expect the ID pin to be forcibly grounded!!)
@@ -2017,8 +2043,8 @@ bad_config:
          */
         if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
                 MUSB_HST_MODE(musb);
-                musb->xceiv.default_a = 1;
-                musb->xceiv.state = OTG_STATE_A_IDLE;
+                musb->xceiv->default_a = 1;
+                musb->xceiv->state = OTG_STATE_A_IDLE;
 
                 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
                 if (status)
@@ -2033,8 +2059,8 @@ bad_config:
 
         } else /* peripheral is enabled */ {
                 MUSB_DEV_MODE(musb);
-                musb->xceiv.default_a = 0;
-                musb->xceiv.state = OTG_STATE_B_IDLE;
+                musb->xceiv->default_a = 0;
+                musb->xceiv->state = OTG_STATE_B_IDLE;
 
                 status = musb_gadget_setup(musb);
                 if (status)
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index efb39b5e55b5..f3772ca3b2cf 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -40,6 +40,7 @@
 #include <linux/interrupt.h>
 #include <linux/smp_lock.h>
 #include <linux/errno.h>
+#include <linux/timer.h>
 #include <linux/clk.h>
 #include <linux/device.h>
 #include <linux/usb/ch9.h>
@@ -171,7 +172,8 @@ enum musb_h_ep0_state {
 
 /* peripheral side ep0 states */
 enum musb_g_ep0_state {
-        MUSB_EP0_STAGE_SETUP,           /* idle, waiting for setup */
+        MUSB_EP0_STAGE_IDLE,            /* idle, waiting for SETUP */
+        MUSB_EP0_STAGE_SETUP,           /* received SETUP */
         MUSB_EP0_STAGE_TX,              /* IN data */
         MUSB_EP0_STAGE_RX,              /* OUT data */
         MUSB_EP0_STAGE_STATUSIN,        /* (after OUT data) */
@@ -179,10 +181,15 @@ enum musb_g_ep0_state {
         MUSB_EP0_STAGE_ACKWAIT,         /* after zlp, before statusin */
 } __attribute__ ((packed));
 
-/* OTG protocol constants */
+/*
+ * OTG protocol constants.  See USB OTG 1.3 spec,
+ * sections 5.5 "Device Timings" and 6.6.5 "Timers".
+ */
 #define OTG_TIME_A_WAIT_VRISE   100             /* msec (max) */
-#define OTG_TIME_A_WAIT_BCON    0               /* 0=infinite; min 1000 msec */
-#define OTG_TIME_A_IDLE_BDIS    200             /* msec (min) */
+#define OTG_TIME_A_WAIT_BCON    1100            /* min 1 second */
+#define OTG_TIME_A_AIDL_BDIS    200             /* min 200 msec */
+#define OTG_TIME_B_ASE0_BRST    100             /* min 3.125 ms */
+
 
 /*************************** REGISTER ACCESS ********************************/
 
@@ -331,6 +338,8 @@ struct musb {
         struct list_head        control;        /* of musb_qh */
         struct list_head        in_bulk;        /* of musb_qh */
         struct list_head        out_bulk;       /* of musb_qh */
+
+        struct timer_list       otg_timer;
 #endif
 
         /* called with IRQs blocked; ON/nonzero implies starting a session,
@@ -355,7 +364,7 @@ struct musb {
         u16                     int_rx;
         u16                     int_tx;
 
-        struct otg_transceiver  xceiv;
+        struct otg_transceiver  *xceiv;
 
         int nIrq;
         unsigned                irq_wake:1;
@@ -386,6 +395,9 @@ struct musb {
         unsigned is_multipoint:1;
         unsigned ignore_disconnect:1;   /* during bus resets */
 
+        unsigned                hb_iso_rx:1;    /* high bandwidth iso rx? */
+        unsigned                hb_iso_tx:1;    /* high bandwidth iso tx? */
+
 #ifdef C_MP_TX
         unsigned bulk_split:1;
 #define can_bulk_split(musb,type) \
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index f79440cdfe7e..8b3c4e2ed7b8 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -310,7 +310,7 @@ static void txstate(struct musb *musb, struct musb_request *req)
                         /* setup DMA, then program endpoint CSR */
                         request_size = min(request->length,
                                                 musb_ep->dma->max_len);
-                        if (request_size <= musb_ep->packet_sz)
+                        if (request_size < musb_ep->packet_sz)
                                 musb_ep->dma->desired_mode = 0;
                         else
                                 musb_ep->dma->desired_mode = 1;
@@ -349,7 +349,8 @@ static void txstate(struct musb *musb, struct musb_request *req)
 #elif defined(CONFIG_USB_TI_CPPI_DMA)
                 /* program endpoint CSR first, then setup DMA */
                 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
-                csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_DMAENAB;
+                csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
+                       MUSB_TXCSR_MODE;
                 musb_writew(epio, MUSB_TXCSR,
                         (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
                                 | csr);
@@ -1405,7 +1406,7 @@ static int musb_gadget_wakeup(struct usb_gadget *gadget)
 
         spin_lock_irqsave(&musb->lock, flags);
 
-        switch (musb->xceiv.state) {
+        switch (musb->xceiv->state) {
         case OTG_STATE_B_PERIPHERAL:
                 /* NOTE:  OTG state machine doesn't include B_SUSPENDED;
                  * that's part of the standard usb 1.1 state machine, and
@@ -1507,9 +1508,9 @@ static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
 {
         struct musb     *musb = gadget_to_musb(gadget);
 
-        if (!musb->xceiv.set_power)
+        if (!musb->xceiv->set_power)
                 return -EOPNOTSUPP;
-        return otg_set_power(&musb->xceiv, mA);
+        return otg_set_power(musb->xceiv, mA);
 }
 
 static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
@@ -1732,11 +1733,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 
                 spin_lock_irqsave(&musb->lock, flags);
 
-                /* REVISIT always use otg_set_peripheral(), handling
-                 * issues including the root hub one below ...
-                 */
-                musb->xceiv.gadget = &musb->g;
-                musb->xceiv.state = OTG_STATE_B_IDLE;
+                otg_set_peripheral(musb->xceiv, &musb->g);
                 musb->is_active = 1;
 
                 /* FIXME this ignores the softconnect flag.  Drivers are
@@ -1748,6 +1745,8 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
                 if (!is_otg_enabled(musb))
                         musb_start(musb);
 
+                otg_set_peripheral(musb->xceiv, &musb->g);
+
                 spin_unlock_irqrestore(&musb->lock, flags);
 
                 if (is_otg_enabled(musb)) {
@@ -1761,8 +1760,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
                         if (retval < 0) {
                                 DBG(1, "add_hcd failed, %d\n", retval);
                                 spin_lock_irqsave(&musb->lock, flags);
-                                musb->xceiv.gadget = NULL;
-                                musb->xceiv.state = OTG_STATE_UNDEFINED;
+                                otg_set_peripheral(musb->xceiv, NULL);
                                 musb->gadget_driver = NULL;
                                 musb->g.dev.driver = NULL;
                                 spin_unlock_irqrestore(&musb->lock, flags);
@@ -1845,8 +1843,9 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
 
                 (void) musb_gadget_vbus_draw(&musb->g, 0);
 
-                musb->xceiv.state = OTG_STATE_UNDEFINED;
+                musb->xceiv->state = OTG_STATE_UNDEFINED;
                 stop_activity(musb, driver);
+                otg_set_peripheral(musb->xceiv, NULL);
 
                 DBG(3, "unregistering driver %s\n", driver->function);
                 spin_unlock_irqrestore(&musb->lock, flags);
@@ -1882,7 +1881,7 @@ EXPORT_SYMBOL(usb_gadget_unregister_driver);
 void musb_g_resume(struct musb *musb)
 {
         musb->is_suspended = 0;
-        switch (musb->xceiv.state) {
+        switch (musb->xceiv->state) {
         case OTG_STATE_B_IDLE:
                 break;
         case OTG_STATE_B_WAIT_ACON:
@@ -1908,10 +1907,10 @@ void musb_g_suspend(struct musb *musb)
         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
         DBG(3, "devctl %02x\n", devctl);
 
-        switch (musb->xceiv.state) {
+        switch (musb->xceiv->state) {
         case OTG_STATE_B_IDLE:
                 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
-                        musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
+                        musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
                 break;
         case OTG_STATE_B_PERIPHERAL:
                 musb->is_suspended = 1;
@@ -1957,22 +1956,24 @@ void musb_g_disconnect(struct musb *musb)
                 spin_lock(&musb->lock);
         }
 
-        switch (musb->xceiv.state) {
+        switch (musb->xceiv->state) {
         default:
 #ifdef  CONFIG_USB_MUSB_OTG
                 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
                         otg_state_string(musb));
-                musb->xceiv.state = OTG_STATE_A_IDLE;
+                musb->xceiv->state = OTG_STATE_A_IDLE;
+                MUSB_HST_MODE(musb);
                 break;
         case OTG_STATE_A_PERIPHERAL:
-                musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
+                musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
+                MUSB_HST_MODE(musb);
                 break;
         case OTG_STATE_B_WAIT_ACON:
         case OTG_STATE_B_HOST:
 #endif
         case OTG_STATE_B_PERIPHERAL:
         case OTG_STATE_B_IDLE:
-                musb->xceiv.state = OTG_STATE_B_IDLE;
+                musb->xceiv->state = OTG_STATE_B_IDLE;
                 break;
         case OTG_STATE_B_SRP_INIT:
                 break;
@@ -2028,10 +2029,10 @@ __acquires(musb->lock)
          * or else after HNP, as A-Device
          */
         if (devctl & MUSB_DEVCTL_BDEVICE) {
-                musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
+                musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
                 musb->g.is_a_peripheral = 0;
         } else if (is_otg_enabled(musb)) {
-                musb->xceiv.state = OTG_STATE_A_PERIPHERAL;
+                musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
                 musb->g.is_a_peripheral = 1;
         } else
                 WARN_ON(1);
diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
index 3f5e30ddfa27..40ed50ecedff 100644
--- a/drivers/usb/musb/musb_gadget_ep0.c
+++ b/drivers/usb/musb/musb_gadget_ep0.c
@@ -4,6 +4,7 @@
  * Copyright 2005 Mentor Graphics Corporation
  * Copyright (C) 2005-2006 by Texas Instruments
  * Copyright (C) 2006-2007 Nokia Corporation
+ * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -58,7 +59,8 @@
 static char *decode_ep0stage(u8 stage)
 {
         switch (stage) {
-        case MUSB_EP0_STAGE_SETUP:      return "idle";
+        case MUSB_EP0_STAGE_IDLE:       return "idle";
+        case MUSB_EP0_STAGE_SETUP:      return "setup";
         case MUSB_EP0_STAGE_TX:         return "in";
         case MUSB_EP0_STAGE_RX:         return "out";
         case MUSB_EP0_STAGE_ACKWAIT:    return "wait";
@@ -628,7 +630,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
                 musb_writew(regs, MUSB_CSR0,
                                 csr & ~MUSB_CSR0_P_SENTSTALL);
                 retval = IRQ_HANDLED;
-                musb->ep0_state = MUSB_EP0_STAGE_SETUP;
+                musb->ep0_state = MUSB_EP0_STAGE_IDLE;
                 csr = musb_readw(regs, MUSB_CSR0);
         }
 
@@ -636,7 +638,18 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
         if (csr & MUSB_CSR0_P_SETUPEND) {
                 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
                 retval = IRQ_HANDLED;
-                musb->ep0_state = MUSB_EP0_STAGE_SETUP;
+                /* Transition into the early status phase */
+                switch (musb->ep0_state) {
+                case MUSB_EP0_STAGE_TX:
+                        musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
+                        break;
+                case MUSB_EP0_STAGE_RX:
+                        musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
+                        break;
+                default:
+                        ERR("SetupEnd came in a wrong ep0stage %s",
+                            decode_ep0stage(musb->ep0_state));
+                }
                 csr = musb_readw(regs, MUSB_CSR0);
                 /* NOTE:  request may need completion */
         }
@@ -697,11 +710,31 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
                         if (req)
                                 musb_g_ep0_giveback(musb, req);
                 }
+
+                /*
+                 * In case when several interrupts can get coalesced,
+                 * check to see if we've already received a SETUP packet...
+                 */
+                if (csr & MUSB_CSR0_RXPKTRDY)
+                        goto setup;
+
+                retval = IRQ_HANDLED;
+                musb->ep0_state = MUSB_EP0_STAGE_IDLE;
+                break;
+
+        case MUSB_EP0_STAGE_IDLE:
+                /*
+                 * This state is typically (but not always) indiscernible
+                 * from the status states since the corresponding interrupts
+                 * tend to happen within too little period of time (with only
+                 * a zero-length packet in between) and so get coalesced...
+                 */
                 retval = IRQ_HANDLED;
                 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
                 /* FALLTHROUGH */
 
         case MUSB_EP0_STAGE_SETUP:
+setup:
                 if (csr & MUSB_CSR0_RXPKTRDY) {
                         struct usb_ctrlrequest  setup;
                         int                     handled = 0;
@@ -783,7 +816,7 @@ irqreturn_t musb_g_ep0_irq(struct musb *musb)
 stall:
                                 DBG(3, "stall (%d)\n", handled);
                                 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
-                                musb->ep0_state = MUSB_EP0_STAGE_SETUP;
+                                musb->ep0_state = MUSB_EP0_STAGE_IDLE;
 finish:
                                 musb_writew(regs, MUSB_CSR0,
                                                 musb->ackpend);
@@ -803,7 +836,7 @@ finish:
                 /* "can't happen" */
                 WARN_ON(1);
                 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
-                musb->ep0_state = MUSB_EP0_STAGE_SETUP;
+                musb->ep0_state = MUSB_EP0_STAGE_IDLE;
                 break;
         }
 
@@ -959,7 +992,7 @@ static int musb_g_ep0_halt(struct usb_ep *e, int value)
 
                 csr |= MUSB_CSR0_P_SENDSTALL;
                 musb_writew(regs, MUSB_CSR0, csr);
-                musb->ep0_state = MUSB_EP0_STAGE_SETUP;
+                musb->ep0_state = MUSB_EP0_STAGE_IDLE;
                 musb->ackpend = 0;
                 break;
         default:
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index db1b57415ec7..94a2a350a414 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -181,6 +181,19 @@ static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
         musb_writew(ep->regs, MUSB_TXCSR, txcsr);
 }
 
+static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
+{
+        if (is_in != 0 || ep->is_shared_fifo)
+                ep->in_qh  = qh;
+        if (is_in == 0 || ep->is_shared_fifo)
+                ep->out_qh = qh;
+}
+
+static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
+{
+        return is_in ? ep->in_qh : ep->out_qh;
+}
+
 /*
  * Start the URB at the front of an endpoint's queue
  * end must be claimed from the caller.
@@ -210,7 +223,6 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
         case USB_ENDPOINT_XFER_CONTROL:
                 /* control transfers always start with SETUP */
                 is_in = 0;
-                hw_ep->out_qh = qh;
                 musb->ep0_stage = MUSB_EP0_START;
                 buf = urb->setup_packet;
                 len = 8;
@@ -239,10 +251,7 @@ musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
                         epnum, buf + offset, len);
 
         /* Configure endpoint */
-        if (is_in || hw_ep->is_shared_fifo)
-                hw_ep->in_qh = qh;
-        else
-                hw_ep->out_qh = qh;
+        musb_ep_set_qh(hw_ep, is_in, qh);
         musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
 
         /* transmit may have more work: start it when it is time */
@@ -286,9 +295,8 @@ start:
         }
 }
 
-/* caller owns controller lock, irqs are blocked */
-static void
-__musb_giveback(struct musb *musb, struct urb *urb, int status)
+/* Context: caller owns controller lock, IRQs are blocked */
+static void musb_giveback(struct musb *musb, struct urb *urb, int status)
 __releases(musb->lock)
 __acquires(musb->lock)
 {
@@ -321,60 +329,57 @@ __acquires(musb->lock)
         spin_lock(&musb->lock);
 }
 
-/* for bulk/interrupt endpoints only */
-static inline void
-musb_save_toggle(struct musb_hw_ep *ep, int is_in, struct urb *urb)
+/* For bulk/interrupt endpoints only */
+static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
+                                    struct urb *urb)
 {
-        struct usb_device       *udev = urb->dev;
+        void __iomem            *epio = qh->hw_ep->regs;
         u16                     csr;
-        void __iomem            *epio = ep->regs;
-        struct musb_qh          *qh;
 
-        /* FIXME:  the current Mentor DMA code seems to have
+        /*
+         * FIXME: the current Mentor DMA code seems to have
          * problems getting toggle correct.
          */
 
-        if (is_in || ep->is_shared_fifo)
-                qh = ep->in_qh;
+        if (is_in)
+                csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
         else
-                qh = ep->out_qh;
+                csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
 
-        if (!is_in) {
-                csr = musb_readw(epio, MUSB_TXCSR);
-                usb_settoggle(udev, qh->epnum, 1,
-                        (csr & MUSB_TXCSR_H_DATATOGGLE)
-                                ? 1 : 0);
-        } else {
-                csr = musb_readw(epio, MUSB_RXCSR);
-                usb_settoggle(udev, qh->epnum, 0,
-                        (csr & MUSB_RXCSR_H_DATATOGGLE)
-                                ? 1 : 0);
-        }
+        usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
 }
 
-/* caller owns controller lock, irqs are blocked */
-static struct musb_qh *
-musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
+/*
+ * Advance this hardware endpoint's queue, completing the specified URB and
+ * advancing to either the next URB queued to that qh, or else invalidating
+ * that qh and advancing to the next qh scheduled after the current one.
+ *
+ * Context: caller owns controller lock, IRQs are blocked
+ */
+static void musb_advance_schedule(struct musb *musb, struct urb *urb,
+                                  struct musb_hw_ep *hw_ep, int is_in)
 {
+        struct musb_qh          *qh = musb_ep_get_qh(hw_ep, is_in);
         struct musb_hw_ep       *ep = qh->hw_ep;
-        struct musb             *musb = ep->musb;
-        int                     is_in = usb_pipein(urb->pipe);
         int                     ready = qh->is_ready;
+        int                     status;
+
+        status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
 
         /* save toggle eagerly, for paranoia */
         switch (qh->type) {
         case USB_ENDPOINT_XFER_BULK:
         case USB_ENDPOINT_XFER_INT:
-                musb_save_toggle(ep, is_in, urb);
+                musb_save_toggle(qh, is_in, urb);
                 break;
         case USB_ENDPOINT_XFER_ISOC:
-                if (status == 0 && urb->error_count)
+                if (urb->error_count)
                         status = -EXDEV;
                 break;
         }
 
         qh->is_ready = 0;
-        __musb_giveback(musb, urb, status);
+        musb_giveback(musb, urb, status);
         qh->is_ready = ready;
 
         /* reclaim resources (and bandwidth) ASAP; deschedule it, and
@@ -388,11 +393,8 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
                 else
                         ep->tx_reinit = 1;
 
-                /* clobber old pointers to this qh */
-                if (is_in || ep->is_shared_fifo)
-                        ep->in_qh = NULL;
-                else
-                        ep->out_qh = NULL;
+                /* Clobber old pointers to this qh */
+                musb_ep_set_qh(ep, is_in, NULL);
                 qh->hep->hcpriv = NULL;
 
                 switch (qh->type) {
@@ -421,36 +423,10 @@ musb_giveback(struct musb_qh *qh, struct urb *urb, int status)
                         break;
                 }
         }
-        return qh;
-}
-
-/*
- * Advance this hardware endpoint's queue, completing the specified urb and
- * advancing to either the next urb queued to that qh, or else invalidating
- * that qh and advancing to the next qh scheduled after the current one.
- *
- * Context: caller owns controller lock, irqs are blocked
- */
-static void
-musb_advance_schedule(struct musb *musb, struct urb *urb,
-                struct musb_hw_ep *hw_ep, int is_in)
-{
-        struct musb_qh  *qh;
-
-        if (is_in || hw_ep->is_shared_fifo)
-                qh = hw_ep->in_qh;
-        else
-                qh = hw_ep->out_qh;
-
-        if (urb->status == -EINPROGRESS)
-                qh = musb_giveback(qh, urb, 0);
-        else
-                qh = musb_giveback(qh, urb, urb->status);
 
         if (qh != NULL && qh->is_ready) {
                 DBG(4, "... next ep%d %cX urb %p\n",
-                                hw_ep->epnum, is_in ? 'R' : 'T',
-                                next_urb(qh));
+                    hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
                 musb_start_urb(musb, is_in, qh);
         }
 }
@@ -629,7 +605,8 @@ musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
         musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
         musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
         /* NOTE: bulk combining rewrites high bits of maxpacket */
-        musb_writew(ep->regs, MUSB_RXMAXP, qh->maxpacket);
+        musb_writew(ep->regs, MUSB_RXMAXP,
+                        qh->maxpacket | ((qh->hb_mult - 1) << 11));
 
         ep->rx_reinit = 0;
 }
@@ -651,9 +628,10 @@ static bool musb_tx_dma_program(struct dma_controller *dma,
         csr = musb_readw(epio, MUSB_TXCSR);
         if (length > pkt_size) {
                 mode = 1;
-                csr |= MUSB_TXCSR_AUTOSET
-                        | MUSB_TXCSR_DMAMODE
-                        | MUSB_TXCSR_DMAENAB;
+                csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
+                /* autoset shouldn't be set in high bandwidth */
+                if (qh->hb_mult == 1)
+                        csr |= MUSB_TXCSR_AUTOSET;
         } else {
                 mode = 0;
                 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
@@ -703,15 +681,8 @@ static void musb_ep_program(struct musb *musb, u8 epnum,
         void __iomem            *mbase = musb->mregs;
         struct musb_hw_ep       *hw_ep = musb->endpoints + epnum;
         void __iomem            *epio = hw_ep->regs;
-        struct musb_qh          *qh;
-        u16                     packet_sz;
-
-        if (!is_out || hw_ep->is_shared_fifo)
-                qh = hw_ep->in_qh;
-        else
-                qh = hw_ep->out_qh;
-
-        packet_sz = qh->maxpacket;
+        struct musb_qh          *qh = musb_ep_get_qh(hw_ep, !is_out);
+        u16                     packet_sz = qh->maxpacket;
 
         DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
                                 "h_addr%02x h_port%02x bytes %d\n",
@@ -1129,17 +1100,14 @@ void musb_host_tx(struct musb *musb, u8 epnum)
         u16                     tx_csr;
         size_t                  length = 0;
         size_t                  offset = 0;
-        struct urb              *urb;
         struct musb_hw_ep       *hw_ep = musb->endpoints + epnum;
         void __iomem            *epio = hw_ep->regs;
-        struct musb_qh          *qh = hw_ep->is_shared_fifo ? hw_ep->in_qh
-                                                            : hw_ep->out_qh;
+        struct musb_qh          *qh = hw_ep->out_qh;
+        struct urb              *urb = next_urb(qh);
         u32                     status = 0;
         void __iomem            *mbase = musb->mregs;
         struct dma_channel      *dma;
 
-        urb = next_urb(qh);
-
         musb_ep_select(mbase, epnum);
         tx_csr = musb_readw(epio, MUSB_TXCSR);
 
@@ -1427,7 +1395,7 @@ static void musb_bulk_rx_nak_timeout(struct musb *musb, struct musb_hw_ep *ep)
                         urb->actual_length += dma->actual_len;
                         dma->actual_len = 0L;
                 }
-                musb_save_toggle(ep, 1, urb);
+                musb_save_toggle(cur_qh, 1, urb);
 
                 /* move cur_qh to end of queue */
                 list_move_tail(&cur_qh->ring, &musb->in_bulk);
@@ -1531,6 +1499,10 @@ void musb_host_rx(struct musb *musb, u8 epnum)
                         /* packet error reported later */
                         iso_err = true;
                 }
+        } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
+                DBG(3, "end %d high bandwidth incomplete ISO packet RX\n",
+                                epnum);
+                status = -EPROTO;
         }
 
         /* faults abort the transfer */
@@ -1738,7 +1710,11 @@ void musb_host_rx(struct musb *musb, u8 epnum)
                                 val &= ~MUSB_RXCSR_H_AUTOREQ;
                         else
                                 val |= MUSB_RXCSR_H_AUTOREQ;
-                        val |= MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAENAB;
+                        val |= MUSB_RXCSR_DMAENAB;
+
+                        /* autoclear shouldn't be set in high bandwidth */
+                        if (qh->hb_mult == 1)
+                                val |= MUSB_RXCSR_AUTOCLEAR;
 
                         musb_writew(epio, MUSB_RXCSR,
                                 MUSB_RXCSR_H_WZC_BITS | val);
@@ -1817,19 +1793,17 @@ static int musb_schedule(
                         epnum++, hw_ep++) {
                 int     diff;
 
-                if (is_in || hw_ep->is_shared_fifo) {
-                        if (hw_ep->in_qh  != NULL)
-                                continue;
-                } else  if (hw_ep->out_qh != NULL)
+                if (musb_ep_get_qh(hw_ep, is_in) != NULL)
                         continue;
 
                 if (hw_ep == musb->bulk_ep)
                         continue;
 
                 if (is_in)
-                        diff = hw_ep->max_packet_sz_rx - qh->maxpacket;
+                        diff = hw_ep->max_packet_sz_rx;
                 else
-                        diff = hw_ep->max_packet_sz_tx - qh->maxpacket;
+                        diff = hw_ep->max_packet_sz_tx;
+                diff -= (qh->maxpacket * qh->hb_mult);
 
                 if (diff >= 0 && best_diff > diff) {
                         best_diff = diff;
@@ -1932,15 +1906,27 @@ static int musb_urb_enqueue(
         qh->is_ready = 1;
 
         qh->maxpacket = le16_to_cpu(epd->wMaxPacketSize);
+        qh->type = usb_endpoint_type(epd);
 
-        /* no high bandwidth support yet */
-        if (qh->maxpacket & ~0x7ff) {
-                ret = -EMSGSIZE;
-                goto done;
+        /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
+         * Some musb cores don't support high bandwidth ISO transfers; and
+         * we don't (yet!) support high bandwidth interrupt transfers.
+         */
+        qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
+        if (qh->hb_mult > 1) {
+                int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
+
+                if (ok)
+                        ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
+                                || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
+                if (!ok) {
+                        ret = -EMSGSIZE;
+                        goto done;
+                }
+                qh->maxpacket &= 0x7ff;
         }
 
         qh->epnum = usb_endpoint_num(epd);
-        qh->type = usb_endpoint_type(epd);
 
         /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
         qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
@@ -2052,14 +2038,15 @@ done:
  * called with controller locked, irqs blocked
  * that hardware queue advances to the next transfer, unless prevented
  */
-static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh, int is_in)
+static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
 {
         struct musb_hw_ep       *ep = qh->hw_ep;
         void __iomem            *epio = ep->regs;
         unsigned                hw_end = ep->epnum;
         void __iomem            *regs = ep->musb->mregs;
-        u16                     csr;
+        int                     is_in = usb_pipein(urb->pipe);
         int                     status = 0;
+        u16                     csr;
 
         musb_ep_select(regs, hw_end);
 
@@ -2112,14 +2099,14 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
 {
         struct musb             *musb = hcd_to_musb(hcd);
         struct musb_qh          *qh;
-        struct list_head        *sched;
         unsigned long           flags;
+        int                     is_in  = usb_pipein(urb->pipe);
         int                     ret;
 
         DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
                         usb_pipedevice(urb->pipe),
                         usb_pipeendpoint(urb->pipe),
-                        usb_pipein(urb->pipe) ? "in" : "out");
+                        is_in ? "in" : "out");
 
         spin_lock_irqsave(&musb->lock, flags);
         ret = usb_hcd_check_unlink_urb(hcd, urb, status);
@@ -2130,47 +2117,25 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
         if (!qh)
                 goto done;
 
-        /* Any URB not actively programmed into endpoint hardware can be
+        /*
+         * Any URB not actively programmed into endpoint hardware can be
          * immediately given back; that's any URB not at the head of an
          * endpoint queue, unless someday we get real DMA queues.  And even
          * if it's at the head, it might not be known to the hardware...
          *
-         * Otherwise abort current transfer, pending dma, etc.; urb->status
+         * Otherwise abort current transfer, pending DMA, etc.; urb->status
          * has already been updated.  This is a synchronous abort; it'd be
          * OK to hold off until after some IRQ, though.
+         *
+         * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
          */
-        if (!qh->is_ready || urb->urb_list.prev != &qh->hep->urb_list)
-                ret = -EINPROGRESS;
-        else {
-                switch (qh->type) {
-                case USB_ENDPOINT_XFER_CONTROL:
-                        sched = &musb->control;
-                        break;
-                case USB_ENDPOINT_XFER_BULK:
-                        if (qh->mux == 1) {
-                                if (usb_pipein(urb->pipe))
-                                        sched = &musb->in_bulk;
-                                else
-                                        sched = &musb->out_bulk;
-                                break;
-                        }
-                default:
-                        /* REVISIT when we get a schedule tree, periodic
-                         * transfers won't always be at the head of a
-                         * singleton queue...
-                         */
-                        sched = NULL;
-                        break;
-                }
-        }
-
-        /* NOTE:  qh is invalid unless !list_empty(&hep->urb_list) */
-        if (ret < 0 || (sched && qh != first_qh(sched))) {
+        if (!qh->is_ready
+                        || urb->urb_list.prev != &qh->hep->urb_list
+                        || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
                 int     ready = qh->is_ready;
 
-                ret = 0;
                 qh->is_ready = 0;
-                __musb_giveback(musb, urb, 0);
+                musb_giveback(musb, urb, 0);
                 qh->is_ready = ready;
 
                 /* If nothing else (usually musb_giveback) is using it
@@ -2182,7 +2147,7 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
                         kfree(qh);
                 }
         } else
-                ret = musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
+                ret = musb_cleanup_urb(urb, qh);
 done:
         spin_unlock_irqrestore(&musb->lock, flags);
         return ret;
@@ -2192,13 +2157,11 @@ done:
 static void
 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
 {
-        u8                      epnum = hep->desc.bEndpointAddress;
+        u8                      is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
         unsigned long           flags;
         struct musb             *musb = hcd_to_musb(hcd);
-        u8                      is_in = epnum & USB_DIR_IN;
         struct musb_qh          *qh;
         struct urb              *urb;
-        struct list_head        *sched;
 
         spin_lock_irqsave(&musb->lock, flags);
 
@@ -2206,31 +2169,11 @@ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
         if (qh == NULL)
                 goto exit;
 
-        switch (qh->type) {
-        case USB_ENDPOINT_XFER_CONTROL:
-                sched = &musb->control;
-                break;
-        case USB_ENDPOINT_XFER_BULK:
-                if (qh->mux == 1) {
-                        if (is_in)
-                                sched = &musb->in_bulk;
-                        else
-                                sched = &musb->out_bulk;
-                        break;
-                }
-        default:
-                /* REVISIT when we get a schedule tree, periodic transfers
-                 * won't always be at the head of a singleton queue...
-                 */
-                sched = NULL;
-                break;
-        }
-
-        /* NOTE:  qh is invalid unless !list_empty(&hep->urb_list) */
+        /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
 
-        /* kick first urb off the hardware, if needed */
+        /* Kick the first URB off the hardware, if needed */
         qh->is_ready = 0;
-        if (!sched || qh == first_qh(sched)) {
+        if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
                 urb = next_urb(qh);
 
                 /* make software (then hardware) stop ASAP */
@@ -2238,7 +2181,7 @@ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
                         urb->status = -ESHUTDOWN;
 
                 /* cleanup */
-                musb_cleanup_urb(urb, qh, urb->pipe & USB_DIR_IN);
+                musb_cleanup_urb(urb, qh);
 
                 /* Then nuke all the others ... and advance the
                  * queue on hw_ep (e.g. bulk ring) when we're done.
@@ -2254,7 +2197,7 @@ musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
                  * will activate any of these as it advances.
                  */
                 while (!list_empty(&hep->urb_list))
-                        __musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
+                        musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
 
                 hep->hcpriv = NULL;
                 list_del(&qh->ring);
@@ -2293,7 +2236,7 @@ static int musb_bus_suspend(struct usb_hcd *hcd)
 {
         struct musb     *musb = hcd_to_musb(hcd);
 
-        if (musb->xceiv.state == OTG_STATE_A_SUSPEND)
+        if (musb->xceiv->state == OTG_STATE_A_SUSPEND)
                 return 0;
 
         if (is_host_active(musb) && musb->is_active) {
diff --git a/drivers/usb/musb/musb_host.h b/drivers/usb/musb/musb_host.h
index 0b7fbcd21963..14b00776638d 100644
--- a/drivers/usb/musb/musb_host.h
+++ b/drivers/usb/musb/musb_host.h
@@ -67,6 +67,7 @@ struct musb_qh {
         u8                      is_ready;       /* safe to modify hw_ep */
         u8                      type;           /* XFERTYPE_* */
         u8                      epnum;
+        u8                      hb_mult;        /* high bandwidth pkts per uf */
         u16                     maxpacket;
         u16                     frame;          /* for periodic schedule */
         unsigned                iso_idx;        /* in urb->iso_frame_desc[] */
diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
index bf677acc83db..bfe5fe4ebfee 100644
--- a/drivers/usb/musb/musb_virthub.c
+++ b/drivers/usb/musb/musb_virthub.c
@@ -78,18 +78,22 @@ static void musb_port_suspend(struct musb *musb, bool do_suspend)
                 DBG(3, "Root port suspended, power %02x\n", power);
 
                 musb->port1_status |= USB_PORT_STAT_SUSPEND;
-                switch (musb->xceiv.state) {
+                switch (musb->xceiv->state) {
                 case OTG_STATE_A_HOST:
-                        musb->xceiv.state = OTG_STATE_A_SUSPEND;
+                        musb->xceiv->state = OTG_STATE_A_SUSPEND;
                         musb->is_active = is_otg_enabled(musb)
-                                        && musb->xceiv.host->b_hnp_enable;
+                                        && musb->xceiv->host->b_hnp_enable;
+                        if (musb->is_active)
+                                mod_timer(&musb->otg_timer, jiffies
+                                        + msecs_to_jiffies(
+                                                OTG_TIME_A_AIDL_BDIS));
                         musb_platform_try_idle(musb, 0);
                         break;
 #ifdef  CONFIG_USB_MUSB_OTG
                 case OTG_STATE_B_HOST:
-                        musb->xceiv.state = OTG_STATE_B_WAIT_ACON;
+                        musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
                         musb->is_active = is_otg_enabled(musb)
-                                        && musb->xceiv.host->b_hnp_enable;
+                                        && musb->xceiv->host->b_hnp_enable;
                         musb_platform_try_idle(musb, 0);
                         break;
 #endif
@@ -116,7 +120,7 @@ static void musb_port_reset(struct musb *musb, bool do_reset)
         void __iomem    *mbase = musb->mregs;
 
 #ifdef CONFIG_USB_MUSB_OTG
-        if (musb->xceiv.state == OTG_STATE_B_IDLE) {
+        if (musb->xceiv->state == OTG_STATE_B_IDLE) {
                 DBG(2, "HNP: Returning from HNP; no hub reset from b_idle\n");
                 musb->port1_status &= ~USB_PORT_STAT_RESET;
                 return;
@@ -186,14 +190,23 @@ void musb_root_disconnect(struct musb *musb)
         usb_hcd_poll_rh_status(musb_to_hcd(musb));
         musb->is_active = 0;
 
-        switch (musb->xceiv.state) {
-        case OTG_STATE_A_HOST:
+        switch (musb->xceiv->state) {
         case OTG_STATE_A_SUSPEND:
-                musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
+#ifdef  CONFIG_USB_MUSB_OTG
+                if (is_otg_enabled(musb)
+                                && musb->xceiv->host->b_hnp_enable) {
+                        musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
+                        musb->g.is_a_peripheral = 1;
+                        break;
+                }
+#endif
+                /* FALLTHROUGH */
+        case OTG_STATE_A_HOST:
+                musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
                 musb->is_active = 0;
                 break;
         case OTG_STATE_A_WAIT_VFALL:
-                musb->xceiv.state = OTG_STATE_B_IDLE;
+                musb->xceiv->state = OTG_STATE_B_IDLE;
                 break;
         default:
                 DBG(1, "host disconnect (%s)\n", otg_state_string(musb));
@@ -332,7 +345,7 @@ int musb_hub_control(
                         musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
                         usb_hcd_poll_rh_status(musb_to_hcd(musb));
                         /* NOTE: it might really be A_WAIT_BCON ... */
-                        musb->xceiv.state = OTG_STATE_A_HOST;
+                        musb->xceiv->state = OTG_STATE_A_HOST;
                 }
 
                 put_unaligned(cpu_to_le32(musb->port1_status
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 60924ce08493..34875201ee04 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -44,7 +44,6 @@
 #define get_cpu_rev()   2
 #endif
 
-#define MUSB_TIMEOUT_A_WAIT_BCON        1100
 
 static struct timer_list musb_idle_timer;
 
@@ -61,17 +60,17 @@ static void musb_do_idle(unsigned long _musb)
 
         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 
-        switch (musb->xceiv.state) {
+        switch (musb->xceiv->state) {
         case OTG_STATE_A_WAIT_BCON:
                 devctl &= ~MUSB_DEVCTL_SESSION;
                 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 
                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
                 if (devctl & MUSB_DEVCTL_BDEVICE) {
-                        musb->xceiv.state = OTG_STATE_B_IDLE;
+                        musb->xceiv->state = OTG_STATE_B_IDLE;
                         MUSB_DEV_MODE(musb);
                 } else {
-                        musb->xceiv.state = OTG_STATE_A_IDLE;
+                        musb->xceiv->state = OTG_STATE_A_IDLE;
                         MUSB_HST_MODE(musb);
                 }
                 break;
@@ -89,7 +88,7 @@ static void musb_do_idle(unsigned long _musb)
                         musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
                         usb_hcd_poll_rh_status(musb_to_hcd(musb));
                         /* NOTE: it might really be A_WAIT_BCON ... */
-                        musb->xceiv.state = OTG_STATE_A_HOST;
+                        musb->xceiv->state = OTG_STATE_A_HOST;
                 }
                 break;
 #endif
@@ -97,9 +96,9 @@ static void musb_do_idle(unsigned long _musb)
         case OTG_STATE_A_HOST:
                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
                 if (devctl &  MUSB_DEVCTL_BDEVICE)
-                        musb->xceiv.state = OTG_STATE_B_IDLE;
+                        musb->xceiv->state = OTG_STATE_B_IDLE;
                 else
-                        musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
+                        musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
 #endif
         default:
                 break;
@@ -118,7 +117,7 @@ void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
 
         /* Never idle if active, or when VBUS timeout is not set as host */
         if (musb->is_active || ((musb->a_wait_bcon == 0)
-                        && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) {
+                        && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
                 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
                 del_timer(&musb_idle_timer);
                 last_timer = jiffies;
@@ -163,8 +162,8 @@ static void omap_set_vbus(struct musb *musb, int is_on)
 
         if (is_on) {
                 musb->is_active = 1;
-                musb->xceiv.default_a = 1;
-                musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
+                musb->xceiv->default_a = 1;
+                musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
                 devctl |= MUSB_DEVCTL_SESSION;
 
                 MUSB_HST_MODE(musb);
@@ -175,8 +174,8 @@ static void omap_set_vbus(struct musb *musb, int is_on)
                  * jumping right to B_IDLE...
                  */
 
-                musb->xceiv.default_a = 0;
-                musb->xceiv.state = OTG_STATE_B_IDLE;
+                musb->xceiv->default_a = 0;
+                musb->xceiv->state = OTG_STATE_B_IDLE;
                 devctl &= ~MUSB_DEVCTL_SESSION;
 
                 MUSB_DEV_MODE(musb);
@@ -188,10 +187,6 @@ static void omap_set_vbus(struct musb *musb, int is_on)
                 otg_state_string(musb),
                 musb_readb(musb->mregs, MUSB_DEVCTL));
 }
-static int omap_set_power(struct otg_transceiver *x, unsigned mA)
-{
-        return 0;
-}
 
 static int musb_platform_resume(struct musb *musb);
 
@@ -202,24 +197,6 @@ int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
         devctl |= MUSB_DEVCTL_SESSION;
         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 
-        switch (musb_mode) {
-#ifdef CONFIG_USB_MUSB_HDRC_HCD
-        case MUSB_HOST:
-                otg_set_host(&musb->xceiv, musb->xceiv.host);
-                break;
-#endif
-#ifdef CONFIG_USB_GADGET_MUSB_HDRC
-        case MUSB_PERIPHERAL:
-                otg_set_peripheral(&musb->xceiv, musb->xceiv.gadget);
-                break;
-#endif
-#ifdef CONFIG_USB_MUSB_OTG
-        case MUSB_OTG:
-                break;
-#endif
-        default:
-                return -EINVAL;
-        }
         return 0;
 }
 
@@ -231,6 +208,16 @@ int __init musb_platform_init(struct musb *musb)
         omap_cfg_reg(AE5_2430_USB0HS_STP);
 #endif
 
+        /* We require some kind of external transceiver, hooked
+         * up through ULPI.  TWL4030-family PMICs include one,
+         * which needs a driver, drivers aren't always needed.
+         */
+        musb->xceiv = otg_get_transceiver();
+        if (!musb->xceiv) {
+                pr_err("HS USB OTG: no transceiver configured\n");
+                return -ENODEV;
+        }
+
         musb_platform_resume(musb);
 
         l = omap_readl(OTG_SYSCONFIG);
@@ -240,7 +227,12 @@ int __init musb_platform_init(struct musb *musb)
         l &= ~AUTOIDLE;         /* disable auto idle */
         l &= ~NOIDLE;           /* remove possible noidle */
         l |= SMARTIDLE;         /* enable smart idle */
-        l |= AUTOIDLE;          /* enable auto idle */
+        /*
+         * MUSB AUTOIDLE don't work in 3430.
+         * Workaround by Richard Woodruff/TI
+         */
+        if (!cpu_is_omap3430())
+                l |= AUTOIDLE;          /* enable auto idle */
         omap_writel(l, OTG_SYSCONFIG);
 
         l = omap_readl(OTG_INTERFSEL);
@@ -257,9 +249,6 @@ int __init musb_platform_init(struct musb *musb)
 
         if (is_host_enabled(musb))
                 musb->board_set_vbus = omap_set_vbus;
-        if (is_peripheral_enabled(musb))
-                musb->xceiv.set_power = omap_set_power;
-        musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
 
         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
 
@@ -282,8 +271,7 @@ int musb_platform_suspend(struct musb *musb)
         l |= ENABLEWAKEUP;      /* enable wakeup */
         omap_writel(l, OTG_SYSCONFIG);
 
-        if (musb->xceiv.set_suspend)
-                musb->xceiv.set_suspend(&musb->xceiv, 1);
+        otg_set_suspend(musb->xceiv, 1);
 
         if (musb->set_clock)
                 musb->set_clock(musb->clock, 0);
@@ -300,8 +288,7 @@ static int musb_platform_resume(struct musb *musb)
         if (!musb->clock)
                 return 0;
 
-        if (musb->xceiv.set_suspend)
-                musb->xceiv.set_suspend(&musb->xceiv, 0);
+        otg_set_suspend(musb->xceiv, 0);
 
         if (musb->set_clock)
                 musb->set_clock(musb->clock, 1);
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index 4ac1477d3569..88b587c703e9 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -259,6 +259,8 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
                 tusb_fifo_read_unaligned(fifo, buf, len);
 }
 
+static struct musb *the_musb;
+
 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
 
 /* This is used by gadget drivers, and OTG transceiver logic, allowing
@@ -269,7 +271,7 @@ void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
  */
 static int tusb_draw_power(struct otg_transceiver *x, unsigned mA)
 {
-        struct musb     *musb = container_of(x, struct musb, xceiv);
+        struct musb     *musb = the_musb;
         void __iomem    *tbase = musb->ctrl_base;
         u32             reg;
 
@@ -419,7 +421,7 @@ static void musb_do_idle(unsigned long _musb)
 
         spin_lock_irqsave(&musb->lock, flags);
 
-        switch (musb->xceiv.state) {
+        switch (musb->xceiv->state) {
         case OTG_STATE_A_WAIT_BCON:
                 if ((musb->a_wait_bcon != 0)
                         && (musb->idle_timeout == 0
@@ -483,7 +485,7 @@ void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
 
         /* Never idle if active, or when VBUS timeout is not set as host */
         if (musb->is_active || ((musb->a_wait_bcon == 0)
-                        && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) {
+                        && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
                 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
                 del_timer(&musb_idle_timer);
                 last_timer = jiffies;
@@ -532,8 +534,8 @@ static void tusb_source_power(struct musb *musb, int is_on)
                 if (musb->set_clock)
                         musb->set_clock(musb->clock, 1);
                 timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
-                musb->xceiv.default_a = 1;
-                musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
+                musb->xceiv->default_a = 1;
+                musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
                 devctl |= MUSB_DEVCTL_SESSION;
 
                 conf |= TUSB_DEV_CONF_USB_HOST_MODE;
@@ -546,24 +548,24 @@ static void tusb_source_power(struct musb *musb, int is_on)
                 /* If ID pin is grounded, we want to be a_idle */
                 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
                 if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
-                        switch (musb->xceiv.state) {
+                        switch (musb->xceiv->state) {
                         case OTG_STATE_A_WAIT_VRISE:
                         case OTG_STATE_A_WAIT_BCON:
-                                musb->xceiv.state = OTG_STATE_A_WAIT_VFALL;
+                                musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
                                 break;
                         case OTG_STATE_A_WAIT_VFALL:
-                                musb->xceiv.state = OTG_STATE_A_IDLE;
+                                musb->xceiv->state = OTG_STATE_A_IDLE;
                                 break;
                         default:
-                                musb->xceiv.state = OTG_STATE_A_IDLE;
+                                musb->xceiv->state = OTG_STATE_A_IDLE;
                         }
                         musb->is_active = 0;
-                        musb->xceiv.default_a = 1;
+                        musb->xceiv->default_a = 1;
                         MUSB_HST_MODE(musb);
                 } else {
                         musb->is_active = 0;
-                        musb->xceiv.default_a = 0;
-                        musb->xceiv.state = OTG_STATE_B_IDLE;
+                        musb->xceiv->default_a = 0;
+                        musb->xceiv->state = OTG_STATE_B_IDLE;
                         MUSB_DEV_MODE(musb);
                 }
 
@@ -674,7 +676,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
                 else
                         default_a = is_host_enabled(musb);
                 DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
-                musb->xceiv.default_a = default_a;
+                musb->xceiv->default_a = default_a;
                 tusb_source_power(musb, default_a);
 
                 /* Don't allow idling immediately */
@@ -686,7 +688,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
         if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
 
                 /* B-dev state machine:  no vbus ~= disconnect */
-                if ((is_otg_enabled(musb) && !musb->xceiv.default_a)
+                if ((is_otg_enabled(musb) && !musb->xceiv->default_a)
                                 || !is_host_enabled(musb)) {
 #ifdef CONFIG_USB_MUSB_HDRC_HCD
                         /* ? musb_root_disconnect(musb); */
@@ -701,9 +703,9 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
 
                         if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
                                 DBG(1, "Forcing disconnect (no interrupt)\n");
-                                if (musb->xceiv.state != OTG_STATE_B_IDLE) {
+                                if (musb->xceiv->state != OTG_STATE_B_IDLE) {
                                         /* INTR_DISCONNECT can hide... */
-                                        musb->xceiv.state = OTG_STATE_B_IDLE;
+                                        musb->xceiv->state = OTG_STATE_B_IDLE;
                                         musb->int_usb |= MUSB_INTR_DISCONNECT;
                                 }
                                 musb->is_active = 0;
@@ -717,7 +719,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
                         DBG(2, "vbus change, %s, otg %03x\n",
                                 otg_state_string(musb), otg_stat);
 
-                        switch (musb->xceiv.state) {
+                        switch (musb->xceiv->state) {
                         case OTG_STATE_A_IDLE:
                                 DBG(2, "Got SRP, turning on VBUS\n");
                                 musb_set_vbus(musb, 1);
@@ -765,7 +767,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
 
                 DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
 
-                switch (musb->xceiv.state) {
+                switch (musb->xceiv->state) {
                 case OTG_STATE_A_WAIT_VRISE:
                         /* VBUS has probably been valid for a while now,
                          * but may well have bounced out of range a bit
@@ -777,7 +779,7 @@ tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
                                         DBG(2, "devctl %02x\n", devctl);
                                         break;
                                 }
-                                musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
+                                musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
                                 musb->is_active = 0;
                                 idle_timeout = jiffies
                                         + msecs_to_jiffies(musb->a_wait_bcon);
@@ -1093,9 +1095,14 @@ int __init musb_platform_init(struct musb *musb)
 {
         struct platform_device  *pdev;
         struct resource         *mem;
-        void __iomem            *sync;
+        void __iomem            *sync = NULL;
         int                     ret;
 
+        usb_nop_xceiv_register();
+        musb->xceiv = otg_get_transceiver();
+        if (!musb->xceiv)
+                return -ENODEV;
+
         pdev = to_platform_device(musb->controller);
 
         /* dma address for async dma */
@@ -1106,14 +1113,16 @@ int __init musb_platform_init(struct musb *musb)
         mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
         if (!mem) {
                 pr_debug("no sync dma resource?\n");
-                return -ENODEV;
+                ret = -ENODEV;
+                goto done;
         }
         musb->sync = mem->start;
 
         sync = ioremap(mem->start, mem->end - mem->start + 1);
         if (!sync) {
                 pr_debug("ioremap for sync failed\n");
-                return -ENOMEM;
+                ret = -ENOMEM;
+                goto done;
         }
         musb->sync_va = sync;
 
@@ -1126,28 +1135,37 @@ int __init musb_platform_init(struct musb *musb)
         if (ret) {
                 printk(KERN_ERR "Could not start tusb6010 (%d)\n",
                                 ret);
-                return -ENODEV;
+                goto done;
         }
         musb->isr = tusb_interrupt;
 
         if (is_host_enabled(musb))
                 musb->board_set_vbus = tusb_source_power;
-        if (is_peripheral_enabled(musb))
-                musb->xceiv.set_power = tusb_draw_power;
+        if (is_peripheral_enabled(musb)) {
+                musb->xceiv->set_power = tusb_draw_power;
+                the_musb = musb;
+        }
 
         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
 
+done:
+        if (ret < 0) {
+                if (sync)
+                        iounmap(sync);
+                usb_nop_xceiv_unregister();
+        }
         return ret;
 }
 
 int musb_platform_exit(struct musb *musb)
 {
         del_timer_sync(&musb_idle_timer);
+        the_musb = NULL;
 
         if (musb->board_set_power)
                 musb->board_set_power(0);
 
         iounmap(musb->sync_va);
-
+        usb_nop_xceiv_unregister();
         return 0;
 }
diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
index aa884d072f0b..69feeec1628c 100644
--- a/drivers/usb/otg/Kconfig
+++ b/drivers/usb/otg/Kconfig
@@ -59,4 +59,18 @@ config NOP_USB_XCEIV
          built-in with usb ip or which are autonomous and doesn't require any
          phy programming such as ISP1x04 etc.
 
+config USB_LANGWELL_OTG
+        tristate "Intel Langwell USB OTG dual-role support"
+        depends on USB && MRST
+        select USB_OTG
+        select USB_OTG_UTILS
+        help
+          Say Y here if you want to build Intel Langwell USB OTG
+          transciever driver in kernel. This driver implements role
+          switch between EHCI host driver and Langwell USB OTG
+          client driver.
+
+          To compile this driver as a module, choose M here: the
+          module will be called langwell_otg.
+
 endif # USB || OTG
diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile
index 208167856529..6d1abdd3c0ac 100644
--- a/drivers/usb/otg/Makefile
+++ b/drivers/usb/otg/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_USB_OTG_UTILS)	+= otg.o
 obj-$(CONFIG_USB_GPIO_VBUS)     += gpio_vbus.o
 obj-$(CONFIG_ISP1301_OMAP)      += isp1301_omap.o
 obj-$(CONFIG_TWL4030_USB)       += twl4030-usb.o
+obj-$(CONFIG_USB_LANGWELL_OTG)  += langwell_otg.o
 obj-$(CONFIG_NOP_USB_XCEIV)     += nop-usb-xceiv.o
 
 ccflags-$(CONFIG_USB_DEBUG)     += -DDEBUG
diff --git a/drivers/usb/otg/langwell_otg.c b/drivers/usb/otg/langwell_otg.c
new file mode 100644
index 000000000000..6f628d0e9f39
--- /dev/null
+++ b/drivers/usb/otg/langwell_otg.c
@@ -0,0 +1,1915 @@
+/*
+ * Intel Langwell USB OTG transceiver driver
+ * Copyright (C) 2008 - 2009, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+/* This driver helps to switch Langwell OTG controller function between host
+ * and peripheral. It works with EHCI driver and Langwell client controller
+ * driver together.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/moduleparam.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb.h>
+#include <linux/usb/otg.h>
+#include <linux/notifier.h>
+#include <asm/ipc_defs.h>
+#include <linux/delay.h>
+#include "../core/hcd.h"
+
+#include <linux/usb/langwell_otg.h>
+
+#define DRIVER_DESC             "Intel Langwell USB OTG transceiver driver"
+#define DRIVER_VERSION          "3.0.0.32L.0002"
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR("Henry Yuan <hang.yuan@intel.com>, Hao Wu <hao.wu@intel.com>");
+MODULE_VERSION(DRIVER_VERSION);
+MODULE_LICENSE("GPL");
+
+static const char driver_name[] = "langwell_otg";
+
+static int langwell_otg_probe(struct pci_dev *pdev,
+                        const struct pci_device_id *id);
+static void langwell_otg_remove(struct pci_dev *pdev);
+static int langwell_otg_suspend(struct pci_dev *pdev, pm_message_t message);
+static int langwell_otg_resume(struct pci_dev *pdev);
+
+static int langwell_otg_set_host(struct otg_transceiver *otg,
+                                struct usb_bus *host);
+static int langwell_otg_set_peripheral(struct otg_transceiver *otg,
+                                struct usb_gadget *gadget);
+static int langwell_otg_start_srp(struct otg_transceiver *otg);
+
+static const struct pci_device_id pci_ids[] = {{
+        .class =        ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
+        .class_mask =   ~0,
+        .vendor =       0x8086,
+        .device =       0x0811,
+        .subvendor =    PCI_ANY_ID,
+        .subdevice =    PCI_ANY_ID,
+}, { /* end: all zeroes */ }
+};
+
+static struct pci_driver otg_pci_driver = {
+        .name =         (char *) driver_name,
+        .id_table =     pci_ids,
+
+        .probe =        langwell_otg_probe,
+        .remove =       langwell_otg_remove,
+
+        .suspend =      langwell_otg_suspend,
+        .resume =       langwell_otg_resume,
+};
+
+static const char *state_string(enum usb_otg_state state)
+{
+        switch (state) {
+        case OTG_STATE_A_IDLE:
+                return "a_idle";
+        case OTG_STATE_A_WAIT_VRISE:
+                return "a_wait_vrise";
+        case OTG_STATE_A_WAIT_BCON:
+                return "a_wait_bcon";
+        case OTG_STATE_A_HOST:
+                return "a_host";
+        case OTG_STATE_A_SUSPEND:
+                return "a_suspend";
+        case OTG_STATE_A_PERIPHERAL:
+                return "a_peripheral";
+        case OTG_STATE_A_WAIT_VFALL:
+                return "a_wait_vfall";
+        case OTG_STATE_A_VBUS_ERR:
+                return "a_vbus_err";
+        case OTG_STATE_B_IDLE:
+                return "b_idle";
+        case OTG_STATE_B_SRP_INIT:
+                return "b_srp_init";
+        case OTG_STATE_B_PERIPHERAL:
+                return "b_peripheral";
+        case OTG_STATE_B_WAIT_ACON:
+                return "b_wait_acon";
+        case OTG_STATE_B_HOST:
+                return "b_host";
+        default:
+                return "UNDEFINED";
+        }
+}
+
+/* HSM timers */
+static inline struct langwell_otg_timer *otg_timer_initializer
+(void (*function)(unsigned long), unsigned long expires, unsigned long data)
+{
+        struct langwell_otg_timer *timer;
+        timer = kmalloc(sizeof(struct langwell_otg_timer), GFP_KERNEL);
+        timer->function = function;
+        timer->expires = expires;
+        timer->data = data;
+        return timer;
+}
+
+static struct langwell_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr,
+        *a_aidl_bdis_tmr, *b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_res_tmr,
+        *b_bus_suspend_tmr;
+
+static struct list_head active_timers;
+
+static struct langwell_otg *the_transceiver;
+
+/* host/client notify transceiver when event affects HNP state */
+void langwell_update_transceiver()
+{
+        otg_dbg("transceiver driver is notified\n");
+        queue_work(the_transceiver->qwork, &the_transceiver->work);
+}
+EXPORT_SYMBOL(langwell_update_transceiver);
+
+static int langwell_otg_set_host(struct otg_transceiver *otg,
+                                        struct usb_bus *host)
+{
+        otg->host = host;
+
+        return 0;
+}
+
+static int langwell_otg_set_peripheral(struct otg_transceiver *otg,
+                                        struct usb_gadget *gadget)
+{
+        otg->gadget = gadget;
+
+        return 0;
+}
+
+static int langwell_otg_set_power(struct otg_transceiver *otg,
+                                unsigned mA)
+{
+        return 0;
+}
+
+/* A-device drives vbus, controlled through PMIC CHRGCNTL register*/
+static void langwell_otg_drv_vbus(int on)
+{
+        struct ipc_pmic_reg_data        pmic_data = {0};
+        struct ipc_pmic_reg_data        battery_data;
+
+        /* Check if battery is attached or not */
+        battery_data.pmic_reg_data[0].register_address = 0xd2;
+        battery_data.ioc = 0;
+        battery_data.num_entries = 1;
+        if (ipc_pmic_register_read(&battery_data)) {
+                otg_dbg("Failed to read PMIC register 0xd2.\n");
+                return;
+        }
+
+        if ((battery_data.pmic_reg_data[0].value & 0x20) == 0) {
+                otg_dbg("no battery attached\n");
+                return;
+        }
+
+        /* Workaround for battery attachment issue */
+        if (battery_data.pmic_reg_data[0].value == 0x34) {
+                otg_dbg("battery \n");
+                return;
+        }
+
+        otg_dbg("battery attached\n");
+
+        pmic_data.ioc = 0;
+        pmic_data.pmic_reg_data[0].register_address = 0xD4;
+        pmic_data.num_entries = 1;
+        if (on)
+                pmic_data.pmic_reg_data[0].value = 0x20;
+        else
+                pmic_data.pmic_reg_data[0].value = 0xc0;
+
+        if (ipc_pmic_register_write(&pmic_data, TRUE))
+                otg_dbg("Failed to write PMIC.\n");
+
+}
+
+/* charge vbus or discharge vbus through a resistor to ground */
+static void langwell_otg_chrg_vbus(int on)
+{
+
+        u32     val;
+
+        val = readl(the_transceiver->regs + CI_OTGSC);
+
+        if (on)
+                writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_VC,
+                                the_transceiver->regs + CI_OTGSC);
+        else
+                writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_VD,
+                                the_transceiver->regs + CI_OTGSC);
+
+}
+
+/* Start SRP */
+static int langwell_otg_start_srp(struct otg_transceiver *otg)
+{
+        u32     val;
+
+        otg_dbg("Start SRP ->\n");
+
+        val = readl(the_transceiver->regs + CI_OTGSC);
+
+        writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HADP,
+                the_transceiver->regs + CI_OTGSC);
+
+        /* Check if the data plus is finished or not */
+        msleep(8);
+        val = readl(the_transceiver->regs + CI_OTGSC);
+        if (val & (OTGSC_HADP | OTGSC_DP))
+                otg_dbg("DataLine SRP Error\n");
+
+        /* FIXME: VBus SRP */
+
+        return 0;
+}
+
+
+/* stop SOF via bus_suspend */
+static void langwell_otg_loc_sof(int on)
+{
+        struct usb_hcd  *hcd;
+        int             err;
+
+        otg_dbg("loc_sof -> %d\n", on);
+
+        hcd = bus_to_hcd(the_transceiver->otg.host);
+        if (on)
+                err = hcd->driver->bus_resume(hcd);
+        else
+                err = hcd->driver->bus_suspend(hcd);
+
+        if (err)
+                otg_dbg("Failed to resume/suspend bus - %d\n", err);
+}
+
+static void langwell_otg_phy_low_power(int on)
+{
+        u32     val;
+
+        otg_dbg("phy low power mode-> %d\n", on);
+
+        val = readl(the_transceiver->regs + CI_HOSTPC1);
+        if (on)
+                writel(val | HOSTPC1_PHCD, the_transceiver->regs + CI_HOSTPC1);
+        else
+                writel(val & ~HOSTPC1_PHCD, the_transceiver->regs + CI_HOSTPC1);
+}
+
+/* Enable/Disable OTG interrupt */
+static void langwell_otg_intr(int on)
+{
+        u32 val;
+
+        otg_dbg("interrupt -> %d\n", on);
+
+        val = readl(the_transceiver->regs + CI_OTGSC);
+        if (on) {
+                val = val | (OTGSC_INTEN_MASK | OTGSC_IDPU);
+                writel(val, the_transceiver->regs + CI_OTGSC);
+        } else {
+                val = val & ~(OTGSC_INTEN_MASK | OTGSC_IDPU);
+                writel(val, the_transceiver->regs + CI_OTGSC);
+        }
+}
+
+/* set HAAR: Hardware Assist Auto-Reset */
+static void langwell_otg_HAAR(int on)
+{
+        u32     val;
+
+        otg_dbg("HAAR -> %d\n", on);
+
+        val = readl(the_transceiver->regs + CI_OTGSC);
+        if (on)
+                writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HAAR,
+                                the_transceiver->regs + CI_OTGSC);
+        else
+                writel((val & ~OTGSC_INTSTS_MASK) & ~OTGSC_HAAR,
+                                the_transceiver->regs + CI_OTGSC);
+}
+
+/* set HABA: Hardware Assist B-Disconnect to A-Connect */
+static void langwell_otg_HABA(int on)
+{
+        u32     val;
+
+        otg_dbg("HABA -> %d\n", on);
+
+        val = readl(the_transceiver->regs + CI_OTGSC);
+        if (on)
+                writel((val & ~OTGSC_INTSTS_MASK) | OTGSC_HABA,
+                                the_transceiver->regs + CI_OTGSC);
+        else
+                writel((val & ~OTGSC_INTSTS_MASK) & ~OTGSC_HABA,
+                                the_transceiver->regs + CI_OTGSC);
+}
+
+static int langwell_otg_check_se0_srp(int on)
+{
+        u32 val;
+
+        int delay_time = TB_SE0_SRP * 10; /* step is 100us */
+
+        otg_dbg("check_se0_srp -> \n");
+
+        do {
+                udelay(100);
+                if (!delay_time--)
+                        break;
+                val = readl(the_transceiver->regs + CI_PORTSC1);
+                val &= PORTSC_LS;
+        } while (!val);
+
+        otg_dbg("check_se0_srp <- \n");
+        return val;
+}
+
+/* The timeout callback function to set time out bit */
+static void set_tmout(unsigned long indicator)
+{
+        *(int *)indicator = 1;
+}
+
+void langwell_otg_nsf_msg(unsigned long indicator)
+{
+        switch (indicator) {
+        case 2:
+        case 4:
+        case 6:
+        case 7:
+                printk(KERN_ERR "OTG:NSF-%lu - deivce not responding\n",
+                                indicator);
+                break;
+        case 3:
+                printk(KERN_ERR "OTG:NSF-%lu - deivce not supported\n",
+                                indicator);
+                break;
+        default:
+                printk(KERN_ERR "Do not have this kind of NSF\n");
+                break;
+        }
+}
+
+/* Initialize timers */
+static void langwell_otg_init_timers(struct otg_hsm *hsm)
+{
+        /* HSM used timers */
+        a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
+                                (unsigned long)&hsm->a_wait_vrise_tmout);
+        a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON,
+                                (unsigned long)&hsm->a_wait_bcon_tmout);
+        a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
+                                (unsigned long)&hsm->a_aidl_bdis_tmout);
+        b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST,
+                                (unsigned long)&hsm->b_ase0_brst_tmout);
+        b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
+                                (unsigned long)&hsm->b_se0_srp);
+        b_srp_res_tmr = otg_timer_initializer(&set_tmout, TB_SRP_RES,
+                                (unsigned long)&hsm->b_srp_res_tmout);
+        b_bus_suspend_tmr = otg_timer_initializer(&set_tmout, TB_BUS_SUSPEND,
+                                (unsigned long)&hsm->b_bus_suspend_tmout);
+}
+
+/* Free timers */
+static void langwell_otg_free_timers(void)
+{
+        kfree(a_wait_vrise_tmr);
+        kfree(a_wait_bcon_tmr);
+        kfree(a_aidl_bdis_tmr);
+        kfree(b_ase0_brst_tmr);
+        kfree(b_se0_srp_tmr);
+        kfree(b_srp_res_tmr);
+        kfree(b_bus_suspend_tmr);
+}
+
+/* Add timer to timer list */
+static void langwell_otg_add_timer(void *gtimer)
+{
+        struct langwell_otg_timer *timer = (struct langwell_otg_timer *)gtimer;
+        struct langwell_otg_timer *tmp_timer;
+        u32     val32;
+
+        /* Check if the timer is already in the active list,
+         * if so update timer count
+         */
+        list_for_each_entry(tmp_timer, &active_timers, list)
+                if (tmp_timer == timer) {
+                        timer->count = timer->expires;
+                        return;
+                }
+        timer->count = timer->expires;
+
+        if (list_empty(&active_timers)) {
+                val32 = readl(the_transceiver->regs + CI_OTGSC);
+                writel(val32 | OTGSC_1MSE, the_transceiver->regs + CI_OTGSC);
+        }
+
+        list_add_tail(&timer->list, &active_timers);
+}
+
+/* Remove timer from the timer list; clear timeout status */
+static void langwell_otg_del_timer(void *gtimer)
+{
+        struct langwell_otg_timer *timer = (struct langwell_otg_timer *)gtimer;
+        struct langwell_otg_timer *tmp_timer, *del_tmp;
+        u32 val32;
+
+        list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
+                if (tmp_timer == timer)
+                        list_del(&timer->list);
+
+        if (list_empty(&active_timers)) {
+                val32 = readl(the_transceiver->regs + CI_OTGSC);
+                writel(val32 & ~OTGSC_1MSE, the_transceiver->regs + CI_OTGSC);
+        }
+}
+
+/* Reduce timer count by 1, and find timeout conditions.*/
+static int langwell_otg_tick_timer(u32 *int_sts)
+{
+        struct langwell_otg_timer *tmp_timer, *del_tmp;
+        int expired = 0;
+
+        list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
+                tmp_timer->count--;
+                /* check if timer expires */
+                if (!tmp_timer->count) {
+                        list_del(&tmp_timer->list);
+                        tmp_timer->function(tmp_timer->data);
+                        expired = 1;
+                }
+        }
+
+        if (list_empty(&active_timers)) {
+                otg_dbg("tick timer: disable 1ms int\n");
+                *int_sts = *int_sts & ~OTGSC_1MSE;
+        }
+        return expired;
+}
+
+static void reset_otg(void)
+{
+        u32     val;
+        int     delay_time = 1000;
+
+        otg_dbg("reseting OTG controller ...\n");
+        val = readl(the_transceiver->regs + CI_USBCMD);
+        writel(val | USBCMD_RST, the_transceiver->regs + CI_USBCMD);
+        do {
+                udelay(100);
+                if (!delay_time--)
+                        otg_dbg("reset timeout\n");
+                val = readl(the_transceiver->regs + CI_USBCMD);
+                val &= USBCMD_RST;
+        } while (val != 0);
+        otg_dbg("reset done.\n");
+}
+
+static void set_host_mode(void)
+{
+        u32     val;
+
+        reset_otg();
+        val = readl(the_transceiver->regs + CI_USBMODE);
+        val = (val & (~USBMODE_CM)) | USBMODE_HOST;
+        writel(val, the_transceiver->regs + CI_USBMODE);
+}
+
+static void set_client_mode(void)
+{
+        u32     val;
+
+        reset_otg();
+        val = readl(the_transceiver->regs + CI_USBMODE);
+        val = (val & (~USBMODE_CM)) | USBMODE_DEVICE;
+        writel(val, the_transceiver->regs + CI_USBMODE);
+}
+
+static void init_hsm(void)
+{
+        struct langwell_otg     *langwell = the_transceiver;
+        u32                     val32;
+
+        /* read OTGSC after reset */
+        val32 = readl(langwell->regs + CI_OTGSC);
+        otg_dbg("%s: OTGSC init value = 0x%x\n", __func__, val32);
+
+        /* set init state */
+        if (val32 & OTGSC_ID) {
+                langwell->hsm.id = 1;
+                langwell->otg.default_a = 0;
+                set_client_mode();
+                langwell->otg.state = OTG_STATE_B_IDLE;
+                langwell_otg_drv_vbus(0);
+        } else {
+                langwell->hsm.id = 0;
+                langwell->otg.default_a = 1;
+                set_host_mode();
+                langwell->otg.state = OTG_STATE_A_IDLE;
+        }
+
+        /* set session indicator */
+        if (val32 & OTGSC_BSE)
+                langwell->hsm.b_sess_end = 1;
+        if (val32 & OTGSC_BSV)
+                langwell->hsm.b_sess_vld = 1;
+        if (val32 & OTGSC_ASV)
+                langwell->hsm.a_sess_vld = 1;
+        if (val32 & OTGSC_AVV)
+                langwell->hsm.a_vbus_vld = 1;
+
+        /* defautly power the bus */
+        langwell->hsm.a_bus_req = 1;
+        langwell->hsm.a_bus_drop = 0;
+        /* defautly don't request bus as B device */
+        langwell->hsm.b_bus_req = 0;
+        /* no system error */
+        langwell->hsm.a_clr_err = 0;
+}
+
+static irqreturn_t otg_dummy_irq(int irq, void *_dev)
+{
+        void __iomem    *reg_base = _dev;
+        u32     val;
+        u32     int_mask = 0;
+
+        val = readl(reg_base + CI_USBMODE);
+        if ((val & USBMODE_CM) != USBMODE_DEVICE)
+                return IRQ_NONE;
+
+        val = readl(reg_base + CI_USBSTS);
+        int_mask = val & INTR_DUMMY_MASK;
+
+        if (int_mask == 0)
+                return IRQ_NONE;
+
+        /* clear hsm.b_conn here since host driver can't detect it
+        *  otg_dummy_irq called means B-disconnect happened.
+        */
+        if (the_transceiver->hsm.b_conn) {
+                the_transceiver->hsm.b_conn = 0;
+                if (spin_trylock(&the_transceiver->wq_lock)) {
+                        queue_work(the_transceiver->qwork,
+                                &the_transceiver->work);
+                        spin_unlock(&the_transceiver->wq_lock);
+                }
+        }
+        /* Clear interrupts */
+        writel(int_mask, reg_base + CI_USBSTS);
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t otg_irq(int irq, void *_dev)
+{
+        struct  langwell_otg *langwell = _dev;
+        u32     int_sts, int_en;
+        u32     int_mask = 0;
+        int     flag = 0;
+
+        int_sts = readl(langwell->regs + CI_OTGSC);
+        int_en = (int_sts & OTGSC_INTEN_MASK) >> 8;
+        int_mask = int_sts & int_en;
+        if (int_mask == 0)
+                return IRQ_NONE;
+
+        if (int_mask & OTGSC_IDIS) {
+                otg_dbg("%s: id change int\n", __func__);
+                langwell->hsm.id = (int_sts & OTGSC_ID) ? 1 : 0;
+                flag = 1;
+        }
+        if (int_mask & OTGSC_DPIS) {
+                otg_dbg("%s: data pulse int\n", __func__);
+                langwell->hsm.a_srp_det = (int_sts & OTGSC_DPS) ? 1 : 0;
+                flag = 1;
+        }
+        if (int_mask & OTGSC_BSEIS) {
+                otg_dbg("%s: b session end int\n", __func__);
+                langwell->hsm.b_sess_end = (int_sts & OTGSC_BSE) ? 1 : 0;
+                flag = 1;
+        }
+        if (int_mask & OTGSC_BSVIS) {
+                otg_dbg("%s: b session valid int\n", __func__);
+                langwell->hsm.b_sess_vld = (int_sts & OTGSC_BSV) ? 1 : 0;
+                flag = 1;
+        }
+        if (int_mask & OTGSC_ASVIS) {
+                otg_dbg("%s: a session valid int\n", __func__);
+                langwell->hsm.a_sess_vld = (int_sts & OTGSC_ASV) ? 1 : 0;
+                flag = 1;
+        }
+        if (int_mask & OTGSC_AVVIS) {
+                otg_dbg("%s: a vbus valid int\n", __func__);
+                langwell->hsm.a_vbus_vld = (int_sts & OTGSC_AVV) ? 1 : 0;
+                flag = 1;
+        }
+
+        if (int_mask & OTGSC_1MSS) {
+                /* need to schedule otg_work if any timer is expired */
+                if (langwell_otg_tick_timer(&int_sts))
+                        flag = 1;
+        }
+
+        writel((int_sts & ~OTGSC_INTSTS_MASK) | int_mask,
+                        langwell->regs + CI_OTGSC);
+        if (flag)
+                queue_work(langwell->qwork, &langwell->work);
+
+        return IRQ_HANDLED;
+}
+
+static void langwell_otg_work(struct work_struct *work)
+{
+        struct langwell_otg *langwell = container_of(work,
+                                        struct langwell_otg, work);
+        int     retval;
+
+        otg_dbg("%s: old state = %s\n", __func__,
+                        state_string(langwell->otg.state));
+
+        switch (langwell->otg.state) {
+        case OTG_STATE_UNDEFINED:
+        case OTG_STATE_B_IDLE:
+                if (!langwell->hsm.id) {
+                        langwell_otg_del_timer(b_srp_res_tmr);
+                        langwell->otg.default_a = 1;
+                        langwell->hsm.a_srp_det = 0;
+
+                        langwell_otg_chrg_vbus(0);
+                        langwell_otg_drv_vbus(0);
+
+                        set_host_mode();
+                        langwell->otg.state = OTG_STATE_A_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (langwell->hsm.b_srp_res_tmout) {
+                        langwell->hsm.b_srp_res_tmout = 0;
+                        langwell->hsm.b_bus_req = 0;
+                        langwell_otg_nsf_msg(6);
+                } else if (langwell->hsm.b_sess_vld) {
+                        langwell_otg_del_timer(b_srp_res_tmr);
+                        langwell->hsm.b_sess_end = 0;
+                        langwell->hsm.a_bus_suspend = 0;
+
+                        langwell_otg_chrg_vbus(0);
+                        if (langwell->client_ops) {
+                                langwell->client_ops->resume(langwell->pdev);
+                                langwell->otg.state = OTG_STATE_B_PERIPHERAL;
+                        } else
+                                otg_dbg("client driver not loaded.\n");
+
+                } else if (langwell->hsm.b_bus_req &&
+                                (langwell->hsm.b_sess_end)) {
+                        /* workaround for b_se0_srp detection */
+                        retval = langwell_otg_check_se0_srp(0);
+                        if (retval) {
+                                langwell->hsm.b_bus_req = 0;
+                                otg_dbg("LS is not SE0, try again later\n");
+                        } else {
+                                /* Start SRP */
+                                langwell_otg_start_srp(&langwell->otg);
+                                langwell_otg_add_timer(b_srp_res_tmr);
+                        }
+                }
+                break;
+        case OTG_STATE_B_SRP_INIT:
+                if (!langwell->hsm.id) {
+                        langwell->otg.default_a = 1;
+                        langwell->hsm.a_srp_det = 0;
+
+                        langwell_otg_drv_vbus(0);
+                        langwell_otg_chrg_vbus(0);
+
+                        langwell->otg.state = OTG_STATE_A_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (langwell->hsm.b_sess_vld) {
+                        langwell_otg_chrg_vbus(0);
+                        if (langwell->client_ops) {
+                                langwell->client_ops->resume(langwell->pdev);
+                                langwell->otg.state = OTG_STATE_B_PERIPHERAL;
+                        } else
+                                otg_dbg("client driver not loaded.\n");
+                }
+                break;
+        case OTG_STATE_B_PERIPHERAL:
+                if (!langwell->hsm.id) {
+                        langwell->otg.default_a = 1;
+                        langwell->hsm.a_srp_det = 0;
+
+                        langwell_otg_drv_vbus(0);
+                        langwell_otg_chrg_vbus(0);
+                        set_host_mode();
+
+                        if (langwell->client_ops) {
+                                langwell->client_ops->suspend(langwell->pdev,
+                                        PMSG_FREEZE);
+                        } else
+                                otg_dbg("client driver has been removed.\n");
+
+                        langwell->otg.state = OTG_STATE_A_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (!langwell->hsm.b_sess_vld) {
+                        langwell->hsm.b_hnp_enable = 0;
+
+                        if (langwell->client_ops) {
+                                langwell->client_ops->suspend(langwell->pdev,
+                                        PMSG_FREEZE);
+                        } else
+                                otg_dbg("client driver has been removed.\n");
+
+                        langwell->otg.state = OTG_STATE_B_IDLE;
+                } else if (langwell->hsm.b_bus_req && langwell->hsm.b_hnp_enable
+                        && langwell->hsm.a_bus_suspend) {
+
+                        if (langwell->client_ops) {
+                                langwell->client_ops->suspend(langwell->pdev,
+                                        PMSG_FREEZE);
+                        } else
+                                otg_dbg("client driver has been removed.\n");
+
+                        langwell_otg_HAAR(1);
+                        langwell->hsm.a_conn = 0;
+
+                        if (langwell->host_ops) {
+                                langwell->host_ops->probe(langwell->pdev,
+                                        langwell->host_ops->id_table);
+                                langwell->otg.state = OTG_STATE_B_WAIT_ACON;
+                        } else
+                                otg_dbg("host driver not loaded.\n");
+
+                        langwell->hsm.a_bus_resume = 0;
+                        langwell->hsm.b_ase0_brst_tmout = 0;
+                        langwell_otg_add_timer(b_ase0_brst_tmr);
+                }
+                break;
+
+        case OTG_STATE_B_WAIT_ACON:
+                if (!langwell->hsm.id) {
+                        langwell_otg_del_timer(b_ase0_brst_tmr);
+                        langwell->otg.default_a = 1;
+                        langwell->hsm.a_srp_det = 0;
+
+                        langwell_otg_drv_vbus(0);
+                        langwell_otg_chrg_vbus(0);
+                        set_host_mode();
+
+                        langwell_otg_HAAR(0);
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell->otg.state = OTG_STATE_A_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (!langwell->hsm.b_sess_vld) {
+                        langwell_otg_del_timer(b_ase0_brst_tmr);
+                        langwell->hsm.b_hnp_enable = 0;
+                        langwell->hsm.b_bus_req = 0;
+                        langwell_otg_chrg_vbus(0);
+                        langwell_otg_HAAR(0);
+
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell->otg.state = OTG_STATE_B_IDLE;
+                } else if (langwell->hsm.a_conn) {
+                        langwell_otg_del_timer(b_ase0_brst_tmr);
+                        langwell_otg_HAAR(0);
+                        langwell->otg.state = OTG_STATE_B_HOST;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (langwell->hsm.a_bus_resume ||
+                                langwell->hsm.b_ase0_brst_tmout) {
+                        langwell_otg_del_timer(b_ase0_brst_tmr);
+                        langwell_otg_HAAR(0);
+                        langwell_otg_nsf_msg(7);
+
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+
+                        langwell->hsm.a_bus_suspend = 0;
+                        langwell->hsm.b_bus_req = 0;
+
+                        if (langwell->client_ops)
+                                langwell->client_ops->resume(langwell->pdev);
+                        else
+                                otg_dbg("client driver not loaded.\n");
+
+                        langwell->otg.state = OTG_STATE_B_PERIPHERAL;
+                }
+                break;
+
+        case OTG_STATE_B_HOST:
+                if (!langwell->hsm.id) {
+                        langwell->otg.default_a = 1;
+                        langwell->hsm.a_srp_det = 0;
+
+                        langwell_otg_drv_vbus(0);
+                        langwell_otg_chrg_vbus(0);
+                        set_host_mode();
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell->otg.state = OTG_STATE_A_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (!langwell->hsm.b_sess_vld) {
+                        langwell->hsm.b_hnp_enable = 0;
+                        langwell->hsm.b_bus_req = 0;
+                        langwell_otg_chrg_vbus(0);
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell->otg.state = OTG_STATE_B_IDLE;
+                } else if ((!langwell->hsm.b_bus_req) ||
+                                (!langwell->hsm.a_conn)) {
+                        langwell->hsm.b_bus_req = 0;
+                        langwell_otg_loc_sof(0);
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+
+                        langwell->hsm.a_bus_suspend = 0;
+
+                        if (langwell->client_ops)
+                                langwell->client_ops->resume(langwell->pdev);
+                        else
+                                otg_dbg("client driver not loaded.\n");
+
+                        langwell->otg.state = OTG_STATE_B_PERIPHERAL;
+                }
+                break;
+
+        case OTG_STATE_A_IDLE:
+                langwell->otg.default_a = 1;
+                if (langwell->hsm.id) {
+                        langwell->otg.default_a = 0;
+                        langwell->hsm.b_bus_req = 0;
+                        langwell_otg_drv_vbus(0);
+                        langwell_otg_chrg_vbus(0);
+
+                        langwell->otg.state = OTG_STATE_B_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (langwell->hsm.a_sess_vld) {
+                        langwell_otg_drv_vbus(1);
+                        langwell->hsm.a_srp_det = 1;
+                        langwell->hsm.a_wait_vrise_tmout = 0;
+                        langwell_otg_add_timer(a_wait_vrise_tmr);
+                        langwell->otg.state = OTG_STATE_A_WAIT_VRISE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (!langwell->hsm.a_bus_drop &&
+                        (langwell->hsm.a_srp_det || langwell->hsm.a_bus_req)) {
+                        langwell_otg_drv_vbus(1);
+                        langwell->hsm.a_wait_vrise_tmout = 0;
+                        langwell_otg_add_timer(a_wait_vrise_tmr);
+                        langwell->otg.state = OTG_STATE_A_WAIT_VRISE;
+                        queue_work(langwell->qwork, &langwell->work);
+                }
+                break;
+        case OTG_STATE_A_WAIT_VRISE:
+                if (langwell->hsm.id) {
+                        langwell_otg_del_timer(a_wait_vrise_tmr);
+                        langwell->hsm.b_bus_req = 0;
+                        langwell->otg.default_a = 0;
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_B_IDLE;
+                } else if (langwell->hsm.a_vbus_vld) {
+                        langwell_otg_del_timer(a_wait_vrise_tmr);
+                        if (langwell->host_ops)
+                                langwell->host_ops->probe(langwell->pdev,
+                                                langwell->host_ops->id_table);
+                        else
+                                otg_dbg("host driver not loaded.\n");
+                        langwell->hsm.b_conn = 0;
+                        langwell->hsm.a_set_b_hnp_en = 0;
+                        langwell->hsm.a_wait_bcon_tmout = 0;
+                        langwell_otg_add_timer(a_wait_bcon_tmr);
+                        langwell->otg.state = OTG_STATE_A_WAIT_BCON;
+                } else if (langwell->hsm.a_wait_vrise_tmout) {
+                        if (langwell->hsm.a_vbus_vld) {
+                                if (langwell->host_ops)
+                                        langwell->host_ops->probe(
+                                                langwell->pdev,
+                                                langwell->host_ops->id_table);
+                                else
+                                        otg_dbg("host driver not loaded.\n");
+                                langwell->hsm.b_conn = 0;
+                                langwell->hsm.a_set_b_hnp_en = 0;
+                                langwell->hsm.a_wait_bcon_tmout = 0;
+                                langwell_otg_add_timer(a_wait_bcon_tmr);
+                                langwell->otg.state = OTG_STATE_A_WAIT_BCON;
+                        } else {
+                                langwell_otg_drv_vbus(0);
+                                langwell->otg.state = OTG_STATE_A_VBUS_ERR;
+                        }
+                }
+                break;
+        case OTG_STATE_A_WAIT_BCON:
+                if (langwell->hsm.id) {
+                        langwell_otg_del_timer(a_wait_bcon_tmr);
+
+                        langwell->otg.default_a = 0;
+                        langwell->hsm.b_bus_req = 0;
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_B_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (!langwell->hsm.a_vbus_vld) {
+                        langwell_otg_del_timer(a_wait_bcon_tmr);
+
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_A_VBUS_ERR;
+                } else if (langwell->hsm.a_bus_drop ||
+                                (langwell->hsm.a_wait_bcon_tmout &&
+                                !langwell->hsm.a_bus_req)) {
+                        langwell_otg_del_timer(a_wait_bcon_tmr);
+
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_A_WAIT_VFALL;
+                } else if (langwell->hsm.b_conn) {
+                        langwell_otg_del_timer(a_wait_bcon_tmr);
+
+                        langwell->hsm.a_suspend_req = 0;
+                        langwell->otg.state = OTG_STATE_A_HOST;
+                        if (!langwell->hsm.a_bus_req &&
+                                langwell->hsm.a_set_b_hnp_en) {
+                                /* It is not safe enough to do a fast
+                                 * transistion from A_WAIT_BCON to
+                                 * A_SUSPEND */
+                                msleep(10000);
+                                if (langwell->hsm.a_bus_req)
+                                        break;
+
+                                if (request_irq(langwell->pdev->irq,
+                                        otg_dummy_irq, IRQF_SHARED,
+                                        driver_name, langwell->regs) != 0) {
+                                        otg_dbg("request interrupt %d fail\n",
+                                        langwell->pdev->irq);
+                                }
+
+                                langwell_otg_HABA(1);
+                                langwell->hsm.b_bus_resume = 0;
+                                langwell->hsm.a_aidl_bdis_tmout = 0;
+                                langwell_otg_add_timer(a_aidl_bdis_tmr);
+
+                                langwell_otg_loc_sof(0);
+                                langwell->otg.state = OTG_STATE_A_SUSPEND;
+                        } else if (!langwell->hsm.a_bus_req &&
+                                !langwell->hsm.a_set_b_hnp_en) {
+                                struct pci_dev *pdev = langwell->pdev;
+                                if (langwell->host_ops)
+                                        langwell->host_ops->remove(pdev);
+                                else
+                                        otg_dbg("host driver removed.\n");
+                                langwell_otg_drv_vbus(0);
+                                langwell->otg.state = OTG_STATE_A_WAIT_VFALL;
+                        }
+                }
+                break;
+        case OTG_STATE_A_HOST:
+                if (langwell->hsm.id) {
+                        langwell->otg.default_a = 0;
+                        langwell->hsm.b_bus_req = 0;
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_B_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (langwell->hsm.a_bus_drop ||
+                (!langwell->hsm.a_set_b_hnp_en && !langwell->hsm.a_bus_req)) {
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_A_WAIT_VFALL;
+                } else if (!langwell->hsm.a_vbus_vld) {
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_A_VBUS_ERR;
+                } else if (langwell->hsm.a_set_b_hnp_en
+                                && !langwell->hsm.a_bus_req) {
+                        /* Set HABA to enable hardware assistance to signal
+                         *  A-connect after receiver B-disconnect. Hardware
+                         *  will then set client mode and enable URE, SLE and
+                         *  PCE after the assistance. otg_dummy_irq is used to
+                         *  clean these ints when client driver is not resumed.
+                         */
+                        if (request_irq(langwell->pdev->irq,
+                                otg_dummy_irq, IRQF_SHARED, driver_name,
+                                langwell->regs) != 0) {
+                                otg_dbg("request interrupt %d failed\n",
+                                                langwell->pdev->irq);
+                        }
+
+                        /* set HABA */
+                        langwell_otg_HABA(1);
+                        langwell->hsm.b_bus_resume = 0;
+                        langwell->hsm.a_aidl_bdis_tmout = 0;
+                        langwell_otg_add_timer(a_aidl_bdis_tmr);
+                        langwell_otg_loc_sof(0);
+                        langwell->otg.state = OTG_STATE_A_SUSPEND;
+                } else if (!langwell->hsm.b_conn || !langwell->hsm.a_bus_req) {
+                        langwell->hsm.a_wait_bcon_tmout = 0;
+                        langwell->hsm.a_set_b_hnp_en = 0;
+                        langwell_otg_add_timer(a_wait_bcon_tmr);
+                        langwell->otg.state = OTG_STATE_A_WAIT_BCON;
+                }
+                break;
+        case OTG_STATE_A_SUSPEND:
+                if (langwell->hsm.id) {
+                        langwell_otg_del_timer(a_aidl_bdis_tmr);
+                        langwell_otg_HABA(0);
+                        free_irq(langwell->pdev->irq, langwell->regs);
+                        langwell->otg.default_a = 0;
+                        langwell->hsm.b_bus_req = 0;
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_B_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (langwell->hsm.a_bus_req ||
+                                langwell->hsm.b_bus_resume) {
+                        langwell_otg_del_timer(a_aidl_bdis_tmr);
+                        langwell_otg_HABA(0);
+                        free_irq(langwell->pdev->irq, langwell->regs);
+                        langwell->hsm.a_suspend_req = 0;
+                        langwell_otg_loc_sof(1);
+                        langwell->otg.state = OTG_STATE_A_HOST;
+                } else if (langwell->hsm.a_aidl_bdis_tmout ||
+                                langwell->hsm.a_bus_drop) {
+                        langwell_otg_del_timer(a_aidl_bdis_tmr);
+                        langwell_otg_HABA(0);
+                        free_irq(langwell->pdev->irq, langwell->regs);
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_A_WAIT_VFALL;
+                } else if (!langwell->hsm.b_conn &&
+                                langwell->hsm.a_set_b_hnp_en) {
+                        langwell_otg_del_timer(a_aidl_bdis_tmr);
+                        langwell_otg_HABA(0);
+                        free_irq(langwell->pdev->irq, langwell->regs);
+
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+
+                        langwell->hsm.b_bus_suspend = 0;
+                        langwell->hsm.b_bus_suspend_vld = 0;
+                        langwell->hsm.b_bus_suspend_tmout = 0;
+
+                        /* msleep(200); */
+                        if (langwell->client_ops)
+                                langwell->client_ops->resume(langwell->pdev);
+                        else
+                                otg_dbg("client driver not loaded.\n");
+
+                        langwell_otg_add_timer(b_bus_suspend_tmr);
+                        langwell->otg.state = OTG_STATE_A_PERIPHERAL;
+                        break;
+                } else if (!langwell->hsm.a_vbus_vld) {
+                        langwell_otg_del_timer(a_aidl_bdis_tmr);
+                        langwell_otg_HABA(0);
+                        free_irq(langwell->pdev->irq, langwell->regs);
+                        if (langwell->host_ops)
+                                langwell->host_ops->remove(langwell->pdev);
+                        else
+                                otg_dbg("host driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_A_VBUS_ERR;
+                }
+                break;
+        case OTG_STATE_A_PERIPHERAL:
+                if (langwell->hsm.id) {
+                        langwell_otg_del_timer(b_bus_suspend_tmr);
+                        langwell->otg.default_a = 0;
+                        langwell->hsm.b_bus_req = 0;
+                        if (langwell->client_ops)
+                                langwell->client_ops->suspend(langwell->pdev,
+                                        PMSG_FREEZE);
+                        else
+                                otg_dbg("client driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_B_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (!langwell->hsm.a_vbus_vld) {
+                        langwell_otg_del_timer(b_bus_suspend_tmr);
+                        if (langwell->client_ops)
+                                langwell->client_ops->suspend(langwell->pdev,
+                                        PMSG_FREEZE);
+                        else
+                                otg_dbg("client driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_A_VBUS_ERR;
+                } else if (langwell->hsm.a_bus_drop) {
+                        langwell_otg_del_timer(b_bus_suspend_tmr);
+                        if (langwell->client_ops)
+                                langwell->client_ops->suspend(langwell->pdev,
+                                        PMSG_FREEZE);
+                        else
+                                otg_dbg("client driver has been removed.\n");
+                        langwell_otg_drv_vbus(0);
+                        langwell->otg.state = OTG_STATE_A_WAIT_VFALL;
+                } else if (langwell->hsm.b_bus_suspend) {
+                        langwell_otg_del_timer(b_bus_suspend_tmr);
+                        if (langwell->client_ops)
+                                langwell->client_ops->suspend(langwell->pdev,
+                                        PMSG_FREEZE);
+                        else
+                                otg_dbg("client driver has been removed.\n");
+
+                        if (langwell->host_ops)
+                                langwell->host_ops->probe(langwell->pdev,
+                                                langwell->host_ops->id_table);
+                        else
+                                otg_dbg("host driver not loaded.\n");
+                        langwell->hsm.a_set_b_hnp_en = 0;
+                        langwell->hsm.a_wait_bcon_tmout = 0;
+                        langwell_otg_add_timer(a_wait_bcon_tmr);
+                        langwell->otg.state = OTG_STATE_A_WAIT_BCON;
+                } else if (langwell->hsm.b_bus_suspend_tmout) {
+                        u32     val;
+                        val = readl(langwell->regs + CI_PORTSC1);
+                        if (!(val & PORTSC_SUSP))
+                                break;
+                        if (langwell->client_ops)
+                                langwell->client_ops->suspend(langwell->pdev,
+                                                PMSG_FREEZE);
+                        else
+                                otg_dbg("client driver has been removed.\n");
+                        if (langwell->host_ops)
+                                langwell->host_ops->probe(langwell->pdev,
+                                                langwell->host_ops->id_table);
+                        else
+                                otg_dbg("host driver not loaded.\n");
+                        langwell->hsm.a_set_b_hnp_en = 0;
+                        langwell->hsm.a_wait_bcon_tmout = 0;
+                        langwell_otg_add_timer(a_wait_bcon_tmr);
+                        langwell->otg.state = OTG_STATE_A_WAIT_BCON;
+                }
+                break;
+        case OTG_STATE_A_VBUS_ERR:
+                if (langwell->hsm.id) {
+                        langwell->otg.default_a = 0;
+                        langwell->hsm.a_clr_err = 0;
+                        langwell->hsm.a_srp_det = 0;
+                        langwell->otg.state = OTG_STATE_B_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (langwell->hsm.a_clr_err) {
+                        langwell->hsm.a_clr_err = 0;
+                        langwell->hsm.a_srp_det = 0;
+                        reset_otg();
+                        init_hsm();
+                        if (langwell->otg.state == OTG_STATE_A_IDLE)
+                                queue_work(langwell->qwork, &langwell->work);
+                }
+                break;
+        case OTG_STATE_A_WAIT_VFALL:
+                if (langwell->hsm.id) {
+                        langwell->otg.default_a = 0;
+                        langwell->otg.state = OTG_STATE_B_IDLE;
+                        queue_work(langwell->qwork, &langwell->work);
+                } else if (langwell->hsm.a_bus_req) {
+                        langwell_otg_drv_vbus(1);
+                        langwell->hsm.a_wait_vrise_tmout = 0;
+                        langwell_otg_add_timer(a_wait_vrise_tmr);
+                        langwell->otg.state = OTG_STATE_A_WAIT_VRISE;
+                } else if (!langwell->hsm.a_sess_vld) {
+                        langwell->hsm.a_srp_det = 0;
+                        langwell_otg_drv_vbus(0);
+                        set_host_mode();
+                        langwell->otg.state = OTG_STATE_A_IDLE;
+                }
+                break;
+        default:
+                ;
+        }
+
+        otg_dbg("%s: new state = %s\n", __func__,
+                        state_string(langwell->otg.state));
+}
+
+        static ssize_t
+show_registers(struct device *_dev, struct device_attribute *attr, char *buf)
+{
+        struct langwell_otg *langwell;
+        char *next;
+        unsigned size;
+        unsigned t;
+
+        langwell = the_transceiver;
+        next = buf;
+        size = PAGE_SIZE;
+
+        t = scnprintf(next, size,
+                "\n"
+                "USBCMD = 0x%08x \n"
+                "USBSTS = 0x%08x \n"
+                "USBINTR = 0x%08x \n"
+                "ASYNCLISTADDR = 0x%08x \n"
+                "PORTSC1 = 0x%08x \n"
+                "HOSTPC1 = 0x%08x \n"
+                "OTGSC = 0x%08x \n"
+                "USBMODE = 0x%08x \n",
+                readl(langwell->regs + 0x30),
+                readl(langwell->regs + 0x34),
+                readl(langwell->regs + 0x38),
+                readl(langwell->regs + 0x48),
+                readl(langwell->regs + 0x74),
+                readl(langwell->regs + 0xb4),
+                readl(langwell->regs + 0xf4),
+                readl(langwell->regs + 0xf8)
+                );
+        size -= t;
+        next += t;
+
+        return PAGE_SIZE - size;
+}
+static DEVICE_ATTR(registers, S_IRUGO, show_registers, NULL);
+
+static ssize_t
+show_hsm(struct device *_dev, struct device_attribute *attr, char *buf)
+{
+        struct langwell_otg *langwell;
+        char *next;
+        unsigned size;
+        unsigned t;
+
+        langwell = the_transceiver;
+        next = buf;
+        size = PAGE_SIZE;
+
+        t = scnprintf(next, size,
+                "\n"
+                "current state = %s\n"
+                "a_bus_resume = \t%d\n"
+                "a_bus_suspend = \t%d\n"
+                "a_conn = \t%d\n"
+                "a_sess_vld = \t%d\n"
+                "a_srp_det = \t%d\n"
+                "a_vbus_vld = \t%d\n"
+                "b_bus_resume = \t%d\n"
+                "b_bus_suspend = \t%d\n"
+                "b_conn = \t%d\n"
+                "b_se0_srp = \t%d\n"
+                "b_sess_end = \t%d\n"
+                "b_sess_vld = \t%d\n"
+                "id = \t%d\n"
+                "a_set_b_hnp_en = \t%d\n"
+                "b_srp_done = \t%d\n"
+                "b_hnp_enable = \t%d\n"
+                "a_wait_vrise_tmout = \t%d\n"
+                "a_wait_bcon_tmout = \t%d\n"
+                "a_aidl_bdis_tmout = \t%d\n"
+                "b_ase0_brst_tmout = \t%d\n"
+                "a_bus_drop = \t%d\n"
+                "a_bus_req = \t%d\n"
+                "a_clr_err = \t%d\n"
+                "a_suspend_req = \t%d\n"
+                "b_bus_req = \t%d\n"
+                "b_bus_suspend_tmout = \t%d\n"
+                "b_bus_suspend_vld = \t%d\n",
+                state_string(langwell->otg.state),
+                langwell->hsm.a_bus_resume,
+                langwell->hsm.a_bus_suspend,
+                langwell->hsm.a_conn,
+                langwell->hsm.a_sess_vld,
+                langwell->hsm.a_srp_det,
+                langwell->hsm.a_vbus_vld,
+                langwell->hsm.b_bus_resume,
+                langwell->hsm.b_bus_suspend,
+                langwell->hsm.b_conn,
+                langwell->hsm.b_se0_srp,
+                langwell->hsm.b_sess_end,
+                langwell->hsm.b_sess_vld,
+                langwell->hsm.id,
+                langwell->hsm.a_set_b_hnp_en,
+                langwell->hsm.b_srp_done,
+                langwell->hsm.b_hnp_enable,
+                langwell->hsm.a_wait_vrise_tmout,
+                langwell->hsm.a_wait_bcon_tmout,
+                langwell->hsm.a_aidl_bdis_tmout,
+                langwell->hsm.b_ase0_brst_tmout,
+                langwell->hsm.a_bus_drop,
+                langwell->hsm.a_bus_req,
+                langwell->hsm.a_clr_err,
+                langwell->hsm.a_suspend_req,
+                langwell->hsm.b_bus_req,
+                langwell->hsm.b_bus_suspend_tmout,
+                langwell->hsm.b_bus_suspend_vld
+                );
+        size -= t;
+        next += t;
+
+        return PAGE_SIZE - size;
+}
+static DEVICE_ATTR(hsm, S_IRUGO, show_hsm, NULL);
+
+static ssize_t
+get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
+{
+        struct langwell_otg *langwell;
+        char *next;
+        unsigned size;
+        unsigned t;
+
+        langwell =  the_transceiver;
+        next = buf;
+        size = PAGE_SIZE;
+
+        t = scnprintf(next, size, "%d", langwell->hsm.a_bus_req);
+        size -= t;
+        next += t;
+
+        return PAGE_SIZE - size;
+}
+
+static ssize_t
+set_a_bus_req(struct device *dev, struct device_attribute *attr,
+                const char *buf, size_t count)
+{
+        struct langwell_otg *langwell;
+        langwell = the_transceiver;
+        if (!langwell->otg.default_a)
+                return -1;
+        if (count > 2)
+                return -1;
+
+        if (buf[0] == '0') {
+                langwell->hsm.a_bus_req = 0;
+                otg_dbg("a_bus_req = 0\n");
+        } else if (buf[0] == '1') {
+                /* If a_bus_drop is TRUE, a_bus_req can't be set */
+                if (langwell->hsm.a_bus_drop)
+                        return -1;
+                langwell->hsm.a_bus_req = 1;
+                otg_dbg("a_bus_req = 1\n");
+        }
+        if (spin_trylock(&langwell->wq_lock)) {
+                queue_work(langwell->qwork, &langwell->work);
+                spin_unlock(&langwell->wq_lock);
+        }
+        return count;
+}
+static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUGO, get_a_bus_req, set_a_bus_req);
+
+static ssize_t
+get_a_bus_drop(struct device *dev, struct device_attribute *attr, char *buf)
+{
+        struct langwell_otg *langwell;
+        char *next;
+        unsigned size;
+        unsigned t;
+
+        langwell =  the_transceiver;
+        next = buf;
+        size = PAGE_SIZE;
+
+        t = scnprintf(next, size, "%d", langwell->hsm.a_bus_drop);
+        size -= t;
+        next += t;
+
+        return PAGE_SIZE - size;
+}
+
+static ssize_t
+set_a_bus_drop(struct device *dev, struct device_attribute *attr,
+                const char *buf, size_t count)
+{
+        struct langwell_otg *langwell;
+        langwell = the_transceiver;
+        if (!langwell->otg.default_a)
+                return -1;
+        if (count > 2)
+                return -1;
+
+        if (buf[0] == '0') {
+                langwell->hsm.a_bus_drop = 0;
+                otg_dbg("a_bus_drop = 0\n");
+        } else if (buf[0] == '1') {
+                langwell->hsm.a_bus_drop = 1;
+                langwell->hsm.a_bus_req = 0;
+                otg_dbg("a_bus_drop = 1, then a_bus_req = 0\n");
+        }
+        if (spin_trylock(&langwell->wq_lock)) {
+                queue_work(langwell->qwork, &langwell->work);
+                spin_unlock(&langwell->wq_lock);
+        }
+        return count;
+}
+static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUGO,
+        get_a_bus_drop, set_a_bus_drop);
+
+static ssize_t
+get_b_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
+{
+        struct langwell_otg *langwell;
+        char *next;
+        unsigned size;
+        unsigned t;
+
+        langwell =  the_transceiver;
+        next = buf;
+        size = PAGE_SIZE;
+
+        t = scnprintf(next, size, "%d", langwell->hsm.b_bus_req);
+        size -= t;
+        next += t;
+
+        return PAGE_SIZE - size;
+}
+
+static ssize_t
+set_b_bus_req(struct device *dev, struct device_attribute *attr,
+                const char *buf, size_t count)
+{
+        struct langwell_otg *langwell;
+        langwell = the_transceiver;
+
+        if (langwell->otg.default_a)
+                return -1;
+
+        if (count > 2)
+                return -1;
+
+        if (buf[0] == '0') {
+                langwell->hsm.b_bus_req = 0;
+                otg_dbg("b_bus_req = 0\n");
+        } else if (buf[0] == '1') {
+                langwell->hsm.b_bus_req = 1;
+                otg_dbg("b_bus_req = 1\n");
+        }
+        if (spin_trylock(&langwell->wq_lock)) {
+                queue_work(langwell->qwork, &langwell->work);
+                spin_unlock(&langwell->wq_lock);
+        }
+        return count;
+}
+static DEVICE_ATTR(b_bus_req, S_IRUGO | S_IWUGO, get_b_bus_req, set_b_bus_req);
+
+static ssize_t
+set_a_clr_err(struct device *dev, struct device_attribute *attr,
+                const char *buf, size_t count)
+{
+        struct langwell_otg *langwell;
+        langwell = the_transceiver;
+
+        if (!langwell->otg.default_a)
+                return -1;
+        if (count > 2)
+                return -1;
+
+        if (buf[0] == '1') {
+                langwell->hsm.a_clr_err = 1;
+                otg_dbg("a_clr_err = 1\n");
+        }
+        if (spin_trylock(&langwell->wq_lock)) {
+                queue_work(langwell->qwork, &langwell->work);
+                spin_unlock(&langwell->wq_lock);
+        }
+        return count;
+}
+static DEVICE_ATTR(a_clr_err, S_IWUGO, NULL, set_a_clr_err);
+
+static struct attribute *inputs_attrs[] = {
+        &dev_attr_a_bus_req.attr,
+        &dev_attr_a_bus_drop.attr,
+        &dev_attr_b_bus_req.attr,
+        &dev_attr_a_clr_err.attr,
+        NULL,
+};
+
+static struct attribute_group debug_dev_attr_group = {
+        .name = "inputs",
+        .attrs = inputs_attrs,
+};
+
+int langwell_register_host(struct pci_driver *host_driver)
+{
+        int     ret = 0;
+
+        the_transceiver->host_ops = host_driver;
+        queue_work(the_transceiver->qwork, &the_transceiver->work);
+        otg_dbg("host controller driver is registered\n");
+
+        return ret;
+}
+EXPORT_SYMBOL(langwell_register_host);
+
+void langwell_unregister_host(struct pci_driver *host_driver)
+{
+        if (the_transceiver->host_ops)
+                the_transceiver->host_ops->remove(the_transceiver->pdev);
+        the_transceiver->host_ops = NULL;
+        the_transceiver->hsm.a_bus_drop = 1;
+        queue_work(the_transceiver->qwork, &the_transceiver->work);
+        otg_dbg("host controller driver is unregistered\n");
+}
+EXPORT_SYMBOL(langwell_unregister_host);
+
+int langwell_register_peripheral(struct pci_driver *client_driver)
+{
+        int     ret = 0;
+
+        if (client_driver)
+                ret = client_driver->probe(the_transceiver->pdev,
+                                client_driver->id_table);
+        if (!ret) {
+                the_transceiver->client_ops = client_driver;
+                queue_work(the_transceiver->qwork, &the_transceiver->work);
+                otg_dbg("client controller driver is registered\n");
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(langwell_register_peripheral);
+
+void langwell_unregister_peripheral(struct pci_driver *client_driver)
+{
+        if (the_transceiver->client_ops)
+                the_transceiver->client_ops->remove(the_transceiver->pdev);
+        the_transceiver->client_ops = NULL;
+        the_transceiver->hsm.b_bus_req = 0;
+        queue_work(the_transceiver->qwork, &the_transceiver->work);
+        otg_dbg("client controller driver is unregistered\n");
+}
+EXPORT_SYMBOL(langwell_unregister_peripheral);
+
+static int langwell_otg_probe(struct pci_dev *pdev,
+                const struct pci_device_id *id)
+{
+        unsigned long           resource, len;
+        void __iomem            *base = NULL;
+        int                     retval;
+        u32                     val32;
+        struct langwell_otg     *langwell;
+        char                    qname[] = "langwell_otg_queue";
+
+        retval = 0;
+        otg_dbg("\notg controller is detected.\n");
+        if (pci_enable_device(pdev) < 0) {
+                retval = -ENODEV;
+                goto done;
+        }
+
+        langwell = kzalloc(sizeof *langwell, GFP_KERNEL);
+        if (langwell == NULL) {
+                retval = -ENOMEM;
+                goto done;
+        }
+        the_transceiver = langwell;
+
+        /* control register: BAR 0 */
+        resource = pci_resource_start(pdev, 0);
+        len = pci_resource_len(pdev, 0);
+        if (!request_mem_region(resource, len, driver_name)) {
+                retval = -EBUSY;
+                goto err;
+        }
+        langwell->region = 1;
+
+        base = ioremap_nocache(resource, len);
+        if (base == NULL) {
+                retval = -EFAULT;
+                goto err;
+        }
+        langwell->regs = base;
+
+        if (!pdev->irq) {
+                otg_dbg("No IRQ.\n");
+                retval = -ENODEV;
+                goto err;
+        }
+
+        langwell->qwork = create_workqueue(qname);
+        if (!langwell->qwork) {
+                otg_dbg("cannot create workqueue %s\n", qname);
+                retval = -ENOMEM;
+                goto err;
+        }
+        INIT_WORK(&langwell->work, langwell_otg_work);
+
+        /* OTG common part */
+        langwell->pdev = pdev;
+        langwell->otg.dev = &pdev->dev;
+        langwell->otg.label = driver_name;
+        langwell->otg.set_host = langwell_otg_set_host;
+        langwell->otg.set_peripheral = langwell_otg_set_peripheral;
+        langwell->otg.set_power = langwell_otg_set_power;
+        langwell->otg.start_srp = langwell_otg_start_srp;
+        langwell->otg.state = OTG_STATE_UNDEFINED;
+        if (otg_set_transceiver(&langwell->otg)) {
+                otg_dbg("can't set transceiver\n");
+                retval = -EBUSY;
+                goto err;
+        }
+
+        reset_otg();
+        init_hsm();
+
+        spin_lock_init(&langwell->lock);
+        spin_lock_init(&langwell->wq_lock);
+        INIT_LIST_HEAD(&active_timers);
+        langwell_otg_init_timers(&langwell->hsm);
+
+        if (request_irq(pdev->irq, otg_irq, IRQF_SHARED,
+                                driver_name, langwell) != 0) {
+                otg_dbg("request interrupt %d failed\n", pdev->irq);
+                retval = -EBUSY;
+                goto err;
+        }
+
+        /* enable OTGSC int */
+        val32 = OTGSC_DPIE | OTGSC_BSEIE | OTGSC_BSVIE |
+                OTGSC_ASVIE | OTGSC_AVVIE | OTGSC_IDIE | OTGSC_IDPU;
+        writel(val32, langwell->regs + CI_OTGSC);
+
+        retval = device_create_file(&pdev->dev, &dev_attr_registers);
+        if (retval < 0) {
+                otg_dbg("Can't register sysfs attribute: %d\n", retval);
+                goto err;
+        }
+
+        retval = device_create_file(&pdev->dev, &dev_attr_hsm);
+        if (retval < 0) {
+                otg_dbg("Can't hsm sysfs attribute: %d\n", retval);
+                goto err;
+        }
+
+        retval = sysfs_create_group(&pdev->dev.kobj, &debug_dev_attr_group);
+        if (retval < 0) {
+                otg_dbg("Can't register sysfs attr group: %d\n", retval);
+                goto err;
+        }
+
+        if (langwell->otg.state == OTG_STATE_A_IDLE)
+                queue_work(langwell->qwork, &langwell->work);
+
+        return 0;
+
+err:
+        if (the_transceiver)
+                langwell_otg_remove(pdev);
+done:
+        return retval;
+}
+
+static void langwell_otg_remove(struct pci_dev *pdev)
+{
+        struct langwell_otg *langwell;
+
+        langwell = the_transceiver;
+
+        if (langwell->qwork) {
+                flush_workqueue(langwell->qwork);
+                destroy_workqueue(langwell->qwork);
+        }
+        langwell_otg_free_timers();
+
+        /* disable OTGSC interrupt as OTGSC doesn't change in reset */
+        writel(0, langwell->regs + CI_OTGSC);
+
+        if (pdev->irq)
+                free_irq(pdev->irq, langwell);
+        if (langwell->regs)
+                iounmap(langwell->regs);
+        if (langwell->region)
+                release_mem_region(pci_resource_start(pdev, 0),
+                                pci_resource_len(pdev, 0));
+
+        otg_set_transceiver(NULL);
+        pci_disable_device(pdev);
+        sysfs_remove_group(&pdev->dev.kobj, &debug_dev_attr_group);
+        device_remove_file(&pdev->dev, &dev_attr_hsm);
+        device_remove_file(&pdev->dev, &dev_attr_registers);
+        kfree(langwell);
+        langwell = NULL;
+}
+
+static void transceiver_suspend(struct pci_dev *pdev)
+{
+        pci_save_state(pdev);
+        pci_set_power_state(pdev, PCI_D3hot);
+        langwell_otg_phy_low_power(1);
+}
+
+static int langwell_otg_suspend(struct pci_dev *pdev, pm_message_t message)
+{
+        int     ret = 0;
+        struct langwell_otg *langwell;
+
+        langwell = the_transceiver;
+
+        /* Disbale OTG interrupts */
+        langwell_otg_intr(0);
+
+        if (pdev->irq)
+                free_irq(pdev->irq, langwell);
+
+        /* Prevent more otg_work */
+        flush_workqueue(langwell->qwork);
+        spin_lock(&langwell->wq_lock);
+
+        /* start actions */
+        switch (langwell->otg.state) {
+        case OTG_STATE_A_IDLE:
+        case OTG_STATE_B_IDLE:
+        case OTG_STATE_A_WAIT_VFALL:
+        case OTG_STATE_A_VBUS_ERR:
+                transceiver_suspend(pdev);
+                break;
+        case OTG_STATE_A_WAIT_VRISE:
+                langwell_otg_del_timer(a_wait_vrise_tmr);
+                langwell->hsm.a_srp_det = 0;
+                langwell_otg_drv_vbus(0);
+                langwell->otg.state = OTG_STATE_A_IDLE;
+                transceiver_suspend(pdev);
+                break;
+        case OTG_STATE_A_WAIT_BCON:
+                langwell_otg_del_timer(a_wait_bcon_tmr);
+                if (langwell->host_ops)
+                        ret = langwell->host_ops->suspend(pdev, message);
+                langwell_otg_drv_vbus(0);
+                break;
+        case OTG_STATE_A_HOST:
+                if (langwell->host_ops)
+                        ret = langwell->host_ops->suspend(pdev, message);
+                langwell_otg_drv_vbus(0);
+                langwell_otg_phy_low_power(1);
+                break;
+        case OTG_STATE_A_SUSPEND:
+                langwell_otg_del_timer(a_aidl_bdis_tmr);
+                langwell_otg_HABA(0);
+                if (langwell->host_ops)
+                        langwell->host_ops->remove(pdev);
+                else
+                        otg_dbg("host driver has been removed.\n");
+                langwell_otg_drv_vbus(0);
+                transceiver_suspend(pdev);
+                langwell->otg.state = OTG_STATE_A_WAIT_VFALL;
+                break;
+        case OTG_STATE_A_PERIPHERAL:
+                if (langwell->client_ops)
+                        ret = langwell->client_ops->suspend(pdev, message);
+                else
+                        otg_dbg("client driver has been removed.\n");
+                langwell_otg_drv_vbus(0);
+                transceiver_suspend(pdev);
+                langwell->otg.state = OTG_STATE_A_WAIT_VFALL;
+                break;
+        case OTG_STATE_B_HOST:
+                if (langwell->host_ops)
+                        langwell->host_ops->remove(pdev);
+                else
+                        otg_dbg("host driver has been removed.\n");
+                langwell->hsm.b_bus_req = 0;
+                transceiver_suspend(pdev);
+                langwell->otg.state = OTG_STATE_B_IDLE;
+                break;
+        case OTG_STATE_B_PERIPHERAL:
+                if (langwell->client_ops)
+                        ret = langwell->client_ops->suspend(pdev, message);
+                else
+                        otg_dbg("client driver has been removed.\n");
+                break;
+        case OTG_STATE_B_WAIT_ACON:
+                langwell_otg_del_timer(b_ase0_brst_tmr);
+                langwell_otg_HAAR(0);
+                if (langwell->host_ops)
+                        langwell->host_ops->remove(pdev);
+                else
+                        otg_dbg("host driver has been removed.\n");
+                langwell->hsm.b_bus_req = 0;
+                langwell->otg.state = OTG_STATE_B_IDLE;
+                transceiver_suspend(pdev);
+                break;
+        default:
+                otg_dbg("error state before suspend\n ");
+                break;
+        }
+        spin_unlock(&langwell->wq_lock);
+
+        return ret;
+}
+
+static void transceiver_resume(struct pci_dev *pdev)
+{
+        pci_restore_state(pdev);
+        pci_set_power_state(pdev, PCI_D0);
+        langwell_otg_phy_low_power(0);
+}
+
+static int langwell_otg_resume(struct pci_dev *pdev)
+{
+        int     ret = 0;
+        struct langwell_otg *langwell;
+
+        langwell = the_transceiver;
+
+        spin_lock(&langwell->wq_lock);
+
+        switch (langwell->otg.state) {
+        case OTG_STATE_A_IDLE:
+        case OTG_STATE_B_IDLE:
+        case OTG_STATE_A_WAIT_VFALL:
+        case OTG_STATE_A_VBUS_ERR:
+                transceiver_resume(pdev);
+                break;
+        case OTG_STATE_A_WAIT_BCON:
+                langwell_otg_add_timer(a_wait_bcon_tmr);
+                langwell_otg_drv_vbus(1);
+                if (langwell->host_ops)
+                        ret = langwell->host_ops->resume(pdev);
+                break;
+        case OTG_STATE_A_HOST:
+                langwell_otg_drv_vbus(1);
+                langwell_otg_phy_low_power(0);
+                if (langwell->host_ops)
+                        ret = langwell->host_ops->resume(pdev);
+                break;
+        case OTG_STATE_B_PERIPHERAL:
+                if (langwell->client_ops)
+                        ret = langwell->client_ops->resume(pdev);
+                else
+                        otg_dbg("client driver not loaded.\n");
+                break;
+        default:
+                otg_dbg("error state before suspend\n ");
+                break;
+        }
+
+        if (request_irq(pdev->irq, otg_irq, IRQF_SHARED,
+                                driver_name, the_transceiver) != 0) {
+                otg_dbg("request interrupt %d failed\n", pdev->irq);
+                ret = -EBUSY;
+        }
+
+        /* enable OTG interrupts */
+        langwell_otg_intr(1);
+
+        spin_unlock(&langwell->wq_lock);
+
+        queue_work(langwell->qwork, &langwell->work);
+
+
+        return ret;
+}
+
+static int __init langwell_otg_init(void)
+{
+        return pci_register_driver(&otg_pci_driver);
+}
+module_init(langwell_otg_init);
+
+static void __exit langwell_otg_cleanup(void)
+{
+        pci_unregister_driver(&otg_pci_driver);
+}
+module_exit(langwell_otg_cleanup);
diff --git a/drivers/usb/otg/nop-usb-xceiv.c b/drivers/usb/otg/nop-usb-xceiv.c
index c567168f89af..9ed5ea568679 100644
--- a/drivers/usb/otg/nop-usb-xceiv.c
+++ b/drivers/usb/otg/nop-usb-xceiv.c
@@ -22,8 +22,8 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  * Current status:
- *      this is to add "nop" transceiver for all those phy which is
- *      autonomous such as isp1504 etc.
+ *      This provides a "nop" transceiver for PHYs which are
+ *      autonomous such as isp1504, isp1707, etc.
  */
 
 #include <linux/module.h>
@@ -36,30 +36,25 @@ struct nop_usb_xceiv {
         struct device           *dev;
 };
 
-static u64 nop_xceiv_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device nop_xceiv_device = {
-        .name           = "nop_usb_xceiv",
-        .id             = -1,
-        .dev = {
-                .dma_mask               = &nop_xceiv_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data          = NULL,
-        },
-};
+static struct platform_device *pd;
 
 void usb_nop_xceiv_register(void)
 {
-        if (platform_device_register(&nop_xceiv_device) < 0) {
+        if (pd)
+                return;
+        pd = platform_device_register_simple("nop_usb_xceiv", -1, NULL, 0);
+        if (!pd) {
                 printk(KERN_ERR "Unable to register usb nop transceiver\n");
                 return;
         }
 }
+EXPORT_SYMBOL(usb_nop_xceiv_register);
 
 void usb_nop_xceiv_unregister(void)
 {
-        platform_device_unregister(&nop_xceiv_device);
+        platform_device_unregister(pd);
 }
+EXPORT_SYMBOL(usb_nop_xceiv_unregister);
 
 static inline struct nop_usb_xceiv *xceiv_to_nop(struct otg_transceiver *x)
 {
diff --git a/drivers/usb/otg/twl4030-usb.c b/drivers/usb/otg/twl4030-usb.c
index d9478d0e1c8b..9e3e7a5c258b 100644
--- a/drivers/usb/otg/twl4030-usb.c
+++ b/drivers/usb/otg/twl4030-usb.c
@@ -217,6 +217,7 @@
 
 /* In module TWL4030_MODULE_PM_MASTER */
 #define PROTECT_KEY                     0x0E
+#define STS_HW_CONDITIONS               0x0F
 
 /* In module TWL4030_MODULE_PM_RECEIVER */
 #define VUSB_DEDICATED1                 0x7D
@@ -351,15 +352,26 @@ static enum linkstat twl4030_usb_linkstat(struct twl4030_usb *twl)
         int     status;
         int     linkstat = USB_LINK_UNKNOWN;
 
-        /* STS_HW_CONDITIONS */
-        status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER, 0x0f);
+        /*
+         * For ID/VBUS sensing, see manual section 15.4.8 ...
+         * except when using only battery backup power, two
+         * comparators produce VBUS_PRES and ID_PRES signals,
+         * which don't match docs elsewhere.  But ... BIT(7)
+         * and BIT(2) of STS_HW_CONDITIONS, respectively, do
+         * seem to match up.  If either is true the USB_PRES
+         * signal is active, the OTG module is activated, and
+         * its interrupt may be raised (may wake the system).
+         */
+        status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER,
+                        STS_HW_CONDITIONS);
         if (status < 0)
                 dev_err(twl->dev, "USB link status err %d\n", status);
-        else if (status & BIT(7))
-                linkstat = USB_LINK_VBUS;
-        else if (status & BIT(2))
-                linkstat = USB_LINK_ID;
-        else
+        else if (status & (BIT(7) | BIT(2))) {
+                if (status & BIT(2))
+                        linkstat = USB_LINK_ID;
+                else
+                        linkstat = USB_LINK_VBUS;
+        } else
                 linkstat = USB_LINK_NONE;
 
         dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
@@ -641,7 +653,7 @@ static int twl4030_set_host(struct otg_transceiver *x, struct usb_bus *host)
         return 0;
 }
 
-static int __init twl4030_usb_probe(struct platform_device *pdev)
+static int __devinit twl4030_usb_probe(struct platform_device *pdev)
 {
         struct twl4030_usb_data *pdata = pdev->dev.platform_data;
         struct twl4030_usb      *twl;
diff --git a/drivers/usb/serial/aircable.c b/drivers/usb/serial/aircable.c
index 6d106e74265e..2cbfab3716e5 100644
--- a/drivers/usb/serial/aircable.c
+++ b/drivers/usb/serial/aircable.c
@@ -364,7 +364,7 @@ static int aircable_attach(struct usb_serial *serial)
         return 0;
 }
 
-static void aircable_shutdown(struct usb_serial *serial)
+static void aircable_release(struct usb_serial *serial)
 {
 
         struct usb_serial_port *port = serial->port[0];
@@ -375,7 +375,6 @@ static void aircable_shutdown(struct usb_serial *serial)
         if (priv) {
                 serial_buf_free(priv->tx_buf);
                 serial_buf_free(priv->rx_buf);
-                usb_set_serial_port_data(port, NULL);
                 kfree(priv);
         }
 }
@@ -601,7 +600,7 @@ static struct usb_serial_driver aircable_device = {
         .num_ports =            1,
         .attach =               aircable_attach,
         .probe =                aircable_probe,
-        .shutdown =             aircable_shutdown,
+        .release =              aircable_release,
         .write =                aircable_write,
         .write_room =           aircable_write_room,
         .write_bulk_callback =  aircable_write_bulk_callback,
diff --git a/drivers/usb/serial/belkin_sa.c b/drivers/usb/serial/belkin_sa.c
index 2bfd6dd85b5a..7033b031b443 100644
--- a/drivers/usb/serial/belkin_sa.c
+++ b/drivers/usb/serial/belkin_sa.c
@@ -90,7 +90,7 @@ static int debug;
 
 /* function prototypes for a Belkin USB Serial Adapter F5U103 */
 static int  belkin_sa_startup(struct usb_serial *serial);
-static void belkin_sa_shutdown(struct usb_serial *serial);
+static void belkin_sa_release(struct usb_serial *serial);
 static int  belkin_sa_open(struct tty_struct *tty,
                         struct usb_serial_port *port, struct file *filp);
 static void belkin_sa_close(struct usb_serial_port *port);
@@ -142,7 +142,7 @@ static struct usb_serial_driver belkin_device = {
         .tiocmget =             belkin_sa_tiocmget,
         .tiocmset =             belkin_sa_tiocmset,
         .attach =               belkin_sa_startup,
-        .shutdown =             belkin_sa_shutdown,
+        .release =              belkin_sa_release,
 };
 
 
@@ -197,14 +197,13 @@ static int belkin_sa_startup(struct usb_serial *serial)
 }
 
 
-static void belkin_sa_shutdown(struct usb_serial *serial)
+static void belkin_sa_release(struct usb_serial *serial)
 {
         struct belkin_sa_private *priv;
         int i;
 
         dbg("%s", __func__);
 
-        /* stop reads and writes on all ports */
         for (i = 0; i < serial->num_ports; ++i) {
                 /* My special items, the standard routines free my urbs */
                 priv = usb_get_serial_port_data(serial->port[i]);
diff --git a/drivers/usb/serial/bus.c b/drivers/usb/serial/bus.c
index 83bbb5bca2ef..ba555c528cc6 100644
--- a/drivers/usb/serial/bus.c
+++ b/drivers/usb/serial/bus.c
@@ -59,23 +59,22 @@ static int usb_serial_device_probe(struct device *dev)
                 retval = -ENODEV;
                 goto exit;
         }
+        if (port->dev_state != PORT_REGISTERING)
+                goto exit;
 
         driver = port->serial->type;
         if (driver->port_probe) {
-                if (!try_module_get(driver->driver.owner)) {
-                        dev_err(dev, "module get failed, exiting\n");
-                        retval = -EIO;
-                        goto exit;
-                }
                 retval = driver->port_probe(port);
-                module_put(driver->driver.owner);
                 if (retval)
                         goto exit;
         }
 
         retval = device_create_file(dev, &dev_attr_port_number);
-        if (retval)
+        if (retval) {
+                if (driver->port_remove)
+                        retval = driver->port_remove(port);
                 goto exit;
+        }
 
         minor = port->number;
         tty_register_device(usb_serial_tty_driver, minor, dev);
@@ -98,19 +97,15 @@ static int usb_serial_device_remove(struct device *dev)
         if (!port)
                 return -ENODEV;
 
+        if (port->dev_state != PORT_UNREGISTERING)
+                return retval;
+
         device_remove_file(&port->dev, &dev_attr_port_number);
 
         driver = port->serial->type;
-        if (driver->port_remove) {
-                if (!try_module_get(driver->driver.owner)) {
-                        dev_err(dev, "module get failed, exiting\n");
-                        retval = -EIO;
-                        goto exit;
-                }
+        if (driver->port_remove)
                 retval = driver->port_remove(port);
-                module_put(driver->driver.owner);
-        }
-exit:
+
         minor = port->number;
         tty_unregister_device(usb_serial_tty_driver, minor);
         dev_info(dev, "%s converter now disconnected from ttyUSB%d\n",
diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c
index 16a154d3b2fe..2b9eeda62bfe 100644
--- a/drivers/usb/serial/cp210x.c
+++ b/drivers/usb/serial/cp210x.c
@@ -50,7 +50,7 @@ static int cp210x_tiocmset_port(struct usb_serial_port *port, struct file *,
                 unsigned int, unsigned int);
 static void cp210x_break_ctl(struct tty_struct *, int);
 static int cp210x_startup(struct usb_serial *);
-static void cp210x_shutdown(struct usb_serial *);
+static void cp210x_disconnect(struct usb_serial *);
 
 static int debug;
 
@@ -137,7 +137,7 @@ static struct usb_serial_driver cp210x_device = {
         .tiocmget               = cp210x_tiocmget,
         .tiocmset               = cp210x_tiocmset,
         .attach                 = cp210x_startup,
-        .shutdown               = cp210x_shutdown,
+        .disconnect             = cp210x_disconnect,
 };
 
 /* Config request types */
@@ -792,7 +792,7 @@ static int cp210x_startup(struct usb_serial *serial)
         return 0;
 }
 
-static void cp210x_shutdown(struct usb_serial *serial)
+static void cp210x_disconnect(struct usb_serial *serial)
 {
         int i;
 
diff --git a/drivers/usb/serial/cyberjack.c b/drivers/usb/serial/cyberjack.c
index 933ba913e66c..336523fd7366 100644
--- a/drivers/usb/serial/cyberjack.c
+++ b/drivers/usb/serial/cyberjack.c
@@ -58,7 +58,8 @@ static int debug;
 
 /* Function prototypes */
 static int cyberjack_startup(struct usb_serial *serial);
-static void cyberjack_shutdown(struct usb_serial *serial);
+static void cyberjack_disconnect(struct usb_serial *serial);
+static void cyberjack_release(struct usb_serial *serial);
 static int  cyberjack_open(struct tty_struct *tty,
                         struct usb_serial_port *port, struct file *filp);
 static void cyberjack_close(struct usb_serial_port *port);
@@ -94,7 +95,8 @@ static struct usb_serial_driver cyberjack_device = {
         .id_table =             id_table,
         .num_ports =            1,
         .attach =               cyberjack_startup,
-        .shutdown =             cyberjack_shutdown,
+        .disconnect =           cyberjack_disconnect,
+        .release =              cyberjack_release,
         .open =                 cyberjack_open,
         .close =                cyberjack_close,
         .write =                cyberjack_write,
@@ -148,17 +150,25 @@ static int cyberjack_startup(struct usb_serial *serial)
         return 0;
 }
 
-static void cyberjack_shutdown(struct usb_serial *serial)
+static void cyberjack_disconnect(struct usb_serial *serial)
 {
         int i;
 
         dbg("%s", __func__);
 
-        for (i = 0; i < serial->num_ports; ++i) {
+        for (i = 0; i < serial->num_ports; ++i)
                 usb_kill_urb(serial->port[i]->interrupt_in_urb);
+}
+
+static void cyberjack_release(struct usb_serial *serial)
+{
+        int i;
+
+        dbg("%s", __func__);
+
+        for (i = 0; i < serial->num_ports; ++i) {
                 /* My special items, the standard routines free my urbs */
                 kfree(usb_get_serial_port_data(serial->port[i]));
-                usb_set_serial_port_data(serial->port[i], NULL);
         }
 }
 
diff --git a/drivers/usb/serial/cypress_m8.c b/drivers/usb/serial/cypress_m8.c
index 669f93848539..9734085fd2fe 100644
--- a/drivers/usb/serial/cypress_m8.c
+++ b/drivers/usb/serial/cypress_m8.c
@@ -171,7 +171,7 @@ struct cypress_buf {
 static int  cypress_earthmate_startup(struct usb_serial *serial);
 static int  cypress_hidcom_startup(struct usb_serial *serial);
 static int  cypress_ca42v2_startup(struct usb_serial *serial);
-static void cypress_shutdown(struct usb_serial *serial);
+static void cypress_release(struct usb_serial *serial);
 static int  cypress_open(struct tty_struct *tty,
                         struct usb_serial_port *port, struct file *filp);
 static void cypress_close(struct usb_serial_port *port);
@@ -215,7 +215,7 @@ static struct usb_serial_driver cypress_earthmate_device = {
         .id_table =                     id_table_earthmate,
         .num_ports =                    1,
         .attach =                       cypress_earthmate_startup,
-        .shutdown =                     cypress_shutdown,
+        .release =                      cypress_release,
         .open =                         cypress_open,
         .close =                        cypress_close,
         .dtr_rts =                      cypress_dtr_rts,
@@ -242,7 +242,7 @@ static struct usb_serial_driver cypress_hidcom_device = {
         .id_table =                     id_table_cyphidcomrs232,
         .num_ports =                    1,
         .attach =                       cypress_hidcom_startup,
-        .shutdown =                     cypress_shutdown,
+        .release =                      cypress_release,
         .open =                         cypress_open,
         .close =                        cypress_close,
         .dtr_rts =                      cypress_dtr_rts,
@@ -269,7 +269,7 @@ static struct usb_serial_driver cypress_ca42v2_device = {
         .id_table =                     id_table_nokiaca42v2,
         .num_ports =                    1,
         .attach =                       cypress_ca42v2_startup,
-        .shutdown =                     cypress_shutdown,
+        .release =                      cypress_release,
         .open =                         cypress_open,
         .close =                        cypress_close,
         .dtr_rts =                      cypress_dtr_rts,
@@ -616,7 +616,7 @@ static int cypress_ca42v2_startup(struct usb_serial *serial)
 } /* cypress_ca42v2_startup */
 
 
-static void cypress_shutdown(struct usb_serial *serial)
+static void cypress_release(struct usb_serial *serial)
 {
         struct cypress_private *priv;
 
@@ -629,7 +629,6 @@ static void cypress_shutdown(struct usb_serial *serial)
         if (priv) {
                 cypress_buf_free(priv->buf);
                 kfree(priv);
-                usb_set_serial_port_data(serial->port[0], NULL);
         }
 }
 
diff --git a/drivers/usb/serial/digi_acceleport.c b/drivers/usb/serial/digi_acceleport.c
index 30f5140eff03..f4808091c47c 100644
--- a/drivers/usb/serial/digi_acceleport.c
+++ b/drivers/usb/serial/digi_acceleport.c
@@ -460,7 +460,8 @@ static int digi_carrier_raised(struct usb_serial_port *port);
 static void digi_dtr_rts(struct usb_serial_port *port, int on);
 static int digi_startup_device(struct usb_serial *serial);
 static int digi_startup(struct usb_serial *serial);
-static void digi_shutdown(struct usb_serial *serial);
+static void digi_disconnect(struct usb_serial *serial);
+static void digi_release(struct usb_serial *serial);
 static void digi_read_bulk_callback(struct urb *urb);
 static int digi_read_inb_callback(struct urb *urb);
 static int digi_read_oob_callback(struct urb *urb);
@@ -524,7 +525,8 @@ static struct usb_serial_driver digi_acceleport_2_device = {
         .tiocmget =                     digi_tiocmget,
         .tiocmset =                     digi_tiocmset,
         .attach =                       digi_startup,
-        .shutdown =                     digi_shutdown,
+        .disconnect =                   digi_disconnect,
+        .release =                      digi_release,
 };
 
 static struct usb_serial_driver digi_acceleport_4_device = {
@@ -550,7 +552,8 @@ static struct usb_serial_driver digi_acceleport_4_device = {
         .tiocmget =                     digi_tiocmget,
         .tiocmset =                     digi_tiocmset,
         .attach =                       digi_startup,
-        .shutdown =                     digi_shutdown,
+        .disconnect =                   digi_disconnect,
+        .release =                      digi_release,
 };
 
 
@@ -1556,16 +1559,23 @@ static int digi_startup(struct usb_serial *serial)
 }
 
 
-static void digi_shutdown(struct usb_serial *serial)
+static void digi_disconnect(struct usb_serial *serial)
 {
         int i;
-        dbg("digi_shutdown: TOP, in_interrupt()=%ld", in_interrupt());
+        dbg("digi_disconnect: TOP, in_interrupt()=%ld", in_interrupt());
 
         /* stop reads and writes on all ports */
         for (i = 0; i < serial->type->num_ports + 1; i++) {
                 usb_kill_urb(serial->port[i]->read_urb);
                 usb_kill_urb(serial->port[i]->write_urb);
         }
+}
+
+
+static void digi_release(struct usb_serial *serial)
+{
+        int i;
+        dbg("digi_release: TOP, in_interrupt()=%ld", in_interrupt());
 
         /* free the private data structures for all ports */
         /* number of regular ports + 1 for the out-of-band port */
diff --git a/drivers/usb/serial/empeg.c b/drivers/usb/serial/empeg.c
index 2b141ccb0cd9..80cb3471adbe 100644
--- a/drivers/usb/serial/empeg.c
+++ b/drivers/usb/serial/empeg.c
@@ -90,7 +90,6 @@ static int  empeg_chars_in_buffer(struct tty_struct *tty);
 static void empeg_throttle(struct tty_struct *tty);
 static void empeg_unthrottle(struct tty_struct *tty);
 static int  empeg_startup(struct usb_serial *serial);
-static void empeg_shutdown(struct usb_serial *serial);
 static void empeg_set_termios(struct tty_struct *tty,
                 struct usb_serial_port *port, struct ktermios *old_termios);
 static void empeg_write_bulk_callback(struct urb *urb);
@@ -124,7 +123,6 @@ static struct usb_serial_driver empeg_device = {
         .throttle =             empeg_throttle,
         .unthrottle =           empeg_unthrottle,
         .attach =               empeg_startup,
-        .shutdown =             empeg_shutdown,
         .set_termios =          empeg_set_termios,
         .write =                empeg_write,
         .write_room =           empeg_write_room,
@@ -427,12 +425,6 @@ static int  empeg_startup(struct usb_serial *serial)
 }
 
 
-static void empeg_shutdown(struct usb_serial *serial)
-{
-        dbg("%s", __func__);
-}
-
-
 static void empeg_set_termios(struct tty_struct *tty,
                 struct usb_serial_port *port, struct ktermios *old_termios)
 {
diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c
index 683304d60615..3dc3768ca71c 100644
--- a/drivers/usb/serial/ftdi_sio.c
+++ b/drivers/usb/serial/ftdi_sio.c
@@ -47,7 +47,7 @@
 /*
  * Version Information
  */
-#define DRIVER_VERSION "v1.4.3"
+#define DRIVER_VERSION "v1.5.0"
 #define DRIVER_AUTHOR "Greg Kroah-Hartman <greg@kroah.com>, Bill Ryder <bryder@sgi.com>, Kuba Ober <kuba@mareimbrium.org>"
 #define DRIVER_DESC "USB FTDI Serial Converters Driver"
 
@@ -82,7 +82,8 @@ struct ftdi_private {
         int rx_processed;
         unsigned long rx_bytes;
 
-        __u16 interface;        /* FT2232C port interface (0 for FT232/245) */
+        __u16 interface;        /* FT2232C, FT2232H or FT4232H port interface
+                                   (0 for FT232/245) */
 
         speed_t force_baud;     /* if non-zero, force the baud rate to
                                    this value */
@@ -94,6 +95,7 @@ struct ftdi_private {
         unsigned long tx_bytes;
         unsigned long tx_outstanding_bytes;
         unsigned long tx_outstanding_urbs;
+        unsigned short max_packet_size;
 };
 
 /* struct ftdi_sio_quirk is used by devices requiring special attention. */
@@ -164,6 +166,7 @@ static struct usb_device_id id_table_combined [] = {
         { USB_DEVICE(FTDI_VID, FTDI_8U232AM_ALT_PID) },
         { USB_DEVICE(FTDI_VID, FTDI_232RL_PID) },
         { USB_DEVICE(FTDI_VID, FTDI_8U2232C_PID) },
+        { USB_DEVICE(FTDI_VID, FTDI_4232H_PID) },
         { USB_DEVICE(FTDI_VID, FTDI_MICRO_CHAMELEON_PID) },
         { USB_DEVICE(FTDI_VID, FTDI_RELAIS_PID) },
         { USB_DEVICE(FTDI_VID, FTDI_OPENDCC_PID) },
@@ -673,6 +676,7 @@ static struct usb_device_id id_table_combined [] = {
         { USB_DEVICE(JETI_VID, JETI_SPC1201_PID) },
         { USB_DEVICE(MARVELL_VID, MARVELL_SHEEVAPLUG_PID),
                 .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
+        { USB_DEVICE(LARSENBRUSGAARD_VID, LB_ALTITRACK_PID) },
         { },                                    /* Optional parameter entry */
         { }                                     /* Terminating entry */
 };
@@ -693,12 +697,13 @@ static const char *ftdi_chip_name[] = {
         [FT232BM] = "FT232BM",
         [FT2232C] = "FT2232C",
         [FT232RL] = "FT232RL",
+        [FT2232H] = "FT2232H",
+        [FT4232H] = "FT4232H"
 };
 
 
 /* Constants for read urb and write urb */
 #define BUFSZ 512
-#define PKTSZ 64
 
 /* rx_flags */
 #define THROTTLED               0x01
@@ -715,7 +720,6 @@ static const char *ftdi_chip_name[] = {
 /* function prototypes for a FTDI serial converter */
 static int  ftdi_sio_probe(struct usb_serial *serial,
                                         const struct usb_device_id *id);
-static void ftdi_shutdown(struct usb_serial *serial);
 static int  ftdi_sio_port_probe(struct usb_serial_port *port);
 static int  ftdi_sio_port_remove(struct usb_serial_port *port);
 static int  ftdi_open(struct tty_struct *tty,
@@ -744,6 +748,8 @@ static unsigned short int ftdi_232am_baud_base_to_divisor(int baud, int base);
 static unsigned short int ftdi_232am_baud_to_divisor(int baud);
 static __u32 ftdi_232bm_baud_base_to_divisor(int baud, int base);
 static __u32 ftdi_232bm_baud_to_divisor(int baud);
+static __u32 ftdi_2232h_baud_base_to_divisor(int baud, int base);
+static __u32 ftdi_2232h_baud_to_divisor(int baud);
 
 static struct usb_serial_driver ftdi_sio_device = {
         .driver = {
@@ -772,7 +778,6 @@ static struct usb_serial_driver ftdi_sio_device = {
         .ioctl =                ftdi_ioctl,
         .set_termios =          ftdi_set_termios,
         .break_ctl =            ftdi_break_ctl,
-        .shutdown =             ftdi_shutdown,
 };
 
 
@@ -838,6 +843,36 @@ static __u32 ftdi_232bm_baud_to_divisor(int baud)
          return ftdi_232bm_baud_base_to_divisor(baud, 48000000);
 }
 
+static __u32 ftdi_2232h_baud_base_to_divisor(int baud, int base)
+{
+        static const unsigned char divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 };
+        __u32 divisor;
+        int divisor3;
+
+        /* hi-speed baud rate is 10-bit sampling instead of 16-bit */
+        divisor3 = (base / 10 / baud) * 8;
+
+        divisor = divisor3 >> 3;
+        divisor |= (__u32)divfrac[divisor3 & 0x7] << 14;
+        /* Deal with special cases for highest baud rates. */
+        if (divisor == 1)
+                divisor = 0;
+        else if (divisor == 0x4001)
+                divisor = 1;
+        /*
+         * Set this bit to turn off a divide by 2.5 on baud rate generator
+         * This enables baud rates up to 12Mbaud but cannot reach below 1200
+         * baud with this bit set
+         */
+        divisor |= 0x00020000;
+        return divisor;
+}
+
+static __u32 ftdi_2232h_baud_to_divisor(int baud)
+{
+         return ftdi_2232h_baud_base_to_divisor(baud, 120000000);
+}
+
 #define set_mctrl(port, set)            update_mctrl((port), (set), 0)
 #define clear_mctrl(port, clear)        update_mctrl((port), 0, (clear))
 
@@ -996,6 +1031,19 @@ static __u32 get_ftdi_divisor(struct tty_struct *tty,
                         baud = 9600;
                 }
                 break;
+        case FT2232H: /* FT2232H chip */
+        case FT4232H: /* FT4232H chip */
+                if ((baud <= 12000000) & (baud >= 1200)) {
+                        div_value = ftdi_2232h_baud_to_divisor(baud);
+                } else if (baud < 1200) {
+                        div_value = ftdi_232bm_baud_to_divisor(baud);
+                } else {
+                        dbg("%s - Baud rate too high!", __func__);
+                        div_value = ftdi_232bm_baud_to_divisor(9600);
+                        div_okay = 0;
+                        baud = 9600;
+                }
+                break;
         } /* priv->chip_type */
 
         if (div_okay) {
@@ -1196,14 +1244,29 @@ static void ftdi_determine_type(struct usb_serial_port *port)
         if (interfaces > 1) {
                 int inter;
 
-                /* Multiple interfaces.  Assume FT2232C. */
-                priv->chip_type = FT2232C;
+                /* Multiple interfaces.*/
+                if (version == 0x0800) {
+                        priv->chip_type = FT4232H;
+                        /* Hi-speed - baud clock runs at 120MHz */
+                        priv->baud_base = 120000000 / 2;
+                } else if (version == 0x0700) {
+                        priv->chip_type = FT2232H;
+                        /* Hi-speed - baud clock runs at 120MHz */
+                        priv->baud_base = 120000000 / 2;
+                } else
+                        priv->chip_type = FT2232C;
+
                 /* Determine interface code. */
                 inter = serial->interface->altsetting->desc.bInterfaceNumber;
-                if (inter == 0)
-                        priv->interface = PIT_SIOA;
-                else
-                        priv->interface = PIT_SIOB;
+                if (inter == 0) {
+                        priv->interface = INTERFACE_A;
+                } else  if (inter == 1) {
+                        priv->interface = INTERFACE_B;
+                } else  if (inter == 2) {
+                        priv->interface = INTERFACE_C;
+                } else  if (inter == 3) {
+                        priv->interface = INTERFACE_D;
+                }
                 /* BM-type devices have a bug where bcdDevice gets set
                  * to 0x200 when iSerialNumber is 0.  */
                 if (version < 0x500) {
@@ -1231,6 +1294,45 @@ static void ftdi_determine_type(struct usb_serial_port *port)
 }
 
 
+/* Determine the maximum packet size for the device.  This depends on the chip
+ * type and the USB host capabilities.  The value should be obtained from the
+ * device descriptor as the chip will use the appropriate values for the host.*/
+static void ftdi_set_max_packet_size(struct usb_serial_port *port)
+{
+        struct ftdi_private *priv = usb_get_serial_port_data(port);
+        struct usb_serial *serial = port->serial;
+        struct usb_device *udev = serial->dev;
+
+        struct usb_interface *interface = serial->interface;
+        struct usb_endpoint_descriptor *ep_desc = &interface->cur_altsetting->endpoint[1].desc;
+
+        unsigned num_endpoints;
+        int i = 0;
+
+        num_endpoints = interface->cur_altsetting->desc.bNumEndpoints;
+        dev_info(&udev->dev, "Number of endpoints %d\n", num_endpoints);
+
+        /* NOTE: some customers have programmed FT232R/FT245R devices
+         * with an endpoint size of 0 - not good.  In this case, we
+         * want to override the endpoint descriptor setting and use a
+         * value of 64 for wMaxPacketSize */
+        for (i = 0; i < num_endpoints; i++) {
+                dev_info(&udev->dev, "Endpoint %d MaxPacketSize %d\n", i+1,
+                        interface->cur_altsetting->endpoint[i].desc.wMaxPacketSize);
+                ep_desc = &interface->cur_altsetting->endpoint[i].desc;
+                if (ep_desc->wMaxPacketSize == 0) {
+                        ep_desc->wMaxPacketSize = cpu_to_le16(0x40);
+                        dev_info(&udev->dev, "Overriding wMaxPacketSize on endpoint %d\n", i);
+                }
+        }
+
+        /* set max packet size based on descriptor */
+        priv->max_packet_size = ep_desc->wMaxPacketSize;
+
+        dev_info(&udev->dev, "Setting MaxPacketSize %d\n", priv->max_packet_size);
+}
+
+
 /*
  * ***************************************************************************
  * Sysfs Attribute
@@ -1314,7 +1416,9 @@ static int create_sysfs_attrs(struct usb_serial_port *port)
                 if ((!retval) &&
                     (priv->chip_type == FT232BM ||
                      priv->chip_type == FT2232C ||
-                     priv->chip_type == FT232RL)) {
+                     priv->chip_type == FT232RL ||
+                     priv->chip_type == FT2232H ||
+                     priv->chip_type == FT4232H)) {
                         retval = device_create_file(&port->dev,
                                                     &dev_attr_latency_timer);
                 }
@@ -1333,7 +1437,9 @@ static void remove_sysfs_attrs(struct usb_serial_port *port)
                 device_remove_file(&port->dev, &dev_attr_event_char);
                 if (priv->chip_type == FT232BM ||
                     priv->chip_type == FT2232C ||
-                    priv->chip_type == FT232RL) {
+                    priv->chip_type == FT232RL ||
+                    priv->chip_type == FT2232H ||
+                    priv->chip_type == FT4232H) {
                         device_remove_file(&port->dev, &dev_attr_latency_timer);
                 }
         }
@@ -1416,6 +1522,7 @@ static int ftdi_sio_port_probe(struct usb_serial_port *port)
         usb_set_serial_port_data(port, priv);
 
         ftdi_determine_type(port);
+        ftdi_set_max_packet_size(port);
         read_latency_timer(port);
         create_sysfs_attrs(port);
         return 0;
@@ -1485,18 +1592,6 @@ static int ftdi_mtxorb_hack_setup(struct usb_serial *serial)
         return 0;
 }
 
-/* ftdi_shutdown is called from usbserial:usb_serial_disconnect
- *   it is called when the usb device is disconnected
- *
- *   usbserial:usb_serial_disconnect
- *      calls __serial_close for each open of the port
- *      shutdown is called then (ie ftdi_shutdown)
- */
-static void ftdi_shutdown(struct usb_serial *serial)
-{
-        dbg("%s", __func__);
-}
-
 static void ftdi_sio_priv_release(struct kref *k)
 {
         struct ftdi_private *priv = container_of(k, struct ftdi_private, kref);
@@ -1671,8 +1766,8 @@ static int ftdi_write(struct tty_struct *tty, struct usb_serial_port *port,
         if (data_offset > 0) {
                 /* Original sio needs control bytes too... */
                 transfer_size += (data_offset *
-                                ((count + (PKTSZ - 1 - data_offset)) /
-                                 (PKTSZ - data_offset)));
+                                ((count + (priv->max_packet_size - 1 - data_offset)) /
+                                 (priv->max_packet_size - data_offset)));
         }
 
         buffer = kmalloc(transfer_size, GFP_ATOMIC);
@@ -1694,7 +1789,7 @@ static int ftdi_write(struct tty_struct *tty, struct usb_serial_port *port,
         if (data_offset > 0) {
                 /* Original sio requires control byte at start of
                    each packet. */
-                int user_pktsz = PKTSZ - data_offset;
+                int user_pktsz = priv->max_packet_size - data_offset;
                 int todo = count;
                 unsigned char *first_byte = buffer;
                 const unsigned char *current_position = buf;
@@ -1775,11 +1870,6 @@ static void ftdi_write_bulk_callback(struct urb *urb)
 
         dbg("%s - port %d", __func__, port->number);
 
-        if (status) {
-                dbg("nonzero write bulk status received: %d", status);
-                return;
-        }
-
         priv = usb_get_serial_port_data(port);
         if (!priv) {
                 dbg("%s - bad port private data pointer - exiting", __func__);
@@ -1790,13 +1880,18 @@ static void ftdi_write_bulk_callback(struct urb *urb)
         data_offset = priv->write_offset;
         if (data_offset > 0) {
                 /* Subtract the control bytes */
-                countback -= (data_offset * DIV_ROUND_UP(countback, PKTSZ));
+                countback -= (data_offset * DIV_ROUND_UP(countback, priv->max_packet_size));
         }
         spin_lock_irqsave(&priv->tx_lock, flags);
         --priv->tx_outstanding_urbs;
         priv->tx_outstanding_bytes -= countback;
         spin_unlock_irqrestore(&priv->tx_lock, flags);
 
+        if (status) {
+                dbg("nonzero write bulk status received: %d", status);
+                return;
+        }
+
         usb_serial_port_softint(port);
 } /* ftdi_write_bulk_callback */
 
@@ -1892,7 +1987,7 @@ static void ftdi_read_bulk_callback(struct urb *urb)
 
         /* count data bytes, but not status bytes */
         countread = urb->actual_length;
-        countread -= 2 * DIV_ROUND_UP(countread, PKTSZ);
+        countread -= 2 * DIV_ROUND_UP(countread, priv->max_packet_size);
         spin_lock_irqsave(&priv->rx_lock, flags);
         priv->rx_bytes += countread;
         spin_unlock_irqrestore(&priv->rx_lock, flags);
@@ -1965,7 +2060,7 @@ static void ftdi_process_read(struct work_struct *work)
 
         need_flip = 0;
         for (packet_offset = priv->rx_processed;
-                packet_offset < urb->actual_length; packet_offset += PKTSZ) {
+                packet_offset < urb->actual_length; packet_offset += priv->max_packet_size) {
                 int length;
 
                 /* Compare new line status to the old one, signal if different/
@@ -1980,7 +2075,7 @@ static void ftdi_process_read(struct work_struct *work)
                         priv->prev_status = new_status;
                 }
 
-                length = min_t(u32, PKTSZ, urb->actual_length-packet_offset)-2;
+                length = min_t(u32, priv->max_packet_size, urb->actual_length-packet_offset)-2;
                 if (length < 0) {
                         dev_err(&port->dev, "%s - bad packet length: %d\n",
                                 __func__, length+2);
@@ -2011,6 +2106,7 @@ static void ftdi_process_read(struct work_struct *work)
                 if (data[packet_offset+1] & FTDI_RS_BI) {
                         error_flag = TTY_BREAK;
                         dbg("BREAK received");
+                        usb_serial_handle_break(port);
                 }
                 if (data[packet_offset+1] & FTDI_RS_PE) {
                         error_flag = TTY_PARITY;
@@ -2025,8 +2121,11 @@ static void ftdi_process_read(struct work_struct *work)
                                 /* Note that the error flag is duplicated for
                                    every character received since we don't know
                                    which character it applied to */
-                                tty_insert_flip_char(tty,
-                                        data[packet_offset + i], error_flag);
+                                if (!usb_serial_handle_sysrq_char(port,
+                                                data[packet_offset + i]))
+                                        tty_insert_flip_char(tty,
+                                                data[packet_offset + i],
+                                                error_flag);
                         }
                         need_flip = 1;
                 }
@@ -2332,6 +2431,8 @@ static int ftdi_tiocmget(struct tty_struct *tty, struct file *file)
         case FT232BM:
         case FT2232C:
         case FT232RL:
+        case FT2232H:
+        case FT4232H:
                 /* the 8U232AM returns a two byte value (the sio is a 1 byte
                    value) - in the same format as the data returned from the in
                    point */
diff --git a/drivers/usb/serial/ftdi_sio.h b/drivers/usb/serial/ftdi_sio.h
index 12330fa1c095..f1d440a728a3 100644
--- a/drivers/usb/serial/ftdi_sio.h
+++ b/drivers/usb/serial/ftdi_sio.h
@@ -10,7 +10,7 @@
  * The device is based on the FTDI FT8U100AX chip. It has a DB25 on one side,
  * USB on the other.
  *
- * Thanx to FTDI (http://www.ftdi.co.uk) for so kindly providing details
+ * Thanx to FTDI (http://www.ftdichip.com) for so kindly providing details
  * of the protocol required to talk to the device and ongoing assistence
  * during development.
  *
@@ -28,11 +28,15 @@
 #define FTDI_8U232AM_ALT_PID 0x6006 /* FTDI's alternate PID for above */
 #define FTDI_8U2232C_PID 0x6010 /* Dual channel device */
 #define FTDI_232RL_PID  0xFBFA  /* Product ID for FT232RL */
+#define FTDI_4232H_PID 0x6011 /* Quad channel hi-speed device */
 #define FTDI_RELAIS_PID 0xFA10  /* Relais device from Rudolf Gugler */
 #define FTDI_NF_RIC_VID 0x0DCD  /* Vendor Id */
 #define FTDI_NF_RIC_PID 0x0001  /* Product Id */
 #define FTDI_USBX_707_PID 0xF857        /* ADSTech IR Blaster USBX-707 */
 
+/* Larsen and Brusgaard AltiTrack/USBtrack  */
+#define LARSENBRUSGAARD_VID             0x0FD8
+#define LB_ALTITRACK_PID                0x0001
 
 /* www.canusb.com Lawicel CANUSB device */
 #define FTDI_CANUSB_PID 0xFFA8 /* Product Id */
@@ -873,6 +877,11 @@
 #define FTDI_SIO_SET_LATENCY_TIMER      9 /* Set the latency timer */
 #define FTDI_SIO_GET_LATENCY_TIMER      10 /* Get the latency timer */
 
+/* Interface indicies for FT2232, FT2232H and FT4232H devices*/
+#define INTERFACE_A             1
+#define INTERFACE_B             2
+#define INTERFACE_C             3
+#define INTERFACE_D             4
 
 /*
  * FIC / OpenMoko, Inc. http://wiki.openmoko.org/wiki/Neo1973_Debug_Board_v3
@@ -1036,6 +1045,8 @@ typedef enum {
         FT232BM = 3,
         FT2232C = 4,
         FT232RL = 5,
+        FT2232H = 6,
+        FT4232H = 7
 } ftdi_chip_type_t;
 
 typedef enum {
diff --git a/drivers/usb/serial/garmin_gps.c b/drivers/usb/serial/garmin_gps.c
index ee25a3fe3b09..8839f1c70b7f 100644
--- a/drivers/usb/serial/garmin_gps.c
+++ b/drivers/usb/serial/garmin_gps.c
@@ -1,7 +1,7 @@
 /*
  * Garmin GPS driver
  *
- * Copyright (C) 2006,2007 Hermann Kneissel herkne@users.sourceforge.net
+ * Copyright (C) 2006-2009 Hermann Kneissel herkne@users.sourceforge.net
  *
  * The latest version of the driver can be found at
  * http://sourceforge.net/projects/garmin-gps/
@@ -51,7 +51,7 @@ static int debug;
  */
 
 #define VERSION_MAJOR   0
-#define VERSION_MINOR   31
+#define VERSION_MINOR   33
 
 #define _STR(s) #s
 #define _DRIVER_VERSION(a, b) "v" _STR(a) "." _STR(b)
@@ -129,7 +129,6 @@ struct garmin_data {
         __u8   state;
         __u16  flags;
         __u8   mode;
-        __u8   ignorePkts;
         __u8   count;
         __u8   pkt_id;
         __u32  serial_num;
@@ -141,8 +140,6 @@ struct garmin_data {
         __u8   inbuffer [GPS_IN_BUFSIZ];  /* tty -> usb */
         __u8   outbuffer[GPS_OUT_BUFSIZ]; /* usb -> tty */
         __u8   privpkt[4*6];
-        atomic_t req_count;
-        atomic_t resp_count;
         spinlock_t lock;
         struct list_head pktlist;
 };
@@ -170,6 +167,8 @@ struct garmin_data {
 #define FLAGS_BULK_IN_ACTIVE      0x0020
 #define FLAGS_BULK_IN_RESTART     0x0010
 #define FLAGS_THROTTLED           0x0008
+#define APP_REQ_SEEN              0x0004
+#define APP_RESP_SEEN             0x0002
 #define CLEAR_HALT_REQUIRED       0x0001
 
 #define FLAGS_QUEUING             0x0100
@@ -184,20 +183,16 @@ struct garmin_data {
 
 
 /* function prototypes */
-static void gsp_next_packet(struct garmin_data *garmin_data_p);
-static int  garmin_write_bulk(struct usb_serial_port *port,
+static int gsp_next_packet(struct garmin_data *garmin_data_p);
+static int garmin_write_bulk(struct usb_serial_port *port,
                              const unsigned char *buf, int count,
                              int dismiss_ack);
 
 /* some special packets to be send or received */
 static unsigned char const GARMIN_START_SESSION_REQ[]
         = { 0, 0, 0, 0,  5, 0, 0, 0, 0, 0, 0, 0 };
-static unsigned char const GARMIN_START_SESSION_REQ2[]
-        = { 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0 };
 static unsigned char const GARMIN_START_SESSION_REPLY[]
         = { 0, 0, 0, 0,  6, 0, 0, 0, 4, 0, 0, 0 };
-static unsigned char const GARMIN_SESSION_ACTIVE_REPLY[]
-        = { 0, 0, 0, 0, 17, 0, 0, 0, 4, 0, 0, 0, 0, 16, 0, 0 };
 static unsigned char const GARMIN_BULK_IN_AVAIL_REPLY[]
         = { 0, 0, 0, 0,  2, 0, 0, 0, 0, 0, 0, 0 };
 static unsigned char const GARMIN_APP_LAYER_REPLY[]
@@ -233,13 +228,6 @@ static struct usb_driver garmin_driver = {
 };
 
 
-static inline int noResponseFromAppLayer(struct garmin_data *garmin_data_p)
-{
-        return atomic_read(&garmin_data_p->req_count) ==
-                                atomic_read(&garmin_data_p->resp_count);
-}
-
-
 static inline int getLayerId(const __u8 *usbPacket)
 {
         return __le32_to_cpup((__le32 *)(usbPacket));
@@ -325,8 +313,11 @@ static int pkt_add(struct garmin_data *garmin_data_p,
                 state = garmin_data_p->state;
                 spin_unlock_irqrestore(&garmin_data_p->lock, flags);
 
+                dbg("%s - added: pkt: %d - %d bytes",
+                        __func__, pkt->seq, data_length);
+
                 /* in serial mode, if someone is waiting for data from
-                   the device, iconvert and send the next packet to tty. */
+                   the device, convert and send the next packet to tty. */
                 if (result && (state == STATE_GSP_WAIT_DATA))
                         gsp_next_packet(garmin_data_p);
         }
@@ -411,7 +402,7 @@ static int gsp_send_ack(struct garmin_data *garmin_data_p, __u8 pkt_id)
 /*
  * called for a complete packet received from tty layer
  *
- * the complete packet (pkzid ... cksum) is in garmin_data_p->inbuf starting
+ * the complete packet (pktid ... cksum) is in garmin_data_p->inbuf starting
  * at GSP_INITIAL_OFFSET.
  *
  * count - number of bytes in the input buffer including space reserved for
@@ -501,7 +492,6 @@ static int gsp_receive(struct garmin_data *garmin_data_p,
         unsigned long flags;
         int offs = 0;
         int ack_or_nak_seen = 0;
-        int i = 0;
         __u8 *dest;
         int size;
         /* dleSeen: set if last byte read was a DLE */
@@ -519,8 +509,8 @@ static int gsp_receive(struct garmin_data *garmin_data_p,
         skip = garmin_data_p->flags & FLAGS_GSP_SKIP;
         spin_unlock_irqrestore(&garmin_data_p->lock, flags);
 
-        dbg("%s - dle=%d skip=%d size=%d count=%d",
-                __func__, dleSeen, skip, size, count);
+        /* dbg("%s - dle=%d skip=%d size=%d count=%d",
+                __func__, dleSeen, skip, size, count); */
 
         if (size == 0)
                 size = GSP_INITIAL_OFFSET;
@@ -568,7 +558,6 @@ static int gsp_receive(struct garmin_data *garmin_data_p,
                 } else if (!skip) {
 
                         if (dleSeen) {
-                                dbg("non-masked DLE at %d - restarting", i);
                                 size = GSP_INITIAL_OFFSET;
                                 dleSeen = 0;
                         }
@@ -599,19 +588,19 @@ static int gsp_receive(struct garmin_data *garmin_data_p,
         else
                 garmin_data_p->flags &= ~FLAGS_GSP_DLESEEN;
 
-        if (ack_or_nak_seen)
-                garmin_data_p->state = STATE_GSP_WAIT_DATA;
-
         spin_unlock_irqrestore(&garmin_data_p->lock, flags);
 
-        if (ack_or_nak_seen)
-                gsp_next_packet(garmin_data_p);
+        if (ack_or_nak_seen) {
+                if (gsp_next_packet(garmin_data_p) > 0)
+                        garmin_data_p->state = STATE_ACTIVE;
+                else
+                        garmin_data_p->state = STATE_GSP_WAIT_DATA;
+        }
         return count;
 }
 
 
 
-
 /*
  * Sends a usb packet to the tty
  *
@@ -733,29 +722,28 @@ static int gsp_send(struct garmin_data *garmin_data_p,
 }
 
 
-
-
-
 /*
  * Process the next pending data packet - if there is one
  */
-static void gsp_next_packet(struct garmin_data *garmin_data_p)
+static int gsp_next_packet(struct garmin_data *garmin_data_p)
 {
+        int result = 0;
         struct garmin_packet *pkt = NULL;
 
         while ((pkt = pkt_pop(garmin_data_p)) != NULL) {
                 dbg("%s - next pkt: %d", __func__, pkt->seq);
-                if (gsp_send(garmin_data_p, pkt->data, pkt->size) > 0) {
+                result = gsp_send(garmin_data_p, pkt->data, pkt->size);
+                if (result > 0) {
                         kfree(pkt);
-                        return;
+                        return result;
                 }
                 kfree(pkt);
         }
+        return result;
 }
 
 
 
-
 /******************************************************************************
  * garmin native mode
  ******************************************************************************/
@@ -888,14 +876,6 @@ static int garmin_clear(struct garmin_data *garmin_data_p)
         unsigned long flags;
         int status = 0;
 
-        struct usb_serial_port *port = garmin_data_p->port;
-
-        if (port != NULL && atomic_read(&garmin_data_p->resp_count)) {
-                /* send a terminate command */
-                status = garmin_write_bulk(port, GARMIN_STOP_TRANSFER_REQ,
-                                        sizeof(GARMIN_STOP_TRANSFER_REQ), 1);
-        }
-
         /* flush all queued data */
         pkt_clear(garmin_data_p);
 
@@ -908,16 +888,12 @@ static int garmin_clear(struct garmin_data *garmin_data_p)
 }
 
 
-
-
-
-
 static int garmin_init_session(struct usb_serial_port *port)
 {
-        unsigned long flags;
         struct usb_serial *serial = port->serial;
         struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
         int status = 0;
+        int i = 0;
 
         if (status == 0) {
                 usb_kill_urb(port->interrupt_in_urb);
@@ -931,30 +907,25 @@ static int garmin_init_session(struct usb_serial_port *port)
                                                         __func__, status);
         }
 
+        /*
+         * using the initialization method from gpsbabel. See comments in
+         * gpsbabel/jeeps/gpslibusb.c gusb_reset_toggles()
+         */
         if (status == 0) {
                 dbg("%s - starting session ...", __func__);
                 garmin_data_p->state = STATE_ACTIVE;
-                status = garmin_write_bulk(port, GARMIN_START_SESSION_REQ,
-                                        sizeof(GARMIN_START_SESSION_REQ), 0);
-
-                if (status >= 0) {
-
-                        spin_lock_irqsave(&garmin_data_p->lock, flags);
-                        garmin_data_p->ignorePkts++;
-                        spin_unlock_irqrestore(&garmin_data_p->lock, flags);
 
-                        /* not needed, but the win32 driver does it too ... */
+                for (i = 0; i < 3; i++) {
                         status = garmin_write_bulk(port,
-                                        GARMIN_START_SESSION_REQ2,
-                                        sizeof(GARMIN_START_SESSION_REQ2), 0);
-                        if (status >= 0) {
-                                status = 0;
-                                spin_lock_irqsave(&garmin_data_p->lock, flags);
-                                garmin_data_p->ignorePkts++;
-                                spin_unlock_irqrestore(&garmin_data_p->lock,
-                                                                        flags);
-                        }
+                                        GARMIN_START_SESSION_REQ,
+                                        sizeof(GARMIN_START_SESSION_REQ), 0);
+
+                        if (status < 0)
+                                break;
                 }
+
+                if (status > 0)
+                        status = 0;
         }
 
         return status;
@@ -962,8 +933,6 @@ static int garmin_init_session(struct usb_serial_port *port)
 
 
 
-
-
 static int garmin_open(struct tty_struct *tty,
                         struct usb_serial_port *port, struct file *filp)
 {
@@ -977,8 +946,6 @@ static int garmin_open(struct tty_struct *tty,
         garmin_data_p->mode  = initial_mode;
         garmin_data_p->count = 0;
         garmin_data_p->flags = 0;
-        atomic_set(&garmin_data_p->req_count, 0);
-        atomic_set(&garmin_data_p->resp_count, 0);
         spin_unlock_irqrestore(&garmin_data_p->lock, flags);
 
         /* shutdown any bulk reads that might be going on */
@@ -1006,6 +973,7 @@ static void garmin_close(struct usb_serial_port *port)
                 return;
 
         mutex_lock(&port->serial->disc_mutex);
+
         if (!port->serial->disconnected)
                 garmin_clear(garmin_data_p);
 
@@ -1013,25 +981,17 @@ static void garmin_close(struct usb_serial_port *port)
         usb_kill_urb(port->read_urb);
         usb_kill_urb(port->write_urb);
 
-        if (!port->serial->disconnected) {
-                if (noResponseFromAppLayer(garmin_data_p) ||
-                    ((garmin_data_p->flags & CLEAR_HALT_REQUIRED) != 0)) {
-                        process_resetdev_request(port);
-                        garmin_data_p->state = STATE_RESET;
-                } else {
-                        garmin_data_p->state = STATE_DISCONNECTED;
-                }
-        } else {
+        /* keep reset state so we know that we must start a new session */
+        if (garmin_data_p->state != STATE_RESET)
                 garmin_data_p->state = STATE_DISCONNECTED;
-        }
+
         mutex_unlock(&port->serial->disc_mutex);
 }
 
+
 static void garmin_write_bulk_callback(struct urb *urb)
 {
-        unsigned long flags;
         struct usb_serial_port *port = urb->context;
-        int status = urb->status;
 
         if (port) {
                 struct garmin_data *garmin_data_p =
@@ -1039,20 +999,13 @@ static void garmin_write_bulk_callback(struct urb *urb)
 
                 dbg("%s - port %d", __func__, port->number);
 
-                if (GARMIN_LAYERID_APPL == getLayerId(urb->transfer_buffer)
-                    && (garmin_data_p->mode == MODE_GARMIN_SERIAL))  {
-                        gsp_send_ack(garmin_data_p,
-                                        ((__u8 *)urb->transfer_buffer)[4]);
-                }
+                if (GARMIN_LAYERID_APPL == getLayerId(urb->transfer_buffer)) {
 
-                if (status) {
-                        dbg("%s - nonzero write bulk status received: %d",
-                            __func__, status);
-                        spin_lock_irqsave(&garmin_data_p->lock, flags);
-                        garmin_data_p->flags |= CLEAR_HALT_REQUIRED;
-                        spin_unlock_irqrestore(&garmin_data_p->lock, flags);
+                        if (garmin_data_p->mode == MODE_GARMIN_SERIAL) {
+                                gsp_send_ack(garmin_data_p,
+                                        ((__u8 *)urb->transfer_buffer)[4]);
+                        }
                 }
-
                 usb_serial_port_softint(port);
         }
 
@@ -1108,7 +1061,11 @@ static int garmin_write_bulk(struct usb_serial_port *port,
         urb->transfer_flags |= URB_ZERO_PACKET;
 
         if (GARMIN_LAYERID_APPL == getLayerId(buffer)) {
-                atomic_inc(&garmin_data_p->req_count);
+
+                spin_lock_irqsave(&garmin_data_p->lock, flags);
+                garmin_data_p->flags |= APP_REQ_SEEN;
+                spin_unlock_irqrestore(&garmin_data_p->lock, flags);
+
                 if (garmin_data_p->mode == MODE_GARMIN_SERIAL)  {
                         pkt_clear(garmin_data_p);
                         garmin_data_p->state = STATE_GSP_WAIT_DATA;
@@ -1140,6 +1097,9 @@ static int garmin_write(struct tty_struct *tty, struct usb_serial_port *port,
 
         usb_serial_debug_data(debug, &port->dev, __func__, count, buf);
 
+        if (garmin_data_p->state == STATE_RESET)
+                return -EIO;
+
         /* check for our private packets */
         if (count >= GARMIN_PKTHDR_LENGTH) {
                 len = PRIVPKTSIZ;
@@ -1184,7 +1144,7 @@ static int garmin_write(struct tty_struct *tty, struct usb_serial_port *port,
                                 break;
 
                         case PRIV_PKTID_RESET_REQ:
-                                atomic_inc(&garmin_data_p->req_count);
+                                process_resetdev_request(port);
                                 break;
 
                         case PRIV_PKTID_SET_DEF_MODE:
@@ -1200,8 +1160,6 @@ static int garmin_write(struct tty_struct *tty, struct usb_serial_port *port,
                 }
         }
 
-        garmin_data_p->ignorePkts = 0;
-
         if (garmin_data_p->mode == MODE_GARMIN_SERIAL) {
                 return gsp_receive(garmin_data_p, buf, count);
         } else {        /* MODE_NATIVE */
@@ -1224,31 +1182,33 @@ static int garmin_write_room(struct tty_struct *tty)
 static void garmin_read_process(struct garmin_data *garmin_data_p,
                                  unsigned char *data, unsigned data_length)
 {
+        unsigned long flags;
+
         if (garmin_data_p->flags & FLAGS_DROP_DATA) {
                 /* abort-transfer cmd is actice */
                 dbg("%s - pkt dropped", __func__);
         } else if (garmin_data_p->state != STATE_DISCONNECTED &&
                 garmin_data_p->state != STATE_RESET) {
 
-                /* remember any appl.layer packets, so we know
-                   if a reset is required or not when closing
-                   the device */
-                if (0 == memcmp(data, GARMIN_APP_LAYER_REPLY,
-                                sizeof(GARMIN_APP_LAYER_REPLY))) {
-                        atomic_inc(&garmin_data_p->resp_count);
-                }
-
                 /* if throttling is active or postprecessing is required
                    put the received data in the input queue, otherwise
                    send it directly to the tty port */
                 if (garmin_data_p->flags & FLAGS_QUEUING) {
                         pkt_add(garmin_data_p, data, data_length);
-                } else if (garmin_data_p->mode == MODE_GARMIN_SERIAL) {
-                        if (getLayerId(data) == GARMIN_LAYERID_APPL)
+                } else if (getLayerId(data) == GARMIN_LAYERID_APPL) {
+
+                        spin_lock_irqsave(&garmin_data_p->lock, flags);
+                        garmin_data_p->flags |= APP_RESP_SEEN;
+                        spin_unlock_irqrestore(&garmin_data_p->lock, flags);
+
+                        if (garmin_data_p->mode == MODE_GARMIN_SERIAL) {
                                 pkt_add(garmin_data_p, data, data_length);
-                } else {
-                        send_to_tty(garmin_data_p->port, data, data_length);
+                        } else {
+                                send_to_tty(garmin_data_p->port, data,
+                                                data_length);
+                        }
                 }
+                /* ignore system layer packets ... */
         }
 }
 
@@ -1363,8 +1323,6 @@ static void garmin_read_int_callback(struct urb *urb)
                         } else {
                                 spin_lock_irqsave(&garmin_data_p->lock, flags);
                                 garmin_data_p->flags |= FLAGS_BULK_IN_ACTIVE;
-                                /* do not send this packet to the user */
-                                garmin_data_p->ignorePkts = 1;
                                 spin_unlock_irqrestore(&garmin_data_p->lock,
                                                                         flags);
                         }
@@ -1391,17 +1349,7 @@ static void garmin_read_int_callback(struct urb *urb)
                         __func__, garmin_data_p->serial_num);
         }
 
-        if (garmin_data_p->ignorePkts) {
-                /* this reply belongs to a request generated by the driver,
-                   ignore it. */
-                dbg("%s - pkt ignored (%d)",
-                        __func__, garmin_data_p->ignorePkts);
-                spin_lock_irqsave(&garmin_data_p->lock, flags);
-                garmin_data_p->ignorePkts--;
-                spin_unlock_irqrestore(&garmin_data_p->lock, flags);
-        } else {
-                garmin_read_process(garmin_data_p, data, urb->actual_length);
-        }
+        garmin_read_process(garmin_data_p, data, urb->actual_length);
 
         port->interrupt_in_urb->dev = port->serial->dev;
         retval = usb_submit_urb(urb, GFP_ATOMIC);
@@ -1527,7 +1475,7 @@ static int garmin_attach(struct usb_serial *serial)
 }
 
 
-static void garmin_shutdown(struct usb_serial *serial)
+static void garmin_disconnect(struct usb_serial *serial)
 {
         struct usb_serial_port *port = serial->port[0];
         struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
@@ -1536,8 +1484,17 @@ static void garmin_shutdown(struct usb_serial *serial)
 
         usb_kill_urb(port->interrupt_in_urb);
         del_timer_sync(&garmin_data_p->timer);
+}
+
+
+static void garmin_release(struct usb_serial *serial)
+{
+        struct usb_serial_port *port = serial->port[0];
+        struct garmin_data *garmin_data_p = usb_get_serial_port_data(port);
+
+        dbg("%s", __func__);
+
         kfree(garmin_data_p);
-        usb_set_serial_port_data(port, NULL);
 }
 
 
@@ -1556,7 +1513,8 @@ static struct usb_serial_driver garmin_device = {
         .throttle            = garmin_throttle,
         .unthrottle          = garmin_unthrottle,
         .attach              = garmin_attach,
-        .shutdown            = garmin_shutdown,
+        .disconnect          = garmin_disconnect,
+        .release             = garmin_release,
         .write               = garmin_write,
         .write_room          = garmin_write_room,
         .write_bulk_callback = garmin_write_bulk_callback,
diff --git a/drivers/usb/serial/generic.c b/drivers/usb/serial/generic.c
index be82ea956720..932d6241b787 100644
--- a/drivers/usb/serial/generic.c
+++ b/drivers/usb/serial/generic.c
@@ -63,7 +63,8 @@ struct usb_serial_driver usb_serial_generic_device = {
         .id_table =             generic_device_ids,
         .usb_driver =           &generic_driver,
         .num_ports =            1,
-        .shutdown =             usb_serial_generic_shutdown,
+        .disconnect =           usb_serial_generic_disconnect,
+        .release =              usb_serial_generic_release,
         .throttle =             usb_serial_generic_throttle,
         .unthrottle =           usb_serial_generic_unthrottle,
         .resume =               usb_serial_generic_resume,
@@ -190,6 +191,88 @@ void usb_serial_generic_close(struct usb_serial_port *port)
         generic_cleanup(port);
 }
 
+static int usb_serial_multi_urb_write(struct tty_struct *tty,
+        struct usb_serial_port *port, const unsigned char *buf, int count)
+{
+        unsigned long flags;
+        struct urb *urb;
+        unsigned char *buffer;
+        int status;
+        int towrite;
+        int bwrite = 0;
+
+        dbg("%s - port %d", __func__, port->number);
+
+        if (count == 0)
+                dbg("%s - write request of 0 bytes", __func__);
+
+        while (count > 0) {
+                towrite = (count > port->bulk_out_size) ?
+                        port->bulk_out_size : count;
+                spin_lock_irqsave(&port->lock, flags);
+                if (port->urbs_in_flight >
+                    port->serial->type->max_in_flight_urbs) {
+                        spin_unlock_irqrestore(&port->lock, flags);
+                        dbg("%s - write limit hit\n", __func__);
+                        return bwrite;
+                }
+                port->tx_bytes_flight += towrite;
+                port->urbs_in_flight++;
+                spin_unlock_irqrestore(&port->lock, flags);
+
+                buffer = kmalloc(towrite, GFP_ATOMIC);
+                if (!buffer) {
+                        dev_err(&port->dev,
+                        "%s ran out of kernel memory for urb ...\n", __func__);
+                        goto error_no_buffer;
+                }
+
+                urb = usb_alloc_urb(0, GFP_ATOMIC);
+                if (!urb) {
+                        dev_err(&port->dev, "%s - no more free urbs\n",
+                                __func__);
+                        goto error_no_urb;
+                }
+
+                /* Copy data */
+                memcpy(buffer, buf + bwrite, towrite);
+                usb_serial_debug_data(debug, &port->dev, __func__,
+                                      towrite, buffer);
+                /* fill the buffer and send it */
+                usb_fill_bulk_urb(urb, port->serial->dev,
+                        usb_sndbulkpipe(port->serial->dev,
+                                        port->bulk_out_endpointAddress),
+                        buffer, towrite,
+                        usb_serial_generic_write_bulk_callback, port);
+
+                status = usb_submit_urb(urb, GFP_ATOMIC);
+                if (status) {
+                        dev_err(&port->dev,
+                                "%s - failed submitting write urb, error %d\n",
+                                __func__, status);
+                        goto error;
+                }
+
+                /* This urb is the responsibility of the host driver now */
+                usb_free_urb(urb);
+                dbg("%s write: %d", __func__, towrite);
+                count -= towrite;
+                bwrite += towrite;
+        }
+        return bwrite;
+
+error:
+        usb_free_urb(urb);
+error_no_urb:
+        kfree(buffer);
+error_no_buffer:
+        spin_lock_irqsave(&port->lock, flags);
+        port->urbs_in_flight--;
+        port->tx_bytes_flight -= towrite;
+        spin_unlock_irqrestore(&port->lock, flags);
+        return bwrite;
+}
+
 int usb_serial_generic_write(struct tty_struct *tty,
         struct usb_serial_port *port, const unsigned char *buf, int count)
 {
@@ -207,6 +290,11 @@ int usb_serial_generic_write(struct tty_struct *tty,
         /* only do something if we have a bulk out endpoint */
         if (serial->num_bulk_out) {
                 unsigned long flags;
+
+                if (serial->type->max_in_flight_urbs)
+                        return usb_serial_multi_urb_write(tty, port,
+                                                          buf, count);
+
                 spin_lock_irqsave(&port->lock, flags);
                 if (port->write_urb_busy) {
                         spin_unlock_irqrestore(&port->lock, flags);
@@ -252,20 +340,26 @@ int usb_serial_generic_write(struct tty_struct *tty,
         /* no bulk out, so return 0 bytes written */
         return 0;
 }
+EXPORT_SYMBOL_GPL(usb_serial_generic_write);
 
 int usb_serial_generic_write_room(struct tty_struct *tty)
 {
         struct usb_serial_port *port = tty->driver_data;
         struct usb_serial *serial = port->serial;
+        unsigned long flags;
         int room = 0;
 
         dbg("%s - port %d", __func__, port->number);
-
-        /* FIXME: Locking */
-        if (serial->num_bulk_out) {
-                if (!(port->write_urb_busy))
-                        room = port->bulk_out_size;
+        spin_lock_irqsave(&port->lock, flags);
+        if (serial->type->max_in_flight_urbs) {
+                if (port->urbs_in_flight < serial->type->max_in_flight_urbs)
+                        room = port->bulk_out_size *
+                                (serial->type->max_in_flight_urbs -
+                                 port->urbs_in_flight);
+        } else if (serial->num_bulk_out && !(port->write_urb_busy)) {
+                room = port->bulk_out_size;
         }
+        spin_unlock_irqrestore(&port->lock, flags);
 
         dbg("%s - returns %d", __func__, room);
         return room;
@@ -276,11 +370,16 @@ int usb_serial_generic_chars_in_buffer(struct tty_struct *tty)
         struct usb_serial_port *port = tty->driver_data;
         struct usb_serial *serial = port->serial;
         int chars = 0;
+        unsigned long flags;
 
         dbg("%s - port %d", __func__, port->number);
 
-        /* FIXME: Locking */
-        if (serial->num_bulk_out) {
+        if (serial->type->max_in_flight_urbs) {
+                spin_lock_irqsave(&port->lock, flags);
+                chars = port->tx_bytes_flight;
+                spin_unlock_irqrestore(&port->lock, flags);
+        } else if (serial->num_bulk_out) {
+                /* FIXME: Locking */
                 if (port->write_urb_busy)
                         chars = port->write_urb->transfer_buffer_length;
         }
@@ -290,7 +389,8 @@ int usb_serial_generic_chars_in_buffer(struct tty_struct *tty)
 }
 
 
-static void resubmit_read_urb(struct usb_serial_port *port, gfp_t mem_flags)
+void usb_serial_generic_resubmit_read_urb(struct usb_serial_port *port,
+                        gfp_t mem_flags)
 {
         struct urb *urb = port->read_urb;
         struct usb_serial *serial = port->serial;
@@ -311,25 +411,28 @@ static void resubmit_read_urb(struct usb_serial_port *port, gfp_t mem_flags)
                         "%s - failed resubmitting read urb, error %d\n",
                                                         __func__, result);
 }
+EXPORT_SYMBOL_GPL(usb_serial_generic_resubmit_read_urb);
 
 /* Push data to tty layer and resubmit the bulk read URB */
 static void flush_and_resubmit_read_urb(struct usb_serial_port *port)
 {
         struct urb *urb = port->read_urb;
         struct tty_struct *tty = tty_port_tty_get(&port->port);
-        int room;
+        char *ch = (char *)urb->transfer_buffer;
+        int i;
+
+        if (!tty)
+                goto done;
 
         /* Push data to tty */
-        if (tty && urb->actual_length) {
-                room = tty_buffer_request_room(tty, urb->actual_length);
-                if (room) {
-                        tty_insert_flip_string(tty, urb->transfer_buffer, room);
-                        tty_flip_buffer_push(tty);
-                }
+        for (i = 0; i < urb->actual_length; i++, ch++) {
+                if (!usb_serial_handle_sysrq_char(port, *ch))
+                        tty_insert_flip_char(tty, *ch, TTY_NORMAL);
         }
+        tty_flip_buffer_push(tty);
         tty_kref_put(tty);
-
-        resubmit_read_urb(port, GFP_ATOMIC);
+done:
+        usb_serial_generic_resubmit_read_urb(port, GFP_ATOMIC);
 }
 
 void usb_serial_generic_read_bulk_callback(struct urb *urb)
@@ -363,12 +466,24 @@ EXPORT_SYMBOL_GPL(usb_serial_generic_read_bulk_callback);
 
 void usb_serial_generic_write_bulk_callback(struct urb *urb)
 {
+        unsigned long flags;
         struct usb_serial_port *port = urb->context;
         int status = urb->status;
 
         dbg("%s - port %d", __func__, port->number);
 
-        port->write_urb_busy = 0;
+        if (port->serial->type->max_in_flight_urbs) {
+                spin_lock_irqsave(&port->lock, flags);
+                --port->urbs_in_flight;
+                port->tx_bytes_flight -= urb->transfer_buffer_length;
+                if (port->urbs_in_flight < 0)
+                        port->urbs_in_flight = 0;
+                spin_unlock_irqrestore(&port->lock, flags);
+        } else {
+                /* Handle the case for single urb mode */
+                port->write_urb_busy = 0;
+        }
+
         if (status) {
                 dbg("%s - nonzero write bulk status received: %d",
                     __func__, status);
@@ -408,11 +523,36 @@ void usb_serial_generic_unthrottle(struct tty_struct *tty)
 
         if (was_throttled) {
                 /* Resume reading from device */
-                resubmit_read_urb(port, GFP_KERNEL);
+                usb_serial_generic_resubmit_read_urb(port, GFP_KERNEL);
+        }
+}
+
+int usb_serial_handle_sysrq_char(struct usb_serial_port *port, unsigned int ch)
+{
+        if (port->sysrq && port->console) {
+                if (ch && time_before(jiffies, port->sysrq)) {
+                        handle_sysrq(ch, tty_port_tty_get(&port->port));
+                        port->sysrq = 0;
+                        return 1;
+                }
+                port->sysrq = 0;
+        }
+        return 0;
+}
+EXPORT_SYMBOL_GPL(usb_serial_handle_sysrq_char);
+
+int usb_serial_handle_break(struct usb_serial_port *port)
+{
+        if (!port->sysrq) {
+                port->sysrq = jiffies + HZ*5;
+                return 1;
         }
+        port->sysrq = 0;
+        return 0;
 }
+EXPORT_SYMBOL_GPL(usb_serial_handle_break);
 
-void usb_serial_generic_shutdown(struct usb_serial *serial)
+void usb_serial_generic_disconnect(struct usb_serial *serial)
 {
         int i;
 
@@ -423,3 +563,7 @@ void usb_serial_generic_shutdown(struct usb_serial *serial)
                 generic_cleanup(serial->port[i]);
 }
 
+void usb_serial_generic_release(struct usb_serial *serial)
+{
+        dbg("%s", __func__);
+}
diff --git a/drivers/usb/serial/io_edgeport.c b/drivers/usb/serial/io_edgeport.c
index 53ef5996e33d..0191693625d6 100644
--- a/drivers/usb/serial/io_edgeport.c
+++ b/drivers/usb/serial/io_edgeport.c
@@ -224,7 +224,8 @@ static int  edge_tiocmget(struct tty_struct *tty, struct file *file);
 static int  edge_tiocmset(struct tty_struct *tty, struct file *file,
                                         unsigned int set, unsigned int clear);
 static int  edge_startup(struct usb_serial *serial);
-static void edge_shutdown(struct usb_serial *serial);
+static void edge_disconnect(struct usb_serial *serial);
+static void edge_release(struct usb_serial *serial);
 
 #include "io_tables.h"  /* all of the devices that this driver supports */
 
@@ -3193,21 +3194,16 @@ static int edge_startup(struct usb_serial *serial)
 
 
 /****************************************************************************
- * edge_shutdown
+ * edge_disconnect
  *      This function is called whenever the device is removed from the usb bus.
  ****************************************************************************/
-static void edge_shutdown(struct usb_serial *serial)
+static void edge_disconnect(struct usb_serial *serial)
 {
         struct edgeport_serial *edge_serial = usb_get_serial_data(serial);
-        int i;
 
         dbg("%s", __func__);
 
         /* stop reads and writes on all ports */
-        for (i = 0; i < serial->num_ports; ++i) {
-                kfree(usb_get_serial_port_data(serial->port[i]));
-                usb_set_serial_port_data(serial->port[i],  NULL);
-        }
         /* free up our endpoint stuff */
         if (edge_serial->is_epic) {
                 usb_kill_urb(edge_serial->interrupt_read_urb);
@@ -3218,9 +3214,24 @@ static void edge_shutdown(struct usb_serial *serial)
                 usb_free_urb(edge_serial->read_urb);
                 kfree(edge_serial->bulk_in_buffer);
         }
+}
+
+
+/****************************************************************************
+ * edge_release
+ *      This function is called when the device structure is deallocated.
+ ****************************************************************************/
+static void edge_release(struct usb_serial *serial)
+{
+        struct edgeport_serial *edge_serial = usb_get_serial_data(serial);
+        int i;
+
+        dbg("%s", __func__);
+
+        for (i = 0; i < serial->num_ports; ++i)
+                kfree(usb_get_serial_port_data(serial->port[i]));
 
         kfree(edge_serial);
-        usb_set_serial_data(serial, NULL);
 }
 
 
diff --git a/drivers/usb/serial/io_tables.h b/drivers/usb/serial/io_tables.h
index 7eb9d67b81b6..9241d3147513 100644
--- a/drivers/usb/serial/io_tables.h
+++ b/drivers/usb/serial/io_tables.h
@@ -117,7 +117,8 @@ static struct usb_serial_driver edgeport_2port_device = {
         .throttle               = edge_throttle,
         .unthrottle             = edge_unthrottle,
         .attach                 = edge_startup,
-        .shutdown               = edge_shutdown,
+        .disconnect             = edge_disconnect,
+        .release                = edge_release,
         .ioctl                  = edge_ioctl,
         .set_termios            = edge_set_termios,
         .tiocmget               = edge_tiocmget,
@@ -145,7 +146,8 @@ static struct usb_serial_driver edgeport_4port_device = {
         .throttle               = edge_throttle,
         .unthrottle             = edge_unthrottle,
         .attach                 = edge_startup,
-        .shutdown               = edge_shutdown,
+        .disconnect             = edge_disconnect,
+        .release                = edge_release,
         .ioctl                  = edge_ioctl,
         .set_termios            = edge_set_termios,
         .tiocmget               = edge_tiocmget,
@@ -173,7 +175,8 @@ static struct usb_serial_driver edgeport_8port_device = {
         .throttle               = edge_throttle,
         .unthrottle             = edge_unthrottle,
         .attach                 = edge_startup,
-        .shutdown               = edge_shutdown,
+        .disconnect             = edge_disconnect,
+        .release                = edge_release,
         .ioctl                  = edge_ioctl,
         .set_termios            = edge_set_termios,
         .tiocmget               = edge_tiocmget,
@@ -200,7 +203,8 @@ static struct usb_serial_driver epic_device = {
         .throttle               = edge_throttle,
         .unthrottle             = edge_unthrottle,
         .attach                 = edge_startup,
-        .shutdown               = edge_shutdown,
+        .disconnect             = edge_disconnect,
+        .release                = edge_release,
         .ioctl                  = edge_ioctl,
         .set_termios            = edge_set_termios,
         .tiocmget               = edge_tiocmget,
diff --git a/drivers/usb/serial/io_ti.c b/drivers/usb/serial/io_ti.c
index db964db42d3c..e8bc42f92e79 100644
--- a/drivers/usb/serial/io_ti.c
+++ b/drivers/usb/serial/io_ti.c
@@ -2663,7 +2663,7 @@ cleanup:
         return -ENOMEM;
 }
 
-static void edge_shutdown(struct usb_serial *serial)
+static void edge_disconnect(struct usb_serial *serial)
 {
         int i;
         struct edgeport_port *edge_port;
@@ -2673,12 +2673,22 @@ static void edge_shutdown(struct usb_serial *serial)
         for (i = 0; i < serial->num_ports; ++i) {
                 edge_port = usb_get_serial_port_data(serial->port[i]);
                 edge_remove_sysfs_attrs(edge_port->port);
+        }
+}
+
+static void edge_release(struct usb_serial *serial)
+{
+        int i;
+        struct edgeport_port *edge_port;
+
+        dbg("%s", __func__);
+
+        for (i = 0; i < serial->num_ports; ++i) {
+                edge_port = usb_get_serial_port_data(serial->port[i]);
                 edge_buf_free(edge_port->ep_out_buf);
                 kfree(edge_port);
-                usb_set_serial_port_data(serial->port[i], NULL);
         }
         kfree(usb_get_serial_data(serial));
-        usb_set_serial_data(serial, NULL);
 }
 
 
@@ -2915,7 +2925,8 @@ static struct usb_serial_driver edgeport_1port_device = {
         .throttle               = edge_throttle,
         .unthrottle             = edge_unthrottle,
         .attach                 = edge_startup,
-        .shutdown               = edge_shutdown,
+        .disconnect             = edge_disconnect,
+        .release                = edge_release,
         .port_probe             = edge_create_sysfs_attrs,
         .ioctl                  = edge_ioctl,
         .set_termios            = edge_set_termios,
@@ -2944,7 +2955,8 @@ static struct usb_serial_driver edgeport_2port_device = {
         .throttle               = edge_throttle,
         .unthrottle             = edge_unthrottle,
         .attach                 = edge_startup,
-        .shutdown               = edge_shutdown,
+        .disconnect             = edge_disconnect,
+        .release                = edge_release,
         .port_probe             = edge_create_sysfs_attrs,
         .ioctl                  = edge_ioctl,
         .set_termios            = edge_set_termios,
diff --git a/drivers/usb/serial/ipaq.c b/drivers/usb/serial/ipaq.c
index c610a99fa477..2545d45ce16f 100644
--- a/drivers/usb/serial/ipaq.c
+++ b/drivers/usb/serial/ipaq.c
@@ -79,7 +79,6 @@ static int  ipaq_open(struct tty_struct *tty,
 static void ipaq_close(struct usb_serial_port *port);
 static int  ipaq_calc_num_ports(struct usb_serial *serial);
 static int  ipaq_startup(struct usb_serial *serial);
-static void ipaq_shutdown(struct usb_serial *serial);
 static int ipaq_write(struct tty_struct *tty, struct usb_serial_port *port,
                         const unsigned char *buf, int count);
 static int ipaq_write_bulk(struct usb_serial_port *port,
@@ -576,7 +575,6 @@ static struct usb_serial_driver ipaq_device = {
         .close =                ipaq_close,
         .attach =               ipaq_startup,
         .calc_num_ports =       ipaq_calc_num_ports,
-        .shutdown =             ipaq_shutdown,
         .write =                ipaq_write,
         .write_room =           ipaq_write_room,
         .chars_in_buffer =      ipaq_chars_in_buffer,
@@ -990,11 +988,6 @@ static int ipaq_startup(struct usb_serial *serial)
         return usb_reset_configuration(serial->dev);
 }
 
-static void ipaq_shutdown(struct usb_serial *serial)
-{
-        dbg("%s", __func__);
-}
-
 static int __init ipaq_init(void)
 {
         int retval;
diff --git a/drivers/usb/serial/iuu_phoenix.c b/drivers/usb/serial/iuu_phoenix.c
index 76a3cc327bb9..96873a7a32b0 100644
--- a/drivers/usb/serial/iuu_phoenix.c
+++ b/drivers/usb/serial/iuu_phoenix.c
@@ -121,8 +121,8 @@ static int iuu_startup(struct usb_serial *serial)
         return 0;
 }
 
-/* Shutdown function */
-static void iuu_shutdown(struct usb_serial *serial)
+/* Release function */
+static void iuu_release(struct usb_serial *serial)
 {
         struct usb_serial_port *port = serial->port[0];
         struct iuu_private *priv = usb_get_serial_port_data(port);
@@ -1202,7 +1202,7 @@ static struct usb_serial_driver iuu_device = {
         .tiocmset = iuu_tiocmset,
         .set_termios = iuu_set_termios,
         .attach = iuu_startup,
-        .shutdown = iuu_shutdown,
+        .release = iuu_release,
 };
 
 static int __init iuu_init(void)
diff --git a/drivers/usb/serial/keyspan.c b/drivers/usb/serial/keyspan.c
index f1195a98f316..2594b8743d3f 100644
--- a/drivers/usb/serial/keyspan.c
+++ b/drivers/usb/serial/keyspan.c
@@ -2689,7 +2689,7 @@ static int keyspan_startup(struct usb_serial *serial)
         return 0;
 }
 
-static void keyspan_shutdown(struct usb_serial *serial)
+static void keyspan_disconnect(struct usb_serial *serial)
 {
         int                             i, j;
         struct usb_serial_port          *port;
@@ -2729,6 +2729,17 @@ static void keyspan_shutdown(struct usb_serial *serial)
                         usb_free_urb(p_priv->out_urbs[j]);
                 }
         }
+}
+
+static void keyspan_release(struct usb_serial *serial)
+{
+        int                             i;
+        struct usb_serial_port          *port;
+        struct keyspan_serial_private   *s_priv;
+
+        dbg("%s", __func__);
+
+        s_priv = usb_get_serial_data(serial);
 
         /*  dbg("Freeing serial->private."); */
         kfree(s_priv);
diff --git a/drivers/usb/serial/keyspan.h b/drivers/usb/serial/keyspan.h
index 0d4569b60768..3107ed15af64 100644
--- a/drivers/usb/serial/keyspan.h
+++ b/drivers/usb/serial/keyspan.h
@@ -41,7 +41,8 @@ static int  keyspan_open		(struct tty_struct *tty,
 static void keyspan_close               (struct usb_serial_port *port);
 static void keyspan_dtr_rts             (struct usb_serial_port *port, int on);
 static int  keyspan_startup             (struct usb_serial *serial);
-static void keyspan_shutdown            (struct usb_serial *serial);
+static void keyspan_disconnect          (struct usb_serial *serial);
+static void keyspan_release             (struct usb_serial *serial);
 static int  keyspan_write_room          (struct tty_struct *tty);
 
 static int  keyspan_write               (struct tty_struct *tty,
@@ -569,7 +570,8 @@ static struct usb_serial_driver keyspan_1port_device = {
         .tiocmget               = keyspan_tiocmget,
         .tiocmset               = keyspan_tiocmset,
         .attach                 = keyspan_startup,
-        .shutdown               = keyspan_shutdown,
+        .disconnect             = keyspan_disconnect,
+        .release                = keyspan_release,
 };
 
 static struct usb_serial_driver keyspan_2port_device = {
@@ -590,7 +592,8 @@ static struct usb_serial_driver keyspan_2port_device = {
         .tiocmget               = keyspan_tiocmget,
         .tiocmset               = keyspan_tiocmset,
         .attach                 = keyspan_startup,
-        .shutdown               = keyspan_shutdown,
+        .disconnect             = keyspan_disconnect,
+        .release                = keyspan_release,
 };
 
 static struct usb_serial_driver keyspan_4port_device = {
@@ -611,7 +614,8 @@ static struct usb_serial_driver keyspan_4port_device = {
         .tiocmget               = keyspan_tiocmget,
         .tiocmset               = keyspan_tiocmset,
         .attach                 = keyspan_startup,
-        .shutdown               = keyspan_shutdown,
+        .disconnect             = keyspan_disconnect,
+        .release                = keyspan_release,
 };
 
 #endif
diff --git a/drivers/usb/serial/keyspan_pda.c b/drivers/usb/serial/keyspan_pda.c
index ab769dbea1b3..d0b12e40c2b1 100644
--- a/drivers/usb/serial/keyspan_pda.c
+++ b/drivers/usb/serial/keyspan_pda.c
@@ -809,7 +809,7 @@ static int keyspan_pda_startup(struct usb_serial *serial)
         return 0;
 }
 
-static void keyspan_pda_shutdown(struct usb_serial *serial)
+static void keyspan_pda_release(struct usb_serial *serial)
 {
         dbg("%s", __func__);
 
@@ -869,7 +869,7 @@ static struct usb_serial_driver keyspan_pda_device = {
         .tiocmget =             keyspan_pda_tiocmget,
         .tiocmset =             keyspan_pda_tiocmset,
         .attach =               keyspan_pda_startup,
-        .shutdown =             keyspan_pda_shutdown,
+        .release =              keyspan_pda_release,
 };
 
 
diff --git a/drivers/usb/serial/kl5kusb105.c b/drivers/usb/serial/kl5kusb105.c
index fa817c66b3e8..0f44bb8e8d4f 100644
--- a/drivers/usb/serial/kl5kusb105.c
+++ b/drivers/usb/serial/kl5kusb105.c
@@ -73,7 +73,8 @@ static int debug;
  * Function prototypes
  */
 static int  klsi_105_startup(struct usb_serial *serial);
-static void klsi_105_shutdown(struct usb_serial *serial);
+static void klsi_105_disconnect(struct usb_serial *serial);
+static void klsi_105_release(struct usb_serial *serial);
 static int  klsi_105_open(struct tty_struct *tty,
                         struct usb_serial_port *port, struct file *filp);
 static void klsi_105_close(struct usb_serial_port *port);
@@ -131,7 +132,8 @@ static struct usb_serial_driver kl5kusb105d_device = {
         .tiocmget =          klsi_105_tiocmget,
         .tiocmset =          klsi_105_tiocmset,
         .attach =            klsi_105_startup,
-        .shutdown =          klsi_105_shutdown,
+        .disconnect =        klsi_105_disconnect,
+        .release =           klsi_105_release,
         .throttle =          klsi_105_throttle,
         .unthrottle =        klsi_105_unthrottle,
 };
@@ -315,7 +317,7 @@ err_cleanup:
 } /* klsi_105_startup */
 
 
-static void klsi_105_shutdown(struct usb_serial *serial)
+static void klsi_105_disconnect(struct usb_serial *serial)
 {
         int i;
 
@@ -325,33 +327,36 @@ static void klsi_105_shutdown(struct usb_serial *serial)
         for (i = 0; i < serial->num_ports; ++i) {
                 struct klsi_105_private *priv =
                                 usb_get_serial_port_data(serial->port[i]);
-                unsigned long flags;
 
                 if (priv) {
                         /* kill our write urb pool */
                         int j;
                         struct urb **write_urbs = priv->write_urb_pool;
-                        spin_lock_irqsave(&priv->lock, flags);
 
                         for (j = 0; j < NUM_URBS; j++) {
                                 if (write_urbs[j]) {
-                                        /* FIXME - uncomment the following
-                                         * usb_kill_urb call when the host
-                                         * controllers get fixed to set
-                                         * urb->dev = NULL after the urb is
-                                         * finished.  Otherwise this call
-                                         * oopses. */
-                                        /* usb_kill_urb(write_urbs[j]); */
-                                        kfree(write_urbs[j]->transfer_buffer);
+                                        usb_kill_urb(write_urbs[j]);
                                         usb_free_urb(write_urbs[j]);
                                 }
                         }
-                        spin_unlock_irqrestore(&priv->lock, flags);
-                        kfree(priv);
-                        usb_set_serial_port_data(serial->port[i], NULL);
                 }
         }
-} /* klsi_105_shutdown */
+} /* klsi_105_disconnect */
+
+
+static void klsi_105_release(struct usb_serial *serial)
+{
+        int i;
+
+        dbg("%s", __func__);
+
+        for (i = 0; i < serial->num_ports; ++i) {
+                struct klsi_105_private *priv =
+                                usb_get_serial_port_data(serial->port[i]);
+
+                kfree(priv);
+        }
+} /* klsi_105_release */
 
 static int  klsi_105_open(struct tty_struct *tty,
                         struct usb_serial_port *port, struct file *filp)
diff --git a/drivers/usb/serial/kobil_sct.c b/drivers/usb/serial/kobil_sct.c
index 6b570498287f..6db0e561f680 100644
--- a/drivers/usb/serial/kobil_sct.c
+++ b/drivers/usb/serial/kobil_sct.c
@@ -69,7 +69,7 @@ static int debug;
 
 /* Function prototypes */
 static int  kobil_startup(struct usb_serial *serial);
-static void kobil_shutdown(struct usb_serial *serial);
+static void kobil_release(struct usb_serial *serial);
 static int  kobil_open(struct tty_struct *tty,
                         struct usb_serial_port *port, struct file *filp);
 static void kobil_close(struct usb_serial_port *port);
@@ -117,7 +117,7 @@ static struct usb_serial_driver kobil_device = {
         .id_table =             id_table,
         .num_ports =            1,
         .attach =               kobil_startup,
-        .shutdown =             kobil_shutdown,
+        .release =              kobil_release,
         .ioctl =                kobil_ioctl,
         .set_termios =          kobil_set_termios,
         .tiocmget =             kobil_tiocmget,
@@ -201,17 +201,13 @@ static int kobil_startup(struct usb_serial *serial)
 }
 
 
-static void kobil_shutdown(struct usb_serial *serial)
+static void kobil_release(struct usb_serial *serial)
 {
         int i;
         dbg("%s - port %d", __func__, serial->port[0]->number);
 
-        for (i = 0; i < serial->num_ports; ++i) {
-                while (serial->port[i]->port.count > 0)
-                        kobil_close(serial->port[i]);
+        for (i = 0; i < serial->num_ports; ++i)
                 kfree(usb_get_serial_port_data(serial->port[i]));
-                usb_set_serial_port_data(serial->port[i], NULL);
-        }
 }
 
 
diff --git a/drivers/usb/serial/mct_u232.c b/drivers/usb/serial/mct_u232.c
index 873795548fc0..d8825e159aa5 100644
--- a/drivers/usb/serial/mct_u232.c
+++ b/drivers/usb/serial/mct_u232.c
@@ -92,7 +92,7 @@ static int debug;
  * Function prototypes
  */
 static int  mct_u232_startup(struct usb_serial *serial);
-static void mct_u232_shutdown(struct usb_serial *serial);
+static void mct_u232_release(struct usb_serial *serial);
 static int  mct_u232_open(struct tty_struct *tty,
                         struct usb_serial_port *port, struct file *filp);
 static void mct_u232_close(struct usb_serial_port *port);
@@ -149,7 +149,7 @@ static struct usb_serial_driver mct_u232_device = {
         .tiocmget =          mct_u232_tiocmget,
         .tiocmset =          mct_u232_tiocmset,
         .attach =            mct_u232_startup,
-        .shutdown =          mct_u232_shutdown,
+        .release =           mct_u232_release,
 };
 
 
@@ -407,7 +407,7 @@ static int mct_u232_startup(struct usb_serial *serial)
 } /* mct_u232_startup */
 
 
-static void mct_u232_shutdown(struct usb_serial *serial)
+static void mct_u232_release(struct usb_serial *serial)
 {
         struct mct_u232_private *priv;
         int i;
@@ -417,12 +417,9 @@ static void mct_u232_shutdown(struct usb_serial *serial)
         for (i = 0; i < serial->num_ports; ++i) {
                 /* My special items, the standard routines free my urbs */
                 priv = usb_get_serial_port_data(serial->port[i]);
-                if (priv) {
-                        usb_set_serial_port_data(serial->port[i], NULL);
-                        kfree(priv);
-                }
+                kfree(priv);
         }
-} /* mct_u232_shutdown */
+} /* mct_u232_release */
 
 static int  mct_u232_open(struct tty_struct *tty,
                         struct usb_serial_port *port, struct file *filp)
diff --git a/drivers/usb/serial/mos7720.c b/drivers/usb/serial/mos7720.c
index 9e1a013ee7f6..bfc5ce000ef9 100644
--- a/drivers/usb/serial/mos7720.c
+++ b/drivers/usb/serial/mos7720.c
@@ -1521,19 +1521,16 @@ static int mos7720_startup(struct usb_serial *serial)
         return 0;
 }
 
-static void mos7720_shutdown(struct usb_serial *serial)
+static void mos7720_release(struct usb_serial *serial)
 {
         int i;
 
         /* free private structure allocated for serial port */
-        for (i = 0; i < serial->num_ports; ++i) {
+        for (i = 0; i < serial->num_ports; ++i)
                 kfree(usb_get_serial_port_data(serial->port[i]));
-                usb_set_serial_port_data(serial->port[i], NULL);
-        }
 
         /* free private structure allocated for serial device */
         kfree(usb_get_serial_data(serial));
-        usb_set_serial_data(serial, NULL);
 }
 
 static struct usb_driver usb_driver = {
@@ -1558,7 +1555,7 @@ static struct usb_serial_driver moschip7720_2port_driver = {
         .throttle               = mos7720_throttle,
         .unthrottle             = mos7720_unthrottle,
         .attach                 = mos7720_startup,
-        .shutdown               = mos7720_shutdown,
+        .release                = mos7720_release,
         .ioctl                  = mos7720_ioctl,
         .set_termios            = mos7720_set_termios,
         .write                  = mos7720_write,
diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c
index 10b78a37214f..c40f95c1951c 100644
--- a/drivers/usb/serial/mos7840.c
+++ b/drivers/usb/serial/mos7840.c
@@ -238,7 +238,7 @@ static int mos7840_set_reg_sync(struct usb_serial_port *port, __u16 reg,
 {
         struct usb_device *dev = port->serial->dev;
         val = val & 0x00ff;
-        dbg("mos7840_set_reg_sync offset is %x, value %x\n", reg, val);
+        dbg("mos7840_set_reg_sync offset is %x, value %x", reg, val);
 
         return usb_control_msg(dev, usb_sndctrlpipe(dev, 0), MCS_WRREQ,
                                MCS_WR_RTYPE, val, reg, NULL, 0,
@@ -260,7 +260,7 @@ static int mos7840_get_reg_sync(struct usb_serial_port *port, __u16 reg,
         ret = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), MCS_RDREQ,
                               MCS_RD_RTYPE, 0, reg, val, VENDOR_READ_LENGTH,
                               MOS_WDR_TIMEOUT);
-        dbg("mos7840_get_reg_sync offset is %x, return val %x\n", reg, *val);
+        dbg("mos7840_get_reg_sync offset is %x, return val %x", reg, *val);
         *val = (*val) & 0x00ff;
         return ret;
 }
@@ -282,18 +282,18 @@ static int mos7840_set_uart_reg(struct usb_serial_port *port, __u16 reg,
         if (port->serial->num_ports == 4) {
                 val |= (((__u16) port->number -
                                 (__u16) (port->serial->minor)) + 1) << 8;
-                dbg("mos7840_set_uart_reg application number is %x\n", val);
+                dbg("mos7840_set_uart_reg application number is %x", val);
         } else {
                 if (((__u16) port->number - (__u16) (port->serial->minor)) == 0) {
                         val |= (((__u16) port->number -
                               (__u16) (port->serial->minor)) + 1) << 8;
-                        dbg("mos7840_set_uart_reg application number is %x\n",
+                        dbg("mos7840_set_uart_reg application number is %x",
                             val);
                 } else {
                         val |=
                             (((__u16) port->number -
                               (__u16) (port->serial->minor)) + 2) << 8;
-                        dbg("mos7840_set_uart_reg application number is %x\n",
+                        dbg("mos7840_set_uart_reg application number is %x",
                             val);
                 }
         }
@@ -315,24 +315,24 @@ static int mos7840_get_uart_reg(struct usb_serial_port *port, __u16 reg,
         int ret = 0;
         __u16 Wval;
 
-        /* dbg("application number is %4x \n",
+        /* dbg("application number is %4x",
             (((__u16)port->number - (__u16)(port->serial->minor))+1)<<8); */
         /* Wval  is same as application number */
         if (port->serial->num_ports == 4) {
                 Wval =
                     (((__u16) port->number - (__u16) (port->serial->minor)) +
                      1) << 8;
-                dbg("mos7840_get_uart_reg application number is %x\n", Wval);
+                dbg("mos7840_get_uart_reg application number is %x", Wval);
         } else {
                 if (((__u16) port->number - (__u16) (port->serial->minor)) == 0) {
                         Wval = (((__u16) port->number -
                               (__u16) (port->serial->minor)) + 1) << 8;
-                        dbg("mos7840_get_uart_reg application number is %x\n",
+                        dbg("mos7840_get_uart_reg application number is %x",
                             Wval);
                 } else {
                         Wval = (((__u16) port->number -
                               (__u16) (port->serial->minor)) + 2) << 8;
-                        dbg("mos7840_get_uart_reg application number is %x\n",
+                        dbg("mos7840_get_uart_reg application number is %x",
                             Wval);
                 }
         }
@@ -346,11 +346,11 @@ static int mos7840_get_uart_reg(struct usb_serial_port *port, __u16 reg,
 static void mos7840_dump_serial_port(struct moschip_port *mos7840_port)
 {
 
-        dbg("***************************************\n");
-        dbg("SpRegOffset is %2x\n", mos7840_port->SpRegOffset);
-        dbg("ControlRegOffset is %2x \n", mos7840_port->ControlRegOffset);
-        dbg("DCRRegOffset is %2x \n", mos7840_port->DcrRegOffset);
-        dbg("***************************************\n");
+        dbg("***************************************");
+        dbg("SpRegOffset is %2x", mos7840_port->SpRegOffset);
+        dbg("ControlRegOffset is %2x", mos7840_port->ControlRegOffset);
+        dbg("DCRRegOffset is %2x", mos7840_port->DcrRegOffset);
+        dbg("***************************************");
 
 }
 
@@ -474,12 +474,12 @@ static void mos7840_control_callback(struct urb *urb)
                 goto exit;
         }
 
-        dbg("%s urb buffer size is %d\n", __func__, urb->actual_length);
-        dbg("%s mos7840_port->MsrLsr is %d port %d\n", __func__,
+        dbg("%s urb buffer size is %d", __func__, urb->actual_length);
+        dbg("%s mos7840_port->MsrLsr is %d port %d", __func__,
             mos7840_port->MsrLsr, mos7840_port->port_num);
         data = urb->transfer_buffer;
         regval = (__u8) data[0];
-        dbg("%s data is %x\n", __func__, regval);
+        dbg("%s data is %x", __func__, regval);
         if (mos7840_port->MsrLsr == 0)
                 mos7840_handle_new_msr(mos7840_port, regval);
         else if (mos7840_port->MsrLsr == 1)
@@ -538,7 +538,7 @@ static void mos7840_interrupt_callback(struct urb *urb)
         __u16 wval, wreg = 0;
         int status = urb->status;
 
-        dbg("%s", " : Entering\n");
+        dbg("%s", " : Entering");
 
         switch (status) {
         case 0:
@@ -570,7 +570,7 @@ static void mos7840_interrupt_callback(struct urb *urb)
          * Byte 5 FIFO status for both */
 
         if (length && length > 5) {
-                dbg("%s \n", "Wrong data !!!");
+                dbg("%s", "Wrong data !!!");
                 return;
         }
 
@@ -587,17 +587,17 @@ static void mos7840_interrupt_callback(struct urb *urb)
                       (__u16) (serial->minor)) + 1) << 8;
                 if (mos7840_port->open) {
                         if (sp[i] & 0x01) {
-                                dbg("SP%d No Interrupt !!!\n", i);
+                                dbg("SP%d No Interrupt !!!", i);
                         } else {
                                 switch (sp[i] & 0x0f) {
                                 case SERIAL_IIR_RLS:
                                         dbg("Serial Port %d: Receiver status error or ", i);
-                                        dbg("address bit detected in 9-bit mode\n");
+                                        dbg("address bit detected in 9-bit mode");
                                         mos7840_port->MsrLsr = 1;
                                         wreg = LINE_STATUS_REGISTER;
                                         break;
                                 case SERIAL_IIR_MS:
-                                        dbg("Serial Port %d: Modem status change\n", i);
+                                        dbg("Serial Port %d: Modem status change", i);
                                         mos7840_port->MsrLsr = 0;
                                         wreg = MODEM_STATUS_REGISTER;
                                         break;
@@ -689,7 +689,7 @@ static void mos7840_bulk_in_callback(struct urb *urb)
 
         mos7840_port = urb->context;
         if (!mos7840_port) {
-                dbg("%s", "NULL mos7840_port pointer \n");
+                dbg("%s", "NULL mos7840_port pointer");
                 mos7840_port->read_urb_busy = false;
                 return;
         }
@@ -702,41 +702,41 @@ static void mos7840_bulk_in_callback(struct urb *urb)
 
         port = (struct usb_serial_port *)mos7840_port->port;
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Port Paranoia failed \n");
+                dbg("%s", "Port Paranoia failed");
                 mos7840_port->read_urb_busy = false;
                 return;
         }
 
         serial = mos7840_get_usb_serial(port, __func__);
         if (!serial) {
-                dbg("%s\n", "Bad serial pointer ");
+                dbg("%s", "Bad serial pointer");
                 mos7840_port->read_urb_busy = false;
                 return;
         }
 
-        dbg("%s\n", "Entering... \n");
+        dbg("%s", "Entering... ");
 
         data = urb->transfer_buffer;
 
-        dbg("%s", "Entering ........... \n");
+        dbg("%s", "Entering ...........");
 
         if (urb->actual_length) {
                 tty = tty_port_tty_get(&mos7840_port->port->port);
                 if (tty) {
                         tty_buffer_request_room(tty, urb->actual_length);
                         tty_insert_flip_string(tty, data, urb->actual_length);
-                        dbg(" %s \n", data);
+                        dbg(" %s ", data);
                         tty_flip_buffer_push(tty);
                         tty_kref_put(tty);
                 }
                 mos7840_port->icount.rx += urb->actual_length;
                 smp_wmb();
-                dbg("mos7840_port->icount.rx is %d:\n",
+                dbg("mos7840_port->icount.rx is %d:",
                     mos7840_port->icount.rx);
         }
 
         if (!mos7840_port->read_urb) {
-                dbg("%s", "URB KILLED !!!\n");
+                dbg("%s", "URB KILLED !!!");
                 mos7840_port->read_urb_busy = false;
                 return;
         }
@@ -777,16 +777,16 @@ static void mos7840_bulk_out_data_callback(struct urb *urb)
         spin_unlock(&mos7840_port->pool_lock);
 
         if (status) {
-                dbg("nonzero write bulk status received:%d\n", status);
+                dbg("nonzero write bulk status received:%d", status);
                 return;
         }
 
         if (mos7840_port_paranoia_check(mos7840_port->port, __func__)) {
-                dbg("%s", "Port Paranoia failed \n");
+                dbg("%s", "Port Paranoia failed");
                 return;
         }
 
-        dbg("%s \n", "Entering .........");
+        dbg("%s", "Entering .........");
 
         tty = tty_port_tty_get(&mos7840_port->port->port);
         if (tty && mos7840_port->open)
@@ -830,15 +830,17 @@ static int mos7840_open(struct tty_struct *tty,
         struct moschip_port *mos7840_port;
         struct moschip_port *port0;
 
+        dbg ("%s enter", __func__);
+
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Port Paranoia failed \n");
+                dbg("%s", "Port Paranoia failed");
                 return -ENODEV;
         }
 
         serial = port->serial;
 
         if (mos7840_serial_paranoia_check(serial, __func__)) {
-                dbg("%s", "Serial Paranoia failed \n");
+                dbg("%s", "Serial Paranoia failed");
                 return -ENODEV;
         }
 
@@ -891,20 +893,20 @@ static int mos7840_open(struct tty_struct *tty,
         Data = 0x0;
         status = mos7840_get_reg_sync(port, mos7840_port->SpRegOffset, &Data);
         if (status < 0) {
-                dbg("Reading Spreg failed\n");
+                dbg("Reading Spreg failed");
                 return -1;
         }
         Data |= 0x80;
         status = mos7840_set_reg_sync(port, mos7840_port->SpRegOffset, Data);
         if (status < 0) {
-                dbg("writing Spreg failed\n");
+                dbg("writing Spreg failed");
                 return -1;
         }
 
         Data &= ~0x80;
         status = mos7840_set_reg_sync(port, mos7840_port->SpRegOffset, Data);
         if (status < 0) {
-                dbg("writing Spreg failed\n");
+                dbg("writing Spreg failed");
                 return -1;
         }
         /* End of block to be checked */
@@ -913,7 +915,7 @@ static int mos7840_open(struct tty_struct *tty,
         status = mos7840_get_reg_sync(port, mos7840_port->ControlRegOffset,
                                                                         &Data);
         if (status < 0) {
-                dbg("Reading Controlreg failed\n");
+                dbg("Reading Controlreg failed");
                 return -1;
         }
         Data |= 0x08;           /* Driver done bit */
@@ -921,7 +923,7 @@ static int mos7840_open(struct tty_struct *tty,
         status = mos7840_set_reg_sync(port,
                                 mos7840_port->ControlRegOffset, Data);
         if (status < 0) {
-                dbg("writing Controlreg failed\n");
+                dbg("writing Controlreg failed");
                 return -1;
         }
         /* do register settings here */
@@ -932,21 +934,21 @@ static int mos7840_open(struct tty_struct *tty,
         Data = 0x00;
         status = mos7840_set_uart_reg(port, INTERRUPT_ENABLE_REGISTER, Data);
         if (status < 0) {
-                dbg("disableing interrupts failed\n");
+                dbg("disabling interrupts failed");
                 return -1;
         }
         /* Set FIFO_CONTROL_REGISTER to the default value */
         Data = 0x00;
         status = mos7840_set_uart_reg(port, FIFO_CONTROL_REGISTER, Data);
         if (status < 0) {
-                dbg("Writing FIFO_CONTROL_REGISTER  failed\n");
+                dbg("Writing FIFO_CONTROL_REGISTER  failed");
                 return -1;
         }
 
         Data = 0xcf;
         status = mos7840_set_uart_reg(port, FIFO_CONTROL_REGISTER, Data);
         if (status < 0) {
-                dbg("Writing FIFO_CONTROL_REGISTER  failed\n");
+                dbg("Writing FIFO_CONTROL_REGISTER  failed");
                 return -1;
         }
 
@@ -1043,12 +1045,12 @@ static int mos7840_open(struct tty_struct *tty,
          * (can't set it up in mos7840_startup as the  *
          * structures were not set up at that time.)   */
 
-        dbg("port number is %d \n", port->number);
-        dbg("serial number is %d \n", port->serial->minor);
-        dbg("Bulkin endpoint is %d \n", port->bulk_in_endpointAddress);
-        dbg("BulkOut endpoint is %d \n", port->bulk_out_endpointAddress);
-        dbg("Interrupt endpoint is %d \n", port->interrupt_in_endpointAddress);
-        dbg("port's number in the device is %d\n", mos7840_port->port_num);
+        dbg("port number is %d", port->number);
+        dbg("serial number is %d", port->serial->minor);
+        dbg("Bulkin endpoint is %d", port->bulk_in_endpointAddress);
+        dbg("BulkOut endpoint is %d", port->bulk_out_endpointAddress);
+        dbg("Interrupt endpoint is %d", port->interrupt_in_endpointAddress);
+        dbg("port's number in the device is %d", mos7840_port->port_num);
         mos7840_port->read_urb = port->read_urb;
 
         /* set up our bulk in urb */
@@ -1061,7 +1063,7 @@ static int mos7840_open(struct tty_struct *tty,
                           mos7840_port->read_urb->transfer_buffer_length,
                           mos7840_bulk_in_callback, mos7840_port);
 
-        dbg("mos7840_open: bulkin endpoint is %d\n",
+        dbg("mos7840_open: bulkin endpoint is %d",
             port->bulk_in_endpointAddress);
         mos7840_port->read_urb_busy = true;
         response = usb_submit_urb(mos7840_port->read_urb, GFP_KERNEL);
@@ -1087,9 +1089,11 @@ static int mos7840_open(struct tty_struct *tty,
         mos7840_port->icount.tx = 0;
         mos7840_port->icount.rx = 0;
 
-        dbg("\n\nusb_serial serial:%p       mos7840_port:%p\n      usb_serial_port port:%p\n\n",
+        dbg("usb_serial serial:%p       mos7840_port:%p\n      usb_serial_port port:%p",
                                 serial, mos7840_port, port);
 
+        dbg ("%s leave", __func__);
+
         return 0;
 
 }
@@ -1112,16 +1116,16 @@ static int mos7840_chars_in_buffer(struct tty_struct *tty)
         unsigned long flags;
         struct moschip_port *mos7840_port;
 
-        dbg("%s \n", " mos7840_chars_in_buffer:entering ...........");
+        dbg("%s", " mos7840_chars_in_buffer:entering ...........");
 
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Invalid port \n");
+                dbg("%s", "Invalid port");
                 return 0;
         }
 
         mos7840_port = mos7840_get_port_private(port);
         if (mos7840_port == NULL) {
-                dbg("%s \n", "mos7840_break:leaving ...........");
+                dbg("%s", "mos7840_break:leaving ...........");
                 return 0;
         }
 
@@ -1148,16 +1152,16 @@ static void mos7840_close(struct usb_serial_port *port)
         int j;
         __u16 Data;
 
-        dbg("%s\n", "mos7840_close:entering...");
+        dbg("%s", "mos7840_close:entering...");
 
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Port Paranoia failed \n");
+                dbg("%s", "Port Paranoia failed");
                 return;
         }
 
         serial = mos7840_get_usb_serial(port, __func__);
         if (!serial) {
-                dbg("%s", "Serial Paranoia failed \n");
+                dbg("%s", "Serial Paranoia failed");
                 return;
         }
 
@@ -1185,27 +1189,27 @@ static void mos7840_close(struct usb_serial_port *port)
          * and interrupt read if they exists                  */
         if (serial->dev) {
                 if (mos7840_port->write_urb) {
-                        dbg("%s", "Shutdown bulk write\n");
+                        dbg("%s", "Shutdown bulk write");
                         usb_kill_urb(mos7840_port->write_urb);
                 }
                 if (mos7840_port->read_urb) {
-                        dbg("%s", "Shutdown bulk read\n");
+                        dbg("%s", "Shutdown bulk read");
                         usb_kill_urb(mos7840_port->read_urb);
                         mos7840_port->read_urb_busy = false;
                 }
                 if ((&mos7840_port->control_urb)) {
-                        dbg("%s", "Shutdown control read\n");
+                        dbg("%s", "Shutdown control read");
                         /*/      usb_kill_urb (mos7840_port->control_urb); */
                 }
         }
 /*      if(mos7840_port->ctrl_buf != NULL) */
 /*              kfree(mos7840_port->ctrl_buf); */
         port0->open_ports--;
-        dbg("mos7840_num_open_ports in close%d:in port%d\n",
+        dbg("mos7840_num_open_ports in close%d:in port%d",
             port0->open_ports, port->number);
         if (port0->open_ports == 0) {
                 if (serial->port[0]->interrupt_in_urb) {
-                        dbg("%s", "Shutdown interrupt_in_urb\n");
+                        dbg("%s", "Shutdown interrupt_in_urb");
                         usb_kill_urb(serial->port[0]->interrupt_in_urb);
                 }
         }
@@ -1225,7 +1229,7 @@ static void mos7840_close(struct usb_serial_port *port)
 
         mos7840_port->open = 0;
 
-        dbg("%s \n", "Leaving ............");
+        dbg("%s", "Leaving ............");
 }
 
 /************************************************************************
@@ -1280,17 +1284,17 @@ static void mos7840_break(struct tty_struct *tty, int break_state)
         struct usb_serial *serial;
         struct moschip_port *mos7840_port;
 
-        dbg("%s \n", "Entering ...........");
-        dbg("mos7840_break: Start\n");
+        dbg("%s", "Entering ...........");
+        dbg("mos7840_break: Start");
 
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Port Paranoia failed \n");
+                dbg("%s", "Port Paranoia failed");
                 return;
         }
 
         serial = mos7840_get_usb_serial(port, __func__);
         if (!serial) {
-                dbg("%s", "Serial Paranoia failed \n");
+                dbg("%s", "Serial Paranoia failed");
                 return;
         }
 
@@ -1310,7 +1314,7 @@ static void mos7840_break(struct tty_struct *tty, int break_state)
 
         /* FIXME: no locking on shadowLCR anywhere in driver */
         mos7840_port->shadowLCR = data;
-        dbg("mcs7840_break mos7840_port->shadowLCR is %x\n",
+        dbg("mcs7840_break mos7840_port->shadowLCR is %x",
             mos7840_port->shadowLCR);
         mos7840_set_uart_reg(port, LINE_CONTROL_REGISTER,
                              mos7840_port->shadowLCR);
@@ -1334,17 +1338,17 @@ static int mos7840_write_room(struct tty_struct *tty)
         unsigned long flags;
         struct moschip_port *mos7840_port;
 
-        dbg("%s \n", " mos7840_write_room:entering ...........");
+        dbg("%s", " mos7840_write_room:entering ...........");
 
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Invalid port \n");
-                dbg("%s \n", " mos7840_write_room:leaving ...........");
+                dbg("%s", "Invalid port");
+                dbg("%s", " mos7840_write_room:leaving ...........");
                 return -1;
         }
 
         mos7840_port = mos7840_get_port_private(port);
         if (mos7840_port == NULL) {
-                dbg("%s \n", "mos7840_break:leaving ...........");
+                dbg("%s", "mos7840_break:leaving ...........");
                 return -1;
         }
 
@@ -1384,16 +1388,16 @@ static int mos7840_write(struct tty_struct *tty, struct usb_serial_port *port,
         /* __u16 Data; */
         const unsigned char *current_position = data;
         unsigned char *data1;
-        dbg("%s \n", "entering ...........");
-        /* dbg("mos7840_write: mos7840_port->shadowLCR is %x\n",
+        dbg("%s", "entering ...........");
+        /* dbg("mos7840_write: mos7840_port->shadowLCR is %x",
                                         mos7840_port->shadowLCR); */
 
 #ifdef NOTMOS7840
         Data = 0x00;
         status = mos7840_get_uart_reg(port, LINE_CONTROL_REGISTER, &Data);
         mos7840_port->shadowLCR = Data;
-        dbg("mos7840_write: LINE_CONTROL_REGISTER is %x\n", Data);
-        dbg("mos7840_write: mos7840_port->shadowLCR is %x\n",
+        dbg("mos7840_write: LINE_CONTROL_REGISTER is %x", Data);
+        dbg("mos7840_write: mos7840_port->shadowLCR is %x",
             mos7840_port->shadowLCR);
 
         /* Data = 0x03; */
@@ -1407,32 +1411,32 @@ static int mos7840_write(struct tty_struct *tty, struct usb_serial_port *port,
         /* status = mos7840_set_uart_reg(port,DIVISOR_LATCH_LSB,Data); */
         Data = 0x00;
         status = mos7840_get_uart_reg(port, DIVISOR_LATCH_LSB, &Data);
-        dbg("mos7840_write:DLL value is %x\n", Data);
+        dbg("mos7840_write:DLL value is %x", Data);
 
         Data = 0x0;
         status = mos7840_get_uart_reg(port, DIVISOR_LATCH_MSB, &Data);
-        dbg("mos7840_write:DLM value is %x\n", Data);
+        dbg("mos7840_write:DLM value is %x", Data);
 
         Data = Data & ~SERIAL_LCR_DLAB;
-        dbg("mos7840_write: mos7840_port->shadowLCR is %x\n",
+        dbg("mos7840_write: mos7840_port->shadowLCR is %x",
             mos7840_port->shadowLCR);
         status = mos7840_set_uart_reg(port, LINE_CONTROL_REGISTER, Data);
 #endif
 
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Port Paranoia failed \n");
+                dbg("%s", "Port Paranoia failed");
                 return -1;
         }
 
         serial = port->serial;
         if (mos7840_serial_paranoia_check(serial, __func__)) {
-                dbg("%s", "Serial Paranoia failed \n");
+                dbg("%s", "Serial Paranoia failed");
                 return -1;
         }
 
         mos7840_port = mos7840_get_port_private(port);
         if (mos7840_port == NULL) {
-                dbg("%s", "mos7840_port is NULL\n");
+                dbg("%s", "mos7840_port is NULL");
                 return -1;
         }
 
@@ -1444,7 +1448,7 @@ static int mos7840_write(struct tty_struct *tty, struct usb_serial_port *port,
                 if (!mos7840_port->busy[i]) {
                         mos7840_port->busy[i] = 1;
                         urb = mos7840_port->write_urb_pool[i];
-                        dbg("\nURB:%d", i);
+                        dbg("URB:%d", i);
                         break;
                 }
         }
@@ -1479,7 +1483,7 @@ static int mos7840_write(struct tty_struct *tty, struct usb_serial_port *port,
                           mos7840_bulk_out_data_callback, mos7840_port);
 
         data1 = urb->transfer_buffer;
-        dbg("\nbulkout endpoint is %d", port->bulk_out_endpointAddress);
+        dbg("bulkout endpoint is %d", port->bulk_out_endpointAddress);
 
         /* send it down the pipe */
         status = usb_submit_urb(urb, GFP_ATOMIC);
@@ -1494,7 +1498,7 @@ static int mos7840_write(struct tty_struct *tty, struct usb_serial_port *port,
         bytes_sent = transfer_size;
         mos7840_port->icount.tx += transfer_size;
         smp_wmb();
-        dbg("mos7840_port->icount.tx is %d:\n", mos7840_port->icount.tx);
+        dbg("mos7840_port->icount.tx is %d:", mos7840_port->icount.tx);
 exit:
         return bytes_sent;
 
@@ -1513,11 +1517,11 @@ static void mos7840_throttle(struct tty_struct *tty)
         int status;
 
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Invalid port \n");
+                dbg("%s", "Invalid port");
                 return;
         }
 
-        dbg("- port %d\n", port->number);
+        dbg("- port %d", port->number);
 
         mos7840_port = mos7840_get_port_private(port);
 
@@ -1525,11 +1529,11 @@ static void mos7840_throttle(struct tty_struct *tty)
                 return;
 
         if (!mos7840_port->open) {
-                dbg("%s\n", "port not opened");
+                dbg("%s", "port not opened");
                 return;
         }
 
-        dbg("%s", "Entering .......... \n");
+        dbg("%s", "Entering ..........");
 
         /* if we are implementing XON/XOFF, send the stop character */
         if (I_IXOFF(tty)) {
@@ -1563,7 +1567,7 @@ static void mos7840_unthrottle(struct tty_struct *tty)
         struct moschip_port *mos7840_port = mos7840_get_port_private(port);
 
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Invalid port \n");
+                dbg("%s", "Invalid port");
                 return;
         }
 
@@ -1575,7 +1579,7 @@ static void mos7840_unthrottle(struct tty_struct *tty)
                 return;
         }
 
-        dbg("%s", "Entering .......... \n");
+        dbg("%s", "Entering ..........");
 
         /* if we are implementing XON/XOFF, send the start character */
         if (I_IXOFF(tty)) {
@@ -1660,7 +1664,7 @@ static int mos7840_tiocmset(struct tty_struct *tty, struct file *file,
 
         status = mos7840_set_uart_reg(port, MODEM_CONTROL_REGISTER, mcr);
         if (status < 0) {
-                dbg("setting MODEM_CONTROL_REGISTER Failed\n");
+                dbg("setting MODEM_CONTROL_REGISTER Failed");
                 return status;
         }
 
@@ -1729,11 +1733,11 @@ static int mos7840_calc_baud_rate_divisor(int baudRate, int *divisor,
                         custom++;
                 *divisor = custom;
 
-                dbg(" Baud %d = %d\n", baudrate, custom);
+                dbg(" Baud %d = %d", baudrate, custom);
                 return 0;
         }
 
-        dbg("%s\n", " Baud calculation Failed...");
+        dbg("%s", " Baud calculation Failed...");
         return -1;
 #endif
 }
@@ -1759,16 +1763,16 @@ static int mos7840_send_cmd_write_baud_rate(struct moschip_port *mos7840_port,
 
         port = (struct usb_serial_port *)mos7840_port->port;
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Invalid port \n");
+                dbg("%s", "Invalid port");
                 return -1;
         }
 
         if (mos7840_serial_paranoia_check(port->serial, __func__)) {
-                dbg("%s", "Invalid Serial \n");
+                dbg("%s", "Invalid Serial");
                 return -1;
         }
 
-        dbg("%s", "Entering .......... \n");
+        dbg("%s", "Entering ..........");
 
         number = mos7840_port->port->number - mos7840_port->port->serial->minor;
 
@@ -1784,7 +1788,7 @@ static int mos7840_send_cmd_write_baud_rate(struct moschip_port *mos7840_port,
                 status = mos7840_set_uart_reg(port, MODEM_CONTROL_REGISTER,
                                                                         Data);
                 if (status < 0) {
-                        dbg("Writing spreg failed in set_serial_baud\n");
+                        dbg("Writing spreg failed in set_serial_baud");
                         return -1;
                 }
 #endif
@@ -1797,7 +1801,7 @@ static int mos7840_send_cmd_write_baud_rate(struct moschip_port *mos7840_port,
                 status = mos7840_set_uart_reg(port, MODEM_CONTROL_REGISTER,
                                                                         Data);
                 if (status < 0) {
-                        dbg("Writing spreg failed in set_serial_baud\n");
+                        dbg("Writing spreg failed in set_serial_baud");
                         return -1;
                 }
 #endif
@@ -1812,14 +1816,14 @@ static int mos7840_send_cmd_write_baud_rate(struct moschip_port *mos7840_port,
                 status = mos7840_get_reg_sync(port, mos7840_port->SpRegOffset,
                                                                  &Data);
                 if (status < 0) {
-                        dbg("reading spreg failed in set_serial_baud\n");
+                        dbg("reading spreg failed in set_serial_baud");
                         return -1;
                 }
                 Data = (Data & 0x8f) | clk_sel_val;
                 status = mos7840_set_reg_sync(port, mos7840_port->SpRegOffset,
                                                                 Data);
                 if (status < 0) {
-                        dbg("Writing spreg failed in set_serial_baud\n");
+                        dbg("Writing spreg failed in set_serial_baud");
                         return -1;
                 }
                 /* Calculate the Divisor */
@@ -1835,11 +1839,11 @@ static int mos7840_send_cmd_write_baud_rate(struct moschip_port *mos7840_port,
 
                 /* Write the divisor */
                 Data = (unsigned char)(divisor & 0xff);
-                dbg("set_serial_baud Value to write DLL is %x\n", Data);
+                dbg("set_serial_baud Value to write DLL is %x", Data);
                 mos7840_set_uart_reg(port, DIVISOR_LATCH_LSB, Data);
 
                 Data = (unsigned char)((divisor & 0xff00) >> 8);
-                dbg("set_serial_baud Value to write DLM is %x\n", Data);
+                dbg("set_serial_baud Value to write DLM is %x", Data);
                 mos7840_set_uart_reg(port, DIVISOR_LATCH_MSB, Data);
 
                 /* Disable access to divisor latch */
@@ -1877,12 +1881,12 @@ static void mos7840_change_port_settings(struct tty_struct *tty,
         port = (struct usb_serial_port *)mos7840_port->port;
 
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Invalid port \n");
+                dbg("%s", "Invalid port");
                 return;
         }
 
         if (mos7840_serial_paranoia_check(port->serial, __func__)) {
-                dbg("%s", "Invalid Serial \n");
+                dbg("%s", "Invalid Serial");
                 return;
         }
 
@@ -1895,7 +1899,7 @@ static void mos7840_change_port_settings(struct tty_struct *tty,
                 return;
         }
 
-        dbg("%s", "Entering .......... \n");
+        dbg("%s", "Entering ..........");
 
         lData = LCR_BITS_8;
         lStop = LCR_STOP_1;
@@ -1955,7 +1959,7 @@ static void mos7840_change_port_settings(struct tty_struct *tty,
             ~(LCR_BITS_MASK | LCR_STOP_MASK | LCR_PAR_MASK);
         mos7840_port->shadowLCR |= (lData | lParity | lStop);
 
-        dbg("mos7840_change_port_settings mos7840_port->shadowLCR is %x\n",
+        dbg("mos7840_change_port_settings mos7840_port->shadowLCR is %x",
             mos7840_port->shadowLCR);
         /* Disable Interrupts */
         Data = 0x00;
@@ -1997,7 +2001,7 @@ static void mos7840_change_port_settings(struct tty_struct *tty,
 
         if (!baud) {
                 /* pick a default, any default... */
-                dbg("%s\n", "Picked default baud...");
+                dbg("%s", "Picked default baud...");
                 baud = 9600;
         }
 
@@ -2020,7 +2024,7 @@ static void mos7840_change_port_settings(struct tty_struct *tty,
         }
         wake_up(&mos7840_port->delta_msr_wait);
         mos7840_port->delta_msr_cond = 1;
-        dbg("mos7840_change_port_settings mos7840_port->shadowLCR is End %x\n",
+        dbg("mos7840_change_port_settings mos7840_port->shadowLCR is End %x",
             mos7840_port->shadowLCR);
 
         return;
@@ -2040,16 +2044,16 @@ static void mos7840_set_termios(struct tty_struct *tty,
         unsigned int cflag;
         struct usb_serial *serial;
         struct moschip_port *mos7840_port;
-        dbg("mos7840_set_termios: START\n");
+        dbg("mos7840_set_termios: START");
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Invalid port \n");
+                dbg("%s", "Invalid port");
                 return;
         }
 
         serial = port->serial;
 
         if (mos7840_serial_paranoia_check(serial, __func__)) {
-                dbg("%s", "Invalid Serial \n");
+                dbg("%s", "Invalid Serial");
                 return;
         }
 
@@ -2063,7 +2067,7 @@ static void mos7840_set_termios(struct tty_struct *tty,
                 return;
         }
 
-        dbg("%s\n", "setting termios - ");
+        dbg("%s", "setting termios - ");
 
         cflag = tty->termios->c_cflag;
 
@@ -2078,7 +2082,7 @@ static void mos7840_set_termios(struct tty_struct *tty,
         mos7840_change_port_settings(tty, mos7840_port, old_termios);
 
         if (!mos7840_port->read_urb) {
-                dbg("%s", "URB KILLED !!!!!\n");
+                dbg("%s", "URB KILLED !!!!!");
                 return;
         }
 
@@ -2144,7 +2148,7 @@ static int mos7840_set_modem_info(struct moschip_port *mos7840_port,
 
         port = (struct usb_serial_port *)mos7840_port->port;
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Invalid port \n");
+                dbg("%s", "Invalid port");
                 return -1;
         }
 
@@ -2189,7 +2193,7 @@ static int mos7840_set_modem_info(struct moschip_port *mos7840_port,
         status = mos7840_set_uart_reg(port, MODEM_CONTROL_REGISTER, Data);
         unlock_kernel();
         if (status < 0) {
-                dbg("setting MODEM_CONTROL_REGISTER Failed\n");
+                dbg("setting MODEM_CONTROL_REGISTER Failed");
                 return -1;
         }
 
@@ -2274,7 +2278,7 @@ static int mos7840_ioctl(struct tty_struct *tty, struct file *file,
         int mosret = 0;
 
         if (mos7840_port_paranoia_check(port, __func__)) {
-                dbg("%s", "Invalid port \n");
+                dbg("%s", "Invalid port");
                 return -1;
         }
 
@@ -2374,9 +2378,8 @@ static int mos7840_calc_num_ports(struct usb_serial *serial)
 {
         int mos7840_num_ports = 0;
 
-        dbg("numberofendpoints: %d \n",
-            (int)serial->interface->cur_altsetting->desc.bNumEndpoints);
-        dbg("numberofendpoints: %d \n",
+        dbg("numberofendpoints: cur %d, alt %d",
+            (int)serial->interface->cur_altsetting->desc.bNumEndpoints,
             (int)serial->interface->altsetting->desc.bNumEndpoints);
         if (serial->interface->cur_altsetting->desc.bNumEndpoints == 5) {
                 mos7840_num_ports = serial->num_ports = 2;
@@ -2385,7 +2388,7 @@ static int mos7840_calc_num_ports(struct usb_serial *serial)
                 serial->num_bulk_out = 4;
                 mos7840_num_ports = serial->num_ports = 4;
         }
-
+        dbg ("mos7840_num_ports = %d", mos7840_num_ports);
         return mos7840_num_ports;
 }
 
@@ -2400,22 +2403,24 @@ static int mos7840_startup(struct usb_serial *serial)
         int i, status;
 
         __u16 Data;
-        dbg("%s \n", " mos7840_startup :entering..........");
+        dbg("%s", "mos7840_startup :Entering..........");
 
         if (!serial) {
-                dbg("%s\n", "Invalid Handler");
+                dbg("%s", "Invalid Handler");
                 return -1;
         }
 
         dev = serial->dev;
 
-        dbg("%s\n", "Entering...");
+        dbg("%s", "Entering...");
+        dbg ("mos7840_startup: serial = %p", serial);
 
         /* we set up the pointers to the endpoints in the mos7840_open *
          * function, as the structures aren't created yet.             */
 
         /* set up port private structures */
         for (i = 0; i < serial->num_ports; ++i) {
+                dbg ("mos7840_startup: configuring port %d............", i);
                 mos7840_port = kzalloc(sizeof(struct moschip_port), GFP_KERNEL);
                 if (mos7840_port == NULL) {
                         dev_err(&dev->dev, "%s - Out of memory\n", __func__);
@@ -2473,10 +2478,10 @@ static int mos7840_startup(struct usb_serial *serial)
                 status = mos7840_get_reg_sync(serial->port[i],
                                  mos7840_port->ControlRegOffset, &Data);
                 if (status < 0) {
-                        dbg("Reading ControlReg failed status-0x%x\n", status);
+                        dbg("Reading ControlReg failed status-0x%x", status);
                         break;
                 } else
-                        dbg("ControlReg Reading success val is %x, status%d\n",
+                        dbg("ControlReg Reading success val is %x, status%d",
                             Data, status);
                 Data |= 0x08;   /* setting driver done bit */
                 Data |= 0x04;   /* sp1_bit to have cts change reflect in
@@ -2486,10 +2491,10 @@ static int mos7840_startup(struct usb_serial *serial)
                 status = mos7840_set_reg_sync(serial->port[i],
                                          mos7840_port->ControlRegOffset, Data);
                 if (status < 0) {
-                        dbg("Writing ControlReg failed(rx_disable) status-0x%x\n", status);
+                        dbg("Writing ControlReg failed(rx_disable) status-0x%x", status);
                         break;
                 } else
-                        dbg("ControlReg Writing success(rx_disable) status%d\n",
+                        dbg("ControlReg Writing success(rx_disable) status%d",
                             status);
 
                 /* Write default values in DCR (i.e 0x01 in DCR0, 0x05 in DCR2
@@ -2498,48 +2503,48 @@ static int mos7840_startup(struct usb_serial *serial)
                 status = mos7840_set_reg_sync(serial->port[i],
                          (__u16) (mos7840_port->DcrRegOffset + 0), Data);
                 if (status < 0) {
-                        dbg("Writing DCR0 failed status-0x%x\n", status);
+                        dbg("Writing DCR0 failed status-0x%x", status);
                         break;
                 } else
-                        dbg("DCR0 Writing success status%d\n", status);
+                        dbg("DCR0 Writing success status%d", status);
 
                 Data = 0x05;
                 status = mos7840_set_reg_sync(serial->port[i],
                          (__u16) (mos7840_port->DcrRegOffset + 1), Data);
                 if (status < 0) {
-                        dbg("Writing DCR1 failed status-0x%x\n", status);
+                        dbg("Writing DCR1 failed status-0x%x", status);
                         break;
                 } else
-                        dbg("DCR1 Writing success status%d\n", status);
+                        dbg("DCR1 Writing success status%d", status);
 
                 Data = 0x24;
                 status = mos7840_set_reg_sync(serial->port[i],
                          (__u16) (mos7840_port->DcrRegOffset + 2), Data);
                 if (status < 0) {
-                        dbg("Writing DCR2 failed status-0x%x\n", status);
+                        dbg("Writing DCR2 failed status-0x%x", status);
                         break;
                 } else
-                        dbg("DCR2 Writing success status%d\n", status);
+                        dbg("DCR2 Writing success status%d", status);
 
                 /* write values in clkstart0x0 and clkmulti 0x20 */
                 Data = 0x0;
                 status = mos7840_set_reg_sync(serial->port[i],
                                          CLK_START_VALUE_REGISTER, Data);
                 if (status < 0) {
-                        dbg("Writing CLK_START_VALUE_REGISTER failed status-0x%x\n", status);
+                        dbg("Writing CLK_START_VALUE_REGISTER failed status-0x%x", status);
                         break;
                 } else
-                        dbg("CLK_START_VALUE_REGISTER Writing success status%d\n", status);
+                        dbg("CLK_START_VALUE_REGISTER Writing success status%d", status);
 
                 Data = 0x20;
                 status = mos7840_set_reg_sync(serial->port[i],
                                         CLK_MULTI_REGISTER, Data);
                 if (status < 0) {
-                        dbg("Writing CLK_MULTI_REGISTER failed status-0x%x\n",
+                        dbg("Writing CLK_MULTI_REGISTER failed status-0x%x",
                             status);
                         goto error;
                 } else
-                        dbg("CLK_MULTI_REGISTER Writing success status%d\n",
+                        dbg("CLK_MULTI_REGISTER Writing success status%d",
                             status);
 
                 /* write value 0x0 to scratchpad register */
@@ -2547,11 +2552,11 @@ static int mos7840_startup(struct usb_serial *serial)
                 status = mos7840_set_uart_reg(serial->port[i],
                                                 SCRATCH_PAD_REGISTER, Data);
                 if (status < 0) {
-                        dbg("Writing SCRATCH_PAD_REGISTER failed status-0x%x\n",
+                        dbg("Writing SCRATCH_PAD_REGISTER failed status-0x%x",
                             status);
                         break;
                 } else
-                        dbg("SCRATCH_PAD_REGISTER Writing success status%d\n",
+                        dbg("SCRATCH_PAD_REGISTER Writing success status%d",
                             status);
 
                 /* Zero Length flag register */
@@ -2562,30 +2567,30 @@ static int mos7840_startup(struct usb_serial *serial)
                         status = mos7840_set_reg_sync(serial->port[i],
                                       (__u16) (ZLP_REG1 +
                                       ((__u16)mos7840_port->port_num)), Data);
-                        dbg("ZLIP offset%x\n",
+                        dbg("ZLIP offset %x",
                             (__u16) (ZLP_REG1 +
                                         ((__u16) mos7840_port->port_num)));
                         if (status < 0) {
-                                dbg("Writing ZLP_REG%d failed status-0x%x\n",
+                                dbg("Writing ZLP_REG%d failed status-0x%x",
                                     i + 2, status);
                                 break;
                         } else
-                                dbg("ZLP_REG%d Writing success status%d\n",
+                                dbg("ZLP_REG%d Writing success status%d",
                                     i + 2, status);
                 } else {
                         Data = 0xff;
                         status = mos7840_set_reg_sync(serial->port[i],
                               (__u16) (ZLP_REG1 +
                               ((__u16)mos7840_port->port_num) - 0x1), Data);
-                        dbg("ZLIP offset%x\n",
+                        dbg("ZLIP offset %x",
                             (__u16) (ZLP_REG1 +
                                      ((__u16) mos7840_port->port_num) - 0x1));
                         if (status < 0) {
-                                dbg("Writing ZLP_REG%d failed status-0x%x\n",
+                                dbg("Writing ZLP_REG%d failed status-0x%x",
                                     i + 1, status);
                                 break;
                         } else
-                                dbg("ZLP_REG%d Writing success status%d\n",
+                                dbg("ZLP_REG%d Writing success status%d",
                                     i + 1, status);
 
                 }
@@ -2599,15 +2604,16 @@ static int mos7840_startup(struct usb_serial *serial)
                         goto error;
                 }
         }
+        dbg ("mos7840_startup: all ports configured...........");
 
         /* Zero Length flag enable */
         Data = 0x0f;
         status = mos7840_set_reg_sync(serial->port[0], ZLP_REG5, Data);
         if (status < 0) {
-                dbg("Writing ZLP_REG5 failed status-0x%x\n", status);
+                dbg("Writing ZLP_REG5 failed status-0x%x", status);
                 goto error;
         } else
-                dbg("ZLP_REG5 Writing success status%d\n", status);
+                dbg("ZLP_REG5 Writing success status%d", status);
 
         /* setting configuration feature to one */
         usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0),
@@ -2627,19 +2633,19 @@ error:
 }
 
 /****************************************************************************
- * mos7840_shutdown
+ * mos7840_disconnect
  *      This function is called whenever the device is removed from the usb bus.
  ****************************************************************************/
 
-static void mos7840_shutdown(struct usb_serial *serial)
+static void mos7840_disconnect(struct usb_serial *serial)
 {
         int i;
         unsigned long flags;
         struct moschip_port *mos7840_port;
-        dbg("%s \n", " shutdown :entering..........");
+        dbg("%s", " disconnect :entering..........");
 
         if (!serial) {
-                dbg("%s", "Invalid Handler \n");
+                dbg("%s", "Invalid Handler");
                 return;
         }
 
@@ -2656,14 +2662,45 @@ static void mos7840_shutdown(struct usb_serial *serial)
                         mos7840_port->zombie = 1;
                         spin_unlock_irqrestore(&mos7840_port->pool_lock, flags);
                         usb_kill_urb(mos7840_port->control_urb);
+                }
+        }
+
+        dbg("%s", "Thank u :: ");
+
+}
+
+/****************************************************************************
+ * mos7840_release
+ *      This function is called when the usb_serial structure is freed.
+ ****************************************************************************/
+
+static void mos7840_release(struct usb_serial *serial)
+{
+        int i;
+        struct moschip_port *mos7840_port;
+        dbg("%s", " release :entering..........");
+
+        if (!serial) {
+                dbg("%s", "Invalid Handler");
+                return;
+        }
+
+        /* check for the ports to be closed,close the ports and disconnect */
+
+        /* free private structure allocated for serial port  *
+         * stop reads and writes on all ports                */
+
+        for (i = 0; i < serial->num_ports; ++i) {
+                mos7840_port = mos7840_get_port_private(serial->port[i]);
+                dbg("mos7840_port %d = %p", i, mos7840_port);
+                if (mos7840_port) {
                         kfree(mos7840_port->ctrl_buf);
                         kfree(mos7840_port->dr);
                         kfree(mos7840_port);
                 }
-                mos7840_set_port_private(serial->port[i], NULL);
         }
 
-        dbg("%s\n", "Thank u :: ");
+        dbg("%s", "Thank u :: ");
 
 }
 
@@ -2701,7 +2738,8 @@ static struct usb_serial_driver moschip7840_4port_device = {
         .tiocmget = mos7840_tiocmget,
         .tiocmset = mos7840_tiocmset,
         .attach = mos7840_startup,
-        .shutdown = mos7840_shutdown,
+        .disconnect = mos7840_disconnect,
+        .release = mos7840_release,
         .read_bulk_callback = mos7840_bulk_in_callback,
         .read_int_callback = mos7840_interrupt_callback,
 };
@@ -2714,7 +2752,7 @@ static int __init moschip7840_init(void)
 {
         int retval;
 
-        dbg("%s \n", " mos7840_init :entering..........");
+        dbg("%s", " mos7840_init :entering..........");
 
         /* Register with the usb serial */
         retval = usb_serial_register(&moschip7840_4port_device);
@@ -2722,14 +2760,14 @@ static int __init moschip7840_init(void)
         if (retval)
                 goto failed_port_device_register;
 
-        dbg("%s\n", "Entring...");
+        dbg("%s", "Entering...");
         printk(KERN_INFO KBUILD_MODNAME ": " DRIVER_VERSION ":"
                DRIVER_DESC "\n");
 
         /* Register with the usb */
         retval = usb_register(&io_driver);
         if (retval == 0) {
-                dbg("%s\n", "Leaving...");
+                dbg("%s", "Leaving...");
                 return 0;
         }
         usb_serial_deregister(&moschip7840_4port_device);
@@ -2744,13 +2782,13 @@ failed_port_device_register:
 static void __exit moschip7840_exit(void)
 {
 
-        dbg("%s \n", " mos7840_exit :entering..........");
+        dbg("%s", " mos7840_exit :entering..........");
 
         usb_deregister(&io_driver);
 
         usb_serial_deregister(&moschip7840_4port_device);
 
-        dbg("%s\n", "Entring...");
+        dbg("%s", "Entering...");
 }
 
 module_init(moschip7840_init);
diff --git a/drivers/usb/serial/omninet.c b/drivers/usb/serial/omninet.c
index 1104617334f5..56857ddbd70b 100644
--- a/drivers/usb/serial/omninet.c
+++ b/drivers/usb/serial/omninet.c
@@ -72,7 +72,8 @@ static void omninet_write_bulk_callback(struct urb *urb);
 static int  omninet_write(struct tty_struct *tty, struct usb_serial_port *port,
                                 const unsigned char *buf, int count);
 static int  omninet_write_room(struct tty_struct *tty);
-static void omninet_shutdown(struct usb_serial *serial);
+static void omninet_disconnect(struct usb_serial *serial);
+static void omninet_release(struct usb_serial *serial);
 static int omninet_attach(struct usb_serial *serial);
 
 static struct usb_device_id id_table[] = {
@@ -108,7 +109,8 @@ static struct usb_serial_driver zyxel_omninet_device = {
         .write_room =           omninet_write_room,
         .read_bulk_callback =   omninet_read_bulk_callback,
         .write_bulk_callback =  omninet_write_bulk_callback,
-        .shutdown =             omninet_shutdown,
+        .disconnect =           omninet_disconnect,
+        .release =              omninet_release,
 };
 
 
@@ -345,13 +347,22 @@ static void omninet_write_bulk_callback(struct urb *urb)
 }
 
 
-static void omninet_shutdown(struct usb_serial *serial)
+static void omninet_disconnect(struct usb_serial *serial)
 {
         struct usb_serial_port *wport = serial->port[1];
-        struct usb_serial_port *port = serial->port[0];
+
         dbg("%s", __func__);
 
         usb_kill_urb(wport->write_urb);
+}
+
+
+static void omninet_release(struct usb_serial *serial)
+{
+        struct usb_serial_port *port = serial->port[0];
+
+        dbg("%s", __func__);
+
         kfree(usb_get_serial_port_data(port));
 }
 
diff --git a/drivers/usb/serial/opticon.c b/drivers/usb/serial/opticon.c
index c20480aa9755..336bba79ad32 100644
--- a/drivers/usb/serial/opticon.c
+++ b/drivers/usb/serial/opticon.c
@@ -463,7 +463,7 @@ error:
         return retval;
 }
 
-static void opticon_shutdown(struct usb_serial *serial)
+static void opticon_disconnect(struct usb_serial *serial)
 {
         struct opticon_private *priv = usb_get_serial_data(serial);
 
@@ -471,9 +471,16 @@ static void opticon_shutdown(struct usb_serial *serial)
 
         usb_kill_urb(priv->bulk_read_urb);
         usb_free_urb(priv->bulk_read_urb);
+}
+
+static void opticon_release(struct usb_serial *serial)
+{
+        struct opticon_private *priv = usb_get_serial_data(serial);
+
+        dbg("%s", __func__);
+
         kfree(priv->bulk_in_buffer);
         kfree(priv);
-        usb_set_serial_data(serial, NULL);
 }
 
 static int opticon_suspend(struct usb_interface *intf, pm_message_t message)
@@ -524,7 +531,8 @@ static struct usb_serial_driver opticon_device = {
         .close =                opticon_close,
         .write =                opticon_write,
         .write_room =           opticon_write_room,
-        .shutdown =             opticon_shutdown,
+        .disconnect =           opticon_disconnect,
+        .release =              opticon_release,
         .throttle =             opticon_throttle,
         .unthrottle =           opticon_unthrottle,
         .ioctl =                opticon_ioctl,
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index a16d69fadba1..575816e6ba37 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -43,13 +43,16 @@
 #include <linux/usb/serial.h>
 
 /* Function prototypes */
+static int  option_probe(struct usb_serial *serial,
+                        const struct usb_device_id *id);
 static int  option_open(struct tty_struct *tty, struct usb_serial_port *port,
                                                         struct file *filp);
 static void option_close(struct usb_serial_port *port);
 static void option_dtr_rts(struct usb_serial_port *port, int on);
 
 static int  option_startup(struct usb_serial *serial);
-static void option_shutdown(struct usb_serial *serial);
+static void option_disconnect(struct usb_serial *serial);
+static void option_release(struct usb_serial *serial);
 static int  option_write_room(struct tty_struct *tty);
 
 static void option_instat_callback(struct urb *urb);
@@ -202,9 +205,9 @@ static int  option_resume(struct usb_serial *serial);
 #define NOVATELWIRELESS_PRODUCT_MC727           0x4100
 #define NOVATELWIRELESS_PRODUCT_MC950D          0x4400
 #define NOVATELWIRELESS_PRODUCT_U727            0x5010
+#define NOVATELWIRELESS_PRODUCT_MC760           0x6000
 
 /* FUTURE NOVATEL PRODUCTS */
-#define NOVATELWIRELESS_PRODUCT_EVDO_FULLSPEED  0X6000
 #define NOVATELWIRELESS_PRODUCT_EVDO_HIGHSPEED  0X6001
 #define NOVATELWIRELESS_PRODUCT_HSPA_FULLSPEED  0X7000
 #define NOVATELWIRELESS_PRODUCT_HSPA_HIGHSPEED  0X7001
@@ -305,6 +308,10 @@ static int  option_resume(struct usb_serial *serial);
 #define DLINK_PRODUCT_DWM_652                   0x3e04
 
 
+/* TOSHIBA PRODUCTS */
+#define TOSHIBA_VENDOR_ID                       0x0930
+#define TOSHIBA_PRODUCT_HSDPA_MINICARD          0x1302
+
 static struct usb_device_id option_ids[] = {
         { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) },
         { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA) },
@@ -422,7 +429,7 @@ static struct usb_device_id option_ids[] = {
         { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_MC950D) }, /* Novatel MC930D/MC950D */
         { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_MC727) }, /* Novatel MC727/U727/USB727 */
         { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_U727) }, /* Novatel MC727/U727/USB727 */
-        { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EVDO_FULLSPEED) }, /* Novatel EVDO product */
+        { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_MC760) }, /* Novatel MC760/U760/USB760 */
         { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_HSPA_FULLSPEED) }, /* Novatel HSPA product */
         { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EVDO_EMBEDDED_FULLSPEED) }, /* Novatel EVDO Embedded product */
         { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_HSPA_EMBEDDED_FULLSPEED) }, /* Novatel HSPA Embedded product */
@@ -523,6 +530,7 @@ static struct usb_device_id option_ids[] = {
         { USB_DEVICE(BENQ_VENDOR_ID, BENQ_PRODUCT_H10) },
         { USB_DEVICE(DLINK_VENDOR_ID, DLINK_PRODUCT_DWM_652) },
         { USB_DEVICE(0x1da5, 0x4515) }, /* BenQ H20 */
+        { USB_DEVICE(TOSHIBA_VENDOR_ID, TOSHIBA_PRODUCT_HSDPA_MINICARD ) }, /* Toshiba 3G HSDPA == Novatel Expedite EU870D MiniCard */
         { } /* Terminating entry */
 };
 MODULE_DEVICE_TABLE(usb, option_ids);
@@ -550,6 +558,7 @@ static struct usb_serial_driver option_1port_device = {
         .usb_driver        = &option_driver,
         .id_table          = option_ids,
         .num_ports         = 1,
+        .probe             = option_probe,
         .open              = option_open,
         .close             = option_close,
         .dtr_rts           = option_dtr_rts,
@@ -560,7 +569,8 @@ static struct usb_serial_driver option_1port_device = {
         .tiocmget          = option_tiocmget,
         .tiocmset          = option_tiocmset,
         .attach            = option_startup,
-        .shutdown          = option_shutdown,
+        .disconnect        = option_disconnect,
+        .release           = option_release,
         .read_int_callback = option_instat_callback,
         .suspend           = option_suspend,
         .resume            = option_resume,
@@ -626,6 +636,18 @@ static void __exit option_exit(void)
 module_init(option_init);
 module_exit(option_exit);
 
+static int option_probe(struct usb_serial *serial,
+                        const struct usb_device_id *id)
+{
+        /* D-Link DWM 652 still exposes CD-Rom emulation interface in modem mode */
+        if (serial->dev->descriptor.idVendor == DLINK_VENDOR_ID &&
+                serial->dev->descriptor.idProduct == DLINK_PRODUCT_DWM_652 &&
+                serial->interface->cur_altsetting->desc.bInterfaceClass == 0x8)
+                return -ENODEV;
+
+        return 0;
+}
+
 static void option_set_termios(struct tty_struct *tty,
                 struct usb_serial_port *port, struct ktermios *old_termios)
 {
@@ -1129,7 +1151,14 @@ static void stop_read_write_urbs(struct usb_serial *serial)
         }
 }
 
-static void option_shutdown(struct usb_serial *serial)
+static void option_disconnect(struct usb_serial *serial)
+{
+        dbg("%s", __func__);
+
+        stop_read_write_urbs(serial);
+}
+
+static void option_release(struct usb_serial *serial)
 {
         int i, j;
         struct usb_serial_port *port;
@@ -1137,8 +1166,6 @@ static void option_shutdown(struct usb_serial *serial)
 
         dbg("%s", __func__);
 
-        stop_read_write_urbs(serial);
-
         /* Now free them */
         for (i = 0; i < serial->num_ports; ++i) {
                 port = serial->port[i];
diff --git a/drivers/usb/serial/oti6858.c b/drivers/usb/serial/oti6858.c
index 7de54781fe61..3cece27325e7 100644
--- a/drivers/usb/serial/oti6858.c
+++ b/drivers/usb/serial/oti6858.c
@@ -159,7 +159,7 @@ static int oti6858_tiocmget(struct tty_struct *tty, struct file *file);
 static int oti6858_tiocmset(struct tty_struct *tty, struct file *file,
                                 unsigned int set, unsigned int clear);
 static int oti6858_startup(struct usb_serial *serial);
-static void oti6858_shutdown(struct usb_serial *serial);
+static void oti6858_release(struct usb_serial *serial);
 
 /* functions operating on buffers */
 static struct oti6858_buf *oti6858_buf_alloc(unsigned int size);
@@ -194,7 +194,7 @@ static struct usb_serial_driver oti6858_device = {
         .write_room =           oti6858_write_room,
         .chars_in_buffer =      oti6858_chars_in_buffer,
         .attach =               oti6858_startup,
-        .shutdown =             oti6858_shutdown,
+        .release =              oti6858_release,
 };
 
 struct oti6858_private {
@@ -782,7 +782,7 @@ static int oti6858_ioctl(struct tty_struct *tty, struct file *file,
 }
 
 
-static void oti6858_shutdown(struct usb_serial *serial)
+static void oti6858_release(struct usb_serial *serial)
 {
         struct oti6858_private *priv;
         int i;
@@ -794,7 +794,6 @@ static void oti6858_shutdown(struct usb_serial *serial)
                 if (priv) {
                         oti6858_buf_free(priv->buf);
                         kfree(priv);
-                        usb_set_serial_port_data(serial->port[i], NULL);
                 }
         }
 }
diff --git a/drivers/usb/serial/pl2303.c b/drivers/usb/serial/pl2303.c
index e02dc3d643c7..ec6c132a25b5 100644
--- a/drivers/usb/serial/pl2303.c
+++ b/drivers/usb/serial/pl2303.c
@@ -878,7 +878,7 @@ static void pl2303_break_ctl(struct tty_struct *tty, int break_state)
                 dbg("%s - error sending break = %d", __func__, result);
 }
 
-static void pl2303_shutdown(struct usb_serial *serial)
+static void pl2303_release(struct usb_serial *serial)
 {
         int i;
         struct pl2303_private *priv;
@@ -890,7 +890,6 @@ static void pl2303_shutdown(struct usb_serial *serial)
                 if (priv) {
                         pl2303_buf_free(priv->buf);
                         kfree(priv);
-                        usb_set_serial_port_data(serial->port[i], NULL);
                 }
         }
 }
@@ -927,6 +926,8 @@ static void pl2303_update_line_status(struct usb_serial_port *port,
         spin_lock_irqsave(&priv->lock, flags);
         priv->line_status = data[status_idx];
         spin_unlock_irqrestore(&priv->lock, flags);
+        if (priv->line_status & UART_BREAK_ERROR)
+                usb_serial_handle_break(port);
         wake_up_interruptible(&priv->delta_msr_wait);
 }
 
@@ -1037,7 +1038,8 @@ static void pl2303_read_bulk_callback(struct urb *urb)
                 if (line_status & UART_OVERRUN_ERROR)
                         tty_insert_flip_char(tty, 0, TTY_OVERRUN);
                 for (i = 0; i < urb->actual_length; ++i)
-                        tty_insert_flip_char(tty, data[i], tty_flag);
+                        if (!usb_serial_handle_sysrq_char(port, data[i]))
+                                tty_insert_flip_char(tty, data[i], tty_flag);
                 tty_flip_buffer_push(tty);
         }
         tty_kref_put(tty);
@@ -1120,7 +1122,7 @@ static struct usb_serial_driver pl2303_device = {
         .write_room =           pl2303_write_room,
         .chars_in_buffer =      pl2303_chars_in_buffer,
         .attach =               pl2303_startup,
-        .shutdown =             pl2303_shutdown,
+        .release =              pl2303_release,
 };
 
 static int __init pl2303_init(void)
diff --git a/drivers/usb/serial/sierra.c b/drivers/usb/serial/sierra.c
index 17ac34f4d668..032f7aeb40a4 100644
--- a/drivers/usb/serial/sierra.c
+++ b/drivers/usb/serial/sierra.c
@@ -1,7 +1,10 @@
 /*
   USB Driver for Sierra Wireless
 
-  Copyright (C) 2006, 2007, 2008  Kevin Lloyd <klloyd@sierrawireless.com>
+  Copyright (C) 2006, 2007, 2008  Kevin Lloyd <klloyd@sierrawireless.com>,
+
+  Copyright (C) 2008, 2009  Elina Pasheva, Matthew Safar, Rory Filer
+                        <linux@sierrawireless.com>
 
   IMPORTANT DISCLAIMER: This driver is not commercially supported by
   Sierra Wireless. Use at your own risk.
@@ -14,8 +17,8 @@
   Whom based his on the Keyspan driver by Hugh Blemings <hugh@blemings.org>
 */
 
-#define DRIVER_VERSION "v.1.3.3"
-#define DRIVER_AUTHOR "Kevin Lloyd <klloyd@sierrawireless.com>"
+#define DRIVER_VERSION "v.1.3.7"
+#define DRIVER_AUTHOR "Kevin Lloyd, Elina Pasheva, Matthew Safar, Rory Filer"
 #define DRIVER_DESC "USB Driver for Sierra Wireless USB modems"
 
 #include <linux/kernel.h>
@@ -30,10 +33,15 @@
 #define SWIMS_USB_REQUEST_SetPower      0x00
 #define SWIMS_USB_REQUEST_SetNmea       0x07
 
-#define N_IN_URB        4
-#define N_OUT_URB       4
+#define N_IN_URB        8
+#define N_OUT_URB       64
 #define IN_BUFLEN       4096
 
+#define MAX_TRANSFER            (PAGE_SIZE - 512)
+/* MAX_TRANSFER is chosen so that the VM is not stressed by
+   allocations > PAGE_SIZE and the number of packets in a page
+   is an integer 512 is the largest possible packet on EHCI */
+
 static int debug;
 static int nmea;
 
@@ -46,7 +54,7 @@ struct sierra_iface_info {
 static int sierra_set_power_state(struct usb_device *udev, __u16 swiState)
 {
         int result;
-        dev_dbg(&udev->dev, "%s", __func__);
+        dev_dbg(&udev->dev, "%s\n", __func__);
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                         SWIMS_USB_REQUEST_SetPower,     /* __u8 request      */
                         USB_TYPE_VENDOR,                /* __u8 request type */
@@ -61,7 +69,7 @@ static int sierra_set_power_state(struct usb_device *udev, __u16 swiState)
 static int sierra_vsc_set_nmea(struct usb_device *udev, __u16 enable)
 {
         int result;
-        dev_dbg(&udev->dev, "%s", __func__);
+        dev_dbg(&udev->dev, "%s\n", __func__);
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                         SWIMS_USB_REQUEST_SetNmea,      /* __u8 request      */
                         USB_TYPE_VENDOR,                /* __u8 request type */
@@ -75,18 +83,22 @@ static int sierra_vsc_set_nmea(struct usb_device *udev, __u16 enable)
 
 static int sierra_calc_num_ports(struct usb_serial *serial)
 {
-        int result;
-        int *num_ports = usb_get_serial_data(serial);
-        dev_dbg(&serial->dev->dev, "%s", __func__);
+        int num_ports = 0;
+        u8 ifnum, numendpoints;
 
-        result = *num_ports;
+        dev_dbg(&serial->dev->dev, "%s\n", __func__);
 
-        if (result) {
-                kfree(num_ports);
-                usb_set_serial_data(serial, NULL);
-        }
+        ifnum = serial->interface->cur_altsetting->desc.bInterfaceNumber;
+        numendpoints = serial->interface->cur_altsetting->desc.bNumEndpoints;
 
-        return result;
+        /* Dummy interface present on some SKUs should be ignored */
+        if (ifnum == 0x99)
+                num_ports = 0;
+        else if (numendpoints <= 3)
+                num_ports = 1;
+        else
+                num_ports = (numendpoints-1)/2;
+        return num_ports;
 }
 
 static int is_blacklisted(const u8 ifnum,
@@ -111,7 +123,7 @@ static int sierra_calc_interface(struct usb_serial *serial)
         int interface;
         struct usb_interface *p_interface;
         struct usb_host_interface *p_host_interface;
-        dev_dbg(&serial->dev->dev, "%s", __func__);
+        dev_dbg(&serial->dev->dev, "%s\n", __func__);
 
         /* Get the interface structure pointer from the serial struct */
         p_interface = serial->interface;
@@ -132,23 +144,12 @@ static int sierra_probe(struct usb_serial *serial,
 {
         int result = 0;
         struct usb_device *udev;
-        int *num_ports;
         u8 ifnum;
-        u8 numendpoints;
 
-        dev_dbg(&serial->dev->dev, "%s", __func__);
-
-        num_ports = kmalloc(sizeof(*num_ports), GFP_KERNEL);
-        if (!num_ports)
-                return -ENOMEM;
-
-        ifnum = serial->interface->cur_altsetting->desc.bInterfaceNumber;
-        numendpoints = serial->interface->cur_altsetting->desc.bNumEndpoints;
         udev = serial->dev;
+        dev_dbg(&udev->dev, "%s\n", __func__);
 
-        /* Figure out the interface number from the serial structure */
         ifnum = sierra_calc_interface(serial);
-
         /*
          * If this interface supports more than 1 alternate
          * select the 2nd one
@@ -160,20 +161,6 @@ static int sierra_probe(struct usb_serial *serial,
                 usb_set_interface(udev, ifnum, 1);
         }
 
-        /* Dummy interface present on some SKUs should be ignored */
-        if (ifnum == 0x99)
-                *num_ports = 0;
-        else if (numendpoints <= 3)
-                *num_ports = 1;
-        else
-                *num_ports = (numendpoints-1)/2;
-
-        /*
-         * save off our num_ports info so that we can use it in the
-         * calc_num_ports callback
-         */
-        usb_set_serial_data(serial, (void *)num_ports);
-
         /* ifnum could have changed - by calling usb_set_interface */
         ifnum = sierra_calc_interface(serial);
 
@@ -289,7 +276,7 @@ static int sierra_send_setup(struct usb_serial_port *port)
         __u16 interface = 0;
         int val = 0;
 
-        dev_dbg(&port->dev, "%s", __func__);
+        dev_dbg(&port->dev, "%s\n", __func__);
 
         portdata = usb_get_serial_port_data(port);
 
@@ -332,7 +319,7 @@ static int sierra_send_setup(struct usb_serial_port *port)
 static void sierra_set_termios(struct tty_struct *tty,
                 struct usb_serial_port *port, struct ktermios *old_termios)
 {
-        dev_dbg(&port->dev, "%s", __func__);
+        dev_dbg(&port->dev, "%s\n", __func__);
         tty_termios_copy_hw(tty->termios, old_termios);
         sierra_send_setup(port);
 }
@@ -343,7 +330,7 @@ static int sierra_tiocmget(struct tty_struct *tty, struct file *file)
         unsigned int value;
         struct sierra_port_private *portdata;
 
-        dev_dbg(&port->dev, "%s", __func__);
+        dev_dbg(&port->dev, "%s\n", __func__);
         portdata = usb_get_serial_port_data(port);
 
         value = ((portdata->rts_state) ? TIOCM_RTS : 0) |
@@ -394,14 +381,14 @@ static void sierra_outdat_callback(struct urb *urb)
         int status = urb->status;
         unsigned long flags;
 
-        dev_dbg(&port->dev, "%s - port %d", __func__, port->number);
+        dev_dbg(&port->dev, "%s - port %d\n", __func__, port->number);
 
         /* free up the transfer buffer, as usb_free_urb() does not do this */
         kfree(urb->transfer_buffer);
 
         if (status)
                 dev_dbg(&port->dev, "%s - nonzero write bulk status "
-                    "received: %d", __func__, status);
+                    "received: %d\n", __func__, status);
 
         spin_lock_irqsave(&portdata->lock, flags);
         --portdata->outstanding_urbs;
@@ -419,50 +406,61 @@ static int sierra_write(struct tty_struct *tty, struct usb_serial_port *port,
         unsigned long flags;
         unsigned char *buffer;
         struct urb *urb;
-        int status;
+        size_t writesize = min((size_t)count, (size_t)MAX_TRANSFER);
+        int retval = 0;
+
+        /* verify that we actually have some data to write */
+        if (count == 0)
+                return 0;
 
         portdata = usb_get_serial_port_data(port);
 
-        dev_dbg(&port->dev, "%s: write (%d chars)", __func__, count);
+        dev_dbg(&port->dev, "%s: write (%zd bytes)\n", __func__, writesize);
 
         spin_lock_irqsave(&portdata->lock, flags);
+        dev_dbg(&port->dev, "%s - outstanding_urbs: %d\n", __func__,
+                portdata->outstanding_urbs);
         if (portdata->outstanding_urbs > N_OUT_URB) {
                 spin_unlock_irqrestore(&portdata->lock, flags);
                 dev_dbg(&port->dev, "%s - write limit hit\n", __func__);
                 return 0;
         }
         portdata->outstanding_urbs++;
+        dev_dbg(&port->dev, "%s - 1, outstanding_urbs: %d\n", __func__,
+                portdata->outstanding_urbs);
         spin_unlock_irqrestore(&portdata->lock, flags);
 
-        buffer = kmalloc(count, GFP_ATOMIC);
+        buffer = kmalloc(writesize, GFP_ATOMIC);
         if (!buffer) {
                 dev_err(&port->dev, "out of memory\n");
-                count = -ENOMEM;
+                retval = -ENOMEM;
                 goto error_no_buffer;
         }
 
         urb = usb_alloc_urb(0, GFP_ATOMIC);
         if (!urb) {
                 dev_err(&port->dev, "no more free urbs\n");
-                count = -ENOMEM;
+                retval = -ENOMEM;
                 goto error_no_urb;
         }
 
-        memcpy(buffer, buf, count);
+        memcpy(buffer, buf, writesize);
 
-        usb_serial_debug_data(debug, &port->dev, __func__, count, buffer);
+        usb_serial_debug_data(debug, &port->dev, __func__, writesize, buffer);
 
         usb_fill_bulk_urb(urb, serial->dev,
                           usb_sndbulkpipe(serial->dev,
                                           port->bulk_out_endpointAddress),
-                          buffer, count, sierra_outdat_callback, port);
+                          buffer, writesize, sierra_outdat_callback, port);
+
+        /* Handle the need to send a zero length packet */
+        urb->transfer_flags |= URB_ZERO_PACKET;
 
         /* send it down the pipe */
-        status = usb_submit_urb(urb, GFP_ATOMIC);
-        if (status) {
+        retval = usb_submit_urb(urb, GFP_ATOMIC);
+        if (retval) {
                 dev_err(&port->dev, "%s - usb_submit_urb(write bulk) failed "
-                        "with status = %d\n", __func__, status);
-                count = status;
+                        "with status = %d\n", __func__, retval);
                 goto error;
         }
 
@@ -470,7 +468,7 @@ static int sierra_write(struct tty_struct *tty, struct usb_serial_port *port,
          * really free it when it is finished with it */
         usb_free_urb(urb);
 
-        return count;
+        return writesize;
 error:
         usb_free_urb(urb);
 error_no_urb:
@@ -478,8 +476,10 @@ error_no_urb:
 error_no_buffer:
         spin_lock_irqsave(&portdata->lock, flags);
         --portdata->outstanding_urbs;
+        dev_dbg(&port->dev, "%s - 2. outstanding_urbs: %d\n", __func__,
+                portdata->outstanding_urbs);
         spin_unlock_irqrestore(&portdata->lock, flags);
-        return count;
+        return retval;
 }
 
 static void sierra_indat_callback(struct urb *urb)
@@ -491,33 +491,39 @@ static void sierra_indat_callback(struct urb *urb)
         unsigned char *data = urb->transfer_buffer;
         int status = urb->status;
 
-        dbg("%s: %p", __func__, urb);
-
         endpoint = usb_pipeendpoint(urb->pipe);
-        port =  urb->context;
+        port = urb->context;
+
+        dev_dbg(&port->dev, "%s: %p\n", __func__, urb);
 
         if (status) {
                 dev_dbg(&port->dev, "%s: nonzero status: %d on"
-                    " endpoint %02x.", __func__, status, endpoint);
+                        " endpoint %02x\n", __func__, status, endpoint);
         } else {
                 if (urb->actual_length) {
                         tty = tty_port_tty_get(&port->port);
+
                         tty_buffer_request_room(tty, urb->actual_length);
                         tty_insert_flip_string(tty, data, urb->actual_length);
                         tty_flip_buffer_push(tty);
+
                         tty_kref_put(tty);
-                } else
+                        usb_serial_debug_data(debug, &port->dev, __func__,
+                                urb->actual_length, data);
+                } else {
                         dev_dbg(&port->dev, "%s: empty read urb"
-                                " received", __func__);
-
-                /* Resubmit urb so we continue receiving */
-                if (port->port.count && status != -ESHUTDOWN && status != -EPERM) {
-                        err = usb_submit_urb(urb, GFP_ATOMIC);
-                        if (err)
-                                dev_err(&port->dev, "resubmit read urb failed."
-                                        "(%d)\n", err);
+                                " received\n", __func__);
                 }
         }
+
+        /* Resubmit urb so we continue receiving */
+        if (port->port.count && status != -ESHUTDOWN && status != -EPERM) {
+                err = usb_submit_urb(urb, GFP_ATOMIC);
+                if (err)
+                        dev_err(&port->dev, "resubmit read urb failed."
+                                "(%d)\n", err);
+        }
+
         return;
 }
 
@@ -529,8 +535,7 @@ static void sierra_instat_callback(struct urb *urb)
         struct sierra_port_private *portdata = usb_get_serial_port_data(port);
         struct usb_serial *serial = port->serial;
 
-        dev_dbg(&port->dev, "%s", __func__);
-        dev_dbg(&port->dev, "%s: urb %p port %p has data %p", __func__,
+        dev_dbg(&port->dev, "%s: urb %p port %p has data %p\n", __func__,
                 urb, port, portdata);
 
         if (status == 0) {
@@ -550,7 +555,7 @@ static void sierra_instat_callback(struct urb *urb)
                                         sizeof(struct usb_ctrlrequest));
                         struct tty_struct *tty;
 
-                        dev_dbg(&port->dev, "%s: signal x%x", __func__,
+                        dev_dbg(&port->dev, "%s: signal x%x\n", __func__,
                                 signals);
 
                         old_dcd_state = portdata->dcd_state;
@@ -565,20 +570,20 @@ static void sierra_instat_callback(struct urb *urb)
                                 tty_hangup(tty);
                         tty_kref_put(tty);
                 } else {
-                        dev_dbg(&port->dev, "%s: type %x req %x",
+                        dev_dbg(&port->dev, "%s: type %x req %x\n",
                                 __func__, req_pkt->bRequestType,
                                 req_pkt->bRequest);
                 }
         } else
-                dev_dbg(&port->dev, "%s: error %d", __func__, status);
+                dev_dbg(&port->dev, "%s: error %d\n", __func__, status);
 
         /* Resubmit urb so we continue receiving IRQ data */
-        if (status != -ESHUTDOWN) {
+        if (port->port.count && status != -ESHUTDOWN && status != -ENOENT) {
                 urb->dev = serial->dev;
                 err = usb_submit_urb(urb, GFP_ATOMIC);
                 if (err)
-                        dev_dbg(&port->dev, "%s: resubmit intr urb "
-                                "failed. (%d)", __func__, err);
+                        dev_err(&port->dev, "%s: resubmit intr urb "
+                                "failed. (%d)\n", __func__, err);
         }
 }
 
@@ -588,7 +593,7 @@ static int sierra_write_room(struct tty_struct *tty)
         struct sierra_port_private *portdata = usb_get_serial_port_data(port);
         unsigned long flags;
 
-        dev_dbg(&port->dev, "%s - port %d", __func__, port->number);
+        dev_dbg(&port->dev, "%s - port %d\n", __func__, port->number);
 
         /* try to give a good number back based on if we have any free urbs at
          * this point in time */
@@ -729,7 +734,7 @@ static int sierra_open(struct tty_struct *tty,
 
         portdata = usb_get_serial_port_data(port);
 
-        dev_dbg(&port->dev, "%s", __func__);
+        dev_dbg(&port->dev, "%s\n", __func__);
 
         /* Set some sane defaults */
         portdata->rts_state = 1;
@@ -782,7 +787,7 @@ static int sierra_startup(struct usb_serial *serial)
         struct sierra_port_private *portdata;
         int i;
 
-        dev_dbg(&serial->dev->dev, "%s", __func__);
+        dev_dbg(&serial->dev->dev, "%s\n", __func__);
 
         /* Set Device mode to D0 */
         sierra_set_power_state(serial->dev, 0x0000);
@@ -797,7 +802,7 @@ static int sierra_startup(struct usb_serial *serial)
                 portdata = kzalloc(sizeof(*portdata), GFP_KERNEL);
                 if (!portdata) {
                         dev_dbg(&port->dev, "%s: kmalloc for "
-                                "sierra_port_private (%d) failed!.",
+                                "sierra_port_private (%d) failed!.\n",
                                 __func__, i);
                         return -ENOMEM;
                 }
@@ -809,13 +814,13 @@ static int sierra_startup(struct usb_serial *serial)
         return 0;
 }
 
-static void sierra_shutdown(struct usb_serial *serial)
+static void sierra_disconnect(struct usb_serial *serial)
 {
         int i;
         struct usb_serial_port *port;
         struct sierra_port_private *portdata;
 
-        dev_dbg(&serial->dev->dev, "%s", __func__);
+        dev_dbg(&serial->dev->dev, "%s\n", __func__);
 
         for (i = 0; i < serial->num_ports; ++i) {
                 port = serial->port[i];
@@ -848,7 +853,7 @@ static struct usb_serial_driver sierra_device = {
         .tiocmget          = sierra_tiocmget,
         .tiocmset          = sierra_tiocmset,
         .attach            = sierra_startup,
-        .shutdown          = sierra_shutdown,
+        .disconnect        = sierra_disconnect,
         .read_int_callback = sierra_instat_callback,
 };
 
diff --git a/drivers/usb/serial/spcp8x5.c b/drivers/usb/serial/spcp8x5.c
index 8f7ed8f13996..3c249d8e8b8e 100644
--- a/drivers/usb/serial/spcp8x5.c
+++ b/drivers/usb/serial/spcp8x5.c
@@ -356,7 +356,7 @@ cleanup:
 }
 
 /* call when the device plug out. free all the memory alloced by probe */
-static void spcp8x5_shutdown(struct usb_serial *serial)
+static void spcp8x5_release(struct usb_serial *serial)
 {
         int i;
         struct spcp8x5_private *priv;
@@ -366,7 +366,6 @@ static void spcp8x5_shutdown(struct usb_serial *serial)
                 if (priv) {
                         free_ringbuf(priv->buf);
                         kfree(priv);
-                        usb_set_serial_port_data(serial->port[i] , NULL);
                 }
         }
 }
@@ -1020,7 +1019,7 @@ static struct usb_serial_driver spcp8x5_device = {
         .write_bulk_callback    = spcp8x5_write_bulk_callback,
         .chars_in_buffer        = spcp8x5_chars_in_buffer,
         .attach                 = spcp8x5_startup,
-        .shutdown               = spcp8x5_shutdown,
+        .release                = spcp8x5_release,
 };
 
 static int __init spcp8x5_init(void)
diff --git a/drivers/usb/serial/symbolserial.c b/drivers/usb/serial/symbolserial.c
index 8b07ebc6baeb..6157fac9366b 100644
--- a/drivers/usb/serial/symbolserial.c
+++ b/drivers/usb/serial/symbolserial.c
@@ -267,7 +267,7 @@ error:
         return retval;
 }
 
-static void symbol_shutdown(struct usb_serial *serial)
+static void symbol_disconnect(struct usb_serial *serial)
 {
         struct symbol_private *priv = usb_get_serial_data(serial);
 
@@ -275,9 +275,16 @@ static void symbol_shutdown(struct usb_serial *serial)
 
         usb_kill_urb(priv->int_urb);
         usb_free_urb(priv->int_urb);
+}
+
+static void symbol_release(struct usb_serial *serial)
+{
+        struct symbol_private *priv = usb_get_serial_data(serial);
+
+        dbg("%s", __func__);
+
         kfree(priv->int_buffer);
         kfree(priv);
-        usb_set_serial_data(serial, NULL);
 }
 
 static struct usb_driver symbol_driver = {
@@ -299,7 +306,8 @@ static struct usb_serial_driver symbol_device = {
         .attach =               symbol_startup,
         .open =                 symbol_open,
         .close =                symbol_close,
-        .shutdown =             symbol_shutdown,
+        .disconnect =           symbol_disconnect,
+        .release =              symbol_release,
         .throttle =             symbol_throttle,
         .unthrottle =           symbol_unthrottle,
 };
diff --git a/drivers/usb/serial/ti_usb_3410_5052.c b/drivers/usb/serial/ti_usb_3410_5052.c
index 42cb04c403be..991d8232e376 100644
--- a/drivers/usb/serial/ti_usb_3410_5052.c
+++ b/drivers/usb/serial/ti_usb_3410_5052.c
@@ -97,7 +97,7 @@ struct ti_device {
 /* Function Declarations */
 
 static int ti_startup(struct usb_serial *serial);
-static void ti_shutdown(struct usb_serial *serial);
+static void ti_release(struct usb_serial *serial);
 static int ti_open(struct tty_struct *tty, struct usb_serial_port *port,
                 struct file *file);
 static void ti_close(struct usb_serial_port *port);
@@ -230,7 +230,7 @@ static struct usb_serial_driver ti_1port_device = {
         .id_table               = ti_id_table_3410,
         .num_ports              = 1,
         .attach                 = ti_startup,
-        .shutdown               = ti_shutdown,
+        .release                = ti_release,
         .open                   = ti_open,
         .close                  = ti_close,
         .write                  = ti_write,
@@ -258,7 +258,7 @@ static struct usb_serial_driver ti_2port_device = {
         .id_table               = ti_id_table_5052,
         .num_ports              = 2,
         .attach                 = ti_startup,
-        .shutdown               = ti_shutdown,
+        .release                = ti_release,
         .open                   = ti_open,
         .close                  = ti_close,
         .write                  = ti_write,
@@ -473,7 +473,7 @@ free_tdev:
 }
 
 
-static void ti_shutdown(struct usb_serial *serial)
+static void ti_release(struct usb_serial *serial)
 {
         int i;
         struct ti_device *tdev = usb_get_serial_data(serial);
@@ -486,12 +486,10 @@ static void ti_shutdown(struct usb_serial *serial)
                 if (tport) {
                         ti_buf_free(tport->tp_write_buf);
                         kfree(tport);
-                        usb_set_serial_port_data(serial->port[i], NULL);
                 }
         }
 
         kfree(tdev);
-        usb_set_serial_data(serial, NULL);
 }
 
 
diff --git a/drivers/usb/serial/usb-serial.c b/drivers/usb/serial/usb-serial.c
index 1967a7edc10c..d595aa5586a7 100644
--- a/drivers/usb/serial/usb-serial.c
+++ b/drivers/usb/serial/usb-serial.c
@@ -141,6 +141,14 @@ static void destroy_serial(struct kref *kref)
         if (serial->minor != SERIAL_TTY_NO_MINOR)
                 return_serial(serial);
 
+        serial->type->release(serial);
+
+        for (i = 0; i < serial->num_ports; ++i) {
+                port = serial->port[i];
+                if (port)
+                        put_device(&port->dev);
+        }
+
         /* If this is a "fake" port, we have to clean it up here, as it will
          * not get cleaned up in port_release() as it was never registered with
          * the driver core */
@@ -148,9 +156,8 @@ static void destroy_serial(struct kref *kref)
                 for (i = serial->num_ports;
                                         i < serial->num_port_pointers; ++i) {
                         port = serial->port[i];
-                        if (!port)
-                                continue;
-                        port_free(port);
+                        if (port)
+                                port_free(port);
                 }
         }
 
@@ -1046,10 +1053,15 @@ int usb_serial_probe(struct usb_interface *interface,
 
                 dev_set_name(&port->dev, "ttyUSB%d", port->number);
                 dbg ("%s - registering %s", __func__, dev_name(&port->dev));
+                port->dev_state = PORT_REGISTERING;
                 retval = device_register(&port->dev);
-                if (retval)
+                if (retval) {
                         dev_err(&port->dev, "Error registering port device, "
                                 "continuing\n");
+                        port->dev_state = PORT_UNREGISTERED;
+                } else {
+                        port->dev_state = PORT_REGISTERED;
+                }
         }
 
         usb_serial_console_init(debug, minor);
@@ -1113,10 +1125,6 @@ void usb_serial_disconnect(struct usb_interface *interface)
         serial->disconnected = 1;
         mutex_unlock(&serial->disc_mutex);
 
-        /* Unfortunately, many of the sub-drivers expect the port structures
-         * to exist when their shutdown method is called, so we have to go
-         * through this awkward two-step unregistration procedure.
-         */
         for (i = 0; i < serial->num_ports; ++i) {
                 port = serial->port[i];
                 if (port) {
@@ -1130,17 +1138,25 @@ void usb_serial_disconnect(struct usb_interface *interface)
                         }
                         kill_traffic(port);
                         cancel_work_sync(&port->work);
-                        device_del(&port->dev);
-                }
-        }
-        serial->type->shutdown(serial);
-        for (i = 0; i < serial->num_ports; ++i) {
-                port = serial->port[i];
-                if (port) {
-                        put_device(&port->dev);
-                        serial->port[i] = NULL;
+                        if (port->dev_state == PORT_REGISTERED) {
+
+                                /* Make sure the port is bound so that the
+                                 * driver's port_remove method is called.
+                                 */
+                                if (!port->dev.driver) {
+                                        int rc;
+
+                                        port->dev.driver =
+                                                        &serial->type->driver;
+                                        rc = device_bind_driver(&port->dev);
+                                }
+                                port->dev_state = PORT_UNREGISTERING;
+                                device_del(&port->dev);
+                                port->dev_state = PORT_UNREGISTERED;
+                        }
                 }
         }
+        serial->type->disconnect(serial);
 
         /* let the last holder of this object
          * cause it to be cleaned up */
@@ -1318,7 +1334,8 @@ static void fixup_generic(struct usb_serial_driver *device)
         set_to_generic_if_null(device, chars_in_buffer);
         set_to_generic_if_null(device, read_bulk_callback);
         set_to_generic_if_null(device, write_bulk_callback);
-        set_to_generic_if_null(device, shutdown);
+        set_to_generic_if_null(device, disconnect);
+        set_to_generic_if_null(device, release);
 }
 
 int usb_serial_register(struct usb_serial_driver *driver)
diff --git a/drivers/usb/serial/usb_debug.c b/drivers/usb/serial/usb_debug.c
index 6c9cbb59552a..614800972dc3 100644
--- a/drivers/usb/serial/usb_debug.c
+++ b/drivers/usb/serial/usb_debug.c
@@ -15,7 +15,19 @@
 #include <linux/usb.h>
 #include <linux/usb/serial.h>
 
+#define URB_DEBUG_MAX_IN_FLIGHT_URBS    4000
 #define USB_DEBUG_MAX_PACKET_SIZE       8
+#define USB_DEBUG_BRK_SIZE              8
+static char USB_DEBUG_BRK[USB_DEBUG_BRK_SIZE] = {
+        0x00,
+        0xff,
+        0x01,
+        0xfe,
+        0x00,
+        0xfe,
+        0x01,
+        0xff,
+};
 
 static struct usb_device_id id_table [] = {
         { USB_DEVICE(0x0525, 0x127a) },
@@ -38,6 +50,32 @@ static int usb_debug_open(struct tty_struct *tty, struct usb_serial_port *port,
         return usb_serial_generic_open(tty, port, filp);
 }
 
+/* This HW really does not support a serial break, so one will be
+ * emulated when ever the break state is set to true.
+ */
+static void usb_debug_break_ctl(struct tty_struct *tty, int break_state)
+{
+        struct usb_serial_port *port = tty->driver_data;
+        if (!break_state)
+                return;
+        usb_serial_generic_write(tty, port, USB_DEBUG_BRK, USB_DEBUG_BRK_SIZE);
+}
+
+static void usb_debug_read_bulk_callback(struct urb *urb)
+{
+        struct usb_serial_port *port = urb->context;
+
+        if (urb->actual_length == USB_DEBUG_BRK_SIZE &&
+            memcmp(urb->transfer_buffer, USB_DEBUG_BRK,
+                   USB_DEBUG_BRK_SIZE) == 0) {
+                usb_serial_handle_break(port);
+                usb_serial_generic_resubmit_read_urb(port, GFP_ATOMIC);
+                return;
+        }
+
+        usb_serial_generic_read_bulk_callback(urb);
+}
+
 static struct usb_serial_driver debug_device = {
         .driver = {
                 .owner =        THIS_MODULE,
@@ -46,6 +84,9 @@ static struct usb_serial_driver debug_device = {
         .id_table =             id_table,
         .num_ports =            1,
         .open =                 usb_debug_open,
+        .max_in_flight_urbs =   URB_DEBUG_MAX_IN_FLIGHT_URBS,
+        .break_ctl =            usb_debug_break_ctl,
+        .read_bulk_callback =   usb_debug_read_bulk_callback,
 };
 
 static int __init debug_init(void)
diff --git a/drivers/usb/serial/visor.c b/drivers/usb/serial/visor.c
index b15f1c0e1d4a..f5d0f64dcc52 100644
--- a/drivers/usb/serial/visor.c
+++ b/drivers/usb/serial/visor.c
@@ -47,7 +47,7 @@ static void visor_unthrottle(struct tty_struct *tty);
 static int  visor_probe(struct usb_serial *serial,
                                         const struct usb_device_id *id);
 static int  visor_calc_num_ports(struct usb_serial *serial);
-static void visor_shutdown(struct usb_serial *serial);
+static void visor_release(struct usb_serial *serial);
 static void visor_write_bulk_callback(struct urb *urb);
 static void visor_read_bulk_callback(struct urb *urb);
 static void visor_read_int_callback(struct urb *urb);
@@ -202,7 +202,7 @@ static struct usb_serial_driver handspring_device = {
         .attach =               treo_attach,
         .probe =                visor_probe,
         .calc_num_ports =       visor_calc_num_ports,
-        .shutdown =             visor_shutdown,
+        .release =              visor_release,
         .write =                visor_write,
         .write_room =           visor_write_room,
         .write_bulk_callback =  visor_write_bulk_callback,
@@ -227,7 +227,7 @@ static struct usb_serial_driver clie_5_device = {
         .attach =               clie_5_attach,
         .probe =                visor_probe,
         .calc_num_ports =       visor_calc_num_ports,
-        .shutdown =             visor_shutdown,
+        .release =              visor_release,
         .write =                visor_write,
         .write_room =           visor_write_room,
         .write_bulk_callback =  visor_write_bulk_callback,
@@ -918,7 +918,7 @@ static int clie_5_attach(struct usb_serial *serial)
         return generic_startup(serial);
 }
 
-static void visor_shutdown(struct usb_serial *serial)
+static void visor_release(struct usb_serial *serial)
 {
         struct visor_private *priv;
         int i;
@@ -927,10 +927,7 @@ static void visor_shutdown(struct usb_serial *serial)
 
         for (i = 0; i < serial->num_ports; i++) {
                 priv = usb_get_serial_port_data(serial->port[i]);
-                if (priv) {
-                        usb_set_serial_port_data(serial->port[i], NULL);
-                        kfree(priv);
-                }
+                kfree(priv);
         }
 }
 
diff --git a/drivers/usb/serial/whiteheat.c b/drivers/usb/serial/whiteheat.c
index 7c7295d09f34..8d126dd7a02e 100644
--- a/drivers/usb/serial/whiteheat.c
+++ b/drivers/usb/serial/whiteheat.c
@@ -144,7 +144,7 @@ static int  whiteheat_firmware_attach(struct usb_serial *serial);
 
 /* function prototypes for the Connect Tech WhiteHEAT serial converter */
 static int  whiteheat_attach(struct usb_serial *serial);
-static void whiteheat_shutdown(struct usb_serial *serial);
+static void whiteheat_release(struct usb_serial *serial);
 static int  whiteheat_open(struct tty_struct *tty,
                         struct usb_serial_port *port, struct file *filp);
 static void whiteheat_close(struct usb_serial_port *port);
@@ -189,7 +189,7 @@ static struct usb_serial_driver whiteheat_device = {
         .id_table =             id_table_std,
         .num_ports =            4,
         .attach =               whiteheat_attach,
-        .shutdown =             whiteheat_shutdown,
+        .release =              whiteheat_release,
         .open =                 whiteheat_open,
         .close =                whiteheat_close,
         .write =                whiteheat_write,
@@ -617,7 +617,7 @@ no_command_buffer:
 }
 
 
-static void whiteheat_shutdown(struct usb_serial *serial)
+static void whiteheat_release(struct usb_serial *serial)
 {
         struct usb_serial_port *command_port;
         struct usb_serial_port *port;
diff --git a/drivers/usb/storage/initializers.c b/drivers/usb/storage/initializers.c
index 2dd9bd4bff56..ec17c96371af 100644
--- a/drivers/usb/storage/initializers.c
+++ b/drivers/usb/storage/initializers.c
@@ -52,7 +52,7 @@ int usb_stor_euscsi_init(struct us_data *us)
         us->iobuf[0] = 0x1;
         result = usb_stor_control_msg(us, us->send_ctrl_pipe,
                         0x0C, USB_RECIP_INTERFACE | USB_TYPE_VENDOR,
-                        0x01, 0x0, us->iobuf, 0x1, 5*HZ);
+                        0x01, 0x0, us->iobuf, 0x1, 5000);
         US_DEBUGP("-- result is %d\n", result);
 
         return 0;
@@ -80,14 +80,16 @@ int usb_stor_ucr61s2b_init(struct us_data *us)
 
         res = usb_stor_bulk_transfer_buf(us, us->send_bulk_pipe, bcb,
                         US_BULK_CB_WRAP_LEN, &partial);
-        if(res)
-                return res;
+        if (res)
+                return -EIO;
 
         US_DEBUGP("Getting status packet...\n");
         res = usb_stor_bulk_transfer_buf(us, us->recv_bulk_pipe, bcs,
                         US_BULK_CS_WRAP_LEN, &partial);
+        if (res)
+                return -EIO;
 
-        return (res ? -1 : 0);
+        return 0;
 }
 
 /* This places the HUAWEI E220 devices in multi-port mode */
@@ -99,6 +101,6 @@ int usb_stor_huawei_e220_init(struct us_data *us)
                                       USB_REQ_SET_FEATURE,
                                       USB_TYPE_STANDARD | USB_RECIP_DEVICE,
                                       0x01, 0x0, NULL, 0x0, 1000);
-        US_DEBUGP("usb_control_msg performing result is %d\n", result);
-        return (result ? 0 : -1);
+        US_DEBUGP("Huawei mode set result is %d\n", result);
+        return (result ? 0 : -ENODEV);
 }
diff --git a/drivers/usb/storage/option_ms.c b/drivers/usb/storage/option_ms.c
index 353f922939a4..d41cc0a970f7 100644
--- a/drivers/usb/storage/option_ms.c
+++ b/drivers/usb/storage/option_ms.c
@@ -37,7 +37,7 @@ MODULE_PARM_DESC(option_zero_cd, "ZeroCD mode (1=Force Modem (default),"
 
 #define RESPONSE_LEN 1024
 
-static int option_rezero(struct us_data *us, int ep_in, int ep_out)
+static int option_rezero(struct us_data *us)
 {
         const unsigned char rezero_msg[] = {
           0x55, 0x53, 0x42, 0x43, 0x78, 0x56, 0x34, 0x12,
@@ -54,10 +54,10 @@ static int option_rezero(struct us_data *us, int ep_in, int ep_out)
         if (buffer == NULL)
                 return USB_STOR_TRANSPORT_ERROR;
 
-        memcpy(buffer, rezero_msg, sizeof (rezero_msg));
+        memcpy(buffer, rezero_msg, sizeof(rezero_msg));
         result = usb_stor_bulk_transfer_buf(us,
-                        usb_sndbulkpipe(us->pusb_dev, ep_out),
-                        buffer, sizeof (rezero_msg), NULL);
+                        us->send_bulk_pipe,
+                        buffer, sizeof(rezero_msg), NULL);
         if (result != USB_STOR_XFER_GOOD) {
                 result = USB_STOR_XFER_ERROR;
                 goto out;
@@ -66,9 +66,15 @@ static int option_rezero(struct us_data *us, int ep_in, int ep_out)
         /* Some of the devices need to be asked for a response, but we don't
          * care what that response is.
          */
-        result = usb_stor_bulk_transfer_buf(us,
-                        usb_sndbulkpipe(us->pusb_dev, ep_out),
+        usb_stor_bulk_transfer_buf(us,
+                        us->recv_bulk_pipe,
                         buffer, RESPONSE_LEN, NULL);
+
+        /* Read the CSW */
+        usb_stor_bulk_transfer_buf(us,
+                        us->recv_bulk_pipe,
+                        buffer, 13, NULL);
+
         result = USB_STOR_XFER_GOOD;
 
 out:
@@ -76,63 +82,75 @@ out:
         return result;
 }
 
-int option_ms_init(struct us_data *us)
+static int option_inquiry(struct us_data *us)
 {
-        struct usb_device *udev;
-        struct usb_interface *intf;
-        struct usb_host_interface *iface_desc;
-        struct usb_endpoint_descriptor *endpoint = NULL;
-        u8 ep_in = 0, ep_out = 0;
-        int ep_in_size = 0, ep_out_size = 0;
-        int i, result;
-
-        udev = us->pusb_dev;
-        intf = us->pusb_intf;
-
-        /* Ensure it's really a ZeroCD device; devices that are already
-         * in modem mode return 0xFF for class, subclass, and protocol.
-         */
-        if (udev->descriptor.bDeviceClass != 0 ||
-            udev->descriptor.bDeviceSubClass != 0 ||
-            udev->descriptor.bDeviceProtocol != 0)
-                return USB_STOR_TRANSPORT_GOOD;
+        const unsigned char inquiry_msg[] = {
+          0x55, 0x53, 0x42, 0x43, 0x12, 0x34, 0x56, 0x78,
+          0x24, 0x00, 0x00, 0x00, 0x80, 0x00, 0x06, 0x12,
+          0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00,
+          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+        };
+        char *buffer;
+        int result;
 
-        US_DEBUGP("Option MS: option_ms_init called\n");
+        US_DEBUGP("Option MS: %s", "device inquiry for vendor name\n");
 
-        /* Find the right mass storage interface */
-        iface_desc = intf->cur_altsetting;
-        if (iface_desc->desc.bInterfaceClass != 0x8 ||
-            iface_desc->desc.bInterfaceSubClass != 0x6 ||
-            iface_desc->desc.bInterfaceProtocol != 0x50) {
-                US_DEBUGP("Option MS: mass storage interface not found, no action "
-                          "required\n");
-                return USB_STOR_TRANSPORT_GOOD;
-        }
+        buffer = kzalloc(0x24, GFP_KERNEL);
+        if (buffer == NULL)
+                return USB_STOR_TRANSPORT_ERROR;
 
-        /* Find the mass storage bulk endpoints */
-        for (i = 0; i < iface_desc->desc.bNumEndpoints && (!ep_in_size || !ep_out_size); ++i) {
-                endpoint = &iface_desc->endpoint[i].desc;
-
-                if (usb_endpoint_is_bulk_in(endpoint)) {
-                        ep_in = usb_endpoint_num(endpoint);
-                        ep_in_size = le16_to_cpu(endpoint->wMaxPacketSize);
-                } else if (usb_endpoint_is_bulk_out(endpoint)) {
-                        ep_out = usb_endpoint_num(endpoint);
-                        ep_out_size = le16_to_cpu(endpoint->wMaxPacketSize);
-                }
+        memcpy(buffer, inquiry_msg, sizeof(inquiry_msg));
+        result = usb_stor_bulk_transfer_buf(us,
+                        us->send_bulk_pipe,
+                        buffer, sizeof(inquiry_msg), NULL);
+        if (result != USB_STOR_XFER_GOOD) {
+                result = USB_STOR_XFER_ERROR;
+                goto out;
         }
 
-        /* Can't find the mass storage endpoints */
-        if (!ep_in_size || !ep_out_size) {
-                US_DEBUGP("Option MS: mass storage endpoints not found, no action "
-                          "required\n");
-                return USB_STOR_TRANSPORT_GOOD;
+        result = usb_stor_bulk_transfer_buf(us,
+                        us->recv_bulk_pipe,
+                        buffer, 0x24, NULL);
+        if (result != USB_STOR_XFER_GOOD) {
+                result = USB_STOR_XFER_ERROR;
+                goto out;
         }
 
+        result = memcmp(buffer+8, "Option", 6);
+
+        /* Read the CSW */
+        usb_stor_bulk_transfer_buf(us,
+                        us->recv_bulk_pipe,
+                        buffer, 13, NULL);
+
+out:
+        kfree(buffer);
+        return result;
+}
+
+
+int option_ms_init(struct us_data *us)
+{
+        int result;
+
+        US_DEBUGP("Option MS: option_ms_init called\n");
+
+        /* Additional test for vendor information via INQUIRY,
+         * because some vendor/product IDs are ambiguous
+         */
+        result = option_inquiry(us);
+        if (result != 0) {
+                US_DEBUGP("Option MS: vendor is not Option or not determinable,"
+                          " no action taken\n");
+                return 0;
+        } else
+                US_DEBUGP("Option MS: this is a genuine Option device,"
+                          " proceeding\n");
+
         /* Force Modem mode */
         if (option_zero_cd == ZCD_FORCE_MODEM) {
                 US_DEBUGP("Option MS: %s", "Forcing Modem Mode\n");
-                result = option_rezero(us, ep_in, ep_out);
+                result = option_rezero(us);
                 if (result != USB_STOR_XFER_GOOD)
                         US_DEBUGP("Option MS: Failed to switch to modem mode.\n");
                 return -EIO;
@@ -142,6 +160,6 @@ int option_ms_init(struct us_data *us)
                           " requests it\n");
         }
 
-        return USB_STOR_TRANSPORT_GOOD;
+        return 0;
 }
 
diff --git a/drivers/usb/storage/sierra_ms.c b/drivers/usb/storage/sierra_ms.c
index 4359a2cb42df..4395c4100ec2 100644
--- a/drivers/usb/storage/sierra_ms.c
+++ b/drivers/usb/storage/sierra_ms.c
@@ -202,6 +202,6 @@ int sierra_ms_init(struct us_data *us)
 complete:
         result = device_create_file(&us->pusb_intf->dev, &dev_attr_truinst);
 
-        return USB_STOR_TRANSPORT_GOOD;
+        return 0;
 }
 
diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h
index 4b8b69045fe6..1b9c5dd0fb27 100644
--- a/drivers/usb/storage/unusual_devs.h
+++ b/drivers/usb/storage/unusual_devs.h
@@ -1385,7 +1385,7 @@ UNUSUAL_DEV(  0x10d6, 0x2200, 0x0100, 0x0100,
 UNUSUAL_DEV(  0x1186, 0x3e04, 0x0000, 0x0000,
            "D-Link",
            "USB Mass Storage",
-           US_SC_DEVICE, US_PR_DEVICE, option_ms_init, 0),
+           US_SC_DEVICE, US_PR_DEVICE, option_ms_init, US_FL_IGNORE_DEVICE),
 
 /* Reported by Kevin Lloyd <linux@sierrawireless.com>
  * Entry is needed for the initializer function override,
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2b5a691064b7..932ffdbf86d9 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2104,6 +2104,7 @@ config FB_MB862XX_LIME
         bool "Lime GDC"
         depends on FB_MB862XX
         depends on OF && !FB_MB862XX_PCI_GDC
+        depends on PPC
         select FB_FOREIGN_ENDIAN
         select FB_LITTLE_ENDIAN
         ---help---
diff --git a/drivers/video/acornfb.c b/drivers/video/acornfb.c
index 6995fe1e86d4..0bcc59eb37fa 100644
--- a/drivers/video/acornfb.c
+++ b/drivers/video/acornfb.c
@@ -859,43 +859,6 @@ acornfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
         return 0;
 }
 
-/*
- * Note that we are entered with the kernel locked.
- */
-static int
-acornfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
-{
-        unsigned long off, start;
-        u32 len;
-
-        off = vma->vm_pgoff << PAGE_SHIFT;
-
-        start = info->fix.smem_start;
-        len = PAGE_ALIGN(start & ~PAGE_MASK) + info->fix.smem_len;
-        start &= PAGE_MASK;
-        if ((vma->vm_end - vma->vm_start + off) > len)
-                return -EINVAL;
-        off += start;
-        vma->vm_pgoff = off >> PAGE_SHIFT;
-
-        /* This is an IO map - tell maydump to skip this VMA */
-        vma->vm_flags |= VM_IO;
-
-        vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
-
-        /*
-         * Don't alter the page protection flags; we want to keep the area
-         * cached for better performance.  This does mean that we may miss
-         * some updates to the screen occasionally, but process switches
-         * should cause the caches and buffers to be flushed often enough.
-         */
-        if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
-                                vma->vm_end - vma->vm_start,
-                                vma->vm_page_prot))
-                return -EAGAIN;
-        return 0;
-}
-
 static struct fb_ops acornfb_ops = {
         .owner          = THIS_MODULE,
         .fb_check_var   = acornfb_check_var,
@@ -905,7 +868,6 @@ static struct fb_ops acornfb_ops = {
         .fb_fillrect    = cfb_fillrect,
         .fb_copyarea    = cfb_copyarea,
         .fb_imageblit   = cfb_imageblit,
-        .fb_mmap        = acornfb_mmap,
 };
 
 /*
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 2fb63f6ea2f1..5afd64482f55 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -345,7 +345,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
         dev_dbg(dev, "  bpp:        %u\n", var->bits_per_pixel);
         dev_dbg(dev, "  clk:        %lu KHz\n", clk_value_khz);
 
-        if ((PICOS2KHZ(var->pixclock) * var->bits_per_pixel / 8) > clk_value_khz) {
+        if (PICOS2KHZ(var->pixclock) > clk_value_khz) {
                 dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
                 return -EINVAL;
         }
diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c
index 97a1f095f327..515cf1978d19 100644
--- a/drivers/video/aty/radeon_pm.c
+++ b/drivers/video/aty/radeon_pm.c
@@ -213,7 +213,6 @@ static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
                          PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb     |
                          PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb       |
                          PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb          |
-                         PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb          |
                          PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
                 OUTPLL(pllPIXCLKS_CNTL, tmp);
 
@@ -395,7 +394,7 @@ static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
                         PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb      |
                         PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb        |
                         PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb           |
-                        PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb);
+                        PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb);
                 OUTPLL(pllPIXCLKS_CNTL, tmp);
 
                 tmp = INPLL(pllMCLK_MISC);
diff --git a/drivers/video/bf54x-lq043fb.c b/drivers/video/bf54x-lq043fb.c
index 37e60b1d2ed9..e49ae5edcc00 100644
--- a/drivers/video/bf54x-lq043fb.c
+++ b/drivers/video/bf54x-lq043fb.c
@@ -323,7 +323,6 @@ static int bfin_bf54x_fb_release(struct fb_info *info, int user)
                 bfin_write_EPPI0_CONTROL(0);
                 SSYNC();
                 disable_dma(CH_EPPI0);
-                memset(fbi->fb_buffer, 0, info->fix.smem_len);
         }
 
         spin_unlock(&fbi->lock);
@@ -530,7 +529,7 @@ static irqreturn_t bfin_bf54x_irq_error(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static int __init bfin_bf54x_probe(struct platform_device *pdev)
+static int __devinit bfin_bf54x_probe(struct platform_device *pdev)
 {
         struct bfin_bf54xfb_info *info;
         struct fb_info *fbinfo;
@@ -626,14 +625,12 @@ static int __init bfin_bf54x_probe(struct platform_device *pdev)
                 goto out3;
         }
 
-        memset(info->fb_buffer, 0, fbinfo->fix.smem_len);
-
         fbinfo->screen_base = (void *)info->fb_buffer;
         fbinfo->fix.smem_start = (int)info->fb_buffer;
 
         fbinfo->fbops = &bfin_bf54x_fb_ops;
 
-        fbinfo->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL);
+        fbinfo->pseudo_palette = kzalloc(sizeof(u32) * 16, GFP_KERNEL);
         if (!fbinfo->pseudo_palette) {
                 printk(KERN_ERR DRIVER_NAME
                        "Fail to allocate pseudo_palette\n");
@@ -642,8 +639,6 @@ static int __init bfin_bf54x_probe(struct platform_device *pdev)
                 goto out4;
         }
 
-        memset(fbinfo->pseudo_palette, 0, sizeof(u32) * 16);
-
         if (fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0)
             < 0) {
                 printk(KERN_ERR DRIVER_NAME
@@ -712,7 +707,7 @@ out1:
         return ret;
 }
 
-static int bfin_bf54x_remove(struct platform_device *pdev)
+static int __devexit bfin_bf54x_remove(struct platform_device *pdev)
 {
 
         struct fb_info *fbinfo = platform_get_drvdata(pdev);
@@ -781,7 +776,7 @@ static int bfin_bf54x_resume(struct platform_device *pdev)
 
 static struct platform_driver bfin_bf54x_driver = {
         .probe = bfin_bf54x_probe,
-        .remove = bfin_bf54x_remove,
+        .remove = __devexit_p(bfin_bf54x_remove),
         .suspend = bfin_bf54x_suspend,
         .resume = bfin_bf54x_resume,
         .driver = {
@@ -790,7 +785,7 @@ static struct platform_driver bfin_bf54x_driver = {
                    },
 };
 
-static int __devinit bfin_bf54x_driver_init(void)
+static int __init bfin_bf54x_driver_init(void)
 {
         return platform_driver_register(&bfin_bf54x_driver);
 }
diff --git a/drivers/video/bfin-t350mcqb-fb.c b/drivers/video/bfin-t350mcqb-fb.c
index 90cfddabf1f7..5cc36cfbf07b 100644
--- a/drivers/video/bfin-t350mcqb-fb.c
+++ b/drivers/video/bfin-t350mcqb-fb.c
@@ -242,7 +242,6 @@ static int bfin_t350mcqb_fb_release(struct fb_info *info, int user)
                 SSYNC();
                 disable_dma(CH_PPI);
                 bfin_t350mcqb_stop_timers();
-                memset(fbi->fb_buffer, 0, info->fix.smem_len);
         }
 
         spin_unlock(&fbi->lock);
@@ -527,8 +526,6 @@ static int __devinit bfin_t350mcqb_probe(struct platform_device *pdev)
                 goto out3;
         }
 
-        memset(info->fb_buffer, 0, fbinfo->fix.smem_len);
-
         fbinfo->screen_base = (void *)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET;
         fbinfo->fix.smem_start = (int)info->fb_buffer + ACTIVE_VIDEO_MEM_OFFSET;
 
@@ -602,7 +599,7 @@ out1:
         return ret;
 }
 
-static int bfin_t350mcqb_remove(struct platform_device *pdev)
+static int __devexit bfin_t350mcqb_remove(struct platform_device *pdev)
 {
 
         struct fb_info *fbinfo = platform_get_drvdata(pdev);
@@ -637,9 +634,6 @@ static int bfin_t350mcqb_remove(struct platform_device *pdev)
 #ifdef CONFIG_PM
 static int bfin_t350mcqb_suspend(struct platform_device *pdev, pm_message_t state)
 {
-        struct fb_info *fbinfo = platform_get_drvdata(pdev);
-        struct bfin_t350mcqbfb_info *info = fbinfo->par;
-
         bfin_t350mcqb_disable_ppi();
         disable_dma(CH_PPI);
         bfin_write_PPI_STATUS(0xFFFF);
@@ -649,9 +643,6 @@ static int bfin_t350mcqb_suspend(struct platform_device *pdev, pm_message_t stat
 
 static int bfin_t350mcqb_resume(struct platform_device *pdev)
 {
-        struct fb_info *fbinfo = platform_get_drvdata(pdev);
-        struct bfin_t350mcqbfb_info *info = fbinfo->par;
-
         enable_dma(CH_PPI);
         bfin_t350mcqb_enable_ppi();
 
@@ -664,7 +655,7 @@ static int bfin_t350mcqb_resume(struct platform_device *pdev)
 
 static struct platform_driver bfin_t350mcqb_driver = {
         .probe = bfin_t350mcqb_probe,
-        .remove = bfin_t350mcqb_remove,
+        .remove = __devexit_p(bfin_t350mcqb_remove),
         .suspend = bfin_t350mcqb_suspend,
         .resume = bfin_t350mcqb_resume,
         .driver = {
@@ -673,7 +664,7 @@ static struct platform_driver bfin_t350mcqb_driver = {
                    },
 };
 
-static int __devinit bfin_t350mcqb_driver_init(void)
+static int __init bfin_t350mcqb_driver_init(void)
 {
         return platform_driver_register(&bfin_t350mcqb_driver);
 }
diff --git a/drivers/video/carminefb.c b/drivers/video/carminefb.c
index c7ff3c1a266a..0c02f8ec4bf3 100644
--- a/drivers/video/carminefb.c
+++ b/drivers/video/carminefb.c
@@ -562,7 +562,7 @@ static int __devinit alloc_carmine_fb(void __iomem *regs, void __iomem *smem_bas
         if (ret < 0)
                 goto err_free_fb;
 
-        if (fb_mode > ARRAY_SIZE(carmine_modedb))
+        if (fb_mode >= ARRAY_SIZE(carmine_modedb))
                 fb_mode = CARMINEFB_DEFAULT_VIDEO_MODE;
 
         par->cur_mode = par->new_mode = ~0;
diff --git a/drivers/video/chipsfb.c b/drivers/video/chipsfb.c
index 777389c40988..57b9d276497e 100644
--- a/drivers/video/chipsfb.c
+++ b/drivers/video/chipsfb.c
@@ -414,7 +414,6 @@ chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
         }
 
         pci_set_drvdata(dp, p);
-        p->device = &dp->dev;
 
         init_chips(p, addr);
 
diff --git a/drivers/video/efifb.c b/drivers/video/efifb.c
index 8dea2bc92705..eb12182b2059 100644
--- a/drivers/video/efifb.c
+++ b/drivers/video/efifb.c
@@ -280,6 +280,9 @@ static int __init efifb_probe(struct platform_device *dev)
         info->pseudo_palette = info->par;
         info->par = NULL;
 
+        info->aperture_base = efifb_fix.smem_start;
+        info->aperture_size = size_total;
+
         info->screen_base = ioremap(efifb_fix.smem_start, efifb_fix.smem_len);
         if (!info->screen_base) {
                 printk(KERN_ERR "efifb: abort, cannot ioremap video memory "
@@ -337,7 +340,7 @@ static int __init efifb_probe(struct platform_device *dev)
         info->fbops = &efifb_ops;
         info->var = efifb_defined;
         info->fix = efifb_fix;
-        info->flags = FBINFO_FLAG_DEFAULT;
+        info->flags = FBINFO_FLAG_DEFAULT | FBINFO_MISC_FIRMWARE;
 
         if ((err = fb_alloc_cmap(&info->cmap, 256, 0)) < 0) {
                 printk(KERN_ERR "efifb: cannot allocate colormap\n");
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
index d412a1ddc12f..f8a09bf8d0cd 100644
--- a/drivers/video/fbmem.c
+++ b/drivers/video/fbmem.c
@@ -1462,6 +1462,16 @@ static int fb_check_foreignness(struct fb_info *fi)
         return 0;
 }
 
+static bool fb_do_apertures_overlap(struct fb_info *gen, struct fb_info *hw)
+{
+        /* is the generic aperture base the same as the HW one */
+        if (gen->aperture_base == hw->aperture_base)
+                return true;
+        /* is the generic aperture base inside the hw base->hw base+size */
+        if (gen->aperture_base > hw->aperture_base && gen->aperture_base <= hw->aperture_base + hw->aperture_size)
+                return true;
+        return false;
+}
 /**
  *      register_framebuffer - registers a frame buffer device
  *      @fb_info: frame buffer info structure
@@ -1485,6 +1495,23 @@ register_framebuffer(struct fb_info *fb_info)
         if (fb_check_foreignness(fb_info))
                 return -ENOSYS;
 
+        /* check all firmware fbs and kick off if the base addr overlaps */
+        for (i = 0 ; i < FB_MAX; i++) {
+                if (!registered_fb[i])
+                        continue;
+
+                if (registered_fb[i]->flags & FBINFO_MISC_FIRMWARE) {
+                        if (fb_do_apertures_overlap(registered_fb[i], fb_info)) {
+                                printk(KERN_ERR "fb: conflicting fb hw usage "
+                                       "%s vs %s - removing generic driver\n",
+                                       fb_info->fix.id,
+                                       registered_fb[i]->fix.id);
+                                unregister_framebuffer(registered_fb[i]);
+                                break;
+                        }
+                }
+        }
+
         num_registered_fb++;
         for (i = 0 ; i < FB_MAX; i++)
                 if (!registered_fb[i])
@@ -1586,6 +1613,10 @@ unregister_framebuffer(struct fb_info *fb_info)
         device_destroy(fb_class, MKDEV(FB_MAJOR, i));
         event.info = fb_info;
         fb_notifier_call_chain(FB_EVENT_FB_UNREGISTERED, &event);
+
+        /* this may free fb info */
+        if (fb_info->fbops->fb_destroy)
+                fb_info->fbops->fb_destroy(fb_info);
 done:
         return ret;
 }
diff --git a/drivers/video/igafb.c b/drivers/video/igafb.c
index 3a81060137a2..15d200109446 100644
--- a/drivers/video/igafb.c
+++ b/drivers/video/igafb.c
@@ -395,17 +395,16 @@ int __init igafb_init(void)
         /* We leak a reference here but as it cannot be unloaded this is
            fine. If you write unload code remember to free it in unload */
         
-        size = sizeof(struct fb_info) + sizeof(struct iga_par) + sizeof(u32)*16;
+        size = sizeof(struct iga_par) + sizeof(u32)*16;
 
-        info = kzalloc(size, GFP_ATOMIC);
+        info = framebuffer_alloc(size, &pdev->dev);
         if (!info) {
                 printk("igafb_init: can't alloc fb_info\n");
                  pci_dev_put(pdev);
                 return -ENOMEM;
         }
 
-        par = (struct iga_par *) (info + 1);
-        
+        par = info->par;
 
         if ((addr = pdev->resource[0].start) == 0) {
                 printk("igafb_init: no memory start\n");
@@ -526,7 +525,6 @@ int __init igafb_init(void)
         info->var = default_var;
         info->fix = igafb_fix;
         info->pseudo_palette = (void *)(par + 1);
-        info->device = &pdev->dev;
 
         if (!iga_init(info, par)) {
                 iounmap((void *)par->io_base);
diff --git a/drivers/video/intelfb/intelfbdrv.c b/drivers/video/intelfb/intelfbdrv.c
index ace14fe02fc4..0cafd642fbc0 100644
--- a/drivers/video/intelfb/intelfbdrv.c
+++ b/drivers/video/intelfb/intelfbdrv.c
@@ -1365,6 +1365,11 @@ static int intelfb_set_par(struct fb_info *info)
         DBG_MSG("intelfb_set_par (%dx%d-%d)\n", info->var.xres,
                 info->var.yres, info->var.bits_per_pixel);
 
+        /*
+         * Disable VCO prior to timing register change.
+         */
+        OUTREG(DPLL_A, INREG(DPLL_A) & ~DPLL_VCO_ENABLE);
+
         intelfb_blank(FB_BLANK_POWERDOWN, info);
 
         if (ACCEL(dinfo, info))
diff --git a/drivers/video/logo/Makefile b/drivers/video/logo/Makefile
index b91251d1fe41..3b437813584c 100644
--- a/drivers/video/logo/Makefile
+++ b/drivers/video/logo/Makefile
@@ -37,22 +37,24 @@ extra-y += $(call logo-cfiles,_clut224,ppm)
 # Gray 256
 extra-y += $(call logo-cfiles,_gray256,pgm)
 
+pnmtologo := scripts/pnmtologo
+
 # Create commands like "pnmtologo -t mono -n logo_mac_mono -o ..."
 quiet_cmd_logo = LOGO    $@
-        cmd_logo = scripts/pnmtologo \
+        cmd_logo = $(pnmtologo) \
                         -t $(patsubst $*_%,%,$(notdir $(basename $<))) \
                         -n $(notdir $(basename $<)) -o $@ $<
 
-$(obj)/%_mono.c: $(src)/%_mono.pbm FORCE
+$(obj)/%_mono.c: $(src)/%_mono.pbm $(pnmtologo) FORCE
         $(call if_changed,logo)
 
-$(obj)/%_vga16.c: $(src)/%_vga16.ppm FORCE
+$(obj)/%_vga16.c: $(src)/%_vga16.ppm $(pnmtologo) FORCE
         $(call if_changed,logo)
 
-$(obj)/%_clut224.c: $(src)/%_clut224.ppm FORCE
+$(obj)/%_clut224.c: $(src)/%_clut224.ppm $(pnmtologo) FORCE
         $(call if_changed,logo)
 
-$(obj)/%_gray256.c: $(src)/%_gray256.pgm FORCE
+$(obj)/%_gray256.c: $(src)/%_gray256.pgm $(pnmtologo) FORCE
         $(call if_changed,logo)
 
 # Files generated that shall be removed upon make clean
diff --git a/drivers/video/logo/logo.c b/drivers/video/logo/logo.c
index 2e85a2b52d05..ea7a8ccc830c 100644
--- a/drivers/video/logo/logo.c
+++ b/drivers/video/logo/logo.c
@@ -21,21 +21,6 @@
 #include <asm/bootinfo.h>
 #endif
 
-extern const struct linux_logo logo_linux_mono;
-extern const struct linux_logo logo_linux_vga16;
-extern const struct linux_logo logo_linux_clut224;
-extern const struct linux_logo logo_blackfin_vga16;
-extern const struct linux_logo logo_blackfin_clut224;
-extern const struct linux_logo logo_dec_clut224;
-extern const struct linux_logo logo_mac_clut224;
-extern const struct linux_logo logo_parisc_clut224;
-extern const struct linux_logo logo_sgi_clut224;
-extern const struct linux_logo logo_sun_clut224;
-extern const struct linux_logo logo_superh_mono;
-extern const struct linux_logo logo_superh_vga16;
-extern const struct linux_logo logo_superh_clut224;
-extern const struct linux_logo logo_m32r_clut224;
-
 static int nologo;
 module_param(nologo, bool, 0);
 MODULE_PARM_DESC(nologo, "Disables startup logo");
diff --git a/drivers/video/mb862xx/mb862xxfb.c b/drivers/video/mb862xx/mb862xxfb.c
index fb64234a3825..a28e3cfbbf70 100644
--- a/drivers/video/mb862xx/mb862xxfb.c
+++ b/drivers/video/mb862xx/mb862xxfb.c
@@ -19,7 +19,7 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/pci.h>
-#if defined(CONFIG_PPC_OF)
+#if defined(CONFIG_OF)
 #include <linux/of_platform.h>
 #endif
 #include "mb862xxfb.h"
diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c
index 16186240c5f2..34e4e7995169 100644
--- a/drivers/video/modedb.c
+++ b/drivers/video/modedb.c
@@ -264,6 +264,14 @@ static const struct fb_videomode modedb[] = {
         /* 1280x800, 60 Hz, 47.403 kHz hsync, WXGA 16:10 aspect ratio */
         NULL, 60, 1280, 800, 12048, 200, 64, 24, 1, 136, 3,
         0, FB_VMODE_NONINTERLACED
+    }, {
+       /* 720x576i @ 50 Hz, 15.625 kHz hsync (PAL RGB) */
+       NULL, 50, 720, 576, 74074, 64, 16, 39, 5, 64, 5,
+       0, FB_VMODE_INTERLACED
+    }, {
+       /* 800x520i @ 50 Hz, 15.625 kHz hsync (PAL RGB) */
+       NULL, 50, 800, 520, 58823, 144, 64, 72, 28, 80, 5,
+       0, FB_VMODE_INTERLACED
     },
 };
 
diff --git a/drivers/video/offb.c b/drivers/video/offb.c
index e1d9eeb1aeaf..4d8c54c23dd7 100644
--- a/drivers/video/offb.c
+++ b/drivers/video/offb.c
@@ -378,7 +378,6 @@ static void __init offb_init_fb(const char *name, const char *full_name,
         struct fb_fix_screeninfo *fix;
         struct fb_var_screeninfo *var;
         struct fb_info *info;
-        int size;
 
         if (!request_mem_region(res_start, res_size, "offb"))
                 return;
@@ -393,15 +392,12 @@ static void __init offb_init_fb(const char *name, const char *full_name,
                 return;
         }
 
-        size = sizeof(struct fb_info) + sizeof(u32) * 16;
-
-        info = kmalloc(size, GFP_ATOMIC);
+        info = framebuffer_alloc(sizeof(u32) * 16, NULL);
         
         if (info == 0) {
                 release_mem_region(res_start, res_size);
                 return;
         }
-        memset(info, 0, size);
 
         fix = &info->fix;
         var = &info->var;
@@ -497,7 +493,7 @@ static void __init offb_init_fb(const char *name, const char *full_name,
                 iounmap(par->cmap_adr);
                 par->cmap_adr = NULL;
                 iounmap(info->screen_base);
-                kfree(info);
+                framebuffer_release(info);
                 release_mem_region(res_start, res_size);
                 return;
         }
diff --git a/drivers/video/pm2fb.c b/drivers/video/pm2fb.c
index c6dd924976a4..36436ee6c1a4 100644
--- a/drivers/video/pm2fb.c
+++ b/drivers/video/pm2fb.c
@@ -1748,7 +1748,7 @@ static void __devexit pm2fb_remove(struct pci_dev *pdev)
         pci_set_drvdata(pdev, NULL);
         fb_dealloc_cmap(&info->cmap);
         kfree(info->pixmap.addr);
-        kfree(info);
+        framebuffer_release(info);
 }
 
 static struct pci_device_id pm2fb_id_table[] = {
diff --git a/drivers/video/s1d13xxxfb.c b/drivers/video/s1d13xxxfb.c
index 0726aecf3b7e..0deb0a8867b7 100644
--- a/drivers/video/s1d13xxxfb.c
+++ b/drivers/video/s1d13xxxfb.c
@@ -2,6 +2,7 @@
  *
  * (c) 2004 Simtec Electronics
  * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
+ * (c) 2009 Kristoffer Ericson <kristoffer.ericson@gmail.com>
  *
  * Driver for Epson S1D13xxx series framebuffer chips
  *
@@ -10,18 +11,10 @@
  *  linux/drivers/video/epson1355fb.c
  *  linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson)
  *
- * Note, currently only tested on S1D13806 with 16bit CRT.
- * As such, this driver might still contain some hardcoded bits relating to
- * S1D13806.
- * Making it work on other S1D13XXX chips should merely be a matter of adding
- * a few switch()s, some missing glue here and there maybe, and split header
- * files.
- *
  * TODO: - handle dual screen display (CRT and LCD at the same time).
  *       - check_var(), mode change, etc.
- *       - PM untested.
- *       - Accelerated interfaces.
- *       - Probably not SMP safe :)
+ *       - probably not SMP safe :)
+ *       - support all bitblt operations on all cards
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License. See the file COPYING in the main directory of this archive for
@@ -31,19 +24,24 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
-
 #include <linux/types.h>
 #include <linux/errno.h>
 #include <linux/mm.h>
 #include <linux/mman.h>
 #include <linux/fb.h>
+#include <linux/spinlock_types.h>
+#include <linux/spinlock.h>
 
 #include <asm/io.h>
 
 #include <video/s1d13xxxfb.h>
 
-#define PFX "s1d13xxxfb: "
+#define PFX     "s1d13xxxfb: "
+#define BLIT    "s1d13xxxfb_bitblt: "
 
+/*
+ * set this to enable debugging on general functions
+ */
 #if 0
 #define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0)
 #else
@@ -51,7 +49,21 @@
 #endif
 
 /*
- * List of card production ids
+ * set this to enable debugging on 2D acceleration
+ */
+#if 0
+#define dbg_blit(fmt, args...) do { printk(KERN_INFO BLIT fmt, ## args); } while (0)
+#else
+#define dbg_blit(fmt, args...) do { } while (0)
+#endif
+
+/*
+ * we make sure only one bitblt operation is running
+ */
+static DEFINE_SPINLOCK(s1d13xxxfb_bitblt_lock);
+
+/*
+ * list of card production ids
  */
 static const int s1d13xxxfb_prod_ids[] = {
         S1D13505_PROD_ID,
@@ -69,7 +81,7 @@ static const char *s1d13xxxfb_prod_names[] = {
 };
 
 /*
- * Here we define the default struct fb_fix_screeninfo
+ * here we define the default struct fb_fix_screeninfo
  */
 static struct fb_fix_screeninfo __devinitdata s1d13xxxfb_fix = {
         .id             = S1D_FBID,
@@ -145,8 +157,10 @@ crt_enable(struct s1d13xxxfb_par *par, int enable)
         s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
 }
 
-/* framebuffer control routines */
 
+/*************************************************************
+ framebuffer control functions
+ *************************************************************/
 static inline void
 s1d13xxxfb_setup_pseudocolour(struct fb_info *info)
 {
@@ -242,13 +256,13 @@ s1d13xxxfb_set_par(struct fb_info *info)
 }
 
 /**
- *      s1d13xxxfb_setcolreg - sets a color register.
- *      @regno: Which register in the CLUT we are programming
- *      @red: The red value which can be up to 16 bits wide
+ *      s1d13xxxfb_setcolreg - sets a color register.
+ *      @regno: Which register in the CLUT we are programming
+ *      @red: The red value which can be up to 16 bits wide
  *      @green: The green value which can be up to 16 bits wide
  *      @blue:  The blue value which can be up to 16 bits wide.
  *      @transp: If supported the alpha value which can be up to 16 bits wide.
- *      @info: frame buffer info structure
+ *      @info: frame buffer info structure
  *
  *      Returns negative errno on error, or zero on success.
  */
@@ -351,15 +365,15 @@ s1d13xxxfb_blank(int blank_mode, struct fb_info *info)
 }
 
 /**
- *      s1d13xxxfb_pan_display - Pans the display.
- *      @var: frame buffer variable screen structure
- *      @info: frame buffer structure that represents a single frame buffer
+ *      s1d13xxxfb_pan_display - Pans the display.
+ *      @var: frame buffer variable screen structure
+ *      @info: frame buffer structure that represents a single frame buffer
  *
  *      Pan (or wrap, depending on the `vmode' field) the display using the
- *      `yoffset' field of the `var' structure (`xoffset'  not yet supported).
- *      If the values don't fit, return -EINVAL.
+ *      `yoffset' field of the `var' structure (`xoffset'  not yet supported).
+ *      If the values don't fit, return -EINVAL.
  *
- *      Returns negative errno on error, or zero on success.
+ *      Returns negative errno on error, or zero on success.
  */
 static int
 s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
@@ -390,8 +404,259 @@ s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
         return 0;
 }
 
-/* framebuffer information structures */
+/************************************************************
+ functions to handle bitblt acceleration
+ ************************************************************/
+
+/**
+ *      bltbit_wait_bitset - waits for change in register value
+ *      @info : framebuffer structure
+ *      @bit  : value expected in register
+ *      @timeout : ...
+ *
+ *      waits until value changes INTO bit
+ */
+static u8
+bltbit_wait_bitset(struct fb_info *info, u8 bit, int timeout)
+{
+        while (!(s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit)) {
+                udelay(10);
+                if (!--timeout) {
+                        dbg_blit("wait_bitset timeout\n");
+                        break;
+                }
+        }
+
+        return timeout;
+}
+
+/**
+ *      bltbit_wait_bitclear - waits for change in register value
+ *      @info : frambuffer structure
+ *      @bit  : value currently in register
+ *      @timeout : ...
+ *
+ *      waits until value changes FROM bit
+ *
+ */
+static u8
+bltbit_wait_bitclear(struct fb_info *info, u8 bit, int timeout)
+{
+        while (s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0) & bit) {
+                udelay(10);
+                if (!--timeout) {
+                        dbg_blit("wait_bitclear timeout\n");
+                        break;
+                }
+        }
+
+        return timeout;
+}
+
+/**
+ *      bltbit_fifo_status - checks the current status of the fifo
+ *      @info : framebuffer structure
+ *
+ *      returns number of free words in buffer
+ */
+static u8
+bltbit_fifo_status(struct fb_info *info)
+{
+        u8 status;
 
+        status = s1d13xxxfb_readreg(info->par, S1DREG_BBLT_CTL0);
+
+        /* its empty so room for 16 words */
+        if (status & BBLT_FIFO_EMPTY)
+                return 16;
+
+        /* its full so we dont want to add */
+        if (status & BBLT_FIFO_FULL)
+                return 0;
+
+        /* its atleast half full but we can add one atleast */
+        if (status & BBLT_FIFO_NOT_FULL)
+                return 1;
+
+        return 0;
+}
+
+/*
+ *      s1d13xxxfb_bitblt_copyarea - accelerated copyarea function
+ *      @info : framebuffer structure
+ *      @area : fb_copyarea structure
+ *
+ *      supports (atleast) S1D13506
+ *
+ */
+static void
+s1d13xxxfb_bitblt_copyarea(struct fb_info *info, const struct fb_copyarea *area)
+{
+        u32 dst, src;
+        u32 stride;
+        u16 reverse = 0;
+        u16 sx = area->sx, sy = area->sy;
+        u16 dx = area->dx, dy = area->dy;
+        u16 width = area->width, height = area->height;
+        u16 bpp;
+
+        spin_lock(&s1d13xxxfb_bitblt_lock);
+
+        /* bytes per xres line */
+        bpp = (info->var.bits_per_pixel >> 3);
+        stride = bpp * info->var.xres;
+
+        /* reverse, calculate the last pixel in rectangle */
+        if ((dy > sy) || ((dy == sy) && (dx >= sx))) {
+                dst = (((dy + height - 1) * stride) + (bpp * (dx + width - 1)));
+                src = (((sy + height - 1) * stride) + (bpp * (sx + width - 1)));
+                reverse = 1;
+        /* not reverse, calculate the first pixel in rectangle */
+        } else { /* (y * xres) + (bpp * x) */
+                dst = (dy * stride) + (bpp * dx);
+                src = (sy * stride) + (bpp * sx);
+        }
+
+        /* set source adress */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START0, (src & 0xff));
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START1, (src >> 8) & 0x00ff);
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_SRC_START2, (src >> 16) & 0x00ff);
+
+        /* set destination adress */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dst & 0xff));
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, (dst >> 8) & 0x00ff);
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, (dst >> 16) & 0x00ff);
+
+        /* program height and width */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, (width & 0xff) - 1);
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (width >> 8));
+
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, (height & 0xff) - 1);
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (height >> 8));
+
+        /* negative direction ROP */
+        if (reverse == 1) {
+                dbg_blit("(copyarea) negative rop\n");
+                s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x03);
+        } else /* positive direction ROP */ {
+                s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, 0x02);
+                dbg_blit("(copyarea) positive rop\n");
+        }
+
+        /* set for rectangel mode and not linear */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
+
+        /* setup the bpp 1 = 16bpp, 0 = 8bpp*/
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (bpp >> 1));
+
+        /* set words per xres */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (stride >> 1) & 0xff);
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (stride >> 9));
+
+        dbg_blit("(copyarea) dx=%d, dy=%d\n", dx, dy);
+        dbg_blit("(copyarea) sx=%d, sy=%d\n", sx, sy);
+        dbg_blit("(copyarea) width=%d, height=%d\n", width - 1, height - 1);
+        dbg_blit("(copyarea) stride=%d\n", stride);
+        dbg_blit("(copyarea) bpp=%d=0x0%d, mem_offset1=%d, mem_offset2=%d\n", bpp, (bpp >> 1),
+                (stride >> 1) & 0xff, stride >> 9);
+
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CC_EXP, 0x0c);
+
+        /* initialize the engine */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
+
+        /* wait to complete */
+        bltbit_wait_bitclear(info, 0x80, 8000);
+
+        spin_unlock(&s1d13xxxfb_bitblt_lock);
+}
+
+/**
+ *
+ *      s1d13xxxfb_bitblt_solidfill - accelerated solidfill function
+ *      @info : framebuffer structure
+ *      @rect : fb_fillrect structure
+ *
+ *      supports (atleast 13506)
+ *
+ **/
+static void
+s1d13xxxfb_bitblt_solidfill(struct fb_info *info, const struct fb_fillrect *rect)
+{
+        u32 screen_stride, dest;
+        u32 fg;
+        u16 bpp = (info->var.bits_per_pixel >> 3);
+
+        /* grab spinlock */
+        spin_lock(&s1d13xxxfb_bitblt_lock);
+
+        /* bytes per x width */
+        screen_stride = (bpp * info->var.xres);
+
+        /* bytes to starting point */
+        dest = ((rect->dy * screen_stride) + (bpp * rect->dx));
+
+        dbg_blit("(solidfill) dx=%d, dy=%d, stride=%d, dest=%d\n"
+                 "(solidfill) : rect_width=%d, rect_height=%d\n",
+                                rect->dx, rect->dy, screen_stride, dest,
+                                rect->width - 1, rect->height - 1);
+
+        dbg_blit("(solidfill) : xres=%d, yres=%d, bpp=%d\n",
+                                info->var.xres, info->var.yres,
+                                info->var.bits_per_pixel);
+        dbg_blit("(solidfill) : rop=%d\n", rect->rop);
+
+        /* We split the destination into the three registers */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START0, (dest & 0x00ff));
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START1, ((dest >> 8) & 0x00ff));
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_DST_START2, ((dest >> 16) & 0x00ff));
+
+        /* give information regarding rectangel width */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH0, ((rect->width) & 0x00ff) - 1);
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_WIDTH1, (rect->width >> 8));
+
+        /* give information regarding rectangel height */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT0, ((rect->height) & 0x00ff) - 1);
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_HEIGHT1, (rect->height >> 8));
+
+        if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
+                info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
+                fg = ((u32 *)info->pseudo_palette)[rect->color];
+                dbg_blit("(solidfill) truecolor/directcolor\n");
+                dbg_blit("(solidfill) pseudo_palette[%d] = %d\n", rect->color, fg);
+        } else {
+                fg = rect->color;
+                dbg_blit("(solidfill) color = %d\n", rect->color);
+        }
+
+        /* set foreground color */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC0, (fg & 0xff));
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_FGC1, (fg >> 8) & 0xff);
+
+        /* set rectangual region of memory (rectangle and not linear) */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x0);
+
+        /* set operation mode SOLID_FILL */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_OP, BBLT_SOLID_FILL);
+
+        /* set bits per pixel (1 = 16bpp, 0 = 8bpp) */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (info->var.bits_per_pixel >> 4));
+
+        /* set the memory offset for the bblt in word sizes */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF0, (screen_stride >> 1) & 0x00ff);
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_MEM_OFF1, (screen_stride >> 9));
+
+        /* and away we go.... */
+        s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL0, 0x80);
+
+        /* wait until its done */
+        bltbit_wait_bitclear(info, 0x80, 8000);
+
+        /* let others play */
+        spin_unlock(&s1d13xxxfb_bitblt_lock);
+}
+
+/* framebuffer information structures */
 static struct fb_ops s1d13xxxfb_fbops = {
         .owner          = THIS_MODULE,
         .fb_set_par     = s1d13xxxfb_set_par,
@@ -400,7 +665,7 @@ static struct fb_ops s1d13xxxfb_fbops = {
 
         .fb_pan_display = s1d13xxxfb_pan_display,
 
-        /* to be replaced by any acceleration we can */
+        /* gets replaced at chip detection time */
         .fb_fillrect    = cfb_fillrect,
         .fb_copyarea    = cfb_copyarea,
         .fb_imageblit   = cfb_imageblit,
@@ -412,9 +677,9 @@ static int s1d13xxxfb_width_tab[2][4] __devinitdata = {
 };
 
 /**
- *      s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
+ *      s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
  *      hardware setup.
- *      @info: frame buffer structure
+ *      @info: frame buffer structure
  *
  *      We setup the framebuffer structures according to the current
  *      hardware setup. On some machines, the BIOS will have filled
@@ -569,7 +834,6 @@ s1d13xxxfb_probe(struct platform_device *pdev)
         if (pdata && pdata->platform_init_video)
                 pdata->platform_init_video();
 
-
         if (pdev->num_resources != 2) {
                 dev_err(&pdev->dev, "invalid num_resources: %i\n",
                        pdev->num_resources);
@@ -655,16 +919,27 @@ s1d13xxxfb_probe(struct platform_device *pdev)
 
         info->fix = s1d13xxxfb_fix;
         info->fix.mmio_start = pdev->resource[1].start;
-        info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start +1;
+        info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start + 1;
         info->fix.smem_start = pdev->resource[0].start;
-        info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start +1;
+        info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start + 1;
 
         printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n",
                default_par->regs, info->fix.smem_len / 1024, info->screen_base);
 
         info->par = default_par;
-        info->fbops = &s1d13xxxfb_fbops;
         info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
+        info->fbops = &s1d13xxxfb_fbops;
+
+        switch(prod_id) {
+        case S1D13506_PROD_ID:  /* activate acceleration */
+                s1d13xxxfb_fbops.fb_fillrect = s1d13xxxfb_bitblt_solidfill;
+                s1d13xxxfb_fbops.fb_copyarea = s1d13xxxfb_bitblt_copyarea;
+                info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
+                        FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_COPYAREA;
+                break;
+        default:
+                break;
+        }
 
         /* perform "manual" chip initialization, if needed */
         if (pdata && pdata->initregs)
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index d3a568e6b169..43680e545427 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -358,9 +358,16 @@ static int s3c_fb_set_par(struct fb_info *info)
         writel(data, regs + VIDOSD_B(win_no));
 
         data = var->xres * var->yres;
+
+        u32 osdc_data = 0;
+
+        osdc_data = VIDISD14C_ALPHA1_R(0xf) |
+                VIDISD14C_ALPHA1_G(0xf) |
+                VIDISD14C_ALPHA1_B(0xf);
+
         if (s3c_fb_has_osd_d(win_no)) {
                 writel(data, regs + VIDOSD_D(win_no));
-                writel(0, regs + VIDOSD_C(win_no));
+                writel(osdc_data, regs + VIDOSD_C(win_no));
         } else
                 writel(data, regs + VIDOSD_C(win_no));
 
@@ -409,8 +416,12 @@ static int s3c_fb_set_par(struct fb_info *info)
                                 data |= WINCON1_BPPMODE_19BPP_A1666;
                         else
                                 data |= WINCON1_BPPMODE_18BPP_666;
-                } else if (var->transp.length != 0)
-                        data |= WINCON1_BPPMODE_25BPP_A1888;
+                } else if (var->transp.length == 1)
+                        data |= WINCON1_BPPMODE_25BPP_A1888
+                                | WINCON1_BLD_PIX;
+                else if (var->transp.length == 4)
+                        data |= WINCON1_BPPMODE_28BPP_A4888
+                                | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
                 else
                         data |= WINCON0_BPPMODE_24BPP_888;
 
@@ -418,6 +429,20 @@ static int s3c_fb_set_par(struct fb_info *info)
                 break;
         }
 
+        /* It has no color key control register for window0 */
+        if (win_no > 0) {
+                u32 keycon0_data = 0, keycon1_data = 0;
+
+                keycon0_data = ~(WxKEYCON0_KEYBL_EN |
+                                WxKEYCON0_KEYEN_F |
+                                WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
+
+                keycon1_data = WxKEYCON1_COLVAL(0xffffff);
+
+                writel(keycon0_data, regs + WxKEYCONy(win_no-1, 0));
+                writel(keycon1_data, regs + WxKEYCONy(win_no-1, 1));
+        }
+
         writel(data, regs + WINCON(win_no));
         writel(0x0, regs + WINxMAP(win_no));
 
@@ -700,9 +725,12 @@ static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
  */
 static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
 {
-        fb_dealloc_cmap(&win->fbinfo->cmap);
-        unregister_framebuffer(win->fbinfo);
-        s3c_fb_free_memory(sfb, win);
+        if (win->fbinfo) {
+                unregister_framebuffer(win->fbinfo);
+                fb_dealloc_cmap(&win->fbinfo->cmap);
+                s3c_fb_free_memory(sfb, win);
+                framebuffer_release(win->fbinfo);
+        }
 }
 
 /**
@@ -753,7 +781,7 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
         ret = s3c_fb_alloc_memory(sfb, win);
         if (ret) {
                 dev_err(sfb->dev, "failed to allocate display memory\n");
-                goto err_framebuffer;
+                return ret;
         }
 
         /* setup the r/b/g positions for the window's palette */
@@ -776,7 +804,7 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
         ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
         if (ret < 0) {
                 dev_err(sfb->dev, "check_var failed on initial video params\n");
-                goto err_alloc_mem;
+                return ret;
         }
 
         /* create initial colour map */
@@ -796,20 +824,13 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
         ret = register_framebuffer(fbinfo);
         if (ret < 0) {
                 dev_err(sfb->dev, "failed to register framebuffer\n");
-                goto err_alloc_mem;
+                return ret;
         }
 
         *res = win;
         dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
 
         return 0;
-
-err_alloc_mem:
-        s3c_fb_free_memory(sfb, win);
-
-err_framebuffer:
-        unregister_framebuffer(fbinfo);
-        return ret;
 }
 
 /**
diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c
index b0b4513ba537..7da0027e2409 100644
--- a/drivers/video/s3c2410fb.c
+++ b/drivers/video/s3c2410fb.c
@@ -24,6 +24,7 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/cpufreq.h>
 
 #include <asm/io.h>
 #include <asm/div64.h>
@@ -89,7 +90,7 @@ static void s3c2410fb_set_lcdaddr(struct fb_info *info)
 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
                                           unsigned long pixclk)
 {
-        unsigned long clk = clk_get_rate(fbi->clk);
+        unsigned long clk = fbi->clk_rate;
         unsigned long long div;
 
         /* pixclk is in picoseconds, our clock is in Hz
@@ -758,6 +759,57 @@ static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
+#ifdef CONFIG_CPU_FREQ
+
+static int s3c2410fb_cpufreq_transition(struct notifier_block *nb,
+                                        unsigned long val, void *data)
+{
+        struct cpufreq_freqs *freqs = data;
+        struct s3c2410fb_info *info;
+        struct fb_info *fbinfo;
+        long delta_f;
+
+        info = container_of(nb, struct s3c2410fb_info, freq_transition);
+        fbinfo = platform_get_drvdata(to_platform_device(info->dev));
+
+        /* work out change, <0 for speed-up */
+        delta_f = info->clk_rate - clk_get_rate(info->clk);
+
+        if ((val == CPUFREQ_POSTCHANGE && delta_f > 0) ||
+            (val == CPUFREQ_PRECHANGE && delta_f < 0)) {
+                info->clk_rate = clk_get_rate(info->clk);
+                s3c2410fb_activate_var(fbinfo);
+        }
+
+        return 0;
+}
+
+static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
+{
+        info->freq_transition.notifier_call = s3c2410fb_cpufreq_transition;
+
+        return cpufreq_register_notifier(&info->freq_transition,
+                                         CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
+{
+        cpufreq_unregister_notifier(&info->freq_transition,
+                                    CPUFREQ_TRANSITION_NOTIFIER);
+}
+
+#else
+static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
+{
+        return 0;
+}
+
+static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
+{
+}
+#endif
+
+
 static char driver_name[] = "s3c2410fb";
 
 static int __init s3c24xxfb_probe(struct platform_device *pdev,
@@ -875,6 +927,8 @@ static int __init s3c24xxfb_probe(struct platform_device *pdev,
 
         msleep(1);
 
+        info->clk_rate = clk_get_rate(info->clk);
+
         /* find maximum required memory size for display */
         for (i = 0; i < mach_info->num_displays; i++) {
                 unsigned long smem_len = mach_info->displays[i].xres;
@@ -904,11 +958,17 @@ static int __init s3c24xxfb_probe(struct platform_device *pdev,
 
         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 
+        ret = s3c2410fb_cpufreq_register(info);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "Failed to register cpufreq\n");
+                goto free_video_memory;
+        }
+
         ret = register_framebuffer(fbinfo);
         if (ret < 0) {
                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
                         ret);
-                goto free_video_memory;
+                goto free_cpufreq;
         }
 
         /* create device files */
@@ -922,6 +982,8 @@ static int __init s3c24xxfb_probe(struct platform_device *pdev,
 
         return 0;
 
+ free_cpufreq:
+        s3c2410fb_cpufreq_deregister(info);
 free_video_memory:
         s3c2410fb_unmap_video_memory(fbinfo);
 release_clock:
@@ -961,6 +1023,7 @@ static int s3c2410fb_remove(struct platform_device *pdev)
         int irq;
 
         unregister_framebuffer(fbinfo);
+        s3c2410fb_cpufreq_deregister(info);
 
         s3c2410fb_lcd_enable(info, 0);
         msleep(1);
diff --git a/drivers/video/s3c2410fb.h b/drivers/video/s3c2410fb.h
index 9a6ba3e9d1b8..47a17bd23011 100644
--- a/drivers/video/s3c2410fb.h
+++ b/drivers/video/s3c2410fb.h
@@ -29,8 +29,13 @@ struct s3c2410fb_info {
         enum s3c_drv_type       drv_type;
         struct s3c2410fb_hw     regs;
 
+        unsigned long           clk_rate;
         unsigned int            palette_ready;
 
+#ifdef CONFIG_CPU_FREQ
+        struct notifier_block   freq_transition;
+#endif
+
         /* keep these registers in case we need to re-write palette */
         u32                     palette_buffer[256];
         u32                     pseudo_pal[16];
diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c
index 7e17ee95a97a..7072d19080d5 100644
--- a/drivers/video/sis/sis_main.c
+++ b/drivers/video/sis/sis_main.c
@@ -5928,7 +5928,7 @@ sisfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 if(pci_enable_device(pdev)) {
                         if(ivideo->nbridge) pci_dev_put(ivideo->nbridge);
                         pci_set_drvdata(pdev, NULL);
-                        kfree(sis_fb_info);
+                        framebuffer_release(sis_fb_info);
                         return -EIO;
                 }
         }
@@ -6134,7 +6134,7 @@ error_3:	vfree(ivideo->bios_abase);
                 pci_set_drvdata(pdev, NULL);
                 if(!ivideo->sisvga_enabled)
                         pci_disable_device(pdev);
-                kfree(sis_fb_info);
+                framebuffer_release(sis_fb_info);
                 return ret;
         }
 
diff --git a/drivers/video/stifb.c b/drivers/video/stifb.c
index eabaad765aeb..eec9dcb7f599 100644
--- a/drivers/video/stifb.c
+++ b/drivers/video/stifb.c
@@ -1380,7 +1380,7 @@ stifb_cleanup(void)
                                 if (info->screen_base)
                                         iounmap(info->screen_base);
                         fb_dealloc_cmap(&info->cmap);
-                        kfree(info); 
+                        framebuffer_release(info);
                 }
                 sti->info = NULL;
         }
diff --git a/drivers/video/tcx.c b/drivers/video/tcx.c
index 643afbfe8277..45b883598bf0 100644
--- a/drivers/video/tcx.c
+++ b/drivers/video/tcx.c
@@ -116,17 +116,16 @@ struct tcx_par {
         u32                     flags;
 #define TCX_FLAG_BLANKED        0x00000001
 
-        unsigned long           physbase;
         unsigned long           which_io;
-        unsigned long           fbsize;
 
         struct sbus_mmap_map    mmap_map[TCX_MMAP_ENTRIES];
         int                     lowdepth;
 };
 
 /* Reset control plane so that WID is 8-bit plane. */
-static void __tcx_set_control_plane(struct tcx_par *par)
+static void __tcx_set_control_plane(struct fb_info *info)
 {
+        struct tcx_par *par = info->par;
         u32 __iomem *p, *pend;
 
         if (par->lowdepth)
@@ -135,7 +134,7 @@ static void __tcx_set_control_plane(struct tcx_par *par)
         p = par->cplane;
         if (p == NULL)
                 return;
-        for (pend = p + par->fbsize; p < pend; p++) {
+        for (pend = p + info->fix.smem_len; p < pend; p++) {
                 u32 tmp = sbus_readl(p);
 
                 tmp &= 0xffffff;
@@ -149,7 +148,7 @@ static void tcx_reset(struct fb_info *info)
         unsigned long flags;
 
         spin_lock_irqsave(&par->lock, flags);
-        __tcx_set_control_plane(par);
+        __tcx_set_control_plane(info);
         spin_unlock_irqrestore(&par->lock, flags);
 }
 
@@ -304,7 +303,7 @@ static int tcx_mmap(struct fb_info *info, struct vm_area_struct *vma)
         struct tcx_par *par = (struct tcx_par *)info->par;
 
         return sbusfb_mmap_helper(par->mmap_map,
-                                  par->physbase, par->fbsize,
+                                  info->fix.smem_start, info->fix.smem_len,
                                   par->which_io, vma);
 }
 
@@ -316,7 +315,7 @@ static int tcx_ioctl(struct fb_info *info, unsigned int cmd,
         return sbusfb_ioctl_helper(cmd, arg, info,
                                    FBTYPE_TCXCOLOR,
                                    (par->lowdepth ? 8 : 24),
-                                   par->fbsize);
+                                   info->fix.smem_len);
 }
 
 /*
@@ -358,10 +357,10 @@ static void tcx_unmap_regs(struct of_device *op, struct fb_info *info,
                            par->bt, sizeof(struct bt_regs));
         if (par->cplane)
                 of_iounmap(&op->resource[4],
-                           par->cplane, par->fbsize * sizeof(u32));
+                           par->cplane, info->fix.smem_len * sizeof(u32));
         if (info->screen_base)
                 of_iounmap(&op->resource[0],
-                           info->screen_base, par->fbsize);
+                           info->screen_base, info->fix.smem_len);
 }
 
 static int __devinit tcx_probe(struct of_device *op,
@@ -391,7 +390,7 @@ static int __devinit tcx_probe(struct of_device *op,
 
         linebytes = of_getintprop_default(dp, "linebytes",
                                           info->var.xres);
-        par->fbsize = PAGE_ALIGN(linebytes * info->var.yres);
+        info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
 
         par->tec = of_ioremap(&op->resource[7], 0,
                                   sizeof(struct tcx_tec), "tcx tec");
@@ -400,7 +399,7 @@ static int __devinit tcx_probe(struct of_device *op,
         par->bt = of_ioremap(&op->resource[8], 0,
                                  sizeof(struct bt_regs), "tcx dac");
         info->screen_base = of_ioremap(&op->resource[0], 0,
-                                           par->fbsize, "tcx ram");
+                                           info->fix.smem_len, "tcx ram");
         if (!par->tec || !par->thc ||
             !par->bt || !info->screen_base)
                 goto out_unmap_regs;
@@ -408,7 +407,7 @@ static int __devinit tcx_probe(struct of_device *op,
         memcpy(&par->mmap_map, &__tcx_mmap_map, sizeof(par->mmap_map));
         if (!par->lowdepth) {
                 par->cplane = of_ioremap(&op->resource[4], 0,
-                                             par->fbsize * sizeof(u32),
+                                             info->fix.smem_len * sizeof(u32),
                                              "tcx cplane");
                 if (!par->cplane)
                         goto out_unmap_regs;
@@ -419,7 +418,7 @@ static int __devinit tcx_probe(struct of_device *op,
                 par->mmap_map[6].size = SBUS_MMAP_EMPTY;
         }
 
-        par->physbase = op->resource[0].start;
+        info->fix.smem_start = op->resource[0].start;
         par->which_io = op->resource[0].flags & IORESOURCE_BITS;
 
         for (i = 0; i < TCX_MMAP_ENTRIES; i++) {
@@ -473,7 +472,7 @@ static int __devinit tcx_probe(struct of_device *op,
         printk(KERN_INFO "%s: TCX at %lx:%lx, %s\n",
                dp->full_name,
                par->which_io,
-               par->physbase,
+               info->fix.smem_start,
                par->lowdepth ? "8-bit only" : "24-bit depth");
 
         return 0;
diff --git a/drivers/video/vesafb.c b/drivers/video/vesafb.c
index d6856f43d241..bd37ee1f6a25 100644
--- a/drivers/video/vesafb.c
+++ b/drivers/video/vesafb.c
@@ -174,8 +174,17 @@ static int vesafb_setcolreg(unsigned regno, unsigned red, unsigned green,
         return err;
 }
 
+static void vesafb_destroy(struct fb_info *info)
+{
+        if (info->screen_base)
+                iounmap(info->screen_base);
+        release_mem_region(info->aperture_base, info->aperture_size);
+        framebuffer_release(info);
+}
+
 static struct fb_ops vesafb_ops = {
         .owner          = THIS_MODULE,
+        .fb_destroy     = vesafb_destroy,
         .fb_setcolreg   = vesafb_setcolreg,
         .fb_pan_display = vesafb_pan_display,
         .fb_fillrect    = cfb_fillrect,
@@ -286,6 +295,10 @@ static int __init vesafb_probe(struct platform_device *dev)
         info->pseudo_palette = info->par;
         info->par = NULL;
 
+        /* set vesafb aperture size for generic probing */
+        info->aperture_base = screen_info.lfb_base;
+        info->aperture_size = size_total;
+
         info->screen_base = ioremap(vesafb_fix.smem_start, vesafb_fix.smem_len);
         if (!info->screen_base) {
                 printk(KERN_ERR
@@ -437,7 +450,7 @@ static int __init vesafb_probe(struct platform_device *dev)
         info->fbops = &vesafb_ops;
         info->var = vesafb_defined;
         info->fix = vesafb_fix;
-        info->flags = FBINFO_FLAG_DEFAULT |
+        info->flags = FBINFO_FLAG_DEFAULT | FBINFO_MISC_FIRMWARE |
                 (ypan ? FBINFO_HWACCEL_YPAN : 0);
 
         if (!ypan)
diff --git a/drivers/video/xen-fbfront.c b/drivers/video/xen-fbfront.c
index 2493f05e9f61..15502d5e3641 100644
--- a/drivers/video/xen-fbfront.c
+++ b/drivers/video/xen-fbfront.c
@@ -384,7 +384,7 @@ static int __devinit xenfb_probe(struct xenbus_device *dev,
                 fb_size = XENFB_DEFAULT_FB_LEN;
         }
 
-        dev->dev.driver_data = info;
+        dev_set_drvdata(&dev->dev, info);
         info->xbdev = dev;
         info->irq = -1;
         info->x1 = info->y1 = INT_MAX;
@@ -503,7 +503,7 @@ xenfb_make_preferred_console(void)
 
 static int xenfb_resume(struct xenbus_device *dev)
 {
-        struct xenfb_info *info = dev->dev.driver_data;
+        struct xenfb_info *info = dev_get_drvdata(&dev->dev);
 
         xenfb_disconnect_backend(info);
         xenfb_init_shared_page(info, info->fb_info);
@@ -512,7 +512,7 @@ static int xenfb_resume(struct xenbus_device *dev)
 
 static int xenfb_remove(struct xenbus_device *dev)
 {
-        struct xenfb_info *info = dev->dev.driver_data;
+        struct xenfb_info *info = dev_get_drvdata(&dev->dev);
 
         xenfb_disconnect_backend(info);
         if (info->fb_info) {
@@ -621,7 +621,7 @@ static void xenfb_disconnect_backend(struct xenfb_info *info)
 static void xenfb_backend_changed(struct xenbus_device *dev,
                                   enum xenbus_state backend_state)
 {
-        struct xenfb_info *info = dev->dev.driver_data;
+        struct xenfb_info *info = dev_get_drvdata(&dev->dev);
         int val;
 
         switch (backend_state) {
diff --git a/drivers/vlynq/Kconfig b/drivers/vlynq/Kconfig
new file mode 100644
index 000000000000..f6542211db48
--- /dev/null
+++ b/drivers/vlynq/Kconfig
@@ -0,0 +1,20 @@
+menu "TI VLYNQ"
+
+config VLYNQ
+        bool "TI VLYNQ bus support"
+        depends on AR7 && EXPERIMENTAL
+        help
+          Support for Texas Instruments(R) VLYNQ bus.
+          The VLYNQ bus is a high-speed, serial and packetized
+          data bus which allows external peripherals of a SoC
+          to appear into the system's main memory.
+
+          If unsure, say N
+
+config VLYNQ_DEBUG
+        bool "VLYNQ bus debug"
+        depends on VLYNQ && KERNEL_DEBUG
+        help
+          Turn on VLYNQ bus debugging.
+
+endmenu
diff --git a/drivers/vlynq/Makefile b/drivers/vlynq/Makefile
new file mode 100644
index 000000000000..b3f61149b599
--- /dev/null
+++ b/drivers/vlynq/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for kernel vlynq drivers
+#
+
+obj-$(CONFIG_VLYNQ) += vlynq.o
diff --git a/drivers/vlynq/vlynq.c b/drivers/vlynq/vlynq.c
new file mode 100644
index 000000000000..7335433b067b
--- /dev/null
+++ b/drivers/vlynq/vlynq.c
@@ -0,0 +1,814 @@
+/*
+ * Copyright (C) 2006, 2007 Eugene Konev <ejka@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * Parts of the VLYNQ specification can be found here:
+ * http://www.ti.com/litv/pdf/sprue36a
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <linux/vlynq.h>
+
+#define VLYNQ_CTRL_PM_ENABLE            0x80000000
+#define VLYNQ_CTRL_CLOCK_INT            0x00008000
+#define VLYNQ_CTRL_CLOCK_DIV(x)         (((x) & 7) << 16)
+#define VLYNQ_CTRL_INT_LOCAL            0x00004000
+#define VLYNQ_CTRL_INT_ENABLE           0x00002000
+#define VLYNQ_CTRL_INT_VECTOR(x)        (((x) & 0x1f) << 8)
+#define VLYNQ_CTRL_INT2CFG              0x00000080
+#define VLYNQ_CTRL_RESET                0x00000001
+
+#define VLYNQ_CTRL_CLOCK_MASK          (0x7 << 16)
+
+#define VLYNQ_INT_OFFSET                0x00000014
+#define VLYNQ_REMOTE_OFFSET             0x00000080
+
+#define VLYNQ_STATUS_LINK               0x00000001
+#define VLYNQ_STATUS_LERROR             0x00000080
+#define VLYNQ_STATUS_RERROR             0x00000100
+
+#define VINT_ENABLE                     0x00000100
+#define VINT_TYPE_EDGE                  0x00000080
+#define VINT_LEVEL_LOW                  0x00000040
+#define VINT_VECTOR(x)                  ((x) & 0x1f)
+#define VINT_OFFSET(irq)                (8 * ((irq) % 4))
+
+#define VLYNQ_AUTONEGO_V2               0x00010000
+
+struct vlynq_regs {
+        u32 revision;
+        u32 control;
+        u32 status;
+        u32 int_prio;
+        u32 int_status;
+        u32 int_pending;
+        u32 int_ptr;
+        u32 tx_offset;
+        struct vlynq_mapping rx_mapping[4];
+        u32 chip;
+        u32 autonego;
+        u32 unused[6];
+        u32 int_device[8];
+};
+
+#ifdef VLYNQ_DEBUG
+static void vlynq_dump_regs(struct vlynq_device *dev)
+{
+        int i;
+
+        printk(KERN_DEBUG "VLYNQ local=%p remote=%p\n",
+                        dev->local, dev->remote);
+        for (i = 0; i < 32; i++) {
+                printk(KERN_DEBUG "VLYNQ: local %d: %08x\n",
+                        i + 1, ((u32 *)dev->local)[i]);
+                printk(KERN_DEBUG "VLYNQ: remote %d: %08x\n",
+                        i + 1, ((u32 *)dev->remote)[i]);
+        }
+}
+
+static void vlynq_dump_mem(u32 *base, int count)
+{
+        int i;
+
+        for (i = 0; i < (count + 3) / 4; i++) {
+                if (i % 4 == 0)
+                        printk(KERN_DEBUG "\nMEM[0x%04x]:", i * 4);
+                printk(KERN_DEBUG " 0x%08x", *(base + i));
+        }
+        printk(KERN_DEBUG "\n");
+}
+#endif
+
+/* Check the VLYNQ link status with a given device */
+static int vlynq_linked(struct vlynq_device *dev)
+{
+        int i;
+
+        for (i = 0; i < 100; i++)
+                if (readl(&dev->local->status) & VLYNQ_STATUS_LINK)
+                        return 1;
+                else
+                        cpu_relax();
+
+        return 0;
+}
+
+static void vlynq_reset(struct vlynq_device *dev)
+{
+        writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET,
+                        &dev->local->control);
+
+        /* Wait for the devices to finish resetting */
+        msleep(5);
+
+        /* Remove reset bit */
+        writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET,
+                        &dev->local->control);
+
+        /* Give some time for the devices to settle */
+        msleep(5);
+}
+
+static void vlynq_irq_unmask(unsigned int irq)
+{
+        u32 val;
+        struct vlynq_device *dev = get_irq_chip_data(irq);
+        int virq;
+
+        BUG_ON(!dev);
+        virq = irq - dev->irq_start;
+        val = readl(&dev->remote->int_device[virq >> 2]);
+        val |= (VINT_ENABLE | virq) << VINT_OFFSET(virq);
+        writel(val, &dev->remote->int_device[virq >> 2]);
+}
+
+static void vlynq_irq_mask(unsigned int irq)
+{
+        u32 val;
+        struct vlynq_device *dev = get_irq_chip_data(irq);
+        int virq;
+
+        BUG_ON(!dev);
+        virq = irq - dev->irq_start;
+        val = readl(&dev->remote->int_device[virq >> 2]);
+        val &= ~(VINT_ENABLE << VINT_OFFSET(virq));
+        writel(val, &dev->remote->int_device[virq >> 2]);
+}
+
+static int vlynq_irq_type(unsigned int irq, unsigned int flow_type)
+{
+        u32 val;
+        struct vlynq_device *dev = get_irq_chip_data(irq);
+        int virq;
+
+        BUG_ON(!dev);
+        virq = irq - dev->irq_start;
+        val = readl(&dev->remote->int_device[virq >> 2]);
+        switch (flow_type & IRQ_TYPE_SENSE_MASK) {
+        case IRQ_TYPE_EDGE_RISING:
+        case IRQ_TYPE_EDGE_FALLING:
+        case IRQ_TYPE_EDGE_BOTH:
+                val |= VINT_TYPE_EDGE << VINT_OFFSET(virq);
+                val &= ~(VINT_LEVEL_LOW << VINT_OFFSET(virq));
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                val &= ~(VINT_TYPE_EDGE << VINT_OFFSET(virq));
+                val &= ~(VINT_LEVEL_LOW << VINT_OFFSET(virq));
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                val &= ~(VINT_TYPE_EDGE << VINT_OFFSET(virq));
+                val |= VINT_LEVEL_LOW << VINT_OFFSET(virq);
+                break;
+        default:
+                return -EINVAL;
+        }
+        writel(val, &dev->remote->int_device[virq >> 2]);
+        return 0;
+}
+
+static void vlynq_local_ack(unsigned int irq)
+{
+        struct vlynq_device *dev = get_irq_chip_data(irq);
+
+        u32 status = readl(&dev->local->status);
+
+        pr_debug("%s: local status: 0x%08x\n",
+                       dev_name(&dev->dev), status);
+        writel(status, &dev->local->status);
+}
+
+static void vlynq_remote_ack(unsigned int irq)
+{
+        struct vlynq_device *dev = get_irq_chip_data(irq);
+
+        u32 status = readl(&dev->remote->status);
+
+        pr_debug("%s: remote status: 0x%08x\n",
+                       dev_name(&dev->dev), status);
+        writel(status, &dev->remote->status);
+}
+
+static irqreturn_t vlynq_irq(int irq, void *dev_id)
+{
+        struct vlynq_device *dev = dev_id;
+        u32 status;
+        int virq = 0;
+
+        status = readl(&dev->local->int_status);
+        writel(status, &dev->local->int_status);
+
+        if (unlikely(!status))
+                spurious_interrupt();
+
+        while (status) {
+                if (status & 1)
+                        do_IRQ(dev->irq_start + virq);
+                status >>= 1;
+                virq++;
+        }
+
+        return IRQ_HANDLED;
+}
+
+static struct irq_chip vlynq_irq_chip = {
+        .name = "vlynq",
+        .unmask = vlynq_irq_unmask,
+        .mask = vlynq_irq_mask,
+        .set_type = vlynq_irq_type,
+};
+
+static struct irq_chip vlynq_local_chip = {
+        .name = "vlynq local error",
+        .unmask = vlynq_irq_unmask,
+        .mask = vlynq_irq_mask,
+        .ack = vlynq_local_ack,
+};
+
+static struct irq_chip vlynq_remote_chip = {
+        .name = "vlynq local error",
+        .unmask = vlynq_irq_unmask,
+        .mask = vlynq_irq_mask,
+        .ack = vlynq_remote_ack,
+};
+
+static int vlynq_setup_irq(struct vlynq_device *dev)
+{
+        u32 val;
+        int i, virq;
+
+        if (dev->local_irq == dev->remote_irq) {
+                printk(KERN_ERR
+                       "%s: local vlynq irq should be different from remote\n",
+                       dev_name(&dev->dev));
+                return -EINVAL;
+        }
+
+        /* Clear local and remote error bits */
+        writel(readl(&dev->local->status), &dev->local->status);
+        writel(readl(&dev->remote->status), &dev->remote->status);
+
+        /* Now setup interrupts */
+        val = VLYNQ_CTRL_INT_VECTOR(dev->local_irq);
+        val |= VLYNQ_CTRL_INT_ENABLE | VLYNQ_CTRL_INT_LOCAL |
+                VLYNQ_CTRL_INT2CFG;
+        val |= readl(&dev->local->control);
+        writel(VLYNQ_INT_OFFSET, &dev->local->int_ptr);
+        writel(val, &dev->local->control);
+
+        val = VLYNQ_CTRL_INT_VECTOR(dev->remote_irq);
+        val |= VLYNQ_CTRL_INT_ENABLE;
+        val |= readl(&dev->remote->control);
+        writel(VLYNQ_INT_OFFSET, &dev->remote->int_ptr);
+        writel(val, &dev->remote->int_ptr);
+        writel(val, &dev->remote->control);
+
+        for (i = dev->irq_start; i <= dev->irq_end; i++) {
+                virq = i - dev->irq_start;
+                if (virq == dev->local_irq) {
+                        set_irq_chip_and_handler(i, &vlynq_local_chip,
+                                                 handle_level_irq);
+                        set_irq_chip_data(i, dev);
+                } else if (virq == dev->remote_irq) {
+                        set_irq_chip_and_handler(i, &vlynq_remote_chip,
+                                                 handle_level_irq);
+                        set_irq_chip_data(i, dev);
+                } else {
+                        set_irq_chip_and_handler(i, &vlynq_irq_chip,
+                                                 handle_simple_irq);
+                        set_irq_chip_data(i, dev);
+                        writel(0, &dev->remote->int_device[virq >> 2]);
+                }
+        }
+
+        if (request_irq(dev->irq, vlynq_irq, IRQF_SHARED, "vlynq", dev)) {
+                printk(KERN_ERR "%s: request_irq failed\n",
+                                        dev_name(&dev->dev));
+                return -EAGAIN;
+        }
+
+        return 0;
+}
+
+static void vlynq_device_release(struct device *dev)
+{
+        struct vlynq_device *vdev = to_vlynq_device(dev);
+        kfree(vdev);
+}
+
+static int vlynq_device_match(struct device *dev,
+                              struct device_driver *drv)
+{
+        struct vlynq_device *vdev = to_vlynq_device(dev);
+        struct vlynq_driver *vdrv = to_vlynq_driver(drv);
+        struct vlynq_device_id *ids = vdrv->id_table;
+
+        while (ids->id) {
+                if (ids->id == vdev->dev_id) {
+                        vdev->divisor = ids->divisor;
+                        vlynq_set_drvdata(vdev, ids);
+                        printk(KERN_INFO "Driver found for VLYNQ "
+                                "device: %08x\n", vdev->dev_id);
+                        return 1;
+                }
+                printk(KERN_DEBUG "Not using the %08x VLYNQ device's driver"
+                        " for VLYNQ device: %08x\n", ids->id, vdev->dev_id);
+                ids++;
+        }
+        return 0;
+}
+
+static int vlynq_device_probe(struct device *dev)
+{
+        struct vlynq_device *vdev = to_vlynq_device(dev);
+        struct vlynq_driver *drv = to_vlynq_driver(dev->driver);
+        struct vlynq_device_id *id = vlynq_get_drvdata(vdev);
+        int result = -ENODEV;
+
+        if (drv->probe)
+                result = drv->probe(vdev, id);
+        if (result)
+                put_device(dev);
+        return result;
+}
+
+static int vlynq_device_remove(struct device *dev)
+{
+        struct vlynq_driver *drv = to_vlynq_driver(dev->driver);
+
+        if (drv->remove)
+                drv->remove(to_vlynq_device(dev));
+
+        return 0;
+}
+
+int __vlynq_register_driver(struct vlynq_driver *driver, struct module *owner)
+{
+        driver->driver.name = driver->name;
+        driver->driver.bus = &vlynq_bus_type;
+        return driver_register(&driver->driver);
+}
+EXPORT_SYMBOL(__vlynq_register_driver);
+
+void vlynq_unregister_driver(struct vlynq_driver *driver)
+{
+        driver_unregister(&driver->driver);
+}
+EXPORT_SYMBOL(vlynq_unregister_driver);
+
+/*
+ * A VLYNQ remote device can clock the VLYNQ bus master
+ * using a dedicated clock line. In that case, both the
+ * remove device and the bus master should have the same
+ * serial clock dividers configured. Iterate through the
+ * 8 possible dividers until we actually link with the
+ * device.
+ */
+static int __vlynq_try_remote(struct vlynq_device *dev)
+{
+        int i;
+
+        vlynq_reset(dev);
+        for (i = dev->dev_id ? vlynq_rdiv2 : vlynq_rdiv8; dev->dev_id ?
+                        i <= vlynq_rdiv8 : i >= vlynq_rdiv2;
+                dev->dev_id ? i++ : i--) {
+
+                if (!vlynq_linked(dev))
+                        break;
+
+                writel((readl(&dev->remote->control) &
+                                ~VLYNQ_CTRL_CLOCK_MASK) |
+                                VLYNQ_CTRL_CLOCK_INT |
+                                VLYNQ_CTRL_CLOCK_DIV(i - vlynq_rdiv1),
+                                &dev->remote->control);
+                writel((readl(&dev->local->control)
+                                & ~(VLYNQ_CTRL_CLOCK_INT |
+                                VLYNQ_CTRL_CLOCK_MASK)) |
+                                VLYNQ_CTRL_CLOCK_DIV(i - vlynq_rdiv1),
+                                &dev->local->control);
+
+                if (vlynq_linked(dev)) {
+                        printk(KERN_DEBUG
+                                "%s: using remote clock divisor %d\n",
+                                dev_name(&dev->dev), i - vlynq_rdiv1 + 1);
+                        dev->divisor = i;
+                        return 0;
+                } else {
+                        vlynq_reset(dev);
+                }
+        }
+
+        return -ENODEV;
+}
+
+/*
+ * A VLYNQ remote device can be clocked by the VLYNQ bus
+ * master using a dedicated clock line. In that case, only
+ * the bus master configures the serial clock divider.
+ * Iterate through the 8 possible dividers until we
+ * actually get a link with the device.
+ */
+static int __vlynq_try_local(struct vlynq_device *dev)
+{
+        int i;
+
+        vlynq_reset(dev);
+
+        for (i = dev->dev_id ? vlynq_ldiv2 : vlynq_ldiv8; dev->dev_id ?
+                        i <= vlynq_ldiv8 : i >= vlynq_ldiv2;
+                dev->dev_id ? i++ : i--) {
+
+                writel((readl(&dev->local->control) &
+                                ~VLYNQ_CTRL_CLOCK_MASK) |
+                                VLYNQ_CTRL_CLOCK_INT |
+                                VLYNQ_CTRL_CLOCK_DIV(i - vlynq_ldiv1),
+                                &dev->local->control);
+
+                if (vlynq_linked(dev)) {
+                        printk(KERN_DEBUG
+                                "%s: using local clock divisor %d\n",
+                                dev_name(&dev->dev), i - vlynq_ldiv1 + 1);
+                        dev->divisor = i;
+                        return 0;
+                } else {
+                        vlynq_reset(dev);
+                }
+        }
+
+        return -ENODEV;
+}
+
+/*
+ * When using external clocking method, serial clock
+ * is supplied by an external oscillator, therefore we
+ * should mask the local clock bit in the clock control
+ * register for both the bus master and the remote device.
+ */
+static int __vlynq_try_external(struct vlynq_device *dev)
+{
+        vlynq_reset(dev);
+        if (!vlynq_linked(dev))
+                return -ENODEV;
+
+        writel((readl(&dev->remote->control) &
+                        ~VLYNQ_CTRL_CLOCK_INT),
+                        &dev->remote->control);
+
+        writel((readl(&dev->local->control) &
+                        ~VLYNQ_CTRL_CLOCK_INT),
+                        &dev->local->control);
+
+        if (vlynq_linked(dev)) {
+                printk(KERN_DEBUG "%s: using external clock\n",
+                        dev_name(&dev->dev));
+                        dev->divisor = vlynq_div_external;
+                return 0;
+        }
+
+        return -ENODEV;
+}
+
+static int __vlynq_enable_device(struct vlynq_device *dev)
+{
+        int result;
+        struct plat_vlynq_ops *ops = dev->dev.platform_data;
+
+        result = ops->on(dev);
+        if (result)
+                return result;
+
+        switch (dev->divisor) {
+        case vlynq_div_external:
+        case vlynq_div_auto:
+                /* When the device is brought from reset it should have clock
+                 * generation negotiated by hardware.
+                 * Check which device is generating clocks and perform setup
+                 * accordingly */
+                if (vlynq_linked(dev) && readl(&dev->remote->control) &
+                   VLYNQ_CTRL_CLOCK_INT) {
+                        if (!__vlynq_try_remote(dev) ||
+                                !__vlynq_try_local(dev)  ||
+                                !__vlynq_try_external(dev))
+                                return 0;
+                } else {
+                        if (!__vlynq_try_external(dev) ||
+                                !__vlynq_try_local(dev)    ||
+                                !__vlynq_try_remote(dev))
+                                return 0;
+                }
+                break;
+        case vlynq_ldiv1:
+        case vlynq_ldiv2:
+        case vlynq_ldiv3:
+        case vlynq_ldiv4:
+        case vlynq_ldiv5:
+        case vlynq_ldiv6:
+        case vlynq_ldiv7:
+        case vlynq_ldiv8:
+                writel(VLYNQ_CTRL_CLOCK_INT |
+                        VLYNQ_CTRL_CLOCK_DIV(dev->divisor -
+                        vlynq_ldiv1), &dev->local->control);
+                writel(0, &dev->remote->control);
+                if (vlynq_linked(dev)) {
+                        printk(KERN_DEBUG
+                                "%s: using local clock divisor %d\n",
+                                dev_name(&dev->dev),
+                                dev->divisor - vlynq_ldiv1 + 1);
+                        return 0;
+                }
+                break;
+        case vlynq_rdiv1:
+        case vlynq_rdiv2:
+        case vlynq_rdiv3:
+        case vlynq_rdiv4:
+        case vlynq_rdiv5:
+        case vlynq_rdiv6:
+        case vlynq_rdiv7:
+        case vlynq_rdiv8:
+                writel(0, &dev->local->control);
+                writel(VLYNQ_CTRL_CLOCK_INT |
+                        VLYNQ_CTRL_CLOCK_DIV(dev->divisor -
+                        vlynq_rdiv1), &dev->remote->control);
+                if (vlynq_linked(dev)) {
+                        printk(KERN_DEBUG
+                                "%s: using remote clock divisor %d\n",
+                                dev_name(&dev->dev),
+                                dev->divisor - vlynq_rdiv1 + 1);
+                        return 0;
+                }
+                break;
+        }
+
+        ops->off(dev);
+        return -ENODEV;
+}
+
+int vlynq_enable_device(struct vlynq_device *dev)
+{
+        struct plat_vlynq_ops *ops = dev->dev.platform_data;
+        int result = -ENODEV;
+
+        result = __vlynq_enable_device(dev);
+        if (result)
+                return result;
+
+        result = vlynq_setup_irq(dev);
+        if (result)
+                ops->off(dev);
+
+        dev->enabled = !result;
+        return result;
+}
+EXPORT_SYMBOL(vlynq_enable_device);
+
+
+void vlynq_disable_device(struct vlynq_device *dev)
+{
+        struct plat_vlynq_ops *ops = dev->dev.platform_data;
+
+        dev->enabled = 0;
+        free_irq(dev->irq, dev);
+        ops->off(dev);
+}
+EXPORT_SYMBOL(vlynq_disable_device);
+
+int vlynq_set_local_mapping(struct vlynq_device *dev, u32 tx_offset,
+                            struct vlynq_mapping *mapping)
+{
+        int i;
+
+        if (!dev->enabled)
+                return -ENXIO;
+
+        writel(tx_offset, &dev->local->tx_offset);
+        for (i = 0; i < 4; i++) {
+                writel(mapping[i].offset, &dev->local->rx_mapping[i].offset);
+                writel(mapping[i].size, &dev->local->rx_mapping[i].size);
+        }
+        return 0;
+}
+EXPORT_SYMBOL(vlynq_set_local_mapping);
+
+int vlynq_set_remote_mapping(struct vlynq_device *dev, u32 tx_offset,
+                             struct vlynq_mapping *mapping)
+{
+        int i;
+
+        if (!dev->enabled)
+                return -ENXIO;
+
+        writel(tx_offset, &dev->remote->tx_offset);
+        for (i = 0; i < 4; i++) {
+                writel(mapping[i].offset, &dev->remote->rx_mapping[i].offset);
+                writel(mapping[i].size, &dev->remote->rx_mapping[i].size);
+        }
+        return 0;
+}
+EXPORT_SYMBOL(vlynq_set_remote_mapping);
+
+int vlynq_set_local_irq(struct vlynq_device *dev, int virq)
+{
+        int irq = dev->irq_start + virq;
+        if (dev->enabled)
+                return -EBUSY;
+
+        if ((irq < dev->irq_start) || (irq > dev->irq_end))
+                return -EINVAL;
+
+        if (virq == dev->remote_irq)
+                return -EINVAL;
+
+        dev->local_irq = virq;
+
+        return 0;
+}
+EXPORT_SYMBOL(vlynq_set_local_irq);
+
+int vlynq_set_remote_irq(struct vlynq_device *dev, int virq)
+{
+        int irq = dev->irq_start + virq;
+        if (dev->enabled)
+                return -EBUSY;
+
+        if ((irq < dev->irq_start) || (irq > dev->irq_end))
+                return -EINVAL;
+
+        if (virq == dev->local_irq)
+                return -EINVAL;
+
+        dev->remote_irq = virq;
+
+        return 0;
+}
+EXPORT_SYMBOL(vlynq_set_remote_irq);
+
+static int vlynq_probe(struct platform_device *pdev)
+{
+        struct vlynq_device *dev;
+        struct resource *regs_res, *mem_res, *irq_res;
+        int len, result;
+
+        regs_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
+        if (!regs_res)
+                return -ENODEV;
+
+        mem_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
+        if (!mem_res)
+                return -ENODEV;
+
+        irq_res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "devirq");
+        if (!irq_res)
+                return -ENODEV;
+
+        dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+        if (!dev) {
+                printk(KERN_ERR
+                       "vlynq: failed to allocate device structure\n");
+                return -ENOMEM;
+        }
+
+        dev->id = pdev->id;
+        dev->dev.bus = &vlynq_bus_type;
+        dev->dev.parent = &pdev->dev;
+        dev_set_name(&dev->dev, "vlynq%d", dev->id);
+        dev->dev.platform_data = pdev->dev.platform_data;
+        dev->dev.release = vlynq_device_release;
+
+        dev->regs_start = regs_res->start;
+        dev->regs_end = regs_res->end;
+        dev->mem_start = mem_res->start;
+        dev->mem_end = mem_res->end;
+
+        len = regs_res->end - regs_res->start;
+        if (!request_mem_region(regs_res->start, len, dev_name(&dev->dev))) {
+                printk(KERN_ERR "%s: Can't request vlynq registers\n",
+                       dev_name(&dev->dev));
+                result = -ENXIO;
+                goto fail_request;
+        }
+
+        dev->local = ioremap(regs_res->start, len);
+        if (!dev->local) {
+                printk(KERN_ERR "%s: Can't remap vlynq registers\n",
+                       dev_name(&dev->dev));
+                result = -ENXIO;
+                goto fail_remap;
+        }
+
+        dev->remote = (struct vlynq_regs *)((void *)dev->local +
+                                            VLYNQ_REMOTE_OFFSET);
+
+        dev->irq = platform_get_irq_byname(pdev, "irq");
+        dev->irq_start = irq_res->start;
+        dev->irq_end = irq_res->end;
+        dev->local_irq = dev->irq_end - dev->irq_start;
+        dev->remote_irq = dev->local_irq - 1;
+
+        if (device_register(&dev->dev))
+                goto fail_register;
+        platform_set_drvdata(pdev, dev);
+
+        printk(KERN_INFO "%s: regs 0x%p, irq %d, mem 0x%p\n",
+               dev_name(&dev->dev), (void *)dev->regs_start, dev->irq,
+               (void *)dev->mem_start);
+
+        dev->dev_id = 0;
+        dev->divisor = vlynq_div_auto;
+        result = __vlynq_enable_device(dev);
+        if (result == 0) {
+                dev->dev_id = readl(&dev->remote->chip);
+                ((struct plat_vlynq_ops *)(dev->dev.platform_data))->off(dev);
+        }
+        if (dev->dev_id)
+                printk(KERN_INFO "Found a VLYNQ device: %08x\n", dev->dev_id);
+
+        return 0;
+
+fail_register:
+        iounmap(dev->local);
+fail_remap:
+fail_request:
+        release_mem_region(regs_res->start, len);
+        kfree(dev);
+        return result;
+}
+
+static int vlynq_remove(struct platform_device *pdev)
+{
+        struct vlynq_device *dev = platform_get_drvdata(pdev);
+
+        device_unregister(&dev->dev);
+        iounmap(dev->local);
+        release_mem_region(dev->regs_start, dev->regs_end - dev->regs_start);
+
+        kfree(dev);
+
+        return 0;
+}
+
+static struct platform_driver vlynq_platform_driver = {
+        .driver.name = "vlynq",
+        .probe = vlynq_probe,
+        .remove = __devexit_p(vlynq_remove),
+};
+
+struct bus_type vlynq_bus_type = {
+        .name = "vlynq",
+        .match = vlynq_device_match,
+        .probe = vlynq_device_probe,
+        .remove = vlynq_device_remove,
+};
+EXPORT_SYMBOL(vlynq_bus_type);
+
+static int __devinit vlynq_init(void)
+{
+        int res = 0;
+
+        res = bus_register(&vlynq_bus_type);
+        if (res)
+                goto fail_bus;
+
+        res = platform_driver_register(&vlynq_platform_driver);
+        if (res)
+                goto fail_platform;
+
+        return 0;
+
+fail_platform:
+        bus_unregister(&vlynq_bus_type);
+fail_bus:
+        return res;
+}
+
+static void __devexit vlynq_exit(void)
+{
+        platform_driver_unregister(&vlynq_platform_driver);
+        bus_unregister(&vlynq_bus_type);
+}
+
+module_init(vlynq_init);
+module_exit(vlynq_exit);