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authorGabor Juhos <juhosg@openwrt.org>2009-01-14 14:17:09 -0500
committerJohn W. Linville <linville@tuxdriver.com>2009-01-29 16:00:33 -0500
commitd03a66c17ab94f7cfec9b343d415111386216847 (patch)
treedcf7d6fdab2407333bf8f02cef2d3d2a961ac26d /drivers
parent9dbeb91a8b97e2892c04461e28d2bdd0198b719d (diff)
ath9k: remove (u16) casts from rtc register access
The RTC register offsets don't fit into 'u16' on the AR913x, so we have to remove the existing casts. Changes-licensed-under: ISC Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Tested-by: Pavel Roskin <proski@gnu.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/wireless/ath9k/hw.c14
-rw-r--r--drivers/net/wireless/ath9k/reg.h4
2 files changed, 9 insertions, 9 deletions
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 55ed0830588b..ed731b9cac85 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -1011,7 +1011,7 @@ static void ath9k_hw_init_pll(struct ath_hal *ah,
1011 pll |= SM(0xb, AR_RTC_PLL_DIV); 1011 pll |= SM(0xb, AR_RTC_PLL_DIV);
1012 } 1012 }
1013 } 1013 }
1014 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll); 1014 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1015 1015
1016 udelay(RTC_PLL_SETTLE_DELAY); 1016 udelay(RTC_PLL_SETTLE_DELAY);
1017 1017
@@ -1550,11 +1550,11 @@ static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1550 rst_flags |= AR_RTC_RC_MAC_COLD; 1550 rst_flags |= AR_RTC_RC_MAC_COLD;
1551 } 1551 }
1552 1552
1553 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags); 1553 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1554 udelay(50); 1554 udelay(50);
1555 1555
1556 REG_WRITE(ah, (u16) (AR_RTC_RC), 0); 1556 REG_WRITE(ah, AR_RTC_RC, 0);
1557 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) { 1557 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1558 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 1558 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1559 "RTC stuck in MAC reset\n"); 1559 "RTC stuck in MAC reset\n");
1560 return false; 1560 return false;
@@ -1576,8 +1576,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1576 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | 1576 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1577 AR_RTC_FORCE_WAKE_ON_INT); 1577 AR_RTC_FORCE_WAKE_ON_INT);
1578 1578
1579 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0); 1579 REG_WRITE(ah, AR_RTC_RESET, 0);
1580 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1); 1580 REG_WRITE(ah, AR_RTC_RESET, 1);
1581 1581
1582 if (!ath9k_hw_wait(ah, 1582 if (!ath9k_hw_wait(ah,
1583 AR_RTC_STATUS, 1583 AR_RTC_STATUS,
@@ -2619,7 +2619,7 @@ static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2619 if (!AR_SREV_9100(ah)) 2619 if (!AR_SREV_9100(ah))
2620 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); 2620 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2621 2621
2622 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET), 2622 REG_CLR_BIT(ah, (AR_RTC_RESET),
2623 AR_RTC_RESET_EN); 2623 AR_RTC_RESET_EN);
2624 } 2624 }
2625} 2625}
diff --git a/drivers/net/wireless/ath9k/reg.h b/drivers/net/wireless/ath9k/reg.h
index 2dffe371ffe4..150eda56055a 100644
--- a/drivers/net/wireless/ath9k/reg.h
+++ b/drivers/net/wireless/ath9k/reg.h
@@ -953,7 +953,7 @@ enum {
953 953
954#define AR_RTC_BASE 0x00020000 954#define AR_RTC_BASE 0x00020000
955#define AR_RTC_RC \ 955#define AR_RTC_RC \
956 (AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000 956 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000)
957#define AR_RTC_RC_M 0x00000003 957#define AR_RTC_RC_M 0x00000003
958#define AR_RTC_RC_MAC_WARM 0x00000001 958#define AR_RTC_RC_MAC_WARM 0x00000001
959#define AR_RTC_RC_MAC_COLD 0x00000002 959#define AR_RTC_RC_MAC_COLD 0x00000002
@@ -961,7 +961,7 @@ enum {
961#define AR_RTC_RC_WARM_RESET 0x00000008 961#define AR_RTC_RC_WARM_RESET 0x00000008
962 962
963#define AR_RTC_PLL_CONTROL \ 963#define AR_RTC_PLL_CONTROL \
964 (AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014 964 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
965 965
966#define AR_RTC_PLL_DIV 0x0000001f 966#define AR_RTC_PLL_DIV 0x0000001f
967#define AR_RTC_PLL_DIV_S 0 967#define AR_RTC_PLL_DIV_S 0