diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-14 19:06:58 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-14 19:06:58 -0400 |
commit | 85082fd7cbe3173198aac0eb5e85ab1edcc6352c (patch) | |
tree | edbc09b7945994f78668d218fa02e991c3b3b365 /drivers | |
parent | 666484f0250db2e016948d63b3ef33e202e3b8d0 (diff) | |
parent | 53ffe3b440aa85af6fc4eda09b2d44bcdd312d4d (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (241 commits)
[ARM] 5171/1: ep93xx: fix compilation of modules using clocks
[ARM] 5133/2: at91sam9g20 defconfig file
[ARM] 5130/4: Support for the at91sam9g20
[ARM] 5160/1: IOP3XX: gpio/gpiolib support
[ARM] at91: Fix NAND FLASH timings for at91sam9x evaluation kits.
[ARM] 5084/1: zylonite: Register AC97 device
[ARM] 5085/2: PXA: Move AC97 over to the new central device declaration model
[ARM] 5120/1: pxa: correct platform driver names for PXA25x and PXA27x UDC drivers
[ARM] 5147/1: pxaficp_ir: drop pxa_gpio_mode calls, as pin setting
[ARM] 5145/1: PXA2xx: provide api to control IrDA pins state
[ARM] 5144/1: pxaficp_ir: cleanup includes
[ARM] pxa: remove pxa_set_cken()
[ARM] pxa: allow clk aliases
[ARM] Feroceon: don't disable BPU on boot
[ARM] Orion: LED support for HP mv2120
[ARM] Orion: add RD88F5181L-FXO support
[ARM] Orion: add RD88F5181L-GE support
[ARM] Orion: add Netgear WNR854T support
[ARM] s3c2410_defconfig: update for current build
[ARM] Acer n30: Minor style and indentation fixes.
...
Diffstat (limited to 'drivers')
55 files changed, 3560 insertions, 3288 deletions
diff --git a/drivers/acorn/char/Makefile b/drivers/acorn/char/Makefile deleted file mode 100644 index d006c9f168d2..000000000000 --- a/drivers/acorn/char/Makefile +++ /dev/null | |||
@@ -1,5 +0,0 @@ | |||
1 | # | ||
2 | # Makefile for the acorn character device drivers. | ||
3 | # | ||
4 | |||
5 | obj-$(CONFIG_L7200_KEYB) += defkeymap-l7200.o keyb_l7200.o | ||
diff --git a/drivers/acorn/char/defkeymap-l7200.c b/drivers/acorn/char/defkeymap-l7200.c deleted file mode 100644 index 93d80a1c36f9..000000000000 --- a/drivers/acorn/char/defkeymap-l7200.c +++ /dev/null | |||
@@ -1,386 +0,0 @@ | |||
1 | /* | ||
2 | * linux/drivers/acorn/char/defkeymap-l7200.c | ||
3 | * | ||
4 | * Default keyboard maps for LinkUp Systems L7200 board | ||
5 | * | ||
6 | * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) | ||
7 | * | ||
8 | * Changelog: | ||
9 | * 08-04-2000 SJH Created file | ||
10 | */ | ||
11 | |||
12 | #include <linux/types.h> | ||
13 | #include <linux/keyboard.h> | ||
14 | #include <linux/kd.h> | ||
15 | |||
16 | /* Normal (maps 1:1 with no processing) */ | ||
17 | #define KTn 0xF0 | ||
18 | /* Function keys */ | ||
19 | #define KTf 0xF1 | ||
20 | /* Special (Performs special house-keeping funcs) */ | ||
21 | #define KTs 0xF2 | ||
22 | #define KIGNORE K(KTs, 0) /* Ignore */ | ||
23 | #define KENTER K(KTs, 1) /* Enter */ | ||
24 | #define KREGS K(KTs, 2) /* Regs */ | ||
25 | #define KMEM K(KTs, 3) /* Mem */ | ||
26 | #define KSTAT K(KTs, 4) /* State */ | ||
27 | #define KINTR K(KTs, 5) /* Intr */ | ||
28 | #define Ksl 6 /* Last console */ | ||
29 | #define KCAPSLK K(KTs, 7) /* Caps lock */ | ||
30 | #define KNUMLK K(KTs, 8) /* Num-lock */ | ||
31 | #define KSCRLLK K(KTs, 9) /* Scroll-lock */ | ||
32 | #define KSCRLFOR K(KTs,10) /* Scroll forward */ | ||
33 | #define KSCRLBAK K(KTs,11) /* Scroll back */ | ||
34 | #define KREBOOT K(KTs,12) /* Reboot */ | ||
35 | #define KCAPSON K(KTs,13) /* Caps on */ | ||
36 | #define KCOMPOSE K(KTs,14) /* Compose */ | ||
37 | #define KSAK K(KTs,15) /* SAK */ | ||
38 | #define CONS_DEC K(KTs,16) /* Dec console */ | ||
39 | #define CONS_INC K(KTs,17) /* Incr console */ | ||
40 | #define KFLOPPY K(KTs,18) /* Floppy */ | ||
41 | /* Key pad (0-9 = digits, 10=+, 11=-, 12=*, 13=/, 14=enter, 16=., 17=# */ | ||
42 | #define KTp 0xF3 | ||
43 | #define KPAD_0 K(KTp, 0 ) | ||
44 | #define KPAD_1 K(KTp, 1 ) | ||
45 | #define KPAD_2 K(KTp, 2 ) | ||
46 | #define KPAD_3 K(KTp, 3 ) | ||
47 | #define KPAD_4 K(KTp, 4 ) | ||
48 | #define KPAD_5 K(KTp, 5 ) | ||
49 | #define KPAD_6 K(KTp, 6 ) | ||
50 | #define KPAD_7 K(KTp, 7 ) | ||
51 | #define KPAD_8 K(KTp, 8 ) | ||
52 | #define KPAD_9 K(KTp, 9 ) | ||
53 | #define KPAD_PL K(KTp,10 ) | ||
54 | #define KPAD_MI K(KTp,11 ) | ||
55 | #define KPAD_ML K(KTp,12 ) | ||
56 | #define KPAD_DV K(KTp,13 ) | ||
57 | #define KPAD_EN K(KTp,14 ) | ||
58 | #define KPAD_DT K(KTp,16 ) | ||
59 | #define KPAD_HS K(KTp,20 ) | ||
60 | /* Console switching */ | ||
61 | #define KCn 0xF5 | ||
62 | /* Cursor */ | ||
63 | #define KTc 0xF6 | ||
64 | #define Kcd 0 /* Cursor down */ | ||
65 | #define Kcl 1 /* Cursor left */ | ||
66 | #define Kcr 2 /* Cursor right */ | ||
67 | #define Kcu 3 /* Cursor up */ | ||
68 | /* Shift/alt modifiers etc */ | ||
69 | #define KMd 0xF7 | ||
70 | #define KSHIFT K(KMd, 0 ) | ||
71 | #define KALTGR K(KMd, 1 ) | ||
72 | #define KCTRL K(KMd, 2 ) | ||
73 | #define KALT K(KMd, 3 ) | ||
74 | /* Meta */ | ||
75 | #define KMt 0xF8 | ||
76 | #define KAs 0xF9 | ||
77 | #define KPADA_0 K(KAs, 0 ) | ||
78 | #define KPADA_1 K(KAs, 1 ) | ||
79 | #define KPADA_2 K(KAs, 2 ) | ||
80 | #define KPADA_3 K(KAs, 3 ) | ||
81 | #define KPADA_4 K(KAs, 4 ) | ||
82 | #define KPADA_5 K(KAs, 5 ) | ||
83 | #define KPADA_6 K(KAs, 6 ) | ||
84 | #define KPADA_7 K(KAs, 7 ) | ||
85 | #define KPADA_8 K(KAs, 8 ) | ||
86 | #define KPADA_9 K(KAs, 9 ) | ||
87 | #define KPADB_0 K(KAs,10 ) | ||
88 | #define KPADB_1 K(KAs,11 ) | ||
89 | #define KPADB_2 K(KAs,12 ) | ||
90 | #define KPADB_3 K(KAs,13 ) | ||
91 | #define KPADB_4 K(KAs,14 ) | ||
92 | #define KPADB_5 K(KAs,15 ) | ||
93 | #define KPADB_6 K(KAs,16 ) | ||
94 | #define KPADB_7 K(KAs,17 ) | ||
95 | #define KPADB_8 K(KAs,18 ) | ||
96 | #define KPADB_9 K(KAs,19 ) | ||
97 | /* Locking keys */ | ||
98 | #define KLk 0xFA | ||
99 | /* Letters */ | ||
100 | #define KTl 0xFB | ||
101 | |||
102 | /* | ||
103 | * Here is the layout of the keys for the Fujitsu QWERTY | ||
104 | * style keyboard: | ||
105 | * | ||
106 | * static char Fujitsu_Key_Table[] = | ||
107 | * { | ||
108 | * KALT, '`' , KNUL, KCTL, KFUN, KESC, '1' , '2' , | ||
109 | * '9' , '0' , '-' , '=' , KNUL, KBSP, KNUL, KNUL, | ||
110 | * KNUL, KBSL, KSHF, KNUL, KNUL, KDEL, KNUL, 't' , | ||
111 | * 'y' , 'u' , 'i' , KRET, KSHF, KPGD, KNUL, KNUL, | ||
112 | * KNUL, KTAB, KNUL, KNUL, KNUL, 'q' , 'w' , 'e' , | ||
113 | * 'r' , 'o' , 'p' , '[' , KNUL, ']' , KNUL, KNUL, | ||
114 | * KNUL, 'z' , KNUL, KNUL, KNUL, KSHL, KNUL, KNUL, | ||
115 | * 'k' , 'l' , ';' , KSQT, KNUL, KPGU, KNUL, KNUL, | ||
116 | * KNUL, 'a' , KNUL, KNUL, KNUL, 's' , 'd' , 'f' , | ||
117 | * 'g' , 'h' , 'j' , '/' , KNUL, KHME, KNUL, KNUL, | ||
118 | * KNUL, 'x' , KNUL, KNUL, KNUL, 'c' , 'v' , 'b' , | ||
119 | * 'n' , 'm' , ',' , '.' , KNUL, ' ' , KNUL, KNUL, | ||
120 | * KNUL, KNUL, KNUL, KNUL, KNUL, '3' , '4' , '5' , | ||
121 | * '6' , '7' , '8' , KNUL, KPRG, KNUL, KEND, KNUL, | ||
122 | * }; | ||
123 | */ | ||
124 | |||
125 | u_short plain_map[NR_KEYS]= | ||
126 | { | ||
127 | 0xf703, 0xf060, 0xf200, 0xf702, 0xf200, 0xf01b, 0xf031, 0xf032, | ||
128 | 0xf039, 0xf030, 0xf02d, 0xf03d, 0xf200, 0xf07f, 0xf200, 0xf200, | ||
129 | 0xf200, 0xf05c, 0xf700, 0xf200, 0xf200, 0xf116, 0xf000, 0xfb74, | ||
130 | 0xfb79, 0xfb75, 0xfb69, 0xf201, 0xf700, 0xf600, 0xf200, 0xf200, | ||
131 | 0xf200, 0xf009, 0xf200, 0xf200, 0xf200, 0xfb71, 0xfb77, 0xfb65, | ||
132 | 0xfb72, 0xfb6f, 0xfb70, 0xf05b, 0xf200, 0xf05d, 0xf200, 0xf200, | ||
133 | 0xf200, 0xfb7a, 0xf200, 0xf200, 0xf200, 0xf207, 0xf200, 0xf200, | ||
134 | 0xfb6b, 0xfb6c, 0xf03b, 0xf027, 0xf200, 0xf603, 0xf200, 0xf200, | ||
135 | 0xf200, 0xfb61, 0xf200, 0xf200, 0xf200, 0xfb73, 0xfb64, 0xfb66, | ||
136 | 0xfb67, 0xfb68, 0xfb6a, 0xf02f, 0xf200, 0xf601, 0xf200, 0xf200, | ||
137 | 0xf200, 0xfb78, 0xf200, 0xf200, 0xf200, 0xfb63, 0xfb76, 0xfb62, | ||
138 | 0xfb6e, 0xfb6d, 0xf02c, 0xf02e, 0xf200, 0xf020, 0xf200, 0xf200, | ||
139 | 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf033, 0xf034, 0xf035, | ||
140 | 0xf036, 0xf037, 0xf038, 0xf200, 0xf200, 0xf200, 0xf602, 0xf200, | ||
141 | 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, | ||
142 | 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, | ||
143 | }; | ||
144 | |||
145 | u_short shift_map[NR_KEYS]= | ||
146 | { | ||
147 | 0xf703, 0xf07e, 0xf200, 0xf702, 0xf200, 0xf01b, 0xf021, 0xf040, | ||
148 | 0xf028, 0xf029, 0xf05f, 0xf02b, 0xf200, 0xf07f, 0xf200, 0xf200, | ||
149 | 0xf200, 0xf07c, 0xf700, 0xf200, 0xf200, 0xf116, 0xf000, 0xfb54, | ||
150 | 0xfb59, 0xfb55, 0xfb49, 0xf201, 0xf700, 0xf600, 0xf200, 0xf200, | ||
151 | 0xf200, 0xf009, 0xf200, 0xf200, 0xf200, 0xfb51, 0xfb57, 0xfb45, | ||
152 | 0xfb52, 0xfb4f, 0xfb50, 0xf07b, 0xf200, 0xf07d, 0xf200, 0xf200, | ||
153 | 0xf200, 0xfb5a, 0xf200, 0xf200, 0xf200, 0xf207, 0xf200, 0xf200, | ||
154 | 0xfb4b, 0xfb4c, 0xf03a, 0xf022, 0xf200, 0xf603, 0xf200, 0xf200, | ||
155 | 0xf200, 0xfb41, 0xf200, 0xf200, 0xf200, 0xfb53, 0xfb44, 0xfb46, | ||
156 | 0xfb47, 0xfb48, 0xfb4a, 0xf03f, 0xf200, 0xf601, 0xf200, 0xf200, | ||
157 | 0xf200, 0xfb58, 0xf200, 0xf200, 0xf200, 0xfb43, 0xfb56, 0xfb42, | ||
158 | 0xfb4e, 0xfb4d, 0xf03c, 0xf03e, 0xf200, 0xf020, 0xf200, 0xf200, | ||
159 | 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf023, 0xf024, 0xf025, | ||
160 | 0xf05e, 0xf026, 0xf02a, 0xf200, 0xf200, 0xf200, 0xf602, 0xf200, | ||
161 | 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, | ||
162 | 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, | ||
163 | }; | ||
164 | |||
165 | u_short altgr_map[NR_KEYS]= | ||
166 | { | ||
167 | KIGNORE ,K(KCn,12 ),K(KCn,13 ),K(KCn,14 ),K(KCn,15 ),K(KCn,16 ),K(KCn,17 ),K(KCn, 18), | ||
168 | K(KCn, 19),K(KCn,20 ),K(KCn,21 ),K(KCn,22 ),K(KCn,23 ),KIGNORE ,KREGS ,KINTR , | ||
169 | KIGNORE ,KIGNORE ,K(KTn,'@'),KIGNORE ,K(KTn,'$'),KIGNORE ,KIGNORE ,K(KTn,'{'), | ||
170 | K(KTn,'['),K(KTn,']'),K(KTn,'}'),K(KTn,'\\'),KIGNORE ,KIGNORE ,KIGNORE ,K(KTf,21 ), | ||
171 | K(KTf,20 ),K(KTf,24 ),KNUMLK ,KPAD_DV ,KPAD_ML ,KPAD_HS ,KIGNORE ,K(KTl,'q'), | ||
172 | K(KTl,'w'),K(KTl,'e'),K(KTl,'r'),K(KTl,'t' ),K(KTl,'y'),K(KTl,'u'),K(KTl,'i' ),K(KTl,'o'), | ||
173 | K(KTl,'p'),KIGNORE ,K(KTn,'~'),KIGNORE ,K(KTf,22 ),K(KTf,23 ),K(KTf,25 ),KPADB_7 , | ||
174 | KPADB_8 ,KPADB_9 ,KPAD_MI ,KCTRL ,K(KAs,20 ),K(KTl,'s'),K(KAs,23 ),K(KAs,25 ), | ||
175 | K(KTl,'g'),K(KTl,'h'),K(KTl,'j'),K(KTl,'k' ),K(KTl,'l'),KIGNORE ,KIGNORE ,KENTER , | ||
176 | KPADB_4 ,KPADB_5 ,KPADB_6 ,KPAD_PL ,KSHIFT ,KIGNORE ,K(KTl,'z' ),K(KTl,'x'), | ||
177 | K(KAs,22 ),K(KTl,'v'),K(KTl,21 ),K(KTl,'n' ),K(KTl,'m'),KIGNORE ,KIGNORE ,KIGNORE , | ||
178 | KSHIFT ,K(KTc,Kcu),KPADB_1 ,KPADB_2 ,KPADB_3 ,KCAPSLK ,KALT ,KIGNORE , | ||
179 | KALTGR ,KCTRL ,K(KTc,Kcl),K(KTc,Kcd ),K(KTc,Kcr),KPADB_0 ,KPAD_DT ,KPAD_EN , | ||
180 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
181 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
182 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
183 | }; | ||
184 | |||
185 | u_short ctrl_map[NR_KEYS]= | ||
186 | { | ||
187 | 0xf703, 0xf200, 0xf200, 0xf702, 0xf200, 0xf200, 0xf001, 0xf002, | ||
188 | 0xf009, 0xf000, 0xf031, 0xf200, 0xf200, 0xf07f, 0xf200, 0xf200, | ||
189 | 0xf200, 0xf01c, 0xf700, 0xf200, 0xf200, 0xf116, 0xf000, 0xf020, | ||
190 | 0xf019, 0xf015, 0xf009, 0xf201, 0xf700, 0xf600, 0xf200, 0xf200, | ||
191 | 0xf200, 0xf009, 0xf200, 0xf200, 0xf200, 0xf011, 0xf017, 0xf005, | ||
192 | 0xf012, 0xf00f, 0xf010, 0xf01b, 0xf200, 0xf01d, 0xf200, 0xf200, | ||
193 | 0xf200, 0xf01a, 0xf200, 0xf200, 0xf200, 0xf207, 0xf200, 0xf200, | ||
194 | 0xf00b, 0xf00c, 0xf200, 0xf007, 0xf200, 0xf603, 0xf200, 0xf200, | ||
195 | 0xf200, 0xf001, 0xf200, 0xf200, 0xf200, 0xf001, 0xf013, 0xf006, | ||
196 | 0xf007, 0xf008, 0xf00a, 0xf07f, 0xf200, 0xf601, 0xf200, 0xf200, | ||
197 | 0xf200, 0xf018, 0xf200, 0xf200, 0xf200, 0xf003, 0xf016, 0xf002, | ||
198 | 0xf00e, 0xf00d, 0xf200, 0xf200, 0xf200, 0xf000, 0xf200, 0xf200, | ||
199 | 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf01b, 0xf01c, 0xf01d, | ||
200 | 0xf036, 0xf037, 0xf038, 0xf200, 0xf200, 0xf200, 0xf602, 0xf200, | ||
201 | 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, | ||
202 | 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf200, 0xf602, 0xf200, | ||
203 | }; | ||
204 | |||
205 | u_short shift_ctrl_map[NR_KEYS]= | ||
206 | { | ||
207 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
208 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KFLOPPY ,KINTR , | ||
209 | KIGNORE ,KIGNORE ,K(KTn, 0 ),KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
210 | KIGNORE ,KIGNORE ,KIGNORE ,K(KTn,31 ),KIGNORE ,KIGNORE ,KIGNORE ,K(KTf,21 ), | ||
211 | K(KTf,20 ),K(KTf,24 ),KNUMLK ,KPAD_DV ,KPAD_ML ,KPAD_HS ,KIGNORE ,K(KTn,17 ), | ||
212 | K(KTn,23 ),K(KTn, 5 ),K(KTn,18 ),K(KTn,20 ),K(KTn,25 ),K(KTn,21 ),K(KTn, 9 ),K(KTn,15 ), | ||
213 | K(KTn,16 ),KIGNORE ,KIGNORE ,KIGNORE ,K(KTf,22 ),K(KTf,23 ),K(KTf,25 ),KPAD_7 , | ||
214 | KPAD_8 ,KPAD_9 ,KPAD_MI ,KCTRL ,K(KTn, 1 ),K(KTn,19 ),K(KTn, 4 ),K(KTn, 6 ), | ||
215 | K(KTn, 7 ),K(KTn, 8 ),K(KTn,10 ),K(KTn,11 ),K(KTn,12 ),KIGNORE ,K(KTn, 7 ),KENTER , | ||
216 | KPAD_4 ,KPAD_5 ,KPAD_6 ,KPAD_PL ,KSHIFT ,KIGNORE ,K(KTn,26 ),K(KTn,24 ), | ||
217 | K(KTn, 3 ),K(KTn,22 ),K(KTn, 2 ),K(KTn,14 ),K(KTn,13 ),KIGNORE ,KIGNORE ,KIGNORE , | ||
218 | KSHIFT ,K(KTc,Kcu),KPAD_1 ,KPAD_2 ,KPAD_3 ,KCAPSLK ,KALT ,K(KTn, 0 ), | ||
219 | KALTGR ,KCTRL ,K(KTc,Kcl),K(KTc,Kcd ),K(KTc,Kcr),KPAD_0 ,KPAD_DT ,KPAD_EN , | ||
220 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
221 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
222 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
223 | }; | ||
224 | |||
225 | u_short alt_map[NR_KEYS]= | ||
226 | { | ||
227 | K(KMt,27 ),K(KCn, 0 ),K(KCn, 1 ),K(KCn, 2 ),K(KCn, 3 ),K(KCn, 4 ),K(KCn, 5 ),K(KCn, 6 ), | ||
228 | K(KCn, 7 ),K(KCn, 8 ),K(KCn, 9 ),K(KCn,10 ),K(KCn,11 ),KIGNORE ,KSCRLLK ,KINTR , | ||
229 | K(KMt,'`'),K(KMt,'1'),K(KMt,'2'),K(KMt,'3' ),K(KMt,'4'),K(KMt,'5'),K(KMt,'6' ),K(KMt,'7'), | ||
230 | K(KMt,'8'),K(KMt,'9'),K(KMt,'0'),K(KMt,'-' ),K(KMt,'='),K(KMt,'£'),K(KMt,127 ),K(KTf,21 ), | ||
231 | K(KTf,20 ),K(KTf,24 ),KNUMLK ,KPAD_DV ,KPAD_ML ,KPAD_HS ,K(KMt, 9 ),K(KMt,'q'), | ||
232 | K(KMt,'w'),K(KMt,'e'),K(KMt,'r'),K(KMt,'t' ),K(KMt,'y'),K(KMt,'u'),K(KMt,'i' ),K(KMt,'o'), | ||
233 | K(KMt,'p'),K(KMt,'['),K(KMt,']'),K(KMt,'\\'),K(KTf,22 ),K(KTf,23 ),K(KTf,25 ),KPADA_7 , | ||
234 | KPADA_8 ,KPADA_9 ,KPAD_MI ,KCTRL ,K(KMt,'a'),K(KMt,'s'),K(KMt,'d' ),K(KMt,'f'), | ||
235 | K(KMt,'g'),K(KMt,'h'),K(KMt,'j'),K(KMt,'k' ),K(KMt,'l'),K(KMt,';'),K(KMt,'\''),K(KMt,13 ), | ||
236 | KPADA_4 ,KPADA_5 ,KPADA_6 ,KPAD_PL ,KSHIFT ,KIGNORE ,K(KMt,'z' ),K(KMt,'x'), | ||
237 | K(KMt,'c'),K(KMt,'v'),K(KMt,'b'),K(KMt,'n' ),K(KMt,'m'),K(KMt,','),K(KMt,'.' ),KIGNORE , | ||
238 | KSHIFT ,K(KTc,Kcu),KPADA_1 ,KPADA_2 ,KPADA_3 ,KCAPSLK ,KALT ,K(KMt,' '), | ||
239 | KALTGR ,KCTRL ,CONS_DEC ,K(KTc,Kcd ),CONS_INC ,KPADA_0 ,KPAD_DT ,KPAD_EN , | ||
240 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
241 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
242 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
243 | }; | ||
244 | |||
245 | u_short ctrl_alt_map[NR_KEYS]= | ||
246 | { | ||
247 | KIGNORE ,K(KCn, 0 ),K(KCn, 1 ),K(KCn, 2 ),K(KCn, 3 ),K(KCn, 4 ),K(KCn, 5 ),K(KCn, 6 ), | ||
248 | K(KCn, 7 ),K(KCn, 8 ),K(KCn, 9 ),K(KCn,10 ),K(KCn,11 ),KIGNORE ,KIGNORE ,KINTR , | ||
249 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
250 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,K(KTf,21 ), | ||
251 | K(KTf,20 ),K(KTf,24 ),KNUMLK ,KPAD_DV ,KPAD_ML ,KPAD_HS ,KIGNORE ,K(KMt,17 ), | ||
252 | K(KMt,23 ),K(KMt, 5 ),K(KMt,18 ),K(KMt,20 ),K(KMt,25 ),K(KMt,21 ),K(KMt, 9 ),K(KMt,15 ), | ||
253 | K(KMt,16 ),KIGNORE ,KIGNORE ,KIGNORE ,KREBOOT ,K(KTf,23 ),K(KTf,25 ),KPAD_7 , | ||
254 | KPAD_8 ,KPAD_9 ,KPAD_MI ,KCTRL ,K(KMt, 1 ),K(KMt,19 ),K(KMt, 4 ),K(KMt, 6 ), | ||
255 | K(KMt, 7 ),K(KMt, 8 ),K(KMt,10 ),K(KMt,11 ),K(KMt,12 ),KIGNORE ,KIGNORE ,KENTER , | ||
256 | KPAD_4 ,KPAD_5 ,KPAD_6 ,KPAD_PL ,KSHIFT ,KIGNORE ,K(KMt,26 ),K(KMt,24 ), | ||
257 | K(KMt, 3 ),K(KMt,22 ),K(KMt, 2 ),K(KMt,14 ),K(KMt,13 ),KIGNORE ,KIGNORE ,KIGNORE , | ||
258 | KSHIFT ,K(KTc,Kcu),KPAD_1 ,KPAD_2 ,KPAD_3 ,KCAPSLK ,KALT ,KIGNORE , | ||
259 | KALTGR ,KCTRL ,K(KTc,Kcl),K(KTc,Kcd ),K(KTc,Kcr),KPAD_0 ,KREBOOT ,KPAD_EN , | ||
260 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
261 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
262 | KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE ,KIGNORE , | ||
263 | }; | ||
264 | |||
265 | ushort *key_maps[MAX_NR_KEYMAPS] = { | ||
266 | plain_map, shift_map, altgr_map, 0, | ||
267 | ctrl_map, shift_ctrl_map, 0, 0, | ||
268 | alt_map, 0, 0, 0, | ||
269 | ctrl_alt_map, 0 | ||
270 | }; | ||
271 | |||
272 | unsigned int keymap_count = 7; | ||
273 | |||
274 | /* | ||
275 | * Philosophy: most people do not define more strings, but they who do | ||
276 | * often want quite a lot of string space. So, we statically allocate | ||
277 | * the default and allocate dynamically in chunks of 512 bytes. | ||
278 | */ | ||
279 | |||
280 | char func_buf[] = { | ||
281 | '\033', '[', '[', 'A', 0, | ||
282 | '\033', '[', '[', 'B', 0, | ||
283 | '\033', '[', '[', 'C', 0, | ||
284 | '\033', '[', '[', 'D', 0, | ||
285 | '\033', '[', '[', 'E', 0, | ||
286 | '\033', '[', '1', '7', '~', 0, | ||
287 | '\033', '[', '1', '8', '~', 0, | ||
288 | '\033', '[', '1', '9', '~', 0, | ||
289 | '\033', '[', '2', '0', '~', 0, | ||
290 | '\033', '[', '2', '1', '~', 0, | ||
291 | '\033', '[', '2', '3', '~', 0, | ||
292 | '\033', '[', '2', '4', '~', 0, | ||
293 | '\033', '[', '2', '5', '~', 0, | ||
294 | '\033', '[', '2', '6', '~', 0, | ||
295 | '\033', '[', '2', '8', '~', 0, | ||
296 | '\033', '[', '2', '9', '~', 0, | ||
297 | '\033', '[', '3', '1', '~', 0, | ||
298 | '\033', '[', '3', '2', '~', 0, | ||
299 | '\033', '[', '3', '3', '~', 0, | ||
300 | '\033', '[', '3', '4', '~', 0, | ||
301 | '\033', '[', '1', '~', 0, | ||
302 | '\033', '[', '2', '~', 0, | ||
303 | '\033', '[', '3', '~', 0, | ||
304 | '\033', '[', '4', '~', 0, | ||
305 | '\033', '[', '5', '~', 0, | ||
306 | '\033', '[', '6', '~', 0, | ||
307 | '\033', '[', 'M', 0, | ||
308 | '\033', '[', 'P', 0, | ||
309 | }; | ||
310 | |||
311 | char *funcbufptr = func_buf; | ||
312 | int funcbufsize = sizeof(func_buf); | ||
313 | int funcbufleft = 0; /* space left */ | ||
314 | |||
315 | char *func_table[MAX_NR_FUNC] = { | ||
316 | func_buf + 0, | ||
317 | func_buf + 5, | ||
318 | func_buf + 10, | ||
319 | func_buf + 15, | ||
320 | func_buf + 20, | ||
321 | func_buf + 25, | ||
322 | func_buf + 31, | ||
323 | func_buf + 37, | ||
324 | func_buf + 43, | ||
325 | func_buf + 49, | ||
326 | func_buf + 55, | ||
327 | func_buf + 61, | ||
328 | func_buf + 67, | ||
329 | func_buf + 73, | ||
330 | func_buf + 79, | ||
331 | func_buf + 85, | ||
332 | func_buf + 91, | ||
333 | func_buf + 97, | ||
334 | func_buf + 103, | ||
335 | func_buf + 109, | ||
336 | func_buf + 115, | ||
337 | func_buf + 120, | ||
338 | func_buf + 125, | ||
339 | func_buf + 130, | ||
340 | func_buf + 135, | ||
341 | func_buf + 140, | ||
342 | func_buf + 145, | ||
343 | 0, | ||
344 | 0, | ||
345 | func_buf + 149, | ||
346 | 0, | ||
347 | }; | ||
348 | |||
349 | struct kbdiacruc accent_table[MAX_DIACR] = { | ||
350 | {'`', 'A', 0300}, {'`', 'a', 0340}, | ||
351 | {'\'', 'A', 0301}, {'\'', 'a', 0341}, | ||
352 | {'^', 'A', 0302}, {'^', 'a', 0342}, | ||
353 | {'~', 'A', 0303}, {'~', 'a', 0343}, | ||
354 | {'"', 'A', 0304}, {'"', 'a', 0344}, | ||
355 | {'O', 'A', 0305}, {'o', 'a', 0345}, | ||
356 | {'0', 'A', 0305}, {'0', 'a', 0345}, | ||
357 | {'A', 'A', 0305}, {'a', 'a', 0345}, | ||
358 | {'A', 'E', 0306}, {'a', 'e', 0346}, | ||
359 | {',', 'C', 0307}, {',', 'c', 0347}, | ||
360 | {'`', 'E', 0310}, {'`', 'e', 0350}, | ||
361 | {'\'', 'E', 0311}, {'\'', 'e', 0351}, | ||
362 | {'^', 'E', 0312}, {'^', 'e', 0352}, | ||
363 | {'"', 'E', 0313}, {'"', 'e', 0353}, | ||
364 | {'`', 'I', 0314}, {'`', 'i', 0354}, | ||
365 | {'\'', 'I', 0315}, {'\'', 'i', 0355}, | ||
366 | {'^', 'I', 0316}, {'^', 'i', 0356}, | ||
367 | {'"', 'I', 0317}, {'"', 'i', 0357}, | ||
368 | {'-', 'D', 0320}, {'-', 'd', 0360}, | ||
369 | {'~', 'N', 0321}, {'~', 'n', 0361}, | ||
370 | {'`', 'O', 0322}, {'`', 'o', 0362}, | ||
371 | {'\'', 'O', 0323}, {'\'', 'o', 0363}, | ||
372 | {'^', 'O', 0324}, {'^', 'o', 0364}, | ||
373 | {'~', 'O', 0325}, {'~', 'o', 0365}, | ||
374 | {'"', 'O', 0326}, {'"', 'o', 0366}, | ||
375 | {'/', 'O', 0330}, {'/', 'o', 0370}, | ||
376 | {'`', 'U', 0331}, {'`', 'u', 0371}, | ||
377 | {'\'', 'U', 0332}, {'\'', 'u', 0372}, | ||
378 | {'^', 'U', 0333}, {'^', 'u', 0373}, | ||
379 | {'"', 'U', 0334}, {'"', 'u', 0374}, | ||
380 | {'\'', 'Y', 0335}, {'\'', 'y', 0375}, | ||
381 | {'T', 'H', 0336}, {'t', 'h', 0376}, | ||
382 | {'s', 's', 0337}, {'"', 'y', 0377}, | ||
383 | {'s', 'z', 0337}, {'i', 'j', 0377}, | ||
384 | }; | ||
385 | |||
386 | unsigned int accent_table_size = 68; | ||
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c index eb69fbadc9cb..dde6ce963a19 100644 --- a/drivers/i2c/busses/i2c-pxa.c +++ b/drivers/i2c/busses/i2c-pxa.c | |||
@@ -39,7 +39,6 @@ | |||
39 | #include <asm/io.h> | 39 | #include <asm/io.h> |
40 | #include <asm/arch/i2c.h> | 40 | #include <asm/arch/i2c.h> |
41 | #include <asm/arch/pxa-regs.h> | 41 | #include <asm/arch/pxa-regs.h> |
42 | #include <asm/arch/pxa2xx-gpio.h> | ||
43 | 42 | ||
44 | struct pxa_i2c { | 43 | struct pxa_i2c { |
45 | spinlock_t lock; | 44 | spinlock_t lock; |
@@ -945,32 +944,6 @@ static const struct i2c_algorithm i2c_pxa_pio_algorithm = { | |||
945 | .functionality = i2c_pxa_functionality, | 944 | .functionality = i2c_pxa_functionality, |
946 | }; | 945 | }; |
947 | 946 | ||
948 | static void i2c_pxa_enable(struct platform_device *dev) | ||
949 | { | ||
950 | if (cpu_is_pxa27x()) { | ||
951 | switch (dev->id) { | ||
952 | case 0: | ||
953 | pxa_gpio_mode(GPIO117_I2CSCL_MD); | ||
954 | pxa_gpio_mode(GPIO118_I2CSDA_MD); | ||
955 | break; | ||
956 | case 1: | ||
957 | local_irq_disable(); | ||
958 | PCFR |= PCFR_PI2CEN; | ||
959 | local_irq_enable(); | ||
960 | break; | ||
961 | } | ||
962 | } | ||
963 | } | ||
964 | |||
965 | static void i2c_pxa_disable(struct platform_device *dev) | ||
966 | { | ||
967 | if (cpu_is_pxa27x() && dev->id == 1) { | ||
968 | local_irq_disable(); | ||
969 | PCFR &= ~PCFR_PI2CEN; | ||
970 | local_irq_enable(); | ||
971 | } | ||
972 | } | ||
973 | |||
974 | #define res_len(r) ((r)->end - (r)->start + 1) | 947 | #define res_len(r) ((r)->end - (r)->start + 1) |
975 | static int i2c_pxa_probe(struct platform_device *dev) | 948 | static int i2c_pxa_probe(struct platform_device *dev) |
976 | { | 949 | { |
@@ -1036,7 +1009,6 @@ static int i2c_pxa_probe(struct platform_device *dev) | |||
1036 | #endif | 1009 | #endif |
1037 | 1010 | ||
1038 | clk_enable(i2c->clk); | 1011 | clk_enable(i2c->clk); |
1039 | i2c_pxa_enable(dev); | ||
1040 | 1012 | ||
1041 | if (plat) { | 1013 | if (plat) { |
1042 | i2c->adap.class = plat->class; | 1014 | i2c->adap.class = plat->class; |
@@ -1080,7 +1052,6 @@ eadapt: | |||
1080 | free_irq(irq, i2c); | 1052 | free_irq(irq, i2c); |
1081 | ereqirq: | 1053 | ereqirq: |
1082 | clk_disable(i2c->clk); | 1054 | clk_disable(i2c->clk); |
1083 | i2c_pxa_disable(dev); | ||
1084 | iounmap(i2c->reg_base); | 1055 | iounmap(i2c->reg_base); |
1085 | eremap: | 1056 | eremap: |
1086 | clk_put(i2c->clk); | 1057 | clk_put(i2c->clk); |
@@ -1103,7 +1074,6 @@ static int __exit i2c_pxa_remove(struct platform_device *dev) | |||
1103 | 1074 | ||
1104 | clk_disable(i2c->clk); | 1075 | clk_disable(i2c->clk); |
1105 | clk_put(i2c->clk); | 1076 | clk_put(i2c->clk); |
1106 | i2c_pxa_disable(dev); | ||
1107 | 1077 | ||
1108 | iounmap(i2c->reg_base); | 1078 | iounmap(i2c->reg_base); |
1109 | release_mem_region(i2c->iobase, i2c->iosize); | 1079 | release_mem_region(i2c->iobase, i2c->iosize); |
diff --git a/drivers/i2c/chips/isp1301_omap.c b/drivers/i2c/chips/isp1301_omap.c index b1b45dddb17e..03a33f1b9cd3 100644 --- a/drivers/i2c/chips/isp1301_omap.c +++ b/drivers/i2c/chips/isp1301_omap.c | |||
@@ -72,7 +72,7 @@ struct isp1301 { | |||
72 | }; | 72 | }; |
73 | 73 | ||
74 | 74 | ||
75 | /* bits in OTG_CTRL_REG */ | 75 | /* bits in OTG_CTRL */ |
76 | 76 | ||
77 | #define OTG_XCEIV_OUTPUTS \ | 77 | #define OTG_XCEIV_OUTPUTS \ |
78 | (OTG_ASESSVLD|OTG_BSESSEND|OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID) | 78 | (OTG_ASESSVLD|OTG_BSESSEND|OTG_BSESSVLD|OTG_VBUSVLD|OTG_ID) |
@@ -186,8 +186,8 @@ isp1301_clear_bits(struct isp1301 *isp, u8 reg, u8 bits) | |||
186 | 186 | ||
187 | /* operational registers */ | 187 | /* operational registers */ |
188 | #define ISP1301_MODE_CONTROL_1 0x04 /* u8 read, set, +1 clear */ | 188 | #define ISP1301_MODE_CONTROL_1 0x04 /* u8 read, set, +1 clear */ |
189 | # define MC1_SPEED_REG (1 << 0) | 189 | # define MC1_SPEED (1 << 0) |
190 | # define MC1_SUSPEND_REG (1 << 1) | 190 | # define MC1_SUSPEND (1 << 1) |
191 | # define MC1_DAT_SE0 (1 << 2) | 191 | # define MC1_DAT_SE0 (1 << 2) |
192 | # define MC1_TRANSPARENT (1 << 3) | 192 | # define MC1_TRANSPARENT (1 << 3) |
193 | # define MC1_BDIS_ACON_EN (1 << 4) | 193 | # define MC1_BDIS_ACON_EN (1 << 4) |
@@ -274,7 +274,7 @@ static void power_down(struct isp1301 *isp) | |||
274 | isp->otg.state = OTG_STATE_UNDEFINED; | 274 | isp->otg.state = OTG_STATE_UNDEFINED; |
275 | 275 | ||
276 | // isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); | 276 | // isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); |
277 | isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND_REG); | 277 | isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND); |
278 | 278 | ||
279 | isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_ID_PULLDOWN); | 279 | isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_ID_PULLDOWN); |
280 | isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0); | 280 | isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0); |
@@ -283,7 +283,7 @@ static void power_down(struct isp1301 *isp) | |||
283 | static void power_up(struct isp1301 *isp) | 283 | static void power_up(struct isp1301 *isp) |
284 | { | 284 | { |
285 | // isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); | 285 | // isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); |
286 | isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND_REG); | 286 | isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND); |
287 | 287 | ||
288 | /* do this only when cpu is driving transceiver, | 288 | /* do this only when cpu is driving transceiver, |
289 | * so host won't see a low speed device... | 289 | * so host won't see a low speed device... |
@@ -360,6 +360,8 @@ isp1301_defer_work(struct isp1301 *isp, int work) | |||
360 | /* called from irq handlers */ | 360 | /* called from irq handlers */ |
361 | static void a_idle(struct isp1301 *isp, const char *tag) | 361 | static void a_idle(struct isp1301 *isp, const char *tag) |
362 | { | 362 | { |
363 | u32 l; | ||
364 | |||
363 | if (isp->otg.state == OTG_STATE_A_IDLE) | 365 | if (isp->otg.state == OTG_STATE_A_IDLE) |
364 | return; | 366 | return; |
365 | 367 | ||
@@ -373,13 +375,17 @@ static void a_idle(struct isp1301 *isp, const char *tag) | |||
373 | gadget_suspend(isp); | 375 | gadget_suspend(isp); |
374 | } | 376 | } |
375 | isp->otg.state = OTG_STATE_A_IDLE; | 377 | isp->otg.state = OTG_STATE_A_IDLE; |
376 | isp->last_otg_ctrl = OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS; | 378 | l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS; |
379 | omap_writel(l, OTG_CTRL); | ||
380 | isp->last_otg_ctrl = l; | ||
377 | pr_debug(" --> %s/%s\n", state_name(isp), tag); | 381 | pr_debug(" --> %s/%s\n", state_name(isp), tag); |
378 | } | 382 | } |
379 | 383 | ||
380 | /* called from irq handlers */ | 384 | /* called from irq handlers */ |
381 | static void b_idle(struct isp1301 *isp, const char *tag) | 385 | static void b_idle(struct isp1301 *isp, const char *tag) |
382 | { | 386 | { |
387 | u32 l; | ||
388 | |||
383 | if (isp->otg.state == OTG_STATE_B_IDLE) | 389 | if (isp->otg.state == OTG_STATE_B_IDLE) |
384 | return; | 390 | return; |
385 | 391 | ||
@@ -393,7 +399,9 @@ static void b_idle(struct isp1301 *isp, const char *tag) | |||
393 | gadget_suspend(isp); | 399 | gadget_suspend(isp); |
394 | } | 400 | } |
395 | isp->otg.state = OTG_STATE_B_IDLE; | 401 | isp->otg.state = OTG_STATE_B_IDLE; |
396 | isp->last_otg_ctrl = OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS; | 402 | l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS; |
403 | omap_writel(l, OTG_CTRL); | ||
404 | isp->last_otg_ctrl = l; | ||
397 | pr_debug(" --> %s/%s\n", state_name(isp), tag); | 405 | pr_debug(" --> %s/%s\n", state_name(isp), tag); |
398 | } | 406 | } |
399 | 407 | ||
@@ -406,7 +414,7 @@ dump_regs(struct isp1301 *isp, const char *label) | |||
406 | u8 src = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE); | 414 | u8 src = isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE); |
407 | 415 | ||
408 | pr_debug("otg: %06x, %s %s, otg/%02x stat/%02x.%02x\n", | 416 | pr_debug("otg: %06x, %s %s, otg/%02x stat/%02x.%02x\n", |
409 | OTG_CTRL_REG, label, state_name(isp), | 417 | omap_readl(OTG_CTRL), label, state_name(isp), |
410 | ctrl, status, src); | 418 | ctrl, status, src); |
411 | /* mode control and irq enables don't change much */ | 419 | /* mode control and irq enables don't change much */ |
412 | #endif | 420 | #endif |
@@ -429,7 +437,7 @@ dump_regs(struct isp1301 *isp, const char *label) | |||
429 | static void check_state(struct isp1301 *isp, const char *tag) | 437 | static void check_state(struct isp1301 *isp, const char *tag) |
430 | { | 438 | { |
431 | enum usb_otg_state state = OTG_STATE_UNDEFINED; | 439 | enum usb_otg_state state = OTG_STATE_UNDEFINED; |
432 | u8 fsm = OTG_TEST_REG & 0x0ff; | 440 | u8 fsm = omap_readw(OTG_TEST) & 0x0ff; |
433 | unsigned extra = 0; | 441 | unsigned extra = 0; |
434 | 442 | ||
435 | switch (fsm) { | 443 | switch (fsm) { |
@@ -494,7 +502,8 @@ static void check_state(struct isp1301 *isp, const char *tag) | |||
494 | if (isp->otg.state == state && !extra) | 502 | if (isp->otg.state == state && !extra) |
495 | return; | 503 | return; |
496 | pr_debug("otg: %s FSM %s/%02x, %s, %06x\n", tag, | 504 | pr_debug("otg: %s FSM %s/%02x, %s, %06x\n", tag, |
497 | state_string(state), fsm, state_name(isp), OTG_CTRL_REG); | 505 | state_string(state), fsm, state_name(isp), |
506 | omap_readl(OTG_CTRL)); | ||
498 | } | 507 | } |
499 | 508 | ||
500 | #else | 509 | #else |
@@ -508,10 +517,11 @@ static void update_otg1(struct isp1301 *isp, u8 int_src) | |||
508 | { | 517 | { |
509 | u32 otg_ctrl; | 518 | u32 otg_ctrl; |
510 | 519 | ||
511 | otg_ctrl = OTG_CTRL_REG | 520 | otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK; |
512 | & OTG_CTRL_MASK | 521 | otg_ctrl &= ~OTG_XCEIV_INPUTS; |
513 | & ~OTG_XCEIV_INPUTS | 522 | otg_ctrl &= ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD); |
514 | & ~(OTG_ID|OTG_ASESSVLD|OTG_VBUSVLD); | 523 | |
524 | |||
515 | if (int_src & INTR_SESS_VLD) | 525 | if (int_src & INTR_SESS_VLD) |
516 | otg_ctrl |= OTG_ASESSVLD; | 526 | otg_ctrl |= OTG_ASESSVLD; |
517 | else if (isp->otg.state == OTG_STATE_A_WAIT_VFALL) { | 527 | else if (isp->otg.state == OTG_STATE_A_WAIT_VFALL) { |
@@ -534,7 +544,7 @@ static void update_otg1(struct isp1301 *isp, u8 int_src) | |||
534 | return; | 544 | return; |
535 | } | 545 | } |
536 | } | 546 | } |
537 | OTG_CTRL_REG = otg_ctrl; | 547 | omap_writel(otg_ctrl, OTG_CTRL); |
538 | } | 548 | } |
539 | 549 | ||
540 | /* outputs from ISP1301_OTG_STATUS */ | 550 | /* outputs from ISP1301_OTG_STATUS */ |
@@ -542,15 +552,14 @@ static void update_otg2(struct isp1301 *isp, u8 otg_status) | |||
542 | { | 552 | { |
543 | u32 otg_ctrl; | 553 | u32 otg_ctrl; |
544 | 554 | ||
545 | otg_ctrl = OTG_CTRL_REG | 555 | otg_ctrl = omap_readl(OTG_CTRL) & OTG_CTRL_MASK; |
546 | & OTG_CTRL_MASK | 556 | otg_ctrl &= ~OTG_XCEIV_INPUTS; |
547 | & ~OTG_XCEIV_INPUTS | 557 | otg_ctrl &= ~(OTG_BSESSVLD | OTG_BSESSEND); |
548 | & ~(OTG_BSESSVLD|OTG_BSESSEND); | ||
549 | if (otg_status & OTG_B_SESS_VLD) | 558 | if (otg_status & OTG_B_SESS_VLD) |
550 | otg_ctrl |= OTG_BSESSVLD; | 559 | otg_ctrl |= OTG_BSESSVLD; |
551 | else if (otg_status & OTG_B_SESS_END) | 560 | else if (otg_status & OTG_B_SESS_END) |
552 | otg_ctrl |= OTG_BSESSEND; | 561 | otg_ctrl |= OTG_BSESSEND; |
553 | OTG_CTRL_REG = otg_ctrl; | 562 | omap_writel(otg_ctrl, OTG_CTRL); |
554 | } | 563 | } |
555 | 564 | ||
556 | /* inputs going to ISP1301 */ | 565 | /* inputs going to ISP1301 */ |
@@ -559,7 +568,7 @@ static void otg_update_isp(struct isp1301 *isp) | |||
559 | u32 otg_ctrl, otg_change; | 568 | u32 otg_ctrl, otg_change; |
560 | u8 set = OTG1_DM_PULLDOWN, clr = OTG1_DM_PULLUP; | 569 | u8 set = OTG1_DM_PULLDOWN, clr = OTG1_DM_PULLUP; |
561 | 570 | ||
562 | otg_ctrl = OTG_CTRL_REG; | 571 | otg_ctrl = omap_readl(OTG_CTRL); |
563 | otg_change = otg_ctrl ^ isp->last_otg_ctrl; | 572 | otg_change = otg_ctrl ^ isp->last_otg_ctrl; |
564 | isp->last_otg_ctrl = otg_ctrl; | 573 | isp->last_otg_ctrl = otg_ctrl; |
565 | otg_ctrl = otg_ctrl & OTG_XCEIV_INPUTS; | 574 | otg_ctrl = otg_ctrl & OTG_XCEIV_INPUTS; |
@@ -639,6 +648,8 @@ pulldown: | |||
639 | 648 | ||
640 | /* HNP switch to host or peripheral; and SRP */ | 649 | /* HNP switch to host or peripheral; and SRP */ |
641 | if (otg_change & OTG_PULLUP) { | 650 | if (otg_change & OTG_PULLUP) { |
651 | u32 l; | ||
652 | |||
642 | switch (isp->otg.state) { | 653 | switch (isp->otg.state) { |
643 | case OTG_STATE_B_IDLE: | 654 | case OTG_STATE_B_IDLE: |
644 | if (clr & OTG1_DP_PULLUP) | 655 | if (clr & OTG1_DP_PULLUP) |
@@ -655,7 +666,9 @@ pulldown: | |||
655 | default: | 666 | default: |
656 | break; | 667 | break; |
657 | } | 668 | } |
658 | OTG_CTRL_REG |= OTG_PULLUP; | 669 | l = omap_readl(OTG_CTRL); |
670 | l |= OTG_PULLUP; | ||
671 | omap_writel(l, OTG_CTRL); | ||
659 | } | 672 | } |
660 | 673 | ||
661 | check_state(isp, __func__); | 674 | check_state(isp, __func__); |
@@ -664,20 +677,20 @@ pulldown: | |||
664 | 677 | ||
665 | static irqreturn_t omap_otg_irq(int irq, void *_isp) | 678 | static irqreturn_t omap_otg_irq(int irq, void *_isp) |
666 | { | 679 | { |
667 | u16 otg_irq = OTG_IRQ_SRC_REG; | 680 | u16 otg_irq = omap_readw(OTG_IRQ_SRC); |
668 | u32 otg_ctrl; | 681 | u32 otg_ctrl; |
669 | int ret = IRQ_NONE; | 682 | int ret = IRQ_NONE; |
670 | struct isp1301 *isp = _isp; | 683 | struct isp1301 *isp = _isp; |
671 | 684 | ||
672 | /* update ISP1301 transciever from OTG controller */ | 685 | /* update ISP1301 transciever from OTG controller */ |
673 | if (otg_irq & OPRT_CHG) { | 686 | if (otg_irq & OPRT_CHG) { |
674 | OTG_IRQ_SRC_REG = OPRT_CHG; | 687 | omap_writew(OPRT_CHG, OTG_IRQ_SRC); |
675 | isp1301_defer_work(isp, WORK_UPDATE_ISP); | 688 | isp1301_defer_work(isp, WORK_UPDATE_ISP); |
676 | ret = IRQ_HANDLED; | 689 | ret = IRQ_HANDLED; |
677 | 690 | ||
678 | /* SRP to become b_peripheral failed */ | 691 | /* SRP to become b_peripheral failed */ |
679 | } else if (otg_irq & B_SRP_TMROUT) { | 692 | } else if (otg_irq & B_SRP_TMROUT) { |
680 | pr_debug("otg: B_SRP_TIMEOUT, %06x\n", OTG_CTRL_REG); | 693 | pr_debug("otg: B_SRP_TIMEOUT, %06x\n", omap_readl(OTG_CTRL)); |
681 | notresponding(isp); | 694 | notresponding(isp); |
682 | 695 | ||
683 | /* gadget drivers that care should monitor all kinds of | 696 | /* gadget drivers that care should monitor all kinds of |
@@ -687,31 +700,31 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp) | |||
687 | if (isp->otg.state == OTG_STATE_B_SRP_INIT) | 700 | if (isp->otg.state == OTG_STATE_B_SRP_INIT) |
688 | b_idle(isp, "srp_timeout"); | 701 | b_idle(isp, "srp_timeout"); |
689 | 702 | ||
690 | OTG_IRQ_SRC_REG = B_SRP_TMROUT; | 703 | omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC); |
691 | ret = IRQ_HANDLED; | 704 | ret = IRQ_HANDLED; |
692 | 705 | ||
693 | /* HNP to become b_host failed */ | 706 | /* HNP to become b_host failed */ |
694 | } else if (otg_irq & B_HNP_FAIL) { | 707 | } else if (otg_irq & B_HNP_FAIL) { |
695 | pr_debug("otg: %s B_HNP_FAIL, %06x\n", | 708 | pr_debug("otg: %s B_HNP_FAIL, %06x\n", |
696 | state_name(isp), OTG_CTRL_REG); | 709 | state_name(isp), omap_readl(OTG_CTRL)); |
697 | notresponding(isp); | 710 | notresponding(isp); |
698 | 711 | ||
699 | otg_ctrl = OTG_CTRL_REG; | 712 | otg_ctrl = omap_readl(OTG_CTRL); |
700 | otg_ctrl |= OTG_BUSDROP; | 713 | otg_ctrl |= OTG_BUSDROP; |
701 | otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; | 714 | otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; |
702 | OTG_CTRL_REG = otg_ctrl; | 715 | omap_writel(otg_ctrl, OTG_CTRL); |
703 | 716 | ||
704 | /* subset of b_peripheral()... */ | 717 | /* subset of b_peripheral()... */ |
705 | isp->otg.state = OTG_STATE_B_PERIPHERAL; | 718 | isp->otg.state = OTG_STATE_B_PERIPHERAL; |
706 | pr_debug(" --> b_peripheral\n"); | 719 | pr_debug(" --> b_peripheral\n"); |
707 | 720 | ||
708 | OTG_IRQ_SRC_REG = B_HNP_FAIL; | 721 | omap_writew(B_HNP_FAIL, OTG_IRQ_SRC); |
709 | ret = IRQ_HANDLED; | 722 | ret = IRQ_HANDLED; |
710 | 723 | ||
711 | /* detect SRP from B-device ... */ | 724 | /* detect SRP from B-device ... */ |
712 | } else if (otg_irq & A_SRP_DETECT) { | 725 | } else if (otg_irq & A_SRP_DETECT) { |
713 | pr_debug("otg: %s SRP_DETECT, %06x\n", | 726 | pr_debug("otg: %s SRP_DETECT, %06x\n", |
714 | state_name(isp), OTG_CTRL_REG); | 727 | state_name(isp), omap_readl(OTG_CTRL)); |
715 | 728 | ||
716 | isp1301_defer_work(isp, WORK_UPDATE_OTG); | 729 | isp1301_defer_work(isp, WORK_UPDATE_OTG); |
717 | switch (isp->otg.state) { | 730 | switch (isp->otg.state) { |
@@ -719,49 +732,49 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp) | |||
719 | if (!isp->otg.host) | 732 | if (!isp->otg.host) |
720 | break; | 733 | break; |
721 | isp1301_defer_work(isp, WORK_HOST_RESUME); | 734 | isp1301_defer_work(isp, WORK_HOST_RESUME); |
722 | otg_ctrl = OTG_CTRL_REG; | 735 | otg_ctrl = omap_readl(OTG_CTRL); |
723 | otg_ctrl |= OTG_A_BUSREQ; | 736 | otg_ctrl |= OTG_A_BUSREQ; |
724 | otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ) | 737 | otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ) |
725 | & ~OTG_XCEIV_INPUTS | 738 | & ~OTG_XCEIV_INPUTS |
726 | & OTG_CTRL_MASK; | 739 | & OTG_CTRL_MASK; |
727 | OTG_CTRL_REG = otg_ctrl; | 740 | omap_writel(otg_ctrl, OTG_CTRL); |
728 | break; | 741 | break; |
729 | default: | 742 | default: |
730 | break; | 743 | break; |
731 | } | 744 | } |
732 | 745 | ||
733 | OTG_IRQ_SRC_REG = A_SRP_DETECT; | 746 | omap_writew(A_SRP_DETECT, OTG_IRQ_SRC); |
734 | ret = IRQ_HANDLED; | 747 | ret = IRQ_HANDLED; |
735 | 748 | ||
736 | /* timer expired: T(a_wait_bcon) and maybe T(a_wait_vrise) | 749 | /* timer expired: T(a_wait_bcon) and maybe T(a_wait_vrise) |
737 | * we don't track them separately | 750 | * we don't track them separately |
738 | */ | 751 | */ |
739 | } else if (otg_irq & A_REQ_TMROUT) { | 752 | } else if (otg_irq & A_REQ_TMROUT) { |
740 | otg_ctrl = OTG_CTRL_REG; | 753 | otg_ctrl = omap_readl(OTG_CTRL); |
741 | pr_info("otg: BCON_TMOUT from %s, %06x\n", | 754 | pr_info("otg: BCON_TMOUT from %s, %06x\n", |
742 | state_name(isp), otg_ctrl); | 755 | state_name(isp), otg_ctrl); |
743 | notresponding(isp); | 756 | notresponding(isp); |
744 | 757 | ||
745 | otg_ctrl |= OTG_BUSDROP; | 758 | otg_ctrl |= OTG_BUSDROP; |
746 | otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; | 759 | otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; |
747 | OTG_CTRL_REG = otg_ctrl; | 760 | omap_writel(otg_ctrl, OTG_CTRL); |
748 | isp->otg.state = OTG_STATE_A_WAIT_VFALL; | 761 | isp->otg.state = OTG_STATE_A_WAIT_VFALL; |
749 | 762 | ||
750 | OTG_IRQ_SRC_REG = A_REQ_TMROUT; | 763 | omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC); |
751 | ret = IRQ_HANDLED; | 764 | ret = IRQ_HANDLED; |
752 | 765 | ||
753 | /* A-supplied voltage fell too low; overcurrent */ | 766 | /* A-supplied voltage fell too low; overcurrent */ |
754 | } else if (otg_irq & A_VBUS_ERR) { | 767 | } else if (otg_irq & A_VBUS_ERR) { |
755 | otg_ctrl = OTG_CTRL_REG; | 768 | otg_ctrl = omap_readl(OTG_CTRL); |
756 | printk(KERN_ERR "otg: %s, VBUS_ERR %04x ctrl %06x\n", | 769 | printk(KERN_ERR "otg: %s, VBUS_ERR %04x ctrl %06x\n", |
757 | state_name(isp), otg_irq, otg_ctrl); | 770 | state_name(isp), otg_irq, otg_ctrl); |
758 | 771 | ||
759 | otg_ctrl |= OTG_BUSDROP; | 772 | otg_ctrl |= OTG_BUSDROP; |
760 | otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; | 773 | otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; |
761 | OTG_CTRL_REG = otg_ctrl; | 774 | omap_writel(otg_ctrl, OTG_CTRL); |
762 | isp->otg.state = OTG_STATE_A_VBUS_ERR; | 775 | isp->otg.state = OTG_STATE_A_VBUS_ERR; |
763 | 776 | ||
764 | OTG_IRQ_SRC_REG = A_VBUS_ERR; | 777 | omap_writew(A_VBUS_ERR, OTG_IRQ_SRC); |
765 | ret = IRQ_HANDLED; | 778 | ret = IRQ_HANDLED; |
766 | 779 | ||
767 | /* switch driver; the transciever code activates it, | 780 | /* switch driver; the transciever code activates it, |
@@ -770,7 +783,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp) | |||
770 | } else if (otg_irq & DRIVER_SWITCH) { | 783 | } else if (otg_irq & DRIVER_SWITCH) { |
771 | int kick = 0; | 784 | int kick = 0; |
772 | 785 | ||
773 | otg_ctrl = OTG_CTRL_REG; | 786 | otg_ctrl = omap_readl(OTG_CTRL); |
774 | printk(KERN_NOTICE "otg: %s, SWITCH to %s, ctrl %06x\n", | 787 | printk(KERN_NOTICE "otg: %s, SWITCH to %s, ctrl %06x\n", |
775 | state_name(isp), | 788 | state_name(isp), |
776 | (otg_ctrl & OTG_DRIVER_SEL) | 789 | (otg_ctrl & OTG_DRIVER_SEL) |
@@ -793,7 +806,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp) | |||
793 | } else { | 806 | } else { |
794 | if (!(otg_ctrl & OTG_ID)) { | 807 | if (!(otg_ctrl & OTG_ID)) { |
795 | otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; | 808 | otg_ctrl &= OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS; |
796 | OTG_CTRL_REG = otg_ctrl | OTG_A_BUSREQ; | 809 | omap_writel(otg_ctrl | OTG_A_BUSREQ, OTG_CTRL); |
797 | } | 810 | } |
798 | 811 | ||
799 | if (isp->otg.host) { | 812 | if (isp->otg.host) { |
@@ -818,7 +831,7 @@ static irqreturn_t omap_otg_irq(int irq, void *_isp) | |||
818 | } | 831 | } |
819 | } | 832 | } |
820 | 833 | ||
821 | OTG_IRQ_SRC_REG = DRIVER_SWITCH; | 834 | omap_writew(DRIVER_SWITCH, OTG_IRQ_SRC); |
822 | ret = IRQ_HANDLED; | 835 | ret = IRQ_HANDLED; |
823 | 836 | ||
824 | if (kick) | 837 | if (kick) |
@@ -834,12 +847,15 @@ static struct platform_device *otg_dev; | |||
834 | 847 | ||
835 | static int otg_init(struct isp1301 *isp) | 848 | static int otg_init(struct isp1301 *isp) |
836 | { | 849 | { |
850 | u32 l; | ||
851 | |||
837 | if (!otg_dev) | 852 | if (!otg_dev) |
838 | return -ENODEV; | 853 | return -ENODEV; |
839 | 854 | ||
840 | dump_regs(isp, __func__); | 855 | dump_regs(isp, __func__); |
841 | /* some of these values are board-specific... */ | 856 | /* some of these values are board-specific... */ |
842 | OTG_SYSCON_2_REG |= OTG_EN | 857 | l = omap_readl(OTG_SYSCON_2); |
858 | l |= OTG_EN | ||
843 | /* for B-device: */ | 859 | /* for B-device: */ |
844 | | SRP_GPDATA /* 9msec Bdev D+ pulse */ | 860 | | SRP_GPDATA /* 9msec Bdev D+ pulse */ |
845 | | SRP_GPDVBUS /* discharge after VBUS pulse */ | 861 | | SRP_GPDVBUS /* discharge after VBUS pulse */ |
@@ -849,18 +865,22 @@ static int otg_init(struct isp1301 *isp) | |||
849 | | SRP_DPW /* detect 167+ns SRP pulses */ | 865 | | SRP_DPW /* detect 167+ns SRP pulses */ |
850 | | SRP_DATA | SRP_VBUS /* accept both kinds of SRP pulse */ | 866 | | SRP_DATA | SRP_VBUS /* accept both kinds of SRP pulse */ |
851 | ; | 867 | ; |
868 | omap_writel(l, OTG_SYSCON_2); | ||
852 | 869 | ||
853 | update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE)); | 870 | update_otg1(isp, isp1301_get_u8(isp, ISP1301_INTERRUPT_SOURCE)); |
854 | update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS)); | 871 | update_otg2(isp, isp1301_get_u8(isp, ISP1301_OTG_STATUS)); |
855 | 872 | ||
856 | check_state(isp, __func__); | 873 | check_state(isp, __func__); |
857 | pr_debug("otg: %s, %s %06x\n", | 874 | pr_debug("otg: %s, %s %06x\n", |
858 | state_name(isp), __func__, OTG_CTRL_REG); | 875 | state_name(isp), __func__, omap_readl(OTG_CTRL)); |
859 | 876 | ||
860 | OTG_IRQ_EN_REG = DRIVER_SWITCH | OPRT_CHG | 877 | omap_writew(DRIVER_SWITCH | OPRT_CHG |
861 | | B_SRP_TMROUT | B_HNP_FAIL | 878 | | B_SRP_TMROUT | B_HNP_FAIL |
862 | | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT; | 879 | | A_VBUS_ERR | A_SRP_DETECT | A_REQ_TMROUT, OTG_IRQ_EN); |
863 | OTG_SYSCON_2_REG |= OTG_EN; | 880 | |
881 | l = omap_readl(OTG_SYSCON_2); | ||
882 | l |= OTG_EN; | ||
883 | omap_writel(l, OTG_SYSCON_2); | ||
864 | 884 | ||
865 | return 0; | 885 | return 0; |
866 | } | 886 | } |
@@ -927,7 +947,11 @@ static void otg_unbind(struct isp1301 *isp) | |||
927 | 947 | ||
928 | static void b_peripheral(struct isp1301 *isp) | 948 | static void b_peripheral(struct isp1301 *isp) |
929 | { | 949 | { |
930 | OTG_CTRL_REG = OTG_CTRL_REG & OTG_XCEIV_OUTPUTS; | 950 | u32 l; |
951 | |||
952 | l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS; | ||
953 | omap_writel(l, OTG_CTRL); | ||
954 | |||
931 | usb_gadget_vbus_connect(isp->otg.gadget); | 955 | usb_gadget_vbus_connect(isp->otg.gadget); |
932 | 956 | ||
933 | #ifdef CONFIG_USB_OTG | 957 | #ifdef CONFIG_USB_OTG |
@@ -999,6 +1023,8 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat) | |||
999 | isp_bstat = 0; | 1023 | isp_bstat = 0; |
1000 | } | 1024 | } |
1001 | } else { | 1025 | } else { |
1026 | u32 l; | ||
1027 | |||
1002 | /* if user unplugged mini-A end of cable, | 1028 | /* if user unplugged mini-A end of cable, |
1003 | * don't bypass A_WAIT_VFALL. | 1029 | * don't bypass A_WAIT_VFALL. |
1004 | */ | 1030 | */ |
@@ -1019,8 +1045,9 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat) | |||
1019 | isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, | 1045 | isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1, |
1020 | MC1_BDIS_ACON_EN); | 1046 | MC1_BDIS_ACON_EN); |
1021 | isp->otg.state = OTG_STATE_B_IDLE; | 1047 | isp->otg.state = OTG_STATE_B_IDLE; |
1022 | OTG_CTRL_REG &= OTG_CTRL_REG & OTG_CTRL_MASK | 1048 | l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK; |
1023 | & ~OTG_CTRL_BITS; | 1049 | l &= ~OTG_CTRL_BITS; |
1050 | omap_writel(l, OTG_CTRL); | ||
1024 | break; | 1051 | break; |
1025 | case OTG_STATE_B_IDLE: | 1052 | case OTG_STATE_B_IDLE: |
1026 | break; | 1053 | break; |
@@ -1046,7 +1073,8 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat) | |||
1046 | /* FALLTHROUGH */ | 1073 | /* FALLTHROUGH */ |
1047 | case OTG_STATE_B_SRP_INIT: | 1074 | case OTG_STATE_B_SRP_INIT: |
1048 | b_idle(isp, __func__); | 1075 | b_idle(isp, __func__); |
1049 | OTG_CTRL_REG &= OTG_CTRL_REG & OTG_XCEIV_OUTPUTS; | 1076 | l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS; |
1077 | omap_writel(l, OTG_CTRL); | ||
1050 | /* FALLTHROUGH */ | 1078 | /* FALLTHROUGH */ |
1051 | case OTG_STATE_B_IDLE: | 1079 | case OTG_STATE_B_IDLE: |
1052 | if (isp->otg.gadget && (isp_bstat & OTG_B_SESS_VLD)) { | 1080 | if (isp->otg.gadget && (isp_bstat & OTG_B_SESS_VLD)) { |
@@ -1130,11 +1158,11 @@ isp1301_work(struct work_struct *work) | |||
1130 | case OTG_STATE_A_WAIT_VRISE: | 1158 | case OTG_STATE_A_WAIT_VRISE: |
1131 | isp->otg.state = OTG_STATE_A_HOST; | 1159 | isp->otg.state = OTG_STATE_A_HOST; |
1132 | pr_debug(" --> a_host\n"); | 1160 | pr_debug(" --> a_host\n"); |
1133 | otg_ctrl = OTG_CTRL_REG; | 1161 | otg_ctrl = omap_readl(OTG_CTRL); |
1134 | otg_ctrl |= OTG_A_BUSREQ; | 1162 | otg_ctrl |= OTG_A_BUSREQ; |
1135 | otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ) | 1163 | otg_ctrl &= ~(OTG_BUSDROP|OTG_B_BUSREQ) |
1136 | & OTG_CTRL_MASK; | 1164 | & OTG_CTRL_MASK; |
1137 | OTG_CTRL_REG = otg_ctrl; | 1165 | omap_writel(otg_ctrl, OTG_CTRL); |
1138 | break; | 1166 | break; |
1139 | case OTG_STATE_B_WAIT_ACON: | 1167 | case OTG_STATE_B_WAIT_ACON: |
1140 | isp->otg.state = OTG_STATE_B_HOST; | 1168 | isp->otg.state = OTG_STATE_B_HOST; |
@@ -1274,7 +1302,7 @@ isp1301_set_host(struct otg_transceiver *otg, struct usb_bus *host) | |||
1274 | return -ENODEV; | 1302 | return -ENODEV; |
1275 | 1303 | ||
1276 | if (!host) { | 1304 | if (!host) { |
1277 | OTG_IRQ_EN_REG = 0; | 1305 | omap_writew(0, OTG_IRQ_EN); |
1278 | power_down(isp); | 1306 | power_down(isp); |
1279 | isp->otg.host = 0; | 1307 | isp->otg.host = 0; |
1280 | return 0; | 1308 | return 0; |
@@ -1325,12 +1353,13 @@ static int | |||
1325 | isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget) | 1353 | isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget) |
1326 | { | 1354 | { |
1327 | struct isp1301 *isp = container_of(otg, struct isp1301, otg); | 1355 | struct isp1301 *isp = container_of(otg, struct isp1301, otg); |
1356 | u32 l; | ||
1328 | 1357 | ||
1329 | if (!otg || isp != the_transceiver) | 1358 | if (!otg || isp != the_transceiver) |
1330 | return -ENODEV; | 1359 | return -ENODEV; |
1331 | 1360 | ||
1332 | if (!gadget) { | 1361 | if (!gadget) { |
1333 | OTG_IRQ_EN_REG = 0; | 1362 | omap_writew(0, OTG_IRQ_EN); |
1334 | if (!isp->otg.default_a) | 1363 | if (!isp->otg.default_a) |
1335 | enable_vbus_draw(isp, 0); | 1364 | enable_vbus_draw(isp, 0); |
1336 | usb_gadget_vbus_disconnect(isp->otg.gadget); | 1365 | usb_gadget_vbus_disconnect(isp->otg.gadget); |
@@ -1351,9 +1380,11 @@ isp1301_set_peripheral(struct otg_transceiver *otg, struct usb_gadget *gadget) | |||
1351 | isp->otg.gadget = gadget; | 1380 | isp->otg.gadget = gadget; |
1352 | // FIXME update its refcount | 1381 | // FIXME update its refcount |
1353 | 1382 | ||
1354 | OTG_CTRL_REG = (OTG_CTRL_REG & OTG_CTRL_MASK | 1383 | l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK; |
1355 | & ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS)) | 1384 | l &= ~(OTG_XCEIV_OUTPUTS|OTG_CTRL_BITS); |
1356 | | OTG_ID; | 1385 | l |= OTG_ID; |
1386 | omap_writel(l, OTG_CTRL); | ||
1387 | |||
1357 | power_up(isp); | 1388 | power_up(isp); |
1358 | isp->otg.state = OTG_STATE_B_IDLE; | 1389 | isp->otg.state = OTG_STATE_B_IDLE; |
1359 | 1390 | ||
@@ -1405,16 +1436,17 @@ isp1301_start_srp(struct otg_transceiver *dev) | |||
1405 | || isp->otg.state != OTG_STATE_B_IDLE) | 1436 | || isp->otg.state != OTG_STATE_B_IDLE) |
1406 | return -ENODEV; | 1437 | return -ENODEV; |
1407 | 1438 | ||
1408 | otg_ctrl = OTG_CTRL_REG; | 1439 | otg_ctrl = omap_readl(OTG_CTRL); |
1409 | if (!(otg_ctrl & OTG_BSESSEND)) | 1440 | if (!(otg_ctrl & OTG_BSESSEND)) |
1410 | return -EINVAL; | 1441 | return -EINVAL; |
1411 | 1442 | ||
1412 | otg_ctrl |= OTG_B_BUSREQ; | 1443 | otg_ctrl |= OTG_B_BUSREQ; |
1413 | otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK; | 1444 | otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK; |
1414 | OTG_CTRL_REG = otg_ctrl; | 1445 | omap_writel(otg_ctrl, OTG_CTRL); |
1415 | isp->otg.state = OTG_STATE_B_SRP_INIT; | 1446 | isp->otg.state = OTG_STATE_B_SRP_INIT; |
1416 | 1447 | ||
1417 | pr_debug("otg: SRP, %s ... %06x\n", state_name(isp), OTG_CTRL_REG); | 1448 | pr_debug("otg: SRP, %s ... %06x\n", state_name(isp), |
1449 | omap_readl(OTG_CTRL)); | ||
1418 | #ifdef CONFIG_USB_OTG | 1450 | #ifdef CONFIG_USB_OTG |
1419 | check_state(isp, __func__); | 1451 | check_state(isp, __func__); |
1420 | #endif | 1452 | #endif |
@@ -1426,6 +1458,7 @@ isp1301_start_hnp(struct otg_transceiver *dev) | |||
1426 | { | 1458 | { |
1427 | #ifdef CONFIG_USB_OTG | 1459 | #ifdef CONFIG_USB_OTG |
1428 | struct isp1301 *isp = container_of(dev, struct isp1301, otg); | 1460 | struct isp1301 *isp = container_of(dev, struct isp1301, otg); |
1461 | u32 l; | ||
1429 | 1462 | ||
1430 | if (!dev || isp != the_transceiver) | 1463 | if (!dev || isp != the_transceiver) |
1431 | return -ENODEV; | 1464 | return -ENODEV; |
@@ -1452,7 +1485,9 @@ isp1301_start_hnp(struct otg_transceiver *dev) | |||
1452 | #endif | 1485 | #endif |
1453 | /* caller must suspend then clear A_BUSREQ */ | 1486 | /* caller must suspend then clear A_BUSREQ */ |
1454 | usb_gadget_vbus_connect(isp->otg.gadget); | 1487 | usb_gadget_vbus_connect(isp->otg.gadget); |
1455 | OTG_CTRL_REG |= OTG_A_SETB_HNPEN; | 1488 | l = omap_readl(OTG_CTRL); |
1489 | l |= OTG_A_SETB_HNPEN; | ||
1490 | omap_writel(l, OTG_CTRL); | ||
1456 | 1491 | ||
1457 | break; | 1492 | break; |
1458 | case OTG_STATE_A_PERIPHERAL: | 1493 | case OTG_STATE_A_PERIPHERAL: |
@@ -1462,7 +1497,7 @@ isp1301_start_hnp(struct otg_transceiver *dev) | |||
1462 | return -EILSEQ; | 1497 | return -EILSEQ; |
1463 | } | 1498 | } |
1464 | pr_debug("otg: HNP %s, %06x ...\n", | 1499 | pr_debug("otg: HNP %s, %06x ...\n", |
1465 | state_name(isp), OTG_CTRL_REG); | 1500 | state_name(isp), omap_readl(OTG_CTRL)); |
1466 | check_state(isp, __func__); | 1501 | check_state(isp, __func__); |
1467 | return 0; | 1502 | return 0; |
1468 | #else | 1503 | #else |
diff --git a/drivers/mmc/host/imxmmc.c b/drivers/mmc/host/imxmmc.c index 95f33e87a99c..eed211b2ac70 100644 --- a/drivers/mmc/host/imxmmc.c +++ b/drivers/mmc/host/imxmmc.c | |||
@@ -42,6 +42,7 @@ | |||
42 | #include <linux/mmc/host.h> | 42 | #include <linux/mmc/host.h> |
43 | #include <linux/mmc/card.h> | 43 | #include <linux/mmc/card.h> |
44 | #include <linux/delay.h> | 44 | #include <linux/delay.h> |
45 | #include <linux/clk.h> | ||
45 | 46 | ||
46 | #include <asm/dma.h> | 47 | #include <asm/dma.h> |
47 | #include <asm/io.h> | 48 | #include <asm/io.h> |
@@ -92,6 +93,8 @@ struct imxmci_host { | |||
92 | unsigned char actual_bus_width; | 93 | unsigned char actual_bus_width; |
93 | 94 | ||
94 | int prev_cmd_code; | 95 | int prev_cmd_code; |
96 | |||
97 | struct clk *clk; | ||
95 | }; | 98 | }; |
96 | 99 | ||
97 | #define IMXMCI_PEND_IRQ_b 0 | 100 | #define IMXMCI_PEND_IRQ_b 0 |
@@ -841,7 +844,7 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
841 | /* The prescaler is 5 for PERCLK2 equal to 96MHz | 844 | /* The prescaler is 5 for PERCLK2 equal to 96MHz |
842 | * then 96MHz / 5 = 19.2 MHz | 845 | * then 96MHz / 5 = 19.2 MHz |
843 | */ | 846 | */ |
844 | clk=imx_get_perclk2(); | 847 | clk = clk_get_rate(host->clk); |
845 | prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE; | 848 | prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE; |
846 | switch(prescaler) { | 849 | switch(prescaler) { |
847 | case 0: | 850 | case 0: |
@@ -994,6 +997,13 @@ static int imxmci_probe(struct platform_device *pdev) | |||
994 | host->res = r; | 997 | host->res = r; |
995 | host->irq = irq; | 998 | host->irq = irq; |
996 | 999 | ||
1000 | host->clk = clk_get(&pdev->dev, "perclk2"); | ||
1001 | if (IS_ERR(host->clk)) { | ||
1002 | ret = PTR_ERR(host->clk); | ||
1003 | goto out; | ||
1004 | } | ||
1005 | clk_enable(host->clk); | ||
1006 | |||
997 | imx_gpio_mode(PB8_PF_SD_DAT0); | 1007 | imx_gpio_mode(PB8_PF_SD_DAT0); |
998 | imx_gpio_mode(PB9_PF_SD_DAT1); | 1008 | imx_gpio_mode(PB9_PF_SD_DAT1); |
999 | imx_gpio_mode(PB10_PF_SD_DAT2); | 1009 | imx_gpio_mode(PB10_PF_SD_DAT2); |
@@ -1017,8 +1027,8 @@ static int imxmci_probe(struct platform_device *pdev) | |||
1017 | host->imask = IMXMCI_INT_MASK_DEFAULT; | 1027 | host->imask = IMXMCI_INT_MASK_DEFAULT; |
1018 | MMC_INT_MASK = host->imask; | 1028 | MMC_INT_MASK = host->imask; |
1019 | 1029 | ||
1020 | 1030 | host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW); | |
1021 | if(imx_dma_request_by_prio(&host->dma, DRIVER_NAME, DMA_PRIO_LOW)<0){ | 1031 | if(host->dma < 0) { |
1022 | dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n"); | 1032 | dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n"); |
1023 | ret = -EBUSY; | 1033 | ret = -EBUSY; |
1024 | goto out; | 1034 | goto out; |
@@ -1053,6 +1063,10 @@ out: | |||
1053 | imx_dma_free(host->dma); | 1063 | imx_dma_free(host->dma); |
1054 | host->dma_allocated=0; | 1064 | host->dma_allocated=0; |
1055 | } | 1065 | } |
1066 | if (host->clk) { | ||
1067 | clk_disable(host->clk); | ||
1068 | clk_put(host->clk); | ||
1069 | } | ||
1056 | } | 1070 | } |
1057 | if (mmc) | 1071 | if (mmc) |
1058 | mmc_free_host(mmc); | 1072 | mmc_free_host(mmc); |
@@ -1082,6 +1096,9 @@ static int imxmci_remove(struct platform_device *pdev) | |||
1082 | 1096 | ||
1083 | tasklet_kill(&host->tasklet); | 1097 | tasklet_kill(&host->tasklet); |
1084 | 1098 | ||
1099 | clk_disable(host->clk); | ||
1100 | clk_put(host->clk); | ||
1101 | |||
1085 | release_resource(host->res); | 1102 | release_resource(host->res); |
1086 | 1103 | ||
1087 | mmc_free_host(mmc); | 1104 | mmc_free_host(mmc); |
diff --git a/drivers/mtd/maps/omap_nor.c b/drivers/mtd/maps/omap_nor.c index c12d8056bebd..68eec6c6c517 100644 --- a/drivers/mtd/maps/omap_nor.c +++ b/drivers/mtd/maps/omap_nor.c | |||
@@ -60,13 +60,22 @@ struct omapflash_info { | |||
60 | static void omap_set_vpp(struct map_info *map, int enable) | 60 | static void omap_set_vpp(struct map_info *map, int enable) |
61 | { | 61 | { |
62 | static int count; | 62 | static int count; |
63 | 63 | u32 l; | |
64 | if (enable) { | 64 | |
65 | if (count++ == 0) | 65 | if (cpu_class_is_omap1()) { |
66 | OMAP_EMIFS_CONFIG_REG |= OMAP_EMIFS_CONFIG_WP; | 66 | if (enable) { |
67 | } else { | 67 | if (count++ == 0) { |
68 | if (count && (--count == 0)) | 68 | l = omap_readl(EMIFS_CONFIG); |
69 | OMAP_EMIFS_CONFIG_REG &= ~OMAP_EMIFS_CONFIG_WP; | 69 | l |= OMAP_EMIFS_CONFIG_WP; |
70 | omap_writel(l, EMIFS_CONFIG); | ||
71 | } | ||
72 | } else { | ||
73 | if (count && (--count == 0)) { | ||
74 | l = omap_readl(EMIFS_CONFIG); | ||
75 | l &= ~OMAP_EMIFS_CONFIG_WP; | ||
76 | omap_writel(l, EMIFS_CONFIG); | ||
77 | } | ||
78 | } | ||
70 | } | 79 | } |
71 | } | 80 | } |
72 | 81 | ||
diff --git a/drivers/mtd/nand/orion_nand.c b/drivers/mtd/nand/orion_nand.c index 59e05a1c50cf..ee2ac3948cd8 100644 --- a/drivers/mtd/nand/orion_nand.c +++ b/drivers/mtd/nand/orion_nand.c | |||
@@ -85,6 +85,9 @@ static int __init orion_nand_probe(struct platform_device *pdev) | |||
85 | nc->cmd_ctrl = orion_nand_cmd_ctrl; | 85 | nc->cmd_ctrl = orion_nand_cmd_ctrl; |
86 | nc->ecc.mode = NAND_ECC_SOFT; | 86 | nc->ecc.mode = NAND_ECC_SOFT; |
87 | 87 | ||
88 | if (board->chip_delay) | ||
89 | nc->chip_delay = board->chip_delay; | ||
90 | |||
88 | if (board->width == 16) | 91 | if (board->width == 16) |
89 | nc->options |= NAND_BUSWIDTH_16; | 92 | nc->options |= NAND_BUSWIDTH_16; |
90 | 93 | ||
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index f4182cfffe9d..45a41b597da9 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
@@ -217,7 +217,7 @@ config MII | |||
217 | 217 | ||
218 | config MACB | 218 | config MACB |
219 | tristate "Atmel MACB support" | 219 | tristate "Atmel MACB support" |
220 | depends on AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263 || ARCH_AT91CAP9 | 220 | depends on AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263 || ARCH_AT91SAM9G20 || ARCH_AT91CAP9 |
221 | select PHYLIB | 221 | select PHYLIB |
222 | help | 222 | help |
223 | The Atmel MACB ethernet interface is found on many AT32 and AT91 | 223 | The Atmel MACB ethernet interface is found on many AT32 and AT91 |
diff --git a/drivers/net/arm/etherh.c b/drivers/net/arm/etherh.c index 00081d2b9cd5..e9d15eccad08 100644 --- a/drivers/net/arm/etherh.c +++ b/drivers/net/arm/etherh.c | |||
@@ -647,7 +647,7 @@ etherh_probe(struct expansion_card *ec, const struct ecard_id *id) | |||
647 | struct ei_device *ei_local; | 647 | struct ei_device *ei_local; |
648 | struct net_device *dev; | 648 | struct net_device *dev; |
649 | struct etherh_priv *eh; | 649 | struct etherh_priv *eh; |
650 | int i, ret; | 650 | int ret; |
651 | DECLARE_MAC_BUF(mac); | 651 | DECLARE_MAC_BUF(mac); |
652 | 652 | ||
653 | etherh_banner(); | 653 | etherh_banner(); |
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c index d5c2d27f3ea4..f76b0b6c277d 100644 --- a/drivers/net/irda/pxaficp_ir.c +++ b/drivers/net/irda/pxaficp_ir.c | |||
@@ -13,16 +13,8 @@ | |||
13 | * | 13 | * |
14 | */ | 14 | */ |
15 | #include <linux/module.h> | 15 | #include <linux/module.h> |
16 | #include <linux/types.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/errno.h> | ||
19 | #include <linux/netdevice.h> | 16 | #include <linux/netdevice.h> |
20 | #include <linux/slab.h> | ||
21 | #include <linux/rtnetlink.h> | ||
22 | #include <linux/interrupt.h> | ||
23 | #include <linux/dma-mapping.h> | ||
24 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
25 | #include <linux/pm.h> | ||
26 | #include <linux/clk.h> | 18 | #include <linux/clk.h> |
27 | 19 | ||
28 | #include <net/irda/irda.h> | 20 | #include <net/irda/irda.h> |
@@ -30,17 +22,9 @@ | |||
30 | #include <net/irda/wrapper.h> | 22 | #include <net/irda/wrapper.h> |
31 | #include <net/irda/irda_device.h> | 23 | #include <net/irda/irda_device.h> |
32 | 24 | ||
33 | #include <asm/irq.h> | ||
34 | #include <asm/dma.h> | 25 | #include <asm/dma.h> |
35 | #include <asm/delay.h> | ||
36 | #include <asm/hardware.h> | ||
37 | #include <asm/arch/irda.h> | 26 | #include <asm/arch/irda.h> |
38 | #include <asm/arch/pxa-regs.h> | 27 | #include <asm/arch/pxa-regs.h> |
39 | #include <asm/arch/pxa2xx-gpio.h> | ||
40 | |||
41 | #ifdef CONFIG_MACH_MAINSTONE | ||
42 | #include <asm/arch/mainstone.h> | ||
43 | #endif | ||
44 | 28 | ||
45 | #define IrSR_RXPL_NEG_IS_ZERO (1<<4) | 29 | #define IrSR_RXPL_NEG_IS_ZERO (1<<4) |
46 | #define IrSR_RXPL_POS_IS_ZERO 0x0 | 30 | #define IrSR_RXPL_POS_IS_ZERO 0x0 |
@@ -163,10 +147,6 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed) | |||
163 | /* set board transceiver to SIR mode */ | 147 | /* set board transceiver to SIR mode */ |
164 | si->pdata->transceiver_mode(si->dev, IR_SIRMODE); | 148 | si->pdata->transceiver_mode(si->dev, IR_SIRMODE); |
165 | 149 | ||
166 | /* configure GPIO46/47 */ | ||
167 | pxa_gpio_mode(GPIO46_STRXD_MD); | ||
168 | pxa_gpio_mode(GPIO47_STTXD_MD); | ||
169 | |||
170 | /* enable the STUART clock */ | 150 | /* enable the STUART clock */ |
171 | pxa_irda_enable_sirclk(si); | 151 | pxa_irda_enable_sirclk(si); |
172 | } | 152 | } |
@@ -201,10 +181,6 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed) | |||
201 | /* set board transceiver to FIR mode */ | 181 | /* set board transceiver to FIR mode */ |
202 | si->pdata->transceiver_mode(si->dev, IR_FIRMODE); | 182 | si->pdata->transceiver_mode(si->dev, IR_FIRMODE); |
203 | 183 | ||
204 | /* configure GPIO46/47 */ | ||
205 | pxa_gpio_mode(GPIO46_ICPRXD_MD); | ||
206 | pxa_gpio_mode(GPIO47_ICPTXD_MD); | ||
207 | |||
208 | /* enable the FICP clock */ | 184 | /* enable the FICP clock */ |
209 | pxa_irda_enable_firclk(si); | 185 | pxa_irda_enable_firclk(si); |
210 | 186 | ||
diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c index 46314b420765..569b746b5731 100644 --- a/drivers/pcmcia/omap_cf.c +++ b/drivers/pcmcia/omap_cf.c | |||
@@ -38,19 +38,19 @@ | |||
38 | #define CF_BASE 0xfffe2800 | 38 | #define CF_BASE 0xfffe2800 |
39 | 39 | ||
40 | /* status; read after IRQ */ | 40 | /* status; read after IRQ */ |
41 | #define CF_STATUS_REG __REG16(CF_BASE + 0x00) | 41 | #define CF_STATUS (CF_BASE + 0x00) |
42 | # define CF_STATUS_BAD_READ (1 << 2) | 42 | # define CF_STATUS_BAD_READ (1 << 2) |
43 | # define CF_STATUS_BAD_WRITE (1 << 1) | 43 | # define CF_STATUS_BAD_WRITE (1 << 1) |
44 | # define CF_STATUS_CARD_DETECT (1 << 0) | 44 | # define CF_STATUS_CARD_DETECT (1 << 0) |
45 | 45 | ||
46 | /* which chipselect (CS0..CS3) is used for CF (active low) */ | 46 | /* which chipselect (CS0..CS3) is used for CF (active low) */ |
47 | #define CF_CFG_REG __REG16(CF_BASE + 0x02) | 47 | #define CF_CFG (CF_BASE + 0x02) |
48 | 48 | ||
49 | /* card reset */ | 49 | /* card reset */ |
50 | #define CF_CONTROL_REG __REG16(CF_BASE + 0x04) | 50 | #define CF_CONTROL (CF_BASE + 0x04) |
51 | # define CF_CONTROL_RESET (1 << 0) | 51 | # define CF_CONTROL_RESET (1 << 0) |
52 | 52 | ||
53 | #define omap_cf_present() (!(CF_STATUS_REG & CF_STATUS_CARD_DETECT)) | 53 | #define omap_cf_present() (!(omap_readw(CF_STATUS) & CF_STATUS_CARD_DETECT)) |
54 | 54 | ||
55 | /*--------------------------------------------------------------------------*/ | 55 | /*--------------------------------------------------------------------------*/ |
56 | 56 | ||
@@ -139,11 +139,11 @@ omap_cf_set_socket(struct pcmcia_socket *sock, struct socket_state_t *s) | |||
139 | return -EINVAL; | 139 | return -EINVAL; |
140 | } | 140 | } |
141 | 141 | ||
142 | control = CF_CONTROL_REG; | 142 | control = omap_readw(CF_CONTROL); |
143 | if (s->flags & SS_RESET) | 143 | if (s->flags & SS_RESET) |
144 | CF_CONTROL_REG = CF_CONTROL_RESET; | 144 | omap_writew(CF_CONTROL_RESET, CF_CONTROL); |
145 | else | 145 | else |
146 | CF_CONTROL_REG = 0; | 146 | omap_writew(0, CF_CONTROL); |
147 | 147 | ||
148 | pr_debug("%s: Vcc %d, io_irq %d, flags %04x csc %04x\n", | 148 | pr_debug("%s: Vcc %d, io_irq %d, flags %04x csc %04x\n", |
149 | driver_name, s->Vcc, s->io_irq, s->flags, s->csc_mask); | 149 | driver_name, s->Vcc, s->io_irq, s->flags, s->csc_mask); |
@@ -270,7 +270,7 @@ static int __init omap_cf_probe(struct platform_device *pdev) | |||
270 | omap_cfg_reg(V10_1610_CF_IREQ); | 270 | omap_cfg_reg(V10_1610_CF_IREQ); |
271 | omap_cfg_reg(W10_1610_CF_RESET); | 271 | omap_cfg_reg(W10_1610_CF_RESET); |
272 | 272 | ||
273 | CF_CFG_REG = ~(1 << seg); | 273 | omap_writew(~(1 << seg), CF_CFG); |
274 | 274 | ||
275 | pr_info("%s: cs%d on irq %d\n", driver_name, seg, irq); | 275 | pr_info("%s: cs%d on irq %d\n", driver_name, seg, irq); |
276 | 276 | ||
@@ -279,14 +279,15 @@ static int __init omap_cf_probe(struct platform_device *pdev) | |||
279 | * CF/PCMCIA variants... | 279 | * CF/PCMCIA variants... |
280 | */ | 280 | */ |
281 | pr_debug("%s: cs%d, previous ccs %08x acs %08x\n", driver_name, | 281 | pr_debug("%s: cs%d, previous ccs %08x acs %08x\n", driver_name, |
282 | seg, EMIFS_CCS(seg), EMIFS_ACS(seg)); | 282 | seg, omap_readl(EMIFS_CCS(seg)), omap_readl(EMIFS_ACS(seg))); |
283 | EMIFS_CCS(seg) = 0x0004a1b3; /* synch mode 4 etc */ | 283 | omap_writel(0x0004a1b3, EMIFS_CCS(seg)); /* synch mode 4 etc */ |
284 | EMIFS_ACS(seg) = 0x00000000; /* OE hold/setup */ | 284 | omap_writel(0x00000000, EMIFS_ACS(seg)); /* OE hold/setup */ |
285 | 285 | ||
286 | /* CF uses armxor_ck, which is "always" available */ | 286 | /* CF uses armxor_ck, which is "always" available */ |
287 | 287 | ||
288 | pr_debug("%s: sts %04x cfg %04x control %04x %s\n", driver_name, | 288 | pr_debug("%s: sts %04x cfg %04x control %04x %s\n", driver_name, |
289 | CF_STATUS_REG, CF_CFG_REG, CF_CONTROL_REG, | 289 | omap_readw(CF_STATUS), omap_readw(CF_CFG), |
290 | omap_readw(CF_CONTROL), | ||
290 | omap_cf_present() ? "present" : "(not present)"); | 291 | omap_cf_present() ? "present" : "(not present)"); |
291 | 292 | ||
292 | cf->socket.owner = THIS_MODULE; | 293 | cf->socket.owner = THIS_MODULE; |
diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c index e7ab060ff118..f123fce65f2e 100644 --- a/drivers/pcmcia/pxa2xx_cm_x270.c +++ b/drivers/pcmcia/pxa2xx_cm_x270.c | |||
@@ -18,6 +18,7 @@ | |||
18 | 18 | ||
19 | #include <pcmcia/ss.h> | 19 | #include <pcmcia/ss.h> |
20 | #include <asm/hardware.h> | 20 | #include <asm/hardware.h> |
21 | #include <asm/mach-types.h> | ||
21 | 22 | ||
22 | #include <asm/arch/pxa-regs.h> | 23 | #include <asm/arch/pxa-regs.h> |
23 | #include <asm/arch/pxa2xx-gpio.h> | 24 | #include <asm/arch/pxa2xx-gpio.h> |
@@ -130,7 +131,7 @@ static void cmx270_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) | |||
130 | } | 131 | } |
131 | 132 | ||
132 | 133 | ||
133 | static struct pcmcia_low_level cmx270_pcmcia_ops = { | 134 | static struct pcmcia_low_level cmx270_pcmcia_ops __initdata = { |
134 | .owner = THIS_MODULE, | 135 | .owner = THIS_MODULE, |
135 | .hw_init = cmx270_pcmcia_hw_init, | 136 | .hw_init = cmx270_pcmcia_hw_init, |
136 | .hw_shutdown = cmx270_pcmcia_shutdown, | 137 | .hw_shutdown = cmx270_pcmcia_shutdown, |
@@ -147,15 +148,21 @@ static int __init cmx270_pcmcia_init(void) | |||
147 | { | 148 | { |
148 | int ret; | 149 | int ret; |
149 | 150 | ||
151 | if (!machine_is_armcore()) | ||
152 | return -ENODEV; | ||
153 | |||
150 | cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); | 154 | cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); |
151 | 155 | ||
152 | if (!cmx270_pcmcia_device) | 156 | if (!cmx270_pcmcia_device) |
153 | return -ENOMEM; | 157 | return -ENOMEM; |
154 | 158 | ||
155 | cmx270_pcmcia_device->dev.platform_data = &cmx270_pcmcia_ops; | 159 | ret = platform_device_add_data(cmx270_pcmcia_device, &cmx270_pcmcia_ops, |
160 | sizeof(cmx270_pcmcia_ops)); | ||
156 | 161 | ||
157 | printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n"); | 162 | if (ret == 0) { |
158 | ret = platform_device_add(cmx270_pcmcia_device); | 163 | printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n"); |
164 | ret = platform_device_add(cmx270_pcmcia_device); | ||
165 | } | ||
159 | 166 | ||
160 | if (ret) | 167 | if (ret) |
161 | platform_device_put(cmx270_pcmcia_device); | 168 | platform_device_put(cmx270_pcmcia_device); |
diff --git a/drivers/pcmcia/pxa2xx_mainstone.c b/drivers/pcmcia/pxa2xx_mainstone.c index 145b85e0f02c..92d1cc33808c 100644 --- a/drivers/pcmcia/pxa2xx_mainstone.c +++ b/drivers/pcmcia/pxa2xx_mainstone.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <pcmcia/ss.h> | 22 | #include <pcmcia/ss.h> |
23 | 23 | ||
24 | #include <asm/hardware.h> | 24 | #include <asm/hardware.h> |
25 | #include <asm/mach-types.h> | ||
25 | #include <asm/irq.h> | 26 | #include <asm/irq.h> |
26 | 27 | ||
27 | #include <asm/arch/pxa-regs.h> | 28 | #include <asm/arch/pxa-regs.h> |
@@ -136,7 +137,7 @@ static void mst_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) | |||
136 | { | 137 | { |
137 | } | 138 | } |
138 | 139 | ||
139 | static struct pcmcia_low_level mst_pcmcia_ops = { | 140 | static struct pcmcia_low_level mst_pcmcia_ops __initdata = { |
140 | .owner = THIS_MODULE, | 141 | .owner = THIS_MODULE, |
141 | .hw_init = mst_pcmcia_hw_init, | 142 | .hw_init = mst_pcmcia_hw_init, |
142 | .hw_shutdown = mst_pcmcia_hw_shutdown, | 143 | .hw_shutdown = mst_pcmcia_hw_shutdown, |
@@ -153,13 +154,17 @@ static int __init mst_pcmcia_init(void) | |||
153 | { | 154 | { |
154 | int ret; | 155 | int ret; |
155 | 156 | ||
157 | if (!machine_is_mainstone()) | ||
158 | return -ENODEV; | ||
159 | |||
156 | mst_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); | 160 | mst_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); |
157 | if (!mst_pcmcia_device) | 161 | if (!mst_pcmcia_device) |
158 | return -ENOMEM; | 162 | return -ENOMEM; |
159 | 163 | ||
160 | mst_pcmcia_device->dev.platform_data = &mst_pcmcia_ops; | 164 | ret = platform_device_add_data(mst_pcmcia_device, &mst_pcmcia_ops, |
161 | 165 | sizeof(mst_pcmcia_ops)); | |
162 | ret = platform_device_add(mst_pcmcia_device); | 166 | if (ret == 0) |
167 | ret = platform_device_add(mst_pcmcia_device); | ||
163 | 168 | ||
164 | if (ret) | 169 | if (ret) |
165 | platform_device_put(mst_pcmcia_device); | 170 | platform_device_put(mst_pcmcia_device); |
diff --git a/drivers/pcmcia/pxa2xx_sharpsl.c b/drivers/pcmcia/pxa2xx_sharpsl.c index d5c33bd78d68..d71f93d45833 100644 --- a/drivers/pcmcia/pxa2xx_sharpsl.c +++ b/drivers/pcmcia/pxa2xx_sharpsl.c | |||
@@ -222,7 +222,7 @@ static void sharpsl_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) | |||
222 | sharpsl_pcmcia_init_reset(skt); | 222 | sharpsl_pcmcia_init_reset(skt); |
223 | } | 223 | } |
224 | 224 | ||
225 | static struct pcmcia_low_level sharpsl_pcmcia_ops = { | 225 | static struct pcmcia_low_level sharpsl_pcmcia_ops __initdata = { |
226 | .owner = THIS_MODULE, | 226 | .owner = THIS_MODULE, |
227 | .hw_init = sharpsl_pcmcia_hw_init, | 227 | .hw_init = sharpsl_pcmcia_hw_init, |
228 | .hw_shutdown = sharpsl_pcmcia_hw_shutdown, | 228 | .hw_shutdown = sharpsl_pcmcia_hw_shutdown, |
@@ -261,10 +261,12 @@ static int __init sharpsl_pcmcia_init(void) | |||
261 | if (!sharpsl_pcmcia_device) | 261 | if (!sharpsl_pcmcia_device) |
262 | return -ENOMEM; | 262 | return -ENOMEM; |
263 | 263 | ||
264 | sharpsl_pcmcia_device->dev.platform_data = &sharpsl_pcmcia_ops; | 264 | ret = platform_device_add_data(sharpsl_pcmcia_device, |
265 | sharpsl_pcmcia_device->dev.parent = platform_scoop_config->devs[0].dev; | 265 | &sharpsl_pcmcia_ops, sizeof(sharpsl_pcmcia_ops)); |
266 | 266 | if (ret == 0) { | |
267 | ret = platform_device_add(sharpsl_pcmcia_device); | 267 | sharpsl_pcmcia_device->dev.parent = platform_scoop_config->devs[0].dev; |
268 | ret = platform_device_add(sharpsl_pcmcia_device); | ||
269 | } | ||
268 | 270 | ||
269 | if (ret) | 271 | if (ret) |
270 | platform_device_put(sharpsl_pcmcia_device); | 272 | platform_device_put(sharpsl_pcmcia_device); |
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 4949dc4859be..fc85bf2e4a97 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig | |||
@@ -469,6 +469,16 @@ config RTC_DRV_VR41XX | |||
469 | To compile this driver as a module, choose M here: the | 469 | To compile this driver as a module, choose M here: the |
470 | module will be called rtc-vr41xx. | 470 | module will be called rtc-vr41xx. |
471 | 471 | ||
472 | config RTC_DRV_PL030 | ||
473 | tristate "ARM AMBA PL030 RTC" | ||
474 | depends on ARM_AMBA | ||
475 | help | ||
476 | If you say Y here you will get access to ARM AMBA | ||
477 | PrimeCell PL030 RTC found on certain ARM SOCs. | ||
478 | |||
479 | To compile this driver as a module, choose M here: the | ||
480 | module will be called rtc-pl030. | ||
481 | |||
472 | config RTC_DRV_PL031 | 482 | config RTC_DRV_PL031 |
473 | tristate "ARM AMBA PL031 RTC" | 483 | tristate "ARM AMBA PL031 RTC" |
474 | depends on ARM_AMBA | 484 | depends on ARM_AMBA |
@@ -495,12 +505,13 @@ config RTC_DRV_AT91RM9200 | |||
495 | this is powered by the backup power supply. | 505 | this is powered by the backup power supply. |
496 | 506 | ||
497 | config RTC_DRV_AT91SAM9 | 507 | config RTC_DRV_AT91SAM9 |
498 | tristate "AT91SAM9x" | 508 | tristate "AT91SAM9x/AT91CAP9" |
499 | depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40) | 509 | depends on ARCH_AT91 && !(ARCH_AT91RM9200 || ARCH_AT91X40) |
500 | help | 510 | help |
501 | RTC driver for the Atmel AT91SAM9x internal RTT (Real Time Timer). | 511 | RTC driver for the Atmel AT91SAM9x and AT91CAP9 internal RTT |
502 | These timers are powered by the backup power supply (such as a | 512 | (Real Time Timer). These timers are powered by the backup power |
503 | small coin cell battery), but do not need to be used as RTCs. | 513 | supply (such as a small coin cell battery), but do not need to |
514 | be used as RTCs. | ||
504 | 515 | ||
505 | (On AT91SAM9rl chips you probably want to use the dedicated RTC | 516 | (On AT91SAM9rl chips you probably want to use the dedicated RTC |
506 | module and leave the RTT available for other uses.) | 517 | module and leave the RTT available for other uses.) |
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index b6e14d51670b..b5d9d67df887 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile | |||
@@ -41,6 +41,7 @@ obj-$(CONFIG_RTC_DRV_MAX6902) += rtc-max6902.o | |||
41 | obj-$(CONFIG_RTC_DRV_OMAP) += rtc-omap.o | 41 | obj-$(CONFIG_RTC_DRV_OMAP) += rtc-omap.o |
42 | obj-$(CONFIG_RTC_DRV_PCF8563) += rtc-pcf8563.o | 42 | obj-$(CONFIG_RTC_DRV_PCF8563) += rtc-pcf8563.o |
43 | obj-$(CONFIG_RTC_DRV_PCF8583) += rtc-pcf8583.o | 43 | obj-$(CONFIG_RTC_DRV_PCF8583) += rtc-pcf8583.o |
44 | obj-$(CONFIG_RTC_DRV_PL030) += rtc-pl030.o | ||
44 | obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o | 45 | obj-$(CONFIG_RTC_DRV_PL031) += rtc-pl031.o |
45 | obj-$(CONFIG_RTC_DRV_PPC) += rtc-ppc.o | 46 | obj-$(CONFIG_RTC_DRV_PPC) += rtc-ppc.o |
46 | obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o | 47 | obj-$(CONFIG_RTC_DRV_R9701) += rtc-r9701.o |
diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c index 39e64ab1ecb7..9c3db934cc24 100644 --- a/drivers/rtc/rtc-at91rm9200.c +++ b/drivers/rtc/rtc-at91rm9200.c | |||
@@ -29,10 +29,6 @@ | |||
29 | #include <linux/completion.h> | 29 | #include <linux/completion.h> |
30 | 30 | ||
31 | #include <asm/uaccess.h> | 31 | #include <asm/uaccess.h> |
32 | #include <asm/rtc.h> | ||
33 | |||
34 | #include <asm/mach/time.h> | ||
35 | |||
36 | #include <asm/arch/at91_rtc.h> | 32 | #include <asm/arch/at91_rtc.h> |
37 | 33 | ||
38 | 34 | ||
diff --git a/drivers/rtc/rtc-at91sam9.c b/drivers/rtc/rtc-at91sam9.c index 38d8742a4bdf..f0246ef413a4 100644 --- a/drivers/rtc/rtc-at91sam9.c +++ b/drivers/rtc/rtc-at91sam9.c | |||
@@ -19,7 +19,6 @@ | |||
19 | #include <linux/interrupt.h> | 19 | #include <linux/interrupt.h> |
20 | #include <linux/ioctl.h> | 20 | #include <linux/ioctl.h> |
21 | 21 | ||
22 | #include <asm/mach/time.h> | ||
23 | #include <asm/arch/board.h> | 22 | #include <asm/arch/board.h> |
24 | #include <asm/arch/at91_rtt.h> | 23 | #include <asm/arch/at91_rtt.h> |
25 | 24 | ||
diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c index 58f81c774943..eb23d8423f42 100644 --- a/drivers/rtc/rtc-omap.c +++ b/drivers/rtc/rtc-omap.c | |||
@@ -22,7 +22,6 @@ | |||
22 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
23 | 23 | ||
24 | #include <asm/io.h> | 24 | #include <asm/io.h> |
25 | #include <asm/mach/time.h> | ||
26 | 25 | ||
27 | 26 | ||
28 | /* The OMAP1 RTC is a year/month/day/hours/minutes/seconds BCD clock | 27 | /* The OMAP1 RTC is a year/month/day/hours/minutes/seconds BCD clock |
diff --git a/drivers/rtc/rtc-pl030.c b/drivers/rtc/rtc-pl030.c new file mode 100644 index 000000000000..8448eeb9d675 --- /dev/null +++ b/drivers/rtc/rtc-pl030.c | |||
@@ -0,0 +1,217 @@ | |||
1 | /* | ||
2 | * linux/drivers/rtc/rtc-pl030.c | ||
3 | * | ||
4 | * Copyright (C) 2000-2001 Deep Blue Solutions Ltd. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #include <linux/module.h> | ||
11 | #include <linux/rtc.h> | ||
12 | #include <linux/init.h> | ||
13 | #include <linux/interrupt.h> | ||
14 | #include <linux/amba/bus.h> | ||
15 | #include <linux/io.h> | ||
16 | |||
17 | #define RTC_DR (0) | ||
18 | #define RTC_MR (4) | ||
19 | #define RTC_STAT (8) | ||
20 | #define RTC_EOI (8) | ||
21 | #define RTC_LR (12) | ||
22 | #define RTC_CR (16) | ||
23 | #define RTC_CR_MIE (1 << 0) | ||
24 | |||
25 | struct pl030_rtc { | ||
26 | struct rtc_device *rtc; | ||
27 | void __iomem *base; | ||
28 | }; | ||
29 | |||
30 | static irqreturn_t pl030_interrupt(int irq, void *dev_id) | ||
31 | { | ||
32 | struct pl030_rtc *rtc = dev_id; | ||
33 | writel(0, rtc->base + RTC_EOI); | ||
34 | return IRQ_HANDLED; | ||
35 | } | ||
36 | |||
37 | static int pl030_open(struct device *dev) | ||
38 | { | ||
39 | return 0; | ||
40 | } | ||
41 | |||
42 | static void pl030_release(struct device *dev) | ||
43 | { | ||
44 | } | ||
45 | |||
46 | static int pl030_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) | ||
47 | { | ||
48 | return -ENOIOCTLCMD; | ||
49 | } | ||
50 | |||
51 | static int pl030_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) | ||
52 | { | ||
53 | struct pl030_rtc *rtc = dev_get_drvdata(dev); | ||
54 | |||
55 | rtc_time_to_tm(readl(rtc->base + RTC_MR), &alrm->time); | ||
56 | return 0; | ||
57 | } | ||
58 | |||
59 | static int pl030_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) | ||
60 | { | ||
61 | struct pl030_rtc *rtc = dev_get_drvdata(dev); | ||
62 | unsigned long time; | ||
63 | int ret; | ||
64 | |||
65 | /* | ||
66 | * At the moment, we can only deal with non-wildcarded alarm times. | ||
67 | */ | ||
68 | ret = rtc_valid_tm(&alrm->time); | ||
69 | if (ret == 0) | ||
70 | ret = rtc_tm_to_time(&alrm->time, &time); | ||
71 | if (ret == 0) | ||
72 | writel(time, rtc->base + RTC_MR); | ||
73 | return ret; | ||
74 | } | ||
75 | |||
76 | static int pl030_read_time(struct device *dev, struct rtc_time *tm) | ||
77 | { | ||
78 | struct pl030_rtc *rtc = dev_get_drvdata(dev); | ||
79 | |||
80 | rtc_time_to_tm(readl(rtc->base + RTC_DR), tm); | ||
81 | |||
82 | return 0; | ||
83 | } | ||
84 | |||
85 | /* | ||
86 | * Set the RTC time. Unfortunately, we can't accurately set | ||
87 | * the point at which the counter updates. | ||
88 | * | ||
89 | * Also, since RTC_LR is transferred to RTC_CR on next rising | ||
90 | * edge of the 1Hz clock, we must write the time one second | ||
91 | * in advance. | ||
92 | */ | ||
93 | static int pl030_set_time(struct device *dev, struct rtc_time *tm) | ||
94 | { | ||
95 | struct pl030_rtc *rtc = dev_get_drvdata(dev); | ||
96 | unsigned long time; | ||
97 | int ret; | ||
98 | |||
99 | ret = rtc_tm_to_time(tm, &time); | ||
100 | if (ret == 0) | ||
101 | writel(time + 1, rtc->base + RTC_LR); | ||
102 | |||
103 | return ret; | ||
104 | } | ||
105 | |||
106 | static const struct rtc_class_ops pl030_ops = { | ||
107 | .open = pl030_open, | ||
108 | .release = pl030_release, | ||
109 | .ioctl = pl030_ioctl, | ||
110 | .read_time = pl030_read_time, | ||
111 | .set_time = pl030_set_time, | ||
112 | .read_alarm = pl030_read_alarm, | ||
113 | .set_alarm = pl030_set_alarm, | ||
114 | }; | ||
115 | |||
116 | static int pl030_probe(struct amba_device *dev, void *id) | ||
117 | { | ||
118 | struct pl030_rtc *rtc; | ||
119 | int ret; | ||
120 | |||
121 | ret = amba_request_regions(dev, NULL); | ||
122 | if (ret) | ||
123 | goto err_req; | ||
124 | |||
125 | rtc = kmalloc(sizeof(*rtc), GFP_KERNEL); | ||
126 | if (!rtc) { | ||
127 | ret = -ENOMEM; | ||
128 | goto err_rtc; | ||
129 | } | ||
130 | |||
131 | rtc->base = ioremap(dev->res.start, SZ_4K); | ||
132 | if (!rtc->base) { | ||
133 | ret = -ENOMEM; | ||
134 | goto err_map; | ||
135 | } | ||
136 | |||
137 | __raw_writel(0, rtc->base + RTC_CR); | ||
138 | __raw_writel(0, rtc->base + RTC_EOI); | ||
139 | |||
140 | amba_set_drvdata(dev, rtc); | ||
141 | |||
142 | ret = request_irq(dev->irq[0], pl030_interrupt, IRQF_DISABLED, | ||
143 | "rtc-pl030", rtc); | ||
144 | if (ret) | ||
145 | goto err_irq; | ||
146 | |||
147 | rtc->rtc = rtc_device_register("pl030", &dev->dev, &pl030_ops, | ||
148 | THIS_MODULE); | ||
149 | if (IS_ERR(rtc->rtc)) { | ||
150 | ret = PTR_ERR(rtc->rtc); | ||
151 | goto err_reg; | ||
152 | } | ||
153 | |||
154 | return 0; | ||
155 | |||
156 | err_reg: | ||
157 | free_irq(dev->irq[0], rtc); | ||
158 | err_irq: | ||
159 | iounmap(rtc->base); | ||
160 | err_map: | ||
161 | kfree(rtc); | ||
162 | err_rtc: | ||
163 | amba_release_regions(dev); | ||
164 | err_req: | ||
165 | return ret; | ||
166 | } | ||
167 | |||
168 | static int pl030_remove(struct amba_device *dev) | ||
169 | { | ||
170 | struct pl030_rtc *rtc = amba_get_drvdata(dev); | ||
171 | |||
172 | amba_set_drvdata(dev, NULL); | ||
173 | |||
174 | writel(0, rtc->base + RTC_CR); | ||
175 | |||
176 | free_irq(dev->irq[0], rtc); | ||
177 | rtc_device_unregister(rtc->rtc); | ||
178 | iounmap(rtc->base); | ||
179 | kfree(rtc); | ||
180 | amba_release_regions(dev); | ||
181 | |||
182 | return 0; | ||
183 | } | ||
184 | |||
185 | static struct amba_id pl030_ids[] = { | ||
186 | { | ||
187 | .id = 0x00041030, | ||
188 | .mask = 0x000fffff, | ||
189 | }, | ||
190 | { 0, 0 }, | ||
191 | }; | ||
192 | |||
193 | static struct amba_driver pl030_driver = { | ||
194 | .drv = { | ||
195 | .name = "rtc-pl030", | ||
196 | }, | ||
197 | .probe = pl030_probe, | ||
198 | .remove = pl030_remove, | ||
199 | .id_table = pl030_ids, | ||
200 | }; | ||
201 | |||
202 | static int __init pl030_init(void) | ||
203 | { | ||
204 | return amba_driver_register(&pl030_driver); | ||
205 | } | ||
206 | |||
207 | static void __exit pl030_exit(void) | ||
208 | { | ||
209 | amba_driver_unregister(&pl030_driver); | ||
210 | } | ||
211 | |||
212 | module_init(pl030_init); | ||
213 | module_exit(pl030_exit); | ||
214 | |||
215 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); | ||
216 | MODULE_DESCRIPTION("ARM AMBA PL030 RTC Driver"); | ||
217 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/rtc/rtc-pl031.c b/drivers/rtc/rtc-pl031.c index 2fd49edcc712..08b4610ec5a6 100644 --- a/drivers/rtc/rtc-pl031.c +++ b/drivers/rtc/rtc-pl031.c | |||
@@ -12,23 +12,12 @@ | |||
12 | * as published by the Free Software Foundation; either version | 12 | * as published by the Free Software Foundation; either version |
13 | * 2 of the License, or (at your option) any later version. | 13 | * 2 of the License, or (at your option) any later version. |
14 | */ | 14 | */ |
15 | |||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/module.h> | 15 | #include <linux/module.h> |
18 | #include <linux/rtc.h> | 16 | #include <linux/rtc.h> |
19 | #include <linux/init.h> | 17 | #include <linux/init.h> |
20 | #include <linux/fs.h> | ||
21 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
22 | #include <linux/string.h> | ||
23 | #include <linux/pm.h> | ||
24 | #include <linux/bitops.h> | ||
25 | |||
26 | #include <linux/amba/bus.h> | 19 | #include <linux/amba/bus.h> |
27 | 20 | #include <linux/io.h> | |
28 | #include <asm/io.h> | ||
29 | #include <asm/hardware.h> | ||
30 | #include <asm/irq.h> | ||
31 | #include <asm/rtc.h> | ||
32 | 21 | ||
33 | /* | 22 | /* |
34 | * Register definitions | 23 | * Register definitions |
@@ -142,13 +131,12 @@ static int pl031_remove(struct amba_device *adev) | |||
142 | { | 131 | { |
143 | struct pl031_local *ldata = dev_get_drvdata(&adev->dev); | 132 | struct pl031_local *ldata = dev_get_drvdata(&adev->dev); |
144 | 133 | ||
145 | if (ldata) { | 134 | amba_set_drvdata(adev, NULL); |
146 | dev_set_drvdata(&adev->dev, NULL); | 135 | free_irq(adev->irq[0], ldata->rtc); |
147 | free_irq(adev->irq[0], ldata->rtc); | 136 | rtc_device_unregister(ldata->rtc); |
148 | rtc_device_unregister(ldata->rtc); | 137 | iounmap(ldata->base); |
149 | iounmap(ldata->base); | 138 | kfree(ldata); |
150 | kfree(ldata); | 139 | amba_release_regions(adev); |
151 | } | ||
152 | 140 | ||
153 | return 0; | 141 | return 0; |
154 | } | 142 | } |
@@ -158,13 +146,15 @@ static int pl031_probe(struct amba_device *adev, void *id) | |||
158 | int ret; | 146 | int ret; |
159 | struct pl031_local *ldata; | 147 | struct pl031_local *ldata; |
160 | 148 | ||
149 | ret = amba_request_regions(adev, NULL); | ||
150 | if (ret) | ||
151 | goto err_req; | ||
161 | 152 | ||
162 | ldata = kmalloc(sizeof(struct pl031_local), GFP_KERNEL); | 153 | ldata = kmalloc(sizeof(struct pl031_local), GFP_KERNEL); |
163 | if (!ldata) { | 154 | if (!ldata) { |
164 | ret = -ENOMEM; | 155 | ret = -ENOMEM; |
165 | goto out; | 156 | goto out; |
166 | } | 157 | } |
167 | dev_set_drvdata(&adev->dev, ldata); | ||
168 | 158 | ||
169 | ldata->base = ioremap(adev->res.start, | 159 | ldata->base = ioremap(adev->res.start, |
170 | adev->res.end - adev->res.start + 1); | 160 | adev->res.end - adev->res.start + 1); |
@@ -173,6 +163,8 @@ static int pl031_probe(struct amba_device *adev, void *id) | |||
173 | goto out_no_remap; | 163 | goto out_no_remap; |
174 | } | 164 | } |
175 | 165 | ||
166 | amba_set_drvdata(adev, ldata); | ||
167 | |||
176 | if (request_irq(adev->irq[0], pl031_interrupt, IRQF_DISABLED, | 168 | if (request_irq(adev->irq[0], pl031_interrupt, IRQF_DISABLED, |
177 | "rtc-pl031", ldata->rtc)) { | 169 | "rtc-pl031", ldata->rtc)) { |
178 | ret = -EIO; | 170 | ret = -EIO; |
@@ -192,10 +184,12 @@ out_no_rtc: | |||
192 | free_irq(adev->irq[0], ldata->rtc); | 184 | free_irq(adev->irq[0], ldata->rtc); |
193 | out_no_irq: | 185 | out_no_irq: |
194 | iounmap(ldata->base); | 186 | iounmap(ldata->base); |
187 | amba_set_drvdata(adev, NULL); | ||
195 | out_no_remap: | 188 | out_no_remap: |
196 | dev_set_drvdata(&adev->dev, NULL); | ||
197 | kfree(ldata); | 189 | kfree(ldata); |
198 | out: | 190 | out: |
191 | amba_release_regions(adev); | ||
192 | err_req: | ||
199 | return ret; | 193 | return ret; |
200 | } | 194 | } |
201 | 195 | ||
diff --git a/drivers/rtc/rtc-s3c.c b/drivers/rtc/rtc-s3c.c index f26e0cad8f16..fed86e507fdf 100644 --- a/drivers/rtc/rtc-s3c.c +++ b/drivers/rtc/rtc-s3c.c | |||
@@ -26,10 +26,6 @@ | |||
26 | #include <asm/uaccess.h> | 26 | #include <asm/uaccess.h> |
27 | #include <asm/io.h> | 27 | #include <asm/io.h> |
28 | #include <asm/irq.h> | 28 | #include <asm/irq.h> |
29 | #include <asm/rtc.h> | ||
30 | |||
31 | #include <asm/mach/time.h> | ||
32 | |||
33 | #include <asm/plat-s3c/regs-rtc.h> | 29 | #include <asm/plat-s3c/regs-rtc.h> |
34 | 30 | ||
35 | /* I have yet to find an S3C implementation with more than one | 31 | /* I have yet to find an S3C implementation with more than one |
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c index 67421b0d3a7b..f47294c60148 100644 --- a/drivers/rtc/rtc-sa1100.c +++ b/drivers/rtc/rtc-sa1100.c | |||
@@ -33,7 +33,6 @@ | |||
33 | 33 | ||
34 | #include <asm/hardware.h> | 34 | #include <asm/hardware.h> |
35 | #include <asm/irq.h> | 35 | #include <asm/irq.h> |
36 | #include <asm/rtc.h> | ||
37 | 36 | ||
38 | #ifdef CONFIG_ARCH_PXA | 37 | #ifdef CONFIG_ARCH_PXA |
39 | #include <asm/arch/pxa-regs.h> | 38 | #include <asm/arch/pxa-regs.h> |
@@ -47,6 +46,42 @@ static unsigned long rtc_freq = 1024; | |||
47 | static struct rtc_time rtc_alarm; | 46 | static struct rtc_time rtc_alarm; |
48 | static DEFINE_SPINLOCK(sa1100_rtc_lock); | 47 | static DEFINE_SPINLOCK(sa1100_rtc_lock); |
49 | 48 | ||
49 | static inline int rtc_periodic_alarm(struct rtc_time *tm) | ||
50 | { | ||
51 | return (tm->tm_year == -1) || | ||
52 | ((unsigned)tm->tm_mon >= 12) || | ||
53 | ((unsigned)(tm->tm_mday - 1) >= 31) || | ||
54 | ((unsigned)tm->tm_hour > 23) || | ||
55 | ((unsigned)tm->tm_min > 59) || | ||
56 | ((unsigned)tm->tm_sec > 59); | ||
57 | } | ||
58 | |||
59 | /* | ||
60 | * Calculate the next alarm time given the requested alarm time mask | ||
61 | * and the current time. | ||
62 | */ | ||
63 | static void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now, struct rtc_time *alrm) | ||
64 | { | ||
65 | unsigned long next_time; | ||
66 | unsigned long now_time; | ||
67 | |||
68 | next->tm_year = now->tm_year; | ||
69 | next->tm_mon = now->tm_mon; | ||
70 | next->tm_mday = now->tm_mday; | ||
71 | next->tm_hour = alrm->tm_hour; | ||
72 | next->tm_min = alrm->tm_min; | ||
73 | next->tm_sec = alrm->tm_sec; | ||
74 | |||
75 | rtc_tm_to_time(now, &now_time); | ||
76 | rtc_tm_to_time(next, &next_time); | ||
77 | |||
78 | if (next_time < now_time) { | ||
79 | /* Advance one day */ | ||
80 | next_time += 60 * 60 * 24; | ||
81 | rtc_time_to_tm(next_time, next); | ||
82 | } | ||
83 | } | ||
84 | |||
50 | static int rtc_update_alarm(struct rtc_time *alrm) | 85 | static int rtc_update_alarm(struct rtc_time *alrm) |
51 | { | 86 | { |
52 | struct rtc_time alarm_tm, now_tm; | 87 | struct rtc_time alarm_tm, now_tm; |
diff --git a/drivers/scsi/arm/Kconfig b/drivers/scsi/arm/Kconfig index 7236143941f3..a8587f1f5e7e 100644 --- a/drivers/scsi/arm/Kconfig +++ b/drivers/scsi/arm/Kconfig | |||
@@ -3,7 +3,7 @@ | |||
3 | # | 3 | # |
4 | config SCSI_ACORNSCSI_3 | 4 | config SCSI_ACORNSCSI_3 |
5 | tristate "Acorn SCSI card (aka30) support" | 5 | tristate "Acorn SCSI card (aka30) support" |
6 | depends on ARCH_ACORN && SCSI && BROKEN | 6 | depends on ARCH_ACORN && SCSI |
7 | select SCSI_SPI_ATTRS | 7 | select SCSI_SPI_ATTRS |
8 | help | 8 | help |
9 | This enables support for the Acorn SCSI card (aka30). If you have an | 9 | This enables support for the Acorn SCSI card (aka30). If you have an |
diff --git a/drivers/scsi/arm/acornscsi-io.S b/drivers/scsi/arm/acornscsi-io.S index 93467e6ac923..5cebe3105260 100644 --- a/drivers/scsi/arm/acornscsi-io.S +++ b/drivers/scsi/arm/acornscsi-io.S | |||
@@ -10,17 +10,10 @@ | |||
10 | #include <asm/assembler.h> | 10 | #include <asm/assembler.h> |
11 | #include <asm/hardware.h> | 11 | #include <asm/hardware.h> |
12 | 12 | ||
13 | #if (IO_BASE == (PCIO_BASE & 0xff000000)) | 13 | #if defined(__APCS_32__) |
14 | #define ADDR(off,reg) \ | 14 | #define LOADREGS(t,r,l...) ldm##t r, l |
15 | tst off, $0x80000000 ;\ | 15 | #elif defined(__APCS_26__) |
16 | mov reg, $IO_BASE ;\ | 16 | #define LOADREGS(t,r,l...) ldm##t r, l##^ |
17 | orreq reg, reg, $(PCIO_BASE & 0x00ff0000) | ||
18 | #else | ||
19 | #define ADDR(off,reg) \ | ||
20 | tst off, $0x80000000 ;\ | ||
21 | movne reg, $IO_BASE ;\ | ||
22 | moveq reg, $(PCIO_BASE & 0xff000000) ;\ | ||
23 | orreq reg, reg, $(PCIO_BASE & 0x00ff0000) | ||
24 | #endif | 17 | #endif |
25 | 18 | ||
26 | @ Purpose: transfer a block of data from the acorn scsi card to memory | 19 | @ Purpose: transfer a block of data from the acorn scsi card to memory |
diff --git a/drivers/scsi/arm/acornscsi.c b/drivers/scsi/arm/acornscsi.c index 8e53f02cc311..918ccf818757 100644 --- a/drivers/scsi/arm/acornscsi.c +++ b/drivers/scsi/arm/acornscsi.c | |||
@@ -123,12 +123,6 @@ | |||
123 | #define DBG(cmd,xxx...) xxx | 123 | #define DBG(cmd,xxx...) xxx |
124 | #endif | 124 | #endif |
125 | 125 | ||
126 | #ifndef STRINGIFY | ||
127 | #define STRINGIFY(x) #x | ||
128 | #endif | ||
129 | #define STRx(x) STRINGIFY(x) | ||
130 | #define NO_WRITE_STR STRx(NO_WRITE) | ||
131 | |||
132 | #include <linux/module.h> | 126 | #include <linux/module.h> |
133 | #include <linux/kernel.h> | 127 | #include <linux/kernel.h> |
134 | #include <linux/string.h> | 128 | #include <linux/string.h> |
@@ -141,9 +135,10 @@ | |||
141 | #include <linux/interrupt.h> | 135 | #include <linux/interrupt.h> |
142 | #include <linux/init.h> | 136 | #include <linux/init.h> |
143 | #include <linux/bitops.h> | 137 | #include <linux/bitops.h> |
138 | #include <linux/stringify.h> | ||
139 | #include <linux/io.h> | ||
144 | 140 | ||
145 | #include <asm/system.h> | 141 | #include <asm/system.h> |
146 | #include <asm/io.h> | ||
147 | #include <asm/ecard.h> | 142 | #include <asm/ecard.h> |
148 | 143 | ||
149 | #include "../scsi.h" | 144 | #include "../scsi.h" |
@@ -203,44 +198,46 @@ static void acornscsi_abortcmd(AS_Host *host, unsigned char tag); | |||
203 | * Miscellaneous | 198 | * Miscellaneous |
204 | */ | 199 | */ |
205 | 200 | ||
206 | static inline void | 201 | /* Offsets from MEMC base */ |
207 | sbic_arm_write(unsigned int io_port, int reg, int value) | 202 | #define SBIC_REGIDX 0x2000 |
203 | #define SBIC_REGVAL 0x2004 | ||
204 | #define DMAC_OFFSET 0x3000 | ||
205 | |||
206 | /* Offsets from FAST IOC base */ | ||
207 | #define INT_REG 0x2000 | ||
208 | #define PAGE_REG 0x3000 | ||
209 | |||
210 | static inline void sbic_arm_write(AS_Host *host, unsigned int reg, unsigned int value) | ||
208 | { | 211 | { |
209 | __raw_writeb(reg, io_port); | 212 | writeb(reg, host->base + SBIC_REGIDX); |
210 | __raw_writeb(value, io_port + 4); | 213 | writeb(value, host->base + SBIC_REGVAL); |
211 | } | 214 | } |
212 | 215 | ||
213 | #define sbic_arm_writenext(io,val) \ | 216 | static inline int sbic_arm_read(AS_Host *host, unsigned int reg) |
214 | __raw_writeb((val), (io) + 4) | ||
215 | |||
216 | static inline | ||
217 | int sbic_arm_read(unsigned int io_port, int reg) | ||
218 | { | 217 | { |
219 | if(reg == SBIC_ASR) | 218 | if(reg == SBIC_ASR) |
220 | return __raw_readl(io_port) & 255; | 219 | return readl(host->base + SBIC_REGIDX) & 255; |
221 | __raw_writeb(reg, io_port); | 220 | writeb(reg, host->base + SBIC_REGIDX); |
222 | return __raw_readl(io_port + 4) & 255; | 221 | return readl(host->base + SBIC_REGVAL) & 255; |
223 | } | 222 | } |
224 | 223 | ||
225 | #define sbic_arm_readnext(io) \ | 224 | #define sbic_arm_writenext(host, val) writeb((val), (host)->base + SBIC_REGVAL) |
226 | __raw_readb((io) + 4) | 225 | #define sbic_arm_readnext(host) readb((host)->base + SBIC_REGVAL) |
227 | 226 | ||
228 | #ifdef USE_DMAC | 227 | #ifdef USE_DMAC |
229 | #define dmac_read(io_port,reg) \ | 228 | #define dmac_read(host,reg) \ |
230 | inb((io_port) + (reg)) | 229 | readb((host)->base + DMAC_OFFSET + ((reg) << 2)) |
231 | 230 | ||
232 | #define dmac_write(io_port,reg,value) \ | 231 | #define dmac_write(host,reg,value) \ |
233 | ({ outb((value), (io_port) + (reg)); }) | 232 | ({ writeb((value), (host)->base + DMAC_OFFSET + ((reg) << 2)); }) |
234 | 233 | ||
235 | #define dmac_clearintr(io_port) \ | 234 | #define dmac_clearintr(host) writeb(0, (host)->fast + INT_REG) |
236 | ({ outb(0, (io_port)); }) | ||
237 | 235 | ||
238 | static inline | 236 | static inline unsigned int dmac_address(AS_Host *host) |
239 | unsigned int dmac_address(unsigned int io_port) | ||
240 | { | 237 | { |
241 | return dmac_read(io_port, DMAC_TXADRHI) << 16 | | 238 | return dmac_read(host, DMAC_TXADRHI) << 16 | |
242 | dmac_read(io_port, DMAC_TXADRMD) << 8 | | 239 | dmac_read(host, DMAC_TXADRMD) << 8 | |
243 | dmac_read(io_port, DMAC_TXADRLO); | 240 | dmac_read(host, DMAC_TXADRLO); |
244 | } | 241 | } |
245 | 242 | ||
246 | static | 243 | static |
@@ -248,15 +245,15 @@ void acornscsi_dumpdma(AS_Host *host, char *where) | |||
248 | { | 245 | { |
249 | unsigned int mode, addr, len; | 246 | unsigned int mode, addr, len; |
250 | 247 | ||
251 | mode = dmac_read(host->dma.io_port, DMAC_MODECON); | 248 | mode = dmac_read(host, DMAC_MODECON); |
252 | addr = dmac_address(host->dma.io_port); | 249 | addr = dmac_address(host); |
253 | len = dmac_read(host->dma.io_port, DMAC_TXCNTHI) << 8 | | 250 | len = dmac_read(host, DMAC_TXCNTHI) << 8 | |
254 | dmac_read(host->dma.io_port, DMAC_TXCNTLO); | 251 | dmac_read(host, DMAC_TXCNTLO); |
255 | 252 | ||
256 | printk("scsi%d: %s: DMAC %02x @%06x+%04x msk %02x, ", | 253 | printk("scsi%d: %s: DMAC %02x @%06x+%04x msk %02x, ", |
257 | host->host->host_no, where, | 254 | host->host->host_no, where, |
258 | mode, addr, (len + 1) & 0xffff, | 255 | mode, addr, (len + 1) & 0xffff, |
259 | dmac_read(host->dma.io_port, DMAC_MASKREG)); | 256 | dmac_read(host, DMAC_MASKREG)); |
260 | 257 | ||
261 | printk("DMA @%06x, ", host->dma.start_addr); | 258 | printk("DMA @%06x, ", host->dma.start_addr); |
262 | printk("BH @%p +%04x, ", host->scsi.SCp.ptr, | 259 | printk("BH @%p +%04x, ", host->scsi.SCp.ptr, |
@@ -272,9 +269,9 @@ unsigned long acornscsi_sbic_xfcount(AS_Host *host) | |||
272 | { | 269 | { |
273 | unsigned long length; | 270 | unsigned long length; |
274 | 271 | ||
275 | length = sbic_arm_read(host->scsi.io_port, SBIC_TRANSCNTH) << 16; | 272 | length = sbic_arm_read(host, SBIC_TRANSCNTH) << 16; |
276 | length |= sbic_arm_readnext(host->scsi.io_port) << 8; | 273 | length |= sbic_arm_readnext(host) << 8; |
277 | length |= sbic_arm_readnext(host->scsi.io_port); | 274 | length |= sbic_arm_readnext(host); |
278 | 275 | ||
279 | return length; | 276 | return length; |
280 | } | 277 | } |
@@ -285,7 +282,7 @@ acornscsi_sbic_wait(AS_Host *host, int stat_mask, int stat, int timeout, char *m | |||
285 | int asr; | 282 | int asr; |
286 | 283 | ||
287 | do { | 284 | do { |
288 | asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR); | 285 | asr = sbic_arm_read(host, SBIC_ASR); |
289 | 286 | ||
290 | if ((asr & stat_mask) == stat) | 287 | if ((asr & stat_mask) == stat) |
291 | return 0; | 288 | return 0; |
@@ -304,7 +301,7 @@ int acornscsi_sbic_issuecmd(AS_Host *host, int command) | |||
304 | if (acornscsi_sbic_wait(host, ASR_CIP, 0, 1000, "issuing command")) | 301 | if (acornscsi_sbic_wait(host, ASR_CIP, 0, 1000, "issuing command")) |
305 | return -1; | 302 | return -1; |
306 | 303 | ||
307 | sbic_arm_write(host->scsi.io_port, SBIC_CMND, command); | 304 | sbic_arm_write(host, SBIC_CMND, command); |
308 | 305 | ||
309 | return 0; | 306 | return 0; |
310 | } | 307 | } |
@@ -331,20 +328,20 @@ void acornscsi_resetcard(AS_Host *host) | |||
331 | 328 | ||
332 | /* assert reset line */ | 329 | /* assert reset line */ |
333 | host->card.page_reg = 0x80; | 330 | host->card.page_reg = 0x80; |
334 | outb(host->card.page_reg, host->card.io_page); | 331 | writeb(host->card.page_reg, host->fast + PAGE_REG); |
335 | 332 | ||
336 | /* wait 3 cs. SCSI standard says 25ms. */ | 333 | /* wait 3 cs. SCSI standard says 25ms. */ |
337 | acornscsi_csdelay(3); | 334 | acornscsi_csdelay(3); |
338 | 335 | ||
339 | host->card.page_reg = 0; | 336 | host->card.page_reg = 0; |
340 | outb(host->card.page_reg, host->card.io_page); | 337 | writeb(host->card.page_reg, host->fast + PAGE_REG); |
341 | 338 | ||
342 | /* | 339 | /* |
343 | * Should get a reset from the card | 340 | * Should get a reset from the card |
344 | */ | 341 | */ |
345 | timeout = 1000; | 342 | timeout = 1000; |
346 | do { | 343 | do { |
347 | if (inb(host->card.io_intr) & 8) | 344 | if (readb(host->fast + INT_REG) & 8) |
348 | break; | 345 | break; |
349 | udelay(1); | 346 | udelay(1); |
350 | } while (--timeout); | 347 | } while (--timeout); |
@@ -353,19 +350,19 @@ void acornscsi_resetcard(AS_Host *host) | |||
353 | printk("scsi%d: timeout while resetting card\n", | 350 | printk("scsi%d: timeout while resetting card\n", |
354 | host->host->host_no); | 351 | host->host->host_no); |
355 | 352 | ||
356 | sbic_arm_read(host->scsi.io_port, SBIC_ASR); | 353 | sbic_arm_read(host, SBIC_ASR); |
357 | sbic_arm_read(host->scsi.io_port, SBIC_SSR); | 354 | sbic_arm_read(host, SBIC_SSR); |
358 | 355 | ||
359 | /* setup sbic - WD33C93A */ | 356 | /* setup sbic - WD33C93A */ |
360 | sbic_arm_write(host->scsi.io_port, SBIC_OWNID, OWNID_EAF | host->host->this_id); | 357 | sbic_arm_write(host, SBIC_OWNID, OWNID_EAF | host->host->this_id); |
361 | sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_RESET); | 358 | sbic_arm_write(host, SBIC_CMND, CMND_RESET); |
362 | 359 | ||
363 | /* | 360 | /* |
364 | * Command should cause a reset interrupt | 361 | * Command should cause a reset interrupt |
365 | */ | 362 | */ |
366 | timeout = 1000; | 363 | timeout = 1000; |
367 | do { | 364 | do { |
368 | if (inb(host->card.io_intr) & 8) | 365 | if (readb(host->fast + INT_REG) & 8) |
369 | break; | 366 | break; |
370 | udelay(1); | 367 | udelay(1); |
371 | } while (--timeout); | 368 | } while (--timeout); |
@@ -374,26 +371,26 @@ void acornscsi_resetcard(AS_Host *host) | |||
374 | printk("scsi%d: timeout while resetting card\n", | 371 | printk("scsi%d: timeout while resetting card\n", |
375 | host->host->host_no); | 372 | host->host->host_no); |
376 | 373 | ||
377 | sbic_arm_read(host->scsi.io_port, SBIC_ASR); | 374 | sbic_arm_read(host, SBIC_ASR); |
378 | if (sbic_arm_read(host->scsi.io_port, SBIC_SSR) != 0x01) | 375 | if (sbic_arm_read(host, SBIC_SSR) != 0x01) |
379 | printk(KERN_CRIT "scsi%d: WD33C93A didn't give enhanced reset interrupt\n", | 376 | printk(KERN_CRIT "scsi%d: WD33C93A didn't give enhanced reset interrupt\n", |
380 | host->host->host_no); | 377 | host->host->host_no); |
381 | 378 | ||
382 | sbic_arm_write(host->scsi.io_port, SBIC_CTRL, INIT_SBICDMA | CTRL_IDI); | 379 | sbic_arm_write(host, SBIC_CTRL, INIT_SBICDMA | CTRL_IDI); |
383 | sbic_arm_write(host->scsi.io_port, SBIC_TIMEOUT, TIMEOUT_TIME); | 380 | sbic_arm_write(host, SBIC_TIMEOUT, TIMEOUT_TIME); |
384 | sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, SYNCHTRANSFER_2DBA); | 381 | sbic_arm_write(host, SBIC_SYNCHTRANSFER, SYNCHTRANSFER_2DBA); |
385 | sbic_arm_write(host->scsi.io_port, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP); | 382 | sbic_arm_write(host, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP); |
386 | 383 | ||
387 | host->card.page_reg = 0x40; | 384 | host->card.page_reg = 0x40; |
388 | outb(host->card.page_reg, host->card.io_page); | 385 | writeb(host->card.page_reg, host->fast + PAGE_REG); |
389 | 386 | ||
390 | /* setup dmac - uPC71071 */ | 387 | /* setup dmac - uPC71071 */ |
391 | dmac_write(host->dma.io_port, DMAC_INIT, 0); | 388 | dmac_write(host, DMAC_INIT, 0); |
392 | #ifdef USE_DMAC | 389 | #ifdef USE_DMAC |
393 | dmac_write(host->dma.io_port, DMAC_INIT, INIT_8BIT); | 390 | dmac_write(host, DMAC_INIT, INIT_8BIT); |
394 | dmac_write(host->dma.io_port, DMAC_CHANNEL, CHANNEL_0); | 391 | dmac_write(host, DMAC_CHANNEL, CHANNEL_0); |
395 | dmac_write(host->dma.io_port, DMAC_DEVCON0, INIT_DEVCON0); | 392 | dmac_write(host, DMAC_DEVCON0, INIT_DEVCON0); |
396 | dmac_write(host->dma.io_port, DMAC_DEVCON1, INIT_DEVCON1); | 393 | dmac_write(host, DMAC_DEVCON1, INIT_DEVCON1); |
397 | #endif | 394 | #endif |
398 | 395 | ||
399 | host->SCpnt = NULL; | 396 | host->SCpnt = NULL; |
@@ -741,9 +738,9 @@ intr_ret_t acornscsi_kick(AS_Host *host) | |||
741 | * If we have an interrupt pending, then we may have been reselected. | 738 | * If we have an interrupt pending, then we may have been reselected. |
742 | * In this case, we don't want to write to the registers | 739 | * In this case, we don't want to write to the registers |
743 | */ | 740 | */ |
744 | if (!(sbic_arm_read(host->scsi.io_port, SBIC_ASR) & (ASR_INT|ASR_BSY|ASR_CIP))) { | 741 | if (!(sbic_arm_read(host, SBIC_ASR) & (ASR_INT|ASR_BSY|ASR_CIP))) { |
745 | sbic_arm_write(host->scsi.io_port, SBIC_DESTID, SCpnt->device->id); | 742 | sbic_arm_write(host, SBIC_DESTID, SCpnt->device->id); |
746 | sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_SELWITHATN); | 743 | sbic_arm_write(host, SBIC_CMND, CMND_SELWITHATN); |
747 | } | 744 | } |
748 | 745 | ||
749 | /* | 746 | /* |
@@ -807,7 +804,7 @@ static void acornscsi_done(AS_Host *host, struct scsi_cmnd **SCpntp, | |||
807 | struct scsi_cmnd *SCpnt = *SCpntp; | 804 | struct scsi_cmnd *SCpnt = *SCpntp; |
808 | 805 | ||
809 | /* clean up */ | 806 | /* clean up */ |
810 | sbic_arm_write(host->scsi.io_port, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP); | 807 | sbic_arm_write(host, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP); |
811 | 808 | ||
812 | host->stats.fins += 1; | 809 | host->stats.fins += 1; |
813 | 810 | ||
@@ -918,13 +915,13 @@ static | |||
918 | void acornscsi_data_read(AS_Host *host, char *ptr, | 915 | void acornscsi_data_read(AS_Host *host, char *ptr, |
919 | unsigned int start_addr, unsigned int length) | 916 | unsigned int start_addr, unsigned int length) |
920 | { | 917 | { |
921 | extern void __acornscsi_in(int port, char *buf, int len); | 918 | extern void __acornscsi_in(void __iomem *, char *buf, int len); |
922 | unsigned int page, offset, len = length; | 919 | unsigned int page, offset, len = length; |
923 | 920 | ||
924 | page = (start_addr >> 12); | 921 | page = (start_addr >> 12); |
925 | offset = start_addr & ((1 << 12) - 1); | 922 | offset = start_addr & ((1 << 12) - 1); |
926 | 923 | ||
927 | outb((page & 0x3f) | host->card.page_reg, host->card.io_page); | 924 | writeb((page & 0x3f) | host->card.page_reg, host->fast + PAGE_REG); |
928 | 925 | ||
929 | while (len > 0) { | 926 | while (len > 0) { |
930 | unsigned int this_len; | 927 | unsigned int this_len; |
@@ -934,7 +931,7 @@ void acornscsi_data_read(AS_Host *host, char *ptr, | |||
934 | else | 931 | else |
935 | this_len = len; | 932 | this_len = len; |
936 | 933 | ||
937 | __acornscsi_in(host->card.io_ram + (offset << 1), ptr, this_len); | 934 | __acornscsi_in(host->base + (offset << 1), ptr, this_len); |
938 | 935 | ||
939 | offset += this_len; | 936 | offset += this_len; |
940 | ptr += this_len; | 937 | ptr += this_len; |
@@ -943,10 +940,10 @@ void acornscsi_data_read(AS_Host *host, char *ptr, | |||
943 | if (offset == (1 << 12)) { | 940 | if (offset == (1 << 12)) { |
944 | offset = 0; | 941 | offset = 0; |
945 | page ++; | 942 | page ++; |
946 | outb((page & 0x3f) | host->card.page_reg, host->card.io_page); | 943 | writeb((page & 0x3f) | host->card.page_reg, host->fast + PAGE_REG); |
947 | } | 944 | } |
948 | } | 945 | } |
949 | outb(host->card.page_reg, host->card.io_page); | 946 | writeb(host->card.page_reg, host->fast + PAGE_REG); |
950 | } | 947 | } |
951 | 948 | ||
952 | /* | 949 | /* |
@@ -963,13 +960,13 @@ static | |||
963 | void acornscsi_data_write(AS_Host *host, char *ptr, | 960 | void acornscsi_data_write(AS_Host *host, char *ptr, |
964 | unsigned int start_addr, unsigned int length) | 961 | unsigned int start_addr, unsigned int length) |
965 | { | 962 | { |
966 | extern void __acornscsi_out(int port, char *buf, int len); | 963 | extern void __acornscsi_out(void __iomem *, char *buf, int len); |
967 | unsigned int page, offset, len = length; | 964 | unsigned int page, offset, len = length; |
968 | 965 | ||
969 | page = (start_addr >> 12); | 966 | page = (start_addr >> 12); |
970 | offset = start_addr & ((1 << 12) - 1); | 967 | offset = start_addr & ((1 << 12) - 1); |
971 | 968 | ||
972 | outb((page & 0x3f) | host->card.page_reg, host->card.io_page); | 969 | writeb((page & 0x3f) | host->card.page_reg, host->fast + PAGE_REG); |
973 | 970 | ||
974 | while (len > 0) { | 971 | while (len > 0) { |
975 | unsigned int this_len; | 972 | unsigned int this_len; |
@@ -979,7 +976,7 @@ void acornscsi_data_write(AS_Host *host, char *ptr, | |||
979 | else | 976 | else |
980 | this_len = len; | 977 | this_len = len; |
981 | 978 | ||
982 | __acornscsi_out(host->card.io_ram + (offset << 1), ptr, this_len); | 979 | __acornscsi_out(host->base + (offset << 1), ptr, this_len); |
983 | 980 | ||
984 | offset += this_len; | 981 | offset += this_len; |
985 | ptr += this_len; | 982 | ptr += this_len; |
@@ -988,10 +985,10 @@ void acornscsi_data_write(AS_Host *host, char *ptr, | |||
988 | if (offset == (1 << 12)) { | 985 | if (offset == (1 << 12)) { |
989 | offset = 0; | 986 | offset = 0; |
990 | page ++; | 987 | page ++; |
991 | outb((page & 0x3f) | host->card.page_reg, host->card.io_page); | 988 | writeb((page & 0x3f) | host->card.page_reg, host->fast + PAGE_REG); |
992 | } | 989 | } |
993 | } | 990 | } |
994 | outb(host->card.page_reg, host->card.io_page); | 991 | writeb(host->card.page_reg, host->fast + PAGE_REG); |
995 | } | 992 | } |
996 | 993 | ||
997 | /* ========================================================================================= | 994 | /* ========================================================================================= |
@@ -1008,8 +1005,8 @@ void acornscsi_data_write(AS_Host *host, char *ptr, | |||
1008 | static inline | 1005 | static inline |
1009 | void acornscsi_dma_stop(AS_Host *host) | 1006 | void acornscsi_dma_stop(AS_Host *host) |
1010 | { | 1007 | { |
1011 | dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON); | 1008 | dmac_write(host, DMAC_MASKREG, MASK_ON); |
1012 | dmac_clearintr(host->dma.io_intr_clear); | 1009 | dmac_clearintr(host); |
1013 | 1010 | ||
1014 | #if (DEBUG & DEBUG_DMA) | 1011 | #if (DEBUG & DEBUG_DMA) |
1015 | DBG(host->SCpnt, acornscsi_dumpdma(host, "stop")); | 1012 | DBG(host->SCpnt, acornscsi_dumpdma(host, "stop")); |
@@ -1031,7 +1028,7 @@ void acornscsi_dma_setup(AS_Host *host, dmadir_t direction) | |||
1031 | 1028 | ||
1032 | host->dma.direction = direction; | 1029 | host->dma.direction = direction; |
1033 | 1030 | ||
1034 | dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON); | 1031 | dmac_write(host, DMAC_MASKREG, MASK_ON); |
1035 | 1032 | ||
1036 | if (direction == DMA_OUT) { | 1033 | if (direction == DMA_OUT) { |
1037 | #if (DEBUG & DEBUG_NO_WRITE) | 1034 | #if (DEBUG & DEBUG_NO_WRITE) |
@@ -1062,13 +1059,13 @@ void acornscsi_dma_setup(AS_Host *host, dmadir_t direction) | |||
1062 | length); | 1059 | length); |
1063 | 1060 | ||
1064 | length -= 1; | 1061 | length -= 1; |
1065 | dmac_write(host->dma.io_port, DMAC_TXCNTLO, length); | 1062 | dmac_write(host, DMAC_TXCNTLO, length); |
1066 | dmac_write(host->dma.io_port, DMAC_TXCNTHI, length >> 8); | 1063 | dmac_write(host, DMAC_TXCNTHI, length >> 8); |
1067 | dmac_write(host->dma.io_port, DMAC_TXADRLO, address); | 1064 | dmac_write(host, DMAC_TXADRLO, address); |
1068 | dmac_write(host->dma.io_port, DMAC_TXADRMD, address >> 8); | 1065 | dmac_write(host, DMAC_TXADRMD, address >> 8); |
1069 | dmac_write(host->dma.io_port, DMAC_TXADRHI, 0); | 1066 | dmac_write(host, DMAC_TXADRHI, 0); |
1070 | dmac_write(host->dma.io_port, DMAC_MODECON, mode); | 1067 | dmac_write(host, DMAC_MODECON, mode); |
1071 | dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_OFF); | 1068 | dmac_write(host, DMAC_MASKREG, MASK_OFF); |
1072 | 1069 | ||
1073 | #if (DEBUG & DEBUG_DMA) | 1070 | #if (DEBUG & DEBUG_DMA) |
1074 | DBG(host->SCpnt, acornscsi_dumpdma(host, "strt")); | 1071 | DBG(host->SCpnt, acornscsi_dumpdma(host, "strt")); |
@@ -1088,8 +1085,8 @@ void acornscsi_dma_setup(AS_Host *host, dmadir_t direction) | |||
1088 | static | 1085 | static |
1089 | void acornscsi_dma_cleanup(AS_Host *host) | 1086 | void acornscsi_dma_cleanup(AS_Host *host) |
1090 | { | 1087 | { |
1091 | dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON); | 1088 | dmac_write(host, DMAC_MASKREG, MASK_ON); |
1092 | dmac_clearintr(host->dma.io_intr_clear); | 1089 | dmac_clearintr(host); |
1093 | 1090 | ||
1094 | /* | 1091 | /* |
1095 | * Check for a pending transfer | 1092 | * Check for a pending transfer |
@@ -1116,7 +1113,7 @@ void acornscsi_dma_cleanup(AS_Host *host) | |||
1116 | /* | 1113 | /* |
1117 | * Calculate number of bytes transferred from DMA. | 1114 | * Calculate number of bytes transferred from DMA. |
1118 | */ | 1115 | */ |
1119 | transferred = dmac_address(host->dma.io_port) - host->dma.start_addr; | 1116 | transferred = dmac_address(host) - host->dma.start_addr; |
1120 | host->dma.transferred += transferred; | 1117 | host->dma.transferred += transferred; |
1121 | 1118 | ||
1122 | if (host->dma.direction == DMA_IN) | 1119 | if (host->dma.direction == DMA_IN) |
@@ -1152,13 +1149,13 @@ void acornscsi_dma_intr(AS_Host *host) | |||
1152 | DBG(host->SCpnt, acornscsi_dumpdma(host, "inti")); | 1149 | DBG(host->SCpnt, acornscsi_dumpdma(host, "inti")); |
1153 | #endif | 1150 | #endif |
1154 | 1151 | ||
1155 | dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_ON); | 1152 | dmac_write(host, DMAC_MASKREG, MASK_ON); |
1156 | dmac_clearintr(host->dma.io_intr_clear); | 1153 | dmac_clearintr(host); |
1157 | 1154 | ||
1158 | /* | 1155 | /* |
1159 | * Calculate amount transferred via DMA | 1156 | * Calculate amount transferred via DMA |
1160 | */ | 1157 | */ |
1161 | transferred = dmac_address(host->dma.io_port) - host->dma.start_addr; | 1158 | transferred = dmac_address(host) - host->dma.start_addr; |
1162 | host->dma.transferred += transferred; | 1159 | host->dma.transferred += transferred; |
1163 | 1160 | ||
1164 | /* | 1161 | /* |
@@ -1190,12 +1187,12 @@ void acornscsi_dma_intr(AS_Host *host) | |||
1190 | length); | 1187 | length); |
1191 | 1188 | ||
1192 | length -= 1; | 1189 | length -= 1; |
1193 | dmac_write(host->dma.io_port, DMAC_TXCNTLO, length); | 1190 | dmac_write(host, DMAC_TXCNTLO, length); |
1194 | dmac_write(host->dma.io_port, DMAC_TXCNTHI, length >> 8); | 1191 | dmac_write(host, DMAC_TXCNTHI, length >> 8); |
1195 | dmac_write(host->dma.io_port, DMAC_TXADRLO, address); | 1192 | dmac_write(host, DMAC_TXADRLO, address); |
1196 | dmac_write(host->dma.io_port, DMAC_TXADRMD, address >> 8); | 1193 | dmac_write(host, DMAC_TXADRMD, address >> 8); |
1197 | dmac_write(host->dma.io_port, DMAC_TXADRHI, 0); | 1194 | dmac_write(host, DMAC_TXADRHI, 0); |
1198 | dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_OFF); | 1195 | dmac_write(host, DMAC_MASKREG, MASK_OFF); |
1199 | 1196 | ||
1200 | #if (DEBUG & DEBUG_DMA) | 1197 | #if (DEBUG & DEBUG_DMA) |
1201 | DBG(host->SCpnt, acornscsi_dumpdma(host, "into")); | 1198 | DBG(host->SCpnt, acornscsi_dumpdma(host, "into")); |
@@ -1209,15 +1206,15 @@ void acornscsi_dma_intr(AS_Host *host) | |||
1209 | * attention condition. We continue giving one byte until | 1206 | * attention condition. We continue giving one byte until |
1210 | * the device recognises the attention. | 1207 | * the device recognises the attention. |
1211 | */ | 1208 | */ |
1212 | if (dmac_read(host->dma.io_port, DMAC_STATUS) & STATUS_RQ0) { | 1209 | if (dmac_read(host, DMAC_STATUS) & STATUS_RQ0) { |
1213 | acornscsi_abortcmd(host, host->SCpnt->tag); | 1210 | acornscsi_abortcmd(host, host->SCpnt->tag); |
1214 | 1211 | ||
1215 | dmac_write(host->dma.io_port, DMAC_TXCNTLO, 0); | 1212 | dmac_write(host, DMAC_TXCNTLO, 0); |
1216 | dmac_write(host->dma.io_port, DMAC_TXCNTHI, 0); | 1213 | dmac_write(host, DMAC_TXCNTHI, 0); |
1217 | dmac_write(host->dma.io_port, DMAC_TXADRLO, 0); | 1214 | dmac_write(host, DMAC_TXADRLO, 0); |
1218 | dmac_write(host->dma.io_port, DMAC_TXADRMD, 0); | 1215 | dmac_write(host, DMAC_TXADRMD, 0); |
1219 | dmac_write(host->dma.io_port, DMAC_TXADRHI, 0); | 1216 | dmac_write(host, DMAC_TXADRHI, 0); |
1220 | dmac_write(host->dma.io_port, DMAC_MASKREG, MASK_OFF); | 1217 | dmac_write(host, DMAC_MASKREG, MASK_OFF); |
1221 | } | 1218 | } |
1222 | #endif | 1219 | #endif |
1223 | } | 1220 | } |
@@ -1271,9 +1268,9 @@ void acornscsi_dma_adjust(AS_Host *host) | |||
1271 | host->dma.xfer_setup = 0; | 1268 | host->dma.xfer_setup = 0; |
1272 | else { | 1269 | else { |
1273 | transferred += host->dma.start_addr; | 1270 | transferred += host->dma.start_addr; |
1274 | dmac_write(host->dma.io_port, DMAC_TXADRLO, transferred); | 1271 | dmac_write(host, DMAC_TXADRLO, transferred); |
1275 | dmac_write(host->dma.io_port, DMAC_TXADRMD, transferred >> 8); | 1272 | dmac_write(host, DMAC_TXADRMD, transferred >> 8); |
1276 | dmac_write(host->dma.io_port, DMAC_TXADRHI, transferred >> 16); | 1273 | dmac_write(host, DMAC_TXADRHI, transferred >> 16); |
1277 | #if (DEBUG & (DEBUG_DMA|DEBUG_WRITE)) | 1274 | #if (DEBUG & (DEBUG_DMA|DEBUG_WRITE)) |
1278 | DBG(host->SCpnt, acornscsi_dumpdma(host, "adjo")); | 1275 | DBG(host->SCpnt, acornscsi_dumpdma(host, "adjo")); |
1279 | #endif | 1276 | #endif |
@@ -1292,12 +1289,12 @@ acornscsi_write_pio(AS_Host *host, char *bytes, int *ptr, int len, unsigned int | |||
1292 | int my_ptr = *ptr; | 1289 | int my_ptr = *ptr; |
1293 | 1290 | ||
1294 | while (my_ptr < len) { | 1291 | while (my_ptr < len) { |
1295 | asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR); | 1292 | asr = sbic_arm_read(host, SBIC_ASR); |
1296 | 1293 | ||
1297 | if (asr & ASR_DBR) { | 1294 | if (asr & ASR_DBR) { |
1298 | timeout = max_timeout; | 1295 | timeout = max_timeout; |
1299 | 1296 | ||
1300 | sbic_arm_write(host->scsi.io_port, SBIC_DATA, bytes[my_ptr++]); | 1297 | sbic_arm_write(host, SBIC_DATA, bytes[my_ptr++]); |
1301 | } else if (asr & ASR_INT) | 1298 | } else if (asr & ASR_INT) |
1302 | break; | 1299 | break; |
1303 | else if (--timeout == 0) | 1300 | else if (--timeout == 0) |
@@ -1320,9 +1317,9 @@ acornscsi_sendcommand(AS_Host *host) | |||
1320 | { | 1317 | { |
1321 | struct scsi_cmnd *SCpnt = host->SCpnt; | 1318 | struct scsi_cmnd *SCpnt = host->SCpnt; |
1322 | 1319 | ||
1323 | sbic_arm_write(host->scsi.io_port, SBIC_TRANSCNTH, 0); | 1320 | sbic_arm_write(host, SBIC_TRANSCNTH, 0); |
1324 | sbic_arm_writenext(host->scsi.io_port, 0); | 1321 | sbic_arm_writenext(host, 0); |
1325 | sbic_arm_writenext(host->scsi.io_port, SCpnt->cmd_len - host->scsi.SCp.sent_command); | 1322 | sbic_arm_writenext(host, SCpnt->cmd_len - host->scsi.SCp.sent_command); |
1326 | 1323 | ||
1327 | acornscsi_sbic_issuecmd(host, CMND_XFERINFO); | 1324 | acornscsi_sbic_issuecmd(host, CMND_XFERINFO); |
1328 | 1325 | ||
@@ -1351,7 +1348,7 @@ void acornscsi_sendmessage(AS_Host *host) | |||
1351 | 1348 | ||
1352 | acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "sending message 1"); | 1349 | acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "sending message 1"); |
1353 | 1350 | ||
1354 | sbic_arm_write(host->scsi.io_port, SBIC_DATA, NOP); | 1351 | sbic_arm_write(host, SBIC_DATA, NOP); |
1355 | 1352 | ||
1356 | host->scsi.last_message = NOP; | 1353 | host->scsi.last_message = NOP; |
1357 | #if (DEBUG & DEBUG_MESSAGES) | 1354 | #if (DEBUG & DEBUG_MESSAGES) |
@@ -1365,7 +1362,7 @@ void acornscsi_sendmessage(AS_Host *host) | |||
1365 | 1362 | ||
1366 | acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "sending message 2"); | 1363 | acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "sending message 2"); |
1367 | 1364 | ||
1368 | sbic_arm_write(host->scsi.io_port, SBIC_DATA, msg->msg[0]); | 1365 | sbic_arm_write(host, SBIC_DATA, msg->msg[0]); |
1369 | 1366 | ||
1370 | host->scsi.last_message = msg->msg[0]; | 1367 | host->scsi.last_message = msg->msg[0]; |
1371 | #if (DEBUG & DEBUG_MESSAGES) | 1368 | #if (DEBUG & DEBUG_MESSAGES) |
@@ -1382,9 +1379,9 @@ void acornscsi_sendmessage(AS_Host *host) | |||
1382 | * initiator. This provides an interlock so that the | 1379 | * initiator. This provides an interlock so that the |
1383 | * initiator can determine which message byte is rejected. | 1380 | * initiator can determine which message byte is rejected. |
1384 | */ | 1381 | */ |
1385 | sbic_arm_write(host->scsi.io_port, SBIC_TRANSCNTH, 0); | 1382 | sbic_arm_write(host, SBIC_TRANSCNTH, 0); |
1386 | sbic_arm_writenext(host->scsi.io_port, 0); | 1383 | sbic_arm_writenext(host, 0); |
1387 | sbic_arm_writenext(host->scsi.io_port, message_length); | 1384 | sbic_arm_writenext(host, message_length); |
1388 | acornscsi_sbic_issuecmd(host, CMND_XFERINFO); | 1385 | acornscsi_sbic_issuecmd(host, CMND_XFERINFO); |
1389 | 1386 | ||
1390 | msgnr = 0; | 1387 | msgnr = 0; |
@@ -1421,7 +1418,7 @@ void acornscsi_readstatusbyte(AS_Host *host) | |||
1421 | { | 1418 | { |
1422 | acornscsi_sbic_issuecmd(host, CMND_XFERINFO|CMND_SBT); | 1419 | acornscsi_sbic_issuecmd(host, CMND_XFERINFO|CMND_SBT); |
1423 | acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "reading status byte"); | 1420 | acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "reading status byte"); |
1424 | host->scsi.SCp.Status = sbic_arm_read(host->scsi.io_port, SBIC_DATA); | 1421 | host->scsi.SCp.Status = sbic_arm_read(host, SBIC_DATA); |
1425 | } | 1422 | } |
1426 | 1423 | ||
1427 | /* | 1424 | /* |
@@ -1438,12 +1435,12 @@ unsigned char acornscsi_readmessagebyte(AS_Host *host) | |||
1438 | 1435 | ||
1439 | acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "for message byte"); | 1436 | acornscsi_sbic_wait(host, ASR_DBR, ASR_DBR, 1000, "for message byte"); |
1440 | 1437 | ||
1441 | message = sbic_arm_read(host->scsi.io_port, SBIC_DATA); | 1438 | message = sbic_arm_read(host, SBIC_DATA); |
1442 | 1439 | ||
1443 | /* wait for MSGIN-XFER-PAUSED */ | 1440 | /* wait for MSGIN-XFER-PAUSED */ |
1444 | acornscsi_sbic_wait(host, ASR_INT, ASR_INT, 1000, "for interrupt after message byte"); | 1441 | acornscsi_sbic_wait(host, ASR_INT, ASR_INT, 1000, "for interrupt after message byte"); |
1445 | 1442 | ||
1446 | sbic_arm_read(host->scsi.io_port, SBIC_SSR); | 1443 | sbic_arm_read(host, SBIC_SSR); |
1447 | 1444 | ||
1448 | return message; | 1445 | return message; |
1449 | } | 1446 | } |
@@ -1480,7 +1477,7 @@ void acornscsi_message(AS_Host *host) | |||
1480 | 1477 | ||
1481 | /* wait for next msg-in */ | 1478 | /* wait for next msg-in */ |
1482 | acornscsi_sbic_wait(host, ASR_INT, ASR_INT, 1000, "for interrupt after negate ack"); | 1479 | acornscsi_sbic_wait(host, ASR_INT, ASR_INT, 1000, "for interrupt after negate ack"); |
1483 | sbic_arm_read(host->scsi.io_port, SBIC_SSR); | 1480 | sbic_arm_read(host, SBIC_SSR); |
1484 | } | 1481 | } |
1485 | } while (msgidx < msglen); | 1482 | } while (msgidx < msglen); |
1486 | 1483 | ||
@@ -1602,7 +1599,7 @@ void acornscsi_message(AS_Host *host) | |||
1602 | host->host->host_no, acornscsi_target(host)); | 1599 | host->host->host_no, acornscsi_target(host)); |
1603 | host->device[host->SCpnt->device->id].sync_xfer = SYNCHTRANSFER_2DBA; | 1600 | host->device[host->SCpnt->device->id].sync_xfer = SYNCHTRANSFER_2DBA; |
1604 | host->device[host->SCpnt->device->id].sync_state = SYNC_ASYNCHRONOUS; | 1601 | host->device[host->SCpnt->device->id].sync_state = SYNC_ASYNCHRONOUS; |
1605 | sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer); | 1602 | sbic_arm_write(host, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer); |
1606 | break; | 1603 | break; |
1607 | 1604 | ||
1608 | default: | 1605 | default: |
@@ -1652,7 +1649,7 @@ void acornscsi_message(AS_Host *host) | |||
1652 | host->device[host->SCpnt->device->id].sync_xfer = | 1649 | host->device[host->SCpnt->device->id].sync_xfer = |
1653 | calc_sync_xfer(period * 4, length); | 1650 | calc_sync_xfer(period * 4, length); |
1654 | } | 1651 | } |
1655 | sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer); | 1652 | sbic_arm_write(host, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer); |
1656 | break; | 1653 | break; |
1657 | #else | 1654 | #else |
1658 | /* We do not accept synchronous transfers. Respond with a | 1655 | /* We do not accept synchronous transfers. Respond with a |
@@ -1792,10 +1789,10 @@ int acornscsi_starttransfer(AS_Host *host) | |||
1792 | 1789 | ||
1793 | residual = scsi_bufflen(host->SCpnt) - host->scsi.SCp.scsi_xferred; | 1790 | residual = scsi_bufflen(host->SCpnt) - host->scsi.SCp.scsi_xferred; |
1794 | 1791 | ||
1795 | sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer); | 1792 | sbic_arm_write(host, SBIC_SYNCHTRANSFER, host->device[host->SCpnt->device->id].sync_xfer); |
1796 | sbic_arm_writenext(host->scsi.io_port, residual >> 16); | 1793 | sbic_arm_writenext(host, residual >> 16); |
1797 | sbic_arm_writenext(host->scsi.io_port, residual >> 8); | 1794 | sbic_arm_writenext(host, residual >> 8); |
1798 | sbic_arm_writenext(host->scsi.io_port, residual); | 1795 | sbic_arm_writenext(host, residual); |
1799 | acornscsi_sbic_issuecmd(host, CMND_XFERINFO); | 1796 | acornscsi_sbic_issuecmd(host, CMND_XFERINFO); |
1800 | return 1; | 1797 | return 1; |
1801 | } | 1798 | } |
@@ -1816,7 +1813,7 @@ int acornscsi_reconnect(AS_Host *host) | |||
1816 | { | 1813 | { |
1817 | unsigned int target, lun, ok = 0; | 1814 | unsigned int target, lun, ok = 0; |
1818 | 1815 | ||
1819 | target = sbic_arm_read(host->scsi.io_port, SBIC_SOURCEID); | 1816 | target = sbic_arm_read(host, SBIC_SOURCEID); |
1820 | 1817 | ||
1821 | if (!(target & 8)) | 1818 | if (!(target & 8)) |
1822 | printk(KERN_ERR "scsi%d: invalid source id after reselection " | 1819 | printk(KERN_ERR "scsi%d: invalid source id after reselection " |
@@ -1832,7 +1829,7 @@ int acornscsi_reconnect(AS_Host *host) | |||
1832 | host->SCpnt = NULL; | 1829 | host->SCpnt = NULL; |
1833 | } | 1830 | } |
1834 | 1831 | ||
1835 | lun = sbic_arm_read(host->scsi.io_port, SBIC_DATA) & 7; | 1832 | lun = sbic_arm_read(host, SBIC_DATA) & 7; |
1836 | 1833 | ||
1837 | host->scsi.reconnected.target = target; | 1834 | host->scsi.reconnected.target = target; |
1838 | host->scsi.reconnected.lun = lun; | 1835 | host->scsi.reconnected.lun = lun; |
@@ -1952,7 +1949,7 @@ static | |||
1952 | void acornscsi_abortcmd(AS_Host *host, unsigned char tag) | 1949 | void acornscsi_abortcmd(AS_Host *host, unsigned char tag) |
1953 | { | 1950 | { |
1954 | host->scsi.phase = PHASE_ABORTED; | 1951 | host->scsi.phase = PHASE_ABORTED; |
1955 | sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_ASSERTATN); | 1952 | sbic_arm_write(host, SBIC_CMND, CMND_ASSERTATN); |
1956 | 1953 | ||
1957 | msgqueue_flush(&host->scsi.msgs); | 1954 | msgqueue_flush(&host->scsi.msgs); |
1958 | #ifdef CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE | 1955 | #ifdef CONFIG_SCSI_ACORNSCSI_TAGGED_QUEUE |
@@ -1979,11 +1976,11 @@ intr_ret_t acornscsi_sbicintr(AS_Host *host, int in_irq) | |||
1979 | { | 1976 | { |
1980 | unsigned int asr, ssr; | 1977 | unsigned int asr, ssr; |
1981 | 1978 | ||
1982 | asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR); | 1979 | asr = sbic_arm_read(host, SBIC_ASR); |
1983 | if (!(asr & ASR_INT)) | 1980 | if (!(asr & ASR_INT)) |
1984 | return INTR_IDLE; | 1981 | return INTR_IDLE; |
1985 | 1982 | ||
1986 | ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR); | 1983 | ssr = sbic_arm_read(host, SBIC_SSR); |
1987 | 1984 | ||
1988 | #if (DEBUG & DEBUG_PHASES) | 1985 | #if (DEBUG & DEBUG_PHASES) |
1989 | print_sbic_status(asr, ssr, host->scsi.phase); | 1986 | print_sbic_status(asr, ssr, host->scsi.phase); |
@@ -1999,15 +1996,15 @@ intr_ret_t acornscsi_sbicintr(AS_Host *host, int in_irq) | |||
1999 | printk(KERN_ERR "scsi%d: reset in standard mode but wanted advanced mode.\n", | 1996 | printk(KERN_ERR "scsi%d: reset in standard mode but wanted advanced mode.\n", |
2000 | host->host->host_no); | 1997 | host->host->host_no); |
2001 | /* setup sbic - WD33C93A */ | 1998 | /* setup sbic - WD33C93A */ |
2002 | sbic_arm_write(host->scsi.io_port, SBIC_OWNID, OWNID_EAF | host->host->this_id); | 1999 | sbic_arm_write(host, SBIC_OWNID, OWNID_EAF | host->host->this_id); |
2003 | sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_RESET); | 2000 | sbic_arm_write(host, SBIC_CMND, CMND_RESET); |
2004 | return INTR_IDLE; | 2001 | return INTR_IDLE; |
2005 | 2002 | ||
2006 | case 0x01: /* reset state - advanced */ | 2003 | case 0x01: /* reset state - advanced */ |
2007 | sbic_arm_write(host->scsi.io_port, SBIC_CTRL, INIT_SBICDMA | CTRL_IDI); | 2004 | sbic_arm_write(host, SBIC_CTRL, INIT_SBICDMA | CTRL_IDI); |
2008 | sbic_arm_write(host->scsi.io_port, SBIC_TIMEOUT, TIMEOUT_TIME); | 2005 | sbic_arm_write(host, SBIC_TIMEOUT, TIMEOUT_TIME); |
2009 | sbic_arm_write(host->scsi.io_port, SBIC_SYNCHTRANSFER, SYNCHTRANSFER_2DBA); | 2006 | sbic_arm_write(host, SBIC_SYNCHTRANSFER, SYNCHTRANSFER_2DBA); |
2010 | sbic_arm_write(host->scsi.io_port, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP); | 2007 | sbic_arm_write(host, SBIC_SOURCEID, SOURCEID_ER | SOURCEID_DSP); |
2011 | msgqueue_flush(&host->scsi.msgs); | 2008 | msgqueue_flush(&host->scsi.msgs); |
2012 | return INTR_IDLE; | 2009 | return INTR_IDLE; |
2013 | 2010 | ||
@@ -2025,10 +2022,10 @@ intr_ret_t acornscsi_sbicintr(AS_Host *host, int in_irq) | |||
2025 | msgqueue_flush(&host->scsi.msgs); | 2022 | msgqueue_flush(&host->scsi.msgs); |
2026 | host->dma.transferred = host->scsi.SCp.scsi_xferred; | 2023 | host->dma.transferred = host->scsi.SCp.scsi_xferred; |
2027 | /* 33C93 gives next interrupt indicating bus phase */ | 2024 | /* 33C93 gives next interrupt indicating bus phase */ |
2028 | asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR); | 2025 | asr = sbic_arm_read(host, SBIC_ASR); |
2029 | if (!(asr & ASR_INT)) | 2026 | if (!(asr & ASR_INT)) |
2030 | break; | 2027 | break; |
2031 | ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR); | 2028 | ssr = sbic_arm_read(host, SBIC_SSR); |
2032 | ADD_STATUS(8, ssr, host->scsi.phase, 1); | 2029 | ADD_STATUS(8, ssr, host->scsi.phase, 1); |
2033 | ADD_STATUS(host->SCpnt->device->id, ssr, host->scsi.phase, 1); | 2030 | ADD_STATUS(host->SCpnt->device->id, ssr, host->scsi.phase, 1); |
2034 | goto connected; | 2031 | goto connected; |
@@ -2476,11 +2473,11 @@ acornscsi_intr(int irq, void *dev_id) | |||
2476 | do { | 2473 | do { |
2477 | ret = INTR_IDLE; | 2474 | ret = INTR_IDLE; |
2478 | 2475 | ||
2479 | iostatus = inb(host->card.io_intr); | 2476 | iostatus = readb(host->fast + INT_REG); |
2480 | 2477 | ||
2481 | if (iostatus & 2) { | 2478 | if (iostatus & 2) { |
2482 | acornscsi_dma_intr(host); | 2479 | acornscsi_dma_intr(host); |
2483 | iostatus = inb(host->card.io_intr); | 2480 | iostatus = readb(host->fast + INT_REG); |
2484 | } | 2481 | } |
2485 | 2482 | ||
2486 | if (iostatus & 8) | 2483 | if (iostatus & 8) |
@@ -2655,7 +2652,7 @@ static enum res_abort acornscsi_do_abort(AS_Host *host, struct scsi_cmnd *SCpnt) | |||
2655 | * busylun bit. | 2652 | * busylun bit. |
2656 | */ | 2653 | */ |
2657 | case PHASE_CONNECTED: | 2654 | case PHASE_CONNECTED: |
2658 | sbic_arm_write(host->scsi.io_port, SBIC_CMND, CMND_DISCONNECT); | 2655 | sbic_arm_write(host, SBIC_CMND, CMND_DISCONNECT); |
2659 | host->SCpnt = NULL; | 2656 | host->SCpnt = NULL; |
2660 | res = res_success_clear; | 2657 | res = res_success_clear; |
2661 | break; | 2658 | break; |
@@ -2699,8 +2696,8 @@ int acornscsi_abort(struct scsi_cmnd *SCpnt) | |||
2699 | #if (DEBUG & DEBUG_ABORT) | 2696 | #if (DEBUG & DEBUG_ABORT) |
2700 | { | 2697 | { |
2701 | int asr, ssr; | 2698 | int asr, ssr; |
2702 | asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR); | 2699 | asr = sbic_arm_read(host, SBIC_ASR); |
2703 | ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR); | 2700 | ssr = sbic_arm_read(host, SBIC_SSR); |
2704 | 2701 | ||
2705 | printk(KERN_WARNING "acornscsi_abort: "); | 2702 | printk(KERN_WARNING "acornscsi_abort: "); |
2706 | print_sbic_status(asr, ssr, host->scsi.phase); | 2703 | print_sbic_status(asr, ssr, host->scsi.phase); |
@@ -2731,9 +2728,7 @@ int acornscsi_abort(struct scsi_cmnd *SCpnt) | |||
2731 | //#if (DEBUG & DEBUG_ABORT) | 2728 | //#if (DEBUG & DEBUG_ABORT) |
2732 | printk("success\n"); | 2729 | printk("success\n"); |
2733 | //#endif | 2730 | //#endif |
2734 | SCpnt->result = DID_ABORT << 16; | 2731 | result = SUCCESS; |
2735 | SCpnt->scsi_done(SCpnt); | ||
2736 | result = SCSI_ABORT_SUCCESS; | ||
2737 | break; | 2732 | break; |
2738 | 2733 | ||
2739 | /* | 2734 | /* |
@@ -2745,7 +2740,7 @@ int acornscsi_abort(struct scsi_cmnd *SCpnt) | |||
2745 | //#if (DEBUG & DEBUG_ABORT) | 2740 | //#if (DEBUG & DEBUG_ABORT) |
2746 | printk("snooze\n"); | 2741 | printk("snooze\n"); |
2747 | //#endif | 2742 | //#endif |
2748 | result = SCSI_ABORT_SNOOZE; | 2743 | result = FAILED; |
2749 | break; | 2744 | break; |
2750 | 2745 | ||
2751 | /* | 2746 | /* |
@@ -2755,11 +2750,7 @@ int acornscsi_abort(struct scsi_cmnd *SCpnt) | |||
2755 | default: | 2750 | default: |
2756 | case res_not_running: | 2751 | case res_not_running: |
2757 | acornscsi_dumplog(host, SCpnt->device->id); | 2752 | acornscsi_dumplog(host, SCpnt->device->id); |
2758 | #if (DEBUG & DEBUG_ABORT) | 2753 | result = FAILED; |
2759 | result = SCSI_ABORT_SNOOZE; | ||
2760 | #else | ||
2761 | result = SCSI_ABORT_NOT_RUNNING; | ||
2762 | #endif | ||
2763 | //#if (DEBUG & DEBUG_ABORT) | 2754 | //#if (DEBUG & DEBUG_ABORT) |
2764 | printk("not running\n"); | 2755 | printk("not running\n"); |
2765 | //#endif | 2756 | //#endif |
@@ -2770,13 +2761,12 @@ int acornscsi_abort(struct scsi_cmnd *SCpnt) | |||
2770 | } | 2761 | } |
2771 | 2762 | ||
2772 | /* | 2763 | /* |
2773 | * Prototype: int acornscsi_reset(struct scsi_cmnd *SCpnt, unsigned int reset_flags) | 2764 | * Prototype: int acornscsi_reset(struct scsi_cmnd *SCpnt) |
2774 | * Purpose : reset a command on this host/reset this host | 2765 | * Purpose : reset a command on this host/reset this host |
2775 | * Params : SCpnt - command causing reset | 2766 | * Params : SCpnt - command causing reset |
2776 | * result - what type of reset to perform | ||
2777 | * Returns : one of SCSI_RESET_ macros | 2767 | * Returns : one of SCSI_RESET_ macros |
2778 | */ | 2768 | */ |
2779 | int acornscsi_reset(struct scsi_cmnd *SCpnt, unsigned int reset_flags) | 2769 | int acornscsi_bus_reset(struct scsi_cmnd *SCpnt) |
2780 | { | 2770 | { |
2781 | AS_Host *host = (AS_Host *)SCpnt->device->host->hostdata; | 2771 | AS_Host *host = (AS_Host *)SCpnt->device->host->hostdata; |
2782 | struct scsi_cmnd *SCptr; | 2772 | struct scsi_cmnd *SCptr; |
@@ -2787,8 +2777,8 @@ int acornscsi_reset(struct scsi_cmnd *SCpnt, unsigned int reset_flags) | |||
2787 | { | 2777 | { |
2788 | int asr, ssr; | 2778 | int asr, ssr; |
2789 | 2779 | ||
2790 | asr = sbic_arm_read(host->scsi.io_port, SBIC_ASR); | 2780 | asr = sbic_arm_read(host, SBIC_ASR); |
2791 | ssr = sbic_arm_read(host->scsi.io_port, SBIC_SSR); | 2781 | ssr = sbic_arm_read(host, SBIC_SSR); |
2792 | 2782 | ||
2793 | printk(KERN_WARNING "acornscsi_reset: "); | 2783 | printk(KERN_WARNING "acornscsi_reset: "); |
2794 | print_sbic_status(asr, ssr, host->scsi.phase); | 2784 | print_sbic_status(asr, ssr, host->scsi.phase); |
@@ -2798,28 +2788,16 @@ int acornscsi_reset(struct scsi_cmnd *SCpnt, unsigned int reset_flags) | |||
2798 | 2788 | ||
2799 | acornscsi_dma_stop(host); | 2789 | acornscsi_dma_stop(host); |
2800 | 2790 | ||
2801 | SCptr = host->SCpnt; | ||
2802 | |||
2803 | /* | 2791 | /* |
2804 | * do hard reset. This resets all devices on this host, and so we | 2792 | * do hard reset. This resets all devices on this host, and so we |
2805 | * must set the reset status on all commands. | 2793 | * must set the reset status on all commands. |
2806 | */ | 2794 | */ |
2807 | acornscsi_resetcard(host); | 2795 | acornscsi_resetcard(host); |
2808 | 2796 | ||
2809 | /* | ||
2810 | * report reset on commands current connected/disconnected | ||
2811 | */ | ||
2812 | acornscsi_reportstatus(&host->SCpnt, &SCptr, DID_RESET); | ||
2813 | |||
2814 | while ((SCptr = queue_remove(&host->queues.disconnected)) != NULL) | 2797 | while ((SCptr = queue_remove(&host->queues.disconnected)) != NULL) |
2815 | acornscsi_reportstatus(&SCptr, &SCpnt, DID_RESET); | 2798 | ; |
2816 | |||
2817 | if (SCpnt) { | ||
2818 | SCpnt->result = DID_RESET << 16; | ||
2819 | SCpnt->scsi_done(SCpnt); | ||
2820 | } | ||
2821 | 2799 | ||
2822 | return SCSI_RESET_BUS_RESET | SCSI_RESET_HOST_RESET | SCSI_RESET_SUCCESS; | 2800 | return SUCCESS; |
2823 | } | 2801 | } |
2824 | 2802 | ||
2825 | /*============================================================================================== | 2803 | /*============================================================================================== |
@@ -2850,7 +2828,7 @@ char *acornscsi_info(struct Scsi_Host *host) | |||
2850 | " LINK" | 2828 | " LINK" |
2851 | #endif | 2829 | #endif |
2852 | #if (DEBUG & DEBUG_NO_WRITE) | 2830 | #if (DEBUG & DEBUG_NO_WRITE) |
2853 | " NOWRITE ("NO_WRITE_STR")" | 2831 | " NOWRITE (" __stringify(NO_WRITE) ")" |
2854 | #endif | 2832 | #endif |
2855 | , host->hostt->name, host->io_port, host->irq, | 2833 | , host->hostt->name, host->io_port, host->irq, |
2856 | VER_MAJOR, VER_MINOR, VER_PATCH); | 2834 | VER_MAJOR, VER_MINOR, VER_PATCH); |
@@ -2881,15 +2859,15 @@ int acornscsi_proc_info(struct Scsi_Host *instance, char *buffer, char **start, | |||
2881 | " LINK" | 2859 | " LINK" |
2882 | #endif | 2860 | #endif |
2883 | #if (DEBUG & DEBUG_NO_WRITE) | 2861 | #if (DEBUG & DEBUG_NO_WRITE) |
2884 | " NOWRITE ("NO_WRITE_STR")" | 2862 | " NOWRITE (" __stringify(NO_WRITE) ")" |
2885 | #endif | 2863 | #endif |
2886 | "\n\n", VER_MAJOR, VER_MINOR, VER_PATCH); | 2864 | "\n\n", VER_MAJOR, VER_MINOR, VER_PATCH); |
2887 | 2865 | ||
2888 | p += sprintf(p, "SBIC: WD33C93A Address: %08X IRQ : %d\n", | 2866 | p += sprintf(p, "SBIC: WD33C93A Address: %p IRQ : %d\n", |
2889 | host->scsi.io_port, host->scsi.irq); | 2867 | host->base + SBIC_REGIDX, host->scsi.irq); |
2890 | #ifdef USE_DMAC | 2868 | #ifdef USE_DMAC |
2891 | p += sprintf(p, "DMAC: uPC71071 Address: %08X IRQ : %d\n\n", | 2869 | p += sprintf(p, "DMAC: uPC71071 Address: %p IRQ : %d\n\n", |
2892 | host->dma.io_port, host->scsi.irq); | 2870 | host->base + DMAC_OFFSET, host->scsi.irq); |
2893 | #endif | 2871 | #endif |
2894 | 2872 | ||
2895 | p += sprintf(p, "Statistics:\n" | 2873 | p += sprintf(p, "Statistics:\n" |
@@ -2976,9 +2954,8 @@ static struct scsi_host_template acornscsi_template = { | |||
2976 | .name = "AcornSCSI", | 2954 | .name = "AcornSCSI", |
2977 | .info = acornscsi_info, | 2955 | .info = acornscsi_info, |
2978 | .queuecommand = acornscsi_queuecmd, | 2956 | .queuecommand = acornscsi_queuecmd, |
2979 | #warning fixme | 2957 | .eh_abort_handler = acornscsi_abort, |
2980 | .abort = acornscsi_abort, | 2958 | .eh_bus_reset_handler = acornscsi_bus_reset, |
2981 | .reset = acornscsi_reset, | ||
2982 | .can_queue = 16, | 2959 | .can_queue = 16, |
2983 | .this_id = 7, | 2960 | .this_id = 7, |
2984 | .sg_tablesize = SG_ALL, | 2961 | .sg_tablesize = SG_ALL, |
@@ -2992,48 +2969,37 @@ acornscsi_probe(struct expansion_card *ec, const struct ecard_id *id) | |||
2992 | { | 2969 | { |
2993 | struct Scsi_Host *host; | 2970 | struct Scsi_Host *host; |
2994 | AS_Host *ashost; | 2971 | AS_Host *ashost; |
2995 | int ret = -ENOMEM; | 2972 | int ret; |
2996 | 2973 | ||
2997 | host = scsi_host_alloc(&acornscsi_template, sizeof(AS_Host)); | 2974 | ret = ecard_request_resources(ec); |
2998 | if (!host) | 2975 | if (ret) |
2999 | goto out; | 2976 | goto out; |
3000 | 2977 | ||
2978 | host = scsi_host_alloc(&acornscsi_template, sizeof(AS_Host)); | ||
2979 | if (!host) { | ||
2980 | ret = -ENOMEM; | ||
2981 | goto out_release; | ||
2982 | } | ||
2983 | |||
3001 | ashost = (AS_Host *)host->hostdata; | 2984 | ashost = (AS_Host *)host->hostdata; |
3002 | 2985 | ||
3003 | host->io_port = ecard_address(ec, ECARD_MEMC, 0); | 2986 | ashost->base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0); |
3004 | host->irq = ec->irq; | 2987 | ashost->fast = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0); |
2988 | if (!ashost->base || !ashost->fast) | ||
2989 | goto out_put; | ||
3005 | 2990 | ||
3006 | ashost->host = host; | 2991 | host->irq = ec->irq; |
3007 | ashost->scsi.io_port = ioaddr(host->io_port + 0x800); | 2992 | ashost->host = host; |
3008 | ashost->scsi.irq = host->irq; | 2993 | ashost->scsi.irq = host->irq; |
3009 | ashost->card.io_intr = POD_SPACE(host->io_port) + 0x800; | ||
3010 | ashost->card.io_page = POD_SPACE(host->io_port) + 0xc00; | ||
3011 | ashost->card.io_ram = ioaddr(host->io_port); | ||
3012 | ashost->dma.io_port = host->io_port + 0xc00; | ||
3013 | ashost->dma.io_intr_clear = POD_SPACE(host->io_port) + 0x800; | ||
3014 | 2994 | ||
3015 | ec->irqaddr = (char *)ioaddr(ashost->card.io_intr); | 2995 | ec->irqaddr = ashost->fast + INT_REG; |
3016 | ec->irqmask = 0x0a; | 2996 | ec->irqmask = 0x0a; |
3017 | 2997 | ||
3018 | ret = -EBUSY; | ||
3019 | if (!request_region(host->io_port + 0x800, 2, "acornscsi(sbic)")) | ||
3020 | goto err_1; | ||
3021 | if (!request_region(ashost->card.io_intr, 1, "acornscsi(intr)")) | ||
3022 | goto err_2; | ||
3023 | if (!request_region(ashost->card.io_page, 1, "acornscsi(page)")) | ||
3024 | goto err_3; | ||
3025 | #ifdef USE_DMAC | ||
3026 | if (!request_region(ashost->dma.io_port, 256, "acornscsi(dmac)")) | ||
3027 | goto err_4; | ||
3028 | #endif | ||
3029 | if (!request_region(host->io_port, 2048, "acornscsi(ram)")) | ||
3030 | goto err_5; | ||
3031 | |||
3032 | ret = request_irq(host->irq, acornscsi_intr, IRQF_DISABLED, "acornscsi", ashost); | 2998 | ret = request_irq(host->irq, acornscsi_intr, IRQF_DISABLED, "acornscsi", ashost); |
3033 | if (ret) { | 2999 | if (ret) { |
3034 | printk(KERN_CRIT "scsi%d: IRQ%d not free: %d\n", | 3000 | printk(KERN_CRIT "scsi%d: IRQ%d not free: %d\n", |
3035 | host->host_no, ashost->scsi.irq, ret); | 3001 | host->host_no, ashost->scsi.irq, ret); |
3036 | goto err_6; | 3002 | goto out_put; |
3037 | } | 3003 | } |
3038 | 3004 | ||
3039 | memset(&ashost->stats, 0, sizeof (ashost->stats)); | 3005 | memset(&ashost->stats, 0, sizeof (ashost->stats)); |
@@ -3045,27 +3011,22 @@ acornscsi_probe(struct expansion_card *ec, const struct ecard_id *id) | |||
3045 | 3011 | ||
3046 | ret = scsi_add_host(host, &ec->dev); | 3012 | ret = scsi_add_host(host, &ec->dev); |
3047 | if (ret) | 3013 | if (ret) |
3048 | goto err_7; | 3014 | goto out_irq; |
3049 | 3015 | ||
3050 | scsi_scan_host(host); | 3016 | scsi_scan_host(host); |
3051 | goto out; | 3017 | goto out; |
3052 | 3018 | ||
3053 | err_7: | 3019 | out_irq: |
3054 | free_irq(host->irq, ashost); | 3020 | free_irq(host->irq, ashost); |
3055 | err_6: | 3021 | msgqueue_free(&ashost->scsi.msgs); |
3056 | release_region(host->io_port, 2048); | 3022 | queue_free(&ashost->queues.disconnected); |
3057 | err_5: | 3023 | queue_free(&ashost->queues.issue); |
3058 | #ifdef USE_DMAC | 3024 | out_put: |
3059 | release_region(ashost->dma.io_port, 256); | 3025 | ecardm_iounmap(ec, ashost->fast); |
3060 | #endif | 3026 | ecardm_iounmap(ec, ashost->base); |
3061 | err_4: | ||
3062 | release_region(ashost->card.io_page, 1); | ||
3063 | err_3: | ||
3064 | release_region(ashost->card.io_intr, 1); | ||
3065 | err_2: | ||
3066 | release_region(host->io_port + 0x800, 2); | ||
3067 | err_1: | ||
3068 | scsi_host_put(host); | 3027 | scsi_host_put(host); |
3028 | out_release: | ||
3029 | ecard_release_resources(ec); | ||
3069 | out: | 3030 | out: |
3070 | return ret; | 3031 | return ret; |
3071 | } | 3032 | } |
@@ -3081,20 +3042,17 @@ static void __devexit acornscsi_remove(struct expansion_card *ec) | |||
3081 | /* | 3042 | /* |
3082 | * Put card into RESET state | 3043 | * Put card into RESET state |
3083 | */ | 3044 | */ |
3084 | outb(0x80, ashost->card.io_page); | 3045 | writeb(0x80, ashost->fast + PAGE_REG); |
3085 | 3046 | ||
3086 | free_irq(host->irq, ashost); | 3047 | free_irq(host->irq, ashost); |
3087 | 3048 | ||
3088 | release_region(host->io_port + 0x800, 2); | ||
3089 | release_region(ashost->card.io_intr, 1); | ||
3090 | release_region(ashost->card.io_page, 1); | ||
3091 | release_region(ashost->dma.io_port, 256); | ||
3092 | release_region(host->io_port, 2048); | ||
3093 | |||
3094 | msgqueue_free(&ashost->scsi.msgs); | 3049 | msgqueue_free(&ashost->scsi.msgs); |
3095 | queue_free(&ashost->queues.disconnected); | 3050 | queue_free(&ashost->queues.disconnected); |
3096 | queue_free(&ashost->queues.issue); | 3051 | queue_free(&ashost->queues.issue); |
3052 | ecardm_iounmap(ec, ashost->fast); | ||
3053 | ecardm_iounmap(ec, ashost->base); | ||
3097 | scsi_host_put(host); | 3054 | scsi_host_put(host); |
3055 | ecard_release_resources(ec); | ||
3098 | } | 3056 | } |
3099 | 3057 | ||
3100 | static const struct ecard_id acornscsi_cids[] = { | 3058 | static const struct ecard_id acornscsi_cids[] = { |
diff --git a/drivers/scsi/arm/acornscsi.h b/drivers/scsi/arm/acornscsi.h index d11424b89f42..8d2172a0b351 100644 --- a/drivers/scsi/arm/acornscsi.h +++ b/drivers/scsi/arm/acornscsi.h | |||
@@ -179,7 +179,6 @@ | |||
179 | 179 | ||
180 | /* miscellaneous internal variables */ | 180 | /* miscellaneous internal variables */ |
181 | 181 | ||
182 | #define POD_SPACE(x) ((x) + 0xd0000) | ||
183 | #define MASK_ON (MASKREG_M3|MASKREG_M2|MASKREG_M1|MASKREG_M0) | 182 | #define MASK_ON (MASKREG_M3|MASKREG_M2|MASKREG_M1|MASKREG_M0) |
184 | #define MASK_OFF (MASKREG_M3|MASKREG_M2|MASKREG_M1) | 183 | #define MASK_OFF (MASKREG_M3|MASKREG_M2|MASKREG_M1) |
185 | 184 | ||
@@ -279,10 +278,11 @@ typedef struct acornscsi_hostdata { | |||
279 | struct Scsi_Host *host; /* host */ | 278 | struct Scsi_Host *host; /* host */ |
280 | struct scsi_cmnd *SCpnt; /* currently processing command */ | 279 | struct scsi_cmnd *SCpnt; /* currently processing command */ |
281 | struct scsi_cmnd *origSCpnt; /* original connecting command */ | 280 | struct scsi_cmnd *origSCpnt; /* original connecting command */ |
281 | void __iomem *base; /* memc base address */ | ||
282 | void __iomem *fast; /* fast ioc base address */ | ||
282 | 283 | ||
283 | /* driver information */ | 284 | /* driver information */ |
284 | struct { | 285 | struct { |
285 | unsigned int io_port; /* base address of WD33C93 */ | ||
286 | unsigned int irq; /* interrupt */ | 286 | unsigned int irq; /* interrupt */ |
287 | phase_t phase; /* current phase */ | 287 | phase_t phase; /* current phase */ |
288 | 288 | ||
@@ -329,8 +329,6 @@ typedef struct acornscsi_hostdata { | |||
329 | 329 | ||
330 | /* DMA info */ | 330 | /* DMA info */ |
331 | struct { | 331 | struct { |
332 | unsigned int io_port; /* base address of DMA controller */ | ||
333 | unsigned int io_intr_clear; /* address of DMA interrupt clear */ | ||
334 | unsigned int free_addr; /* next free address */ | 332 | unsigned int free_addr; /* next free address */ |
335 | unsigned int start_addr; /* start address of current transfer */ | 333 | unsigned int start_addr; /* start address of current transfer */ |
336 | dmadir_t direction; /* dma direction */ | 334 | dmadir_t direction; /* dma direction */ |
@@ -345,9 +343,6 @@ typedef struct acornscsi_hostdata { | |||
345 | 343 | ||
346 | /* card info */ | 344 | /* card info */ |
347 | struct { | 345 | struct { |
348 | unsigned int io_intr; /* base address of interrupt id reg */ | ||
349 | unsigned int io_page; /* base address of page reg */ | ||
350 | unsigned int io_ram; /* base address of RAM access */ | ||
351 | unsigned char page_reg; /* current setting of page reg */ | 346 | unsigned char page_reg; /* current setting of page reg */ |
352 | } card; | 347 | } card; |
353 | 348 | ||
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 9bc42763623c..18ca9075e131 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig | |||
@@ -448,22 +448,27 @@ config SERIAL_CLPS711X_CONSOLE | |||
448 | your boot loader (lilo or loadlin) about how to pass options to the | 448 | your boot loader (lilo or loadlin) about how to pass options to the |
449 | kernel at boot time.) | 449 | kernel at boot time.) |
450 | 450 | ||
451 | config SERIAL_S3C2410 | 451 | config SERIAL_SAMSUNG |
452 | tristate "Samsung S3C2410/S3C2440/S3C2442/S3C2412 Serial port support" | 452 | tristate "Samsung SoC serial support" |
453 | depends on ARM && ARCH_S3C2410 | 453 | depends on ARM && PLAT_S3C24XX |
454 | select SERIAL_CORE | ||
455 | help | 454 | help |
456 | Support for the on-chip UARTs on the Samsung S3C24XX series CPUs, | 455 | Support for the on-chip UARTs on the Samsung S3C24XX series CPUs, |
457 | providing /dev/ttySAC0, 1 and 2 (note, some machines may not | 456 | providing /dev/ttySAC0, 1 and 2 (note, some machines may not |
458 | provide all of these ports, depending on how the serial port | 457 | provide all of these ports, depending on how the serial port |
459 | pins are configured. | 458 | pins are configured. |
460 | 459 | ||
461 | Currently this driver supports the UARTS on the S3C2410, S3C2440, | 460 | config SERIAL_SAMSUNG_DEBUG |
462 | S3C2442, S3C2412 and S3C2413 CPUs. | 461 | bool "Samsung SoC serial debug" |
462 | depends on SERIAL_SAMSUNG | ||
463 | help | ||
464 | Add support for debugging the serial driver. Since this is | ||
465 | generally being used as a console, we use our own output | ||
466 | routines that go via the low-level debug printascii() | ||
467 | function. | ||
463 | 468 | ||
464 | config SERIAL_S3C2410_CONSOLE | 469 | config SERIAL_SAMSUNG_CONSOLE |
465 | bool "Support for console on S3C2410 serial port" | 470 | bool "Support for console on Samsung SoC serial port" |
466 | depends on SERIAL_S3C2410=y | 471 | depends on SERIAL_SAMSUNG=y |
467 | select SERIAL_CORE_CONSOLE | 472 | select SERIAL_CORE_CONSOLE |
468 | help | 473 | help |
469 | Allow selection of the S3C24XX on-board serial ports for use as | 474 | Allow selection of the S3C24XX on-board serial ports for use as |
@@ -476,6 +481,37 @@ config SERIAL_S3C2410_CONSOLE | |||
476 | your boot loader about how to pass options to the kernel at | 481 | your boot loader about how to pass options to the kernel at |
477 | boot time.) | 482 | boot time.) |
478 | 483 | ||
484 | config SERIAL_S3C2400 | ||
485 | tristate "Samsung S3C2410 Serial port support" | ||
486 | depends on ARM && SERIAL_SAMSUNG && CPU_S3C2400 | ||
487 | default y if CPU_S3C2400 | ||
488 | help | ||
489 | Serial port support for the Samsung S3C2400 SoC | ||
490 | |||
491 | config SERIAL_S3C2410 | ||
492 | tristate "Samsung S3C2410 Serial port support" | ||
493 | depends on SERIAL_SAMSUNG && CPU_S3C2410 | ||
494 | default y if CPU_S3C2410 | ||
495 | help | ||
496 | Serial port support for the Samsung S3C2410 SoC | ||
497 | |||
498 | config SERIAL_S3C2412 | ||
499 | tristate "Samsung S3C2412/S3C2413 Serial port support" | ||
500 | depends on SERIAL_SAMSUNG && CPU_S3C2412 | ||
501 | default y if CPU_S3C2412 | ||
502 | help | ||
503 | Serial port support for the Samsung S3C2412 and S3C2413 SoC | ||
504 | |||
505 | config SERIAL_S3C2440 | ||
506 | tristate "Samsung S3C2440/S3C2442 Serial port support" | ||
507 | depends on SERIAL_SAMSUNG && (CPU_S3C2440 || CPU_S3C2442) | ||
508 | default y if CPU_S3C2440 | ||
509 | default y if CPU_S3C2442 | ||
510 | help | ||
511 | Serial port support for the Samsung S3C2440 and S3C2442 SoC | ||
512 | |||
513 | |||
514 | |||
479 | config SERIAL_DZ | 515 | config SERIAL_DZ |
480 | bool "DECstation DZ serial driver" | 516 | bool "DECstation DZ serial driver" |
481 | depends on MACH_DECSTATION && 32BIT | 517 | depends on MACH_DECSTATION && 32BIT |
@@ -753,7 +789,7 @@ config BFIN_UART3_CTSRTS | |||
753 | 789 | ||
754 | config SERIAL_IMX | 790 | config SERIAL_IMX |
755 | bool "IMX serial port support" | 791 | bool "IMX serial port support" |
756 | depends on ARM && ARCH_IMX | 792 | depends on ARM && (ARCH_IMX || ARCH_MXC) |
757 | select SERIAL_CORE | 793 | select SERIAL_CORE |
758 | help | 794 | help |
759 | If you have a machine based on a Motorola IMX CPU you | 795 | If you have a machine based on a Motorola IMX CPU you |
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 0d9c09b1e836..7d85c1fbe7e0 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile | |||
@@ -28,7 +28,11 @@ obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o | |||
28 | obj-$(CONFIG_SERIAL_SA1100) += sa1100.o | 28 | obj-$(CONFIG_SERIAL_SA1100) += sa1100.o |
29 | obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o | 29 | obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o |
30 | obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o | 30 | obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o |
31 | obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o | ||
32 | obj-$(CONFIG_SERIAL_S3C2400) += s3c2400.o | ||
31 | obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o | 33 | obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o |
34 | obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o | ||
35 | obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o | ||
32 | obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o | 36 | obj-$(CONFIG_SERIAL_SUNCORE) += suncore.o |
33 | obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o | 37 | obj-$(CONFIG_SERIAL_SUNHV) += sunhv.o |
34 | obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o | 38 | obj-$(CONFIG_SERIAL_SUNZILOG) += sunzilog.o |
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index 5a375bf0ebf4..64acb39a51ba 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c | |||
@@ -40,6 +40,7 @@ | |||
40 | #include <linux/tty_flip.h> | 40 | #include <linux/tty_flip.h> |
41 | #include <linux/serial_core.h> | 41 | #include <linux/serial_core.h> |
42 | #include <linux/serial.h> | 42 | #include <linux/serial.h> |
43 | #include <linux/clk.h> | ||
43 | 44 | ||
44 | #include <asm/io.h> | 45 | #include <asm/io.h> |
45 | #include <asm/irq.h> | 46 | #include <asm/irq.h> |
@@ -61,6 +62,11 @@ | |||
61 | #define UBIR 0xa4 /* BRM Incremental Register */ | 62 | #define UBIR 0xa4 /* BRM Incremental Register */ |
62 | #define UBMR 0xa8 /* BRM Modulator Register */ | 63 | #define UBMR 0xa8 /* BRM Modulator Register */ |
63 | #define UBRC 0xac /* Baud Rate Count Register */ | 64 | #define UBRC 0xac /* Baud Rate Count Register */ |
65 | #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 | ||
66 | #define ONEMS 0xb0 /* One Millisecond register */ | ||
67 | #define UTS 0xb4 /* UART Test Register */ | ||
68 | #endif | ||
69 | #ifdef CONFIG_ARCH_IMX | ||
64 | #define BIPR1 0xb0 /* Incremental Preset Register 1 */ | 70 | #define BIPR1 0xb0 /* Incremental Preset Register 1 */ |
65 | #define BIPR2 0xb4 /* Incremental Preset Register 2 */ | 71 | #define BIPR2 0xb4 /* Incremental Preset Register 2 */ |
66 | #define BIPR3 0xb8 /* Incremental Preset Register 3 */ | 72 | #define BIPR3 0xb8 /* Incremental Preset Register 3 */ |
@@ -70,6 +76,7 @@ | |||
70 | #define BMPR3 0xc8 /* BRM Modulator Register 3 */ | 76 | #define BMPR3 0xc8 /* BRM Modulator Register 3 */ |
71 | #define BMPR4 0xcc /* BRM Modulator Register 4 */ | 77 | #define BMPR4 0xcc /* BRM Modulator Register 4 */ |
72 | #define UTS 0xd0 /* UART Test Register */ | 78 | #define UTS 0xd0 /* UART Test Register */ |
79 | #endif | ||
73 | 80 | ||
74 | /* UART Control Register Bit Fields.*/ | 81 | /* UART Control Register Bit Fields.*/ |
75 | #define URXD_CHARRDY (1<<15) | 82 | #define URXD_CHARRDY (1<<15) |
@@ -89,7 +96,12 @@ | |||
89 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | 96 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ |
90 | #define UCR1_SNDBRK (1<<4) /* Send break */ | 97 | #define UCR1_SNDBRK (1<<4) /* Send break */ |
91 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | 98 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ |
99 | #ifdef CONFIG_ARCH_IMX | ||
92 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ | 100 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ |
101 | #endif | ||
102 | #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 | ||
103 | #define UCR1_UARTCLKEN (0) /* not present on mx2/mx3 */ | ||
104 | #endif | ||
93 | #define UCR1_DOZE (1<<1) /* Doze */ | 105 | #define UCR1_DOZE (1<<1) /* Doze */ |
94 | #define UCR1_UARTEN (1<<0) /* UART enabled */ | 106 | #define UCR1_UARTEN (1<<0) /* UART enabled */ |
95 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ | 107 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ |
@@ -163,8 +175,19 @@ | |||
163 | #define UTS_SOFTRST (1<<0) /* Software reset */ | 175 | #define UTS_SOFTRST (1<<0) /* Software reset */ |
164 | 176 | ||
165 | /* We've been assigned a range on the "Low-density serial ports" major */ | 177 | /* We've been assigned a range on the "Low-density serial ports" major */ |
178 | #ifdef CONFIG_ARCH_IMX | ||
166 | #define SERIAL_IMX_MAJOR 204 | 179 | #define SERIAL_IMX_MAJOR 204 |
167 | #define MINOR_START 41 | 180 | #define MINOR_START 41 |
181 | #define DEV_NAME "ttySMX" | ||
182 | #define MAX_INTERNAL_IRQ IMX_IRQS | ||
183 | #endif | ||
184 | |||
185 | #if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2 | ||
186 | #define SERIAL_IMX_MAJOR 207 | ||
187 | #define MINOR_START 16 | ||
188 | #define DEV_NAME "ttymxc" | ||
189 | #define MAX_INTERNAL_IRQ MXC_MAX_INT_LINES | ||
190 | #endif | ||
168 | 191 | ||
169 | /* | 192 | /* |
170 | * This determines how often we check the modem status signals | 193 | * This determines how often we check the modem status signals |
@@ -176,12 +199,15 @@ | |||
176 | 199 | ||
177 | #define DRIVER_NAME "IMX-uart" | 200 | #define DRIVER_NAME "IMX-uart" |
178 | 201 | ||
202 | #define UART_NR 8 | ||
203 | |||
179 | struct imx_port { | 204 | struct imx_port { |
180 | struct uart_port port; | 205 | struct uart_port port; |
181 | struct timer_list timer; | 206 | struct timer_list timer; |
182 | unsigned int old_status; | 207 | unsigned int old_status; |
183 | int txirq,rxirq,rtsirq; | 208 | int txirq,rxirq,rtsirq; |
184 | int have_rtscts:1; | 209 | int have_rtscts:1; |
210 | struct clk *clk; | ||
185 | }; | 211 | }; |
186 | 212 | ||
187 | /* | 213 | /* |
@@ -405,6 +431,26 @@ out: | |||
405 | return IRQ_HANDLED; | 431 | return IRQ_HANDLED; |
406 | } | 432 | } |
407 | 433 | ||
434 | static irqreturn_t imx_int(int irq, void *dev_id) | ||
435 | { | ||
436 | struct imx_port *sport = dev_id; | ||
437 | unsigned int sts; | ||
438 | |||
439 | sts = readl(sport->port.membase + USR1); | ||
440 | |||
441 | if (sts & USR1_RRDY) | ||
442 | imx_rxint(irq, dev_id); | ||
443 | |||
444 | if (sts & USR1_TRDY && | ||
445 | readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) | ||
446 | imx_txint(irq, dev_id); | ||
447 | |||
448 | if (sts & USR1_RTSS) | ||
449 | imx_rtsint(irq, dev_id); | ||
450 | |||
451 | return IRQ_HANDLED; | ||
452 | } | ||
453 | |||
408 | /* | 454 | /* |
409 | * Return TIOCSER_TEMT when transmitter is not busy. | 455 | * Return TIOCSER_TEMT when transmitter is not busy. |
410 | */ | 456 | */ |
@@ -477,7 +523,8 @@ static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) | |||
477 | * RFDIV is set such way to satisfy requested uartclk value | 523 | * RFDIV is set such way to satisfy requested uartclk value |
478 | */ | 524 | */ |
479 | val = TXTL << 10 | RXTL; | 525 | val = TXTL << 10 | RXTL; |
480 | ufcr_rfdiv = (imx_get_perclk1() + sport->port.uartclk / 2) / sport->port.uartclk; | 526 | ufcr_rfdiv = (clk_get_rate(sport->clk) + sport->port.uartclk / 2) |
527 | / sport->port.uartclk; | ||
481 | 528 | ||
482 | if(!ufcr_rfdiv) | 529 | if(!ufcr_rfdiv) |
483 | ufcr_rfdiv = 1; | 530 | ufcr_rfdiv = 1; |
@@ -509,21 +556,34 @@ static int imx_startup(struct uart_port *port) | |||
509 | writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); | 556 | writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); |
510 | 557 | ||
511 | /* | 558 | /* |
512 | * Allocate the IRQ | 559 | * Allocate the IRQ(s) i.MX1 has three interrupts whereas later |
560 | * chips only have one interrupt. | ||
513 | */ | 561 | */ |
514 | retval = request_irq(sport->rxirq, imx_rxint, 0, | 562 | if (sport->txirq > 0) { |
515 | DRIVER_NAME, sport); | 563 | retval = request_irq(sport->rxirq, imx_rxint, 0, |
516 | if (retval) goto error_out1; | 564 | DRIVER_NAME, sport); |
517 | 565 | if (retval) | |
518 | retval = request_irq(sport->txirq, imx_txint, 0, | 566 | goto error_out1; |
519 | DRIVER_NAME, sport); | 567 | |
520 | if (retval) goto error_out2; | 568 | retval = request_irq(sport->txirq, imx_txint, 0, |
521 | 569 | DRIVER_NAME, sport); | |
522 | retval = request_irq(sport->rtsirq, imx_rtsint, | 570 | if (retval) |
523 | (sport->rtsirq < IMX_IRQS) ? 0 : | 571 | goto error_out2; |
572 | |||
573 | retval = request_irq(sport->rtsirq, imx_rtsint, | ||
574 | (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 : | ||
524 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | 575 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, |
525 | DRIVER_NAME, sport); | 576 | DRIVER_NAME, sport); |
526 | if (retval) goto error_out3; | 577 | if (retval) |
578 | goto error_out3; | ||
579 | } else { | ||
580 | retval = request_irq(sport->port.irq, imx_int, 0, | ||
581 | DRIVER_NAME, sport); | ||
582 | if (retval) { | ||
583 | free_irq(sport->port.irq, sport); | ||
584 | goto error_out1; | ||
585 | } | ||
586 | } | ||
527 | 587 | ||
528 | /* | 588 | /* |
529 | * Finally, clear and enable interrupts | 589 | * Finally, clear and enable interrupts |
@@ -548,9 +608,11 @@ static int imx_startup(struct uart_port *port) | |||
548 | return 0; | 608 | return 0; |
549 | 609 | ||
550 | error_out3: | 610 | error_out3: |
551 | free_irq(sport->txirq, sport); | 611 | if (sport->txirq) |
612 | free_irq(sport->txirq, sport); | ||
552 | error_out2: | 613 | error_out2: |
553 | free_irq(sport->rxirq, sport); | 614 | if (sport->rxirq) |
615 | free_irq(sport->rxirq, sport); | ||
554 | error_out1: | 616 | error_out1: |
555 | return retval; | 617 | return retval; |
556 | } | 618 | } |
@@ -568,9 +630,12 @@ static void imx_shutdown(struct uart_port *port) | |||
568 | /* | 630 | /* |
569 | * Free the interrupts | 631 | * Free the interrupts |
570 | */ | 632 | */ |
571 | free_irq(sport->rtsirq, sport); | 633 | if (sport->txirq > 0) { |
572 | free_irq(sport->txirq, sport); | 634 | free_irq(sport->rtsirq, sport); |
573 | free_irq(sport->rxirq, sport); | 635 | free_irq(sport->txirq, sport); |
636 | free_irq(sport->rxirq, sport); | ||
637 | } else | ||
638 | free_irq(sport->port.irq, sport); | ||
574 | 639 | ||
575 | /* | 640 | /* |
576 | * Disable all interrupts, port and break condition. | 641 | * Disable all interrupts, port and break condition. |
@@ -589,6 +654,7 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, | |||
589 | unsigned long flags; | 654 | unsigned long flags; |
590 | unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; | 655 | unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; |
591 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | 656 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; |
657 | unsigned int div, num, denom, ufcr; | ||
592 | 658 | ||
593 | /* | 659 | /* |
594 | * If we don't support modem control lines, don't allow | 660 | * If we don't support modem control lines, don't allow |
@@ -634,7 +700,7 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, | |||
634 | /* | 700 | /* |
635 | * Ask the core to calculate the divisor for us. | 701 | * Ask the core to calculate the divisor for us. |
636 | */ | 702 | */ |
637 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | 703 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); |
638 | quot = uart_get_divisor(port, baud); | 704 | quot = uart_get_divisor(port, baud); |
639 | 705 | ||
640 | spin_lock_irqsave(&sport->port.lock, flags); | 706 | spin_lock_irqsave(&sport->port.lock, flags); |
@@ -684,14 +750,41 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, | |||
684 | sport->port.membase + UCR2); | 750 | sport->port.membase + UCR2); |
685 | old_txrxen &= (UCR2_TXEN | UCR2_RXEN); | 751 | old_txrxen &= (UCR2_TXEN | UCR2_RXEN); |
686 | 752 | ||
687 | /* set the baud rate. We assume uartclk = 16 MHz | 753 | div = sport->port.uartclk / (baud * 16); |
688 | * | 754 | if (div > 7) |
689 | * baud * 16 UBIR - 1 | 755 | div = 7; |
690 | * --------- = -------- | 756 | if (!div) |
691 | * uartclk UBMR - 1 | 757 | div = 1; |
692 | */ | 758 | |
693 | writel((baud / 100) - 1, sport->port.membase + UBIR); | 759 | num = baud; |
694 | writel(10000 - 1, sport->port.membase + UBMR); | 760 | denom = port->uartclk / div / 16; |
761 | |||
762 | /* shift num and denom right until they fit into 16 bits */ | ||
763 | while (num > 0x10000 || denom > 0x10000) { | ||
764 | num >>= 1; | ||
765 | denom >>= 1; | ||
766 | } | ||
767 | if (num > 0) | ||
768 | num -= 1; | ||
769 | if (denom > 0) | ||
770 | denom -= 1; | ||
771 | |||
772 | writel(num, sport->port.membase + UBIR); | ||
773 | writel(denom, sport->port.membase + UBMR); | ||
774 | |||
775 | if (div == 7) | ||
776 | div = 6; /* 6 in RFDIV means divide by 7 */ | ||
777 | else | ||
778 | div = 6 - div; | ||
779 | |||
780 | ufcr = readl(sport->port.membase + UFCR); | ||
781 | ufcr = (ufcr & (~UFCR_RFDIV)) | | ||
782 | (div << 7); | ||
783 | writel(ufcr, sport->port.membase + UFCR); | ||
784 | |||
785 | #ifdef ONEMS | ||
786 | writel(sport->port.uartclk / div / 1000, sport->port.membase + ONEMS); | ||
787 | #endif | ||
695 | 788 | ||
696 | writel(old_ucr1, sport->port.membase + UCR1); | 789 | writel(old_ucr1, sport->port.membase + UCR1); |
697 | 790 | ||
@@ -801,65 +894,7 @@ static struct uart_ops imx_pops = { | |||
801 | .verify_port = imx_verify_port, | 894 | .verify_port = imx_verify_port, |
802 | }; | 895 | }; |
803 | 896 | ||
804 | static struct imx_port imx_ports[] = { | 897 | static struct imx_port *imx_ports[UART_NR]; |
805 | { | ||
806 | .txirq = UART1_MINT_TX, | ||
807 | .rxirq = UART1_MINT_RX, | ||
808 | .rtsirq = UART1_MINT_RTS, | ||
809 | .port = { | ||
810 | .type = PORT_IMX, | ||
811 | .iotype = UPIO_MEM, | ||
812 | .membase = (void *)IMX_UART1_BASE, | ||
813 | .mapbase = 0x00206000, | ||
814 | .irq = UART1_MINT_RX, | ||
815 | .uartclk = 16000000, | ||
816 | .fifosize = 32, | ||
817 | .flags = UPF_BOOT_AUTOCONF, | ||
818 | .ops = &imx_pops, | ||
819 | .line = 0, | ||
820 | }, | ||
821 | }, { | ||
822 | .txirq = UART2_MINT_TX, | ||
823 | .rxirq = UART2_MINT_RX, | ||
824 | .rtsirq = UART2_MINT_RTS, | ||
825 | .port = { | ||
826 | .type = PORT_IMX, | ||
827 | .iotype = UPIO_MEM, | ||
828 | .membase = (void *)IMX_UART2_BASE, | ||
829 | .mapbase = 0x00207000, | ||
830 | .irq = UART2_MINT_RX, | ||
831 | .uartclk = 16000000, | ||
832 | .fifosize = 32, | ||
833 | .flags = UPF_BOOT_AUTOCONF, | ||
834 | .ops = &imx_pops, | ||
835 | .line = 1, | ||
836 | }, | ||
837 | } | ||
838 | }; | ||
839 | |||
840 | /* | ||
841 | * Setup the IMX serial ports. | ||
842 | * Note also that we support "console=ttySMXx" where "x" is either 0 or 1. | ||
843 | * Which serial port this ends up being depends on the machine you're | ||
844 | * running this kernel on. I'm not convinced that this is a good idea, | ||
845 | * but that's the way it traditionally works. | ||
846 | * | ||
847 | */ | ||
848 | static void __init imx_init_ports(void) | ||
849 | { | ||
850 | static int first = 1; | ||
851 | int i; | ||
852 | |||
853 | if (!first) | ||
854 | return; | ||
855 | first = 0; | ||
856 | |||
857 | for (i = 0; i < ARRAY_SIZE(imx_ports); i++) { | ||
858 | init_timer(&imx_ports[i].timer); | ||
859 | imx_ports[i].timer.function = imx_timeout; | ||
860 | imx_ports[i].timer.data = (unsigned long)&imx_ports[i]; | ||
861 | } | ||
862 | } | ||
863 | 898 | ||
864 | #ifdef CONFIG_SERIAL_IMX_CONSOLE | 899 | #ifdef CONFIG_SERIAL_IMX_CONSOLE |
865 | static void imx_console_putchar(struct uart_port *port, int ch) | 900 | static void imx_console_putchar(struct uart_port *port, int ch) |
@@ -878,7 +913,7 @@ static void imx_console_putchar(struct uart_port *port, int ch) | |||
878 | static void | 913 | static void |
879 | imx_console_write(struct console *co, const char *s, unsigned int count) | 914 | imx_console_write(struct console *co, const char *s, unsigned int count) |
880 | { | 915 | { |
881 | struct imx_port *sport = &imx_ports[co->index]; | 916 | struct imx_port *sport = imx_ports[co->index]; |
882 | unsigned int old_ucr1, old_ucr2; | 917 | unsigned int old_ucr1, old_ucr2; |
883 | 918 | ||
884 | /* | 919 | /* |
@@ -944,7 +979,7 @@ imx_console_get_options(struct imx_port *sport, int *baud, | |||
944 | else | 979 | else |
945 | ucfr_rfdiv = 6 - ucfr_rfdiv; | 980 | ucfr_rfdiv = 6 - ucfr_rfdiv; |
946 | 981 | ||
947 | uartclk = imx_get_perclk1(); | 982 | uartclk = clk_get_rate(sport->clk); |
948 | uartclk /= ucfr_rfdiv; | 983 | uartclk /= ucfr_rfdiv; |
949 | 984 | ||
950 | { /* | 985 | { /* |
@@ -984,7 +1019,7 @@ imx_console_setup(struct console *co, char *options) | |||
984 | */ | 1019 | */ |
985 | if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) | 1020 | if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) |
986 | co->index = 0; | 1021 | co->index = 0; |
987 | sport = &imx_ports[co->index]; | 1022 | sport = imx_ports[co->index]; |
988 | 1023 | ||
989 | if (options) | 1024 | if (options) |
990 | uart_parse_options(options, &baud, &parity, &bits, &flow); | 1025 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
@@ -998,7 +1033,7 @@ imx_console_setup(struct console *co, char *options) | |||
998 | 1033 | ||
999 | static struct uart_driver imx_reg; | 1034 | static struct uart_driver imx_reg; |
1000 | static struct console imx_console = { | 1035 | static struct console imx_console = { |
1001 | .name = "ttySMX", | 1036 | .name = DEV_NAME, |
1002 | .write = imx_console_write, | 1037 | .write = imx_console_write, |
1003 | .device = uart_console_device, | 1038 | .device = uart_console_device, |
1004 | .setup = imx_console_setup, | 1039 | .setup = imx_console_setup, |
@@ -1007,14 +1042,6 @@ static struct console imx_console = { | |||
1007 | .data = &imx_reg, | 1042 | .data = &imx_reg, |
1008 | }; | 1043 | }; |
1009 | 1044 | ||
1010 | static int __init imx_rs_console_init(void) | ||
1011 | { | ||
1012 | imx_init_ports(); | ||
1013 | register_console(&imx_console); | ||
1014 | return 0; | ||
1015 | } | ||
1016 | console_initcall(imx_rs_console_init); | ||
1017 | |||
1018 | #define IMX_CONSOLE &imx_console | 1045 | #define IMX_CONSOLE &imx_console |
1019 | #else | 1046 | #else |
1020 | #define IMX_CONSOLE NULL | 1047 | #define IMX_CONSOLE NULL |
@@ -1023,7 +1050,7 @@ console_initcall(imx_rs_console_init); | |||
1023 | static struct uart_driver imx_reg = { | 1050 | static struct uart_driver imx_reg = { |
1024 | .owner = THIS_MODULE, | 1051 | .owner = THIS_MODULE, |
1025 | .driver_name = DRIVER_NAME, | 1052 | .driver_name = DRIVER_NAME, |
1026 | .dev_name = "ttySMX", | 1053 | .dev_name = DEV_NAME, |
1027 | .major = SERIAL_IMX_MAJOR, | 1054 | .major = SERIAL_IMX_MAJOR, |
1028 | .minor = MINOR_START, | 1055 | .minor = MINOR_START, |
1029 | .nr = ARRAY_SIZE(imx_ports), | 1056 | .nr = ARRAY_SIZE(imx_ports), |
@@ -1050,29 +1077,98 @@ static int serial_imx_resume(struct platform_device *dev) | |||
1050 | return 0; | 1077 | return 0; |
1051 | } | 1078 | } |
1052 | 1079 | ||
1053 | static int serial_imx_probe(struct platform_device *dev) | 1080 | static int serial_imx_probe(struct platform_device *pdev) |
1054 | { | 1081 | { |
1082 | struct imx_port *sport; | ||
1055 | struct imxuart_platform_data *pdata; | 1083 | struct imxuart_platform_data *pdata; |
1084 | void __iomem *base; | ||
1085 | int ret = 0; | ||
1086 | struct resource *res; | ||
1087 | |||
1088 | sport = kzalloc(sizeof(*sport), GFP_KERNEL); | ||
1089 | if (!sport) | ||
1090 | return -ENOMEM; | ||
1056 | 1091 | ||
1057 | imx_ports[dev->id].port.dev = &dev->dev; | 1092 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1093 | if (!res) { | ||
1094 | ret = -ENODEV; | ||
1095 | goto free; | ||
1096 | } | ||
1097 | |||
1098 | base = ioremap(res->start, PAGE_SIZE); | ||
1099 | if (!base) { | ||
1100 | ret = -ENOMEM; | ||
1101 | goto free; | ||
1102 | } | ||
1103 | |||
1104 | sport->port.dev = &pdev->dev; | ||
1105 | sport->port.mapbase = res->start; | ||
1106 | sport->port.membase = base; | ||
1107 | sport->port.type = PORT_IMX, | ||
1108 | sport->port.iotype = UPIO_MEM; | ||
1109 | sport->port.irq = platform_get_irq(pdev, 0); | ||
1110 | sport->rxirq = platform_get_irq(pdev, 0); | ||
1111 | sport->txirq = platform_get_irq(pdev, 1); | ||
1112 | sport->rtsirq = platform_get_irq(pdev, 2); | ||
1113 | sport->port.fifosize = 32; | ||
1114 | sport->port.ops = &imx_pops; | ||
1115 | sport->port.flags = UPF_BOOT_AUTOCONF; | ||
1116 | sport->port.line = pdev->id; | ||
1117 | init_timer(&sport->timer); | ||
1118 | sport->timer.function = imx_timeout; | ||
1119 | sport->timer.data = (unsigned long)sport; | ||
1120 | |||
1121 | sport->clk = clk_get(&pdev->dev, "uart_clk"); | ||
1122 | if (IS_ERR(sport->clk)) { | ||
1123 | ret = PTR_ERR(sport->clk); | ||
1124 | goto unmap; | ||
1125 | } | ||
1126 | clk_enable(sport->clk); | ||
1058 | 1127 | ||
1059 | pdata = (struct imxuart_platform_data *)dev->dev.platform_data; | 1128 | sport->port.uartclk = clk_get_rate(sport->clk); |
1129 | |||
1130 | imx_ports[pdev->id] = sport; | ||
1131 | |||
1132 | pdata = pdev->dev.platform_data; | ||
1060 | if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS)) | 1133 | if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS)) |
1061 | imx_ports[dev->id].have_rtscts = 1; | 1134 | sport->have_rtscts = 1; |
1135 | |||
1136 | if (pdata->init) | ||
1137 | pdata->init(pdev); | ||
1138 | |||
1139 | uart_add_one_port(&imx_reg, &sport->port); | ||
1140 | platform_set_drvdata(pdev, &sport->port); | ||
1062 | 1141 | ||
1063 | uart_add_one_port(&imx_reg, &imx_ports[dev->id].port); | ||
1064 | platform_set_drvdata(dev, &imx_ports[dev->id]); | ||
1065 | return 0; | 1142 | return 0; |
1143 | unmap: | ||
1144 | iounmap(sport->port.membase); | ||
1145 | free: | ||
1146 | kfree(sport); | ||
1147 | |||
1148 | return ret; | ||
1066 | } | 1149 | } |
1067 | 1150 | ||
1068 | static int serial_imx_remove(struct platform_device *dev) | 1151 | static int serial_imx_remove(struct platform_device *pdev) |
1069 | { | 1152 | { |
1070 | struct imx_port *sport = platform_get_drvdata(dev); | 1153 | struct imxuart_platform_data *pdata; |
1154 | struct imx_port *sport = platform_get_drvdata(pdev); | ||
1071 | 1155 | ||
1072 | platform_set_drvdata(dev, NULL); | 1156 | pdata = pdev->dev.platform_data; |
1073 | 1157 | ||
1074 | if (sport) | 1158 | platform_set_drvdata(pdev, NULL); |
1159 | |||
1160 | if (sport) { | ||
1075 | uart_remove_one_port(&imx_reg, &sport->port); | 1161 | uart_remove_one_port(&imx_reg, &sport->port); |
1162 | clk_put(sport->clk); | ||
1163 | } | ||
1164 | |||
1165 | clk_disable(sport->clk); | ||
1166 | |||
1167 | if (pdata->exit) | ||
1168 | pdata->exit(pdev); | ||
1169 | |||
1170 | iounmap(sport->port.membase); | ||
1171 | kfree(sport); | ||
1076 | 1172 | ||
1077 | return 0; | 1173 | return 0; |
1078 | } | 1174 | } |
@@ -1095,8 +1191,6 @@ static int __init imx_serial_init(void) | |||
1095 | 1191 | ||
1096 | printk(KERN_INFO "Serial: IMX driver\n"); | 1192 | printk(KERN_INFO "Serial: IMX driver\n"); |
1097 | 1193 | ||
1098 | imx_init_ports(); | ||
1099 | |||
1100 | ret = uart_register_driver(&imx_reg); | 1194 | ret = uart_register_driver(&imx_reg); |
1101 | if (ret) | 1195 | if (ret) |
1102 | return ret; | 1196 | return ret; |
diff --git a/drivers/serial/s3c2400.c b/drivers/serial/s3c2400.c new file mode 100644 index 000000000000..a1102053e553 --- /dev/null +++ b/drivers/serial/s3c2400.c | |||
@@ -0,0 +1,106 @@ | |||
1 | /* linux/drivers/serial/s3c240.c | ||
2 | * | ||
3 | * Driver for Samsung SoC onboard UARTs. | ||
4 | * | ||
5 | * Ben Dooks, Copyright (c) 2003-2005 Simtec Electronics | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/module.h> | ||
14 | #include <linux/ioport.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | |||
18 | #include <asm/irq.h> | ||
19 | |||
20 | #include <asm/hardware.h> | ||
21 | |||
22 | #include <asm/plat-s3c/regs-serial.h> | ||
23 | #include <asm/arch/regs-gpio.h> | ||
24 | |||
25 | #include "samsung.h" | ||
26 | |||
27 | static int s3c2400_serial_getsource(struct uart_port *port, | ||
28 | struct s3c24xx_uart_clksrc *clk) | ||
29 | { | ||
30 | clk->divisor = 1; | ||
31 | clk->name = "pclk"; | ||
32 | |||
33 | return 0; | ||
34 | } | ||
35 | |||
36 | static int s3c2400_serial_setsource(struct uart_port *port, | ||
37 | struct s3c24xx_uart_clksrc *clk) | ||
38 | { | ||
39 | return 0; | ||
40 | } | ||
41 | |||
42 | static int s3c2400_serial_resetport(struct uart_port *port, | ||
43 | struct s3c2410_uartcfg *cfg) | ||
44 | { | ||
45 | dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n", | ||
46 | port, port->mapbase, cfg); | ||
47 | |||
48 | wr_regl(port, S3C2410_UCON, cfg->ucon); | ||
49 | wr_regl(port, S3C2410_ULCON, cfg->ulcon); | ||
50 | |||
51 | /* reset both fifos */ | ||
52 | |||
53 | wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); | ||
54 | wr_regl(port, S3C2410_UFCON, cfg->ufcon); | ||
55 | |||
56 | return 0; | ||
57 | } | ||
58 | |||
59 | static struct s3c24xx_uart_info s3c2400_uart_inf = { | ||
60 | .name = "Samsung S3C2400 UART", | ||
61 | .type = PORT_S3C2400, | ||
62 | .fifosize = 16, | ||
63 | .rx_fifomask = S3C2410_UFSTAT_RXMASK, | ||
64 | .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, | ||
65 | .rx_fifofull = S3C2410_UFSTAT_RXFULL, | ||
66 | .tx_fifofull = S3C2410_UFSTAT_TXFULL, | ||
67 | .tx_fifomask = S3C2410_UFSTAT_TXMASK, | ||
68 | .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, | ||
69 | .get_clksrc = s3c2400_serial_getsource, | ||
70 | .set_clksrc = s3c2400_serial_setsource, | ||
71 | .reset_port = s3c2400_serial_resetport, | ||
72 | }; | ||
73 | |||
74 | static int s3c2400_serial_probe(struct platform_device *dev) | ||
75 | { | ||
76 | return s3c24xx_serial_probe(dev, &s3c2400_uart_inf); | ||
77 | } | ||
78 | |||
79 | static struct platform_driver s3c2400_serial_drv = { | ||
80 | .probe = s3c2400_serial_probe, | ||
81 | .remove = s3c24xx_serial_remove, | ||
82 | .driver = { | ||
83 | .name = "s3c2400-uart", | ||
84 | .owner = THIS_MODULE, | ||
85 | }, | ||
86 | }; | ||
87 | |||
88 | s3c24xx_console_init(&s3c2400_serial_drv, &s3c2400_uart_inf); | ||
89 | |||
90 | static inline int s3c2400_serial_init(void) | ||
91 | { | ||
92 | return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf); | ||
93 | } | ||
94 | |||
95 | static inline void s3c2400_serial_exit(void) | ||
96 | { | ||
97 | platform_driver_unregister(&s3c2400_serial_drv); | ||
98 | } | ||
99 | |||
100 | module_init(s3c2400_serial_init); | ||
101 | module_exit(s3c2400_serial_exit); | ||
102 | |||
103 | MODULE_LICENSE("GPL v2"); | ||
104 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | ||
105 | MODULE_DESCRIPTION("Samsung S3C2400 SoC Serial port driver"); | ||
106 | MODULE_ALIAS("platform:s3c2400-uart"); | ||
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c index 2b6a013639e6..c5f03f41686f 100644 --- a/drivers/serial/s3c2410.c +++ b/drivers/serial/s3c2410.c | |||
@@ -1,1270 +1,30 @@ | |||
1 | /* | 1 | /* linux/drivers/serial/s3c2410.c |
2 | * linux/drivers/serial/s3c2410.c | ||
3 | * | 2 | * |
4 | * Driver for onboard UARTs on the Samsung S3C24XX | 3 | * Driver for Samsung S3C2410 SoC onboard UARTs. |
5 | * | 4 | * |
6 | * Based on drivers/char/serial.c and drivers/char/21285.c | 5 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics |
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | 7 | * |
8 | * Ben Dooks, (c) 2003-2005 Simtec Electronics | 8 | * This program is free software; you can redistribute it and/or modify |
9 | * http://www.simtec.co.uk/products/SWLINUX/ | 9 | * it under the terms of the GNU General Public License version 2 as |
10 | * | 10 | * published by the Free Software Foundation. |
11 | * Changelog: | ||
12 | * | ||
13 | * 22-Jul-2004 BJD Finished off device rewrite | ||
14 | * | ||
15 | * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out | ||
16 | * problems with baud rate and loss of IR settings. Update | ||
17 | * to add configuration via platform_device structure | ||
18 | * | ||
19 | * 28-Sep-2004 BJD Re-write for the following items | ||
20 | * - S3C2410 and S3C2440 serial support | ||
21 | * - Power Management support | ||
22 | * - Fix console via IrDA devices | ||
23 | * - SysReq (Herbert Pötzl) | ||
24 | * - Break character handling (Herbert Pötzl) | ||
25 | * - spin-lock initialisation (Dimitry Andric) | ||
26 | * - added clock control | ||
27 | * - updated init code to use platform_device info | ||
28 | * | ||
29 | * 06-Mar-2005 BJD Add s3c2440 fclk clock source | ||
30 | * | ||
31 | * 09-Mar-2005 BJD Add s3c2400 support | ||
32 | * | ||
33 | * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART | ||
34 | */ | ||
35 | |||
36 | /* Note on 2440 fclk clock source handling | ||
37 | * | ||
38 | * Whilst it is possible to use the fclk as clock source, the method | ||
39 | * of properly switching too/from this is currently un-implemented, so | ||
40 | * whichever way is configured at startup is the one that will be used. | ||
41 | */ | ||
42 | |||
43 | /* Hote on 2410 error handling | ||
44 | * | ||
45 | * The s3c2410 manual has a love/hate affair with the contents of the | ||
46 | * UERSTAT register in the UART blocks, and keeps marking some of the | ||
47 | * error bits as reserved. Having checked with the s3c2410x01, | ||
48 | * it copes with BREAKs properly, so I am happy to ignore the RESERVED | ||
49 | * feature from the latter versions of the manual. | ||
50 | * | ||
51 | * If it becomes aparrent that latter versions of the 2410 remove these | ||
52 | * bits, then action will have to be taken to differentiate the versions | ||
53 | * and change the policy on BREAK | ||
54 | * | ||
55 | * BJD, 04-Nov-2004 | ||
56 | */ | 11 | */ |
57 | 12 | ||
58 | |||
59 | #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | ||
60 | #define SUPPORT_SYSRQ | ||
61 | #endif | ||
62 | |||
63 | #include <linux/module.h> | 13 | #include <linux/module.h> |
64 | #include <linux/ioport.h> | 14 | #include <linux/ioport.h> |
15 | #include <linux/io.h> | ||
65 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
66 | #include <linux/init.h> | 17 | #include <linux/init.h> |
67 | #include <linux/sysrq.h> | ||
68 | #include <linux/console.h> | ||
69 | #include <linux/tty.h> | ||
70 | #include <linux/tty_flip.h> | ||
71 | #include <linux/serial_core.h> | 18 | #include <linux/serial_core.h> |
72 | #include <linux/serial.h> | 19 | #include <linux/serial.h> |
73 | #include <linux/delay.h> | ||
74 | #include <linux/clk.h> | ||
75 | 20 | ||
76 | #include <asm/io.h> | ||
77 | #include <asm/irq.h> | 21 | #include <asm/irq.h> |
78 | |||
79 | #include <asm/hardware.h> | 22 | #include <asm/hardware.h> |
80 | 23 | ||
81 | #include <asm/plat-s3c/regs-serial.h> | 24 | #include <asm/plat-s3c/regs-serial.h> |
82 | #include <asm/arch/regs-gpio.h> | 25 | #include <asm/arch/regs-gpio.h> |
83 | 26 | ||
84 | /* structures */ | 27 | #include "samsung.h" |
85 | |||
86 | struct s3c24xx_uart_info { | ||
87 | char *name; | ||
88 | unsigned int type; | ||
89 | unsigned int fifosize; | ||
90 | unsigned long rx_fifomask; | ||
91 | unsigned long rx_fifoshift; | ||
92 | unsigned long rx_fifofull; | ||
93 | unsigned long tx_fifomask; | ||
94 | unsigned long tx_fifoshift; | ||
95 | unsigned long tx_fifofull; | ||
96 | |||
97 | /* clock source control */ | ||
98 | |||
99 | int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk); | ||
100 | int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk); | ||
101 | |||
102 | /* uart controls */ | ||
103 | int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *); | ||
104 | }; | ||
105 | |||
106 | struct s3c24xx_uart_port { | ||
107 | unsigned char rx_claimed; | ||
108 | unsigned char tx_claimed; | ||
109 | |||
110 | struct s3c24xx_uart_info *info; | ||
111 | struct s3c24xx_uart_clksrc *clksrc; | ||
112 | struct clk *clk; | ||
113 | struct clk *baudclk; | ||
114 | struct uart_port port; | ||
115 | }; | ||
116 | |||
117 | |||
118 | /* configuration defines */ | ||
119 | |||
120 | #if 0 | ||
121 | #if 1 | ||
122 | /* send debug to the low-level output routines */ | ||
123 | |||
124 | extern void printascii(const char *); | ||
125 | |||
126 | static void | ||
127 | s3c24xx_serial_dbg(const char *fmt, ...) | ||
128 | { | ||
129 | va_list va; | ||
130 | char buff[256]; | ||
131 | |||
132 | va_start(va, fmt); | ||
133 | vsprintf(buff, fmt, va); | ||
134 | va_end(va); | ||
135 | |||
136 | printascii(buff); | ||
137 | } | ||
138 | |||
139 | #define dbg(x...) s3c24xx_serial_dbg(x) | ||
140 | |||
141 | #else | ||
142 | #define dbg(x...) printk(KERN_DEBUG "s3c24xx: "); | ||
143 | #endif | ||
144 | #else /* no debug */ | ||
145 | #define dbg(x...) do {} while(0) | ||
146 | #endif | ||
147 | |||
148 | /* UART name and device definitions */ | ||
149 | |||
150 | #define S3C24XX_SERIAL_NAME "ttySAC" | ||
151 | #define S3C24XX_SERIAL_MAJOR 204 | ||
152 | #define S3C24XX_SERIAL_MINOR 64 | ||
153 | |||
154 | |||
155 | /* conversion functions */ | ||
156 | |||
157 | #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev) | ||
158 | #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data) | ||
159 | |||
160 | /* we can support 3 uarts, but not always use them */ | ||
161 | |||
162 | #ifdef CONFIG_CPU_S3C2400 | ||
163 | #define NR_PORTS (2) | ||
164 | #else | ||
165 | #define NR_PORTS (3) | ||
166 | #endif | ||
167 | |||
168 | /* port irq numbers */ | ||
169 | |||
170 | #define TX_IRQ(port) ((port)->irq + 1) | ||
171 | #define RX_IRQ(port) ((port)->irq) | ||
172 | |||
173 | /* register access controls */ | ||
174 | |||
175 | #define portaddr(port, reg) ((port)->membase + (reg)) | ||
176 | |||
177 | #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg))) | ||
178 | #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg))) | ||
179 | |||
180 | #define wr_regb(port, reg, val) \ | ||
181 | do { __raw_writeb(val, portaddr(port, reg)); } while(0) | ||
182 | |||
183 | #define wr_regl(port, reg, val) \ | ||
184 | do { __raw_writel(val, portaddr(port, reg)); } while(0) | ||
185 | |||
186 | /* macros to change one thing to another */ | ||
187 | |||
188 | #define tx_enabled(port) ((port)->unused[0]) | ||
189 | #define rx_enabled(port) ((port)->unused[1]) | ||
190 | |||
191 | /* flag to ignore all characters comming in */ | ||
192 | #define RXSTAT_DUMMY_READ (0x10000000) | ||
193 | |||
194 | static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) | ||
195 | { | ||
196 | return container_of(port, struct s3c24xx_uart_port, port); | ||
197 | } | ||
198 | |||
199 | /* translate a port to the device name */ | ||
200 | |||
201 | static inline const char *s3c24xx_serial_portname(struct uart_port *port) | ||
202 | { | ||
203 | return to_platform_device(port->dev)->name; | ||
204 | } | ||
205 | |||
206 | static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) | ||
207 | { | ||
208 | return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE); | ||
209 | } | ||
210 | |||
211 | static void s3c24xx_serial_rx_enable(struct uart_port *port) | ||
212 | { | ||
213 | unsigned long flags; | ||
214 | unsigned int ucon, ufcon; | ||
215 | int count = 10000; | ||
216 | |||
217 | spin_lock_irqsave(&port->lock, flags); | ||
218 | |||
219 | while (--count && !s3c24xx_serial_txempty_nofifo(port)) | ||
220 | udelay(100); | ||
221 | |||
222 | ufcon = rd_regl(port, S3C2410_UFCON); | ||
223 | ufcon |= S3C2410_UFCON_RESETRX; | ||
224 | wr_regl(port, S3C2410_UFCON, ufcon); | ||
225 | |||
226 | ucon = rd_regl(port, S3C2410_UCON); | ||
227 | ucon |= S3C2410_UCON_RXIRQMODE; | ||
228 | wr_regl(port, S3C2410_UCON, ucon); | ||
229 | |||
230 | rx_enabled(port) = 1; | ||
231 | spin_unlock_irqrestore(&port->lock, flags); | ||
232 | } | ||
233 | |||
234 | static void s3c24xx_serial_rx_disable(struct uart_port *port) | ||
235 | { | ||
236 | unsigned long flags; | ||
237 | unsigned int ucon; | ||
238 | |||
239 | spin_lock_irqsave(&port->lock, flags); | ||
240 | |||
241 | ucon = rd_regl(port, S3C2410_UCON); | ||
242 | ucon &= ~S3C2410_UCON_RXIRQMODE; | ||
243 | wr_regl(port, S3C2410_UCON, ucon); | ||
244 | |||
245 | rx_enabled(port) = 0; | ||
246 | spin_unlock_irqrestore(&port->lock, flags); | ||
247 | } | ||
248 | |||
249 | static void s3c24xx_serial_stop_tx(struct uart_port *port) | ||
250 | { | ||
251 | if (tx_enabled(port)) { | ||
252 | disable_irq(TX_IRQ(port)); | ||
253 | tx_enabled(port) = 0; | ||
254 | if (port->flags & UPF_CONS_FLOW) | ||
255 | s3c24xx_serial_rx_enable(port); | ||
256 | } | ||
257 | } | ||
258 | |||
259 | static void s3c24xx_serial_start_tx(struct uart_port *port) | ||
260 | { | ||
261 | if (!tx_enabled(port)) { | ||
262 | if (port->flags & UPF_CONS_FLOW) | ||
263 | s3c24xx_serial_rx_disable(port); | ||
264 | |||
265 | enable_irq(TX_IRQ(port)); | ||
266 | tx_enabled(port) = 1; | ||
267 | } | ||
268 | } | ||
269 | |||
270 | |||
271 | static void s3c24xx_serial_stop_rx(struct uart_port *port) | ||
272 | { | ||
273 | if (rx_enabled(port)) { | ||
274 | dbg("s3c24xx_serial_stop_rx: port=%p\n", port); | ||
275 | disable_irq(RX_IRQ(port)); | ||
276 | rx_enabled(port) = 0; | ||
277 | } | ||
278 | } | ||
279 | |||
280 | static void s3c24xx_serial_enable_ms(struct uart_port *port) | ||
281 | { | ||
282 | } | ||
283 | |||
284 | static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port) | ||
285 | { | ||
286 | return to_ourport(port)->info; | ||
287 | } | ||
288 | |||
289 | static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port) | ||
290 | { | ||
291 | if (port->dev == NULL) | ||
292 | return NULL; | ||
293 | |||
294 | return (struct s3c2410_uartcfg *)port->dev->platform_data; | ||
295 | } | ||
296 | |||
297 | static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport, | ||
298 | unsigned long ufstat) | ||
299 | { | ||
300 | struct s3c24xx_uart_info *info = ourport->info; | ||
301 | |||
302 | if (ufstat & info->rx_fifofull) | ||
303 | return info->fifosize; | ||
304 | |||
305 | return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; | ||
306 | } | ||
307 | |||
308 | |||
309 | /* ? - where has parity gone?? */ | ||
310 | #define S3C2410_UERSTAT_PARITY (0x1000) | ||
311 | |||
312 | static irqreturn_t | ||
313 | s3c24xx_serial_rx_chars(int irq, void *dev_id) | ||
314 | { | ||
315 | struct s3c24xx_uart_port *ourport = dev_id; | ||
316 | struct uart_port *port = &ourport->port; | ||
317 | struct tty_struct *tty = port->info->tty; | ||
318 | unsigned int ufcon, ch, flag, ufstat, uerstat; | ||
319 | int max_count = 64; | ||
320 | |||
321 | while (max_count-- > 0) { | ||
322 | ufcon = rd_regl(port, S3C2410_UFCON); | ||
323 | ufstat = rd_regl(port, S3C2410_UFSTAT); | ||
324 | |||
325 | if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) | ||
326 | break; | ||
327 | |||
328 | uerstat = rd_regl(port, S3C2410_UERSTAT); | ||
329 | ch = rd_regb(port, S3C2410_URXH); | ||
330 | |||
331 | if (port->flags & UPF_CONS_FLOW) { | ||
332 | int txe = s3c24xx_serial_txempty_nofifo(port); | ||
333 | |||
334 | if (rx_enabled(port)) { | ||
335 | if (!txe) { | ||
336 | rx_enabled(port) = 0; | ||
337 | continue; | ||
338 | } | ||
339 | } else { | ||
340 | if (txe) { | ||
341 | ufcon |= S3C2410_UFCON_RESETRX; | ||
342 | wr_regl(port, S3C2410_UFCON, ufcon); | ||
343 | rx_enabled(port) = 1; | ||
344 | goto out; | ||
345 | } | ||
346 | continue; | ||
347 | } | ||
348 | } | ||
349 | |||
350 | /* insert the character into the buffer */ | ||
351 | |||
352 | flag = TTY_NORMAL; | ||
353 | port->icount.rx++; | ||
354 | |||
355 | if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { | ||
356 | dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n", | ||
357 | ch, uerstat); | ||
358 | |||
359 | /* check for break */ | ||
360 | if (uerstat & S3C2410_UERSTAT_BREAK) { | ||
361 | dbg("break!\n"); | ||
362 | port->icount.brk++; | ||
363 | if (uart_handle_break(port)) | ||
364 | goto ignore_char; | ||
365 | } | ||
366 | |||
367 | if (uerstat & S3C2410_UERSTAT_FRAME) | ||
368 | port->icount.frame++; | ||
369 | if (uerstat & S3C2410_UERSTAT_OVERRUN) | ||
370 | port->icount.overrun++; | ||
371 | |||
372 | uerstat &= port->read_status_mask; | ||
373 | |||
374 | if (uerstat & S3C2410_UERSTAT_BREAK) | ||
375 | flag = TTY_BREAK; | ||
376 | else if (uerstat & S3C2410_UERSTAT_PARITY) | ||
377 | flag = TTY_PARITY; | ||
378 | else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN)) | ||
379 | flag = TTY_FRAME; | ||
380 | } | ||
381 | |||
382 | if (uart_handle_sysrq_char(port, ch)) | ||
383 | goto ignore_char; | ||
384 | |||
385 | uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag); | ||
386 | |||
387 | ignore_char: | ||
388 | continue; | ||
389 | } | ||
390 | tty_flip_buffer_push(tty); | ||
391 | |||
392 | out: | ||
393 | return IRQ_HANDLED; | ||
394 | } | ||
395 | |||
396 | static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) | ||
397 | { | ||
398 | struct s3c24xx_uart_port *ourport = id; | ||
399 | struct uart_port *port = &ourport->port; | ||
400 | struct circ_buf *xmit = &port->info->xmit; | ||
401 | int count = 256; | ||
402 | |||
403 | if (port->x_char) { | ||
404 | wr_regb(port, S3C2410_UTXH, port->x_char); | ||
405 | port->icount.tx++; | ||
406 | port->x_char = 0; | ||
407 | goto out; | ||
408 | } | ||
409 | |||
410 | /* if there isnt anything more to transmit, or the uart is now | ||
411 | * stopped, disable the uart and exit | ||
412 | */ | ||
413 | |||
414 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | ||
415 | s3c24xx_serial_stop_tx(port); | ||
416 | goto out; | ||
417 | } | ||
418 | |||
419 | /* try and drain the buffer... */ | ||
420 | |||
421 | while (!uart_circ_empty(xmit) && count-- > 0) { | ||
422 | if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) | ||
423 | break; | ||
424 | |||
425 | wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); | ||
426 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | ||
427 | port->icount.tx++; | ||
428 | } | ||
429 | |||
430 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | ||
431 | uart_write_wakeup(port); | ||
432 | |||
433 | if (uart_circ_empty(xmit)) | ||
434 | s3c24xx_serial_stop_tx(port); | ||
435 | |||
436 | out: | ||
437 | return IRQ_HANDLED; | ||
438 | } | ||
439 | |||
440 | static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) | ||
441 | { | ||
442 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
443 | unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); | ||
444 | unsigned long ufcon = rd_regl(port, S3C2410_UFCON); | ||
445 | |||
446 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | ||
447 | if ((ufstat & info->tx_fifomask) != 0 || | ||
448 | (ufstat & info->tx_fifofull)) | ||
449 | return 0; | ||
450 | |||
451 | return 1; | ||
452 | } | ||
453 | |||
454 | return s3c24xx_serial_txempty_nofifo(port); | ||
455 | } | ||
456 | |||
457 | /* no modem control lines */ | ||
458 | static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) | ||
459 | { | ||
460 | unsigned int umstat = rd_regb(port,S3C2410_UMSTAT); | ||
461 | |||
462 | if (umstat & S3C2410_UMSTAT_CTS) | ||
463 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; | ||
464 | else | ||
465 | return TIOCM_CAR | TIOCM_DSR; | ||
466 | } | ||
467 | |||
468 | static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | ||
469 | { | ||
470 | /* todo - possibly remove AFC and do manual CTS */ | ||
471 | } | ||
472 | |||
473 | static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) | ||
474 | { | ||
475 | unsigned long flags; | ||
476 | unsigned int ucon; | ||
477 | |||
478 | spin_lock_irqsave(&port->lock, flags); | ||
479 | |||
480 | ucon = rd_regl(port, S3C2410_UCON); | ||
481 | |||
482 | if (break_state) | ||
483 | ucon |= S3C2410_UCON_SBREAK; | ||
484 | else | ||
485 | ucon &= ~S3C2410_UCON_SBREAK; | ||
486 | |||
487 | wr_regl(port, S3C2410_UCON, ucon); | ||
488 | |||
489 | spin_unlock_irqrestore(&port->lock, flags); | ||
490 | } | ||
491 | |||
492 | static void s3c24xx_serial_shutdown(struct uart_port *port) | ||
493 | { | ||
494 | struct s3c24xx_uart_port *ourport = to_ourport(port); | ||
495 | |||
496 | if (ourport->tx_claimed) { | ||
497 | free_irq(TX_IRQ(port), ourport); | ||
498 | tx_enabled(port) = 0; | ||
499 | ourport->tx_claimed = 0; | ||
500 | } | ||
501 | |||
502 | if (ourport->rx_claimed) { | ||
503 | free_irq(RX_IRQ(port), ourport); | ||
504 | ourport->rx_claimed = 0; | ||
505 | rx_enabled(port) = 0; | ||
506 | } | ||
507 | } | ||
508 | |||
509 | |||
510 | static int s3c24xx_serial_startup(struct uart_port *port) | ||
511 | { | ||
512 | struct s3c24xx_uart_port *ourport = to_ourport(port); | ||
513 | int ret; | ||
514 | |||
515 | dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n", | ||
516 | port->mapbase, port->membase); | ||
517 | |||
518 | rx_enabled(port) = 1; | ||
519 | |||
520 | ret = request_irq(RX_IRQ(port), | ||
521 | s3c24xx_serial_rx_chars, 0, | ||
522 | s3c24xx_serial_portname(port), ourport); | ||
523 | |||
524 | if (ret != 0) { | ||
525 | printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port)); | ||
526 | return ret; | ||
527 | } | ||
528 | |||
529 | ourport->rx_claimed = 1; | ||
530 | |||
531 | dbg("requesting tx irq...\n"); | ||
532 | |||
533 | tx_enabled(port) = 1; | ||
534 | |||
535 | ret = request_irq(TX_IRQ(port), | ||
536 | s3c24xx_serial_tx_chars, 0, | ||
537 | s3c24xx_serial_portname(port), ourport); | ||
538 | |||
539 | if (ret) { | ||
540 | printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port)); | ||
541 | goto err; | ||
542 | } | ||
543 | |||
544 | ourport->tx_claimed = 1; | ||
545 | |||
546 | dbg("s3c24xx_serial_startup ok\n"); | ||
547 | |||
548 | /* the port reset code should have done the correct | ||
549 | * register setup for the port controls */ | ||
550 | |||
551 | return ret; | ||
552 | |||
553 | err: | ||
554 | s3c24xx_serial_shutdown(port); | ||
555 | return ret; | ||
556 | } | ||
557 | |||
558 | /* power power management control */ | ||
559 | |||
560 | static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, | ||
561 | unsigned int old) | ||
562 | { | ||
563 | struct s3c24xx_uart_port *ourport = to_ourport(port); | ||
564 | |||
565 | switch (level) { | ||
566 | case 3: | ||
567 | if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) | ||
568 | clk_disable(ourport->baudclk); | ||
569 | |||
570 | clk_disable(ourport->clk); | ||
571 | break; | ||
572 | |||
573 | case 0: | ||
574 | clk_enable(ourport->clk); | ||
575 | |||
576 | if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) | ||
577 | clk_enable(ourport->baudclk); | ||
578 | |||
579 | break; | ||
580 | default: | ||
581 | printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level); | ||
582 | } | ||
583 | } | ||
584 | |||
585 | /* baud rate calculation | ||
586 | * | ||
587 | * The UARTs on the S3C2410/S3C2440 can take their clocks from a number | ||
588 | * of different sources, including the peripheral clock ("pclk") and an | ||
589 | * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") | ||
590 | * with a programmable extra divisor. | ||
591 | * | ||
592 | * The following code goes through the clock sources, and calculates the | ||
593 | * baud clocks (and the resultant actual baud rates) and then tries to | ||
594 | * pick the closest one and select that. | ||
595 | * | ||
596 | */ | ||
597 | |||
598 | |||
599 | #define MAX_CLKS (8) | ||
600 | |||
601 | static struct s3c24xx_uart_clksrc tmp_clksrc = { | ||
602 | .name = "pclk", | ||
603 | .min_baud = 0, | ||
604 | .max_baud = 0, | ||
605 | .divisor = 1, | ||
606 | }; | ||
607 | |||
608 | static inline int | ||
609 | s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c) | ||
610 | { | ||
611 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
612 | |||
613 | return (info->get_clksrc)(port, c); | ||
614 | } | ||
615 | |||
616 | static inline int | ||
617 | s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c) | ||
618 | { | ||
619 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
620 | |||
621 | return (info->set_clksrc)(port, c); | ||
622 | } | ||
623 | |||
624 | struct baud_calc { | ||
625 | struct s3c24xx_uart_clksrc *clksrc; | ||
626 | unsigned int calc; | ||
627 | unsigned int quot; | ||
628 | struct clk *src; | ||
629 | }; | ||
630 | |||
631 | static int s3c24xx_serial_calcbaud(struct baud_calc *calc, | ||
632 | struct uart_port *port, | ||
633 | struct s3c24xx_uart_clksrc *clksrc, | ||
634 | unsigned int baud) | ||
635 | { | ||
636 | unsigned long rate; | ||
637 | |||
638 | calc->src = clk_get(port->dev, clksrc->name); | ||
639 | if (calc->src == NULL || IS_ERR(calc->src)) | ||
640 | return 0; | ||
641 | |||
642 | rate = clk_get_rate(calc->src); | ||
643 | rate /= clksrc->divisor; | ||
644 | |||
645 | calc->clksrc = clksrc; | ||
646 | calc->quot = (rate + (8 * baud)) / (16 * baud); | ||
647 | calc->calc = (rate / (calc->quot * 16)); | ||
648 | |||
649 | calc->quot--; | ||
650 | return 1; | ||
651 | } | ||
652 | |||
653 | static unsigned int s3c24xx_serial_getclk(struct uart_port *port, | ||
654 | struct s3c24xx_uart_clksrc **clksrc, | ||
655 | struct clk **clk, | ||
656 | unsigned int baud) | ||
657 | { | ||
658 | struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); | ||
659 | struct s3c24xx_uart_clksrc *clkp; | ||
660 | struct baud_calc res[MAX_CLKS]; | ||
661 | struct baud_calc *resptr, *best, *sptr; | ||
662 | int i; | ||
663 | |||
664 | clkp = cfg->clocks; | ||
665 | best = NULL; | ||
666 | |||
667 | if (cfg->clocks_size < 2) { | ||
668 | if (cfg->clocks_size == 0) | ||
669 | clkp = &tmp_clksrc; | ||
670 | |||
671 | /* check to see if we're sourcing fclk, and if so we're | ||
672 | * going to have to update the clock source | ||
673 | */ | ||
674 | |||
675 | if (strcmp(clkp->name, "fclk") == 0) { | ||
676 | struct s3c24xx_uart_clksrc src; | ||
677 | |||
678 | s3c24xx_serial_getsource(port, &src); | ||
679 | |||
680 | /* check that the port already using fclk, and if | ||
681 | * not, then re-select fclk | ||
682 | */ | ||
683 | |||
684 | if (strcmp(src.name, clkp->name) == 0) { | ||
685 | s3c24xx_serial_setsource(port, clkp); | ||
686 | s3c24xx_serial_getsource(port, &src); | ||
687 | } | ||
688 | |||
689 | clkp->divisor = src.divisor; | ||
690 | } | ||
691 | |||
692 | s3c24xx_serial_calcbaud(res, port, clkp, baud); | ||
693 | best = res; | ||
694 | resptr = best + 1; | ||
695 | } else { | ||
696 | resptr = res; | ||
697 | |||
698 | for (i = 0; i < cfg->clocks_size; i++, clkp++) { | ||
699 | if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud)) | ||
700 | resptr++; | ||
701 | } | ||
702 | } | ||
703 | |||
704 | /* ok, we now need to select the best clock we found */ | ||
705 | |||
706 | if (!best) { | ||
707 | unsigned int deviation = (1<<30)|((1<<30)-1); | ||
708 | int calc_deviation; | ||
709 | |||
710 | for (sptr = res; sptr < resptr; sptr++) { | ||
711 | printk(KERN_DEBUG | ||
712 | "found clk %p (%s) quot %d, calc %d\n", | ||
713 | sptr->clksrc, sptr->clksrc->name, | ||
714 | sptr->quot, sptr->calc); | ||
715 | |||
716 | calc_deviation = baud - sptr->calc; | ||
717 | if (calc_deviation < 0) | ||
718 | calc_deviation = -calc_deviation; | ||
719 | |||
720 | if (calc_deviation < deviation) { | ||
721 | best = sptr; | ||
722 | deviation = calc_deviation; | ||
723 | } | ||
724 | } | ||
725 | |||
726 | printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation); | ||
727 | } | ||
728 | |||
729 | printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n", | ||
730 | best->clksrc, best->clksrc->name, best->quot, best->calc); | ||
731 | |||
732 | /* store results to pass back */ | ||
733 | |||
734 | *clksrc = best->clksrc; | ||
735 | *clk = best->src; | ||
736 | |||
737 | return best->quot; | ||
738 | } | ||
739 | |||
740 | static void s3c24xx_serial_set_termios(struct uart_port *port, | ||
741 | struct ktermios *termios, | ||
742 | struct ktermios *old) | ||
743 | { | ||
744 | struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); | ||
745 | struct s3c24xx_uart_port *ourport = to_ourport(port); | ||
746 | struct s3c24xx_uart_clksrc *clksrc = NULL; | ||
747 | struct clk *clk = NULL; | ||
748 | unsigned long flags; | ||
749 | unsigned int baud, quot; | ||
750 | unsigned int ulcon; | ||
751 | unsigned int umcon; | ||
752 | |||
753 | /* | ||
754 | * We don't support modem control lines. | ||
755 | */ | ||
756 | termios->c_cflag &= ~(HUPCL | CMSPAR); | ||
757 | termios->c_cflag |= CLOCAL; | ||
758 | |||
759 | /* | ||
760 | * Ask the core to calculate the divisor for us. | ||
761 | */ | ||
762 | |||
763 | baud = uart_get_baud_rate(port, termios, old, 0, 115200*8); | ||
764 | |||
765 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) | ||
766 | quot = port->custom_divisor; | ||
767 | else | ||
768 | quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud); | ||
769 | |||
770 | /* check to see if we need to change clock source */ | ||
771 | |||
772 | if (ourport->clksrc != clksrc || ourport->baudclk != clk) { | ||
773 | s3c24xx_serial_setsource(port, clksrc); | ||
774 | |||
775 | if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) { | ||
776 | clk_disable(ourport->baudclk); | ||
777 | ourport->baudclk = NULL; | ||
778 | } | ||
779 | |||
780 | clk_enable(clk); | ||
781 | |||
782 | ourport->clksrc = clksrc; | ||
783 | ourport->baudclk = clk; | ||
784 | } | ||
785 | |||
786 | switch (termios->c_cflag & CSIZE) { | ||
787 | case CS5: | ||
788 | dbg("config: 5bits/char\n"); | ||
789 | ulcon = S3C2410_LCON_CS5; | ||
790 | break; | ||
791 | case CS6: | ||
792 | dbg("config: 6bits/char\n"); | ||
793 | ulcon = S3C2410_LCON_CS6; | ||
794 | break; | ||
795 | case CS7: | ||
796 | dbg("config: 7bits/char\n"); | ||
797 | ulcon = S3C2410_LCON_CS7; | ||
798 | break; | ||
799 | case CS8: | ||
800 | default: | ||
801 | dbg("config: 8bits/char\n"); | ||
802 | ulcon = S3C2410_LCON_CS8; | ||
803 | break; | ||
804 | } | ||
805 | |||
806 | /* preserve original lcon IR settings */ | ||
807 | ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); | ||
808 | |||
809 | if (termios->c_cflag & CSTOPB) | ||
810 | ulcon |= S3C2410_LCON_STOPB; | ||
811 | |||
812 | umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0; | ||
813 | |||
814 | if (termios->c_cflag & PARENB) { | ||
815 | if (termios->c_cflag & PARODD) | ||
816 | ulcon |= S3C2410_LCON_PODD; | ||
817 | else | ||
818 | ulcon |= S3C2410_LCON_PEVEN; | ||
819 | } else { | ||
820 | ulcon |= S3C2410_LCON_PNONE; | ||
821 | } | ||
822 | |||
823 | spin_lock_irqsave(&port->lock, flags); | ||
824 | |||
825 | dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot); | ||
826 | |||
827 | wr_regl(port, S3C2410_ULCON, ulcon); | ||
828 | wr_regl(port, S3C2410_UBRDIV, quot); | ||
829 | wr_regl(port, S3C2410_UMCON, umcon); | ||
830 | |||
831 | dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", | ||
832 | rd_regl(port, S3C2410_ULCON), | ||
833 | rd_regl(port, S3C2410_UCON), | ||
834 | rd_regl(port, S3C2410_UFCON)); | ||
835 | |||
836 | /* | ||
837 | * Update the per-port timeout. | ||
838 | */ | ||
839 | uart_update_timeout(port, termios->c_cflag, baud); | ||
840 | |||
841 | /* | ||
842 | * Which character status flags are we interested in? | ||
843 | */ | ||
844 | port->read_status_mask = S3C2410_UERSTAT_OVERRUN; | ||
845 | if (termios->c_iflag & INPCK) | ||
846 | port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY; | ||
847 | |||
848 | /* | ||
849 | * Which character status flags should we ignore? | ||
850 | */ | ||
851 | port->ignore_status_mask = 0; | ||
852 | if (termios->c_iflag & IGNPAR) | ||
853 | port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; | ||
854 | if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) | ||
855 | port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; | ||
856 | |||
857 | /* | ||
858 | * Ignore all characters if CREAD is not set. | ||
859 | */ | ||
860 | if ((termios->c_cflag & CREAD) == 0) | ||
861 | port->ignore_status_mask |= RXSTAT_DUMMY_READ; | ||
862 | |||
863 | spin_unlock_irqrestore(&port->lock, flags); | ||
864 | } | ||
865 | |||
866 | static const char *s3c24xx_serial_type(struct uart_port *port) | ||
867 | { | ||
868 | switch (port->type) { | ||
869 | case PORT_S3C2410: | ||
870 | return "S3C2410"; | ||
871 | case PORT_S3C2440: | ||
872 | return "S3C2440"; | ||
873 | case PORT_S3C2412: | ||
874 | return "S3C2412"; | ||
875 | default: | ||
876 | return NULL; | ||
877 | } | ||
878 | } | ||
879 | |||
880 | #define MAP_SIZE (0x100) | ||
881 | |||
882 | static void s3c24xx_serial_release_port(struct uart_port *port) | ||
883 | { | ||
884 | release_mem_region(port->mapbase, MAP_SIZE); | ||
885 | } | ||
886 | |||
887 | static int s3c24xx_serial_request_port(struct uart_port *port) | ||
888 | { | ||
889 | const char *name = s3c24xx_serial_portname(port); | ||
890 | return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY; | ||
891 | } | ||
892 | |||
893 | static void s3c24xx_serial_config_port(struct uart_port *port, int flags) | ||
894 | { | ||
895 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
896 | |||
897 | if (flags & UART_CONFIG_TYPE && | ||
898 | s3c24xx_serial_request_port(port) == 0) | ||
899 | port->type = info->type; | ||
900 | } | ||
901 | |||
902 | /* | ||
903 | * verify the new serial_struct (for TIOCSSERIAL). | ||
904 | */ | ||
905 | static int | ||
906 | s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | ||
907 | { | ||
908 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
909 | |||
910 | if (ser->type != PORT_UNKNOWN && ser->type != info->type) | ||
911 | return -EINVAL; | ||
912 | |||
913 | return 0; | ||
914 | } | ||
915 | |||
916 | |||
917 | #ifdef CONFIG_SERIAL_S3C2410_CONSOLE | ||
918 | |||
919 | static struct console s3c24xx_serial_console; | ||
920 | |||
921 | #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console | ||
922 | #else | ||
923 | #define S3C24XX_SERIAL_CONSOLE NULL | ||
924 | #endif | ||
925 | |||
926 | static struct uart_ops s3c24xx_serial_ops = { | ||
927 | .pm = s3c24xx_serial_pm, | ||
928 | .tx_empty = s3c24xx_serial_tx_empty, | ||
929 | .get_mctrl = s3c24xx_serial_get_mctrl, | ||
930 | .set_mctrl = s3c24xx_serial_set_mctrl, | ||
931 | .stop_tx = s3c24xx_serial_stop_tx, | ||
932 | .start_tx = s3c24xx_serial_start_tx, | ||
933 | .stop_rx = s3c24xx_serial_stop_rx, | ||
934 | .enable_ms = s3c24xx_serial_enable_ms, | ||
935 | .break_ctl = s3c24xx_serial_break_ctl, | ||
936 | .startup = s3c24xx_serial_startup, | ||
937 | .shutdown = s3c24xx_serial_shutdown, | ||
938 | .set_termios = s3c24xx_serial_set_termios, | ||
939 | .type = s3c24xx_serial_type, | ||
940 | .release_port = s3c24xx_serial_release_port, | ||
941 | .request_port = s3c24xx_serial_request_port, | ||
942 | .config_port = s3c24xx_serial_config_port, | ||
943 | .verify_port = s3c24xx_serial_verify_port, | ||
944 | }; | ||
945 | |||
946 | |||
947 | static struct uart_driver s3c24xx_uart_drv = { | ||
948 | .owner = THIS_MODULE, | ||
949 | .dev_name = "s3c2410_serial", | ||
950 | .nr = 3, | ||
951 | .cons = S3C24XX_SERIAL_CONSOLE, | ||
952 | .driver_name = S3C24XX_SERIAL_NAME, | ||
953 | .major = S3C24XX_SERIAL_MAJOR, | ||
954 | .minor = S3C24XX_SERIAL_MINOR, | ||
955 | }; | ||
956 | |||
957 | static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = { | ||
958 | [0] = { | ||
959 | .port = { | ||
960 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock), | ||
961 | .iotype = UPIO_MEM, | ||
962 | .irq = IRQ_S3CUART_RX0, | ||
963 | .uartclk = 0, | ||
964 | .fifosize = 16, | ||
965 | .ops = &s3c24xx_serial_ops, | ||
966 | .flags = UPF_BOOT_AUTOCONF, | ||
967 | .line = 0, | ||
968 | } | ||
969 | }, | ||
970 | [1] = { | ||
971 | .port = { | ||
972 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock), | ||
973 | .iotype = UPIO_MEM, | ||
974 | .irq = IRQ_S3CUART_RX1, | ||
975 | .uartclk = 0, | ||
976 | .fifosize = 16, | ||
977 | .ops = &s3c24xx_serial_ops, | ||
978 | .flags = UPF_BOOT_AUTOCONF, | ||
979 | .line = 1, | ||
980 | } | ||
981 | }, | ||
982 | #if NR_PORTS > 2 | ||
983 | |||
984 | [2] = { | ||
985 | .port = { | ||
986 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock), | ||
987 | .iotype = UPIO_MEM, | ||
988 | .irq = IRQ_S3CUART_RX2, | ||
989 | .uartclk = 0, | ||
990 | .fifosize = 16, | ||
991 | .ops = &s3c24xx_serial_ops, | ||
992 | .flags = UPF_BOOT_AUTOCONF, | ||
993 | .line = 2, | ||
994 | } | ||
995 | } | ||
996 | #endif | ||
997 | }; | ||
998 | |||
999 | /* s3c24xx_serial_resetport | ||
1000 | * | ||
1001 | * wrapper to call the specific reset for this port (reset the fifos | ||
1002 | * and the settings) | ||
1003 | */ | ||
1004 | |||
1005 | static inline int s3c24xx_serial_resetport(struct uart_port * port, | ||
1006 | struct s3c2410_uartcfg *cfg) | ||
1007 | { | ||
1008 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
1009 | |||
1010 | return (info->reset_port)(port, cfg); | ||
1011 | } | ||
1012 | |||
1013 | /* s3c24xx_serial_init_port | ||
1014 | * | ||
1015 | * initialise a single serial port from the platform device given | ||
1016 | */ | ||
1017 | |||
1018 | static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, | ||
1019 | struct s3c24xx_uart_info *info, | ||
1020 | struct platform_device *platdev) | ||
1021 | { | ||
1022 | struct uart_port *port = &ourport->port; | ||
1023 | struct s3c2410_uartcfg *cfg; | ||
1024 | struct resource *res; | ||
1025 | int ret; | ||
1026 | |||
1027 | dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev); | ||
1028 | |||
1029 | if (platdev == NULL) | ||
1030 | return -ENODEV; | ||
1031 | |||
1032 | cfg = s3c24xx_dev_to_cfg(&platdev->dev); | ||
1033 | |||
1034 | if (port->mapbase != 0) | ||
1035 | return 0; | ||
1036 | |||
1037 | if (cfg->hwport > 3) | ||
1038 | return -EINVAL; | ||
1039 | |||
1040 | /* setup info for port */ | ||
1041 | port->dev = &platdev->dev; | ||
1042 | ourport->info = info; | ||
1043 | |||
1044 | /* copy the info in from provided structure */ | ||
1045 | ourport->port.fifosize = info->fifosize; | ||
1046 | |||
1047 | dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport); | ||
1048 | |||
1049 | port->uartclk = 1; | ||
1050 | |||
1051 | if (cfg->uart_flags & UPF_CONS_FLOW) { | ||
1052 | dbg("s3c24xx_serial_init_port: enabling flow control\n"); | ||
1053 | port->flags |= UPF_CONS_FLOW; | ||
1054 | } | ||
1055 | |||
1056 | /* sort our the physical and virtual addresses for each UART */ | ||
1057 | |||
1058 | res = platform_get_resource(platdev, IORESOURCE_MEM, 0); | ||
1059 | if (res == NULL) { | ||
1060 | printk(KERN_ERR "failed to find memory resource for uart\n"); | ||
1061 | return -EINVAL; | ||
1062 | } | ||
1063 | |||
1064 | dbg("resource %p (%lx..%lx)\n", res, res->start, res->end); | ||
1065 | |||
1066 | port->mapbase = res->start; | ||
1067 | port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART); | ||
1068 | ret = platform_get_irq(platdev, 0); | ||
1069 | if (ret < 0) | ||
1070 | port->irq = 0; | ||
1071 | else | ||
1072 | port->irq = ret; | ||
1073 | |||
1074 | ourport->clk = clk_get(&platdev->dev, "uart"); | ||
1075 | |||
1076 | dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n", | ||
1077 | port->mapbase, port->membase, port->irq, port->uartclk); | ||
1078 | |||
1079 | /* reset the fifos (and setup the uart) */ | ||
1080 | s3c24xx_serial_resetport(port, cfg); | ||
1081 | return 0; | ||
1082 | } | ||
1083 | |||
1084 | /* Device driver serial port probe */ | ||
1085 | |||
1086 | static int probe_index = 0; | ||
1087 | |||
1088 | static int s3c24xx_serial_probe(struct platform_device *dev, | ||
1089 | struct s3c24xx_uart_info *info) | ||
1090 | { | ||
1091 | struct s3c24xx_uart_port *ourport; | ||
1092 | int ret; | ||
1093 | |||
1094 | dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index); | ||
1095 | |||
1096 | ourport = &s3c24xx_serial_ports[probe_index]; | ||
1097 | probe_index++; | ||
1098 | |||
1099 | dbg("%s: initialising port %p...\n", __func__, ourport); | ||
1100 | |||
1101 | ret = s3c24xx_serial_init_port(ourport, info, dev); | ||
1102 | if (ret < 0) | ||
1103 | goto probe_err; | ||
1104 | |||
1105 | dbg("%s: adding port\n", __func__); | ||
1106 | uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); | ||
1107 | platform_set_drvdata(dev, &ourport->port); | ||
1108 | |||
1109 | return 0; | ||
1110 | |||
1111 | probe_err: | ||
1112 | return ret; | ||
1113 | } | ||
1114 | |||
1115 | static int s3c24xx_serial_remove(struct platform_device *dev) | ||
1116 | { | ||
1117 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | ||
1118 | |||
1119 | if (port) | ||
1120 | uart_remove_one_port(&s3c24xx_uart_drv, port); | ||
1121 | |||
1122 | return 0; | ||
1123 | } | ||
1124 | |||
1125 | /* UART power management code */ | ||
1126 | |||
1127 | #ifdef CONFIG_PM | ||
1128 | |||
1129 | static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state) | ||
1130 | { | ||
1131 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | ||
1132 | |||
1133 | if (port) | ||
1134 | uart_suspend_port(&s3c24xx_uart_drv, port); | ||
1135 | |||
1136 | return 0; | ||
1137 | } | ||
1138 | |||
1139 | static int s3c24xx_serial_resume(struct platform_device *dev) | ||
1140 | { | ||
1141 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | ||
1142 | struct s3c24xx_uart_port *ourport = to_ourport(port); | ||
1143 | |||
1144 | if (port) { | ||
1145 | clk_enable(ourport->clk); | ||
1146 | s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); | ||
1147 | clk_disable(ourport->clk); | ||
1148 | |||
1149 | uart_resume_port(&s3c24xx_uart_drv, port); | ||
1150 | } | ||
1151 | |||
1152 | return 0; | ||
1153 | } | ||
1154 | |||
1155 | #else | ||
1156 | #define s3c24xx_serial_suspend NULL | ||
1157 | #define s3c24xx_serial_resume NULL | ||
1158 | #endif | ||
1159 | |||
1160 | static int s3c24xx_serial_init(struct platform_driver *drv, | ||
1161 | struct s3c24xx_uart_info *info) | ||
1162 | { | ||
1163 | dbg("s3c24xx_serial_init(%p,%p)\n", drv, info); | ||
1164 | return platform_driver_register(drv); | ||
1165 | } | ||
1166 | |||
1167 | |||
1168 | /* now comes the code to initialise either the s3c2410 or s3c2440 serial | ||
1169 | * port information | ||
1170 | */ | ||
1171 | |||
1172 | /* cpu specific variations on the serial port support */ | ||
1173 | |||
1174 | #ifdef CONFIG_CPU_S3C2400 | ||
1175 | |||
1176 | static int s3c2400_serial_getsource(struct uart_port *port, | ||
1177 | struct s3c24xx_uart_clksrc *clk) | ||
1178 | { | ||
1179 | clk->divisor = 1; | ||
1180 | clk->name = "pclk"; | ||
1181 | |||
1182 | return 0; | ||
1183 | } | ||
1184 | |||
1185 | static int s3c2400_serial_setsource(struct uart_port *port, | ||
1186 | struct s3c24xx_uart_clksrc *clk) | ||
1187 | { | ||
1188 | return 0; | ||
1189 | } | ||
1190 | |||
1191 | static int s3c2400_serial_resetport(struct uart_port *port, | ||
1192 | struct s3c2410_uartcfg *cfg) | ||
1193 | { | ||
1194 | dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n", | ||
1195 | port, port->mapbase, cfg); | ||
1196 | |||
1197 | wr_regl(port, S3C2410_UCON, cfg->ucon); | ||
1198 | wr_regl(port, S3C2410_ULCON, cfg->ulcon); | ||
1199 | |||
1200 | /* reset both fifos */ | ||
1201 | |||
1202 | wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); | ||
1203 | wr_regl(port, S3C2410_UFCON, cfg->ufcon); | ||
1204 | |||
1205 | return 0; | ||
1206 | } | ||
1207 | |||
1208 | static struct s3c24xx_uart_info s3c2400_uart_inf = { | ||
1209 | .name = "Samsung S3C2400 UART", | ||
1210 | .type = PORT_S3C2400, | ||
1211 | .fifosize = 16, | ||
1212 | .rx_fifomask = S3C2410_UFSTAT_RXMASK, | ||
1213 | .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, | ||
1214 | .rx_fifofull = S3C2410_UFSTAT_RXFULL, | ||
1215 | .tx_fifofull = S3C2410_UFSTAT_TXFULL, | ||
1216 | .tx_fifomask = S3C2410_UFSTAT_TXMASK, | ||
1217 | .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, | ||
1218 | .get_clksrc = s3c2400_serial_getsource, | ||
1219 | .set_clksrc = s3c2400_serial_setsource, | ||
1220 | .reset_port = s3c2400_serial_resetport, | ||
1221 | }; | ||
1222 | |||
1223 | static int s3c2400_serial_probe(struct platform_device *dev) | ||
1224 | { | ||
1225 | return s3c24xx_serial_probe(dev, &s3c2400_uart_inf); | ||
1226 | } | ||
1227 | |||
1228 | static struct platform_driver s3c2400_serial_drv = { | ||
1229 | .probe = s3c2400_serial_probe, | ||
1230 | .remove = s3c24xx_serial_remove, | ||
1231 | .suspend = s3c24xx_serial_suspend, | ||
1232 | .resume = s3c24xx_serial_resume, | ||
1233 | .driver = { | ||
1234 | .name = "s3c2400-uart", | ||
1235 | .owner = THIS_MODULE, | ||
1236 | }, | ||
1237 | }; | ||
1238 | |||
1239 | static inline int s3c2400_serial_init(void) | ||
1240 | { | ||
1241 | return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf); | ||
1242 | } | ||
1243 | |||
1244 | static inline void s3c2400_serial_exit(void) | ||
1245 | { | ||
1246 | platform_driver_unregister(&s3c2400_serial_drv); | ||
1247 | } | ||
1248 | |||
1249 | #define s3c2400_uart_inf_at &s3c2400_uart_inf | ||
1250 | #else | ||
1251 | |||
1252 | static inline int s3c2400_serial_init(void) | ||
1253 | { | ||
1254 | return 0; | ||
1255 | } | ||
1256 | |||
1257 | static inline void s3c2400_serial_exit(void) | ||
1258 | { | ||
1259 | } | ||
1260 | |||
1261 | #define s3c2400_uart_inf_at NULL | ||
1262 | |||
1263 | #endif /* CONFIG_CPU_S3C2400 */ | ||
1264 | |||
1265 | /* S3C2410 support */ | ||
1266 | |||
1267 | #ifdef CONFIG_CPU_S3C2410 | ||
1268 | 28 | ||
1269 | static int s3c2410_serial_setsource(struct uart_port *port, | 29 | static int s3c2410_serial_setsource(struct uart_port *port, |
1270 | struct s3c24xx_uart_clksrc *clk) | 30 | struct s3c24xx_uart_clksrc *clk) |
@@ -1323,8 +83,6 @@ static struct s3c24xx_uart_info s3c2410_uart_inf = { | |||
1323 | .reset_port = s3c2410_serial_resetport, | 83 | .reset_port = s3c2410_serial_resetport, |
1324 | }; | 84 | }; |
1325 | 85 | ||
1326 | /* device management */ | ||
1327 | |||
1328 | static int s3c2410_serial_probe(struct platform_device *dev) | 86 | static int s3c2410_serial_probe(struct platform_device *dev) |
1329 | { | 87 | { |
1330 | return s3c24xx_serial_probe(dev, &s3c2410_uart_inf); | 88 | return s3c24xx_serial_probe(dev, &s3c2410_uart_inf); |
@@ -1333,612 +91,28 @@ static int s3c2410_serial_probe(struct platform_device *dev) | |||
1333 | static struct platform_driver s3c2410_serial_drv = { | 91 | static struct platform_driver s3c2410_serial_drv = { |
1334 | .probe = s3c2410_serial_probe, | 92 | .probe = s3c2410_serial_probe, |
1335 | .remove = s3c24xx_serial_remove, | 93 | .remove = s3c24xx_serial_remove, |
1336 | .suspend = s3c24xx_serial_suspend, | ||
1337 | .resume = s3c24xx_serial_resume, | ||
1338 | .driver = { | 94 | .driver = { |
1339 | .name = "s3c2410-uart", | 95 | .name = "s3c2410-uart", |
1340 | .owner = THIS_MODULE, | 96 | .owner = THIS_MODULE, |
1341 | }, | 97 | }, |
1342 | }; | 98 | }; |
1343 | 99 | ||
1344 | static inline int s3c2410_serial_init(void) | 100 | s3c24xx_console_init(&s3c2410_serial_drv, &s3c2410_uart_inf); |
101 | |||
102 | static int __init s3c2410_serial_init(void) | ||
1345 | { | 103 | { |
1346 | return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf); | 104 | return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf); |
1347 | } | 105 | } |
1348 | 106 | ||
1349 | static inline void s3c2410_serial_exit(void) | 107 | static void __exit s3c2410_serial_exit(void) |
1350 | { | 108 | { |
1351 | platform_driver_unregister(&s3c2410_serial_drv); | 109 | platform_driver_unregister(&s3c2410_serial_drv); |
1352 | } | 110 | } |
1353 | 111 | ||
1354 | #define s3c2410_uart_inf_at &s3c2410_uart_inf | 112 | module_init(s3c2410_serial_init); |
1355 | #else | 113 | module_exit(s3c2410_serial_exit); |
1356 | |||
1357 | static inline int s3c2410_serial_init(void) | ||
1358 | { | ||
1359 | return 0; | ||
1360 | } | ||
1361 | |||
1362 | static inline void s3c2410_serial_exit(void) | ||
1363 | { | ||
1364 | } | ||
1365 | |||
1366 | #define s3c2410_uart_inf_at NULL | ||
1367 | |||
1368 | #endif /* CONFIG_CPU_S3C2410 */ | ||
1369 | |||
1370 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) | ||
1371 | |||
1372 | static int s3c2440_serial_setsource(struct uart_port *port, | ||
1373 | struct s3c24xx_uart_clksrc *clk) | ||
1374 | { | ||
1375 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
1376 | |||
1377 | // todo - proper fclk<>nonfclk switch // | ||
1378 | |||
1379 | ucon &= ~S3C2440_UCON_CLKMASK; | ||
1380 | |||
1381 | if (strcmp(clk->name, "uclk") == 0) | ||
1382 | ucon |= S3C2440_UCON_UCLK; | ||
1383 | else if (strcmp(clk->name, "pclk") == 0) | ||
1384 | ucon |= S3C2440_UCON_PCLK; | ||
1385 | else if (strcmp(clk->name, "fclk") == 0) | ||
1386 | ucon |= S3C2440_UCON_FCLK; | ||
1387 | else { | ||
1388 | printk(KERN_ERR "unknown clock source %s\n", clk->name); | ||
1389 | return -EINVAL; | ||
1390 | } | ||
1391 | |||
1392 | wr_regl(port, S3C2410_UCON, ucon); | ||
1393 | return 0; | ||
1394 | } | ||
1395 | |||
1396 | |||
1397 | static int s3c2440_serial_getsource(struct uart_port *port, | ||
1398 | struct s3c24xx_uart_clksrc *clk) | ||
1399 | { | ||
1400 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
1401 | unsigned long ucon0, ucon1, ucon2; | ||
1402 | |||
1403 | switch (ucon & S3C2440_UCON_CLKMASK) { | ||
1404 | case S3C2440_UCON_UCLK: | ||
1405 | clk->divisor = 1; | ||
1406 | clk->name = "uclk"; | ||
1407 | break; | ||
1408 | |||
1409 | case S3C2440_UCON_PCLK: | ||
1410 | case S3C2440_UCON_PCLK2: | ||
1411 | clk->divisor = 1; | ||
1412 | clk->name = "pclk"; | ||
1413 | break; | ||
1414 | |||
1415 | case S3C2440_UCON_FCLK: | ||
1416 | /* the fun of calculating the uart divisors on | ||
1417 | * the s3c2440 */ | ||
1418 | |||
1419 | ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON); | ||
1420 | ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON); | ||
1421 | ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON); | ||
1422 | |||
1423 | printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2); | ||
1424 | |||
1425 | ucon0 &= S3C2440_UCON0_DIVMASK; | ||
1426 | ucon1 &= S3C2440_UCON1_DIVMASK; | ||
1427 | ucon2 &= S3C2440_UCON2_DIVMASK; | ||
1428 | |||
1429 | if (ucon0 != 0) { | ||
1430 | clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT; | ||
1431 | clk->divisor += 6; | ||
1432 | } else if (ucon1 != 0) { | ||
1433 | clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT; | ||
1434 | clk->divisor += 21; | ||
1435 | } else if (ucon2 != 0) { | ||
1436 | clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT; | ||
1437 | clk->divisor += 36; | ||
1438 | } else { | ||
1439 | /* manual calims 44, seems to be 9 */ | ||
1440 | clk->divisor = 9; | ||
1441 | } | ||
1442 | |||
1443 | clk->name = "fclk"; | ||
1444 | break; | ||
1445 | } | ||
1446 | |||
1447 | return 0; | ||
1448 | } | ||
1449 | |||
1450 | static int s3c2440_serial_resetport(struct uart_port *port, | ||
1451 | struct s3c2410_uartcfg *cfg) | ||
1452 | { | ||
1453 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
1454 | |||
1455 | dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n", | ||
1456 | port, port->mapbase, cfg); | ||
1457 | |||
1458 | /* ensure we don't change the clock settings... */ | ||
1459 | |||
1460 | ucon &= (S3C2440_UCON0_DIVMASK | (3<<10)); | ||
1461 | |||
1462 | wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); | ||
1463 | wr_regl(port, S3C2410_ULCON, cfg->ulcon); | ||
1464 | |||
1465 | /* reset both fifos */ | ||
1466 | |||
1467 | wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); | ||
1468 | wr_regl(port, S3C2410_UFCON, cfg->ufcon); | ||
1469 | |||
1470 | return 0; | ||
1471 | } | ||
1472 | |||
1473 | static struct s3c24xx_uart_info s3c2440_uart_inf = { | ||
1474 | .name = "Samsung S3C2440 UART", | ||
1475 | .type = PORT_S3C2440, | ||
1476 | .fifosize = 64, | ||
1477 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | ||
1478 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | ||
1479 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | ||
1480 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | ||
1481 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | ||
1482 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | ||
1483 | .get_clksrc = s3c2440_serial_getsource, | ||
1484 | .set_clksrc = s3c2440_serial_setsource, | ||
1485 | .reset_port = s3c2440_serial_resetport, | ||
1486 | }; | ||
1487 | |||
1488 | /* device management */ | ||
1489 | |||
1490 | static int s3c2440_serial_probe(struct platform_device *dev) | ||
1491 | { | ||
1492 | dbg("s3c2440_serial_probe: dev=%p\n", dev); | ||
1493 | return s3c24xx_serial_probe(dev, &s3c2440_uart_inf); | ||
1494 | } | ||
1495 | |||
1496 | static struct platform_driver s3c2440_serial_drv = { | ||
1497 | .probe = s3c2440_serial_probe, | ||
1498 | .remove = s3c24xx_serial_remove, | ||
1499 | .suspend = s3c24xx_serial_suspend, | ||
1500 | .resume = s3c24xx_serial_resume, | ||
1501 | .driver = { | ||
1502 | .name = "s3c2440-uart", | ||
1503 | .owner = THIS_MODULE, | ||
1504 | }, | ||
1505 | }; | ||
1506 | |||
1507 | |||
1508 | static inline int s3c2440_serial_init(void) | ||
1509 | { | ||
1510 | return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf); | ||
1511 | } | ||
1512 | |||
1513 | static inline void s3c2440_serial_exit(void) | ||
1514 | { | ||
1515 | platform_driver_unregister(&s3c2440_serial_drv); | ||
1516 | } | ||
1517 | |||
1518 | #define s3c2440_uart_inf_at &s3c2440_uart_inf | ||
1519 | #else | ||
1520 | |||
1521 | static inline int s3c2440_serial_init(void) | ||
1522 | { | ||
1523 | return 0; | ||
1524 | } | ||
1525 | |||
1526 | static inline void s3c2440_serial_exit(void) | ||
1527 | { | ||
1528 | } | ||
1529 | |||
1530 | #define s3c2440_uart_inf_at NULL | ||
1531 | #endif /* CONFIG_CPU_S3C2440 */ | ||
1532 | |||
1533 | #if defined(CONFIG_CPU_S3C2412) | ||
1534 | |||
1535 | static int s3c2412_serial_setsource(struct uart_port *port, | ||
1536 | struct s3c24xx_uart_clksrc *clk) | ||
1537 | { | ||
1538 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
1539 | |||
1540 | ucon &= ~S3C2412_UCON_CLKMASK; | ||
1541 | |||
1542 | if (strcmp(clk->name, "uclk") == 0) | ||
1543 | ucon |= S3C2440_UCON_UCLK; | ||
1544 | else if (strcmp(clk->name, "pclk") == 0) | ||
1545 | ucon |= S3C2440_UCON_PCLK; | ||
1546 | else if (strcmp(clk->name, "usysclk") == 0) | ||
1547 | ucon |= S3C2412_UCON_USYSCLK; | ||
1548 | else { | ||
1549 | printk(KERN_ERR "unknown clock source %s\n", clk->name); | ||
1550 | return -EINVAL; | ||
1551 | } | ||
1552 | |||
1553 | wr_regl(port, S3C2410_UCON, ucon); | ||
1554 | return 0; | ||
1555 | } | ||
1556 | |||
1557 | |||
1558 | static int s3c2412_serial_getsource(struct uart_port *port, | ||
1559 | struct s3c24xx_uart_clksrc *clk) | ||
1560 | { | ||
1561 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
1562 | |||
1563 | switch (ucon & S3C2412_UCON_CLKMASK) { | ||
1564 | case S3C2412_UCON_UCLK: | ||
1565 | clk->divisor = 1; | ||
1566 | clk->name = "uclk"; | ||
1567 | break; | ||
1568 | |||
1569 | case S3C2412_UCON_PCLK: | ||
1570 | case S3C2412_UCON_PCLK2: | ||
1571 | clk->divisor = 1; | ||
1572 | clk->name = "pclk"; | ||
1573 | break; | ||
1574 | |||
1575 | case S3C2412_UCON_USYSCLK: | ||
1576 | clk->divisor = 1; | ||
1577 | clk->name = "usysclk"; | ||
1578 | break; | ||
1579 | } | ||
1580 | |||
1581 | return 0; | ||
1582 | } | ||
1583 | |||
1584 | static int s3c2412_serial_resetport(struct uart_port *port, | ||
1585 | struct s3c2410_uartcfg *cfg) | ||
1586 | { | ||
1587 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
1588 | |||
1589 | dbg("%s: port=%p (%08lx), cfg=%p\n", | ||
1590 | __func__, port, port->mapbase, cfg); | ||
1591 | |||
1592 | /* ensure we don't change the clock settings... */ | ||
1593 | |||
1594 | ucon &= S3C2412_UCON_CLKMASK; | ||
1595 | |||
1596 | wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); | ||
1597 | wr_regl(port, S3C2410_ULCON, cfg->ulcon); | ||
1598 | |||
1599 | /* reset both fifos */ | ||
1600 | |||
1601 | wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); | ||
1602 | wr_regl(port, S3C2410_UFCON, cfg->ufcon); | ||
1603 | |||
1604 | return 0; | ||
1605 | } | ||
1606 | |||
1607 | static struct s3c24xx_uart_info s3c2412_uart_inf = { | ||
1608 | .name = "Samsung S3C2412 UART", | ||
1609 | .type = PORT_S3C2412, | ||
1610 | .fifosize = 64, | ||
1611 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | ||
1612 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | ||
1613 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | ||
1614 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | ||
1615 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | ||
1616 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | ||
1617 | .get_clksrc = s3c2412_serial_getsource, | ||
1618 | .set_clksrc = s3c2412_serial_setsource, | ||
1619 | .reset_port = s3c2412_serial_resetport, | ||
1620 | }; | ||
1621 | |||
1622 | /* device management */ | ||
1623 | |||
1624 | static int s3c2412_serial_probe(struct platform_device *dev) | ||
1625 | { | ||
1626 | dbg("s3c2440_serial_probe: dev=%p\n", dev); | ||
1627 | return s3c24xx_serial_probe(dev, &s3c2412_uart_inf); | ||
1628 | } | ||
1629 | |||
1630 | static struct platform_driver s3c2412_serial_drv = { | ||
1631 | .probe = s3c2412_serial_probe, | ||
1632 | .remove = s3c24xx_serial_remove, | ||
1633 | .suspend = s3c24xx_serial_suspend, | ||
1634 | .resume = s3c24xx_serial_resume, | ||
1635 | .driver = { | ||
1636 | .name = "s3c2412-uart", | ||
1637 | .owner = THIS_MODULE, | ||
1638 | }, | ||
1639 | }; | ||
1640 | |||
1641 | |||
1642 | static inline int s3c2412_serial_init(void) | ||
1643 | { | ||
1644 | return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf); | ||
1645 | } | ||
1646 | |||
1647 | static inline void s3c2412_serial_exit(void) | ||
1648 | { | ||
1649 | platform_driver_unregister(&s3c2412_serial_drv); | ||
1650 | } | ||
1651 | |||
1652 | #define s3c2412_uart_inf_at &s3c2412_uart_inf | ||
1653 | #else | ||
1654 | |||
1655 | static inline int s3c2412_serial_init(void) | ||
1656 | { | ||
1657 | return 0; | ||
1658 | } | ||
1659 | |||
1660 | static inline void s3c2412_serial_exit(void) | ||
1661 | { | ||
1662 | } | ||
1663 | |||
1664 | #define s3c2412_uart_inf_at NULL | ||
1665 | #endif /* CONFIG_CPU_S3C2440 */ | ||
1666 | |||
1667 | |||
1668 | /* module initialisation code */ | ||
1669 | |||
1670 | static int __init s3c24xx_serial_modinit(void) | ||
1671 | { | ||
1672 | int ret; | ||
1673 | |||
1674 | ret = uart_register_driver(&s3c24xx_uart_drv); | ||
1675 | if (ret < 0) { | ||
1676 | printk(KERN_ERR "failed to register UART driver\n"); | ||
1677 | return -1; | ||
1678 | } | ||
1679 | |||
1680 | s3c2400_serial_init(); | ||
1681 | s3c2410_serial_init(); | ||
1682 | s3c2412_serial_init(); | ||
1683 | s3c2440_serial_init(); | ||
1684 | |||
1685 | return 0; | ||
1686 | } | ||
1687 | |||
1688 | static void __exit s3c24xx_serial_modexit(void) | ||
1689 | { | ||
1690 | s3c2400_serial_exit(); | ||
1691 | s3c2410_serial_exit(); | ||
1692 | s3c2412_serial_exit(); | ||
1693 | s3c2440_serial_exit(); | ||
1694 | |||
1695 | uart_unregister_driver(&s3c24xx_uart_drv); | ||
1696 | } | ||
1697 | |||
1698 | |||
1699 | module_init(s3c24xx_serial_modinit); | ||
1700 | module_exit(s3c24xx_serial_modexit); | ||
1701 | |||
1702 | /* Console code */ | ||
1703 | |||
1704 | #ifdef CONFIG_SERIAL_S3C2410_CONSOLE | ||
1705 | |||
1706 | static struct uart_port *cons_uart; | ||
1707 | |||
1708 | static int | ||
1709 | s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) | ||
1710 | { | ||
1711 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
1712 | unsigned long ufstat, utrstat; | ||
1713 | |||
1714 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | ||
1715 | /* fifo mode - check ammount of data in fifo registers... */ | ||
1716 | |||
1717 | ufstat = rd_regl(port, S3C2410_UFSTAT); | ||
1718 | return (ufstat & info->tx_fifofull) ? 0 : 1; | ||
1719 | } | ||
1720 | |||
1721 | /* in non-fifo mode, we go and use the tx buffer empty */ | ||
1722 | |||
1723 | utrstat = rd_regl(port, S3C2410_UTRSTAT); | ||
1724 | return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0; | ||
1725 | } | ||
1726 | |||
1727 | static void | ||
1728 | s3c24xx_serial_console_putchar(struct uart_port *port, int ch) | ||
1729 | { | ||
1730 | unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON); | ||
1731 | while (!s3c24xx_serial_console_txrdy(port, ufcon)) | ||
1732 | barrier(); | ||
1733 | wr_regb(cons_uart, S3C2410_UTXH, ch); | ||
1734 | } | ||
1735 | |||
1736 | static void | ||
1737 | s3c24xx_serial_console_write(struct console *co, const char *s, | ||
1738 | unsigned int count) | ||
1739 | { | ||
1740 | uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); | ||
1741 | } | ||
1742 | |||
1743 | static void __init | ||
1744 | s3c24xx_serial_get_options(struct uart_port *port, int *baud, | ||
1745 | int *parity, int *bits) | ||
1746 | { | ||
1747 | struct s3c24xx_uart_clksrc clksrc; | ||
1748 | struct clk *clk; | ||
1749 | unsigned int ulcon; | ||
1750 | unsigned int ucon; | ||
1751 | unsigned int ubrdiv; | ||
1752 | unsigned long rate; | ||
1753 | |||
1754 | ulcon = rd_regl(port, S3C2410_ULCON); | ||
1755 | ucon = rd_regl(port, S3C2410_UCON); | ||
1756 | ubrdiv = rd_regl(port, S3C2410_UBRDIV); | ||
1757 | |||
1758 | dbg("s3c24xx_serial_get_options: port=%p\n" | ||
1759 | "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n", | ||
1760 | port, ulcon, ucon, ubrdiv); | ||
1761 | |||
1762 | if ((ucon & 0xf) != 0) { | ||
1763 | /* consider the serial port configured if the tx/rx mode set */ | ||
1764 | |||
1765 | switch (ulcon & S3C2410_LCON_CSMASK) { | ||
1766 | case S3C2410_LCON_CS5: | ||
1767 | *bits = 5; | ||
1768 | break; | ||
1769 | case S3C2410_LCON_CS6: | ||
1770 | *bits = 6; | ||
1771 | break; | ||
1772 | case S3C2410_LCON_CS7: | ||
1773 | *bits = 7; | ||
1774 | break; | ||
1775 | default: | ||
1776 | case S3C2410_LCON_CS8: | ||
1777 | *bits = 8; | ||
1778 | break; | ||
1779 | } | ||
1780 | |||
1781 | switch (ulcon & S3C2410_LCON_PMASK) { | ||
1782 | case S3C2410_LCON_PEVEN: | ||
1783 | *parity = 'e'; | ||
1784 | break; | ||
1785 | |||
1786 | case S3C2410_LCON_PODD: | ||
1787 | *parity = 'o'; | ||
1788 | break; | ||
1789 | |||
1790 | case S3C2410_LCON_PNONE: | ||
1791 | default: | ||
1792 | *parity = 'n'; | ||
1793 | } | ||
1794 | |||
1795 | /* now calculate the baud rate */ | ||
1796 | |||
1797 | s3c24xx_serial_getsource(port, &clksrc); | ||
1798 | |||
1799 | clk = clk_get(port->dev, clksrc.name); | ||
1800 | if (!IS_ERR(clk) && clk != NULL) | ||
1801 | rate = clk_get_rate(clk) / clksrc.divisor; | ||
1802 | else | ||
1803 | rate = 1; | ||
1804 | |||
1805 | |||
1806 | *baud = rate / ( 16 * (ubrdiv + 1)); | ||
1807 | dbg("calculated baud %d\n", *baud); | ||
1808 | } | ||
1809 | |||
1810 | } | ||
1811 | |||
1812 | /* s3c24xx_serial_init_ports | ||
1813 | * | ||
1814 | * initialise the serial ports from the machine provided initialisation | ||
1815 | * data. | ||
1816 | */ | ||
1817 | |||
1818 | static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info) | ||
1819 | { | ||
1820 | struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports; | ||
1821 | struct platform_device **platdev_ptr; | ||
1822 | int i; | ||
1823 | |||
1824 | dbg("s3c24xx_serial_init_ports: initialising ports...\n"); | ||
1825 | |||
1826 | platdev_ptr = s3c24xx_uart_devs; | ||
1827 | |||
1828 | for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) { | ||
1829 | s3c24xx_serial_init_port(ptr, info, *platdev_ptr); | ||
1830 | } | ||
1831 | |||
1832 | return 0; | ||
1833 | } | ||
1834 | |||
1835 | static int __init | ||
1836 | s3c24xx_serial_console_setup(struct console *co, char *options) | ||
1837 | { | ||
1838 | struct uart_port *port; | ||
1839 | int baud = 9600; | ||
1840 | int bits = 8; | ||
1841 | int parity = 'n'; | ||
1842 | int flow = 'n'; | ||
1843 | |||
1844 | dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n", | ||
1845 | co, co->index, options); | ||
1846 | |||
1847 | /* is this a valid port */ | ||
1848 | |||
1849 | if (co->index == -1 || co->index >= NR_PORTS) | ||
1850 | co->index = 0; | ||
1851 | |||
1852 | port = &s3c24xx_serial_ports[co->index].port; | ||
1853 | |||
1854 | /* is the port configured? */ | ||
1855 | |||
1856 | if (port->mapbase == 0x0) { | ||
1857 | co->index = 0; | ||
1858 | port = &s3c24xx_serial_ports[co->index].port; | ||
1859 | } | ||
1860 | |||
1861 | cons_uart = port; | ||
1862 | |||
1863 | dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index); | ||
1864 | |||
1865 | /* | ||
1866 | * Check whether an invalid uart number has been specified, and | ||
1867 | * if so, search for the first available port that does have | ||
1868 | * console support. | ||
1869 | */ | ||
1870 | if (options) | ||
1871 | uart_parse_options(options, &baud, &parity, &bits, &flow); | ||
1872 | else | ||
1873 | s3c24xx_serial_get_options(port, &baud, &parity, &bits); | ||
1874 | |||
1875 | dbg("s3c24xx_serial_console_setup: baud %d\n", baud); | ||
1876 | |||
1877 | return uart_set_options(port, co, baud, parity, bits, flow); | ||
1878 | } | ||
1879 | |||
1880 | /* s3c24xx_serial_initconsole | ||
1881 | * | ||
1882 | * initialise the console from one of the uart drivers | ||
1883 | */ | ||
1884 | |||
1885 | static struct console s3c24xx_serial_console = | ||
1886 | { | ||
1887 | .name = S3C24XX_SERIAL_NAME, | ||
1888 | .device = uart_console_device, | ||
1889 | .flags = CON_PRINTBUFFER, | ||
1890 | .index = -1, | ||
1891 | .write = s3c24xx_serial_console_write, | ||
1892 | .setup = s3c24xx_serial_console_setup | ||
1893 | }; | ||
1894 | |||
1895 | static int s3c24xx_serial_initconsole(void) | ||
1896 | { | ||
1897 | struct s3c24xx_uart_info *info; | ||
1898 | struct platform_device *dev = s3c24xx_uart_devs[0]; | ||
1899 | |||
1900 | dbg("s3c24xx_serial_initconsole\n"); | ||
1901 | |||
1902 | /* select driver based on the cpu */ | ||
1903 | |||
1904 | if (dev == NULL) { | ||
1905 | printk(KERN_ERR "s3c24xx: no devices for console init\n"); | ||
1906 | return 0; | ||
1907 | } | ||
1908 | |||
1909 | if (strcmp(dev->name, "s3c2400-uart") == 0) { | ||
1910 | info = s3c2400_uart_inf_at; | ||
1911 | } else if (strcmp(dev->name, "s3c2410-uart") == 0) { | ||
1912 | info = s3c2410_uart_inf_at; | ||
1913 | } else if (strcmp(dev->name, "s3c2440-uart") == 0) { | ||
1914 | info = s3c2440_uart_inf_at; | ||
1915 | } else if (strcmp(dev->name, "s3c2412-uart") == 0) { | ||
1916 | info = s3c2412_uart_inf_at; | ||
1917 | } else { | ||
1918 | printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name); | ||
1919 | return 0; | ||
1920 | } | ||
1921 | |||
1922 | if (info == NULL) { | ||
1923 | printk(KERN_ERR "s3c24xx: no driver for console\n"); | ||
1924 | return 0; | ||
1925 | } | ||
1926 | |||
1927 | s3c24xx_serial_console.data = &s3c24xx_uart_drv; | ||
1928 | s3c24xx_serial_init_ports(info); | ||
1929 | |||
1930 | register_console(&s3c24xx_serial_console); | ||
1931 | return 0; | ||
1932 | } | ||
1933 | |||
1934 | console_initcall(s3c24xx_serial_initconsole); | ||
1935 | |||
1936 | #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */ | ||
1937 | 114 | ||
1938 | MODULE_LICENSE("GPL"); | 115 | MODULE_LICENSE("GPL v2"); |
1939 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | 116 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); |
1940 | MODULE_DESCRIPTION("Samsung S3C2410/S3C2440/S3C2412 Serial port driver"); | 117 | MODULE_DESCRIPTION("Samsung S3C2410 SoC Serial port driver"); |
1941 | MODULE_ALIAS("platform:s3c2400-uart"); | ||
1942 | MODULE_ALIAS("platform:s3c2410-uart"); | 118 | MODULE_ALIAS("platform:s3c2410-uart"); |
1943 | MODULE_ALIAS("platform:s3c2412-uart"); | ||
1944 | MODULE_ALIAS("platform:s3c2440-uart"); | ||
diff --git a/drivers/serial/s3c2412.c b/drivers/serial/s3c2412.c new file mode 100644 index 000000000000..ce0c220e3e92 --- /dev/null +++ b/drivers/serial/s3c2412.c | |||
@@ -0,0 +1,151 @@ | |||
1 | /* linux/drivers/serial/s3c2412.c | ||
2 | * | ||
3 | * Driver for Samsung S3C2412 and S3C2413 SoC onboard UARTs. | ||
4 | * | ||
5 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/module.h> | ||
14 | #include <linux/ioport.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/serial_core.h> | ||
19 | #include <linux/serial.h> | ||
20 | |||
21 | #include <asm/irq.h> | ||
22 | #include <asm/hardware.h> | ||
23 | |||
24 | #include <asm/plat-s3c/regs-serial.h> | ||
25 | #include <asm/arch/regs-gpio.h> | ||
26 | |||
27 | #include "samsung.h" | ||
28 | |||
29 | static int s3c2412_serial_setsource(struct uart_port *port, | ||
30 | struct s3c24xx_uart_clksrc *clk) | ||
31 | { | ||
32 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
33 | |||
34 | ucon &= ~S3C2412_UCON_CLKMASK; | ||
35 | |||
36 | if (strcmp(clk->name, "uclk") == 0) | ||
37 | ucon |= S3C2440_UCON_UCLK; | ||
38 | else if (strcmp(clk->name, "pclk") == 0) | ||
39 | ucon |= S3C2440_UCON_PCLK; | ||
40 | else if (strcmp(clk->name, "usysclk") == 0) | ||
41 | ucon |= S3C2412_UCON_USYSCLK; | ||
42 | else { | ||
43 | printk(KERN_ERR "unknown clock source %s\n", clk->name); | ||
44 | return -EINVAL; | ||
45 | } | ||
46 | |||
47 | wr_regl(port, S3C2410_UCON, ucon); | ||
48 | return 0; | ||
49 | } | ||
50 | |||
51 | |||
52 | static int s3c2412_serial_getsource(struct uart_port *port, | ||
53 | struct s3c24xx_uart_clksrc *clk) | ||
54 | { | ||
55 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
56 | |||
57 | switch (ucon & S3C2412_UCON_CLKMASK) { | ||
58 | case S3C2412_UCON_UCLK: | ||
59 | clk->divisor = 1; | ||
60 | clk->name = "uclk"; | ||
61 | break; | ||
62 | |||
63 | case S3C2412_UCON_PCLK: | ||
64 | case S3C2412_UCON_PCLK2: | ||
65 | clk->divisor = 1; | ||
66 | clk->name = "pclk"; | ||
67 | break; | ||
68 | |||
69 | case S3C2412_UCON_USYSCLK: | ||
70 | clk->divisor = 1; | ||
71 | clk->name = "usysclk"; | ||
72 | break; | ||
73 | } | ||
74 | |||
75 | return 0; | ||
76 | } | ||
77 | |||
78 | static int s3c2412_serial_resetport(struct uart_port *port, | ||
79 | struct s3c2410_uartcfg *cfg) | ||
80 | { | ||
81 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
82 | |||
83 | dbg("%s: port=%p (%08lx), cfg=%p\n", | ||
84 | __func__, port, port->mapbase, cfg); | ||
85 | |||
86 | /* ensure we don't change the clock settings... */ | ||
87 | |||
88 | ucon &= S3C2412_UCON_CLKMASK; | ||
89 | |||
90 | wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); | ||
91 | wr_regl(port, S3C2410_ULCON, cfg->ulcon); | ||
92 | |||
93 | /* reset both fifos */ | ||
94 | |||
95 | wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); | ||
96 | wr_regl(port, S3C2410_UFCON, cfg->ufcon); | ||
97 | |||
98 | return 0; | ||
99 | } | ||
100 | |||
101 | static struct s3c24xx_uart_info s3c2412_uart_inf = { | ||
102 | .name = "Samsung S3C2412 UART", | ||
103 | .type = PORT_S3C2412, | ||
104 | .fifosize = 64, | ||
105 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | ||
106 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | ||
107 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | ||
108 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | ||
109 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | ||
110 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | ||
111 | .get_clksrc = s3c2412_serial_getsource, | ||
112 | .set_clksrc = s3c2412_serial_setsource, | ||
113 | .reset_port = s3c2412_serial_resetport, | ||
114 | }; | ||
115 | |||
116 | /* device management */ | ||
117 | |||
118 | static int s3c2412_serial_probe(struct platform_device *dev) | ||
119 | { | ||
120 | dbg("s3c2440_serial_probe: dev=%p\n", dev); | ||
121 | return s3c24xx_serial_probe(dev, &s3c2412_uart_inf); | ||
122 | } | ||
123 | |||
124 | static struct platform_driver s3c2412_serial_drv = { | ||
125 | .probe = s3c2412_serial_probe, | ||
126 | .remove = s3c24xx_serial_remove, | ||
127 | .driver = { | ||
128 | .name = "s3c2412-uart", | ||
129 | .owner = THIS_MODULE, | ||
130 | }, | ||
131 | }; | ||
132 | |||
133 | s3c24xx_console_init(&s3c2412_serial_drv, &s3c2412_uart_inf); | ||
134 | |||
135 | static inline int s3c2412_serial_init(void) | ||
136 | { | ||
137 | return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf); | ||
138 | } | ||
139 | |||
140 | static inline void s3c2412_serial_exit(void) | ||
141 | { | ||
142 | platform_driver_unregister(&s3c2412_serial_drv); | ||
143 | } | ||
144 | |||
145 | module_init(s3c2412_serial_init); | ||
146 | module_exit(s3c2412_serial_exit); | ||
147 | |||
148 | MODULE_DESCRIPTION("Samsung S3C2412,S3C2413 SoC Serial port driver"); | ||
149 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | ||
150 | MODULE_LICENSE("GPL v2"); | ||
151 | MODULE_ALIAS("platform:s3c2412-uart"); | ||
diff --git a/drivers/serial/s3c2440.c b/drivers/serial/s3c2440.c new file mode 100644 index 000000000000..38f954bd39c6 --- /dev/null +++ b/drivers/serial/s3c2440.c | |||
@@ -0,0 +1,181 @@ | |||
1 | /* linux/drivers/serial/s3c2440.c | ||
2 | * | ||
3 | * Driver for Samsung S3C2440 and S3C2442 SoC onboard UARTs. | ||
4 | * | ||
5 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/module.h> | ||
14 | #include <linux/ioport.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/serial_core.h> | ||
19 | #include <linux/serial.h> | ||
20 | |||
21 | #include <asm/irq.h> | ||
22 | #include <asm/hardware.h> | ||
23 | |||
24 | #include <asm/plat-s3c/regs-serial.h> | ||
25 | #include <asm/arch/regs-gpio.h> | ||
26 | |||
27 | #include "samsung.h" | ||
28 | |||
29 | |||
30 | static int s3c2440_serial_setsource(struct uart_port *port, | ||
31 | struct s3c24xx_uart_clksrc *clk) | ||
32 | { | ||
33 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
34 | |||
35 | /* todo - proper fclk<>nonfclk switch. */ | ||
36 | |||
37 | ucon &= ~S3C2440_UCON_CLKMASK; | ||
38 | |||
39 | if (strcmp(clk->name, "uclk") == 0) | ||
40 | ucon |= S3C2440_UCON_UCLK; | ||
41 | else if (strcmp(clk->name, "pclk") == 0) | ||
42 | ucon |= S3C2440_UCON_PCLK; | ||
43 | else if (strcmp(clk->name, "fclk") == 0) | ||
44 | ucon |= S3C2440_UCON_FCLK; | ||
45 | else { | ||
46 | printk(KERN_ERR "unknown clock source %s\n", clk->name); | ||
47 | return -EINVAL; | ||
48 | } | ||
49 | |||
50 | wr_regl(port, S3C2410_UCON, ucon); | ||
51 | return 0; | ||
52 | } | ||
53 | |||
54 | |||
55 | static int s3c2440_serial_getsource(struct uart_port *port, | ||
56 | struct s3c24xx_uart_clksrc *clk) | ||
57 | { | ||
58 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
59 | unsigned long ucon0, ucon1, ucon2; | ||
60 | |||
61 | switch (ucon & S3C2440_UCON_CLKMASK) { | ||
62 | case S3C2440_UCON_UCLK: | ||
63 | clk->divisor = 1; | ||
64 | clk->name = "uclk"; | ||
65 | break; | ||
66 | |||
67 | case S3C2440_UCON_PCLK: | ||
68 | case S3C2440_UCON_PCLK2: | ||
69 | clk->divisor = 1; | ||
70 | clk->name = "pclk"; | ||
71 | break; | ||
72 | |||
73 | case S3C2440_UCON_FCLK: | ||
74 | /* the fun of calculating the uart divisors on | ||
75 | * the s3c2440 */ | ||
76 | |||
77 | ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON); | ||
78 | ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON); | ||
79 | ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON); | ||
80 | |||
81 | printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2); | ||
82 | |||
83 | ucon0 &= S3C2440_UCON0_DIVMASK; | ||
84 | ucon1 &= S3C2440_UCON1_DIVMASK; | ||
85 | ucon2 &= S3C2440_UCON2_DIVMASK; | ||
86 | |||
87 | if (ucon0 != 0) { | ||
88 | clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT; | ||
89 | clk->divisor += 6; | ||
90 | } else if (ucon1 != 0) { | ||
91 | clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT; | ||
92 | clk->divisor += 21; | ||
93 | } else if (ucon2 != 0) { | ||
94 | clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT; | ||
95 | clk->divisor += 36; | ||
96 | } else { | ||
97 | /* manual calims 44, seems to be 9 */ | ||
98 | clk->divisor = 9; | ||
99 | } | ||
100 | |||
101 | clk->name = "fclk"; | ||
102 | break; | ||
103 | } | ||
104 | |||
105 | return 0; | ||
106 | } | ||
107 | |||
108 | static int s3c2440_serial_resetport(struct uart_port *port, | ||
109 | struct s3c2410_uartcfg *cfg) | ||
110 | { | ||
111 | unsigned long ucon = rd_regl(port, S3C2410_UCON); | ||
112 | |||
113 | dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n", | ||
114 | port, port->mapbase, cfg); | ||
115 | |||
116 | /* ensure we don't change the clock settings... */ | ||
117 | |||
118 | ucon &= (S3C2440_UCON0_DIVMASK | (3<<10)); | ||
119 | |||
120 | wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); | ||
121 | wr_regl(port, S3C2410_ULCON, cfg->ulcon); | ||
122 | |||
123 | /* reset both fifos */ | ||
124 | |||
125 | wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); | ||
126 | wr_regl(port, S3C2410_UFCON, cfg->ufcon); | ||
127 | |||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | static struct s3c24xx_uart_info s3c2440_uart_inf = { | ||
132 | .name = "Samsung S3C2440 UART", | ||
133 | .type = PORT_S3C2440, | ||
134 | .fifosize = 64, | ||
135 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | ||
136 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | ||
137 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | ||
138 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | ||
139 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | ||
140 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | ||
141 | .get_clksrc = s3c2440_serial_getsource, | ||
142 | .set_clksrc = s3c2440_serial_setsource, | ||
143 | .reset_port = s3c2440_serial_resetport, | ||
144 | }; | ||
145 | |||
146 | /* device management */ | ||
147 | |||
148 | static int s3c2440_serial_probe(struct platform_device *dev) | ||
149 | { | ||
150 | dbg("s3c2440_serial_probe: dev=%p\n", dev); | ||
151 | return s3c24xx_serial_probe(dev, &s3c2440_uart_inf); | ||
152 | } | ||
153 | |||
154 | static struct platform_driver s3c2440_serial_drv = { | ||
155 | .probe = s3c2440_serial_probe, | ||
156 | .remove = s3c24xx_serial_remove, | ||
157 | .driver = { | ||
158 | .name = "s3c2440-uart", | ||
159 | .owner = THIS_MODULE, | ||
160 | }, | ||
161 | }; | ||
162 | |||
163 | s3c24xx_console_init(&s3c2440_serial_drv, &s3c2440_uart_inf); | ||
164 | |||
165 | static int __init s3c2440_serial_init(void) | ||
166 | { | ||
167 | return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf); | ||
168 | } | ||
169 | |||
170 | static void __exit s3c2440_serial_exit(void) | ||
171 | { | ||
172 | platform_driver_unregister(&s3c2440_serial_drv); | ||
173 | } | ||
174 | |||
175 | module_init(s3c2440_serial_init); | ||
176 | module_exit(s3c2440_serial_exit); | ||
177 | |||
178 | MODULE_DESCRIPTION("Samsung S3C2440,S3C2442 SoC Serial port driver"); | ||
179 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | ||
180 | MODULE_LICENSE("GPLi v2"); | ||
181 | MODULE_ALIAS("platform:s3c2440-uart"); | ||
diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c new file mode 100644 index 000000000000..4a3ecaa629e6 --- /dev/null +++ b/drivers/serial/samsung.c | |||
@@ -0,0 +1,1317 @@ | |||
1 | /* linux/drivers/serial/samsuing.c | ||
2 | * | ||
3 | * Driver core for Samsung SoC onboard UARTs. | ||
4 | * | ||
5 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | /* Hote on 2410 error handling | ||
14 | * | ||
15 | * The s3c2410 manual has a love/hate affair with the contents of the | ||
16 | * UERSTAT register in the UART blocks, and keeps marking some of the | ||
17 | * error bits as reserved. Having checked with the s3c2410x01, | ||
18 | * it copes with BREAKs properly, so I am happy to ignore the RESERVED | ||
19 | * feature from the latter versions of the manual. | ||
20 | * | ||
21 | * If it becomes aparrent that latter versions of the 2410 remove these | ||
22 | * bits, then action will have to be taken to differentiate the versions | ||
23 | * and change the policy on BREAK | ||
24 | * | ||
25 | * BJD, 04-Nov-2004 | ||
26 | */ | ||
27 | |||
28 | #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | ||
29 | #define SUPPORT_SYSRQ | ||
30 | #endif | ||
31 | |||
32 | #include <linux/module.h> | ||
33 | #include <linux/ioport.h> | ||
34 | #include <linux/io.h> | ||
35 | #include <linux/platform_device.h> | ||
36 | #include <linux/init.h> | ||
37 | #include <linux/sysrq.h> | ||
38 | #include <linux/console.h> | ||
39 | #include <linux/tty.h> | ||
40 | #include <linux/tty_flip.h> | ||
41 | #include <linux/serial_core.h> | ||
42 | #include <linux/serial.h> | ||
43 | #include <linux/delay.h> | ||
44 | #include <linux/clk.h> | ||
45 | |||
46 | #include <asm/irq.h> | ||
47 | |||
48 | #include <asm/hardware.h> | ||
49 | |||
50 | #include <asm/plat-s3c/regs-serial.h> | ||
51 | #include <asm/arch/regs-gpio.h> | ||
52 | |||
53 | #include "samsung.h" | ||
54 | |||
55 | /* UART name and device definitions */ | ||
56 | |||
57 | #define S3C24XX_SERIAL_NAME "ttySAC" | ||
58 | #define S3C24XX_SERIAL_MAJOR 204 | ||
59 | #define S3C24XX_SERIAL_MINOR 64 | ||
60 | |||
61 | /* we can support 3 uarts, but not always use them */ | ||
62 | |||
63 | #ifdef CONFIG_CPU_S3C2400 | ||
64 | #define NR_PORTS (2) | ||
65 | #else | ||
66 | #define NR_PORTS (3) | ||
67 | #endif | ||
68 | |||
69 | /* port irq numbers */ | ||
70 | |||
71 | #define TX_IRQ(port) ((port)->irq + 1) | ||
72 | #define RX_IRQ(port) ((port)->irq) | ||
73 | |||
74 | /* macros to change one thing to another */ | ||
75 | |||
76 | #define tx_enabled(port) ((port)->unused[0]) | ||
77 | #define rx_enabled(port) ((port)->unused[1]) | ||
78 | |||
79 | /* flag to ignore all characters comming in */ | ||
80 | #define RXSTAT_DUMMY_READ (0x10000000) | ||
81 | |||
82 | static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) | ||
83 | { | ||
84 | return container_of(port, struct s3c24xx_uart_port, port); | ||
85 | } | ||
86 | |||
87 | /* translate a port to the device name */ | ||
88 | |||
89 | static inline const char *s3c24xx_serial_portname(struct uart_port *port) | ||
90 | { | ||
91 | return to_platform_device(port->dev)->name; | ||
92 | } | ||
93 | |||
94 | static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) | ||
95 | { | ||
96 | return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE); | ||
97 | } | ||
98 | |||
99 | static void s3c24xx_serial_rx_enable(struct uart_port *port) | ||
100 | { | ||
101 | unsigned long flags; | ||
102 | unsigned int ucon, ufcon; | ||
103 | int count = 10000; | ||
104 | |||
105 | spin_lock_irqsave(&port->lock, flags); | ||
106 | |||
107 | while (--count && !s3c24xx_serial_txempty_nofifo(port)) | ||
108 | udelay(100); | ||
109 | |||
110 | ufcon = rd_regl(port, S3C2410_UFCON); | ||
111 | ufcon |= S3C2410_UFCON_RESETRX; | ||
112 | wr_regl(port, S3C2410_UFCON, ufcon); | ||
113 | |||
114 | ucon = rd_regl(port, S3C2410_UCON); | ||
115 | ucon |= S3C2410_UCON_RXIRQMODE; | ||
116 | wr_regl(port, S3C2410_UCON, ucon); | ||
117 | |||
118 | rx_enabled(port) = 1; | ||
119 | spin_unlock_irqrestore(&port->lock, flags); | ||
120 | } | ||
121 | |||
122 | static void s3c24xx_serial_rx_disable(struct uart_port *port) | ||
123 | { | ||
124 | unsigned long flags; | ||
125 | unsigned int ucon; | ||
126 | |||
127 | spin_lock_irqsave(&port->lock, flags); | ||
128 | |||
129 | ucon = rd_regl(port, S3C2410_UCON); | ||
130 | ucon &= ~S3C2410_UCON_RXIRQMODE; | ||
131 | wr_regl(port, S3C2410_UCON, ucon); | ||
132 | |||
133 | rx_enabled(port) = 0; | ||
134 | spin_unlock_irqrestore(&port->lock, flags); | ||
135 | } | ||
136 | |||
137 | static void s3c24xx_serial_stop_tx(struct uart_port *port) | ||
138 | { | ||
139 | if (tx_enabled(port)) { | ||
140 | disable_irq(TX_IRQ(port)); | ||
141 | tx_enabled(port) = 0; | ||
142 | if (port->flags & UPF_CONS_FLOW) | ||
143 | s3c24xx_serial_rx_enable(port); | ||
144 | } | ||
145 | } | ||
146 | |||
147 | static void s3c24xx_serial_start_tx(struct uart_port *port) | ||
148 | { | ||
149 | if (!tx_enabled(port)) { | ||
150 | if (port->flags & UPF_CONS_FLOW) | ||
151 | s3c24xx_serial_rx_disable(port); | ||
152 | |||
153 | enable_irq(TX_IRQ(port)); | ||
154 | tx_enabled(port) = 1; | ||
155 | } | ||
156 | } | ||
157 | |||
158 | |||
159 | static void s3c24xx_serial_stop_rx(struct uart_port *port) | ||
160 | { | ||
161 | if (rx_enabled(port)) { | ||
162 | dbg("s3c24xx_serial_stop_rx: port=%p\n", port); | ||
163 | disable_irq(RX_IRQ(port)); | ||
164 | rx_enabled(port) = 0; | ||
165 | } | ||
166 | } | ||
167 | |||
168 | static void s3c24xx_serial_enable_ms(struct uart_port *port) | ||
169 | { | ||
170 | } | ||
171 | |||
172 | static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port) | ||
173 | { | ||
174 | return to_ourport(port)->info; | ||
175 | } | ||
176 | |||
177 | static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port) | ||
178 | { | ||
179 | if (port->dev == NULL) | ||
180 | return NULL; | ||
181 | |||
182 | return (struct s3c2410_uartcfg *)port->dev->platform_data; | ||
183 | } | ||
184 | |||
185 | static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport, | ||
186 | unsigned long ufstat) | ||
187 | { | ||
188 | struct s3c24xx_uart_info *info = ourport->info; | ||
189 | |||
190 | if (ufstat & info->rx_fifofull) | ||
191 | return info->fifosize; | ||
192 | |||
193 | return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; | ||
194 | } | ||
195 | |||
196 | |||
197 | /* ? - where has parity gone?? */ | ||
198 | #define S3C2410_UERSTAT_PARITY (0x1000) | ||
199 | |||
200 | static irqreturn_t | ||
201 | s3c24xx_serial_rx_chars(int irq, void *dev_id) | ||
202 | { | ||
203 | struct s3c24xx_uart_port *ourport = dev_id; | ||
204 | struct uart_port *port = &ourport->port; | ||
205 | struct tty_struct *tty = port->info->tty; | ||
206 | unsigned int ufcon, ch, flag, ufstat, uerstat; | ||
207 | int max_count = 64; | ||
208 | |||
209 | while (max_count-- > 0) { | ||
210 | ufcon = rd_regl(port, S3C2410_UFCON); | ||
211 | ufstat = rd_regl(port, S3C2410_UFSTAT); | ||
212 | |||
213 | if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) | ||
214 | break; | ||
215 | |||
216 | uerstat = rd_regl(port, S3C2410_UERSTAT); | ||
217 | ch = rd_regb(port, S3C2410_URXH); | ||
218 | |||
219 | if (port->flags & UPF_CONS_FLOW) { | ||
220 | int txe = s3c24xx_serial_txempty_nofifo(port); | ||
221 | |||
222 | if (rx_enabled(port)) { | ||
223 | if (!txe) { | ||
224 | rx_enabled(port) = 0; | ||
225 | continue; | ||
226 | } | ||
227 | } else { | ||
228 | if (txe) { | ||
229 | ufcon |= S3C2410_UFCON_RESETRX; | ||
230 | wr_regl(port, S3C2410_UFCON, ufcon); | ||
231 | rx_enabled(port) = 1; | ||
232 | goto out; | ||
233 | } | ||
234 | continue; | ||
235 | } | ||
236 | } | ||
237 | |||
238 | /* insert the character into the buffer */ | ||
239 | |||
240 | flag = TTY_NORMAL; | ||
241 | port->icount.rx++; | ||
242 | |||
243 | if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { | ||
244 | dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n", | ||
245 | ch, uerstat); | ||
246 | |||
247 | /* check for break */ | ||
248 | if (uerstat & S3C2410_UERSTAT_BREAK) { | ||
249 | dbg("break!\n"); | ||
250 | port->icount.brk++; | ||
251 | if (uart_handle_break(port)) | ||
252 | goto ignore_char; | ||
253 | } | ||
254 | |||
255 | if (uerstat & S3C2410_UERSTAT_FRAME) | ||
256 | port->icount.frame++; | ||
257 | if (uerstat & S3C2410_UERSTAT_OVERRUN) | ||
258 | port->icount.overrun++; | ||
259 | |||
260 | uerstat &= port->read_status_mask; | ||
261 | |||
262 | if (uerstat & S3C2410_UERSTAT_BREAK) | ||
263 | flag = TTY_BREAK; | ||
264 | else if (uerstat & S3C2410_UERSTAT_PARITY) | ||
265 | flag = TTY_PARITY; | ||
266 | else if (uerstat & (S3C2410_UERSTAT_FRAME | | ||
267 | S3C2410_UERSTAT_OVERRUN)) | ||
268 | flag = TTY_FRAME; | ||
269 | } | ||
270 | |||
271 | if (uart_handle_sysrq_char(port, ch)) | ||
272 | goto ignore_char; | ||
273 | |||
274 | uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, | ||
275 | ch, flag); | ||
276 | |||
277 | ignore_char: | ||
278 | continue; | ||
279 | } | ||
280 | tty_flip_buffer_push(tty); | ||
281 | |||
282 | out: | ||
283 | return IRQ_HANDLED; | ||
284 | } | ||
285 | |||
286 | static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) | ||
287 | { | ||
288 | struct s3c24xx_uart_port *ourport = id; | ||
289 | struct uart_port *port = &ourport->port; | ||
290 | struct circ_buf *xmit = &port->info->xmit; | ||
291 | int count = 256; | ||
292 | |||
293 | if (port->x_char) { | ||
294 | wr_regb(port, S3C2410_UTXH, port->x_char); | ||
295 | port->icount.tx++; | ||
296 | port->x_char = 0; | ||
297 | goto out; | ||
298 | } | ||
299 | |||
300 | /* if there isnt anything more to transmit, or the uart is now | ||
301 | * stopped, disable the uart and exit | ||
302 | */ | ||
303 | |||
304 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | ||
305 | s3c24xx_serial_stop_tx(port); | ||
306 | goto out; | ||
307 | } | ||
308 | |||
309 | /* try and drain the buffer... */ | ||
310 | |||
311 | while (!uart_circ_empty(xmit) && count-- > 0) { | ||
312 | if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) | ||
313 | break; | ||
314 | |||
315 | wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); | ||
316 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | ||
317 | port->icount.tx++; | ||
318 | } | ||
319 | |||
320 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | ||
321 | uart_write_wakeup(port); | ||
322 | |||
323 | if (uart_circ_empty(xmit)) | ||
324 | s3c24xx_serial_stop_tx(port); | ||
325 | |||
326 | out: | ||
327 | return IRQ_HANDLED; | ||
328 | } | ||
329 | |||
330 | static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) | ||
331 | { | ||
332 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
333 | unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); | ||
334 | unsigned long ufcon = rd_regl(port, S3C2410_UFCON); | ||
335 | |||
336 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | ||
337 | if ((ufstat & info->tx_fifomask) != 0 || | ||
338 | (ufstat & info->tx_fifofull)) | ||
339 | return 0; | ||
340 | |||
341 | return 1; | ||
342 | } | ||
343 | |||
344 | return s3c24xx_serial_txempty_nofifo(port); | ||
345 | } | ||
346 | |||
347 | /* no modem control lines */ | ||
348 | static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) | ||
349 | { | ||
350 | unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); | ||
351 | |||
352 | if (umstat & S3C2410_UMSTAT_CTS) | ||
353 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; | ||
354 | else | ||
355 | return TIOCM_CAR | TIOCM_DSR; | ||
356 | } | ||
357 | |||
358 | static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | ||
359 | { | ||
360 | /* todo - possibly remove AFC and do manual CTS */ | ||
361 | } | ||
362 | |||
363 | static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) | ||
364 | { | ||
365 | unsigned long flags; | ||
366 | unsigned int ucon; | ||
367 | |||
368 | spin_lock_irqsave(&port->lock, flags); | ||
369 | |||
370 | ucon = rd_regl(port, S3C2410_UCON); | ||
371 | |||
372 | if (break_state) | ||
373 | ucon |= S3C2410_UCON_SBREAK; | ||
374 | else | ||
375 | ucon &= ~S3C2410_UCON_SBREAK; | ||
376 | |||
377 | wr_regl(port, S3C2410_UCON, ucon); | ||
378 | |||
379 | spin_unlock_irqrestore(&port->lock, flags); | ||
380 | } | ||
381 | |||
382 | static void s3c24xx_serial_shutdown(struct uart_port *port) | ||
383 | { | ||
384 | struct s3c24xx_uart_port *ourport = to_ourport(port); | ||
385 | |||
386 | if (ourport->tx_claimed) { | ||
387 | free_irq(TX_IRQ(port), ourport); | ||
388 | tx_enabled(port) = 0; | ||
389 | ourport->tx_claimed = 0; | ||
390 | } | ||
391 | |||
392 | if (ourport->rx_claimed) { | ||
393 | free_irq(RX_IRQ(port), ourport); | ||
394 | ourport->rx_claimed = 0; | ||
395 | rx_enabled(port) = 0; | ||
396 | } | ||
397 | } | ||
398 | |||
399 | |||
400 | static int s3c24xx_serial_startup(struct uart_port *port) | ||
401 | { | ||
402 | struct s3c24xx_uart_port *ourport = to_ourport(port); | ||
403 | int ret; | ||
404 | |||
405 | dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n", | ||
406 | port->mapbase, port->membase); | ||
407 | |||
408 | rx_enabled(port) = 1; | ||
409 | |||
410 | ret = request_irq(RX_IRQ(port), | ||
411 | s3c24xx_serial_rx_chars, 0, | ||
412 | s3c24xx_serial_portname(port), ourport); | ||
413 | |||
414 | if (ret != 0) { | ||
415 | printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port)); | ||
416 | return ret; | ||
417 | } | ||
418 | |||
419 | ourport->rx_claimed = 1; | ||
420 | |||
421 | dbg("requesting tx irq...\n"); | ||
422 | |||
423 | tx_enabled(port) = 1; | ||
424 | |||
425 | ret = request_irq(TX_IRQ(port), | ||
426 | s3c24xx_serial_tx_chars, 0, | ||
427 | s3c24xx_serial_portname(port), ourport); | ||
428 | |||
429 | if (ret) { | ||
430 | printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port)); | ||
431 | goto err; | ||
432 | } | ||
433 | |||
434 | ourport->tx_claimed = 1; | ||
435 | |||
436 | dbg("s3c24xx_serial_startup ok\n"); | ||
437 | |||
438 | /* the port reset code should have done the correct | ||
439 | * register setup for the port controls */ | ||
440 | |||
441 | return ret; | ||
442 | |||
443 | err: | ||
444 | s3c24xx_serial_shutdown(port); | ||
445 | return ret; | ||
446 | } | ||
447 | |||
448 | /* power power management control */ | ||
449 | |||
450 | static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, | ||
451 | unsigned int old) | ||
452 | { | ||
453 | struct s3c24xx_uart_port *ourport = to_ourport(port); | ||
454 | |||
455 | switch (level) { | ||
456 | case 3: | ||
457 | if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) | ||
458 | clk_disable(ourport->baudclk); | ||
459 | |||
460 | clk_disable(ourport->clk); | ||
461 | break; | ||
462 | |||
463 | case 0: | ||
464 | clk_enable(ourport->clk); | ||
465 | |||
466 | if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL) | ||
467 | clk_enable(ourport->baudclk); | ||
468 | |||
469 | break; | ||
470 | default: | ||
471 | printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level); | ||
472 | } | ||
473 | } | ||
474 | |||
475 | /* baud rate calculation | ||
476 | * | ||
477 | * The UARTs on the S3C2410/S3C2440 can take their clocks from a number | ||
478 | * of different sources, including the peripheral clock ("pclk") and an | ||
479 | * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") | ||
480 | * with a programmable extra divisor. | ||
481 | * | ||
482 | * The following code goes through the clock sources, and calculates the | ||
483 | * baud clocks (and the resultant actual baud rates) and then tries to | ||
484 | * pick the closest one and select that. | ||
485 | * | ||
486 | */ | ||
487 | |||
488 | |||
489 | #define MAX_CLKS (8) | ||
490 | |||
491 | static struct s3c24xx_uart_clksrc tmp_clksrc = { | ||
492 | .name = "pclk", | ||
493 | .min_baud = 0, | ||
494 | .max_baud = 0, | ||
495 | .divisor = 1, | ||
496 | }; | ||
497 | |||
498 | static inline int | ||
499 | s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c) | ||
500 | { | ||
501 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
502 | |||
503 | return (info->get_clksrc)(port, c); | ||
504 | } | ||
505 | |||
506 | static inline int | ||
507 | s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c) | ||
508 | { | ||
509 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
510 | |||
511 | return (info->set_clksrc)(port, c); | ||
512 | } | ||
513 | |||
514 | struct baud_calc { | ||
515 | struct s3c24xx_uart_clksrc *clksrc; | ||
516 | unsigned int calc; | ||
517 | unsigned int quot; | ||
518 | struct clk *src; | ||
519 | }; | ||
520 | |||
521 | static int s3c24xx_serial_calcbaud(struct baud_calc *calc, | ||
522 | struct uart_port *port, | ||
523 | struct s3c24xx_uart_clksrc *clksrc, | ||
524 | unsigned int baud) | ||
525 | { | ||
526 | unsigned long rate; | ||
527 | |||
528 | calc->src = clk_get(port->dev, clksrc->name); | ||
529 | if (calc->src == NULL || IS_ERR(calc->src)) | ||
530 | return 0; | ||
531 | |||
532 | rate = clk_get_rate(calc->src); | ||
533 | rate /= clksrc->divisor; | ||
534 | |||
535 | calc->clksrc = clksrc; | ||
536 | calc->quot = (rate + (8 * baud)) / (16 * baud); | ||
537 | calc->calc = (rate / (calc->quot * 16)); | ||
538 | |||
539 | calc->quot--; | ||
540 | return 1; | ||
541 | } | ||
542 | |||
543 | static unsigned int s3c24xx_serial_getclk(struct uart_port *port, | ||
544 | struct s3c24xx_uart_clksrc **clksrc, | ||
545 | struct clk **clk, | ||
546 | unsigned int baud) | ||
547 | { | ||
548 | struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); | ||
549 | struct s3c24xx_uart_clksrc *clkp; | ||
550 | struct baud_calc res[MAX_CLKS]; | ||
551 | struct baud_calc *resptr, *best, *sptr; | ||
552 | int i; | ||
553 | |||
554 | clkp = cfg->clocks; | ||
555 | best = NULL; | ||
556 | |||
557 | if (cfg->clocks_size < 2) { | ||
558 | if (cfg->clocks_size == 0) | ||
559 | clkp = &tmp_clksrc; | ||
560 | |||
561 | /* check to see if we're sourcing fclk, and if so we're | ||
562 | * going to have to update the clock source | ||
563 | */ | ||
564 | |||
565 | if (strcmp(clkp->name, "fclk") == 0) { | ||
566 | struct s3c24xx_uart_clksrc src; | ||
567 | |||
568 | s3c24xx_serial_getsource(port, &src); | ||
569 | |||
570 | /* check that the port already using fclk, and if | ||
571 | * not, then re-select fclk | ||
572 | */ | ||
573 | |||
574 | if (strcmp(src.name, clkp->name) == 0) { | ||
575 | s3c24xx_serial_setsource(port, clkp); | ||
576 | s3c24xx_serial_getsource(port, &src); | ||
577 | } | ||
578 | |||
579 | clkp->divisor = src.divisor; | ||
580 | } | ||
581 | |||
582 | s3c24xx_serial_calcbaud(res, port, clkp, baud); | ||
583 | best = res; | ||
584 | resptr = best + 1; | ||
585 | } else { | ||
586 | resptr = res; | ||
587 | |||
588 | for (i = 0; i < cfg->clocks_size; i++, clkp++) { | ||
589 | if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud)) | ||
590 | resptr++; | ||
591 | } | ||
592 | } | ||
593 | |||
594 | /* ok, we now need to select the best clock we found */ | ||
595 | |||
596 | if (!best) { | ||
597 | unsigned int deviation = (1<<30)|((1<<30)-1); | ||
598 | int calc_deviation; | ||
599 | |||
600 | for (sptr = res; sptr < resptr; sptr++) { | ||
601 | calc_deviation = baud - sptr->calc; | ||
602 | if (calc_deviation < 0) | ||
603 | calc_deviation = -calc_deviation; | ||
604 | |||
605 | if (calc_deviation < deviation) { | ||
606 | best = sptr; | ||
607 | deviation = calc_deviation; | ||
608 | } | ||
609 | } | ||
610 | } | ||
611 | |||
612 | /* store results to pass back */ | ||
613 | |||
614 | *clksrc = best->clksrc; | ||
615 | *clk = best->src; | ||
616 | |||
617 | return best->quot; | ||
618 | } | ||
619 | |||
620 | static void s3c24xx_serial_set_termios(struct uart_port *port, | ||
621 | struct ktermios *termios, | ||
622 | struct ktermios *old) | ||
623 | { | ||
624 | struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); | ||
625 | struct s3c24xx_uart_port *ourport = to_ourport(port); | ||
626 | struct s3c24xx_uart_clksrc *clksrc = NULL; | ||
627 | struct clk *clk = NULL; | ||
628 | unsigned long flags; | ||
629 | unsigned int baud, quot; | ||
630 | unsigned int ulcon; | ||
631 | unsigned int umcon; | ||
632 | |||
633 | /* | ||
634 | * We don't support modem control lines. | ||
635 | */ | ||
636 | termios->c_cflag &= ~(HUPCL | CMSPAR); | ||
637 | termios->c_cflag |= CLOCAL; | ||
638 | |||
639 | /* | ||
640 | * Ask the core to calculate the divisor for us. | ||
641 | */ | ||
642 | |||
643 | baud = uart_get_baud_rate(port, termios, old, 0, 115200*8); | ||
644 | |||
645 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) | ||
646 | quot = port->custom_divisor; | ||
647 | else | ||
648 | quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud); | ||
649 | |||
650 | /* check to see if we need to change clock source */ | ||
651 | |||
652 | if (ourport->clksrc != clksrc || ourport->baudclk != clk) { | ||
653 | s3c24xx_serial_setsource(port, clksrc); | ||
654 | |||
655 | if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) { | ||
656 | clk_disable(ourport->baudclk); | ||
657 | ourport->baudclk = NULL; | ||
658 | } | ||
659 | |||
660 | clk_enable(clk); | ||
661 | |||
662 | ourport->clksrc = clksrc; | ||
663 | ourport->baudclk = clk; | ||
664 | } | ||
665 | |||
666 | switch (termios->c_cflag & CSIZE) { | ||
667 | case CS5: | ||
668 | dbg("config: 5bits/char\n"); | ||
669 | ulcon = S3C2410_LCON_CS5; | ||
670 | break; | ||
671 | case CS6: | ||
672 | dbg("config: 6bits/char\n"); | ||
673 | ulcon = S3C2410_LCON_CS6; | ||
674 | break; | ||
675 | case CS7: | ||
676 | dbg("config: 7bits/char\n"); | ||
677 | ulcon = S3C2410_LCON_CS7; | ||
678 | break; | ||
679 | case CS8: | ||
680 | default: | ||
681 | dbg("config: 8bits/char\n"); | ||
682 | ulcon = S3C2410_LCON_CS8; | ||
683 | break; | ||
684 | } | ||
685 | |||
686 | /* preserve original lcon IR settings */ | ||
687 | ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); | ||
688 | |||
689 | if (termios->c_cflag & CSTOPB) | ||
690 | ulcon |= S3C2410_LCON_STOPB; | ||
691 | |||
692 | umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0; | ||
693 | |||
694 | if (termios->c_cflag & PARENB) { | ||
695 | if (termios->c_cflag & PARODD) | ||
696 | ulcon |= S3C2410_LCON_PODD; | ||
697 | else | ||
698 | ulcon |= S3C2410_LCON_PEVEN; | ||
699 | } else { | ||
700 | ulcon |= S3C2410_LCON_PNONE; | ||
701 | } | ||
702 | |||
703 | spin_lock_irqsave(&port->lock, flags); | ||
704 | |||
705 | dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot); | ||
706 | |||
707 | wr_regl(port, S3C2410_ULCON, ulcon); | ||
708 | wr_regl(port, S3C2410_UBRDIV, quot); | ||
709 | wr_regl(port, S3C2410_UMCON, umcon); | ||
710 | |||
711 | dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", | ||
712 | rd_regl(port, S3C2410_ULCON), | ||
713 | rd_regl(port, S3C2410_UCON), | ||
714 | rd_regl(port, S3C2410_UFCON)); | ||
715 | |||
716 | /* | ||
717 | * Update the per-port timeout. | ||
718 | */ | ||
719 | uart_update_timeout(port, termios->c_cflag, baud); | ||
720 | |||
721 | /* | ||
722 | * Which character status flags are we interested in? | ||
723 | */ | ||
724 | port->read_status_mask = S3C2410_UERSTAT_OVERRUN; | ||
725 | if (termios->c_iflag & INPCK) | ||
726 | port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY; | ||
727 | |||
728 | /* | ||
729 | * Which character status flags should we ignore? | ||
730 | */ | ||
731 | port->ignore_status_mask = 0; | ||
732 | if (termios->c_iflag & IGNPAR) | ||
733 | port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; | ||
734 | if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) | ||
735 | port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; | ||
736 | |||
737 | /* | ||
738 | * Ignore all characters if CREAD is not set. | ||
739 | */ | ||
740 | if ((termios->c_cflag & CREAD) == 0) | ||
741 | port->ignore_status_mask |= RXSTAT_DUMMY_READ; | ||
742 | |||
743 | spin_unlock_irqrestore(&port->lock, flags); | ||
744 | } | ||
745 | |||
746 | static const char *s3c24xx_serial_type(struct uart_port *port) | ||
747 | { | ||
748 | switch (port->type) { | ||
749 | case PORT_S3C2410: | ||
750 | return "S3C2410"; | ||
751 | case PORT_S3C2440: | ||
752 | return "S3C2440"; | ||
753 | case PORT_S3C2412: | ||
754 | return "S3C2412"; | ||
755 | default: | ||
756 | return NULL; | ||
757 | } | ||
758 | } | ||
759 | |||
760 | #define MAP_SIZE (0x100) | ||
761 | |||
762 | static void s3c24xx_serial_release_port(struct uart_port *port) | ||
763 | { | ||
764 | release_mem_region(port->mapbase, MAP_SIZE); | ||
765 | } | ||
766 | |||
767 | static int s3c24xx_serial_request_port(struct uart_port *port) | ||
768 | { | ||
769 | const char *name = s3c24xx_serial_portname(port); | ||
770 | return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY; | ||
771 | } | ||
772 | |||
773 | static void s3c24xx_serial_config_port(struct uart_port *port, int flags) | ||
774 | { | ||
775 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
776 | |||
777 | if (flags & UART_CONFIG_TYPE && | ||
778 | s3c24xx_serial_request_port(port) == 0) | ||
779 | port->type = info->type; | ||
780 | } | ||
781 | |||
782 | /* | ||
783 | * verify the new serial_struct (for TIOCSSERIAL). | ||
784 | */ | ||
785 | static int | ||
786 | s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | ||
787 | { | ||
788 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
789 | |||
790 | if (ser->type != PORT_UNKNOWN && ser->type != info->type) | ||
791 | return -EINVAL; | ||
792 | |||
793 | return 0; | ||
794 | } | ||
795 | |||
796 | |||
797 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE | ||
798 | |||
799 | static struct console s3c24xx_serial_console; | ||
800 | |||
801 | #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console | ||
802 | #else | ||
803 | #define S3C24XX_SERIAL_CONSOLE NULL | ||
804 | #endif | ||
805 | |||
806 | static struct uart_ops s3c24xx_serial_ops = { | ||
807 | .pm = s3c24xx_serial_pm, | ||
808 | .tx_empty = s3c24xx_serial_tx_empty, | ||
809 | .get_mctrl = s3c24xx_serial_get_mctrl, | ||
810 | .set_mctrl = s3c24xx_serial_set_mctrl, | ||
811 | .stop_tx = s3c24xx_serial_stop_tx, | ||
812 | .start_tx = s3c24xx_serial_start_tx, | ||
813 | .stop_rx = s3c24xx_serial_stop_rx, | ||
814 | .enable_ms = s3c24xx_serial_enable_ms, | ||
815 | .break_ctl = s3c24xx_serial_break_ctl, | ||
816 | .startup = s3c24xx_serial_startup, | ||
817 | .shutdown = s3c24xx_serial_shutdown, | ||
818 | .set_termios = s3c24xx_serial_set_termios, | ||
819 | .type = s3c24xx_serial_type, | ||
820 | .release_port = s3c24xx_serial_release_port, | ||
821 | .request_port = s3c24xx_serial_request_port, | ||
822 | .config_port = s3c24xx_serial_config_port, | ||
823 | .verify_port = s3c24xx_serial_verify_port, | ||
824 | }; | ||
825 | |||
826 | |||
827 | static struct uart_driver s3c24xx_uart_drv = { | ||
828 | .owner = THIS_MODULE, | ||
829 | .dev_name = "s3c2410_serial", | ||
830 | .nr = 3, | ||
831 | .cons = S3C24XX_SERIAL_CONSOLE, | ||
832 | .driver_name = S3C24XX_SERIAL_NAME, | ||
833 | .major = S3C24XX_SERIAL_MAJOR, | ||
834 | .minor = S3C24XX_SERIAL_MINOR, | ||
835 | }; | ||
836 | |||
837 | static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = { | ||
838 | [0] = { | ||
839 | .port = { | ||
840 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock), | ||
841 | .iotype = UPIO_MEM, | ||
842 | .irq = IRQ_S3CUART_RX0, | ||
843 | .uartclk = 0, | ||
844 | .fifosize = 16, | ||
845 | .ops = &s3c24xx_serial_ops, | ||
846 | .flags = UPF_BOOT_AUTOCONF, | ||
847 | .line = 0, | ||
848 | } | ||
849 | }, | ||
850 | [1] = { | ||
851 | .port = { | ||
852 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock), | ||
853 | .iotype = UPIO_MEM, | ||
854 | .irq = IRQ_S3CUART_RX1, | ||
855 | .uartclk = 0, | ||
856 | .fifosize = 16, | ||
857 | .ops = &s3c24xx_serial_ops, | ||
858 | .flags = UPF_BOOT_AUTOCONF, | ||
859 | .line = 1, | ||
860 | } | ||
861 | }, | ||
862 | #if NR_PORTS > 2 | ||
863 | |||
864 | [2] = { | ||
865 | .port = { | ||
866 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock), | ||
867 | .iotype = UPIO_MEM, | ||
868 | .irq = IRQ_S3CUART_RX2, | ||
869 | .uartclk = 0, | ||
870 | .fifosize = 16, | ||
871 | .ops = &s3c24xx_serial_ops, | ||
872 | .flags = UPF_BOOT_AUTOCONF, | ||
873 | .line = 2, | ||
874 | } | ||
875 | } | ||
876 | #endif | ||
877 | }; | ||
878 | |||
879 | /* s3c24xx_serial_resetport | ||
880 | * | ||
881 | * wrapper to call the specific reset for this port (reset the fifos | ||
882 | * and the settings) | ||
883 | */ | ||
884 | |||
885 | static inline int s3c24xx_serial_resetport(struct uart_port *port, | ||
886 | struct s3c2410_uartcfg *cfg) | ||
887 | { | ||
888 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
889 | |||
890 | return (info->reset_port)(port, cfg); | ||
891 | } | ||
892 | |||
893 | /* s3c24xx_serial_init_port | ||
894 | * | ||
895 | * initialise a single serial port from the platform device given | ||
896 | */ | ||
897 | |||
898 | static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, | ||
899 | struct s3c24xx_uart_info *info, | ||
900 | struct platform_device *platdev) | ||
901 | { | ||
902 | struct uart_port *port = &ourport->port; | ||
903 | struct s3c2410_uartcfg *cfg; | ||
904 | struct resource *res; | ||
905 | int ret; | ||
906 | |||
907 | dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev); | ||
908 | |||
909 | if (platdev == NULL) | ||
910 | return -ENODEV; | ||
911 | |||
912 | cfg = s3c24xx_dev_to_cfg(&platdev->dev); | ||
913 | |||
914 | if (port->mapbase != 0) | ||
915 | return 0; | ||
916 | |||
917 | if (cfg->hwport > 3) | ||
918 | return -EINVAL; | ||
919 | |||
920 | /* setup info for port */ | ||
921 | port->dev = &platdev->dev; | ||
922 | ourport->info = info; | ||
923 | |||
924 | /* copy the info in from provided structure */ | ||
925 | ourport->port.fifosize = info->fifosize; | ||
926 | |||
927 | dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport); | ||
928 | |||
929 | port->uartclk = 1; | ||
930 | |||
931 | if (cfg->uart_flags & UPF_CONS_FLOW) { | ||
932 | dbg("s3c24xx_serial_init_port: enabling flow control\n"); | ||
933 | port->flags |= UPF_CONS_FLOW; | ||
934 | } | ||
935 | |||
936 | /* sort our the physical and virtual addresses for each UART */ | ||
937 | |||
938 | res = platform_get_resource(platdev, IORESOURCE_MEM, 0); | ||
939 | if (res == NULL) { | ||
940 | printk(KERN_ERR "failed to find memory resource for uart\n"); | ||
941 | return -EINVAL; | ||
942 | } | ||
943 | |||
944 | dbg("resource %p (%lx..%lx)\n", res, res->start, res->end); | ||
945 | |||
946 | port->mapbase = res->start; | ||
947 | port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART); | ||
948 | ret = platform_get_irq(platdev, 0); | ||
949 | if (ret < 0) | ||
950 | port->irq = 0; | ||
951 | else | ||
952 | port->irq = ret; | ||
953 | |||
954 | ourport->clk = clk_get(&platdev->dev, "uart"); | ||
955 | |||
956 | dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n", | ||
957 | port->mapbase, port->membase, port->irq, port->uartclk); | ||
958 | |||
959 | /* reset the fifos (and setup the uart) */ | ||
960 | s3c24xx_serial_resetport(port, cfg); | ||
961 | return 0; | ||
962 | } | ||
963 | |||
964 | static ssize_t s3c24xx_serial_show_clksrc(struct device *dev, | ||
965 | struct device_attribute *attr, | ||
966 | char *buf) | ||
967 | { | ||
968 | struct uart_port *port = s3c24xx_dev_to_port(dev); | ||
969 | struct s3c24xx_uart_port *ourport = to_ourport(port); | ||
970 | |||
971 | return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->clksrc->name); | ||
972 | } | ||
973 | |||
974 | static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL); | ||
975 | |||
976 | /* Device driver serial port probe */ | ||
977 | |||
978 | static int probe_index; | ||
979 | |||
980 | int s3c24xx_serial_probe(struct platform_device *dev, | ||
981 | struct s3c24xx_uart_info *info) | ||
982 | { | ||
983 | struct s3c24xx_uart_port *ourport; | ||
984 | int ret; | ||
985 | |||
986 | dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index); | ||
987 | |||
988 | ourport = &s3c24xx_serial_ports[probe_index]; | ||
989 | probe_index++; | ||
990 | |||
991 | dbg("%s: initialising port %p...\n", __func__, ourport); | ||
992 | |||
993 | ret = s3c24xx_serial_init_port(ourport, info, dev); | ||
994 | if (ret < 0) | ||
995 | goto probe_err; | ||
996 | |||
997 | dbg("%s: adding port\n", __func__); | ||
998 | uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); | ||
999 | platform_set_drvdata(dev, &ourport->port); | ||
1000 | |||
1001 | ret = device_create_file(&dev->dev, &dev_attr_clock_source); | ||
1002 | if (ret < 0) | ||
1003 | printk(KERN_ERR "%s: failed to add clksrc attr.\n", __func__); | ||
1004 | |||
1005 | return 0; | ||
1006 | |||
1007 | probe_err: | ||
1008 | return ret; | ||
1009 | } | ||
1010 | |||
1011 | EXPORT_SYMBOL_GPL(s3c24xx_serial_probe); | ||
1012 | |||
1013 | int s3c24xx_serial_remove(struct platform_device *dev) | ||
1014 | { | ||
1015 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | ||
1016 | |||
1017 | if (port) { | ||
1018 | device_remove_file(&dev->dev, &dev_attr_clock_source); | ||
1019 | uart_remove_one_port(&s3c24xx_uart_drv, port); | ||
1020 | } | ||
1021 | |||
1022 | return 0; | ||
1023 | } | ||
1024 | |||
1025 | EXPORT_SYMBOL_GPL(s3c24xx_serial_remove); | ||
1026 | |||
1027 | /* UART power management code */ | ||
1028 | |||
1029 | #ifdef CONFIG_PM | ||
1030 | |||
1031 | static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state) | ||
1032 | { | ||
1033 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | ||
1034 | |||
1035 | if (port) | ||
1036 | uart_suspend_port(&s3c24xx_uart_drv, port); | ||
1037 | |||
1038 | return 0; | ||
1039 | } | ||
1040 | |||
1041 | static int s3c24xx_serial_resume(struct platform_device *dev) | ||
1042 | { | ||
1043 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | ||
1044 | struct s3c24xx_uart_port *ourport = to_ourport(port); | ||
1045 | |||
1046 | if (port) { | ||
1047 | clk_enable(ourport->clk); | ||
1048 | s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); | ||
1049 | clk_disable(ourport->clk); | ||
1050 | |||
1051 | uart_resume_port(&s3c24xx_uart_drv, port); | ||
1052 | } | ||
1053 | |||
1054 | return 0; | ||
1055 | } | ||
1056 | #endif | ||
1057 | |||
1058 | int s3c24xx_serial_init(struct platform_driver *drv, | ||
1059 | struct s3c24xx_uart_info *info) | ||
1060 | { | ||
1061 | dbg("s3c24xx_serial_init(%p,%p)\n", drv, info); | ||
1062 | |||
1063 | #ifdef CONFIG_PM | ||
1064 | drv->suspend = s3c24xx_serial_suspend; | ||
1065 | drv->resume = s3c24xx_serial_resume; | ||
1066 | #endif | ||
1067 | |||
1068 | return platform_driver_register(drv); | ||
1069 | } | ||
1070 | |||
1071 | EXPORT_SYMBOL_GPL(s3c24xx_serial_init); | ||
1072 | |||
1073 | /* module initialisation code */ | ||
1074 | |||
1075 | static int __init s3c24xx_serial_modinit(void) | ||
1076 | { | ||
1077 | int ret; | ||
1078 | |||
1079 | ret = uart_register_driver(&s3c24xx_uart_drv); | ||
1080 | if (ret < 0) { | ||
1081 | printk(KERN_ERR "failed to register UART driver\n"); | ||
1082 | return -1; | ||
1083 | } | ||
1084 | |||
1085 | return 0; | ||
1086 | } | ||
1087 | |||
1088 | static void __exit s3c24xx_serial_modexit(void) | ||
1089 | { | ||
1090 | uart_unregister_driver(&s3c24xx_uart_drv); | ||
1091 | } | ||
1092 | |||
1093 | module_init(s3c24xx_serial_modinit); | ||
1094 | module_exit(s3c24xx_serial_modexit); | ||
1095 | |||
1096 | /* Console code */ | ||
1097 | |||
1098 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE | ||
1099 | |||
1100 | static struct uart_port *cons_uart; | ||
1101 | |||
1102 | static int | ||
1103 | s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) | ||
1104 | { | ||
1105 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | ||
1106 | unsigned long ufstat, utrstat; | ||
1107 | |||
1108 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | ||
1109 | /* fifo mode - check ammount of data in fifo registers... */ | ||
1110 | |||
1111 | ufstat = rd_regl(port, S3C2410_UFSTAT); | ||
1112 | return (ufstat & info->tx_fifofull) ? 0 : 1; | ||
1113 | } | ||
1114 | |||
1115 | /* in non-fifo mode, we go and use the tx buffer empty */ | ||
1116 | |||
1117 | utrstat = rd_regl(port, S3C2410_UTRSTAT); | ||
1118 | return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0; | ||
1119 | } | ||
1120 | |||
1121 | static void | ||
1122 | s3c24xx_serial_console_putchar(struct uart_port *port, int ch) | ||
1123 | { | ||
1124 | unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON); | ||
1125 | while (!s3c24xx_serial_console_txrdy(port, ufcon)) | ||
1126 | barrier(); | ||
1127 | wr_regb(cons_uart, S3C2410_UTXH, ch); | ||
1128 | } | ||
1129 | |||
1130 | static void | ||
1131 | s3c24xx_serial_console_write(struct console *co, const char *s, | ||
1132 | unsigned int count) | ||
1133 | { | ||
1134 | uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); | ||
1135 | } | ||
1136 | |||
1137 | static void __init | ||
1138 | s3c24xx_serial_get_options(struct uart_port *port, int *baud, | ||
1139 | int *parity, int *bits) | ||
1140 | { | ||
1141 | struct s3c24xx_uart_clksrc clksrc; | ||
1142 | struct clk *clk; | ||
1143 | unsigned int ulcon; | ||
1144 | unsigned int ucon; | ||
1145 | unsigned int ubrdiv; | ||
1146 | unsigned long rate; | ||
1147 | |||
1148 | ulcon = rd_regl(port, S3C2410_ULCON); | ||
1149 | ucon = rd_regl(port, S3C2410_UCON); | ||
1150 | ubrdiv = rd_regl(port, S3C2410_UBRDIV); | ||
1151 | |||
1152 | dbg("s3c24xx_serial_get_options: port=%p\n" | ||
1153 | "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n", | ||
1154 | port, ulcon, ucon, ubrdiv); | ||
1155 | |||
1156 | if ((ucon & 0xf) != 0) { | ||
1157 | /* consider the serial port configured if the tx/rx mode set */ | ||
1158 | |||
1159 | switch (ulcon & S3C2410_LCON_CSMASK) { | ||
1160 | case S3C2410_LCON_CS5: | ||
1161 | *bits = 5; | ||
1162 | break; | ||
1163 | case S3C2410_LCON_CS6: | ||
1164 | *bits = 6; | ||
1165 | break; | ||
1166 | case S3C2410_LCON_CS7: | ||
1167 | *bits = 7; | ||
1168 | break; | ||
1169 | default: | ||
1170 | case S3C2410_LCON_CS8: | ||
1171 | *bits = 8; | ||
1172 | break; | ||
1173 | } | ||
1174 | |||
1175 | switch (ulcon & S3C2410_LCON_PMASK) { | ||
1176 | case S3C2410_LCON_PEVEN: | ||
1177 | *parity = 'e'; | ||
1178 | break; | ||
1179 | |||
1180 | case S3C2410_LCON_PODD: | ||
1181 | *parity = 'o'; | ||
1182 | break; | ||
1183 | |||
1184 | case S3C2410_LCON_PNONE: | ||
1185 | default: | ||
1186 | *parity = 'n'; | ||
1187 | } | ||
1188 | |||
1189 | /* now calculate the baud rate */ | ||
1190 | |||
1191 | s3c24xx_serial_getsource(port, &clksrc); | ||
1192 | |||
1193 | clk = clk_get(port->dev, clksrc.name); | ||
1194 | if (!IS_ERR(clk) && clk != NULL) | ||
1195 | rate = clk_get_rate(clk) / clksrc.divisor; | ||
1196 | else | ||
1197 | rate = 1; | ||
1198 | |||
1199 | |||
1200 | *baud = rate / (16 * (ubrdiv + 1)); | ||
1201 | dbg("calculated baud %d\n", *baud); | ||
1202 | } | ||
1203 | |||
1204 | } | ||
1205 | |||
1206 | /* s3c24xx_serial_init_ports | ||
1207 | * | ||
1208 | * initialise the serial ports from the machine provided initialisation | ||
1209 | * data. | ||
1210 | */ | ||
1211 | |||
1212 | static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info) | ||
1213 | { | ||
1214 | struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports; | ||
1215 | struct platform_device **platdev_ptr; | ||
1216 | int i; | ||
1217 | |||
1218 | dbg("s3c24xx_serial_init_ports: initialising ports...\n"); | ||
1219 | |||
1220 | platdev_ptr = s3c24xx_uart_devs; | ||
1221 | |||
1222 | for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) { | ||
1223 | s3c24xx_serial_init_port(ptr, info, *platdev_ptr); | ||
1224 | } | ||
1225 | |||
1226 | return 0; | ||
1227 | } | ||
1228 | |||
1229 | static int __init | ||
1230 | s3c24xx_serial_console_setup(struct console *co, char *options) | ||
1231 | { | ||
1232 | struct uart_port *port; | ||
1233 | int baud = 9600; | ||
1234 | int bits = 8; | ||
1235 | int parity = 'n'; | ||
1236 | int flow = 'n'; | ||
1237 | |||
1238 | dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n", | ||
1239 | co, co->index, options); | ||
1240 | |||
1241 | /* is this a valid port */ | ||
1242 | |||
1243 | if (co->index == -1 || co->index >= NR_PORTS) | ||
1244 | co->index = 0; | ||
1245 | |||
1246 | port = &s3c24xx_serial_ports[co->index].port; | ||
1247 | |||
1248 | /* is the port configured? */ | ||
1249 | |||
1250 | if (port->mapbase == 0x0) { | ||
1251 | co->index = 0; | ||
1252 | port = &s3c24xx_serial_ports[co->index].port; | ||
1253 | } | ||
1254 | |||
1255 | cons_uart = port; | ||
1256 | |||
1257 | dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index); | ||
1258 | |||
1259 | /* | ||
1260 | * Check whether an invalid uart number has been specified, and | ||
1261 | * if so, search for the first available port that does have | ||
1262 | * console support. | ||
1263 | */ | ||
1264 | if (options) | ||
1265 | uart_parse_options(options, &baud, &parity, &bits, &flow); | ||
1266 | else | ||
1267 | s3c24xx_serial_get_options(port, &baud, &parity, &bits); | ||
1268 | |||
1269 | dbg("s3c24xx_serial_console_setup: baud %d\n", baud); | ||
1270 | |||
1271 | return uart_set_options(port, co, baud, parity, bits, flow); | ||
1272 | } | ||
1273 | |||
1274 | /* s3c24xx_serial_initconsole | ||
1275 | * | ||
1276 | * initialise the console from one of the uart drivers | ||
1277 | */ | ||
1278 | |||
1279 | static struct console s3c24xx_serial_console = { | ||
1280 | .name = S3C24XX_SERIAL_NAME, | ||
1281 | .device = uart_console_device, | ||
1282 | .flags = CON_PRINTBUFFER, | ||
1283 | .index = -1, | ||
1284 | .write = s3c24xx_serial_console_write, | ||
1285 | .setup = s3c24xx_serial_console_setup | ||
1286 | }; | ||
1287 | |||
1288 | int s3c24xx_serial_initconsole(struct platform_driver *drv, | ||
1289 | struct s3c24xx_uart_info *info) | ||
1290 | |||
1291 | { | ||
1292 | struct platform_device *dev = s3c24xx_uart_devs[0]; | ||
1293 | |||
1294 | dbg("s3c24xx_serial_initconsole\n"); | ||
1295 | |||
1296 | /* select driver based on the cpu */ | ||
1297 | |||
1298 | if (dev == NULL) { | ||
1299 | printk(KERN_ERR "s3c24xx: no devices for console init\n"); | ||
1300 | return 0; | ||
1301 | } | ||
1302 | |||
1303 | if (strcmp(dev->name, drv->driver.name) != 0) | ||
1304 | return 0; | ||
1305 | |||
1306 | s3c24xx_serial_console.data = &s3c24xx_uart_drv; | ||
1307 | s3c24xx_serial_init_ports(info); | ||
1308 | |||
1309 | register_console(&s3c24xx_serial_console); | ||
1310 | return 0; | ||
1311 | } | ||
1312 | |||
1313 | #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ | ||
1314 | |||
1315 | MODULE_DESCRIPTION("Samsung SoC Serial port driver"); | ||
1316 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | ||
1317 | MODULE_LICENSE("GPL v2"); | ||
diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h new file mode 100644 index 000000000000..5c92ebbe7d9e --- /dev/null +++ b/drivers/serial/samsung.h | |||
@@ -0,0 +1,102 @@ | |||
1 | /* linux/drivers/serial/samsung.h | ||
2 | * | ||
3 | * Driver for Samsung SoC onboard UARTs. | ||
4 | * | ||
5 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | struct s3c24xx_uart_info { | ||
14 | char *name; | ||
15 | unsigned int type; | ||
16 | unsigned int fifosize; | ||
17 | unsigned long rx_fifomask; | ||
18 | unsigned long rx_fifoshift; | ||
19 | unsigned long rx_fifofull; | ||
20 | unsigned long tx_fifomask; | ||
21 | unsigned long tx_fifoshift; | ||
22 | unsigned long tx_fifofull; | ||
23 | |||
24 | /* clock source control */ | ||
25 | |||
26 | int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk); | ||
27 | int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk); | ||
28 | |||
29 | /* uart controls */ | ||
30 | int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *); | ||
31 | }; | ||
32 | |||
33 | struct s3c24xx_uart_port { | ||
34 | unsigned char rx_claimed; | ||
35 | unsigned char tx_claimed; | ||
36 | |||
37 | struct s3c24xx_uart_info *info; | ||
38 | struct s3c24xx_uart_clksrc *clksrc; | ||
39 | struct clk *clk; | ||
40 | struct clk *baudclk; | ||
41 | struct uart_port port; | ||
42 | }; | ||
43 | |||
44 | /* conversion functions */ | ||
45 | |||
46 | #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev) | ||
47 | #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data) | ||
48 | |||
49 | /* register access controls */ | ||
50 | |||
51 | #define portaddr(port, reg) ((port)->membase + (reg)) | ||
52 | |||
53 | #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg))) | ||
54 | #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg))) | ||
55 | |||
56 | #define wr_regb(port, reg, val) __raw_writeb(val, portaddr(port, reg)) | ||
57 | #define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg)) | ||
58 | |||
59 | extern int s3c24xx_serial_probe(struct platform_device *dev, | ||
60 | struct s3c24xx_uart_info *uart); | ||
61 | |||
62 | extern int s3c24xx_serial_remove(struct platform_device *dev); | ||
63 | |||
64 | extern int s3c24xx_serial_initconsole(struct platform_driver *drv, | ||
65 | struct s3c24xx_uart_info *uart); | ||
66 | |||
67 | extern int s3c24xx_serial_init(struct platform_driver *drv, | ||
68 | struct s3c24xx_uart_info *info); | ||
69 | |||
70 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE | ||
71 | |||
72 | #define s3c24xx_console_init(__drv, __inf) \ | ||
73 | static int __init s3c_serial_console_init(void) \ | ||
74 | { \ | ||
75 | return s3c24xx_serial_initconsole(__drv, __inf); \ | ||
76 | } \ | ||
77 | \ | ||
78 | console_initcall(s3c_serial_console_init) | ||
79 | |||
80 | #else | ||
81 | #define s3c24xx_console_init(drv, inf) extern void no_console(void) | ||
82 | #endif | ||
83 | |||
84 | #ifdef CONFIG_SERIAL_SAMSUNG_DEBUG | ||
85 | |||
86 | extern void printascii(const char *); | ||
87 | |||
88 | static void dbg(const char *fmt, ...) | ||
89 | { | ||
90 | va_list va; | ||
91 | char buff[256]; | ||
92 | |||
93 | va_start(va, fmt); | ||
94 | vsprintf(buff, fmt, va); | ||
95 | va_end(va); | ||
96 | |||
97 | printascii(buff); | ||
98 | } | ||
99 | |||
100 | #else | ||
101 | #define dbg(x...) do { } while (0) | ||
102 | #endif | ||
diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c index c730d05bfeb6..54ac7bea5f8c 100644 --- a/drivers/spi/spi_imx.c +++ b/drivers/spi/spi_imx.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <linux/spi/spi.h> | 29 | #include <linux/spi/spi.h> |
30 | #include <linux/workqueue.h> | 30 | #include <linux/workqueue.h> |
31 | #include <linux/delay.h> | 31 | #include <linux/delay.h> |
32 | #include <linux/clk.h> | ||
32 | 33 | ||
33 | #include <asm/io.h> | 34 | #include <asm/io.h> |
34 | #include <asm/irq.h> | 35 | #include <asm/irq.h> |
@@ -250,6 +251,8 @@ struct driver_data { | |||
250 | int tx_dma_needs_unmap; | 251 | int tx_dma_needs_unmap; |
251 | size_t tx_map_len; | 252 | size_t tx_map_len; |
252 | u32 dummy_dma_buf ____cacheline_aligned; | 253 | u32 dummy_dma_buf ____cacheline_aligned; |
254 | |||
255 | struct clk *clk; | ||
253 | }; | 256 | }; |
254 | 257 | ||
255 | /* Runtime state */ | 258 | /* Runtime state */ |
@@ -855,15 +858,15 @@ static irqreturn_t spi_int(int irq, void *dev_id) | |||
855 | return drv_data->transfer_handler(drv_data); | 858 | return drv_data->transfer_handler(drv_data); |
856 | } | 859 | } |
857 | 860 | ||
858 | static inline u32 spi_speed_hz(u32 data_rate) | 861 | static inline u32 spi_speed_hz(struct driver_data *drv_data, u32 data_rate) |
859 | { | 862 | { |
860 | return imx_get_perclk2() / (4 << ((data_rate) >> 13)); | 863 | return clk_get_rate(drv_data->clk) / (4 << ((data_rate) >> 13)); |
861 | } | 864 | } |
862 | 865 | ||
863 | static u32 spi_data_rate(u32 speed_hz) | 866 | static u32 spi_data_rate(struct driver_data *drv_data, u32 speed_hz) |
864 | { | 867 | { |
865 | u32 div; | 868 | u32 div; |
866 | u32 quantized_hz = imx_get_perclk2() >> 2; | 869 | u32 quantized_hz = clk_get_rate(drv_data->clk) >> 2; |
867 | 870 | ||
868 | for (div = SPI_PERCLK2_DIV_MIN; | 871 | for (div = SPI_PERCLK2_DIV_MIN; |
869 | div <= SPI_PERCLK2_DIV_MAX; | 872 | div <= SPI_PERCLK2_DIV_MAX; |
@@ -947,7 +950,7 @@ static void pump_transfers(unsigned long data) | |||
947 | tmp = transfer->speed_hz; | 950 | tmp = transfer->speed_hz; |
948 | if (tmp == 0) | 951 | if (tmp == 0) |
949 | tmp = chip->max_speed_hz; | 952 | tmp = chip->max_speed_hz; |
950 | tmp = spi_data_rate(tmp); | 953 | tmp = spi_data_rate(drv_data, tmp); |
951 | u32_EDIT(control, SPI_CONTROL_DATARATE, tmp); | 954 | u32_EDIT(control, SPI_CONTROL_DATARATE, tmp); |
952 | 955 | ||
953 | writel(control, regs + SPI_CONTROL); | 956 | writel(control, regs + SPI_CONTROL); |
@@ -1109,7 +1112,7 @@ static int transfer(struct spi_device *spi, struct spi_message *msg) | |||
1109 | msg->actual_length = 0; | 1112 | msg->actual_length = 0; |
1110 | 1113 | ||
1111 | /* Per transfer setup check */ | 1114 | /* Per transfer setup check */ |
1112 | min_speed_hz = spi_speed_hz(SPI_CONTROL_DATARATE_MIN); | 1115 | min_speed_hz = spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN); |
1113 | max_speed_hz = spi->max_speed_hz; | 1116 | max_speed_hz = spi->max_speed_hz; |
1114 | list_for_each_entry(trans, &msg->transfers, transfer_list) { | 1117 | list_for_each_entry(trans, &msg->transfers, transfer_list) { |
1115 | tmp = trans->bits_per_word; | 1118 | tmp = trans->bits_per_word; |
@@ -1176,6 +1179,7 @@ msg_rejected: | |||
1176 | applied and notified to the calling driver. */ | 1179 | applied and notified to the calling driver. */ |
1177 | static int setup(struct spi_device *spi) | 1180 | static int setup(struct spi_device *spi) |
1178 | { | 1181 | { |
1182 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | ||
1179 | struct spi_imx_chip *chip_info; | 1183 | struct spi_imx_chip *chip_info; |
1180 | struct chip_data *chip; | 1184 | struct chip_data *chip; |
1181 | int first_setup = 0; | 1185 | int first_setup = 0; |
@@ -1304,14 +1308,14 @@ static int setup(struct spi_device *spi) | |||
1304 | chip->n_bytes = (tmp <= 8) ? 1 : 2; | 1308 | chip->n_bytes = (tmp <= 8) ? 1 : 2; |
1305 | 1309 | ||
1306 | /* SPI datarate */ | 1310 | /* SPI datarate */ |
1307 | tmp = spi_data_rate(spi->max_speed_hz); | 1311 | tmp = spi_data_rate(drv_data, spi->max_speed_hz); |
1308 | if (tmp == SPI_CONTROL_DATARATE_BAD) { | 1312 | if (tmp == SPI_CONTROL_DATARATE_BAD) { |
1309 | status = -EINVAL; | 1313 | status = -EINVAL; |
1310 | dev_err(&spi->dev, | 1314 | dev_err(&spi->dev, |
1311 | "setup - " | 1315 | "setup - " |
1312 | "HW min speed (%d Hz) exceeds required " | 1316 | "HW min speed (%d Hz) exceeds required " |
1313 | "max speed (%d Hz)\n", | 1317 | "max speed (%d Hz)\n", |
1314 | spi_speed_hz(SPI_CONTROL_DATARATE_MIN), | 1318 | spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN), |
1315 | spi->max_speed_hz); | 1319 | spi->max_speed_hz); |
1316 | if (first_setup) | 1320 | if (first_setup) |
1317 | goto err_first_setup; | 1321 | goto err_first_setup; |
@@ -1321,7 +1325,7 @@ static int setup(struct spi_device *spi) | |||
1321 | } else { | 1325 | } else { |
1322 | u32_EDIT(chip->control, SPI_CONTROL_DATARATE, tmp); | 1326 | u32_EDIT(chip->control, SPI_CONTROL_DATARATE, tmp); |
1323 | /* Actual rounded max_speed_hz */ | 1327 | /* Actual rounded max_speed_hz */ |
1324 | tmp = spi_speed_hz(tmp); | 1328 | tmp = spi_speed_hz(drv_data, tmp); |
1325 | spi->max_speed_hz = tmp; | 1329 | spi->max_speed_hz = tmp; |
1326 | chip->max_speed_hz = tmp; | 1330 | chip->max_speed_hz = tmp; |
1327 | } | 1331 | } |
@@ -1352,7 +1356,7 @@ static int setup(struct spi_device *spi) | |||
1352 | chip->period & SPI_PERIOD_WAIT, | 1356 | chip->period & SPI_PERIOD_WAIT, |
1353 | spi->mode, | 1357 | spi->mode, |
1354 | spi->bits_per_word, | 1358 | spi->bits_per_word, |
1355 | spi_speed_hz(SPI_CONTROL_DATARATE_MIN), | 1359 | spi_speed_hz(drv_data, SPI_CONTROL_DATARATE_MIN), |
1356 | spi->max_speed_hz); | 1360 | spi->max_speed_hz); |
1357 | return status; | 1361 | return status; |
1358 | 1362 | ||
@@ -1465,6 +1469,14 @@ static int __init spi_imx_probe(struct platform_device *pdev) | |||
1465 | goto err_no_pdata; | 1469 | goto err_no_pdata; |
1466 | } | 1470 | } |
1467 | 1471 | ||
1472 | drv_data->clk = clk_get(&pdev->dev, "perclk2"); | ||
1473 | if (IS_ERR(drv_data->clk)) { | ||
1474 | dev_err(&pdev->dev, "probe - cannot get get\n"); | ||
1475 | status = PTR_ERR(drv_data->clk); | ||
1476 | goto err_no_clk; | ||
1477 | } | ||
1478 | clk_enable(drv_data->clk); | ||
1479 | |||
1468 | /* Allocate master with space for drv_data */ | 1480 | /* Allocate master with space for drv_data */ |
1469 | master = spi_alloc_master(dev, sizeof(struct driver_data)); | 1481 | master = spi_alloc_master(dev, sizeof(struct driver_data)); |
1470 | if (!master) { | 1482 | if (!master) { |
@@ -1526,24 +1538,24 @@ static int __init spi_imx_probe(struct platform_device *pdev) | |||
1526 | drv_data->rx_channel = -1; | 1538 | drv_data->rx_channel = -1; |
1527 | if (platform_info->enable_dma) { | 1539 | if (platform_info->enable_dma) { |
1528 | /* Get rx DMA channel */ | 1540 | /* Get rx DMA channel */ |
1529 | status = imx_dma_request_by_prio(&drv_data->rx_channel, | 1541 | drv_data->rx_channel = imx_dma_request_by_prio("spi_imx_rx", |
1530 | "spi_imx_rx", DMA_PRIO_HIGH); | 1542 | DMA_PRIO_HIGH); |
1531 | if (status < 0) { | 1543 | if (drv_data->rx_channel < 0) { |
1532 | dev_err(dev, | 1544 | dev_err(dev, |
1533 | "probe - problem (%d) requesting rx channel\n", | 1545 | "probe - problem (%d) requesting rx channel\n", |
1534 | status); | 1546 | drv_data->rx_channel); |
1535 | goto err_no_rxdma; | 1547 | goto err_no_rxdma; |
1536 | } else | 1548 | } else |
1537 | imx_dma_setup_handlers(drv_data->rx_channel, NULL, | 1549 | imx_dma_setup_handlers(drv_data->rx_channel, NULL, |
1538 | dma_err_handler, drv_data); | 1550 | dma_err_handler, drv_data); |
1539 | 1551 | ||
1540 | /* Get tx DMA channel */ | 1552 | /* Get tx DMA channel */ |
1541 | status = imx_dma_request_by_prio(&drv_data->tx_channel, | 1553 | drv_data->tx_channel = imx_dma_request_by_prio("spi_imx_tx", |
1542 | "spi_imx_tx", DMA_PRIO_MEDIUM); | 1554 | DMA_PRIO_MEDIUM); |
1543 | if (status < 0) { | 1555 | if (drv_data->tx_channel < 0) { |
1544 | dev_err(dev, | 1556 | dev_err(dev, |
1545 | "probe - problem (%d) requesting tx channel\n", | 1557 | "probe - problem (%d) requesting tx channel\n", |
1546 | status); | 1558 | drv_data->tx_channel); |
1547 | imx_dma_free(drv_data->rx_channel); | 1559 | imx_dma_free(drv_data->rx_channel); |
1548 | goto err_no_txdma; | 1560 | goto err_no_txdma; |
1549 | } else | 1561 | } else |
@@ -1623,6 +1635,9 @@ err_no_iores: | |||
1623 | spi_master_put(master); | 1635 | spi_master_put(master); |
1624 | 1636 | ||
1625 | err_no_pdata: | 1637 | err_no_pdata: |
1638 | clk_disable(drv_data->clk); | ||
1639 | clk_put(drv_data->clk); | ||
1640 | err_no_clk: | ||
1626 | err_no_mem: | 1641 | err_no_mem: |
1627 | return status; | 1642 | return status; |
1628 | } | 1643 | } |
@@ -1662,6 +1677,9 @@ static int __exit spi_imx_remove(struct platform_device *pdev) | |||
1662 | if (irq >= 0) | 1677 | if (irq >= 0) |
1663 | free_irq(irq, drv_data); | 1678 | free_irq(irq, drv_data); |
1664 | 1679 | ||
1680 | clk_disable(drv_data->clk); | ||
1681 | clk_put(drv_data->clk); | ||
1682 | |||
1665 | /* Release map resources */ | 1683 | /* Release map resources */ |
1666 | iounmap(drv_data->regs); | 1684 | iounmap(drv_data->regs); |
1667 | release_resource(drv_data->ioarea); | 1685 | release_resource(drv_data->ioarea); |
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 6e784d2db423..d6bab0d5f453 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig | |||
@@ -118,10 +118,10 @@ config USB_AMD5536UDC | |||
118 | config USB_GADGET_ATMEL_USBA | 118 | config USB_GADGET_ATMEL_USBA |
119 | boolean "Atmel USBA" | 119 | boolean "Atmel USBA" |
120 | select USB_GADGET_DUALSPEED | 120 | select USB_GADGET_DUALSPEED |
121 | depends on AVR32 || ARCH_AT91CAP9 | 121 | depends on AVR32 || ARCH_AT91CAP9 || ARCH_AT91SAM9RL |
122 | help | 122 | help |
123 | USBA is the integrated high-speed USB Device controller on | 123 | USBA is the integrated high-speed USB Device controller on |
124 | the AT32AP700x and AT91CAP9 processors from Atmel. | 124 | the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel. |
125 | 125 | ||
126 | config USB_ATMEL_USBA | 126 | config USB_ATMEL_USBA |
127 | tristate | 127 | tristate |
@@ -172,7 +172,7 @@ config USB_NET2280 | |||
172 | default USB_GADGET | 172 | default USB_GADGET |
173 | select USB_GADGET_SELECTED | 173 | select USB_GADGET_SELECTED |
174 | 174 | ||
175 | config USB_GADGET_PXA2XX | 175 | config USB_GADGET_PXA25X |
176 | boolean "PXA 25x or IXP 4xx" | 176 | boolean "PXA 25x or IXP 4xx" |
177 | depends on (ARCH_PXA && PXA25x) || ARCH_IXP4XX | 177 | depends on (ARCH_PXA && PXA25x) || ARCH_IXP4XX |
178 | help | 178 | help |
@@ -184,19 +184,19 @@ config USB_GADGET_PXA2XX | |||
184 | zero (for control transfers). | 184 | zero (for control transfers). |
185 | 185 | ||
186 | Say "y" to link the driver statically, or "m" to build a | 186 | Say "y" to link the driver statically, or "m" to build a |
187 | dynamically linked module called "pxa2xx_udc" and force all | 187 | dynamically linked module called "pxa25x_udc" and force all |
188 | gadget drivers to also be dynamically linked. | 188 | gadget drivers to also be dynamically linked. |
189 | 189 | ||
190 | config USB_PXA2XX | 190 | config USB_PXA25X |
191 | tristate | 191 | tristate |
192 | depends on USB_GADGET_PXA2XX | 192 | depends on USB_GADGET_PXA25X |
193 | default USB_GADGET | 193 | default USB_GADGET |
194 | select USB_GADGET_SELECTED | 194 | select USB_GADGET_SELECTED |
195 | 195 | ||
196 | # if there's only one gadget driver, using only two bulk endpoints, | 196 | # if there's only one gadget driver, using only two bulk endpoints, |
197 | # don't waste memory for the other endpoints | 197 | # don't waste memory for the other endpoints |
198 | config USB_PXA2XX_SMALL | 198 | config USB_PXA25X_SMALL |
199 | depends on USB_GADGET_PXA2XX | 199 | depends on USB_GADGET_PXA25X |
200 | bool | 200 | bool |
201 | default n if USB_ETH_RNDIS | 201 | default n if USB_ETH_RNDIS |
202 | default y if USB_ZERO | 202 | default y if USB_ZERO |
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 12357255d740..e258afd25faf 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile | |||
@@ -8,7 +8,7 @@ endif | |||
8 | obj-$(CONFIG_USB_DUMMY_HCD) += dummy_hcd.o | 8 | obj-$(CONFIG_USB_DUMMY_HCD) += dummy_hcd.o |
9 | obj-$(CONFIG_USB_NET2280) += net2280.o | 9 | obj-$(CONFIG_USB_NET2280) += net2280.o |
10 | obj-$(CONFIG_USB_AMD5536UDC) += amd5536udc.o | 10 | obj-$(CONFIG_USB_AMD5536UDC) += amd5536udc.o |
11 | obj-$(CONFIG_USB_PXA2XX) += pxa2xx_udc.o | 11 | obj-$(CONFIG_USB_PXA25X) += pxa25x_udc.o |
12 | obj-$(CONFIG_USB_PXA27X) += pxa27x_udc.o | 12 | obj-$(CONFIG_USB_PXA27X) += pxa27x_udc.o |
13 | obj-$(CONFIG_USB_GOKU) += goku_udc.o | 13 | obj-$(CONFIG_USB_GOKU) += goku_udc.o |
14 | obj-$(CONFIG_USB_OMAP) += omap_udc.o | 14 | obj-$(CONFIG_USB_OMAP) += omap_udc.o |
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c index 274c60a970cd..b6b2a0a5ba37 100644 --- a/drivers/usb/gadget/at91_udc.c +++ b/drivers/usb/gadget/at91_udc.c | |||
@@ -888,7 +888,7 @@ static void pullup(struct at91_udc *udc, int is_on) | |||
888 | at91_udp_write(udc, AT91_UDP_TXVC, 0); | 888 | at91_udp_write(udc, AT91_UDP_TXVC, 0); |
889 | if (cpu_is_at91rm9200()) | 889 | if (cpu_is_at91rm9200()) |
890 | gpio_set_value(udc->board.pullup_pin, active); | 890 | gpio_set_value(udc->board.pullup_pin, active); |
891 | else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) { | 891 | else if (cpu_is_at91sam9260() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { |
892 | u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC); | 892 | u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC); |
893 | 893 | ||
894 | txvc |= AT91_UDP_TXVC_PUON; | 894 | txvc |= AT91_UDP_TXVC_PUON; |
@@ -906,7 +906,7 @@ static void pullup(struct at91_udc *udc, int is_on) | |||
906 | at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS); | 906 | at91_udp_write(udc, AT91_UDP_TXVC, AT91_UDP_TXVC_TXVDIS); |
907 | if (cpu_is_at91rm9200()) | 907 | if (cpu_is_at91rm9200()) |
908 | gpio_set_value(udc->board.pullup_pin, !active); | 908 | gpio_set_value(udc->board.pullup_pin, !active); |
909 | else if (cpu_is_at91sam9260() || cpu_is_at91sam9263()) { | 909 | else if (cpu_is_at91sam9260() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { |
910 | u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC); | 910 | u32 txvc = at91_udp_read(udc, AT91_UDP_TXVC); |
911 | 911 | ||
912 | txvc &= ~AT91_UDP_TXVC_PUON; | 912 | txvc &= ~AT91_UDP_TXVC_PUON; |
diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 8d61ea67a817..4ce3950b997f 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c | |||
@@ -262,7 +262,7 @@ MODULE_PARM_DESC(host_addr, "Host Ethernet Address"); | |||
262 | /* For CDC-incapable hardware, choose the simple cdc subset. | 262 | /* For CDC-incapable hardware, choose the simple cdc subset. |
263 | * Anything that talks bulk (without notable bugs) can do this. | 263 | * Anything that talks bulk (without notable bugs) can do this. |
264 | */ | 264 | */ |
265 | #ifdef CONFIG_USB_GADGET_PXA2XX | 265 | #ifdef CONFIG_USB_GADGET_PXA25X |
266 | #define DEV_CONFIG_SUBSET | 266 | #define DEV_CONFIG_SUBSET |
267 | #endif | 267 | #endif |
268 | 268 | ||
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index f7f159c1002b..ca5149ea7312 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h | |||
@@ -29,8 +29,8 @@ | |||
29 | #define gadget_is_dummy(g) 0 | 29 | #define gadget_is_dummy(g) 0 |
30 | #endif | 30 | #endif |
31 | 31 | ||
32 | #ifdef CONFIG_USB_GADGET_PXA2XX | 32 | #ifdef CONFIG_USB_GADGET_PXA25X |
33 | #define gadget_is_pxa(g) !strcmp("pxa2xx_udc", (g)->name) | 33 | #define gadget_is_pxa(g) !strcmp("pxa25x_udc", (g)->name) |
34 | #else | 34 | #else |
35 | #define gadget_is_pxa(g) 0 | 35 | #define gadget_is_pxa(g) 0 |
36 | #endif | 36 | #endif |
diff --git a/drivers/usb/gadget/inode.c b/drivers/usb/gadget/inode.c index 69b0a2754f2a..f132a9219e11 100644 --- a/drivers/usb/gadget/inode.c +++ b/drivers/usb/gadget/inode.c | |||
@@ -1501,7 +1501,7 @@ gadgetfs_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) | |||
1501 | } | 1501 | } |
1502 | break; | 1502 | break; |
1503 | 1503 | ||
1504 | #ifndef CONFIG_USB_GADGET_PXA2XX | 1504 | #ifndef CONFIG_USB_GADGET_PXA25X |
1505 | /* PXA automagically handles this request too */ | 1505 | /* PXA automagically handles this request too */ |
1506 | case USB_REQ_GET_CONFIGURATION: | 1506 | case USB_REQ_GET_CONFIGURATION: |
1507 | if (ctrl->bRequestType != 0x80) | 1507 | if (ctrl->bRequestType != 0x80) |
diff --git a/drivers/usb/gadget/omap_udc.c b/drivers/usb/gadget/omap_udc.c index 881d74c3d964..03a7f49d207d 100644 --- a/drivers/usb/gadget/omap_udc.c +++ b/drivers/usb/gadget/omap_udc.c | |||
@@ -135,13 +135,17 @@ static void use_ep(struct omap_ep *ep, u16 select) | |||
135 | 135 | ||
136 | if (ep->bEndpointAddress & USB_DIR_IN) | 136 | if (ep->bEndpointAddress & USB_DIR_IN) |
137 | num |= UDC_EP_DIR; | 137 | num |= UDC_EP_DIR; |
138 | UDC_EP_NUM_REG = num | select; | 138 | omap_writew(num | select, UDC_EP_NUM); |
139 | /* when select, MUST deselect later !! */ | 139 | /* when select, MUST deselect later !! */ |
140 | } | 140 | } |
141 | 141 | ||
142 | static inline void deselect_ep(void) | 142 | static inline void deselect_ep(void) |
143 | { | 143 | { |
144 | UDC_EP_NUM_REG &= ~UDC_EP_SEL; | 144 | u16 w; |
145 | |||
146 | w = omap_readw(UDC_EP_NUM); | ||
147 | w &= ~UDC_EP_SEL; | ||
148 | omap_writew(w, UDC_EP_NUM); | ||
145 | /* 6 wait states before TX will happen */ | 149 | /* 6 wait states before TX will happen */ |
146 | } | 150 | } |
147 | 151 | ||
@@ -216,7 +220,7 @@ static int omap_ep_enable(struct usb_ep *_ep, | |||
216 | ep->has_dma = 0; | 220 | ep->has_dma = 0; |
217 | ep->lch = -1; | 221 | ep->lch = -1; |
218 | use_ep(ep, UDC_EP_SEL); | 222 | use_ep(ep, UDC_EP_SEL); |
219 | UDC_CTRL_REG = udc->clr_halt; | 223 | omap_writew(udc->clr_halt, UDC_CTRL); |
220 | ep->ackwait = 0; | 224 | ep->ackwait = 0; |
221 | deselect_ep(); | 225 | deselect_ep(); |
222 | 226 | ||
@@ -232,7 +236,7 @@ static int omap_ep_enable(struct usb_ep *_ep, | |||
232 | if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC | 236 | if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC |
233 | && !ep->has_dma | 237 | && !ep->has_dma |
234 | && !(ep->bEndpointAddress & USB_DIR_IN)) { | 238 | && !(ep->bEndpointAddress & USB_DIR_IN)) { |
235 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 239 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
236 | ep->ackwait = 1 + ep->double_buf; | 240 | ep->ackwait = 1 + ep->double_buf; |
237 | } | 241 | } |
238 | 242 | ||
@@ -259,7 +263,7 @@ static int omap_ep_disable(struct usb_ep *_ep) | |||
259 | nuke (ep, -ESHUTDOWN); | 263 | nuke (ep, -ESHUTDOWN); |
260 | ep->ep.maxpacket = ep->maxpacket; | 264 | ep->ep.maxpacket = ep->maxpacket; |
261 | ep->has_dma = 0; | 265 | ep->has_dma = 0; |
262 | UDC_CTRL_REG = UDC_SET_HALT; | 266 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
263 | list_del_init(&ep->iso); | 267 | list_del_init(&ep->iso); |
264 | del_timer(&ep->timer); | 268 | del_timer(&ep->timer); |
265 | 269 | ||
@@ -360,13 +364,13 @@ write_packet(u8 *buf, struct omap_req *req, unsigned max) | |||
360 | if (likely((((int)buf) & 1) == 0)) { | 364 | if (likely((((int)buf) & 1) == 0)) { |
361 | wp = (u16 *)buf; | 365 | wp = (u16 *)buf; |
362 | while (max >= 2) { | 366 | while (max >= 2) { |
363 | UDC_DATA_REG = *wp++; | 367 | omap_writew(*wp++, UDC_DATA); |
364 | max -= 2; | 368 | max -= 2; |
365 | } | 369 | } |
366 | buf = (u8 *)wp; | 370 | buf = (u8 *)wp; |
367 | } | 371 | } |
368 | while (max--) | 372 | while (max--) |
369 | *(volatile u8 *)&UDC_DATA_REG = *buf++; | 373 | omap_writeb(*buf++, UDC_DATA); |
370 | return len; | 374 | return len; |
371 | } | 375 | } |
372 | 376 | ||
@@ -385,13 +389,13 @@ static int write_fifo(struct omap_ep *ep, struct omap_req *req) | |||
385 | prefetch(buf); | 389 | prefetch(buf); |
386 | 390 | ||
387 | /* PIO-IN isn't double buffered except for iso */ | 391 | /* PIO-IN isn't double buffered except for iso */ |
388 | ep_stat = UDC_STAT_FLG_REG; | 392 | ep_stat = omap_readw(UDC_STAT_FLG); |
389 | if (ep_stat & UDC_FIFO_UNWRITABLE) | 393 | if (ep_stat & UDC_FIFO_UNWRITABLE) |
390 | return 0; | 394 | return 0; |
391 | 395 | ||
392 | count = ep->ep.maxpacket; | 396 | count = ep->ep.maxpacket; |
393 | count = write_packet(buf, req, count); | 397 | count = write_packet(buf, req, count); |
394 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 398 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
395 | ep->ackwait = 1; | 399 | ep->ackwait = 1; |
396 | 400 | ||
397 | /* last packet is often short (sometimes a zlp) */ | 401 | /* last packet is often short (sometimes a zlp) */ |
@@ -425,13 +429,13 @@ read_packet(u8 *buf, struct omap_req *req, unsigned avail) | |||
425 | if (likely((((int)buf) & 1) == 0)) { | 429 | if (likely((((int)buf) & 1) == 0)) { |
426 | wp = (u16 *)buf; | 430 | wp = (u16 *)buf; |
427 | while (avail >= 2) { | 431 | while (avail >= 2) { |
428 | *wp++ = UDC_DATA_REG; | 432 | *wp++ = omap_readw(UDC_DATA); |
429 | avail -= 2; | 433 | avail -= 2; |
430 | } | 434 | } |
431 | buf = (u8 *)wp; | 435 | buf = (u8 *)wp; |
432 | } | 436 | } |
433 | while (avail--) | 437 | while (avail--) |
434 | *buf++ = *(volatile u8 *)&UDC_DATA_REG; | 438 | *buf++ = omap_readb(UDC_DATA); |
435 | return len; | 439 | return len; |
436 | } | 440 | } |
437 | 441 | ||
@@ -446,7 +450,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) | |||
446 | prefetchw(buf); | 450 | prefetchw(buf); |
447 | 451 | ||
448 | for (;;) { | 452 | for (;;) { |
449 | u16 ep_stat = UDC_STAT_FLG_REG; | 453 | u16 ep_stat = omap_readw(UDC_STAT_FLG); |
450 | 454 | ||
451 | is_last = 0; | 455 | is_last = 0; |
452 | if (ep_stat & FIFO_EMPTY) { | 456 | if (ep_stat & FIFO_EMPTY) { |
@@ -460,7 +464,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) | |||
460 | if (ep_stat & UDC_FIFO_FULL) | 464 | if (ep_stat & UDC_FIFO_FULL) |
461 | avail = ep->ep.maxpacket; | 465 | avail = ep->ep.maxpacket; |
462 | else { | 466 | else { |
463 | avail = UDC_RXFSTAT_REG; | 467 | avail = omap_readw(UDC_RXFSTAT); |
464 | ep->fnf = ep->double_buf; | 468 | ep->fnf = ep->double_buf; |
465 | } | 469 | } |
466 | count = read_packet(buf, req, avail); | 470 | count = read_packet(buf, req, avail); |
@@ -473,7 +477,7 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) | |||
473 | req->req.status = -EOVERFLOW; | 477 | req->req.status = -EOVERFLOW; |
474 | avail -= count; | 478 | avail -= count; |
475 | while (avail--) | 479 | while (avail--) |
476 | (void) *(volatile u8 *)&UDC_DATA_REG; | 480 | omap_readw(UDC_DATA); |
477 | } | 481 | } |
478 | } else if (req->req.length == req->req.actual) | 482 | } else if (req->req.length == req->req.actual) |
479 | is_last = 1; | 483 | is_last = 1; |
@@ -491,32 +495,6 @@ static int read_fifo(struct omap_ep *ep, struct omap_req *req) | |||
491 | 495 | ||
492 | /*-------------------------------------------------------------------------*/ | 496 | /*-------------------------------------------------------------------------*/ |
493 | 497 | ||
494 | static inline dma_addr_t dma_csac(unsigned lch) | ||
495 | { | ||
496 | dma_addr_t csac; | ||
497 | |||
498 | /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | ||
499 | * read before the DMA controller finished disabling the channel. | ||
500 | */ | ||
501 | csac = OMAP_DMA_CSAC_REG(lch); | ||
502 | if (csac == 0) | ||
503 | csac = OMAP_DMA_CSAC_REG(lch); | ||
504 | return csac; | ||
505 | } | ||
506 | |||
507 | static inline dma_addr_t dma_cdac(unsigned lch) | ||
508 | { | ||
509 | dma_addr_t cdac; | ||
510 | |||
511 | /* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is | ||
512 | * read before the DMA controller finished disabling the channel. | ||
513 | */ | ||
514 | cdac = OMAP_DMA_CDAC_REG(lch); | ||
515 | if (cdac == 0) | ||
516 | cdac = OMAP_DMA_CDAC_REG(lch); | ||
517 | return cdac; | ||
518 | } | ||
519 | |||
520 | static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) | 498 | static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) |
521 | { | 499 | { |
522 | dma_addr_t end; | 500 | dma_addr_t end; |
@@ -527,7 +505,7 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) | |||
527 | if (cpu_is_omap15xx()) | 505 | if (cpu_is_omap15xx()) |
528 | return 0; | 506 | return 0; |
529 | 507 | ||
530 | end = dma_csac(ep->lch); | 508 | end = omap_get_dma_src_pos(ep->lch); |
531 | if (end == ep->dma_counter) | 509 | if (end == ep->dma_counter) |
532 | return 0; | 510 | return 0; |
533 | 511 | ||
@@ -537,15 +515,11 @@ static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start) | |||
537 | return end - start; | 515 | return end - start; |
538 | } | 516 | } |
539 | 517 | ||
540 | #define DMA_DEST_LAST(x) (cpu_is_omap15xx() \ | ||
541 | ? OMAP_DMA_CSAC_REG(x) /* really: CPC */ \ | ||
542 | : dma_cdac(x)) | ||
543 | |||
544 | static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) | 518 | static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) |
545 | { | 519 | { |
546 | dma_addr_t end; | 520 | dma_addr_t end; |
547 | 521 | ||
548 | end = DMA_DEST_LAST(ep->lch); | 522 | end = omap_get_dma_dst_pos(ep->lch); |
549 | if (end == ep->dma_counter) | 523 | if (end == ep->dma_counter) |
550 | return 0; | 524 | return 0; |
551 | 525 | ||
@@ -565,7 +539,7 @@ static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start) | |||
565 | 539 | ||
566 | static void next_in_dma(struct omap_ep *ep, struct omap_req *req) | 540 | static void next_in_dma(struct omap_ep *ep, struct omap_req *req) |
567 | { | 541 | { |
568 | u16 txdma_ctrl; | 542 | u16 txdma_ctrl, w; |
569 | unsigned length = req->req.length - req->req.actual; | 543 | unsigned length = req->req.length - req->req.actual; |
570 | const int sync_mode = cpu_is_omap15xx() | 544 | const int sync_mode = cpu_is_omap15xx() |
571 | ? OMAP_DMA_SYNC_FRAME | 545 | ? OMAP_DMA_SYNC_FRAME |
@@ -596,14 +570,18 @@ static void next_in_dma(struct omap_ep *ep, struct omap_req *req) | |||
596 | 0, 0); | 570 | 0, 0); |
597 | 571 | ||
598 | omap_start_dma(ep->lch); | 572 | omap_start_dma(ep->lch); |
599 | ep->dma_counter = dma_csac(ep->lch); | 573 | ep->dma_counter = omap_get_dma_src_pos(ep->lch); |
600 | UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel); | 574 | w = omap_readw(UDC_DMA_IRQ_EN); |
601 | UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl; | 575 | w |= UDC_TX_DONE_IE(ep->dma_channel); |
576 | omap_writew(w, UDC_DMA_IRQ_EN); | ||
577 | omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel)); | ||
602 | req->dma_bytes = length; | 578 | req->dma_bytes = length; |
603 | } | 579 | } |
604 | 580 | ||
605 | static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) | 581 | static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) |
606 | { | 582 | { |
583 | u16 w; | ||
584 | |||
607 | if (status == 0) { | 585 | if (status == 0) { |
608 | req->req.actual += req->dma_bytes; | 586 | req->req.actual += req->dma_bytes; |
609 | 587 | ||
@@ -620,7 +598,9 @@ static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status) | |||
620 | 598 | ||
621 | /* tx completion */ | 599 | /* tx completion */ |
622 | omap_stop_dma(ep->lch); | 600 | omap_stop_dma(ep->lch); |
623 | UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel); | 601 | w = omap_readw(UDC_DMA_IRQ_EN); |
602 | w &= ~UDC_TX_DONE_IE(ep->dma_channel); | ||
603 | omap_writew(w, UDC_DMA_IRQ_EN); | ||
624 | done(ep, req, status); | 604 | done(ep, req, status); |
625 | } | 605 | } |
626 | 606 | ||
@@ -628,6 +608,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req) | |||
628 | { | 608 | { |
629 | unsigned packets = req->req.length - req->req.actual; | 609 | unsigned packets = req->req.length - req->req.actual; |
630 | int dma_trigger = 0; | 610 | int dma_trigger = 0; |
611 | u16 w; | ||
631 | 612 | ||
632 | if (cpu_is_omap24xx()) | 613 | if (cpu_is_omap24xx()) |
633 | dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel); | 614 | dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel); |
@@ -654,12 +635,14 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req) | |||
654 | omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF, | 635 | omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF, |
655 | OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, | 636 | OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual, |
656 | 0, 0); | 637 | 0, 0); |
657 | ep->dma_counter = DMA_DEST_LAST(ep->lch); | 638 | ep->dma_counter = omap_get_dma_dst_pos(ep->lch); |
658 | 639 | ||
659 | UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1); | 640 | omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel)); |
660 | UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel); | 641 | w = omap_readw(UDC_DMA_IRQ_EN); |
661 | UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf); | 642 | w |= UDC_RX_EOT_IE(ep->dma_channel); |
662 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 643 | omap_writew(w, UDC_DMA_IRQ_EN); |
644 | omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM); | ||
645 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); | ||
663 | 646 | ||
664 | omap_start_dma(ep->lch); | 647 | omap_start_dma(ep->lch); |
665 | } | 648 | } |
@@ -667,7 +650,7 @@ static void next_out_dma(struct omap_ep *ep, struct omap_req *req) | |||
667 | static void | 650 | static void |
668 | finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) | 651 | finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) |
669 | { | 652 | { |
670 | u16 count; | 653 | u16 count, w; |
671 | 654 | ||
672 | if (status == 0) | 655 | if (status == 0) |
673 | ep->dma_counter = (u16) (req->req.dma + req->req.actual); | 656 | ep->dma_counter = (u16) (req->req.dma + req->req.actual); |
@@ -686,13 +669,15 @@ finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one) | |||
686 | return; | 669 | return; |
687 | 670 | ||
688 | /* rx completion */ | 671 | /* rx completion */ |
689 | UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel); | 672 | w = omap_readw(UDC_DMA_IRQ_EN); |
673 | w &= ~UDC_RX_EOT_IE(ep->dma_channel); | ||
674 | omap_writew(w, UDC_DMA_IRQ_EN); | ||
690 | done(ep, req, status); | 675 | done(ep, req, status); |
691 | } | 676 | } |
692 | 677 | ||
693 | static void dma_irq(struct omap_udc *udc, u16 irq_src) | 678 | static void dma_irq(struct omap_udc *udc, u16 irq_src) |
694 | { | 679 | { |
695 | u16 dman_stat = UDC_DMAN_STAT_REG; | 680 | u16 dman_stat = omap_readw(UDC_DMAN_STAT); |
696 | struct omap_ep *ep; | 681 | struct omap_ep *ep; |
697 | struct omap_req *req; | 682 | struct omap_req *req; |
698 | 683 | ||
@@ -706,7 +691,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src) | |||
706 | struct omap_req, queue); | 691 | struct omap_req, queue); |
707 | finish_in_dma(ep, req, 0); | 692 | finish_in_dma(ep, req, 0); |
708 | } | 693 | } |
709 | UDC_IRQ_SRC_REG = UDC_TXN_DONE; | 694 | omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC); |
710 | 695 | ||
711 | if (!list_empty (&ep->queue)) { | 696 | if (!list_empty (&ep->queue)) { |
712 | req = container_of(ep->queue.next, | 697 | req = container_of(ep->queue.next, |
@@ -725,7 +710,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src) | |||
725 | struct omap_req, queue); | 710 | struct omap_req, queue); |
726 | finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB); | 711 | finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB); |
727 | } | 712 | } |
728 | UDC_IRQ_SRC_REG = UDC_RXN_EOT; | 713 | omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC); |
729 | 714 | ||
730 | if (!list_empty (&ep->queue)) { | 715 | if (!list_empty (&ep->queue)) { |
731 | req = container_of(ep->queue.next, | 716 | req = container_of(ep->queue.next, |
@@ -739,7 +724,7 @@ static void dma_irq(struct omap_udc *udc, u16 irq_src) | |||
739 | ep->irqs++; | 724 | ep->irqs++; |
740 | /* omap15xx does this unasked... */ | 725 | /* omap15xx does this unasked... */ |
741 | VDBG("%s, RX_CNT irq?\n", ep->ep.name); | 726 | VDBG("%s, RX_CNT irq?\n", ep->ep.name); |
742 | UDC_IRQ_SRC_REG = UDC_RXN_CNT; | 727 | omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC); |
743 | } | 728 | } |
744 | } | 729 | } |
745 | 730 | ||
@@ -762,9 +747,9 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) | |||
762 | 747 | ||
763 | is_in = ep->bEndpointAddress & USB_DIR_IN; | 748 | is_in = ep->bEndpointAddress & USB_DIR_IN; |
764 | if (is_in) | 749 | if (is_in) |
765 | reg = UDC_TXDMA_CFG_REG; | 750 | reg = omap_readw(UDC_TXDMA_CFG); |
766 | else | 751 | else |
767 | reg = UDC_RXDMA_CFG_REG; | 752 | reg = omap_readw(UDC_RXDMA_CFG); |
768 | reg |= UDC_DMA_REQ; /* "pulse" activated */ | 753 | reg |= UDC_DMA_REQ; /* "pulse" activated */ |
769 | 754 | ||
770 | ep->dma_channel = 0; | 755 | ep->dma_channel = 0; |
@@ -792,7 +777,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) | |||
792 | status = omap_request_dma(dma_channel, | 777 | status = omap_request_dma(dma_channel, |
793 | ep->ep.name, dma_error, ep, &ep->lch); | 778 | ep->ep.name, dma_error, ep, &ep->lch); |
794 | if (status == 0) { | 779 | if (status == 0) { |
795 | UDC_TXDMA_CFG_REG = reg; | 780 | omap_writew(reg, UDC_TXDMA_CFG); |
796 | /* EMIFF or SDRC */ | 781 | /* EMIFF or SDRC */ |
797 | omap_set_dma_src_burst_mode(ep->lch, | 782 | omap_set_dma_src_burst_mode(ep->lch, |
798 | OMAP_DMA_DATA_BURST_4); | 783 | OMAP_DMA_DATA_BURST_4); |
@@ -801,7 +786,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) | |||
801 | omap_set_dma_dest_params(ep->lch, | 786 | omap_set_dma_dest_params(ep->lch, |
802 | OMAP_DMA_PORT_TIPB, | 787 | OMAP_DMA_PORT_TIPB, |
803 | OMAP_DMA_AMODE_CONSTANT, | 788 | OMAP_DMA_AMODE_CONSTANT, |
804 | (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG), | 789 | (unsigned long) io_v2p(UDC_DATA_DMA), |
805 | 0, 0); | 790 | 0, 0); |
806 | } | 791 | } |
807 | } else { | 792 | } else { |
@@ -813,12 +798,12 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) | |||
813 | status = omap_request_dma(dma_channel, | 798 | status = omap_request_dma(dma_channel, |
814 | ep->ep.name, dma_error, ep, &ep->lch); | 799 | ep->ep.name, dma_error, ep, &ep->lch); |
815 | if (status == 0) { | 800 | if (status == 0) { |
816 | UDC_RXDMA_CFG_REG = reg; | 801 | omap_writew(reg, UDC_RXDMA_CFG); |
817 | /* TIPB */ | 802 | /* TIPB */ |
818 | omap_set_dma_src_params(ep->lch, | 803 | omap_set_dma_src_params(ep->lch, |
819 | OMAP_DMA_PORT_TIPB, | 804 | OMAP_DMA_PORT_TIPB, |
820 | OMAP_DMA_AMODE_CONSTANT, | 805 | OMAP_DMA_AMODE_CONSTANT, |
821 | (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG), | 806 | (unsigned long) io_v2p(UDC_DATA_DMA), |
822 | 0, 0); | 807 | 0, 0); |
823 | /* EMIFF or SDRC */ | 808 | /* EMIFF or SDRC */ |
824 | omap_set_dma_dest_burst_mode(ep->lch, | 809 | omap_set_dma_dest_burst_mode(ep->lch, |
@@ -834,7 +819,7 @@ static void dma_channel_claim(struct omap_ep *ep, unsigned channel) | |||
834 | 819 | ||
835 | /* channel type P: hw synch (fifo) */ | 820 | /* channel type P: hw synch (fifo) */ |
836 | if (cpu_class_is_omap1() && !cpu_is_omap15xx()) | 821 | if (cpu_class_is_omap1() && !cpu_is_omap15xx()) |
837 | OMAP1_DMA_LCH_CTRL_REG(ep->lch) = 2; | 822 | omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P); |
838 | } | 823 | } |
839 | 824 | ||
840 | just_restart: | 825 | just_restart: |
@@ -860,7 +845,7 @@ just_restart: | |||
860 | (is_in ? write_fifo : read_fifo)(ep, req); | 845 | (is_in ? write_fifo : read_fifo)(ep, req); |
861 | deselect_ep(); | 846 | deselect_ep(); |
862 | if (!is_in) { | 847 | if (!is_in) { |
863 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 848 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
864 | ep->ackwait = 1 + ep->double_buf; | 849 | ep->ackwait = 1 + ep->double_buf; |
865 | } | 850 | } |
866 | /* IN: 6 wait states before it'll tx */ | 851 | /* IN: 6 wait states before it'll tx */ |
@@ -881,7 +866,7 @@ static void dma_channel_release(struct omap_ep *ep) | |||
881 | else | 866 | else |
882 | req = NULL; | 867 | req = NULL; |
883 | 868 | ||
884 | active = ((1 << 7) & OMAP_DMA_CCR_REG(ep->lch)) != 0; | 869 | active = omap_get_dma_active_status(ep->lch); |
885 | 870 | ||
886 | DBG("%s release %s %cxdma%d %p\n", ep->ep.name, | 871 | DBG("%s release %s %cxdma%d %p\n", ep->ep.name, |
887 | active ? "active" : "idle", | 872 | active ? "active" : "idle", |
@@ -894,23 +879,25 @@ static void dma_channel_release(struct omap_ep *ep) | |||
894 | 879 | ||
895 | /* wait till current packet DMA finishes, and fifo empties */ | 880 | /* wait till current packet DMA finishes, and fifo empties */ |
896 | if (ep->bEndpointAddress & USB_DIR_IN) { | 881 | if (ep->bEndpointAddress & USB_DIR_IN) { |
897 | UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ; | 882 | omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ, |
883 | UDC_TXDMA_CFG); | ||
898 | 884 | ||
899 | if (req) { | 885 | if (req) { |
900 | finish_in_dma(ep, req, -ECONNRESET); | 886 | finish_in_dma(ep, req, -ECONNRESET); |
901 | 887 | ||
902 | /* clear FIFO; hosts probably won't empty it */ | 888 | /* clear FIFO; hosts probably won't empty it */ |
903 | use_ep(ep, UDC_EP_SEL); | 889 | use_ep(ep, UDC_EP_SEL); |
904 | UDC_CTRL_REG = UDC_CLR_EP; | 890 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
905 | deselect_ep(); | 891 | deselect_ep(); |
906 | } | 892 | } |
907 | while (UDC_TXDMA_CFG_REG & mask) | 893 | while (omap_readw(UDC_TXDMA_CFG) & mask) |
908 | udelay(10); | 894 | udelay(10); |
909 | } else { | 895 | } else { |
910 | UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ; | 896 | omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ, |
897 | UDC_RXDMA_CFG); | ||
911 | 898 | ||
912 | /* dma empties the fifo */ | 899 | /* dma empties the fifo */ |
913 | while (UDC_RXDMA_CFG_REG & mask) | 900 | while (omap_readw(UDC_RXDMA_CFG) & mask) |
914 | udelay(10); | 901 | udelay(10); |
915 | if (req) | 902 | if (req) |
916 | finish_out_dma(ep, req, -ECONNRESET, 0); | 903 | finish_out_dma(ep, req, -ECONNRESET, 0); |
@@ -997,9 +984,13 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |||
997 | req->req.actual = 0; | 984 | req->req.actual = 0; |
998 | 985 | ||
999 | /* maybe kickstart non-iso i/o queues */ | 986 | /* maybe kickstart non-iso i/o queues */ |
1000 | if (is_iso) | 987 | if (is_iso) { |
1001 | UDC_IRQ_EN_REG |= UDC_SOF_IE; | 988 | u16 w; |
1002 | else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { | 989 | |
990 | w = omap_readw(UDC_IRQ_EN); | ||
991 | w |= UDC_SOF_IE; | ||
992 | omap_writew(w, UDC_IRQ_EN); | ||
993 | } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) { | ||
1003 | int is_in; | 994 | int is_in; |
1004 | 995 | ||
1005 | if (ep->bEndpointAddress == 0) { | 996 | if (ep->bEndpointAddress == 0) { |
@@ -1017,23 +1008,23 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |||
1017 | * requests to non-control endpoints | 1008 | * requests to non-control endpoints |
1018 | */ | 1009 | */ |
1019 | if (udc->ep0_set_config) { | 1010 | if (udc->ep0_set_config) { |
1020 | u16 irq_en = UDC_IRQ_EN_REG; | 1011 | u16 irq_en = omap_readw(UDC_IRQ_EN); |
1021 | 1012 | ||
1022 | irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE; | 1013 | irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE; |
1023 | if (!udc->ep0_reset_config) | 1014 | if (!udc->ep0_reset_config) |
1024 | irq_en |= UDC_EPN_RX_IE | 1015 | irq_en |= UDC_EPN_RX_IE |
1025 | | UDC_EPN_TX_IE; | 1016 | | UDC_EPN_TX_IE; |
1026 | UDC_IRQ_EN_REG = irq_en; | 1017 | omap_writew(irq_en, UDC_IRQ_EN); |
1027 | } | 1018 | } |
1028 | 1019 | ||
1029 | /* STATUS for zero length DATA stages is | 1020 | /* STATUS for zero length DATA stages is |
1030 | * always an IN ... even for IN transfers, | 1021 | * always an IN ... even for IN transfers, |
1031 | * a weird case which seem to stall OMAP. | 1022 | * a weird case which seem to stall OMAP. |
1032 | */ | 1023 | */ |
1033 | UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR); | 1024 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM); |
1034 | UDC_CTRL_REG = UDC_CLR_EP; | 1025 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1035 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1026 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1036 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1027 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1037 | 1028 | ||
1038 | /* cleanup */ | 1029 | /* cleanup */ |
1039 | udc->ep0_pending = 0; | 1030 | udc->ep0_pending = 0; |
@@ -1042,11 +1033,11 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |||
1042 | 1033 | ||
1043 | /* non-empty DATA stage */ | 1034 | /* non-empty DATA stage */ |
1044 | } else if (is_in) { | 1035 | } else if (is_in) { |
1045 | UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; | 1036 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM); |
1046 | } else { | 1037 | } else { |
1047 | if (udc->ep0_setup) | 1038 | if (udc->ep0_setup) |
1048 | goto irq_wait; | 1039 | goto irq_wait; |
1049 | UDC_EP_NUM_REG = UDC_EP_SEL; | 1040 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); |
1050 | } | 1041 | } |
1051 | } else { | 1042 | } else { |
1052 | is_in = ep->bEndpointAddress & USB_DIR_IN; | 1043 | is_in = ep->bEndpointAddress & USB_DIR_IN; |
@@ -1062,7 +1053,7 @@ omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |||
1062 | req = NULL; | 1053 | req = NULL; |
1063 | deselect_ep(); | 1054 | deselect_ep(); |
1064 | if (!is_in) { | 1055 | if (!is_in) { |
1065 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1056 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1066 | ep->ackwait = 1 + ep->double_buf; | 1057 | ep->ackwait = 1 + ep->double_buf; |
1067 | } | 1058 | } |
1068 | /* IN: 6 wait states before it'll tx */ | 1059 | /* IN: 6 wait states before it'll tx */ |
@@ -1130,9 +1121,9 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value) | |||
1130 | else if (value) { | 1121 | else if (value) { |
1131 | if (ep->udc->ep0_set_config) { | 1122 | if (ep->udc->ep0_set_config) { |
1132 | WARN("error changing config?\n"); | 1123 | WARN("error changing config?\n"); |
1133 | UDC_SYSCON2_REG = UDC_CLR_CFG; | 1124 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1134 | } | 1125 | } |
1135 | UDC_SYSCON2_REG = UDC_STALL_CMD; | 1126 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1136 | ep->udc->ep0_pending = 0; | 1127 | ep->udc->ep0_pending = 0; |
1137 | status = 0; | 1128 | status = 0; |
1138 | } else /* NOP */ | 1129 | } else /* NOP */ |
@@ -1159,8 +1150,8 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value) | |||
1159 | channel = 0; | 1150 | channel = 0; |
1160 | 1151 | ||
1161 | use_ep(ep, UDC_EP_SEL); | 1152 | use_ep(ep, UDC_EP_SEL); |
1162 | if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) { | 1153 | if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) { |
1163 | UDC_CTRL_REG = UDC_SET_HALT; | 1154 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1164 | status = 0; | 1155 | status = 0; |
1165 | } else | 1156 | } else |
1166 | status = -EAGAIN; | 1157 | status = -EAGAIN; |
@@ -1170,10 +1161,10 @@ static int omap_ep_set_halt(struct usb_ep *_ep, int value) | |||
1170 | dma_channel_claim(ep, channel); | 1161 | dma_channel_claim(ep, channel); |
1171 | } else { | 1162 | } else { |
1172 | use_ep(ep, 0); | 1163 | use_ep(ep, 0); |
1173 | UDC_CTRL_REG = ep->udc->clr_halt; | 1164 | omap_writew(ep->udc->clr_halt, UDC_CTRL); |
1174 | ep->ackwait = 0; | 1165 | ep->ackwait = 0; |
1175 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { | 1166 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { |
1176 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1167 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1177 | ep->ackwait = 1 + ep->double_buf; | 1168 | ep->ackwait = 1 + ep->double_buf; |
1178 | } | 1169 | } |
1179 | } | 1170 | } |
@@ -1205,7 +1196,7 @@ static struct usb_ep_ops omap_ep_ops = { | |||
1205 | 1196 | ||
1206 | static int omap_get_frame(struct usb_gadget *gadget) | 1197 | static int omap_get_frame(struct usb_gadget *gadget) |
1207 | { | 1198 | { |
1208 | u16 sof = UDC_SOF_REG; | 1199 | u16 sof = omap_readw(UDC_SOF); |
1209 | return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC; | 1200 | return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC; |
1210 | } | 1201 | } |
1211 | 1202 | ||
@@ -1224,7 +1215,7 @@ static int omap_wakeup(struct usb_gadget *gadget) | |||
1224 | */ | 1215 | */ |
1225 | if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) { | 1216 | if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) { |
1226 | DBG("remote wakeup...\n"); | 1217 | DBG("remote wakeup...\n"); |
1227 | UDC_SYSCON2_REG = UDC_RMT_WKP; | 1218 | omap_writew(UDC_RMT_WKP, UDC_SYSCON2); |
1228 | retval = 0; | 1219 | retval = 0; |
1229 | } | 1220 | } |
1230 | 1221 | ||
@@ -1247,12 +1238,12 @@ omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) | |||
1247 | 1238 | ||
1248 | udc = container_of(gadget, struct omap_udc, gadget); | 1239 | udc = container_of(gadget, struct omap_udc, gadget); |
1249 | spin_lock_irqsave(&udc->lock, flags); | 1240 | spin_lock_irqsave(&udc->lock, flags); |
1250 | syscon1 = UDC_SYSCON1_REG; | 1241 | syscon1 = omap_readw(UDC_SYSCON1); |
1251 | if (is_selfpowered) | 1242 | if (is_selfpowered) |
1252 | syscon1 |= UDC_SELF_PWR; | 1243 | syscon1 |= UDC_SELF_PWR; |
1253 | else | 1244 | else |
1254 | syscon1 &= ~UDC_SELF_PWR; | 1245 | syscon1 &= ~UDC_SELF_PWR; |
1255 | UDC_SYSCON1_REG = syscon1; | 1246 | omap_writew(syscon1, UDC_SYSCON1); |
1256 | spin_unlock_irqrestore(&udc->lock, flags); | 1247 | spin_unlock_irqrestore(&udc->lock, flags); |
1257 | 1248 | ||
1258 | return 0; | 1249 | return 0; |
@@ -1265,18 +1256,36 @@ static int can_pullup(struct omap_udc *udc) | |||
1265 | 1256 | ||
1266 | static void pullup_enable(struct omap_udc *udc) | 1257 | static void pullup_enable(struct omap_udc *udc) |
1267 | { | 1258 | { |
1268 | UDC_SYSCON1_REG |= UDC_PULLUP_EN; | 1259 | u16 w; |
1269 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) | 1260 | |
1270 | OTG_CTRL_REG |= OTG_BSESSVLD; | 1261 | w = omap_readw(UDC_SYSCON1); |
1271 | UDC_IRQ_EN_REG = UDC_DS_CHG_IE; | 1262 | w |= UDC_PULLUP_EN; |
1263 | omap_writew(w, UDC_SYSCON1); | ||
1264 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { | ||
1265 | u32 l; | ||
1266 | |||
1267 | l = omap_readl(OTG_CTRL); | ||
1268 | l |= OTG_BSESSVLD; | ||
1269 | omap_writel(l, OTG_CTRL); | ||
1270 | } | ||
1271 | omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); | ||
1272 | } | 1272 | } |
1273 | 1273 | ||
1274 | static void pullup_disable(struct omap_udc *udc) | 1274 | static void pullup_disable(struct omap_udc *udc) |
1275 | { | 1275 | { |
1276 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) | 1276 | u16 w; |
1277 | OTG_CTRL_REG &= ~OTG_BSESSVLD; | 1277 | |
1278 | UDC_IRQ_EN_REG = UDC_DS_CHG_IE; | 1278 | if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) { |
1279 | UDC_SYSCON1_REG &= ~UDC_PULLUP_EN; | 1279 | u32 l; |
1280 | |||
1281 | l = omap_readl(OTG_CTRL); | ||
1282 | l &= ~OTG_BSESSVLD; | ||
1283 | omap_writel(l, OTG_CTRL); | ||
1284 | } | ||
1285 | omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN); | ||
1286 | w = omap_readw(UDC_SYSCON1); | ||
1287 | w &= ~UDC_PULLUP_EN; | ||
1288 | omap_writew(w, UDC_SYSCON1); | ||
1280 | } | 1289 | } |
1281 | 1290 | ||
1282 | static struct omap_udc *udc; | 1291 | static struct omap_udc *udc; |
@@ -1304,6 +1313,7 @@ static int omap_vbus_session(struct usb_gadget *gadget, int is_active) | |||
1304 | { | 1313 | { |
1305 | struct omap_udc *udc; | 1314 | struct omap_udc *udc; |
1306 | unsigned long flags; | 1315 | unsigned long flags; |
1316 | u32 l; | ||
1307 | 1317 | ||
1308 | udc = container_of(gadget, struct omap_udc, gadget); | 1318 | udc = container_of(gadget, struct omap_udc, gadget); |
1309 | spin_lock_irqsave(&udc->lock, flags); | 1319 | spin_lock_irqsave(&udc->lock, flags); |
@@ -1311,10 +1321,12 @@ static int omap_vbus_session(struct usb_gadget *gadget, int is_active) | |||
1311 | udc->vbus_active = (is_active != 0); | 1321 | udc->vbus_active = (is_active != 0); |
1312 | if (cpu_is_omap15xx()) { | 1322 | if (cpu_is_omap15xx()) { |
1313 | /* "software" detect, ignored if !VBUS_MODE_1510 */ | 1323 | /* "software" detect, ignored if !VBUS_MODE_1510 */ |
1324 | l = omap_readl(FUNC_MUX_CTRL_0); | ||
1314 | if (is_active) | 1325 | if (is_active) |
1315 | FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510; | 1326 | l |= VBUS_CTRL_1510; |
1316 | else | 1327 | else |
1317 | FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510; | 1328 | l &= ~VBUS_CTRL_1510; |
1329 | omap_writel(l, FUNC_MUX_CTRL_0); | ||
1318 | } | 1330 | } |
1319 | if (udc->dc_clk != NULL && is_active) { | 1331 | if (udc->dc_clk != NULL && is_active) { |
1320 | if (!udc->clk_requested) { | 1332 | if (!udc->clk_requested) { |
@@ -1384,9 +1396,9 @@ static void nuke(struct omap_ep *ep, int status) | |||
1384 | dma_channel_release(ep); | 1396 | dma_channel_release(ep); |
1385 | 1397 | ||
1386 | use_ep(ep, 0); | 1398 | use_ep(ep, 0); |
1387 | UDC_CTRL_REG = UDC_CLR_EP; | 1399 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1388 | if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC) | 1400 | if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC) |
1389 | UDC_CTRL_REG = UDC_SET_HALT; | 1401 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1390 | 1402 | ||
1391 | while (!list_empty(&ep->queue)) { | 1403 | while (!list_empty(&ep->queue)) { |
1392 | req = list_entry(ep->queue.next, struct omap_req, queue); | 1404 | req = list_entry(ep->queue.next, struct omap_req, queue); |
@@ -1414,8 +1426,8 @@ static void update_otg(struct omap_udc *udc) | |||
1414 | if (!gadget_is_otg(&udc->gadget)) | 1426 | if (!gadget_is_otg(&udc->gadget)) |
1415 | return; | 1427 | return; |
1416 | 1428 | ||
1417 | if (OTG_CTRL_REG & OTG_ID) | 1429 | if (omap_readl(OTG_CTRL) & OTG_ID) |
1418 | devstat = UDC_DEVSTAT_REG; | 1430 | devstat = omap_readw(UDC_DEVSTAT); |
1419 | else | 1431 | else |
1420 | devstat = 0; | 1432 | devstat = 0; |
1421 | 1433 | ||
@@ -1426,9 +1438,14 @@ static void update_otg(struct omap_udc *udc) | |||
1426 | /* Enable HNP early, avoiding races on suspend irq path. | 1438 | /* Enable HNP early, avoiding races on suspend irq path. |
1427 | * ASSUMES OTG state machine B_BUS_REQ input is true. | 1439 | * ASSUMES OTG state machine B_BUS_REQ input is true. |
1428 | */ | 1440 | */ |
1429 | if (udc->gadget.b_hnp_enable) | 1441 | if (udc->gadget.b_hnp_enable) { |
1430 | OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ) | 1442 | u32 l; |
1431 | & ~OTG_PULLUP; | 1443 | |
1444 | l = omap_readl(OTG_CTRL); | ||
1445 | l |= OTG_B_HNPEN | OTG_B_BUSREQ; | ||
1446 | l &= ~OTG_PULLUP; | ||
1447 | omap_writel(l, OTG_CTRL); | ||
1448 | } | ||
1432 | } | 1449 | } |
1433 | 1450 | ||
1434 | static void ep0_irq(struct omap_udc *udc, u16 irq_src) | 1451 | static void ep0_irq(struct omap_udc *udc, u16 irq_src) |
@@ -1446,7 +1463,7 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1446 | 1463 | ||
1447 | nuke(ep0, 0); | 1464 | nuke(ep0, 0); |
1448 | if (ack) { | 1465 | if (ack) { |
1449 | UDC_IRQ_SRC_REG = ack; | 1466 | omap_writew(ack, UDC_IRQ_SRC); |
1450 | irq_src = UDC_SETUP; | 1467 | irq_src = UDC_SETUP; |
1451 | } | 1468 | } |
1452 | } | 1469 | } |
@@ -1466,9 +1483,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1466 | if (irq_src & UDC_EP0_TX) { | 1483 | if (irq_src & UDC_EP0_TX) { |
1467 | int stat; | 1484 | int stat; |
1468 | 1485 | ||
1469 | UDC_IRQ_SRC_REG = UDC_EP0_TX; | 1486 | omap_writew(UDC_EP0_TX, UDC_IRQ_SRC); |
1470 | UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; | 1487 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); |
1471 | stat = UDC_STAT_FLG_REG; | 1488 | stat = omap_readw(UDC_STAT_FLG); |
1472 | if (stat & UDC_ACK) { | 1489 | if (stat & UDC_ACK) { |
1473 | if (udc->ep0_in) { | 1490 | if (udc->ep0_in) { |
1474 | /* write next IN packet from response, | 1491 | /* write next IN packet from response, |
@@ -1476,26 +1493,26 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1476 | */ | 1493 | */ |
1477 | if (req) | 1494 | if (req) |
1478 | stat = write_fifo(ep0, req); | 1495 | stat = write_fifo(ep0, req); |
1479 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1496 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1480 | if (!req && udc->ep0_pending) { | 1497 | if (!req && udc->ep0_pending) { |
1481 | UDC_EP_NUM_REG = UDC_EP_SEL; | 1498 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); |
1482 | UDC_CTRL_REG = UDC_CLR_EP; | 1499 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1483 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1500 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1484 | UDC_EP_NUM_REG = 0; | 1501 | omap_writew(0, UDC_EP_NUM); |
1485 | udc->ep0_pending = 0; | 1502 | udc->ep0_pending = 0; |
1486 | } /* else: 6 wait states before it'll tx */ | 1503 | } /* else: 6 wait states before it'll tx */ |
1487 | } else { | 1504 | } else { |
1488 | /* ack status stage of OUT transfer */ | 1505 | /* ack status stage of OUT transfer */ |
1489 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1506 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1490 | if (req) | 1507 | if (req) |
1491 | done(ep0, req, 0); | 1508 | done(ep0, req, 0); |
1492 | } | 1509 | } |
1493 | req = NULL; | 1510 | req = NULL; |
1494 | } else if (stat & UDC_STALL) { | 1511 | } else if (stat & UDC_STALL) { |
1495 | UDC_CTRL_REG = UDC_CLR_HALT; | 1512 | omap_writew(UDC_CLR_HALT, UDC_CTRL); |
1496 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1513 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1497 | } else { | 1514 | } else { |
1498 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1515 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1499 | } | 1516 | } |
1500 | } | 1517 | } |
1501 | 1518 | ||
@@ -1503,9 +1520,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1503 | if (irq_src & UDC_EP0_RX) { | 1520 | if (irq_src & UDC_EP0_RX) { |
1504 | int stat; | 1521 | int stat; |
1505 | 1522 | ||
1506 | UDC_IRQ_SRC_REG = UDC_EP0_RX; | 1523 | omap_writew(UDC_EP0_RX, UDC_IRQ_SRC); |
1507 | UDC_EP_NUM_REG = UDC_EP_SEL; | 1524 | omap_writew(UDC_EP_SEL, UDC_EP_NUM); |
1508 | stat = UDC_STAT_FLG_REG; | 1525 | stat = omap_readw(UDC_STAT_FLG); |
1509 | if (stat & UDC_ACK) { | 1526 | if (stat & UDC_ACK) { |
1510 | if (!udc->ep0_in) { | 1527 | if (!udc->ep0_in) { |
1511 | stat = 0; | 1528 | stat = 0; |
@@ -1513,34 +1530,35 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1513 | * reactiviting the fifo; stall on errors. | 1530 | * reactiviting the fifo; stall on errors. |
1514 | */ | 1531 | */ |
1515 | if (!req || (stat = read_fifo(ep0, req)) < 0) { | 1532 | if (!req || (stat = read_fifo(ep0, req)) < 0) { |
1516 | UDC_SYSCON2_REG = UDC_STALL_CMD; | 1533 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1517 | udc->ep0_pending = 0; | 1534 | udc->ep0_pending = 0; |
1518 | stat = 0; | 1535 | stat = 0; |
1519 | } else if (stat == 0) | 1536 | } else if (stat == 0) |
1520 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1537 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1521 | UDC_EP_NUM_REG = 0; | 1538 | omap_writew(0, UDC_EP_NUM); |
1522 | 1539 | ||
1523 | /* activate status stage */ | 1540 | /* activate status stage */ |
1524 | if (stat == 1) { | 1541 | if (stat == 1) { |
1525 | done(ep0, req, 0); | 1542 | done(ep0, req, 0); |
1526 | /* that may have STALLed ep0... */ | 1543 | /* that may have STALLed ep0... */ |
1527 | UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; | 1544 | omap_writew(UDC_EP_SEL | UDC_EP_DIR, |
1528 | UDC_CTRL_REG = UDC_CLR_EP; | 1545 | UDC_EP_NUM); |
1529 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1546 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1530 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1547 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1548 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); | ||
1531 | udc->ep0_pending = 0; | 1549 | udc->ep0_pending = 0; |
1532 | } | 1550 | } |
1533 | } else { | 1551 | } else { |
1534 | /* ack status stage of IN transfer */ | 1552 | /* ack status stage of IN transfer */ |
1535 | UDC_EP_NUM_REG = 0; | 1553 | omap_writew(0, UDC_EP_NUM); |
1536 | if (req) | 1554 | if (req) |
1537 | done(ep0, req, 0); | 1555 | done(ep0, req, 0); |
1538 | } | 1556 | } |
1539 | } else if (stat & UDC_STALL) { | 1557 | } else if (stat & UDC_STALL) { |
1540 | UDC_CTRL_REG = UDC_CLR_HALT; | 1558 | omap_writew(UDC_CLR_HALT, UDC_CTRL); |
1541 | UDC_EP_NUM_REG = 0; | 1559 | omap_writew(0, UDC_EP_NUM); |
1542 | } else { | 1560 | } else { |
1543 | UDC_EP_NUM_REG = 0; | 1561 | omap_writew(0, UDC_EP_NUM); |
1544 | } | 1562 | } |
1545 | } | 1563 | } |
1546 | 1564 | ||
@@ -1555,14 +1573,14 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1555 | 1573 | ||
1556 | /* read the (latest) SETUP message */ | 1574 | /* read the (latest) SETUP message */ |
1557 | do { | 1575 | do { |
1558 | UDC_EP_NUM_REG = UDC_SETUP_SEL; | 1576 | omap_writew(UDC_SETUP_SEL, UDC_EP_NUM); |
1559 | /* two bytes at a time */ | 1577 | /* two bytes at a time */ |
1560 | u.word[0] = UDC_DATA_REG; | 1578 | u.word[0] = omap_readw(UDC_DATA); |
1561 | u.word[1] = UDC_DATA_REG; | 1579 | u.word[1] = omap_readw(UDC_DATA); |
1562 | u.word[2] = UDC_DATA_REG; | 1580 | u.word[2] = omap_readw(UDC_DATA); |
1563 | u.word[3] = UDC_DATA_REG; | 1581 | u.word[3] = omap_readw(UDC_DATA); |
1564 | UDC_EP_NUM_REG = 0; | 1582 | omap_writew(0, UDC_EP_NUM); |
1565 | } while (UDC_IRQ_SRC_REG & UDC_SETUP); | 1583 | } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP); |
1566 | 1584 | ||
1567 | #define w_value le16_to_cpu(u.r.wValue) | 1585 | #define w_value le16_to_cpu(u.r.wValue) |
1568 | #define w_index le16_to_cpu(u.r.wIndex) | 1586 | #define w_index le16_to_cpu(u.r.wIndex) |
@@ -1593,9 +1611,9 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1593 | * later if it fails the request. | 1611 | * later if it fails the request. |
1594 | */ | 1612 | */ |
1595 | if (udc->ep0_reset_config) | 1613 | if (udc->ep0_reset_config) |
1596 | UDC_SYSCON2_REG = UDC_CLR_CFG; | 1614 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1597 | else | 1615 | else |
1598 | UDC_SYSCON2_REG = UDC_DEV_CFG; | 1616 | omap_writew(UDC_DEV_CFG, UDC_SYSCON2); |
1599 | update_otg(udc); | 1617 | update_otg(udc); |
1600 | goto delegate; | 1618 | goto delegate; |
1601 | case USB_REQ_CLEAR_FEATURE: | 1619 | case USB_REQ_CLEAR_FEATURE: |
@@ -1613,10 +1631,10 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1613 | || !ep->desc) | 1631 | || !ep->desc) |
1614 | goto do_stall; | 1632 | goto do_stall; |
1615 | use_ep(ep, 0); | 1633 | use_ep(ep, 0); |
1616 | UDC_CTRL_REG = udc->clr_halt; | 1634 | omap_writew(udc->clr_halt, UDC_CTRL); |
1617 | ep->ackwait = 0; | 1635 | ep->ackwait = 0; |
1618 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { | 1636 | if (!(ep->bEndpointAddress & USB_DIR_IN)) { |
1619 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1637 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1620 | ep->ackwait = 1 + ep->double_buf; | 1638 | ep->ackwait = 1 + ep->double_buf; |
1621 | } | 1639 | } |
1622 | /* NOTE: assumes the host behaves sanely, | 1640 | /* NOTE: assumes the host behaves sanely, |
@@ -1649,15 +1667,15 @@ static void ep0_irq(struct omap_udc *udc, u16 irq_src) | |||
1649 | } | 1667 | } |
1650 | use_ep(ep, 0); | 1668 | use_ep(ep, 0); |
1651 | /* can't halt if fifo isn't empty... */ | 1669 | /* can't halt if fifo isn't empty... */ |
1652 | UDC_CTRL_REG = UDC_CLR_EP; | 1670 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1653 | UDC_CTRL_REG = UDC_SET_HALT; | 1671 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
1654 | VDBG("%s halted by host\n", ep->name); | 1672 | VDBG("%s halted by host\n", ep->name); |
1655 | ep0out_status_stage: | 1673 | ep0out_status_stage: |
1656 | status = 0; | 1674 | status = 0; |
1657 | UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; | 1675 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); |
1658 | UDC_CTRL_REG = UDC_CLR_EP; | 1676 | omap_writew(UDC_CLR_EP, UDC_CTRL); |
1659 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1677 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1660 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1678 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1661 | udc->ep0_pending = 0; | 1679 | udc->ep0_pending = 0; |
1662 | break; | 1680 | break; |
1663 | case USB_REQ_GET_STATUS: | 1681 | case USB_REQ_GET_STATUS: |
@@ -1694,10 +1712,10 @@ intf_status: | |||
1694 | 1712 | ||
1695 | zero_status: | 1713 | zero_status: |
1696 | /* return two zero bytes */ | 1714 | /* return two zero bytes */ |
1697 | UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR; | 1715 | omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM); |
1698 | UDC_DATA_REG = 0; | 1716 | omap_writew(0, UDC_DATA); |
1699 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1717 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1700 | UDC_EP_NUM_REG = UDC_EP_DIR; | 1718 | omap_writew(UDC_EP_DIR, UDC_EP_NUM); |
1701 | status = 0; | 1719 | status = 0; |
1702 | VDBG("GET_STATUS, interface %d\n", w_index); | 1720 | VDBG("GET_STATUS, interface %d\n", w_index); |
1703 | /* next, status stage */ | 1721 | /* next, status stage */ |
@@ -1706,8 +1724,8 @@ zero_status: | |||
1706 | delegate: | 1724 | delegate: |
1707 | /* activate the ep0out fifo right away */ | 1725 | /* activate the ep0out fifo right away */ |
1708 | if (!udc->ep0_in && w_length) { | 1726 | if (!udc->ep0_in && w_length) { |
1709 | UDC_EP_NUM_REG = 0; | 1727 | omap_writew(0, UDC_EP_NUM); |
1710 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1728 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1711 | } | 1729 | } |
1712 | 1730 | ||
1713 | /* gadget drivers see class/vendor specific requests, | 1731 | /* gadget drivers see class/vendor specific requests, |
@@ -1748,9 +1766,9 @@ do_stall: | |||
1748 | if (udc->ep0_reset_config) | 1766 | if (udc->ep0_reset_config) |
1749 | WARN("error resetting config?\n"); | 1767 | WARN("error resetting config?\n"); |
1750 | else | 1768 | else |
1751 | UDC_SYSCON2_REG = UDC_CLR_CFG; | 1769 | omap_writew(UDC_CLR_CFG, UDC_SYSCON2); |
1752 | } | 1770 | } |
1753 | UDC_SYSCON2_REG = UDC_STALL_CMD; | 1771 | omap_writew(UDC_STALL_CMD, UDC_SYSCON2); |
1754 | udc->ep0_pending = 0; | 1772 | udc->ep0_pending = 0; |
1755 | } | 1773 | } |
1756 | } | 1774 | } |
@@ -1764,7 +1782,7 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src) | |||
1764 | { | 1782 | { |
1765 | u16 devstat, change; | 1783 | u16 devstat, change; |
1766 | 1784 | ||
1767 | devstat = UDC_DEVSTAT_REG; | 1785 | devstat = omap_readw(UDC_DEVSTAT); |
1768 | change = devstat ^ udc->devstat; | 1786 | change = devstat ^ udc->devstat; |
1769 | udc->devstat = devstat; | 1787 | udc->devstat = devstat; |
1770 | 1788 | ||
@@ -1804,7 +1822,8 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src) | |||
1804 | INFO("USB reset done, gadget %s\n", | 1822 | INFO("USB reset done, gadget %s\n", |
1805 | udc->driver->driver.name); | 1823 | udc->driver->driver.name); |
1806 | /* ep0 traffic is legal from now on */ | 1824 | /* ep0 traffic is legal from now on */ |
1807 | UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE; | 1825 | omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE, |
1826 | UDC_IRQ_EN); | ||
1808 | } | 1827 | } |
1809 | change &= ~UDC_USB_RESET; | 1828 | change &= ~UDC_USB_RESET; |
1810 | } | 1829 | } |
@@ -1848,7 +1867,7 @@ static void devstate_irq(struct omap_udc *udc, u16 irq_src) | |||
1848 | VDBG("devstat %03x, ignore change %03x\n", | 1867 | VDBG("devstat %03x, ignore change %03x\n", |
1849 | devstat, change); | 1868 | devstat, change); |
1850 | 1869 | ||
1851 | UDC_IRQ_SRC_REG = UDC_DS_CHG; | 1870 | omap_writew(UDC_DS_CHG, UDC_IRQ_SRC); |
1852 | } | 1871 | } |
1853 | 1872 | ||
1854 | static irqreturn_t omap_udc_irq(int irq, void *_udc) | 1873 | static irqreturn_t omap_udc_irq(int irq, void *_udc) |
@@ -1859,7 +1878,7 @@ static irqreturn_t omap_udc_irq(int irq, void *_udc) | |||
1859 | unsigned long flags; | 1878 | unsigned long flags; |
1860 | 1879 | ||
1861 | spin_lock_irqsave(&udc->lock, flags); | 1880 | spin_lock_irqsave(&udc->lock, flags); |
1862 | irq_src = UDC_IRQ_SRC_REG; | 1881 | irq_src = omap_readw(UDC_IRQ_SRC); |
1863 | 1882 | ||
1864 | /* Device state change (usb ch9 stuff) */ | 1883 | /* Device state change (usb ch9 stuff) */ |
1865 | if (irq_src & UDC_DS_CHG) { | 1884 | if (irq_src & UDC_DS_CHG) { |
@@ -1882,7 +1901,7 @@ static irqreturn_t omap_udc_irq(int irq, void *_udc) | |||
1882 | irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT); | 1901 | irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT); |
1883 | } | 1902 | } |
1884 | 1903 | ||
1885 | irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX); | 1904 | irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX); |
1886 | if (irq_src) | 1905 | if (irq_src) |
1887 | DBG("udc_irq, unhandled %03x\n", irq_src); | 1906 | DBG("udc_irq, unhandled %03x\n", irq_src); |
1888 | spin_unlock_irqrestore(&udc->lock, flags); | 1907 | spin_unlock_irqrestore(&udc->lock, flags); |
@@ -1903,7 +1922,7 @@ static void pio_out_timer(unsigned long _ep) | |||
1903 | spin_lock_irqsave(&ep->udc->lock, flags); | 1922 | spin_lock_irqsave(&ep->udc->lock, flags); |
1904 | if (!list_empty(&ep->queue) && ep->ackwait) { | 1923 | if (!list_empty(&ep->queue) && ep->ackwait) { |
1905 | use_ep(ep, UDC_EP_SEL); | 1924 | use_ep(ep, UDC_EP_SEL); |
1906 | stat_flg = UDC_STAT_FLG_REG; | 1925 | stat_flg = omap_readw(UDC_STAT_FLG); |
1907 | 1926 | ||
1908 | if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN) | 1927 | if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN) |
1909 | || (ep->double_buf && HALF_FULL(stat_flg)))) { | 1928 | || (ep->double_buf && HALF_FULL(stat_flg)))) { |
@@ -1913,8 +1932,8 @@ static void pio_out_timer(unsigned long _ep) | |||
1913 | req = container_of(ep->queue.next, | 1932 | req = container_of(ep->queue.next, |
1914 | struct omap_req, queue); | 1933 | struct omap_req, queue); |
1915 | (void) read_fifo(ep, req); | 1934 | (void) read_fifo(ep, req); |
1916 | UDC_EP_NUM_REG = ep->bEndpointAddress; | 1935 | omap_writew(ep->bEndpointAddress, UDC_EP_NUM); |
1917 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1936 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1918 | ep->ackwait = 1 + ep->double_buf; | 1937 | ep->ackwait = 1 + ep->double_buf; |
1919 | } else | 1938 | } else |
1920 | deselect_ep(); | 1939 | deselect_ep(); |
@@ -1934,20 +1953,20 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) | |||
1934 | unsigned long flags; | 1953 | unsigned long flags; |
1935 | 1954 | ||
1936 | spin_lock_irqsave(&udc->lock, flags); | 1955 | spin_lock_irqsave(&udc->lock, flags); |
1937 | epn_stat = UDC_EPN_STAT_REG; | 1956 | epn_stat = omap_readw(UDC_EPN_STAT); |
1938 | irq_src = UDC_IRQ_SRC_REG; | 1957 | irq_src = omap_readw(UDC_IRQ_SRC); |
1939 | 1958 | ||
1940 | /* handle OUT first, to avoid some wasteful NAKs */ | 1959 | /* handle OUT first, to avoid some wasteful NAKs */ |
1941 | if (irq_src & UDC_EPN_RX) { | 1960 | if (irq_src & UDC_EPN_RX) { |
1942 | epnum = (epn_stat >> 8) & 0x0f; | 1961 | epnum = (epn_stat >> 8) & 0x0f; |
1943 | UDC_IRQ_SRC_REG = UDC_EPN_RX; | 1962 | omap_writew(UDC_EPN_RX, UDC_IRQ_SRC); |
1944 | status = IRQ_HANDLED; | 1963 | status = IRQ_HANDLED; |
1945 | ep = &udc->ep[epnum]; | 1964 | ep = &udc->ep[epnum]; |
1946 | ep->irqs++; | 1965 | ep->irqs++; |
1947 | 1966 | ||
1948 | UDC_EP_NUM_REG = epnum | UDC_EP_SEL; | 1967 | omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM); |
1949 | ep->fnf = 0; | 1968 | ep->fnf = 0; |
1950 | if ((UDC_STAT_FLG_REG & UDC_ACK)) { | 1969 | if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { |
1951 | ep->ackwait--; | 1970 | ep->ackwait--; |
1952 | if (!list_empty(&ep->queue)) { | 1971 | if (!list_empty(&ep->queue)) { |
1953 | int stat; | 1972 | int stat; |
@@ -1959,15 +1978,15 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) | |||
1959 | } | 1978 | } |
1960 | } | 1979 | } |
1961 | /* min 6 clock delay before clearing EP_SEL ... */ | 1980 | /* min 6 clock delay before clearing EP_SEL ... */ |
1962 | epn_stat = UDC_EPN_STAT_REG; | 1981 | epn_stat = omap_readw(UDC_EPN_STAT); |
1963 | epn_stat = UDC_EPN_STAT_REG; | 1982 | epn_stat = omap_readw(UDC_EPN_STAT); |
1964 | UDC_EP_NUM_REG = epnum; | 1983 | omap_writew(epnum, UDC_EP_NUM); |
1965 | 1984 | ||
1966 | /* enabling fifo _after_ clearing ACK, contrary to docs, | 1985 | /* enabling fifo _after_ clearing ACK, contrary to docs, |
1967 | * reduces lossage; timer still needed though (sigh). | 1986 | * reduces lossage; timer still needed though (sigh). |
1968 | */ | 1987 | */ |
1969 | if (ep->fnf) { | 1988 | if (ep->fnf) { |
1970 | UDC_CTRL_REG = UDC_SET_FIFO_EN; | 1989 | omap_writew(UDC_SET_FIFO_EN, UDC_CTRL); |
1971 | ep->ackwait = 1 + ep->double_buf; | 1990 | ep->ackwait = 1 + ep->double_buf; |
1972 | } | 1991 | } |
1973 | mod_timer(&ep->timer, PIO_OUT_TIMEOUT); | 1992 | mod_timer(&ep->timer, PIO_OUT_TIMEOUT); |
@@ -1976,13 +1995,13 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) | |||
1976 | /* then IN transfers */ | 1995 | /* then IN transfers */ |
1977 | else if (irq_src & UDC_EPN_TX) { | 1996 | else if (irq_src & UDC_EPN_TX) { |
1978 | epnum = epn_stat & 0x0f; | 1997 | epnum = epn_stat & 0x0f; |
1979 | UDC_IRQ_SRC_REG = UDC_EPN_TX; | 1998 | omap_writew(UDC_EPN_TX, UDC_IRQ_SRC); |
1980 | status = IRQ_HANDLED; | 1999 | status = IRQ_HANDLED; |
1981 | ep = &udc->ep[16 + epnum]; | 2000 | ep = &udc->ep[16 + epnum]; |
1982 | ep->irqs++; | 2001 | ep->irqs++; |
1983 | 2002 | ||
1984 | UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL; | 2003 | omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM); |
1985 | if ((UDC_STAT_FLG_REG & UDC_ACK)) { | 2004 | if (omap_readw(UDC_STAT_FLG) & UDC_ACK) { |
1986 | ep->ackwait = 0; | 2005 | ep->ackwait = 0; |
1987 | if (!list_empty(&ep->queue)) { | 2006 | if (!list_empty(&ep->queue)) { |
1988 | req = container_of(ep->queue.next, | 2007 | req = container_of(ep->queue.next, |
@@ -1991,9 +2010,9 @@ static irqreturn_t omap_udc_pio_irq(int irq, void *_dev) | |||
1991 | } | 2010 | } |
1992 | } | 2011 | } |
1993 | /* min 6 clock delay before clearing EP_SEL ... */ | 2012 | /* min 6 clock delay before clearing EP_SEL ... */ |
1994 | epn_stat = UDC_EPN_STAT_REG; | 2013 | epn_stat = omap_readw(UDC_EPN_STAT); |
1995 | epn_stat = UDC_EPN_STAT_REG; | 2014 | epn_stat = omap_readw(UDC_EPN_STAT); |
1996 | UDC_EP_NUM_REG = epnum | UDC_EP_DIR; | 2015 | omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM); |
1997 | /* then 6 clocks before it'd tx */ | 2016 | /* then 6 clocks before it'd tx */ |
1998 | } | 2017 | } |
1999 | 2018 | ||
@@ -2021,7 +2040,7 @@ static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) | |||
2021 | req = list_entry(ep->queue.next, struct omap_req, queue); | 2040 | req = list_entry(ep->queue.next, struct omap_req, queue); |
2022 | 2041 | ||
2023 | use_ep(ep, UDC_EP_SEL); | 2042 | use_ep(ep, UDC_EP_SEL); |
2024 | stat = UDC_STAT_FLG_REG; | 2043 | stat = omap_readw(UDC_STAT_FLG); |
2025 | 2044 | ||
2026 | /* NOTE: like the other controller drivers, this isn't | 2045 | /* NOTE: like the other controller drivers, this isn't |
2027 | * currently reporting lost or damaged frames. | 2046 | * currently reporting lost or damaged frames. |
@@ -2053,9 +2072,14 @@ static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) | |||
2053 | if (!list_empty(&ep->queue)) | 2072 | if (!list_empty(&ep->queue)) |
2054 | pending = 1; | 2073 | pending = 1; |
2055 | } | 2074 | } |
2056 | if (!pending) | 2075 | if (!pending) { |
2057 | UDC_IRQ_EN_REG &= ~UDC_SOF_IE; | 2076 | u16 w; |
2058 | UDC_IRQ_SRC_REG = UDC_SOF; | 2077 | |
2078 | w = omap_readw(UDC_IRQ_EN); | ||
2079 | w &= ~UDC_SOF_IE; | ||
2080 | omap_writew(w, UDC_IRQ_EN); | ||
2081 | } | ||
2082 | omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC); | ||
2059 | 2083 | ||
2060 | spin_unlock_irqrestore(&udc->lock, flags); | 2084 | spin_unlock_irqrestore(&udc->lock, flags); |
2061 | return IRQ_HANDLED; | 2085 | return IRQ_HANDLED; |
@@ -2104,7 +2128,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver) | |||
2104 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) | 2128 | if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) |
2105 | continue; | 2129 | continue; |
2106 | use_ep(ep, 0); | 2130 | use_ep(ep, 0); |
2107 | UDC_CTRL_REG = UDC_SET_HALT; | 2131 | omap_writew(UDC_SET_HALT, UDC_CTRL); |
2108 | } | 2132 | } |
2109 | udc->ep0_pending = 0; | 2133 | udc->ep0_pending = 0; |
2110 | udc->ep[0].irqs = 0; | 2134 | udc->ep[0].irqs = 0; |
@@ -2128,7 +2152,7 @@ int usb_gadget_register_driver (struct usb_gadget_driver *driver) | |||
2128 | } | 2152 | } |
2129 | DBG("bound to driver %s\n", driver->driver.name); | 2153 | DBG("bound to driver %s\n", driver->driver.name); |
2130 | 2154 | ||
2131 | UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK; | 2155 | omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); |
2132 | 2156 | ||
2133 | /* connect to bus through transceiver */ | 2157 | /* connect to bus through transceiver */ |
2134 | if (udc->transceiver) { | 2158 | if (udc->transceiver) { |
@@ -2225,7 +2249,7 @@ static void proc_ep_show(struct seq_file *s, struct omap_ep *ep) | |||
2225 | else | 2249 | else |
2226 | buf[0] = 0; | 2250 | buf[0] = 0; |
2227 | 2251 | ||
2228 | stat_flg = UDC_STAT_FLG_REG; | 2252 | stat_flg = omap_readw(UDC_STAT_FLG); |
2229 | seq_printf(s, | 2253 | seq_printf(s, |
2230 | "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n", | 2254 | "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n", |
2231 | ep->name, buf, | 2255 | ep->name, buf, |
@@ -2292,11 +2316,11 @@ static int proc_otg_show(struct seq_file *s) | |||
2292 | trans = CONTROL_DEVCONF_REG; | 2316 | trans = CONTROL_DEVCONF_REG; |
2293 | } else { | 2317 | } else { |
2294 | ctrl_name = "tranceiver_ctrl"; | 2318 | ctrl_name = "tranceiver_ctrl"; |
2295 | trans = USB_TRANSCEIVER_CTRL_REG; | 2319 | trans = omap_readw(USB_TRANSCEIVER_CTRL); |
2296 | } | 2320 | } |
2297 | seq_printf(s, "\nOTG rev %d.%d, %s %05x\n", | 2321 | seq_printf(s, "\nOTG rev %d.%d, %s %05x\n", |
2298 | tmp >> 4, tmp & 0xf, ctrl_name, trans); | 2322 | tmp >> 4, tmp & 0xf, ctrl_name, trans); |
2299 | tmp = OTG_SYSCON_1_REG; | 2323 | tmp = omap_readw(OTG_SYSCON_1); |
2300 | seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," | 2324 | seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s," |
2301 | FOURBITS "\n", tmp, | 2325 | FOURBITS "\n", tmp, |
2302 | trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), | 2326 | trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R), |
@@ -2308,7 +2332,7 @@ static int proc_otg_show(struct seq_file *s) | |||
2308 | (tmp & HST_IDLE_EN) ? " !host" : "", | 2332 | (tmp & HST_IDLE_EN) ? " !host" : "", |
2309 | (tmp & DEV_IDLE_EN) ? " !dev" : "", | 2333 | (tmp & DEV_IDLE_EN) ? " !dev" : "", |
2310 | (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active"); | 2334 | (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active"); |
2311 | tmp = OTG_SYSCON_2_REG; | 2335 | tmp = omap_readl(OTG_SYSCON_2); |
2312 | seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS | 2336 | seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS |
2313 | " b_ase_brst=%d hmc=%d\n", tmp, | 2337 | " b_ase_brst=%d hmc=%d\n", tmp, |
2314 | (tmp & OTG_EN) ? " otg_en" : "", | 2338 | (tmp & OTG_EN) ? " otg_en" : "", |
@@ -2323,7 +2347,7 @@ static int proc_otg_show(struct seq_file *s) | |||
2323 | (tmp & HMC_TLLATTACH) ? " tllattach" : "", | 2347 | (tmp & HMC_TLLATTACH) ? " tllattach" : "", |
2324 | B_ASE_BRST(tmp), | 2348 | B_ASE_BRST(tmp), |
2325 | OTG_HMC(tmp)); | 2349 | OTG_HMC(tmp)); |
2326 | tmp = OTG_CTRL_REG; | 2350 | tmp = omap_readl(OTG_CTRL); |
2327 | seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp, | 2351 | seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp, |
2328 | (tmp & OTG_ASESSVLD) ? " asess" : "", | 2352 | (tmp & OTG_ASESSVLD) ? " asess" : "", |
2329 | (tmp & OTG_BSESSEND) ? " bsess_end" : "", | 2353 | (tmp & OTG_BSESSEND) ? " bsess_end" : "", |
@@ -2343,13 +2367,13 @@ static int proc_otg_show(struct seq_file *s) | |||
2343 | (tmp & OTG_PU_VBUS) ? " pu_vb" : "", | 2367 | (tmp & OTG_PU_VBUS) ? " pu_vb" : "", |
2344 | (tmp & OTG_PU_ID) ? " pu_id" : "" | 2368 | (tmp & OTG_PU_ID) ? " pu_id" : "" |
2345 | ); | 2369 | ); |
2346 | tmp = OTG_IRQ_EN_REG; | 2370 | tmp = omap_readw(OTG_IRQ_EN); |
2347 | seq_printf(s, "otg_irq_en %04x" "\n", tmp); | 2371 | seq_printf(s, "otg_irq_en %04x" "\n", tmp); |
2348 | tmp = OTG_IRQ_SRC_REG; | 2372 | tmp = omap_readw(OTG_IRQ_SRC); |
2349 | seq_printf(s, "otg_irq_src %04x" "\n", tmp); | 2373 | seq_printf(s, "otg_irq_src %04x" "\n", tmp); |
2350 | tmp = OTG_OUTCTRL_REG; | 2374 | tmp = omap_readw(OTG_OUTCTRL); |
2351 | seq_printf(s, "otg_outctrl %04x" "\n", tmp); | 2375 | seq_printf(s, "otg_outctrl %04x" "\n", tmp); |
2352 | tmp = OTG_TEST_REG; | 2376 | tmp = omap_readw(OTG_TEST); |
2353 | seq_printf(s, "otg_test %04x" "\n", tmp); | 2377 | seq_printf(s, "otg_test %04x" "\n", tmp); |
2354 | return 0; | 2378 | return 0; |
2355 | } | 2379 | } |
@@ -2370,7 +2394,7 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2370 | driver_desc, | 2394 | driver_desc, |
2371 | use_dma ? " (dma)" : ""); | 2395 | use_dma ? " (dma)" : ""); |
2372 | 2396 | ||
2373 | tmp = UDC_REV_REG & 0xff; | 2397 | tmp = omap_readw(UDC_REV) & 0xff; |
2374 | seq_printf(s, | 2398 | seq_printf(s, |
2375 | "UDC rev %d.%d, fifo mode %d, gadget %s\n" | 2399 | "UDC rev %d.%d, fifo mode %d, gadget %s\n" |
2376 | "hmc %d, transceiver %s\n", | 2400 | "hmc %d, transceiver %s\n", |
@@ -2384,16 +2408,16 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2384 | ? "external" : "(none)")); | 2408 | ? "external" : "(none)")); |
2385 | if (cpu_class_is_omap1()) { | 2409 | if (cpu_class_is_omap1()) { |
2386 | seq_printf(s, "ULPD control %04x req %04x status %04x\n", | 2410 | seq_printf(s, "ULPD control %04x req %04x status %04x\n", |
2387 | __REG16(ULPD_CLOCK_CTRL), | 2411 | omap_readw(ULPD_CLOCK_CTRL), |
2388 | __REG16(ULPD_SOFT_REQ), | 2412 | omap_readw(ULPD_SOFT_REQ), |
2389 | __REG16(ULPD_STATUS_REQ)); | 2413 | omap_readw(ULPD_STATUS_REQ)); |
2390 | } | 2414 | } |
2391 | 2415 | ||
2392 | /* OTG controller registers */ | 2416 | /* OTG controller registers */ |
2393 | if (!cpu_is_omap15xx()) | 2417 | if (!cpu_is_omap15xx()) |
2394 | proc_otg_show(s); | 2418 | proc_otg_show(s); |
2395 | 2419 | ||
2396 | tmp = UDC_SYSCON1_REG; | 2420 | tmp = omap_readw(UDC_SYSCON1); |
2397 | seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp, | 2421 | seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp, |
2398 | (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "", | 2422 | (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "", |
2399 | (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "", | 2423 | (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "", |
@@ -2412,7 +2436,7 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2412 | return 0; | 2436 | return 0; |
2413 | } | 2437 | } |
2414 | 2438 | ||
2415 | tmp = UDC_DEVSTAT_REG; | 2439 | tmp = omap_readw(UDC_DEVSTAT); |
2416 | seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp, | 2440 | seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp, |
2417 | (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "", | 2441 | (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "", |
2418 | (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "", | 2442 | (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "", |
@@ -2424,20 +2448,20 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2424 | (tmp & UDC_ADD) ? " ADD" : "", | 2448 | (tmp & UDC_ADD) ? " ADD" : "", |
2425 | (tmp & UDC_DEF) ? " DEF" : "", | 2449 | (tmp & UDC_DEF) ? " DEF" : "", |
2426 | (tmp & UDC_ATT) ? " ATT" : ""); | 2450 | (tmp & UDC_ATT) ? " ATT" : ""); |
2427 | seq_printf(s, "sof %04x\n", UDC_SOF_REG); | 2451 | seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF)); |
2428 | tmp = UDC_IRQ_EN_REG; | 2452 | tmp = omap_readw(UDC_IRQ_EN); |
2429 | seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp, | 2453 | seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp, |
2430 | (tmp & UDC_SOF_IE) ? " sof" : "", | 2454 | (tmp & UDC_SOF_IE) ? " sof" : "", |
2431 | (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "", | 2455 | (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "", |
2432 | (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "", | 2456 | (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "", |
2433 | (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "", | 2457 | (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "", |
2434 | (tmp & UDC_EP0_IE) ? " ep0" : ""); | 2458 | (tmp & UDC_EP0_IE) ? " ep0" : ""); |
2435 | tmp = UDC_IRQ_SRC_REG; | 2459 | tmp = omap_readw(UDC_IRQ_SRC); |
2436 | seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp, | 2460 | seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp, |
2437 | (tmp & UDC_TXN_DONE) ? " txn_done" : "", | 2461 | (tmp & UDC_TXN_DONE) ? " txn_done" : "", |
2438 | (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "", | 2462 | (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "", |
2439 | (tmp & UDC_RXN_EOT) ? " rxn_eot" : "", | 2463 | (tmp & UDC_RXN_EOT) ? " rxn_eot" : "", |
2440 | (tmp & UDC_SOF) ? " sof" : "", | 2464 | (tmp & UDC_IRQ_SOF) ? " sof" : "", |
2441 | (tmp & UDC_EPN_RX) ? " epn_rx" : "", | 2465 | (tmp & UDC_EPN_RX) ? " epn_rx" : "", |
2442 | (tmp & UDC_EPN_TX) ? " epn_tx" : "", | 2466 | (tmp & UDC_EPN_TX) ? " epn_tx" : "", |
2443 | (tmp & UDC_DS_CHG) ? " ds_chg" : "", | 2467 | (tmp & UDC_DS_CHG) ? " ds_chg" : "", |
@@ -2447,7 +2471,7 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2447 | if (use_dma) { | 2471 | if (use_dma) { |
2448 | unsigned i; | 2472 | unsigned i; |
2449 | 2473 | ||
2450 | tmp = UDC_DMA_IRQ_EN_REG; | 2474 | tmp = omap_readw(UDC_DMA_IRQ_EN); |
2451 | seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp, | 2475 | seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp, |
2452 | (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "", | 2476 | (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "", |
2453 | (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "", | 2477 | (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "", |
@@ -2461,29 +2485,29 @@ static int proc_udc_show(struct seq_file *s, void *_) | |||
2461 | (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "", | 2485 | (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "", |
2462 | (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : ""); | 2486 | (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : ""); |
2463 | 2487 | ||
2464 | tmp = UDC_RXDMA_CFG_REG; | 2488 | tmp = omap_readw(UDC_RXDMA_CFG); |
2465 | seq_printf(s, "rxdma_cfg %04x\n", tmp); | 2489 | seq_printf(s, "rxdma_cfg %04x\n", tmp); |
2466 | if (tmp) { | 2490 | if (tmp) { |
2467 | for (i = 0; i < 3; i++) { | 2491 | for (i = 0; i < 3; i++) { |
2468 | if ((tmp & (0x0f << (i * 4))) == 0) | 2492 | if ((tmp & (0x0f << (i * 4))) == 0) |
2469 | continue; | 2493 | continue; |
2470 | seq_printf(s, "rxdma[%d] %04x\n", i, | 2494 | seq_printf(s, "rxdma[%d] %04x\n", i, |
2471 | UDC_RXDMA_REG(i + 1)); | 2495 | omap_readw(UDC_RXDMA(i + 1))); |
2472 | } | 2496 | } |
2473 | } | 2497 | } |
2474 | tmp = UDC_TXDMA_CFG_REG; | 2498 | tmp = omap_readw(UDC_TXDMA_CFG); |
2475 | seq_printf(s, "txdma_cfg %04x\n", tmp); | 2499 | seq_printf(s, "txdma_cfg %04x\n", tmp); |
2476 | if (tmp) { | 2500 | if (tmp) { |
2477 | for (i = 0; i < 3; i++) { | 2501 | for (i = 0; i < 3; i++) { |
2478 | if (!(tmp & (0x0f << (i * 4)))) | 2502 | if (!(tmp & (0x0f << (i * 4)))) |
2479 | continue; | 2503 | continue; |
2480 | seq_printf(s, "txdma[%d] %04x\n", i, | 2504 | seq_printf(s, "txdma[%d] %04x\n", i, |
2481 | UDC_TXDMA_REG(i + 1)); | 2505 | omap_readw(UDC_TXDMA(i + 1))); |
2482 | } | 2506 | } |
2483 | } | 2507 | } |
2484 | } | 2508 | } |
2485 | 2509 | ||
2486 | tmp = UDC_DEVSTAT_REG; | 2510 | tmp = omap_readw(UDC_DEVSTAT); |
2487 | if (tmp & UDC_ATT) { | 2511 | if (tmp & UDC_ATT) { |
2488 | proc_ep_show(s, &udc->ep[0]); | 2512 | proc_ep_show(s, &udc->ep[0]); |
2489 | if (tmp & UDC_ADD) { | 2513 | if (tmp & UDC_ADD) { |
@@ -2535,7 +2559,7 @@ static inline void remove_proc_file(void) {} | |||
2535 | * buffer space among the endpoints we'll be operating. | 2559 | * buffer space among the endpoints we'll be operating. |
2536 | * | 2560 | * |
2537 | * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when | 2561 | * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when |
2538 | * UDC_SYSCON_1_REG.CFG_LOCK is set can now work. We won't use that | 2562 | * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that |
2539 | * capability yet though. | 2563 | * capability yet though. |
2540 | */ | 2564 | */ |
2541 | static unsigned __init | 2565 | static unsigned __init |
@@ -2597,9 +2621,9 @@ omap_ep_setup(char *name, u8 addr, u8 type, | |||
2597 | name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf); | 2621 | name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf); |
2598 | 2622 | ||
2599 | if (addr & USB_DIR_IN) | 2623 | if (addr & USB_DIR_IN) |
2600 | UDC_EP_TX_REG(addr & 0xf) = epn_rxtx; | 2624 | omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf)); |
2601 | else | 2625 | else |
2602 | UDC_EP_RX_REG(addr) = epn_rxtx; | 2626 | omap_writew(epn_rxtx, UDC_EP_RX(addr)); |
2603 | 2627 | ||
2604 | /* next endpoint's buffer starts after this one's */ | 2628 | /* next endpoint's buffer starts after this one's */ |
2605 | buf += maxp; | 2629 | buf += maxp; |
@@ -2638,15 +2662,15 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv) | |||
2638 | unsigned tmp, buf; | 2662 | unsigned tmp, buf; |
2639 | 2663 | ||
2640 | /* abolish any previous hardware state */ | 2664 | /* abolish any previous hardware state */ |
2641 | UDC_SYSCON1_REG = 0; | 2665 | omap_writew(0, UDC_SYSCON1); |
2642 | UDC_IRQ_EN_REG = 0; | 2666 | omap_writew(0, UDC_IRQ_EN); |
2643 | UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK; | 2667 | omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC); |
2644 | UDC_DMA_IRQ_EN_REG = 0; | 2668 | omap_writew(0, UDC_DMA_IRQ_EN); |
2645 | UDC_RXDMA_CFG_REG = 0; | 2669 | omap_writew(0, UDC_RXDMA_CFG); |
2646 | UDC_TXDMA_CFG_REG = 0; | 2670 | omap_writew(0, UDC_TXDMA_CFG); |
2647 | 2671 | ||
2648 | /* UDC_PULLUP_EN gates the chip clock */ | 2672 | /* UDC_PULLUP_EN gates the chip clock */ |
2649 | // OTG_SYSCON_1_REG |= DEV_IDLE_EN; | 2673 | // OTG_SYSCON_1 |= DEV_IDLE_EN; |
2650 | 2674 | ||
2651 | udc = kzalloc(sizeof(*udc), GFP_KERNEL); | 2675 | udc = kzalloc(sizeof(*udc), GFP_KERNEL); |
2652 | if (!udc) | 2676 | if (!udc) |
@@ -2677,8 +2701,8 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv) | |||
2677 | 2701 | ||
2678 | /* initially disable all non-ep0 endpoints */ | 2702 | /* initially disable all non-ep0 endpoints */ |
2679 | for (tmp = 1; tmp < 15; tmp++) { | 2703 | for (tmp = 1; tmp < 15; tmp++) { |
2680 | UDC_EP_RX_REG(tmp) = 0; | 2704 | omap_writew(0, UDC_EP_RX(tmp)); |
2681 | UDC_EP_TX_REG(tmp) = 0; | 2705 | omap_writew(0, UDC_EP_TX(tmp)); |
2682 | } | 2706 | } |
2683 | 2707 | ||
2684 | #define OMAP_BULK_EP(name,addr) \ | 2708 | #define OMAP_BULK_EP(name,addr) \ |
@@ -2763,7 +2787,7 @@ omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv) | |||
2763 | ERR("unsupported fifo_mode #%d\n", fifo_mode); | 2787 | ERR("unsupported fifo_mode #%d\n", fifo_mode); |
2764 | return -ENODEV; | 2788 | return -ENODEV; |
2765 | } | 2789 | } |
2766 | UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR; | 2790 | omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1); |
2767 | INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf); | 2791 | INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf); |
2768 | return 0; | 2792 | return 0; |
2769 | } | 2793 | } |
@@ -2807,7 +2831,7 @@ static int __init omap_udc_probe(struct platform_device *pdev) | |||
2807 | } | 2831 | } |
2808 | 2832 | ||
2809 | INFO("OMAP UDC rev %d.%d%s\n", | 2833 | INFO("OMAP UDC rev %d.%d%s\n", |
2810 | UDC_REV_REG >> 4, UDC_REV_REG & 0xf, | 2834 | omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf, |
2811 | config->otg ? ", Mini-AB" : ""); | 2835 | config->otg ? ", Mini-AB" : ""); |
2812 | 2836 | ||
2813 | /* use the mode given to us by board init code */ | 2837 | /* use the mode given to us by board init code */ |
@@ -2822,12 +2846,12 @@ static int __init omap_udc_probe(struct platform_device *pdev) | |||
2822 | * know when to turn PULLUP_EN on/off; and that | 2846 | * know when to turn PULLUP_EN on/off; and that |
2823 | * means we always "need" the 48MHz clock. | 2847 | * means we always "need" the 48MHz clock. |
2824 | */ | 2848 | */ |
2825 | u32 tmp = FUNC_MUX_CTRL_0_REG; | 2849 | u32 tmp = omap_readl(FUNC_MUX_CTRL_0); |
2826 | 2850 | tmp &= ~VBUS_CTRL_1510; | |
2827 | FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510; | 2851 | omap_writel(tmp, FUNC_MUX_CTRL_0); |
2828 | tmp |= VBUS_MODE_1510; | 2852 | tmp |= VBUS_MODE_1510; |
2829 | tmp &= ~VBUS_CTRL_1510; | 2853 | tmp &= ~VBUS_CTRL_1510; |
2830 | FUNC_MUX_CTRL_0_REG = tmp; | 2854 | omap_writel(tmp, FUNC_MUX_CTRL_0); |
2831 | } | 2855 | } |
2832 | } else { | 2856 | } else { |
2833 | /* The transceiver may package some GPIO logic or handle | 2857 | /* The transceiver may package some GPIO logic or handle |
@@ -2907,7 +2931,7 @@ known: | |||
2907 | #endif | 2931 | #endif |
2908 | 2932 | ||
2909 | /* starting with omap1710 es2.0, clear toggle is a separate bit */ | 2933 | /* starting with omap1710 es2.0, clear toggle is a separate bit */ |
2910 | if (UDC_REV_REG >= 0x61) | 2934 | if (omap_readw(UDC_REV) >= 0x61) |
2911 | udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE; | 2935 | udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE; |
2912 | else | 2936 | else |
2913 | udc->clr_halt = UDC_RESET_EP; | 2937 | udc->clr_halt = UDC_RESET_EP; |
@@ -3005,7 +3029,7 @@ static int __exit omap_udc_remove(struct platform_device *pdev) | |||
3005 | put_device(udc->transceiver->dev); | 3029 | put_device(udc->transceiver->dev); |
3006 | udc->transceiver = NULL; | 3030 | udc->transceiver = NULL; |
3007 | } | 3031 | } |
3008 | UDC_SYSCON1_REG = 0; | 3032 | omap_writew(0, UDC_SYSCON1); |
3009 | 3033 | ||
3010 | remove_proc_file(); | 3034 | remove_proc_file(); |
3011 | 3035 | ||
@@ -3036,7 +3060,7 @@ static int __exit omap_udc_remove(struct platform_device *pdev) | |||
3036 | * | 3060 | * |
3037 | * REVISIT we should probably reject suspend requests when there's a host | 3061 | * REVISIT we should probably reject suspend requests when there's a host |
3038 | * session active, rather than disconnecting, at least on boards that can | 3062 | * session active, rather than disconnecting, at least on boards that can |
3039 | * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT). And in any case, we need to | 3063 | * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to |
3040 | * make host resumes and VBUS detection trigger OMAP wakeup events; that | 3064 | * make host resumes and VBUS detection trigger OMAP wakeup events; that |
3041 | * may involve talking to an external transceiver (e.g. isp1301). | 3065 | * may involve talking to an external transceiver (e.g. isp1301). |
3042 | */ | 3066 | */ |
@@ -3045,7 +3069,7 @@ static int omap_udc_suspend(struct platform_device *dev, pm_message_t message) | |||
3045 | { | 3069 | { |
3046 | u32 devstat; | 3070 | u32 devstat; |
3047 | 3071 | ||
3048 | devstat = UDC_DEVSTAT_REG; | 3072 | devstat = omap_readw(UDC_DEVSTAT); |
3049 | 3073 | ||
3050 | /* we're requesting 48 MHz clock if the pullup is enabled | 3074 | /* we're requesting 48 MHz clock if the pullup is enabled |
3051 | * (== we're attached to the host) and we're not suspended, | 3075 | * (== we're attached to the host) and we're not suspended, |
diff --git a/drivers/usb/gadget/omap_udc.h b/drivers/usb/gadget/omap_udc.h index c6b9cbc7230a..8522bbb12278 100644 --- a/drivers/usb/gadget/omap_udc.h +++ b/drivers/usb/gadget/omap_udc.h | |||
@@ -8,23 +8,22 @@ | |||
8 | /* | 8 | /* |
9 | * USB device/endpoint management registers | 9 | * USB device/endpoint management registers |
10 | */ | 10 | */ |
11 | #define UDC_REG(offset) __REG16(UDC_BASE + (offset)) | ||
12 | 11 | ||
13 | #define UDC_REV_REG UDC_REG(0x0) /* Revision */ | 12 | #define UDC_REV (UDC_BASE + 0x0) /* Revision */ |
14 | #define UDC_EP_NUM_REG UDC_REG(0x4) /* Which endpoint */ | 13 | #define UDC_EP_NUM (UDC_BASE + 0x4) /* Which endpoint */ |
15 | # define UDC_SETUP_SEL (1 << 6) | 14 | # define UDC_SETUP_SEL (1 << 6) |
16 | # define UDC_EP_SEL (1 << 5) | 15 | # define UDC_EP_SEL (1 << 5) |
17 | # define UDC_EP_DIR (1 << 4) | 16 | # define UDC_EP_DIR (1 << 4) |
18 | /* low 4 bits for endpoint number */ | 17 | /* low 4 bits for endpoint number */ |
19 | #define UDC_DATA_REG UDC_REG(0x08) /* Endpoint FIFO */ | 18 | #define UDC_DATA (UDC_BASE + 0x08) /* Endpoint FIFO */ |
20 | #define UDC_CTRL_REG UDC_REG(0x0C) /* Endpoint control */ | 19 | #define UDC_CTRL (UDC_BASE + 0x0C) /* Endpoint control */ |
21 | # define UDC_CLR_HALT (1 << 7) | 20 | # define UDC_CLR_HALT (1 << 7) |
22 | # define UDC_SET_HALT (1 << 6) | 21 | # define UDC_SET_HALT (1 << 6) |
23 | # define UDC_CLRDATA_TOGGLE (1 << 3) | 22 | # define UDC_CLRDATA_TOGGLE (1 << 3) |
24 | # define UDC_SET_FIFO_EN (1 << 2) | 23 | # define UDC_SET_FIFO_EN (1 << 2) |
25 | # define UDC_CLR_EP (1 << 1) | 24 | # define UDC_CLR_EP (1 << 1) |
26 | # define UDC_RESET_EP (1 << 0) | 25 | # define UDC_RESET_EP (1 << 0) |
27 | #define UDC_STAT_FLG_REG UDC_REG(0x10) /* Endpoint status */ | 26 | #define UDC_STAT_FLG (UDC_BASE + 0x10) /* Endpoint status */ |
28 | # define UDC_NO_RXPACKET (1 << 15) | 27 | # define UDC_NO_RXPACKET (1 << 15) |
29 | # define UDC_MISS_IN (1 << 14) | 28 | # define UDC_MISS_IN (1 << 14) |
30 | # define UDC_DATA_FLUSH (1 << 13) | 29 | # define UDC_DATA_FLUSH (1 << 13) |
@@ -38,8 +37,8 @@ | |||
38 | # define UDC_FIFO_EN (1 << 2) | 37 | # define UDC_FIFO_EN (1 << 2) |
39 | # define UDC_NON_ISO_FIFO_EMPTY (1 << 1) | 38 | # define UDC_NON_ISO_FIFO_EMPTY (1 << 1) |
40 | # define UDC_NON_ISO_FIFO_FULL (1 << 0) | 39 | # define UDC_NON_ISO_FIFO_FULL (1 << 0) |
41 | #define UDC_RXFSTAT_REG UDC_REG(0x14) /* OUT bytecount */ | 40 | #define UDC_RXFSTAT (UDC_BASE + 0x14) /* OUT bytecount */ |
42 | #define UDC_SYSCON1_REG UDC_REG(0x18) /* System config 1 */ | 41 | #define UDC_SYSCON1 (UDC_BASE + 0x18) /* System config 1 */ |
43 | # define UDC_CFG_LOCK (1 << 8) | 42 | # define UDC_CFG_LOCK (1 << 8) |
44 | # define UDC_DATA_ENDIAN (1 << 7) | 43 | # define UDC_DATA_ENDIAN (1 << 7) |
45 | # define UDC_DMA_ENDIAN (1 << 6) | 44 | # define UDC_DMA_ENDIAN (1 << 6) |
@@ -48,12 +47,12 @@ | |||
48 | # define UDC_SELF_PWR (1 << 2) | 47 | # define UDC_SELF_PWR (1 << 2) |
49 | # define UDC_SOFF_DIS (1 << 1) | 48 | # define UDC_SOFF_DIS (1 << 1) |
50 | # define UDC_PULLUP_EN (1 << 0) | 49 | # define UDC_PULLUP_EN (1 << 0) |
51 | #define UDC_SYSCON2_REG UDC_REG(0x1C) /* System config 2 */ | 50 | #define UDC_SYSCON2 (UDC_BASE + 0x1C) /* System config 2 */ |
52 | # define UDC_RMT_WKP (1 << 6) | 51 | # define UDC_RMT_WKP (1 << 6) |
53 | # define UDC_STALL_CMD (1 << 5) | 52 | # define UDC_STALL_CMD (1 << 5) |
54 | # define UDC_DEV_CFG (1 << 3) | 53 | # define UDC_DEV_CFG (1 << 3) |
55 | # define UDC_CLR_CFG (1 << 2) | 54 | # define UDC_CLR_CFG (1 << 2) |
56 | #define UDC_DEVSTAT_REG UDC_REG(0x20) /* Device status */ | 55 | #define UDC_DEVSTAT (UDC_BASE + 0x20) /* Device status */ |
57 | # define UDC_B_HNP_ENABLE (1 << 9) | 56 | # define UDC_B_HNP_ENABLE (1 << 9) |
58 | # define UDC_A_HNP_SUPPORT (1 << 8) | 57 | # define UDC_A_HNP_SUPPORT (1 << 8) |
59 | # define UDC_A_ALT_HNP_SUPPORT (1 << 7) | 58 | # define UDC_A_ALT_HNP_SUPPORT (1 << 7) |
@@ -64,26 +63,26 @@ | |||
64 | # define UDC_ADD (1 << 2) | 63 | # define UDC_ADD (1 << 2) |
65 | # define UDC_DEF (1 << 1) | 64 | # define UDC_DEF (1 << 1) |
66 | # define UDC_ATT (1 << 0) | 65 | # define UDC_ATT (1 << 0) |
67 | #define UDC_SOF_REG UDC_REG(0x24) /* Start of frame */ | 66 | #define UDC_SOF (UDC_BASE + 0x24) /* Start of frame */ |
68 | # define UDC_FT_LOCK (1 << 12) | 67 | # define UDC_FT_LOCK (1 << 12) |
69 | # define UDC_TS_OK (1 << 11) | 68 | # define UDC_TS_OK (1 << 11) |
70 | # define UDC_TS 0x03ff | 69 | # define UDC_TS 0x03ff |
71 | #define UDC_IRQ_EN_REG UDC_REG(0x28) /* Interrupt enable */ | 70 | #define UDC_IRQ_EN (UDC_BASE + 0x28) /* Interrupt enable */ |
72 | # define UDC_SOF_IE (1 << 7) | 71 | # define UDC_SOF_IE (1 << 7) |
73 | # define UDC_EPN_RX_IE (1 << 5) | 72 | # define UDC_EPN_RX_IE (1 << 5) |
74 | # define UDC_EPN_TX_IE (1 << 4) | 73 | # define UDC_EPN_TX_IE (1 << 4) |
75 | # define UDC_DS_CHG_IE (1 << 3) | 74 | # define UDC_DS_CHG_IE (1 << 3) |
76 | # define UDC_EP0_IE (1 << 0) | 75 | # define UDC_EP0_IE (1 << 0) |
77 | #define UDC_DMA_IRQ_EN_REG UDC_REG(0x2C) /* DMA irq enable */ | 76 | #define UDC_DMA_IRQ_EN (UDC_BASE + 0x2C) /* DMA irq enable */ |
78 | /* rx/tx dma channels numbered 1-3 not 0-2 */ | 77 | /* rx/tx dma channels numbered 1-3 not 0-2 */ |
79 | # define UDC_TX_DONE_IE(n) (1 << (4 * (n) - 2)) | 78 | # define UDC_TX_DONE_IE(n) (1 << (4 * (n) - 2)) |
80 | # define UDC_RX_CNT_IE(n) (1 << (4 * (n) - 3)) | 79 | # define UDC_RX_CNT_IE(n) (1 << (4 * (n) - 3)) |
81 | # define UDC_RX_EOT_IE(n) (1 << (4 * (n) - 4)) | 80 | # define UDC_RX_EOT_IE(n) (1 << (4 * (n) - 4)) |
82 | #define UDC_IRQ_SRC_REG UDC_REG(0x30) /* Interrupt source */ | 81 | #define UDC_IRQ_SRC (UDC_BASE + 0x30) /* Interrupt source */ |
83 | # define UDC_TXN_DONE (1 << 10) | 82 | # define UDC_TXN_DONE (1 << 10) |
84 | # define UDC_RXN_CNT (1 << 9) | 83 | # define UDC_RXN_CNT (1 << 9) |
85 | # define UDC_RXN_EOT (1 << 8) | 84 | # define UDC_RXN_EOT (1 << 8) |
86 | # define UDC_SOF (1 << 7) | 85 | # define UDC_IRQ_SOF (1 << 7) |
87 | # define UDC_EPN_RX (1 << 5) | 86 | # define UDC_EPN_RX (1 << 5) |
88 | # define UDC_EPN_TX (1 << 4) | 87 | # define UDC_EPN_TX (1 << 4) |
89 | # define UDC_DS_CHG (1 << 3) | 88 | # define UDC_DS_CHG (1 << 3) |
@@ -91,41 +90,41 @@ | |||
91 | # define UDC_EP0_RX (1 << 1) | 90 | # define UDC_EP0_RX (1 << 1) |
92 | # define UDC_EP0_TX (1 << 0) | 91 | # define UDC_EP0_TX (1 << 0) |
93 | # define UDC_IRQ_SRC_MASK 0x7bf | 92 | # define UDC_IRQ_SRC_MASK 0x7bf |
94 | #define UDC_EPN_STAT_REG UDC_REG(0x34) /* EP irq status */ | 93 | #define UDC_EPN_STAT (UDC_BASE + 0x34) /* EP irq status */ |
95 | #define UDC_DMAN_STAT_REG UDC_REG(0x38) /* DMA irq status */ | 94 | #define UDC_DMAN_STAT (UDC_BASE + 0x38) /* DMA irq status */ |
96 | # define UDC_DMA_RX_SB (1 << 12) | 95 | # define UDC_DMA_RX_SB (1 << 12) |
97 | # define UDC_DMA_RX_SRC(x) (((x)>>8) & 0xf) | 96 | # define UDC_DMA_RX_SRC(x) (((x)>>8) & 0xf) |
98 | # define UDC_DMA_TX_SRC(x) (((x)>>0) & 0xf) | 97 | # define UDC_DMA_TX_SRC(x) (((x)>>0) & 0xf) |
99 | 98 | ||
100 | 99 | ||
101 | /* DMA configuration registers: up to three channels in each direction. */ | 100 | /* DMA configuration registers: up to three channels in each direction. */ |
102 | #define UDC_RXDMA_CFG_REG UDC_REG(0x40) /* 3 eps for RX DMA */ | 101 | #define UDC_RXDMA_CFG (UDC_BASE + 0x40) /* 3 eps for RX DMA */ |
103 | # define UDC_DMA_REQ (1 << 12) | 102 | # define UDC_DMA_REQ (1 << 12) |
104 | #define UDC_TXDMA_CFG_REG UDC_REG(0x44) /* 3 eps for TX DMA */ | 103 | #define UDC_TXDMA_CFG (UDC_BASE + 0x44) /* 3 eps for TX DMA */ |
105 | #define UDC_DATA_DMA_REG UDC_REG(0x48) /* rx/tx fifo addr */ | 104 | #define UDC_DATA_DMA (UDC_BASE + 0x48) /* rx/tx fifo addr */ |
106 | 105 | ||
107 | /* rx/tx dma control, numbering channels 1-3 not 0-2 */ | 106 | /* rx/tx dma control, numbering channels 1-3 not 0-2 */ |
108 | #define UDC_TXDMA_REG(chan) UDC_REG(0x50 - 4 + 4 * (chan)) | 107 | #define UDC_TXDMA(chan) (UDC_BASE + 0x50 - 4 + 4 * (chan)) |
109 | # define UDC_TXN_EOT (1 << 15) /* bytes vs packets */ | 108 | # define UDC_TXN_EOT (1 << 15) /* bytes vs packets */ |
110 | # define UDC_TXN_START (1 << 14) /* start transfer */ | 109 | # define UDC_TXN_START (1 << 14) /* start transfer */ |
111 | # define UDC_TXN_TSC 0x03ff /* units in xfer */ | 110 | # define UDC_TXN_TSC 0x03ff /* units in xfer */ |
112 | #define UDC_RXDMA_REG(chan) UDC_REG(0x60 - 4 + 4 * (chan)) | 111 | #define UDC_RXDMA(chan) (UDC_BASE + 0x60 - 4 + 4 * (chan)) |
113 | # define UDC_RXN_STOP (1 << 15) /* enable EOT irq */ | 112 | # define UDC_RXN_STOP (1 << 15) /* enable EOT irq */ |
114 | # define UDC_RXN_TC 0x00ff /* packets in xfer */ | 113 | # define UDC_RXN_TC 0x00ff /* packets in xfer */ |
115 | 114 | ||
116 | 115 | ||
117 | /* | 116 | /* |
118 | * Endpoint configuration registers (used before CFG_LOCK is set) | 117 | * Endpoint configuration registers (used before CFG_LOCK is set) |
119 | * UDC_EP_TX_REG(0) is unused | 118 | * UDC_EP_TX(0) is unused |
120 | */ | 119 | */ |
121 | #define UDC_EP_RX_REG(endpoint) UDC_REG(0x80 + (endpoint)*4) | 120 | #define UDC_EP_RX(endpoint) (UDC_BASE + 0x80 + (endpoint)*4) |
122 | # define UDC_EPN_RX_VALID (1 << 15) | 121 | # define UDC_EPN_RX_VALID (1 << 15) |
123 | # define UDC_EPN_RX_DB (1 << 14) | 122 | # define UDC_EPN_RX_DB (1 << 14) |
124 | /* buffer size in bits 13, 12 */ | 123 | /* buffer size in bits 13, 12 */ |
125 | # define UDC_EPN_RX_ISO (1 << 11) | 124 | # define UDC_EPN_RX_ISO (1 << 11) |
126 | /* buffer pointer in low 11 bits */ | 125 | /* buffer pointer in low 11 bits */ |
127 | #define UDC_EP_TX_REG(endpoint) UDC_REG(0xc0 + (endpoint)*4) | 126 | #define UDC_EP_TX(endpoint) (UDC_BASE + 0xc0 + (endpoint)*4) |
128 | /* same bitfields as in RX_REG */ | 127 | /* same bitfields as in RX */ |
129 | 128 | ||
130 | /*-------------------------------------------------------------------------*/ | 129 | /*-------------------------------------------------------------------------*/ |
131 | 130 | ||
@@ -195,14 +194,14 @@ struct omap_udc { | |||
195 | 194 | ||
196 | /*-------------------------------------------------------------------------*/ | 195 | /*-------------------------------------------------------------------------*/ |
197 | 196 | ||
198 | #define MOD_CONF_CTRL_0_REG __REG32(MOD_CONF_CTRL_0) | 197 | /* MOD_CONF_CTRL_0 */ |
199 | #define VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */ | 198 | #define VBUS_W2FC_1510 (1 << 17) /* 0 gpio0, 1 dvdd2 pin */ |
200 | 199 | ||
201 | #define FUNC_MUX_CTRL_0_REG __REG32(FUNC_MUX_CTRL_0) | 200 | /* FUNC_MUX_CTRL_0 */ |
202 | #define VBUS_CTRL_1510 (1 << 19) /* 1 connected (software) */ | 201 | #define VBUS_CTRL_1510 (1 << 19) /* 1 connected (software) */ |
203 | #define VBUS_MODE_1510 (1 << 18) /* 0 hardware, 1 software */ | 202 | #define VBUS_MODE_1510 (1 << 18) /* 0 hardware, 1 software */ |
204 | 203 | ||
205 | #define HMC_1510 ((MOD_CONF_CTRL_0_REG >> 1) & 0x3f) | 204 | #define HMC_1510 ((omap_readl(MOD_CONF_CTRL_0) >> 1) & 0x3f) |
206 | #define HMC_1610 (OTG_SYSCON_2_REG & 0x3f) | 205 | #define HMC_1610 (omap_readl(OTG_SYSCON_2) & 0x3f) |
207 | #define HMC (cpu_is_omap15xx() ? HMC_1510 : HMC_1610) | 206 | #define HMC (cpu_is_omap15xx() ? HMC_1510 : HMC_1610) |
208 | 207 | ||
diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa25x_udc.c index 08f699b1fc57..031dceb93023 100644 --- a/drivers/usb/gadget/pxa2xx_udc.c +++ b/drivers/usb/gadget/pxa25x_udc.c | |||
@@ -1,5 +1,4 @@ | |||
1 | /* | 1 | /* |
2 | * linux/drivers/usb/gadget/pxa2xx_udc.c | ||
3 | * Intel PXA25x and IXP4xx on-chip full speed USB device controllers | 2 | * Intel PXA25x and IXP4xx on-chip full speed USB device controllers |
4 | * | 3 | * |
5 | * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker) | 4 | * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker) |
@@ -46,19 +45,25 @@ | |||
46 | #include <linux/err.h> | 45 | #include <linux/err.h> |
47 | #include <linux/seq_file.h> | 46 | #include <linux/seq_file.h> |
48 | #include <linux/debugfs.h> | 47 | #include <linux/debugfs.h> |
48 | #include <linux/io.h> | ||
49 | 49 | ||
50 | #include <asm/byteorder.h> | 50 | #include <asm/byteorder.h> |
51 | #include <asm/dma.h> | 51 | #include <asm/dma.h> |
52 | #include <asm/gpio.h> | 52 | #include <asm/gpio.h> |
53 | #include <asm/io.h> | ||
54 | #include <asm/system.h> | 53 | #include <asm/system.h> |
55 | #include <asm/mach-types.h> | 54 | #include <asm/mach-types.h> |
56 | #include <asm/unaligned.h> | 55 | #include <asm/unaligned.h> |
57 | #include <asm/hardware.h> | ||
58 | 56 | ||
59 | #include <linux/usb/ch9.h> | 57 | #include <linux/usb/ch9.h> |
60 | #include <linux/usb/gadget.h> | 58 | #include <linux/usb/gadget.h> |
61 | 59 | ||
60 | /* | ||
61 | * This driver is PXA25x only. Grab the right register definitions. | ||
62 | */ | ||
63 | #ifdef CONFIG_ARCH_PXA | ||
64 | #include <asm/arch/pxa25x-udc.h> | ||
65 | #endif | ||
66 | |||
62 | #include <asm/mach/udc_pxa2xx.h> | 67 | #include <asm/mach/udc_pxa2xx.h> |
63 | 68 | ||
64 | 69 | ||
@@ -91,7 +96,7 @@ | |||
91 | #define DRIVER_DESC "PXA 25x USB Device Controller driver" | 96 | #define DRIVER_DESC "PXA 25x USB Device Controller driver" |
92 | 97 | ||
93 | 98 | ||
94 | static const char driver_name [] = "pxa2xx_udc"; | 99 | static const char driver_name [] = "pxa25x_udc"; |
95 | 100 | ||
96 | static const char ep0name [] = "ep0"; | 101 | static const char ep0name [] = "ep0"; |
97 | 102 | ||
@@ -111,10 +116,10 @@ static const char ep0name [] = "ep0"; | |||
111 | 116 | ||
112 | #endif | 117 | #endif |
113 | 118 | ||
114 | #include "pxa2xx_udc.h" | 119 | #include "pxa25x_udc.h" |
115 | 120 | ||
116 | 121 | ||
117 | #ifdef CONFIG_USB_PXA2XX_SMALL | 122 | #ifdef CONFIG_USB_PXA25X_SMALL |
118 | #define SIZE_STR " (small)" | 123 | #define SIZE_STR " (small)" |
119 | #else | 124 | #else |
120 | #define SIZE_STR "" | 125 | #define SIZE_STR "" |
@@ -126,8 +131,8 @@ static const char ep0name [] = "ep0"; | |||
126 | * --------------------------------------------------------------------------- | 131 | * --------------------------------------------------------------------------- |
127 | */ | 132 | */ |
128 | 133 | ||
129 | static void pxa2xx_ep_fifo_flush (struct usb_ep *ep); | 134 | static void pxa25x_ep_fifo_flush (struct usb_ep *ep); |
130 | static void nuke (struct pxa2xx_ep *, int status); | 135 | static void nuke (struct pxa25x_ep *, int status); |
131 | 136 | ||
132 | /* one GPIO should be used to detect VBUS from the host */ | 137 | /* one GPIO should be used to detect VBUS from the host */ |
133 | static int is_vbus_present(void) | 138 | static int is_vbus_present(void) |
@@ -212,24 +217,24 @@ static inline void udc_ack_int_UDCCR(int mask) | |||
212 | /* | 217 | /* |
213 | * endpoint enable/disable | 218 | * endpoint enable/disable |
214 | * | 219 | * |
215 | * we need to verify the descriptors used to enable endpoints. since pxa2xx | 220 | * we need to verify the descriptors used to enable endpoints. since pxa25x |
216 | * endpoint configurations are fixed, and are pretty much always enabled, | 221 | * endpoint configurations are fixed, and are pretty much always enabled, |
217 | * there's not a lot to manage here. | 222 | * there's not a lot to manage here. |
218 | * | 223 | * |
219 | * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints, | 224 | * because pxa25x can't selectively initialize bulk (or interrupt) endpoints, |
220 | * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except | 225 | * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except |
221 | * for a single interface (with only the default altsetting) and for gadget | 226 | * for a single interface (with only the default altsetting) and for gadget |
222 | * drivers that don't halt endpoints (not reset by set_interface). that also | 227 | * drivers that don't halt endpoints (not reset by set_interface). that also |
223 | * means that if you use ISO, you must violate the USB spec rule that all | 228 | * means that if you use ISO, you must violate the USB spec rule that all |
224 | * iso endpoints must be in non-default altsettings. | 229 | * iso endpoints must be in non-default altsettings. |
225 | */ | 230 | */ |
226 | static int pxa2xx_ep_enable (struct usb_ep *_ep, | 231 | static int pxa25x_ep_enable (struct usb_ep *_ep, |
227 | const struct usb_endpoint_descriptor *desc) | 232 | const struct usb_endpoint_descriptor *desc) |
228 | { | 233 | { |
229 | struct pxa2xx_ep *ep; | 234 | struct pxa25x_ep *ep; |
230 | struct pxa2xx_udc *dev; | 235 | struct pxa25x_udc *dev; |
231 | 236 | ||
232 | ep = container_of (_ep, struct pxa2xx_ep, ep); | 237 | ep = container_of (_ep, struct pxa25x_ep, ep); |
233 | if (!_ep || !desc || ep->desc || _ep->name == ep0name | 238 | if (!_ep || !desc || ep->desc || _ep->name == ep0name |
234 | || desc->bDescriptorType != USB_DT_ENDPOINT | 239 | || desc->bDescriptorType != USB_DT_ENDPOINT |
235 | || ep->bEndpointAddress != desc->bEndpointAddress | 240 | || ep->bEndpointAddress != desc->bEndpointAddress |
@@ -268,7 +273,7 @@ static int pxa2xx_ep_enable (struct usb_ep *_ep, | |||
268 | ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize); | 273 | ep->ep.maxpacket = le16_to_cpu (desc->wMaxPacketSize); |
269 | 274 | ||
270 | /* flush fifo (mostly for OUT buffers) */ | 275 | /* flush fifo (mostly for OUT buffers) */ |
271 | pxa2xx_ep_fifo_flush (_ep); | 276 | pxa25x_ep_fifo_flush (_ep); |
272 | 277 | ||
273 | /* ... reset halt state too, if we could ... */ | 278 | /* ... reset halt state too, if we could ... */ |
274 | 279 | ||
@@ -276,12 +281,12 @@ static int pxa2xx_ep_enable (struct usb_ep *_ep, | |||
276 | return 0; | 281 | return 0; |
277 | } | 282 | } |
278 | 283 | ||
279 | static int pxa2xx_ep_disable (struct usb_ep *_ep) | 284 | static int pxa25x_ep_disable (struct usb_ep *_ep) |
280 | { | 285 | { |
281 | struct pxa2xx_ep *ep; | 286 | struct pxa25x_ep *ep; |
282 | unsigned long flags; | 287 | unsigned long flags; |
283 | 288 | ||
284 | ep = container_of (_ep, struct pxa2xx_ep, ep); | 289 | ep = container_of (_ep, struct pxa25x_ep, ep); |
285 | if (!_ep || !ep->desc) { | 290 | if (!_ep || !ep->desc) { |
286 | DMSG("%s, %s not enabled\n", __func__, | 291 | DMSG("%s, %s not enabled\n", __func__, |
287 | _ep ? ep->ep.name : NULL); | 292 | _ep ? ep->ep.name : NULL); |
@@ -292,7 +297,7 @@ static int pxa2xx_ep_disable (struct usb_ep *_ep) | |||
292 | nuke (ep, -ESHUTDOWN); | 297 | nuke (ep, -ESHUTDOWN); |
293 | 298 | ||
294 | /* flush fifo (mostly for IN buffers) */ | 299 | /* flush fifo (mostly for IN buffers) */ |
295 | pxa2xx_ep_fifo_flush (_ep); | 300 | pxa25x_ep_fifo_flush (_ep); |
296 | 301 | ||
297 | ep->desc = NULL; | 302 | ep->desc = NULL; |
298 | ep->stopped = 1; | 303 | ep->stopped = 1; |
@@ -304,18 +309,18 @@ static int pxa2xx_ep_disable (struct usb_ep *_ep) | |||
304 | 309 | ||
305 | /*-------------------------------------------------------------------------*/ | 310 | /*-------------------------------------------------------------------------*/ |
306 | 311 | ||
307 | /* for the pxa2xx, these can just wrap kmalloc/kfree. gadget drivers | 312 | /* for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers |
308 | * must still pass correctly initialized endpoints, since other controller | 313 | * must still pass correctly initialized endpoints, since other controller |
309 | * drivers may care about how it's currently set up (dma issues etc). | 314 | * drivers may care about how it's currently set up (dma issues etc). |
310 | */ | 315 | */ |
311 | 316 | ||
312 | /* | 317 | /* |
313 | * pxa2xx_ep_alloc_request - allocate a request data structure | 318 | * pxa25x_ep_alloc_request - allocate a request data structure |
314 | */ | 319 | */ |
315 | static struct usb_request * | 320 | static struct usb_request * |
316 | pxa2xx_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags) | 321 | pxa25x_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags) |
317 | { | 322 | { |
318 | struct pxa2xx_request *req; | 323 | struct pxa25x_request *req; |
319 | 324 | ||
320 | req = kzalloc(sizeof(*req), gfp_flags); | 325 | req = kzalloc(sizeof(*req), gfp_flags); |
321 | if (!req) | 326 | if (!req) |
@@ -327,14 +332,14 @@ pxa2xx_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags) | |||
327 | 332 | ||
328 | 333 | ||
329 | /* | 334 | /* |
330 | * pxa2xx_ep_free_request - deallocate a request data structure | 335 | * pxa25x_ep_free_request - deallocate a request data structure |
331 | */ | 336 | */ |
332 | static void | 337 | static void |
333 | pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req) | 338 | pxa25x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req) |
334 | { | 339 | { |
335 | struct pxa2xx_request *req; | 340 | struct pxa25x_request *req; |
336 | 341 | ||
337 | req = container_of (_req, struct pxa2xx_request, req); | 342 | req = container_of (_req, struct pxa25x_request, req); |
338 | WARN_ON (!list_empty (&req->queue)); | 343 | WARN_ON (!list_empty (&req->queue)); |
339 | kfree(req); | 344 | kfree(req); |
340 | } | 345 | } |
@@ -344,7 +349,7 @@ pxa2xx_ep_free_request (struct usb_ep *_ep, struct usb_request *_req) | |||
344 | /* | 349 | /* |
345 | * done - retire a request; caller blocked irqs | 350 | * done - retire a request; caller blocked irqs |
346 | */ | 351 | */ |
347 | static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status) | 352 | static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status) |
348 | { | 353 | { |
349 | unsigned stopped = ep->stopped; | 354 | unsigned stopped = ep->stopped; |
350 | 355 | ||
@@ -367,13 +372,13 @@ static void done(struct pxa2xx_ep *ep, struct pxa2xx_request *req, int status) | |||
367 | } | 372 | } |
368 | 373 | ||
369 | 374 | ||
370 | static inline void ep0_idle (struct pxa2xx_udc *dev) | 375 | static inline void ep0_idle (struct pxa25x_udc *dev) |
371 | { | 376 | { |
372 | dev->ep0state = EP0_IDLE; | 377 | dev->ep0state = EP0_IDLE; |
373 | } | 378 | } |
374 | 379 | ||
375 | static int | 380 | static int |
376 | write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max) | 381 | write_packet(volatile u32 *uddr, struct pxa25x_request *req, unsigned max) |
377 | { | 382 | { |
378 | u8 *buf; | 383 | u8 *buf; |
379 | unsigned length, count; | 384 | unsigned length, count; |
@@ -398,7 +403,7 @@ write_packet(volatile u32 *uddr, struct pxa2xx_request *req, unsigned max) | |||
398 | * caller guarantees at least one packet buffer is ready (or a zlp). | 403 | * caller guarantees at least one packet buffer is ready (or a zlp). |
399 | */ | 404 | */ |
400 | static int | 405 | static int |
401 | write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | 406 | write_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
402 | { | 407 | { |
403 | unsigned max; | 408 | unsigned max; |
404 | 409 | ||
@@ -455,7 +460,7 @@ write_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | |||
455 | * ep0 data stage. these chips want very simple state transitions. | 460 | * ep0 data stage. these chips want very simple state transitions. |
456 | */ | 461 | */ |
457 | static inline | 462 | static inline |
458 | void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag) | 463 | void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag) |
459 | { | 464 | { |
460 | UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR; | 465 | UDCCS0 = flags|UDCCS0_SA|UDCCS0_OPR; |
461 | USIR0 = USIR0_IR0; | 466 | USIR0 = USIR0_IR0; |
@@ -465,7 +470,7 @@ void ep0start(struct pxa2xx_udc *dev, u32 flags, const char *tag) | |||
465 | } | 470 | } |
466 | 471 | ||
467 | static int | 472 | static int |
468 | write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | 473 | write_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
469 | { | 474 | { |
470 | unsigned count; | 475 | unsigned count; |
471 | int is_short; | 476 | int is_short; |
@@ -525,7 +530,7 @@ write_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | |||
525 | * request buffer having filled (and maybe overran till end-of-packet). | 530 | * request buffer having filled (and maybe overran till end-of-packet). |
526 | */ | 531 | */ |
527 | static int | 532 | static int |
528 | read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | 533 | read_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
529 | { | 534 | { |
530 | for (;;) { | 535 | for (;;) { |
531 | u32 udccs; | 536 | u32 udccs; |
@@ -602,7 +607,7 @@ read_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | |||
602 | * protocols do use them. | 607 | * protocols do use them. |
603 | */ | 608 | */ |
604 | static int | 609 | static int |
605 | read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | 610 | read_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req) |
606 | { | 611 | { |
607 | u8 *buf, byte; | 612 | u8 *buf, byte; |
608 | unsigned bufferspace; | 613 | unsigned bufferspace; |
@@ -641,21 +646,21 @@ read_ep0_fifo (struct pxa2xx_ep *ep, struct pxa2xx_request *req) | |||
641 | /*-------------------------------------------------------------------------*/ | 646 | /*-------------------------------------------------------------------------*/ |
642 | 647 | ||
643 | static int | 648 | static int |
644 | pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | 649 | pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) |
645 | { | 650 | { |
646 | struct pxa2xx_request *req; | 651 | struct pxa25x_request *req; |
647 | struct pxa2xx_ep *ep; | 652 | struct pxa25x_ep *ep; |
648 | struct pxa2xx_udc *dev; | 653 | struct pxa25x_udc *dev; |
649 | unsigned long flags; | 654 | unsigned long flags; |
650 | 655 | ||
651 | req = container_of(_req, struct pxa2xx_request, req); | 656 | req = container_of(_req, struct pxa25x_request, req); |
652 | if (unlikely (!_req || !_req->complete || !_req->buf | 657 | if (unlikely (!_req || !_req->complete || !_req->buf |
653 | || !list_empty(&req->queue))) { | 658 | || !list_empty(&req->queue))) { |
654 | DMSG("%s, bad params\n", __func__); | 659 | DMSG("%s, bad params\n", __func__); |
655 | return -EINVAL; | 660 | return -EINVAL; |
656 | } | 661 | } |
657 | 662 | ||
658 | ep = container_of(_ep, struct pxa2xx_ep, ep); | 663 | ep = container_of(_ep, struct pxa25x_ep, ep); |
659 | if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) { | 664 | if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) { |
660 | DMSG("%s, bad ep\n", __func__); | 665 | DMSG("%s, bad ep\n", __func__); |
661 | return -EINVAL; | 666 | return -EINVAL; |
@@ -751,14 +756,14 @@ pxa2xx_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) | |||
751 | /* | 756 | /* |
752 | * nuke - dequeue ALL requests | 757 | * nuke - dequeue ALL requests |
753 | */ | 758 | */ |
754 | static void nuke(struct pxa2xx_ep *ep, int status) | 759 | static void nuke(struct pxa25x_ep *ep, int status) |
755 | { | 760 | { |
756 | struct pxa2xx_request *req; | 761 | struct pxa25x_request *req; |
757 | 762 | ||
758 | /* called with irqs blocked */ | 763 | /* called with irqs blocked */ |
759 | while (!list_empty(&ep->queue)) { | 764 | while (!list_empty(&ep->queue)) { |
760 | req = list_entry(ep->queue.next, | 765 | req = list_entry(ep->queue.next, |
761 | struct pxa2xx_request, | 766 | struct pxa25x_request, |
762 | queue); | 767 | queue); |
763 | done(ep, req, status); | 768 | done(ep, req, status); |
764 | } | 769 | } |
@@ -768,13 +773,13 @@ static void nuke(struct pxa2xx_ep *ep, int status) | |||
768 | 773 | ||
769 | 774 | ||
770 | /* dequeue JUST ONE request */ | 775 | /* dequeue JUST ONE request */ |
771 | static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | 776 | static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) |
772 | { | 777 | { |
773 | struct pxa2xx_ep *ep; | 778 | struct pxa25x_ep *ep; |
774 | struct pxa2xx_request *req; | 779 | struct pxa25x_request *req; |
775 | unsigned long flags; | 780 | unsigned long flags; |
776 | 781 | ||
777 | ep = container_of(_ep, struct pxa2xx_ep, ep); | 782 | ep = container_of(_ep, struct pxa25x_ep, ep); |
778 | if (!_ep || ep->ep.name == ep0name) | 783 | if (!_ep || ep->ep.name == ep0name) |
779 | return -EINVAL; | 784 | return -EINVAL; |
780 | 785 | ||
@@ -798,12 +803,12 @@ static int pxa2xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) | |||
798 | 803 | ||
799 | /*-------------------------------------------------------------------------*/ | 804 | /*-------------------------------------------------------------------------*/ |
800 | 805 | ||
801 | static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value) | 806 | static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value) |
802 | { | 807 | { |
803 | struct pxa2xx_ep *ep; | 808 | struct pxa25x_ep *ep; |
804 | unsigned long flags; | 809 | unsigned long flags; |
805 | 810 | ||
806 | ep = container_of(_ep, struct pxa2xx_ep, ep); | 811 | ep = container_of(_ep, struct pxa25x_ep, ep); |
807 | if (unlikely (!_ep | 812 | if (unlikely (!_ep |
808 | || (!ep->desc && ep->ep.name != ep0name)) | 813 | || (!ep->desc && ep->ep.name != ep0name)) |
809 | || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { | 814 | || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) { |
@@ -853,11 +858,11 @@ static int pxa2xx_ep_set_halt(struct usb_ep *_ep, int value) | |||
853 | return 0; | 858 | return 0; |
854 | } | 859 | } |
855 | 860 | ||
856 | static int pxa2xx_ep_fifo_status(struct usb_ep *_ep) | 861 | static int pxa25x_ep_fifo_status(struct usb_ep *_ep) |
857 | { | 862 | { |
858 | struct pxa2xx_ep *ep; | 863 | struct pxa25x_ep *ep; |
859 | 864 | ||
860 | ep = container_of(_ep, struct pxa2xx_ep, ep); | 865 | ep = container_of(_ep, struct pxa25x_ep, ep); |
861 | if (!_ep) { | 866 | if (!_ep) { |
862 | DMSG("%s, bad ep\n", __func__); | 867 | DMSG("%s, bad ep\n", __func__); |
863 | return -ENODEV; | 868 | return -ENODEV; |
@@ -872,11 +877,11 @@ static int pxa2xx_ep_fifo_status(struct usb_ep *_ep) | |||
872 | return (*ep->reg_ubcr & 0xfff) + 1; | 877 | return (*ep->reg_ubcr & 0xfff) + 1; |
873 | } | 878 | } |
874 | 879 | ||
875 | static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep) | 880 | static void pxa25x_ep_fifo_flush(struct usb_ep *_ep) |
876 | { | 881 | { |
877 | struct pxa2xx_ep *ep; | 882 | struct pxa25x_ep *ep; |
878 | 883 | ||
879 | ep = container_of(_ep, struct pxa2xx_ep, ep); | 884 | ep = container_of(_ep, struct pxa25x_ep, ep); |
880 | if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) { | 885 | if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) { |
881 | DMSG("%s, bad ep\n", __func__); | 886 | DMSG("%s, bad ep\n", __func__); |
882 | return; | 887 | return; |
@@ -898,19 +903,19 @@ static void pxa2xx_ep_fifo_flush(struct usb_ep *_ep) | |||
898 | } | 903 | } |
899 | 904 | ||
900 | 905 | ||
901 | static struct usb_ep_ops pxa2xx_ep_ops = { | 906 | static struct usb_ep_ops pxa25x_ep_ops = { |
902 | .enable = pxa2xx_ep_enable, | 907 | .enable = pxa25x_ep_enable, |
903 | .disable = pxa2xx_ep_disable, | 908 | .disable = pxa25x_ep_disable, |
904 | 909 | ||
905 | .alloc_request = pxa2xx_ep_alloc_request, | 910 | .alloc_request = pxa25x_ep_alloc_request, |
906 | .free_request = pxa2xx_ep_free_request, | 911 | .free_request = pxa25x_ep_free_request, |
907 | 912 | ||
908 | .queue = pxa2xx_ep_queue, | 913 | .queue = pxa25x_ep_queue, |
909 | .dequeue = pxa2xx_ep_dequeue, | 914 | .dequeue = pxa25x_ep_dequeue, |
910 | 915 | ||
911 | .set_halt = pxa2xx_ep_set_halt, | 916 | .set_halt = pxa25x_ep_set_halt, |
912 | .fifo_status = pxa2xx_ep_fifo_status, | 917 | .fifo_status = pxa25x_ep_fifo_status, |
913 | .fifo_flush = pxa2xx_ep_fifo_flush, | 918 | .fifo_flush = pxa25x_ep_fifo_flush, |
914 | }; | 919 | }; |
915 | 920 | ||
916 | 921 | ||
@@ -919,12 +924,12 @@ static struct usb_ep_ops pxa2xx_ep_ops = { | |||
919 | * --------------------------------------------------------------------------- | 924 | * --------------------------------------------------------------------------- |
920 | */ | 925 | */ |
921 | 926 | ||
922 | static int pxa2xx_udc_get_frame(struct usb_gadget *_gadget) | 927 | static int pxa25x_udc_get_frame(struct usb_gadget *_gadget) |
923 | { | 928 | { |
924 | return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff); | 929 | return ((UFNRH & 0x07) << 8) | (UFNRL & 0xff); |
925 | } | 930 | } |
926 | 931 | ||
927 | static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget) | 932 | static int pxa25x_udc_wakeup(struct usb_gadget *_gadget) |
928 | { | 933 | { |
929 | /* host may not have enabled remote wakeup */ | 934 | /* host may not have enabled remote wakeup */ |
930 | if ((UDCCS0 & UDCCS0_DRWF) == 0) | 935 | if ((UDCCS0 & UDCCS0_DRWF) == 0) |
@@ -933,14 +938,14 @@ static int pxa2xx_udc_wakeup(struct usb_gadget *_gadget) | |||
933 | return 0; | 938 | return 0; |
934 | } | 939 | } |
935 | 940 | ||
936 | static void stop_activity(struct pxa2xx_udc *, struct usb_gadget_driver *); | 941 | static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *); |
937 | static void udc_enable (struct pxa2xx_udc *); | 942 | static void udc_enable (struct pxa25x_udc *); |
938 | static void udc_disable(struct pxa2xx_udc *); | 943 | static void udc_disable(struct pxa25x_udc *); |
939 | 944 | ||
940 | /* We disable the UDC -- and its 48 MHz clock -- whenever it's not | 945 | /* We disable the UDC -- and its 48 MHz clock -- whenever it's not |
941 | * in active use. | 946 | * in active use. |
942 | */ | 947 | */ |
943 | static int pullup(struct pxa2xx_udc *udc) | 948 | static int pullup(struct pxa25x_udc *udc) |
944 | { | 949 | { |
945 | int is_active = udc->vbus && udc->pullup && !udc->suspended; | 950 | int is_active = udc->vbus && udc->pullup && !udc->suspended; |
946 | DMSG("%s\n", is_active ? "active" : "inactive"); | 951 | DMSG("%s\n", is_active ? "active" : "inactive"); |
@@ -970,11 +975,11 @@ static int pullup(struct pxa2xx_udc *udc) | |||
970 | } | 975 | } |
971 | 976 | ||
972 | /* VBUS reporting logically comes from a transceiver */ | 977 | /* VBUS reporting logically comes from a transceiver */ |
973 | static int pxa2xx_udc_vbus_session(struct usb_gadget *_gadget, int is_active) | 978 | static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active) |
974 | { | 979 | { |
975 | struct pxa2xx_udc *udc; | 980 | struct pxa25x_udc *udc; |
976 | 981 | ||
977 | udc = container_of(_gadget, struct pxa2xx_udc, gadget); | 982 | udc = container_of(_gadget, struct pxa25x_udc, gadget); |
978 | udc->vbus = (is_active != 0); | 983 | udc->vbus = (is_active != 0); |
979 | DMSG("vbus %s\n", is_active ? "supplied" : "inactive"); | 984 | DMSG("vbus %s\n", is_active ? "supplied" : "inactive"); |
980 | pullup(udc); | 985 | pullup(udc); |
@@ -982,11 +987,11 @@ static int pxa2xx_udc_vbus_session(struct usb_gadget *_gadget, int is_active) | |||
982 | } | 987 | } |
983 | 988 | ||
984 | /* drivers may have software control over D+ pullup */ | 989 | /* drivers may have software control over D+ pullup */ |
985 | static int pxa2xx_udc_pullup(struct usb_gadget *_gadget, int is_active) | 990 | static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active) |
986 | { | 991 | { |
987 | struct pxa2xx_udc *udc; | 992 | struct pxa25x_udc *udc; |
988 | 993 | ||
989 | udc = container_of(_gadget, struct pxa2xx_udc, gadget); | 994 | udc = container_of(_gadget, struct pxa25x_udc, gadget); |
990 | 995 | ||
991 | /* not all boards support pullup control */ | 996 | /* not all boards support pullup control */ |
992 | if (!udc->mach->gpio_pullup && !udc->mach->udc_command) | 997 | if (!udc->mach->gpio_pullup && !udc->mach->udc_command) |
@@ -997,11 +1002,11 @@ static int pxa2xx_udc_pullup(struct usb_gadget *_gadget, int is_active) | |||
997 | return 0; | 1002 | return 0; |
998 | } | 1003 | } |
999 | 1004 | ||
1000 | static const struct usb_gadget_ops pxa2xx_udc_ops = { | 1005 | static const struct usb_gadget_ops pxa25x_udc_ops = { |
1001 | .get_frame = pxa2xx_udc_get_frame, | 1006 | .get_frame = pxa25x_udc_get_frame, |
1002 | .wakeup = pxa2xx_udc_wakeup, | 1007 | .wakeup = pxa25x_udc_wakeup, |
1003 | .vbus_session = pxa2xx_udc_vbus_session, | 1008 | .vbus_session = pxa25x_udc_vbus_session, |
1004 | .pullup = pxa2xx_udc_pullup, | 1009 | .pullup = pxa25x_udc_pullup, |
1005 | 1010 | ||
1006 | // .vbus_draw ... boards may consume current from VBUS, up to | 1011 | // .vbus_draw ... boards may consume current from VBUS, up to |
1007 | // 100-500mA based on config. the 500uA suspend ceiling means | 1012 | // 100-500mA based on config. the 500uA suspend ceiling means |
@@ -1015,7 +1020,7 @@ static const struct usb_gadget_ops pxa2xx_udc_ops = { | |||
1015 | static int | 1020 | static int |
1016 | udc_seq_show(struct seq_file *m, void *_d) | 1021 | udc_seq_show(struct seq_file *m, void *_d) |
1017 | { | 1022 | { |
1018 | struct pxa2xx_udc *dev = m->private; | 1023 | struct pxa25x_udc *dev = m->private; |
1019 | unsigned long flags; | 1024 | unsigned long flags; |
1020 | int i; | 1025 | int i; |
1021 | u32 tmp; | 1026 | u32 tmp; |
@@ -1076,8 +1081,8 @@ udc_seq_show(struct seq_file *m, void *_d) | |||
1076 | 1081 | ||
1077 | /* dump endpoint queues */ | 1082 | /* dump endpoint queues */ |
1078 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { | 1083 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { |
1079 | struct pxa2xx_ep *ep = &dev->ep [i]; | 1084 | struct pxa25x_ep *ep = &dev->ep [i]; |
1080 | struct pxa2xx_request *req; | 1085 | struct pxa25x_request *req; |
1081 | 1086 | ||
1082 | if (i != 0) { | 1087 | if (i != 0) { |
1083 | const struct usb_endpoint_descriptor *desc; | 1088 | const struct usb_endpoint_descriptor *desc; |
@@ -1150,7 +1155,7 @@ static const struct file_operations debug_fops = { | |||
1150 | /* | 1155 | /* |
1151 | * udc_disable - disable USB device controller | 1156 | * udc_disable - disable USB device controller |
1152 | */ | 1157 | */ |
1153 | static void udc_disable(struct pxa2xx_udc *dev) | 1158 | static void udc_disable(struct pxa25x_udc *dev) |
1154 | { | 1159 | { |
1155 | /* block all irqs */ | 1160 | /* block all irqs */ |
1156 | udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM); | 1161 | udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM); |
@@ -1170,7 +1175,7 @@ static void udc_disable(struct pxa2xx_udc *dev) | |||
1170 | /* | 1175 | /* |
1171 | * udc_reinit - initialize software state | 1176 | * udc_reinit - initialize software state |
1172 | */ | 1177 | */ |
1173 | static void udc_reinit(struct pxa2xx_udc *dev) | 1178 | static void udc_reinit(struct pxa25x_udc *dev) |
1174 | { | 1179 | { |
1175 | u32 i; | 1180 | u32 i; |
1176 | 1181 | ||
@@ -1181,7 +1186,7 @@ static void udc_reinit(struct pxa2xx_udc *dev) | |||
1181 | 1186 | ||
1182 | /* basic endpoint records init */ | 1187 | /* basic endpoint records init */ |
1183 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { | 1188 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { |
1184 | struct pxa2xx_ep *ep = &dev->ep[i]; | 1189 | struct pxa25x_ep *ep = &dev->ep[i]; |
1185 | 1190 | ||
1186 | if (i != 0) | 1191 | if (i != 0) |
1187 | list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list); | 1192 | list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list); |
@@ -1198,7 +1203,7 @@ static void udc_reinit(struct pxa2xx_udc *dev) | |||
1198 | /* until it's enabled, this UDC should be completely invisible | 1203 | /* until it's enabled, this UDC should be completely invisible |
1199 | * to any USB host. | 1204 | * to any USB host. |
1200 | */ | 1205 | */ |
1201 | static void udc_enable (struct pxa2xx_udc *dev) | 1206 | static void udc_enable (struct pxa25x_udc *dev) |
1202 | { | 1207 | { |
1203 | udc_clear_mask_UDCCR(UDCCR_UDE); | 1208 | udc_clear_mask_UDCCR(UDCCR_UDE); |
1204 | 1209 | ||
@@ -1254,7 +1259,7 @@ static void udc_enable (struct pxa2xx_udc *dev) | |||
1254 | */ | 1259 | */ |
1255 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) | 1260 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) |
1256 | { | 1261 | { |
1257 | struct pxa2xx_udc *dev = the_controller; | 1262 | struct pxa25x_udc *dev = the_controller; |
1258 | int retval; | 1263 | int retval; |
1259 | 1264 | ||
1260 | if (!driver | 1265 | if (!driver |
@@ -1299,7 +1304,7 @@ fail: | |||
1299 | EXPORT_SYMBOL(usb_gadget_register_driver); | 1304 | EXPORT_SYMBOL(usb_gadget_register_driver); |
1300 | 1305 | ||
1301 | static void | 1306 | static void |
1302 | stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver) | 1307 | stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver) |
1303 | { | 1308 | { |
1304 | int i; | 1309 | int i; |
1305 | 1310 | ||
@@ -1310,7 +1315,7 @@ stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver) | |||
1310 | 1315 | ||
1311 | /* prevent new request submissions, kill any outstanding requests */ | 1316 | /* prevent new request submissions, kill any outstanding requests */ |
1312 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { | 1317 | for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) { |
1313 | struct pxa2xx_ep *ep = &dev->ep[i]; | 1318 | struct pxa25x_ep *ep = &dev->ep[i]; |
1314 | 1319 | ||
1315 | ep->stopped = 1; | 1320 | ep->stopped = 1; |
1316 | nuke(ep, -ESHUTDOWN); | 1321 | nuke(ep, -ESHUTDOWN); |
@@ -1327,7 +1332,7 @@ stop_activity(struct pxa2xx_udc *dev, struct usb_gadget_driver *driver) | |||
1327 | 1332 | ||
1328 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) | 1333 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) |
1329 | { | 1334 | { |
1330 | struct pxa2xx_udc *dev = the_controller; | 1335 | struct pxa25x_udc *dev = the_controller; |
1331 | 1336 | ||
1332 | if (!dev) | 1337 | if (!dev) |
1333 | return -ENODEV; | 1338 | return -ENODEV; |
@@ -1364,7 +1369,7 @@ EXPORT_SYMBOL(usb_gadget_unregister_driver); | |||
1364 | static irqreturn_t | 1369 | static irqreturn_t |
1365 | lubbock_vbus_irq(int irq, void *_dev) | 1370 | lubbock_vbus_irq(int irq, void *_dev) |
1366 | { | 1371 | { |
1367 | struct pxa2xx_udc *dev = _dev; | 1372 | struct pxa25x_udc *dev = _dev; |
1368 | int vbus; | 1373 | int vbus; |
1369 | 1374 | ||
1370 | dev->stats.irqs++; | 1375 | dev->stats.irqs++; |
@@ -1383,7 +1388,7 @@ lubbock_vbus_irq(int irq, void *_dev) | |||
1383 | return IRQ_NONE; | 1388 | return IRQ_NONE; |
1384 | } | 1389 | } |
1385 | 1390 | ||
1386 | pxa2xx_udc_vbus_session(&dev->gadget, vbus); | 1391 | pxa25x_udc_vbus_session(&dev->gadget, vbus); |
1387 | return IRQ_HANDLED; | 1392 | return IRQ_HANDLED; |
1388 | } | 1393 | } |
1389 | 1394 | ||
@@ -1391,20 +1396,20 @@ lubbock_vbus_irq(int irq, void *_dev) | |||
1391 | 1396 | ||
1392 | static irqreturn_t udc_vbus_irq(int irq, void *_dev) | 1397 | static irqreturn_t udc_vbus_irq(int irq, void *_dev) |
1393 | { | 1398 | { |
1394 | struct pxa2xx_udc *dev = _dev; | 1399 | struct pxa25x_udc *dev = _dev; |
1395 | int vbus = gpio_get_value(dev->mach->gpio_vbus); | 1400 | int vbus = gpio_get_value(dev->mach->gpio_vbus); |
1396 | 1401 | ||
1397 | if (dev->mach->gpio_vbus_inverted) | 1402 | if (dev->mach->gpio_vbus_inverted) |
1398 | vbus = !vbus; | 1403 | vbus = !vbus; |
1399 | 1404 | ||
1400 | pxa2xx_udc_vbus_session(&dev->gadget, vbus); | 1405 | pxa25x_udc_vbus_session(&dev->gadget, vbus); |
1401 | return IRQ_HANDLED; | 1406 | return IRQ_HANDLED; |
1402 | } | 1407 | } |
1403 | 1408 | ||
1404 | 1409 | ||
1405 | /*-------------------------------------------------------------------------*/ | 1410 | /*-------------------------------------------------------------------------*/ |
1406 | 1411 | ||
1407 | static inline void clear_ep_state (struct pxa2xx_udc *dev) | 1412 | static inline void clear_ep_state (struct pxa25x_udc *dev) |
1408 | { | 1413 | { |
1409 | unsigned i; | 1414 | unsigned i; |
1410 | 1415 | ||
@@ -1417,7 +1422,7 @@ static inline void clear_ep_state (struct pxa2xx_udc *dev) | |||
1417 | 1422 | ||
1418 | static void udc_watchdog(unsigned long _dev) | 1423 | static void udc_watchdog(unsigned long _dev) |
1419 | { | 1424 | { |
1420 | struct pxa2xx_udc *dev = (void *)_dev; | 1425 | struct pxa25x_udc *dev = (void *)_dev; |
1421 | 1426 | ||
1422 | local_irq_disable(); | 1427 | local_irq_disable(); |
1423 | if (dev->ep0state == EP0_STALL | 1428 | if (dev->ep0state == EP0_STALL |
@@ -1430,11 +1435,11 @@ static void udc_watchdog(unsigned long _dev) | |||
1430 | local_irq_enable(); | 1435 | local_irq_enable(); |
1431 | } | 1436 | } |
1432 | 1437 | ||
1433 | static void handle_ep0 (struct pxa2xx_udc *dev) | 1438 | static void handle_ep0 (struct pxa25x_udc *dev) |
1434 | { | 1439 | { |
1435 | u32 udccs0 = UDCCS0; | 1440 | u32 udccs0 = UDCCS0; |
1436 | struct pxa2xx_ep *ep = &dev->ep [0]; | 1441 | struct pxa25x_ep *ep = &dev->ep [0]; |
1437 | struct pxa2xx_request *req; | 1442 | struct pxa25x_request *req; |
1438 | union { | 1443 | union { |
1439 | struct usb_ctrlrequest r; | 1444 | struct usb_ctrlrequest r; |
1440 | u8 raw [8]; | 1445 | u8 raw [8]; |
@@ -1444,7 +1449,7 @@ static void handle_ep0 (struct pxa2xx_udc *dev) | |||
1444 | if (list_empty(&ep->queue)) | 1449 | if (list_empty(&ep->queue)) |
1445 | req = NULL; | 1450 | req = NULL; |
1446 | else | 1451 | else |
1447 | req = list_entry(ep->queue.next, struct pxa2xx_request, queue); | 1452 | req = list_entry(ep->queue.next, struct pxa25x_request, queue); |
1448 | 1453 | ||
1449 | /* clear stall status */ | 1454 | /* clear stall status */ |
1450 | if (udccs0 & UDCCS0_SST) { | 1455 | if (udccs0 & UDCCS0_SST) { |
@@ -1654,9 +1659,9 @@ stall: | |||
1654 | USIR0 = USIR0_IR0; | 1659 | USIR0 = USIR0_IR0; |
1655 | } | 1660 | } |
1656 | 1661 | ||
1657 | static void handle_ep(struct pxa2xx_ep *ep) | 1662 | static void handle_ep(struct pxa25x_ep *ep) |
1658 | { | 1663 | { |
1659 | struct pxa2xx_request *req; | 1664 | struct pxa25x_request *req; |
1660 | int is_in = ep->bEndpointAddress & USB_DIR_IN; | 1665 | int is_in = ep->bEndpointAddress & USB_DIR_IN; |
1661 | int completed; | 1666 | int completed; |
1662 | u32 udccs, tmp; | 1667 | u32 udccs, tmp; |
@@ -1665,7 +1670,7 @@ static void handle_ep(struct pxa2xx_ep *ep) | |||
1665 | completed = 0; | 1670 | completed = 0; |
1666 | if (likely (!list_empty(&ep->queue))) | 1671 | if (likely (!list_empty(&ep->queue))) |
1667 | req = list_entry(ep->queue.next, | 1672 | req = list_entry(ep->queue.next, |
1668 | struct pxa2xx_request, queue); | 1673 | struct pxa25x_request, queue); |
1669 | else | 1674 | else |
1670 | req = NULL; | 1675 | req = NULL; |
1671 | 1676 | ||
@@ -1702,16 +1707,16 @@ static void handle_ep(struct pxa2xx_ep *ep) | |||
1702 | } | 1707 | } |
1703 | 1708 | ||
1704 | /* | 1709 | /* |
1705 | * pxa2xx_udc_irq - interrupt handler | 1710 | * pxa25x_udc_irq - interrupt handler |
1706 | * | 1711 | * |
1707 | * avoid delays in ep0 processing. the control handshaking isn't always | 1712 | * avoid delays in ep0 processing. the control handshaking isn't always |
1708 | * under software control (pxa250c0 and the pxa255 are better), and delays | 1713 | * under software control (pxa250c0 and the pxa255 are better), and delays |
1709 | * could cause usb protocol errors. | 1714 | * could cause usb protocol errors. |
1710 | */ | 1715 | */ |
1711 | static irqreturn_t | 1716 | static irqreturn_t |
1712 | pxa2xx_udc_irq(int irq, void *_dev) | 1717 | pxa25x_udc_irq(int irq, void *_dev) |
1713 | { | 1718 | { |
1714 | struct pxa2xx_udc *dev = _dev; | 1719 | struct pxa25x_udc *dev = _dev; |
1715 | int handled; | 1720 | int handled; |
1716 | 1721 | ||
1717 | dev->stats.irqs++; | 1722 | dev->stats.irqs++; |
@@ -1820,9 +1825,9 @@ static void nop_release (struct device *dev) | |||
1820 | * doing it at run-time) to save code, eliminate fault paths, and | 1825 | * doing it at run-time) to save code, eliminate fault paths, and |
1821 | * be more obviously correct. | 1826 | * be more obviously correct. |
1822 | */ | 1827 | */ |
1823 | static struct pxa2xx_udc memory = { | 1828 | static struct pxa25x_udc memory = { |
1824 | .gadget = { | 1829 | .gadget = { |
1825 | .ops = &pxa2xx_udc_ops, | 1830 | .ops = &pxa25x_udc_ops, |
1826 | .ep0 = &memory.ep[0].ep, | 1831 | .ep0 = &memory.ep[0].ep, |
1827 | .name = driver_name, | 1832 | .name = driver_name, |
1828 | .dev = { | 1833 | .dev = { |
@@ -1835,7 +1840,7 @@ static struct pxa2xx_udc memory = { | |||
1835 | .ep[0] = { | 1840 | .ep[0] = { |
1836 | .ep = { | 1841 | .ep = { |
1837 | .name = ep0name, | 1842 | .name = ep0name, |
1838 | .ops = &pxa2xx_ep_ops, | 1843 | .ops = &pxa25x_ep_ops, |
1839 | .maxpacket = EP0_FIFO_SIZE, | 1844 | .maxpacket = EP0_FIFO_SIZE, |
1840 | }, | 1845 | }, |
1841 | .dev = &memory, | 1846 | .dev = &memory, |
@@ -1847,7 +1852,7 @@ static struct pxa2xx_udc memory = { | |||
1847 | .ep[1] = { | 1852 | .ep[1] = { |
1848 | .ep = { | 1853 | .ep = { |
1849 | .name = "ep1in-bulk", | 1854 | .name = "ep1in-bulk", |
1850 | .ops = &pxa2xx_ep_ops, | 1855 | .ops = &pxa25x_ep_ops, |
1851 | .maxpacket = BULK_FIFO_SIZE, | 1856 | .maxpacket = BULK_FIFO_SIZE, |
1852 | }, | 1857 | }, |
1853 | .dev = &memory, | 1858 | .dev = &memory, |
@@ -1860,7 +1865,7 @@ static struct pxa2xx_udc memory = { | |||
1860 | .ep[2] = { | 1865 | .ep[2] = { |
1861 | .ep = { | 1866 | .ep = { |
1862 | .name = "ep2out-bulk", | 1867 | .name = "ep2out-bulk", |
1863 | .ops = &pxa2xx_ep_ops, | 1868 | .ops = &pxa25x_ep_ops, |
1864 | .maxpacket = BULK_FIFO_SIZE, | 1869 | .maxpacket = BULK_FIFO_SIZE, |
1865 | }, | 1870 | }, |
1866 | .dev = &memory, | 1871 | .dev = &memory, |
@@ -1871,11 +1876,11 @@ static struct pxa2xx_udc memory = { | |||
1871 | .reg_ubcr = &UBCR2, | 1876 | .reg_ubcr = &UBCR2, |
1872 | .reg_uddr = &UDDR2, | 1877 | .reg_uddr = &UDDR2, |
1873 | }, | 1878 | }, |
1874 | #ifndef CONFIG_USB_PXA2XX_SMALL | 1879 | #ifndef CONFIG_USB_PXA25X_SMALL |
1875 | .ep[3] = { | 1880 | .ep[3] = { |
1876 | .ep = { | 1881 | .ep = { |
1877 | .name = "ep3in-iso", | 1882 | .name = "ep3in-iso", |
1878 | .ops = &pxa2xx_ep_ops, | 1883 | .ops = &pxa25x_ep_ops, |
1879 | .maxpacket = ISO_FIFO_SIZE, | 1884 | .maxpacket = ISO_FIFO_SIZE, |
1880 | }, | 1885 | }, |
1881 | .dev = &memory, | 1886 | .dev = &memory, |
@@ -1888,7 +1893,7 @@ static struct pxa2xx_udc memory = { | |||
1888 | .ep[4] = { | 1893 | .ep[4] = { |
1889 | .ep = { | 1894 | .ep = { |
1890 | .name = "ep4out-iso", | 1895 | .name = "ep4out-iso", |
1891 | .ops = &pxa2xx_ep_ops, | 1896 | .ops = &pxa25x_ep_ops, |
1892 | .maxpacket = ISO_FIFO_SIZE, | 1897 | .maxpacket = ISO_FIFO_SIZE, |
1893 | }, | 1898 | }, |
1894 | .dev = &memory, | 1899 | .dev = &memory, |
@@ -1902,7 +1907,7 @@ static struct pxa2xx_udc memory = { | |||
1902 | .ep[5] = { | 1907 | .ep[5] = { |
1903 | .ep = { | 1908 | .ep = { |
1904 | .name = "ep5in-int", | 1909 | .name = "ep5in-int", |
1905 | .ops = &pxa2xx_ep_ops, | 1910 | .ops = &pxa25x_ep_ops, |
1906 | .maxpacket = INT_FIFO_SIZE, | 1911 | .maxpacket = INT_FIFO_SIZE, |
1907 | }, | 1912 | }, |
1908 | .dev = &memory, | 1913 | .dev = &memory, |
@@ -1917,7 +1922,7 @@ static struct pxa2xx_udc memory = { | |||
1917 | .ep[6] = { | 1922 | .ep[6] = { |
1918 | .ep = { | 1923 | .ep = { |
1919 | .name = "ep6in-bulk", | 1924 | .name = "ep6in-bulk", |
1920 | .ops = &pxa2xx_ep_ops, | 1925 | .ops = &pxa25x_ep_ops, |
1921 | .maxpacket = BULK_FIFO_SIZE, | 1926 | .maxpacket = BULK_FIFO_SIZE, |
1922 | }, | 1927 | }, |
1923 | .dev = &memory, | 1928 | .dev = &memory, |
@@ -1930,7 +1935,7 @@ static struct pxa2xx_udc memory = { | |||
1930 | .ep[7] = { | 1935 | .ep[7] = { |
1931 | .ep = { | 1936 | .ep = { |
1932 | .name = "ep7out-bulk", | 1937 | .name = "ep7out-bulk", |
1933 | .ops = &pxa2xx_ep_ops, | 1938 | .ops = &pxa25x_ep_ops, |
1934 | .maxpacket = BULK_FIFO_SIZE, | 1939 | .maxpacket = BULK_FIFO_SIZE, |
1935 | }, | 1940 | }, |
1936 | .dev = &memory, | 1941 | .dev = &memory, |
@@ -1944,7 +1949,7 @@ static struct pxa2xx_udc memory = { | |||
1944 | .ep[8] = { | 1949 | .ep[8] = { |
1945 | .ep = { | 1950 | .ep = { |
1946 | .name = "ep8in-iso", | 1951 | .name = "ep8in-iso", |
1947 | .ops = &pxa2xx_ep_ops, | 1952 | .ops = &pxa25x_ep_ops, |
1948 | .maxpacket = ISO_FIFO_SIZE, | 1953 | .maxpacket = ISO_FIFO_SIZE, |
1949 | }, | 1954 | }, |
1950 | .dev = &memory, | 1955 | .dev = &memory, |
@@ -1957,7 +1962,7 @@ static struct pxa2xx_udc memory = { | |||
1957 | .ep[9] = { | 1962 | .ep[9] = { |
1958 | .ep = { | 1963 | .ep = { |
1959 | .name = "ep9out-iso", | 1964 | .name = "ep9out-iso", |
1960 | .ops = &pxa2xx_ep_ops, | 1965 | .ops = &pxa25x_ep_ops, |
1961 | .maxpacket = ISO_FIFO_SIZE, | 1966 | .maxpacket = ISO_FIFO_SIZE, |
1962 | }, | 1967 | }, |
1963 | .dev = &memory, | 1968 | .dev = &memory, |
@@ -1971,7 +1976,7 @@ static struct pxa2xx_udc memory = { | |||
1971 | .ep[10] = { | 1976 | .ep[10] = { |
1972 | .ep = { | 1977 | .ep = { |
1973 | .name = "ep10in-int", | 1978 | .name = "ep10in-int", |
1974 | .ops = &pxa2xx_ep_ops, | 1979 | .ops = &pxa25x_ep_ops, |
1975 | .maxpacket = INT_FIFO_SIZE, | 1980 | .maxpacket = INT_FIFO_SIZE, |
1976 | }, | 1981 | }, |
1977 | .dev = &memory, | 1982 | .dev = &memory, |
@@ -1986,7 +1991,7 @@ static struct pxa2xx_udc memory = { | |||
1986 | .ep[11] = { | 1991 | .ep[11] = { |
1987 | .ep = { | 1992 | .ep = { |
1988 | .name = "ep11in-bulk", | 1993 | .name = "ep11in-bulk", |
1989 | .ops = &pxa2xx_ep_ops, | 1994 | .ops = &pxa25x_ep_ops, |
1990 | .maxpacket = BULK_FIFO_SIZE, | 1995 | .maxpacket = BULK_FIFO_SIZE, |
1991 | }, | 1996 | }, |
1992 | .dev = &memory, | 1997 | .dev = &memory, |
@@ -1999,7 +2004,7 @@ static struct pxa2xx_udc memory = { | |||
1999 | .ep[12] = { | 2004 | .ep[12] = { |
2000 | .ep = { | 2005 | .ep = { |
2001 | .name = "ep12out-bulk", | 2006 | .name = "ep12out-bulk", |
2002 | .ops = &pxa2xx_ep_ops, | 2007 | .ops = &pxa25x_ep_ops, |
2003 | .maxpacket = BULK_FIFO_SIZE, | 2008 | .maxpacket = BULK_FIFO_SIZE, |
2004 | }, | 2009 | }, |
2005 | .dev = &memory, | 2010 | .dev = &memory, |
@@ -2013,7 +2018,7 @@ static struct pxa2xx_udc memory = { | |||
2013 | .ep[13] = { | 2018 | .ep[13] = { |
2014 | .ep = { | 2019 | .ep = { |
2015 | .name = "ep13in-iso", | 2020 | .name = "ep13in-iso", |
2016 | .ops = &pxa2xx_ep_ops, | 2021 | .ops = &pxa25x_ep_ops, |
2017 | .maxpacket = ISO_FIFO_SIZE, | 2022 | .maxpacket = ISO_FIFO_SIZE, |
2018 | }, | 2023 | }, |
2019 | .dev = &memory, | 2024 | .dev = &memory, |
@@ -2026,7 +2031,7 @@ static struct pxa2xx_udc memory = { | |||
2026 | .ep[14] = { | 2031 | .ep[14] = { |
2027 | .ep = { | 2032 | .ep = { |
2028 | .name = "ep14out-iso", | 2033 | .name = "ep14out-iso", |
2029 | .ops = &pxa2xx_ep_ops, | 2034 | .ops = &pxa25x_ep_ops, |
2030 | .maxpacket = ISO_FIFO_SIZE, | 2035 | .maxpacket = ISO_FIFO_SIZE, |
2031 | }, | 2036 | }, |
2032 | .dev = &memory, | 2037 | .dev = &memory, |
@@ -2040,7 +2045,7 @@ static struct pxa2xx_udc memory = { | |||
2040 | .ep[15] = { | 2045 | .ep[15] = { |
2041 | .ep = { | 2046 | .ep = { |
2042 | .name = "ep15in-int", | 2047 | .name = "ep15in-int", |
2043 | .ops = &pxa2xx_ep_ops, | 2048 | .ops = &pxa25x_ep_ops, |
2044 | .maxpacket = INT_FIFO_SIZE, | 2049 | .maxpacket = INT_FIFO_SIZE, |
2045 | }, | 2050 | }, |
2046 | .dev = &memory, | 2051 | .dev = &memory, |
@@ -2050,7 +2055,7 @@ static struct pxa2xx_udc memory = { | |||
2050 | .reg_udccs = &UDCCS15, | 2055 | .reg_udccs = &UDCCS15, |
2051 | .reg_uddr = &UDDR15, | 2056 | .reg_uddr = &UDDR15, |
2052 | }, | 2057 | }, |
2053 | #endif /* !CONFIG_USB_PXA2XX_SMALL */ | 2058 | #endif /* !CONFIG_USB_PXA25X_SMALL */ |
2054 | }; | 2059 | }; |
2055 | 2060 | ||
2056 | #define CP15R0_VENDOR_MASK 0xffffe000 | 2061 | #define CP15R0_VENDOR_MASK 0xffffe000 |
@@ -2090,9 +2095,9 @@ static struct pxa2xx_udc memory = { | |||
2090 | /* | 2095 | /* |
2091 | * probe - binds to the platform device | 2096 | * probe - binds to the platform device |
2092 | */ | 2097 | */ |
2093 | static int __init pxa2xx_udc_probe(struct platform_device *pdev) | 2098 | static int __init pxa25x_udc_probe(struct platform_device *pdev) |
2094 | { | 2099 | { |
2095 | struct pxa2xx_udc *dev = &memory; | 2100 | struct pxa25x_udc *dev = &memory; |
2096 | int retval, vbus_irq, irq; | 2101 | int retval, vbus_irq, irq; |
2097 | u32 chiprev; | 2102 | u32 chiprev; |
2098 | 2103 | ||
@@ -2155,7 +2160,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev) | |||
2155 | 2160 | ||
2156 | if (dev->mach->gpio_vbus) { | 2161 | if (dev->mach->gpio_vbus) { |
2157 | if ((retval = gpio_request(dev->mach->gpio_vbus, | 2162 | if ((retval = gpio_request(dev->mach->gpio_vbus, |
2158 | "pxa2xx_udc GPIO VBUS"))) { | 2163 | "pxa25x_udc GPIO VBUS"))) { |
2159 | dev_dbg(&pdev->dev, | 2164 | dev_dbg(&pdev->dev, |
2160 | "can't get vbus gpio %d, err: %d\n", | 2165 | "can't get vbus gpio %d, err: %d\n", |
2161 | dev->mach->gpio_vbus, retval); | 2166 | dev->mach->gpio_vbus, retval); |
@@ -2168,7 +2173,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev) | |||
2168 | 2173 | ||
2169 | if (dev->mach->gpio_pullup) { | 2174 | if (dev->mach->gpio_pullup) { |
2170 | if ((retval = gpio_request(dev->mach->gpio_pullup, | 2175 | if ((retval = gpio_request(dev->mach->gpio_pullup, |
2171 | "pca2xx_udc GPIO PULLUP"))) { | 2176 | "pca25x_udc GPIO PULLUP"))) { |
2172 | dev_dbg(&pdev->dev, | 2177 | dev_dbg(&pdev->dev, |
2173 | "can't get pullup gpio %d, err: %d\n", | 2178 | "can't get pullup gpio %d, err: %d\n", |
2174 | dev->mach->gpio_pullup, retval); | 2179 | dev->mach->gpio_pullup, retval); |
@@ -2194,7 +2199,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev) | |||
2194 | dev->vbus = is_vbus_present(); | 2199 | dev->vbus = is_vbus_present(); |
2195 | 2200 | ||
2196 | /* irq setup after old hardware state is cleaned up */ | 2201 | /* irq setup after old hardware state is cleaned up */ |
2197 | retval = request_irq(irq, pxa2xx_udc_irq, | 2202 | retval = request_irq(irq, pxa25x_udc_irq, |
2198 | IRQF_DISABLED, driver_name, dev); | 2203 | IRQF_DISABLED, driver_name, dev); |
2199 | if (retval != 0) { | 2204 | if (retval != 0) { |
2200 | pr_err("%s: can't get irq %d, err %d\n", | 2205 | pr_err("%s: can't get irq %d, err %d\n", |
@@ -2260,14 +2265,14 @@ lubbock_fail0: | |||
2260 | return retval; | 2265 | return retval; |
2261 | } | 2266 | } |
2262 | 2267 | ||
2263 | static void pxa2xx_udc_shutdown(struct platform_device *_dev) | 2268 | static void pxa25x_udc_shutdown(struct platform_device *_dev) |
2264 | { | 2269 | { |
2265 | pullup_off(); | 2270 | pullup_off(); |
2266 | } | 2271 | } |
2267 | 2272 | ||
2268 | static int __exit pxa2xx_udc_remove(struct platform_device *pdev) | 2273 | static int __exit pxa25x_udc_remove(struct platform_device *pdev) |
2269 | { | 2274 | { |
2270 | struct pxa2xx_udc *dev = platform_get_drvdata(pdev); | 2275 | struct pxa25x_udc *dev = platform_get_drvdata(pdev); |
2271 | 2276 | ||
2272 | if (dev->driver) | 2277 | if (dev->driver) |
2273 | return -EBUSY; | 2278 | return -EBUSY; |
@@ -2317,9 +2322,9 @@ static int __exit pxa2xx_udc_remove(struct platform_device *pdev) | |||
2317 | * VBUS IRQs should probably be ignored so that the PXA device just acts | 2322 | * VBUS IRQs should probably be ignored so that the PXA device just acts |
2318 | * "dead" to USB hosts until system resume. | 2323 | * "dead" to USB hosts until system resume. |
2319 | */ | 2324 | */ |
2320 | static int pxa2xx_udc_suspend(struct platform_device *dev, pm_message_t state) | 2325 | static int pxa25x_udc_suspend(struct platform_device *dev, pm_message_t state) |
2321 | { | 2326 | { |
2322 | struct pxa2xx_udc *udc = platform_get_drvdata(dev); | 2327 | struct pxa25x_udc *udc = platform_get_drvdata(dev); |
2323 | unsigned long flags; | 2328 | unsigned long flags; |
2324 | 2329 | ||
2325 | if (!udc->mach->gpio_pullup && !udc->mach->udc_command) | 2330 | if (!udc->mach->gpio_pullup && !udc->mach->udc_command) |
@@ -2333,9 +2338,9 @@ static int pxa2xx_udc_suspend(struct platform_device *dev, pm_message_t state) | |||
2333 | return 0; | 2338 | return 0; |
2334 | } | 2339 | } |
2335 | 2340 | ||
2336 | static int pxa2xx_udc_resume(struct platform_device *dev) | 2341 | static int pxa25x_udc_resume(struct platform_device *dev) |
2337 | { | 2342 | { |
2338 | struct pxa2xx_udc *udc = platform_get_drvdata(dev); | 2343 | struct pxa25x_udc *udc = platform_get_drvdata(dev); |
2339 | unsigned long flags; | 2344 | unsigned long flags; |
2340 | 2345 | ||
2341 | udc->suspended = 0; | 2346 | udc->suspended = 0; |
@@ -2347,27 +2352,27 @@ static int pxa2xx_udc_resume(struct platform_device *dev) | |||
2347 | } | 2352 | } |
2348 | 2353 | ||
2349 | #else | 2354 | #else |
2350 | #define pxa2xx_udc_suspend NULL | 2355 | #define pxa25x_udc_suspend NULL |
2351 | #define pxa2xx_udc_resume NULL | 2356 | #define pxa25x_udc_resume NULL |
2352 | #endif | 2357 | #endif |
2353 | 2358 | ||
2354 | /*-------------------------------------------------------------------------*/ | 2359 | /*-------------------------------------------------------------------------*/ |
2355 | 2360 | ||
2356 | static struct platform_driver udc_driver = { | 2361 | static struct platform_driver udc_driver = { |
2357 | .shutdown = pxa2xx_udc_shutdown, | 2362 | .shutdown = pxa25x_udc_shutdown, |
2358 | .remove = __exit_p(pxa2xx_udc_remove), | 2363 | .remove = __exit_p(pxa25x_udc_remove), |
2359 | .suspend = pxa2xx_udc_suspend, | 2364 | .suspend = pxa25x_udc_suspend, |
2360 | .resume = pxa2xx_udc_resume, | 2365 | .resume = pxa25x_udc_resume, |
2361 | .driver = { | 2366 | .driver = { |
2362 | .owner = THIS_MODULE, | 2367 | .owner = THIS_MODULE, |
2363 | .name = "pxa2xx-udc", | 2368 | .name = "pxa25x-udc", |
2364 | }, | 2369 | }, |
2365 | }; | 2370 | }; |
2366 | 2371 | ||
2367 | static int __init udc_init(void) | 2372 | static int __init udc_init(void) |
2368 | { | 2373 | { |
2369 | pr_info("%s: version %s\n", driver_name, DRIVER_VERSION); | 2374 | pr_info("%s: version %s\n", driver_name, DRIVER_VERSION); |
2370 | return platform_driver_probe(&udc_driver, pxa2xx_udc_probe); | 2375 | return platform_driver_probe(&udc_driver, pxa25x_udc_probe); |
2371 | } | 2376 | } |
2372 | module_init(udc_init); | 2377 | module_init(udc_init); |
2373 | 2378 | ||
@@ -2380,4 +2385,4 @@ module_exit(udc_exit); | |||
2380 | MODULE_DESCRIPTION(DRIVER_DESC); | 2385 | MODULE_DESCRIPTION(DRIVER_DESC); |
2381 | MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell"); | 2386 | MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell"); |
2382 | MODULE_LICENSE("GPL"); | 2387 | MODULE_LICENSE("GPL"); |
2383 | MODULE_ALIAS("platform:pxa2xx-udc"); | 2388 | MODULE_ALIAS("platform:pxa25x-udc"); |
diff --git a/drivers/usb/gadget/pxa2xx_udc.h b/drivers/usb/gadget/pxa25x_udc.h index e2c19e88c875..4d11ece7c95f 100644 --- a/drivers/usb/gadget/pxa2xx_udc.h +++ b/drivers/usb/gadget/pxa25x_udc.h | |||
@@ -1,6 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * linux/drivers/usb/gadget/pxa2xx_udc.h | 2 | * Intel PXA25x on-chip full speed USB device controller |
3 | * Intel PXA2xx on-chip full speed USB device controller | ||
4 | * | 3 | * |
5 | * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix | 4 | * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix |
6 | * Copyright (C) 2003 David Brownell | 5 | * Copyright (C) 2003 David Brownell |
@@ -21,14 +20,14 @@ | |||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
22 | */ | 21 | */ |
23 | 22 | ||
24 | #ifndef __LINUX_USB_GADGET_PXA2XX_H | 23 | #ifndef __LINUX_USB_GADGET_PXA25X_H |
25 | #define __LINUX_USB_GADGET_PXA2XX_H | 24 | #define __LINUX_USB_GADGET_PXA25X_H |
26 | 25 | ||
27 | #include <linux/types.h> | 26 | #include <linux/types.h> |
28 | 27 | ||
29 | /*-------------------------------------------------------------------------*/ | 28 | /*-------------------------------------------------------------------------*/ |
30 | 29 | ||
31 | /* pxa2xx has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */ | 30 | /* pxa25x has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */ |
32 | #define UFNRH_SIR (1 << 7) /* SOF interrupt request */ | 31 | #define UFNRH_SIR (1 << 7) /* SOF interrupt request */ |
33 | #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ | 32 | #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ |
34 | #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ | 33 | #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ |
@@ -45,11 +44,11 @@ | |||
45 | 44 | ||
46 | /*-------------------------------------------------------------------------*/ | 45 | /*-------------------------------------------------------------------------*/ |
47 | 46 | ||
48 | struct pxa2xx_udc; | 47 | struct pxa25x_udc; |
49 | 48 | ||
50 | struct pxa2xx_ep { | 49 | struct pxa25x_ep { |
51 | struct usb_ep ep; | 50 | struct usb_ep ep; |
52 | struct pxa2xx_udc *dev; | 51 | struct pxa25x_udc *dev; |
53 | 52 | ||
54 | const struct usb_endpoint_descriptor *desc; | 53 | const struct usb_endpoint_descriptor *desc; |
55 | struct list_head queue; | 54 | struct list_head queue; |
@@ -72,7 +71,7 @@ struct pxa2xx_ep { | |||
72 | volatile u32 *reg_uddr; | 71 | volatile u32 *reg_uddr; |
73 | }; | 72 | }; |
74 | 73 | ||
75 | struct pxa2xx_request { | 74 | struct pxa25x_request { |
76 | struct usb_request req; | 75 | struct usb_request req; |
77 | struct list_head queue; | 76 | struct list_head queue; |
78 | }; | 77 | }; |
@@ -98,7 +97,7 @@ struct udc_stats { | |||
98 | unsigned long irqs; | 97 | unsigned long irqs; |
99 | }; | 98 | }; |
100 | 99 | ||
101 | #ifdef CONFIG_USB_PXA2XX_SMALL | 100 | #ifdef CONFIG_USB_PXA25X_SMALL |
102 | /* when memory's tight, SMALL config saves code+data. */ | 101 | /* when memory's tight, SMALL config saves code+data. */ |
103 | #define PXA_UDC_NUM_ENDPOINTS 3 | 102 | #define PXA_UDC_NUM_ENDPOINTS 3 |
104 | #endif | 103 | #endif |
@@ -107,7 +106,7 @@ struct udc_stats { | |||
107 | #define PXA_UDC_NUM_ENDPOINTS 16 | 106 | #define PXA_UDC_NUM_ENDPOINTS 16 |
108 | #endif | 107 | #endif |
109 | 108 | ||
110 | struct pxa2xx_udc { | 109 | struct pxa25x_udc { |
111 | struct usb_gadget gadget; | 110 | struct usb_gadget gadget; |
112 | struct usb_gadget_driver *driver; | 111 | struct usb_gadget_driver *driver; |
113 | 112 | ||
@@ -130,7 +129,7 @@ struct pxa2xx_udc { | |||
130 | struct clk *clk; | 129 | struct clk *clk; |
131 | struct pxa2xx_udc_mach_info *mach; | 130 | struct pxa2xx_udc_mach_info *mach; |
132 | u64 dma_mask; | 131 | u64 dma_mask; |
133 | struct pxa2xx_ep ep [PXA_UDC_NUM_ENDPOINTS]; | 132 | struct pxa25x_ep ep [PXA_UDC_NUM_ENDPOINTS]; |
134 | 133 | ||
135 | #ifdef CONFIG_USB_GADGET_DEBUG_FS | 134 | #ifdef CONFIG_USB_GADGET_DEBUG_FS |
136 | struct dentry *debugfs_udc; | 135 | struct dentry *debugfs_udc; |
@@ -144,7 +143,7 @@ struct pxa2xx_udc { | |||
144 | /* lubbock can also report usb connect/disconnect irqs */ | 143 | /* lubbock can also report usb connect/disconnect irqs */ |
145 | #endif | 144 | #endif |
146 | 145 | ||
147 | static struct pxa2xx_udc *the_controller; | 146 | static struct pxa25x_udc *the_controller; |
148 | 147 | ||
149 | /*-------------------------------------------------------------------------*/ | 148 | /*-------------------------------------------------------------------------*/ |
150 | 149 | ||
@@ -209,7 +208,7 @@ dump_udccs0(const char *label) | |||
209 | } | 208 | } |
210 | 209 | ||
211 | static void __maybe_unused | 210 | static void __maybe_unused |
212 | dump_state(struct pxa2xx_udc *dev) | 211 | dump_state(struct pxa25x_udc *dev) |
213 | { | 212 | { |
214 | u32 tmp; | 213 | u32 tmp; |
215 | unsigned i; | 214 | unsigned i; |
@@ -264,4 +263,4 @@ dump_state(struct pxa2xx_udc *dev) | |||
264 | #define INFO(stuff...) pr_info("udc: " stuff) | 263 | #define INFO(stuff...) pr_info("udc: " stuff) |
265 | 264 | ||
266 | 265 | ||
267 | #endif /* __LINUX_USB_GADGET_PXA2XX_H */ | 266 | #endif /* __LINUX_USB_GADGET_PXA25X_H */ |
diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c index e02bfd4df3a6..9c0e82ec5c43 100644 --- a/drivers/usb/gadget/pxa27x_udc.c +++ b/drivers/usb/gadget/pxa27x_udc.c | |||
@@ -38,7 +38,7 @@ | |||
38 | #include <linux/usb.h> | 38 | #include <linux/usb.h> |
39 | #include <linux/usb/ch9.h> | 39 | #include <linux/usb/ch9.h> |
40 | #include <linux/usb/gadget.h> | 40 | #include <linux/usb/gadget.h> |
41 | 41 | #include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */ | |
42 | #include <asm/arch/udc.h> | 42 | #include <asm/arch/udc.h> |
43 | 43 | ||
44 | #include "pxa27x_udc.h" | 44 | #include "pxa27x_udc.h" |
@@ -2360,18 +2360,19 @@ static int pxa_udc_resume(struct platform_device *_dev) | |||
2360 | * Software must configure the USB OTG pad, UDC, and UHC | 2360 | * Software must configure the USB OTG pad, UDC, and UHC |
2361 | * to the state they were in before entering sleep mode. | 2361 | * to the state they were in before entering sleep mode. |
2362 | */ | 2362 | */ |
2363 | PSSR |= PSSR_OTGPH; | 2363 | if (cpu_is_pxa27x()) |
2364 | PSSR |= PSSR_OTGPH; | ||
2364 | 2365 | ||
2365 | return 0; | 2366 | return 0; |
2366 | } | 2367 | } |
2367 | #endif | 2368 | #endif |
2368 | 2369 | ||
2369 | /* work with hotplug and coldplug */ | 2370 | /* work with hotplug and coldplug */ |
2370 | MODULE_ALIAS("platform:pxa2xx-udc"); | 2371 | MODULE_ALIAS("platform:pxa27x-udc"); |
2371 | 2372 | ||
2372 | static struct platform_driver udc_driver = { | 2373 | static struct platform_driver udc_driver = { |
2373 | .driver = { | 2374 | .driver = { |
2374 | .name = "pxa2xx-udc", | 2375 | .name = "pxa27x-udc", |
2375 | .owner = THIS_MODULE, | 2376 | .owner = THIS_MODULE, |
2376 | }, | 2377 | }, |
2377 | .remove = __exit_p(pxa_udc_remove), | 2378 | .remove = __exit_p(pxa_udc_remove), |
diff --git a/drivers/usb/gadget/pxa27x_udc.h b/drivers/usb/gadget/pxa27x_udc.h index 97453db924ff..1d1b7936ee11 100644 --- a/drivers/usb/gadget/pxa27x_udc.h +++ b/drivers/usb/gadget/pxa27x_udc.h | |||
@@ -484,12 +484,4 @@ static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget) | |||
484 | #define ep_warn(ep, fmt, arg...) \ | 484 | #define ep_warn(ep, fmt, arg...) \ |
485 | dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg) | 485 | dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg) |
486 | 486 | ||
487 | /* | ||
488 | * Cannot include pxa-regs.h, as register names are similar. | ||
489 | * So PSSR is redefined here. This should be removed once UDC registers will | ||
490 | * be gone from pxa-regs.h. | ||
491 | */ | ||
492 | #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status */ | ||
493 | #define PSSR_OTGPH (1 << 6) /* OTG Peripheral Hold */ | ||
494 | |||
495 | #endif /* __LINUX_USB_GADGET_PXA27X_H */ | 487 | #endif /* __LINUX_USB_GADGET_PXA27X_H */ |
diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c index 3a7c24c03671..a19a4f80a6e1 100644 --- a/drivers/usb/host/ohci-omap.c +++ b/drivers/usb/host/ohci-omap.c | |||
@@ -169,13 +169,16 @@ static void start_hnp(struct ohci_hcd *ohci) | |||
169 | { | 169 | { |
170 | const unsigned port = ohci_to_hcd(ohci)->self.otg_port - 1; | 170 | const unsigned port = ohci_to_hcd(ohci)->self.otg_port - 1; |
171 | unsigned long flags; | 171 | unsigned long flags; |
172 | u32 l; | ||
172 | 173 | ||
173 | otg_start_hnp(ohci->transceiver); | 174 | otg_start_hnp(ohci->transceiver); |
174 | 175 | ||
175 | local_irq_save(flags); | 176 | local_irq_save(flags); |
176 | ohci->transceiver->state = OTG_STATE_A_SUSPEND; | 177 | ohci->transceiver->state = OTG_STATE_A_SUSPEND; |
177 | writel (RH_PS_PSS, &ohci->regs->roothub.portstatus [port]); | 178 | writel (RH_PS_PSS, &ohci->regs->roothub.portstatus [port]); |
178 | OTG_CTRL_REG &= ~OTG_A_BUSREQ; | 179 | l = omap_readl(OTG_CTRL); |
180 | l &= ~OTG_A_BUSREQ; | ||
181 | omap_writel(l, OTG_CTRL); | ||
179 | local_irq_restore(flags); | 182 | local_irq_restore(flags); |
180 | } | 183 | } |
181 | 184 | ||
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c index d4ee27d92be8..127b15799024 100644 --- a/drivers/usb/host/ohci-pxa27x.c +++ b/drivers/usb/host/ohci-pxa27x.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
28 | #include <asm/hardware.h> | 28 | #include <asm/hardware.h> |
29 | #include <asm/arch/pxa-regs.h> | 29 | #include <asm/arch/pxa-regs.h> |
30 | #include <asm/arch/pxa2xx-regs.h> /* FIXME: for PSSR */ | ||
30 | #include <asm/arch/ohci.h> | 31 | #include <asm/arch/ohci.h> |
31 | 32 | ||
32 | #define PXA_UHC_MAX_PORTNUM 3 | 33 | #define PXA_UHC_MAX_PORTNUM 3 |
@@ -104,7 +105,7 @@ static int pxa27x_start_hc(struct device *dev) | |||
104 | UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); | 105 | UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); |
105 | 106 | ||
106 | /* Clear any OTG Pin Hold */ | 107 | /* Clear any OTG Pin Hold */ |
107 | if (PSSR & PSSR_OTGPH) | 108 | if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH)) |
108 | PSSR |= PSSR_OTGPH; | 109 | PSSR |= PSSR_OTGPH; |
109 | 110 | ||
110 | return 0; | 111 | return 0; |
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig index dcd8073c2369..30bf7f2f1635 100644 --- a/drivers/video/backlight/Kconfig +++ b/drivers/video/backlight/Kconfig | |||
@@ -112,3 +112,10 @@ config BACKLIGHT_CARILLO_RANCH | |||
112 | help | 112 | help |
113 | If you have a Intel LE80578 (Carillo Ranch) say Y to enable the | 113 | If you have a Intel LE80578 (Carillo Ranch) say Y to enable the |
114 | backlight driver. | 114 | backlight driver. |
115 | |||
116 | config BACKLIGHT_PWM | ||
117 | tristate "Generic PWM based Backlight Driver" | ||
118 | depends on BACKLIGHT_CLASS_DEVICE && HAVE_PWM | ||
119 | help | ||
120 | If you have a LCD backlight adjustable by PWM, say Y to enable | ||
121 | this driver. | ||
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile index 33f6c7cecc73..b51a7cd12500 100644 --- a/drivers/video/backlight/Makefile +++ b/drivers/video/backlight/Makefile | |||
@@ -10,3 +10,4 @@ obj-$(CONFIG_BACKLIGHT_LOCOMO) += locomolcd.o | |||
10 | obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o | 10 | obj-$(CONFIG_BACKLIGHT_OMAP1) += omap1_bl.o |
11 | obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o | 11 | obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o |
12 | obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o | 12 | obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o |
13 | obj-$(CONFIG_BACKLIGHT_PWM) += pwm_bl.o | ||
diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c new file mode 100644 index 000000000000..6338d0e2fe07 --- /dev/null +++ b/drivers/video/backlight/pwm_bl.c | |||
@@ -0,0 +1,185 @@ | |||
1 | /* | ||
2 | * linux/drivers/video/backlight/pwm_bl.c | ||
3 | * | ||
4 | * simple PWM based backlight control, board code has to setup | ||
5 | * 1) pin configuration so PWM waveforms can output | ||
6 | * 2) platform_data casts to the PWM id (0/1/2/3 on PXA) | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/module.h> | ||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/init.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/fb.h> | ||
18 | #include <linux/backlight.h> | ||
19 | #include <linux/err.h> | ||
20 | #include <linux/pwm.h> | ||
21 | #include <linux/pwm_backlight.h> | ||
22 | |||
23 | struct pwm_bl_data { | ||
24 | struct pwm_device *pwm; | ||
25 | unsigned int period; | ||
26 | int (*notify)(int brightness); | ||
27 | }; | ||
28 | |||
29 | static int pwm_backlight_update_status(struct backlight_device *bl) | ||
30 | { | ||
31 | struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev); | ||
32 | int brightness = bl->props.brightness; | ||
33 | int max = bl->props.max_brightness; | ||
34 | |||
35 | if (bl->props.power != FB_BLANK_UNBLANK) | ||
36 | brightness = 0; | ||
37 | |||
38 | if (bl->props.fb_blank != FB_BLANK_UNBLANK) | ||
39 | brightness = 0; | ||
40 | |||
41 | if (pb->notify) | ||
42 | brightness = pb->notify(brightness); | ||
43 | |||
44 | if (brightness == 0) { | ||
45 | pwm_config(pb->pwm, 0, pb->period); | ||
46 | pwm_disable(pb->pwm); | ||
47 | } else { | ||
48 | pwm_config(pb->pwm, brightness * pb->period / max, pb->period); | ||
49 | pwm_enable(pb->pwm); | ||
50 | } | ||
51 | return 0; | ||
52 | } | ||
53 | |||
54 | static int pwm_backlight_get_brightness(struct backlight_device *bl) | ||
55 | { | ||
56 | return bl->props.brightness; | ||
57 | } | ||
58 | |||
59 | static struct backlight_ops pwm_backlight_ops = { | ||
60 | .update_status = pwm_backlight_update_status, | ||
61 | .get_brightness = pwm_backlight_get_brightness, | ||
62 | }; | ||
63 | |||
64 | static int pwm_backlight_probe(struct platform_device *pdev) | ||
65 | { | ||
66 | struct platform_pwm_backlight_data *data = pdev->dev.platform_data; | ||
67 | struct backlight_device *bl; | ||
68 | struct pwm_bl_data *pb; | ||
69 | int ret; | ||
70 | |||
71 | if (!data) | ||
72 | return -EINVAL; | ||
73 | |||
74 | if (data->init) { | ||
75 | ret = data->init(&pdev->dev); | ||
76 | if (ret < 0) | ||
77 | return ret; | ||
78 | } | ||
79 | |||
80 | pb = kzalloc(sizeof(*pb), GFP_KERNEL); | ||
81 | if (!pb) { | ||
82 | ret = -ENOMEM; | ||
83 | goto err_alloc; | ||
84 | } | ||
85 | |||
86 | pb->period = data->pwm_period_ns; | ||
87 | pb->notify = data->notify; | ||
88 | |||
89 | pb->pwm = pwm_request(data->pwm_id, "backlight"); | ||
90 | if (IS_ERR(pb->pwm)) { | ||
91 | dev_err(&pdev->dev, "unable to request PWM for backlight\n"); | ||
92 | ret = PTR_ERR(pb->pwm); | ||
93 | goto err_pwm; | ||
94 | } | ||
95 | |||
96 | bl = backlight_device_register(pdev->name, &pdev->dev, | ||
97 | pb, &pwm_backlight_ops); | ||
98 | if (IS_ERR(bl)) { | ||
99 | dev_err(&pdev->dev, "failed to register backlight\n"); | ||
100 | ret = PTR_ERR(bl); | ||
101 | goto err_bl; | ||
102 | } | ||
103 | |||
104 | bl->props.max_brightness = data->max_brightness; | ||
105 | bl->props.brightness = data->dft_brightness; | ||
106 | backlight_update_status(bl); | ||
107 | |||
108 | platform_set_drvdata(pdev, bl); | ||
109 | return 0; | ||
110 | |||
111 | err_bl: | ||
112 | pwm_free(pb->pwm); | ||
113 | err_pwm: | ||
114 | kfree(pb); | ||
115 | err_alloc: | ||
116 | if (data->exit) | ||
117 | data->exit(&pdev->dev); | ||
118 | return ret; | ||
119 | } | ||
120 | |||
121 | static int pwm_backlight_remove(struct platform_device *pdev) | ||
122 | { | ||
123 | struct platform_pwm_backlight_data *data = pdev->dev.platform_data; | ||
124 | struct backlight_device *bl = platform_get_drvdata(pdev); | ||
125 | struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev); | ||
126 | |||
127 | backlight_device_unregister(bl); | ||
128 | pwm_config(pb->pwm, 0, pb->period); | ||
129 | pwm_disable(pb->pwm); | ||
130 | pwm_free(pb->pwm); | ||
131 | kfree(pb); | ||
132 | if (data->exit) | ||
133 | data->exit(&pdev->dev); | ||
134 | return 0; | ||
135 | } | ||
136 | |||
137 | #ifdef CONFIG_PM | ||
138 | static int pwm_backlight_suspend(struct platform_device *pdev, | ||
139 | pm_message_t state) | ||
140 | { | ||
141 | struct backlight_device *bl = platform_get_drvdata(pdev); | ||
142 | struct pwm_bl_data *pb = dev_get_drvdata(&bl->dev); | ||
143 | |||
144 | pwm_config(pb->pwm, 0, pb->period); | ||
145 | pwm_disable(pb->pwm); | ||
146 | return 0; | ||
147 | } | ||
148 | |||
149 | static int pwm_backlight_resume(struct platform_device *pdev) | ||
150 | { | ||
151 | struct backlight_device *bl = platform_get_drvdata(pdev); | ||
152 | |||
153 | backlight_update_status(bl); | ||
154 | return 0; | ||
155 | } | ||
156 | #else | ||
157 | #define pwm_backlight_suspend NULL | ||
158 | #define pwm_backlight_resume NULL | ||
159 | #endif | ||
160 | |||
161 | static struct platform_driver pwm_backlight_driver = { | ||
162 | .driver = { | ||
163 | .name = "pwm-backlight", | ||
164 | .owner = THIS_MODULE, | ||
165 | }, | ||
166 | .probe = pwm_backlight_probe, | ||
167 | .remove = pwm_backlight_remove, | ||
168 | .suspend = pwm_backlight_suspend, | ||
169 | .resume = pwm_backlight_resume, | ||
170 | }; | ||
171 | |||
172 | static int __init pwm_backlight_init(void) | ||
173 | { | ||
174 | return platform_driver_register(&pwm_backlight_driver); | ||
175 | } | ||
176 | module_init(pwm_backlight_init); | ||
177 | |||
178 | static void __exit pwm_backlight_exit(void) | ||
179 | { | ||
180 | platform_driver_unregister(&pwm_backlight_driver); | ||
181 | } | ||
182 | module_exit(pwm_backlight_exit); | ||
183 | |||
184 | MODULE_DESCRIPTION("PWM based Backlight Driver"); | ||
185 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index fafe7db20d6d..d0746261c957 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c | |||
@@ -1792,11 +1792,49 @@ failed: | |||
1792 | return ret; | 1792 | return ret; |
1793 | } | 1793 | } |
1794 | 1794 | ||
1795 | static int __devexit pxafb_remove(struct platform_device *dev) | ||
1796 | { | ||
1797 | struct pxafb_info *fbi = platform_get_drvdata(dev); | ||
1798 | struct resource *r; | ||
1799 | int irq; | ||
1800 | struct fb_info *info; | ||
1801 | |||
1802 | if (!fbi) | ||
1803 | return 0; | ||
1804 | |||
1805 | info = &fbi->fb; | ||
1806 | |||
1807 | unregister_framebuffer(info); | ||
1808 | |||
1809 | pxafb_disable_controller(fbi); | ||
1810 | |||
1811 | if (fbi->fb.cmap.len) | ||
1812 | fb_dealloc_cmap(&fbi->fb.cmap); | ||
1813 | |||
1814 | irq = platform_get_irq(dev, 0); | ||
1815 | free_irq(irq, fbi); | ||
1816 | |||
1817 | dma_free_writecombine(&dev->dev, fbi->map_size, | ||
1818 | fbi->map_cpu, fbi->map_dma); | ||
1819 | |||
1820 | iounmap(fbi->mmio_base); | ||
1821 | |||
1822 | r = platform_get_resource(dev, IORESOURCE_MEM, 0); | ||
1823 | release_mem_region(r->start, r->end - r->start + 1); | ||
1824 | |||
1825 | clk_put(fbi->clk); | ||
1826 | kfree(fbi); | ||
1827 | |||
1828 | return 0; | ||
1829 | } | ||
1830 | |||
1795 | static struct platform_driver pxafb_driver = { | 1831 | static struct platform_driver pxafb_driver = { |
1796 | .probe = pxafb_probe, | 1832 | .probe = pxafb_probe, |
1833 | .remove = pxafb_remove, | ||
1797 | .suspend = pxafb_suspend, | 1834 | .suspend = pxafb_suspend, |
1798 | .resume = pxafb_resume, | 1835 | .resume = pxafb_resume, |
1799 | .driver = { | 1836 | .driver = { |
1837 | .owner = THIS_MODULE, | ||
1800 | .name = "pxa2xx-fb", | 1838 | .name = "pxa2xx-fb", |
1801 | }, | 1839 | }, |
1802 | }; | 1840 | }; |
@@ -1809,7 +1847,13 @@ static int __init pxafb_init(void) | |||
1809 | return platform_driver_register(&pxafb_driver); | 1847 | return platform_driver_register(&pxafb_driver); |
1810 | } | 1848 | } |
1811 | 1849 | ||
1850 | static void __exit pxafb_exit(void) | ||
1851 | { | ||
1852 | platform_driver_unregister(&pxafb_driver); | ||
1853 | } | ||
1854 | |||
1812 | module_init(pxafb_init); | 1855 | module_init(pxafb_init); |
1856 | module_exit(pxafb_exit); | ||
1813 | 1857 | ||
1814 | MODULE_DESCRIPTION("loadable framebuffer driver for PXA"); | 1858 | MODULE_DESCRIPTION("loadable framebuffer driver for PXA"); |
1815 | MODULE_LICENSE("GPL"); | 1859 | MODULE_LICENSE("GPL"); |