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authorYaniv Rosner <yaniv.rosner@broadcom.com>2010-09-07 07:40:58 -0400
committerDavid S. Miller <davem@davemloft.net>2010-09-07 16:13:37 -0400
commit62b29a5dd0930e0c956b6740f32d5b3bbaf20136 (patch)
treef2924249c994f3e76439740afb341e42b7a7ee2c /drivers
parentb7737c9be9d3e894d1a4375c52f5f47789475f26 (diff)
bnx2x: Adjust alignment of split PHY functions
In previous patch, common PHY functions were split in simple way to allow easy diff. This patch comes to align code in the new functions. In addition, the non-production BCM8072 PHY was removed. Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/bnx2x/bnx2x_link.c2164
-rw-r--r--drivers/net/bnx2x/bnx2x_main.c1
2 files changed, 894 insertions, 1271 deletions
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index c1540727cdbf..c2f1e3c24c0b 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -2096,7 +2096,7 @@ void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
2096 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 2096 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2097 msleep(1); 2097 msleep(1);
2098 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 2098 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2099 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 2099 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
2100} 2100}
2101 2101
2102static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, 2102static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
@@ -2133,30 +2133,14 @@ static void bnx2x_save_8481_spirom_version(struct bnx2x_phy *phy,
2133 2133
2134 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/ 2134 /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
2135 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 2135 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
2136 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 2136 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
2137 0xA819, 0x0014); 2137 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
2138 bnx2x_cl45_write(bp, phy, 2138 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
2139 MDIO_PMA_DEVAD, 2139 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
2140 0xA81A, 2140 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
2141 0xc200);
2142 bnx2x_cl45_write(bp, phy,
2143 MDIO_PMA_DEVAD,
2144 0xA81B,
2145 0x0000);
2146 bnx2x_cl45_write(bp, phy,
2147 MDIO_PMA_DEVAD,
2148 0xA81C,
2149 0x0300);
2150 bnx2x_cl45_write(bp, phy,
2151 MDIO_PMA_DEVAD,
2152 0xA817,
2153 0x0009);
2154 2141
2155 for (cnt = 0; cnt < 100; cnt++) { 2142 for (cnt = 0; cnt < 100; cnt++) {
2156 bnx2x_cl45_read(bp, phy, 2143 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
2157 MDIO_PMA_DEVAD,
2158 0xA818,
2159 &val);
2160 if (val & 1) 2144 if (val & 1)
2161 break; 2145 break;
2162 udelay(5); 2146 udelay(5);
@@ -2170,86 +2154,29 @@ static void bnx2x_save_8481_spirom_version(struct bnx2x_phy *phy,
2170 2154
2171 2155
2172 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 2156 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
2173 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 2157 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
2174 0xA819, 0x0000); 2158 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
2175 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 2159 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
2176 0xA81A, 0xc200);
2177 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
2178 0xA817, 0x000A);
2179 for (cnt = 0; cnt < 100; cnt++) { 2160 for (cnt = 0; cnt < 100; cnt++) {
2180 bnx2x_cl45_read(bp, phy, 2161 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
2181 MDIO_PMA_DEVAD,
2182 0xA818,
2183 &val);
2184 if (val & 1) 2162 if (val & 1)
2185 break; 2163 break;
2186 udelay(5); 2164 udelay(5);
2187 } 2165 }
2188 if (cnt == 100) { 2166 if (cnt == 100) {
2189 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n"); 2167 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
2190 bnx2x_save_spirom_version(bp, params->port, 2168 bnx2x_save_spirom_version(bp, params->port, 0,
2191 shmem_base, 0); 2169 phy->ver_addr);
2192 return; 2170 return;
2193 } 2171 }
2194 2172
2195 /* lower 16 bits of the register SPI_FW_STATUS */ 2173 /* lower 16 bits of the register SPI_FW_STATUS */
2196 bnx2x_cl45_read(bp, phy, 2174 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
2197 MDIO_PMA_DEVAD,
2198 0xA81B,
2199 &fw_ver1);
2200 /* upper 16 bits of register SPI_FW_STATUS */ 2175 /* upper 16 bits of register SPI_FW_STATUS */
2201 bnx2x_cl45_read(bp, phy, 2176 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
2202 MDIO_PMA_DEVAD,
2203 0xA81C,
2204 &fw_ver2);
2205
2206 bnx2x_save_spirom_version(bp, params->port,
2207 shmem_base, (fw_ver2<<16) | fw_ver1);
2208}
2209
2210static void bnx2x_bcm8072_external_rom_boot(struct bnx2x_phy *phy,
2211 struct link_params *params)
2212{
2213 struct bnx2x *bp = params->bp;
2214 u8 port = params->port;
2215
2216 /* Need to wait 200ms after reset */
2217 msleep(200);
2218 /* Boot port from external ROM
2219 * Set ser_boot_ctl bit in the MISC_CTRL1 register
2220 */
2221 bnx2x_cl45_write(bp, phy,
2222 MDIO_PMA_DEVAD,
2223 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2224 2177
2225 /* Reset internal microprocessor */ 2178 bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
2226 bnx2x_cl45_write(bp, phy, 2179 phy->ver_addr);
2227 MDIO_PMA_DEVAD,
2228 MDIO_PMA_REG_GEN_CTRL,
2229 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2230 /* set micro reset = 0 */
2231 bnx2x_cl45_write(bp, phy,
2232 MDIO_PMA_DEVAD,
2233 MDIO_PMA_REG_GEN_CTRL,
2234 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2235 /* Reset internal microprocessor */
2236 bnx2x_cl45_write(bp, phy,
2237 MDIO_PMA_DEVAD,
2238 MDIO_PMA_REG_GEN_CTRL,
2239 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2240 /* wait for 100ms for code download via SPI port */
2241 msleep(100);
2242
2243 /* Clear ser_boot_ctl bit */
2244 bnx2x_cl45_write(bp, phy,
2245 MDIO_PMA_DEVAD,
2246 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2247 /* Wait 100ms */
2248 msleep(100);
2249
2250 bnx2x_save_bcm_spirom_ver(bp, port,
2251 phy,
2252 params->shmem_base);
2253} 2180}
2254 2181
2255static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) 2182static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
@@ -2382,9 +2309,7 @@ static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
2382 2309
2383 /* Micro controller re-boot */ 2310 /* Micro controller re-boot */
2384 bnx2x_cl45_write(bp, phy, 2311 bnx2x_cl45_write(bp, phy,
2385 MDIO_PMA_DEVAD, 2312 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
2386 MDIO_PMA_REG_GEN_CTRL,
2387 0x018B);
2388 2313
2389 /* Set soft reset */ 2314 /* Set soft reset */
2390 bnx2x_cl45_write(bp, phy, 2315 bnx2x_cl45_write(bp, phy,
@@ -2614,10 +2539,11 @@ static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
2614 *edc_mode = EDC_MODE_LIMITING; 2539 *edc_mode = EDC_MODE_LIMITING;
2615 2540
2616 /* First check for copper cable */ 2541 /* First check for copper cable */
2617 if (bnx2x_read_sfp_module_eeprom(phy, params, 2542 if (bnx2x_read_sfp_module_eeprom(phy,
2618 SFP_EEPROM_CON_TYPE_ADDR, 2543 params,
2619 1, 2544 SFP_EEPROM_CON_TYPE_ADDR,
2620 &val) != 0) { 2545 1,
2546 &val) != 0) {
2621 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n"); 2547 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
2622 return -EINVAL; 2548 return -EINVAL;
2623 } 2549 }
@@ -2629,7 +2555,8 @@ static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
2629 2555
2630 /* Check if its active cable( includes SFP+ module) 2556 /* Check if its active cable( includes SFP+ module)
2631 of passive cable*/ 2557 of passive cable*/
2632 if (bnx2x_read_sfp_module_eeprom(phy, params, 2558 if (bnx2x_read_sfp_module_eeprom(phy,
2559 params,
2633 SFP_EEPROM_FC_TX_TECH_ADDR, 2560 SFP_EEPROM_FC_TX_TECH_ADDR,
2634 1, 2561 1,
2635 &copper_module_type) != 2562 &copper_module_type) !=
@@ -2669,10 +2596,11 @@ static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
2669 2596
2670 if (check_limiting_mode) { 2597 if (check_limiting_mode) {
2671 u8 options[SFP_EEPROM_OPTIONS_SIZE]; 2598 u8 options[SFP_EEPROM_OPTIONS_SIZE];
2672 if (bnx2x_read_sfp_module_eeprom(phy, params, 2599 if (bnx2x_read_sfp_module_eeprom(phy,
2673 SFP_EEPROM_OPTIONS_ADDR, 2600 params,
2674 SFP_EEPROM_OPTIONS_SIZE, 2601 SFP_EEPROM_OPTIONS_ADDR,
2675 options) != 0) { 2602 SFP_EEPROM_OPTIONS_SIZE,
2603 options) != 0) {
2676 DP(NETIF_MSG_LINK, "Failed to read Option" 2604 DP(NETIF_MSG_LINK, "Failed to read Option"
2677 " field from module EEPROM\n"); 2605 " field from module EEPROM\n");
2678 return -EINVAL; 2606 return -EINVAL;
@@ -2720,14 +2648,16 @@ static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
2720 } 2648 }
2721 2649
2722 /* format the warning message */ 2650 /* format the warning message */
2723 if (bnx2x_read_sfp_module_eeprom(phy, params, 2651 if (bnx2x_read_sfp_module_eeprom(phy,
2652 params,
2724 SFP_EEPROM_VENDOR_NAME_ADDR, 2653 SFP_EEPROM_VENDOR_NAME_ADDR,
2725 SFP_EEPROM_VENDOR_NAME_SIZE, 2654 SFP_EEPROM_VENDOR_NAME_SIZE,
2726 (u8 *)vendor_name)) 2655 (u8 *)vendor_name))
2727 vendor_name[0] = '\0'; 2656 vendor_name[0] = '\0';
2728 else 2657 else
2729 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 2658 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
2730 if (bnx2x_read_sfp_module_eeprom(phy, params, 2659 if (bnx2x_read_sfp_module_eeprom(phy,
2660 params,
2731 SFP_EEPROM_PART_NO_ADDR, 2661 SFP_EEPROM_PART_NO_ADDR,
2732 SFP_EEPROM_PART_NO_SIZE, 2662 SFP_EEPROM_PART_NO_SIZE,
2733 (u8 *)vendor_pn)) 2663 (u8 *)vendor_pn))
@@ -2743,7 +2673,7 @@ static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
2743 2673
2744static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp, 2674static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
2745 struct bnx2x_phy *phy, 2675 struct bnx2x_phy *phy,
2746 u16 edc_mode) 2676 u16 edc_mode)
2747{ 2677{
2748 u16 cur_limiting_mode; 2678 u16 cur_limiting_mode;
2749 2679
@@ -2758,9 +2688,9 @@ static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
2758 DP(NETIF_MSG_LINK, 2688 DP(NETIF_MSG_LINK,
2759 "Setting LIMITING MODE\n"); 2689 "Setting LIMITING MODE\n");
2760 bnx2x_cl45_write(bp, phy, 2690 bnx2x_cl45_write(bp, phy,
2761 MDIO_PMA_DEVAD, 2691 MDIO_PMA_DEVAD,
2762 MDIO_PMA_REG_ROM_VER2, 2692 MDIO_PMA_REG_ROM_VER2,
2763 EDC_MODE_LIMITING); 2693 EDC_MODE_LIMITING);
2764 } else { /* LRM mode ( default )*/ 2694 } else { /* LRM mode ( default )*/
2765 2695
2766 DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); 2696 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
@@ -2848,7 +2778,6 @@ static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
2848} 2778}
2849 2779
2850static void bnx2x_8727_power_module(struct bnx2x *bp, 2780static void bnx2x_8727_power_module(struct bnx2x *bp,
2851 struct link_params *params,
2852 struct bnx2x_phy *phy, 2781 struct bnx2x_phy *phy,
2853 u8 is_power_up) { 2782 u8 is_power_up) {
2854 /* Make sure GPIOs are not using for LED mode */ 2783 /* Make sure GPIOs are not using for LED mode */
@@ -2880,9 +2809,9 @@ static void bnx2x_8727_power_module(struct bnx2x *bp,
2880 val = ((!(is_power_up)) << 1); 2809 val = ((!(is_power_up)) << 1);
2881 2810
2882 bnx2x_cl45_write(bp, phy, 2811 bnx2x_cl45_write(bp, phy,
2883 MDIO_PMA_DEVAD, 2812 MDIO_PMA_DEVAD,
2884 MDIO_PMA_REG_8727_GPIO_CTRL, 2813 MDIO_PMA_REG_8727_GPIO_CTRL,
2885 val); 2814 val);
2886} 2815}
2887 2816
2888static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 2817static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
@@ -2916,7 +2845,7 @@ static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
2916 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) { 2845 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
2917 /* Shutdown SFP+ module */ 2846 /* Shutdown SFP+ module */
2918 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n"); 2847 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
2919 bnx2x_8727_power_module(bp, params, phy, 0); 2848 bnx2x_8727_power_module(bp, phy, 0);
2920 return rc; 2849 return rc;
2921 } 2850 }
2922 } else { 2851 } else {
@@ -2929,7 +2858,7 @@ static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
2929 2858
2930 /* power up the SFP module */ 2859 /* power up the SFP module */
2931 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) 2860 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
2932 bnx2x_8727_power_module(bp, params, phy, 1); 2861 bnx2x_8727_power_module(bp, phy, 1);
2933 2862
2934 /* Check and set limiting mode / LRM mode on 8726. 2863 /* Check and set limiting mode / LRM mode on 8726.
2935 On 8727 it is done automatically */ 2864 On 8727 it is done automatically */
@@ -2984,8 +2913,8 @@ void bnx2x_handle_module_detect_int(struct link_params *params)
2984 config)); 2913 config));
2985 2914
2986 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3, 2915 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
2987 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 2916 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
2988 port); 2917 port);
2989 /* Module was plugged out. */ 2918 /* Module was plugged out. */
2990 /* Disable transmit for this module */ 2919 /* Disable transmit for this module */
2991 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 2920 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
@@ -2998,21 +2927,13 @@ static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
2998{ 2927{
2999 /* Force KR or KX */ 2928 /* Force KR or KX */
3000 bnx2x_cl45_write(bp, phy, 2929 bnx2x_cl45_write(bp, phy,
3001 MDIO_PMA_DEVAD, 2930 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
3002 MDIO_PMA_REG_CTRL,
3003 0x2040);
3004 bnx2x_cl45_write(bp, phy, 2931 bnx2x_cl45_write(bp, phy,
3005 MDIO_PMA_DEVAD, 2932 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
3006 MDIO_PMA_REG_10G_CTRL2,
3007 0x000b);
3008 bnx2x_cl45_write(bp, phy, 2933 bnx2x_cl45_write(bp, phy,
3009 MDIO_PMA_DEVAD, 2934 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
3010 MDIO_PMA_REG_BCM_CTRL,
3011 0x0000);
3012 bnx2x_cl45_write(bp, phy, 2935 bnx2x_cl45_write(bp, phy,
3013 MDIO_AN_DEVAD, 2936 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
3014 MDIO_AN_REG_CTRL,
3015 0x0000);
3016} 2937}
3017 2938
3018static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp, 2939static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
@@ -3020,8 +2941,7 @@ static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
3020{ 2941{
3021 u16 val; 2942 u16 val;
3022 bnx2x_cl45_read(bp, phy, 2943 bnx2x_cl45_read(bp, phy,
3023 MDIO_PMA_DEVAD, 2944 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
3024 MDIO_PMA_REG_8073_CHIP_REV, &val);
3025 2945
3026 if (val == 0) { 2946 if (val == 0) {
3027 /* Mustn't set low power mode in 8073 A0 */ 2947 /* Mustn't set low power mode in 8073 A0 */
@@ -3030,47 +2950,32 @@ static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
3030 2950
3031 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */ 2951 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3032 bnx2x_cl45_read(bp, phy, 2952 bnx2x_cl45_read(bp, phy,
3033 MDIO_XS_DEVAD, 2953 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
3034 MDIO_XS_PLL_SEQUENCER, &val);
3035 val &= ~(1<<13); 2954 val &= ~(1<<13);
3036 bnx2x_cl45_write(bp, phy, 2955 bnx2x_cl45_write(bp, phy,
3037 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val); 2956 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3038 2957
3039 /* PLL controls */ 2958 /* PLL controls */
3040 bnx2x_cl45_write(bp, phy, 2959 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805E, 0x1077);
3041 MDIO_XS_DEVAD, 0x805E, 0x1077); 2960 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805D, 0x0000);
3042 bnx2x_cl45_write(bp, phy, 2961 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805C, 0x030B);
3043 MDIO_XS_DEVAD, 0x805D, 0x0000); 2962 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805B, 0x1240);
3044 bnx2x_cl45_write(bp, phy, 2963 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805A, 0x2490);
3045 MDIO_XS_DEVAD, 0x805C, 0x030B);
3046 bnx2x_cl45_write(bp, phy,
3047 MDIO_XS_DEVAD, 0x805B, 0x1240);
3048 bnx2x_cl45_write(bp, phy,
3049 MDIO_XS_DEVAD, 0x805A, 0x2490);
3050 2964
3051 /* Tx Controls */ 2965 /* Tx Controls */
3052 bnx2x_cl45_write(bp, phy, 2966 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3053 MDIO_XS_DEVAD, 0x80A7, 0x0C74); 2967 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A6, 0x9041);
3054 bnx2x_cl45_write(bp, phy, 2968 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A5, 0x4640);
3055 MDIO_XS_DEVAD, 0x80A6, 0x9041);
3056 bnx2x_cl45_write(bp, phy,
3057 MDIO_XS_DEVAD, 0x80A5, 0x4640);
3058 2969
3059 /* Rx Controls */ 2970 /* Rx Controls */
3060 bnx2x_cl45_write(bp, phy, 2971 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3061 MDIO_XS_DEVAD, 0x80FE, 0x01C4); 2972 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FD, 0x9249);
3062 bnx2x_cl45_write(bp, phy, 2973 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FC, 0x2015);
3063 MDIO_XS_DEVAD, 0x80FD, 0x9249);
3064 bnx2x_cl45_write(bp, phy,
3065 MDIO_XS_DEVAD, 0x80FC, 0x2015);
3066 2974
3067 /* Enable PLL sequencer (use read-modify-write to set bit 13) */ 2975 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3068 bnx2x_cl45_read(bp, phy, 2976 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
3069 MDIO_XS_DEVAD,
3070 MDIO_XS_PLL_SEQUENCER, &val);
3071 val |= (1<<13); 2977 val |= (1<<13);
3072 bnx2x_cl45_write(bp, phy, 2978 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3073 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3074} 2979}
3075 2980
3076static void bnx2x_8073_set_pause_cl37(struct link_params *params, 2981static void bnx2x_8073_set_pause_cl37(struct link_params *params,
@@ -3080,8 +2985,7 @@ static void bnx2x_8073_set_pause_cl37(struct link_params *params,
3080 u16 cl37_val; 2985 u16 cl37_val;
3081 struct bnx2x *bp = params->bp; 2986 struct bnx2x *bp = params->bp;
3082 bnx2x_cl45_read(bp, phy, 2987 bnx2x_cl45_read(bp, phy,
3083 MDIO_AN_DEVAD, 2988 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
3084 MDIO_AN_REG_CL37_FC_LD, &cl37_val);
3085 2989
3086 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 2990 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3087 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 2991 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
@@ -3105,8 +3009,7 @@ static void bnx2x_8073_set_pause_cl37(struct link_params *params,
3105 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 3009 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
3106 3010
3107 bnx2x_cl45_write(bp, phy, 3011 bnx2x_cl45_write(bp, phy,
3108 MDIO_AN_DEVAD, 3012 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
3109 MDIO_AN_REG_CL37_FC_LD, cl37_val);
3110 msleep(500); 3013 msleep(500);
3111} 3014}
3112 3015
@@ -3117,9 +3020,7 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
3117 u16 val; 3020 u16 val;
3118 struct bnx2x *bp = params->bp; 3021 struct bnx2x *bp = params->bp;
3119 /* read modify write pause advertizing */ 3022 /* read modify write pause advertizing */
3120 bnx2x_cl45_read(bp, phy, 3023 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3121 MDIO_AN_DEVAD,
3122 MDIO_AN_REG_ADV_PAUSE, &val);
3123 3024
3124 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 3025 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3125 3026
@@ -3133,14 +3034,10 @@ static void bnx2x_ext_phy_set_pause(struct link_params *params,
3133 if ((vars->ieee_fc & 3034 if ((vars->ieee_fc &
3134 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 3035 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3135 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 3036 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3136 val |= 3037 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3137 MDIO_AN_REG_ADV_PAUSE_PAUSE;
3138 } 3038 }
3139 DP(NETIF_MSG_LINK, 3039 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3140 "Ext phy AN advertize 0x%x\n", val); 3040 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3141 bnx2x_cl45_write(bp, phy,
3142 MDIO_AN_DEVAD,
3143 MDIO_AN_REG_ADV_PAUSE, val);
3144} 3041}
3145 3042
3146static void bnx2x_set_preemphasis(struct bnx2x_phy *phy, 3043static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
@@ -3153,16 +3050,16 @@ static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
3153 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 3050 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
3154 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 3051 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
3155 CL45_WR_OVER_CL22(bp, phy, 3052 CL45_WR_OVER_CL22(bp, phy,
3156 bank, 3053 bank,
3157 MDIO_RX0_RX_EQ_BOOST, 3054 MDIO_RX0_RX_EQ_BOOST,
3158 phy->rx_preemphasis[i]); 3055 phy->rx_preemphasis[i]);
3159 } 3056 }
3160 3057
3161 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 3058 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
3162 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 3059 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
3163 CL45_WR_OVER_CL22(bp, phy, 3060 CL45_WR_OVER_CL22(bp, phy,
3164 bank, 3061 bank,
3165 MDIO_TX0_TX_DRIVER, 3062 MDIO_TX0_TX_DRIVER,
3166 phy->tx_preemphasis[i]); 3063 phy->tx_preemphasis[i]);
3167 } 3064 }
3168} 3065}
@@ -3257,18 +3154,16 @@ static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
3257 struct bnx2x_phy *phy) 3154 struct bnx2x_phy *phy)
3258{ 3155{
3259 u16 cnt, ctrl; 3156 u16 cnt, ctrl;
3260 /* Wait for soft reset to get cleared upto 1 sec */ 3157 /* Wait for soft reset to get cleared upto 1 sec */
3261 for (cnt = 0; cnt < 1000; cnt++) { 3158 for (cnt = 0; cnt < 1000; cnt++) {
3262 bnx2x_cl45_read(bp, phy, 3159 bnx2x_cl45_read(bp, phy,
3263 MDIO_PMA_DEVAD, 3160 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
3264 MDIO_PMA_REG_CTRL, &ctrl); 3161 if (!(ctrl & (1<<15)))
3265 if (!(ctrl & (1<<15))) 3162 break;
3266 break; 3163 msleep(1);
3267 msleep(1); 3164 }
3268 } 3165 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
3269 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", 3166 return cnt;
3270 ctrl, cnt);
3271 return 0;
3272} 3167}
3273 3168
3274static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy, 3169static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
@@ -3284,29 +3179,18 @@ static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
3284 bnx2x_ext_phy_hw_reset(bp, params->port); 3179 bnx2x_ext_phy_hw_reset(bp, params->port);
3285 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 3180 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
3286 bnx2x_wait_reset_complete(bp, phy); 3181 bnx2x_wait_reset_complete(bp, phy);
3287 DP(NETIF_MSG_LINK, "XGXS 8705\n");
3288
3289 bnx2x_cl45_write(bp, phy,
3290 MDIO_PMA_DEVAD,
3291 MDIO_PMA_REG_MISC_CTRL,
3292 0x8288);
3293 bnx2x_cl45_write(bp, phy,
3294 MDIO_PMA_DEVAD,
3295 MDIO_PMA_REG_PHY_IDENTIFIER,
3296 0x7fbf);
3297 bnx2x_cl45_write(bp, phy,
3298 MDIO_PMA_DEVAD,
3299 MDIO_PMA_REG_CMU_PLL_BYPASS,
3300 0x0100);
3301 bnx2x_cl45_write(bp, phy,
3302 MDIO_WIS_DEVAD,
3303 MDIO_WIS_REG_LASI_CNTL, 0x1);
3304 3182
3305 /* BCM8705 doesn't have microcode, hence the 0 */ 3183 bnx2x_cl45_write(bp, phy,
3306 bnx2x_save_spirom_version(bp, params->port, 3184 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
3307 params->shmem_base, 0); 3185 bnx2x_cl45_write(bp, phy,
3308 3186 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
3309 return 0; 3187 bnx2x_cl45_write(bp, phy,
3188 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
3189 bnx2x_cl45_write(bp, phy,
3190 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
3191 /* BCM8705 doesn't have microcode, hence the 0 */
3192 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
3193 return 0;
3310} 3194}
3311 3195
3312static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy, 3196static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
@@ -3322,95 +3206,73 @@ static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
3322 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 3206 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
3323 3207
3324 bnx2x_wait_reset_complete(bp, phy); 3208 bnx2x_wait_reset_complete(bp, phy);
3325 /* Wait until fw is loaded */
3326 for (cnt = 0; cnt < 100; cnt++) {
3327 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3328 MDIO_PMA_REG_ROM_VER1, &val);
3329 if (val)
3330 break;
3331 msleep(10);
3332 }
3333 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized "
3334 "after %d ms\n", cnt);
3335 if ((params->feature_config_flags &
3336 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3337 u8 i;
3338 u16 reg;
3339 for (i = 0; i < 4; i++) {
3340 reg = MDIO_XS_8706_REG_BANK_RX0 +
3341 i*(MDIO_XS_8706_REG_BANK_RX1 -
3342 MDIO_XS_8706_REG_BANK_RX0);
3343 bnx2x_cl45_read(bp, phy,
3344 MDIO_XS_DEVAD,
3345 reg, &val);
3346 /* Clear first 3 bits of the control */
3347 val &= ~0x7;
3348 /* Set control bits according to
3349 configuation */
3350 val |= (phy->rx_preemphasis[i] &
3351 0x7);
3352 DP(NETIF_MSG_LINK, "Setting RX"
3353 "Equalizer to BCM8706 reg 0x%x"
3354 " <-- val 0x%x\n", reg, val);
3355 bnx2x_cl45_write(bp, phy,
3356 MDIO_XS_DEVAD,
3357 reg, val);
3358 }
3359 }
3360 /* Force speed */
3361 if (params->req_line_speed == SPEED_10000) {
3362 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3363
3364 bnx2x_cl45_write(bp, phy,
3365 MDIO_PMA_DEVAD,
3366 MDIO_PMA_REG_DIGITAL_CTRL,
3367 0x400);
3368 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3369 MDIO_PMA_REG_LASI_CTRL, 1);
3370 } else {
3371 /* Force 1Gbps using autoneg with 1G
3372 advertisment */
3373
3374 /* Allow CL37 through CL73 */
3375 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3376 bnx2x_cl45_write(bp, phy,
3377 MDIO_AN_DEVAD,
3378 MDIO_AN_REG_CL37_CL73,
3379 0x040c);
3380
3381 /* Enable Full-Duplex advertisment on CL37 */
3382 bnx2x_cl45_write(bp, phy,
3383 MDIO_AN_DEVAD,
3384 MDIO_AN_REG_CL37_FC_LP,
3385 0x0020);
3386 /* Enable CL37 AN */
3387 bnx2x_cl45_write(bp, phy,
3388 MDIO_AN_DEVAD,
3389 MDIO_AN_REG_CL37_AN,
3390 0x1000);
3391 /* 1G support */
3392 bnx2x_cl45_write(bp, phy,
3393 MDIO_AN_DEVAD,
3394 MDIO_AN_REG_ADV, (1<<5));
3395
3396 /* Enable clause 73 AN */
3397 bnx2x_cl45_write(bp, phy,
3398 MDIO_AN_DEVAD,
3399 MDIO_AN_REG_CTRL,
3400 0x1200);
3401 bnx2x_cl45_write(bp, phy,
3402 MDIO_PMA_DEVAD,
3403 MDIO_PMA_REG_RX_ALARM_CTRL,
3404 0x0400);
3405 bnx2x_cl45_write(bp, phy,
3406 MDIO_PMA_DEVAD,
3407 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3408 3209
3409 } 3210 /* Wait until fw is loaded */
3410 bnx2x_save_bcm_spirom_ver(bp, params->port, 3211 for (cnt = 0; cnt < 100; cnt++) {
3411 phy, 3212 bnx2x_cl45_read(bp, phy,
3412 params->shmem_base); 3213 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
3413 return 0; 3214 if (val)
3215 break;
3216 msleep(10);
3217 }
3218 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
3219 if ((params->feature_config_flags &
3220 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3221 u8 i;
3222 u16 reg;
3223 for (i = 0; i < 4; i++) {
3224 reg = MDIO_XS_8706_REG_BANK_RX0 +
3225 i*(MDIO_XS_8706_REG_BANK_RX1 -
3226 MDIO_XS_8706_REG_BANK_RX0);
3227 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
3228 /* Clear first 3 bits of the control */
3229 val &= ~0x7;
3230 /* Set control bits according to configuration */
3231 val |= (phy->rx_preemphasis[i] & 0x7);
3232 DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
3233 " reg 0x%x <-- val 0x%x\n", reg, val);
3234 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
3235 }
3236 }
3237 /* Force speed */
3238 if (phy->req_line_speed == SPEED_10000) {
3239 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3240
3241 bnx2x_cl45_write(bp, phy,
3242 MDIO_PMA_DEVAD,
3243 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
3244 bnx2x_cl45_write(bp, phy,
3245 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
3246 } else {
3247 /* Force 1Gbps using autoneg with 1G advertisment */
3248
3249 /* Allow CL37 through CL73 */
3250 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3251 bnx2x_cl45_write(bp, phy,
3252 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
3253
3254 /* Enable Full-Duplex advertisment on CL37 */
3255 bnx2x_cl45_write(bp, phy,
3256 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
3257 /* Enable CL37 AN */
3258 bnx2x_cl45_write(bp, phy,
3259 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
3260 /* 1G support */
3261 bnx2x_cl45_write(bp, phy,
3262 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
3263
3264 /* Enable clause 73 AN */
3265 bnx2x_cl45_write(bp, phy,
3266 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
3267 bnx2x_cl45_write(bp, phy,
3268 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
3269 0x0400);
3270 bnx2x_cl45_write(bp, phy,
3271 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
3272 0x0004);
3273 }
3274 bnx2x_save_bcm_spirom_ver(bp, params->port, phy, params->shmem_base);
3275 return 0;
3414} 3276}
3415 3277
3416static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy, 3278static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
@@ -3429,86 +3291,85 @@ static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
3429 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 3291 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
3430 bnx2x_wait_reset_complete(bp, phy); 3292 bnx2x_wait_reset_complete(bp, phy);
3431 3293
3432 bnx2x_wait_reset_complete(bp, phy); 3294 bnx2x_8726_external_rom_boot(phy, params);
3433 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
3434 bnx2x_8726_external_rom_boot(phy, params);
3435
3436 /* Need to call module detected on initialization since
3437 the module detection triggered by actual module
3438 insertion might occur before driver is loaded, and when
3439 driver is loaded, it reset all registers, including the
3440 transmitter */
3441 bnx2x_sfp_module_detection(phy, params);
3442 3295
3443 /* Set Flow control */ 3296 /* Need to call module detected on initialization since
3444 bnx2x_ext_phy_set_pause(params, phy, vars); 3297 the module detection triggered by actual module
3445 if (params->req_line_speed == SPEED_1000) { 3298 insertion might occur before driver is loaded, and when
3446 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 3299 driver is loaded, it reset all registers, including the
3447 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3300 transmitter */
3448 MDIO_PMA_REG_CTRL, 0x40); 3301 bnx2x_sfp_module_detection(phy, params);
3449 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3302
3450 MDIO_PMA_REG_10G_CTRL2, 0xD); 3303 if (phy->req_line_speed == SPEED_1000) {
3451 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3304 DP(NETIF_MSG_LINK, "Setting 1G force\n");
3452 MDIO_PMA_REG_LASI_CTRL, 0x5); 3305 bnx2x_cl45_write(bp, phy,
3453 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3306 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
3454 MDIO_PMA_REG_RX_ALARM_CTRL, 3307 bnx2x_cl45_write(bp, phy,
3455 0x400); 3308 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
3456 } else if ((params->req_line_speed == 3309 bnx2x_cl45_write(bp, phy,
3457 SPEED_AUTO_NEG) && 3310 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
3458 ((params->speed_cap_mask & 3311 bnx2x_cl45_write(bp, phy,
3459 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) { 3312 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
3460 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 3313 0x400);
3461 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3314 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
3462 MDIO_AN_REG_ADV, 0x20); 3315 (phy->speed_cap_mask &
3463 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3316 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
3464 MDIO_AN_REG_CL37_CL73, 0x040c); 3317 ((phy->speed_cap_mask &
3465 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3318 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
3466 MDIO_AN_REG_CL37_FC_LD, 0x0020); 3319 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
3467 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3320 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
3468 MDIO_AN_REG_CL37_AN, 0x1000); 3321 /* Set Flow control */
3469 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3322 bnx2x_ext_phy_set_pause(params, phy, vars);
3470 MDIO_AN_REG_CTRL, 0x1200); 3323 bnx2x_cl45_write(bp, phy,
3471 3324 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
3472 /* Enable RX-ALARM control to receive 3325 bnx2x_cl45_write(bp, phy,
3473 interrupt for 1G speed change */ 3326 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
3474 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3327 bnx2x_cl45_write(bp, phy,
3475 MDIO_PMA_REG_LASI_CTRL, 0x4); 3328 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
3476 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3329 bnx2x_cl45_write(bp, phy,
3477 MDIO_PMA_REG_RX_ALARM_CTRL, 3330 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
3478 0x400); 3331 bnx2x_cl45_write(bp, phy,
3479 3332 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
3480 } else { /* Default 10G. Set only LASI control */ 3333 /* Enable RX-ALARM control to receive
3481 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3334 interrupt for 1G speed change */
3482 MDIO_PMA_REG_LASI_CTRL, 1); 3335 bnx2x_cl45_write(bp, phy,
3483 } 3336 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
3337 bnx2x_cl45_write(bp, phy,
3338 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
3339 0x400);
3340
3341 } else { /* Default 10G. Set only LASI control */
3342 bnx2x_cl45_write(bp, phy,
3343 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
3344 }
3484 3345
3485 /* Set TX PreEmphasis if needed */ 3346 /* Set TX PreEmphasis if needed */
3486 if ((params->feature_config_flags & 3347 if ((params->feature_config_flags &
3487 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 3348 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3488 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x," 3349 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
3489 "TX_CTRL2 0x%x\n", 3350 "TX_CTRL2 0x%x\n",
3490 phy->tx_preemphasis[0], 3351 phy->tx_preemphasis[0],
3491 phy->tx_preemphasis[1]); 3352 phy->tx_preemphasis[1]);
3492 bnx2x_cl45_write(bp, phy, 3353 bnx2x_cl45_write(bp, phy,
3493 MDIO_PMA_DEVAD, 3354 MDIO_PMA_DEVAD,
3494 MDIO_PMA_REG_8726_TX_CTRL1, 3355 MDIO_PMA_REG_8726_TX_CTRL1,
3495 phy->tx_preemphasis[0]); 3356 phy->tx_preemphasis[0]);
3496 3357
3497 bnx2x_cl45_write(bp, phy, 3358 bnx2x_cl45_write(bp, phy,
3498 MDIO_PMA_DEVAD, 3359 MDIO_PMA_DEVAD,
3499 MDIO_PMA_REG_8726_TX_CTRL2, 3360 MDIO_PMA_REG_8726_TX_CTRL2,
3500 phy->tx_preemphasis[1]); 3361 phy->tx_preemphasis[1]);
3501 } 3362 }
3502 return 0; 3363 return 0;
3503 3364
3504} 3365}
3505 3366
3506static u8 bnx2x_8072_8073_config_init(struct bnx2x_phy *phy, 3367static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
3507 struct link_params *params, 3368 struct link_params *params,
3508 struct link_vars *vars) 3369 struct link_vars *vars)
3509{ 3370{
3510 struct bnx2x *bp = params->bp; 3371 struct bnx2x *bp = params->bp;
3511 u16 val = 0; 3372 u16 val = 0, tmp1;
3512 u8 gpio_port; 3373 u8 gpio_port;
3513 DP(NETIF_MSG_LINK, "Init 8073\n"); 3374 DP(NETIF_MSG_LINK, "Init 8073\n");
3514 3375
@@ -3520,183 +3381,117 @@ static u8 bnx2x_8072_8073_config_init(struct bnx2x_phy *phy,
3520 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, 3381 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3521 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 3382 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
3522 3383
3523 { 3384 /* enable LASI */
3524 u16 tmp1; 3385 bnx2x_cl45_write(bp, phy,
3525 u16 rx_alarm_ctrl_val; 3386 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
3526 u16 lasi_ctrl_val; 3387 bnx2x_cl45_write(bp, phy,
3527 if (phy->type == 3388 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x0004);
3528 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
3529 rx_alarm_ctrl_val = 0x400;
3530 lasi_ctrl_val = 0x0004;
3531 } else {
3532 rx_alarm_ctrl_val = (1<<2);
3533 lasi_ctrl_val = 0x0004;
3534 }
3535
3536 /* enable LASI */
3537 bnx2x_cl45_write(bp, phy,
3538 MDIO_PMA_DEVAD,
3539 MDIO_PMA_REG_RX_ALARM_CTRL,
3540 rx_alarm_ctrl_val);
3541
3542 bnx2x_cl45_write(bp, phy,
3543 MDIO_PMA_DEVAD,
3544 MDIO_PMA_REG_LASI_CTRL,
3545 lasi_ctrl_val);
3546
3547 bnx2x_8073_set_pause_cl37(params, phy, vars);
3548 3389
3549 if (phy->type == 3390 bnx2x_8073_set_pause_cl37(params, phy, vars);
3550 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072)
3551 bnx2x_bcm8072_external_rom_boot(phy, params);
3552 else
3553 /* In case of 8073 with long xaui lines,
3554 don't set the 8073 xaui low power*/
3555 bnx2x_8073_set_xaui_low_power_mode(bp, phy);
3556 3391
3557 bnx2x_cl45_read(bp, phy, 3392 bnx2x_8073_set_xaui_low_power_mode(bp, phy);
3558 MDIO_PMA_DEVAD,
3559 MDIO_PMA_REG_M8051_MSGOUT_REG,
3560 &tmp1);
3561 3393
3562 bnx2x_cl45_read(bp, phy, 3394 bnx2x_cl45_read(bp, phy,
3563 MDIO_PMA_DEVAD, 3395 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
3564 MDIO_PMA_REG_RX_ALARM, &tmp1);
3565 3396
3566 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1):" 3397 bnx2x_cl45_read(bp, phy,
3567 "0x%x\n", tmp1); 3398 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
3568 3399
3569 /* If this is forced speed, set to KR or KX 3400 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
3570 * (all other are not supported)
3571 */
3572 if (params->loopback_mode == LOOPBACK_EXT) {
3573 bnx2x_807x_force_10G(bp, phy);
3574 DP(NETIF_MSG_LINK,
3575 "Forced speed 10G on 807X\n");
3576 return 0;
3577 } else {
3578 bnx2x_cl45_write(bp, phy,
3579 MDIO_PMA_DEVAD,
3580 MDIO_PMA_REG_BCM_CTRL,
3581 0x0002);
3582 }
3583 if (params->req_line_speed != SPEED_AUTO_NEG) {
3584 if (params->req_line_speed == SPEED_10000) {
3585 val = (1<<7);
3586 } else if (params->req_line_speed ==
3587 SPEED_2500) {
3588 val = (1<<5);
3589 /* Note that 2.5G works only
3590 when used with 1G advertisment */
3591 } else
3592 val = (1<<5);
3593 } else {
3594 3401
3595 val = 0; 3402 /* Enable CL37 BAM */
3596 if (params->speed_cap_mask & 3403 bnx2x_cl45_read(bp, phy,
3597 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 3404 MDIO_AN_DEVAD,
3598 val |= (1<<7); 3405 MDIO_AN_REG_8073_BAM, &val);
3599 3406 bnx2x_cl45_write(bp, phy,
3600 /* Note that 2.5G works only when 3407 MDIO_AN_DEVAD,
3601 used with 1G advertisment */ 3408 MDIO_AN_REG_8073_BAM, val | 1);
3602 if (params->speed_cap_mask &
3603 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
3604 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
3605 val |= (1<<5);
3606 DP(NETIF_MSG_LINK,
3607 "807x autoneg val = 0x%x\n", val);
3608 }
3609 3409
3610 bnx2x_cl45_write(bp, phy, 3410 if (params->loopback_mode == LOOPBACK_EXT) {
3611 MDIO_AN_DEVAD, 3411 bnx2x_807x_force_10G(bp, phy);
3612 MDIO_AN_REG_ADV, val); 3412 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
3413 return 0;
3414 } else {
3415 bnx2x_cl45_write(bp, phy,
3416 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
3417 }
3418 if (phy->req_line_speed != SPEED_AUTO_NEG) {
3419 if (phy->req_line_speed == SPEED_10000) {
3420 val = (1<<7);
3421 } else if (phy->req_line_speed == SPEED_2500) {
3422 val = (1<<5);
3423 /* Note that 2.5G works only
3424 when used with 1G advertisment */
3425 } else
3426 val = (1<<5);
3427 } else {
3428 val = 0;
3429 if (phy->speed_cap_mask &
3430 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
3431 val |= (1<<7);
3432
3433 /* Note that 2.5G works only when
3434 used with 1G advertisment */
3435 if (phy->speed_cap_mask &
3436 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
3437 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
3438 val |= (1<<5);
3439 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
3440 }
3613 3441
3614 bnx2x_cl45_read(bp, phy, 3442 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
3615 MDIO_AN_DEVAD, 3443 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
3616 MDIO_AN_REG_8073_2_5G, &tmp1);
3617
3618 if (((params->speed_cap_mask &
3619 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
3620 (params->req_line_speed ==
3621 SPEED_AUTO_NEG)) ||
3622 (params->req_line_speed ==
3623 SPEED_2500)) {
3624 u16 phy_ver;
3625 /* Allow 2.5G for A1 and above */
3626 bnx2x_cl45_read(bp, phy,
3627 MDIO_PMA_DEVAD,
3628 MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
3629 DP(NETIF_MSG_LINK, "Add 2.5G\n");
3630 if (phy_ver > 0)
3631 tmp1 |= 1;
3632 else
3633 tmp1 &= 0xfffe;
3634 } else {
3635 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
3636 tmp1 &= 0xfffe;
3637 }
3638
3639 bnx2x_cl45_write(bp, phy,
3640 MDIO_AN_DEVAD,
3641 MDIO_AN_REG_8073_2_5G, tmp1);
3642
3643 /* Add support for CL37 (passive mode) II */
3644 3444
3645 bnx2x_cl45_read(bp, phy, 3445 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
3646 MDIO_AN_DEVAD, 3446 (phy->req_line_speed == SPEED_AUTO_NEG)) ||
3647 MDIO_AN_REG_CL37_FC_LD, 3447 (phy->req_line_speed == SPEED_2500)) {
3648 &tmp1); 3448 u16 phy_ver;
3449 /* Allow 2.5G for A1 and above */
3450 bnx2x_cl45_read(bp, phy,
3451 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
3452 &phy_ver);
3453 DP(NETIF_MSG_LINK, "Add 2.5G\n");
3454 if (phy_ver > 0)
3455 tmp1 |= 1;
3456 else
3457 tmp1 &= 0xfffe;
3458 } else {
3459 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
3460 tmp1 &= 0xfffe;
3461 }
3649 3462
3650 bnx2x_cl45_write(bp, phy, 3463 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
3651 MDIO_AN_DEVAD, 3464 /* Add support for CL37 (passive mode) II */
3652 MDIO_AN_REG_CL37_FC_LD, (tmp1 |
3653 ((params->req_duplex == DUPLEX_FULL) ?
3654 0x20 : 0x40)));
3655 3465
3656 /* Add support for CL37 (passive mode) III */ 3466 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
3657 bnx2x_cl45_write(bp, phy, 3467 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
3658 MDIO_AN_DEVAD, 3468 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
3659 MDIO_AN_REG_CL37_AN, 0x1000); 3469 0x20 : 0x40)));
3660
3661 if (phy->type ==
3662 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
3663 /* The SNR will improve about 2db by changing
3664 BW and FEE main tap. Rest commands are executed
3665 after link is up*/
3666 /*Change FFE main cursor to 5 in EDC register*/
3667 if (bnx2x_8073_is_snr_needed(bp, phy))
3668 bnx2x_cl45_write(bp, phy,
3669 MDIO_PMA_DEVAD,
3670 MDIO_PMA_REG_EDC_FFE_MAIN,
3671 0xFB0C);
3672
3673 /* Enable FEC (Forware Error Correction)
3674 Request in the AN */
3675 bnx2x_cl45_read(bp, phy,
3676 MDIO_AN_DEVAD,
3677 MDIO_AN_REG_ADV2, &tmp1);
3678 3470
3679 tmp1 |= (1<<15); 3471 /* Add support for CL37 (passive mode) III */
3472 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
3680 3473
3681 bnx2x_cl45_write(bp, phy, 3474 /* The SNR will improve about 2db by changing
3682 MDIO_AN_DEVAD, 3475 BW and FEE main tap. Rest commands are executed
3683 MDIO_AN_REG_ADV2, tmp1); 3476 after link is up*/
3477 if (bnx2x_8073_is_snr_needed(bp, phy))
3478 bnx2x_cl45_write(bp, phy,
3479 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
3480 0xFB0C);
3684 3481
3685 } 3482 /* Enable FEC (Forware Error Correction) Request in the AN */
3483 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
3484 tmp1 |= (1<<15);
3485 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
3686 3486
3687 bnx2x_ext_phy_set_pause(params, phy, vars); 3487 bnx2x_ext_phy_set_pause(params, phy, vars);
3688 3488
3689 /* Restart autoneg */ 3489 /* Restart autoneg */
3690 msleep(500); 3490 msleep(500);
3691 bnx2x_cl45_write(bp, phy, 3491 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
3692 MDIO_AN_DEVAD, 3492 DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
3693 MDIO_AN_REG_CTRL, 0x1200); 3493 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
3694 DP(NETIF_MSG_LINK, "807x Autoneg Restart: " 3494 return 0;
3695 "Advertise 1G=%x, 10G=%x\n",
3696 ((val & (1<<5)) > 0),
3697 ((val & (1<<7)) > 0));
3698 return 0;
3699 }
3700} 3495}
3701 3496
3702static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy, 3497static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
@@ -3709,143 +3504,120 @@ static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
3709 struct bnx2x *bp = params->bp; 3504 struct bnx2x *bp = params->bp;
3710 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 3505 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
3711 3506
3712 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 3507 bnx2x_wait_reset_complete(bp, phy);
3508 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
3509 lasi_ctrl_val = 0x0004;
3713 3510
3714 rx_alarm_ctrl_val = (1<<2) | (1<<5) ; 3511 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
3715 lasi_ctrl_val = 0x0004; 3512 /* enable LASI */
3716 bnx2x_wait_reset_complete(bp, phy); 3513 bnx2x_cl45_write(bp, phy,
3717 DP(NETIF_MSG_LINK, "Initializing BCM8727\n"); 3514 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
3718 /* enable LASI */ 3515 rx_alarm_ctrl_val);
3719 bnx2x_cl45_write(bp, phy,
3720 MDIO_PMA_DEVAD,
3721 MDIO_PMA_REG_RX_ALARM_CTRL,
3722 rx_alarm_ctrl_val);
3723 3516
3724 bnx2x_cl45_write(bp, phy, 3517 bnx2x_cl45_write(bp, phy,
3725 MDIO_PMA_DEVAD, 3518 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
3726 MDIO_PMA_REG_LASI_CTRL,
3727 lasi_ctrl_val);
3728 3519
3729 /* Initially configure MOD_ABS to interrupt when 3520 /* Initially configure MOD_ABS to interrupt when
3730 module is presence( bit 8) */ 3521 module is presence( bit 8) */
3731 bnx2x_cl45_read(bp, phy, 3522 bnx2x_cl45_read(bp, phy,
3732 MDIO_PMA_DEVAD, 3523 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
3733 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 3524 /* Set EDC off by setting OPTXLOS signal input to low
3734 /* Set EDC off by setting OPTXLOS signal input to low 3525 (bit 9).
3735 (bit 9). 3526 When the EDC is off it locks onto a reference clock and
3736 When the EDC is off it locks onto a reference clock and 3527 avoids becoming 'lost'.*/
3737 avoids becoming 'lost'.*/ 3528 mod_abs &= ~((1<<8) | (1<<9));
3738 mod_abs &= ~((1<<8) | (1<<9)); 3529 bnx2x_cl45_write(bp, phy,
3739 bnx2x_cl45_write(bp, phy, 3530 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
3740 MDIO_PMA_DEVAD,
3741 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
3742 3531
3743 /* Make MOD_ABS give interrupt on change */
3744 bnx2x_cl45_read(bp, phy,
3745 MDIO_PMA_DEVAD,
3746 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
3747 &val);
3748 val |= (1<<12);
3749 bnx2x_cl45_write(bp, phy,
3750 MDIO_PMA_DEVAD,
3751 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
3752 val);
3753 3532
3754 /* Set 8727 GPIOs to input to allow reading from the 3533 /* Make MOD_ABS give interrupt on change */
3755 8727 GPIO0 status which reflect SFP+ module 3534 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
3756 over-current */ 3535 &val);
3536 val |= (1<<12);
3537 bnx2x_cl45_write(bp, phy,
3538 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
3539 /* Set 8727 GPIOs to input to allow reading from the
3540 8727 GPIO0 status which reflect SFP+ module
3541 over-current */
3542
3543 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
3544 &val);
3545 val &= 0xff8f; /* Reset bits 4-6 */
3546 bnx2x_cl45_write(bp, phy,
3547 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
3757 3548
3758 bnx2x_cl45_read(bp, phy, 3549 bnx2x_8727_power_module(bp, phy, 1);
3759 MDIO_PMA_DEVAD,
3760 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
3761 &val);
3762 val &= 0xff8f; /* Reset bits 4-6 */
3763 bnx2x_cl45_write(bp, phy,
3764 MDIO_PMA_DEVAD,
3765 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
3766 val);
3767 3550
3768 bnx2x_8727_power_module(bp, params, phy, 1); 3551 bnx2x_cl45_read(bp, phy,
3552 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
3769 3553
3770 bnx2x_cl45_read(bp, phy, 3554 bnx2x_cl45_read(bp, phy,
3771 MDIO_PMA_DEVAD, 3555 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
3772 MDIO_PMA_REG_M8051_MSGOUT_REG,
3773 &tmp1);
3774 3556
3775 bnx2x_cl45_read(bp, phy, 3557 /* Set option 1G speed */
3776 MDIO_PMA_DEVAD, 3558 if (phy->req_line_speed == SPEED_1000) {
3777 MDIO_PMA_REG_RX_ALARM, &tmp1); 3559 DP(NETIF_MSG_LINK, "Setting 1G force\n");
3778 3560 bnx2x_cl45_write(bp, phy,
3779 /* Set option 1G speed */ 3561 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
3780 if (params->req_line_speed == SPEED_1000) { 3562 bnx2x_cl45_write(bp, phy,
3781 3563 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
3782 DP(NETIF_MSG_LINK, "Setting 1G force\n"); 3564 bnx2x_cl45_read(bp, phy,
3783 bnx2x_cl45_write(bp, phy, 3565 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
3784 MDIO_PMA_DEVAD, 3566 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
3785 MDIO_PMA_REG_CTRL, 0x40); 3567 } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
3786 bnx2x_cl45_write(bp, phy, 3568 ((phy->speed_cap_mask &
3787 MDIO_PMA_DEVAD, 3569 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
3788 MDIO_PMA_REG_10G_CTRL2, 0xD); 3570 ((phy->speed_cap_mask &
3789 bnx2x_cl45_read(bp, phy, 3571 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
3790 MDIO_PMA_DEVAD, 3572 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
3791 MDIO_PMA_REG_10G_CTRL2, &tmp1); 3573
3792 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); 3574 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
3793 3575 bnx2x_cl45_write(bp, phy,
3794 } else if ((params->req_line_speed == 3576 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
3795 SPEED_AUTO_NEG) && 3577 bnx2x_cl45_write(bp, phy,
3796 ((params->speed_cap_mask & 3578 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
3797 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 3579 } else {
3798 ((params->speed_cap_mask & 3580 /**
3799 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 3581 * Since the 8727 has only single reset pin, need to set the 10G
3800 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 3582 * registers although it is default
3801 DP(NETIF_MSG_LINK, "Setting 1G clause37\n"); 3583 */
3802 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3584 bnx2x_cl45_write(bp, phy,
3803 MDIO_AN_REG_8727_MISC_CTRL, 0); 3585 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
3804 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3586 0x0020);
3805 MDIO_AN_REG_CL37_AN, 0x1300); 3587 bnx2x_cl45_write(bp, phy,
3806 } else { 3588 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
3807 /* Since the 8727 has only single reset pin, 3589 bnx2x_cl45_write(bp, phy,
3808 need to set the 10G registers although it is 3590 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
3809 default */ 3591 bnx2x_cl45_write(bp, phy,
3810 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3592 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
3811 MDIO_AN_REG_8727_MISC_CTRL, 3593 0x0008);
3812 0x0020); 3594 }
3813 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3814 MDIO_AN_REG_CL37_AN, 0x0100);
3815 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3816 MDIO_PMA_REG_CTRL, 0x2040);
3817 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3818 MDIO_PMA_REG_10G_CTRL2, 0x0008);
3819 }
3820 3595
3821 /* Set 2-wire transfer rate of SFP+ module EEPROM 3596
3822 * to 100Khz since some DACs(direct attached cables) do 3597 /* Set 2-wire transfer rate of SFP+ module EEPROM
3823 * not work at 400Khz. 3598 * to 100Khz since some DACs(direct attached cables) do
3824 */ 3599 * not work at 400Khz.
3825 bnx2x_cl45_write(bp, phy, 3600 */
3826 MDIO_PMA_DEVAD, 3601 bnx2x_cl45_write(bp, phy,
3827 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 3602 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
3828 0xa001); 3603 0xa001);
3829 3604
3830 /* Set TX PreEmphasis if needed */ 3605 /* Set TX PreEmphasis if needed */
3831 if ((params->feature_config_flags & 3606 if ((params->feature_config_flags &
3832 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 3607 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3833 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x," 3608 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
3834 "TX_CTRL2 0x%x\n", 3609 phy->tx_preemphasis[0],
3835 phy->tx_preemphasis[0],
3836 phy->tx_preemphasis[1]); 3610 phy->tx_preemphasis[1]);
3837 bnx2x_cl45_write(bp, phy, 3611 bnx2x_cl45_write(bp, phy,
3838 MDIO_PMA_DEVAD, 3612 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
3839 MDIO_PMA_REG_8727_TX_CTRL1, 3613 phy->tx_preemphasis[0]);
3840 phy->tx_preemphasis[0]);
3841
3842 bnx2x_cl45_write(bp, phy,
3843 MDIO_PMA_DEVAD,
3844 MDIO_PMA_REG_8727_TX_CTRL2,
3845 phy->tx_preemphasis[1]);
3846 }
3847 3614
3848 return 0; 3615 bnx2x_cl45_write(bp, phy,
3616 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
3617 phy->tx_preemphasis[1]);
3618 }
3619
3620 return 0;
3849} 3621}
3850 3622
3851static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy, 3623static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
@@ -3861,40 +3633,31 @@ static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
3861 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 3633 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
3862 /* HW reset */ 3634 /* HW reset */
3863 bnx2x_ext_phy_hw_reset(bp, params->port); 3635 bnx2x_ext_phy_hw_reset(bp, params->port);
3636 bnx2x_wait_reset_complete(bp, phy);
3864 3637
3865 DP(NETIF_MSG_LINK, 3638 bnx2x_cl45_write(bp, phy,
3866 "Setting the SFX7101 LASI indication\n"); 3639 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
3867 bnx2x_wait_reset_complete(bp, phy); 3640 DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
3868 bnx2x_cl45_write(bp, phy, 3641 bnx2x_cl45_write(bp, phy,
3869 MDIO_PMA_DEVAD, 3642 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
3870 MDIO_PMA_REG_LASI_CTRL, 0x1);
3871 DP(NETIF_MSG_LINK,
3872 "Setting the SFX7101 LED to blink on traffic\n");
3873 bnx2x_cl45_write(bp, phy,
3874 MDIO_PMA_DEVAD,
3875 MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
3876
3877 bnx2x_ext_phy_set_pause(params, phy, vars);
3878 /* Restart autoneg */
3879 bnx2x_cl45_read(bp, phy,
3880 MDIO_AN_DEVAD,
3881 MDIO_AN_REG_CTRL, &val);
3882 val |= 0x200;
3883 bnx2x_cl45_write(bp, phy,
3884 MDIO_AN_DEVAD,
3885 MDIO_AN_REG_CTRL, val);
3886 3643
3887 /* Save spirom version */ 3644 bnx2x_ext_phy_set_pause(params, phy, vars);
3888 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 3645 /* Restart autoneg */
3889 MDIO_PMA_REG_7101_VER1, &fw_ver1); 3646 bnx2x_cl45_read(bp, phy,
3647 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
3648 val |= 0x200;
3649 bnx2x_cl45_write(bp, phy,
3650 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
3890 3651
3891 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 3652 /* Save spirom version */
3892 MDIO_PMA_REG_7101_VER2, &fw_ver2); 3653 bnx2x_cl45_read(bp, phy,
3654 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
3893 3655
3894 bnx2x_save_spirom_version(params->bp, params->port, 3656 bnx2x_cl45_read(bp, phy,
3895 params->shmem_base, 3657 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
3896 (u32)(fw_ver1<<16 | fw_ver2)); 3658 bnx2x_save_spirom_version(bp, params->port,
3897 return 0; 3659 (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
3660 return 0;
3898} 3661}
3899 3662
3900static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy, 3663static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
@@ -3902,145 +3665,121 @@ static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
3902 struct link_vars *vars) 3665 struct link_vars *vars)
3903{ 3666{
3904 struct bnx2x *bp = params->bp; 3667 struct bnx2x *bp = params->bp;
3905 { 3668 u16 autoneg_val, an_1000_val, an_10_100_val;
3906 /* This phy uses the NIG latch mechanism since link 3669 bnx2x_wait_reset_complete(bp, phy);
3907 indication arrives through its LED4 and not via 3670 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
3908 its LASI signal, so we get steady signal 3671 1 << NIG_LATCH_BC_ENABLE_MI_INT);
3909 instead of clear on read */ 3672
3910 u16 autoneg_val, an_1000_val, an_10_100_val, temp; 3673 bnx2x_cl45_write(bp, phy,
3911 temp = vars->line_speed; 3674 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
3912 vars->line_speed = SPEED_10000; 3675 bnx2x_8481_set_led(bp, phy);
3913 bnx2x_wait_reset_complete(bp, phy); 3676 /* set 1000 speed advertisement */
3914 bnx2x_set_autoneg(phy, params, vars, 0); 3677 bnx2x_cl45_read(bp, phy,
3915 bnx2x_program_serdes(phy, params, vars); 3678 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
3916 vars->line_speed = temp; 3679 &an_1000_val);
3917 3680
3918 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, 3681 bnx2x_ext_phy_set_pause(params, phy, vars);
3919 1 << NIG_LATCH_BC_ENABLE_MI_INT); 3682 bnx2x_cl45_read(bp, phy,
3683 MDIO_AN_DEVAD,
3684 MDIO_AN_REG_8481_LEGACY_AN_ADV,
3685 &an_10_100_val);
3686 bnx2x_cl45_read(bp, phy,
3687 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
3688 &autoneg_val);
3689 /* Disable forced speed */
3690 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
3691 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
3692
3693 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3694 (phy->speed_cap_mask &
3695 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3696 (phy->req_line_speed == SPEED_1000)) {
3697 an_1000_val |= (1<<8);
3698 autoneg_val |= (1<<9 | 1<<12);
3699 if (phy->req_duplex == DUPLEX_FULL)
3700 an_1000_val |= (1<<9);
3701 DP(NETIF_MSG_LINK, "Advertising 1G\n");
3702 } else
3703 an_1000_val &= ~((1<<8) | (1<<9));
3920 3704
3921 bnx2x_cl45_write(bp, phy, 3705 bnx2x_cl45_write(bp, phy,
3922 MDIO_PMA_DEVAD, 3706 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
3923 MDIO_PMA_REG_CTRL, 0x0000); 3707 an_1000_val);
3708
3709 /* set 10 speed advertisement */
3710 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3711 (phy->speed_cap_mask &
3712 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
3713 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
3714 an_10_100_val |= (1<<7);
3715 /* Enable autoneg and restart autoneg for legacy speeds */
3716 autoneg_val |= (1<<9 | 1<<12);
3717
3718 if (phy->req_duplex == DUPLEX_FULL)
3719 an_10_100_val |= (1<<8);
3720 DP(NETIF_MSG_LINK, "Advertising 100M\n");
3721 }
3722 /* set 10 speed advertisement */
3723 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3724 (phy->speed_cap_mask &
3725 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
3726 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
3727 an_10_100_val |= (1<<5);
3728 autoneg_val |= (1<<9 | 1<<12);
3729 if (phy->req_duplex == DUPLEX_FULL)
3730 an_10_100_val |= (1<<6);
3731 DP(NETIF_MSG_LINK, "Advertising 10M\n");
3732 }
3924 3733
3925 bnx2x_8481_set_led(bp, phy); 3734 /* Only 10/100 are allowed to work in FORCE mode */
3735 if (phy->req_line_speed == SPEED_100) {
3736 autoneg_val |= (1<<13);
3737 /* Enabled AUTO-MDIX when autoneg is disabled */
3738 bnx2x_cl45_write(bp, phy,
3739 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
3740 (1<<15 | 1<<9 | 7<<0));
3741 DP(NETIF_MSG_LINK, "Setting 100M force\n");
3742 }
3743 if (phy->req_line_speed == SPEED_10) {
3744 /* Enabled AUTO-MDIX when autoneg is disabled */
3745 bnx2x_cl45_write(bp, phy,
3746 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
3747 (1<<15 | 1<<9 | 7<<0));
3748 DP(NETIF_MSG_LINK, "Setting 10M force\n");
3749 }
3926 3750
3927 bnx2x_cl45_read(bp, phy, 3751 bnx2x_cl45_write(bp, phy,
3928 MDIO_AN_DEVAD, 3752 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
3929 MDIO_AN_REG_8481_1000T_CTRL, 3753 an_10_100_val);
3930 &an_1000_val);
3931 bnx2x_ext_phy_set_pause(params, phy, vars);
3932 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3933 MDIO_AN_REG_8481_LEGACY_AN_ADV,
3934 &an_10_100_val);
3935 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3936 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
3937 &autoneg_val);
3938 /* Disable forced speed */
3939 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) |
3940 (1<<13));
3941 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
3942
3943 if (((params->req_line_speed == SPEED_AUTO_NEG) &&
3944 (params->speed_cap_mask &
3945 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3946 (params->req_line_speed == SPEED_1000)) {
3947 an_1000_val |= (1<<8);
3948 autoneg_val |= (1<<9 | 1<<12);
3949 if (params->req_duplex == DUPLEX_FULL)
3950 an_1000_val |= (1<<9);
3951 DP(NETIF_MSG_LINK, "Advertising 1G\n");
3952 } else
3953 an_1000_val &= ~((1<<8) | (1<<9));
3954 3754
3955 bnx2x_cl45_write(bp, phy, 3755 if (phy->req_duplex == DUPLEX_FULL)
3956 MDIO_AN_DEVAD, 3756 autoneg_val |= (1<<8);
3957 MDIO_AN_REG_8481_1000T_CTRL,
3958 an_1000_val);
3959
3960 /* set 10 speed advertisement */
3961 if (((params->req_line_speed == SPEED_AUTO_NEG) &&
3962 (params->speed_cap_mask &
3963 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
3964 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
3965 an_10_100_val |= (1<<7);
3966 /*
3967 * Enable autoneg and restart autoneg for
3968 * legacy speeds
3969 */
3970 autoneg_val |= (1<<9 | 1<<12);
3971
3972 if (params->req_duplex == DUPLEX_FULL)
3973 an_10_100_val |= (1<<8);
3974 DP(NETIF_MSG_LINK, "Advertising 100M\n");
3975 }
3976 /* set 10 speed advertisement */
3977 if (((params->req_line_speed == SPEED_AUTO_NEG) &&
3978 (params->speed_cap_mask &
3979 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
3980 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
3981 an_10_100_val |= (1<<5);
3982 autoneg_val |= (1<<9 | 1<<12);
3983 if (params->req_duplex == DUPLEX_FULL)
3984 an_10_100_val |= (1<<6);
3985 DP(NETIF_MSG_LINK, "Advertising 10M\n");
3986 }
3987 3757
3988 /* Only 10/100 are allowed to work in FORCE mode */ 3758 bnx2x_cl45_write(bp, phy,
3989 if (params->req_line_speed == SPEED_100) { 3759 MDIO_AN_DEVAD,
3990 autoneg_val |= (1<<13); 3760 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
3991 /* Enabled AUTO-MDIX when autoneg is disabled */
3992 bnx2x_cl45_write(bp, phy,
3993 MDIO_AN_DEVAD,
3994 MDIO_AN_REG_8481_AUX_CTRL,
3995 (1<<15 | 1<<9 | 7<<0));
3996 DP(NETIF_MSG_LINK, "Setting 100M force\n");
3997 }
3998 if (params->req_line_speed == SPEED_10) {
3999 /* Enabled AUTO-MDIX when autoneg is disabled */
4000 bnx2x_cl45_write(bp, phy,
4001 MDIO_AN_DEVAD,
4002 MDIO_AN_REG_8481_AUX_CTRL,
4003 (1<<15 | 1<<9 | 7<<0));
4004 DP(NETIF_MSG_LINK, "Setting 10M force\n");
4005 }
4006 3761
4007 bnx2x_cl45_write(bp, phy, 3762 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
4008 MDIO_AN_DEVAD, 3763 (phy->speed_cap_mask &
4009 MDIO_AN_REG_8481_LEGACY_AN_ADV, 3764 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
4010 an_10_100_val); 3765 (phy->req_line_speed == SPEED_10000)) {
3766 DP(NETIF_MSG_LINK, "Advertising 10G\n");
3767 /* Restart autoneg for 10G*/
4011 3768
4012 if (params->req_duplex == DUPLEX_FULL) 3769 bnx2x_cl45_write(bp, phy,
4013 autoneg_val |= (1<<8); 3770 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
3771 0x3200);
3772 } else if (phy->req_line_speed != SPEED_10 &&
3773 phy->req_line_speed != SPEED_100) {
3774 bnx2x_cl45_write(bp, phy,
3775 MDIO_AN_DEVAD,
3776 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
3777 1);
3778 }
3779 /* Save spirom version */
3780 bnx2x_save_8481_spirom_version(phy, params, params->shmem_base);
4014 3781
4015 bnx2x_cl45_write(bp, phy, 3782 return 0;
4016 MDIO_AN_DEVAD,
4017 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4018 autoneg_val);
4019
4020 if (((params->req_line_speed == SPEED_AUTO_NEG) &&
4021 (params->speed_cap_mask &
4022 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
4023 (params->req_line_speed == SPEED_10000)) {
4024 DP(NETIF_MSG_LINK, "Advertising 10G\n");
4025 /* Restart autoneg for 10G*/
4026
4027 bnx2x_cl45_write(bp, phy,
4028 MDIO_AN_DEVAD,
4029 MDIO_AN_REG_CTRL,
4030 0x3200);
4031
4032 } else if (params->req_line_speed != SPEED_10 &&
4033 params->req_line_speed != SPEED_100)
4034 bnx2x_cl45_write(bp, phy,
4035 MDIO_AN_DEVAD,
4036 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
4037 1);
4038
4039 /* Save spirom version */
4040 bnx2x_save_8481_spirom_version(phy, params,
4041 params->shmem_base);
4042 return 0;
4043 }
4044} 3783}
4045 3784
4046static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy, 3785static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
@@ -4132,16 +3871,16 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
4132 absence of the Rx signal. (bit 9) */ 3871 absence of the Rx signal. (bit 9) */
4133 mod_abs |= ((1<<8)|(1<<9)); 3872 mod_abs |= ((1<<8)|(1<<9));
4134 bnx2x_cl45_write(bp, phy, 3873 bnx2x_cl45_write(bp, phy,
4135 MDIO_PMA_DEVAD, 3874 MDIO_PMA_DEVAD,
4136 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 3875 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4137 3876
4138 /* Clear RX alarm since it stays up as long as 3877 /* Clear RX alarm since it stays up as long as
4139 the mod_abs wasn't changed. This is need to be done 3878 the mod_abs wasn't changed. This is need to be done
4140 before calling the module detection, otherwise it will clear 3879 before calling the module detection, otherwise it will clear
4141 the link update alarm */ 3880 the link update alarm */
4142 bnx2x_cl45_read(bp, phy, 3881 bnx2x_cl45_read(bp, phy,
4143 MDIO_PMA_DEVAD, 3882 MDIO_PMA_DEVAD,
4144 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); 3883 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4145 3884
4146 3885
4147 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 3886 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
@@ -4164,37 +3903,33 @@ static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4164 struct link_params *params, 3903 struct link_params *params,
4165 struct link_vars *vars) 3904 struct link_vars *vars)
4166{ 3905{
4167 u8 ext_phy_link_up = 0; 3906 u8 link_up = 0;
4168 u16 val1, rx_sd; 3907 u16 val1, rx_sd;
4169 struct bnx2x *bp = params->bp; 3908 struct bnx2x *bp = params->bp;
4170 DP(NETIF_MSG_LINK, "XGXS 8705\n"); 3909 DP(NETIF_MSG_LINK, "read status 8705\n");
4171 bnx2x_cl45_read(bp, phy, 3910 bnx2x_cl45_read(bp, phy,
4172 MDIO_WIS_DEVAD, 3911 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4173 MDIO_WIS_REG_LASI_STATUS, &val1); 3912 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4174 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4175 3913
4176 bnx2x_cl45_read(bp, phy, 3914 bnx2x_cl45_read(bp, phy,
4177 MDIO_WIS_DEVAD, 3915 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4178 MDIO_WIS_REG_LASI_STATUS, &val1); 3916 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4179 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4180 3917
4181 bnx2x_cl45_read(bp, phy, 3918 bnx2x_cl45_read(bp, phy,
4182 MDIO_PMA_DEVAD, 3919 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4183 MDIO_PMA_REG_RX_SD, &rx_sd);
4184 3920
4185 bnx2x_cl45_read(bp, phy, 3921 bnx2x_cl45_read(bp, phy,
4186 1, 3922 MDIO_PMA_DEVAD, 0xc809, &val1);
4187 0xc809, &val1); 3923 bnx2x_cl45_read(bp, phy,
4188 bnx2x_cl45_read(bp, phy, 3924 MDIO_PMA_DEVAD, 0xc809, &val1);
4189 1,
4190 0xc809, &val1);
4191 3925
4192 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); 3926 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4193 ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && 3927 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4194 ((val1 & (1<<8)) == 0)); 3928 if (link_up) {
4195 if (ext_phy_link_up) 3929 vars->line_speed = SPEED_10000;
4196 vars->line_speed = SPEED_10000; 3930 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4197 return ext_phy_link_up; 3931 }
3932 return link_up;
4198} 3933}
4199 3934
4200static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy, 3935static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
@@ -4204,52 +3939,41 @@ static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
4204 u8 link_up = 0; 3939 u8 link_up = 0;
4205 u16 val1, val2, rx_sd, pcs_status; 3940 u16 val1, val2, rx_sd, pcs_status;
4206 struct bnx2x *bp = params->bp; 3941 struct bnx2x *bp = params->bp;
4207 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n"); 3942 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
4208 /* Clear RX Alarm*/ 3943 /* Clear RX Alarm*/
4209 bnx2x_cl45_read(bp, phy, 3944 bnx2x_cl45_read(bp, phy,
4210 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, 3945 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4211 &val2); 3946 /* clear LASI indication*/
4212 /* clear LASI indication*/ 3947 bnx2x_cl45_read(bp, phy,
4213 bnx2x_cl45_read(bp, phy, 3948 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4214 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, 3949 bnx2x_cl45_read(bp, phy,
4215 &val1); 3950 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
4216 bnx2x_cl45_read(bp, phy, 3951 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
4217 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4218 &val2);
4219 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->"
4220 "0x%x\n", val1, val2);
4221 3952
4222 bnx2x_cl45_read(bp, phy, 3953 bnx2x_cl45_read(bp, phy,
4223 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, 3954 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4224 &rx_sd); 3955 bnx2x_cl45_read(bp, phy,
4225 bnx2x_cl45_read(bp, phy, 3956 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
4226 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, 3957 bnx2x_cl45_read(bp, phy,
4227 &pcs_status); 3958 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
4228 bnx2x_cl45_read(bp, phy, 3959 bnx2x_cl45_read(bp, phy,
4229 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, 3960 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
4230 &val2); 3961
4231 bnx2x_cl45_read(bp, phy, 3962 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
4232 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, 3963 " link_status 0x%x\n", rx_sd, pcs_status, val2);
4233 &val2); 3964 /* link is up if both bit 0 of pmd_rx_sd and
4234 3965 * bit 0 of pcs_status are set, or if the autoneg bit
4235 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x" 3966 * 1 is set
4236 " pcs_status 0x%x 1Gbps link_status 0x%x\n", 3967 */
4237 rx_sd, pcs_status, val2); 3968 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
4238 /* link is up if both bit 0 of pmd_rx_sd and 3969 if (link_up) {
4239 * bit 0 of pcs_status are set, or if the autoneg bit 3970 if (val2 & (1<<1))
4240 1 is set 3971 vars->line_speed = SPEED_1000;
4241 */ 3972 else
4242 link_up = ((rx_sd & pcs_status & 0x1) || 3973 vars->line_speed = SPEED_10000;
4243 (val2 & (1<<1))); 3974 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4244 if (link_up) { 3975 }
4245 if (val2 & (1<<1)) 3976 return link_up;
4246 vars->line_speed = SPEED_1000;
4247 else
4248 vars->line_speed = SPEED_10000;
4249 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4250 return link_up;
4251 }
4252 return 0;
4253} 3977}
4254 3978
4255static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy, 3979static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
@@ -4284,312 +4008,217 @@ static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
4284 4008
4285{ 4009{
4286 struct bnx2x *bp = params->bp; 4010 struct bnx2x *bp = params->bp;
4287 u8 ext_phy_link_up = 0; 4011 u8 link_up = 0;
4288 u16 link_status = 0; 4012 u16 link_status = 0;
4289 u16 rx_alarm_status, val1; 4013 u16 rx_alarm_status, val1;
4290 /* Check the LASI */ 4014 /* Check the LASI */
4291 bnx2x_cl45_read(bp, phy, 4015 bnx2x_cl45_read(bp, phy,
4292 MDIO_PMA_DEVAD, 4016 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
4293 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status); 4017 &rx_alarm_status);
4018 vars->line_speed = 0;
4019 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
4294 4020
4295 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", 4021 bnx2x_cl45_read(bp, phy,
4296 rx_alarm_status); 4022 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4297 4023
4298 bnx2x_cl45_read(bp, phy, 4024 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
4299 MDIO_PMA_DEVAD,
4300 MDIO_PMA_REG_LASI_STATUS, &val1);
4301 4025
4302 DP(NETIF_MSG_LINK, 4026 /* Clear MSG-OUT */
4303 "8727 LASI status 0x%x\n", 4027 bnx2x_cl45_read(bp, phy,
4304 val1); 4028 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4305 4029
4306 /* Clear MSG-OUT */ 4030 /**
4307 bnx2x_cl45_read(bp, phy, 4031 * If a module is present and there is need to check
4308 MDIO_PMA_DEVAD, 4032 * for over current
4309 MDIO_PMA_REG_M8051_MSGOUT_REG, 4033 */
4310 &val1); 4034 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
4035 /* Check over-current using 8727 GPIO0 input*/
4036 bnx2x_cl45_read(bp, phy,
4037 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
4038 &val1);
4039
4040 if ((val1 & (1<<8)) == 0) {
4041 DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
4042 " on port %d\n", params->port);
4043 netdev_err(bp->dev, "Error: Power fault on Port %d has"
4044 " been detected and the power to "
4045 "that SFP+ module has been removed"
4046 " to prevent failure of the card."
4047 " Please remove the SFP+ module and"
4048 " restart the system to clear this"
4049 " error.\n",
4050 params->port);
4311 4051
4312 /* 4052 /*
4313 * If a module is present and there is need to check 4053 * Disable all RX_ALARMs except for
4314 * for over current 4054 * mod_abs
4315 */ 4055 */
4316 if (!(phy->flags & FLAGS_NOC) && 4056 bnx2x_cl45_write(bp, phy,
4317 !(rx_alarm_status & (1<<5))) { 4057 MDIO_PMA_DEVAD,
4318 /* Check over-current using 8727 GPIO0 input*/ 4058 MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
4319 bnx2x_cl45_read(bp, phy,
4320 MDIO_PMA_DEVAD,
4321 MDIO_PMA_REG_8727_GPIO_CTRL,
4322 &val1);
4323
4324 if ((val1 & (1<<8)) == 0) {
4325 DP(NETIF_MSG_LINK, "8727 Power fault"
4326 " has been detected on "
4327 "port %d\n",
4328 params->port);
4329 netdev_err(bp->dev, "Error: Power fault on Port %d has been detected and the power to that SFP+ module has been removed to prevent failure of the card. Please remove the SFP+ module and restart the system to clear this error.\n",
4330 params->port);
4331 /*
4332 * Disable all RX_ALARMs except for
4333 * mod_abs
4334 */
4335 bnx2x_cl45_write(bp, phy,
4336 MDIO_PMA_DEVAD,
4337 MDIO_PMA_REG_RX_ALARM_CTRL,
4338 (1<<5));
4339
4340 bnx2x_cl45_read(bp, phy,
4341 MDIO_PMA_DEVAD,
4342 MDIO_PMA_REG_PHY_IDENTIFIER,
4343 &val1);
4344 /* Wait for module_absent_event */
4345 val1 |= (1<<8);
4346 bnx2x_cl45_write(bp, phy,
4347 MDIO_PMA_DEVAD,
4348 MDIO_PMA_REG_PHY_IDENTIFIER,
4349 val1);
4350 /* Clear RX alarm */
4351 bnx2x_cl45_read(bp, phy,
4352 MDIO_PMA_DEVAD,
4353 MDIO_PMA_REG_RX_ALARM,
4354 &rx_alarm_status);
4355 return ext_phy_link_up;
4356 }
4357 } /* Over current check */
4358
4359 /* When module absent bit is set, check module */
4360 if (rx_alarm_status & (1<<5)) {
4361 bnx2x_8727_handle_mod_abs(phy, params);
4362 /* Enable all mod_abs and link detection bits */
4363 bnx2x_cl45_write(bp, phy,
4364 MDIO_PMA_DEVAD,
4365 MDIO_PMA_REG_RX_ALARM_CTRL,
4366 ((1<<5) | (1<<2)));
4367 }
4368 4059
4369 /* If transmitter is disabled,
4370 ignore false link up indication */
4371 bnx2x_cl45_read(bp, phy, 4060 bnx2x_cl45_read(bp, phy,
4372 MDIO_PMA_DEVAD, 4061 MDIO_PMA_DEVAD,
4373 MDIO_PMA_REG_PHY_IDENTIFIER, 4062 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
4374 &val1); 4063 /* Wait for module_absent_event */
4375 if (val1 & (1<<15)) { 4064 val1 |= (1<<8);
4376 DP(NETIF_MSG_LINK, "Tx is disabled\n"); 4065 bnx2x_cl45_write(bp, phy,
4377 ext_phy_link_up = 0; 4066 MDIO_PMA_DEVAD,
4378 return ext_phy_link_up; 4067 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
4379 } 4068 /* Clear RX alarm */
4380
4381 bnx2x_cl45_read(bp, phy, 4069 bnx2x_cl45_read(bp, phy,
4382 MDIO_PMA_DEVAD, 4070 MDIO_PMA_DEVAD,
4383 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 4071 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4384 &link_status); 4072 return 0;
4385 4073 }
4386 /* Bits 0..2 --> speed detected, 4074 } /* Over current check */
4387 bits 13..15--> link is down */
4388 if ((link_status & (1<<2)) &&
4389 (!(link_status & (1<<15)))) {
4390 ext_phy_link_up = 1;
4391 vars->line_speed = SPEED_10000;
4392 } else if ((link_status & (1<<0)) &&
4393 (!(link_status & (1<<13)))) {
4394 ext_phy_link_up = 1;
4395 vars->line_speed = SPEED_1000;
4396 DP(NETIF_MSG_LINK,
4397 "port %x: External link"
4398 " up in 1G\n", params->port);
4399 } else {
4400 ext_phy_link_up = 0;
4401 DP(NETIF_MSG_LINK,
4402 "port %x: External link"
4403 " is down\n", params->port);
4404 }
4405 return ext_phy_link_up;
4406 4075
4076 /* When module absent bit is set, check module */
4077 if (rx_alarm_status & (1<<5)) {
4078 bnx2x_8727_handle_mod_abs(phy, params);
4079 /* Enable all mod_abs and link detection bits */
4080 bnx2x_cl45_write(bp, phy,
4081 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
4082 ((1<<5) | (1<<2)));
4083 }
4084
4085 /* If transmitter is disabled, ignore false link up indication */
4086 bnx2x_cl45_read(bp, phy,
4087 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
4088 if (val1 & (1<<15)) {
4089 DP(NETIF_MSG_LINK, "Tx is disabled\n");
4090 return 0;
4091 }
4092
4093 bnx2x_cl45_read(bp, phy,
4094 MDIO_PMA_DEVAD,
4095 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
4096
4097 /* Bits 0..2 --> speed detected,
4098 bits 13..15--> link is down */
4099 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4100 link_up = 1;
4101 vars->line_speed = SPEED_10000;
4102 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4103 link_up = 1;
4104 vars->line_speed = SPEED_1000;
4105 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4106 params->port);
4107 } else {
4108 link_up = 0;
4109 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4110 params->port);
4111 }
4112 if (link_up)
4113 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4114 return link_up;
4407} 4115}
4116
4408static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy, 4117static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
4409 struct link_params *params, 4118 struct link_params *params,
4410 struct link_vars *vars) 4119 struct link_vars *vars)
4411{ 4120{
4412 struct bnx2x *bp = params->bp; 4121 struct bnx2x *bp = params->bp;
4413 u8 ext_phy_link_up = 0; 4122 u8 link_up = 0;
4414 u16 val1, val2; 4123 u16 val1, val2;
4415 u16 link_status = 0; 4124 u16 link_status = 0;
4416 u16 an1000_status = 0; 4125 u16 an1000_status = 0;
4417 4126
4418 if (phy->type == 4127 bnx2x_cl45_read(bp, phy,
4419 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) { 4128 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4420 bnx2x_cl45_read(bp, phy,
4421 MDIO_PCS_DEVAD,
4422 MDIO_PCS_REG_LASI_STATUS, &val1);
4423 bnx2x_cl45_read(bp, phy,
4424 MDIO_PCS_DEVAD,
4425 MDIO_PCS_REG_LASI_STATUS, &val2);
4426 DP(NETIF_MSG_LINK,
4427 "870x LASI status 0x%x->0x%x\n",
4428 val1, val2);
4429 } else {
4430 /* In 8073, port1 is directed through emac0 and
4431 * port0 is directed through emac1
4432 */
4433 bnx2x_cl45_read(bp, phy,
4434 MDIO_PMA_DEVAD,
4435 MDIO_PMA_REG_LASI_STATUS, &val1);
4436 4129
4437 DP(NETIF_MSG_LINK, 4130 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
4438 "8703 LASI status 0x%x\n",
4439 val1);
4440 4131
4441 } 4132 /* clear the interrupt LASI status register */
4442 /* clear the interrupt LASI status register */ 4133 bnx2x_cl45_read(bp, phy,
4443 bnx2x_cl45_read(bp, phy, 4134 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4444 MDIO_PCS_DEVAD, 4135 bnx2x_cl45_read(bp, phy,
4445 MDIO_PCS_REG_STATUS, &val2); 4136 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4446 bnx2x_cl45_read(bp, phy, 4137 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4447 MDIO_PCS_DEVAD, 4138 /* Clear MSG-OUT */
4448 MDIO_PCS_REG_STATUS, &val1); 4139 bnx2x_cl45_read(bp, phy,
4449 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", 4140 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4450 val2, val1);
4451 /* Clear MSG-OUT */
4452 bnx2x_cl45_read(bp, phy,
4453 MDIO_PMA_DEVAD,
4454 MDIO_PMA_REG_M8051_MSGOUT_REG,
4455 &val1);
4456 4141
4457 /* Check the LASI */ 4142 /* Check the LASI */
4458 bnx2x_cl45_read(bp, phy, 4143 bnx2x_cl45_read(bp, phy,
4459 MDIO_PMA_DEVAD, 4144 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4460 MDIO_PMA_REG_RX_ALARM, &val2);
4461 4145
4462 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); 4146 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4463 4147
4464 /* Check the link status */ 4148 /* Check the link status */
4465 bnx2x_cl45_read(bp, phy, 4149 bnx2x_cl45_read(bp, phy,
4466 MDIO_PCS_DEVAD, 4150 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4467 MDIO_PCS_REG_STATUS, &val2); 4151 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4468 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4469 4152
4470 bnx2x_cl45_read(bp, phy, 4153 bnx2x_cl45_read(bp, phy,
4471 MDIO_PMA_DEVAD, 4154 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4472 MDIO_PMA_REG_STATUS, &val2); 4155 bnx2x_cl45_read(bp, phy,
4473 bnx2x_cl45_read(bp, phy, 4156 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4474 MDIO_PMA_DEVAD, 4157 link_up = ((val1 & 4) == 4);
4475 MDIO_PMA_REG_STATUS, &val1); 4158 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4476 ext_phy_link_up = ((val1 & 4) == 4);
4477 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4478 if (phy->type ==
4479 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
4480
4481 if (ext_phy_link_up &&
4482 ((params->req_line_speed !=
4483 SPEED_10000))) {
4484 if (bnx2x_8073_xaui_wa(bp, phy)
4485 != 0) {
4486 ext_phy_link_up = 0;
4487 return ext_phy_link_up;
4488 }
4489 }
4490 bnx2x_cl45_read(bp, phy,
4491 MDIO_AN_DEVAD,
4492 MDIO_AN_REG_LINK_STATUS,
4493 &an1000_status);
4494 bnx2x_cl45_read(bp, phy,
4495 MDIO_AN_DEVAD,
4496 MDIO_AN_REG_LINK_STATUS,
4497 &an1000_status);
4498 4159
4499 /* Check the link status on 1.1.2 */ 4160 if (link_up &&
4500 bnx2x_cl45_read(bp, phy, 4161 ((phy->req_line_speed != SPEED_10000))) {
4501 MDIO_PMA_DEVAD, 4162 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4502 MDIO_PMA_REG_STATUS, &val2); 4163 return 0;
4503 bnx2x_cl45_read(bp, phy, 4164 }
4504 MDIO_PMA_DEVAD, 4165 bnx2x_cl45_read(bp, phy,
4505 MDIO_PMA_REG_STATUS, &val1); 4166 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4506 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," 4167 bnx2x_cl45_read(bp, phy,
4507 "an_link_status=0x%x\n", 4168 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4508 val2, val1, an1000_status); 4169
4509 4170 /* Check the link status on 1.1.2 */
4510 ext_phy_link_up = (((val1 & 4) == 4) || 4171 bnx2x_cl45_read(bp, phy,
4511 (an1000_status & (1<<1))); 4172 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4512 if (ext_phy_link_up && 4173 bnx2x_cl45_read(bp, phy,
4513 bnx2x_8073_is_snr_needed(bp, phy)) { 4174 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4514 /* The SNR will improve about 2dbby 4175 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4515 changing the BW and FEE main tap.*/ 4176 "an_link_status=0x%x\n", val2, val1, an1000_status);
4516 4177
4517 /* The 1st write to change FFE main 4178 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4518 tap is set before restart AN */ 4179 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4519 /* Change PLL Bandwidth in EDC 4180 /* The SNR will improve about 2dbby
4520 register */ 4181 changing the BW and FEE main tap.*/
4521 bnx2x_cl45_write(bp, phy, 4182 /* The 1st write to change FFE main
4522 MDIO_PMA_DEVAD, 4183 tap is set before restart AN */
4523 MDIO_PMA_REG_PLL_BANDWIDTH, 4184 /* Change PLL Bandwidth in EDC
4524 0x26BC); 4185 register */
4525 4186 bnx2x_cl45_write(bp, phy,
4526 /* Change CDR Bandwidth in EDC 4187 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4527 register */ 4188 0x26BC);
4528 bnx2x_cl45_write(bp, phy, 4189
4529 MDIO_PMA_DEVAD, 4190 /* Change CDR Bandwidth in EDC register */
4530 MDIO_PMA_REG_CDR_BANDWIDTH, 4191 bnx2x_cl45_write(bp, phy,
4531 0x0333); 4192 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4532 } 4193 0x0333);
4533 bnx2x_cl45_read(bp, phy, 4194 }
4534 MDIO_PMA_DEVAD, 4195 bnx2x_cl45_read(bp, phy,
4535 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 4196 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4536 &link_status); 4197 &link_status);
4537 4198
4538 /* Bits 0..2 --> speed detected, 4199 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4539 bits 13..15--> link is down */ 4200 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4540 if ((link_status & (1<<2)) && 4201 link_up = 1;
4541 (!(link_status & (1<<15)))) { 4202 vars->line_speed = SPEED_10000;
4542 ext_phy_link_up = 1; 4203 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4543 vars->line_speed = SPEED_10000; 4204 params->port);
4544 DP(NETIF_MSG_LINK, 4205 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4545 "port %x: External link" 4206 link_up = 1;
4546 " up in 10G\n", params->port); 4207 vars->line_speed = SPEED_2500;
4547 } else if ((link_status & (1<<1)) && 4208 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4548 (!(link_status & (1<<14)))) { 4209 params->port);
4549 ext_phy_link_up = 1; 4210 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4550 vars->line_speed = SPEED_2500; 4211 link_up = 1;
4551 DP(NETIF_MSG_LINK, 4212 vars->line_speed = SPEED_1000;
4552 "port %x: External link" 4213 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4553 " up in 2.5G\n", params->port); 4214 params->port);
4554 } else if ((link_status & (1<<0)) && 4215 } else {
4555 (!(link_status & (1<<13)))) { 4216 link_up = 0;
4556 ext_phy_link_up = 1; 4217 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4557 vars->line_speed = SPEED_1000; 4218 params->port);
4558 DP(NETIF_MSG_LINK, 4219 }
4559 "port %x: External link"
4560 " up in 1G\n", params->port);
4561 } else {
4562 ext_phy_link_up = 0;
4563 DP(NETIF_MSG_LINK,
4564 "port %x: External link"
4565 " is down\n", params->port);
4566 }
4567 } else {
4568 /* See if 1G link is up for the 8072 */
4569 bnx2x_cl45_read(bp, phy,
4570 MDIO_AN_DEVAD,
4571 MDIO_AN_REG_LINK_STATUS,
4572 &an1000_status);
4573 bnx2x_cl45_read(bp, phy,
4574 MDIO_AN_DEVAD,
4575 MDIO_AN_REG_LINK_STATUS,
4576 &an1000_status);
4577 if (an1000_status & (1<<1)) {
4578 ext_phy_link_up = 1;
4579 vars->line_speed = SPEED_1000;
4580 DP(NETIF_MSG_LINK,
4581 "port %x: External link"
4582 " up in 1G\n", params->port);
4583 } else if (ext_phy_link_up) {
4584 ext_phy_link_up = 1;
4585 vars->line_speed = SPEED_10000;
4586 DP(NETIF_MSG_LINK,
4587 "port %x: External link"
4588 " up in 10G\n", params->port);
4589 }
4590 }
4591 4220
4592 return ext_phy_link_up; 4221 return link_up;
4593} 4222}
4594 4223
4595static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy, 4224static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
@@ -4597,42 +4226,33 @@ static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
4597 struct link_vars *vars) 4226 struct link_vars *vars)
4598{ 4227{
4599 struct bnx2x *bp = params->bp; 4228 struct bnx2x *bp = params->bp;
4600 u8 ext_phy_link_up; 4229 u8 link_up;
4601 u16 val1, val2; 4230 u16 val1, val2;
4602 bnx2x_cl45_read(bp, phy, 4231 bnx2x_cl45_read(bp, phy,
4603 MDIO_PMA_DEVAD, 4232 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
4604 MDIO_PMA_REG_LASI_STATUS, &val2); 4233 bnx2x_cl45_read(bp, phy,
4605 bnx2x_cl45_read(bp, phy, 4234 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4606 MDIO_PMA_DEVAD, 4235 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
4607 MDIO_PMA_REG_LASI_STATUS, &val1); 4236 val2, val1);
4608 DP(NETIF_MSG_LINK, 4237 bnx2x_cl45_read(bp, phy,
4609 "10G-base-T LASI status 0x%x->0x%x\n", 4238 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4610 val2, val1); 4239 bnx2x_cl45_read(bp, phy,
4611 bnx2x_cl45_read(bp, phy, 4240 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4612 MDIO_PMA_DEVAD, 4241 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
4613 MDIO_PMA_REG_STATUS, &val2); 4242 val2, val1);
4614 bnx2x_cl45_read(bp, phy, 4243 link_up = ((val1 & 4) == 4);
4615 MDIO_PMA_DEVAD, 4244 /* if link is up
4616 MDIO_PMA_REG_STATUS, &val1); 4245 * print the AN outcome of the SFX7101 PHY
4617 DP(NETIF_MSG_LINK, 4246 */
4618 "10G-base-T PMA status 0x%x->0x%x\n", 4247 if (link_up) {
4619 val2, val1); 4248 bnx2x_cl45_read(bp, phy,
4620 ext_phy_link_up = ((val1 & 4) == 4); 4249 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
4621 /* if link is up 4250 &val2);
4622 * print the AN outcome of the SFX7101 PHY 4251 vars->line_speed = SPEED_10000;
4623 */ 4252 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
4624 if (ext_phy_link_up) { 4253 val2, (val2 & (1<<14)));
4625 bnx2x_cl45_read(bp, phy, 4254 }
4626 MDIO_AN_DEVAD, 4255 return link_up;
4627 MDIO_AN_REG_MASTER_STATUS,
4628 &val2);
4629 vars->line_speed = SPEED_10000;
4630 DP(NETIF_MSG_LINK,
4631 "SFX7101 AN status 0x%x->Master=%x\n",
4632 val2,
4633 (val2 & (1<<14)));
4634 }
4635 return ext_phy_link_up;
4636} 4256}
4637 4257
4638static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy, 4258static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
@@ -4640,73 +4260,78 @@ static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
4640 struct link_vars *vars) 4260 struct link_vars *vars)
4641{ 4261{
4642 struct bnx2x *bp = params->bp; 4262 struct bnx2x *bp = params->bp;
4643 u16 val1, val2; 4263 u16 val, val1, val2;
4644 u8 ext_phy_link_up = 0; 4264 u8 link_up = 0;
4645 4265
4646 /* Check 10G-BaseT link status */ 4266 /* Check 10G-BaseT link status */
4647 /* Check PMD signal ok */ 4267 /* Check PMD signal ok */
4268 bnx2x_cl45_read(bp, phy,
4269 MDIO_AN_DEVAD, 0xFFFA, &val1);
4270 bnx2x_cl45_read(bp, phy,
4271 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
4272 &val2);
4273 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
4274
4275 /* Check link 10G */
4276 if (val2 & (1<<11)) {
4277 vars->line_speed = SPEED_10000;
4278 link_up = 1;
4279 } else { /* Check Legacy speed link */
4280 u16 legacy_status, legacy_speed;
4281
4282 /* Enable expansion register 0x42 (Operation mode status) */
4283 bnx2x_cl45_write(bp, phy,
4284 MDIO_AN_DEVAD,
4285 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
4286
4287 /* Get legacy speed operation status */
4288 bnx2x_cl45_read(bp, phy,
4289 MDIO_AN_DEVAD,
4290 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
4291 &legacy_status);
4292
4293 DP(NETIF_MSG_LINK, "Legacy speed status"
4294 " = 0x%x\n", legacy_status);
4295 link_up = ((legacy_status & (1<<11)) == (1<<11));
4296 if (link_up) {
4297 legacy_speed = (legacy_status & (3<<9));
4298 if (legacy_speed == (0<<9))
4299 vars->line_speed = SPEED_10;
4300 else if (legacy_speed == (1<<9))
4301 vars->line_speed = SPEED_100;
4302 else if (legacy_speed == (2<<9))
4303 vars->line_speed = SPEED_1000;
4304 else /* Should not happen */
4305 vars->line_speed = 0;
4306
4307 if (legacy_status & (1<<8))
4308 vars->duplex = DUPLEX_FULL;
4309 else
4310 vars->duplex = DUPLEX_HALF;
4311
4312 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
4313 " is_duplex_full= %d\n", vars->line_speed,
4314 (vars->duplex == DUPLEX_FULL));
4315
4316 /* Check legacy speed AN resolution */
4648 bnx2x_cl45_read(bp, phy, 4317 bnx2x_cl45_read(bp, phy,
4649 MDIO_AN_DEVAD, 4318 MDIO_AN_DEVAD,
4650 0xFFFA, 4319 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
4651 &val1); 4320 &val);
4321 if (val & (1<<5))
4322 vars->link_status |=
4323 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
4652 bnx2x_cl45_read(bp, phy, 4324 bnx2x_cl45_read(bp, phy,
4653 MDIO_PMA_DEVAD, 4325 MDIO_AN_DEVAD,
4654 MDIO_PMA_REG_8481_PMD_SIGNAL, 4326 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
4655 &val2); 4327 &val);
4656 DP(NETIF_MSG_LINK, "PMD_SIGNAL 1.a811 = 0x%x\n", val2); 4328 if ((val & (1<<0)) == 0)
4657 4329 vars->link_status |=
4658 /* Check link 10G */ 4330 LINK_STATUS_PARALLEL_DETECTION_USED;
4659 if (val2 & (1<<11)) { 4331 }
4660 vars->line_speed = SPEED_10000; 4332 }
4661 ext_phy_link_up = 1; 4333 return link_up;
4662 } else { /* Check Legacy speed link */
4663 u16 legacy_status, legacy_speed;
4664
4665 /* Enable expansion register 0x42
4666 (Operation mode status) */
4667 bnx2x_cl45_write(bp, phy,
4668 MDIO_AN_DEVAD,
4669 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS,
4670 0xf42);
4671
4672 /* Get legacy speed operation status */
4673 bnx2x_cl45_read(bp, phy,
4674 MDIO_AN_DEVAD,
4675 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
4676 &legacy_status);
4677
4678 DP(NETIF_MSG_LINK, "Legacy speed status"
4679 " = 0x%x\n", legacy_status);
4680 ext_phy_link_up = ((legacy_status & (1<<11))
4681 == (1<<11));
4682 if (ext_phy_link_up) {
4683 legacy_speed = (legacy_status & (3<<9));
4684 if (legacy_speed == (0<<9))
4685 vars->line_speed = SPEED_10;
4686 else if (legacy_speed == (1<<9))
4687 vars->line_speed =
4688 SPEED_100;
4689 else if (legacy_speed == (2<<9))
4690 vars->line_speed =
4691 SPEED_1000;
4692 else /* Should not happen */
4693 vars->line_speed = 0;
4694
4695 if (legacy_status & (1<<8))
4696 vars->duplex = DUPLEX_FULL;
4697 else
4698 vars->duplex = DUPLEX_HALF;
4699
4700 DP(NETIF_MSG_LINK, "Link is up "
4701 "in %dMbps, is_duplex_full"
4702 "= %d\n",
4703 vars->line_speed,
4704 (vars->duplex == DUPLEX_FULL));
4705 }
4706 }
4707 return ext_phy_link_up;
4708} 4334}
4709
4710static void bnx2x_link_int_enable(struct link_params *params) 4335static void bnx2x_link_int_enable(struct link_params *params)
4711{ 4336{
4712 u8 port = params->port; 4337 u8 port = params->port;
@@ -4847,7 +4472,6 @@ static void bnx2x_link_int_ack(struct link_params *params,
4847 NIG_STATUS_SERDES0_LINK_STATUS); 4472 NIG_STATUS_SERDES0_LINK_STATUS);
4848 } 4473 }
4849 4474
4850 } else { /* link_down */
4851 } 4475 }
4852} 4476}
4853 4477
@@ -4933,13 +4557,12 @@ u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
4933} 4557}
4934 4558
4935static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy, 4559static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
4936 struct link_params *params, 4560 struct link_params *params)
4937 u8 is_10g)
4938{ 4561{
4939 u8 port = params->port; 4562 u8 port = params->port;
4940 struct bnx2x *bp = params->bp; 4563 struct bnx2x *bp = params->bp;
4941 4564
4942 if (is_10g) { 4565 if (phy->req_line_speed != SPEED_1000) {
4943 u32 md_devad; 4566 u32 md_devad;
4944 4567
4945 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n"); 4568 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
@@ -5474,7 +5097,7 @@ u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5474 if (params->phy[phy_index].config_loopback) 5097 if (params->phy[phy_index].config_loopback)
5475 params->phy[phy_index].config_loopback( 5098 params->phy[phy_index].config_loopback(
5476 &params->phy[phy_index], 5099 &params->phy[phy_index],
5477 params); 5100 params);
5478 } 5101 }
5479 } 5102 }
5480 5103
@@ -5714,7 +5337,7 @@ static u8 bnx2x_update_link_up(struct link_params *params,
5714 * - DUAL_MEDIA - The link between the 577xx and the first 5337 * - DUAL_MEDIA - The link between the 577xx and the first
5715 * external phy needs to be up, and at least one of the 2 5338 * external phy needs to be up, and at least one of the 2
5716 * external phy link must be up. 5339 * external phy link must be up.
5717*/ 5340 */
5718u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars) 5341u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
5719{ 5342{
5720 struct bnx2x *bp = params->bp; 5343 struct bnx2x *bp = params->bp;
@@ -6084,7 +5707,7 @@ static struct bnx2x_phy phy_8073 = {
6084 .speed_cap_mask = 0, 5707 .speed_cap_mask = 0,
6085 .req_duplex = 0, 5708 .req_duplex = 0,
6086 .rsrv = 0, 5709 .rsrv = 0,
6087 .config_init = (config_init_t)bnx2x_8072_8073_config_init, 5710 .config_init = (config_init_t)bnx2x_8073_config_init,
6088 .read_status = (read_status_t)bnx2x_8073_read_status, 5711 .read_status = (read_status_t)bnx2x_8073_read_status,
6089 .link_reset = (link_reset_t)bnx2x_8073_link_reset, 5712 .link_reset = (link_reset_t)bnx2x_8073_link_reset,
6090 .config_loopback = (config_loopback_t)NULL, 5713 .config_loopback = (config_loopback_t)NULL,
@@ -6427,6 +6050,7 @@ static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
6427 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); 6050 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
6428 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); 6051 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
6429 phy->mdio_ctrl = bnx2x_get_emac_base(bp, phy->type, port); 6052 phy->mdio_ctrl = bnx2x_get_emac_base(bp, phy->type, port);
6053
6430 return 0; 6054 return 0;
6431} 6055}
6432 6056
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index 1ecff37bab18..1184677640e5 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -4348,7 +4348,6 @@ static int bnx2x_init_port(struct bnx2x *bp)
4348 REG_WR(bp, reg_addr, val); 4348 REG_WR(bp, reg_addr, val);
4349 } 4349 }
4350 break; 4350 break;
4351 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4352 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 4351 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4353 bp->port.need_hw_lock = 1; 4352 bp->port.need_hw_lock = 1;
4354 break; 4353 break;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 05:19:18 -0500