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authorBruce Allan <bruce.w.allan@intel.com>2009-12-02 12:02:43 -0500
committerDavid S. Miller <davem@davemloft.net>2009-12-02 22:57:17 -0500
commit5eb6f3c70fcc0fb19b9087863e6e29f96a76f3bd (patch)
tree53b19370657a6af448f5b82d2bcef9f4fb79f2c1 /drivers
parent94e5b651595a8eb77665787f7559a6a7c916c195 (diff)
e1000e: refactor PHY ID detection workaround
The workaround that detects the correct PHY ID when an initial read of the PHY ID registers returns an invalid one should retry up to ten times with a small delay between attempts using a single PHY address and then repeat using the remaining possible PHY addresses. Do this instead of trying each possible PHY address repeating that up to 100 times. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/e1000e/hw.h2
-rw-r--r--drivers/net/e1000e/phy.c26
2 files changed, 17 insertions, 11 deletions
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index 41609d5561ba..a7d08dae79c4 100644
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -219,7 +219,7 @@ enum e1e_registers {
219 E1000_HICR = 0x08F00, /* Host Interface Control */ 219 E1000_HICR = 0x08F00, /* Host Interface Control */
220}; 220};
221 221
222/* RSS registers */ 222#define E1000_MAX_PHY_ADDR 4
223 223
224/* IGP01E1000 Specific Registers */ 224/* IGP01E1000 Specific Registers */
225#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 225#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index 0c69649af069..67a718862e70 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -2197,28 +2197,34 @@ enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2197s32 e1000e_determine_phy_address(struct e1000_hw *hw) 2197s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2198{ 2198{
2199 s32 ret_val = -E1000_ERR_PHY_TYPE; 2199 s32 ret_val = -E1000_ERR_PHY_TYPE;
2200 u32 phy_addr= 0; 2200 u32 phy_addr = 0;
2201 u32 i = 0; 2201 u32 i;
2202 enum e1000_phy_type phy_type = e1000_phy_unknown; 2202 enum e1000_phy_type phy_type = e1000_phy_unknown;
2203 2203
2204 do { 2204 hw->phy.id = phy_type;
2205 for (phy_addr = 0; phy_addr < 4; phy_addr++) { 2205
2206 hw->phy.addr = phy_addr; 2206 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2207 hw->phy.addr = phy_addr;
2208 i = 0;
2209
2210 do {
2207 e1000e_get_phy_id(hw); 2211 e1000e_get_phy_id(hw);
2208 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); 2212 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2209 2213
2210 /* 2214 /*
2211 * If phy_type is valid, break - we found our 2215 * If phy_type is valid, break - we found our
2212 * PHY address 2216 * PHY address
2213 */ 2217 */
2214 if (phy_type != e1000_phy_unknown) { 2218 if (phy_type != e1000_phy_unknown) {
2215 ret_val = 0; 2219 ret_val = 0;
2216 break; 2220 goto out;
2217 } 2221 }
2218 } 2222 msleep(1);
2219 i++; 2223 i++;
2220 } while ((ret_val != 0) && (i < 100)); 2224 } while (i < 10);
2225 }
2221 2226
2227out:
2222 return ret_val; 2228 return ret_val;
2223} 2229}
2224 2230