diff options
author | Yaniv Rosner <yanivr@broadcom.com> | 2009-11-05 12:18:12 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-11-05 23:00:35 -0500 |
commit | 15ddd2d0ef4849410a2251587b3652fe6a689fda (patch) | |
tree | 4964565c9e2f4bf350cc2774f29424c17028eac6 /drivers | |
parent | d5cb9e997708bd48d2ed3dd926dad7a6fc83bf56 (diff) |
bnx2x: Enable FC when parallel-detect is used
When parallel detect is used, flow-control is set to the
req_fc_auto_adv instead of none.
Motive: when 577xx is FC configuration is set to AUTO, while LP speed
is set to FORCE mode and FC to force RX/TX, link would come up using
parallel detect, and the FC will be set to NONE since FC capabilities
were not negotiated, although the LP is setting FC to force RX/TX.
Signed-off-by: Yaniv Rosner <yanivr@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/bnx2x_link.c | 37 | ||||
-rw-r--r-- | drivers/net/bnx2x_reg.h | 4 |
2 files changed, 41 insertions, 0 deletions
diff --git a/drivers/net/bnx2x_link.c b/drivers/net/bnx2x_link.c index bf1021ed5dd6..4c16a46f0caf 100644 --- a/drivers/net/bnx2x_link.c +++ b/drivers/net/bnx2x_link.c | |||
@@ -1621,6 +1621,39 @@ static u8 bnx2x_ext_phy_resolve_fc(struct link_params *params, | |||
1621 | return ret; | 1621 | return ret; |
1622 | } | 1622 | } |
1623 | 1623 | ||
1624 | static u8 bnx2x_direct_parallel_detect_used(struct link_params *params) | ||
1625 | { | ||
1626 | struct bnx2x *bp = params->bp; | ||
1627 | u16 pd_10g, status2_1000x; | ||
1628 | CL45_RD_OVER_CL22(bp, params->port, | ||
1629 | params->phy_addr, | ||
1630 | MDIO_REG_BANK_SERDES_DIGITAL, | ||
1631 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | ||
1632 | &status2_1000x); | ||
1633 | CL45_RD_OVER_CL22(bp, params->port, | ||
1634 | params->phy_addr, | ||
1635 | MDIO_REG_BANK_SERDES_DIGITAL, | ||
1636 | MDIO_SERDES_DIGITAL_A_1000X_STATUS2, | ||
1637 | &status2_1000x); | ||
1638 | if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { | ||
1639 | DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n", | ||
1640 | params->port); | ||
1641 | return 1; | ||
1642 | } | ||
1643 | |||
1644 | CL45_RD_OVER_CL22(bp, params->port, | ||
1645 | params->phy_addr, | ||
1646 | MDIO_REG_BANK_10G_PARALLEL_DETECT, | ||
1647 | MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, | ||
1648 | &pd_10g); | ||
1649 | |||
1650 | if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { | ||
1651 | DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n", | ||
1652 | params->port); | ||
1653 | return 1; | ||
1654 | } | ||
1655 | return 0; | ||
1656 | } | ||
1624 | 1657 | ||
1625 | static void bnx2x_flow_ctrl_resolve(struct link_params *params, | 1658 | static void bnx2x_flow_ctrl_resolve(struct link_params *params, |
1626 | struct link_vars *vars, | 1659 | struct link_vars *vars, |
@@ -1639,6 +1672,10 @@ static void bnx2x_flow_ctrl_resolve(struct link_params *params, | |||
1639 | (!(vars->phy_flags & PHY_SGMII_FLAG)) && | 1672 | (!(vars->phy_flags & PHY_SGMII_FLAG)) && |
1640 | (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == | 1673 | (XGXS_EXT_PHY_TYPE(params->ext_phy_config) == |
1641 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) { | 1674 | PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) { |
1675 | if (bnx2x_direct_parallel_detect_used(params)) { | ||
1676 | vars->flow_ctrl = params->req_fc_auto_adv; | ||
1677 | return; | ||
1678 | } | ||
1642 | if ((gp_status & | 1679 | if ((gp_status & |
1643 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | | 1680 | (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | |
1644 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == | 1681 | MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == |
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h index b80fde44c85d..4be9bab42f5c 100644 --- a/drivers/net/bnx2x_reg.h +++ b/drivers/net/bnx2x_reg.h | |||
@@ -4920,6 +4920,8 @@ | |||
4920 | 4920 | ||
4921 | 4921 | ||
4922 | #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 | 4922 | #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 |
4923 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 | ||
4924 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 | ||
4923 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 | 4925 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 |
4924 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 | 4926 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 |
4925 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 | 4927 | #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 |
@@ -4944,6 +4946,8 @@ | |||
4944 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 | 4946 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 |
4945 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 | 4947 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 |
4946 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 | 4948 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 |
4949 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 | ||
4950 | #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 | ||
4947 | #define MDIO_SERDES_DIGITAL_MISC1 0x18 | 4951 | #define MDIO_SERDES_DIGITAL_MISC1 0x18 |
4948 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 | 4952 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 |
4949 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 | 4953 | #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 |