aboutsummaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorMauro Carvalho Chehab <mchehab@redhat.com>2011-07-20 21:21:26 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-01-04 19:18:43 -0500
commit6d3d748a6265f156d14029237ffc3dbdc85d7e44 (patch)
tree0f3074eac567ee9b2a7539240e0ae3787c87fe53 /drivers
parentf867695a0f6d7133f5e7ebc9a5ba9be7ccff6c03 (diff)
[media] mt2063: Move data structures to the driver
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/media/common/tuners/mt2063.c529
-rw-r--r--drivers/media/common/tuners/mt2063.h526
2 files changed, 528 insertions, 527 deletions
diff --git a/drivers/media/common/tuners/mt2063.c b/drivers/media/common/tuners/mt2063.c
index 43e543e1efe2..0c4ae7f15c45 100644
--- a/drivers/media/common/tuners/mt2063.c
+++ b/drivers/media/common/tuners/mt2063.c
@@ -12,6 +12,534 @@
12static unsigned int verbose; 12static unsigned int verbose;
13module_param(verbose, int, 0644); 13module_param(verbose, int, 0644);
14 14
15/* Internal structures and types */
16
17#define DVBFE_TUNER_OPEN 99
18#define DVBFE_TUNER_SOFTWARE_SHUTDOWN 100
19#define DVBFE_TUNER_CLEAR_POWER_MASKBITS 101
20
21#define MT2063_ERROR (1 << 31)
22#define MT2063_USER_ERROR (1 << 30)
23
24/* Macro to be used to check for errors */
25#define MT2063_IS_ERROR(s) (((s) >> 30) != 0)
26#define MT2063_NO_ERROR(s) (((s) >> 30) == 0)
27
28#define MT2063_OK (0x00000000)
29
30/* Unknown error */
31#define MT2063_UNKNOWN (0x80000001)
32
33/* Error: Upconverter PLL is not locked */
34#define MT2063_UPC_UNLOCK (0x80000002)
35
36/* Error: Downconverter PLL is not locked */
37#define MT2063_DNC_UNLOCK (0x80000004)
38
39/* Error: Two-wire serial bus communications error */
40#define MT2063_COMM_ERR (0x80000008)
41
42/* Error: Tuner handle passed to function was invalid */
43#define MT2063_INV_HANDLE (0x80000010)
44
45/* Error: Function argument is invalid (out of range) */
46#define MT2063_ARG_RANGE (0x80000020)
47
48/* Error: Function argument (ptr to return value) was NULL */
49#define MT2063_ARG_NULL (0x80000040)
50
51/* Error: Attempt to open more than MT_TUNER_CNT tuners */
52#define MT2063_TUNER_CNT_ERR (0x80000080)
53
54/* Error: Tuner Part Code / Rev Code mismatches expected value */
55#define MT2063_TUNER_ID_ERR (0x80000100)
56
57/* Error: Tuner Initialization failure */
58#define MT2063_TUNER_INIT_ERR (0x80000200)
59
60#define MT2063_TUNER_OPEN_ERR (0x80000400)
61
62/* User-definable fields (see mt_userdef.h) */
63#define MT2063_USER_DEFINED1 (0x00001000)
64#define MT2063_USER_DEFINED2 (0x00002000)
65#define MT2063_USER_DEFINED3 (0x00004000)
66#define MT2063_USER_DEFINED4 (0x00008000)
67#define MT2063_USER_MASK (0x4000f000)
68#define MT2063_USER_SHIFT (12)
69
70/* Info: Mask of bits used for # of LO-related spurs that were avoided during tuning */
71#define MT2063_SPUR_CNT_MASK (0x001f0000)
72#define MT2063_SPUR_SHIFT (16)
73
74/* Info: Tuner timeout waiting for condition */
75#define MT2063_TUNER_TIMEOUT (0x00400000)
76
77/* Info: Unavoidable LO-related spur may be present in the output */
78#define MT2063_SPUR_PRESENT_ERR (0x00800000)
79
80/* Info: Tuner input frequency is out of range */
81#define MT2063_FIN_RANGE (0x01000000)
82
83/* Info: Tuner output frequency is out of range */
84#define MT2063_FOUT_RANGE (0x02000000)
85
86/* Info: Upconverter frequency is out of range (may be reason for MT_UPC_UNLOCK) */
87#define MT2063_UPC_RANGE (0x04000000)
88
89/* Info: Downconverter frequency is out of range (may be reason for MT_DPC_UNLOCK) */
90#define MT2063_DNC_RANGE (0x08000000)
91
92/*
93 * Data Types
94 */
95
96#define MAX_UDATA (4294967295) /* max value storable in u32 */
97
98/*
99 * Define an MTxxxx_CNT macro for each type of tuner that will be built
100 * into your application (e.g., MT2121, MT2060). MT_TUNER_CNT
101 * must be set to the SUM of all of the MTxxxx_CNT macros.
102 *
103 * #define MT2050_CNT (1)
104 * #define MT2060_CNT (1)
105 * #define MT2111_CNT (1)
106 * #define MT2121_CNT (3)
107 */
108
109
110#define MT2063_TUNER_CNT (1) /* total num of MicroTuner tuners */
111#define MT2063_I2C (0xC0)
112
113/*
114 * Constant defining the version of the following structure
115 * and therefore the API for this code.
116 *
117 * When compiling the tuner driver, the preprocessor will
118 * check against this version number to make sure that
119 * it matches the version that the tuner driver knows about.
120 */
121/* Version 010201 => 1.21 */
122#define MT2063_AVOID_SPURS_INFO_VERSION 010201
123
124/* DECT Frequency Avoidance */
125#define MT2063_DECT_AVOID_US_FREQS 0x00000001
126
127#define MT2063_DECT_AVOID_EURO_FREQS 0x00000002
128
129#define MT2063_EXCLUDE_US_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_US_FREQS) != 0)
130
131#define MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_EURO_FREQS) != 0)
132
133enum MT2063_DECT_Avoid_Type {
134 MT2063_NO_DECT_AVOIDANCE = 0, /* Do not create DECT exclusion zones. */
135 MT2063_AVOID_US_DECT = MT2063_DECT_AVOID_US_FREQS, /* Avoid US DECT frequencies. */
136 MT2063_AVOID_EURO_DECT = MT2063_DECT_AVOID_EURO_FREQS, /* Avoid European DECT frequencies. */
137 MT2063_AVOID_BOTH /* Avoid both regions. Not typically used. */
138};
139
140#define MT2063_MAX_ZONES 48
141
142struct MT2063_ExclZone_t;
143
144struct MT2063_ExclZone_t {
145 u32 min_;
146 u32 max_;
147 struct MT2063_ExclZone_t *next_;
148};
149
150/*
151 * Structure of data needed for Spur Avoidance
152 */
153struct MT2063_AvoidSpursData_t {
154 u32 nAS_Algorithm;
155 u32 f_ref;
156 u32 f_in;
157 u32 f_LO1;
158 u32 f_if1_Center;
159 u32 f_if1_Request;
160 u32 f_if1_bw;
161 u32 f_LO2;
162 u32 f_out;
163 u32 f_out_bw;
164 u32 f_LO1_Step;
165 u32 f_LO2_Step;
166 u32 f_LO1_FracN_Avoid;
167 u32 f_LO2_FracN_Avoid;
168 u32 f_zif_bw;
169 u32 f_min_LO_Separation;
170 u32 maxH1;
171 u32 maxH2;
172 enum MT2063_DECT_Avoid_Type avoidDECT;
173 u32 bSpurPresent;
174 u32 bSpurAvoided;
175 u32 nSpursFound;
176 u32 nZones;
177 struct MT2063_ExclZone_t *freeZones;
178 struct MT2063_ExclZone_t *usedZones;
179 struct MT2063_ExclZone_t MT2063_ExclZones[MT2063_MAX_ZONES];
180};
181
182/*
183 * Values returned by the MT2063's on-chip temperature sensor
184 * to be read/written.
185 */
186enum MT2063_Temperature {
187 MT2063_T_0C = 0, /* Temperature approx 0C */
188 MT2063_T_10C, /* Temperature approx 10C */
189 MT2063_T_20C, /* Temperature approx 20C */
190 MT2063_T_30C, /* Temperature approx 30C */
191 MT2063_T_40C, /* Temperature approx 40C */
192 MT2063_T_50C, /* Temperature approx 50C */
193 MT2063_T_60C, /* Temperature approx 60C */
194 MT2063_T_70C, /* Temperature approx 70C */
195 MT2063_T_80C, /* Temperature approx 80C */
196 MT2063_T_90C, /* Temperature approx 90C */
197 MT2063_T_100C, /* Temperature approx 100C */
198 MT2063_T_110C, /* Temperature approx 110C */
199 MT2063_T_120C, /* Temperature approx 120C */
200 MT2063_T_130C, /* Temperature approx 130C */
201 MT2063_T_140C, /* Temperature approx 140C */
202 MT2063_T_150C, /* Temperature approx 150C */
203};
204
205/*
206 * Parameters for selecting GPIO bits
207 */
208enum MT2063_GPIO_Attr {
209 MT2063_GPIO_IN,
210 MT2063_GPIO_DIR,
211 MT2063_GPIO_OUT,
212};
213
214enum MT2063_GPIO_ID {
215 MT2063_GPIO0,
216 MT2063_GPIO1,
217 MT2063_GPIO2,
218};
219
220/*
221 * Parameter for function MT2063_SetExtSRO that specifies the external
222 * SRO drive frequency.
223 *
224 * MT2063_EXT_SRO_OFF is the power-up default value.
225 */
226enum MT2063_Ext_SRO {
227 MT2063_EXT_SRO_OFF, /* External SRO drive off */
228 MT2063_EXT_SRO_BY_4, /* External SRO drive divide by 4 */
229 MT2063_EXT_SRO_BY_2, /* External SRO drive divide by 2 */
230 MT2063_EXT_SRO_BY_1 /* External SRO drive divide by 1 */
231};
232
233/*
234 * Parameter for function MT2063_SetPowerMask that specifies the power down
235 * of various sections of the MT2063.
236 */
237enum MT2063_Mask_Bits {
238 MT2063_REG_SD = 0x0040, /* Shutdown regulator */
239 MT2063_SRO_SD = 0x0020, /* Shutdown SRO */
240 MT2063_AFC_SD = 0x0010, /* Shutdown AFC A/D */
241 MT2063_PD_SD = 0x0002, /* Enable power detector shutdown */
242 MT2063_PDADC_SD = 0x0001, /* Enable power detector A/D shutdown */
243 MT2063_VCO_SD = 0x8000, /* Enable VCO shutdown */
244 MT2063_LTX_SD = 0x4000, /* Enable LTX shutdown */
245 MT2063_LT1_SD = 0x2000, /* Enable LT1 shutdown */
246 MT2063_LNA_SD = 0x1000, /* Enable LNA shutdown */
247 MT2063_UPC_SD = 0x0800, /* Enable upconverter shutdown */
248 MT2063_DNC_SD = 0x0400, /* Enable downconverter shutdown */
249 MT2063_VGA_SD = 0x0200, /* Enable VGA shutdown */
250 MT2063_AMP_SD = 0x0100, /* Enable AMP shutdown */
251 MT2063_ALL_SD = 0xFF73, /* All shutdown bits for this tuner */
252 MT2063_NONE_SD = 0x0000 /* No shutdown bits */
253};
254
255/*
256 * Parameter for function MT2063_GetParam & MT2063_SetParam that
257 * specifies the tuning algorithm parameter to be read/written.
258 */
259enum MT2063_Param {
260 /* tuner address set by MT2063_Open() */
261 MT2063_IC_ADDR,
262
263 /* max number of MT2063 tuners set by MT_TUNER_CNT in mt_userdef.h */
264 MT2063_MAX_OPEN,
265
266 /* current number of open MT2063 tuners set by MT2063_Open() */
267 MT2063_NUM_OPEN,
268
269 /* crystal frequency (default: 16000000 Hz) */
270 MT2063_SRO_FREQ,
271
272 /* min tuning step size (default: 50000 Hz) */
273 MT2063_STEPSIZE,
274
275 /* input center frequency set by MT2063_Tune() */
276 MT2063_INPUT_FREQ,
277
278 /* LO1 Frequency set by MT2063_Tune() */
279 MT2063_LO1_FREQ,
280
281 /* LO1 minimum step size (default: 250000 Hz) */
282 MT2063_LO1_STEPSIZE,
283
284 /* LO1 FracN keep-out region (default: 999999 Hz) */
285 MT2063_LO1_FRACN_AVOID_PARAM,
286
287 /* Current 1st IF in use set by MT2063_Tune() */
288 MT2063_IF1_ACTUAL,
289
290 /* Requested 1st IF set by MT2063_Tune() */
291 MT2063_IF1_REQUEST,
292
293 /* Center of 1st IF SAW filter (default: 1218000000 Hz) */
294 MT2063_IF1_CENTER,
295
296 /* Bandwidth of 1st IF SAW filter (default: 20000000 Hz) */
297 MT2063_IF1_BW,
298
299 /* zero-IF bandwidth (default: 2000000 Hz) */
300 MT2063_ZIF_BW,
301
302 /* LO2 Frequency set by MT2063_Tune() */
303 MT2063_LO2_FREQ,
304
305 /* LO2 minimum step size (default: 50000 Hz) */
306 MT2063_LO2_STEPSIZE,
307
308 /* LO2 FracN keep-out region (default: 374999 Hz) */
309 MT2063_LO2_FRACN_AVOID,
310
311 /* output center frequency set by MT2063_Tune() */
312 MT2063_OUTPUT_FREQ,
313
314 /* output bandwidth set by MT2063_Tune() */
315 MT2063_OUTPUT_BW,
316
317 /* min inter-tuner LO separation (default: 1000000 Hz) */
318 MT2063_LO_SEPARATION,
319
320 /* ID of avoid-spurs algorithm in use compile-time constant */
321 MT2063_AS_ALG,
322
323 /* max # of intra-tuner harmonics (default: 15) */
324 MT2063_MAX_HARM1,
325
326 /* max # of inter-tuner harmonics (default: 7) */
327 MT2063_MAX_HARM2,
328
329 /* # of 1st IF exclusion zones used set by MT2063_Tune() */
330 MT2063_EXCL_ZONES,
331
332 /* # of spurs found/avoided set by MT2063_Tune() */
333 MT2063_NUM_SPURS,
334
335 /* >0 spurs avoided set by MT2063_Tune() */
336 MT2063_SPUR_AVOIDED,
337
338 /* >0 spurs in output (mathematically) set by MT2063_Tune() */
339 MT2063_SPUR_PRESENT,
340
341 /* Receiver Mode for some parameters. 1 is DVB-T */
342 MT2063_RCVR_MODE,
343
344 /* directly set LNA attenuation, parameter is value to set */
345 MT2063_ACLNA,
346
347 /* maximum LNA attenuation, parameter is value to set */
348 MT2063_ACLNA_MAX,
349
350 /* directly set ATN attenuation. Paremeter is value to set. */
351 MT2063_ACRF,
352
353 /* maxium ATN attenuation. Paremeter is value to set. */
354 MT2063_ACRF_MAX,
355
356 /* directly set FIF attenuation. Paremeter is value to set. */
357 MT2063_ACFIF,
358
359 /* maxium FIF attenuation. Paremeter is value to set. */
360 MT2063_ACFIF_MAX,
361
362 /* LNA Rin */
363 MT2063_LNA_RIN,
364
365 /* Power Detector LNA level target */
366 MT2063_LNA_TGT,
367
368 /* Power Detector 1 level */
369 MT2063_PD1,
370
371 /* Power Detector 1 level target */
372 MT2063_PD1_TGT,
373
374 /* Power Detector 2 level */
375 MT2063_PD2,
376
377 /* Power Detector 2 level target */
378 MT2063_PD2_TGT,
379
380 /* Selects, which DNC is activ */
381 MT2063_DNC_OUTPUT_ENABLE,
382
383 /* VGA gain code */
384 MT2063_VGAGC,
385
386 /* VGA bias current */
387 MT2063_VGAOI,
388
389 /* TAGC, determins the speed of the AGC */
390 MT2063_TAGC,
391
392 /* AMP gain code */
393 MT2063_AMPGC,
394
395 /* Control setting to avoid DECT freqs (default: MT_AVOID_BOTH) */
396 MT2063_AVOID_DECT,
397
398 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */
399 MT2063_CTFILT_SW,
400
401 MT2063_EOP /* last entry in enumerated list */
402};
403
404/*
405 * Parameter for selecting tuner mode
406 */
407enum MT2063_RCVR_MODES {
408 MT2063_CABLE_QAM = 0, /* Digital cable */
409 MT2063_CABLE_ANALOG, /* Analog cable */
410 MT2063_OFFAIR_COFDM, /* Digital offair */
411 MT2063_OFFAIR_COFDM_SAWLESS, /* Digital offair without SAW */
412 MT2063_OFFAIR_ANALOG, /* Analog offair */
413 MT2063_OFFAIR_8VSB, /* Analog offair */
414 MT2063_NUM_RCVR_MODES
415};
416
417/*
418 * Possible values for MT2063_DNC_OUTPUT
419 */
420enum MT2063_DNC_Output_Enable {
421 MT2063_DNC_NONE = 0,
422 MT2063_DNC_1,
423 MT2063_DNC_2,
424 MT2063_DNC_BOTH
425};
426
427/*
428** Two-wire serial bus subaddresses of the tuner registers.
429** Also known as the tuner's register addresses.
430*/
431enum MT2063_Register_Offsets {
432 MT2063_REG_PART_REV = 0, /* 0x00: Part/Rev Code */
433 MT2063_REG_LO1CQ_1, /* 0x01: LO1C Queued Byte 1 */
434 MT2063_REG_LO1CQ_2, /* 0x02: LO1C Queued Byte 2 */
435 MT2063_REG_LO2CQ_1, /* 0x03: LO2C Queued Byte 1 */
436 MT2063_REG_LO2CQ_2, /* 0x04: LO2C Queued Byte 2 */
437 MT2063_REG_LO2CQ_3, /* 0x05: LO2C Queued Byte 3 */
438 MT2063_REG_RSVD_06, /* 0x06: Reserved */
439 MT2063_REG_LO_STATUS, /* 0x07: LO Status */
440 MT2063_REG_FIFFC, /* 0x08: FIFF Center */
441 MT2063_REG_CLEARTUNE, /* 0x09: ClearTune Filter */
442 MT2063_REG_ADC_OUT, /* 0x0A: ADC_OUT */
443 MT2063_REG_LO1C_1, /* 0x0B: LO1C Byte 1 */
444 MT2063_REG_LO1C_2, /* 0x0C: LO1C Byte 2 */
445 MT2063_REG_LO2C_1, /* 0x0D: LO2C Byte 1 */
446 MT2063_REG_LO2C_2, /* 0x0E: LO2C Byte 2 */
447 MT2063_REG_LO2C_3, /* 0x0F: LO2C Byte 3 */
448 MT2063_REG_RSVD_10, /* 0x10: Reserved */
449 MT2063_REG_PWR_1, /* 0x11: PWR Byte 1 */
450 MT2063_REG_PWR_2, /* 0x12: PWR Byte 2 */
451 MT2063_REG_TEMP_STATUS, /* 0x13: Temp Status */
452 MT2063_REG_XO_STATUS, /* 0x14: Crystal Status */
453 MT2063_REG_RF_STATUS, /* 0x15: RF Attn Status */
454 MT2063_REG_FIF_STATUS, /* 0x16: FIF Attn Status */
455 MT2063_REG_LNA_OV, /* 0x17: LNA Attn Override */
456 MT2063_REG_RF_OV, /* 0x18: RF Attn Override */
457 MT2063_REG_FIF_OV, /* 0x19: FIF Attn Override */
458 MT2063_REG_LNA_TGT, /* 0x1A: Reserved */
459 MT2063_REG_PD1_TGT, /* 0x1B: Pwr Det 1 Target */
460 MT2063_REG_PD2_TGT, /* 0x1C: Pwr Det 2 Target */
461 MT2063_REG_RSVD_1D, /* 0x1D: Reserved */
462 MT2063_REG_RSVD_1E, /* 0x1E: Reserved */
463 MT2063_REG_RSVD_1F, /* 0x1F: Reserved */
464 MT2063_REG_RSVD_20, /* 0x20: Reserved */
465 MT2063_REG_BYP_CTRL, /* 0x21: Bypass Control */
466 MT2063_REG_RSVD_22, /* 0x22: Reserved */
467 MT2063_REG_RSVD_23, /* 0x23: Reserved */
468 MT2063_REG_RSVD_24, /* 0x24: Reserved */
469 MT2063_REG_RSVD_25, /* 0x25: Reserved */
470 MT2063_REG_RSVD_26, /* 0x26: Reserved */
471 MT2063_REG_RSVD_27, /* 0x27: Reserved */
472 MT2063_REG_FIFF_CTRL, /* 0x28: FIFF Control */
473 MT2063_REG_FIFF_OFFSET, /* 0x29: FIFF Offset */
474 MT2063_REG_CTUNE_CTRL, /* 0x2A: Reserved */
475 MT2063_REG_CTUNE_OV, /* 0x2B: Reserved */
476 MT2063_REG_CTRL_2C, /* 0x2C: Reserved */
477 MT2063_REG_FIFF_CTRL2, /* 0x2D: Fiff Control */
478 MT2063_REG_RSVD_2E, /* 0x2E: Reserved */
479 MT2063_REG_DNC_GAIN, /* 0x2F: DNC Control */
480 MT2063_REG_VGA_GAIN, /* 0x30: VGA Gain Ctrl */
481 MT2063_REG_RSVD_31, /* 0x31: Reserved */
482 MT2063_REG_TEMP_SEL, /* 0x32: Temperature Selection */
483 MT2063_REG_RSVD_33, /* 0x33: Reserved */
484 MT2063_REG_RSVD_34, /* 0x34: Reserved */
485 MT2063_REG_RSVD_35, /* 0x35: Reserved */
486 MT2063_REG_RSVD_36, /* 0x36: Reserved */
487 MT2063_REG_RSVD_37, /* 0x37: Reserved */
488 MT2063_REG_RSVD_38, /* 0x38: Reserved */
489 MT2063_REG_RSVD_39, /* 0x39: Reserved */
490 MT2063_REG_RSVD_3A, /* 0x3A: Reserved */
491 MT2063_REG_RSVD_3B, /* 0x3B: Reserved */
492 MT2063_REG_RSVD_3C, /* 0x3C: Reserved */
493 MT2063_REG_END_REGS
494};
495
496struct MT2063_Info_t {
497 void *handle;
498 void *hUserData;
499 u32 address;
500 u32 version;
501 u32 tuner_id;
502 struct MT2063_AvoidSpursData_t AS_Data;
503 u32 f_IF1_actual;
504 u32 rcvr_mode;
505 u32 ctfilt_sw;
506 u32 CTFiltMax[31];
507 u32 num_regs;
508 u8 reg[MT2063_REG_END_REGS];
509};
510typedef struct MT2063_Info_t *pMT2063_Info_t;
511
512enum MTTune_atv_standard {
513 MTTUNEA_UNKNOWN = 0,
514 MTTUNEA_PAL_B,
515 MTTUNEA_PAL_G,
516 MTTUNEA_PAL_I,
517 MTTUNEA_PAL_L,
518 MTTUNEA_PAL_MN,
519 MTTUNEA_PAL_DK,
520 MTTUNEA_DIGITAL,
521 MTTUNEA_FMRADIO,
522 MTTUNEA_DVBC,
523 MTTUNEA_DVBT
524};
525
526
527struct mt2063_state {
528 struct i2c_adapter *i2c;
529
530 const struct mt2063_config *config;
531 struct dvb_tuner_ops ops;
532 struct dvb_frontend *frontend;
533 struct tuner_state status;
534 struct MT2063_Info_t *MT2063_ht;
535 bool MT2063_init;
536
537 enum MTTune_atv_standard tv_type;
538 u32 frequency;
539 u32 srate;
540 u32 bandwidth;
541 u32 reference;
542};
15 543
16/* Prototypes */ 544/* Prototypes */
17static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info, 545static void MT2063_AddExclZone(struct MT2063_AvoidSpursData_t *pAS_Info,
@@ -150,7 +678,6 @@ unsigned int tuner_MT2063_ClearPowerMaskBits(struct dvb_frontend *fe)
150 678
151/*****************/ 679/*****************/
152 680
153
154//i2c operation 681//i2c operation
155static int mt2063_writeregs(struct mt2063_state *state, u8 reg1, 682static int mt2063_writeregs(struct mt2063_state *state, u8 reg1,
156 u8 * data, int len) 683 u8 * data, int len)
diff --git a/drivers/media/common/tuners/mt2063.h b/drivers/media/common/tuners/mt2063.h
index 5dece2c314ce..27273bfef5d6 100644
--- a/drivers/media/common/tuners/mt2063.h
+++ b/drivers/media/common/tuners/mt2063.h
@@ -3,537 +3,11 @@
3 3
4#include "dvb_frontend.h" 4#include "dvb_frontend.h"
5 5
6#define DVBFE_TUNER_OPEN 99
7#define DVBFE_TUNER_SOFTWARE_SHUTDOWN 100
8#define DVBFE_TUNER_CLEAR_POWER_MASKBITS 101
9
10#define MT2063_ERROR (1 << 31)
11#define MT2063_USER_ERROR (1 << 30)
12
13/* Macro to be used to check for errors */
14#define MT2063_IS_ERROR(s) (((s) >> 30) != 0)
15#define MT2063_NO_ERROR(s) (((s) >> 30) == 0)
16
17#define MT2063_OK (0x00000000)
18
19/* Unknown error */
20#define MT2063_UNKNOWN (0x80000001)
21
22/* Error: Upconverter PLL is not locked */
23#define MT2063_UPC_UNLOCK (0x80000002)
24
25/* Error: Downconverter PLL is not locked */
26#define MT2063_DNC_UNLOCK (0x80000004)
27
28/* Error: Two-wire serial bus communications error */
29#define MT2063_COMM_ERR (0x80000008)
30
31/* Error: Tuner handle passed to function was invalid */
32#define MT2063_INV_HANDLE (0x80000010)
33
34/* Error: Function argument is invalid (out of range) */
35#define MT2063_ARG_RANGE (0x80000020)
36
37/* Error: Function argument (ptr to return value) was NULL */
38#define MT2063_ARG_NULL (0x80000040)
39
40/* Error: Attempt to open more than MT_TUNER_CNT tuners */
41#define MT2063_TUNER_CNT_ERR (0x80000080)
42
43/* Error: Tuner Part Code / Rev Code mismatches expected value */
44#define MT2063_TUNER_ID_ERR (0x80000100)
45
46/* Error: Tuner Initialization failure */
47#define MT2063_TUNER_INIT_ERR (0x80000200)
48
49#define MT2063_TUNER_OPEN_ERR (0x80000400)
50
51/* User-definable fields (see mt_userdef.h) */
52#define MT2063_USER_DEFINED1 (0x00001000)
53#define MT2063_USER_DEFINED2 (0x00002000)
54#define MT2063_USER_DEFINED3 (0x00004000)
55#define MT2063_USER_DEFINED4 (0x00008000)
56#define MT2063_USER_MASK (0x4000f000)
57#define MT2063_USER_SHIFT (12)
58
59/* Info: Mask of bits used for # of LO-related spurs that were avoided during tuning */
60#define MT2063_SPUR_CNT_MASK (0x001f0000)
61#define MT2063_SPUR_SHIFT (16)
62
63/* Info: Tuner timeout waiting for condition */
64#define MT2063_TUNER_TIMEOUT (0x00400000)
65
66/* Info: Unavoidable LO-related spur may be present in the output */
67#define MT2063_SPUR_PRESENT_ERR (0x00800000)
68
69/* Info: Tuner input frequency is out of range */
70#define MT2063_FIN_RANGE (0x01000000)
71
72/* Info: Tuner output frequency is out of range */
73#define MT2063_FOUT_RANGE (0x02000000)
74
75/* Info: Upconverter frequency is out of range (may be reason for MT_UPC_UNLOCK) */
76#define MT2063_UPC_RANGE (0x04000000)
77
78/* Info: Downconverter frequency is out of range (may be reason for MT_DPC_UNLOCK) */
79#define MT2063_DNC_RANGE (0x08000000)
80
81/*
82 * Data Types
83 */
84
85#define MAX_UDATA (4294967295) /* max value storable in u32 */
86
87/*
88 * Define an MTxxxx_CNT macro for each type of tuner that will be built
89 * into your application (e.g., MT2121, MT2060). MT_TUNER_CNT
90 * must be set to the SUM of all of the MTxxxx_CNT macros.
91 *
92 * #define MT2050_CNT (1)
93 * #define MT2060_CNT (1)
94 * #define MT2111_CNT (1)
95 * #define MT2121_CNT (3)
96 */
97
98
99#define MT2063_TUNER_CNT (1) /* total num of MicroTuner tuners */
100#define MT2063_I2C (0xC0)
101
102/*
103 * Constant defining the version of the following structure
104 * and therefore the API for this code.
105 *
106 * When compiling the tuner driver, the preprocessor will
107 * check against this version number to make sure that
108 * it matches the version that the tuner driver knows about.
109 */
110/* Version 010201 => 1.21 */
111#define MT2063_AVOID_SPURS_INFO_VERSION 010201
112
113/* DECT Frequency Avoidance */
114#define MT2063_DECT_AVOID_US_FREQS 0x00000001
115
116#define MT2063_DECT_AVOID_EURO_FREQS 0x00000002
117
118#define MT2063_EXCLUDE_US_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_US_FREQS) != 0)
119
120#define MT2063_EXCLUDE_EURO_DECT_FREQUENCIES(s) (((s) & MT2063_DECT_AVOID_EURO_FREQS) != 0)
121
122enum MT2063_DECT_Avoid_Type {
123 MT2063_NO_DECT_AVOIDANCE = 0, /* Do not create DECT exclusion zones. */
124 MT2063_AVOID_US_DECT = MT2063_DECT_AVOID_US_FREQS, /* Avoid US DECT frequencies. */
125 MT2063_AVOID_EURO_DECT = MT2063_DECT_AVOID_EURO_FREQS, /* Avoid European DECT frequencies. */
126 MT2063_AVOID_BOTH /* Avoid both regions. Not typically used. */
127};
128
129#define MT2063_MAX_ZONES 48
130
131struct MT2063_ExclZone_t;
132
133struct MT2063_ExclZone_t {
134 u32 min_;
135 u32 max_;
136 struct MT2063_ExclZone_t *next_;
137};
138
139/*
140 * Structure of data needed for Spur Avoidance
141 */
142struct MT2063_AvoidSpursData_t {
143 u32 nAS_Algorithm;
144 u32 f_ref;
145 u32 f_in;
146 u32 f_LO1;
147 u32 f_if1_Center;
148 u32 f_if1_Request;
149 u32 f_if1_bw;
150 u32 f_LO2;
151 u32 f_out;
152 u32 f_out_bw;
153 u32 f_LO1_Step;
154 u32 f_LO2_Step;
155 u32 f_LO1_FracN_Avoid;
156 u32 f_LO2_FracN_Avoid;
157 u32 f_zif_bw;
158 u32 f_min_LO_Separation;
159 u32 maxH1;
160 u32 maxH2;
161 enum MT2063_DECT_Avoid_Type avoidDECT;
162 u32 bSpurPresent;
163 u32 bSpurAvoided;
164 u32 nSpursFound;
165 u32 nZones;
166 struct MT2063_ExclZone_t *freeZones;
167 struct MT2063_ExclZone_t *usedZones;
168 struct MT2063_ExclZone_t MT2063_ExclZones[MT2063_MAX_ZONES];
169};
170
171/*
172 * Values returned by the MT2063's on-chip temperature sensor
173 * to be read/written.
174 */
175enum MT2063_Temperature {
176 MT2063_T_0C = 0, /* Temperature approx 0C */
177 MT2063_T_10C, /* Temperature approx 10C */
178 MT2063_T_20C, /* Temperature approx 20C */
179 MT2063_T_30C, /* Temperature approx 30C */
180 MT2063_T_40C, /* Temperature approx 40C */
181 MT2063_T_50C, /* Temperature approx 50C */
182 MT2063_T_60C, /* Temperature approx 60C */
183 MT2063_T_70C, /* Temperature approx 70C */
184 MT2063_T_80C, /* Temperature approx 80C */
185 MT2063_T_90C, /* Temperature approx 90C */
186 MT2063_T_100C, /* Temperature approx 100C */
187 MT2063_T_110C, /* Temperature approx 110C */
188 MT2063_T_120C, /* Temperature approx 120C */
189 MT2063_T_130C, /* Temperature approx 130C */
190 MT2063_T_140C, /* Temperature approx 140C */
191 MT2063_T_150C, /* Temperature approx 150C */
192};
193
194/*
195 * Parameters for selecting GPIO bits
196 */
197enum MT2063_GPIO_Attr {
198 MT2063_GPIO_IN,
199 MT2063_GPIO_DIR,
200 MT2063_GPIO_OUT,
201};
202
203enum MT2063_GPIO_ID {
204 MT2063_GPIO0,
205 MT2063_GPIO1,
206 MT2063_GPIO2,
207};
208
209/*
210 * Parameter for function MT2063_SetExtSRO that specifies the external
211 * SRO drive frequency.
212 *
213 * MT2063_EXT_SRO_OFF is the power-up default value.
214 */
215enum MT2063_Ext_SRO {
216 MT2063_EXT_SRO_OFF, /* External SRO drive off */
217 MT2063_EXT_SRO_BY_4, /* External SRO drive divide by 4 */
218 MT2063_EXT_SRO_BY_2, /* External SRO drive divide by 2 */
219 MT2063_EXT_SRO_BY_1 /* External SRO drive divide by 1 */
220};
221
222/*
223 * Parameter for function MT2063_SetPowerMask that specifies the power down
224 * of various sections of the MT2063.
225 */
226enum MT2063_Mask_Bits {
227 MT2063_REG_SD = 0x0040, /* Shutdown regulator */
228 MT2063_SRO_SD = 0x0020, /* Shutdown SRO */
229 MT2063_AFC_SD = 0x0010, /* Shutdown AFC A/D */
230 MT2063_PD_SD = 0x0002, /* Enable power detector shutdown */
231 MT2063_PDADC_SD = 0x0001, /* Enable power detector A/D shutdown */
232 MT2063_VCO_SD = 0x8000, /* Enable VCO shutdown */
233 MT2063_LTX_SD = 0x4000, /* Enable LTX shutdown */
234 MT2063_LT1_SD = 0x2000, /* Enable LT1 shutdown */
235 MT2063_LNA_SD = 0x1000, /* Enable LNA shutdown */
236 MT2063_UPC_SD = 0x0800, /* Enable upconverter shutdown */
237 MT2063_DNC_SD = 0x0400, /* Enable downconverter shutdown */
238 MT2063_VGA_SD = 0x0200, /* Enable VGA shutdown */
239 MT2063_AMP_SD = 0x0100, /* Enable AMP shutdown */
240 MT2063_ALL_SD = 0xFF73, /* All shutdown bits for this tuner */
241 MT2063_NONE_SD = 0x0000 /* No shutdown bits */
242};
243
244/*
245 * Parameter for function MT2063_GetParam & MT2063_SetParam that
246 * specifies the tuning algorithm parameter to be read/written.
247 */
248enum MT2063_Param {
249 /* tuner address set by MT2063_Open() */
250 MT2063_IC_ADDR,
251
252 /* max number of MT2063 tuners set by MT_TUNER_CNT in mt_userdef.h */
253 MT2063_MAX_OPEN,
254
255 /* current number of open MT2063 tuners set by MT2063_Open() */
256 MT2063_NUM_OPEN,
257
258 /* crystal frequency (default: 16000000 Hz) */
259 MT2063_SRO_FREQ,
260
261 /* min tuning step size (default: 50000 Hz) */
262 MT2063_STEPSIZE,
263
264 /* input center frequency set by MT2063_Tune() */
265 MT2063_INPUT_FREQ,
266
267 /* LO1 Frequency set by MT2063_Tune() */
268 MT2063_LO1_FREQ,
269
270 /* LO1 minimum step size (default: 250000 Hz) */
271 MT2063_LO1_STEPSIZE,
272
273 /* LO1 FracN keep-out region (default: 999999 Hz) */
274 MT2063_LO1_FRACN_AVOID_PARAM,
275
276 /* Current 1st IF in use set by MT2063_Tune() */
277 MT2063_IF1_ACTUAL,
278
279 /* Requested 1st IF set by MT2063_Tune() */
280 MT2063_IF1_REQUEST,
281
282 /* Center of 1st IF SAW filter (default: 1218000000 Hz) */
283 MT2063_IF1_CENTER,
284
285 /* Bandwidth of 1st IF SAW filter (default: 20000000 Hz) */
286 MT2063_IF1_BW,
287
288 /* zero-IF bandwidth (default: 2000000 Hz) */
289 MT2063_ZIF_BW,
290
291 /* LO2 Frequency set by MT2063_Tune() */
292 MT2063_LO2_FREQ,
293
294 /* LO2 minimum step size (default: 50000 Hz) */
295 MT2063_LO2_STEPSIZE,
296
297 /* LO2 FracN keep-out region (default: 374999 Hz) */
298 MT2063_LO2_FRACN_AVOID,
299
300 /* output center frequency set by MT2063_Tune() */
301 MT2063_OUTPUT_FREQ,
302
303 /* output bandwidth set by MT2063_Tune() */
304 MT2063_OUTPUT_BW,
305
306 /* min inter-tuner LO separation (default: 1000000 Hz) */
307 MT2063_LO_SEPARATION,
308
309 /* ID of avoid-spurs algorithm in use compile-time constant */
310 MT2063_AS_ALG,
311
312 /* max # of intra-tuner harmonics (default: 15) */
313 MT2063_MAX_HARM1,
314
315 /* max # of inter-tuner harmonics (default: 7) */
316 MT2063_MAX_HARM2,
317
318 /* # of 1st IF exclusion zones used set by MT2063_Tune() */
319 MT2063_EXCL_ZONES,
320
321 /* # of spurs found/avoided set by MT2063_Tune() */
322 MT2063_NUM_SPURS,
323
324 /* >0 spurs avoided set by MT2063_Tune() */
325 MT2063_SPUR_AVOIDED,
326
327 /* >0 spurs in output (mathematically) set by MT2063_Tune() */
328 MT2063_SPUR_PRESENT,
329
330 /* Receiver Mode for some parameters. 1 is DVB-T */
331 MT2063_RCVR_MODE,
332
333 /* directly set LNA attenuation, parameter is value to set */
334 MT2063_ACLNA,
335
336 /* maximum LNA attenuation, parameter is value to set */
337 MT2063_ACLNA_MAX,
338
339 /* directly set ATN attenuation. Paremeter is value to set. */
340 MT2063_ACRF,
341
342 /* maxium ATN attenuation. Paremeter is value to set. */
343 MT2063_ACRF_MAX,
344
345 /* directly set FIF attenuation. Paremeter is value to set. */
346 MT2063_ACFIF,
347
348 /* maxium FIF attenuation. Paremeter is value to set. */
349 MT2063_ACFIF_MAX,
350
351 /* LNA Rin */
352 MT2063_LNA_RIN,
353
354 /* Power Detector LNA level target */
355 MT2063_LNA_TGT,
356
357 /* Power Detector 1 level */
358 MT2063_PD1,
359
360 /* Power Detector 1 level target */
361 MT2063_PD1_TGT,
362
363 /* Power Detector 2 level */
364 MT2063_PD2,
365
366 /* Power Detector 2 level target */
367 MT2063_PD2_TGT,
368
369 /* Selects, which DNC is activ */
370 MT2063_DNC_OUTPUT_ENABLE,
371
372 /* VGA gain code */
373 MT2063_VGAGC,
374
375 /* VGA bias current */
376 MT2063_VGAOI,
377
378 /* TAGC, determins the speed of the AGC */
379 MT2063_TAGC,
380
381 /* AMP gain code */
382 MT2063_AMPGC,
383
384 /* Control setting to avoid DECT freqs (default: MT_AVOID_BOTH) */
385 MT2063_AVOID_DECT,
386
387 /* Cleartune filter selection: 0 - by IC (default), 1 - by software */
388 MT2063_CTFILT_SW,
389
390 MT2063_EOP /* last entry in enumerated list */
391};
392
393/*
394 * Parameter for selecting tuner mode
395 */
396enum MT2063_RCVR_MODES {
397 MT2063_CABLE_QAM = 0, /* Digital cable */
398 MT2063_CABLE_ANALOG, /* Analog cable */
399 MT2063_OFFAIR_COFDM, /* Digital offair */
400 MT2063_OFFAIR_COFDM_SAWLESS, /* Digital offair without SAW */
401 MT2063_OFFAIR_ANALOG, /* Analog offair */
402 MT2063_OFFAIR_8VSB, /* Analog offair */
403 MT2063_NUM_RCVR_MODES
404};
405
406/*
407 * Possible values for MT2063_DNC_OUTPUT
408 */
409enum MT2063_DNC_Output_Enable {
410 MT2063_DNC_NONE = 0,
411 MT2063_DNC_1,
412 MT2063_DNC_2,
413 MT2063_DNC_BOTH
414};
415
416/*
417** Two-wire serial bus subaddresses of the tuner registers.
418** Also known as the tuner's register addresses.
419*/
420enum MT2063_Register_Offsets {
421 MT2063_REG_PART_REV = 0, /* 0x00: Part/Rev Code */
422 MT2063_REG_LO1CQ_1, /* 0x01: LO1C Queued Byte 1 */
423 MT2063_REG_LO1CQ_2, /* 0x02: LO1C Queued Byte 2 */
424 MT2063_REG_LO2CQ_1, /* 0x03: LO2C Queued Byte 1 */
425 MT2063_REG_LO2CQ_2, /* 0x04: LO2C Queued Byte 2 */
426 MT2063_REG_LO2CQ_3, /* 0x05: LO2C Queued Byte 3 */
427 MT2063_REG_RSVD_06, /* 0x06: Reserved */
428 MT2063_REG_LO_STATUS, /* 0x07: LO Status */
429 MT2063_REG_FIFFC, /* 0x08: FIFF Center */
430 MT2063_REG_CLEARTUNE, /* 0x09: ClearTune Filter */
431 MT2063_REG_ADC_OUT, /* 0x0A: ADC_OUT */
432 MT2063_REG_LO1C_1, /* 0x0B: LO1C Byte 1 */
433 MT2063_REG_LO1C_2, /* 0x0C: LO1C Byte 2 */
434 MT2063_REG_LO2C_1, /* 0x0D: LO2C Byte 1 */
435 MT2063_REG_LO2C_2, /* 0x0E: LO2C Byte 2 */
436 MT2063_REG_LO2C_3, /* 0x0F: LO2C Byte 3 */
437 MT2063_REG_RSVD_10, /* 0x10: Reserved */
438 MT2063_REG_PWR_1, /* 0x11: PWR Byte 1 */
439 MT2063_REG_PWR_2, /* 0x12: PWR Byte 2 */
440 MT2063_REG_TEMP_STATUS, /* 0x13: Temp Status */
441 MT2063_REG_XO_STATUS, /* 0x14: Crystal Status */
442 MT2063_REG_RF_STATUS, /* 0x15: RF Attn Status */
443 MT2063_REG_FIF_STATUS, /* 0x16: FIF Attn Status */
444 MT2063_REG_LNA_OV, /* 0x17: LNA Attn Override */
445 MT2063_REG_RF_OV, /* 0x18: RF Attn Override */
446 MT2063_REG_FIF_OV, /* 0x19: FIF Attn Override */
447 MT2063_REG_LNA_TGT, /* 0x1A: Reserved */
448 MT2063_REG_PD1_TGT, /* 0x1B: Pwr Det 1 Target */
449 MT2063_REG_PD2_TGT, /* 0x1C: Pwr Det 2 Target */
450 MT2063_REG_RSVD_1D, /* 0x1D: Reserved */
451 MT2063_REG_RSVD_1E, /* 0x1E: Reserved */
452 MT2063_REG_RSVD_1F, /* 0x1F: Reserved */
453 MT2063_REG_RSVD_20, /* 0x20: Reserved */
454 MT2063_REG_BYP_CTRL, /* 0x21: Bypass Control */
455 MT2063_REG_RSVD_22, /* 0x22: Reserved */
456 MT2063_REG_RSVD_23, /* 0x23: Reserved */
457 MT2063_REG_RSVD_24, /* 0x24: Reserved */
458 MT2063_REG_RSVD_25, /* 0x25: Reserved */
459 MT2063_REG_RSVD_26, /* 0x26: Reserved */
460 MT2063_REG_RSVD_27, /* 0x27: Reserved */
461 MT2063_REG_FIFF_CTRL, /* 0x28: FIFF Control */
462 MT2063_REG_FIFF_OFFSET, /* 0x29: FIFF Offset */
463 MT2063_REG_CTUNE_CTRL, /* 0x2A: Reserved */
464 MT2063_REG_CTUNE_OV, /* 0x2B: Reserved */
465 MT2063_REG_CTRL_2C, /* 0x2C: Reserved */
466 MT2063_REG_FIFF_CTRL2, /* 0x2D: Fiff Control */
467 MT2063_REG_RSVD_2E, /* 0x2E: Reserved */
468 MT2063_REG_DNC_GAIN, /* 0x2F: DNC Control */
469 MT2063_REG_VGA_GAIN, /* 0x30: VGA Gain Ctrl */
470 MT2063_REG_RSVD_31, /* 0x31: Reserved */
471 MT2063_REG_TEMP_SEL, /* 0x32: Temperature Selection */
472 MT2063_REG_RSVD_33, /* 0x33: Reserved */
473 MT2063_REG_RSVD_34, /* 0x34: Reserved */
474 MT2063_REG_RSVD_35, /* 0x35: Reserved */
475 MT2063_REG_RSVD_36, /* 0x36: Reserved */
476 MT2063_REG_RSVD_37, /* 0x37: Reserved */
477 MT2063_REG_RSVD_38, /* 0x38: Reserved */
478 MT2063_REG_RSVD_39, /* 0x39: Reserved */
479 MT2063_REG_RSVD_3A, /* 0x3A: Reserved */
480 MT2063_REG_RSVD_3B, /* 0x3B: Reserved */
481 MT2063_REG_RSVD_3C, /* 0x3C: Reserved */
482 MT2063_REG_END_REGS
483};
484
485struct MT2063_Info_t {
486 void *handle;
487 void *hUserData;
488 u32 address;
489 u32 version;
490 u32 tuner_id;
491 struct MT2063_AvoidSpursData_t AS_Data;
492 u32 f_IF1_actual;
493 u32 rcvr_mode;
494 u32 ctfilt_sw;
495 u32 CTFiltMax[31];
496 u32 num_regs;
497 u8 reg[MT2063_REG_END_REGS];
498};
499typedef struct MT2063_Info_t *pMT2063_Info_t;
500
501enum MTTune_atv_standard {
502 MTTUNEA_UNKNOWN = 0,
503 MTTUNEA_PAL_B,
504 MTTUNEA_PAL_G,
505 MTTUNEA_PAL_I,
506 MTTUNEA_PAL_L,
507 MTTUNEA_PAL_MN,
508 MTTUNEA_PAL_DK,
509 MTTUNEA_DIGITAL,
510 MTTUNEA_FMRADIO,
511 MTTUNEA_DVBC,
512 MTTUNEA_DVBT
513};
514
515struct mt2063_config { 6struct mt2063_config {
516 u8 tuner_address; 7 u8 tuner_address;
517 u32 refclock; 8 u32 refclock;
518}; 9};
519 10
520struct mt2063_state {
521 struct i2c_adapter *i2c;
522
523 const struct mt2063_config *config;
524 struct dvb_tuner_ops ops;
525 struct dvb_frontend *frontend;
526 struct tuner_state status;
527 struct MT2063_Info_t *MT2063_ht;
528 bool MT2063_init;
529
530 enum MTTune_atv_standard tv_type;
531 u32 frequency;
532 u32 srate;
533 u32 bandwidth;
534 u32 reference;
535};
536
537#if defined(CONFIG_MEDIA_TUNER_MT2063) || (defined(CONFIG_MEDIA_TUNER_MT2063_MODULE) && defined(MODULE)) 11#if defined(CONFIG_MEDIA_TUNER_MT2063) || (defined(CONFIG_MEDIA_TUNER_MT2063_MODULE) && defined(MODULE))
538struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe, 12struct dvb_frontend *mt2063_attach(struct dvb_frontend *fe,
539 struct mt2063_config *config, 13 struct mt2063_config *config,
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 11:40:42 -0500